1996_Cypress_Data_Communications_Data_Book 1996 Cypress Data Communications Book
User Manual: 1996_Cypress_Data_Communications_Data_Book
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ATM
Ethernet
Fibre
Channel
FIFOs
Dual-Ports
Clocks
1996
Data Communications
Data Book
Cypress Semiconductor is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor, 3901 North First St., San Jose, CA 95134 (408) 943-2600
Telex: 821032 CYPRESS SNJ UD, TWX: 910 997 0753, FAX: (408) 943-2741
Web Address: http://www.cypress.com
How To Use This Book
Overall Organization
Key to Waveform Diagrams
This book has been organized by product type, beginning with Product Information. The products are
next, starting with SRAMs, then Modules, Non-Volatile Memories, FIFOs, Dual-Ports, Data Communications, Bus Interface Products, FCT Logic, Timing Technology Products, and PC Chip Sets. A section
containing military information is next, followed by
Quality and Reliability aspects, then Thermal Data
and Packages. Within each section, data sheets are arranged in order of part number.
Recommended Search Paths
To search by:
Use:
Product line
Table of Contents or flip
through the book using the
tabs on the right-hand pages.
Size
The Product Selector Guide
in section 1.
Numeric part number Numeric Device Index following the Table of Contents. The book is also arranged in order of part
number.
Rising edge of signal will
occur during this time.
=
Falling edge of signal will
occur during this time.
Signal may transition
during this time (don't
care condition).
Signal changes from highimpedance state to valid
logic level during this time.
Signal changes from valid
logic level to high-impedance
state during this time.
Other manufacturer's The Cross Reference Guide
part number
in section 1.
Military part number
The Military Selector Guide
in section 12.
© Cypress Semiconductor Corporation, 1996. The Infonnation contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does It conveyor Imply any license under patent orother rights. Cypress Semiconductor does not authorize Its products for use as critical components in life-support systems where a malfunction or failure of the product may reasonably be expected to result in significant
inJury to the user. The inclusion of Cypress Semiconductor products in life-support systems applications implies that the manufacturer assumes all risk of such use and in so dOing indemnifies
Cypress Semiconductor against all damages.
Table of Contents
Page Number
Table of Contents
General Product Information
Page Number
Cypress Semiconductor Background ......................................................................... 1-1
DataCom Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-4
Ordering Information ..................................................................................... 1-5
Product Selector Guide ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1- 6
Cypress Semiconductor Bulletin Board System (BBS) Announcement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-13
Ethernet
Page Number
Device Number
CY7C971
CY7B8392
CY7B4663
Description
100BASE-T4/l0BASE-T Fast Ethernet ltansceiver (CAT 3) . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
Ethernet Coax Transceiver Interface ............................................ 2-24
Integrated 10BASE-FL Ethernet ltansceiver ..................................... 2-31
Application Notes
CY7B8392
CY7C971
CY7C971
CY7C971/CY7C388P
Low Power Ethernet Coaxial Transceiver Application ..............................
100BASE-T4/lOBASE-T Ethernet Transceiver Application ..........................
100BASE-T4 /lOBASE-T Ethernet PCI Network Adapter ...........................
100BASE-T4 Ethernet Repeater ................................................
2-40
2-51
2-55
2-72
Page Number
ATMs
Device Number
CY7B951
CY7B952
CY7B955
Description
Local Area Network ATM ltansceiver ............................................ 3-1
SST" SONET/SDH Serial Transceiver ........................................... 3-9
ATM SONET/SDH ltansceiver ................................................ 3 -16
Application Notes
CY7B951
Interfacing with the SST"
Fibre Channel/ESCON'"
Device Number
CY7B923/CY7B933
CY101E383
CY9266-T/C/F
Application Notes
CY7B923/CY7B933
CY7B923/CY7B933
CY7B923/CY7B933
CY7B923/CY7B933
CY7B923/CY7B933
FIFOs
Device Number
CY7C408NCY7C409A
CY7C419/21/25/29/33
CY7C42Xl
CY7C42X5
CY7C4255/65
CY7C4261/71
3-17
Page Number
Description
HOTLink" ltansmitterlReceiver ................................................ 4-1
ECL/TTL/ECL Translator and High-Speed Bus Driver ............................. 4-28
HOTLink'M Evaluation Board ................................................. 4-34
Frequently Asked Questions about HOTLink'M ................................... 4-36
Frequently Asked Questions about HOTLink" Evaluation
Boards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-45
Serializing High Speed Parallel Buses to Extend Their Operational
Length ..................................................................... 4-50
Drive ESCON" With HOTLink" .............................................. 4-77
Replace Your TAXI -125 and TAXI -175 ....................................... 4-110
Page Number
Description
64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO ................................... 5-1
256 x 9, 512 x 9, lK x 9, 2K x 9, 4K x 9 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -15
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFO .................................. 5-37
64/256/512/1K/2K/4K/x 18 Synchronous FIFO .................................... 5-57
8K/16Kx 18 Synchronous FIFO ................................................ 5-77
16K/32K Synchronous FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -94
Table of Contents
FIFOs (continued)
CY7C439
CY7C441/43
CY7C455/56/57
CY7C460/62/64
CY7C470m/74
Dual Ports
Device Number
CY7C130/31/40/41
CY7B131/41
CY7C132/136/142/146
CY7C133/CY7C143
CY7B134/135/1342
CY7B136/CY7B146
CY7B138/CY7B139
CY7B144/145
CY7COO6/016
CY7C024/0241/025/0251
Timing Technology
Device Number
CY7B991/CY7B992
CY7B9910/CY7B9920
Quality
Page Number
Bidirectional 2K x 9 FIFO .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
512 x 9 Cascadable Clocked and 2K x 9 Cascadable Clocked
FIFO with Programmable Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFO
with Programmable Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Cascadable 8Kx 9 FIFO/Cascadable 16Kx 9 FlFO/Cascadable 32Kx 9 FIFO .........
8Kx9 FIFO, 16Kx 9 FIFO/32Kx 9 FIFO with Programmable Flags ................
5 -109
5 -138
5-161
5-181
5-194
Page Number
Description
1Kx8 Dual-Port Static RAM ................................................... 6-1
1Kx8 Dual-Port Static RAM .................................................. 6-14
2K x 8 Dual-Port Static RAM
6-27
2K x 16 Dual-Port Static RAM ................................................. 6-40
4Kx8 Dual-Port Static RAMs and 4Kx 8 Dual-Port Static RAM with Semaphores ..... 6-51
2K x 8 Dual-Port Static RAM .................................................. 6-64
4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-77
8K x 8/9 Dual-Port Static RAMwith Sem, Int, Busy ................................ 6-93
16Kx 8/9 Dual-Port Static RAM with Sem, Int, Busy .............................. 6-111
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy. . . . . . . . . . . . . . .. 6-128
Page Number
Description
Programmable Skew Clock Buffer (PSCB) ........................................ 7-1
Low Skew Clock Buffer ....................................................... 7-13
Page Number
Quality, Reliability, and Process Flows ....................................................................... 8-1
Package Diagrams
Page Number
Thin Quad Flat Packs ...••••..•.••••..•••.•••...••••••...••••••••••••••.•••..•••.•••••.•.•.•••••••.•••..••
32-Lead Plastic Thin Quad Flat Pack (TQFP) A32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64-Pin Thin Quad Flat Pack A64 ............................................................................
64-Lead Thin Plastic Quad Flat Pack A65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
80-Pin Thin Plastic Quad Flat Pack A80 ......................................................................
lOO-Pin Plastic Thin Quad Flat Pack (TQFP) AlOO ............................................................
9-1
9-1
9-2
9-3
9- 3
9-4
Ceramic Dual-In-Line Packages •••.•..•••.••••.•••••...•••••••....•••••••••••••••••••••••••..•••••••.•.••••.
16-Lead (300-Mil) CerDIP D2 MIL-STD-1835 D-2 Config. A .................................................
28-Lead (600-Mil) CerDIP D16 MIL-STD-1835 D-lO Config. A ............................................. "
28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D-15 Config. A ...............................................
32-Lead (300-Mil) CerDIP D32 ........................................................................... ..
28-Lead (600-Mil) Sidebraze DIP D43 .......................................................................
9-5
9-5
9-5
9-5
9-6
9-6
Plastic Leaded Chip Carriers ..•••.••.••••••••.••.••••..•••••••..••••.•.•••..•••••••••••.•••••••.•••••••••••
28-Lead Plastic Leaded Chip Carrier J64 .....................................................................
32-Lead Plastic Leaded Chip Carrier J65 .....................................................................
52-Lead Plastic Leaded Chip Carrier J69 .....................................................................
68-Lead Plastic Leaded Chip Carrier J81 .....................................................................
84-Lead Plastic Leaded Chip Carrier J83 .....................................................................
9-7
9-7
9-7
9-8
9-8
9-8
Ceramic Leadless Chip Carriers ••••••..•••.••••••.••••••••.•••••••••••••.••••••••••••••.•.••••••••••.•••••. 9-9
32-Pin Rectangular Leadless Chip Carrier L55 MIL-STD-1835 C-12 ........................................... 9-9
28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 .................................................... 9-9
Table of Contents
Package Diagrams (continued)
Page Number
52-Square Leadless Chip Carrier L69 ........................................................................ 9-9
68-Square Leadless Chip Carrier L81 MIL-STD-1835 C-7 ................................................... 9-10
Plastic Quad F1atpacks ..••••.•....•...•••.••..•....••..•.....••..•..•••.........••..•...••.•••.•••..•...• 9-11
52-Lead Plastic Quad F1atpack N52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . .. . . . . .. . . . . . . . . ... 9-11
80-Lead Plastic Quad Flatpack N80 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 9 -12
Plastic Dual-In-Line Packages ..•.•...••...•.....•••••.•.•..•••.•••...•••..•••.•••..••.•••..•..••.•....•.•.
28-Lead (600-Mil) Molded DIP P15 ........................................................................
28-Lead (300-Mil) Molded DIP P21 ........................................................................
48-Lead (600-Mil) Molded DIP P25 ........................................................................
9-13
9-13
9-13
9-13
Plastic Small Outline ICs ••.•..••••.•••.••••••...••••.••••.••••.•...••••....••••••....•••.•••...••...••...
24-Lead (300-Mil) Molded SOIC S13 .......................................................................
28-Lead 450-Mil (300-Mil Body Width) SOIC S22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28-Lead (300-Mil) Molded SOJ V21 ........................................................................
9-14
9-14
9-15
9-15
Ceramic Windowed Dual-In-Line Packages .................................................................. 9-16
28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D-15 Config. A .................................... 9-16
Ceramic J-Leaded Chip Carriers •..••.•...•..•••.•••..••..•..•..•.••••••••.•.•.•...•••.••..•..•...•••.. . . •• 9-17
84-Pin Ceramic Leaded Chip Carrier Y84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . .. . . . . . . . . . .. 9-17
iii
II
General Information 1
General Information
Page Number
Cypress Semiconductor Background ......................................................................... 1-1
DataCom Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-4
Ordering Information ..................................................................................... 1-5
Product Selector Guide .................................................................................... 1-6
Cypress Semiconductor Bulletin Board System (BBS) Announcement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-13
@-.~
•
" CYPRESS
to ensure competitive advantage. Used extensively in a wide
range of applications, PLDs constitute a large and growing mar·
ket. Cypress's UItraLogic m product line addresses the high-density programmable logic market. UltraLogic includes the
Ultra38000 m and pASIC380 m families of field-programmable
gate arrays (FPGAs), the industry'S fastest. It also includes high
performance complex PLDs, the FLASH370 m family. Both of
these product families are supported by Cypress's VHDL (Very
high-speed integrated circuit Hardware Description Language)
based Wap software design tools. Cypress pioneered the use of
VHDL for PLD programming, and Wap software is a key factor
in the company's overall success in the PLD market.
Cypress is a leading provider of the industry-standard 22VlO
PLD with a wide range of products. Cypress is committed to
competing in all ranges of the PLD market, with small devices,
including the industry standard 16V8, the MAX340 EPLD line,
and the UItraLogic products. To support these products, Cypress offers one of the industry's broadest range of programming
tools and software for the programming of its PLDs.
Cypress provides one of the industry'S broadest ranges of CMOS
EPROMs and PROMs. Cypress owns a large share of the highspeed CMOS PROM market, and with its new cost structure, is
effectively penetrating the mainstream EPROM market with a
popular 256 Kbit EPROM, and the introduction of the world's
fastest 512K and 1 Megabit EPROMs at 25 ns.
FCT Logic products are used in bus interface and data buffering
applications in almost all digital systems. With the addition of
tbe FCT logic product line, Cypress now offers over 46 standard
logic and bus interface functions. The products are offered in
the second generation FCT-T format, which is pin-compatible
with the older FCT devices, but adds TTL (transistor-to-transistor logic) outputs for significantly lower ground bounce and improved system noise immunity. Cypress also offers the most
popular devices with on-chip 25-ohm termination resistors
(FCT2-T) to further lower ground bounce witb no speed loss.
Included in the new product family is the CYBUS3384, a bus
switch tbat enables bidirectional data transfer between multiple
bus systems or between 5 volt and 3.3 volt devices. Cypress also
offers 16-bit versions of popular FCT products. This broad
product offering is produced on Cypress's high-volume, CMOS
manufacturing lines.
Cypress Semiconductor Background
Cypress Semiconductor was founded in April 1983 with the
stated goal of serving the high-performance semiconductor market. This market is served by producing the highest-performance
integrated circuits using state-of-the-art processes and circuit design. Cypress is a complete semiconductor manufacturer, performing its own process development, circuit design, wafer fabrication, assembly, and test. The company went public in May
1986 and has been listed on the New York Stock Exchange since
October 1988.
The initial semiconductor process, a CMOS process employing
1.2-micron geometries, was introduced in March 1984. This process is used in tbe manufacturing of Static RAMs and Logic circuits. In the third quarter of 1984, a 1.2-micron CMOS EPROM
process was introduced for the production of programmable
products. At the time of introduction, these processes were the
most advanced production processes in the industry. Following
the 1.2-micron processes, a O.8-micron CMOS SRAM process
was implemented in the first quarter of 1986, and a O.8-micron
EPROM process in the third quarter of 1987.
In keeping witb the strategy of serving the high-performance
markets with state-of-the-art integrated circuits, Cypress introduced two new processes in 1989. These were a bipolar submicron process, targeted for ECL circuits, and a BiCMOS process
to be used for most types of TTL and ECL circuits.
The circuit design technology used by Cypress is also state of the
art. This design technology, along with advanced process technology, allows Cypress to introduce tbe fastest, highest-performance circuits in the industry. Cypress's offers products in four
divisions: the Static Memory Division, the Programmable Products Division, the Computation Products Division, and the Data
Communications Division.
Static Memories Division
Cypress is a market-leading supplier of SRAMs, providing a
wide range of SRAM memories for leading companies worldwide. SRAMs are used in high-performance personal computers, workstations, telecommunications systems, industrial systems, instrumentation devices, and networking products.
Cypress's lower production cost structure allows the company to
compete effectively in the high-volume personal computer and
workstation market for SRAMs, including providing cache
RAMs to support today's high-performance microprocessors,
such as Pentium m, and PowerPC m. This business, combined
with upcoming low-voltage products for the cellular communications, portable instrument, and laptop/notebook PC markets,
positions Cypress for future success in this key product area.
Multichip modules is a fast-growing market segment tbat consists of mUltiple semiconductor chips mounted in packages that
can be inserted in a computer circuit board. Cache modules for
personal computers are the mainstay of this product line, and
Cypress has announced major design wins for these products in
IBM's PSNaluePoint m line of PCs, and in Apple Computer's
highest performing Power Macintosh ,. products.
Data Communications Division
This is an especially significant area for Cypress since it represents a more market-driven orientation for the company in a
fast-growing market segment. As part of the new company strategy, Cypress has dedicated this product line to serve the highspeed data communications market with a range of products
from the physical connection layer to system-level solutions.
HOTLink m , high-speed, point-to-point serial communications
chips have been well received. HOTLink, along with the SONET./SDS Serial Transceiver (SST m ), address the fast-growing
market segments of Asynchronous 1tansfer Mode (ATM) and
Fibre Channel communications. The company has also entered
the Ethernet market with the 100BaseT-4 CY7C971 Fast
Ethernet Transceiver and the CY7B8392 Coax Ethernet 1tansceiver. The data communications division encompasses related
products including RoboClock, a programmable skew clock buffer that adjusts complex timing control signals for a broad range
of systems. The division also offers a broad range of First-In,
First-Out (FIFO) memories, used to communicate data between
systems operating at different frequencies, and Dual-Port Memories, used to distribute data to two different systems simultaneously.
Programmable Products Division
Witb increasing pressure on system designers to bring products
to market more quickly, programmable logic devices (PLDs) are
becoming extremely popular. PLDs are logic control devices
tbat can be easily programmed by engineers in the field, and later erased and reprogrammed. This allows the designers to make
key changes to tbeir systems very late in the development cycle
1-1
&~
.)CYPRESS
Computation Products Division
This division focuses on the high-volume, high-growth market
surrounding the desktop computer. It is the second of Cypress's
market-oriented divisions. The division includes timing technology products offered through Cypress's IC Designs Subsidiary in
Kirkland, Washington. IC Designs products are used widely in
personal computers and disk drives, and the product line provides Cypress with major inroads into these markets, helping
move the company towards a more market-driven orientation.
IC Designs clock oscillators control the intricate timing of all aspects of a computer system, including signals for the computer's
central processing unit (CPU), keyboard, disk drives, system bus,
serial port, and real-time clock. They replace all of the metal can
oscillators used in the system. IC Designs recently announced a
new product, QuiXTAL ~ , which is a programmable metal can
oscillator, and replaces individual oscillators used to control timing signals in virtually every type of electronics equipment.
QuiXTAL can be programmed to any frequency, providing users
the ability to make last-minute frequency adjustments, speeding
time to market. QuiXTAL takes frequency synthesis beyond the
PC market, and addresses the broad market segments of electronic instrumentation, telecommunications equipment, and
medical systems.
Also offered by this division are chipsets for personal computers.
Cypress entered this market with the 1994 acquisition of Contaq
Microsystems, and recently announced the hyperCache ~ Chipset for Pentium ~ -class PCS. The hyperCache Chipset is the industry's most highly integrated. In addition to integrating keyboard and mouse control, real-time clock, and local-bus IDE
control, it is the only chipset which offers integrated second-level
cache.
Thailand. Be assured that Cypress's total quality commitment
extends to the new site-Cypress Bangkok.
The move to Bangkok consummated an intense search by Cypress for a world-class, environmentally sophisticated facility
that we could bring on line quickly. The Cypress search team
scrutinized fifteen manufacturing facilities in five countries and
chose a site managed by Alphatec Electronics Co., Ltd., a privately owned, entrepreneurial company promoted by the Thailand Board of Investment. Cypress Bangkok occupies almost
25,000 square feet-a significant portion of the manufacturing
floor space available within the facility. The full facility at Bangkok occupies more than 85,000 square feet on a site that encompasses 25 acres--sufficient room for expansion to a number of
buildings in a campus-like setting. In order to meet growing demand for its products, Cypress has broken ground on a new assembly and test facility in the Philippines, which is scheduled for
completion in 1996.
Cypress San Jose maintains complete management control of all
assembly, test, mark, and ship operations worldwide, thus assuring complete continuity of back-end operations and quality.
Cypress has added Thpe Automated Bonding (TAB) to its package offering. TAB, a surface-mount packaging technology, provides the densest lead and package footprint available for fully
tested die.
From Cypress's facility in Minnesota, a VME Bus Interface
Products group has been in operation since the acquisition of
VTC's fab in 1990. Cypress manufactures VIC and VAC VME
devices on the 0.8 micron CMOS process.
The Cypress motto has always been "only the best-the best facilities, the best equipment, the best employees ... all striving to
make the best products."
Cypress Facilities
Cypress operates wafer fabrication facilities in California's Silicon Valley (San Jose), Round Rock (Austin), 'lexas, and Bloomington, Minnesota. The company's fourth wafer fab, located adjacent to the Bloomington, Minnesota facility, went on-line in
July 1995. There are additional Cypress Design Centers in
Starkville, Mississippi, Colorado Springs, Colorado, and the
United Kingdom, and a PLD software design group in Beaverton, Oregon. The facilities are designed to the most demanding
technical and environmental specifications in the industry. At the
Texas and Minnesota facilities, the entire wafer fabrication area
is specified to be a Class 1 environment. This means that the ambient air has less than 1 particle of greater than 0.2 microns in
diameter per cubic foot of air. Other environmental considerations are carefully insured: temperature is controlled to a ±0.1
degree Fahrenheit tolerance; filtered air is completely exchanged
more than 10 times each minute throughout the fab; and critical
equipment is situated on isolated slabs to minimize vibration.
The company has also received IS09000 registration, a standard
model of quality assurance that is awarded to companies with exacting standards of quality management, production, and inspections.
Attention to assembly is equally critical. Cypress manufactures
100 percent of its wafers in the United States, at the front-end
fabrication sites in California (San Jose), Minnesota (Bloomington), and 'lexas (Round Rock). Cypress Thxas, the company's
largest fab, and Cypress Minnesota's fabs, are all Class 1 facilities.
To improve global competitiveness, Cypress chose to move most
back-end assembly, test, and mark operations to a facility in
Cypress Process Technology
In the last decade, there has been a tremendous need for highperformance semiconductor products manufactured with a balance of SPEED, RELIABILITY, and POWER. Cypress Semiconductor overcame the classically held perceptions that CMOS
was a moderate-performance technology.
Cypress initially introduced a 1.2-micron "N" well technology
with double-layer poly and a single-layer metal. The process
employed lightly doped extensions of the heavily doped source
and drain regions for both "N" and "P" channel transistors for
significant improvement in gate delays. Further improvements in
performance, through the use of substrate bias techniques, have
added the benefit of eliminating the input and output latch-up
characteristics associated with older CMOS technologies.
Cypress pushed process development to new limits in the areas
of PROMs (Programmable Read Only Memory) and EPLDs
(Erasable Programmable Logic Devices). Both PROMs and
EPLDs have existed since the early 1970s in a bipolar process
that employed various fuse technologies and was the only viable
high-speed nonvolatile process available. Cypress PROMs and
EPLDs use EPROM technology, which has been in use in MOS
(Metal Oxide Silicon) since the early 1970s. EPROM technology
has traditionally emphasized density while forsaking performance. Through improved technology, Cypress produced the first
high-performance CMOS PROMs and EPLDs, replacing their
bipolar counterparts.
To maintain our leadership position in CMOS technology, Cypress introduced a sub-micron technology in 1987. This 0.8 micron breakthrough made Cypress's CMOS one of the most advanced production processes in the world. The drive to maintain
1-2
~.~
W;CYPRESS
lem. The effort to adequately protect against ESD failures is perturbed by circuit delays associated with ESD protection circuits.
Focusing on these constraints, Cypress has developed ESD protection circuitry specific to 1.2-, 0.8-, 0.65-, and O.S-micron
CMOS process technology. Cypress products are designed to
withstand voltage and energy levels in excess of 2001 volts and
0.4 milli-joules.
Latch-up, a traditional problem with CMOS technologies, has
been eliminated through the use of substrate bias generation
techniques, the elimination of the "P" MOS pull-ups in the output drivers, the use of guardring structures and care in the physical layout of the products.
Cypress has also developed additional process innovations and
enhancements: multilayer metal interconnections, advanced
metal deposition techniques, silicides, exclusive use of plasma for
etching, and 100-percent stepper technology with the world's
most advanced equipment.
Cypress technologies have been carefully designed, creating
products that are "only the best" in high-speed, excellent reliability, and low power.
leadership in process technology has not stopped with the
0.8-micron devices. Cypress introduced a 0.6S-micron process in
1991. A O.5-micron process is currently in production.
Although not a requirement in the high-performance arena,
CMOS technology substantially reduces the power consumption
for any device. This improves reliability by allowing the device to
operate at a lower die temperature. Now higher levels of integration are possible without trading performance for power. For instance, devices may now be delivered in plastic packages without
any impact on reliability.
While addressing the performance issues of CMOS technology,
Cypress has not ignored the quality and reliability aspects of
technology development. Rather, the traditional failure mechanisms of electrostatic discharge (ESD) and latch-up have been
addressed and solved through process and design technology innovation.
ESD-induced failure has been a generic problem for many highperformance MOS and bipolar products. Although in its earliest
years, MOS technology experienced oxide reliability failures, this
problem has largely been eliminated through improved oxide
growth techniques and a better understanding of the ESD prob-
UltraLogic, Ultra3800, FLASH370, Wa1p3, HOTLink, SST, and hyperCache are trademarks of Cypress Semiconductor Corporation.
pASIC is a trademark of QuickLogic.
Pentium is a trademark of Intel Corporation.
Power PC and PSNalue Point are trademarks of International Business Machines Corporation.
Power Macintosh is a trademark of Apple.
MAX is a trademark of Altera.
1-3
I
L~
~,CYPRESS
DataCom Background
Cypress Semiconductor was founded in April 1983 with the
stated goal of serving the high-performance semiconductor market. We have continued to serve this market using state-of-theart process and circuit technology combined with architectural
excellence. Our initial product thrusts included high-performance SRAMs, PLDs, FIFOs, Dual Port RAMs, and EPROMs.
In 1991, Cypress created a Data Communications division, with
a focus on Physical Layer (PHY) devices to serve the ATM, SONET, Ethernet, ESCON, and Fibre Channel markets. Cypress's
DataCom division has delivered a family of these PHY devices
including the SST (SONET Serial1tansceiver) Clock Recovery
Device, the HOTLink 330 MHz point-to-point transmitter/receiver chip set, the CY7C971 10/100 Base-T4 Fast Ethernet
1tansceiver and the industry standard CY7B8392 10Base-2
Ethernet Coax Transceiver. In 1996 and 1997, Cypress will continue to deliver high performance solutions for the Physical
Layer Datacom market covering 10 Base-FL, 100 Base-TX, and
155 MHz (OC-3) ATM/SONET Integration.
Our goal is to continue to provide PRY solutions for all segments of the DataCom market induding Network Adapter
Cards, Routers, Switches, Repeaters, Mass Storage, and Disk
Farms. Our product evolution will continue through complete
solutions for these growth markets.
In addition to PHY devices, the DataCom division includes a
multitude of Specialty Memories including FIFOs (First-InFirst-Out) and Dual Port RAMs which are frequently used in
communications systems. Our current product count includes 44
Asynchronous and Synchronous FIFOs ranging from 64 x 9/18
through 32K x 9 at 100 MHz as well as 18 Dual Ports from 1K x
8 through 8K x 18 with 15 ns access times. We are confident that
our wide variety of Specialty Memory products will suit many of
your buffering requirements.
In addition to this DataCom Data Book, Cypress also offers
technical documentation including a new Applications Handbook, HOTLink User's Guide, and a VME User's Guide.
We look forward to serving you. Please call with any requests for
design, application, or additional product information.
1-4
~~YPRESS===================O==r=de=r=in~g==In=fI=o=rm==at=i=on~
In general, the valid ordering codes for all products (except modules and VMEbus products) follow the format below; e.g.,
CY7C128-45DMB, PALC16R8L-35PC
RAM, PROM, FIFO, JIP, EeL
PREFIX
r-cY"'
CY
CY
CY
DEVICE
SUFFIX
I 7C128 I I -45 D M B I
j7C245
L-35P C
7C404
-25DMB
7C9101
-30 P C
C = CMOS
B = BiCMOS
L
FAMILY
CMOSSRAM
PROM
FIFO
flP
PROCESSING
B =
=
T=
R =
MIL-STD-883C FOR MILITARY PRODUCT
LEVEL 2 PROCESSING FOR COMMERCIAL PRODUCT
SURFACE-MOUNTED DEVICES TO BE TAPE AND REELED
LEVEL 2 PROCESSING ON TAPE AND REELED DEVICES
TEMPERATURE RANGE
C = COMMERCIAL (O°CTO +700C)
I = INDUSTRIAL (-40°C TO +85°C)
M= MILITARY (-55°CTO +125°C)
PACKAGE
A = TIIIN QUAD PLSTIC FLATPACK (TQFP)
B = PLASTIC PIN GRID ARRAY (PPGA)
D = CERAMIC DUAL IN-LINE PACKAGE (CERDIP)/BRAZED DIP
E = TAPE AUTOMATED BONDING (TAB)
F = FLATPACK (SOLDER-SEALED FLAT PACKAGE)
G = PIN GRID ARRAY (PGA)
H = WINDOWED LEADED CHIP CARRIER
J = PLASTIC LEADED CHIP CARRIER (PLCC)
K = CERPACK (GLASS-SEALED FLAT PACKAGE)
L = LEADLESS CHIP CARRIER (LCC)
N = PLASTIC QUAD FLATPACK (PQFP)
P = PLASTIC DUAL IN-LINE (PDIP)
Q = WINDOWED LEADLESS CHIP CARRIER (LCC)
R = WINDOWED PIN GRID ARRAY (PGA)
S = SOIC (GULL WING)
T = WINDOWED CERPACK
U = CERAMIC QUAD FLATPACK (CQFP)
V = SOIC (J LEAD)
W = WINDOWED CERAMIC DUAL IN-LINE PACKAGE (CERDIP)
X = DICE (WAFFLE PACK)
Y = CERAMIC LEADED CHIP CARRIER
SPEED (ns or MHz)
L = LOW-POWER OPTION
A, B, C = REVISION LEVEL
Cypress FSCM #65786
1-5
I
Q~
Product Selector Guide
~,CYPRESS
Dual-Port RAMs
Size
Organization
Pins
Part Nnmber
Icc
(mA@ns)
Speed (ns)
1Kx8-Dual-PortMaster
1Kx8-Dual-PortSlave
48
48
CY7C130
CY7C140
tAA = 25,30,35,45,55
tAA = 25,30,35,45,55
8K
1Kx8-Dual-Port Master
52
CY7C131
8K
1Kx8-Dual-Port Slave
52
CY7C141
16K
2Kx8-Dual Port Master
48
16K
2Kx8-Dual-PortSlave
16K
16K
Packages
170@25
170@25
D,P
D,P
tAA = 25,30,35,45,55
170@25
J,L,N
tAA = 25,30,35,45,55
170@25
J,L,N
CY7C132
tAA = 25,30,35,45,55
170@25
D,P
48
CY7C142
tAA = 25,30,35,45,55
170@25
D,P
2Kx8-Dual-PortMaster
52
CY7C136
tAA = 25,30,35,45,55
170@25
J,L,N
2Kx8-Dual-PortSlave
52
CY7C146
tAA = 25,30,35,45,55
170@25
J,L,N
32K
4Kx8-Dual-Port, No Arbitration
48
CY7B134
tAA = 20,25,35,55
240@20
D,L,P
32K
4Kx8-Dual-Port, w/Semaph
52
CY7B1342
tAA = 20,25,35,55
240@20
J
32K
2Kx 16-Dual-Port Slave
68
CY7C143
tAA = 15,25,35,55
170@25
J,A
32K
2Kx 16-Dual-Port Master
68
CY7C133
tAA= 15,25,35,55
170@25
J,A
32K
4Kx8-Dual-Port, w/Semaph, Busy, Int
64,68
CY7B138
tAA = 15,25,35,55
260@15
J,L,A
32K
4Kx8-Dual-Port, No Arbitration
52
CY7B135
tAA = 20,25,35,55
240@20
J,L
32K
4Kx9-Dual-Port,w/Semaph,Busy,Int
68,80
CY7B139
tAA = 15,25,35,55
260@15
J,L,A
64K
8Kx8-Dual-Port, w/ Semaph, Busy, Int
64,68
CY7B144
tAA = 15,25,35,55
260@15
J,L,A
64K
8Kx9-Dual-Port, w/Semaph, Busy, Int
68,80
CY7B145
tAA = 15,25,35,55
260@15
J,L,A
64K
4Kx 16-Dual-Port, w/Semaph, Busy, Int
84,100
CY7C024
tAA = 15,25,35,55
280@15
J,A
64K
4Kx 18-Dual-Port, w/ Semaph,Busy, Int
84,100
CY7C0241
tAA = 15,25,35,55
280@15
J,A
128K
8Kx 16-Dual-Portw/Semaph, Busy, Int
84,100
CY7C025
tAA = 15, 25, 35, 55
280@15
J,A
128K
8Kx 18-Dual-Portw/Semaph, Busy, Int
84,100
CY7C0251
tAA = 15, 25, 35, 55
280@15
J,A
128K
16Kx8-Dual-Portw/Semaph, Busy, Int
64,68
CY7C006
tAA = 15, 25, 35, 55
260@15
J,A
128K
16Kx9-Dual-Portw/Semaph,Busy,Int
68,80
CY7C016
tAA = 15, 25, 35, 55
260@15
J,A
8K
8K
Communication Products
Description
Pins
HOTLink Transmitter
HOTLinkReceiver
28
28
SONET/SDH Serial1fansceiver
24
Part Nnmber
CY7B923
CY7B933
CY7B951
Speed (MHz)
Packages
Icc(mA)
160-330
160-330
65
120
J,L,S
J,L,S
51&155
50
S
CY7B955
ATM SONET/SDH1fansceiver
lOBASE 2/5 Ethernet Coax 1fansceiver
Fast Ethernet 100BASE-T41fansceiver
16,20,28
80
CY7B8392
CY7C971
10
10&100
25
300
J,P
N
Fast Ethernet 1OOBASE-TX 1fansceiver
HOTLinkEvaluation Card
44
N/A
CY7C973
CY9266
100
160-330
200
-N/A
J
C,F*,T
Note: Please contact a Cypress Representative for product availability.
1-6
Product Selector Guide
arcYPRESS
I
FIFOs
Asynchronous
Organization
64x4
64x4
64x4-w/OE
64x5
Pins
Part Number
16
16
16
18
CY3341
CY7C401
CY7C403
CY7C402
64x5-w/OE
18
64x8-w/OE and Almost Flags
285
64x 9-w/Almost Flags
Icc
(mA@ns)
Speed (ns)
Packages
1.2,2MHz
5,10,15,25 MHz
lO, 15,25 MHz
5, lO, 15,25 MHz
45
75
75
75
D,P
D,L,P
D,L,P
D,L,P
CY7C404
10,15,25 MHz
75
D,L,P
CY7C408A
15,25,35 MHz
115@15
D,L,p,V
285
CY7C409A
15,25,35MHz
115@15
D,L,p,V
256 x 9-w/HalfFull Flag
285,32
CY7C419
lO, 15,20,25,30,40,65
35@20
A,D,L,p,V
512 x 9-w/Half Full Flag
28
CY7C420
20,25,30,40,65
35@20
D,P
512x9-w/HalfFullFlag
285,32
CY7C421
10,15,20, 25,30,40,65
35@20
A,D,l,L,p,V
lKx9-w/HalfFullFlag
28
CY7C424
20, 25,30,40,65
35@20
D,P
A,D,l,L,P,V
lKx9-w/HalfFullFlag
285,32
CY7C425
10,15,20,25,30,40,65
35@20
2Kx9-w/HaifFuIlFlag
28
CY7C428
20,25,30,40,65
35@20
D,P
2Kx9-w/HaIfFuIlFlag
285,32
CY7C429
10,15,20, 25,30,40,65
35@20
A,D,l,L,P,V
4Kx9-w/HaIfFuIlFlag
28
CY7C432
25,30,40,65
35@20
D,P
4Kx9-w/HaIfFuIlFlag
285,32
CY7C433
10,15,20,25,30,40,65
35@20
A,D,l,L,P,V
8Kx 9-wIHaifFullFlag
28
CY7C460
15,25,40,65
lO5@15
D,l,L,P
8K x 9-w/Prog. Flags
28
CY7C470
15,25,40,65
lO5@15
D,l,L,P
16K x 9-w/HalfPuIlFlag
28
CY7C462
15,25,40,65
lO5@15
D,l,L,P
D,l,L,P
16K x 9-w/Prog. Flags
28
CY7C472
15,25,40,65
lO5@15
32Kx 9-w/HalfFuIlFlag
28
CY7C464
15,25,40,65
lO5@15
D,l,L,P
32K x 9-w/Prog. Flags
2Kx9-Bidirectional .
28
285
CY7C474
CY7C439
15,25,40,65
25,30,40,65
lO5@15
147@25
D,l,L,P
D,l,L,P
Clocked
Organization
512 x 9--Clocked
512 x 9--Clockedw/Prog. Flags
Pins
285,32
32
Part Number
Speed (ns)
Icc
(mA@MHz)
Packages
CY7C441
CY7C451
14,20,30'
14,20,30'
70@20
70@20
D,l,L,p,V
D,J,L
D,J,L,p,V
2K x 9-Clocked
285,32
CY7C443
14,20,30'
70@20
2Kx 9-Clocked w/Prog. Flags
32
CY7C453
14,20,30'
70@20
D,J,L
512 x 18--Clocked w/Prog. Flags
52
CY7C455
14,20,30'
90@20
J,L,N
lKx IS-Clocked w/Prog. Flags
2Kx IS-Clocked w/Prog. Flags
52
52
CY7C456
CY7C457
14,20,30'
14,20,30'
90@20
9O@20
l,L,N
J,L,N
Synchronous
Organization
64 x 9-Synchronous
256 x 9-Synchronous
512x9-Synchronous
lKx9-Synchronous
2Kx9-Synchronous
Pins
32
32
32
32
32
Part Number
CY7C4421
CY7C4201
CY7C4211
CY7C4221
CY7C4231
Speed (ns)
lO,15,25,35'
lO, 15,25,35'
10,15,25,35'
10,15,25,35'
10,15,25,35'
Note: Please contact a Cypress Representative for product availability.
1-7
Icc
(mA@MHz)
50@20
50@20
50@20
50@20
50@20
Packages
A,J
A,J
A,J
A,J
A,J
Product Selector Guide
FIFOs
(continued)
ICC
Organization
Pins
CY7C4241
10,15,25,35'
32
CY7C4251
CY7C4261
32Kx9-Synchronous
32
64 x 18-Synchronous
256x IS-Synchronous
4Kx9-Synchronous
512x IS-Synchronous
1Kx 18-Synchronous
2Kx 18-Synchronous
4Kx IS-Synchronous
8Kx IS-Synchronous
16Kx 18-Synchronous
Packages
A,J
10,15,25,35"
50@20
50@20
10,15,25,35'
50@20
A,J
CY7C4271
10,15,15,35'
50@20
A,J
64,68
CY7C4425
100@20
64,68
64,68
CY7C4205
10,15,25,35'
10,15,25,35'
A,J
A,J
CY7C4215
10,15,25,35'
100@20
1oo@20
64,68
CY7C4225
10,15,25,35'
100@20
A,J
64,68
64,68
64,68
64,68
CY7C4235
CY7C4245
CY7C4255
CY7C4265
10,15,25,35'
10,15,25,35'
10,15,25,35'
10,15,25,35'
100@20
100@20
100@20
1oo@20
A,J
A,J
A,J
A,J
32
32
8Kx9-Synchronous
16Kx9-Synchronous
(mA@MHz)
Speed (ns)
PartNmnber
A,J
A,J
• Cycle Times
Timing Technology Products
Application
Industry Standard Motherboard
Frequency Synthesizers
General Purpose Programmable
Products (486 Pentium/pentium
Pro motherboards, peripherals,
cable Tv, video games, MPEG
decoders, etc.)
PC Gral?hics Frequency
SynthesIZers
Part#
#of
PLLs
#of
Outputs
Features
Package
CY2250
1
14
PentiumlPentium Pro servers: 12 skew controlled CPU
clocks (250 ps pin-to-pin), 2 buffered reference clocks, 3.3V
28SOIC
CY2252
2
14
Pentium portables: 5 CPU/6 PCI clocks ~2 "early" PCI for
docking stations),24 MHz, 2 buffered re erence clocks, 3.3V
28SS0P
CY2254
2
14
Intel1l"iton chipset compatible: 4 CPU/6 PCI clocks, 12
MHz, 24 MHz, 2 buffered reference clocks, 3.3V
28SOIC
CY2255
1
14
OPTiVi'berchipsetcompatible: 6CPU(1 "early")/6PCI
clocks,2 uffered reference clocks, 3.3V
28SOIC
CY2257
1
14
Ali Aladdin chipset com~atible: 6 CPU/6 PCI clocks, 2 buffered reference clocks, 3. V
28SOIC
CY2260
2
14
Intel N atoma/'Il"iton II chipset compatible: 4 CPU/6 PCI
clocks, 48 MHz USB clock, 3 buffered reference clocks, 3.3V
28SOIC
28SS0P
CY2071
1
3
Fact0RrEPROM programmable singlePLL, 0.5-100 MHz,
5V/3.3
8SOIC
CY2081
3
3
Fact0RrEPROM programmable triple PLL, 0.5-100 MHz,
5V/3.3
8SOIC
CY2291
3
8
Factory EPROM progrmmable triple PLL, 0.2-100 MHz,
5V/3.3V
2OSOIC
CY2292
3
6
Factory EPROM programmable triplePLL, 0.2-100 MHz,
5V/3.3V
16SOIC
ICD2051
2
5
User-programmable dual PLL, 0.3-120 MHz, 5V
16SOIC
ICD2053B
1
1
User-programmable single PLL, 0.4 100MHz,5V
8SOIC
ICD2061A
2
2
User-programmable PC video/memory clocks, 0.4-120
MHz,5V
16SOIC
ICD2062B
2
6
User-pro~mable PECLvideoclockforworkstations,
2OSOIC
0.5-165
,5V
ICD2063
2
2
user-pror;ammable PC video/memory clocks, 0.3-135
MHz,5V3.3V
16SOIC
Programmable Skew Clock Buffer
(TIL Output)
CY7B991
1
8
3 -80 MHz, Programmable Skew (700 ps increments)
250 ps pin-to-pin skew
J,L
Pr~ammableSkewClockBuffer
CY7B992
1
8
3 - 80 MHz, Programmable Skew (700 ps increments)
250ps pin-to-pin skew
J,L
(C OS Output)
Note: Please contact a Cypress Representative for product availability.
1-8
Product Selector Guide
Timing Technology Products (continued)
Application
Part #
#of
PLLs
#of
Outputs
Features
Package
Low Skew Clock Buffer
(TIL Output)
CY7B991O
1
8
15-80MHz, tpD = 500ps
250 ps pin-to-pin skew
S
Low Skew Clock Buffer
(CMOS Output)
CY7B9920
1
8
15-80 MHz, tpD = 500ps
250 ps pin-to-pin skew
S
Note: Please contact a Cypress Representative for product availability.
1-9
II
Product Cross Reference
HOTLink Cross Reference
Cypress
TriQuiut
Raytheon
AMCC
Device
Speed
Range
Device
Speed
Range
Device
Speed Range
Device
Speed
Range
CY7B923/33
160-330
GA91Ol/2/3*
200/265
S2032/33*
265/531/1062
RCC700*
200/265
SST Cross Reference
Cypress
Device
Analog Devices
Requires
ISS·MHz
Oscillator
AMCC
Requires
ISS·MHz
Oscillator
Device
Requires
ISS·MHz
Oscillator
Device
CY7B951
No
AD 802*
Yes
S3014'
, Not pm compatible; see product profile for CyPress advantages.
Yes
CY7C971 Fast Ethernet Transceiver (lOOBASE-T4) Cross Reference
Cypress
Device
Broadcom
Integrated
'Iransmit
Filter
Seeq
Device
Integrated
Transmit
Filter
CY7C971
Yes
BCM5000*
No
, Not pm compatl e; see product proflle tor Cypress ae vantages.
AT&T
Device
Integrated
Transmit
Filter
80C240*
Yes
Device
.
Integrated
Transmit
Filter
No
CY7B839210BASE-2 Ethernet Coax Transceiver Cross Reference
Cypress
Seeq
National
Device
IcC
Auto
AU!
Distance
Device
Icc
Auto
AU!
Distance
Device
Icc
Auto
AU!
Distance
CY7B8392
35mA
Yes
300M
8392
130 rnA
No
185M
83C92
70 rnA
No
185M
CY7B839210BASE-2 Ethernet Coax Transceiver Cross Reference
Phillips/Sig
SSI
Device
Icc
Auto
AU!
Distance
Device
Icc
Auto
AU!
Distance
NE83Q92
35 rnA
Yes
185M
78Q8392
130 rnA
No
185M
• Not pin compatible; see product profile for Cypress advantages .
• , Speed in MHz.
1-10
=r
Product Cross Reference
rcYPRESS
FIFO Cross Reference
Cypress, prefix CY
Speed
(ns)
Device
IDT, prefix IDT
Speed
(ns)
Device
AMD, prefix Am
Speed
(ns)
Device
Quality, prefix QS
Speed
(ns)
Device
TI, prefix SN74
Device
Speed
(ns)
7C401
5-25*'
72401
10-45**
67C401
10-35*
*
7C402
5-25*'
72402
10-45**
67C402
10-35*
*
7C403
5-25**
72403
10-45**
67C403
10-35*
*
7C404
5-25**
72404
10-45**
67C404
10-35*
7C408/9
15-35*'
7C419
10-65
7200
15-65
7200
25-120
7C420/1
10-65
7201
15-65
7201
25-120
7201
7C424/5
10-65
7202
15-65
7202
15-80
7C428/9
10-65
7203
15-65
7203A
7C432/3
10-65
7204
15-65
7204A
7C441/451
14-30
72211*
15-50
7C443/453
14-30
72231*
7C455
14-30
72215'
7C457
14-30
72235'
15-50
7C460
15-40
7205
20-50
7C462
15-40
7206
20-50
7C462
15-40
7207
15-50
7C4421
10-35
72421
15-50
7C4201
10-35
72201
15-50
7C4211
10-35
72211
15-50
72211
ACT72211
15-50
7C4221
10-35
72221
15-50
72221
ACT72221
15-50
7C4231
10-35
72231
15-50
72231
ACT72231
15-50
7C4241
10-35
72241
15-50
72241
ACT72241
15-50
7C4251
10-35
7C4261
10-35
Sharp, prefix LH
Speed
(ns)
Device
ALS236
10-45**
ALS234
10-45**
5481/91 *
15-50
ACI7200
15-50
5495
15-80
12-120
ACI7201
15-50
5496
15-80
7202
12-120
ACT7202
15-50
5497
15-80
15-80
7203
10-120
ACT7203
20-50
5498
15-80
15-80
7204
10-120
ACT7204
20-50
5499
20-50
15-50
5492'
25-50
15-50
540215'
20-50
7205
,
15-50
7C4271
10-35
7C4425
10-35
7C4205
10-35
72205
10-50
7C4215
10-35
72215
10-50
72215
7C4225
10-35
72225
10-50
72215
7C4235
10-35
72235
10-50
7C4245
10-35
72245
10-50
7C4255
10-35
7C4265
10-35
Package
Code
Package
Code
Package
Code
Package
Code
Package
Code
Package
Code
PLCC
J
PLCC
J
PLCC
J
PLCC
JR
PLCC
RJ
PLCC
U
T/PQFP
N
T/PQFP
PF
T/PQFP
PN/PH
POIP
P
POIP
TP
POIP
RIP
POIP
P/P6
POIP
NP/NT
POIP
D/Blank
COIP
D
COIP
D
COIP
X
COIP
D/D6
COIP
NRI
Temp.
Range
Code
Temp.
Range
Code
Temp.
Range
Code
Temp.
Range
Code
Temp.
Range
Code
Temp.
Range
Code
Com'l
C
Com'l
Blank
Com'l
C
Com'l
N/A
Com'l
SN
Com'l
Industrial
I
Industrial
Military
MB
Military
Industrial
Industrial
B
Military
B
Military
• Nat pin compatible; see product profile for Cypress advantages.
*' Speed in MHz.
1-11
Industrial
B
Military
Industrial
SNJ
Military
Not offered
I
&~
Product Cross Reference
S;" CYPRESS
Dual Port Cross Reference
Cypress, prefix CY
Speed
(ns)
Device
lOT, prefix lOT
Speed
(ns)
Device
7C130/1
7B131
15-55
7130
7C132
25-55
7132
20-100
7C133
15-55
7133
7C136
7B136
15-55
71321
25-90
25-55
7C140/1
7B141
15-55
7140
20-100
7C142
25-55
7142
20-100
7C143
15-55
7143
25-90
7C146
7B146
15-55
71421
25-55
7B134/5
15-35
7134
25-70
7B1342
15-35
71342
25-70
7B144
15-35
7005
25-70
7C024
15-55
15-55
7024
20-70
7C025
7025
20-70
7C006
15-55
7006
25-70
7C016
15-55
7016
15-70
7C0241
15-55
7C0251
15-55
7B145
Package
Code
7015
Package
Code
PLCC
J
PLCC
J
PDIP
P
PDIP
P
CDIP
D
CDIP
D
Temp.
Range
Code
Temp.
Range
Code
Com'l
C
Com'l
Blank
Industrial
I
Industrial
Military
MB
Military
15-55
20-100
20-70
B
• Not pin compatible; see product profile for Cypress advantages.
•• Speed in MHz.
1-12
·
~.,
~
..•~
,CYPRESS================================
Cypress Semiconductor Bulletin Board System (BBS) Announcement
Cypress Semiconductor supports a 24-hour electronic Bulletin Board System (BBS) that allows Cypress
Applications to better serve our customers by allowing them to transfer files to and from the BBS.
The BBS is set up to serve in multiple ways. One of its purposes is to allow customers to receive the most
recent versions of Cypress programming software. Another is to allow the customers to send PLD programming files that they are having trouble with to the BBS. Cypress Applications can then find the errors in the
files, correct them, and place them back on the BBS for the customer to download. The customer may also
ask questions in our open forum message area. The sysop (system operator) will forward these questions to
the appropriate applications engineer for an answer. The answers then get posted back into the forum.
Communications Set-Up
The BBS uses US Robotics HST Dual Standard modems capable of 14.4-Kbaud rates without compression
and rates upwards of 19.2-Kbaud with compression. It is compatible with CCITT V32 bis, V32, V22
(2400-baud), Bell 212A (1200-baud), CCITT V42, and CCITT V42 bis. It also handles MNP levels 2, 3, 4,
and 5.
To call the BBS, set your communication package parameters as follows:
Baud Rate:
1200 baud to 19.2 Kbaud. Max. is determined by your modem.
Data Bits: 8
Parity: None (N)
Stop Bits: 1
In the U.S. the phone number for the BBS is (408) 943-2954. In Japan the BBS number is
81-423-69-8220. In Europe the BBS number is 49-810-62-2675. These numbers are for transmitting
data only.
If the line is busy, please retry at a later time. When you access the BBS, an initial screen with the following
statement will appear:
Rybbs Bulletin Board
After you choose the graphics format you want to use, the system will ask for your first and last name. If you
are a first-time user, you will be asked a few questions for the purposes of registration. Otherwise you will be
asked for your password, and then you will be logged onto the BBS, which is completely menu driven.
Downloading Application Notes and Datasheets
A complete listing of files that may be downloaded is included on the BBS. Application notes are available
for downloading in two formats, PCL and Postscript'M . An "hp" in front of the file name indicates it is a PCL
file and can be downloaded to Hewlett-Packard LaserJets'M and compatible printers. Files without the hp
preceding them are in Postscript and can be downloaded to any Postscript printer.
If you have any problems or questions regarding the BBS, please contact Cypress Applications at (408)
943-2821 (voice).
Postscript is a trademark of Adobe Corporation.
LaserJet is a trademark of Hewlett Packard Corporation.
1-13
II
Ethernet 2
Ethernet
Page Number
Device Number
CY7C971
CY7B8392
CY7B4663
Description
100BASE-T4/10BASE-T Fast Ethernet nansceiver (CAT 3) . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
Ethernet Coax nansceiver Interface ............................................ 2-24
Integrated lOBASE-FL Ethernet nansceiver ..................................... 2-31
Application Notes
CY7B8392
CY7C971
CY7C971
CY7C971/CY7C388P
Low Power Ethernet Coaxial nansceiver Application ..............................
100BASE-T4/lOBASE-T Ethernet nansceiver Application ..........................
100BASE-T4 /lOBASE-T Ethernet PCI Network Adapter ...........................
100BASE-T4 Ethernet Repeater ................................................
2-40
2-51
2-55
2-72
CY7C971
PRELIMINARY
lOOBASE-T4/10BASE-T
Fast Ethernet Transceiver (CAT 3)
Features
• Complies with IEEE 802.3u draft
standard
• Three operating modes:
-100BASE-T4
-IOBASE-T Full Duplex
-IOBASE-T
• Media Independent Interface (MIl)
- Tbree-state receive port
- Serial management port
• Auto-Negotiation
• On-cbip transmit wave sbaper
• Receive filter and adaptive
equalization
• PMA Interface for repeater
applications
• Jam function for bub applications
• LED status indicators: TX, RX, Link
• Loopback mode for PHY integrity
testing
• Auto-polarity correction
• Low-power CMOS
• SO-pin PQFP
Functional Description
The CY7C971 is a full featured physical
layer transceiver (PRY) device supporting
both l00BASE-T4 (Fast Ethernet) and
lOBASE-T Local Area Network (LAN)
standards. The CY7C971 complies with
IEEE 802.3 100BASE-T4, lOBASE-T,
MIl, and Auto-Negotiation standards for
twisted pair interfaces.
The CY7C971 interfaces to category 3, 4,
or 5 unshielded twisted-pair cable through
its Media Dependent Interface (MDI).
The Media Independent Interface (MIl)
attaches directly to Media Access Control
(MAC) layer devices.
Control and Status
PMA
The CY7C971 performs the Physical Coding Sublayer (PCS), Physical Layer Signalling (PLS), Physical Media Attachment
(PMA), and Media Attachment Unit
(MAU) functions defined in the 802.3
standard. Ethernet frames are transferred
from the MAC to the CY7C971 over the
MIl interface. The data is encoded in the
PCS or PLS encoder (8B6T for
100BASE-T4 or Manchester
for
10BASE-T) and then passed to the PMA
or MAU where the encoded data is shifted
bitwise on to the twisted-pair media. Collision and Carrier Sense signals are generated by the CY7C971 and passed to the
MAC over the MIl.
The CY7C971 PHY uses 802.3 standard
Auto Negotiation to configure the link.
The PHY includes a direct interface to the
PMA layer for repeater applications.
Address
u..
-$-Vcc
~GND
~~~~B~~
TX ClK
TXD[3:0]
TX ER
nCEN
-
:?!
PCS
TX/RX
4
2
E-T4~:x
(BB6T)
2
COL
CRS
COLLISION
DETECT
CARRIER
SENSE
CLOCK
AUTO
RECOVERY NEGOTIATIO
2
2
RX CLK
RXD[3:0]
RX ER
RlfDV
RX=EN
TX_D1±
4
2
PlS
TX/RX
2
MAU
TX/RX
1
RX_D2±
TX_D3±
RX_D3±
TX_D4±
RX_D4±
(MANCHESTER)
7C971·1
Clock
LED Drivers
2-1
External Com onents
0
:?!
~
PRELIMINARY
CY7C971
.TcYPRESS===============
Pin Configuration
SO-Lead Plastic Quad Flatpack
(Top View)
PINl
AX03
RX02
GNOO
AXOl
AXDO
AlCOV
AX.ClK
RlCER
TX.ER
VCCO
TX.ClK
TJCEN
TXOO
TXOl
TX02
TX03
GNOO
VCCS
AlC04TX.04GNOS
TX_D4+
RX.04+
VCCS
RX.OSTlC03GNOS
TX.03+
RlC03+
vccs
RlC02·
RX_D2+
vccs
TX 01·
GNDS
TX_D1+
05
COL
CRS
vccs
7C971-2
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Thmperature with
Power Applied ........................ -55°C to + 125°C
Supply Voltage to Ground Potential ......... -O.SV to +7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5V to + 7.0V
DC Input Voltage ........................ -3.0V to +7.0V
Static Discharge Voltage ........................ >2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
2-2
Range
Commercial
Ambient
Temperature
O°Cto +70°C
Vee
SV ± 10%
~22~YPRESS==========PRE==L=IM=I=N=~=R=Y=========CY==7C=9=71=
Pin Descriptions
Media Independent Interface (MIl)
Description
Name
I/O
TXD[3:0]
(D[3:0])
Input
(TTL)
nansmit Data. TXD[3:0] are the data signals that carry the Ethernet transmit frame data from the
MAC to the PHY on a nibble basis. TXD[3:0] are sampled on the rising edge of TX_ CLK when
TX_EN is asserted HIGH. In PMA mode, these pins become the D[3:0) pins used for passing
binary encoded 8B6T symbols to the PMA sub layer.
TX_EN
Input
(TTL)
TX_CLK
Output
(TTL, Three
State)
Input
(TTL)
Transmit Enable. When asserted HIGH, TX_EN indicates that the MAC is presenting data to the
TXD[3:0) inputs of the PHY. TX_EN should be asserted HIGH with the first nibble of the
preamble and remain HIGH for the duration of the frame.TX_EN should be deasserted on the
first cycle following the final nibble of the frame. In PMA mode, TX_EN is asserted HIGH in order
to latch D[5:0) into the transmitter.
nansmit Clock. In MIl Mode (MODE = HIGH), TX_CLK is a continuous clock that provides a
timing reference for the transfer ofTXD[3:0), TX_EN, and TX_ER from the MAC. The nominal
frequency of TX_CLK is 25 MHz in lOO-Mb/s mode and 2.5 MHz in lO-Mb/s mode.
Transmit Coding Error. When asserted HIGH while TX_EN is HIGH, the PHY will transmit an
error code word. TX_ER is sampled on the rising edge of TX_CLK. In PMA mode, this pin becomes the D4 pin used for passing binary encoded 8B6T symbols to the PMA sublayer.
Receive Data. RXD[3:0] are the data signals that carry the received Ethernet frame data from the
PHY to the MAC on a nibble basis. RXD[3:0) are driven synchronous to RX_ CLK. In PMA mode,
these pins become the Q[3:0) pins used for transferring binary encoded 8B6T symbols from the
PMA sublayer.
TX ER
(D4)
RXD[3:0]
(Q[3:0))
Output
(TTL, Three
State)
RX_DV
Output
(TTL, Three
State)
RX_CLK
Output
(TTL, Three
State)
RX_EN[lJ
Input
(TTL)
RX_ER
Output
(TTL, Three
State)
Output
(TTL, Three
State)
Receive Error. RX ER is asserted HIGH to indicate to the MAC that a fault condition was detected during the frame presently being transferred from the PHY to the MAC. RX_ER is driven
synchronously with RX_CLK.
Collision Detect. COL is asserted HIGH to indicate that a collision has occurred on the media.
COL is asserted asynchronously and with minimum delay from the start of the collision. In PMA
Mode, this pin becomes the Q4 pin used for transferring binary encoded 8B6T symbols from the
PMA sublayer.
CRS
Output
(TTL, Three
State)
MDC
Input
(TTL)
Carrier Sense. CRS is asserted HIGH by the PHY to indicate the detection of a non-idle condition
on the media. CRS is asserted asynchronously and with minimum delay from the detection of the
non-idle condition. CRS is asserted HIGH throughout the duration of a collision condition.
Management Data Clock. MDC is sourced from the station management entity (STA) to the PHY
as a timing reference for the transfer of management information on the MDIO signal.
MDIO
Bidirectional
(TTL, Three
State)
COL
(Q4)
Receive Data Valid. When asserted HIGH, RX_DV indicates that the PHY is presenting recovered and decoded nibbles on the RXD[3:0) lines and that RX_CLK has been synchronized to the
recovered data. RX_ DV is first driven HIGH when RXD[3:0] contains the SFD and is held HIGH
for the duration of the frame. RX_DV makes transitions synchronous to RX_ CLK. InPMA Mode,
RX DV is driven high when Q2-3 contains the first data symbol.
Receive Clock. RX_ CLKis a continuous clock that provides a timing reference for the transfer of
RXD[3:0], RX_DV, and RX_ER signals from the PHY to the MAC. When RX_DV is HIGH,
RX CLK is recovered from the received data. When RX DV is LOW, RX CLK is sourced from
the PHY's nominal frequency. Transition between nominal frequency and recovered frequency is
made while RX_DV is LOW. In lOO-Mh/s mode, the nominal clock frequency is 25 MHz,and in
lO-Mb/s the nominal frequency is 2.5 MHz.
Receiver Output Enable. RX_EN enables the RXD[3:0], COL, Q5, RX_ER, and RX_DV signal
drivers. RX_EN allows the receive data signals to bussed together for multiple PHY applications.
Management Data Input/Output. MDIO is a bidirectional signal between the PHY and the station
management entity (STA) used to transfer control and status information. Control information is
driven from STA to the PHY synchronously with MDC and sampled on the rising edge of MDC.
The PHY drives status information to the STA synchronously With MDC. The STA samples the
data on the rising edge of MDC.
Note:
1. RX_EN is not specified in the 802.3 MIl standard.
2-3
=t
1-" ~
PRELIMINARY
CY7C971
;CYPRESS==============
Pin Descriptions (continued)
Media Dependent Interface
Name
I/O
Description
TX D1+
TX=D1-
Differential
Output
Transmit Data. TX Dl ± are differential line drivers for data transmission. In lOBASE-T mode
TX_D1± transmit Manchester encoded data with a nominal period of 100 ns. In 1ooBASE-T4
mode TX_D1 ± transmit 8B6T ternary symbols with a nominal period of 40 ns. TX_D1 ± also participate in the Link Integrity function.
RX D2+
RX=D2-
Differential
Input
Receive Data. RX_D2± are differential line receivers for data reception. In 100-Mb/s mode,
RX_D2± receives 8B6T ternary symbols with a nominal period of 40 ns. In lO-Mb/s mode,
RX_D2± receives Manchester encoded bits with a nominal period of lOOns. RX_D2± alsoparticipates in the Link Integrity function.
TX D3+
TX=D3-
Differential
Output
MODE
Input
(TTL)
Mode. When MODE is tied HIGH, the transceiver is in normal mode. Received and tranmitted
data will move through the PMA and the PCS sublayers. Asserting MODE LOW exposes the
100BASE-T4 PMA service interface and disables 10BASE-T. The pes is bypassed and the binary
coded 6T serial data is presented at the MIl and PMA interface pins.
D5
Input
PMA Input Data. D5 is an input signal to the PMA transmit sublayer when MODE is asserted
LOW.
nansmit Data. TX_D3± are differential line drivers for data transmission. In 100-Mb/s mode,
TX_D3± transmits 6T ternary symbols with a nominal period of 40 ns. In 10-Mb/s mode, TX_D3±
are not used.
Receive Data. RX_D3 ± are differentialline receivers used for data reception. In 100-Mb/s mode,
RX D3+
Differential
Input
RX_D3 ± receives 6T ternary symbols with a nominal period of 40 ns. In lO-Mb/s mode, RX_D3±
RX=D3are not used.
Transmit Data. TX D4± are differential line drivers used for data transmission. In 1OO-Mb/s
TX D4+
Differential
mode, TX_D4± tnmsmits 6T ternary symbols with a nominal period of 40 ns. In 10-Mb/s mode,
Output
TX=D4TX_D4± are not used.
Differential
Receive Data. RX_D4± are differentialline receivers used for data reception. In 1oo-Mb/s mode,
RX D4+
RX_D4± receives 6T ternary symbols with a nominal period of 40 ns. In lO-Mb/s mode, RX_D4±
Input
RX=D4are not used.
Physical Media Attachment Interface
Name
Description
I/O
(TTL)
Q5
Output
(TTL,
Three State)
Control and Status
Name
I/O
PMA Output Data. Q5 is an output signal from the PMAreceive sublayerwhen MODE is asserted
LOW. Q5 is high-impedence when RX_EN is HIGH.
Description
RESET
Input
(TTL)
Reset. When RESET is asserted LOW, the PHY is placed in the reset state and the transmit and
receive functions are disables. The MIl registers are placed in their default states.
AUTONEG
Input
(TTL)
Auto-Negotiation Enable. When asserted HIGH, Auto-Negotation capability is enabled by setting
the Status Register bit 1.3. Auto-Negotation is controlled through the MIl management registers.
When asserted LOW, Auto-Negotation capability is disabled. AUTONEG is sampled on the rising
edge of RESET.
ENT4
Input
(TTL)
Enable 1ooBASE-T4. ENT4 enables 100BASE-T4 operation by setting the Status Register bit
1.15. When ENT4 is HIGH, bit 1.15 is forced HIGH, enabling 100BASE-T4 operation. When
ENT4 is LOW, bit 1.15 is forced LOW, disabling 100BASE-T4. ENT4 is latched on the rising edge
of RESET.
ENT
Input
(TTL)
ENTFD
Input
(TTL)
Enable lOBASE-T. ENT enables 10BASE-T operation by setting the Status Register bit 1.11.
When ENT is HIGH, bit 1.11 is forced HIGH, enabling lOBASE-T operation. When ENT4 is
LOW, bit 1.11 is forced LOW, disabling lOBASE-T. ENT is latched on the rising edge of RESET.
Enable 10BASE-T Full Duplex. ENTFD enables lOBASE-T Full Duplex operation by setting the
Status Register bit 1.12. When ENTFD is HIGH, bit 1.12 is forced HIGH, enabling lOBASE-TFull
Duplex operation. When ENTFD is LOW, bit 1.12 is forced LOW, disabling lOBASE-T Full Duplex. ENTFD is latched on the rising edge of RESET.
ISODEF
Input
(TTL)
Isolate Default. ISODEF determines the default state of Isolate Bit 0.10 in the Control Register.
When ISODEF is HIGH, the default value for 0.10 is 1. When ISODEF is LOW, the default value
for 0.10 is O. ISODEF is latched on the rising edge of RESET.
LOOP
Input
(TTL)
Lodiback Enable. When asserted LOW, the transmitter bit stream is looped back to the receiver
for iagnostic testing. When LOOP is HIGH, the Loopbackfunction is controlled by the Loopback
bit in the control register.
2-4
- .~
PRELIMINARY
CY7C971
'CYPRESS============~=
Pin Descriptions (continued)
Control and Status (continued)
Name
JAM
TEST
Address
Name
A[4:0]
LED Drivers
Name
I/O
Description
Input
(TTL)
100BASE-T4 Jam Generation. When JAM is LOW in 100BASE-T4 mode and a carrier is present,
the PRY will enter the collision state and generate the Jam pattern. The jam condition will persist
for a minimum of 512 bit times.
Test. This pin is used for factory testing and should be tied LOW for normal operation.
Input
(TTL)
I/O
Input
(TTL)
I/O
LRX
Output
(Open Drain,
Weak Pull-Up)
LTX
Output
(Open Drain,
Weak Pull-Up)
Output
(Open Drain,
Weak Pull-Up)
LINKT4
LINKT
LINKFD
Output
(Open Drain,
Weak Pull-Up)
Output
(Open Drain,
Weak Pull-Up)
Description
PHY Address. These pins assign the management address to the PHY. AO is least significant bit
andA4 is the most significant bit. A4 is the first address bit received by the PHY in the management
frame. The address is latched on the rising edge of RESET.
Description
Receive LED Indicator. LRX is driven LOW when the transceiver is receiving. An internal20KQ
resistor will pull LRX HIGH when the transceiver is not receiving.
1tansmit LED Indicator. LTX is driven LOW when the transceiver is transmitting. An internal
20KQ resistor will pull LTX HIGH when the transceiver is not transmitting.
100BASE-T4 Link Pass LED Indicator. LINKT4 is driven LOWwhen the 100BASE-T4 transceiver
is in the Link Pass State. An internal20KQ resistor will pull LINKT4 HIGH when the transceiver
is not in the 100BASE-T4 Link Pass State.
lOBASE-TLink Pass LED Indicator. LINKT is driven LOW when the lOBASE- Ttransceiver is in
the Link Pass State. An internal20KQ resistor will pull LINKT HIGH when the transceiver is not
in the 100BASE-T Link Pass State.
lOBASE-T Full Duplex Link Pass LED Indicator. LINKFD is driven LOW when lOBASE-T Full
Duplex has been negotiated or chosen as the operating mode and the lOBASE-T transceiver is in
the Link Pass State. An internal20KQ resistor will pull LINTFD HIGH when the transceiver is not
in the 100BASE-T Link Pass State.
Clock
I/O
Name
CLKI
Input
CLKO
Output
Description
Reference Clock Input. In MIl Mode (MODE=HIGH), the 25-MHz signal is used as a timing
reference for TX_CLK and analog circuits. This pin should be connected to either to a 25-MHz
crystal or a crystal-controlled TTL-level clock source. In PMA mode (MODE = LOW), CLKI is
an input and is used as a timing reference for the PMA interface and analog circuits.
Reference Clock Output. This pin connects to a 25 MHz crystal or is left open if a TTL clock is used
with CLKI. In PMA mode, CLKO should be left open.
External Components
Name
R1
I/O
Description
Passive
10K ±1 % External resistor.
R2
Passive
Power and Ground
Name
I/O
Digital Power
VeeD
10K ±1 % External resistor.
Description
Positive Voltage Supply. Vee requires a 5V ± 10% supply.
VeeA
Analog Power
Positive Voltage Supply. Vee requires a 5V±1O% supply.
Vecs
Serial MDI
Power
Positive Voltage Supply. Vee requires a 5V ± 10% supply.
GNDD
GNDA
Digital Ground
Analog Ground
Ground.
Ground.
GNDS
SerialMDI
Ground
Ground.
2-5
PRELIMINARY
CY7C971
1OBASE-T/1 OOBASE-T4
Transceiver Card
CY7C971
Transceiver
802.3
MAC
Mil
7C971-3
Figure 1. Transceiver Card Block Diagram
Transmit Physical Coding Sublayer (PCS)
CY7C971 Description
lOOBASE-T4
The CY7C971 provides a physical layer interface (PHY) for dual
speed IEEE 802.3 100BASE-T4 and lOBASE-T CSMNCD local
area networks.lOOBASE-T4 offers increased performance over existing lOBASE-T networks while maintaining compatibility with
the existing Ethernet Media Access Control (MAC) specification.
The lOOBASE-T4 PHY interfaces to 4 pairs of category 3, 4, or 5
cable. The 100BASE-T4 PHY is comprised of the Physical Coding
Sublayer (PCS), Physical Media Attachment (PMA), Media Independent Interface (MIl), and Media Dependent Interface (MDI).
A typica1100BASE-T4 transceiver card application is shown inFig-
ure 1.
Transmitter
The transmitter is comprised of the Physical Coding Sublayer
(PCS) and the Physical Media Attachment (PMA). Figure 2 shows
a block diagram of the T4 transmitter.
pes
The PCS takes nibble-wide data from the MIl and accumulates
them into 8-bit octets in the TXD! and TXD2 registers. The octets
are then encoded using the 8B6T ternary code according to the
802.3 standard. The encoded 8B6Tcode groups are then loaded in
binary form to the shift registers.
Three shift registers convert the parallel8B6Tcode groups to serial form. When the transmitter is active, a shift register is loaded on
every otherTX_CLKcycle. The first 8B6Tcode group ofthe frame
is loaded into TX shiftl. The second group is loaded into
TX shift2 and the third into TX shift3. The 4th group will be
loaded into TX_shiftl. This sequence continues until all of the
8B6T code groups comprising the frame have been transmitted.
At the start of the transmit frame, TX shift2 and TX shift3 will be
loaded with a pad sequence aligned With first 8B6T code group in
TX_shiftl. The pad sequence aides the receiver with clock recovery and pair alignment. The preamble is generated automatically
and follows the pad sequence.
-----------------T
.-----____:l
8B6T r6""X~2......
Encoder
I
I
Wave
Shaper
7C971-4
Fignre 2. T4 Transmitter Block Diagram
2-6
PRELIMINARY
PMA
CY7C971
pes
r-~----------------------------------~RX_CLK
6x2
RXD[3:0]
RX_ER
RX_DV
" ________
Loopback
data
_
I
l.
Figure 3. T4 Receiver Block Diagram
7C971-5
Transmit Physical Media Attachment (PMA)
Carrier Sense
The Transmit PMA converts the serial encoded 6T bits from the
transmitPCS to their corresponding ternary waveforms. The waveshaper Digial to Analog Converter (OAC) generates high precision raised cosine waveforms on each transmission pair. The
waveforms conform tothe 100BASE-T4 output template specification. No external filters are required. The PMA output drivers interface to the media through external termination resistors and
isolation transformers.
The carrier sense function detects activity on the media using a
smart squelch function similiar to lOBASE-T. The CRS signal is asserted HIGH when a valid carrier is detected on the pair RX_02
according to the 1OBASE-T4 draft standard. After detecting a valid
carrier, an eopl code group or seven consecutive zeros on RX_02
must be detected before CRS is deasserted.
Collision Detection
Receiver
The T4 receiver is comprised of the PCS and the PMA. Figure 3
shows a block diagram of the receiver
Receive Physical Media Attachment (PMA)
The PMAreceivesserial8B6Tsymboisfrom the twisted-pair interface and presents them to the PCS. The T4 receiver media interface features three adaptive equalizers. The equalizers compensate
for the attentuation of high-frequency signals by up to 100 meters
of category 3,4, or 5 twisted-pair cable. The equalized waveforms
are converted to binary form and passed to the clock recovery and
data alignment blocks. The clock recovery circuit aligns the frequency and phase ofRX_CLK with that of the received serial data.
The data alignment block deskews the three receive channels.
Receive Physical Coding Sublayer (peS)
The PCS accepts serial8B6T symbols from the PMA, deserializes
them, and then decodes the 8B6T code groups. Three shift registers convert the serial data back to parallel form. The first 8B6T
code group is shifted into RX_shiftl. The second 6Tsymbol group
is shifted into RX shift2 and the third into RX shift3. The fourth
code group is then shifted into RX_shiftl. ThiS-process continues
until the entire frame has been deserialized. The parallel 8B6T
data are converted to 8-bit octets and latched into registers RXDI
and RX02 on every other RX_ CLK. The data is then presented at
the MIl interface in nibble form. RX OV indicates that received
data is present on the RXD[3:0] pins.-RX_ER indicates that a receiver fault has occured.
A collision is detected when the transmitter is active simultaneouslywith the detection of a valid carrier by the carrier sense function.
The MIl COL signal will be asserted HIGH to signal the presence
of a collision. When a collision is detected the TX 02 and TX 03
pair drivers turn off.
- -
Auto-Polarity Correction
The Auto-Polarity Correction function monitors the received signal polarity on RX_02± and inverts the received signal internally
if its polarity is inverted. Auto-Polarity Correction is active during
Auto-Negotation and normal operation.
lOBASE-T
The CY7C971 provides a lOBASE-T physical layer interface for
compatibilitywithexistinglO-Mb/sEthernetnetworks.lOBASE-T
operation is automatically selected if Auto-N egotation established
lOBASE-T as the highest common operating mode. The
10BASE-T transceiver can also be enabled manually by disabling
Auto-Negotation and clearing the Speed Selection (0.13) bit in the
Mil Control Register. The LINKTpinindicateswhen 10BASE-Tis
the selected mode of operation and the 1OBASE-T transceiver is in
the link pass state. Figure 4 shows a block diagram of the lOBASE-T
transceiver.
During lOBASE-T operation, transmit and receive data are transfered over the MIl interface in nibble wide groups. The TX_CLK
and RX CLK clocks are sourced from the PRY with a 2.5-MHz
nominalclock rate. TX_EN qualifies incoming transmit data, and
RX_DV qualifies receive data. In this mode, the MIl complies
with the IEEE Mil specification for a lO-Mb/s interface.
2-7
--2~YPRESS~~~~~P=~=L=1=M=IN=~~Y~~~~~C~Y7~C~9~71~
Manchesterl-...,....._ _.....~
Encoder
Link
Integrity
COL_-----!
CRS_-----!
RXCLK_--------~~----------------~
(2.5 MHz)
7C971·6
Figure 4. lOBASE-T Transmitter & Receiver Block Diagram
Full Duplex
The CY7C971 supports Full Duplex operation in lOBASE-T
mode. lOBASE-T Full Duplex operation is automatically selected
ifAuto-Negotation established lOBASE-TFull Duplex as the highest common operating mode. The 10BASE-T Full Duplex operation can also be selected manually by disabling Auto-Negotation
and clearing the Speed Selection (0.13) bit and setting the Duplex
Mode Bit (0.8) in the MIl Control Register. lOBASE-T Full Duplexmode cannot be enabled through Auto-Negotation or manually unless the the ENTFD pin is HIGH. The LINKFD pin indicates when lOBASE-T Full Duplex is the selected mode of
operation and the lOBASE-T transceiver is in the link Pass State.
During full duplex operation, the collision pin (COL) is Ww.
Auto-Polarity Correction
The Auto-Polarity Correction function monitors the received signal polarity on RX_D2± and inverts the received signal internally
if its polarity is inverted. Auto-Polarity Correction is active during
Auto-Negotation and normal operation.
Media Independent Interface (MIl)
The MIl provides a connection between the PRY and the MAC
and between the PRY and the station management (STA) entity.
The MIl is capable of supporting 100- and 10-Mb/s operation.
Data transfer is accomplished over nibble-wide dedicated transmit
and receive channels. When TX EN is asserted HIGH, data on
TXD[3:0] channel is latched into the PRY on the rising edge of
TX_CLK and passed to the PCS. IfTX_ER is asserted HIGH, an
8B6T code violation word will be sent in place of the transmit data.
TX_CLK provides a continuous clock that is sourced from the
PRY.
When recovered data is available from thePCS, the RX_DV signal
is asserted HIGH simultaneously with the first Start of Frame Delimiter (SFD) nibble on RXD[3:0]. The RX_DV signal remains
HIGH continuously through the final recovered nibble of the
frame. If an error is detected in the frame by the PRY, the RX_ER
signal is driven HIGH synchronously with RX_CLK.
RX_ CLKis a continuous clock that provides a timing reference for
the transfer of RXD[3:0], RX_DY, and RX_ER from the PRY to
the MAC. RX CLK is sourced from the PRY. While RX DV is
deasserted, RX_CLK will run at the PHY's nominal frequency.
When RX_DV is asserted, the frequency and phase ofRX_ CLKis
recovered from the received data. During the transition from nominal to recovered frequency, the period ofRX_CLKmay extend by
up to one cycle. RX_ CLK stretching prevents logic failures from
occuring in downstream logic while the clock makes it transition.
When a carrier is detected, the CRS signal is asserted HIGH. A
collision is signaled by asserting COL HIGH. CRS is asserted
throughout a collision condition.
Access to the management facilities are provided throught the MIl
with the MDC and MDIO pins. These pins provide a serial interface to the management control and status registers. The MDCsignal is driven to the PRY from the management station (STA) as a
timing reference for transfer of information on the MDIO signal.
The MDIO signal is a bidirectional signal between the PRY and
the STA. Control information is driven by the STA to the PRY.
Status information is driven from the PRY to the STA.
2-8
PRELIMINARY
CY7C971
Media Dependent Interface
Mil Management Interface
The Media Interface is comprised of four communications channels. A dedicated transmit channel, TX D1±, transmits
100BASE-T4 and lOBASE-Tsignals. RX_D2±-is a dedicated receive channel for both 100BASE-T4 and lOBASE-T signals. The
two bidirectional channels for 100BASE-T4 are formed from
TX_D3±, RX_D3± and TX_D4±, RX_D4±.
The MDI pins interface to the medium through external resistors
and isolation transformers. No external filters are required. The
transmit drivers use class AB differential drivers to help reduce
power consumption while providing ample drive capability. The
drivers have a common mode control circuit to help reduce common mode emissions.
The management facilities are accessed through the MIl management pins MDCand MDIO. The management facilities respond to
register accesses that match the PHY address. The PHY address is
assigned with the A[4:0) pins. The value of these pins are latched
into the internal PHY address register on the rising edge of RESET.
Register accesses are perfomed by transferring an opcode, address,
and register number to the PHY management facility. If the address transferred matches the PHY address at theAO-A4 pins, the
PHY responds to the access. During a read access, 16 bits of data
from the selected register are transferred from the PHY to the STA
on the MDIO pin. During a write, 16 bits of data are transferred
from the STA to the PHY and written into the selected register.
Control and Status Registers
Control and status information are stored in two 16-bit registers.
The Control register is assigned address 0 and the Status register is
assigned address 1. Table 1 shows a map of the Control register and
Table 2 shows the Status register.
Management
The management facilities are used to control and indicate the statusofthe PHY resources. The management facilities and MIl management interface is compliant with the IEEE 802.3 MIl draft
specification.
Table 1. Mil Control Register Detinition[2]
Control Register (Register 0)
Bit(s)
Name
0.15
Reset
0.14
Loopback
0.13
Speed Selection
0.12
Auto Negotiation Enable
0.11
Power Down
0.10
Isolate[3]
0.9
RestartAuto-Negotiation
0.8
Duplex Mode
0.7
Collision Test
0.6:0
Reserved
R/W
Default
Description
1- PHYReset
o = Normal Operation
R/W
SIC
0
Resets the status and control registers to their default states. Reset is
self clearing.
1 = Loopback Mode
R/W
0
Loopback connects the transmit
data path to the receive data path.
1 - 100 Mbls
0= 10 Mbls
R/W
1
When Auto-Negotiation is disabled,
Speed Select determines the speed
of the PHY.
1 - Enable Auto-Negotation
R/W
1
This bit enables the Auto-Negotiation function.
1 - Power Down
R/W
0
Power down shuts off the internal
PLLs and core logic.
1 = Isolate PHY from MIl
R/W
0,1
Isolate places the receiver MIl channel in high impedence, and the MIl
transmiter channel does not respond
to MIl activity.
o = Normal Operation
1 = Restart Auto-Negotiation
R/W
SIC
0
Restart Auto-Negotiation breaks
the link and restarts the Auto Negotiation process.
1 = Full Duplex
R/W
0
Duplex Mode selects between full
and half duplex operation for
lOBASE-T.
1 = Test COL Signal
R/W
0
Collision test causes the COL signal
to be asserted when TX_EN is asserted.
Setting
o = Normal Operation
o = Disable Auto-Negotiation
o = Normal operation
o = Normal Operation
o = Half Duplex
o = Normal Operation
0
Notes:
2. RIW = ReadlWrite
SC = Self Cleaning
RO = Read Only
LH = Latched HIGH
3. Isolate default is set by the ISODEF pin.
2-9
E
='-.f~
PRELIMINARY
CY7C971
'CYPRESS============
Thble 2. Mil Status Register Definition
Status Register (Register 1)
Bit(s)
1.15[4J
Setting
R/W
Default
Description
100BASE-T4
1 = 100BASE-T4 Able
o = 100BASE-T4 Able
RO
1,0
When set, this bit indicates that
the PHY is 100BASE-T4 capable.
1.14
100BASE-TX Full Duplex
O = 100BASE-TX Full Duplex
Not Supported
RO
0
This bit is always set to zero.
1.13
100BASE-TX Half Duplex
O = 100BASE-TX Half Duplex
Not Supported
RO
0
This bit is always set to zero.
1.12P1
1OBASE-T Full Duplex
1 - 1OBASE-T Full Duplex Able
RO
1,0
When set, this bit indicates that
the PHY is 1OBASE-T full duplex
capable.
1.11l6 J
1OBASE-T Half Duplex
1 = 1OBASE-THalfDuplexAble
0= 10BASE-THalfDuplexAble
RO
1,0
When set, this bit indicates that
the PHY is 1OBASE-T half duplex
capable.
1.10:6
Reserved
0- Default
RO
0
1.5
Auto-Negotiation
Complete
1 = Auto-Negotiation Complete
0= Auto-Negotiation Incomplete
RO
0
This bit is set when NWAY has
completed the auto negotiation
process.
1.4
Remote Fault
1 = Remote Fault Condition
RO
0
This bit is set when Auto Negotiation detects a remote fault.
1.317J
Auto Negotiation Ability
1 = PHY is Able to Perform Auto
Negotiation
RO
1,0
PHY supports Auto-Negotiation.
1.2
Link Status
1- Link Is Up
RO
0
Link Status indicates that the
PRY is in the Link Pass State.
1.1
Jabber Detect
o = No Jabber Condition
1 = Jabber Condition Detected
RO
LH
0
Jabber Detect indicates that ajabber condition has been detected
for 1OBASE-T.
1.0
Extended Capabilities
1 - Extended Register Capable
RO
1
~UI and Auto-Negotiation Extended Registers 2 - 7 are present.
Name
o = 10BASE-T Full Duplex Able
o = No Remote Fault Condition
o = Link Is Down
Detected
Vendor and Product ID Registers
Vendor and Product identification codes are stored in management ID registers 2 and 3. These registers contain the Cypress
Semiconductor Corporation unique identifier and the CY7C971
product and revision number. Table 3 explains the ID registers.
Auto-Negotation Registers
The Auto-Negotation process is managed through the Auto-Negotation registers. Register 4 is the Auto-Negotation Advertisement register. This register contains the 16-bit code word that is
advertised to the remote link partner. Register 5 is the Auto-Negotation Link Partner Ability register for base and next pages. This
register holds the 16-bitcode word that the Auto-Negotation function receives from the remote link partner. Register 6 is the AutoNegotation Expansion register and is used to monitor the negotiation process. Register 7 is the Auto-Negotation Next Page
nansmit register. The function of the Auto-Negotation register
bits are defined in Tables 4 through 7.
Auto-Negotation
Auto-Negotation advertises the capabilities of the PRY by transmitting a sequence of fast link pulses (FLPs) that form a standard
16-bit code word. The advertised code word is contained in the
Auto-Negotation Advertisement register (Register 4). Auto-Negotation receives 16-bit code words and stores them in the AutoNegotation Partner Ability register (Register 5). Once the code
words have been sent and acknowledged, Auto-Negotation selects
the highest common operating mode as the current mode of operation. The highest common mode of operation is determined by the
Priority Resolution Thble specified in the Auto-Negotation standard. When a mode of operation is selected, Auto-Negotation enables the transition to the selected mode's Link Pass state.
TheAuto-Negotation process is controlled and monitored through
the MIl management registers. Auto-Negotation may be disabled
in the MIl control register or by asserting the AUTONEG pin
HIGH.
The Auto-Negotation is capable of transmitting and receiving code
word pages in addition to the base pages. The next page process is
controlled through the MIl registers.
The IEEE Auto-Negotation function provides remote capability
detection and automatic speed selection. Auto-Negotation is fully
compatible with existing 1OBASE-T only devices.
Notes:
4.
5.
lOOBASE-T4 Default is set by the ENT4 pin.
lOBASE-T FD Default is set by the ENTFD pin.
6. lOBASE-T HD Default is set by he ENT pin.
7. Auto-Negotiation Default is set by the AUTONEG pin.
2-10
PRELIMINARY
CY7C971
Table 3. MIl PHY ID Register Definition
PHY Identifier (Register 2 and 3)
Bit(s)
R!W
Default
Description
RO
0028h
This field contains 16 bits of the
Cypress Organizationally Unique
Identifier (OUI).
RO
02h
This field contains 6 bits of the
Cypress Organizationally Unique
Identifier (OUI).
CY7C971 Model Number
RO
01h
This field contains a 6-bit model
number.
CY7C971 Revision Number
RO
-
This field contains a 4-bit revision
number.
Setting
Name
2.15:0
OUI PHY Identifier
16 Most Significant OUI Bits
3.15:10
~UI
6 Least Significant
3.9:4
Model Number
3.3:0
Revision Number
PHY Identifier
~UI
Bits
Table 4. MIl Auto-Negotation Advertisement Register Definition
Auto-Negotation Advertisement Register (Register 4)
Bit(s)
Name
4.15
Next Page
4.14
Reserved
Setting
1 = Next Page to be Transmitted
o = No Next Page
R!W
Default
Description
R/W
0
When set, this bit will cause the PHY
to advertise Next Page capability.
RO
0
Reserved.
Wben set, this bit will cause the PHY
to advertise a Remote Fault has occured.
4.13
Remote Fault
1 = Fault Indication
0= No Fault
R/W
0
4.12
Technology Ability Field
Reserved
Reserved
RO
0
Reserved.
4.11
Technology Ability Field
Reserved
Reserved
RO
0
Reserved.
4.10
Technology Ability Field
Reserved
Reserved
RO
0
Reserved.
4.9[8]
Technology Ability Field
100BASE-T4
o = Do Not Advertise
1 = Advertise 100BASE-T4
R/W
1,0
Wben set, this bit will cause the PHY
to advertise 100BASE-T4 capability.
This bit may only be set if
100BASE-T4 is enabled.
4.8
Technology Ability Field
100BASE-TX Full
Duplex
o=
100BASE-TX FD
Not Supported
RO
0
This bit will always be zero.
100BASE-TX FD is not supported.
4.7
Technology Ability Field
100BASE-TX
o = 100BASE-TX Not
Supported
RO
0
This bit will always be zero.
100BASE-TX is not supported.
4.6[9]
Technology Ability Field
10BASE-T Full Duplex
o = Do Not Advertise
1 = Advertise lOBASE-T FD
R/W
1,0
Wben set, this bit will cause the PHY
to advertise lOBASE·T FD capability. This bit may only be set if
lOBASE-T FD is enabled.
4.5[10]
Technology Ability Field
lOBASE-T
o = Do Not Advertise
1 = Advertise 10BASE-T
R/W
1,0
When set, this bit will cause the PHY
to advertise 10BASE-T capability.
This bit may only be set if lOBASE-T
is enabled.
4.4:0
Selector Field
Indicates IEEE 802.3 LAN
RO
01h
This field is permanently set to 0001
to advertise IEEE 802.3 CSMNCD
LAN.
Notes:
8. 100BASE-T4 Advertised Ability default is set by the ENT4 pin.
9. lOBASE-T FD Advertised Ability default is set by !be ENTFD pin.
10. lOBASE-T Advertised Ability default is set by the ENT pin.
2-11
E
§§ ~YPRESS~~~~~P~~~L~1~M~IN~~~R~Y~~~~~C~Y7~C~9~71=
Table 5. MIl Auto·Negotation Link Partner Ability Register Definition
Auto·Negotation Link Partner Ability Register (Register 5)
Bit(s)
Setting
R!W
Default
Description
1 = Next Page to be 'fransmitted
o = No Next Page
RO
0
When set, this bit indicates the
remote PRY has a Next Page to
send.
1 = Remote Acknowledge
RO
0
When set, this bit indicates that
the remote PHY has acknowl·
edged receipt of a page.
Remote Fault
1 = Fault Indication
0= No Fault
RO
0
When set, this bit indicates that a
fault has ocurred in the remote
PHY.
5.12
Thchnology Ability Field
Reserved
Reserved
RO
0
Reserved.
5.11
Thchnology Ability Field
Reserved
Reserved
RO
0
Reserved.
5.10
Technology Ability Field
Reserved
Reserved
RO
0
Reserved.
5.9
Technology Ability Field
100BASE·T4
o = Not lOOBASE·T4
RO
0
When set, this bit indicates that
remote
the
PHY
has
100BASE·T4 capability.
5.8
Technology Ability Field
100BASE·TX Full Duplex
o = Not 100BASE·TX FD Able
1 = l00BASE·TX FD Able
RO
0
When set, this bit indicates that
the remote PHY has 100BASE·
TX FD capability.
5.7
Thchnology Ability Field
l00BASE·TX
o = Not OOBase·TX Able
1 = 100BASE·TX Able
RO
0
When set, this bit indicates that
the remote PRY has l00BASE·
TX capability.
5.6
Thchnology Ability Field
lOBASE-T Full Duplex
o = Not lOBASE·T Able
1 = 10BASE·T FD Able
RO
0
When set, this bit indicates that
the remote PRY has lOBASE-T
FD capability.
5.5
Thchnology Ability Field
10BASE·T
o = Not lOBASE-T Able
1 = lOBASE·T Able
RO
0
When set, this bit indicates that
the remote PRY has lOBASE-T
capability.
5.4:0
Selector Field
Indicates LAN 'JYpe
RO
OOh
This field indicates the type of
LANs being advertised by the remotePHY.
Name
5.15
Remote Next Page
5.14
Remote Acknowledge
5.13
o = No Acknowledge
1 = l00BASE·T4 Able
Able
2-12
--b~YPRESS==========PRE==L=IM=I=N=~==Y=========CY==7C=9=71=
Thble 6. MIl Auto.Negotation Expansion Register Definition
Auto Negotiation Expansion Register (Register 6)
R!W
Default
6.15:5
Reserved
Reserved
RO
0
Reserved.
6.4
Parallel Detection Fault
1 = Parallel Detection Fault
0= No Parallel Detection Fault
RO
LH
0
When set, this bit indicates that
local Auto·Negotation has
detcted more than one valid link.
6.3
Link Partner Next Page
Able
1 = Link Partner is Next Page
Able
o = Link Partner is Not Next
Page Able
RO
0
When set, this bit indicates that
the remote PRY supports Next
Page capability
6.2
Next Page Able
1 = Next Page Able
RO
1
This bit indicates that local
Auto·Negotation supports Next
Page capability.
6.1
Page Received
1 = 3 Identical Code Words Re·
ceived
O = 3 Identical Code Words
Have Not Been Received
RO
LH
0
When set, this bit indicates that
local Auto-Negotation has received three consecutive and
identical code words.
6.0
Link Partner Auto Negotiation Able
1 = Link Partner is Auto-Negotiation Able
o = Link Partner is Not AutoNegotiation Able
RO
0
When set, this bit indicates that
the remote PHY has Auto-Negotation capability.
Bit(s)
Setting
Name
Description
Thble 7. MIl Auto-Negotation Next Page Transmit Register Definition
Auto-Negotation Next Page Transmit Register (Register 7)
Bit(s)
Name
7.15
Next page
7.14
Reserved
7.13
Message Page
7.12
Acknowledge 2
7.11
Thggle
7.10:0
MessagelUnformatted
Code Field
R!W
Default
Description
1 = More Pages Follow
0= Last Page
R!W
0
When set, this bit indicates that
more pages follow. When clear,
it indicates that the last page is
being sent.
RO
0
1 = Message Page
o = Unformatted Page
R!W
0
When set, this bit indicates that
the next page being sent is formatted as a message page.
1 = Will Comply
RO
1
When set, this bit indicates that
the device can comply with the
received message.
1 = Previous Thggle Was Zero
RO
0
This bit is used to ensure synchronization with the link partner during next page exchange.
Eleven-Bit Field
R!W
OOOh
This field contains the message/
unformatted bits for the next
page.
Setting
o = Cannot Comply
o = Previous Thggle Was One
Loopback
PMAMode
In Loopback Mode, the transmit PMA circuits are isolated from
the media and are connected to the receive PMAcircuits. 'fransmit
data flows from the MIl through the PCS and into the PMA. The
serial data is then looped back through the Receiver PMAand PCS
to the MIl interface. Loopback Mode is useful for checking the integrity of the PHY and MAC operations.
Loopback Mode is enabled by either setting the Loopback bit in
the Management Control register to one or by asserting the LOOP
pin LOW.
When the MODE pin is LOW, the CY7C971 is in 100BASE-T4
PMAmode. This mode of operation is intended for use in repeater
applications. In PMA mode, the PCS is bypassed exposing the
PMA sublayer. Binary encoded 6T symbols are transfered directly
over the PMA interface pins. This reduces the transmitter latency
for use in class 1 and class 2 repeaters. A block diagram ofthe PMA
interface is shown in Figure 5. 10BASE-T is disabled in the Status
register.
2-13
IJ
PRELIMINARY
T4 Receiver
Repeater
r---------~CRS
CY7C971
T4 Transmitter
Link
LlNKT4 +------1 Integrity
ClKI
Carrier
Detect
RX_EN
' - - - _ RX_DV
' - - - - - + RX_ER
7C971·7
Figure 5. T4 Transmitter & Receiver PMA Interface and Block Diagram (MODE
Serial6T data from the three PMA circuits are transferred over the
PMA interface pins in binary form. The Receiver aligns and converts the line signals to their 6T binary representation and drives
them to the Q[5:0] pins. The transmitter latches the three 6Tsymbol streams on its D[5:0] input pins on the rising edge ofTX_CLK
The 6T symbols are loaded into the waveshaper DAC and converted to their correspondingternarywaveforms. TableS shows the
mapping of binary PMA signals to ternary waveforms.
Table 8, PMA Binary to Ternary Map[ll]
PMA
QI-O, Q3-2, Q5-4
DI-O, D3-2, D5-4
"Transmitter
Receiver
00
CSO
CSO
10
CSI
CSI
01
CS-l
CS-l
11
CSO
-
=LOW)
The RX_ DV signal indicates when the first data symbol after sosb
is present on the QO- 5 PMA interface pins. RX_ DV will remain
HIGH throughout the transfer of data symbols across the PMAinterface. RX_ DV is LOW when there is no carrier present RX_ER
HIGH indicates a pair alignment error. The RX_EN input pin enables the QO-5, RX DY, and RX ER drivers. RX EN LOW
places the drivers in the high-impedence state.
The transmit PMA interface is synchronous to the CLK! input
clock signaL The TX_EN HIGH causes data on the PMA DO-5
pins to be loaded into the transmit PMA waveshaper on the rising
edge of CLK!. When TX_EN is Law, the output drivers transmit
the CSO idle symbols.
Applications
The CY7C971 is a flexible physical-layer device that fits into any
Ethernet application including network interface cards, transceiver cards, repeaters, hubs and switches. Figure 6 shows a schematic
of the CY7C971 configured for a transceiver card application with
an exposed MIl port
Notes:
1 L CSO is a wavefonn which conveys the ternary symbol O.
CS1 is a waveform which conveys the ternary symbol L
CS-1 is a waveform which conveys the ternary symbol - L
2-14
PRELIMINARY
CY7C971
~z
LEDS
1.5K
5Kr.
1 KQ
•
~ ~ fL-1"!'
~ -- ...
~
~
.
.::47'-'Q""''II'-1-1-1
~~
""
I"
I
!-"----'
~
~
!~
~
80
~ ~ § ~ !, § § Ig I~ ~I~rI~~I~ TI~g ~ ~
RXD3
>
~
> >
~ ~
...J
4m
",,",""'111'-1--1
RXD2
GNDD
15
I
II
4m
47Q
~
T
II
3
C!J 0
1 :2
-
r" .... "
.-
I
RXD1
I
RXDO
I
RX_DV
RX_ClK
RX_ER
;-
CY7C971
VCCD
TX_ClK
I
I
I
I
I
I
I
I
TX_EN
TXDO
TXD1
TXD2
-
-
TXD3
GNDD
D5
COL
CRS
11 1
+5V
~
GND
5KQ
7C971-8
Figure 6. 100/10 Transceiver Card Schematic
2-15
I
I
TX_ER
4m
f:
I
f:
=-'~YPRESS=========P=RE==L=IM=I=NAR==Y=========CY==7=C9=7=1
Electrical Characteristics Over the Operating Range
Description
Parameter
Test Conditions
Min.
Max.
Unit
TTL Pins
VOHT
Output HIGH Voltage
VOLT
Output LOW Voltage
VIHT
Input HIGH Voltage
VILT
Input LOW Voltage
IIxr
Input Load Current
GNDsVrsVee
-10
IOZT
Output Leakage Current
GND S Vo s Vee, Output Disabled
-SO
lOST
Output Short Circuit Current[12]
Vee = Max., VOUT = GND
Vee = Min., IOL = 12.0 rnA
0.4
V
Vee = Min., IOH = -4.0 rnA
2.4
V
0.4
V
2.0
6.0
V
-3.0
0.8
V
+10
+SO
JAA
JAA
-3S0
rnA
Vee = Min., IOL = 4.0 rnA
Open Drain LED Pins
Output LOW Voltage
VOLD
Miscellaneous
leel
Vee Operating Supply Current
Vee = Max., lOUT = 0 rnA,
100BASE-T4 transmitting
300
rnA
lecz
Vee Operating Supply Current
Vee = Max., lOUT = 0 rnA,
100BASE-T4 not transmitting
100
rnA
ISB
Power-Down Current
Max. Vee
TBD
rnA
Capacitance[13]
Description
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
AC Test Loads and Waveforms
481'-1
~~8~~NG J
SCOPE
~
255'-1
OUTP~~
5 pF
~~8~~NG
~
SCOPE
(a)
Equivalent to:
5n
J
(b)
Unit
S
pF
8
pF
3.0V---90%
255'-1
7C971·9
THEvENIN EQUIVALENT
OUTPUT~
Max.
ALL INPUT PULSES
481'-1
OUTP~~ ~
30 pF
Test Conditions
TA = 2SoC, f = 1 MHz,
Vee = S.OV
1.73V
Notes:
12. Thsted one output at a time, output shorted for less than one second,
less than 10% duty cycle.
13. Thsted initially and after any design or process changes that may affect
these parameters.
2-16
GND
7C971·10
PRELIMINARY
CY7C971
Switching Characteristics Over the Operating Rangel14]
Description
Parameter
Min.
Max.
Unit
MDTiming
tTCPWHT4
TX_CLK Pulse Width HIGH (T4)
14
26
ns
tTCPWLT4
TX_CLK Pulse Width LOW (T4)
14
26
ns
tTCPWHT
TX_CLK Pulse Width HIGH (T)
194
206
ns
tTCPWLT
TX_CLK Pulse Width LOW (T)
194
206
ns
tIDS
TXD Set Up
10
tIDH
TXDHold
0
tTMIIT4
Transmit Latency (T4)
110
ns
tTMIIT
Transmit Latency (T)
500
ns
tTCRSHT4
Transmit Path CRS Assert (T4)
20
ns
tTCRSHT
Transmit Path CRS Assert (T)
20
ns
tTCRSLT4
'Itansmit Path CRS Deassert (T4)
320
ns
tTCRSLT
Transmit Path CRS Deassert (T)
100
ns
tRCPWHT4LlOj
tRCPWLT4 LDj
RX_CLK Pulse Width HIGH
14
26
ns
RX_CLK Pulse Width LOW
14
26
ns
tRCPWHTL"j
RX_CLKPulse Width HIGH
194
206
ns
tRCPWLTL j
RX_CLK Pulse Width LOW
194
206
ns
tRDV
RXD Valid from Clock
18
ns
tRDH
RXD Hold from Clock
tRXDVT4
RXD Valid Latency (T4)
870
ns
tRXDVT
RXD Valid Latency (T)
500
ns
tRXDATAT4
RXD Latency (T4)
950
ns
tRXDATAT
RXD Latency (T)
8700
ns
tRHZD
RX_EN HIGH to Valid Data
15
ns
tRDHZ
RX_EN LOW to High Impedance
20
ns
I'
ns
ns
10
ns
lOOBASE-T4 CRS and COL
tCRSH[lbj
CRS Assert Latency for Preamble
140
ns
tCRSLC[llj
CRS Deassert Latency for EOe
370
ns
tCRSLELl~j
CRS Deassert Latency for EOP
370
ns
tCOLHI L1Yj
COL Assert Latency from TX_EN HIGH
20
ns
tcoLL1L~Uj
COL Deassert Latency from TX_EN LOW
20
ns
tCOLH2L~lj
COL Assert Latency from Preamble
190
ns
tCOLL2 LUj
COL Deassert Latency from EOC or EOP
370
ns
110
Notes:
14. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOl)lOH and 30-pF load capacitance.
15. During clock transition, clock max time could be as long as an entire
cycle.
16. tCRSH is measured from the rising edge of the latest arriving signal of
the three pair that meets the lOOBASE-T4 squelch criterion to the rising edge of CRS. The rising and falling edges of CRS are guarenteed
to meet the fairness timing specification defined in the 100BASE-T4
standard.
17. tCRSLC is measured from the end ofthe last data symbol on RX_D2 to
the falling edge on CRS. Seven consecutive zeros must be received on
RX_D2 in order for the PMA to recognize loss of carrier.
18. tCRSLE is measured from the begining of the first symbol of EOP1 on
any RX_Dx MDI pair accounting for skew to the falling edge on CRS.
Detection of a properly framed EOP1 will cause the PCS to recognize
loss of carrier.
19. tCOLHl is measured from the rising edge ofTX_CLK while TX_EN is
HIGH to the rising edge of COL.
20. tCOLL! is measured from the rising edge ofTX_CLK while TX_EN is
LOW to the falling edge of COL.
21. tCOLIU is measured from the rising edge ofthe signal on RX_ D2 that
meets the 100BASE-T4 unsquelch criterion to the rising edge of COL.
22. tCOLL2 is measured from the first symbol of the EOP or EOC sequences to the falling edge of COL.
2-17
IJ
PRELIMINARY
CY7C971
Switching Characteristics Over the Operating Range (continued)
Parameter
Description
Min.
Max.
Unit
10BASE·T CRS and COL
tcRSH3 l23j
CRS Assert Latency
500
ns
tCRSL3 l24j
CRS Deassert Latency
500
ns
Management Timing
tMCPWH
MDC Pulse Width HIGH
25
tMCPWL
MDC Pulse Width LOW
25
fM
MDC Frequency
ns
12.5
tMDS
MDIOSet·Up
10
tMDH
MDIOHold
0
tMDO
MDIO Valid from Clock
tMDOH
MDIO Hold from Clock
tMDHZ
MDC to High Impedance
ns
0
Reset Pulse Width LOW
ns
ns
0
Control Input Set·Up
tRS
PMA Interface Timing
MHz
ns
40
MDC to Low Impedance
tMDLZ
Control and Status Timing
tRL
ns
40
ns
20
ns
5
!-IS
100
ns
tTPMA
PMA 1tansmit Latency
tIDS
PMA 1tansmit Data Set Up
10
40
tIDH
PMA 1tansmit Data Hold
0
tpMACRSH
PMA CRS Assert Latency
110
tpMACRSL
ns
ns
ns
140
ns
PMA CRS Deassert Latency
650
ns
tpMADATA
Clock Timing
PMA Receiver Data Latency
800
ns
tCPWH
Reference Clock Pulse Width HIGH
16
24
ns
tCPWL
Reference Clock Pulse Width LOW
16
24
fc
Reference Clock Frequency
25 - 100 ppm
Notes:
23. tCRSH3 is measured from the rising edge of the signal on RX_D2 that
meets the lOBASE-T carrier criterion to the rising edge of CRS.
24. tCRSL3 is measured from th eend ofthe last data symbol on RX_D2 to
the falling edge of CRS.
2-18
25
+ 100 ppm
ns
MHz
II
~
PRELIMINARY
CY7C971
,CYPRESS==============
Switching Waveforms
MIl Thansmit Port Data Timing[25)
tTCPWHT4,
tTCPWHT
tTCPWLT4,
tTCPWLT
•
tTM11T4,
tTMIlT
tTCRSHT4,
tTCRSHT
CRS
tTCRSLT4,
tTCRSLT
7C971-11
MIl Receive Port Data Timing[26, 27]
~------------------------- ~XDATAT4,
____________________________~
tRXDATAT
-----+--
PREAMBLE
-"'*------~If_-- DATA
""0--------
tRXDVT4,
tRXDVT
---ilr-------*'-----
-------j,-----t---------t---
RXD[3:0],
DATA
RX_ER
7C971·12
Notes:
25. tMII is measured from the rising edge of TX_eLK to the 50% point of
the TX_Dx± outputs at the MOl pins.
26. tRXDV is measured from the first rising edge of the preamble at the
MDI input pins to the rising edge of RX_DY. This includes up to 64
bits of preamble and SFD plus the latency of the receive circuitry.
27. tRxDATA is measured from the first rising edge of the preamble at the
MOl input pins to tbe rising edge of valid data at the RXD pins. This
includes up to 64 bits of preamble and SFD plus the first 8 bits of data
and the latency of the receive circuitry.
2-19
- . .~
PRELIMINARY
CY7C971
,CYPRESS=============
Switching Waveforms (continued)
MIl Receive Port Three State Timing
RX DV,
'"
""
RX-::'ER
RXD[3:0]
(05-00)
,\ \, \, \,
RV DVVALID
""
\\\\
DATA VALID
\\\\
..
""
7C971-13
MIl Carrier Sense and Collision (lOOBASE-T4)
3
~-: _-+t:_tc_~
t=~
XXXXXX
!cRSLC1,
!cRSLP1
L
COL
!cOLL1
7C971-14
2-20
PRELIMINARY
CY7C971
Switching Waveforms (continued)
MIl Carrier Sense and Collision (lOOBASE.T4)
E
CRS
-------'
EOp, EOC
14----
tCOLL2 - - - - . ,
COL
7C971-15
tCOLH2
MIl Carrier Sense and Collision (lOBASE.T) [28]
COL
_ _ _ _ _ _ _ _- - J
7C971-16
Notes:
28. Switching waveforms show CRS and COL timing for a colision that is
started and terminated by the transmit path (TX_EN HIGH).
2-21
5i
~PRESS=========P=RE==L=IM=1N.=~=R=Y=========CY==7C=9=7=1
Switching Waveforms (continued)
MIl Carrier Sense and Collision (lOBASE.T)
[29]
ITCRSlT
CRS
RX_01±
COL
---3""'"
._
\XXXXXf
7C971·17
MIl Management Port
MOC
MOIO
7C971-18
Control and Status Pins
It:
AUTONEG
ENT4
ENT
ENTFO
ISOOEF
IRS
7C971-19
Notes:
29. Switchingwavefonns show CRS and COL timing for a collision that is
started and terminiated by activity on the receive path.
2-22
PRELIMINARY
CY7C971
Switching Waveforms (continued)
PMA Receiver Interface (MODE = LOW)
CRS
E
--------r---------JI
Q[5:0J
7C971-20
PMA Transmitter Interface (MODE = LOW)
ClKI
D[5:0J
7C971-21
Reference Clock Pins
ClKI
7C971-22
Document #: 38-00415
2-23
CY7B8392
PRELIMINARY
Ethernet Coax Transceiver Interface
• Low power BiCMOS design
• 16·Pin DIP or 28·Pin PLCC)
Features
• Compliant with IEEE802.3 lOBASE5
and lOBASE2
• Pin compatible with the popular 8392
• Internal squelch circuit to eliminate
input noise
• Hybrid mode collision
detect for extended distance
• Automatic AU! port isolation when
coaxial connector is not present
Functional Description
The CY7B8392 is a low power coaxial
transceiver for Ethernet lOBASE5 and
lOBASE2 applications. The device con·
tains all the circuits required to perform
transmit, receive, collision detection,
heartbeat generation, jabber timer and at·
tachment unit interface (AUI) functions.
In addition, the CY7B8392 features an
advanced hybrid collision detection.
The transmitter output is connected di·
rectly to a double terminated 50Q cable.
The CY7B8392 is fabricated with an ad·
vanced low power BiCMOS process. JYpi·
cal standby current during idle is 25 rnA.
Logic Block Diagram
RX+
AUI
DRIVER
AX-
REFERENCE
CIRCUIT
8392-1
HBE
Pin Configurations
PLCC
ThpView
DIP
ThpView
~888§~~
CD+
CDS
CD-
TXO
AX+
AXI
VEE
VEE
RR-
VEE
RX-
TX+
TX-
4 3
VEE (NC)
VEE (NO)
VEE
VEE
VEE (NO)
VEE (NO)
RR+
GND
VEE (NO)
HBE
L.-i'rnrrirnrn'n:j--'
VEE (NC)
VEE
VEE (NC)
VEE (NO)
VEE
VEE (NO)
RR-
8392-2
8392-3
2-24
PRELIMINARY
CY7B8392
Pin Description
Pin Number
16-PinDIP
28-Pin
PLCC
Pin Name
Description
1
2
2
3
CD+
CD-
AUI Collision Output pins. Differential driver that transmit a lO-MHz signal during
collision events, jabber and CD Heartbeat conditions. Also referred to as CI port.
3
6
4
12
RX+
RX-
AUI Receive Output pins. Differential driver that outputs the signal receive from
the line. Also referred to as DI port.
7
8
13
14
TX+
TX-
AUI Transmit Input pins. Differential receiver that inputs the signal for transmission
onto the cable.
9
15
HBE
Heartbeat Enable Pin. When this pin is grounded, the heartbeat is enabled. When
the pin is connected to VEE, the heartbeat is disabled.
11
12
18
19
RR+
RR-
External Resistor. A IK 1% resistor should be connected between these pins to establish proper internal operation current.
14
26
RXI
Receive Input. This pin is connected directly to the coaxial cable.
15
28
TXO
Transmitter Output. This pin is connected directly (lOBASE2 thin wire) or through
a diode to the coaxial cable.
16
1
CDS
Collision Detect Sense. Ground sense connection for the collision detect circuit.
This pin should be connected separately to the shield to prevent ground drops from
altering the receive mode collision detect threshold.
10
16,17
GND
Positive Power Supply Pin.
4,5,13
5-11,
20-25
VEE
Negative Power Supply Pin.
CY7B8392 Description
Long Cable Application
Transmitter
The IEEE 802.3 standard is designed for 500 meters of Ethernet
cable and 185 meters of thin coax cable (RG58NU). To extend
the cable segment to 1000 meters and 300 meters of Ethernet
cable and thin coaxial cable respectively, transmit collision detection mode is required. The disadvantage of ordinary transmit collision detection mode is that it will detect collision only when the
station is transmitting; it will not be able to detect collision of two
far-end stations when it is not transmitting. 1tansmit mode collision detection is not allowed in repeater applications.
The CY7B8392 utilizes a hybrid combination of receive and
transmit collision detection. When the device is not transmitting,
the unit automatically sets the collision threshold voltage to the
smaller (less negative) receive level. This allows collision detection of two far end stations while the unit is not transmitting. If
the unit enters the transmit mode, the collision detection threshold is automatically changed to the larger (more negative) transmit collision detection threshold. This feature eliminates the
need for an external voltage divider at the input of CDS when using the 1000 meters and 300 meters of Ethernet and thin coaxial
cable length, respectively.
Heartbeat Test Function
The Heartbeat Test Function is enabled when the HBE pin is tied
to ground. When enabled, a lO-MHz collision signal is transmitted to the MAC over the CD+(CD- pair after the transmission of a packet for 1O±5BT[11. The Heartbeat function should
be disabled by tying the HBE pin to VEE for repeater applications.
The CY7B8392 transfers Manchester-encoded data from the
AUI port of the DTE (TX + and TX - ) to the coaxial cable. The
output waveform is wave shaped to meet IEEE 802.3 specifications. For Ethernet compatible applications (lOBASE5), an external isolation diode should be added to further reduce the coax
load capacitance.
The AUI squelch circuit prevents signals with less than 15 ns
pulse width or smaller than 225 mV in amplitude from reaching
the output driver. The squelch circuit also turns the transmitter
off at the end of the packet if the amplitude remains less than 225
mV for more than 190 ns.
Receiver
The CY7B8392 receiver transfers the serial data from the coaxial
cable to the DTE via the balanced differential output (RX + and
RX -). The received signal is amplified and equalized by the on
chip equalizer.
The device also contains an internal squelch function that discriminates noise from valid data. A 4-po\e Bessel filter is used to
extract the DC level of the received signal. If the DC level of the
received signal is lower than an internally set squelch threshold,
the CY7B8392 receive function will not be activated.
Collision Detection
The collision detection circuit monitors the signal level on the
coax cable. This signal voltage level is compared against the collision voltage threshold V CD. When the measured signal level is
more negative than VCD, a collision condition is declared by the
CY7B8392 by sending a lO-MHz signal over the CD+(CDpair.
Note:
1. BT = Bit Time = 100 us.
2-25
E
CY7B8392
PRELIMINARY
Jabber Function
The on-chip watchdog timer prevents the DTE from locking up a
network by transmitting continuously. When the transmission exceeds the jabber time limit, the Jabber function disables the
transmitter and sends a lO-MHz signal over the CD± pair. Once
the transmitter is in the jabber state, it must remain in the idle
state for 500 ms before it will exit the jabber state.
AUI Function
The CY7B8392 Auto AUI function will isolate the AUI port
when coaxial cable is not present. Initially, during power-up, the
CI and DI ports ofthe AU! are high impedance. The CY7B8392
monitors the average DC level at the RXI input and determines
if a properly terminated coaxial segment is attached. While RXI
is unterminated the AUI port will remain powered down. The
AUI port will only be activated when RXI is connected to a terminated coaxial segment.
When the RXI input becomes unterminated (after power-up), a
10-MHz signal is transmitted over the CI circuit for 800 ms with
the DI port disabled. After the transmission of the lO-MHz signal, the CI port is disabled.
This function allows multiple MAUs to be connected to a single
AUI port without having to turn off the coaxial transceiver
manually.
Connection Diagram for Standard CY7B8392 Applications
AUI
CABLE
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
r - - ..
2to15VDC
COLLISION
PAIR
,
,
78Q
1- ,,
w
b
NOTE 2
,
,
,
78Q
,
,
,
,
,
,
,
I
,
I
I
I
I
I
I
~
I
TRANSMIT
PAIR
,
,
I
I
I
I
I
,
,
,
+
DC to DC
CONVERTER
9V (ISOLATED)
~100mA
2
16
~II
510Q
510Q
15
510Q
T1 (NOTE 3)
4
5
COAX
13
III
CD+
CD-
1
I
I
~4
,,
L....YEE..
I
,
,
7
I
,
,
I
8
Ilf. l
AX-
78Q
TX+
I
TX-
16
2
AX+ 3
,
NOTE 5
510Q
1
,
,
,
,
,
,
,
,
,
,
~
RECEIVE
PAIR
,
,
,
,
,
,
15
14
CY7B8392
13
5
6
7
8
12
11
10
c;:
CDS
TXO
AXI
I
... NOTE 4
I
.... I
I
I
I
VEE
I
I
RRRR+ lKQ1%
I
I
J
I
I
I
GND
I
I
9~
I
• __ J
'----'
8392-4
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Thmperature with
Power Applied .......................... -O°C to +70°C
Supply Voltage .................................. -12V
Input Voltage .................. GND+0.3V to VEE-O.3V
Operating Range
Notes:
78Q resistors not required if AUI cable not present.
2.
3.
4.
5.
T1 is a 1:1 pulse transformer, with an inductance of 30 to 100 [.tH.
IN916 or equivalent.
Resistors may be as small as 51OQ; larger values may be used to reduce
power dissipation.
2-26
Range
Commercial
Ambient
Temperature
O°Cto +70°C
VEE
-9V ± 5%
CY7B8392
PRELIMINARY
Electrical Characteristics Over the Operating Rangd6]
Parameter
Description
VEE
Supply Voltage
IEE1
(VEE to GND) Non-transmitting[7]
Min.
'!Yp.
Max.
Unit
-8.55
-9.0
-9.45
V
-25
-35
rnA
-70
-80
rnA
IEE2
(VEE to GND) Transmitting
lMAU
Input Bias Current (RXI and Txo pin)
-2
IIDC
1tansmitter Output DC Current
37
ITAC
Transmitter AC Current
VCD
Collision Threshold (Receive Mode)
-1.45
VCS
Carrier Sense Threshold
-0.42
-0.60
V
RX,CD
Differential Output Voltage
±475
±1500
mV
Voc
Common Mode Voltagd 8] (DI and CI ports)
VTS
Transmitter Squelch Threshold[9]
-300
mV
RRXI
Shunt Resistance-Non-transmitting[lO]
100
KQ
RTXO
Shunt Resistance-Transmitting[10]
10
KQ
41
25
!LA
45
rnA
±28
rnA
-1.53
-1.62
V
-3.5
-175
-225
V
Capacitance
Parameter
Cx
Test Conditions
lYP.
Unit
Guaranteed by Design
1.5
pF
Description
Input Capacitance
Notes:
6. Testing is done under test load as defined in AC Thst Loads and
Waveforms.
7. Not including current through external pulldown resistors.
S. During idle, Voc is reduced to minimize the power dissipation across
the load resistors connected to RX± and CD±.
9. For a minimum pulse width of >40 ns.
10. To measure shunt resistance, the pin (RXI or TXO) is terminated toO
volts and the current is measured, then the pin is forced to - 2 volts and
2-27
the current is measured. The resistance is found by:
R = AV =
AI
2V
1(011)
I( -211)
CY7B8392
PRELIMINARY
AC Test Loads and Waveforms
390
TXO
RECEIVER (RX±)
TRANSMITTER - : }
OUTPUT
COLLISION OUTPUT (CD±)
250
Vee
(a)
(b)
8392-5
Switching Characteristics Over the Operating Range
Parameter
Description
Min.
'!Yp.
Max.
Unit
bits
tRON
Receiver Start-Up Delay
2.5
5
tRD
Receiver Propagation Delay
25
50
ns
tRR
Differential Output Rise Time (RX±, CD±)
4
7
ns
tRF
Differential Output Fall Time (RX±, CD±)
4
7
tRJ
Receiver and Cable Thtal Jitter
tTST
1tansmitter Start-Up Delay
ns
ns
±2
1
2
bits
tTD
1tansmitter Propagation Delay
25
50
ns
tTR
1tansmitter Output Rise Time (TXO)
20
25
30
ns
tTF
1tansmitter Fall Time (TXO)
20
25
30
ns
tTM
tTR and tTF Mismatch
±0.5
±3
ns
tTS
1tansmit Skew (TXO)
±0.5
±2
ns
tTON
1tansmit Thrn-On Pulse Width at VTS (TX±)[llJ
10
20
40
ns
tToFF
1tansmit Tum-Off Delay
130
200
300
ns
tCON
Collision Tum-On Delay
7
13
bits
tCOFF
Collision Thm-Off Delay
20
bits
fco
Collision Frequency
8.5
10
12.5
MHz
tCD
Collision Pulse Width
40
50
60
ns
tHaN
CD Heartbeat Delay
0.6
1.1
1.6
lIS
tHW
CD Heartbeat Duration
0.5
1.0
1.5
J.ls
tJA
Jabber Activation Delay
20
26
32
ms
tJR
Jabber Reset Time Out
300
420
550
ms
Note:
11. For a minimum pulse amplitude of > 300 mV.
2-28
PRELIMINARY
CY7B8392
Switching Waveforms
Receiver Timing
Ir-----~,~<------------
INPUT
TORXI
)4-----
RX+
IRON
E
-----II
RX8392-6
Transmit Timing
~
TX+
TX....- - - ITOFF
----.t
r-------~,~'------~1rr--------
TXO
OUTPUT
ITF
6392-7
ITR
Heartbeat Timing
TX+
TX-
lJ1JU1""'.0---- \~~--~----~---IHON - - -....- - - - - -
CD+
CD8392-8
Collision Timing
INPUT
TORXI
OV
-1.75V---...p.--..:.:;,~...:...--...,/
_--------------______-:-~1.:!2V
(min) #
"7---:'-------:-1':"'""1Veo
~.:.:::.::..Zj:I_=----
r- ... --
leo
-6 BV
tcOFF'~
CD+
CD8392-9
Jabber Timing
TX+
TXTXO
CD+
CD-
-------«XX~X-x-xxx=\r-----.61
6392-10
2-29
PRELIMINARY
Ordering Information
Ordering Code
Package
Name
Package 'JYpe
CY7B8392-JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7B8392-PC
P1
16-Lead (300-Mil) Molded DIP
Document #: 38-00430-B
2-30
Operating
Range
Commercial
CY7B8392
CY7B4663
PRELIMINARY
Integrated lOBASE-FL
Ethernet Transceiver
Features
• Single chip Ethernet solution
• Complies with IEEE 802.3
10BASE-FL standard
• Pin compatible with the popular 4663
• 110 mA LED current drive capability
• AUI interface allows both
transformer and capacitive coupling
• Requires single 5 volt ± 10% supply
• No external crystal or clock required
• Five network status LED pins
• 28 pin PLCC package
• 1 MHz idle signal, Jabber function,
and SQE Test with enable/disable
function integrated on chip
• Receive squelch function
• Integrated data quantizer
• Low power BiCMOS design
Functional Description
The CY7B4663 is a single chip solution
low power fiber optic transceiver for
lOBASE-FL applications. The
CY7B4663 complies with IEEE 802.3
standards for fiber optic Ethernet.
The CY7B4663 has a current driven output which drives the fiber optic LED
transmitter with a maximum current of
Block Diagram
110 mA. The transmitter automatically
inserts a 1 MHz signal during idle time.
The 1 MHz idle signal, Jabber function,
and SQE test are all internal functions of
the chip. The receiver contains a data
quantizer capable of accepting input signals as low as 2mVp_p with a 55dB dynamic range.
The CY7B4663 is fabricated using an advanced, low power BiCMOS process. Typical standby current during idle is 35 rnA.
+5V
SQEN/JABO
TX+
TX-
TXOUT
LED
DRIVERS
=
RECEIVE
SQUELCH
CO+
CO-
VtN+
VIN-
RX+
RX-
Voc
VAEF
VTHADJ
RRSET
LBDIS
CrlMER
+5V
784663·
11
2-31
E
PRELIMINARY
CY7B4663
Pin Descriptions
CY7B4663
Pin Number
1
Name
CLSN
Description
Active low LED driver which indicates that a collision is occurring. The collision event is
extended with an internal timer for visibility.
2
3
CD+
CD-
AUI collision output pins. Differential driver that transmits a 10 MHz signal during collision events, jabber, and CD Heartbeat conditions. Also referred to as CI port.
4
5
CTIMER
SQEN/JABD
6
7
RX+
RX-
Tying a capacitor from this pin to Vee determines the Link Monitor response time.
SQE Test Enable, Jabber Disable. Tying this pin low disables the SQE test, tying higb enables the SQE function. When tied between 1.5V and Vee- 2.0V both the SQE test and
Jabber are disabled.
AUI receive output pins. Differential driver that outputs the signal received from the fiber
optic. Also referred to as the DI port.
8
LBDIS
Loopback Disable. Tying this pin to VCC disables the loopback function. The AUI transmit pair data is not looped back to the AU I receive pair and the collision function is disabled. Tying this pin to ground or leaving it floating enables the loopback and collision
functions.
9
10
Vee
TX+
TX-
+ 5 volt supply.
AUI Transmit Input pins. Differential receiver that inputs the signal for transmission onto
the cable.
Sets the current level driven by the transmitter
A 1% 61.9 ill resistor tied to Vee sets the proper internal operating currents
Active low LED driver indicating the Link Monitor status. If there are transitions on
RXIN ± indicating an idle signal or a packet transmission this pin will be pulled low. The
threshold for input sensing by the Link Monitor circuitry is set with the VTHADJ pin.
Active low LED driver which indicates that a transmission is occurring. The event is extended with an internal timer for visibility.
Active low LED driver that indicates the transceiver is receiving a frame from the optical
receiver. The event is extended with an internal timer for visibility.
11
12
14
RTSET
RRSET
LMON
15
XMT
16
RCV
17
18
19
20
VeeTX
TXOUT
GND
GND
+ 5 volt supply for LED driver.
Fiber optic LED driver output.
Ground Reference
21
VDe
Tying a capacitor from this pin to ground alters the DC feedback loop pole. The value of
this capacitor should be at least ten times larger than the input coupling capacitors.
22
23
24
25
26
VREF
A 2.5V reference.
Input pin which sets the link monitor threshold.
Ground Reference
These pins are capacitively coupled to the fiber optic receiver.
27
Vee
JAB
13
28
VTHADJ
GND
VINVIN+
+5 Volt Supply
Active low LED driver. When Jabber occurs this pin is low to indicate the Jabber status.
CY7B4663 Description
The CY7B4663 contains:
1. Transmitter which drives the fiber optic LED.
2. Receiver with integrated quantizer which takes data from the
fiber optic receiver module and passes it to the AUI.
3. AUI (Attachment Unit Interface) which consists of three signal
pairs: the transmit pair, receive pair, and the collision pair.
4. Fiber media link monitor function with link status LED.
5. Collision, Loopback, Signal Quality Error (SQE) , and Jabber
functions.
6. Five chip/system status LED pins with 10 rnA nominal drivers.
Transmitter
The CY7B4663 transfers Manchester-encoded data from the
AUI port of the DTE (TX + and TX - ) to the fiber optic media.
The output meets IEEE 802.3 specifications for fiber optic
Ethernet.
The fiber transmitter detects data on the TX± input and passes
this data to the fiber media. If TX + is positive with respect to
TX-, then TXOUT is high impedance and no current flows
through the transmitter. When TX + is negative with respect to
TX - then TXOUT will sink up to 110 rnA of current into the
2-32
iL~
PRELIMINARY
CY7B4663
JfCYPRESS~~~~~~~~~~~~~~~~~~~
CY7B4663 and the fiber LED transmitter will light up. When in
the non-transmitting state the CY7B4663 will transmit a 1 MHz
link signal over the fiber network to maintain link integrity.
In order for data to be transferred from the AUI TX± inputs to
the fiber output it must meet the squelch requirements for the
DO pair. The squelch circuit prevents noise from reaching the
LED driver. The circuit rejects signals with pulse widths less than
15 ns or smaller than (typically) 225 mY. After TX unsquelches it
looks for the start of idle signal before turning on the squelch
again. If tbe TX± signal exceeds 225 mV for more than 190 ns
the squelch circuitry is turned on and the transmitter disabled.
Receiver
The CY7B4663 receiver has an integrated data quantizer which
takes data directly from the fiber optic receiver. This data is sent
out on the AUI over the RX± pins.
The device also contains an internal squelch function that discriminates noise from signal. The receive squelch will reject frequencies lower than 2.5 MHz, or any signal if the link monitor
function indicates a link loss. When in the unsquelched state the
receive circuitry looks for the start of idle signal. Any signal which
exceeds 160 ns without transition will send the receiver into
squelched state and the start of idle signal will be sent over the
RX± AU! driver.
The VrnADJ pin can be used to adjust the sensitivity of the receiver. For 1OBASE-FL VTHADJ can be tied directly to VREF
and achieve a bit error ratio of less than 1.0 X 10- 9. If greater
sensitivity is desired a voltage divider can be used to adjust
VrnADJ. The relationship between VTHADJ and VTH is:
VTHADJ
= 408VTH
AUI Function
The AUI consists of three pairs of signals: TX±, RX±, and
CD±. Manchester encoded differential data is sent from the
MAC to the TX±. In the case of an external Medium Attachment Unit (MAU) the data is AC coupled through either an
isolation transformer or through isolation capacitors. If the transceiver is internal the part may be either AC or DC coupled. Valid
data from the fiber optic media is sent from the RX± differential
pair to the DTE. In the case of a collision or Jabber the CD±
drivers will send a signal to the MAC.
The AUI drivers are capable of driving a full 50 meters of AUI
cabling. They have a typical rise and fall time of 4 ns. The RX±
and CD± differential output voltage is minimized during idle
time to prevent standing current in the isolation transformer.
Link Monitor Function
The link monitor function monitors the input signal voltage level
and determines if it falls below a preset level. If the input voltage
falls below a preset level the CY7B4663 enters the Low Light
state. In this state the transmitter sends out the IMHz link signal,
but all data received at TX± is ignored. In addition, the loopback
function and the receiver are disabled and the LMON LED pin
goes high. Th switch back to the Link Pass state the link monitor
threshold must be exceeded by 20%. Once the CY7B4663 returns to Link Pass it waits 250ms to 750ms and then checks if
TX± is idle and no data is being received before re-enabling the
transmitter, loopback, and receiver, and bringing the LMON pin
low.
Collision
with a worst case 45/55 or 55/45 duty cycle. The collision signal is
also activated during Jabber and at the end of packet for the SQE
test.
Loopback
The CY7B4663 loopback function sends the transmit data from
the DTE back over the AUI receive pair, RX±. Loopback can be
disabled by tying LBDIS to Vee. This allows the chip to act as a
full duplex transmitter and receiver with collision detection disabled.
Heartbeat Test Function (SQE Thst)
The Signal Quality Error (SQE) / Heartbeat function is enabled
by tying the SQEN pin to Vee. When enabled, a 10 MHz collision signal is transmitted to the MAC over the CD± pair after
the transmission of a packet. The transmission lasts 1O±5 BT.
The heartbeat function should be disabled by tying the HBE pin
to ground for repeater applications.
Jabber Function
The on chip timer prevents the DTE from locking up a network
by transmitting continuously. When the transmission exceeds the
jabber time limit, the Jabber function disables the transmitter
and sends a 10 MHz signal over the CD± pair. Once the transmitter is in the jabber state, it must remain idle for 500 ms before
it will exit the jabber state. The 1 MHz idle signal will be transmitted during jabber regardless ofthe transmitter being disabled.
The jabber function is enabled by tying the SQEN/JABD pin to
either VCC or ground. The function can be disabled by tying the
pin between 1.5V and Vcc-2Y.
LED Drivers
The CY7B4663 provides five LED status drivers. The LED drivers are active low, and the LEDs are normally off except for the
LMON pin, which remains on until link is lost. The pins are tied
to Vee through the LED and a series 500n resistor.
Because the transmit, receive, and collision events occur so rapidly, the XMT, RCV; and CLSN pins have event extenders on them.
The extenders allow the event to be visible. Whenever a transmission, reception, or collision occurs the respective pin will be visible for a typical period of 16 ms. If the event is repeated before
the 16 ms period expires, the timer is reset and the LED timing
period is restarted. The JAB and LMON LEDs do not have event
extenders because they occur for a long enough period to be visible to the user.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested)
Storage Temperature .................. -65·C to +150·C
Ambient Temperature with
Power Supplied ....................... -55·C to + 125·C
Supply Voltage to Ground Potential ........ -O.SV to +7.0V
DC Input Voltage ....................... -0.5V to + 7.0V
Output Current
TXOUT ...................................... 110 rnA
Input Current _ _ _ _ _ _ _ _ _ _ _ __
RRSET, RTSET, JAB, CLSN, XMT, RCV;, LMON ... 60 rnA
Operating Range
If the transceiver is both receiving data and transmitting at the
same time the collision AUI outputs will be activated. The collision ports will not be activated when the loopback is disabled.
The collision signal consists of a 10 MHz -15%/+25% signal
2-33
Range
Ambient
Temperature
Vee
Commercial
O·Cto +70·C
5V ± 10%
E
~~YPRESS;;;;;;;;;;;;;;;;PRE;;L_IM~IN~~~R~Y;;;;~CY~7B~4~66~3
+5V
+5V
0--,-,-,.-.-...,.-.......- .....
1620
Nlin~~n~~,.L..!L...1,12
16
TXOUT~1"'8~------_....:;1--l
TXVeeI-'-'17_ _~
+5V
LBOISI-"'--....._
O.5pF
CY7B4663
CnMEA 4
Voc
21
f--o
t-:t
"1-
FIBEROPTlC
TRANSMITTER
+5V
+5V
O.1I1F .".
F ..11........l
:...
V'N+ j-='26=-_ _--'.:::01:t:
c
lOll
FIBER OPTIC
4
V,N .. ~25~_ _ _ _-'.~01~II!:.F~I---l ~5
ABO
Vee
6k1l
+5V~
!
10kll
O.23jl
7B4663-
12
Figure 1. CY7B4663 Schematic Diagram
2-34
Electrical Characteristics
Min.
'!Yp.
Max.
4.5
5.0
5.5
V
Power Supply Current Non -1i"ansmitting
35
50
rnA
Iccz
Power Supply Current 1i"ansmitting
80
100
rnA
VOL
LED Driver Low Voltage (IOL =lOrnA)
0.8
V
ITXP
1i"ansmit Peak Output Current
110
rnA
VTS
1i"ansmitter Squelch Voltage (TX±)
300
mV
VIC
Common Mode Input Voltage (TX±, RXlN±)
RX,CD
Differential Output Voltage
Description
Parameter
VCC
Supply Voltage
ICCl
175
Voc
Common Mode Output Voltage (RX±, CD±)
VIMB
Differential Output Voltage Imbalance
225
2
Vcc-0.5
V
±500
±1200
V
±40
mV
0.3
V
Vcc-2
V
2.5
VSQED
SQE Thst Disable Voltage
VJD
Jabber Disable Voltage
VSQBE
SQE/Jabber Both Enabled
Vcc-0.5
VLBD
LBDIS Disable Threshold
Vcc-1
VLBE
LBDIS Enable Threshold
Vcrx
Common Mode Voltage (TX±)
3.5
VClN
Common Mode Voltage (VIN +, YiN - )
1.65
VREF
Reference Voltage
VRSC
VREF Output Source Current
GAMP
Input Amplifier Gain
VISR
Fiber Input Signal Range
1.5
External Voltage at VTHADJ to Set VTH
VIOP
Input Offset (VDC
Input Referred Noise (50 MHz BW)
RIN
Input Resistance VIN±
V
V
2.45
0.5
V
2.55
V
5
rnA
1600
mVp_p
VN
2.7
3
25
ITHADJ
Input Bias Current of VTHADJ
Threshold for Switching from Link Fail to Link Pass
Hysteresis of Link Fail to Link Pass
IlV
kil
2.0
-200
0
200
jlA
5
6
7
mVp_p
20
2-35
V
mV
1.3
0.8
VLP1V
V
V
100
2
= VREP)
VIRN
V
1
2.35
VSET
Units
%
I
AC Electrical Characteristics
Min.
1YP.
Max.
Units
tTXNPW
1tansmit Thm On Pulse Width
10
20
40
ns
tTXFPW
1tansmit Thm -Off Pulse Width (TX to idle transitions)
500
tTXLP
1tansmit Loopback Startup Delay
Description
Parameter
tTXODY
1tansmit Thm-On Delay
tTXIDF
1tansmit Idle Frequency
0.85
tTXDC
1tansmit Idle Duty Cycle
45
tTXSDY
1tansmit Steady State Propagation Delay
tTXI
1tansmitter Jitter Into 31 n
tRXSFf
Receive Squelch Frequency Threshold
15
2.5
2000
ns
400
ns
100
ns
1.25
MHz
55
%
50
ns
±1.5
ns
4.5
MHz
150
ns
tRXODY
Receive Thm-On Delay
tRXFX
Last Bit Received Th Slow Decay Output
tRXSDY
Receive Steady State Propagation Delay
tRXJ
Receiver Jitter
tAR
Differential Output Rise Time (RX±, CD±)
4
tAF
Differential Output Fall Time (RX±, CD±)
4
7
ns
tCPSQE
Collision Tum-On Delay
300
ns
tSQEXR
Collision Thm-OffDelay
650
ns
tCLF
Collision Frequency
8.5
11.5
MHz
tCLPDC
Collision Pulse Duty Cycle
45
50
55
%
tSQEDY
SQE Test Thm -On Delay After 1tansmission
0.7
1.1
1.5
lls
tSQETD
SQE Test Duration
0.6
1.0
1.4
tJAD
Jabber Activation Delay
20
26
32
l1S
ms
tJRT
Jabber Reset Time Out
300
420
550
ms
tJSQE
Delay From Outputs Disabled to Collision Oscillator On
tLED
Rev, CLSN, XMIT On Time
32
ms
10
l1S
ms
tLLPH
Low Light Present to LMON High
tLLCL
Low Light Clear to LMON Low
230
300
15
ns
50
ns
7
ns
±1.5
ns
100
8
16
3
5
250
2-36
ns
750
=r-.-,-,~CYPRESS
PRELIMINARY
CY7B4663
===============
TX+
TXTXOUT._ _ _+-_----'
RX+
RX- - - - - - - {
784663-13
Figure 2. Transmit and Loopback Timing
VIN+
VIN-
RX+
RX784663-14
Figure 3. Receive Timing
TXOUT
~
\
~- X
VIN+
.,";0
VINCD+
CDRX+
RXVIN+
VIN-
TXOUT
CD+
CD-
/
Tx
=x
X
Tx
X
~i
tCPSQE
~
VALID
X
DATA
eSD
Rx
DATA
/
c=x
eSD
\
/
\
X
X
X
X
X
X
X
X
X
X
X
'£
\
/
r
X
X
\
X
Rx
Figure 4. Collision Timing
2-37
'I:..
784663·15
~YPRESS:=:=:=:=:=:=:==P=nE:=L~IM~IN~~~R~Y:=:=~CY~7B~4:66~3
VIN+
VINTXOUT
CD+
CDRX+
RX-
=>
'/
J
/
-tSOEXR-1
X
eso
~
/
\
/
\
)
X
Rx
X
Tx
X
Tx
Tx
)
784663-16
Figure 5. Collision Timing
TXOUT
VIN+
VIN-
=>r
l ------------------=x
X
x~_~X~_~)r-----------VALID
DATA
l-tsaExR-1
eso X
Jr----------
CD+
CD-
J
RX+
RX-
__
R_X1N_----JX
X
RXIN
RXI.
X
X
RXIN
Axl.
)r--------
1
tcLF-
x
CD+
CD-
~----------784663-17
Figure 6. Collision Timing
TXOUT
--cJ\
VALID DATA
)r-------------------tsaETD -
~~,~f
CD+ ---------~( --e-sD---~)r------CDFigure 7. SQE Timing
784663-18
2-38
~~YPRESS~==============PRE==L=IM==IN=~=R=Y====~C~Y~7B~4~66~3
TX+
TX-
---~~ 'ffi __~I
---11 ~~~~ 1
TXOUT _ _ _ _ _ _
~------L-------
I
--I I=--Lt.JSQE
CD_----------~(~____
CD+
C_SO_ _ _ _ _
lr--------
Figure 8. Jabber Timing
TXOUT
784663-19
([J]])
~--14
XMT
'LED
--+I
r------------------------
1
VIN+
VIN-
([J]])
([J]])~-----------------------
~14-tLED~~1
~--------------------I
~
VIN+
:~j-J:~
784663-20
Figure 9. LED Timing
Document #: 38-00508
2-39
CY7B8392 Low Power Ethernet Coaxial
Transceiver Application
Figure 2 displays an example of Manchester encoding. Instead of straight binary encoding, each bit period is divided into two equal intervals. To send a
one, the voltage is HIGH (ground) for the first half
of the interval and LOW ( - 2.0 V by IEEE 802.3) for
the second half of the interval. In the case of a binary
zero the reverse is true, the first half of the bit period
the signal is LOW and HIGH the second half.
This application note describes the differences between the lOBASE5 (Ethernet) and lOBASE2
(Cheapernet) versions of the IEEE 802.3 standard,
and provides guidelines for design with the
CY7B8392.
Introduction
Data is sent out over the network in packets. An
Ethernet packet consists of the preamble, destination address, source address, length field, data, and
a Cyclic Redundancy Check (CRC). Each packet
can be viewed as a sequence of 8-bit bytes, with the
least significant bit of each byte being transmitted
first. A typical Ethernet packet is shown in Figure 3.
The preamble contains 8 bytes of alternating ones
and zeros, ending with two consecutive ones. The
preamble allows the receiving PLS to synchronize
its clock with the sender. The two consecutive ones
at the end of the preamble signify the start of frame
packet and are sometimes referred to as the Start of
Frame Delimiter. The destination address is a 6-byte
The CY7B8392 is a physical layer device used to
transmit data over a shared coaxial medium. It functions as specified by the IEEE 802.3 standard.
Figure 1 shows a block diagram of a single network
node. The MAC (Media Access Control) is responsible for framing data and controlling its transmission and reception on the network. When transmitting the MAC sends NRZ data to the Physical
Signaling (PLS) Layer. The PLS processes the
MAC sub layer data, setting the signaling rate and
translating the NRZ data to Manchester Encoded
Data, and sends it to the transceiver.
-
STATION OR DTE
I
S
0
B
U
S
-
MAU
L
I-
PHYSICAL
MAC
SUBLAYER ~ SIGNALING
LAYER
A
OPTIONAL
AUI
CABLE
T
I
(USED IN
10BASE5)
~
0
N
I+-
I
CY7B8392
COAXIAL
TRANSCEIVER
INTERFACE
DC-DC
CONVERTER
Figure 1. Block Diagram of Single Network Node
2-40
1-1
cp,
,
,
,
,
,
,
,
,
-----
COAXIAL
CABLE
CY7B8392 Low Power Ethernet Coaxial
i~YPRESS~~~~~~~~~~~~~1r~a~n~sc~e~iv~e~rA~pp~l;ic=a;ti;on~
o
o
o
o
o
o
MANCHESTER ENCODED DATA
NRZDATA
Figure 2. Manchester Encoding
field that specifies the station(s) to which the packet
is being sent. Every station examines this field and
determines whether it should accept the packet. The
high-order bit of the destination address is a zero for
ordinary addresses and one for group (multicast)
addresses. Group addresses allow multiple stations
to listen to one address. The source address is a 6 byte
field that contains the unique address of the station
that is transmitting the packet. The length field is
used to determine how many bytes are in the data
field. This is necessary because IEEE 802.3 dictates
the data portion of a packet must be a minimum of
46 bytes. If the data portion of a packet is less than
46 bytes, it is padded with random bits until it is the
legal size. The length field is used to notify the controller which part of the data field is valid. The data
field contains an integral number of bytes ranging
from 46 to 1500. The CRC field contains code that
checks on the integrity of a packet.
up to 500 meter lengths of RG-8 coaxial cable to be
used in lOBASE5 applications. lOBASE2 (Cheapernet) uses a thin, flexible cable which can be directly attached to the DTE or a Medium Attachment
Unit (MAU). A maximum of 185 meters of cable is
allowed when using lOBASE2. Figure 4 and Table 1
show the differences between Ethernet and Cheapernet (sometimes referred to as Thinnet).
Table I. Comparison of IOBASE5 and IOBASE2
Media
IOBASE5
IOBASE2
RG-8
Cable type
RG-58NU
Maximum cable
length
Maximum
network length
Attachments per
segment
Attachment
spacing
Topology
lOBASE5/10BASE2 Ethernet Network
IEEE 802.3 standard allows for two different versions of coaxial data transmission, 10BASE5 and
lOBASE2. 10BASE5 (Ethernet) uses thick coaxial
cable with transceivers directly attached to the cable
network. Because of the inflexibility of the thick coaxial cable an AUI drop cable is needed to electrically connect the Ethernet transceiver to the Data
Terminal Equipment (DTE). IEEE standard allows
500 meters
185 meters
2500 meters
925 meters
100
30
2.5 meters
0.5 meters
Linear bus
Linear bus
Due to the inflexibility of the thick coaxial cable it is
difficult to bring the cable directly to the DTE. To
solve this problem an AUI drop cable is used in
10BASE5 applications. The AUI cable consists of
four individually shielded twisted pairs with an overall shield covering these pairs. The twisted pairs
SINGLE PACKET --------+~ I
III(
PREAMBLE
8 BYTES
DESTINATION
ADDRESS
6 BYTES
SOURCE
ADDRESS
LENGTH
DATA
CRC
6 BYTES
2 BYTES
46-1500
BYTES
4 BYTES
PREAMBLE DESTINATION
ADDRESS
8 BYTES
6 BYTES
Figure 3. 1Ypical Ethernet Packet
2-41
SOURCE )
ADDRESS
6 BYTES ()
£2.
~
CY7B8392 Low Power Ethernet Coaxial
£ /CYPRESS ==============Tr=a=n=sc=e=iv=e=r=A:!::p~p=li=ca=t=io=n==
THICK COAX
RG-8
STANDARD'T'
COAX CONNECTOR
I
TRANSCEIVER
RG58NU
I
AUIDROP
¥"" CABLE (UP TO
50 METERS)
MAU
(MEDIUM
ATTACHMENT UNIT)
ORDTE
DTE
(DATA TERMINAL
EQUIPMENT)
Figure 4. Ethernet vs. Cheapernet
pairs are shown in Table 2. AUI drop cable is typically not used in lOBASE2 applications because the
thin coaxial cable is flexible enough to be directly attached to the DTE.
have a characteristic impedance of 78 ±5Q. The
cable can be up to 50 meters in length. The individual shields should be connected to logic ground while
the outer shield should be connected to chassis
ground. The signal assignments for the AUI twisted
Table 2. AUI Interface Signal Assignments
Signal
Description
Pins
1
Control In circuit Shield
Shield for CD± twisted pair
2
Control In circuit A
CD+ signal
3
Data Out circuit A
TX+ signal
4
Data In circuit Shield
Shield for the RX± twisted pair
5
Data In circuit A
RX+ signal
6
Voltage Common
7
No Connect
8
No Connect
9
Control in circuit B
CD- signal
10
Data Out circuit B
TX- signal
11
Data Out circuit Shield
Shield for the TX± twisted pair
12
Data In circuit B
RX- signal
13
Voltage Plus
Voltage supply from DTE
14
Voltage Shield
15
No Connect
2-42
CY7B8392 Low Power Ethernet Coaxial
22~YPRESS~~~~~~~~~~~~~n~a~n~sc~e~iv~er~A~p~p~l~iC~at~io~n=
Manchester encoded signal from the cable and
sends differential data to the DTE.
It is possible, through the use of repeaters, to combine several networks together. These networks can
be a single Physical layer, i.e., only lOBASE2 or only
lOBASE5, or it can by a combination of many different Ethernet physical layers. The maximum length
of a lOBASE5 network using repeaters is 2500 meters, while the maximum length of a lOBASE2 network with repeaters is 925 meters. Figure 5 shows a
combined network with both Ethernet and Cheapernet connected through repeaters.
In order to visualize the operation of a lOBASE system using the CY7B8392, we will follow a signal
from transmission to reception. When the DTE decides to send a packet, the controller sends NRZ
data to the SNI, which in turn sends differential
Manchester encoded data through an isolation
transformer to the CY7B8392. The transceiver and
the coaxial network must be electrically isolated
from all external signals. The isolation is required to
be 500 VAC for lOBASE2 and 2000 VAC for
lOBASE5. This isolation can be performed using
three pulse transformers, which are available in
16-pin DIP and 16- or 12-pin surface mount packages available from several manufacturers (Pulse
Engineering, Valor Electronics, Bel Fuse). After the
differential signal passes through the transformer it
is received at the TX± ports of the CY7B8392. This
CY7B8392 Signal nansmissionl
Reception
During transmission, differential Manchester encoded data is sent to the CY7B8392 from the DTE.
This data is shaped to meet IEEE signal requirements and sent out single-ended onto the coaxial
cable. Conversely, when the transceiver is receiving
data from the coaxial cable it takes single-ended
WORD
PROCESSOR
TAPE
BACKUP
T
T
.......
50 OHM TERMINATOR
TRANSCEIVER/MAU
t
10BASE2 RG58 NU
Figure 5. Combined Ethernet and Cheapernet Network
2-43
E
-=..
CY7B8392 Low Power Ethernet Coaxial
-:S~YPRESS~~~~~~~~~~~~~Tr~a~n~Sc~e~iv~er~A~pp~l~ic~a~ti~on~
signal must have an AC signal amplitude greater
than - 225 mV and a pulse width of more than 15 ns.
If these values are not met, the transmitter squelch
circuitry will not allow the signal to reach the output
driver. The differential signal is sent to a comparator
with hysteresis. Every differential voltage crossing flips
the output ofthe comparator which triggers the internal
waveform shaping circuitry. The waveform shaping circuitry, feeds a current amplifier which sinks 10 mA
(LOW) and 75 mA (HIGH) into the TXO port. Because
the network appears as a 25Q load (two 50Q resistors
in parallel), this translates to a single-ended voltage
swing of -0.25V to -1.875V at TXO.
filter characteristics of the cable can induce a significant jitter by attenuating the higher frequencies
more than the lower frequency signal content. The
maximum system jitter allowed by IEEE 802.3 standards is ±7 ns. Minimizing jitter allows the MAC
sub layer devices to accurately process data received
from the CY7B8392. If the jitter is too great then the
bit error rate may increase above acceptable levels.
Collision Detection
Because lOBASE2 and lOBASE5 transmit over a
shared medium, it is necessary to detect instances
where two or more stations are transmitting at the
same time. This is known as collision detection.
By IEEE 802.3 specifications, the DC offset of the
output driver should be between -37 rnA and -45
mA. The AC swing should be from ± 28 mA up to the
offset value. This current drive limit must be met
even in the case of one other unit transmitting on the
network. The 10-90% rise/fall times must be 25 ±5
ns at 10 Mb/s and they must match within 2 ns.
There are two standard types of collision detection,
receive and transmit. Both modes compare the average DC voltage on the coaxial cable with respect
to ground and determine if a collision is occurring
between two transmitting stations.
In receive mode collision detection, any collision between two separate transmitting nodes will be detected by the transceiver when the average DC cable
voltage with two nodes transmitting is from -l.4V
to -1.58V. The CY7B8392 and all competition devices have a set internal collision detection voltage
that falls into this collision window. IEEE 802.3
standards require receive mode collision detection
in applications where repeaters are used. This is
done to limit the round trip signal delay to 50 ~s, ensuring that all stations on the network will detect a
collision before the end of a minimum length packet
(57.6 ~s). The allowable cable lengths using receive
mode collision detection are 185 and 500 meters for
lOBASE2 and lOBASE5, respectively.
On the other end of the network data is received
from the coaxial cable at the RXI port. The signal is
the equalized and amplified before being sent out of
the RX± ports. Due to the low pass characteristics
of the coaxial cable, equalization of the signal is necessary before it can be amplified and sent to the
DTE. The CY7B8392 receiver circuitry has a high
pass filter which compensates for the cable characteristics and sends equalized differential Manchester encoded data to Physical Signaling Layer
through the RX± ports. In addition to the equalizer, the receiver has a carrier sense feature which
will reject signals with less than 467 mV DC content.
Figure 6 depicts CY7B8392 transmission and reception over the network.
In transmit mode collision detection a collision between two stations will be detected while the transceiver is actively transmitting (i.e., it is one of the
two colliding stations). Competition 8392 parts require an external voltage divider at the CDS input
in order to implement transmit collision detection
mode. The voltage divider is used to give the CDS
pin a DC offset of approximately - 250 mV. Because
collision is detected as the voltage difference between the RXI and CDS pins, this allows the coaxial
cable to fall 250 mV lower than the receive mode
threshold before collision is detected. The relaxed
JITTER
A characteristic of transmission over a coaxial network is system jitter. Jitter is defined as the short
term variations of a digital signal from its ideal position in time. In other words, a clock may be expected
to have a rising edge at time t=O, but instead the rising edge occurs slightly after or before t=O. Jitter
can be caused by many parts of a network such as
source clock imperfections, cable distortion, etc. If
the length of the network is large then the low pass
2-44
CY7B8392 Low Power Ethernet Coaxial
22~YPRESS~~~~~~~~~~~~~1r~a~n~sc~e~iv;er~A~pp~l~ic~a~ti~on~
...-----,{EXAGGERATED LENGTH FOR DEMO PURPOSE ONI.:
TXO~~---------------------------r~
CY7B8392
c-t-------tTX+
1:...f------tTX-
-,.wrY
-1.725V
m
1
E
RG-58A/U
COAX
1-- 1 -+- 0 -+- 0 -1
CY7B8392
~-----,RX+
TXO~~--------~~---------------r~
1:...f------tRX1 :1 Isolation
Transformer
1
OV~-------------------
-3V
-4V
Figure 6. CY7B8392 Transmission and Reception over the Network
upper limit allows longer cable lengths to be used.
Transmit mode collision detection allows 300 and
1000 meters of coaxial cable to be used with
lOBASE2 and 10BASE5, respectively.
In the case of transceivers with receive collision
detection, a separate board is required for repeater
and long cable applications. Thus, the CY7B8392
Hybrid collision detection is a more flexible solution
than the competition's collision detection techniques.
The collision detection offered only by the
CY7B8392 is hybrid coUision detection, a combination of receive and transmit mode collision detection. When the CY7B8392 is not transmitting, it automatically sets the collision threshold voltage to
the smaller (less negative) receive level. If the unit
enters the transmit mode, the collision detection
threshold is automatically changed to the larger
(more negative) transmit mode. Hybrid collision
detection allows extended cable lengths to be used
in non-repeater applications without an external
voltage divider at the CDS pin. It can also be used
in repeater applications with regular cable lengths
without redoing the board design.
CY7B8392 Heartbeat Function
The CY7B8392 Heartbeat function is enabled when
the HBE pin is tied to GND (OV). When enabled,
a 10 MHz collision signal is transmitted to the MAC
over the CD± pair after the transmission of a
packet. For repeater applications the Heartbeat
function can be disabled by tying the HBE pin to
VEE (-9V). Additionally, if the HBE pin is raised
to approximately a TTL level above ground (l.OV
nominal) the 8392 enters the test mode state. In the
test mode state the Jabber timer, which controls
datasheet parameters TJA and TJR, is accelerated by
2-45
~
--
CY7B8392 Low Power Ethernet Coaxial
~YPRESS~~~~~~~~~~~~~~Tr~a~n~sc~e~iv~e~r~A=p=p~li~ca~t~io~n=
212. This allows accelerated testing of these parameters in production.
Do not place power and
,- 10
10
10
1
0
Designing a lOBASE5 MAU with the
CY7B8392
1
10
When designing an Ethernet board electrical isolation of both the signal and power supply is necessary. AUI signal isolation is easily achieved through
the use of a pulse transformer at the AUI ports.
Power isolation is achieved using an isolated DCDC converter which is required to take the
12V -15V DTE supply as an input and provide a
-9V nominal output. To step down the voltage, a
transformer is used, which also supplies the required isolation characteristics. For a detailed DCDC converter design see the section on power supply design in this application note.
1
-,---,--'---,--
COSO
nco
~'--'--JL:""
RlEIO...l----'-'-'"
• -I
0
1
0 1
0 CYB83920
10
1
+ ground planes near RXI and TXO.
0
1
0 1Keep RXI and TXO as
0 .J
L _____
1
short as possible
Figure 7. CY7B8392 Application (not to scale)
A controlled breakdown path is required that will
shunt high-energy transients to an effective ground.
This controlled breakdown is required to meet the
isolation requirements outlined in the IEEE S02.3
standard. In addition, the standard also requires
that all applications provide an adequate radio frequency ground return path. These requirements
can be met by connecting a 1 MQ, 0.25W resistor and
a 0.01 f-tF capacitor in parallel. The resistor provides
the static discharge path while the capacitor ensures
low susceptibility to magnetic interference. Figure 8
shows a typical CY7BS392 lOBASE5 application
with heartbeat disabled.
Careful consideration should be taken when designing the MAU printed circuit board. According to
IEEE S02.3, a total of 4 pF of capacitive loading is
allowed for each transceiver attachment in
10BASE5 applications when measured by both a 25
ns rise time and 25 ns fall time waveform (typical coaxial media waveform). This allotment is split into
2 pF of shunt capacitance allowed for the MAU circuitry and 2 pF for the cable tap mechanism. To keep
capacitance as low as possible, the traces from TXO
and RXI to the connector should be kept as short as
possible. The addition of a diode with the anode
electrically connected to the TXO port and the cathode to the cable tap mechanism helps minimize tap
capacitance by isolating the output capacitance of
the export. The CY7BS392 should be directly soldered to the board without a socket to keep stray capacitance to a minimum. Finally, all metal traces,
including ground and VEE, should be kept as far
from the RXI and TXO traces as possible to minimize stray capacitance. Figure 7 displays the
CY7BS392 layout considerations.
Designing a lOBASE2 MAU with the
CY7B8392
lOBASE2 transceivers are designed using the same
circuit as in lOBASE5. The one difference is that an
AUI drop cable is not used in lOBASE2. Because an
AUI drop cable is not used in Thinnet applications,
the termination resistors are not necessary on the
incoming TX± signal traces.
Driving Longer Cable with the
CY7B8392
With the CY7BS392 it is possible to drive longer
cable lengths. Because of the Hybrid collision detection which is available in the CY7BS392, up to
1000m (10 BASE5) or 300m (10 BASE2) of coaxial
cable can be used. These extended cable lengths can
be used in non-repeater applications only. In repeater applications the standard cable length maximums of 500 and lS5 meters must be adhered to.
This limit is enforced because the maximum end-toend delay time for a signal on the network cannot ex-
Because 10 BASE5 applications use an AUI drop
cable, termination resistors are required on the differential transmit pair. The AUI cable has a characteristic impedance of 7SQ Using two 390 and a 0.01
f-tF capacitor as the center grounding effectively terminates the line and also minimizes common mode
signal, or a more simple 7S0 resistor will suffice.
2-46
~
.2
CY7B8392 Low Power Ethernet Coaxial
~YPRESS~~~~~~~~~~~~~~1r==a~n=sc=e~w;e~r~A~p~p=li~ca=t=io~n~
AUI
CABLE (Not in IOBASE2)
r - - •
I
+
DC to DC
CONVERTER
12to 15VDC
9V (ISOLATED)
~OOmA
E
16
~
COLLISION
PAIR
780
2
II
15
w
b
4
COAX
13
~
I
RECEIVE
PAIR
$ :
78"
"~
CD+
:
5
CDRX+
1
2
3
~4
7
L....Ya;.
RX-
I
TRANSMIT
PAIR
300
TX+
I
390
NOT~l
TX-
16
15
14
CY7B8392
13
5
12
CDS
.....
....
TXO
RXI
I
I
I
10
8
9
I
I
I
RR-
I
I
11
7
I
I
VEE
RR+ lKQ1%·1
6
I
I
I
I
GND
I
I
HBE
:
.. __ J
1 MO
1:1 PULSE
TRANSFORMER
1
1
0.01 ~F
Figure 8. CY7B8392 MAD Application with Heartbeat Disabled[l]
ceed 25 itS by IEEE 802.3 standard. Thus, the total
delay of the cable plus a maximum of four repeaters
must be less than 25 its.
UNbalanced) or modifying the transceiver board
design to operate with the non-standard cable.
Modifying the transceiver board for non-standard
cable applications involves attenuating the signal at
the RXI and CDS pin. If this is not done then the
voltage appearing at the RXI pin will not be within
acceptable limits for the CY7B8392. In the case of
93Q cable, the window for setting collision threshold is between - 2637 mV and - 2895 m V due to the
altered resistance of the cable network. These voltages are calculated by taking the RG-58 AJU thresholds and multiplying by 1.86 (93/50). Because the
CY7B8392 is designed to send a collision signal if
the DC voltage on the line falls below -1530 m V, every transmission on 93Q cable will be seen as a colli-
Driving Non-Standard Cable with the
CY7B8392
In many situations a network cabling system will already be installed, and some these networks used
coaxial cable with different characteristic impedances. Because a significant portion of the cost for
installing a LAN is the cost of the cable and the labor
to install it, it is in the interest of the customer to use
the existing cable plant if possible. This can be
achieved either by using a BALUN (BALanced to
2-47
~
CY7B8392 Low Power Ethernet Coaxial
~~YPRESS~~~~~~~~~~~~~1r~a~n~sc~e=w~er~A~pp=l~ic~a~ti~on~
INTRINSIC
V~E
CAPACITANCE ""'- : _
Auto-AUI Function
The CY7B8392 Auto-AUI function allows a
lOBASE designer the ability to easily design NICs
(Network Interface Cards). The Auto-AUI function
has the ability to switch between AUI, twisted pair,
and coax connections (assuming both the twisted
pair and coax transceivers have Auto-AUI function). This feature benefits both the board designer
with a cost savings, and the user who no longer has
to open the computer or program software to reconfigure the NIC.
RXlh~.............""",~~
TXOI--~---.....I
CDS I - - ' V I / I r - - - - - .
24.9k
CY7B8392
A typical NIC is shown in Figure 10. If the user
wishes to change from the AUI port to the lOBASE2
coaxial connection it is necessary to open the computer and flip switches, or in some cases reconfigure
the NIC software through a tedious process. Both of
these situations require the user to consult a manual
for reference. If this manual is lost, changing the
configuration becomes problematic for the user.
Figure 9. CY7B8392 application using 93U
Cable
sion. Thus, a resistive divider is required to lower
the receive voltage to an acceptable level for collision detection. Using standard resistor values, the
voltages should be divided so that 1530 mV lies in
the acceptable window of collision detection.
Choosing a voltage divider with resistor values of
54.9 kQ and 45.3 kQ provides a satisfactory result.
An example of an application using 93Q cable is
shown in Figure 9. The intrinsic capacitance of the
RXI pin and trace capacitance (typically 1 pF combined) can create a low pass filter effect with the
voltage divider in place. This can be offset by compensated by placing a capacitor ( -1.2 pF) in parallel with the leading resistor of the voltage divider, as
shown in Figure 9. A series 24. 9 kQ (45.3k I I54.9k)
resistor is also required on the CDS pin to insure
that biasing currents on CDS and RXI produce an
equivalent voltage drop.
Figure 11 shows a NIC design using the CY7B8392
Auto-AUI function. This application eliminates the
need for switches/jumpers or special software. The
CY7B8392 automatically does the reconfiguration
by either turning its AUI drivers on (properly terminated coaxial cable is attached), or placing them in
a high-impedance state (no coaxial cable attached).
Thus, simply attaching a coaxial cable to the
lOBASE2 coaxial port and leaving the lOBASE-T
and AUI ports unconnected automatically configures the NIC.
DC - DC Converter Design for
CY7B8392 Applications
Any resistor combination that solves Equation 1 will
provide the necessary offset for non-standard cable
applications. Larger resistor values are desirable to
keep the shunt resistance of the transceiver node as
high as possible.
(R2/R1+R2) *(ZcoAX/50Q)=1
In MAU applications the CY7B8392 requires a
-9V isolated power supply from a 12-15V power
source. Both discrete and integrated DC- DC converters are available for this application. Integrated
DC- DC converters are available through several
vendors (Fil- Mag, Valor). A discrete design can be
provided through a transformer, self-oscillating primary, and rectifying secondary. Because the 8392
consumes very little power when compared to competitive devices a discrete transformer allows the
designer to minimize the DC-DC cost through the
selection of low power components. A schematic of
the circuit is shown in Figure 12.
Eq.1
(ZcoAX=Non-standard cable impedance)
When different resistor values are used at the voltage divider of RXI, the biasing resistor at CDS must
also be changed to reflect the altered parallel resistance of R1 and R2.
2-48
CY7B8392 Low Power Ethernet Coaxial
'IiIr~YPRESS~~~~~~~~~~~~~~Tr~a~n~sc~e~iv~e~r~A~p~PI~ic~a~t~io~n~
I
;---c!,--;
NETWORK
r-CONTROLLER
SNI
,
,
'
,
,
,
,
,
TP
TRANSCEIVER
,
,
-;;'
I
,
AUI
PORT
,
,
,
,
"r----·
I
ISOLATION
t--
CY7B8392 r-
COAX
PORT
I
Switch/jumper or software
Figure 10. 'IYPicaJ Network Interface Card
The function of the circuit is as follows: Initially,
12V is applied across the input of the converter. This
causes the voltage at (1) to rise until one ofthe transistors arbitrarily turns on. For this example we will
assume that Q1 turns on. As Q1 starts conducting,
current begins to flow through the transformer
winding connected to the collector of Q1. This current change is opposed by the inductive characteristics of the transformer, which induces a voltage in
the opposite direction. Because all the transformer
windings are wound around a common core, every
separate winding will induce a voltage. The direction of the induced voltages follow the transformer
dot convention. Thus, with Q1 ramping, every winding appears as a voltage source with the positive terminal at the end of the winding (opposite the dot).
This induced voltage will force the base voltage of
TP
PORT
Q1 higher, turning it on hard, and force the base
voltage of Q2 low, ensuring that it remains off.
At the same time the current is ramping up in the
primary, the voltage induced in the transformer is
applied to the secondary rectification circuit. Again,
following the dot convention, a positive voltage is
applied at the cathode of D1 and a negative voltage
at the cathode of D2. Current flows through D1 and
charges the output capacitors, while D2 opposes
current flow.
Eventually, as the current increases in Q1, it reaches
a point where the 12V supply cannot continue to
sustain dildt. As this occurs, the induced voltage opposing the current flow in the transformer will disappear. Consequently, the voltage at the base of Ql
will be unable to sustain the collector current and
I
TP
TRANSCEIVER
TP
PORT
I
NETWORK
I-CONTROLLER
AUI
PORT
SNI
I
ISOLATION
-
CY7B8392 f-
COAX
PORT
I
Figure 11. Advanced Network Interface Card with Auto-AUI Function
2-49
E
~
.;CYPRESS
CY7B8392 Low Power Ethernet Coaxial
=============;;;;Tr=a;;;;n;;;;sc;;;;e;;;;iv;;;;e;;;;r;;;;A;;:;p;!;p;;;;li;;;;ca;;;;t;;;;io;;;;n=
.----_ _ _ _ _ _ _ _ _'_-::\- - - - - ~ Transformer: Pulse PE-68279
•
~-r--'--4--~
I
-9V
Transistors: 2N2222A or equivalent
Diodes: BAT54C or equivalent
Figure 12. DC- DC Converter Design
Ql will come out of saturation. In turn, the current
crete DC- DC converter shown in Figure 12 can be
flow in the winding will begin to decrease. Because
easily redesigned to use this supply. Simply replace
the inductive nature of the transformer opposes the
the 3.3 KQ resistor on the input with a 270Q resistor
and change the transformer to a Pulse PE-68283.
change in current, a voltage is induced which opposes this decrease in current. Following the dot
convention, the positive terminal appears at the beCY7B8392 vs. The Competition
ginning of the winding (the end with the dot). The
induced voltage forces the voltage at the base of Q2
As shown in this application note and the
high and turns the transistor on hard while Ql is
CY7B8392 data sheet, the Cypress coaxial transforced off. The current then flows through the transceiver has features which set it apart from the comformer winding to the collector of Q2 and then to
petition. The low power characteristics of the
ground. In this manner the primary circuit oscillates
CY7B8392 mean that the cost of the power supply
and changes DC to AC.
is reduced, saving on the overall cost of the board
design.
Cypress hybrid collision detection, available
Applying the induced voltage to the secondary rectionly on the CY7B8392, allows larger diameter netfication circuit, a positive voltage is applied to the
works to be used without reconfiguring the transcathode of D2, which allows current to charge the
ceiver board with a voltage divider at CDS. Pulloutput capacitors. These capacitors minimize voltdown resistors are no longer required on the RX±
age ripple at the output and provide a constant DC
and CD ± AUI ports, again minimizing board space
supply to the CY7B8392.
and cost. These features make the CY7B8392 a
If the CY7B8392 is being used in an adapter card apstandard to follow in coaxial Ethernet transceiver
plication where 5V± 5% is available, then the disapplications.
Notes:
1. The TX± 78Q termination resistor may be exchanged with two 39Q resistors and a l-t-tF capacitor for
common mode rejection. Only one configuration should be used, not both together.
2-50
lOOBASE-T4/10BASE-T Ethernet Transceiver
Application
media and modifies the signal amplitude. The
25MHz crystal is used as a timing reference for the
CY7C971. The connectors provide for an external
interface to the twisted pair media, and the MIL
LEDs are used to indicate the mode of operation
(lOOBASE-T4, lOBASE-T, or lOBASE-T Full Duplex), as well as indicating transmit and receive status. Finally, the various resistors are used for terminations and current limiting, and the capacitors
are used for decoupling.
Introduction
This application note briefly describes a
lOOBASE-T4/lOBASE-T transceiver application using the CY7C971 Fast Ethernet Transceiver. A
schematic and a description of the board layout are
included.
The transceiver's function is to provide an interface
between the media (4 pair of CATegory 3, 4, or 5 Unshielded Twisted Pair for lOOBASE-T4, or 2 pair of
CAT3, 4, or 5 UTP for 10BASE-T) and the Media
Independent Interface (or MIl) as defined in the
IEEE Fast Ethernet standard.
Note, there is no external transmit or receive filter
required. Without the bulky filter magnetics, the
board layout becomes quite simple.
Tl"ansceiver Schematic
Tl"ansceiver Board Layout
The schematic for the transceiver application is very
simple due to the high level of integration designed
into the CY7C971 (see the CY7C971 data sheet).
The schematic is shown in Figures 1 and 2. The basic
components are:
Figure 3 is a Printed Circuit Board (PCB) design for
the transceiver application shown in Figures 1 & 2.
As noted above, due to the high level of integration
within the CY7C971, the board layout is very simple. The board consists of two layers, one signal layer and one split power and ground plane.
1. CY7C971 Fast Ethernet Transceiver
4. Connectors (MIl and RJ45)
The dominating components on the board are the
CY7C971 (u1), the quad transformer (tl), the
25MHz crystal (xl), the MIl connector U2), and the
RJ45 connector U1). Other components are the
LEDs, resistors, and capacitors.
5. LEDs
Conclusion
6. Resistors
The transceiver application breifly described in this
application note is intended as an evaluation tool
for the CY7C971 Fast Ethernet Transceiver. Transceiver boards, schematics, and Gerber files are
available from Cypress Semiconductor by contacting a local Cypress sales office.
2. Quad 1:21tansformer
3. 25MHz Crystal
7. Capacitors
The CY7C971 performs all of the functions necessary to implement the transceiver design. The quad
transformer provides isolation from the twisted pair
2-51
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lOOBASE-T4/10BASE-T Transceiver Application
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2-52
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lOOBASE-T4/10BASE-T Transceiver Application
I
Figure 2. Transceiver Application Schematic Sheet 2
2-53
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lOOBASE-T4/10BASE-T Transceiver Application
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2-54
3.680"
lOOBASE-T4/ lOBASE-T Ethernet
PCI Network Adapter
The network adapter card's function is to interface
the host computer to the network cabling. The
adapter card plugs into the host computer's PCI bus.
The twisted-pair network cable plugs into the end of
the network adapter card via an 8-pin modular
RJ -45 jack. Figure 1 illustrates a PCI Network
Adapter with a host motherboard.
Background
This application note describes the design of a dual
speed 100BASE-T4/lOBASE-T Ethernet Network
Adapter card for PCI systems using the Cypress
CY7C971 PHY and the Digital Semiconductor
21140 MAC (Media Access Controller). The adapter card has the following features:
The network interface card contains all of the circuitry for the Ethernet physical layer, MAC layer,
and PCI interface. The Cypress CY7C971 contains
all of the physical layer circuitry for 100BASE-T4,
lOBASE-T, and Auto-Negotiation. The DEC 21140
contains all of the logic for Ethernet MAC and the
PCI bus interface. The CY7C971 and the DEC
• Dual Speed 100BASE-T4/lOBASE-T
• Full Duplex lOBASE-T
• IEEE Compliant Auto-Negotiation
• High Performance PCI Interface
Figure 1. PCI Network Adapter Card
2-55
I
21140 interface to each other through the Media Independent Interface (MIl). The MIl is an IEEE
standard interface between the Ethernet physical
layer and the MAC layer.
Media Dependent Interface (MDI)
The output buffer design uses a feedback voltage
driver that minimizes power consumption and controls the common mode output voltage. The transformer provides sufficient common-mode rejection
over the frequencies of interest so that an external
common mode choke is not needed. Figure 2 shows
a schematic of the media interface with the
CY7C971.
The CY7C971 provides a simple interface to the
8-pin modular RJ -45 jack. No expensive external
filters or components are necessary because all
transmit filtering and equalization are performed
on-chip. All CY7C971 media interface pins are dual
speed, allowing shared magnetics to be used. A quad
1:2 transformer for electrical isolation and termination resistors to match the cable impedance are all
that is required.
The characteristic impedance of the twisted pair
medium is a nominallOOQ. The 1:2 transformer reduces (by the square of the turns ratio) medium load
impedance to 250 on the primary (971) side. The
termination resistors and the output buffer impedance together form a matching 250 load. The
matching load insures that maximum signal is transferred to the medium and minimizes reflections due
to impedance mismatch.
CY7C971
CY7C971
Modular Shielded
a-Pin Jack
Quad
Transformer
1:2
RX_D4TX_D4-
a
24
7
TX_D4+
RX_D4+
RX_D3TX_D3TX_D3+
RX_D3+
RX_D2RX_D2+
TX_D1- 44
TX_D1+ 42
2
10Q
T220PF
Chassis Ground
10KQ 1%
Figure 2. MDI Schematic
2-56
RJ-45
lOOBASE-T4 PCI Adapter
The center taps on the media side of the transformer
are connected to the chassis ground through 220-pF
(minimum) high-voltage (2 KV) capacitors. These
capacitors help absorb common-mode noise that is
picked up or generated on the twisted-pair medium.
The capacitors must be capable of withstanding the
isolation
requirements
specified
in
the
100BASE-T4 standard. High-voltage ceramic disc
capacitors are economical and work well in this application.
Media Independent Interface (MIl)
The Media Independent Interface (MIl) is the
IEEE Ethernet standard interface for communication between the MAC and PHY devices. The MIl
supports both 100 Mb/s and 10 Mb/s data transfer
modes. In 100 Mb/s mode, the MIl transfers nibble
wide data groups at 25 MHz transfer rate yielding
100 Mb/s throughput. In 10 Mb/s mode, the transfer
rate is reduced to 2.5 MHz for a 10 M/s throughput.
During all transfers, the receive and transmit reference clock are continuously sourced from the
CY7C971 PHY to the 21140 MAC. Figure 3 shows
the MIl connections between the CY7C971 and the
DEC 21140.
The high precision currents needed for the transmit
DAC and equalizer are derived from the external
lOKQ 1% resistor on pins Rl and R2. An internally
generated band-gap voltage reference is used by the
CY7C971 for all internal reference voltages.
+5V
CY7C971
t:::
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/
MDIO
MDC
RXD3
RXD2
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TXD3
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77
79
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D5
14
15
16
19
20
18
05
RX_EN
80
76
105
106
118
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7
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9
11
12
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DEC 21140
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114
110
123
125
126
127
130
131
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112
113
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109
MII_MDIO
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Mil_ERR
s::
-
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Serial Port
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SYM_TXD4
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a: 0:: a: a: a: a:
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2-57
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MILCRS
SYM_RXD4
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lOOBASE.T4PCIAdapter
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All data transfers between the CY7C971 and the
DEC 21140 are over the MIl interface. The DEC
21140 has an additional7-wire serial interface for an
external 10 Mb/s transceiver. This port is not used
in conjunction with the CY7C971 and these port
pins are tied inactive as shown in the schematic (AppendixA).
CY7C971
~
52
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The CY7C971 has a buffer enable input signal,
RX_EN, that is not part of the MIl standard. This
pin is used to place the MIl output buffers in high
impedance. In this application, RX_EN should be
tied HIGH to permanently enable the MIl output
buffers. The Q5 and D5 pins on the CY7C971 are
not used in MIl mode. D5 can be tied either HIGH
or LOW Since the DEC 21140 does not support explicit transmit error generation over the MIl interface, the 971 TX_ER pin should be tied LOW to prevent inadvertent transmit error generation.
Cload
(33 pF)
T
25.000 MHz
T
Cload
(33 pF)
Figure 4. Clock Pins
The package pins contribute approximately 1.5 pF
to the parallel load capacitance. Board trace and
pads contribute between 1-2 pF of parasitic capacitance depending on trace length, width and dielectric thickness. According to this formula, an 18-pF
parallel resonant crystal would require 33-pF load
capacitors.
The MDC and MDIO pins form a simple two-wire
serial management interface between the 7C971
and 21140. MDC is a clock signal sourced from the
21140. The MDIO line is a bidirectional data line
used to transfer management data frames. The
MDIO signal requires a 1.5 Kohm pull-up resistor
to VCe. This interface is used to transfer standard
management frames that control and monitor the
behavior of the CY7C971. Management frames
contain a PHY address, register number, op code,
and a 16-bit data field.
The crystal should have frequency stability of 100
ppm or less in order to comply with the Ethernet
standards Figure 4 shows the CY7C971 clock pin
connections. The load capacitors are connected between the Clock pins and ground.
LED Pins
The CY7C971 can drive LEDs directly. The LED
pins use an open drain output buffer that can sink up
to 12 rnA. The buffers have a weak internal pull-up
resistor. Figure 5 shows how the LED pins connect
to the LEDs.
Clock Pins
The CY7C971 generates all internal and external
clock signals from its on-board oscillator circuit.
The oscillator circuit requires an external 25 MHz
parallel resonant crystal connected between the
CLKO and CLKI pins. The external load capacitors
(qoad) should be chosen so that the total load capacitance matches the parallel resonant capacitance of the crystal. The load capacitors form a series capacitance network. The required load
capacitance is derived from the following equation:
The LTX and LRX pins indicate when the CY7C971
is actively transmitting or receiving Ethernet
frames. LTX indicates that the transmitter is active,
and LRX indicates that the receiver is active. These
signals are time stretched to at least 25 ms so that
light pulses emitted from the LED can be detected
by the human eye. These pins may be tied together
in a wire-or fashion to form a generic activity indicator.
Cxtal = (Cpin + qoad + Ctrace) / 2
The LINKT4, LINKT, and LINKFD pins indicate
when the CY7C971 is in the link pass state for
2-58
=-~
lOOBASE-T4 PCI Adapter
==,CYPRESS = = = = = = = = = = = = = = = =
vertised abilities by changing the code word in the
Auto-Negotiation Advertisement Register (Reg. 4).
The ISODEF (Isolate Default) pin is tied LOW in
order to force the CY7C971 to power up with the
MIl ready for normal operation (not isolated). The
Isolate Bit (0.10) will indicate normal operation as
the default setting. The address pins (AO-A4) are
wired for PHY address OlH. Address OOH is reserved for external transceivers and should not be
used. The CY7C971 will respond to PRY management frames that use the assigned address. The values on the ISODEF and AO-A4 pins are latched
into the 7C971 during a hard reset or power-on
reset.
1.5KQ
I~
I z~
::J
CY7C971
Figure 5. LED Pins
The MODE pin is tied HIGH to force the 7C971
into MIl mode. MIl mode enables the MIl, PCS
(Physical Coding Sublayer), and PLS (Physical Layer Signaling) logic. The PCS performs the 8B6T encoding/decoding and serial/parallel conversion for
lOOBASE-T4. The PLS performs Manchester encoding/decoding and serial/parallel conversion for
lOBASE-T. When the MODE pin is LOW (PMA
Mode), the MIl, PCS, and PLS are disabled and the
lOOBASE-T4 PMA (Physical Medium Attachment)
interface is exposed on the MIl I/O pins. PMA
Mode is used only in repeater applications.
100BASE-T4, lOBASE-T, or lOBASE-T Full Duplex.
The operating mode is determined either through
the Auto-Negotiation process or by manual configuration with the control register (see section on
MDC/MDIO Management Interface). The
CY7C971 will enter a link pass state when an operating mode has been selected (either through AutoNegotiation or manually) and properly formed
technology dependent link integrity pulses are received from the medium. If only a single link indication is needed, the link indicator pins may be tied
together in a wire-or fashion to form a generic link
pass signal. These signals may also be individually
connected to the 21140's General Purpose pins in
order to quickly inform the MAC of any changes in
the link status.
The Test pin is tied LOW to permanently disable the
CY7C971 test mode. Test mode is used for factory
ATE testing only.
+5V
,.-
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Configuration Pins
The configuration pins are wired for the adapter
card application as shown in Figure 6. The ENT4,
ENT, ENFD, AUTO NEG are wired HIGH to enable all of the 7C971 operating modes. At power-up
or during a hard reset, the logic values on these pins
are loaded into their corresponding ability bits in
the MIl Status Register. The ability bits in the Status
Register dictate whether an operating mode can be
become active. After the power-up or reset cycle
completes, the Auto-Negotiation process will advertise all operating modes that the Status Register
reports as enabled. Management can alter the ad-
10KQ
WI~
w 0 «
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5~
C)
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CY7C971
Figure 6. Configuration Pins
2-59
tii
°en
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a:
1-11-
wenw
u.
owen
Ol-W
~
a:
The ground plane runs under both the 5V and 3.3V
planes. There is a cutout in both the power and
ground planes under the RJ -45 and transformer.
The RESET pin should be connected to the PCI reset pin on the card edge. Power-on reset is taken
care of by an internally generated reset signal. During a hard or power-on reset, the values on the
ENT4, ENT, ENFD, AUTONEG, ISODEF, and
AO-A4 are loaded into the CY7C971 and all of the
logic and analog circuits are forced to their default
states. During a soft reset all of the logic and analog
circuits are reset but the values on the configuration
pins are ignored. The software drivers can issue a
soft reset by setting the Reset Bit (0.15) in the Control Register. This bit is self clearing.
The media interface components can be neatly
placed behind the RJ -45 connector. Figure 8 illustrates the physical layout of the media interface with
a 4-layer board. 0.027 !!F decoupling capacitors are
used on each of the CY7C971 power pins. These
0805 SMT capacitors are placed in a row as close to
the pins as possible. The termination resistors fit
neatly in a row behind the decoupling capacitors.
Thntalum 10 !!F capacitors are placed on opposite
corners of the CY7C971. The CY7C971 media interface and power pins were placed in such a way to
minimize the use of vias and simplify board layout.
Layout Considerations
The adapter card design is simple enough to fit on
a standard PCI short card (3.5" x 5") or smaller
PCB. A 4 layer PCB construction with dedicated
power and ground planes is recommended. The
DEC 21140 requires a 3.3V power supply. The
CY7C971 requires a 5V supply. Separate 5V and
3.3V power planes can be partitioned on a single
power layer. Figure 7 shows an example of partitioned power planes with component placement.
Software Considerations
Software drivers are responsible for configuring
registers within the DEC 21140 for proper operation with the CY7C971. The software drivers are
also responsible for transferring Ethernet packets
between the host computer's local memory and the
Figure 7. Power Plane and Component Placement
2-60
==~YPRESS~=;=;=;=;=;=;=;=;=;=;~10~O~B~A~S~E~~~4~P~C~I~A~da~p~te==r
High Voltage
Caps
E
7C971
Power
Cutout
Figure 8. Media Interface Layout
21140's data buffers, and for managing the 21140
and CY7C971 resources during normal operation.
pins on the MIl. This connection is shown in
Figure 3.
The CY7C971 contains an on-chip management facility that is accessed through its serial management
port on the MIl. The management facility consists
of registers that report and control basic activities of
the PHY such as Auto-Negotiation and link status.
The DEC MAC emulates the management agent
with its software drivers. During power-up, reset, or
a down link, the drivers should poll the management
registers to determine the result of Auto-Negotiation and the state of the link. While the link is up,
the drivers should poll the CY7C971 Status Register
on a timely basis to make sure the link is active. The
CY7C971 was designed so that standard MIl compliant software drivers can support the management
facility.
The CY7C971 management facility acts as a slave
device to management accesses from the MAC.
Management data is transferred between CY7C971
and the DEC 21140 MAC with the MDC and MDIO
2-61
DEC Register Set-Up
CY7C971 will only respond to management frames
whose address matches the address assigned to the
CY7C971 by the address pins AO-4. In this application, the CY7C971 address has been permanently
wired to 01H. All management accesses to the
CY7C971 should use this address.
The 21140 Command and Status Registers (CSR)
must be configured so that the 21140 communicates
with the CY7C971 through the MIl port. Register
CSR6 in the 21140 controls the MAC-PHY interface configuration. The 21140 parallel MIl port is
enabled with the Port Select bit in CSR6 (CSR6, bit
18). When set, the MIl port is enabled and the serial
10-Mb/s port is disabled.
The register field determines the target register for
the operation. The tum around field provides time
to switch the direction of the bus during a read operation. The next 16 bits are the data field. During
a read operation, the PHY will drive the MDIO line
with the target register contents. During a write operation, 16 bits are transferred to the PHY from the
MAC and written in the target register.
The PCS Function and Scrambler Mode inside the
21140 must be disabled for proper operation with
MIl based transceivers such as the CY7C971. PCS
and scrambler modes are used with 100BASE-X
physical layer devices only. The PCS Function is disabled by clearing the PCS bit in CSR6 (CSR6, bit
23). The scrambler is disabled by clearing SCR bit
in CSR6 (CRS6, bit 24).
The CY7C971 can accept management frames that
are not preceded by a 32-bit preamble. A sequence
of 32 ones will force a reset on the CY7C971 management facility. It is recommended that the MAC
issue this 32-bit sequence after power-up and periodically during normal operation.
The 1tansmit Threshold Mode (TIM) must be adjusted according to the operating speed of the link.
This bit determines the number of bytes in a frame
that must be stored in the transmit FIFO before the
transmission process is initiated. In lO-Mb/s mode,
the TIM bit (CSR6, bit 22) should be set. In
100-Mb/s mode, the TIM bit should be cleared. The
link operating speed can be determined by polling
the CY7C971 management Auto-Negotiation and
Control registers or by monitoring the LED Link
pins through the General Purpose Register.
The CY7C971 supports the standard and expanded
MIl register set. The Expanded Register set includes the OUI (Organizationally Unique Identifier) and Auto-Negotiation registers (registers 2-7).
Figure 10 shows the CY7C971 register map.
Control Register (Reg. 0)
The Control Register is used to manually set the operating modes and enable/disable certain features.
Auto-Negotiation can be enabled/disabled through
this register with bit 0.12. When Auto-Negotiation
is enabled, the speed of the link is determined automatically, and the speed selection bit (0.13) has no
effect. When Auto-Negotiation is disabled, the
speed selection bit determines the speed of the link.
MDC/MDIO Management Interface
The CY7C971 contains all of the standard and extended registers defined in the MIl standard (Registers 0-7). There is also an additional CY7C971
specific register (Reg.16).The MAC can perform
write and read operations to the CY7C971 management registers by transferring management frames
over the MDIO serial interface. The MDC signal
serves as the management data clock and is sourced
from the MAC. The MDIO signal is bidirectional.
The frame structure is shown in Figure 9.
The loop backbit (0.14) is used to internally loop the
transmit signal path to the receive signal path. Placing the CY7C971 in loopback mode will cause the
The management frame is comprised of several
fields. The start sequence 01 is used to identify the
start of a frame. The op-code field determines
whether a read, write, or no-op will be performed.
The address field determines the target PHY. The
Read
0000000000000000
~~~~~~~=+~~~~~~~
0000000000000000
Figure 9. Management Frame Structure
2-62
=»
~YPRESS======================1~OO~B~A~S~E~~~4~P~C~I~A~da~p~te~r
link to be broken and the transmit drivers will be
forced to idle. The power-down bit (0.11) places the
CY7C971 in low power stand-by mode. All of the
analog circuits are placed in low power mode and
the clock is stopped to all of the CMOS digital logic.
Only the MDC/MDIO port is active. When powerdown mode is exited, the CY7C971 will reset all of
the registers to their default values. Any register setting other than the default value must be restored by
the driver.
15
Reg 2 =
Reg 3 =
16
0
4
II
12
11
I
2
OUI
8 7
8
I
4 3
0
IPart0 II Revx II
The Cypress OUI is 00A050h. According to the
Ethernet MIl standard, twenty-two bits of the OUI
are split between Registers 2 and 3. Register 2 contains 16 bits of the OUI and register 3 contains the
other 6. Register 3 also contains 6 bits for the
CY7C971 part number and 4 bits for the revision
number. The register mapping and contents are
shown in Figure 11.
Auto-Negotiation Registers (Reg. 4 -7)
Registers 4 through 7 manage the Auto-Negotiation
process. These registers only have meaning when
Auto-Negotiation is enabled. Management intervention is not required during the normal Auto-Negotiation process. Management should only intervene with the Auto-Negotiation process in order to
influence the outcome.
Registers 2 and 3 contain the Cypress Semiconductor Organizationally Unique Identifier and the
CY7C971 part and revision number. The OUI is a
24-bit sequence that is uniquely assigned to organizations for identification purposes by the IEEE.
2
3
4
5
6
7
430
Figure 11. OUI Registers
OUI Registers (Reg. 2-3)
1
8 7
OUI
The Status Register is a read-only register that reports the capabilities and status of the CY7C971.
The status of the Auto-Negotiation process can be
monitored through bit 1.5. This bit reports when
Auto-Negotiation has completed. The Remote
Fault bit (1.4) will indicate if Auto-Negotiation has
detected a remote fault at the other end of the link.
The Link Status bit indicates whenever any technology (i.e., the lOBASE-T or the 100BASE-T4 circuits
of the CY7C971) has entered the Link Pass State.
This means that the link is available for data transmission and reception.
o
11
0
15
Status Register (Reg. 1)
#
12
The Auto-Negotiation Advertisement Register
(Reg. 4) holds the 16-bit code word that the
CY7C971 advertises over the medium. This code
word encodes the capabilities of the CY7C971, the
LAN technology (CSMNCD Ethernet), and fault
indications. During power-up or reset, this register
will set to the default conditions of the CY7C971
that are dictated by the enable pins. This causes
Auto-Negotiation to only advertise the capabilities
that are enabled. These enabled capabilities are reflected in the Status register. Management may intervene in the Auto-Negotiation process by writing
to this register. Only the operating modes that are
enabled in the Status Register will be advertised.
Any attempt to advertise a disabled mode (disabled
when ENx pin is LOW) by writing to the Advertisement Register will be ignored. Management should
restart the Auto-Negotiation process by setting bit
0.9 (Restart Auto-Negotiation Bit) if the contents of
the Advertisement Register are changed. Figure 12
shows a block diagram of how the enable pins affect
Register Description
Control
Status
OUI
OUI
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
Auto-Negotiation Next Page Transmit
•• (reserved)
•
Cypress Proprietary
Figure 10. Register Map
2-63
I
Auto-Negotiation
Advertisement Register
Status Register
ENT4~>---------T:~--~-~!r---~~1_.1_5----e---~
: 1.14
_ _...;i_--I- - - - - - ~
4.9
(from
MDIO
ENTFDOO~~----~~
ENT OO~>-------l---'---1
:1.11
RESET OO~>-----l
(Power-on)
Reset
Figure 12. Register Block Diagram
Auto-Negotiation Advertisement and Status Registers.
ceived and that there is not a Parallel Detection
fault.
The Auto-Negotiation Link Partner Ability Register (Reg. 5) contains the code word that has been
consistently received from the PRY at other end of
the medium. This register is valid when the Page Received bit (6.1) is set in Register 6. Auto-Negotiation
uses the received code word to decide the operating
mode of the link. The choice is based on the priority
resolution table in the Auto-Negotiation standard.
lOOBASE-T4 has the highest priority. If Auto-Negotiation completes through parallel detection, the
contents of this register are invalid. (Parallel Detection part of the Auto-Negotiation process. Its function is to detect the presence of Ethernet transceivers that do not support Auto-Negotiation.)
Register 7 is used to hold the Next Page code word
that is to be transmitted during next page exchanges.
Next Pages are code words that can be sent in addition to the base code word in the advertisement register. The Next Page facility is intended to be used
as a simple scheme for passing messages between
the PRYs on the medium before the link becomes
active. The messages may contain information such
as the presence of a fault, for example. The Next
Page Transmit Register defaults to 200lR (Null
Message) after power-up or a reset.
Cypress Proprietary Register (Reg. 16)
The Cypress Proprietary Register (Reg. 16) contains specific information about the CY7C971. Bit
15 indicates the polarity of the RX_D2 ± signal
pair. When clear, this bit indicates that the polarity
of RX_D2 ± is correct or undetermined. When set,
this bit indicates that inverted polarity on RX_D2 ±
was detected and has been corrected. Inverted po-
The Auto-Negotiation Expansion Register (Reg. 6)
is a Read-Only register that reports the status of the
Auto-Negotiation process. This register should be
monitored during the Auto-Negotiation process in
order to make sure that code words are being re2-64
::'~YPRESS~~~~~~~~~~~1=OO=B=A=S=E=~=4=P=C=I=A=da=p=te~r
larity is most likely caused by inadvertently reversing the signal wires at the medium connector.
ternal components to a minimum helping to reduce
system cost and design effort.
The complete adapter card schematics and a bill of
materials are included at the end of this application
note (Appendix A and Appendix B, respectively).
More information on the CY7C971 can be found in
the data sheet. For more information on
lOOBASE-T4, MIl and Auto-Negotiation standards,
consult the IEEE 802.3u document: "MAC Parameters, Physical Layer, Medium Attachment Units
and Repeater for lOOMb/s Operation."
Conclusion
This application note covers the major issues for a
dual speed Ethernet/PCI Bus adapter card design
using the CY7C971 lOOBASE-T4/lOBASE Transceiver and DEC21140 MAC. The high degree of integration in the CY7C971 keeps the number of ex-
2-65
~
~
+5V
1DOP
Il.
R3
:::>
:::l
~~
:::>
Il.
MDIO
MDC
RXD3
AXD2
1
2
AXDl
4
5
6
7
8
RX_DV
AX_CLK
AX_ER
N
I
00-
~
TX_CLK
TX_EN
TXDO
TXDl
TXD2
TXD3
~
12
13
14
15
16
PUlLI
'UP~
COL
20
CRS
'r
Rl
h~
~~
n
°OO~OO
RXD3
RXD2
GNDD
RXDl
RXDO
RX_DV
AX_CLK
RX_ER
TX_ER
VCCD
TX_CLK
TX_EN
TXDO
TXDl
TXD2
TXD3
GNDD
D5
COL
CRS
g~
m
G
~"tI~~,JIo.~C
CY7C971
100BASE-T4/10BASE-T
Transceiver
>
1::~
g
~~~
~~ ~~ gjl" ~ ~
PUL
2MA_LED
"l3
l2
1.5K
LTX
AX_D4TX_D4GNDS
~
~ ~ o_~
~~o~_zzoz~o£w ~~ZN_O
8
2MA_LED
,r
11
PULLUP
~
~ ~
~~
O~<~~«~~G1_1~G>m
DEC21140
~
Q
MII_MDC
SYM_RXD4
AD03
AD05
AD06
AD07
AD08
AD09
AD10
ADll
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Jl
PCI- MAC Controller
'"
c:
U>
-f
!'
U4
SR_DI
MIl_RXD3
MII_RXD2
MIl_RXDl
MII_RXDO
MII_DV
MII_RClK
Mil_ERR
MII_TClK
MII_TXEN
MII_TXDO
MIl3XD1
MIl_TXD2
MII_TXD3
SYM_TXD4
MU_CLSN
MII_CRS
SD
105
106
119
118
117
116
115
111
114
110
123
125
126
127
130
131
1 2
112
113
109
2
_
1
93G46
DI
Serial
SK
DOl 4
>-<:
'lj
R_DO
ROM
::D
CS
tTJ
U)
U)
MDIO
MDC
RXD3
RXD2
RXD1
RXDO
RX_DV
RX_ClK
RX_ER
~
"CI
~
6.~'
TX_ClK
TX_EN
TXDO
TXD1
TXD2
TXD3
~
'"
::r
r'l
-9
~
COL
CRS
;:;'
'"
PULlUP
~
::r
~
~
Jl
General
Purpose
JTAG
Boot ROM
SRL_RCLK
SRl_RXEN
SRL_RXD
SRl_ClSN
137
136
135
134
SRl_TClK
SRl_TXEN
SRl_TXD
139
140
138
~
N
o.....
~
I-'
~
~
rJ1
t'!'j
~
"'C
...
{1
cn;;;;C
<:
~
000'0
-(I)~O
-..,
~
't:l
~
m
~-~
lOOBASE-T4 PCI Adapter
} CYPRESS
Appendix A. Schematics (Sheet 3 of 4)
J2
lB
2B
4B
7B
88
9B
-12V
TCK
TDO
iNrB
iNTO
7.5 W Card
T
~
PGI GlK
-REO
AD31
AD29
AD27
AD25
G/BE3
AD23
AD21
AD19
AD17
G/BE2
ilii5Y
DEvSEr
LOci'<
PEi'iR
SEAR
CiBTI
AD14
AD12
AD10
AD08
AD07
ADOS
AD03
ADOl
.J..Qg..
PCI Connector
Side B
Side A
-12V
TRST
TCK
TDO
INTB
+12V
TMS
TDI
iNTO
"PRs'N'lT
"iNTA
"'iNTC
Reserved
llB
"'PRsNT2
Reserved
Reserved
.1.±§....
Reserved
Reserved
16B
18B
20B
21B
23B
24B
26B
27B
29B
3 B
32B
33B
35B
37B
39B
40B
42B
44B
45B
47B
48B
52B
53B
55B
56B
58B
GlK
.illl!L
"REO
AD30
AD28
AD26
AD24
IDSEL
AD22
AD20
AD18
AD16
FRAME
TFii5Y
IRDY
DEvSEr
"'COciZ
STOP
PEi'iR
SDONE
SERR
G/BEl
AD14
AD12
AD10
AD08
AD07
'§Bcj
PAR
AD15
AD13
AD11
AD09
CiBEo
ADOS
AD06
AD04
AD03
ADOl
AD02
ADOO
ACK64
+12V
TMS
TDI
~
~
~
22A
23A
25A
26A
28A
29A
31A
32A
34A
3SA
38A
40A
41A
43A
44A
46A
47A
49A
52A
54A
55A
57A
58A
RE064 ...§lliI.
2-68
TRs'f
RST ~
GNr 17A
Reserved
AD31
AD29
AD27
AD25
G/BE3
AD23
AD21
AD19
AD17
G/BE2
lA
2A
3A
4A
6A
7A
AD30
AD28
AD26
AD24
IDSEL
AD22
AD20
AD18
AD16
FRAME
TRi5Y
STOP
SDONE
SBo
PAR
AD15
AD13
AD11
AD09
GIBED
AD06
AD04
AD02
ADOO
!J
>--<:
'"U
::::0
+3V
tr1
U2
U2
1=
I~
1= 1= I~'
I~"
1°' I'" I'"
t" to. to< t"~
.6''0"
~
=
~
~.
+5V
?\11
'=-"'
~
N
I
Q',
'D
1= f'
r= I'" I'"
I"" I ~ I" I"
I~ I~
I" I" ~
8~
'=-"'
'"
@
!E=-
-""'
So
~
~
U5
+5V
+3V
Q
Q
C30
rJ".J
t'I"j
~
~
"'C
(1
""""
~
~
"0
..,g
m
~YPRESS~~~~~~~~~~~1=OO=B=A=S=E=~=4=P=C=I=A=da=p=te~r
Appendix B. Parts List
Qty
Description, Vendor, Part Number
Reference Designator
10 ftF!16V Tantalum Capacitor (EIA Size C)
Sprague £lee. 293DI06X9016C2
6
C2S, C26, C27, C28, C29, C31
47 ftF/16V Tantalum Capacitor (EIA Size D)
Sprague Elec. 293D476X9016D2
1
C30
.1 ftF/SOV Ceramic Capacitor (Size 1206)
Panasonic
ECU - VIH104KBW
8
C13, C14, CIS, C16, C17, C18, C19,
C20
.01 ftF/SOV Ceramic Capacitor (Size 1206)
Panasonic
ECU - VIH103KBM
4
C21, C22, C23, C24
.027 ftF/SOV Ceramic Capacitor (Size 080S)
Panasonic
ECU - VIH273KBX
10
C3, C4, CS, C6, C7, C8, C9, ClO,
Cl1, C12
33 pF/SOV Ceramic Capacitor (Size 080S)
Panasonic
ECU - VIH330JCG
220 pF/2KV Ceramic Disk Capacitor
MuratalErie DE040SB2212KV
2
C1,C2
4
C31, C32, C33, C34
10.0K ohm S% 1/8W Resistor (Size 080S)
Panasonic
ERJ -6GEYJ10.0K
1
R1
IO.OK ohm 1% l/lOW Resistor (Size 080S)
Panasonic
ERJ - 6ENFIO.OK
1
R2
10.0 ohm 1% l/lOW Resistor (Size 080S)
ERJ -6ENFIO.0
Panasonic
6
RIO, Rl1, R12, R13, R14, R1S
24.9 ohm 1% l/lOW Resistor (Size 080S)
Panasonic
ERJ -6ENF24.9
1
R9
l.SOK ohm S% l/lOW Resistor (Size 080S)
Panasonic
ERJ -6ENF1.50K
6
R3, R4, RS, R6, R7, R8
2 rnA Green LED, PC Board Side Mount
IDI
S3S0TSLC
3
L3,L4,LS
2 rnA Yellow LED, PC Board Side Mount
IDI
S3S0T7LC
1
L2
2 rnA Red LED, PC Board Side Mount
IDI
S3S0TlLC
1
L1
25.0000 MHz SMT Crystal, Parallel Res 18 pF
EpsonAmer MA-S062S.000M-AD
EpsonAmer MA-4062S.000M-G
1
Xl
2S.0000 MHz HC-49/U Crystal, Parallel Res 18 pF
Ecliptek
EC2S0- 2S.0000
1
X2
Quad 2:1 Transformer, 330 ftH Primary, lS00V
Valor
ST611S
Pulse
PE-69001
SSS3-1204-00
Bel
1
U2
CY7C971100BASE-T4/lOBASE-T Transceiver
Cypress Sem. CY7C971-NC
1
U1
2-70
Appendix B. Parts List (continued)
Description, Vendor, Part Number
Qty
LT1117 3.3V Regulator
Linear Tech. LT1117CST-3.3
RJ -45 Modular 8-Pin Shielded Jack
555141-1
Amp
DEC21140 Fast Ethernet PCI MAC
Digital Sem. 21140-AA
93C46 1K Serial EEPROM (8-Pin SOle)
National Sem. NM93C46M8
Assembly Instructions
1. Assemble only 1 crystal (Xl or X2).
2-71
Reference Designator
1
US
1
11
1
U3
1
U4
lOOBASE-T4 Ethernet Repeater
printer, etc.) communicate with the repeater over
dedicated twisted pair links. The repeater listens to
the signal being received on one port and "repeats"
the restored signal to the other ports. Figure 1 illustrates the function of the repeater in a 100BASE-T4
Ethernet Network. The repeater in this application
note has eight communication ports.
Background
This application note describes the design of a
100BASE-T4 Ethernet Network Repeater using the
Cypress CY7C971 PHY and CY7C388P for the
core logic. The repeater has the following features:
• 100-Mb/s Shared Bandwidth over Cat. 3 UTP
The functional requirements of the 100BASE-T4 repeater are defined in the IEEE 802.3u Standard
"MAC Parameters, Physical Layer, Medium Attachment Units and Repeater for 100 Mb/s Operation," Clause 27. The repeater functional requirements are summarized below:
• 8 Unmanaged Ports
• Integrated 1tansmit Filters
• Compact Layout
• Low Latency
• Detect port activity and receive Ethernet packets
The function of the repeater is to create a logically
shared communication channel between the end
stations in the network. The end stations (computer,
• Restore the shape, amplitude, and timing of the
received signals prior to retransmission
Signal restored and
repeated to active ports
Station with bad
network connection
Figure 1. Ethernet Network Built with Repeaters
2-72
sic repeater functions such as data retiming, sequence generation, and port control.
• Regenerate preamble sequence and prepend it to
the received frame
• Forward the Ethernet frame to each of the ports
CY7C971
• Detect collisions between ports and generate jam
sequence to all ports
The CY7C971 (see Figure 3) has a special low latency repeater mode that is enabled when the MODE
pin is LOW. In this mode, the MIl (Media Independent Interface), PCS (Physical Coding Sublayer),
and lOBASE-T are disabled. Only the lOOBASE-T4
PMA (Physical Medium Attachment) circuits are
active. These circuits perform the analog functions
required to interface to the twisted-pair media such
as transmit filtering, adaptive equalization, and
clock recovery. A block diagram of the PMA interface is shown in Figure 4.
• Protect network from long carrier events (jabber)
and repeated collisions (partition)
• Allow installation (removal) of station without
network disruption
• Provide basic port control (enable/disable)
Repeater Block Diagram
Media Dependent Interface (MDI)
The CY7C971 provides a simple interface to the
8-pin modular RJ -45 jack. No expensive external
filters or components are necessary because all
transmit filtering and equalization are performed
on-chip. A quad 2:1 transformer for electrical isolation and termination resistors to match the cable impedance are all that is required.
A block diagram of the 8-port repeater is shown in
Figure 2. The CY7C971 functions as the physical layer device that interfaces the digital core logic to the
twisted-pair medium. Each CY7C971 requires a
quad 1:2 transformer for electrical isolation from
the medium. The core logic is implemented with a
CY7C388A FPGA. This device takes care of the ba-
CY7C971
CY7C971
CY7C971
CY7C971
CY7C971
CY7C971
Core
Logic
(7C388A)
Figure 2. Repeater Block Diagram
2-73
CY7C971
CY7C971
1&~YPRESS
lOOBASE-T4 Repeater
PMA
S
10KQ
<;>
--'--
0
0
Jumper
21
32
RESET 33
TEST 34
S YSTEM
RESET
Figure 7. Configuration Pins
The ENT4 pin is wired HIGH to enable
lOBASE-T4. The ENT and ENFD pins are wired
LOW to disable 10BASE-T and Full Duplex operation. The AUTO NEG pin is wired to a header block
and pull-up. When a jumper is installed in the header block, Auto-Negotiation is disabled. When the
jumper is absent, Auto-Negotiation is enabled.
repeater application does not use the management
port. The address pins can be assigned any address
configuration.
The Test pin is tied LOW to permanently disable the
971 test mode. Test mode is used for factory ATE
testing only.
The ISODEF (Isolate Default) pin is tied LOW in
order to force the CY7C971 to power up with the
MIl ready for normal operation (not isolated). This
The RESET pin should be connected to the system
reset pin from the core logic. A system reset is issued at power-up orwhen the reset button is pushed.
If a port is disabled by the core logic, the reset to the
port will be active.
Layout Considerations
1.5KQ
()
z
()
z
()
z
The repeater design is simple enough to fit on a
small 7.75 in x 6.0 board using top-side-only placement. A four-layer PCB construction with dedicated
power and ground planes is recommended. The
CY7C971 requires a 5V supply. Figure 8 shows an
example of component placement.
()
z
The media interface components can be neatly
placed in-line with the CY7C971. 0.027 !-IF decoupling capacitors are used on the CY7C971 power
pins. These 0805 SMT capacitors are placed in a row
as close to the pins as possible. The termination resistors fit neatly in a row behind the decoupling capacitors. The CY7C971 media interface and power
CY7C971
Figure 6. LED Pins
2-76
--=-
22~YPRESS~======================1~O~OB~A~S~E~~~4~R~e~p~ea~te~r
Termination Decoupling
Resistors Capacitors
High Voltage
Capacitors
"
~ §O--
~'~ DO
co
3
aD
CD
0
c.....:::!....
r-:::j"""
~
Cypress
7C971
Q aD
OJ
§~
DO
a- aD
3CD a~
c.....:::!....
0
:::J
~§o
0
~'~ DO
co
3 aD
CD
0
§~
r-:::j"""
8 port
RJ-45
~
OJ
0
DO
:::J
3 a~
c.....:::!....
§~
~I
DO
aD
CD
a~
c.....:::!....
r-:::j""" §O
~'~ DO
co
Q aD
3
aD
CD
0
c.....:::!....
r-:::j"""
§O
0
ffff(f(ff-
0
0
c.....:::!....
~1
§~
DO
0' aD
3CD a~
c.....:::!....
0
0
0
Cypress
7C971
0
0
0
Cypress
7C971
0
7C388A
Core
0
Cypress
7C971
3
aD
CD
0
LEDs
0
0
Cypress
7C971
~ Q~ aD
co~
(-
rn
rn []
CD
r-:::j"""
(-
0
0
Cypress
7C971
a- aD
0
0
Cypress
7C971
Q aD
L.......:!.....
0
Cypress
7C971
E
0
rn
~
t
0
0
Figure 8. Component Placement
2-77
pins are placed in such a way to minimize the use of
vias and simplify board layout.
Core Logic
• Repeater State Machines and Logic. Controls
port selection during data reception. Also, provides collision detection and handling. Included
in this block is the control of two expansion ports
for use in the design of a stackable repeater.
Figure 9 shows a block diagram of the repeater core
logic. The blocks perform functions as follows:
The core logic is written in Verilog and fills 7K gates
of a Cypress CY7C388P 8K pASIC.
• Port N. Synchronizes signals and provides control
signals to each port, along with detecting jabber
and partition conditions.
Conclusion
This application note covers the major issues for a
8-port 100BASE-T4 Repeater design using the
CY7C971100BASE-T4/lOBASE-T 1tansceiver and
CY7C388P 8KFPGA. The high degree of integration in the CY7C971 keeps the number of external
components to a minimum, helping to reduce system cost and design effort.
• Selection and Clock MUX. Selects the receive
clock from the incoming port and provides a common receive clock for use in retiming the incoming data.
• RX FIFO. Used for temporary storage and to retime the incoming data to TX_CLK.
The complete repeater schematics and a bill of materials are available from Cypress Semiconductor.
More information on the CY7C971 can be found in
the data sheet. For more information on
100BASE-T4, MIl, and Auto-Negotiation standards, consult the IEEE 802.3u document: "MAC
Parameters, Physical Layer, Medium Attachment
Units and Repeater for 100Mb/s Operation."
• Bad Symbol, Jam, Idle, Preamble Generator.
Provides the special characters that are transmitted during different conditions.
• Output Register. Provides temporary storage of
outgoing data along with retiming to the
TX_CLK.
2-78
lOOBASE·T4 Repeater
CRS 1
RX EN1~
TX::: EN1
Port 1
••
•
Port
Signals
S8
N8
N8
Repeater
State
Machines
and
Logic
Port 8
K1_
••
•
Receive
Clocks
K8_
Receive
Data
~CLK
Selection
and
Clock Mux
!I==
RX FIFO
00-5
Bad Symbol
Generate
Jam
Generate
Idle
Generate
Preamble
Generate
Transmit
Data
DO-5
I
I
Output
Reaister
I
~
1
t.:
Figure 9. Core Logic
2-79
)
TX_CL K
(system cl ock)
Asynchronous Transfer Mode (ATM) 3
E
ATMs
Page Number
Device Number
CY7B951
CY7B952
CY7B955
Description
Local Area Network ATM Ttansceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
SST m SONET/SDH Serial Transceiver ........................................... 3-9
ATM SONET/SDH Ttansceiver ................................................ 3-16
Application Notes
CY7B951
Interfacing with the SST m
•••••••••••••••••••••••••••••••••••••••••••••••••••••
3-17
CY7B951
Local Area Network ATM Transceiver
Features
• lOOK ECL compatible I/O
• No output clock "drift" without data
transitions
• Link Status Indication
• Loop-back testing
• Single +5V supply
• 24-pin SOiC
• Compatible with fiber-optic modules,
coaxial cable, and twisted pair media
• No external PLL components
• Power-down options to minimize
power or crosstalk
• Low operating current: <65 rnA
• 0.81-1 BiCMOS
• SONET/SDH and ATM Compatible
• Compatible with PMC- Sierra
PM5345 SUNI'"
• Clock and data recovery from 51.84or 155_52-MHz datastream
• 155.52-MHz clock mUltiplication from
19.44-MHz source
• 51.84-MHz clock multiplication from
6.48-MHz source
• ±l% frequency agility
• Line Receiver Inputs: No external
buffering required
• Differential output buffering
Logic Block Diagram
Functional Description
The Local Area Network ATM Transceiver is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz
or
51.84-MHz NRZ or NRZI serial data
stream and to provide differential data
buffering for the nansmit side of the
system.
E
Pin Configuration
WOP(t)
MODE
SOiC
Top View
ROUT+~--~71--,
ROUT+
ROUTRIN+
RINMODE
Vee
CD
WOP
REFCLKREFCLK+
TOUTTOUT+
ROUT -~--+-""J-,
RIN+
RIN-
RCLK+
RCLKRSER+
RSER-
PLL
CD
lJ'l(t)
RECEIVE
TRANSMIT
TOUT+~--r-7r-r+--+-r---------?'r--r~
RCLKRCLK+
RSERRSER+
LFI
Vee
Vss
Vee
TCLKTCLK+
TSER+
TSER-
TSER+
TSER-
TOUT-~--~'~+----rr-------~,~-+~
7B951-2
TCLK+
TCLK78951-1
REFCLK+
1
JJ
Fiber or Copper
Media Interface
III
Fiber or Copper
Media Interface
IReceive Serial Data
I Carrier Detect
L
Buffered Transmit
Data
REFCLK-
CY7B951
SONETj
SDH
Serial
Transceiver
Link Fault Indication
f
Byte Rate
Oscillator
Receive Parallel Data
to
Recovered Clock
Recovered Serial
Data
Frammg
Transmit Serial Data
Parallel
to
Bit Rat.
Serial
Conversion
Clock
I
Serial
Parallel
Conversion
and
Receive Start of Cell
Read Strobe
SONETI
SDH
Overhead
Processing
PMC-Sierra PM5345 SUNI
I
IgTWAC-013
Brooktree BT8222
Figure 1. SONET/SDH aud ATM Interface
SUNI is a trademark of PMC-Sierra, Incorporated,
3-1
or
ATM Switch
Core
ATM
Cell
ProceSSing
Packet
Reassembly
Transmit Parallel Data
Transmit Start of Cell
Write Strobe
Packet
Segmentation
or
ATM Switch
Core
7B951-3
-=-,
=~~
CYPRESS
CY7B951
Pin Descriptions
Name
RIN±
I/O
Differential
In
ROUT±
ECLOut
RSER±
ECLOut
RCLK±
ECLOut
CD
TfL/ECLIn
Description
Receive Input. This line receiver port connects the receive differential serial input data stream to the
internal Receive PLL. This PLL will recover the embeded clock (RCLK±) and data (RSER±) information for one of two data rates depending on the state of the MODE pin. These inputs can receive very
low amplitude signals and are compatible with all PECL signaling levels. If the RIN ± inputs are not
being used, connect RIN + to Vee and RIN - to V ss.
Receive Output. These ECL lOOK outputs (+5V referenced) represent the buffered version of the
input data stream (RIN~. This output pair can be used for Receiver input data equalization in copper
based systems, reducing e system impact of data dependent jitter. All PECL outputs can be powered
down by connecting both outputs to Vee or leaving them both unconnected.
Recovered Serial Data. These ECL lOOK outputs ( + 5V referenced) representthe recovered data from
the input data stream (RIN ±). This recovered data is aligned with the recovered clock (RCLK±) with
a sampling window compatible with most data processing devices.
Recovered Clock. These ECL lOOK outputs ( + 5V referenced) representthe recovered clock from the
input data stream (RIN ±). This recovered clock is used to sample the recovered data (RSER±) and
has timing compatible with most data processing devices. If both the RSER± and the RCLK± are tied
to Vee or left unconnected, the entire Receive PLL will be powered down.
Carrier Detect. This input controls the recovery function of the Receive PLL and can be driven by the
carrier detect output from optical modules or from external transition detection circuitry. When this input is at an ECL HIGH, the input data stream (RIN ± is recovered normally by the Receive PLL.
When this input is at an ECL LOW, the Receive PLL no onger aligns to RIN ±, but instead aligns with
the REFCLK X 8 frequency. Also, the Link Fault Indicator (LFI) will transition LOW, and the recovered data outputs (RSER) will remain LOW regardless of the signal level on the Receive data-stream
inputs (RIN). When the CD input is at a TIL LOW, the internal transitions detection circuitry is disabled.
I.
LFI
TTL Out
Link Fault Indicator. This output indicates the status of the input data stream (RIN ±). It is controlled
by three functions; the Carrier Detect (CD) input, the internalnansition Detector, and the Out of Lock
(OOL) detector. The nansition Detector determines ifRIN ± contains enough transitions to be accurately recovered by the Receive PLL. The Out of Lock detector determines if RIN ± is within the frequency range ofthe Receive PLL. When CD is HIGH and RIN ± has sufficient transitions and is within
the frequency range of the Receive PLL, the LFI output will be HIGH. If CD is at an ECL LOW or
RIN ± does not contain sufficient transitions or RIN ± is outside the fr~ency range of the Receive
PLL then the LFI output will be LOW. If CD is at a TTL LOW then the LFI output will only transition
LOW when the frequency of RIN ± is outside the range of the Receive PLL.
TSER±
Differential
In
TOUT±
ECLOut
REFCLK±
DifffITLIn
nansmit Serial Data. This line receiver port connects the transmit differential serial input data stream
to the TOUT transmit buffers. Depending on the state of the LOOP pin, this input port can also be set
up to supply the serial input data stream to the Receive PLL. These inputs can receive very low amplitude signals and are compatible with all PECL signalling levels. If the TSER± inputs are not being
used, connect TSER + to Vee and TSER - to Vss.
Transmit Output. These ECL lOOK outputs (+5V referenced) represent the buffered version of the
nansmit data stream (TSER±). This Transmit path is used to take weak input signals and rebufferthem
to drive low impedance copper media.
Reference Clock. This input is the clock frequency reference for the clock and data recovery Receive
PLL. REFCLKis multiplied internally by eight and sets the approximate center frequency for the internal Receive PLL to track the incoming bit stream. This input is also mUlti)lied by eight by the frequency
multiplier nansmit PLL to produce the bit rate nansmit Clock (TCLK± . REFCLKcan be connected
to either a differential PECL or single-ended TTL frequency source. When either REFCLK + or
REFCLK - is at a TTL LOW, the opposite REFCLK signal becomes a TTL level input.
TCLK±
ECLOut
LOOP
TTL In
Transmit Clock. These ECL lOOK outputs ( + 5V referenced) provide the bit rate frequency source for
externalnansmit data processing devices. This output is synthesized by the Transmit PLLand is derived
by multiplying the REFCLK frequency by eight. When this output is turned off, the entire nansmit
PLL is powered down. All PECL outputs can be powered down by connecting both outputs to Vee or
leaving them both unconnected.
Loop Back Select. This input is used to select the input data stream source that the Receive PLL uses for
clock and data recovery. When the LOOP input is HIGH, the Receive input data stream (RIN ± ~ is
used for clock and data recovery. When LOOP is LOW, the nansmit input data stream (TSER± is
used by the Receive PLL for clock and data recovery.
3-2
~-.A
CY7B951
,CYPRESS
Pin Descriptions (continued)
Name
MODE
Vee
Vss
110
3-Level In
Description
Frequency Mode Select. This three-level input selects the frequency range for the clock and data recovery Receive PLL and the frequency multiplier Transmit PLL. When this input is held HIGH the two
PLLs operate at the SONET (SDH) STS-3 (STM -1) line rate of 155.52 MHz. When this input is held
!-DW the two ~LLs oper~te at the SONET STS-1line rate of 51.84 MHz. The REFCLK± frequency
m both operatmg modes IS 1/8 the PLL operatmg frequency. When the MODE input is left floating or
held at Ved2 the TSER± inputs substitute for the internal PLL VCO for use in factory testing.
Power.
Ground.
Description
Receive Functions
The CY7B951 Local Area Network ATM lJ:ansceiver is used in
SONET/SDH andATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ (Non Return
to Zero) or NRZI (Non Return to Zero Invert on ones) serial
data stream. This device also provides a bit-rate Transmit clock,
from a byte rate source through the use of a frequency multiplier
PLL, and differential data buffering for the Transmit side of the
system (see Figure 1).
Operating Frequency
The CY7B951 operates at either of two frequency ranges. The
MODE input selects which ofthe two frequency ranges the Transmit frequency multiplier PLL and the Receive clock and data recovery PLL will operate. The MODE input has three different
functional selections. When MODE is connected to Vee, the
highest operating range of the device is selected. A 19.44-MHz
± I % source must drive the REFCLK input and the two PLLs will
multiply this rate by 8 to provide output clocks that operate at
155.52 MHz ±l%. When the MODE input is connected to
ground (GND), the lowest operating range of the device is selected. A 6.48-MHz ± I % source must drive the REFCLK inputs
and the two PLLs will mUltiply this rate by 8 to provide output
clocks that operate at 51.84 MHz ±1 %. When the MODE input
is left unconnected or forced to approximately Ved2, the device
enters lest mode.
'fransmit Functions
The primary function of the receiver is to recover clock (RCLK±)
and data (RSER±) from the incoming differential PECL data
stream (RIN ±) without the need for external buffering. These
built-in line receiver inputs, as well as the TSER± inputs mentioned above, have a wide common-mode range (2.5V) and the
ability to receive signals with as little as 50 mV differential voltage.
They are compatible with all PECL signals and any copper media.
The clock recovery function is performed using an embedded
PLL. The recovered clock is not only passed to the RCLK± outputs, but also used internally to sample the input serial stream in
order to recover the data pattern. The Receive PLL uses the
REFCLK input as a byte-rate reference. This input is multiplied
by 8 (REFCLK X 8) and is used to improve PLL lock time and to
provide a center frequency for operation in the absence of input
data stream transitions. The receiver can recover clock and data
in two different frequency ranges depending on the state of the
three-level MODE pin as explained earlier. To insure accurate
data and clock recovery, REFCLK X 8 must be within 1000 ppm
of the transmit bit rate. The standards, however, specify that the
REFCLK X 8 frequency accuracy be within 20-100 ppm.
The differential input serial data (RIN ±) is not only used by the
PLL to recover the clock and data, but it is also buffered and presented as the PECL differential output pair ROUT±. This output
pair can be used as part of the transmission line interface circuit for
base line wander compensation, improving system performance by
providing reduced input jitter and increased data eye opening.
Carrier Detect (CD) and Link Fault Indicator (LFI) Functions
The transmit section ofthe CY7B951 contains a PLL that takes a
REFCLK input and multiplies it by 8 (REFCLK x 8) to produce a
PECL (Pseudo ECL) differential output clock (TCLK±). The
transmitter has two operating ranges that are selectable with the
three-level MODE pin as explained above. The CY7B9511J:ansmit frequency multiplier PLL allows low-cost byte rate clock
sources to be used to time the upstream serial data transmitter as
shown in Figure 1.
The REFCLK± input can be configured three ways. When both
REFCLK + and REFCLK - are connected to a differential
lOOK-compatible PECL source, the REFCLK input will behave
as a differential PECL input. When either the REFCLK - or the
REFCLK + input is at a TTL LOW; the other REFCLK input becomes a TTL-level input allowing it to be connected to a low-cost
TTL crystal oscillator. The REFCLK input structure, therefore,
can be used as a differential PECL input, a single TTL input, or as
a dual TTL clock mUltiplexing input.
The lJ:ansmit PECL differential input pair (TSER±) is buffered
by the CY7B95I yielding the differential data outputs (TOUT±).
These outputs can be used to directly drive transmission media
such as Printed Circuit Board (PCB) traces, optical drivers,
twisted pair, or coaxial cable.
The Link Fault Indicator (LFI) output is a TTL-level output that
indicates the status of the receiver. This output can be used by an
external controller for Loss of Signal (LO~ Loss of Frame
(LOF), or Out of Frame (OaF) indications. LFI is controlled by
the Carrier Detect input, the internal Transitions Detector, and
the PLL Out of Lock (OOL) circuitry.
The CD input may be driven by external circuitry that is monitoring the incoming data stream. Optical modules have CD outputs
that indicate the presence of light on the optical fiber and some
copper based systems use external threshold detection circuitry to
monitor the incoming data stream. The CD input is a lOOK
PECL compatible signal that should be held HIGH when the incoming data stream is valid. When CD is pulled to a PECLLOW
(.5.2.5V Max.), the LFI output will transition LOW and the Receiver PLL will align itself with the REFCLK X 8 frequency and
the recovered data outputs (RSER) will remain LOW regardless
of the signal level on the Receive data-stream inputs (RIN).
In addition, the CY7B951 has a built-in transitions detector that
also checks the quality of the incoming data stream. The absence
of data transition can be caused by a broken transmission media, a
broken transmitter, or a problem with the transmit or receive media coupling. The CY7B951 will detect a quiet link by counting
3-3
E
CY7B951
CY7B951
ROUHS~
ROUTRIN+
RIN-
g; 0
9:;
CD
I
+
TOUH :5 :5
TOUT- ~ ~
ww
a: a:
GPIN
I:FI(t)
RCLK+
RCLK-
RXC+
RXC-
RSER+
RSER-
RXD+
RXD-
PM5345
SUNI
TSER+ ~--------I TXD+
TSERTXDTCLK+
TCLK-
TXCi+
TXCI-
79951-4
Figure 2. CY7B951 to PMC-Sierra PM5345 SUNI Connection Diagram
the number of bit times that have passed without a data transition.
A bit time is defined as the period of RCLK±. When 512 bit
times have passed without a data transition on RIN ±, LFI will
transition LOW. The receiver will assume that the serial data
stream is invalid and, instead of allowing the RCLK± frequency
to wander in the absence of data, the PLL will lock to the
REFCLK*8 frequency. This will insure that RCLK± is as close
to the correct link operating frequency as the REFCLK accuracy.
LFI will be driven HIGH again and the receiver will recover clock
and data from the incoming data stream when the transition
detection circuitry determines that at least 64 transitions have
been detected within 512 bit-times.
The Transition Detector can be turned off by pulling the CD input
to a TTL LOW (':::;'0.8V). When CD is pulled to a TILWW the
LFI will only be driven LOW if the incoming data stream fre~ncy is not within 1000 ppm of the REFCLKX8 frequency.
LFI LOW in this case will only indicate that the Receiver PLL is
Out of Lock (OOL). When this pin is left unconnected, an internal pull-down resistor will pull this input to Ground.
Loop Back Thsting
The TTL level LOOP pin is used to perform loop-back testing.
When LOOP is asserted (held LOW) the Transmitter serial input
(TSER±) is used by the Receiver PLLfor clock and data recovery.
This allows in-system testing to be performed on the entire device
except for the differential1tansmit drivers (TOUT±) and the differential Receiver inputs (RIN ±). For example, an ATM controller can present ATM cells to the input of the ATM cell processor
and check to see that these same cells are received. When the
LOOP input is deasserted (held HIGH) the Receive PLL is once
again connected to the Receiver serial inputs (RIN ±).
The LOOP feature can also be used in applications where clock
and data recovery are to be performed from either of two data
streams. In these systems the LOOP pin is used to select whether
the TSER± or the RIN ± inputs are used by the Receive PLL for
clock and data recovery.
Power Down Modes
There are several power-down features on the CY7B951. Any of
the differential output drivers can be powered down by either tying both outputs to Vee or by simply leaving them unconnected
where internal pull-up resistors will force these outputs to Vee.
This will save approximately 4 rnA per output pair in addition to
the associated output current. If the TOUT± or ROUT± outputs are tied to Vee or left unconnected, the Transmit buffer or
Receive buffer path respectively will be turned off. If the TCLK±
outputs are tied to Vee or left unconnected, the entire Transmit
PLL will be powered down.
By leaving both the RCLK± and RSER± outputs unconnected
or tied to Vee, the entire Receive PLL is turned off. Even though
the Receive PLL may be turned off, the Link Fault Indicator
(LFI) will still reflect the state of the Carrier Detect (CD) input.
This feature can be used for aggressive power management.
Applications
The CY7B951 can be used in Local Area Network ATM applications. The operating frequency of the CY7B951 is centered
around the SONET/SDH STS-l rate of 51.84 MHz and the
SONET/SDH STS-3/STM -1 rate of 155.52 MHz. This device
can also be used in data mover and Local Area Network (LAN)
applications that operate at these frequencies.
The CY7B951 can provide clock and data recovery as well as output buffering for physical layer protocol engines such as the SONET/SDH and ATM processing application shown in Figures 1
and 2
Figure 1 shows the CY7B951 in an ATM system that uses the
PMC-Sierra PM5345 SUNI, or the IgT WAC-013, or the
Brooktree BT8222 device. Assuming that PM5345 SUNI is used,
the CY7B951 will recover clock and data from the input serial
data stream and pass it to the PM5345 SUNI. The SUNI device
will perform serial to parallel conversion, SONET/SDH overhead
processing and ATM cell processing and then pass ATM cells to
an ATM packet reassembly engine. On the Transmit side, a segmentation engine will divide long packets of data such as Ethernet
packets into 53 byte cells and pass them to the SUNI. The SUNI
device will then perform ATM cell processing, such as header generation, SONET/SDH overhead processing and parallel to serial
conversion. This serial data will then be passed to the CY7B951
which will buffer this data stream and pass it along to the transmission media.
The CY7B951 provides the necessary clock and data recovery
function to the PM5345. These differential PECL clock and data
signals interface directly with the RXD ± and RXC± inputs ofthe
SUNI device as show in Figure 2. In addition, the CY7B951 provides transmit data output buffering for direct drive of cable
transmission media. Lastly, the CY7B951 provides a bit rate reference clock to the SUNI transmitter by multiplying a local clock
by eight allowing an inexpensive crystal oscillator to be used for
the local reference.
3-4
CY7B951
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................... -65°C to + 150°C
Ambient Temperature with
Power Applied ........................ -55°C to + 125°C
Supply Voltage to Ground Potential ......... -0.5V to + 7.0V
DC Input Voltage ........................ -O.5V to +7.0V
Output Current into TTL Outputs (LOW) ........... 30 rnA
Output Current into ECL Outputs (HIGH) ........ -50 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature[l J
O°C to +70°C
5V ± 10%
-40°C to +85°C
5V ± 10%
Vee
Notes:
1. TA is the "instant on" case temperature.
E
3-5
CY7B951
Electrical Characteristics Over the Operating Range
Description
Parameter
Thst Condition
TTL Compatible Input Pins (LOOP, REFCLK +, REFCLK - )
Input HIGH Voltage
VIHT
Input LOW Voltage
VILT
REFCLK
Input HIGH Current
VIN=Vee
IlIff
LOOP
VIN=Vee
REFCLK
VIN=O.OV
Input LOW Current
lILT
LOOP
VIN=O.OV
TTL Compatible Output Pins (LFI)
Output HIGH Voltage
IOH=-2rnA
VOHT
Output LOW Voltage
IOL-4rnA
VOLT
VOUT=OVl2]
Output Short Circuit Current
lOST
ECL Compatible Input Pins (REFCLK ± CD, TSER±, RIN ±)
REFCLK/CD
ECL Input HIGH Current
VIN- VIHE(MAX)
IIHE
TSERIRIN
VIN-VIHE(MAX)
lILE[3]
REFCLKlCD
ECL Input LOW Current
VIN= VILE(MIN)
TSERIRIN
VIN= VILE(MIN)
TSERIRIN
Input Differential Voltage
VIDIFF
REFCLK
TSERJRIN
Input High Voltage
VIHE
REFCLK
CD
TSERJRIN
Input LOW Voltage
VILE
REFCLK
CD (ECL)
CD (Disable)
ECL Compatible Output Pins (ROUT±,RCLK ±,RSER±,TOUT±,TCLK±)
Commercial
ECL Output HIGH Voltage
VOHE
Industriall']
ECL Output LOW Voltage
T>O'C
VOLE
Output Differential Voltage
VODIFF
Three-Level Input Pins (MODE)
Three-Level Input HIGH
VIHH
Three-Level Input MID
VIMM
Three-Level Input LOW
VILL
Operating Current15 J
Static Operating Current
Ices
Receiver Operating Current
leeR
ltansmitter Operating Current
leeT
ECL Pair Operating Current
leCE
Additional Current at 51.84 MHz
leC5
Additional Current LFI-LOW
leeo
Min.
Max.
Unit
2.0
-0.5
+0.5
-10
-50
-500
Vee
0.8
+200
+10
+50
V
V
2.4
-15
+0.5
-200
50
100
3.0
Vee - 1.165
2.0
2.5
2.5
-0.5
CIN
Description
Input Capacitance
+250
+750
!JA
!JA
!JA
!JA
1200
1200
mV
mV
V
V
V
V
V
V
V
Vee
Vee
Vee
Vee-1.475
0.8
Vee- 0.83
Vee - 0.83
Vee-1.62
V
Vee - 0.75
Ved2 - 0.5
0.0
Vee
Ved2 + 0.5
0.75
V
V
V
30
50
13
7.0
7.0
3
rnA
rnA
rnA
rnA
rnA
rnA
Thst Conditions
TA = 25°C, fo = 1 MHz, Vee = 5.0V
3-6
V
V
rnA
Vee- 1.03
Vee - 1.08
Vee-1.86
0.6
Capacitancd6]
Parameter
0.45
-90
!JA
!JA
!JA
!JA
V
V
=
---."..
-,,~
CY7B951
r;CYPRESS
AC Test Loads and Waveforms
OUTPUT
-ii
clI
R1 = 910Q
R2 = 510Q
Cl<30pF
(Includes fixture and
probe capacitance)
-
R1
v
Rl = 50Q
Cl < 5 pF
(Includes fixture and
probe capacitance)
R2
-
78951-7
(b) ECL AC Test Load[7]
(a) TTL AC Test Load[7]
3.0V
E
3.0V---2.0V
1.0V
GND
S 1 ns
78951-6
78951-5
(c) TTL Input Test Waveform
(d) ECL Input Test Waveform
Switching Characteristics Over the Operating Range
Min.
Max.
Unit
fREF
Reference Frequency
MODE-LOW
6.41
6.55
MHz
MODE-HIGH
19.24
19.64
MHz
fB
Bit Timel 8]
MODE-LOW
19.5
19.1
ns
MODE=HIGH
6.50
6.40
ns
MODE-LOW
100
ps
MODE-HIGH
200
ps
Parameter
tPE
Description
Receiver Static Phase Error[6]
tooc
Output Duty Cycle (TCLK±, RCLK±)IDJ
48
52
%
tRF
Output Rise/Fall Time l6J
0.4
1.2
ns
tLOCK
PLL Lock Time (RIN transition density 25% )[9
tRPWH
REFCLK Pulse Width HIGH
10
100
fts
ns
tRPWL
REFCLK Pulse Width LOW
10
ns
tov
Data Valid
3
ns
tOH
Data Hold
1
tpo
Propagation Delay (RIN to ROUT, TSER to TOUT)llOJ
Notes:
2. Tested one output at a time, output shorted for less than one second.
less than 10% duty cycle.
3. Input currents are always positive at all voltages above V ccl2.
4. Specified only for temperatures below O°C.
S. Total Receiver operating current (assuming that the Transmitter is not
activated) can be found by adding Iccs + ICCR + x * ICCE; where x is
2 if the ROUT± outputs are not activated and 3 if they are activated.
Total Transmitter operating current (assuming that the Receiver is not
activated) can be found by adding Ices + lcer + x * lCCE; where x is
1 if the TOUT± outputs are not activated and 2 if they are activated.
Thtal device power (assuming that the Transmitter and the Receiver
are activated) can be found by adding Ices + lCCR + lcer + x * lCCE;
where x represents the number of ECL output pairs activated.
6.
ns
10
ns
Tested initially and after any design or process changes that may affect
these parameters.
7. Cypress uses constant current (ATE) load configurations and forcing
functions. This figure is for reference only_
8. fB is calculated as 1/(fREFX8).
9. tLOCK is the time needed for transitioning from lock to REFCLK X8
to lock to data.
10. The ECL switching threshold is the differential zero crossing (i.e., the
place where + and - signals cross).
3-7
CY7B951
tisrcYPRESS
Switching Waveforms for the CY7B951 SONET/SDH Serial 'fransceiver
REFCLK
78951-8
TSER±
(RIN±)
TOUT±
(ROUT±)
78951-9
~tooe
tooe
If
RCLK+
If
1\
---1
1
toy
RSER±
tOH-
W
'If
Ji\
11\
78951-10
RIN±
78951-11
Ordering Information
Speed
(ns)
25
Ordering Code
Package
Name
Package 'JYpe
Operating
Range
CY7B951-SC
S13
24-Lead (300-Mil) Molded SOIC
Commercial
CY7B951-SI
S13
24-Lead (300-Mil) Molded SOIC
Industrial
Document #: 38-00358-0
3-8
CY7B952
PRELIMINARY
SSTTM
SONET/SDH Serial Transceiver
Features
• Fully compliant with Bellcore and
CClTT (lTV) specifications on:
-Jitter Generation «0.01 VI)
- Jitter Transfer ( < 130 kHz)
- Jitter Tolerance
• SONET/SDH and ATM Compliant
• Compatible with PMC-Sierra
PM5343
• Clock and data recovery from 51.84or 155.52-MHz datastream
• 155.52-MHz clock multiplication from
19.44-MHz source
• 51.84-MHz clock multiplication from
6.48-MHz source
• ± 1% frequency agility
• Line Receiver Inputs: No external
buffering required
• Differential output buffering
• lOOK ECL compatible I/O
• No output clock "drift" without data
transitions
• Link Status Indication
• Loop-back testing
• Single +5V supply
• 24-piu SOIC
• Compatible with fiber-optic modules,
coaxial cable, and twisted pair media
• No external PLL components
Logic Block Diagram
!DOPe!)
• Power-down options to minimize
power or crosstalk
• Low operating current: <65 rnA
• 0.8!! BiCMOS
Functional Description
The SONET/SDH Serial ltansceiver·
(SST) is used in Wide Area Network
(WAN) SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz
NRZ or NRZI serial data stream and to
provide differential data buffering for the
ltansmit side of the system.
Pin Configuration
MODE
SOIC
Top View
ROUT +--t--::,..,...--,
ROUT ---I--"'~
RCLK+
RCLKRSER+
RSER-
RIN+
RIN-
CD
[FI(t)
TOUT+---r-,..,...~~~t-------~,..,...-+~
TOUT--~~~~-+4----~~~
ROUT+
ROUTRIN+
RINMODE
RCLKRCLK+
RSERRSER+
rn
Vee
Vee
CD
[0015
REFCLKREFCLK+
TOUTTOUT+
Vss
Vee
TCLKTCLK+
TSER+
TSER-
TSER+
TSER-
78952-2
TCLK+
TCLK78952-1
REFCLK+
SST
S->P
P->S
Cypress
CY78952
SONET/SDH
SONET/SDH
Transport
Overhead
Transceiver
Overhead
Transceiver
PMC-Sierra
PM5343STXC
Path
PMC-Sierra
PM5344SPTX
Figure 1. SONET/SDH Overhead Processing Application
SST is a trademark of Cypress Semiconductor Corporation
SUNI is a trademark of PMC-Sierra, Incorporated
3-9
78952-3
PRELIMINARY
CY7B952
Pin Descriptions
Name
RIN±
I/O
Differential
In
ROUT±
ECLOut
RSER±
ECLOut
RCLK±
ECLOut
CD
TTUECLIn
LFI
TIL Out
TSER±
Differential
In
TOUT±
ECLOut
REFCLK±
DifffITLIn
TCLK±
ECLOut
r:m:>P
TIL In
Description
Receive Input. This line receiver port connects the receive differential serial input data stream to the
internal Receive PLL. This PLL will recover the embedd clock (RCLK±) and data (RSER±) information for one of two data rates depending on the state of the MODE pin. These inputs can receive very
low amplitude signals and are compatible with all PECL signalling levels. If the RIN ± inputs are not
being used, connect RIN + to Vee and RIN - to V ss.
Receive Output. These ECL lOOK outputs (+5V referenced) represent the buffered version of the
input data stream (RIN ±). This output pair can be used for Receiver input data equalization in copper
based systems, reducing the system impact of data dependent jitter. All PECL outputs can be powered
down by connecting both outputs to Vee or leaving them both unconnected.
Recovered Serial Data. These ECL 100Koutputs ( + 5V referenced) represent the recovered data from
the input data stream (RIN ±). This recovered data is aligned with the recovered clock (RCLK±) with
a sampling window compatible with most data processing devices.
Recovered Clock. These ECL lOOK outputs ( +5V referenced) represent the recovered clock from the
input data stream (RIN ±). This recovered clock is used to sample the recovered data (RSER±) and
has timing compatible with most data processing devices. If both the RSER± and the RCLK± are tied
to Vee or left unconnected, the entire Receive PLL will be powered down.
Carrier Detect. This input controls the recovery function of the Receive PLL and can be driven by the
carrier detect outputfrom optical modules or from external transition detection circuitry. When this input is at an ECL HIGH, the input data stream (RIN ± lc is recovered normally by the Receive PLL.
When this input is at an ECL LOW, the Receive PLL no onger aligns to RIN ±, but instead aligns with
the REFCLKx 8 frequency. Also, the Link Fault Indicator (LFI) will transition LOW, and the recovered data outputs (RSER) will remain LOW regardless of the signal level on the Receive data-stream
inputs (RIN). When the CD input is at a TTL LOW, the internal transitions detection circuitry is disabled.
Link Fault Indicator. This output indicates the status ofthe input data stream (RIN ±). It is controlled
by three functions; the Carrier Detect (CD) input, the internal 'Itansition Detector, and the Out of Lock
(OOL) detector. The 'Itansition Detector determines if RIN ± contains enough transitions to be accurately recovered by the Receive PLL. The Out of Lock detector determines if RIN ± is within the frequency range of the Receive PLL. When CD is HIGH and RIN ± has sufficient transitions and is within
the frequency range of the Receive PLL, the LFI output will be HIGH. If CD is at an ECL LOW or
RIN ± does not contain sufficient transitions or RIN ± is outside the fr~ency range of the Receive
PLL then the LFI output will be LOW. If CD is at a TIL LOW then the LFI output will only transition
LOW when the frequency of RIN ± is outside the range of the Receive PLL.
'Itansmit Serial Data. This line receiver port connects the transmit differential serial input data stream
to the TOUT transmit buffers. Depending on the state of the LOOP pin, this input port can also be set
up to supply the serial input data stream to the Receive PLL. These inputs can receive very low amplitude signals and are compatible with all PECL signalling levels. If the TSER± inputs are not being
used, connect TSER + to Vee and TSER - to Vss.
'Itansmit Output. These ECL lOOK outputs ( + 5V referenced) represent the buffered version of the
'Itansmit data stream (TSER±). This 'Itansmit path is used to take weak input signals and rebuffer them
to drive low impedance cOpper media.
Reference Clock. This input is the clock frequency reference for the clock and data recovery Receive
PLL. REFCLKis multiplied internally by eight and sets the approximate center frequency for the internal Receive PLL to track the incoming bit stream. This input is also mUlti)lied by eight by the frequency
multiplier 'Itansmit PLL to produce the bit rate Transmit Clock (TCLK± . REFCLKcan be connected
to either a differential PECL or single-ended TTL frequency source. When either REFCLK + or
REFCLK - is at a TIL LOW, the opposite REFCLK signal becomes a TIL level input.
Transmit Clock. These ECL lOOK outputs ( + 5V referenced) provide the bit rate frequency source for
external 'Itansmit data processing devices. This output is synthesized by the 'Itansmit PLL and is derived
by multiplying the REFCLK frequency by eight. When this outgut is turned off, the entire 'Itansmit
PLL is powered down. All PECL outputs can be powered down y connecting both outputs to Vee or
leaving them both unconnected.
Loop Back Select. This input is used to select the input data stream source that the Receive PLL uses for
clock and data recovery. When the LOOP input is HIGH, the Receive input data stream (RIN ± ~ is
used for clock and data recovery. When LOOP is LOW, the Transmit input data stream (TSER± is
used by the Receive PLL for clock and data recovery.
3-10
PRELIMINARY
CY7B952
Pin Descriptions (continued)
Name
MODE
Vee
Vss
I/O
3-Level In
Description
Frequency Mode Select. This three-level input selects the frequency range for the clock and data recovery Receive PLL and the frequency multiplier Transmit PLL. When this input is held HIGH the two
PLLs operate at the SONET (SDH) STS- 3 (STM -1) line rate of155.52 MHz. When this input is held
LOW the two PLLs operate at the SONET STS -1 line rate of 51.84 MHz. The REFCLK± frequency
in both operating modes is 1/8 the PLL operating frequency. When the MODE input is left floating or
held at Ved2 the TSER± inputs substitute for the internal PLL VCO for use in factory testing.
Power.
Ground.
Description
Receive Functions
The CY7B952 Serial SONET/SDH Transceiver (SST) is used in
SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ (Non Return
to Zero) or NRZI (Non Return to Zero Invert on ones) serial
data stream. This device also provides a bit-rate Transmit clock,
from a byte rate source through the use of a frequency multiplier
PLL, and differential data buffering for the Transmit side of the
system. This device is fully compliant with all relevant SONET/
SDH specifications including Bellcore TR - NWT -00253, ANSI
T1X1.6/91 -022, and CCITT G958.
Operating Frequency
The primary function of the receiver is to recover clock (RCLK±)
and data (RSER±) from the incoming differential PECL data
stream (RIN ±) without the need for external buffering. These
built-in line receiver inputs, as well as the TSER± inputs mentioned above, have a wide common-mode range (2.5V) and the
ability to receive signals with as little as 50 mV differential voltage.
They are compatible with all PECL signals and any copper media.
The clock recovery function is performed using an embedded
PLL. The recovered clock is not only passed to the RCLK± outputs, but also used internally to sample the input serial stream in
order to recover the data pattern. The Receive PLL uses the
REFCLK input as a byte-rate reference. This input is multiplied
by 8 (REFCLK X 8) and is used to improve PLL lock time and to
provide a center frequency for operation in the absence of input
data stream transitions. The receiver can recover clock and data
in two different frequency ranges depending on the state of the
three-level MODE pin as explained earlier. Th insure accurate
data and clock recovery, REFCLKx8 must be within 1000 ppm
of the transmit bit rate. The standards, however, specify that the
REFCLK X 8 frequency accuracy be within 20-100 ppm.
The differential input serial data (RIN ±) is not only used by the
PLL to recover the clock and data, but it is also buffered and presented as the PECL differential output pair ROUT±. This output
pair can be used as part ofthe transmission line interface circuit for
base line wander compensation, improving system performance by
providing reduced input jitter and increased data eye opening.
The Receive PLLis fully compliant with the Bellcore jitter generation, jitter transfer, and jitter tolerance specifications.
Carrier Detect (CD) and Link Fault Indicator (LFI) Functions
The SST operates at either of two frequency ranges. The MODE
input selects which of the two frequency ranges the 1tansmit frequency multiplier PLL and the Receive clock and data recovery
PLL will operate. The MODE input has three different functional selections. When MODE is connected to Vee, the highest operating range ofthe device is selected. A 19.44-MHz ± 1% source
must drive the REFCLK input and the two PLLs will multiply this
rate by 8 to provide output clocks that operate at 155.52 MHz
±1 %. When the MODE input is connected to ground (GND),
the lowest operating range ofthe device is selected. A 6.48-MHz
± 1% source must drive the REFCLK inputs and the two PLLs
will mUltiply this rate by 8 to provide output clocks that operate at
51.84 MHz ±1 %. When the MODE input is left unconnected or
forced to approximately Ved2, the device enters Test mode.
'fransmit Functions
The transmit section of the SST contains a PLL that takes a
REFCLK input and multiplies it by 8 (REFCLK X 8) to produce a
PECL (Pseudo ECL) differential output clock (TCLK±). The
transmitter has two operating ranges that are selectable with the
three-level MODE pin as explained above. The SST1tansmit frequency multiplier PLL allows low-cost byte rate clock sources to
be used to time the upstream serial data transmitter
The REFCLK± input can be configured three ways. When both
REFCLK + and REFCLK - are connected to a differential
lOOK-compatible PECL source, the REFCLK input will behave
as a differential PECL input. When either the REFCLK - or the
REFCLK + input is at a TTL Law, the other REFCLK input becomes a TTL-level input allowing it to be connected to a low-cost
TTL crystal oscillator. The REFCLK input structure, therefore,
can be used as a differential PECL input, a single TTL input, or as
a dual TTL clock multiplexing input.
The 1tansmit PECL differential input pair (TSER±) is buffered
by the SST yielding the differential data outputs (TOUT±).
These outputs can be used to directly drive transmission media
such as Printed Circuit Board (PCB) traces, optical drivers,
twisted pair, or coaxial cable.
The Link Fault Indicator (LFI) output is a TTL-level output that
indicates the status ofthe receiver. This output can be used by an
external controller for Loss of Signal (LO~ Loss of Frame
(LOF), or Out of Frame (OaF) indications. LFI is controlled by
the Carrier Detect input, the internal1tansitions Detector, and
the PLL Out of Lock (OOL) circuitry.
The CD input may be driven by external circuitry that is monitoring the incoming data stream. Optical modules have CD outputs
that indicate the presence of light on the optical fiber and some
copper based systems use external threshold detection circuitry to
monitor the incoming data stream. The CD input is a lOOK
PECL compatible signal that should be held HIGH when the incoming data stream is valid. When CD is pulled to a PECL LOW
(~2.5V Max.), the m output will transition LOW and the Receiver PLL will align itself with the REFCLKx8 frequency and
the recovered data outputs (RSER) will remain LOW regardless
of the signal level on the Receive data-stream inputs (RIN).
In addition, the SST has a built-in transitions detector that also
checks the quality of the incoming data stream. The absence of
data transition can be caused by a broken transmission media, a
broken transmitter, or a problem with the transmit or receive me-
3-11
PRELIMINARY
'k?cYPRESS
dia coupling. The SST will detect a quiet link by counting the
number of bit times that have passed without a data transition. A
bit time is defined as the period of RCLK±. When 512 bit times
have passed without a data transition on RIN ±, LFI will transition LOW. The receiver will assume that the serial data stream is
invalid and, instead of allowing the RCLK± frequency to wander
in the absence of data, the PLL will lock to the REFCLK*8 frequency. This will insure that RCLK± is as close to the correct
link operating frequency as the REFCLK accuracy. LFI will be
driven HIGH again and the receiver will recover clock and data
from the incoming data stream when the transition detection circuitry determines that at least 64 transitions have been detected
within 512 bit-times.
The 1l:ansition Detector can be turned offby pulling the CD input
to a TIL LOW (sO.8V). When CD is pulled to a TTL LOW the
LFI will only be driven LOW if the incoming data stream fre~ncy is not within 1000 ppm of the REFCLKx8 frequency.
LFI LOW in this case will only indicate that the Receiver PLL is
Out of Lock (OOL). When this pin is left unconnected, an internal pull-down resistor will pull this input to Ground.
Loop Back Testing
The TIL level LOOP pin is used to perform loop-back testing.
When LOOP is asserted (held LOW) the 1l:ansmitter serial input
(TSER±) is used by the Receiver PLLfor clock and data recovery.
This allows in-system testing to be performed on the entire device
except for the differential1l:ansmit drivers (TOUT±) and the differential Receiver inputs (RIN ±). For example, an ATM controller can present ATM cells to the input of the ATM cell processor
and check to see that these same cells are received. When the
LOOP input is deasserted (held HIGH) the Receive PLL is once
again connected to the Receiver serial inputs (RIN ±).
The LOOP feature can also be used in applications where clock
and data recovery are to be performed from either of two data
streams. In these systems the LOOP pin is used to select whether
the TSER± or the RIN ± inputs are used by the Receive PLL for
clock and data recovery.
Power Down Modes
There are several power-down features on the SST. Any of the
differential output drivers can be powered down by either tying
CY7B952
both outputs to Vee or by simply leaving them unconnected
where internal pull-up resistors will force these outputs to Vee.
This will save approximately 4 rnA per output pair in addition to
the associated output current. If the TOUT± or ROUT± outputs are tied to Vee or left unconnected, the 1l:ansmit buffer or
Receive buffer path respectively will be turned off. If the TCLK±
outputs are tied to Vee or left unconnected, the entire 1l:ansmit
PLL will be powered down.
By leaving both the RCLK± and RSER± outputs unconnected
or tied to V ce, the entire Receive PLL is turned off. Even though
the Receive PLL may be turned off, the Link Fault Indicator
(LFI) will still reflect the state of the Carrier Detect (CD) input.
This feature can be used for aggressive power management.
Applications
The SST can provide clock and data recovery as well as output
buffering for physical layer protocol engines such as those used in
WAN SONET/SDH and ATM applications. The operating frequency of the 7B952 is centered around the SONET/SDH STS-l
rate of 51.84 MHz and the SONET/SDH STS - 3/STM -1 rate of
155.52 MHz. This device can also be used in data mover, Local
Area Network (LAN) applications that operate at these frequencies.
In an ATM system, the SST is used to recover clock and data
from an input SONET/SDH serial data stream for subsequent
chips to do serial to parallel conversion, SONET/SDH overhead
processing, ATM cell processing, and switching. On the 1l:ansmit
side, ATM cells coming out of a switching matrix goes through
ATM cell processing, SONET/SDH overhead processing and parallel to serial conversion before passing to the SST which buffers
the data stream and drive the transmission media.
In a more generic telecommunications system (Figure 1), the SST
is used to provide clock and data recovery for a pure SONET/
SDH system such as a SONET/SDH switch. The SST provides
the recovered clock and data to a serial to parallel converter and
SONET/SDH Transport Overhead Processor such as the PMCSierra PM5343 STXC. The parallel data is then passed to a SONET/SDH Path Overhead Processor such as the PMC-Sierra
PM5344 SPTX.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Thmperature with
Power Applied ........................ -55°C to + 125°C
Supply Voltage to Ground Potential ......... -0.5V to +7.0V
DC Input Voltage ........................ -O.5V to +7.0V
Output Current into TTL Outputs (LOW) ........... 30 rnA
Output Current into ECL Outputs (HIGH) ........ -50 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Notes:
1. TA is the "instant on" case temperature.
3-12
Range
Commercial
Industrial
Ambient
Temperature[l]
O°Cto +70°C
Vee
5V± 10%
-40°C to +85°C
5V ± 10%
PRELIMINARY
CY7B952
Electrical Characteristics Over the Operating Range
Parameter
Description
Thst Condition
TTL Compatible Input Pins (LOOP, REFCLK +, REFCLK - )
Input HIGH Voltage
VIHr
Input LOW Voltage
VILT
REFCLK
Input HIGH Current
VIN=Vee
IIHr
LOOP
YIN-Vee
REFCLK
VIN-O.OV
Input LOW Current
lILT
LOOP
VIN-O.OV
TTL Compatible Output Pins (LFI)
Output HIGH Voltage
IOH=-2rnA
VOHT
Output LOW Voltage
IOL=4rnA
VOLT
Output Short Circuit Current
VOUT=OVl2]
lOST
ECL Compatible Input Pins (REFCLK±, CD, TSER±, RIN±)
REFCLK/CD
ECL Input HIGH Current
VIN= VIHE(MAX)
Inrn
TSERJRIN
VIN= VIHE(MAX)
IILE[3]
REFCLK/CD
ECL Input LOW Current
VIN= VILE(MIN)
TSER/RIN
VIN-VILE(MIN)
TSER/RIN
Input Differential Voltage
VIDIFF
REFCLK
TSERJRIN
Input High Voltage
VIHE
REFCLK
CD
TSER/RIN
Input LOW Voltage
VILE
REFCLK
CD (ECL)
CD (Disable)
ECL Compatible Output Pins (ROUT±, RCLK±, RSER±, TOUT±, TCLK±)
Commercial
ECL Output HIGH Voltage
VOHE
Industriall4 ]
ECL
Output
LOW
Voltage
T>O°C
VOLE
Output Differential Voltage
VODIFF
Three-Level Input Pins (MODE)
Three-Level Input HIGH
VIHH
Three-Level Input MID
VIMM
Three-Level Input LOW
VILL
Operating CurrentL']
Ices
leeR
leer
IeeE
Ices
Ieeo
Min.
Max.
Unit
2.0
-0.5
Vee
0.8
+200
+10
+50
V
V
+0.5
-10
-50
-500
2.4
-15
+0.5
-200
50
100
3.0
Vee - 1.165
2.0
2.5
2.5
-0.5
+250
+750
ttA
ttA
ttA
ttA
1200
1200
mV
mV
V
V
V
V
V
V
V
Vee
Vee
Vee
Vee~
1.475
0.8
Vee- 0.83
Vee - 0.83
Vee-1.62
Vee - 0.75
VecJ2 - 0.5
0.0
Vee
Ved2 + 0.5
0.75
V
V
V
30
50
rnA
rnA
rnA
rnA
rnA
rnA
13
7.0
7.0
3
Capacitance[6]
Description
Input Capacitance
Thst Conditions
TA = 25°C, fo = 1 MHz, Vee = 5.0V
3-13
V
V
rnA
Vee-1.03
Vee - 1.08
Vee - 1.86
0.6
Static Operating Current
Receiver Operating Current
1tansmitter Operating Current
ECL Pair Operating Current
Additional Current at 51.84 MHz
Additional Current LFI=LOW
Parameter
0.45
-90
ttA
ttA
ttA
ttA
V
V
V
I
PRELIMINARY
ILrcYPRESS
CY7B952
AC Test Loads and Waveforms
OUTPUT
R1 = 9100
R2 = 5100
CL<30pF
-ii
CLI
(Includes fixture and
probe capacitance)
-
R1
v
CL
RL = 500
< 5 pF
(Includes fixture and
probe capacitance)
R2
-
(a) TTL AC Test Load[7]
78952-6
(b) ECL AC Test Load[7]
3.0V
VIHE
3.0V--2.0V
GND
VILE
78952-5
78952-4
(c) TTL Input Test Waveform
(d) ECL Input Test Waveform
Switching Characteristics Over the Operating Range
Parameter
Description
fREF
Reference Frequency
fB
Bit Timd8]
tpE
Receiver Static Phase Error[6]
Min.
Max.
Unit
MODE-LOW
6.41
6.55
MHz
MODE-HIGH
19.24
19.64
MHz
MODE-LOW
19.5
19.1
ns
MODE-HIGH
6.50
6.40
ns
MODE-LOW
100
ps
MODE-HIGH
200
ps
tODe
Output Duty Cycle (TCLK±, RCLK± )!oJ
48
52
%
tRF
Output Rise/Fall Time!oJ
0.4
1.2
ns
tLOCK
PLL Lock Time (RIN transition density 25%)
0.5
ms
tRPWH
REFCLK Pulse Width HIGH
10
ns
tRPWL
REFCLK Pulse Width LOW
10
ns
tov
Data Valid
3
ns
tOH
Data Hold
1
ns
tpo
Propagation Delay (RIN to ROUT, TSER to TOUT)!"J
Jitter Generation
Jitter Generation of RX PLL
L3dB
- 3 dB Gain Bandwidth of RX PLL
(Jitter 1tansfer Bandwidth)
Gpeak
Maximum Peaking of RX PLL
Notes:
2. Thsted one output at a time, output shorted for less than one second,
less than 10% duty cycle.
3. Input currents are always positive at all voltages above Vcd2.
4. Specified only for temperatures below 0° C.
5. Total Receiver operating current (assuming that the Transmitter is not
activated) can be found by adding Ices + ICCR + x • ICCE; where x is
2 if the ROUT± outputs are not activated and 3 if they are activated.
Thtal1tansmitter operating current (assuming that the Receiver is not
activated) can be found by adding Ices + Icer + x • ICCE; where x is
1 if the TOUT± outputs are not activated and 2 if they are activated.
6.
7.
8.
9.
3-14
10
ns
0.01
UIrms
@155MHz
130
kHz
@52MHz
45
kHz
0.1
dB
Total device power (assuming that the 1tansmitter and the Receiver
are activated) can be found by adding Iccs + ICCR + Icer + x· ICCE;
where x represents the number of ECL output pairs activated.
Thsted initially and after any design or process changes that may affect
these parameters.
Cypress uses constant current (ATE) load configurations and forcing
functions. This figure is for reference only.
fB is calculated a 1/(fREFx8).
The EeL switching threshold is the differential zero crossing (Le., the
place where + and - signals cross).
~-,~
PRELIMINARY
a'CYPRESS
CY7B952
Switching Waveforms for the CY7B952 SONET/SDH Serial 'fransceiver
REFCLK
76951-7
TSER±
(RIN±)
E1
TOUT±
(ROUT±)
78951-8
_IOOC
/
RCLK+
--1
,
looc_
\
/
1/
lov
IOH-
"
/
RSER±
J\
/\
76951-9
RIN±
76951-10
Ordering Information
Speed
(ns)
25
Ordering Code
Package
Name
Package 1YPe
Operating
Range
CY7B952-SC
S13
24-Lead (300-Mil) Molded SOlC
Commercial
CY7B952-SI
S13
24-Lead (300-Mil) Molded SOlC
Industrial
Document #: 38-00502
3-15
This is an abbreviated version of this datasheet. For the complete version, please contact
your Cypress Marketing Representative.
ADVANCED INFORMATION
CY7C955
ATM -SONET/SDH Transceiver
Features
• WAN and LAN ATM physical layer
device
• Provides complete physical layer
transport of ATM cells at
-STS-3c/ STM-1 rate of l55.52MHz
-STS-1 rate of 5l.84MHz
• Compliant with ATM Forum User
Network Interface 3.1 specification
• UTOPIA ATM interface
• ATM cell processing including
-nEC generation/verification
-Cell scramblingldescrambling
-Rate adaption/idle cell filtering
-Local Flow Control
TTTTTt
RDB
WRB
CSB
INTB
RSTB
VCLK
RALM
::
~
~
Controller
Interface
';:
::
Receive
UTOPIAJIF
Receive FIFO
4 Cell by 8 bit
l
~UJ.q
Transmit
ATMCell
Processor
I
I
Transmit
Path
Overhead
Processor
TTT
Transmit
Section
Overhead
Processor
Transmit
Line
Overhead
Processor
Conliguration and Status
Register FUe
I
Error Monitoring
Receive
ATMCeII
Processor
• Alarm indications including
-Loss Of Signal
-Out Of Frame, Loss Of Frame
-Line Far End Receive Failure
-Line Alarm Indication Signal
-B1 Parity Error
-Loss Of Cell Alignment
-Loss Of Receive Data
• Controller interface for internal
interrupt and configuration registers
-Error monitoring
-Status indication
-Device configuration
• 0.651-1 low-power CMOS
f f
t TT
Transmit
UTOPIAJIF
Transmit FIFO
4 Cell by 8 bit
D[7:0]
A[7:0]
ALE
-Cell alignment
• SONET frame processing including
-Compliant with, Bellcore GR-253,
T1.105 1.432, and G.709
-Frame generation/recovery
-SONET scramblingldescrambling
-Frequency justification/pointer
processing
• Complete line interface
-Clock and data recovery
-Transmit timing derived from
receiver or byte - rate source
-No external PLL components
-SONET compliant PLL
-lOOK EeL compatible I/O
Receive
Path
Overhead
Processor
Receive
Line
Overhead
Processor
U
II
Transmit
Clock
Multiplier &
Transmit
Buffer
::
TXD+/TXC+/-
::
:::
ALOS+/RRCLK+/RXD+/RXDO+I-
-< TRCLK+/-
Rate
Selection
Receive
Section
Overhead
Processor
SONET/SDH
Clock
Recovery
J.
7C955-1
Document #: 38-00417
3-16
Interfacing with the SSTTM
input and the transmit PLL will multiply this rate by
8 to provide an output clock that operates at 155.52
MHz ± 1%. When the MODE input is connected to
ground (GND), the lowest operating range of the
This application note describes how to interface the
CY7B951 SONET/SDH Serial Transceiver (SST"')
with other physical-layer devices. The SST performs clock and data recovery from a SONET/SDH
(Synchronous Optical NEThrorkiSynchronous Digital Hierarchy) 51.84 Mb/s or 155.52 Mb/s interface
and can be used in a variety of SONET and ATM applications. The application note will begin with a
brief introduction to the SST. Next, interface examples will be given that illustrate how to connect the
SST to three different ATM controller devices; the
first from PMC-Sierra called the PM5345 SUNI, the
second, also from PMC-Sierra, called the S/UNILITE, and the third from Integrated Telecom
Technologies (IgT) called the WAC-013.
amP(t)
MODE
ROUT·-r---!-"""--,
ROUT ---IP-.t--.
RIN+ _--J-l'--'~
RIN- - - - 1 - 1 . . - - - 1
1---"'--1-.... RCLK+
PLL 1 - - -.........; -.... RCLK1---0/'--4-.... RSER+
r--1r--t-.... RSERt--i>--t-.... LFI(t)
CD
Introduction
TOUT +--+-;l1-t.......-+-+----~++_.... TSER+
TOUTTSER-
The CY7B951 SST is used in SONET/SDH applications to recover clock and data information from a
155.52-MHz or 51.84-MHz NRZ (Non Return to
Zero) or NRZI (Non Return to Zero Invert on
ones) serial data stream. This device also provides
a bit-rate Transmit Clock, from a byte-rate source
through the use of a frequency multiplier PhaseLocked Loop (PLL), and differential data buffering
for the 1tansmit side of the system (see Figure 1).
The pinout is shown in Figure 2.
1---~4-..... TCLK+
t - - I r - - t - - TCLK-
REFCLK+
REFCLK-
Figure 1. SST Block Diagram
sOle
Top View
ROUT+
ROUTRIN+
RINMODE
VCC
CD
amP
REFCLKREFCLK+
TOUTTOUT+
Operating Frequency
The SST operates at either of two frequency ranges.
The MODE input selects which of the two frequency ranges the Transmit frequency multiplier PLL
and the Receive clock and data recovery PLL will
operate. When MODE is connected to Vee, the
highest operating range of the device is selected. A
19.44-MHz ±1% source must drive the REFCLK
RCLKRCLK+
RSERRSER+
LFI
VCC
VSS
VCC
TCLKTCLK+
TSER+
TSER-
Figure 2. SST Pinout
3-17
-.~
Interfacing with the SST
-:;;;]JjjjjI, CYPRESS = = = = = = = = = = = = = = = = = =
4i
device is selected. A 6.48-MHz ± 1% source must
drive the REFCLK inputs and the transmit PLL will
multiply this rate by 8 to provide an output clock that
operates at 51.84 MHz ± 1%. In addition, when the
MODE input is left unconnected or forced to
approximately Vcd2, the device enters Test Mode.
and any copper media (such as coaxial cable or
twisted pair).
The clock recovery function is performed using an
embedded PLL. The recovered clock is not only
passed to the RCLK± outputs, but also used internally to sample the input serial stream in order to recover the data pattern. The Receive PLL uses the
REFCLK input as a byte-rate reference. This input
is multiplied by 8 (REFCLK*8) and is used as a bitrate reference in comparison to the recovered clock
to improve PLL lock time, and to provide a center
frequency for operation in the absence of input data
stream transitions. The Receiver can recover clock
and data in two different frequency ranges depending on the state of the three-level MODE pin, as explained earlier. To ensure accurate data and clock
recovery, REFCLK*8 must be within 1000 ppm of
the transmit bit rate. The standards, however, specify that the REFCLK*8 frequency accuracy be within
20-100 ppm.
Transmit Functions
The Transmit section of the SST contains a PLL that
takes a REFCLK input and multiplies it by 8
(REFCLK*8) to produce a PECL (Pseudo ECL or
Positive ECL) differential output clock (TCLK±).
The Transmitter has two operating ranges that are
selectable with the three-level MODE pin, as explained above. The SST 1tansmit frequency multiplier PLL allows low-cost byte-rate clock sources to
be used to time the upstream serial data transmitteJ:
The REFCLK± inputs can be configured in three
different ways. When both REFCLK + and
REFCLK - are connected to a differential lOOK
compatible PECL source, the REFCLK input will
behave as a differential PECL input. When either
the REFCLK - or the REFCLK + input is at a TTL
Law, the other REFCLK input becomes a TTLlevel input allowing it to be connected to a low-cost
TTL crystal oscillator. The REFCLK input structure, therefore, can be used as a differential PECL
input, a single TTL input, or as a dual TTL clock
multiplexing input.
The differential input serial data (RIN ± ) is not only
used by the PLL to recover the clock and data, but
it is also buffered and presented as the PECL differential output pair ROUT±. This output pair can be
used as part of the transmission line interface circuit
for base-line wander compensation, improving system performance by providing reduced input jitter
and increased data eye opening.
Carrier Detect (CD) and Link Fault Indicator
(LFI) Functions
The 1tansmit PECL differential input pair
(TSER±) is buffered by the SST yielding the differential data outputs (TOUT±). These outputs can
be used to directly drive transmission media such as
Printed Circuit Board (PCB) traces, optical fiber
drivers, twisted pair, or coaxial cable.
The Link Fault Indicator (LFI) output is a TTLlevel output that indicates the status of the Receiver.
This output can be used by an external controller for
Loss of Signal (LOS), Loss of Frame (LOF), or Out
of Frame (OaF) indications. LFI is controlled by
the Carrier Detect (CD) input, the internal Transitions Detector, and the PLL Out of Lock (OOL) circuitry.
Receive Functions
The primary function of the Receiver is to generate
recovered clock (RCLK±) and data (RSER±) signals from the incoming differential PECL data
stream (RIN ±). These built-in line receiver inputs,
as well as the TSER± inputs mentioned above, have
a wide common-mode range (2-5V) and the ability
to receive signals with as little as 50 mV differential
voltage. They are compatible with all PECL signals
The CD input may be driven by external circuitry
that is monitoring the incoming data stream. Optical modules have CD outputs that indicate the presence of light on the optical fiber and some copperbased systems use external threshold detection
circuitry to monitor the incoming data stream. The
CD input is a lOOK PECL-compatible signal that
should be held HIGH when the incoming data
3-18
· -.,~
Interfacing with the SST
,CYPRESS================================
stream is valid. When CD is pulled to a PECL LOW,
the LFI output will transition LOW, the Receiver
PLL will align itself with the REFCLK* 8 frequency,
and the recovered data outputs (RSER) will remain
LOW regardless of the signal level on the Receive
data stream inputs (RIN).
(RIN ±). For example, an ATM controller can present ATM cells to the input of the ATM cell processor
and check to see that these same cells are received.
When the LOOP input is de asserted (held HIGH)
the Receive PLL is once again connected to the Receiver serial inputs (RIN ±).
In addition, the SST has a built-in transitions detector that also checks the quality of the incoming data
stream. The absence of data transitions can be
caused by a break in the transmission media, a problem at the transmitter end of the media, or a problem with the transmit or receive media coupling
hardware. The SST will detect a quiet link by counting the number of bit times that have passed without
a data transition. A bit time is defined as the period
of RCLK±. When 512 bit times have passed without a data transition on RIN ±, LFI will transition
LOW. The Receiver will assume that the serial data
stream is invalid and, instead of allowing the
RCLK± frequency to wander in the absence of data,
the PLL will lock to the REFCLK*8 frequency.
This will insure that RCLK± is as close to the correct link operating frequency as the REFCLK accuracy. LFI will be driven HIGH again and the Receiver will recover clock and data from the incoming
data stream when the transition detection circuitry
determines that at least 64 transitions have been detected within 512 bit times.
The LOOP feature can also be used in applications
where clock and data recovery are to be performed
from either of two data streams. In these systems
the LOOP pin is used to select whether the TSER±
or the RIN ± inputs are used by the Receive PLL for
clock and data recovery.
Power-Down Modes
There are several power-down features on the SST.
Any of the differential output drivers can be powered down by either tying both outputs to Vee or by
simply leaving them unconnected where internal
pull-up resistors will force these outputs to V ccThis will save approximately 4 rnA per output pair
in addition to the associated output current. If the
TOUT± or ROUT± outputs are tied to Vee or left
unconnected, the Transmit buffer or Receive buffer
path respectively will be turned off. If the TCLK±
outputs are tied to Vee or left unconnected the entire Transmit PLL will be powered down.
By leaving both the RCLK± and RSER± outputs
unconnected or tied to Vee the entire Receive PLL
is turned off. Even though the Receive PLL may be
turned off, the (LFI will still reflect the state of the
CD input. This feature can be used for aggressive
power management.
The Transition Detector can be turned off by pulling
the CD input to a TTL LOW (~0.8V). When CD
is pulled to a TTL LOW, the LFI will only be driven
LOW if the incoming data stream frequency is not
within 1000 ppm of the REFCLK*8 frequency. LFI
LOW in this case will only indicate that the Receiver
PLLis Out of Lock (OOL). When LFI is left unconnected, an internal pull-down resistor will pull this
input to ground.
Interfacing with the PM5345 (SUNI)
The PM5345 is used in ATM applications for
SONET frame processing, ATM cell processing,
and error monitoring. The PMC-Sierra SUNI device requires Receive serial data aligned with a bitrate clock. These signals need to be supplied
through the RXD± and RXC± inputs respectively.
A 155.52-MHz PECL Transmit clock (TXC±) is required to provide PM5345 transmit side clocking.
For copper-based systems, the TXD ± outputs must
be buffered in order to drive transmission lines with
low impedances. Lastly, a LOS detection is required from the clock and data recovery engine to
Loop Back Testing
The TTL level LOOP pin is used to perform loopback testing. When LOOP is asserted (held LOW)
the Transmitter serial inputs (TSER±) are used by
the Receiver PLL for clock and data recovery. This
allows in-system testing to be performed on the entire device except for the differential Transmit drivers (TOUT±) and the differential Receiver inputs
3-19
II
~
Interfacing with the SST
_;CYPRESS = = = = = = = = = = = = = = = =
side 155.52-MHz clock that is used by the PM5345
TXCI± input by multiplying a 19.44-MHz oscillator
by eight. This function eliminates the need for an
expensive 155.52-MHz oscillator to be used in the
system. The SST buffers the TXD± output signals
from the SUNI device for driving copper-based systems or for improved operation in fiber-based systems.
aid in the determination of the LOS, LOF, and OaF
error conditions reported by the SUNI device. This
signal is brought in through the SUNI GPIN (General Purpose Input). Before the introduction of the
SST, clock and data recovery devices were interfaced to the PMC-SUNI as shown in Figure 3.
Figure 4 shows the SST signal connections with the
PMC-Sierra PM5345 SUNI. The SST, together with
the PM5345, provides a complete Physical layer interface. The Receive section of the SST provides serial SONET/SDH data at 155.52 Mb/s to the receive
section of the PM5345 (RXC± and RXD±). The
Transmit section of the SST provides the transmit
The LFI output is used to drive the GPIN input.
This LFI output will transition LOW when any of
the following occur: the CD (Carrier Detect) input
transitions Law, the frequency of the incoming
data is outside of the lock range of the Receive PLL,
Noise input source to PLL
Additional Component
and Board Space
10H116
Clock and
D'
a a
Recovery
I
Ine
Receiver
river \..__
.------------.,
No Lock to
GPIN
I--'L:::o~c~a~/.!..f,~un:..:.:c~t.:.::io~n'_l~ RXC+
I--------I~ RXC-
D t
Differential
L·
Nine power and grounds
Higher
Power
I--------I~ RXD+
--=======-I------------------------~~ TXD+
RXD-
~--------------------------------~ TXD-
.------------------I~ TXCI+
.--------------~ TXCINo Transmit
No built-in line
frequency multiplicatio
.--.........--,
receiver or driver
No loop-back
testing capability
Expensive Oscillator
Figure 3. 'J)pical SUNI interface without the Use of the SST
.
SST
III
ROUT+ e: ~
ROUT- ~ 0
RIN+
9:::!'
Medial/F]: RIN-
L - - CD
III
Medial/F
I:
TOUT+ ~
TOUT- ~
W
a:
mIt)
RCLK+
RCLKRSER
RSER
;;:
...
TSER+
TSER ,;;;
TCLK+
TCLK-
RXC+
RXC-
;;;;
RXD+
RXD-
....
.
;;;;
+
GPIN
;:
PM5345
SUNI
TXD+
TXDTXCI+
TXCI-
f19.44l
~
Figure 4. SST to PMC-Sierra PM5345 SUNI Connection Diagram
3-20
PM5345
SUNI
g-.,2
Interfacing with the SST
rcYPRESS =============
or there have been no transitions in the incoming
data stream for the last 512 bit times. Additionally,
when the CD input is forced LOW by an output from
a source such as the signal detect of an optical module or an external transition detection circuitry for
copper-based systems, the SST will force the
RSER± outputs Law. This will aid the SUNI device in the determination of the LOS state and minimize the length of time needed to determine an error condition.
bias circuit built into each PECL input) its inputs
and also provides the SST outputs with 50Q terminations to approximately Vee - 2Y. The termination resistors are bypassed with .01-IAF capacitors to provide high-speed switching current. For
PCB trace impedances higher than 50Q, the terminating resistors should be scaled accordingly. For
example, a 100Q transmission line would require a
pull-up resistor of 160Q and a pull-down resistor of
260Q. Terminations for the SST outputs (TCLK,
RCLK, RSER) should be placed as close to the
SUNI as possible.
Figure 5 shows an electrical interface of the SST to
the PMC-SUNI device. Each SST PECL output is
AC coupled into the SUNI inputs with a .01-IAF capacitor, and is loaded with an 80Q pull-up resistor
and a 130Q pull-down resistor. This scheme allows
the SUNI device to self-bias (since the SUNI has a
The TXD± outputs require different termination
resistors values. The ideal biasing voltage for
TXD± is 4.2Y. This bias is achieved by connecting
a 62Q pull up to TAVD and a 330Q pull down to
GND at the end of the termination line connecting
TAVD
SST
VDD
I
Iv
'.l
l=
628Q
r~
.g-
~
330Q62Q
ZO-50Q
330"J·62Q
.01 IAF
TCLK+ I-U
TCLK- KJ
RCLK+ H
ZO=50Q
TXCI+
ll-
TXCI-
:~
RXC+
:~
RXC-
ll-
RXD+
:1-
RXD-
ZO-50Q
ZO-50Q
RSER- H
130~
,...
.01 IAF ~
RVDD
I
~
,...
80Q
~
I-t
TXD-
:l-
RCLK- H
RSER+ H
TSER
RSER
VT1
VT2
TXD+
TSER+
TSER-
PMC·SUNI
r-
~ ~~~~
~
m
FPOS_MLT
GPIN
Figure 5. High Performance SST to PMC SUNI Interface
3-21
desirable than the PM5345 in cases where not all of
the SONET frame processing functions of the
PM5345 are needed. For performance reasons, the
PLL of S/UNI-LITE can be bypassed and the SST
can be used to perform clock and data recovery
functions for the S/UNI-LITE.
TXD± and TSER±. These resistor values are calculated based on Zo = 50Q. For PCB trace impedances higher than 50Q, the terminating resistors
should be scaled accordingly. For example, a lOOQ
transmission line would require a pull-up resistor of
120Q and a pull-down resistor of 636Q. In addition,
the VT2 resistor should also be scaled from 62SQ to
1260Q when using lOOQ trace impedances. In general, RVf2 = 12.564 * Zoo
Figure 6 shows how to interface the SST to the
S/UNI-LITE. When RBYP is tied HIGH, the internal PLL of the S/UNI-LITE is disabled and
RRCLK± is used to sample RXD±. In this configuration, the SST is used to supply the bit-aligned
RRCLK. This is achieved by connecting RCLK± to
RRCLK± and RSER± to RXD ± using four equallength traces. Each of these traces has an SOQ pullup to RVDD and a 130Q pull-down to GND. These
termination resistors are bypassed with .00-!-tF capacitors to satisfy the high-speed switching current
Interfacing with the PM5346
(S/UNI-LITE)
The PM5346 is another PMC-Sierra product used in
ATM systems for clock and data recovery, SONET
frame processing, ATM cell processing, and error
monitoring. Its small package size makes it more
TAVD
I~'
SST
y
S/UNI~LITE
1
:!-
.01 !-tF
~
TBVP
1
\7
RBVP
.01 !-tF
237Q I~
TSER+
67Q192Q
237Q I ~
ZO=50Q
TSER-
i~ TRCLK:~ RRCLK+
ZO=50Q
:~
RCLK- K
RSER+ H
RSER- K
....
RVDD
I
..:t
RRCLK-
:r RXD+
ZO=50Q 130Q80'
.01 !-t F
TXD+
~ TXDi~ TRCLK+
67Q192Q
TCLK+ KJ
ZO=50Q
TCLK- H
RCLK+ H
PMC
VDD
r-----i
....
....
130q
~
80Q:~ RXD-
r-
~ ~ ~ ~ 'l
ALOS+
~ ALOS-
rn
Figure 6. High Performance SST to PMC S/UNI-LITE Interface
3-22
requirements. A .00-!J.F DC-blocking capacitor is
used in series with the transmission line to allow the
S/UNI-LITE to self-bias its inputs (since the S/UNILITE, like the SUNI, also has bias circuits built into
each PECL input). All these passive components
are placed close to the S/UNI -LITE.
Interfacing with the IgT WAC-013.
The Integrated Telecom Technology (IgT)
WAC-013 provides SONET frame processing, ATM
cell processing, and error monitoring. The IgT device requires differential PECL Receive data
(RS_SER_DATA) aligned with a differential PECL
bit-rate clock (RS_SER_CLK). These signals represent the recovered clock and data from a SONET/
SDH STS-3/STM-1 data stream of 155.52 Mb/s or a
SONET STS-1 data stream of 51.84 Mb/s. The
WAC-013 also requires a bit-rate transmit-clock
(TS_SER_CLK) for Transmit Side clocking. The
transmit data (TS_SER_DATA) should also be
buffered for driving low-impedance transmission
lines or copper transmission media. Prior to the
introduction of the SST, clock and data recovery devices were connected to the WAC-013 as shown in
Figure 7.
In the same way, the transmit side PLL of the
S/UNI-LITE can also be disabled. When TBYP is
tied HIGH, the clock multiplication function of the
S/UNI-LITE is disabled and the 155.52-MHz or
51.84-MHz clock received from either RRCLK± or
TRCLK± is used for clocking the transmit portion
ofthe S/UNI-LITE. If the LOOPTbit ofthe Master
Control register of the S/UNI-LITE is 1, RRCLK
will be used and when the LOOPT bit is 0, TRCLK±
will be used. TRCLK± is supplied by TCLK± of the
SST. The terminationlbiasing circuit used for this
TRCLK connection is the same as that used in the
RXD ± and RRCLK± connections described previously. These termination/biasing circuits should
also be placed as close to the S/UNI-LITE as
possible.
Figure 8 shows the SST signal connections with the
The SST, together with the
IgT WAC-013.
WAC-013, provides a complete physical-layer interface. The Receive section of the SST provides serial
SONET/SDH data at 155.52 Mb/s or 51.84 Mb/s
(depending on the state of the SST MODE pin) to
the Receive section of the IgT RS _SER_DATA and
RS_SER_CLK inputs. The Transmit section of the
SST provides the bit-rate clock (TS_SER_CLK)
and Transmit buffering of the TS_SER_DATA outputs. The SST multiples a 19.44-MHz reference
For the TXD± to TSER± connections, a 2370
source resistor in series with a .01-!J.F capacitor
placed closed to the S/UNI-LITE side is used with
a 670 pull-up to TAVD and a 1920 pull-down to
GND placed close to the SST side to provide the
necessary termination and biasing.
Additional Component
and Board Space
10H116
Differential
L· D' /
Ine
river
Receiver
Noise input source to PLL
HI'gher
N'me power and groun ds
Power
,........---------,
Clock and
Data
Recovery
I--------I~ AS SEA CLK+
t-------~ AS=SEA=CLK-
I--------I~ AS SEA OATA+
~____-.!:=~~~~=~======~
RS=SER=OATA-
SEA OATA+
14-------------------1 TS
TS=SEA=OATA.r--------I~ TS SEA CLK+
r--------~ TS=SEA:CLK-
WAC-013
No loop-back
testing capability
Expensive Oscillator
Figure 7. lYPical WAC·OI3 interface without the Use of the SST
3-23
E
SST
III
ROUH s~
ROUT0
RIN+
9::;:
MediallF]: RIN-
III
MediallF~
15
L - - CD
[R
RCLK+
RCLK
RSER
RSER
:s
TSER+
TSER
a:
TCLK+
TCLK-
I
TOUT+
TOUT- ()
"l.U
•
..
...
::
..
.
::
..
RS SER CLK+
RS=SER=CLK-
;::
-:::
RS SER DATA+
RS=SER=DATATS SER DATA+
TS=SER=DATATS SER CLK+
TS=SER=CLK-
WAC-013
(6.48)
1 19
.441
osc
Figure 8. SST to IgT WAC-013 Connection Diagram
clock (6.48-MHz for STS-l applications) by eight to
produce the 155.52-MHz (51.84-MHz) transmit
clock. This frequency multiplication function eliminates the need for an expensive 155.52-MHz crystal
oscillator.
Conclusion
The interface examples shown in this note demonstrate how to connect the SST to the PMC-Sierra
PM5345 SUNI, the PMC-Sierra PM5346 SIUNILITE, and the IgT WAC-013. Together these devices provide a complete physical-layer solution for
ATM applications over SONET/SDH at 155.52
Mb/s and 51.84 Mb/s. The SST greatly simplifies the
physical-layer implementation with its ability to
generate a Loss of Signal indication, its capability to
lock to the local reference clock during error conditions, and its capacity to buffer the transmit data
stream for driving low-impedance transmission
lines. The SST also reduces the cost of physical-layer
implementations by eliminating the need for a
155.52-MHz crystal oscillator with its ability to multiply a byte-rate clock to provide the bit-rate transmit
source. Cypress's expertise in PLL-based clock and
data recovery as well as the added features of the
SST provide designers with the capacity to create
simple, low cost, and robust ATM physical-layer
designs.
Figure 9 shows the electrical interface of the SST to
the WAC-013. The outputs are loaded and terminated with 80Q pull-up resistors and 130Q pulldown resistors at the load. This provides a 50Q termination to Vcc-2y. These resistors are also
bypassed with a .OI-I-IF capacitor to provide highspeed switching current. For PCB trace impedances
higher than 50Q, the terminating resistors should be
scaled accordingly. For example, a lOOQ transmission line would require a pull-up resistor of 160Q
and a pull-down resistor of 260Q.
3-24
Interfacing with the SST
SST
WAC-013
.01 !-IF
\?P--We \?P; Vee
130Q
TSER+
80Q
}-
TS SER DATA+
}-
TS_SER_DATA-
ZO=50Q
TSERTCLK+
H~
TS_SER_CLK+
ZO=50Q
TCLK-
H~
TS_SER_CLK-
RCLK+ H
RS_SER_CLK+
ZO=50Q
RCLK-
,...-{
RSER+
,...-{
RSER-
,...-{
RS_SER_CLKRS SER DATA+
ZO=50Q
130Q
80Q
4~
.01 !-IF ~
Vee
-I
~
~
~
r-
t-
~ ~~~~
Figure 9. High Performance SST to WAC-013 Interface
SST is a trademark of Cypress Semiconductor Corporation.
3-25
RS SER DATA-
E
High-Speed Serial/Fibre Channel/ESCON ™ 4
I
Fibre Channel/ESCON""
Page Number
Device Number
Description
CY7B923/CY7B933
CYlO1E383
CY9266-T/C/F
HOTLink m 1tansmitter/Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
EClIITL/ECL Translator and High-Speed Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4- 28
HOTLink m Evaluation Board ................................................. 4-34
Application Notes
CY7B923/CY7B933
CY7B923/CY7B933
CY7B923/CY7B933
CY7B923/CY7B933
CY7B923/CY7B933
Frequently Asked Questions about HOTLink m ••••••••••••••••••••••••••••••••••• 4-36
Frequently Asked Questions about HOTLink m Evaluation
Boards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-45
Serializing High Speed Parallel Buses to Extend Their Operational
Length ..................................................................... 4-50
Drive ESCON'" With HOTLink m •••••••••••••••••••••••••••••••••••••••••••••• 4-77
Replace Your TAXI -125 and TAXI -175 ....................................... 4-110
CY7B923
CY7B933
HOTLink®
Transmitter/Receiver
Features
Functional Description
•
•
•
•
•
•
•
•
•
•
The CY7B923 HOTLink ~ Transmitter
and CY7B933 HOTLink Receiver are
point-to-point communications building
blocks that transfer data over high-speed
serial links (fiber, coax, and twisted pair) at
160 to 330 Mbits/second. Figure 1 illustrates typical connections to host systems
or controllers.
Eight bits of user data or protocol information are loaded into the HOTLink transmitter and are encoded. Serial data is
shifted out ofthe three differential positive
ECL (PECL) serial ports at the bit rate
(which is 10 times the byte rate).
The HOTLink receiver accepts the serial
bit stream atits differential line receiver inputs and, using a completely integrated
PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. The bit stream is deserialized,
•
•
•
•
•
Fibre Channel compliant
IBM ESCON® compliant
ATM compliant
8B/10B-coded or 10-bit unencoded
160- to 330-Mbps data rate
TTL synchronous I/O
No external PLL components
Triple PECL lOOK serial outputs
Dual PECL lOOK serial inputs
Low power: 350 mW (Tx),
650mW (Rx)
Compatible with fiber optic modules,
coaxial cable, and twisted pair media
Built-In Self-Test
Single +5V supply
28-pin SOIC/PLCC/LCC
0.8!! BiCMOS
CY7B923 Transmitter Logic Block Diagram
decoded, and checked for transmission errors. Recovered bytes are presented in
parallel to the receiving host along with a
byte rate clock.
The 8B/1 OB encoder/decoder can be
disabled in systems that already encode or
scramble the transmitted data. I/O signals
are available to create a seamless interface
with both asynchronous FIFOs (i.e.,
CY7C42X) and clocked FIFOs (i.e.,
CY7C44X). A Built-In Self-Test pattern
generator and checker allows testing ofthe
transmitter, receiver, and the connecting
link as a part of a system diagnostic check.
HOTLink devices are ideal for a variety of
applications where a parallel interface can
be replaced with a high-speed point-topoint serial link. Applications include interconnecting workstations, servers, mass
storage, and video transmission equipment.
CY7B933 Receiver Logic Block Diagram
RF
AlB - - - - ,
INA+
INAINS (INS+)
SI (INS-)
so
REFCLK _ _ _ _- /
MODE~
msmr~
MODE . .
SISTEN . .
CKR
ouu
~a
09
0::
a.
SERIAL LINK
HOST
HOST
Figure 1. HOTLink System Connections
HOTLink is a trademark of Cypress Semiconductor Corporation.
ESCON is a registered trademark of IBM.
4-1
8923-3
I
£JP
CY7B923
CY7B933
-rc-YPRESS
CY7B933 Receiver Pin Configurations
CY7B923 Transmitter Pin Configurations
SOIC
Top View
SOIC
Top View
OutBOutCOutC+
VCCN
BISTEN
GND
MODE
RP
Vcca
SVS{D j)
(Dh) D7
(Dg) DS
(Dj) D5
(Di) D4
OutB+
OutA+
OutAFaro
ENN
ENA
Vcca
Ct
000 000
4 3 2 L'J 282726
BISTEN
GND
MODE
RP
Vcca
SVS{Dj)
(Dh) D7
78923
!:@~w
m<~~ ~u;::;:
25
22
21
9
+-
=Zo
II!:!CIllm «+ «I m=o
1112131415161718 19
------eel
BB
Faro
ENN
ENA
Vcca
Ct4001V
(per MIL-STD-883, Method 301S)
Latch-Up Current ............................ >200 rnA
4-2
Range
Ambient
Temperatnre
O°C to +70°C
Vee
SV ± 10%
Industrial
-40°C to +8SoC
SV ± 10%
Military
-S5°C to + 125°C
Case Temperature
5V ± 10%
Commercial
-.
-'f
CY7B923
CY7B933
~
'CYPRESS================================
Pin Descriptions
CY7B923 HOTLink "fransmitter
Name
Description
I/O
TTL In
Parallel Data Input. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW (or
DO-7
on the next rising CKW with ENN LOW). If ENA and ENN are HIGH, a Null character (KZ8.5) is sent.
(Db - h)
When MODE is HIGH, Do, I, ... 7 become Db, c, ... h respectively.
TTL In
Special Character/Data Select. A HIGH on SC/Dwhen CKW rises causes the transmitter to encode the
SC/D
pattern on DO-7 as a control code (Special Character1.while a LOW causes the dat~to be coded using the
(Da)
8BI10B data alphabet. When MODE is HIGH, SC/D (Da) acts as Da input. SC/D has the same timing
as DO-7'
TTL In
Send Violation Symbol. If SVS is HIGH when CKW rises, a Violation symbol is e.!!.coded and sent while
SVS
the data on the parallel inputs is ignored. If SVS is LOW, the state ofDo-7 and SC/D determines the code
(Dj)
sent. In normal or test mode, this pin overrides the BIST generator and forces the transmission of a Violation code. When MODE is HIGH (placing the transmitter in un encoded mode), SVS (Dj) acts as the Dj
input. SVS has the same timing as DO-7'
ENA
TTL In
Enable Parallel Data. IfENA is LOW on the rising edge of CKW, the data is loaded, encoded, and sent.
IfENA and ENN are HIGH, the data inputs are ignored and the Transmitter will insert a Null character
(K28.5) to fill the space between user data. ENA may be held HIGH/LOW continuously or it may be
pulsed with each data byte to be sent. If ENA is being used for data control, ENN will normally be
strapped HIGH, but can be used for BIST function control.
ENN
TTL In
Enable Next Parallel Data. IfENN is LOW, the data appearing on DO-7 at the next rising edge of CKW
is loaded, encoded, and sent. IfENA and ENN are HIGH, the data appearing on DO-7 at the next rising
edge of CKW will be ignored and the Transmitterwill insert a Null character to fill the space between user
data. ENN may be held HIGH/LOW continuously or it may be pulsed with each data byte sent. IfENN
is being used for data control, ENA will normally be strapped HIGH, but can be used for BIST function
control.
CKW
TTL In
Clock Write. CKW is both the clock frequency reference for the multiplying PLL that generates the highspeed transmit clock, and the byte rate write signal that synchronizes the parallel data input. CKW must
be connected to a crystal controlled time base that runs within the specified frequency range ofthe nansmitter and Receiver.
FOTO
TTL In
OUTA±
OUTB±
OUTC±
PECL
Out
MODE
3-Level
In
BISTEN
TTL In
Fiber Optic Transmitter Off. FOTO determines the function of two of the three PECL transmitter output
pairs. If FOTO is LOW, the data encoded by the Transmitter will appear at the outputs continuously. If
FOTO is HIGH, OUTA± and OUTB± are forced to their "logic zero" state (OUT + = LOW and OUT= HIGH), causing a fiber optic transmit module to extinguish its light output. OUTC is unaffected by the
level on FOTO, and can be used as a loop-back signal source for board-level diagnostic testing.
Differential Serial Data Outputs. These PECL lOOK outputs (+5V referenced) are capable of driving
terminated transmission lines or commercial fiber optic transmitter modules. Unused pairs of outputs
can be wired to Vcc to reduce power if the output is not required. OUTA± and OUTB± are controlled
by the level on FOTO, and will remain at their "logical zero" states when FOTO is asserted. OUTC± is
unaffected by the level on FOTO. (OUTA + and OUTB+ are used as a differential test clock input while
in Test mode, i.e., MODE=UNCONNECTED or forced to VcdZ.)
Encoder Mode Select. The level on MODE determines the encoding method to be used. When wired to
GND, MODE selects 8B/lOB encoding. When wired to Vcc, data inputs bypass the encoder and the bit
pattern on Da _j goes directly to the shifter. When left floating (internal resistors hold the input at V cdZ)
the internal bit-clock generator is disabled and OUTA +/OUTB+ become the differential bit clock to be
used for factory test. In typical applications MODE is wired to VCC or GND.
Built-In Self-Thst Enable. When BISTEN is LOW and ENA and ENN are HIGH, the transmitter sends
an alternating 1-0 pattern (Dl0.Z or DZ1.5). When either ENA or ENN is set LOW and BISTEN is
LOW, the transmitter begins a repeating test sequence that allows the nansmitter and Receiver to work
together to test the function of the entire link. In normal use this input is held HIGH or wired to Vcc.
The BIST generator is a free-running pattern generator that need not be initialized, but if required, the
BIST sequence can be initialized by momentarily asserting SVS while BISTEN is LOW. BISTEN has the
same timing as DO-7'
RP
TTL Out
VCCN
VCCQ
GND
Read Pulse. RP is a 60% LOW duty-cycle byte-rate pulse train suitable for the read pulse in CY7C4ZX
FIFOs. The frequency on RP is the same as CKW when enabled by ENA, and duty cycle is independent
of the CKW duty cycle. Pulse widths are set by logic internal to the transmitter. In BIST mode, RPwill
remain HIGH for all but the last byte of a test loop. RP will pulse LOW one byte time per BIST loop.
Power for output drivers.
Power for internal circuitry.
Ground.
4-3
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CY7B923
CY7B933
~
?cYPRESS
CY7B933 HOTLink Receiver
Name
Description
I/O
TTL Out
QO-7 Parallel Data Output. QO-7 contain the most recently received data. These outputs change synQO-7
chronously with CKR. When MODE is HIGH, Qo, 1, ... 7 become Ob, c, ...h respectively.
(Qb - h)
son (Q a)
TTL Out
RVS (Qj)
TTL Out
RDY
TTL Out
CKR
TTL Out
Clock Read. This byte r~e clock output is phase and frequency aligned to the incoming serial data
stream. RDY, QO-7, SC/D, and RVS all switch synchronously with the rising edge of this output.
AlB
PECLin
INA±
Diff In
Serial DataInput Select. This PECL lOOK ( + 5V referenced) input selects INA or INB as the active data
inp!!t. If AlB is HIGH, INA is connected to the shifter and signals connected to INA will be decoded. If
NB is LOW INB is selected.
Serial Data Input A. The differential signal at the receiver end of the communication link may be connected to the differential input pairs INA± or INB ±. Either the INA pair or the INB pair can be used as
the main data input andihe other can be used as a loopback channel or as an alternative data input selected by the state of AlB.
INB
(INB+)
PECLin
(DiffIn)
Serial Data Input B. This pin is either a single-ended PECL data receiver (INB) or half ofthe INB ofthe
differential pair. If SO is wired to V cc, then INB± can be used as differential line receiver interchangeably with INA±. If SO is normally connected and loaded, INB becomes a single-ended PECL lOOK
( + 5V referenced) serial data input. INB is used as the test clock while in Test mode.
SI
(INB-)
PECLin
(Diffin)
Status Input. This pin is either a single-ended PECL status monitor input (SI) or half of the INB of the
differential pair. If SO is wired to V cc, then INB± can be used as differential line receiver interchangeably with INA±. If SO is normally connected and loaded, SI becomes a single-ended PECL lOOK ( + 5V
referenced) status monitor input, which is translated into a TTL-level signal at the SO pin.
SO
TTL Out
RF
TTL In
Status Out. SO is the TTL-translated output of SI. It is typically used to translate the Carrier Detect
output from a fiber-optic receiver connected to SI. When this pin is normally connected and loaded (without any external pull-up resistor), SO will assume the same logical level as SI and INB will become a
single-ended PECL serial data input. If the status monitor translation is not desired, then SO may be
wired to V cc and the INB ± pair may be used as a differential serial data input.
Reframe Enable. RF controls the Framer logic in the Receiver. When RF is held HIGH, each SYNC
(K28.5) symbol detected in the shifter will frame the data that follows. If is HIGH for 2,048 consecutive
bytes, the internal framer switches to double-byte mode. When RF is held LOW, the reframing logic is
disabled. The incoming data stream is then continuously deserialized and decoded using byte boundaries
set by the internal byte counter. Bit errors in the data stream will not cause alias SYNC characters to
reframe the data erroneously,
REFCLK
TTL In
Reference Clock. REFCLK is the clock frequency reference for the clock/data synchronizing PLL.
REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream.
REFCLKmust be connected to a crystal-controlled time base that runs within the frequency limits ofthe
Tx/Rxpair, and the frequency must be the same as the transmitter CKW frequency (within CKW ±O.l %)
MODE
3-Levelln
BISTEN
TTL In
Decoder Mode Select. The level on the MODE pin determines the decoding method to be used. When
wired to GND, MODE selects 8B/lOB decoding. When wired to V cc, registered shifter contents bypass
the decoder and are sent to Qa-j directly. When left floating (internal resistors hold the MODE pin at
Vcd2) the internal bit clock generator is disabled and INB becomes the bit rate test clock to be used for
factory test. In typical applications, MODE is wired to V cc or GND.
Built-In Self-Thst Enable. When BISTEN is LOW the Receiver awaits a DO.O (sent once per BIST loop)
character and begins a continuous test sequence that tests the functionality of the Transmitter, the Receiver, and the link connecting them. In BIST mode the status of the test can be monitored with RDY and
RVS outputs. In normal use BISTEN is held HIGH or wired to V cc. BISTEN has the same timing as
Special CharacterlData Select. SC/D indicates the context of received data. HIGH indicates a Control
(Special Character) code, L...9W indicates a Data charact"'-!:' When MODE is HIGH (placing the receiver
in Unencoded mode), SC/D acts as the Q a output. SC/D has the same timing as QO-7'
Received Violation Symbol. A HIGH on RVS indicates that a code rule violation has been detected in the
received data stream. A LOW shows that no error has been detected. In BIST mode, a LOW on RVS
indicates correct operation ofthe Transmitter, Receiver, and link on a byte-by-byte basis. When MODE
is HIGH (placing the receiver in Unedcoded mode), RVS acts as the Qj output. RVS has the same timing
as QO-7'
Data Output Ready. A LOW pulse on RDY indicates that new data has been received and is ready to be
delivered. A missing pulse on RDY shows that the received data is the Null character (normally inserted
by the transmitter as a pad between data inputs). In BISTmode RDY will remain LOW for all but the last
byte of a test loop and will pulse HIGH one byte time per BIST loop.
QO-7·
VCCN
VCCQ
GND
Power for output drivers.
Power for internal circuitry.
Ground.
4-4
CY7B923
CY7B933
CY7B923 HOTLink Transmitter Block Diagram
Description
Input Register
The Input register holds the data to be processed by the HOTLink
transmitter and allows the input timing to be made consistent with
standard FIFOs. The Input register is clocked by CKW and loaded
with information on the DO-7, SCll), and SVS pins. Two enable
inputs (ENA and ENN) allow the user to choose when data is
loaded in the register. Asserting ENA (Enable, active LOW)
causes the inputs to be loaded in the register on the rising edge of
CKW. IfENN (Enable Next, active LOW) is asserted when CKW
rises, the data present on the inputs on the next rising edge ofCKW
will be loaded into the Input register. If neither ENAnor ENN are
asserted LOW on the rising edge of CKW, then a SYNC (K28.5)
character is sent. These two inputs allow proper timing and function for compatibility with either asynchronous FIFOs or clocked
FIFOs without external logic, as shown in Figure 5.
In BIST mode, the Input register becomes the signature pattern
generator by logically converting the parallel Input register into a
Linear Feedback Shift Register (LFSR). When enabled, this
LFSR will generate a 511-byte sequence that includes all Data and
Special Character codes, including the explicit violation symbols.
This pattern provides a predictable but pseudo-random sequence
that can be matched to an identical LFSR in the Receiver.
Encoder
The Encoder transforms the input data held by the Input register
into a form more suitable for transmission on a serial interface link.
The code used is specified by ANSI X3.230 (Fibre Channel) and
the IBM ESCON channel (code tables are at the end of this datasheet). The eight DO-7 data inputs are converted to either a Data
symbol or a Special Character, depending upon the state of the
scm input. If scm is HIGH, the data inputs represent a control
code and are encoded using the Special Character code table. If
scm is LOW, the data inputs are converted using the Data code
table. If a byte time passes with the inputs disabled, the Encoder
will output a Special Character Comma K28.5 (or SYNC) that will
maintain link synchronization. SVS input forces the transmission
of a specified Violation symbol to allow the user to check error
handling system logic in the controller or for proprietary applications.
The 8B/lOB coding function of the Encoder can be bypassed for
systems that include an external coder or scrambler function as
part of the controller. This bypass is controlled by setting the
MODE select pin HIGH. When in bypass mode, D a_· (note that
bit order is specified in the Fibre Channel 8B/lOB code) become
the ten inputs to the Shifter, with Da being the first bit to be shifted
out.
Shifter
The Shifter accepts parallel data from the Encoder once each byte
time and shifts it to the serial interface output buffers using a PLL
multiplied bit clock that runs at ten (10) times the byte clock rate.
Timing for the parallel transfer is controlled by the counter included in the Clock Generator and is not affected bysignallevels or
timing at the input pins.
OutA, OutB, OutC
The serial interface PECLoutput buffers (ECLlOOKreferenced to
+ 5v) are the drivers for the serial media. They are all connected to
the Shifter and contain the same serial data. Tho of the output
pairs (OUTA± and OUTB±) are controllable by the FOTO input
and can be disabled by the system controller to force a logical zero
(i.e., "light off") atthe outputs. The third output pair (OUTC±) is
not affected by FOTO and will supply a continuous data stream
suitable for loop-back testing of the subsystem.
OUTA± and OUTB ± will respond to FOTO input changes within
a few bit times. However, since FOTO is not synchronized with the
transmitter data stream, the outputs will be forced off or turned on
at arbitrary points in a transmitted byte. This function is intended
to augment an external laser safety controller and as an aid for Receiver PLL testing.
In wire-based systems, control of the outputs may not be required,
and FOTO can be strapped LOW. The three outputs are intended
to add system and architectural flexibility by offering identical serial bit streams with separate interfaces for redundant connections
or for multiple destinations. Unneeded outputs can be wired to
Vee to disable and power down the unused output circuitry.
Clock Generator
The clock generator is an embedded phase-locked loop (PLL) that
takes a byte-rate reference clock (CKW) and multiplies it by ten
(10) to create a bit rate clock for driving the serial shifter. The byte
rate reference comes from CKW, the rising edge of which clocks
data into the Input register. This clock must be a crystal referenced
pulse stream that has a frequency between the minimum and maximum specified for the HOTLink 1tansmitter/Receiver pair. Signals controlled by this block form the bit clock and the timing signals that control internal data transfers between the Input register
and the Shifter.
The read pulse (RP) is derived from the feedback counter used in
the PLL multiplier. It is a byte-rate pulse stream with the proper
phase and pulse widths to allow transfer of data from an asynchronous FIFO. Pulse width is independent of CKW duty cycle, since
proper phase and duty cycle is maintained by the PLL. The RP
pulse stream will insure correct data transfers between asynchronous FIFOs and the transmitter input latch with no external logic.
Test Logic
Test logic includes the initialization and control for the Built-In
Self-Test (BIST) generator, the multiplexer forTest mode clock distribution, and control logic to properly select the data encoding.
Test logic is discussed in more detail in the CY7B923 HOTLink
1tansmitter Operating Mode Description.
CY7B933 HOTLink Receiver Block Diagram
Description
Serial Data Iuputs
Tho pairs of differential line receivers are the inputs for the serial
data stream. INA± or INB± can be selected with the NB input.
INA± is selected with NB HIGH and INB± is selected with NB
LOW. The threshold of AlB is compatible with the ECL lOOK signals from PECL fiber optic interface modules. TTL logic elements
can be used to select the A or B inE?ts by adding a resistor pull-up
to the TTL driver connected to AlB. The differential threshold of
INA± and INB± will accommodate wire interconnect with filtering losses or transmission line attenuation greater than 20 db
(VDIF ~ 50mv) or can be directly connected to fiber optic interface
modules (any ECL logic family, not limited to ECL lOOK). The
common mode tolerance will accommodate a wide range of signal
termination voltages. The highest HIGH input that can be tolerated is VIN = Vee, and the lowest LOW input that can be interpreted correctly is VIN = GND+2.0V.
PECL-TTL 'franslator
The function of the INB(INB+) input and the SI(INB-) input is
defined by the connections on the SO output pin. If the PECU
TTL translator function is not required, the SO output is wired to
4-5
I
CY7B923
CY7B933
Vee. A sensor circuit will detect this connection and cause the inputs to become INB± (a differential line-receiver serial-data input). If the PECIJrfL translator function is required, the SO output is connected to its normal TIL load (typically one or more TIL
inputs, but no pull-up resistor) and the INB+ input becomes INB
(single-ended ECL lOOK, serial data input) and the INB- input
becomes SI (single-ended, ECL lOOK status input).
This positive-referenced PECL-to-TIL translator is provided to
eliminate external logic between an PECL fiber-optic interface
module "carrier detect" output and the TIL input in the control
logic. The input threshold is compatible with ECL lOOK levels
(+5V referenced). It can also be used as part ofthe link status indication logic for wire connected systems.
Clock Synchronization
frame. Double-byte framing greatly reduces the possibility of erroneously reframing to an aliased K28.5 character.
Shifter
The Clock Synchronization function is performed by an embedded
phase-locked loop (PLL) that tracks the frequency ofthe incoming
bit stream and aligns the phase of its internal bit rate clock to the
serial data transitions. This block contains the logic to transfer the
data from the Shifter to the Decode register once every byte. The
counter that controls this transferis initialized by the Framer logic.
CKR is a buffered output derived from the bit counter used to control the Decode register and the output register transfers.
Clock output logic is designed so that when reframing causes the
counter sequence to be interrupted, the period and pulse width of
CKR will never be less than normal. Reframing may stretch the period of CKR by up to 90%, and either CKR Pulse Width HIGH or
Pulse Width LOW may be stretched, depending on when reframe
occurs.
The REFCLK input provides a byte-rate reference frequency to
improve PLLacquisition time and limit unlocked frequencyexcursions of the CKR when no data is present at the serial inputs. The
frequency of REFCLK is required to be within ±O.l % of the frequency of the clock that drives the transmitter CKW pin.
Framer
Parallel data is transformed from ANSI-specified X3.230 BB/lOB
codes back to "raw data" in the Decoder. This block uses the standard decoder patterns shown in the Valid Data Characters and Valid Special Character Codes and Sequences sections of this datasheet. Data patterns are signaled by a LOW on the SC;D output
and Special Character patterns are signaled by a HIGH on the
SC/l) output. Unused patterns or disparity errors are signaled as
errors by a HIGH on the RVS output and by specific Special Character codes.
Output Register
Framer logic checks the incoming bit stream for the pattern that
defines the byte boundaries. This combinatorial logic filter looks
for the X3.230 symbol defined as a Special Character Comma
(K28.5). When it is found, the free-running bit counter in the
Clock Synchronization block is synchronously reset to its initial
state, thus framing the data correctly on the correct byte boundaries.
Random errors that occur in the serial data can corrupt some data
patterns into a bit pattern identical to a K28.5, and thus cause an
erroneous data-framing error. The RF input prevents this by inhibiting reframing during times when normal message data is present. When RF is held LOW, the HOTLink receiver will deserialize
the incoming data without trying to reframe the data to incoming
patterns. When RF rises, RDY will be inhibited until a K28.5 has
been detected, after which RDY will resume its normal function.
While RFis HIGH, it is possible that an error could cause misframing, after which all data will be corrupted. Likewise, a K28.7 followed by Dl1.x, D20.x, or an SVS (CO.7) followed by Dl1.x will
create alias K28.5 characters and cause erroneous framing. These
sequences must be avoided while RF is HIGH.
If RF remains HIGH for greater than 2048 bytes, the framer converts to double-byte framing, requiring two K28.5 characters
aligned on the same byte boundary within 5 bytes in order to re-
The Shifter accepts serial inputs from the Serial Data inputs one bit
at a time, as clocked by the Clock Synchronization logic. Data is
transferred to the Framer on each bit, and to the Decode register
once per byte.
Decode Register
The Decode register accepts data from the Shifter once per byte as
determined by the logic in the Clock Synchronization block. It is
presented to the Decoder and held until it is transferred to the output latch.
Decoder
The Output register holds the recovered data (00-7, SC;D, and
RVS) and aligns it with the recovered byte clock (CKR). This synchronization insures proper timing to match a FIFO interface or
other logic that requires glitch free and specified output behavior.
Outputs change synchronously with the rising edge of CKR.
In BIST mode, this register becomes the signature pattern generator and checker by logically converting itself into a Linear Feedback Shift Register (LFSR) pattern generator. When enabled, this
LFSR will generate a 51l-byte sequence that includes all Data and
Special Character codes, including the explicit violation symbols.
This pattern provides a predictable but pseudo-random sequence
that can be matched to an identical LFSR in the nansmitter.
When synchronized, it checks each byte in the Decoder with each
byte generated by the LFSR and shows errors at RVS. Patterns
generated by the LFSR are compared after being buffered to the
output pins and then fed back to the comparators, allowing test of
the entire receive function.
In BIST mode, the LFSR is initialized by the first occurrence of the
transmitter BIST loop start code DO.O (DO.O is sent only once per
BIST loop). Once the BIST loop has been started, RVS will be
HIGH for pattern mismatches between the received sequence and
theinternallygeneratedsequence. Coderuleviolationsorrunning
disparity errors that occur as part of the BIST loop will not cause an
error indication. RDY will pulse HIGH once per BIST loop and
can be used to check test pattern progress. The receiver BIST generator can be reinitialized by leaving and re-entering BIST mode.
Test Logic
Thst logic includes the initialization and control for the Built-In
Self-Test (BIST) generator, the multiplexerforThst mode clock distribution, and controllogicfor the decoder. Thst logic is discussed
in more detail in the CY7B933 HOTLink Receiver Operating
Mode Description.
4-6
CY7B923
CY7B933
=r:- -'f~
; CYPRESS
CY7B923/CY7B933 Electrical Characteristics Over the Operating Rangel!]
Parameter
Description
Test Conditions
TTL OUTs, CY7B923: RP; CY7B933: QO-7, SC/D, RVS, RDY, CKR, SO
Min.
Max.
Unit
Output HIGH Voltage
2.4
IOH - - 2mA
VOHT
Output LOW Voltage
0.45
IOL = 4 rnA
VOLT
Output Short Circuit Current
VOUT =OVI2J
-15
-90
lOST
TTL INs, CY7B923: DO-7, SC/D, SVS, ENA, ENN, CKw, FOTO, BISTEN; CY7B933: RF, REFCLK, BISTEN
V
V
rnA
VIHT
Com'l& Mil
Input HIGH Voltage
Mil (eKW and FOTO, only) .
2.0
2.2
- 0.5
-10
Input LOW Voltage
VILT
Input HIGH Current
IIHT
VIN = Vee
Input LOW Current
VIN = O.OV
lILT
Transmitter PECL-Compatible Output Pius: OUTA+, OUTA-, OUTB+, OUTB-, OUTC+, OUTCOutput HIGH Voltage
Load = 50Q to Com'l
Vee-l.03
VOHE
(Vee referenced)
Vee - 2V
Mil
Vee-l.05
Load = 50 Q to Com'l
Output LOW Voltage
Vee-l.86
VOLE
(Vee referenced)
Vee - 2V
Mil
Vee- 1.96
Output Differential Voltage
Load - 50 ohms to Vee - 2V
0.6
VODIF
1(OUT+) - (OUT-)1
Receiver PECL-Compatible Input Pins: AlB, SI, INB
Com'l
Input HIGH Voltage
Vee-1.165
VIHE
Mil
Vee-1.l4
Com'l
2.0
Input LOW Voltage
VILE
Mil
2.0
Input HIGH Current
VIN = VIHE Max.
IIHE l3J
Input LOW Current
+0.5
VIN = VILE Min.
IILE l3J
Differential Line Receiver Input Pins: INA+, INA , INB+, INB
Input Differential Voltage
50
VDIFF
I(IN+) - (IN-)I
Highest Input HIGH Voltage
VIHH
Lowest Input LOW Voltage
2.0
VILL
Input HIGH Current
VIN = VIHH Max.
IIHH
IILLl41
Input LOW Current
-200
VIN = VILL Min.
Miscellaneous
'!Yp.
Transmitter Power Supply
65
Com'l
IeeTI'1
Freq. = Max.
Current
Mil
75
Com'l
ICCR[6]
120
Receiver Power Supply Current
Freq. = Max.
Mil
135
Notes:
1. See the last page of this specification for Group A subgroup testing
information.
2. Tested one output at a time, output shorted for less than one second,
Jess than 10% duty cycle.
3. Applies to AlB only.
4. Input currents are always positive at all voltages above V cd2.
5. Maximum lCCT is measured with V cc = Max., one PECL output pair
loaded with 50 ohms to V cc - 2.0V, and other PECL outputs tied to
VCC. Typical ICCTismeasured with Vcc = 5.0V, TA = 25"C, one out~air loaded with 50 ohms to V cc - 2.0V, others tied to V CC, BlSTEN = LOW. lCCT includes current into V CCQ (pin 9 and pin 22)
only. Current into V CCN is determined by PECL load currents, typically 30 rnA with 50 ohms to V CC - 2.0V. Each additional enabled
PECL pair adds 5 rnA to lCCT and an additional load current to V CCN
as described. When calculating the contribution of PECL load currents to chip power dissipation, the output load current should be
multiplied by 1V instead of V CC.
6.
4-7
Vee
Vee
0.8
+10
- 500
V
V
V
[.lA
[.lA
Vee- 0.83
Vee- 0.83
Vee-l.62
Vee-1.62
V
V
V
V
V
Vee
Vee
Vee- 1.475
Vec-1.50
+500
V
V
V
V
[.lA
[.lA
mV
V
V
[.lA
[.lA
Vee
750
Max.
85
95
155
160
rnA
rnA
rnA
rnA
Maximum lCCR is measured with V CC = Max., RF = Law, and outputs unloaded. TY~R is measured with VCC = 5.0V, TA =
25 C, RF = Law, BISTEN = Law, and outputs unloaded. lCCR includes current into V CCQ (pins 21 and 24). Current into V CCN (pin 9)
is determined by the total TTL output buffer quiescent current plus
the sum of all the load currents for each output pin. The total buffer
quiescent current is lOrnA max., and max. TIL load current for each
output pin can be calculated as follows:
0
/CCN _
ITLPin -
r
O.95
+ (VCCN
RL
-5)*0.3
+ CL
*
(VCCN
), Fpin
2
+ LS
1,
1.1
Where RL = equivalent load resistance, CL :::::::capacitive load, and
Fpin =frequency in MHz of data on pin. A derating factor of 1.1 has
been included to account for worst process corner and temperature
condition.
I
CY7B923
CY7B933
Capacitance[7]
Parameter
Description
Test Conditions
Input Capacitance
TA
= 25°C, fo = 1 MHz, Vcc = 5.0V
AC Test Loads and Waveforms
OUTPUT
-ii
Rl
v
Rl = 910g
R2 = SlOg
CL<30pF
(Includes fixture and
probe capacitance)
CLI
RL = 50g
< 5 pF
(Includes fixture and
probe capacitance)
CL
R2
-
-
(a) TTL AC Test Load[8]
(b) PECL AC Test Load[8]
6923-8
3.0V
3.0V - - - ~~-----\J
2.0V
GND
51 ns
(c) TTL Input Test Waveform
8923-10
8923-9
(d) PECL Input Test Waveform
Transmitter Switching Characteristics Over the Operating Rangd 1]
7B923
Parameter
Description
Max.
Unit
tCKW
Write Clock Cycle
30.3
62.5
ns
tB
Bit Timd 9]
3.03
6.25
ns
tCPwH
CKW Pulse Width HIGH
6.5
ns
tCPWL
CKW Pulse Width LOW
6.5
ns
tSD
Data Set-Up Timd lO ]
5
ns
tHD
Data Hold Time(10]
0
ns
tSENP
Enable Set-Up Time (to insure correct RP)[ll]
tHENP
tpDR
Enable Hold Time (to insure correct RP)[ll]
Read Pulse Rise Alignmentl l2]
tPPWH
Read Pulse HIGH[12]
4tB-3
tpDF
Read Pulse Fall Alignmentl l2]
6tB-3
tRISE
PECL Output Rise Time 20-80% (PECL Thst Load)[7]
1.2
ns
tFALL
PECL Output Fall Time 80- 20% (PECL Test Load)p]
1.2
ns
tOJ
Deterministic Jitter (peak-peak)[7, 13]
35
ps
tRJ
Random Jitter (peak-peak)p, 14]
175
ps
Random Jitter (0)[7,14]
20
ps
Notes:
7. Thsted initially and after any design or process changes that may affect
these parameters, but not 100% tested.
8. Cypress uses constant current (ATE) load configurations and forcing
functions. This figure is for reference only.
9. Transmitter tB is calculated as tCKW/lO. The byte rate is one tenth of
the bit rate.
10. Data includes DO-7, SC/D, SVS, ENA, ENN, and BISTEN. tSD and
tHD minimum timing assures correct data load on rising edge of CKW,
but not RP function or timing.
Min.
6tB
+8
ns
ns
0
-4
2
ns
ns
ns
11. tSENP and tHENP timing insures correct RP function and correct data
load on the rising edge of CKW.
12. Loading on RP is the standard TTL test load shown in part (a) of AC
Thst Loads and Waveforms except CL = 15 pF.
13. While sending continuous K28.5s, Rp unloaded, outputs loaded to
50g to V CC-2.0V, over the operating range.
14. While sending continuous K28.7s, after 100,000 samples measured at
the cross point of differential outputs, time referenced to CKW input,
over the operating range.
4-8
CY7B923
CY7B933
Receiver Switching Characteristics Over the Operating Rangd 1]
7B933
Parameter
Description
Min.
Max.
-1
+1
Unit
%
3.03
6.25
ns
tCKR
Read Clock Period (No Serial Data Input), REFCLK as Referencd l5 ]
tB
Bit Timd l6]
tCPRH
Read Clock Pulse HIGH
5tB-3
ns
tCPRL
Read Clock Pulse LOW
5tB-3
ns
tRH
RDY Hold Time
tB-3
ns
tpRF
RDY Pulse Fall to CKR Rise
5tB-3
ns
tpRH
RDY Pulse Width HIGH
4tB-3
tA
2tB-2
tROH
Data Access Timd 17, 18]
Data Hold Timet l7 , 18]
2tB-3
ns
2tB+4
tH
Data Hold Time from CKR Rise [17, 18]
tCKX
REFCLK Clock Period Referenced to CKW of Transmitter[19]
tCPXH
REFCLK Clock Pulse HIGH
6.5
tCPXL
REFCLK Clock Pulse LOW
6.5
tDS
tSA
Propagation Delay SI to SO (note PECL and TTL thresholds)[20]
Static Alignment[7, 21]
tEFW
Error Free Window[7, 22]
-0.1
ns
ns
tB-3
ns
+0.1
%
ns
ns
20
ns
100
ps
0.9tB
Notes:
IS. The period of tCKR will match the period of the transmitter CKW
when the receiver is receiving serial data. When data is interrupted,
CKR may drift to one of the range limits above.
16. Receiver tB is calculated as tCKR/I0 if no data is being received, or
tCKW/IO if data is being received. See note 9.
17. Data includes QO-7' SC/D, and RVS.
18. !k.!ll.OH, and tH..3'ecifications are only valid if all outputs (CKR,
RDY, QO-7, SC/D, and RVS) are loaded with similar DC and AC
loads.
19. REFCLKhas no phase or frequency relationship with CKR and only
acts as a centering reference to reduce clock synchronization time.
REFCLKmust be within 0.1 % of the transmitter CKW frequency, necessitating a ±SOO-PPM crystal.
20. The PECL switching threshold is the midpoint between the PECLVOH, and VOL specification (approximately V CC - 1.3SV). The TTL
switching threshold is 1.SV
21. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in 3,000 nominal transitions until a byte error occurs.
22. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error.
EFW is measured over the operating range, input jitter < SO% Dj.
4-9
I
CY7B923
~YPRESS============================CY==7=B=93=;3
Switching Waveforms for the CY7B923 HOTLink Transmitter
CKW
0 0-0 7 ,
scm,
svs,
BTSTEN
CKW
Do-Db
scm,
svs,
BTSTEN
6923-12
4-10
-..
&
~
CY7B923
CY7B933
~~ CYPRESS = = = = = = = = = = = = = =
Switching Waveforms for the CY7B933 HOTLink Receiver
....------ tCKR -------./
CKR
------t--tr-----~----tPRF ---~
00 - 07,
SC/D, RVS,
J3ISTEf'j
6923-13
I
~------~~-------~
ICPXL - - - - ' - - - - ICPXH
REFCLK[ 191
6923·14
SI
Vee
-lOS
so
NOTE 20
1.5V
8923·15
Static Alignment
Error-Free Window
INA±
INB±
INA±,
INB±
SAMPLE WINDOW
8923-16
4-11
BIT CENTER
BIT CENTER
6923-17
Q_~'
CY7B923
CY7B933
I~
CYPRESS = = = = = = = = = = = = = = =
DATA LATCHED IN
~I+--
TRANSMITTER LATENCY
= 21 IS -10 ns
---~
DO-7,
SC/D,
SVS
8923·18
Figure 2. CY7B923 'Iransmitter Data Pipeline
HOTLink CY7B923 Transmitter and CY7B933
Receiver Operation
The CY7B923 Transmitter operating with the CY7B933 Receiver
form a general purpose data communications subsystem capable of
transporting user data at up to 33Mbytes per second over several
types of serial interface media. Figure 2 illustrates the flow of data
through the HOTLink CY7B923 transmitter pipeline. Data is
latched into the transmitter on the rising edge of CKW when
enabled by ENA or ENN. RP is asserted LOW with a 60%
LOW/40%HIGHdutycycIewhenENAisLOW. RPmaybeused
as a read strobe for accessing data stored in a FIFO. The parallel
data flows through the encoder and is then shifted out of the
OUTx± PECL drivers. The bit-rate clock is generated internally
from a multiply-by-ten PLL clock generator. The latency through
the transmitter is approximately 211s - 10 ns over the operating
range. A more complete description is found in the section
CY7B923 HOTLink Transmitter Operating Mode Description.
Figure 3 illustrates the data flow through the HOTLink CY7B933
receiver pipeline. Serial data is sampled by the receiver on the
INx± inputs. The receiver PLLlocksonto the serial bit stream and
generates an internal bit rate clock. The bit stream is deserialized,
decoded and then presented at the parallel output pins. A byte rate
clock (bit clock -+- 10) sycnchronous with the parallel data is
presented at the CKR pin. The RDY pin will be asserted to LOW
to indicate that data or control characters are present on the outputs. RDY will not be asserted LOW in a field ofK28.5s except for
any single K28.5 or the last one in a continuous series of K28.5's.
The latency through the receiver is approximately 24ts + 10 ns
over the operating range. A more complete description of the receiver is in the section CY7B933 HOTLink Receiver Operating
Mode Description.
The HOTLink Receiver has a built-in byte framer that
synchronizes the ReceiverpipeIinewithincommingSYNC(K28.5)
characters. Figure 4 illustrates the HOTLink CY7B933 Receiver
framing operation. The Framer is enabled when the RF pin is
asserted HIGH. RF is latched into the receiver on the falling edge
of CKR. The framer looks for K28.5 characters embedded in the
serial data stream. When a K28.5 is found, the framer sets the
parallel byte boundary for subsequent data to the the K28.5
boundary. While the framer is enabled, the RDY pin indicates the
status of the framing operation.
SERIAL DATA IN
INX
CKR
00-7,
SC/D,
RVS
FID'I'
DATA
\
K28.5
I
K28.5
1IDY IS HIGH IN FIELD OF K28.5S
\
I
"'--
RriY IS LOW FOR LAST K28.5
ROY IS LOW FOR DATA
PARALLEL
DATA OUT
8923-19
Figure 3. CY7B933 Receiver Data Pipeline in Encoded Mode
4-12
CY7B923
CY7B933
~.,~
==-; CYPRESS
CKR STRETCHES AS
DATA BOUNDARY CHANGES
RF LATCHED ON
FALLING EDGE OF CKR
CKR
RF
00-7.
SC/I).
RVS
DATA
DATA
X
DATA
X
DATA
X. .
_D_A_TA_...JX
K2B.5
DATA
RD'Y' IS HIGH WHILE WAITING FOR K2B.5
RD'Y'IS LOW
FORK28.5
Figure 4. CY7B933 Framing Operation in Encoded Mode
When the RFpin is asserted HIGH. RDY leaves it normal mode of
operation and is asserted HIGH while the framer searches the data
stream for a K28.5 character. After the framer has synchronized to
a K28.5 character, the Receiver will assert the RDY pin LOW
when the K28.5 character is present at the parallel output. The
RDY pin will then resume its normal operation as dictated by the
MODE and BISTEN pins.
The normal operation of the RDY pin in encoded mode is to signal
when parallel data is present at the output pins by pulsing LOW
with a 60% LOW/40% HIGH duty cycle. RDY does not pulse
LOW in a field of K28.5 characters; however, RDY does pulse
LOW for the last K28.5 character in the field or for any single
K28.5. In unencoded mode, the normal operation of the RDY pin
is to signal when any K28.5 is at the parallel output pins.
The Transmitter and Receiver parallel interface timing and
functionality can be made to match the timing and functionality of
either an asynchronous FIFO or a clocked FIFO by appropriately
connecting signals (See Figure 5). Proper operation of the FIFO
interface depends upon various FIFO-specific access and response
specifications.
The HOTLinkTransmitter and Receiver serial interface provides a
seamless interface to various types of media. Aminimal number of
external components are needed to properly terminate
transmission lines and provide PECL loads. For proper power
supply decoupling, a single O.Oll!Fforeach device is all that is required to bypass the Vee and GND pins. Figure 6 illustrates a
HOTLink TIansmitter and Receiver interface to fiber optic and
copper media. More information on interfacing HOTLink tovarious media can be found in the HOTLinkDesign Considerations application note.
CY7B923 HOTLink Transmitter Operating Mode
Description
In normal operation, the TIansmitter can operate in either of two
modes. The Encoded mode allows a user to send and receive eight
(8) bit data and control information without first converting it to
transmission characters. The Bypass mode is used for systems in
which the encoding and decoding is performed in an external protocol controller.
In either mode, data is loaded into the Input register of the Transmitter on the rising edge of CKW. The input timing and functional
response ofthe Transmitter input can be made to match the timing
RD'Y' RESUMES
NORMAL
OPERATION
8923-20
and functionality of either an asynchronous FIFO or a clocked
FIFO by an appropriate connection of input signals (See Figure 5).
Proper operation of the FIFO interface depends upon various
FIFO-specific access and response specifications.
Encoded Mode Operation
In Encoded mode the input data is int~reted as eight bits of data
(Do - D7), a context control bit (SCID), and a system diagnostic
input bit (SV~. If the context of the data is to be normal message
data, the SC/D input should be LOW, and the data should be encoded using the valid data character set described in the Valid Data
Characters section ofthis datasheet. If the context of the data is to
be control or protocol information, the SCJl) input will be HIGH,
and the data will be encoded using the valid special character set
described in the Valid Special Character Codes and Sequences section. Special characters include all protocol characters necessary
to encode packets for Fibre Channel, ESCON, proprietary systems, and diagnostic purposes.
The diagnostic characters and sequences available as Special Characters include those for Fibre Channel link testing, as well as codes
to be used for testing system response to link errors and timing. A
Violation symbol can be explicitly sent as part of a user data packet
(i.e., send CO.7; D7-0 = 111 00000 andSC/D = l),oritcanbesent
in response to an external system using the SVS input. This will allow system diagnostic logic to evaluate the errors in an unambiguous manner, and will not require any modification to the transmission interface to force transmission errors for testing purposes.
Bypass Mode Operation
In Bypass mode the input data is interpreted as ten (10) bits
(Db-h), SCJl) (D.), and SVS (Dj) of pre-encoded transmission
data to be serialized and sent over the link. This data can use any
encoding method suitable to the designer. The only restrictions
upon the data encoding method is that it contain suitable transition
density for the Receiver PLL data synchronizer (one per 10 bit
byte), and that it be compatible with the transmission media.
Data loaded into the Input register on the rising edge of CKW will
be loaded into the Shifter on the subsequent rising edges of CKW.
It will then be shifted to the outputs one bit at a time using the internal clock generated by the clock generator. The first bit of the
transmission character (D.) will appear at the output (OUTA±,
OUTB±, and OUTC±) after the next CKW edge.
4-13
CY7B923
CY7B933
.~YPRESS
ASYNCHRONOUS FIFO
CLOCKED FIFO
7C42X/3X/6X!7X
7C44X/5X
HOTLINK TRANSMITTER
HOTLINK TRANSMITTER
HOTLINK RECEIVER
HOTLINK RECEIVER
w
CKW
Do- B
Do_ B
7C42X/3X/6X/7X
7C44X/5X
ASYNCHRONOUS FIFO
CLOCKED FIFO
8923-21
Figure S. Seamless FIFO Interface
While in either the Encoded mode or Bypass mode, if a CKW edge
arrives when the inputs are not enabled (ENA and ENN both
HIGH), the Encoder will insert a pad character K28.5 (e.g., C5.0)
to maintain proper link synchronization (in Bypass mode the proper sense of running disparity cannot be guaranteed for the first pad
character, butis correct for all pad characters that follow). This automatic insertion of pad characters can be inhibited by insuring
that the 1tansmitter is always enabled (i.e., ENA or ENN is hardwired LOW).
PECL Output Functional and Connection Options
The three pairs of PECL outputs all contain the same information
and are intended for use in systems with multiple connections.
Each output pair may be connected to a different serial media,
each of which may be a different length, link type, or interface
technology. For systems that do not require all three output pairs,
the unused pairs should be wired to Vee to minimize the power
dissipated by the output circuit, and to minimize unwanted noise
generation. An internal voltage comparator detects when an output differential pair is wired to Vee, causing the current source for
that pair to be disabled. This results in a power savings of around
5 rnA for each unused pair.
In systems that require the outputs to be shut off during some periods when link transmission is prohibited (e.g., for laser safetyfunctions), the FOTO input can be asserted. While it is possible to insure that the output state of the PECLdrivers is LOW (i.e., light is
off) by sending all O's in Bypass mode, it is often inconvenient to
insert this level of control into the data transmission channel, and
it is impossible in Encoded mode. FOTO is provided to simplify
and augment this control function (typically found in laser-based
trallSiUissioli Sy~t~lll~). FOTO wili force QUTA + and OU 1 H+ to
go Law, OUTA- and OUTB- to go HIGH, while allowing
OUTC± to continue to function normally (OUTe is typically used
as a diagnostic feedback and cannot be disabled). This separation
of function allows various system configurations without undue
load on the control function or data channel logic.
Transmitter Serial Data Characteristics
The CY7B923 HOTLink1tansmitter serial output conforms to the
requirements of the Fibre Channel specification. The serial data
output is controlled by an internal Phase-Locked Loop that multiplies the frequency of CKWby ten (10) to maintain the proper bit
clock frequency. The jitter characteristics (including both PLL and
logic components) are shown below:
4-14
CY7B923
CY7B933
_?cYPRESS
Tx PEel Load
MODE
Config
(:::===+15 FOTO
Con~QI
:~==~~2~3~
_24
Status
=
BfSTEN
82
OUTA-j 26
T~~:~?tfe~
B RP
19 SCID (Oa) OUTB
~7 DO (Db) OUT
Data
(
~
g~ m~\
270
1
82
130
Tx PECl Load
270
t
Coaxer
Twisted Pair
06 (Og)
07 (Oh)
SVS(Oj)
CKW
Transmission
Line
C ...._ _":,::e:;,:rm;::in:;:at:::;io::;,n_.....
--..=_+-r-----.
Config
con~ot
(
(
Status
-(
26 MODE
Coax or
Twisted Pair
O ___------+---~~~
25 REFClK
~~~~~~4~
Tx
Power Dissipation
~2 ~m~
1t
Fiber Optic
B
28 Unused Ouput Left
1 Open to Minimize
03 (De)
4
130
OUTA,++1~2~7====~A~~=~;:::=~I======t=~
~3 ~ CY7B933
llISTEl'I
7~
SC/O(Oa)
~ DO (Ob)
19
82
01 (Oe)
1
02 (Od)
14 03
(Oe)
13
04(Oi)
IA+I-j:::===jo~f====+=::;:;:=~~==t=~
lA-I-
12 05 (Of)
1t
~g
Fiber Optic
Rx
82
g;ig~l
RVS(Oj)
CKR GNO
B923-22
Figure 6. HOTLink Connection Diagram
Deterministic Jitter (Dj) < 35 ps (peak-peak). Typicallymeasured while sending a continuous K28.5 (C5.0).
Random Jitter (Rj) < 175ps (peak-peak).1YPicallymeasured
while sending a continuous K28.7 (C7.0).
IhlDsmitter Test Mode Description
The CY7B923 Transmitter offers two types oftestmode operation,
BIST mode and Thst mode. In a normal system application, the
Built-In Self-Test (BIST) mode can be used to check the functionality of the 1tansmitter, the Receiver, and the link connecting them.
This mode is available with minimal impact on user system logic,
and can be used as part of the normal system diagnostics. Typical
connections and timing are shown in Figure 7.
BISTMode
BIST mode functions as follows:
1. Set BISTEN LOW to begin test pattern generation. 1tansmitter begins sending bit rate ... 10lD...
2. Set either ENA or ENN LOW to begin pattern sequence generation (use of the Enable pin not being used for normal FIFO
or system interface can minimize logic delays between the controller and transmitter).
3. Allow the Transmitter to run thro~ several BIST loops or until the Receiver test is complete. RP will pulse LOW once per
BIST loop, and can be used by an external counter to monitor
the number of test pattern loops.
4. When testing is completed, set BISTEN HIGH and ENA and
ENN HIGH and resume normal function.
Note: It may be advisable to send violation characters to test the
RVS output in the Receiver. This can be done by explicitly sending
a violation with the SVS input, or allowing the transmitter BIST
loop to run while the Receiver runs in normal mode. The BIST
loop includes deliberate violation symbols and will adequately test
the RVS function.
BIST mode is intended to check the entire function of the Transmitter (except the 1tansmitterinput pins and the bypass function in
the Encoder), the seriallink, and the Receiver. It augments normal
factory ATE testing and provides the designer with a rigorous test
mechanism to check the link transmission system without requiring
any significant system overhead.
While in Bypass mode, the BIST logic will function in the sameway
as in the Encoded mode. MODE = HIGH and BISTEN = LOW
causes the 1tansmitter to switch to Encoded mode and begin sending the BISTpattern, as if MODE =Law. When BISTEN returns
4-15
~
CY7B923
IYCYPRESS ==============CY=7B=9=33=
CY7B923
DON'T CARE
FOTO
DON'T CARE
I
L~~1>
-+-1-----!(~i).......u '»
I
WITHIN SPEC.
CKW
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
MODE
Rp
DON'T CARE
SCfi)
OUTA 1-_ __
Do -7
OUTB 1-_ __
SVS
OUTC 1-_ _
DON'T CARE
8
LOW
-ir--~S~S~~~)----~rTx
STA.;r
I
»
SS
I
Tx
HIGH
SpP
CY7B933
WITHIN SPEC.
REFCLK
DON'T CARE
LOW
MODE
RF
SO
CKR
SCfi)
8
ERROR
INA
00 -7
INB
Os,)
RVS
RD'i'
AlB
LOW
BISTEN
B923-23
Figure 7. Built..ln Self..Test Illustration
to HIGH, the Transmitter resumes normal Bypass operation. In
Thst mode the BIST function works as in the Normal mode. For
more information on BIST, consult the "HOTLink Built-In SelfThst" Application Note.
Test Mode
The MODE input pin selects between three transmitter functional
modes. W~en wired to Vce, theD(a-;D in~uts bypass the Encoder
and load dIrectly from the Input register mto the Shifter. When
wired to GND, the inputs DO-7, SVS, and SCID are encoded using
the ~ibre Channel8B/lOB codes and sequences (shown at the end
of thIS datasheet). Since the 'Ii'ansmitter is usually hard wired to
Encoded or Bypass mode and not switched between them a third
function is provided for the MODE pin. Thst mode is sel~cted by
floating the MODE pin (internal resistors hold the MODE pin at
Vcd2). Test mode is used for factory or incoming device test.
Thst mode causes the 'Ii'ansmitter to function in its Encoded mode
but with OutA + /OutB + (used as a differential test clock input) a~
the bit rate clock input instead of the internal PLL-generated bit
clock. In this mode, inputs are clocked by CKW and transfers between the Input register and Shifter are timed by the internal
c<;n~nters. The bit:clock and CKW must maintain a fix~hase and
dlvlde-by-ten ratio. The phase and pulse width of RP are controlled by phases of the bit counter (PLL feedback counter) as in
Normal mode. Input and output patterns can be synchronizedwith
internal logic by observing the state of RP or the device can be
4-16
CY7B923
CY7B933
=- -~
'CYPRESS = = = = = = = = = = = = = = = =
initialized to match an A1E test pattern using the following
technique:
1. With the MODE pin either HIGH or Law, stop CKW and
bit-clock.
2. Force the MODE pin to MID (open or V cd2) while the clocks
are stopped.
3. Start the bit-clock and let it run for at least 2 cycles.
4. Start the CKW clock at the bit-clock/lO rate.
Thst mode is intended to allow logical, DC, and AC testing of the
ltansmitter without requiring that the tester check output data
patterns at the bit rate, or accommodate the PLL lock, tracking,
and frequency range characteristics that are required when the
HOTLink part operates in its normal mode.
Th use
OutA+/OutB+ as the test clock input, the FOTO input is held
HIGH while in Test mode. This forces the two outputs to go to an
"PECL Law," which can be ignored while the test system creates
a differential input signal at some higher voltage.
CY7B933 HOTLink Receiver Operating Mode
Description
The Violation symbol that can be explicitly sent as part of a user
dat!!packet (i.e., Transmitter sending CO.7; D7 -0 = 111 00000 and
SaD = 1; or SVS = 1) will be decoded and indicated in exactly the
same way as a noise-induced error in the transmission link. This
function will allow system diagnostics to evaluate the error in an
unambiguous manner, and will not require any modification to the
receiver data interface for error-testing purposes.
Bypass Mode Operation
In Bypass mode the serial input data is not decoded, and is transferred directly from the Decode register to the Output register's 10
bits (O(a-j)' It is assumed that the data has been pre-encoded
prior to transmission, and will be decoded in subsequent logic external to HOTLink. This data can use any encoding method suitable to the designer. The only restrictions upon the data encoding
method is that it contain suitable transition density for the Receiver PLL data synchronizer (one per 10 bit byte) and that it be compatible with the transmission media.
The framer function in Bypass mode is identical to Encoded mode,
so a K28.5 pattern can still be used to re-frame the serial bit stream.
Parallel Output Function
In normal user operation, the Receiver can operate in either of two
modes. The Encoded mode allows a user system to send and receive 8-bit data and control information without first converting it
to transmission characters. The Bypass mode is used for systems in
which the encoding and decoding is performed by an external protocol controller.
In either mode, serial data is received at one of the differential line
receiver inputs and routed to the Shifter and the Clock Synchronization. The PLL in the Clock Synchronizer aligns the internally
generated bit rate clock with the incoming data stream and clocks
the data into the shifter. At the end of a byte time (ten bit times),
the data accumulated in the shifter is transferred to the Decode
register.
To properly align the incoming bit stream to the intended byte
boundaries, the bit counter in the Clock Synchronizer must be initialized. The Framer logic block checks the incoming bit stream for
the unique pattern that defines the byte boundaries. This combinatoriallogic filter looks for the X3.230 symbol defined as "Special
Character Comma" (K28.5). Once K28.5 is found, the free running bit counter in the Clock Synchronizer block is synchronously
reset to its initial state, thus "framing" the data to the correct byte
boundaries.
Since noise-induced errors can cause the incoming data to be corrupted, and since many combinations of error and legal data can
create an alias K28.5, an option is included to disable resynchronization of the bit counter. The Framer will be inhibited when the RF input is held LOW. When RF rises, RDY will be inhibited until a K28.5
has been detected, and RDY will resume its normal function. Data
will continue to flow through the Receiver while RDY is inhibited.
Encoded Mode Operation
In Encoded mode the serial input data is decoded into eight bits of
data (00 - 07), a context control bit (SC;D), and a system diagnostic output bit (RVS). If the pattern in the Decode register is
found in the Valid Data Characters table, the context ofthe data is
decoded as normal message data and the SC;D output will be
Law. If the incoming bit pattern is found in the Valid Special
Character Codes and Sequences table, iti~nterpreted as "control"
or "protocol information," and the SC/D output will be HIGH.
Special characters include all protocol characters defined for use in
packets for Fibre Channel, ESCON, and other proprietary and
diagnostic purposes.
The 10 outputs (00-7, SC;D, and RVS) all transition simultaneously, and are aligned with RDY and CKR with timing allowances to interface directly with either an asynchronous FIFO or a
clocked FIFO. 1)'pical FIFO connections are shown in Figure 5.
Data outputs can be clocked into the system using either the rising
or falling edge of CKR, or the rising or falling edge of RDY. If
CKR is used, RDY can be used as an enable for the receiving logic.
A LOW pulse on RDY shows that new data has been received and
is ready to be delivered. The signal on RDY is a 60% - LOW duty
cycle byte-rate pulse train suitable for the write pulse in asynchronous FIFOs such as the CY7C42X, or the enable write input on
Clocked FIFOs such as the CY7C44X. HIGH on RDY shows that
the received data appearing at the outputs is the null character
(normally inserted by the transmitter as a pad between data inputs)
and should be ignored.
When the Transmitter is disabled it will continuously send pad characters (K28.5). To assure that the receive FIFO will not be overfilled
with these dummy bytes, the RDY pulse output is inhibited during fill
strings. Data at the 00_70utputswillreflectthe correct received data,
but will not appear to change, since a string of K28.5s all are decoded
as 07-0 =00000101 and SC;D = 1 (CS.O). When new data appears
(not K28.5), the RDY output will resume normal function. The "last"
K28.5 will be accompanied by a normal RDY pulse.
Fill characters are defined as any K28.5 followed by another K28.5.
All fill characters will not cause RDY to pulse. Any K28.5 followed
by any other character (including violation or illegal characters)
will be interpreted as usable data and will cause RDY to pulse.
As noted above, RDY can also be used as an indication of correct
framing of received data. While the Receiver is awaiting receipt of
a K28.5 with RF HIGH, the RDY outputs will be inhibited. When
RDY resumes, the received data will be properly framed and will
be decoded correctly. In Bypass mode with RF HIGH, RDY will
pulse once for each K28.5 received. For more information on the
RDY pin, consult the "HOTLink CY7B933 RDYPin Description"
application note.
4-17
I
CY7B923
CY7B933
Code rule violations and reception errors will be indicated as follows:
RVS scm Oouts Name
1. Good Data code received
with good Running Disparity
OO-FF DO.0-31.7
(RD)
0
0
2. Good Special Character
code received with good RD 0
OO-OB CO.0-l1.0
3. K28.7 immediately following
K28.1 (ESCON Connect_SOF)O
1
27
C7.1
4. K28.7 immediately following
47
C7.2
K28.5 (ESCON Passive_SOF) 0
5. Unassigned code received
EO CO.7
6. -K28.5+ received when
RDwas +
1
El C1.7
7. +K28.5- received when
RDwas E2 C2.7
8. Good code received
with wrong RD
E4 C4.7
Receiver Serial Data Requirements
The CY7B933 HOTLinkReceiver serial input capability conforms
to the requirements of the Fibre Channel specification. The serial
data input is tracked by an internal Phase-Locked Loop that is used
to recover the clock phase and to extractthe data from the serial bit
stream. Jitter tolerance characteristics (including both PLL and
logic component requirements) are shown below:
Deterministic Jitter tolerance (Dj) >40% of tB. l:ypically
measured while receiving data carried by a bandwidth-limited
channel (e.g., a coaxial transmission line) while maintaining a
Bit Error Rate (BER) <10- 12.
Random Jitter tolerance (Rj) > 90% of tB. lJpically measured while receiving data carried by a random-noise-limited
channel (e.-g., a ~ber:optic tra!lsmission system with low liEht
levels) while maIntaInIng a Bit Error Rate (BER) <10- 2.
Total Jitter tolerance >90% of tB. Total of Dj + Rj.
PLL-Acquisition time <500-bit times from worst-case phase
or frequency change in the serial input data stream, to receiving data within BER objective of 10- 12. Stable power supplies within specifications, stable REFCLK input frequency
and normal data framing protocols are assumed. Note: Acquisition time is measured from worst-case phase or frequency change to zero phase and frequency error. As a result ofthe
receiver's wide jitter tolerance, valid data will appear at the receiver's outputs a few byte times after a worst-case phase
change.
Receiver Test Mode Description
2. Monitor RVS and checkfor any byte time with the pin HIGH to
detect pattern mismatches. RDY will pulse HIGH once per
BIST loop, and can be used by an external counter to monitor
test pattern progress. 00-7 and SC/D will show the expected
pattern and may be useful for debug purposes.
3. When testing is completed, set BISTEN HIGH and resume normal function.
Note: A specific test of the RVS output may be required to assure
an adequate test. To perform this test, it is only necessary to have
the 1l:ansmitter send violation (SVS = HIGH) for a few bytes before beginning theBISTtest sequence. Alternatively, the Receiver
could enter BIST mode after the 1l:ansmitter has begun sending
BIST loop data, or be removed before the Transmitter finishes
sending BIST loops, each of which contain several deliberate violations and should cause RVS to pulse HIGH.
BIST mode is intended to check the entire function of the 1l:ansmitter, serial link, and Receiver. It augments normal factory ATE
testing and provides the user system with a rigorous test mechanism to check the link transmission system, without requiring any
significant system overhead.
When in Bypass mode, the BIST logicwill function in the same way
as in the Encoded mode. MODE = HIGH and BISTEN = LOW
causes the Receiver to switch to Encoded mode and begin checking
the decoded received data of the BIST pattern, as if MODE =
Law. When BISTEN returns to HIGH, the Receiver resumes
normal Bypass operation. In Thstmode the BISTfunction works as
in the normal mode.
Test Mode
The MODE input pin selects between three receiver functional
modes. When wired to Vee, the Shifter contents bypass the Decoder
and go directly from the Decoder latch to the 0. _j inputs of the Output latch. When wired to GND, the outputs are decoded using the
8B/IOB codes shown at the end of this datasheet and become 00-7,
RVS, and sc/D. The third function is Test mode, used for factory or
incoming device test. 1bis mode can be selected by leaving the
MODE pin open (internal circuitry forces the open pin to V cel2).
Test mode causes the Receiver to function in its Encoded mode,
but with INB (INB+ ) as the bit rate Test clock instead of the Internal PLL generated bit clock. In this mode, transfers between the
Shifter, Decoder register and Output register are controlled by
theirnormallogic, but with an external bit rate clock instead ofthe
PLL (the recovered bit clock). Internal logic and test pattern inputs can be synchronized by sending a SYNC pattern and allowing
the Framer to align the logic to the bit stream. The flow is as follows:
1. Assert Test mode for several test clock cycles to establish normal
counter sequence.
2. Assert
Rr to enable refraining.
The CY7B933 Receiver offers two types of test mode operation,
BIST mode and Thst mode. In a normal system application, the
Built-In Self-Thst (BIST) mode can be used to check the functionality ofthe 1l:ansmitter, the Receiver and the link connecting them.
This mode is available with minimal impact on user system logic,
and can be used as part ofthe normal system diagnostics. l:ypical
connections and timing are shown in Figure 7.
BISTMode
BIST Mode function is as follows:
3. Input a repeating sequence of bits representing K28.5 (Sync).
4. RDY falling shows the byte boundary established by the K28.5
input pattern.
5. Proceed with pattern, voltage and timing tests as is convenient
for the test program and tester to be used.
(While in Test mode and in BIST mode with RF HIGH, the 00-7,
RVS, and SC/D outputs reflect various internal logic states and not
the received data.)
1. Set BISTEN LOW to enable self-test generation and await RDY
LOW indicating that the initialization code has been received.
Test mode is intended to allow logical, DC, and AC testing of the
Receiver without requiring that the tester generate input data at
the bit rate or accommodate the PLL lock, tracking and frequency
4-18
CY7B923
CY7B933
range characteristics that are required when the part operates in its
normal mode.
X3.230 Codes and Notation Conventions
Information to be transmitted over a serial link is encoded eight bits at
a time into a IO-bit Transmission Character and then sent serially, bit
by bit. Information received over a serial link is collected ten bits at a
time, and those Transmission Characters that are used for data (Data
Characters) are decoded into the correct eight-bit codes. The 10-bit
Transmission Code supports all 256 8-bit combinations. Some of the
remaining Transmission Characters (Special Characters) are used for
functions other than data transmission.
The primary rationale for use of a Transmission Code is to improve
the transmission characteristics of a serial link. The encoding defined by the Transmission Code ensures that sufficient transitions
are present in the serial bit stream to make clock recovery possible
at the Receiver. Such encoding also greatly increases the likelihood of detecting any single or multiple bit errors that may occur
during transmission and reception of information. In addition,
some Special Characters of the Transmission Code selected by
Fibre Channel Standard consist of a distinct and easily recognizable bit pattern (the Special Character Comma) that assists a Receiver in achieving word alignment on the incoming bit stream.
Notation Conventions
The documentation for the 8B/IOB Transmission Code uses letter
notation for the bits in an 8-bit byte. Fibre Channel Standard notation uses a bit notation of A, B, C, D, E, F, G, H for the 8-bit byte
for the raw 8-bit data, and the letters a, b, c, d, e, i, f, g, h, j for encoded IO-bit data. There is a correspondence between bit A and
bit a, Band b, C and c, D and d, E and e, F and f, G and g, and Hand
h. Bits i and j are derived, respectively, from (A,B,C,D,E) and
(F,G,H).
The bit labeled A in the description of the 8B/lOB Transmission
Code corresponds to bit 0 in the numbering scheme of the FC-2
specification, B corresponds to bit 1, as shown below.
FC-2 bit designation7 6 5 4 3 2 1 0
H01Link D/Q designation- 7 6 5 4 3 2 1 0
8B/10B bit designationH G FED C B A
To clarify this correspondence, the following example shows the
conversion from an FC-2 Valid Data Byte to a Transmission Character (using 8B/10B Transmission Code notation)
FC-2 45
Bits: 76543210
0100 0101
Converted to 8B/1 OB notation (note carefully that the order of bits
is reversed):
Data Byte Name D5.2
Bits:ABCDE FGH
10100 010
1tanslated to a transmission Character in the 8B/1 OB Transmission
Code:
Bi ts: abcdei 1.ghj
101001 0101
Each valid Transmission Character of the 8B/10B Transmission
Code has been given a name using the following convention: cxx.y,
where c is used to show whether the Transmission Character is a
Data Character (c is set to D, and the SC/D pin is LOW) or a Special Character (c is set to K, and the SC/D pin is HIGH). When c
is set to D, xx is the decimal value ofthe binary number composed
of the bitsE, D, C, B, andAin that order, and they is the decimal
value of the binary number composed ofthe bits H, G, and F in that
order. When c is set to K, xx and yare derived by comparing the
encoded bit patterns of the Special Character to those patterns
derived from encoded Valid Data bytes and selecting the names of
the patterns most similar to the encoded bit patterns of the Special
Character.
Under the above conventions, the Transmission Character used for
the examples above, is referred to by the name D5.2. The Special
Character K29.7 is so named because the first six bits (abcdei) of
this character make up a bit pattern similar to that resulting from
the encoding of the unencoded 11101 pattern (29), and because
the second four bits (fghj) make up a bit pattern similar to that resulting from the encoding of the unencoded 111 pattern (7).
Note: This definition of the lO-bit Transmission Code is based on
(and is in basic agreementwith) the following references, which describe the same 10-bit transmission code.
AX. Widmer and P.A Franaszek. ':.\ DC-Balanced, PartitionedBlock, 8B/lOB Transmission Code" IBM Journal of Research and
Development, 27, No.5: 440-451 (September, 1983).
U.S. Patent 4,488,739. Peter A Franaszek and Albert X. Widmer.
"Byte-Oriented DC Balanced (0.4) 8B/lOB Partitioned Block
Transmission Code" (December 4,1984).
Fibre Channel Physical and Signaling Interface (dpANS
X3.230-199X ANSI FC- PH Standard).
IBM Enterprise Systems Architecture/390 ESCON I/O Interface
(document number SA22-7202).
8B/IOB Transmission Code
The following information describes how the tables shall be used
for both generating valid Transmission Characters (encoding) and
checking the validity of received Transmission Characters (decoding). It also specifies the ordering rules to be followed when transmitting the bits within a character and the characters within the
higher-level constructs specified by the standard.
Transmission Order
Within the definition of the 8B/lOB Transmission Code, the bit
positions of the Transmission Characters are labeled a, b, c, d, e, i,
f, g, h,j. Bit "a" shall be transmitted first followed by bits b, c, d, e,
i, f, g, h, and j in that order. (Note that bit i shall be transmitted
between bit e and bit f, rather than in alphabetical order.)
Valid and Invalid Transmission Characters
The following tables define the valid Data Characters and valid
Special Characters (K characters), respectively. The tables are
used for both generating valid Transmission Characters (encoding)
and checking the validity of received Transmission Characters (decoding). In the tables, each Valid-Data-byte or Special-Charactercode entry has two columns that represent two (not necessarily different) Transmission Characters. The two columns correspond to
the current value of the running disparity ("Current RD-" or
"Current RD+ "). Running disparity is a binary parameter with either the value negative (-) or the value positive (+).
After powering on, the 1tansmitter may assume either a positive or
negative value for its initial running disparity. Upon transmission
of any Transmission Character, the transmitter will select the proper version of the 1tansmission Character based on the current running disparityvalue, and the Transmitter shall calculate a new value
for its running disparity based on the contents of the transmitted
character. Special Character codes Cl.7 and C2.7 can be used to
force the transmission of a specific Special Character with a specific running disparity as required for some special sequences in
X3.230.
4-19
I
CY7B923
CY7B933
acter byte to be encoded and transmitted. Table 1 shows naming
notations and examples of valid transmission characters.
After powering on, the Receiver may assume either a positive or
negative value for its initial running disparity. Upon reception of
anynansmission Character, the Receiver shall decide whether the
nansmission Character is valid or invalid according to the following rules and tables and shall calculate a new value for its Running
Disparity based on the contents of the received character.
The following rules for running disparity shall be used to calculate
the new running-disparity value for Transmission Characters that
have been transmitted (nansmitter's running disparity) and that
have been received (Receiver's running disparity).
Running disparity for a nansmission Character shall be calculated
from sub-blocks, where the first six bits (abcdei) form one subblock and the second four bits (fghj) form the other sub-block.
Running disparity at the beginning of the 6-bit sub-block is the running disparity at the end of the previous Transmission Character.
Running disparity at the beginning ofthe4-bit sub-block is the running disparity at the end of the 6-bit sub-block. Running disparity
at the end of the nansmission Character is the running disparity at
the end of the 4-bit sub-block.
Running disparity for the sub-blocks shall be calculated as follows:
Table 1. Valid Transmission Characters
Data
DIN or QOUT
1. Running disparity at the end of any sub-block is positive if the
sub-block contains more ones than zeros. It is also positive at
the end of the 6-bit sub-block if the 6-bit sub-block is 000111,
and it is positive at the end ofthe 4-bit sub-block ifthe 4-bit subblock is 0011.
2. Running disparity at the end of any sub-block is negative if the
sub-block contains more zeros than ones. It is also negative at
the end of the 6-bit sub-block if the 6-bit sub-block is 111000,
and it is negative at the end of the 4-bit sub-block if the 4-bit
sub-block is 1100.
3. Otherwise, running disparity at the end of the sub-block is the
same as at the beginning of the sub-block.
Use of the Tables for Generating Transmission Characters
Byte Name
765
'3210
DO.O
000
00000
Hex Value
00
D1.0
000
00001
01
D2.0
000
00010
02
D5.2
010
000101
45
D30.7
111
11110
FE
D31. 7
111
11111
FF
Use of the Tables for Checking the Validity of Received Transmission Characters
The column corresponding to the current value of the Receiver's
running disparity shall be searched for the received nansmission
Character. If the received nansmission Character is found in the
proper column, then the nansmission Character is valid and the
associated Data byte or Special Character code is determined (decoded). If the received Transmission Character is not found in that
column, then the Transmission Character is invalid. This is called
a code violation. Independent of the Transmission Character's validity, the received Transmission Character shall be used to calculate a new value of running disparity. The new value shall be used
as the Receiver's current running disparity for the next received
nansmission Character.
Detection of a code violation does not necessarily show that the
Transmission Character in which the code violation was detected is
in error. Code violations may result from a prior error that altered
the running disparity of the bit stream which did not result in a detectable error at the nansmission Character in which the error occurred. Table 2 shows an example of this behavior.
The appropriate entry in the table shall be found for the Valid Data
byte or the Special Character byte for which a nansmission Characteris to be generated (encoded). The currentvalueofthe nansmitter's running disparity shall be used to select the nansmission
Character from its corresponding column. For each nansmission
Character transmitted, a newvalue of the running disparity shall be
calculated. This new value shall be used as the nansmitter's current running disparity for the next Valid Data byte or Special Char-
Table 2. Code Violations Resulting from Prior Errors
RD
Character
RD
Character
RD
Character
RD
Transmitted data character
-
021.1
-
010.2
023.5
nansmitted bit stream
-
101010 1001
-
0101010101
Bit stream after error
-
101010 1011
+
0101010101
Decoded data character
-
021.0
+
010.2
+
+
+
+
+
+
4-20
111010 1010
111010 1010
Code Violation
-
-., ~
~;CYPRESS
CY7B923
CY7B933
================
Valid Data Characters (SC/D
= LOW)
CurreutRD-
CurrentRD+
EDCBA
abcdei
fghj
abcdei
fghj
Data
Byte
Name
HGF
EDCBA
abcdei
fghj
abcdei
fghj
000
00000
100111
0100
011000
1011
DO.1
001
00000
100111
1001
011000
1001
Dl. 0
000
00001
011101
0100
100010
1011
D1.1
001
00001
011101
1001
100010
1001
D2.0
000
00010
101101
0100
010010
1011
D2.1
001
00010
101101
1001
010010
1001
D3.0
000
00011
110001
1011
110001
0100
D3.1
001
00011
110001
1001
110001
1001
D4.0
000
00100
110101
0100
001010
1011
D4.1
001
00100
110101
1001
001010
1001
DS.O
000
00101
101001
1011
101001
0100
DS.1
001
00101
101001
1001
101001
1001
D6.0
000
00110
011001
1011
011001
0100
D6.1
001
00110
011001
1001
011001
1001
D7.0
000
00111
111000
1011
000111
0100
D7.1
001
00111
111000
1001
000111
1001
Data
Byte
Name
HGF
DO.O
Bits
Bits
CurrentRD-
CurrentRD+
DS.O
000
01000
111001
0100
000110
1011
DS.1
001
01000
111001
1001
000110
1001
D9.0
000
01001
100101
1011
100101
0100
D9.1
001
01001
100101
1001
100101
1001
D10.0
000
01010
010101
1011
010101
0100
D10.1
001
01010
010101
1001
010101
1001
D11. 0
000
01011
110100
1011
110100
0100
D11.1
001
01011
110100
1001
110100
1001
D12.0
000
01100
001101
1011
001101
0100
D12.1
001
01100
001101
1001
001101
1001
D13.0
000
01101
101100
1011
101100
0100
D13.1
001
01101
101100
1001
101100
1001
D14.0
000
01110
011100
1011
011100
0100
D14.1
001
01110
011100
1001
011100
1001
D1S.0
000
01111
010111
0100
101000
1011
D1S .1
001
01111
010111
1001
101000
1001
D16.0
000
10000
011011
0100
100100
1011
D16.1
001
10000
011011
1001
100100
1001
D17.0
000
10001
100011
1011
100011
0100
D17.1
001
10001
100011
1001
100011
1001
D1S.0
000
10010
010011
1011
010011
0100
D18.1
001
10010
010011
1001
010011
1001
D19.0
000
10011
110010
1011
110010
0100
D19.1
001
10011
110010
1001
110010
1001
D20.0
000
10100
001011
1011
001011
0100
D20.1
001
10100
001011
1001
001011
1001
D21. 0
000
10101
101010
1011
101010
0100
D21.1
001
10101
101010
1001
101010
1001
D22.0
000
10110
011010
1011
011010
0100
D22.1
001
10110
011010
1001
011010
1001
D23.0
000
10111
111010
0100
000101
1011
D23.1
001
10111
111010
1001
000101
1001
D24.0
000
11000
110011
0100
001100
1011
D24.1
001
11000
110011
1001
001100
1001
D2S.0
000
11001
100110
1011
100110
0100
D2S.1
001
11001
100110
1001
100110
1001
D26.0
000
11010
010110
1011
010110
0100
D26.1
001
11010
010110
1001
010110
1001
D27.0
000
11011
110110
0100
001001
1011
D27.1
001
11011
110110
1001
001001
1001
D2S.0
000
11100
001110
1011
001110
0100
D28.1
001
11100
001110
1001
001110
1001
D29.0
000
11101
101110
0100
010001
1011
D29.1
001
11101
101110
1001
010001
1001
D30.0
000
11110
011110
0100
100001
1011
D30.1
001
11110
011110
1001
100001
1001
D31. 0
000
11111
101011
0100
010100
1011
D31.1
001
11111
101011
1001
010100
1001
4-21
II
CY7B923
CY7B933
Valid Data Characters
Data
Byte
Name
HGF EDCBA
DO.2
010
00000
Dl. 2
010
D2.2
010
D3.2
D4.2
(scll> =
LOW) (continued)
abcdei
fgbj
abcdei
fgbj
Data
Byte
Name
100111
0101
011000
0101
DO.3
011
00000
00001
011101
0101
100010
0101
Dl. 3
011
00010
101101
0101
010010
0101
D2.3
011
010
00011
110001
0101
110001
0101
D3.3
010
00100
110101
0101
001010
0101
Bits
CurrentRD-
CurrentRD+
Bits
HGF EDCBA
CurrentRD-
CurrentRD+
abcdei
fgbj
abcdei
fgbj
100111
0011
011000
1100
00001
011101
0011
100010
1100
00010
101101
0011
010010
1100
011
00011
110001
1100
110001
0011
D4.3
011
00100
110101
0011
001010
1100
DS.2
010
00101
101001
0101
101001
0101
DS.3
011
00101
101001
1100
101001
0011
D6.2
010
00110
011001
0101
011001
0101
D6.3
011
00110
011001
1100
011001
0011
D7.2
010
00111
111000
0101
000111
0101
D7.3
011
00111
111000
1100
000111
0011
DB.2
010
01000
111001
0101
000110
0101
DB.3
011
01000
111001
0011
000110
1100
0011
D9.2
010
01001
100101
0101
100101
0101
D9.3
011
01001
100101
1100
100101
D10.2
010
01010
010101
0101
010101
0101
D10.3
011
01010
010101
1100
010101
0011
Dll. 2
010
01011
110100
0101
110100
0101
D11. 3
011
01011
110100
1100
110100
0011
D12.2
010
01100
001101
0101
001101
0101
D12.3
011
01100
001101
1100
001101
0011
D13.2
010
01101
101100
0101
101100
0101
D13 .3
011
01101
101100
1100
101100
0011
D14.2
010
01110
011100
0101
011100
0101
D14.3
011
01110
011100
1100
011100
0011
D15.2
010
01111
010111
0101
101000
0101
D1S.3
011
01111
010111
0011
101000
1100
D16.2
010
10000
011011
0101
100100
0101
D16.3
011
10000
011011
0011
100100
1100
D17.2
010
10001
100011
0101
100011
0101
D17.3
011
10001
100011
1100
100011
0011
D18.2
010
10010
010011
0101
010011
0101
DIB.3
011
10010
010011
1100
010011
0011
D19.2
010
10011
110010
0101
110010
0101
D19.3
011
10011
110010
1100
110010
0011
D20.2
010
10100
001011
0101
001011
0101
D20.3
011
10100
001011
1100
001011
0011
D21.2
010
10101
101010
0101
101010
0101
D21. 3
011
10101
101010
1100
101010
0011
D22.2
010
10110
011010
0101
011010
0101
D22.3
011
10110
011010
1100
011010
0011
D23.2
010
10111
111010
0101
000101
0101
D23.3
011
10111
111010
0011
000101
1100
D24.2
010
11000
110011
0101
001100
0101
D24.3
011
11000
110011
0011
001100
1100
D2S.2
010
11001
100110
0101
100110
0101
D25.3
011
11001
100110
1100
100110
0011
D26.2
010
11010
010110
0101
010110
0101
D26.3
011
11010
010110
1100
010110
0011
D27.2
010
11011
110110
0101
001001
0101
D27.3
011
11011
110110
0011
001001
1100
D28.2
010
11100
001110
0101
001110
0101
D2B.3
011
11100
001110
1100
001110
0011
.,.....''If'>
n,n
111"1
...L...LJ..U.L
11"1111f'1
...LV...L...L...LV
"'"".,
/'"I"""""
1"\1""
V...LV.L
T"V")f'I
V.LVUU.L
n' ,
111f'11
..,(\111{\
"""111
('11f'\(\"1
1100
......
V/..Y.L...
v~v
V.LU.L
')
J....I"',J.-J
.L.L.LV...L
.LU..i....L..1..V
VU..L...L
D30.2
010
11110
011110
0101
100001
0101
D30.3
011
11110
011110
0011
100001
1100
D31.2
010
11111
101011
0101
010100
0101
D31. 3
011
11111
101011
0011
010100
1100
4-22
CY7B923
CY7B933
Valid Data Characters (SCID = LOW)
Bits
Data
Byte
Name
HGF EDCBA
00.4
100
00000
01.4
100
02.4
100
CurrentRD-
(continued)
CurrentRD+
Bits
abcdei
fghj
abcdei
fghj
Data
Byte
Name
100111
0010
011000
1101
00.5
101
00000
00001
011101
0010
100010
1101
01.5
101
00010
101101
0010
010010
1101
02.5
101
1101
110001
0010
03.5
HGF EDCBA
CurrentRD-
CurrentRD+
abcdei
fghj
abcdei
fghj
100111
1010
011000
1010
00001
011101
1010
100010
1010
00010
101101
1010
010010
1010
101
00011
110001
1010
110001
1010
03.4
100
00011
110001
04.4
100
00100
110101
0010
001010
1101
04.5
101
00100
110101
1010
001010
1010
05.4
100
00101
101001
1101
101001
0010
05.5
101
00101
101001
1010
101001
1010
06.4
100
00110
011001
1101
011001
0010
06.5
101
00110
011001
1010
011001
1010
07.4
100
00111
111000
1101
000111
0010
07.5
101
00111
111000
1010
000111
1010
08.4
100
01000
111001
0010
000110
1101
08.5
101
01000
111001
1010
000110
1010
09.4
100
01001
100101
1101
100101
0010
09.5
101
01001
100101
1010
100101
1010
010.4
100
01010
010101
1101
010101
0010
010.5
101
01010
010101
1010
010101
1010
011.4
100
01011
110100
1101
110100
0010
011.5
101
01011
110100
1010
110100
1010
012.4
100
01100
001101
1101
001101
0010
012.5
101
01100
001101
1010
001101
1010
013 .4
100
01101
101100
1101
101100
0010
013.5
101
01101
101100
1010
101100
1010
014.4
100
01110
011100
1101
011100
0010
014.5
101
01110
011100
1010
011100
1010
015.4
100
01111
010111
0010
101000
1101
015.5
101
01111
010111
1010
101000
1010
016.4
100
10000
011011
0010
100100
1101
016.5
101
10000
011011
1010
100100
1010
100011
1010
100011
1010
100011
0010
017.5
101
10001
1101
010011
0010
018.5
101
10010
010011
1010
010011
1010
1101
110010
0010
019.5
101
10011
110010
1010
110010
1010
001011
1101
001011
0010
020.5
101
10100
001011
1010
001011
1010
10101
101010
1101
101010
0010
021.5
101
10101
101010
1010
101010
1010
100
10110
011010
1101
011010
0010
022.5
101
10110
011010
1010
011010
1010
023.4
100
10111
111010
0010
000101
1101
023.5
101
10111
111010
1010
000101
1010
024.4
100
11000
110011
0010
001100
1101
024.5
101
11000
110011
1010
001100
1010
025.4
100
11001
100110
1101
100110
0010
025.5
101
11001
100110
1010
100110
1010
026.4
100
11010
010110
1101
010110
0010
026.5
101
11010
010110
1010
010110
1010
027.4
100
11011
110110
0010
001001
1101
027.5
101
11011
110110
1010
001001
1010
028.4
100
11100
001110
1101
001110
0010
028.5
101
11100
001110
1010
001110
1010
029.4
100
11101
101110
0010
010001
1101
029.5
101
11101
101110
1010
010001
1010
030.4
100
11110
011110
0010
100001
1101
030.5
101
11110
011110
1010
100001
1010
11111
101011
1010
010100
1010
017.4
100
10001
100011
1101
018.4
100
019.4
100
10010
010011
10011
110010
020.4
100
10100
021.4
100
022.4
031.4
100
11111
101011
0010
010100
1101
031. 5
4-23
101
I
CY7B923
CY7B933
~~
"CYPRESS
Valid Data Characters (SC/D = LOW) (continued)
Data
Byte
Name
HGF EDCBA
DO.6
110
00000
Dl. 6
110
D2.6
110
D3.6
110
D4.6
110
DS.6
D6.6
fgbj
Data
Byte
Name
HGF EDCBA
011000
0110
DO.7
111
00000
0110
100010
0110
Dl. 7
111
00001
0110
010010
0110
D2.7
111
00010
110001
0110
110001
0110
D3.7
111
00011
110101
0110
001010
0110
D4.7
111
00100
101001
0110
101001
0110
DS.7
111
011001
0110
011001
0110
D6.7
111
00111
111000
0110
000111
0110
D7.7
110
01000
111001
0110
000110
0110
D9.6
110
01001
100101
0110
100101
0110
D10.6
110
01010
010101
0110
010101
D11.6
110
01011
110100
0110
D12.6
110
01100
001101
D13.6
110
01101
101100
D14.6
110
01110
011100
D1S.6
110
01111
010111
D16.6
110
10000
D17.6
110
D1S.6
CurrentRD-
CurrentRD+
abcdei
fghj
abcdei
100111
0110
00001
011101
00010
101101
00011
00100
110
00101
110
00110
D7.6
110
DS.6
Bits
CurrentRD-
CurrentRD+
abcdei
fghj
abcdei
fghj
100111
0001
011000
1110
011101
0001
100010
1110
101101
0001
010010
1110
110001
1110
110001
0001
110101
0001
001010
1110
00101
101001
1110
101001
0001
00110
011001
1110
011001
0001
111
00111
111000
1110
000111
0001
DS.7
111
01000
111001
0001
000110
1110
D9.7
111
01001
100101
1110
100101
0001
0110
D10.7
111
01010
010101
1110
010101
0001
110100
0110
D11. 7
111
01011
110100
1110
110100
1000
0110
001101
0110
D12.7
111
01100
001101
1110
001101
0001
0110
101100
0110
D13.7
111
01101
101100
1110
101100
1000
0110
011100
0110
D14.7
111
01110
011100
1110
011100
1000
0110
101000
0110
D1S.7
111
01111
010111
0001
101000
1110
011011
0110
100100
0110
D16.7
111
10000
011011
0001
100100
1110
10001
100011
0110
100011
0110
D17.7
111
10001
100011
0111
100011
0001
110
10010
010011
0110
010011
0110
D1S.7
111
10010
010011
0111
010011
0001
D19.6
110
10011
110010
0110
110010
0110
D19.7
111
10011
110010
1110
110010
0001
D20.6
110
10100
001011
0110
001011
0110
D20.7
111
10100
001011
0111
001011
0001
D21.6
110
10101
101010
0110
101010
0110
D21. 7
111
10101
101010
1110
101010
0001
D22.6
110
10110
011010
0110
011010
0110
D22.7
111
10110
011010
1110
011010
0001
D23.6
110
10111
111010
0110
000101
0110
D23.7
111
10111
111010
0001
000101
1110
D24.6
110
11000
110011
0110
001100
0110
D24.7
111
11000
110011
0001
001100
1110
D2S.6
110
11001
100110
0110
100110
0110
D2S.7
111
11001
100110
1110
100110
0001
D26.6
110
11010
010110
0110
010110
0110
D26.7
111
11010
010110
1110
010110
0001
D27.6
110
11011
110110
0110
001001
0110
D27.7
111
11011
110110
0001
001001
1110
D2S.6
110
11100
001110
0110
001110
0110
D2S.7
111
11100
001110
1110
001110
0001
D29.0
110
11101
101110
0110
010001
0110
D29.7
111
11101
101110
0001
010001
1110
D30.6
110
11110
011110
0110
100001
0110
D30.7
111
11110
011110
0001
100001
1110
D31. 6
110
11111
101011
0110
010100
0110
D31. 7
111
11111
101011
0001
010100
1110
4-24
Bits
CY7B923
CY7B933
'i~
~;CYPRESS
Valid Special Character Codes and Sequences (SC/D =
HIGH)[23,24]
Bits
CurrentRD-
CurrentRD+
HGF
EDCBA
abcdei
fgbj
abcdei
fgbj
K28.0
CO.O
(COO)
000
00000
001111
0100
110000
1011
K28.1
CLO
(Cal)
000
00001
001111
1001
110000
0110
K28.2
C2.0
(C02 )
000
00010
001111
0101
110000
1010
K28.3
C3.0
(C03 )
000
00011
001111
0011
110000
1100
K28.4
C4.0
(C04)
000
00100
001111
0010
110000
1101
K28.5
C5.0
(C05)
000
00101
001111
1010
110000
0101
K28.6
C6.0
(C06)
000
00110
001111
0110
110000
1001
K28.7
C7.0
(C07 )
000
00111
001111
1000
110000
0111
K23.7
C8.0
(C08)
000
01000
111010
1000
000101
0111
K27.7
C9.0
(C09)
000
01001
110110
1000
001001
0111
K29.7
C10.0
(COA)
000
01010
101110
1000
010001
0111
K30.7
C11. a
(COB)
000
01011
011110
1000
100001
0111
S.c. Byte Name
S.C. Code Name
Idle
CO.1
(C20)
001
00000
R_ROY
CL1
(C21)
001
00001
-K28. 5+,021.4,021.5,021.5, repead25 ]
-K28. 5+,021.4,010.2,010.2, repead26]
EOFxx
C2.1
(C22)
001
00010
-K28. 5, On.xxxO[27]
+K28. 5, On.xxx1[27]
Follows K28.1 for ESCON Connect-SOF (Rx indication only)
C-SOF
C7.1
(C27)
001
00111
001111
1000
110000
0111
110000
0111
Follows K28.5 for ESCON Passive-SOF (Rx indication only)
P-SOF
C7.2
(C47)
010
00111
Exception
CO.7
(CEO)
111
00000
-K28.5
CL 7
(CE1)
111
00001
+K28.5
C2.7
(CE2)
111
00010
Exception
C4.7
(CE4)
111
00100
Notes:
23. All codes not shown are reserved.
24. Notation for Special Character Byte Name is consistent with Fibre
Channel and ESCON naming conventions. Special Character Code
Name is intended to describe binary information present on I/O pins.
Common usage for the name can either be in the form used for describing Oata patterns (i.e., CO.O through C31.7), or in hex notation
(i.e., Cnn where nn=the specified value between 00 and FF).
25. CO.I = Transmit Negative K28.5 (-K28.5+) disregarding Current
RD when input is held for only one byte time. Ifheld longer, transmit-
4-25
001111
1000
Code Rule Violation and SVS Tx Pattern
0111[28]
1000[28]
011000
100111
1010[29]
1010[29]
001111
001111
110000
0101[30]
Running Disparity Violation Pattern
0101[31]
110111
001000
1010[31]
110000
0101[30]
ter begins sending the repeating transmit sequence - K28.5 +,021.4,
021.5,021.5, (repeat all four bytes) ... defined in X3.230 as the primitive signal "Idle word." This Special Character input must be held for
four (4) byte times or multiples of four bytes or it will be truncated by
the new data.
The receiver will never output this Special Character, since K28.5 is
decoded as C5.0, Cl. 7, or C2. 7, and the subsequent bytes are decoded
as data.
II
#
CY7B923
CY7B933
?cYPRESS
Notes (continued):
26. CLl = Transmit Negative K28.5 (-K28.5 +) disregarding Current
RO when input is held for only one byte time. If held longer, transmitter begins sending the repeating transmit sequence - K28.5 +, 021.4,
010.2, 010.2,(repeat all four bytes) ... defined in X3.230 as the primitive signal "Receiver_Ready (R_ROY)." This Special Character input
must be held for four (4) byte times or mUltiples of four bytes or it will
be truncated by the new data.
The receiver will never output this Special Character, since K28.5 is
decoded as CS.O, C1.7, or C2.7 and the subsequent bytes are decoded
as data.
27. C2.1 = 'Iransmit either - K28.5 + or + K28.5 - as determined by Current RO and modify the Transmission Character that follows, by setting its least significant bit to 1 or O. If Current RO at the start of the
following character is plus ( + ) the LSB is set to 0, and if Current RO
is minus ( - ) the LSB becomes 1. This modification allows construction of X3.230 "EOF" frame delimiters wherein the second data byte
is determined by the Current RO.
For example, to send "EOFdt" the controller could issue the sequence
C2.1-021.4- 021.4-021.4, and the HOTlink 'Iransmitter will
send either K28.S-021.4-021.4-021.4 or K28.5-021.S021.4- 021.4 based on Current RO. Likewise to send "EOFdti" the
controller could issue the sequence C2.1-01004-021.4-021.4, and
the HOTLink 'Iransmitter will send either K28.5-01Oo4-02104021.4 or K28.S - 01O.S - 021.4- 021.4 based on Current RD.
The receiver will never output this Special Character, since K28.5 is
decoded as CS.O, C1.7, orC2.7, and the subsequent bytes are decoded
as data.
28. CO.7 = Transmit a deliberate code rule violation. The code chosen for
this function follows the normal Running ~isparity mies. 'Iransmission of this Special Character has the same effect as asserting SVS =
HIGH.
The receiver will only output this Special Character if the 'Iransmission Character being decoded is not found in the tables.
29. C1.7 = Transmit Negative K28.5 (-K28.5+) disregarding Current
RD.
The receiver will only output this Special Character if K28.5 is received with the wrong running disparity. The receiver will output C1.7
if - K28.5 is received with RD +, otherwise K28.5 is decoded as CS.O
or C2.7.
30. C2.7 = 'Iransmit Positive K28.5 (+ K28.5 -) disregarding Current
RD.
The receiver will only output this Special Character if K28.5 is received with the wrong running disparity. The receiver will output C2.7
if +K28.5 is received with RO-, otherwise K28.5 is decoded as CS.O
or C1.7.
31. C4.7 = 'Iransmit a deliberate code rule violation to indicate a Running
~isparity violation.
The receiver will only output this Special Character if the 'Iransmission Character being decoded is found in the tables, but Running Disparity does not match. This might indicate that an error occurred in a
prior byte.
Ordering Information
Package
Name
Package 1YPe
J64
S21
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) SOIC
Commercial
CY7B923-JI
J64
28-Lead Plastic Leaded Chip Carrier
Industrial
CY7B923- LMB
L64
28-Square Leadless Chip Carrier
Military
Ordering Code
CY7B923-JC
CY7B923 SC
Ordering Code
CY7B933-JC
CY7B933-SC
Operating
Range
Operating
Range
Package
Name
Package 1Ype
J64
S21
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) SOIC
Commercial
CY7B933-JI
J64
28-Lead Plastic Leaded Chip Carrier
Industrial
CY7B933-LMB
L64
28-Square Leadless Chip Carrier
Military
4-26
-
-'f
CY7B923
CY7B933
~
; CYPRESS = = = = = = = = = = = = = = = =
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Switching Characteristics
Subgroup
Parameter
VOHT
1,2,3
VOLT
1,2,3
tB
VOHE
1,2
tCPWH
VOLE
1,2,3
VODIF
1,2,3
lOST
1,2,3
VIHT
1,2,3
VILT
1,2,3
tpDR
VIHE
1,2,3
tpPWH
VILE
1,2,3
tpDF
IIHT
1,2,3
lILT
1,2,3
IIHE
1,2,3
tCPRH
IILE
1,2,3
tCPRL
Icc
1,2,3
tRH
VDIFF
1,2,3
tpRF
VIHH
1,2,3
VILL
1,2,3
tCKW
tCPWL
tSD
tHD
tSENP
tHENP
tRISE
tFALL
tCKR
tpRH
tA
tROH
tCKX
tCPXH
tCPXL
tDS
Document #: 38-00189-F
4-27
Subgroup
9, 10, 11
9,10,11
9,10,11
9,10,11
9,10,11
9, 10, 11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9, la, 11
9,10,11
CYIOIE383
ECL{fTLIECL Translator
and High-Speed Bus Driver
Features
Functional Description
• BiCMOS for optimum speed/power
• High speed (max.)
-2.5 ns tpD TTL-to-ECL
-3 ns tpD ECL-to-TTL
• Low skew < ± Ins
• Can operate on single +5V supply
• Full-duplex ECl/fTL data
transmission
• Internal 2 kg ECL pull-down
resistors on each ECL output
• SO-pin PQFP package
• Surface-mouut PLCC/CLCC package
• VBB EeL reference voltage output
• Single- or dual-supply operation
• Capable of greater than 200lV ESD
• ECL cable/twisted pair driver
The CYlOIE383 is a new-generation
TTL-to-ECL and ECL-to-TTL logic level
translator designed for high-performance
systems. The device contains ten independent TTL-to-ECL and ten independent
ECL-to-TTL translators for high-speed
full-duplex data transmission, mixed logic,
and bus applications. The CYlO1E383 is
especially suited to drive ECL backplanes
between TTL boards. The CYlOlE383 is
implemented with differential ECL I/O to
provide balanced low noise operation over
controlled impedance buses between TTL
and/or ECLsubsystems. In addition, the
device has internal output 2 kg pull-down
resistors tied to VEE to decrease the number of external components. For system
testing purposes or for driving light loads,
the 2 kg is used as the only termination
Logic Block Diagram
Pin Configurations
PLCC/CLCC
ThpView
VBB
o0
DIFFERENTIAL
ECLINPUTS
ECl SUPPLY
00
00
0
01
01
1
[jf
g"22
02
03
o3
D4
o4
05
03
04
ITlOUTPUTS
ITlSUPPlY
05
05
06
D6
07
lJ7
08
116
09
09
06
07
08
09
010
010
010
011
011
Q11
012
~
013
00
013
~
014
015 DIFFERENTIAL
016 EClOUTPUTS
016 EClSUPPlY
017
TTL INPUTS D15
ITlSUPPlY
thereby eliminating up to 20 external resistors. The part meets standard lOOK logic
levels with the internal pull-down while
driving SOg to - 2V.
The device is designed with ample ground
pins to reduce bounce, and has separate
ECL and TTL power/ground pins to reduce noise coupling between logic families. The parts can operate in single- or dual-supplyconfigurationswhilemaintaining
absolute and lOOK level swings. The translators are offered in a standard lOOK
ECL-compatible version with -S.2V or
-4.5V power supply. The TTL I/O is fully
TTL compatible. The CYI01E383 is
packaged in 84-pin surface-mountable
PLCCs and CLCCs. To save board space,
an SO-pin PQFP package with 25-mil-lead
pitch is available.
mo
016
017
0T7
018
018
016
019
019
ECl05
EClDS
EClD6
EClDS
ECl07
ECl lJ7
EClD6
ECl 116
ECl09
ECl 116
EClVBB
EClVCC
ECl010
ECl010
EClVCC
ECl011
ECl011
EClVCC
ECl012
EClO12
EClVCC
101E383
TTLGNO
ITl04
ITlVCC
TTL 03
ITlGNO
ITl02
ITlVCC
ITl01
ITlGNO
ITlOO
ITlGNO
TTL 019
ITl018
ITl017
ITl016
ITl015
TTL 014
ITl013
TILD12
ITl011
ITl010
me
~i ~i~i-i
<>
§z
~
'"
Z
'~"
<>
<>
>
....
<>
UJ
UJ
UJ
E383·1
E383·2
>
c3
UJ
Note 1
Note:
1. The PQFP package has one less each TTL Vee and TIL GND pin and two less EeL Vee pins.
4-28
CYIOIE383
Pin Configurations (continued)
PQFP
ThpView
TTlQ.
EClD5
EClD5
EClD6
ECl !l6
ECLD7
TTL VCC
TTlQ3
TTL GND
TTlQ2
TTL vee
ECl Il7
EClD8
ECl08
EClD9
ECl08
TTlQ1
TTL GND
TTL 00
101E383
TTL GND
TTL D19
TTL D18
TTL D17
ECl VBB
EClVCC
EClQ10
ECLc:rfO
TTL
TTL
TTL
TTL
EClVCC
ECl Q11
EClOIT
EClQ12
EClQf2
I
D16
D15
D1.
D13
TTL D12
TTlD11
TTL D10
EClVCC
E383-3
Selection Guide
lOlE383-2
2.5
3
270
Maximum Propagation Delay Time (ns) (TTL to ECL)
Maximum Propagation Delay Time (ns) (ECL to TTL)
Maximum Operating Current (rnA) Sum of lEE and Icc
lOlE383-3
3
4
270
Maximum Ratings
(Above which the useful life may be impaired. Foruser guidelines,
not tested.)
Operating Range
Storage Temperature .................. -65°Cto +150°C
Ambient Temperature with
Power Applied ....................... -55°C to +125°C
TTL Supply Voltage to Ground Potential ... -O.5V to + 7.0V
TTLDClnputVoltage .................. -3.0Vto +7.0V
ECL Supply Voltage VEE to ECL Vee ..... -7.0V to +0.5V
ECL Input Voltage ........................ VEE to +0.5V
ECL Output Current. . . . . . . . . . . . . . . . . . . . . . . . .. -50 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
4-29
Range
Commercial
Ambient
Version Temperature
lOOK lOlE
O°Cto
+85°C
I/O
EeL
TTL
VEE
-4.2Vto
-5.46V
Vee
5V±
5%
~
CYIOIE383
=- rcYPRESS
EeL Electrical Characteristics Over the Operating Rangd 2]
Parameter
VOH
Description
Output HIGH Voltage
VIH
Input HIGH Voltage
Test Conditions
lOlE, RL = 50Q to -2V
VIN = VIH Min. or VIL Max.
10lE, RL = 50Q to -2V
VIN = VIH Min. or VIL Max.
lOlE
VOL
Output LOW Voltage
VIL
Input LOW Voltage
lOlE
VBB
Output Reference
Voltage
10lEl4 J
VCM PJ
VDIFF
Common Mode Voltage
Input Voltage
Differential
Input HIGH Current
Input LOW Current
Pull-Down Resistor
±VeMwith respect to VBB
Required for Full Output Swing
IIH
IlL
RpD
Temperature[3]
lOlE383
Max.
-880
TA
= O°C to 85°C
Min.
-1025
TA
= O°C to 85°C
-1810
TA
TA
= O°C to 85°C
= O°C to 85°C
TA = O°C to 85°C
-1.40
VIN = VIH Max.
VIN = VIL Min.
Connected from All ECLOutputs TA
to VEE
-1620
mV
-1165
-880
mV
-1810
-1475
mV
-1.23
V
1.0
V
mV
220
170
2.6
fAA
fAA
kQ
-180
rnA
150
= O°C to 85°C
-0.5
1.6
Supply Current (All inputs
and outputs open)
lEE
Unit
mV
TTL Electrical Characteristics Over the Operating Rangd2]
lOlE383
Parameter
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Test Conditions
Min.
= Min., 10H = -3.2mA
Vee = Max., 10L = 16.0 rnA
VIH
Input HIGH Voltagd 6]
VIL
Input LOW Voltagd5]
VeD
Input Clamp Diode Voltage
IOS[7]
Output Short-Circuit Current
Ilx
Icc
Max.
Unit
2.4
Vee
V
0.5
V
2.0
V
0.8
V
rnA
= -10 rnA
V ce = Max., VOUT = 0.5V[8]
-180
-40
Input Load Current[9]
GND~VI~Vec
-250
+20
fAA
Vec Operating Supply Current
Vee
90
rnA
-1.5
lIN
= Max., lOUT = 0 rnA, f = f max.
V
Capacitance[7]
Max.
Unit
C IN l7J
Parameter
Input Capacitance
Description
4
pF
COUTl7J
Output Capacitance
5
pF
TTL AC Test Load and WaveformLiOj
R1 238Q (319Q MIL)
5V
OUTPUTo---....--+
CLPF
INCLUDING
JIG AND
SCOPE
Equivalent to:
r-=
11::
R2170Q
(236QMIL)
....
<3n5
E383·5
E383-4
THEvENIN EQUIVALENT (Commercial)
99Q
OUTPUTo.o--_y\l\o>,_ _-oO
THEVENIN EQUIVALENT (Military)
136Q
OUTPUTo.o--_y\l\o>,_--oO
2.08V
4-30
2.13Vthm
~
CYIOIE383
~'CYPRESS
ECL AC Test Load and Waveform[1l, 12, 13, 14,15J
GND
ALL INPUT PULSES
V1H
Vee,Veeo
INPUT
DoUT
VEE
RL
0.01 ~FJ.
r
20%
V1L
CL
1f
11-
20%
I,
If
-2.0V
VEE
E3B3·6
E383-7
ECL-to-TTL Switching Characteristics Over the Operating Range
lOlE383-2
Parameter
Description
lOlE383-3
Test Conditions
Min.
Max.
Min.
Max.
Unit
tpLH
Propagation Delay Time
Dn, Dn to Q n
1
3
1
4
ns
tpHL
Propagation Delay Time
Dn, Dn toQn
1
3
1
4
ns
TTL-to-ECL Switching Characteristics Over the Operating Range
lOlE383-2
Parameter
Description
Test Conditions
Min.
Max.
lOlE383-3
Min.
Max.
Unit
ns
tpLH
Propagation Delay Time
Dn to Qn, Q n
1
2.5
1
3
tpHL
Propagation Delay Time
Dn to Qn, Q n
1
2.5
1
3
ns
tR[7J
Output Rise Time
20% to 80%
0.35
1.7
0.35
1.7
ns
tR[7J
Output Fall Time
20% to 80%
0.35
1.7
0.35
1.7
ns
Skew Time Switching Characteristics[7J (Same test conditions as TTL-to-ECL and ECL-to-TTL Electrical Characteristics)
Symbol
Characteristic
Test Conditions
Min.
Max.
Unit
tSKT[7J
Data Skew Time ECL-to-TTL
TTLQ n to TTLQn+ m
1
ns
tSKE[7J
Data Skew Time TTL-to-ECL
ECLQn, Q n to ECLQn+m, Qn+m
1
ns
Notes:
2. See AC Test Load and Waveform for test conditions.
3. Commercial grade is specified as ambient temperature with transverse
air flow greater than 500 linear feet per minute.
4. Max. IBB = -1 rnA.
S. The internal gain of the CY101E383 guarantees that the output voltage will not change for common mode signals to ± 1Y. Therefore, input
CMRR is infinite within the common mode range.
6. These are absolute values with respect to device ground.
7. Characterized initially and after any design or process changes that
may affect these parameters.
8. Not more than one output should be tested at a time. Duration of the
short should not be more than one second.
I/O pin leakage is the worst case of Ilx (where X = H or L).
10. TIL test conditions assume signal transition times of3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOlJIOH, and CL = 10 pF.
11. VIL = -1.7V, VIH= -0.9Y.
12. ECL RL = SOg, CL < S pF (includes fixture and stray capacitance).
13. All coaxial cables should be son with equal lengths. The delay of the
coaxial cables should be "nulled" out of the measurement.
14. t, = tf= 0.7ns
IS. All timing measurements are made from the SO% point of all waveforms.
9.
4-31
I
CYIOIE383
Switching Waveforms
ECL·to.TTL Timing
--f~ ---.I~I,..---__~_5_0%
PHL
_t
tpLH
______________¥1.5V
=-1
~
E383-B
TTL·to·ECL Timing
~'~j""'50_%
1._5V_~~_tP_"'1""'50_%
____
_ _ _ _ __
E383·9
Skew Test (tSKT)
TTLQn·to.TTLQn+m
-E'.,~~ ...---_1=_1.5V=:1
tSKT
~
____________ J1.5V
E383-10
________* --=-t
50%
Qn+m(ECL)
Qn+m(ECL)
_ _ _ _ _-1rf-_tS_KE
t:=tSKE~
*50%
50%
4-32
r-
tSKE
W,,---50%_ _
~tSKE-t
E383·11
CYIOIE383
ECL-to-TTL 'fruth Table
Table 1. CY101E383 Nominal Voltages Applied in lOOK System
Inputs
Outputs
ECLDn
ECLDn
TTLQn
Open[16]
Open[16]
L
L
H
H
L
L
H
Supply Pin
Single-Supply
System
Dual-Supply
System
TTL Vee
+S.OV
+S.OV
TTLGND
O.OV
O.OV
ECLVee
+S.OV
O.OV
ECL VEE
O.OV
-4.SV
TTL-to-ECL 'fruth Table
Inputs
Table 2. CY101E383 Nominal Voltages Applied in 101K System
Outputs
TTLDn
ECLQn
ECLQn
L
L
H
H
H
L
Supply Pin
Single-Supply
System
Dual-Supply
System
TTL Vee
+S.OV
+5.0V
TTLGND
O.OV
O.OV
Nominal Voltages
ECLVee
+5.0V
O.OV
The CY101E383 can be used in dual ±5V or single +5V supply
systems. The supply pins should be connected as shown in Tables 1
and 2. This connection technique involves shifting up all ECL supply pins by 5Y. When operating in single-supply systems, the ECL
termination voltage level must also be shifted up by adding 5Y. For
example, if the termination is SO ohms to - 2V in a dual-supply system, the single + SV system should have SO ohms to + 3Y. If the termination is a thevenin type, then the resistor tied to ground is now
at + SV and the resistor tied to - SV is now at ground potential.
Consideration should be given to the power supply so that adequate bypassing is made to isolate the ECL output switching noise
from the supply. Having separate TTL and ECL + SV supply lines
will help to reduce the noise.
ECL VEE
O.OV
-5.2V
Ordering Information
Speed
(ns)
2.S
3
Ordering Code
Package
Name
Package lYpe
Operating
Range
Commercial
CYlOIE383-2JC
J83
84-Lead Plastic Leaded Cbip Carrier
CYIOIE383-2NC
N80
80-Lead Plastic Quad Fiatpack
CYlOIE383-3JC
J83
84-Lead Plastic Leaded Chip Carrier
CYIOIE383 - 3NC
N80
80-Lead Plastic Quad Fiatpack
Note:
16. The EeL inputs will pull to a known logic level if left open.
Document#: 38-A-00023-F
4-33
Commercial
PRELIMINARY
CY9266-T
CY9266-C
CY9266-F
HOTLink ™ Evaluation Board
Features
• 160 to 330 Mbps point-to-point serial
data link
• Parallel-to-serial and serial-toparallel I/O
• 10-bit-wide 8B/10B encode, decode or
unencoded
• Full system diagnostics with Built-InSelf-Test (BIST)
• Compliant with ESCON®, Fiber
Channel and ATM standards
• Compatible with Fiber Channel FC-O
specification (CY9266-C/T):
-25-TV-EL-S
-25-MI-EL-S
-25-TP-EL-S
• Compatible with Fiber Channel FC-O
specification (CY9266-F):
-25-M6-LE-I
• Development tool for proprietary
networks
• 1\vo-digit error display for BER
analysis
• Multiple host interface:
- 48-pin connector (IBM
OLC-266 m compatible)
- 60-pin edge connector
- 6O-pin two-row right-angle
connector
• Easy to use for applications
development
48-PIN
OLC-266
CONNECTOR
60-PIN EDGE
CONNECTOR
SYSTEM TEST
AND I/O
STATE MACHINE
DIAGNOSTIC DISPLAY
Figure 1. Copper Media Interface Evaluation Board CY9266-C
9266-1
48-PIN
OLC-266
CONNECTOR
60-PIN EDGE
CONNECTOR
SYSTEM TEST
AND 1/0
STATE MACHINE
DIAGNOSTIC DISPLAY
Figure 2. Fiber-Optic Interface Evaluation Board CY9266- F
9266-2
48-PIN
OLC-266
CONNECTOR
60-PIN EDGE
CONNECTOR
SYSTEM TEST
AND I/O
STATE MACHINE
Figure 3. 1Wisted-Pair Interface Evaluation Board CY9266-T
4-34
9266-3
PRELIMINARY
CY9266-T
CY9266-C
CY9266-F
Functional Description
Typical Applications for the Evaluation Board include:
The HOTLink'~ Evaluation Board (CY9266) is a system development tool that facilitates the design and evaluation of the Cypress
HOTLink transmitter (CY7B923) and receiver (CY7B933) devices. The CY9266 Evaluation Board is offered with three serial
media interface options: CY9266-C (copper), CY9266-F (fiber), and CY9266-T (twisted pair). The CY9266-C offers a low
cost 1/4" coaxial connection, the CY9266- F interfaces with a
longwave (1300 nm) LED optical transceiver and SC fibcroptics
connector, and the CY9266-T is configured to support shielded
twisted pair or twin axial cable that attaches through a 9-pin D-sub
connector.
The CY9266 accepts data and control commands from the host via
the parallel interface ports (available in three connectors). The
48-pin header connector allows interoperability with the IBM
OLC-266 interface. The two 60-pin connectors are functionally
equivalent. The vertical pin connector is used for probing and
monitoring the appropriate signals, while the edge connector can
be connected to a flat ribbon cable as a direct host communication
interface.
In a typical point-to-point link, the host downloads parallel data to
the CY9266 Evaluation Board. Parallel data can be formatted as
pre-encoded lO-bit patterns or 8-bit data/special characters to be
encoded by the HOTLink transmitter. The data is then encoded
(optionally) and serialized by CY7B923 HOTLink Transmitter.
Serial data is then transmitted via coax, twisted pair, or fiber.
In the receive operation, serial data is sent from a remote source
(via copper/fiber/twisted pair) and transferred to the CY7B933
HOTLink receiver. The serialized data is converted to parallel and
then optionally decoded. Parallel data is transferred to the host
system along with various status and synchronizing signals. Alll/O
operations are performed between the host and the Evaluation
Board using simple handshakes.
The CY9266 Evaluation Board can also operate in self-diagnostic
mode and indicate errors in the serial transmission stream using a
built-in two-digit, seven-segment LED display.
•
•
•
•
•
•
•
•
•
HOTLink system development
Telecommunication
Remote data acquisition
Processor-to-disk/peripheral communication
Backplane extender
Point-to-point video/image communications
Point-to-point CPU/server communications
High-speed data switching (TI Multiplier, etc.)
Similar in function to IBM OLC-266 (single channel) and
HP HOLC-0266'~
Specification
Board Dimensions
Two media types:
CY9266-C
3.0" x 4.0" (approx., plus media connector)
Coax connectors-BNC for transmit,
TNC for receive
Fiber optic module, single row or 4 row
CY9266-F
modules
Twisted pair connector, 9-pin D-sub
CY9266-T
Power Supply
+5V ± 5%
Maximum Clock Rate 33 MHz
Maximum Data Rate 330 Mbps
TTL
Parallell/O
Coax or twisted pair (CY9266-C/T) or
Serial I/O
Fiber optic with SC connector
(CY9266-F)
Ordering Information
Ordering Code
CY9266-C
CY9266-F
Fiber
CY9266-T
Twisted Pair
CY9266-FX
Fiber w/o optic
module
Document #: 38-00236-A
HOTLink is a trademark of Cypress Semiconductor Corporation.
ESCON is a registered trademark of International Business Machines.
IBM OLC- 266 is a trademark of International Business Machines Corporation.
HP HOLC-0266 is a trademark of Hewlett-Packard Corporation.
4-35
Media 'IYpe
Copper
II
Frequently Asked Questions about HOTLink ™
The following questions are frequently asked by customers who are evaluating HOTLink products. These
cursory answers will serve as an introduction for each topic. Separate application notes cover these topics in
more complete detail.
OM
1. How far can HOTLink communicate over various media?
HOTLink has no intrinsic distance limit. The two issues that determine the distances over which data can
be sent using HOTLink are: (1) the choice of interconnect media (fiber-optic cable, coaxial cable, twistedpair cable, etc.); and (2) the jitter that accumulates or is injected while the data is in transit over the
selected media.
HOTLink can drive all standard fiber-optic interface modules that support standard PECL interface signals. These electro-optical modules are suitable for communicating over distances from a few meters to several kilometers. Fiber-optic interconnect offers the longest distances and the lowest interference potential of all transmission media.
For lower-cost applications, HOTLink can directly drive wire transmission lines. The main distance determining factors when using wire links are related to the characteristics of the cable. Wire transmission
lines have significant frequency-dependent attenuation that causes jitter as a direct function of the data
rate and the media length. Uncompensated transmission line lengths are limited much more by jitter (and
the jitter tolerance of the receiver) than by actual signal attenuation. The detrimental effect of jitter can
be lessened with the addition of a suitable attenuation compensation filter that matches the attenuation
characteristics of the cable. This filter trades receiver differential voltage amplitude for jitter reduction
and increases the possible transmission distance. When using wire transmission lines, other issues beyond
transmission distance often determine transmission line suitability. These issues include both radiated
emissions and susceptibility to external disturbance that must be examined prior to selection of a link media type.
Some typical wire types and uncompensated transmission distances over which HOTLink can communicate
are shown in Table 1. A simple compensation filter, built from passive components, can increase reliable
transmission distance to more than twice these distances.
For inore infof1l1ation See the application note "HOTLink Copper Interconnect-r,,1aximum Length vs.
Frequency."
Table 1. Coaxial Cable lYpes
Coaxial
Cable
SOQ
7SQ
RG-6 NU - 900 ft
266 Mbaud
RG-58 NU - 350 ft
RG-58 NU - 225 ft
RG-6 NU - 600 ft
RG-59 NU - 525 ft RG-62 NU - 675 ft
RG-59 NU - 350 ft RG-62NU - 400 ft
330 Mbaud
RG-58 NU - 115 ft
RG-6 NU - 500 ft
RG-59 NU - 250 ft RG-62 NU - 325 ft
160 Mbaud
7SQ
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Frequently Asked Questions about HOTLink
'CYPRESS
Table 2. 1Wisted Pair Cable 1Ypes
Shielded 1\visted Pair
150Q
Unshielded 1\visted Pair
UTP3
UTP5
160 Mbaud
IBM® - Type 1 - 550 ft
160 Mbaud
140 ft
280 ft
266 Mbaud
IBM - Type 1 - 350 ft
266 Mbaud
80 ft
180 ft
330 Mbaud
IBM - Type 1 - 275 ft
330 Mbaud
60 ft
130 ft
2. Can the PECL inputs and outputs of HOTLink products be connected to ECL (-5.2V) products?
The +5.0V PECL inputs and outputs are directly compatible with true ECL (10K, lOKH, lOOK, etc.) running on + 5V power supplies. Connections between the HOTLink PECL I/O and ECL running on - 5.2V
is easily accomplished by capacitor-coupling the serial data lines. Details on this coupling technique are
included in the Cypress application note "HOTLink Design Considerations."
3. What happens when the ECL inputs of the HOTLink Receiver are left open?
All of the ECL inputs on the HOTLink Receiver have internal pull-down resistors to assure that ECLemitter follower outputs will see a positive input current (approximately 250 ~A into the pin) at all normal
ECL voltages. Thus, all single-ended ECL inputs (i.e., A/B, SI, INB) will float to a logical LOW level.
(These pull-downs will not sink enough current to act as the normal ECL output termination. They are
only intended to prevent the emitter-follower oscillations caused by negative input-impedance that are
possible in some less robust designs.) Open inputs will be interpreted as follows: NB = LOW will cause
the Receiver to accept data from the INB serial inputs; SI = LOW will cause the SO output to assume
a LOW output state; INB = LOW will be interpreted as an input with no data (assuming NB is also
LOW). No data is interpreted as an error (RVS=HIGH & CO.7 in Encoded mode, and Qa-j outputs
LOW in Bypass mode) and will cause the internal clock-synchronizer phase-locked loop (PLL) to track
the REFCLK input frequency.
The internal resistor network used to pull the differential serial data inputs (i.e., INA± and INB±) will
cause unconnected inputs to rest at approximately 2.0V. This resting voltage is a byproduct of the internal
resistive attenuator used to enhance input-common mode range. If both inputs of a differential pair are
left unconnected, the inputs will be in an undefined state and HOTLink receiver behavior will be unpredictable. Stray, non-differential noise that appears on these unconnected inputs will be amplified and interpreted as serial data. This will cause random parallel-data output changes, and may cause the PLL to
wander or drift away from the REFCLK frequency. One input of an intentionally unused differential-pair
should be terminated to Vee through a 1-5 KQ resistor to assure that no data transitions are accidentally
created.
4. What special power-supply bypassing is required for HOTLink products?
HOTLink requires no special considerations for power-supply bypassing beyond that normally associated
with high speed logic. This typically includes the use of a ground plane, a split Vee plane, and multiple
chip bypassing using RF quality capacitors. Each of the ground pins of a HOTLink IC should connect
directly to the ground plane using short ( < .25") traces and vias. All of the Vee pins should connect to a
Vee pad under the HOTLink and then connect to the board Vee through a single via. Connect one 22-nF
capacitor for each Vee pin directly from the pin to GND. For more information see the "Using Decoupling
Capacitors" application note.
4-37
•
•
Frequently Asked Questions about HOTLink
5. If the HOTLink Receiver is switched from INA to IND, how long will it take for the PLL to re-Iock?
Assuming that the data on both INA and INB are within the ±O.1 % frequency offset described in the
HOTLink datasheet, the phase-locked loop (PLL) will acquire and lock to the new data stream within a
few byte times. The exact time required involves statistical probabilities related to phase, frequency, and
jitter, and cannot be exactly predicted. Empirical testing using normal data patterns shows that the time
required to achieve absolute minimum phase error with the new data stream will vary from zero to about
ten bytes.
An operational serial link will produce valid parallel data much earlier than the amount of time required
to achieve minimum phase error, since instantaneous phase error is accommodated as jitter. The wide
jitter tolerance offered by the HOTLink Receiver will minimize the time that data is incorrectly interpreted during phase acquisition. The larger problem facing a system protocol that allows switching of serial data streams, is byte synchronization (byte-framing). After the data-stream has been switched, it must
be reframed. This requires that a K28.5 (or two K28.5s within five bytes if multibyte framing is enabled)
must be received. The time that elapses before this happens depends on the system protocol and the timing of the data input switch. Correct data might not come out of the HOTLink Receiver for hundreds of
byte times due to reframing regardless of speed of phase acquisition.
For more information, refer to the Receiver Data-Phase Acquisition Time section of the "HOTLink Jitter
Characteristics" application note.
6. If the connection between the HOTLink Transmitter and Receiver is briefly interrupted, how long will
it take for the PLL to re-Iock?
The exact behavior of the HOTLink Receiver depends on the length and cause of the interruption. If the
interruption is synchronous with the data (i.e., data bits disappear without any significant disturbance to
the placement of the final few data transitions), and lasts for less than a few dozen bytes, it is probable
that the PLL will relock on the very first bit. If the interruption is asynchronous (i.e., the timing of the
final few transitions is disturbed) or if the synchronous interruption lasts longer than a few dozen bytes,
the PLL will relock within the first one or two bytes after resumption of the data stream. If a long interruption occurs that is not synchronous to byte boundaries, the receiver may lose byte synchronization when
the PLL relocks. In this case, the data will need to be reframed.
If the interruption is asynchronous, and the link interface allows noise to be injected into the serial inputs
of the HOTLink Receiver, the time to relock the PLL becomes much harder to predict. If the noise that
is being injected causes the PLL to track within its frequency offset limits (approximately ±O.25% of the
REFCLK frequency) the PLL will reacquire in a few bytes (typically less than ten) after a good data
stream reappears. If the PLL frequency has been moved to its offset limits by the input noise, it may take
more than 60-70 bytes before the PLL lOl:ks tu tllt: guuu uata. Wht:n tht: PLL hiis iht: frt:qut:m.;y offsei
limit, it will recenter itself at the REFCLK frequency and then attempt to lock to the data. While the PLL
is out of lock (after experiencing a data stream interruption) the frequency of CKR will not wander beyond
the offset limits.
For more information, refer to the Receiver Data-Phase Acquisition Time section of the "HOTLink Jitter
Characteristics" application note.
7. If the connection between HOTIink Transmitter and Receiver is broken, what will come out of the receiver?
The exact behavior of HOTLink Receiver is difficult to predict when the serial data link is broken, since
there are so many ways that the link itself can behave. The following behaviors are most common;
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-===rcYPRESS
Frequently Asked Questions about HOTLink
Bypass Mode-Reframe-OFF (RF = LOW) Clean link break with no extraneous noise input into serial
inputs:
•
CKR runs at REFCLK frequency.
•
RDY is always HIGH.
•
Oa-j all go LOW or HIGH depending on exact offsets built into transmission line termination. If
the terminations are exactly matched, then Oa -j may be indeterminate.
Bypass Mode-Reframe-OFF Noise injection into serial inputs:
•
CKR runs at REFCLK frequency ± < 1.0% (typically < ±0.25%) and may wander between its range
limits and the center frequency, randomly controlled by the injected noise.
•
RDY may rest HIGH or may pulse randomly as false K28.5s are decoded from the noise.
•
Oa-j will be indeterminate and may switch randomly.
Encoded Mode- Reframe-OFF Clean break with no extraneous noise input into serial inputs:
I
•
CKR runs at REFCLK frequency.
•
RDY pulses once per byte.
•
00-7 indicate CO.7, SC/D is always HIGH, RVS is always HIGH if there are any offsets built into
transmission line termination. If the terminations are exactly matched, then 00-7, SC/D and RVS
may be indeterminate.
Encoded Mode- Reframe-OFF Noise injection into serial inputs:
•
CKR runs at REFCLK frequency ± < 1.0% (typically < ±0.25%) and may wander between its range
limits and the center frequency randomly controlled by the injected noise.
•
RDY may pulse randomly or once per byte.
•
00-7,
SC/D and RVS may be indeterminate and may switch randomly.
Either Mode-Reframe-ON Noise injection into serial inputs:
•
CKR runs at REFCLKfrequency ± <1.0% (typically < ±0.25%) and may wander between its range
limits and the center frequency randomly controlled by the injected noise. If RF has been HIGH for
less than 2048 bytes, CKR will stretch randomly as false K28.5s are decoded from the noise. If RF
has been HIGH for more than 2048 byte-times, CKR will only stretch when a multiple K28.5 string
is decoded from the noise.
•
RDY may pulse randomly or once per byte.
•
00-7,
SC/I) and RVS may be indeterminate and may switch randomly.
8. What is the correct operation of the RF input on the receiver? What is the minimum number of K28.5
characters required to insure proper framing? How can I tell if the receiver is framed properly?
Recovery of information from a serial data stream requires recovery of the bit clock (accomplished by the
receiver PLL) and byte synchronization (accomplished by the receiver framer). The HOTLink framer
is enabled or disabled by the RF input. In well behaved, standardized point-to-point protocols that are
seldom switched, the control of the byte framer is managed as a service in the protocol controller. This
service monitors when some error criteria have been exceeded, and goes to a framing subroutine. This
framer service sets RF=HIGH while framing and LOW during normal message transactions.
4-39
Frequently Asked Questions about HOTLink
In less well behaved systems, or systems that switch data sources often, it may be necessary to leave
RF=HIGH for long periods (or permanently). Leaving RF HIGH opens the system to the problem of
data corruption in the serial link caused by data patterns that happen to match the SYNC character. Since
this Alias SYNC is unlikely to be aligned to the normal byte boundaries, it will cause the framer to align
the parallel data to the wrong byte boundary resulting in long running data corruption. When RF is set
HIGH, the receiver searches the received data stream for the bit pattern matching K28.5 (OOl1l1lOlO
or 110000 OlOl). When it is found, the internal bit counter that controls byte translation is reset and the
byte boundaries are aligned to the SYNC character.
HOTLink minimizes the alias SYNC problem by incorporating a multi-byte framer into the receiver. If
RF has been HIGH for less than 2048 bytes, as would be typical in protocol driven framing control, a single
K28.5 will align the byte boundaries. If RF has been HIGH for more than 2048 bytes, as would be typical
in packet switched systems, the multi-byte framer is enabled and a single K28.5 is no longer sufficient to
align the byte boundaries. To minimize the risk of alias SYNC, reframing is only allowed when two K28.5s
are detected. These two K28.5s can be adjacent, or separated by exactly one, two, or three transmission
characters. Any other spacing (i.e., non-integral character separation, or too far between K28.5) is assumed to be caused by transmission errors and will be ignored for framing purposes.
In addition to the upper level protocol error detection mechanisms common in communication links, the
HOTLink Receiver offers several indications that a link is misframed. For example, in Bypass mode the
RDY output pulses once per K28.5 detected. If RF is LOW, the only K28.5 that can be detected is one
that is properly framed, and all others will just pass through as part of the received data. If the protocol
in use has a maximum packet size or a minimum number of K28.5s, a simple retriggerable-one-shot can
be used to detect when framing has been lost. In this example, if the one-shot is retriggered by the properly
spaced K28.5s, then the data is properly framed. If the one-shot times-out, indicating that too much time
had elapsed between SYNC characters, the data would automatically be reframed by raising RF till the
next K28.5 indication.
Another example of HOTLink's indication of a misframed link occurs during Encoded mode. In Encoded
mode, the RVS output serves a similar if not quite as obvious function. Normal data being sent over typical
data links will have a very low error rate (e.g., bit-error-rates of 1xlO- 12 are quite common. BER = 1xlO- 12
= one error per hour at 266 MHz). Therefore, if RVS is asserted often it can be assumed that the cause
is misframing. Another retriggerable-one-shot could be used to detect this condition, or it could be detected by a simple synchronous state machine constructed in a PLD.
For more information, refer to the "HOTLink CY7B933 RDY Pin Description" application note.
9. What happens to the receiver's clock and parallel outputs when it reframes?
When a byte boundary realignment occurs, the external timing of the HOTLink Receiver changes to
match the ne\v byte alignment. Logic internal to the receiver guarantees that the clock outputs (CKR and
RDY) never glitch. They will stretch to the new byte alignment by adding to the HIGH or LOW time of
the output pulse. The exact width of the high or low times of these clock outputs will depend on the exact
timing of the realignment, but neither will ever be less than that of a nominal, normally running output
(i.e., five bit times, each, minimum).
The data outputs (00-7, SCW, and RVS) all change at a time determined by internal bit-rate counters,
and are timed to assure maximum set-up and hold times to down-stream logic. Since realignment will
reset the cycle of the internal counter, it is possible that the outputs will change, and then change again
between clock edges when byte realignment happens. Since the clock-cycle stretches, this glitch on the
data output remains outside the specified data-access and hold times.
For more information, refer to the "HOTLink CY7B933 RDY Pin Description" application note.
4-40
~ ?cYPRESS ======;;;;;Fr;;;;;e;;;;;q;;;;;u;;;;;eD;;;;;t;;;;;ly;;;;;A=sk;;;;;e;;;;;d;;;;;Q;;;;;u;;;;;e;;;;;s;;;;;ti;;;;;o;;;;;D;;;;;S;;;;;ab;;;;;o;;;;;u;;;;;t;;;;;H;;;;;O;;;;;T;;;;;L;;;;;I;;;;;'D;;;;;k;;;;;
10. What does BIST do? How can I add BIST to my system without redoing all calculations for my critical
interface timing? What functionality does the BIST test and guarantee?
The HOTLink built-in self-test allows a clear and unambiguous check of the HOTLink Transmitter and
Receiver, and the serial link connecting them. As part of an offline diagnostic, this feature allows the user
to insure that the interconnect link is fully operational and that any other diagnostic failure indications
are caused by system blocks above the physical layer. BIST allows the HOTLink adapter card manufacturer to do a quick link quality test (or node quality test with the use of the loop-back functionality of HOTLink) without the necessity of bringing up a fully functional system to do link testing.
BIST is controlled by unused HOTLink data-enable inputs. Only a few connections and minimal external
logic are necessary to add BIST to an otherwise complete system. (See the Cypress application note
"HOTLink Built-In Self-Test.") BIST status indications appear on the RP, RVS(Qj) and RDY outputs
which are easily monitored by logic internal or external to the data flow controller.
In BIST mode, the HOTLink Transmitter generates a 29 -1 (511 byte) pseudo-random pattern using its
Input register configured as a Linear Feedback Shift register. The HOTLink Receiver compares the serial
BIST data stream with identical BIST patterns generated in its Output register. All of the logic in the
transmitter (except the input pins) and all of the logic in the receiver (including the output pins and their
attached loads) are checked by BIST. All of the serial link interconnect components are exercised with
normal data patterns, which are checked byte-by-byte in real time.
11. What fiber-optic components are compatible with HOTLink products?
All standard fiber-optic interface components are compatible with HOTLink products. The following
table is a representative but not comprehensive list of optical interface manufacturers. A more complete
list of vendors and products is included in the "HOTLink Design Considerations" application note.
AMP/Lyte! Division
61 Chubb Way
P.O. Box 1300
Somerville, NJ 08876
(908) 685-2000
Hewlett-Packard
Components Division
370 West Trimble Road
San Jose, CA 95131
(800) 535-7449 or (408) 435-6342
CTS Corp
1201 Cumberland Ave
West Lafayette, IN 47906-1388
(317) 463-2565
Siemens Fiber Optic Components
20F Commerce Way
Totowa, NJ 07512
(201) 890-1606
Sumitomo Electric
Fiber Optics Corporation
777 Old Sawmill River Road
Thrrytown, NY 10591-6725
(914) 347-3770
12. What is the significance of the HOTLink claim of "no external PLL components"?
HOTLink Transmitter and Receiver have completely integrated the PLL clock multiplier and data separator functions. These functions are implemented with high-performance phase-locked loops (PLLs) that
have been tuned for maximum performance and minimum system noise sensitivity. In competitive products that purport to offer similar functions, these PLLs are often implemented with external filter and frequency setting components with the goal of achieving maximum performance. But these very same external components are the largest cause of end-user complaints and random system failures because they
expose the most critical analog signals in the circuit to the external noises that abound in normal systems.
External components require critical, costly and time consuming printed circuit board layout as well as
high-speed analog and digital design techniques that are unfamiliar to many system integrators. HOTLink products are designed and built using fully differential analog and digital circuits to give the lowest
possible output jitter and highest possible jitter tolerance. There are no external components to compromise system performance in unexpected and unpredictable ways. For more information, refer to the
HOTLink Transmitter Jitter section of the "HOTLink Jitter Characteristics" application note.
4-41
I
~
Frequently Asked Questions about HOTLink
13. What is the intrinsic bit-error-rate of HOTLink Transmitter and Receiver?
HOTLink BER = Zero. HOTLink Transmitter and Receiver have no intrinsic failure modes. If their power is maintained and if the interface to the link connecting them has reasonable design margin, the total
error rate will be exactly that of the interconnect media. Link error rates of < < lxlO- 15 are common and
easily achieved. Even with worst-case design derating and end-of-life derating, BER < < lxlO- 12 presents
no significant challenge.
The real question being asked is, "What will be my link BER when using HOTLink?" The answer to this
question involves the design of the serial transmission link and the margins designed into it. HOTLink
will not significantly degrade the BER ofthe link. For more information, refer to the "Understanding BitError-Rate with HOTLink" application note.
14. How much jitter is created by the transmitter? How much jitter is created by the receiver? What is the
significance of the HOTLink Transmitter requirement for a crystal-stable clock source?
The phase-locked loops (PLLs) in the HOTLink Transmitter and Receiver act like low-pass filters to jitter
that is embedded in the data or clock signal source. For the transmitter, the signal source is the CKW
input. Any jitter that appears at CKW will be passed unattenuated if it has frequency components below
the natural frequency of the PLL filter (approximately 500 kHz). Frequency components above the natural frequency will be attenuated at about 6 dB/octave. Frequency components that fall very near the natural frequency of the filter will be slightly amplified (approximately 0.5 dB). These are the normal characteristics of a Type-2, second-order PLL filter. When the transmitter is fed by a low jitter clock source,
typical output jitter will be less than 20 ps RMS and 200 ps peak-to-peak. It is possible to measure significantly more jitter than that which is actually present if the complete system is not well understood. A few
hundred millivolts of Vee noise, while insignificant to the logic of a normal system board, will add imaginary ,
jitter to the measured output. This imaginary jitter appears because a single ended oscilloscope sees the
waveform as if it were measured against a fixed threshold, while the differential serial interface sees Vee
noise as a common mode signal to be ignored (e.g., 100 mV of Vee noise could create 100 - 200 ps of imaginary jitter). Likewise, the normal meiliod of measuring peak-to-peakjitter, an infinite persistence scope
trace, will show larger jitter than that contributed by the HOTLink Transmitter. Low frequency jitter
(wander) in the oscillator, scope trigger, temperature, and voltage related delay variations will all contribute to the width of the stored scope trace. Delay variations include TTL threshold variations that cause
apparent delay variation (e.g., 100 mV of TTL threshold change can cause 100 - 200 ps of apparent jitter).
The signal source for the receiver is the serial data stream and, like the transmitter, it passes the frequency
components of received jitter that fall below the natural frequency of its filter (approximately 300 kHz to
1000 kHz depending on actual data transition density being received). Frequency components above the
natural frequency will be attenuated and there is minor jitter peaking at about the natural frequency of
the PLL. Since the characteristics of the input jitter will determine the jitter content on the receiver elm
output (the only place to directly measure Rx-PLL jitter) it is somewhat difficult to predict the output jitter. Maximum CKR output jitter is less than 200 ps (peak-to-peak) when the receiver is tracking normal
data (BIST data is typical) that exhibits maximum tolerable peak-to-peak jitter. Jitter from normal data
is wide-bandwidth, has a significantly high-frequency content, and can have peak-to-peak amplitude of up
to about 90% of a bit time. If the serial data contains a significant low frequency jitter component (typical
of crystal oscillators and some pulse generators) the output jitter measured on the CKR pin could be much
higher. Jitter measurements at the receiver output can be more misleading than those associated with the
transmitter serial outputs, since all measurements are made on TTL outputs.
The jitter characteristics mentioned above affect system performance in the following ways. Any lowfrequency jit~er (below the bandwidth of either transmitter or receiver PLL) will be treated as wander.
4-42
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'CYPRESS
Frequently Asked Questions about HOTLink
For purposes of the PLLs, wander (usually caused by low frequency power supply variations or temperature fluctuations within the timing ICs) will not reduce the system timing margins and will not contribute
to bit-error-rate. Wander can affect system timing at interfaces where the transmitter clock source is used
to clock information received from a receiver tracking data from another clock source. The variation in
clock frequencies may violate set-up and hold times, the exact problems usually solved by FIFO memories
in typical communication systems.
High-frequency jitter (at or above the natural frequency of the PLL filters) may contribute to BER. Highfrequency jitter can be caused by the clock source, media transfer characteristics, or external noise. The
recovered internal bit-rate clock will not track high-frequency jitter above the PLL natural frequency.
High-frequency jitter, therefore, may cause a bit edge to move into the receiver sampling window causing
the bit to be erroneously sampled (a bit error).
A suitable clock source should be selected with the above effects in mind. The only clock source guaranteed to offer the required stability and high-frequency specifications is a crystal oscillator. High-frequency
jitter is minimal, and low-frequency wander is usually small and very low frequency. Frequency accuracy
is easily guaranteed by mechanical means, and high accuracy devices are relatively low cost. Free-running
resistor-capacitor (RC) oscillators, logic gate ring oscillators or inductor-capacitor (LC) oscillators include too much high-frequency jitter, experience wide frequency variation as a function of process and
environmental conditions and thus are unsuitable for this application. See the "HOTLink Jitter Characteristics" application note for more information.
15. Can I use HOTLink for anything other than Fibre Channel/ESCON'" interconnect?
HOTLink has been designed to implement the required performance and specifications of Fibre Channel
and ESCON, but has additional user features that encourage use beyond these specifications. The specific
timing of the parallel I/O and clock signals allow efficient interconnect with typical generic controllers and
FIFO memories. The built-in self-test and the included 8B/lOB encoder functions allow users to implement
custom protocols that are suitable to any data-movement application. HOTLink is compatible with all
common link interconnect media and interfaces. It is a low-cost, low-power, high-performance tool that
enables otherwise impractical system innovation. If there is data to move, HOTLink can carry it.
16. Is HOTLink compatible with ATM?
HOTLink is compatible with the 194.40 Mbaud (155.52 MBit/second), 8B/lOB interface defined by the
ATM Forum. It offers all of the data, special characters and framing behaviors described in the ATM Forum User-Network Interface (UNI) Specification. In particular HOTLink serves as the physical layer interface for the physical layer for 155 Mbps Interface (and its copper variant). When operating in this capacity, HOTLink runs at 194.40 Mbaud and uses the built-in 8B/lOB encoder. All required data and
special codes and responses are included in HOTLink.
17. Is HOTLink compatible with SONET?
HOTLink is not directly compatible with SONET for at least the following reasons:
•
There are no standard SONET frequencies within its operating range of 160-330 Mbaud.
•
HOTLink has a lO-bit unencoded interface, and SONET systems use an 8-bit interface.
•
SONET requires a much slower rate-of-change of frequency during loss of signal than HOTLink can
achieve.
The HOTLink Receiver can tolerate the long strings of zeros contained in SONET serial streams, and
future designs will directly accommodate SONET specifications.
4-43
I
Frequently Asked Questions about HOTLink
18. What is the latency through a HOTLink Transmitter and Receiver?
The input data is stored in the Transmitter Input register on the rising edge of CKW, so this becomes timezero. Approximately 21 bit-times (i.e., 21 times the period of CKW + 10) minus the tpD of a TTL output
buffer (approximately 10 ns) later, the first bit of that data will emerge from the OUTA±, B±, and C±
pins. Mter the transit time of the serial link, which can be significant, that bit will appear at the receiver.
Transit times for typical serial links include the propagation delay of the optical modules (typically
5-10 ns for the pair), if any, and the propagation rate in the link media (Le., approximately 1 ns/ft in
copper, and 2 ns/ft in multi-mode optical cable). Approximately 24 bit-times plus the tPD of a TTL output
buffer (approximately 10 ns) after the first data bit is received at the input of the receiver, it appears at
the QO-7 outputs. Eight bit-times later CKR rises and the data transfer is complete. The total latency
of a HOTLink Tx/Rx pair is approximately link delay plus 45 bit-times.
19. Is there a VERILOG or VHDL model of HOTLink?
Logic Modeling offers full function logic models of both the HOTLink ltansmitter (CY7B923) and the
HOTLink Receiver (CY7B933). These models perform all of the normal chip functions including BIST,
Encoded, and Bypass modes of operation. The models accurately model the "real" parts and have been
validated by having them run the actual-chip design-simulation vectors and the outgoing-test vectors.
Logic Modeling offers a wide variety of standard product logic models that run on various simulations
platforms. They can be reached at:
Logic Modeling
19500 N.W. Gibbs Drive
P.O Box 310
Beaverton, OR 97006
Telephone (503) 690-6900
Fax (503) 690-6906
20. I need to estimate the reliability of HOTLink in my design. How many components does it contain?
Table 3. HOTLink Reliability Data
CY7B923
CY7B933
Number of components
4285
7988
Number of transistors
3813
6855
Number of gates
2072
2960
85
90
Percent digital by gate count
Percent analog by die area
30
Die size
96 x 116 mils
20
126 x 131 mils
Built on Cypress Standard 0.8-micron BiCMOS. Designed for reliable operation at temperatures -55°C
< Tj < 155°C. All pins characterized to withstand ESD >4400V (HBM). Wafer Fab Capability in San
Jose, CA; Round Rock, TX.
HOTLink is a trademark of Cypress Semiconductor.
IBM is a registered trademark of International Business Machines Corporations.
ESCON is a trademark of International Business Machines Corporations.
4-44
Frequently Asked Questions about
HOTLink ™ Evaluation Boards
The following questions are frequently asked by customers who are using HOTLink Th1 Evaluation Boards.
These cursory answers will serve as an introduction for each topic. Separate application notes cover these
topics in more complete detail.
1. How can I convert a CY9266-C (7SQ) Evaluation Board to use SOQ cables? How can I convert a
CY9266- C (7SQ) board to use 93Q coax? How can I convert a CY9266-T (1S0Q) STP (shielded twistedpair) board to use 1000 STP cables?
Conversions of the CY9266 - C and CY9266 - T boards to use transmission lines other than those shipped
in the standard configurations is as simple as changing the transmission line termination resistors (R40
and R41) on the back side of the board. Carefully remove the ones currently on the board (presently 37.4Q
on a -C) and replace them with resistors with a value equal to half the transmission line characteristic
impedance (i.e., 2SQ for a SOQ cable). See Table 1 for the values used for some common cable impedances. Extreme care must be used to avoid delamination of the board and damage to the traces by excessive heat during desoldering and resoldering.
The change from higher to lower impedance transmission lines (e.g., 7SQ to SOQ coax or IS0Q to lOOQ
STP) may also require that the user change the transformer at Tl. Changes from lower to higher impedance transmission lines usually do not require transformer changes. Alternatively, it may be desirable to
add resistors at R54 and R5S. (If these resistors are added, cut the built-in wire-traces that currently short
the previously unused solder pads.) The higher currents involved in driving lower impedance transmission
lines require either a higher inductance transformer or series current limiting resistors.
As the impedance of the external cable changes, the drive level must vary to compensate. Part of the drive
circuit, R61 & R62, needs to change to in order to vary the drive current available. See Table 1 for the
values required for various cable impedances. Changes in drive current will change the spectral characteristics of the souce signal and therefore the usable distance with a specific media type.
Table 1. Cable Impedance vs. R Values
Cable Impedance
IS0Q
R40& R41
R61 &R62
75Q
392Q
lOOQ
50Q
261Q
93Q
46.4Q
243Q
7SQ
37.4Q
196Q
SOQ
24.9Q
130Q
4-45
I
Frequently Asked Questions
about HOTLink Evaluation Boards
#~
~'CYPRESS
2. How can I convert a CY9266-C (7Sr!) Evaluation Board to use lS0r! STP cables (like CY9266-T)? How
can I convert a CY9266-T (lS0r!) STP board to use 7Sr! cables (like CY9266-C)?
Conversion of the CY9266 - C and CY9266 - T boards to use transmission lines other than those shipped
in the standard configurations is as simple as changing the transmission line connectors and the transmission line termination resistors (see the answer to question 1).
For the CY9266-C: Carefully desolder and remove the BNC and TNC connectors installed at at 11 and 12.
Replace them with the connector of choice using the mounting and solder terminal holes provided.
WARNING: the CY9266 - C board grounds the shield of the coax, and therefore one side of the transformer secondaries. Cut the traces leading to 11 and 12 on the solder side of the board (Under PI) to
convert to balanced operation.
For the CY9266-T: Carefully desolder and remove the Sub-D installed at at Pl. Replace it with the connector of choice using the mounting and solder terminal holes provided. The three traces running on the
solder side from PI to 11 and 12 were cut to unground the cable and allow balanced operation. Reconnect
these wires for unbalanced cable connections.
Changing connectors often also involves changing the impedance of the cable used. See question 1 above
about changing the resistor values for different values of cable impedance.
3. What types of Optical Modules are compatible with the CY9266-FX Evaluation Board?
We have tested and are shipping the CY9266 - F Evaluation Board with Siemens, HP, and AT&T Optical
Modules.
Table 2. Vendors for Optical Modules
Vendor
Markings
Part Number
CTS
(formerly AT&T)
HP
1408N
1408N ODLXCVR
HFBR-5302
HFBR-5302
Siemens
V23806-A7-C2
Optical Data Link FC266 Transceiver
HP
(formerly BT&D)
AMP/Lytel
DLT1D40-ST-2
DLR1040-ST-2
269063-1
Separate TX & RX modules
uses ST Fiber cabling
AMP SC Duplex Transceiver 270 Mb/s 269063-1
These modules may be purchased from the following vendors. Although this is not a complete list of Optical Module vendors, it will serve as a starting point for finding a module that may suit your needs:
AMP/Lytel Division
61 Chubb Way
P.O. Box 1300
Somerville, NJ 08876
(908) 685-2000
Hewlett-Packard
Components Division
370 West nimble Road
San Jose, CA 95131
(800) 535-7449 or (408) 435-6342
CTSCorp
1201 Cumberland Ave
West Lafayette, IN 47906-1388
(317) 463-2565
Siemens Fiber Optic Components
20F Commerce Way
Totowa, NJ 07512
(201) 890-1606
Sumitomo Electric
Fiber Optics Corporation
777 Old Sawmill River Road
Tarrytown, NY 10591-6725
(914) 347-3770
4. Is this board compatible with (i.e., how do I use it with ... ) the IBMlHP OLC card?
The HOTLink Evaluation Board is intended to allow easy evaluation of Cypress HOTLink parts and is
not intended to replace the IBM® OLC card as a system interface (although it is capable of performing
4-46
Frequently Asked Questions
about HOTLink Evaluation Boards
this function). The OLC compatibility offered with these boards allows a familiar interface for those systems already compatible with the IBM cards.
OLC system interface signals in JP4 have the same timing and logical levels as the OLC card. Drive and
loading are similar, but not identical. The function of the CY9266 Byte-Sync output differs from that of
the OLC card when Sync-Enable is LOW. The OLC card will hold Byte-Sync LOW if Sync-Enable is
LOW, while the CY9266 will set Byte-Sync HIGH for each byte containing a K28.5. When Sync-Enable
is HIGH both boards will behave as the CY9266 does. The CY9266 behavior is convenient for implementing
a simple "out of lock" indicator using timers that detect the interval between K28.5s (when Sync-Enable
is LOW, a misframed K28.5 does not cause a Byte-Sync indication).
The CY9266 serial interface is incompatible with the IBM OLC card serial interface. The IBM OLC interface uses an 850-nm short wave laser and detector. The HOTLink Evaluation board uses off-the-shelf
1300-nm LED transmitters and detectors or copper transmission line interfaces. These various types are
not compatible. For an operational link, use two compatible serial interfaces (i.e., two CY9266 boards
of the same type, either - C, - T, or - F) for the two ends of the transmission link.
Note: The active signal level of the LOOPBACK signal, as implemented on the CY9266, is opposite that
of an actual OLC-266 card. If this signal is under software control, it should be programmed to allow signal
loopback when the signal is active Law. For hardware controlled systems an external signal inversion
is necessary, or the signal may be jumpered at JP1 for operation from the Sl-7 DIP switch.
The physical size of the HOTLink Evaluation Board was chosen to be compatible with the two-channel
version of the IBM OLC card. The X - Y dimensions are identical to those of the IBM product, but the
thickness and the protrusion of the serial interface hardware is different from the IBM product.
The IBM OLC card includes plastic card guides and attachment clips that facilitate its use in production
systems. The HOTLink Evaluation Board has none of these components since it is not intended for the
same function.
5. Where can I get additional fiber-optic cables and accessories? Where can I get additional coaxial cables
or STP cables?
We have located the following vendors of fiber-optic cables and accessories. You may contact them to receive
further information about their offerings. The lists below represent only some of the available sources.
Fiber Instrument
Sales Inc.
315-736-2206
315-736-2285 FAX
Nu-Power Optics
619-471-7131
FIBERTRON
Tel: 714-871-3344
Fax: 714-871-5616
Belden Wire and Cable
800-BELDEN-1order
317-983-5200
Additional coaxial and STP cables and other accessories may be found through:
Pasternack
Enterprises
714-261-1920
First Source
408-371-1470
Newark
312-784-5100
Digi-Key
Tel: 800-DIGI-KEY
6. How do I use this board to do bit-error-rate (HER) tests?
•
Connect the board(s) with a suitable length of transmission line or fiberfrom the TX port of one board
to the RX Port on another (or itself).
•
Place the receiving board's Receiver in BIST mode by setting the RCV_BlSTEN signal Law. Ground
the external pin marked RCV_BlSTEN or set switch Sl-5 to ON.
4-47
I
Frequently Asked Questions
about HOTLink Evaluation Boards
Siii.....-._,~
~~CYPRESS
•
Place the transmitting board's 'fransmitter in BIST Transmit mode by setting the XMIT_BISTEN signal LOW. Ground the external pin marked XMIT_BISTEN or set switch Sl-l to ON.
•
Press the white reset button on the receiving board. The display should initially show a .0.. As the
receiver finds an error in the data stream, it will show this with an increasing count. As the count exceeds 100, the overflow indicator will light up.
•
The BER may be approximated by: 1 errorlhour "" a BER of 1.1 x 10- 12 using the 2S.0-MHz oscillator
shipped with the board.
7. How do I use this board to do transmitter jitter tests?
To achieve the best possible and most accurate transmit jitter measurements, the external environment
of the HOTLink chips needs to have the lowest possible jitter to start. Common oscilloscopes and sources
have so much jitter as to obscure the contribution of the transmitter. Additional sources of jitter on this
board include:
•
For the -C and -T versions: the transformer's frequency characteristics. For the -F version: the
optical module.
•
Layout of these boards has not been optimized for this testing, and does not have specific test connections built in.
With these items understood, a set-up to do an adequate test requires a quiet clock source and a digital
oscilloscope such as the Tek 11801 or the HP 54720. The - F version without an optical module has the
most convenient connections. Making connections to the - F board at location U4, all differential PECL
signals, will allow the best measurements possible. (See the "HOTLink Jitter Characteristics" application
note for information on how to measure jitter.)
Note: Transmit Jitter measured out of a -C or -T board includes significant crosstalk from the receive
channel, coupled through the transformer. Ideally, measure Transmit Jitter with a quiet receive channel.
8. How do I use this board to do receiver jitter tolerance tests?
The ultimate performance of any serial link is determined by the performance of the receiver. The function of the receiver is to recover data from a (seemingly arbitrary) serial data stream. This data stream
is translated several times, coupled to and though several non-linear devices and subjected to all manner
of distortion. The receiver must accept this serial pulse train and recover a high-speed bit-synchronous
clock, de-jitter it, and then separate the DATA from the CLOCK. Jitter tolerance is the typical term for
the ability of the receiver to correctly recover the DATA and CLOCK in the presence of these many distortions. HOTLink Receiver jitter tolerance can be measured by connecting a suitable transmission media
between the transmitter and receiver, and inserting a jitter generation source similar to that shown in the
"HOTLink Jitter Characteristics" application note. By inserting measured jitter amplitudes and watching
the RVS output of the receiver, jitter tolerance can be measured. Further details on the fabrication of the
jitter generator and the measurement techniques required for accurate measurement of this injected jitter
is beyond the scope of this note, but are covered in detail in the "HOTLink Jitter Characteristics" and
"HOTLink Built-In Self-Test (BIST)" application notes.
9. How do I use this board to do HOTLink power supply noise immunity tests?
The layout and design of this board makes it difficult to test the power supply immunity of these parts.
Power supply noise immunity testing requires injecting a signal into the power supply pins and observing
the effect of this injected signal on the link. This requires a different layout to allow access to the power
supply pins of the HOTLink chips without affecting the operation of the other parts on the board.
4-48
Frequently Asked Questions
about HOTLink Evaluation Boards
:::::::::- - ~
~TcYPRESS = = = = = = = = = = = = = = = =
10. How do I use this board to do transmission-line tests?
To check for the maximum transmission-line length over which the HOTLink Evaluation Board can communicate, it is only necessary to connect the selected transmission line between the TX and RX ports of the
HOTLink Evaluation Board. Using one board with the cable returning to its own RX port or two boards and
cables for simultaneous testing in both/either directions of the transmission line will work quite well. The
H01Link Transmitter and Receiver BIST function serves the purpose of generating and testing the data so
the user can check for an acceptable error rate without extra test equipment. Transmission lines can be
extended or modified until the BIST error count indicates an unacceptable error rate. An error rate of
approximately 1 error/hour = a BER of 1.1xlO- 12 using the 2S.0-MHz oscillator shipped with the board.
11. How do I use this board to do receiver-PLL acquisition-time tests?
Two kinds of receiver acquisition are measurable using this board. One kind shows how fast the receiver
can recover from a phase hop, and the other shows how fast the receiver can acquire a datastream once
the device is powered up with a stable REFCLK.
To measure the receiver recovery from a phase hop, connect a loopback cable with a delay just large
enough to delay the data by almost one half a bit time (=2 ns for the shipped oscillator) with respect to
the OUTC+ line that goes between the CY7B923 and the CY7B933. Then arrange a delayed synchronous
switch signal into the NB Select input of the receiver. Trigger this delay from RP and delay this pulse to
a point in the data stream where the data stays HIGH for several bit times. By switching between the
delayed and fast signal path, a phase hop can be created at the input to the receiver. Increase the delay
until the receiver shows an RVS pulse during BIST testing. The receiver will properly recover data with
a phase hop as large as ± 170 Invert the AlB select signal to get the other polarity of phase hop.
0 •
To observe the receiver recovery from a "lost" data stream, arrange the evaluation board to have an external REFCLOCK 0.1 % faster or slower than the on-board oscillator. Configure the transmitter to only
send K28.5s by either deasserting both the ENN and ENA signals, or constantly transmitting a CS.O character in Encoded mode. With a clean pulse, switch the AlB select line to the B input. This will cause the
receiver to see a lost and then found data stream. Using a delayed trigger, watch the CKR output with
respect to the transmit clock. The two clocks will match frequency and stabilize in phase difference in less
than 60 !-Is.
12. How do I use this board to do minimax frequency tests?
•
Arrange the jumpers on the board so that the CKW and REFCLK use the same external clock input.
Do this by removing the jumpers across pins IX - IY and GY - HY, then jumpering pins GX-GY and
HX - IX. Apply an external reference clock to the XMITCLOCK pin on any of the interface connectors. Loopback the board either externally or by closing Sl-7, which loops the board back on itself.
•
Now enable the both the XMIT and RCVR BIST functions and the transmitter. The LED display
should now show a stable number. Clear the count by pressing the RESET button S2.
•
With the board set up as above, vary the frequency of the external reference clock from a nominal 20
MHz downward. As you approach the limits of operation, the board will start to indicate errors on
the display. Clear the errors after setting a new frequency by pressing S2 again. The point in frequency
where you do not see any BIST errors marks the edge of the frequency range. Change your frequency
source upward toward 33 MHz and again clear the error indications until you achieve stable operation
just below the high frequency limit.
Typical boards will operate as high as 40 MHz and as low as 12.5 MHz.
HOTLink is a trademark of Cypress Semiconductor.
IBM is a registered trademark of International Business Machines Corporation.
4-49
I
~
Serializing High Speed Parallel Buses to Extend
Their Operational Length
8. The UTOPIA Extender
Introduction
9. Conclusions
Parallel buses are used in many designs for the purpose of moving data from one point to another.
VME, ISA, EISA, VESA, PCI, SBus, and NuBus
are some of the more familiar bus architectures.
These buses are usually configured with a single bus
master and multiple users, all communicating over
a shared set of address and data lines. Some bus architectures, however, involve only two nodes on the
bus, creating a point-to-point data link. Regardless
of the architecture, the trend in bus design is for
higher bandwidth achieved by increasing the width
and transfer rate of the bus. When wide, highspeed, parallel buses are operated over distances of
more than a couple of feet, problems can result. The
source of these problems relates to the high-frequency signals interfering with each other over the
long parallel conductors of the bus. This application
note uses the UTOPIA bus as an example of how to
serialize a high speed parallel point-to-point bus in
order to allow the bus to operate over any distance.
The UTOPIA Bus
A good example of a high speed point-to-point parallel bus is the Universal Test and Operations Physical Interface for ATM (or UTOPIA). UTOPIA is
used in ATM (or Asynchronous Transfer Mode) applications. ATM is a network protocol that has
grown out of the need for a worldwide standard to
allow inter operability of information, regardless of
the "end-system" or type of information. With
ATM, the goal is one international standard.
ATM is a method of communication which can be
used as the basis for both LAN and WAN technologies. When information needs to be communicated,
the sender negotiates a "requested path" with the
network for a connection to the destination. When
setting up this connection, the sender specifies the
type, speed, and other attributes of the call, which
determine the quality of service. Thus ATM is a
switch-based technology (see Figure 1). By providing
connectivity through a switch (instead of a shared
bus) ATM delivers several benefits including dedicated bandwidth per connection, higher aggregate
bandwidth, well-defined connection procedures,
and flexible access speeds.
The topics covered in this application note are as
follows:
l. The UTOPIA Bus
2. UTOPIA Applications
3. Problems with Parallel Buses
Using ATM, information to be sent is segmented
into a fixed-length cell, transported to and reassembled at the destination. The ATM cell has a fixed
length of 53 bytes. Being fixed-length allows different traffic types on the same network. The cell itself
is broken into two main sections, the header and the
payload. The payload (48 bytes) is the portion that
4. The Serial Solution
5. Serial Links and HOTLink '"
6. Serializing the UTOPIA Bus
7. Round 'Trip Latency
4-50
-., ~
Serializing Parallel Buses
'CYPRESS
================
Each layer of the "protocol stack" provides services
to the layer above that allow the top most processes
to communicate. The idea is that two different devices, using hardware and software from different
vendors, but still conforming to the model, can communicate over an ATM network. The layers of the
protocol stack can be thought of as modules in software code. Each layer performs a specific function
and must provide data to other layers according to
a specified interface. However, how that layer accomplishes its task is immaterial. Thus, layers in the
stack can be updated without affecting the communication model.
Figure 1. ATM Connections Through Switch
carries the actual information-either voice, data,
or video. The Header (5 bytes) is the addressing
mechanism (see Figure 2).
The UTOPIA bus is a standard defined by the ATM
forum for moving data between the physical (or
PHY) and Asynchronous Transfer Mode (or ATM)
layers in the ATM protocol stack. The PHY layer interfaces directly to the network media (i.e., fiber,
twisted pair, etc.) and also handles "transmission
convergence" (that is, extracting the ATM cells
from the transport coding scheme). The ATM layer
processes the cell headers and directs routing. The
signals used by the UTOPIA bus are shown in Figure
4 and described in Table 1.
ATM closely follows the International Standards
Organization's (ISO) Open Systems Interconnection (OSI) model for communication. This model
breaks down any communication process into several sub processes arranged in a stack (see Figure 3).
Transmit Direction
48 bytes
5 bytes
TxDATA[O:7]
TxENB*
TxFULL *rrX{;LAV
TxSOC
TXvLK
Figure 2. ATM Cell Format
"*
Application Layer
-
Higher Layers
RxDATA[O:7]
RxENB*
RxEMt-' * RXvLAV
., jl
jl
Rx~Ut;
ATM Adaptation Layer (AAL)
RxCLK
ATM Layer
<=:J
Physical Layer
Receive Direction
PHY Layer
ATM Layer
Figure 4. UTOPIA Signals
Figure 3. ATM Protocol Stack
4-51
~ -., ~
Serializing Parallel Buses
'CYPRESS ================
Table 1. UTOPIA Signals
Signal Name
TxDATA[O:7]
TxENB*
TxFULL*
TxCLAV
TxSOC
TxCLK
RxDATA[O:7]
RxENB*
RxEMPTY*
RxCLAV
RxSOC
RxCLK
Description
Data lines for transmit (from
ATM to PHY layer)
Indicates data on this cycle is
valid
Indicates Tx FIFO on PHY layer can only accept 4 more bytes
(used only in Octet Level
Handshaking)
Indicates Tx FIFO on PHY layer is capable of storing an entire cell
Indicates data on this clock
cycle is the start of a cell
Clock for Tx signals and data
Data lines for receive (from
PHY to ATM layer)
Indicates data on this cycle is
valid
Indicates Rx FIFO on PHY layer is empty (used only in Octet
Level Handshaking)
Figure 5. UTOPIA in a Rack Mount Switch
shelves is a simple multi-conductor ribbon cable.
Since the shelves can be fairly far apart, the ribbon
cable required to connect the shelves can be anywhere from 1 to 6 feet in length.
Indicates Rx FIFO on PHY layer is currently storing an entire
cell
Indicates data on this clock
cycle is the start of a cell
Clock for Rx signals and data
Problems with Parallel Buses
The difficulty with the use of ribbon cable for the
UTOPIA switch application is related to the width
and bandwidth requirements of the bus, combined
with the uncontrolled impedance of the ribbon
cable. These three characteristics can lead to skew
across the signals of the UTOPIA bus as shown in
Figure 6.
UTOPIA Applications
The UTOPIA bus is present in any ATM system that
makes use of the ATM and PHY layers. Typical applications utilizing UTOPIA include Network Interface Cards and ATM switches. The ATM switch
application for UTOPIA is of particular interest.
Many switches are built using a rack mounted architecture as shown in Figure 5.
Note the skew shown in Figure 6 has violated the setup and/or hold times of the UTOPIA bus at the load
end. Therefore, data communication over the bus
will be corrupted. This effect is typical when highspeed parallel buses are driven over long distances.
One possible solution is to drive each line of the bus
differentially, but this also has the disadvantage of
increasing the already bulky ribbon cable, and it is
not guaranteed to solve the skew problem (skew can
In this type of switch, individual shelves of the rack
are dedicated to PHY layer circuits, and others to
ATM layer circuits. Thus the UTOPIA bus is used
to move the data between the different shelves of
the switch. Usually, the interconnect between the
4-52
-
-" ~
Serializing Parallel Buses
#CYPRESS================================
Source End
Load End
~
TxCLK
TxDATA[O:7]
~
III
TXENS*1+r
~
1+r
TXSOC~
TxFULL*rrxCLAV
J-tl
..f H
Iselup
_
I II
I~
~
Iselup
.... Ihold
in this single signal. To accomplish this clock and
data multiplexing function, serial links make use of
special encoding schemes and use clock recovery
circuits. The clock recovery circuits rely on the special characteristics of the data encoding scheme in
order to recover or generate a clock of the same frequency and phase (with respect to the serial data) as
the clock used to shift the data onto the serial link.
The serial-to-parallel converter then uses this recovered clock to resample or retime the serial data
before placing this data into a parallel word register.
When this register is full, the serial-to-parallel converter presents the data in the register (in a parallel
format) along with a parallel word clock (generated
by diViding down the recovered serial clock). Thus,
there is no skew between the clock and parallel data.
1 ..rL
I II
Ihold
The main advantages of a serial link over a parallel
bus are: (1) the clock is embedded with data, thus
there is no skew between clock and data signals, (2)
the distance over which the serial link is operated
can be changed and the link will remain operational,
(3) the transfer rate of the serial link can be scaled
up and the link will remain operational, and (4) the
cables required are smaller in size.
Figure 6. Effect of Skew on UTOPIA Bus
still result from differences in propagation delays
for each signal through its respective differential
driver/cable/receiver).
The Serial Solution
A good solution to the skew problems described
above is to transmit the parallel bus data as a serial
data stream. Transmitting the data serially requires
a parallel-to-serial conversion of the UTOPIA data
at the source end and a corresponding serial-to-parallel conversion at the load end. With such a
scheme, the skew problems associated with operating a high-speed parallel bus over long distances are
eliminated. In addition, the cable size is reduced
from a multi-conductor ribbon cable to a two-conductor serial cable (such as coaxial cable).
Serial Links and HOTLink
1M
The Cypress HOTLink chipset performs all of the
functions shown in the simplified block diagram in
Figure 7. The CY7B923 HOTLink Transmitter
serves as the serializer while the CY7B933
HOTLink Receiver operates as a deserializer. In
the HOTLink chipset, clock multiplication and
clock recovery are accomplished using Phase
Locked Loops (or PLLs). PLLs are closed loop control systems which align an output waveform in
phase and frequency with an input waveform. Block
diagrams of PLLs performing clock multiplication
and clock recovery are shown in Figure 8.
1M
The method by which a serial data transfer eliminates the skew problems associated with parallel
buses is related to how serial links operate. Although some "serial" communication systems utilize more than one conductor (e.g., RS232), more
serial links provide for transmission of only one signal. Note that to transmit one signal over copper
media requires two conductors. This transmission
can be either single-ended (requiring one conductor
for the signal and one reference or ground) or differential (requiring two conductors for one signal).
Both clock and data information must be included
PLLs operate by constantly comparing their output
waveform with their input (or reference) waveform.
Deviations in phase or frequency are then corrected
at a rate governed by the Low Pass Filter (LPF). A
wide bandwidth LPF allows a PLL to track high-frequency phase deviations between the reference and
the output waveforms. A narrow bandwidth LPF
dictates that the PLL rejects high-frequency phase
4-53
II
-., ~
Serializing Parallel Buses
'CYPRESS
Input word
================
Word clock
Ref
--------,
~
....H------,a.
'---.--,---'
o
0"
o
,-_..1..--_...,
Ref*N
I
I
I
I
I
ISerializer
!-_ _ _ _..,,J.Jata
'------,,-----' I
I
o
I
0"
o
I
_ _ _--l'"
I...----.-_-_---I
_ _ _ _ _ _ _ _ _ ...JI
~
Serial
In
Clock
Serial
Link
r--
Figure 8. Multiplication and Clock/Data Recovery
PLLs
------------,
of frequency lock. In order to reliably perform clock
recovery with PLLs, the serial data needs to be encoded in such a way as to ensure there are frequent
transitions (either from HIGH to LOW or LOW to
HIGH) in the serial stream. These transitions cannot be ensured when sending unencoded data, since
a user is free to send any data pattern. Some serial
patterns like 00000000 contain no transitions and
therefore could be transmited indefinitely resulting
in a serial link without any transitions.
Deserializer
Output word
The HOTLink chipset utilizes an encoding scheme
known as SB/lOB. This code takes in a S-bit data
word and converts it into a lO-bit transmission character. The transmission characters are chosen such
that their run length is limited to 5 consecutive ones
or zeros. With this encoding scheme, the HOTLink
Receiver's clock recovery circuit can maintain lock
and recover the clock from the serial data stream.
Word clock
Figure 7. Architecture of a Serial Link
deviations between the reference and output waveform. Ideally, an input waveform would have a transition at a regular periodic rate, thus allowing the
PLL to check its alignment constantly. However,
such a signal would contain no information (essentially the link would be composed of one baseband
frequency and its harmonics) and is not useful for
data communication. Actual serial streams do not
have data transitions at strictly periodic intervals.
Instead, there are often "runs" of consecutive ones
or zeros, which result in short periods where the serial stream has no transitions. The lack of transitions in the serial stream can cause the clock recovery PLL to fall out of phase lock, and eventually out
Serializing the UTOPIA Bus
Operating the UTOPIA bus over a serial link is accomplished using the architecture shown in Figure 9.
The basic block functions are as follows: On the
ATM side, the serializer converts the parallel
UTOPIA transmit data into a serial stream, embedding the UTOPIA transmit clock with the data. The
deserializer converts the serial receive stream (from
the PHY layer) back into parallel data and a receive
clock. The First In First Out (FIFO) memory works
4-54
Transmit Direction
c=:>
ATM Layer
PHY Layer
octets
Serial links
TxDATA
TxENB*
TxFULL*
<:=J
time
(clock cycles)
Receive Direction
, ,
5 4
,
o
Figure 10. Round Trip Latency Example
Figure 9. UTOPIA Serializer Block Diagram
tencywith respect to the TX_ENB* and TX_DATA
from the ATM layer to the PHY layer. A problem
arises if a transfer is in progress and TX_FULL *
goes LOW. The figure shows that the transfer began
successfully and several octets were placed onto the
serial link.
However, at clock cycle 1, the
TX_FULL* signal on the PHY side went LOW, indicating that the PHY layer is full. According to the
UTOPIA specification, the transfer must stop
(TX_ENB* must go HIGH) within four byte times
of TX_FULL* going LOW. In order for TX_ENB*
to go HIGH, the ATM layer must recognize the
change in state of TX_FULL *, but there is a delay
from the PHY layer to the ATM layer. During this
delay, the ATM layer may have already sent out too
many bytes (in Figure 10 five bytes are shown as being transmitted before TX_FULL * is recognized at
the ATM layer). Since it is possible to not recognize
the change in state of TX_FULL* within the four
byte specification, there is the potential for data loss
at the PHY layer.
as an elastic buffer, queuing the parallel receive
data until the ATM layer parallel interface is ready
to accept the data. The control logic provides control for all of the blocks. On the PHY side, the
blocks perform similar functions. The serializer
converts the parallel receive data into a serial
stream, embedding the UTOPIA receive clock into
the data. The deserializer converts the serial transmit stream (from the ATM layer) back into parallel
data and a transmit clock. The FIFO provides buffering for the transmit interface, and the control logic manages all of the blocks.
Round Trip Latency
The purpose of the FIFO in the serialized UTOPIA
architecture is to account for latency in the system.
To understand the importance of the FIFO, consider a design which implemented a serialized
UTOPIA bus. For UTOPIA transmits, there are
two handshaking signals TX_FULL* (sourced at
the PHY layer) and TX_ENB* (sourced at the ATM
load). A transfer is initiated when TX_FULL * goes
HIGH, followed by TX_ENB* going LOW and the
UTOPIA data placed onto the bus. If TX_FULL *
should go LOW at any time, the transfer must stop
(according to the UTOPIA specification) within
four write cycles. However, since TX_FULL* is
sourced at the PHY layer and sampled at the ATM
layer, there is a time delay for any change of state of
TX_FULL* at the PHY layer to be recognized at
the ATM layer. Figure 10 shows an example of the
timing relationships of the critical UTOPIA signals.
This time delay is the latency through the serializer,
serial media, and deserializer. There is a similar la-
Note that the latency in the link that is the source of
the problem in the above example is not entirely due
to the serializer and deserializer. If the serial link
itself is long enough, the mere time delay required
for the electrical pulses to travel down the link may
be enough to cause the problems described above.
The latency issue is solved by buffering the data
coming out of the deserializer. A FIFO is an adequate buffer for this application. With the FIFO
buffer, the effects of the link latency are corrected.
When the PHY layer UTOPIA interface indicates
it has no more room for data, the FIFO can store the
octets that are sent by the ATM layer before it receives the TX_FULL* signal. The data can then be
4-55
I
Serializing Parallel Buses
read out of the FIFO when the PHY layer UTOPIA
interface is ready.
The UTOPIA Extender
PHY Layer "'"',U'''''IO
Following the block diagram shown in Figure 9, and
the hierarchical schematics shown in Appendix A, a
serialized UTOPIA bus can be implemented. With
the bus serialized, it can essentially be extended to
any length, thus the design results in a "UTOPIA extender." The major components required to implement such a design are shown in Table 2.
Table 2. Cypress UTOPIA Extender Components
Generic Part
ATM Layer
Cypress Part
Serializer
CY7B923 HOTLink Tx
Deserializer
CY7B933 HOTLink Rx
FIFO
CY7B451 512x9 clocked FIFO
Control Logic
CY7C371 32-macrocell Flash
PLD
The "Top Level" hierarchical schematic shows a generic breakdown of the entire design. The ''ATM
Layer UTOPIA Extender" block implements all of
the functions at the ATM layer interface necessary
to serialize the UTOPIA bus. Likewise, the "PHY
Layer UTOPIA Extender" block implements all of
the functions at the PHY layer interface. Between
these two blocks are two serial links over which the
serialized UTOPIA bus operates. A system level
application of the UTOPIA Extender is shown in
Figure 11.
Figure 11. UTOPIA Extender in a Rack Mount
Switch
axial cable). The "Media Interface" schematic contains termination networks and transformers used
to interface the transmit and receive serial signals to
the coaxial cable.
The ''ATM'' and "PHY UTOPIA Logic" blocks contain all of the circuits used to serialize the UTOPIA
bus. These blocks contain the serializers, deserializers, FIFOs, and PLDs used to implement the logic
for the UTOPIA extender.
Both the ''ATM'' and "PHY Layer UTOPIA Extender" blocks have additional hierarchical schematics associated with them. Within these lowerlevel hierarchical schematics are additional blocks
that show more detail than the previous levels. Each
block performs a specific function necessary for the
operation of the entire design. Some functions are
common to both the ''ATM'' and "PHY Layer
UTOPIA Extender" blocks, such as the "Media Interface" block. The "Media Interface" block performs the function of interfacing the transmit and
receive electrical signals (comprising the serial links
carrying the serialized UTOPIA bus) to the specific
media interface used in the design (in this case to co-
The operation of the UTOPIA extender, implemented in the ''ATM'' and "PHY UTOPIA Logic"
blocks, can be broken down into two modes. The
first mode, or Steady State mode, moves the
UTOPIA transmit and receive data between the
ATM and PHY layers, and handles generation of
the necessary control signals. The second mode, or
FIFO State Update mode, handles the control of
the buffering FIFOs assuring that no data is lost due
to overfilling of these buffers. This mode also handles the case of the CLAV signals going inactive, indicating the UTOPIA interface cannot accept more
4-56
'i~
Serializing Parallel Buses
_'CYPRESS = = = = = = = = = = = = = = = =
data. Regardless ofthe mode of operation, the basic
link operation revolves around the Cell Level
Handshaking (or CLH) protocol.
Upon receiving the octets from the ATM layer, the
output of the HOTLink Receiver is immediately
placed into the buffering FIFO. In addition, when
the first octet out of the receiver is sensed (by taking
advantage ofthe forced gap between cells), an additional bit, serving as the TX_SOC signal, is placed
into the FIFO coincident with the first octet. The remaining 52 octets are also placed into the FIFO, but
without the TX SOC bit set. The TX_ENB * signal
to the UTOPIAl.nterface is then generated from the
TX CLAY signal and the FIFO status signals. The
PHYUTOPIA interface directly reads the output of
the buffering FIFO. Data movement in the
UTOPIA receive direction is similar.
The main characteristic of CLH is that once a cell
transmission begins, all 53 octets of the cell are sent
in succession on consecutive clocks. In this mode,
back to back cell transmissions are also possible.
For this design, however, back to back cell transmissions will not be allowed (this is accomplished
through special considerations in the UTOPIA controllogic). A gap will be forced between all cells.
This gap serves two purposes. The first is to allow
for the communication of the CLAY control codes
from the PHY layer to the ATM layer and also to update the status of the buffering FIFOs. The second
reason for the gap is to allow for easy generation of
the SOC signal at the load end of the serial link.
The other mode of operation is FIFO State Updating. This mode basically serves to handle the case
when the CLAY signals change state. That is, if the
TX CLAV is deasserted, no data will be read out of
the -PRY side buffering FIFO. Eventually, this
FIFO will fill beyond a check point and a code will
be sent back to the ATM layer side indicating no
more data should be sent until the FIFO is read beyond a certain level. The operation of this mode requires some additional control logic. Again, consider the case of UTOPIA transmission. A FIFO state
update begins when the control logic on the PHY
layer side detects that the buffering FIFO has filled
beyond a predefined level. The control logic then
waits for a pause in the data stream going back to the
ATM layer side (remember a gap is forced between
successive cells). During this pause, the control logic inserts a "FIFO Full" control code into the HOTLink transmitter in place of one of the comma characters (see Figure 13). This FIFO Full code travels
across the link back to the ATM layer side. The
ATM layer control logic then interprets the FIFO
Full code and deasserts the TX CLAY signal at the
ATM layer UTOPIA interface,thus stopping transmission on the next cell boundary.
The Steady State mode of operation for the
UTOPIA extender is defined as the condition when
neither buffer FIFO is overfilled. When in this
mode, there is a minimal amount of control logic
necessary to implement the extender. As an example, consider a UTOPIA transmit (defined as data
movement from the ATM to the PHY layer). When
a 53-octet cell becomes available on the ATM layer
side, it is immediately placed into the HOTLink
transmitter and sent over to the PHY side. Following the first octet, the remaining 52 octets of the cell
are sent consecutively. Following transmission of
the 53rd byte, the link pauses to implement the
forced cell gap. During this pause, the HOTLink
Transmitter is disabled and sends idle characters
(called K28.5 or "Commas") across the link. If
there is another cell available from the ATM layer,
it is sent across after the cell gap. If no data is available, the link remains disabled. The flow of data under the steady state mode is shown in Figure 12.
SOC bits added after deserializer
Eventually, the PRY layer FIFO will empty past
another predefined level, thus indicating data transmission can begin again. The control logic on the
PRY layer side then waits for a pause in the data
stream back to the ATM layer side, and inserts a
"FIFO Not Full" code in place of one of the comma
characters (see Figure 14). This code travels down
the link back to the ATM layer side where it is inter-
Figure 12. Transmission Data Flow
4-57
II
-. ~
Serializing Parallel Buses
~'CYPRESS================================
as shown in Figure 11. In general, these remaining
blocks contain connectors with pinouts specific to
the particular ATM/PHY layer circuits used in the
system. In addition, some ATM and/or PHY layer
circuits require additional circuits to configure and/
or monitor their operation. Thus the actual design
of the ''ATM UTOPIA and Processor Interface,"
"PHY UTOPIA and Processor Interface," and
"Framer Processor Interface" blocks differs depending on the unique ATM and PHY layer circuits
used in the system.
37 S.CJ
-c=:J
I
FIFO FULL
1
12): s~hdFIFO FULLcode 1
To exemplify a system using the UTOPIA Extender,
a complete design of the PHY Layer is shown in the
schematics (that is, only the "PHY Layer UTOPIA
Extender" is shown fully implemented). The PHY
Layer Circuit used was a Duke Communications
DC-202® SONET/ATM UNI Transceiver Module.
Thus the "PHY UTOPIA and Processor Interface"
block was tailored to interface to the DC-202. In
addition, the "Framer and Processor Interface"
block was required to configure the DC-202 for
proper operation. VHDL code for the "Framer and
Processor Interface Block" is included in Appendix
B. Also included in Appendix B is VHDL code implementing the algorithms for the "PHY UTOPIA
Logic" PLD.
Figure 13. FIFO State Updating, FIFO Full
preted by the ATM layer control logic. The control
logic then asserts the TX_CLAV signal to the ATM
layer UTOPIA interface allowing data transmission
to resume. Operation then reverts back to the
Steady State mode.
The remaining blocks in the UTOPIA Extender
(''ATM UTOPIA and Processor Interface," "PHY
UTOPIA and Processor Interface," and "Framer
Processor Interface") are used to interface the
''ATM'' and "PHY UTOPIA Logic" blocks to the
UTOPIA bus of the ATM and PHY Layer Circuits
Conclusions
This application note has shown that signal skew
across a ribbon cable can limit the operational distance of high-speed parallel buses such as UTOPIA.
Serial links can operate over longer distances since
they are not susceptible to the skew effects that limit
parallel buses. This application note describes the
design of a serialized parallel bus called the "UTOPIA Extender." Implementation of the UTOPIA
Extender requires only a minimal amount of logic,
with most of the work being performed by a highspeed serial-link chipset such as the Cypress
HOTLink chipset.
Figure 14. FIFO State Updating, FIFO Not Full
H01Link is a trademark of Cypress Semiconductor.
DC-202 is a registered trademark of Duke Communications.
4-58
~CYPRESS ===========~S;e;n;;;·a;li;;;zi;n~g~P;;ar~a~lI;el~B~u~s:es~
Appendix A. Hierarchical Schematics
Sheet 1 of 7: Top Level
II
4-59
Appendix A. Hierarchical Schematics
Sheet 2 of 7: ATM Layer UTOPIA Extender
4-60
~
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Appendix A. Hierarchical Schematics
Sheet 3 of 7: PHY Layer UTOPIA Extender
I
4-61
Appendix A. Hierarchical Schematics
Sheet 4 of 7: Media Interface
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Appendix A. Hierarchical Schematics
Sheet 5 of 7: PHY UTOPIA Logic
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Serializing Parallel Buses
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Appendix A. Hierarchical Schematics
Sheet 6 of 7: PHY UTOPIA Processor Interface
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4-65
Serializing Parallel Buses
QYPRESS
Appendix B: VHDL Code
UTOPIA Extender, PHY Layer
UTOPIA extender, PHY layer
USE WORK.phy_utopia_transmitter-package.ALL;
USE WORK.phy_utopia_receiver-package.ALLi
ENTITY phy_utopia IS
PORT (
hl_rx_ckr, hl_rx_sc_d,
master_reset,
phy_tx_full_tx_clav,
phy_fifo_hf, phy_fifo-pafe,
phy_fifo_empty
hl_rx_data
rX_fifo_soc,
phy_tx_enb, phy_fifo_enr
IN BIT;
IN BIT_VECTOR(O to 3);
INOUT BIT;
phy_rx_clk,
phy_rx_empty_rx_clav
phy_rx_data
hl_tx_sc_d, hl_tx_ena,
phy_rx_enb
hl_tx_data
IN BIT;
IN BIT_VECTOR(O to 7);
INOUT BIT;
INOUT BIT_VECTOR(O to 7));
ATTRIBUTE pi~numbers OF phy_utopia:ENTITY IS
"hl_tx_data(3):2 " &
"hl_tx_data(4):3 " &
"hl_tx_data(5):4 " &
"hl_tx_data(6) :5
&
"hl_tx_data(7):6 " &
"rx_fifo_soc:9 H &
"phy_fifo-pafe:l0 " &
"phy_fifo_hf:ll " &
"phy_rx_clk:13 " &
"hl_rx_sc_d:14 " &
"phy_fifo_enr:15 " &
"phy_tx_enb:16 " &
"hl_tx_sc_d:17 " &
'phy_rx_data(O):18 • &
'phy_rx_data(l) :19 • &
"phy_rx_data(2):20 " &
'phy_rx_data(3):21 • &
'phy_r~data(4)'24 " &
'phy_rx_data(5):25 " &
"phy_rx_data(6):26 " &
"phy_rx_data(7):27 " &
Nhl_tx_ena:28 n &
"hl_rx_data(O):30 • &
"hl_rx_data(1):31
&
"hl_rx_data(2) :32 " &
"hl_r~data(3):33 " &
"hl_rx_ckr:35 • &
"master_reset:36 " &
'phy_tx_full_tx_clav:37 " &
"phy_fifo_empty:38 " &
"phy_rx_empty_rx_clav:39 • &
"phy_rx_enb:40 " &
"hl_tx_data(O):41 " &
"hl_tx_data(l) :42 " &
"hl_tx_data(2):43 ".
END phy_utopia;
ARCHITECTURE netlist OF phy_utopia IS
SIGNAL atm_fifo_hf_code
SIGNAL atm_fifo_not_hf_code
SIGNAL phy_fifo_hf_state
: BIT;
: BIT;
BIT;
4-66
Serializing Parallel Buses
Appendix B: VHDL Code
UTOPIA Extender, PHY Layer (continued)
BEGIN
01: phy_utopia_transmitter
PORT MAP (hl_rx_ckr, hl_rx_sc_d, master_reset,
phy_tx_full_tx_clav, phy_fifo_hf,
phy_fifo-pafe, phy_fifo_empty, hl_rx_data,
phY_fifo_hf_state, rX_fifo_soc,
atm_fifo_hf_code, atm_fifo_not_hf_code,
phy_tx_enb, phy_fifo_enr);
U2: phy_utopia_receiver
PORT MAP (phy_rx_clk, phy_rx_empty_rx_clav, master_reset,
atm_fifo_hf_code, atm_fifo_not_hf_code,
phy_fifo_hf_state, phy_rx_data, hl_tx_sc_d,
hl_tx_ena, phy_rx_enb, hl_tx_data);
END netlist;
4-67
.-.
-
Serializing Parallel Buses
?cYPRESS
Appendix B: VHDL Code
UTOPIA Extender, PHY Layer 'fransmitter Interface (PHY to ATM)
-- UTOPIA extender, PHY layer transmitter interface (PHY to ATM).
PACKAGE phy_utopia_transmitter-package IS
COMPONENT phy_utopia_transmitter
PORT (
hl_rx_ckr, hl_rx_sc_d,
master_reset,
phy_tx_full_tx_clav,
phy_fifo_hf, phy_fifo-pafe,
phy_fifo_empty
hl_rx_data
phy_fifo_hf_state,
rX_fifo_soc, atm_fifo_hf_code,
IN BIT;
IN BIT_VECTOR(O to 3);
atrn_fifo_TIot_hf_code,
phy_tx_enb, phy_fifo_enr
INOUT BIT);
END COMPONENT;
END phy_utopia_transrnitter-package;
ENTITY phy_utopia_transmitter IS
PORT (
hl_rx_ckr, hl_rx_sc_d,
master_reset,
phy_tx_full_tx_clav,
phy_fifo_hf, phy_fifo-pafe,
phy_fifo_ernpty
hl_rx_data
phy_fifo_hf_state,
rX_fifo_soc, atm_fifo_hf_code,
IN BIT;
IN BIT_VECTOR(O to 3);
atm_fifO_TIot_hf_code,
phy_tx_enb, phy_fifo_enr
INOUT BIT);
END phy_utopia_transmitter;
ARCHITECTURE behavior OF phy_utopia_transmitter IS
Codes received from ATM side pertaining to the state
of the ATM side FIFO.
Note, the 'fifo_hf_code'
is a HOTLink K28.0 code, while the 'fifo_not_hf_code'
is a HOTLink K28.2 code.
CONSTANT fifo_hf_code : BIT_VECTOR := X"2";
CONSTANT fifo_not_hf_code
BIT_VECTOR
X"O";
: BIT;
BEGIN
-- Generate the FIFO read enable signal using the invert of
-- phy_tx_full_tx_clav. Also, want to disable when resetting.
Note that data out of the FIFO is valid on the rising edge
AFTER the data is read out.
So, want to delay the phy_tx_enb
one clock from the FIFO read enable.
PROCESS
BEGIN
WAIT UNTIL hl_rx_ckr = '1';
phy_tx_enb_wait <= phy_fifo_empty AND phy_tx_full_tx_claVi
END PROCESS;
phy_tx_enb <= NOT(phy_tx_enb_wait) OR NOT(master_reset);
Essentially, rx_fifo_soc is a one clock delay (w.r.t.
hl_rx_ckr) of the hl_rx_sc_d pin.
This is then used to
generate the input bit to the FIFO for the phy_tx_soc signal.
4-68
-=
.,~
Serializing Parallel Buses
W;CYPRESS
Appendix B: VHDL Code
UTOPIA Extender, PHY Layer Transmitter Interface (PHY to ATM) (continued)
PROCESS
BEGIN
WAIT UNTIL hl_rx_ckr = '1';
rx_fifo_soc
<=
hl_rx_sc_di
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL hl_rx_ckr = '1';
IF «hl_rx_data = fifo_hf_code) AND (hl_r~sc_d = '1')) THEN
atm_fifo_hf_code <= '1';
ELSIF «hl_rx_data = fifo_not_hf_code) AND (hl_rx_sc_d = '1'))
THEN
atm_fifo_not_hf_code <= ' l ' i
ELSE
atm_fifo_hf_code
<=
'O'i
atm_fifo_not_hf_code <= 'O'i
END IF;
END PROCESS;
PROCESS (master_reset, phy_fifo-pafe, phy_fifo_hf)
Hysterisis is added to the PHY FIFO half-full flag via the
input 'phy_fifo_hf_state'. Thus, the half-full state
is set to TRUE (1) when 'phy_fifo_hf' = O. The half-full state
is set to FALSE (0) when 'phy_fifo-pafe' = O.
BEGIN
phy_fifo_hf_state <= (NOT (phy_fifo_hf) OR (phy_fifo-pafe AND
phy_fifo_hf_state)) AND (master_reset);
END PROCESS;
END behavior;
4-69
I
Serializing Parallel Buses
Appendix B: VHDL Code
UTOPIA Extender, PHY Layer Receiver Interface (PHY to ATM)
UTOPIA extender, PHY layer receiver interface (PHY to ATM).
PACKAGE phy_utopia_receiver-package IS
COMPONENT phy_utopia_receiver
PORT (
phy_rx_clk, phy_rx_empty_rx_clav,
master_reset, a~fifo_hf_code,
atm_fifo_not_hf_code,
phy_fifo_hf_state
IN
phy_rx_data
hl_tx_sc_d, hl_tx_ena,
phy_rx_enb
hl_tx_data
BIT;
IN BIT_VECTOR(O to 7);
INOUT BIT;
INOUT BIT_VECTOR(O to 7»;
END COMPONENT;
END phy_utopia_receiver-packagei
ENTITY phy_utopia_receiver IS
PORT (
phy_rx_clk, phy_rx_empty_rx_clav,
master_reset, atm_fifo_hf_code,
atm_fifo_not_hf_code,
phy_fifo_hf_state
IN
phy_rx_data
hl_tx_sc_d, hl_tx_ena,
phy_rx_enb
hl_tx_data
BIT;
IN BIT_VECTOR(O to 7);
INOUT BIT;
INOUT BIT_VECTOR(O to 7»;
END phy_utopia_receiver;
ARCHITECTURE behavior OF phy_utopia_receiver IS
Codes received from ATM side pertaining to the state
of the PHY side FIFO. Note, the 'fifo_hf_code'
is a HOTLink K28.0 code, while the 'fifo_not_hf_code'
is a HOTLink K28.2 code.
'packet_size' is the number of bytes in a packet (i.e. 53 bytes)
'packet_gap' is the minimum number clocks allowed between
packets.
'packet_start_delay' is the number of clocks from when 'phy_rx_enb'
is valid to when data appears at the PHY UTOPIA receiver
interface.
Currently, this is defined by the UTOPIA spec.
as 1 clock.
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
fifo_hf_code
fifo_not_hf_code
packet_size
packet_gap
packet_start_delay
BIT_VECTOR
BIT_VECTOR
INTEGER :=
INTEGER :=
INTEGER :=
:= X"02";
:= X"OO";
53;
1;
0;
State of ATM side FIFO maintained on PHY side as tatm_fifo_hf'.
State of PHY side FIFO as known on ATM side is
'phy_fifo_hf_on_atm'.
SIGNAL atm_fifo_hf
SIGNAL phy_fifo_hf_on_atm
: BIT:=' 0' ;
: BIT:=' 0' ;
The 'counter' signal is used to establish the length of
the packet from the PHY UTOPIA receiver interface.
It
is also used to assure that there are a sufficient number
of clocks in between packets as defined by 'packet_gap'.
The 'hotlink_idle' signal is used to indicate no data
is being transmitted by the HOTLink Tx and thus the
Tx could be used to send FIFO update codes.
: INTEGER(O to packet_size) :=0;
BIT:='O' ;
SIGNAL counter
SIGNAL hotlink_idle
4-70
=
~
Serializing Parallel Buses
.'CYPRESS
Appendix B: VHDL Code
UTOPIA Extender, PHY Layer Receiver Interface (PHY to ATM) (continued)
TYPE
state_type IS (wait_here, start_delay, count, cell_gap);
SIGNAL present_state, next_state
: state_type := wait_here;
BEGIN
PROCESS (master_reset, atm_fifo_hf_code, atm_fifo_not_hf_code)
BEGIN
IF (master_reset = '0' OR atm_fifo_not_hf_code
atm_fifo_hf <= 'O'i
ELSIF (atm_fifo_hf_code = '1') THEN
atm_fifo_hf <= '1';
=
'1') THEN
Set 'atro_fifo_hf' to 1 when receive
'atm_fifo_hf_code' and clear when receive
'atrn_fifo_not_hf_code'.
END IF;
END PROCESS;
PROCESS
BEGIN
I
WAIT UNTIL phy_rx_clk = '1';
IF (present_state /= next_state>
THEN
counter <= 1i
ELSE
counter <= counter +1;
END IF;
END PROCESS;
PROCESS (present_state, counter, phy_rx_empty_rx_clav, atm_fifo_hf,
mas ter_reset)
'phy_rx_empty_rx_clav' is 1 when the PHY side has
a full cell (53 bytes).
So, if the ATM side
FIFO is not half-full, then set 'phy_rx_enb'
to 0 and start transmitting cells back to the
ATM side.
Stop (i.e. set 'phy_rx_enb' to 1)
after 53 bytes to prevent back to back cell
transfers from the PHY UTOPIA receiver interface.
Wait an additional 'packet_gap' number of clocks
before reenabling the receiver via 'phy_rx_enb'.
We must assure that there are at least packet_gap
bytes between packets in order to recreate the
rx_soc signal on the ATM side.
This gap will
also be used to send PHY FIFO state codes to
the ATM side.
BEGIN
CASE present_state IS
WHEN wait_here =>
phy_rx_enb <= '1';
hotlink_idle <= '1';
IF (phy_rx_empty_rx_clav = '1' AND atm_fifo_hf
AND master_reset = 11')
THEN
IF (counter < packet_start_delay)
THEN
next_state <= start_delay;
ELSE
next_state <= count;
END IF;
ELSE
END IF;
4-71
'0'
i
iiE
~
Serializing Parallel Buses
CYPRESS = = = = = = = = = = = = = = = =
Appendix B: VHDL Code
UTOPIA Extender, PHY Layer Receiver Interface (PHY to ATM) (continued)
WHEN start_delay =>
phy_rx_enb <= '0';
hotlink_idle <= '1';
IF «counter < packet_start_delay)
AND master_reset = '1')
THEN
next_state <= start_delay;
ELSIF (master_reset = '0')
THEN
ELSE
next_state <= count;
END IF;
WHEN count ==>
phy_rx_enb <= '0';
hotlink_idle <= '0';
IF «counter < packet_size)
AND master_reset = '1')
THEN
next_state <= count;
ELSIF (master_reset = '0')
THEN
ELSE
END IF;
WHEN cell_gap =>
phy_rx_enb <= '1';
hotlink_idle <= '1';
IF (counter < packet_gap)
THEN
next_state <= cell_gap;
ELSIF (phy_rx_empty_rx_clav = '1'
AND at~fifo_hf
'0' AND master_reset
THEN
IF (packet_start_delay < packet_gap)
THEN
next_state <= count;
ELSE
next_state <= start_delay;
END IF;
ELSE
next_state <= wait_here;
END IF;
END CASE;
END PROCESS;
=
PROCESS
BEGIN
WAIT UNTIL phy_rx_clk = '1';
present_state <= next_state;
END PROCESS;
PROCESS (phy_fifo_hf_state, phy_fifo_hf_on_atm, hotlink_idle,
phy_rx_clk)
BEGIN
-- If hot1ink_idle = '0' send data.
IF (hotlink_idle = '0')
THEN
hl_tx_ena
<= 'O'i
hl_tx_sc_d <= '0';
hl_tx_data <= phy_rx_data;
4-72
'1')
Appendix B: VHDL Code
UTOPIA Extender, PHY Layer Receiver Interface (PHY to ATM) (continued)
-- If the HOTLink is idle (no data being sent) and
the FIFO state needs updating, send the code.
ELSE
hl_tx_sc_d <= '1';
IF (phy_fifo_hf_state /= phy_fifo_hf_on_atrn)
THEN
hl_tx_ena <= '0';
IF (phy_fifo_hf_state = '1') THEN
hl_tx_data <= fifo_hf_code;
ELSE
hl_tx_data <= fifo_not_hf_code;
END IF;
ELSE
END IF;
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL phy_rx_clk
'1' ;
IF hotlink_idle = '1'
THEN
phy_fifo_hf_on_atrn <= phy_fifo_hf_state;
END IF;
END PROCESS;
END behaviori
4-73
I
~CYPRESS
Serializing Parallel Buses
Appendix B: VHDL Code
UTOPIA Extender, Duke PHY Board Programmer
-- UTOPIA extender, Duke PHY board programmer
PACKAGE duke-programmer-package IS
COMPONENT duke-programmer
PORT (
ref_clk, reset
proc_modcs, master_reset
: IN BIT;
INOUT BIT;
INOUT INTEGER(O to 24));
counter
END COMPONENT;
END duke-programmer-package;
ENTITY duke-programmer IS
PORT (
ref_clk, reset
: IN BIT;
INOUT BIT;
INOUT INTEGER(O to 24));
proc_modcs, master_reset
counter
ATTRIBUTE pin_numbers OF duke-programmer:ENTITY IS
"reset:2
II
'ref_clk:1
"counter(O)
"counter (1)
"counter (2)
"counter (3)
"counter (4)
&
" &
:21
:20
:19
:lS
:17
"
"
'
"
"
"proc~odcs:22 "
"master_reset:23
END
&
&
&
&
&
&
II.
duke-programmer;
ARCHITECTURE behavior OF duke-programmer IS
CONSTANT num_values
: INTEGER :=24;
TYPE state_type IS (wait_here, do_reset, count1, count2, count3);
TYPE addrdata IS ARRAY(O to num-values - 1) OP BIT_VECTOR(O to 7);
CONSTANT addresses: addrdata :=
(
X'Sl",
X'Sl" ,
X"SO" ,
X"SO" ,
X"20" ,
X"SO" ,
X"S2' ,
X'S3",
X"S4",
X'SS',
X"S6",
X"S7" ,
X"SS" ,
X"S9" ,
X"SA' ,
X"SB" ,
X"SC" ,
X"SE" ,
X"SP" ,
X"90",
X"91" ,
X"92" ,
X"9E' ,
X"9P') ;
4-74
Serializing Parallel Buses
QPRESS
Appendix B: VHDL Code
UTOPIA Extender, Duke PHY Board Programmer (continued)
CONSTANT data : addrdata :=
(
X'Ol",
X"OO' ,
X'Ol" ,
X'OO" ,
X"OA" ,
X'OO",
X"OO' ,
X'OO",
X"OO",
X"OO' ,
X"OO" ,
X"OO' ,
X"OO' ,
X"OO",
X"OO',
X"OO" ,
X"OO' ,
X"OO" ,
X'OO" ,
X"OO" ,
X"OO' ,
X'OO" ,
I
x·oo·) ;
SIGNAL
present_state, next_state
BEGIN
PROCESS (present_state, reset,
BEGIN
ref_elk)
CASE present_state IS
master reset
<; 'l'i
proc_modcs <; '1':
IF (reset = '0')
THEN
ELSE
END IF;
master_reset <= 'O'i
proc_modcs <= '1':
next_state <= countl:
WHEN
count!
=>
master_reset <= '1':
proc~odcs <= '1';
next_state <= count2;
WHEN count2 =>
master_reset <= '1';
proc~odcs <= 'O'i
next_state <= count3;
4-75
-.
~
Serializing Parallel Buses
,CYPRESS = = = = = = = = = = = = = =
Appendix B: VHDL Code
UTOPIA Extender, Duke PHY Board Programmer (continued)
WHEN count3 =>
master reset <= 'l'i
proc~odcs
<=
'l'i
next_state <= count2i
IF (counter < num_values - 1)
THEN
next_state <= count1;
ELSE
END IF;
END CASE;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL ref_clk
=
'1';
present_state <= next_state;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL ref_clk
=
'1';
IF (present_state = count3)
THEN
counter <= counter + Ii
END IF;
END PROCESS;
END behavior;
4-76
Drive ESCON™ With HOTLink™
erals as shown in Figure 1. These bus and tag cables
were daisy-chained from the host channel adapter
through multiple storage and VO directors.
Introduction
The IBM® ESCON'" (Enterprise System CONnection) interface is presently experiencing rapid
growth. Originally designed as a replacement for
the older block-mux channel, it is also finding use as
a high-performance system interface. This once
IBM-proprietary interface is presently being processed to become an ANSI standard interface
(known as SBCON) for computer to peripheral interconnect.
While quite powerful in its day, the block-mux channel shows both its heritage and its age. The bus and
tag cables are quite bulky (around 1.5" in diameter),
heavy, and costly. The maximum length of the link
between the host CPU channel adapter and the
cable terminator is 400 feet, and operates at a maximum transfer rate of 4.5 MBytes/second. While
originally designed to simultaneously support a
larger number of peripherals, its is now possible to
saturate the full VO bandwidth capability of a blockmux channel with a single disk drive.
This application note contains an overview of
ESCON operation and a design example of an
ESCON physical interface, including a number of
the low-level ESCON state machines (including the
VHDL source code), implemented using
HOTLink™ and a pASIC'" field programmable
gate array.
ESCON Channel
The ESCON channel was introduced in 1990 along
with the ESA390 series of mainframe computers. It
uses high-speed serial, point-to-point fiber-optic
links to replace the daisy-chained parallel-bus copper cables of a block-mux channel. By maintaining
the same host CPU software structures used with
the block-mux channel, it was possible to dramatically change the architecture (and performance) of
the VO subsystem without effecting the major VO
routines present in the host CPU and channel microcode.
Channels
The term channel, when referring to mainframes,
carries a specific meaning. Rather than representing the connection between pieces of equipment,
here it also represents a significant piece of equipment as well. The channel is, in effect, a sophisticated and intelligent DMA engine whose purpose is
to move information between I/O devices and main
storage. This channel function removes the burden
of handling VO activities from the main CPU.
This new interconnect media was also merged with
a dynamic switched connection scheme to improve
both availability and access to the I/O peripherals.
The use of switches (known as directors) allows
many more paths to each peripheral, with multiple
paths being active through each director at the same
time. This new interconnect structure is shown in
Figure 2. This switched VO structure is now finding
popular use in many other data communications in-
Block-Multiplexer Channel
The original block-multiplexer channel dates back
to the System 360/370 family of IBM mainframe
CPUs. It uses a pair of parallel-bus copper cables
(referred to as Bus and Tag cables) to move data between the host CPU and the VO and storage periph-
4-77
II
~
Drive ESCON With HOTLink
_;CYPRESS = = = = = = = = = = = = = = = =
Host
CPU
Figure 1. Block-Multiplexer Channel Subsystem
HostCPU-B
Host CPU-A
Channel
Subsystem
Channel
Subsystem
Channel
Subsystem
Channel
Subsystem
ESCON 1/0 Ports
ESCON 1/0 Ports
ESCON 1/0 Ports
ESCON 1/0 Ports
Figure 2. ESCON Channel Subsystem
4-78
-
-" ~
Drive ESCON With HOTLink
'CYPRESS================================
terfaces like switched Ethernet, ATM, and Fibre
Channel.
With a transmission character being ten bits in
length, there are actually 1024 possible transmission
characters. Of these possible codes, only a fraction
of them meet all the run length and DC-balance
coding rules. The remainder are illegal codes and
are detected as errors at the receive end of the link.
Most of the valid codes are used to represent the 256
possible data bytes, with a few remaining legal transmission characters used for synchronization and inband signaling.
The ESCON interface provides numerous improvements over the older block-mux channel. A few of
these are
• Improved transfer rate to 20 MBytes/second
• Longer distances-up to 3 km for each link and
up to three links (two switches) between Channel
and Control Unit
The term in-band means that all delimiters, protocol, clocking, etc., are handled through the same serial interface as the data; i.e., there are no other control lines or interfaces used for this information.
The 8B/lOB code provides twelve transmission
characters for these in-band functions. Of these
twelve characters (referred to as special characters), only six are defined for use by ESCON.
• Immunity from EMIJEMC concerns
• Improved access, redundancy, and availability
through use of dynamic switches
ESCON Physical
The physical-level interconnections of ESCON are
all made with 1300-nm LED-based optical links.
These links operate through either 62.5 !lm or 50 !lm
core multi-mode optical fibers at a fixed bit rate of
200 Mbits/second. This bit rate represents the encoded bit rate for the data being sent.
Synchronization
With any serial interface some form of synchronization is necessary at the receiver-end of a link. The
function of synchronization is to line up the receiver
bit and byte clocks with the serial data stream.
Bit Synchronization
The data sent across ESCON links is encoded using
the 8B/IOB code built into HOTLink. (See the
CY7B923/933 datasheet for a detailed description
of the 8B/lOB code.) This code converts normal
8-bit bytes into lO-bit transmission characters.
While this encoding does have a 25% overhead, the
benefits of using it far outweigh the data-rate penalty.
Bit synchronization is performed (for the most part)
automatically by the receiver PLL. As transitions
are detected, the phase detector in the receiver uses
the position of the transition (relative to its internal
bit-clock) to adjust the phase and frequency of the
local bit-clock. This local bit-clock is optimally adjusted to allow the serial data stream to be sampled
at the center of each bit. However, bit synchronization alone is not sufficient to recover and decode the
transmitted information. This requires knowledge
of which bit in the serial stream is the start of a character.
Part of the reason for the two extra bits in each character is to guarantee a minimum transition density
for the receive PLL. Since no clock is present in the
serial data, the HOTLink receiver PLL is used to extract a bit-rate clock from the data steam
Framing
Another benefit from this code is its DC-balance
characteristic. This means that, over time, the net
difference of all I-bits versus O-bits sent is at or
near zero. This DC-balance characteristic allows
the optical receiver circuits to be much simpler and
lower in cost by reducing the complexity of the AGC
(automatic gain control) in the receiver preamplifier.
Proper detection of character boundaries is referred to as framing. Unlike bit synchronization,
which occurs primarily in the analog domain, framing is a full-digital operation.
Framing is performed by examining the serial bit
stream for a specific pattern (called a comma). This
4-79
II
b~
Drive ESCON With HOTLink
~'CYPRESS ===============
test occurs on every bit-clock until an exact match is
found. At this point the receiver byte-clock is reset
to line up with the character boundary. Following
this, all characters output from the receiver should
remain properly synchronized, until some external
event causes a significant disruption in the data
stream.
No-Signal or
Power-On-Reset
The comma in the 8B/I0B code is the seven bit pattern 0011111 (orits alternate 1100000). This bit pattern is part ofthe K28.5 special character. It cannot
appear in any other location in any 8B/lOB encoded
character, and cannot be generated across the
boundaries of any pair of characters.
While the detection of individual bits is controlled
automatically by the PLL, the detection of framing
for ESCON must be under the control of a separate
state machine. This machine determines under
what conditions the receiver is allowed to perform
its framing function.
Figure 3. Synchronization State Machine
ESCON Synchronization
This requires reception of a minimum of fifteen
K28.5 characters with no intervening code violations between any of the received characters. These
K28.5 characters may be directly adjacent or more
likely will have other characters interspersed. Once
this string of K28.5 characters has been received, the
receiver enters the Synchronization_Acquired
state.
An ESCON interface is normally considered to be
in one of two states regarding synchronization; either Synchronization_Acquired or Loss_OCSynchronization (LOS). The transitions between these
two primary states actually involve a number of substates that track error conditions and special characters on the interface. This state machine is shown in
Figure 3.
Synchronization Acquired
. In addition to its five states (four Sync Acquired and
one Loss Of Sync), it operates with a 4-bit counter
to track both valid characters and K28.5 characters.
Since in any specific state of the machine only one
thing is being counted (valid characters or K28.5
characters), only a single counter is needed.
Exit from the LOS state also removes the reframe
signal from the receiver (RF=O). In this condition
the receiver will ignore (for framing purposes) all
K28.5 characters embedded in the data stream.
These characters are still properly received and decoded for use as part of the link protocol.
Loss Of Synchronization
In the Sync Acquired state the state machine now
tracks any code violations (RVS). If a code violation
occurs the state machine changes from the basic
Sync Acquired state (SAO) to SAL In this state the
machine has now detected a single error. It then enables the separate 4-bit counter to check for consecutive valid characters. If the following fifteen characters are received without error, the machine
reverts back to the basic Sync_Acquired state.
The ESCON interface automatically enters the
LOS state following power-on. In this state (if a valid signal is present) the serial data receiver is enabled not only to received data, but also to frame on
any received K28.5 character (RF=l).
While the receiver will frame on the first K28.5 received, this is not sufficient to leave the LOS state.
4-80
=:;;::• .,~
Drive ESCON With HOTLink
~'CYPRESS = = = = = = = = = = = = = = = = =
If, however, additional character errors are de-
• the first character of many ordered sets
tected, the state machine will advance through the
SAl, SA2, and SA3 states-one change for each
character received in error. At each of these states
the machine will again check for valid characters
and will revert to the previous state if fifteen are received without any errors. This would allow an interface receiving exactly one error every sixteen
characters to remain in the SAO and SAl states,
while a similar interface receiving one error every
fifteen characters would quickly move to the LOS
state and remain there.
• used to provide byte framing of the serial data
stream
• used as a fill or Idle character between frames
and sequences
Because the K28.5 character is contained in many of
the other ordered sets, a single K28.5 cannot be conferred to be an Idle function until the following character is detected. If the following character is also
an K28.5, then the previous K28.5 is part of an Idle
Function. If the following character is anything else,
then the K28.5 character is part of a delimiter or sequence (or an error).
Link-Level Operations
The actual functionality of an ESCON link is defined in terms of various ordered sets of special
characters and data bytes. These ordered sets are
used to define frame boundaries, control dynamic
connections, and control synchronization between
the transmitter and receiver circuits. All valid
ESCON ordered sets are listed in Table 1.
Delimiters
Delimiters are used to mark the start and end of
frames. Frames are the real workhorse of the interface because they carry data. All frames have a
start-of-frame delimiter (SOF) and an end-offrame delimiter (EOF). (An Abort delimiter is considered to be a type of EOP.) These delimiters are
only sent once per frame. Each frame must be separated by a minimum of four Idle characters.
Table 1. ESCON Ordered Sets
Characters
Ordered Set
Idle function
K28.5
Connect-start-of-frame
delimiter
Passive-start-of-frame delimiter
K28.1 K28.7
Abort delimiter
Disconnect-end-of-frame
delimiter
Passive-end-of-frame delimiter
Not-operational
Unconditional-disconnect
sequence
Unconditional-disconnectresponse sequence
Off-line Sequence
Sequences
Sequences are used to indicate specific equipment
conditions or states that cannot be identified
through the use of frames. Unlike a delimiter, the
ordered set defined for a specific sequence is sent
repeatedly until the machine state changes or a specific response is received. At the receiver, a sequence is only detected as being valid if the defined
ordered set is received a specific minimum number
of times in succession.
K28.5 K28.7
K28.6 K28.4
K28.4
K28.6 K28.1
K28.1
K28.6, K28.2
K28.5
K28.5 DO.2
K28.5 D15.2
Frames
Frames are used to carry information between the
channel, switches, and the peripherals. Tho generic
types of frames exist; Link-Control and Device
Level.
K28.5 D16.2
K28.5 D24.2
All frames follow the same three-field format:
Idle Function
• a 7-byte fixed-length link header
The K28.5 character in ESCON is used for multiple
purposes. It is
• a variable-length information field (may have a
length of zero for some Link-Control frames)
4-81
~~YPRESS~~~~~~~~~~;D;n;'v;e;E;S;C;O;N;W~ith~H;O;T;L;in;k=
FRAME STRUCTURE
Link Header Field
Information Field
Link Trailer Field
Figure 4. ESCON Frame Format
• and a 5-byte fixed-length link-trailer field
The CRC code used with ESCON is that defined by
the lTV VA 1 standard (previously known as
CCITT). The polynomial for this CRC is listed in
Equation 1.
The structure of an ESCON frame is shown in Figure 4. The low-order bit of the Link Control field in
the Link Header identifies the type of frame. When
set to a one, the frame is a Link Control frame.
When set to a zero, the frame is Device Level frame.
Eq.l
Normally with a code of this type the CRC remainder register is preset to an all 1s condition prior to
the first bit of information being clocked through
the polynomial. This is done to ensure that the polynomial will change state no matter what the data
stream contains. At the end of the generation, the
two bytes comprising the CRC remainder are sent as
part of the data stream. At the receiving end the
same process occurs, but the two CRC bytes are also
clocked into the CRC register. If no errors exist in
the serial stream then the contents of the CRC check
register should be zero.
Link-Control frames are use to manage, configure,
and maintain the link itself, and range in length from
12 to 116 bytes. Device Level frames carry data between the channel and the peripheral and range in
size from 17 to 1040 bytes.
Frame Validation
Before a frame can be processed, it must be validated as a properly received frame. This involves
making sure that there are no special characters or
idles in the middle of the frame, no decoding errors
are detected in the serial stream, and that the CRC
Field (Cyclic Redundancy Check) shows no errors.
To increase the level of protection, the CRC is handled slightly differently in an ESCON interface.
Here the CRC remainder generated at the transmitter is inverted prior to sending it across the link.
When it is received (correctly) the CRC check register is no longer cleared, but must be set to exactly
1DOF (hexadecimal). Any other value indicates a
transmission or reception error.
Cyclic Redundancy Check Field
The CRC field contains a 16-bit redundancy check
code, used to insure that the received frame contents are the same as those sent. This field is generated at the transmitting end of a link and sent as the
first two bytes of the Link Trailer field. It is calculated on all bytes between the start-of-frame delimiter and the Link Trailer field.
ESCON Design Example
The following design was originally done to replace
an existing ESCON protocol component that was no
longer available. All VHD L source code listed here
has been both simulated and tested in a functioning
ESCON system.
At the receiving end of the link the CRC is again
generated using the received data stream. Now the
CRC is generated on all bytes between the start-offrame delimiter and the end-of-frame delimiter.
4-82
-
-·f
~
; CYPRESS
Drive ESCON With HOTLink
================
This design example covers
To operate with the ESCON interface the transceiver must meet a number of specific characteristics:
• an ESCON-compatible optical media interface
• operate at 200 Mbaud
• ESCON-certified HOTLink serializer/deserializer components
• operate at 1300 nm wavelength
• use 62.5-f,lm or 50-f,lm core optical fiber
• a pASIC383 protocol chip containing
transmit and receive CRC circuits
parity check and generate circuits
synchronization state machine
command code translation capability
input/output pipeline registers
miscellaneous flip-flops, muxes, and gates
• meet the 0.7" ferrule spacing and other dimensions of an ESCON optical connector
In addition to these criteria, compliant transceivers
must meet numerous power level, receive sensitivity, and electrical interface criteria to properly operate in an ESCON environment. Manufacturers of
ESCON compatible fiber-optic transceivers include
Siemens, AMp, IBM, and others.
The design is partitioned into transmit and receive
data paths, and is implemented in four active devices:
SERDES
The next section in an ESCON link is the serializer/
deserializer block, also known as the SERDES.
This section converts parallel bytes of information
into an 8B/I DB encoded serial data stream for transmission, and also converts a received 8B/lOB encoded serial data stream back into parallel data
bytes.
• a pASIC383 containing both transmit and receive protocol functions
• a CY7B923 HOTLink transmitter for serialization and 8B/lOB encode
• a CY7B933 HOTLink receiver for deserialization and IOB/8B decode
The Cypress CY7B923/933 HOTLink components
are designed to perform this SERDES function.
These components are specifically optimized to
support the ESCON interface, as well as Fibre
Channel, ATM (Asynchronous Transfer Mode),
and proprietary communications links.
• a Siemens V23806-AI-MI6 ESCON fiberoptic transceiver
The structure of how these components connect and
major data paths are shown in Figure 5, with a complete schematic shown in Figure 6.
These HOTLink parts are especially well suited to
the ESCON market because of their built-in 8B/IOB
encoders and decoders. This encode/decode function is required for ESCON operation. By building
the encode/decode into the SERDES block, the
complexity of this part of the interface design is removed from the design process. Its presence in the
SERDES block also means that hardware resources
are not required elsewhere to implement the encode/decode function.
Fiber-optic Transceiver
The fiber-optic transceiver is an optoelectric device
that both converts electrical signals to light (transmitter) and light into electrical signals (receiver).
The 8B/IOB code used in the HOTLink components
is licensed by Cypress Semiconductor from IBM.
Any user of these parts is fully licensed to use the
8B/IOB encoders and decoders contained in them at
no cost and no royalties. For those applications that
already have 8BIlOB encoder/decoder circuits pres-
Figure 5. Design Example Structure
4-83
+5V
18
52
t:L
47 LOOPEN
~
~;a
?'
l"'l
11
12
13
14
15
CTXD7
CTXDB
C1J(D5
CTXD4
CTXD3
CTXD2
CTXD1
CTXDO
>
191 DATA IN
IDATilClN
1 VBB
o 1uF
270
• 110
2~
C1J(P
7 C1J(CD
PERR
17 1J(CLK
.¢.
SIEMENS-1J(
V23806-A1-M16
C"I:l
0
z
I
~
tr1
en
en
51
("'J
.j:>.
~
~
+5V
"'d
~
L1
15uH
--¥i DATA OUT
~/DATAOUT
I
;-
1nF I
20 SIG DET
/SIG" DET
- OPTICAL
INPUT
I 1nF
So
t".>
n>
C"I:l
t".>
i...
1=
;:;"
270 'S
270
.t
~
""I
~.
:2- 130
.!
tr.:l
00
n
o
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~
er
==
~5r
~
22~YPRESS~~~~~~~~~~D;r;iv;e;E;s;c;o;N;W~ith~H;o;T;L;in~k
ent in their system, the encoder/decoder present in
HOTLink can be bypassed through use of the
MODE pin on each part.
The serial data is connected to the fiber-optic transmitter using a differential connection from the
OUTA± differential output of the HOTLink transmitter. Because these are ECL/PECL signals, they
require a pull-down bias to allow the outputs to
switch.
An in-depth explanation of the operation and usage
of the HOTLink components may be found in the
CY7B923/933 datasheet and the HOTLink User's
Guide.
With a transmission rate of 200 Mbits/second, the
interconnect used for these signals should (in most
cases) be constructed as a controlled-impedance
transmission line. The bias network used on the
OUTA± signals is referred to as a Y-bias network.
It is designed to provide an equivalent transmission
line termination impedance of SOQ while providing
a bias level of V cc- 2Y.
Serial I/O Electrical Inteiface
The interface between the fiber-optic transceiver
and the HOTLink SERDES operates at 200 Mbits/
second. This interface is implemented with ECL
(Emitter~Coupled-Logic) signaling to provide a
low-noise, high-speed connection. Unlike standard
ECL, which is normally operated below ground,
both the fiber-optic transceiver and the HOTLink
SERDES components are operated above ground.
This allows the ECL portion of the design to use the
same +SV supply as the surrounding logic. When
ECL is operated from a positive supply it is referred
to as Positive-ECL or PECL.
The received serial data stream is output from the
fiber-optic receiver as a differential signal, as shown
in Figure 6, and is sent to the CY7B933 HOTLink receiver INA± inputs. A simplified schematic showing just the interconnect of the serial receive path is
shown in Figure 8. Because this is also a PECL signal, it should be treated in a manner similar to the
transmit serial path. This means controlled impedance transmission lines and a proper bias/termination network.
The source for the serial data stream is the
CY7B923 HOTLink transmitter shown in Figure 6.
A simplified schematic showing just the interconnect for the serial transmit path is shown in Figure 7.
While the receive-path bias/termination network
may be implemented using the same Y -bias network
used with the transmit serial path, a Tbevenin network is shown here. These two bias networks, when
used with differential signals, are effectively interchangeable. For single-ended signals requiring the
1+
5V
O.1IlF
OPTICAL
DRIVER
CY7B923
OUTA+ 1---4---+----1
OUTA- ~-4-+----+--9
L -_ _- - 1
OUTB+
OUTB-
OPTICAL
RECEIVER
DATA OUT
OUTC+ 1-------,
OUTC-
CY7B933
INA+
/DATA-OUT~----t-+---+---'-'IINA
SIG-DET
/SIG=DET
FROM
TRANSMITTER >--+-1------+--1--1------1 INB+
OUTC+
INB-(SI)
TO RECEIVER
INB+ f - - - - - - - +
Figure 7. HOTLink Transmitter-to-Optical
Serial Interface
Figure 8. Optical-to-HOTLink Receiver
Serial Interface
4-85
II
....... -, ~
Drive ESCON With HOTLink
,CYPRESS================================
same electrical characteristics, the Th6venin network must be used. For additional information on
terminating and biasing PECL signals, please see
the application note "HOTLink Design Considerations" in the HOTlink User's Guide.
and the INB+ input on the HOTLink receiver in a
single-ended PECL connection, as shown in Figures
6,7, and B.
While the best PECL connection is always a differential connection (like that used on INA±), the
usage of INB + in a single-ended mode is fine under
these conditions. Because the HOTLink transmitter and receiver are close together in the system and
operate from a common power supply, the normal
noise-margin concerns of single-ended connections
do not apply.
Serial I/O Support Interface
In addition to the transmit and receive serial data
streams, two other PECL signals are normally present in an ESCON interface: signal-detect and localloopback. The signal-detect function is performed
by the fiber-optic receiver. It outputs a PECL logic
signal to inform the upstream hardware if a valid signal is present or not. This signal is monitored to determine the synchronization state of the interface.
This localloopback functionality is selected through
the LOOPBACK signal on the pASIC FPGA.
When active (HIGH), this signal drives the
HOTLink receiver AlB select input LOW to selected the INB+ input for the deserializer, and
drives the FOTO input to the HOTLink transmitter
HIGH. This FOTO pin is used to disable the
OUTA± and OUTB± outputs of the transmitter.
This is normally done during loopback diagnostics
to prevent the diagnostic data from being interpreted at the other end of the fiber-optic link.
Because this is a PECL-Ievel signal, it is necessary
to convert it to a TTL-level signal for use by upstream logic. While there are components available
that explicitly perform this level translation, they
are not necessary for this application. Instead it is
possible to use one of the design features of the
HOTLink receiver INB± inputs to perform this
signal-level conversion.
ESCON Protocol Controller
The INB± input can be configured as either a differential PECL receiver (like INA±), or as a single-ended serial PECL receiver and a PECL-to-TTL converter. To use INB± as a differential receiver it is
necessary to pull the SO (Status Out) pin to Vee.
This disables the PECL-to-TTL converter and
maintains both inputs as a differential pair.
The control of the serial data stream is performed
using a pASIC383 FPGA. This part has been programmed to manage both the transmit and receive
serial data streams. The programming and verification were done using VHDL (VHSIC Hardware
Description Language) using Cypress's Wa7p3 '"
logic synthesis and simulation tools. Complete
source code of the design VHDL modules is listed
in Appendixes A through H of this application note,
and is available for download from the Cypress Bulletin Board system.
To use INB± as two separate inputs requires that
the SO pin be loaded as a normal TTL-level output.
When configured this way the INB- pin is the input
for the PECL-to-TTL converter, with SO being the
TTL output. This is the configuration used in Figures 6 andB.
The design shown in this application note is effectively a logic replacement for a Triquint GA9104
ESCON protocol chip. Due to the flexibility of the
pASIC family of parts, it is possible to add, replace,
or remove logic that is not optimal for a specific application. In this design, the 8B/lOB encoders present in the normal GA9104 were not implemented in
the pASIC383 because they are already present in
the HOTLink CY7B923/933. This allowed the entire functionality to be duplicated in a 2K-equivalent
gate FPGA. The functions present in this design are
Most ESCON interfaces are also equipped with numerous self-diagnostic capabilities. At the physical
interface the most common is a selectable loopback
of the serial data stream. This allows all components (with the exception of the fiber-optic transceiver) of the interface to be tested by transmitting
data and verifying that it can be properly received.
This loopback function is normally implemented using the OUTC+ output of the HOTLink transmitter
4-86
~ "' ~
Drive ESCON With HOTLink
~~CYPRESS==================================
neously presented to the CRC register, the parity
checker, and the output multiplexers. At the next
rising edge of the transmit clock, this data byte is
clocked into the CRC register, checked for proper
parity, and loaded into the output register along
with TSC D set LOW.
• Transmit Path
input and output pipeline registers
parity checker and status bit
CRC generator and control state machine
Command/data mux
Command translator
The detection of a parity error is only a reported
event, and occurs one cycle after the data (or command) is latched into the input register. Recovery
from detected parity errors would normally require
abnormal termination of the current frame using
the Abort delimiter.
• Receive Path
input and output pipeline registers
CRC checker, control state machine, and
status bit
parity generator
Command/data mux
Command translator
The CRC/MUX Control block is the heart of the
transmit path logic. It monitors the CTXCO line to
determine when to
II
• preset the CRC register
• Byte-Sync State Machine
• accumulate a CRC
Transmit Path
• output the CRC bytes
A block diagram of the transmit path is shown in Figure 9. Data is captured into a lO-bit register on each
rising edge of the transmit clock (CKW). The data
consists of an 8-bit data byte, a single control line
(CTXCO), and a parity bit. The CTXCO line is used
to identify whether the data on the inputs is a command code (HIGH) or a data byte (LOW). If the
latched character is a data byte, the data is simulta-
CTXCO
CTXD 8
• translate/send command codes
This block is implemented as a simple shift register
that tracks the current and previous three states of
CTXCO. These sixteen possible combinations (with
don't care states removed) and their resulting outputs are listed in Table 2. The VHDL source code
for this block is listed in Appendix C.
COMMAND
TRANSLATE
8
8 TXD
CTXP
TSC D
CKW
PERR
Figure 9. pASIC 'Iransmit Path Block Diagram
4-87
,~
ffiK
Drive ESCON With HOTLink
~'CYPRESS================================
Table 2. Transmit Path Control
CTXCO
Mux Select!
t+3 t+2 t+l t+O
CRC Control
X
X
X
0 Data
0
1 CRC High Byte
X
0
0
0
1
1 CRC Low Byte
X
X
1
1 Preset CRC
0
1 Command
X
1
1
0
1
1 Command
character set. For ESCON implementations this
logic could be simplified because only half of these
(six) are actually allowed for use in ESCON ordered
sets. The VHDL source code for this function is
listed in Appendix D.
The last section in the transmit path is the output
pipeline register. This block receives the multiplexed output of either the input pipeline register,
the high-CRC byte, the low-CRC byte, or the translated command. It serves to keep the data presented to the HOTLink transmitter synchronous
with the transmit clock.
The CRC block implements the CRC-16 function in
a byte-parallel fashion. This allows a full byte to be
accumulated in a single clock cycle. While this does
require a much larger number of XOR gates to implement than a serial CRC function, it allows the design to be constructed from much slower logic. Here
the main CRC register is clocked at 20 MHz, rather
than having to operate at a 200-MHz bit-clock rate.
The VHDL source code for this function is listed in
AppendixB.
Receive Path
A block diagram of the receive path is shown in Figure 10. Data is captured from the HOTLink receiver
into the input register on each falling edge of the
HOTLink recovered receive clock (CKR). Note
that this could also be implemented using a rising
edge clock, but that a falling edge clock was used for
compatibility with the implementation being replaced.
All received data characters are clocked into the
CRC register. Like the transmit path, this function
is implemented in a byte-parallel form. The CRC
register is synchronously preset if any command
code is present in the input register. For all data
codes it accumulates the CRC remainder.
The command-translate block is not normally needed for new designs. For this specific design it was
necessary to translate an existing set of command
codes to the native HOTLink command set. This
translation is quite simple with the logic reduction
performed manually for the transmit path. Here an
8-bit input command is decoded into a 4-bit command field (with the upper four bits of the byte set
to zero).
The CRC register is constantly compared for the
x'lDOF' pattern. The output of this compare is
clocked into the output register. It is forced to a
LOW for all clocks except the first command character received following a data character. This CRC
status remains valid for only one clock cycle. The
The translation block actually implements circuitry
to translate all twelve command codes in the 8B/lOB
RSC_D
a:
RXQ
8
LJ.I
I-
m
a:
CRXS1
m
CRXSO
8 CRXD
LJ.I
I-
8
C5
LJ.I
8
a:
=>
a.
C5
LJ.I
a:
=>
l-
l-
~
l:=O
CKR
Figure 10. pASIC Receive Path Block Diagram
4-88
~
0
CRXP
~
=:t
~
Drive ESCON With HOTLink
~; CYPRESS = = = = = = = = = = = = = = = =
VHDL source code for this function is listed in AppendixE.
tected that is generated by the fiber-optic receiver.
Sufficient I/O and logic resources are still available
in the FPGA to add this into the state machine
equations.
Just as in the transmit path, a command translation
block is present in the design. This command translate block is not normally needed for new designs.
For this specific design it was necessary to translate
an existing set of command codes from the native
HOTLink command set to a different set of command codes embedded in upstream logic. This
block allows the HOTLink command codes to be
translated to any host command set.
Design Summary
The small size of the FPGA design is made possible
by the enhanced functionality present in the HOTLink transmitter and receiver. This removes the
need to design and implement the 8B/lOB encoders
and decoders, and provides full received character
validation. The embedded PECL-to-TTL converter
also allows a small footprint by removing the need
for an external conversion circuit.
The translation block actually implements circuitry
to translate all twelve command codes in the 8B/10B
character set. For ESCON implementations this
logic could be simplified because only half of these
(six) are actually allowed for use in ESCON ordered
sets. The VHDL source code for this function is
listed in Appendix D.
The VHDL design both auto-routes and autoplaces into a pASIC383 FPGA. Because of the highspeed operation of the pASIC cells and interconnect, this design meets or exceeds all design
performance parameters, over worst case temperature and voltage, using the slow - 0 speed bin of the
pASIC383.
Odd parity is generated on the output data byte and
the CRXSO status bit. This allows upstream logic to
validate that the byte received is the same as that
generated by the pASIC FPGA.
The 100% routability of the pASIC family allows the
circuit board signal routing to be improved by selecting pins that best match the system interconnect.
The pinouts listed in the top-level VHDL file were
selected to allow straight-through routing (no crossovers) of the signals between the FPGA and the
HOTLink transmitter and receiver. In addition, the
The last block in the receive section is the output
pipeline register. This block receives the multiplexed output of either the input pipeline register or
the translated command. It serves to keep the data
presented to the upstream logic synchronous with
the receive clock.
"'
L
Byte-Sync State Machine
A block diagram of the byte-sync state machine is
shown in Figure 11. The two primary structures in
the machine are a 4-bit counter and a controlling
state machine. The controlling state machine is programmed to follow the state diagram shown in Figure 11. It tracks the state of the RVS signal from the
receiver and a decode from the input register of all
C5.0 command codes (Idle characters). The fourbit counter is used to alternately count either valid
characters (the absence of RVS) or valid Idle characters, based on the state of the machine.
A f------J
B f---/
RESET
BYTE- c - SYNC
STATE
MACHINE
IDLE
-
--.t::,)
Cf------J
D f---/
L
,J
EN
[>R 4-BIT
~
CNTR
.-R RVS
-
DQ
~>
-
The present form of this state machine was designed
to duplicate the functionality of a previous implementation. Because of this it does not take into account the the additional condition of Signal De-
1
1-0:
:::lW
Il..I-
I-~
i'
:::lC!l
OW
0:
'------
CKR
Figure 11. Byte-Sync State Machine
Block Diagram
4-89
BSYNC
ERROR
. .~
Drive ESCON With HOTLink
~'CYPRESS============
placement of the HOTLink transmitter and receiver were selected to line up with the transmit and receive halves of the fiber-optic transceiver. This pinout selection and interconnect are shown in
Figure 12.
Conclusions
The ESCON interface is both an elegant and powerful replacement for the older block-mux channels.
The use of the HOTLink serializer/deserializer
components to implement an ESCON interface
guarantees both compliance with the 8B/10B coding
rules and all jitter and timing specifications of the
ESCON interface.
Due to the high-speed operation of the ESCON interface, the byte-level control is best implemented
in hardware. The flexibility of the VHDL language
and the unlimited routing of the Cypress pASIC
family of FPGAs make them a perfect choice for
building the control state machines. While only the
lower level of the ESCON protocol is controll~d in
the design documented here, much of the higher level control may also be implemented through the use
of either larger or additional FPGA components.
CY7C383A-O
o
z
References
C!l
1. ESCON I/O Inteiface, IBM, 1990, 1991
2. HOTLink User's Guide, Cypress Semiconductor, 1995
-'
m
3. GA9104 Datasheet, 1tiquint Semiconductor,
Inc, 1992
~I
Figure 12. HOTLink/pASIC Pinout
and Interconnect
Warp3 and HOTLink are trademarks of Cypress Semiconductor
pASIC is a trademark of QuickLogic
ESCON is a trademark of International Business Machines, Inc.
IBM is a registered trademark of International Business Machines, Inc.
4-90
1& .,-:z
Drive ESCON With HOTLink
7CYPRESS = = = = = = = = = = = = = =
Appendix A. Top-Level pASIC Code
ESCON Interface Control PLD
Equivalent to the Triquint GA9104 but designed for operation
with the Cypress Semiconductor HOTLink chipset
ENTITY esc_top IS PORT (
transmit path byte clock
txclk: IN BIT;
rxclkA: IN BIT;
receiver path byte clock
rxclkB: IN BIT;
receiver path byte clock
resetn: IN BIT;
active low reset
rxq: INOUT X01Z_VECTOR(0 TO 7);
HOTLink receiver data in
rsc_d: INOUT X01Z;
HOTLink receiver SC/D
r_rvs: INOUT X01Z;
HOTLink receiver RVS
txd: INOUT X01Z_VECTOR(0 TO 7);
HOTLink transmitter data out
tsc_d: INOUT X01Z;
HOTLink transmitter SC/D
crxd: INOUT X01Z_VECTOR(0 TO 7);
receive path data output
ctxd: INOUT X01Z_VECTOR(0 TO 7);
transmit path data input
crxsO: INOUT X01Z;
receive status 0 (command/data)
crxs1: INOUT X01Z;
receive status 1 (CRC)
ctxcO: INOUT X01Z;
transmit control 0 (command/data)
byte sync acquired
bsync: INOUT X01Z;
error: INOUT X01Z;
receive bad character error
perr: INOUT X01Z;
transmit-in parity error
crxp: INOUT X01Z;
odd parity output
ctxp: INOUT X01Z;
odd parity input
loopen: INOUT X01Z;
local loopback enable
ab_sel: INOUT X01Z) ;
receiver A/B select
ATTRIBUTE part_name OF esc_top:ENTITY IS "C383A";
ATTRIBUTE pin_numbers OF esc_top:ENTITY IS
"txclk:17 rxclkA:53 rxclkB:54 resetn:50 rxq(7) :44 rxq(6) :43 "
& "rxq(5) :42 rxq(4) :41 rxq(3) :40 rxq(2) :39 rxq(l) :38 rxq(O) :37 "
& "rsc_d:36 r_rvs:45 txd(7) :34 txd(6) :33 txd(5) :32 txd(4) :31 "
& "txd(3) :30 txd(2) :29 txd(l) :28 txd(O) :27 tsc_d:26 crxd(O) :62 "
& "crxd(l) :61 crxd(2) :60 crxd(3) :59 crxd(4) :58 crxd(5) :57 "
& "crxd(6) :56 crxd(7) :55 ctxd(O) :15 ctxd(l) :14 ctxd(2):13 "
& "ctxd(3) :12 ctxd(4):11 ctxd(5) :10 ctxd(6):9 ctxd(7):8 "
& "crxsO:63 crxs1:64 ctxcO:21 bsync:65 error:66 perr:7 "
& "crxp:49 ctxp:6 loopen:47 ab_sel:46";
USE
USE
USE
USE
USE
work.cypress.all;
work.rtlpkg.all;
work.memorypkg.all;
work.ttlpkg.all;
work.registerpkg.all;
4-91
Drive ESCON With HOTLink
Appendix A. Top-Level pASIC Code (continued)
USE
USE
USE
USE
USE
USE
USE
USE
USE
USE
USE
work.iopkg.all;
work.mcpartspkg.all;
work.gatespkg.all;
work.resolutionpkg.all;
work.bv_math.all;
work.crc_t.all;
work.crc_r.all;
work.crc_ctl.all;
work.sync_det.all;
work.tri~code.all;
work.iopluspkg.all;
used to double-buffer
allow use of INV function
add in CRC transmit function
add in CRC receive function
add in transmit CRC control machine
add in SYNC detect state machine
add in command decoder section
add in enhanced I/O buffers
ARCHITECTURE escon_top OF esc_top IS
-- add internal signal equivalents of
SIGNAL tclk : BIT;
SIGNAL rclk : BIT;
SIGNAL reset : BIT;
SIGNAL HL_rx : BIT_VECTOR(O to 7);
SIGNAL HL_rsc_d : BIT;
SIGNAL HL_r_rvs : BIT;
SIGNAL HL_tx : BIT_VECTOR(O to 7);
SIGNAL HL_tsc_d : BIT;
SIGNAL HL_tsc_q : BIT;
SIGNAL sync_r : BIT;
SIGNAL c_rxd : BIT_VECTOR(O to 7);
SIGNAL c_txd : BIT_VECTOR(O to 7);
SIGNAL c - rxsO
BIT;
BIT;
SIGNAL c - rxsl
BIT;
SIGNAL c - txcO
BIT;
SIGNAL b_sync
SIGNAL r - error : BIT;
BIT;
SIGNAL p-err
SIGNAL c_rxp : BIT;
SIGNAL c_txp : BIT;
SIGNAL b_Ioopen : BIT;
signals after I/O pads
transmit clock
negative edge receiver clock
reset controller
HOTLink receiver data bus
HOTLink receiver SC/D
HOTlink receiver RVS
HOTLink transmitter data bus
HOTLink transmitter SC/D
clocked HOTLink transmitter SC/D
receiver byte sync
controller receive path data out
controller transmit path dataout
receive status 0 (command/data)
receive status 1 (CRC)
transmit control 0 (command/data)
byte sync acquired
receive bad character error
parity error
odd parity output
odd parity input
buffered loop enable
-- transmit internal signals
SIGNAL t_data : BIT_VECTOR(O TO 7);
SIGNAL t_mux : BIT_VECTOR(O TO 7);
SIGNAL t_comm : BIT_VECTOR(O TO 7);
SIGNAL tp_odd : BIT;
SIGNAL t-parity : BIT;
transmit data bus
muxed transmit data path
re-encoded transmit commands
transmit data parity input
transmit parity checker output
4-92
Drive ESCON With HOTLink
Appendix A. Top-Level pASIC Code (continued)
SIGNAL t - CRC : BIT_VECTOR(O TO 7);
SIGNAL c - txc - 0 : BIT;
SIGNAL mux_hi : BIT;
SIGNAL mux_Iow : BIT;
sIGNAL ctxc3 : BIT;
SIGNAL t_CRC_reset : BIT;
-- receive internal signals
SIGNAL r_data : BIT_VECTOR(O TO 7);
SIGNAL r_mux : BIT_VECTOR(O TO 7);
SIGNAL rp_odd : BIT;
SIGNAL rcom_data : BIT;
SIGNAL r_com_data: multi_buffer BIT;
SIGNAL r_crc_err : BIT;
SIGNAL r_CRC_d : BIT;
SIGNAL rvs : BIT;
SIGNAL sync : BIT;
SIGNAL t_code : BIT_VECTOR(O to 7);
transmit CRC vector
transmit command/data
enable HI/LOW transmit CRC byte
enable LOW transmit CRC byte
3x registered c_txc_O
preset transmit CRC register
registered receiver data bus
muxed data and translated commands
receive data parity output
registered SC/D pin
double buffered registerd SC/D pin
un-registered CRC status
CRC check D-input
registered RVS signal
decoded K28.5 signal
Triquint pattern for K-codes
BEGIN
-- instantiate pASIC buffers/drivers on I/O signals
-- clocks
pl: CKPAD PORT MAP (txclk, tclk);
-- transmit path clock
p2: HDI2PAD PORT MAP (rxclkA, rxclkB, rclk);
receive path clock on
-- on negative edge
-- high drive pads
p3: HDIPAD PORT MAP (resetn ,reset);
active HIGH system reset
-- data buses
-- HOTLink receiver data bus (input)
p4:
INPAD PORT MAP (rxq(O) , HL_rx(O)) ;
p5:
INPAD PORT MAP (rxq(l) , HL_rx(l)) ;
p6: INPAD PORT MAP (rxq(2) , HL_rx(2)) ;
p7:
INPAD PORT MAP (rxq(3) , HL_rx(3)) ;
p8: INPAD PORT MAP (rxq(4) , HL_rx(4)) ;
p9: INPAD PORT MAP (rxq(5) , HL_rx(5)) ;
plO: INPAD PORT MAP (rxq(6) , HL_rx(6)) ;
pll: INPAD PORT MAP (rxq(7) , HL_rx(7));
pl2: INPAD PORT MAP (rsc_d,
HL_rsc_d) ;
receive SC/D
pl3: INPAD PORT MAP (r_rvs, HL_r_rvs) ;
RVS
-- HOTLink transmitter data bus (output)
pl4: OUT PAD PORT MAP (HL_tx(O) , txd(O)) ;
pl5: OUT PAD PORT MAP (HL_tx(l) , txd(l)) ;
pl6: OUT PAD PORT MAP (HL_tx(2) , txd(2)) ;
pl7: OUT PAD PORT MAP (HL_tx(3) , txd(3)) ;
pl8: OUTPAD PORT MAP (HL_tx(4) , txd(4)) ;
pl9: OUT PAD PORT MAP (HL_tx(5) , txd(5)) ;
4-93
I
1&rc
Drive ESCON With HOTLink
CYPRESS = = = = = = = = = = = = = =
Appendix A. Top-Level pASIC Code (continued)
p20: OUT PAD PORT MAP (HL_tx(6) , txd(6» ;
p21: OUT PAD PORT MAP (HL_tx(7) , txd(7» ;
p22: OUT PAD PORT MAP (HL_tsc_q, tsc_d) ;
-- controller transmit data bus (input)
p24: INPAD PORT MAP (ctxd(O) , c_txd(O» ;
p25: INPAD PORT MAP (ctxd(l) , c_txd(l» ;
p26: INPAD PORT MAP (ctxd(2) , c_txd(2»;
p27: INPAD PORT MAP (ctxd(3) , c_txd(3» ;
p28: INPAD PORT MAP (ctxd(4) , c_txd(4) ) ;
p29: INPAD PORT MAP (ctxd(5) , c_txd(5» ;
p30: INPAD PORT MAP (ctxd(6) , c_txd(6) ) ;
p31: INPAD PORT MAP (ctxd (7) , c_txd(7»;
-- controller receiver data bus (output)
p34: OUTPAD PORT MAP (c_rxd(O) , crxd(O»;
p35: OUT PAD PORT MAP (c_rxd(l) , crxd(l) ) ;
p36: OUTPAD PORT MAP (c_rxd(2) , crxd(2»;
p37: OUT PAD PORT MAP (c_rxd(3) , crxd(3» ;
p38: OUT PAD PORT MAP (c_rxd(4) , crxd(4» ;
p39: OUT PAD PORT MAP (c_rxd(5) , crxd(5) ) ;
p40: OUT PAD PORT MAP (c_rxd(6) , crxd(6» ;
p41: OUT PAD PORT MAP (c_rxd(7) , crxd(7) ) ;
-- misc input pads
p44: INPAD PORT MAP (loopen, b_loopen);
loopback enable
p45: INPAD PORT MAP (ctxcO, c_txcO);
transmit control 0
p49: INPAD PORT MAP (ctxp, c_txp);
odd parity input
-- misc output pads
p50: OUTPAD PORT MAP (c_rxsO, crxsO);
receiver status 0 output
p51: OUT PAD PORT MAP (c_rxsl, crxsl);
receiver status 1 output
p53: OUT PAD PORT MAP (b_sync, bsync);
byte sync acquired
p54: OUTPAD PORT MAP (r_error, error);
received bad character
p55: OUT PAD PORT MAP (p_err, perr);
parity error
p56: OUTPAD PORT MAP (c_rxp, crxp);
odd parity output
p57: OUTPAD PORT MAP (INV(b_loopen),ab_sel); -- HOTLink receiver AlB select
-------------- TRANSMIT PATH ----------------------------------------------- add in transmit path input data
tla: DFF PORT MAP (c_txd(O) , tclk,
tlb: DFF PORT MAP (c_txd(l) , tclk,
tic: DFF PORT MAP (c_txd(2) , tclk,
tid: DFF PORT MAP (c_txd(3) , tclk,
tie: DFF PORT MAP (c_txd(4) , tclk,
tlf: DFF PORT MAP (c_txd(5) , tclk,
tlg: DFF PORT MAP (c_txd(6) , tclk,
tlh: DFF PORT MAP (c_txd(7) , tclk,
pipeline register
t_data(O» ;
t_data(l» ;
t_data(2» ;
t_data(3» ;
t_data(4» ;
t_data(5» ;
t_data(6» ;
t_data(7» ;
4-94
Drive ESCON With HOTLink
Appendix A. Top-Level pASIC Code (continued)
-- add parity and control bits
t1j: DFF PORT MAP (c_txp, tclk, tp_odd);
t1k: DFF PORT MAP (c_txcO, tclk, c_txc_O);
-- add transmit data parity checker (10 bit parity tree)
t-parity <= NOT(t_data(O) XOR t_data(l) XOR t_data(2) XOR t_data(3)
XOR t_data(4) XOR t_data(5) XOR t_data(6) XOR t_data(7)
XOR tp_odd XOR c_txc_O);
-- add parity check F-F
t2: DFF PORT MAP (
t-parity,
tclk,
p_err) ;
-- add transmitter CRC generator
t3: crc_tx PORT MAP (
tclk,
t_CRC_reset,
c_txc_O,
mux_hi,
t_data,
t_CRC) ;
parity of inputs
transmit clock
output parity status
transmit clock
from tx CRC control state machine
from tx input register
enable low byte onto bus
transmit data bus
8-bit transmit CRC output vector
-- add transmit output register
t5a: DFF PORT MAP (t_mux(O) , tclk, HL_tx(O»;
t5b: DFF PORT MAP (t_mux(l), tclk, HL_tx(l»;
t5c: DFF PORT MAP (t_mux(2), tclk, HL_tx(2»;
t5d: DFF PORT MAP (t_mux(3), tclk, HL_tx(3»;
t5e: DFF PORT MAP (t_mux(4), tclk, HL_tx(4»;
t5f: DFF PORT MAP (t_mux(5), tclk, HL_tx(5»;
t5g: DFF PORT MAP (t_mux(6), tclk, HL_tx(6»;
t5h: DFF PORT MAP (t_mux(7), tclk, HL_tx(7»;
HL_tsc_d <= (mux_low AND c_txc_O) OR
(c_txc_O AND mux_hi AND ctxc3);
-- add in SC/D output bit
t5j: DFF PORT MAP (HL_tsc_d, tclk, HL_tsc_q);
-- add in transmit CRC supervisor machine
-- contains the double pipelined C/D bit
t6: tx_ctl_crc PORT MAP (
tclk,
transmit clock
c_txc_O,
registerd command/data control bit
mux_hi,
registered c_txc_O
mux_low) ;
2x registered c_txc
°
4-95
I
&_~CYPRESS = = = = = = = =
Drive ESCON With HOTLink
======
Appendix A. Top-Level pASIC Code (continued)
-- transmit path data/command/CRC mux
t8: PROCESS (c_txc_O, mux_low, mux_hi)
BEGIN
IF (c_txc_O = '0') THEN
t_mux <= t_data;
ELSIF (c_txc_O = '1' AND «mux_low = '0' AND mux_hi='O') OR
(ctxc3 = '0' AND mux_low = '0' AND mux_hi = '1'))) THEN
-- output CRC bytes
t_mux <= t_CRC;
ELSE
-- output re-encoded command codes
t_mux <= t_comm;
END IF;
END PROCESS t8;
-- Add in transmit command decoder
t9: t_decode PORT MAP (t_data, t_comm); -- translate to HOTLink commands
-------------- RECEIVE PATH ------------------------------------------------ add in receive path input data pipeline register
r1a: DFF PORT MAP (HL_rx(O) , rclk, r_data(O));
r1b: DFF PORT MAP (HL_rx(l) , rclk, r_data(l));
r1c: DFF PORT MAP (HL_rx(2) , rclk, r_data(2));
r1d: DFF PORT MAP (HL_rx(3) , rclk, r_data(3));
r1e: DFF PORT MAP (HL_rx(4) , rclk, r_data(4));
r1f: DFF PORT MAP (HL_rx(5) , rclk, r_data(5));
r1g: DFF PORT MAP (HL_rx(6) , rclk, r_data(6));
r1h: DFF PORT MAP (HL_rx(7) , rclk, r_data(7)); -- add SC/D bit and RVS
r1j: DFF PORT MAP (HL_rsc_d, rclk, rcom_data); -- registerd SC/D
r1k: DFF PORT MAP (HL_r_rvs, rclk, rvs);
-- registered RVS signal
-- create double buffered signals
db1: BUF PORT MAP (rcom_data, r_com_data);
db2: BUF PORT MAP (rcom_data, r_com_data);
-- receive path output register
r2a: DFF PORT MAP (r_mux(O) , rclk, c_rxd(O));
r2b: DFF PORT MAP (r_mux(l), rclk, c_rxd(l));
r2c: DFF PORT MAP (r_mux(2) , rclk, c_rxd(2));
r2d: DFF PORT MAP (r_mux(3) , rclk, c_rxd(3));
r2e: DFF PORT MAP (r_mux(4) , rclk, c_rxd(4));
r2f: DFF PORT MAP (r_mux(5) , rclk, c_rxd(5));
r2g: DFF PORT MAP (r_mux(6) , rclk, c_rxd(6));
r2h: DFF PORT MAP (r_mux(7), rclk, c_rxd(7));-- command/data bit and rvs
r2j: DFF PORT MAP (r_com_data, rclk, c_rxsO);
r2k: DFF PORT MAP (rvs, rclk, r_error);
4-96
AppendixA. Top-Level pASIC Code (continued)
-- add receive parity generate
r3: TTL180 PORT MAP (
r_rnux(O) , r_ffiux(l) , r_mux(2) , r_mux(3), r_mux(4) , r_mux(5) ,
r_rnux(6) , r_mux(7) , INV(r_com_data), r_com_data, rp_odd, open);
r3a: DFF PORT MAP (rp_odd, rclk, c_rxp);
-- add in receive CRC block
r4: crc rx PORT MAP (
rclk,
r_corn_data,
r_data,
r_crc_err) ;
receive path clock
enable only for data bytes
receiver data bus
receive path crc status
-- add CRC check register
r5: DFF PORT MAP (r_CRC_d, rclk, c_rxs1);
r_CRC_d <= r_crc_err AND r_com_data AND (NOT(c_rxsO));
-- add in byte-sync state machine
r6: byte_syn PORT MAP (
rclk,
receiver clock
reset,
system reset
rvs,
receiver RVS signal
sync,
decoded k28.5
b_sync) ;
byte sync acquired
sync <= '1' WHEN (r_com_data='l' AND r_data(O TO 3)="1010") ELSE '0';
-- add command transposition logic and mux
r7: PROCESS (r_corn_data, r_data(O) , r_data(l) , r_data(2) , r_data(3))
BEGIN
IF (r_com_data='O') THEN
r_mux <= r_data;
ELSE
r_mux <= t_code;
-- add in command decoder
END IF;
END PROCESS r7;
-- add receiver path command encoder
-- t_code is output vector
r8: t_encode PORT MAP (
r_data,
HOTLink data bus
t_code) ;
decoded Triquint commands
END escon_top;
4-97
I
1I-~
Drive ESCON With HOTLink
~ CYPRESS ==============
Appendix B. Transmit Path CRC Generator
transmit 16-bit CCITT CRC for use in data mover
When sequencing bytes out, the qt(15)-qt(8) byte must be sent out first.
Per the ESCON spec, the CRC is the l's compliment (inversion) of the
qt[15:0] bus.
PACKAGE crc_T IS
COMPONENT crc_tx PORT
clk,
preset: IN
BIT;
enable: IN
BIT;
mux_hi: IN
BIT;
BIT_VECTOR
dt:
IN
BIT_VECTOR
IF ((ent="!!!!") AND (error='O')) THEN
s_state <= state!;
ELSE
s_state <= stateO;
END IF;
WHEN state! =>
IF (error='l') THEN
s_state <= state2;
ELSE
s_state <= state!;
END IF;
WHEN state2 =>
IF (error='!') THEN
s_state <= state3;
ELSIF (ent="llll") THEN
s_state <= state!;
ELSE
s_state <= state2;
END IF;
WHEN state3 =>
IF (error='!') THEN
s_state <= state4;
ELSIF (ent="llll") THEN
s_state <= state2;
ELSE
s_state <= state3;
END IF;
WHEN state4 =>
IF (error='l') THEN
s_state <= stateO;
ELSIF
(ent="!!!!") THEN
s_state <= state3;
ELSE
s_state <= state4;
END IF;
WHEN others =>
s_state <= stateO;
END CASE;
END IF;
END PROCESS proe!;
4-107
I
~~
Drive ESCON With HOTLink
W,CYPRESS = = = = = = = = = = = = = = = =
Appendix F. Byte Sync Controller (continued)
-- build 4-bit counter with enable and reset
ctr_en <=
'1' WHEN ((s_state=stateO AND reset='O' AND sync='l')
OR (s_state=state2)
OR (s_state=state3)
OR (s_state=state4))
ELSE '0';
ctr_reset <= '1' WHEN ((reset=' 1') OR (error=' 1')) ELSE '0';
-- add standard counter module
ctr1: cntr4 PORT MAP (
one,
open,
ctr_en,
zero,
zero, zero, zero, zero,
clk,
ctr_reset,
cnt (3), cnt (2),
cnt(l), cnt(O)
-- contains the 4 bits of ctr1
set carry in always active
carry out unused
counter enable
never load this counter
load inputs are not used
counter clock
will need to expand this signal
counter holding register inputs
) ;
-- assign output
bbsync <= '0' WHEN (s_state=stateO) ELSE '1';
d1: DFF PORT MAP (bbsync, clk, bsync);
END arch1;
4-108
~~
Drive ESCON With HOTLink
_'CYPRESS
================
Appendix G. I/O Support
IOPLUS.VHD
Create enhanced I/O buffer that is not part of the io.vhd
package for the pASIC 380 family
PACKAGE iopluspkg IS
COMPONENT HDI2PAD PORT
pO
IN BIT;
pl : IN BIT;
qn : OUT BIT) ;
END COMPONENT;
END iopluspkg;
USE
USE
USE
USE
work.cypress.all;
work.rtlpkg.all;
work.iopkg.all;
work.resolutionpkg.all;
I
ENTITY HDI2PAD IS PORT (
pO
IN BIT;
pl : IN BIT;
qn : OUT BIT);
END HDI2PAD;
ARCHITECTURE archHDI2PAD OF HDI2PAD IS
SIGNAL
0
:
multi_buffer BIT;
BEGIN
uO: PAINCELL PORT MAP
ul: PAINCELL PORT MAP
ip => pO, ini =>
ip => pl, ini =>
qn <= 0;
END archHDI2PAD;
4-109
0,
0,
iz => OPEN);
iz => OPEN);
Replace Your TAXI ™ -125 and TAXI -175
This application note will explain how to replace
TAXIchip'" devices with the HOTLink devices
from Cypress Semiconductor. This note begins with
an introduction to HOTLink and then gives advantages and replacement suggestions for the
TAXI -125 and TAXI -175 devices.
TM
HOTLink Introduction
The HOTLink family of devices transfers data from
point to point over high-speed serial links at 160 to
330 Mbits/second (Figure 1). The CY7H923 Transmitter (Figure 2) takes an 8-bit parallel data stream
and encodes it using the Fibre Channel compliant
~
16b-330',Mbnts
_________ _c..0pper O!: ~i~!r_ _______ :
and ESCON™ -compliant 8H/lOH code. This code
maps a1l8-bit data characters into a 10-bit transmission code that insures the transmission signal contains suitable transitions for recovery by the receiving device. The transmitter takes this lO-bit data
word and converts it to a serial bit-stream and transmits it at 10 times the byte rate over a serial transmission link.
The CY7H933 HOTLink Receiver (Figure 3) lies on
the other end of a transmission link that may consist
of anything from a few inches of printed circuitboard trace to several kilometers of fiberoptic cable.
The receiver decodes the incoming bit stream and
reconstructs the original parallel data character,
which is presented at the outputs aligned with the recovered clock. The receiver, in addition to these
tasks, checks the incoming data stream for errors
that may have occurred in the serial transmission.
The SC/i") (Special Character!Data) pin provides
the ability to transmit command codes in addition to
sending data characters. These codes are mapped
Figure 1. CY7B923 Transmitter Logic Diagram
RF
AlB -----. hJ=~==~!::~=~
INA+
INA-
so
REFCLK _ _ _---I
MODE
BlS1'EN
SCIO (0.)
Figure 3. CY7B933 Receiver Logic Diagram
Figure 2. CY7B923 Transmitter Logic Diagram
4-110
S£
~YPRESS~~~~~~~~R~e~PI~a~Ce~Y4~O~U~r~TAX~I~-~1~2~5~an~d~T~~~~-~1~75
to lO-bit transmission characters defined in the
8B/lOB codes of the Fibre Channel standard. This
provides the ability to send commands as part of the
transmission stream signaling events such as Idle,
Start-of-frame, End-of-frame, etc.
Other features include Built-In Self-Test for in-system diagnostic testing, unencoded mode for sending
lO-bit data in systems that use a different encoding
method, and a seamless parallel interface for connection with both asynchronous and clocked FIFOs.
A brief description of the various features of HOTLink is given below with a more detailed discussion
found in the CY7B923/CY7B933 HOTLink Transmitter/Receiver datasheet. The PLCC pinouts for
these devices are shown in Figure 4.
Replacement of TAXI -1 Devices
The following section shows how to upgrade a system using the TAXI -1 (Am7968/Am7969-12S or
PLCC
Top View
+
I I
++
I
8~~~ ~~~
> 000000
BlSTEN
I'W
Vcca
SVS (Dj)
(Dh) D7
78923
U)Ll)'<:!"(")C\I
....
The Am7968/AM7969 provide a method of connecting systems over a serial link. These devices accept 8-, 9-, or lO-bit parallel data words on the transmitting side of the link (Figure 5) and convert the
data to a serial bit stream using 4B/SB and SB/6B
NRZI (Non Return to Zero, Invert on Is) codes.
These codes convert 4 input bits into S transmission
bits in the case of the 4B/SB code, or S input bits into
6 transmission bits in the case of the SB/6B code.
These codes insure that enough signal transitions
occur on the link for the receiving device to recover
the data. On the receiving end ofthe system (Figure
6), the serial data is decoded and presented to the
outputs along with the recovered transmitted clock.
The pinouts of the Am7968 TAXI Transmitter and
Am7969 TAXI Receiver are shown in Figure 7.
FOTO
Simplifying Your System with HOTLink
HOTLink offers an extensive feature list that provides a host of benefits when designing systems that
perform point-to-point serial communication.
Vcca
9
21
10
1112131415161718 19
Brief Description of TAXI -1
ENA
J:NN
GND
MODE
the Am7968/Am7969-17S) with HOTLink. This
section begins with a brief explanation of the
TAXI -1 devices. It then shows how HOTLink simplifies systems that either use, or plan to use, these
devices. It ends with a discussion on how to modify
systems that use some of the features of these TAXI
devices that are different from HOTLink.
CKW
GND
SC/l) (Dol
0
ClClClClClClCl
Data
Command
RF
GND
REFCLK
Vcca
IID"i' 7
7B933
SO
GND 8
CKR
VCCN 9
21
Vcca
GND
RVS(Oj)
(Oh) 0 7 o....;.'+T."TT'irT"rT.:;.;.:,.,:.:;-..r SC(i) (Ool
u)
LO"d"
C')
(\I ....
0
0000000
TLS
Figure 4. CY7B923 and CY7B933 Pin
Configurations
Figure 5. Am7968 Logic Diagram
4-111
I
~~
Replace Your TAXI -125 and TAXI -175
~_., CYPRESS
X1
X2
~l-r-L---L-~_CNB
10M
"---IF=::!...,. ClK
DSTRB
CSTRB
Data
Figure 6.
Command
Am7~69
Logic Diagram
PLCC
'ThpView
I
+
':;':;
a?a?~I<:", ... ",
~ ~~~ 000
Vcc2 (ECll
Vccl (TTl
VCC3R~~f
7
DMS
TlS
TSERIN -"';';'8imrnmrr-.r
DI2
Dll
DIO
GNDl (TTL)
GND2 (CMl)
Xl
X2
8
o~8 C58~
CI CI CI CI CI CI CI
IGM
RESET
6
Vccl /TTl)
Vcc2 (CMl)
SERIN+
SERINDMS o....:.:..oi:n:iUimtrr
D07
CNB
X2
Xl
GND2 (CMl)
GNDl (TTL)
ClK
While many of these features are offered in the
TAXI -1 devices, they are difficult to use. These
features include multiplexed command and data,
multiple inputs and outputs, self-test operation, and
many others. Below is a list of HOTLink features
and advantage offered to the system designer when
compared with the TAXI -1 devices.
Multiplexed Command and Data
One of the major differences between the HOTLink
and the TAXI devices is the parallel data interface.
The TAXI devices have separate inputs for command and data, while the HOTLink devices have an
integrated command and data path. An external
controller connected to the command inputs determines what command or data is to be sent. HOTLink determines if a Special Character (Command)
should be sent by the status on SC/D pin (Special
Character/Data).
The integrated command and data paths of HOTLink allow a simpler, more conventional controller
architecture. Instead of creating a separate command path, command codes can be integrated within the data stream and a ninth bit (the SC/Dbit) can
be added to indicate the status of the associated 8
bits of information.
More Serial Outputs
TAXI has one pair of differential ECL outputs. The
HOTLink transmitter has three identical differential Pseudo ECL (PECL) serial output ports, any
number of which can be disabled to conserve power.
Additionally, two of these outputs may be switched
off with the use of the FOTO (Fiberoptic 1l:ansmitter Off) pin. The AMD'" devices, on the other
hand, have only one differential PECL output pair.
The additional HOTLink outputs can be used in a
system to provide redundant data paths, for loopback testing, or for building complete networks
where a single transmitter is received by multiple receivers.
More Serial Inputs
The TAXI Receiver has a single pair of differential
inputs (SERIN ±). The HOTLink Receiver has
multiple interfaces to the serial transmission medium (INA± and INB±). As in the case of the
Figure 7. Am7968 and Am7969 Pin
Configurations
4-112
.zs-."..
~i~
Replace Your TAXI -125 and TAXI -175
HOTLink Transmitter, the additional media inputs
of the HOTLink Receiver can be used to provide
loop-back testing, redundant transmission paths, or
more complex network configurations. The TAXI
SERIN - is used to control Test Mode function of
the part. In addition to limiting the "in-circuit" test
ability of TAXI, this limits the common mode range
of the TAXI receiver.
of the transmitter to the the second input pair of the
receiver as shown in Figure 8, the system gains the
ability to perform a complete self-check upon system initialization or when an excessive amount of
errors are received over the transmission link.
HOTLink provides the ability to check the transmitting and receiving devices as well as the associated
serial transmission link.
Loop-back testing is easily accomplished with the
multiple media interface features of the HOTLink
devices. In a typical network-style configuration,
both a transmitter and a receiver will exist for each
node. By connecting one of the three output pairs
Neither complete system diagnostics nor integrated
loop-back testing can be accomplished with the
TAXI-1 devices. Many TAXI -1 based systems attempt this feature with single-ended EeL multi-
'CYPRESS
I
HOTLlNKTX
CKW
RP
HOTLlNKRX
BISTEN
MODE
FOTO
ENN
ENA
REFCLK
CKR
MODE
BISTEN
RF
RO
so
.....-....;AlB
SCID(Da)
DO(Db)
D1(Oo)
D2(Od)
D3(Oe)
D4(0))
D5(0I)
06(Og)
D7(Oh)
SVS(D))
OUTA+
OUTAOUTB+I------1
OUTB-I------1
'-------'
1------1INA+
SC/O(Oa)
1-----iINAOO(Ob)
'------'
Q1(Qc)
INB(INB+) 02(Od)
SI(INB-)
Q3(Oe)
04(01)
05(01)
06(Og)
07(Oh)
RVS(Oj)
r----f
DUTC+I-::=::::;;,
DUTC-I-
HOTLlNKRX
RVS(Oj)
07(Oh)
06(Og)
05(01)
04(01)
~~g~\ IN~~:::~~""--'"
01 (Oc)
OO(Ob)
SC/O(Qa)
r
INA-t:====L::~:..W
'----I
OUTCOUTC+
~~:::~:'-J====1
OUTBOUTB+
SVS(Dj)
07(Oh)
06(Og)
05(01)
04(0j)
03(Oe)
02(Od)
01 (Dc)
OUTAOO(Ob)
OUTA+ SC/O(Oa)
AlB
ROY
SO
RF
BISTEN
MODE
CKR
REFCLK
ENA
ENN
FOTO
MODE
BISTEN
RP
System 1
System 2
Figure 8. Example HOTLink Loop-Back System Connection
4-113
CKW
~
sa
~YPRESS~=;=;=;=;=;=;~&~e~PI~a~Ce~Y4~O~U~r~TAXI=;~-~1~2~5~an~d~T~~=;I~-~1~75
plexers, as shown in Figure 9. This solution compromises system reliability and performance.
number of Is sent is equal to the number of Os. This
improves system performance by reducing the lowfrequency "base-line" wander that causes jitter.
Superior Data Encoding
More Robust Reframing Capabilities
Both the HOTLink and TAXI devices map the 8 bits
of incoming transmission data into 10-bit transmission characters. The TAXI -1 devices accomplish
this task by changing each pair of 4-bit nibbles of
data into a pair of 5-bit transmission symbols according to the ANSI X3T9.5 (FDDI) standard.
HOTLink, on the other hand, converts each 8 bits of
data into a lO-bit transmission symbol according to
the ANSI X3T9.3 Fibre Channel and ESCON (Enterprise System CONnection) specifications.
The primary purpose of converting the 8 data bits to
10 transmission bits is to include clock information
in the data stream. A code is selected that maps
each user character to a transmission character.
This mapping insures that the data stream contains
enough signal transitions to insure that the receiver
PLL stays frequency and phase locked with the incoming data. By including the clock along with the
data, the receiver is able to sample the incoming
stream of data at the correct rate and position. For
example, without this embedded clock information
there would be no way of knowing if 1000, 999, or
10011s were sent in a row.
While the 4B/5B code used in TAXI -1 merely insures that the transition density of the serial bit
stream is maintained, the 8B/lOB code used in
HOTLink also maintains the DC balance of the signal on the transmission line. This code maintains
DC balance by insuring that, on the average, the
TAXI 0 - - - - 1 - . . . - - - 0 TAXI
TX
TAXI
RX
RX
TAXI
TX
Figure 9. Loop-Back Testing with Multiplexers
To reassemble the incoming data stream into parallel data words, the receiver must know which bit
location is the beginning of each byte. The transmitter must send SYNC characters to let the receiver
know the location of byte boundaries. The TAXI -1
Transmitter sends a SYNC character when neither
Data or Command is strobed into the part. At the
receiver, this character is decoded as a command
and the command strobe is pulsed.
The HOTLink Transmitter also sends a SYNC character when neither data nor command information
is latched into the device. And again, at the receiver
this character is decoded and the SC/D is held
HIGH. HOTLink, however, differs in some very
important ways from TAXI -1 devices.
TAXI -1 does not have a method for sending a
SYNC character as part of the user character
stream. HOTLink has a dedicated code that forces
a SYNC character to be sent. This is important for
controllers that wish to send a SYNC character at
the beginning of each packet to insure that previous
framing errors do not affect the current packet of
data. This simplifies the controller and parallel data
interface since the code can be embedded in a
stream of other data.
Both TAXI -1 and HOTLink pad the spaces between data packets with SYNC characters. When
the "No STRB" condition exists with TAXI -1 or
the "No Enable" condition exists with HOTLink,
the transmitter fills the unused bandwidth with JK
(TAXI-I) or K28.5 (HOTLink). This pad string
must be identified at the receiver so that the receiving system is not forced to process this information.
TAXI -1 has no method for ignoring multiple
SYNC characters and preventing them from being
passed to the receiving system. This is important in
systems that have bursty data transmission or transmit data slower than the maximum TAXI -1 data
operating frequency. If multiple SYNCs are passed
to the outputs of the receiver, the receive FIFO will
overflow with useless SYNC characters and this will
4-114
-.~
; CYPRESS
Replace Your TAXI -125 and TAXI -175
require external decoder logic to discard the extraneous information. HOTLink eliminates this problem by only presenting the last SYNC character in
a string of SYNC characters (the first SYNC character of a new packet of information) to the outputs of
the receiver. This prevents redundant information
from being passed to the receive system, yet maintains packet boundaries for easy packet identification.
Occasionally transmission links will experience
noise that transforms part of the information stream
into a SYNC character (an alias SYNC). This may
cause the receiver to incorrectly identify the byte
boundary and cause all of the following information
to be misframed. This will continue to occur until
the transmitter sends an intentional SYNC symbol.
The TAXI -1 devices have no method to prevent
this unintended reframing. HOTLink can prevent
this in two ways.
The first way HOTLink prevents misalignment is
provided by its ability to disengage reframing under
user control with the RF (reframe) pin. In systems
that need reframing only between packets, or only
during supervisory functions, the reframe option
can be selectively activated or deactivated depending on the system needs.
The second way HOTLink prevents misalignment is
provided by its multi-byte framing capability. After
the initial start-up phase, approximately 2K bytes
after reframe (RF=HIGH) has been activated, the
receiver will no longer frame on just one SYNC
character, but instead requires at least two SYNC
characters separated by exactly 0, 10, 20, or 30 bits
of valid data as shown in Figure 10.
The multi-byte reframe option is useful in systems
that wish to keep the Reframe option activated continuously, but do not want to suffer the data corruption consequences of erroneous misalignment. Systems that stay connected for long communication
sessions (e.g., point-to-point data recovery) rarely
need to be Reframed since the receiver will rarely
lose byte alignment. In these systems, the protocol,
or an external timer, can control reframing and only
enable framing when it is required. On the HOTLink Receiver this will save 50 mW of power.
4-115
Receiver Reframed
Receiver NOT Reframed
Figure 10. Double-Byte Reframing
For systems that are reconnected often (switched
systems) the need to quickly reacquire byte synchronization requires that Reframe be continuously enabled. Multibyte framing available with HOTLink
protects these systems from alias SYNC characters.
Higher Operating Frequency
HOTLink provides the biggest improvement in a
system upgrade by allowing operation at nearly
twice the rate of the TAXI -175 devices and nearly
2.5 times the rate of the TAXI -125s. The range of
the TAXI -1 devices is 40 to 175 MBaud whereas
HOTLink operates from 160 to 330 MBaud. This
increased operating frequency range provides the
ability to transfer data at over twice the rate of an
equivalent TAXI system.
Built-In Self-Test Capabilities
BIST (Built-In Self-Test) can be used to test the
transmitter, receiver, and the serial data link connecting them. During BIST (See Figure 11), the
transmitter repeats a pattern representing all possible data and command characters, decodes them
into transmission symbols and passes them to its
outputs. The receiver, while in BIST, waits for the
symbol that represents the beginning of the BIST
pattern. It then decodes this symbol and every following symbol and compares it with an internally
generated pattern that matches those produced by
the transmitter's pattern generator. Error signals
are indicated with pulses on the RVS (Received
I
£2~
CYPRESS
Replace Your TAXI -125 and TAXI 175
_
CY7B923
DON'T CARE
DON'T CARE
I
II
I
I
BIST
LOOP
~(
T>u
~
II
I
I
I
I
I
I
Tx
I
START I
--,
I
I
I
I
I
I
I
I
I
I
I
I
I
"f>
»
WITHIN SPEC.
n
CKW
SCfI)
OUTA
DON'T CARE
8
LOW
Tx
STOP
SS
MODE
Rp
DON'T CARE
r-
((
FOTO
DO -7
OUTB
SVS
OUTC
EfJA
HIGH
r
ENN
BISTEN
CY7B933
WITHIN SPEC.
DON'T CARE
LOW
REFCLK
MODE
RF
SO
CKR
SCiLl
ERROR
O~
8
~
INA
00-7
INB
RVS
ROY
BISTEIiI
Figure 11. Built-In Self-Test
4-116
AlB
LOW
~,,~
Replace Your TAXI -125 and TAXI -175
~'CYPRESS
Violation Symbol) while completed BlST loops are
indicated with pulses on the ROY line. The BlST
function, therefore, checks the entire function of the
transmitter (except the transmitter input pins and
the bypass function in the Encoder), the serial link,
and the receiver.
These functions can not be implemented with the
TAXI devices. A substantial amount of additional
circuitry would need to be added to a TAXI system
to imitate this function. This type of testing is necessary for many types of diagnostics including device
functionality and link integrity.
The receiver has an ROY output that pulses LOW
each time new data has been received. The ROY
output has timing that allows the receiver to be
seamlessly interfaced with both asynchronous and
clocked FIFOs as shown in Figures 12 and 13. The
TAXI devices require a significant amount of additional circuitry to allow interfacing with FIFOs.
Better DC Specifications
The maximum current specifications of the
TAXI -1 Transmitter operating at 17.5 MB/sec is
265 mA. The maximum current specification of the
HOTLink Transmitter, on the other hand is 80 rnA
even when operating at 33 MB/sec.
Simplified Synchronous Inte/face
The TAXI -1 Receiver requires a maximum of 350
rnA to operate at 17.5 MB/sec whereas the HOTLink Receiver requires only 150 rnA when operating
at 33 MB/sec.
The TAXI -1 devices have two methods of strobing
data into the devices, synchronous and asynchronous. In the asynchronous mode of operation, a
strobe line is used in conjunction with an acknowledge line to present data to the device. In this mode
of operation the maximum byte-rate frequency for
the TAXI -175 devices under the most ideal conditions is no faster than 14 MB/sec. The synchronous
strobing feature of the TAXI -1 devices is also
cumbersome. This method involves connecting the
strobe to the clock line.
HOTLink has a very simple interface that allows
seamless connection to both asynchronous and
clocked FIFOs. On the transmitter, two enable inputs control when data is to be transmitted. When
the ENA input is asserted, data on the data lines is
serialized and transmitted. When the ENN line is
asserted, data that is presented on the data lines
during the next rising edge of the CLK input is transmitted. This allows efficient, synchronous state machines to control the flow of data over the serial link.
In addition, the RP (read pulse) output can be connected to the R (read) input of asynchronous FIFOs, as shown in Figure 12, to provide a seamless
asynchronous interface. The RP signal has timing
that matches the timing required by asynchronous
FIFOs. For clocked FIFO designs like that shown
in Figure 13, the ENN input is used to read data from
a Clocked FIFO like the Cypress CY7C453 as well
as latch data into the transmitter on the next rising
edgeofCKW.
The TAXI -1 devices require 300 m V of differential
input voltage at the receiver to accurately recover
the clock and data from the input serial data stream.
The HOTLink Receiver requires only 50 m V of differential input voltage. This translates into lower
error rates, increased noise margins, higher jitter
tolerance, and longer transmission distances when
compared with the TAXI -1 devices.
Loop-Back Testing Capabilities
TAXI -1 has no loop-back testing capabilities. As
mentioned previously, the redundant inputs and
outputs on the HOTLink devices allow in-system
loop-back testing to be performed. An additional
output from the transmitter can be connected to an
unused input of the receiver. The transmitterlreceiver pair of an individual port can be tested together by simply switching the receiver from the link
input to the Loop-back input as shown in Figure 8.
Ability to Send Violations
4-117
The TAXI -1 Transmitter has no method of sending
violations. The TAXI Receiver has no unambiguous
violation indication. Many, but not all, errors will be
indicated as CO (SYNC) while others will be indicated as other commands. In many systems it is important to explicitly send violations. In normal system operation, a violation can be caused by either a
received symbol having no corresponding decode
I
e ~YPRESS
Replace Your TAXI -125 and TAXI -175
SEND
FOIT
HOTLlNKTX
Ef.iWfY
CY7C429
--=::
STORE
.....
....
TXCONTROL
----
-
--
FIF02Kx9
MR
II
W
XI
XOHF
FLIRT
00
01
02
D3
04
05
06
07
08
-
El' " - - l'F " ' - - -
00
01
02
Q3
Q4
05
06
07
08
.....
V
V
V
-
CLK
READ
-
CY7C429
FIF02Kx9
EfiifI5iY
El'
RJ[[
FI'
~
RXCONTROL
Rl'
CKW
-
XOHF
QO
01
02
os
04
Q5
06
07
08
WI
II
W
XI
FLIRT
~II
-
13iS'fEN
MOOE
FOTO
EfIN
ENJ\
SC/O(Oa)
OO(Ob)
01(00)
02(Od)
D3(Oe)
04(0j)
05(01)
06(09)
07(Oh)
SVS(Oj)
OUTA+
OUTAOUTB+
OUTBOUTC+
OUTC-
-
-
~
HOTLlNKRX
CKR
SO
ROY
REFCLK
MODE
~
!--
:--
BlSTEf'I
RF :-AlB
!--
INA+
INA-
!--
INB(INB+)
SI(INB-)
!--
"'"'-
DO
SC/O(Oa)
QO(Ob)
01(00)
02(Od)
03(Oe)
Q4(Qi)
05(0!)
01
02
D3
04
05
06
07
08
-
:-:--
08(09)
07(Oh)
RVS(Oj)
Figure 12. Asynchronous FIFO Interface
to force errors on an otherwise undisturbed data
stream. Received errors are unambiguously indicated in the received data stream. All errors also
generate an indication on the RVS (Received Violation Symbol) pin to be used by external supervisory
logic.
value in the receiver, or a valid code received with
the wrong running disparity. Sending a violation
code on purpose is useful for testing, signaling, and
interrupting the receiving system.
The HOTLink 1l:ansmitter, on the other hand, provides two mechanisms to allow a system to send a
pattern that will translate into a Code Rule Violation at the receiver. Various codes are included in
the Special Character (SC) codes to send code rule
and Running Disparity (RD) violations as part of
the normal data stream. The SVS (Send Violation
Symbol) pin allows an external supervisory system
Ability to Tum-Off Serial Output Stream
There is no method of turning off the serial output
of the TAXI -1 devices. The FOTO (Fiberoptic
1l:ansmitter Off) is an input found on the HOTLink
Transmitter that allows the OUTA and OUTB differential outputs to be logically turned off. Laser
4-118
Replace Your TAXI -125 and TAXI -175
SEND
FULLJEMPTY
STORE
TXCONTROL
HOTLlNKTX
I
~
-
-
CKW
CY7C453
FIF02Kx9
CKR
CKW
F1
MR
ENR
F2
ENW
00
01
02
00
01
02
03
04
05
06
07
08
03
04
05
-
-
-
-
BISTEN
MOOE
FOTO
-
ENN
ENA
-
SC/O(Oa)
OO(Ob)
01 (Oe)
02(Od)
03(Oe)
04(0))
05(01)
06(Og)
07(Oh)
SVS(Oj)
as
07
08
CLK
-
OUTA+
OUTA-
I-I'-
OUTB+
OUTB-
I-I'-
OUTC+
OUTC-
I-I--
I
HOTLlNKRX
READ
~
CY7C453
FIFO 2Kx9
CKR
CKW
F1
MR
FULLJEMPTY
RXCONTROL
RP
-
-
F2
ENR
ENW
00
01
02
00
01
02
03
03
04
==-----
I
D4
05
06
07
08
05
06
07
08
-
CKR
REFCLK
SO
ROY
MODE
BISTEN
RF
SC/D(Oa)
OO(Ob)
01 (Oe)
02(Od)
03(Oe)
04(Oi)
05(On
06(Og)
07(Oh)
RVS(Oj)
AlB
I-I-I'I--
INA+
I--
INA-
I--
INB(INB+)
SI(INB-)
I-I'-
Figure 13. Clocked FIFO Interface
Modifying the System for HOTLink
safety systems can use this input to shut off the lasers
in the case of a fiber disconnect.
Listed below are some simple system modifications
that can be performed in lieu of modifying the entire
system architecture for designers who currently use
the TAXI -1 devices and wish to easily upgrade to
the HOTLink devices in order to take advantage of
its performance and architectural improvements.
ECL to TTL Translator
The TAXI devices have no EeL to TTL translator.
The HOTLink devices have a built-in EeL to TTL
translator. The SI input takes the single-ended EeL
lOOK (+5V referenced) input and the translated
TTL signal is presented at the SO output. The system can utilize this translator to convert a carrierdetect signal into its TTL equivalent for use by a
controller.
Multiplexed Command and Data
4-119
Most systems have, at some level, an integrated
command and data path, much like that used in
HOTLink. These systems explicitly demultiplex
these paths to make themselves compatible with the
TAXI architecture. These systems can easily take
I
....::=...
zg~YPRESS~~~~~~~R~e~p~la~C~e~YO~U~r~T~~~I-~1~2~5~an~d~T~~~I~-~1~75
advantage of the HOTLink architecture by removing the unnecessary multiplexing circuitry and allowing the demultiplexer control line and the datal
command lines to drive HOTLink directly.
Operating Frequency
The operating frequency of HOTLink is much faster
than the TAXI devices. No design issues need to be
considered in systems that wish to operate their parallel side at the same rate and take advantage of the
increased system flexibility and functionality that
HOTLink offers. When the system has no data to
send over the transmission link, HOTLink simply
sends strings of SYNC characters automatically.
These SYNC characters are ignored on the receiving end. So, whenever the transmitting side of the
link does not present data to the transmitter, a
SYNC character will be sent. These characters, although used to keep the receiver in lock with the
transmission stream, will not be presented as a character to the outputs.
Some systems, however, send command codes outof-band with respect to the data stream. These systems can be easily modified by adding a simple multiplexer external to HOTLink or external to the
FIFO that drives HOTLink. The MUX select can
be driven by the AND of the command lines.
Data Words Longer than 8 Bits
Most data words that need to be encoded are 8 bits
in length. In a few cases, however, the data that
needs to be encoded is 9, or even 10, bits in length.
In these cases, an external multiplexer can be used
external to a FIFO that would put each half of the
9- or lO-bit data word into the FIFO separately. At
the receiving end, the same operation would be performed in reverse. This is possible due to the extended operating frequency of HOTLink.
Conclusion
The HOTLink Transmitter and Receiver have many
advantages over the AMD Am7968 Transmitter and
the Am7969 Receiver (TAXI -1). These advantages include those listed below.
Asynchronous Strobing
HOTLink provides a very user-friendly synchronous interface. For asynchronous operation, a
FIFO can be used to interface the two asynchronous
entities.
• Multiplexed command and data
• More serial outputs
• More serial inputs
Mapping Command Codes
• Superior data encoding
In 8-bit mode, TAXI -1 has 15 different command
codes (see Table 1), while HOTLink can transmit
and receive 12 specific codes (see Table 2). Several
of these TAXI command codes have restrictions on
their usage. HOTLink has no restrictions on the use
of any codes. If the system must use more than 12
codes, an easy way to expand the command set is by
utilizing a specific code that indicates that the next
data word is also a command code. Using this method, or a simple extension of this method, allows
nearly an infinite command code set to be transmitted and received.
4-120
• More robust reframing
• Higher operating frequency
• Built-in self-test
• Simplified synchronous interface
• Reduced power consumption
• Loop-back testing capabilities
• Ability to send violations
• Ability to turn off serial output stream
• ECL-to-TTL translator
-= ~YPRESS~~~~~~~R~e~p~la~C~e~YO~U~r~T~~~I~-~1~2~5~an~d~T~~~I~-~1==75
Table 1. TAXIchip Command Symbols
Am7968 Transmitter
Am7969 Receiver
Command Input
Command Output
HEX
Binary
Encoded
Symbol
Mnemonic
HEX
Binary
8-BitMode
0
0000
XXXXXXXXXX
Data
No Change
No Change
NoSTRB
NoSTRB
1100010001
JK (8-bit Sync)
0
0000
0001
1
0001
1111111111
0010
0110101101
II
TT
1
2
2
0010
3
0011
0110111001
TS
3
0011
4
0100
11111 00100
IH
4
0100
5
0101
0110100111
TR
5
0101
6
0110
11001 00111
SR
6
0110
7
0111
1100111001
SS
7
0111
8L1]
1000
0010000100
1000
1001
0010011111
9
1001
1010
0010000000
HH
HI
HO
8
9
A[l]
A
1010
B
1011
0011100111
RR
B
1011
C
D[l]
1100
0011111001
RS
C
1100
1101
0000000100
D
1101
EL1j
1110
0000011111
E
1110
F[1]
1111
0000000000
OH
01
00
F
1111
Note
1. While these Commands are legal data and will
not disrupt normal operation if used occasionally, they may cause data errors if grouped into
recurrent fields. Normal PLL operation cannot
be guaranteed if one or more of these
commands is continuously repeated.
4-121
II
Replace Your TAXI -125 and TAXI -175
Table 2. HOTLink Valid Special Character Codes and Sequences (SCID = HIGH)
000
00000
001111
0100
110000
1011
Receiver
Output
Code Name
CO.O
CloD
(COl)
000
00001
001111
1001
110000
0110
CloD
C2.0
(CO2)
000
00010
001111
0101
110000
1010
C2.0
C3.0
(C03)
000
00011
001111
0011
110000
1100
C3.0
C4.0
(C04)
000
00100
001111
0010
110000
1101
C4.0
K28.S
CS.O
(COS)
000
00101
001111
1010
110000
0101
CS.O
K28.6
K28.7
K23.7
K27.7
K29.7
C6.0
(C06)
000
00110
001111
0110
110000
1001
C6.0
C7.0
(C07)
000
00111
001111
1000
110000
0111
C7.0
CS.O
(COS)
000
01000
111010
1000
000101
0111
CS.O
C9.0
(C09)
000
01001
110110
1000
001001
0111
C9.0
C10.0
(COA)
000
01010
101110
1000
010001
0111
C10.0
K30.7
C1l. 0
(COB)
000
01011
011110
1000
100001
0111
C1l. 0
HOTLink
Special Code
Byte Name
K28.0
Bits
Special Code
Code Name
(COO)
CO.O
K28.1
K28.2
K28.3
K28.4
CurrentRD-
HGF
EDCBA
abcdei
CurrentRD+
fgbj
abcdei
fghj
Sequences
Idle
CO.1
(C20)
001
00000
-K2S.S+,D21.4,D21.S,D21.S,
repeat
CS.O, D2l. 4,
D2l. S, D2l. S
R_RDY
Cl.1
(C21)
001
00001
-K2S.S+,D21.4,D10.2,D10.2,
repeat
C5.0, D2l.4,
D10.2, D10.2
EOFxx
C2.1
(C22)
001
00010
-K2S.S,Dn.xxxO
CS.O,Dn.xxxO
or
C5.0,Dn.xxx1
I+K2S.S,Dn.xxx1
Follows K28.1 for ESCON Connect-SOF (RK indication only)
I C7.1
I C7.2
C-SOF
(C27)
I
I
001
00111
I 001111
I 001111
r
110000
0111
I
C7.1
1000
I 110000
0111
J
C7.2
1000
Follows K28.5 for ESCON Passive-SOF (RK indication only)
P-SOF
(C47)
010
00111
Code Rule Violation and SVS Tx Pattern
Exception
CO.7
(CEO)
111
00000
100111
1000
011000
0111
CO.7
-K2S.5
Cl.7
(CE1)
111
00001
001111
1010
001111
1010
CS.O or C1.7
C2.7
(CE2)
111
00010
110000
0101
110000
0101
CS.O or C2.7
110111
0101
001000
1010
+K2S.S
Running Disparity Violation Pattern
Exception
I
C4. 7
(CE4)
I
111
00100
I
References
1. Cypress Semiconductor, CY7B923/CY7B933
HOTLink Transmitter/Receiver Preliminary Datasheet, Cypress Semiconductor High Performance Data Book, August 1, 1993.
2. Cypress Semiconductor, HOTLink Design Considerations Application Note, October 1993.
3. Advanced Micro Devices, TAXIchip Integrated
Circuits Transparent Asynchronous Transmitter/Receiver Interface Am7968/Am7969-125
I
I
C4.7
Am7968/Am7969-175 Data Sheet and Thchnical Manual, 1992
4. Advanced
Micro
Devices,
Am79168/
Am79169-275 TAXI-275 Integrated Circuits
Technical Manual, Rev. 1.0, 1993.
5. Advanced
Micro
Devices,
Am79168/
Am79169-275 TAXI -275 'fransmitter/Receiver Transparent Asynchronous Transmitter/Receiver Interface Preliminary Data Sheet, March
1993 RevB.
AMD, TAXI, and TAXlchip are trademarks of Advanced Micro Devices.
HOTLink is a trademark of Cypress Semiconductor.
ESCON is a trademark of International Business Machines.
4-122
FIFOs 5
FIFOs
Device Number
CY7C408NCY7C409A
CY7C419/21/25/29/33
CY7C42X1
CY7C42X5
CY7C4255/65
CY7C4261/71
CY7C439
CY7C441143
CY7C455/56/57
CY7C460/62/64
CY7C470/72/74
Page Number
Description
64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
256 x 9, 512x 9, 1Kx 9, 2Kx 9, 4Kx 9 Cascadable FIFO ............................ 5-15
64/256/512/1K/2K/4K/8Kx 9 Synchronous FIFO .................................. 5-37
64/256/512/1K/2K/4K/ x 18 Synchronous FIFO .................................... 5-57
8K/16K x 18 Synchronous FIFO ................................................ 5-77
16K/32K x 9 Synchronous FIFO ................................................ 5-94
Bidirectional 2K x 9 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -109
512 x 9 Cascadable Clocked and 2K x 9 Cascadable Clocked
FIFO with Programmable Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -138
512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFO
with Programmable Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -161
Cascadable 8K x 9 FIFO/Cascadable 16K x 9 FIFO/Cascadable 32K x 9 FIFO. . . . . . . .. 5 -181
8K x 9 FIFO, 16K x 9 FIFO/32K x 9 FIFO with Programmable Flags ................ 5 -194
CY7C408A
CY7C409A
64 x 8 Cascadable FIFO
64 x 9 Cascadable FIFO
Features
• 64 x 8 and 64 x 9 first-in first-out
(FIFO) buffer memory
• 35-MHz shift in and shift out rates
• Almost Full/Almost Empty and Half
Fulll1ags
• Dual-port RAM architecture
• Fast (50-ns) bubble-through
• Independent asynchronous inputs
and outputs
• Output enable (CY7C408A)
• Expandable in word width and FIFO
depth
• 5V :!::10% supply
• TTL compatible
• Capable of withstanding greater than
2001V electrostatic discharge voltage
• 300-mil, 28-pin DIP
Functional Description
The CY7C408A and CY7C409A are
64-word deep by 8- or 9-bit wide first-in
first-out (FIFO) buffer memories. In
addition to the industry-standard
handshaking signals, almost ful1!almost
empty (APE) and half full (HF) flags are
provided.
APE is HIGH when the FIFO is almost full
or almost empty, otherwise AFE is LOW.
HF is HIGH when the FIFO is half full,
otherwise HF is LOW.
The CY7C408A has an output enable
(OE) function.
The memory accepts 8- or 9-bit parallel
words at its inputs (Dlo - Dig) under the
control of the shift in (SI) input when the
input ready (IR) control signal is HIGH.
The data is output, in the same order as it
was stored, on the DOo - DOg output pins
under the control of the shift out (SO)
input when the output ready (OR) control
signal is HIGH. If the FIFO is full (IR
LOW), pulses at the SI input are ignored; if
the FIFO is empty (OR LOW), pulses at
the SO input are ignored.
The IR and OR signals are also used to
connect the FIFOs in parallel to make a
wider word or in series to make a deeper
buffer, or both.
Parallel expansion for wider words is
implemented by logically ANDing the IR
and OR outputs (respectively) of the
individual FIFOs together (Figure 5). The
AND operation insures that all of the
FIFOs are either ready to accept more
data (IR HIGH) or ready to output data
(OR HIGH) and thus compensate for
variations in propagation delay times
between devices.
Serial expansion (cascading) for deeper
buffer memories is accomplished by
connecting the data outputs of the FIFO
closest to the data source (upstream
device) to the data inputs of the following
(downstream) FIFO (Figure 4). In
addition, to insure proper operation, the
SO signal of the upstream FIFO must be
connected to the IR output of the
downstream FIFO and the SI signal of the
downstream FIFO must be connected to
the OR output of the upstream FIFO. In
this serial expansion configuration, the IR
and OR signals are used to pass data
through the FIFOs.
Reading and writing operations are
completely asynchronous, allowing the
FIFO to be used as a buffer between two
digital machines of widely differing
operating frequencies. The high shift in
and shift out rates of these FIFOs, and
their high throughput rate due to the fast
bubblethrough time, which is due to their
dual-port RAM architecture, make them
ideal for high-speed communications and
controllers.
Logic Block Diagram
Pin Configurations
AFE
Vee
81
WRITE POINTER
AFE
HF
IR
IJlR
IR
WRITE MULTIPLEXER
HF
81
OR
Dlo
DI,
DOo
000
Dlo
80
DO,
GND
GND
MEMORY
ARRAY
DI,
DO,
DI2
DI3
DO, (7C409A)
DI.
DE (7C40SA)
DI.
(7C409A) DI,
D02
D03
DO.
DOs
DO.
015
READ MULTIPLEXER
DI,
OR
IJlR
READ POINTER
80
DO,
(7C40SA) NC
(7C409A) DI,
0E(7C40SA)
DO, (7C409A)
C40SA-3
C408A-1
uHf
010
01,
Flag Definitions
HF
L
L
H
H
AFE
H
L
L
H
GND
DI2
DI3
DI.
Dis
Words Stored
0-8
9 - 31
32 - 55
56 - 64
~ ~>g~ ~
432 L1l 282726
7C40SA
7C409A
10
11
25
24
23
22
21
20
19
OR
DOo
DO,
GND
D02
DO,
DO.
12131415161718
_coJ'-_cod:Cbl"-d'blD
OCl~§ClOO
5-1
C40BA·2
E
CY7C408A
CY7C409A
-,~
=-
~'CYPRESS
Selection Guide
7C408A-15
7C409A-15
Maximum Shift Rate (MHz)
Maximum 03erating
Current (rnA [1]
7C408A-25
7C409A-25
7C408A-35
7C409A-35
15
25
35
I Commercial
115
125
135
I
140
150
N/A
Military
Maximum Ratings
(Above which the useful life maybe impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to + 150°C
Ambient Temperature with
Power Applied ....................... -55°C to +125°C
Supply Voltage to Ground Potential ........ -0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State (7C40SA) ................ -O.5V to +7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. l.OW
Output Current, into Outputs (Low) ............... 20 rnA
Static Discharge Voltage ........................ >2oo1V
(per MIL-STD-S83, Method 3015)
Operating Range
Range
Commercial
Military[2]
Ambient
Temperature
O°C to +70°C
Vee
5V ±1O%
-55°C to + 125°C
5V ±1O%
Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)[3]
Parameter
Description
Test Conditions
Min.
VOH
Output HIGH Voltage
V CC = Min., lOR = -4.0 rnA
VOL
Output LOW Voltage
V CC = Min., IOL = 8.0 rnA
VIR
Input HIGH Voltage
2.2
VIL
Input LOW Voltage
IJX
Input Leakage Current
Output Short Circuit CurrentL4J
V CC = Max., VOUT = GND
IccQ
Quiescent Power Supply Current
V ce = Max., lOUT = 0 rnA
VIN .::;. VIL, VIN ~ VIR
Power Supply Current
Ice
Unit
2.4
GND,::;,VI,::;,Vee
los
Max.
I Commercial
I Military
V
0.4
V
Vee
O.S
V
-3.0
-10
+10
JlA
-90
rnA
100
rnA
125
rnA
V
Ice = ICCQ + 1 mA/MHz X (fsl + fso)/2
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
Vcc = 4.5V
Notes:
1. ICC = ICCQ + 1 mNMHz X (fsl + fso)/2
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing infonnation.
4.
5.
Max.
5
7
Unit
pF
pF
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
5V
~R14820
ALL INPUT PULSES
3.0V - - - _ - - - - - -...1
90%
5V S f 1 R
48201
OUTPUT
OUTPUT
CL
~78~~~NG J,
R2
2560
30 pF
R2
2560
5 pF
~78~~~NG J,
-=
SCOPE
-=
SCOPE
(a)
(b)
C40BA-4
Equivalent to: THEvENIN EQUIVALENT
1670
OUTPUT
GND
o------vw------
1.73V
C40BA·6
5-2
C40SA-5
CY7C408A
CY7C409A
~-.~
=--; CYPRESS
Switching Characteristics Over the Operating Rangel 3, 6]
Parameter
Description
7C408A-15
7C409A-15
Test
Conditions
Min.
Max.
7C408A-25
7C409A-25
Min.
Max.
7C408A-35
7C409A-35
Min.
Max.
Unit
35
MHz
fa
Operating Frequency
Note 7
tpHSI
SIHIGHTime
Note 7
23
11
9
ns
tpLSI
SILOWTime
Note 7
25
24
17
ns
tSSI
Data Set-Up to SI
Note 8
0
0
0
ns
tHSI
Data Hold from SI
Note 8
30
20
12
tDLIR
Delay, SI HIGH to IR LOW
35
21
15
ns
tDHIR
Delay, SI LOW to IR HIGH
40
23
16
ns
tpHSO
SO HIGH Time
Note 7
23
11
9
ns
tpLSO
SO LOW Time
Note 7
25
24
17
ns
tDLOR
Delay, SO HIGH to OR LOW
35
21
15
ns
tDHOR
Delay, SO LOW to OR HIGH
40
23
16
ns
tSaR
Data Set-Up to OR HIGH
0
0
0
tHSO
Data Hold from SO LOW
0
0
0
tBT
Fall-through, Bubble-back Time
10
tSIR
Data Set-Up to IR
Note 9
5
5
5
tHIR
Data Hold from IR
Note 9
30
20
20
ns
tpIR
Input Ready Pulse HIGH
Note 10
6
6
6
ns
tpOR
Output Ready Pulse HIGH
Note 11
6
tDLZOE
OE LOW to LOW Z (7C408A)
Note 12
35
30
25
ns
tDHZOE
OE HIGH to HIGH Z (7C408A)
Note 7
35
30
25
ns
tDHHF
SI LOW to HF HIGH
65
55
45
ns
tDLHF
SO LOW to HF LOW
65
55
45
ns
tDLAFE
SO or SI LOW to APE LOW
65
55
45
ns
tDHAFE
SO or SI LOW to AFE HIGH
65
55
45
ns
tpMR
MR Pulse Width
55
45
35
tDSI
MR HIGH to SI HIGH
25
10
10
tDOR
MR LOW to OR LOW
55
45
35
ns
tDJR
MR LOW to IR HIGH
55
45
35
ns
tLZMR
MR LOW to Output LOW
55
45
35
ns
tAFE
MR LOW to APE HIGH
55
45
35
ns
tHF
MR LOW to HF LOW
55
45
35
ns
taD
SO LOW to Next Data Out Valid
28
20
16
ns
15
Note 13
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOrflOH and
30-pF load capacitance, as in parts (a) and (b) of AC Thst Loads and
Waveforms.
7. lifo ~ (tpHSI + tPLSI), lifo ~ (tpHSO + tpLSO)·
8. tSSI and tHSI apply when memory is not full.
9. tSIR and tHJR apply when memory is full, SI is high and minimum
bubble-through (tBT) conditions exist.
10. At any given operating condition tpIR ~ (tpHSO required).
11. At any given operating condition tpOR ~ (tpHSI required).
65
25
10
60
6
10
ns
ns
ns
50
ns
ns
6
ns
ns
ns
12. tDHZOE and tDLZOE are specified with CL ; 5 pF as in part (b) of AC
Thst Loads and Waveforms. tDHZOE transition is measured ±500 m V
from steady-state voltage. tDLZOE transition is measured ± 100 m V
from steady-state voltage. These parameters are guaranteed and not
100% tested.
13. All data outputs will be at LOW level after reset goes HIGH until data
is entered into the FIFO.
5-3
CY7C408A
CY7C409A
=:?cYPRESS
Switching Waveforms
Data In Timing Diagram
SHIFT IN
INPUT READY
DATA IN
AFE
HF
(LOW)
C40SA-7
Data Out Timing Diagram
1 - - - - - I/fo
----+-----
SHIFT OUT
OUTPUT READY
DATA OUT
HF
(LOW)
AFE ________________________________________
~t_D_H ,f;r------------------------.
__.
C40SA-8
Notes:
14_ FIFO contains 8 words_
15. FIFO contains 9 words.
5-4
CY7C408A
CY7C409A
· -.,:Z
; CYPRESS
Switching Waveforms
(continued)
Data In Timing Diagram
SHIFT IN
INPUT READY
DATA IN
AFE
HF
C40BA-9
Data Out Timing Diagram
SHIFT OUT
OUTPUT READY
DATA OUT
HF
AFE
(LOW)
Output Enable (CY7C40SA only)
OUTPUT ENABLE
£3
C40BA-10
~
_ _
tDHWE
DATA OUT
----________________
-
!-=tDLZOE
=(_ _
NOTE 12
C40BA-11
Notes:
16. FIFO contains 31 words.
17. FIFO contains 32 words.
5-5
CY7C408A
CY7C409A
=-~
W;CYPRESS
Switching Waveforms (continued)
Data In Timing Diagram
SHIFT IN
INPUT READY
DATA IN
HF
AFE
C408A·12
Data Out Timing Diagram
SHIFT OUT
OUTPUT READY
DATA OUT
AFE
HF
(HIGH)
Bubble-Back, Data Out To Data In Diagram
SHIFT OUT : : : 0
'"" ,
SHIFT IN
t
C408A·13
~--------~----------------------------~',-____________
1----
_ _..,.~I
leT -
"-
INPUTREADY _________________________________- '
DATA IN
ISIR
Notes:
18. FIFO contains 55 words.
19. FIFO contains 56 words.
-1014----
20. FIFO contains 64 words.
5-6
C40BA·14
..
CY7C408A
CY7C409A
-,,~
,CYPRESS
Switching Waveforms (continued)
Fall-Through, Data In to Data Out Diagram
SHIFT IN NOTE 21
SHIFT OUT
OUTPUT READY
DATA OUT
./
t
J,--------j~,r.=====-tB-T-----------l-r---_------------
_
_ _ .. tPOR=1
---------->k tSOR
~
_
------
--------~
C40BA·15
Master Reset Timing Diagram
I+-MASTER RESET
tpMR-
~"
~
INPUT READY
tOIR
tOOR
~~
~
OUTPUT READY
tOSI
SHIFT IN
tLZMR
AFE
~
}
"'\~
DATA OUT
HF
E
-tHF
--tAFE
"-
C40BA·16
Note:
21. FIFO is empty.
5-7
CY7C408A
CY7C409A
=r;~
==:::, CYPRESS
Architecture of the CY7C408A and CY7C409A
Shifting Data Into the FIFO
The CY7C408A and CY7C409A FIFOs consist of an array of 64
words of 8 or 9 bits each (which are implemented using a dual-port
RAM cell), a write pointer, a read pointer, and the control logic
necessary to generate the handshaking (SI/IR, SO/OR) signals as
well as the almost full/almost empty (AFE) and halffull (HF) flags.
The handshaking signals operate in a manner identical to those of
the industry standard CY7C401/402/403/404 FIFOs.
The availability of an empty location is indicated by the HIGH
state of the input ready (IR) signal. When IR is HIGH a LOW to
HIGH transition on the shift in (SI) pin will clock the data on the
Dlo - Dig inputs into the FIFO. Data propagates through the
device at the falling edge of SI.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is necessary to
achieve truly asynchronous operation of the inputs and outputs. A
second benefit is that the time required to increment the read and
write pointers is much less than the time that would be required for
data to propagate through the memory, which it would have to do
if the memory were implemented using the conventional register
array architecture.
Fall-Through and Bubble-Back
The time required for data to propagate from the input to the
output of an initially empty FIFO is defined as the fall-through
time.
The time required for an empty location to propagate from the
output to the input of an initially full FIFO is defined as the
bubble-back time.
The maximum rate at which data can be passed through the FIFO
(called the throughput) is limited by the fall-through time when it
is empty (or near empty) and by the bubble-back time when it is full
(or near full).
The IR output will then go LOW, indicating that the data has been
sampled. The HIGH-to-LOW transition of the SI signal initiates
the LOW-to-HIGH transition of the IR signal if the FIFO is not
full. If the FIFO is full, IR will remain LOW.
Shifting Data Out of the FIFO
The availability of data at the outputs of the FIFO is indicated by
the HIGH state of the output ready (OR) signal. After the FIFO is
reset all data outputs (DOo - DOg) will be in the LOW state. As
long as the FIFO remains empty, the OR signal will be LOW and
all SO pulses applied to it will be ignored. After data is shifted into
the FIFO, the OR signal will go HIGH. The external control logic
(designed by the user) should use the HIGH state of the OR signal
to generate a SO pulse. The data outputs of the FIFO should be
sampled with edge-sensitive type D flip-flops (or equivalent), using
the SO signal as the clock input to the flip-flop.
AFE and HF Flags
Two flags, almost fulValmost empty (AFE) and half full (HF),
describe how many words are stored in the FIFO. AFE is HIGH
when there are 8 or fewer or 56 or more words stored in the FIFO.
Otherwise the AFE flag is LOW. HF is HIGH when there are 32 or
more words stored in the FIFO, otherwise the HF flag is LOW.
Flag transitions occur relative to the falling edges of SI and SO
(Figures 1 and 2).
The conventional definitions of fall-through and bubble-back do
not apply to the CY7C408A and CY7C409A FIFOs because the
data is not physically propagated through the memory. The read
and write pointers are incremented instead of moving the data.
However, the parameter is specified because it does represent the
worst-case propagation delay for the control signals. That is, the
time required to increment the write pointer and propagate a
signal from the SI input to the OR output of an empty FIFO or the
time required to increment the read pointer and propagate a signal
from the SO input to the IR output of a full FIFO.
Due to the asynchronous nature of the SI and SO signals, it is
possible to encounter specific timing relationships which may
cause short pulses on the AFE and HF flags. These pulses are
entirely due to the dynamic relationship of the SI and SO signals.
The flags, however, will always settle to their correct state after the
appropriate delay (tDHAFE, tDLAFE, tDHHB or tDLHF). Therefore,
use of level-sensitive rather than edge-sensitive flag detection
devices is recommended to avoid false flag encoding.
Resetting the FIFO
If the handshaking signals IR and OR are not properly used to
generate the SI and SO signals, it is possible to violate the
minimum (effective) SI and SO positive pulse widths at the full and
empty boundaries.
Upon power-up, the FIFO must be reset with a master reset (MR)
signal. This causes the device to enter the empty condition, which
is signified by the OR signal being LOW at the same time that the
IR signal is HIGH. In this condition, the data outputs (DOo DOg) will be LOW. The AFE flag will be HIGH and the HF flag
will be LOW.
Possible Minimum Pulse Width Violation at the Boundary
Conditions
EMPTY
1
SHIFT IN
2
SLSL...
8
9
10
31
32
33
55
56
57
FULL
64
•••~_
•••_~",--._
•• SL_
HF
AFE
C40BA-17
Figure 1. Shifting Words In
5-8
CY7C408A
CY7C409A
....0:=...
=-
~YPRESS
Cascading the 7C408/9A-35 Above 25 MHz
first device has its data shifted in faster than it is shifted out, and
eventually this device becomes momentarily full. When this
occurs, the maximum sustainable external clock frequency
changes from 35 MHz to the cascade interface frequency.l28]
First, the capacity of N cascaded FIFOs is decreased from N X 64
to (N X 63) + l.
If cascaded FIFOs are to be operated with an external clock rate
greater than 25 MHz, the interface IR signal must be inverted
before being fed back to the interface SO pin (Figure 3). lWo things
should be noted when this configuration is implemented.
Secondly, the frequency at the cascade interface is less than the 35
MHz rate at which the external clocks may operate. Therefore, the
When data packets[29] are transmitted, this phenomenon does not
occur unless more than three FIFOs are depth cascaded. For
example, if two FIFOs are cascaded, a packet of 127 (=2 X 63 +
1) words may be shifted in at up to 35 MHz and then the entire
packet may be shifted out at up to 35 MHz.
EMPTY
FULL
64
SHIFT OUT
63
56
55
31
32
54
..n....rL...
9
30
7
8
... JL
•••
HF
AFE
C408A·1S
Figure 2. Shifting Words Out
r - .. - - - .. - - - - - - - - - - ..... - - - - - - - - - - - - - - - - - ... - .. - - - - - - ...•
A
IRX
IR
I
SI
Six
0INX
I
c
B
IR
SO
SI
OR
r--2000V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
32 31 30 29 2827 2625
FI'
00
7C419-40
7C420-40
7C421-40
7C424-40
7C425-40
7C428-40
7C429-40
7C432-40
7C433-40
20
40
35
(Above which the useful life may be impaired. For user guidelines,
not tested.)
TQFP
Top View
70419
70421/5/9
70433
7C419-30
7C420-30
7C421-30
7C424-30
7C425-30
7C428-30
7C429-30
7C432-30
7C433-30
25
30
35
Maximum Rating
Pin Configurations (continued)
0,
Do
NC
NC
7C419-25
7C420-25
7C421-25
7C424-25
7C425-25
7C428-25
7C429-2S
7C432-25
7C433-2S
28.5
25
35
9 1011 1213141516
Operating Range
OOO~!rr.OOO
Ambient
Temperature[l]
Vee
O°Cto + 70°C
5V:!: 10%
Industrial
-40°C to +85°C
5V:!: 10%
Military
-55°C to + 125°C
5V:!: 10%
Range
Commercial
"
Electrical Characteristics Over the Operating Range[2]
7C419-10, 15, 20, 25, 30, 40, 65
7C420/1-10, 15, 20, 25, 30, 40, 65
7C424/5-10, 15,20,25,30,40,65
7C428/9-10, 15, 20, 25, 30, 40, 65
7C432/3-10, 15,20,25,30,40, 65
Parameter
Description
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VIL
IIX
loz
los
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Output Short Circuit Current[4]
Test Conditions
Min.
Vee = Min., IOH = -2.0 rnA
Vee = Min., IOL = 8.0 rnA
ICom'l
I Mil/Ind
2..4
GND.s VI.s Vee
R~ VIH, GND.s Vo.s Vee
Vee = Max., Vom = GND
5-16
Max.
Unit
0.4
V
V
V
2.0
2.2
Note 3
-10
Vee
Vee
0.8
+10
-io
+10
-90
V
!!A
!!A
rnA
CY7C419/21/25/29/33
Electrical Characteristics Over the Operating Rangd2] (continued)
Parameter
Description
Operating Current
Icc
Test Conditions
Vee = Max., Com'!
lOUT = ornA
MiI/lnd
f = fMAX
IcC!
Operating Current
Vee = Max., Com'!
lOUT = ornA
F = 20 MHz
ISBl
Standby Current
AI! Inputs
VIHMin.
Power-Down Current
ISB2
=
7C419-10
7C419-15
7C421-10
7C421-15
7C425-10
7C425-15
7C429-10
7C429-15
7C419-20
7C420-20
7C421-20
7C424-20
7C425-20
7C428-20
7C429-20
7C433-10
7C433-15
7C433-20
7C419-25
7C420-25
7C421-25
7C424-25
7C425-25
7C428-25
7C429-25
7C432-25
7C433-25
Min. Max. Min. Max. Min. Max. Min. Max. Unit
85
Com'!
65
55
50
100
90
80
35
35
35
35
rnA
10
10
10
10
rnA
15
15
15
5
5
5
8
8
8
Mil/lnd
AI! Inputs ~ Com'!
Vee - 0.2V
MiI/lnd
5
rnA
rnA
Electrical Characteristics Over the Operating Rangd2] (continued)
7C419-30
7C420-30
7C421-30
7C424-30
7C425-30
7C428-30
7C429-30
7C432-30
7C433-30
Parameter
Icc
Description
Operating Current
Test Conditions
Min.
Max.
7C419-40
7C420-40
7C421-40
7C424-40
7C425-40
7C428-40
7C429-40
7C432-40
7C433-40
Min.
Max.
7C419-65
7C420-65
7C421-65
7C424-65
7C425-65
7C428-65
7C429-65
7C432-65
7C433-65
Min.
I
Max.
Units
rnA
Vee = Max.,
lOUT = ornA
f = fMAX
Com'!
40
35
35
MiI/lnd
75
70
65
Com'!
35
35
35
rnA
rnA
IcC!
Operating Current
Vee = Max.,
lOUT = ornA
F=20MHz
ISBI
Standby Current
AI! Inputs
VIHMin.
=
Corn'l
10
10
10
Mil
15
15
15
ISB2
Power-Down Current
All Inputs~
Vee - 0.2V
Com'!
5
5
5
Mil
8
8
8
rnA
Capacitance[5]
Parameter
CrN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
= 25°C, f = 1 MHz,
Vee = 4.5V
TA
Max.
6
6
Unit
pF
pF
Notes:
1.
TA is the "instant on" case temperature.
4.
2.
See the last page ofthis specification for Group A subgroup testing information.
V IL (Min.) = - 2.0V for pulse durations of less than 20 ns.
shorted. Short circuit test duration should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect
these parameters.
3
5-17
For test purposes, not more than one output at a time should be
CY7C419/21/25/29/33
1
AC Test Loads and Waveforms
OlITP:;',: '" '"
pC
333Q
INCLUDING _
JIG AND SCOPE
(a)
Equivalent to:
1
Ii' ~ OlITP~:, Ii' ~
_
-
C420·6
ALL INPUT PULSES
'.w~ 90%·
GND
333Q
INCLUDING _
JIG AND SCOPE
_
-
10%
53ns-
I.-
-
~
53 ns
C42D-B
C42D-7
(b)
THEvENIN EQUIVALENT
200Q
____~o2V
OUTPUToo-----N.~.
Switching Characteristics Over the Operating Rangd 6, 7]
7C419-10
Parameter
tRe
tA
Description
Read Cycle Time
Access Time
tRR
tpR
tLZRl),8J
Read Recovery Time
tDVRI~,~J
Data Valid After Read HIGH
Read HIGH to High Z
tHZR[5,8,9j
Read Pulse Width
Read LOW to Low Z
twc
tpw
tHWZl),oJ
Write Cycle Time
Write Pulse Width
tWR
Write Recovery Time
tSD
Data Set-Up Time
Data Hold Time
tMRSC
tpMR
MR Cycle Time
MR Pulse Width
tRMR
tHD
tRPW
twpw
tRrC
tpRT
tRTR
7C419-15
7C421-10
7C421-15
7C425-10
7C425-15
7C429-10
7C429-15
7C433-10
Min. Max.
20
10
10
10
3
5
15
20
10
5
10
7C433-15
Max.
Min.
25
7C419-20
7C420-20
7C421-20
7C424-20
7C425-20
7C428-20
7C429-20
7C433-20
Max.
Min.
30
15
10
20
10
20
15
3
3
5
5
15
15
25
7C419-25
7C420-25
7C421-25
7C424-25
7C425-25
7C428-25
7C429-25
7C432-25
7C433-25
Min. Max.
35
25
10
25
3
5
18
35
25
5
10
15
0
35
Unit
ns
ns
ns
ns
ns
ns
ns
15
30
20
5
10
5
10
6
8
0
20
0
25
12
0
30
10
15
20
25
MR Recovery Time
10
10
10
10
ns
ns
Read HIGH to MR HIGH
10
10
15
20
20
25
25
ns
ns
ns
Write HIGH to Low Z
ns
ns
ns
ns
ns
ns
ns
Write HIGH to MR HIGH
Retransmit Cycle Time
20
15
25
30
35
Retransmit Pulse Width
10
15
20
25
ns
Retransmit Recovery Time
10
10
10
10
ns
Notes:
6. Thst conditions assume signal transition time of 3 ns or less, timing ref~
erence levels of 1.5V and output loading of the specified IorlIOH and
30 pF load capacitance, as in part (a) of AC Test Load and Waveforms,
unless otherwise specified.
7. See the last page of this specification for Group A subgroup testing information.
8.
9.
5-18
tHzRtransitionismeasuredat+ZOOmVfromVoLand-ZOOmVfrom
VOH. tDVR transition is measured at the 1.5V level. tHWZ and tLZR
transition is measured at ± 100 m V from the steady state.
tHZR and tDVR use capacitance loading as in part (b) of AC Thst Load
and Waveforms.
-~
CY7C419/21/25/29/33
'CYPRESS
'"=-
Switching Characteristics Over the Operating Rangd6, 7] (continued)
7C419-10
Parameter
7C421-10
7C421-15
7C425-10
7C425-15
7C429-10
7C429-15
7C419-20
7C420-20
7C421-20
7C424-20
7C425-20
7C428-20
7C429-20
7C433-10
Min. Max.
20
20
20
10
10
10
10
10
10
10
7C433-15
Min. Max.
25
7C433-20
Min. Max.
30
tHFH
Description
MR to EFLOW
MR to HFHIGH
tFFH
MRtoFFHIGH
tREF
tRFF
Read LOW to EF LOW
Read HIGH to FF HIGH
tWEF
tWFF
Write HIGH to EF HIGH
Write LOW to FF LOW
tWHF
Write LOW to HF LOW
tRHF
tRAE
Read HIGH to HF HIGH
Effective Read from Write HIGH
tRPE
tWAF
Effective Read Pulse Width After EF HIGH
Effective Write from Read HIGH
10
tWPF
Effective Write Pulse Width After FF HIGH
10
tXOL
tXOH
Expansion Out LOW Delay from Clock
Expansion Out HIGH Delay from Clock
tEFL
7C419-15
25
5-19
30
30
35
35
15
15
20
20
ns
ns
15
20
25
25
25
15
15
20
20
25
25
ns
ns
15
20
20
25
25
ns
ns
25
ns
25
ns
ns
15
20
15
15
10
10
Unit
ns
ns
25
15
10
7C419-25
7C420-25
7C421-25
7C424-25
7C425-25
7C428-25
7C429-25
7C432-25
7C433-25
Min. Max.
35
25
20
20
15
15
ns
ns
25
20
20
ns
ns
25
E
#t_~
'CYPRESS
CY7C419/21/25/29/33
Switching Characteristics Over the Operating Rangd6, 7] (continued)
Description
Parameter
tRe
tA
tRR
tpR
tLZRl5 ,8J
tDVRl8 ,9J
tHZR[O,~,9J
twe
tpw
tHWzl5,~J
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
Read LOW to Low Z
Data Valid After Read HIGH
Read HIGH to High Z
Write Cycle Time
Write Pulse Width
Write HIGH to Low Z
tSD
Write Recovery Time
Data Set-Up Time
tHD
Data Hold Time
tMRse
tpMR
MR Cycle Time
MR Pulse Width
tRMR
MR Recovery Time
Read HIGH to MR HIGH
tWR
tRPW
twrw
Write HIGH to MR HIGH
tRTC
tpRT
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
tRTR
tEFL
MR to EF LOW
tHFH
tFFH
tREF
MRtoHFHIGH
MR to FF HIGH
tRFF
tWEF
tWFF
Read LOW to EF LOW
Read HIGH to FF HIGH
Write HIGH to EF HIGH
tWHF
Write LOW to FF LOW
Write LOW to HF LOW
tRHF
tRAE
Read HIGH to HF HIGH
Effective Read from Write HIGH
tRPE
tWAF
Effective Read Pulse Width After EF HIGH
tWPF
Effective Write from Read HIGH
Effective Write Pulse Width After FF HIGH
tXOL
tXOH
Expansion Out LOW Delay from Clock
Expansion Out HIGH Delay from Clock
5-20
7C419-30
7C420-30
7C421-30
7C424-30
7C425-30
7C428-30
7C429-30
7C432-30
7C433-30
Min.
Max.
40
30
10
30
3
5
20
40
30
5
10
18
0
40
30
10
30
30
40
30
10
40
40
40
30
30
30
30
30
30
30
30
30
30
30
30
7C419-40
7C420-40
7C421-40
7C424-40
7C425-40
7C428-40
7C429-40
7C432-40
7C433-40
Min.
Max.
50
40
10
40
3
5
20
50
40
5
10
20
0
50
40
10
40
40
50
40
10
50
50
50
35
35
35
35
35
35
35
40
35
40
40
40
7C419-65
7C420-65
7C421-65
7C424-65
7C425-65
7C428-65
7C429-65
7C432-65
7C433-65
Min.
Max.
80
65
15
65
3
5
20
80
65
5
15
30
0
80
65
15
65
65
80
65
15
80
80
80
60
60
60
60
60
60
60
65
60
65
65
65
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CY7C419/21/25/29/33
Switching Waveforms
Asynchronous Read and Write
R
---...1
Oo-Oa--------{
w -i14:_-_-_-_-_t_Pw_-_-_-_-_---Do-Da
~
_____JI
---------1( _____---' lI-------«
DATA VALID
)>----
C420-9
Master Reset
--------+1
1 + _ - - - - tMRSC[11]
_ _ _ _ _ _~I+-----
tpMR
----------~--~---------
R,W[10]
I
C420-10
Half-Full Flag
HALF FULL +1
HALF FULL
HALF FULL
-
/
1+
tWHF .-
tRHF
I-
r
C420-11
Notes:
10. Wand R ~ VIH around the rising edge of MR.
11. tMRSC
5-21
= tpMR +
tRMR·
CY7C419/21/25/29/33
Switching Waveforms (continued)
Last Write to First Read Full Flag
LAST WRITE
R
---r-------------r~
ADDITIONAL
READS
FIRST READ
FIRST WRITE
IN
C420-12
Last Read to First Write Empty Flag
LAST READ
ADDITIONAL
WRITES
FIRST WRITE
FIRST READ
IN
DATA OUT
C420-13
Retransmit[12]
tRTC[13]
I--- tpRT
R,W
-
tRTR----
Notes:
12. EF, HF and FF may change state during retransmit as a result ofthe 0 ffset of the read and write pointers, but flags will be valid at tRTC
13. tRTC = tpRT + tRTR'
5-22
C420-14
CY7C419/21/25/29/33
Switching Waveforms (continued)
Empty Flag and Read Data Flow-Through Mode
DATA IN
W - - f - -.....
EF---t--------~-~
DATA OUT
--t---------+V
C420-15
Full Flag and Write Data Flow-Through Mode
I
w
Fi=----t----------L-.-/I
DATA IN ---r-------------~
t~,
DATAOUT----~~D-A-TA-V-AL-ID--~~-----------------0420·16
5-23
CY7C419/21/25/29/33
Switching Waveforms (continued)
Expansion Timing Diagrams
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
w---""\
XCi1 (XI2l[14j
------""'1
DATA VALID
Do-Ds
0420·17
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
Oo-Os
----+----0(
C420-18
Note:
14. Expansion Out of device 1 (XOl) is connected to Expansion In of device 2 (X12).
5-24
CY7C419/21/25/29/33
Architecture
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9,
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of duai:E~t
RAM ce~ a re~ointer, a write pointer, control signals (W, R,
XI, XO, FL, RT, MR), and Full, Half Full, and Empty flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write operations to be independent of each other, which is necessary to achieve
truly asynchronous operation of the inputs and outputs. A second
benefit is that the time required to increment the read and write
pointers is much less than the time that would be required for data
propagation through the memory, which would be the case if the
memory were implemented using the conventional register array
architecture.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset (MR)
cycle. This causes the FIFO to enter the empty condition signified
by the Empty flag (EF) being LOW, and both the Half Full (HF)
and Full flags (FF) being HIGH. Read (R:) and write (W) must be
HIGH tRPW/tWpw before and tRMR after the rising edge of MR
for a valid reset cycle. If reading from the FIFO after a reset cycle
is attempted, the outputs will all be in the high-impedance state.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FE The falling edge of W initiates a write cycle. Data appearing at the inputs (Do - Ds) tSD before and tHD after the rising
edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGH transition ofWfor an empty FIFO. HFgoes LOW
tWHF after the faIling edge ofW following the FIFO actually being
HalfFuII. Therefore, the HF is active once the FIFO is filled to half
its capacity plus one word. HFwill remain LOWwhile less than one
half oftotal memory is available for writing. The LOW-to-HIGH
transition of HF occurs tRHF after the rising edge of R when the
FIFO goes from half full + 1 to half full. HF is available in standalone and width expansion modes. FF goes LOW tWFF after the
falling edge ofW, during the cycle in which the last available location is filled. Internal logic prevents overrunning a full FIFO.
Writes to a full FIFO are ignored and the write pointer is not incremented. FF goes HIGH tRFF after a read from a full FIFO.
Readiug Data from the FIFO
The faIling edge ofR initiates a read cycle if the EF is not LOW.
Data outputs (00 - Os) are in a high-impedance condition between
read operations (R HIGH), when the FIFO is empty, or when the
FIFO is not the active device in the depth expansion mode.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EE The rising edge ofR causes the
data outputs to go to the high-impedance state and remain such until a write is performed. Reads to an empty FIFO are ignored and
do not increment the read pointer. From the empty condition, the
FIFO can be read tWEF after a valid write.
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a
number of writes equal to or less than the depth ofthe FIFO have
occurred since the last MR cycle. A LOW pulse on RT resets the
internal read pointer to the first physical location of the FIFO. R
and W must both be HIGH while and tRTR after retransmit is
LOW. With every read cycle after retransmit, previously accessed
data as well as not previously accessed data is read and the read
pointer is incremented until it is equal to the write pointer. Full,
Half Full, and Empty flags are governed by the relative locations of
the read and write pointers and are updated during a retransmit
cycle. Data written to the FIFO after activation of RT are transmitted also.
Up to the full depth of the FIFO can be repeatedly retransmitted.
Standalone/Width Expansion Modes
Standalone and width expansion modes are set by grounding Expansion In (XI) and tying First Load (FL) to Vee. FIFOs can be
expanded in width to provide word widths greater than nine in increments of nine. Duringwidth expansion mode, all control line inputs are common to all devices, and flag outputs from any device
can be monitored.
Depth Expansion Mode (see Figure 1)
Depth expansion mode is entered when, duringaMRcycle, Expansion Out (XO) of one device is connected to Expansion In (XI) of
the next device, with XO of the last device connected to XI of the
first device. In the depth expansion mode the First Load (FL) input, when grounded, indicates that this part is the first to be loaded.
All other devices must have this pin HIGH. To enable the correct
FIFO, XO is pulsed LOW when the last physical location of the
previous FIFO is written to and pulsed LOW again when the last
physical location is read. Only one FIFO is enabled for read and
one for write at any given time. All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and width.
Consequently, any depth or width FIFO can be created of word
widths in increments of9. When e~nding in depth, a composite
FF must be created by ORing the FFs together. Likewise, a composite EF is created by ORing the EFs together. HF and RT functions are not available in depth expansion mode.
Use of the Empty and Full Flags
In order to achieve the maximum frequency, the flags must be valid
at the beginning of the next cycle. However, because they can be
updated by either edge ofthe read of write signal, they must be valid by one-half of a cycle. Cypress FIFOs meet this requirement;
some competitors' FIFOs do not.
The reason why the flags are required to be valid by the next cycle
is fairly complex. It has to do with the "effective pulse width violation" phenomenon, which can occur at the full and empty boundary
conditions, if the flags are not properly used. The empty flag must
be used to prevent reading from an empty FIFO and the full flag
must be used to prevent writing into a full FIFO.
For example, consider an empty FIFO that is receiving read pulses.
Because the FIFO is empty, the read pulses are ignored by the
FIFO, and nothing happens. Next, a single word is written into the
FIFO, with a signal that is asynchronous to the read signal. The (internal) state machine in the FIFO goes from empty to empty+ 1.
However, it does this asynchronously with respect to the read signal, so that it cannot be determined what the effective pulse width
of the read signal is, because the state machine does not look at the
read signal until it goes to the empty+ 1 state. In a similar manner,
the minimum write pulse width may be violated by attempting to
write into a full FIFO, and asynchronously performing a read. The
empty and full flags are used to avoid these effective pulse width
violations, but in order to do this and operate at the maximum frequency, the flag must be valid at the beginning of the next cycle.
5-25
E
---~
~~
~,CYPRESS
CY7C419/21/25/29/33
Ixc
w
9,
D
R
FF
T
I
~
/
IV
T
Ei'
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
I
1
9,
/
F[
Q
Vc
XI
XC
~
RJ[[
FF
9~
IV
EliM'TY
Ei'
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
F[
---J
XI
XO
*
~
FF
9 ....
/
!M'i
1
V
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
1X1
Ei'
f-
-
~
• FIRST DEVICE
0420-19
Figure 1. Depth Expansion
5-26
CY7C419/21/25/29/33
Ordering Information
Speed
(ns)
10
15
20
25
30
40
Ordering Code
CY7C419-lOAC
CY7C419-1OJC
CY7C419-lOPC
CY7C419-10VC
CY7C419-15AC
CY7C419-15JC
CY7C419-15PC
CY7C419-15VC
CY7C419-15JI
CY7C419-15PI
CY7C419-15VI
CY7C419-15DMB
CY7C419-15LMB
CY7C419-20AC
CY7C419-20JC
CY7C419-20PC
CY7C419-20VC
CY7C419-20JI
CY7C419-20PI
CY7C419-20VI
CY7C419-20DMB
CY7C419-20LMB
CY7C419-25AC
CY7C419-25JC
CY7C419-25PC
CY7C419-25VC
CY7C419-25JI
CY7C419-25PI
CY7C419-25VI
CY7C419-25DMB
CY7C419-25LMB
CY7C419-30AC
CY7C419-30JC
CY7C419-30PC
CY7C419-30VC
CY7C419-30JI
CY7C419-30PI
CY7C419-30VI
CY7C419-30DMB
CY7C419-30LMB
CY7C419-40AC
CY7C419-40JC
CY7C419-40PC
CY7C419-40VC
Package
'JYpe
A32
J65
P21
V21
A32
J65
P21
V21
J65
P21
V21
D22
L55
A32
J65
P21
V21
J65
P21
V21
022
L55
A32
J65
P21
V21
J65
P21
V21
D22
L55
A32
J65
P21
V21
J65
P21
V21
D22
L55
A32
J65
P21
V21
Package 'JYpe
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
5-27
Operating
Range
Commercial
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
=-~
CY7C419/21/25/29/33
W;CYPRESS
Ordering Information (continued)
Speed
(ns)
65
Ordering Code
CY7C4I9-40JI
CY7C419-40PI
CY7C4I9-40VI
CY7C4I9-40DMB
CY7C4I9-40LMB
CY7C4I9-65AC
CY7C4I9-65JC
CY7C419-65PC
CY7C4I9-65VC
CY7C4I9-65JI
CY7C4I9-65PI
CY7C4I9-65VI
CY7C4I9-65DMB
CY7C4I9-65LMB
Package
lYpe
J65
P2I
V2I
D22
L55
A32
J65
P2I
V2I
J65
P2I
V2I
D22
L55
Package lYpe
32-Lead Plastic Leaded Chip Carrier
Operating
Range
Industrial
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Fiatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
Ordering Information (continued)
Speed
(ns)
20
25
30
40
65
Ordering Code
CY7C420-20PC
CY7C420-25PC
CY7C420-25PI
CY7C420-25DMB
CY7C420-30PC
CY7C420-30PI
CY7C420-30DMB
CY7C420-40PC
CY7C420-40PI
CY7C420-40DMB
CY7C420-65PC
CY7C420-65PI
CY7C420-65DMB
Package
lYPe
PI5
PI5
P15
D16
PI5
PI5
D16
PI5
PI5
D16
PI5
PI5
DI6
Package lYPe
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) CerDIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) CerDIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) CerDIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) CerDIP
5-28
Operating
Range
Commercial
Commercial
Industrial
Military
Commercial
Industrial
Military
Commerical
Industry
Military
Commerical
Industrial
Military
= : - -,~
CY7C419/21/25/29/33
,CYPRESS
Ordering Information (continued)
Speed
(ns)
10
Ordering Code
CY7C421-lOAC
CY7C421-1OJC
V21
A32
28-Lead (300-Mil) Molded SOJ
32-Pin Thin Plastic Quad Flatpack
J65
32-Lead Plastic Leaded Chip Carrier
P21
V21
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
J65
P21
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
V21
D22
28-Lead (300-Mil) Molded SOJ
CY7C421-15DMB
CY7C421-15LMB
L55
CY7C421- 20AC
CY7C421-2OJC
CY7C421- 20PC
A32
CY7C421- 20VC
V21
CY7C421- 20H
J65
P21
CY7C421-15AC
CY7C421-15JC
CY7C421-15PC
CY7C421 -15H
CY7C421-15PI
CY7C421-15VI
CY7C421-20PI
CY7C421- 20VI
CY7C421-20DMB
CY7C421- 20LMB
25
30
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
CY7C421-15VC
20
Package '!Ype
J65
P21
CY7C421-lOPC
CY7C421-lOVC
15
Package
1YPe
A32
J65
P21
V21
D22
Operating
Range
Commercial
28-Lead (300-Mil) Molded DIP
Commercial
Industrial
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
CY7C421- 25AC
L55
A32
CY7C421-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C421- 25PC
CY7C421-25VC
P21
V21
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
CY7C421-25JI
CY7C421-25PI
J65
P21
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
32-Pin Thin Plastic Quad Flatpack
Commercial
Industrial
CY7C421-25VI
V21
28-Lead (300-Mil) Molded SOJ
CY7C421-25DMB
CY7C421- 25LMB
D22
L55
CY7C421- 30AC
A32
28-Lead (300-Mil) CerDIP
Military
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
CY7C421-30JC
J65
P21
32-Lead Plastic Leaded Chip Carrier
CY7C421- 30PC
CY7C421- 30VC
CY7C421- 30JI
V21
J65
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
CY7C421- 30PI
P21
CY7C421- 30VI
V21
D22
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
CY7C421- 30DMB
CY7C421- 30LMB
L55
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
5-29
Industrial
Military
E
CY7C419/21/25/29/33
Ordering Information (continued)
Speed
(ns)
40
65
Ordering Code
CY7C42I-40AC
CY7C42I-4OJC
CY7C42I-40PC
CY7C42I-40VC
CY7C42I-40JI
CY7C42I-40PI
CY7C42I-40VI
CY7C42I-40DMB
CY7C42I-40LMB
CY7C42I-65AC
CY7C421-40JC
CY7C421-65PC
CY7C421-65VC
CY7C42I-65JI
CY7C42I-65PI
CY7C42I-65VI
CY7C42I-65DMB
CY7C42I-65LMB
Package
'lYpe
A32
J65
P2I
V2I
J65
P2I
V2I
D22
L55
A32
J65
P21
V2I
J65
P21
V2I
D22
L55
Operating
Range
Commercial
Package 1.Ype
32-Pin Thin Plastic Quad Fiatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-MiI) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
Industrial
Military
Commercial
Industrial
Military
Ordering Information (continued)
Speed
(ns)
20
25
30
40
65
Ordering Code
CY7C424- 20PC
CY7C424-25PC
CY7C424-25PI
CY7C424-25DMB
CY7C424-30PC
CY7C424-30PI
CY7C424- 30DMB
CY7C424-40PC
CY7C424-40PI
CY7C424-40DMB
CY7C424-65PC
CY7C424-65PI
CY7C424-65DMB
Package
'lYpe
PIS
PIS
PIS
D16
PIS
PIS
D16
PIS
PIS
DI6
PIS
PIS
D16
Package 1.Ype
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) CerDIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) CerDIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) CerDIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) CerDIP
5-30
Operating
Range
Commercial
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
-~
-
CY7C419/21/25/29/33
'CYPRESS
Ordering Information (continued)
Speed
(ns)
10
15
20
25
30
Ordering Code
CY7C425 -lOAC
CY7C425 -lOJC
CY7C425 -lOPC
CY7C425 -lOVC
CY7C425-15AC
CY7C425-15JC
CY7C425 -15PC
CY7C425 -15VC
CY7C425 -15JI
CY7C425 -15PI
CY7C425 -15VI
CY7C425 -150MB
CY7C425 -15LMB
CY7C425-20AC
CY7C425-20JC
CY7C425 - 20PC
CY7C425 - 20VC
CY7C425 - 20JI
CY7C425-20PI
CY7C425-20VI
CY7C425-200MB
CY7C425-20LMB
CY7C425-25AC
CY7C425 - 25JC
CY7C425-25PC
CY7C425 - 25VC
CY7C425-25JI
CY7C425-25PI
CY7C425-25VI
CY7C425-250MB
CY7C425 - 25LMB
CY7C425 - 30AC
CY7C425-30JC
CY7C425 - 30PC
CY7C425 - 30VC
CY7C425-30JI
CY7C425-30PI
CY7C425 - 30VI
CY7C425-300MB
CY7C425-30LMB
Package
'JYpe
A32
J65
P21
V21
A32
J65
P21
V21
J65
P21
V21
022
L55
A32
J65
P21
V21
J65
P21
V21
022
L55
A32
J65
P21
V21
J65
P21
V21
022
L55
A32
J65
P21
V21
J65
P21
V21
022
L55
Package 'JYpe
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
5-31
Operating
Range
Commercial
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
I
=--:~
CY7C419/21/25/29/33
_"CYPRESS
Ordering Information (continued)
Speed
(ns)
40
65
Ordering Code
Package
'JYpe
Package 'lYpe
Operating
Range
A32
32-Pin Thin Plastic Quad Fiatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-MiI) Molded DIP
28-Lead (300-MiI) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Fiatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-MiI) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
Commercial
CY7C425-40AC
CY7C425-40JC
CY7C425-40PC
CY7C425-40VC
CY7C425-40JI
CY7C425-40PI
CY7C425-40VI
CY7C425-40DMB
CY7C425 -40LMB
CY7C425-65AC
CY7C425-65JC
CY7C425-65PC
CY7C425-65VC
CY7C425-65JI
CY7C425-65PI
CY7C425-65VI
CY7C425 -65DMB
CY7C425-65LMB
J65
P21
V21
J65
P21
V21
D22
L55
A32
J65
P21
V21
J65
P21
V21
D22
L55
Industrial
Military
Commercial
Industrial
Military
Ordering Information (continued)
Speed
(ns)
Ordering Code
Package
'lYpe
Package 'lYpe
Operating
Range
20
CY7C428-20PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
25
CY7C428-25PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
CY7C428-25PI
P15
28-Lead (600-Mil) Molded DIP
Industrial
CY7C428- 25DMB
D16
28-Lead (600-Mil) CerDIP
Military
CY7C428-30PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
Industrial
30
40
65
CY7C428-30PI
P15
28-Lead (600-Mil) Molded DIP
CY7C428-30DMB
D16
28-Lead (600-Mil) CerDIP
Military
CY7C428-40PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
Industrial
CY7C428-40PI
P15
28-Lead (600-Mil) Molded DIP
CY7C428-40DMB
D16
28-Lead (600-Mil) CerDIP
Military
CY7C428-65PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
CY7C428-65PI
P15
28-Lead (600-Mil) Molded DIP
Industrial
CY7C428-65DMB
D16
28-Lead (600-Mil) CerDIP
Military
5-32
==--':;i~
CY7C419/21/25/29/33
; CYPRESS
Ordering Information (continued)
Speed
(ns)
10
15
20
25
30
40
Ordering Code
CY7C429-lOAC
CY7C429-101C
CY7C429-lOPC
CY7C429-lOVC
CY7C429-15AC
CY7C429-151C
CY7C429-15PC
CY7C429-15VC
CY7C429-15JI
CY7C429-15PI
CY7C429-15VI
CY7C429-150MB
CY7C429-15LMB
CY7C429-20AC
CY7C429-2OJC
CY7C429-20PC
CY7C429-20VC
CY7C429-20JI
CY7C429-20PI
CY7C429-20VI
CY7C429-200MB
CY7C429- 20LMB
CY7C429-25AC
CY7C429-251C
CY7C429-25PC
CY7C429-25VC
CY7C429-25JI
CY7C429-25PI
CY7C429-25VI
CY7C429- 250MB
CY7C429- 25LMB
CY7C429-30AC
CY7C429-301C
CY7C429-30PC
CY7C429-30VC
CY7C429-30JI
CY7C429-30PI
CY7C429-30VI
CY7C429-300MB
CY7C429- 30LMB
CY7C429-40AC
CY7C429-4OJC
CY7C429-40PC
CY7C429-40VC
Package
lYpe
Package lYpe
Operating
Range
A32
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
28-Lead (300-Mil) CerOIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Fiatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Fiatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Fiatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
Commercial
165
P21
V21
A32
165
P21
V21
165
P21
V21
022
L55
A32
165
P21
V21
165
P21
V21
022
L55
A32
165
P21
V21
165
P21
V21
022
L55
A32
165
P21
V21
165
P21
V21
022
L55
A32
165
P21
V21
5-33
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Ii
CY7C419/21/25/29/33
Ordering Information (continued)
Speed
(ns)
40
65
Ordering Code
Package
1Ype
CY7C429-40JI
CY7C429-40PI
CY7C429-40VI
CY7C429-40DMB
CY7C429-40LMB
CY7C429-65AC
CY7C429-65JC
CY7C429-65PC
CY7C429-65VC
CY7C429-65JI
CY7C429-65PI
CY7C429-65VI
CY7C429-65DMB
CY7C429-65LMB
J65
P21
V21
D22
L55
A32
J65
P21
V21
J65
P21
V21
D22
L55
Package 1Ype
Operating
Range
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (3OO-MiI) Molded DIP
28-Lead (300-MiI) Molded SOJ
28-Lead (300-MiI) CerDIP
Military
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad F1atpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead(300-MiI) Molded DIP
28-Lead (300-MiI) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-MiI) Molded DIP
28-Lead (300-MiI) Molded SOJ
28-Lead (300-MiI) CerDIP
Military
32-Pin Rectangular Leadless Chip Carrier
Ordering Information (continued)
Speed
(ns)
Ordering Code
Package
Name
Package 1YPe
Operating
Range
25
CY7C432-25PC
P15
28-Lead (600-MiI) Molded DIP
Commercial
30
CY7C432-30PC
P15
28-Lead (600-MiI) Molded DIP
Commerical
CY7C432-30PI
P15
28-Lead (600-MiI) Molded DIP
Industrial
CY7C432- 30DMB
D16
28-Lead (600-MiI) CerDIP
Military
CY7C432-40PC
P15
28-Lead (600-MiI) Molded DIP
Commercial
CY7C432-40PI
P15
28-Lead (600-MiI) Molded DIP
Industrial
CY7C432-40DMB
D16
28-Lead (600-MiI) CerDIP
Military
CY7C432-65PC
P15
28-Lead (600-MiI) Molded DIP
Commercial
40
65
CY7C432-65PI
P15
28-Lead (600-MiI) Molded DIP
Industrial
CY7C432-65DMB
D16
28-Lead (600-MiI) CerDIP
Military
Ordering Information (continued)
Speed
(ns)
10
15
Ordering Code
CY7C433-lOAC
CY7C433-lOJC
CY7C433 -lOPC
CY7C433-10VC
CY7C433 -15AC
CY7C433-15JC
CY7C433 -15PC
CY7C433 -15VC
CY7C433-15JI
CY7C433-15PI
CY7C433-15VI
CY7C433-15DMB
CY7C433 -15LMB
Package
Name
A32
J65
P21
V21
A32
J65
P21
V21
J65
P21
V21
D22
L55
Package 1YPe
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-MiI) Molded DIP
28-Lead (300-MiI) Molded SOJ
32-Pin Thin Plastic Quad F1atpack
Operating
Range
Commercial
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-MiI) Molded DIP
28-Lead (300-MiI) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-MiI) Molded DIP
28-Lead (300-MiI) Molded SOJ
28-Lead (300-MiI) CerDIP
Military
32-Pin Rectangular Leadless Chip Carrier
5-34
~
.
-,;~
CY7C419/21/25/29/33
'CYPRESS
Ordering Information (continued)
Speed
(ns)
20
25
30
40
65
Ordering Code
CY7C433-20AC
CY7C433 - 201C
CY7C433-20PC
CY7C433-20VC
CY7C433-20Jl
CY7C433-20PI
CY7C433-20VI
CY7C433-20DMB
CY7C433 - 20LMB
CY7C433-25AC
CY7C433-251C
CY7C433-25PC
CY7C433-25VC
CY7C433 - 2511
CY7C433 - 25PI
CY7C433 - 25VI
CY7C433 - 25DMB
CY7C433 - 25LMB
CY7C433 - 30AC
CY7C433-3OJC
CY7C433-30PC
CY7C433-30VC
CY7C433-30JI
CY7C433-30PI
CY7C433 - 30VI
CY7C433-30DMB
CY7C433-30LMB
CY7C433-40AC
CY7C433-401C
CY7C433-40PC
CY7C433-40VC
CY7C433-4OJI
CY7C433-40PI
CY7C433 - 40VI
CY7C433-40DMB
CY7C433 -40LMB
CY7C433-65AC
CY7C433-651C
CY7C433-65PC
CY7C433-65VC
CY7C433-6511
CY7C433-65PI
CY7C433-65VI
CY7C433-65DMB
CY7C433-65LMB
Package
Name
A32
165
P21
V21
165
P21
V2l
D22
L55
A32
165
P21
V21
165
P21
V21
D22
L55
A32
165
P21
V21
165
P21
V21
D22
L55
A32
165
P21
V21
165
P21
V21
D22
L55
A32
165
P21
V21
J65
P21
V21
D22
L55
Package 1Ype
Operating
Range
32-Pin Thin Plastic Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
28-Lead (300-Mil) CerDIP
Military
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
28-Lead (300-Mil) CerDIP
Military
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
28-Lead (300-Mil) CerDIP
Military
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOl
28-Lead (300-Mil) CerDIP
Military
32-Pin Rectangular Leadless Chip Carrier
5-35
E
~~YPRESS
CY7C419/21/25/29/33
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIH
VILMax.
IIX
Icc
Icc!
ISB!
ISB2
los
Switching Characteristics
Parameters
Subgroups
9,10,11
9,10,11
tA
9,10,11
tRR
9,10,11
tpR
9,10,11
tDVR
9,10,11
twc
9,10,11
tpw
9,10,11
tWR
9,10,11
tSD
9,10,11
tHD
9,10,11
tMRSC
9,10,11
tpMR
9,10,11
tRMR
9,10,11
tRPw
9,10,11
twpw
9,10,11
tRTC
9,10,11
tpRT
9,10,11
tRJ'R
9,10,11
tEFL
9,10,11
tHFH
9,10,11
tFFH
9,10,11
tREF
9,10,11
tRFF
9,10,11
tWEF
9,10,11
tWFF
9,10,11
tWHF
9,10,11
tRHF
9,10,11
tRAE
9,10,11
tRPE
9,10,11
tWAF
9,10,11
tWPF
9,10,11
tXOL
9,10,11
tXOH
Document #: 38-00079-L
tRC
5-36
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64/256/512/1K/2K/4K/8K X 9
Synchronous FIFOs
Features
•
•
•
•
•
•
•
•
64 x 9 (CY7C4421)
256 x 9 (CY7C4201)
512 x 9 (CY7C4211)
lK x 9 (CY7C4221)
2K x 9 (CY7C4231)
4K x 9 (CY7C4241)
8K x 9 (CY7C4251)
High-speed 100-MHz operation (10 ns
read/write cycle time)
• Pin compatihle and functionally
equivalent to IDT72421, 72201, 72211,
72221,72231,72241
• Fully asynchronous and simultaneous read and write operation
• Four status flags: Empty, Full, and
programmable Almost Empty/Almost
Full
• Expandable in width
• Low operating power
ICC2 = 50 rnA
• Output Enable (OE) pin
• 32-pin PLCC/TQFP
Functional Description
The CY7C42Xl are high-speed, low-power, first-in first-out (FIFO) memories with
clocked read and write interfaces, All are 9
bits wide, TheCY7C42Xl arepin-compatible to IDT722XL The CY7C42Xl can be
cascaded to increase FIFO depth, Programmable features include Almost Full/
Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.
These FIFOs have 9-bit input and output
ports that are controlled by separate clock
and enable signals. The input port is controlled by a free-running clock (WCLK)
and two write-enable pins (WENl,
WEN2/LD).
When WENl is LOW and WEN2/LD is
HIGH, data is written into the FIFO on
the rising edge of the WCLKsignal. While
WENl, WEN2/LD is held active, data is
continually written into the FIFO on each
WCLKcycle. The output port is controlled
in a similar manner by a free-running read
clock (RCLK) and two read enable pins
(RENl, REN2).
In addition, the
CY7C42Xl has an output enable pin
(OE). The read (RCLK) and write
(WCLK) clocks may be tied together for
single-clock operation or the two clock, may
be run independently for asynchronous
read/write applications. Clock frequencies
up to 100 MHz are achievable.
Depth expansion is possible using one enable input for system control, while the
other enable is controlled by expansion
logic to direct the flow of data.
Pin Configuration
Logic Block Diagram
PLCC
Top View
Do - 8
"" ID
<0 r-- co
0000000
N
4
<'l
3
2
1
0,
Do
AS
WEN1
WCLK
WEN2/[[)
PAF
PAE
GND
Vee
REN1
RCLK
10
11
REm
DE
12
13
,----r~-I--~~ IT
as
21
14151617181920
Itt Itt
PAE
PAF
L.._ _--.-_ _~.
08
07
06
a 00 ccJ
TQFP
FF
Top View
33oroncf6"0'122
00 - 8
RCLK
REN1
42X1-2
0,
24
WEN1
Do
23
WCLK
PAF
22
WEN2/CO
PAE
Vee
GND
AEN1
08
07
RCLK
06
REN2
05
REN2
42X1-1
~
5-37
Itt Itt 00
a
00
42X1-3
-
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
-.,~
'CYPRESS
Functional Description (continued)
The CY7C42X1 provides four status pins: Empty, Full, Almost
Empty, Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags
default to Empty-7 and Full-7.
The flags are synchronous, i.e., they change state relative to either
the read clock (RCLK) or the write clock (WCLK). When entering
or exiting the Empty and Almost Empty states, the flags are updated exclusively by the RCLK. The flags denoting Almost Full,
and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.65ft N-Well
CMOS technology. Input ESD protection is greater than 4001 V,
and latch-up is prevented by the use of guard rings.
Selection Guide
7C42Xl-1O
7C42Xl-15
7C42Xl-25
7C42Xl-35
Maximum Frequency (MHz)
100
66.7
40
28.6
Maximum Access Time (ns)
8
10
15
20
Minimum Cycle Time (ns)
10
15
25
35
Minimum Data or Enable Set-Up (ns)
3
4
6
7
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Operating Current (Iccs)
(rnA)
0.5
1
1
2
I Commercial
8
10
15
20
50
50
50
50
I Industrial
70
70
70
70
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to + 150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential ........ -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to + 7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Note:
1. TA is the "instant on" case temperature.
5-38
Range
Commercial
Industrial[l]
Ambient
Temperature
O°Cto +70°C
Vee
5V ± 10%
-40°C to +85°C
5V ± 10%
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
~-~
lCYPRESS
Pin Definitions
Signal Name
Description
I/O
Description
Data Inputs
I
Qo-s
Data Outputs
0
Data Outputs for 9-bit bus
WENl
Write Enable 1
I
The only write enable when device is configured to have programmable fla~ Data is written on a LOW-to-HIGH transition ofWCLK when WENl is asserted and FF is HIGH. If
the FIFO is configured to have two write enables, data iswritten on aLOW-to-HIGH transition of WCLK when WENl is WW and WEN2/LD and FF are HIGH.
WEN2/LD
Write Enable 2
Dual Mode Pin
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin operates as a control to write or read the programmable flag offsets. WENl must be LOW and
WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held
LOW to write or lead the programmable flag offsets.
Do-s
Load
Data Inputs for 9-bit bus
RENl,REN2
Read Enable
Inputs
I
Enables the device for Read operation.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WENl is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out ofthe FIFO when RENl and REN2 are LOW and the FIFO
is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flagoffset register.
EF
Empty Flag
0
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
0
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
0
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO.
PAP
Programmable
Almost Full
0
When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO's data outputs drive the bus to which they are connected. If OE
is HIGH, the FIFO's outputs are in High Z (high-impedance) state.
5-39
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
=-.~
=;sg., CYPRESS
Electrical Characteristics Over the Operating Rangd2]
Parameter
Description
7C42XI-IO
Min. Max.
Test Conditions
7C42Xl-15
Min. Max.
7C42Xl-25
Min. Max.
2.4
VOH
Output HIGH Voltage Vee = Min.,
10H = -2.0 rnA
VOL
Output LOW Voltage
VIR
Input HIGH Voltage
2.2
VIL
Input LOW Voltage
-3.0
Vee
0.8
-3.0
Vee
0.8
-3.0
Vee
0.8
IIX
Input Leakage
Current
Vee = Max.
-10
+10
-10
+10
-10
+10
IOS[3]
Output Short
Circuit Current
Vee = Max.,
VOUT = GND
-90
10ZL
10ZH
leel[4]
Output OFF,
High Z Current
OE~ VIR,
Vss < Va < Vee
Com'!
Vee = Max.,
lOUT = ornA
Ind
-10
Operating Current
lee2[5]
Operating Current
ISB[6]
Standby Current
2.4
2.4
2.4
0.4
0.4
Vee = Min.,
10L = 8.0 rnA
2.2
-90
+10
-10
0.4
2.2
-90
+10
7C42Xl- 35
Min. Max.
-10
V
0.4
V
Vee
0.8
V
-3.0
-10
+10
fAA
2.2
-90
+10
Unit
.,-10
V
rnA
+10
fAA
150
130
75
60
rnA
170
150
95
80
rnA
Vee = Max.,
lOUT = ornA
Com'!
50
50
50
50
rnA
Ind
70
70
70
70
rnA
Vee = Max.,
lOUT = ornA
Com'!
30
28
25
22
rnA
Ind
40
38
35
35
rnA
Capacitance[7]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 2SoC, f = 1 MHz,
Vee = 5.0V
Max.
5
7
Unit
pF
pF
AC Test Loads and Waveforms[8, 9]
R11.1Kg
ALL INPUT PULSES
OUTP~~~
I
CL
INCLUDING _
JIG AND SCOPE
Equivalent to:
3.0V
---':::Jr------:>L.
GND
R2
680g
_
42X1-4
42Xl-5
THEVENIN EQUIVALENT
420g
OUTPUT 00---"''1''''''---<10 1.91V
Notes:
2. See the last page ofthis specification for Group A subgroup testing information.
3. Thst no more than one output at a time for not more than one second.
4. Input signals switch from OV to 3V with a rise/fall time of less than 3
ns, clocks and clock enables switch at maximum frequency (fMAX),
while data inputs switch at fMAX/2_ Outputs are unloaded_
5. Input signals switch from OV to 3V with a rise/fall time less than 3 ns,
clocks and clock enables switch at 20 MHz, while the data inputs switch
at 10 MHz. Outputs are unloaded.
6.
7.
8.
9.
5-40
All input signals are connected to V ce. All outputs are unloaded.
Read aod write clocks switch at maximum frequency (fMAXl.
Thsted initially and after aoy design or process changes that may affect
these parameters.
CL = 30 pF for all AC parameters except for 10HZ.
CL = 5 pFfortoHZ.
=--
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
~
.;CYPRESS
Switching Characteristics Over the Operating Range
Parameter
Description
7C42XI-IO 7C42Xl-15
7C42Xl-25
7C42Xl-35
Min.
Min.
Min.
Max.
Min.
Max.
Max.
Max.
Unit
ts
Clock Cycle Frequency
tA
Data Access Time
tCLK
Clock Cycle Time
10
15
25
35
ns
tCLKH
Clock HIGH Time
4.5
6
10
14
ns
tCLKL
Clock LOW Time
4.5
6
10
14
ns
tDS
Data Set-Up Time
3
4
6
7
ns
tDH
Data Hold Time
100
2
8
66.7
2
10
40
2
15
2
28.6
ns
20
ns
0.5
1
1
2
ns
3
4
6
7
ns
ns
tENS
Enable Set-Up Time
tENH
Enable Hold Time
0.5
1
1
2
tRS
Reset Pulse Width[lOj
10
15
25
35
ns
tRSS
Reset Set-Up Time
8
10
15
20
ns
tRSR
Reset Recovery Time
8
tRSF
Reset to Flag and Output Time
tOLZ
Output Enable to Output in Low Z[lIj
0
tOE
Output Enable to Output Valid
3
7
3
8
3
12
3
15
ns
tOHZ
Output Enable to Output in High Z[ll]
3
7
3
8
3
12
3
15
ns
tWFF
Write Clock to Full Flag
10
15
20
ns
tREF
Read Clock to Empty Flag
8
10
15
20
ns
tPAF
Oock to Programmable Almost-Full Flag
8
10
15
20
ns
20
ns
10
10
15
15
0
8
20
25
0
ns
35
0
ns
ns
tpAE
Oock to Programmable Almost-Full Flag
tSKEW!
Skew Time between Read Clock and Write Clock
for Full Flag
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write Clock
for Empty Flag
10
15
18
20
ns
Notes:
10. Pulse widths less than minimum values are not allowed.
15
10
8
11. Values guaranteed by design, not currently tested.
5-41
E
~
I
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
?cYPRESS
Switching Waveforms
Write Cycle Timing
WCLK
DO-Os
WEN2
----------i:::::~tv:~==~
(if applicable)
FF
RCLK
/
42XH
Read Cycle Timing
--;'--ICLKL
,------.
RCLK
VAUDDATA
10HZ
OE
WCLK
WEN1
WEN2
"/
42X1-7
Notes:
12. tSKEW! is the minimum time between a rising RCLK edge and a rising
WCLK edge to guarantee that FF will go HIGH during the current
clock cycle. If the time between the risin~ge of RCLK and the rising
edge ofWCLKis less than tSKEW!. then FF may not change state until
the next WCLK edge.
13. tSKEW2 is the minimum time between a rising WCLK edge and a rising
RCLK edge to guarantee that EF will go HIGH during the current
clock cycle. It the time between the rising ed~of WCLK and the rising edge of RCLK is less than tSKEW2. then EF may not change state
until the next RCLK edge.
5-42
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Reset Timing[14]
- - _ I - - - - - - t R s -------i~
,,------------------
1 4 - - - - tRSS - - - -....o-----tRSR - - - - - I..~I
J - - - - tRSS - - - - * o - - - - - t R S R -----I~I
1 4 - - - - tRSS - - - -....o-----tRSR
-----I~I
WEN2f[D[ 16l
OE=1[ 15l
_______________________ _ _fr_ ________
_
-----------------------\:".
Notes:
14. The clocks (RCLK. WCLK) can be free-running during reset.
15. After reset, the outputs will be LOW if OE = 0 and three-state if
OE = 1.
OE~;
--
-4~~-B
16. Holding WEN2/LD HIGH durin~set will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the
pin act as a load enable for the programmable flag offset registers.
5-43
I
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
00- Os
WEN2
(if applicable)
RCLK
Qo-Qs
Do
toLZ
________________________
~~---------tOE----------~
42X1-9
Notes:
17. When tSKEW2'?' minimum specification, tFRdmaximum) = tCLJ( +
tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) =
either Z*tCLR + tSKEW2 or tCLK + !sKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
18. The first word is available the cycle after EF goes HIGH, always.
5-44
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Empty Flag Timing
WCLK
Do- Ds
WEN2
(if applicable)
RCLK
LOW
aD-aS
------------~~~~--------~
DATA IN OUTPUT REGISTER
DATA READ
42X1-10
5-45
I
----........
~(f~
CY7C4421/420l/4211/4221
_ r; CYPRESS
===========~C=Y7~C;4;;23==1~/4=24:;;l~/4==25~1
Switching Waveforms (continued)
Full Flag Timing
NO WRITE
NO WRITE
WCLK
FF
________+-______- J
WEN2
(if applicable)
RCLK
0 0 -08 ________________-J
42X1-11
5-46
~
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
~'CYPRESS
Switching Waveforms
(continued)
Programmable Almost Empty Flag Timing
tCLKH
WCLK
WEN2
(if applicable)
_ _ _ _"""'........J
N + 1 WORDS
IN FIFO
RCLK
42X1-12
Programmable Almost Full Flag Timing
E
tCLKH
WCLK
WEN2
(if applicable)
--------'~~I~~~~~~---~----------------4_-------_
________________
~
________
FULL - M + 1 WORDS
IN FIFO
~ AF~
__
tP__
_____________
_+---J
FULL - M WORDS
IN FIFOf241
RCLK
42Xl-13
Notes:
19. tSKEW2 is the minimum time between a rising WCLK and a rising
RCLK edge for PAE to change state during that clock cycle. If the time
hetween the edge ofWCLK and the rising RCLK is less than tSKEW2,
then PAE may not change state until the next RCLK.
20. PAE offset - n.
21. If a read is preformed on this rising edge of the read clock, there will
be Empty + (n-1) words in the FIFO when PAEgoes Law.
22. If a write is performed on this rising edge of the write clock, there will
be Full- (m-1) words of the FIFO when PAP goes Law.
23. PAP offset = m.
24. 64-m words for CY7C4421, 256-m words in FIFO for CY7C4201,
512-m words for CY7C4211, lO24-m words for CY7C4221,
2048-m words for CY7C4231, 4096-m words for CY7C4241,
8192-m words for CY7C4251.
25. tSKEW2 is the minimum time between a rising RCLK edge and a rising
WCLK edge for PAP to change during that clock cycle. If the time between the rising ed~f RCLK and the rising edge of WCLK is less
than tSKEW2, then PAF may not change state until the next WCLK
rising.
5-47
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Write Programmable Registers
WCLK
WEN2!ID
Do- DB
PAEOFFSET
LSB
PAEOFFSET
MSB
PAFOFFSET
LSB
PAFOFFSET
MSB
42X1-14
Read Programmable Registers
RCLK
WEN2/ID
PAE OFFSET LSB
00- 0 8
PAE OFFSET MSB
42X1-15
Architecture
The CY7C42X1 consists of an array of 64 to 8K words of 9 bits
each (implemented by a dual-port array of SRAM cells), a read
pointer, a write pointer, control signals ..@CLK, WCLK, REN1,
REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAP, FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by EF
being LOW. All data outputs (Qo _ 8) go LOW tRSF after the rising
edge ofRS. In orderfor the FIFO to reset to its default state, a falling e~ must occur on RS and the user must not read or write
while RS is LOW. All flags are guaranteed to be valid tRSF after irS
is taken LOW.
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active
HIGH, data present on the Do _ 8 pins is written into the FIFO on
each rising edge of the WCLK signal. Similarly, when the REN1
and REN2 signals are active LOW, data in the FIFO memory will
be presented on the Qo _ 8 outputs. New data will be presented
on each rising edge of RCLK while REN1 and REN2 are active.
REN1 and REN2 must set up tENS before RCLK for it to be a
valid read function. WEN1 and WEN2 must occur tENS before
WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Qo - 8
outputs when OE is asserted. When OE is enabled (LOW), data in
the output register will be available to the Qo _ 8 outputs after tOE.
If devices are cascaded, the OE function will only output data on
the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the
data ofthe last valid read on its Qo _ 8 outputs even after additional
reads occur.
Write Enable t (WENt) - If the FIFO is configured for programmable flags, Write Enable 1 (WEN1) is the only write enable control pin. In this configuration, when Write Enable 1 (WEN1) is
LOW, data can be loaded into the input register and RAM array on
the LOW-to-HIGH transition of every write clock (WCLK). Data
5-48
-
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
-,~
2&7 CYPRESS
is stored is the RAM array sequentially and independently of any
on-going read operation.
Write Enable 2/Load
u
~
~
2
z
"
3
OUTPUT VOLTAGE
f---~-----I
V
M
4
iil
60
~
40
20
0
./
100
80
/
/
/
V
/
oV
o
2
OUTPUT VOLTAGE
5-52
3
M
l/
o
~
200
Vee = 5.0V
TA = 25°C
400
600
800 1000
CAPACITANCE (pF)
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE
160
140
120
o
V'
.~
10
AMBIENT TEMPERATURE (0G)
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE
"
0.75
0.50 '----------''---------55
25
125
6
5.5
SUPPLY VOLTAGE
45
./
25
~ 1.00 F~--!.....---~
V
55
~
::0
0.9
100
FREQUENCY (MHz)
NORMALIZED tA VS.
AMBIENT TEMPERATURE
1.2
1/
o
AMBIENT TEMPERATURE (0G)
NORMALIZED tA VS. SUPPLY
VOLTAGE
I
1/
Z
0.80 ' - - - - - . 1 - - - - - -55
25
125
6
= 3.0V
VIN
0
W
I
= 5.0V
.9 1.00 f-- TA = 25°C
~
II:
Vee
()
o
oZ
VS.
,------~---~
()
]
NORMALIZED SUPPLY CURRENT
FREQUENCY
NORMALIZED SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
VS.
4
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
-~
=
='CYPRESS
Ordering Information
Speed
(ns)
10
15
25
35
Speed
(ns)
10
15
25
35
Ordering Code
Package
Name
Package
lYpe
CY7C4421-lOAC
A32
32-Lead Thin Quad Flatpack
CY7C4421-lOJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4421-lOAl
A32
32-Lead Thin Quad Flatpack
CY7C4421-lOJI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4421-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4421-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4421 -15AI
A32
32-Lead Thin Quad Fiatpack
CY7C4421-15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4421-25AC
A32
32-Lead Thin Quad Fiatpack
CY7C4421- 25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4421-25AI
A32
32-Lead Thin Quad Fiatpack
CY7C4421- 25JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4421-35AC
A32
32-Lead Thin Quad Fiatpack
CY7C4421-35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4421- 35Al
A32
32-Lead Thin Quad Flatpack
CY7C4421- 35JI
J65
32-Lead Plastic Leaded Chip Carrier
Package
Name
Package
lYpe
Ordering Code
CY7C4201-lOAC
A32
32-Lead Thin Quad Flatpack
CY7C4201-lOJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4201-lOAl
A32
32-Lead Thin Quad Flatpack
CY7C4201-lOJI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4201-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4201-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4201-15Al
A32
32-Lead Thin Quad Flatpack
CY7C4201-15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4201-25AC
A32
32-Lead Thin Quad Flatpack
CY7C4201-25JC
J65
CY7C4201- 25Al
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
A32
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
Industrial
CY7C4201- 25JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4201-35AC
A32
32-Lead Thin Quad Fiatpack
CY7C4201-35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4201-35Al
A32
32-Lead Thin Quad Flatpack
CY7C4201- 3511
J65
32-Lead Plastic Leaded Chip Carrier
5-53
Commercial
Industrial
I
1;~YPRESS
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Ordering Information (continued)
Speed
(ns)
10
15
25
35
Speed
(ns)
10
15
25
35
Ordering Code
Package
Name
Package
1Ype
CY7C4211-lOAC
A32
32-Lead Thin Quad Flatpack
CY7C4211-1OJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4211-lOAI
A32
32-Lead Thin Quad Flatpack
CY7C4211-10JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4211-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4211-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4211-15AI
A32
32-Lead Thin Quad Flatpack
CY7C4211-15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4211- 25AC
A32
32-Lead Thin Quad Flatpack
CY7C4211-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4211- 25AI
A32
32-Lead Thin Quad Flatpack
CY7C4211- 2511
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4211-35AC
A32
32-Lead Thin Quad Flatpack
CY7C4211-35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4211-35AI
A32
32-Lead Thin Quad Flatpack
CY7C4211- 3511
J65
32-Lead Plastic Leaded Chip Carrier
Package
Name
Package
1Ype
Ordering Code
CY7C4221-lOAC
A32
32-Lead Thin Quad Flatpack
CY7C4221-lOJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4221-10AI
A32
32-Lead Thin Quad Flatpack
CY7C4221-lOJI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4221-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4221-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4221-15AI
A32
32-Lead Thin Quad Flatpack
CY7C4221-15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4221-25AC
A32
32-Lead Thin Quad Flatpack
CY7C4221- 25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4221- 25AI
A32
32-Lead Thin Quad Flatpack
CY7C4221- 2511
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4221-35AC
A32
32-Lead Thin Quad Flatpack
CY7C4221-35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4221- 35AI
A32
32-Lead Thin Quad Flatpack
CY7C4221- 35JI
J65
32-Lead Plastic Leaded Chip Carrier
5-54
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
~
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
=- -:~
CYPRESS
=:::,
Ordering Infonnation (continued)
Speed
(ns)
10
15
25
35
Speed
(ns)
10
15
25
35
Ordering Code
Package
Name
Package
lYpe
CY7C4231-lOAC
A32
32-Lead Thin Quad Flatpack
CY7C4231-1OJC
165
32-Lead Plastic Leaded Chip Carrier
CY7C4231-lOAI
A32
32-Lead Thin Quad Fiatpack
CY7C4231 -lOJI
165
32-Lead Plastic Leaded Chip Carrier
CY7C4231 -15AC
A32
32-Lead Thin Quad Flatpack
CY7C4231-151C
165
32-Lead Plastic Leaded Chip Carrier
CY7C4231-15AI
A32
32-Lead Thin Quad Fiatpack
CY7C4231-15JI
165
32-Lead Plastic Leaded Chip Carrier
CY7C4231- 25AC
A32
32-Lead Thin Quad Flatpack
CY7C4231-251C
165
32-Lead Plastic Leaded Chip Carrier
CY7C4231-25AI
A32
32-Lead Thin Quad Flatpack
CY7C4231-25JI
165
32-Lead Plastic Leaded Chip Carrier
CY7C4231- 35AC
A32
32-Lead Thin Quad Fiatpack
CY7C4231-351C
165
32-Lead Plastic Leaded Chip Carrier
CY7C4231- 35AI
A32
32-Lead Thin Quad Fiatpack
CY7C4231- 35JI
165
32-Lead Plastic Leaded Chip Carrier
Package
Name
CY7C4241-lOAC
A32
Package
lYpe
32-Lead Thin Quad Flatpack
CY7C4241-101C
165
32-Lead Plastic Leaded Chip Carrier
CY7C4241-lOAI
A32
32-Lead Thin Quad Flatpack
CY7C4241-10JI
165
32-Lead Plastic Leaded Chip Carrier
CY7C4241-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4241-151C
165
32-Lead Plastic Leaded Chip Carrier
CY7C4241-15AI
A32
32-Lead Thin Quad Flatpack
CY7C4241-15JI
165
32-Lead Plastic Leaded Chip Carrier
CY7C4241- 25AC
A32
32-Lead Thin Quad Flatpack
CY7C4241-251C
165
32-Lead Plastic Leaded Chip Carrier
CY7C4241-25AI
A32
32-Lead Thin Quad Flatpack
CY7C4241-25JI
165
32-Lead Plastic Leaded Chip Carrier
CY7C4241 - 35AC
A32
32-Lead Thin Quad Fiatpack
CY7C4241-351C
165
32-Lead Plastic Leaded Chip Carrier
CY7C4241- 35AI
A32
32-Lead Thin Quad Flatpack
CY7C4241-35JI
J65
32-Lead Plastic Leaded Chip Carrier
Ordering Code
5-55
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
E
CY7C4421/420l/4211/4221
CY7C4231/4241/4251
Ordering Information (continued)
CY7C4251-lOAC
A32
Package
1YPe
32-Lead Thin Quad Fiatpack
CY7C4251-lOJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4251-lOAI
A32
32-Lead Thin Quad Fiatpack
CY7C4251-lOJI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4251-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4251-15JC
J65
32-Lead Plastic Leaded Chip Carrier
Speed
(ns)
10
15
25
35
Ordering Code
Package
Name
CY7C4251-15AI
A32
32-Lead Thin Quad Fiatpack
CY7C4251-15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4251-25AC
A32
32-Lead Thin Quad Flatpack
CY7C4251-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4251-25AI
A32
32-Lead Thin Quad Fiatpack
CY7C4251-25JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4251- 35AC
A32
32-Lead Thin Quad Fiatpack
CY7C4251-35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4251- 35AI
A32
32-Lead Thin Quad Flatpack
CY7C4251-35JI
J65
32-Lead Plastic Leaded Chip Carrier
Document #: 38-00419
5-56
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
CY7C4425/4205/4215
CY7C4225/4235/4245
64, 256, 512, 1K, 2K, 4K x 18
Synchronous FIFOs
Features
• Output Enable (OE) pin
•
•
•
•
•
•
•
• 68-pin PLCC and 64-pin TQFP
•
•
•
•
•
64 x 18 (CY7C4425)
256 x 18 (CY7C4205)
512 x 18 ( CY7C4215)
lK x 18 (CY7C4225)
2K x 18 (CY7C4235)
4K x 18 (CY7C4245)
High-speed 100-MHz operation
(10 ns read/write cycle time)
Pin compatible and functional equivalent to IDT72425, 72205, 72215,
72225,72235,72245
Additional features
- Retransmit
- Synchronous Almost Empty/Full
flags
Fully asynchronous and simultaneous
read and write operation
Five status flags: Empty, Full, Half
Full, and programmable Almost
Empty/Almost Full
Low operating power
-IcC! = 100 rnA
Functional Description
The CY7C42X5 are high-speed, low-power, first-in first-out (FIFO) memories with
clocked read and write interfaces. All are
18 bits wide and are pin/functionally compatible to IDT722x5. The CY7C42X5 can
be cascaded to increase FIFO depth. Programmable features include Almost Full/
Almost Empty flags. These FIFOs provide
solutions for a wide variety of data bufferi~~ needs, i~cludinghigh-speed data acquiSItion, multiprocessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output
ports that are controlled by separate clock
and enable signals. The input port is controlled by a free-running ~k (WCLK)
and a write enable pin (WE .
When WEN is asserted, data is written
into the FIFO on the rising edge of the
WCLK signal. While WEN is held active,
data is continually written into the FIFO
on each cycle. The output port is cont~olled in a similar manner by a free-runmng read clock (RCLK) and a read enable
pin (REN). In addition, the CY7C42X5
have an output enable pin (OE). The read
and write clocks may be tied together for
single·dock operation or the two clocks may
be run independently for asynchronous
read/write applications. Clock frequencies
up to 100 MHz are achievable.
Retransmit and Synchronous Almost Full/
Almost Empty flag features are available
on these devices.
Depth expansion is~sible using the cascade input (WXI, RXI), cascade output
(WXO, RXO), and First Load (FL) pins.
The WXO and RXO pins are connected to
the WX1 and RXI pins of the next device,
and the WXQ and RXO pins of the last device should be connected to the WXI and
RXI pins of the first device. The FL..E!.n of
the first device is tied to V 55 and the FL pin
of all the remaining devices should be tied
to Vee.
Logic Block Diagram
DO-17
WCLK
wrn
••
RAM
ARRAY
64x 18
256 x 18
512x 18
1Kx 18
2Kx 18
4Kx 18
r---r=~~--~w
EF
PAE
PAl'
' - - - . . - -..... SIi!OllE
••
I
AS --IL_R_E_S_ET_...J
LOGIC
FDRT
WXi
WXO/FiF
100
_.-r-----.
EXPANSION
LOGIC
=
42X5·1
RCLK
5-57
REI'I
CY7C4425/4205/4215
CY7C4225/4235/4245
Pin Configurations
PLCC
Top View
987
014
65
43216867666564636261
10
vecfS1iIDllE
60
°13
11
012
011
010
D9
12
13
14
15
Vee
08
GND
[q
16
17
18
19
20
Vee
21
a7
22
Vee
23
a,
as
a"
a'3
GND
a10
a9
GND
a.
~ V~~W~~~M~~D~~~~G~
GND
a.
"
a"
GND
D'3
D'2
0
"
D'0
0,
D,
[q
D,
Os
0,
0,
02
0,
Do
a'2
a"
24
25
a"
D,S
D,.
a'2
a"
Vee
a'0
a9
GND
a,
a7
a,
as
GND
a,
Vee
&o~aa~
42><52
Functional Description (continued)
The CY7C42X5 provides five status pins. These pins are decoded to
detennine one of five states: Empty, Almost Empty, Half Full, Almost
Full, and Full (see Table 4). The Half Full flag shares the WXO pin.
'This flag is valid in the standalone and width-expansion configurations. In the depth expansion, this pin provides the expansion o~t
(WXO) information that is used to signal the next FIFO when It
will be activated.
The Empty and Full flags are synchronous, i.e., they cha~ge state
relative to either the read clock (RCLK) or the wnte clock
(WCLK). When entering or exiting the Empty ~tates, the flag!s updated exclusively by the RCLK. The flag denotmg Full states IS updated exclusively by WCLK. The synchronous flag architecture
guarantees that the flags will remain valid from one clock cycle to
the next. As mentioned previously, the Almost Empty/Almost Full
flags become synchronous if the VCdSMODE is tied to Vss. All
configurations are fabricated using an advanced 0.6511 N-Well
CMOS technology. Input ESD protection is greater than 2001Y,
and latch-up is prevented by the use of guard rings.
Selection Guide
Maximum Frequency (MHz)
7C42X5-10
7C42X5-15
7C42X5 25
7C42X5 35
100
66.7
40
28.6
Maximum Access Time (ns)
8
10
15
20
Minimum Cycle Time (ns)
10
15
25
35
7
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
I Commercial
Active Power Supply
Current (ICCI) (rnA)
Density
I Industrial
I
I
3
4
6
0.5
1
1
2
8
10
15
20
100
100
100
100
120
120
120
120
CY7C4425
CY7C4205
64x 18
256 x 18
I
I
CY7C4215
512x 18
5-58
I
J
CY7C4225
1Kx 18
I
I
CY7C4235
2Kx18
J
J
CY7C4245
4Kx18
CY7C4425/4205/4215
CY7C4225/4235/4245
~-~
a? CYPRESS
Pin Definitions
Signal Name
Description
Function
I/O
DO-17
Data Inputs
I
Data inputs for an 18-bit bus
00 -17
WEN
Data Outputs
Write Enable
0
I
Enables the WCLK input
Data outputs for an 18-bit bus
REN
Read Enable
I
Enables the RCLK input
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When
LD is asserted, WCLK writes data into the programmable flag-offset register.
RCLK
Read Clock
I
The risfug edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty.
When LD is asserted, RCLK reads data out of the programmable flag-offset register.
WXO/HF
Write Expansion
Out/Half Full
Flag
0
EF
Empty Flag
Full Flag
0
Dual-Mode Pin:
Single device or width expansion - Half Full status fla~
Cascaded - Write Expansion Out signal, connected to WXI of next device.
When EF is LOW; the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW; the FIFO is full. FF is synchronized to WCLK.
Programmable
Almost Empty
0
PAF
Programmable
Almost Full
0
LD
Load
I
FLIRT
First Load/
Retransmit
I
WXI
Write Expansion
Input
I
RXI
Read Expansion
Input
I
Cascaded - Connected to RXO of previous device.
Not Cascaded - Tied to Vss.
RXO
Read Expansion
Output
0
Cascaded - Connected to RXI of next device.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write operation
after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO's data outputs drive the bus to which they are connected. If OE
is HIGH, the FIFO's outputs are in High Z (high-impedance) state.
~
SMODE
Synchronous
Almost Empty/
Almost Full
Flags
I
Dual-Mode Pin
Asynchronous Almost Empty/Almost Full flags - tied to Vee.
Synchronous Almost Empty/Almost Full flags - tied to Vss.
(Almost Empty synchonized to RCLK, Almost Full synchronized to WCLK.)
FF
PAE
0
When PAE is LOW; the FIFO is almost empty based on the almost-empty offset value programmed into the FIFO. PAE is asynchronous when VedSMODE is tied to Vee; it is synchronized to RCLK when VedSMODE is tied to V ss.
When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed
into the FIFO. PAF is asynchronous when VedSMODE is tied to Vee; it is synchronized to
WCLK when VedSMODE is tied to V ss.
When LD is LOW, Do -17(00 -17) are written (read) into (from) theprogrammable-flag-offset register.
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to V ss; all other devices will
have FL tied to Vee. In standalone mode or width expansion, FLis tied to V ss on all devices.
Not Cascaded - Tied to Vss. Retransmit function is also available in standalone mode by
strobing RT.
Cascaded - Connected to WXO of previous device.
Not Cascaded - Tied to Vss.
Maximum Ratings
(Above which the usefullife may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to + 150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential ........ -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to +7.0V
DC Input Voltage ....................... - 3.0V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Ambient
Temperature
Commercial
O°Cto +70°C
Vee
5V ± 10%
IndustriaJ[1]
-40°C to +85°C
5V ± 10%
Note:
1.
5-59
TA is the "instant on" case temperature.
CY7C442S/420S/421S
CY7C422S/423S/424S
Electrical Characteristics Over the Operating Rangel2]
Parameter
Description
Test Conditions
7C42X5-10
7C42X5-15
7C42X5-25
7C42X5- 35
Min.
Min.
Min.
Min.
Max.
Max.
Max.
VOH
Output HIGH Voltage Vee = Min.,
IOH = -2.0 rnA
VOL
Output LOW Voltage
VJH[3]
Input HIGH Voltage
2.0
VIL[3]
Input LOW Voltage
-3.0
Vee
0.8
-3.0
Vee
0.8
-3.0
Vee
0.8
IJX
Input Leakage
Current
Vee = Max.
-10
+10
-10
+10
-10
+10
IOS[4]
Output Short
Circuit Current
Vee = Max.,
VOUT= GND
-90
IOZL
10ZH
Ieel[5]
Ou:t:ut OFF,
Hig Z Current
OE~VJH,
-10
Active Power Supply
Current
lee2[6]
leCfmaP]
2.4
2.4
2.4
0.4
Vee = Min.,
IOL= 8.0 rnA
VSS < Vo < Vee
Com'l
2.0
-90
+10
0.4
0.4
-10
2.0
-90
+10
-10
Max.
2.4
V
0.4
V
-3.0
Vee
0.8
V
-10
+10
!JA
2.0
-90
+10
Unit
-10
V
rnA
+10
!JA
100
100
100
100
rnA
Ind
120
120
120
120
rnA
Average Standby
Current
Com'l
30
28
25
25
rnA
Ind
40
38
35
35
rnA
Operating Current at
Maximum Frequency
Com'l
230
200
115
90
rnA
Ind
250
220
135
110
rnA
Capacitance[8]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
5
7
Unit
pF
pF
AC Test Loads and Waveforms[9, 10]
R11.1KQ
ALL INPUT PULSES
OUTP~~31
CL
I
INCLUDING _
JIG AND SCOPE
Equivalent to:
3.0V ---~9:':'O%:-:-----""oI.
GND
R2
680Q
_
42X54
42X5·5
THEVENIN EQUIVALENT
410Q
OUTPUT 000--_,111._ - - - 0 0 1.91V
Notes:
2. See the last page ofthis specification for Group A subgroup testing information.
3. The ~..!!.Y.ILspecifications apply for all inputs except WXI, RXI.
The WXI, RXI pin is not a TTL input. It is connected to either RXO,
WXO of the previous device or V ss.
4. Thst no more than one output at a time for not more than one second.
5. Thsted at frequency = 20 MHz with outputs open.
6. All input = V CC - 0.2Y, exce~CLKandWCLK, which are switching
at maximum frequency, and FLIRT = Vss.
Input signals switch from OV to 3V with a rise/faIl time of less than 3
ns, clocks and clock enables switch at maximum frequency (fMAX),
while data inputs switch at fMAXJ2. Outputs are unloaded.
8. Tested initially and after any design or process changes that may affect
these parameters.
9. CL = 30 pF for all AC parameters except for 10HZ.
10. CL = 5 pF for tOHZ'
7.
5-60
=-
CY7C4425/4205/4215
CY7C4225/4235/4245
-.~
-==-1 CYPRESS
-_.II'
Switching Characteristics Over the Operating Range
Parameter
Description
7C42X5-10
7C42XS-15
7C42XS-25
7C42XS-35
Min.
Min.
Min.
Min.
Max.
100
Max.
Max.
40
Unit
28.6
MHz
Clock Cycle Frequency
tA
Data Access Time
2
tCLK
Clock Cycle Time
10
15
tCLKH
Clock HIGH Time
4.5
6
10
14
ns
tCLKL
Clock LOW Time
4.5
6
10
14
ns
tDS
Data Set-Up Time
tDH
Data Hold Time
8
66.7
Max.
ts
2
10
2
15
25
2
20
35
ns
ns
3
4
6
7
ns
0.5
1
1
2
ns
ns
tENS
Enable Set-Up Time
3
4
6
7
tENH
Enable Hold Time
0.5
1
1
2
ns
tRS
Reset Pulse Width[ll]
10
15
25
35
ns
tRSR
Reset Recovery Time
8
tRSF
Reset to Flag and Output Time
tpRT
Retransmit Pulse Width
12
15
25
35
ns
12
15
25
35
ns
10
10
tRTR
Retransmit Recovery Time
tOLZ
Output Enable to Output in Low Z[!2]
0
tOE
Output Enable to Output Valid
3
7
3
tOHz
Output Enable to Output in High Z[!2]
3
7
3
tWFF
Write Clock to Full Flag
20
15
25
15
0
0
ns
35
0
8
3
12
3
8
3
12
3
ns
ns
15
ns
15
ns
8
10
15
20
ns
tREF
Read Clock to Empty Flag
8
10
15
20
ns
tPAFasynch
Clock to Programmable Almost-Full Flag[13]
(Asynchonous mode, VcdSMODE tied to Vce)
12
16
20
25
ns
tpAFsynch
Clock to Programmable Almost-Full Flag
(Synchonous mode, VcdSMODE tied to Vss)
8
10
15
20
ns
tPAEasynch
Clock to Programmable Almost-Empty Flag[13]
(Asynchonous mode, VcdSMODE tied to Vce)
12
16
20
25
ns
tpAEsynch
Clock to Programmable Almost-Full Flag
(Synchonous mode, V cdSMODE tied to VSS)
8
10
15
20
ns
tHF
Clock to Half-Full Flag
12
16
20
25
ns
6
10
15
20
ns
txo
Clock to Expansion Out
tXI
Expansion in Pulse Width
4.5
6.5
10
14
ns
tXIS
Expansion in Set-Up Time
4
5
10
15
ns
tSKEW!
Skew Time between Read Clock and Write Clock
for Full Flag
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write Clock
for Empty Flag
5
6
10
12
ns
tSKEW3
Skew Time between Read Clock and Write Clock
for Programmable Almost Empty and Programmable Almost Full Flags (Synchronous Mode
only).
10
15
18
20
ns
Notes:
11. Pulse widths less than minimum values are not allowed.
12. Values guaranteed by design, not currently tested.
13. tPAFasynch, tPAEa'ynch, after program register write will not be valid until 5 ns + tpAF(E).
5-61
CY7C4425/4205/4215
CY7C4225/4235/4245
~
..,.....:, CYPRESS
Switching Waveforms
Write Cycle Timing
RCLK
____-..J/
42X5-6
Read Cycle Timing
VALID DATA
1+---tOHZ
,,~--------------------------------
42X5-7
Notes:
14. tSKEW! is the minimum time hetween a rising RCLK edge and a rising
WCLK edge to guarantee that FF will go HIGH during the current
clock cycle. If the time between the risin~dge ofRCLK and the rising
edge ofWCLK is less than tSKEWh then FF may not change state until
the next WCLK rising edge.
15. tSKEW2 is the minimum time between a rising WCLK edge and a rising
RCLK edge to guarantee that EF will go HlGH during the current
clock cycle. It the time between the rising ed~of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state
until the next RCLK rising edge.
5-62
=-
CY7C4425/4205/4215
CY7C4225/4235/4245
-.."..
~,,~
a7CYPRESS
Switching Waveforms (continued)
Reset Timing[16j
--~ i - - - - - - t R S -------<-1 , , - - - - - - - - - - - - - - - - - -
14----- tRSR
---~
FF, PAF,
~~~~~====~~~~~
tRSF
rOE-1[17l
~
~
~ -----------------------------------------------~-----:----------t:iE=O
42X5-8
First Data Word Latency after Reset with Simnltaneons Read and Write
E
42X5-9
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOWifOE = 0 and three-state ifOE
=l.
18. When tSKEW2 ~ minimum specification, tpRL (maximum) = tCLK +
tSKEW2. When tSKEW2 < minimum specification, tpRL (maximum) =
either 2*tCLK + tSKEW2 or tCLK + !sKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
19. The first word is available the cycle after EF goes IDGH, always.
5-63
CY7C4425/4205/4215
CY7C4225/4235/4245
Switching Wavefonns (continued)
Empty Flag Timing
WCLK
_ _...J
RCLK
tA-:I~
'"
(WCLK). When entering or exiting the Empty~tates, the flag!s updated exclusively by the RCLK. The flag denotmg Full states IS updated exclusively by WCLK. The synchronous flag architecture
guarantees that the flags will remain valid from one clock cycle to
the next. As mentioned previously, the Almost Empty/Almost Full
flags become synchronous if the VcdSMODE is tied to V ss. All
configurations are fabricated using an advanced 0.65J.L N-Well
CMOS technology. Input ESD protection is greater than 200lV,
and latch-up is prevented by the use of guard rings.
Selection Guide
7C4255/65 -10
7C4255/65 -15
7C4255/65 25
7C4255/65-35
100
66.7
40
28.6
Maximum Access Time (ns)
8
10
15
20
Minimum Cycle Time (ns)
10
15
25
35
7
Maximum Frequency (MHz)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (ICCl) (rnA)
Density
I Commercial
I Industrial
I
I
CY7C4255
8Kx18
I
1
3
4
6
0.5
1
1
2
8
10
15
20
100
100
100
100
120
120
120
120
CY7C4265
16K x 18
I
I
5-78
....;;::=a..
CY7C4255
CY7C4265
PRELIMINARY
=:rcYPRESS
Pin Definitions
I/O
Fnnction
DO-17
QO-17
WEN
REN
WCLK
Signal Name
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
I
0
I
I
I
Data inputs for an 18-bit bus
Data outputs for an 18-bit bus
Enables the WCLK input
Enables the RCLK input
The ri~ edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
RCLK
Read Clock
I
The risi!!g edge clocks data out ofthe FIFO when REN is LOW and the FIFO is not Empty.
When LD is asserted, RCLK reads data out of the programmable flag-offset register.
WXO/HF
Write Expansion
Out/Half Full Flag
0
EF
FF
PAE
Empty Flag
Full Flag
Programmable
Almost Empty
0
PAP
Programmable
Almost Full
0
LD
Load
I
Dual-Mode Pin:
Single device or width expansion - Half Full status fla1LCascaded - Write Expansion Out signal, connected to WXI of next device.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value programmed into the FIFO. PAE is asynchronous when VedSMODE is tied to Vee; it is synchronized to RCLK when VedSMODE is tied to Vss.
When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF is asynchronous when VedSMODE is tied to Vee; it is synchronized to WCLK when VedSMODE is tied to Vss.
When LD is LOW, Do -17 (00 _ 17) are written (read) into (from) the programmable-flagoffset register.
FL/RT
First Load/
Retransmit
I
WXI
Write Expansion
Input
I
RXI
Read Expansion
Input
I
RXO
Read Expansion
Output
0
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write operation after power-up.
OE
Output Enable
I
~
Synchronous
Almost Empty/
Almost Full Flags
I
When OE is LOW, the FIFO's data outputs drive the bus to which they are connected. If OE
is HIGH, the FIFO's outputs are in High Z (high-impedance) state.
Dual-Mode Pin
Asynchronous Almost Empty/Almost Full flags - tied to Vee.
Synchronous Almost Empty/Almost Full flags - tied to Vss.
(Almost Empty synchonized to RCLK, Almost Full synchronized to WCLK.)
SMODE
Description
0
0
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to Vss; all other devices will
have FL tied to Vee. In standard mode of width expansion, FLis tied to V ss on all devices.
Not Cascaded - Tied to Vss. Retransmit function is also available in standalone mode by
strobing RT.
Cascaded - Connected to WXO of previous device.
Not Cascaded - Tied to Vss.
Cascaded - Connected to RXO of previous device.
Not Cascaded - Tied to Vss.
Cascaded - Connected to RXI of next device.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to + 150°C
Ambient Thmperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential ........ -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to + 7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ........................ >200lV
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperatnre
Range
Commercial
O°C to +70°C
Vee
5V ± 10%
Industrial[1]
-40°C to +85°C
5V ± 10%
Note:
1. TA is the "instant on" case temperature.
5-79
E
.£# .. ~
.~CYPRESS
CY7C4255
CY7C4265
PRELIMINARY
Electrical Characteristics Over the Operating Rangd2]
7C42X5-10
lest Conditions
Parameter
Description
Min.
VOH
Output HIGH Voltage Vee = Min.,
10H = -2.0 rnA
VOL
Output LOW Voltage
Max.
2.4
7C42X5-15
7C42X5-25
7C42X5- 35
Min.
Min.
Min.
Max.
2.4
Vee = Min.,
10L = 8.0 rnA
0.4
Max.
2.4
0.4
Max.
2.4
0.4
Unit
V
0.4
V
VIH[3]
Input HIGH Voltage
2.2
VIL[3]
Input LOW Voltage
-3.0
Vee
0.8
-3.0
Vee
0.8
-3.0
Vee
0.8
-3.0
Vee
0.8
V
IIX
Input Leakage
Current
Vee = Max.
-10
+10
-10
+10
-10
+10
-10
+10
!AA
IOS[4]
Output Short
Circuit Current
Vee = Max.,
VOUT = GND
-90
10ZL
IOZH
Outgut OFF,
Hig Z Current
OE~ VIH,
Vss < Va < Vee
-10
leeP]
Active Power Supply
Current
Com'l
100
100
Ind
120
120
Operating Current at
Maximum Frequency
Com'l
230
Ind
Average Standby
Current
IeefMAx. [6]
leeP]
2.2
-90
+10
-10
2.2
-90
+10
-10
2.2
-90
+10
-10
V
rnA
+10
J.lA
100
100
rnA
120
120
rnA
200
115
90
rnA
250
220
135
110
rnA
Com'l
30
28
25
25
rnA
Ind
40
38
35
35
rnA
Capacitance[8]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
lest Conditions
= 25°C, f = 1 MHz,
Vee = 5.0V
TA
Max.
Unit
5
7
pF
pF
AC Test Loads and Waveforms[9, 10]
R11.1KO
ALL INPUT PULSES
OUTP~~31
I
CL
INCLUDING _
JIG AND SCOPE
Equivalent to:
3.0V -----:~90:":'%:----........
GND
R2
6800
_
4255.4
4255·5
THEvENIN EQUIVALENT
4100
OUTPUT 00---"'''''''''_---00 1.91V
Notes:
2. See the last page of this specification for Group A subgroup testing infonnation.
3. The Yui..an..E.Y!L specifications apply for all inputs except WXI, RXI.
The WXI, RXI pin is not a TIL input. It is connected to either RXO,
WID of the previous device or V ss.
4. Thst no more than one output at a time for not more than one second.
5. Tested at freqeumcy = 20 MHz with outputs open.
6. Input signals switch from OV to 3V with a rise/fail time of less than 3
ns, clocks and clock enables switch at maximum frequency (fMAX),
while data inputs switch at fMAXf2. Outputs are unloaded.
AIIinputs = Vee - 0.2Y, except RCLKand WCLK (which are switching at frequency = 100 MHz). All outputs are unloaded.
8. Tested initially and after any design or process changes that may affect
these parameters.
9. CL = 30 pF for all AC parameters except for tOHZ'
10. CL = 5 pF for tOHZ.
7.
5-80
-
-~
CY7C4255
CY7C4265
PRELIMINARY
=-1 CYPRESS
Switching Characteristics Over the Operating Range
Parameter
ts
Description
7C42XS-IO 7C42X5-15
7C42X5-25
7C42X5-35
Min.
Min.
Min.
Clock Cycle Frequency
Max.
Min.
100
8
Max.
66.7
10
Max.
40
Max.
Unit
28.6
MHz
20
ns
tA
Data Access Time
2
tCLK
Clock Cycle Time
10
15
25
35
ns
tCLKH
Clock HIGH Time
4.5
6
10
14
ns
tCLKL
Clock LOW Time
4.5
6
10
14
ns
tDS
Data Set-Up Time
3
4
6
7
ns
tDH
Data Hold Time
0.5
1
1
2
ns
tENS
Enable Set-Up Time
3
4
6
7
ns
tENH
Enable Hold Time
0.5
1
1
2
ns
tRS
Reset Pulse Width[ll]
10
15
25
35
ns
tRSR
Reset Recovery Time
8
10
15
20
ns
2
15
15
2
tRSF
Reset to Flag and Output Time
tpRT
Retransmit Pulse Width
40
60
60
60
ns
tRTR
Retransmit Recovery Time
90
90
90
90
ns
tOLZ
Output Enable to Output in Low Z[l2]
0
0
0
0
tOE
Output Enable to Output Valid
3
7
3
8
3
12
3
15
ns
tOHZ
Output Enable to Output in High Z[l2]
3
7
3
8
3
12
3
15
ns
tWFF
Write Clock to Full Flag
8
10
15
20
ns
tREF
Read Clock to Empty Flag
8
10
15
20
ns
tpAFasynch
Oock to Programmable Almost-Full Flag[J3]
(Asynchonous mode, Vcx;!SMODE tied to Vce)
12
16
20
25
ns
tpAFsynch
Oock to Programmable Almost-Full Flag
(Synchonous mode, V cx;!SMODE tied to Vss)
8
10
15
20
ns
tPAEasynch
Clock to Programmable Almost-Empty Flag[13]
(Asynchonous mode, Vcx;!SMODE tied to Vce)
12
16
20
25
ns
tpAEsynch
Oock to Programmable Almost-Full Flag
(Synchonous mode, Vcx;!SMODE tied to Vss)
8
10
15
20
ns
tHF
Clock to Half-Full Flag
12
16
20
25
ns
txo
Clock to Expansion Out
7.5
10
15
20
ns
tXI
Expansion in Pulse Width
4.5
6.5
10
14
ns
tXIS
Expansion in Set-Up Time
2.5
5
10
15
ns
tSKEWl
Skew Time between Read Clock and Write Clock
for Full Flag
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write Oock
for Empty Flag
5
6
10
12
ns
tSKEW3
Skew Time between Read Clock and Write Clock
for Programmable Almost Empty and Programmable Almost Full Flags (Synchronous Mode
only)
10
15
18
20
ns
Notes:
11. Pulse widths less than minimum values are not allowed.
12. Values guaranteed by design, not currently tested.
10
2
25
35
ns
ns
13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tpAF(E).
5-81
E
CY7C4255
CY7C4265
PRELIMINARY
Switching Waveforms
Write Cycle Timing
RCLK
____----J/
4255-6
Read Cycle Timing
---<*,~- tClKl
RCLK
•
VALID DATA
tOlZ
tOHZ----I~
WCLK
,,~--------------------------------
4255-7
Notes:
14_ tSKEW! is the minimum time between a rising RCLK edge and a rising
WCLK edge to guarantee that FF will go HIGH during the current
clock cycle. If the time between the risin~ge of RCLKand the rising
edge ofWCLKis less than tSKEWh then FF may not change state until
the next WCLK rising edge.
15. tSKEW2 is the minimum time between a rising WCLK edge and a rising
RCLK edge to guarantee that 'ElF will go mGH during the current
clock cycle. It the time between the rising ed~ of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state
until the next RCLK rising edge_
5-82
CY7C4255
CY7C4265
~
$?
~YPRESS
Switching Waveforms
PRELIMINARY
(continued)
Reset Timing[16]
------~~~--------tRS----------~~~------------------------------------
1------ tRSR -------i
RrIi/, WEN,
ill
FF, PAF,
HF~~~~====~~======~
tRSF
r OE=1[17]
~
~
~ -----------------------------------------------~--~-~-----------lJE- 0
4255-8
First Data Word Latency after Reset with Simnltaneons Read and Write
E
~~".
00 - 017
f-_
D
_1_ -
4255-9
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = a and three-state if OE
=1.
18. When tSKEW2 ~ minimum specification, tFRL (maximum) = tCLK +
tSKEW2. WhentsKEw2 < minimum specification, tFRL(maximum) =
either Z*tCLK + tSKEWZ or tCLK + !sKEw2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
19. The first word is available the cycle after EF goes HIGH, always.
5-83
CY7C42SS
CY7C426S
PRELIMINARY
Switching Waveforms (continued)
Empty Flag Timing
WCLI<
DO - D17
RCLK
tA--:I . .
2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Supply Voltage to Ground Potential ........ -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to +7.0V
DC Input Voltage ....................... - 3.0V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Note:
1. TA is the "instant on" case temperature.
5-95
Ambient
Temperature
Vee
Commercial
O°Cto +70°C
5V ± 10%
Industrial[!]
-40°C to +85°C
5V ± 10%
Range
E
L~
PRELIMINARY
~;CYPRESS
CY7C4261
CY7C4271
Pin Definitions
Signal Name
Description
Description
I/O
Data Inputs for 9-bit bus
Data Inputs
I
Qo- s
Data Outputs
0
Data Outputs for 9-bit bus
WENl
Write Enable 1
I
The only write enable when device is configured to have programmable fla~ Data is written on a LOW-to-HIGH transition ofWCLK when WENl is asserted and FF is HIGH. If
the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when WENl is LOW and WEN2/LD and FF are HIGH.
WEN2/LD
Write Enable 2
Dual Mode Pin
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin operates as a control to write or read the programmable flag offsets. WENl must be LOW and
WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held
LOW to write or lead the programmable flag offsets.
Do-s
Load
RENl,REN2
Read Enable
Inputs
I
Enables the device for Read operation.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WENl is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out ofthe FIFO when RENl and REN2 are LOW and the FIFO
is not Empty. When WEN2/LD is LOW, RCLK reads data out ofthe programmable flagoffset register.
EF
Empty Flag
0
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Bag
0
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
0
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO.
PAP
Programmable
Almost Full
0
When PAP is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO.
RS
Reset
I
Resets device to empty condition. A reset is requ1:red before an initial read or write operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO's data outputs drive the bus to which they are connected. IfOE
is HIGH, the FIFO's outputs are in High Z (high-impedance) state.
5-96
=--- ---.."...
-.,~
CY7C4261
CY7C4271
PRELIMINARY
~'CYPRESS
Electrical Characteristics Over the Operating Rangd 2]
Parameter
Description
7C42Xl-1O
Min. Max.
Test Conditions
2.4
7C42Xl-25 7C42Xl- 35
Min. Max. Min. Max.
VOH
Output HIGH Voltage Vee = Min.,
IOH = -2.0 rnA
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
2.2
VrL
Input LOW Voltage
-3.0
Vee
0.8
-3.0
Vee
0.8
-3.0
Vee
0.8
Irx
Input Leakage
Current
Vee = Max.
-10
+10
-10
+10
-10
+10
IOS[3]
Output Short
Circuit Current
Vee = Max.,
VOUT= GND
-90
IOZL
IOZH
IeC1[4]
Output OFF,
High Z Current
OE~ VIH,
Vss < Vo < Vee
Com'l
-10
Active Power Supply
Current
2.4
7C42Xl-15
Min. Max.
0.4
Vee = Min.,
IOL = 8.0 rnA
2.4
0.4
2.2
-90
+10
-10
2.4
-90
+10
-10
V
0.4
V
-3.0
Vee
0.8
V
-10
+10
~
0.4
2.2
2.2
-90
+10
Unit
-10
V
rnA
+10
~
rnA
50
50
50
50
Ind
70
70
70
70
rnA
IeCfMAX[5]
Operating Current at
Maximum Frequency
Com'l
150
130
75
60
rnA
Ind
170
150
95
80
rnA
Ied 6]
Average Standby
Current
Com'l
30
28
25
22
rnA
Ind
40
38
35
35
rnA
Capacitance[7]
Parameter
CrN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
5
7
Unit
pF
pF
AC Test Loads and Waveforms[8, 9]
R11.1KQ
OUTP~~~
I
CL
INCLUDING _
JIG AND SCOPE
Equivalent to:
ALL INPUT PULSES
3.0V --~::J.t::'90::-:%:----""'>J..
GND
R2
680Q
_
4261-4
4261-5
THEVENIN EQUIVALENT
420Q
OUTPUT 0-0---'11
..'\1\,._ _--00 1.91V
Notes:
2. See the last page ofthis specification for Group A subgroup testing information.
3. Test no more than one output at a time for not more than one second.
4. Outputs open. lOsted at frequency = 20 MHz.
5. Input signals switch from OV to 3V with a rise/fall time of less than 3
ns, clocks and clock enables switch at maximum frequency (fMAX),
while data inputs switch at fMAXi2. Outputs are unloaded.
6_
7_
8.
9.
5-97
All inputs = Vee - 0.2v, except WCLK and RCLK (which are switching at frequency = 100 MHz). All outputs are unloaded.
Tested initially and after any design or process changes that may affect
these parameters_
CL = 30 pF for all AC parameters except for tOHZ.
CL = 5 pF for tOHZ'
I
~rcYPRESS
CY7C4261
CY7C4271
PRELIMINARY
Switching Characteristics Over the Operating Range
Description
Parameter
ts
7C42Xl-1O
7C42Xl-15
7C42Xl-25 7C42Xl-35
Min.
Min.
Min.
Max.
100
Clock Cycle Frequency
8
Max.
66.7
2
Min.
40
2
2
Unit
28.6
MHz
20
ns
Data Access Time
2
tCLK
Clock Cycle Time
10
15
25
35
ns
tCLKH
Clock HIGH Time
4.5
6
10
14
ns
tCLKL
Clock LOW Time
4.5
6
10
14
ns
tDS
Data Set-Up Time
3
4
6
7
ns
tDH
Data Hold Time
0.5
1
1
2
ns
tENS
Enable Set-Up Time
3
4
6
7
ns
tENH
Enable Hold Time
0.5
1
1
2
ns
tRS
Reset Pulse Width[10]
10
15
25
35
ns
tRSS
Reset Set-Up Time
8
10
15
20
ns
tRSR
Reset Recovery Time
8
10
15
20
tRSF
Reset to Flag and Output Time
tOLZ
Output Enable to Output in Low Z[ll]
0
tOE
Output Enable to Output Valid
3
7
3
8
3
12
3
15
ns
tOHZ
Output Enable to Output in High Z[ll]
3
7
3
8
3
12
3
15
ns
tWFF
Write Clock to Full Flag
8
10
15
20
ns
tREF
Read Clock to Empty Flag
8
10
15
20
ns
tpAF
Clock to Programmable Almost-Full Flag
8
10
15
20
ns
tpAE
Clock to Programmable Almost-Full Flag
8
10
15
20
ns
tSKEWl
Skew Time between Read Clock and Write Clock
for Empty Flag and Full Flag
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
10
15
18
20
ns
25
15
0
15
Max.
tA
10
10
Max.
0
0
Notes:
10. Pulse widths less than minimum values are not allowed.
11. Values guaranteed by design, not currently tested.
5-98
ns
35
ns
ns
=---~
==-:,~
PRELIMINARY
ffCYPRESS
CY7C4261
CY7C4271
Switching Waveforms
Write Cycle Timing
WCLK
WEN2
----------i:::::::~~::~
(if applicable)
FF
tSKEW1[ 12l
RCLK
/
Read Cycle Timing
14------- tCKL
-
tCLKH
4261·6
----------*1
---<*'>--
tCLKL
I
-
tREF -----1~ ~---------
VALID DATA
tOHZ
WEN2
~~---------------------------------------------__...J/
4261-7
Notes:
12. tSKEW! is the minimum time between a rising RCLK edge and a rising
WCLK edge to guarantee that FF will go HIGH during the current
clock cycle. If the time between the risin&-,-dge of RCLK and the rising
edge of WCLK is less than tSKEWh then FF may not change state until
the next WCLK rising edge.
13. tSKEW! is the minimum time between a rising WCLKedge and a rising
RCLK edge to guarantee that EF will go HIGH during the current
clock cycle. It the time between the rising ed~ofWCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state
until the next RCLK rising edge.
5-99
PRELIMINARY
CY7C4261
CY7C4271
Switching Wavefonns (continued)
Reset Timing[14]
---'-""I-------tRS
-------I~
...- __________________
i - - - - t R S S - - - -....I-----tRSR - - -.....~I
i - - - - t R S S - - - - - + 0 1 - - - - - tRSR
----1
i - - - - t R S S - - - -....I-----tRSR
----I
WEN2J[D[16]
O E=I[15]
_______________________ _ _1r_ ________
_
Qo-Os
Notes:
14. The clocks (RCLK, WCLK) can be free-running during reset.
15. After reset, the outputs will be LOW if OE = 0 and three-state if
OE= 1.
16. Holding WENZ/LD HIGH durinlW'set will make the pin act as a second enable pin. Holding WENZ/LD LOW during reset will make the
pin act as a load enable for the programmable flag offset registers.
5-100
~
-----
,-~
PRELIMINARY
~7CYPRESS
CY7C4261
CY7C4271
Switching Waveforms (continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
Do·DS
WEN2
(if applicable)
RCLK
Oo'Os
Do
I
toLZ
________________________
~~~-------tOE----------~
4261·9
Notes:
17. When tSKEW! ~ minimum specification, tFRL (maximum) = tCLK +
tSKEwz. When tSKEWZ < minimnm specification, tFRL (maximum) =
either Z*tCLK + tSKEW! or tCLK + !sKEW!. The Latency Timing ap·
plies only at the Empty Boundary (EF = LOW).
18. The first word is available the cycle after EF goes HIGH, always.
5-101
PRELIMINARY
CY7C4261
CY7C4271
Switching Waveforms (continued)
Empty Flag Timing
WCLK
---
Do· DB
WEN2
(if applicable)
RCLK
LOW
DATA IN OUTPUT REGISTER
tA-:I,~
_
_
?I'--DATA READ
4261-10
5-102
PRELIMINARY
CY7C4261
CY7C4271
Switching Waveforms (continued)
FuJI Flag Timing
NO WRITE
NO WRITE
WCLK _ _...J
Do - D8
WEN2
(if applicable)
RCLK
I
00- 0 8 _______________-J
4261-11
5-103
~
PRELIMINARY
=- rcYPRESS
CY7C4261
CY7C4271
Switching Waveforms (continued)
Programmable Almost Empty Flag Timing
tCLKH
WCLK
WEN2
(ilappliCable) _ _ _ _ _- "............Jf_-t-_-I ....~~----------------------N
+1
WORDS
IN FIFO
RCLK
4261·12
Programmable Almost Fnll Flag Timing
tCLKH
WCLK
WEN2
(if applicable)
---_..............
"-'
_
tR_~~,_FULL
__
_ _ _ __+--~
- M WORDS
_______________
FULL - (M + 1) WORDS
IN FIFO
IN FIFO[24]
RCLK
. Rmf,
REN2
4261·13
Notes:
19. tSKEW2 is the minimum time between a rising WCLK and a rising
RCLK edge for PAE to change state during that clock cycle. If the time
between the edge of WCLK and the rising RCLK is less than tSKEW2,
then PAE may not change state until the next RCLK.
20. PAE offset - n.
21. If a read is preformed on this !ising edge of the read clock, there will
be Empty + (n-1) words in the FIFO when PAE goes LOW.
22. If a write is performed on this rising edge of the write clock, there will
be Full - (m -1) words of the FIFO when PAF goes LOW.
23. PAF offset = m.
24. 16,384 - m words for CY7C4261, 32,768 - m words for CY4271.
25. tSKEW2 is the minimum time between a rising RCLK edge and a rising
WCLK edge for PAF to change during that clock cycle. If the time between the rising ed~f RCLK and the rising edge of WCLK is less
than tSKEW2, then PAF may not change state until the next WCLK.
5-104
~-...........
CY7C4261
CY7C4271
PRELIMINARY
)'CYPRESS
Switching Waveforms (continued)
Write Programmable Registers
WCLK
WEN2/LD
Do - D8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
4261-14
Read Programmable Registers
tCLKH
RCLK
I
WEN2/LD
PAE OFFSET LSB
PAE OFFSET MSB
4261-15
Architecture
The CY7C426l/7l consists of an array of 64 to 8K words of 9 bits
each (implemented by a dual-port array of SRAM cells), a read
pointer, a write pointer, control signals .lB:CLK, WCLK, RENl,
REN2, WENl, WEN2, RS), and flags (EF, PAE, PAF, FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by EF
being LOW. All data outputs (Qo ~ 8) go LOW tRSF after the rising
edge ofRS. In order forthe FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write
while RS is LOW. All flags are guaranteed to be valid tRSF after RS
is taken LOW.
FIFO Operation
When the WENl signal is active LOW and WEN2 is active
HIGH, data present on the Do ~ 8 pins is written into the FIFO on
each rising edge of the WCLK signal. Similarly, when the RENl
and REN2 signals are active LOW, data in the FIFO memory will
be presented on the Qo ~ 8 outputs. New data will be presented
on each rising edge of RCLK while RENl and REN2 are active.
RENl and REN2 must set up tENS before RCLK for it to be a
valid read function. WENl and WEN2 must occur tENS before
WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Qo ~ 8
outputs when OE is asserted. When OE is enabled (LOW), data in
the output register will be available to the Qo ~ 8 outputs after tOE.
If devices are cascaded, the OE function will only output data on
the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the
data of the last valid read on its Qo ~ 8 outputs even after additional
reads occur.
Write Enable 1 (WENl) - If the FIFO is configured for programmable flags, Write Enable 1 (WENl) is the only write enable control pin. In this configuration, when Write Enable 1 (WEN1) is
LOW, data can be loaded into the input register and RAM array on
the LOW-to-HIGH transition of every write clock (WCLK). Data
5-105
CY7C4261
CY7C4271
PRELIMINARY
is stored is the RAM array sequentially and independently of any
on-going read operation.
Write Enable 2/Load (WEN2/LD) - This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags or to
have two write enables, which allows for depth expansion. If Write
Enable 2/Load (WEN2/LD) is set active HIGH at Reset
(RS=LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every write clock (WCLK).
Data is stored in the RAM array sequentially and independently of
anyon-going read operation.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers contained in the CY7C42Xl for writing or reading data to these registers.
When the device is configured for programmable flags and both
WEN2/LD and WENI are LOW, the first LOW-to-HIGH transition ofWCLK writes data from the data inputs to the empty offset
least significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions ofWCLK store data in the empty offset most significant bit (MSB) register, full offset LSB register, and
full offset MSB register, respectively, when WEN2/LD and WENI
are LOW. The fifth LOW-to-HIGH transition of WCLK while
WEN2/LD and WENI are LOW writes data to the empty LSB register again. Figure 1 shows the registers sizes and default values for
the various device types.
16Kx9
32Kx9
0
7
Empty Offset (LSB) Reg.
Default Value = 007h
8
IXXX]
Empty Offset (LSB) Reg.
Default Value = 007h
0
5
(MSB)
000000
8
IXXX]
(MSB)
000000
0
Full Offset (LSB) Reg
Default Value = 007h
0
5
I
(MSB)
0000000
7
Full Offset (LSB) Reg
Default Value = Q07h
8
0
6
I IXXX]
0
7
0
7
8
I IXXX]
0
6
(MSB)
0000000
It is not necessary to write to all the offset registers at one time. A
subset of the offset registers can be written; then by bringing the
WEN2/LD input HIGH, the FIFO is returned to normal read and
write operation. The next time WEN2/LD is brought LOW, a write
operation stores data in the next offset register in sequence.
The contents ofthe offset registers can be read to the data outputs
when WEN2/LD is LOW and both RENI and REN2 are LOW.
LOW-to-HIGH transitions of RCLK read register contents to the
data outputs. Writes and reads should not be preformed simultaneously on the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as described in
Table 1 or the default values are used, the programmable almostempty flag (PAE) and programmable almost-full flag (PAP) states
are determined by their corresponding offset registers and the difference between the read and write pointers.
Table 1. Writing the Offset Registers
LD WEN
WCLK[26j
Selection
0
0
~
Empty Offset ~LSB)
Empty Offset MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
No Operation
1
0
1
1
~
~
~
]
Write Into FIFO
No Operation
The number formed by the empty offset least significant bit register and empty offset most significant registeris referred to asn and
determines the operation of PAE. PAE is synchronized to the
LOW-to-HIGH transition of RCLK by one flip-flop and is LOW
when the FIFO contains n or fewer unread words. PAE is set
HIGH by the LOW-to-HIGH transition of RCLK when the FIFO
contains (n+ 1) or greater unread words.
The number formed by the full offset least significant bit register
and full offset most significant bit re~ is referred to as m and
determines the operation of PAP. PAE is synchronized to the
LOW-to-HIGH transition of WCLK by one flip-flop and is set
LOW when the number of unread words in the FIFO is greater
than or equal to CY7C4261 (16K -m) and CY7C4271 (32K-m).
PAP is set HIGH by the LOW-to-HIGH transition ofWCLKwhen
the number of available memory locations is greater than m.
I
4261-16
Figure 1. Offset Register Location and Default Values
Note:
26. The same selection sequence applies to reading from the registers.
RENl and REN2 are enabled and a read is performed on the WWto-HIGH transition of RCLK.
5-106
=:.: rcYPRESS
CY7C4261
CY7C4271
PRELIMINARY
Table 2. Status Flags
Number of Words in FIFO
FF
PAF
PAE
0
CY7C4261
0
CY7C4271
H
H
L
EF
L
1 to n[27]
1 to n[27]
H
H
L
H
(n+1) to 8192
(n+l) to 16384
H
H
H
H
8193 to (16384 - (m+ 1»
(16384 - m)[28] to 16383
16385 to (32768 - (m+l»
(32768 - m)[28] to 32767
H
H
H
H
H
L
H
H
16384
32768
L
L
H
H
Width Expansion Configuration
Flag Operation
Word width may be increased simply by connecting the corresponding input controls signals of multiple devices. A composite
flag should be created for each of the end-~t status flags (EF
and FF). The partial status flags (PAE and PAF) can be detected
from anyone device. Figure 2 demonstrates a 18-bit word width by
using two CY7C42Xls. Any word width can be attained by adding
additional CY7C42Xls.
When the CY7C42Xl is in a Width Expansion Configuration, the
Read Enable (REN2) control input can be grounded (See Fi8!:!:!:.e
2). In this configuration, the Write Enable 2/Load (WEN2/LD)
pin is set to LOW at Reset so that the pin operates as a control to
load and read the programmable flag offsets.
The CY7C4261171 devices provide five flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
RESET
DATA IN (D)
18
FULL FLAG
READ CLOCK (RCLK)
--
(FF) # 1
FF
...........
(FF) # 2
_--_ ......EF f------.J
f-g+-
r-
t t J
-:!:-
0-
-----------
EMPTY FLAG (EF) #2
EF
"FJ!'
9
f 1 J
-:!:-
Read Enable 2 (REf\J2)
Read Enable 2
(REN2)
Figure 2. Block Diagram of 16K x 18/32K x 18 Synchronous FIFO
Memory Used in a Width Expansion Configuration
Noles:
27. n = Empty Offset (n=7 default value).
28. m = Full Offset (m=7 default value).
5-107
(DE)
PROGRAMMABLE (J5AE)
EMPTY FLAG (N) #1
CY7C4261/71
CY7C4261/71
(REN1)
OUTPUT ENABLE
.... --------
-----------
(PAF')
READ ENABLE 1
------------
---------_ ..
WRITE ENABLE 2/LOAD
(WEN2f[!))
--0
•
9
I
(AS)
-----------
WRITE ENABLE 1 (WEm)
FULL FLAG
RESET
------------
WRITE CLOCK (WCLK)
PROGRAMMABLE
The Empty Flag (EF) will go LOWwhen the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of RENI and REN2. EF is synchronized to RCLK, i.e., it is
exclusively updated by each rising edge of RCLK.
(AS)
•
9
The Full Flag (FF) will go LOW when device is full. Write operations are inhibited whenever FF is LOW regardless ofthe state of
WENI and WEN2/LD. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK.
Empty Flag
DATA OUT (Q)
18
==--- -,,~
PRELIMINARY
~;CYPRESS
Ordering Infonnation
Speed
(ns)
10
15
25
35
Speed
(ns)
10
15
25
35
Ordering Code
Package
Name
Package
1YPe
CY7C4261-lOAC
A32
32-Lead Thin Quad Flatpack
CY7C4261-lOJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-10AI
A32
32-Lead Thin Quad Flatpack
CY7C4261-lOJI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4261-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-15AI
A32
32-Lead Thin Quad Flatpack
CY7C4261-15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-25AC
A32
32-Lead Thin Quad Flatpack
CY7C4261-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-25AI
A32
32-Lead Thin Quad Flatpack
CY7C4261- 25JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-35AC
A32
32-Lead Thin Quad Flatpack
CY7C4261- 35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-35AI
A32
32-Lead Thin Quad Flatpack
CY7C4261-35JI
J65
32-Lead Plastic Leaded Chip Carrier
Package
Name
Package
1YPe
Ordering Code
CY7C4271-lOAC
A32
32-Lead Thin Quad Flatpack
CY7C4271-1OJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271-lOAI
A32
32-Lead Thin Quad Flatpack
CY7C4271-lOJI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4271-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271-15AI
A32
32-Lead Thin Quad Flatpack
CY7C4271-15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271- 25AC
A32
32-Lead Thin Quad Flatpack
CY7C4271-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271-25AI
A32
32-Lead Thin Quad Flatpack
CY7C4271- 25JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271- 35AC
A32
32-Lead Thin Quad Flatpack
CY7C4271- 35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271- 35AI
A32
32-Lead Thin Quad Flatpack
CY7C4271- 35JI
J65
32-Lead Plastic Leaded Chip Carrier
Document #: 38-00467
5-108
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
CY7C4261
CY7C4271
CY7C439
Bidirectional 2K x 9 FIFO
Features
Functional Description
• 2048 x 9 FIFO butTer memory
• Bidirectional operation
• High-speed 28.5-MHz asynchronous
reads and writes
• Simple control interface
• Registered and transparent bypass
modes
• Flags indicate Empty, Full, and Half
Full conditions
The CY7C439 is a 2048 x 9 FIFO memory
capable of bidirectional operation. As the
term first-in first-out (FIFO) implies, data
becomes available to the output port in the
same order that it was presented to the input port. There are two pins that indicate
the amount of data contained within the
FIFO block-ElF (Empty/Full) and HF
(Half Full). These pins can be decoded to
determine one of four states. Two 9-bit
data ports are provided. The direction selected for the FIFO determines the input
and output ports. The FIFO direction can
be programmed by the user at any time
through the use of the reset pin (MR) and
the bypass/direction pin (BYPA). There
are no control or status registers on the
CY7C439, making the part simple to use
• 5V ± 10% supply
• Available in 300-mil DIP, PLCC, LCC,
and SOJ packages
• TTL compatible
while meeting the needs of the majority of
bidirectional FIFO applications.
FIFO read and write operations may occur
simultaneously, and each can occur at up to
28.5 MHz. The port designated as the write
port drives its strobe pin (STBX, X = A or
B) LOW to initiate the write operation.
The port designated as the read port drives
its strobe pin LOW to initiate the read operation. Output port pins go to a high-impedance state when the associated strobe
pin is HIGH. All normal FIFO operations
require the bypass control pin (BYPX, X =
A or B) to remain HIGH.
In addition to the FIFO, two other data
paths are provided; registered bypass and
transparent bypass. Registered bypass can
be considered as a single-word FIFO in the
reverse direction to the main FIFO. The
Logic Block Diagram
Pin Configurations
PLCC/LCC
Top View
STBI!
lM'I!
A2
A,
Ao
B'i'PA
GND
BYPB
IlllA
Be
-~-.-t
NC
PORT
Ao
-AsA . . .
B,
TRANSPARENT
BYPASS
Ao A.,NCAa As A7
4 3 2 ~ 1J 32 31 30
29
28
6
27
7
26
8
25
7C439
9
24
10
23
11
22
12
21
13
14151617181920
As
E!I'
I
NC
STIlA
Vee
MR
STIlB
AI'
B8
82 8 3 8 4 NC 8 5 Be 8 7
C439-2
DIP
'Ibp View
EiF
FLAG
AI'
CONTROL
!IDA
A.,
Aa
Ao
As
A2
A,
A,
As
Elf
Ao
Il'II'A
GND
lM'I!
STIlA
Vee
MR
STBI!
!IDA
2048 x 9
FIFO
C439-1
Be
AI'
B,
B2
B8
S,
B,
B,
B6
B,
C439-3
Selection Guide
7C439-25
7C439-30
7C439-40
28.5
25
20
25
30
140
40
65
130
115
170
160
145
Frequency (MHz)
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
I Commercial
I Military
147
5-109
7C439-65
12.5
CY7C439
Functional Description (continued)
bypass register provides a means of sending a 9-bit status or control
word to the FIFO-write port. The bypass data available pin (BDA)
indicates whether the bypass registeris full or empty. The direction
of the bypass register is always opposite to that of the main FIFO.
The port designated to write to the bypass register drives its bypass
control pin (BYPX) LOW. The other port detects the presence of
data by monitoring BDA and reads the data by driving its bypass
control pin (BYPX) LOW. Register~ass operations require
that the associated FIFO strobe pin (STBX) remains HIGH. Registered bypass operations do not affect data residing in the FIFO,
or FIFO operations at the other port.
ltansparent bypass provides a means of transferring a single word
(9 bits) of data immediately in either direction. This feature allows
the device to act as a simple 9-bit bidirectional buffer. This is useful
for allowing the controlling circuitry to access a dumb peripheral
for control/programming information.
For transparent bypass, the port wishing to send immediate data to
the other side drives both its bypass and its strobe pins LOW simultaneously. This causes the buffered data to be driven out of the other port. On-chip circuitry detects conflicting use ofthe control pins
and causes both data ports to enter a high-impedance state until
the conflict is resolved.
Additionally, a Thst mode is offered on the CY7C439. This mode
allows the user to load data into the FIFO and then read it back
out ofthe same port. Built-In SelfThst (BIST) and diagnostic functions can take advantage of these features.
The CY7C439 is fabricated using an advanced 0.81-1 N-well CMOS
technology. Input ESD protection is greater than 2OO0V and latchup is prevented by reliable layout techniques, guard rings, and a
substrate bias generator.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature .................. -65°C to + 150°C
Ambient Thmperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential ........ -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5V to + 7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. l.OW
Output Current into Outputs (LOW) .............. 20 mA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
I/O
Description
A(S-O)
I/O
Data Port Associated with BYPA and STBA
B(S-O)
I/O
Data Port Associated with BYPB and STBB
BYPA
I
Registered Bypass Mode Select for A Side
BYPB
I
Registered Bypass Mode Select for B Side
BDA
0
Bypass Data Available Flag
STBA
I
Data Strobe for A Side
STBB
I
Data Strobe for B Side
ElF
0
Encoded EmptyIFull Flag
HF
0
Half Full Flag
MR
I
Master Reset
Ambient
Temperature
Commercial
O°C to +70°C
Vee
5V± 10%
-55°C to + 125°C
5V ± 10%
Military[lj
Note:
1. TA is the "instant on" case temperature.
Pin Definitions
Signal
Name
Range
5-110
==
~
---.....
-.,~
CY7C439
'CYPRESS
Electrical Characteristics Over the Operating Rangd 2]
Parameter
VOH
Description
Output HIGH
Voltage
VOL
Output LOW
Voltage
VIH
Input HIGH
Voltage
VIL
Input LOW
Voltage
Ilx
Input Leakage
Current
Ioz
Output Leakage
Current
Icc
Operating Current
ISB!
Standby Current
ISB2
Power-Down
Current
los
Output Short
Circuit Current[5]
7C439-25
Min. Max.
2.4
Test Conditions
Vee = Min.,
IOH = -2.0 rnA
7C439-30
Min. Max.
2.4
0.4
Vee = Min., IOL = 8.0 rnA
Corn'l
Mil
7C439-40
Min. Max.
2.4
0.4
7C439-65
Min. Max.
2.4
0.4
Unit
V
0.4
V
0.8
2.2
2.2
-3.0
Vee
Vee
0.8
2.2
2.2
-3.0
Vee
Vee
0.8
2.2
2.2
-3.0
Vee
Vee
0.8
V
V
V
-10
+10
-10
+10
-10
+10
-10
+10
iJA
-10
+10
-10
+10
-10
+10
-10
+10
iJA
115
145
40
45
20
25
-90
rnA
2.2
Vee
-3.0
GND.$. VI.$...Vee
STBXz VIH,
GND.$. Vo.$. Vee
Corn'I[3]
Vee = Max.,
lOUT = ornA
Mil[4]
147
All Inputs =
VIHMin.
Corn'l
Mil
All Inputs
Corn'l
Vee - 0.2V
Mil
Vee = Max., VOUT = GND
140
170
40
45
20
25
-90
40
20
-90
130
160
40
45
20
25
-90
rnA
rnA
rnA
Capacitance[6]
Parameter
Test Conditions
Description
Input Capacitance
Output Capacitance
CIN
COUT
Notes:
2.
3.
See the last page ofthis specification for Group A subgroup testing information.
Icc(commercial} = 115 rnA + [(f - !2.5)· 2 mA/MHz] for
fz 12.5 MHz
where f = the larger of the write or read
operating frequency.
4.
5.
6.
Unit
pF
Max.
8
10
TA = 25°C, f = 1 MHz,
Vee = 4.5V
pF
Icc (military) = 145 rnA + [(f - 12.5)·2 mNMHz] for
fz 12.5 MHz
where f = the larger of the write or read
operating frequency.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveform
R1500Q
R1500Q
30 pF
R2
I _
333Q
INCLUDING
JIG AND SCOPE
5 PF
,.OV
R2
333Q
INCLUDING _
JIG AND SCOPE
(a)
Equivalent to:
I
=1i
ALL INPUT PULSES
OUTP~~31
OUTPUT
5V31
_
C439-4
(b)
THEVENIN EQUIVALENT
200Q
OUTPUTGo----~.~.__--~o2V
5-111
GND
~5ns--
90%
10%
i.-
~
10%
__
~5ns
C439-5
E
*-.~
CY7C439
~;CYPRESS
Switching Characteristics Over the Operating Rangd2,7J
7C439-25
Parameter
Description
Min,
Max.
35
7C439-30
Min.
Max.
40
7C439-40
Min.
Max.
Max.
Unit
65
ns
tRC
Read Cycle Time
tA
Access Time
tRR
Read Recovery Time
10
10
10
15
ns
ns
25
50
7C439-65
Min.
30
80
40
ns
tpR
Read Pulse Width
25
30
40
65
tLZR[8,9J
Read LOW to Low Z
3
3
3
3
ns
tDVR[8,9J
Data Valid from Read HIGH
3
3
3
3
ns
tHZR[8,9J
Read HIGH to High Z
twc
Write Cycle Time
35
40
50
80
ns
tpw
Write Pulse Width
25
30
40
65
ns
tHWZ[8,9J
Write HIGH to Low Z
10
10
10
10
ns
tWR
Write Recovery Time
10
10
10
15
ns
tSD
Data Set-Up Time
15
18
20
30
ns
tHD
Data Hold Time
0
0
0
10
ns
tMRSC
MR Cycle Time
35
40
50
80
ns
tpMR
MR Pulse Width
25
30
40
65
ns
18
20
25
30
ns
tRMR
MR Recovery Time
10
10
10
15
ns
tRPS
STBX HIGH to MR HIGH
25
30
40
65
ns
tRPBS
BYPA to MR HIGH
10
10
15
20
ns
tRPBH
BYPA Hold after MR HIGH
0
0
0
0
tBDH
MR LOW to BDA HIGH
tBSR
STBX HIGH to BYPA LOW
tEFL
tHFH
tBRS
BYPX HIGH to STBX LOW
tREF
STBX LOW to ElF LOW (Read)
25
30
35
60
ns
tRFF
STBX HIGH to ElF HIGH (Read)
25
30
35
60
ns
tWEF
STBX HIGH to ElF HIGH (Write)
25
30
35
60
ns
tWFF
STBX LOW to ElF LOW (Write)
25
30
35
60
ns
tBDA
BYPX HIGH to BDA LOW (Write)
25
30
35
60
ns
tBDB
BYPX HIGH to BDA HIGH (Read)
25
30
35
60
ns
tBA
BYPX LOW to Data Valid (Read)
30
30
40
60
ns
tBHZ[8,9J
BYPX HIGH to High Z (Read)
18
20
25
30
ns
tTSB
STBX HIGH to BYPX LOW Set-Up
tTBS
STBX LOW after BYPX LOW
0
tTSN
STBX HIGH Recovery Time
10
tTSD[8,9J
STBX HIGH to Data High Z
tTBN
BYPX HIGH Recovery Time
tTBD
BYPX HIGH to Data High Z
35
40
10
10
50
10
ns
80
15
ns
ns
MRto ElF LOW
35
40
50
80
ns
MRtoHFHIGH
35
40
50
80
ns
10
10
10
10
0
10
10
18
0
20
10
0
ns
10
ns
30
ns
15
25
10
20
ns
15
10
10
10
15
10
10
18
5-112
10
ns
15
25
ns
30
ns
~
'CYPRESS
CY7C439
Switching Characteristics Over the Operating Rangel2,7] (continued)
7C439-25
Parameter
Description
Min.
Max.
7C439-30
Min.
Max.
7C439-40
Min.
Max.
7C439-65
Min.
Max.
Unit
tTPO[8,9]
STBX LOW to Data Valid
20
20
30
55
ns
tOL
tESO[8,9]
Transparent Propagation Delay
20
20
25
30
ns
STBX LOW to High Z
18
20
25
30
ns
tEBO[8,9]
BYPX LOW to High Z
18
20
25
30
ns
18
20
25
30
ns
30
ns
tEoS
STBX HIGH to Low Z
tEOB
BYPX HIGH to Low Z
tBPW
BYPX Pulse Width (nans,)
25
30
40
65
ns
tTSP
tBLZ[8,9]
STBX Pulse Width (nans.)
20
20
30
55
ns
BYPX LOW to Low Z (Read)
10
10
10
10
ns
tBOV
BYPX HIGH to Data Invalid (Read)
3
3
3
3
ns
tWHF
STBX LOW to HF LOW (Write)
35
tRHF
STBX HIGH to HF HIGH (Read)
tRAE
Effective Read from Write HIGH
tRPE
Effective Read Pulse Width after ElF
HIGH
tWAF
Effective Write from Read HIGH
tWPF
Effective Write Pulse Width after ElF
HIGH
25
30
40
65
ns
tBSU
Bypass Data Set-Up Time
15
18
20
30
ns
tBHL
Bypass Data Hold Time
0
0
10
ns
40
50
80
ns
35
40
50
80
ns
25
30
35
60
25
30
Notes:
7. Test conditions assume signal transition time of 5 ns oriess, timing reference levels of 1.5Y, and output loading ofthe specified IOJ)IOH and
30·pF load capacitance as in part (al of AC lest Loads, unless otherwise specified.
8. tDVR. tBm, tHZR. tTBD. tBHZ. tEBD. tESD. tTSD. tLZR. tHWZ. and tBLZ
use capacitance loading as in part (bl of AC Test Loads.
9.
40
30
25
0
25
20
18
65
35
ns
ns
60
ns
tHZR. tTBD, tBHZ. tEBD. tESD, and tTSD transition is measured at +500
m V from VOL and - 500 m V from VOH. tDVR and tBDV transition is
measured at the 1.5V level. tLZR. tHWZ. and tBLZ transition is measured at ± 100 m V from the steady state.
Switching Waveforms
Asynchronous Read and Write Timing Diagram
STBB[10]
READ
PORT B
-------1(
~---------------twc --------------~~
WRITE
mw''''
PORT A
i
~~X,o~
--------1<1<-
DATA VALID
___----J/
..)j.--------«,,___D_A_TA_V_A_Ll_D_-J~
5-113
CY7C439
Switching Waveforms (continued)
Master Reset Timing Diagram
C439-7
Half-Full Flag Timing Diagram[ll j
HALF FULL + 1
HALF FUll
HALF FUll
"
. . tRHF'"
/
.. tWHF ....
RF
~I'I..
/
r-009-8
LastWriteto First Read Empty/Full Flag Timing Diagram[llj
LAST WRITE
FIRST READ
ADDITIONAL READS
FIRST WRITE
/1{
- ~~
~
~~
~
/tt:
C439-9
Notes:
10. Direction selected Port A to Port B.
11. Direction selected as A to B.
5-114
===,
-,~
CY7C439
CYPRESS
Switching Waveforms (continued)
Last Read to First Write Empty/Full Flag Timing Diagram[ll]
LAST READ
FIRST WRITE
ADDITIONAL WRITES
FIRST READ
DATA OUT
C439-10
Empty/Full Flag and Read Bubble-Through Mode Timing Diagram[ll]
DATA IN
(PORTA)
Ii
EMPTY
DATA OUT
(PORT B)
DATA VALID
C439-11
Empty/Full Flag and Write Bubble-Through Mode Timing Diagram[ll]
FULL
DATA IN
(PORTA)
DATA VALID
DATA OUT
(PORT B)
C439-12
5-115
CY7C439
Switching Waveforms (continued)
Registered Bypass Read Timing Diagram[12j
14---- tesR ----1101+--
PORTB
0439-13
Registered Bypass Write Timing Diagram[13j
tesu
t-------
I.
lepw
- - - - - - 0..+1·... -
C439-14
'Iransparent Bypass Read Timing Diagram[14j
lesR
tTSP
W
ITse
'i
~
~I'\.
/'
ITSN
tTBS
t--
leRS
~
~
lepw
.....
PORTA
r-
VALID INPUT 1
/1+-- ITeN
--too
j4 tTeD ....
tTPD
~
-ITSD--
elK
"-
VALID INPUT 2
/
~tDLPORTB
/
I'
VALID OUTPUT 1
elK
VALID OUTPUT 2
"'
/
C439 -15
Notes:
12. Port B selected to read bypass register (BFO direction Port B to
PortA).
13. Port A selected to write bypass register (FIFO direction Port B to
Port A.
1,4. Diagram shows transparent bypass initiated by PortA. Times are iden-
5-116
tical if initiated by Port B.
CY7C439
Switching Waveforms (continued)
Test Mode Timing Diagram
C439-16
Exception Condition Timing Diagram[14]
~
________________________________
~;I
------------------------~;I
(
K.
I-
It'
K-
I-
"" tEBO ...
DATAB
VALID OUTPUT
E
~ tEDS ..
tESO ..
tEOB ..
HIGHZ
V
I'
VALID OUTPUT
C439-17
Architecture
The CY7C439 consists of a 2048 by 9-bit dual-ported RAM array,
a read pointer, a write pointer, data switching circuitry, buffers, a
bypass register, control signals (STBA, STBB, BYPA, BYPB, MR),
and flags (ElF, HF, BDA).
Operation at Power-On
~
power-up, the FIFO must be reset with a Master Reset
(MR) cycle. During an MR cycle, the user can initialize the device
by choosing the direction of FIFO operation (see Table 1). There is
a minimum LOW period for MR, but no maximum time. The state
ofBYPA is latched internally by the rising edge ofMR and used to
determine the direction of subsequent data operations.
Resetting the FIFO
During the reset condition (see Table 1),lh~ FIFO three-states
the data ports, sets BDA and HF HIGH, ElF LOW, and ignores
the state of BYPA!B and STBA/B. The bypass registers are initialized to zero. During this time the user is expected to set the direction of the FIFO by driving BYPA HIGH or LOW, and BYPB,
STBA, and STBB HIGH. If BYPA is LOW (selecting direction
B>A), the FIFO will then remain in a reset condition until the
user terminates the reset operation by driving BYPA HIGH. If
BYPA is HIGH (selecting direction A> B), the reset condition ter-
minates after the rising edge of MR. The entire reset phase can be
accomplished in one cycle time of tRe.
FIFO Operation
( e oPjration of the FIFO requires only one control pin per port
STBX . The user determines the direction ofthe FIFO data flow
by initiating an MR cycle (see Table 1), which clea~ the FIF
40
(J
w
li!
:::>
5l
= 25'C
5.5
SUPPLY VOLTAGE
M
6.0
"I"
30
20
f-
:::>
o~
Vee = 5.0V
10
TA = 25'C
0
0.0
1.0
""
2.0
3.0
"
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
<" 140
.s 120
f-
z
~ 100
a:
0
.............. ..........
a:
0
50 r-.....
NORMAliZED tA
vs. AMBIENT TEMPERATURE
NORMAliZED tA
vs. SUPPLY VOLTAGE
0 1.1
w
N
:::;
25
125
AMBIENT TEMPERATURE (0G)
60
!zw
a:
a:
Jl1.2
:::; 1.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
----
0.6
-55
:::>
~
Vee = 5.0V
25
125
AMBIENT TEMPERATURE (0G)
5-119
(J
:.:
~ 60
!:;
o~
/
80
40
/
o 1/
0.0
V
..".,
/
Vee = 5.0V
20
TA = 25'C
I
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
CY7C439
1YPical DC and AC Characteristics (continued)
NORMALIZED tA CHANGE
vs. OUTPUT LOADING
NORMALIZED Icc
vs. CYCLE FREQUENCY
1.6
1.3
1.5
1.1
.5-
ew
!:l 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
Range
Commercial
Industrial
Military[lj
Ambient
Temperature
O°C to +70°C
Vee
5V ± 10%
- 40°C to +85°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Pin Definitions
Signal Name
I/O
Description
Do-s
I
Data Inputs: when the FIFO is not full and ENW is active, CKW (rising edge)
writes data (Do - Ds) into the FIFO's memory
Oo-s
0
Data Outputs: when the FIFO isnot empty and ENR is active, CKR (rising edge)
reads data (00 - Os) out of the FIFO's memory
ENW
I
Enable Write: enables the CKW input
ENR
I
Enable Read: enables the CKR input
CKW
I
Write Clock: the rising edge clocks data into the FIFO when ENW is LOW and
updates the Almost Full flag state
CKR
I
Read Clock: the rising edge clocks data out ofthe FIFO when ENR is LOW and
updates the Almost Empty and Empty flag states
Fl
0
Flag 1: is used in conjunction with flag 2 to decode which state the FIFO is in
(see Table 1)
F2
0
Flag 2: is used in conjunction with Flag 1 to decode which state the FIFO is in
(see Table 1)
MR
I
Master Reset: resets the device to an empty condition
Note:
1. TA is the "instant on" case temperature.
5-123
CY7C441
CY7C443
~
:'rcYPRESS
Electrical Characteristics Over the Operating Range!2]
Parameter
VOH
VOL
VJH
VIL
IIX
IOS[3]
leel[4]
Description
Test Conditions
Output HIGH Voltage Vee = Min.,loH = - 2.0 rnA
Output LOW Voltage Vee = Min., 10L = 8.0 rnA
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Vee = Max.,
Current
GND5VI5 Vee
Output Short
Vee = Max., VOUT = GND
Circuit Current
Operating Current
Vee = Max., lOUT = 0 rnA Corn'l
led5]
Operating Current
ISB[6]
Standby Current
7C441-14
7C443-14
Min. Max.
2.4
0.4
2.2
Vee
- 3.0 0.8
-10 +10
7C441-20
7C443-20
Min. Max.
2.4
0.4
2.2
Vee
- 3.0 0.8
- 10 +10
7C441-30
7C443-30
Min. Max.
2.4
0.4
2.2
Vee
- 3.0 0.8
-10 +10
- 90
- 90
- 90
140
150
70
80
30
30
Mi1!Ind
Vee = Max., lOUT = 0 rnA Corn'l
Mi1!Ind
Vee = Max., lOUT = 0 rnA Corn'l
MiVlnd
Unit
V
V
V
V
J.tA
rnA
120
130
70
80
30
30
100
110
70
80
30
30
rnA
rnA
rnA
rnA
rnA
rnA
Capacitance[7]
Description
Parameter
eIN
Input Capacitance
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. Thst no more than one output at a time and do not test any ontpnt for
more than one second.
4. Input signals switch from OV to 3V with a rise/fall time of 3 ns or less,
clocks and clock enables switch at maximum frequency (fMAX), while
data inputs switch at fMAX!2. Outputs are unloaded.
Unit
pF
Max.
10
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
5.
Input signals switch from OV to 3V with a rise/fall time less than 3 ns,
clocks and clock enables switch at 20 MHz, while the data inputs switch
at 10 MHz. Outputs are unloaded.
6. All inputs signals are connected to Vee. All outputs are unloaded.
Read and write clocks switch at maximum frequency (fMAX).
7. Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveform[8,9]
R1500Q
eLI
INCLUDING _
JIG AND SCOPE
Equivalent to:
=t1
ALL INPUT PULSES
OUTP~~~
,W
GND
~i3Q
5.3ns
_
C441-4
10~%
I-
~
10%
___
5.3 ns
C441-5
THEvENIN EQUIVALENT
200Q
OUTPUT~o----~'~~~~-----ao2V
5-124
CY7C441
CY7C443
-. -:::4:
JCYPRESS
Switching Characteristics Over the Operating Rangd 2,JO]
7C441-14
7C443-14
Description
Parameter
Min.
Max.
7C441-20
7C443-20
Min.
Max.
7C441-30
7C443-30
Min.
Max.
Unit
tCKw
Write Clock Cycle
14
20
30
ns
tCKR
Read Clock Cycle
14
20
30
ns
tCKH
Clock HIGH
6.5
9
12
ns
9
12
ns
tCKL
Clock LOW
tA PJ ]
Data Access Time
tOH
Previous Output Data Hold After Read HIGH
0
0
0
ns
tFH
Previous Flag Hold After Read/Write HIGH
0
0
0
ns
tSD
DataSet-Up
7
9
12
ns
tHD
Data Hold
0
0
0
ns
tSEN
Enable Set-Up
7
9
12
ns
tHEN
Enable Hold
0
0
0
tFD
Flag Delay
tSKEWJ[J2]
Opposite Clock After Clock
0
0
0
ns
tSKEW2(13]
Opposite Clock Before Clock
14
20
30
ns
tpMR
Master Reset Pulse Width (MR LOW)
14
20
30
ns
6.5
10
20
15
10
15
ns
ns
20
ns
tscMR
Last Valid Clock LOW Set-Up to MR LOW
0
0
0
ns
tOHMR
Data Hold From MR LOW
0
0
0
ns
tMRR
Master Reset Recovery (MR HIGH Set-Up to First
Enabled Write/Read)
14
20
30
ns
tMRF
MR HIGH to Flags Valid
14
20
30
ns
tAMR
MR HIGH to Data Outputs LOW
14
20
30
ns
Notes.
S. CL = 30 pF for all AC parameters.
9. All AC measurements are referenced to J.5y.
10. Test conditions assume signal transition time of3 TIS or less, timing reference levels of1.SV, and output loading as shown in theACTest Loads
and Waveforms and capacitance as in note NO TAG, unless otherwise
specified.
11. Access time includes all data outputs switching simultaneously.
12. tSKEWl is the minimum time an opposite clock can occur after a clock
and still be guaranteed not to be included in the current clock cycle (for
purposes offlag update). If the opposite clock occurs less than tSKEWl
after the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. Note: The opposite clock
IS the signal to which a flag is not synchronized; i.e .• CKW is the opposIte clock for Empty and Almost Empty flags, CKR is the the opposite
clock for the Almost Full flag. The clock is the signal to which a flag is
synchronized; i.e .• CKW is the clock for the Almost Full flag, CKR is the
clock for Empty and Almost Empty flags.
13. tSKEW2 is the minimum time an opposite clock can uccur before a clock
and still be guaranteed to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEW2
before the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is abritrary. See Note NO TAG for definition of clock and opposite clock.
5-125
CY7C441
CY7C443
-.,~
'CYPRESS
Switching Waveforms
Write Clock Timing Diagram
Read Clock Timing Diagram
CKR
QO - 8
C441-7
Master Reset Timing Diagram[14,15,16,17]
1+-----
tpMR
-------1
CKW
CKR
ENR
QO- 8
ALL DATA
OUTPUTS LOW
VALID DATA
tMRFZl
,2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
Range
Commercial
Industrial
Military(3]
Ambient
Temperature
O°Cto +70°C
Vee
5V ± 10%
-40°C to +85°C
5V ± 10%
-55°Cto +125°C
5V ± 10%
Notes:
1. 71.4-MHz operation is available only in the standalone configuration.
2. The -14 device cannot be cascaded.
3. TA is the "instant on" case temperature.
5-139
I
CY7C451
CY7C453
¥-.~
•
'CYPRESS
Pin Definitions
Signal Name
I/O
Description
Do-s
I
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (Do _ 8) into the
FIFO's memory. IfMR is asserted at the rising edge ofCKW then data is written into the FIFO's programming
register. Ds is ignored if the device is configured for parity generation.
00-7
0
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (00 -7) out of the
FIFO's memory. If MR is active at the rising edge of CKR then data is read from the programming register.
Og/PG/PE
0
Function varies according to mode:
Parity disabled - same function as 00 - 7
Parity enabled, generation - parity generation bit (PG)
Parity enabled, check - Parity Error Hag (PE)
ENW
I
Enable Write: enables the CKW input (for both non-program and program modes)
ENR
I
Enable Read: enables the CKR input (for both non-program and program modes)
CKW
I
Write Clock: the rising ~e clocks data into the FIFO when ENW is LOW; updates Half Full, Almost Full, and
Full flag states. When MR is asserted, CKW writes data into the program register.
CKR
I
Read Clock: the rising ed~ocks data out of the FIFO when ENR is LOW; updates the Empty and Almost
Empty flag states. When MR is asserted, CKR reads data out of the program register.
HF
0
Half Full Hag - synchronized to CKW.
ElF
0
Empty or Full Hag - E is synchronized to CKR; F is synchronized to CKW
PAFE/ID
0
Dual-Mode Pin:
Not Cascaded - Programmable Almost Full is synchronized to CKW; Programmable Almost Empty is synchronized to CKR
Cascaded - Expansion Out signal, connected to XI of next device
Xl
I
Not Cascaded - XI is tied to Vss
Cascaded - Expansion Input, connected to XO of previous device
FL
I
First Load Pin:
Cascaded - the first device in the daisy chain will have FL tied to Vss; all other devices will have FL tied to Vee
(Figure2)
Not Cascaded - tied to Vee
MR
I
Master Reset: resets device to empty condition.
__
Non-Programming Mode: program register is reset to default condition of no parity and PAPE active at 16 or
less locations from Full/Empty.
Programming Mode: Data present on Do _ 8 is written into the programmable register on the rising edge of
CKW. Program register contents appear on 00 _ 8 after the rising edge of CKR.
OE
I
Output Enable for 00 _ 7 and Os/PG/PE pins
5-140
CY7C451
CY7C453
Electrical Characteristics Over the Operating Rangd4]
Parameter
Description
7C451-14
7C453-14
Min. Max.
Test Conditions
VOH
Output HIGH Voltage Vee = Min., 10H = - 2.0 rnA
2.4
VOL
VIH[S]
Output LOW Voltage
Input HIGH Voltage
2.2
VIL[S]
Input LOW Voltage
IIX
Input Leakage
Current
IOS[6]
Output Short
Circuit Current
10ZL
10ZH
leC1[7]
Output OFF, High Z OE L VIH, Vss < Vo < Vee
Current
-3.0
Vee
0.8
Vee = Max.
-10
+10
Vee = Max., VOUT = GND
-90
-10
MillInd
lee2[8]
Vee = Max., lOUT = 0 rnA Corn'!
Operating Current
MiVlnd
ISB[9]
Vee = Max., lOUT = 0 rnA Corn'!
Standby Current
2.4
MillInd
2.4
2.2
2.2
V
V
V
!lA
-3.0
-3.0
Vee
0.8
-10
+10
-10
+10
-10
-90
+10
-10
Unit
0.4
Vee
0.8
-90
+10
7C451-30
7C453-30
Min. Max.
0.4
0.4
Vee = Min., 10L = 8.0 rnA
Vee = Max., lOUT = 0 rnA Corn'l
Operating Current
7C451-20
7C453-20
Min. Max.
V
rnA
+10
!lA
140
120
100
rnA
150
130
110
rnA
70
70
70
rnA
80
80
80
rnA
30
30
30
rnA
30
30
30
rnA
Capacitance[lO]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
25°C, f = 1 MHz,
Vee = S.OV
TA =
Max.
10
12
Unit
pF
pF
AC Thst Loads and Waveforms[ll, 12, 13, 14, ISJ
R1500Q
ALL INPUT PULSES
OUTP~~~
CLI
INCLUDING _
JIG AND SCOPE
Equivalent to:
3.0V
~i3Q
GND
_
C451-4
C451-5
THEVENIN EQUIVALENT
200Q
OUTPUTo~----~Y~'__--~o2V
Notes:
4. See the last page ofthis specification for Group A subgroup testing in-
formation.
5.
6.
7.
8.
---"::11"----_.
90%
The YIa and V IL specifications apply for all inputs exc~XI and FL.
The XI pin is not a TTL input. It is connected to either XO ofthe previous device or V ss. FL must be connected to either V ss or Vee.
Test no more than one output at a time for not more than one second.
Input signals switch from OV to 3V with a rise/fall time of 3 ns or less,
clocks and clock enables switch at maximum frequency (fMAX), while
data inputs switch at fMAXf2. Outputs are unloaded.
Input signals switch from OV to 3V with a rise/fall time less than 3 ns,
clocks and clock enables switch at 20 MHz, while the data inputs switch
at 10 MHz. Outputs are unloaded.
9.
All inputs signals are connected to Vee. All outputs are unloaded.
Read and write clocks switch at maximum frequency (fMAX)'
10. Tested initially and after any design or process changes that may affect
these parameters.
11. CL = 30 pF for all AC parameters except for tOHZ.
12. CL = 5 pF for tOHZ.
13. All AC measurements are referenced to l.5V except tOE, tOLZ, and
tOHZ·
14. tOE and tOLZ are measured at ± 100 mY from the steady state.
15. tOHZ is measured at +500 mY from VOL and - 500 mV from VOH-
5-141
I
CY7C451
CY7C453
Switching Characteristics Over the Operating Rangel4,16)
7C4S1-14
7C453-14
Parameter
Description
Min.
Max.
7C451-20
7C453-20
Min.
Max.
7C451-30
7C453-30
Min.
Max.
Unit
tCKW
Write Clock Cycle
14
20
30
ns
tCKR
Read Clock Cycle
14
20
30
ns
tCKH
Clock HIGH
6.5
9
12
ns
tCKL
tA[I?)
Clock LOW
6.5
9
i2
Data Access Time
tOH
Previous Output Data Hold After Read HIGH
0
0
0
ns
tFH
Previous Flag Hold After Read/Write HIGH
0
0
0
ns
10
15
ns
20
ns
tSD
DataSet-Up
7
9
12
ns
tHO
Data Hold
0
0
0
ns
tSEN
Enable Set-Up
7
9
12
ns
tHEN
Enable Hold
0
0
0
tOE
tOLZ[lO, 18]
OE LOW to Output Data Valid
tOHZ[lO, 18]
OE HIGH to Output Data in High Z
10
15
20
ns
tpo
Read HIGH to Parity Generation
10
15
20
ns
tpE
Read HIGH to Parity Error Flag
10
15
20
ns
tFD
tSKEW1[19)
Flag Delay
10
15
20
ns
Opposite Clock After Clock
0
0
0
ns
tSKEWZ[ZO)
Opposite Clock Before Clock
14
20
30
ns
tpMR
Master Reset Pulse Width (MR LOW)
14
20
. 30
ns
tSCMR
Last Valid Clock LOW Set-Up to MR LOW
0
0
0
ns
tOHMR
Data Hold From MR LOW
0
0
0
ns
tMRR
Master Reset Recovery
(MR HIGH Set-Up to First Enabled Write/Read)
14
20
30
ns
tMRF
MR HIGH to Flags Valid
14
20
30
tAMR
MR HIGH to Data Outputs LOW
14
20
30
tSMRP
Program Mode-MR LOW Set-Up
14
tHMRP
Program Mode-MR LOW Hold
10
tFfP
Program Mode-Write HIGH to Read HIGH
14
tAP
Program Mode-Data Access Time
tOHP
Program Mode-Data Hold Time from MR HIGH
15
10
OE LOW to Output Data in Low Z
0
0
0
20
ns
ns
ns
ns
30
ns
15
25
ns
20
30
14
0
ns
20
20
0
ns
30
0
ns
ns
Notes:
16. Thst conditions assume signal transition time of3 ns or less, timing reference levels of l.Sv, and output loading as shown in AC Thst Loads
and Waveforms and capacitance as in notes 11 and 12, unless otherwise
specified.
17. Access time includes all data outputs switching simultaneously.
18. At any given temperature and voltage condition, tOLz is greater than
tOHZ for any given device.
19. tSKEW! is the minimum time an opposite clock can occur after a clock
and still be guaranteed not to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEW!
after the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. Note: The opposite clock is
the signal to which a flag is not synchronized; i.e., CKW is the opposite
clock for Empty and Almost Emptyflags, CKR is the the opposite clock
for the Almost Full, Half Full, and Full flags. The clock is the signal to
which a flag is synchronized; i.e., CKW is the clock for the HalfFull,AImost Full, and Full flags, CKR is the clock for Empty and Almost
Empty flags.
20. tSKEW2 is the minimum time an opposite clock can occur before a clock
and still be guaranteed to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEW2
before the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. See Note 19 for definition
of clock and opposite clock.
5-142
CY7C451
CY7C453
Switching Waveforms
Write Clock Timing Diagram
C'rWI
Do - 8
Read Clock Timing Diagram
CKR
00 - 8
NEW WORD
Ii
C451-7
Master Reset (Default with Free-Running Clocks) Timing Diagram[21, 22, 23, 24]
________________
~~---------tpMR
--------~~
1 _________________________
C'rWI
CKR
0 0 -8
ALL DATA
VALID DATA
OUTPUTSLQW
C451-8
5-143
CY7C45 1
CY7C453
Switching Waveforms (continued)
Master Reset (Programming Mode) Timing Diagram[23, 24]
00-8
CKR
ENR __LO_W____________+-______________________+-______~______~--------------------------------00-8
ALL DATA
OUTPUTS LOW
VALID DATA
C451-9
Master Reset (Programming Mode with Free-Running Clocks) Timing Diagram[23, 24]
tHMRP
MR
CKW
ENW
00-8
CKR
ENR
ALL DATA
OUTPUTS LOW
00-8
C451-10
Notes:
21. Th only =rm reset (no programming), the following criteria must
be met:
or CKW must be inactive while MR is LOW.
22. Th only ~rm reset (no programming), the following criteria must
be met: ENR or CKR must be inactive while MR is LOW
23. All data outputs (Qo _ 8) go LOW as a result of the rising edge of MR
after tAMR.
24. In this example, Qo _ 8 will remain valid until tOHMR if either the first
read shown did not occur or if the read occurred soon enough such that
the valid data was caused by it.
5-144
CY7C451
CY7C453
L~
~'CYPRESS
Switching Waveforms (continued)
Read to Empty Timing Diagram[25, 28, 29J
1 (NO CHANGE)
COUNT
LATENT CYCLE
CKR
CKW
E/F
LOW
C451-12
Read to Empty Timing Diagram with Free-Running Clocks[25, 26, 27, 28J
LATENT CYCLE
COUNT
E
CKR
CKW
LOW
C451-11
Notes:
25. "Count" is the number of words in the FIFO.
26. The FIFO is assumed to be programmed with P > 0 (i.e., PAFE does not
transition at Empty or Full).
27. R2 is ignored because the FIFO is empty (count = 0). It is important
to note that R3 is also ignored because W3, the first enabled write after
empty, occurs less than tSKEW2 before R3. Therefore, the FIFO still
appears empty when R3 occurs. Because W3 occurs greater than
tSKEW2 before R4, R4 includes W3 in the flag update.
28. CKR is clock; CKW is opposite clock.
29. R3 updates the flag to the Empty state by asserting ElF. Because WI
occurs greater than tSKEW! after R3, R3 does not recognize WI when
updating flag status. But because WI occurs greater than tSKEW2 before R4, R4 includes WI in the flag update and, therefore, updates
FIFO to Almost Empty state. It is important to note that R4 is a latent
cycle; i.e., it only updates the flag status regardless ofthe state of ENR.
It does not change the count or the FIFO's data outputs.
5-145
CY7C451
CY7C453
&~
.'CYPRESS
Switching Waveforms (continued)
Read to Almost Empty Timing Diagram with Free-Running Clocks[25, 28, 30]
COUNT
17
16
17
18
17
16
15
CKR
Ef\IR
CKW
ENW
HIGH
RF
HIGH
ElF
t_ffi_~~--------------------t-FO-~
AAFE__________
tFO~-------C451-14
Read to Almost Empty Timing Diagram with Read Flag Update Cycle and Free-Running Clocks[25, 28, 30, 31, 32]
18 {no change}
COUNT
17
RF
HIGH
ElF
HIGH
16
17
FLAG UPDATE CYCLE
18
17
16
15
C451-13
Notes:
30. The FIFO in this example is assumed to be programmed to its default
flag values. Almost Empty is 16 words from Empty; Almost Full is 16
locations from Full.
31. R4 only updates the flag status. It does not affect the count because
ENRis IDGH.
3Z. When making the transition from Almost Empty to Intermediate, the
count must increase by two (16 .18; two enabled writes: WZ, W3) before a read (R4) can update flags to the Less Than Half Full state.
5-146
CY7C451
CY7C453
=r_.,~
""=or? CYPRESS
Switching Waveforms
(continued)
Write to Half Full Timing Diagram with Free-Running Clocks[25, 33, 34, 35]
COUNT
1024
[256J
1025
[257J
1023
[255J
1024
[256J
1025
[257J
1024
[256J
1026
[258J
CIWV
ENW
CKR
ENR
'--------'/
HF
Ell"
PAFE
HIGH
HIGH
C451-15
Write to Half Full Timing Diagram with Write Flag Update Cycle with Free-Running Clocks[25, 33, 34, 35, 36, 37]
1023 (no change)
[255J
COUNT 1024
[256J
1025
[257]
1024
[256J
FLAG UPDATE CYCUE
1023
[255J
1024
[256J
1025
[257J
1026
[258J
CIWV
ENW
CKR
ENR
HF
ElF
PAFE
HIGH
HIGH
C451-16
Notes:
33. CKW is clock and CKR is opposite clock.
34. Count = 1,025 indicates Half Full for the CY7C453 and count = 257
indicates Half Full for the CY7C451. Values for CY7C451 count are
shown in brackets.
35. When the FIFO contains ug4 [256] words, the rising edge ofthe next
enabled write causes the HF to be true (LOW).
36. The HFwrite flag update c~e does not affect the count because ENW
is HIGH. It only updates HF to HIGH.
37. When making the transition from HaJfFull to Less Than Half Full, the
count must decrease by two (1,025 .1,023; two enabled reads: R2 and
R3) before a write (W4) can update flags to less than Half Full.
5-147
-=-,
CY7C451
CY7C453
.a=._.,~
CYPRESS
Switching Waveforms
(continued)
Write to Almost Full Timing Diagram[25, 30,33, 38, 39J
COUNT
2030
[494)
2031
[495)
2032
[496)
2031
[495)
2030
[494)
2031
[495)
-20'30'''
: !4~L ~
r
2032
[496)
r
20-3r ..
: !4~5L ;
2033
[497)
r
20'32
'I
: !4~6L ;
CKW
CKR
,_-----,t- - - - - - ~F~-1
LOW
HIGH
C451-18
Write to Almost Full Timing Diagram with Free-Running Clocks[25, 30, 33J
COUNT
2031
[495)
2032
[496]
2031
[495)
2030
[494)
2031
[495]
2032
[496]
2033
[497]
CKW
ENW
CKR
ENR
HI'
LOW
ElF
HIGH
l"AFE
tFD~
C451-17
Notes:
38. W2 updates the flag to the Almost Full state by asserting PAFE. Because Rl occurs greater than tSKEW] after W2, W2 does not recognize
Rl when updating the flag status. W3 includes R2in the flag update because R2 occurs greater than tSKEW2 before W3. Note that W3 does
not have to be enabled to update flags.
39. The dashed lines showW3 as aflagupdatewriteratherthan anenab]e d
write because ENW is deasserted.
5-148
CY7C451
CY7C453
Switching Waveforms
(continued)
Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks[25, 30, 33]
2030 (no change)
[494J
FLAG UPDATE CYCLE
COUNT
C'rWV
ENW
CKR
ENR
LOW
RF
HIGH
ElF
tFD1
PAFE
C451-19
Write to Full Flag Timing Diagram with Free-Running Clocks[25, 26, 33, 40]
LATENT CYCLE
COUNT
C'rWV
CKR
ENR
RF
LOW
tFD1
ElF
PAFE
LOW
C451-20
Notes:
40. W2 is ignored because the FIFO is full (count = 2,048 [512]). It isimportant to note that W3 is also ignored because R3, the first enabled
read after full, occurs less than tSKEW2 before W3. Therefore, the
FIFO still appears full when W3 occurs. Because R3 occurs greater
than tSKEW2 before W4, W4 includes R3 in the flag update.
5-149
I
CY7C451
CY7C453
Switching Waveforms (continued)
Even Parity Generation Timing Diagram[41, 42]
CKR
QalPG/PE
QO-7
-1
ENABLED READ
tpo
DISABLED READ
----+I
PREVIOUS WORD:
EVEN NUMBER OF 18
,,~--
NEW WORD
ODD NUMBER OF 18
t
CKR
Oa/PG / ' - - - - - - - - - - - - - - - - - 1 ~--------PE
Oo-HF
1
1
0
494
2030
Flag Update
>HF
1
1
0
494
2030
Write
(EiiIW=O)
>HF
1
1
0
495
2031
Write
>HF
1
1
0
495
2031
Write
AF
(ENW =0)
1
0
0
496
2032
Write (nansition from
>HF to AF)
Notes:
48. Applies to both CY7C451 and CY7C453 operations when devices are
programmed so that Almost Empty becomes active when the FIFO
contains 32 or fewer words.
49. Programmed so that Almost Full becomes active when the FIFO contains 16 or less empty locations.
5-156
CY7C451
CY7C453
Table 5. Programmable Almost Full/Almost Empty Options - CY7C451/CY7C453[50j
p[51j
D5
D4
D3
D2
Dl
DO
0
0
0
0
0
0
0
0
0
0
0
1
16 or less locations from Empty/Full (default)
1
0
0
0
0
1
0
32 or less locations from Empty/Full
2
0
0
0
0
1
1
48 or less locations from Empty/Full
3
PAFE Active when CY7C451/453 is:
0
Completely Full and Empty.
224 or less locations from Empty/Full
240 or less locations from Empty/Full
992 or less locations from Empty/Full
1008 or less locations from Empty/Full
Table 6. Programmable Parity Options
D8
D7
D6
0
X
X
Parity disabled.
1
0
0
Generate even parity on PG output pin.
1
0
1
Generate odd parity on PG output pin.
1
1
0
Check for even parity. Indicate error on PE output pin.
1
1
1
Check for odd parity. Indicate error on PE output pin.
Condition
Notes:
50. D4 and D5 are don't care for CY7C451.
51. Referenced in Table 1.
5-157
CY7C451
CY7C453
lYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
NORMALIZED SUPPLY CURRENT
v•• SUPPLY VOLTAGE
1.4 , . . . - - , . . - - - , - - - . - - - - ,
~
:::i
~
II:
1.1
1.2
Jl
c
1.0 ~---+--~~--_4----~
~
:::i
~
II:
az
~ 0.8 i--7I'I!:..j---0.6 L:----:L::----~--_::l-=---...J
4
4.5
5
5.5
6
1.0
I~
az
0.9
o
25
125
AMBIENT TEMPERATURE (0G)
1-----
4.0
z
1.0
....---
0.8
4.5
5.0
5.5
~
1 60
!zw
50
a
40
a:
a:
w
~ 30
:::l
1il
20
I
""
~
~
5
a
10
o
25
OUTPUT SOURCE CURRENT v••
OUTPUT VOLTAGE
TA = 25°C,
Vee=5.0V
o
1
~
/
15.0
10.0
5.0
~
V
"V
:..J
~
-
~
«
125
V
1/
o
200 400 600 800 1000
CAPACITANCE (pF)
f----
1:::
OUTPUT SINK CURRENT vs.
OUTPUT VOLTAGE
TA =125oc,
Vee=5.0V
!zw
a: 80
a:
:::l
"- ~
2
I
g20.0
AMBIENT TEMPERATURE (OC)
SUPPLY VOLTAGE (V)
100
o
0.6
-55
6.0
I
Vee = 5.0V
25.0 ~ t- TA = 25°C
----
~ 1.2
~
I
25
50
75
FREQUENCY (MHz)
30.0
cw
g5
o
TYPICAL tA CHANGE vs.
OUTPUT LOADING
Vee = 5.0V
I
~
Vee = 5.0V
TA=25°C
V'N=3.0V
/'
v,.
V
.-""
"" 1.0
0.5
o
$1.4
w
/
~
1.6
S. 1.1
C
~
~
NORMALIZED tA
AMBIENT TEMPERATURE
~ 25°C
TA
V
c
:::i 0.7
~
0.8
-55
NORMALIZED tA v••
SUPPLY VOLTAGE
1.2
/
u 0.9
2
0.9
SUPPLY VOLTAGE (V)
II:
Vee=5.0V
V N=3.0V _
'
f=50MHz
1.1
Jl1.2
c
NORMALIZED SUPPLY
CURRENT v•• FREQUENCY
v•• AMBIENT TEMPERATURE
3
OUTPUT VOLTAGE (V)
~
60
~
40
z
V
:::l
"
1=:::l
a
4
20
o
II
o
/
-
-
/
1
2
3
OUTPUT VOLTAGE (V)
5-158
4
CY7C451
CY7C453
Ordering Information
Speed
(ns)
14
20
30
Ordering Code
14
20
30
Package 'JYpe
Operating
Range
CY7C451-14DC
D32
32-Lead (300-Mil) CerDIP
CY7C451-14JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C451-14JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C451-14DMB
D32
32-Lead (300-Mil) CerDIP
Military
CY7C451-14LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C451-20DC
D32
32-Lead (300-Mil) CerDIP
CY7C451-20JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C451-20JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C451-20DMB
D32
32-Lead (300-Mil) CerDIP
Military
CY7C451-20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Commercial
Commercial
CY7C451-30DC
D32
32-Lead (300-Mil) CerDIP
CY7C451-3OJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C451-30JI
D32
32-Lead (300-Mil) CerDIP
Industrial
CY7C451-30DMB
D32
32-Lead (300-Mil) CerDIP
Military
CY7C451-30LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Package
Name
Package
1Ype
Speed
(ns)
Package
Name
Ordering Code
Commercial
Operating
Range
CY7C453-14DC
D32
32-Lead (300-Mil) CerDIP
CY7C453-14JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C453-14JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C453-14DMB
D32
32-Lead (300-Mil) CerDIP
Military
CY7C453-14LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C453-20DC
D32
32-Lead (300-MiI) CerDIP
CY7C453 - 20JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C453 - 20JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C453-20DMB
032
32-Lead (300-MiI) CerDIP
Military
CY7C453 - 20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C453 - 30DC
D32
32-Lead (300-MiI) CerDIP
CY7C453 - 30JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C453-30JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C453 - 30DMB
D32
32-Lead (300-Mil) CerDIP
Military
CY7C453-30LMB
L55
32-Pin Rectangular Leadless Chip Carrier
5-159
Commercial
E
CY7C451
CY7C453
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIH
VIL
Ilx
ICCl
Iccz
ISB
los
loz
Switching Characteristics
Parameter
Subgroups
tCKW
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
tCKR
tCKH
tCKL
tA
tOH
tpH
tSD
tHD
tSEN
tHEN
tOE
tpG
tpE
tpD
tSKEWl
tSKEW2
tpMR
tSCMR
tOHMR
tMRR
tMRP
tAMR
tSMRP
tHMRP
tFJ'P
tAP
tOHP
Document #: 38-00125-E
5-160
CY7C455
CY7C456
CY7C457
512 X 18, lK X 18, and 2K X 18
Cascadable Clocked FIFOs
with Programmable Flags
Features
Functional Description
• 512 x 18 (CY7C455), 1,024 x 18
(CY7C456), 2,048 x 18 ( CY7C457)
FIFO buffer memory
• Expandable in width
• Expandable in depth
• High-speed 70-MHz standalone;
50-MHz cascaded
• Supports free-running 50% duty cycle
clock inputs
• Empty, Full, Half Full, and programmable Almost Empty and Almost Full
status flags
• Parity generation/checking
• Fully asynchronous and simultaneous
read and write operation
• Output Enable (OE) pin
• Independent read and write enable
pins
• Center power and ground pins for reduced noise
• 52-pin PLCC and 52-pin PQFP
• Proprietary 0.81l CMOS technology
• TTL compatible
The CY7C455, CY7C456, and CY7C457
are high-speed,low-power, first-in first-out
(FIFO) memories with clocked read and
write interfaces. All are 18 bits wide. The
CY7C455 has a 512-word memory array,
the CY7C456 has a 1,024-word memory
array, and the CY7C457 has a 2,048-word
memory array. The CY7C455, CY7C456,
and CY7C457 can be cascaded to increase
FIFO depth. Programmable features include Almost Full/Empty flags and generation/checking of parity. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data
acquisition, multiprocessor interfaces, and
communications buffering.
These FIFOs have 18-bit input and output
ports that are controlled by separate clock
and enable signals. The input port is controlled by a free-running clock (CKW) and
a write enable pin (ENW).
When ENW is asserted, data is written
into the FIFO on the rising edge of the
Logic Block Diagram
CKW signal. While ENW is held active,
data is continually written into the FIFO
on each CKW cycle. The output port is
controlled in a similar manner by a freerunning read clock (CKR) and a read enable pin (ENR).
In addition, the
CY7C455, CY7C456, and CY7C457 have
an output enable pin (OE). The read
(CKR) and write (CKW) clocks may be
tied together for single-clock operation or
the two clocks may be run independently
for asynchronous read/write applications.
Clock frequencies up to 71.4 MHz are
achievable in the standalone configuration, and up to 50 MHz is achievable when
FIFOs are cascaded for depth expansion.
Depth expansion is possible using the cascade input (XI), cascade output (XO), and
First Load (FL) pins. The XO pin is connected to the XI pin of the next device, and
the XO pin of the last device should be
connected to the XI pin of the first device.
The FL pin of the first device is tied to V ss.
Pin Configuration
PLCC
Top View·
;[
8~r!fr!!tJrf~~~8gJg
7 6 5 4 3 2
D,
0,
Do
XI
AI'
ElF
PAFEtxO
=
CKW
AI'
ElF
j«j!I'J\FE
00
a,
a,
a,
8
9
10
11
12
13
14
15
16
17
18
19
20
~ 1~
52 51 50 49 48 47
46
45
44
43
42
41
40
39
38
37
36
35
34
0"
0,.
D,s
0'6
0"
IT
MIl
CKR
EI'lR
DE
0,,/PG2/PE2
0,6
a,s
212223242526272829 30 313233
0455·1
00 - ,. OalPG1!1'Ef
09-,6. 017/PG2/PE2
CKR
5-161
c455·2
E
•.
CY7C455
CY7C456
CY7C457
,~
; CYPRESS
Pin Configurations (continued)
Functional Description (continued)
The CY7C455, CY7C456, and CY7C457 provide three status pins.
These pins are decoded to detennine one of six states: Empty, Almost
Empty, Less than or Equal to Half Full, Greater than Half Full, Almost Full, and Full ~ Table 1). The Almost Empty/Full flag
(PAFE) shares the XO pin on the CY7C455, CY7C456, and
CY7C457. This flag is valid in the standalone and width-expansion
configurations. In the depth expansion, this pin provides the expansion out (XO) information that is used to signal the next FIFO
when it will be activated.
The flags are synchronous, Le., they change state relative to either
the read clock (CKR) or the write clock (CKW). When entering or
exiting the Empty and Almost Empty states, the flags are updated
exclusively by the CKR. The flags denoting Half Full, Almost Full,
and Full states are updated exclusively by CKW. The synchronous
flag architecture guarantees that the flags maintain their status for
some minimum time. This time is typically equal to approximately
one cycle time.
The CY7C45X uses center power and ground for reduced noise.
All configurations are fabricated using an advanced 0.81-1 N-well
CMOS technology. Input ESD protection is greater than 2001V,
and latch-up is prevented by the use of guard rings and a substrate
bias generator.
PQFP
ThpVlew
~
80
cr r! 0 ~~:j~ 8 J J g
52 51 50 49 4847 4645 44 43 42 41 40
02
1
0,
0
39
38
37
36
35
34
33
32
31
30
29
Do
)(J
ENW
CKW
FiF
rtf
XCi/PAlt
00
0,
02
0,
9
10
11
12
13
013
0,•
015
016
017
1'[
IiilI!
CKR
mil
017/PG 2/PE2
0,.
28
015
c45S..a
Selection Guide
7C45X-14
7C45X-20
7C45X-30
71.4[1]
50
33.3
N/A
50
33.3
Maximum Access Time (ns)
10
15
20
Minimum Cycle Time (ns)
14
20
30
Minimum Clock HIGH Time (ns)
6.5
9
12
Minimum Clock LOW Time (ns)
6.5
9
12
Minimum Data or Enable Set-Up (ns)
5
7
9
Minimum Data or Enable Hold (ns)
1
1
1
Maximum flag Delay (ns)
10
15
20
160
140
120
Maximum Frequency (MHz)
Maximum Cascadable Frequency
Maximum Current (rnA)
I Commercial
I Industrial
Density
OE, Depth Cascadable
Package
180
160
140
CY7C455
CY7C456
CY7C457
512 x 18
1,024 x 18
2,048 x 18
Yes
Yes
Yes
52-Pin LCC/PLCC/PQFP
52-Pin LCC/PLCC/PQFP
52-Pin LCC/PLCC/PQFP
Note:
1. 71.4-MHz operation is available only in the standalone configuration.
5-162
CY7C455
CY7C456
CY7C457
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -6SoC to +lS0°C
Ambient Temperature with
Power Applied ....................... -5SoC to + 12SoC
Supply Voltage to Ground Potential ........ -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.SVto +7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 301S)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Vee
Commercial
O°C to +70°C
SV ± 10%
Industrial[2]
-40°C to +8SoC
SV ± 10%
Range
Pin Definitions
I/O
Description
DO-17
I
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (Do _ 17) into the
FIFO's memory. IfMR is asserted at the rising edge ofCKW, data is written into the FIFO's programming register. Ds, 17 are ignored if the device is configured for parity generation.
00-7
09-16
0
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (00 - 7, 09 - 16)
out of the FIFO's memory. If MR is active at the rising edge of CKR, data is read from the programming
register.
0s/PGl/PE1
017/PG2/PE2
0
Function varies according to mode:
Parity disabled - same function as 00 - 7 and 09 - 16
Parity enabled, generation - parity generation bit (PGx)
Parity enabled, check - Parity Error Flag (PBx)
ENW
I
Enable Write: Enables the CKW input (for both non-program and program modes).
ENR
I
Enable Read: Enables the CKR input (for both non-program and program modes).
CKW
I
Write Clock: The risin~e clocks data into the FIFO when ENW is LOW; updates Half Full, Almost Full, and
Full flag states. When MR is asserted, CKW writes data into the program register.
CKR
I
Read Clock: The rising e~locks data out of the FIFO when ENR is LOW; updates the Empty and Almost
Empty flag states. When MR is asserted, CKR reads data out of the program register.
HF
0
Half Full Flag: Synchronized to CKW
ElF
0
Empty or Full Flag: E is synchronized to CKR; F is synchronized to CKW.
PAFE/XO
0
Dual-Mode Pin:
Not Cascaded - programmable Almost Full is synchronized to CKW; Programmable Almost Empty is synchronized to CKR.
Cascaded - expansion out signal, connected to XI of next device.
XI
I
Expansion-In Pin~
Not Cascaded - XI is tied to Vss.
Cascaded - expansion Input, connected to XO of previous device.
FL
I
First Load Pin:
Cascaded - the first device in the daisy chain will have FL tied to V ss; all other devices will have FL tied to Vee
(Figure 1).
Not Cascaded - tied to Vee.
MR
I
__
Master Reset: Resets device to empty condition.
Non-Programming Mode: Program register is reset to default condition of no parity and PAFE active at 16 or
less locations from Full/Empty.
Programming Mode: Data present on Do _ s is written into the programmable register on the rising edge of
CKW. Program register contents appear on 00 _ S after the rising edge of CKR.
OE
I
Output Enable for 00 _ 7, 09 _ 16, 0s/PG1/PE1 and 0n/PG2/PE2 pins.
Signal Name
Note:
2. TA is the "instant on" case temperature.
S-163
E
CY7C455
CY7C456
CY7C457
=sa _~
'CYPRESS
Electrical Characteristics Over the Operating Rangd3]
7C45X-14
Parameter
Description
Test Conditions
Min.
rnA
Vee = Min., 10L = 8.0 rnA
Max.
2.4
7C45X-20
7C45X-30
Min.
Min.
Max.
VOH
Output HIGH Voltage
VOL
VIR[4]
Output LOW Voltage
Input HIGH Voltage
2.2
Vee
2.2
Vee
VIL[4]
Input LOW Voltage
-3.0
0.8
-3.0
IIX
Input Leakage
Current
Vee = Max.
-10
+10
-10
IOS[5]
Output Short
Circuit Current
Vee = Max., VOUT = GND
-90
10ZL
10ZH
Output OFF, High Z
Current
OE~ VIR, VSS
leel[6]
Operating Current
Vee = Max., lOUT = 0 rnA Com'!
Vee = Min., 10H = -2.0
0.4
< Vo < Vee
-10
Ind
Operating Current
leeP]
Vee = Max., lOUT = 0 rnA Com'!
Ind
ISB[8]
Standby Current
Vee = Max., lOUT = 0
2.4
rnA Com'!
Ind
0.4
-10
Unit
V
0.4
V
2.2
Vee
V
0.8
-3.0
0.8
V
+10
-10
+10
iJA
-90
+10
Max.
2.4
-90
+10
-10
rnA
+10
~A
160
140
120
rnA
180
160
140
rnA
90
90
90
rnA
100
100
100
40
40
40
40
40
40
rnA
rnA
rnA
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
Unit
10
pF
12
pF
AC Test Loads and Waveforms[lO, 11, 12, 13, 14]
R15000
ALL INPUT PULSES
OUTP~~:n
3.0V ---~9~0%:-:-----'~
ClI :30
INCLUDING _
JIG AND SCOPE
Equivalent to:
GND
_
-
0455.'
c455-5
THEvENIN EQUIVALENT
2000
OUTPUT~2V
Notes:
3. See the last page of this specification for Group A subgroup testing in·
formation.
4. The Ym and V IL specifications apply for all inputs exce~XI and FL.
The XI pin is not a TIL input. It is connected to either XO of the previous device or Vss. FL must be connected to either Vss or Vee.
S. Test no more than one output at a time for not more than one second.
6. Input signals switch from OV to 3V with a rise/fall time of less than 3
ns, clocks and clock enables switch at maximum frequency (fMAX),
while data inputs switch at fMAX/2. Outputs are unloaded.
7. Input signals switch from OV to 3V with a rise/fall time less than 3 ns,
clocks and clock enables switch at 20 MHz, while the data inputs switch
at 10 MHz. Outputs are unloaded.
8.
9.
10.
11.
12.
13.
14.
5-164
All input signals are connected to Vee. All outputs are unloaded.
Read and write clocks switch at maximum frequency (fMAX)'
Thsted initially and after any design or process changes that may affect
these parameters.
CL = 30 pF for all AC parameters except for tOHZ.
CL=SpFfortoHz,
All AC measurements are referenced to I.SV except tOE, tOLZ, and
tOHZ·
tOE and tOLZ are measured at ± 100 mV from the steady state.
tOHZ is measured at +Soo mV from VOL and - sao mV from VOH.
CY7C455
CY7C456
CY7C457
-=-.
=:;F
?cYPRESS
Switching Characteristics Over the Operating Rangel3, 15]
Parameter
Description
7C45X-14
7C45X-20
7C45X-30
Min.
Min.
Min.
Max.
Max.
Max.
Unit
tCKW
Write Clock Cycle
14
20
30
ns
tCKR
Read Clock Cycle
14
20
30
ns
tCKH
Clock HIGH
6.5
9
12
ns
tCKL
Clock LOW
6.5
9
12
tA
Data Access Time
tOH
Previous Output Data Hold After Read HIGH
0
0
0
ns
tFH
Previous Flag Hold After ReadIWrite HIGH
0
0
0
ns
tSD
DataSet-Up
5
7
9
ns
tHD
Data Hold
1
1
1
ns
tSEN
Enable Set-Up
5
7
9
ns
tHEN
Enable Hold
1
1
1
tOE
tOLZ[9,16J
OE LOW to Output Data Valid
tOHZ[9,16]
OE HIGH to Output Data in High Z
10
15
20
tpo
Read HIGH to Parity Generation
10
15
20
ns
tpE
Read HIGH to Parity Error Flag
10
15
20
ns
20
ns
10
15
10
OE LOW to Output Data in Low Z
0
15
0
10
ns
20
ns
20
ns
ns
0
15
ns
ns
tFD
Flag Delay
tSKEWI[17]
Opposite Clock After Clock
0
0
0
ns
tSKEWPS]
Opposite Clock Before Clock
14
20
30
ns
tpMR
Master Reset Pulse Width (MR LOW)
14
20
30
ns
tSCMR
Last Valid Clock LOW Set-Up to MR LOW
0
0
0
ns
tOHMR
Data Hold From MR LOW
0
0
0
ns
tMRR
Master Reset Recovery
(MR HIGH Set-Up to First Enabled Write/Read)
14
20
30
ns
tMRF
MR HIGH to Flags Valid
14
20
30
ns
tAMR
MR HIGH to Data Outputs LOW
14
20
30
ns
tSMRP
Program Mode-MR LOW Set-Up
14
20
30
ns
tHMRP
Program Mode-MR LOW Hold
10
15
20
ns
tFTP
Program Mode-Write HIGH to Read HIGH
14
20
30
tAP
Program Mode-Data Access Time
tOHP
Program Mode-Data Hold Time from MR HIGH
14
Notes:
15. Test conditions assume signal transition time of3 ns or less, timing reference levels of l.Sv, and output loading as shown in AC Test Loads
and Waveforms and capacitance as in notes 10 and 11, unless otherwise
specified.
16. At any given temperature and voltage condition, tOLZ is greater than
tOHZ for any given device.
17. tSKEW! is the minimum time an opposite clock can occur after a clock
and still be guaranteed not to be included in the current clock cycle (for
purposes offlag update). If the opposite clock occurs less than tSKEW!
after the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. Note: The opposite clock is
the signal to which a flag is not synchronized; i.e., CKW is the opposite
0
20
0
ns
30
0
flS
flS
clock for Empty and Almost Empty flags, and CKR is the the opposite
clock for the Almost Full, Half Full, and Full flags. The clock is the signal to which a flag is synchronized; i.e., CKW is the clock for the Half
Full, Almost Full, and Full flags, and CKR is the clock for Empty and
Almost Empty flags.
18. tSKEW2 is the minimum time an opposite clock can occur before a clock
and still be guaranteed to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEW2
before the clock, the decision of whether ornot to include the opposite
clock in the current clock cycle is arbitrary. See Note 17 for definition
of clock and opposite clock.
5-165
E
CY7C455
CY7C456
CY7C457
Switching Waveforms
Write Clock Timing Diagram
CKW
Do - 17
Read Clock Timing Diagram
CKR
0 0 -17
0455-7
Master Reset (Defanlt with Free-Rnnning Clocks) Timing Diagram[19, 20, 21, 22]
MR
________, ""1------
IpMR
----__to! ~-------------
CKW
CKR
00
-17
ALL DATA
OUTPUTS LOW
VALID DATA
c455-8
5-166
CY7C455
CY7C456
CY7C457
-~
~'CYPRESS
Switching Waveforms (continued)
Master Reset (Programming Mode) Timing Diagram[21, 22]
CKW
0 0 - 17
CKR
LOW
00 -17
ALL DATA
OUTPUTS LOW
VALID DATA
0455-9
Master Reset (Programming Mode with Free-Rnnning Clocks) Timing Diagram[21, 22]
I
tHMRP
MR
CKW
ENW
Do -17
CKR
EN"R:
ALL DATA
OUTPUTS LOW
00 -17
c455-10
Notes:
19. To only perform reset (no programming), the following criteria must
be met: ENW or CKW must be inactive while MR is LOW.
20. To only ~rm reset (no programming), the following criteria must
be met: ENR or CKR must be inactive while MR is LOW.
21. All data outputs (00 _ 17 ) go LOW as a result ofthe rising edge ofMR
afiertAMR'
22. In this example, 00 _ 17 will remain valid until tOHMR if either the first
read shown did not occur or if the read occurred soon enough such that
the valid data was caused by it.
5-167
CY7C455
CY7C456
CY7C457
Switching Waveforms
(continued)
Read to Empty Timing Diagram[23, 26, 27]
t (NO CHANGE)
COUNT
LATENT CYCLE
CKR
CKW
LOW
ElF
-------tFDt
c455-t2
Read to Empty Timing Diagram with Free-Running Clocks[23, 24, 25, 26]
LATENT CYCLE
COUNT
CKR
CKW
ENW
HF
HIGH
ElF
PAFE
ww
tFD
tFD
=t
1 tFD=t
0455·11
Notes:
23_ "Count" is the number of words in the F1FO.
24. TheF1FOisassumedtobeprogrammedwithP>O(i.e.,PAFEdoesnot
transition at Empty or Full).
25. R2 is ignored because the FIFO is empty (count = 0). It is important
to note that R3 is also ignored because W3, the first enabled write after
empty, occurs less than tSKEW2 before R3. Therefore, the F1FO still
appears empty when R3 occurs. Because W3 occurs greater than
tSKEW2 before R4, R4 includes W3 in the flag update.
26. CKR is clock and CKW is opposite clock.
27. R3 updates the flag to the Empty state by asserting ElF. Because WI
occurs greater than tSKEW! after R3, R3 does not recognize WI when
updating flag status. But because WI occurs tSKEW2 before R4, R4 includes WI in the flag update and, therefore, updates FIFO to Almost
Empty state. It is important to note that R4 is a late~e; i.e., it only
updates the flag status regardless of the state of ENR. It does not
change the count or the FIFO's data outputs.
5-168
CY7C455
CY7C456
CY7C457
-'i~
,CYPRESS
Switching Waveforms
(continued)
Read to Almost Empty Timing Diagram with Free-Running Clocks[23, 26, 28]
COUNT
17
16
17
18
17
16
15
CKR
CKYV
HF
HIGH
ElF
HIGH
tFD_~~____________________t_FD__J~-----t-FD-~~_______
____________
c455-14
Read to Almost Empty Timing Diagram with Read Flag Update Cycle with Free-Running C1ocks[23, 26, 28, 29, 30]
I
18 (no change)
FLAG UPDATE CYCLE
RF
HIGH
8F
HIGH
c455-13
Notes:
28. The FIFO in this example is assumed to be programmed to its default
flag values. Almost Empty is 16 words from Empty; Almost Full is 16
locations from Full.
29. R4 only updates the flag status. It does not affect the count because
ENRisHIGH.
30. When making the transition from Almost Empty to Intermediate, the
count must increase by two (16 t18; two enabled writes: W2, W3) before a read (R4) can update flags to the Less Than Half Full state.
5-169
CY7C455
CY7C456
CY7C457
~~
•
,CYPRESS
Switching Waveforms (continued)
Write to Half Full Timing Diagram with Free-Running Clocks[23, 31, 32, 33]
1024
COUNT
I~~~I
1025
1024
1023
1024
Iml
I~~~l
I~~~
1025
I~~~l
1026
I~~~
I~;I
Ct
e LSBs OF
WORDM-1
8 LSBs OF
WORDM+2
C455·23
Output Enable Timing[43, 44]
CKR
--------------~;I
READ M+1
,,'------------
8NR ____LO
__
W_________________________________________________________________
00-17
VALID DATA
WORDM+1
VAUDDATA
WORDM
Notes:
42. In this example, the FIFO is assumed to be programmed to check for
even parity. The 00-7 word is shown.
43. This example assumes that the time from the CKR rising edge to valid
word M+l ~ tAo The 00-7 word is shown.
44. IfENRwas HIGH around the rising edge of CKR (Le., read disabled),
the valid data at the far right would once again be word M instead of
word M+l.
5-174
CY7C455
CY7C456
CY7C457
~
=:arcYPRESS
Architecture
The CY7C45X consists of an array of 512, 1,024, or 2,048 words of
18 bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, cOEtrol signals (CKR, CKW, ENR,
ENW, and MR), and flags (HP, ElF, PAFE). The CY7C45X also
includes the control signals OE, FL, XI, and XO for depth expansion.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the Empty condition
signified by 'ElF and PAFE being LOW and HF being HIGH. All
data outputs (Qo - 17) go low at the rising edge ofMR. In orderfor
the FIFO to reset to its default state, a falling~e must occur on
MR and the user must not read or write while MR is LOW (unless
ENR and/or ENW are HIGH or unless the device is being programmed). Upon completion ofthe master reset cycle, all data outputs will go LOW tAMR after MR is deasserted. All flags are guaranteed to be valid tMRF after MR is taken HIGH.
FIFO Operation
When the ENW signal is active (LOW), data present on the
Do _ 17 pins is written into the FIFO on each rising edge of the
CKW signal. Similarly, when the ENR signal is active, data in the
FIFO memory will be presented on the Qo _ 17 outputs. New data
will be presented on each rising edge of CKR while ENR is active.
ENR must set up tSEN before CKR for it to be a valid read function. ENW must occur tSEN before CKW for it to be a valid write
function.
An output enable (OE) pin is provided to three-state the Qo - 17
outputs when OE is asserted. When OE is enabled (low), data in
the output register will be available to the Qo _ 17 outputs after
tOE. If devices are cascaded, the OE function will only output data
on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the
data ofthe lastvaJid read on its Qo _ 17 outputs even after additional reads occur.
Programming
The CY7C45X is programmed during a master reset cycle. If MR
and ENW are LOW, a rising edge on CKW will write the Do - 9, 10
or 11 inputs into the programming register[45]. MR must be set up a
minimum of tSMRP before the program write rising edge and held
tHMRP after the program write falling edge. The user has the ability
to also perform a program read during the master reset cycle. This
will occur at the rising edge of CKR when MR and ENR are asserted. The program read must be performed a minimum of tFfP
after a program write, and the program word will be available tAP
after the read occurs. If a program write does not occur, a program
read may occur a minimum oftSMRP after MR is asserted. This will
read the default program value.
When free-running clocks are tied to CKW and CKR, programming can still occur during a master reset cycle with the adherence
to a few additional timing parameters. The enable pins must be setup tSEN before the rising edge of CKW or CKR. Hold times of
tHEN must also be met for ENW and ENR.
Data present on Do _ 9 during a program write will determine the
distance from Empty (Full) that the Almost Empty (Almost Full)
flags will become active. See Table 1 for a description of the six possible FIFO states. P in Table 1 refers to the decimal equivalent of
the binary number represented by Do - 7. 8 or 9. Programming options for the CY7C45X are listed in Table 4.
The programmable PAFE function on the CY7C45X is only valid
when not cascaded. If the user elects not to program the FIFO's
flags, the default is as follows: the Almost Empty condition (Almost Full condition) is activated when the FIFO contains 16 or less
words (empty locations).
Parity is programmed with the D15 _ 17 bits. See Table 4 for a summary of the various parity programming options. Data present on
D15 - 17 during a program write will determine whether the FIFO
will generate or check even/odd parity for the data present on DO-7
and D9-16 thereafter. If the user elects not to program the FIFO,
the parity function is disabled. Flag operation and parity are described in greater detail in subsequent sections.
Flag Operation
The CY7C4....?~ provides three status pins when not cascaded. The
three pins, ElF, PAFE, and HP, allow decoding of six FIFO states
(Table 1). PAFE is not available when the CY7C45X is cascaded
for depth expansion. All flags are synchronous, meaning that the
change of states is relative to one of the clocks (CKR or CKW, as
appropriate),[46] The Empty and Almost Empty flag states are exclusively updated by each rising edge ofthe read clock (CKR). For
example, when the FIFO contains 1 word, the next read (rising
edge of CKR while ENR=LOW) causes the flag pins to output a
state that represents Empty. The Half Full, Almost Full, and Full
flag states are updated exclusively by the write clock
Table 1. Flag 'frutb Table[47]
ElF
HF
0
1
PAFE
0
0
1
1
1
1
1
1
U
0
0
0
0
U
1
1
State
Empty
Almost Empty
Less than or Equal to
Half Full
Greater than Half Full
Almost Full
Full
7C455
Words in FIFO
7C457
Words in FIFO
7C456
Words in FIFO
0
I.P
0
I.P
u
P + 1.256
P + 1.512
P+l.1024
257.511 - P
512 P.511
512
513.1023 - P
1024 P .1023
1024
1025 • 2047 - P
2U41l P.2047
2048
I.P
Notes:
45. CKW will write Do _ 9 into the programming register. CKR will read
Do - 9 during a programming register read.
46. The synchronous architecture guarantees the flags valid for approxi-
47. P is the decimal value of the binary numberrepresented by Do _ 7 for
the CY7C455, Do _ 8 for the CY7C456, and Do _ 9 for the CY7C457.
P = 0 signifies that the Almost Empty state = Empty state.
mately one cycle of the clock they are synchronized to.
5-175
E
CY7C455
CY7C456
CY7C457
Flag Operation (continued)
(CKW). For example, if the CY7C457 contains 2,047 words (2,048
words indicate Full for the CY7C457), the next write (rising edge
of CKW while ENW = LOW) causes the flag pins to output a state
that is decoded as Full.
Since the flags denoting emptiness (Empty, Almost Empty) are
only updated by CKR and the flags signifying fullness (Half Full,
Almost Full, Full) are exclusively updated by CKW, careful attention must be given to the flag operation. The user must be aware
that if a boundary (Empty, Almost Empty, Half Full, Almost Full,
or Full) is crossed due to an operation from a clock that the flag is
not synchronized to (i.e., CKW does not affect Empty or Almost
Empty), a flag update cycle is necessary to represent the FIFO's
new state. The signal to which a flag is not synchronized will be referred to as the opposite clock (CKW is opposite clock for Empty
and Almost Empty flags; CKR is the opposite clock for Half Full,
Almost Full, and Full flags). Until a proper flag update cycle is executed, the synchronous flags will not show the new state of the
FIFO.
When updating flags, the FIFO must make a decision as to whether
or not the opposite clock was recognized when a clock updates the
flag. For example (when updating the Empty flag), if a write occurs
at least tSKEWI after a read, the write is guaranteed not to be included when CKR updates the flag. If a write occurs at least
tSKEW2 before a read, the write is guaranteed to be included when
CKR updates flag. If a write occurs within tSKEWI after or tSKEW2
before CKR, then the decision of whether or not to include the
write when the flag is updated by CKR is arbitrary.
The update cycle for non-boundary flags (Almost Empty, Half
Full, Almost Full) is different from that used to update the boundary flags (Empty, Full). Both operations are described below.
Boundary and Non-Boundary Flags
Boundary Flags (Empty)
The Empty flag is synchronized to the CKR signal (i.e., the Empty
flag can only be updated by a clock pulse on the CKR pin). An
empty FIFO that is written to will be described with an Empty flag
state until a rising edge is presented to the CKR pin. When making
the transition from Empty to Almost Empty (or Empty to Less
than or Equal to Half Full), a clock cycle on CKR is necessary to
update the flags to the current state. In such a state (flags showing
Empty even though data has been written to the FIFO), two read
clock cycles are required to read data out of the FIFO. The first
read serves only to update the flags to the Almost Empty or Less
than or Equal to Half Full state, while the second read outputs the
data. This first read cycle is known as the latent or flag update cycle
because it does not affect the data in the FIFO or the count (number of words in FIFO). It sim~easserts the Empty flag. The flag
is updated regardless of the ENR state. Therefore, the update occurs even when ENR is deasserted (HIGH), so that a valid read is
not necessary to update the flags to correctly describe the FIFO. In
this example, the write must occur at least tSKEW2 before the flag
update cycle in order for the FIFO to guarantee that the write will
be included in the count when CKR updates the flags. When a freerunning clock is connected to CKR, the flag is updated each cycle.
Table 2 shows an example of a sequence of operations that update
the Empty flag.
to Almost Full (or Full to Greater Than Half Full), a clock cycle on
CKW is necessary to update the flags to the current state. In such a
state (flags showing Full even through data has been read from the
FIFO), two write cycles are required to write data into the FIFO.
The first write serves only to update the flags to the Almost Full or
Greater Than Half Full state, while the second write inputs the
data. This first write cycle is known as the latent or flag update cycle
because it does not affect the data in the FIFO or the count (number of words in the FIFO). It simply deasserts the Full flag. The flag
is updated regardless of the ENW state. Therefore, the update occurs even when ENW is deasserted (HIGH), so that a valid write is
not necessary to update the flags to correctly describe the FIFO. In
this example, the read must occur at least tSKEW2 before the flag
update cycle in order for the FIFO to guarantee that the read will
be included in the count when CKW updates the flags. When a
free-running clock is connected to CKW, the flag updates each
cycle. Full flag operation is similar to the Empty flag operation described in Table 2.
Non-Boundary Flags (Almost Empty, Half Full, Almost Full)
The CY7C45Xfeatures programmable Almost Empty and Almost
Full flags. Each flag can be programmed a specific distance from
the corresponding boundary flags (Empty or Full). The flags can be
programmed to be activated at the Empty or Full boundary, or at
any distance from the Empty/Full boundary. When the FIFO contains the number of words or fewer for which the flags have been
programmed, the PAFE flag will be asserted signifying that the
FIFO is Almost Empty. When the FIFO is within that same number of empty locations from being Full, the PAFE will also be asserted signifying that the FIFO is Almost Full. The HF flag is decoded to distinguish the states.
The default distance from where PAFE becomes active to the
boundary (Empty, Full) is 16words/locations. The Almost Full and
Almost Empty flags can be programmed so that they are only active at Full and Empty boundaries. However, the operation will remain consistent with the non-boundary flag operation that is discussed below.
Almost Empty is only updated by CKR while Half Full and Almost
Full are updated by CKW Non-boundary flags employ flag update
cycles similar to the boundary flag latent cycles in order to update
the FIFO status. For example, if the FIFO just reaches the Greater
than Half Full state, and then two words are read from the FIFO,
a write clock (CKW) will be required to update the flags to the Less
than Half Full state. However, unlike the boundary flag latent
cycle, the state of the enable pin (ENW in this case) affects the operation. Therefore, set-up and hold times for the enable pins must
be met (tSEN and tHEN)' If the enable pin is active during th~
update cycle, the count and data are updated in addition to P.
and HE If the enable pin is not asserted during the flag update
cycle, only the flags are updated. Tables 3 show an example of a sequence of operations that update the Almost Empty and Almost
Full flags.
The CY7C45X also features even or odd parity checking and generation. DIS _ 17 are used during a program write to describe the
parity option desired. Table 4 summarizes programmable parity
options. If the user elects not to program the device, then parity is
disabled. Parity information is provided on two multi-mode output
pins (QglPGliPEI and Q17/PG2/PE2). The three possible modes
are described in the following paragraphs.
Boundary Flags (Full)
The Full flag is synchronized to the CKW signal (i.e., the Full flag
can only be updated by a clock pulse on the CKW pin). Afull FIFO
that is read will be described with a Full flag until a rising edge is
presented to the CKW pin. When making the transition from Full
5-176
CY7C455
CY7C456
CY7C457
Thble 2. Empty Flag (Boundary Flag) Operation Example
Status Before Operation
Current
Number
State of
of Words
FIFO
ElF AFE HF in FIFO
Empty
0
0
1
0
Empty
0
0
1
1
Empty
0
0
1
2
AE
1
0
1
2
AE
1
0
1
1
Empty
0
0
1
0
Empty
1
0
1
1
AE
1
0
1
1
Status After Operation
Operation
Write
(ENW = 0)
Write
(ENW=O)
Read
(ENR = X)
Read
(ENR = 0)
Read
(ENR=O)
Write
(ENR = 0)
Read
(ENR = X)
Read
(ENR = 0)
ElF
AFE
0
0
HF
1
Number
of words
in FIFO
1
Empty
0
0
1
2
Write
AE
1
0
1
2
Flag Update
AE
1
0
1
1
Read
Empty
0
0
1
0
Empty
0
0
1
1
Read (transition from A1most Empty to Empty)
Write
AE
1
0
1
1
Flag Update
Empty
0
0
1
0
Read (transitionfromAImost Empty to Empty)
Next State
of FIFO
Empty
Programmable Parity
Parity Disabled (QslQ17 mode)
When parity is disabled (or the user does not program parity option) the FIFO stores all 18 bits present on Do _ 17 inputs internally
and will output all 18 bits on 00 - 17.
Parity Generate (PG mode)
This mode is used to generate either even or odd parity (as programmed) from Do _ 7 and D9 _ 16. Dg and D17 inputs are ignored.
The parity bits are stored internally as Dg and D17, and during a
subsequent read will be available on the PG 1 and PG2 pins along
with the data words from which the parity was generated (00 - 7
and 09 _ 16). For example, if parity generate is set to ODD and the
Do _ 7 inputs have an EVEN number of Is, PG1 will be HIGH.
Parity Check (PE mode)
If the FIFO is programmed for parity checking, it will compare the
parity of Do _ g and D9 _ 17 with the program register. For example, Dg and D17 will be set according to the result of the parity
check on each word. When these words are later read, PEl and
PE2 will reflect the result of the parity check. If a parity error occurs in Do _ g, DB will be set LOW internally. When this word is
later read, PEl will be LOW.
Width Expansion Modes
Duringwidthexpansion all flags (programmable and nonprogrammabie) are available. These FIFOs can be expanded in width to
provide word width greater than 18 in increments of 18. During
width expansion mode all control line inputs are common. When
the FIFO is being read near the Empty (Full) boundary, it is important to note that both sets of flags should be checked to see if they
have been updated to the Not Empty (Not Full) condition to insure
that the next read (write) will perform the same operation on all
devices.
Checking all sets of flags is critical so that data is not read from the
FIFOs "staggered" by one clock cycle. This situation could occur
when the first write to an empty FIFO and a read are very close together. If the read occurs less than tSKEW2 after the first write to
two width-expanded devices, A and B, device A may go Almost
Comments
Write
Empty (read recognized as flag update ) while device B stays Empty
(read ignored). This occurs because a read can be either recognized or ignored if it occurs within tSKEW2 of a write. The next read
cycle outputs the first half of the first word on device A while device
B updates its flags to Almost Empty. Subsequent reads will continue to output "staggered" data assuming more data has been
written to FIFOs.
Depth Expansion Mode
The CY7C45X can operate up to 50 MHz when cascaded. Depth
expansion is accomplished by connecting expansion out (~ of
the first device to expansion in (XI) of the next device, with XO of
the last device connected to XI of the first device. The first device
has its first load pin (FL) tied to V ss while all other devices must
have this pin tied to Vee. The first device will be the first to be write
and read enabled after a master reset.
Proper operation also requires that all cascaded devices have common CKW, CKR, ENW, ENR, Do - 17, Qo _ 17, and MR pins.
When cascaded, one device at a time will be read enabled so as to
avoid bus contention. By asserting XO when appropriate, the currently enabled FIFO alerts the next FIFO that it should be enabled. The next rising edge on CKR puts 00 -17 outputs of the first
device into a high-impedance state. This occurs regardless of the
state ofENR or the next FIFO's Empty flag. Therefore, ifthe next
FIFO is empty or undergoing a latent cycle, the 00 _ 17 bus will be
in a high-impedance state until the next device receives its first
read, which brings its data to the 00 - 17 bus.
Program Write/Read of Cascaded Devices
Programming of cascaded FIFOs is the same as for a single device.
Because the controls of the FIFOs are in parallel when cascaded,
they all get programmed the same. During program mode, only
parity is programmed since Almost Full and Almost Empty flags
are not available when CY7C45X is cascaded. Only the "first device" (FIFO with FL= LOW) will output its program register contents on 00 _ 17 during a program read. 00 _ 17 of all other devices
will remain in a high-impedance state to avoid bus contention.
5-177
CY7C455
CY7C456
CY7C457
CKW
CKR
Ii
mill
"
v..
-,...
DATA IN
°0-17
XI
Do -17
00-17
CKR
CKW
CY7C455,6,7
MIl
mil
HI'
UE
ElF
EI'IW
1
I'AFEJl«l
MIl
"
I I I
I I
I'[
----
f--<
J
Vss
00 -
00 -17
17
CKW
CKR
~Y7C455.6Ek
L r----- MIl
HI'
ElF
~ OE
I'[
IWE/l«l
00- 17
V
.....:::
II
xr
V
"DATA 0 UT
~
il ~
l'O[[
M
Vee
J
I
c455-25
Figure 1. Depth Expansion with CY7C4SX
Table 3. Almost Empty Flag (Non-Boundary Flag) Operation Example[48)
Status After Operation
Status Before Operation
Number
~nmoe.r
Current State
of Words
of words
Next State
of FIFO
'ElF AFE HF in FIFO Operation of FIFO ElF PAFE HF in FIFO
AE
1
0
1
32
1
1
33
Write
AE
0
(ENW = 0)
AE
1
0
1
Write
1
34
1
33
AE
0
(ENW = 0)
33
AE
0
1
Read
1
1
1
1
34
60.00
Z
(j)
40.00
40.00
W
30.00
5
20.00
a?
f-
a.
5
a
/'
/
45.00
'"
10.00
0.00
0.00
I"...
Vee; 5.0V
TA; 25°C
a:
a:
"- ~
5a.
5a
"\
I
1.00
()
;0::
2.00
3.00
4.00
OUTPUT VOLTAGE (V)
20.00
/
/
/
i""'"
Vee; 5.0V
TA ; 25°C
V
0.00
0.00
I
1.00
2.00
3.00
OUTPUT VOLTAGE (V)
5-179
Ii
60.00
FREQUENCY (MHz)
f-
CJ)
:::>
0.60
30.00
V
/'
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
:i!
a
0.70
AMBIENT TEMPERATURE (OC)
60.00
a:
l
Vee; 5.0V
1.00 I-- TA; 25°C
VIN; 3.0V
0.90
..: 0.80
:2:
a:
VIN; 3.0V
Vee; 5.0V
f ; 71 MHz
!~
N
0.80 '-------'------'------'
-55.00
5.00
125.00
65.00
SUPPLY VOLTAGE (V)
5.00f-~---
0.00 "---------'-------'
1000.00
0.00
500.00
125.00
1.20 , - - - , - - - - - - - , - - - - - ,
15
5.00 f-------oifiC-------j
~ 10.00 r------:;-F--+--------j
o
Vee;5.0V
0.60
-55.00
6.00
r------t---:7'~---1
W
SUPPLY VOLTAGE (V)
15Z
.$
L..---
a
Z 0.90
~
20.00
~ 1.00
a
15
.,.s,
.$ 1.40
o
N
~ 1.00
25.00 , - - - - - - , - - - - - - - - ,
1.60
g
1.10
w
:2:
TYPICAL tA CHANGE vs.
OUTPUT LOADING
NORMALIZED tA vs. AMBIENT
TEMPERATURE
NORMAUZED tA vs. SUPPLY
VOLTAGE
4.00
75.00
CY7C455
CY7C456
CY7C457
£_-~
'CYPRESS
Ordering Information
Speed
(ns)
14
20
30
Speed
(ns)
14
20
30
Speed
(ns)
14
20
30
Ordering Code
Package
Name
Package
1Ype
Operating
Range
CY7C455-14JC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C455-14NC
N52
52-Pin Plastic Quad Fiatpack
CY7C455 -1411
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C455-20JC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C455 - 20NC
N52
52-Pin Plastic Quad Fiatpack
CY7C455 - 2011
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C455-30JC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C455-30NC
N52
52-Pin Plastic Quad Fiatpack
CY7C455 - 3011
J69
52-Lead Plastic Leaded Chip Carrier Industrial
Ordering Code
Package
Name
Package
1Ype
Operating
Range
CY7C456-14JC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C456-14NC
N52
52-Pin Plastic Quad Flatpack
CY7C456-14JI
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C456-20JC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C456-20NC
N52
52-Pin Plastic Quad Flatpack
CY7C456-20JI
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C456-3OJC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C456-30NC
N52
52-Pin Plastic Quad Fiatpack
CY7C456-301l
J69
52-Lead Plastic Leaded Chip Carrier Industrial
Ordering Code
Package
Name
Package
1Ype
Operating
Range
CY7C457-14JC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C457-14NC
N52
52-Pin Plastic Quad Flatpack
CY7C457 -14JI
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C457-20JC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C457 - 20NC
N52
52-Pin Plastic Quad Fiatpack
CY7C457 - 20JI
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C457-3OJC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C457 - 30NC
N52
52-Pin Plastic Quad Flatpack
CY7C457 - 3011
J69
52-Lead Plastic Leaded Chip Carrier Industrial
Document #: 38-00211-C
5-180
CY7C460
CY7C462
CY7C464
Cascadable 8K X 9 FIFO
Cascadable 16Kx 9 FIFO
Cascadable 32K X 9 FIFO
Features
Functional Description
•
•
•
•
•
The CY7C460, CY7C462, and CY7C464
are respectively, 8K, 16K, and 32K words
by 9-bit wide first-in-first-out (FIFO) memories. Each FIFO memory is organized
such that the data is read in the same sequential order that it was written. Full and
Empty flags are provided to prevent overrun and underrun. Three additional pins
are also provided to facilitate unlimited expansion in width, depth, or both. The
depth expansion technique steers the control signals from one device to another in
parallel, thus eliminating the serial addition of propagation delays, so that
throughput is not reduced. Data is steered
in a similar manner.
The read and write operations may be
asynchronous; each can occur at a rate of
33.3 MHz. The write operation occurs
when the write (Wl signal is LOW Read
occurs when read (R) goes LOW The nine
•
•
•
•
•
•
•
•
•
•
8K x 9 FIFO (CY7C460)
16K x 9 FIFO (CY76C462)
32K x 9 FIFO (CY7C464)
Asynchronous read/write
High-speed 33.3-MHz read/write
independeut of depth/width
Low operating power
- Icc = 70 rnA (max.)
Half Full flag in standalone
Empty and Full flags
Retrausmit in standalone
Expandable in width and depth
5V ± 10% supply
PLCC, LCC, and 600-mil DIP
packaging
TTL compatible
Three-state outputs
Pin compatible and functionally
equivalent to IDT7205, IDT7206
data outputs go to the high-impedance
state when R is HIGH.
A Half Full (HF) output flag is provided
that is valid in the standalone (single device) and width expansion configurations.
In the depth expansion configuration, this
pin provides the expansion out (XO) information that is used to tell the next FIFO
that it will be activated.
In the standalone and width expansion
configurations, a LOW on the retransmit
(RT) input causes the FIFOs to retransmit
the data. Read enable (R) and write enable
(W) must both be HIGH during a retransmit cycle, and then R is used to access the
data.
The CY7C460, CY7C462, and CY7C464
are fabricated using an advanced 0.8micron N-well CMOS technology. Input
ESD protection is greater than 2000V and
latch-up is prevented by careful layout,
guard rings, and a substrate bias generator.
I
Logic Block Diagram
Pin Configurations
DATA INPUTS
(Do-Ds)
PLCC/LCC
ThpView
om dDIs:
~ >8 o" 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Commercial
Industrial
Military[l]
Ambient
Temperature
O°Cto + 70°C
5V ± 10%
-40°C to +85°C
5V ± 10%
-55°C to + 125°C
5V ± 10%
Vee
Electrical Characteristics Over the Operating RangelZ]
7C460-15
7C462-15
7C464-15
Parameter
VOH
VOL
VIH
VIL
IIX
loz
Icc
ISB!
ISBZ
los
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
Power-Down Current
Output Short
Circuit Currentf3]
Thst Conditions
Min.
Vee = Min., IOH = -2.0 rnA
Vee - Min., IOL - 8.0 rnA
Com'l
Mil/Ind
2.4
GND~VI~Vce
RL VIH,GND~ Vo~ Vee
Com'l
Vee = Max.,
lOUT = OmA
Mil/Ind
Com'l
MilJlnd
Com'l
All Inputs
Vee- 0.2V
Milllnd
Vee - Max., VOUT - GND
All Inputs =
VIHMin.
Max.
7C460-20
7C462-20
7C464-20
Min.
Max.
0.4
2.2
-10
-10
0.8
+10
+10
110
25
30
20
-90
Max.
Unit
0.4
V
V
V
2.2
2.2
2.2
0.8
+10
+10
105
Min.
2.4
2.4
0.4
-10
-10
7C460-25
7C462-25
7C464-25
25
-90
-10
-10
0.8
+10
+10
90
95
25
30
20
25
-90
V
!JA
!JA
rnA
rnA
rnA
rnA
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
information.
3.
5-182
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 1 second.
CY7C460
CY7C462
CY7C464
~-,,~
'CYPRESS
Electrical Characteristics Over the Operating Range (continued)[2J
7C460-40
7C462-40
7C464-40
Parameter
Description
Test Conditions
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VIL
IIX
Ioz
Icc
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
GNDsVIsVee
R~ VIH,GNDs Vos Vee
Vee = Max., lOUT = 0 rnA
ISBI
Standby Current
All Inputs =VIH Min.
ISB2
Power-Down Current
All Inputs Vee - 0.2V
los
Output Short
Circuit Current[3]
Vee - Max., VOUT - GND
Min.
Max.
2.4
Vee - Min., IOH = - 2.0 rnA
Vee - Min., IOL - 8.0 rnA
7C460-65
7C462-65
7C464-65
Min.
0.4
Com' I
Mil/lnd
2.2
2.2
Corn'l
Mil/Ind
Corn'l
Mil/lnd
Corn'l
Mil/lnd
Unit
0.4
V
V
V
2.2
2.2
0.8
-10
-10
Max.
2.4
+10
+10
-10
-10
70
75
25
30
20
25
-90
0.8
V
+10
+10
flA
f.lA
rnA
70
25
30
20
25
-90
rnA
rnA
rnA
Capacitance[4]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
Max.
TA = 25°C, f = 1 MHz,
10
Vee = 4.5V
12
Unit
pF
pF
AC Test Loads and Waveforms
'1" 0""':: 'P'II'1"'
0""':: "''' II
INCLUDING _
JIG AND SCOPE
(a)
Equivalent to:
333Q
_
-
C460-4
333Q
INCLUDING _
JIG AND SCOPE
_
-
C460-5
(b)
THEVENIN EQUIVALENT
200Q
_____oo2V
OUTPUTGo-----Ny~·~
Notes:
4. Tested initially and after any design or process changes that may affect
these parameters.
5-183
ALL INPUT PULSES
'.ov~
GND
.$.5 ns - -
10~~%
I+-
~~O%
--I C:::s
C460·6
Ii
CY7C460
CY7C462
CY7C464
Switching Characteristics Over the Operating Rangd2,5]
7C460-15
7C462-15
7C464-15
Parameter
tRe
tA
tRR
tpR
tLZR
tDVR lbJ
tHZR l6J
twc
tpw
tHWZ
tWR
tSD
tHD
tMRSC
tpMR
tRMR
tRPW
twpw
tRTC
tpRT
tRTR
tEFL
tHFH
tFFH
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
tRAE
tRPE
tWAF
tWPF
tXOL
tXOH
Description
Min.
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
Read LOW to Low Z
Data Valid After Read HIGH
Read HIGH to High Z
Write Cycle Time
Write Pulse Width
Write HIGH to Low Z
Write Recovery Time
Data Set-Up Time
Data Hold Time
MR Cycle Time
MR Pulse Width
MR Recovery Time
Read HIGH to MR HIGH
Write HIGH to MR HIGH
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
MRtoEFLOW
MRtoHFHIGH
MR to FFHIGH
Read LOW to EF LOW
Read HIGH to FF HIGH
Write HIGH to EF HIGH
Write LOW to FF LOW
Write LOW to HF LOW
Read HIGH to HF HIGH
Effective Read from Write HIGH
Effective Read Pulse Width
After EF HIGH
Effective Write from Read HIGH
Effective Write Pulse
Width After FF HIGH
Expansion Out LOW
Delay from Clock
Expansion Out HIGH
Delay from Clock
30
7C460-20
7C462-20
7C464-20
Max.
Min.
Max.
30
15
7C460-25
7C462-25
7C464-25
Min.
20
15
15
3
3
15
25
15
30
20
5
10
12
0
30
20
10
20
20
30
20
10
25
25
25
15
15
15
15
15
15
15
20
15
20
15
65
3
3
40
80
80
80
60
60
60
60
60
60
60
65
40
40
25
25
80
65
5
15
30
10
80
65
15
65
65
80
65
15
50
50
50
40
40
40
40
50
50
40
25
Max.
65
25
35
35
35
25
25
25
25
35
35
25
25
Min.
80
50
40
5
10
20
0
50
40
10
40
40
50
40
10
10
7C460-65
7C462-65
7C464-65
40
18
25
20
Max.
10
40
3
3
35
25
5
10
15
0
35
25
10
25
25
35
30
30
30
20
20
20
20
30
30
20
25
25
Min.
50
10
25
3
3
10
20
3
3
30
15
5
15
11
0
30
15
15
15
15
30
15
15
Max.
35
7C460-40
7C462-40
7C464-40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
60
65
ns
ns
15
20
25
40
65
ns
30
35
35
50
65
ns
Notes:
S. Thst conditions assume signal transmission time of S ns or less, timing
reference levels of l.SV and output loading of the specified ImjIoH
and 30-pF load capacitance, as in part (a) of AC Test Load, unless
otbetwise specified.
6.
5-184
tHZR and tDVR use capacitance loading as in part (b) of AC Thst Load.
CY7C460
CY7C462
CY7C464
===-.,;;,~
; CYPRESS
Switching Waveforms[7]
Asynchronous Read and Write
~----
QO-Q8------------~
W
~--------tP-w-------twc
r,:'"
Do-D8
--------------1<1<.-
I '""~
Master Reset
'~r,:," l."~
../IlI-------------I<1<..-
DATA VALID
DATA VALlD_
.,)IlI--------
C460-7
tMRscl9]
tpMR
Fl, \fi18]
-tEFL
~
twpw I+- tRMR _
I
-tHFH
.X7f
HF
~
-tFFH
XXXXXXXXXXXXXXX?
C460-8
Half Full Flag
HALF FULL
HALF FULL +1
/
HALF FUL L
-
tRHF
-
+-twHFj
r-
l'
C460-9
Last Write to First Read Full Flag
LAST WRITE
R--+-------h
ADDITIONAL
READS
FIRST READ
FIRST WRITE
W-~r_'\,
~-+--..I
C460-10
Notes;
7.
A HIGH-to-LOW transition of either the write or read strobe causes
a HIGH-to-LOW transition of the responding flag. Correspondingly,
a LOW-to-HIGH strobe transition causes a LOW-to-HIGH flag transition.
8.
9.
5-185
Wand R = VIR around the rising edge of MR.
tMRSC = tpMR + tRMR·
CY7C460
CY7C462
CY7C464
Switching Waveforms
Last READ to First WRITE Empty Flag
LAST READ
w--~----------~
ADDITIONAL
WRITES
FIRST WRITE
FIRST READ
EF--+-+--,I
DATA OUT
--+--(
0460-11
Retransmit[lO, 11]
1 + - - - - - - tRTC
-----~.,j
tpRT----t
~-----+---------------------
FI..IRT -+---""'"'\1
C460-12
Fnll Flag and Write Data Flow-Through Mode
~_-+
_______
~_-J'
DATA IN
DATA OUT
I.-~-:::L
~--D-A-I-A-V-A-L-ID~~~-------------------------------------C460-13
Notes:
10. tRfC = tpRT + tRTR-
11. EF,HFandFFmaychangestateduringretransmit as a result of the 0 ffset ofthe read and write pointers, but flags will be valid at tRfC, except
for the CY7C46x- 20 (Military), whose flags will be valid after tRfC +
IOns_
5-186
CY7C460
CY7C462
CY7C464
-~
=,CYPRESS
Switching Waveforms (continued)
Empty Flag and Read Data Flow-Through Mode
Expansion Timing Diagrams
w ___---..
X0 1(Xl2)[12]
--------------~~:::j-
DATA VALID
C460-15
QO-QB---i----~
C450-16
Note:
12_ E~nsion out of device 1 (XOj) is connected to expansion in of device
2 (X1z)-
5-187
-=-,
='
CY7C460
CY7C462
CY7C464
.. ~
CYPRESS
Architecture
Retransmit
Resetting the FIFO
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The retransmit (RT) input is
active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes
equal-to-or-less-than the depth of the FIFO have 0:curred since
the last MR cycle. A LOW pulse on RT resets th~_mter~ read
pointer to the first physical location of the FI~
~,CYPRESS
lxo
w
1
9
D
I 1
/
R
EI'
IT
9~
-71/
T
I
CY7C460
CY7C462
CY7C464
l
9
/
IT
r--
~
Vc
XI
xo
~
=
EI'
IT
9.1\.
7'
-V
EMPlY
CY7C460
CY7C462
CY7C464
IT
I---------
I--'
XI
xo
'-
'---
IT
9, I\.
AS
7'
,1/
.
'-
EF
CY7C460
CY7C462
CY7C464
IT
r
'::'
l
* FIRST DEVICE
C460-17
Figure 1. Depth Expansion
5-189
CY7C460
CY7C462
CY7C464
~ -.,~
'CYPRESS
1Ypical AC and DC Characteristics
NORMALIZED tA vs. AMBIENT
TEMPERATURE
NORMALIZED tA vs. SUPPLY
VOLTAGE
;r.
0
1.20
1.60
1.10
o
~ 1.20
::;
w
N
::;
..: 1.00
::;;
a:
0
z 0.90
TYPICAL tA CHANGE vs.
OUTPUT LOADING
20.00,-----.,--------,
;r. 1.40
-
0.80
4.00
(i)15.00 I-----+----c;;~
-S
..:
~ 1.00
TA = 25'C
4.50
I
I
5.00
5.50
-
:;10.00 1-----:7"'f---------i
!:J
w
o
z 0.80 I- Vee
I
0.60
-55.00
6.00
1.40 , - - - , - - , - - - - - , - - - - ,
5.00
65.00
0.00 < - - - - - " - - - - - - - - - "
0.00
500.00
1000.00
125.00
AMBIENT TEMPERATURE (DC)
CAPACITANCE (pF)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. FREQUENCY
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
o 5.00 I - f - - - '
= 5.0V
1.20
1.10
I
Jl
1.20 I-----+--+---I:~--I
.9 1.10
1.00 I---+--~/(C----+----j
::;
o
w
N
~
u 1.00 .9
u
0
..:
::;;
::;;
a:
~ 0.80I-JII""-t--z
0
0
z
0.60 ~-~--~-~-~
4.00
4.50
5.00
5.50
6.00
-S
~
40.00
()
30.00
w
()
a:
::::>
20.00
o
~
"~
::::>
z
65.00
10.00
0.00
0.00
125.00
AMBIENT TEMPERATURE (DC)
Vee = 5.0V
TA = 25°C
2.00
0.60
15.00
20.00
25.00
~
80.001---+--.F'---+---I
::::>
60.00 I---+--f-+---+---I
0.::
Z
40.00
()
ii5
~
3.00
"-
~
o
4.00
OUTPUT VOLTAGE (V)
I--~--+---+---I
Vee = 5.0V
20.00 hF--+----+ TA = 25°C
0.00 ~_-L_---"_ _--L_---"
0.00
1.00
2.00
3.00
4.00
OUTPUT VOLTAGE (V)
5-190
30.00
FREQUENCY (MHz)
ill
a:
a:
.. v
II"
1100.00,---,--,-----,---,
""""'\
I
1.00
0.70
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
'" "- ""-
::::>
o
5.00
50.00
~
a:
(Jl
0
I
/
/
a:
I
0.80
-55.00
0.90
..:
::;; 0.80
VIN = 3.0V
0.90 r- TA = 25°C
f = 33 MHz
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
z
::::>
.....
1.00
SUPPLY VOLTAGE (V)
<'
w
N
::;
W
N
Vee = 5.0V
TA = 25°C
VIN = 3.0V
35.00
CY7C460
CY7C462
CY7C464
= -.,::4:
~;CYPRESS
Ordering Infonnation
Speed
(ns)
15
Ordering Code
CY7C460-15JC
CY7C460-15PC
Package
Name
Package lYpe
Operating
Range
J65
P15
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Commercial
CY7C460-15JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
20
CY7C460-20DMB
CY7C460- 20LMB
D43
L55
28-Lead (600-Mil) Sidebraze CerDIP
32-Pin Rectangular Leadless Chip Carrier
Military
25
CY7C460-25JC
CY7C460-25PC
J65
PIS
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Commercial
CY7C460-25JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C460-25DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C460-25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C460-40JC
CY7C460-40PC
J65
PIS
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Commercial
CY7C460-40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C460-40DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C460-40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C460-65JC
CY7C460-65PC
J65
PIS
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Commercial
CY7C460-65JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
40
65
Speed
(ns)
15
20
25
40
65
Ordering Code
Package
Name
Package lYpe
Operating
Range
CY7C462-15JC
J65
CY7C462-15PC
P15
28-Lead (600-Mil) Molded DIP
CY7C462-15JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C462-20DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C462-20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C462-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C462-25PC
P15
28-Lead (600-Mil) Molded DIP
CY7C462-25JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C462-25DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C462-25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C462-40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C462-40PC
P15
28-Lead (600-Mil) Molded DIP
CY7C462-40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C462-40DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C462-40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C462-65JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C462-65PC
P15
28-Lead (600-Mil) Molded DIP
CY7C462-65JI
J65
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
5-191
Commercial
Commercial
Commercial
Commercial
Industrial
I
CY7C460
CY7C462
CY7C464
Ordering Information (continued)
Speed
(ns)
15
20
25
40
65
Ordering Code
Package
Name
Package 'JYpe
CY7C464-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C464-15PC
PI5
28-Lead (600-Mil) Molded DIP
Operating
Range
Commercial
CY7C464-I5JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C464-20DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C464-20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C464-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C464-25PC
PI5
28-Lead (600-Mil) Molded DIP
Commercial
CY7C464-25JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C464-25DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C464-25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C464-40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C464-40PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C464-40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C464-40DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C464-40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C464-65JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C464-65PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C464-65JI
J65
32-Lead Plastic Leaded Chip Carrier
5-192
Commercial
Commercial
Industrial
CY7C460
CY7C462
CY7C464
rcYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIH
VILMax.
IIX
Icc
ISBl
ISBZ
los
loz
Switching Characteristics
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Parameter
Subgroups
9,10,11
9,10,11
tA
9, 10, 11
tRR
9,10,11
tpR
9,10,11
tLZR
9,10,11
tDVR
9,10,11
tHZR
9,10,11
twc
9,10,11
tpw
9,10,11
tHwz
9,10,11
tWR
9,10,11
tSD
9,10,11
tHD
9,10,11
tMRSC
9,10,11
tpMR
9,10,11
tRMR
9,10,11
tRPW
9,10,11
twpw
9,10,11
tRTC
9,10,11
tpRT
9,10,11
tRTR
9,10,11
tEFL
9,10,11
tHFH
9,10,11
tFFH
9,10,11
tREF
9,10,11
tRFF
9,10,11
tWEF
9,10,11
tWFF
9,10,11
tWHF
9,10,11
tRHF
9,10,11
tRAE
9,10,11
tRPE
9,10,11
tWAF
9,10,11
tWPF
9,10,11
tXOL
9,10,11
tXOH
Document #: 38-00141-0
tRC
5-193
I
CY7C470
CY7C472
CY7C474
8K X 9 FIFO, 16K X 9 FIFO,
32K X 9 FIFO with Programmable Flags
Features
Functional Description
• SKx9, 16K x 9, and32Kx9 FIFO
buffer memory
• Asynchronous read/write
• High-speed 33.3-MHz read/write
The CYC47X FIFO series consists of
high-speed, low-power, first-in first-out
(FIFO) memories with programmable
flags and retransmit mark. The CY7C470,
CY7C472, and CY7C474 are 8K, 16K,
and 32K words by 9 bits wide, respectively. They are offered in 600-mil DIP,
PLCC, and LCC packages. Each FIFO
memory is organized such that the data is
read in the same sequential order that it
was written. Three status pins-Emptyl
Full (Et), Programmable Almost FulV
Empty PAPE), and Half Full (HF)-are
provided to the user. These pins are decoded to determine one of six states:
Empty, Almost Empty, Less than Half
Full, Greater than Half Full, Almost Full,
and Full.
The read and write operations may be
asynchronous; each can occur at a rate of
33.3 MHz. The write operation occurs
independentofdeptlV~dtb
• Low operating power
- Icc (max.) = 70 rnA
• Programmable Almost Foll/Empty
flag
• Empty, Almost Empty, Half foil,
Almost foil, and foil status flags
• Programmable retransmit
• Expandable in ~dtb
• 5V:!: 10% supply
• TTL compatible
• Three-state outputs
• Proprietary O.S-micron CMOS
technology
Logic Block Diagram
Pin Configurations
DATAINPlJTS
(Do-Del
DIP
PLCC/LCC
lbpView
at') oCDI?:
D.
4
5
3
2
Do
MJ\RR
PAl'E
00
R
0,
NC
RT
02
IiiWlR
lbpView
~ >8 CJ~ oln
111
L.
0,
W
whenthewrite(W) signal goes LOW: Read
occurs when read (R) goes LOW: The nine
data outputs go into a high-impedance
state when R is HIGH.
The user can store the value of the read
pointer for retransmit by using the MARK
pin. A LOW on the retransmit (RT) input
causes the FIFO to resend data by resetting
the read pointer to the value stored in the
mark pointer.
In the standalone and width expansion
configurations, a LOW on the retransmit
(lIT) input causes the FIFO to resend the
data. With the mark feature, retransmit
can start from any word in the FIFO.
The CYC47X series is fabricated using a
proprietary 0.8-micron N-well CMOS
technology. Input ESD protection is
greater than 2001 V and latch-up is prevented by the use of reliable layout techniques, guard rings, and a substrate bias
generator.
7C470
7C472
7C474
323130
29
28
W
V"
D.
D.
03
D.
27
06
07
NC
26
AT
Do
AT
25
IlR
IlR
AF
02
06
0,
0]
24
Ell'
MJ\RR
l'III'E
23
AF
00
12
22
13
21
14 151617181920
07
0,
~
06
02
06
10
11
r!' c!'
~ ~ 10: 0" c!'
0
ElF'
03
O.
O.
O.
GND
R
70470·2
7C470-3
DATA OlJTPlJTS
(Oo-Oel
7C470-1
5-194
CY7C470
CY7C472
CY7C474
Selection Guide
Frequency (MHz)
Maximum Access Time (ns)
Maximum Operating Current (rnA)
I
I
7C470-15
7C472-15
7C474-15
7C470-20
7C472-20
7C474-20
7C470-25
7C472-25
7C474-25
33.3
15
105
33.3
20
28.5
25
90
95
Commercial
Military/Industrial
110
7C470-40
7C472-40
7C474-40
20
40
70
75
Maximum Ratings
Storage Temperature .................. -65°C to + 150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential ........ -0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5V to + 7.0V
DC Input Voltage ....................... -3.0Vto +7.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Output Current, into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
O°C to +70°C
Range
Commercial
Industrial
Military[l]
Vee
5V ± 10%
-40°C to +85°C
5V ± 10%
-55°C to + 125°C
5V ± 10%
Electrical Characteristics Over the Operating Rangd2]
7C470-15
7C472-15
7C474-15
Parameter
Description
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VIL
IIX
Ioz
lee
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
ISBl
Standby Current
ISB2
los13j
Power-Down Current
Output Short Circuit Current
Test Conditions
Vee - Min., 10H - -2.0 rnA
Vee = Min., 10L = 8.0 rnA
Com'!
Mil/Ind
GNDs VIS Vee
R~ VIH,GNDs Vos Vee
Com'l
Vee = Max.,
lOUT = ornA
Miil/Ind
Com'!
All Inputs =
VIHMin.
Mil/Ind
Com'l
All Inputs =
Vee - O.2V
MiVInd
Vee = Max., VOUT = GND
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3.
5-195
7C470-20
7C472-20
7C474-20
7C470-25
7C472-25
7C474-25
Min. Max. Min. Max. Min. Max.
2.4
2.4
0.4
2.4
0.4
2.2
2.2
2.2
2.2
-10
-10
0.8
+10
+10
105
-10
-10
0.8
+10
+10
110
25
30
20
-90
0.4
25
-90
-10
-10
0.8
+10
+10
90
95
25
30
20
25
-90
Unit
V
V
V
V
f.tA
f.tA
rnA
rnA
rnA
rnA
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second.
I
CY7C470
CY7C472
CY7C474
Electrical Characteristics Over the Operating Rangd2] (continued)
7C470-40
7C472-40
7C474-40
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
Vee - Min., IOH - -2.0 rnA
VOL
Output LOW Voltage
Vee
VIH
Input HIGH Voltage
Input LOW Voltage
IIX
Input Leakage Current
GND.::;. VI'::;' Vee
loz
Output Leakage Current
RLVIH,GND.::;. Vo'::;' Vee
lee
Operating Current
Vee
Standby Current
losL3]
= VIH Min.
All Inputs
Power-Down Current
ISB2
= Max., lOUT = 0 rnA
All Inputs
Output Short Circuit Current
Vee
= V cc -
0.2V
Max.
Unit
0.4
V
2.4
= Min., IOL = 8.0 rnA
VIL
ISB!
Min.
Com'l
2.2
Mil/lnd
2.2
V
V
0.8
V
+10
+10
fAA
fAA
Com'l
70
rnA
Mil/lnd
75
-10
-10
Com'l
25
Mil/lnd
30
Com'l
20
Mil/lnd
25
= Max., VOUT = GND
rnA
rnA
-90
rnA
Capacitance[4]
Parameter
Test Conditions
Description
TA = 25°C, f
Vee = 4.5V
Input Capacitance
Output Capacitance
CIN
COUT
"1
AC Test Loads and Waveforms
o~: "p'II"1~ o",p~~: '" II ~
333Q
INCLUDING _
_
JIG AND SCOPE
(a)
Equivalent to:
7C470·4
333Q
INCLUDING _
JIG AND SCOPE
_
-
= 1 MHz,
Max.
Unit
10
pF
12
pF
ALL INPUT PULSES
'''~
GND~5ns~
10%
90%
Jt::
10%
~5ns
7C47Q-6
7C470-5
(b)
THEVENIN EQUIVALENT
200Q
OUTPUTGo-----Ny~~__--~o2V
Note:
4. Tested initially and after any design or process changes that may affect
these parameters.
5-196
CY7C470
CY7C472
CY7C474
~
rcYPRESS
Switching Characteristics Over the Operating Rangd5, 6]
7C470-15
7C472-15
7C474-15
Description
Parameter
Min.
7C470-20
7C472-20
7C474-20
Max.
Min.
Max.
30
7C470-25
7C472-25
7C474-25
Min.
Max.
Min.
tcy-
Cycle Time
tA
Access Time
tRY
Recovery Time
15
10
10
10
30
15
35
7C470-40
7C472-40
7C474-40
20
Max.
Unit
40
ns
50
25
ns
ns
tpw
Pulse Width
15
20
25
40
ns
tLZR
Read LOW to Low Z
3
3
3
3
ns
tDV(7]
Valid Data from Read HIGH
3
tHZ[7]
Read HIGH to High Z
tHWz
Write HIGH to Low Z
5
5
5
5
ns
tSD
Data Set-Up Time
11
12
15
20
ns
tHD
Data Hold Time
0
tEFD
E/FDelay
15
20
25
40
ns
tEFL
MR to E/FLOW
25
30
35
50
ns
tHFD
HFDeiay
25
30
35
50
ns
tAFED
PAFEDeiay
25
30
35
50
ns
tRAE
Effective Read from
Write HIGH
15
20
25
40
ns
tWAF
Effective Write from
Read HIGH
15
20
25
40
ns
3
15
3
3
0
0
ns
25
18
15
ns
ns
0
Notes:
5.
6.
Thst conditions assume signal transmission time of 5 ns or less, timing
reference levels of 1.5V and output loading of the specified IOl)IOH
and 30-pF load capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
See the last page of this specification for Group A subgroup testing
information.
7.
5-197
tHZR and tDvR use capacitance loading as in part (b) of AC Test Loads.
tHZR transition is measured at +500mV from VOLand -500mV from
V OH. tDvR transition is measured at the 1.5V level. tHWZ and tLZR
transition is measured at :t 100 m V from the steady state.
Ii
CY7C470
CY7C472
CY7C474
Switching Waveforms
Asynchronous Read and Write
R--~
7C470-7
Master Reset (No Write to Programmable Flag Register)
~---------~y-------------~
________~~------tpw----------_,;:~~---------
R,W
7C470·8
Master Reset (Write to Programmable Flag Register) [8, 9]
tCY
~tpw
J
.1
r
tCY
tRV
tRV-
-
W(R)
L
DO-Os
(Oo-Os)
ft.
tpw -- -
~y
tRV
tRV-
-
tHO
VALID
7C470·9
Note:
8. Waveform labels in parentheses pertain to writing the programmable
flag register from the output port (00 - 08).
9. Master Reset (MR) must be pulsed LOW once prior to programming.
5-198
CY7C470
CY7C472
CY7C474
rcYPRESS
Switching Waveforms (continued)
ElF Flag (Last Write to First Read Full Flag)
W
FULL-1
R
Ell'
~
L~i
FULL
FULL-1
/
\
~>roj-
LOW
7C47Q-10
ElF Flag (Last Read to First Write Empty Flag)
R
EMPTY +1
t-i
w
ElF
HF
EMPTY
EMPTY +1
/
\
~>roj-
I
HIGH
7C47Q-ll
Half Full Flag
W
HALF-FULL
HALF-FULL + 1
HALF-FULL
R
FiF
\
~-~i
__rnj7C470-12
5-199
CY7C470
CY7C472
CY7C474
a:::_~
""""'=-'-,CYPRESS
Switching Waveforms (continued)
PAFE Flag (Almost Full)
W
I
t-1___'--_-_~-I--i_
"R
PAFE
LOW
70470·13
PAFE Flag (Almost Empty)
R
W
PAFE
L~1'--__' ---_-_~_~0i_
I
HF----~H~IG~H~-----------------------------------------------------
7C47Q-14
Retransmit[10]
ICV
Icv
W,R
I--.. IRV'" f4-- Ipw-- I- IRV ....
Icv
oo-os
FLAGS[10]
XXXXXXXXX
tA-
II~R
@
DATA VALID
)
FLAGS VALID
70470-15
Notes:
10. The flags may change state during retransmit, but they will be valid a
Icy later, except for the CY7C47X - 20 (Military), whose flags will be
valid after tcy + 10 ns.
5-200
CY7C470
CY7C472
CY7C474
-.. ~
,CYPRESS
Switching Waveforms (continued)
Mark
tCY
tCY
W,R
I--
tRV ... - t p w - - .... tRV'"
7C470-16
Empty Flag and Read Data Flow-Through Mode
E
DATA IN
W---+--.....,.
8F----t-----------~==~
DATA OUT
7C470-17
5-201
CY7C470
CY7C472
CY7C474
Switching Waveforms (continued)
Full Flag and Write Data Flow-Through Mode
w
DATAIN------+------------------------(
DATA OUT -------{
DATA VALID
DATA VALID
7C470-18
Architecture
Retransmit
The CY7C470, CY7C472, and CY7C474 FIFOs consist of an array
of 8,192, 16,384, and 32,768 words of9 bits each, respectively. The
control consists of a read pointer, a write pointer, a retransmit
pointer, control signals (i.e., write, read, mark, retransmit, and masterreset), and flags (i.e., Empty/Full, Half Full, and Programmable
Almost Full/Empty).
Resetting the FIFO
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the receiver and resent if necessary. Retransmission can start from anywhere in the FIFO and be repeated without limitation.
The retransmit methodology is as follows: mark the current value
of the read pointer, after an error in subsequent read operations
return to that location and resume reading. This effectively resends all of the data from the mark point. When MARK is LOW,
the current value of the read pointer is stored. Thi~eration
marks the beginning of the packet to be resent. When RT is LOW,
the read pointer is updated with the mark location. During each
subsequent read cycle, data is read and the read pointer
incremented.
Care must be taken when using the retransmit feature. Use the
mark function such that the write pointer does not pass the mark
pointer, because further write operations will overwrite data.
Programmable Almost Full/Empty Flag
Upon power-up, the FIFO must beresetwith a Master Reset (MR)
cycle. This causes the FIFO to enter the empty condition signified
by the Empty flag (ElF) and Almost Full/Empty flag (PAFE) being
LOW, and Half Full flag (HF) being HIGH. The read pointer, write
pointer, and retransmit pointer are reset to zero. For a valid reset,
Read (R) and Write (W) must be HIGH tRPw/twpwbefore the faIling edge and tRMR after the rising edge of MR.
Writing Data to the FIFO
Data can be written to the FIFO when it is not FULUlll. A falling
edge of W initiates a write cycle. Data appearing at the inputs
(Do- Ds) tSD before and tHD after the rising edge of W will be
stored sequentially in the FIFO.
Reading Data from the FIFO
Data can be read from the FIFO when it is not empty[121. A falling
edge of R initiates a read cycle. Data outputs (Qo-Qs) are in a
high-impedance ~ndition when the FIFO is em.Ety and between
read operations (R HIGH). The falling edge of R during the last
read cycle before the empty condition triggers a high-to-low transition of ElF, prohibiting any further read operations until tRFF
after a valid write.
Notes:
11. When the FIFO is less than half.full, the flags make a LOW-to-illGH
transitionontherisinged~ofWaodmaketheHIGH-to-LOWtransi
The CY7C470/2/4 offer a variable offset for the Almost Empty
and the Almost Full condition. The offset is loaded into the proJl!!!llmable flag register (PFR) during a master reset cycle. Whi~
MR is LOW, the PFR can be loaded from Qs-Qo by pulsing R
LOW or from Ds- Do by pulsing W LOW. The offset options are
listed in Table 2. See Table 1 for a description of the six FIFO
states. If the PFR is not loaded during master reset (R and W
HIGH) the default offset will be 256 words from Full and Empty.
12. Foil and eme!Y. states cao be decoded from the Half-Full (HF) and
Empty/Full (ElF) flags.
tionon the falling edge ofR. If the FIFO is more than half full, the flags
make the LOW-to-HIGH traosition on the risi!!g edge of II aod
HIGH-to-LOW transition on the falling edge ofW.
5-202
CY7C470
CY7C472
CY7C474
57 -~
:z,CYPRESS
Thble I. Flag Truth Thblel 13]
CY77C470
(8Kx 9)
Number of Words in
FIFO
HF
ElF
PAFE
1
0
0
Empty
1
1
0
Almost Empty
1
1
1
Less tban Half Full
0
1
1
Greater than Half Full
0
1
0
Almost Full
0
0
0
Full
State
CY77C472
(16K x 9)
Number of Words in
FIFO
CY77C474
(32Kx9)
Number of Words in
FIFO
0
0
0
1 • (P - 1)
1. (P - 1)
1. (P - 1)
P.4096
P.8192
P .16384
4097 • (8192 - P)
8193 • (16384 - P)
16385 • (32768 - P)
(8192 - P+ 1) • 8191
(16384 - P+l). 16383
(32768 - P+ 1) • 32767
8192
16384
32768
Thble 2. Programmable Almost FullJEmpty Options(14]
D3
D2
D1
DO
0
0
0
0
0
0
0
1
16 or less locations from Empty/Full
16
0
0
1
0
32 or less locations from Empty/Full
32
0
0
1
1
64 or less locations from Empty/Full
64
0
1
0
0
128 or less locations from Empty/Full
128
0
1
0
1
256 or less locations from Empty/Full (default)
256
0
1
1
0
512 or less locations from Empty/Full
512
0
1
1
1
1024 or less locations from Empty/Full
1024
1
0
0
0
2048 or less locations from Empty/Full
2048
1
0
0
1
4098 or less locations from Empty/Full[15]
4098
0
8192 or less locations from Empty/Full[16]
8192
1
0
1
PAFE Active when:
P
256 or less locations from Empty/Full (default)
Notes:
13. See Table 2 for P values.
14. Almost flags default to 256 locations from Empty/Full.
15. Only for CY7C472 and CY7C474.
16. Only for CY7C470.
5-203
256
I
CY7C470
CY7C472
CY7C474
~~
; CYPRESS
'JYpical AC and DC Characteristics
$- 1.40
1
;; 1.10
Z
1.00
TA = 25°C
4.50
I
I
5.00
5.50
-
Z
0.80
r-
Vee = 5.0V
I
0.60
-55.00
6.00
5.00
65.00
NORMALIZED SUPPLY CURRENT
SUPPLY VOLTAGE
1l 1.20 f---+----1---u,.L------i
o
1.10
0
0
.9 1.10
.9
0
0
N
::;
«
::;;
0
Z
0.60 '--_--'---_---L_----L_--"
4.00
4.50
5.00
5.50
6.00
w
~
--
1.00
VIN = 3.0V
0.90 I-- TA = 25°C
f = 33 MHz
5.00
0.90
0
VIN
I
I
= 5.0V
125.00
/'
=3.0V
/
/
0.70
~
0.60
15.00
AMBIENT TEMPERATURE (OC)
OUTPUT SOURCE CURRENT
OUTPUT VOLTAGE
Vee
r- TA = 25°C
« 0.80
::;;
Z
65.00
1.00
II:
I
0.80
-55.00
01)
20.00
25.00
OUTPUT SINK CURRENT
50.00
1100.00,.---,-----,---,-----,
Z
::>
() 30.00
w
1f::>
oen
~
~
o
20.00
10.00
0.00
0.00
80.00
"- ~
40.00
2.00
3.00
f-----.~-_j--+_-_____i
20.00 hf---+---
'\
I
1.00
f----+--~=--+_-_____i
60.00 f----+-+-_j--+_-_____i
'\..
=
=
Vee 5.0V
TA 25°C
4.00
OUTPUT VOLTAGE (V)
0.00 "----_--'---_---L_----L_--"
0.00
1.00
2.00
3.00
4.00
OUTPUT VOLTAGE (V)
5-204
30.00
FREQUENCY (MHz)
vs. OUTPUT VOLTAGE
VS.
ll!
40.00 ~
II:
I-
VS. FREQUENCY
1.20
II:
0.80 f--"""''+--
NORMALIZED SUPPLY CURRENT
NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE
W
1.00 f----+---..IL--+_-_____i
CAPACITANCE (pF)
VS.
1.40 ,-----,----,---,--------,
--'
.p1~~ I~I~ ~~-'JlI~!f Iii! I~ ~
.?I~~ I~-r-'~
~ I~...l~Io
U.lf!f(a:
~ I~ ~
7 6 5 4 3 2:1: 52 51 504948 47
-46
AsL
~L
AoL
45
44
43
42
10
11
12
~ ~:
~g~!~
AsL
...J..J...J
:
...Joe a:: a:: a:: a: a:: a: a:
A'R
A:!R
AsR
OER
A'L
A:!L
AsL
~R
15
39
AsL 16
38
VOOL 17
37
VO'L, 18
36
V02L: 19
35
1/0 3L ~ 20
34
\
2122232425262728~93031 ;:~
g"g"'grIZr;, 'lgrJ:rtg.. rt~
DER
A",
AQR
A'R
~L
AsR
AoR
A7R
A2R
As.
ASL
AoL
A7L
AoL
AsL
I/OoL
I/O'L
I/0 2L
I/0 3L
AsR
AoR
NC
I/0 7R
C130-3
~R
As.
AoR
A7R
As.
As.
NC
II00R
C130-4
o"iiorAorat-~~
JJ~J>o~JoP5
CJ::::,:::,.::::,.:::::-::::.::::::,
:=:-::::.:;::.::.
Selection Guide
7CI30-25[3]
7C131-25
7C140-25
7C141-25
Maximum Access Time (ns)
Maximum oserating
Current (rnA
Maximum Standby
Current (rnA)
Com'l!Ind
7C130-30
7C131-30
7C140-30
7C141-30
7C130-35
7C131-35
7C140-35
7C141-35
7C130-55
7C131-55
7C140-55
7C141-55
25
30
35
45
55
170
170
120
90
90
170
120
120
65
65
45
35
35
65
45
45
Military
Com'l!Ind
7C130-45
7C131-45
7CI40-45
7C141-45
Military
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................. -65°C to +150 oo C
Ambient Thmperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24) ....................... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5V to + 7.0V
DC Input Voltage ....................... - 3.5V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Notes:
3. 2S-ns version available only in PLCC/PQFP packages.
Static Discharge Voltage....................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
Industrial
-40°C to +85°C
5V ± 10%
Military[4j
-55°C to + 125°C
5V ± 10%
Range
Commercial
4.
6-2
TA is the "instant on" case temperature
CY7C130/CY7C131
CY7C140/CY7C141
Electrical Characteristics Over the Operating RangelS]
7C130-25,30[3]
7C131-25,30
7Cl40-25,30
7C141-25,30
Parameter
Description
Test Conditions
Min.
VOH
Output HIGH Voltage Vee: Min., IOH : -4.0 rnA
VOL
Output LOW Voltage
Max.
2.4
7C130-35
7C131-35
7C140-35
7C141-35
Min.
Max.
V
IOL: 4.0 rnA
0.4
0.4
0.4
IOL : 16.0 rnA[6]
0.5
0.5
0.5
2.2
Input HIGH Voltage
Input LOW Voltage
2.2
IIX
InputLeakageCurrent
GND~VI~Vee
-5
+5
-5
+5
loz
Output Leakage
Current
GND ~ Vo~ Vee,
Output Disabled
-5
+5
-5
+5
los
Output Short
Circuit Currentl7, 8]
Vee: Max.,
VOUT: GND
lee
Vee Operating
Supply Current
CE:VIL,
Outputs O~en,
0.8
Corn'l
V
-5
+5
jJA
-5
+5
IlA
-350
rnA
rnA
120
90
170
120
45
35
65
45
90
75
115
90
15
15
15
15
85
70
105
85
CEL and CER ~ VIH,
Corn'l
ISB2
Standby Current
One Port,
TTL Inputs
Corn'l
CEL or CER ~ VIH,
Active Port Outputs Open,
f : fMAX[9]
Mil
115
ISB3
Standby Current
Both Ports,
CMOS Inputs
Both Ports CEL and
CER~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
VIN ~ 0.2V, f : 0
Corn'l
15
Standby Current
One Port,
CMOS Inputs
One Port CEL or
CER ~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
Corn'l
65
Mil
Mil
VIN~0.2Y,
V
0.8
170
Standby Current
Both Ports,
TIL Inputs
105
Mil
Active Port Outputs Open,
2.2
0.8
-350
Mil
f : fMAX[9]
V
-350
f : fMAX[
Unit
2.4
VIL
ISB4
Min.
Max.
2.4
VIH
ISBI
7C130-45, 55
7C131-45,55
7C140-45, 55
7C141-45, 55
rnA
rnA
rnA
rnA
f : fMAX[9]
Capacitance[8]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA: 25°C, f : 1 MHz,
Vee: 5.0V
Notes:
5. See the last page of this specification for Group A subgroup testing
information.
6. BUSY and INT pins only.
7. Dnration of the short circuit should not exceed 30 seconds.
8. Tested initially and after any design or process changes that may affect
these parameters.
9. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of lItRC and using AC Thst Waveforms input levels of GND to 3Y.
10. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5Y, input pulse levels of 0 to 3.0V and output
loading of the specified IOlJIOH, and 30-pF load capacitance.
Max.
Unit
15
pF
10
pF
11. AC Thst Conditions use VOH = 1.6V and VOL = 1.4Y.
12. At any given temperature and voltage condition for any given device,
tHZCE is less than tLzcE and tHZOE is less than tLZOE.
13. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL =
5pF as in part (b) of AC Thst Loads. ltansition is measured ± 500 mV
from steady state voltage.
14. The internal write time of the memory is defined by the overlap of CS
WW and R/W LOW. Both signals must be low to initiate a write and
either signal can terminate a write by going high. The data input set-up
and hold timing should be referenced to the rising edge of the signal
that terminates the write.
6-3
CY7C130/CY7C131
CY7C140/CY7C141
"1~
AC Test Loads and Waveforms
0""':: "" II
p'
347Q
INCLUDING _
JIG AND SCOPE
(a)
1~
0""':: 'p' "II
_
-
INCLUDING
JIG AND
SCOPE
_
-
BUSY
OR
INT
347Q
(b)
C130-5
(CY7C130/CY7C131 ONLy)
~
GND
,,;.5ns--'
--.
Switching Characteristics Over the Operating RangdS, 10]
Parameter
Description
Min.
Max.
7C130-30
7C131-30
7C140-30
7C141-30
Min.
Max.
7C130-35
7C131-35
7CI40-35
7C141-35
Min.
C130-6
10%
10%
7C130-25L3J
7C131-25
7C140-25
7C141-25
30
pF
BUSY Output Load
3.0V~90%
THEVENIN EQUIVALENT
250Q
OUTPUT 0
W'
0 1.40V
I-=
_
ALL INPUT PULSES
Equivalent to:
~"~,o
Max.
,,;.5 ns
7C130-45
7C131-45
7C140-45
7C141-45
Min.
Max.
7C130-55
7C131-55
7C140-55
7C141-55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid[ll]
tOHA
Data Hold from
Address Change
25
30
25
0
45
35
35
30
0
0
55
45
0
ns
55
0
ns
uS
tACE
CE LOW to Data Valid[ll]
25
30
35
45
55
ns
tDOE
OE LOW to Data Valid[ll]
15
20
20
25
25
ns
tLZOE
OE LOW to Low Z[12, 13]
tHZOE
OE HIGH to High Z[12, 13]
tLZCE
CE LOW to Low Z[12, 13]
tHZCE
CE HIGH to High Z[12, 13]
tpu
CE LOW to Power-Up
3
3
15
5
15
5
15
0
20
5
15
0
25
CE HIGH to Power-Down
tpD
WRITE CYCLE[14]
3
3
20
5
5
0
0
35
ns
25
20
20
25
3
ns
25
us
ns
0
35
ns
35
uS
twc
Write Cycle Time
25
30
35
45
55
ns
tSCE
CE LOW to Write End
20
25
30
35
40
ns
tAW
Address Set-Up to Write End
20
25
30
35
40
ns
tHA
Address Hold from Write End
2
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
R!W Pulse Width
15
25
25
30
30
ns
tSD
Data Set-Up to Write End
15
15
15
20
20
ns
tHD
Data Hold from Write End
0
0
0
0
0
tHZWE
R!W LOW to High Z[13]
R!W HIGH to Low Z[13]
tLZWE
15
0
20
15
0
6-4
0
20
0
ns
25
0
ns
ns
CY7C130/CY7C131
CY7C140/CY7C141
Switching Characteristics Over the Operating Rangd5, 10] (continued)
Parameter
Description
7C130-25LJJ
7C131-25
7C140-25
7C141-25
Min. Max.
7C130-30
7C131-30
7C140-30
7C141-30
Min.
Max.
7C130-35
7C131-35
7C140-35
7C141-35
Min. Max.
7C130-45
7C131-45
7C140-45
7C141-45
Min. Max.
7C130-55
7C131-55
7CI40-55
7C141-55
Min. Max.
Unit
BUSY/INTERRUPT TIMING
tBLA
tBHA
BUSY LOW from Address Match
BUSY HIGH from
Address Mismatch[15]
20
20
20
20
20
20
25
25
30
30
ns
ns
tBLC
tBHC
tps
tWBll "]
BUSY LOW from CE LOW
BUSY HIGH from CE HIGHL15J
20
20
20
20
20
20
25
25
30
30
ns
ns
ns
ns
ns
ns
ns
tWH
tBDD
tODD
tWDD
Port Set Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to
Read Data Valid
Write Pulse to Data Delay
5
0
20
5
0
30
5
0
30
5
0
35
5
0
35
25
Note
17
30
Note
17
35
Note
17
45
Note
17
45
Note
17
Note
Note
Note
Note
17
17
17
Note
17
ns
17
25
25
25
25
25
25
25
25
25
35
35
35
45
45
45
ns
ns
ns
25
25
25
35
45
ns
25
25
25
35
45
ns
25
25
25
35
45
ns
INTERRUPT TIMING
tWINS
tEINS
tINS
tOINR
tEINR
tINR
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
Address to INTERRUPT
Set Time
OE to INTERRUPT
Reset Timd 15]
CE to INTERRUPT
Reset Timd 15]
Address to INTERRUPT
Reset Timd 15]
Notes:
15. These parameters are measured from the input signal changing, until
the output pin goes to a high-impedance state.
16. CY7C140jCY7C1410nly.
17. A write operation on PortA, where PortA has priority, leaves the data
on Port B's outputs undisturbed until one access time after one of the
following:
A. BUSY on Port B goes HIGH.
B. Port B's address is toggled.
for Port B is toggled.
D. R/W for Port B is toggled during valid read.
C. CE
18. R/W is HIGH for read cycle.
19. Device is continuously selected,
= VIL and OE = VIL.
20. Address valid prior to or coincident with
transition
21. If
is
during a R/W controlled write cycle, the write pulse
be
the
larger
oftpWEortHzwE
+
tSD
to allow the data I/O
width must
pins to enter high impedance and for data to be placed on the bus for
the required tSD.
22. If the
transition occurs simultaneously with or after the
R/W
transition, the outputs remain in the high-impedance
state.
CE
OE LOW
ADDRESS
=f=___
DATA OUT
Either Port Address Access
t RC
t=tOHA~
PREVIOUS DATA
LOW
CE LOW
LOW
Switching Waveforms
Read Cycle No. 1[18, 19]
CE
*_
_ _
tAA~~
vALID/f'XXX~===============D=AT=A=V=A=L=ID==============
C130-7
6-5
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Read Cycle No. 2[18,20]
CE
Either Port CE/OE Access
~~
-tHZCE-
tACE
~
r--
tHZOE
IOOE-
tLZCE
tLZOE -
...,':771////
rISB~
DATA OUT
~
Ipu
"'" ., .,
..35:---
DATA VALID
-lpD
ICC
Read Cycle No. 3[19]
Read with BUSY, Master: CY7C130 and CY7C131
IRC
)
ADDRESSR
)(
ADDRESS MATCH
IPWE
~"
RiWR
tHD
'-./
DINR
VALID
'-
-
ADDRESSL
ffiJS"i'L
)/
Ips
-*
.~
ADDRESS MATCH
~
--IBHA
-:IBLA
IBDD-
)~
DOUTL
IDDD
IWDD
C130 9
Write Cycle No.1 (OE Three-States Data I/Os - Either Port) [14, 21]
Either Port
~-----------------------Iwc------------------------~
ADDRESS
ISCE
lAW
____.t"~_-_-_-_-_-__- .,.;IS:;.A__-_-_-_-_-_-_-_-l-cOol-.l-.........'" i4---lpWE ---~ , ________+-_______
ISD
DATA VALID
'HZOE
DOUT
»»»
9
HIGH IMPEDANCE
C130-l0
6-6
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Write Cycle No.2 (R/W Three-States Data IJOs - Either Port)[15, 22]
Either Port
~------------------~C----------------------~
ADDRESS
tSCE
R~
--_.....:._-..:;;.;.-.......-t-.-.......... "",...:;..-----
IPWE - - - - - - -
~--------------
DATAIN
IH~E~
DATAouT
)
)
)
)
)
)
)
)
)
)
)
)
)
)
tLZWE~
HIGH IMPEDANCE
_
~,...,~...,(...,(...,(,..,(.....,(
C130-11
Busy Timing Diagram No.1 (CE Arbitration)
CEL Valid First:
ADDRESSL,R
X
~~k
GEL
GER
X
ADDRESS MATCH
IBLC
BUSYR
=i
t..~~
I
C130-12
CER Valid First:
ADDRESSL,R
CER
et:L
BUSYL
X
X
ADDRESS MATCH
t~k
IBLC
=i
t~'-;r
C130-13
6-7
CY7C130/CY7C131
~
CY7C140/CY7C141
=-- ?cYPRESS
Switching Waveforms (continued)
Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First:
tRcortWC
ADDRESSL
ADDRESSR
)K
ADDRESS MATCH
BOSY
ADDRESS MISMATCH
") (
--1'""---1...-----C130-14
~tBLA
R
jl(
_tps-
I---
tBHA
Right Address Valid First:
'--
K
ADDRESSR
tRcortWC
ADDRESS MATCH
)K
ADDRESS MISMATCH
_tps-
)~
ADDRESSL
I - tBLA
BOSYL
1-1-----c130-15
I-- tBHA
Busy Timing Diagram No.3
Write with BUSY (Slave: CY7Cl40/CY7C141)
CE~
~--~----------------------
~~~-----------t~E
-t,,"-1
C130-16
6-8
CY7C130/CY7C131
CY7C140/CY7C141
~~
1CYPRESS
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR
C130-17
Right Side Clears INTR
MOO""
CER
XXXXXXXXXXXXXX~I+--_-_R_E~:C....,..3FF----,*
tHA
+
-;=:":'2:======
C130-18
Right Side Sets INT L
Left Side Clears INTL
m,""
CEl
xxxxxxxxxxxxxxf_R_E;~---:-C3FE_*,---_
tHA -----Il...-
C130-20
6-9
CY7C130/CY7C131
CY7C 140/CY7C141
~
=- .,~
~;CYPRESS
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NO~ZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.4
./
ffi 1.2
lee/
Ji 1.0
c
0.8
~
0.6
~
./
/
1.2
l)
~
~
..:
::;:
az
I---
ISB3
0.0
4.0
4.5
5.0
5.5
0.6
SUPPLY VOLTAGE
0.2
~===:;!;;::::===::;~
25
125
M
1.4
1.3
J.1.4
c 1.2
w
C
::::i
~~
~
...........
a:
az
1.0
0.9
0.8
4.0
"'"
4.5
TA = 25'C
5.0
5.5
./
1.2
1.0
0.8
1/
/
25
2.5
25.0
w 2.0
'iii'
£20.0
.,g.
C
::::i
o
1.0
2.0
-
3.0
4.0
SUPPLY VOLTAGE M
V'
/V
C 10.0
5.0
80
5D..
5a
/
~ 15.0
5.0
'"
4.0
t-
~ 100
aa:
V
20
/
I
40
/
V
o
0.0
125
/
'-'
w
/
3.0
Vee =5.0V _
TA = 25'C
1.0
I
I
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NO~ZED
Icc vs. CYCLE TIME
1.25
~
N
"
V
Z 60
1ii
Vee = 5.0V
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
0.0
/
0.6
-55
6.0
2.0
OUTPUT VOLTAGE (V)
~
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
V
1.0
.s 120
AMBIENT TEMPERATURE ('G)
0.5
o
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
SUPPLY VOLTAGE M
..:
::;: 1.5
a:
az 1.0
0
!z
3.0
l)
20
ISB3
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
J.
~ 60
a:
Vee = 5.0V
V1N = 5.0V
0.6
-55
6.0
80
:::>
a: 0.4
0.2
100
o
w
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
f-
as
C
~ 0.4
g120
m 1.01----=:::..j.""""':::::..---.-1
.!? 0.8
a:
~
V
V
o
o
Vee = 4.5V _
TA = 25'C
I
I
200 400 600 800 1000
CAPACITANCE (pF)
6-10
Jl
c
Vee = 4.5V
TA = 25'C
VIN = 0.5V
~ 1.0
~a:
~0.751----J..'£'--l----
0.501::----,:':-----::1:-----1
10
20
30
40
CYCLE FREQUENCY (MHz)
CY7C130/CY7C131
CY7C140/CY7C141
Ordering Infonnation
Speed
(ns)
30
35
45
55
Ordering Code
25
30
35
45
55
Package 'JYpe
Operating
Range
CY7C130-30PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C130-30PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C130-35PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C130-35PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C130- 35DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C130-45PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C130-45PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C130-45DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C130-55PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C130-55PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C130-55DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
Package
Name
Package 'JYpe
Operating
Range
CY7C131-25JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C131-25NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-25JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-25NI
N52
52-Pin Plastic Quad Fiatpack
CY7C131-30JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131- 30NC
N52
52-Pin Plastic Quad Fiatpack
CY7C131-30JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C131-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C131-35NC
N52
52-Pin Plastic Quad Fiatpack
CY7C131-35JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-35NI
N52
52-Pin Plastic Quad Fiatpack
CY7C131- 35LMB
L69
52-Square Leadless Chip Carrier
Military
CY7C131-45JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C131-45NC
N52
52-Pin Plastic Quad Fiatpack
CY7C131-45JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-45NI
N52
52-Pin Plastic Quad Fiatpack
CY7C131-45LMB
L69
52-Square Leadless Chip Carrier
Military
CY7C131-55JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C131-55NC
N52
52-Pin Plastic Quad Fiatpack
CY7C131-55JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-55NI
N52
52-Pin Plastic Quad Flatpack
CY7C131-55LMB
L69
52-Square Leadless Chip Carrier
Speed
(ns)
Package
Name
Ordering Code
6-11
Industrial
Commercial
Industrial
Industrial
Industrial
Military
CY7C130/CY7C131
CY7C140/CY7C141
=r":~
==-,
CYPRESS
Ordering Information (continued)
Speed
(ns)
30
35
45
55
Speed
(ns)
25
30
35
45
55
Ordering Code
Package
Name
Package 1Ype
Operating
Range
CY7C140-30PC
P25
48-Lead (600-Mil) Molded DIP
CY7C140-30PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C140-35PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C140-35PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C140-35DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C140-45PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C140-45PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C140-45DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C140-55PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C140- 55PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C140-55DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
Commercial
Package
Name
Package 1Ype
Operating
Range
CY7C141-25JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C141-25NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-25JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-25NI
N52
52-Pin Plastic Quad Flatpack
CY7C141-30JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-30NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-30JI
Ordering Code
Industrial
Commercial
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C141-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C141-35NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-35JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-35NI
N52
52-Pin Plastic Quad Flatpack
CY7C141-35LMB
L69
52-Square Leadless Chip Carrier
Military
CY7C141-45JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C141-45NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-45JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-45NI
N52
52-Pin Plastic Quad Flatpack
CY7C141-45LMB
L69
52-Square Leadless Chip Carrier
Military
CY7C141-55JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C141-55NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-55JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-55NI
N52
52-Pin Plastic Quad Flatpack
CY7C141-55LMB
L69
52-Square Leadless Chip Carrier
6-12
Industrial
Industrial
Industrial
Military
CY7C130/CY7C131
CY7C140/CY7C141
:.rcYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
Vrn
1,2,3
VILMax.
1,2,3
Ilx
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISB1
1,2,3
ISB2
1,2,3
ISB3
1,2,3
ISB4
1,2,3
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
BUSY/INTERRUPT TIMING
READ CYCLE
tRC
7,8,9, 10, 11
tBLA
7, 8, 9, 10, 11
tAA
7, 8, 9, 10, 11
tBHA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
tBLC
7, 8, 9, 10, 11
tOOE
7, 8, 9, 10, 11
tBHC
7, 8, 9, 10, 11
tps
7, 8, 9, 10, 11
WRITE CYCLE
twc
7,8,9,10,11
tWINS
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tEINS
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tINS
tHA
7, 8, 9, 10, 11
tOINR
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tEINR
7, 8, 9, 10, 11
tPWE
7, 8, 9, 10, 11
tINR
7, 8, 9, 10, 11
tso
7, 8, 9, 10, 11
BUSY TIMING
tHO
7, 8, 9, 10, 11
tWB[23]
7, 8, 9, 10, 11
tWH
7, 8, 9, 10, 11
tBOO
7, 8, 9, 10, 11
Note:
23. CY7C140/CY7C141 only.
Document #: 38-00027-K
6-13
I
CY7B131
CY7B141
lKx 8 Dual-Port
Static RAM
Features
Functional Description
• O.S-micron BiCMOS for high
performance
• Automatic power-down
• TTL compatible
• Capable of withstanding greater than
2001V electrostatic discharge
• Fully asynchronous operation
• Master CY7B131 easily expands data
bus width to 16 or more bits using
slave CY7B141
• BUSY output flag on CY7BI31; BUSY
input on CY7B141
• INT flag for port-to-port
communication
The CY7B131 and CY7B141 are highspeed BiCMOS 1K by 8 dual-port static
RAMS. Two ports are provided to permit
independent access to any location in
memory. The CY7B131 can be utilized as
either a standalone 8-bit dual-port static
RAM or as a MASTER dual-port RAM in
conjunction with the CY7B141 SlAVE
dual-port device in systems requiring
16-bit or greater word widths. It is the solution to applications requiring shared or
buffered data such as cache memory for
DSp, bit-slice, or multiprocessor designs.
Each port has independent control pins;
chip enable (CE), write enable (R/W), and
output enable (DE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port.
BUSY signals that the port is trying to access the same location currently being accessed by the other port. The INT is an interrupt flag indicating that data has been
placed in a unique location (3FF for the
right port and 3FE for the left port).
An automatic power-down feature is controlled independently on each port by the
chip enable (CE) pins.
The CY7B13l1CY7B141 are available in
52-lead PLCC.
Logic Block Diagram
RiWL
RiWR
Q:R
eEL
OE:l
OER
I\gl
I\gR
Asl
AsR
liOOl
IlOoR
1107l
lIDSYl [11
1107R
ElOS'I'R[11
A7L
A7R
Aol
AOR
INTR[21
B131-1
Notes:
1. CY7B131 (Master): BUSY is an open drain output and requires a pull-up resistor.
CY7B141 (Slave): BUSY is an input.
2. Open drain outputs; pull-up resistor required.
6-14
CY7B131
CY7B141
==- -.~
==,CYPRESS
Pin Configuration
52-Lead PLCC
'fupView
7 6 5 4 3 2
1 5251504948 47
46
11
12
13
14
15
16
17
18
19
20
7B131
78141
21222324252627282930313233
8131-2
Selection Guide
78131-15
78141-15
Maximum Access Time (ns)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)
I Com'VInd
I Com'l/Ind
78131-20
78141-20
15
20
260
240/300
110
100/105
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to +150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 52 to Pin 26) ....................... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5V to +7.0V
DC Input Voltage ....................... - 3.5V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage..................... .. >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
6-15
Range
Commercial
Industrial
Ambient
Thmperature
Vee
DoC to +70°C
5V ± 10%
-40°C to +85°C
5V ± 10%
CY7B131
CY7B141
Electrical Characteristics Over the Operating Rangel3]
78131-20
78141-20
78131-15
78141-15
Parameter
Description
Thst Conditions
Min.
Min.
Max.
Max.
VOH
Output HIGH Voltage
Vee = Min., IOH = -4.0 rnA
VOL
Output LOW Voltage
IOL = 4.0 rnA
0.4
0.4
IOL = 16.0 rnA[4]
0.5
0.5
VIH
Input HIGH Voltage
Unit
2.4
2.4
2.2
V
V
2.2
V
VIL
Input LOW Voltage
0.8
V
Irx
Input Load Current
GND.$. VI.$. Vee
-10
+10
-10
+10
Ioz
Output Leakage
Current
GND.$. Vo.$. Vee,
Output Disabled
-10
+10
-10
+10
JAA
JAA
lee
Vee Operating
Supply Current
CE = VIB Outputs Open,
f= fMAX ]
240
rnA
0.8
Standby Current Both Ports, CEL and CER ~ VIH,
f = fMAX[S]
TTL Inputs
ISBl
Com'l
Com'l
Standby Current One Port,
TIL Inputs
CEL or CER ~ VIH,
Active Port Outputs Open,
f = fMAX[S]
Com'l
ISB3
Standby Current Both Ports,
CMOS Inputs
Both Ports CEL and
CER~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
VIN.$.0.2Y,f=0
Com'l
Standby Current One Port,
CMOS Inputs
300
105
165
rnA
155
Ind
180
15
rnA
15
Ind
One Port CEL or
Com'l
CER~ Vee - 0.2Y,
VIN ~ Vee - 0.2V or VIN.$. 0.2Y,
Ind
Active Port Outputs Open,
f = fMAX[S]
rnA
100
110
Ind
ISBZ
ISB4
260
Ind
30
160
rnA
150
170
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Thst Conditions
Max.
Unit
TA = 25°C, f = 1 MHz,
10
pF
10
pF
Vee = 5.0V
Notes:
3. See the last page ofthis specification for Group A subgroup testing information.
4. BUSY and INT pins only.
5. At f~fMAX, address and data inputs are cycling at the maximum frequency of read cycle of litre and using AC Test Waveforms input levels
ofGNDto 3V.
6.
6-16
Thsted initially and after any design or process changes that may affect
these parameters.
CY7B131
CY7B141
\1~
AC Test Loads and Waveforms
5V
"1"
QUTl':;;: "p' II
""":;;: '''' II
347Q
INCLUDING _
_
JIG AND SCOPE
(a)
BOSY~2B1Q
OR
347Q
INCLUDING _
_
JIG AND SCOPE
(b)
iNT
I30pF
B131-4
B131-3
BUSY Output Load
(CY7B131 ONLy)
Equivalent to:
THEVENIN EQUIVALENT
3.0V
~£.L INPUT PULSEk~o%
_I ~
C
250Q
O
%
OUTPUT 00---"1""''''_---<10 1.4V
GND<:5
Switching Characteristics Over the Operating Rangd3, 7]
7B131-15
7B141-15
Parameter
Description
Min.
Max.
7B131-20
7B141-20
Min.
Max.
Unit
20
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Validl"]
15
20
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Validl"]
15
20
ns
tDOE
OE LOW to Data Validl8]
10
13
ns
tLZOE
OE LOW to Low ZI"1
tHZOE
OE HIGH to High Zl", iU]
tLZCE
CE LOW to Low Z19]
tHZCE
tpu
CE HIGH to High ZIY, Iu]
15
3
3
3
3
ns
13
3
0
0
ns
ns
20
15
ns
ns
13
10
CE HIGH to Power-Down
tpD
WRITE CYCLElll]
ns
3
10
CE LOW to Power-Up
ns
ns
twc
Write Cycle Time
15
20
ns
tSCE
CE LOW to Write End
12
15
ns
tAw
Address Set-Up to Write End
12
15
ns
tHA
Address Hold from Write End
2
2
ns
tSA
Address Set-Up to Write Start
0
0
ns
tpWE
RJW Pulse Width
12
15
ns
tSD
Data Set-Up to Write End
10
13
ns
tHD
Data Hold from Write End
0
0
tHZWE
R/W LOW to High Z
tLZWE
RJW HIGH to Low Z
3
Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IOlJIOH, and 30-pF load capacitance.
8. AC test conditions use VOH = 1.6V and VOL = 1.4V:
9. At any given temperature and voltage condition for any given device,
tHZCE is less than tLZCE and tHZOE is less than tLZOE.
ns
13
10
3
ns
ns
10. tLZCE, tLZWE, tHzOE, tLZOE, tHZCE, and tHZWE are tested with CL =
5pF as in part (b) of AC Test Load& Transition is measured ±500 mV
from steady-state voltage.
11. The internal write time ofthe memory is defined by the overlap of CE
LOW and R/W LOW. Both signals must be LOW to initiate a write
and either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
6-17
.1
CY7B131
CY7B141
.. ~
&
CYPRESS
Switching Characteristics Over the Operating Rangel3, 7] (continued)
7B131-15
7B141-15
Parameter
Description
Min.
Max.
7B131-20
7B141-20
Min.
Max.
Unit
20
20
20
ns
BUSY/INTERRUPT TIMING
BUSY LOW from Address Match
BUSY HIGH from Address Mismatchl12J
tBLA
tBRA
15
15
15
15
ns
ns
ns
tBLC
tBHC
tps
BUSY LOW from CE LOW
BUSY HIGH from CE HIGHllLJ
Port Set Up for Priority
5
5
ns
tWBI13J
tWH
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
0
0
ns
tBDD
tDDD
BUSY HIGH to Valid Data
Write Data Valid to Read Data Validl 14J
Write Pulse to Data Delayl14J
13
tWDD
INTERRUPT TIMING
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
tWINS
tEINS
tINS
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time l12J
CE to INTERRUPT Reset Timel 12J
tOINR
tEINR
tINR
Address to INTERRUPT Reset Timel 12J
20
15
25
20
20
30
ns
ns
ns
30
40
ns
15
20
15
15
20
ns
ns
20
ns
15
15
20
ns
20
ns
15
20
ns
Switching Waveforms
Read Cycle No.1 (Either Port-Address Access[15, 16]
~_s~
~~~~
~-
~~tRC
B131-5
Read Cycle No.2 (Either Port-CE/OE)[15, 17]
CE
DATA VALID
DATA OUT
---,~--------------------~_tPD=L
Icc~
ISB - - / '
B131-6
Notes:
12. These parameters are measured from the input signal changing, until
the output pin goes to a high-impedance state.
13. CY7B141 only.
14. For information on port-to-port deJaythrough RAM cells, from writing port to reading port, refer to the Read Timing with Port-to-Port
Delay timing diagram.
15. R/W is HIGH for read cycle.
16. Device is continuously selected, CE ~ VIL and OE ~ VIL.
17. Address valid prior to or coincident with CE transition LOW.
6-18
CY7B131
CY7B141
Switching Waveforms
(continued)
Read Cycle No.3 (Read with BUSY Master: CY7BI31)
tRC
)l'
)(
ADDRESS MATCH
tpWE
~i'\.
/
- -
(
VALID
tps
ADDRESSL
':!Jl'
ADDRESS MATCH
_t~~
SOS'(L
I-tBH~
tBoo-
~E
DOUh
tO~~
twoo
B131-7
Write Cycle No.1 (OE Three-States Data IJOs - Either Port) [11,18]
~------------------------twc--------------------------~
ADDRESS
tSCE
___~====~tS:!A-====~~. . . . . . . "'. . .----tPWE -------1_----+---Iso
- tHZOE
Dour
) ») )
DATA VALID
»
HIGH IMPEDANCE
8131-8
Note:
18. If OE is WW during a R/W controlled write cycle, the write pulse
width must be the larger of tpWE or tHZWE + tSD to allow the data I/O
pins to enter high impedance and for data to be placed on the bus for
the required tSD.
6-19
CY7B131
CY7B141
~
iz?cYPRESS
Switching Wavefonns (continued)
Write Cycle No.2
(R.iW Three-States Data IIOs -
Either Port) [11, 19]
~-------------------twc --------------------------~
ADDRESS
tSCE
Rm
~-------IPWE --------~
----------~--~~~I
,--------------
DATAIN
DOUT
ILZWE
»»»»»»»
HIGH IMPEDANCE
----t
~~(r<'7"'<'7'"<'7'"<'7'"(
8131-9
Read Timingwith Port-to-Port Delay (CEL
=CER =LOW, BUSY =HIGH for the Writing Port)
twc
ADDRESSR
RmR
DATAINR
ADDRESSL
~
/~
MATCH
tpWE
~~
/
~o
_tSD
)K
"{
VALID
MATCH
tODD
)K
DATAoUTL
)E
tWDD
8131 - 10
Note:
19. If the CE LOW transition occurs simultaneously with or after the R/W
LOW transition, the outputs remain in a high-impedance state.
6-20
CY7B131
CY7B141
Switching Waveforms (continued)
Write Timing with Port-to-Port Delay (CEL = CER = LOW)
twe
ADDRESSR
"\
':l
MATCH
~
l
1
ADDRESSL
tpWE
/
I----tSD
)~
DATAINR
-----....'/
NO MATCH
VALID
i'"
)V
MATCH
---.J
)K.
DATAINL
)~
VALID
tHD
I---tSD
I'\.
tpWE
~
t-tSHA ....
BUSYL
/V
I- tSLA
8131-11
Busy Timing Diagram No_ 1 (CE Arbitration)
CEL Valid First:
ADDRESSL,R
X
t~b
GEL
GER
X
ADDRESS MATCH
tSLe~
BUSYR
t-l
B131-12
CER Valid First:
ADDRESSL,R
GER
GEL
BOSYL
X
X
ADDRESS MATCH
~~b
tSLC~
6-21
t~'l
8131-13
CY7B131
CY7B141
1s~YPRESS
Switching Waveforms (continued)
Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First:
tRcortWC
(
ADDRESSL
ADDRESS MATCH
~(
ADDRESS MISMATCH
_tps~,{'
ADDRESSR
--=j~~I-_tSLA
_tSHA
}---.-{
8131-14
Right Address Valid First:
tRcortWC
ADDRESSR
(
ADDRESS MATCH
~(
ADDRESS MISMATCH
_tps~,{'
ADDRESSL
--:j~~I--tSLA
ElUS'i'L
-tsHA
}---.-{
8131-15
Busy Timing Diagram No.3 (Write with BUSY; Slave: CY7B141)
cr~~__________________________________
--J. .------- ------*'t
---! _f,,"-1
: -f_
t ws
tpWE
8131-16
6-22
CY7B131
CY7B141
=--~
.,CYPRESS
Interrupt Timing Diagrams
Left Side Sets INTR:
ADDRESSL
R/WL
f-*
:::;+J:::-;=-=:t-;==~====:
B131-17
Right Side Clears INTR:
ADDRESSR
vXvX~X""X"'X"'X"'X"'""'X","",X~X~X.X
....X
. . . .X
...
CER
tHA
tRC
B131-18
Right Side Sets INTL:
ADDRESSR
B131-19
Left Side Clears INTL:
ADDRESSL
CEL
VXVXVXVX"'X"'X"'X","",X","",X~X~X.X...-.X-XWI4--....
j
~---------~--'------:':':':':'::"tRC
tHA
ffiITL--------------------------------------J
6-23
I
,-
B131-20
CY7B131
CY7B141
Architecture
Flow-Through Operation
The CY7B131 (master) andCY7B141 (slave) are lO24-bytedeep
dual-port RAMs, with two independent sets of address signals,
common I/O data signals, and control signals. By convention, the
two ports are called the left port and the right port. The subscript
R or L on the signal name identifies the port.
The upper two memory locations (3FF, 3FE) are special locations
and may be used as "mailboxes" for passing messages between the
ports. Location 3FF is the mailbox for the right port and location
3FE is the mailbox for the left port. When one port writes to the
other port's mailbox, an interrupt is generated to the owner of the
mailbox. When the owner reads the mailbox, the interrupt is reset.
The address and control signals provide independent, asynchronous, random access to any location in the memory. It is possible
that both ports may attempt to access the same memory location at
the same time. If this contention occurs, a circuit in the master
called an arbiter decides which port temporarily "owns" the
memory location. The losing port receives a BUSY signal, which
notifies it that the memory location is owned by the other port and
that the operation it attempted to perform may not be successful.
The two BUSY signals are outputs from the master and inputs to
the slave.
The CY7B 131/141 have a flow-through architecture that facilitates
repeating (actually extending) an operation when a BUSY is received by a losing port. The BUSY signal should be interpreted as
aNOTREADY.lfaBUSY to a port is active, the port should wait
for BUSY to go inactive, and then extend the operation itwas performing for another cycle. The timing diagram titled, "Read Timing with Port-to-Port Delay" illustrates the case where the right
port is writing to an address and the left port reads the same address. The data that the right port has just written flows through to
the left, and is valid either tWDD after the falling edge of the write
strobe of the left port, or tDDD after the data being written becomes stable.
The timing diagram titled, "Write Timingwith Port-to-Port Delay"
illustrates the case where the right port is writing to an address and
the left port wants to write to the same address. If the left port extends its write strobe for a minimum time of tpWE after the BUSY
signal to it goes inactive, its write will be successful; it writes over
the data just written by the right port.
Contention, Arbitration and ResolutionThe Significance of BUSY
When contention occurs, the arbiter decides which port wins
(owns) the memory location and which port loses. The decision is
on a "first-come-first-served" basis. In order for contention to occur, both ports must address the same memory location and have
their respective chip enables active. If one port precedes the other
by an amount of time greater than or equal to tps (port set-up for
priority;equal to five nanoseconds) it is guaranteed to win the arbitration. If contention occurs within the tps interval, it is not possible to predict which port will win, but one will win and the other
will lose.
There are two ports and each may be either reading or writing, and
each may win or lose, so there are eight combinations. They are
listed in Table 1 and identified as cases one through eight. In cases
one and two, both ports are reading, the losing port receives a
BUSY, the read is allowed to occur, and the data read by both ports
is valid. In case three, the left port wins and reads valid data, and
the write attempted by the right port is inhibited. In cases four and
five, when the winning port is writing, the write is completed, but
the data read by the losing port may be invalid. Case six is similar
to case three; the right port successfully reads and the write attempt by the left port is inhibited. In cases seven and eight the winning port successfully writes and the attempted write by the losing
port is inhibited.
In cases four and five, where the losing port is reading, if the port
signals are asynchronous to each other, the data read may be the
old data, the new data, or some random combination of the two
sets of data. In cases seven and eight the losing port is prevented
from writing. The commonality between these four cases is that
the losing port receives a busy signal, which tells it that either (1)
the operation it attempted was not successful, or (2) that the data
it read may not be valid. In either situation, the operation should
be repeated after the busy signal becomes inactive.
Data Bus Width Expansion Using Slaves
One master and as many slaves as necessary may be connected in
parallel to expand the data bus width in byte increments.
Two masters must not be connected in parallel because, if the time
interval between which they address the same location is less than
tps, both could end up waiting for the other to release the BUSY to
it.
Therefore, only one master must arbitrate, and it can drive as many
slaves as required. The write strobe to the slaves must be delayed
an amount of time equal to at leasttBLA. This insures thatthe slave
is not inadvertently written to before the outcome of the arbitration is determined.
6-24
Table 1. Operation
Operation Port
Case
L
R
Winning
Port
1
R
R
L
Result
Both Read
2
R
R
R
Both Read
3
R
W
L
LReads OK,
R Write Inhibited
4
R
W
R
R Writes OK
L Data May Be Invalid
5
W
R
L
LwritesOK
R Data May Be Invalid
6
W
R
R
R Reads OK
L Write Inhibited
7
W
W
L
LWrites OK
R Write Inhibited
8
W
W
R
R Writes OK
L Write Inhibited
CY7B131
CY7B141
~
::arcYPRESS
'!ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
Jl1.2
Jl1.0
Cl
~ 0.8
::;
~ 0.6
gs
1.2
- ISB
I--:::::.
"
~ 0.6
~
a:
oz
lee
4.5
5.0
5.5
0.4
120
25
125
AMBIENT TEMPERATURE (OC)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
\
~ 100
:J
80
g;;
60
oen
40
~
20
o
0
I-
0.2
SUPPLY VOLTAGE (V)
« 100
1.2
1.10
!zUJ
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
Vee = 5.0V
TA = 25°C
r\
.......
o
J
J
1.1 1-----f----7'~---1
Cl
~
~
a:
~ 1.00 I--~--~<--+---l
z
a:
a:
I-
70
:J
0..
:J
60
0
AMBIENT TEMPERATURE (OC)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
1.0
~
;:;0.75
/
V
~
~0.50
a:
oz
:1
1.0
2.0
.,15.0
.s
/
V
V
Cl
SUPPLY VOLTAGE
M
5.0
"'...--V'
I
3.0
4.0
5.0
M
NORMALIZED Icc vs. CYCLE TIME
Cl
Vee = 5.0V
TA = 25°C
VIN = 0.5V
~ 1.0
~0.751---I---+-~:..j----I
I
o
Jl
~
Vee = 4.5V
TA = 25°C
5.0
4.0
I
2.0
a:
o
3.0
1.0
Vee = 5.0V 1 TA = 25°C
1.25
UJ
~V
o
/
1/
OUTPUT VOLTAGE
20.0
~
:;;: 10.0
~
J
0.25
50
0.0
0!5~5----~2~5----~125
SUPPLY VOLTAGE (V)
/
~
I-
0.95'--_---l._ _--'-_ _..L-_--'
4.0
4.5
5.0
5.5
6.0
J
z
C7i
oz
/
1/
80
()
5.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
90
UJ
:J
~
L-_ _ _~~----~
~ 1.0r
a:
I-
-
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
.§.
Cl
~1.05
0.0
\
1\
\
()
Vee = 5.0V
VIN = 5.0V
0.6
-55
6.0
§. 140
~
UJ
0.2
4.0
-
ISB3
Cl
f-""
0.0
-
..s? 0.8 -
V
0.4
z
Jl1.0
lee _ _ _ _ _
_
-
I
200 400
600 800 1000
CAPACITANCE (pF)
6-25
20
30
40
CYCLE FREQUENCY (MHz)
50
=
CY7B131
CY7B141
.,.~
='CYPRESS
o r d·
enn~
Speed
(ns)
I nt1onnatlon
Ordering Code
Package
Name
Package 1Ype
Operating
Range
15
CY7B131-15JC
J69
52-Lead Plastic Leaded Chip Carrier
20
CY7B131-20JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B131-20JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
Speed
(ns)
Ordering Code
Package
Name
Package 1YPe
Commercial
Operating
Range
15
CY7B141-15JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
20
CY7B141-20JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B141-20JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
Document #: 38-00466
6-26
CY7C132/CY7C136
CY7C142/CY7C146
2K x 8 Dual-Port
Static RAM
Features
Functional Description
• O.8-micron CMOS for optimum speed!
power
• Automatic power-down
• TTL compatible
• Capable of withstanding greater than
2001V electrostatic discharge
• Fully asynchronous operation
• Master CY7CI32/CY7CI36 easily expands data bus width to 16 or more
bits using slave CY7C142/CY7C146
• BUSY output ~ag on CY7C132/
CY7C136; BU Y input on
CY7C142/CY7C146
• INT flag for port-to-port communication (52-pin LCC/PLCC/PQFP
versions)
The CY7C132/CY7C136/CY7C142 and
CY7C146 are high-speed CMOS 2K by 8
dual-port static RAMS.1\vo ports are provided to permit independent access to any
location in memory. The CY7C132/
CY7C136 can be utilized as either a standalone 8-bit dual-port static RAM or as a
MASTER dual-port RAM in conjunction
with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit
or greater word widths. It is the solution to
applications requiring shared or buffered
data such as cache memory for nsp, bitslice, or multiprocessor designs.
Each port has independent control pins;
chip enable (CE), write enable (R/W), and
output enable (DE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of
the 52-pin LCC andPLCCversions. BUSY
signals that the port is trying to access the
same location currently being accessed by
the other port. On the LCC/PLCC versions, INT is an interrupt flag indicating
that data has been placed in a unique location (7FF for the left port and 7FE for the
right port).
An automatic power-down feature is controlled independently on each port by the
chip enable (CE) pins.
The CY7C132/CY7C142 are available in
both 48-pin DIP and 48-pin LCC. The
CY7C136/CY7C146 are available in
52-pin LCC, PLCC, and PQFP..
Logic Block Diagram
Pin Configuration
r----------CJ==~RlWR
GER
DIP
Top View
o.....t..:::J
I/o'L
MlSYL[t[ _ _
~
_ _ _ _ _..J
ASL
---+-.,--,
AOL
----t 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
Industrial
-40°C to +85°C
5V ± 10%
Military[4j
-55°C to + 125°C
5V ± 10%
Range
Commercial
4.
6-28
TA is the "instant on" case temperature
CY7C 132/CY7C136
CY7C142/CY7C146
,~
@
~"CYPRESS
Electrical Characteristics Over the Operating Range r5 ]
7C132-25,3O[3]
7C136-25,30
7C142-25,30
7C146-25,30
Parameter
Description
Test Conditions
Min.
VOH
Output HIGH Voltage Vee = Min., IOH = -4.0 rnA
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Max.
2.4
Min.
IOL = 16.0 rnA[6]
Max.
Min.
2.4
0.4
IOL = 4.0 rnA
7C132-45,55
7C136-45, 55
7C142-45,55
7C146-45, 55
7C132-35
7C136-35
7C142-35
7C146-35
0.4
0.5
2.2
0.5
Unit
0.4
V
V
0.5
2.2
0.8
Max.
2.4
2.2
0.8
V
0.8
V
IIX
Input Load Current
GND~VI~Vee
-5
+5
-5
+5
-5
+5
ftA
Ioz
Output Leakage
Current
GND~ Vos. Vee,
-5
+5
-5
+5
-5
+5
Output Disabled
f!A
los
Output Short
Circuit Current[7]
Vee = Max.,
VOUT= GND
-350
rnA
lee
Vee Operating
Supply Current
CE = VIL,
Outputs 0sren,
f = fMAX[
Corn'l
120
90
rnA
170
120
Standby Current
Both Ports,
TTL Inputs
CEL and CER L VIH,
f = fMAX[8]
Corn'l
Standby Current
One Port,
TTL Inputs
Corn'l
CEL or CER L VIH,
Active Port Outputs Open,
f = fMAX[8]
Mil
115
Standby Current
Both Ports,
CMOS Inputs
Both Ports CEL and
CERL Vee - 0.2v,
VIN L Vee - O.2Vor
VIN ~ 0.2V, f = 0
Corn'l
15
Standby Current
One Port,
CMOS Inputs
One Port CEL or
CER L Vee - 0.2V,
VIN L Vee - O.2Vor
Corn'l
ISBI
ISB2
ISB3
ISB4
-350
170
Mil
65
Mil
Mil
VIN~0.2V,
Active Port Outputs Open,
f= fMAX[8]
105
Mil
-350
45
35
65
45
90
75
115
90
15
15
15
15
85
70
105
85
rnA
rnA
rnA
rnA
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
TA = 25°C, f = 1 MHz,
15
pF
10
pF
Vee = 5.0V
Notes:
S. See the last page of this specification for Group A subgroup testing information.
6. BUSY and INT pins only.
7. Duration of the short circuit should not exceed 30 seconds.
8. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of litre and using AC Test Waveforms input levels
ofGNDt03Y.
9. Thsted initially and after any design or process changes that may affect
these parameters.
10. Test conditions assume signal transition times of S ns or less, timing
reference levels of l.SY, input pulse levels of 0 to 3.0V and output
loading of the specified Im)IoH, and 30-pF load capacitance.
11. AC test conditions use VOH = 1.6V and VOL = 1.4Y.
12. At any given temperature and voltage condition for any given device,
tHZCE is less than tLZCE and tHZOE is less than tLZOE.
13. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL =
SpF as in part (b) of AC Thst Loads. Transition is measured ±SOO m V
from steady-state voltage.
14. The internal write time of the memory is defined by the overlap of CE
LOW and R/W LOW Both signals must be LOW to initiate a write
and either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
6-29
I
CY7C132/CY7C136
CY7C 142/CY7C146
_?cYPRESS
AC Test Loads and Waveforms
5V
~:"P'II1~ o~: 'P'II1~
347Q
BlJSY
OR
3470
INCLUDING _
_
JIG AND SCOPE
(b)
INCLUDING _
_
JIG AND SCOPE
(a)
--J281Q
JfJT
I30pF
-=
C132-5
C132-6
BUSY Output Load
(CY7C132/CY7C136 ONLy)
Equivalent to:
THEvENIN EQUIVALENT
ft!=
ALL INPUT PULSES
'.W~om
10%
GND~=
2500
OUTPUT Q.O---'·I/\
.......
• ---ool.4V
10%
..
_5ns
Switching Characteristics Over the Operating Rangds. 10]
7C132-25l>j
7C136-25
7C142-25
7Cl46-25
Parameter
Description
Min.
Max.
7C132-30
7C136-30
7C142-30
7Cl46-30
Min.
Max.
7C132-35
7C136-35
7C142-35
7C146-35
Min.
Max.
7C132-45
7C136-45
7C142-45
7C146-45
Min.
Max.
7C132-55
7C136-55
7C142-55
7C146-55
Min.
Max.
Unit
READ CYCLE
25
tRC
Read Cycle Time
tAA
Address to Data Valid[ll]
tOHA
Data Hold from
Address Change
tACE
CE LOW to Data Valid[ll]
25
30
35
45
55
ns
tDOE
OE LOW to Data Valid[ll]
15
20
20
25
25
ns
tLZOE
OE LOW to Low Z[12]
tHZOE
OE HIGH to High Z[12. 13]
tLZcE
CE LOW to Low Z[12]
tHZCE
CE HIGH to High Z[12, 13]
tpu
a::: LOW to Power-Up
30
25
0
3
15
5
5
0
0
25
20
0
25
0
25
0
ns
ns
35
35
ns
ns
5
20
35
ns
25
20
ns
ns
3
5
5
ns
55
0
3
20
15
55
45
0
3
15
15
45
35
0
0
3
CE HIGH to Power-Down
tpD
WRITE CYCLE[14]
35
30
ns
twc
Write Cycle Time
25
30
35
45
55
ns
tsCE
CE LOW to Write End
20
25
30
35
40
ns
tAW
Address Set-Up to Write End
20
25
30
35
40
ns
tHA
Address Hold from Write End
2
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
R/W Pulse Width
15
25
25
30
30
ns
tSD
Data Set-Up to Write End
15
15
15
20
20
ns
tHD
Data Hold from Write End
0
0
0
0
0
tHZWE
R/W LOW to High Z
tLZWE
R/W HIGH to Low Z
15
0
15
0
6-30
20
0
20
0
ns
25
0
ns
ns
CY7C132/CY7C136
CY7C142/CY7C146
Switching Characteristics Over the Operating Rangd5, lOJ (cootioued)
7C132-251:Jj
7C136-25
7C142-25
7C146-25
Parameter
Description
Min.
7C132-30
7C136-30
7C142-30
7C146-30
Max.
Min.
Max.
7C132-35
7C136-35
7C142-35
7C146-35
Min.
Max.
7C132-45
7C136-45
7C142-45
7C146-45
Min.
Max.
7C132-55
7C136-55
7C142-55
7Cl46-55
Min.
Max.
Unit
BUSY/INTERRUPT TIMING
tBLA
BUSY LOW from Address Match
20
20
20
25
30
os
tBHA
BUSY HIGH from
Address Mismatchl 15 J
20
20
20
25
30
os
tBLC
BUSY LOW from CE LOW
20
20
20
25
30
os
tBHC
BUSY HIGH from CEHIGHlbj
20
20
20
25
30
os
tps
Port Set Up for Priority
5
5
5
5
5
os
tWB l16j
R/W LOW after BUSY LOW
0
0
0
0
0
os
tWH
R/W HIGH after BUSY HIGH
20
30
30
35
35
tBDD
BUSY HIGH to Valid Data
tDDD
tWDD
os
25
30
35
45
45
os
Write Data Valid to
Read Data Valid
Note
Note
17
Note
17
Note
17
Note
os
Write Pulse to Data Delay
Note
Note
17
Note
17
Note
Note
17
17
17
17
17
os
INTERRUPT TIMINGl18J
tWINS
R/W to INTERRUPT Set Time
25
25
25
35
45
os
tEINS
CE to INTERRUPT Set Time
25
25
25
35
45
os
tINS
Address to INTERRUPT
Set Time
25
25
25
35
45
os
tOlNR
OE to INTERRUPT
Reset Timel15 J
25
25
25
35
45
os
tEINR
CE to INTERRUPT
Reset Timel15 J
25
25
25
35
45
os
tINR
Address to INTERRUPT
Reset Time l15 J
25
25
25
35
45
os
Notes:
15. These parameters are measured from the input signal changing, until
the output pin goes to a high-impedance state.
16. CY7C142/CY7C146 only.
17. A write operatioo on Port A, where Port A has priority, leaves the data
on Port B's outputs undisturbed until one access time after one of the
following:
A. BUSY on Port B goes HIGH.
B. Port B's address toggled.
C. CE for Port B is toggled.
D. RiW for Port B is toggled during valid read.
18.
19.
20.
21.
22.
52-pin LCC/PLCC versions only.
RiW is HIGH for read cycle.
Device is contiouously selected, CE ~ VIL and OE ~ VIL.
Address valid prior to or coincident with CE transition Law.
If OE is LOW during a RiW controlled write cycle, the write pulse
width must be the larger of tPWE or tHZWE + tSD to allow the data I/O
pins to enter high impedance and for data to be placed on the bus for
the required tSD'
23. If the CE LOW transition occurs simultaneously with or after the RiW
LOW transition, the outputs remain in a high-impedance state.
Switching Waveforms
Read Cycle No.1 (Either Port-Address Access[19, 20J
ADDRESS
DATA OUT
PREVIOUS DATA
vALiD)(XX
===============D=AT=A=V=A=L=ID==============
C132-7
6-31
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
Read Cycle No.2 (Either Port-CElOE)[19, 21]
CE
i(
~I\..
OE
I--tHZCE-
tACE
~
I4--tLZOEi---tLZCE
DATA OUT
ICC
Iss
tpu
tHZOE
toOE--
...,f// / / / / / /
...
r-
...l
DATAVAUD
."\."\."\."\."\. ."\.
...,
_tpo
/I
--J"
Cl32-8
Read Cycle No.3 (Read with BUSY Master: CY7C132 and CY7C136)
tRC
)K
)K
ADDRESS MATCH
tPWE
~r
/
'd
- -
VAUD
tps
ADDRESSL
~
ADDRESS MATCH
-tLA~
.:t::'
~ tBHA
tsoo-
)E
DOUh
tO~~
twoo
Cl32 -9
Write Cycle No.1 (OE Three-States Data I/Os - Either Port) [14,22]
~-----------------------twc------------------------~
ADDRESS
~~~~---------------~CE------------------~/?~~rr~~~~~T
tAW
__-1~::::::~t~~~::::::~~~~----tpWE------~~________~________
tso
- tHZOE
Dour
»»>
»
DATAVAUD
HIGH IMPEDANCE
C132-10
6-32
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
Write Cycle No.2
(RJW Three-States Data I/Os -
Either Port)[14, 23]
~-----------------~C ------------------------~
ADDRESS
tSCE
NW
DOUT
----------~~--~~~
~----- IPWE
----------I
~---------------
ILZWE
»»»»»»»
HIGH IMPEDANCE
-----t
~j,:o("""<'7"'<-r<-r<-r~
C132-11
Busy Timing Diagram No.1 (CE Arbitration)
CEL Valid First:
ADDRESSL,R
X
~"b
GEL
CER
X
ADDRESS MATCH
BOSYR
IBLC~
t~'1
a
C132-12
CER Valid First:
ADDRESSL,R
GER
GEL
ffiJSYL
X
X
ADDRESS MATCH
~"b
IBLC~
t~l
C132-13
6-33
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First"
tRcortWC
ADDRESSL
.;(
ADDRESS MATCH
)(
ADDRESS MISMATCH
_tps-
~{
ADDRESSR
--1-1
-
BOS'i'R
tBLA
-tBHA
C132-14
Right Address Valid First:
tRcortWC
ADDRESSR
~K
ADDRESS MATCH
~(
ADDRESS MISMATCH
_tps-
ADDRESSL
)t'
--=:1_=1,-i'
--1
-tBLA
BOS'i'L
-tBHA
C132-15
Busy Timing Diagram No.3 (Write with BUSY, Slave: CY7C142/CY7C146)
cr~~__________________________________
~~~-----------tPWE-------------~~
:
_f,,"-1
-t_tWB--!
-C132-16
6-34
-
CY7C132/CY7C136
CY7C142/CY7C146
-~
---=--,
CYPRESS
Interrupt Timing Diagrams[18]
Left Side Sets INTR:
ADDRESSL
R/WL
--+-_.:.....-......
C132-17
C132-18
Right Side Sets INTL:
~----------- ~c------------~
ADDRESSR
WRITE7FE
~==~~~==~~~~~----~
JliITL
C132-19
Left Side Clears INTL:
ADDRESSL
CEL
vX'"'VX'"'VX'"'VX""X""X""X",X",X~X~X~X.X
. . . . X~~....
j,
~------.J'----. .-~--::.:.:.:.:.:.-----:..tRC
tHA
CiEL
JliITL
------------------------------------~
6-35
C132-20
CY7C132/CY7C136
CY7C142/CY7C146
1Ypicai DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
./
Jl1.2
lee/
Jl1.0
!ilN
0.8
::;
~ 0.6
~
Jl 1.0
~
0.6
Vee = 5.0V
VIN = 5.0V
a: 0.4
oZ
o 0.4
Z
0.2
-
IS63
0.0
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE
0.2
ISB3
0.6
-55
6.0
1.4
1.6
1. 1.3
1.1.4
0
W
N 1.2
::;
«
::;:
a: 1.0
0
1.2
"
~ 1.0
0.9
0.8
4.0
r-....
4.5
TA = 25°C
80
u
w
a?
60
~
-
~
o~
~
20
0
o
1.0
2001 V
(per MIL·STD·883, Method 3015)
Latch·Up Current ........................... >200 rnA
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24) ....................... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5V to + 7.0V
DC Input Voltage ....................... - 3.5V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Operating Range
6-41
Range
Commercial
Industrial
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
-40°C to +85°C
5V ± 10%
CY7C133
CY7C143
Electrical Characteristics Over the Operating Range[2]
7C133-25
7Cl43-25
Parameter
Description
Test Conditions
Min.
'!Yp.
7C133-35
7Cl43-35
Max.
2.4
Min.
'!Yp.
7C133-55
7Cl43-55
Max.
2.4
Output HIGH
Voltage
Vee = Min.,
IOH = -4.0 rnA
VOL
Output LOW
Voltage
IOL = 4.0mA
VIH
Input HIGH
Voltage
VIL
Input LOW
Voltage
Irx
Input Leakage
Current
GND.$. VI.$. Vee
-5
+5
-5
+5
Ioz
Output Leakage
Current
GND .$. Va.$. Vee,
Output Disabled
-5
+5
-5
+5
los
Output Short
Circuit
Currentf4,5]
Vee = Max.,
VOUT= GND
Icc
Vee Operating
Supply Current
CE= VIL,
0.4
IOL = 16.0 mAP]
Max. Unit
V
0.4
2.2
V
0.8
0.8
V
-5
+5
fAA
-5
-5
fAA
-200
mA
rnA
-200
-200
Com'l
170
250
160
230
150
220
Ind
170
290
160
260
150
250
60
30
50
20
40
ISBI
Standby Current CELandCER> Com'l
Both Ports, 1TL VIH, f = fMAX[OJ
Ind
Inputs
40
40
75
30
65
20
55
ISB2
Standby Current CELorCER2
Com'l
One Port, 1TL
VIH, Active Port
Inputs
Outputs oren,
Ind
f= fMAX[6
100
140
85
125
75
110
100
160
85
140
75
125
Standby Current Both Ports CEL Com'l
Both Ports,
andCER2 Vee
CMOS Inputs
- 0.2V, VIN2
Vee - 0.2Vor
Ind
VIN .$. 0.2V,
f= 0
3
15
3
15
3
15
3
15
3
15
3
15
90
120
80
105
70
90
90
140
80
120
70
105
ISB3
Standby Current One Port CEL or Com'l
One Port,
CER 2 VeeCMOS Inputs
0.2V, VIN 2 Vee
- 0.2Vor
VIN.$. 0.2V,
Ind
Active Port
ISB4
V
0.5
0.5
2.2
0.8
Outputs ~en,
f= fMAX[
'!Yp.
0.4
0.5
2.2
Min.
2.4
VOH
rnA
mA
mA
mA
Outputs~n,
f= fMAX[]
Capacitance[5]
Parameter
Test Conditions
Description
CIN
Input Capacitance
COUT
Output Capacitance
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
2. See the last page of this specification for Group A subgroup testing
information.
3. BUSY pin only.
4. Duration of the short circuit should not exceed 30 seconds.
Max.
Unit
10
pF
10
pF
Thsted initially and after any design or process changes that may affect
these parameters.
6. At f=fMAX' address and data inputs are cycling at the maximum
frequency of read cycle of litRe and using AC Test Waveforms input
levels of GND to 3Y.
5.
6-42
CY7C133
CY7C143
'1~
AC Test Loads and Waveforms
QUTl'::'r: ""'rI
INCLUDING _
JIG AND SCOPE
(a)
347Q
_
1~
'ri
0UTl':;;: '"
BOS'i'
II'IT
347Q
INCLUDING
JIG AND
SCOPE
_
-
(b)
C133-3
250Q
OUTPUTo.o---".N._---oO 1.40V
30
pF
BUSY Output Load
90%
'.ov~
10%
THEVENIN EQUIVALENT
I-=
_
-
(CY7C133 ONLy)
ALL INPUT PULSES
Equivalent to:
_r~,o
OR
Jt:::
C133-4
10%
GND
__
~3ns
_3ns
Switching Characteristics Over the Operating Range[7]
7C133-25
7C143-25
Parameter
Description
Min.
Max.
7C133-35
7C143-35
Min.
Max.
7C133-55
7CI43-55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid[8]
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid[8]
25
35
55
ns
tDOE
OE LOW to Data Valid[8]
20
25
30
ns
tLZOE
OE LOW to Low Z[9, 10]
tHZOE
OE HIGH to High Z[9, 10]
tLZCE
CE LOW to Low Z[9, 10]
tHZCE
CE HIGH to High Z[9, 10]
tpu
CE LOW to Power-Up
tpD
CE HIGH to Power-Down
25
35
25
0
55
35
3
3
15
3
20
5
15
0
20
0
25
ns
ns
5
0
25
ns
25
20
ns
ns
0
0
3
ns
55
ns
ns
25
ns
WRITE CYCLE[U]
twc
Write Cycle Time
25
35
55
ns
tSCE
CE LOW to Write End
20
25
40
ns
tAW
Address Set-Up to Write End
20
25
40
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
R!W Pulse Width
20
25
35
ns
tSD
Data Set-Up to Write End
15
20
20
ns
tHD
Data Hold from Write End
0
0
0
tHZWE
R!W LOW to High Z[10]
tLZWE
R!W HIGH to Low Z[lO)
15
0
20
0
Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5Y, input pulse levels of 0 to 3.0V and output
loading of the specified IQI)IOH, and 30-pF load capacitance.
8. AC Test Conditions use VOH = 1.6V and VOL = 1.4Y.
9. At any given temperature and voltage condition for any given device,
tLZCE is less than tHZCE and tLZOE is less than tHZOE.
ns
20
0
ns
ns
10. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHzWE are tested with CL =
5 pF as in part (b) of AC Thst Loads. Transition is measured ±500 mV
from steady state voltage.
11. The internal write time ofthe memory is defined by the overlap of CS
LOW and RiW LOW. Both signals must be LOW to initiate a write
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the
signal that terminates the write.
6-43
CY7C133
CY7C143
Switching Characteristics Over the Operating Rangd2,7] (continued)
7C133-25
7Cl43-25
Parameter
Description
Min.
Max.
7C133-35
7Cl43-35
Min.
Max.
7C133-55
7Cl43-55
Min.
Max.
Unit
BUSY/INTERRUPT TIMING (For Master CY7C133)
tSLA
BUSY Low from Address Match
25
35
50
ns
tSHA
BUSY High from Address Mismatch
20
30
40
ns
tSLC
BUSY Low from CE Low
20
25
35
ns
tSHC
BUSY High from CE High
20
20
30
ns
tWDO
Write Pulse to Data Delayl12J
50
60
80
ns
tO~~
Write Data Valid to Read Data Valid! 12J
35
45
55
ns
tsoo
tps
BUSY High to Valid Datal 13 J
Note 13
Note 13
Note 13
ns
Arbitration Priority Set Up Time!14J
5
5
5
ns
ns
BUSY TIMING (For Slave CY7Cl43)
tws
Write to BUsyl15J
0
0
0
tWH
Write Hold After BUSY!1OJ
20
25
30
tWDO
Write Pulse to Data Delayl17J
50
60
80
ns
tO~~
Write Data Valid to Read Data Valid! 1/J
35
45
55
ns
ns
Switching Wavefonns
Read Cycle No. 1[18,19]
Either Port Address Access
~!..===t;=
=======-;:-:-===t~_*~~~~ ~,
DATA OUT
ADDRESS
RC
PREVIOUS DATA vAlID4'XXX~===============DA=T=A=V=A=L=ID==============
C133-5
Notes:
12. Port-to-port delay through RAM cells from writing port to reading
port. Refer to timing waveform of "Read with BUSY, Master:
CY7C133."
13. tBOO is calculated parameter and is greater of O,twoo-twp
(actual) or toDD-tow (actual).
14. Th ensure that the earlier of the two ports wins.
15. To ensure that write cycle is inhibited during contention.
16. To ensure that a write cycle is completed after contention.
17. Port-to-port delay through RAM cells from writing port to reading
port. Refer to timing waveform of "Read with Port-to-port Delay."
18. R/W is HIGH for read cycle
19. Device is continuously selected, CE = VIL and OE = VIL.
6-44
CY7C133
CY7C143
=-~
~7CYPRESS
Switching Waveforms
(continued)
Read Cycle No. 2[18,20]
Either Port CE/OE Access
CE ~
JIt'
I-
tACE
~
ILZCE
DATA OUT
-
",
tpu
IHZOE
IOOE - -
f.-- tLZOE---
tHZCE -
../ / / / / / / /
-'
DATA VALID
~
_Ipo
Read Cycle No. 3[19]
Read with BUSY, Master: CY7C133
tRC
ADDRESSR
)K
ADDRESS MATCH
)"
IPWE
~,
-,
---)K
IHO
,,~
ADDRESSL
ffiJSYL
-
)r
tps
VALID
ADDRESS MATCH
I-
I+--
1+
tBHA
IBLA
IBOO - -
tO~~
twoo
Notes:
20. Address valid prior to or coincident with CE transition Law.
6-45
~
-
C133 7
CY7C133
CY7C143
Switching Waveforms (continued)
Timing Waveform of Read with Port-to-port Delay No.4 (For Slave CY7CI43)[21,22,23]
twc
~(
)
MATCH
twp
~
tOH
tow
~~
VALID
MATCH
twoo
)~
DOUh
tO~~
Write Cycle No.1 (OE Three-States Data I/Os - Either Port)[14,24]
Either Port
~------------------------twc ------------------------~~
~~~~~----------------tSCE ------------------~~I~~~~~~~~~~
Rm ____-1::::::::~t~sA~::::::~~~~~-----tPWE ------~~________~--------_
DATAIN ___________________
tso
~
DATA VALID
DE
~-------------------'
HIGH IMPEDANCE
C133-8
Notes:
2!. Assume BUSY input at VIR for the writing port and at VIL for the
reading port.
22. Write cycle parameters should be adhered to inorder to ensure proper
writing.
23. Device is continuously enabled for both ports.
24. If DE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger oftPWE0rtHzwE + tSD to allow the data I/O
pins to enter high impedance and for data to be placed on the bus for
the required tSD.
6-46
CY7C133
CY7C143
Switching Waveforms (continued)
Write Cycle No.2
(RiW Three-States Data I/Os -
Either Port)[20.25]
Either Port
~---------------------twc --------------------------~
ADDRESS
tSCE
R/W ----~--------~~~
~--------- tpWE -------~
tH~E~
DATAouT
>>>>>>>>>>>>>>
,--------------tLZWE
HIGH IMPEDANCE
I,
~-r<-r<-r(-r(.,..-:<
C133-10
Busy Timing Diagram No.1 (CE Arbitration)
CEL Valid First:
.JX. ._______
ADDRESSL,R _ _ _
-'X. .________
A_D_D_R_E_SS_M_A_TC_H
________
:__
\Lk~==ji\ t~'-1.
BUSyR-----------------
~
__
CER Valid First:
ADDRESSL,R
____J)x(..._______A_D_D_R_E_SS_M_A_TC_H_ _ _ _ _ _ _ _-J)xC...________
Note:
25, If the CE WW transition occurs simultaneously with or after the
R/W WW transition, the outputs remain in the high-impedance
state,
6-47
CY7C133
CY7C143
Switching Waveforms (continued)
Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First:
tRcertwC
{
ADDRESSL
{
ADDRESS MATCH
ADDRESS MISMATCH
_tps-
~(
BOSYR--1_1
ADDRESSR
_tSLA
-tSHA
Right Address Valid First:
tRcertwC
ADDRESSR
BOSY
/K
ADDRESS MATCH
) (
ADDRESS MISMATCH
I+- tps~{
ADDRESSL
_tSLA
L
--1,
i'-Jj
-------------j
-tSHA
C133-11
Busy Timing Diagram No.3
Write with BUSY (Slave: CY7C143)
cr
R/W
~~________________________________________
~~~-----------tPwE -----------~~~
F~~1
-{_tws-1
_ _
C133-12
6-48
~
CY7C133
CY7C143
-.. ~
==:;;:; CYPRESS
32-Bit Master/Slave Dual-Port Memory Systems
LEFT
RIGHT
R/W
R/W
MASTER
fvw---
5V
5V
R/W
R/W
SLAVE
~
--VIN-
BUSY
BUSY
-
C133-13
Ordering Information
Speed
(ns)
25
35
55
Speed
(ns)
25
35
55
Package
Name
Package 1YPe
Operating
Range
CY7C133-25JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C133-2511
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
Ordering Code
CY7C133 - 35JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C133-35J1
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7C133-55JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C133-5511
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
Package
Name
Package lYpe
Operating
Range
CY7C143-25JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C143 - 2511
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
Ordering Code
CY7C143-35JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C143-35J1
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7C143-55JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C143-55J1
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
6-49
I
CY7C133
CY7C143
t1iircYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
Ilx
1,2,3
loz
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISB2
1,2,3
ISB3
1,2,3
ISB4
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
Subgroups
Parameter
BUSY/INTERRUPT TIMING
tRC
7, 8, 9, 10, 11
tBLA
7, 8, 9, 10, 11
tM
7,8, 9, 10, 11
tBHA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
tBLC
7, 8, 9, 10, 11
tOOE
7, 8, 9, 10, 11
tBHC
7, 8, 9, 10, 11
WRITE CYCLE
tps
7, 8, 9, 10, 11
twc
7, 8, 9, 10, 11
tWINS
7,8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tEINS
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tiNS
7,8,9,10,11
tHA
7, 8, 9, 10, 11
tOiNR
7,8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tEINR
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tINR
7, 8, 9, 10, 11
tso
7,8,9,10,11
BUSY TIMING
tHO
7,8,9,10,11
tWB[26]
7, 8, 9, 10, 11
tWH
7, 8, 9, 10, 11
tBOD
7, 8, 9, 10, 11
Note:
23. CY7Cl43 only.
Document #: 38-00414
6-50
CY7B134
CY7B135
CY7B1342
4Kx 8 Dual-Port Static RAMs
and 4K x 8 Dual-Port Static RAM with Semaphores
Features
Functional Description
• O.S-micron BiCMOS for high
performance
• High-speed access
-15 ns (commercial)
-25 ns (military)
The CY7B134, CY7B135, and CY7B1342
are high-speed BiCMOS 4K x 8 dual-port
static RAMs. The CY7B1342 includes
semaphores that provide a means to allocate portions of the dual-port RAM or
any shared resource. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. Application areas include interprocessor/muitiprocessor designs, communications status buffering,
and dual-port video/graphics memory.
Each port has independent control pins:
chip enable (CE), read or write enable (R!
W), and output enable (DE). The
CY7B134/135 are suited for those systems
•
•
•
•
•
Automatic power-down
Fully asynchronous operation
7B1342 includes semaphores
7B134 available in 4S-pin DIP
7BI35/7B1342 available in 52-pin
LCC/PLCC
that do not require on-chip arbitration or
are intolerant ofwait states. Therefore, the
user must be aware that simultaneous access to a location is possible. Semaphores
are offered on the CY7B1342 to assist in
arbitrating between ports. The semaphore
logic is comprised of eight shared latches.
Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in
use. An automatic power-down feature is
controlled independently on each port by a
chip enable (CE) pin or SEM pin
(CY7B1342 only).
The CY7B134 is available in 48-pin DIP.
The CY7B135 and CY7B1342 are available in 52-pin LCC/PLCC.
Logic Block Diagram
RmL
-r-;====~=r----------------~
~L .::==~-,
OEL
__________
AmR
CER
~
OER
Al1R
AlOR
1/07L
I/OoL
:
VL------~
-------""-L.J-L____...::.:____.J
·•
AgL ------~~-------,
AoL
·•
-----J..-::-.~~'1_-r~==::_I~....I
I/O,"
I/OOR
·•
MEMORY
ARRAY
------~~______~
AgR
E
AoR
A'1R
SEMAPHORE
ARBITRATION
AoR
(7B1342 only)
CER
OER
AmR
(7B1342 only)
(781342 only)
SEML
SEMR
1342-1
Selection Guide
Maximum Access Time (ns)
Commercial
Maximum oserating
Current (rnA
Military
Commercial
Maximum Standby
Current (rnA)
Military
7B135-15
7B1342-15
15
260
7B134-20
7B135-20
7B1342-20
20
240
110
100
6-51
7B134-25
7B135-25
7B1342-25
25
220
260
95
100
7B134-35
7B135-35
7B1342-35
35
210
250
90
95
7B134-55
7B135-55
7B1342-55
55
210
250
90
95
==:
CY7B134
CY7B135
CY7B1342
ircYPRESS
Pin Configurations
LCC/PLCC
DIP
Top View
Top View
A2L
9
AsL
AoL
10
11
12
13
iIoL
AsL
~
AsL
AsL
I/OoL
1/0 1L
1/0 2L
1/0 3L
7 6 5 4 3 2~1~525150494847
46
45(
78135
M
15
16
17
18
19
20
44 ( A'A
43 (
42
41
~
39
38
37 (
36 (
35 (
34 (
212223242526;: 28 29 30 3~2 ~........
a: a: a: a: a: a: a:
gg z ~~g~rtg' (,)
W
(f)
~ 0
«C 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
Ambient
Temperature
O°C to +70°C
-40°C to +85°C
Range
Commercial
Industrial
MilitarylLJ
Vee
5V ± 10%
5V ± 10%
5V ± 10%
-55°C to + 125°C
Electrical Characteristics Over the Operating Range[3]
7B135-15
7B1342-15
Parameter
Description
Test Conditions
Output HIGH Voltage
Vee = Min., lOR = -4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 4.0 rnA
Vrn
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
Ioz
Output Leakage Current
Icc
Operating Current
Vee = Max.,
lOUT = OmA
ISBl
ISB2
ISBJ
ISB4
Max. Min.
2.4
0.4
7B134-25
7B135-25
7B1342-25
Max. Min.
2.2
2.2
0.8
0.8
V
GND~VI~Vee
-10
+10
-10
+10
-10
+10
Outputs Disabled,
-10
+10
-10
+10
-10
+10
fAA
fAA
220
rnA
Com'l
260
240
260
MilJInd.
Standby Current
(Both Ports TIL Levels)
CEL and CER ~ VIR,
f= fMAX[4]
Standby Current
(One Port TIL Level)
CEL and CER ~ Vrn,
f = fMAX[4]
Standby Current
(One Port CMOS Level)
V
V
GND~Vo~Vee
Standby Current
(Both Ports CMOS Levels)
Unit
V
0.4
0.4
0.8
Max.
2.4
2.4
2.2
Com'l
110
Com'l
BothPortsCEandCER~
165
155
Com'l
15
6-53
145
rnA
15
15
rnA
30
One Port CEL or CER ~ Com'l
Vee - 0.2Y,
VIN ~ Vee - 0.2V or
VIN .!>. 0.2Y, Active
Mil/Ind.
Port Out~uts,
f= fMAX4]
=
rnA
170
Mil/Ind.
4.
95
100
MilJInd.
Vee - 0.2Y,
VIN ~ Vee - O.2V
or VIN .!>. 0.2Y, f = 0[4]
Pulse width < 20 ns.
TA is the "instant on" case temperature.
See the last page ofthis specification for Group A subgroup testing information.
100
MilJInd.
Notes:
1.
2.
3.
Min.
VOR
7B134-20
7B135-20
7B1342-20
160
150
140
rnA
160
=
=
fMAX I/tRC All inputs cycling at f lItRC (except output enable).
f = 0 meas no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
CY7B134
CY7B135
CY7B1342
Electrical Characteristics Over the Operating Rangd3](continued)
Description
Parameter
Test Conditions
= Min., IOH = -4.0 mA
Vee = Min., IOL = 4.0 mA
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
Ioz
Output Leakage Current
Icc
Operating Current
Vee
ISBl
ISB2
ISB3
7B134-55
7B135-55
7B1342-55
Min.
Min.
Max.
2.4
Vee
Max.
2.4
0.4
2.2
Unit
V
0.4
V
2.2
0.8
V
0.8
V
GND:S; VI:S; Vee
-10
+10
-10
+10
Outputs Disabled, GND :s; Vo :s; Vee
-10
+10
-10
+10
!JA
!JA
mA
= Max., lOUT = 0 mA
= fMAX[4]
Standby Current
(Both Ports TTL Levels)
CEL and CER ~ VIH, f
Standby Current
(One Port TTL Level)
CEL and CER ~ VIH, f
Standby Current
(Both Ports CMOS Levels)
Both Ports CE and CER ~ Vee - 0.2Y,
VIN ~ Vee - O.2V
or VIN ::;. 0.2Y, f = 0[4]
Standby Current
(One Port CMOS Leve!)
ISB4
7B134-35
7B135-35
7B1342-35
= fMAX[4]
One Port CEL or CER ~ Vee - 0.2Y,
VIN ~ Vee - O.2V or VIN ::;. 0.2Y,
Active Port Outputs, f = fMAX[4]
Com'!
210
210
Mil/lnd.
250
250
Com'l
90
90
Mil/lnd.
95
95
Com'!
135
135
Mil/lnd.
160
160
mA
mA
Com'!
15
15
Mil/lnd.
30
30
mA
Com'!
130
130
Mil/lnd.
140
140
mA
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = S.OV
= 1 MHz,
Max.L°J
Unit
10
pF
10
pF
AC Test Loads and Waveforms
OUTPUT
~
I
C = 30pF
--
R1=893Q
R1 = 347Q
::-TI
1 1
RTH = 250Q
RTH = 250Q
OUTPUT
OUTPUT=rl
C=5pF
C=30pF
--
-=
VTH = 1.4V
(a) Normal Load (Load 1)
(b) Thevenin Equivalent (Load 1)
1342-5
Vx
(e) Three-State Delay (Load 3)
1342-6
re:
I
1342-7
ALL INPUT PULSES
'.ov~
GND$. 3 ns : .
90%
....
Notes:
5. Thsted initially and after any design or process changes that may affect
these parameters.
6.
6-54
5.3ns
1342-8
For all packages except DIP and cerDIP (D26, P25), which have maximums of eIN = 15 pF, CoUT = 15 pF.
CY7B134
CY7B135
CY7B1342
¥~
'-'CYPRESS
Switching Characteristics Over the Operating Rangel 7, 8]
Parameter
Description
7B135-15
7B1342-15
7B134 20
7B135-20
7B1342-20
7B134-25
7B135-25
7B1342-25
Min.
Min.
Min.
Max.
Max.
Max.
7B134 35
7B135-35
7B1342-35
7B134 55
7B135-55
7B1342-55
Min.
Min.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From
Address Change
15
20
15
25
20
3
3
35
25
3
3
tACE
CE LOW to Data Valid
15
20
25
tOOE
tLzOEI", lUI
OE LOW to Data Valid
10
13
15
tHZOE l9,IOJ
OE HIGH to High Z
tLZCEl9,IOJ
CE LOW to Low Z
tHZCE l9 ,IOJ
CE HIGH to High Z
tpu
CE LOW to Power Up
tpD
CE HIGH to Power Down
OE Low to Low Z
3
3
3
13
10
3
3
10
0
0
15
3
20
0
0
25
ns
ns
ns
25
0
35
ns
ns
25
3
3
ns
ns
55
25
20
15
20
3
3
3
ns
55
35
20
15
13
55
35
ns
ns
55
ns
WRITE CYCLE
twc
Write Cycle Time
15
20
25
35
55
ns
tSCE
CE LOW to Write End
12
15
20
30
50
ns
tAW
Address Set-Up to Write End
12
15
20
30
50
ns
tHA
Address Hold from Write End
2
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
Write Pulse Width
12
15
20
25
50
ns
tso
Data Set-Up to Write End
10
13
15
15
25
ns
tHO
Data Hold from Write End
0
0
0
0
0
tHZWE llO]
R!W LOW to High Z
tLZWEllU]
R!W HIGH to Low Z
twoo lll ]
Write Pulse to Data Delay
30
40
50
tooOI!l]
Write Data Valid to Read
Data Valid
25
30
30
10
13
3
3
15
3
20
ns
25
ns
60
70
ns
35
40
ns
3
3
ns
SEMAPHORE TIMING(12]
tsop
SEM Fl~date Pulse
(OEor SEM)
tSWRO
tsps
10
10
10
SEM Flag Write to Read Time
5
5
5
SEM Flag Contention Window
5
5
5
Notes:
7. See the last page ofthis specification for Group A subgroup testing information.
8. Test conditions assume signal transition time oB ns orless, timing reference levels of 1.Sv, input pulse levels ofO to 3.0V, and outpu!loading
of the specified ImJ10H and 30-pF load capacitance
9. At any given temperature and voltage condition for any given device,
tHZCE is less than tLZCE and tHZOE is less than tLZOE.
15
15
ns
5
5
ns
5
5
ns
10. Test conditions used are Load 3.
11. For information on port-to-port delay tbrough RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay
waveform.
12. Semaphore timing applies only to CY7B1342.
6-55
CY7B134
CY7B135
CY7B1342
Switching Waveforms
Read Cycle No. 1[13, 14)
Either Port Address Access
ADDRESS
DATA OUT
~-~~-IAA-~-,-*PREVIOUS DATA VALID4'XXX 2S2SJI<.==============D=A=TA=V=A=L=ID=============
1342-9
Read Cycle No. 2[13, IS)
S"EM[12IorC!: ~
Either Port CE/OE Access
'-
~
!;-ILZOEILZCE
DATA OUT
-
IHZOE
IOOEJ-///////.
Ipu
/~
I--IHZCE-
lACE
-'
DATA VALID
r-
_Ipo
~2-10
Read Timing with Port.to·Port Delay[16)
Iwe
ADDRESSR
R/WR
)(
)(
MATCH
IpWE
~~
,/
_ISO
~,(
DATAINR
ADDRESSL
VALID
f
MATCH
1000
)~
DATAouTL
Iwoo
1342-11
Notes:
13. R/W is HIGH for read cycle.
14. Device is continuously selected, CE = VIL and DE = VIL.
15. Address valid prior to or coincident with CE transition Ww.
16. CEL = CER =LDW; R/WL = HIGH
6-56
CY7B134
CY7B135
CY7B1342
~7cYPRESS
Switching Waveforms
(continued)
Write Cycle No.1: OE Three-States Data I/Os (Either Port)l17, 18, 19]
~------------------------twc--------------------------~
ADDRESS
SEJiijl12J
OReE
R/W
----~----~--~
~------------tpwE--------------~
..J;:==tSD
-----------------~
DATA VALID
,----------------
.'. tHD;J:
~-------
HIGH IMPEDANCE
1342-12
Notes:
17. The internal write tim.",2f the memory is defined by the overlap of CE
or SEM LOW and R/W LOW. Both signals must be LOW to initiate
a write and either signal can terminate a write by going HIGH. The
data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
18. R/W must be HIGH during all address transactions.
19. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O
drivers...!Q. turn off and data to ~ placed on the bus for the required
tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as
short as the specified tPWE.
6-57
CY7B134
CY7B135
CY7B1342
Switching Waveforms (continued)
Write Cycle No.2: R/WThree-States Data I/Os (Either Port)[18. 20]
~---------------------twc----------------------------~
ADDRESS
tLZWE
DATAouT
)
)
)
)
)
)
)
)
)
)
)
)
)
HIGH IMPEDANCE
)
-----L
---,Io:-(r-('r(-r(-r('r~
1342-13
Semaphore Read After Write Timing, Either Side (CY7B13420nly)[21]
1/0 0
DATAOUT VALID
R/W
1342-14
Notes:
20. Data I/O pins enter high-impedance when OE is held LOW during
write.
21. CE; HIGH for the duration ofthe above timing (both write and read
cycle).
6-58
CY7B134
CY7B135
CY7B1342
Switching Waveforms
(continued)
Timing Diagram of Semaphore Contention (CY7B1342 only)[22, 23, 24]
AoL -A2L
RIWL
"S!:fiiIL
AOR-A2R
RlWR
SEMR
----------------------------~)(~-----------MATCH
E~MATCH
L
L
1342-15
Notes:
22. I/OOR = I/OOL = LOW (request semaphore); CER = CEL = HIGH
23. Semaphores are reset (available to both ports) at cycle start.
24. Iftsps is violated, it is guaranteed that only one side will gain access to
the semaphore.
I
6-59
CY7B134
CY7B135
CY7B1342
Architecture
The CY7B134 and CY7B135 consist of an array of 4K words of 8
bits each of dual-port RAM cells, I/O and address lines, and control
signals (CE, 00, RJW). Tho semaphore control pins exist for the
CY7B1342 (SEMuR)'
Functional Description
Write Operation
Data must be set up for a duration of tso before the rising edge of
R/W in order to guarantee a valid write. Since there is no on-chip
arbitration, the user must be sure that a specific location will not be
accessed simultaneously by both ports or erroneous data could result. A write operation is controlled by either the OE pin (see Write
Cycle No.1 timing diagram) or the R/W pin (see Write Cycle No.
2 timing diagram). Data can be written tHZOE after the OE is deasserted or tHZWE after the falling edge of R/W. Required inputs for
write operations are summarized in Table 1.
If a location is being written to by one port and the opposite port
attempts to read the same location, a port-to-port flowthrough
delay is met before the data is valid on the output. Data will be valid
on the port wishing to read the location tO~~ after the data is presented on the writing port.
Read Operation
When reading a semaphore, all eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the
other port. If both ports request a semaphore control by writing a
oto a semaphore within tsps of each other, it is guaranteed that
only one side will gain access to the semaphore.
Initialization of the semaphore is not automatic and must be reset
during initialization program at power-up. All semaphores on both
sides should have a one written into them at initialization from
both sides to assure that they will be free when needed.
Table 1. Non-Contending Read/Write
Inputs
CE
When reading the device, the user must assert both the OE and CE
pins. Data will be available tACE after CE or tOOE after OE are asserted. If the user of the CY7B1342 wishes to access a semaphore,
the SEM pin must be asserted instead of the CE pin. Required inputs for read operations are summarized in Table 1.
Semaphore Operation
The CY7B1342 provides eight semaphore latches which are separate from the dual port memory locations. Semaphores are used to
reserve resources which are shared between the two ports. The
state ofthe semaphore indicates that a resource is in use. For exampie, if the left port wants to request a given resource, it sets a latch
by writing a zero to a semaphore location. The left port then verifies its success in setti~he latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tsop before attempting to read the semaphore. The semaphore value will be
available tswRO + tOOE after the rising edge of the semaphore
write. If the left port was successful (reads a zero), it assumes control over the shared resource, otherwise (reads a one) it assumes
the right port has control and continues to poll the semaphore.
When the right side has relinquished control ofthe semaphore (by
writing a one), the left side will succeed in gaining control of the
semaphore. If the left side no longer requires the semaphore, a one
is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM pin
functions as a chip enable for the semaphore latches. CE must remain HIGH during SEM LOW. Ao-z represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access. When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only 1/00 is used. If a 0 is written
to the left port of an unused semaphore, a one will appear at the
same semaphore address on the right port. That semaphore can
now only be modified by the side showing a zero (the left port in
this case). If the left port now relinquishes control by writing a one
to the semaphore, the semaphore will be set to one for both sides.
However, if the right port had requested the semaphore (written a
zero) while the left port had control, the right port would immediately own the semaphore. Table 2 shows sample semaphore operations.
6-60
R/W OE
Outputs
SEM
Operation
1/00 -1/0 7
H
X
X
H
HighZ
Power-Down
H
H
L
L
Data Out
Read DataIN
Semaphore
I/O Lines Disabled
X
X
H
X
HighZ
H
....r
X
L
Data In
Write to Semaphore
L
H
L
H
Data Out
Read
Data In
L
L
X
H
L
X
X
L
Write
Illegal Condition
Table 2. Semaphore Operation Example
Function
No Action
Left port writes
semaphore
1/0 0
Left
1
1/0 0
Right
1
Status
Semaphore free
Left port obtains
semaphore
0
1
Right port writes 0
to semaphore
0
1
Right side is denied
access
Left port writes 1 to
semaphore
1
0
Right port is granted
access to Semaphore
Left port writes 0 to
semaphore
1
0
No change. Left port
is denied access
Right port writes 1
to semaphore
0
1
Left port obtains
semaphore
Left port writes 1 to
semaphore
1
1
No port accessing
semaphore address
Right port writes 0
to semaphore
1
0
Right port obtains
semaphore
Right port writes 1
to semaphore
1
1
No port accessing
semaphore
Left port writes 0 to
semaphore
0
1
Left port obtains
semaphore
Left port writes 1 to
semaphore
1
1
No port accessing
semaphore
CY7B134
CY7B135
CY7B1342
'IYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
1.2
ISB
jl1.2
Jl1.0
C
~ O.B
:::i
...- ~
r-
V
,......
jl1.0
o
.l> O.B t - - ISB3
C
~
~ 0.6
:s
:sz 0.4
z
0.2
lee
0.0
4.0
-
lee.____
1-
4.5
5.0
5.5
0.6
~
6en
5
25
125
AMBIENT TEMPERATURE ('C)
\
Vee = 5.0V
TA = 25'C
\
40
o
0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
\
o
J.
c
1.1 f----+----.~---I
C
~
~1.05
~
cr:
~ 1.00 I--;t---::;,v;:.--+---I
~
cr:
oz
zIw
90
::l
BO
cr:
cr:
()
1.01-----4C------1
70
60
1.0
lr
':;0.75
w
/
V-
!:J
~0.50
cr:
oz
AMBIENT TEMPERATURE ('C)
/
......
0.0
o
1.0
.,15.0
:J:
/
;;: 10.0
!j
w
/
V
C
SUPPLY VOLTAGE (V)
5.0
,/
2.0
3.0
4.0
5.0
NORMALIZED Icc vs. CYCLE TIME
Jl
c
Vee = 5.0V
TA = 25'C
VIN = 0.5V
~ 1.0
~
'1
o
.,.-
Vee = 4.5V
TA = 25'C
o
4.0
1.0
Vee = 5.0V
ITA = ~5'C
cr:
5.0
3.0
/
1/
1.25
.s
V
2.0
/
OUTPUT VOLTAGE (V)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT WADING
20.0
/
0.25
50
0.0
O.B ' - - - - - - - - ' - - - - - - - - - '
-55
25
125
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
J
z
en
I::l
0I::l
SUPPLY VOLTAGE (V)
/
lI'
:.::
0
0.95 '----'----'------'----'
4.0
4.5
5.0
5.5
6.0
5.0
:? 100
.§.
J.
"- "-
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.2
1.10
\
BO
~ 20
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
'\
~ 100
::l
cr: 60
0.2
0.6
-55
6.0
§. 140
!zw 120
()
Vee = 5.0V
VIN = 5.0V
0.4
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
~
~0.751---+---I----:o.£..lI-~
-
1
200 400 600 BOO 1000
CAPACITANCE (pF)
6-61
20
30
40
CYCLE FREQUENCY (MHz)
50
I
CY7B134
CY7B135
CY7B1342
QYPRESS
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package lYPe
Operating
Range
20
CY7B134-20PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
25
CY7B134-25PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7B134-25PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7B134-25DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7B134-35PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7B134-35PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7B134-35DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7B134-55PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7B134-55PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
35
55
Speed
(ns)
Ordering Code
Package
Name
Package 1Ype
Operating
Range
15
CY7B135-15JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
20
CY7B135-20JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
25
CY7B135-25JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B135 - 25JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7B135 - 25LMB
L69
52-Square Leadless Chip Carrier
Military
CY7B135-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B135-35JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
35
55
Speed
(ns)
CY7B135 - 35LMB
L69
52-Square Leadless Chip Carrier
Military
CY7B135-55JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B135-55JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
Ordering Code
Package
1Ype
Package 1Ype
Operating
Range
15
CY7B1342-15JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
20
CY7B1342-20JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
25
CY7B1342-25JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B1342-25JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7B1342- 25LMB
L69
52-Square Leadless Chip Carrier
Military
CY7B1342-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
35
55
CY7B1342-35JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7B1342-35LMB
L69
52-Square Leadless Chip Carrier
Military
CY7B1342-55JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B1342-55JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
6-62
CY7B134
CY7B135
CY7B1342
~
-,~
~,CYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIR
VILMax.
Irx
Ioz
Icc
ISB!
ISB2
ISB3
ISB4
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
WRITE CYCLE
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tPWE
7,8,9,10,11
tSD
7,8,9,10,11
tHD
SEMAPHORE CYCLE
twc
tSCE
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tsps
Document #: 38-00161-D
tSOD
tSWRD
6-63
CY7B136
CY7B146
2K X 8 Dual-Port
Static RAM
Features
Functional Description
• O.8-micron BiCMOS for high
performance
• Automatic power-down
• TIL compatible
• Capable of withstanding greater than
2001V electrostatic discharge
• Fully asynchronous operation
• Master CY7B136 easily expands data
bus width to 16 or more bits using
slave CY7B146
• BUSY output flag on CY7B136; BUSY
input on CY7B146
• INT flag for port-to-port
communication
The CY7B136 and CY7B146 are highspeed BiCMOS 2K by 8 dual-port static
RAMS. Tho ports are provided to permit
independent access to any location in
memory. The CY7B136 can be utilized as
either a standalone 8-bit dual-port static
RAM or as a MASTER dual-port RAM in
conjunction with the CY7B146 SlAVE
dual-port device in systems requiring
16-bit or greater word widths. It is the solution to applications requiring shared or
buffered data such as cache memory for
DSp, bit-slice, or multiprocessor designs.
Each port has independent control pins;
chip enable (CE), write enable (R/W), and
output enable (00). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port.
BUSY signals that the port is trying to access the same location currently being accessed by the other port. The INT is an interrupt flag indicating that data has been
placed in a unique location (7FF for the
right port and 7FE for the left port).
An automatic power-down feature is controlled independently on each port by the
chip enable (CE) pins.
The CY7B136/CY7B146 are available in
52-lead PLCC.
Logic Block Diagram
RmL
CEL
RfliR
CE.
OEL
OE.
A10L
A10R
A7L
A7R
I/OOL
1/00.
1/07R
1/07L
l!llSYL111
llOSYRI11
AsL
AsR
AOL
AoR
Notes:
1. CY7B136 (Master~&~Y is an open drain output and requires a pull-up resistor.
2.
CY7B146 (Slave):
is an input.
Open drain outputs; pull-up resistor required.
6-64
CY7B136
CY7B146
=~
~'CYPRESS
Pin Configuration
52-Lead PLCC
Top View
-,[>-..J
.p1~.cI~ ~ 1fI~ ~I~
...,l....l
I/0 1L
I/02l
I/0 3L
t
0:
1>-0:: a: a:
~ I~ .c
7 6 5 4 3 2 1 52 51 50 4948 47
All
A'L
A'L
A.L
A'L
AsL
A7L
AsL
A9L
I/DoL
....JO
46
11
12
13
14
15
16
41
40
39
78136
78146
38
17
37
36
18
19
20
35
34
21 222324252627282930313233
...J...J...J....I
g'2001V
(per MIL-STD-883, Method 301S)
Storage Temperature .................. -65°C to + 150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Latch-Up Current ........................... >200 rnA
Operating Range
Supply Voltage to Ground Potential
(Pin 52 to Pin 26) ....................... -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.SV to + 7.0V
DC Input Voltage ....................... -3.5V to +7.0V
Output Current into Outputs (LOW) .............. 20 rnA
6-6S
Range
Commercial
Industrial
Ambient
Thmperature
Vee
O°C to +70°C
SV ± 10%
-40°C to +8SoC
SV ± 10%
CY7B136
CY7B146
Electrical Characteristics Over the Operating Rangef3]
7B136-lS
7Bl46-lS
Description
Parameter
Test Conditions
Min.
7B136-20
7B146-20
Max.
Min.
Max.
VOH
Output HIGH Voltage
Vee = Min., IOH = -4.0 rnA
VOL
Output LOW Voltage
IOL = 4.0 rnA
0.4
0.4
IOL = 16.0 rnA[4]
0.5
0.5
VIH
Input HIGH Voltage
Unit
2.4
2.4
2.2
V
V
2.2
0.8
V
VIL
Input LOW Voltage
0.8
V
IIX
Input Load Current
GND~VI~Vee
-10
+10
-10
+10
Ioz
Output Leakage
Current
GND ~ Vo~ Vee,
Output Disabled
-10
+10
-10
+10
iJA
iJA
Icc
Vee Operating
Supply Current
CE = VIB Outputs Open,
f = fMAX ]
240
rnA
Standby Current Both Ports, CEL and CER ~ VIH,
f= fMAX[5]
1TLInputs
ISB!
Com'l
Com'l
Standby Current One Port,
1TLInputs
CEL or CER ~ VIH,
Active Port Outputs Open,
f= fMAX[5]
Ind
ISB3
Standby Current Both Ports,
CMOS Inputs
Both Ports CEL and
CER~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
VIN ~ 0.2Y, f = 0
Com'l
Standby Current One Port,
CMOS Inputs
300
110
100
Ind
ISBZ
ISB4
260
Ind
Com'l
165
rnA
155
180
15
rnA
15
Ind
One Port CEL or
Com'l
CER~ Vee - 0.2Y,
VIN ~ Vee - 0.2VorVIN ~0.2Y,
Ind
Active Port Outputs Open,
rnA
105
30
160
rnA
150
170
f= fMAX[5]
Capacitance[6]
Parameter
Description
Thst Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
10
pF
COUT
Output Capacitance
Vee
10
pF
Notes:
3. See the last page of this specification for Group A subgroup testing in·
formation.
4. &JSY and 00 pins only.
5. At f=fMAX, address and data inputs are cycling at the maximum fre·
quency of read cycle of lItre and using AC Thst Waveforms input levels
ofGNDto3v'
6.
6-66
= 5.0V
Thsted initially and after any design or process changes that may affect
these parameters.
CY7B136
CY7B146
~
==
-,~
'CYPRESS
"1"
AC Test Loads and Waveforms
"1"
mIT"::;: '" pF II
INCLUDING _
JIG AND SCOPE
(a)
0""'::;: 'p' II
347Q
_
-
BUS'7
OR
347Q
INCLUDING _
_
JIG AND SCOPE
(b)
--1
5V
fI\IT
281
Q
I30PF
8136-4
8136-3
BUSY Output Load
(CY7B136 ONLY)
Equivalent to:
THEVENIN EQUIVALENT
250Q
OUTPUT OO---""J\I\
.._ - - - 4 0 1.4V
3.0V
~7a:PUT PULSE~S
90%
10%
GND
10%
~3ns
~3ns
-
Switching Characteristics Over the Operating RaDgd 3, 7]
7B136-15
7Bl46-15
Parameter
Description
Min.
Max.
7B136-20
7B146-20
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Validl~j
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Validl~j
tDOE
OE LOW to Data Validl~j
tLZOE
OE LOW to Low ZIYj
tHZOE
OE HIGH to High ZIY, lUj
tLZCE
CE LOW to Low Zl9J
tHZCE
CE HIGH to High ZIY, lUj
tpu
CE LOW to Power-Up
15
20
15
DS
20
DS
13
DS
3
3
15
10
DS
3
3
3
DS
13
10
3
10
0
DS
DS
13
DS
DS
0
15
CE HIGH to Power-Down
tpD
WRITE CYCLElllj
DS
20
20
DS
twc
Write Cycle Time
15
20
DS
tSCE
CE LOW to Write EDd
12
15
DS
tAW
Address Set-Up to Write EDd
12
15
DS
tHA
Address Hold from Write EDd
2
2
DS
tSA
Address Set-Up to Write Start
0
0
DS
tpWE
RJW Pulse Width
12
15
DS
tSD
Data Set-Up to Write EDd
10
13
DS
tHD
Data Hold from Write EDd
0
tHZWE
RJW LOW to High Z
RJW HIGH to Low Z
tLZWE
3
Notes:
7. Test coDditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IorJIOH, and 30-pF load capacitance.
8. AC test conditions use VOH = 1.6V and VOL = 1.4Y.
9. At any given temperature and voltage condition for any given device,
tHZCE is less than tLZCE and tHZOE is less than tLZOE'
DS
0
13
10
3
DS
DS
10. tLZCE, tLZWE, tHZOE, tLzOE, tHZCE, and tHZWE are tested with CL =
5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV
from steady-state voltage.
11. The internal write time of the memory is defined by the overlap of CE
LOW and R/W LOW: Both signals must be LOW to initiate a write
and either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
6-67
CY7B136
CY7B146
•,CYPRESS
4~
Switching Characteristics Over the Operating Rangel3, 7] (continued)
7B136-15
7B146-15
Parameter
BUSY/INTERRUPT TIMING
tBLA
tBHA
tBLC
tBHe
tps
tWB 1Uj
Description
Min.
Min.
Max.
Unit
BUSY LOW from Address Match
BUSY HIGH from Address Mismatchl12j
15
20
ns
15
20
ns
BUSY LOW from CE LOW
BUSY HIGH from CE HIGHP2j
15
15
20
20
ns
ns
Port Set Up for Priority
5
0
R!W LOW after BUSY LOW
R!W HIGH after BUSY HIGH
tWH
Max.
7B136-20
7B146-20
13
5
ns
0
20
ns
ns
BUSY HIGH to Valid Data
Write Data Valid to Read Data Validl14j
Write Pulse to Data Delay[l4j
15
25
20
30
ns
ns
30
40
ns
tWINS
R!W to INTERRUPT Set Time
15
20
ns
tErNS
tINS
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time l1Zj
15
15
20
20
ns
15
20
ns
CE to INTERRUPT Reset Time l12j
15
20
ns
Address to INTERRUPT Reset Time l12j
15
20
ns
tBDD
tDDD
tWDD
INTERRUPT TIMING
tOINR
tEINR
tINR
ns
Switching Waveforms
Read Cycle No.1 (Either Port-Address Access[15,16]
=lL~
.oD'=
DATA OUT
~~.
*-
PREVIOUS DATA v;3J\<=============D=A=JA==VA=L=ID=============
Bl36-5
Read Cycle No.2 (Either Port-CE/OE)[15, 17]
DATA OUT
ICC
______~------------------------------------~~--_I__PD~
lSB
B136-6
Notes:
12. These parameters are measured from the input signal changing, until
the output pin goes to a high-impedance state.
13. CY7B146 only.
14. For information on port-to-port delay through RAM cells, from writing port to reading port, refer to the Read Timing with Port-to-Port
Delay timing diagram.
15. R/W is HIGH for read cycle.
16. Device is continuously selected, CE = VIL and OE = VIL.
17. Address valid prior to or coincident with CE transition Law.
6-68
CY7B136
CY7B146
lzrcYPRESS
Switching Waveforms
(continued)
Read Cycle No.3 (Read with BUSY Master: CY7B136)
lAC
j(
tpWE
~
ADDRESSL
-
),
ADDRESS MATCH
/
)(
VALID
Ips ~
)~
ADDRESS MATCH
~t~~
SITS'i'L
-tBHA~
tSDD-
)~
twoo
tODD
8136 -7
Write Cycle No.1 (OE Three-States Data II0s - Either Port) [11,18)
~------------------------twc--------------------------~
ADDRESS
R/W
_.J::===~tSA~===:::::;~.......,"", ....-----tPWE ----...-/ ,.._ _ _ _1-_ _ __
I
Iso
DATA VALID
-tHZOEa
DOUT
»»>
HIGH IMPEDANCE
8136-8
Note:
18. If DE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tpWE or tHZWE + tso to allow the data I/O
pins to enter higb impedance and for data to be placed on the bus for
the required tso.
6-69
CY7B136
CY7B146
Switching Waveforms (continued)
Write Cycle No.2
(R/W Three-States Data I10s -
Either Port)[ll, 19]
~-------------------twc --------------------------~
ADDRESS
tSCE
RM ----------------~~~
DOUT
~-------tPWE--------~
/----------------
tlZWE4
»»»»»»»
HIGH IMPEDANCE
~T<-r<-r<-r<"T'~
8136-9
ReadTimingwith Port-to-Port Delay (CEL = CER= WW,BUSY=IDGHforthe Writing Port)
twc
ADDRESSR
RmR
DATAINR
ADDRESSL
~K
K
MATCH
tpWE
~i'i.
/
_tso
)K
'd
f
VALID
MATCH
toDD
)
DATAOUTL
twoo
)E
-
8136 10
Note:
19. If the CE LOW transition occurs simultaneously with or after the R/W
LOW transition, the outputs remaio in a high-impedance state.
6-70
CY7B136
CY7B146
Switching Waveforms (continued)
Write Timing with Port·to·Port Delay (CEL = CER = LOW)
twe
ADDRESSR
")E
)E
MATCH
./
I
1>WE
'}
)(
DATAINR
ADDRESSL
/
I---tSO
=:)<
VALID
NO MATCH
*
tHO
)K:
MATCH
)
DATAINL
)t=
VALID
_tso
tpWE
"-
tHO
/
. . tBHA ....
/
_ tBLA
BI36- 11
Busy Timing Diagram No.1 (CE Arbitration)
eEL Valid First:
-JX'-_______
ADDRESSL,R _ _
--'X'--_______
A_D_D_R_E_S_S_M_A_TC_H_ _ _ _ _ _ _
8136-12
-JX'-_______
ADDRESSL,R _ _
--'X'-_______
A_D_D_R_E_S_S_M_AT_C_H_ _ _ _ _ _ _
6-71
CY7B136
CY7B146
Switching Waveforms (continued)
Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First:
IRCorlWC
(
ADDRESSL
)(
ADDRESS MATCH
ADDRESS MISMATCH
_IpsADDRESSR
E~IBLA
I--
tsHA
::j_41--
}
--./f
B136-14
Right Address Valid First:
IRCorlWC
ADDRESSR
(
ADDRESS MATCH
(
ADDRESS MISMATCH
_lpSADDRESSL
I{
~IBLA
!roS'i'L
1",-----1
I--
IBHA
B136-15
Busy Timing Diagram No.3 (Write with BUSY, Slave: CY7B146)
cr~~_______________________________________
~~~------------IPWE ------------~~~
:
_f,,"--J
-f_IWB-!
B136-16
6-72
"~
CY7B136
~, CYPRESS ==============~C~Y7~B~14~6
Interrupt Timing Diagrams
Left Side Sets INTR:
ADDRESSL
8136-17
8136-18
Right Side Sets INTL:
~------------
ADDRESSR
GER
twc
WRITE7FE
::==~~::~=t:;~::::::=1--~~~::::~~~------------J
8136-19
Left Side Clears INTL:
ADDRESSL
GEL
vX"VX"VX"VX""X""X"'X"""'X,,"",X~X~X~X,........,X-Xtl4--:1,
~-----------,,----~--=~~~-------------=
tRC
tHA
m:L
INTL
----------------------------------------~
6-73
8136-20
CY7B136
CY7B146
Architecture
Flow-Through Operation
The CY7B136 (master) and CY7B146 (slave) are 2048-byte deep
dual-port RAMs, with two independent sets of address signals,
common I/O data signals, and control signals. By convention, the
two ports are called the left port and the right port. The subscript
R or L on the signal name identifies the port.
The upper two memory locations (7FF, 7FE) are special locations
and may be used as "mailboxes" for passing messages between the
ports. Location 7FF is the mailbox for the right port and location
7FE is the mailbox for the left port. When one port writes to the
other port's mailbox, an interrupt is generated to the owner of the
mailbox. When the owner reads the mailbox, the interrupt is reset.
The address and control signals provide independent, asynchronous, random access to any location in the memory. It is possible
that both ports may attempt to access the same memory location at
the same time. If this contention occurs, a circuit in the master
called an arbiter decides which port temporarily "owns" the
memory location. The losing port receives a BUSY signal, which
notifies it that the memory location is owned by the other port and
that the operation it attempted to perform may not be successful.
The two BUSY signals are outputs from the master and inputs to
the slave.
The CY7B136/146 have a flow-through architecture that facilitates
repeating (actually extending) an operation when a BUSY is received by a losing port. The BUSY signal should be interpreted as
a NOT READY. If a BUSY to a port is active, the port should wait
for BUSY to go inactive, and then extend the operation it was performing for another cycle. The timing diagram titled, "Read Timing with Port-to-Port Delay" illustrates the case where the right
port is writing to an address and the left port reads the same address. The data that the right port has just written flows through to
the left, and is valid either tWDD after the falling edge of the write
strobe of the left port, or tDDD after the data being written becomes stable.
The timing diagram titled, "Write Timingwith Port-to-PortDelay"
illustrates the case where the right port is writing to an address and
the left port wants to write to the same address. If the left port extends its write strobe for a minimum time of tpWE after the BUSY
signal to it goes inactive, its write will be successful; it writes over
the data just written by the right port.
Contention, Arbitration and ResolutionThe Significance of BUSY
When contention occurs, the arbiter decides which port wins
(owns) the memory location and which port loses. The decision is
on a "first-come-first-served" basis. In orderfor contention to occur, both ports must address the same memory location and have
their respective chip enables active. If one port precedes the other
by an amount of time greater than or equal to tps (port set-up for
priority;equal to five nanoseconds) it is guaranteed to win the arbitration. If contention occurs within the tpsinterval, it is not possible to predict which port will win, but one will win and the other
will lose.
There are two ports and each may be either reading or writing, and
each may win or lose, so there are eight combinations. They are
listed in Table 1 and identified as cases one through eight. In cases
one and two, both ports are reading, the losing port receives a
BUSY, the read is allowed to occur, and the data read by both ports
is valid. In case three, the left port wins and reads valid data, and
the write attempted by the right port is inhibited. In cases four and
five, when the winning port is writing, the write is completed, but
the data read by the losing port may be invalid. Case six is similar
to case three; the right port successfully reads and the write attempt by the left port is inhibited. In cases seven and eight the winning port successfully writes and the attempted write by the losing
port is inhibited.
In cases four and five, where the losing port is reading, if the port
signals are asynchronous to each other, the data read may be the
old data, the new data, or some random combination of the two
sets of data. In cases seven and eight the losing port is prevented
from writing. The commonality between these four cases is that
the losing port receives a busy signal, which tells it that either (1)
the operation it attempted was not successful, or (2) that the data
it read may not be valid. In either situation, the operation should
be repeated after the busy signal becomes inactive.
Data Bus Width Expansion Using Slaves
One master and as many slaves as necessary may be connected in
parallel to expand the data bus width in byte increments.
1Wo masters must not be connected in parallel because, if the time
interval between which they address the same location is less than
tps, both could end up waiting for the other to release the BUSY to
it.
Therefore, only one master must arbitrate, and it can drive as many
slaves as required. The write strobe to the slaves must be delayed
an amount of time equal to at leasttBLA. This insures thatthe slave
is not inadvertently written to before the outcome of the arbitration is determined.
6-74
Thble 1. Operation
Operation Port
Case
L
R
Winning
Port
1
R
R
L
2
R
R
R
Both Read
LReadsOK,
R Write Inhibited
Result
Both Read
3
R
W
L
4
R
W
R
R Writes OK
L Data May Be Invalid
5
W
R
L
Lwrites OK
R Data May Be Invalid
6
W
R
R
RReadsOK
L Write Inhibited
7
W
W
L
LWrites OK
R Write Inhibited
8
W
W
R
R Writes OK
L Write Inhibited
CY7B136
CY7B146
'lYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NO~ZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.4
Jl1.2
15 1.0
o
~
1--".-
I!:l
~
0.8 i-""
gs
0.4
z
12
-
ISB
.......-
Jl1.0
I!:l::::;
~
gs
z
0.2
lee
4.5
5.0
-
-
u
;; 0.8 ' - - ISB3
0.6
0.0
4.0
lee _ _ _ _
1-
5.5
~ 120
0.4
~ 100
=>
80
en
~
25
125
AMBIENT TEMPERATURE (OC)
a
0
o
o
~
~ 1.00 I---\l-----::;,joo£--+---I
~
a:
az
1
100
zw
90
I-
1.1 f-----+------",tL----1
I!:l
1!:l1.05
z
(j)
a
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
/
V
~0.50
a:
az
o
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
0015.0
~
~
:;c 10.0
/
V
~
w
o
"
1.0
Vee = 5.0V 1 TA = 25°C
I
I
2.0
3.0
4.0
5.0
NO~ZED
Icc vs. CYCLE TIME
Vee = 5.0V
TA = 25°C
VIN = 0.5V
Jl
o
I!:l
1.0
~a:
~ 0.75!---+--+-.......,,,L-1---l
I
o
o
..... :---
Vee = 4.5V
TA = 25°C
5.0
5.0
/
1/
1.25
.s
V
0.0
60
/
OUTPUT VOLTAGE (II)
20.0
J
0.25
70
50
0.0
0!5~5----~25~---~1~25
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
~
5.0
/
~
I::l
AMBIENT TEMPERATURE (OC)
/
-
J
=> 80
1.01------:10,£...-----1
SUPPLY VOLTAGE (II)
J.
0 0.75
V
a:
a:
0..
1.0
"-
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (II)
u
I::l
0.95 '--_-'-_ _.l..-_--1._ _....I
4.0
4.5
5.0
5.5
6.0
o
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.2
J
~
~ 20
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
J
Vee = 5.0V
TA = 25°C
!:i
SUPPLY VOLTAGE (II)
1.10
\
1\
\
~ 60
a
0.2
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
\
w
~
Vee = 5.0V
VIN = 5.0V
0.6
-55
6.0
11~
c..:>
0.6
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
~
-
I
200 400 600 800 1000
CAPACITANCE (pF)
6-75
20
30
~
CYCLE FREQUENCY (MHz)
50
CY7B136
CY7B146
QYPRESS
ord
.
enn~
Speed
(ns)
I ntionnabon
Ordering Code
Package
Name
Package 1YPe
Operating
Range
15
CY7B136-15JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
20
CY7B136-20JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B136-20JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
Speed
(ns)
Ordering Code
Package
Name
Package 1Ype
Operating
Range
15
CY7B146-15JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
20
CY7B146- 20JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B146- 20n
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
Document #: 38-00464
6-76
CY7B138
CY7B139
4Kx 8/9 Dual-Port Static RAM
with Sem, lnt, Busy
Features
Functional Description
• O.8-micron BiCMOS for high
performance
• High-speed access
-15 ns (com'l)
-25ns (mil)
• Automatic power-down
• Fully asynchronous operation
• Master /Slave select pin allows hus
width expansion to 16/18 hits or more
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking between ports
• INT flag for port-to-port
communication
• Available in 68-pin LCC/PLCC/PGA
• TTL compatible
The CY7B138 and CY7B139 are highspeed BiCMOS 4K x 8 and 4K x 9 dualport static RAMs. Various arbitration
schemes are included on the CY7B138/9
to handle situations when multiple processors access the same piece of data. Tho
ports are provided permitting independent, asynchronous access for reads and
writes to any location in memory. The
CY7B138/9 can be utilized as a standalone 32-Kbit dual-port static RAM or
multiple devices can be combined in order
to function as a 16/18-bit or wider master/
slave dual-port static RAM. An M/S pin is
provided for implementing 16/18-bit or
wider memory applications without the
need for separate master and slave devices
or additional discrete logic. Application
areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.
Each port has independent control pins:
chi£..enable (CE), read or write enable
(R/W), and output enable (OE).Tho flags
are provided on each port (BU~Y ~nd
INT). BUSY signals that the port IS trymg
to access the same location currently being accesse~ the other port. The interrupt flag (INT) permits communication
between ports or systems by means of a
mail box. The semaphores are used to
pass a flag, or token, from one port to the
other to indicate that a shared resource is
in use. The semaphore logic is comprised
of eight shared latches. Only one side can
control the latch (semaphore) at any time.
Control of a semaphore indicates that a
shared resource is in use. An automatic
power-down feature is controlled independently on each port by a chip enable
(CE) pin or SEM pin.
The CY7B138 and CY7B139 are available in 68-pin LCCs, and PLCCs.
Logic Block Diagram
RJWL ......_ _--<~-
RfiiR
CER
ITER
A11L
A10l
(7B139)
====t=:::::;~
A11A
A10R
:;g~~ ::---...J~...rr~l_1...J...::::::_;_:::;:_-_n--'
:
I/O.R (7B139)
1/0 7R
V~------~~
L __,--__.l-L.....Jf-----
VOOl •
·
•
•
AcL -t--~~---~
AcL
INTERRUPT
SEMAPHORE
ARBITRATION
eEL
~L
·
AgR
AcR
A11A
Ace
CER
eER
RfiiR
RJWL
JiiiiL[21
••
MEMORY
ARRAY
A11L
eEL
I/OOR
IlUSYR[1.21
iIDSYL[ 1 . 2 1 - - t - - - - - - - - - - - '
------------"
--------------
B138-1
MiS
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2.
6-77
Master: push-pull output and requires no pull-up resistor.
II
CY7B138
CY7B139
Pin Configurations
68·Pin LCC/PLCC
ThpView
V0 2L
I/O.L
V0 4L
VOSL
GND
IfOSL
I/0 7L
Vcr;
GND
I/OOR
VOlA
va..
Vee
VO.R
V04R
VOSR
1/a...
9 8 7 6 5 4 3 2 168 67666564636261 "
60 (
59
58 (
57 (
10
11
12
13
AsL
~L
AsL
A2L
14
56
15
ffl
55
AcL
M
~
17
18
19
A1L
53
llOS'IL
52
GND
51 ( MiS
76138/9
20
50 ( I!US'IR
21
22
23
49 (
IN'i'R
48 (
!\oR
24
25
26
46
A2R
45 ( AvR
44
~R
47( AIR
V2626~~~~M~38U38~~~.~
6138-2
Notes:
3. I/O 8R on the CY7B139.
4. IJOSL on the CY7B139.
Pin Definitions
Right Port
LeftPort
Description
I/OOL-7L(8L)
I/O OR-7R(8R)
Data Bus Input/Output
AoL-llL
CEL
AoR-llR
Address Lines
CER
Chip Enable
OEL
OER
Output Enable
RiWL
SEML
RiWR
SEMR
INTL
INTR
Interrupt Flag. INTL is set when ri!!!!!'p"ortwrites location FFE and is cleared
when left port reads location FFE. INTR is set when left port writes location
FFF and is cleared when right port reads location FFF.
IffiSYL
BUSYR
Busy Flag
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight semaphores.
The three least significant bits of the address lines will determine which serna·
phore to write or read. The lIOo pin is used when writing to a semaphore.
Semaphores are requested by writing a 0 into the respective location.
MIS
Master or Slave Select
Vee
GND
Power
Ground
Selection Guide
7B138-15
7B139-15
Maximum Access Time (ns)
Maximum oserating
Current (rnA
Maximum Standby
Current for ISBl(rnA)
Commercial
7B138-35
7B139-35
15
78138-25
7B139-25
25
35
55
260
220
210
210
280
250
250
95
90
90
100
95
95
Military/Industrial
Commercial
110
Military/Industrial
6-78
7B138-55
7B139-55
CY7B138
CY7B139
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to + 150°C
Ambient Thmperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential ........ -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to + 7.0V
DC Input Voltage[5] ..................... -O.5V to + 7.0V
Static Discharge Voltage....................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Commercial
Industrial
Military[6]
Output Current into Outputs (LOW) .............. 20 rnA
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Range
-40°C to +85°C
5V ± 10%
-55°C to + 125°C
5V ± 10%
Electrical Characteristics Over the Operating Rangd 7]
Parameter
Description
7B138 15
7B139-15
Min.
Max.
Test Conditions
Output HIGH Voltage
Vee = Min., IOH = -4.0 rnA
Vee - Min., IOL = 4.0 rnA
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IIX
loz
Input Leakage Current
Output Leakage Current
Icc
Operating Current
GND.$. VI.$. Vee
Output Disabled, GND .$. Vo.$. VCC
Com'l
Vee = Max.,
lOUT = ornA,
MiVlnd
Outputs Disabled
VOH
VOL
VIH
ISB2
Standby Current
(One Port TTL Level)
CEL and CER ~ VIH,
f = fMAX[8)
ISB3
Standby Current
(Both Ports CMOS Levels)
Both Ports
CE and CER ~ Vcc - 0.2Y,
VIN ~ Vee - 0.2V
or VIN .$. 0.2Y, f = 0(8)
Standby Current
(One Port CMOS Level)
0.4
2.2
One Port
CEL or CER ~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
VIN.$. 0.2Y, Active
Port Outputs, f = fMAX[8)
Notes:
5. Pulse width < 20ns.
6. TA is the "instant on" case temperature.
7. See the last page of this specification for Group A subgroup testing
information.
8. fMAX = l/tRC = All inputs cycling at f = I/tRC (except output enable).
f = 0 means no address or control lines change. This applies only to
inputs at CMOS level standby ISB3.
6-79
Com'l
MiI/lnd
Com'l
MiVInd
Com'l
+10
-10
-10
+10
260
-10
MiVInd
+10
+10
220
V
V
V
iJA
iJA
rnA
280
110
165
15
95
100
145
180
15
rnA
rnA
rnA
30
MiI/lnd
Com'l
0.8
-10
Unit
V
0.4
0.8
CEL and CER ~ VIH,
f= fMAX[8]
ISB4
2.4
2.2
Standby Current
(Both Ports TTL Levels)
ISB!
2.4
7B138 25
7B139-25
Min.
Max.
160
140
160
rnA
£2.-:z
CY7B138
CY7B139
~rcYPRESS
Electrical Characteristics Over the Operating Rangd7] (continued)
7B138-35
7B139-35
Description
Parameter
'lest Conditions
Min.
VOH
Output HIGH Voltage
Vee - Min., IOH - -4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 4.0 mA
VIH
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
VIL
IIX
ISBl
Standby Current
(Both Ports TIL Levels)
ISBZ
Standby Current
(One Port TTL Level)
Standby Current
(Both Ports CMOS Levels)
Standby Current
(One Port CMOS Level)
ISB4
0.4
GND.$. VI.$. Vee
Output Disabled, GND .$. Vo.$. V cc
Com'l
Vee = Max.,
lOUT = ornA,
Mil/lnd
Outputs Disabled
Com'l
CEL and CER ~ VIH,
f= fMAX[8]
MiVlnd
Com'l
CEL and CER ~ VIH,
f= fMAX[8]
MiVlnd
Com'l
Both Ports
CE and CER ~ V cc - 0.2Y,
VIN ~ Vee - 0.2V
MiVInd
or VIN .$. 0.2Y, f = 0[8]
One Port
CEL or CER ~ Vcc - 0.2Y,
VIN ~ Vee - O.2Vor
V IN .$. 0.2Y, Active
Port Outputs, f = fMAX[8]
-10
-10
Max.
Unit
2.4
V
0.4
V
V
2.2
0.8
Operating Current
ISB3
Min.
Max.
2.4
2.2
Output Leakage Current
loz
Icc
7B138-55
7B139-55
-10
-10
+10
+10
0.8
V
+10
!1A
!1A
210
+10
210
250
250
90
95
135
90
95
135
160
15
160
15
30
30
Com'l
130
130
MiVlnd
140
140
rnA
rnA
rnA
rnA
rnA
Capacitance[9]
Parameter
Description
'lest Conditions
Input Capacitance
Output Capacitance
CIN
COUT
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
Unit
10
15
JJF
pF
AC Test Loads and Waveforms
~
R1 = 893Q
OUTPU
C = 30 pF
I
_
-
-
R2 = 347Q
OUTPUT
OUTPUT:rl
C=30pF
I
C = 5 pF
-=-
VTH = 1.4V
(b) Thevenin Equivalent (Load 1)
(a) Normal Load (Load 1)
8138-3
I
C =30pF
8138-4
Load (Load 2)
,OV~90%
GND~3ns ....
~
....
8138-6
_3ns
8138-7
Note:
9. Tested initially :n:.d after any dcsigri or process chaHgc~ thai may affeci
these parameters.
6-80
I
_
-
-
R2 = 34m
(e) Three-State Delay (Load 3)
ALL INPUT PULSES
OUTPU~
:rl
R1 = 893Q
RTH = 250Q
8138-5
CY7B138
CY7B139
Switching Characteristics Over the Operating Range[7, lOJ
Parameter
READ CYCLE
Description
tRC
tAA
tOHA
tACE
tOOE
tLZOE111. UJ
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
~W'0Elll,
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
tpu
CE HIGH to Power-Down
tpo
WRITE CYCLE
Write Cycle Time
twc
CE LOW to Write End
tSCE
Address Set-Up to Write End
tAW
Address Hold From Write End
tHA
Address Set-Up to Write Start
tSA
Write Pulse Width
tpWE
Data Set-Up to Write End
tso
Data Hold From Write End
tHO
tHZWEllLJ
R/W LOW to High Z
tLZWEl12j
R/W HIGH to Low Z
Write Pulse to Data Delay
twoo l15j
Write Data Valid to Read Data Valid
tooo1"'J
BUSY TIMINGl14j
tLZCEI , iLJ
tHZCEllI,12j
7B138-15
7B139-15
Min. Max.
15
7B138-25
7B139-25
Min. Max.
25
15
3
35
25
25
15
10
0
10
30
25
3
0
15
0
55
55
40
40
2
0
30
20
0
20
3
50
30
25
35
35
30
30
2
0
25
15
0
3
3
25
20
25
25
20
20
2
0
20
15
0
55
25
3
3
0
15
12
12
2
0
12
10
0
3
20
15
15
55
35
20
15
3
3
55
3
3
10
7B138-55
7B139-55
Min. Max.
35
3
3
15
10
3
7B138-35
7B139-35
Min. Max.
25
3
60
35
70
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY LOW from Address Match
45
ns
20
15
20
tBLA
BUSY HIGH from Address Mismatch
15
20
20
40
ns
tBHA
40
BUSY LOW from CE LOW
15
20
20
ns
tBLC
BUSY HIGH from CE HIGH
20
20
35
ns
15
tBHe
5
5
5
ns
Port Set-Up for Priority
5
tps
R!W LOW after BUSY LOW
0
0
0
0
ns
tWB
R!W HIGH after BUSY HIGH
13
20
30
40
ns
tWH
tBOOP)j
BUSY HIGH to Data Valid
Note 15
Note 15
Note 15
ns
Note 15
INTERRUPT TIMING114j
INT Set Time
25
15
25
tINS
I 30 I ns
INT Reset Time
15
25
25
30
ns
tINR
SEMAPHORE TIMING
SEM Flag Update Pulse (OE or SEM)
10
10
15
20
ns
tsop
SEM Flag Write to Read Time
ns
5
5
5
5
tSWRO
SEM Flag Contention Window
5
5
5
5
ns
tsps
Notes:
10. Test conditions assume signal transition time of3 ns oriess, timing ref12. Test conditions used are Load 3.
erence levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading 13. For information on part-to-part delay through RAM cells from writof the specified Im/IoH and 30-pF load capacitance.
ing port to reading port, refer to Read Timing with Port -to-Port Delay
11. At any given temperature and voltage condition for any given device,
waveform.
tHZCE is less than tLZCE and tHZOE is less than tLZOE.
14. Thst conditions used are Load 2.
6-81
CY7B138
CY7B139
arcYPRESS
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)[16, 17]
ADDRESS
DATA OUT
8138-8
Read Cycle No.2 (Either Port CE/OE Access) [16,18,19]
SEIiil or CE ~
~
\..
1s
r
tLZCE
DATA OUT
ICC
-
tpu
~tHZCE-
tACE
IHZOE
tOOEtLZOE
..,~// / / / / /
~"
r-
-'
DATA VALID
" """
":l
_tpo
/I
ISB~'
Read Timing with Port-to-Port Delay (MIS = L)[20, 21]
twc
ADDRESSR
)~
~(
MATCH
IpWE
~~
/
_ISO
DATAINR
ADDRESSL
~~
)~
VALID
~"
MATCH
tODD
)~
DATAOUTL
-
-:J~
tWDD
-
8138 10
Notes:
15. taDD is a calculated parameter and is the greater of tWDD - tpWE
(actual) or tDDD - tSD (actual).
16. R/W is HIGH for read eyele.
17. Device is continuously selected CE = LOW and OE = LOW. This
waveform cannot be used for semaphore reads.
18. Address valid prior to or coincident with CE transition LOW.
19. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when
accessing semaphores.
20. BUSY = HIGH for the writing port.
21. CEL = CER = LOW.
6-82
CY7B138
CY7B139
~-......"..
=r............_.~
~'CYPRESS
Switching Waveforms (continued)
Write Cycle No.1: OE Three-States Data I/Os (Either Port) [22, 23, 24]
~------------------------twc--------------------------~
ADDRESS
tAW
R/W ---+---~----.
~-----------tpWE--------------~
E
DATA IN - - - - - - - - - - - - - - - - -
HIGH IMPEDANCE
---------
.1.
tSD
DATA VALID
tHD~
~-------
~
8138-11
Write Cycle No.2:
RiW Three-States Data I/Os (Either Port)[22, 24, 25]
~--------------------twc--------------------------~
ADDRESS
SEMORCE
R/W
~.~-----tSA------~~~--------
DATA IN
DATA OUT
8138-12
Notes:
22. The internal write tim"-2f the memory is defmed by the overlap of CE
or SEM LOW and R/W LOW Both signals must be LOW to initiate
a write, and either signal can terminate a write by going HIGH. The
data input set-up and hold timing should be referenced to the rising
edge ofthe signal that terminates the write.
23. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tpWE or (tHzWE + tSD) to allow the I/O
driversJQ. tum off and data to ~ placed on the bus for the required
tSD' If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as
short as the specified tpWE.
24. R/W must be HIGH during all address transitions.
25. Data I/O pins enter high impedance when OE is beld LOW during
write.
6-83
CY7B138
CY7B139
=--~
~~CYPRESS
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[26j
1/0 0
DATAouT VALID
R/W
---*'f----IDOE
---I
8138-13
Timing Diagram of Semaphore Contention[27, 28, 29]
__________________________--J)(~___________
B138-14
Notes:
26. CE = HIGH for the duration ofthe above timing (both write and read
cycle).
27. IIOOR = IIOOL = LOW (request semaphore); CER = CEL = HIGH
28. Semaphores are reset (available to both ports) at cycle start.
29. If tsps is violated, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control the
semaphore.
6-84
CY7B138
CY7B139
-,~
~'CYPRESS
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[21j
Iwe
ADDRESSR
'{
"-
)(
MATCH
,
IpWE
}~
I---tSD
~(
DATAINR
Ips
ADDRESSL
¥
VALID
~D
1--00
~
MATCH
tBLA
]C
IBDD_
tDDD
~~
DATAOUTL
E
tWDD
8138-15
Write Timing with Busy Input (M/S=WW)
8138-16
6-85
CY7B138
CY7B139
'rcYPRESS
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[30j
CEL Valid First:
X
ADDRESSL,R
X
ADDRESS MATCH
1.,\:
CEL
CER
tSLC~
BUSYR
CER Valid First:
X
ADDRESSL,R
CEL
tSLC~
BUSYL
8138-17
X
ADDRESS MATCH
1,,\:
CER
t~'1
t~'1
6138-18
Busy Timing Diagram No.2 (Address Arbitration)[30j
Left Address Valid First:
tRcortWC
(
ADDRESSL
(
ADDRESS MATCH
ADDRESS MISMATCH
_tps-
~~
ADDRESS R
I4-tSLA
BOSYR
::j_~,-}
--Jj
I--tBHA
B138-19
Right Address Valid First:
tRC ortwc
ADDRESSR
~lC
)(
ADDRESS MATCH
ADDRESS MISMATCH
I«--tps_
ADDRESSL
~~
--=j-~--I4-tBLA
BOSYL
I--tsHA
~
~
Note:
30. Iftps is viulal~t.i, ihe busy signai will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
6-86
8138-20
CY7B138
CY7B139
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
~--------- twe
ADDRESSL
WRITE FFF
f
----1"------------------------
t1NS[32]
Right Side Clears INTR :
ADDRESSR
~ ~
tRe
_~
XXXXXXXXXXXXXX ____
RE_AD_FF_F
K
GER
8138-21
_______
,-------------
~
INTR
8138-22
Right Side Sets INTL:
~-------
ADDRESSR
twe
---------.j
WRITEFFE
1---
t1NS[32]
- - - . p ' -______________________
8138-23
Left Side Clears INTL
AD"'..,
XXXXXXXXXXXXXXf_R_~_~eF_FE_*---
GEL
.JK
R!WL
////}I'
L
OE
INh
~
' "" " "" " "" " "
r\.
/~
8138-24
Notes:
31. tHA depends on which enable pin (CEL or RfWLl is deasserted first.
32. tINS or tINR depends on which enable pin (CEL or RiWLl is asserted
last.
6-87
CY7B138
CY7B139
Architecture
Master/Slave
The CY7B 138/9 consists of an array of 4K words of 8/9 bits each of
dual-J2£!:t RA~ cells, I/O and address lines, and control signals
(CE, OE, R/W). These control pins permit independent access for
reads or writes to any location in memory. Th handle simultaneous
writes/reads to the same location, a BUSY pin is provided on each
port. Tho interrupt (INT) pins can be utilized forport-to-portcommunication. Tho semaphore (SEM) control pins are used for allocating shared resources. With the MiS pin, the CY7B138/9 can
function as a master (BUSY pins are outputs) or as a slave (BUSY
pins are inputs). The CY7B138/9 has an automatic power-down
feature controlled byCE. Each portis provided with its own output
enable control (OE), which allows data to be read from the device.
A MIS pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will
allow the device to interface to a master device with no external
components. Writing of slave devices must be delayed until after
the BUSY input has settled. Otherwise, the slave chip may begin a
write cycle during a contention situation. When presented as a
HIGH input, the M/S pin allows the device to be used as a master
and therefore the BUSY line is an output. BUSY can then be used
to send the arbitration outcome to a slave.
Semaphore Operation
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge of
R/W in order to guarantee a valid write. A write operation is controlled by either the OE pin (see Write Cycle No.1 waveform) or
the R/W pin (see Write Cycle No. 2waveform). Data can be written
to the device tHZOE after the OE is deasserted or tHZWE after the
falling edge of R/W. Required inputs for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tDDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and CE
pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user of the CY7B138/9 wishes to access a se~hore
flag, then the SEM pin must be asserted instead of the CE pin.
Interrnpts
The interrupt flag (INT) permits communications between
ports. When the left port writes to location FFF, the right port's interrupt flag (INfR) is set. This flag is cleared when the ris!!!..Port
reads that same location. Setting the left port's interrupt flag (INTdis
accomplished when the right port writes to location FFE. This flag
is cleared when the left port reads location FFE. The message at
FFF or FFE is user-defined. See Table 2 for input requirements for
INT. INTR and INTLare push-pull outputs and do not require pullup resistors to operate. BUSYL and BUSY R in master mode are
push-pull outputs and do not require pull-up resistors to operate.
Busy
The CY7B138/9 provides on-chip arbitration to alleviate simultaneous memory location access (contention). Ifboth ports' CEs are
asserted and an address match occurs within tps of each other the
Busy logic will determine which port has access. If tps is violated,
one port will definitely gain permission to the location, but it is
not guaranteed which one. BUSY will be asserted tBLA after an
address match or tBLC after CE is taken Law.
The CY7B138/9 provides eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used
to reserve resources that are shared between the two ports. The
state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a
latch by writing a zero to a semaphore location. The left port then
verifies its success in settin.£.!!1e latch by reading it. After writing
to the semaphore, SEM or OE must be deasserted for tsop before
attempting to read the semaphore. The semaphore value will be
available tSWRD + tDOE after the rising edge of the semaphore
write. If the left port was successful (reads a zero), it assumes control over the shared resource, otherwise (reads a one) it assumes
the right port has control and continues to poll the semaphore.When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the a semaphore.If the left side no longer requires the
semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM Law. The SEM pin
functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). Ao-2 represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access.When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only 1/00 is used. If a zero is written to the left port of an unused semaphore, a one will appear at the
same semaphore address on the right port. That semaphore can
now only be modified by the side showing zero (the left port in this
case). If the left port now relinquishes control by writing a one to
the semaphore, the semaphore will be set to one for both sides.
However, if the right port had requested the semaphore (written a
zero) while the left port had control, the right port would immediatelyown the semaphore as soon as the left port released it. Table
3 shows sample semaphore operations.
When reading a semaphore, all eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the
other port. If both ports attempt to access the semaphore within
tsps of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
Initialization of the semaphore is not automatic and must be reset
during initialization program at power-up. All semaphores on both
sides should have a one written into themn at initialization from
both sides to assure that they will be free when needed.
6-88
CY7B138
CY7B139
-,,~
-==-' - ;
CYPRESS
Table 1. Non-Contending Read/Write
Outputs
Inputs
CE
R/W OE
SEM
1/0 0-7
Operation
H
X
X
H
HighZ
Power-Down
H
H
L
L
Data Out
Read Data in
Semaphore
I/O Lines Disabled
X
X
H
X
HighZ
H
S
X
L
Data In
Write to Semaphore
L
H
L
H
Data Out
Read
Data In
Write
L
L
X
H
L
X
X
L
Illegal Condition
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)
Function
Set Left INT
Reset Left INT
Set Right INT
Reset Right INT
R/W
X
X
L
X
CE
X
L
L
X
Left Port
OE Ao-n
X
X
FFE
L
X
FFF
X
X
INT
L
H
X
X
R/W
L
X
X
X
CE
L
X
X
L
Right Port
OE Ao-n
X
FFE
X
X
X
X
L
FFF
INT
X
X
Table 3. Semaphore Operation Example
Function
I/O 0 Left
1
I/O 0 Right
1
Left port writes semaphore
0
1
Left port obtains semaphore
Right port writes 0 to semaphore
0
1
Right side is denied access
Left port writes 1 to semaphore
1
0
Right port is granted access to semaphore
Left port writes 0 to semaphore
1
0
No change. Left port is denied access
Right port writes 1 to semaphore
0
1
Left port obtains semaphore
Left port writes 1 to semaphore
1
1
No port accessing semaphore address
Right port writes 0 to semaphore
1
0
Right port obtains semaphore
Right port writes 1 to semaphore
1
1
No port accessing semaphore
Left port writes 0 to semaphore
0
1
Left port obtains semaphore
Left port writes 1 to semaphore
1
1
No port accessing semaphore
No action
6-89
Status
Semaphore free
L
H
CY7B138
CY7B139
ll?cYPRESS
'iYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
.,.
Jl1.2
lee~"""
j
1.0
fa
0.8
N
........
.,.V
1.2
I!J
:::;
:::;
~ 0.6
ala:
0.8
0.0
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE
0.6
M
1.3
:<
a:
1.1
I......
...........
0 1.0
z
~
0.8
4.0
4.5
--
5.0
I--
5.5
SUPPLY VOLTAGE
!z
a:.::a:
1.0
z
i
0 .75
I!J
~0.50
a:
oz
0.25
0.0
o
-I---V
1.0
2.0
3.0
SUPPLY VOLTAGE
-
l.--""'
Vee = 5.0V
0.6
-55
25
40
20
3.0
4.0
5.0
M
I
/
o II
0.0
125
1.0
2.0
Vee = 5. V_
TA = 25°
"I
3.0
4.0 5.0
OUTPUT VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT WADING
M
NORMALIZED Icc vs. CYCLE TIME
1.25
25.0
'iii"
&20.0
~ 15.0
V ...
'-'
w
010.0
V
o1/
o
--
Vee = 4.5V
TA = 25°C
5.0
M
~
30.0
5.0
"'\."
/
60
::l
:1
4.0
Z
1i5
AMBIENT TEMPERATURE (0G)
I
II
2.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
80
o
/
1.0
~ 100
0.8
6.0
o
OUTPUT VOLTAGE
j1.4
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
I
0
<" 140
M
1.00
o~
Vee = 5.0V
TA= 25°C
1\
~ 40
o
!5~
1\\
.s 120
~ 1.2
TA = 25°C
0.9
0
g
1.6
0 1.2
w
~
;:)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
«
~ 80
Vee = 5.0V
VIN = 5.0V
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
j
u 120
w
0.6.'::-------:!:=-----:-;!
-55
25
125
AMBIENT TEMPERATURE (0G)
6.0
\
;:)
0.21------+-----1
0.2
160
a:
ISB3
~
a: 0.4
oz
~ 0.4
g 200
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
I-
"'
.!!?
~
o
ISB3
~
I
o
I!J
1.0
~
a:
~0.751----+""''''---j---~
_
I
200 400 600 800 1000
CAPACITANCE (pF)
6-90
Vee = 5.0V
TA = 25°C
VIN = 0.5V
Jl
28
40
CYCLE FREQUENCY (MHz)
66
CY7B138
CY7B139
=&&1:rcYPRESS
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package 1Ype
Operating
Range
15
CY7B138-15JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
25
CY7B138-25JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7B138-25JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7B138- 25LMB
L81
68-Square Leadless Chip Carrier
Military
CY7B138-35JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7B138-35JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7BI38-35LMB
L81
68-Square LeadIess Chip Carrier
Military
CY7B138-55JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7B138-55JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
Package
1Ype
Package 1YPe
Operating
Range
35
55
Speed
(ns)
Ordering Code
15
CY7B139-15JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
25
CY7B139-25JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7B139-25JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7B139-25LMB
LSI
68-Square Leadless Chip Carrier
Military
CY7B139-35JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7B139-35JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7B139-35LMB
LSI
68-Square Leadless Chip Carrier
Military
CY7B139-55JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7B139-55JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
35
55
I
6-91
-:a~YPRESS
CY7B138
CY7B139
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
VOL
1,2,3
tRC
7, 8,9, 10, 11
VIH
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
tOHA
7, 8, 9, 10, 11
IIX
1,2,3
tACE
7, 8, 9, 10, 11
Ioz
1,2,3
tDoE
7, 8, 9, 10, 11
ICC
1,2,3
WRITE CYCLE
ISB!
1,2,3
twc
7, 8, 9, 10, 11
ISB2
1,2,3
tSCE
7, 8, 9, 10, 11
ISB3
1,2,3
tAW
7, 8, 9, 10, 11
ISB4
1,2,3
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7,8,9,10,11
tHD
7, 8, 9, 10, 11
BUSY/INTERRUPT TIMING
tBLA
7, 8, 9, 10, 11
tBHA
7, 8, 9, 10, 11
tBLC
7, 8, 9, 10, 11
tBHC
7,8,9,10,11
tps
7, 8, 9, 10, 11
tINs
7, 8, 9, 10, 11
tINR
7, 8, 9, 10, 11
BUSY TIMING
tWB
7, 8, 9, 10, 11
tWH
7, 8, 9, 10, 11
tBDD
7, 8, 9, 10, 11
tDDD
7,8,9,10,11
tWDD
7, 8, 9, 10, 11
Document #: 38-00162-G
6-92
CY7B144
CY7B145
8Kx 8/9 Dual-Port Static RAM
with Sem, lnt, Busy
Features
Functional Description
• O.S-micron BiCMOS for high
performance
• High-speed access
-15 ns (commercial)
- 25 ns (military)
The CY7B144 and CY7B145 are highspeed BiCMOS 8K x 8 ~nd 8K x d~al
port static RAMs. Vanous arbitration
schemes are included on the CY7B144/5
to handle situations when multiple processors access the same piece of data. Two
ports are provided permitting independent, asynchronous access for reads and
writes to any location in memory. The
CY7B144/5 can be utilized as a standalone 64-Kbit dual-port static RAM or
multiple devices can be combined in order
to function as a 16/18-bit or wider master/
slave dual-port static RAM. An MIS pin is
provided for implementing 16/18-bit or
wider memory applications without the
need for separate master and slave devices
or additional discrete logic. Application
areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.
?
• Automatic power-down
• Fully asynchronous operation
• Master/Slave select pin allows bus
width expansion to 16/18 bits or more
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking between ports
• INT flag for port-to-port
communication
• Available in 68-pin LCCIPLCC, 64-pin
and 80-pin TQFP
• TTL compatible
• Pin compatible and functionally
equivalent to IDT7005 and IDT7015
Each port has independent control pins:
chi£.:nable (CE), read or write enable
(R/W), and output enable (OE). Two
flags, BUSY and INT, are provided on
each port. BUSY signals that the port is
trying to access the same location currently being accessed by the other port. The
interrupt flag (INT) permits communication between ports or systems by means of
a mail box. The semaphores are used to
pass a flag, or token, from one port to th.e
other to indicate that a shared resource IS
in use. The semaphore logic is comprised
of eight shared latches. Only one side can
control the latch (semaphore) at any time.
Control of a semaphore indicates that a
shared resource is in use. An automatic
power-down feature is controlled independently on each port by a chip enable
(CE) pin or SEM pin.
The CY7B144 and CY7B145 are available
in 68-pin LCCs, PLCCs, 64-pin (CY7Bl44)
and 80-pin TQFP (CY7B145).
Logic Block Diagram
RmL~~~~~~~______________1
RmA
"CE A
OEA
A12A
Al0R
(76145)
:;g~ ----A~-tr;r;'t_l-L..=~=--_r.;---1
1/08A (76145)
·•
•
11'----''11
I/0 7R
IfOOR
OOSYR[1,2j
AOL
••--t----+L____
·
·••
MEMORY
ARRAY
.J
cr L
AoA
A12R
A12L
AoL
AgA
INTERRUPT
SEMAPHORE
AR61TRAnoN
OEL
AoA
crA
DEA
AmL
AmA
~L ------------~
iNfL[2]
6144-1
MiS
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2.
6-93
Master: push-pull output and requires no pull-up resistor.
I
CY7B144
CY7B145
iS~YPRESS
Pin Configurations
68·Pin LCC/PLCC
ThpView
-;:!i5SE
1....i..J
O...J....J....J.
gg zo
0lw'~ IW
000
ozz>..(".«
N
9 8 7 6
I/0 2L
I/03l
1/0 4l
I/OSl
GND
I/Oel
I/0 7L
Vee
GND
VOOR
I/O,.
I/O'R
Vee
1/03R
1/04R
I/OSA
l/°eR
-
0
i>i>/J!l
5 4 3 2 1 68 6766 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
60
59
58
57
56
55
54
53
52
51
50
CY7B144/5
20
Asl
~l
Aal
A'l
A,l
Aol
WTl
l!US'Il
GND
MIS
BOSYR
21
22
49
48
AoR
23
47
46
45
44
AIR
A'R
24
25
26
B~~~~~roM~~U~~~~.~
D:M'
a: a: a:
0:0 (,) C
WTR
AoR
~R
c:: a: a: a: a: a: cr a:
~~~~@~ZZ~;~;~~~~~
B144-2
64-PinTQFP
ThpView
I/O'l
~l
1/0 3l
Aal
A2l
All
Aol
1/04L
I/O'l
GND
I/Oel
I/O'l
Tml
Vee
GND
lIDSI'l
GND
MIS
I/OOR
I/0 1R
I/O'R
l!US'IR
WTR
Vee
1/03R
1/04R
A,.
I/O'R
~R
AoR
A'R
AaR
Notes:
3.
4.
IjOSR on the CY7B145.
I/OSL on the CY7B145.
6-94
=:.
CY7B144
CY7B145
?cYPRESS
Pin Configurations (continued)
80-PinTQFP
Top View
I/0 1L
I/0 2L
A5l
I/0 3L
I/0 4L
A3l
I/OSL
A2l
NC
A.,c
A,"
GND
1/00l
Aol
1/0 7l
Vee
GND
BUSYl
GND
INTl
flOOR
MiS
II0 1R
1lIJ!l'/R
INTR
I/0 2R
Vee
AOR
V03R
I/0 4R
A'R
A2R
I/OSR
AoR
rloSR
A.,R
I/0 7R
NC
A,R
NC
8144-4
Pin Definitions
Right Port
Left Port
I/OOL-7L(8L)
I/OOR -7R(8R)
AoL-12L
CEL
OEL
AoR-12R
CER
OER
R/WL
SEML
R/WR
SEMR
INTL
INTR
BUSYL
M/S
BUSYR
Vee
GND
Description
Data bus Input/Output
Address Lines
Chip Enable
Output Enable
ReadIWrite Enable
Semaphore Enable. When asserted LOW, allows access to eight sema~hores.
The three least significant bits of the address lines will determine whic semaphore to write or read. The I100 pin is used when writing to a semaphore.
Semaphores are requested by writing a 0 into the respective location.
Interrupt Flag. OOL is set when right port writes location IFFE and is
cleared when left port reads location IFFE. INTR is set when left port writes
location IFFF and is cleared when right port reads location IFFF.
Busy Flag
Master or Slave Select
Power
Ground
6-95
CY7B144
CY7B145
Selection Guide
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
Maximum Standby
Current for ISBl (rnA)
Commercial
78144-15
78145-15
15
78144-25
78145-25
25
78144-35
78145-35
35
78144-55
78145-55
55
260
220
210
210
280
250
Military
Commercial
110
Military
95
90
100
95
90
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Thmperature with
Power Applied ........................ -55°C to + 125°C
Supply Voltage to Ground Potential ......... -0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5V to + 7.0V
DC Input Voltagef5] ...................... -0.5V to + 7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Industrial
-40°C to +85°C
5V ± 10%
Military[6]
-55°C to + 125°C
5V ± 10%
Range
Commercial
Notes:
5. Pulse width < 20 ns.
6.
6-96
TA is the "instant on" case temperature.
CY7B144
CY7B145
==- rcYPRESS
Electrical Characteristics Over the Operating Rangel?]
Description
Parameter
VOH
VOL
Vm
VIL
IIX
Ioz
lee
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Test Conditions
GND.sVI.$Vee
Outputs Disabled, GND .$ Vo .$ V cc
Corn'l
Vee = Max., lOUT = 0 rnA
Outputs Disabled
Mil/lnd
165
Both Ports
CE and CER';:>: VCC - 0.2Y,
VIN';:>: Vee - 0.2V
or VIN .$ 0.2Y, f = 0[8]
Corn'l
15
One Port
CEL or CER';:>: Vee - 0.2Y,
VIN';:>: Vee - 0.2Vor
VIN .$ 0.2Y, Active
Port Outputs, f = fMAX[8]
Corn'l
ISB3
Standby Current
(Both Ports CMOS Levels)
VOH
VOL
Vm
VIL
IIX
Ioz
lee
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
rnA
rnA
rnA
rnA
160
7B144 55
7B145-55
Min.
Max.
2.4
2.4
0.4
-10
-10
0.4
2.2
0.8
+10
+10
210
-10
-10
0.8
+10
+10
210
250
250
Unit
V
V
V
V
!lA
!lA
rnA
90
95
90
95
rnA
135
160
135
160
rnA
Both Ports
CE and CER .;:>: V cc - 0.2Y,
VIN';:>: Vee - 0.2V
or VIN .$ O.2Y, f = 0[8]
Com'!
15
15
rnA
Mil/lnd
30
30
One Port
CELor CER';:>: Vee - 0.2Y,
VIN';:>: Vee - 0.2Vor
VIN .$ 0.2Y, Active
Port Outputs, f = fMAX[8]
Com'!
130
130
MilJInd
140
140
Standby Current
(One Port TIL Level)
CEL or CEr';:>: Vm,
f= fMAX[8
ISB3
Standby Current
(Both Ports CMOS Leve!s)
Notes:
7. See the last page ofthis specification for Group A subgroup testing
Com'!
rnA
Mil/lnd
Com'!
Mil/lnd
ISB2
Standby Current
(One Port CMOS Level)
140
160
7B144 35
7B145-35
Min.
Max.
GND : Vm,
f= fMAX[8]
ISB4
15
Mil/lnd
Test Conditions
0.8
+10
+10
220
95
100
145
180
MilJInd
Vee = Min., IOH = -4.0 rnA
Vee = Min., IOL = 4.0 rnA
Standby Current
(Both Ports TTL Leve!s)
ISB!
-10
-10
Unit
V
V
V
V
280
110
CELorCEr';:>: Vm,
f = fMAX[8
Parameter
0.8
+10
+10
260
MilJInd
Corn'l
Mil/lnd
Standby Current
(One Port TIL Level)
Standby Current
(One Port CMOS Level)
-10
-10
0.4
2.2
Corn'l
ISB2
ISB4
0.4
2.2
CELandCER';:>: VIH,
f = fMAX[8]
7BI44 25
7B145-25
Min.
Max.
2.4
2.4
Vee = Min., IOH = -4.0 rnA
Vee = Min., IOL = 4.0 rnA
Standby Current
(Both Ports TTL Levels)
ISB!
7B144 15
7B145-15
Min.
Max.
8.
information.
6-97
rnA
fMAX = lItRC = All inputs cycling at f = I/tRC (except output enable).
f = 0 means no address or control lines change. This applies only to
inputs at CMOS level standby Isro.
CY7B144
CY7B145
.~YPRESS
Capacitance[9]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
CoUT
Test Conditions
TA = 25°C, f
Vcc = 5.0V
AC Test Loads and Waveforms
I:~:
°"';::"1
OUTPUT
OUTPUT::-rI
C=30pF
J
1
C
:rl
= 5 pF
VTH = 1.4V
1
-=
(b) Thevenin Eqnivalent (Load 1)
R1 = 893Q
R2
= 347Q
-=
(c) Three-State Delay (Load 3)
8144-5
l
pF
pF
5V
RTH = 250Q
(a) Normal Load (Load 1)
OUTPUT
Unit
Max.
10
15
= 1 MHz,
8144-6
Bl44-7
ALL INPUT PULSES
I
C =30 p F
90%
,OV~
10%
~
10%
GND
5.3 ns
5.3 ns
Load (Load 2)
Bl44-8
8144-9
Switching Characteristics Over the Operating Range[7, 10]
Parameter
READ CYCLE
Description
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Output Hold From Address
Change
7B144-15
7B145-15
Min_
Max.
7B144-25
7B14S-2S
Max_
Min.
15
25
15
7Bl44-35
7B14S-3S
Max_
Min.
35
3
55
35
25
3
7Bl44-SS
7B14S-SS
Max_
Min.
3
ns
55
3
tACE
CE LOW to Data Valid
15
25
35
55
OE LOW to Data Valid
10
15
20
25
tHZOE[ll, 12]
OE HIGH to High Z
tLZCE[ll, 12]
CE LOW to Low Z
tHZCE[ll, 12]
CE HIGH to High Z
tpu
CE LOW to Power-Up
tpD
CE HIGH to Power-Down
3
3
10
3
15
3
3
10
20
0
15
0
25
ns
25
ns
25
ns
ns
0
35
ns
ns
3
20
15
0
3
3
ns
ns
tDOE
tLZOE[ll, 12]
OE Low to Low Z
Unit
ns
55
ns
Notes:
9.
Thsted initially and after any design or process changes that may affect
these parameters.
10. Thst conditions assume signal transition time oB ns or less, timing reference levels of 1.Sv, input pulse levels of 0 to 3.0V, and output loading
of the specified Im/10H and 30-pF load capacitance.
11. At any given temperature and voltage condition for any given device,
tHZCE is less than tLZCE and tHZOE is less than tLZOE.
12. Test conditions used are Load 3.
6-98
=-
CY7B144
CY7B145
.,~
';CYPRESS
Switching Characteristics Over the Operating Rangel?, 10] (continued)
Parameter
WRITE CYCLE
Description
7B144-15
7B145-15
Min.
Max.
7B144-25
7B145-25
Min.
Max.
7B144-35
7B145-35
Min.
Max.
7B144-55
7B145-55
Min.
Max.
Unit
twc
Write Cycle Time
15
25
35
55
ns
tSCE
CE LOW to Write End
12
20
30
45
ns
tAW
Address Set-Up to Write End
12
20
30
45
ns
tHA
Address Hold From Write
End
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
Write Pulse Width
12
20
25
40
ns
tso
Data Set-Up to Write End
10
15
15
25
ns
tHO
tHZWE[12]
Data Hold From Write End
0
0
0
0
tLZWE[12]
R/W HIGH to Low Z
tWOO[13]
Write Pulse to Data Delay
R/W LOW to High Z
10
15
3
20
3
3
3
ns
25
ns
ns
30
50
60
70
ns
Write Data Valid to Read
Data Valid
BUSY TIMINGL"]
25
30
35
40
ns
tBLA
BUSY LOW from Address
Match
15
20
20
30
ns
tBHA
BUSY HIGH from Address
Mismatch
15
20
20
30
ns
tooo[13]
tBLC
BUSY LOW from CE LOW
15
20
20
30
ns
tBHe
BUSYHIGHfromCEHIGH
15
20
20
30
ns
tps
Port Set-Up for Priority
5
5
5
5
ns
tWB
R/WLOW after BUSY LOW
0
0
0
0
ns
tWH
R/W HIGH after BUSY
HIGH
13
20
30
30
ns
BUSY HIGH to Data Valid
tBOO
INTERRUPT TIMINGL~']
tINS
INTSetTime
INT Reset Time
tINR
SEMAPHORE TIMING
SEM Flag Update Pulse (OE
tsop
orSEM)
tSWRD
tsps
15
25
35
55
ns
15
25
25
35
ns
15
25
25
35
ns
10
10
15
20
ns
SEMFlag Write to Read Time
5
5
5
5
ns
SEM Flag Contention
Window
5
5
5
5
ns
Notes:
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay
waveform.
14. Thst conditions used are Load 2.
6-99
CY7B144
CY7B145
=--- -.. ~
==:;:'; CYPRESS
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)[15, 16J
ADDRESS
DATA OUT
BI44-10
Read Cycle No.2 (Either Port CE/OE Access)[15, 17, 18J
SEMorCE
~I'..
;;'f
~
I--tHZCE-
tACE
~tLZOE--
tHZOE
tDOE-
tLZCE
DATA OUT
ICC
ISB
-
<'////////
tpu
~
..,
DATA VALID
r-
~tpD
/l
---./ .
Read Timing with Port-to-Port Delay (MIS = L)[19, 20J
twc
ADDRESSR
)K
K
MATCH
tpWE
~~
/
_tSD
DATAINR
ADDRESS L
'K
'd
:f
VALID
MATCH
tDDD
),
DATAOUTL
~
;~
tWDD
B144 - 12
Notes:
15. RiW is HIGH for read cycle.
16. Device is continuously selected CE = WW and OE = Law. This
waveform cannot be used for semaphore reads.
17. Address valid prior to or coincident with CE transition Law.
18. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when
accessing semaphores.
19. BUSY = HIGH for the writing port.
20. CEL = CER = Law.
6-100
CY7B144
CY7B145
'?cYPRESS
Switching Waveforms (continued)
Write Cycle No.1: OE Three-State Data I/Os (Either Port)[21, 22, 23J
~------------------------twc--------------------------~
ADDRESS
,....,~...................'""'
i4_-----------tScE ------------------~~ .J'~'"7"'T'1'~"*'T'1'''r"J~'"7''r
SEMORCE
R/W
__-+___~-_i4-------tpwE ---------t~--------j;::=tSD
DATA IN
------------------~
DATA VALID
.' .. tHD~
~-------
HIGH IMPEDANCE
8144-13
Write Cycle No.2:
RJW Three-State Data I/Os (Either Port)[21, 23, 24J
~--------------------twc----------------------------~
ADDRESS
R/W --------------~~~,
DATA IN
DATA OUT
8144-14
Notes:
21. The internal write tim~fthe memory is defined by the overlap of CE
or SEM LOW and R/W LOW. Both signals must be LOW to initiate
a write, and either signal can terminate a write by going HIGH. The
data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
22. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O
drivers to tum off and data to be placed on the bus for the required
tSD' If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as
short as the specified tpWE'
23. R/W must be HIGH during all address transitions.
24. Data I/O pins enter high impedance when OE is held LOW during
write.
6-101
CY7B144
CY7B145
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[25j
1/00
DATAOUT VALID
R/W
B144-15
Semaphore Contention[26, 27, 28]
~L-A2L _____________________M_A_TC_H______________________J~~____________________
:: ----.. E",,~
MATCH
SEfi.1R
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J
~
B144-16
Notes:
25. (;E = HIGH for the duration of the above timing (both write and read
cycle).
26. IIOOR = IIOOL = LOW (request semaphore); CER = CEL = HIGH
27. Semaphores are reset (available to both ports) at cycle start.
28. If tsps is violated, the semaphore will definitely be obtained by one
side or the other, bnt there is no guarantee which side will control the
semaphore.
6-102
CY7B144
CY7B145
=-~,~
,CYPRESS
Switching Wavefonns (continued)
Read with BUSY (MlS=HIGH)[201
twe
ADDRESS R
;,
tpWE
~"
DATAINR
Ips
ADDRESSL
-
)K
MATCH
)~
~Iso
)~
)
VALID
~"
MATCH
~
tSLA
r--
]2
IBOO_
tO~~
~F
DATAouTL
Iwoo
8144·17
Write Timing with Busy Input (MIS = LOW)
':-f~} -f-~J-8144-18
6-103
CY7B144
CY7B145
#if rcYPRESS
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[29]
CEL Valid First:
X
ADDRESSL,R
X
ADDRESS MATCH
~~k
CEL
CER
tBLC~
BUSYR
CER Valid First:
X
ADDRESSL,R
CEL
tBLC~
BOS'i'L
B144-19
X
ADDRESS MATCH
~~k
CER
t'~1
t'~l
8144-20
Busy Timing Diagram No.2 (Address Arbitration) [29]
Left Address Valid First:
tRcortwC
elK
ADDRESSL
ADDRESS MATCH
ADDRESS MISMATCH
_tps-
~E
ADDRESSR
--1-1....-----tBLA
R
BUSY
-tBHA
8144-21
Right Address Valid First:
tRcortWC
ADDRESSR
)K
ADDRESS MATCH
/ (
ADDRESS MISMATCH
'---tpsADDRESSL
~
1-1
-tBLA
-tBHA
Note:
29. Iftp.dsviolated. the busv siena! will be asserted on one side or the other, hut there is no guanintee on which side BUSY will be asserted
30. IlIA depends on which enable pin (CEk or RiWL) is deasserted first.
31.
6-104
8144-22
IT"," or ITMD deoeods 00 which enahle oio (CR. or R/W. \ is a....rt..cl
last.·· .. • •
• , ~
.~,
CY7B144
CY7B145
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
twc
ADDRESSL
WRITE 1FFF
INi R
tINS[31]
f---
----t:>I.'-___________________
Right Side Clears OOR:
ADDRESSR
tRC
---~~
~::_:_:_
8144-23
..
XXXXXXXXXXXXXX ~R_EA_D _~
Cl::R
~"
1_FF_F
_ _ __
tINR[31]
/ / / /)rt:
K
OE:R
' "' "' "' "'lo
~
fl\IT R
Right Side Sets INTL:
8144- 24
14------- twc - - - - - - - - . ]
ADDRESSR
WRITE 1FFE
Cl::R
14---
tINS[31]
----.f''-_____________________
8144-25
'"
////
tINR[31]
/
'"'"'"'"
"-
/
8144- 26
6-105
CY7B144
CY7B145
Architecture
Master/Slave
The CY7B 144/5 consists of a an array of 8K words of 8/9 bits each
of dual-port RAM cells, I/O and address lines, and control signals
(CE,OE, R/W). These control pins permit independent access for
reads or writes to any location in memory. To handle simultaneous
writes/reads to the same location, a BUSY pin is provided on each
port. Tho interrupt (INT) pins can be utilized for port -to-port communication. Tho semaphore (SEM) control pins are used for allocating shared resources. With the MIS pin, the CY7B144/5 can
function as a Master (BUSY pins are outputs) or as a slave (BUSY
pins are inputs). The CY7B144/5 has an automatic power-down
feature controlled by"CE. Each port is provided with its own output
enable control (00), which allows data to be read from the device.
An MIS pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will
allow the devioe to interface to a master device with no external
components. Writing of slave devioes must be delayed until after
the BUSY input has settled. Otherwise, the slave chip may begin a
write cycle during a contention situation.When presented a HIGH
input, the MIS pin allows the device to be used as a master and
therefore the BUSY line is an output. BUSY can then be used to
send the arbitration outcome to a slave.
Semaphore Operation
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge of
R/W in order to guarantee a valid write. A write operation is controlled by either the OE pin (see Write Cycle No.1 waveform) or
the R/W pin (see Write Cycle No.2 waveform). Data can be written
to the device tHZOE after the OE is deasserted or tHZWE after the
falling edge of R/W. Required inputs for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tDDD
after the data is presented on the other port.
Read Operation
When reading the devioe, the user must assert both the OE and CE
pins. Data will be available tACE after CE or tDOE after OE are asserted. If the user of the CY7B 144/5 wishes to acoess a semaphore
flag, then the SEM pin must be asserted instead of the CE pin.
Interrupts
The interrupt flag (00) permits communications between
ports. When the left port writes to location IFFF, the right port's interrupt flag (INTR) is set. This flag is cleared when the ri8!!!.Port
reads that same location. Setting the left port's interrupt flag (INTd is
accomplished when the right port writes to location IFFE. This
flag is cleared when the left port reads location IFFE. The message
at IFFF or IFFE is user-defined. See Table 2 for input requirements for INT. INTR and INTL are push-pull outputs and do not
require pull-up resistors to operate.
Busy
The CY7B144/5 provides on-chip arbitration to alleviate simultaneous memory location acoess (contention). Ifboth ports' CEs are
asserted and an address match occurs within tps of each other the
Busy logic will determine which port has access. If tps is violated,
one port will definitely gain permission to the location, but it is not
guaranteed which one. BUSY will be asserted tBlA after an address match or tBLC after CE is taken LOW. BUSYLand BUSYR
in master mode are push-pull outputs and do not require pull-up
resistors to operate.
The CY7B144/5 provides eight semaphore latches which are separate from the dual-port memory locations. Semaphores are used
to reserve resources that are shared between the two ports. The
state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a
latch by writing a 0 to a semaphore location. The left port then
verifies its success in settin£!!Ie latch by reading it. After writing
to the semaphore, SEM or OE must be deasserted for tsop before
attempting to read the semaphore. The semaphore value will be
available tSWRD + tDOE after the rising edge of the semaphore
write. If the left port was successful (reads a 0), it assumes control
over the shared resouroe, otherwise (reads a 1) it assumes the
right port has control and continues to poll the semaphore. When
the right side has relinquished control of the semaphore (by writing a 1), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a 1 is
written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM pin
functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). Ao- 2 represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access. When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only 1/00 is used. If a 0 is written
to the left port of an unused semaphore, a 1 will appear at the same
semaphore address on the right port. That semaphore can now only
be modified by the side showing 0 (the left port in this case). If the
left port now relinquishes control by writing a 1 to the semaphore,
the semaphore will be set to 1 for both sides. However, if the right
port had requested the semaphore (written a 0) while the left port
had control, the right port would immediately own the semaphore
as soon as the left port released it. Table 3 shows sample semaphore
operations.
When reading a semaphore, all eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the
other port. If both ports attempt to access the semaphore within
tsps of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
Initialization of the semaphore is not automatic and must be reset
during initialization program at power-up. all Semaphores on both
sides should have a one written into them at initialization from
both sides to assure that they will be free when needed.
6-106
CY7B144
CY7B145
Table 1. Non-Contending Read/Write
Inputs
CE
H
Outputs
R/W
OE
SEM
X
X
H
HighZ
Power-Down
H
H
L
L
Data Out
Read Data in
Semaphore
X
I/O Lines Disabled
1/0 0-7
Operation
X
H
X
HighZ
H
...J
X
L
Data In
Write to Semaphore
L
H
L
H
Data Out
Read
L
L
X
H
Data In
Write
L
X
X
L
Illegal Condition
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)
Right Port
Left Port
R/W
CE
OE
Set Left INT
Reset Left INT
X
X
X
X
Set Right INT
L
X
L
L
X
Function
Reset Right INT
Ao-12
INT
R/W
CE
OE
Ao-12
X
L
L
L
X
1FFE
X
L
X
1FFE
1FFF
H
X
X
L
X
L
X
X
X
X
L
X
X
X
L
L
1FFF
H
X
X
INT
Table 3. Semaphore Operation Example
Function
No action
1/00 Left
1
1/00 Right
1
Status
Semaphore free
Left port writes semaphore
0
1
Left port obtains semaphore
Right port writes 0 to semaphore
0
1
Right side is denied access
Left port writes 1 to semaphore
1
0
Right port is granted access to semaphore
Left port writes 0 to semaphore
1
0
No change. Left port is denied access
Right port writes 1 to semaphore
0
1
Left port obtains semaphore
Left port writes 1 to semaphore
1
1
No port accessing semaphore address
Right port writes 0 to semaphore
1
0
Right port obtains semaphore
Right port writes 1 to semaphore
1
1
No port accessing semaphore
Left port writes 0 to semaphore
0
1
Left port obtains semaphore
Left port writes 1 to semaphore
1
1
No port accessing semaphore
6-107
CY7B144
CY7B145
'lYPicaJ DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
!Jl1.2
lee~
111.0
o 0.8
~
~
0.6
oa:
0.4
Z
.... ~
I--""
--
18B3
1.2
g200
I-
~
o
ia::D
0.8
~
oz
0.0
4.0
4.5
5.0
5.5
UJ
0.6
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
J
1.3
J
0
1.2
UJ
N
N
::J
«
::;
1.1
0
1.0
..........
a:
z
r-........
4.5
a: 1.0
5.0
t--
5.5
Z
V-
0.6
-55
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
I
0 0.75
::J
~0.50
a:
oz
25
-
i3
o
-
I--
60
Z
iii
5
o~
1.0
2.0
3.0
5.0
/
oII
Vee = 5. V _
TA = 25°
1.0
2.0
3.0
4.0
5.0
NORMALIZED Icc vs. CYCLE TIME
5 20.0
fa
~ 10.0
SUPPLY VOLTAGE (V)
20
I
OUTPUT VOLTAGE (V)
_15
.;c 15.0
4.0
40
0.0
25.0
5.0
5.0
4.0
1.25
!:J
V
'"
~
3.0
/'
80
~
125
:J:
1/
0.25
0.0
Vee = 5.0V
Ii)
!
UJ
N
2.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
/
1.0
OUTPUT VOLTAGE (V)
30.0
~
o
AMBIENT TEMPERATURE (0C)
SUPPLY VOLTAGE (V)
1.00
\.
~ 100
0.8
6.0
0
Vee = 5.0V
TA = 25°C
~
1.2
0
40
a:
«
::;
TA = 25°C
0.9
0.8
4.0
--
::J
5
o~
1\\
.s. 120
1.4
0
I......
80
« 140
1.6
1.4
::>
orn
0.21-----l-------l
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
UJ
~
Vee = 5.0V
VIN = 5.0V
0.6 ':-------::'-:-------:-!
-55
25
125
AMBIENT TEMPERATURE (0C)
6.0
\
::>
(,) 120
~ 0.4
0.2
160
a:
ISB3
UJ
I--""
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
~
V
1/
o
o
I--""
V
I--
~a:
Vee = 5.0V
TA = 25°C
VIN = 0.5V
1.0 f----+---+----.,.I
~ 0.751----I~.£.-+_----1
Vee = 4.5V
TA = 25°C
I
_
I
200 400 600 800 1000
CAPACITANCE (pF)
6-108
28
40
CYCLE FREQUENCY (MHz)
66
CY7B144
CY7B145
===--- -,~
=7CYPRESS
Ordering Information
Speed
(ns)
15
25
35
55
Speed
(ns)
15
25
35
55
Ordering Code
CY7BI44-15AC
Package
Name
A65
Package lYPe
64-Lead Thin Quad Flat Pack
Operating
Range
Commercial
CY7B144-151C
181
68-Lead Plastic Leaded Chip Carrier
CY7B144-25AC
A65
64-Lead Thin Quad Flat Pack
CY7B144-251C
181
68-Lead Plastic Leaded Chip Carrier
CY7BI44-25AI
A65
64-Lead Thin Quad Flat Pack
CY7B144-25JI
181
68-Lead Plastic Leaded Chip Carrier
CY7BI44-25LMB
L81
68-Square Leadless Chip Carrier
Military
CY7B144-35AC
A65
64-Lead Thin Quad Flat Pack
Commercial
CY7B144-351C
181
68-Lead Plastic Leaded Chip Carrier
CY7B144-35AI
A65
64-Lead Thin Quad Flat Pack
CY7B144-35JI
181
68-Lead Plastic Leaded Chip Carrier
CY7BI44-35LMB
L81
68-Square Leadless Chip Carrier
Military
CY7BI44-55AC
A65
64-Lead Thin Quad Flat Pack
Commercial
CY7B144-551C
181
68-Lead Plastic Leaded Chip Carrier
CY7BI44-55AI
A65
64-Lead Thin Quad Flat Pack
CY7BI44-55JI
181
68-Lead Plastic Leaded Chip Carrier
Package
Name
Package 1Ype
Ordering Code
CY7B145-15AC
A80
80-Lead Thin Quad Flat Pack
Commercial
Industrial
Industrial
Industrial
Operating
Range
Commercial
CY7B145-151C
181
68-Lead Plastic Leaded Chip Carrier
CY7B145-25AC
A80
80-Lead Thin Quad Flat Pack
CY7B145-251C
181
68-Lead Plastic Leaded Chip Carrier
CY7B145-25AI
A80
80-Lead Thin Quad Flat Pack
CY7BI45-25JI
181
68-Lead Plastic Leaded Chip Carrier
CY7BI45-25LMB
LSI
68-Square Leadless Chip Carrier
Military
CY7B145-35AC
A80
80-Lead Thin Quad Flat Pack
Commercial
CY7B145-351C
181
68-Lead Plastic Leaded Chip Carrier
CY7B145-35AI
A80
80-Lead Thin Quad Flat Pack
CY7B145-35JI
181
68-Lead Plastic Leaded Chip Carrier
Commercial
Industrial
Industrial
CY7B145-35LMB
L81
68-Square Leadless Chip Carrier
Military
CY7B145-55AC
A80
80-Lead Thin Quad Flat Pack
Commercial
CY7B145-551C
181
68-Lead Plastic Leaded Chip Carrier
CY7B145-55AI
A80
80-Lead Thin Quad Flat Pack
CY7B145-55JI
181
68-Lead Plastic Leaded Chip Carrier
6-109
Industrial
CY7B144
CY7B145
cii?cYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
Parameters
Subgroups
VOL
1,2,3
tRC
7, 8, 9, 10, 11
Vm
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
tOHA
7, 8, 9, 10, 11
IIX
1,2,3
tACE
7, 8, 9, 10, 11
Ioz
1,2,3
tDOE
7, 8, 9, 10, 11
WRITE CYCLE
READ CYCLE
Icc
1,2,3
ISBl
1,2,3
twc
7, 8, 9, 10, 11
ISB2
1,2,3
tSCE
7, 8, 9, 10, 11
ISB3
1,2,3
tAW
7, 8, 9, 10, 11
ISB4
1,2,3
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7,8,9,10,11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
BUSY/INTERRUPT TIMING
tBLA
7, 8, 9, 10, 11
tBHA
7, 8, 9, 10, 11
tBLC
7,8,9,10,11
tBHC
7, 8, 9, 10, 11
tps
7, 8, 9, 10, 11
tINS
7,8, 9, 10, 11
tINR
7, 8, 9, 10, 11
BUSY TIMING
tWB
7,8,9,10,11
tWH
7, 8, 9, 10, 11
tBDD
7, 8, 9, 10, 11
tDDD
7, 8, 9, 10, 11
tWDD
7, 8, 9, 10, 11
Document #: 38-00163-G
6-110
PRELIMINARY
CY7C006
CY7C016
16K X 8/9 Dual-Port Static RAM
with Sem, Int, Busy
Features
Functional Description
• CMOS for optimum speed/power
• High-speed access
-15 ns (commercial)
The CY7CO06 and CY7C016 are highspeed CMOS 16K x 8 and 16K x 9 dualport static RAMs. Various arbitration
schemes
are
included
on
the
CY7C006/016 to handle situations when
multiple processors access the same piece
of data. Two ports are provided permitting
independent, asynchronous access for
reads and writes to any location in
memory. The CY7C006/016 can be utilized as a standalone 128-Kbit dual-port
static RAM or multiple devices can be
combined in order to function as a
16-/18-bit or wider master/slave dual-port
static RAM. An MIS pin is provided for
implementing 16-/18-bit or wider memory
applications without the need for separate
master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessordesigns,communications status buffering, and
dual-port video/graphics memory.
•
•
•
•
•
•
•
•
•
•
•
Low operating power: 140 rnA (typ.)
Automatic power-down
Fully asynchronous operation
Master/Slave select pin allows bus
width expansion to 16/1S bits or more
Busy arbitration scheme provided
Semaphores included to permit software handshaking between ports
INT flag for port-to-port communication
Available in 6S-pin PLCC; SO-pin
(7COI6) and 64-pin (7C006) TQFP
TTL compatible
Capable of withstanding greater than
2001VESD
Pin compatible and functional equivalent to IDT7006 and IDT7016
Each port has independent control pins:
chi£..enable (CE), read or write enable
(R/W), and output enable (DE). Two
flags, BUSY and INT, are provided on
each port. BUSY signals that the port is
trying to access the same location currently being accessed by the other port. The
interrupt flag (INT) permits communication between ports or systems by means of
a mail box. The semaphores are used to
pass a flag, or token, from one port to the
other to indicate that a shared resource is
in use. The semaphore logic is comprised
of eight shared latches. Only one side can
control the latch (semaphore) at any time.
Control of a semaphore indicates that a
shared resource is in use. An automatic
power-down feature is controlled independently on each port by a chip enable
(CE) pin or SEM pin.
The CY7C006 and CY7C016 are available
in 68-pin PLCCs, and 80-pin (7C016)
TQFP and 64-pin (7C006) TQFP.
Logic Block Diagram
RmL
lr~==~)-------------~
CEL ~~~=>
DEL -
A13L
A10L
(7C016)
:;g~~
____________
RmR
~
CER
DER
::===t=:;-l
A 13R
A10R
:-____-J~...r,~l-,...L=~::-:---~....J
:
I/OoL:.---------+l~.J-_I.
1/08R (7C016)
I/0 7R
VL------~
____- r____...J
I/OOR
BTISYR[1,2]
=LI:;.1,::,21....________________--I
A9L
AOL
.•
--I-----~r--------'
MEMORY
ARRAY
---i-----.-{.---------.J
AgR
AnA
INTERRUPT
SEMAPHORE
ARBITRATION
L ----------------------~
mSEM
LI2)
C006-1
Notes:
L
BUSY is an output in master mode and an input in slave mode.
2.
6-111
Master: push-pull output and requires no pull-up resistor.
Ii)
.~YPRESS
CY7C006
CY7C016
PRELIMINARY
Pin Configurations
68·Pin LCC/pLCC
Top View
AsL
~L
AsL
A2L
A"
!\oL
/NT,
IlOS'IL
CY7C006/16
GND
MiS
IlOS'IR
/NTR
!\oR
A'R
CDD6-2
64·PinTQFP
Top View
~,
AsL
A2'
A"
AOL
/NT,
IlOS'IL
GND
MiS
COO6-3
Notes:
3. I/O for 7C016 only.
6-112
~
PRELIMINARY
:'rcYPRESS
CY7C006
CY7C016
Pin Configurations (continued)
80-PinTQFP
Top View
N/C
I/0 1L
I/0 2L
ASL
AIL
AoL
I/0 3l
I/o4L
I/OSL
A2L
GND
A1L
I/OSl
AOL
I/0 7L
Tl'lTL
I!iJSYL
Vee
GND
GND
MiS
I/OOR
I!iJSYR
Tl'lTR
I/OtR
I/0 2R
Vee
AsR
1/0",
A1R
I/0 4R
A2R
1/0sR
1/0 6R
A'R
1/0 7R
AsR
N/C
N/C
A4R
Pin Definitions
Left Port
I/OOL-7L(SL)
AoL-13L
CEL
OEL
RfWL
SEML
Right Port
IIOOR -7R(SR)
AoR-13R
CER
OER
RfWR
SEMR
INTL
INTR
BUSYL
M/S
BUSYR
Vee
GND
Description
Data Bus Input/Output
Address Lines
Chip Enable
Output Enable
ReadfWrite Enable
Semaphore Enable. When asserted LOW, allows access to eight semaphores.
The three least significant bits ofthe address lines will determine which semaphore to write or read. The I/Oo pin is used when writing to a semaphore.
Semaphores are requested by writing a 0 into the respective location.
Interrupt Flag. INTL is set when right port writes location 3FFE and is
cleared when left port reads location 3FFE. INTR is set when left port writes
location 3FFF and is cleared when right port reads location 3FFF.
Busy Flag
Master or Slave Select
Power
Ground
6-113
CY7C006
CY7C016
PRELIMINARY
Selection Guide
7(:006-15
7C016-15
15
7COO6-25
7C016-25
25
7C006-35
7C016-35
35
7C006-55
7C016-55
55
Maximum 03erating
Current (rnA
260
220
210
200
Maximum Standby
Current for ISBI (rnA)
70
60
50
40
Maximum Access Time (ns)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................... -65°C to + 150°C
Ambient Thmperature with
Power Applied ........................ -55°C to + 125°C
SupplyVoJtage to Ground Potential ......... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -0.5V to +7.0V
DC Input Voltagel4j ..•...•.......•.•..... -O.5V to +7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Static Discharge Voltage ........................ >200lV
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Range
Commercial
Industrial
6-114
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
-40°C to +85°C
5V ± 10%
CY7C006
CY7C016
PRELIMINARY
Electrical Characteristics Over the Operating Range[S]
Parameter
VOH
VOL
VIH
VIL
IIX
loz
Icc
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
7COO6-15
7C016-15
Min. Typ. Max.
Test Conditions
0.4
2.2
GND~VI~Vee
Outputs Disabled, GND ~ Vo ~ Vee
Com'l
Vee = Max., lOUT = 0 rnA
Outputs Disabled
Ind
ISB!
Standby Current
(Both Ports TTL Levels)
CEL and CER ~ VIH,
f= fMAX[6]
ISB2
Standby Current
(One Port TTL Level)
CEL or CEr ~ VIH,
f = fMAX[7
Standby Current
(Both Ports CMOS
Levels)
Both Ports
CE and CER ~ Vee - 0.2Y,
VIN ~ Vee - 0.2V
or VIN ~ 0.2Y, f = 0[7]
Com'l
Standby Current
(One Port CMOS Level)
One Port
CEL or CER ~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
VIN ~ 0.2Y, Active
Port Outputs, f = fMAX[7]
Com'l
ISB3
ISB4
Parameter
VOH
VOL
Vrn
VIL
IIX
loz
Icc
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
2.4
2.4
Vee = Min., IOH - -4.0 rnA
Vee - Min., IOL - 4.0 rnA
7COO6-25
7C016-25
Min. tYp. Max.
2.2
270
40
40
60
75
130
50
70
110
170
90
90
3
3
15
100
150
Ind
7COO6-35
7C016-35
Min. tYP· Max.
Test Conditions
160
170
-10
-10
Ind
2.4
Vee - Min., IOH - -4.0 rnA
Vee = Min., IOL = 4.0 rnA
160
0.8
+10
+10
220
0.8
+10
+10
260
-10
-10
Com'l
Ind
Com'l
Ind
0.4
3
15
80
120
80
130
7COO6-55
7C016-55
Min. Typ. Max.
2.4
0.4
0.4
2.2
2.2
GND~VI~Vee
Outputs Disabled, GND ~ Vo ~ Vee
Com'l
Vee = Max., lOUT = 0 rnA
Outputs Disabled
Ind
150
15
150
0.8
+10
+10
210
150
250
140
30
50
65
20
20
120
130
15
70
70
3
55
100
115
15
-10
-10
-10
-10
140
~
~
rnA
rnA
rnA
rnA
rnA
Unit
V
V
V
V
~
~
rnA
240
40
rnA
CEL and CER ~ VIH,
f = fMAX[7]
Com'l
Ind
ISB2
Standby Current
(One Port TTL Level)
CEL or CEr ~ VIH,
f = fMAX[7
ISB3
Standby Current
(Both Ports CMOS
Levels)
Both Ports
CE and CER ~ Vee - 0.2Y,
VIN ~ Vee - 0.2V
or VIN ~ 0.2Y, f = 0[7]
Com'l
Ind
Com'l
30
80
80
3
Ind
3
15
3
15
Standby Current
(One Port CMOS Level)
One Port
CEL or CER ~ Vee - 0.2Y,
VIN ~ Vee - O.2Vor
VIN ~ 0.2Y, Active
Port Outputs, f = fMAX[7]
Com'l
70
100
60
90
Ind
70
110
60
95
ISB4
V
V
V
V
0.8
+10
+10
200
Standby Current
(Both Ports TTL Levels)
ISBl
Unit
rnA
rnA
rnA
Notes:
5.
6.
Pulse width < 20 ns.
See the last page of this specification for Group A subgroup testing information.
7.
6-115
litRe = Allinputs cycling at f = litRe( except output enable).
f = 0 means no address or control lines change. This applies only to
inputs at CMOS level standby ISB3.
fMAX =
CY7C006
CY7C016
PRELIMINARY
Capacitance[8]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
'lest Conditions
TA = 25°C, f
Vcc = 5.0V
= 1 MHz,
AC Test Loads and Waveforms
:rl
R1 = 893Q
RTH = 250Q
r
OUTPUT~
OUTPUT
-=
R2=347Q
C=30pF
-=
(a) Nonnal Load (Load 1)
l
OUTPUT
1
10
pF
C
:rl
= 5 pF
VTH = l.4V
(b) Thevenin Equivalent (Load 1)
J
-=
R1 = 893Q
= 347Q
R2
(c) Three-State Delay (Load 3)
C006-6
COOS-5
OUTPUT
Unit
pF
5V
5V
C=30 PF I
Max.
10
CO06-7
ALL INPUT PULSES
I
~
10%
C =30 PF
....
Load (Load 2)
.$.3n5
coos-a
COO6-9
Switching Characteristics Over the Operating Rangd7,8]
Parameter
READ CYCLE
Description
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
tACE
CE LOW to Data Valid
tDOE
tLZOE[8,9]
OE LOW to Data Valid
tHZOE[lO,ll]
OE HIGH to High Z
tLZCE[lO,ll]
CE LOW to Low Z
tHZCE[lO,ll]
CE HIGH to High Z
tpu
CE LOW to Power-Up
tpD
CE HIGH to Power-Down
OE Low to Low Z
7COO6-1S
7C016-1S
Min.
Max.
15
7COO6-2S
7C016-2S
Min.
Max.
25
15
35
25
3
3
10
13
20
3
15
10
3
3
10
0
15
ns
ns
25
0
35
ns
ns
25
15
ns
ns
3
0
25
55
25
15
15
0
ns
3
3
Unit
55
3
35
I
ns
55
3
3
3
7COO6-SS
7C016-SS
Min.
Max.
35
25
15
Notes:
8. Thsted initially and after any design or process changes that may affect
these parameters.
9. Thst conditions assume signal transition time of 3 ns or less, timing reference levels of 1.Sv, input pulse levels of 0 to 3.0V, and output loading
of the specified IOJ/IoH and 30-pF load capacitance.
7COO6-3S
7C016-3S
Min.
Max.
ns
ns
55
ns
10. At any given temperature and voltage condition for any given device,
tHzCE is less than tLZCE and tHZOE is less than tLZOE.
11. Test conditions used are Load 3.
6-116
....;;::;;==r,;
CY7C006
CY7C016
PRELIMINARY
=:srcYPRESS
Switching Characteristics Over the Operating Rangel?, 10J (continued)
Parameter
wruTECYCLE
Description
7COO6-1S
7C016-1S
Min.
Max.
7COO6-2S
7C016-2S
Min.
Max.
7COO6-3S
7C016-3S
Min.
Max.
7COO6-SS
7C016-SS
Min.
Max.
Unit
twc
Write Cycle Time
15
25
35
55
ns
tSCE
CE LOW to Write End
12
20
30
45
ns
tAW
Address Set-Up to Write End
12
20
30
45
ns
tHA
Address Hold From Write End
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
Write Pulse Width
12
20
25
40
ns
tSD
tHD[12J
Data Set-Up to Write End
10
15
15
25
ns
Data Hold From Write End
0
0
0
0
tHZWE[12J
R/W LOW to High Z
tLZWE[12J
R/W HIGH to Low Z
tWDD[13J
Write Pulse to Data Delay
10
3
3
tDDD[13J
Write Data Valid to Read Data Valid
BUSY TIMINGLl.]
20
15
3
ns
25
ns
ns
3
30
50
60
80
ns
25
30
35
60
ns
tBLA
BUSY LOW from Address Match
15
20
20
30
ns
tBHA
BUSY HIGH from Address
Mismatch
15
20
20
30
ns
tBLC
BUSY LOW from CE LOW
15
20
20
30
ns
tBHC
BUSY HIGH from CE HIGH
15
17
25
30
ns
tps
Port Set-Up for Priority
5
5
5
5
ns
tWB
R/W LOW after BUSY LOW
0
0
0
0
ns
tWH
tBDD[15J
R/W HIGH after BUSY HIGH
13
17
25
30
BUSY HIGH to Data Valid
ns
Note
15
Note
15
Note
15
Note
15
ns
15
25
25
30
ns
15
25
25
30
ns
INTERRUPT TIMINGLl4]
tINS
INTSetTime
INT Reset Time
tINR
SEMAPHORE TIMING
SEM Flag Update Pulse (OE
tsop
orSEM)
tSWRD
tsps
Notes:
10
10
15
20
ns
SEM Flag Write to Read Time
5
5
5
SEM Flag Contention Window
5
5
5
5
5
ns
ns
12. Must be met by the device writing to the RAM under all operating
conditions.
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay
waveform.
14. Test conditions used are Load 2.
15. tBDD is a calculated parameter and is the greater oftWDD - tPWE (actual) or tDDD - tSD (actual).
6-117
•
CY7C006
CY7C016
PRELIMINARY
?cYPRESS
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)[16, 17]
~~
_ _ _
tRC _ _ *~
ADDRESS
~DA::;bXXXX*.". '_-_-_-_-_-_-_-_-_-_-_-_D-A~T_A-_V-A~L_I-D~ ~ ~ ~ ~ ~_
DATA OUT
C006-10
Read Cycle No.2 (Either Port CE/OE Access) [15, 18, 19]
SEMorCE
~"
,E
/
tACE
't
DATA OUT
ICC
-
-tHZCE-
tHZOE
tOOE-
!:'--=tLlOE tLlCE
f////////
tpu
~'\.'\.'\.'\.
r-
-"
..,
DATA VALID
.'\. .'\.
-tpo
/I
ISB - - - . / .
Read Timing with Port-to-Port Delay (MiS = L)[20, 21]
twc
ADDRESSR
-l
'{
MATCH
tpWE
~"-
/
~tso
)K
~K
DATAINR
ADDRESSL
~"
VALID
MATCH
toDD
),
DATAOUTL
~~
twoo
-
C006 12
Notes:
15. R/W is HIGH for read cycle.
16. Device is continuously selected CE LOW and OE Law. This
waveform cannot be used for semaphore reads.
17. Address valid prior to or coincident with CE transition Law.
=
=
=
=
18. CEL L, SEM H when accessing RAM. CE
accessing semaphores.
19. BUSY = HIGH for the writing port.
20. CEL = CER = LOW.
6-118
= H, SEM = L when
CY7C006
CY7C016
PRELIMINARY
==-rcYPRESS
Switching Waveforms (continued)
Write Cycle No.1: OE Three-State Data I/Os (Either Port) [22, 23, 24]
~------------------------twc--------------------------~
ADDRESS
R!W
DATA IN
____~------~~~,~~----------tpwE------------~~I-------------------
E
----------------~
tSD
DATA VALID
.1 .. tHD:;;:L
.:;p-------
HIGH IMPEDANCE
COO6-13
Write Cycle No.2:
RJW Three-State Data I/Os (Either Port)[21, 23, 25]
~--------------------twc--------------------------~
ADDRESS
SEMORCE
R!W ----------------~~~
DATA IN
DATA OUT
C006-14
Notes:
21, The internal write tim~fthe memory is defined by the overlap ofa;:
or SEM LOW and R/W LOW. Both signals must be LOW to initiate
a write, and either signal can terminate a write by going HIGH. The
data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
22. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tpWE or (tHZWE + tSD) to allow the I/O
drivers to turn off and data to be placed on the bus for the required
tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as
short as the specified tPWE.
23. R/W must be HIGH during all address transitions.
24. Data I/O pins enter high impedance when OE is held LOW during
write.
6-119
CY7C006
CY7C016
PRELIMINARY
Switching Wavefonns (continued)
Semaphore Read After Write TIming, Either Side[26]
1/°0
DATAourVALID
R/W
----+o>----tDOE - - - I
C006-15
Semaphore Contention[27, 28, 29]
~L-A2L
R/W
_____________________
M_A_JC_H
____________________--J)xC~
E
L
SEIiiIL
-
____________________
tspsMATCH
SEIiiIR
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
~
C006-16
Notes:
25. CE = HIGH for the duration of the above timing (both write and read
cycle).
26. IIOoR = IIOOL = LOW (request semaphore); CER = eEL = HIGH
27. Semaphores are reset (available to both ports) at cycle start.
28. If tsps is violated, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control the
semaphore.
6-120
=--~
CY7C006
?CYPRESS ======~P;;'RE;;L;;1~M~IN~'A~R~Y===~CY~7~C~Ol~6
Switching Waveforms (continued)
Read with BUSY (M/S=HIGH)[20J
twe
ADDRESSR
jl(
)1(
MATCH
tpWE
~
)'oL'
~tso
K
DATAINR
tps
ADDRESS L
VALID
~O
I--
)K
I--
MATCH
tBLA
tBHA
BOS'i'L
tBOO_
tO~~
~~
DATAOUTL
twoo
COO8 17
Write Timing with Busy Input (MlS=LOW)
6-121
ciiii~YPRESS
PRELIMINARY
CY7COO6
CY7C016
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[30]
CEL Valid First:
X
ADDRESSL,R
~"h
CEL
CER
X
ADDRESS MATCH
BOSYR
tBLC~
CER Valid First:
X
ADDRESSL,R
1"'h
tBLC~
SOSV'L
COO6-19
X
ADDRESS MATCH
CER
CEL
t'~l
t~l
COO6-20
Busy Timing Diagram No.2 (Address Arbitration)[29]
Left Address Valid First:
tRcortWC
)(
ADDRESSL
ADDRESS MATCH
)(
ADDRESS MISMATCH
_tps-
~(
ADDRESSR
----------=j ____--1I...------------cooa--21
'-tBLA
BUSYR
I--tBHA
i'
Right Address Valid First:
~
tRcortWC
ADDRESSR
)~
ADDRESS MATCH
),
ADDRESS MISMATCH
!.--tpsADDRESSL
~{
-tBLA
lIDS'i'L
~~1
-tBHA
Note:
29. Iftpsisviolated, the busy signal will be asserted on one side or the othel, bullh~r~ is no guarantee on which side BUSY will be asserted.
30. IRA depends on which enable pin (eEL or RiWd is deasserted first.
C006-22
31. tINS or tn"rR. rlp.pp.llds O!! 'Nhich enable pin (CEL or R/WL) hi asserted
last,
6-122
#f!!r" ~1 ~
CY7C006
"CYPRESS ======~PRE~L;;IM;;I;;N.;;'AR~Y~==~C~Y7~C~O~16
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
twe
ADDRESSL
WRITE3FFF
ico--- t'NS[32]
---...r-'--________________...,...._
Right Side Clears INTR:
C006-23
ADDRE:: ,X7XV"':X7X~~~X-,.;X~X~X~X..,..X.--X...,....X-X-~. .==R=EA-:R-:FF-F;=~*..::====
RNi/R
OER
/
/
/
//rZ
~~
' \ . ' \ .' \ .
~R -=~------------------~~
COO6-24
Right Side Sets INTL:
ADDRESSR
- - - t'NS[31]
--_1"'-__________________
COO6-25
Left Side Clears INTL
ADDRESSR XXXXXXXXXXXXXX~I4-~~R_EA:_R:F_FF_*
CE
~I\.
l'
:;:::~=====
L
mL
------------------------------~}(
6-123
C006-26
CY7C006
CY7C016
PRELIMINARY
Architecture
Interrupts
The CY7C006/016 consists of a an array of 16K words of 8/9 bits
each of du~ort RAM cells, I/O and address lines, and controlsignals (CE, DE, R/W). These control pins permit independent access for reads or writes to any location in memory. Th handle simultaneous writes/reads to the same location, a BUSY pin is provided
on each port. Two interrupt (INT) pins can be utilized for port-toport communication. Tho semaphore (SEM) controll2..ins are used
for allocating shared resources. With the MIS pin, the
CY7C006/016 can function as a Master (BUSY pins are outputs)
or as a slave (BUSY pins are inputs). The CY7COO6/016 has an automatic power-down feature controlled Er..CE. Each port is providedwith its own output enable control (DE), which allows data to
be read from the device.
The interrupt flag (INT) permits communications between
ports.When the left port writes to location 3FFE(HEX), the right
port's interrupt flag (INTR) is set. This flag is cleared when the
ri~port reads that same location. Setting the left port's interrupt flag
(INTL) is accomplished when the right port writes to location
3FFE(HEX). This flag is cleared when the left port reads location
3FFE(HEX). The message at 3F~HE29 is user-defined. See
Table 2 for input requirements for INT. INTRand INTL are pushpull outputs and do not require pull-up resistors to operate.
Busy
Functional Description
Write Operation
D~ must be set up for a duration of tSD before the rising edge of
R/W in order to guarantee a valid write. A write operation is controlleol~I~I~I~ I~ ~
11 10 9 8 7 6 5 4 3 2
...J...J....I....I
...J...J
if ./>~
1
Arc
AcL
AcL
AoL
AsL
A2L
AIL
AcL
IJO'4L
I/O'5l
Vee
JJ'lTL
IlUS'IL
GNO
MiS
CY7C024
GND
I/OOR
l!OS'i'R
110 m
JJ'lTR
I/0 2A
Vee
1/0 3R
1/0 4R
AOR
I/0 5R
I/O",
I/0 7R
AoR
A'R
A2R
AcR
AcR
AOR
VOSR
7C024-2
84·PinPLCC
ThpView
~
m ffi
;;# ~ C\I
0
:;::!
cL...r
(.)
~I':Z...J
..J ...J
..J
gg g g g g l5g g!~ >ol~ ~I~I~ I~
..J - '
...J
Ii! ~~
111098765432184838281807978777675
A7L
AcL
AcL
1I0 '0l
AoL
I/O'1L
AcL
A2L
1/0 ,2l
I/O'3L
AIL
GND
1/0 ,4l
AOL
I/O'5L
l!OS'i'L
lIIITL
CY7C025
Vee
GND
MiS
GND
IIOOR
l!OS'i'R
I/O'R
lNiR
1/0 2R
AcR
Vee
A'R
1I0 3R
I/0 4R
I/05R
IIOOR
1I0 7R
I/OSR
A2R
AcR
30
~
E
3 2 33343536 373839 40414243 4445464748495051 525354
6-129
A4R
A'R
AOR
Pin Configurations (continued)
tOO-Pin TQFP
Top View
10099 98 97 96 95 94 93 92 91 90 B9 88 87 8685 84 83 82 81 BO 79 78 77 76
NC
NC
NC
NC
NC
NC
NC
NC
AoL
I/0 10L
I/0 11L
I/O,2L
I/O ,3L
GND
I/O,4L
I/O,5L
~
AoL
Aa
A'L
AoL
II'lTL
l!lJS\'L
Vee
GND
MiS
GND
I/OOR
I/O'R
I/0 2R
BUSYR
II'lTR
AoR
Vee
A'R
A2R
1/0 3R
AsR
1/0 4R
1/0 5R
~R
NC
NC
NC
NC
1/0 6R
NC
NC
NC
NC
7C024-4
10099 98 97 96 95 94 93 92 91 90 8988 8786 85 84 83 82 81 80 79 78
n
76
75
NC
NC
NC
NC
NC
NC
NC
NC
AsL
I/O,0L
~L
AsL
AcL
I/O'1L
I/O,2L
I/O'3L
A'L
GND
I/O'4L
I/O,5L
AoL
lfITL
l!lJS\'L
GND
Vee
MiS
GND
I/OOR
I/O'R
1/0 2R
BUSYR
lfITR
1/00R
A'R
A'R
AoR
Vee
AaR
110..
1/0 5R
I/OeR
~R
NC
NC
NC
NC
NC
NC
NC
NC
7C024-5
6-130
Sir" _"~
CY7C024/0241
CY7C025/0251
PRELIMINARY
......... 'CyPRESS
Pin Configurations (continued)
lOO-Pin TQFP
lbpView
10099989796 9594 93 92 91 908988 8786 85 84 83 82 81 80 79 78 IT 76
75
NC
NC
ilOal
I/017L
AsL
I/0 11L
I/0 12L
A4L
A3L
A'L
AtL
I/0 13L
I/0 14L
GND
AoL
I/015L
II'JTL
IlUS'/L
1I0 16L
Vee
GND
MiS
GND
=R
lIiITR
I/OOR
110 m
1/0 2R
AoR
Vee
110,"
1/0 4R
I/O'R
AtR
A'R
AsR
AoR
I/06R
NC
NC
I/DaA
I/0
NC
NC
NC
NC
17R
NC
NC
NC
NC
7C024-6
10099989796 9594 93 92 91 90 89 88 87868584 83 82 81 aD 79 787776
NC
NC
NC
NC
NC
I/O'L
NC
t/°17L
A'L
I/0 11L
AoL
I/0 12L
A3L
l/013L
I/0 14L
AoL
AtL
GND
AoL
1/0 15L
II'JTL
=L
MiS
=R
lIiITR
I/0 16l
GND
Vee
GND
I/OOR
I/0 1R
I/0 2R
AoR
Vee
AtR
A'R
I/0 3A
I/0 4R
I/O'R
AoR
AoR
1/0 6R
NC
I/OSR
NC
I/017R
NC
NC
NC
NC
7C024-7
6-131
=--
~
? -,
CY7C024/0241
CYPRESS ========P;;;;;'RE=L;;;;;IM;;;;;I;;;;;"N;;;;;S4;;;;;R;;;;;Y=;;;;;C;;;;;Y;;;;;7C;;;;;O;;;;;2;;;;;5/;;;;;02;;;;;5=1
Pin Definitions
Left Port
CEL
Right Port
CER
Description
Chip Enable
R/WL
R!WR
Read!Write Enable
OEL
OER
Output Enable
AoL -A12L
AoR-A 12R
Address
IIOOL - II0 15L
SEML
IIOOR - I/015R
Data Bus Input/Output
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select
LBL
LBR
Lower Byte Select
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
MIS
Master or Slave Select
Vee
GND
Ground
Power
Selection Guide
7C024/0241-15
7C025/0251-15
15
7C024/0241-25
7C025/0251-25
25
7C024/0241-35
7C025/0251-35
35
7C024/0241-55
7C025/0251-55
55
Maximum Operating Current (rnA)
280
250
230
220
Maximum Standby Current for ISBl (rnA)
70
60
50
40
Maximum Access Time (ns)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................ -65°C to + 150 00 C
Ambient Temperature with
Power Applied ...................... -55°C to + 125°C
Supply Voltage to Ground Potential. . . . . .. -0.3V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . .. -0.5V to + 7.0V
DC Input Voltage[3] ..... . . . . . . . . . . . . . .. -O.5V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Commercial
Industrial
Note:
3. Pulse width < 20 ns.
6-132
Ambient
Temperature
O°C to +70°C
Vee
5V ± 10%
-40°C to +85°C
5V ± 10%
=---
~
CY7C024/0241
~);CYPRESS================P=~==L=IM=I=N=~=R=Y===C=Y=7C=O=2=5/=02=5~1
Electrical Characteristics Over the Operating Range
7C024/0241-15
7C025/0251-15
Parameter
VOH
VOL
VIH
VIL
IIX
Ioz
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Icc
Operating Current
Min.
2.4
Test Conditions
Vee = Min., IOH - -4.0 rnA
Vee - Min., IOL - 4.0 rnA
Max. Min.
2.4
0.4
2.2
0.8
10
+10
+10 -10
lYp.
190
280
170
170
250
290
rnA
'JYp.
2.2
10
-10
GND.s VI.s Vee
Output Disabled,
GND.sVo.sVee
Vee = Max., lOUT = 0 rnA,
Outputs Disabled
Ind
Com'l
7C024/0241-25
7C025/0251-25
Max.
0.4
0.8
+10
+10
Unit
V
V
V
V
J.IA.
I-\A
ISBl
Standby Current
(Both Ports TTL Levels)
CEL and CER ~ VIH,
f= fMAX[4J
Com'l
Ind
50
70
40
60
75
rnA
ISB2
Standby Current
(One Port TTL Level)
CEL or CEf ~ VIH,
f= fMAX[4
120
180
Standby Current
(Both Ports CMOS
Levels)
Both Ports CE and CER ~
Vee - 0.2Y,
VIN ~ Vee - 0.2V
or VIN .s 0.2Y, f = 0[4J
3
15
100
100
3
140
160
15
rnA
ISB3
Com'l
Ind
Com'l
3
15
Standby Current
(Both Ports CMOS
Levels)
One Port CEL or
CER ~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
VIN.s0.2Y,
Active Port Outputs,
f = fMAX[4J
90
120
90
140
ISB4
Ind
Com'l
110
160
Ind
7C024/0241-35
7C025/0251-35
Parameter
VOH
VOL
VIH
VIL
IIX
loz
Icc
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Min.
2.4
Test Conditions
Vee = Min., IOH = -4.0 rnA
V cc - Min., IOL - 4.0 rnA
lYP·
2.2
GND.s VI.s Vee
Output Disabled, GND .s Vo.s Vee
Com'l
Vee = Max., lOUT = 0 rnA,
Outputs Disabled
Ind
10
-10
160
160
rnA
rnA
7C024/0241-55
7C025/0251-55
Max. Min.
2.4
0.4
2.2
0.8
10
+10
+10 -10
230
260
lYP·
150
150
Max. Unit
V
0.4
V
V
0.8
V
+10 J.IA.
+10 J.IA.
220 rnA
250
ISBl
Standby Current
(Both Ports TTL Levels)
CEL and CER ~ VIH,
f = fMAX[4J
Com'l
Ind
30
30
50
65
20
20
40
60
rnA
ISB2
Standby Current
(One Port TTL Level)
CEL or CEf ~ VIH,
f = fMAX[4
Standby Current
roth Ports CMOS
evels)
Both Ports CE and CER ~
Vee - 0.2Y,VIN~ VPfr - 0.2V
Ind
or VIN .s 0.2Y, f = 0
85
85
3
125
140
15
75
75
3
110
145
15
rnA
ISB3
Com'l
Ind
Com'l
3
15
3
15
Standby Current
(Both Ports CMOS
Levels)
One Port CEL or
CER ~ Vee - 0.2Y,
VIN ~ Vee - 0.2V
or VIN .s 0.2Y,
Active Port Outputs,
f = fMAX[4J
Com'l
80
105
70
90
Ind
80
120
70
105
ISB4
Notes:
4. fMAX = lItRC = All inputs cycling at f = lItRC (except output enable). f = 0 means no address or control lines change. This applies
only to inputs at CMOS level standby ISB3.
6-133
rnA
rnA
=:'~YPRESS;;;;;;;;;;;;;;;;P=~;;L=IM=I=N=~=R=Y;;=~=~=~~=~=~;~=~~=;==~
Capacitance[5]
Parameter
Description
Input Capacitance
Uutput Capacitance
CIN
COUT
:r-l
Test Conditions
TA = 25°C, f
Vcc = 5.OV
Max.
10
10
= 1 MHz,
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
C
= 30 pF
I
OUTPUT
_=
R2
I
0
RTH = 2500
I
'No
c-"'1
3470
-
-
:r-l
5V
R1 = 8930
OUTPUT
C=5 F
P
VTH = 1.4V
--
7C024-9
7C02"S
(a) Normal Load (Load 1)
I
R1 = 8930
R2 = 3470
--
7C024-10
(c) Three-State Delay (Load 3)
(b) Thevenin Eqnivalent (Load 1)
ALL INPUT PULSES
OUTPU~
I
C=30pF
,OV~
100
90%
~
10%
GND
~3ns
~3ns
Load (Load 2)
7C024-l2
7C02'·11
Switching Characteristics Over the Operating Range[6]
Parameter
Description
READ CYCLE
Read Cycle Time
tRC
tAA
tOHA
tACE!?j
tDOE
tLZOE lH ,9J
tHZOElH ,9j
tLZCE!8,9j
tHZCEI8,9J
tpu
tpD
tABEL7J
7C024/0241-15
7C025/0251-15
Min.
Max.
7C024/0241 25
7C025/0251- 25
Min.
Max.
15
Address to Data Valid
25
3
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
0
35
25
15
OUTrut Hold From
Ad ress Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
7C024/0241 35
7C025/0251-35
Min.
Max.
3
3
3
10
3
0
15
15
25
25
Notes:'
5. Tested initiaIJy and after any design or process changes that may
affect these parameters.
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of l.SY, input pulse levels of ato 3.0Y, and output loading
of the specified IOIlIoH and 30-pF load capacitance.
7.
8.
9.
6-134
25
55
ns
ns
ns
25
3
20
0
0
25
35
ns
ns
ns
ns
ns
ns
ns
ns
3
3
Unit
ns
55
25
20
15
10
3
3
15
3
55
35
20
13
3
55
35
25
15
10
7C024/0241-55
7C025/0251- 55
Min.
Max.
To access RAM, CE=L, UB=L, SEM=H. To access semaphore,
CE=H and SEM=L. Either condition must be valid for the entire
tscEtime.
At any given temperature and voltage condition for any given device,
tHZCE is less than tLZCE and tHZOE is less than tLZOE·
Test conditions used are Load 3.
=r- -.,:;:4:
PRELIMINARY
CCYy77CC00224S//00224S11
~'CYPRESS~~~~~~~~~~~~~~~~~~
Switching Characteristics Over the Operating Rangd 6j (continued)
Parameter
Description
WRITE CYCLE
Write Cycle Time
twc
tSCEl/J
CE LOW to Write End
Address Set-Up to
tAW
Write End
Address Hold From
tHA
Write End
tSAI?J
Address Set-Up to
Write Start
Write Pulse Width
tpWE
Data Set-Up to Write End
tSD
Data Hold From Write End
tHD
R/W LOW to High Z
tHZWE l9J
R/W HIGH to Low Z
tLZWEI"J
tWDDllOJ
Write Pulse to Data Delay
Write Data Valid to Read
tDDD llOj
Data Valid
BUSY TIMlNG[llj
tBLC
BUSY LOW from Address
Match
BUSY HIGH from Address
Mismatch
BUSY LOW from CE LOW
tBHC
tps
BUSY HIGH from CEHIGH
Port Set-Up for Priority
tWB
R/W HIGH after BUSY
(Slave)
R/W HIGH after BUSY
HIGH (Slave)
BUSY HIGH to Data Valid
tBLA
tBHA
tWH
tBDD[12j
7C024/0241 15
7C025/0251-15
Min.
Max.
7C024/0241 25
7C025/0251-25
Min.
Max.
7C024/0241 35
7C025/0251-35
Min.
Max.
7C024/0241 55
7C025/0251-55
Min.
Max.
Unit
15
12
12
25
20
20
35
30
30
55
35
35
ns
ns
ns
0
0
0
0
ns
0
0
0
0
ns
12
10
0
20
15
0
25
15
0
35
20
0
30
25
50
35
60
35
70
45
ns
ns
ns
ns
ns
ns
ns
15
20
20
45
ns
15
20
20
40
ns
15
20
20
40
ns
15
20
20
35
10
15
0
20
0
0
25
0
5
5
5
5
ns
ns
0
0
0
0
ns
13
20
30
40
ns
Note
12
Note
12
Note
12
Note
12
ns
15
15
20
20
25
25
30
ns
30
ns
INTERRUPT TIMING[llj
INT Set Time
tINS
INT Reset Time
tINR
SEMAPHORE TIMlNG
SEM Flag Update Pulse (OE
tsop
orSEM)
SEM Flag Write to Read Time
tSWRD
tsps
SEM Flag Contention
Window
tSAA
SEM Address Access Time
10
12
5
5
15
15
20
ns
10
10
15
ns
10
10
15
ns
25
35
55
ns
Notes:
10. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
11. Test conditions used are Load 2.
12. taDD is a calculated parameter and is the greater oftWDD-tpWE (actual) or tDDD-tSD (actual).
6-135
i!!I!!:~
CY7C024/0241
.;CYPRESS ========P;;;;;'RE=L;;;;;IM;;;;;I;;;;;N.;;;;;~=Y=;;;;;CY=7C;;;;;O;;;;;2;;;;;5/;;;;;02;;;;;5=1
Data Retention Mode
The CY7COZ4/0241 is designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over temperature. The following rules insure data retention:
1. Chip enable (CE) must be held HIGH during data retention,
within Vcc to Vcc - O.ZY.
Z.
3.
Timing
Data Reiention Mode
4.SV
Vcc?. 2.0V
Vee to Vee - 2.0V
7C024·13
Parameter
ICCDRl
Thst Conditions[13]
@VCCDR=ZV
Note:
13. CE = Vee, Vin = GNDto Vee, TA = 25°C. This parameter is guaranteed but not tested.
6-136
CE must be kept between Vcc - O.ZV and 70% of Vcc during the power-up and power-down transitions.
The RAM can begin operation >tRC after V cc reaches the
minimum operating voltage ( 4.5 volts).
_
~
CY7C024/0241
);CYPRESS~~~~~~~~P=~~L=IM=I=N=~=R=Y~=C=Y=7C=O=2=5/=02=5~1
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)[14, IS, 16]
~O~~------ttRC
ADDRESS
f-tOHA
DATA OUT
r-------------------------~
DATA VALID
PREVIOUS DATA VALID
7C024·14
Read Cycle No.2 (Either Port CE/OE Access)[14, 17, 18]
tACE
~I'..
CEand
LS or US
;;'f
I+--tHZCE-
-'K.
tDOE
tHZDE .....
~tLZOE-
...,L// / / / / /
DATA OUT
--
ICC
CURRENT
DATA VALID
-'
tLzCE
tpu
i----tpD
Iss
Read Cycle No.3 (Either Port)[14, 16, 17, 18]
ADDRESS
~
tRC----------------------~
__________________________________________
~
"'-1------------- tAA -------------+/_!
DATA OUT __________________________~~~~----------------------~~~~~)
7C024-16
Notes:
14_ RiW is HIGH for read cycles.
IS. Device is continuously selected CE = VIL and UB or LB = VIL. This
waveform cannot be used for semaphore reads.
16. OE= VIL.
17. Address valid prior to or coincident with CE transition LOW
18. To access RAM, CE = V.lL!..!!B or LB = VIL, SEM = V]H. To access
semaphore, CE = V]H, SEM = VIL.
6-137
=-- ~
CY7C024/0241
. , CYPRESS ========P;;;;;'RE=L;;;;;IM;;;;;I;;;;;N.;;;;;r:4;;;;;R;;;;;Y=;;;;;C;;;;;Y;;;;;7C;;;;;O;;;;;2;;;;;5/;;;;;02;;;;;5=1
Switching Waveforms (continued)
Write Cycle No.1:
11M Controlled Timing[19, 20, 21, 22]
ADDRESS
CE[23, 241
Rm
--+----,,1
DATA OUT
NOTE 26
l---------------~--------------~NOTE26
tSD
DATA IN
7C024-17
Write Cycle No.2: CE Controlled Timing[19, 20, 21, 27]
ADDRESS
twc
=>K
)(
tAW
"CE[23, 241
/V
!\.
I--tSA
tHA--
tSCE
R/W
tsD
1/
DATA IN
/1
I'
Notes:
19. R/W must be HIGH during all address transitions.
20. A write occurs duti!!g the overlap (tSCE or tPWE) of a LOW CE or
SEM and a LOW UB or LB.
21. IRA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH al the end of write cycle.
22. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tpWE or (tHzWE + tSD) to allow the I/O
drivers to tum off and data to be p.!!!.ced on the bus for the required
tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tpWE.
tHD~
7C024·18
23. 1b access RAM, CE = VIL, SEM = VIH.
24. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
1b access lower byte, CE = VIL, LB = VIlA SEM = VIH.
25. ltansition is measured ±500 mV from steady state with a 5-pF load
(including scope and jig). This parameter is sampled and not 100%
tested.
26. During this period, the I/O pins are in the output state, and input signals must not be applied.
27. If the CE or SEM LOW transition occurs simultaneously with or after
the R/W LOW transition, the outputs remain in the high-impedance
state.
6-138
~
lsrcYPRESS
CY7C024/0241
========P;;;;;;'RE=L;;;;;;IM;;;;;;I;;;;;;N;;;;;;r:4;;;;;;R;;;;;;Y=;;;;;;C;;;;;;Y;;;;;;7C;;;;;;O;;;;;;2;;;;;;5/;;;;;;02;;;;;;5=1
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[28]
1100
DATAOUT VALID
7C024-19
Timing Diagram of Semaphore Contention[29, 3D, 31]
AoL -A2L
R/WL
SEML
AoR-A2R
-----------------------------><~---------MATCH
~.~MATCH
R!WR
K.
SEMR
I\.
7C024-20
Notes:
28. CE = HIGH for the duration of the above timing (both write and read
cycle).
29. I/DOR = I/DOL = WW (request semaphore); CER = CEL = HIGH
30. Semaphores are reset (available to both ports) at cycle start.
31. If tsps is violated, the semaphore will definitely be obtained by one
side or the other, but which side will get the semaphore is unpredictable.
6-139
~. ~
CY7C024/0241
~'CYPRESS~~~~~~~~P~~~L~IM~I~N~~~R~Y~~C~Y~7~CO~2~5/~02~5~1
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (MJS=HIGH)[32j
twe
K
ADDRESSR
)K
MATCH
tpWE
~
;V'
_Iso
~
'?
DATAINR
tps
~O
i-~
ADDRESSL
VALID
MATCH
tBLA
tBHA
BOS'i'L
£tBOO_
tO~~
~
DATAouTL
E=
twoo
70024-21
Write Timing with Busy Input (MJS=LOW)
Rm
BDS'i'
-r-
tpWE
----f ~, J'- f....;t
-i
W
,;;.;,H-:1---------7C024·22
Note:
32. CEL = CER = LOW.
6-140
PRELIMINARY
-:rcYPRESS
CY7C024/0241
CY7C025/0251
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)(33]
CEL Valid First:
ADDRESSL,R
X
t~b
GEL
CER
IBLC~
ffiJS'i'R
CER Valid First:
ADDRESSL,R
X
GEL
t'~l
BUSYL
IBLC~
7C024-23
X
ADDRESS MATCH
~"b
CER
X
ADDRESS MATCH
t' l
OC
7C024-24
Busy Timing Diagram No.2 (Address Arbitration)[33]
Left Address Valid First:
tRC orlwc
ADDRESSL
~
ADDRESS MATCH
)K
ADDRESS MISMATCH
_tps-
)(
ADDRESSR
BOSY
1-1
-IBLA
R
Right Address Valid First:
I--tBHA
7C024-25
IRCorlWC
ADDRESSR
'!JE
ADDRESS MATCH
)(
ADDRESS MISMATCH
_IpsADDRESSL
~(
BOSYL---j~=:--I+-IBLA
I--IBHA
~
Note:
33. Iftpsisviolated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
6-141
7C024-26
;-- ~
CY7C024/0241
=r -, CYPRESS ========;;;;PRE=L;;;;I;;;;M;;;;IN;;;;r.4;;;;R;;;;Y==C;;;;Y;;;;7C;;;;O;;;;2;;;;;5/;;;;02;;;;5=1
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
twc
ADDRESSL
WRITE FFF (1 FFF CY7C025)
RiWL
f
INTR
t1NS[35l
----1"-----------------------
Right Side Clears ooR:
~
tRC
7C024·27
...
XXXXXXXXXXXXXX . . . .,{1.:. :.Fl.:. .;F~=~=~=~5"'-)_~
ADDRESSR
_ _ __
CER
"-
t1NR[35l
/////
lJER
INTR
'"'"'"'"~
"~
7C024·28
Right Side Sets INTL:
twc
ADDRESSR
WRITE FFE (1 FFE CY7C025)
14---
t1NS[35l
- - - . f ' ' -_____________________
70024-29
Left Side Clears INTL:
AD,"-
XXXXXXXXXXXX>OOf~(1.;..;.F~..;;;.~.;;.;;~;.;.;fc~Fg2~5)'___'*
_ _ __
::ilK.
CEL
RiWL
OE
L
~L
/
/
/
/-;V
"'.oK
' "' "' "
/
7C024-30
Notes:
34. tHA depends on which enable pin (eEL or RlWL) is deasserted first.
35. tINS or tINR depends on which enable pin (eEL or RlWL) is asserted
last.
6-142
PRELIMINARY
Architecture
The CY7C024/0241 and CY7C025/0251 consist of an array of 4K
words of 16/18 bits each and 8K words of 16/18 bits each of dual~t RAM cells, I/O and address lines, and control signals (CE,
OE, R/W). These control pins permit independent accessforreads
or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each
port.1Wo interrupt (INT) pins can be utilized forport-to-port communication. Two semaphore (SEM) £.ontrol pins are used for allocating shared resources. With the M/S pin, the CY7C024/0241 and
CY7C025/0251 can function as a master (BUSY pins are outputs)
or as a slave (BUSY pins are inputs). The CY7C024/0241 and
CY7C025/0251 have an automatic power-down feature controlled
b.r..gE. Each port is provided with its own output enable control
(OE), which allows data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge of
R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No.1 waveform) or
the CE pin (see Write Cycle No.2 waveform). Required inputs for
non-contention operations are summarized in Table 1.
If a location is being written to 'by one port and tbe opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tODD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and CE
pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user of the CY7C024/0241 or CY7C025/0251 wishes
to access a semaphore fla&..Q1en the SEM pin must be asserted instead of the CE pin, and OE must also be asserted.
Interrupts
The upper two memory locations maybe used for message passing.
The highest memory location (FFF for the CY7C024/0241, IFFF
for the CY7C025/0251) is the mailbox for the right port and the
second-highest memory location (FFE for the CY7C024/0241,
IFFE for the CY7C025/0251) is the mailbox for the left port.
When one port writes to the other port's mailbox, an interrupt is
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
Each port can read the other port's mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox
and thus resetting the interrupt to it.
If your application does not require message passing, do not connect the interrupt pin to the processor's interrupt request input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2.
Busy
The CY7C024/0241 and CY7C025/0251 provide on-chip arbitration to resolve simultaneous memory location access (contention).
CY7C024/0241
CY7C025/0251
Ifboth ports' CEs are asserted and an address match occurs within
tps of each other, the busy logic will determine which port has access. Iftpsisviolated,oneportwilldefinitelygainpermissiontothe
location, but which one is not predictable. BUSY will be asserted
tBLA after an address match or tBLC after CE is taken LOW.
Master/Slave
A MIS pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will
allow the device to interface to a master device with no external
components.Writing to slave devices must be delayed until after
the BUSY input has settled (tBLC or tBLA). Otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the MIS pin allows the device to be used as a master
and, therefore, the BUSY line is an output. BUSY can then be used
to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C02410241 and CY7C025/0251 provide eight semaphore
latches, which are separate from the dual-port memory locations.
Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a
resource is in use. For example, if the left port wants to request a
given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in settin~ latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for tsop before attempting to read the semaphore. The
semaphore value will be available tSWRD + tDOE after the rising
edge of the semaphore write. If the left port was successful (reads
a zero), it assumes control of the shared resource, otherwise
(reads a one) it assumes the right port has control and continues
to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed
in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM pin
functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW).Ao-2 represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access. When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only 1/00 is used. If a zero is written to the left port of an available semaphore, a one will appear at
the same semaphore address on the right port. That semaphore can
now only be modified by the side showing zero (the left port in this
case). If the left port now relinquishes control by writing a one to
the semaphore, the semaphore will be set to one for both sides.
However, if the right port had requested the semaphore (written a
zero) while the left port had control, the right port would immediatelyown the semaphore as soon as the left port released it. Table
3 shows sample semaphore operations.
When reading a semaphore, all sixteen data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the
other port. If both ports attempt to access the semaphore within
tsps of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
6-143
~
CY7C024/0241
~~YPRESS~~~~~~~~P~~~L~IM~I~N~~~Y~~C~Y~7C~O~2~5/~02~5~1
Thble 1. Non-Contending Read/Write
Inputs
CE
RIW
OE
H
X
X
X
X
X
L
L
X
L
Outputs
LB
SEM
X
X
H
HighZ
HighZ
H
H
H
HighZ
HighZ
Deselected: Power-Down
H
H
Data In
HighZ
Write to Upper Byte Only
UB
1/0 0-1/0 7
1/0 8-1/0 15
Operation
Deselected: Power-Down
L
L
X
H
L
H
HighZ
Data In
Write to Lower Byte Only
L
L
X
L
L
H
Data In
Data In
Write to Both Bytes
L
H
L
L
H
H
Data Out
HighZ
Read Upper Byte Only
L
H
L
H
L
H
HighZ
Data Out
Read Lower Byte Only
L
H
L
L
L
H
Data Out
Data Out
Read Both Bytes
X
X
H
X
X
X
HighZ
HighZ
Outputs Disabled
H
H
L
X
X
L
Data Out
Data Out
Read Data in Semaphore
Flag
X
H
L
H
H
L
Data Out
Data Out
Read Data in Semaphore
Flag
H
...r
X
X
X
L
Data In
Data In
Write DlNo into
Semaphore Flag
X
..r
X
H
H
L
Data In
Data In
Write DlNo into
Semaphore Flag
L
X
X
L
X
L
Not Allowed
L
X
X
X
L
L
Not Allowed
Thble 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)[36j
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
RlWL
L
X
X
X
CEL
L
X
X
L
Left Port
OEL AoL-llL
X
(l)FFF
X
X
X
X
(l)FFE
L
INTL
X
X
D37J
HP~J
RlWR
X
X
L
X
CER
X
L
L
X
Right Port
OER AoR-llR
X
X
L
(l)FFF
X
(l)FFE
X
X
INTR
D,Sj
HLjfJ
X
X
Thble 3. Semaphore Operation Example
Function
No action
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Do-DIS Left
1
0
0
Do-DIS Right
1
1
1
Left port writes 1 to semaphore
Left port writes 0 to semaphore
1
1
0
0
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left port writes 1 to semaphore
0
1
1
1
0
1
1
1
0
1
1
1
Notes:
36. AoL-12L and AoR-12R, IFFF/lFFE for the CY7C025.
37. If BUSYR - L, then no change.
Status
Semaphore free
Left Port has semaphore token
No change. Right side has no write access to
semaphore.
Right port obtains semaphore token
No change. Left port has no write access to
semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
38. If BUSYL = L, then no change.
6-144
Ordering Information
Speed
(ns)
15
25
35
Ordering Code
CY7C024-15AC
A100
CY7C024-15JC
J83
CY7C024-25AC
A100
CY7C024-25JC
J83
CY7C024-25AI
AlOO
CY7C024-25JI
J83
CY7C024-35AC
A100
CY7C024-35JC
J83
CY7C024-35AI
AlOO
CY7C024-35JI
55
15
25
35
55
J83
Package1Ype
lOO-Pin Thin Quad Flat Pack
lOO-Pin Thin Quad Flat Pack
lOO-Pin Thin Quad Flat Pack
lOO-Pin Thin Quad Flat Pack
lOO-Pin Thin Quad Flat Pack
lOO-Pin Thin Quad Flat Pack
CY7C024-55AI
AlOO
J83
84-Lead Plastic Leaded Chip Carrier
Package
Name
Package 1Ype
J83
CY7C025-25AC
A100
CY7C025-25JC
J83
CY7C025-25AI
AlOO
CY7C025-25JI
J83
CY7C025-35AC
AlOO
CY7C025-35JC
J83
CY7C025-35AI
AlOO
CY7C025-35JI
J83
CY7C025 - 55AC
AlOO
CY7C025-55JC
J83
CY7C025-55AI
AlOO
CY7C025 - 55JI
J83
Commercial
Industrial
84-Lead Plastic Leaded Chip Carrier
CY7C024-55JI
AlOO
Industrial
84-Lead Plastic Leaded Chip Carrier
J83
CY7C025-15JC
Commercial
84-Lead Plastic Leaded Chip Carrier
CY7C024-55JC
CY7C025 -15AC
Commercial
84-Lead Plastic Leaded Chip Carrier
AlOO
Ordering Code
Operating
Range
84-Lead Plastic Leaded Chip Carrier
CY7C024-55AC
Speed
(ns)
Package
Name
Commercial
84-Lead Plastic Leaded Chip Carrier
lOO-Pin Thin Quad Flat Pack
lOO-Pin Thin Quad Flat Pack
Industrial
Operating
Range
Commercial
84-Lead Plastic Leaded Chip Carrier
lOO-Pin Thin Quad Flat Pack
Commercial
84-Lead Plastic Leaded Chip Carrier
lOO-Pin Thin Quad Flat Pack
Industrial
84-Lead Plastic Leaded Chip Carrier
lOO-Pin Thin Quad Flat Pack
Commercial
84-Lead Plastic Leaded Chip Carrier
lOO-Pin Thin Quad Flat Pack
Industrial
84-Lead Plastic Leaded Chip Carrier
lOO-Pin Thin Quad Flat Pack
Commercial
84-Lead Plastic Leaded Chip Carrier
lOO-Pin Thin Quad Flat Pack
84-Lead Plastic Leaded Chip Carrier
6-145
Industrial
Ordering Information (continued)
Speed
(ns)
Ordering Code
Package
Name
Package type
Operating
Range
15
CY7C0241-15AC
AI00
100-Pin Thin Quad Flat Pack
Commercial
25
CY7C0241- 25AC
AlOO
100-Pin Thin Quad Flat Pack
Commercial
CY7C0241-25AI
AI00
100-Pin Thin Quad Flat Pack
Industrial
CY7C0241- 35AC
AI00
100-Pin Thin Quad Flat Pack
Commercial
CY7C0241-35AI
AI00
lOO-Pin Thin Quad Flat Pack
Industrial
CY7C0241- 55AC
AlOO
100-Pin Thin Quad Flat Pack
Commercial
CY7C0241- 55AI
AI00
lOO-Pin Thin Quad Flat Pack
Industrial
35
55
Speed
(ns)
Ordering Code
Package
Name
Package TYpe
Operating
Range
15
CY7C0251-15AC
AlOO
loo-Pin Thin Quad Flat Pack
Commercial
25
CY7C0251-25AC
AlOO
lOO-Pin Thin Quad Flat Pack
Commercial
CY7C0251-25AI
AlOO
lOO-Pin Thin Quad Flat Pack
Industrial
35
CY7C0251- 35AC
AlOO
lOO-Pin Thin Quad Flat Pack
Commercial
CY7C0251-35AI
AlOO
lOO-Pin Thin Quad Flat Pack
Industrial
CY7C0251-55AC
AlOO
lOO-Pin Thin Quad Flat Pack
Commercial
CY7C0251-55AI
Aloo
lOO-Pin Thin Quad Flat Pack
Industrial
55
Document #: 38-00255-A
6-146
Timing Technology 7
I
Timing Technology
Device Number
CY7B991/CY7B992
CY7B991O/CY7B9920
Page Number
Description
Programmable Skew Clock Buffer (PSCB) ........................................ 7-1
Low Skew Clock Buffer ....................................................... 7-13
CY7B991
CY7B992
Programmable Skew
Clock Buffer (PSCB)
Features
• All output pair skew <100 ps typical
(250 max.)
• 3.75- to SO-MHz output operation
• User-selectable output functions
- Selectable skew to IS ns
- Inverted and non-inverted
- Operation at Y2 and Y. input
frequency
- Operation at 2x and 4x input
frequency (input as low as 3.75
MHz)
•
•
•
•
•
•
Zero input to output delay
50% duty-cycle outputs
Outputs drive 50n terminated lines
Low operating current
32-pin PLCC/LCC package
Jitter < 200 ps peak-to-peak
« 25 ps RMS)
• Compatible witb a Pentium m -based
processor
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer
user-selectable control over system clock
functions. These multiple-output clock
drivers provide the system integrator with
functions necessary to optimize the timing
of high-performance computer systems.
Eight individual drivers, arranged as four
pairs of user-controllable outputs, can
each drive terminated transmission lines
with impedances as low as son while delivering minimal and specified output
skews and full-swing logic levels
(CY7B991 TTL or CY7B992 CMOS).
Each output can be hardwired to one of
nine delay or function configurations.
Delay increments of 0.7 to 1.5 ns are de-
termined by the operating frequency with
outputs able to skew up to ±6 time units
from their nominal "zero" skew position.
The completely integrated PLL allows externalload and transmission line delay effects to be canceled. When this "zero
delay" capability of the PSCB is combined
with the selectable output skew functions,
the user can create output-to-output delays of up to ± 12 time units.
Divide-by-two and divide-by-four output
functions are provided for additional flexibility in designing complex clock systems.
When combined with the internal PLL,
these divide functions allow distribution
of a low-frequency clock that can be multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility.
CY7B991
::'~YPRESS===========================C=Y=7=B9=92=
Pin Definitions
Signal Name
Description
I/O
Reference frequency input. This input supplies the frequency and timing against which all functional
variation is measured.
REF
FB
PLL feedback input (typically connected to one of the eight outputs).
FS
Three-level frequency range select. See Table 1.
1FO,lF1
Three-level function select inputs for output pair 1 (100, 101). See Table 2.
2FO,2F1
Three-level function select inputs for output pair 2 (ZOO, ZOI). See Table 2.
3FO,3Fl
Three-level function select inputs for output pair 3 (300, 301). See Table 2.
4FO,4Fl
Three-level function select inputs for output pair 4 (400, 401). See Table 2.
TEST
I
Three-level select. See test mode section under the block diagram descriptions.
100,101
a
a
a
a
Output pair 1. See Table 2.
200,201
3QO,301
400,401
Output pair Z. See Table 2.
Output pair 3. See Table 2.
Output pair 4. See Table 2.
VCCN
PWR
Power supply for output drivers.
VCCQ
GND
PWR
Power supply for internal circuitry.
PWR
Ground.
Table 2. Programmable Skew Configurations[l]
Block Diagram Description
Phase Frequency Detector aud Filter
Function Selects
These two blocks accept inputs from the reference frequency
(REF) input and the feedback (FB) input and generate correction information to control the frequency of the Voltage-Controlled Oscillator (VeO). These blocks, along with the veo,
form a Phase-Locked Loop (PLL) that tracks the incoming REF
signal.
VCO and Time Unit Generator
The veo accepts analog control inputs from the PLL filter block
and generates a frequency that is used by the time unit generator
to create discrete time units that are selected in the skew select
matrix. The operational range of the veo is determined by the
FS control pin. The time unit (tu) is determined by the operating
frequency of the device and the level of the FS pin as shown in
Table 1.
fNOM
FS[2,3]
Min. Max.
tu
=
1
lFO,2FO,
3FO,4FO
LOW
LOW
- 4tu
LOW
MID
- 3tu
- 6tu
- 6tu
LOW
HIGH
- Ztu
- 4tu
- 4tu
MID
LOW
-ltu
- Ztu
- Ztu
MID
MID
Otu
Otu
Otu
MID
HIGH
+ltu
+Ztu
+Ztu
HIGH
LOW
+Ztu
+ 4tu
+ 4tu
HIGH
MID
+ 3tu
+ 6tu
+ 6tu
HIGH
HIGH
+ 4tu
Divide by4
Inverted
whereN
=
Which tu = 1.0 ns
15
30
44
MID
25
50
Z6
38.5
HIGH
40
80
16
6Z.5
3QO,3Ql
4QO,4Ql
DividebyZ DividebyZ
Notes:
1. For all three-state inputs, HIGH indicates a connection to Vee, LOW
indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to
Approximate
f NOM x N Frequency (MHz) At
LOW
lQO,IQl,
2QO,2Ql
IFl,2Fl,
3Fl,4Fl
Table 1. Frequency Range Select and tu Calculation[l]
(MHz)
Output Functions
Vcd2.
ZZ.7
2.
Skew Select Matrix
The skew select matrix is comprised offour independent sections.
Each section has two low-skew, high-fanout drivers (xOO, xQ1),
and two corresponding three-level function select (xFO, xFl) inputs. Table 2 below shows the nine possible output functions for
each section as determined by the function select inputs. All
times are measured with respect to the REF input assuming that
the output connected to the FB input has Otu selected.
3.
7-Z
The level to be set on FS is determined by the "normal" operating frequency (fNOM) ofthe V co and Time Unit Generator (see Logic Block
Diagram). Nominal frequency (fNOM) always appears at lQO and the
other outputs when they are operated in their undivided modes (see
Table 2). The frequency appearing at the REF and FB inputs will be
fNOM when the output connected to FB is undivided. The frequency
of the REF and FB inputs will be fNOMi2 or fNOM/4 when the part is
configured for a frequency multiplication by using a divided output as
the FB input.
When the FS pin is selected HIGH, the REF input must not transition
upon power-up until Vee has reached 4.3Y.
CY7B991
CY7B992
::')~YPRESS================================
15"
;:0"
°
_0
I
"
~
I
" If <;?
"
M
I
°
°
_0
°
_0
" M" ~"
1\i
+
+
_0
°
+
_0
+
°
"
;:0
+
_0
"
15
+
_0
FB Input
REF Input
lFx
2Fx
3Fx
4Fx
(N/A)
LM
- Stu
LL
LH
- 4tu
LM
(N/A)
- 3tu
LH
ML
- 2tu
ML
(N/A)
- 1tu
MM
MM
MH
(N/A)
+ ltu
HL
MH
+ 2tu
HM
(N/A)
+ 3tu
HH
HL
HM
LL/HH
HH
+ 4tu
(N/A)
(N/A)
(N/A)
--i
Otu
If"'-
+Stu
DIVIDED
INVERT
Figure 1.'Jypical Outputs with FB Connected to a Zero-Skew Outputl4]
78991-3
Test Mode
Maximum Ratings
The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the
CY7B9911CY7B992 to operate as explained briefly above (for
testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a 100g resistor.
This will allow an external tester to change the state of these
pins.)
If the TEST input is forced to its MID or HIGH state, the device
will operate with its internal phase locked loop disconnected, and
input levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal
mode.
In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own function select inputs (xFO and xF1) and the waveform characteristics
of the REF input.
(Above which the usefullife may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to +150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential ........ -O.5V to +7.0V
DC Input Voltage ....................... -O.5V to +7.0V
Output Current into Outputs (LOW) .............. 64 rnA
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Notes:
4. FB connected to an output selected for "zero" skew (i.e., xFl : xFO :
MID).
5. Indicates case temperature.
7-3
Range
Commercial
Industrial
MilitaryL'J
Ambient
Temperature
O°C to +70°C
-40°C to +85°C
-55°C to + 125°C
Vee
5V::!: 10%
5V::!: 10%
5V ± 10%
I
~
CY7B991
_;CYPRESS ==============CY=7B=9=92=
Electrical Characteristics Over the Operating Rangd6]
VOH
Description
Output HIGH Voltage
VOL
Output LOW Voltage
Parameter
VIH
VIL
VIHH
VIMM
VILL
IIH
IlL
IIHH
IIMM
IILL
los
leeQ
Input HIGH Voltage
(REF and FB inputs only)
Input LOW Voltage
(REF and FB inputs only)
Three-Level Input HIGH
Voltage (Test, FS, xFn)[7]
Three-Level Input MID
Voltage (Test, FS, xFn)[7]
Three-Level Input LOW
Voltage (Thst, FS, xFn)[7]
Input HIGH Leakage Current
(REF and FB inputs only)
Input LOW Leakage Current
(REF and FB inputs only)
Input HIGH Current
(Test, FS, xFn)
Input MID Current
(Test, FS, xFn)
Input LOW Current
(Thst, FS, xFn)
Output Short Circuit
Currentl8]
Operating Current Used by
Internal Circuitry
leeN
Output Buffer Current per
Output Pair[9]
PD
Power Dissigation per
Output Pair 10]
CY78991
Min.
Max.
2.4
Test Conditions
Vee - Min., IOH - - 16 rnA
Vee - Min., IOH - - 40 rnA
Vee = Min., IOL = 46 rnA
Vee - Min., IOL -46 rnA
CY78992
Min.
Max.
Unit
V
Vee- 0.75
V
0.45
0.45
Vee
V
1.35
V
2.0
Vee
- 0.5
0.8
Vee1.35
- 0.5
Min. ~ V ee ~ Max.
Vee -IV
Vee
Vee -1V
Vee
V
Min. ~ Vee ~ Max.
Ved2500mV
0.0
Ved2+
500rnV
1.0
Ved2500rnV
0.0
Ved2+
500rnV
1.0
V
10
IlA
Min. ~ V ee ~ Max.
10
Vee - Max., VIN - Max.
Vee - Max., VIN - O.4V
-500
- 50
VIN- Ved2
200
flA
50
IlA
- 200
flA
N/A
rnA
85
90
85
90
rnA
14
19
rnA
78
1041 11 J
rnW
50
- 50
- 200
VIN= GND
Vee - Max., VOUT
= GND (25°C only)
VeeN - VeeQ - I Corn'l
Max., All Input
Mill
Selects Open
Ind
I
VCCN - VCCQ - Max.,
lOUT = ornA
Input Selects Open, fMAX
VeeN - VeeQ - Max.,
lOUT = ornA
Input Selects Open, fMAX
IlA
- 500
200
VIN- Vee
V
250
Capacitance[12]
Parameter
Description
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, Vee = 5.0V
Notes:
6. See the last page of this specification for Group A subgroup testing information.
7. These inputs are normally wired to VCC, GND, orlef! unconnected
(actual threshold voltages vary as a percentage of V ce). Internal termination resistors hold unconnected inputs at V ccJ2. If these inputs
are switched, the function and timing ofthe outputs may glitch and the
PLL may require an additional tLOCK time before all datasheet limits
are achieved.
8. CY7B991 should be tested one output at a time, output shortedfor less
than one second, less than 10% duty cycle. Room temperature only.
CY7B992 outputs should not be shorted to GND. Doing so may cause
permanent damage.
9. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7B991:
ICCN = [(4 + O.l1F) + [«835 - 3F)/Z) + (.0022FC)]N] x 1.1
CY7B992:
ICCN = [(3.5+ .l7F) + [«HtiO - :i..8!<)/Z) + (.UU25FC)JNJ x 1.1
Max.
10
Unit
pF
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC=F.C
10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power
dissipation due to the load circuit:
CY7B991:
PD = [(22 + 0.61F) + [«1550 - 2.7F)/Z) + (.Ol25FC)]N] x 1.1
CY7B992:
PD = [(19.25+ 0.94F) + [«700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 9 for variable definition.
11. CMOS output buffer current and power dissipation specified at
50-MHz reference frequency.
12. Appliesto REF and FB inputs only. Thstedinitially and after any design
or process changes that may affect these parameters.
7-4
~~
CYcy77BB999921
7CYPRESS==================================~
AC Test Loads and Waveforms
5V
~
I
Cl
R1
R2
3.0V
2.0V
Vth = 1.5V
0.8V
R1=130
R2 = 91
Cl = 50 pF (Cl = 30pF for -2 and-5 devices)
(Includes fixture and probe capacitance)
~1
""':""
""':""
ns
789914
78991·5
TTLAC Test Load (CY7B991)
TTL Input Test Waveform (CY7B991)
Vee
~
Cl
I .",.
R1
R1 = 100
R2 = 100
Cl = 50 pF (Cl = 30pF for-2 and -5 devices)
(Includes fixture and probe capacitance)
80%
Vth = Vecl2
20%
R2
~3ns
78991-6
CMOS AC Test Load (CY7B992)
CMOS Input Test Waveform (CY7B992)
Switching Characteristics Over the Operating Rangd 2, 13]
CY7B991-2[14]
Parameter
fNOM
Description
Operating Clock
Frequency in MHz
Min.
FS - LOWlI,Lj
FS
FS
= MID[l, Lj
= HIGHlI.~,jj
tRPWL
REF Pulse Width HIGH
REF Pulse Width LOW
tv
Programmable Skew Unit
tSKEWPR
Zero Output Matched·Pair Skew
(XQO, XQ1)[16, 17]
tRPWH
lYP·
15
25
40
CY7B992-2[14]
Max.
Min.
30
50
80
15
25
40
5.0
5.0
lYP·
Max.
Unit
30
50
80ll;j
MHz
5.0
5.0
ns
ns
See Table 1
Zero Output Skew (All OutputS)[l6,
l~,lYj
0.05
0.20
0.05
0.20
ns
0.1
0.25
0.1
0.25
ns
Output Skew ~Rise-Rise, Fail-Fail, Same Class
Outputs )[16, 2 ]
0.25
0.5
0.25
0.5
ns
tSKEW2
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided) [16, 20]
0.3
0.5
0.3
0.5
ns
tSKEW3
Output Skew ~Rise-Rise, Fall-Fall, Different
Class Outputs) 16,20]
0.25
0.5
0.25
0.5
ns
tSKEW4
Output Skew (Rise-Fallj Nominal-Divided,
Divided-Inverted)[16,20
0.5
0.9
0.5
0.7
ns
tDEV
tpD
Device-to-Device Skewll4, L1j
0.75
ns
- 0.25
0.0
+0.25
- 0.25
0.0
+0.25
ns
- 0.65
0.0
+0.65
- 0.5
0.0
+0.5
3.0
3.0
ns
ns
ns
2.5
2.5
ns
ns
0.5
ms
25
200
ps
tSKEWO
tSKEWI
tODCV
tpWH
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variationl 22 j
OutputHIGHTimeDeviationfrom50%lB,~4j
tOFALL
Output LOW Time Deviation from 50%l23, 24J
Output Rise Timel L3 , 25j
Output Fall Timel L3 , L;J
tLOCK
PLL Lock Time l26j
tJR
Cycle-to-Cycle Output
Jitter
tpWL
tORISE
0.75
2.0
1.5
0.15
1.0
0.15
1.0
1.2
1.2
0.5
25
200
RMSll4j
Peak-to-Peak[l4j
7-5
0.5
2.0
0.5
2.0
ps
I
~
CY7B991
~;CYPRESS=============================CY=7=B=99==2
Switching Characteristics Over the Operating Rangd2, 13] (continued)
CY7B991-S
Parameter
fNOM
Description
Operating Clock
Frequency in MHz
Min.
'!Yp.
CY7B992-S
Max.
Min.
30
15
'!Yp.
Max.
Unit
30
MHz
FS = LOW[l,4J
15
FS = MID[l,2J
25
50
25
50
FS = IDGHl1,2, 3J
40
80
40
80l15 J
tRPWH
REF Pulse Width HIGH
5.0
5.0
ns
tRPWL
REF Pulse Width LOW
5.0
5.0
ns
tu
Programmable Skew Unit
tSKEWPR
Zero Output Matched-Pair Skew
(XQO, XQ1)[16, 17]
0.1
tSKEWO
Zero Output Skew (All Outputs)l16, 18J
tSKEW1
Output Skew bRise-Rise, Fall-Fall, Same Class
Outputs)[16,2 ]
tSKEW2
See Table 1
0.25
0.1
0.25
ns
0.25
0.5
0.25
0.5
ns
0.6
0.7
0.6
0.7
ns
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16,20]
0.5
1.0
0.6
1.5
ns
tSKEW3
Output Skew ~Rise-Rise, Fall-Fa\l, Different
Class Outputs) 16,20]
0.5
0.7
0.5
0.7
ns
tSKEW4
Output Skew (Rise-Fallj Nominal-Divided,
DiVlded-lnverted)[16,20
0.5
1.0
0.6
1.7
ns
tDEY
Device-to-Device Skewl 14, 21J
1.25
ns
tpD
Propagation Delay, REF Rise to FB Rise
- 0.5
0.0
+0.5
- 0.5
0.0
+0.5
ns
tODCV
Output Duty Cycle Variationl22J
- 1.0
0.0
+1.0
- 1.2
0.0
+1.2
ns
tpWH
Output HIGH Time Deviation from 50%l4j,LAJ
4.0
ns
tPWL
Output LOW Time Deviation from 50%l23, 24J
4.0
ns
tORISE
Output Rise Timel23, Z:>J
0.15
1.0
1.5
0.5
2.0
3.5
ns
tOFALL
Output Fall Timel23 , 4:lJ
0.15
1.0
1.5
0.5
2.0
3.5
ns
tLOCK
PLL Lock Time l26J
0.5
ms
tJR
Cyc1e-to-Cyc1e Output
Jitter
1.25
2.5
3
0.5
RMSll4J
25
25
ps
Peak-to-Peakl14J
200
200
ps
Notes:
13. Thst measurement levels for the CY7B991 are TTL levels (1.5V to
1.5V). Thst measurement levels for the CY7B992 are CMOS levels
(Vcd2 to V cd2). Thst conditions assume signal transition times of 2
ns or less and output loading as shown in the AC Thst Loads and Waveforms unless otherwise specified.
14. Guaranteed by statistical correlation. Thsted initially and after any design or process changes that may affect these parameters.
15. Except as noted, all CY7B992- 2 and -5 timing parameters are specified to BO-MHz with a 30-pF load.
16. SKEW is defined as the time between the earliest and the latest output
transition among all outputs for which the same tu delay has been selected when all are loaded with 50 pF and terroinated with500 to 2.06V
(CY7B991) or Vcd2 (CY7B992).
17. tSKEWPR is defined as the skew between a pair of outputs (XQO and
XQ1) when all eight outputs are selected for Otu.
18. tSKEWO is defined as the skew between outputs when they are selected
for Otu. Other outputs are divided or inverted but not shifted.
19. CL =OpR For CL =30pF, tSKEwo=0.35ns.
20. There are three classes of outputs: Nominal (multiple oftu delay), Inverted (4QO and 4Q1 only with 4FO = 4F1 = HIGH), and Divided
(3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
21. tDEv is the output-to-output skew between any two devices operating
under the same conditions (Vcc ambient temperature, air flow, etc.)
22. toDCV is the deviation of the output from a 50% duty cycle. Output
pulse width variations are included in tSKEW2 and tSKEW4 specifications.
23. Specified with outputs loaded with 30 pF for the CY7B99X - 2 and - 5
devices and 50 pF for the CY7B99X -7 devices. Devices are terminated through 500 to 2.06V (CY7B991) or Vcd2 (CY7B992).
24. tpWH is measured at 2.0V for the CY7B991 and O.B V cc for the
CY7B992. tpWL is measured at O.BV for the CY7B991 and 0.2 V cc for
the CY7B992.
25. tORlSE and loFALLmeasured between O.BV and 2.0V forthe CY7B991
or O.BVcc and 0.2Vcc for the CY7B992.
26. tLOCK is the time that is required before synchronization is achieved.
This specification isvalid only after V ccis stable and within normal operating limits. This parameter is measured from the application of a
new signal or frequency at REF or FB until tpD is within specified
limits.
7-6
CY7B991
=r
=-~YPRESS=============================C=Y7=B=99~2
Switching Characteristics Over the Operating Rangd2, 13] (continued)
CY7B991-7
Parameter
fNOM
Description
Min.
FS - LOWl"Lj
Operating Clock
Frequency in MHz
FS
FS
= MIDll,2J
= HIGHL1,2J
CY7B992-7
Max.
Min.
30
15
25
50
25
50
40
80
40
50
'!Yp.
15
'!Yp.
Max.
Unit
30
MHz
tRPWH
REF Pulse Width HIGH
5.0
5.0
ns
tRPWL
REF Pulse Width LOW
5.0
5.0
ns
tv
Programmable Skew Unit
tSKEWPR
Zero Output Matched-Pair Skew
(XQO, XQ1)[16, 17J
0.1
0.25
0.1
0.25
ns
tSKEWO
Zero Output Skew (All OutputS)LI6, lMJ
0.3
0.75
0.3
0.75
ns
tSKEWI
Output SkewfoRise-Rise, Fall-Fall, Same Class
Outputs)[16,2 ]
0.6
1.0
0.6
1.0
ns
tSKEW2
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided) [16, 20]
1.0
1.5
1.0
1.5
ns
tSKEW3
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[16, 20J
0.7
1.2
0.7
1.2
ns
tSKEW4
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted) [16, 20]
1.2
1.7
1.2
1.7
ns
See Table 1
tDEV
Device-to-Device SkewLl4, 21J
1.65
ns
tpD
Propagation Delay, REF Rise to FB Rise
- 0.7
0.0
+0.7
- 0.7
0.0
+0.7
ns
tODCV
Output Duty Cycle VariationL22J
- 1.2
0.0
+1.2
- 1.5
0.0
+1.5
ns
tPWH
Output HIGH Time Deviation from 50%l""', U>j
3
5.5
ns
tPWL
Output LOW Time Deviation from 50%lLj,L4j
3.5
5.5
ns
tORISE
ns
tOFALL
Output Rise TimeL23, 25J
Output Fall TimelLj, L:>j
tLOCK
PLL Lock TimeL2bJ
tJR
Cycle-to-Cycle Output
Jitter
1.65
0.15
1.5
0.15
1.5
2.5
0.5
3.0
5.0
2.5
0.5
3.0
5.0
ns
0.5
ms
25
25
ps
200
200
ps
0.5
RMSllOj
I Peak-to-PeakllOj
I
7-7
~
CY7B991
"-"cYPRESS ===============CY=7=B=99=2
AC Timing Diagrams
REF
FB
Q
OTHERQ
INVERTED Q
REF DIVIDED BY 2
REF DIVIDED BY 4
78991-8
7-8
CY7B991
=:'~YPRESS~============================CY==7=B=99==2
Operational Mode Descriptions
REF~
, , ,
FB
, , ,
SySTEM _ _- - - - , REF
CLOCK
FS
4FO
4Fl
3FO
3Fl
2FO
2Fl
lFO
lFl
TEST
.------...,
~
~"
,- ~ ::==========:
::: ~ ~1
" ' /
300
301
200
201
LOAD
LOAD
~
, , ,
L~
~ZOL---_--J
fNt-~LI__
100
101
LO_A_D_--J
LENGTH Ll = L2 = L3 = L4
78991-9
Figure 2. Zero-Skew aud/or Zero-Delay Clock Driver
Figure 2 shows the PSCB configured as a zero-skew clock buffer.
In this mode the 7B991/992 can be used as the basis for a lowskew clock distribution tree. When all of the function select inputs (xFO, xFl) are left open, the outputs are aligned and may
each drive a terminated transmission line to an independent load.
SYSTEM
FB
_ _- - - i REF
FS
CLOCK
4FO
4Fl
3FO
3Fl
'-_----,2FO
2Fl
#V~'---L-OA-D_-'
, , ,
400
401
300
301
200
201
,-------,
~ fz ~L._LO_A_D----,
, , ,
I
~-_--I1FO
lFl
TEST
The FB input can be tied to any output in this configuration and
the operating frequency range is selected with the FS pin. The
low-skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), allows efficient printed circuit board design.
I
I
0
::fLI.L..f.l=:~
"
L4
, , ,,
100
101
,
,
,
~----L-E-NG-T-H~Ll=L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
LOAD
'--_ _ _ _...J
~
78991-10
Figure 3. Programmable-Skew Clock Driver
Figure 3 shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between outputs, the PSCB can be programmed to stagger the timing of its
outputs. The four groups of output pairs can each be programmed to different output timing. Skew timing can be adjusted
over a wide range in small increments with the appropriate strapping of the function select pins. In this configuration the 4QO output is fed back to FB and configured for zero skew. The other
three pairs of outputs are programmed to yield different skews
relative to the feedback. By advancing the clock signal on the
longer traces or retarding the clock signal on shorter traces, all
loads can receive the clock pulse at the same time.
In this illustration the FB input is connected to an output with
O-ns skew (xFl, xFO = MID) selected. The internal PLL synchro-
nizes the FB and REF inputs and aligns their rising edges to insure that all outputs have precise phase alignment.
Clock skews can be advanced by ±6 time units (tv) when using
an output selected for zero skew as the feedback. A wider range
of delays is possible if the output connected to FB is also skewed.
Since "Zero Skew", +tv, and - tv are defined relative to output
groups, and since the PLL aligns the rising edges of REF and FB,
it is possible to create wider output skews by proper selection of
the xFn inputs. For example a + 10 tv between REF and 3Qx can
be achieved by connecting lQO to FB and setting IFO = IFI =
GND, 3FO = MID, and 3Fl = High. (Since FB aligns at - 4 tv
and 3Qx skews to +6 tv, a total of + 10 tv skew is realized.)
Many other configurations can be realized by skewing both the
output used as the FB input and skewing the other outputs.
7-9
I
~
CY7B991
=:'~YPRESS=============================C=Y7=B=99~2
REF
JL..ILJL.
, , ,
FB
- - - I REF
FS
4FO
4F1
400
401
3FO
3F1
2FO
2F1
300
301
200
201
"'U1J1J""
, , ,
1FO
1F1
100
101
~
, , ,
TEST
76991-11
Figure 4. Inverted Output Connections
Figure 4 shows an example of the invert function of the PSCB. In
this example the 400 output used as the FB input is programmed
for invert (4FO = 4F1 = HIGH) while the other three pairs of
outputs are programmed for zero skew. When 4FO and 4F1 are
tied high, 400 and 401 become inverted zero phase outputs. The
PLL aligns the rising edge of the FB input with the rising edge of
the REF. This causes the 10, 20, and 30 outputs to become the
"inverted" outputs with respect to the REF input. By selecting
which output is connect to FB, it is possible to have 2 inverted
and 6 non-inverted outputs or 6 inverted and 2 non-inverted outputs. The correct configuration would be determined by the need
for more (or fewer) inverted outputs. 10, 20, and 30 outputs
can also be skewed to compensate for varying trace delays independent of inversion on 40.
Figure 5 illustrates the PSCB configured as a clock multiplier. The
300 output is programmed to divide by four and is fed back to
FB. This causes the PLL to increase its frequency until the 300
and 301 outputs are locked at 20 MHz while the lOx and 20x
outputs run at 80 MHz. The 400 and 401 outputs are programmed to divide by two, which results in a 40-MHz waveform
at these outputs. Note that the 20- and 40-MHz clocks fall simultaneously and are out of phase on their rising edge. This will ai-
low the designer to use the rising edges of the Y, frequency and V.
frequency outputs without concern for rising-edge skew. The
200, 201, 100, and 101 outputs run at 80 MHz and are skewed
by programming their select inputs accordingly. Note that the FS
pin is wired for 80-MHz operation because that is the frequency
of the fastest output.
Figure 6 demonstrates the PSCB in a clock divider application.
200 is fed back to the FB input and programmed for zero skew.
30x is programmed to divide by four. 4Qx is programmed to divide by two. Note that the falling edges of the 40x and 30x outputs are aligned. This allows use of the rising edges of the Yz frequency and 1/. frequency without concern for skew mismatch. The
lOx outputs are programmed to zero skew and are aligned with
the 2Qx outputs. In this example, the FS input is grounded to
configure the device in the 15- to 30-MHz range since the highest
frequency output is running at 20 MHz.
Figure 7 shows some of the functions that are selectable on the
30x and 40x outputs. These include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output allows the system designer to clock different subsystems
on opposite edges, without suffering from the pulse asymmetry
typical of non-ideal loading. This function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be
aligned within the skew spec.
The divided outputs offer a zero-delay divider for portions of the
system that need the clock to be divided by either two or four,
and still remain within a narrow skew of the "IX" clock. Without
this feature, an external divider would need to be added, and the
propagation delay of the divider would add to the skew between
the different clock signals.
These divided outputs, coupled with the Phase Locked Loop, allow the PSCB to multiply the clock rate at the REF input by either two or four. This mode will enable the desiguer to distribute
a low-frequency clock between various portions of the system,
and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low-skew characteristics of the
clock driver. The PSCB can perform all of the functions described above at the same time. It can multiply by two and four or
divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs.
REF~
,
REF~
20 MHz
FB
REF
FS
4FO
4F1
3FO
3F1
2FO
2F1
1FO
1F1
TEST
FB
REF
FS
,
400
401
300
301
200
201
100
101
"
,
,
,
,
'10MHz
'40 MHz
4FO
4F1
400
401
l-II--fJ.-r
'20 MHz
3FO
3F1
2FO
2F1
300
301
~
1FO
1F1
TEST
100
101
-u--u-u-
~
'SO MHz
..n.n.nn.tu1..
,
n.n.rtJ"t.n.rL
17B991~12
200
201
•
I
I
,
f
I
I
I
15 rMHz
:20)v1Hz
..f1..f1.rlf1-f
78991-13
Figure 6. Frequency Divider Connections
Figure 5. Frequency Multiplier with Skew Connections
7-10
CY7B991
CY7B992
FB
20-MHz
DISTRIBUTION
CLOCK
aO-MHz
~--~REF
r
=
FS
4FO
4F1
3FO
3F1
2FO
2F1
_ _-I 1FO
1F1
TEST
:
400
401
300
301
200
201
100
101
:
:
:
~INVERTED
:
,
Zo
20-MHz
~
111,'
~~HZ
,
'
,
,
,
,
LOAD
------,
__
I
~I,--
ZERO SKEW
"'fzo
LOAD
__
--,
f --1ZO'------...1
' ' , , "
aO-MHZ-:r.ut.rit.L.rlt
----, , , , "
SKEWED 4 ns
LOAD
=
78991-14
Figure 7. Multi-Fuuction Clock Driver
REF
.JL.lLJL
,
FB
----1 REF
SYSTEM _ _
CLOCK
LOAD
FS
4FO
4F1
3FO
3F1
2FO
2F1
1FO
1F1
400
401
:~~
201
100
101
I-~-+
1----1-= "_ t
'
,
,
.n n n -! ~ ~ ~
_
L4
IL-.._LO_A_D_--,
0
r-~~~§~~~=====l
TEST
Figure 8. Board-to-Board Clock Distribution
Figure 8 shows the CY7B991/992 connected in series to construct
a zero-skew clock distribution tree between boards. Delays of the
downstream clock buffers can be programmed to compensate for
the wire length (i.e., select negative skew equal to the wire delay)
necessary to connect them to the master clock source, approxi-
78991-15
mating a zero-delay clock tree. Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering
characteristics ofthe PLL filter. It is recommended that not more
than two clock buffers be connected in series.
7-11
I
~
CY7B991
.ftYPRESS ===============C=Y7=B=99=2
Ordering Information
Accuracy
(ps)
Ordering Code
Package
Name
Package 1YPe
Operating
Range
250
CY7B991-2JC
J65
32-Lead Plastic Leaded Chip Carrier
500
CY7B991-5JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7B991- 5JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7B991-7JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7B991-7JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
750
Commercial
CY7B991-7LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Military
250
CY7B992-2JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
500
CY7B992-5JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7B992-5JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7B992-7JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7B992-7JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7B992-7LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Military
750
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
VOL
VIH
VIL
VIHH
VIMM
VILL
IIH
IlL
IIHH
IIMM
IILL
ICCQ
ICCN
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Document #: 38-00188-G
7-12
CY7B9910
CY7B9920
Low Skew
Clock Buffer
Features
• All outputs skew <100 ps typical
(250 max.)
• 15- to SO-MHz output operation
• Zero input to output delay
• 50% duty-cycle outputs
• Outputs drive 50Q terminated lines
• Low operating current
• 24-pin SOIC package
• Jitter: <200 ps peak to peak,
<25 psRMS
• Compatible with Pentium m -based
processors
Functional Description
The CY7B991O and CY7B9920 Low
Skew Clock Buffers offer low-skew system clock distribution. These multipleoutput clock drivers optimize the timing
of high-performance computer systems.
Eight individual drivers can each drive
terminated transmission lines with imped-
ances as low as SOQ while delivering minimal and specified output skews and fullswing logic levels (CY7B9910 TIL or
CY7B9920 CMOS).
The completely integrated PLL allows
"zero delay" capability. External divide
capability, combined with the internal PLL,
allows distribution of a low-frequency
clock that can be multiplied by virtually
any factor at the clock destination. This
facility minimizes clock distribution difficulty while allowing maximum system
clock speed and flexibility.
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept inputs from the
reference frequency (REF) input and the
feedback (FB) input and generate correction information to control the frequency
of the Voltage-Controlled Oscillator
(VCO). These blocks, along with the
VCO, form a Phase-Locked Loop (PLL)
that tracks the incoming REF signal.
Logic Block Diagram
VCO
The VCO accepts analog control inputs
from the PLL filter block and generates a
frequency. The operational range of the
VCO is determined by the FS control pin.
Test Mode
The TEST input is a three-level input. In
normal system operation, this pin is connected to ground, allowing the
CY7B991O/CY7B9920 to operate as explained above. (For testing purposes, any
of the three-level inputs can have a removable jumper to ground, or be tied
LOW through a lOOQ resistor. This will
allow an external tester to change the
state of these pins.)
If the TEST input is forced to its MID or
HIGH state, the device will operate with
its internal phase-locked loop disconnected, and input levels supplied to REF
will directly control all outputs. Relative
output to output functions are the same
as in normal mode.
Pin Configuration
TEST
FB
REF
PHASE
FREO
DET
Voltage
Controlled
Oscillator
FS -------'
SOIC
Top View
00
REF
GND
Vcca
TEST
NC
NC
GND
FS
01
Vcca
VCCN
00
01
02
03
GND
02
03
04
05
VCCN
I
VCCN
07
06
GND
05
04
VCCN
FB
06
789910·1
Q7
789910·2
Pentium is a trademark of Intel Corporation.
7-13
CY7B9910
'Iz~YPRESS===========================CY=7=B=99=20=
Pin Definitions
I/O
Description
REF
Signal Name
I
Reference frequency input. This input supplies the frequency and timing against which all functional
variation is measured.
FB
FSL9,IU,UJ
I
PLL feedback input (typically connected to one ofthe eight outputs).
I
Three-level frequency range select.
TEST
I
Three-level select. See Thst Mode section.
Q[O .. 7]
0
VeeN
PWR
Power supply for output drivers.
VeeQ
GND
PWR
Power supply for internal circuitry.
PWR
Ground.
Clock outputs.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature .................. -6SoC to + IS0°C
Ambient Temperature with
Power Applied ....................... -SsoC to + 12SoC
Supply Voltage to Ground Potential ........ -O.SV to +7 .OV
DC Input Voltage ....................... -O.5V to +7.0V
Output Current into Outputs (LOW) .............. 64 rnA
Static Discharge Voltage ........................ >200lV
(per MIL-STD-883, Method 301S)
Latch-Up Current ........................... > 200 rnA
Operating Range
Ambient
Temperature
O°Cto +70°C
-40°C to +8SoC
Range
Commercial
Industrial
Vee
SV ± 10%
SV ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
CY7B9920
CY7B9910
Min.
Max.
Test Conditions
Min.
Max.
Unit
V
2.4
Vee = Min., IOH = -16mA
Vcc- 0.7S
Vee = Min., IOH =-40 rnA
O.4S
Vee = Min., IOL = 46 rnA
V
O.4S
Vee - Min., IOL -46 rnA
VIH
Input HIGH Voltage
(REF and FB inputs only)
2.0
Vee
Vee1.3S
Vee
V
VIL
Input LOW Voltage
(REF and FB inputs only)
-0.5
0.8
-0.5
1.3S
V
VIHH
Three-Level Input HIGH
Voltage (Thst, FS)[l]
Min.::>. Vee::>' Max.
Vee -IV
Vee
Vee -IV
Vee
V
VIMM
Three-Level Input MID
Voltage (Thst, FS)[l]
Min.::>. Vee::>. Max.
Ved2SOOmV
Ved2+
SOOmV
Ved2SOOmV
Ved2+
SOOmV
V
VILL
Three-Level Input LOW
Voltage (Test, FS)[l]
Min.::>. Vee::>' Max.
0.0
1.0
0.0
1.0
V
IIH
InputHIGHLeakageCurrent
(REF and FB inputs only)
Vee - Max., VIN - Max.
10
fAA
ILL
Input LOW Leakage Current
(REF and FB inputs only)
Vee = Max., VIN = O.4V
IIHH
Input HIGH Current
(Thst, FS)
VIN - Vee
~ut
VIN - Ved2
IIMM
IILL
(
MID Current
st, FS)
Input LOW Current
(Thst, FS)
10
-SOO
fAA
-SOO
200
-SO
SO
-SO
-200
VIN- GND
,
I
7-14
I
200
fAA
SO
fAA
fAA
-200
I
I
I
I
CY7B9910
~
::'~CYPRESS============================;C;Y;7B;9;92~O
Electrical Characteristics Over the Operating Range (continued)
Parameter
lOS
Description
Output Short Circuit
Currentl2)
lCCQ
Operating Current Used by
Internal Circuitry
VCCN = VCCQ
Max., All Input
Selects Open
lCCN
Output Buffer Current per
Output Pair[3J
PD
Power Dissir,ation per
Output Pair 4J
CY7B9910
Min.
Max.
-250
Test Conditions
CY7B9920
Max.
N/A
Unit
rnA
85
85
rnA
90
90
VCCN = VCCQ = Max.,
lOUT = ornA
Input Selects Open, fMAX
14
19
rnA
VCCN = VCCQ = Max.,
lOUT = ornA
Input Selects Open, fMAX
78
10415 J
rnW
Vcc = Max., VOUT
= GND (25°C only)
= ICorn'l
IMil/Ind
Min.
Capacitance[6J
Parameter
Description
Input Capacitance
TA
Test Conditions
Max.
Unit
= 25°C, f = 1 MHz, Vcc = 5.0V
10
pF
Notes:
1. These inputs are normally wired to VCC, GND, or left unconnected
(actual threshold voltages vary as a percentage of V cd. Internal termination resistors hold unconnected inputs at V cel2. If these inputs
are switched, the function and timing ofthe outputs may glitch and the
PLL may require an additional tWCK time before all datasheet limits
are achieved.
2. Thsted one output at a time, output shorted for less than one second,
less than 10% duty cycle. Room temperature only. CY7B9920 outputs
are not short circuit protected.
3. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7B9910:
ICCN = [(4 + 0.11p) + [«835 - 3F)/Z) + (.0022FC)JN] x 1.1
CY7B9920:
ICCN = [(3.5+ .17F) + [«1160 - 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz
4.
5.
6.
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC=F*C
Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power
dissipation due to the load circuit:
CY7B9910:
PD = [(22 + 0.61F) + [«1550 - 2.7F)/Z) + (.Ol25FC)]N] x 1.1
CY7B9920:
PD = [(19.25+ 0.94F) + [«700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 3 for variable definition.
CMOS output buffer current and power dissipation specified at
50-MHz reference frequency.
Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V
tRl
TIR2
3.0V
R2=91
CL = 50 pF (CL = 30 pF for -5 and -2 devices)
(Includes fixture and probe capacitance)
789910·3
789910-4
TTL AC Thst Load (CY7B9910)
TTL Input Thst Waveform (CY7B9910)
Vee
Vee
Rl = 100
tRl
TIR2
2.0V
V1h = 1.5V
0.8V
Rl = 130
R2 = 100
CL = 50 pF (CL = 30 pF for -5 and -2 devices)
(Includes fixture and probe capacitance)
80%
Vth = Vecf2
20%
~3ns
789910-5
789910-6
CMOS AC Thst Load (CY7B9920)
CMOS Input Thst Waveform (CY7B9920)
7-15
I
CY7B9910
=:'~YPRESS============================CY==7B=9=92~O
Switching Characteristics Over the Operating Rangel 7]
Parameter
fNOM
tRPWH
tRPWL
tSKEW
tDEY
tpD
tODCY
tORISE
tOFALL
tLOCK
tJR
CY7B9910-2l 8J
Min.
Max.
'lYP.
15
30
25
50
40
80
5.0
5.0
0.1
0.25
0.75
-0.25
0.0
+0.25
-0.65
0.0
+0.65
0.15
1.0
1.2
0.15
1.0
1.2
0.5
200
25
Description
FS = LOWlY, lUI
Operating Clock
Frequency in MHz
FS = MIDl9, lUJ
FS _ HIGHLY, 1U, 11]
REF Pulse Width HIGH
REF Pulse Width LOW
Zero Output Skew (All Outputs)l13, 14J
Device-to-Device Skew!8, 15]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation!!oJ
Output Rise Timel 17, 1KJ
Output Fall Timel17, 10J
PLL Lock Time!!YJ
Peak to Peak
Cycie-to·Cycie Output
Jitter
RMS
CY7B9920-2l8J
Min.
Max.
'!Yp.
15
30
25
50
801"'J
40
5.0
5.0
0.1
0.25
0.75
-0.25
0.0
+0.25
-0.65
0.0
+0.65
0.5
2.0
2.5
0.5
2.0
2.5
0.5
200
25
CY7B9910-5
Parameter
fNOM
tRPWH
tRPWL
tSKEW
tDEY
tpD
tODCY
tORISE
tOFALL
tLOCK
tJR
Min.
15
25
40
5.0
5.0
Description
FS = LOWlY,lU]
Operating Clock
Frequency in MHz
FS = MIDlY,IO]
FS = HIGHl9, lU, llJ
REF Pulse Width HIGH
REF Pulse Width LOW
Zero Output Skew (All Outputs)l13, 14J
Device.to-Device SkewlK, 1;]
'!Yp.
0.25
-0.5
-1.0
0.15
0.15
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation!16]
Output Rise TimelI/, I~]
Output Fall Timel17, 18J
PLL Lock Timel 19]
Peak to Peakl8J
Cycle-to-Cycle Output
Jitter
IRMS10J
Notes:
7. Test measurement levels for the CY7B991O are TTL levels (1.5V to
1.5V). Test measurement levels for the CY7B9920 are CMOS levels
(Vcd2 to Vcd2). Thst conditions asume signaitransition timesof2 ns
or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. For all three-state inputs, HIGH indicates a connection to V cc, LOW
indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to
Vcd2.
10. The level to be set on FS is determined by the "normal" operating frequency(fNOM) ofthe VCO (see LogicBlockDiagram). The frequency
appearing at the REF and FB inputs will be fNOMwhen the output connected to FB is undivided. The frequency of the REF and FB inputs
will be fNOM/X when the device is configured for a frequency multiplication by using external division in the feedback path of value X.
11. When Ibe FS pin is selected HIGH, the REF input must not transition
upon power-up until V cc has reached 4.3Y.
0.0
0.0
1.0
1.0
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
CY7B9920-5
Max.
30
50
80
0.5
1.0
+0.5
+1.0
1.5
1.5
0.5
200
25
Min.
15
25
40
5.0
5.0
'!Yp.
0.25
-0.5
-1.0
0.5
0.5
0.0
0.0
2.0
2.0
Max.
30
50
80[12J
0.5
1.0
+0.5
+1.0
3.0
3.0
0.5
200
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
12. Except as noted, all CY7B9920 - 2 and -5 timing parameters are specified to 80-MHz with a 30-pF load.
13. SKEW is defined as the time between the earliest and the latest output
transition among all outputs when all are loaded with 50 pF and terminated with 50Q to 2.06V (CY7B9910) or VCd2 (CY7B9920).
14. tSKEW is defined as the skew between outputs.
15. tDEY is the output-to-output skew between any two outputs on separate devices operating underlbe same conditions (Vcc, ambient temperature, air flow, etc.).
16. tODCY is the deviation of the output from a 50% duty cycle.
17. Specified with outputs loaded with 30 pF for the CY7B99XO-2 and
- 5 devices and 50 pF for Ibe CY7B99XO-7 devices. Devices are terminated through 50Q to 2.06V (CY7B991O) or V Cd2 (CY7B9920).
18. tORISE and tOFALL measured between 0.8V and 2.0V for the
CY7B9910 or 0.8Vcc and 0.2Vcc for the CY7B9920.
19. tLOCK is tbe time tbat is required before synchronization is achieved.
This specification is valid only after V cc is stable and within normal operating limits. This parameter is measured from the application of a
ne'.v eignnl or frequency at REF ur FB uniii tpD is within specified
limits.
7-16
~
CevY77BB99992100
~'CYPRESS~~~~~~~~~~~~~~~~~~
.§';
Switching Characteristics Over the Operating Range[7]
(continued)
CY7B9910-7
Parameter
fNOM
Description
FS = LOWlY, lUJ
Operating Clock
Frequency in MHz
FS = MIDI9, lUJ
FS _ HIGHI", lU, 11J
Min.
CY7B9920-7
Max.
Min.
15
30
15
30
25
40
50
25
50
80
40
50
'!Yp.
tRPWH
REF Pulse Width HIGH
5.0
5.0
tRPWL
REF Pulse Width LOW
Zero Output Skew (All Outputs)ll.>, 14J
5.0
5.0
tSKEW
tDEV
tpD
0.3
Device-to-Device Skewl~, I)J
0.75
'!Yp.
Max.
Unit
MHz
ns
ns
0.3
1.5
0.75
ns
1.5
ns
Propagation Delay, REF Rise to FB Rise
- 0.7
0.0
+0.7
- 0.7
0.0
+0.7
ns
- 1.2
0.0
+1.2
- 1.2
0.0
+1.2
ns
0.15
1.5
2.5
0.5
3.0
5.0
ns
tOFALL
Output Duty Cycle Variationl16J
Output Rise Timel l7 , 18J
Output Fall Timel l7, 10J
0.15
1.5
2.5
0.5
3.0
5.0
ns
tLOCK
PLL Lock Time t19J
0.5
0.5
ms
tJR
Cycle-to-Cycle Output
Jitter
200
25
200
ps
ps
tODCV
tORISE
Peak to Peakl8J
IRMSlOJ
25
AC Timing Diagrams
REF
FB
Q
I
OTHERQ
789910·8
7-17
~ii,{~
CY7B9910
-:;;s;;r' CYPRESS ==============~C~Y7~B~9~92~O
REF~
, , ,
FB
. --------,
, , ,
SySTEMI _ _- - - - i REF
FS
"'/~
CLOCK
~ ~,. ::====LO=A=D====:
00
01
02
~
03
04
05
I
I
I
f 1L-_LO_AD
----J
Zo
fIT-~I_-LO-A-D_---J
..
06
07
789910-9
Figure 1. Zero-Skew and/or Zero-Delay Clock Driver
Operational Mode Descriptions
Figure 1 shows the device configured as a zero-skew clock buffer.
In this mode the 7B9910/9920 can be used as the basis for a lowskew clock distribution tree. The outputs are aligned and may
each drive a terminated transmission line to an independent load.
The FB input can be tied to any output and the operating frequency range is selected with the FS pin. The low-skew specification, coupled with the ability to drive terminated transmission
REF
lines (with impedances as low as 50 ohms), allows efficient
printed circuit board design.
Figure 2 shows the CY7B9910/9920 connected in series to
construct a zero-skew clock distribution tree between boards.
Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the PLL filter. It
is not recommended that more than two clock buffers be connected in series.
JLfL-h,
FB
LOAD
SySTEM, _ _ _- - - - j REF
FS
CLOCK
00
01
02
LOAD
03
04
05
06
07
769910·10
Figure 2. Board-to-Board Clock Distribution
7-18
~
CY7B9910
=:'~~YPRESS~============================CY=7=B=9=92==O
Ordering Information
Accuracy
(ps)
250
500
750
Ordering Code
Package
Name
Package lYPe
CY7B991O-2SC
S13
24-Lead Small Outline IC
CY7B9920-2SC
S13
24-Lead Small Outline IC
Operating
Range
Commercial
CY7B991O-5SC
S13
24-Lead Small Outline IC
CY7B991O-5SI
S13
24-Lead Small Outline IC
Industrial
CY7B9920-5SC
S13
24-Lead Small Outline IC
Commercial
CY7B9920-5SI
S13
24-Lead Small Outline IC
Industrial
CY7B991O-7SC
S13
24-Lead Small Outline IC
Commercial
CY7B9910-7SI
S13
24-Lead Small Outline IC
Industrial
CY7B9920-7SC
S13
24-Lead Small Outline IC
Commercial
CY7B9920-7SI
S13
24-Lead Small Outline IC
Industrial
Document #: 38-00437-A
7-19
Commercial
Quality 8
Quality
Page Number
Description
Quality, Reliability, and Process Flows ....................................................................... 8-1
Quality, Reliability, and Process Flows
Miliary Product Assurance
Corporate Views on Quality and Reliability
Cypress under the QML program, uses MIL-STD-883 and
MIL-PRF-38535 as baseline documents to determine our Test
Methods, Procedures and General Specifications for
Semiconductors.
Cypress believes in product excellence. Excellence can only be defined by how the users perceive both our product quality and reliability.lfyou, the user, are not satisfied with every device that is
shipped, then product excellence has not been achieved.
Product excellence does not occur by following the industry
norms. It begins by being better than one's competitors, with better designs, processes, controls and materials. Therefore, product
quality and reliability are built into every Cypress product from
the beginning.
Cypress's Military components and SMD products are processed
per MIL-STD-883 using methods 5004 and 5005 to baseline our
screening and quality conformance procedures. Refer to Tables
3 -7, for the baseline flows and requirements. The processingperformed by Cypress results in a product that meets the class B
screening requirements as specified by these methods. Every
device shipped, as a minimum, meets these requirements.
Some of the techniques used to insure product excellence are the
following:
Commercial Product Assurance
• Product Reliability is built into every product design, starting
from the initial design conception.
• Product Quality is built into every step of the manufacturing
process through stringent inspections of incoming materials
and conformance checks after critical process steps.
• Stringent inspections and reliability conformance checks are
done on finished product to insure the finished product quality requirements are met.
• Field data test results are encouraged and tracked so that
accelerated testing can be correlated to actual use experiences.
Product Testing Categories
Three different testing categories are offered by Cypress:
1. Commercial operating range product: O°C to +70°C.
2. Industrial operating range product: -40°C to +85°C.
3. Military SMD (Standard Military Drawing) product processed
to QML Mil PRF 38535; Military operating range: -55°C to
+125°C.
8-1
Cypress is a IS09000 certified supplier. All commercial and industrial temp range products are manufactured using the same
controlled systems as our QML military product. Tables 1 and 2
define the 100% screening and conformance inspection for commercial and industrial temp range product.
~~
Quality, Reliability, and Process Flows
~,CYPRESS
Table 1. Cypress Commercial and Industrial Product Screening F1ows-Components
Product Temperature Ranges
MIL·STD·883 Method
Screen
Commercial O°C to +70°C;
Industrial -40°C to +8S o C
Plastic
Hermetic
VisuallMechanical
2010
• Internal Visual
• Hermeticity
- Fine Leak
- Gross Leak
Final Electrical
• Static (DC), Functional, and
Switching (AC) Thsts
Cypress Quality
Lot Acceptance
• External Visual
• Final Electrical Conformance
1014, Cond A or B (sample)
1014, Cond C
Per Device Specification
1. At Hot Thmperature and
Power Supply Extremes
2009
Cypress Method 17-00064
0.4%AQL
100%
Does Not Apply
Does Not Apply
LTPD = 5
100%
100%
100%
Note 1
Note 1
Note 1
Note 1
Table 2. Cypress Commercial and Industrial Product Screening Flows-Modules
Product Temperature Ranges
Screen
Final Electrical
• Static (DC), Functional, and
Switching (AC) Tests
MIL·STD·883 Method
Per Device Specification
1. At 25 ° C and Power
Supply Extremes
2. At Hot Thmperature and
Power Supply Extremes
Commercial O°C to +70°C;
Industrial -40°C to +85°C
100%
100%
Cypress Quality
Lot Acceptance
• External Visual
• Final Electrical Conformance
2009
Cypress Method 17·00064
Notes:
1. Lot acceptance testing is performed on every lot. AOQL (the Average
Outgoing Quality Level) for 1995 was 0 PPM.
8-2
Per Cypress Module Specification
Note 1
Quality, Reliability, and Process Flows
Table 3. Cypress QML/JAN/SMD/Military Product Screening Flows for Class B
Screen
Product Temperature Ranges -55°C to + 125°C
QML/JAN/SMD/Military
Military Modules
Components l2l
Screening Per
Method 5004 of
MIL-STD-883
VisuaIJMecbanical
• Internal Visual
Method 2010, Cond B
100%
N/A
• Temperature Cycling
Method 1010, Cond C, (10 cycles)
100%
100%
• Constant Acceleration
Method 2001, Cond E (Min.),
Y1 Orientation Only
100%
N/A
• Hermeticity:
-Fine Leak
-Gross Leak
Method 1014, Cond A or B
Method 1014, Cond C
100%
100%
N/A
100%
• Pre-Bum-in Electrical
Parameters
Per Applicable Device
Specification
100%
100%
• Burn-in Test
Method 1015, Cond D,
160 Hrs at 125°C Min. or
80 Hrs at 150°C
100%
100%
(48 Hours at 125 ° C)
• Post-Bum-in Electrical
Parameters
Per Applicable Device
Specification
100%
100%
• Percent Defective
Allowable (PDA)
Maximum PDA, for All Lots
5%
5%
Burn-in
Final Electrical Tests
• Static Tests
Method 5005
Subgroups 1, 2, and 3
100% Test to
Applicable Device
Specification
100% Test to
Applicable
Specification
• Functional Tests
Method 5005
Subgroups 7, 8A, and 8B
100% Test to
Applicable Device
Specification
100% Test to
Applicable
Specification
• Switching
Method 5005
Subgroups 9, 10, and 11
100% Test to
Applicable Device
Specification
100% Test to
Applicable
Specification
• Group A
Method 5005, See Table 4
Sample
Sample
• GroupB
Method 5005, See Table 5
Sample
Sample
• Group C[3j
Method 5005, See Table 6
Sample
Sample
• GroupD[3j
Method 5005, See Table 7
Sample
Sample
100%
100%
Quality Conformance Tests
External Visual
Method 2009
Notes:
2. QML product is allowed a reduction in screening requirements with
DESC approval per MIL-PRF-38535.
3.
8-3
Group C and 0 end-point electrical tests for QMUSMD/Military
Grade products are performed to Group A subgroups 1, 2, 3, 7, 8A,
8B, 9, 10, 11, or per JAN Slash Sheet.
Quality, Reliability, and Process Flows
Thble 4. Group A Test Descriptions
Subgroup
1
Description
Thble 5. Group B Quality lests
Sample Size/Accept No.
Components Modules[4]
Static Tests at 25°C
116/0
116/0
2
Static Tests at
Maximum Rated
Operating Thmperature
116/0
3
Static Tests at
Minimum Rated
Operating Temperature
116/0
116/0
116/0
4
Dynamic Tests at 25°C
116/0
116/0
5
Dynamic Thsts at
Maximum Rated
Operating Thmperature
116/0
116/0
6
Dynamic Thsts at
Minimum Rated
Operating Temperature
116/0
116/0
Quantity/Accept #
orLTPD
Components Modules[4]
Subgroup
Description
2
Resistance to Solvents,
Method 2015
3/0
3/0
3
Solderability,
Method 2003[5]
22/0
3
5
Bond Strengt~
Method 2011[
15/0
NA
~roup ~ test~g is performed for each inspection lot. An inspection lot IS defmed as a group of material of the same device type,
package type and lead finish built within a sixweek seal period and
submitted to Group B testing at the same time.
Thble 6. Group C Quality lests
7
Functional Thsts at 25 ° C
116/0
116/0
Subgroup
8A
Functional Tests at
Maximum Temperature
116/0
116/0
1
8B
Functional Thsts at
Minimum Thmperature
116/0
116/0
9
Switching Tests at 25°C
116/0
116/0
10
Switching Thsts at
Maximum Thmperature
116/0
116/0
11
Switching Thsts at
Minimum Thmperature
116/0
116/0
LTPD
Description
Steady State Life Test,
End-Point Electricals,
Method 1005, Cond D
Components Modules[4]
45/0
15/0
Group C tests for all Military Grade products are performed on
one device type from one inspection lot representing each technology. Sample tests are performed per MIL-PRF-38535/MILST~-883 from each four calendar quarters production of devices,
which is based upon the die fabrication date code.
End-point electrical tests and parameters are performed per the
applicable device specification.
Cypress uses an LTPD sampling plan that was developed by the
Military to assure product qUality. Testing is performed to the subgroups found to be appropriate for the particular device type. All
Military products have a Group A sample test performed on each
inspection lot per MIL-PRF-38535 or MIL-STD-883 and the
applicable device specification.
8-4
Quality, Reliability, and Process Flows
Table 7. Group D Quality Tests (Package Related)
Subgroup
Description
15/0
15/0
Lead Integrity, Seal:
Fine and Gross Leak,
Method 2004 and 1014
45/0[5]
15/0
Thermal Shock, TempCycling, Moisture
Resistance, Seal: Fine
and Gross Leak, Visual
Examination, EndPoint, Electricals,
Methods 1011, 1010,
1004, and 1014
15/0
Mechanical Shock,
Vibration - Variable
Frequency, Constant
Acceleration, Seal:
Fine and Gross Leak,
Visual Examination,
End-Point Electricals,
Methods 2002,2007,
2001, and 1014
15/0
Salt Atmo&here,
Seal: Fine Gross Leak,
Visual Examination,
Methods 1009 & 1014
Internal Water-Vapor
Content; 5000 ppm
maximum @ 100°e.
Method 1018
Adhesion of Lead
Finish, [8]
Method 2025
15/0
1
Physical Dimensions,
Method 2016
2
3
4
5
6
7
8
Lid Torque,
Method 2024[9)
Product Screening Summary Components
QuantitylAccept #
orLTPD
Components Modules[7]
Commercial and Industrial Product
• Screened per Table 1 product assurance flows
• Hermetic and molded packages available
• Incoming mechanical and electrical performance guaranteed:
- 0.02% AQL Electrical Sample test performed on every lot
prior to shipment
- 0.01% AQL External Visual Sample inspection
N/A
for Seal
15/0
• Electrically tested to Cypress data sheet
N/Afor
Moisture
Resistance;
N/Afor
Fine Leak
Ordering Information
• Order Standard Cypress part number
• Parts marked the same as ordered part number
Ex: CY7C122-15PC, PALC22VlO-25PI
Military Product
15/0
N/Afor
Constant
Acceleration;
N/Afor
Fine Leak
• SMD and Military components are manufactured in compliance with paragraph 1.2.1 of MIL-STD-883. Compliant
products are identified by an 'MB' suffix on the part number
(CY7CI22-25DMB) and the letter "c"
• QML devices are manufactured in accordance with MILPRF-38535. Compliant products are identified with the letter
"Q."
• Military devices electrically tested to:
- SMD devices are electrically tested to the applicable standard military drawing specifications
OR
15/0
N/Afor
Fine Leak
3(0) or 5(1)
N/A
15/0
15/0
5(0)
N/A
- Cypress data sheet specifications
• All devices supplied in hermetic packages
• Quality conformance inspection: Method 5005, Groups A, B,
C, and D performed as part of the standard process flow
• Burn-in performed on all devices
- Cypress detailed circuit specification for non-JAN devices
• Static functional and switching tests performed at 25°C as
well as temperature and power supply extremes on 100% of
the product in every lot
Group D tests for all Military Grade procedures are performed
per MIL-PRF-38535IMIL-STD-883 on each package type from
each six months of production, based on the identification (or
date) codes.
End-point electrical tests and parameters are performed per the
applicable device specification.
Ordering Information
SMD Product:
• Order per military document
• Marked per military document
Ex: 5962-8867001LA
Military Modules
• Military Thmperature Grade Modules are designated with an
'M' suffix only. These modules are screened to standard combined flows and tested at both military temperature extremes.
• MIL-STD-883 Equivalent Modules are processed to proposed JEDEC standard flows for MIL-STD-883 compliant
modules. All MIL-STD-883 equivalent modules are assembled with fully compliant MIL-STD-883 components.
Military Product:
• Order per Cypress standard military part number
• Marked the same as ordered part number
Ex: CY7CI22-25DMB
Notes:
4. Military Grade Modules are processed to proposed JEDEC standard
flows for MIL-STD-883 compliant modules. Alternate Group A
method as detailed in JC-13-BP-123A.
5. Sample size is based upon leads taken from a minimum of 3 devices.
6. Sample size is based upon leads taken from a minimum of 4 devices.
7. Does not apply to leadless chip carriers.
8.
9.
8-5
Based on the number ofleads.
Applies only to packages with glass seals.
·~PRESS
Quality, Reliability, and Process Flows
Product Quality Assurance F1ow-Components
•
Area
PROCESS
Process Details
QC
INCOMING MATERIALS
INSPECTION
All incoming materials are inspected to documented procedures covering the
handling, inspection, storage, and release of raw materials used in the
manufacture of Cypress products. Materials inspected are: wafers, masks,
leadframes, ceramic packages and/or piece parts, molding compounds, gases,
chemicals, etc.
FAB
DIFFUSION/ION
IMPLANTATION
Sheet resistance, implant dose, species and CV characteristics are measured
for all critical implants on every product run. Test wafers may be used to collect
this data instead of actual production wafers. If this is done, they are processed
with the standard product prior to collecting specific data. This insures accurate
correlation between the actual product and the wafers used to monitor
implantation.
FAB
OXIDATION
Sample wafers and sample sites are inspected on each run from various
positions of the furnace load to inspect for oxide thickness.The integrity of
critical oxides is monitored at electrical test.
FAB
PHOTOLITHOGRAPHY
/ETCHING
Appearance of resist is checked by the operator after the spin operation. Also,
after the film is developed, both dimensions and appearance are checked by
the operator on a sample of wafers and locations upon each wafer. Final CDs
and alignment are also sample inspected on several wafers and sites on each
wafer on every product run.
FAB
METALIZATION
Film thickness is monitored on a daily basis. Step coverage cross-sections are
performed on a periodic basis to insure coverage.
FAB
PASSIVATION
Film thickness is verified on a sample of wafers and locations on each run. Film
stress is monitored on a weekly basis.
FAB
QC VISUAL OF
WAFERS
FAB
E-TEST
Electrical test is performed for final process electrical characteristics on every
wafer.
FAB
QC MONITOR OF
E-TESTDATA
Weekly review of all data trends; running averages, minimUmS, maximums,
etc. are reviewed with the process control manager.
TEST
WAFER PROBE/SORT
Verify functionality, electrical characteristics, stress test devices.
TEST
QC CHECK PROBING
AND ELECTRICAL
TEST RESULTS
Pass/fail lot based on yield and correct probe placement.
TO ASSEMBLY
AND TEST
(continued)
8-6
Quality, Reliability, and Process Flows
Product Quality Assurance Flow-Components (continued)
Commercial and Industrial Product
COMMERCIAL AND INDUSTRIAL PRODUCT
PLASTIC
ASSEMBLY
FLOW
HERMETIC
ASSEMBLY
FLOW
Wafer Prep/Mount/Saw
Inspect for accurate sawing of
scribeline and 100% saw-through
Die Visual Inspection
Inspect die per Cypress equivalent to
MIL-STD-883, Method 2010, condition B,
only done if gate fails
QC Visual Lot Acceptance
Sample inspect die; LTPD 5%
Die Attach
Attach per Cypress detailed specification
QC Process Monitor
Inspect for die position, quality and uniformity of
die attach and attachment strength, MIL-STD-883,
Method 2010, criteria
Wire Bond
Bond per Cypress detailed specification
QC Process Monitor - Wire Bonding
Monitor bond strength and failure mode
Internal Visual Inspection
Low-power (30x) inspection of workmanship
MIL-STD-883, Method 2010, condition B
QC Visual Lot Acceptance
Sample inspect lot to verify workmanship,
MIL-STD-883, Method 2010, condition B,
criteria; LTPD 5%
Die Coat
Coating applied to selected products
(continued)
8-7
E
"~YPRESS
Quality, Reliability, and Process Flows
Product Quality Assurance FIow-Components (continued)
Commercial and Industrial Product
PLASTIC
HERMETIC
QC Visual Lot Acceptance for Die Coated Products
Mold/Encapsulate Plastic Devices
Seal Hermetic Devices
Periodic QC Monitor, Lid-Torque
Shear strength of glass-frit seal tested
to MIL-STD-883, Method 2024
Post Mold Cure
Per Cypress method for molding compound
Lead Trim/Form
Lead trim and form for plastic devices, lead
trim for hermetic devices (where applicable)
Lot 10
Mark assembly lot on devices
Lead Prep/Finish (Solder Dip) hermetic,
Solder Plate for Plastic
Prepare leads for solder dip, solder dip devices
and inspect for uniform solder coverage
QC Process Monitor
Verify workmanship and solder coverage
Fine and Gross Leak Test
Method 1014, Cond A or 8; fine leak (sample)
Method 1014, Cond C; gross leak (100%)
External Visual Inspection
Inspect for workmanship, construction, cracked or
broken devices, bent leads, crazing, castellation
alignment, and solder coverage.
MIL-STO-883, Method 2009
(continued)
8-8
Quality, Reliability, and Process Flows
Product Quality Assurance Flow-Components (continued)
Commercial and Industrial Product
PLASTIC
HERMETIC
Final Electrical Test
100% test lot; static (DC), functional and switching (AC)
tests perfomed per applicable device specification
Final Device Marking
Final Visual Inspection
Inspect for bent leads, marking, solder coverage, etc.
I QC LOT ACCEPTANCE I
External Visual Sample
Method 2009; 0.065% AQL
Electrical Sample Test
0.02% AQL every lot
Inspection - Pre-Shipment
Confirm part type, count, package, check for
completeness of processing requirements, confirm
supporting documentation is sent, if required
Pack/Ship Order
o
Key
Production Process
D
Test/Inspection
IQI
Production Process and Test Inspection
<>
QC Sample Gate and Inspection
8-9
Quality, Reliability, and Process Flows
Product Quality Assurance F1ow-Components
Military Components
MILITARY ASSEMBLY FLOW
Wafer Prep/Mount/Saw
Inspect for accurate sawing of scribeline and 100% saw-through
Die Visual Inspection
Inspect die per MIL-STD-883, Method 2010, condition B
QC Visual Lot Acceptance
Sample inspect die; 1.0% AQL
Die Attach
Attach per Cypress detailed specification
Die Adherence Monitor
MIL-STD-883, Method 2019 or Method 2027
Wire Bond
Bond per Cypress detailed specification
Bond Pull Monitor
MIL-STD-883, Method 2011
Internal Visual Inspection
Low-power and high-power inspection per
MIL-STD-883, Method 2010, condition B
QC Visual Lot Acceptance
Sample inspect lot per MIL-STD-883,
Method 2010, condition B, 0.4% AQL
Die Coat
Coating applied to selected products
QCVisual Lot Acceptance for Die Coated Products
Seal
Periodic QC Monitor, Lid-Torque
Shear strength of glass
(continued)
8-10
Quality, Reliability, and Process Flows
Product Quality Assurance F1ow-Components (continued)
Military Components
Temperature Cycle
Method 1010, Cond C, 10 cycles
Constant Acceleration
Method 2001, Cond E, Y1 Orientation
Lead Trim
Lead trim when applicable
Lot ID
Mark assembly lot on devices
Lead Finish
Solder dip or matte tin plate applicable devices and inspect
QC Process Monitor
Verify workmanship and lead finish coverage
External Visual Inspection
Method 2009
Pre-Bum-In Electrical Test
Method 5004, per applicable device speCification
Burn-In
Method 1015, condition D
Post-Bum-In Electricals
Method 5004, per applicable device specification
PDA Calculation
Method 5004, 5%
Final Electrical Test
Method 5004; StatiC, functional and switching
tests per applicable device specification
(continued)
8-11
E
'~YPRESS
Quality, Reliability, and Process Flows
Product Quality Assurance Flow-Components (continued)
Military Components
Lead Finish - Solder Dip
Solder dip applicable devices
Fine and Gross Leak Test
Method 1014, condition A or B, fine leak; condition C, gross leak
Final Device Marking
MIL-STD-883 or applicable device specification
Group B
Method 5005
Group A
Method 5005, per applicable device specification
Group C and D
Method 5005, in accordance with
1.2.1 of MIL-STD-883; JAN devices
in accordance with MIL-PRF-38535
External Visual
Method 2009, 100% inspection
External Visual Sample
Method 2009, 0.01 % AQL
Plant Clearance
Pack/Ship Order
Key
o
Production Process
D
Test/Inspection
IQ]
Production Process and Test Inspection
<>
QC Sample Gate and Inspection
8-12
~~
:sa"
Quality, Reliability, and Process Flows
CYPRESS
Product Quality Assurance Flow-Modules
All incoming materials are inspected to documented
procedures covering the handling, inspection, storage,
and release of raw materials used in the manufacture of
Cypress products. Materials inspected are: substrates,
active device packages, chip capacitors, lead frames,
solder paste, inks, chemicals, etc.
Incoming materials
inspection
Kit Picked
Compliance verified, documented,
. and traceability established
Clean
Pre-assembly cleaning of components
Solder Paste Depostion
Screen printed and/or dispensed per detailed specifiction
Component Placement
Robotic and/or manual per detailed specification
Solder Reflow
Microprocessor controlled forced convection
Data logging
(optional)
Clean
Flux removal by
semi-aqueous vapor phase
per detailed specification
AQLvisual
2-sided
o
1-sided
~
c)
100% visual
Double-Sided Assembly
Repeat process for side 2
Solder paste deposition
Component placement
Solder reflow
C)
... .:... -<>
A. ..
V'
Inspect
o
~
c)
C)
Clean
100% visual
2-sided
100% visual
<>-... ...
~
Lead Trim
Electrical Test
(Pre-burn-in test)
(continued)
8-13
Boac 100%
1-sided
Quality, Reliability, and Process Flows
QYPRESS
Product Quality Assurance Flow-Modules (continued)
Burn-In
Method 1015
QC Monitor - Burn-In Documents!
Results
Post-Burn-In Electricals
Per applicable device specification
QC Inspection
PDA verified within limits
Final Device Marking
Final Electrical Test
100% test lot; DC, AC, functional, and dynamic
tests performed per applicable device specification
Final Visual Inspection
Confirm part type, count, package, check for
completeness of processing requirements, confirm
supporting documentation is sent, if required
QA electrical test
(roomtemperature)
Inspection - Pre-Shipment
Pack/Ship Order
o
Key
Production Process
D
TesVlnspection
IQ]
Production Process and Test Inspection
<>
QC Sample gate and inspection
8-14
<>-
Quality, Reliability, and Process Flows
Reliability Monitor Program
Quarterly Reliability Monitor Test Matrix
The Reliability Monitor Program is a documented Cypress procedure that is described in Cypress specification #25-00008, which is
available to Cypress customers upon request. This specification
describes a procedure that provides for periodic reliability monitors to insure that all Cypress products comply with established
goals for reliability improvement and to minimize reliability risks
for Cypress customers. The Reliability Monitor Program monitors
our most advanced technologies and packages. Every technology
produced at a given fabrication site (Tech. - Fab.) and all assembly houses are monitored at least quarterIy.lffailures occur, detailed failure analyses are performed and corrective actions are
implemented. Asummary ofthe Reliability Monitor Program test
and sampling plan is shown below.
Sampling Strategy
Stress
Lots Thsted
per Quarter
HTOL
Thchnology-Fab Location
8
HTSSL
Technology-Fab Location
8
TEV
Technology-Fab Location
8
DRET
Technology-Fab Location
2
HAST
Technology-Fab Location
8
Package-Assembly Location
10
TC
PCT
Technology-Fab Location
8
Package-Assembly Location
12
Package-Assembly Location
10
Reliability Monitor Test Conditions
Abbrev.
Temp. (0C)
R.H.(%)
Bias
Sample
Size
LTPD
(hrs.)
High-Temperature
Operating Life
HTOL
+125
N/A
5.75V Dynamic
116
2
96,500,1000
High-Thmperature SteadyState Life
HTSSL
+125
N/A
5.75V Static
116
2
96,500,1000
Data Retention for
Plastic Packages
DRET
+165
N/A
N/A
76
3
168,1000
Data Retention for
Ceramic Packages
DRET2
+250
N/A
N/A
76
3
168,500
Thst
Pressure Cooker
,
Read Points
PCT
+121
100
N/A
76
3
96, 168
HAST
+140
85
5.5V Static
76
3
128
Thmperature Cycling
TC
-65 to
+150°C
N/A
N/A
45
5
300, 1000 Cycles
Thmperature Extreme
Verification
TEV
Commercial
Hot & Cold
oto +70°C
N/A
N/A
116
2
N/A
Highly Accelerated Stress
Thst
8-15
Packages 9
Package Diagrams
Page Number
Thin Quad Flat Packs ••••••••••.•••••••••••••••••••••••••••••••••••••••••.•...•••••••••••.••••••.•••••.••.
32-Lead Plastic Thin Quad Flat Pack (TQFP) A32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64-Pin Thin Quad Flat Pack A64 ............................................................................
64-Lead Thin Plastic Quad Flat Pack A65 .....................................................................
80-Pin Thin Plastic Quad Flat Pack A80 ......................................................................
l00-Pin Plastic Thin Quad Flat Pack (TQFP) AlOO ............................................................
9-1
9-1
9-2
9-3
9-3
9-4
Ceramic Dual-In-Line Packages. • • • • . • . • • • • • • • • • • • • • • • • • .. • • • • • • • • • • . • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • . .•
16-Lead (300-Mil) CerDIP D2 MIL-STD-1835 D-2 Config. A .................................................
28-Lead (600-Mil) CerDIP 016 MIL-STD-1835 D-lO Config. A ...............................................
28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D-15 Config. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
32-Lead (300-Mil) CerDIP D32 .............................................................................
28-Lead (600-Mil) Sidebraze DIP D43 .......................................................................
9-5
9-5
9-5
9-5
9-6
9-6
Plastic Leaded Chip Carriers ...............................................................................
28-Lead Plastic Leaded Chip Carrier J64 .....................................................................
32-Lead Plastic Leaded Chip Carrier J65 .....................................................................
52-Lead Plastic Leaded Chip Carrier J69 .....................................................................
68-Lead Plastic Leaded Chip Carrier J81 .....................................................................
84-Lead Plastic Leaded Chip Carrier J83 .....................................................................
9-7
9-7
9-7
9-8
9-8
9-8
Ceramic Leadless Chip Carriers ............................................................................ 9-9
32-Pin Rectangular Leadless Chip Carrier L55 MIL-STD-1835 C-12 ........................................... 9-9
28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 .................................................... 9-9
52-Square Leadless Chip Carrier L69 ........................................................................ 9-9
68-Square Leadless Chip Carrier L81 MIL-STD-1835 C-7 ................................................... 9-10
Plastic Quad Flatpacks ................................................................................... 9-11
52-Lead Plastic Quad Flatpack N52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-11
80-Lead Plastic Quad Flatpack N80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-12
Plastic Dual-In-Line Packages .............................................................................
28-Lead (600-Mil) Molded DIP PIS ........................................................................
28-Lead (300-Mil) Molded DIP P21 ........................................................................
48-Lead (600-Mil) Molded DIP P25 ........................................................................
9-13
9-13
9-13
9-13
Plastic Small Outline ICs .................................................................................
24-Lead (300-Mil) Molded SOIC S13 .......................................................................
28-Lead 450-Mil (300-MiI Body Width) SOIC S22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28-Lead (300-Mil) Molded SOJ V21 ........................................................................
9-14
9-14
9-15
9-15
Ceramic Windowed Dual-In-Line Packages •.••••.•••••••••••••••••••••••••••••••.•••.••••.••••••••.••••••••• 9-16
28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D-15 Config. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-16
CeramicJ-LeadedChipCarriers ........................................................................... 9-17
84-Pin Ceramic Leaded Chip Carrier Y84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-17
Package Diagrams
Thin Quad Flat Packs
32-Lead Plastic Thin Quad Flat Pack (TQFP) Al2
DIMENSIONS IN MILLIMETERS
LEAD COPLANARITY 0.080 MAX.
0.60±0.15
1.00 REF. -+---1
,
~l
ll/13'
DIM. Al
-(8X)
1.40±0.05 PKG. THICK
1.00±0.05 PKG. THICK
~
~A~t--dJ-;;;:t{;;:;u::;:tj:;:;:tj;;::;:tj;::;tl:::;:H:;:::tj:;::tj;::;=\t~
~
n-
0.20 MAX.
9-1
Package Diagrams
IBrcYPRESS
Thin Quad Flat Packs (continued)
64-Pin Thin Quad Flat Pack AM
~":~~:::: ~
DIMENSIONS IN MILLIMETERS
LEAD CDPLANARITY 0,080 MAX,
1
0.50 BSC.
R 0,08 MIN,
0.20 MAX.
~E~~~NG~
I
1.60 MAX.
t
____ ,-____________~.~--L
0.20 MAX.
9-2
Package Diagrams
Thin Quad Flat Packs (continued)
64-Lead Thin Plastic Quad Flat Pack A65
DIMENSIONS IN MILLIMETERS
LEAD CDPLANARITY 0,100 MAX,
0,80 TYP,
~~~,"m
l
IT
!
6·±4·
1.60 MAX,
005
1.40±0,05
MIN~ ,-J1[0::
017 MAX,
i
015 MAX,
STANDOFF
0.60 :~::~
80-Pin Thin Plastic Quad Flat Pack A80
DIMENSIONS IN MILLIMETERS
LEAD COPLANARITY 0.080 MAX.
0.08/0.20 R.
STAND-OFF
~
~ GAUGE
PLANE
0-7"
1.00 REF.
DIM. A
1.60 MAX.
1.20 MAX.
"/13'
~1-----.l
-(8X)
~
DIM. Al
1.40±O.05 PKG. THICK
1.00±O.05 PKG. THICK
I
Tt== Jbfi~iJn~nimniniJnunimniniJn~nmn~niniJninimniHiJn~~~~Al
0.20 MAX.
9-3
Package Diagrams
d Flat P aCks (continued)
Thin Qua
. Plastic Thm
. Quad Flat Pa
lOO-Pm
rt::::~::
ck (TQFP) AlOO
=:J
l1F
160 MAX,
020 MAX,
=rl'~"
~
0,50
TYP.
9-4
= 7~
~;CYPRESS
Package Diagrams
Ceramic Dual-In-Line Packages
16-Lead (300-MiI) CerDIP D2
28-Lead (300-Mil) CerDIP D22
MIL-SID-1835 0-2 Config. A
MIL-STO-1835 D-15 Config. A
Cj
IN 1
.155
.200
DIMENSIONS IN INCHES
~l~.
---.
.245
~O
~~f--~~§ .7~0:5~MIN.
--Il--rJ(
tJ _.
-785
BASE PLANE
1--.290 --1
.~~~
1,·320,1
r~jt~.··"';"" ~ . ~L
·~tt:~
065
015
.020
110
SEA TING PLANE
15°
.330
.390
28-Lead (600-MiI) CerDIP 016
MIL-SID-1835 0-10 Config. A
OD
IN I
DIMENSIONS IN INCHES
MIN,
MAX,
.505
.550
J
d i=r
FITTIi~
~~I50
IY-
II- ~
-j
.
.005 MIN.
~~~rI490
1.450
'jt
.015
.020
--Il,
I
'200~V
.125
1
.~~~
.::;~ri
MIN.
.045
.090
TID
BASE PLANE
I
.009
,012
~._ J_
\
~.630~r
.690
.065
SEATING PLANE
I
9-5
Package Diagrams
Ceramic Dual-In-Line Packages (continued)
32-Lead (300-MiI) CerDIP D32
b;Jd
j
IN!
MAX,
d
~
,005 MIN,
---II--
1.640
m~·
MIN,
t
.245
I
,065
.095
DIMENSIONS IN INCHES
--r
JlfnT
125~~
~ ~r'50
,200
T
jt~~~
BASE PLANE
·I:~~
1.685
-If--~
}fttj{\
MIN,
.045
,090
.065
,110
\,~~:~
L.~~~-=:r
3·
W
SEATING PLANE
28-Lead (600-Mil) Sidebraze DIP D43
DIMENSIONS IN INCHES
MIN,
MAX,
PIN 1
,550
];fO
:"'-"-"~~~.-.,i~
-I L020
,080
---JL ,005
I
~~
1.370
,200 1 1 1 . 4 3 0
J..Q.Q.
.125
160
:~~~jt
,015
,022
MIN,
~
-1l- :~?ooT~r~,
SEA TING PLANE
9-6
BASE
PLANE
,030
,060
f==1
L:~~~-Ij
590
,620
-=..
~rcYPRESS
Package Diagrams
Plastic Leaded Chip Carriers
28-Lead Plastic Leaded Chip Carrier J64
DIMENSIONS IN INCHES MIN,
MAX,
PIN 1
rrr
--.1
---,-
~
~
0.495
0.055
M2Q
0.458
~~~
0.495
32-Lead Plastic Leaded Chip Carrier J65
DIMENSIONS IN INCHES MIN,
MAX,
0,045
TYP, l~t~~~=:,:,=PI~N~'=TI
n
0'045J[jl-=1tTYP,
0,025
TYP,
=
0.595
0.490
0.530
Q,24Z
0,553
B
~
0.032
O'050 REF,
I-Mfl
0.453
~
0.495
0.065
0,095
llliQ
0,140
I
9-7
Package Diagrams
Plastic Leaded Chip Carriers (continued)
52-Lead Plastic Leaded Chip Carrier J69
DIMENSIONS IN INCHES MIN,
MAX,
PIN 1
.Q,12Q
0,756
~J J
t
0,020 MIN,
Q&2Q
0.130
0.165
0.200
68-Lead Plastic Leaded Chip Carrier J81
DIMENSIONS IN INCHES MIN,
MAX,
PIN 1
Q&2Q.
0,930
0.950
0.958
84-Lead Plastic Leaded Chip Carrier J83
DIMENSIONS IN INCHES MIN,
MAX,
PIN 1
lJllO:
1.195
~
1.158
0.026
0,032
0020 MIN,
JlJl2Q
~
n;::>nn
9-8
0130
Package Diagrams
:"rcYPRESS
Ceramic Leadless Chip Carriers
52-Square Leadless Chip Carrier L69
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
DIMENSIONS IN INCHES
MIN.
MAX.
DIMENSIONS IN INCHES
MIN.
MAX,
.045
.055
.008 R.
32 PLACES
~~
090
.008 R.
52 PLACES
C
1
IOlf:
~
~mdJ
050
C.740._
.761
T
i
~
.086
.100
.072
.088
t
.458
2S·Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
DIMENSIONS IN INCHES
MIN.
BOTTOM
MAX.
045
.055
~
TOP
'064
.078
.045
.066
SIDE
I
9-9
Package Diagrams
Ceramic Leadless Chip Carners (continued)
6S.Square Leadless Chip Carrier LS1
MIL-STD-1835 C-7
DIMENSIONS IN INCHES
MIN,
MAX,
,045
,055
,008 R,
68 PLACES
9-10
ZP-.."...
-
-.,-#=
"CYPRESS =============~P;ac;;ka~ge~D;;i~ag~r;am;;s
Plastic Quad Flatpacks
52-Lead Plastic Quad Flatpack NS2
N
DIMENSIONS ARE IN MILLIMETERS
LEAD CDPLANARITY 0,102 MAX,
lS,:::::.:: ::~J
I
9-11
Package Diagrams
QYPRESS
Plastic Quad Flatpacks (continued)
SO-Lead Plastic Quad Flatpack N80
N
DIMENSIONS ARE IN MILLIMETERS
LEAD rnPL.ANARITY 0.102 MAX,
<.,"n~
SEATING PLAN \
,
~'~~~OOS
+
JL
o·-s·
R. 0,20 TYP,
9-12
O,SO±O,IS
~~
Package Diagrams
~_" CYPRESS
Plastic Dual-In-Line Packages
28-Lead (600-MiI) Molded DIP P15
PIN 1
DIMENSIONS IN INCHES MIN,
MAX,
r--
Ir-
0570
-----1
0625~1
Mill.W
0012
3 'MIN
Q&lQ-------l
0.685
28-Lead (300-MiI) Molded DIP P21
oq~l
DIMENSIONS IN INCHES Ml!i
MAX,
~
~o
I
I-
0.030
0,080
Lm!
~J
r=--!
Ir0 11
1425
~
!lHl!
rub 01~0
0160
325
Mil . i8l\
~~ 3'
0012+
r QJI.2Q
0,110
,
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DIMENSIONS IN INCHES MIN,
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Plastic Small Outline ICs
24·Lead (300·MiI) Molded
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PIN 1 ID
DIMENSIONS IN INCHES
MIN,
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Package Diagrams
Plastic Small Outline ICs (continued)
28·Lead 4S0.Mil (300·Mil Body Width)
sOle S22
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(,mQ = ANAM DIMENSIONS
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DIMENSIONS IN INCHES MIN.
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SEATING PLANE
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DIMENSIONS IN INCHES
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0.013
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0.272
0.025 MIN.
I
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Package Diagrams
Ceramic Windowed Dual-In-Line Packages
2S-Lead (300-MiI) Windowed CerDIP W22
MIL-STD-1835 D-15 Config. A
.140 X .300 DR
,140 X .400
GLASS LENS
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DIMENSIONS IN INCHES
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Package Diagrams
=t: ?cYPRESS
Ceramic J-Leaded Chip Carriers
84-Pin Ceramic Leaded Chip Carrier Y84
DIMENSIONS IN INCHES
MIN.
MAX.
PIN 1
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1.185
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I
9-17
trCYPRESS
Sales Representatives and Distributors
Domestic Direct Sales Offices
Corporate Headquarters
Cypress Semiconductor
3901 N. First Street
San Jose, CA 95134
(408) 943-2600
Telex: 821032 CYPRESS SNJ UD
TWX: 910 997 0753
FAX: (408) 943-2741
IC Designs Division
12020-113th Ave. N.E.
Kirkland, WA 98034
(206) 821-9202
FAX: (206) 820-8959
Alabama
Cypress Semiconductor
4940B Corporate Drive
Huntsville, AL 35805
(205) 721-9500
FAX: (205) 721-0230
California
Northwest Sales Office
Cypress Semiconductor
100 Century Center Court
Suite 340
San Jose, CA 95112
(408) 437-2600
FAX: (408) 437-2699
Cypress Semiconductor
2 Venture Plaza, Suite 460
Irvine, CA 92718
(714) 753-5800
FAX: (714) 753-5808
Cypress Semiconductor
12526 High Bluff Dr., Ste. 300
San Diego, CA 92130
(619) 755-1976
FAX: (619) 755-1969
Cypress Semiconductor
20121 Ventura Blvd.
Suite 104
Woodland Hills, CA 91367
(818) 704-6565
FAX: (818) 704-6045
Canada
Cypress Semiconductor
701 Evans Avenue
Suite 312
Thronto, Ontario M9C 1A3
(416) 620-7276
FAX: (416) 620-7279
Colorado
Cypress Semiconductor
4704 Harlan St., Suite 360
Denver, CO 80212
(303) 433-4889
FAX: (303) 433-0398
Florida
Cypress Semiconductor
13535 Feather Sound Drive
Suite 130
Oearwater, FL 34622
(813) 968-1504
Cypress Semiconductor
255 South Orange Avenue
Suite 1255
Orlando, FL 32801
(407) 422-0734
FAX: (407) 422-1976
Cypress Semiconductor
1000 W. McNab Road
Pompano Beach, FL 33069
(954) 943-9295
FAX: (954) 943-4057
Georgia
Cypress Semiconductor
1080 Holcomb Bridge Rd.
Building 200, Ste. 265
Roswell, GA 30076
(770) 998-0491
FAX (770) 998-2172
Illinois
Cypress Semiconductor
1530 E. Dundee Rd., Ste. 190
Palatine, IL 60067
(847) 934-3144
FAX: (847) 934-7364
Maryland
Cypress Semiconductor
8850 Stanford Blvd., Suite 1600
Columbia, MD 21045
(410) 312-2911
FAX: (410) 290-1808
Minnesota
Cypress Semiconductor
14525 Hwy. 7, Ste. 360
Minnetonka, MN 55345
(612) 935-7747
FAX: (612) 935-6982
New Hampshire
Cypress Semiconductor
61 Spit Brook Road, Ste. 550
Nashua, NH 03060
(603) 891-2655
FAX: (603) 891-2676
New Jersey
Cypress Semiconductor
100 Metro Park South
3rdFloor
Laurence Harbor, NJ 08878
(908) 583-9008
FAX (908) 583-8810
New York
Cypress Semiconductor
22 IBM Road
Suite 103B
Poughkeepsie, NY 1260
(914) 463-3218
FAX: (914) 463-3220
North Carolina
Cypress Semiconductor
7500 Six Forks Rd., Suite G
Raleigh, NC 27615
(919) 870-0880
FAX: (919) 870-0881
Oregon
Cypress Semiconductor
8196 S.w. Hall Blvd. Suite 100
Beaverton, OR 97005
(503) 626-6622
FAX: (503) 626-6688
Pennsylvania
Cypress Semiconductor
Tho Neshaminy Interplex, Ste. 206
'frevose, PA 19053
(215) 639 - 6663
FAX: (215) 639-9024
Texas
Cypress Semiconductor
101 W. Renner Rd, Suite 155
Richardson, TX 75082 - 2002
(214) 437-0496
FAX: (214) 644-4839
Cypress Semiconductor
8834 Capital of Texas Highway North
Suite 220
Austin, TX 78759
(512) 418-4205
FAX: (512) 418-4201
Cypress Semiconductor
20405 SH 249, Ste. 215
Houston, TX 77070
(713) 370-0221
FAX: (713) 370-0222
-==--.
z;;~
"7 CYPRESS
====S;;;;;;a;;;;;;le;;;;;;s;;;;;;R;;;;;;e;;;;;;p;;;;;;r;;;;;;e;;;;;;s;;;;;;eD;;;;;;t;;;;;;a;;;;;;ti;;;;;;v;;;;;;e;;;;;;s;;;;;;a;;;;;;D;;;;;;d;;;;;;D;;;;;;i;;;;;;s;;;;;;tr;;;;;;i;;;;;;bu;;;;;;t;;;;;;o;;;;;;r=s
Domestic Sales Representatives
Alabama
Giesting & Associates
4835 University Square
Suite 15
Huntsville, AL 35816
(205) 830-4554
FAX: (205) 830-4699
Arizona
Thorn Luke Sales, Inc.
9700 North 91st St., Suite A-200
Scottsdale, AZ 85258
(602) 451-5400
FAX: (602) 451-0172
California
TAARCOM
451 N. Shoreline Blvd.
Mountain View, CA 94043
(415) 960-1550
FAX: (415) 960-1999
TAARCOM
735 Sunrise Ave., Suite 200-4
Roseville, CA 95661
(916) 782-1776
FAX: (916) 782-1786
Technology Solutions Company
5525 Oakdale Ave., Suite 275
Woodland Hills, CA 91364
(818) 704-1693
FAX: (818) 704-6165
Technology Solutions Company
10 Hughes, Suite AZ01
Irvine, CA 92718
(714) 707-4565
FAX: (714) 707-4510
Canada
bbd Electronics, Inc.
6685 -1 Millcreek Dr.
Mississauga, Ontario LSN 5M5
(905) 821-7800
FAX: (905) 821-4541
bbd Electronics, Inc.
298 Lakeshore Rd., Ste. 203
Pointe Claire, Quebec H9S 4L3
(514) 697-0801
FAX: (514) 697-0277
bbd Electronics, Inc. - Ottawa
(613) 564-0014
FAX: (416) 821-4092
bbd Electronics, Inc. - Winnipeg
(204) 942-2977
FAX: (416) 821-4092
Western Canada
Microwe Electronics Corporation
Site #7, Box 40 R.R.1
Dewinton, Alberta, Canada TOL OXO
(403) 254-4180
FAX: (403) 256-0942
Colorado
Lange Sales
1500 W. Canal Court, Bldg. A
Suite 100
Littleton, CO 80120
(303) 795 - 3600
FAX: (303) 795-0373
Georgia
Giesting & Associates
2434 Highway 120
Suite 108
Duluth, GA 30155
(770) 476-0025
FAX: (770) 476-2405
Idaho
Sierra Technical Sales
10378 Fairview
Suite 246
Boise, ID 83704
(208) 378-8981
FAX: (208) 378-0228
Illinois
Micro Sales Inc.
901 W. Hawthorn Drive
Itasca, IL 60143
(708) 285 -1000
FAX: (708) 285 -1008
Indiana
Technology Mktg. Corp.
1526 East Greyhound Pass
Carmel, IN 46032
(317) 844-8462
FAX: (317) 573-5472
Thchnology Mktg. Corp.
4630-10 W. Jefferson Blvd.
Ft. Wayne, IN 46804
(219) 432-5553
FAX: (219) 432-5555
Technology Marketing Corp.
1214 Appletree Lane
Kokomo, IN 46902
(317) 459-5152
FAX: (317) 457-3822
Iowa
Midwest Thchnical Sales
463 Northland Ave., N.E.
Suite 101
Cedar Rapids, IA 52402
(319) 377-1688
FAX: (319) 377-2029
Kansas
Midwest Technical Sales
13 Woodland Dr.
Augusta, KS 67010
(316) 775-2565
FAX: (316) 775-3577
Midwest Technical Sales
10,000 College Blvd.
Suite 240
Overland Park, KS 66210
(913) 338-2400
FAX: (913) 338-0404
Kentucky
Technology Marketing Corp.
100 nade Street, Suite 1A
Lexington, KY 40510-1007
(606) 253 -1808
FAX: (606) 253-1662
Maryland
ni-Mark, Inc.
1410 Crain Highway, N.W.
Suite 4B
Glen Burnie, MD 21061
(410) 761-6000
FAX: (410) 761-6006
Massachusetts
The Nashoba Group
321 Billerica Rd.
Chelmsford, MA 01824
(508) 256-9900
FAX: (508) 256-1142
Mexico
Ciber Electronica, S.A. de C. V.
Prolongacion Arbol No. 33
Col. Chapalita Sur
45000 Guadalajara, Jal.
Mexico
Tel: (52) 3-647-5217
Tel: (52) 3-647-1998
FAX: (52) 3-121-3331
Ciber Electronica, S.A. de C. V.
Monrovia No. 410
Col. Portales
03300 Mexico, D.E
Thl & FAX: (52) 5-539-7832
Ciber Electronica, S.A. de C.V.
Missouri No. 202 aTE.
Col. del Valle
66220 Garza Garcia, N .L.
Mexico
Tel & FAX: (52) 8-356-842
Michigan
Thchrep
2200 North Canton Center Rd.
Suite 110
Canton, MI 48187
(313) 981-1950
FAX: (313) 981-2006
Minnesota
Matrix Marketing, Inc.
5001 West 80th Street, Suite 375
Bloomington, MN 55437
(612) 835-6977
FAX: (612) 835-6822
Missouri
Midwest Technical Sales
4203 Earth City Expwy., #149
Earth City, MO 63045
(314) 298-8787
FAX: (314) 298-9843
Nevada
TAARCOM
735 Sunrise Ave.
Suite 200-4
Roseville, CA 95661
(916)782-1776
FAX: (916) 782-1786
~CYPRESS
Sales Representatives and Distributors
Domestic Sales Representatives (continued)
New Jersey
GroupThc
111 Howard Blvd.
Suite 212
Mt. Arlington, NJ 07856
(201) 398-1200
FAX: (201) 398-3344
New Mexico
Thom Luke Sales
(719) 661-8795
FAX: (602) 451-0172
New York
Reagan/Compar
815 Montrose Thrnpike
Owego, NY 13827
(716) 271-2230
FAX: (716) 381-2840
Reagan/Compar
44 Riverferry Way
Rochester, NY 14608
(716) 454-3350
FAX: (716) 454-4230
Reagan/Compar
532 Benton Street
Rochester, NY 14620
(716) 473-6070
FAX: (716) 473-6075
Reagan/Compar
3301 Country Club Road
Ste.2211
P.O. Box 135
Endwell, NY 13760
(607) 754-2171
FAX: (607) 754-4270
North Carolina
Quantum Marketing
6604 Six Forks Rd., Ste. 102
Raleigh, NC 27615
(919) 846-5728
FAX: (919) 847-8271
Quantum Marketing
4801 E. Independent Blvd.
Ste.1000
Charlotte, NC 28212
(704) 536-8558
FAX: (704) 536-8768
Ohio
KW Electronic Sales, Inc.
8514 North Main Street
Dayton, OH 45415
(513) 890-2150
FAX: (513) 890-5408
KW Electronic Sales, Inc.
3645 Warrensville Center Rd. #244
Shaker Heights, OH 44122
(216) 491-9177
FAX: (216) 491-9102
Oregon
Northwest Marketing Associates
4905 SW Griffith Drive
Suite 106
Beaverton, OR 97005
(503) 644-4840
FAX: (503) 644-9519
Pennsylvania
KW Electronic Sales, Inc.
4068 Mt. Royal Blvd., Ste. 110
Allison Park, PA 15101
(412) 492-0777
FAX: (412) 492-0780
Omega Electronic Sales, Inc.
Four Neshaminy Interplex, Ste. 101
nevose, PA 19053
(215) 244-4000
FAX: 244-4104
Puerto Rico
Electronic Thchnical Sales
P.O. Box 10758
Caparra Heights Station
San Juan, P.R. 00922
(809) 781-1313
FAX: (809) 781-2020
Tenessee
Giesting & Associates
475 Arrowhead Springs Lane
Versailles, KY 40383
(606) 873 - 2330
Utah
Sierra Thchnical Sales
1192 E. Draper Parkway
Suite 103
Draper, UT 84020
(801) 571-8195
FAX: (801) 571-8194
Washington
Northwest Marketing Associates
12835 Bellevue-Redmond, Ste. 330N
Bellevue, WA 98005
(206) 455-5846
FAX: (206) 451-1130
Wisconsin
Micro Sales Inc.
210 Regency Court
Suite 100
Brookfield, WI 53045
(414) 786-1403
FAX: (414) 786-1813
Sales Representatives and Distributors
International Direct Sales Offices
Cypress Semiconductor
International-Europe
Avenue Ernest Solvay, 7
B-1310 La Hulpe, Belgium
Thl: (32) 2-652-0270
Thlex: 64677 CYPINT B
FAX: (32) 2-652-1504
Cypress Benelux
Heilig Hartstraat 14
2600 Berchem - Antwerpen
Belgium
Thl: (32) 3-230-80-55
FAX: (32) 3-230-98-51
France
Cypress Semiconductor France
Miniparc Bat. no 8
Avenue des Andes, 6
Z.A. de Courtaboeuf
91952 Les Vlis Cedex, France
Tel: (33) 1-69-29-88-90
FAX: (33) 1-69-07-55-71
Germany
Cypress Semiconductor GmbH
Muenchner Str. 15A
85604, Zorneding, Germany
Tel: (49) 81-06-2855
FAX: (49) 81-06-20087
Italy (continued)
Cypress Semiconductor
Via Gallarana 4
20052 Monza, Milano, Italy
Thl: (39) 202-7099
FAX: (39) 202-7101
Japan
Cypress Semiconductor Japan KK
Shinjuku·Marune Bldg.
1-23 -1 Shinjuku
Shinjuku·ku, Tokyo, Japan 160
Tel: (81) 3-5269-0781
FAX: (81) 3-5269-0788
Cypress Semiconductor Japan KKOsaka Sales Office
Sanmoto Bldg. 4F
4-2-18 Minamihonmachi
Chyuo·ku, Osaka, 541 Japan
Tel: (81) 6-241-4774
FAX: (81) 6-241-4940
Singapore
Cypress Semiconductor Singapore
583 Orchard Road, #11-03 Forum
Singapore 0923
Tel: (65) 735-0338
FAX: (65) 735-0228
Sweden
Cypress Semiconductor Scandinavia AB
Marknadsvagen 15
Box 1114
S-18311 Thby, Sweden
Tel: (46) 8 638 0100
FAX: (46) 8 792 1560
Taiwan, R.O.C.
Cypress Semiconductor Taiwan
11F, RM 1102, No. 333
Section 1, Keelung Rd.,
Thipei, Taiwan, R.O.c.
Thl: (886) 2-757 -6898
FAX: (886) 2-757-6892
United Kingdom
Cypress Semiconductor U.K, Ltd.
Gate House
Fretherne Road
Welwyn Garden City
Herts., V.K. ALB 6NS
Tel: (44) 707-33-88-88
FAX: (44) 707-33-88-11
Cypress Semiconductor Manchester
27 Saville Rd. Cheadle
Gatley, Cheshire, V.K
Thl: (44) 614-28-22-08
FAX: (44) 614-28-0746
Italy
Cypress Semiconductor Italy
Interporto di Thrino
Prima Strada n. 5IB
10043 Orbassano (TO), Italy
Thl: (39) 11-397-57-57
FAX: (39) 11-397-58-10
International Sales Representatives
Australia
Belgium
Braemac Pty. Ltd.
1/59-61 Burrows Road
Alexandria, Sydney 2015, Australia
Thl: (61) 2-550-6600
FAX: (61) 2-550-6377
N.V. Memec Benelux
Sint·Lambertusstraat 135
1200 Brussels, Belgium
Tel: (32) 2-778-9850
FAX: (32) 2-778-9858
Braemac Pty. Ltd.
6/417 Ferntree Gully Rd.
Mt. Waverly, Victoria 3149, Australia
Thl: (61) 3-540-0100
FAX: (61) 3-540-0122
Sonetech/Arcobel
Limburgstirumlaan 243, B-2
1780 Wemmel, Belgium
Tel: (32) 2-460-0707
FAX: (32) 2-460-1200
Braemac Pty. Ltd.
300 Gilles Street
Adelaide, SA 5000, Australia
Tel: (61) 8-232-5550
FAX: (61) 8-232-5551
Braemac Pty Ltd.
345 Harborne Street
Herdsman w.A. 6017, Australia
Tel: (61) 9-443-5122
FAX: (61) 9-443-5262
Austria
Eurodis Electronics GmbH
Lamenzanstrasse 10
1232 Wien, Austria
Thl: (43) 1-610-62-128
FAX: (43) 1-610-62-151
Denmark
Tech·Partner NS
Tomsagervej 18
8230 Aabyhoj (Aarhus)
Finland
ScandComp Finland OY
Asemakuja 2 A
02 770 Espoo, Finland
Tel: (358) 0 61352695
FAX: (358) 0 61352620
France
Arrow Electronics
73/79, Rue des Solets
Silic 585
94653 Rungis Cedex
Tel: (33) 1 49 78 49 78
FAX: (33) 1 49 78 05 96
Tel: (45) 87 -46-1600
FAX: (45) 87-46-1616
Newtek
Rue de I;Esterel, 8, Silic 583
94663 Rungis Cedex, France
Tel: (33) 1-46-87-22-00
FAX: (33) 1-46-87-80-49
Tharn Tech
Bygstubben 3
2950 Vedbaek, Denmark
Tel: (45) 45-66-25-00
FAX: (45) 45-66-02-44
Scaib,SA
6 Rue Ambroise Croizat
91127 Palaiseau Cedex, France
Tel: (33) 1-69-19-89-00
FAX: (33) 1-69-19-89-20
Denmark
"?cYPRESS ====S;;;;;;a;;;;;;le;;;;;;s;;;;;;R;;;;;;e;;;;;;p=r;;;;;;e;;;;;;s;;;;;;eD;;;;;;t;;;;;;a;;;;;;ti;;;;;;v;;;;;;e;;;;;;s;;;;;;a;;;;;;D;;;;;;d;;;;;;D;;;;;;i;;;;;;s;;;;;;tn;;;;;;O;;;;;;h;;;;;;u;;;;;;to;;;;;;r=s
International Sales Representatives (continued)
Germany
AktiveRep Electronic GmbH
Kennedy Strasse 5
75438 Knittlingen, Germany
Thl: (49) 70-43-94 0012
FAX: (40) 70-43-334 92
AktiveRep Electronic GmbH
Obenitterstr. 21
42719 Solingen, Germany
Tel: (49) 212-230-4046
FAX: (49) 212-230-4023
CED Ditronic GmbH
Julius-Hoelder Str. 42
70597 Stuttgart, Germany
Thl: (49) 711-72001-0
FAX: (49) 711-7289780
CED Ditronic GmbH
30539 Hannover, Germany
Tel: (49) 511-8764-0
FAX: (49) 511-8764-160
CED Ditronic GmbH
85551 Kirchheim, Germany
Tel: (49) 89-903 8551
FAX: (49) 89-903 0944
Metronik GmbH
Leonhardsweg 2
82008 Unterhaching, Germany
Thl: (49) 89-61108-0
FAX: (49) 89-6116468
Metronik GmbH
16548 Glienicke, Germany
Thl: (49) 3305-68450
FAX: (49) 3305-684550
Metronik GmbH
44319 Dortmund, Germany
Thl: (49) 231-9271100
FAX: (49) 231-92711099
Metronik GmbH
69221 Dossenhem, Germany
Thl: (49) 6221-87044
FAX: (49) 6221-87046
Metronik GmbH
04207 Leipzig, Germany
Tel: (49) 341-4239413
FAX: (49) 341-4239424
Metronik GmbH
25451 Quickbom, Germany
Tel: (49) 41-06-77 30 50
FAX: (49) 41-06-77 30 52
Metronik GmbH
70597 Stuttgart, Germany
Thl: (49) 711-764033
FAX: (49) 711-7655181
Metronik GmbH
65205 Wiesbaden, Germany
Thl: (49) 611-973840
FAX: (49) 611-9738418
SASCOGmbH
Hermann-Oberth-Strasse 16
85640 Putzbrunn, Germany
Thl: (49) 89-4611-211
FAX: (49) 89-4611-271
Germany (continued)
SASCOGmbH
10553 Berlin, Germany
Tel: (49) 30-349-9240
FAX: (49) 30-349-52 36
SASCOGmbH
44149 Dortmund, Germany
Thl: (49) 231-1797 91
FAX: (49) 231-17 29 91
SASCOGmbH
60599 Frankfurt, Germany
Thl: (49) 69-9613640
FAX: (49) 69-6188 24
SASCOGmbH
22850 Norderstedt, Germany
Thl: (49) 40-52-87460
FAX: (49) 40-52-874622
SASCOGmbH
70184 Stuttgart, Germany
Tel: (49) 711-21 0710
FAX: (49) 711-23 39 63
SASCOGmbH
79224 Umkirch bei Freiburg
Germany
Tel: (49) 7665-70 18
FAX: (49) 7665-8778
Hong Kong
Tekcomp Electronics, Ltd.
Rm. 913-914 Bank Centre
636, Nathan Road, Mongkok
Knwloon, Hong Kong
Tel: (852) 2-710-8121
Thlex: 38513 TEKHL
FAX: (852) 2-710-9220
India
Spectra Innovations Inc.
Manipal Centre, Unit No. S-822
47, Dickenson Rd.
Bangalore-560,042
Karnataka, India
Tel: (91) 80-558-8323/3977
FAX: (91) 80-558-6872
Israel
ThIviton Electronics
p.o. Box 21104
11 Halgilgal Street
52167 Ramat Gan
Thl: (972) 3-5799457
Thlex: 33400 VITKO
FAX: (972) 3-6183996
Italy
Silverstar Ltd. SPA
Viale Fulvio Thsti, 280
20126 Milano, Italy
Thl: (39) 2 661251
FAX: (39) 2 66101359
Italy (continued)
CEDItaly
Via Volta 54
20090 Cusago (MI)
Italy
Thl: (39) 2 903361
FAX: (39) 2 90390757
ECC Electronica S.P.A.
Via C. Goldoni 29
20090 Trezzano SuI NavigIo (Milano)
Italy
Tel: (39) 2 48401547
FAX: (39) 248401599
Japan
Thmen Electronics Corp.
2-1-1 Uchisaiwai-cho, Chiyoda-ku
Thkyo, 100 Japan
Thl: (81) 3-3506-3673
Telex: 23548 TMELCA
FAX: (81) 3-3506-3497
Fuji Electronics Co., Ltd.
Ochanomizu Center Bldg.
3-2-12 Hongo, Bunkyo-ku
Tokyo, 113 Japan
Tel: (81) 3-3814-1416
Thlex: J28603 FUJITRON
FAX: (81) 3-3814-1414
Ryoyo Electro Corporation
Konwa Bldg., 1-12-22 'Thukiji,
Chuo-ku, Tokyo 104 Japan
Thl: (81) 3-3546-5088
FAX: (81) 3-3546-5044
Korea
Logicom Inc.
5th Hoor, Haesung Bldg.
2-46 Yangjae-Dong
Seocho-ku
Seoul, Korea 137-131
Tel: (82) 2-575-3211
FAX: (82) 2-576-7040
Netherlands
Memec Benelux B. Y.
Insulindelaan 134
5613 BT Eindhoven
The Netherlands
Tel: (31) 40265-9399
FAX: (31) 40 265-9393
Sonetec Nederland B.Y.
Gulberg 33
5674 TE Nuenen
The Netherlands
Thl: (31) 40-2-635-635
FAX: (31) 40-2-832-300
Norway
Acte Nc Norway AS
Vestvollveien 10
2020 Skedsmokorset
Norway
Thl: (47) 638 98969
FAX: (47) 638 98979
~rcYPRESS ====S;;;;;3;;;;;le;;;;;s;;;;;R;;;;;e;;;;;p;;;;;r;;;;;e;;;;;s;;;;;eD;;;;;t;;;;;3;;;;;tI;;;;;"V;;;;;e;;;;;s;;;;;3;;;;;D;;;;;d;;;;;D;;;;;i;;;;;s;;;;;tr;;;;;ih;;;;;u;;;;;t;;;;;o;;;;;r=s
International Sales Representatives (continued)
Portugal
AID Electronica S.A.
Avenida das Laranjeiras, Lote 20
2720 Alfragide (Lisboa)
Portugal
Tel: (351) 1-4714182
FAX: (351) 1-4715886
SELCO
En 107, N 743 Aguas Santas
4445 Ennensinde (Portugal)
Tel: (351) 2-9736957
FAX: (351) 2-9736958
Singapore
Electec PTE Ltd.
Block 50, Kallang Bahru
#04-21, Singapore 1233
Thl: (65) 294-8389
FAX: (65) 294-7623
South Mrica
Electronic Bldg. Elements
P.O. Box 912-1222
Silverton 0127
178 Erasmus St., Meyers Park
Pretoria 0184, South Africa
Tel: (27) 12803-8294
FAX: (27) 12 803 - 7680
Spain
ATD Electronica S.A
Albasanz,75
28037 Madrid, Spain
Thl: (34) 1-304-1534
FAX: (34) 1-327-2778
AID Electronica S.A
Conchita Suprevia 9
08028 Barcelona, Spain
Thl: (34) 3-4907344
FAX: (34) 3 - 4901723
SELCO
,
Clra. de La Comna, Km 18.200
28230 Las Rozas (Madrid), Spain
Tel: (34) 1-637-1333
FAX: (34) 1-637-5114
Sweden
ScandComp Sweden AB
Box 8303 Domnarvsgatan 33
16308 Spanga
Sweden
Tel: (46) 8-761-73-00
FAX: (46) 8-760-46-69
Switzerland
BasixAG.
Hardturmstrasse 181
8010 Zurich, Switzerland
Tel: (41) 1-276-11-11
FAX: (41) 1-276-14-48
Taiwan R.O.C.
Prospect Thchnology Corp.
5F, No. 348, Section 7
Cheng-Teh Rd.
Thipei, Taiwan
Tel: (886) 2-820-5353
Thlex: 14391 PROSTECH
FAX: (886) 2-820-5731
Thrkey
Inter Electronik Sanavi ve Ticaret AS.
Kadlkoy Hasircibasi Caddesi no. 55
81310 Istanbul
Turkey
Tel: (90) 216 349-94-00
Thlex: 29245 Inmd tr
FAX: (90) 216 349-94-30
United Kingdom
2001 Electronic Components Ltd.
Stevenage Business Park
Pin Green
Stevenage, Herts
SG14SUU. K.
Ambar Components Ltd.
17 Thame Park Road
Thame, Oxfordshire
England, OX9 3XD
Tel: (44) 1844-26-11-44
Telex: 837427
FAX: (44) 1844-26-17-89
Arrow Electronics (UK) Ltd.
St. Martins Business Centre
Cambridge Road
Bedford MK42 OLF, UK.
Tel: (44) 1234 270027
FAX: (44) 1234791579
Pronto Electronic System Ltd.
City Gate House
Eastern Avenue, 399-425
Gants Hill, Ilford,
Essex, U K. IG2 6LR
Tel: (44) 181-5546222
FAX: (44) 181-5183222
Spectrum
2 Grange Mews
Station Road
Launton
Bicester
Oxon, UK. OX60DX
Tel: (44) 1-869-325-174
FAX: (44) 1-869-325-175
lzrcYPRESS ====S;;;;;;3;;;;;;le;;;;;;s;;;;;;R;;;;;;e;;;;;;p;;;;;;r;;;;;;e;;;;;;S;;;;;;eD;;;;;;t;;;;;;3;;;;;;tI;;;;;;·V;;;;;;e;;;;;;S;;;;;;3;;;;;;D;;;;;;d;;;;;;D;;;;;;i;;;;;;s;;;;;;tr;;;;;;i;;;;;;h;;;;;;u;;;;;;to;;;;;;r=s
Distributors
Anthem Electronics, Inc.:
Huntsville, AL 35805
(205) 890-0302
Tempe, AZ 85281
(602) 966-6600
Chatsworth, CA 91311
(818) 775-1333
Irvine, CA 92718
(714) 768-4444
Rocklin, CA 95677
(916) 624-9744
San Jose, CA 95131
(408) 453-1200
San Diego, CA 92121
(619) 453-9005
Englewood, CO 80112
(303) 790-4500
Waterbury, CT 06705
(203) 575 -1575
Altamonte Springs, FL 32701
(407) 831-0007
Fort Lauderdale, FL 33309
(305) 484-0990
Arrow Electronics:
Alabama
Huntsville, AL 35816
(205) 837-6955
Arrow Electronics: (cont.)
Massachusetts
Wilmington, MA 01887
(617) 658-0900
Arizona
Thmpe, AZ 85282
(602) 431-0030
Michigan
Livonia, MI 48152
(313) 462-2290
California
Calabasas, CA 91302
(818) 880-9686
Minnesota
Eden Prairie, MS 55344
(612) 941-5280
Irvine, CA 92718
(714) 587-0404
San Diego, CA 92123
(619) 565-4800
San Jose, CA 95131
(408) 441-9700
San Jose, CA 95134
Canada
Mississauga, Ontario LST lMA
(416) 670-7769
Dorval, Quebec H9P 2T5
(514) 421-7411
Missouri
St. Louis, MO 63146
(314) 567-6888
New Jersey
Marlton, NJ 08053
(609) 596-8000
Pinebrook, NJ 07058
(201) 227-7880
New York
Rochester, NY 14623
(716) 427-0300
Hauppauge, NY 11788
(516) 231-1000
Duluth, GA 30136
(404) 931-3900
Neapean, Ontario K2E 7W5
(613) 226-6903
Quebec City, Quebec G2E 5RN
(418) 871-7500
North Carolina
Raleigh, NC 27604
(919) 876-3132
Schaumburg, IL 60173
(708) 884 - 0200
Burnaby, British Columbia V5A 4T8
(604) 421-2333
Ohio
Centerville, OH 45458
(513) 435-5563
Wilmington, MA 01887
(508) 657-5170
Columbia, MD 21046
(301) 995-6640
Eden Prairie, MN 55344
(612) 944-5454
Pine Brook, NJ 07058
(201) 227-7960
Commack, NY 11725
(516) 864-6600
Raleigh, NC 27604
(919) 871-6200
Beaverton, OR 97005
(503) 643-1114
Horsham, PA 19044
(215) 443-5150
Austin, TX 78728
(512) 388-0049
Richardson, TX 75081
(214) 238-7100
Salt Lake City, UT 84119
(801) 973-8555
Bothel, WA 98011
(206) 483 -1700
Colorado
Englewood, CO 80112
(303) 799-0258
Solon, OH 44139
(216) 248- 3990
Connecticut
Wallingford, CT 06492
(203) 265-7741
Oklahoma
Thlsa, OK 74146
(918) 252-7537
Florida
Deerfield Beach, FL 33441
(305) 429-8200
Oregon
Beaverton, OR 97006-7312
(503) 629-8090
Lake Mary, FL 32746
(407) 333-9300
Georgia
Deluth, GA 30071
(404) 497 -1300
Illinois
Itasca, IL 60143
(708) 250-0500
Indiana
Indianapolis, IN 46268
(317) 299-2071
Kansas
Lenexa, KS 66214
(913) 541-9542
Maryland
Columbia, MD 21046
(410) 596-7800
Gathersburg, ~.1D
(301) 596-7800
Pennsylvania
Pittsburgh, PA 15238
(412) 963-6807
Texas
Austin, TX 78758
(512) 835-4180
Carrollton, TX 75006
(214) 380-6464
Houston, TX 77099
(713) 530-4700
Washington
Bellevue, WA 98007
(206) 643-9992
Wisconsin
Brookfield, WI 53045
(414) 792-0150
= rcYPRESS ====S=a=le=s=R=e=p=r=e=s=eo=t=a=ti=v=e=s=a=o=d=D=i=s=tr=i=bu=t=o=r=s
Distributors (continued)
axis:components
Corporate Headquarters
SanDiego, CA 92121
(619) 677-7950
(800) 556-0225
Irvine, CA 92714
(714) 442-8325
Westlake Village, CA 91362
(818) 706-0166
Sunnyvale, CA 94086
(408) 522-9599
Westminster, CO 80234
(303) 469-8186
Bell Microproducts:
Irvine, CA 92718
(714) 470-2900
San Jose, CA 94131
(408) 451-9400
Altamonte Springs, FL 32714
(407) 682 - 1199
Deerfield Beach, FL 33441
(305) 429-1001
Billerica, MA 01882
(508) 667-2400
Columbia, MD 21045
(410) 720-5100
Edina, MN 55435
(612) 933-3236
Clifton, NJ 07013
(201) 777-4100
Smithtown, NY 11787
(516) 543-2000
Ambler, PA 19002
(215) 540-4148
Austin, TX 78759
(512) 258-0725
Richardson, TX 75081
(214) 783-4191
Chantilly, VA 22021
(703) 803 -1020
Redmond, WA 98052
(206) 861-7510
Marshall Industries:
Alabama
Huntsville, AL 35801
(205) 881-9235
Arizona
Phoenix, AZ 85044
(602) 496-0290
California
Marshall Industries, Corp_ Headquarters
El Monte, CA 91731-3004
(818) 307-6000
Irvine, CA 92718
(714) 458-5301
Calabasas, CA 91302
(818) 878-7000
Rancho Cordova, CA 95670
(916) 635 - 9700
San Diego, CA 92123
(619) 627-4140
Milpitas, CA 95035
(408) 942-4600
Canada
Mississauga, Ontario L4V lX5
(416) 458-8046
Pointe Claire, Quebec H9R 5P9
(514) 694-8142
Colorado
Colorado Springs, CO 80915
(719) 573-0904
Thornton, CO 80241
(303) 451-8383
Connecticut
Wallingford, CT 06492-0200
(203) 265-3822
Florida
Ft. Lauderdale, FL 33309
(305) 977 -4880
Florida (continued)
Altamonte Springs, FL 32701
(407) 767 -8585
St. Petersburg, FL 33716
(813) 573-1399
Georgia
Norcross, GA 30093
(404) 923-5750
Illinois
Schaumbrug, IL 60173
(708) 490-0155
Indiana
Carmel, IN 46032
(317) 431-6554
Kansas
Lenexa, KS 66214
(913) 492-3121
Maryland
Columbia, MD 21046
(410) 880-3030
.a;;z
~YPRESS ====S;;;;;al;;;;;e;;;;;s;;;;;R;;;;;e;;;;;p;;;;;re;;;;;S;;;;;e;;;;;D;;;;;ta;;;;;t;;;;;iv;;;;;e;;;;;S;;;;;a;;;;;D;;;;;d;;;;;D=is;;;;;tr;;;;;i;;;;;h;;;;;ut;;;;;o;;;;;r=s
Distributors
(continued)
Marshall Industries:
Semad:
Massachusetts
Wilmington, MA 01887
(508) 658-0810
Calgary
Calgary, Alberta T2E 7H7
(403) 252-5664
FAX: (800) 565-9779
Michigan
Livonia, MI 48150
(313) 525-5850
Minnesota
Plymouth, MN 55447
(612) 559-2211
Missouri
Bridgeton, MO 63044
(314) 291-4650
New Jersey
Fairfield, NJ 07006
(201) 882-0320
Mt. Laurel, NJ 08054
(609) 234-9100
New York
Endicott, NY 13760
(607) 785 - 2345
Rochester, NY 14624
(716) 235-7620
Ronkonkoma, NY 11779
(516) 737-9300
North Carolina
Raleigh, NC 27604
(919) 878-9882
Ohio
Solon, OH 44139
(216) 248-1788
Dayton, OH 45414
(513) 898-4480
Oregon
Beaverton, OR 97005
(503) 644-5050
Pennsylvania
Mt. Laurel, NJ 08054
(609) 234-9100
Texas
Austin, TX 78754
(512) 837 -1991
Richardson, TX 75081
(214) 705-0600
Houston, TX 77043
(713) 467-1666
Utah
Salt Lake City, UT 84119
(801) 973-2288
Washington
Bothell, WA 98011
(206) 486-5747
Wisconsin
Waukesha, WI 53186
(414) 797-8400
Montreal
Pointe Claire, Quebec H9R 427
(514) 694-0860
1-800-361-6558
FAX: (514) 694-0965
Ottawa
Ottawa, Ontario KlB 1A7
(613) 526-4866
FAX: (613) 523-4372
Toronto
Markham, Ontario L3R 4Z4
(905) 475-3922
FAX: (905) 475-4158
Vancouver
Burnaby, British Columbia V5G 1H1
(604) 451-3444
i -800-663-8956
FAX: (604) 451-3445
Zeus Electronics:
Yorba Linda, CA 92686
(714) 921-9000
San Jose, CA 95131
(408) 629-4789
Lake Mary, FL 32746
(407) 333-3055
Itasca, IL 60143
(708) 595 -9730
Wilmington, MA 01887
(508) 658-4776
Port Chester, NY 10573
(914) 937-7400
Carrollton, TX 75006
(214) 380-4330
'0,
Cypress Semiconductor
3901 North First Street
San Jose, CA 95134
Tel: (408) 943-2600
FAX: (408) 943-2741
FAX-Back: (800) 213-5120
Internet: http://www.cypress.com
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