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intel·

LITERATURE

For additional information on Intel products in the U.S. or Canada, call Intel's Literature Center at
(800) 548-4725 or write to:
INTEL LITERATURE SALES
P. O. Box 7641
Mt. Prospect, IL 60056-7641

To order literature outside of the U.S. and Canada contact your local sales office.
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CURRENT DATABOOKS
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the U.S. and Canada contact your local sales office.
Title
SET OF NINE DATABOOKS
(Available in U.S. and Canada)

Intel
Order Number
231003

ISBN
N/A

CONTENTS LISTED BELOW FOR INDIVIDUAL ORDERING:
EMBEDDED MICROCONTROLLERS

270646

EMBEDDED MICROPROCESSORS

272396

1-55512-248-5
1-55512-249-3

FLASH MEMORY (2 volume set)

210830
272084

1-55512-250-7

i960® PROCESSORS AND RELATED PRODUCTS
NETWORKING

297360

1-55512-256-6

OEM BOARDS, SYSTEMS AND SOFTWARE

280407

PACKAGING

240800

1-55512-253-1
1-55512-254-X

PENTIUM® AND PENTIUM PRO PROCESSORS
AND RELATED PRODUCTS

241732

1-55512-251-5

PERIPHERAL COMPONENTS

296467

1-55512-255-8

231792
210997

1-55512-257-4

COMPONENTS QUALITY/RELIABILITY
EMBEDDED APPLICATIONS (1995/96)

270648

MILITARY

210461

SYSTEMS QUALITY/RELIABILITY

231762

1-55512-252-3

ADDITIONAL LITERATURE:
(Not included in handbook set)
AUTOMOTIVE ,PRODUCTS

1-55512-258-2
1-55512-179-9

N/A
1-555.12-046-6

A complete set of this information is available on CD-ROM through Intel's Data on Demand program, order
number 240897. For information about Intel's Data on Demand ask for item number 240952.

December 1995
Order Number: 000900-001

intel·

Intel· Application Support Services

World Wide Web [URL: http://www.intel.com/J
Intel's Web site now contains technical and product information that is available 24-hours a day! Also visit Intel's
site for financials, history, current news and events, job opportunities, educational news and much, much more!

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To use FaxBack (for Intel components and systems), dial (800) 628-2283 or 916-356-3105 (U.S./Canada/APAC/Japan) or +44(0\ 1793-496646 (Europe) and follow the automated voice-prompt. Document orders will be faxed to
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Check the back of an Intel data book or request one of the following distributor listing FaxBack documents: # 4083
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Pacific Time Zone), #4209 (Europe) or #4403 (Canada) .

• Other brands and names are the property of their respective owners.

D.ecember 1995
Order Number: 000901-001

Networking
Networking Components (Ethernet * Controllers,
Ethernet Coprocessors); Telecommunication Components;
Communication/Interface Controllers

1996

I

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in
Intel's Terms and Conditions of Sale for such products.
Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer
Products may have minor variations to this specification known as errata.
*Other brands and names are the property of their respective owners.
tSince publication of documents referenced in this document, registration of the Pentium, OverDrive and
iCOMP trademarks has been issued to Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your
product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
COPYRIGHT @ INTEL CORPORATION, 1996

intel·
DATASHEET DESIGNATIONS
Intel uses various datasheet markings to designate each phase of the document as it relates to
the product. The markings appear in the lower inside corner of each datasheet page. Following are the definitions of each marking:
Datasheet Marking

Description

Product Preview

Contains information on products in the design phase of development. Do not
finalize a design with this information. Revised information will be published when
the product becomes available.

Advanced Information

Contains information on products being sampled Or in the initial production phase of
development. •

Preliminary

Contains preliminary information on new products in production.'

No Marking

Contains information on products in full production.'

, Specifications within these datasheets are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.

November 1995
Order Number: 000902·001

Local Area Network
Components
Telecommunication Products
Communication/Interface
Controllers

CONTENTS

Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

x

CHAPTER 1
Local Area Network Components
DATA SHEETS
82595TX ISA/PCMCIA High Integration Ethernet Controller ....................
82596CA High-Performance 32-Bit Local Area Network Coprocessor . . . . . . . . . . . .
82596DX and 82596SX High-Performance 32-Bit Local Area Network
Coprocessor ...........................................................
82503 Dual Serial Transceiver (DST) ........................................
82557 Fast Ethernet PCI Bus Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82595FX ISA Bus High Integration Ethernet Controller. . . . . . . . . . . . . . . . . . . . . . . ..
NETWORK READY APPLICATION NOTE
AP-368 82557 10/100 Mbps PCI LAN Controller ..... . . . . . . . . . . . . .. . . . . . . . . . ..

1-1
1-60
1-136
1-213
1-258
1-310
1-364

CHAPTER 2
Telecommunication Products
DATA SHEETS
2910A PCM Codec-microLaw 8-Bit Companded AID and 0/ A Converter. . . . . . . . .
2911 A-1 PCM Codec-A Law 8-Bit Companded AID and 0/ A Converter ..........
2912A PCM Transmit/Receive Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2913 and 2914 Combined Single-Chip PCM Codec and Filter ...................
iATC 29C48 Feature Control Combo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1
2-2
2-3
2-4
2-5

CHAPTER 3
Communication/Interface Controllers
DATA SHEETS
8251A Programmable Communication Interface .............................. .
82050 Asynchronous Communications Controller ............................ .
82510 Asynchronous Serial Controller .............................. , ....... .
8273 Programmable HDLC/SDLC Protocol Controller ......................... .
8274 Multi-Protocol Serial Controller (MPSC) ................................ .
82530/82530-6 Serial Communications Controller (SCC) ...................... .
8291A GPIB Talker/Listener ............................................... .
8292 GPIB Controller ..................................................... .
8294A Data Encryption/Decryption Unit ..................................... .

I

3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9

ix

ALPHANUMERIC INDEX

Alphanumeric Index
2910A PCM Codec-microLaw 8-Bit Companded AID and 0/ A Converter ............... .
2911 A-1 PCM Codec-A Law 8-Bit Companded A/O and 0/ A Converter ................ .
2912A PCM Transmit/Receive Filter .............................................. .
2913 and 2914 Combined Single-Chip PCM Codec and Filter ......................... .
82050 Asynchronous Communications Controller ................................... .
82503 Dual Serial Transceiver (OST) .............................................. .
82510 Asynchronous Serial Controller ............................................. .
8251 A Programmable Communication Interface .................................... .
82530/82530-6 Serial Communications Controller (SCC) ............................. .
82557 Fast Ethernet PCI Bus Controller ............................................ .
82595FX ISA Bus High Integration Ethernet Controller ............................... .
82595TX ISA/PCMCIA High Integration Ethernet Controller .......................... .
82596CA High-Performance 32-Bit Local Area Network Coprocessor .................. .
825960X and 82596SX High-Performance 32-Bit Local Area Network Coprocessor ..... .
8273 Programmable HOLC/SOLC Protocol Controller ............................... .
8274 Multi-Protocol Serial Controller (MPSC) ....................................... .
8291A GPIB Talker/Listener ..................................................... .
8292 GPIB Controller ............................................................ .
8294A Data Encryption/Decryption Unit ........................................... .
AP-368 8255710/100 Mbps PCI LAN Controller .................................... .
iATC 29C48·Feature Control Combo .............................................. .

x

2-1
2-2
2-3
2-4
3-2
1-213
3-3
3-1
3-6
1-258
1-310
1-1
1-60
1-136
3-4
3-5
3-7
3-8
3-9
1-364
2-5

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1
Local Area Network
Components

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82595TX
ISA/PCMCIA HIGH INTEGRATION
ETHERNET CONTROLLER
• Optimal Integration for Lowest Cost
Solution
- Glueless 8-Bit/16-Bit ISA/PCMCIA 2.0
Bus Interface
- Provides Fully 802.3 Compliant AUI
and TPE Serial Interface
- Local DRAM Support up to
64 Kbytes
- FLASH/EPROM Boot Support up to
1 Mbyte for Diskless Workstations
- Hardware and Software Portable
between Motherboard, Adapter, and
PCMCIA LAN Card Solution
•

High Performance Networking
Functions
- Concurrent Processing Functionality
for Enhanced Performance
-16-Bit/32-Bit 10 Accesses to Local
DRAM with Zero Added Wait-States
- Ring Buffer Structure for Continuous
Frame Reception and Transmit
Chaining
- Automatic Retransmission on
Collision
- Automatically Corrects TPE Polarity
Switching Problems

•

Low Power CHMOS IV Technology

•

Ease of Use
-Integrated Plug N' PlayTM Hardware
Functionality
- EEPROM Interface to Support
Jumperless Designs
- Software Structures Optimized to
Reduce Processing Steps
- Automatically Maps into Unused PC
10 Locations to Help Eliminate LAN
Setup Problems
- All Software Structures Contained in
One 16-Byte 10 Space
- JTAG Port for Reduced Board
Testing Times
- Automatic or Manual Switching
between TPE and AUI Ports

•

Power Management
- SL Compatible SMOUT Power Down
Input
- Software Power Down Command for
Non-SL Systems

•

144-Lead tQFP Package Provides
Smallest Available Form Factor

•

100% Backwards Hardware/Software
Compatible to 82595

TPE

AD-II

TPE Serial
Interface

A14-19

ISA/PCMCIA
Bus
Interface

00-15

Control

Link IIF

LED

CSMA/CD
Unit

Control

SMOUT

Local Memory
Interface (DMA)

~

7

AUI Serial
Interface

AUI
Link IIF

0

e

20 MHz XTAL

00-

8~ 8
'"

0

'"'---.--'
'"
Local DRAM

1/,
281630-1

Figure 1. 82595TX Block Diagram
October 1995
Order Number: 281630'()01

1-1

82595TX
ISA/PCMCIA High Integration ETHERNET Controller

CONTENTS

PAGE

1.0 INTRODUCTION ..................... 1-5
1.1 82595TX Overview ................ 1-5
1.2 Enhancements to the 82595 ....... 1-5
1,3 Compliance to Industry
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.1 Bus Interface-ISA IEEE
P996/PCMCIA 2.0 ............... 1-6
1.3.2 ETHERNETITwisted Pair
Ethernet Interface-IEEE 802.36
Specification .•................... 1-6

CONTENTS

PAGE
4.4 Local DRAM Accesses ........... 1-20
4.4.1 Writing to Local MerT:lory ..... 1-20
4.4.2 Reading from Local
Memory . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
4.5 Serial EEPROM Interface .... :' .... 1-21

4.6 Boot EPROM/FLASHlnterface ... 1-22
4.7 IA PROM Interface ............... 1-22
. 4.8 PCMCIA CIS Structures ........... 1-22
4.9 PCMCIA Decode Functions ....... 1-22.

2.0 82595TX PIN DEFINITIONS .......... 1-6

5.0 COMMAND AND STATUS
INTERFACE .......................... 1-23

2.1 ISA Bus Interface .............•.... 1-6
2.2 PCMCIA Bus Interface ............. 1-8
2.3 Local Memory Interface ............ 1-9

5.1 Command OP Code Field ......... 1-23
5.2 ABORT (Bit 5) .................... 1-23

2.4 Miscellaneous Control ............ 1-11

5.4 82595TX Status Interface .....•... 1-24

2.5 JTAG Control ..................... 1-11
2.6 Serial Interface ................... 1-12

6.0 INITIALIZATION ......... ........... 1-24

2.7 Power and Ground .... ; ........... 1-13

7.0 FRAME TRANSMISSION ........... 1-25

2.8 82595TX Pin Summary ........... 1-14

7.1 82595TX XMT Block Memory
Format ............................. 1-25
7.2 XMT Chaining .................... 1-27

3.0 82595TX INTERNAL
ARCHITECTURE OVERViEW ........ 1-15
3.1 System Interface Overview ....... 1-15
3.1.1 Concurrent ProceSSing
Functionality .................... 1-15
3.2 Local Memory Interface ........... 1-15
3.3 CSMA/CD Unit ................... 1-16

5.3 Pointer Field (Bits 6 and 7) ........ 1-23

7.3 Automatic Retransmission on
Collision ........................... 1-30
8.0 FRAME RECEPTION ................ 1-30

3.4 Serial Interface ................... 1-16

8.1 82595TX RCV Memory
Structure . . . . . . . . . . . . . . . . . .. . . . . .. .. 1-30
8.2 RCV Ring Buffer Operation ....... 1-33

4.0 ACCESSING THE 82595TX ......... 1-16

9.0 SERIAL INTERFACE ............... 1-34

4.1 82595TX Register Map ........... 1-16
4.1.1 10 Bank 0 .................... 1-17

10.0 APPLICATION NOTES ............ 1-35
10.1 Bus Interface .................... 1-35

4.1.210 Bank 1 .................... 1-18

10.2 Local Memory Interface ......... 1-35

4.1.310Bank2 ......... ; .......... 1-19

10.3 EEPROM Interface (ISA Only) ... 1-35

4.2 Writing to the 82595TX ........... 1-19

10.4 Serial Interface .................. 1-35

4.3 Reading from the 82595TX ....... 1-20

10.4.1 AUI Circuit .................. 1-35
10.4.2 TPE Circuit ................. 1-35
10.4.3 LED Circuit ................. 1-36

1-2

I

CONTENTS

PAGE

CONTENTS

PAGE

10,5 Layout Guidelines ............... 1-36

11.2 A.C. Timing Characteristics ...... 1-38

10.5.1 General .................... 1-36

11.3 A.C. Measurement Conditions ... 1-38

10.5.2 Crystal ..................... 1-36

11.4 ISA Interface Timing ............. 1-39

10.5.3 82595TX Analog Differential
Signals ......................... 1-36

11.5 PCMCIA Interface Timing ........ 1-44

10.5.4 Decoupling
Considerations .................. 1-36

11.6 Local Memory Timings ........... 1-47
11.6.1 DRAM Timings ............. 1-47
11.6.2 FLASH/EPROM Timings ... 1-49

11.0 ELECTRICAL SPECIFICATIONS
AND TIMINGS ........................ 1-37
11.1 Absolute Maximum Ratings ...... 1-37
11.1.1 Package Thermal
Specifications ................... 1-38

11.6.3 IA PROM Timings .......... 1-51
11.7lnterruptTiming .................. 1-52
11.8 RESET and SMOUT Timing ..... 1-52
11.9 JTAG Timing .................... 1-53
11.10 Serial Timings .................. 1-54

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~L....,..J:=fJ:8!l!t!::.~En~obi!:I'Jt>.)
290218-1

Figure 1. 82596CA Block Diagram

1-60

October 1995
Order Number: 290218-006

intel®

82596CA

82596CA High-Performance 32-Bit
Local Area Network Coprocessor
CONTENTS

PAGE

CONTENTS

PAGE

INTRODUCTION ........................ 1-62

SYSTEM CONTROL BLOCK (SCB) ..... 1-86

PIN DESCRiPTIONS .................... 1-66

SCB OFFSET ADDRESSES ............. 1-89
CBlOffset(Address) .................... 1-89

82596 AND HOST CPU
INTERACTION ....................... 1-70

RFA Offset (Address) ................... 1-89

82596 BUS INTERFACE ................ 1-70

SCB STATISTICAL COUNTERS ........ 1-90

82596 MEMORY ADDRESSING ........ 1-70

Statistical Counter Operation ............ 1-90

82596 SYSTEM MEMORY
STRUCTURE ......................... 1-72

ACTION COMMANDS AND
OPERATING MODES ................. 1-91
NOP ....................... ,.......... ,. .. 1-92

TRANSMIT AND RECEIVE MEMORY
STRUCTURES ........................ 1-73
TRANSMITTING FRAMES .............. 1-76
RECEIVING FRAMES ................... 1-77
82596 NETWORK MANAGEMENT AND
DIAGNOSTICS ....................... 1-77
NETWORK PLANNING AND
MAINTENANCE ...................... 1-79
STATION DIAGNOSTICS AND SELFTEST ..............' ................... 1-80

Individual Address Setup ......... ~ ...... 1-92
Configure ............................... 1-93
Multicast-Setup ......................... 1~99
Transmit ....... ; ....................... 1-100
Jamming Rules ......................... 1-102
TDR .................... .' .............. 1-103
Dump .... : ............................. 1-105
Diagnose .............................. 1-108
RECEIVE FRAME DESCRIPTOR ...... 1-109

82586 SOFTWARE COMPATIBILITY ... 1-80

Simplified Memory Structure ............ 1-109
Flexible Memory Structure ... , .......... 1-110

INITIALIZING THE 82596 ............... 1-80 '

Receive Buffer Descriptor (RBD) ; ...... 1-111

SYSTEM CONFIGURATION POINTER
(SCP) ................................. 1-80
Writing the Sysbus ...................... 1-81
INTERMEDIATE SYSTEM
CONFIGURATION POINTER
(ISCP) ................................ 1-82
INITIALIZATION PROCESS ............ 1-82
CONTROLLING THE 82596CA ......... 1-83
82596 CPU ACCESS INTERFACE
(PORT) ............................... 1-83
MEMORY ADDRESSING FORMATS .... 1-83
, LITTLE ENDIAN AND BIG ENDIAN
BYTE ORDERING .................... 1-84

PGA PACKAGE THERMAL
SPECIFICATIONS ........ , .......... 1-116
ELECTRICAL AND TIMING
CHARACTERISTICS . ............... 1-116
Absolute Maximum Ratings .. , ..........
DC Characteristics .....................
AC Characteristics ....... .'.............
82596CA C-Step Input/Output System
Timings ..............................
Transmit/Receive Clock Parameters ...

1-116
1-116
1-117
1-117
1-122

82596CA BUS Operation ............... 1-125
System Interface AC Timing
Characteristics ....................... 1-126
Input Waveforms ....................... 1-127
Serial AC Timing Characteristics ........ 1-129

COMMAND UNIT (CU) .................. 1-85

OUTLINE DIAGRAMS ................. 1-131

RECEIVE UNIT (RU) .................... 1-85

REVISION HiSTORy .................. 1-135

I

1-61

82596CA

INTRODUCTION
The 82596CA is an intelligent, high-performance
32-bit Local Area Network coprocessor. The
82596CA implements the CSMAlCD access method
and can be configured to support all existing IEEE
802.3 standards-TYPEs 10BASE-T, 10BASE5,
10BASE2, 1BASE5, and 10BROAD36. It can also be
used to implement the proposed standard· TYPE
10BASE-F. The 82596CA performs high-level commands, command chaining, and interprocessor communications via shared memory, thus relieving the
host CPU of many tasks associated with network
control. All time-critical functions are performed independently of the CPU, this increases network performance and efficiency. The 82596CA bus interface
is optimized for Intel's i486™SX, i486™DX,
i487™SX, 80960CA, and 80960KB processors.
The 82596CA implements all IEEE 802.3 Medium
Access Control and channel interface functions,
these include framing, preamble generation and
stripping, source address generation, destination address checking, short-frame detection, and automatic length-field handling. Data rates up to 20 Mb/s are
supported.
The 82596CA provides a powerful host system inter~
face. It manages memory structures automatically,
with command chaining and bidirectional data chaining. An on-chip DMA controller manages four channels, this allows autonomous transfer of data blocks
(buffers and frames)· and relieves the CPU of byte
transfer overhead. Buffers containing errored or collided frames can be automatically recovered without
CPU intervention. The 82596CA provides an upgrade path for existing 82586 software drivers by
providing an 82586-software-compatible mode that
supports the current 82586 memory structure. The
82586CA also has a Flexible memory structure and
a Simplified memory structure. The 82596CA can
address up to 4 gigabytes of memory. The 82596CA
supports Little Endian and Big Endian byte ordering.
The 82596CA bus interface can achieve a burst
transfer rate of 106 MB/s at 33 MHz. The bus interface employs bus throttle timers to regulate
82596CA bus use. Two large, independent FIFOs.128 bytes for Receive and 64 bytes for Transmittolerate long bus latencies and provide programmable thresholds that allow the user to optimize bus
overhead for any worst-case bus latency. The highperformance bus is capable of back-to-back transmission and reception during the IEEE 802.3 9.6-,...s
Interframe Spacing (IFS) period.
The 82596CA provides a wide range of diagnostics
and network management functions, these include
internal and external loopback, exception condition

1-62

tallies, channel activity indicators, optional capture
of all frames regardless of destination address
(promiscuous mode), optional capture of errored or
collided frames, and time domain reflectometry for
locating fault points on the network cable. The statistical counters, in 32-bit segmented and linear
modes, are 32-bits each and include CRC errors,
alignment errors, overrun errors, resource errors,
short frames, and received collisions. The 82596CA
also features a monitor mode for network analysis.
In this mode the 82596CA can capture status bytes,
and update statistical counters, of frames monitored
on the link without transferring the contents of the
frames to memory. This can be done concurrently
while transmitting and receiving frames destined for
that station.
.
The 82596CA can be used in both baseband and
broadband networks. It can be configured for maximum network efficiency (minimum contention overhead) with networks of any length. Its highly flexible
CSMAlCD unit supports address field lengths of
zero through six bytes .for IEEE 802.3/Ethernet
frame delimitation. It also supports 16- or 32-bit cyclic redundancy checks. The CRC. can be transferred directly to memory for receive operations, or
dynamically inserted for transmit operations. The
CSMAlCD unit can also be configured for full duplex
operation for high throughput in pOint-to-point connections.
The 82596 C-step incorporates several new features
not found in previous steppings. The following is a
summary of the 82596 C-step's new features.
• The 82596 C-step fixes Errata found in the A 1
and B steppings.
• The 82596 C-step has improved AC timings over
both the A and B step pings.
.
• the 82596 C-step has a New Enhanced Big Endian Mode where in Linear Addressing Mode, true
32-bit Big Endian functionality is achieved. New
Enhanced Big Endian Mode is enabled by setting
bit 7 of the SYSBUS byte. This mode is software
compatible with the big end ian mode of the
B-step with one exception-no 32-bit addresses
need to be swapped by software in the C-step.ln
this new mode, the 82596 C-step treats 32-bit address pointers as true 32-bit entities and the SCB
absolute address and statistical counters are still
treated as two ·16-bit big endian entities. Not setting this mode will configure the 82596 C-step to
be 100% compatible to the A1-step big endian
mode.
• The 82596 C-step is hardware and software compatible to both the A 1 and B steppings allowing
for easy "drop-in" to current designs~ Pinout and
control structures remain unchanged ..

I

82596CA

The 82596CA is fabricated with Intel's reliable, 5-V, CHMOS IV (process 648.8) technology. It is available in a
132-pin PQFP or PGA package.

82596CA

(Top View)

290218-2

Figure 2. 82596CA PQFP Pin Configuration

I

1-63

82596CA

A
01

02

1'0

o

o

o

015

013

06

05

0
018

03

0
020

04

0
022

05

0
026

06

0
Vss

07

08

09

10

11

12

13

14

G

o o
o o
o o
o o
o o

o

o

o

Vss

04

o

o

o

o

o

o

o

Vss '

Vss

DP2

BRDY

8516

PCHK

09

o
o

08

o
o

o

012

o

o

o
o

016

014

011

010

o

o

o

o

o

07

03

01

ClK

OP3

OP 1

READY

021

017

02..

019

iDs'

o

Vee

023

HLOA

02

o

o

o

o

o

o

00

Vee

OPO

PORT

ii'CA'ST

HOLD

o

LoCK

METAL LID

o

(82596CA Pin View)

o

INTliNT

o

wIR

o

06

Vss

0
025

BEO

Vee

o

o

o
028

04

o

0

o

o
BREa

BOfF

Yee

027

03

CA

os

0
0

02

o

o
AHOLD

Vss

Vss

o

01

iEf

000

07

Vss

o

08

Vss

0

o

o

o

o

o

029

031

030

A3

A2

BE3

0

o

o

10

11

TxD

RxC

o
o
ers

o

0

o
o

0

0

'["ji"jj(

RxO

0

TxC

o

o

o

A8

A6

A5

o

0

0

0

0

0

0

0

0

0

A30

A28

A25

A23

A21

A18

A16

A12

Al0

A9

o

12

13

A7

0

0

0

0

0

0

0

0

000

0

o

o

COT

RESET

Vee

A29

Vee

A26

Vee

Vee

Vee

AU

A13

All

;.19

Vee

09

0

o

o

o

o

o

o

o

o

o

o

o

o

o

CRS

lE!BE

A3;

A27

Vss

A24

Vss

Vss

Vss

A22

Vss

A20

A17

A15

A

290218-3

Figure 3. 82596CA PGA Pinout

1-64

I

82596CA

82596CA PGA Cross Reference by Pin Name
Address

Data

Control

Serial
Interface

Vee

Vss

Signal

Pin No.

Signal

Pin No.

Signal

Pin No.

Signal

Pin No.

Pin No.

Pin No.

A2
A3

N9
M9
M10
P11
N11
P12
M11
N12
M12
P13
L12
N13
M13
P14
K12
N14
J12
K13
M14
H12
K14
G12
F14
F12
F13
014
E12
013
012
C14

00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
02B
029
030
031

J2
H3
G2
G3
G1
01
C1
F3
02
C2
E3
03
B2
B1
C3
A1
B3
C4
A2
C5
A3
B4

AOS
AHOLO
BEO
BE1
BE2
BE3
BLAST
BOFF
BROY
BREQ
BS16
CA
CLK
OPO
OP1
OP2
OP3
HLOA
HOLD
INT/INT
LE/BE
LOCK
PCHK
PORT
REAOY
RESET

M5
N5
M7
P5
M8
P9
N2
N6
M1
P4
N1
P3
J3
L2
L3
L1
K3
M6
P2
N3
B14
M4
P1
M2
M3
B13
N4

COT
CRS
CTS
LPBK
RTS
RxC
RxO
TxC
TxO

A13
A14
C11
A12
C10
B11
B12
C12
A11

B6
B7
B10
C13
E2
E13
F2
G13
H2
H13
J13
K2
L13
N7
N8
N10

A6
A7
A8
A10
E1
E14
F1
G14
H1
H14
J1
J14
K1
L14
P6
P7
PB
P10

A4

A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A1B
A19
A20
A21
A22
A23
A24
A25
A26
A27
A2B
A29
A30
A31

I

A4

C6
B5
C7
A5
BB
CB
A9
C9
B9

wlF5.

1-65

82596CA

PIN DESCRIPTIONS
Symbol
elK

00-031

PQFP
Pin No.

Type

9

I

14-53

I/O

Name and Function
CLOCK. The system clock input provides the fundamental timing for
the 82596. It is a 1X ClK input used to generate the 82596 clock and
requires TTL levels. All external timing parameters are specified in
reference to the rising edge of ClK.
DATA BUS. The 32 Data Bus lines are bidirectional, tri-state lines that
provide the general purpose data path between the 82596 and
memory. With the 82596 the bus can be either 16 or 32 bits wide; this
is determined by the BS16 signal. The 82596 always drives all 32 data
lines during Write operations, even with a 16-bit bus. 031- DO are
floated after a Reset or when the bus is not acquired.
These lines are inputs during a CPU Port access; in this mode the CPU
writes the next address to the 82596 through the data lines. During
PORT commands (Relocatable SCP, Self-Test, Reset and Dump) the
address must be aligned to a 16-byte boundary. This frees the 03-00
lines so they can be used to distinguish the commands. The following
is a summary of the decoding data.
DO

01

02

03

031-04

Function

0
0
1
1

0
1
0
1

0
0
0
0

0
0
0
0

0000
AOOR
AOOR
AOOR

Reset
Relocatable SCP
Self-Test
Oump Command

DPO-OP3

4-7

1/0

DATA PARITY. These are tri-stated data parity pins. There is one
parity line for each byte of the data bus. The 82596 drives them with
even-parity information during write operations having the same timing
as data writes. Likewise, even-parity information, with the same timing
as read information, must be driven back to the 82596 over these pins
to ensure that the correct parity check status is indicated by the
82596.

PCHK

127

0

PARITY CHECK. This pin is driven high one clock after ROY to inform
Read operations of the parity status of data sampled at the end of the
previous clock cycle. When driven low it indicates that incorrect parity
data has been sampled. It only checks the parity status of enabled
bytes, which are indicated by the Byte Enable and Bus Size signals.
PCHK is only valid for one clock time after data read is returned to the
82596; i.e., it is inactive (high) at all other times.

A31-A2

70-108

0

ADDRESS LINES. These 30 tri-stated Address lines output the
address bits required for memory operation. These lines are floated
after a Reset or when the bus is not acquired.

BE3-BEO

109-114

0

BYTE ENABLE. These tri-stated signals are used to indicate which
bytes are involved with the current memory access. The number of
Byte Enable signals asserted indicates the physical size of the data
being transferred (1, 2, 3, or 4 bytes).
• BEO indicates 07-00
• BE1 indicates 015-08
• BE2 indicates 023-016
• BE3 indicates 031-024
These lines are floated after a Reset or when the bus is not acquired.

120

0

WRITE/READ. This dual function pin is used to distinguish Write and
Read cycles. This line is floated after a Reset or when the bus is not
acquired.

WIR

1-66

I

intel®

82596CA

PIN DESCRIPTIONS (Continued)
PQFP
Pin No.

Type

Name and Function

ADS

124

0

ADDRESS STATUS. The 82596 uses this tri·state pin to indicate to
indicate..!hat a valid bus cycle has begun and that A31-A2, BE3-BEO,
and W/R are being driven. It is asserted during t1 bus states. This line
is floated after a Reset or when the bus is not acquired.

RDY

130

I

READY. Active low. This signal is the acknowledgment from
addressed memory that the transfer cycle can be completed. When
high, it causes wait states to be inserted. It is ignored at the end of the
first clock of the bus cycle's data cycle. This active·low signal does not
have an internal pull-up resistor. This signal must meet the setup and
hold times to operate correctly.

BRDY

2

I

BURST READY. Active low. Burst Ready, like RDY, indicates that the
.external system has presented valid data on the data pins in response
to a Read, or that the external system has accepted the 82596 data in
response to a Write request. Also, like RDY, this signal is ignored at
the end of the first clock in a bus cycle. If the 82596 can still receive
data from the previous cycle, ADS will not be asserted in the next
clock cycle; however, Address and Byte Enable will change to reflect
the next data item expected by the 82596. BRDY will be sampled
during each succeeding clock and if active, the data on the pins will be
strobed to the 82596 or to external memory (read/write). BRDY
operates exactly like READY during the last data cycle of a burst
sequence and during nonburstable cycles.

BLAST

128

0

BURST LAST. A signal (active low) on this tri-state pin indicates that
the burst cycle is finished and when BRDY is next returned it will be
treated as a normal ready; i.e., another set of addresses will be driven
with ADS or the bus will go idle. BLAST is not asserted if the bus is not
acquired.

AHOLD

117

I

ADDRESS HOLD. This hold signal is active.high, it allows another bus
master to access the 82596 address bus. In a system where an 82596
and an i486 processor share the local bus, AHOLD allows the cache
controller to make a cache invalidation cycle while the 82596 holds the
address lines. In response to a signal on this pin, the 82596
immediately (i.e. during the next clock) stops driving the entire address
bus (A31-A2); the rest of the bus can remain active. For example,
data can be returned for a previously specified bus cycle during
Address Hold. The 82596 will not begin another bus cycle while
AHOLD is active.

BOFF

116

I

BACKOFF. This signal is active low, it informs the 82596 that another
bus master requires access to the bus before the 82596 buS cycle
completes. The 82596 immediately (i.e. during the next clock) floats its
bus. Any data returned to the 82596 while BOFF is asserted is ignored.
BOFF has higher priority than RDY or BRDY; if two such signals are
returned in the same clock period, BOFF is given preference. The
82596 remains in Hold until BOFF goes high, then the 82596 resumes
its bus cycle by driving out the address and status, and asserting ADS.

LOCK

126

0

LOCK. This tri-state pin is used to distinguish locked and unlocked bus
cycles. LOCK generates a semaphore handshake to the CPU. LOCK
can be active for several memory cycles, it goes active during the first
locked memory cycle (t1) and goes inactive at the last locked cycle
(t2). This line is floated after a Reset or when the bus is not acquired.
LOCK can be disabled via the sysbus byte in software.

Symbol

I

1-67

82596CA

PIN DESCRIPTIONS (Continued)
PQFP
Pin No.

Type

B816

129

I

BUS SIZE. This signal allows the 82596CA to work with either 16- or
32-bit bytes. Inserting B816 low causes the 82596 to perform two 16bit memory accesses when transferring 32-bit data. In little endian
mode the D15-DO lines are driven when B816 is inserted, in Big
Endian mode the D31-D16 lines are driven.

HOLD

123

0

HOLD. The HOLD signal is active high, the 82596 uses it to request
local bus mastership. In normal operation HOLD goes inactive before
HLDA. The 82596 can be forced off the bus by deasserting HLDA or if
the bus throttle timers expire.

HLDA

118

I

HOLD ACKNOWLEDGE. The HLDA signal is active high, it indicates
that bus mastership has been given to the 82596. HLDA is internally
synchronized; after HOLD is detected low, the CPU drives HLDA low.
NOTE:
Do not connect HLDA to Vcc-it will cause a deadlock. A user wanting
to give the 82596 permanent access to the bus should connect HLDA
to HOLD. If HLDA goes inactive before HOLD, the 82596 will release
the bus (by deasserting HOLD) within a maximum of within a specified
number of bus cycles as specified in the 82596 User's Manual.

BREQ

115

I

BUS REQUEST. This signal, when configured to an externally
activated mode, is used to trigger the bus throttle timers.

PORT

3

I

PORT. When this signal is received,the 82596 latches the data on the
data bus into an internal 32-bit register. When the CPU is asserting this
signal it can write into the 82596 (via the data bus). This pin must be
activated twice during all CPU Port access commands.

RE8ET

69

I

RESET. This active high, internally synchronized signal causes the
82596 to terminate current activity. The signal must be high for at least
five system clock cycles. After five system clock cycles and four TxC
clock cycles the 82596 will execute a Reset when it receives a high
RE8ET signal. When RE8ET returns to low the 82596 waits for the
first CA signal and then begins the initialization sequence.

LE/BE

65

I

LITTLE EN DIAN/BIG ENDIAN. This dual-function pin is used to
select byte ordering. When LE/BE is high, little endian byte ordering is
used; when low, big end ian byte ordering is used for data in frames
(bytes) and for control (8CB, RFD, CBL, etc).

CA

119

I

CHANNEL ATTENTION. The CPU uses this pin to force the 82596 to
begin executing memory resident Command blocks. The CA signal is
internally synchronized. The signal must be high for at least one
system clock. It is latched internally on the high to low edge and then
detected by the 82596.
The first CA after a Reset forces the 82596 into the initialization
sequence beginning at location 00FFFFF6h or an 8CP address written
to the 82596 using CPU Port access. All subsequent CA signals cause
the 82596 to begin executing new command sequences from the 8CB.

Symbol

INT/INT

1-68

125

0

Name and Function

,

,INTERRUPT. A high signal on this pin notifies the CPU that the 82596
is requesting an interrupt. This signal is an edge triggered interrupt
signal, and can be configured to be active high or low.

I

82596CA

PIN DESCRIPTIONS (Continued)

I

Symbol

PQFP
Pin No.

Vee

17 Pins

POWER. +5 V ±10%.
GROUND.OV.

Type

Name and Function

Vss

17 Pins

TxO

54

0

TRANSMIT DATA. This pin transmits data to the serial link. It is high
when not transmitting.

TxC

64

I

TRANSMIT CLOCK. This signal provides the fundamental timing for
the serial subsystem. The clock is also used to transmit data
synchronously on the TxO pin. For NRZ encoding, data is transferred
to the TxO pin on the high to low clock transition. For Manchester
encoding, the transmitted bit center is aligned with the low to high
transition. Transmit clock must always be running for proper device
operation.

LPBK

58

0

LOOPBACK. This TIL-level control signal enables the loopback
mode. In this mode serial data on the TxO input is routed through the
82C501 internal circuits and back to the RxO output without driving the
transceiver cable. To enable this signal, both internal and external
loopback need to be set with the Configure command.

RxO

60

I

RECEIVE DATA. This pin receives NRZ serial data only. It must be
high when not receiving.

RxC

59

I

RECEIVE CLOCK. This signal provides timing information to the
internal shifting logic. For NRZ data the state of the RxO pin is
sampled on the high to low transition of the clock.

RTS

57

0

CTS

62

I

CLEAR TO SEND. An active-low signal that enables the 82596 to
send data. It is normally used as an interface handshake to RTS.
Asserting CTS high stops transmission. CTS is internally synchronized.
If CTS goes inactive, meeting the setup time to the TxC negative edge,
the transmission will stop and RTS will go inactive within, at most, two
TxC cycles.

CRS

63

I

CARRIER SENSE. This signal is active low, it is used to notify the
82596 that traffic is on the serial link. It is only used if the 82596 is
configured for external Carrier Sense. In this configuration external
circuitry is required for detecting traffic on the serial link. CRS is
internally synchronized. To be accepted, the signal must remain active
for at least two serial clock cycles (for CRSF = 0).

COT

61

I

COLLISION DETECT. This active-low signal informs the 82596 that a
collision has occurred. It is only used if the 82596 is configured for
external Collision Detect. External circuitry is required for collision
detection. COT is internally synchronized. To be accepted, the signal
must remain active for at least two serial clock cycles (for COTF = 0).

REQUEST TO SEND. When this signal is low the 82596 informs the
external interface that it has data to transmit. It is forced high after a
Reset or when transmission is stopped.

1-69

82596CA

82596 AND HOST CPU INTERACTION

82596 BUS INTERFACE

The 82596CA and the host CPU communicate
through shared memory. Because of its on-chip
DMA capability, the 82596 can make data block
transfers (buffers and frames) independently of the
CPU; this greatly reduces the CPU byte transfer
overhead.

The 82596CA has bus interface timings and pin definitions that are compatible with Intel's 32-bit
i486™SX and i486™DX microprocessors. This
eliminates the need for additional bus interface logic.
Operating at 33 MHz,. the 82596's bus bandwidth
can. be as high as 106 MB/s. Since Ethernet only
requires 1.25 MB/s, this leaves a considerable
amount of bandwidth for the CPU. The 82596 also
has a bus throttle to regulate its use of the bus. Two
timers can be programmed through the SCB: one
controls the maximum time the 82596 can remain on
the bus, the other controls the time the 82596 must
stay off the bus (see Figure 5). The bus throttle can
be programmed to trigger internally with HLDA or
externally with BREQ. These timers can restrict the
82596 HOLD activation time and improve bus utilization.

The 82596 is a multitasking aaprocessor that comprises two independent logical units-the Command
Unit (CU) and the Receive Unit (RU). The CU executes commands from shared memory. The RU handles all activities related to frame reception. The independence of the CU and RU enables the 82596 to
engage in both activities simultaneously-the. CU
can fetch and execute commands from memory
while the RU is storing received frames in memory.
The CPU is only involved with this process after the
CU has executed a sequence of commands or the
RU has finished storiog a sequence of frames.
The CPU and the 82596 use the hardware signals
Interrupt (INT) and Channel Attention (CA) to initiate
communication with the System Control Block
(SCB), see Figure 4. The 82596 uses INT to alert the
CPU of a change in the contents of the SCB, the
CPU uses CA to alert the 82596.
The 82596 has a CPU Port Access state that allows
the CPU to execute certain functions without accessing memory. The 82596 PORT pinand data bus
pins are used to enable this feature. The CPU can
directly activate four operations when the 82596 is in
this state.
• Write an alternative System Configuration Pointer
(SCP). This can be used when the 82596 cannot
use the default SCP address spate.
• Write a different Dump Command Pointer and execute Dump. This can be used for troubleshooting No Response problems.
• The CPU can reset the 82596 via software without disturbing the rest of the system.

82596 MEMORY ADDRESSING
The 82596 has a 32-bit memory address range,
which allows addressing up to four gigabytes of
memory. The 82596 has three memory addressing
mOdes (see Table 1).
• 82586 Mode. The 82596 has a 24-bit memory
address range. The System Control Block, Command List, Receive Descriptor List, and Buffer
Descriptors must reside in one 64-KB memory'
segment. Transmit and Receive buffers can reside in a 24-bit address space.
• 32-8it Segmented Mode. The 82596 has a 32bit memory address range. The System Control
Block, Command List, Receive Descriptor List,
and Buffer Descriptors must reside in one 64-KB
memory segment. Transmit and Receive buffers
can reside in a 32-bit address space.
• Linear Mode. The 82596 has a 32-bit memory
address range. Any memory structure can reside
anywhere within the 32-bit memory address
range.

• A self-test can be used for board testing; the
82596 will execute a self-test and write the results to memory.

1-70

I

82596CA

I

CHANNEL ATTENTION

CPU

'"

.1

CAl

182596

INTERRUPT

INT

..

~

;:..

SHARED MEMORY
INITIALIZATION
ROOT

-~
SYSTEM CONTROL
BLOCK (SCB).
"MAILBOX"

"-

v

A
'I

J.

J.

RECEIVE
FRAME
AREA

COMMAND
LIST

290216-4

Figure 4. 82596 and Host CPU Intervention

82596 Bus Use
without Bus
Throttle Timers

I

r-

82596 Bus Use
with Bus Throttle

I

I

·1

t1

T-ON

IT-OFF

['T-ONl

Timers

tl =t2+t3

290216-5

. Figure 5. Bus Throttle Timers
Table 1.82596 Memory Addressing Formats
Operation Mode
Pointer or Offset

I

82586

ISCP Address

24-Bit Linear

SCBAddress

Base (24)

Command Block Pointers

Base (24)

Rx Frame Descriptors

Base (24)

Tx Frame Descriptors

Base (24)

Rx Buffer Descriptors

'Base (24)

+ Offset (16)
+ Offset (16)
+ Offset(16)
+ Offset (16)
+ Offset (16)
+ Offset (16)

32-Bit
Segmented
32-Bit Linear
Base (32)
Base (32)
Base (32)
Base (32)
Base (32)

+ Offset (16)
+ Offset (16)
+ Offset (16)
+ Offset (16)
+ Offset (16)
+ Offset (16)

Linear
32-Bit Linear
32-Bit Linear
32-Bit Linear
32-Bit Linear
32-Bit Linear
32-Bit Linear

Tx Buffer Descriptors

Base (24)

Rx Buffers

24-Bit Linear

32-Bit Linear

32-Bit Linear

Tx Buffers

24-Bit Linear

32-Bit Linear

32-Bit Linear

Base (32)

32-Bit Linear

1-71

82596CA

INITIALIZATION ROOT

COMMAND LIST (CL)

CO~~~NNT~~JST ~---i-..I
RECEIVE FRAME
POINTER

L-_ _ _.J(N)

STATISTICS
TRANSMIT
BUFFER
DESCRIPTOR
(TBD)

I

BUS
THROTTLE

I

.. _-------_.
I
I

T
RECEIVE FRAME AREA (RFA)

----------------------------.----------'------.
'--_ _....... (N)

(1)

RECEIVE
BUFFER
DESCRIPTOR
(RBD)

EL= 1
RECEIVE
BUFFER
DESCRIPTOR
(RBD)

' - - _ , -....... (N)

TL--_---IT TL..-_---1T T

T
290218-6

Figure 6. 82596 Shared Memory Structure

82596 SYSTEM MEMORY STRUCTURE
The Shared Memory structure consists of four parts:
the Initialization Root, the System Control Block, the
Command List, and the Receive Frame Area (see
Figure 6).
The Initialization Root is in an established location
known to the host CPU and the 82596 (OOFFFFF6h).
However, the CPU can establish the Initialization
Root in another location by using the CPU Port access. This root is accessed during initialization, and
points to the System Control Block.

1-72

The System Control Block serves as a bidirectional
mail drop for the host CPU and the 82596 CU and
RU. It is the central point through which the CPU and
the 82596 exchange control and status information.
The SCB has two areas. The first contains instructions from the CPU to the 82596. These include:
control of the CU and RU(Start, Abort, Suspend,
and Resume), a pointer to the list of CU commands,
a pointer to the Receive Frame Area, a set of Interrupt Acknowledge bits, and the T-ON and T-OFF
timers for the bus throttle. The second area contains
status information the 82596 is sending to the CPU.
Such as, the CU and RU states (Idle, Active

I

82596CA

Ready, Suspended, No Receive Resources, etc.), interrupt bits (Command Completed, Frame Received,
CU Not Ready, and RU Not Ready), and statistical
counters.
The Command List functions as a program for the
CU; individual commands are placed in memory
units called Command Blocks (CBs). These CBs
contain the parameters and status of specific highlevel commands called Action Commands; e.g.,
Transmit or Configure.
Transmit causes the 82596 to transmit a frame. The
Transmit CB contains the destination address, the
length field, and a pointer to a list of linked buffers
holding the frame that is to be constructed from several buffers scattered throughout memory. The
Command Unit operates without CPU intervention;
the DMA for each buffer, and the prefetching of references to new buffers, is performed in parallel. The
CPU is notified only after a transmission is complete.
The Receive Frame Area is a list of Free Frame Descriptors (descriptors not yet used) and a list of userprepared buffers. Frames arrive at the 82596 unsolicited; the 82596 must always be ready to receive
and store them in the Free Frame Area. The Receive Unit fills the buffers when it receives frames,
and reformats the Free Buffer List into receivedframe structures. The frame structure is, for all practical purposes, identical to the format of the frame to
be transmitted. The first Frame descriptor is referenced by the SCB. Unless the 82596 is configured
to Save Bad Frames, the frame descriptor, and the
associated buffer descriptor, which is wasted when
a bad frame is received, are automatically reclaimed
and returned to the Free Buffer List.
Receive buffer chaining (storing incoming frames in
a linked buffer list) significantly improves memory
utilization. Without buffer chaining, the user must allocate consecutive blocks of memory, each capable
of containing a maximum frame (for Ethernet, 1518
bytes). Since an average frame is about 200 bytes,
this is very inefficient. With buffer chaining, the user
can allocate small buffers and the 82596 will only
use those that are needed.
Figure 7 A-D illustrates how the 82596 uses the
Receive Frame Area. Figure 7A shows an unused
Receive Frame Area composed of Free Frame Descriptors and Free Receive Buffers prepared by the
user. The SCB points to the first Frame Descriptor of
the Frame Descriptor List. Figure 7B shows the
same Receive Frame Area after receiving one
frame. This first frame occupies two Receive Buffers
and one Frame Descriptor-a valid received frame
will only occupy one Frame Descriptor. After receiv-

I

ing this frame the 82596 sets the next Free Frame
Descriptor RBD pointer to the next Free RBD. Figure
7C shows the RFA after receiving a second frame.
In this example the second frame occupies only one
Receive Buffer and one RFD. The 82596 again sets
the RBD pointer. This process is repeated again in
Figure 70, showing the reception of another frame
using one Receive Buffer; in this example there is an
extra Frame Descriptor.

TRANSMIT AND RECEIVE MEMORY
STRUCTURES
There are three memory structures for reception and
transmission. The 82586 memory structure, the
Flexible memory structure, and the Simplified memory structure. The 82586 mode is selected by configuring the 82596 during initialization. In this mode all
the 82596 memory structures are compatible with
the 82586 memory structures.
When the 82596 is not configured to the 82586
mode, the other two memory structures, Simplified
and Flexible, are available for transmitting and receiving. These structures are selected by setting the
S/F bit in the Transmit Command and/or the Receive Frame Descriptor (see Figures 29, 30, 41, and
42). It is recommended that any linked list of buffers
be relegated to a single type-either simplified or
flexible. The Simplified memory structure offers a
simple structure for ease of programming (see Figure 8). All information about a frame is contained in
one structure; for example, during reception the RFD
and data field are contained in one structure.
The Flexible memory structure (see Figure 9) has a
control field that allows the programmer to specify
the amount of receive data the RFD will contain for
receive operations and the amount of transmit data
the Transmit Command Block will contain for transmit operations. For example, when the control field
in the RFD is set to 20 bytes during a reception, the
first 20 bytes of the data field are stored in the RFD
(6 bytes of destination address, 6 bytes of source
address, 2 bytes of length field, and 6 bytes of data)
and the remainder of the data field is stored in the
Receive Data Buffers. This is useful for capturing
frame headers when header information is contained in the data field. The header information can
then be automatically stored in the RFD partitioned
from the Receive Data. Buffer.
The control field can also be used for the Transmit
Command when the Flexible memory structure is
used. The quantity of data field bytes to be transmitted from the Transmit Command Block is specified
by the variable control field.

1-73

82596CA

}

"'..,
..,
...

00)
0)

In

I

OJ'"
reO)
_ ..... 0
~ ~~.

290218-7

Figure 7. Frame Reception in the RFA

1-74

I

82596CA

SCB
STATUS

TO COMMAND LIST

14

I

FD
POINTER

F01
STATUS

-

STATUS

I

I
I
I

BUS
THROTTLE

F03

FD2

STATISTICS
I
I
I

•

RECEIVE FRAME AREA

.------_.
VARIABLE
DATA
FIELD

Y

F04

-r

- J:

STATUS

STATUS

EMPTY

EMPTY

EMPTY

RECEIVE
FRAME
DESCRIPTORS

:+--

RECEIVE FRAME LIST ---I~":"'4--------- FREE FRAME LIST ----------I~..,

290218-8

Figure 8. Simplified Memory Structure
se9

TO COMMAND LIST

STATUS

ra1

FD2

.~ STATUS

FO
POINTER

BUS
THROTTLE

. .-

t
:

_ _ _ _ _ _ _ 01

U-

F04

STATUS...-I-r

CONTROL
FIELD

VARIABLE

RECEIVE
FRAME
DESCRIPTORS

FD3

11-+-I.~~S~TA~T~US=l_lJ S1ATUS....

t=~...-:t-_-~

STATISTICS

I
:•

,.

•••- - - - - - - - - - - - - RECEIVE FRAME AREA

EMPTY

EMPTY

EMPTY

OATA
FIELD

R90I --l...-Lr
LI---

"02...-ut

Re03

-Lr

ReO'

...-U-

R905...-lJ

RECEIVE
BUFFER
DESCRIPTORS

RECEIVE
BUFFERS

BurFER 1

,+--- RECEIVE

BUFFER 2
rRAME LIST

T

T

T

1

1

1

BUFFER ..

BUFFER S

EJ EJ EJ
BurFER 3

- - + ,••- - - - - - -

FREE FRAME LIST

'. 290218-9

Figure 9. Flexible Memory Structure

I

1-75

82596CA

TRANSMITTING FRAMES
The 82596 executes high-level Action Commands
from the Command List in system memory. Action
Commands are fetched and executed in parallel with
the host CPU operation, thereby significantly improving system performance. The format of the Action
Commands is shown in Figure 10. Figure 28 shows
the 82586 mode, and Figures 29 and 30 show the
command formats of the Linear and 32-bit Segmented modes.
A single Transmit command contains, as part of the
command-specific parameters, the destination address and length field of the transmitted frame and a
pointer to buffer area in memory containing the data
portion of the frame. The data field is contained in a
memory data structure consisting of a buffer descriptor (BO), and a data buffer-or a linked list of
buffer descriptors and buffers-as shown in Figure
11.
Multiple data buffers can be chained together using
the BOs. Thus, a frame with a long data field can be
transmitted using several (shorter) data buffers
chained together. This chaining technique allows the
system designer to develop efficient buffer management.

start frame delimiter is 10101011 and the end frame
delimiter is indicated by the lack of a signal after the
last bit of the frame check sequence field has been
transmitted. In EOC, the 82596 can be configured to
extend short frames by adding pad bytes (7Eh) during transmission, according to the length field.
When a collision occurs, the 82596 manages the
jam, random wait, and retry processes, reinitializing
OMA pointers without CPU intervention. Multiple
frames can be sent by linking the appropriate number of Transmit commands together. This is particularly useful when transmitting a message larger than
the maximum frame size (1518 bytes for Ethernet).

I

CONTROL
FIELDS

(POINTER

COMMAND STATUS

I

COMMAND

~~KN~~TL~OMMAND)

•

NEXT
I- COMMAND

PARAMETER FIELD
(COMMAND-SPECIFIC
PARAMETERS)

290216-10

Figure 10. Action Command Format

TRANSMIT BD

The 82596 automatically generates the preamble
(alternating 1s and Os) and start frame delimiter,
fetches the destination address and length field from
the Transmit command, inserts its unique address
as the source address, fetches the data field specified by the Transmit command, and computes and
appends the CRC to the end of the frame (see Figure 12). In the Linear and 32-bit Segmented mode
the CRC can be optionally inserted on a frame-byframe basis by setting the NC bit in the Transmit
Command Block (see Figures 29 and 30).

ACTUAL COUNT
LINK FIELD

•

DB ADDRESS.
(24 BITS)

~ NEXT BUFFER DES CRIPTOR

f--+

DATA
BUFFER
(DB)
290216-11

Figure 11. Data Buffer Descriptor and
Data Buffer Structure

The 82596 generates the standard End Of Carrier
(EOG) start and end frame delimiters. In EOC, the

PREAMBLE

START
FRAME
DELIMITER

DESTINATION
ADDRESS

SOURCE
ADDRESS

LENGTH
FIELD

DATA
FIELD

FRAME
CHECK
SEQUENCE

END
FRAME
DELIMITER

Figure 12. Frame Format

1-76

I

82596CA

RECEIVING FRAMES
To reduce CPU overhead, the 82596 is designed to
receive frames without CPU supervision. The host
CPU first sets aside an adequate receive buffer
space and then enables the 82596 Receive Unit.
Once enabled, the RU watches for arriving frames
and automatically stores them in the Receive Frame
Area (RFA). The RFA contains Receive Frame Descriptors, Receive Buffer Descriptors, and Data Buffers (see Figure 13). The individual Receive Frame
Descriptors make up a Receive Descriptor List
(RDL) used by the 82596 to store the destination
and source addresses, the length field, and the
status of each frame received (see Figure 14).
Once enabled, the 82596 checks each passing
frame for an address match. The 82596 will recognize its own unique address, one or more multicast
addresses, or the broadcast address. If a match is
found the 82596 stores the destination and source
addresses and the length field in the next available
RFD. It then begins filling the next available Data
Buffer on the FBL, which is pointed to by the current
RFD, with the data portion of the incoming frame. As
one Data Buffer is filled, the 82596 automatically
fetches the next DB on the FBL until the entire frame
is received. This buffer chaining technique is particularly memory efficient because it allows the system
designer to set aside buffers to fit frames much
shorter than the maximum allowable frame length. If
AL-LOC = 1, or if the flexible memory structure is
used, the addresses and length field can be placed
in the Receive Buffer.
Once the entire frame is received without error, the
82596 does the following housekeeping tasks.
• The actual count field of the last Buffer Descriptor used to hold the frame just received is updated with the number of bytes stored in the associ. ated Data Buffer.
• The next available Receive Frame Descriptor is
fetched.
• The address of the next available Buffer Descriptor is written to the next available Receive Frame
Descriptor.
• A frame received interrupt status bit is posted in
the SCB.
• An interrupt is sent to the CPU.
If a frame error occurs, for example a CRC error, the
82596 automatically reinitializes its DMA pointers
and reclaims any data buffers containing the bad

I

frame. The 82596 will continue to receive frames
without CPU help as long as Receive Frame Descriptors and Data Buffers are available.

82596 NETWORK MANAGEMENT
AND DIAGNOSTICS
The behavior of data communication networks is
normally very complex because of their distributed
and asynchronous nature. It is particularly difficult to
pinpoint a failure when it occurs. The 82596 has extensive diagnostic and network management functions that help improve reliability and testability. The
82596 reports on the following events after each
frame is transmitted.
• Transmission successful.
• Transmission unsuccessful. Lost Carrier Sense.
• Transmission unsuccessful. Lost Clear to Send.
• Transmission unsuccessful. A DMA underrun occurred because the system bus did not keep up
with the transmission.
• Transmission unsuccessful. The number of collisions exceeded the maximum allowed.
• Number of Collisions. The number of collisions
experienced during transmission of the frame.
• Heartbeat Indicator. This indicates the presence
of a heartbeat during the last Interframe Spacing
(lFS) after transmission.
When configured to Save Bad Frames the 82596
checks each incoming frame and reports the following errors.
• CRC error. Incorrect CRC in a properly aligned
frame.
• Alignment error. Incorrect CRC in a misaligned
frame.
• Frame too short. The frame is shorter than the
value configured for minimum frame length.
• Overrun. Part of the frame was not placed in
memory because the system bus did not keep up
with incoming data.
• Out of buffer. Part of the frame was discarded
because of insufficient memory storage space.
• Receive collision. A collision was detected during
reception and the destination address of the incoming frame matches the 82596 individual address. Collisions in the preamble are not counted.
• Length error. A frame not matching the frame
length parameter was detected.

1-77

intel®

82596CA

RECEIVER FRAME AREA (RFA)

FD

FD

FREE BUFFER LIST (FBL)

~C~~

BUFFER
DESCRIPTOR(RBD)

I

I

-+---.IL___R-lBf-D___•.J•
~ ••••
~ L___R.,Bf-D___.J

1

1

DD

DATA
BUFFER (DB)

290218-12

Figure 13. Receive Frame Area Diagram

RECEIVE FRAME STATUS
LINK FIELD
BUFFER DESCRIPTOR
LINK FIELD

• -.
• -.

NEXT RECEIVE
FRAME DESCRIPTOR
BUFFER DESCRIPTOR

DESTINATION ADDRESS
SOURCE ADDRESS
LENGTH FIELD
290218-13

Figure 14. Receive Frame Descriptor

1·78

I

82596CA

NETWORK PLANNING AND
MAINTENANCE
To properly plan, operate, and maintain a communication network, the network management entity
must accumulate information on network behavior.
The 82596 provides a rich set of network-wide diagnostics that can serve as the basis for a network
management entity.
Information on network activity is provided in the
status of each frame transmitted. The 82596 reports
the following activity indicators after each frame.
• Number of collisions. The number of collisions
the 82596 experienced while attempting to transmit the frame.
• Deferred transmission. During the first transmission attempt the 82596 had to defer to traffic on
the link.
The 82596 updates its 32-bit statistical counters after each received frame that both passes address
filtering and is longer than the Minimum Frame
Length configuration parameter. The 82596 reports
the following statistics.
• CRC errors. The number of well-aligned frames
that experienced a CRC error.
• Alignment errors. The number of misaligned
frames that experienced a CRC error.
• No resources. The number of frames that were
discarded because of insufficient resources for
reception.
• Overrun errors. The number of frames that were
not completely stored in memory because the
system bus did not keep up with incoming data.
• Receive Collision counter. The number of collisions detected during receive. Collisions occurring before the minimum frame length will be
counted as short frames. Collisions in the preamble will not be counted at all.
• Short Frame counter. The number of frames that
were discarded because they were shorter than
the configured minimum frame length.
Once again, these counters are not updated until the
82596 decodes a destination address match.
The 82596 can be configured to Promiscuous mode.
In this mode it captures all frames transmitted on the
network without checking the Destination Address.
This is useful when implementing a monitoring station to capture all frames for analysis.

The 82596 will receive all frames and put them in the
RFD. Frames that exceed the available space in the
RFD will be truncated, the status will be updated,
and the 82596 will retrieve the next RFD. This allows
the user to capture the initial data bytes of each
frame (for instance, the header) and discard the remainder of the frame.
The 82596 also has a monitor mode for network
analysis. During normal operation the receive function enables the 82596 to receive frames that pass
address filtering. These frames must have the Start
of Frame Delimiter (SFD) field and must be longer
than the absolute minimum frame length of 5 bytes
(6 bytes in case of Multicast address filtering). Con. tents and status of the received frames are transferred to memory. The monitor function enables the
82596 to simply evaluate the incoming frames. The
82596 can monitor the frames that pass or do not
pass the address filtering. It can also monitor frames
which do not have the SFD fields. The 82596 can be
configured to only keep statistical information about
monitor frames. Three options are available in the
Monitor mode. These options are selected by the
two monitor mode configuration bits available in the
configuration command.
When the first option is selected, the 82596 receives
good frames that pass address filtering and transfers them to memory while monitoring frames that
do not pass address filtering or are shorter than the
minimum frame size (these frames are not transferred to memory). When this option is used the
82596 updates six counters: CRC errors, alignment
errors, no resource errors, overrun errors, short
frames and total good frames received.
When the second option is selected, the receive
function is completely disabled. The 82596 monitors
only those frames that pass address filterings and
meet the minimum frame length requirement. When
this option is used the 82596 updates six counters:
CRC errors, alignment errors, total frames (good and
bad), short frames, collisions detected and total
good frames.
When the third option is selected, the receive function is completely disabled. The 82596 monitors all
frames, including frames that do not have a Start
Frame Delimiter. When this option is used the 82596
updates six counters: CRC errors, alignment errors,
total frames (good and bad), short frames, collisions
detected and total good frames.

A useful method of capturing frame headers is to
use the Simplified memory mode, configure the
82596 to Save Bad Frames, and configure the
82596 to Promiscuous mode with space in the RFD
allocated for specific number of receive data bytes.

I

1-79

82596CA

STATION DIAGNOSTICS
AND SELF-TEST
The 82596 provides a large set of diagnostic and
network management functions. These include internal and external loop back and time domain reflectometry for locating fault points in the network cable:
The 82596 ensures software reliability by dumping
the contents of the 82596 internal registers into system memory. The 82596 has a self-test mode that
enables it to run an internal self-test and place the
results in system memory.

82586 SOFTWARE COMPATIBILITY
The 82596 has a software-compatible state in which
all its memory structures are compatible with the
82586 memory structure. This includes all the Action
Commands, the Receive Frame Area (including the
RFD, Buffer Descriptors, and Data Buffers), the System Control Block, and the initialization procedures.
There are two minor differences between the 82596
in the 82586-Compatible memory structure and the
82586.
• When the internal and external loopback bits in
the Configure command are set to 11 the 82596
is in external loopback and the LPBK pin is activated; in the 82586 this situation would produce
internal loop back.
• During a Dump command both the 82596 and
82586 dump the same number of bytes; however,
the data format is different.

INITIALIZING THE 82596
A Reset command is issued to the 82596 to prepare
it for normal operation. The 82596 is initialized
through two data structures that are addressed by
two pointers, the System Configuration Pointer
(SCP) and the Intermediate System Configuration
Pointer (ISCP). The initialization procedure begins
when a Channel Attention signal is asserted after
RESET. The 82596 uses the address of the double
word that contains the SCP as a default00FFFFF4h. Before the CA signal is asserted this
default address can be changed to any other available address by asserting the PORT pin and providing the desired address over the 031-04 pins of the
address bus. Pins 03-00 must be 0010; i.e., any
alternative address must be aligned to 16-byte
boundaries. All addresses sent to the 82596 must be
word aligned, which means that all pOinters and
memory structures must start on an even address
(Ao=zero).

SYSTEM CONFIGURATION POINTER
(SCP)
The SCP contains the sysbus byte and the location
of the next structure of the initialization process, the
ISCP. The following parameters are selected in the
SYSBUS.
• The 82596 operation mode.
• The Bus Throttle timer triggering method.
• Lock enabled.
• Interrupt polarity.
• Big Endian 32-bit entity mode.
Byte ordering is determined by the LEIBE pin.
LEIBE = 1 selects Little Endian byte ordering and
LEIBE = 0 selects Big Endian byte ordering.
NOTE:
In the following, X indicates a bit not checked
82586 mode. This bit must be set to 0 in all other
modes.

1-80

I

82596CA

The following diagram illustrates the format of the SCPo
ODD WORD

31

X X X X X X X X

16 15
SYSBUS

X X X X X X X X X X X X X X X

EVEN WORD

10 0

xix

X X X X X X

A31 ................ A24 A23

0

0 0 0 0 0 010 0 0 0 0 0 0 0 OFFFFF4h

xix

X X X X X X X OFFFFF6h

ISCP ADDRESS

AO OFFFFFCh

A31 ................ A24 are not checked in 62566 mode
X .................... X areas are not checked in 62566 mode; they must be 0 in all other modes.
23

SYSBUS

H •• 'N" .,,~.

BE

~,",." 'oC'.,", .~.,. ,,_~---.J

as two 16-bit big endien entities. This is identical to
the 82596 A 1 stepping definition.

J l ·,;, -.,,~.'"~ .~.

I I

16

1 liNT

I I I I Ix I
LOCK

TRG

loll

lola

~ L : NOT CHECKED
a a : 82586 mode

1 - The 32-bit address pointers in linear mode are treated
as 32-bit big endien entities. This mode is only supported
in the 82596 B stepping. In this mode the see absolute
address and statistical counters are still treated as two

1 0 : Linear mode
1 1 : Reserved

a:

16-bit big endien entities.
Interrupt polarity
o - Interrupt pin is active
high
1 - Interrupt pin is active
low

internal triggering of the
Bus Throttle timers
1 : external triggering of the
Bus Throttle timers
-

0 : lock function enabled
1 : lock function disabled

290218-14

ISCP ADDRESS- The physical address of the ISCP. In the 82586 mode, bits A31-A24 are considered to
be zero.

Figure 15. The System Configuration Pointer

Writing the Sysbus
When writing the sysbus byte it is important to pay attention to the byte order.
• When a Little Endian processor is used, the sysbus byte is located at byte address OOFFFFF6h (or address
n+ 2 if an alternative SCP address n was programmed) .
• When a processor using Big Endian byte ordering is used, the sysbus, alternative SCP, and ISCP addresses
will be different.
• The sysbus byte is located at OOFFFFF5h.
• If an alternative SCP address is programmed, the sysbus byte should be at byte address

I

n + 1.

1-81

82596CA

INTERMEDIATE SYSTEM CONFIGURATION POINTER (ISCP)
The ISCP indicates the location of the System Control Block. Often the SCP is in ROM and the ISCP is in RAM.
The CPU loads the SCB address (or an equivalent data structure) into the ISCP and asserts CA. This Channel
Attention signal causes the 82596 to begin its initialization procedure and to get the SCB address from the
ISCP and SCPo In 82586 and 32-bit Segmented modes the SCP base address is also the base address of all
Command Blocks, Frame Descriptors, and Buffer Descriptors (but not buffers). All these data structures must
reside in one 64-KB segment; however, in Linear mode no such limitation is imposed.
The following diagram illustrates the ISCP format.
ODD WORD
31

16 15

A15

SGB OFFSET

EVEN WORD
8 7

AO

r---~----------,,--------------~----------------~--------------~

A23

ISGP

SGB BASE ADDRESS

i
X X X X X X X X - in 82586 mode
A31 ................ A24 - in 32-bit segmented mode.

BUSY

-

Indicates that the 82596 is being initialized. The CPU sets the ISCP to 01 h before it gives
the first CA to the 82596. The ISCP is cleared by the 82596 after the SCB base and offset
are read. Note that the most significant byte of the first word of the ISCI;' is not modified
when BUSY is cleared. .

SGB OFFSET-This 16-bit quantity specifies the offset portion of the address of the SCB.
SCB BASE

-

Specifies the base portion of the address of the SCB. The base of SCB is also the base of
all 82596 Command Blocks, Frame Descriptors and Buffer Descriptors. In the 82586
.
mode, bits A31-A24 are considered to be zero.

Figure 16. The Intermediate System Configuration Pointer-82586 and 32-Bit Segmented Modes
ODD WORD

o

16 15

rO__O
__O
___
.._._
.._._
.._._._
.. _._
.._._
.._.~
.._.~
.._._._
.. _.~
..~._
.._._
..~._._
.. _._
.._.~
.._._
.._._
.._.~O~O~O~____~B~U~S~Y____~ISGP
A31

SGB ABSOLUTE ADDRESS

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

BUSY

-

~

AO ISGP

______________

~

+4

Indicates that the 82596 is being initialized. The ISCP is set to 01 h by the CPU before its
first CA to the 82596. It is cleared by the 82596 after the SCB address is read.

SCB ADDRESS- This 32-bit quantity specifies the physical address of the SCB.
Figure 17. The Intermediate System Configuration Pointer-Linear Mode.

INITIALIZATION PROCESS
The CPU sets up the SCP, ISCP, and the SCB structures, and, if desired, an alternative SCP address. It also
sets BUSY to 01 h. The 82596 is initialized when a Channel Attention signal follows a Reset signal, causing the
82596 to access the System Configuration Pointer. The sysbus byte, the operational mode, the bus throttle
timer triggering method, the interrupt polarity, and the state of LOCK are read. After reset the Bus Throttle
timers are essentially disabled-the T-ON value is infinite, the T-OFF value is zero. After the SCP is read, the
82596 reads the ISCP and saves the SCB address. In 82586 and 32-bit Segmented modes this address is
represented as a base address plus the offset (this base address is also the base address of all the control
blocks). In Linear mode the base address is also an absolute address. The 82596 clears BUSY, sets CX and
CNR to equal 1 in the SCB, clears the SCB command word, sends an interrupt to the CPU, and awaits another
Channel Attention signal. RESET configures the 82596 to its default state before CA is asserted.

1·82

I

82596CA

CONTROLLING THE 82596CA
The host CPU controls the 82596 with the commands, data structures, and methods described in this section.
The CPU and the 82596 communicate through shared memory structures. The 82596 contains two independent units: the Command Unit and the Receive Unit. The Command Unit executes commands from the CPU,
and the Receive Unit handles frame reception. These two units are controlled and monitored by the CPU
through a shared memory structure called the System Control Block (SCB). The CPU and the 82596 use the
CA and INT signals to communicate with the SCB.

82596 CPU ACCESS INTERFACE (PORT)
The 82596 has a CPU access interface that allows the host CPU to do four things.
• Write an alternative System Configuration Pointer address.
• Write an alternative Dump area pointer and perform Dump.
• Execute a software reset.
• Execute a self-test.
The following events initiate the CPU access state.
• Presence of an address on the D31-D4 data bus pins.
• The D3-DO pins are used to select one of the four functions.
• The PORT input pin is asserted, as in a regular write cycle.
NOTE.
The SCP Dump and Self-Test addresses must be 16-byte aligned.

The 82596 requires two 16-bit write cycles for a port command. The first write holds the internal machines and
reads the first 16 bits; the second activates the PORT command and reads the second 16 bits.
The PORT Reset is useful when only the 82596 needs to be reset. The CPU must wait for 1a-system and 5-serial clocks before issuing another CA to the 82596; this new CA begins a new initialization process.
The Dump function is useful for troubleshooting No Response problems. If the chip is in a No Response state,
the PORT Dump operation can be executed and a PORT, Reset can be used to reinitialize the 82596 without
disturbing the rest of the system.
The Self-Test function can be used for board testing; the 82596 will execute a self-test and write the results to
memory.
Table 2_ PORT Function Selection

031 ............................... . '. . 04 ............................ . 00
Function

03

02

01

00

a

a

a

a

A4

a

a

a

1

A4

a

a

1

a

A4

a

a

1

1

Addresses and Results

A31

Don't Care

A4

Self-Test

A31

Self-Test Results Address

SCP

A31

Alternative SCP Address

Dump

A31

Dump Area Pointer

Reset

MEMORY ADDRESSING FORMATS
The 82596 accesses memory by 32-bit addresses. There are two types of 32-bit addresses: linear and segmented. The type of address used depends on the 82596 operating mode and the type of memory structure it
is addressing. The 82596 has three operating modes.

I

1-83

82596CA

• 82586 Mode
• A Linear address is a single 24-bit entity. Address pins A31-A24 are always zero.
• A Segmented address uses a 24-bit base and a 16-bit offset.
• 32-bit Segmented Mode
• A Linear address is a single 32-bit entity.
• A Segmented address uses a 32-bit base and a 16-bit offset.

NOTE:
In the previous two memory addressing modes, each command header (CB, TBD, RFD, RBD, and SCB)
must wholly reside within one segment. If the 82596 encounters a memory structure that does not follow this
restriction, the 82596 will fetch the next contiguous location in memory (beyond the segment).
• Linear Mode
• A Linear address is a single 32-bit entity.
• There are no Segmented addresses.
Linear addresses are primarily used to address transmit and receive data buffers. In the 82586 and 32-bit
Segmented modes, segmented addresses (base plus offset) are used for all Command Blocks, Buffer Descriptors, Frame Descriptors, and System Control Blocks. When using Segmented addresses, only the offset
portion of the entity being addressed is specified in the block. The base for all offsets is the same-that of the
SCB. See Table 1.

LITTLE ENDIAN AND BIG ENDIAN BYTE ORDERING
The 82596 supports both Little Endian and Big Endian byte ordering for its memory structures.
The 82595 A 1 stepping supports Big Endian byte ordering for word and byte entities. Dword entities are not
supported with 82596 A 1 Big Endian byte ordering. This results in slightly different 82596A 1 memory structures for Big Endian operation. These structures are defined in the 32-8;t LAN Components User's Manual.
The 82596 B stepping supports Big Endian byte ordering for Linear mode only. All 82596 B 32-bit address
pointers are treated as 32-bit Big Endian entities, however, the SCB absolute address and statistical counters
are treated as two 16-bit Big Endian entities. This 32-bit Big Endian entity support is configured through bit 7'in
the SYSBUS byte.
The 82596 C-step has a New Enhanced Big Endian Mode where in Linear Addressing mode, true 32-bit Big
Endian functionality is achieved. New Enhanced Big Endian Mode is enabled exactly the same as the B-step,
by setting bit 7 of the SYSBUS byte. This mode is software compatible with the big endian mode of the B-step
with one exception-no 32-bit addresses need to be swapped by software in the C-step. In this new mode, the
82596 C-step treats 32-bit address pointers as true 32-bit entities and the SCB absolute address and statistical
counters are still treated as two 16-bit big end ian entities. Not setting this mode will configure the 82596 C-step
to be 100% compatible to the A 1-step big endian mode.

NOTE:
All 82596 memory entities must be word or dword aligned, except the transmit buffers can be byte aligned
.
for the 82596 B or C-steppings.
An example of a dword entity is a frame descriptor command/status dword, whereas the raw data of the frame
are byte entities. Both 32- and 16-bit buses are supported. When a 16-bit bus is used with Big Endian memory
organization, data lines 015-00 are used. The 82596 has an internal crossover that handles these swap
operations.

1-84

I

82596CA

COMMAND UNIT (CU)
The Command Unit is the logical unit that executes Action Commands from a list of commands very similar to
a CPU program. A Command Block is associated with each Action Command. The CU is modeled as a logical
machine that takes, at any given time, one of the following states.
• Idle. The CU is not executing a command and is not associated with a CB on the list. This is the initial state.
• Suspended. The CU is not executing a command; however, it is associated with a CB on the list.
• Active. The CU is executing an Action Command and pointing to its CB.
The CPU can affect CU operation in two ways: by issuing a CU Control Command or by setting bits in the
Command word of the Action Command.
When programming the 82596 CU, it is important to consider the asynchronous way the 82596 processes
commands. If a command is issued to the 82596 CU, it may be busy processing other commands. In order to
avoid asynchronous race conditions, the following guidelines are recommended to the 82596 programmer:
• If the CU is already in the Active state, and another command needs to be executed, it is unwise to
immediately issue another CU Start command. If a new command (or list of commands) needs to be
started, first issue a CU Suspend command, wait for the CU to become Suspended, then issue the new CU
Start. This will insure that all commands are processed correctly.
• In general, it is a good idea to make sure any CU command has been accepted and executed before
issuing a new control command to the CU.

RECEIVE UNIT (RU)
The Receive Unit is the logical unit that receives frames and stores them in memory. The RU is modeled as a
logical machine that takes, at any given time, one of the following states.
• Idle. The RU has no memory resources and is discarding incoming frames. This is the initial state.
• No Resources. The RU has no memory resources and is discarding incoming frames. This state differs
from Idle in that the RU accumulates statistics on the number of discarded frames.
• Suspended. The RU has memory available for storing frames, but is discarding them. The suspend state
can only be reached if the CPU forces this through the SCB or sets the suspend bit in the RFD.
• Ready. The RU has memory available and is storing incoming frames.
The CPU can affect RU operation in three ways: by issuing an RU Control Command, by setting bits in the
Frame Descriptor Command word of the frame being received, or by setting the EL bit of the current buffer'S
Buffer Descriptor.
When programming the 82596 RU, it is important to consider the asynchronous way the 82596 processes
receive frames. If an RU Start is issued to the 82596 RU, it may be busy processing other incoming packets. In
order to avoid asynchronous race conditions, the following guidelines are recommended to the 82596 programmer:
• If the RU is already in the Ready state, and a new RFA is required to be started, it is unwise to immediately
issue another RU Start command. If the new RFA needs to be started, first issue an RU Suspend command, wait for the RU to become Suspended, then issue the new RU Start. This will insure that all incoming
frames are received correctly.
• In general, it is a good idea to make sure any RU command has been accepted and executed before
-issuing a new control command to the RU.

I

1-85

82596CA

SYSTEM CONTROL BLOCK (SCB)
The SCB is a memory block that plays a major role in communications between the CPU and the 82596. Such
communications include the following.
• Commands issued by the CPU
• Status reported by the 82596
Control commands are sent to the 82596 by writing them into the SCB and then asserting CA. The 82596
examines the command, performs the required action, and then clears the SCB command word. Control
commands perform the following types of tasks.
• Operation of the Command Unit (CU). The SCB controls the CU by specifying the address of the Command
Block List (CBL) and by starting, suspending, resuming, or aborting execution of CBL commands.
• Operation of the Bus Throttle. The SCB controls the Bus Throttle timers by providing them with new values
and sending the Load and Start timer commands. The timers can be operated in both the 32-bit Segmented
and Linear modes.
• Reception of frames by the Receive Unit (RU). The SCB controls the RU by specifying the address of the
Receive Frame Area and by starting, suspending, resuming, or aborting frame reception.
• Acknowledgment of events that cause interrupts.
• Resetting the chip.
The 82596 sends status reports to the CPU via the System Control Block. The SCB contains four types of
status reports.
• The cause of the current interrupts. These interrupts are caused by one or more of the following 82596
events.
• The Command Unit completes an Action Command that has its I bit set.
• The Receive Unit receives a frame.
• The Command Unit becomes inactive.
• The Receive Unit becomes not ready.
• The status of the Command Unit.
• The status of the Receive Unit.
• Status reports from the 82596 regarding reception of corrupted frames.

1-86

I

82596CA

Events can be cleared only by CPU acknowledgment. If some events are not acknowledged by the ACK field
the Interrupt signal (INT) will be reissued after Channel Attention (CA) is processed. Furthermore, if a new
event occurs while an interrupt is set, the interrupt is temporarily cleared to trigger edge-triggered interrupt
controllers.
The CPU uses the Channel Attention line to cause the 82596 to examine the 8CB. This signal is trailing-edge
triggered-the 82596 latches CA on the trailing edge. The latch is cleared by the 82596 before the 8CB
control command is read.
31
ACK

JI
X

ODD WORD

cuc

1R I

RUC

IX

16 15

EVEN WORD
STAT

X X X

10 1

cus

I0 I

RUS

0
I0

0 0 0 SCB

+4
+8
SCB + 12

RFAOFFSET

CBLOFFSET

SCB

ALIGNMENT ERRORS

CRCERRORS

SCB

OVERRUN ERRORS

RESOURCE ERRORS

Figure 18. SCB-82586 Mode
31

16 15

ODD WORD
ACK

I0 I

cuc

IRI

RUC

I0

o

0 01

o

EVEN WORD
STAT

101

J

CUS ·1

RUS

ITlo 0

0 SCB

ALIGNMENT ERRORS

SCB

+4
+8
+ 12

RESOURCE ERRORS (*)

SCB

+

OVERRUN ERRORS (*)

SCB

+ 20

RCVCDT ERRORS (*)

SCB

+ 24

SHORT FRAME ERRORS

SCB

+ 28

SCB

+ 32

RFAOFFSET

CBLOFFSET

SCB

CRCERRORS

SCB

I

T-ON TIMER

T-OFFTIMER

16

*In monitor mode these counters change function

Figure 19. SCB-32-Bit Segmented Mode
31

16 15

ODD WORD
ACK

I0 I

cuc

IRI

RUC

10 0 0

01

EVEN WORD
STAT

1 0 1 CUS

I

RUS

0
ITlo 0

0 SCB

COMMAND BLOCK ADDRESS

SCB

RECEIVE FRAME AREA ADDRESS

SCB

CRCERRORS

SCB

ALIGNMENT ERRORS

SCB

RESOURCE ERRORS (*)

SCB

OVERRUN ERRORS (*)

SCB

RCVCDT ERRORS (*)

SCB

SHORT FRAME ERRORS

SCB

I

T-ONTIMER

T·OFFTIMER

SCB

+
+
+
+
+
+
+
+
+

4
8
12
16
20
24
28
32
36

*In MONITOR mode these counters change function

Figure 20. SCB-Linear Mode

I

1-87

intel®

82596CA

Command Word
31

16

A?K

0

: eue:

A

: Aue:

0

0

0

0

5eB + 2

These bits specify the action to be performed as a result of a CA. This word is set by the CPU and cleared by
the 82596. Defined bits are:
Bit 31 ACK-CX

-

Acknowledges that the CU completed an Action Command.

Bit 30 ACK-FR

-

Acknowledges that the RU received a frame.

Bit 29 ACK-CNA

-

Acknowledges that the Command Unit became not active.

Bit 28 ACK-RNR

-

Acknowledges that the Receive Unit became not ready.

Bits 24-26 CUC

-

(3 bits) This field contains the command to the Command Unit. Valid values are:

o -

Bit 23 RESET

-

Bits 20-22 RUC

-

NOP (does not affect current state of the unit).

-

Start execution of the first command on the CBL. If a command is executing,
complete it.before starting the new CBL. The beginning of the CBl is in CBl
OFFSET (address).

2

-

Resume the operation of the Command Unit by executing the next command.
This operation assumes that the Command Unit has been previously suspended.

3

-

Suspend execution of commands on CBl after current command is complete.

4

-

Abort current command immediately.

5

-

loads the Bus Throttle timers so they will be initialized with their new values
after the active timer (T-ON or T-OFF) reaches Terminal Count. If no timer is
active new values will be loaded immediately. This command is not valid in
82586 mode.

6

-

loads and immediately restarts the Bus Throttle timers with their new values.
This command is not valid in 82586 mode.

7

-

Reserved.

Reset chip (logically the same as hardware RESET).
(3 bits) This field contains the command to the Receive Unit. Valid values are:

o -

NOP (does not alter current state of unit).
Start reception of frames. The beginning of the RFA is contained in the RFA
OFFSET (address). If a frame is being received complete reception before
starting.

2

-

Resume frame reception (only when in suspended state).

3

-

Suspend frame reception. If a frame is being received complete its reception
before suspending.

4

-

Abort receiver operation immediately.

5-7 - Reserved.

1-88

I

82596CA

Status Word
0

15

o I

: GUS:

o

: RUS:

0

0

I

0

0

T

0

I

0

0

SGB

82586 mode
0

15

32-Bit Segmented and Linear mode.

I SGB

Indicates the status of the 82596. This word is modified only by the 82596. Defined bits are:
The CU finished executing a command with its I (interrupt) bit set.

Bit 15 CX

-

Bit 14 FR

- The RU finished receiving a frame.

Bit 13 CNA

-

The Command Unit left the Active state.

Bit 12 RNR

-

The Receive Unit left the Ready state.

Bits 8-10 CUS

-

(3 bits) This field contains the status of the command unit. Valid values are:

o

-Idle
-

2

3-7 Bits 4-7 RUS

Suspended

-Active
Not used

- This field contains the status of the receive unit. Valid values are:
Oh (0000) -

Idle

1h (0001) -

Suspended

2h (0010) -

No Resources. This bit indicates both no resources due to lack of
RFDs in the RDL and no resources due to lack of RBDs in the FBL.

4h (0100) -

Ready

Ah (1010) -

No resources due to no more RBDs (not in the 82586 mode).

Ch (1100) -

No more RBDs (not in 82586 mode)

No other combinations are allowed
Bit3T

-

Bus Throttle timers loaded (not in 82586 mode).

SCB OFFSET ADDRESSES
CBl Offset (Address)
In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the
first Command Block on the CBL. In Linear mode it is a 32-bit linear address for the first Command Block on
the CBL. It is accessed only if CUC equals Start.

RFA Offset (Address)
In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the
Receive Frame Area. In Linear mode it is a 32-bit linear address for the Receive Frame Area. It is accessed
only if RUC equals Start.

I

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82596CA

SCB STATISTICAL COUNTERS
Statistical Counter Operation
• The CPU is responsible for clearing all error counters before initializing the 82596. The 82596 updates
these counters by reading them, adding 1, and then writing them back to the SCB.
• The counters are wraparound counters. After reaching FFFFFFFFh the counters wrap around to zero.
• The 82596 updates the required counters for each frame. It is possible fo~ more than one counter to be
updated; multiple errors will result in all affected counters being updated.
• The 82596 executes the read-counter/incrementlwrite-counter operation without relinquishing the bus
(locked operation). This is to ensure that no logical contention exists between the 82596 and the CPU due
to both attempting to write to the counters simultaneously. In the dual-port memory configuration the CPU
should not execute any write operation to a counter if LOCK is asserted.
• The counters are 32-bits wide and their behavior is fully compatible with the IEEE 802.3 standard. The
82596 supports all relevant statistics (mandatory, optional, and desired) through the status of the transmit
and receive header and directly through SCB statistics.

CRCERRS
This 32-bit quantity contains the number of aligned frames discarded because of a CRC error. This counter is
updated, if needed, regardless of the RU state.
.

ALNERRS
This 32-bit quantity contains the number of frames that both are misaligned (i.e., where CRS deasserts on a
nonoctet boundary) and contain a CRC error. The counter is updated, if needed, regardless of the RU state.

SHRTFRM
This 32-bit quantity contains the number of received frames shorter than the minimum frame length.
The last three counters change function. in monitor mode.

RSCERRS
This 32-bit quantity contains the number of good frames discarded because there were no resources to
contain them. Frames intended for a host whose RU is in the No Receive Resources state, fall into this
category. This counter is updated only if the RU is in the No Resources state. When in Monitor mode this
counter counts the total number of frames-good and bad.

I

82596CA

OVRNERRS
This 32-bit quantity contains the number of frames known to be lost because the local system bus was not
available. If the traffic problem lasts longer than the duration of one frame, the frames that follow the first are
lost without an indicator, and they are not counted. This counter is updated, if needed, regardless of the RU
state.
This 32-bit counter contains the number of collisions detected during frame reception. This counter will only be
updated if at least 64 bytes of data are received before the collision occurs. If a collision occurs before 64
bytes of data are received, the frame is counted as a short frame. If the collision occurs in the preamble, no
counters are incremented.

ACTION COMMANDS AND OPERATING MODES
This section lists all the Action Commands of the Command Unit Command Block List (CBL). Each command
contains the Command field, the Status and Control fields, the link to the next Action Command, and any
command-specific parameters. There are three basic types of action commands: 82596 Configuration and
Setup, Transmission, and Diagnostics. The following is a list of the actual commands.
• NOP

• Transmit

• Individual Address Setup

• TOR
• Dump
• Diagnose

• Configure
• MC Setup

The 82596 has three addressing modes. In the 82586 mode all the Action Commands look exactly like those
of the 82586.
• 82586 Mode. The 82596 software and memory structure is compatible with the 82586.
• 32-Bit Segmented Mode. The 82596 can access the entire system memory and use the two new memory
structures-Simplified and Flexible-while still using the segmented approach. This does not require any
significant changes to existing software.
• Linear Mode. The 82596 operates in a flat, linear, 4 gigabyte memory space without segmentation. It can
also use the two new memory structures.

In the 32-bit Segmented mode there are some differences between the 82596 and 82586 action commands,
mainly in programming and activating new 82596 features. Those bits marked "don't care" in the compatible
mode are not checked; however, we strongly recommend that those bits all be zeroes; this will allow future
enchancements and extensions.
In the Linear mode all of the address offsets become 32-bit address pointers. All new 82596 features are
accessible in this mode, and all bits previously marked "don't care" must be zeroes.
The Action Commands, and all other 82596 memory structures, must begin on even byte boundaries, i.e., they
must be word aligned.

I

1-91

82596CA

NOP
This command results in no action by the 82596 except for those performed in the normal command processing. It is used to manipulate the CBl manipulation. The format of the Nap command is shown in Figure 21.

NOP-82586 and 32-Blt Segmented Modes'
ODD WORD

EVEN WORD

x X X X X X X X X X

o

o 0 o. 0 0 0 0 0 0 0 0 0

X XX X X XX X X X

LINK OFFSET

AO 4

EVEN WORD

o

NOP-Linear Mode
ODD WORD

000

0

0

0

0

00000000000000

AO 4

where:
LINK POINTER
El

-In the 82586 or 32-bit Segmented modes this is a 16-bit offset to the next Command
Block. In the Linear mode this is the 32-bit address of the next Command Block.
- If set, this bit indicates that 'this command block is the last on the CBL.

S

-

If set to one, suspend the CU upon completion of this CB.

-

If set to. one, the 82596 will gerierate an interrupt after execution of the command is
complete. If I is not set to one, the CX bit will not be set.
CMD (bits 16-18) - The Nap command. Value: Oh.
Bits 19-28

-

C

-;- This bit indicates the execution status of the command, The CPU initially resets it to zero
when the Command Block is placed on the CBL. Following a command Completion, the
82596 will set it to one.
-"" This bit indicates that the 82596 is currently executing the Nap command. It is initially
reset to zero by the CPU. The 82596 sets it to.one when execution begins and to zero
when execution is completed. This bit is also set when the 82596 prefetches .the command.

B

Reserved (zero in the 32-bit Segmented and Linear modes).

NOTE:
The C and B bits are modified in one operation.
OK

-

Indicates that the command was executed without error. If set to one no error occurred
(command executed OK). If zero an error occured.

Individual Address Setup
This command is used to load the 82596 with the Individual Address. This address is used by the 82596 for
inserting the Source Address during transmission and recognizing the Destination Address during reception.
After RESET, and prior to Individual Address Setup Command execution, the 82596 assumes the Broadcast
Address is the Individual Address in all aspects, I.e.:
• This will be the Individual Address Match reference .
• This will be the Source Address of a transmitted frame (for Al-lOC = 0 mode only).

1-92

I

82596CA

The format of the Individual Address Setup command is shown in Figure 22.
IA Setup-82586 and 32-Bit Segmented Modes
1615

ODD WORD

31
ELI S II I X

X

X

X

X

X

X

X

X

xlo

INDIVIDUAL ADDRESS

0

1

0

1st byte A15
5th byte

6th byte

0

EVEN WORD

c I B lOKI A 10

0

0

0

0

0

0

0

0

0

LINK OFFSET

o

0

A04

4th byte

3rd byte

8

IA Setup-Linear Mode
31

1615

ODD WORD

ELI S II 10

0

0

0

0

0

0

0

0

010

A31

0

1

0

EVEN WORD

c I B lOKI A

I0

0

0

0

0

0

0

0

0

0

3rd byte

o

0

AO 4

LINK ADDRESS
4th byte

0

INDIVIDUAL ADDRESS

1st byte

8

6th byte

5th byte

C

Figure 22

where:
LINK ADDRESS,
EL, B, C, I, S

-

As per standard Command Block (see the NOP command for details)

A

-

Indicates that the command was abnormally terminated due to CU Abort control
command. If one, then the command was aborted, and if necessary it should be
repeated. If this bit is zero, the command was not aborted.

Bits 19-28
CMD (bits 16-18)

-

Reserved (zero in the 32-bit Segmented and Linear modes).
The Address Setup command. Value: 1h.

INDIVIDUAL ADDRESS -

The individual address of the node, 0 to 6 bytes long.

The least significant bit of the Individual Address must be zero for Ethernet (see the Command Structure).
However, no enforcement of 0 is provided by the 82596. Thus, an Individual Address with 1 as its least
significant bit is a valid Individual Address in all aspects.
The default address length is 6 bytes long, as in 802.3. If a different length is used the IA Setup command
should be executed after the Configure command.

Configure
The Configure command loads the 82596 with its operating parameters. It allows changing some of the
parameters by specifying a byte count less than the maximum number of configuration bytes (11 in the 82586
mode, 14 in the 32-Bit Segmented and Linear modes). The 82596 configuration depends on its mode of
operation. When configuring the 12th byte (Byte 11 undefined) in 82586 mode this byte should be all ones.
• In the 82586 mode the maximum number of configuration bytes is 12. Any number larger than 12 will be
reduced to 12 and any number less than 4 will be increased to 4.
• The additional features of the serial side are disabled in the 82586 mode.
• In both the 32-Bit Segmented and Linear modes there are four additional configuration bytes, which hold
parameters for additional 82596 features. If these parameters are not accessed, the 82596 will follow their
default values.
• For more detailed information refer to the 32-Bit LAN Components User's Manual.

I

1-93

82596CA

The format of the Configure command is shown in Figure 23, 24 and 25.
31

ODD WORD

ELISJ I

Jx

x

x

x

x

x

x

1615
x

X xlo

1

o

EVEN WORD

G I B lOKI A 10

0

' A15

0

0

0

0

0
0

0

0

0

0

Byte 1

Byte 0

Byte 5

Byte 4

Byte 3

Byte 2

8

Byte 9

Byte 8

Byte 7

Byte6 ,

12

X X X X X

Byte 10

16

X X X X X X X X X X X X X X X X X X

LINK OFFSET

o 0

X

AO 4

Figure 23. CONFIGURE-82586 Mode
31

ODD WORD

ELI S II 10

0

0

0

0

0

0

1615
0

0

010

1

EVEN WORD

o c I B lOKI A I 0

0

A15

0

0

0

0

0
0

0

0

0

0

LINK OFFSET

o 0

Byte 1

Byte 0

Byte 5

Byte 4

Byte 3

Byte 2

8

Byte 9

Byte 8

Byte 7

Byte 6

12

Byte 13

Byte 12

Byte 11

Byte 10

16

AO 4

Figure 24. CONFIGURE-32-Blt Segmented Mode
31

ODD WORD

ELI S II 10

0

0

0

0

0

0

1615
0

0

010

A31

1

o

EVEN WORD

c I B lOKI A I 0

0

0

0

0

0
0

0

0

0

0

LINK ADDRESS'

0

o 0
AO 4

Byte 3

Byte 2

Byte 1

Byte 0

8

Byte 7

Byte 6

Byte 5

Byte 4

12

Byte 11

Byte 10

Byte 9,

Byte 8

16

Byte 13

Byte 12

20

X X X X X X X X X X X X X X X X

Figure 25. CONFIGURE-Linear Mode
LINK ADDRESS, EL, B, C,I, S

As per standard Command Block (see the NOP command for detaiis)

A

-

Indicates that the command was abnormally terminated due to a CU Abort control command. If 1, then the command was aborted and if necessary it should be repeated. If this
bit is 0, the command was not aborted.

Bits 19-28

-

CMD (bits 16-18) -

Reserved (zero in the 32-Bit Segmented and Linear Modes)
The CONFIGURE command. Value: 2h.

The interpretation of the fields follows:
7

6

5

p

X

X

4

,I

x

3

2

1

o

BYTE¢OUNT

BYTE 0
BYTE CNT (Bits 0-3)

Byte Count. Number of bytes, including this one, that hold pa'
rameters to be configured.

PREFETCHED (Bit 7)

Enable'the 82596 to write the prefetched bit in all prefetch
RBDs.

1-94

I

82596CA

NOTE:
The P bit is valid only in the new memory structure modes. In 82586 mode this bit is disabled (Le., no
prefetched mark).

o

7

x

x

FIFO:LlMIT

BYTE 1
FIFO Limit (Bits 0-3)

FIFO limit.

MONITOR # (Bits 6-7)

Receive monitor options. If the Byte Count of the configure
command is less than 12 bytes then these Monitor bits are ignored.

DEFAULT: C8h

o

7

o

SAVBF

BYTE

o

o

o

o

2

SAY BF (Bit 7)

O-Received bad frames are not saved in the memory.
1-Received bad frames are saved in the memory.

DEFAULT: 40h

o-

RESUME_RD (Bit 1)

The 82596 does not reread the next CB on the list when a CU Resume
Control Command is issued.

1 - The 82596 will reread the next CB on the list when a CU Resume
Control Command is issued. This is available only on the 82596B stepping.

o

7
LOOP BACK
MODE

PREAMBLE LENGTH

BYTE 3
ADR LEN (Bits 0-2)

ADDRESS LENGTH

Address length (any kind).

NO SCR ADD INS (Bit 3)

No Source Address Insertion.
In the 82586 this bit is called AL LOC.

PREAM LEN (Bits 4-5)

Preamble length.

LP BCK MODE (Bits 6-7)

Loopback mode.

DEFAULT: 26h

o

7

IBOFMETD I
BYTE 4
LIN PRIO (Bits 0-2)

o
Linear Priority.

EXP PRIO (Bits 4-6)

Exponential Priority.

BOF METD (Bit 7)

Exponential Backoff method.

DEFAULT: OOh

o

7
: INTER FRA¥E SPACING :

BYTE 5
INTERFRAME SPACING

Interframe spacing.

DEFAULT: 60h

I

1-95

82596CA

o

7

SLOT m~E . LOW
BYTE 6
SLOT TIME (L)

Slot time, low byte.

DEFAULT: OOh

o

7

~AXIMUM RE!RY NUMBE~

o

S~OT TIME . HI~H

BYTE 7
SLOT TIME (H)
(Bits 0-2)

Slot time, high part.

RETRY NUM (Bits 4-7)

Number of transmission retries on collision.

DEFAULT: F2h
7

BYTES
PRM (Bit 0)

Promiscuous mode.

BC DIS (Bit 1)

Broadcast disable.

MANCH/NRZ (Bit 2)

Manchester or NRZ encoding. See specific timing requirements for TXC in Manchester mode.

TONO CRS (Bit 3)

Transmit on no CRS.

NOCRC INS (Bit 4)

No CRC insertion.

CRC-16/CRC-32 (Bit 5)

CRC type.

BIT STF (Bit 6)

Bit stuffing.

PAD (Bit 7)

Padding.

DEFAULT: OOh

7

0

~1_C_DT_S_R_C~I___c_O_LL_IS~iIO_N_D_E_TE_C_T~:F_IL_TE_R__~_C_R_S_S_RC~____C_A_RR~:I_ER_S_E_N_S_E~~_~_E_R____I
BYTE 9
CRSF (Bits 0-2)

Carrier Sense filter (length).

CRS SRC (Bit 3)

Carrier Sense source.

CDTF (Bits 4-6)

Collision Detect filter (length).

COT SRC (Bit 7)

Collision Detect source.

DEFAULT: OOh

1-96

I

82596CA

o

7
: MINIMUM

FR~ME LENGTH

:

BYTE 10
MIN FRAME LEN

Minimum frame length.

DEFAULT: 40h

o

7
MCJLL

COBSAC

AUTOTX

CRCINM

LNGFLO

PRECRS

I

BYTE 11
PRECRS (Bit 0)

Preamble until Carrier Sense

LNGFLD (Bit 1)

Length field. Enables padding at the End-of-Carrier framing (802.3).

CRCINM (Bit 2)

Rx CRC appended to the frame in memory.

AUTOTX (Bit 3)

Auto retransmit when a collision occurs during the preamble.

CDBSAC (Bit 4)

Collision Detect by source address recognition.

MCJLL (Bit 5)

Enable to receive all MC frames.

MONITOR (Bits S-7)

Receive monitor options.

DEFAULT: FFH
7

o

FOX

BYTE 12
FDX (BitS)

o

o

o

o

I

o
0

o

Enables Full Duplex operation.

DEFAULT: OOh

o

7

BYTE 13
MULT_IA (Bit S)
DIS_BOF (Bit 7) .

Multiple individual address.
Disable the backoff algorithm.

DEFAULT: 3Fh

I

1-97

82596CA

A reset (hardware or software) configures the 82596 according to the following defaults.

Table 4. Configuration Defaults
Parameter

•
•
•

•

•

•

•
•

•

•

ADDRESS LENGTH
AIL FIELD LOCATION
AUTO RETRANSMIT
BITSTUFFING/EOC
BROADCAST DISABLE
CDBSAC
CDTFILTER
CDTSRC
CRC IN MEMORY
CRC-16/CRC-32
CRSFILTER
CRSSRC
DISBOF
EXT LOOPBACK
EXPONENTIAL PRIORITY
EXPONENTIAL BACKOFF METHOD
FULL DUPLEX (FDX)
FIFO THRESHOLD
INT LOOPBACK
INT.ERFRAME SPACING
LINEAR PRIORITY
LENGTH FIELD
MIN FRAME LENGTH
MCALL
MONITOR
MANCHESTERiNRZ
MULTI IA
NUMBER OF RETRIES
NO CRC INSERTION
PREFETCH BIT IN RBD
PREAMBLE LENGTH
Preamble UntilCRS
PROMISCUOUS MODE
PADDING
SLOT TIME
SAVE BAD FRAME
TRANSMIT ON NO CRS

Default Value
"6
0
1
0
0
1
0
0
"0
0
0
-0
0
"0
"0
0
8
0
"96
"0
"64
1
11
0
0
"15
0
0

"7
1
0
0
"512
0
0

Units/Meaning
Bytes
Located in FD
Auto Retransmit Enable
EOC
Broadcast Reception Enabled
Disabled
Bit Times
External Collision Detection
CRC Not Transferred to Memory
.CRC-32
o Bit Times
External CRS
Backoff Enabled
Disabled·
802.3 Algorithm
802.3 Algorithm
CSMAlCD Protocol (No FDX)
TX: 32 Bytes, RX: 64 Bytes
Disabled
Bit Times
802.3 Algorithm
Padding Disabled
Bytes
Disabled
Disabled
NRZ
Disabled
Maximum Number of Retries
_CRC Appended to Frame
Disabled (Valid Only in New Modes)
Bytes
Disabled
Address Filter On
No Padding
Bit Times
Discards Bad Frames
Disabled

NOTES:
1. This configuration setup is compatible with the IEEE 802.3 specification.
2. The Asterisk "." signifies a new configuration parameter not available in the 82586.
3. The default value of the Auto retransmit configuration parameter is enabled(1).
4. Double Asterisk " •• " signifies IEEE 802.3 requirements.

1-98

I

82596CA

Multicast-Setup
This command is used to load the 82596 with the Multicast-IDs that should be accepted. As noted previously,
the filtering done on the Multicast-IDs is not perfect and some unwanted frames may be accepted. This
command resets the current filter and reloads it with the specified Multicast-IDs. The format of the Multicastaddresses setup command is:
31
ELI S II I X

ODDWORD
X

X

X

X

X

X

16 15
X

X xlo

1

MCCOUNT

xlxl

1

C I B lOKI A 10

EVEN WORD

0

A15

0

0

0

0
0

0

0

0

0

0

LINK OFFSET

0
AO

4th byte

1st byte
MULTICAST Ai DRESSES LIST

Nth byte

Figure 26. MC Setup-82586 and 32·Bit Segmented Modes
31
ELI S II 10

ODD WORD

o

0

0

0

o

0

16 15
o

0

010

1

1 I C I B lOKI A I 0

EVEN WORD
o

0

000

0
0

0

0

LINK ADDRESS

A31
2nd byte

1st byte I X I X I

o

0

0
AO

MCCOUNT

MULTICAST A,DRESSES LIST
Nth byte

Figure 27. MC Setup-Linear Mode
where:
LINK ADDRESS,
EL, B, C, I, S

-

As per standard Command Block (see the NOP command for details)

A

-

Indicates that the command was abnormally terminated due to a CU Abort control
command. If one, then the command was aborted and if necessary it should be
repeated. If this bit is zero, the command was not aborted.

Bits 19-28

-

Reserved (0 in both the 32-Bit Segmented and Linear Modes).

CMD (bits 16-18)

- The MC SETUP command value: 3h.

MC-CNT

MC LIST

This 14-bit field indicates the number of bytes in the MC LIST field. The MC CNT
must be a multiple of the ADDR LEN; otherwise, the 82596 reduces the MC CNT to
the nearest AD DR LEN multiple. MC CNT = 0 implies resetting the Hash table
which is equivalent to disabling the Multicast filtering mechanism.
-

A list of Multicast Addresses to be accepted by the 82596. The least significant bit
of each MC address must be 1.

NOTE:
The list is sequential; i.e., the most significant byte of an address is immediately followed by the least significant byte of the next address.
When the 82596 is configured to recognize multiple Individual Address (Multi-IA),
the MC-Setup command is also used to set up the Hash table for the individual
address.
The least significant bit in the first byte of each IA address must be o.
-

I

1-99

82596CA

Transmit
This command is used to transmit a frame of user data onto the serial link. The format of a Transmit command
is as follows.
31

ODD WORD

ELI S II I X

1615

x x x x x x x x

A15

Xli

0

TBDOFFSET

0

EVEN WORD

C IBI

AO A15

4th byte

STATUS BITS

I
LINK OFFSET

DESTINATION ADDRESS
LENGTH FIELD

0
MAXCOLL

0
AO 4

1st byte 8

6th byte

12

Figure 28. TRANSMIT-82586 Mode
31

ODD WORD

1615

ELlsl 1i010101010101010INClsFI1
A15

o

0

TBDOFFSET
0

0

0

0

0

0

0

0

C

EVEN WORD

IB I

AO A15

000

0

o

0

0

o

4th byte

STATUS BITS

I

LINK OFFSET

0
AO 4

'TCBCOUNT

EOFI 0 I
DESTINATION ADDRESS

LENGTH FIELD

0
MAXCOLL

8
1st byte 12

6th byte

16

OPTIONAL DATA

Figure 29. TRANSMIT-32-Blt Segmented Mode
31

ODD WORD

1615

ELlsl 1i010101010101010INClsFI1
A31

0

C IBI

EVEN WORD
STATUS BITS

I

LINK ADDRESS

A31

o

0

000

o

0

0

0

o

0

0 0 0 0 0 EOFI 0 I

4th byte

DESTINATION ADDRESS

LENGTH FIELD

6th byte

0
AO 4

TRANSMIT BUFFER DESCRIPTOR ADDRESS
0

0
MAXCOLL

AO 8
TCBCOUNT

12
1st byte 16
20

.OPTIONAL DATA

Figure 30. TRANSMIT-Linear Mode
31

COMMAND WORD

16

IELI S II I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 INClsFI1

0

0 12

t t
0: No CRC Insertion disable; when the 0: Simplified Mode, all the Tx data is in
configure command is configured to
the Transmit Command Block. The
Transmit Buffer Descriptor Address
not insert the CRC during
field is all 1s.
transmission the NC bit has no
effect.
1:. Flexible Mode. 'Data is in the TCB and
1: No CRC Insertion enable; when the
in a linked list of TBDs.
configure command is configured to
insert the CRC during transmisSion
the CRC will not be inserted when
NC = 1.

1-100

I

82596CA

where:
EL, B, C, I, S
OK (Bit 13)
A (Bit 12)

-

As per standard Command Block (see the NOP command for details).
Error free completion.

-

Indicates that the command was abnormally terminated due to CU Abort control
command. If 1, then the command was aborted, and if necessary it should be
repeated. If this bit is 0, the command was not aborted.

Bits 19-28
CMD (Bits 16-18)
Status Bit 11

- Reserved (0 in the 32-bit Segmented and Linear modes).
- The transmit command: 4h.
- Late collision. A late collision (a collision after the slot time is elapsed) is detected.

Status Bit 10

-

Status Bit 9

- Transmission unsuccessful (stopped) due to Loss of CTS.
- Transmission unsuccessful (stopped) due to DMA Underrun; i.e., the system did
not supply data for transmission.
- Transmission Deferred, i.e., transmission was not immediate due to previous link
activity.

Status Bit 8
Status Bit 7

No Carrier Sense signal during transmission. Carrier Sense sig'nal is monitored
from the end of Preamble transmission until the end of the Frame Check Sequence
for TONOCRS = 1 (Transmit On No Carrier Sense mode) it indicates that transmission has been executed despite a lack of CRS. For TONOCRS = 0 (Ethernet
mode), this bit also indicates unsuccessful transmission (transmission stopped
when lack of Carrier Sense has been detected).

'Status Bit 6

-

Status Bit 5

- Transmission attempt was stopped because the number of collisions exceeded the
maximum allowable number of retries.

Status Bit 4
MAX-COL
(Bits 3-0)

Heartbeat Indicator, Indicates that after a previously performed transmission, and
before the most recently performed transmission, (Interframe Spacing) the COT
signal was monitored as active. This indicates that the Ethernet Transceiver Collision Detect logic is performing properly. The Heartbeat is monitored during the
Interframe Spacing period.

LINK OFFSET

- 0 (Reserved).
- The number of Collisions experienced during this frame. Max Col = 0 plus S5 = 1
indicates 16 collisions.
- As per standard Command Block (see the NOP Command for details)

TBDPOINTER

-

DEST ADDRESS

-

LENGTH FIELD

If the Destination Address bits are all 1s this is a Broadcast Address.
- The contents of this 2-byte field are user defined. In 802.3 it contains the length of
the data field. It is placed in memory in the same order it is transmitted; i.e., most
significant byte first, least significant byte second.

In the 82586 and 32-bit Segmented modes this is the offset of the first Tx Buffer
Descriptor containing the data to be transmitted. In the Linear mode this is the 32bit address of the first Tx Buffer Descriptor on the list. If the TBD POINTER is all 1s
it indicates that no TBD is used.
Contains the Destination Address of the frame. The least significant bit (MC) indicates the address type.
MC = 0: Individual Address.
MC

=

1: Multicast or Broadcast Address.

TCBCOUNT

- This 14-bit counter indicates the number of bytes that will be transmitted from the
Transmit Command Block, starting from the third byte after the TCB COUNT field
(address n+12 in the 32-bit Segmented mode, N+16 in the Linear mode). The
TCB COUNT field can be any number of bytes (including an odd byte), this allows
the user to transmit a frame with a header having an odd number of bytes. The
TCB COUNT field is not used in the 82586 mode.

EOF Bit

-

I

Indicates that the whole frame is kept in the Transmit Command Block. In the
Simplified memory model it must be always asserted.

1-101

82596CA

The interpretation of what is transmitted depends on the No Source Address insertion configuration bit and the
memory model being used.
NOTES:
1. The Destination Address and the Length Field are sequential. The Length Field immediately follows the
most significant byte of the Destination Address.
2. In case the 82596 is configured with No Source Address insertion bit equal to 0, the
configured Source Address in the transmitted frame.

8259~

inserts its

• In the 82586 mode, or when the Simplified memory model is used, the Destination and Length fields of the
transmitted frame are taken from the Transmit Command Block.
• If the FLEXIBLE memory model is used, the Destination and Length fields of the transmitted frame can be
found either in the TCB or TBD, depending on the TCB COUNT.
3. If the 82596 is configured with the Address/Length Field Location equal to 1, the 82596 does not insert its
configured Source Address in the transmitted frame. The first (2 x Address Length) + 2 bytes of the
transmitted frame are interpreted as Destination Address, Source Address, and Length fields respectively.
The location of the first transmitted byte depends on the operational mode of the 82596:
• In the 82586 mode, it is always the first byte of the first Tx Buffer.
• In both the 32-bit Segmented and Linear modes it depends on the SF bit and TCB COUNT:
- In the Simplified memory mode the first transmitted byte is always the third byte after the TCB COUNT
field.
-

In the Flexible mode, if the TCB COUNT is greater than 0 then it is the third byte after the TCB COUNT
field. If TCB COUNT equals 0 then it is first byte of the first Tx Buffer.

• Transmit frames shorter than six bytes are invalid. The transmission will be aborted (only in 82586 mode)
because of a DMA Underrun.
.
4. Frames which are aborted during transmission are jammed. Such an interruption of transmission can be
caused by any reason indicated by any of the status bits 8, 9, 10 and 12.

Jamming Rules
1. Jamming will not start before completion of preamble transmission.
2. Collisions detected during transmission of the last 11 bits will not result in jamming.
The format of a Transmit Buffer Descriptor is:
82586 Mode

ODD WORD
13
EVEN WORD
o
~__________
N_E_XT__
TB_D.-O_FF_S_E_T__________~__~~_________
SI_Z_E~(A_C_T_C_O_U_N_T~)________~O
~X__X
___X__X__X~X___X__X-L______~_________T_R_A_N_S_M_IT__B_U_FF_E_R_A_D_D_R_E_s_s________________~4
31

32·Bit Segmented Mode

ODD WORD
1615
13
EVEN WORD
o
r-__________N_E_XT__TB_D__O_FF_S_E_T__________-LE_O~F~O~_________S~IZ~E~~~C~T_C~O~U~N~T~)________~O
TRANSMIT BUFFER ADDRESS
4
31

~----------------------------------------------------------------------~

Linear Mode

31
0

ODD WORD
0

0

0

0

0

0

010

0

0

0

1615
13
o IEOFI 0 I
NEXT TBD ADDRESS
TRANSMIT BUFFER ADDRESS
0

00

EVEN WORD
SIZE (ACT COUNT)

o
o
4
8

Figure 31

1-102

I

82596CA

where:
EOF

-

SIZE (ACT COUNT)

-

This bit indicates that this TBD is the last one associated with the frame being
transmitted. It is set by the CPU before transmit.
This 14-bit quantity specifies the number of bytes that hold information for the
current buffer. It is set by the CPU before transmission.

NEXT TBD ADDRESS -

BUFFER ADDRESS

In the 82586 and 32-bit Segmented modes, it is the offset of the next TBD on the
list. In the Linear mode this is the 32-bit address of the next TBD on the list. It is
meaningless if EOF = 1.
- The starting address of the memory area that contains the data to be sent. In the
82586 mode, this is a 24-bit address (A31-A24 are considered to be zero). In the
32-bit Segmented and Linear modes this is a 32-bit address. This buffer can be
byte aligned for the 82596 B step.

TOR
This operation activates Time Domain Reflectomet, which is a mechanism to detect open or short circuits on
the link and their distance from the diagnosing station. The TOR command has no parameters. The TOR
transmit sequence was changed, compared to the 82586, to form a regular transmission. The TOR command
is designed to be used statically. Make sure that both the CU ano RU are idle before attempting a TOR
command. The TOR bit stream is as follows.
- Preamble
-

Source address

-

Another Source address (the TOR frame is transmitted back to. the sending station,
so DEST ADR = SRC ADR).

-

Data field containing 7Eh patterns.

-

Jam Pattern, which is the inverse CRC of the transmitted frame.

Maximum length of the TOR frame is 2048 bits. If the 82596 senses collision while transmitting the TOR frame
it transmits the jam pattern and stops the transmission. The 82596 then triggers an internal timer (STC); the
timer is reset at the beginning of transmission and reset if CRS is returned. The timer measures the time
elapsed from the start of transmission until an echo is returned. The echo is indicated by Collision Detect going
active or a drop in the Carrier Sense signal. The following table lists the possible cases that the 82596 is able
to analyze.
Conditions of TOR as Interpreted by the 82596
Transceiver Type
Condition

Ethernet

Non Ethernet

Carrier Sense was inactive for 2048-bit-time
periods

Short or Open on the
Transceiver Cable

NA

Carrier Sense signal dropped

Short on the Ethernet cable

NA

Collision Detect went active

Open on the Ethernet cable

Open on the Serial Link

The Carrier Sense Signal did not drop or the
Collision Detect did not go active within
2048-bit time period

No Problem

No Problem

An Ethernet transceiver is defined as one that returns transmitted data on the receive pair and activates the
Carrier Sense Signal while transmitting. A Non-Ethernet Transceiver is defined as one that does not do so.

I

1-103

intel®

82596CA

The format of the Time Domain Reflectometer command is:
~2586

31

and 32-Blt Segmented Modes

ODD WORD

EL

S

I

X

X

1615

X X X X X

LNK XVR ET
Errl X
OK PRS OPN SRT

I

31

ODD WORD

X X X 11

o

EVEN WORD

1 cis lOKI 0

TIME
(11 bits)

o

0

A15

0

0

0

0

0
0

o

0

0

0

LINK OFFSET

0
AO

Linear Mode
ELI S II 10

1615

0

0

0

0

0

0

0

0

011

0

o

0

o

0

0

0

0

o

A31
o

0

1 Ie

EVEN WORD
S lOKI 0

0

000

o

0
0

0

000

LINK ADDRESS
0

0

0

0

0

0

I I I I II
LNK
OK

XVR
PRS

ET
OPN

ET
SRT

X

0

0
AO

TIME
(11 bits)

Figure 32. TOR
where:
LINK ADDRESS,
EL, B, C, I, S

-

A

-

Bits 19-28
CMD (Bits 16-18)

-

Reserved (0 in the 32-bit Segmented and Linear Modes).

-

The TOR command. Value: Sh.

TIME

-

An 11-bit field that specifies the number of TxC cycles that elapsed before an echo
was observed. No echo is indicated by a reception consisting of "1s" only. Bec8usethe network contains various elements such as transceiver links, transceivers; Ethernet, repeaters etc., the TIME is not exactly proportional to the problems
distance.
.

As per 'standard Command Block (see the NOP command for details).
Indicates that the command was abnormally terminated due to CU Abort control
. command. If one, then the command was aborted, and if necessary it should be
repeated. If this bit is zero, the command was not aborted.

LNK OK (Bit 1S)

-

No link problem identified. TIME = 7FFh.

XCVR PRB (Bit 14)

-

Indicates a Transceiver problem. Carrier Sense was inactive for 2048-bit time period. LNK OK=O. TIME=7FFh.

ET OPN (Bit 13)

-

The transmission line is not properly terminated. Collision Detect went active and
LNK OK=O.

ET SRT (Bit 12)

-

There is a short circuit on the transmission line. Carrier Sense Signal dropp~d and
LNK OK=O.

1-104

I

82596CA

DUMP
This command causes the contents of various 82596 registers to be placed in a memory area specified by the
user. It is supplied as a 82596 self·diagnostic tool, and to provide registers of interest to the user. The format
of the DUMP command is:
82586 and 32-Bit Segmented Modes
31
IELI S II I X

ODD WORD
X

X

X

X

X

X

1615
X

X

X 11

1

BUFFER OFFSET

IA15

ole I B lOKI 0

EVEN WORD
0

0

0

0

0

0
0

0

0

0

0

0

LINK OFFSET

AoIA15

01
Aol

Linear Mode
31
ELI S II I X

ODD WORD
X

X

X

X

X

X

EVEN WORD

1615
X

X

X 11

1

ole I B lOKI 0

0

0

0

0

0

0
0

0

0

0

0

0

0

A31

LINK ADDRESS

AO

A31

BUFFER ADDRESS

AD

Figure 33. Dump

where:
LINK ADDRESS,
EL, B,C, 1,5

-

OK

-

Indicates error free completion.

Bits 19-28
CMD (Bits 16-18)

-

Reserved (0 in the 32·bit Segmented and Linear Modes).

-

The Dump command. Value: 6h.

BUFFER POINTER

As per standard Command Block (see the NOP cOmmand for details).

-In the 82586 and 32·bit Segmented modes this is the 16·bit·offset portion of the
dump area address. In the Linear mode this is the 32·bit linear address of the dump
area.

Dump Area Information Format

• The 82596 is not Dump compatible with the 82586 because of the 32·bit internal architecture. In 82586
. mode the 82596 will dump the same number of bytes as the 82586. The compatible data will be marked
with an asterisk.
• In 82586 mode the dump area is 170 bytes.
• The DUMP area format of the 32·bit Segmented and Linear modes is described in Figure 35.
• The size of the dump area of the 32·bit Segmented and Linear modes is 304 bytes.
• When the Dump is executed by the Port command an extra word will be appended to the Dump Area. The
extra word is a copy of the Dump Area status word (containing the C, B, and OK Bits). The C and OK Bits
are set when the 82596 has completed the Port Dump command.

I

1·105

82596CA

15 14 13 12 11

10

9

8

7

6

5

4

3

2

1

0

DMA CONTROL REGISTER

00

CONFIGURE BYTES' 3, 2
CONFIGURE BYTES' 5,4

02
04

CONFIGURE BYTES' 7, 6

06

CONFIGURE BYTES' 9,8

08

CONFIGURE BYTES' 10

OA

LA. BYTES I, 0'

OC

LA. BYTES 3, 2'
LA. BYTES 5, 4'

OE
10

LAST T.X. STATUS'

12

T.X. CRC BYTES I, 0'

14

T.X. CRC BYTES 3, 2'

16

R.x. CRC BYTES I, 0'

18

R.x. CRC BYTES 3, 2'

lA

R.x. TEMP MEMORY I, 0'

lC

R.x. TEMP MEMORY 3, 2'

IE

R.x. TEMP MEMORY 5, 4'

20

LAST RECEIVED STATUS'

22

HASH REGISTER BYTES I, 0'

24

HASH REGISTER BYTES 3, 2'

26

HASH REGISTER BYTES 5, 4'

28

HASH REGISTER BYTES 7, 6'

2A

SLOT TIME COUNTER'

2C

WAIT TIME COUNTER'

2E

MICRO MACHINE"

30

'The 82596 is not Dump compatible with
the 82586 because of the 32-bit internal architecture. In 82586 mode the 82596 will
dump the same number of bytes as the
82586.
"""These bytes are not user defined, results
may vary from Dump command to Dump
command.

.

-

I

REGISTER FILE
60 BYTES

6A

MICRO MACHINE LFSR"

6C

MICRO MACHINE"

6E

FLAG ARRAY
14 BYTES
QUEUE MEMORY"

7A
7C

CU PORT
8 BYTES

82

MICRO MACHINE ALU"

84

RESERVED"

86

M.M. TEMP A ROTATE R"

88

M.M. TEMPA"

8A

T.X. DMA BYTE COUNT"

8C

M.M. INPUT PORT ADDRESS"

8E

T.X. DMA ADDRESS

90

M.M. OUTPUT PORT"

92

R.x. DMA BYTE COUNT"

94

M.M. OUTPUT PORT ADDRESS REGISTER"

96

R. DMA ADDRESS"

98

RESERVED"

9A

BUS THROTILE TIMERS

9C

DIU CONTROL REGISTER"

9E

RESERVED"

AO

DMA CONTROL REGISTER"

A2
A4
A6
A8

BIU CONTROL REGISTER"
M.M. DISPATCHER .REG."
M.M. STATUS REGISTER"

Figure 34. Dump Area Format-82586 Mode

1-106

I

82596CA

31
CONFIGURE BYTES 5, 4, 3, 2

00

CONFIGURE BYTES 9, 8, 7, 6

04

CONFIGURE BYTES 13,12,11,10
I.A. BYTES 1, 0

X

X

X

X

08
X

X

X

I.A. BYTES 5, 2

X

OC
10

TX CRC BYTES 0, 1

LAST T.X. STATUS

14

RX CRC BYTES 0, 1

TX CRC BYTES 3, 2

18

RX TEMP MEMORY 1, 0

RX CRC BYTES 3, 2

R.x. TEMP MEMORY 5, 2
HASH REGISTERS 1, 0

LAST R.x. STATUS

HASH REGISTER BYTES 5, 2

1C
20
24
28

SLOT TIME COUNTER

HASH REGISTERS 7, 6

2C

RECEIVE FRAME LENGTH

WAIT-TIME COUNTER

30

MICRO MACHINE"

The 82596 is not Dump compatible with the
82586 because of the 32-bit internal architecture. In 82586 mode the 82596 will dump
the same number of bytes as the 82586.
"These bytes are not user defined, results
may vary from Dump command to Dump
command.

34

REGISTER FILE
128 BYTES

BO

MICRO MACHINE LFSR"

B4

MICRO MACHINE"

B8

FLAG ARRAY
28 BYTES
M.M. INPUT PORT"
16 BYTES

DO
D4

EO

MICRO MACHINE ALU"

E4

RESERVED"

E8

M.M. TEMP A ROTATE R."

EC

M.M. TEMP A"

FO

T.X. DMA BYTE COUNT"

F4

M.M. INPUT PORT ADDRESS REGISTER"

F8

T.X. DMA ADDRESS"

FC

M.M. OUTPUT PORT REGISTER"

100

R.x. DMA BYTE COUNT"

104

M.M. OUTPUT PORT ADDRESS REGISTER"

108

R.X. DMA ADDRESS REGISTER"

10C

RESERVED"

110

BUS THROTILE TIMERS

114

DIU CONTROL REGISTER"

118

RESERVED"

11C

DMA CONTROL REGISTER"

120

BIU CONTROL REGISTER"

124

M.M. DISPATCHER REG."

128

M.M. STATUS REGISTER"

12C

Figure 35. Dump Area Format-Linear and 32·Bit Segmented Mode

I

1-107

intel®

82596CA

Diagnose
The Diagnose Command triggers an internal self-test procedure that checks internal 82596 hardware, which
includes:
• Exponential Backoff Random Number Generator (Linear Feedback Shift Register).
• Exponential Backoff Timeout Counter.
• Slot Time Period Counter.
• Collision Number Counter.
• Exponential Backoff Shift Register.
• Exponential Backoff Mask Logic.
• Timer Trigger Logic.
This procedure checks the operation of the Backoff block, which resides in the serial side and is not easily
controlled. The Diagnose command is performed in two phases.
.
The format of the 82596 Diagnose command is:
82586 and 32-Bit Segmented Modes
1615

ODD WORD

x

X X X X X XX X X
X X X X X X X X X X

0

0

o

EVEN WORD

ODD WORD
000

EVEN WORD

C BOO 0 0 0 0 0 0 0 0
LINK OFFSET
AO

0

0

0

1

o

0

0

0

0

0

0

0

O· 0 0
AO

l7igure 36. Diagnose
where:
LINK ADDRESS,
EL, B, C, I, S

'- As per standard Command Block (see the NOP command for details):

Bits 19-28

-

Reserved (0 in the 32-bit Segmented and Linear Modes).

CMD (bits 16-18)

-

The Diagnose command. Value: 7h.

OK (bit 13)

-

Indicates error free completion.

F(bit11)

-

Indicates that the self-test procedure has failed.

1·108

I

82596CA

RECEIVE FRAME DESCRIPTOR
Each received frame is described by one Receive Frame Descriptor (see Figure 37). Two new memory
structures are available for the received frames. The structures are available only in the Linear and 32-bit
Segmented modes.

Simplified Memory Structure
The first is the Simplified memory structure, the data section of the received frame is part of the RFD and is
located immediately after the Length Field. Receive Buffer Descriptors are not used with the Simplified structure, it is primarily used to make programming easier. If the length of the data area described in the Size Field
is smaller than the incoming frame, the following happens.
1. The received frame is truncated.
2. The No Resource error counter is updated.
3. If the 82596 is configured to Save Bad Frames the'RFD is not reused; otherwise, the same RFD is used to
hold the next received frame, and the orily action taken regarding the truncated frame is to update the
counter.
4. The 82596 continues to receive the next frame in the next RFD.

L
;-

SCB

4

RECEIVE FRAME AREA

i"4

RFD 1

RFA
POINTER

STATUS

-

STATISTICS
TO
COMMAND
BLOCK
LIST

.

r--

VALID
PARAMETERS

RECEIVE
FRAME
DESCRIPTORS

l
RECEIVE
BUFFER
DESCRIPTORS

RBD2

-Lr

ACT-cnt

,

RECEIVE
BUFFERS

I ACT-cnt

1

,

~

VALID
DATA

VALID
DATA

BUFFER 1

-

I

- lr

J'----_

EMPTY

RBDl

01

-lJ

STATUS

I

BUFFER 2

-

-lJ

STATUS

EMPTY

EMPTY

e-

RBD3

01

RBD4

-Lr

ACT-cnt

,

-f

STATUS

01

RBD5

-Lr

ACT-cnt

,

01

f
,

ACT-cnt

~

J-

J-

-

'-----

'---

BUFFER 4

BUFFER 5

BUFFER 3

RECEIVE FRAME LIST

FREE FRAME LIST

290218-15

Figure 37. The Receive Frame Area

I

1-109

82596CA

Note that this sequence is very useful for monitoring. If the 82596 is configured to Save Bad Frames, to
receive in Promiscuous mode, and to use the Simplified memory structure, any programmed length of received
data. can be saved in memory.
The Simplified memory structure is shown in Figure 38.

SCB
STATUS
CBL
POINTER
RFA
POINTER

W

TO COIAIAAND LIST
~

~

FDl

FD2

STATUS

STATUS

STATISTICS
I
I
I

BUS
THROTILE

I

I
I
I

._---- - _.

I

RECEIVE
FRAIAE
DESCRIPTORS

I

VARIABLE
DATA
FIELD

'+-,I

~

RECEIVE FRAIAE AREA

RECEIVE FRAIAE LIST

I
I
I

I
I
~I~

,I

I
I
I

FD3

-~

EIAPTY

FD4

I

I

I

I

I
I
I
I
I
I
I

I

I

I
I
I

I

I
I
I
I
I
I
I

... _---_.

EIAPTY

I

I
I

I
I
I
I
I

. _----_ .

-u:

STATUS

I
I

I

EIAPTY

I

I
I
I
I

.. _--- ..
~

FREE FRAIAE LIST

I

,

290218-16

Figure 38. RFA Simplified Memory Structure

Flexible Memory Structure
The second structure is the Flexible memory structure, the data structure of the received frame is stored in
both the RFD and in a linked list of Receive Buffers-Receive Buffer Descriptors. The received frame is placed
in the RFD as configured in the Size field. Any remaining data is placed in a linked list of RBDs.
The Flexible memory structure is shown in Figure 39.

1·110

I

82596CA

SCB
STATUS

Lr

TO COMMAND LIST

4
FDI

RFA
POINTER

STATUS

-

1
1
1

CONTROL
FIELD

L
RECEIVE
BUFFER
DESCRIPTORS

1
1
1
1
1
1
1
1

VARIABLE
DATA
FIELD

RECEIVE
FRAME
DESCRIPTORS

RBDI

RBD2

-.J
T

RECEIVE
BUFFERS

I

-lLr

T

~

--B

~

i...--

i...--

BUFFER 1

BUFFER 2

EMPTY

I

~ :4

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

-Lh

STATUS

EMPTY

1
1
1
1
1
I·

1
1

1
1
1
1
1
1
1
1

EMPTY

1
1
1
1
1
1
1
1

._----_.

._----_ .

.. _----_ .

RBD3

RBD4

RBDS

-.J
T

VALID
DATA

,+--- RECEIVE FRAME LIST

FD4

STATUS

I

-

._-----_ ..

FD3

FD2

STATISTICS
1
BUS
1
1 THROTTLE

•

RECEIVE FRAM E AREA

CBl
POINTER

-Lr -lJ:

T

T

~

~

~

EMPTY

EMPTY

EMPTY

i...--

i...--

i...--

BUFFER 3

BUFFER 4

BUFFER S

~

FREE FRAME LIST

:

290218-17

Figure 39. RFA Flexible Memory Structure
Buffers on the receive side can be different lengths. The 82596 will not place more bytes into a buffer than
indicated in the associated RBD. The 82596 will fetch the next RBD before it is needed. The 82596 will
attempt to receive frames as long as the FBL is not exhausted. If there are no more buffers, the 82596
Receive Unit will enter the No Resources state. Before starting the RU, the CPU must place the FBL pointer in
the RBD pointer field of the first RFD. All remaining RBD pointer fields for subsequent RFDs should be "ls." If
. the Receive Frame Descriptor and the associated Receive Buffers are not reused (e.g., the frame is properly
received or the 82596 is configured to Save Bad Frames), the 82596 writes the address of the next free RBD
to the RBD pointer field of the next RFD.

Receive Buffer Descriptor (RBD)
The RBDs are used to store received data in a flexible set of linked buffers. The portion of the frame's data
field that is outside the RFD is placed in a set of buffers chained by a sequence of RBDs. The RFD points to
the first RBD, and the last RBD is flagged with an EOF bit set to 1. Each buffer in the linked list of buffers
related to a particular frame can b!3 any size up to 214 bytes but must be word aligned (begin on an even
numbered byte). This ensures optimum use of the memory resources while maintaining low overhead. All
buffers in a frame are filled with the received data except for the last, in which the actual count can be smaller
than the allocated buffer space.

I

1-111

82596CA

31

ODD WORD

ELI S I x

x

x

x

A15

x

x

x

x

1615
x

x

x

x

x

RBDOFFSET

C I B lOKI 0 I

x

AO A15

4th byte

EVEN WORD
STATUS BITS

0
10

o

LINK OFFSET

DESTINATION ADDRESS

0

o

0

o 0
AO 4

1st byte 8

1st byte 6th byte

SOURCE ADDRESS
6th byte

12

4th byte

X X X X X X X X X X X X X X X X

16
LENGTH FIELD

20

Figure 40. Recelve'Frame Descriptor-82586 Mode
31

ODD WORD

ELI S 10

000

A15

o

0

()

0

1615
0

olsFlo

0

RBDOFFSET

0

AO A15

SIZE

0101

EVEN WORD

LINK OFFSET

8
1st byte 12

DESTINATION ADDRESS

SOURCE ADDRESS

0
AO 4

ACTUAL COUNT

EOFI FI

4th byte

0

STATUS BITS

C I B lOKI

1st byte 6th byte

16

4th byte

20

6th byte

LENGTH FIELD

24

OPTIONAL DATA AREA

Figure 41. Receive Frame Descriptor-32-BitSegmented Mode
31

ODD WORD

ELI S 10

0

o

0

000

0

A31

o ISFI 0

0

0

6th byte

STATUS BITS

EOFI FI

0

AO 8
ACTUAL COUNT

DESTINATION ADDRESS
1st byte

0

A04

RECEIVE BUFFER DESCRIPTOR ADDRESS
SIZE

4th byte
SOURCE ADDRESS

EVEN WORD

C I B lOKI

LINK ADDRESS

A31
0101

1615
0

6th byte

12
1st byte 16
20

4th byte

24
LENGTH FIELD

28

OPTIONAL DATA AREA

Figure 42. Receive Frame Descriptor-Linear Mode

1-112

I

82596CA
where:
EL
S

-

SF

-

When set, this bit indicates that this RFD is the last one on the RDL.
When set, this bit suspends the RU after receiving the frame.
This bit selects between the Simplified or the Flexible mode.
0- Simplified mode, all the RX data is in the RFD. RBD ADDRESS field is all
"1 s."

1-

C
B

OK (bit 13)

STATUS

Flexible mode. Data is in the RFD and in a linked list of Receive Buffer Descriptors.
-This bit indicates the completion of frame reception. It is set by the 82596.
This bit indicates that the82596 is currently receiving this frame, or that the 82596
is ready to receive the frame. It is initially set to 0 by the CPU. The 82596 sets it to
1 when reception set up begins, and to 0 upon completion. The G and B bits are
set during the same operation.
- Frame received successfully, without errors. RFDs with bit 13 equal to 0 are possible only if the save bad frames, configuration option· is selected. Otherwise all
frames with errors will be discarded, although statistics will be collected on them.

-

-

The results of the Receive operation. Defined bits are,
Bit 12:
Bit 11:
Bit 10:

Length error if configured to check length
GRG error in an aligned frame
Alignment error (CRG error in misaligned frame)

Bit 9:

Ran out of buffer space-no resources

Bit 8:

DMA Overrun failure to acquire the system bus.

Bit 7:
Bit 6:

Frame too short.
No EOP flag (for Bit stuffing only)

Bit 5:

When the SF bit equals zero, and the 82596 is configured to save bad
frames, this bit signals that the receive frame was truncated. Otherwise it
is zero.

Bits 2-4: Zeros
Bit 1:
When it is zero, the destination address of the received frame matches
the IA address. When it is a 1, the destination address of the received
frame did not match the individual address. For example, a multicast
address or broadcast address will set this bit to a 1.
Bit 0:

Receive collision. A collision is detected during reception and the collision occurred after the destination address was received.
A 16-bit offset (32-bit address in the Linear mode) to the next Receive Frame
Descriptor. The Link Address of the last frame can be used to form a cyclical list.

LINK ADDRESS

-

RBDPOINTER

-

The offset (address in the Linear mode) of the first RBD containing the received
frame data. An RBD pointer of all ones indicates no RBD.

EOF

-

These fields are for the Simplified and Flexible memory models. They are exactly
the same as the respective fields in the Receive Buffer Descriptor. See the next
section for detailed explanation of their functions.

F
SIZE
ACT COUNT
MC
DESTINATION
ADDRESS
SOURCE ADDRESS

-

LENGTH FIELD

-

I

-

Multicast bit.

-

The contents of the destination address of the receive frame. The field is 0 to 6
bytes long.
The contents of the Source Address field of the received frame. It is 0 to 6 bytes
long.
The contents of this 2-byte field are user defined. In 802.3 it contains the length of
the data field. It is placed in memory in the same order it is received, i.e., most
significant byte first, least significant byte second.

1-113

intel®

82596CA

NOTES
1. The Destination address, Source address and Length fields are packed, i.e., one field immediately follows
the next.
2. The affect of Address/Length Location (No Source Address Insertion) configuration parameter while receiving is as follows:
- . 82586 Mode: The Destination address, Source address and Length field are not used, they are placed in
the RX data buffers.
-

32-Bit Segmented arid Linear Modes: when the Simplified memory model is used, the Destination address,
Source address and Length fields reside in their respective fields in the RFD. When the Flexible memory
strucrture is used the Destination address, Source address, and Length field locations depend on the SIZE
field of the RFD. They can be placed in the RFD, in the RX data buffers, or partially in the RFD and the rest
in the RX data buffers, depending on the SIZE field value.
.

82586 Mode
31

ODD WORD

A15

1615

NEXT RBD OFFSET

X

X

X

X

X

X

X

XIA23

X

X

X

X

X

X

X

X

X

EVEN WORD

.. RECEIVE BUFFER ADDRESS
X

X

X

X

X

X

o .

0

ACTuAL COUNT

AolEOFI F I

AO 4
8

SIZE

X I EL I X I

32-Bit Segmented Mode
31

ODD WORD

A15

1615

NEXT RBD OFFSET

A31

0

EVEN WORD

RECEIVE BUFFER ADDRESS

0

0

0

0

0

0

0

0

0

0

0

0

0

0

01 EL I

0
0

ACTUAL COUNT

AolEOFI F I

AO 4

pi

SIZE

8

Linear Mode
31

0

ODD WORD

0

0

0

0

0

0

0

0

0

1615

0

0

A31

0

0

EVEN WORD

OIEOFI FI

ACTUAL COUNT

NEXT RBD ADDRESS

A31

0

0

0

0

0

0

0

0

0

0

0

0

00

0

01 EL Ip I

0
AO 4

RECEIVE BUFFER ADDRESS

0

0

AO 8
SIZE

Figure 43. Receive Buffer Descriptor

1-114

I

82596CA

where:
EOF

-

Indicates that this is the last buffer related to the frame. It is cleared by the CPU
before starting the RU, and is written by the 82596 at the end of reception of the
frame.

F·

-

Indicates that this buffer has already been used. The Actual Count has no meaning
unless the F bit equals one. This bit is cleared by the CPU before starting the RU,
and is set by the 82596 after the associated buffer has been. This bit has the same
meaning as the Complete bit in the RFD and CB.

ACT COUNT

-

This 14-bit quantity indicates the number of meaningful bytes in the buffer. It is
cleared by the CPU before starting the RU, and is written by the 82596 after the
associated buffer has alr!;lady been used. In general, after the buffer is full, the
Actual Count value equals the size field of the same buffer. For the last buffer of
the frame, Actual Count can be less than the buffer size.

NEXT BD ADDRESS

-

The offset (absolute address in the Linear mode) of the next RBD on the list. It is
meaningless if EL = 1.
.

BUFFER ADDRESS

-

The starting address of the memory area that contains the received data. In the
82586 mode, this is a 24-bit address (with pins A24-A31 = 0). In the 32-bit Segmented and Linear modes this is a 32-bit address.

EL
P

-

Indicates that the buffer associate.d with this RBD is last in the FBL.

SIZE

I

-

This bit indicates that the 82596 has already prefetched the RBDs and any change
in the RBD data will be. ignored. This bit is valid only in the new 82596 memory
modes, and if this feature has been enabled during configure command. The
82596 Prefetches the RBDs in locked cycles; after prefetching the RBD the 82596
performs a write cycle where the P bit is set to one and"the rest of the data remains
unchanged, The CPU is responsible for resetting it in all RBDs. The 82596 will not
check this bit before setting it.
- This 14-bit quantity indicates the size, in bytes, of the associated buffer. This quantity must be an even number.

1-115

82596CA

PGA PACKAGE THERMAL
SPECIFICATION
Parameter

NOTICE: This is a production data sheet. The specifications are subject to change without notice .
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Thermal Resistance

9JC

3°C/W

9JA

24°C/W

ELECTRICAL AND TIMING
CHARACTERISTICS
Absolute Maximum Ratings
• Storage Temperature ........ - 65°C to + 150°C
• Case Temperature under Bias -65°C to :+ 110°C
• Supply Voltage
with Respect to Vss ......... -0.5V to + 6.5V
• Voltage on Other Pins .... -0.5V to Vcc + 0.5V

DC Characteristics
Tc = 0°C-85°C, vce = 5V ±10% LE/BE have MOS levels (see VMll, VMIH).
All other signals have TTL levels (see Vll, VIH, VOL, VOH).
Symbol

Parameter

Vil

Input Low Voltage (TTL)

VIH

Input High Voltage (TTL)

VMll

Input Low Voltage (MOS)

VMIH

Input High Voltage (MOS)

VOL

Output Low Voltage (TTL)

Min

Max

Units

-0.3

+0.8

V

2.0

Vec + 0.3

V

+0.8

V

. -0.3
3.7

Vec

+ 0.3

Notes

V

0.45

V

IOl

= 4.0 mA

IOH

= 0.9 mA-1 mA

VCll

RXC, TXC Input Low Voltage

-0.5

0.6

V

VCIH

RXC, TXC Input High Voltage

3.3

Vcc+ 0.5

V

VOH

Output High Voltage (TTL)

2.4

III

Input Leakage Current

±15

/J- A

0::;; VIN ::;; Vee

V

< VOUT < Vcc
= 1 MHz
FC = 1 MHz

ILO

Output Leakage Current

±15

/J- A

0.45

CIN

Capacitance of Input Buffer

10

pF

FC

COUT

Capacitance of Input/Output
Buffer

12

pF

CClK

CLK Capacitance

20

pF

FC

Icc

Power Supply

200

mA

At 25 MHz
Icc Typical

= 100 mA

Icc

Power Supply

300

mA

At 33 MHz
Icc Typical

= 150 mA

1-116

= 1 MHz

I

82596CA

AC Characteristics
82596CA C-STEP INPUT/OUTPUT SYSTEM TIMINGS
TC = O·C- + 85·C, Vcc = 5V ± 10%. These timing assume the CL on all outputs is 50 pF unless otherwise
specified. CL can be 20 pF to 120 pF however timings must be derated. All timing requirements are given in
nanoseconds.
Symbol

Parameter
Operating Frequency

16 MHz
Min

Max

12.5 MHz

16 MHz

62.5

80

Notes
1X ClK Input

T1

ClK Period

T1a

ClK Period Stability

T2

ClK High

20

2.0V

T3

ClK low

20

0.8V

T4

ClK Rise Time

8

0.8V to 2.0V

T5

ClK Fall Time

8

2.0V to 0.8V

0.1%

T6

BEn, lOCK, and A2-A31 Valid Delay

3

23

T6a

BLAST, PCHK Valid Delay

3

32

T7

BEn, lOCK, BLAST, A2-A31 Float Delay

3

39

T8

W/R and ADS Valid Delay

3

23

T9

W/R and ADS Float Delay

3

39

T10

00-031, DPn Write Data Valid Delay

3

27

1'11

00-031, DPn Write Data Float Delay

3

39
30

Adjacent ClK I::.

T12

HOLD Valid Delay

2

T13

CA and BREQ Setup Time

11

1,2

T14

CA and BREQ Hold Time

6

1,2

T15

BS16 Setup Time

12

2

T16

B816 Hold Time

5

2

T17

BRDY, ROY Setup Time

12

2

T18

BRDY, ROY Hold Time

5

2

T19

00-031, DPn READ Setup Time

10

2

T20

00-031, DPn READ Hold Time

6

2

T21

AHOlD and HlDA Setup Time

15

1,2
1,2

T22

AHOlD Hold Time

5

T22a

HlDA Hold Time

5

1,2

T23

RESET Setup Time

14

1,2

T24

RESET Hold Time

5

T25

INT/INT Valid Delay

1

T26

CA and BREQ, PORT Pulse Width

T27

00-031 CPU PORT Access Setup Time

1,2
23

2T1

1,2,3

10

2

T28

00-031 CPU PORT Access Hold Time

6

2

T29

PORT Setup Time

11

2

T30

PORT Hold Time

5

2

T31

BOFF Setup Time

12

2

T32

BOFF Hold Time

5

2

-Timings shown are for the 82596CA C-Stepping. For information regarding timings for the 82596CA A1 or B-Step, contact
your local Intel representative.

I

1-117

82596CA

AC Characteristics (Continued)
82596CA C-STEP INPUTIOUTPUT SYSTEM TIMINGS
T C = O·C- + 85·C, VCC = 5V ± 10%. These timing assume the CL on all outputs is 50 pF unless otherwise
specified. CL can be 20 pF to 120 pF however timings must be derated. All timing requirements are given in
nanoseconds.
Symbol

Parameter
Operating Frequency

T1

ClK Period

20 MHz
Min

Max

12.5 MHz

20 MHz

50

80
0.1%

Notes
1X ClK Input

T1a

ClK Period Stability

T2

ClK High

16

Adjacent ClK

T3

ClK low

16

T4

ClK Rise Time

T5

ClK Fall Time

T6

BEn, lOCK, and A2-A31 Valid Delay

3

T6a

BLAST, PCHK Valid Delay

3

25

T7

BEn; lOCK, BLAST, A2-A31 Float Delay

3

34

T8

W/R and ADS Valid Delay

3

20

T9

W/R and ADS Float Delay

3

34

T10

DO- D31, DPn Write Data Valid Delay

3

23

T11

DO - D31, DPn Write Data Float Delay

3

34

T12

HOLD Valid Delay

2

25

T13

CA and BREO Setup Time

10

1,2

T14

CA and BREO Hold Time

6

1,2

T15

BS16 Setup Time

12

2

T16

8S16 Hold Time

4

2

T17

BRDY, RDY Setup Time

12

2

T18

BRDY, RDY Hold Time

4

2

T19

DO-D31, DPn READ Setup Time

6

2

T20

DO- D31, DPn READ Hold Time

5

2

T21

AHOlD and HlDA Setup Time

15

1,2

T22

AHOlD Hold Time

4

1,2

T22a

HlDA Hold Time

5

1,2

T23

RESET Setup Time

12

1,2

T24

RESET Hold Time

4

T25

INTliNT Valid Delay

1

0.8V
6

0.8Vto 2.0V

6

2.0V to 0.8V

20

1,2
23
1,2,3

T26

CA and BREO, PORT Pulse Width

T27

DO-D31 CPU PORT Access Setup Time

6

2

T28

DO-D31 CPU PORT Access Hold Time

5

2

T29

PORT Setup Time

10

2

T30

PORT Hold Time

5

2

T31

BOFF Setup Time

12

2

T32

BOFF Hold Time

4

2

2T1

t:.

2.0V

'Timings shown are for the 82596CA C-Stepping. For information regarding timings for the 82596CA A1 or B-Step, contact
your local Intel representative.
1-118

I

82596CA

AC Characteristics (Continued)
82596CA C-STEP INPUTIOUTPUT SYSTEM TIMINGS
Tc = O·C- + 85·C, Vcc = 5V ± 10%. These timing assume the CL on all outputs is 50 pF unless otherwise
specified. CL can be 20 pF to 120 pF however timings must be derated. All timing requirements are given in
nanoseconds
Symbol

Parameter
Operating Frequency

T1

ClK Period

T1a

ClK Period Stability

25 MHz
Min

Max

12.5 MHz

25 MHz

40

80
0.1%

Notes
1X ClK Input
Adjacent ClK A

T2

ClK High

14

2.0V

T3

ClKlow

14

0.8V

T4

ClK Rise Time

4

0.8Vto 2.0V

T5

ClKFaliTime

4

2.0Vto 0.8V

T6

BEn Valid Delay

3

17

T6a

BLAST Valid Delay

3

20

T6b

lOCK Valid Delay

3

18

T6c

A2,.;A31 Valid Delay

3

18

T6d

PCHK Valid Delay

3

24

T7

BEn, lOCK, BLAST, A2-A31 Float Delay

3

30

T8

WIR and ADS Valid Delay

3

19

T9

WIR and ADS Float Delay

3

30

T10

DO-D31, DPn Write Data Valid Delay

3

20

T11

DO-D31, DPn Write Data Float Delay

3

30

T12

HOLD Valid Delay

3

19

T13

CA and BREO Setup Time

7

1,2

T14

CA and BREO Hold Time

3

1,2
2

T15

BS16 Setup Time

8

T16

BS16 Hold Time

3

2

T17

BRDY Setup Time

9

2

T17a

RDY Setup Time

8

2

T18

BRDY, RDY Hold Time

3

2
2

T19

DO-D31, DPn READ Setup Time

6

T20

DO-D31, DPn READ Hold Time

4.5

2

T21

AHOlD and HlDA Setup Time

10

1,2

T22

AHOlD Hold Time

3

1,2

T22a

HlDA Hold Time

3

1,2

T23

RESET Setup Time

10

1,2

T24

RESET Hold Time

3

T25

INTliNT Valid Delay

1

1,2
20

·Tlmlngs shown are for the 82596CA C-Stepplng. For Information regarding timings for the 82596CA A 1 or B-Step, contact
your local Intel representative.

I

1.-119

82596CA

AC Characteristics (Continued)

.

82596CA C-STEP INPUT/OUTPUT SYSTEM TIMINGS

o·c-

Tc =
+8SoC, Vcc = SV ± 10%. These timing assume the CL on all outputs is SOpF unless otherwise
specified. CL can be 20 pF to 120 pF however timings must be derated. All timing requirements are given in
nanoseconds.
Symbol

Parameter

25 MHz
Min

Max

Notes

T26

CA and BREQ, PORT Pulse Width

T27

00-031 CPU PORT Access Setup Time

6

2

T28

00-031 CPU PORT Access Hold Time

4.S

2

2T1

1,2,3

T29

PORT Setup Time

7

2

T30

PORT Hold Time

3

2

T31

BOFF Setup Time

10

2

T32

BOFF Hold Time

3

2

'Timings shown are for the B2596CA C-Stepping. For information regarding timings for the B2596CA A 1 or B-Step, contact
your local Intel representative.

1-120

I

82596CA

AC Characteristics (Continued)
82596CA C-STEP INPUT/OUTPUT SYSTEM TIMINGS
TC = O·C to + 85·C, Vcc = 5V ± 5%. These timing assume the CL on all outputs is 50 pF unless otherwise
specified. CL can be 20 pF to 120 pF, however timings must be derated. All timing requirements are given in
nanoseconds.
Symbol

Parameter
Operating Frequency

33 MHz
Min

Max

12.5 MHz

33 MHz

30

Notes
1X ClK Input

T1

ClK Period

T1a

ClK Period Stability

80

T2

ClK High

11

T3

ClK low

11

T4

ClK Rise Time

3

0.8Vt02.0V

T5

ClK Fall Time

3

2.0Vto 0.8V

0.1%

Adjacent elK 6.
2.0V
0.8V

T6

BEn Valid Delay

3

17

T6a

BLAST Valid Delay

3

20

T6b

lOCK Valid Delay

3

16

T6c

A2-A31 Valid Delay

3

18

T6d

PCHK Valid Delay

3

23

T7

BEn, lOCK, BLAST, A2-A31 Float Delay

3

20

T8

W/R and ADS Valid Delay

3

16

T9

W/R and ADS Float Delay

3

20

T10

00-031, DPn Write Data Valid Delay

3

19

T11

00-031, DPn Write

[iata Float Delay

3

20

T12

HOLD Valid Delay

3

19

T13

CA and BREQ Setup Time

7

1,2

T14

CA and BREQ Hold Time

3

1,2

T15

BS16 Setup Time

7

2

T16

BS16 Hold Time

3

2

T17

BRDY Setup Time

9

2

T17a

ROY Setup Time

8

2

T18

BROY, ROY Hold Time

3

2

T19

00-031, DPn READ Setup Time

6

2

T20

00-031, DPn READ Hold Time

4.5

2

T21

AHOlD Setup Time

10

1,2

T21a

HlOA Setup Time

8

1,2

T22

AHOlD Hold Time

3

1,2

·Timings shown are for the 82596CA C-Stepping. For information regarding timings for the 82596CA A1 or B-Step, contact
your local Intel representative.

I

1-121

82596CA

AC Characteristics (Continued)
82596CA C-STEP INPUT/OUTPUT SYSTEM TIMINGS
CL on all outputs is 50 pF unless otherwise specified.
All timing requirements are given in nanoseconds.
Symbol

33 MHz

Parameter

Min

Max

Notes

T22a

HLOA Hold Time

3

1,2

T23

RESET Setup Time

9

1,2

T24

RESET Hold Time

3

T25

INTliNT Valid Oelay

1

T26

CA and BREQ, PORT Pulse Width

2T1

1,2,3

T27

00-031 CPLrpORT Access Setup Time

6

2

T28

00-031 CPU PORT Access Hold Time

4.5

2

T29

PORT Setup Time

7

2

T30

.PORT Hold Time

3

2

T31

BOFF Setup Time

10

2

T32

BOFF Hold Time

3

2

..

1,2
20

NOTES:
·Timings shown are for the 82596CA C-stepping. For information regarding timings for the 82596CA A 1 or B-step, contact
your local Intel rep~esentative.
1. RESET, HLDA, and CA are internally synchronized. This timing is to guarantee recognition at next clock for RESET, HLDA
.
and CA.
2. All set-up, hold and delay timings are at maximum frequency specification Fmax, and must be derated according to the
following equation for operation at lower frequencies;
.
Tderated = (Fmax/Fopr) x T .
where:
Tderate = Specifies the value to derate the specification.
Frilax = Maximum operating frequency.
. Fopr = Actual operating frequency.
T = Specification at maximum frequency.
This calculation only provides a rough estimate for derating the frequency. For more detailed information, contact your
Intel Sales Office for the data sheet supplement.
3. CA pulse width need only be 1 T1 wide if the set up and hold times are met; BREQ must meet setup and hold times and
need only be 1 T1 wide.

TRANSMIT/RECEIVE CLOCK PARAMETERS
20 MHz

Parameter

Symbol

Min

Notes
Max

T36

TxCCycie

T38

TxC Rise Time

5

T39

TxCFaliTime

5

T40

TxC High Time

19

T41

TxCLowTime

18

T42

TxO Rise Time

10

T43

TxOFaliTime

10

T44

TxO Transition

T45

TxC Low to TxO Valid

25

4,6

T46

TxC Low to TxO Transition

25

2,4

T47

TxC High to TxOTransition

25

2,4

T48

TxC Low to TxO High (At End of Transition)

25

4

1-122

50

1,3
1
1
1,3
1,3

20

4
4
2,4

I

82596CA

TRANSMITIRECEIVE CLOCK PARAMETERS (Continued)
Symbol

20 MHz

Parameter
Min

Notes
Max

RTS AND CTS PARAMETERS
T49

TxC Low to RTS Low,
Time to Activate RTS

25

T50

CTS Low to TxC Low, CTS Setup Time

20

T51

TxC Low to CTS Invalid, CTS Hold Time

T52

TxC Low to RTS High

10

5

7
25

5

RECEIVE CLOCK PARAMETERS
T53

RXCCycle

50

1,3

T54

RXC Rise Time

5

1

T55 .

RXCFaliTime

5

1

T56

RXC High Time

19

1

T57

RXCLowTime

18

1

RECEIVED DATA PARAMETERS
T58

RXD Setup Time

20

6

T59

RXD Hold Time

10

6

T60

RXD Rise Time

10

T61

RXDFaliTime

10

CRS AND CDT PARAMETERS

I

T62

CDT Low to TXC HIGH
External Collision Detect Setup Time

20

T63

TXC High to CDT Inactive, CDT Hold Time

10

T64

CDT Low to Jam Start

T65

CRS Low to TXC High,
Carrier Sense Setup Time

20

T66

TXC High to CRS Inactive, CRS Hold Time
(Internal Collision Detect)

10

T67

CRS High to Jamming Start,

T68

Jamming Period

T69

CRS High to RXC High,
CRS Inactive Setup Time

30

T70

RXC High to CRS High,
CRS Inactive Hold Time

10

10

12
11

1-123

82596CA

TRANSMITIRECEIVE CLOCK PARAMETERS (Continued)
Symbol

I

Parameter

I
I

20 MHz

Min

I

Max

I
I

Notes

I

9

I
I

4

INTER FRAME SPACING PARAMETERS

T71

I

Interframe Delay

I

I

I
I

I'
I

EXTERNAL LOOPBACK-PIN PARAMETERS
T72
T73

I
I

TXC Low to LPBK Low
TXC Low to LPBK High

T36
T36

4

NOTES:
Special MOS levels. Veil = 0.9V and VelH = 3.0V.
Manchester only.
Manchester. Needs 50 % duty cycle.
1 TTL load + 50 pF ..
1 TTL load + 100 pF.
NRZ only.
Abnormal end of transmission-CTS expires before RTS.
Normal end to transmission.
Programmable value:
T71 = NIFS. T36
where: NIFS = the IFS configuration value
(if NIFS is less than 12 then NIFS is forced to 12).
10. Programmable value:
T64 = (NeDF. T36) + x. T36
(If the collision occurs after the preamble)
where:
NeDF = the collision detect filter configuration value,
and
x = 12,13,14, or15
11. T6B = 32. T36
12. Programmable value:
T67 = (NeSF. T36) + x. T36.
where: NeSF = the Carrier Sense Filter configuration
value, and
.
x = 12,13,14, or15
13. To guarantee recognition on the next clock.

1.
2.
3.
4.
5.
6.
7.
B.
9.

1-124

I

82596CA

82596CA BUS OPERATION
The following figures show the 82596CA basic bus cycle and basic burst cycle.

Please refer to the 32·8it LAN Component User's Manual.
IIDlE

T1

T2

T1

T2

T1

T2

T1

IIDlE

T2

ClK

W/R

\

/
I

1

I

I

I

I

I

I

\

/

,

I

I

I

I

I

I

I

I

I

I

I

I

I

I

ROY

BLAST

-

r=J
,

..............

I

CTJ' CTJ : CTJ : C
,
,

,

DATA - - - ' - - - - - - - - (

LJ

PCHK

READ

LJ

WRITE

READ

WRITE

290218':'40

Figure 44. Basic 82596CA Bus Cycle
IDLE

T1

T2

T2

T2

IIDlE

T2

ClK

w

ADS

,

A31;~~

,

-v-:-v--:-v-:--

-;...-'Xr----·-:

__

8EO-3

:

,
"

~

:

I

I

I

I'

I

I

I

I

I

I

I

I

ROY

BRDY

BLAST

Q..1

_ _........

,
,
DATA

\

c

--~--:---(

PCHK

290218-41

Figure 45. Basic 82596CA Burst Cycle

I

82596CA

SYSTEM INTERFACE A.C. TIMING CHARACTERISTICS
The measurements should be done at:
• Te = O°C to +B5°C, Vee = 5V ± 10%, C

=

50 pF unless otherwise specified.

• A.C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
• Timing measurements are made at 1.5V for both logic "1" and "0".
• Rise and Fall time of inputs and outputs signals are measured between O.BV
otherwise specified.
• All timings are relative to ClK crossing the 1.5V level.

~nd

2.0V respectively unless

• All A.C. parameters are valid only after 100 /Ls from power up.

2.4V
0.4SV

--v-:
----J'\::.

1.5V rest Point

~
~

290218-18

290218-19

Figure 46. ClK Timings
Two types of timing specifications are presented below:
1. Input Timing-minimum setup and hold times.
2. Output Timings-output delays and float times from ClK rising edge.
Figure 47 defines how the measurements should be done:

elK

1.5V

LEGEND:
Ts = Input Setup Time
Th = 'Input Hold Time
Tn = Minimum output delay or Mininum float delay
Tx = Maximum output delay or Maximum float delay

290218-20

Figure 47. Drive levels and Measurements Points for A.C. Specifications
Ts = T13, T15, T17, T19, T21, T23, T27, T29, T31
Th = T14, T16, T1B, T20, T22, T22a, T24, T2B, T30, T32
Tn = T6, T6a, T7, TB, T9, T10, T11, T12, T25
Tx = T6, T6a, T7, TB, T9, Ti0, T11, T12, T25

1-126

I

82596CA

INPUT WAVEFORMS

ClK
BREO
CA
290218-21

Figure 48. CA and BREQ Input Timing

290218-22

Figure 49.INT/INT Output Timing

eLK

L.JLJl..SU--U-U-UT121

HOLD

Flr-___-+-..._Tl~j'\1'-____
T21a

T22

T21--T22a~

E T31- -- T32:::J

Borr

AHOLO ~----------~X
HLOA

X~--290218-23

Figure 50. HOLD/HLDA Timings

eLK

031-00
OP3-0PO

290218-24

Figure 51. Input Setup and Hold Time

I

1-127

82596CA

T2

T1
CLK

A31-A2,BEn,
__
LOCK (T6)
PCHK, BLAST (T60)

WjR,

ADS

---.J

r-

-i~~:t;:j
MIN

VALID n

MAX

~

XXXXXX~ n+1

II
_.;..I_T_8......·I~IMAX

VALIOn~n+1

rTIO~MAX
DP3-DPO
031-00
(OUTPUT)

_ _ _ _.JXXXXXX~IO DATA
290218-25

Figure 52. Output Valid Delay Timing

CLK

T7

MIN
A31-A2, BEn
LOCK, BLAST
PCHK

MAX
FLOAT

VALID n

I

T9
MIN

MAX
FLOAT

W/R, ADS

VALID n
T11
MIN

DP3-0PO
031-00
(OUTPUT)

MAX
FLOAT

VALID n
290218-26

Figure 53. Output Float Delay Timing

CLK

PORT

00-031
290218-27

Figure 54. PORT Setup and Hold Time

1·128

I

82596CA

RESET
290218-28

Figure 55. RESET Input Timing
SERIAL AC TIMING CHARACTERISTICS

3.0V

0.9V

1-----T36
T53

I-T41
~.
T57

290218-29

Figure 56. Serial Input Clock Timing

TXC

RTS

cis

COT

CRS

TXO_V_ •• ·.!,6!.~t._ ..T!'!. •• .:,~I------T-6-7==L •••••••••••••••••••••• -••••••••••• __

(NRZ) _ . "... _______ ••" •• ______ ..'

~

290218-30

Figure 57. Transmit Data Waveforms

I

1·129

82596CA

TXC

RTS

CTS

CDT

T46

CRS

-- .",(.--- ·. v·- ----

TXD----.....;.-,
(NRZ)

T43

TXD---"\.H
(MANCHESTER)

.--- -.".- - - - -

t.-----.~......--------

.r.---\ T47

. T.::J'L

'---·I.·-----L~.

290218-31

Figure 58. Transmit Data Waveforms

5 ..

RXD _ _ _ _
T5_8

..J::.-T60 ,T61

-J
....

1 ____

290218-32

Figure 59. Receive Data Waveforms (NRZ)

290218-33

Figure 60. Receive Data Waveforms (CRS)

1-130

I

82596CA

OUTLINE DIAGRAMS
132 LEAD CERAMIC PIN GRID ARRAY PACKAGE INTEL TYPE A

~1'65FD~
SI~·UREF.

:::.[QJ
.......::::::1
:::

SEATING~
PLANE

•••• e •••••••• 0

• • • 0' • • • • 110.11 • •

.a..'

.. ---,

~

•••

oB

.::
:::~
••• •••••••• •••
••
\_--'

.L

I

••e e•••••••
e..
allee.saUD
SWAGGE

~:;~ REF.
dl~b
45° CHAMFER
(INDEX CORNER)

It
It

(ALL PINS)

t=~

0

I
-.l.

SWAGGED
PIN
DETAIL

6:~; REF.
45°(CHAt,1FER
3 PL)

mm (inch)
290218-34

Family: Ceramic Pin Grid Array Package
Millimeters

Symbol
Min

Max

A

3.56

4.57

A1

0.76

1.27

A2

2.67

3.43

Notes

Min

Max

0.140

0.180

Solid Lid

0.030

0.050

Solid Lid

Solid Lid

0.105

0.135

Solid Lid

Aa

1.14

1.40

0.045

0.055

B

0.43

0.51

0.017

0.020

D

36.45

37.21

1.435

1.465

D1

32.89

33.15

1.295

1.305

e1

2.29

2.79

0.090

0.110

L

2.54

3.30

0.100

0.130

132

N

S1
iSSUE

I

Inches

1.27
IWS

2.54

Notes

132
0.050

0.100

10/12/88

1-131

82596CA

Intel Case Outline Drawings
Plastic Quad Flat Pack (PQFP)
0.025 Inch (0.635mm) Pitch
Symbol

N

Description

Max

Min

Leadcount

Min

Max

84

68

Min

Max

100

Min

Max

132

Min

Max

164

Min

Max

196

A

Package Height

0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170

A1

Standoff

0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030

D,E

Terminal Dimension

0.675 0.685 0.775 0.785 0.875 0.885 1.075 1.085 1.275 1.285 1.475 1.485

D1, E1

Package Body

0.547 0.553 0.647 0.653 0.747 0.753 0.947 0.953 1.147 1.153 1.347 1.353

D2, E2

Bumper Distance

0.697 0.703 0.797 0.803 0.897 0.903 1.097 1.103 1.297 1.303 1.497 1.503

D3, E3

Lead Dimension

D4, E4

Foot Radius Location 0.623 0.637 0.723 0.737 0.823 0.837 1.023 1.037 1.223 1.237 1.423 1.437

0.400 REF

L1

Foot Length

Issue

IWS Preliminary 12/12/88

Symbol

N

Description

0.500 REF

0.600 REF

0.800 REF

1.000 REF

1.200 REF

0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030
INCH

Min

Leadcount

Max

Min

Max

84

68

Min

Max

100

Min

Max

132

Min

Max

164

Min

Max

196

A

Package Height

4.06

4.32

4.06

4.32

4.06

4.32

4.06

4.32

4.06

4.32

4.06

4.32

A1

Standoff

0.51

0.76

0.51

0.76

0.51

0.76

0.51

0.76

0.51

0.76

0.51

0.76

D,E

Terminal Dimension

17.15 17.40 19.69 19.94 22.23 22.48 27.31 27.56 32.39 32.64 37.47 37.72

D1, E1

Package Body

13.89 14.05 16.43 16.59 18.97 19.13 24.05 24.21 29.13 29.29 34.21 34.37

D2,E2

Bumper Distance

17.70 17.85 20.24 20.39 22.78 22.93 27.86 28.01 32.94 33.09 38.02 38.18

D3,E3

Lead Dimension

D4,E4

Foot Radius Location 15.82 16.17 18.36 18.71 21.25 21.25 25.89 26.33 31.06 31.41 36.14 36.49

L1

Foot Length

Issue

IWS Preliminary 12/12/88

1·132

10.16 REF

0.51

0.76

12.70 REF

0.51

0.76

15.24 REF

0.51

0.76

20.32 REF

0.51

0.76

25.40 REF

0.51

0.76

30.48 REF

0.51

0.76
mm

I

82596CA

mm (inch)

290218-35

Figure 61. Principal Dimensions and Dat!Jms

1I

r---02

1~ IlL25 <'.010')@ICIA®-B®10®1&
IJLI .0'0'2 MM/MM (IN/IN)IA-BI

t---01

1~ 10'.25 (.0'10')@ ICIA®-B® lo®l&
IJLI .0'0'2 MM/MM (IN/IN)IA-BI

t
3.81 (.150') MAX TYP

-~((

f

rSEE DETAIL M

-

~)
~1.91

(.0'75) MAX TYP

~10'.25 (.0'l0')@ICIA®-B®IO®1

JLI.0'0'2 MM/MM (IN/IN) 101

mm (inch)

~ 10'.25 (.0'10')@ ICIA®-B® lo®l&
JLI .0'0'2 MM/MM (IN/IN)lol
290218-36

Figure 62. Molded Details

I

1-133

intel®

82596CA

SEE DETAIL L.
L.t--++---SEE DETAIL J

~ D3/E3-----l
~---

D4/E4

---~

mm (inch)

290218-37

Figure 63. Terminal Details

I $ 1IiJ. 13

( .IH~5)@

Ie IA®-B® lo® lA
0.41 (.01b)
0.20 (.008)
0.20 (.008)
''--~'-0.14

0.31 (.012)-110.20 (.008)

_ .....
e---

(.0aS)

04/E4 -----1--1

8 OEG.
o OEG.
290218-38

mm (inch)
Detail L

Detail J
Figure 64. Typical Lead

1·134

I

82596CA

I

l.J2 (.052)
1.22 (.048)
~
0.90 (.0J5) MIN.

2.03 (.080)
1. 93 (. 07b)

2.0J (.080)
1.9J (.07b)
-~-- D2

----1

290218-39

mm (inch)
Figure 65. Detail M

REVISION SUMMARY
The following represents the key differences between version 004 and version 005 of the 82596CA
Data Sheet.
1. Timings added for -16 MHz and -20 MHz specfications.
The following represents the key differences between version 005 and version 006 of the 82596CA
Data Sheet.
1. A description of the 82596CA C-stepping enhancements was added and the 82596CA B-step
information was removed.
2. Description of BOFF pin changed. BOFF may be
asserted in T1 in the 82596 C-step.

I

3. Recommendation to use only one type of buffer
(either Simplified or Flexible) in any given linked
list.
4. Added detailed description regarding operation
or RCVCDT counter.
5. Added New Enhanced Big Endian Mode section.
The New Enhanced Big Endian Mode applies
only to the 82596 C-stepping.
6. Added programming recommendations regarding
RU and CU Start commands. These warn against
Starting the CU while it is Active and Starting the
RU while it is Ready.
7. Emphasized that the TOR command is a static
command and should not be used in an active
network.
8. Improved 82596CA C-step timings were added
for all speeds.

1-135

82596DX AND 82596SX
HIGH-PERFORMANCE 32-BIT LOCAL
AREA NETWORK COPROCESSOR
•

High-Performance 16-/32-Bit Bus
Master Interface
- 66-MB/s Bus Bandwidth
- 33-MHz Clock, Two Clocks Per
Transfer
~Bus Throttle Timers
-Transfers Data at 100% of Serial
Bandwidth
- 128-Byte Receive FIFO, 64-Byte
Transmit FIFO
III Network Management and Diagnostics
- Monitor Mode
- 32-Bit Statistical Counters

• Performs Complete CSMA/CD Medium
Access Control (MAC) Functions.
Independently of CPU
-IEEE 802.3 (EOC) Frame Delimiting
• Supports Industry Standard LANs
-IEEE TYPE 10BASE-T (TPE),
IEEE TYPE 10BASE5 (Ethernet*),
IEEE TYPE 10BASE2 (Cheapernet),
IEEE TYPE 1BASE5 (StarLAN),
and the Proposed Standard
TYPE 10BASE-F
- Proprietary CSMA/CD Networks Up
to 20 Mb/s
• On-Chip Memory Managem~nt
- Automatic Buffer Chaining
- Buffer Reclamation after Receipt of
Bad Frames; Optional Save Bad
Frames
.
- 32-Bit Segmented or Linear (Flat)
. Memory Addressing.Formats

• Self-Test Diagnostics
• Configurable Initialization Root for Data
Structures
..

• 82586 Software Compatible
Ii Optimized CPU Interface
- 82596DX Bus Interface Optimized to
Intel's 32-Bit i386TMDX
- 82596SX Bus Interface Optimized to
Intel's 16-Bit i386TMSX
- Supports Big Endlan and Little
Endian Byte Ordering
r -

I
I

-

-- -

--- -

----"': -- -

Seriol
Subsystem

--- -

•

High-Speed, 5-V, CHMOS** IV
Technology

•

132-Pin Plastic Quad Flat Pack (PQFP)
and PGA Package
(See Packaging Specifications Order Number: 240800·001,
Package Type KU and A)

1386TM is a trademark of Intel Corporation
• Ethernet is a registered trademark of Xerox Corporation.
··CHMOS is a patented process of Intel Corporation.
..

r-- -----.,

FIFO
Subsystem

LPBK I
RTS

I

ers

I

TxC

r- - - - - - - - -----.,

I I
I I

Parallel
Subsystem'

I 1

rf:"l
Tron:smit

Transmit

t.la:~~ne

... ::~~ne

l..!!J

I
I

I
Control

I LE/BE

I I

I
32-Blt DBus

Data

I PORT

T,D
Data Bus
CRS

Carrier

Sense
COT

Collision
Detect
Logic

Control

I

RxC

Address

I
I
I B t. Enable

---------------------

----------------~-----~

290219-1

Figure 1. 82596DX/SX Block Diagram

1·136

October 1995
Order Number: 290219-006

jj

fI

n+'61®
_I

82596DX/SX

82596DX and 82596SX High-Performance
32=Bit local Area Network Coprocessor
CONTENTS

PAGE

INTRODUCTION ....................... 1-138
PIN DESCRiPTIONS ................... 1-145

CONTENTS

PAGE
CBL Offset (Address) ................... 1-168
RFA Offset (Address) .................. 1-169

82596 AND HOST CPU
INTERACTION ...................... 1-149

SCB STATISTICAL COUNTERS ....... 1-169

82596 BUS INTERFACE .. ............. 1-149

ACTION COMMANDS AND
OPERATING MODES ........ : ....... 1-170
NOP ................................... 1-170

82596 MEMORY ADDRESSING ....... 1-149
82596 SYSTEM MEMORY
STRUCTURE ........................ 1-151
TRANSMIT AND RECEIVE MEMORY
STRUCTURES ...................... 1-152
TRANSMITTING FRAMES ............. 1-155
RECEIVING FRAMES ................. 1-156
82596 NETWORK MANAGEMENT AND
DIAGNOSTICS ...................... 1-156
NETWORK PLANNING AND
MAINTENANCE ..................... 1-158
STATION DIAGNOSTICS AND SELFTEST ................................ 1-159
82586 SOFTWARE COMPATIBILITY . . 1-159
INITIALIZING THE 82596 .............. 1-159
SYSTEM CONFIGURATION POINTER
(SCP) ................................ 1-159
Writing the Sysbus ..................... 1-160
INTERMEDIATE SYSTEM
CONFIGURATION POINTER
(ISCP) ............................... 1-161
INITIALIZATION PROCESS ........... 1-161
CONTROLLING THE 82596DX/SX .... 1-162
82596 CPU ACCESS INTERFACE
(PORT#) ............................ 1-162
MEMORY ADDRESSING FORMATS ... 1-163
LITTLE ENDIAN AND BIG EN DIAN
BYTE ORDERING ................... 1-163

Statistical Counter Operation ........... 1-169

Individual Address Setup ............... 1-171
Configure .............................. 1-172
Multicast-Setup ........................ 1-178
Transmit ............................... 1-179
Jamming Rules ......................... 1-181
TDR ................................... 1-182
Dump .................................. 1-184
Diagnose .............................. 1-187
RECEIVE FRAME DESCRiPTOR ...... 1-187
Simplified Memory Structure ............ 1-188
Flexible Memory Structure .............. 1-189
Receive Buffer Descriptor (RBD) .... 1-190
PGA PACKAGE THERMAL
SPECIFICATION .................... 1-195
ELECTRICAL AND TIMING
CHARACTERISTICS ................ 1-195
Absolute Maximum Ratings ............. 1-195
DC Characteristics ..................... 1-195
AC Characteristics .....................
82596DX Input/Output System
Timings ...........................
82596SX Input/Output System
Timings ...........................
Transmit/Receive Clock
Parameters .......................

1-196
1-196
1-198
1-201

82596DX/SX BUS OPERATION ....... 1-203
System Interlace A.C. Timing
Characteristics ....................... 1-204

COMMAND UNIT (CU) ................. 1-164

Input Waveforms ....................... 1-205

RECEIVE UNIT (RU) ................... 1-165

Serial A.C. Timing Characteristics ....... 1-207

SYSTEM CONTROL BLOCK (SCB) .... 1-165

OUTLINE DIAGRAMS ................. 1-209

SCB OFFSET ADDRESSES ........... 1-168

REVISION SUMMARy ................. 1-212

I

1-137

82596DX/SX

INTRODUCTION
The 82596DX/SX is an intelligent, high-performance
32-bit Local Area Network coprocessor. The
82596DX/SX implements the CSMAlCD access
method and can be configured to support all existing IEEE 802.3 standards-TYPEs 10BASE-T,
10BASE5, 10BASE2, 1BASE5, and 10BROAD36. It
can also be used to implement the proposed standard TYPE 10BASE-F. The 82596DX/SX performs
high-level commands, command chaining, and interprocessor communications via shared memory, thus
relieving the host CPU of many tasks associated
with network control. All time-critical functions are
performed independently of the CPU, this increases
network
performance
and
efficiency.
The
82596DX/SX bus interface is optimized for Intel's
i386™ DX and i386™ SX microprocessors.
The 82596DX/SX implements all IEEE 802.3 Medium Access Control and channel interface functions,
these include framing, preamble generation and
stripping, source address generation, destination address checking, short-frame detection, and automatic length-field handling. Data rates up to 20 Mb/s are
supported.
The 82596DX/SX provides a powerful host system
interface. It manages memory structures automatically, with command chaining and bidirectional data
chaining. An on-chip DMA controller manages four
channels, this allows autonomous transfer of data
blocks (buffers and frames) and relieves the CPU of
byte transfer overhead. Buffers containing errored or
collided frames can be automatically recovered without CPU intervention. The 82596DX/SX provides an
upgrade path for existing 82586 software drivers by
providing an 82586-software-compatible mode that
supports the current 82586 memory structure. The
82596DX/SX also has a Flexible memory structure
and a Simplified memory structure. The 82596DX/
SX can address up to 4 gigabytes of memory. The
82596DX/SX supports Little Endian and Big Endian
byte ordering.
The 82596DX/SX bus interface is optimized to Intel's i386™ DX and i386 SX microprocessors, providing a bus transfer rate of up to 66 MB/s at
33 MHz. The bus interface employs bus throttle timers to regulate 82596DX/SX bus use. Two large, independent FIFOs-128 bytes for Receive and 64
bytes for Transmit-tolerate long bus latencies and
provide programmable thresholds that allow the
user to optimize bus overhead for any worst-case
bus latency.
The 82596DX/SX provides a wide range of diagnostics and network management functions, these include internal and external loopback, exception condition tallies, channel activity indicators, optional
capture of all frames regardless of destination ad1-138

dress (promiscuous mode), optional capture of errored or collided frames, and time domain reflectometry for locating fault points on the network cable.
The statistical counters, in 32-bit segmented and linear modes, are 32-bits each and include CRC errors,
alignment errors, overrun· errors, resource errors,
short frames, and received collisions. The
82596DX/SX also features a monitor mode for network analysis. In this mode the 82596DX/SX can
capture status bytes, and update statistical counters, of frames monitored on the link without transferring the contents of the frames to memory. This
can be done concurrently while transmitting and receiving frames destined for that station.
The 82596DX/SX can be used in both baseband
and broadband networks. It can be configured for
maximum network efficiency (minimum contention
. overhead) with networks of any length. Its highly
flexible CSMAlCD unit supports address field
lengths of zero through six bytes for IEEE 802.3/
Ethernet frame delimitation. It also supports. 16- or
32-bit cyclic redundancy checks. The CRC can be
transferred directly to memory for receive, operations or dynamically inserted for transmit operations.
The CSMAlCD unit can also be configured for full
duplex operation for high throughput in point-to-point
connections.
The 82596 C-Step incorporates several new features not found in previous steppings. The following
is a summary of the 82596 C-step's new features.
• The 82596 C-step fixes Errata found in the A1
and B steppings.
• The 82596 C-step has improved AC timings over
both the A and B steppings.
• The 82596 C-step has a New Enhanced Big Endian Mode where in Linear Addressing mode, true
32-bit Big Endian functionality is achieved. New
Enhanced Big Endian Mode is enabled by setting
bit 7 of the SYSBUS byte. This mode.is software
compatible with the big endian mode of the Bstep with one exception-no 32-bit addresses
need to be swapped by software in the C-step. In
this new mode, the 82596 C-step treats 32-bit address pointers as true 32-bit entities and the SCB
absolute address and statistical counters are still
treated as two 16-bit big endian entities. Not setting this mode will configure the 82596 C-step to
be 100% compatible to the A1-step bit endian
mode.
• The 82596 C-step is hardware and software compatible to both the A 1 and B steppings allowing
for easy "drop-in" to current designs. Pinout and
control structures remain unchanged.
The 82596DX/SX is fabricated with Intel's reliable,
5-V, CHMOS IV (Process 648.8) technology. It is
available in a 132-pin PQFP or PGA package.

I

82596DX/SX

Vee
Vss
AID
All
A12
A13
A14
A15
A16
A17

Vss
Vee
AlB

Vee
A19

82596DX
(Top View)

A2D
A21
A22
A23
A24
A25

Vss
Vee
A26

Vss
A27
A2B
A29
A3D
A31

RESET

Vss
Vss

290219-2

Figure 2a. 82596DX PQFP Pin Configuration

I

1-139

intel®

82596DX/SX

Vss
vee
PORT

Vee
Vss
3

AID

All
A12

NC

A13

NC

A14
A15
A16
A17

Vss

Vee

11

Vss

Vss

Vee
A18

Vee

00

Vee
A19

01

02

A2D

82596SX

03

A21

04

A22

(Top View)

05

A23

06

A24

07

A25

Vee

Vss

Vss

Vee

Vss

A26

08
09

Vss
A27

010

A28

011

A29

012

A30·

013

A31

014

RESET

015
Vee

Vss
33 ... on ......
1"1

I"')

to')

...,

OX>

0>

0

pi)

...,

...

o ....

10

N

<

J")

...

co co co co

U')

ID

co

67

Vss

co

290219-34

Figure 2b. 82596SX PQFP Pin Configuration

1·140

I

82596DX/SX

A

D15

02

0
D18

03

0
020

04

0
D22

05

0
D26

06

07

08

09

10

12

13

14

o

o

o

D13

06

D5

o
o
o
o

o

o

o

o

D4

o

o

o

o

o

o

Yss

Vss

NC

Yee

8516

Ne

o

Ne

o
o

"PCRr

Ne

HOLD

NC

READY

INT/iNT

CA

o
o
o
o

o

o

o

D12

D9

D8

Vee

Vee

o

o

o

o

o

o

o
o

016

01"

D11

D1D

D7

D3

Dl

CLK2

NC

D21

D17

0204

019

o

o

DO

.02

o
o
o

LOCK

METAL LID

o

o o
o o
o o
/Ii
o o

W

0

0

o

o

o

o

Yee

023

HLOA.

Yee

Vss

0

0

0

Vss

Yee

025

82596DX

000
BED

(Pin View)

Vee

0

o

o

o

o

o

027

D28

BE2

Vee

Vss

0

o

o

o

o

D29

D31

D3D

A3

A2

Vee

RTS

o
o

A4

o
o

Vee

Vss

0

o
o

TxO

RxC

CTS

AS

A6

AS

0

0

LPBK

RxD

0

TxC

boo
A30

A28

A25

0

Vee

AU

A13

0

0

0

0

AlB

A16

A12

Al0

0

0

0

0

0

0

0

RESET

Yss

A29

Yee

A26

Yee

A

0

.4.19

0
A21

0

0

0

Vee

0
A23

COl

C'iiS

0

o
o
o
o

o

o

o

o

o

o

o

LE/iiE

A31

A27

Vss

A2-4

Vss

Vss

o

Vss

o

A22

o

Yss

o

A20

A9

o

.17

02

03

D4

05

06

07

Vss

Vss

0

01

BREa

Vss

Yss

11

C

o

08

D9

BE3

o
o
o

lD

11

12

A7

o

13

All

o

A15

'D

290219-3

Figure 3a. 82596DX PGA Pin View Side

I

1-141

82596DX/SX

82596DX PGA Cross Reference by Pill Name
Address

Data

Control

Serial
Interface

NIC

Vee

Vss

Pin No.

Pin No.

Signal

Pin No.

Signal

Pin No.

Signal

Pin No.

Signal

Pin No.

Pin No.

A2
A3
A4
A5
A6
A7
A8
A9
AlO
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31

N9
M9
M10
P11
N11
P12
M11
N12
M12
P13
L12
N13
M13
P14
K12
N14
J12
K13
M14
H12
K14
G12
F14
F12
F13
014
E12
013
012
C14

00
01
02
03
04
05
06
D7
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031

J2
H3
G2
G3
G1
01
C1
F3
02
C2
E3
03
B2
B1
C3
A1
B3
C4
A2
C5
A3
B4

AOS
BEO
BE1
BE2
BE3.
BREQ
BS16
CA
CLK2
HLOA
HOLO
INT/INT
LE/BE
LOCK
PORT
REAOY
RESET

M5
M7
P5
M8
P9
P4
N1
P3
J3
M6
P2
N3
B14
M4
.M2
M3
B13
N4

COT
CRS
CTS
LPBK
RTS
RxC
RxO
TxC
TxO

A13
A14
C11
A12
C10
B11
B12
C12
A11

K3
L1
L2
L3
N2
P1

1-142

W/R

B6
B7
B10
E2
E13
F2
G13
H2
H13
J13
K2
L13 .
M1
N6
N7
N8
N10

A6
A7
A8
A10
C13
E1
E14
F1
G14
H1
H14
J1
J14
K1
L14
N5
P6
P7
P8
P10

A4

C6
B5
C7
A5
B8
C8
A9
C9
B9

I

82596DX/SX

01

02

03

04

05

06

1'0

o

015

013

o

o

o

06

05

Vss

o

0

o

o

o

Ne

012

09

08

0

o

NC

NC

o

o

o

o

o

o

011

010

o

o

o

o

o

ot

o

o

o

00

o

o

o

Ne

PORT

Ne

HOLD

o

o

o

o

o

o

o

o

03

01

CLK2

Ne

Ne

READY

INT

CA

o

o

o

NC

NC

NC

LOCK

0

o

o

NC

NC

NC

0

o

08

0

0
Vee

METAL LID

o

0
Yss

09

10

11

12

13

o

o

w/A

o

02

03

04

BREo

o

o

o

ADS

Vee

'HE

o

o

o

HLOA

Vee

Vss

000
BlE

Ne

01

05

06

07

Vee

o

o

o

Al

Vee

Vss

08

0

o

o

o

o

o

NC

NC

NC

A3

A2

'ON

0

o

o

o

10

11

o

o

ATS

A4

09

0

o

o

o

o

o

TxD

RxC

CTS

AB

A6

AS

o

o

12

13

0

o

lPBK

RxD

0
COT

14

o

Ne

82596SX
(Pin View)

o

NC

o
HC

0

Vss

o

o

NC

07

o

NC

02

014

o

04

0
CRS

o

Txe

o

A30

o

A28

o

A25

o

o

o

o

o

RESET

Vss

A29

Vee

A26

o
LEIsE

o

o

A23

A21

o

o

Vee

o

o

o

o

o

A31

A27

Vss

A24

Yss

o

o

AI8

o

A16

o

AI2

o

AID

A9

A7

o

o

o

o

o

o

Vee

A19

Vee

AU

A13

All

o

o

o

o

o

o

Vss

A22

Vss

A20

AI7

A15

14

290219-35

Figure ab. 82596SX PGA Pin View Side

I

1-143

82596DX/SX

82596SX PGA Cross Reference by Pin Name
Address

Data

Control

Serial
Interface

N/C

Vee

Vss

Signal

Pin No.

Signal

Pin No.

Signal

Pin No.

Signal

Pin No.

Pin No.

Pin No.

Pin No.

A2
A3
A4
A5
A6
A7
As
A9
AlO
A11
A12
A13
A14
A15
A16
A17
A1S
A19
A20
A21
A22
A23
A24
A25
A26
A27
A2S
A29
A30
A31

N9
M9
M10
P11
N11
P12
M11
N12
M12
P13
L12
N13
M13
P14
K12
N14
J12
K13
M14
H12
K14
G12
F14
F12
F13
014
E12
013
012
C14

00
01
02
03
04
05
06
07
Os
09
010
011
012
013
0 14
015

J2
H3
G2
G3
G1
01
C1
F3
02
C2
E3
03
B2
B1
C3
A1

AOS
BLE
BHE
BON
BREQ
CA
CLK2
HLOA
HOLO
INT/INT
LE/BE
LOCK
PORT
ROY
RESET

M5
M7
P5
P9
P4
P3
J3
M6
P2
N3
B14
M4
M2
M3
B13
N04

COT
CRS
CTS
LP8K
RTS
RxC
RxO
TxC
TxO

A13
A14
C11
A12
C10
B11
B12
C12
A11

A2
A3

B6
B7
B10
E2
E13
F2
G13
H2
H13
J13
K2
L13
M1
N5
N6
N7
N8
N10

A6
A7
A8
A10
C13
E1
E14
F1
G14
H1
H14
J1
J14
K1
L14
N1
P6
P7
P8
P10

1·144

W/R

A4

A5
A9
83
B4
B5
B8
89
C4
C5
C6
C7
C8
C9
K3
L1
L2
L3
N2
P1

I

82596DX/SX

PIN DESCRIPTIONS
Symbol

CLK2

031-00

(015-00)

Type

9

I

14-53

I/O

Name and Function
CLOCK. The system clock input provides the fundamental timing for
the 82596. It is internally divided by two to generate the 82596 clock.
All external timing parameters are specified in reference to the rising
edge of CLK2. For clock levels see D.C. Characteristics.
DATA BUS. The 32 Data Bus lines are bidirectional, tri-state lines that
provide the general purpose data path between the 82596 and
memory. With the 82596DX the bus can be either 16 or 32 bits wide;
this is determined by the BS16 signal which is static. The 82596
always drives all 32 data lines during Write operations, even with a
16-bit bus. 00- 031 are floated after a Reset or when the bus is not
acquired.
These lines are inputs during a CPU Port access; in this mode the CPU
writes the next address to the 82596 through the Data lines. During
PORT commands (Relocatable SCP, Self-Test, and Dump) the
address must be aligned to a 16 byte boundary. This frees the 03-00
lines so they can be used to distinguish the commands. The following
is a summary of the decoding data.
DO

01

D2

D3

0
0
1
1

0
1
0
1

0
0
0
0

0
0
0
0

D4-D31

0000
. AD DR
ADDR
ADDR

Function

Reset
Relocatable SCP
Self-Test
Dump Command

14-32

I/O

These 16 Data Bus lines are bidirectional, tri-state lines that provide
the entire data path for the 82596SX. In the 82596SX 016-031 are
not connected (NC).

70-108

0

ADDRESS LINES. These 30 tri-stated Address lines output the
address bits required for memory operation. These lines are floated
after a Reset or when the bus is not acquired.

112

0

The 82596SX requires this additional address line to output the
address bits required for memory operation.

BE3-BEO

109-114

0

BYTE ENABLE. (825960X only.) These tri-stated signals are used to
indicate which bytes are involved with the current memory access. The
number of Byte Enable signals asserted indicates the physical size of
the data being transferred (1, 2, 3, or 4 bytes).
• BEO indicates 00-07
• BE1 indicates 08-015
• BE2 indicates 016- 023
• BE3 indicates 024-031
These lines are floated after a Reset or when the bus is not acquired.

BHE, BLE

113-114

0

(82596SX only.) These signals are the Byte High Enable and Byte Low
Enable signals for the 82596SX.

109

0

BUS ON. (82596SX only.) This signal is driven high when the 82596 is
holding the bus. This signal is tri-stated when the bus is relinquished.
BON has the same timing as the Byte Enables.

A31-A2

A1

BON

I

PQFP
Pin No.

1-145

82596DX/SX

PIN DESCRIPTIONS (Continued)
PQFP
PinNo.

Type

W/R

120

0

WRITE/READ. This dual-function pin is used to distinguish Write and
Read cycles. This line is floated after a Reset or when the bus is not
acquired.

AD8

124

0

ADDRESS STATUS. This tri-state pin is used by the 82596 to indicate
tha~a valid bus cycle has begun and that A31-A2, BE3-BEO, and
W/R are being driven. It is asserted during t1 bus states. This line is
floated after a Reset or when the bus is not acquired.

RDY

130

I

READY. Active low. This signal is the acknowledgment from
addressed memory that the transfer cycle can be completed. When
high, it causes wait states to be inserted. It is ignored at the end of the
first clock of the bus cycle's data cycle. This active-low signal does not
have an internal pull-up resistor. This signal must meet the setup and
hold times to operate correctly.

LOCK

126

0

LOCK. This tri-state pin is used to distinguish locked and unlocked bus
cycles. LOCK generates a semaphore handshake to the CPU. LOCK
can be active for several memory cycles, it goes active during the first
locked memory cycle (t1) and goes inactive at the last locked cycle
(t2). This line is floated after a Reset or when the bus is not acquired.
LOCK can be disabled via the sysbus by1e in software.

B816

129

I

BUS SIZE. This signal allows the 82596DX to work with either 16- or
32-bit by1es. This signal is static and should be tied high for 32-bit
operation or low for 16-bit operation. In Little Endian mode the DOD15 lines are driven when B816 is inserted, in Big Endian mode the
D16-D31 lines are driven.

HOLD

123

0

HOLD. The HOLD signal is active high, the 82596 uses it to request
local bus mastership. In normal operation HOLD goes inactive before
HLDA. The 82596 can be forced off the bus bydeasserting HLDA or if
the bus throttle timers expire.

HLDA

118

I

HOLD ACKNOWLEDGE. The HLDA signal is active high, it indicates
that bus mastership has been given to the 82596. HLDA is internally
synchronized; after HOLD is detected low, the CPU drives HLDA.low.
NOTE
Do not connect HLDA to Vcc-it will cause a deadlock. A user wanting
to give the 82596 permanent access to the bus should connect HLDA
to HOLD. If HLDA goes inactive before HOLD, the 82596 will release
the bus (by deasserting HOLD) within a specified number of system
clocks.

BREQ

115

I

BUS REQUEST. This signal, when configured to an externally
activated mode, is used to trigger the bus throttle timers.

Symbol

1·146

Name and Function

I

82596DX/SX

PIN DESCRIPTIONS (Continued)
PQFP
Pin No.

Type

Name and Function

PORT

3

I

PORT. When this signal is received, the 82596 latches the data on the
data bus into an internal 32-bit register. When the CPU is asserting this
signal it can write into the 82596 (via the data bus). This pin must be
activated twice during all CPU Port access commands.

RESET

69

I

RESET. This active high, internally synchronized signal causes the
82596 to terminate current activity. The signal must be high for at least
five system clock cycles. After five system clock cycles and four TxC
clock cycles the 82596 will execute a Reset when it receives a high
RESET signal. When RESET returns to low, the 82596 waits for the
first CA signal and then begins the initialization sequence.

LEIBE

65

I

LITTLE ENDIAN/BIG ENDIAN. This dual-function pin is used to
select byte ordering. When LEIBE is high, little endian byte ordering is
used; when low, big endian byte ordering is used for data in frames
(bytes) and for control (SCB, RFO, CBL, etc.).

CA

119

I

CHANNEL ATTENTION. The CPU uses this pin to force the 82596 to
begin executing memory resident Command blocks. The CA signal is
internally synchronized. The signal must be high for at least one
system clock. It is latched internally on the high to low edge and then
detected by the 82596.
The first CA after a Reset forces the 82596 into the initialization
sequence beginning at location OOFFFFF6h or an SCP address written
to the 82596 using CPU Port access. All subsequent CA signals cause
the 82596 to begin executing new command sequences from the SCB.

INT/INT

125

0

INTERRUPT. A high signal on this pin notifies the CPU that the 82596
is requesting an interrupt. This signal is an edge triggered interrupt
signal, and can be configured to be active high or low.

Symbol

Vee

18 Pins (OX)
19 Pins (SX)

POWER. +5V ±10%.

Vss

19 Pins
(OX and SX)

GROUND.OV:

TxO

54

0

TRANSMIT DATA. This pin transmits data to the serial link. It is high
when not transmitting.

TxC

64

I

TRANSMIT CLOCK. This signal provides the fundamental timing for
the serial subsystem. The clock is also used to transmit data
synchronously on the TxO pin. For NRZ encoding, data is transferred
to the TxD pin on the high to low clock transition. For Manchester
encoding, the transmitted bit center is aligned with the low to high
transition. Transmit clock should always be running for proper device
operation.

I

1-147

82596DX/SX

PIN DESCRIPTIONS (Continued)
PQFP
Pin No.

Type

Name and Function

LPBK

58

0

LOOPBACK. This TTL·level control signal enables the loopback
mode. In this mode serial data on the TxD input is routed through the
82C501 internal circuits and back to the RxD output without driving the
transceiver cable. To enable this signal, both internal and external
loopback need to be set with the Configure command.

RxD

60

I

RECEIVE DATA. This pin receives NRZ serial data only. It must be
high when not receiving.

RxC

59

I

RECEIVE CLOCK. This signal provides timing information to the
internal shifting logic. For NRZ data the state of the RxD pin is
sampled on the high to low transition of the clock.

RTS

57

0

REQUEST TO SEND. When this signal is low the 82596 informs the
external interface that it has data to transmit. It is forced high after a
Reset or when transmission is stopped.

CTS

62

I

CLEAR TO SEND. An active-low signal that enables the 82596 to
send data. It is normally used as an interface handshake to RTS.
Asserting CTS high stops transmission. CTS is internally synchronized.
If CTS goes inactive, meeting the setup time to the TxC negative edge,
the transmission will stop and RTS will go inactive within, at most, two
TxC cycles.

CRS

63

I

CARRIER SENSE. This signal is active low, it is used to notify the
82596 that traffic is on the serial link. It is only used if the 82596 is
configured for external Carrier Sense. In this configuration external
circuitry is required for detecting traffic on the serial link. CRS is
internally synchronized. To be accepted, the signal must remain active
for at least two serial clock cycles (for CRSF = 0).

CDT

61

I

; COLLISION DETECT. This active-low signal informs the 82596 that a
collision has occurred. It is only used if the 82596 is configured for
external Collision Detect. External circuitry is required for collision
detection. CDT is internally synchronized. To be accepted, the signal
must remain active for at least two serial clock cycles (for CDTF = 0).

Symbol

1-148

I

82596DX/SX

82596 AND HOST CPU INTERACTION

• The CPU can reset the 82596 via software without disturbing the rest of the system.

The 82596DX/SX and the host CPU communicate
through shared memory. Because of its on-chip
DMA capability, the 82596 can make data block
transfers (buffers and frames) independently of the
CPU; this greatly reduces the CPU byte transfer
overhead.

• A self-test can be used for board testing; the
82596 will execute a self-test and write the results to memory.

NOTE:

The 82596DX and 82596SX differ in their address
pin definitions and their data bus sizes. Information
in this data sheet applies to both versions unless
otherwise stated.
the 82596 is a multitasking coprocessor that comprises two independent logical units-the Command
Unit (CU) and the Receive Unit (RU). The CU executes commands from shared memory. The RU handles all activities related to frame reception. The independence of the CU and RU enables the 82596 to
engage in both activities simultaneously-the CU
can fetch and execute commands from memory
while the RU is storing received frames in memory.
The CPU is only involved with this process after the
CU has executed a sequence of commands or the
RU has finished storing a sequence of frames.
The CPU and the 82596 use the hardware signals
Interrupt (INT) and Channel Attention (CA) to initiate
communication with the System Control Block
(SCB), see Figure 4. The 82596 uses INT to alert the
CPU of a change in the contents of the SCB, the
CPU uses CA to alert the 82596.
The 82596 has a CPU Port Access state that allows
the CPU to execute certain functions without accessing memory. The 82596 PORT pin and data bus
pins are used to enable this feature. The CPU can
directly activate four operations when the 82596 is in
this state.
.
• Write an alternative System Configuration Pointer
(SCP). This can be used when the 82596 cannot
use the default SCP address space.
• Write a different Dump Command Pointer and execute Dump. This can be used for troubleshooting No Response problems.

82596 BUS INTERFACE
The 82596DX/SX has bus interface timings and pin
definitions that are compatible with Intel's 32-bit i386
DX and i386 SX micrQprocessors. This eliminates
the need for additional bus interface logic. Operating
at 33 MHz, the 82596's bus bandwidth can be as
high as 66 MB/s. Since Ethernet only requires
1.25 MB/s, this leaves a considerable amount of
bandwidth for the CPU. The 82596 also has a bus
throttle to regulate its use of the bus. Two timers can
be programmed through the SCB: one controls the
maximum time the 82596 can remain on the bus, the
other controls the time the 82596.must stay off the
bus (see Figure 5). The bus throttle can be programmed to trigger internally with HLDA or externally with BREQ. These timers.can restrict the 82596
HOLD activation time and improve bus utilization.

82596 I\IIEMORY ADDRESSING
.

I

The 82596 has a 32-bit memory address range,
which allows addressing up to four gigabytes of
memory. The 82596 has three memory addressing
modes (see Table 1).
• 82586 Mode. The 82596 has a 24-bit memory
address range. The System Control Block, Command List, Receive Descriptor List, and Buffer
Descriptors must reside in one 64-kB memory
segment. Transmit and Receive buffers can reside in a 24-bit address space.
• 32-Bit Segmented Mode. The 82596 has a 32bit memory address range. The System Control
Block, Command List, Receive Descriptor List,
and Buffer Descriptors must reside in one 64-kB
memory segment. Transmit and Receive buffers
can reside in a 32-bit address space.
• Linear Mode. The 82596 has a 32-bit memory
address range. Any memory structure can reside
anywhere within the 32-bit memory address
range.

1-149

82596DX/SX

I

CHANNEL AnENTION

.1

CPU
INT

"

CA
1 82596
" ~

INTERRUPT

~

I

SHARED MEMORY
INITIALIZATION
ROOT

•

SYSTEM CONTROL
BLOCK (SCB)
"MAILBOX"

II.
I'

'"

A

'"

RECEIVE
FRAME
AREA

COMMAND
LIST

290219-4

Figure 4. 82596 and Host CPU Intervention

r--

82596 Bus Use
without Bus
Throttle Timers

I

82596 Bus Use
with Bus Throttle

I

I

I

t1 - - - I '

T-ON

I

T-DFF

~

Timers

t1 =t2+t3

290219-5

Figure 5. Bus Throttle Timers
Table 1.82596 Memory Addressing Formats
Operation Mode
Pointer or Offset

82586

ISCP ADDRESS

24-Bit Linear

SCBADDRESS

Base (24)

Command Block Pointers

Base (24)

Rx Frame Descriptors

Base (24)

Tx Frame Descriptors

Base (24)

+ Offset(16)
+ Offset (16)
+ Offset (16)
+ Offset (16)
+ Offset (16)
+ Offset (16)

32-Bit
Segmented

Linear

32-Bit Linear

32-Bit Linear

Base (32)

+ Offset (16)
+ Offset (16)
Base (32) + Offset (16)
Base (32) + Offset (16)
Base (32) + Offset (16)
Base (32) + Offset (16)

32-Bit Linear

Base (32)

32-Bit Linear
32-Bit Linear
32-Bit Linear
32-Bit Linear

Rx Buffer Descriptors

Base (24)

Tx Buffer Descriptors

Base (24)

Rx Buffers

24-Bit Linear

32-Bit Linear

32-Bit Linear

Tx Buffers

24-Bit Linear

32-Bit Linear

32-Bit Linear

1-150

32-Bit Linear

I

82596DX/SX

INITIALIZATION ROOT

COMMAND lIST (Cl)

-----------------------------------CO~~~:~~IST I-_+-~I
RECEIVE FRAME
POINTER

L..._ _ _.J(N)

STATISTICS
I
I

BUS

DESCRIPTOR

._------- ..
I

I

El=1
TRANSMIT
BUFFER

TRANSMIT
BUFFER
THROTIlE

(TBD)

I

T
-------------------------,----------~~
RECEIVE FRAME AREA (RFA)

...........,_--1

L..._ _ _..I(N)

(I)

El=1
RECEIVE
BUFFER
DESCRIPTOR
(RBD)
L..._.,...._.J (N)

RECEIVE
BUFFER
DESCRIPTOR
(RBD)

I.
I

T

T T

T T

T

I

I

--------------------------------------------~

290219-6

Figure 6. 82596 Shared Memory Structure

82596 SYSTEM MEMORY
STRUCTURE
The Shared Memory structure consists of four parts:
the Initialization Root, the System Control Block, the
Command List, and the Receive Frame Area (see
Figure 6).
The Initialization Root is in an established location
known to the host CPU and the 82596 (OOFFFFF6h).
However, the CPU can establish the Initialization
Root in another location by using the CPU Port access. This root is accessed during initialization, and
points to the System Control Block.

I

The System Control Block serves as a bidirectional
mail drop for the host CPU and the 82596 CU and
RU. It is the central point through which the CPU and
the 82596 exchange control and status information.
The SCB has two areas. The first contains instructions from the CPU to the 82596. These include:
control of the CU and RU (Start, Abort, Suspend,
and Resume), a pointer to the list of CU comm~nds,
a pointer to the Receive Frame Area, a set of Interrupt Acknowledge bits, and the T·ON and T-OFF
timers for the bus throttle. The second area contains
status information the 82596 is sending to the CPU.
Such as, the CU and RU states (Idle, Active

1·151

82596DX/SX

Ready, Suspended, No Receive Resources, etc.), interrupt bits (Command Completed, Frame Received,
CU Not Ready, and RU Not Ready), and statistical
counters.
The Command List functions as a program for the
CU; individual commands are placed in memory
units called Command Blocks (CBs). These CBs
contain the parameters and status of specific highlevel commands called Action Commands; e.g.,
Transmit or Configure.
Transmit causes the 82596 to transmit a frame. The
Transmit CB contains the destination address, the
length field, and a pointer to a list of linked buffers
holding the frame that is to be constructed from several buffers scattered throughout memory. The
Command Unit operates without CPU intervention·
the DMA for each buffer, and the prefetching of ref~
erences to new buffers, is performed in parallel. The
CPU is notified only after a transmission is complete.
The Receive Frame Area is a list of Free Frame Descriptors (descriptors not yet used) and a list of userprepared buffers. Frames arrive at the 82596 unsolicited; the 82596 must always be ready to receive
and store them in the Free Frame Area. The Receive Unit fills the buffers when it receives frames,
and reformats the Free Buffer List into receivedframe structures. The frame structure is, for all practical purposes, identical to the format of the frame to
be transmitted. The first Frame descriptor is referenced by the SCB. Unless the 82596 is configured
to Save Bad Frames, the frame descriptor, and the
associated buffer descriptor, which is wasted when
a bad frame is received, are automatically reclaimed
and returned to the Free Buffer List.
Receive buffer chaining (storing incoming frames in
a linked buffer list) significantly improves memory
utilization. Without buffer chaining, the user must allocate consecutive blocks of memory, each capable
of containing a maximum frame (for Ethernet, 1518
bytes). Since an average frame is about 200 bytes,
this is very inefficient. With buffer chaining, the user
can allocate small buffers and the 82596 will only
use those that are needed.
Figure 7 A-D illustrates how the 82596 uses the
Receive Frame Area. Figure 7A shows an unused
Receive Frame Area composed of Free Frame Descriptors and Free Receive Buffers prepared by the
user. The SCB points to the first Frame Descriptor of
the Frame Descriptor List. Figure 7B shows the
same Receive Frame Area after receiving one
frame. This first frame occupies two Receive Buffers
and one Frame Descriptor-a valid received frame

1-152

will only occupy one Frame Descriptor. After receiving this frame the 82596 sets the next Free Frame
Descriptor RBD pointer to the next Free RBD. Figure
7C shows the RFA after receiving a second frame.
In this example the second frame occupies only one
Receive Buffer and one RFD. The 82596 again sets
the RBD pointer. This process is repeated again in
Figure 70, showing the reception of another frame
using one Receive Buffer; in this example there is an
extra Frame Descriptor.

TRANSMIT AND RECEIVE MEMORY
STRUCTURES
There are three memory structures for reception and
transmission. The 82586 memory structure, the
Flexible memory structure, and the Simplified memory.structure. The 82586 mode is selected by configunng the 82596 during initialization. In this mode all
the 82596 memory structures are compatible with
the 82586 memory structures.
When the 82596 is not configured to the 82586
. mode, the other two memory structures, Simplified
and Flexible, are available for transmitting and receiving. These structures are selected by setting the
S/F bit in the Transmit Command and/or the Receive Frame Descriptor (see Figures 29, 30, 41, and
42). It is recommended that any linked list of buffers
be relegated to a single type-either simplified or
flexible. The Simplified memory structure offers a
simple structure for ease of programming (see Figure 8). All information about a frame is contained in
one structure; for example, during reception the RFD
and data field are contained in one structure.
The Flexible memory structure (see Figure 9) has a
control field that allows the programmer to specify
the amount of receive data the RFD will contain for
receive operations and the amount of transmit data
the Transmit Command Block will contain for transmit operations. For example, when the control field
in the RFD is set to 20 bytes during a reception, the
first 20 bytes of the data field are stored in the RFD
(6 Bytes of Destination Address, 6 Bytes of Source
Address, 2 Bytes of Length Field, and 6 Bytes of
Data), and the remainder of the data field is stored in
the Receive Data Buffers. This is useful for capturing
frame headers when header information is contained in the data field. The header information can
then be automatically stored in the RFD partitioned
from the Receive Data Buffer.
The control field can also be used for the Transmit
Command when the Flexible memory structure is
used. The quantity of data field bytes to be transmitted from the Transmit Command Block is specified
by the variable control field.

I

82596DX/SX

·• ·•.• • .f*~~··j •.• • .·•·• ·

290219-7

Figure 7. Frame Reception in the RFA

I

1-153

82596DX/SX

SCB
STATUS

TO COMMAND LIST

14

I

FD
POINTER

FD1

FD2

STATUS

FD3
STATUS

STATUS

EMPTY

EMPTY

EMPTY

••
-----_.•
VARIABLE
DATA
FIELD
RECEIVE
FRAME
DESCRIPTORS

.. -

~ RECEIVE FRAME LIST

,I

-It:

STATUS

BUS
THROTTLE

..

FD4

-lJ

-Lr

I

STATISTICS

•••

••

RECEIVE FRAME AREA

.,

FREE FRAME LIST

,I

,

290219-8

Figure 8. Simplified Memory Structure.

SCB

TO COMMAND LIST

STATUS

-4

FD
POINTER

I

FD2

STATUS

RBD1

EMPTY

RBD3

RBD4

RBD5

T

T

T

-lJ -T -lJ -r -Lr:

T

~

T

l

DATA
FIELD

RECEIVE
BUFFERS

-Lt:

EMPTY

L

RBD2

-r

EMPTY

r-

VARIABLE
DATA
FIELD

L

lJ

I

FD4
STATUS

CONTROL
rJELD

RECEIVE
FRAME
DESCRIPTORS

FD3

STATUS,

t--

BUS
•• THROTTLE
••
•
•
._-----_.

--

STATUS

I

-

STATISTICS

RECEIVE
BUFFER
DESCRIPTORS

~

RECEIVE FRAME AREA
FD1

----

BUFFER 1

l
DATA
rJELD

-

BUFFER 2

,+--- RECEIVE FRAME LIST

l
EMPTY

I

----

BUFFER 3

••...;..-------

----I.~':

l
EMPTY

-

BUFFER 4

EMPTY

----

BUFFER 5

FREE FRAME LIST - - - - - - - -••:

290219-9

Figure 9. Flexible Memory Structure

1·154

I

82596DX/SX

TRANSMITTING FRAMES
The 82596 executes high-level Action Commands
from the Command List in system memory. Action
Commands are fetched and executed in parallel with
the host CPU operation, thereby significantly improving system performance. The format of the Action
Commands is shown in Figure 10. Figure 28 shows
the 82586 mode, and Figures 29 and 30 shows the
command formats of the Linear and 32-bit Segmented modes.
A single Transmit command contains, as part of the
command-specific parameters, the destination address and length field of the transmitted frame and a
pOinter to buffer area in memory containing the data
portion of the frame. The data field is contained in a
memory data structure consisting of a buffer descriptor (BO) and a data buffer-or a linked list of
buffer descriptors and buffers-as shown in Figure
11.
Multiple data buffers can be chained together using
the BOs. Thus, a frame with a long data field can be
transmitted using several (shorter) data buffers
chained together. This chaining technique allows the
system designer to develop efficient buffer management.
The 82596 automatically generates the preamble
(alternating 1s and Os) and start frame delimiter,
fetches the destination address and length field from
the Transmit command, inserts its unique address
as the source address, fetches the data field specified by the Transmit command, and computes and
appends the CRC to the end of the frame (see Figure 12). In the Linear and 32-bit Segmented mode
the CRC can be optionally inserted on a frame-byframe basis by setting the NC bit in the Transmit
Command Block (see Figures 29 and 30).
The 82596 generates the standard End Of Carrier
(EOG) start and end frame delimiters. In EOC, the

I

start frame delimiter is 10101011 and the end frame
delimiter is indicated by the lack of a signal after the
last bit of the frame check sequence field has been
transmitted. In EOC, the 82596 can be configured to
extend short frames by adding pad bytes (7Eh) during transmission, according to the length field.
When a collision occurs, the 82596 manages the
jam, random wait, and retry processes, reinitializing
OMA pointers without CPU intervention. Multiple
frames can be sent by linking the appropriate number of Transmit commands together. This is particularly useful when transmitting a message larger than
the maximum frame size (1518 bytes for Ethernet).

CONTROL
FIELDS

I COMMAND STATUS
I COMMAND

LINK FIELD
•
(POINTER TO NEXT COMMAND)

NEXT
f-+ COMMAND

PARAMETER FIELD
(COMMAND-SPECIFIC
PARAMETERS)
290219-10

Figure 10_ Action Command Format

TRANSMIT BD
ACTUAL COUNT
LINK FIELD

•

DB ADDRESS.
(24 BITS)

~ NEXT BUFFER DES CRIPTOR

~

DATA
BUFFER
(DB)
290219-11

Figure 11_ Data Buffer Descriptor and
Data Buffer Structure

1-155

intel®

82596DX/SX

PREAMBLE

START
FRAME
DELIMITER

DESTINATION
ADDRESS

SOURCE
ADDRESS

LENGTH
FIELD

DATA
FIELD

FRAME
CHECK
SEQUENCE

END
FRAME
DELIMITER

Figure 12. Frame Format

RECEIVING FRAMES
To reduce CPU overhead, the 82596 is designed to
receive frames without CPU supervision. The host
CPU first sets aside an adequate receive buffer
space and then enables the 82596 Receive Unit.
Once enabled, the RU watches for arriving frames
and automatically stores them in the Receive Frame
Area (RFA). The RFA contains Receive Frame Descriptors, Receive Buffer Descriptors, and Data Buff"
ers (see Figure 13). The individual Receive Frame
Descriptors make up a Receive. Descriptor· List
(RDL) used by the 82596 to store the destination
and source addresses, the length field, and the
status of each frame received (see Figure 14).
Once enabled, the 82596 checks each passing
frame for an address match. The 82596 will recognize its own unique address, one or more multicast
addresses, or the broadcast address. If a match is
found the 82596 stores the destination and source
addresses and the length field in the next available
RFD. It then begins filling the next available Data
Buffer on the FBL, which is pointed to by the current
RFD, with the data portion of the incoming frame. As
one Data Buffer is filled, the 82596 automatically
fetches the next DB on the FBL until the entire frame
is received. This buffer chaining technique is particularly memory efficient because it allows the system
designer to set aside buffers to fit frames much
shorter than the maximum allowable frame length. If
AL·LOC = 1, or if the flexible memory structure is
used, the addresses and length fierd can be placed
in the receive buffer.
Once the entire frame is received without error, the
82596 does the following housekeeping tasks.
• The actual count field of the last Buffer Descrip·
tor used to hold the frame just received is updated with the number of bytes stored in the associated Data Buffer.
• The next available Receive Frame Descriptor is
fetched.
• The address of the next available Buffer Descriptor is written to the next available Receive Frame
Descriptor.
• A frame received interrupt status bit is posted in
the SCB.
• An interrupt is sent to the CPU.
If a frame error occurs, for example a CRC error, the
82596 automatically reinitializes its DMA pointers
and reclaims any data buffers containing the bad
1·156

frame. The 82596 will continue to receive frames
without CPU help as long as Receive Frame Descriptors and Data Buffers are available.

82596 NETWORK MANAGEMENT
AND DIAGNOSTICS
The behavior of data communication networks is
normally very complex because of their distributed
and asynchronous nature. It is particularly difficult to
pinpoint a failure when it occurs. The 82596 has extensive diagnostic and network management functions that help improve reliability and testability. The
82596 reports on the following events after each
frame is transmitted.
• Transmission successful.
• Transmission unsuccessful. Lost Carrier Sense.
• Transmission unsuccessful. Lost Clear to Send.
• Transmission unsuccessful. A DMA underrun occurred because the system bus did not keep up
with the transmission.
• Transmission unsuccessful. The number of collisions exceeded the maximum allowed.
• Number of Collisions. The number of collisions
experienced during transmission of the :rame.
• Heartbeat Indicator. This. indicates the presence
of a heartbeat during the last Interframe Spacing
(IFS) after transmission.
When configured to Save Bad Frames the 82596
checks each incoming frame and reports the following errors.
• CRC error. Incorrect CRC in a properly aligned
frame;
• Alignment error. Incorrect CRC in a misaligned
frame.
• Frame too short. The frame is shorter than the
value configured for minimum frame length.
• Overrun. Part of the frame was not placed in
memory because the system bus did not keep up
with incoming data.
• Out of buffer. Part of the frame was discarded
because of insufficient memory storage space.
II

Receive collision. A collision was detected during
reception and the destination address of the incoming frame passes 82596 address filtering.
Collisions in the preamble are not counted.

• Length error. A frame not matching the frame
length parameter was detected.

I

82596DX/SX

RECEIVER FRAME AREA (RFA)

FD

FD
FREE BUFFER LIST (FBL)

RECEIVE
BUFFER
DESCRIPTOR(RBD)

RBD

RBD

DATA
BUFFER (DB)

[J

[J
290219-12

Figure 13. Receive Frame Area Diagram

RECEIVE FRAME STATUS
LINK FIELD
BUFFER DESCRIPTOR
LINK FIELD

NEXT RECEIVE
• -+ FRAME
DESCRIPTOR
BUFFER
DESCRIPTOR
-+
•

DESTINATION ADDRESS
SOURCE ADDRESS
LENGTH FIELD
290219-13

Figure 14. Receive Frame Descriptor

I

1-157

82596DX/SX

NETWORK PLANNING AND
MAINTENANCE
To properly plan, operate, and maintain a communication network, the network management entity
must accumulate information on network behavior.
The 82596 provides a rich set of network-wide diagnostics that can serve as the basis for a network
management entity.
Information on network activity is provided in the
status of each frame transmitted. The 82596 reports
the following activity indicators after each frame.
• Number of collisions. The number of collisions
the 82596 experienced while attempting to trans.
mit the frame.
• Deferred transmission. During the first transmission attempt the 82596 had to defer to traffic on
the link.
The 82596 updates its 32-bit statistical counters after each received frame that both passes address
filtering and is longer than the Minimum Frame
Length configuration parameter. The 82596 reports
the following statistics.
• CRC errors. The number of well-aligned frames
that experienced a CRC error.
• Alignment errors. The number of misaligned
frames that experienced a CRC error.
• No resources. The number of frames that· were
discarded because of insufficient resources for
reception.
• Overrun errors. The number of frames that were
not completely stored in memory because the
system bus did not keep up with incoming data.
• Receive Collision counter. The number of collisions detected during receive. Collisions occurring before the minimum frame length will be
counted as short frames. Collisions in the preamble will not be counted at all.
• Short Frame counter. The number of frames that
were discarded because they were shorter than
the configured minimum frame length.
Once again, these counters are not updated until the
82596 decodes a destination address match.
The 82596 can be configured to Promiscuous mode.
In this mode it captures <\11 frames transmitted on the
network without checking the Destination Addr~ss.
This is useful when implementing a monitoring station to capture all frames for analysis:

82596 to Save Bad Frames, and configure the
82596 t6 Promiscuous mode with space in the RFD
allocated for specific number of receive data bytes.
The 82596 will receive all frames and put them in the
RFD. Frames that exceed the available space in the
RFD will be truncated, the status will be updated,
and the 82596 will retrieve the next RFD. This allows
the user to capture the initial data bytes of each
frame (for i'1stance, the header) and discard the remainder of the frame.
The 82596 also has a· monitor mode for network
analysis. During normal operation the receive function enables the 82596 to receive frames which pass
address filtering. These frames must have the Start
of Frame Delimiter (SFD) field and must be longer
than the absolute minimum frame length of 5 bytes
(6 bytes in case of Multicast address filtering). Contents and status of the received frames are transferred to memory. The monitor function enables the
82596 to simply evaluate the incoming frames. The
82596 can monitor the frames that pass or do not
pass the address filtering. It can also monitor frames
which do not have the SFD fields. The 82596 can be
configured to only keep statistical information about
monitor frames. Three options are available in the
Monitor mode. These modes are selectable by the
two monitor mode configuration bits available in the
configuration comrnand.
When the first option is selected, the 82596 receives
good frames that pass address filtering and transfers them to memory while monitoring frames that
do not pass address filtering or are shorter than the
minimum frame size (these frames are not transferred to memory).· When this option is used the
82596 updates six counters: CRC errors, alignment
errors, no resource errors, overrun errors, short
frames, and total good frames received.
When the second option is selected, the receive
function is completely disabled. The 82596 monitors
only those frames that pass address filterings and
meet the minimum frame length requirement. When
this option is used the 82596 updates six counters:
CRCerrors, alignmelJt errors, total frames (good and
bad), short frames, collisions detected, and total
good frames.
When the third option is selected, the receive function is completely disabled. The 82596 monitors all
frames, including frames that do not have a Start
Frame Delimiter. When this option is used the 82596
updates six counter (CRC errors, alignment errors,
total frames (good and bad), short frames, collisions
detected, and total good frames.

A useful method of capturing frame headers is to
use the Simplified memory mode, configure the

1-158

I

82596DX/SX

STATION DIAGNOSTICS
AND SELF-TEST
The 82596 provides a large set of diagnostic and
network management functions. These include internal and external loopback and time domain reflectometry for locating fault points in the network cable.
The 82596 ensures software reliability by dumping
the contents of the 82596 internal registers into system memory. The 82596 has a self-test mode that
enables it to run an internal self-test and place the
results in system memory.

82586 SOFTWARE COMPATIBILITY
The 82596 has a software-compatible state in which
all its memory structures are compatible with the
82586 memory structure. This includes all the Action
Commands, the Receive Frame Area (including the
RFD, Buffer Descriptors, and Data Buffers), the System Control Block, and the initialization procedures.
There are two minor differences between the 82596
in the 82586-Compatible memory structure and the
82586.
• When the internal and external loop back bits in
the Configure command are set to 11 the 82596
is in external loopback and the LPBK pin is activated; in the 82586 this situation would produce
internal loopback.
• During a Dump command both the 82596 and
82586 dump the same number of bytes; however,
the data format is different.

INITIALIZING THE 82596
A Reset command is issued to the 82596 to prepare
it for normal operation. The 82596 is initialized
through two data structures that are addressed by

I

two pointers, the System Configuration Pointer
(SCP) and the Intermediate System Configuration
Pointer (ISCP). The initialization procedure begins
when a Channel Attention signal is asserted after
RESET. The 82596 uses the address of the double
word that contains the SCP as a default00FFFFF4h. Before the CA signal is asserted this
default address can be changed to any other available address by asserting the PORT pin and providing the desired address over the 031-04 pins of the
address bus. Pins 03-00 must be 0010; i.e., any
alternative address must be aligned to 16 byte
boundaries. All addresses sent to the 82596 must be
word aligned, which means that all pointers and
memory structures must start on an even address
(Ao = zero).

SYSTEM CONFIGURATION POINTER
(SCP)
.
The SCP contains the SYSBUS byte and the location of the next structure of the initialization process,
the ISCP. The following parameters are selected in
the SYSBUS.
• The 82596 operation mode.
• The Bus Throttle timer triggering method.
• Lock enabled.
• Interrupt polarity.
• Big Endian 32-bit entity mode.
Byte ordering is determined by the LEIBE pin.
LE/BE= 1 selects little end ian byte ordering and
LEIBE = 0 selects big endian byte ordering.
NOTE:
In the following, X indicates a bit not checked in
82586 mode. This bit must be set to 0 in all other
modes.

1-159

82596DX/SX
The following diagram illustrates the format of the SCPo
31

ODD WORD

16 15

EVEN WORD

0

10 0 0 0 0 0 0 010 0 0 0 0 0 0 o OFFFFF4h
X X X X X X X X X X X X X X X xix X X X X X X xix X X X X X X X OFFFFF8h
X X X X X XX X

SYSBUS

A31 .•.•....•...•... A24 A23

AO OFFFFFCh·

ISCP ADDRESS

A31 .•••.•••......•. A24 are not checked in 82586 mode.
X ••..•............. X
areas are not checked in 82586 mode; they must be 0 in all other modes.
23

SYSBUS

J l ',"-, "'-~ . .

I I
BE

,- ..
,,-",
-big-endian
~....entities.
'" "-,This........
~--.J
aa two
16-bit
il identical to
Iho 82596 AI .Iopplng dollnilion.
'
I - Tho 32-blt addr... polnlo.. In Linear mode are trealed
aa 32-bit big ."dian entities. This mode ia only supported
In Iho 82596 B .Iopplng. In Ihls modo tho SCB absolulo

addr... and .tattstlcal counter. afe .tln treated a8 two

16

1 liNT

IS-bit big .ndlon .ntltl...
, Inlorrupl polarlly

o-

Interrupt pin is active
high
1 - Intorrupt pin is actlyo
low

I I I I I I
LOCK

TRG

1.11

1.10

x

~ L: NOT CHECKED
o 0 : 82586 modo

,

'

1 0 : Linear mode

1 1 : Ro..rved

o : Inlernal trlggorlng of tho
Bu. Throttle tim ...
I : oxlornal Irlggorlng of the
Bus Throttlo tlmo..

o : LOCK fun.tlon

onabled
I : LOCK fun.tion dlsablod
290219-14

ISCP ADDRESs-.- The physical address of the ISCP. In the 82586 mode, bits A31-A24 are considered to
be zero.
Figure 15. The System Configuration Pointer

Writing the Sysbus
When writing the Sysbus byte it is important to pay attention to the byte order.
• When a Little Endian processor is used, the Sysbus byte is located at byte address 00FFFFF6h (or address
, .n + 2 if an alternative SCP address n was programmed).
.
• When a processor using Big Endian byte ordering is used; the SYSBUS, alternative SCP, and ISCP addresses will be different.
• The Sysbus byte is located at 00FFFFF7h .
• If an alternative SCP address is programmed, the SYSBUS byte should be at byte address

1-160

n+ 1.

I

82596DX/SX

/

INTERMEDIATE SYSTEM CONFIGURATION POINTER (lSCP)
The ISCP indicates the location of the System Control Block. Often the SCP is in ROM and the ISCP is in RAM.
The CPU loads the SCB address (or an equivalent data structure) into the ISCP and asserts CA. This Channel
Attention signal causes the 82596 to begin its initialization procedure and to get the SCB address from the
ISCP and SCPo In 82586 and 32·bit Segmented modes the SCP base address is also the base address of all
Command Blocks, Frame Descriptors, and Buffer Descriptors (but not buffers). All these data structures must
reside in one 64·kB segment; however, in Linear mode no such limitation is imposed.
The following diagram illustrates the ISCP format.

ODD WORD

EVEN WORD
16 15
87
0
~A~1~5________~S~C~B~OrF~FS~E~T~________'~A~0L-______________~____B~U~S~Y~____~ISCP
~______~______~A_2_3________________
SC_B__
BA_S_E_A_D_D_R_E_S_S________________A~O ISCP+4
31

t

x x x x x x x x -in 82586 mode
A31 ................ A24 - in 32·bit segmented mode
BUSY

-

Indicates that the 82596 is being initialized. The CPU sets the ISCP to 01 h before it gives
the first CA to the 82596. The ISCP is cleared by the 82596 after the SCB base and offset
are read. Note that the most significant byte of the first word of the ISCP is not modified
when BUSY is cleared.

SCB OFFSET-This 16·bit quantity specifies the offset portion of the address of the SCB.
SCB BASE

-

Specifies the base portion of the address of the SCB. The base of SCB is also the base of
all 82596 Command Blocks, Frame Descriptors and Buffer Descriptors. In the 82586
mode, bits A31-A24 are considered to be zero.

Figure 16. The Intermediate System Configuration Pointer-82586 and 32-8it Segmented Modes

ODD WORD
31

16 15

EVEN WORD
87

o

rO~O__O~.~._
..~.~.._.~
..~.~
..~.~
..~.~
.. ~.~
.. ~..~.~..~.~..~.~..~.~"~'~"~'~"~'~"~'~"~'~"~'~"~O~O~0L-_____B~U~S~Y~__--1ISCP

A31

.SCB ABSOLUTE ADDRESS

AO ISCP + 4

~------------------------------------------------------------~

BUSY

-

Indicates that the 82596 is being initialized. The ISCP is set to 01 h by the CPU before its
first CA to the 82596. It is cleared by the 82596 after the SCB address is read.

SCB ADDRESS- This 32-bit quantity specifies the physical address of the SCB.

Figure 17. The Intermediate System Configuration Pointer-Linear Mode.

INITIALIZATION PROCESS
The CPU sets up the SCP, ISCP, and the SCB structures, and, if desired, an alternative SCP address. It also
sets BUSY to 01 h. The 82596 is initialized when a Channel Attention signal follows a Reset signal, causing the
82596 to access the System Configuration Pointer. The sysbus byte, the operational mode, the bus throttle
timer triggering method, the interrupt polarity, and the state of LOCK are read. After reset the bus throttle

I

1-161

82596DX/SX

timers are essentially disabled-the T-ON value is infinite, the T-OFF value is zero. After the SCP is read, the
82596 reads the ISCP and saves the SCB address. In 82586 and 32-bit Segmented modes this address is
represented as a base address plus the offset (this base address is also the base address of all the control
blocks). In Linear mode the base address is also an absolute address. The 82596 clears BUSY, sets CX and
CNR to equal 1 in the SCB, clears the SCB command word, sends. an interrupt to the CPU, and awaits another
Channel Attention signal. RESET configures the 82596 to its default state before CA is asserted.

CONTROLLING THE 82596DX/SX
The host CPU controls the 82596 with the commands, data structures, and methods described in this section.
The CPU and the 82596 communicate through shared memory structures. The 82596 contains two independent units: the Command Unit and the Receive Unit. The Command Unit executes commands from the CPU,
and the Receive Unit handles frame reception. These two units are controlled and monitored by the CPU
through a shared memory structure called the System Control Block (SCB). The CPU and the 82596 use the
CA and INT signals to communicate with the SCB.

82596 CPU ACCESS INTERFACE (PORT)
The 82596 has a CPU access interface that allows the host CPU to do four things.
• Write an alternative System Configuration Pointer address.
• Write an alternative Dump area pointer and perform Dump.
• Execute a software reset.
• Execute a self-test.
The following events initiate the CPU access state.
• Presence of an address on the 0 31 -04 data bus pins.
• The 03-00 pins are used to select one of the four functions.
• The PORT input pin is asserted, as in a regular write cycle.
NOTE
The SCP Dump and Self-Test addresses must be 16-byte aligned.
The 82596 requires two 16-bit write cycles for a port command. The first write holds the internal machines and
reads the first 16 bits, the second activates th~ PORT command and reads the second 16 bits.
The PORT Reset is useful when only the 82596 needs to be reset. The CPU must wait for 1a-system and 5-serial clocks before issuing another CA to the 82596; this new CA begins new initialization process.

a

The Dump function is useful for troubleshooting No Response problems. If the chip is in a No Response state,
the PORT Dump operation can be executed and a PORT Reset can be used to reinitialize the 82596 without
disturbing the rest of the system.
The Self-Test function can be used for board testing; the 82596 will execute a self-test and write the results to
memory.
Table 2. PORT Function Selection

031 .................................. 04···························· .00
Function

Addresses and Results

03

02

01

Do

Reset

A31

Don't Care

.A4

a

a

a

a

Self-Test

A31

Self-Test Results Address

A4

a

a

a

1

SCP

A31

Alternative SCP Address

A4

a

a

1

a

Dump

A31

Dump Area Pointer

A4

a

a

1

1

1-162

I

82596DX/SX

MEMORY ADDRESSING FORMATS
The 82596 accesses memory by 32-bit addresses. There are two types of 32-bit addresses: linear and segmented. The type of address used depends on the 82596 operating mode and the type of memory structure it
is addressing. The 82596 has three operating modes.
• 82586 Mode
• A Linear address is a single 24-bit entity. Address pins A31-A24 are always zero.
• A Segmented address uses a 24-bit base and a 16-bit offset.
• 32-bit Segmented Mode
• A Linear address is a single 32-bit entity.
• A Segmented address uses a 32-bit base and a 16-bit offset.

NOTE:
In the previous two memory addressing modes, each command header (CB, TBD, RFD, RBD, and SCB)
must wholly reside within one segment. If the 82596 encounters a memory structure that does not follow this
restriction, the 82596 will fetch the next contiguous location in memory (beyond the segment).
• Linear Mode
• A Linear address is a single 32-bit entity.
• There are no Segmented addresses.
Linear addresses are primarily used to address transmit and receive data buffers. In the 82586 and 32-bit
Segmented modes, segmented addresses (base plus offset) are us'ed for all Command Blocks, Buffer Descriptors, Frame Descriptors, and System Control Blocks. When using Segmented addresses, only the offset
portion of the entity being addressed is specified in the block. The base for all offsets is the same-that of the
SCB. See Table A.

LITTLE ENDIAN AND BIG END IAN BYTE ORDERING
The 82596 supports both Little Endian and Big Endian byte ordering for its memory structures.
The 82596A 1 stepping supports Big Endian byte ordering for word and byte entities. Dword entities are not
supported with 82596A 1 Big Endian byte ordering. This results in slightly different 82596 memory structures
for Big Endian operation. These structures are defined in the 32-Bit LAN Components A 1 Manual.

I

1-163

82596DX/SX

intel®

The 82596 B stepping supports Big Endian byte ordering for dword, word, and byte entities in Linear mode
only. All 82596 B 32-bit address pointers are treated as 32-bit Big Endian entities, however, the SCB absolute
address and statistical counters are treated as two. 16-bit Big Endian !3ntities. This 32-bit Big Endian entity
support is configured via bit 7 in the SYSBUS byte.
The 82596 C-step has a New Enhanced Big Endian Mode where in Linear Addressing mode, true 32-bit Big
Endian functionality is achieved. New Enhanced Big Endian Mode is enabled exactly the same as the B-step,
by setting bit 7 of the SYSBUS byte. This mode is software compatible with the big end ian mode of the B-step
with one exception-no 32-bit addresses need to be swapped by software in the C-step. In this new mode, the
82596 C-step treats 32-bit address pointers as true 32-bit entities and the SCB absolute address and statistical
counters are still treated as two 16-bit big endian entities. Not setting this mode will configure the 82596 C-step
to be 100% compatible to the A 1-step big endian mode.
NOTE:
All 82596 memory entities must be word or dword aligned, except the transmit buffers can be byte aligned
for the 82596 B or C steppings.
An example of a double word entity is a frame descriptor command/status dword, whereas the raw data of the
frame are byte entities. Both 32- and 16-bit buses are supported. When a 16-bit bus is used with Big Endian
memory organization, data lines D15-DO are used. The 82596 has an internal crossover that handles these
swap operations.

COMMAND UNIT (CU)
The Command Unit is the logical unit that executes Action Commands from a list of commands very similar to
a CPU program. A Command Bloc.k is associated with each Action Command. The CU is modeled as a logical
machine that takes, at any given time, one of the following states.
.
• Idle. The CU is not executing a command and is not associated with a CB on the list. This is the initial state.
• Suspended. The CU is not executing a command; however, it is associated with a CB on the list. The
suspend state can only be reached if the CPU forces it through the SCB or sets the suspend bit in the RFD.
• Active. The CU is executing an Action Command and pointing to its CB.
The CPU can affect CU operation in two ways: by issuing a CU Control Command or by setting bits in the.
Command word of the Action Command.
When programming the 82596 CU, it is important to consider the asynchronous way the 82596 processes
commands. If a command is issued to the 82596 CU, it may be busy processing other commands. In order to
avoid asynchronous race conditions, the following guidelines are recommended to the 82596 programmer:
.. If the CU is already in the Active state, and another command needs to be executed, it is unwise to
immediately issue another CU Start command. If a new command (or list of commands) needs to be
started, first issue a CU Suspend command, wait for the CU to become Suspended, then issue the new CU
Start. This will insure that all commands are processed correctly.
• In general, it is a good idea to make sure any CU command has been accepted and executed before
issuing a new control command to the CU.

1·164

I

82596DX/SX

RECEIVE UNIT (RU)
The Receive Unit is the logical unit that receives frames and stores them in memory. The RU is modeled as a
logical machine that takes, at any given time, one of the following states.
• Idle. The RU has no memory resources and is discarding incoming frames. This is the initial state.

• No Resources. The RU has no memory resources and is discarding incoming frames. This state differs
from Idle in that the RU accumulates statistics on the number of discarded frames.
• Suspended. The RU has memory available for storing frames, but is discarding them. The suspend state
can only be reached if the CPU forces it through the SCB or sets the suspend bit in the RFD.
• Ready. The RU has memory available and is storing incoming frames.

The CPU can affect RU operation in three ways: by issuing a RU Control Command, by setting bits in the
Frame Descriptor Command word of the frame being received, or by setting the El bit of the current buffer's
Buffer Descriptor.
.
When programming the 82596 RU, it is important to consider the asynchronous way the 82596 processes
receive frames. If an RU Start is issued to the 82596 RU, it may be busy processing other incoming packets. In
order to avoid asynchronous race conditions, the following guidelines are recommended to the 82596 programmer:
• If the RU is already in the Ready state, and a new RFA is required to be started, it is unwise to immediately
issue another RU Start command. If the new RFA needs to be started, first issue an RU Suspend command, wait for the RU to become Suspended, then issue the new RU Start. This will insure that all incoming
frames are received correctly.
• In general, it is a good idea to make sure any RU command has been accepted and executed before
issuing a new control command to the RU.

SYSTEM CONTROL BLOCK (SCB)
The SCB is a memory block that plays a major role in communications between the CPU and the 82596. Such
communications include the following.
.
• Commands issued by the CPU
• Status reported by the 82596
Control commands are sent to the 82596 by writing them into the SCB and then asserting CA. The '82596
examines the command, performs the required action, and then clears the SCB command word. Control
commands perform the following types of tasks.
• Operation of the Command Unit (CU). The SCB controls the CU by specifying the address of the Command
Block List (CBl) and by starting, suspending, resuming, or aborting execution of CBl commands.

I

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82596DX/SX

• Operation of the Bus Throttle. The SCB controls the Bus Throttle timers by providing them with new values
and sending the Load and Start timer commands. The timers can be operated in both the 32-bit Segmented
and Linear modes.
• Reception of frames by the Receive Unit (RU). The SCB controls the RU by specifying the address of the
Receive Frame Area and by starting, suspending, resuming, or aborting frame reception.
• Acknowledgment of events that cause interrupts.
• Resetting the chip.
The 82596 sends status reports to the CPU via the System Control Block. The SCB contains four types of
status reports.
• The cause of the current interrupts. These interrupts are caused by one or more of the following 82596
events.
• The Command Unit completes an Action Command that has its I bit set.
• The Receive Unit receives a frame.
• The Command Unit becomes inactive.
• The Receive Unit becomes not ready.
• The status of the Command Unit.
• The status of the Receive Unit.
• Status reports from the 82596 regarding reception of corrupted frames.
Events can be cleared only by CPU acknowledgment. If some events are not acknowledged by the ACK field
the Interrupt signal (INT) will be reissued after Channel Attention (CA) is processed. Furthermore, if a new
event occurs while an interrupt is set, the interrupt is temporarily cleared to trigger edge-triggered interrupt
controllers.
The CPU uses the Channel Attention line to cause the 82596 to examine the SCB. This signal is trailing-edge
triggered-the 82596 latches CA on the trailing edge. The latch is cleared by the 82596 before the SCB
control command is read.
31

ODDWORD
ACK

IXI

cuc

IRI

16 15
RUC

IX X X X

o

EVEN WORD
STAT

I0I

cus

I0I

RUS

I0 0

0 0 SCB

RFAOFFSET

CBLOFFSET

SCB

ALIGNMENT ERRORS

CRCERRORS

SCB

OVERRUN ERRORS

RESOURCE ERRORS

SCB

+
+
+

4
8
12

Figure 18. SCB-82586 Mode
31

ODD WORD
ACK

10 1

cuc

IRI

16 15
RUC

RFAOFFSET

10

o 0

01

EVEN WORD
STAT

I
CRCERRORS

RUS

1 0 1 CUS I
CBLOFFSET

ALIGNMENT ERRORS

OVERRUN ERRORS (*)
RCVCDT ERRORS (*)
SHORT FRAME ERRORS

I

ITlo

+4
+8
SCB + 12
SCB + 16
SCB + 20
SCB + 24
SCB + 28
SCB + 32

SCB

SCB

RESOURCE ERRORS (*)

T-ONTIMER

0
0 o SCB

T-OFFTIMER

* In MONITOR mode these counters change function

Figure 19. SCB-32·Bit Segmented Mode

1-166

I

82596DX/SX

31

ODD WORD
ACK

I

a I cuc

IRI

16 15
RUC

10 a a 01

EVEN WORD
STAT

I

aI

CUS

RUS

I

ITla

a
a a SCB

COMMAND BLOCK ADDRESS

SCB

RECEIVE FRAME AREA ADDRESS

SCB

+4
+B

CRCERRORS

SCB

+

12

ALIGNMENT ERRORS

SCB

+

16

RESOURCE ERRORS ('J

SCB

OVERRUN ERRORS ('J

SCB

RCVCDT ERRORS ('J

SCB

+ 20
+ 24
+ 28

SCB

+

32

SCB

+

36

SHORT FRAME ERRORS

I

T·ONTIMER

T·OFFTIMER

'In MONITOR mode these counters change function

Figure 20. SCB-Linear Mode

Command Word
31

16

a

; CUC;

R

; RUC;

a

a

a

a

SCB

+

2

These bits specifiy the action to be performed as a result of a CA. This word is set by the CPU and cleared by
the 82596. Defined bits are:
Bit 31 ACK-CX

-

Acknowledges that the CU completed an Action Command.

Bit 30 ACK-FR

-

Acknowledges that the RU received a frame.

Bit 29 ACK-CNA

-

Acknowledges that the Command Unit became not active.

Bit 28 ACK-RNR

-

Acknowledges that the Receive Unit became not ready.

Bits 24-26 CUC

-(3 bits) This field contains the command to the Command Unit. Valid values are:

o -

I

NOP (does not affect current state of the unit).

-

Start execution of the first command on the CBL. If a command is executing,
complete it before starting the new CBL. The beginning of the CBL is in CBL
OFFSET (address).

2

-

3
4
5

-

Resume the operation of the Command Unit by executing the next command.
This operation assumes that the Command Unit has been previously suspended.
Suspend execution of commands on CBL after current command is complete.

-

Abort current command immediately.

-

Loads the Bus Throttle timers so they will be initialized with their new values
after the active timer (T-ON or T-OFF) reaches Terminal Count. If no timer is
active new va.lues will be loaded immediately. This command is not valid in
82586 mode.

6

-

Loads and immediately restarts the Bus Throttle timers with their new values.
This command is not valid in 82586 mode.

7

-

Reserved.

1-167

82596DX/SX

Bits 20-22 RUC

-

(3 bits) This field contains the command to the Receive Unit. Valid values are:

o

-

NOP (does not alter current state of unit).

-

Start reception of frames. The beginning of the RFA is contained in the RFA
OFFSET (address). If a frame is being received complete reception before
starting.

2

-

Resume frame reception (only when in suspended state).

3

-

Suspend frame reception. If a frame is being received complete its reception
before suspending.

4

-

Abort receiver operation immediately.

5-7 Bit 23 RESET

-

Reserved.

Reset chip (logically the same as hardware RESET).

Status Word
15

0

o

: GUS:

o

: GUS:

0

: RUS:

0

0

0

0

T

0

0

GJ

SGB

82586 Mode
15

0
RyS

SGB

32-Bit Segmented and Linear Modes
Indicates the status of the 82596. This word is modified only by the 82596. Defined bits are:
The CU finished executing a command with its I (interrupt) bit set.

Bit 15 CX

-

Bit 14 FR

-

The RU finished receiving a frame.

Bit 13 CNA

-

The Command Unit left the Active state.

Bit 12 RNR

-

The Recl9ive Unit left the Ready state.

Bits 8-10 CUS

-

(3 bits) This field contains the status of the command unit. Valid values are:

o

-Idle

1

-

2

-Active

3-7 Bits 4-7 RUS

-

Suspended
Not used

This field contains the status of the receive unit. Valid values are:
Oh (0000) -

Idle

1h (0001) -

Suspended

2h (0010) -

No resources. This bit indicates both no resources due to lack of RFDs
in the RDL and no resources due to lack of RBDs in the FBL.

4h (0100) -

Ready

Ah (1010) -

No resources due to no more RBDs. (Not in the 82586 mode.)

Ch (1100) -

No more RBDs (not in the 82586 mode).

No other combinations are allowed.
Bit3 T

-

Bus Throttle timers loaded (not in 82586 mode).

SCB OFFSET ADDRESSES
CBl Offset (Address)
In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the
first Command Block on the CBL. In Linear mode it is a 32-bit linear address for the first Command Block on
the CBL. It is accessed only if CUC equals Start.
1-168

I

82596DX/SX

RFA Offset (Address)
In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the
Receive Frame Area. In Linear mode it is a 32-bit linear address for the Receive Frame Area. It is accessed
only if RUC equals Start.

SCB STATISTICAL COUNTERS
Statistical Counter Operation
• The CPU is responsible for clearing all error counters before initializing the 82596. The 82596 updates
these counters by reading them, adding 1, and then writing thelTl back to the SCB.
o The counters are wraparound counters. After reaching FFFFFFFFh the counters wrap around to zero.
• The 82596 updates the required counters for each frame. It is possible for more than one counter to be
updated; multiple errors will result in all affected counters being updated.
• The 82596 executes the read-counter/incrementlwrite-counter operation without relinquishing the bus
(locked operation). This is to ensure that no logical contention exists between the 82596 and the CPU due
to both attempting to write to the counters Simultaneously. In the dual-port memory configuration the CPU
should not execute any write operation to a counter if LOCK is asserted .
• The counters are 32-bits wide and their behavior is fully compatible with the IEEE 802.3 standard. The
82596 supports all relevant statistics (mandatory, optional, and desired) through the status of the transmit
and receive header and directly through SCB statistics.

CRCERRS
This 32-bit quantity contains the number of aligned frames discarded because of a CRC error. This counter is
updated, if needed, regardless of the RU state.

ALNERRS
This 32-bit quantity contains the number of frames that both are misaligned (Le., where CRS deasserts on a
nonoctet boundary) and contain a CRC error. The counter is updated, if needed, regardless of the RU state.

SHRTFRM
This 32-bit quantity contains the number of received frames shorter than the minimum frame length.
The last three counters change function in monitor mode.

RSCERRS
This 32-bit quantity contains the number of good frames discarded because there were no resources to
contain them. Frames intended for a host whose RU is in the No Receive Resources state, fall into this
category. This counter is updated only if the RU is in the No Resources state. When in Moniitor mode, this
counter counts the total number of frames.

OVRNERRS
ThiS 32-bit quantity contains the number of frames known to be lost because the local system bus was not
available. If the traffic problem lasts longer than the duration of one frame, the frames that follow the first are
lost without an indicator, and they are not counted. This counter is updated, if needed, regardless of the RU
state.

RCVCDT
This 32-bit counter contains the number of collisions detected during frame reception. This counter will only be
updated if at least 64 bytes of data are received before the collision occurs. If a collision occurs before 64
bytes of data are received, the frame is counted as a short frame. If the collisions occurs in the preamble, no
counters are incremented.

I

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82596DX/SX

ACTION COMMANDS AND OPERATING MODES
This section lists all the Action Commands of the Command Unit Command Block List (CBl). Each command
contains the Command field, the Status and Control fields, the link to the next Action Command, and any
command-specific parameters. There are three basic types of action commands: 82596 Configuration and
Setup, Transmission, and Diagnostics. The following is a list of the actual commands.
• NOP

• Transmit

• Individual Address Setup

• TDR
• Dump
• Diagnose

• Configure
• MC Setup

. The 82596 has three addressing modes. In the 82586 mode all the Action Commands look exactly like those
of the 82586.
.
• 82586 Mode. The 82596 software and memory structure is compatible with the 82586. .
• 32-Bit Segmented Mode. The 82596 can access the entire system memory and use the two new memory
structures-Simplified and Flexible-while still using the segmented approach. This does not require any
significant changes to existing software.
• Linear Mode. The 82596 operates in a flat, linear, 4 gigabyte memory space without segmentation. It can
also use the two new memory structures.
In the 32-bit Segmented mode there are some differences between the 82596 and 82586 action commands,
mainly in programming and activating new 82596 features. Those bits marked "don't care" in the compatible
mode are not checked; however, we strongly recommend that those bits all be zeroes; this will allow future
enchancements and extensions.
In the Linear mode all of the addr.ess offsets become 32-bit address pointers. All new 82596 features are
accessible in this mode, and all bits previously marked "don't care" must be zeroes.
The Action Commands, and all other 82596 memory structures, must begin on even byte boundaries, i.e., they
must be word aligned.
NOP
This command results in no action by the 82596 except for those performed in the normal command processing. It is used to manipulate the CBl manipulation. The format of the NOP command is shown in Figure 21.
NOP-82586 and 32-Bit Segmented Modes
ODD WORD

0

EVEN WORD

X X X X X X X X X X

0

X X X X X X X X X X

0

0'0

0

0

0

o

,0

0

LINK OFFSET

o

0

AO 4

NOP-Linear Mode
1615

ODD WORD

0

0

0 .0

0

0

0
LINK ADDRESS

0

EVEN WORD

0

0

0

0

0

0

0

0

0

0

0

0

o

0

AO 4

Figure 21

1-170

I

82596DX/SX

where:
LINK POINTER
EL
S

-In the 82586 or 32-bit Segmented modes this is a 16-bit offset to the next Command
Block. In the Linear mode this is the 32-bit address of the next Command Block.
- If set, this bit indicates that this command block is the last on the CBL.
-

CMD (bits 16-18) Bits 19-28

C

-

B

-

If set to one, suspend the CU upon completion of this CB.
If set to one, the 82596 will generate an interrupt after execution of the command is
complete. If I is not set to one, the CX bit will not be set.
The Nap command. Value: Oh.
Reserved (zero in the 32-bit Segmented and Linear modes).
This bit indicates the execution status of the command. The CPU initially resets it to zero
when the Command Block is placed on the CBL. Following a command Completion, the
82596 will set it to one.
This bit indicates that the 82596 is currently executing the Nap command. It is initially
reset to zero by the CPU. The 82596 sets it to one when execution begins and to zero
when execution is completed. This bit is also set when the 82596 prefetches the com.
mand.

NOTE:
The C .and B bits are modified in one operation.
OK
- Indicates that the command was executed without error. If set to one no error occurred
(command executed OK). If zero an error occur.
INDIVIDUAL ADDRESS SETUP

This command is used to load the 82596 with the Individual Address. This address is used by the 82596 for
inserting the Source Address during transmission and recognizing the Destination Address during reception.
After RESET, and prior to Individual Address Setup Command execution, the 82596 assumes the Broadcast
Address is the Individual Address in all aspects, i.e.:
• This will be the Individual Address Match reference.
• This will be the Source Address of a transmitted frame (for AL-LOC = 0 mode only).
The format of the Individual Address Setup command is shown in Figure 22.
IA Setup-82586 and 32-Bit Segmented Modes
ODD WORD

31
ELI S I I

16 15

IX X X X X X X X X

xla a

, INDIVIDUAL ADDRESS

1 c I B lOKI A I

EVEN WORD
a
a
a
a
a
a
a
a
a
a
a
a
a
a

1st byte A15

6th byte

5th byte

LINK OFFSET

Aa 4
3rd byte

4th byte

8

IA Setup-Linear Mode
31

1615

ODD WORD

ELI S II I

a a a a a a a a a 010 a

A31

a

EVEN WORD

1 I c I B lOKI A I

a a a a a a a a a a

LINK ADDRESS
4th byte

3rd byte

0

0

o

AO 4

I

INDIVIDUAL ADDRESS

1st byte

8

I

6th byte

5th byte

C

Figure 22
where:
LINK ADDRESS,
EL, B, C, I, S

-

As per standard Command Block (see the Nap command for details)

A

-

Indicates that the command was abnormally terminated due to CU Abort control
command. If one, then the command was aborted, and if necessary it should be
repeated. If this bit is zero, the command was not aborted.

I

1-171

82596DX/SX

Bits 19-28
CMD (bits 16-18)
INDIVIDUAL ADDRESS -

Reserved (zero in the 32-bit Segmented and Linear modes).
The Address Setup command. Value: 1h.
The individual address of the node, 0 to 6 bytes long.

The least significant bit of the Individual Address must be zero for Ethernet (see the Command Structure).
However, no enforcement of 0 is provided by the 82596. Thus, an Individual Address with 1 as its least
significant bit is a valid Individual Address in all aspects.
The default address length is 6 bytes long, as in 802.3. If a different length is used the IA Setup command
should be executed after the Configure command.
CONFIGURE
The Configure command loads the 82596 with its operating parameters. It allows changing some of the
parameters by specifying a byte count less than the maximum number of configuration bytes (11 in the 82586
mode, 14 in the 32-Bit Segmented and Linear modes). The 82596 configuration depends on its mode of
operation.
• In the 82586 mode the maximum number of configuration bytes is 12. Any number larger than 12 will be
reduced to 12 and any number less than 4 will be increased to 4. When configuring the 12th byte (Byte 11
undefined) in 82586 mode this byte should be all ones.
• The additional features of the serial side are disabled in the 82586 mode.
• In both the 32-Bit Segmented and Linear modes there are four additional configuration bytes, which hold
parameters for additional 82596 features. If these parameters are not accessed, the 82596 will follow their
default values.
• For more detailed information refer to the 32-Bit LAN Components User's Manual.
The format of the Configure command is shown in Figures 23, 24, and 25.
31

X

1615

ODD WORD

ELI S II I X

X

X X

X X X X

X X xlo

1

0

EVEN WORD

c I B lOKI A 10

0

0

0

0

0

0
0

0

0

0

0

LINK OFFSET

AO 4

Byte 1

Byte 0

Byte 5

Byte 4

Byte 3

Byte 2

8

Byte 9

Byte 8

Byte?

Byte 6

12

Byte 10

16

X X

X X

X

X X X

X X X

A15

o 0

X

X

X X

X

X

X

X X X X

Figure 23. CONFIGURE-82586 Mode
31

1615

ODD WORD

ELI S II 10

0

0

0

0

0

0

0

0

010

1

0

0

EVEN WORD

c I B lOKI A 10

0

0

0

0

0

0

0

0

LINK OFFSET

A15

0

0

o 0
AO 4

Byte 1

Byte 0

Byte 5

Byte 4

Byte 3

Byte 2

8

Byte 9

Byte 8

Byte?

Byte 6

12

Byte 13

Byte 12

Byte 11

Bytel 0

16

Figure 24. CONFIGURE-32-Bit Segmented Mode

1-172

I

82596DX/SX

31

ODD WORD

ELI S II 10

0

0

0

0

0

0

1615
0

0

01 0

A31

1

o

EVEN WORD

c I B lOKI A I 0

0

0

0

0

0
0

0

0

0

0

LINK ADDRESS

0

o 0
AO 4

Byte 3

Byte 2

Byte 1

ByleO

Byle7

Byte 6

Byte 5

Byte 4

12

Byte 11

Byte 10

Byte 9

Byle8

16

Byte 13

Byle12

20

X X X X X X X X X X X X X X X X

LINK ADDRESS, EL, B, C,I, S
A

-

Bits 19-28
CMD (bits 16-18) -

8

Figure 25. CONFIGURE-Linear Mode
As per standard Command Block (see the NOP command for details) _

Indicates that the command was abnormally terminated due to a CU Abort control command. If 1, then the command was aborted and if necessary it should be repeated. If this
bit is 0, the command was not aborted.
Reserved (zero in the 32-Bit Segmented and Linear Modes)
The CONFIGURE command. Value: 2h.

The interpretation of the fields follows:
7

6

5

4

p

X

X

X

BYTE 0
BYTE CNT (Bits 0-3)

3

2

1

o

BYTE?OUNT

Byte Count. Number of bytes, including this one, that hold parameters to be configured.

PREFETCHED (Bit 7)

Enable the 82596 to write the prefetched bit in all prefetch
RBDs.

NOTE:
The P bit is valid only in the new memory structure modes. In 82586 mode this bit is disabled
(I.e., no prefetched mark).

o

7
X

BYTE 1
FIFO Limit (Bits 0-3)
MONITOR# (Bits 6-7)

X

FIFO:LlMIT

FIFO limit.
Receive monitor options. If the Byte Count of the configure
command is less than 12 bytes then these Monitor bits are
ignored.

DEFAULT: C8h

o

7
SAVBF

BYTE 2
RESUME_RD (Bit 1)

o

o

o

o

o

0- The 82596 does not reread the next CB on the list when a CU RESUME
Control Command is issued.
1- The 82596 will reread the next CB on the list when a CU RESUME
Control Command is issued. This is available only on the 82596B stepping.

SAV BF (Bit 7)

0- Received bad frames are not saved in the memory.
1- Received bad frames are saved in the memory.

DEFAULT: 40h

I

1-173

82596DX/SX

intel®

7

o
LOOP BACK
MODE

BYTE

PREAMBLE LENGTH

ADDRESS LENGTH

3

ADR LEN (Bits 0-2)

Address length (any kind).

NO SCR ADD INS (Bit 3)

No Source Address Insertion.
In the 82586 this bit is called AL LOC.

PREAM LEN (Bits 4-5)

Preamble length.

LP BCK MODE (Bits 6-7)

Loopback mode.

DEFAULT: 26h

o

7

IBOFMETD I

EXPO~ENTIAL PRlpRITY

o

BYTE 4
LIN PRIO (Bits 0-2)

Linear Priority.

EXP PRIO (Bits 4-6)

Exponential Priority.

BOF METD (Bit 7)

Exponential Backoff method.

DEFAULT: OOh

o

7
: INTER FRNY,E SPACING :

BYTE 5
INTER FRAME SPACING

Interframe spacing.

DEFAULT: 60h

o

7
SLOT TI¥E - LOW

BYTE 6
SLOT TIME(L)

Slot time, low byte.

DEFAULT: OOh

o·

7

~AXIMUM RE1RY NUMBE~

o

BYTE 7
SLOT TIME (H)
(Bits 0-2)

Slot time, high part ..

RETRY NUM (Bits 4-7)

Number of transmission retries on collision.

DEFAULT: F2h

1-174

I

82596DX/SX

BYTE 8
PRM (Bit 0)

Promiscuous mode.

BC DIS (Bit 1)

Broadcast disable.

MANCH/NRZ (Bit 2)

Manchester or NRZ encoding. See specific timing requirements for TxC in Manchester mode.

TONO CRS (Bit 3)

Transmit on no CRS.

NOCRC INS (Bit 4)

No CRC insertion.

CRC-16/CRC-32 (Bit 5)

CRC type.

BIT STF (Bit 6)

Bit stuffing.

PAD (Bit 7)

Padding.

DEFAULT: OOh

o

7

I CDTSRC I

COLLI~ION DETECT:FILTER

CRSSRC

BYTE 9
CRSF (Bits 0-2)

Carrier Sense filter (length).

CRS SRC (Bit 3)

Carrier Sense source.

CDTF (Bits 4-6)

Collision Detect filter (length).

CDT SRC (Bit 7)

Collision Detect source.

DEFAULT: OOh
7

0

~INIMUM FR~ME LENGT~

I

I

BYTE 10
MIN FRAME LEN

Minimum frame length.

DEFAULT: 40h

o

7

MCJLL

CDBSAC

AUTOTX

CRCINM

LNGFLD

PRECRS

I

BYTE 11
PRECRS (Bit 0)

Preamble until Carrier Sense

LNGFLD (Bit 1)

Length field. Enables padding at the End-of-Carrier framing
(802.3).

CRCINM (Bit 2)

Rx CRC appended to the frame in memory.

AUTOTX (Bit 3)

Auto retransmit.

CDBSAC (Bit 4)

Collision Detect by source address recognition.

MCJLL (Bit 5)

Enable to receive all MC frames.

MONITOR (Bits 6-7)

Receive monitor options.

DEFAULT: FFH

I

1-175

82596DX/SX
7

o

FOX

o

o

I

o

o

I

o
o

o

BYTE 12
FDX (Bit 6)

Enables Full Duplex operation.

DEFAULT: OOh

o

7

I

OIS_BOF

I

MULT...:..IA

I

BYTE 13
MULT _IA (Bit 6)
DIS_BOF (Bit 7)

Multiple individual address.
. Disable the backoff algorithm.

DEFAULT: 3Fh

1-176

I

82596DX/SX
A reset (hardware or software) configures the 82596 according to the following defaults.
Table 4. Configuration Defaults
Parameter

,
,
,

•
•

•

•
•

,

•

ADDRESS LENGTH
AIL FIELD LOCATION
AUTO RETRANSMIT
BITSTUFFING/EOC
BROADCAST DISABLE
CDBSAC
CDTFILTER
CDTSRC
CRC IN MEMORY
CRC-16/CRC-32
CRSFILTER
CRSSRC
DISBOF
EXT LOOPBACK
EXPONENTIAL PRIORITY
EXPONENTIAL BACKOFF METHOD
FULL DUPLEX (FDX)
FIFO THRESHOLD
INT LOOPBACK
INTERFRAME SPACING
LINEAR PRIORITY
LENGTH FIELD
MIN FRAME LENGTH
MCALL
MONITOR
MANCHESTER/NRZ
MULTI IA
NUMBER OF RETRIES
NO CRC INSERTION
PREFETCH BIT IN RBD
PREAMBLE LENGTH
Preamble Until CRS
PROMISCUOUS MODE
PADDING.
SLOT TIME
SAVE BAD FRAME
TRANSMIT ON NO CRS

Default Value

Units/Meaning

Bytes
Located in FD
Auto Retransmit Enable
EOC
Broadcast Reception Enabled
Disabled
Bit Times
External Collision Detection
CRC Not Transferred to Memory
CRC-32
Bit Times
External CRS
Backoff Enabled
Disabled
802.3 Algorithm ..
802.3 Algorithm
CSMAlCD Protocol (No FDX)
TX: 32 Bytes, RX: 64 Bytes
Disabled
Bit Times
802.3 Algorithm
Padding Disabled
"64 Bytes
1
Disabled
11 Disabled
0
NRZ
0
Disabled
"15 Maximum Number of Retries
CRC Appended to Frame
0
Disabled (Valid Only in New Modes)
0
Bytes
"7
1
Disabled
0
Address Filter On
No Padding
0
"512 Bit Times
0
Discards Bad Frames
Disabled
0
"6
0
1
0
0
1
0
0
1
"0
0
0
0
0
"0
"0
0
8
0
"96
"0

o

I

NOTES:
1. This configuration setup is compatible with the IEEE 802.3 specification.
2. The Asterisk ..... signifies a new configuration parameter not available in the 825.86.
3. The default value of the Auto retransmit configuration parameter is enabled (1).
4. Double Asterisk ...... signifies IEEE 802.~ requirements.

I

1-177

infel~

82596DX/SX

MULTICAST-SETUP
This command is used to load the 82596 with the Multicast-IDs that should be accepted. As noted previously,
the filtering done on. the Multicast-IDs is not perfect and some unwanted frames may be accepted. This
command resets the current filter and reloads it with the specified Multicast-IDs. The format of the Multicastaddresses setup command is:
31
ELI S II I X

ODD WORD
X

X

X

X

X

X

MCCOUNT

xlxl

EVEN WORD

1615
X

X

xlo

1

1 C I B lOKI A 10

0

A15

0

00

0
0

0

0

0

0

0

LINK OFFSET

0
AO

4th byte

1st byte
MULTICAST ArRESSES LIST

-

Nth byte

Figure 26. MCSetup-82586 and 32-Bit Segmented Modes
31
ELI S II 10

ODD WORD

0

0

0

0

A31

0

1615

0

EVEN WORD

0 0 0 01 0 1 1 I C I B lOKI A I 0 0 0 0

o

0

0

0

0

LINK ADDRESS

2nd byte

1st byte I X I X I

0

0

0
AO

MCCOUNT

MULTICAST ArRESSES LIST
Nth byte

Figure 27. MC Setup-Linear Mode
where:,
LINK ADDRESS,
EL, B, C,I, S

-

As per standard Command Block (see the NOP command for details)

A

-

Indicates that the command was abnormally terminated due to a CU Abort control
command. If one, then, the command was aborted and if necessary it should be
repeated. If this bit is zero, the command was n()t aborted.

Bits 19-28

-

Reserved (0 in both the 32-Bit Segmented and Linear Modes).

CMD (bits 16-18)

-

The MC SETUP command value: 3h.

MC-CNT

MC LIST

This 14-bit field indicates the number of bytes in the MC LIST field. The MC CNT
must be a multiple of the ADDR LEN; otherwise, the 82596 reduces the MC CNT to
the nearest ADDR LEN multiple. MC CNT = 0 implies resetting the Hash table
which is equivalent to disabling the Multicast filtering mechanism.
-

A list of Multicast Addresses to be accepted by the 82596. The least significant bit
of each MCaddress must be 1.

NOTE:
The list is sequential; i.e., the most significant byte of an address is immediately followed by the least signifi'
.
cant byte of the next address.
-

When the 82596 is configured to recognize multiple Individual Address (Multi-IA),
the MC-Setup command is also used to set up the Hash table for the individual
address.
The least significant bit in the first byte of each IA address must be O.

1-178

I

82596DX/SX

TRANSMIT
This command is used to transmit a frame of user data onto the serial link. The format of a Transmit command
is as follows.
31

ODD WORD

16 15

ELI S II I X X X X X X X X
A15

X X 11

0

TBD OFFSET

0

C IBI

AO A15

4th byte

EVEN WORD

0
MAXCOLL

STATUS BITS

I
LINK OFFSET

DESTINATION ADDRESS
LENGTH FIELD

0
AO 4

1st by1e 8

6th byte

12

Figure 28. TRANSMIT-82586 Mode

31

ODD WORD

16 15

ELlsl 1i010101010101010INClsFI1
A15

0

TBD OFFSET

000

o

0

0

0

0

0

0

0

C I BI

AO A15
0

0

o

0

o

EVEN WORD
MAXCOLL

I
LINK OFFSET

0 EOFlol

4th byte

0

STATUS BITS

TCB COUNT

DESTINATION ADDRESS
LENGTH FIELD

0
AO 4

8
1st byte 12

6th byte

16

OPTIONAL DATA

Figure 29. TRANSMIT-'-32-Bit Segmented Mode

31

ODD WORD

16 15

E~sllJoJoJololoJolol0lNclsFl1
A31

0

EVEN WORD
STATUS BITS

0
I

000

0

0

0

0

o

0

0

000

0 EOFI 0 I
DESTINATION ADDRESS

LENGTH FIELD

MAXCOLL

0
AO 4

TRANSMIT BUFFER DESCRIPTOR ADDRESS
0

4th byte
20

C IBI

LINK ADDRESS

A31
o

o

AO 8
TCB COUNT

12
1st by1e 16

6th by1e
OPTIONAL DATA

Figure 30. TRANSMIT-Linear Mode

31

COMMAND WORD

16

IELI S II 10 I 0 I 0 I 0 I 0 I 0 10 I 0 INClsFI1

t t
0: No CRC Insertion disable; when the 0: Simplified Mode, all the Tx data is in
configure Command is configured to
the Transmit Command Block. The
not insert the CRC during
Transmit Buffer Descriptor Address
transmission the NC has no effect.
field is .all 1s.
1: No CRC Insertion enable; when the 1: Flexible Mode. Data is in the TCB and
in a linked lislof TBDs.
configure command is configured to.
insert the CRC during transmission
the CRC will not be inserted when
NC = 1.

I

1-179

82596DX/SX

where:
EL, B, C, I, S
OK (Bit 13)

-

Error free completion.

A (Bit 12)

-

Indicates that the command was abnormally terminated due to CU· Abort control
command. If 1, then the command was aborted, and if necessary it should be
repeated. If this bit is 0, the command was not aborted.

Bits 19-28
CMD (Bits 16-18)

-

Reserved (0 in the 32-bit Segmented and Linear modes).
The transmit command: 4h.

As per standard Command Block (see the NOP command for details).

Status Bit 11

-

Late collision. A late collision (a collision after the slot time is elapsed) is detected.

Status Bit 10

-

No Carrier Sense signal during transmission. Carrier Sense signal is monitored
from the end of Preamble transmission until the end of the Frame Check Sequence
for TONOCRS= 1 (Transmit On No Carrier Sense mode) it indicates that transmission has been executed despite a lack of CRS. For TONOCRS = 0 (Ethernet
mode), this bit also indicates unsuccessful transmission (transmission stopped
when lack of Carrier Sense has been detected).

Status Bit 9

-

Transmission unsuccessful (stopped) due to Loss of C,TS.

Status Bit 8

-

Transmission unsuccessful (stopped) due to DMA Underrun; i.e., the system did
not supply data for transmission.

Status Bit 7

-

Transmission Deferred, i.e., transmission was not immediate due to previous link
activity.

Status Bit 6

-

Heartbeat Indicator, Indicates that after a previously performed transmission, and
before the most recently performed transmission, (Interframe Spacing) the CDT
signal was monitored as active. This indicates that the Ethernet Transceiver Collision Detect logic is performing properly. The Heartbeat is monitored during the
Interframe Spacing period.

Status Bit 5

-

Transmission attempt was stopped because the number of collisions exceeded the
maximum allowable number of retries.

Status Bit 4

-

0 (Reserved).

MAX-COL
(Bits 3-0)

-

The number of Collisions experienced during this frame. Max Col = 0 plus S5 = 1
indicates 16 collisions.
s~andard

LINK OFFSET

-

As per

TBD POINTER

-

In the 82586 and 32-bit Segmented modes this is the offset of the first Tx Buffer
Descriptor containing the data to be transmitted. In the Linear mode this is the 32bit address of the first Tx Buffer Descriptor on the list. If the TBD POINTER is all 1s
it indicates that no TBD is used.

DEST ADDRESS

-

Contains .the Destination Address of the frame. The least significant bit (MC) indicates the address type.

Command Block (see the Nap for details).

MC = 0: Individual Address.
MC = 1: Multicast or Broadcast Address.
If the Destination Address bits are all 1s this is a Broadcast Address.
LENGTH FIELD

-

The contents of this 2-byte field are user defined. In 802.3 it contains the length of
the data field. It is placed in memory in the same order it is transmitted; i.e., most
significant byte first, least significant byte second.

TCBCOUNT

-

This 14-bit counter indicates the number of bytes that will be transmitted from the
Transmit Command Block, starting from the third byte after the TCB COUNT field
(address n+ 12 in the 32-bit Segmented mode, N+ 16 in the Linear mode). The
TCB COUNT field can be any number of bytes (including an odd byte), this allows
the user to transmit a frame with a header having an odd number of bytes. The
TCB COUNT field is not used in the 82586 mode.

EOF Bit

-

Indicates that the whole frame is kept in the Transmit Command Block. In the
Simplified memory model it must be always asserted.

1-180

I

82596DX/SX
The interpretation of what is transmitted depends on the No Source Address insertion configuration bit and the
memory model being used.
NOTES

1. The Destination Address and the Length Field are sequential of the Length Field immediately follows the
most significant byte ofthe Destination Address.
2. In case the 82596 is configured with No Source Address insertion bit equal to 0, the 82596 inserts its
configured Source Address in the transmitted frame.
• ,In the 82586 mode, or when the Simplified memory model is used, the Destination and Length fields of the
transmitted frame are taken from the Transmit Command Block.
• If the FLEXIBLE memory model is used, the Destination and Length fields of the transmitted frame can be
found either in the TCB or TBD, depending on the TCB COUNT.
3. If the 82596 is configured with the Address/Length Field Location equal to 1, the 82596 does not insert its
configured Source Address in the transmitted frame. The first (2 x Address Length) +2 bytes of the
transmitted frame are interpreted as Destination Address, Source Address, and Length fields respectively.
The location of the first transmitted byte depends on the operational mode of the 82596:
• In the 82586 mode, it is always the first byte of the first Tx Buffer.
• In both the 32-bit Segmented and Linear modes it depends o~ the SF bit and TCB COUNT:
-

In the Simplified memory mode the first transmitted byte is always the third byte after the TCB COUNT
field.

-

In the Flexible mode, if the TCB COUNT is greater than 0 then it is the third byte after the TCB COUNT
field. If TCB COUNT equals 0 then it is first byte of the first Tx Buffer.

• Transmit frames shorter than six bytes are invalid. The transmission will be aborted (only in 82586 mode)
because of a DMA Underrun.
4. Frames which are aborted during transmission are jammed. Such an interruption of transmission can be
caused by any reason indicated by any of the status bits 8, 9, 10 and 12.
JAMMING RULES

1. Jamming will not start before completion of preamble transmission.
2. Collisions detected during transmission of the last 11 bits will not result in jamming.
The format of a Transmit Buffer Descriptor is:
82586 Mode
31

ODD WORD

1615

NEXT TBD OFFSET

I
Ix X X X X X X xl

31

EVEN WORD

0

SIZE (ACT COUNT)

0

4

TRANSMIT BUFFER ADDRESS

32-81t Segmented Mode
1615
13

ODD WORD
NEXT TBD OFFSET

I

13

IEOFI X I

EVEN WORD

0

SIZE (ACT COUNT)

IEOFI 0 I

0

4

TRANSMIT BUFFER ADDRESS

I

Linear Mode
31
0 o 0 0 0

ODD WORD
0 o 010

0

1615
0 000

13

o 0 IEOFI 0 I

EVEN WORD
SIZE (ACT COUNn

0
0

NEXT TBD ADDRESS

4

TRANSMIT BUFFER ADDRESS

8

Figure 31

I

1-181

82596DX/SX

where:
EOF

-

This bit indicates that this TBD is the last one associated with the frame being
transmitted. It is set by the CPU before transmit.

SIZE (ACT COUNT)

-

This 14-bit quantity specifies the number of bytes that hold information for the
current buffer. It is set by' the CPU before transmission.

NEXT TBD ADDRESS -

In the 82586 and 32-bit Segmented modes; it is the offset of the next TBD on the
list. In the Linear mode this is the 32-bit address of the next TBD on the list. It is
meaningless if EOF = 1.

BUFFER ADDRESS

The starting address of the memory area that contains the data to be sent. In the
82586 mode, this is a 24-bit address (A31-A24 are considered to be zero). In the
32-bit Segmented and Linear modes this is a 32-bit address. This buffer can be
byte aligned for the 82596 B-step.

-

TOR

. This operation activates Time Domain Reflectometry, which is a mechanism to detect open or short circuits on
the link and their distance from the diagnosing station. The TOR command has no parameters. The TOR
transmit sequence was changed, compared to the 82586, to form a regular transmission. The TOR command
is designed to be used statically. Make sure that both the CU and RU are idle before attempting a TOR
command. The TOR bit stream is as follows.
-

Preamble

-

Source address

-

Another Source address (the TOR frame is transmitted back to the sending station,
.
so DEST ADR = SRC ADR).

-

Data field containing 7Eh patterns.

-

Jam Pattern, which is the inverse CRC of the transmitted frame.

Maximum length of the TOR frame is 2048 bits. If the 82596 senses collision while transmitting the TOR frame
it transmits the jam pattern and stops the transmission. The 82596 then triggers an internal timer (STC); the
timer is reset at the beginning of transmission and reset if CRS is returned. The timer measures the time
elapsed from the start of transmission until an echo is returned. The echo is indicated by Collision Detect going
active or a drop in the Carrier Sense signal. The following table lists the possible cases that the 82596 is able
to analyze.
Conditions of TOR as Interpreted by the 82596
Transceiver Type
Condition

Carrier Sense was inactive for 2048-bit-time
periods

Ethernet

Short or Open on the
Transceiver Cable

Non Ethernet

NA

Carrier Sense signal dropped

Short on the Ethernet cable

NA

Collision Detect went active

Open on the Ethernet cable

Open on the Serial Link

The Carrier Sense Signal did not drop or the
Collision Detect did not go active within
2048-bit time period

No Problem

No Problem

An Ethernet transceiver is defined as one that returns transmitted data on the receive pair and activates the
Carrier Sense Signal while transmitting. A Non-Ethernet Transceiver is defined as one that does not do so.

1-182

I

82596DX/SX

The format of the Time Domain Reflectometer command is:

82586 and 32-Blt Segmented Modes
31

ODD WORD

EL

S

I

X

1615

X X X X X X X X xll

LNK XVR ET
ETrl X
OK PRS OPN SRT

I

31

ODDWORD

o

TIME
(11 bits)

0

EVEN WORD

0 o 0 000 0 000 0 0

1 cis lOKI 0
A15

LINK OFFSET

AO

Linear Mode
ELI S 1110

0

o

0

0

0

0

1615

0

0

011

A31

0

0

llc

0

EVEN WORD
sloKlo

0

o

0

0

0

0

000

0

LINK ADDRESS

000

o

0

000

o

0

0

0

0

0

0

I I I I II
LNK
OK

XVR
PRS

ET
OPN

ET
SRT

X

0

0
AO

TIME
(11 bits)

Figure 32. TOR
where:
LINK ADDRESS,
EL, B, C,I, S

-

As per standard Command Block (see the NOP command for details).

A

-

Indicates that the command was abnormally terminated due to CU Abort control
command. If one, then the command was aborted, and if necessary it should be
repeated. If this bit is zero, the command was not aborted.

Bits 19-28
CMD (Bits 16-18)

-

Reserved (0 in the ,32-bit Segmented and Linear Modes).

-

The TDR command. Value: 5h.

TIME

, - An 11·bit field that specifies the number of TxC cycles that elapsed before an echo
was observed. No echo is indicated by a reception consisting of "1 s" only. Because the network contains various elements such as transceiver links, transceivers, Ethernet, repeaters etc., the TIME is not exactly proportional to the problems
distance.

LNK OK (Bit 15)

-

XCVR PRB (Bit 14)

-'- Indicates a Transceiver problem. Carrier Sense was inactive for 2048-bit time period. LNK OK = O. TIME = 7FFh.

ET OPN (Bit 13)

-

The transmission line is not properly terminated. Collision Detect went active' and
LNK OK=O.

ET SRT (Bit 12)

-

There is a short circuit on the transmission line. Carrier Sense Signal dropped and
LNK OK=O.

I

No link problem identified. TIME = 7FFh.

1-183

82596DX/SX

DUMP
This command causes the contents of various 82596 registers to be placed in a memory area specified by the
user. It is supplied as a 82596 self-diagnostic tool, and to provide registers of interest to the user. The format
of the DUMP command is:
.
82586 and 32-8it Segmented Modes
31
IELI S II

ODD WORD

JX

x

x

x

X X

X

X 11

1

BUFFER OFFSET

IA15

EVEN WORD

1615
X X

oj c I SIOKI 0

0

0

0

0

0

0
0

0

0

0

0

0

LINK OFFSET

AoIA15

01
Aol

Linear Mode
31
ELI S II I X

ODD WORD
X

X X

X X

X

16 15
X

X

X 11

1

ole I slOKI 0

EVEN WORD
0

0

0

0

0

0
0

0

0

0

0

0

0

A31

LINK ADDRESS

AO

A31

BUFFER ADDRESS

AO

Figure 33. Dump
where:
LINK ADDRESS,
EL, B,C,I,S

-

Asper standard Command Block (see the NOP command for details).

OK

-

Indicates error free completion.

Bits 19-28
CMD (Bits 16-18)

-

Reserved (0 in the 32-bit Segmented and Linear Modes).

-

The Dump command. Value: 6h.

BUFFER POINTER·

-

In the 82586 and 32-bit Segmented modes this is the 16-bit-offset portion of the
dump area address. In the Linear mode this is the 32~bit linear address of the dump
area.

Dump Area Information Format
• The 82596 is not Dump compatible with the 82586 because of the 32-bit internal architecture. in 82586
mode the 82596 will dump the same number of bytes as the 82586. The compatible data will be marked
with an asterisk.
• In 82586 mode the dump area is 170 bytes.
• The dump area format of the. 32-bit Segmented and Linear modes is described in Figure 35.
• The size of the dump area of the 32-bit Segmented and Linear modes is 304 bytes.
• When the dump is executed by the Port command an extra word will be appended to the Dump Area. The
extra word is a copy of the Dump Area status word (containing the C, B, and OK bits). The C and OK bits
are set when the 82596 has completed the Port Dump command.

1-184

I

82596DX/SX

15 14 13 12

11

10

9

765432

o

DMA CONTROL REGISTER'

00

CONFIGURE BYTES 3. 2

02

CONFIGURE BYTES 5, 4

04

CONFIGURE BYTES 7. 6

06

CONFIGURE BYTES 9, 8

08

CONFIGURE BYTES 10

OA

LA. BYTES 1, 0'
LA. BYTES 3, 2'

OC
OE

LA. BYTES 5, 4'

10

LASTT.X. STATUS'

12

T.X. CRC BYTES 1, 0'

14

T.X. CRC BYTES 3, 2'

16

R.X. CRC BYTES 1, 0'

18

R.X. CRC BYTES 3, 2'

1A

R.X. TEMP MEMORY 1, 0'

1C

R.X. TEMP MEMORY 3, 2'

1E

R.X. TEMP MEMORY 5, 4'

20

LAST RECEIVED STATUS'

22

HASH REGISTER BYTES 1, 0'

24

HASH REGISTER BYTES 3, 2'

26

HASH REGISTER BYTES 5, 4'

28
2A
2C

HASH REGISTER BYTES 7, 6'
SLOT TIME COUNTER'
WAIT TIME COUNTER'

2E

MICRO MACHINE"

30

NOTE:
'The 82596 is not Dump compatible
with the 82586 because of the 32-bit
internal architecture. In 82586 mode
the 82596 will dump the same number
of bytes as the 82586. The compatible data will be marked with an asterisk.
"These bytes are not user defined,
results may vary from Dump command to Dump command.

REGISTER FILE
60 BYTES

6A

MICRO MACHINE LFSR"

6C

MICRO MACHINE

6E

FLAG ARRAY
14 BYTES

7A

QUEUE MEMORY"

7C

CUPORT
8 BYTES
MICRO MACHINE ALU"
RESERVED"
M.M. TEMP A ROTATE R"

82
84
86
88

M.M. TEMP A"

8A

T.X. DMA BYTE COUNT"

8C

M.M. INPUT PORT ADDRESS"

8E

T.X. DMA ADDRESS"

R.X. DMAADDRESS"

90
92
94
96
98

M.M. OUTPUT PORT"
R.X. DMA BYTE COUNT"
M.M. OUTPUT PORT ADDRESS REGISTER"
RESERVED"

9A

BUS THROTTLE TIMERS

9C

DIU CONTROL REGISTER"

9E

RESERVED"

AO

DMA CONTROL REGISTER"

A2

. BIU CONTROL REGISTER"

A4

M.M. DISPATCHER REGISTER"

AS

M.M. STATUS REGISTER"

A8

Figure 34. Dump Area Format-82586 Mode

I

1-185

82596DX/SX

o

31
CONFIGURE; BYTES 5, 4, 3, 2

00

CONFIGURE BYTES 9,8,7,6

04

CONFIGURE BYTES 13, 12, 11, 10
I.A. BYTES 1,0

X

X

X

X

08
X

X

X

'I.A. BYTES 5, 2

X

OC
10

TX CRC BYTES 0, 1

LAST T.X. STATUS

RX CRC BYTES 0, 1

TX CRC BYTES 3, 2

18

RX TEMP MEMORY 1, 0

RX CRC BYTES 3, 2

1C

R.X. TEMP MEMORY 5, 2
HASH REGISTERS 1, 0

14

NOTE:
The 82596 is not Dump compatible
with the 82586 because of the 32-bit
internal architecture. 'In 82586 mode
the 82596 will dump the same number
of bytes as the' 82586. The compatible data will be marked with an asterisk.
"These bytes are not user defined,
results may vary from Dump command to Dump command.

20

LAST R.X. STATUS

HASH REGISTER BYTES 5, 2

24
28

SLOT TIME COUNTER

HASH REGISTERS 7, 6

2C

RECEIVE FRAME LENGTH

WAIT-TIME COUNTER

30
34

MICRO MACHINE"
REGISTER FILE
128 BYTES

BO

MICRO MACHINE LFSR"

B4

MICRO Mi\CHINE"

B8

FLAG ARRAY
28 BYTES

DO

M.M. INPUT PORT"
16 BYTES

D4

MICRO MACHINE ALU"

E4

RESERVED"

E8

M.M. TEMP A ROTATE R."

EC

EO

M.M. TEMP A"

FO

T.X. DMA BYTE COUNT"

F4

M.M. INPUT PORT ADDf'lESS REGISTER"

F8

T.X. DMA ADDRESS"

FC

M.M. OUTPUT PORT REGISTER"

100

R.X. DMA BYTE COUNT"

104

M.M, OUTPUT PORT ADDRESS REGISTER"

108

R.X. DMA ADDRESS REGISTER"

10C

RESERVED"

110

BUS THROTILE TIMERS

114

DIU CONTROL REGISTER"

118

RESERVED"

11C

DMA CONTROL REGISTER"

120

BIU CONTROL REGISTER"
M.M. DISPATCHER REG."
M.M. STATUS REGISTER"

124,
,

128

12C

'Figure 35_ Dump Area Format-Linear and,32-Blt Segmented Mode

1-186

I

82596DX/SX

DIAGNOSE

The Diagnose Command triggers an internal self-test procedure that checks internal 82596 hardware, which
includes:
• Exponential Backoff Random Number Generator (Linear Feedback Shift Register).
• Exponential Backoff Timeout Counter.
• Slot Time Period Counter.
• Collision Number Counter.
• Exponential Backoff Shift Register.
• Exponential Backoff Mask Logic.
• Timer Trigger Logic.
This procedure checks the operation of the Backoff block, which resides in the serial side and is not easily
controlled. The Diagnose command is performed in two phases.
The format of the 82596 Diagnose command is:
82586 and 32-Bit Segmented Modes
1615

ODD WORD

0

EVEN WORD

X X X X X X X X X X

0

X X X X X X X X X X

0

0

0

0

0

0

0

0

0

AD

LINK OFFSET

Linear Mode
ODD WORD

0

0

0

0

0

EVEN WORD

0

0

0

0

0

0

0

0

0

0

0

LINK ADDRESS

0

0

0
AO

Figure 36. Diagnose

where:
LINK ADDRESS,
EL, B, C, I, S

-

As per standard Command Block (see the NOP command for details).

Bits 19-28

-

Reserved (0 in the 32-bit Segmented and Linear Modes).

CMD (bits 16-18)

-

The Diagnose command. Value: 7h.

OK (bit 13)

-

Indicates error free completion.

F (bit 11)

-

Indicates that the self-test procedure has failed.

RECEIVE FRAME DESCRIPTOR
Each received frame is described by one Receive Frame Descriptor (see Figure 37). Two new memory
structures are available for the received frames. The structures are available only in the Linear and 32-bit
Segmented modes.

I

1-187

82596DX/SX

L
r--

...

SCB

RECEIVE FRAt.lE AREA
RFD 1

RFA
POINTER

--

,

y

I

-

STATISTICS

Y

STATUS

STATUS

I--

TO
COt.lt.lAND
BLOCK
LIST

RECEIVE
FRAt.lE
DESCRIPTORS

VALID
PARAf.lETERS

L

RECEIVE
BUFFERS

RBD2

RBDl

OIACT-:Lr
RECEIVE
BUFFER
DESCRIPTORS

Et.lPTY

1

I ACT-cnt

- lr

,

,

J--

~

VALID
DATA

VALID
DATA

'--

'--

BUFFER 1

BUFFER 2

I+-- RECEIVE FRAt.lE LIST

I

-r

STATUS

Et.lPTY

Et.lPTY

RBDS

01

ACT-cnt

-y

STATUS

RBD4

~

----

BUFFER 3

01

RBD5

-LJ

ACT-cnt

,

01

-S

ACT-cnt

t

~

~

-

-

BUFFER 4

BUFFER 5

FREE FRAt.lE LIST

290219-15

Figure 37. The Receive Frame Area

Simplified Memory Structure
The first is the Simplified memory structure, the data section of the received frame is part of the RFD and is
located immediately after the Length Field. Receive Buffer Descriptors are not used with the Simplified structure, it is primarily used to make programming easier. If the length of the data area described in the Size Field
is smaller than the incoming frame, the following happens.
1. The received frame is truncated.
2. The No Resource error counter is updated.
3. If the 82596 is configured to Save Bad Frames the RFD is not reused; otherwise, the same RFD is used to
hold the next received frame, and the only action taken regarding the truncated frame is to update the
counter.
4. The 82596 continues to receive the next frame in the next RFD.

1·188

I

82596DX/SX

Note that this sequence is very useful for monitoring. If the 82596 is configured to Save Bad Frames, to
receive in Promiscuous mode, and to use the Simplified memory structure, any programmed length of received
data can be saved in memory.
The Simplified memory structure is shown in Figure 38.

SCB

Y

STATUS
CBl
POINTER

TO COMMAND liST
RECEIVE FRAME AREA

'4

---,

RFA
POINTER

FDl
STATUS

STATISTICS
I
I
I

BUS
THROTIlE

FD2

.------_.
VARIABLE
DATA
FIELD

:+-,

I
I
I

I
I
I

,
,,
,
._----_.
....------

RECEIVE FRAME liST ----t~~:4

,
,,
I
I

FD4

STATUS

STATUS

-Lr -lJ -r:

STATUS

I

I
I
I

RECEIVE
FRAME
DESCRIPTORS

~

FD3

EMPTY

I

I
I

"

,,,

I
I

EMPTY

,,

,,
,,
,
I

I
I

,,
,
,,,

EMPTY

I
I
I
I

,
I
I

,

._----- . ._----_ .
FREE FRAME LIST --------I~~,

290219-16

Figure 3S. RFA Simplified Memory Structure

Flexible Memory Structure
The second structure is the Flexible memory structure,.the data structure of the received frame is stored in
both the RFD and in a linked list of Receive Buffers-Receive Buffer Descriptors. The received frame is placed
in the RFD as configured in the Siz~ field. Any remaining data is placed in a linked list of RBDs.
The Flexible memory structure is shown in Figure 39.

I

1-189

82596DX/SX

Buffers on the receive side can be different lengths. The 82596 will not place more bytes into a buffer than
indicated in the associated RBD. The 82596 will fetch the next RBD before it is needed. The 82596 will
attempt to receive frames as long as the FBL is not exhausted. If there are no more buffers, the 82596
Receive Unit will enter the No Resources state. Before starting the RU, the CPU must place the FBL pOinter in
the RBD pointer field of the first RFD. All remaining RBD pointer fields for subsequent RFDs should be "1s." If
the Receive Frame Descriptor and the associated Receive Buffers are not reused (e.g., the frame is properly
received or the 82596 is configured to Save Bad Frames), the 82596 writes the address of the next free RBD
to the RBD pointer field of the next RFD.
RECEIVE BUFFER DESCRIPTOR (RBD)
The RBDs are used to store received data in a flexible set of linked buffers. The portion of the frame's data
field that is outside the RFD is placed in a set of buffers chained by a sequence of RBDs. The RFD points to
the first RBD, and the last RBD is flagged with an EOF bit set to 1. Each buffer in the linked list of buffers
related to a particular frame can be any size up to 214 bytes but must be word aligned (begin on an even
numbered byte). This ensures optimum use of the memory resources while maintaining low overhead. All
buffers in a frame are filled with the received data except for the last, in which the actual count can be smaller
than the allocated ,buffer space.

SCB

TO

CO~~AND

LIST

,~

STATUS

RECEIVE

FRA~E

AREA

I

CBl
POINTER

FDl

RFA
POINTER

FD2

STATISTICS
BUS
THROTTLE

FD3

FD4

.~

STATUS

CONTROL
FIELD

._-----_.

RECEIVE

VARIABLE
DATA
FIELD

FRA~E

DESCRIPTORS

E~PTY

E~PTY

E~PTY

. _----_.

.---'- -_..

E~PTY

E~PTY

._----_ ..

RECEIVE
BUFFER
DESCRIPTORS

VALID
DATA

RECEIVE
BUFFERS
:

BUFFER 1

:+--

RECEIVE

BUFFER 2

FRA~E

LIST

I

BUFFER 3

-----!.~~:.~~-------

E~PTY

BUFFER 4
FREE

FRA~E

BUFFER 5

LIST - - - - - - -.....:

290219-17

Figure 39. RFA Flexible Memory Structure

1-190

I

inteL

82596DX/SX

31

ODD WORD

ELI S I x

x

x

x

A15

x

x

x

x

16 15
x

x

x

x

x

RBDOFFSET

x

C I B lOKI 0 I

AO A15

4th byte

0

EVEN WORD
STATUS BITS

10

0

LINK OFFSET

DESTINATION ADDRESS

0

0

0

o 0
AO 4

1st byte 8

1st byte 6th byte

SOURCE ADDRESS
6th byte

12

4th byte

X X X X X X X X X X X X X X X X

16
LENGTH FIELD

20

Figure 40. Receive Frame Descriptor-82586 Mode
ODD WORD

31
ELI S 10

o

0

0

0

000

1615
0

oJSFlo

0

RBDOFFSET

A15

010 I

0

AO A15

SIZE

EVEN WORD

LINK OFFSET

8
1st byte 12

DESTINATION ADDRESS

SOURCE ADDRESS

0
AO 4

ACTUAL COUNT

EOFI FI

4th byte

0

STATUS BITS

C I B lOKI

1st byte 6th byte

16

4th byte

20

6th byte

LENGTH FIELD

24

OPTIONAL DATA AREA

Figure 41. Receive Frame Descriptor-32-8it Segmented Mode
31

1615

ODD WORD

ELI S 10

0

0

000

0

0

A31

o ISFI 0

0

0

6th byte

STATUS BITS

EOFI FI

o
AO 8

ACTUAL COUNT

DESTINATION ADDRESS
1st byte

o
AO 4

RECEIVE BUFFER DESCRIPTOR ADDRESS
SIZE

4th byte
SOURCE ADDRESS

EVEN WORD

C I BloKI

LINK ADDRESS

A31
0101

0

12
1st byte 16
20

6th byte

24

4th byte
LENGTH FIELD

28

OPTIONAL DATA AREA

Figure 42. Receive Frame Descriptor-Linear Mode

I

1-191

intel~

82596DX/SX

where:

S

- When set, this bit indicates that this RFD is the last one on the RDL.
- When set, this bit suspends the RU after receiving the frame.

SF

-

EL

This bit selects between the Simplified or the Flexible mode.
0- Simplified mode, all the RX data is in the RFD. RBD ADDRESS field is all
"18."

1-

C

B

OK (bit 13)

STATUS

Flexible mode. Data is in the RFD and in a linked list of Receive Buffer Descriptors.
- This bit indicates the completion of frame reception. It is set by the 82596.
- This bit indicates that the 82596 is currently receiving this frame, or that the 82596
is ready to receive the frame. It is initially set to 0 by the CPU. The 82596 sets it to
1 when reception set up begins, and to 0 upon completion. The C and B bits are
set during the same operation.
- Frame received successfully, without errors. RFDs with bit 13 equal to 0 are possible only if the save bad frames configuration option is selected. Otherwise all
frames with errors will be discarded, although statistics will be collected on them.
- The results of the Receive operation. Defined bits are,
Bit 12:
Bit 11:
Bit 10:

Length error if configured to check length
CRC error in an aligned frame
Alignment error (CRC error in misaligned frame)

Bit 9:

Ran out of buffer space-no resources

Bit 8:

DMA Overrun failure to acquire the system bus.

Bit 7:
Bit 6:

Frame too short.
No EOP flag (for Bit stuffing only)

Bit 5:

When the SF bit equals zero, and the 82596 is configured to save bad
frames, this bit signals that the received frame was truncated. Otherwise
it is zero.
Bits 2-4: Zeros
Bit 1:

LINK ADDRESS
RBDPOINTER
EOF
F
SIZE
ACT COUNT
MC
DESTINATION
ADDRESS
SOURCE ADDRESS

1-192

When it is zero, the destination address· of the received frame matches
the IA address. When it is 1, the destination address of the received
frame does not match the individual address. For example, a multicast
address or broadcast address will set this bit to a 1.
Bit 0:
Receive collision. A collision is detected during reception, and the collision occurred after the destination address was received.
- A 16-bit offset (32-bit address in the Linear mode) to the next Receive Frame
Descriptor. The Link Address of the last frame can be used to form.a cyclical list.
- The offset (address in the Linear mode) of the first RBD containing the received
frame data. An RBD pointer of all ones indicates no RBD.
- These fields are for the Simplified and Flexible memory models. They are exactly
the same as the respective fields in the Receive Buffer Descriptor. See the next
section for detailed explanation of their functions.
- Multicast bit.
- The contents of the destination address of the receive frame. The field is 0 to 6
bytes long.
- The contents of the Source Address field of the received frame. It is 0 to 6 bytes
long.

I

82596DX/SX

LENGTH FIELD

-

The contents of this 2-byte field are user defined. In 802.3 it contains the length of
the data field. It is placed in memory in the same order it is received, i.e., most
significant byte first, least significant byte second.

NOTES
1. The Destination address, Source address and Length fields are packed, i.e., one field immediately follows
the next.
2. The affect of Address/Length Location (No Source Address Insertion) configuration parameter while receiving is as follows:

-

82586 Mode: The Destination address, Source address and Length field are not used, they are placed in
the RX data buffers.

-

32-Bit Segmented and Linear Modes: when the Simplified memory model is used, the Destination address,
Source address and Length fields reside in their respective fields in the RFD. When the Flexible memory
strucrture is used the Destination address, Source address, and Length field locations depend on the SIZE
field of the RFD. They can be placed in the RFD, in the RX data buffers, or partially in the RFD and the rest
in the RX data buffers, depending on the SIZE field value.
82586 Mode
31

ODD WORD

A15

16 15

NEXT RBD OFFSET

X

X

X

X

X

X

X

X IA23

X

X

X

X

X

X

X

X

X

EVEN WORD

RECEIVE BUFFER ADDRESS
X

X

X

X

X

X

0
0

ACTUAL COUNT

AolEOFI F I

AO 4
6

SIZE

X I EL I X I

32-Blt Segmented Mode
31

ODD WORD

A15

16 15

NEXT RBD OFFSET

A31

0

EVEN WORD

RECEIVE BUFFER ADDRESS

0

0

0

0

0

0

0

0

0

0

0

0

0

0

01 EL I

0
0

ACTUAL COUNT

AolEOFI F I

AO 4

pi

6

SIZE

Linear Mode
31

0

ODD WORD

000

0

0

o

0

0

0

0

0

A31

0

0

OIEOFI FI

ACTUAL COUNT

NEXT RBD ADDRESS

A31

0

EVEN WORD

1615

0

0

0

0

0

o

0

0

00

0

0

0

0

01 EL I

pi

0
AO 4
AO 6

RECEIVE BUFFER ADDRESS

0

0

SIZE

Figure 43. Receive Buffer Descriptor

I

1-193

82596DX/SX

where:
EOF

-

F

-:- Indicates that this buffer has already been used. The Actual Count has no meaning
unless the F bit equals one. This bit is cleared by the CPU before starting the RU,
and is set by the 82596 after the associated buffer has been. This bit has the same
meaning as the Complete bit iii the RFD and CB .

ACT COUNT

.-

This 14-bit quantity indicates the number of meaningful bytes in the buff~r. It is
cleared by the CPU before starting the RU, and is written by the 82596 after the
associated buffer has already been used. In general, after the buffer is full, the
.Actual Count value equals the size field of the same buffer. For the last buffer of
. 'the frame, Actual Count can be less thim the buffer size.

NEXT BO ADDRESS

-

The offset(absolute address in the Linear mode) of the next RBD on the list. It is
meaningless ifE[= 1:
.

BUFFER ADDRESS.

-

The starting address of the memory area that contains the received data. In the
82586 mode, this is a 24-bit address (with pins A24-A31 =0). In the 32-bit Segmented and Linear modes this is a 32-bit address.

EL

-

Indicates that the buffer associated with this RBD is last in the FBL.

P

This bit indicates that the 82596 has already prefetched the RBDs and any change
in the RBD data will be ignored. This bit is valid only in the new 82596 memory
modes, and if this feature has been enabled during configure command. The
82596 Prefetches the RBDs in locked cycles; after prefetching the RBD the 82596
performs a write cycle where the P bit is set to one and the rest of the data remains
unchanged. The CPU is responsible for resetting it in all RBDs. The 82596 will not
check this bit before setting it.
....:. This 14-bit quantity indicates the size, in bytes, of the associated buffer. This quantity must be an even number..

SIZE

, 1-194 .

Indicates that this is the last buffer related to the frame. It is cleared by the CPU
before starting the RU;and is written by the 82596 at the end of reception of the
frame.

-

I

82596DX/SX

ELECTRICAL AND TIMING
CHARACTERISTICS

PGA PACKAGE THERMAL
SPECIFICATION
Parameter

Thermal Resistance

OJC

3°C/W

OJA

24°C/W

ABSOLUTE MAXIMUM RATINGS
Storage Temperature .......... - 65°C to + 150°C
Case Temperature under Bias ... - 65°C to + 110°C
Supply Voltage
with Respect to V55 .......... , - 0.5V to + 6.5V
Voltage on Other Pins ....... -0.5V to VCC + 0.5V

D.C. CHARACTERISTICS
Tc = O°C to + 85°C, Vcc = 5V ± 10% CLK2 and LE/BE have MOSlevels (see VMll, VMIH).
All other signals have TTL levels (see Vll, VIH, VOL, VOH)'

Symbol

I·

Parameter

Min

Max

Units

-0.3

+0.8

V

Input High Voltage (TTL)

2.0

Vcc + 0.3

V

Input Low Voltage (MOS)

-0.3

+0.8

V

VMIH

Input High Voltage (MOS)

3.7

Vcc + 0.3

V

VOL

Output Low Voltage (TTL)

0.45

V

VCll

RxC, TxC Input Low Voltage

-0.5

0.6

V

VCIH

RxC, TxC Input High Voltage

3.3

Vcc + 0.5

V

VOH

Output High Voltage (TTL)

2.4

Vil

Input Low Voltage (TTL)

VIH
VMll

V

Notes

IOl = 4.0 rnA

IOH = O.9mA-1 rnA

III

Input Leakage Current

±15

/LA

0::;; VIN ::;; VCC

ILO

Output Leakage Current

±15

/LA

0.45

CIN

Capacitance of Input Buffer

10

pF

FC = 1 MHz

COUT

Capacitance of Input/Output
Buffer

12

pF

FC = 1 MHz

CClK

CLK Capacitance

20

pF

FC = 1 MHz

Icc

Power Supply

150

rnA

At 20 MHz
for the 82596SX
Icc Typical = 90 rnA

Icc

Power Supply

200

rnA

At 25 MHz
Icc Typical = 100 rnA

Icc

Power Supply

300

rnA

At 33 MHz
ICC Typical = 150 rnA

< VOUT < Vcc

1-195

82596DX/SX

A.C. CHARACTERISTIC,S
82596DX C-STEP INPUT/OUTPUT SYSTEM TIMINGS TC

=

O°Cto +85°, Vcc

=

SV ±10%

These timings assume the CL on all outputs is SOpF unless otherwise specified. CL can be 20 pF to 120 pF,'
however, timings must be derated.·
All timing requirements are given in nanoseconds.

Symbol

25 MHz

Parameter
Operating Frequency

Notes

Min

Max

12.S MHz

2SMHz

Tl

CLK2 Period .

20

40

CLK2/2

T2

CLK2 High

4

3.7V

T3

CLK2 Low

S

0.8V

T4

CLK2 Rise Time

TS

CLK2 Fall Time

-

T13

CA and SREa Setup Time

7

1,2,3

7

0.8Vto 3.7V

.7

3.7Vto 0.8V

T14

SREa Hold Time

3

1,2,3

T14a

CA Hold Time

S

1,2,3

T26

CA and SREa, PORT Pulse Width

4 Tl

3

T2S

INT Valid Delay

1

26

T6

SEx Valid Delay

3

' 17

T6b

LOCK Valid Delay

3

21

T6c

A2-A31 Valid Delay

3

18

T7

SEx, LOCK, and A2-A31 Float Delay

4

30

T8

W/R and ADS Valid Delay

3

21
30

T9

W/R and ADS Float Delay

4

Tl0

00-031 Write Data Valid Delay

3

19

Tll

00-031 Write Data Float Delay

4

22

T27

00-031 CPU PORT Access Setup Time

7

2

T28

00-031 CPU PORT Access Hold Time

S

2

T29

PORT Setup Time

7

2

T30

PORT Hold Time

3

2

T17

ROY Setup Time

9

2

3

2

T18

, ROY Hold Time

T19

00-031 READ Setup Time

7

2

T20

00-031 READ Hold Time

S

2

T12

HOLD Valid Delay

3

T21

HLDA Setup Time

10

1,2

T22a

HLDA Hold Time

3

1,2

T23

RESET Setup Time

10

2

T24

RESET Hold Time

3

2

22

NOTE:
TImings shown are for the 82596CA C·Stepping. For information regarding timings for the 82596CA A 1 or B·Step, contact
your local Intel representative.
.

1-196

I

82596DX/SX

A.C. CHARACTERISTICS (Continued)
B2596DX C-STEP INPUT/OUTPUT SYSTEM TIMINGS Te

= O·Cto + 85·C, Vee = 5V

±5%

These timings assume the CL on all outputs is 50 pF unless otherwise specified. CL can be 20 pF to 120 pF,
however, timings must be derated.
All timing requirements are given in nanoseconds.

Symbol

Operating Frequency
T1

33 MHz

Parameter

Notes

Min

Max

12.5 MHz

33 MHz

CLK2 Period

15

40

CLK2/2

T2

CLK2 High

4.5

T3

CLK2 Low

4.5

T4

CLK2 Rise Time

T5

CLK2 Fall Time

-

T13

CA and BREQ Setup Time

7

T14

BREQ Hold Time

3

1,2,3

T14a

CAHoldTime

5

1,2,3

T26

CA and BREQ, PORT Pulse Width

T25

INTValid Delay

1

20

3.7V
0.8V
4

3.7V to 0.8V

4

0.8Vt03.7V
1,2,3

4 T1

3

T6

BEx Valid Delay

3

17

T6b

LOCK Valid Delay

3

16

T6c

A2-A31 Valid Delay

3

18
20

T7

BEx, LOCi<, and A2-A31 Float Delay

4

T8

W/R and ADS Valid Delay

3

16

T9

W/R and ADS Float Delay

4

20

T10

00-031 Write Data Valid Delay

3

19

T11

00-031. Write Data Float Delay

4

17

T27

00-031 CPU PORT Access Setup Time

5

2

T28

00-031 CPU PORT Access Hold Time

3

2

T29

PORT Setup Time

7

2

T30

PORT Hold Time

3

2

T17

ROY Setup Time

8

2

T18

ROY Hold Time

3

2

T19

00-031 READ Setup Time

5.5

2

T20

00-031 READ Hold Time

4

2

T12

HOLD Valid Delay

3

T21

HLDA Setup Time

8

1,2

T22a

HLDA Hold Time

3

1,2

T23

RESET Setup Time

9

2

T24

RESET Hold Time

3

2

19

NOTE:
Timings shown are for the 82596CA C·Stepping. For information regarding timings for the 82596CA AI or a·Step, contact
your local Intel representative.

I

1-197

82596DX/SX

A.C. CHARACTERISTICS (Continued)
82596SX C-STEP INPUTIOUTPUTSVSTEM TIMINGS T c = O°C to

+ 85°C, VCC

=

5V

± 10%

These timings assume the CL on all outputs is 50 pF unless otherwise specified. CL can be 20 pF to 120 pF,
however, timings must be derated.
.
All timing requirements are given in nanoseconds.
20 MHz

Paramet~r

Symbol

Operating Frequency

Notes

Min

Max

12.5 MHz

20 MHz

T1

CLK2 Period

25

40

T2

CLK2 High

8

at 2.OV

T3

CLK2 Low

8

at2.OV

T4

CLK2 Rise Time

-

8

0.8V to 3.7V

T5

CLK2 Fall Time

-

8

3.7V to 0.8V

T13

CA and BREQ Setup Time

10

1,2,3

T14

BREQ Hold Time

7

1,2,3

T14a

CA Hold Time

8

1,2,3

T26

CA and BREQ, PORT Pulse Width

T25

INT Valid Delay

1

35

T6

BHE, BLE, LOCK, BON, and A 1":A31
Valid Delay

3

30

T7

BHE, BLE, LOCK, BON, and A1-A31
Float Delay

4

30

T8

W/R and ADS Valid Delay

3

26

T9

W/R and ADS Float Delay

4

30

T10

DO-D15 Write Data Valid Delay

3

38
27

4 T1

,

CLK2/2

3

T11

DO- D15 Write Data Float Delay

4

T27

DO-D15 CPU PORT Access Setup Time

9

2

T28

DO-D15 CPU PORT Access Hold Time

6

2

T29

PORT Setup Time

10

2

T30

PORT Hold Time

7

2

T17

RDY Setup Time

12

2

T18

RDY Hold Time

4

2

T19

DO-D15 READ Setup Time

9

2

T20

DO-D15 READ Hold Time

5

T12

HOLD Valid Delay

3

T21

H LDA Setup Time

15

1,2

T22a

HLDA Hold Time

7

1,2

T23

RESET Setup Time

12

1,2

T24

RESET Hold Time

4

1,2

2
28

NOTE:
Timings shown are for the 82596CA C-Stepping. For information regarding timings for the 82596CA A 1 or B-Step, contact
your local Intel representative.

1-198

I

82596DX/SX

A.C. CHARACTERISTICS (Continued)
82596SX C-STEP INPUTIOUTPUT SYSTEM TIMINGS Te

= O·C to + 85·C, Vee =

5V

± 10%

These timings assume the CL on all outputs is 50 pF unless otherwise specified. CL can be 20 pF to 120 pF,
however, timings must be derated.
All timing requirements are given in nanoseconds.

Symbol

Operating Frequency

I

16MHz

Parameter

Notes

Min

Max

12.5 MHz

16 MHz
40

CLK2/2

T1

CLK2 Period

31

T2

CLK2 High

9

2.0V

T3

CLK2 Low

9

2.0y

T4

CLK2 Rise Time

-

8

0.8Vto 3.7V

T5

CLK2 Fall Time

-

8

3.7Vto 0.8V

T13

CA and BREQ Setup Time

11

1,2,3

T14

CA and BREQ Hold Time

8

1,2,3

T26

CA and BREQ, PORT Pulse Width

T25

INT Valid Delay

1

T6

BHE, BLE, BON, and A 1-A31 Valid Delay

3

36

T6b

LOCK# Valid Delay

1

33

4 T1

3
40

T7

BHE, BLE, LOCK, BON, and A1-A31 Float Delay

4

40

T8

W/R and ADS Valid Delay

1

33

T9

.W IR and ADS Float Delay

4

35

3

40
35

T10

00-015 Write Data Valid Delay

T11

00-015 Write Data Float Delay

4

T27

00-015 CPU PORT Access Setup Time

9

2

T28

00-015 CPU PORT Access Hold Time

6

2

T29

PORT Setup Time

11

2

T30

PORT Hold Time

8

2

T17

ROY Setup Time

19

2

T18

ROY Hold Time

6

2

T19

00-015 READ Setup Time

9

2

T,20

00-015 READ Hold Time

6

2

T12

HOLD Valid Delay

2

33

1-199

82596DX/SX

A.C. CHARACTERISTICS (Continued)
82596SX C-STEP INPUT/OUTPUT SYSTEM TIMINGSTC

=

O·Cto

+ 85·C, VCC

=

5V ±10% (Continued)

These timings assume the CL on all outputs is 50 pF unless otherwise specified. CL can be 20 pF to 120 pF,
however, timings must be derated.
All timing requirements are given in nanoseconds.

Symbol

16MHz

Parameter
Min

T21

HLDA Setup Time

Notes
Max

15

1,2

T22a

HLDA Hold Time

7

1,2

T23

RESET Setup Time

13

1,2

T24

RESET Hold Time

4

1,2

NOTES:
Timings shown are for the 82596CA C-Stepping. For information regarding timings for the 82596CA A 1 or B-Step, contact
your local Intel representative.
1. RESET, HLDA, and CA are internally synchronized. This timing is to guarantee recognition at next clock for RESET,
HlDA, and CA.
2. All set~up, hold, and delay timings are at the maximum frequency specification Fmax, and must be derated according to
the following equation for operation at lower frequencies:
Tderated = (Fmax/Fopr) x T
where:
Tderated = Specifies the value to derate the specification.
Fmax = Maximum operating frequency.
Fopr = Actual operating frequency.
T = Specification at maximum frequency.
This calculation only provides a rough estimate for derating the frequency. For more detailed information contact your Intel
sales office for the data sheet supplement.
3. CA is internally synchronized; if the setup and hold times are met then CA needs to be only 2 T1. BREQ and PORT are
not internally synchronized. BREQ must meet setup and hold times and need only be 2 T1 wide.

1-200

I

82596DX/SX

TRANSMIT/RECEIVE CLOCK PARAMETERS
Symbol

20 MHz

Parameter
Min

T36

TxCCycle

T38

TxC Rise Time

Notes
Max

50

1,3
5

T39

TxC Fall Time

T40

TxC High Time

19

T41

TxC Low Time

18

T42

TxD Rise Time

T43

TxD Fall Time

T44

TxD Transition

T45

TxC Low to TxD Valid

T46
T47
T48

5

1
1
1,3
1,3

10
10

4
4
2,4

20
25

4,6

TxC Low to TxD Transition

25

2,4

TxC High to TxD Transition

25

2,4

TxC Low to TxD High (At End of Transition)

25

4

25

5

RTS AND CTS PARAMETERS
T49

TxC Low to RTS Low,
Time to Activate RTS

T50

CTS Low to TxC Low, CTS Setup Time

T51

TxC Low to CTS Invalid, CTS Hold Time

T52

TxC Low to RTS High

20
10

7
25

5

RECEIVE CLOCK PARAMETERS
T53

RxCCycle

T54

RxC Rise Time

50

1,3
5

1

5

1

T55

RxC Fall Time

T56

RxC High Time

19

1

T57

RxC Low Time

18

1

RECEIVED DATA PARAMETERS

I

T58

RxD Setup Time

20

6

T59

RxD Hold Time

10

6

1-201

82596DX/SX

TRANSMIT/RECEIVE CLOCK PARAMETERS (Continued)
Symbol

20 MHz

Parameter
Min

Notes
Max

RECEIVED DATA PARAMETERS (Continued)
T60

RxD Rise Time

10

T61

RxD Fall Time

10

CRS AND CDT PARAMETERS
T62

COT Low to TxC HIGH
External Collision Detect Setup Time

20

T63

TxC High to COT Inactive, COT Hold Time

10

T64

COT Low to Jam Start

T65

CRS Low to TxC High,
Carrier Sense Setup Time

20

T66

TxC High to CRS Inactive, CRS Hold Time

10

T67

CRS High to Jamming Start,
(Internal Collision Detect)

10

12

T68

Jamming Period

T69

CRS High to RxC High,
CRS Inactive Setup Time

30

T70

RxC High to CRS High,
CRS Inactive Hold Time

10

11

INTERFRAME SPACING PARAMETERS
T71

Interframe Delay

9

EXTERNAL LOOPBACK·PIN PARAMETERS
T72

TxC Low to LPBK Low

T36

4

T73

TxC Low to LPBK High

T36

4

NOTES:
1. Special MOS levels, VCll = 0.9V and VCIH = 3.0V.
2. Manchester only.
3. Manchester. Needs 50% duty cycle.
4. 1 TTL load + 50 pF.
5.1 TTL load + 100 pF.
6. NRZ only.
7. Abnormal end of transmission-CTS expires before RTS.
B. Normal end to transmission.
.
9. Programmable value:
T71 = NIFS. T36
where: NIFS = the IFS configuration value
(if NIFS is less than 12 then NIFS is forced to 12).
10. Programmable value:
T64 = (NCOF. T36) + x. T36
(If the collision occurs after the preamble)
where:
NCDF. = the collision detect filter configuration value, and
x = 12,13,14, or 15
11. T6B = 32. T36
12. Programmable value:
T67 = (NCSF. T36) + x • T36
where: NCSF = the Carrier Sense Filter configuration value, and
x = 12,13,14, or 15
13. To guarantee recognition on the next clock.

1·202

I

82596DX/SX

82596DX/SX BUS OPERATION
The following figures show thae basic bus cycles for the 82596DX and 82596SX.
For more details refer to the 32-8it LAN Components Manual.
CYCLE 1
T1

CYCLE 2

T2

T1

~ 1 1 ,P2 ~ 1 1 <1>2 ~ 1 1 <1>2.

CYCLE 3
T2

'P 1 1 <1>2

T1

T2

~ 1 1 <1>2 ~ 1 1 <1>2

4> 1

CLK2

(INPUT)
BE3-BEO, A31-A2,

W/R
(OUTPUTS)
ADS
(OUTPUT)
ROY

(INPUT)
LOCK

(OUTPUT)
031-00

(INPUT DURING READ)
031-00

(OUTPUT DURING WRITE)

290219-42

Figure 44_ Basic 82596DX Bus Cycles
CYCLE 1
T1

T2

 1 1 <1>2

 1 14>2

CYCLE 2



CYCLE 3

T1

T2

1 1 <1>2

 1 1 <1>2

T1
 1

1 <1>2

T2
 1

1 <1>2

'" 1

CLK2

(INPUT)
BHE-BLE,A31-Al,

BON, W/R
(OUTPUTS)
ADS
(OUTPUT)
ROY

(INPUT)
LOCK

(OUTPUT)
015-00

(INPUT DURING READ)
015-00

(OUTPUT DURING WRITE)

290219-43

Figure 45. Basic 82596SX Bus Cycles

I

1-203

82596DX/SX

SYSTEM INTERFACE A.C. TIMING CHARACTERISTICS

The measurements should be done at:
• Te

=

0°C-8SoC, Vee

=

SV ± 1 0%, C

=

SO pF unless otherwise specified.

• A.C. testing inputs are driven at 2.4V for a logic "1" and O.4SV for a logic "0".
• Timing measurements are made at 1.SV for both logic "1" and "0".
• Rise and Fall time of inputs and outputs signals are measured between 0.8V and 2.0V respectively unless
.
otherwise specified.
• All timings are relative to CLK2 crossing the 1.SV level.
• All A.C. parameters are valid only after 100 fJ-s from power up.

2.4V
0.45V

~1.5vTestPOlrity-

--'C.

~
290219-18

1----- T1

-----+I
290219-19

Figure 46. CLK2 Timings

Two types of timing specifications are presented below: .
1. Input Timing-minimum setup and hold times.
2. Output Timings-output delays and float times from CLK2 rising edge.
Figure 4S defines how the measurements should be done:

1.5V
290219-20

LEGEND:
Ts = Input Setup Time
Th = Input Hold Time
Tn = Minimum output delay or Mininum float delay
Tx = Maximum output delay or Maximum float delay

Figure 47. Drive Levels and Measurements Points for A.C. Specifications

1·204

I

82596DX/SX

INPUT WAVEFORMS

Ts = T13, T15, T17, T19, T21, T23, T27, T29, T31
Th = T14, T16, T18, T20, T22, T22a, T24, T28, T30, T32
(PHIZ)

(PHil)

CLKZ

BREQ

CA

290219-21

Figure 48. CA and BREQ Input Timing

(PHil)

""~Q

INT/INT

~~
"290219-22

Figure 49.INTIINT Output Timing

CLK

HOLD

HLOA _ _ _ _ _ _ _ _ _--' "--_ _ _- J

"--_ __

290219-23

Figure 50. HOLD/HLDA Timings

(PHI z)

(PHil)

CLKZ

ROY

031-00
290219-24

Figure 51. Input Setup and Hold Time

I

1·205

82596DX/SX

T1
CLK2 - - - '

T6-

A31-A2, BEn,
BHE, BLE, BON, LOCK (T6)

T6d

(PHI1)

--r-------I

(PHI2)

v--

I~MAX

-';'V-AL-ID-n""'XXXXXX~

n+ 1

I-TS-CIMJ

W/R, ADS

VALID n

X~

n+1

IT10-~MAX
_ _ _ _.....~IO DATA

031-00
(OUTPUT)

290219-25

Figure 52. Output Valid Delay Timing

(PHI 1)

(PHI2)

CLK2

MIN
A31-A2, BEn
BHE, BLE, BON, LOCK

MAX
FLOAT

VALID n

MIN

MAX
FLOAT

VALID n

MIN

MAX
FLOAT

VALID n

031-00
(OUTPUT)

290219-26

Figure 53. Output Float Delay Timing

CLK2

PORT.

031-00

290219-27

Figure 54. PORT Setup and Hold Time

I

82596DX/SX

RESET
290219-28

Figure 55. RESET Input Timing.
SERIAL A.C. TIMING CHARACTERISTICS

3.0V

0.9V

I_T41j
T57_

~---------~~~----------~

290219-29

Figure 56. Serial Input Clock Timing

TxC

CTS

TxO

----------------------~

- V... __ ~6! _

;t.. __T!~

__

:,~I~-------T6-7---j--_+r.v.. ______________ _

(NRZ) _ _ ."... _______ ••" ... ______ ...'

' .. - -- - - - - - - - - - - --

-jT44rTxD _•••
_. 411.'" • ______ •••• • ______ ,.-_ _ _ _ _.....;._ _ _ _ _ _ _ _ _ _ _ _ __
XXX

(MANCHES,TER) .......

XX

til . . . . . _ _ _ _ • •

"

_ . . . . . _ _ _ ...

290219-30

Figure 57. Transmit Data Waveforms

I

1-207

82596DX/SX

TxC

RTS

CTS

COT

CRS

___

TxD - - - - - - - - - ' \ .
(NRZ)

T43

TXD~H

(MANCHESTER)

~,\f'.

_____

"'~"_

- - --

•••••• - •• - - - -

;,----"'\.

T4~L

T47

~•••• _ •• ~_ _ _ __

'---I.····-·t~

290219-31

Figure 58. Transmit Data Waveforms

CRS

290219-33
290219-32

Figure 60. Receive Data Waveforms (eRS)
Figure 59. Receive Data Waveforms (NRZ)

1-208

I

82596DX/SX

OUTLINE DIAGRAMS
132 LEAD CERAMIC PIN GRID ARRAY PACKAGE INTEL TYPE A
SEATING
PLANE

SEATING~
PLANE

oB

(ALL PINS)

~c==ij
SWAGGED
PIN
DETAIL

290219-36

Family: Ceramic Pin Grid Array Package
. Millimeters

Symbol
Min

Max

Min

Max

Notes

A

3.56

4.57

0.140

0.180

A1

0.76

1.27

Solid Lid

0.030

0.050

Solid Lid

A2

2.67

3.43

Solid Lid

0.105

0.135

Solid Lid

As

1.14

1.40

0.045

0.055

B

0.43

0.51

0.017

0.020

D

36.45

37.21

1.435

1.465

D1

32.89

33.15

1.295

1.305

61

2.29

2.79

0.090

0.110

L

2.54

3.30

0.100

0.130

1.27

2.54

0.050

0.100

132

N
S1
ISSUE

I

Inches
Notes

IWS

132

10/12/88

1-209

82596DX/SX

Intel Case Outline Drawings
Plastic Quad Flat Pack (PQFP)
0.025 Inch (O.635mm) Pitch
Symbol

N

Description

Min

Leadcount

Max

Min

68

Max

84

Min

Max

100

Min

Max

132

Min

Max

164

Min

Max

196

A

Package Height

0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170

A1

Standoff

0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030

D,E

Terminal Dimension

0.675 0.685 0.775 0.785 0.875 0.885 1.075 1.085 1.275 1.285 1.475 1.485

D1,E1

Package Body

0.547 0.553 0.647 0.653 0.747 0.753 0.947 0.953 1.147 1.153 1.347 1.353

D2,E2

Bumper Distance

0.697 0.703 0.797 0.803 0.897 0.903 1.097 1.103 1.297 1.303 1.497 1.503

D3,E3

Lead Dimension

D4,E4

Foot Radius Location 0.623 0.637 0.723 0.737 0.823 0.837 1.023 1.037 1.223 1.237 1.423 1.437

0.400 REF

Foot Length

IWS Preliminary 12/12/88

N

Description

0.600 REF

0.800 REF

1.000 REF

1.200 REF

0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030

L1
Issue
Symbol

0.500 REF

INCH

Min

Leadcount

Max

Max

Min

68

84

Min

Max

100

Min

Max

132

Min

Max

164

Min

Max

196

A

Package Height

4.06

4.32

4.06

4.32

4.06

4.32

4.06

4.32

4.06

4.32

4.06

4.32

A1

Standoff

0.51

0.76

0.51

0.76

0.51

0.76

0.51

0.76

0.51

0.76

0.51

0.76

D,E

Terminal Dimension

17.15 17.40 19.69 19.94 22.23 22.48 27.31 27.56 32.39 32.64 37.47 37.72

01, E1

Package Body

13.89 14.05 16.43 16.59 18.97 19.13 24.05 24.21 29.13 29.29 34.21 34.37
17.70 17.85 20.24 20.39 22.78 22.93 27.86 28.01 32.94 33.09 38.02 38.18

02, E2

Bumper Distance

D3,E3

Lead Dimension

D4,E4

Foot Radius Location 15.82 16.17 18.3618.71 21.25 21.25 25.8926.33 31.0631.41 36.14 36.49

10.16REF

0.51

L1

Foot Length

Issue

IWS Preliminary 12/12/88

1-210

0.76

12.70 REF

0.51

0.76

15.24 REF

0.51

0.76

20.32 REF

0.51

0.76

25.40 REF

0.51

0.76

30.48 REF

0.51

0.76
mm

I

82596DX/SX

mm (inch)
290219-37

Figure 61. Principal Dimensions and Datums

1$10.25 (.010)@ ICIA®-B® 10®~
--L .002 MM/MM (IN/IN)IA-BJ

r~"

$ 0.25 (.010)@LCLA®-B®ID®~
--L .002 MM/MM -=~~~

11.31 (.1l12)
1l.21l <'IlIlB)

1l.2" <'IlIlB)
1l.14 <'1l1l5)

-t IB OEG.

1$18.28 (.8IlB)@ICIA@-B®10®i&

Il DEG.
290219-40

mm (inch)
DetallJ

Detail L
Figure 64. Typical Lead

I

1.32 (.1l52)
1.22 <'1l4B)
~
8.911 <'''35) MIN.
.
2.83 (.8BIl)
1.93 <'Illb)
---02-----t

290219-41

mm (inch)
Figure 65. Detail M

REVISION SUMMARY
The following represents the key differences be·
tween version -005 and version ·006 of the
82596CA Data Sheet.

1. A description of the 82596DX/$X C·stepping en·
hancements was added and the 82596DX/SX
B·step·information was removed.
2. Recommendation to use only one type of buffer
(either Simplified or Flexible) in any given linked
list.

3. Added detailed description regarding operation of

4. Added New Enhanced Big Endian Mode section.
The New Enhanced Big Endian Mode applies only
to the 82596 C-stepping.
5. Added programming recommendations regarding
RU and CU Start commands. These warn against
Starting the CU while it is Active and Starting the
RU while it is Ready.
6. Emphasized that the TDR command is a static
command and· should not be used in an active
network.

7. Improved 82596DX/SX C-step timings were added for all speeds.

RCVCDT counter.

1·212

I

82503
DUAL SERIAL TRANSCEIVER (DST)
82503 PRODUCT FEATURE SET OVERVIEW
Component Ethernet* Interface
• Single
to Both 802.3 10BASE-T and AUI
or Manual Port Selection
• Automatic
Manchester Encoder/Decoder and
• Clock Recovery
Glue Interface to Industry-Standard
• No
LAN Controllers
-Intel 82586, 82590, 82593 and 82596
-AMD 7990 (LANCE*)
- National Semiconductor 8390 and
83932 (SONIC*)
- Western Digital 83C690
- Fujitsu 86950 (Etherstar*)

Loopback
• Diagnostic
Reset, Low Power Modes
•
Status Indicators
• Network
Defeatable Jabber Timer
• Test Modes
• User
10 MHz Transmit Clock Generator
• One
Micron CHMOS** IV (Px48)
• Technology
• Single 5-V Supply

INTERFACE FEATURES
TPE

AUI

• Complies with 10BASE-T, IEEE Std.
802.3i-1990 for Twisted Pair Ethernet

•
•

Direct Interface to AUI Transformers

• Selectable Polarity Switching

•

On-Chip AUI Squelch

•

Direct Interface to TPE Analog Filters

•

On-Chip TPE Squelch

•

Defeatable Link Integrity (LI)

•

Support of Cable Lengths> 100m

Complies with IEEE 802.3 AUI Standard

A block diagram of a typical application is shown in Figure 1. The 82503 Dual Serial Transceiver is a high-integration CMOS device designed to simplify interfacing industry standard Ethernet LAN Controllers to IEEE
802.3 local area network applications (10BASE5, 10BASE2, and 1OBASE-T). The component supports both
an attachment unit interface (AUI) and a Twisted Pair Ethernet interface (TPE). It allows OEMs to design a
state-of-the-art media interface that is jumperless and fully automatic. The 82503 includes on-chip AUI and
TPE drivers and receivers; it offers designers a cost-effective, integrated solution for interfacing LAN control~
lers to the wire medium.

"CHMOS is a patented process of Intel Corporation .
• Ethernet is a registered trademark of Xerox Corporation.
LANCE is a registered trademark of Advanced Micro Devices.
Etherstar is a registered trademark of Fujitsu Electronics.
Sonic is a registered trademark of National Semiconductor Corporation.
October 1995
Order Number: 290421-004

1-213

82503 Dual Serial Transceiver (DST)
CONTENTS

PAGE

1.082503 PRODUCT FEATURES ..... 1-215

2.0 PIN DEFINITION ...................
2.1 Power Pins ......................
2.2 Clock Pins .......................
2.3 AUI Pins .........................

1-217
1-218
1-218
1-218

2.4 TPE Pins ........................ 1-219
2.5 Controller Interface Pins ......... 1-219
2.6 Mode Pins ........................ 1-220
2.7 LED Pins ........................ 1-221

3.082503 ARCHITECTURE ...........
3.1 Clock Generation ................
3.2 Transmit Blocks .................
3.3 Receive Blocks ..................
3.4 Collision Detection ..............
3.5 Link Integrity ....................
3.6 Jabber Function .................
3.7 TPE Loopback ..................
3.8 SQE Test Function ..............
3.9 Port Selection ...................
3.10 LED Description ................
3.11 Polarity Switching ..............
3.12 Controller Interface .............

1-214

1-222
1-222
1-222
1-223
1-225
1-225

CONTENTS

PAGE

4.0 RESET, LOW POWER AND TEST
MODES ..............................
4.1 Reset ...........................
4.2 Low Power and High Impedance
Modes ............................
4.3 Diagnostic Loopback ............

1-228
1-228
1-228
1-228

4.4 Customer Test Modes (Continuous
AUI/TPE Transmit) ............... 1-228

5.0 APPLICATION EXAMPLE .........
5.1 Introduction .....................
5.2 Design Guidelines ...............
5.3 Layout Guidelines ...............

1-229
1-229
1-229
1-229

6.0 PACKAGE THERMAL
SPECIFICATIONS ................... 1-231
7.0 ELECTRICAL SPECIFICATIONS
AND TIMINGS ....................... 1-232

1-225
1-225
1-226
1-226
1-226
1-226
1-227

I

82503

TRt.lT

DO-A

TRt.lT

DO-8
DI-A

RCV

LAN
Controller

Pulse
Transformer

DI-8

TxC

RCV

TxD

CLSN

Cl-A

RxC

CLSN

CI-8

RxD
CDT

82503

D8-15

TDH

RTS

TDL

TD+

CRS

TDH

TD-

TDL
RD

Analog
Front
End,

RD+

RJ-45

RD-

RD
290421-1

Figure 1. Application Block Diagram

1.0

82503 PRODUCT FEATURES

The 82503 incorporates all the active circuitry required to interface Ethernet controllers to 10BASE-T
networks or the attachment unit interface (AU I). It
supports a direct no-glue interface to Intel's family of
high-performance LAN controllers (82586, 82590,
82593, and 82596). The 82503 also provides a direct no-glue interface to the National Semiconductor
8390 and 83932 (SONIC), the Western Digital
83C690, the Advanced Micro Devices 7990
(LANCE) and 79C900 (ILACC), and the Fujitsu
86950 (Etherstar) controllers.
This component includes three advanced features:
jumperless two-port design capability, automatic port
selection, and polarity switching. The jumperless
TPE or AUI port selection capability allows designers maximum ease-of-use and network flexibility. Automatic port selection ensures complete software
compatibility with existing 10BASE2 and 10BASE5
software drivers. The 82503's polarity switching feature will detect and correct polarity errors on the
twisted pair-the most common wiring fault in twisted pair networks.
The 82503 contains all the circuitry needed to meet
the 10BASE-T specification, including link integrity, a
jabber timer and internal predistortion. Deselecting
link integrity allows the component to be used in
some prestandard networks. The 82503's jabber
timer prevents the station from continuously transmitting and is defeatable for simple design charac-

I

terization. The predistortion circuitry eliminates line
overcharge and reduces jitter on 10BASE-T links.
The 82503 can also support twisted pair cable
lengths of up to 200m when placed in TPE Extended
Squelch Mode (XSQ).
This component incorporates six LED drivers to display transmit data, receive data, collision, link integrity, polarity faults and port selections, allowing for
complete network monitoring by the user. The transmit, receive and collision LEDs indicate the rate of
activity by the frequency of flashing. The 82503 also
has a low power mode. During low power, many of
the 82503's pins are in a high-impedance state to
facilitate board-level testing ..
The 82503's diagnostic loopback control enables it
to route a transmission signal from the LAN controller through its Manchester encoder-decoder circuitry
and back to the LAN controller. This provides effective network node fault detection and isolation capabilities. In addition, the 82503 supports diagnostic
test modes that generate continuous tranmission of
data through the twisted pair port, allowing designers to measure the analog performance of their design.
The 82503 is available in 44-lead PLCC and 44-lead
QFP packages and is fabricated with Intel's lowpower, high-speed, CHMOS IV technology using a
single 5-V supply.

1-215

82503

VCCA

Vee

I

... RxD
RxC

I

I

Collision
. Presence
and SQE

...... -

I
AUICLSN

CLSN

Noise Filter

CLSN

a:

Carrier
Prasensa

lAanchester
Decoder

a:

Clock Recovery

~

APOL/XSQ

~

AUI RCV

RCV

Noise Filter

RCV

a:

Polarity
Switching

POLED

f
Link
Integrity

LID.
APORT

Xl

X2

..... ~

...

,

!
Clock
Generation

1 .1

.....
RTS .....
~
CSO
CSI
RESET
TEST
LPBK

Auto Port
Detect/Select

J.

Divide
by

Test
Controller

1
lA~nchester

Encoder

RD

Noise Filter

RD

a:

TPE/Aui

!

,l..

1.

rll
.

AUI
Xmit Drivers

~

Low Power

I
I

TP Xmit Drivers

a:

Predistortion

...,....
...,....

Control
Logic

~

I

Vss

I
Vss

TRIAT

II

TRIAT

JABD

Timer

a:

2

TxD

LlLED
TP RCV

I

Vss

~ TDH .
~ ~ TDL

f-f--

TDH
TDL

TXLED
Status
LEDS

RXLED
COLED

I
290421-2

Figure 2.82503 Functlpnal Block Diagram

1-216

I

82503

2.0

PIN DEFINITION
0

U1

x

'-'

>'-'

0

U1
U

>"-'
0

0..

<

I~

...
'"0 "0..

<

0..

>-

... ... .., ... ...
0

-'

0

0..

0

0

...J

...J

...J

'"

>-

0
U

x

0

X

0

...J

:::;

'-'

>'-'

VSS

VSS

CSI

LID

TxC

TDH

CRS

TDL

82503

LPBK

TDH

44L PLCC
Top View

CDT
RxD
RxC

TDL

RD
RD

31

RTS

RCV

TxD

RCV

VSS

VSSA

'-' >U1

...

>'-' >-

N

X

X

...>...
U1

'"

o
'"
<
..,

IZu Z 1>U1
...J

U1

::E

...J
u

'"
>-

>-

<

'">-

>'-'

::E

'-'

290421-3

Figure 3. 44·Lead PLCC Pin Configuration

0

U1

x

'-'

0

U1

>'-' u

"-'
0

0..

<

>- I~ 0 0 0 0
'"0 ;::,. ...0 ...0 ... ...
< >'" >0..

...J

...J

0..

U

0..

...J
X

...J
X

...
0

...J

:::;

'-'

>'-'

44 43 42 41 40 39 38 37 36 35 34
VSS

VSS

CSI

LID

TxC

TDH

CRS
LPBK
CDT
RxD
RxC

82503
44L QFP
Top View

TDL
TDH
TDL

RD
RD

RTS

RCV

TxD

RCV

VSS

VSSA

290421-44

Figure 4. 44·Lead QFP Pin Configuration

I

1-217

82503
2.1 Power Pins
PLCC
Pin

Symbol

QFP
Pin

Type

Name and Function

VSS(1)

7,17,39

1,11,33

Supply

Vcc!11

6,18,40

44,12,34

Supply

Digital Vee. A 5-V ± 5% Power Supply.

VCCA(1)

28

22

Supply

Analog Vee. A 5-V ± 5% Power Supply.

VSSA(1)

29

23

Supply

Analog Ground.

Digital Ground.

NOTE:
1. Vcc and VCCA must be connected to the same power supply. Vss and VSSA must be connected to the same ground:
Separate decoupling and noise conditioning (e.g., ferrite beads) should be used.

2.2 Clock Pins
Symbol

PLCC
Pin

QFP
Pin

Type

X1

21

15

I

X2

20

14

a

PLCC
Pin

QFP
Pin

Type

Name and Function

fRMT

27
26

21
20

a
a

TRANSMIT PAIR. Adifferential output driver pair that drives the
transmit pair ofthe transceiver cable. The output bit stream is
Manchester encoded. Following the last transition, which is positive
at TRMT, the differential voltage is reduced to zero volts.

RCV
RCV

31
30

25
24

I
I

RECEIVE PAIR. A differentially driven input pair which is tied to the
receive pair of the Ethernet transc'eiver cable. The first transition on
RCV is negative-going to indicate the beginning of the frame. The
last transition is positive-going to indicate the end of the frame. The
received bit stream is assumed to be Manchester encoded.

CLSN
CLSN

25
24

19
18

I
I

COLLISION PAIR. A differentially driven input pair tied to the
collision presence pair of the Ethernet transceiver cable. The
collision presence signal is a 10 MHz square wave. The first
transition atCLSN is negative-going to indicate the beginning of the
signal; the last transition is positive~going to indicate the end of the
signal.

Name and Function
CLOCK CRYSTAL. A 20 MHz crystal input. This pin can be driven
. with an external MaS level clock when X2 is left floating.
CLOCK CRYSTAL. A 20 MHz crystal output. X1 can be driven with
an external MaS level clock when this pin is left floating.

2.3 AUI Pins
Symbol
TRMT

1-218

I

82503

2.4 TPE Pins
PLCC
Pin

QFP
Pin

Type

Name and Function

TDH
TDH
TDL
TDL

35
37
34
36

29
31
28
30

0
0
0
0

TP TRANSMIT PAIR DRIVERS. These four outputs constitute the
twisted-pair drivers, which have predistortion capabilities. The TDHI
TDH outputs generate the 10 Mb/s Manchester Encoded data. The
TDLlTDL outputs mirror the TDH/TDH outputs except for fat bit
occurrences (100 ns pulses). During the second half of a fat bit
(either high or low), the TDLlTDL outputs are inverted with respect
to TDH/TDH outputs. This signal behavior reduces the amount of
jitter by preventing overcharge on the twisted pair medium.

RD
RD

32
33

26
27

I
I

TP RECEIVE PAIR. The differential twisted pair receiver. The
receiver pair is connected to the twisted pair medium and is driven
with 10 Mb/s Manchester encoded data.

Symbol

2.5 Controller Interface Pins
PLCC
Pin

QFP
Pin

Type

TxC

9

3

0

TxD

16

10

I

TRANSMIT DATA. TTL input. NRZ serial data is clocked in on TxD
from the Ethernet controller. Connects directly to the transmit data
pin of the Ethernet controller.

RTS

15

9

I

REQUEST TO SEND. TTL input. An active low input signal
synchronous to TxC which enables data transmission on the active
port. Changes sense depending on controller selected. Active low
for the Intel controller interface, active high for National, AMD, and
Fujitsu interfaces.

RxC

14

8

0

RECEIVE CLOCK. A 10 MHz clock output tied directly to the
receive clock pin of the Ethernet controller. This clock is the
recovered clock from incoming data on the active port. Changes
sense depending on controller selected. Active low for Intel and
Fujitsu controller interfaces, active high for National and AMD
interfaces. Can drive one TTL load.

RxD

13

7

0

RECEIVE DATA. Received NRZ data (synchronous to RxC) passed
to the Ethernet controller. Connect directly to the receive data pin of
the controller. Can drive one TTL load.

CRS

10

4

0

CARRIER SENSE. Output that alerts the Ethernet controller that
data is present on the active port. Connects directly to the carrier
sense pin of the Ethernet controller. Changes sense depending on
controller mode selected. Active low for Intel controller interface;
active high for National, AMD, and Fujitsu interfaces. Can drive one
TTL load.

COT

12

6

0

COLLISION DETECT. Output that indicates presence of a collision.
Connects directly to the collision detect pin of the Ethernet
controller. Changes sense depending on controller selected. Active
low for Intel and Fujitsu controller interfaces, active high for National
and AMD interfaces. Can drive one TTL load.

Symbol

I

Name and Function
TRANSMIT CLOCK. A 10 MHz clock output tied directly to the
transmit clock pin of the Ethernet controller. Changes sense
depending on controller selected. Active low for Intel and Fujitsu
controller interfaces, active high for National and AMD interfaces.
Can drive one TTL load.

1-219

82503

2.6 Mode Pins
PLCC
Pin

QFP
Pin

Type

Name and Function

TPE/AUI

2

40

I/O

PORT SELECT. TTL input/LED output. If APORT is low,
TPE/ AUI is an input and selects either the TPE port (TPE/ AUI
high) or AUI port (TPE/ AUllow). If APORT is high, the 82503 will
indicate the port selected by driving TPE/ AUI high (TPE) or low
(AU I). TPE/ AUI can drive an LED pull-up.

APORT

3

41

I

AUTOMATIC PORT SELECTION. TTL input. When high, 82503
will automatically select TPE or AUI port based on presence of
valid link beats or frames on theTPE receive input. Mode
selected will be indicated on TPE/ AU I.

APOLlXSQ

4

42

I

AUTOMATIC POLARITY CORRECTION/EXTENDED
SQUELCH ENABLE. TTL input. When high, the extended
squelch mode is disabled and automatic polarity correction is
enabled. Both junctions (APOL and XSQ) are enabled when this
pin is at a high impedance state. When low, both functions
become disabled. The presence of a polarity fault on the TPE
receive pair is indicated on POLED regardless of the state of
APOL.

LID

38

32

I

LI.NK INTEGRITY DISABLE. TTL input. If high, link integrity
function is disabled. If low, link integrity function is enabled.

eso
eS1

5
8

43
2

I
I

CONTROLLER SELECT. Selects the appropriate interface for
the desired Ethernet controller. When eSO/1 = 0/0, supports
Intel controllers. When eSO/1 = 0/1, supports Fujitsu
controllers. When eSO/1 = 1/0, supports Western Digital and
National controllers. When eSO/1 = 1/1, supports AMD
controllers. (See Table 2.)

LPBK

11

5

I

LOOPBACK. TTL input. An active low input signal that causes
the 82503 to enter diagnostic loopback mode. The twisted pair
or AUI medium will be removed from the circuit, thus isolating
the node from the network. When not connected, this pin
assumes the inactive (high) state. Diagnostic loopback does not
disable the operation of the link integrity processor, link beat
generator, or automatic port selection.

JABD

23

17

I

JABBER DISABLE. TTL input. When high, this pin disables the
jabber function. When low, the jabber function is enabled and
the device performs AUI or TP jabber protection for the active
port. If this pin and TEST are asserted during a falling edge of
RESET, the 82503 enters its low power mode; when either this
pin or TEST deasserts, then the 82503 transitions to its normal
operating mode.

TEST

19

13

I

TEST MODE ENABLE. TTL input. When TEST is high and
RESET is deasserted, a customer test mode is directly
accessed. When driven low, test mode is disabled. If this pin and
JABD are asserted during a falling edge of RESET, the 82503
enters its low power mode; when either this pin or JABD
deasserts, then the 82503 transitions to its normal operating
mode.

RESET

22

16

I

RESET. TTL input. When high, resets internal circuitry. On the
falling edge of RESET, either test mode or low power mode can
be entered depending on the state of JABD and TEST.

Symbol

1-220

I

82503

2.7 LED Pins
PLCC
Pin

QFP
Pin

Type

Name and Function

TxLED

42

36

1/0

TRANSMIT LED. LED output. Indicates transmit status of the AUI or
TPE port. Normally off (high) output. Turns on to indicate
transmission. Flashes at a rate dependent on the level of transmit
activity. Upon entering a customer test mode, this pin must be
driven high either through an LED, or a resistor.

RxLED

43

37

1/0

RECEIVE LED. LED output. Indicates receive status of the AUI or
TPE port. Normally off (high) output. Turns on to indicate reception.
Flashes at a rate dependent on the level of receive activity. Upon
entering a customer test mode, this pin must be driven high either
through an LED, or a resistor.

COLED

44

38

1/0

COLLISION LED. LED output. Indicates collision status of the AUI
or TPE port. Normally off (high) output. Turns on to indicate
collision. Flashes at a rate dependent on the level of collision
activity. This pin is also used to determine which customer test
modes are entered.

LlLED

41

35

0

LINK INTEGRITY LED. LED output. Normally on (low) output which
indicates good link integrity on the TPE port during TPE mode.
Remains on when link integrity function has been disabled. Turns off
during AUI mode or when link integrity fails in TPE mode. Minimum
off time is 100 ms, minimum on time is set by the link integrity
function.

POLED

1

39

0

POLARITY INDICATION. LED output. If the 82503 detects that the
receive TPE wires are reversed, POLED will turn on (low) to indicate
the fault. POLED remains on even if APOLlXSQ is high and the
82503 has automatically corrected for the reversed wires.

Symbol

NOTE:
1. The LED outputs have a weak pull-up capable of sourcing 500 /LA. They can sink 10 rnA while still meeting TTL levels. All
LEOs can be used as indication pins if no LED is needed. Some of these outputs include pulse width conditioning, which
should be accounted for in software.

I

1-221

82503

3.0

82503 ARCHITECTURE

3.2 Transmit Blocks

3.1

Clock Generation

3.2.1 MANCHESTER ENCODER

A 20 MHz parallel resonant crystal is used to control
the clock generation oscillator, which provides the
basic 20 MHz clock source. An internal divide-bytwo counter generates the 10 MHz ± 0.01 % clock
required by the IEEE 802.3 specification.
We recommend a crystal that meets the following
specifications be used.
• Quartz Crystal
.. 20 MHz ± 0.002% at 25'C
• Accuracy ± 0.005% over full operating temperature, O'C to· + 70'C
• Parallel resonant with 20 pF Load Fundamental
Mode

The 20 MHz clock is used to Manchester-encode
data on the TxD input. This clock is also divided by
two to produce the 10 MHz clock the LAN controller
needs for synchronizing its RTS and TxD signals.
Data encoding and transmission begins with RTS
asserting. Since the first bit of a transmission is a 1,
the first transition is always negative on the transmit
outputs (TRMT or TD pins). Transmission ends
when RTS deasserts. The last transition is always
positive at the transmit outputs (TRMT or TD pins)
and may occur at the center of the bit cell if the last
data bit to be transmitted is a 1, or at the boundary
of the bit cell if the last data bit to be sent is a O.

Several vendors have such crystals; either-off-the
shelf or custom made. Two possible vendors are:

Immediately after the end of a transmission, all signals on the RCV pair (when AUI mode is selected)
are inhibited for 4 to 5 ,..,s. This dead time is necessary for proper operation of the SQE (heartbeat)
test.

1. M-Tron Industries, Inc.
Yankton, SD 57078

3.2.2 AUI CABLE DRIVER

• Maximum Series Resistance: RSERIES

=

30n

Specifications;
Part No. HC49 with 20 MHz, 50 PPM over O'C to
+ 70'C, and 20 pF fundamental load.
2. Crystek Corporation
100 Crystal Drive
Ft. Myers, FL 33907
Part No. 013212
The accuracy of the Crystal Oscillator frequency depends on the PC board characteristics, therefore it is
advisable to keep the X1 and X2 traces as short as
possible. The optimum value of C1 and C2 should
be determined experimentally under nominal operating conditions. The typical value of C1 and C2 is
between 22 pF and 35 pF.
An external 20 MHz MOS-Ievel clock may be applied
to pin X1, if pin X2 is left floating.

1-222

The AUI cable driver (TRMT pair) is a differential
circuit, which interfaces to the AUI cable through a
pulse transformer.
High voltage protection is achieved by using a transformer to isolate the transmit pins (TRMT pair) from
the transceiver cable. The total transmit circuit inductance, including the 802.3 transceiver transformers, should be a minimum of 27 ,..,H for Ethernet applications.
3.2.3 TWISTED PAIR CABLE DRIVER
Jhe twisted pair line drivers (TD pairs) begin transmitting the serial Manchester bit stream 3 bit times
after RTS is asserted. The line drivers use a predistortion algorithm to improve jitter performance for up
to 100 meters of twisted pair cable. The line drivers
reduce their drive level during the second half of
"fat" (100 ns) Manchester pulses and maintain a full
drive level during all "thin" (50 ns) pulses and during
the first half of the "fat" pulses. This reduces line
overcharging during "fat" pulses, a major source of
jitter.

I

82503

290421-4

Figure 5. TPE Pre distortion

3.3 Receive Blocks
3.3.1 MANCHESTER DECODER AND CLOCK
RECOVERY

The 82503 performs Manchester decoding and timing recovery of the incoming data in AUI and TPE
modes.
The Manchester-encoded data stream is decoded to
separate the Receive Clock (RxC) and the Receive
Data (RxD) from the differential signal. The 82503
uses an advanced digital technique to perform the
decoding function. The use of digital circuitry instead
of analog circuitry (e.g., a phase-lock loop) to perform the decoding ensures that the decoding function is less sensitive to variations in operating conditions.
A high-resolution phase reference is used to digitize
the phase of the incoming data bit-center transition.
The digitizer has a phase resolution of 1/32 of a bit
time.

I

The digitized phase is filtered by a digital low-pass
filter to remove rapid phase variations, i.e., phase
jitter. Slow phase variations, such as those caused
by small differences between the data frequency
and the clock frequency, are not filtered by the lowpass filter.
The RxC generator digitally sets the phases of the
two RxC transitions to respectively lead and lag the
bit-center transition by % bit time. RxC is used to
recover RxD by sampling the incoming data with an
edge-triggered flip-flop.
Lock is achieved by reducing the time constant of
the digital filter to zero at the start of a new fra~e.
Any uncertainty in the bit-center phase of the first
transition that is caused by jitter is subsequently removed by gradually increasing the filter time constant during the following preamble. By that time, the
phase of the bit center is output by the filter, and
lock is achieved. Lock is achieved within the first 14
bit times as seen by the AUI inputs. The maximum
bit-cell timing distortion (jitter) tolerated by the Manchester decoder circuitry is ± 12 ns (preamble),
± 18 ns (data) for AUI, and ± 13.5 ns for TPE (data
and preamble).

1-223

82503

IO-MHz
CLOCK

D~=--"

HIGH RESOLUTION
PHASE
REFERENCE

MANCHESTER
ENCODED
DATA

ol--C>RXD

FRAME
DETECT CIO--..;...--------1~------I
290421-5

Figure 6, Manchester Decoder and Clock Recovery
3.3.2AUI RECEIVE AND COLLISION BUFFERS
The AUI receive and collision inputs are driven
through isolation transformers to provide high voltage protection and DC common mode voltage rejection. The incoming signals are converted to digital
levels and passed to the Manchester decoder and
collision detection circuitry.
3.3.3 AUI RECEIVE AND COLLISION
SQUELCH CIRCUITS
Both the receive (RCV) and collision (CLSN) pairs
have the following squelch characteristics.

devices and EMI filters necessary to conform to the
10BA$E-T standards and local RF regulations. The
input differential voltage range for the TPE receiver
is greater than 500 mV and less than 3.1 V differential.
3.3.5 TPE; RECEIVE SQUELCH CIRCUITS
The TPE receive buffer distinguishes valid receive
differential data, link test pulses, and the idle condition according to the requirements of the 1OBASE-T
standard. Signals at the output of the EMI filter (thus
at the RD and RD pair) are rejected as follows:

• The squelch circuits are turned on at idle.

• All differential pulses of peak magnitude less than
300 mV are rejected.

• A pulse is rejected if the peak differential voltage
is more pOsitive than -160 mV regardless of
pulse width.

• All continuous sinusoids with a differential amplitude less than 6.2 Vpp and a frequency less than
'
2 MHz are rejected.

• A pulse is considered valid if its peak differential
voltage is more 'negative than - 300 mV and its
width, measured at - 285 mV, is greater than
25 ns.
'

• All sine waves, of single cycle duration starting
with phase O· or 180· that have an amplitude less
than 6.2 Vpp, and a frequency of 2 MHz to
16 MHz are rejected, if the single cycle is preceeded and followed by 4 bit times of silence
(Le., a signal less than 300 mY).

• The squelch circuits are disabled by the first valid
negative differential pulse on either the AUI receive (RCV) or the AUI collision (CLSN) pair.
• If a positive differential pulse occurs ,on either the
AUI receive or collision pairs for greater than
160 ns, End of Frame (EOF) is assumed and the
squelch circuitry is turned on.
3.3.4 TPE RECEIVE BUFFER
The TPE receive pins (RD and RD) are connected to
the twisted pair medium through an analog front
end. The analog front end contains the line coupling

1-224

3.3.6 TPE Extended Squelch Mode
By placing the 82503 into TPE extended squelch
mode, the 82503 can support cable lengths greater
than the 100m specified in the 10Base-T IEEE standard (802.3i-1990). The squelch thresholds for the
signals at the RD/RD pair are typically reduced by
4.5 dB. This allows Grade 5 twisted-pair cable to be
used to overcome attenuation and multipair crosstalk for cable lengths up to 200 meters.

I

82503
TPE extended squelch mode is enabled by presenting a high-impedance (> 100 Kfl) at the APOLlXSQ
pin. This can be done by floating the APOL/XSQ pin,
tying APOL/XSQ low through a 100 Kfl resistor, or
driving APOL/XSQ with a three-state buffer. When
driven high or low using a TTL driver or a low impedance pull-up or pull-down « 2 Kfl) extended
squelch is disabled and the driven level at the
APOL/XSQ pin determines the state of the polaritycorrection function (APOLlXSQ = 1 enables polarity correction, APOL/XSQ = 0 disables polarity correction). The TPE extended squelch feature is transparent to previous step pings of the 82503. Polarity
correction is always enabled when the TPE extended-squelch feature is enabled (APOL/XSQ = Z).
The APOLlXSQ pin senses a high-impedance state
by an active-polling circuit implemented at the pin.
Two small polling devices attempt to pull the APOLI
XSQ pin up to Vee and down to Vss. If the pin is in a
high-impedance state, the devices will be successful
in pulling the APOL/XSQ pin high and low. If the pin
is driven high or low, the polling devices will not be
able to successfully pull the pin in the opposite direction. In this way, an internal state machine can
correctly determine one of three states of the
APOL/XSQ pin. The pin is polled every 25.6 /los.

to the twisted pair medium as an indication to the
remote MAU that the link is good. These pulses will
be transmitted 8 ms to 24 ms after the end of the
last transmission or link test pulse.
The link integrity function continuously monitors activity on the receive circuit. If neither valid data nor
link test pulses are received, the link integrity processor declares the link bad, and disables transmission and reception on the media, loopback, and the
SQE test function. Transmission of link test pulses
and monitoring receive activity are not affected. The
idle time required for the link integrity processor to '
determine the link is bad is 50 ms to 150 ms.
Once a frame or a sequence of 2 to 10 valid consecutive link test pulses are detected, the Link Integrity
Processor declares the link is good, and reconnects
the transmitter and receiver.
The link integrity function can be disabled by driving
the LID pin high or by disabling automatic port selection (APORT = 0) and selecting the AUI port. This
option is intended primarily for use with pre1OBASE-T networks.

3.6 Jabber Function
3.4 Collision Detection
3.4.1 AUI COLLISION DETECTION
Collision detection in the AUI mode is performed by
the attached transceiver, and signalled to the 82503
on the CLSN pair. A 10 MHz +25%, or -15%,
square wave with transition times between 35 ns
and 70 ns indicates the collision. The 82503 reports
this to the LAN controller on the COT pin.
3.4.2 TPE COLLISION DETECTION
Collision detection in the TPE mode is indicated by
simultaneous transmission and reception on the
twisted pair link segment. The COT signal is asserted for the duration of both RTS and the presence of
received data; CRS is asserted for the duration of
either RTS or the presence of received data. During
a collision, the source of RxO will be the received
data. If the received data stream ends before the
transmit data stream, the RxO source will be
changed to transmit data stream until it ends.

The 82503 contains a jabber timer to implement the
jabber function. ,If a transmission continues beyond
the limits specified, the jabber function inhibits further transmission and asserts the collision indicator,
COT. The limits for jabber transmission are 20 ms to
150 ms in TPE Mode, and 8 ms to 16 ms in AUI
mode. For both AUland TPE mode, the transmission inhibit period extends until the 82503 detects
sufficient idle time (between 250 ms and 750 ns) on
the RTS signal. The jabber function can be disabled
by driving the JABO high.
In TPE mode the link integrity function continues to
operate even if the jabber function is inhibiting transmission. Link test pulses continue to be sent and the
receive circuit continues to be monitored. Additionally, the link integrity function reconnects to a restored
link without waiting for the transmit input to go idle
when the jabber function is inhibiting transmission.

3.7 TPE Loopback

3.5 Link Integrity

In TPE mode the'82503 implements the transmit to
receive loop back (DO to 01) mode specified in the
10BASE-T standard. This mode loops back transmitted data through the receive path.

The 82503 supports the link integrity function as defined by 10BASE-T. During long periods of idle on
the transmitter, link test pulses will be transmitted on

This function is required to maintain full compatibility
with coax MAUs where the data loopback is a natural result of the architecture.

I

1-225

82503
The transmit to receive loop back function is disabled
when the jabber function or link integrity function is
inhibiting transmission.

3.8 SQE Test Function
The 82503 supports the SQE test function when in
TPE mode or in Diagnostic Loopback mode. The
82503 will assert its COT pin within 0.6 !,-S to 1.6 !,-S
after the end of a transmission, and it will remain
asserted for 5- to 15-bit times. If the 82503 is in the
TPE mode and is not in diagnostic loop back mode,
the link integrity function will disable the SQE test
'
function when it detects a bad link.

3.10 LED Description
The 82503 supports six LED pins to indicate the
status of important. states; TPEI AUI, TxLED,
POLED, LlLED, RxLED, COLED. Each pin is capable
of directly driving an LED.
3.10.1 TPE/AUI
When automatic port selection is enabled (APORT is
high), TPEI AUI becomes an LED output and turns
off if TPE mode is selected and on if AUI mode is
selected.
3.10.2 TxLED

3.9 'Port Selection
The 82503 features both manual and automatic port
selection. To enable automatic port selection, connect APORTto Vee. The 82503 then starts in TPE
mode and monitors link integrity. If the link is good,
the 82503 stays in TPE mode and pulls TPEI AUI
high to indicate that the TPE port was selected. If
link integrity fails, the 82503 switches to AUI mode
and pulls TPEI AUI low to indicate that the AUI port
is now active. TPEI AUI can drive an LED to indicate
port selection (on for AUI, off for TPE mode). Note
that LlLED will be on if TPE mode is selected and off
if AUI mode is selected. If link integrity is disabled
while automatic port selection is enabled, the 82503
defaults to TPE mode. If the 82503 changes ports
while RTS is active, transmission is terminated with
an End of Frame marker on the old port. Transmission of the remaining packet fragment is not allowed
on the new port. Transmissions will, begin with a
complete data packet.
The port can be manually selected by driving'
APORT low. TPEI AUI = 0 selects AUI mode, and
TPEI AUI = 1 TPE mode. When the port is manually
selected, the circuitry for the unused port is powered
down. Changing ports requires 100 ,...S to allow the
circuitry for the new port to resume normal operation.
Table 1. Port Selection
Configuration

State

LID APORT TPE/AUI
X
X
0
1

0
0
1
1

0
1
X'
X'

AUI (TPE Port Powered Down)
TPE (AUI Port Powered Down)
Automatic Port Selection
TPE

NOTE:

*TPEI AUI is an output pin when APORT

=

1.

Transmit status. This LED is normally off and flashes
at 2.5 Hz, 5 Hz, and 10Hz to indicate respectively a
low, medium, and high rate of transmit activity.
3.10.3 RxLED
Receive LED. This LED is normally off and flashes at
2.5 Hz, 5 Hz, and 10Hz to indicate respectively a
loW, medium, and high rate of receive activity.
3.10.4 COLED
Collision LED. This LED is normally off and flashes
at 2.5 Hz, 5 Hz, and 10Hz to indicate respectively a
low, medium, and high rate of collision activity.
3.10.5 POLED
Polarity Fault. This LED is normally off and turns on
to indicate a polarity fault in the receive pair of the
1OBASE-T link. Operation of this pin is not affected
by the state of the polarity correction function
(APOL/XSQ = X).
3.10.6 LlLED
Link Integrity status. When Aport is enabled
(APORT = 1), this LED is normally on (driven low)
to indicate the presence of a valid 1OBASE-T link
when the TPE port is active. The LED will turn off
(driven high) when the link fails. When link integrity is
disabled (LID = 1) while APORT is enabled
(APORT = 1) this LED is turned on (driven low). If
APORT is disabled (APORT = 0) and the AUI port is
manually selected (TPEI AUI = 0) the LED output is
tristated.

3.11 Polarity Switching
In TPE mode, the 82503 monitors receive link beats
and end-of-frame delimiters for a possible receiver

1-226

I

82503

RESET

FOUR CONSECUTIVE
NORMAL LINK BEATS
OR PACKETS DETECTED

FOUR CONSECUTIVE
REVERSED LINK BEATS
OR PACKETS DETECTED

• IF APOL IS ASSERTED DATA WILL
BE INTERNALLY CORRECTED

290421-6

Figure 7. Polarity Fault State Diagram

polarity error due to crossed wires. If Pin 4 of the
82503 is high and the TPE receive pins are reversed, the 82503 will correct the error by reversing
the signals internally, and turn POLED on (low) to
indicate that the fault has been detected and corrected. The polarity correction function is defeatable
by driving the APOL/XSQ input low. However, the
polarity fault will continue to be indicated on the
POLED.

3.12 Controller Interface
Connecting the 82503 to one of the Intel Ethernet
controllers (82586, 82590, 82593, 82596) requires
no additional components. Simply drive CSO and
CS1 both low, and connect TxC, TxD, RTS, RxC,
RxD, CRS, CDT, and LPBK to the corresponding
controller pins.

I

The 82503 also works with other Ethernet controllers without additional components, including the
National Semiconductor 8390 and 83932 (SONIC),
Western Digital 83C690, Fujitsu 86950 (Etherstar),·
depending on the state of and CSO and CS1 inputs.
The interface of the 82503 to the AMD 7990
(LANCE) requires external logic to control the LPBK
pin of the 82503. Note that when an AMD LAN controlle(is used to interface to the 82503, the LPBK
pin of the 82503 becomes active high. That is, the
82503 enters diagnostic loopback mode when LPBK
pin is high and is in normal operation mode when
LPBK pin is low.
The logic sense of the 82503 controller pins will
change and should be connected to the controller
pins according to the following table.

1-227

82503

Table 2. Controller Interface Selection
82503
Pin

,

Intel
Controller
825XX

National, WD
Controllers
8390, 83C690,
83832 (SONIC)

AMD
Controller
7990 (LANCE),
79C900 (ILACC)

Fujitsu
Controllers
86950 (Etherstar)

0
0

1
0

1
1

0
1

CSO(1)
CS1
Pin

Pin

Sense

Pin

Sense

Pin

Sense

Pin

Sense

TxC
TxD
RTS
RxC
RxD
CRS
CDT
LPBK

TxC
TxD
RTS
RxC
RxD
CRS
CDT
LPBK

Low
High
Low
Low
High
Low
Low
Low

TXC
TXD
TXE
RXC
RXD
CRS
COL
LPBK

High
High
High
High
High
High
High
High

TCLK
TX
TENA
RCLK
RX
RENA
CLSN

High
High
High
High
High
High
High

TCKN
TXD
TEN
RCKN
RXD
XCD
XCOL
LPBK

Low
High
High
Low
High
High
Low
High

(Note 2)

NOTES:

1, eso and eS1 are intended to be static pins only. Switching eso and eS1 during network reception or transmission will
produce unpredictable results.
2. Refer to Section 3.12.

4.0
4.1

RESET, LOW-POWER AND
TEST MODES
Reset

When RESET is asserted the device resets its internal circuits. RESET is required after power up, and
before data can be transmitted or received. It is allowed any time thereafter, but any existing receive or
transmit activity will be lost, and all state machines
(Link integrity, Jabber, and Polarity Correction) return to their initial states. TEST must be held low for
a device reset to prevent entering a test for low power mode. During RESET, TxC continues without interruption (in Fujitsu mode both TxC and RxC run
continuously).

4.2 Low Power and High Impedance
Modes
When RESET is deasserted while both TEST and
JABD are held high, the 82503 enters its low power
and high impedance modes. The majority of internal
circuitry is powered down, and many inputs and outputs are three.stated. These pins are: APORT,
APOLlXSQ, LID, TPEI AUI, POLED, L1LED, RTS,
LPBK, RxD, TxD, CRS and CDT. When either JABD
or TEST is deasserted, the device begins a power
on cycle which lasts less than 1 ms. During this cycle, all inputs are ignored and all transmissions are
disabled. If RTS is active when the device returns to
normal operation, the remainder of that packet fragment is not transmitted. Normal transmissions are
resumed at the start of the first complete data packet.
'

1-228

4.3 Diagnostic Loopback
This is a diagnostic test mode to help in fault isolation and detection. Serial NRZ data input on TxD is
Manchester encoded and then looped back through
the Manchester decoder (TMD) appearing at the
RxD output. Collision detect is asserted following
each transmission to simulate the SQE test.Output
cable drivers and input amplifiers are disconnected
from the controller interface pins while in this mode.
The link integrity and polarity fault detection functions are not inhibited by diagnostic loopback mode.
If otherwise enabled, they continue to function.

4.4 Customer Test Mode
(Continuous AUI/TPE Transmit)
In this mode, the 82503 continuously transmits data
without the intervention of a LAN controller. Transmission is at 10 MHz (11-bit pattern), and can occur
on either the TPE or AUI port. The jabber timer is
disabled in this mode, allowing users to easily test
the 10BASE-T harmonic content specification and
the quality of their analog front end design without
complex software exercisers.
Customer Test Mode-and Low Power Mode are selected at the deassertion of RESET as shown in the
following table. (Note that the 82503 must be in nonloopback mode before it can enter the customer test
mode.)

I

82503

Table 3. Test and Low Power Mode Selection
RESET

TEST

JABO

TxLEO(1)

RxLEO(1)

COLEO(1)

i
i
i

0

X

X

X

X

Normal Mode

1

0

1

1

1

Cont Tx 10 MHz

1

1

X

X

X

Low Power

Mode Selected

NOTE:
1. A standard LED connection to these pins is sufficient to pull them to a logic 1.

The port on which the continuous transmit appears
is determined by the APORT and TPEI AUI pins. If
automatic port selection is enabled (APORT = 1)
then the TPE port broadcasts the continuous trans·
mit. If manual port selection is enabled (APORT =
0), then TPEI AUI selects the port (1 for TPE, 0 for
AUI). Test mode is disabled when TEST is deassert·
ed and the device is reset.

5.0

APPLICATION EXAMPLE

5.1 Introduction
The 82503 is designed to work directly with the Intel
LAN controllers (82586, 82590, 82593, and 82596),
as well as AMD's Am7990, National Semiconduc·
tor's 8390, Western Digital's 82C690, and Fujitsu's
86950. The serial interface signals connect directly
between one of the aforementioned LAN controllers
and the 82503 without the need for external logic.
This example is targeted toward interfacing the
82503 to the Intel 82596 in a two·port (TPEI AUI)
application.
.

Terminating Resistors
The terminating resistors used across the receive
and collision pairs are recommended to be 78.7 n
±1%.

Analog Front-End
The 82503 provides six TPE pins (TDH, TDH, TDL,
TDL, RD, and RD) that connect to the Analog Front
End through a resistor summing network (Figure 7).
AFE solutions can be made discretely or purchased
from several manufacturers. Two different solutions
are described in Application Note 356. The example
shown here uses a Pulse Engineering AFE package
PE65434 which includes EMI filter, isolation transformer, and common mode choke. The output of the
AFE connects directly to the 10BASE-T connector
(RJ-45).
Decoupling
It is recommended that 0.01 f.loF X7R and 0.001 f.loF
NPO decoupling capacitors be placed between the
VCCA and VCCD of the 82503 to VSSA and VSSD.
Clock Generation

5.2 Design Guidelines
AUI Pulse Transformer
In order to meet the 16V fault tolerance specification
of 802.3 a pulse transformer is recommended for the
transmit, receive and collision pairs. The transformer
should be placed between the TRMT, RCV, and
CLSN pairs of the 503, and the DO, 01, and CI pairs
respectively, of the AUI (08·15 connector). The
pulse transformer should have a parallel inductance
- of 75 f.loH minimum (100 f.loH recommended).
Several vendors stock such transformers. Two possible vendors are:
1. Pulse Engineering (PIN PE-641 03)
2. Valor Electronics (PIN LT6003)

I

The clock input to the 82503 can be from a clock
oscillator or a crystal. If a clock oscillator is used, X1
should be driven, and X2 left floating. If a crystal
oscillator is used, refer to Section 3.1 for crystal
specifications.
A complete 82596/82503 TPEI AUI Ethernet Solution is shown at the end of this section.

5.3 Layout Guidelines
General
The analog section, as well as, the entire board itself
should conform to good high·frequency practices
and standards to minimize switching transients and
parasitic interaction between various circuits. To
achieve this, the following guidelines are presented.

1-229

82503

r--------,
;:~-"".".". ~

nn

;~

~~~~~~ae~~~~1 ~i

290421-7

Figure a.Application Example Schematic

1-230

I

82503
Make power supply and ground traces as thick as
possible. This will reduce high-frequency cross coupling caused by the inductance of thin traces.
Connect logic and chassis ground together.
Separate and decouple all of the analog and digital
power supply lines.
Close signal paths to ground as close as possible to
their sources to avoid ground loops and noise cross
coupling.
Use high-loss magnetic beads on power supply distribution lines.
.
Crystal
The crystal should be adjacent to the 82503 and
trace lengths should be as short as possible. The Xl
and X2 traces should be symmetrical.
82503 Analog Differential Signals
The differential signals from the 82503 to the transformers, analog front end, and the connectors
should be symmetrical for each pair and as short as
possible. Differential signal layout should be performed to a characteristic impedance of 78n (for
AUI) or 1DOn (for TPE).
As a general rule, the trace widths should be one to
three times the distance between the PCB layers to
eliminate excessive trace inductance.
The differential signals should also be isolated from
the high speed logic signals on the same layer as
well as on any sublayers of the PCB.
Group each of the circuits together, but keep them
separate from each other. Separate their grounds.
In layout, the circuitry from the connectors to the
filter network, should have the ground plane removed from beneath it. This will prevent ground
noise from being induced into the analog front end.
All trace bends should not exceed 45 degrees.

I

6.0

PACKAGE THERMAL
SPECIFICATIONS

The 82503 Dual Serial Transceiver is specified for
operation when case temperature (Tc> is within the
range of DOC to + 85°C. The case temperature can
be measured in any environment, to determine if the
82503 is within the specified operating range. The
case temperature should be measured at the center
of the top surface opposite the pins.
The acceptable operating ambient temperature (TA)
is guaranteed as long as Tc is not violated. The ambient temperature can be calculated from the 0ia
and 0ie from the following equations:
Tc

+

P x 0je

TJ = TA

+

P x 0ia

TJ

=

TA = Tc - P x (Oia - 0jd

Values for 0ia and 0ie are given in Table 4 for the 44lead PLCC and 44-lead QFP packages. Various values for 0ia at different airflows. Table 5 shows the
maximum T A allowable (without exceeding Tc> at
various airflows.
Table 4. Thermal Resistance
eC/Watt) 0ie and 0la
lila vs Airflow-ft/min (m/s)
Package lIie 0 200
400
600
800 1000
(0) (1.01) (2.03) (3.04) (4.06) (5.07)
44-Lead 19 57
PLCC.

48

43

41

39

37

44-Lead 26 98
OFP

94

78

70

66

64

Table 5. Maximum T A at Various Airflows
Ilia vs Airflow-ft/min (m/s)
Package

0
200
400
600
1000
800
(0) (1.01) (2.03) (3.04) (4.06) (5.07)

44-Lead
PLCC

66

71

73

74

75

76

44-Lead
OFP

49

51

59

63

65

66

1-231

82503

ELECTRICAL SPECIFICATIONS
AND TIMINGS

7.0

NOTICE: This is a production data sheet. The specifi·
cations are subject to change without notice.

* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

ABSOLUTE MAXIMUM RATINGS
Case Temperature Under Bias ....... O°C to
Storage Temperature .......... -65°C to

+ 85°C

+ 140°C

All Output and Supply Voltages ..... -O.5V to
All Input Voltages ............. -1.0V to

DC CHARACTERISTICS
Symbol

(Tc

=

+ 7V

+ 6.0V(1)

O°Cto

Parameter

+ 85°C, VCC =
Min

5V ±5%, VCCA
Max

Units

VldTTL)(2)

Input Low Voltage

-0.3

0.8

V

VIH(TTL)(2)

Input High Voltage

2.0

Vec

V

IU(2)

Input Leakage Current

±10

/LA

VodMOS)(3)

Output Low Voltage

0.45

V

VOH(MOS)

Output High Voltage

VodLED)(4)

Output Low Voltage

VOH(LED)

Output High Voltage

ILP

Leakage Current, Low
Power Mode(5)

RDIFF

Input Differential Resistance(6)

VIDF(TPE)<7)

Input Differential
Input Differential
Input Differential
Input Differential

Accept
Reject
Accept (XSQ)
Reject (XSQ)

3.9
0.45
3.9

10

5V ±5%)
Test Conditions

O.OV ,:; VI ,:; Vee, RESET = 1
IOL = 4 mA

=

V

IOH

V

IOL= 10 mA

V
±10

=

IOH

-500/LA

= -

500 /LA..,

/LA

O.OV ,:; VI ,:; Vee

kn

dc

±3.1
±0.300
±3.1
±0.180

Vp
Vp
Vp
Vp

5MHz,:; f,:; 10MHz

6

13

n

IILOADI

±0.500
(Note 8)

Rs(TPE)(8)

Output Source Resistance

VIDF(AUI)(9)

Input Differential Accept
Input Differential Reject

±0.300

± 1.5
±0.160

Vp
Vp

VODF(AUI)(10)

Output Differential Voltage

±0.450

± 1.20

V

=

25 mA

NOTES:
1. The voltage levels for RCV, CLSN, and RD pairs are -0.75V to +8.5V.
2. TTL Input Pins: TxD, RTS, TPE/AUI, APORT, APOLlXSO, LID, CSO, CS1, LPBK, JABD, TEST,RESET.
3. MaS Output Pins: TxC, RxD, RxC, CRS, CDT.
4. LED Pins: TPE/AUI, TxLED, RxLED, COLED, POLED, LlLED. VOL measured 10 ns after falling edge of TxC.
5. Pins: APORT, APOL/XSO, LID, TPEI AUI, POLED, LlLED, RTS, LPBK, RxD, TxD, CRS,
CDT, CSO, CS1, JABD, TEST, and RESET.
6. Pins: RD to RD, RCV to RCV, and CLSN to CLSN.
7. TPE Input Pins: RD, and RD. See Section 3.3.4 and Section 3.3.5.
8. Typically it is -4.5 dB below normal squelch level.
9. TPE Output Pins: TDH, TDH, TDL, and TDL. Rs measures Vee or Vss to Pin.
10. AUI Input Pins: RCV, and CLSN pairs.
11. AUI Output Pins: TRMT pair.

1-232

I

82503

DC CHARACTERISTICS

(Tc

=

O·Cto

+ 85·C, vcc =

5V ±5%, VCCA

Min

Symbol

Parameter

Max

Units

losc(AUI)

AUI Output Short Circuit Current

± 150

mA

Vu(AUI)

Output Differential Undershoot

-100

mV

±40

mV

VODI(AUI) Differential Idle Voltage(11)

=

5V ±5%) (Continued)

Test Conditions
Short Circuit to Vcc or GND

=
=
=

Icc(HOT)

Power Supply Current(12)

65

mA

APORT

Icc

Power Supply Current

75

mA

APORT

60

mA

APORT

1

mA

Low Power Mode, 20 p.A Typical

1
1

IcC

Power Supply Current

Iccss

Standby Supply Current(13)

PD(HOT)

Power Dissipation(12)

0.38

W

APORT
onAUI

=

1, Continuous Transmission

PD

Power Dissipation

0.40

W

APORT
onAUI

=

1, Continuous Transmission

PDss

Standby Power Dissipation(13)

5.25

mW

Low Power Mode, 105 P. W Typical

CIN(14)

Input Capacitance

10

pF

atf

=

0

1 MHz

NOTES:
11. Measured B.O
after last positive transition of data packet.
12. Ice HOT measurements made at Te = +B5'C. Additionally, TRMT, TRMT, TDH, TDH, TDL, TDL are loaded with 20 pF
and load resistors removed.
13. Pins CSO and CS1 connected to Vee or Vss through a 2.5 k!l (or less) resistor. leess is typically at 20 ",A after 30s
from power down assertion-not tested.
14. Characterized, not tested. (Controller interface and mode pins only.)

"'S

AC TIMING CHARACTERISTICS

2.4V===+-I"
___
2.0V
~

1.5V ---+1/.
o.8v===~I~
O.45V
OELAY/WIDTH MEASUREMENT 7~
RISE/fALL MEASUREMENT -

___

-

3'0V~:X-r-,

O.9V==~.~\"\..._ __

290421-9

--

290421-8

Figure 9. MOS Input Voltage Levels
(TTL Compatible) for Timing Measurements
(TxD, RTS, TPE/AUI, APORT, APOL/XSa,
LID, LPBK, JABD, TEST, and RESET).

Figure 10. Voltage Levels for MOS Level
Output Timing Measurements
(TxC, RxD, RxC, CRS, and CDT).

](+---OV

DELAY/WIDTH MEASUREMENT RISE/FALL MEASUREMENT -

DELAY/WIDTH MEASUREMENT RISE/FALL MEASUREt.tENT -

I-290421-10

Figure 11. Voltage Levels for Differential Input
Timing Measurements (RCV and CLSN Pairs).

I

](+---OV

--

290421-11

Figure 12. Voltage Levels for TRMT Pair
Output Timing Measurements.

1-233

intel®

82503

AC TIMING CHARACTERISTICS (Continued)
IV

+

vee

][+---ov

1\
LI

t

vss

vee/ 2
DELAY/WIDTH MEASUREMENT RISE/FALL MEASUREMENT -

1~

DELAY/WIDTH MEASUREMENT -~
RISE/FALL MEASUREMENT -

I290421-13

--

Figure 14. Voltage levels for Differential Input
Timing Measurements (RD Pair).

290421-12

Figure 13. Voltage levels for
TDH, TDl, TDH, and TDL

AC MEASUREMENT CONDITIONS
1. Tc = O°C to

+ 85°C, Vce

=

5V ±5%.

2. The AC MaS, TTL and differential signals are referred to in Figures, 8, 9, 10, 11, 12, and 13.
3. AC loads
a. MaS: 20 pF total capacitance to ground.
b. AUI Differential: a 10 pF total capacitance from each terminal to ground and a load resistor of 780. ± 1 %
in parallel with a 27 fA-H ± 1% inductor between terminals.
c. TPE: 20 pF total capacitance to ground.
4. All parameters become valid 200 fA-s after the supply voltage and input clock has stabilized, or after RESET
deasserts.

CLOCK TIMING (15)
Typ

Symbol

Parameter

Min

Max

Units

tl

X1 Cycle Time

49.995

t2

Xi Fall Time

50.005

ns

5

ns

t3

X1 Rise Time

t4

X1 Low Time

15

5

ns
ns

ts

Xi High Time

15

ns

NOTE:
15. Refers to External Clock Input.

290421-14

Figure 15. Xi Input Voltage levels for Timing Measurements

1-234

I

82503

Controller Interface Timings (Intel Mode)
TRANSMIT TIMINGS (Intel)
Symbol

Parameter

tlO

TxC Cycle Time

t11

TxC High/Low Time

t12

TxC Rise/Fall Time

t13

TxD and RTS Rise/Fall Time

t14

TxD Setup Time to TxC

t15
t16
t17

Min

Typ

99.99

!TxD Hold Time from TxC !RTS Setup Time to TxC !RTS Hold Time from TxC !-

Max

Units

100.01

ns

40

ns

5

ns

10

ns

45

ns

0

ns

45

ns

0

ns

290421-15

Figure 16. Transmit Timing (Intel)

I

1·235

intel®

82503

RECEIVE TIMING (Intel)
Min

Typ

RxC 'Cycle Time

96

100

t21

RxC High Time

36

ns

t22

RxCLowTime

40

ns

t23

RxC Rise/Fall Time

t24

RxC Delay from CRS ,J..

t25

RxD Rise/Fall Time

t26

RxD Setup from RxC ,J..

30

t27

RxD Hold from RxC ,J..

30

t28

CRS Deassertion Hold Time from RxC High

10

Symbol
t20

Parameter

1100

Max

Units
ns

5

ns

1400

ns

5

ns
ns
ns

40

ns

290421-16

Figure 17. Receive Timing (Intel)

1·236

I

82503

Controller Interface Timings (National Mode)
TRANSMIT TIMINGS (National)
Symbol

Parameter

Min

t30

TXC Cycle Time(16)

99.99

t31

TXC High/Low Time

40

t32

TXC Rise/Fall Time at 20% to 80%

t33

TXD Setup Time to TXC i

t34

Typ

Max

Units

100.01

ns

50

ns

5

ns

20

ns

TXD Hold Time from TXC i

0

ns

t35

TXE Setup Time to TXC i

20

ns

t36

TXE Hold Time from TXC i

0

ns

NOTE:

16. All delay and width measurements on TxC are made at 1.5V.

TXC

lX'

290421-17

Figure 18. Transmit Timing (National)

I

1-237

82503

RECEIVE TIMINGS (National)
Min

Typ

RxC Cycle Time

96

100

t41

RxC High/Low Time(17)

40

SO

t42

RxC Rise/Fall Time at 20% to 80%

t43

RXD Rise/Fall Time at 20% to 80%

t44

RXD Setup Time to RxC

t45

RXD Hold Time from RxC

t46

RxC Delay from CRS

t47

RxC Continuing Beyond CRS

Symbol
t40

Parameter

t

Max

ns

60

ns

'S

ns

S

ns

30

t

ns

20

t
J.

Units

ns

1400

ns

S

cycles

NOTE:
17. All delay and width measurements on RXC are made at 1.5V.

CRS

----J/L
'46

,xc

290421-18

Figure 19. Receiving Timings (National)

1-238

I

82503

Controller Interface Timing (AMD Mode)
TRANSMIT TIMINGS(18) (AMO)
Symbol

Parameter

Min

tso

TCLK Cycle Time

tS1

TCLK High Time (@ 0.8V to 2.0V)

45

tS2

TCLK Low Time (@ 2.0V to 0.8V)

45

tS3

TCLK Rise/Fall Time (@ 0.8V to 2.0V)

tS4

TX Setup Time to TCLK i

tss

TX Hold Time from TCLK i

tS6
tS7

Typ

Max

Units

100.01

ns

50

58

ns

50

58

ns

2.5

5

ns

99.99

20

ns

5

ns

TENA Setup Time to TCLK i

20

ns

TENA Hold Time from TCLK i

5

ns

NOTE:
18. Delay times for TX, TENA, and TCLK are measured from O.8V for falling edges, and 2.0V for rising edges.

~

TCLK

r-------~------------------~----~;~

''''1
TX

290421-19

Figure 20. Transmit Timings (AMD)

I

1-239

82503

RECEIVE TIMINGS(19) (AMD)
Symbol

Parameter

Min

Typ

Max

Units

t60

RCLK Cycle Time

96

100

ns

t61

RCLK High Time (@ 0.8V to 2.0V)

38

50

ns

t62

RCLK Low Time (@ 2.0V to 0.8V)

38

t63

RCLK Rise/Fall Time (@ 0.8V to 2.0V)

t64

RX Rise/Fall Time (@ 0.8V to 2.0V)

t65

RX Hold time from RCLK

t66

RX Setup Time to RCLK

t67

RENA Deassertion Hold Time from RCLK i

t68

RCLK Delay from RENA i

i

50

ns

2.5

5

ns

2.5

5

ns

10

i

ns

ns

45
40

50

80

ns

450

ns

NOTE:
19. Delay times for RX. RENA. and RCLK are measured from O.BV for falling edges and 2.0V for rising edges.

1

RENA

-I---'
RCLK

-----.---\

RX

290421-20

Figure 21. Receive Timings (AMD-Start of Frame)

~-----

RENA

t67

I-

RClK

RX

,\-__---J!
LAST BIT

290421-21

Figure 22. Receive Timings (AMD-End of Frame)

1-240

I

82503

Controller Interface Timings (Fujitsu Mode)
TRANSMIT TIMINGS (Fujitsu)
Symbol

Parameter

t70

TCKN Cycle Time

t71

TCKN High/Low Time(20)

t72

TCKN Rise/Fall Time at 20% to 80%

t73
t74
t75
t76

J.. (20)
TXD Hold Time from TCKN J.. (20)
TEN Setup Time to TCKN J.. (20)
TEN Hold Time from TCKN J.. (20)
TXD Setup Time to TCKN

Min

Typ

99.99
40

Max

Units

100.01

ns

50

ns

5

ns

20

ns

0

ns

20

ns

0

ns

NOTE:
20. Timing measurements are referenced at 1.5V level.

TCKN

TEN

TXD

-------'

-------'

~~----------------290421-22

Figure 23. Transmit Timings (Fujitsu)

I

1-241

82503
RECEIVE TIMINGS (Fujilsu)
Symbol

Min

Typ

180

RCKN Cycle Time

Parameter

96

100

181

RCKN High/Low Time(21)

35

50

182

RCKN Rise/Fall Time al 20% 10 80%

183

RXD Selup Time from RCKN

t (21)

RXD Hold Time from RCKN

185

XCD Assertion Hold Time from RCKN

187
188

RCKN Delay from XCD

186

i

ns
ns

5

ns
ns

10

t (21)
XCD Deassertion Hold Time from RCKN t (21)
XCD Deassertion Selup Time from RCKN t (21)

Units

60

20

t (21)

184

Max

ns

0

10

ns

120

ns

80

(21)

130

ns

1400

ns

NOTE:
21. Timing measurements are referenced at 1.5V.

I

XCD

r-

r--- ---111---- ----1,j t=j
:=j
~mm<
till
~
1'5

I"

II

RXD

\

IC

I83

\

1'0

r
290421-23

Figure 24. Receive Timings (Fujitsu ......Start of Frame)

XCD

RCKN

.290421-24

Figure 25. Receive Timings (Fujitsu-End of Frame)

1-242

I

82503
TPETimings
TPE TRANSMIT TIMINGS
Symbol

Parameter

Min

Typ

Units

2

bits

400

ns

600

ns

3

ns

2

5

ns

100

101

ns

51

ns

t90

TxD to TD Bit Loss at Start of Packet

t91

TxD to TD Steady State Propagation Delay

t92

TxD to TD Startup Delay

t93

TDH and TDL Pairs Edge Skew (@ Vee/2)

t94

TDH and TDL Pairs Rise/Fall Times (@ 0.5V to Vee - 0.5V)

t95

TDH and TDL Pairs Bit Cell Center to Center

99

t96

TDH and TDL Pairs Bit Cell Center to Boundary

49

50

t97

TDH and TDL Pairs Return to Zero from Last TDH

t98

Link Test Pulse Width

t99

Last TD Activity to Link Test Pulse

t100

Link Test Pulse to Data Separation

1.5

i

Max

250

400

ns

100

102

ns

8

13

24

ms

190

200

98

ns

TxC

Bit 1

Bit 4

Bit 3

Bit 2

Bit 5

Bit 6

bD

1----TO, - - - - - . - ; . .

"'0

-----I

b;'

3

-=====:-:-===~;~~=~=j~
.,

1 - - - - - - - - "',

___-,,-___
290421-25

Figure 26. TPE Transmit Timings (Start of Frame)

1------

"'7 - - - - - - 1

TOH

TDL

290421-26

Figure 27. TPE Transmit Timings (End of Frame)

I

1-243

82503

TDH~

1s9

~!

TDL~

!

~

Isa={'---___--I}-~\...
~oo

1 \--------~--~.~

TDH

II

TDL~
.
!

1 \'-------_1\..

290421-27

Figure 28. TPE Transmit Timings (Link Test Pulse)
TPE RECEIVE TIMINGS
Symbol

Parameter

t105

RD to RxD Bit Loss at Start of Packet

t106

RD. to RxD Invalid
Bits Allowed at Start of Packet
.

t107

RD to RxD Steady State Propagation Delay

t108

RD to RxD Start UP Delay

t109

RD Pair Bit Cell Center Jitter

t110

RD Pair Bit Cell Boundary Jitter

t111

RD Pair Held High from Last Valid Positive Transition

t112
t113

Min

4

Typ

Max

Units

19

bits

1

bits

400

ns

2.4

,...s

±13.5

ns

±13.5

ns

400

ns

CRS Assertion Delay (Intel, NS, and Fuji Mode)
(AMDMode)

700
1500

ns
ns

CAS Deassertion Delay

450

ns

230

bit 22
RD

Rii

RxC

-------+--!li--J

RxD

290421-28

Figure 29. TPE Receive Timings (Start

1-244

of Frame)

I

82503

t",

I

I

RD~

\

~'3.:j

c

F

CRS

290421-29

Figure 30. TPE Receive Timings (End of Frame)
TPE COLLISION TIMINGS
Max

Units

Onset of Collision (RD Pair and RTS Active) to CDT Assert

900

ns

t116

End of Collision (RD Pair or RTS Inactive) to CDT Deassert

900

ns

t117

CDT Assert to RxD Sourced from RD Pair

900

ns

t11 B

CDT Deassert (RD Pair Inactive) to RxD Sourced from TxD

900

ns

Symbol
t115

RD po;r

--------C:::X::::X

RTS ""\

COT

Parameter

I.

II

.

Min

Typ

~...J'--...J'--..J\..--.J'---...J'--..J\....-

c:::::'------:........s·1

II

I

______f---_----l~;~
11-----·,,6---11,...-___
~~I--------------------~I~

TXD~~--1\...,~i--1- - - I
~17~

RXD~~I

Sourced by 1 x D - - - - - - - - - - - - 1 - .- - - - -

290421-30

Figure 31. TPE Collision Timings (Start of Collision)

I

1·245

82503

::x:::::x

RD pair

>

Ii

I

CRS

l 1~~"

CDr

RrS

1
II

1

II

hD

O,D

290421';'31

Figure 32. TPE Collision Timings (End of Collision)
TPE LINK INTEGRITY TIMINGS
Symbol

Parameter

Min

Typ

Max

Units

t120

Last RD Activity to Link Fault (Link Loss Timer)

50

100

150

ms

t121

Minimum Received Linkbeat Separation(20)

2

5

7

ms

t122

Maximum Received Linkbeat Separation(21)

25

50

150

ms

NOTES:
20. Linkb·eats closer in time to this value are considered noise, and are rejected.
21. Linkbeats further apart in time than this value are not considered consecutive, and are rejected.

C--~21
RD pair

~_

_ _..J

I

~22------1

~~

1--~20---j,.--_ _ _ _ _ _ _ _ _ _ _ _ _ __

1

LlLED _ _ _ _ _ _ _ _ _

290421-32

Figure 33. TPE Link Integrity Timings

1·246

I

82503

AUI Timings
AUI TRANSMIT TIMINGS
Symbol

Parameter

Min

Typ

Max

Units

200

ns

3

5

ns

100

100.5

ns

50.5

ns

t125

TxD to TRMT Pair Steady State Propagation Delay

t126

TRMT Pair Rise/Fall Times

t127

Bit Cell Center to Bit Cell Center of TRMT Pair

99.5

t128

Bit Cell Center to Bit Cell Boundary of TRMT Pair

49.5

50

t129

TRMT Pair Held at Positive Differential at Start of Idle

200

t130

TRMT Pair Return to ,,; 40 mV from Last Positive Transition

RTS~L

ns

8.0

/ks

__________________________________________--J/

290421-33

Figure 34. AUI Transmit Timings
AUI RECEIVE TIMINGS
Symbol

Parameter

t135

RCV Pair Rise/Fall Times

t136

RCV Pair BifCell Center Jitter in Preamble

t137

RCV Pair Bit Cell Center/Boundary Jitter in Data

Min

Typ

Max

Units

10

ns

±12

ns

±18

ns

t138

RCV Pair Idle Time after Transmission

t139

RCV Pair Return to Zero from Last Positive Transition

t140

CRS Assertion Delay (Intel, National, Fujitsu Modes)
(AMD Mode)

100
1050

ns
ns

t141

CRS Deassertion Delay

350

ns

t142

CRS Inhibited after Frame Transmission

5

/ks

8

/ks
ns

160

4

4.3

1------ 1138
Rev
pair

r-

\140

~36

\

C

139

I
I-----'r--C

----1
1'41~1r-...._

'-------------\\I!f-----------------!!

1-- 1'42--1----.
290421-34

Figure 35. AUI Receive Timings

I

1-247

82503

AUI COLLISION TIMINGS
Symbol

Min

Parameter

Typ

80

Max

Units

118

ns

10

ns

t145

CLSN Pair Cycle Time

t146

CLSN Pair Rise/Fall Times

t147

CLSN Pair Return to Zero from Last Positive Transition

160

t148

CLSN Pair High/Low Times

35

t149

COT Assertion Time

t150·

COT Oeassertion Time

t151

CRS Oeassertion Time (Intel Mode Only, RCV Pair Idle)

450

ns

~

ns

75

ns

300

ns

r.--,,,==r

CLSN
pair

COT

ns

70

____________________________-+~~~r--------------1----\151

-I~

\~----------------------~li~I------J!

________
290421-35

Figure 36. AUI Collision Timings
AUI NOISE FILTER TIMINGS
Symbol

Min

Parameter

Typ

Max

Units

t152

RCV Pair Noise Filter Pulse Width Accept (@ -285 mV)

25

ns

t153

CLSN Pair Noise Filter Pulse Width Accept (@ -285 mV)

25

ns

300 mV
- -·285 mV

290421-36

Figure 37. AUI Noise Filter Timings

1·248

I

82503

LOOPBACK TIMINGS
Symbol

Parameter

Typ

Min

Max

Units

16

bits
ns

t155

TxD to RxD Bit Loss at Start of Packet

t156

TxD to RxD Steady State Propagation Delay

600

t157

TxD to RxD Startup Delay

2.2

J.tS

t158

SQE Test Wait Time

0.6

1.2

1.6

J.ts

t159

SQE Test Duration

0.5

0.8

1.5

J.ts

t160

LPBK Setup/Hold Times to RTS(22)

1.0

J.ts

NOTE:
22. Guarantees proper processing of transmitted packets. Violation of this specification will not result in spurious data trans·
mission. Incoming data packets occuring during transitions on LPBK will not be accepted.

__

LPBK~~,
~
~Il~~r----------,,~'----------~ll.i---j:====~,;'==~~========j;--J....-----" ~60
I
L._ _ _ _ _ _ _ _ _"'----------~I~

RTS

TXC~~~'\J"V'.J"'~
bit 1

bit 2

bit 3

bit 4

bit 5

bit l '8 bit 19 bit 20

(l....
AS_T_B_lTl_ _ _ _l-----------

TXO---------JI----"8'_____I

r---\

TDH
(CONTINOUS TRANSMIT) _ _ _ _ _ _ _ _ _ _ _~,

r---\

~~

,~

_ _ _ _ _ _ _ _ _ _- ; ; ; , . - - - -

290421-41

Figure 42. Reset Timings (Test Mode)

/1 1
-1 f-

Ii

.JA90 _ _ _ _ _

t180

TEST _____________________'_18jr...,;~-+----;r----------------------------RESET

--------..J1

}\..+--~"'i-------------------­

I - - - ',8,-----1

TOH
Low Power/High Impedance Mode

Normal mode

290421-43

Figure 43. Reset Timings (Start of Low Power Mode)

------------------.L
1

TE5~

~tl1~82--;-I------------------

JABD

\~----------~/

:'~~.- - - - - - - - - - - - - - - - - - - - - - - - - - -

1
1
1

TOH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~'-~~~~n>+-~

0.18(.007)

%1 1
A

®

SEE DETAIL L

A1

o

CP
SEE DETAIL J FOR
MEASUREMENT ZONE

-CSEE DETAIL J

290421-47

Figure 47. Terminal Details

MMlINCH)

290421-48

Figure 48. Standard Package Bottom View (Tooling Option 1)

1·254

I

82503

'811('035)
0.114(.025)

~

TYP

5"TYP

0.51(.020)
0.25(.010)
0.71(.028)
0.411(.018)

MM(INCH)

290421-49

Figure 49. Standard Package Bottom View (Tooling Option II)

1.52(.060) MIN - ,

\

i1~-

0.81(.032)
0.66(.026)

I

r-

80TTOM OF SHOULDER

SEATING
PLANE
MEASUREMENT ZONE FOR LT

80TTOM OF PLASTIC BODY
0.64(.025) MIN

~

[$ I

0.18(.007)

@ I F-G

® ,D":E ®-.I

DETAIL J

MM(INCH)

290421-50

Figure 50. Detail J. Terminal Detail

I

1-255

82503

1.14{.045) R

0.14(.025)

DETAILL

IIM(INCH)

290421-51

Figure 51. Detail L. Terminal Details
NOTES:
The above diagrams use a 20·lead PLCC package to show symbols for package dimensions. The table below indicates
dimensions in mm that are specific to the 44·lead PLCC package.
1. All dimensions and tolerances conform to ANSI YI4.5M·1982.
2. Datum plane -H- located at top of mold parting line and coincident with top of lead, where lead exits plastic body.
3. Datums O-E and F-G to be determined where center leads exit plastic body at datum plane -H-.
4. To be determined at seating plane -C-.
5. Dimensions D1 and E1 do not include mold protrusion.
6. Pin 1 identifier is located within one of the two defined zones.
7. Locations to datum-A- and -B- to be determined at plane -H-.
8. These two dimensions determine maximum angle of the lead for certain socket applications. If unit is intended to be
socketed, it is advisable to review these dimensions with the socket supplier.
9. Controlling dimension, inch.
10. All dimensions and tolerances include lead trim offset and lead plating finish.
11. Tweezing surface planarity is defined as the furthest any lead on a side may be from the datum. The datum is estab,
' .
lished by touching the outermost lead on that side and parallel to O-E or F-G.

Description

Symbol

1-256

Min

Max

A

Overall Height

4.19

4.57

AI

Distance from Lead Shoulder to Seating Plane

2.29

3.05

0

Overall Package Dimension

17.4

17.7

01

Plastic Body Dimension

16.5

16.7

02

Foot Print

15.0

16.0

E

Overall Package Dimension

17.4

17.7

El

Plastic BodyDimension

16.5

16.7

E2

Foot Print

15.0

16.0

CP

Seating Plans Coplanarity

0.00

0.10

TCP

Tweezing Coplanarity

0.00

0.10

LT

Lead Thickness

0.23

0.38

I

82503

44-LEAD QUAD FLATPACK PACKAGE

I~

SEA TI NG dL~:H:I*I-:II:#:I:l:I:H:I::H:I*l!I1::I-'
PLANE

290421-52

Figure 52. 44-Lead Quad Flatpack Package
Symbol

Description

Min

Nom

Max
2.35

A

Package Height

A1

Stand Off

B

Lead Width

0.2

0.3

0.4

C

Lead Thickness

0.1

0.15

0.2

01

Package Body

10

El

Package Body

10

0.60

0

91

Lead Pitch

0.65

0.8

0.95

0

Terminal Dimension

12.0

12.4

12.8

E

Terminal Dimension

Ll

Foot Length

Y

Coplanarity

T

Lead Angle

12

12.4

12.8

0.38

0.58

0.78
0.1

0

10·

NOTE:
Unless otherwise specified, all units are in millimeters.

I

1-257

82557

FASTETHERNETPCIBUSLANCONTROLLER
•

Optimum Integration for Lowest Cost
Solution
-IEEE 802.3 10BASE-T and 100BASE-T
Compatible
- Glueless 32-bit PCI Bus Master
Interface
- Flash Support up to 1 Mbyte

•

High Performance Networking
Functions
- Chained Memory Structure Similar to
the 82596 Controller
-Improved Dynamic Transmit
Chaining

- Programmable Transmit Threshold
- Early Receive Interrupt,
- Large Internal Receive and Transmit.
FIFOs
- Back-to-Back Transmit at 100 Mbps,
within minimum IFS
•

Ease of Use
- Built-in Interface to Mil Compliant
Serial Devices
- Full or Half Duplex Capable at
10 Mbps or 100 Mbps
- Standard 7-Pin ENDEC Interface to
Serial Device Such as the Intel 82503
for 10 Mbps Only Designs
- EEPROM Support
-Internal Counters for Network
Management

Parallel Side

< >
Q)

0

.g
Q)

c:
u

"-

Serial Side

Flash/EEPROM
Target Interface

Mil Interface

TX FIFO

On-Board
System
Control
Block
(SCB)
Structure

MicroMachine

FI FO Extender
Control

< >
10/100 Mbps
CSMA/CD

..

--

'",

Serial Interface
,

< >

4-Channel PCI
Bus Master Interface

RX FIFO

290545-1

Figure 1. Intel 82557 Block Diagram

·Other brands and names are the property of their respective owners.

1-258

October 1995
Order Number: 290545-001

82557
FAST ETHERNET* PCI BUS CONTROLLER
CONTENTS

PAGE

1.0 INTRODUCTION ................... 1-263
1.1 82557 Overview ................. 1-263
1.2 Features and Enhancements .... 1-263
1.3 Compliance to Industry
Standards ........................ 1-263

CONTENTS

PAGE

4.0 THE 82557 HARDWARE
INTERFACE ......................... 1-272
4.1 PCI Bus Interface ................ 1-272
4.1.1 PCI Configuration ........... 1-273

1.4 Other Literature ................. 1-263

4.1.1.1 PCI Configuration Space
Organization ................ 1-273

2.0 PIN DEFINITIONS ................. 1-264

4.1.1.2 PCI Configuration
Registers ................... 1-273

2.1 PCI Bus Interface Signals ........ 1-265
2.1.1 Signal Type Definition ....... 1-265
2.1.2 Address and Data Pins ...... 1-266
2.1.3 Interface Control Pins ....... 1-267
2.1.4 Error Reporting Pins ........ 1-267
2.1.5 Interrupt Pin ................ 1-268
2.1.6 Arbitration Pins ............. 1-268
2.1.7 System Pins ................ 1-268
2.2 Local Memory Interface .......... 1-269
2.3 Mll/Serialinterface Pins ......... 1-270

4.1.1.2.1 Device
Identification Registers ... 1-274
4.1.1.2.2 PCI
Command Register ...... 1-274
4.1.1.2.3 PCI Status
Register ................. 1-277
4.1.1.2.4
Miscellaneous PCI
Configuration Registers .. 1-279
4.1.1.2.5 Base
Address Registers ....... 1-279

2.4 Power and Ground .............. 1-271

4.1.1.2.6 Expansion
ROM Base Address
Register ................. 1-281

3.0 82557 ARCHITECTURE
OVERVIEW ......................... 1-271

4.1.1.3 PCI Configuration
Cycles ...................... 1-281

3.1 Parallel Subsystem Overview .... 1-271
3.2 FIFO Subsystem Overview ....... 1-272
3.310 Mbps/100 Mbps Serial
CSMAlCD Unit Overview ......... 1-272

I

1-259

CONTENTS

PAGE
4.1.2 82557 Bus Operations ...... 1-284
4.1 .2.1 General Overview ......
4.1.2.1.1 82557
Slave Bus Operation .....
4.1.2.1.2 Control/
Status Registers (CSR)
Accesses ; ...............
4.1 .2.1.3 FLASH
Buffer Accesses .........

1-284
1-284

1-284
1-286

4.1.2.1.4 Error
Handling ................. 1-287
4.1.2.1.5 82557 Bus
Master Operation ........ 1-288
4.2 FLASH/EEPROM Interface ...... 1-290
4.2.1.1 Flash Interface
Operation ................... 1-291
4.2.1.2 Serial EEPROM
Interface .................... 1-291
4.310 Mbps/100 Mbps CSMAlCD
UNIT ............................. 1-292
4.3.110 Mbps/100 Mbps Mil
Compatible Interface ........... 1-292
4.3.1.110 Mbps/100 Mbps Mil
Transmission ................ 1-292
4.3.1.210 Mbps/100 Mbps Mil
Reception ................... 1-292
4.3.210 Mbps/100 Mil Mbps Full
Duplex Operation .............. 1-292
4.3.3 10 Mbps-Only Interface ..... 1-293
4.3.3.1 10 Mbps
Transmission ................ 1-293
4.3.3.2 10 Mbps Reception .... 1-293
4.3.3.3 10 Mbps Full Duplex
Operation ...... ; ............ 1-293

CONTENTS

PAGE

5.082557 SOFTWARE INTERFACE ...
5.1 The Shared Memory
Communication Architecture ......
5.2 Initializing the 82557 .............
5.3 Controlling the 82557 .. : .........
5.3.1 The 82557 Control/Status
Register (CSR) .................
5.3.1.1 Statistical Counters ....

1-294
1-294
1-296
1-297
1-297
1-298

6.0 ELECTRICAL SPECIFICATIONS
AND TIMINGS ....................... '1-300
6.1 Absolute Maximum Ratings ...... 1-300
6.2 DC Specifications ............... 1-300
6.3 AC Specifications ............... r 1-302
6.3.1 PCI Interface ............... 1-302
6.4 Timing Specification ............. 1-302
6.4.1 Clock Specifications ........ 1-302
6.4.1.1 PCI Interface Clock .... 1-302
6.4.1 .2 M II Interface Clock ..... 1-303
6.4.1.3 10 Mbps Serial Interface
Clock ....................... 1-303
6.4.2 Timing Parameters .......... 1-304
6.4.2.1 PCI Timings ............ 1-304
6.4.2.2 Mil and 10 Mbps
Interface Timings ............ 1-305
6.4.2.3 Collision Parameters ... 1-306
6.4.2.4 FLASH Interface
Timings ..................... 1-307
7.0 PHYSICAL ATTRIBUTES AND
DIMENSIONS ....................... 1-309

4.4 Mil Management Interface ....... 1-293
4.4.1 MDI Cycles ................. 1-294

1-260

I

CONTENTS

PAGE

FIGURES
Figure 1. Intel 82557 Block Diagram ..................................................... 1-267
Figure 2. Device Pinout, Top View .....•.................................................. 1-264
Figure 3.

PCI Configuration Registers .................................................... 1-274

Figure 4.
Figure 5.

PCI Command Register Layout ................................................ 1-275
PCI Status Register Layout .................................................... 1-277

Figure 6.

Base Address Register for Memory Mapping ................................... 1-280

Figure 7.

Base Address Register for I/O ................................................. 1-280
Expansion ROM Base Address Register Layout ................................ 1-281

Figure 8.
Figure 9.

82557 Expansion ROM Base Address Register Format ......................... 1-281

Figure 10. Configuration Read Cycle ...................................................... 1-282
Figure 11. Configuration Write Cycle ...................................................... 1-283
Figure 12. CSR Read Cycles ............................................................. 1-285
Figure 13. CSR Write Cycle ............................................................... 1-285
Figure 14. Flash Buffer Read Cycles ...................................................... 1-286
Figure 15. Flash Buffer Write Cycle ....................................................... 1-287
Figure 16. Memory Read Burst Cycles .................................................... 1-288
Figure 17. Memory Write Burst Cycle .... " .......................................... , .... 1-289
Figure 18. 82557 EEPROM Timing Diagram (Example Read from Address 0) .............. 1-291
Figure 19. 82557 Shared Memory Structure ............................................... 1-295
Figure 20. Control/Status Register ....................................................... 1-297
Figure 21. Clock Waveform ............................................................... 1-302
Figure 22. Transmit Timings .............................................................. 1-306
Figure 23. FLASH Timings: Write Cycle .................................................... 1-308
Figure 24. FLASH Timings: Read Cycle ................................................... 1-308
Figure 25. Dimensions Diagram for Table 20 .............................................. 1~309
Figure 26. Terminal Dimensions for Table 20 .............................................. 1-309

I

1-261

CONTENTS
TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.

1-262

PAGE

Device Identification Registers ................................... , ... .: .......... 1-275
PCI Command Register Bits .............. ·....................................... 1-276
PCI Status Register Bits ........................ ; .....................•.......... 1-278
Miscellaneous PCI Configuration Bits ........................................... 1-279
82557 Base Address Registers .. : ...................... ~" ..................... 1-281
Summary of Reset Commands ........... : ~ .............. : ..................... 1-296
Error Counters .......................................................... :....... 1-298
General DC Specifications .......... ; .......................................... 1-300 .
PCllnterface DC Specifications .. ; .........................•.................... 1-300
Mil and 10 Mbps PHY Interface DC Specifications .............................. 1-301
FLASH/EEPROM Interface DC Specifications ................................... 1-301
AC Specifications for PCI Signaling ...................................•......... 1-302
PCI Clock Specifications ....................................................... 1-303
Mil Clock Specifications ........................................................ 1-303
Serial Interface Clock Specifications ..................... ; .. ; ................... 1-303
PCI Timing Parameters ........................ ; ................................ 1-304
Mil and Serial Interface Timing Parameters ............. : ... : ................... 1-305
FLASH Interface Timing Parameters ..............•............................. 1-307
Intel 82557 Package Attributes ............. ; ................. : ................ ~ .. 1-309
Quad Flatpack Dimensions in Figures 25 and 26 ....... ;.; •... ; .................. 1-309

I

82557

1.0

INTRODUCTION

1.1 82557 Overview
The 82557 is Intel's first highly integrated 32-bit PCI
LAN controller for 10 Mbps or 100 Mbps Fast Ethernet networks. The 82557 offers a high performance
LAN solution while maintaining low-cost through its
high-integration. It contains a 32-bit PCI Bus Master
interface to fully utilize the high bandwidth available
(up to 132 Mbytes per second) to masters on the
PCI bus. The bus master interface can eliminate the
intermediate copy step in Receive (RCV) and Transmit (XMT) frame copies, resulting in faster processing of these frames. It maintains a similar memory
structure to the Intel 82596 LAN Coprocessor, however, these memory structures have been streamlined for better network operating system (NOS) interaction and improved performance.
The 82557 contains two large receive and transmit
FIFOs which prevent data overruns or underruns
while waiting for access to the PCI bus, as well as
enabling back to back frame transmission within the
minimum 960 ns inter frame spacing. Full support for
up to 1 Mbyte of FLASH enables network management support via Intel FlashWorks utilities as well as
remote boot capability (a BIOS extension stored in
the FLASH which could allow a node to boot itself
off of a network drive). For 100 Mbps applications,
the 82557 contains an IEEE Mil compliant interface
to the Intel 82553 serial interface device (or other
Mil compliant PHYs) which will allow connection to
100 Mbps/10 Mbps networks. For 10 Mbps networks, the 82557 can be interfaced to a standard
ENDEC device (such as the Intel 82503 Serial Interface), while maintaining software compatibility with
100 Mbps solutions.
The 82557 is designed to implement cost effective,
high performance PCI add-in adapters, PC motherboards, or other interconnect devices such as a
hubs or bridges. Its combination of high integration
and low cost make it ideal for these applications.

1.2 Features and Enhancements
The following list summarizes the main features of
the Intel 82557 controller:
• Glueless 32-bit PCI Bus Master Interface (Direct
Drive of Bus), compatible with PCI Bus Specification, revision 2.1
• 82596-like Chained Memory Structure

• Improved dynamic transmit chaining for enhanced performance
• Programmable transmit threshold for improved
bus utilization
• Early receive interrupt for concurrent processing
of receive data
•
•
•
•

FLASH support up to 1 Mbyte
Large on-chip receive and transmit FIFOs
On-chip counters for network management
Back-to-back transmit at 100 Mbps

• EEPROM support
• Support for both 10 Mbps and 100 Mbps Networks
• Interface to Mil compliant PHY devices, including
Intel 82553 Physical Interface component for
10 Mbps/100 Mbps designs
• IEEE 802.3 100BASE-T, TX, and T4 compatible
• Interface to Intel 82503 or other serial device for
10 Mbps designs: IEEE 802.3 1OBASE-T compatible
• Autodetect and autoswitching for 10 Mbps or
100 Mbps network speeds
• Full or half duplex-capable at 10 Mbps and
100 Mbps
• 160-Lead QFP package

1.3 Compliance to Industry Standards
The 82557 has two interfaces. The host system PCI
bus interface and the serial or network interface.
The network interface complies to the IEEE standard for 10Base-T, TX, and T4 Ethernet interfaces.
The 82557 also complies to the PCI Bus Specification, Revision 2.1.

1.4 Other Literature
This data sheet provides complete pin identification,
definitions and electrical specifications. It also provides an overview of each main subsystem within
the component. Most of this information is aimed at
hardware design engineers.
Software engineers and others who are designing
interfaces or writing device drivers for this component, should refer to the 82557 User's Guide. This
document provides more detailed information on
feature sets, register descriptions and implementation steps for various functions.

1-263

82557

2.0

PIN DEFINITIONS

Figure 2 shows pin numbering and signal identification for the 82557. Sections 2.1 through 2.4 describe the
signals.

0
TXD3
TXD2
vee
Vss
TXDI
TXDO
TXClK
Vec
Vss
Vss
vee
RST
GNT
REQ
vee
Vss
INTA
AD31
AD30
vee
Vss
AD29
AD28
ClK
AD27
AD26
vee
Vss
AD25
AD24
vee
Vss
IDSEl
CBE3
AD23
vee
VSS
AD22
AD21

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104

Intel 82557
[Top View]

102
101
99
98

95

81

FlADDR 1
FlADDR2
FlADDR3
Vee
Vss
FlADDR4
FlADDR5
Vee
Vss
Vss
Vee
FlADDR6
FlADDR7
FlADDR8
Vee
Vss
FlADDR9
FlADDR10
FlADDR 11
FlWE
Vee
Vss
FLOE
Vee
FlCS
Vss
ADO
ADI
Vee
Vss
AD2
AD3
Vce
Vss
AD4
AD5
Vss
Vee
AD6
AD7

290545-2

NOTE:
See Section 2.3 for special notations on pins 1 and 144

Figure 2. Device Pinout, Top View

1-264

I

82557

2.1 PCI Bus Interface Signals
The following sections describe the 82557 pins and
signals by function.

2.1.1 SIGNAL TYPE DEFINITION
IN

Input is a standard input-only signal.

OUT

Totem Pole Output is a standard active
driver.

TS

Tri-State is a bi-directional, tri-state
input! output pin.

STS

Sustained Tri-State is an active low tristate signal owned and driven by the
82557. When the 82557 drives this pin
low, it must drivE1 it high for at least one
clock before letting it float.

00

Open Drain allows multiple devices to
share as a wire-OR.

1-265

82557

2.1.2 ADDRESS AND DATA PINS
Symbol

Pin

Type

Name and Function

ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

94
93
90
89
86
85
82
81
77
74
73
72
71
68
67
66
49
48
47
44
43
40
39
36
31
30
27
26
24
23
20
19

TS

Address and Data are multiplexed on the same PCI pins by the 82557. A bus
transaction consists of an address phase followed by one or more data
phases. The address phase is the clock cycle in which FRAME is asserted.
During the address phase ADO-31 contain a physical address (32 bits). For
I/O, this is a byte address; for configuration and memory it is a DWORD
address. The 82557 used "Little Endian" byte ordering. During data phases
ADO-7 contain the least significant byte (L8B) and AD24-31 contain the most
significant byte (M8B).

CBEO
CBE1
CBE2
CBE3

78
65
50
35

T8

Bus Command and Byte Enables are multiplexed on the same PCI pins by the
82557. During the address phase of a transaction, C/BEO-3 define the bus
command. During the data phase C/BEO-3 are used as Byte Enables. The
Byte Enables are valid for the entire data phase and determine which byte
lanes carry meaningful data. C/BEO applies to byte 0 (LSB) and C/BE3 applies
to byte 3 (M8B).

PAR

62

T8

Parity is even parity across ADO-31 and C/BEO-3. PAR is stable and valid one
clock after the address phase. For data phases, PAR is stable and valid one
clock after either IRDY is asserted on a write transaction or TRDY is asserted
on a read transaction. Once PAR is valid, it remains valid until one clock after
the completion of the current data phase. When the 82557 is a bus master, it
. drives PAR for address and write data phases. As a slave, it drives PAR for
read data phases.

1·266

82557

2.1.3 INTERFACE CONTROL PINS
Symbol

Pin

Type

Name and Function

FRAME

53

STS

FRAME is driven by the 82557 to indicate the beginning and duration of an
access. FRAME is asserted to indicate a bus transaction is beginning. While
FRAME is asserted, data transfers continue. When FRAME is deasserted, the
transaction is in the final data phase.

IRDY

54

STS

INITIATOR READY indicates the ability of the 82557 (as a bus mastering
device) to complete the current data phase of the transaction. IRDY is used in
conjunction with TROY. A data phase is completed on any clock in which both
IRDY and TROY are sampled asserted. During a write, IRDY indicates that
valid data is present on ADO-31. During a read, it indicates the master is
prepared to accept data. Wait cycles are inserted until both IRDY and TROY
are asserted together. The 82557 drives IRDY when acting as a master, and
samples it when acting as a slave.

TROY

55

STS

TARGET READY indicates the ability of the 82557 (as a selected device) to
complete the current data phase of the transaction. TROY is used in
conjunction with IRDY. A data phase is completed on any clock in which both
TROY and IRDY are sampled asserted. During a read, TROY indicates that
valid data is present on ADO-31. During a write, it indicates the target is
prepared to accept data. Wait cycles are inserted until both IRDY and TROY
are asserted together. The 82557 drives TROY when acting as a slave, and
samples it when acting as a master.

STOP

59

STS

STOP indicates the current target is requesting the master to stop the current
transaction. As a slave, the 82557 drives STOP to inform the bus master to
stop the current transaction. As a bus master, the 82557 receives STOP from
the slave and stops the current transaction.

IDSEL

34

IN

DEVSEL

56

STS

Initialization Device Select is used by the 82557 as a chip select during
configuration read and write transactions.
DEVICE SELECT, when actively driven by the 82557 as a slave, indicates to
the bus master that it has decoded its address as the target of the current
access. As an input, DEVSEL indicates whether any device on the bus has
been selected.

2.1.4 ERROR REPORTING PINS
Symbol

Pin

Type

Name and Function

SERR

60

00

SYSTEM ERROR is used by the 82557 to report address parity errors. SERR is
open drain and is actively driven for a single PCI clock when reporting the error.

PERR

61

STS

PARITY ERROR is used by the 82557 for reporting data parity errors during all
PCI transactions except a Special Cycle. The PERR pin is sustained tri-state
and must be driven active by the 82557 receiving data two clocks following the
data when a data parity error is detected. The minimum duration of PERR is
one clock for each data phase that a data parity error is detected.

1-267

82557

2.1.5 INTERRUPT PIN
Symbol

Pin

Type

INTA

18

00

Name and Function
INTERRUPT A is used to request an interrupt by the 82557. This is an active
low, level-triggered interrupt signal.

2.1.6 ARBITRATION PINS
Symbol

Pin

Type

Name and Function

REO

15

TS

REOUEST indicates to the arbiter that the 82557 desires use of the bus. This is
a point to point signal. Every master has its own REO.

GNT

14

IN

GRANT indicates to the 82557 that access to the bus has been granted. This
is a point to point signal.
.

2.1.7 SYSTEM PINS
Symbol

Pin

Type

Name and Function

ClK

25

IN

Clock provides timing for all transactions on the PCI bus and is an input to the
82557. All other PCI signals, except RST and the INT lines are sampled on the
rising edge of ClK and all other timing parameters are defined with respect to
this edge.

RST

13

IN

RESET is used to bring PC I-specific registers, sequencers and signals to a
, consistent state. Anytime RST is asserted, all PCI output signals must be
driven to their benign state. In general, this means they must be tri-stated.
SERR (open drain) is floated. To prevent AD, CIBE and PAR signals from
floating during reset, the central device may drive these lines during reset (bus
parking) but only to a logic low level-they may not be driven high.

1·268

82557

2.2 Local Memory Interface
Pin

Type

EECS

Symbol

138

OUT

FLDOEESK

135

TS

Multiplexed pin. During flash access acts as FLASH Data 0 input/output.
During EEPROM access acts as EEPROM SHIFT CLOCK output to shift
data into and out of the serial EEPROM.

FLD1EEDO

134

TS

Multiplexed pin. During flash access acts as FLASH Data 1 input/output.
During EEPROM access, this pin acts as the input EEPROM DATA OUT.

FLD2EEDI

133

TS

Multiplexed pin. During flash access acts as FLASH Data 2 input/output.
During EEPROM access, this pin acts as the output EEPROM DATA IN.

FLD3
FLD4
FLD5
FLD6
FLD7

130
129
128
127
124

TS

FLASH Data 7 to 3 input/outputs.

FLADDRO
FLADDR1
FLADDR2
FLADDR3
FLADDR4
FLADDR5
FLADDR6
FLADDR7
FLADDR8
FLADDR9
FLADDR10
FLADDR11

123
120
119
118
115
114
109
108
107
104
103
102

OUT

FLASH Address 11 to O. These 12 pins work in conjunction with an
external 8-bit Address Latch to control the FLASH addressing up to
1 Mbyte. The 8 most significant FLASH address pins (FLADDR11 to 4)
should be connected to both the Address Latch and to Address Pins 11
to 4 of the FLASH. The Address Latch provides the upper 8 bits, 19 to 12,
of address to the FLASH and is loaded by assertion of the FLCS pin.

96

OUT

FLASH CS will normally be high to disable access to the FLASH.
Whenever a FLASH high address is to be latched, FLCS will go low, thus
latching the data in the latch and enabling the FLASH. FLCS should be
connected to both the ENABLE pin on the external address latch and the
CE pin on the FLASH.

FLOE

98

OUT

This output provides the active low Output Enable control to the FLASH.

FLWE

101

OUT

This output provides the active low Write Enable control to the FLASH.

FLCS

Name and Function
EEPROM Chip Select: Active high signal used to assert Chip Select to the
serial EEPROM.

1-269

intet~

82557

2.3 Mil/Serial Interface Pins
Pin

Type

RXCLK

151

IN

Receive Clock input operates at either 25 MHz, 2.5 MHz (Mil Mode), or
10 MHz (10 Mbps-only mode).

RXDO
RXD1
RXD2
RXD3

150
149
148
147

IN

Receive Data. In Mil mode: nibble wide receive data inputs. In 10 Mbps
only mode, RXDO is the serial receive data input.

RXDV

153

IN

Receive DataValid indicates that valid data is present on the RXD lines.
Used for Mil mode only. When this pin is inactive (lOw), receive data is not
sampled by the 82557.

RXER

152

IN

Receive Data Error. Indicates that an invalid symbol has been detected
inside a receive packet. Mil mode only.

-

No connection.

Symbol

Reserved
CRS

1

Name and Function

155

IN

Carrier Sense. Indicates traffic on the wire

TXCLK

8

IN

Transmit Clock input operates at either 25 MHz, 2.5 MHz (Mil Mode), or
10 MHz (10 Mbps-only mode).

TXDO
TXD1
TXD2
TXD3

7
6
3
2

OUT

Transmit Data. In Mil mode: nibble wide transmit data outputs. In 10 Mbps
only mode: TXDO is the serial transmit data output.

158

OUT

Request To Send. Indicates that the 82557 has a frame pending for
transmission (10 Mbps-only mode)

RTS/TXEN

Transmit Enable. Indicates that the 82557 is transferring data to the PHY
(Mil mode).
COL

154

IN

Collision Detect. Indicates a collision has been detected on the wire. In Full
Duplex mode, assertion of COL indicates a Congestion condition has
occurred.
Tie high witha 3.3 KO pull"up resistor.

Reserved

144

IN

RSTOUT

146

OUT

LPBCK

145

OUT

FDX

143

IN

Full Duplex is an input from the physical layer component indicating if it 'has
switched into or out of full duplex mode. FDX is active low.

OUT

When active, indicates 82557 is in full duplex mode. This pin is multiplexed
with the TXD1 pin and operates only when in 10 Mbps-only mode.

FULHAL

6

Reset Out signal to the PHY, driven high during H/W reset of the 82557.
Loopback controls the PHY into loopback mode.

MDIO

156

TS

Management Data Input/Output. Bidirectional signal between the 82557
and an Mil-compatible PHY. It is used to transfer control information and
status between the 82557 and the PHY. Control information is driven by
the 82557 on the MDIO synchronously to MDC and sampled
synchronously by PHY. Status information is driven synchronously by PHY
and sampled synchronously by 82557.

MDC

157

OUT

Management Data Clock. Timing reference for transfer of control
information and status on the MDIO signal. The frequency of this clock is·
up to 2.5 MHz..

1-270

82557

2.4 Power and Ground
Symbol

Type

Pin

Name and Function

+ 5V ,± 5%.

Vee

4,9,12,16,21,28,32,37,42,45,51,57,63,69,75,79,83,
88,92,97,100,106,110,113,117,122,126,132,137,159

IN

Power:

VSS

5,10,11,17,22,29,33,38,41,46,52,58,64,70,76,80,84,
87,91,95,99; 105, 111, 112, 116, 121, 125, 131, 136, 160

IN

Ground: OV.

3.0

82557 ARCHITECTURE
OVERVIEW

Figure 1 (on the cover) shows a high level block
diagram of the 82557 part. It is divided into three
main subsystems: a parallel subsystem, a FIFO subsystem and the 10 Mbps/100 Mbps CSMAlCD unit.

3.1

Parallel Subsystem Overview

The parallel subsystem is broken down into several
functional blocks: a PCI Bus Master Interface, a Micro Machine processing unit and its corresponding
microcode ROM and a PCI Target Control/FLASH/
EEPROM interface. The parallel subsystem also interfaces to the FIFO subsystem, passing data (XMT,
RCV and Configuration), command and status parameters between these two blocks.
The PCI Bus Master Interface provides a complete
interface to.a PCI bus and is compliant with revision
2.1 of the PCI Bus Specification. No external logic is
required to interface the 82557 to a PCI bus. The
82557 provides 32 bits of addressing and data, as
well as the cqmplete control interface to operate on
a PCI bus. As a PCI Target, it follows the PCI Configuration format which allows all accesses to the
82557 (control register, FLASH accesses, boot, etc.)
to be automatically mapped into free memory and
I/O space upon initialization of a PCI system. For
processing of XMT and RCV frames, the 82557 operates as a master on the PCI bus, initiating zero
wait state transfers for accessing these data parameters.
The PCI Bus Master Interface consists of three
units. The Bus Interface Unit (BIU) controls the access to the PCI bus according to the bus protocol.

The BIU controls such actions as initiating when to
request or relinquish the external PCI bus and handles internal DMA (XMT, RCV, or Control) channel
arbitration. The Data Interface Unit (DIU) routs data
into and out of the 82557 at high speed data transfers. The DMA unit controls the addressing for four
separate DMA channels.
The 82557 Control/Status Register Block is contained as part of the PCI Target element. The Control/Status Register Block consists of the following
82557 internal control registers: SCB, PORT, FLASH
control register, EEPROM control register and MDI
Control register. Refer to the 82557 User's Guide for
more information on the Control/Status Register
Block.
The Micro Machine is an embedded processing unit
contained in the 82557. The Micro Machine accesses the 82557 microcode ROM working its way
through the op-codes (or instructions) contained in
the ROM to perform its functions. Parameters accessed from memory such as Transmit Buffer Descriptor fields or pointers to data buffers are also
used by the Micro Machine during processing of
RCV or XMT frames by the 82557. A typical function
of the Micro Machine would be to take a data buffer
pointer field and load it into the 82557 DMA unit for
direct access to the data buffer. The Micro Machine
is divided into two units, a Receive Unit and a Command Unit (including XMT functions). These two
units operate independently and concurrently. Control is switched between the two units according to
the microcode instruction flow. The independence of
the Receive and Command units of the Micro Machine allows the 82557 to execute commands and
receive incoming frames simultaneously, with no
real-time CPU intervention.

1-271

82557
The 82557 centains an interface te beth an external
FLASH memery and an external serial EEPROM.
The FLASH interface, which ceuld alse be used te
cennect te any standard 8-bit EPROM device, prevides up to 1 MByte .of addressing te the FLASH. It
utilizes a multiplexed address scheme that werks in
cenjunctien with an LS373 .or cempatible latch te demultiplex the address. Beth Read and Write accesses are supperted. With .out the latch,up te 16 Kbytes
can be addressed. The FLASH may be used fer remete beet functiens, netwerk statistical and diagnestics functiens, etc. The FLASH is mapped inte
hest .system ,memery (anywhere within the 32-bit
memery address space) fer seftware accesses. It is
alse mapped inte an available beet expansien ROM
lecatien during beet time .of the system. Fer more
infermatien on the FLASH interface, see Sectien
4.1.3. The EEPROM is used te stere relevant infermatien fer a LAN cennection such as Nede Individual Address, as well as beard manufacturing and cenfiguratien infermatien. Beth Read and Write accesses te the EEPROM are supperted by the 82557. Fer
mere· infermatien on the EEPROM interface, see
Sectien 4.1.3.

3.2 FIFO Subsystem Overview
The 82557 FIFO subsystem censists of a large
transmit FIFO and large receive FIFO. Each FIFO is
unidirectienal and independent .of the ether. The
FIFO subsystem serves as the interface between
the 82557 parallel side and the serial CSMAlCD
unit. It prevides a temperary buffer sterage area fer
frames as they are either being received .or transmitted by the 82557. This allews fer several important
features in the 82557:
.
,. Transmit frames can be queued within the XMT
FIFO,allewing back te back transmissien within
the minimum inter-frame spacing (IFS). '
• The 'sterage area in the FIFO area allews the"
82557 te withstand leng PCI Bus latencies with.out lesing inceming data .or cerrupting eutgeing
data.
• The 82557 XMT FIFO Thresheld allews the transmit start thresheld te be tuned te eliminate underruns while cencurrent transmits are being perfermed.
• The FIFO subsectien allews extended PCI 0 Wait
State burst accesses te .or frem the 82557 fer
beth RCV and XMT frames, since the transfer is
te the FIFO sterage area as eppesed te directly
te the serial link.

1-272

• Transmissiens resulting in errers (CDT, Underrun)
are retransmitted directly frem the 82557 FIFO,
increasing perfermance and eliminating the need
te reaccess this data frem the hest system.
.Inceming Runt RCV Frames (less than the legal
minimum frame size) can be discarded autematically by the 82557 witheut transferring this faulty
data te the hest system.'

3.3 10 Mbps/100 Mbps Serial CSMAI
CD Unit Overview
.
The CSMAlCD unit .of the 82557 allews it te be cennected te either a 10 Mbps .or 100 Mbps Ethernet
netwerk. The 82557 interfaces te either an IEEE
802.3 10 Mbps/100 Mbps Mllcempatitile PHY device .or a 10 Mbps-enly IEEE 802.3 PHY. In the case
.of the Mil cempatible PHY, the 82557 can switch
autematically between 10Mbps .or 100 Mbps epera-'
tien depending en the speed .of the netwerk. The
CSMAlCD unit perferms all .of the functiens .of the
802.3 pretecel .such as frame fermatting, frame stripping, cellisien handling, deferral te link traffic, etc.
The CSMAlCD unit can alse be placed in a Full Duplex mede which allews fer simultaneeus transmis.sien and receptien .of frames. The' CSMAlCD unit
accepts data frem the 82557 XMT FIFO and' cenverts it te either serial .or nibble-wide (Mil Cempatible
mede) data fer transmissien en the link. During receptien, the CSMAlCD unit cenverts data frem either serial .or nibbie-wide'data te a byte-wide fermat
and transfers it te the ReV FIFO .of thE! 82557. The
CSMAlCD unit centains a Management Data Interface (MDI) te an Mil cempliant PHY. This allews centrel and status. parameters te be passed between
the 82557 and the PHY(parameters specified by
se.ftware) by .one serial pin and a clecking pin, reducing the number .of centrel pins needed fer PHY mede
centrel.

4.0

THE 82557 HARDWARE
INTERFACE

4.1 PCI Bus Interface
The PCI bus interface enables the 82557 te interact
with the hest system via the PCI bus. It prevides the
centrel, address and data interface te implement a

82557
PCI compliant interface. The 82557 operates as
both a master and slave on the PCI bus. As a master, the 82557 interacts with the system main memory to access data for transmission or deposit received data.
As a slave, some 82557 control structures are accessed by the host CPU which reads or writes to
these on-chip registers. The CPU provides the
82557 with the necessary action commands, control
commands and pointers which enable the 82557 to
process RCV and XMT data. The PCI bus interface
also provides the means for configuring PCI parameters in the 82557. Refer to the PCI Bus Interface
Specification for more details specific to the PCI bus.
4.1.1 PCI CONFIGURATION

The configuration process in a PCI system starts before anything else. The 82557 is actually disconnected from the PCI bus until it is configured. At this
stage it responds to configuration cycles only. This
subsection provides a detailed description of the PCI
configuration process from S/W and H/W point of
view. Specifically, it defines the programming model
and usage rules for the configuration register space
of the 82557.
The82557 supports all mandatory required registers
along with specific registers that are needed for its
operation. Mainly, it implements several Base Address registers. These registers and their purpose
will be described in details later on. For more con-'
cise information refer to the PCI System Design
Guide.
4.1.1.1 PCI Configuration Space Organization

The organization of configuration space registers as
defined in the PCI specification is shown in Figure 3.
This region consists of fields that uniquely identify
the 82557 and allow it to be generically controlled.
The 82557 treats configuration space write operations to reserved registers as no-ops (the data written is ignored). Read accesses to reserved or undefined registers will always return a data value of all
zeros. For all accesses to the PCI Configuration
Registers, the 82557 will disconnect ,from the bus
following each access. In other words, no burst accesses may be made to these registers.

Figure 3 shows the layout of the 64-byte predefined
header portion of the 256-byte configuration space
that every PCI device must support. These registers
are known as the PCI Configuration Registers in the
82557. Devices must place any necessary device
specific registers only in locations 64 through 255.
Currently, the 82557 does not implement any register beyond the 64-byte predefined header portion.
All multibyte numeric fields follow little-endian ordering. That is, lower addresses contain the least significant parts of the field. Software must take care to
deal correctly with bit-encoded fields that have
some bits reserved for future use.
On reads, software must use appropriate masks to
extract the defined bits, and may not rely on reserved bits being any particular value. On writes,
software must ensure, that the values of reserved bit
positions are preserved. That is, the values of reserved bit positions must first be read, merged with
the new values for other bit positions and the data
then written back. Section 4.1.2 describes the registers in the predefined header portion of the configuration space. It also specifies which registers are reserved and which ones are implemented.
The predefined header portion of the configuration
space is divided into two parts. The first 16 bytes are
defined the same for all types of PCI compliant devices. The 82557, as a PCI compliant device, supports the Vendor 10, Device 10, Command and
Status fields in the header. Implementation of the
other registers is optional (Le., they can be treated
as reserved registers). The specific implementation
of these resisters in the 82557 is described in Section 4.1.2.
4.1.1.2 PCI Configuration Registers

This section lists and describes all PCI registers defined in the predefined header portion of the configuration space that are supported and implemented in
the 82557. All reserved registers are also specified.
Configuration space is intended for configuration, initialization, and catastrophic error handling functions.
Its use should be restricted to initialization software
and error handling software. All operational software
must continue to use I/O and/or memory space accesses to manipulate device registers. The PCI configuration registers are described' while partitioned
into several groups according to their functionality.

1-273

82557

~

"

Device ID
Status

Vendor ID

OOh

Command

04h

Class Code
BIST

I

Header
Type

Latency
Timer

Revision ID

OBh

Cache Line
Size

OCh

CSR Mem Mapped Base Addr Register

10h

CSR 1/0 Mapped Base Address Register

14h

FLASH Mem Mapped Base Addr Register

1Bh

Reserved B ase Address Register

1Ch

Reserved B ase Address Register

20h

Reserved B ase Address Register

24h

Reserved

2Bh

Reserved

2Ch

Expansion ROM Base Address
Reserved

34h

Reserved
Max_Lat

I

Min - Gnt

30h

3Bh

Interrupt
Pin

Interrupt
Line

3Ch
290545-3

Figure 3. PCI Configuration Registers
4.1.1.2.1 DEVICE IDENTIFICATION REGISTERS

4.1.1.2.2 PCI COMMAND REGISTER

Five fields in the predefined header deal with device
identification. The 82557, as a PCI compliant device,
implements them as required. These registers
(fields) enable generic configuration software to eas·
ily determine what devices are available on the system's PCI bus{ses). All of these registers are readonly. The description of their functionality and their
assigned value in the 82557 is given in Table 1.
Their location (offset) in the PCI configuration space
in given in Figure 3.

The PCI Command Register provides control over
the 82557's ability to generate and respond to PCI
cycles. When a 0 is written to this register, the 82557
is logically disconnected from the PCI bus for all accesses except configuration accesses. Figure 4
shows the layout of the register and Table 2 explains
the meanings of the different bits in the Command
register. Table 2 also gives the defa.ult value of this
register upon power up and the specific implementation of individual bits in the 82557 (i.e., RIO or R/W).

1-274

82557

Table 1. Device Identification Registers
Register

Description

Vendor 10

This field identifies the manufacturer of the device. Valid vendor identifiers are allocated by
the PCI SIG to ensure uniqueness. The vendor 10 value for the 82557 is always 8086 and
is read-only.

Device 10

This field identifies the particular device. This identifier is allocated by the vendor. The
device 10 for the 82557 is 1229 and is read-only.

Revision 10

This read-only register specifies the 82557 stepping.

Header Type

This byte identifies the layout of bytes 1Oh through 3Fh in configuration space and also
whether or not the device contains multiple functions. The 82557 Header Type of OOh
specifies the layout shown in Figure 3 and indicates a single function device. This field is
read-only.

Class Code

The Class Code register is read-only and is used to identify the generic function of the
device and (in some cases) a specific register-leitel programming interface. The register is
broken into three byte-size fields. The upper byte, 02h is a base class code and specifies
the 82557 as a Network Controller. The middle byte is a sub-class code, OOh which
specifies Ethernet Controller. 'The lower byte identifies a specific register-level
programming interface and the 82~57 always returns OOh in this field.

15

10

Reserved
I

9

8

7

6

5

4

3

2

o

I I I I , I , I I I , II
,, ':-- I

~' :' "

'i'

' i'

'

Fast Back-to-Back Enable
SERR enable
Wait cycle control
Parity Error Response
VGA Palette snoop
Memo ry Write and Invalidate Enable
SpeciaI Cycles
Bus Master
Memo ry Space
IOSpace

290545-4

Figure 4. PCI Command Register Layout

1-275

82557
Table 2. PCI Command Register Bits
Bit #

0

Bit Name
. 10 Space

Description

Controls a device's response to liD space accesses. A value of 0 disables the
device response. A value of 1 allows the device to respond to I/O space
accesses. The specific implementation of this bit in the 82557 is configurable
with default value O.

1

Mem Space

Controls a device's response to memory space accesses. A value of 0 disables
the device response. A value of 1 allows the device to respond to Memory
space accesses. This bit is configurable in the 82557 with a default value O.

2

Bus Master

Controls a device's ability to act as a master on the PCI bus. A value of 0
disables the device from generating PCI accesses. A value of 1 allows the
device to behave as a bus master. This bit is configurable in the 82557 with a
default value O.

3

Special Cycle

Controls a device's action on Special Cycle operations. A value of 0 causes the
device to ignore all Special Cycle operations. This bit is always set to 0 in the
82557.

4

MemWR&
Invalidate En

This is an enable bit for using the Memory Write and Invalidate command. This
bit is always set to 0 in the 82557 (disabled).

5

VGA Palette
Snoop

This bit controls how VGA compatible devices handle accesses to their palette
registers. This bit is always set to a 0 in the 82557 (disabled).

6

Parity Error
Response

This bit controls the 82557's response to parity errors. When the bit is set, the
82557 takes its normal action when a parity error is detected. When the bit is
reset, the 82557 ignores any parity errors that it detects and continues normal
operation. This bit must be set to 0 after RST. This bit is configurable in the
82557 with a default value O.

7

Wait Cycle
Control

This bit, when set to a 1, is used to control whether or not a device does
address/data stepping. This bit is always set to 0 in the 82557 (disabled).

8

Serr Enable

This bit is an enable bit for the SERR driver. A value of 0 disables the SERR
driver. A value of 1 enables theSERR driver. This bit (and bit 6, Perr Enable)
must be on to report address parity errors. This bit is configurable in the 82557
with a default value of O.

9

Fast Back-toBack Enable

This bit controls whether or not a master can do fast back-to-back transactions
to different devices. This bit is set to a 0 in the 82557, fast back-to-back
transactions are only allowed to the same agent.

Reserved

Reserved. These bits are hardwired to 0 in the 82557.

10-15

1-276

82557
in Table 4. Reads to this register behave normally.
Writes are slightly different in that bits can be reset,
but not set. A bit is reset whenever the register is
written, and the data in the corresponding .bit location is a 1. For instance, to clear bit 14 and not affect
any other bits, write the value 0100_0000_0000_
OOOOb to the register.

4.1_1.2.3 PCI STATUS REGISTER
The PCI Status Register is used to record status information for PCI bus related events. The definition
of each of the bits is given in Table 3 and the layout
of the register is shown in Figure 5. The specific
implementation of each bit in the 82557 is also given

15 14 13 12 11 10

9 8 .7

o

6
Reserved

I

I,

I

I

I
'[\

I
'[\

,I

1

I

I
'[\

I

L

I

Fast Back-to-Back Capabl e
Data Parity Detected
DEVSEL timing
00 - fast
01 • medium
10· slow
Signaled Target Abort
Received Target Abort
Received Master Abort
Signaled System Error
Detected Parity Error
290545-5

Figure 5. PCI Status Register Layout

1-277

82557

Table 3. PCI Status Register Bits
Bit #

Bit Location

0-6

Reserved

Reserved. These bits are hardwired to 0 in the 82557.

7

Fast Backto-Back
Capable

This read-only bit indicates whether or not the target is capable 6f accepting fast
back-to-back transactions when the transactions are not to the same agent. The
value of this bit in the 82557 is 1 (Fast Back-to-Back Capable).

8

Data Parity
Detected

This bit is set when three conditions are met: 1) the bus agent asserted PERR
itself or observed PERR asserted; 2) the agent setting the bit acted as the bus
master for the operation in which the error occurred; 3) the Parity Error
Response bit (Command Register) is set. The initial value of this bit in the 82557
isO.

DEVSEL
Timing

These bits encode the timing of DEVSEL. There are three allowable timings for
assertion of DEVSEL. These are encoded as OOb for fast, 01 b for medium, and
1 Ob for slow (11 b is reserved). The value of these bits are always set to 01
(medium).

11

Signaled
Target Abort

This bit must be set by a target device whenever it terminates a transaction with
target-abort~ The value of this bit is always O.

12

Received
Target Abort

This bit must be set by a master device whenever its transaction is terminated
with target-abort. The initial value of this bit in the 82557 is O.

13

Received
MasterAbort

This bit must be set by a master device whenever its transaction (except for
Special Cycle) is terminated with master-abort. The initial value of this bit in the
82557 is O.

14

Signalled
System Error

This bit must be set whenever the device asserts SERR. The initial value of this
bit in the 82557 is O.

15

Detected
Parity Error

This bit must be set by the device whenever it detects a parity error, even if parity
error handling is disabled (as controlled by bit 6 in the Command register). The
initial value of this bit in the 82557 is O.

9-10

1-278

Description

82557
4.1.1.2.4 MISCELLANEOUS PCI
CONFIGURATION REGISTERS

This section describes the registers that are device
independent and only need to be implemented by
devices that provide the described function. The
specific implementation of each register for the
82557 is also provided.

Table 4. Miscellaneous PCI Configuration Bits
Register

Description

Cache Line
Size

This register is not implemented in
the 82557. The value of this field is
fixed to O.

Latency
Timer

The 82557, as a master device,
implements this register to limit the
size of very long burst cycles. The
initial value is 0 and is then
programmed by system BIOS at
initialization time.

Built·ln Self
Test (BIST)

This optional register is used for
control and status of BIST. The
82557 will not provide PCI BIST
and the value of this field is always
set to O.

Interrupt
Line

The Interrupt Line register is an
8·bit register used to communicate
interrupt line routing information.
This register is configurable in the
82557. POST software will write
the routing information into this
register as it initializes and
configures the system. The value in
this register tells which input of the
system interrupt controller(s) the
device's interrupt pin is connected
to. Device drivers and operating
systems can then use this
information to determine priority
and vector information.

Interrupt Pin

The Interrupt Pin register tells
which interrupt pin the device (or
device function) uses. This eight bit
register is always set to a 1 in the
82557, indicating INTA is used.

MIN_GNTI
MALLAT

These read·only byte registers are
used to specify the devices desired
settings for Latency Timer values.
For both registers, the value
specifies a period of time in units of
microsecond. MIN_GNT is used
for specifying how long a burst
period the device needs assuming
a clock rate of 33 MHz. MALLAT
is used for specifying how often the
device needs to gain access to the
PCI bus. The values of these
registers are 8h (2 ~s) for
MIN_GNT and 38h (14 ~s) for
MALLAT.

4.1.1.2.5 BASE ADDRESS REGISTERS

One of the most important functions for enabling suo
perior configurability and ease of use is the ability to
relocate PCI devices in the address spaces. At sys·
tem power·up device independent software must be
able to determine what devices are present, build a
consistent address map, and determine if a device
has an expansion ROM.
The 82557 contains three Base Address registers,
two requesting memory mapped resources, and one
requesting lID mapping. Each register is 32 bits
wide. The least significant bit in each base address
register determines whether it represents an lID or
memory space. Figures 6 and 7 show the layout of a
Base Address register for both lID and memory
mapping. After determining this information, power·
up software can map the lID and memory control·
lers into available locations and proceed with system
boot. In order to do this mapping in a device inde·
pendent manner, the base registers for this mapping
are placed in the predefined header portion of configuration space. Device drivers can then access this
configuration space to determine the mapping of a
particular device.
Bit 0 in all base registers is read·only and used to
determine whether the register maps into Memory or
lID space. Base registers that map to Memory
space must return a 0 in bit O. Base registers ,that
map to lID space must return a,1 in bit o.
Base registers that map into lID space are always
32 bits with bit 0 hardwired to a 1, bit 1 is reserved
and must return 0 on reads, and the other bits are
used to map the device into lID space.

1-279

82557

4 3 2

0

Base Address
Prefetchable

t ),

I

----------------------~

Set to one if there are no side effects on reads, the device returns all
bytes on reads regardless of the byte enables, and host bridges can
merge processor writes into this range without causing errors.
Bit must be set to zero otherwise.

Type

00 -locate anywhere in 32 bit address space
01 - locate below I Meg
10 -locate anywhere in 64 bit address space
II - reserved

Memory space indicator
290545-6

Figure 6. Base Address Register for Memory Mapping

31

210

Base Address

Reserved -----------!
10 space indicator---------!

290545-7

Figure 7. Base Address Register for I/O
The number of upper bits that a device actually implements depends on 'how much of the address
space the device will respond to. A device that
wants a 1 MB memory address space would set the
most significant 12 bits of the base address register
to be configurable, setting the other bits to o.
For its Control/Status Registers (CSR), the 82557
requires one Base Address Register to I/O Map
these registers, and one Base Address Register to
Memory Map these registers anywhere within the

1-280

32-bit memory address space. It is up to the software driver to determine which Base Address Register (I/O or Memory) to use to access the 82557 Control/Status registers. Both are always requested by
the 82557. The 82557 requires one Base Address
Register to map the accesses to an optional FLASH
memory. The size of the space requested is 1 MB,
and it is always mapped anywhere in the 32-bit
memory address space. Table 5 describes the implementation of the Base Address Registers in the
82557.

82557

l

1 0

11 10

31
Expansion ROM Base Address
(Upper 21 bits)

I

Reserved

Address decode enable

II
'I
290545-8

Figure 8. Expansion ROM Base Address Register Layout

31

19 20

Read/Write

0

Reserved (All O's)

En
290545-25

Figure 9. 82557 Expansion ROM Base Address Register Format
Table 5. 82557 Base Address Registers
Register
Location
10h

Description
Memory space for the 82557
Control/Status Registers. The size
of this space is 4 Kbytes. It will be
marked as a prefetchable space
and is mapped anywhere in the
32-bit memory address space.

14h

I/O space for 82557 Control/Status
Registers. The size of this space is
32 bytes.

18h

Memory space for the 82557 flash
buffer for accesses above 1 MB.
The size of this space is 1 MB. It will
be marked as a non-prefetchable
space and is mapped anywhere in
the 32-bit address space.

1C-27h

ReseNed. 82557 returns O.

4.1.1.2.6 EXPANSION ROM BASE ADDRESS
REGISTER
The 82557 provides an interface to a local FLASH
(or EPROM) which can be used as an expansion
ROM. A 32-bit Expansion ROM Base Address Register at offset 30h in the configuration space is defined to handle the address and size information for
boot-time access to the FLASH. Figure 8 shows how

this register is organized. The register functions exactly like a 32-bit Base Address register except that
the encoding (and usage) of the bottom bits is different. The upper 21 bits correspond to the upper 21
.bits of the Expansion ROM base address. The
82557 allows its Expansion ROM to be mapped on
any 1 MB boundary. The most significant 12 bits are
configurable to indicate the 1 MB size requirement.
Bit 0 in the register is used to control whether or not
the device accepts accesses to its expansion ROM.
When this bit is reset, the device's Expansion ROM
address space is disabled. This bit is programmed at
initialization time by the system BIOS. The Memory
Space bit in the Command register has precedence
over the Expansion ROM enable bit. A device responds to accesses to its expansion ROM only if
both the Memory Space bit and the Expansion ROM
Base Address Enable bit are set to 1 (it is reset to 0
on Reset).
4.1.1.3 PCI Configuration Cycles
As already mentioned, the PCI definition provides for
totally software driven initialization and configuration
via a separate configuration address space. This
section provides a description of the PCI commands
for accessing the PCI configuration space. For more
concise information please refer to the latest revision of the PCI Local Bus Specification.

1-281

82557
For normal accesses (Le., memory or 1/0), each device decodes its own addresses. In configuration accesses, the device selection decoding is done externally, and signaled to the PCI device via the IDSEL
pin. The 82557 becomes the target of a configuration command (RD or WR) only if its IDSEL is asserted and ADO-1 are 00 during the address phase of

the command. The addressed register in the configuration space is determined by AD2-7 and BEO-3
lines. The 82557 will support non-burst configuration
accesses of a BYTE, WORD, or DWORD. Read and
Write configuration cycles are shown in Figures 10
and 1t

290545-9

Figure 10. Configuration Read Cycle

1-282

82557

ClK

n: ___ \:
,'I

FRAME

'2
,

I

AD

IDSEl

c/BE

--H

,'4

'3
,

;1

'5

'6

---(.1>----~-

,,

'7

,

~ADDRESS X:

DATA

)---O----~,
,

,

,

:

:~'
CFG WR
BEs''(.1>':
--- , ----'--

__ .. _____ 1.
I

I

I

, (o)
--100--, ____
I

I
I

I

I

I

I

I

I
I

I
I

I
I

I
I

'~'

, <>'
I

I

I

I

"

--'---- , ----'~
I
I

I

I
I

, 0-'

DEVSEl

STOP

I
I

I
I

"

I
I

--,---- , ----'~.
I
I
I
I
I
I

I
I

..J"1"IIl

I
I
I
I

I
I

I
I

I

I
I

I

I
I
I
I

I
I
I
I

,.

--I----~---.,~'
I
I

I
I

290545-10

Figure 11. Configuration Write Cycle

I

1-283

82557

4.1.2 82557 BUS OPERATIONS

4.1.2.1.2 CONTROL/STATUS REGISTERS (CSR)
ACCESSES

4.1.2.1 General Overview

The 82557 supports zero wait state single cycle 1/0,
or memory mapped accesses to its CSR space.
Separate base address registers request 32 bytes of
both memory and 1/0 space to accomplish this.
Based on its needs, the software driver will use either 1/0 or memory mapping to access these registers. The 82557 provides 32 valid bytes of CSR,
which include the following elements:
1. SCB.
2. PORT.
3. FLASH control register.
4. EEPROM control register.
5. MOl Control register.

After configuration, the 82557 is ready for its normal
operation. As a Fast Ethernet Controller, the role of
the 825.57 is to access transmitted data or deposit
received data. In both cases the 82557, as a bus
master device, will initiate memory cycles via the PCI
bus to fetchldeposit the required data.
In order to perform these actions, the 82557 is controlled and examined by the CPU via its control and
status structures and registers. Some of these control and status structures reside on chip and some
reside in system memory. For access to its Controll
Status Registers (CSR), the 82557 serves as a slave
(target). The 82557 serves as a slave also while the
CPU accesses its 1 MB Flash buffer or its EEPROM.
The next subsection describes the 82557 slave operation. It is followed by a description of the 82557
operation as a bus master (initiator).
4.1.2.1.1 82557 SLAVE BUS OPERATION
The 82557 serves as a Slave in one of the following
cases:
• CPU accesses to the 82557 SCB control and
status structures (CSR).
• CPU accesses to the EEPROM through its control register (CSR).
• CPU accesses to the 82557 PORT address
(CSR).
• CPU accesses to the MOl control register (CSR).
• CPU accesses to the FLASH control register
(CSR).
• CPU accesses to the 1 MB FLASH.
The CSR and the 1 MB Flash buffer are considered
by the 82557 as two totally separated memory
spaces. The 82557 provides separate Base Address
Registers in the configuration space to distinguish
between them. The size of the control and status
registers memory space is 32 bytes in the 1/0 space
and 4 Kbytes in the memory space. The 82557
treats accesses to these memory spaces differently.
For more information, refer to the 82557 User's
Guide.

1-284

Figures 12 and 13 show CSR read and write cycles.
They show general zero wait state 1/0 read and
write cycles. In case of accessing the Control and
Status structures, the CPU is the initiator and the
82557 is the target of the transaction.
Read Accesses: The CPU, as the initiator, drives
the address lines ADO-31, the command and byte
enable lines C/BEO-3 and the control lines IRDY
and FRAME. As a slave, the 82557 controls the
TROY signal and provides valid data on each data
access. The 82557 allows the CPU to issue only one
read cycle when it accesses the Control and Status
registers, generating a Disconnect by asserting the
STOP signal. The CPU can insert wait states by
deasserting IRDY when it is not ready.
Write Accesses: The CPU, as the initiator, drives
the address lines ADO-31, the command and byte
enable lines C/BEO-3 and the control lines IRDY
and FRAME. It also provides the 82557 with valid
data on each data access immediately after asserting IRDY. The 82557 controls the TROY signal and
asserts it from the data access. As for read cycles,
the 82557 allows the CPU to issue only one 1/0
write cycle to the Control and Status registers, generating a Disconnect by asserting the STOP signal.
This is true for both memory mf:\pped and 1/0
mapped accesses.

82557

290545-11

Figure 12. CSR Read Cycles

290545-12

Figure 13. CSR Write Cycle

1·285

82557

4.1.2.1.3 FLASH BUFFER ACCESSES

The CPU accesses to the Flash Buffer are very slow.
For this reason the 82557 issues a target-disconnect
at the first data access. The 82557 asserts the
STOP signal to indicate a target·disconnect. Figures
14 and 15 show memory CPU read and write ac·
cesses to the 1 MB Flash Buffer. The longest Burst
cycle to the Flash Buffer contains one data access
only.
Read Accesses: The CPU, as the initiator, drives
the address lines AOO-31, the command and byte
enable lines C/BEO-3 and the control lines IROY
and FRAME. The 82557 controls the TROY signal
and deasserts it for a certain number of clocks until
valid data can be read from the Flash Buffer. When
TROY is asserted, the 82557 drives valid data on

,

,

the AOO-31 lines. The CPU can also insert wait
states by deasserting IROY until it is ready. Flash
buffer read accesses can be byte or word length.
See NOTE in Section 4.2 for additional information.
Write Accesses: The CPU, as the initiator, drives
the address lines AOO-31, the command and byte
enable lines C/BEO-3 and the control lines IROY
and FRAME. It also provides the 82557 with valid
data immediately after asserting IROY. The 82557
controls the TROY signal and deasserts it for a certain number of clocks until valid data is written to the
Flash Buffer. By asserting TROY, the 82557 signals
the CPU that the current data access is completed.
Flash buffer write accesses can be byte length only.
See NOTE in Section 4.2 for additional information.

,

CLK~

u!\
I

AD

elBE
IROY

TROY

OEVSEL

'

I

~~

!/

. . .__. . .__. . .8--"""--"';'"
!

:

-+~1"::

u:_ S

:

:~:'~BESL:----i.._:.J-)----t-----t"

-+---th :
IT, :.
:- ~I-\~---:---~-"""'--':-'
u:_ -- Q ~ II-I~~----!-\\ /
--~---~
:,

0"T.
:

--~---:

:

STOP:

,

':

:

;---r-

~I-I....'____--;..--.;....-.....;.--...;...1.

' ,
:.:

r:: -

'II~'--.......-~~

: :

\

~-----.;...I

290545-13

Figure 14. Flash Buffer Read Cycles

1-286

82557

290545-14

Figure 15. Flash Buffer Write Cycle
4.1.2.1.4 ERROR J-IANDLING
Data Parity Errors: The 82557 checks for data parity errors while it is the target of the transaction. If an
error was detected, the 82557 always sets the Detected Parity Error bit (PCI Status Register, bit 15).
The 82557 also asserts PERR, if the Parity Error Response bit is set (PCI Command Register, bit 6). The
82557 does not attempt to terminate a cycle in
which a parity error was detected. This gives the initiator of the access, at each H/W or S/W level, the
option of recovery.
Target-Disconnect: The 82557 will use premature
termination in the following cases:
• After accesses to the 1 MB Flash buffer.
• After accesses to its CSA.
• After accesses to the configuration space.

System Error: The 82557 reports parity error on address phase using the SERR pin. If the SERR Enable bit (in the PCI-configuration command register)
or the Parity Error Response bit are not set, the
82557 only sets the Detected Parity Error bit (PCI
Status Register, bit 15). If SERR Enable and Parity
Error Response bits are both set, the 82557 sets the
Signaled System Error bit (PC I Status Register, bit
14) as well as the Detected Parity Error bit and asserts SERR for one clock.
The 82557, when detecting system error, will claim
the cycle if it was the target of the transaction and
continue the transaction as though the address was
correct.
NOTE:
The 82557 will report a system error for any parity
error on address phase, whether or not it is involved in the current transaction.

1-287

82557

4.1.2.1.5 82557 BUS MASTER OPERATION
As a PCI Bus Master, the 82557 initiates memory
cycles to fetch data for transmission or deposit received data, as well as for accessing the memory
resident control structures. The 82557 performs
zero wait state burst read and write cycles to the
host main memory. Figures 16 and 17 depict memory read and write burst cycles. For Bus Master cycles, the 82557 is the initiator and the host main
memory (or the PCI Host Bridge depending on the
configuration of the systems) is the target.

The CPU provides the 82557 with action commands
and pointers to the data buffers that reside in host
main memory. The 82557 independently manages
these structures and initiates burst memory cycles to
transfer data to and from them. The 82557 uses
MEM-RD Multiple for burst accesses to data buffers
and MEM-RD LINE for burst accesses to control
structures (commands, pointers, etc.). For all write
burst accesses to either data or control, the 82557
. uses the MEM-WR command. The 82557 does not
use the MEM-WR and Invalidate command.

CLK

FRAME

AD

c/SE
_IRDY

--.\
~,

--f<
-~{

:7

,

'

,

'

:

:

:

~

,----,-;: ---O----~--I
'
,

~·---~------~------~------~------~-------+JI
ADDRESS

}n

'

MEM-RD

X'-_";'-_-+__ X~--+__
,;J:

-+---~

:

---<)----:---

BE_S.:..:_ _..,.,:).-..

9----~---

i/

-+---     
< DATA> 
.

where:
PREAMBLE At the beginning of each transaction,
the 82557 sends a sequence of 32
contiguous logic one bits on the MOIO
pin with corresponding cycles on the
MOC clock pin for synchronization by
the PHY.
.
ST

A Start of Frame pattern of 01.

OP

An Operation Code which can assume
one of two values:

PHYAD

REGAD

TA

DATA

IDLE

1-294

10 Read
01 Write
A 5-bit address of the PHY device
.which provides support for 32 unique
PHY addresses. The 82557 will drive
the value written into the PHYAO portion of the MOl register in this field.
A 5-bit address of the specific register
within the PHY device. Provides support for 32 unique registers. The desired register address is specified by
the value written to the MOl register.
A two-bit turnaround time during which
no device actively drives the MOIO signal on a Read cycle. Ouring a Read
transaction the PHY should not drive
MOIO in the first bit time and drive a 0
in the second bit time. Ouring a Write
transaction the 82557 will drive a 10
pattern to fill this time.
16 bits of data driven by the PHY on
Read transactions or by the 82557 on
Write transactions. This data is either
control or status parameters passed
between the 82557 and the PHY.
The IOLE condition on MOIO is a high
impedance state .. The MOIO driver is
disabled, and the PHY should pull-up
the MOIO line to a logic one.

82557 SOFTWARE INTERFACE

The 82557 establishes a shared memory communication system with the host CPU. This· shared memory is divided into three parts: the Control/Status
Registers (CSR), the Command Block List (CBL),
and the Receive Frame Area (RFA). The CSR resides on-chip and can be accessed by either 1/0 or
memory cycles, while the rest of the 82557 memory
structures reside in system (host) memory. The first
8 bytes of the CSR is called the System Control
Block (SCB). The SCB serves as a central communication point for exchanging control and status information between the host CPU and the 82557.
The host software coritrols· the state of the 82557
Command Unit (CU) and Receive Unit (RU) (e.g. Active, Suspended or Idle) by writing commands to the
SCB. The 82557 posts the status of the CU and RU
in the SCB Status wbrd and indicates status changes with an interrupt. The SCB also holds pointers to
a linked list of action commands called the CBL and
a linked list of receive resources called the RFA.
Figure 19 shows this type of structure.
The CBL consists of a linked list of individual action
commands in structures called Command Blocks
(CBs). The CBs contain command parameters and
status of the action commands. Action commands
are categorized as follows:
• Non-Tx commands: This category includes commands such as NOP, Configure,lA Setup, Multicast Setup, Oumpand Diagnose.
• Tx command: This includes Transmit Command
Blocks (TxCB).

82557

System Control
Block (SCB)

82557 Registers

290545-18

Figure 19. 82557 ~hared Memory Structure
Transmit commands can oe programmed in Simplified or Flexible memory modes. In the Simplified
memory model, the TxCB contains the full transmit
frame, immediately following the header information.
In the Flexible memory model, each TxCB can be
associated with an array of 0 or more Transmit Buffer Descriptors (TBD). Each TBD points to a data
. buffer fragment. All the data fragments associated
with a TxCB (including data in the optional data area
of the TxCB) comprise the full transmit frame.
The RFA consists of a list of Receive Frame Descriptors (RFD) and a list of l!ser-prepared or NOS
provided buffers. Two memory models are supported. In the Simplified memory model, the data buffer

immediately follows the RFD. In the Flexible memory
model, each RFD can be associated with a list of
zero or more Receive Buffer Descriptors (RBD).
Each RBD points to a data buffer fragment. The
82557 RU fills the buffers when it receives frames
and updates the status in the RFD (and RBDs if applicable).
The 82557 also provides read/write aCcess to external EEPROM, Flash memory and MOl (Management
Data Interface) registers. This is achieved through
the EEPROM Control Register, Flash Control Register, and the MOl Control Register respectively.
These three registers make up the last eight bytes of
the CSA.
Refer to the 82557 User's Guide for additional information.

1-295

82557

5.2 Initializing the 82557
A power-on or software reset prepares the 82557 for
normal operation. Because the PCI specification already provides for auto-configuration of many critical
parameters such as 1/0, memory mapping and inter-

rupt assignment, the 82557 is set to an operational
default state after reset. However,·the 82557 cannot
transmit or receive frames until a Configure command is issued. Refer to the 82557 User's Guide for
additional information. Table 6 lists the different reset options..

Table 6. Summary of Reset Commands
RESET
Operation

Effect on 82557

Hardware Reset

Resets all internal registers. A full initialization
sequence is needed to make the 82557 operational.

Software Reset' (issued as PORT RESEP'
command)

Resets all internal registers. A full initialization
sequence is needed to make the 82557 operational.

Selective Reset (issued as PORT SELECTIVE
RESET" command)

Maintains configuration information. All other setup
information is lost.

Self Test (issued as a PORT SELF TEST"
Command) or PORT DUMP Command

Resets all internal registers. A Selective Reset is
issued internally before the command is executed. A
Software Reset is issued internally after the command
is completed. A full initialization sequence is needed to
'make the 82557 operational.

NOTES:
• Software reset will be used throughout this manual to indicate ,a complete reset using the PORT reset command.
o. PORT commands are discussed in detail in the 82557 User's Guide.

1·296

82557
5.3 Controlling the 82557
The CPU issues control commands to the Command
Unit (CU) and Receive Unit (RU) through the SCB,
which is part of the CSR(described below). The
CPU instructs the 82557 to Activate, Suspend, Re~
sume or Idle the CU or RU by placing the appropriate control command in the CU or RU control field. A
CPU write access to the SCB causes the 82557 to
read the SCB, including the Status word, Command
word, CU and RU Control fields, and the SCB General Pointer. Activating the CU causes the 82557 to
begin executing the CBL. When execution is completed the 82557 updates the SCB with the CU
status then interrupts the CPU, if configured to do
so. Activating the RU causes the 82557 to access
the RFA and go into the READY state for frame reception. When a frame is received the RU updates
the SCB with the RU status and interrupts the CPU.
31

It also automatically advances to the next free RFO
in the RFA. This interaction between the CPU and
82557 can continue until a software reset is issued
to the 82557, at which point the initialization process
must be executed again. The CPU can also perform
certain 82557 functions directly through a CPU
PORT interface.
5.3.1 THE 82557 CONTROL/STATUS
REGISTER (CSR)
The 82557 has seven Control/Status registers
which make up the CS.R space. These are the SCB
Command word, SCB Status word, SCB General
Pointer, PORT interface, EEPROM Control register,
Flash Control register, and MOl Control register. The
CSR space is five OWOROs in length and is shown
in Figure 20. The 82557 CSR can be accessed as
either an I/O mapped or memory mapped PCI slave.

Upper Word

16 1 15

Lower Word

SCB Command Word

1

SCB Status Word

SCB General Pointer
PORT
EEPROM Control Register

1

Flash Control Register

MOl Control Register

0

Offset

+ Oh
+ 4h
Base + 8h
Base + Ch
Base + 10h
Base

Base

Figure 20. Control/Status Register

1-297

82557
SCBCommand
Word:

The CPU places commands for
the CU and RU and acknowledges interrupts in this register.

Table 7. Error Counters
Counter

Description

Transmit Good
Frames

This counter contains the
number of frames that were
transmitted properly on the link.
It is updated only after the actual
transmission on the link is
completed, and not when the
frame was read from memory as
is done for the TxCB status.

SCB Status
Word:

The 82557 places the status of
its CU and RU and interrupt indications in this register, for the
CPU to read.

SCBGeneral
Pointer:

This points to various data
structures in main memory depending on the current SCB
Command word.

PORT Interface:

This special interface allows the
CPU to reset the. 82557, force
the 82557 to dump information
to main memory, or perform an
internal Self-Test.

Transmit
Maximum
Collisions
(Maxcol)
Errors

This counter contains the
number of frames that were not
transmitted since they
encountered the configured
maximum number of collisions.

EEPROM
Control
Register:

This register allows the CPU to
read and write· to an external
EEPROM.

Flash Control
Register:

This register allows the CPU to
enable writes to an external
Flash.

Transmit Late
Collisions
(Latecol) .
Errors

This counter contains the
number of frames that were not
transmitted since they
encountered a collision later
than the configured slot time.

MOl Control
Register:

This register allows the CPU to
read and write information from
Physical Layer components via
the Management Data Interface.

Transmit·
Underrun
Errors

A DMA underrun occured
because the system bus did not
keep up with the transmission.
This counter contains the
number of frames that were
either not transmitted or
retransmitted due to a TxDMA
underrun. If the 82557 is
configured to retransmit on
underrun, this counter may be
updated multiple times for a
single frame.

Transmit Lost
Carrier. Sense
(CRS)

Transmission was not
successful due to lost Carrier
Sense. This counter contains
the number of frames that were
transmitted by the 82557
despite the fact that it detected
the deassertion of CRS during
the transmission.

Transmit
Deferred

During the transmission attempt
the 82557 had to defer to traffic
on the link. This counter
contains the number of frames
that were deferred before
transmission due to activity on
the link.

5.3.1.1 Statistical Counters
The 82557 provides information for network management statistics by providing on-chip statistical
counters that count a variety of events associated
with both transmit and receive. The counters are updated by the 82557 when it completes the processing of a frame, i.e., when it has completed transmitting a frame on the link or when it completed receiving a frame. The Statistical Counters are reported to
the software on demand by issuing the Dump Statistical Counters command in the SCB CUC field.

1-298

82557

Table 7. Error Counters (Continued)
Description

Counter

Description

Transmit Single
Collisions

This counter contains the
number of transmitted frames
that encountered one
collision.

Receive
Resource Errors

Transmit Multiple
Collisions

This counter contains the
number of transmitted frames
that encountered more than
one collision.

Transmit Total
Collisions

This counter contains the total
number of collisions that were
encountered while attempting
to transmit. This count
includes late collisions and
frames that encountered
MAXCOL.

This counter contains the
number of good frames
discarded because there were
no resources available.
Frames intended for a host
whose RU is in the No
Resources state fall into this
category. If the 82557 is
configured to Save Bad
Frames and the status of the
received frame indicates that
it is a bad frame, the
RSCERRS counter is not
updated.

Receive Overrun
Errors

This counter contains the
number of frames known to
be lost because' the local
system bus was not available.
If the traffic problem persists
for more than one frame, the
frames that follow the first are
also lost; however, because
there is no lost frame
indicator, they are not
counted.

Receive Collision
Detect (COT)
Errors

This counter contains the
number of frames that
encountered collisions during
frame reception.

Receive Short
Frame Errors

This counter contains the
number of received frames
that are shorter than the
minimum frame length. The
SHRTFRM counter is
mutually exclusive to the
ALNERRS and CRCERRS
counters and has a higher
priority (Le., a short frame will
always increment only the
SHRTFRM counter).

Counter

Receive Good
Frames

This counter contains the
number of frames that were
received properly from the
link. It is updated only after
the actual reception from the
link is completed, and all the
data bytes are stored in
memory.

ReceiveCRC
Errors

This counter contains the
number of aligned frames
discarded because of a CRC
error. This counter is updated,
if needed, regardless of the
RU state. If the RX_ER pin is
asserted during a receive
frame, the CRCERRS counter
will increment (only once per
receive frame). The
CRCERRS counter is mutually
exclusive to the ALNERRS
and SHRTFRM counters.

Receive
Alignment Errors

This counter contains the
number of frames that are
both misaligned (Le., where
CRS deasserts on a non octal
boundary) and contain a CRC
error. The counter is updated,
if needed, regardless of the
RU state. The ALNERRS
counter is mutually exclusive
to the CRCERRS and
SHRTFRM counters.

The Statistical Counters are initially set to zero by
the 82557 after reset. They cannot be preset to anything other than zero. The 82557 increments the
counters by internally reading them, incrementing
them and writing them back. This process is invisible
to the CPU and PCI bus. Refer to the 82557 User's
Guide for additional information.

1-299

intel®

82557

6.0

ELECTRICAL SPECIFICATIONS
AND TIMINGS

NOTICE: This data sheet contains preliminaryinformation on new products in production. The specificationsare subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.

6.1 Absolute Maximum Ratings

+ 85°C
Storage Temperature .......... - 65°C to + 140°C
All Output and Supply Voltages ..... - 0.5V to + 7V
Case Temperature under Bias ....... O°C to

All Input Voltages .................. -1.0V to 6.0V

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

More information on the quality and reliability of the
82557, refer to the Components Quality and Reliability Handbook, order number 210997.

6.2 DC Specifications
Table 8. General DC Specifications
Symbol

Parameter

Vee

Supply Voltage

lee

Power Supply

Condition

Min

Typ

4.75

Max

Units

5.25

V

Notes

rnA

300
Table 9. PCI Interface DC Specifications'

Symbol

Parameter

Condition

Min

VIH

Input High Voltage

2.0

VIL

Input low Voltage

-0.5

= 2.7
= 0.5
lOUT = -2 rnA
lOUT = 3 rnA, 6 rnA

Max
Vee

+ 0.5

Units

Notes

V

0.8

V

IIH

Input High leakage Current

VIN

70

p.A

1

IlL

Input low leakage Current

VIN

-70

p.A

1

VOH

Output HighVoltage

VOL

Output low Voltage

CIN

Input Pin Capacitance

CCLK

ClK Pin Capacitance

CIDSEL

IDSEl Pin Capacitance

lplN

Pin Inductance

2.4

V
0.55

5

V

2

10

. pF

3

12

pF

3

8

pF

3

20

nH

3

NOTES:
1. Input leakage currents include hi-Z output leakage for all bi·directional buffers with tri-state outputs. .
2. Signals without pullup resistors have 3 mA low output current. Signals requiring pull. up have 6 mA; the latter include,
FRAME, TROY, IROY, OEVSEL, STOP, SERR and PERR.
3. Characterized, not tested.

1-300

82557

Table 10. Mil and 10 Mbps PHY Interface DC Specifications
Symbol

Parameter

Condition

Min

VIH

Input High Voltage

2.0

VIL

Input Low Voltage

-0.5

IlL

Input Low Leakage Current

0< VIN < VCC

VOH

Output High Voltage

lOUT

VOL

Output Low Voltage

lOUT

CIN

Input Pin Capacitance

NOTES:
1. Characterized, not tested.
2. To drive an Mil cable (Zo = 6sn ± 15%, Length
Mil output.
3. For pins LPBCK and RSTOUT IOL = 1 mA.

=

=
=

-4 rnA

Max
VCC

Units

+ 0.5

0.8

V

±20

f.LA
V

2.4

4 rnA

Notes

V

0.4

V

3

8

pF

1

0.5m) a 40n ± 10% resistor should be connected in series to each

Table 11. FLASH/EEPROM Interface DC Specifications
Symbol

Parameter

Condition

Min

VIH

Input High Voltage

2.0

VIL

Input Low Voltage

-0.5

IlL

Input Low Leakage Current

0< VIN < Vcc

VOH

Output High Voltage

lOUT

=

-1 rnA

VOL

Output Low Voltage

lOUT

=

1 rnA

GIN

Input Pin Capacitance

Max
VCC

+

Units
0.5

0.8

V

±20

f.LA

2.4

Notes

V

V
0.4

V

10

pF

1

NOTE:
1. Characterized, not tested.

1·301

82557

6.3 AC Specifications
6.3.1 PCI Interface
Table 12. AC Specifications for PCI Signaling
Symbol
IOH(AC)

IOL(AC)

Parameter

Condition

Switching
Current High

0< VOUT

:s:

1,4

1,4 < VOUT < 2,4

(Test Point)

VOUT = 3.1

Switching
Current Low

VOUT:2 2.2

-44

+ (VOUT

- 104)/0.024

2.2> VOUT > 0.55

VOUT/0.023

ICL

Low Clamp
Current

-5 < VIN

tr

Unloaded Output
Rise Time

O,4V to 2,4V

1

tf

Unloaded Output
Fall Time

2,4V to Oo4V

1

-1

-25

+ (VIN +

Notes

mA

1,2

mA

1,2

-142

mA

1,2

mA

2

Eqt'n B

mA

2

206

VOUT = 0.71

Units

Eqt'nA

95

(Test Point)

:s:

Max

Min
-44

mA

2

mA

2

5

V/ns

1,2

5

V/ns

2

1)/0.015

NOTES:
1. Not relevant to SERR or INTA which are open drain outputs.
2. Characterized, not tested.

6.4 Timing Specification
6.4.1 CLOCK SPECIFICATIONS
6.4.1.1 PCI Interface Clock
The 82557 uses the PCI clock. Figure 21 shows the clock waveform and required measurement points for the
PCI clock signal. Table 13 summarizes the PCI clock specifications. This clock waveform should be treated as
minimum requirement of the 82557.

2V

p.to·p

(minimum)

1-oII1------T_cyc - - - - -__~
290545-19

Figure 21. Clock Waveform

1·302

82557

Table 13. PCI Clock Specifications
SymbGl
T1

tCYC

Parameter

Min

Units

Notes

ClK Cycle Time

30

ns

1

ns

T2

tHIGH

ClK High Time

11

T3

tLOw

ClKlowTime

11

-

T4

ClK Slew Rate

Max

ns
4

1

V/ns

2

NOTES:

1. The 82557 will work with any PCI clock frequency up to 33 MHz.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate should be met across the
minimum peak·to·peak portion of the clock waveform as shown in Figure 21.
6.4.1.2 Mil Interface Clock
The 82557 uses two clocks on the Mil interface: transmit clock (TXClK) and receive clock (RXClK). Table 14
shows timings for each clock.
Table 14. Mil Clock Specifications
Symbol

Parameter

Min

TXClK/RXClK Cycle Time

@

100 Mbps Operation

tCYC10

TXClK/RXClK Cycle Time

@

10 Mbps Operation

DC

TXClK/RXClK Duty Cycle

T5

tCYC100

T6
T7

Typ

Max

40
400
65

35

Units

Notes

ns

1,2,3

ns

1,2,3

%

1,2,3

NOTES:

1. Either high or low times of RXCLK may be extended at the event of switching it from recovered clock to TXCLK, or vice
versa.
2. No specific phase relationship is assumed between TXCLK and RXCLK.
3. When RXDV is active, the frequency difference between TXCLK and RXCLK should not exceed ± 200 ppm.
6.4.1.3 10 Mbps Serial Interface Clock
The 82557 uses two clocks on the serial interface: transmit clock TXClK and receive clock RXClK. Table 15
shows timings for both clocks.
Table 15. Serial interface Clock Specifications
Symbol

Parameter

Min

tcycTXCLK

TXClK Cycle Time

99.99

thi 10TXCLK

TXClK Duty Cycle

35

T10

tr fTXCLK

TXClK Rise/Fall Time

T11

tcycRXCLK

RXClK Cycle Time

T12

thi 10RXCLK

RXClK Duty Cycle

T13

tr fRXCLK

RXClK Rise/Fall Time

T8
T9

Typ

50

Max

Units

100.01

ns

65

%

5

ns
ns

100
35

Notes

65

%

5

ns

NOTE:

1. No specific phase relationship is assumed between TXCLK and RXCLK.

1-303

82557

6.4.2 TIMING PARAMETERS
6.4.2.1 PCI Timings
Table 16 provides the timing parameters of the 82557 for its pel interface.
Table 16. PCI Timing Parameters
Symbol

Min

Max

Units

Notes

tval

elK to Signal Valid Delay: Bussed Signals'

2

11

ns

1,2,3

T15

tval(ptp)

elK to Signal Valid Delay: Point to Poirit

2

12

ns

1,2,3

T16

tON

Float to Active Delay

2

ns

1

T14

Parameter

T17

tOFF

Active to Float Delay

ns

1

T18

tsu

Input Set Up Time to elK: Bussed Signals

7

ns

3,4

T19

tsu(ptp)

Input Set Up Time to elK: Point to Point

10

ns

3,4

T20

tH

Input Hold Time from elK

0

ns

4

T22

trst·clk

Reset Active Time after elK Stable

T23

trst-off

Reset Active to Output Float Delay

28

100
40

,""S

5

ns

5,6

NOTES:
t. See timing measurement conditions diagram in this section.
2. Minimum times are specified with 0 pF equivalent load; maximum times are specified with 50 pF equivalent load. Actual
test capacitance may vary, but results are correlated to these specifications.
3. REO and GNT are point-to-point signals, and have different output valid delay and input setup times than do bussed
signals. All other signals are bussed.
4. See timing measurement conditions in this section.
, 5. RST is asserted and deasserted asynchronously with respect to eLK.
6. All PCI ifF output drivers are floated when RST is active.

1·304

82557
6.4.2.2 Mil and 10 Mbps Interface Timings
Table 17 provides the timing parameters for Mil and serial interface signals.
Table 17. Mil and Serial Interface Timing Parameters
Symbol

Parameter

Min

Max

Units

Notes

0

15

ns

1,3

T24

tvalTX

TX Synchronous Signals Valid Time

T25

tsuRX

RX Synchronous Signals Setup Time

10

ns

2,3

T26

thRX

RX Synchronous Signals Hold Time

10

ns

2,3

T27

thiloMDC

MOC High/Low Time

200

ns

5, 7

310

ns

5,8

T28

T29

T30

tvalMD

TsuMDIO

thMDIO

MOC to MOIO Valid Oelay

MOIO Setup Time

MOIO Hold Time

50

440

ns

6, 7

50

580

ns

6,8

120

ns

6, 7

120

ns

6,8

0

ns

6

NOTES:
1. TX Synchronous Signals are: TXOO-3 and TXEN (RTS in serial inter/ace).
2. RX Synchronous Signals are: RXOO-3, RXOV and RXER.
3. The timing reference is the rising edge of TXCLK, for transmit, or RXCLK, for receive.
4. To drive an Mil cable (Zo = 6an ± 15%, Length = 0.5m) a 40n ± 10% resistor should be connected in series with
each Mil output (TXOO-3, TXEN, MOC and MOIO).
5. MOC is an aperiodic signal.
6. Referenced to rising edge of MOC.
7. These timings apply when the PCI clock rate is 33 MHz. As the PCI clock rate references the MOC/MOIO I/F these
timings scale accordingly.
a. These timings apply when the PCI clock rate is 25 MHz. As the PCI clock rate references the MOC/MOIO IIF these
timings scale accordingly.
9. The MOC/MOIO timings are specified as measured at the 82557, and as required or supplied by the 82557.
10. CRS and COL (CLO in serial inter/ace) are asynchronous with regard to either RXCLK or TXCLK.

1·305

82557

TXC

I'

. \5/\6/\11

\7/\12

'1

RXC

TXDO-3
TXEN ............................................................~ ' -_ _ _-+_..I"\•....;._ _.....;._ _J ...._ _ __

RXDOc3
RXDV
RXER

290545-24

Figure 22. Transmit Timings

6.4.2.3 Collision' Parameters

1-306

Symbol

Parameter

Units

TeOl

Collision Active to Jam Start

TXCLK Periods

82557

6.4.2.4 FLASH Interface Timings
o The 82557 is designed to support FLASH of up to

Table 18 provides the timing parameters for FLASH
interface signals. The timing parameters are illustrated in Figures 23 and 24.

150 ns access time.
• The Vpp signal in FLASH implementation should
be connected permanently to 12V. Thus, writing
to the FLASH is controlled only by the WEp sig·

.

n~.

Table 18. FLASH Interface Timing Parameters

Symbol
T31
T32

Parameter

Min

Max

Units

Notes

tllrwc

Read/Write Cycle Time

150

ns

1, flash tAVAV

= 150 ns

tllacc

FLADDR to Read FLD Setup Time

150

ns

1, flash tAVQV

T33

tllce

FLCS to Read FLD Setup Time

150

ns

1 , flash tELQV

= 150 ns
= 1 50 ns

T34

tlloe

FLOE Active to Read FLD Setup Time

120

ns

1 , flash tGLQV

= 55 ns

ttldl

FLOE Inactive to FLD Driven Delay Time

ns

1, flash tGHQZ

= 35 ns

T36

til as

FLWE Active Delay after FLADDR Stable

5

ns

2, flash tAVWL

T37

tllah

FLADDR Stable after FLWE Active

100

ns

2, flash tWLAX

= 0 ns
= 60 ns

T38

tllcs

FLWE Active Delay after FLCS Active

20

ns

2, flash tELWL

= 20 ns

T39

ttlch

FLCS Inactive Delay after FLWE Inactive

0

ns

2, flash tWHEH

T35

50

T40

tllds

FLWE Inactive Delay after FLD Stable

T41

tfldh

FLD Delay after FLWE Inactive

10

50

T42

ns

= 0 ns
2, flash tDvWH = 50 ns

ns

2, flash tWHDX

= 10 ns

tllwp

Write Pulse Width

120

ns

2, flash tWLwH

= 60 ns

T43

tflwph

Write Pulse Width High

25

ns

2, flash tWHwL

= 20 ns

T44

tlasu

FLADDR Setup Time before FLCS

4

ns

3, latch tsu

tlah

FLADDR Hold Time after FLCS

4

ns

3, latch tH

T45

= 2 ns
= 1.5 ns

NOTES:

1. These timing specilications apply to FLASH read cycles. The flash timings referenced are 28F020-150 timings.
2. These timing specifications apply to FLASH write cycles. The Ilash timings referenced are 28F020-150 timings.
3. These timing specifications apply to all FLASH cycles. The latch timings referenced are '373 timings.

1-307

82557

T31

FLCS

FLWE
T43

FLDATA-W - - - - - - - - - - - (
290545-20

Figure 23. FLASH Timings: Write Cycle

FLADDR

FLOE

FLDATA-R

---------~~t:~~~E~
290545-21

Figure 24. FLASH Timings: Read Cycle

1-308

82557

7.0

PHYSICAL ATTRIBUTES and
DIMENSIONS

This section provides the physical packaging information for the 82557. The 82557 is a 160-lead plastic quad flatpack (PQFP) device. Package attributes
are provided in Table 19 and dimensions are shown
in Figures 25 and 26. Table 20 shows the dimensions for the figures. For more information on Intel
device package, refer to the Intel Packaging Handbook, available from Intel Literature or your local
sales office.

Figure 26. Terminal Dimensions for Table 20
Table 20. Quad Flatpack Dimensions
in Figures 25 and 26

Table 19. Intel 82557 Package Attributes
Attribute

Symbol

Value

Lead Count
Square or Rectangle?
Pitch (mm)
Package Thickness (mm)
Shipping Media

I

I

I

3.75

0

0.30

Overall Height

Square

Standoff

0.65

b

Lead Width

0.20

0040

3.65

c

Lead Thickness

0.150

0.188

0

Terminal Dimension

30.2

31.0

Package Body

27.9

28.1

Terminal Dimension

30.2

31.0

Package Body

27.9

28.1

e1

Lead Pitch

0.55

0.75

L1

Foot Length

0.60

1.0

T

Lead Angle

O·

10·

V

Coplanarity

c

01
E
E1

0.1

NOTE:
Dimensions are in millimeters.

,-----~~~,-----------,
I
I
I

3.25

A

Gull wing lead
configuration, nonbumpered

I

Max

A1

Ves

Comments

Min

160

Trays

Desiccant Pack

.Description

I
I
I

~=;l_L._______J I iii

I[

[J( DDDDDDDDDDD) ~=4
.

c-I
290545-22

Figure 25. Dimensions Diagram for Table 20

1-309

82595FX
ISA BUS HIGH INTEGRATION
ETHERNET CONTROLLER
iii Optimal Integration for Lowest Cost

Solution·
.
- Glueless 8-Bitl16-Bit ISA Bus
Interface
- Provides Fully 802.3 Compliant AUI
and TPE Serial Interface
-Local SRAM Support up to 64 Kbytes
-Integrated ISA Bus Data
Transceivers
- FLASH/EPROM Boot Support up to
1 Mbyte for Diskless Workstations
- Hardware and Software Portable
. between Motherboard and Adapter
Card Solutions

of Use
• -EaseAuto-Negotiation
of Full Duplex

Performance .Networking
• High
Functions
- Advanced Concurrent Processing of
Receive and Transmit Functions
-16-Blt/32-Bit 10 Accesses to Local
SRAM with Zero Added Wait-States
.....;. Ring Buffer Structure for Continuous
Frame Reception and Transmit
Chaining
. - Automatic Retransmission on
Collision
- Automatically Corrects TPE Polarity
Switching Problems
- Auto Negotiation/Manual Full Duplex
Support

•

Low Power CHMOSIV Technology

•

Functionality
- Fully Compatible with ISA Plug and
Play SpeCification
- EEPROM Interface to Support
Jumperless Designs
- Software Structures Optimized to
Reduce Processing Steps
- Automatically Maps into Unused PC
10 Locations to Help Eliminate LAN
Setup Problems
- All Software Structures Contained In
One 16-Byte 10 Space
- JTAG Port for Reduced Board
Testing Times
- Automatic or Manual Switching.
between TPE and AUI Ports
- Supports Eight IRQs
Power Management
- Advanced Power Management
Support by Power Down and Sleep
Mode
- Both SL Compatible SMOUT Input
and Non-SL Software Parameter for
Power Down Mode

160-Lead QFP Package Provides
• Smallest
Available Form Factor
100% Backwards Software Compatible
• to 82595TX

AO-11

TPE Serial
Interface

AI"'-19

ISA
Bus
Interface

00-15

LED
Control

CSMA/CD
Unit

Control

TPE
link I/F

SMOUT

Local Memory
Interface (DMA)

, ", ]

~

0

0

;!.

:!i
:l 9

.3

~

local SRAM I/r

~

'::,

,. '::,,.
~

AUI Serial
Interface

AUI

Link I/F

0
20 MHz XTAL

~

Ii;

t:l

~

D

~ ~

281732-1

Figure 1. 82595FX Block Diagram
September 1995
Order Number: 281732·001

82595FX
ISA Bus High Integration ETHERNET Controller

CONTENTS·

PAGE

1.0 INTRODUCTION ................... 1-314
1.1 82595FX Overview .............. 1-314
1.2 Power Management ............. 1-314
1.3 Auto-Negotiation ................ 1-314

CONTENTS

PAGE
4.4 Local SRAM Accesses .......... 1-327
4.4.1 Writing to Local Memory .... 1-327
4.4.2 Reading from Local
Memory ........................ 1-327

4.5 Serial EEPROM Interface ........ 1-328

1.4 Compliance to Industry
Standards ........................ 1-315

4.6 Boot EPROM/FLASH Interface .. 1-329

1.4.1 Bus Interface-ISA IEEE
P996 .......................... 1-315

5.0 COMMAND AND STATUS
INTERFACE ......................... 1-329

1.4.2 ETHERNET/Twisted Pair
Ethernet Interface-IEEE802.3
Specification ................... 1-315

5.1 Command OP Code Field ........ 1-329

2.0 82595FX PIN DEFINITIONS ....... 1-315
2.1 ISA Bus Interface ................ 1-315
2.2 Local Memory Interface .......... 1-317

5.2 ABORT (Bit 5) ................... 1-329
5.3 Pointer Field (Bits 6 and 7) ........1-329
5.4 82595FX Status Interface ........ 1-331
6.0 INITIALIZATION ................... 1-331

2.3 Miscellaneous Control ........... 1-318

7.0 FRAME TRANSMiSSiON .......... 1-332

2.4 JTAG Control .................... 1-318
2.5 Serial Interface .................. 1-318

7.1 82595FX XMT Block Memory
Format ........................... 1-332

2.6 Serial Interface LEOs ............ 1-319
2.7 Power and Ground .............. 1-320

7.2 XMT Chaining ................... 1-334

2.8 Reserved Pins ................... 1-320
2.9 82595FX Pin Summary .......... 1-321
3.0 82595FX INTERNAL
ARCHITECTURE OVERVIEW ....... 1-322
3.1 System Interface Overview ...... 1-322
3.1.1 Concurrent Processing
Functionality ................... 1-322
3.2 Local Memory Interface .......... 1-322
3.3 CSMA/CO Unit .................. 1-323
3.4 Serial Interface .................. 1-323
4.0 ACCESSING THE 82595FX ........ 1-323

7.3 Automatic Retransmission on
Collision .......................... 1-337
8.0 FRAME RECEPTION .............. 1-337
8.1 82595FX RCV Memory
Structure .......................... 1-337
8.2 RCV Ring Buffer Operation ...... 1-340
9.0 SERIAL INTERFACE .............. 1-341
10.0 APPLICATION NOTES ........... 1-342
10.1 Bus Interface ................... 1-342
10.2 Local Memory Interface ........ 1-342
10.3 EEPROM Interface (ISA Only) .. 1-342
10.4 Serial Interface ................. 1-342

4.1 82595FX Register Map .......... 1-323

10.4.1 AUI Circuit ................. 1-342

4.1.110BankO .................. 1-324

10.4.2 TPE Circuit ................ 1-343

4.1.210 Bank 1 .................. 1-325
4.1.310 Bank 2 .................. 1-326

10.4.3 LED Circuit ................ 1-343

4.2 Writing to the 82595FX .......... 1-326
4.3 Reading from the 82595FX ...... 1-327

I

1-311

CONTENTS

PAGE

10.5 Layout Guidelines .............. 1-343
10.5.1 General ................... 1-343
. 10.5.2 Crystal .................... 1-343 .
10.5.3 82595FX Analog Differential
Signals ........................ 1-343

CONTENTS

PAGE

11.2 AC Timing Characteristics ....... 1-345
11.3 AC Measurement Conditions ... 1-345
11.4 ISA Interface Timing ............ 1-346
11.6 Local Memory Timings ...... , .. 1-350
11.6.1 SRAM Timings ............ 1-350

10.5.4 Decoupling
Considerations ................. 1-343

11.6.2 FLASH/EPROM Timings ." 1-352
11.7 Interrupt Timing ................ 1-354

11.0 ELECTRICAL SPECIFICATIONS
AND TIMINGS ............... .-....... 1-344

1 f.8 RESET and SMOUT Timing .... 1-355

11.1 Absolute Maximum Ratings ..... 1-344
11.1.1 Package Thermal
Specifications .................. 1-345

11.9 JTAG Timing ................... 1-356
11.10 Serial Timings ................. 1-357

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82595FX

1.0

INTRODUCTION

1.1 82595FX Overview
The 82595FX is a highly integrated, high performance LAN. controller which provides a cost effective
LAN solution for ISA compatible Personal Computer
(PC) motherboards (both desktop and portable), and
add-on ISA adapter boards. The 82595FX integrates
all of the major functions of a buffered LAN solution
into one chip with the exception of the local buffer
memory, which is implemented by adding one SRAM
component to the LAN solution. The 82595FX's
Concurrent Processing feature significantly enhances throughput performance. Both system bus and
serial link activities occur concurrently, allowing the
82595FX to maximize network bandwidth by minimizing delays associated with transmit or receiving
frames. The 82595FX's bus interface is a glueless
attachment to an ISA bus. Its serial interface provides a Twisted Pair Ethernet (TPE) and an Attachment Unit Interface (AU I) connection. By integrating
the majority of the LAN solution functions into one
cost effective component, production cost saving
can be achieved as well as significantly decreasing
the design time for a solution. This level of integration also allows an 82595FX solution to be ported
between different applications (PC motherboards,
and· adapters, while maintaining a compatible hardware and software base.
The 82595FX's software interface is optimized to reduce the number of processing steps that are required to interface to the 82595FX solution. The
82595FX's initialization and control registers are directly addressable within one 16-byte 10 address
block. The 82595FX can automatically resolve any
conflicts to an 10 block by moving its 10 offset to an
unused location in the case that a conflict occurs.
The 82595FX's local memory is arranged in a simple
ring buffer structure for efficient transfer of transmit
and receive packets. The local memory, up to
64 Kbytes of SRAM, resides as either a 16-bit or 32bit 10 port in the. host systems 10 map programmable through configuration. The 82595FX provides direct control over the local SRAM. The 82595FX performs a prefetch to the SRAM memory allowing CPU
10 cycles to this data with no added wait-states. The
82595FX also provides an interface to up to 1 Mbyte
of FLASH or EPROM memory. An interface to an
EEPROM, which holds solution configuration values
and can also contain the Node 10, allows for the
implementation of a "jumperless" design. In addition, the 82595FX contains full hardware support for
the implementation of the ISA Plug N' Play specification. Plug N' Play eliminates jumpers and complicat:
ed setup utilities by allowing peripheral functions to
be added to a PC automatically (such as adapter
cards) without the need to individually configure
1-314

each parameter (e.g. Interrupt, 10 Address, etc).
This allows for configuration ease-of-use, which results in minimal time associated with installation.
The 82595FX's packaging and power management
features are designed to consume minimal board
real estate and system power. This is required for
applications such as portable PC motherboard designs which require a solution with very low real estate and power consumption. The 82595FX package
is a 160-lead PQFP (Plastic Quad Flat Pack). Its dimensions are 28 mm by 28 mm, and 3.5 mm in
height. The 82595FX contains two power down
modes; an SL compatible power down mode which
utilizes the SL SMOUT input, and a POWER DOWN
command for non:SL systems.

1.2 Pqwer Management
Power management and low power consumption are
two items that will allow any design using the
82595FX to be suitable for green PC use. Low power operation is initiated when software issues a
SLEEP command to the device. After a short wait, it
will shut off the system clock, some parts of the
Backoff Randomizer, several input buffers and the
two LED drivers. The 82595FX will subsequently
wake up from sleep mode when software initiates an
ISA cycle in the application, as well as when it receives a frame addressed to it. The total power consumption when in sleep mode can be as low as approximately 175 mW. Normal idle power consumption is 300 mW.
The software POWER DOWN command, along with
its companion hardware implementation-the
SMOUT I/O pin, provide additional power management capabilities. This feature allows the 82595FX
to be powered down, and then at some time in the
future be selectively reset without having lost the
current configuration. See the 82595FX User's
Guide for further details on these features.

1.3 Auto-Negotiation
Auto-negotiation functionality is a method of automatically determining the highest common operating
mode (Le., 10BaseT half duplex, 10BaseT full duplex, etc.) between two network devices. Using this
functionality, two stations, each having a varying
number of different operating modes, negotiate the
highest possible common operating mode between
them. During the power up sequence, the auto-negotiation functionality will automatically establish a
link with which it can take advantage of any auto"negotiation-capable device iUs connected to. An autonegotiation capable hub can detect and automatically configure its ports to take maximum advantage of

82595FX

common modes of operation without any user intervention or prior knowledge by connected stations.
See the 82595FX User's Guide for details on this
function.
For further information on these enhancements
and a description of all the differences between
the 82595TX and 82595FX, please consult the
82595FX User's Manual, available through your
local sales representative.

1.4 Compliance to Industry Standards
The 82595FX has two interfaces; the host system
interface, which is an ISA bus interface, and the serial, or network interface. This interface has been
standardized by the IEEE.

2.0

82595FX PIN DEFINITIONS

2.1

ISA Bus Interface

1.4.1 BUS INTERFACEISA IEEE P996
The 82595FX implements the full ISA bus interface.
It is compatible with the IEEE spec P996.
1.4.2 ETHERNET/TWISTED PAIR ETHERNET
INTERFACE-IEEE 802.3 SPECIFICATION
The 82595FX's serial interface provides either an
AUI port interface or a Twisted Pair Ethernet (TPE)
interface. The AUI port can be connected to an
Ethernet Transceiver cable drop, providing a fully
compliant IEEE 802.3 AUI interface. The TPE port
provides a fully compliant IEEE 1OBASE-T interface.
The 82595FX can automatically switch to whichever
port (TPE or AUI) is active.

Symbol

Pin
No.

SAO
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11

61
62
63
64
65
66
67
68
69
70
71
72

I

ADDRESS BUS: These pins provide address decoding for up to 1 Kbyte of
address. These pins also provide 4 Kbytes of 10 addressing to support the
Plug N' Play Standard.

SA14
SA15
SA16
SA17
SA18
SA19

73
74
75
76
77
78

I

ADDRESS BUS: These pins provide address decoding between the 16 Kbyte
and 1 Mbyte memory space. This allows for decoding of a Boot EPROM or a
FLASH in 16K increments.

Type

Name and Function

1-315

82595FX

2.1 ISA Bus Interface (Continued)
Symbol

Pin
No.

Type

Name and Function
DATA BUS: This is the data interface between the 82595FX and the host
system. This data is buffered by one (8-bit design) or two (16-bit design)
internal transceivers.

500
501
S02
503
504
505
506
507
508
509
5010
5011
5012
5013
5014
5015

81
83
'85
87
88
90
92
94
60
58
56
54
53
51
49
-47

I/O

AEN

24

I

ADDRESS ENABLE: Active high signal indicates a OMA cycle is active.

5MEMR

20

I

MEMORY READ for system memory accesses below 1 Mbyte. Active low.

5MEMW

21

I

MEMORY WRITE for system memory accesses below 1 Mbyte. Active
low.

lOR

22

I

10 READ: Active low.

lOW

23

I

10 WRITE: Active low.

IOC516

45

0

10 CHIP SELECT 16: Active low, open drain output which indicates that
an 10 cycle access to the 82595FXsolution is 16-bit wide. Oriven for 10
cycles to the local memory or to the 82595FX.

10CHROY

42

0

10 CHANNEL READY: Active high, open drain output. When driven low, it
extends host cycles to the 82595FX solution.

SBHE

37

I

SYSTEM BUS HIGH ENABLE: Active low input indicates a data transfer
on the high-byte (08-015) of the system bus (a 16-bit transfer). This pin
also determines if the 82595FX is operating in an 8- or 16-bit system upon
initialization.

29
30
31
32
33
34
35
36

0

82595FX INTERRUPT 0-7: One of these 8 pins is selected to be active
one at a time (the other seven are in Hi-Z state) by configuration. These
active high outputs serve as interrupts to the host system.

19

I

RESET DRIVE: Active high reset signal.

, INTO
INn
INT2
INT3
INT4
INT5
INT6
INT7
RE5ETORV

1-316

82595FX

2.2 Local Memory Interface
Symbol

Pin
No.

LADDRO
LADDR1
LADDR2
LADDR3
LADDR4
LADDR5
LADDR6
LADDR7
LADDR8
LADDR9
LADDR10
LADDR11
LADDR12
LADDR13
LADDR14
LADDR15

143
144
145
146
147
148
149
150
153
154
155
156
157
158
159
2

0

LDATAO
LDATA1
LDATA2
LDATA3
LDATA4
LDATA5
LDATA6
LDATA7

132
133
134
135
137
138
139
140

1/0

SRAMCS

13

0

LWE

12

0

Type

Name and Function
LOCAL MEMORY ADDRESS (LADDRO-LADDR1S): These outputs
contain the multiplexed address for the local SRAM.
FLASH ADDRESS 14-17 (LADDRO-LADDRS): These pins control the
FLASH addressing from 16K to 1M to allow paging 01 the FLASH in 16K
spaces. These addresses are under direct control 01 the FLASH PAGING
configuration register.

LOCAL MEMORY DATA BUS (LDATAO-LDATA7): The eight 1/0
signals, comprising the local data bus, are used to read or write data to or
from the 8-bit wide SRAM.
FLASH MEMORY DATA BUS (LDATAO-LDATA7): These signals also
provide eight bits of data lor accesses to an 8-bit FLASH/EPROM il these
components are used.

SRAM CHIP SELECT: This active low output is the chip select to the
SRAM.
This active low output is the Write Enable to the SRAM.
. This pin also provides the active low Write Enable to the FLASH.

LOE

16

0

This active low output is the Output Enable to the SRAM.
This pin also provides the active low Output Enable control to the
FLASH.

10

0

EEPROMCS

8

1/0

EEPROM CS: Active high signal. II no EEPROM is connected, this pin
should be connected to Vee. In this case it will lunction as an input to the
82595FX to indicate no EEPROM is connected.

EEPROMSK

117

0

EEPROM SHIFT CLOCK: This output is used to shift data into and out 01
the serial EEPROM.

EEPROM DO

119

0

EEPROM DATA OUT

EEPROMDI

118

0

EEPROM DATA IN

BOOTCS

BOOT EPROM/FLASH CHIP SELECT: Active low output.

1-317

82595FX

2.4 Miscellaneous Control
Symbol

Pin
No.

SMOUT

18

JO
Jl
J2

119
118
117

Type

Name and Function

1/0

This active LOW signal, when asserted, places the 82595FX into a Power
Down mode. The 82595FX will remain in power down mode until SMOUT is
unasserted. If this line is unconnected to SMOUT from the system bus, it can
be used as an active low output which, when a POWER DOWN command is
issued to the 82595FX, can be used to power down other external
components (this output function is enabled by configuration).

I
I
I

JUMPER: Input for selecting between 7 ISA 10 spaces. These pins should be
connected to either Vee or GND or the EEPROM. The 82595FX reads the
Jumper block during its initialization sequence.
JO
Connected
GND
Vee
GND
Vee
GND
Vee
GND
Vee

Jl
J2
to EEPROM
GND
GND
GND
GND
GND
Vee
GND
Vee
GND
Vee
GND
Vee
Vee
Vee
Vee
Vee

10 Address
Configuration contained in EEPROM
1/0 Window Disabled
2AOh
280h
340h
300h
360h
350h
330h

2.4 JTAG Control
Symbol

Pin
No.

Type

TDO

109

0

TMS

110

I

JTAG TEST MODE SELECT

TCK

111

I

JTAG TEST CLOCK

112

I

JTAG TEST DATA IN

TDI

Name and Function
JTAG TEST DATA OUT

2.5 Serial Interface
Symbol

Pin
No.

Type

TRMT

122

0

Positive side of the differential output driver pair that drives 10 Mb/s
Manchester Encoded data on the TRMT pair of the AUI cable (Data Out A).

TRMT

123

0

NE;lgative side of the differential output driver pair that drives 10 Mb/s
Manchester Encoded data on the TRMT pair of the AUI cable (Data Out 8).

RCV

115

I

The positive input to a differential amplifier connected to the RCV pair of the
AUI cable (Data In A). It is driven with 10 Mb/s Manchester Encoded data.

1-318

Name and Function

82595FX

2.5 Serial Interface (Continued)
Symbol

Pin
No.

Type

RCV

116

I

The negative input to a differential amplifier connected to the RCV pair of the
AUI cable (Data In B). It is driven with 10 Mb/s Manchester Encoded data.

CLSN

124

I

The positive input to a differential amplifier connected to the CLSN pair of the
AUI cable (Collision In A).

CLSN

125

I

The negative input to a differential amplifier connected to the CLSN pair of the
AUI cable (Collision In B).

TDH

105

0

TRANSMIT DATA HIGH: Active high Manchester Encoded data to be
transmitted onto the twisted pair. This signal is used in conjunction with TDL,
TDH, and TDL to generate the pre-conditioned twisted pair output waveform.

TDL

106

0

TRANSMIT DATA LOW: Twisted Pair Output Driver. Active high Manchester
Encoded data with embedded pre-distortion information to be transmitted onto
the twisted pair. This signal is used in conjunction with TDH, TDH, and TDL to
generate the pre-conditioned twisted pair output waveform.

TDH

103

0

TRANSMIT DATA HIGH INVERT: Active low Manchester Encoded data to be
transmitted onto the twisted pair. This signal is used in conjunction with TDL,
TDH, and TDL to generate the pre-conditioned twisted pair output waveform.

TDL

104

0

TRANSMIT DATA LOW INVERT: Twisted Pair Output Driver. Active low
Manchester Encoded data with embedded pre-distortion information to be
transmitted onto the twisted pair. This signal is used in conjunction with TDL,
TDH, and TDH to generate the pre-conditioned twisted pair output waveform.

RD

114

I

Active high Manchester Encoded data received from the twisted pair.

Name and Function

RD

113

I

Active low Manchester Encoded data received from the twisted pair.

X1

127

I

20 MHz CRYSTAL INPUT: This pin can be driven with an external MOS level
clock when X2 is left floating. This input provides the timing for all of the
82595FX functional blocks.

X2

128

0

20 MHz CRYSTAL OUTPUT: If X1 is driven with an external MOS level clock,
X2 should be left floating.

2.6 Serial Interface LEOs
Symbol

Pin
No.

Type

Name and Function

AUI LED/BNC DIS

95

0

AUI LED INDICATOR: This output, when the 82595FX is used as a
TPEI AUI solution, will turn on an LED when the 82595FX is actively
interfaced to its AUI serial port. When the 82595FX is used as a
BNCI AUI solution, this output becomes the BNC DIS output, which
can be used to power down the BNC Transceiver section (the
Transceiver and the DC to DC Converter) of the solution when the
BNC port is unconnected.

LlLED

98

0

LINK INTEGRITY LED: Normally on (low) ouput which indicates a
good link integrity status when the 82595FX is connected to an
active TPE port. This output will remain on when the Link Integrity
function has been disabled. It turns off (driven high) when Link
Integrity fails, or when the 82595FX is actively interfaced to an AUI
port. The minimum off time is 100 ms.

1-319

82595FX

2.6 Serial Interface LEOs (Continued)
Symbol

Pin
No.

Type

ACT LED

97

0

LINK ACTIVITY LED: Normally off (high) output turns on to indicate activity
for transmission, reception, or collision. Flashes at a rate dependent on the
level of activity on the link.

POLED

96

0

POLARITY LED: If the 82595FX detects that the receive TPE wires are
reversed, the POLED will turn on (low) to indicate the fault. POLED remains on
even if automatic polarity correction is enabled, and the 82595FX has
automatically corrected for the reversed wires.

Name and Function

2.7 Power and Ground
Symbol

Pin
No.

Type

Name and Function

Vee

1,3,7,15,
26,28,40,
43,46,50,
57,80,84,
91,99,101,
107,121,
129,131,
141,152

I

POWER: +5V ±5%.

Vss

4,6,9,11,
14,17,25,
27,38,39,
41,44,48,
52,55,59,
79,82,86,
89,93,100,
102,108,
120,126,
130,136,
142,151

I

GROUND: OV.

2.8 Reserved Pins
Symbol

NIC

1-320

Pin
No.

5,160

Type

Name and Function
Reserved. Do not connect.

82595FX

Miscellaneous Control

2.9 82595FX Pin Summary
ISA Bus Interface
ISA
Pin Name
SAO-SA3 (In)
SA4-SA11
SA14-19 (In)
SDO-SD15 (1/0)
SMEMR(ln)
SMEMW(ln)
lOR (In)
lOW (In)
INTO-7 (Ou1)
RESET DRV (In)
IOCS16 (Out)
10CHRDY (Out)
SBHE (In)
AEN (In)

Pin Name
P·Down
State

Pin
Type

TS

TS
OD
OD

Inactive
Inactivel Act(1)
Inactive
TS
Inactive
Inactive
Inactive
Inactivel Act(1)
TS
Act
TS
TS
Inactive
Inactivel Act(1)

NOTE:
1. For hardware powerdown using SMOUT, these pins will
be inactive. For software powerdown, these pins remain
active.

Local Memory Interface
Pin
Name

MUXed
Name

Pin
Type

P·Down

LADDR[5:0) (Out)
LADDR[6:15) (Out)
LDATA[0:7) (1/0)
LWE (Out)
LOE (Out)
BOOTCS (Out)
SRAMCS (Out)
EEPROMCS (1/0)

FADDR[14:19)

2S
2S
TS
2S
2S
2S
2S
TS

TS
TS
TS
TS
TS
PU
PU
PD

MUXed
Pin
Name

Pin
Type

P·Down
State

Dual
Pin Name

ACT

EEPROM2DO
(In)
EEPROM2DI
(Out)
EEPROM2SK
(Out)

JO(ln)
J1 (1/0)

TS

TS

J2 (1/0)

TS

TS

SMOUT(I/O)

TS

ACT/TS

JTAG Control
Pin Name

MUXed
Pin Name

Pin
Type

TMS (In)
TCK(ln)
TDI (In)
TDO (Out)

P·Down
State
In Act
In Act
In Act

TS

Serial Interface
Pin Name
TRMT(Out)
TRMT(Out)
RCV(ln)
RCV(ln)
CLSN (In)
CLSN (In)
TDH (Out)
TDL(Out)
TDH (Out)
TDL(Out)
RD(ln)
RD(ln)
X1 (In)
X2 (Out)
LlLED (Out)
POLED (Out)
ACTLED (Out)
AUILED (Out)

MUXed
Pin Name

BNC DIS (Out)

Pin
Type

P-Down
State

Ana
Ana
Ana
Ana
Ana
Ana
Ana
Ana
Ana
Ana
Ana
Ana

TS
TS
In Act
In Act
In Act
In Act
TS
TS
TS
TS
In Act
In Act
In Act
TS
TS'
TS'
TS'
TS'

2S
2S
2S
2S
2S

• Assuming auto-negotiation disabled.
Legend:
TS-TriState.
OD-Open Drain.
2S-Two State, will be found in either a 1 or 0 logic level.
Ana-Analog pin (all serial interface signals).
Act-Input buffer is active during Power Down.
In Act-Inpulbuffer is inactive during Power Down.
PU-Output in inactive state with weak internal Pull-up during Power Down.
PD-Output in inactive state with weak internal Pull-down during Power Down.
Dual-Dual function pin.

1-321

B2595FX

3.0

82595FX INTERNAL
ARCHITECTURE OVERVIEW

Figure 1 shows a high level block diagram of the
82595FX. The 82595FX is divided into four main
subsections; a system interface, a local memory
sub-system interface, a CSMAlCD unit, and a serial
interface.
.

3.1 System Interface Overview
The 82595FX's system interface subsection includes a glueless ISA bus interface, and the
82595FX's 10 registers (including the 82595FX's
. command, status, and Data In/Out registers). The
system interface block also interfaces with the
82595FX's local memory interface subsystem and
CSMAlCD subsystem.
The bus interface logic provides the control, address, and data interface to an ISA compatible bus.
The 82595FX decodes up to 1M of total memory
address space. Address decoding within 16K block
increments (A14-A19) are used for Flash or Boot
EPROM. 10 accesses are decoded throughout the 1
Kbyte PC 10 address range (A 10 and A11 provide up
to 4K of 10 addressing and are used for Plug N'
Play). The 82595FX data bus interface provides either an 8- or 16-bit interface to the host system's
data bus. The control interface provides complete
handshaking interface with the system bus to enable
transfer of data between the 82595FX solution and
the host system.
The 82595FX's 10 registers provide 3 banks of directly addressable registers which are used as the
control and data interface to the 82595FX. There
are 16 10' registers per bank, with only one bank
enabled at a time. This allows the complete
82595FX software interface to be contained in one
16-byte 10 space. The base address of this 10 space
is selectable via either software (which can be
stored in a serial EEPROM), or by strapping the
82595FX 10 Jumper block (JO-J2). The 82595FX
can also detect conflicts to its base 10 space, and
automatically resolve these conflicts either by allowing the selection of one Plug N' Play card from multiple cards (using Plug N' Play software), or by mapping itself into an un-used 10 space (Automatic 10
Resolution). Included in the 82595FX 10 registers
are the Command Register, the Status Register, and
the Local Memory 10 Port register, which provides
the data interface to the local SRAM buffer contained in an 82595FX solution. Functions such as 10
window mapping, Interrupt enable, RCV and XMT
buffer initialization, etc. are also configured and controlled through the 10 registers.

1-322

3.1.1 CONCURRENT PROCESSING
FUNCTIONALITY

The 82595FX's Concurrent Processing feature significantly enchances data throughput performance
by performing both system bus and serial link activities concurrently. Transmission of a frame is started
by the 82595FX before that frame is completely copied into local memory. During reception, a frame is
processed by the host CPU before that frame is entirely copied to local memory. Transmit Concurrent
Processing feature is enabled by writing to BANK 2,
Register 1, Bit O. A 1 written to this bit enables this
functionality, a 0 (default) disables it. To enable Re.
ceive Concurrent Processing, BANK 1, Register 7
must be programmed to value other than OOh (OOh
disables RCV Concurrent Processing, and is default). (See Section 4.1 for the format of 10 BANK 1
and 2.) Improvements in concurrent processing
functionality have allowed the 82595FX to include
enhancements to the throughput efficiency of the
82595TX. For details, refer to the 82595FX User's
Guide. Concurrent Processing is not recommended
for 8-bit interfaces. For more information on Transmit and Receive Concurrent Processing, refer to
Section 7.0 and Section 8.0.

3.2 Local Memory Interface
The 82595FX's local memory interface includes a
DMA unit which controls data transfers to or from
the 82595FX's local SRAM, control for access to a
Boot EPROM/FLASH, and two interfaces to a serial
EEPROM. The local memory interface subsection
also arbitrates accesses to the local memory by the
host CPU and the 82595FX.
Data transfers between the 82595FX and the local
SRAM are always through the 82595FX's Local
Memory 16-bitl32-bit 10 Port. This allows the entire
SRAM memory (up to 64 Kbytes) to be mapped into
one 10 location in the host systems 10 map. By
setting a configuration bit in the 82595FX's 10
Registers (3210/HAR #), the local memory can be
extended from 16 bits to a full 32 bits. During 32-bit
accesses, the CPU would perform a doubleword access addressed to register 12 of BANKO. The ISA
bus will break this access up into two 16-bit accesses to Registers 12/13 followed by Registers 14/15,
(or 4 sequential 8-bit accesses in an 8-bit interface).
The CPU always accesses the 82595FX 10 Port for
Receive or Transmit data transfers, while the
82595FX automatically increments the address to
the SRAM after each CPU access. The SRAMs data
path is an 8-bit interface (typically 64K by 8-bits
wide, or 256K by 8-bits wide) to allow for the lowest
possible solution cost. The 82595FX implements a

82595FX

prefetch mechanism to the local SRAM so that the
data is always available to the CPU as either an 8- or
16-bit word. In the case of the CPU reading from the
SRAM, the 82595FX reads the next two bytes from
the SRAM, the 82595FX between CPU cycles so
that the data is always available as a word in the
82595FX's Local Memory 10 Port register. In the
case of the CPU writing to the SRAM, the data is
written into the 82595FX's Local Memory 10 Port
then transferred to the SRAM by the 82595FX between CPU cycles. This prefetch mechanism of the
82595FX allows for 10 read and writes to the local
memory to be performed with no additional waitstates (3 clocks per data transfer cycle).
The DMA unit provides addressing and control to
move RCV or XMT data between the 82595FX and
the local SRAM. For transmission, the CPU is required only to copy the data to the local memory,
initialize the 82595FX's DMA Current Address Register (CAR) to point to the beginning of the frame,
and issue a Transmit Command to the 82595FX.
The DMA unit facilitates the transfers from the local
memory to the 82595FX as transmission takes
place. The DMA unit will reset upon collision during
a transmission, enabling automatic re-transmission
of the transmit frame. During reception, the DMA
unit implements a recyclable ring buffer structure
which can receive continuous back to back frames
without CPU intervention on a per frame basis (see
Section 8.2 fqr details).
The 82595FX provides address decoding and control to allow access to an external Boot EPROMI
FLASH if these components are utilized in an
82595FX design. The 82595FX also provides an interface to a serial EEPROM to replace jumper
blocks used to contain configuration information.
This port is used to store configuration information
and in addition, it is used to store Plug N' Play information as defined in the Plug N' Play Specification.
The 82595FX arbitrates accesses to the local memory sub-system by the CPU and the 82595FX. The
arbitration unit will hold off an 82595FX DMA cycle
to the local memory if a CPU cycle is already in progress. Likewise, it will hold off the CPU if an 82595FX
cycle is already in progress. The cycle which is held
off will be completed on termination of the preceding
cycle.

3.3 CSMA/CD Unit
The CSMAlCD unit implements the IEEE 802.3
CSMA/CD protocol. It performs such functions as
transmission deferral to link traffic, interframe spacing, exponential backoff for collision handling, address recognition, etc. The CSMAlCD unit serves as
the interface between the local memory and the serial interface. It serializes data transferred from the
local memory before it is passed to the serial interface unit for transmission. During frame reception, it
converts the serial data received from the serial interface to a byte format before it is transferred to
local memory. The CSMAlCD unit strips framing parameters such as the Preamble and SFD fields before the frame is passes to memory for reception,
For transmission, the CSMAlCD unit builds the
frame format before the frame is passed to the serial
interface for transmission.

3.4 Serial Interface
The 82595FX's serial interface provides either an
AUI port interface or a Twisted Pair Ethernet (TPE)
interface. The AUI port can be connected to an
Ethernet Transceiver cable drop to provide a fully
compliant IEEE 802.3 AUI interface. The AUI port
can also interface to a transceiver device to
provide a fully compliant IEEE 802.3 10BASE2
(Cheapernet) interface. The TPE port provides a fully compliant 10BASE-T interface. The 82595FX automatically enables either to the AUI or TPE interface depending on which medium is connected to
the chip. Software configuration can override this
automatic selection.

4.0

ACCESSING THE 82595FX

All access to the 82595FX is made through one of
three banks of 10 registers. Each bank contains 16
registers. Each register in a bank is directly accessible via addressing. Through the use of bank switching, the 82595FX utilizes only 16 10 locations in the
host system's 10 map to access each of its registers. The different banks are accessed by setting the
POINTER field in the 82595FX Command Register
to select each bank. The Command Register is Register for each bank.

4.1 82595FX Register Map
The 82595FX registers are contained in three banks
of 16 10 registers per bank. These three banks are
shown in the following three pages.

1-323

82595FX

4.1.1 10 BANK 0
The format for 10 Bank 0 is shown below.

7

6
POINTER
RCV
States

,

(Counter)
01
Resvrd

0
Resvrd

3

4

5
ABORT

I

IDREGISTER
1
(Auto En)
3210/ -'
HAR

EXEC
INT

I

0
EXEC
Mask

TX
INT
1

I

TX
Mask

RX
INT

I

RXSTP
INT

0
0
RESERVED
RX
Mask

I

RXSTP
Mask

Reg 1
Reg 2
Reg 3

RCVCAR/BAR
(Low)

Reg 4

RCVCAR/BAR
(High)

Reg 5

RCVSTOPREG
(Low)
RCVSTOPREG
(High)
RCV Copy Threshold REG
EARLY XMT THRESHOLD REGISTER (XTR)

1-324

Reg 0
(CMD
Reg)

.cOMMAND OP CODE

EXEC
States

Curl
Base

o

2

,

Reg 6
Reg 7
RegS
Reg~

XMTCAR/BAR
(Low)

Reg 10

XMT CAR/BAR '
(High)

Reg11

Host Address Reg (Low)
/32-Bit I/O (Byte 0)

Reg 12

Host Address Reg (High)
/32-Bit I/O (Byte 1)

Reg 13

Local Memory I/O Port (Low)
/32-Bit I/O (Byte 2)

Reg 14

Local Memory I/O Port (High)
/32-Bit I/O (Byte 3)

Reg 15

82595FX

4.1.2 10 BANK 1
The format for 10 Bank 1 is shown below.

7

6
POINTER

Tri-ST
INT

0
Resvrd

0

0
Resvrd

o

2

3

Reg 0
(CMD
Reg)

COMMAND OP CODE

ABORT

FL/BT
Present
0

4

5

0
Resvrd

Boot EPROM/FLASH
Decode Window

0
Resvrd

0
Resvrd

I

Bad
IRQ

Host
BusWd

I

0
Resvrd

INTSelect

Reg2

I/O Mapping
Window

0
0

0

0

0

Reg 3

0

0

0

(Reserved)
0

0

0

0

Reg 4

6

0

0

0

(Reserved)

RegS

BACK TO BACK TRANSMIT IFS

Reg 6

RCV BOF Threshold REG

Reg 7

RCV LOWER LIMIT REG
(High Byte)

Reg

RCV UPPER LIMiT REG
(High Byte)

Reg 9

XMT LOWER LIMIT REG
(High Byte)

Reg 10

XMT UPPER LIMIT REG
(High Byte)
FLASH
SELECT

PAGE
HIGH

0

0

Reg 1

FLASH WRITE
ENABLE

Reg 11
FLASH PAGE
SELECT

I

0
Resvrd

Reg 12
0
Resvrd

0

0

0

SMOUT
OUTEN

0

0

0

0

0

0

0

0

(Reserved)
0

0

0

0

0

0

0

0

I

Reg 13
Reg 14

(Reserved)
(Reserved)

a

Reg 1p

1-325

82595FX

4.1.3 10 BANK 2

The format for 10 Bank 2 is shown below.

7

6
POINTER

Disc
Bad Fr

I
I

3

4

ABORT

TxChn
ErStp

LoopBack
Test 1

5

Test 2

Res
0

0

Multi
IA

NoSA
Ins
APORT

0
(Reserved)

0

Length
Enable

RXPRC
InMEM.

Jabber
Disable

TPE/
AUI

0
0

I

Reg 2

Pol
Corr

Link In
Dis

Reg 3

Reg 5
Reg 6

INDIVIDUAL ADDRESS
REGISTER 3

Reg 7

INDIVIDUAL ADDRESS
REGISTER 4

Reg 8

INDIVIDUAL ADDRESS
REGISTER 5

Reg 9
EEDI

EEDO

Link
LED

Activity
LED

0
(Resvrd)

0

0

0

,
Status
0

0

0

4.2 Writing to the 82595FX
Writing to the 82595FX is accomplished by an 10
Write instruction (such as an OUT instruction) from
the host processor to one of the 82595FX registers.
The 82595FX registers reside in a block of 16 con·
tiguous addresses contained within the PC 10 ad·
dress space. The mapping of this address block is
programmable throughout the 1 Kbyte PC 10 ad·
dress map.

EESK

Reg 10
Reg 11

0
(Reserved) .

0

EECS

,

Auto~Negotiation

(Reserved)

1·326

PRMSC
Mode

INDIVIDUAL ADDRESS
REGISTER 2

Enabl~

0

BC
DIS

INDIVIDUAL ADDRESS
REGISTER 1

Reserved
0

0

Reg 1

Reg 4

RCV NO RESOURCE
COUNTER

Polarity
LED

TXCon
Proc En

INDIVIDUAL ADDRESS
REGISTER 0

Turnoff

STEPPING

Reg 0
(CMD
Reg)

COMMAND OP CODE·

TxChri
IntMd

BNC/
TPE

o

2

Reg 12

A·N
Enable

FDX/
. HDX

0

0

Reg 13
Reg 14.

0

0
Reg 15

The 82595FX registers ·are contained within three
banks of 10 registers. When writing to a particular
register, the processor must first select the correct
bank (Bank 0, 1 or 2) in which the register resides.
Once a bank is selected, all register accesses are
made in that bank until a switch to another bank is
performed. Switching banks is accomplished by writ·
ing to the PTR field of Reg 0 in any bank. Reg 0 is
the command register of the 82595FX and its functionality is identical in each banK Once in the appro-

82595FX

priate bank, the processor can write directly to any
of the B2595FX registers by simply issuing an OUT
instruction to the 10 address of the register.

4.4.1 WRITING TO LOCAL MEMORY

Reading from the B2595FX is accomplished ~y an
10 Read instruction (such as an IN instruction) from
the host processor to one of the B2595FX registers.
When reading from a particular register, the processor must first select the correct bank (Bank 0, 1 or 2)
in which the register resides. Once in the appropriate bank, the processor can read directly from any
of the B2595FX registers by simply issuing an IN instruction to the 10 address of the register.

The local memory of an 82595FX solution is written
to whenever the host CPU performs a Write operation to the B2595FX Local Memory 10 Port. Prior to
writing a block of data to the local memory, the CPU
should update the B2595FX Host Address Register
with the first address to be written. The CPU then
copies the data to the local memory by writing it to
the 82595FX Local Memory 10 Port. The addressing
to the local memory is provided by the Host Address
Register which is automatically incremented by the
82595FX upon completion of each write cycle. This
allows sequential accesses to the local memory,
even though the 10 port a~dress accessed does not
change.

4.4 Local SRAM Accesses

4.4.2 READING FROM LOCAL MEMORY

10 mapping the local SRAM memory of an B2595FX
solution allows it to appear as simply an 10 Port to
the host system. This allows an B2595FX solution to
work in PCs which do not have enough space in
their system memory map to accommodate the addition of LAN buffer memory (typically 16 Kbytes to
64 Kbytes) into the map. The entire local memory
(up to 64 Kbytes) is mapped into one 16-bit 10 Port
location. For all 10-mapped accesses to the local
memory of a B2595FX solution, the 82595FX performs the 10 address decoding and the ISA Bus interface handshake and asserts the address and
control signals to the local memory.

The local memory of an 82595FX solution is read
from whenever the host CPU performs a Read operation from the B2595FX Local Memory 10 Port. Prior
to reading a block of data from the local memory,
the CPU should utilize the 82595FX Host Address
Register to point to first address to be read. The
CPU then reads the data from the local memory
through the 82595FX Local Memory 10 Port. The
addressing to the local memory is provided by the
Host Address Register which is automatically incremented by the 82595FX upon completion of each
read cycle.

4.3 Reading from the 82595FX

1-327

82595FX

4.5 Serial EEPROM Interface
A Serial EEPROM, a Hyundai HY93C46 or equivalent IC, stores configuration data for the 82595FX.
The use of an EEPROM enables 82595FX designs
to be implemented without jumpers (the use of jumpers to select 10 windows is optional.) The port interface to the serial EEPROM provides both configuration and Plug N' Play information access. Plug N'
Play allows peripheral functions to be added to a PC
(such as adapter cards) without the need to individually configure each parameter (e.g. Interrupt, 10 Address, etc). Information describing system resources
are contained within the 82595FX configuration registers. This allows Auto-configuration software,
which is usually contained in the BIOS or OIS, to
identify system resource usage, identify conflicts
and automatically re-configure the 82595FX.
The 82595FX automatically accesses Register 0 of
the EEPROM upon a RESET in ISA Bus Interface
mode. Register 0 contains the information that the
82595FX must be configured to allow CPU
accesses to it (10 Mapping Window, FLASH Detect
Enable, Auto 1/0 Enable, Boot EPROM/FLASH
Window, Host Bus Width, and Plug N' Play Enable)
following a system boot. The format for EEPROM
Register 0 is shown in Figure 4-1. Note that all O's
are assumed to be reserved. In the case where an
EEPROM is either unprogrammed (each bit defaults
to a 1) or completely erased (all O's), the 82595FX·
will default to 10 Address 300h.

WordO, Bit 1, the Word 1 Enable bit, is asserted. to
enable the read of EEPROM Word 1 during reset.
This bit is active high.
NOTE:
If Word 1 of the EEPROM is not to be read
during a reset, software must wait 200 /Ls after the reset is issued before accessing the
82595FX, as was the case on all versions of
the 82595. If Word 1 is to be read during' a
reset, software must wait 400 /Ls after reset
before accessing the part. During this
"blackout" period, the part will not respond
to accesses on the ISA bus.
Word 0, Bit 8, is the Flash Present bit. This bit is
active low to indicate the presence of flash memory,
as in the 82595FX B-3. The functionality of the bit is
changed from the 82595FX B-2 and prior versions.
Word 0, Bit 9 is the Auto-Negotiation, or A-N, Enable
bit for the negotiation process at boot time. The bit is
active high.
Word 1 of the EEPROM is used to store the INT
Select value to which the part will default on reset.
The mapping from INT Select to IRQ is explained
later in this document. The value stored in bits 0
through 2 of word 1 of the EEPROM is loaded into
the INT Select register of the 82595FX, bank 1, register 2, bits 0 through 2 on any hardware or software
reset. The reading of Word 1 on reset is enabled
when bit 1 of word 0 of the EEPROM is set. If this bit
is not set on reset, word 1 will not be read and the
INT select register and Bad IRQ bit in bank 1 will be
initialized to zero.

For additional information regarding a Plug N' Play implementation for the 82595FX, please consult the
82595FX User's Guide and LAN595TX Specification, available through your local sales representative.
The latest Plug N' Play Specification is available by Microsoft.
015

03

01
INTSelec!

Software Reserved

Figure 4-1. EEPROM Register 0
05

04
BTl FLASH

1/0 Mapping Window

Window

Figure 4-2. EEPROM Register 1

1-328

02

03

DO

intel®
4.6 Boot EPROM/FLASH Interface
The Boot EPROM/FLASH of an 82595FX solution is
read from or written to (FLASH only) whenever the
host CPU performs a Read or a Write operation to a
memory location that is within the Boot EPROM/
FLASH mapping window. This window is programmable throughout the ISA PROM address range
(C8000-DFFFF) by configuring the 82595FX Boot
EPROM Decode Window register (Bank 1, Register
2, bits 4-6). The 82595FX asserts the BOOTCS#
signal when it decodes a valid access. Up to 1
MBytes of FLASH can be addressed by the
82595FX.

5.0

COMMAND AND STATUS
INTERFACE

The format for the 82595FX Command Register is
shown in Figure 5-1. The Command Register resides
in Register 0 of each of the three 10 Banks of the
82595FX, and can be accessed in any of these
banks. The Command Register is accessed by writing to or reading from the 10 address for Register O.

5.1

Command OP Code Field

Bits 0 through 4 of the Command Register comprise
the Command OP Code field. A command is issued
to the 82595FX by writing it into the Command OP
Code field. A command can be issued to the
82595FX at any time; however in certain cases the
command may be ignored (for example, issuing a
Transmit command while a Transmit is already in
progress). In these cases the command is not performed, and no interrupt will result from it.

82595FX

The Command·OP Code field can also be read. In
this case it will indicate an execution status event
other than TRANSMIT DONE (TOR Done, DIAGNOSE Done, MC-SETUP Done, DUMP Done, INIT
Done, and POWER-UP) has been completed. This
fieldis valid only when the EXEC INT bit (Bank 0,
Reg 1, Bit 3) is set.

5.2 ABORT (Bit 5)
This bit indicates if an execution command other
than TRANSMIT was aborted while in progress. This
bit provides status information only. It should be written to a 0 whenever the Command Register is written to.

5.3 Pointer Field (Bits 6 and 7)
The Pointer field controls which 82595FX 10 register
bank is currently to be accessed (Bank 0, Bank 1, or
Bank 2). Writing a OO:b to the Pointer field selects
Bank 0, 01:b for Bank 1, and 10:b for Bank 2. The
Pointer field is valid only when the SWITCH BANK
(Oh) command is issued. This field will be ignored for
any other command. The 82595FX will continue to
operate in a current bank until a different bank is
selected. Upon power up of the device or Reset, the
82595FX will default to Bank O.

1-329

intel®

82595FX

7

6
Pointer

I

5
ABORT

4

I

1

2

3

0

I Reg 0 (CMD Reg)

COMMAND OP CODE
Figure 5-1. 82595FX Command Register

I
82595rX Command Register
7

654 3 2

1 0

IAbl

'--,..-J

Lo~o~

'-SWITCH BANK
RESERVEO
RESERVEO
MC-SETUP
TRANSMIT
TOR
DUMP
DIAGNOSE
ABORT
RESERVED
XMT no CRC/SA
RESUME XMT LIST
CONT XMT TEST
SET TRISTATE
RESET TRISTATE
POWER DOWN
SLEEP MODE
RESET
SEL RESET
RCV ENABLE
RCV DISABLE
RCV STOP
NEGOTIATE

00
01
02
03
04
05
06
07
00
12
14
lC
15
16
17
18
19
OE
1E
08
OA
OB
lA

'-

Pointer

Gank 0
Bank 1
Bank 2

00
01
10
281732-3

Figure 5-2. 82595FX Command Interface

1-330

82595FX

5.4 82595FX Status Interface

6.0

The Status of the 82595FX can be read from Register 1 of Bank 0, with additional status information
contained in Register 0 (the Command Register).
Figure 5-3 shows these registers. Other information
concerning the configuration and initialization of the
82595FX and its registers can be obtained by directly reading the 82595FX registers.

Upon either a software or hardware RESET, the
82595FX enters into its initialization sequence.
When the 82595FX is interfaced to an ISA bus, the
82595FX reads information from its EEPROM and
Jumper block (if utilized) which configures critical parameters (10 Address mapping, etc.) to allow initial
accesses to the 82595FX during the host system's
initialization sequence and also access by the software device driver. The 82595FX can also be configured (via the EEPROM) to automatically resolve any
conflicts to its 10 address location either by moving
its 10 address offset to an unused location in the
case that a conflict occurs, or by using the Plug N'
Play Software to the 1/0 address location. This process eliminates a large majority of LAN end-user
setup problems.

When read, the Command OP Code field indicates
which event (MC Done, Init Done, TOR Done, or
DIAG Done) has been completed. This field is valid
only when the EXEC INT Bit (Bank 0, Reg 1, Bit 3) is
set to a 1. Reading the Pointer field indicates which
bank the 82595FX is currently operating in. Register
1 in Bank 0 contains the 82595FX interrupts status
as well as the current states of the RCV and Execution units of the 82595FX. Resultant status from
events such as the completion of a transmission or
the reception of an incoming frame is contained in
the status field of the memory structures for these
particular events.

6

7
Pointer
RCV
States

5
ABORT

The 82595FX can be configured to operate with ISA
systems that require early deassertion of the
lOCH ROY signal to its low (not ready) state. The
82595FX, along with its software driver, can perform
a test at initialization to determine if early lOCH ROY
deassertion is required.

3

4

I

INITIALIZATION

o

2

EXECUTION EVENT

EXEC
States

I

EXEC
INT

I

TX
INT

I

RX
INT

Reg 0 (CMD Reg)

I RX STP
INT

Reg 1 (Bank 0)

Figure 5-3. 82595FX Status Information

1-331

82595FX

7.0

point to that frame, and issue a XMT command to
the 82559TX. The 82595FX performs all the link
management functions, DMA operations, and statistics keeping to handle transmission onto the link and
communicate the status of the transmission to the
CPU. The 82595FX performs automatic retransmission on collision with no CPU interaction.

FRAME TRANSMISSION

The 82595FX performs all of the necessary functions needed to transmit frames from its local memory. If Transmit Concurrent Processing is enabled,
the CPU must only program the Base and Host Address Register with the starting address to be transmitted, copy a portion of the frame into the
82595FX's transmit buffer located in local memory
(the number of bytes for this first portion is deter~
mined by the software driver without causing an Underrun), issue a XMT command to the 82595FX, and
complete the data copies for this frame to local
memory. If Transmit Concurrent Processing is disabled, the CPU must copy an entire frame into the
82595FX's transmit buffer located in local memory,
set up the 82595FX's Current Address Registers to

7.1

82595FX XMTBlock Memory
Format

The format in which a XMT block is written to memory by the CPU is shown in Figure 7-1 for a 16-bit
interface. Figure 7-2 shows this structure for an 8-bit
interface.

15
XMT Opcode
Status 1

Status 0

XMT Chain Point HI

XMT Chain Point LO

Byte Count HI

Byte Count LO

Base/Current Addr Reg
..- Command Field
Status Field
Transmit Choin Pointer

Byte Count/Chain

XMT Data field (Start)

XMT DATA

XMT Data Field (End)

o

Dn

I 0 I Ab I

XMT Opcode

Commmond Field for Next
Transmission in Choin

281732-4

Figure 7-1. XMT Block Memory Structure (1S-Bit)

1-332

82595FX

a

7
Dn

Ia I I

XMT Opcode

Ab

a

a

a

+-

a

a

Status

a

a

a

Base/Current Addr Reg
Command Field

a

Status 1

Status Field

XMT Chain Point La
XMT Chain Point Hi

Transmit Chain Pointer

Byte Count Lo
Ch

I

Byte Count Hi

Byte Count/Chain

XMT Data Field (Start)

---------------------

XMT DATA

--------------------XMT Data Field (End)
Dn

Ia I I
Ab

XMT Opcode

Command Field for
Next Transmission in Chain

281732-5

Figure 7-2. XMT Block Memory Structure (S-Bit)

1-333

82595FX

Status Field

The two bytes of the Status Field (Status 0 and
Status 1) are shown in detail in Figure 7-3. In a 16-bit
wide interface, these two bytes will combine to form
one word. This field is originally set to all O's by the
CPU as the XMT block is copied to memory. It is
updated by the 82595FX upon completion of the
transmission.

7.2 XMT Chaining
The 82595FX can transmit consecutive frames without the CPU having issued a separate Transmit
command for each frame. This is called Transmit
Chaining. The 82595FX Transmit Chaining memory
structure for a 16-bit interface is shown in Figure 7-4,
7

6

3

with an 8-bit interface shown in Figure 7-5. The
82595FX registers which control the memory structure are also shown. The CPU places multiple XMT
blocks in the Transmit buffer. The 82595FX will
transmit each frame in the chain, reporting the
status for each frame in its status field. If Concurrent
Processing is enabled, the copy of additional frames
in a chain will take place while the first portion of the
chain (one or more frames) is being transmitted by
the 82595FX. This chain can be dynamically updated by the CPU to add more frames to the chain. The
transmit chain can be configured to terminate upon
an errored frame (maximum collisions, underrun, lost
CRS, etc.) or it can continue to the next frame in the
chain. The 82595FX can be configured to interrupt
upon completion of each transmission or to interrupt
at the end of the transmit chain only (it always interrupts upon an errored condition).

2

o

~----+------+------1------r-----.------,-------,-----~

Status 0
Status 1

NOTE:
1. Only functional in full duplex operations.

Figure 7-3. Transmit Result

1-334

82595FX

15

Ch

o

Start of XtdT Buffer

0

0

0

0

0

0

0

0

Status 1

Status 0

XtdT Chain Point HI

XtdT Chain Point LO

Byte Count HI

Byte Count LO

I

+- Lower Limit Register

XtdT Opcode

DnlOIAbl

Bose Addr Register
Current Addr Register
Ch
1 (Chaining Bit)

=

XtdT Data field (Start)

------------------------------------------XtdT DATA

frome 1

------------------------------------------XtdT Data Field (End)

0

Ch

0

0

0

0

0

0

0

On

I

XNT Opcode

Status 1

Status 0

Next FRtd Point HI

Next FRtd Point LO

I

Byte Cou nt HI

Byte Count LO

Ch

=0

XtdT Data Field (Start)

------------------------------------------XtdT DATA
Frame 2

-------------------------------------------

(End of XtdT Chain)

XtdT Data Field (End)

0

0

0

0

0

0

0

0

On

I 0 I Ab I
Ch

r

Remaining Unused

~

r

1.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....

_

=0

Upper Limit Register

281732-6

Figure 7-4. 82595FX XMT Chaining Memory Structure

1-335

82595FX

o

7
On

10 1 Ab
0

a

0

+- Lower Limit Register

XMT apcode

1
0

a

a

0

0

0

0

Base Addr Register
Current Addr Register

Status 0
Status 1
XMT Chain Point Lo
XMT Chain Point Hi
Byte Count Lo
Byte Cou nt Hi

Ch 1

XMT Data Field (Start)

XMT DATA

XMT Data Field (End)
XMT Opcode

On 1
a

0'

0

0

0

0

Status 0
Status 1
XMT Chain Point Lo
XMT Chain Point Hi
Byte Count Lo
Ch

I

Byte .Count Hi
XMT Data Field (start)

XMT DATA

~

XMT Data Field (End)
On 1

Nap
Remaining Unused Area

(End of XMT Chain)
Ch

=0

. - Upper Limit Register

Figure 7-5. XMT Block Memory Structure (8-Bit)

1-336

281732-7

82595FX

7.3 Automatic Retransmission on
Collision
The 82595FX performs automatic retransmission
when a collision is experienced within the first slot
time of the transmission with no intervention by the
CPU. The 82595FX performs jamming, exponential
backoff, and retransmission attempts as specified by
the IEEE 802.3 spec. The 82595FX reaccesses its
local memory automatically on collision. This allows
the 82595FX to retransmit up to 15 times after the
initial collision with no CPU interaction.
The 82595FX reaccesses the data in its transmit
buffer by simply resetting the value of its Current
Address Register back to the value of the Base Address Register (the beginning of the XMT block) and
repeating the DMA process to access the data in the
transmit buffer again. Once it regains access to the
link, retransmission is attempted. When Transmit
Chaining is utilized, the process for retransmission is
exactly the same. Only the current frame in the'
chain will be retransmitted, since the Base Address
Register is updated upon transmission of each
frame.

8.0

FRAME RECEPTION

The 82595FX implements a recyclable ring buffer
DMA structure to support the reception of back to
back incoming RCV frames with minimal CPU overhead. The structure of the RCV frames in memory is
optimized to allow the CPU to process each frame
with as few software processing steps as pos-

sible. The frame format is arranged so that all of the
required infomation for each frame (status, size,
etc.) is located at the beginning of the frame.

8.1

82595FX RCV Memory Structure

, The 82595FX RCV memory structure for a 16-bit interface is shown in Figure 8-1. Figure 8-2 shows this
structure for the 8-bit interface. Once an incoming
frame passes the 82595FX's address filtering, the
82595FX deposits the frame into the RCV Data field
of the RCV Memory Structure. The fields which precede the RCV Data field, Event, Status, Byte Count,
Next Frame Pointer, and the Event field of the following frame, are updated upon the end of the frame
after all of the incoming data has been deposited in
the RCV Data field. If Receive Concurrent Processing is enabled, the CPU processes the receive frame
without the entire frame being deposited by the
82595FX to the RCV Data Field. The 85295FX,
along with the software driver, determines the portion of the frame being copied to host memory before the rest cif that frame is copied to local memory.
An interrrupt is asserted by the 82595FX (EOF) after
frame reception has been completed.
If the 82595FX is configured to Discard Bad Frames,
it will discard all incoming errored frames by resetting its DMA Currel')t Address Register back to the
value of the Base Address Register and not updating any of the fields in the RCV frame structure. This
area will now be reused to store the next incoming
frame.

,f

1-337

82595FX

15
0

.

Start of ReV Buffer

0

0

0

0

0

0

Rev

0

Status 1

0

<4-lower Limit Register

Event

Status 0

Next FRM Point HI

Next

Byte Count HI

rR~

Point LO

Byte Count LO

RCV Data Field (Start)

RCV DATA

Frome 1

RCV Data Field (End)
0

0

0

0

0

0

0

0

ReV Event

Status 1

Status 0

Next FRM Point HI

Next FRM Point LO

Byte Count HI

Byte Count LO

RCV Data Field (Start)

RCV DATA

Frome 2

RCV Data Field (End)
0

0

0

0

0

0

0

0

+- Base

NOP

Addr Register
Current Addr Register

Remaining Unused

I

Area

J

+- Upper

281732-8

Figure 8-1. 82595FX ReV Memory Structure (1S-Bit)

1-338

Limit Register

82595FX

7

o

Start of RCV Buffer

+-- Lower Limit Register

RCV Event
0

0

0

0

0

0

0

0

0

0

Status 0
Status 1
Next Frame Point La
Next Frame Point Hi
Byte Count La
Byte Count Hi
RCV Data Field (Sta rt)

RCV DATA
(Frame 1)

RCV Data Field (End)
RCV Event
0

0

0

0

0

0

Status 0
Status 1
Next Frame Point La
Next Frame Point Hi
Byte Cou nt La
Byte Count Hi
RCV Data Field (Start)

RCV DATA

RCV Data Field (End)
Base Addr Register
Current Addr Register

NOP
Remaining Unused Area

+--

Upper limit Register

281732-9

Figure 8-2. 82595FX ReV Memory Structure (8-Bit)

1-339

82595FX

Status Field
The two bytes of the Status Field (Status 0 and
Status 1) are shown in detail in Figure 8-3. In a 16-bit
wide interface, these two bytes will combine to form
one word. The 82595FX provides this field for each
.
incoming frame.

8.2 ReV Ring Buffer Operation
The 82595FX RCV Ring Buffer operation is illustrated in Figure 8-4. The 82595FX copies received
frames sequentially into the RCV Buffer area .ofthe
local memory. The CPU processes these frames by
copying the frames from the local memory. After a
frame is processed,- the CPU updates the 82595FX's
Stop Register to point to the last location processed.
This indicates that the RCV Buffer memory which

6

precedes the value programmed in the Stop Register is now free area (it has been processed by the
CPU). When the 82595FX reachl-_ _: Ie end of the
RCV Buffer (the Upper Limit Register yalue) it will
now wrap around back to the beginning of the buffer, and continue to copy RCV frames into the buffer,
beginning at the value pointed to by the Lower Limit
Register. The 82595FX will continue to copy frames
into the RCV Buffer area as long as it does not reach
the address pointed to by the Stop Register (if this
.does occur, the 82595FX stops copying the frames
into memory and issues an Interrupt to the CPU). As
the CPU processes additional incoming frames, the.
Stop Register value continues to be moved. This action allows the CPU to keep ahead of the incoming
frames and allows the Ring Buffer to be continually
recycled as the memory [space consumed by an incoming frame is reused as that frame is processed.

o

5

~------~----~------~--------~------~--------~------~------~

Status 0
Status 1

Figure 8·3. RCV Status Field

1ImII-..........

+--- Lower Limit Register

\

\

, ,

Unprocessed
Fram ••

\

\

I
I

I
I

I
--~

I
+--- Upper Limit RegIster
281732-10

Figure 8-4. 82595FX RCV Ring Buffer Operation

1-340

82595FX

9.0 SERIAL INTERFACE
The 82595FX's serial interface subsystem incorporates all the active circuitry required to interface the
82595FX to 10BASE-T networks or to the attachment unit (AUI) interface. It includes on-chip AUI and
TPE drivers and receivers as well as Manchester
Encoder/Decoder and Clock Recovery circuitry. The
AUI port can be connected to an Ethernet Transceiver cable drop to provide a fully compliant IEEE
802.3 AUI interface. The AUI port can also be interfaced to a transceiver to provide a fully compliant
IEEE 802.3 10BASE2 (Cheapernet) interface. The
TPE port provides a fully compliant 10BASE-T interface. The 8259,5FX automatically enables either the
AUI or TPE interface, depending on which medium is
active. This automatic selection can be overridden
by software configuration. The TPE interface also
features a polarity fault detection and correction circuit which will detect and correct a polarity error on
the twisted pair wire, the most common wiring fault
in twisted pair networks.
A 20 MHz parallel resonant crystal is used to control
the clock generation oscillator, which provides the
basic 20 MHz clock source. An internal divide-bytwo counter generates the 10 MHz ±0.01,% clock
required by the IEEE 802.3 specification.
The 82595FX supports 802.3 Half Duplex Ethernet
functionality, as did previous versions of the 82595.
, It also supports a Full Duplex Ethernet mode that
complies with Specifications for Full Duplex Ethernet, Rev. 1.0, Sept. 9th, 1993, from Kalpana, when
connected, to a Full Duplex hub through the TPE
port. Full-duplex provides increased network
throughput (using full duplex. network components)
by providing dedicated channels for both Transmit
and Receive data at the, same time. Full Duplex operation is transparent to existing software drivers.
More details on Full Duplex functionality can be
found in the 82595FX User's Guide.
Auto-Negotiation (or N-Way) is a method of maximizing network operational efficiency. Auto-Negotiation
works by interrogating Auto-Negotiation compliant
equipment to determine the highest common mode
of operation shared by all connected devices. When
Auto-Negotiation is enabled, the 82595FX will negotiate the Highest Common Denominator (HCD)
transmission mode with the hub to which it is attached, on a hardware reset. If the hub does not
support Auto-Negotiation and Auto-Negotiation is
enabled on the 82595FX, the 82595FX will revert to
Half Duplex.

The 82595FX is in Auto-Negotiation mode only
when the A-N Enable bit, bit 1 in register 13 of bank
2, is set. On hardware reset, the state of this bit is
copied from the EEPROM A-N Enable bit, bit 9 of
Word 0 of the EEPROM.
We recommend that a crystal that meets the following specifications be used:
• Quartz Crystal
• 20.00 MHz ± 0.002% at 25·C
• Accuracy ±0.005% over Full Operating Temperature, O·C to + 70·C
• Parallel resonant with 20 pF Load Fundamental
Mode
Several vendors have such crystals; either off-theshelf or custom-made. Two possible vendors are:
1. M-Tron Industries, Inc.
Yankton, SO 57078
Specifications:
Part No. HC49 with 20 MHz, 50 PPM over O·C to
+ 70·C, and 20 pF fundamental load.
2. Crystek Corporation
100 Crystal Drive
Ft. Myers, FL 33907
Part No. 013212
The accuracy of the Crystal Oscillator frequency depends on the PC board characteristics; therefore, it
is advisable to keep th,e X1 and X2 traces as short
as possible. The optimum value of C1 and C2 should
be determined experimentally under nominal 'operating conditions. The typical value of C1 and C2 is
between 22 pF and 35 pF.
An external 20 MHz MOS-Ievel clock may be applied
to pin X1, if pin X2 is left floating.
A summary of the 82595FX's serial interface subsections functions is shown below:
• Manchester Encoder/Decoder and Clock
Recovery
• Diagnostic Loopback
• Reset-Low-Power Mode
• Network Status Indicators
• Defeatable Jabber Timer
• User Test Modes

1-341

82595FX

• Complies with IEEE 802.3 AUI Standard
- Direct Interface to AUI Transformers
- On-Chip AUI Squelch
• Complies with IEEE 802.3 10BASE-T for
Twisted Pair Ethernet
- Selectable Polarity Detection and
Correction
- Direct Interface to TPE Analog Filters
- On-Chip TPE Squelch
- Defeatable Link Integrity for Pre-Standard
Networks
- Supports 4 LEOs (Link Integrity, Activity,
AUI/BNC DIS and Polarity Correction)
- Auto-Negotiation of Full Duplex
Functionality

10.0 APPLICATION NOTES
This section is intended to provide Ethernet LAN deSigners with a basic understanding of how the
82595FX is used in a buffered LAN design.

10.1 Bus Interface
The 82595FX Bus Interface unit integrates ISA Bus
data transceivers, providing an even more cost efficient and seamless integration than that of the
82595TX. The 82595FX provides the complete coritrol and. address interface to the host system busimplementing a complete ISA bus protocol.

10.2 Local Memory Interface
The 82595FX's local memory interface includes a
OMA unit which controls data transfers between the
82595FX and the local memory SRAM. The
82595FX can support up to 64 Kbytes of local
SRAM.
The 82595FX provides address decoding and control to allow access to an external Boot EPROM or a
FLASH. Addition of a Boot EPROM or FLASH to an
ISA solution is optional. The IA is assumed to be
stored in the serial EEPROM for the ISA solution.

10.3 EEPROM Interface
The 82595FX provides a complete interface to a se·
rial EEPROM for ISA adapter designs. For ISA motherboard designs, the EEPROM is not required. The
EEPROM is used to store configuration information
such as Memory and 10 Mapping Window, Interrupt
line selection, Plug N' Play resource data local bus
width, etc. The EEPROM is used to replace jumper
blocks which previously contained this type of information.

10.4 Serial Interface
The 82595FX's serial interface provides either an
AUI port interface or a Twisted Pair Ethernet (TPE)
interface. The AUI port can be connected to an
Ethernet Transceiver cable drop to provide a fully
compliant IEEE 802.3 10BASE5 interface. The AUI
port can also be interfaced to a transceiver device
on the adapter to provide a fully compliant IEEE
802.3 10BASE2 (Cheapernet) interface. The TPE
port provides a fully compliant 1OBASE-T interface.
The 82595FX automatically enables either the AUI
or TPE interface, depending on which medium is
connected to the chip. This automatic selection can
be overridden by software configuration.
10.4.1 AUI CIRCUIT
When used in conjunction with pulse transformers,
the 82595FX provides a complete IEEE 802.3 AUI
interface. In order to meet the 16V fault tolerance
specification of IEEE 802.3, a pulse transformer is
recommended. The transformer should _be placed
between the TRMT, RCV, and CLSN pairs of the
82595FX and the ~O, 01, and CI pairs of the AUI
(OB-15) connector. The pulse transformer should
have the following characteristics:
• 75 J-LH minimum inductance (100 J-LH recommended)
• 2000V isolation between the primary and secondary windings
• 2000V isolation between the primaries of separate transformers
• 1:1 Turns ratio
The RCV and CLSN input pairs should each be terminated by 78.7fl ± 1 % resistors.

1-342

82595FX

10.4.2 TPE CIRCUIT
The B2595FX provides the line drivers and receivers
needed to directly Fabinterface to the TPE analog
filter network. The TPE receive section requires a
100.11 termination resistor, a filter section (filter, isolation transformer, and a common mode choke) as
described by the 10BASE-T B02.3i-1990 specification.
The TPE transmit section is implemented by connecti~e B2595FX's four TPE outputs (TDH, TDH,
TDL, TDLl to a resistor summing network to form the
differential output signal. The parallel resistance of
R5 and R6 sets the transmitters maximum output
voltage, while the difference (R5 - R6)/R5 + R6), is
used to reduce the amplitude of the second half of
the fat bit (100 ns) to a predetermined level. This
predistortion reduces line overcharging, a major
source of jitter in the TPE environment. The output
of the summing network is .then fed into the above
mentioned filter and then to the 10BASE-T connector (RJ-45). Analog Front End solutions can be purchased in a single-chip solution from several manufacturers. The solution described in this data sheet
uses the Pulse Engineering (PE65434) AFE.
10.4.3 LED CIRCUIT
The B2595FX's internal LED drivers support four
LED indicators displaying node status and activity
(i.e., Transmit data, receive data, collisions, link integrity, polarity correction, and port (TPE/ AUI). To
implement the LED indicators, connect the LED driver output to an LED in series with a 510.11 resistor
tied to Vee. Each driver can sink up to 10 mA of
current with an output impedance of less than 50.11.

10.5 Layout Guidelines

Connect logic and chassis ground together, only at
one point on the fab-near the connection to system
ground.
You must connect all Vee pins to the same power
supply and all Vss pins to the same ground plane.
Use separate decoupling per power-supply/ground
pin.
Close signal paths to ground as close as possible to
their sources to avoid ground loops and noise cross
coupling.
10.5.2 CRYSTAL
The crystal should be adjacent to the B2595FX and
trace lengths should be as short as possible. the X1
and X2 traces should be as symmetrical as possible.
10.5.3 82595FX ANALOG DIFFERENTIAL
SIGNALS
The differential signals from the 82595FX to the
transformers, analog front end, and the connectors
should be symmetrical for each pair and as short as
possible.
The differential signals should also be isolated from
the high speed logic signals on the same layer as
well as on any ·sublayers of the PCB.
Group each of the circuits together, but keep them
separate from each other. Separate their grounds.
In layout, the circuitry from the connectors to the
filter network should have the ground and power
planes removed from beneath it. This will prevent
ground noise from being induced into. the analog
front end.
All trace bends should not exceed 45 degrees.

10.5.1 GENERAL
The analog section, as well as the. entire board itself,
should conform to good high-frequency practices
and standards to minimize switching transients and
parasitic interaction between various circuits. To
achieve this, follow these guidelines:
Make power supply and ground traces as thick and
as short as possible. This will reduce high-frequency
cross coupling caused by the inductance of thin
traces.

10.5.4 DECOUPLING CONSIDERATIONS
Four 0.1 /LF ceramic capacitors should be used.
Place one on each side in the center of the I.C. adjacent to the B2595FX. Connect the capacitors directly to the Vee pins and ground planes of the
82595FX.

1-343

82595FX

11.0

ELECTRICAL SPECIFICATIONS
AND TIMINGS

NOTICE: This data sheet containsinlormation on
products in the sampling and initial production phases
of development. The specilications are subject to
change without notice. Verify with your local Intel
Sales office that you. have the latest data sheet belore linalizing a design. .
.

11.1 Absolute Maximum Ratings

+ 85·C
+ 140·C
..... -0.5V to + 7V

Case Temperature under Bias ....... O·C to

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Storage Temperature .......... -65·C to
All Output and Supply Voltages

All Input Voltages ............. -1.0V to

+ 6.0V(1)

Further information on the quality and reliability of
the 82595FX may be found in the Components
. Ouality and Reliability Handbook, Order Number
210997.

Table 11-1. DC Characteristics (Tc = O·C to + 85·C, VCC = 5V ± 5%)
Max
Units
Test Conditions
Pararr-eter
Min

Symbol
VIL
VIH
VIHCJUMPRl
VOL1(2)
VOL2(3)
VOL4(4)
VOH
VOL (LED)(5)
VOH (LED)
ILP(6)
RDIFF(7)
VIDF (TPE)(S)
Rs (TPE)(9)
VIDF (AUI)(10)
VI eM (AUI)(11)
VODF (AUI)
lose (AUI)
VU(AUI)
VODI (AUI)(12)
lee
leeHwPD
leeSWPD
leeSLEEP
CIN(13)

..

Input LOW Voltage (TTL)
Input HIGH Voltage (TTL)
Input HIGH Voltage (Jumpers)
Output LOW Voltage
Output LOW Voltage
Output LOW Voltage
Output HIGH Voltage
Output Low Voltage
Output High Voltage
Leakage Current
Input Differential-Resistance
Input Differential Accept
Input Differential Reject
Output Source Resistance
Input Differential Accept
Input Differential Reject
AC Input Common Mode
Output Differential Voltage
AU I Output Short Circuit Current
Output Differential Undershoot
Differential Idle Voltage
Power Supply Current
Hardware Power Down
Software Power Down
Sleep Mode
Input Capacitance

-0.3
2.0
3.0

+0.8
Vee + 0.3
Vee + 0.3
0.45
0.45
0.45

2.4
0.45
3.9
±10
10
±0.5
5
±0.3

±0.45

±3.1
±0.3
13
±1.5
±0.16
±0.5
±0.1
± 1.2
±150
-100
40
90
400
2
35
10

V
V
V
V
V
V
V
V
V
/LA
Kn
Vp
Vp
n
Vp
Vp
Vp
Vp
V
mA
mV
mV
mA
/LA
mA
mA
pF

IOL =17 mA
IOL = 12 mA
IOL = 2 mA
IOH = -1 mA
IOL = 10 mA
IOH = -500/LA
o ~ VI ~ Vee
DC
5 MHz ~ I ~ 10 MHz
IILOADI = 25 mA

1~40KHz
~ I ~

40 KHz

Short Circuit to Vee or GND

@I = 1 MHz

NOTES:
1. The voltage level lor RCV and CLSN pairs are -'-0.75V to +S.5V.
2. SDx, IOCS16.
3. IOCHRDY, IRQx.
4. LDATAx, LADDRx, LOE, LWE, BOOTCS, SRAMCS, EEPROMCS, SMOUT, TSTCLK, TDO, J1, J2.
5. LlLED, ACTLED, POLED and TPLBNC-AUI.
6. Pins: ACTLED, LlLED, POLED, TPE_BNC-AUI.
7. RD to RD, RCV to RCV and CLSN to CLSN.
S. TPE input pins: RD and RD.
9. TPE output pins: TDH, TDH, TDL and TDL, Rs measure Vee or Vss to pin.
10. AUI input pins: RCV and CLSN pairs.
11. AUI output pins: TPMT pair.
12. Measured S.O /Ls after last positive transition 01 data packet.
13. Characterized, not tested.

1·344

10 MHz

.

82595FX

11.1.1 PACKAGE THERMAL SPECIFICATIONS
The 82595FX is specified for operation when case
temperature is within the range of O·G to 85·G. The
case temperature may be measured in any environment to determine whether the 82595FX is within
the specified operating range. The case temperature
should be measured at the center of the top surface
opposite the pins.
The ambient temperature is guaranteed as long as
Tc is not violated. The ambient temperature can be
calculated from the 8JA and the 8JC from the following equations:

Vee

vss

,~
I281732-13

Figure 11-3. Voltage Levels for TRMT
Pair Output Timing Measurements

"x+---OV

DELAY /WIDTH MEASUREMENT -joo
RISE/FALL MEASUREMENT --

VS - Air1low ft/mln (m/Sec)
0(0)

I281732-14

Thermal Resistance ("C/Watt)

4.9

vee/ 2

Il

8 JA and 8 JC values for the 160 QFP package are as
follows:

8JA -

:

DELAY /WIDTH MEASUREMENT RISE/FALL M'EASUREMENT --

TJ = Tc + p*oJC
TA;" TJ - P*OJA
Tc = TA + P*(OJA - oJcl

8JC

':

Figure 11-4; Voltage Levels for Olfferentiallnput
Timing Measurements (RD Pair)

34.4

11.3 AC Measurement Conditions
11.2' AC Timing Characteristics
28~mV
t ____ _ - - - - -ov
DELAY /WIDTH MEASUREMENT RISE/FALL MEASUREMENT --

I-281732-11

1. Tc = O·G to + 85·G, Vcc = 5V ±5%
2. The signal levels are referred to in Figures 1, 2, 3
and 4.
3. AG Loads:
a) AUI Differential: a 10 pF total capacitance
from each terminal to ground,and a load resistor of 78!1 ± 1 % in parallel with a 27 ,...H
± 5% inductor between termina,ls.
b) TPE: 20 pF totaicapacitance to ground.

Figure 11-1. Voltage Levels for Olfferentlallnput
Timing Measurements (RCV and CLSN Pairs)

O.9V - - O.4SV

DELAY /WIDTH MEASUREMENT RISE/FALL MEASUREMENT --

281732-15 ,

I-281732-12

Figure 11-2. Voltage Levels for
TDH, TOL, TDH and TOL

Figure 11-5. X11nput Voltage Levels
for Timing Measurements

1-345

82595FX

Table 11-2. Clock Timing
Symbol

Parameter

Min

Max

Unit

t1

X1 Cycle Time

49.995

50.005

ns

t2

X1 Fall Time

5

ns

t3

X1 Rise Time

t4

X1 Low Time

15

ns

ns

t5

X1 High Time

15

ns

5

11.4 ISA Interface Timing
Table 11-3. 16-Bit 1/0 Access
Parameter

Description

Min

Max

Units

T1a

AEN Valid to 1/0 Command Active

100

ns
ns

T2a

AEN Valid from 1/0 Command Inactive

30

T3a

SA to CMDActive

63

ns

T4a

SA Valid Hold from CMD Inactive

42

ns

T5a

Valid SA to IOCS16 Active

T6a

IOCS16 Valid Hold from Valid SA

T7a

100

Comments

ns

0

ns

CMD Active to Inactive

125

ns

TSa

CMD Inactive to Active

92

T9a

Active CMD toValid 10CHRDY

T10a

CMD Active Hold from 10CHRDY Active

SO

T11a

DATA Driven from READ CMDActive

0

T12a

Valid READ Data from CMD Active

64

ns

Applies to Standard Cycles Only

T13a

Valid READ Data from 10CHRDY Active

52

ns

Applies to Ready Cycles Only

T14a

READOata Hold from CMD Inactive

T15a

READ CMD Inactive toOata Tristate

30

ns

T16a

CMD to WRITE Data Active

62

T17a

WRITE Data Hold from CMD Inactive

T1Sa

WRITE CMD Inactive to Data Tristate

1-346

30

ns

Before 1/0 Command

ns

Applies to Ready Cycles

ns

Applies to Ready Cycles

ns

0

ns

15

ns
ns

30

ns

82595FX

Table 11-4. a-Bit 1/0 Access
Parameter
T1b

Description
AEN Valid to 1/0 Command Active

Min

Max

100

Units

T2b

AEN Valid from 1/0 Command Inactive

30

ns

T3b

SA to CMD Active

63

ns

T4b

SA Valid Hold from CMD Inactive

42

T5b

Valid SA to IOCS16 Inactive

ns
100

ns

T6b

IOCS16 Valid Hold from Valid SA

0

ns

T7b

CMD Active to Inactive

125

ns

T8b

CMD Inactive to Active

92

T9b

Active CMD to Valid 10CHRDY

T10b

CMD Active Hold from 10CHRDY Active

T11b

DATA Driven from READ CMD Active

Comments

ns

ns

Before 1/0 Command

ns

Applies to Ready Cycles

80

ns

Applies to Ready Cycles

0

ns

226

T12b

Valid READ Data from CMD Active

64

ns

Applies to Standard Cycles

T13b

Valid READ Data from 10CHRDY Active

52

ns

Applies to Ready Cycles Only

T14b

READ Data Hold from CMD Inactive

0

ns

T15b

READ CMD Inactive to Data Tristate

30

ns

T16b

CMD to WRITE Data Active

62

ns

T17b

WRITE Data Hold from CMD Inactive

T18b

WRITE CMD Inactive to Data Tristate

15

ns
ns

1·347

82595FX

Table 11-5. 8-Blt Memory Access
Parameter
T1c

Description

Min

Max

Units

AEN Valid to Command Active

100

T2c

AEN Valid from Command Inactive

30

ns

T3c

SA to CMD Active

63

ns

T4c

SA Valid Hold from CMD Inactive

42

ns

T5c

CMD Active to Inactive

125

ns

60

T6c

CMD Inactive to Active

T7c

Active CMD toValid IOCHRDY

T8c

CMD Active Hold from IOCHRDY Active

T9c

DATA Driven from READ CMD Active

T10c

Valid READ Data from IOCHRDY Active

T11c

READ Data Hold from CMD Inactive

ns

Before Memory Command

ns

Applies to Ready Cycles

80

ns

Applies to Ready Cycles

0

ns

226

52
0

ns
ns

T12c

READ CMD'lnactive to Data Tristate

30

T13c

CMD to WRITE Data Active

62

ns

T14c

WRITE CMD Inactive to Data Tristate

30

ns

1-348

Comments

ns

ns

82595FX

T2

T1
AEN

SAl 19:0]. SBHE

________

II~--------~--------------------~~-JI

10CHRDY

DATA (READ) -------------------+--~

~~~~~~----~~~T_--

DATA (WRITE)

________________+--1
281732-16

Figure 11-6. ISA Read/Write Cycle

1-349

82595FX

11.6 Local Memory Timings
11.6.1 SRAM TIMINGS
• The S2595FX any SRAM up to 25 ns access
time .
• SRAM type supported are 4K, SK, 16K, 32K,
64K x S.
Table 11-6. 82595FX SRAM-AC Characteristics
Parameter

Description

Min

Max

Units

T1w

LADDR Valid to SRAMCS Active

0

ns

T2w

LADDR Valid to LWE Active

0

ns

T3w

SRAMCS Active Time

25

ns

T4w

LWE Active Time

25

ns

T5w

Data Valid to SRAMCS Inactive

15

ns

T6w

Data Valid to LWE Inactive

15

ns

T7w

SRAMCS Inactive to Data Invalid

0

ns

TSw

LWE Inactive to Data Invalid

0

ns

T9w

SRAMCS Inactive to LADDR Invalid

0

ns

T10w

LWE Inactive to LADDR Invalid

0

ns

T1r

LADDR Valid to SRAMCS Active

0

ns

T2r

LADDR Valid to LOE Active

0

ns

T3r

SRAMCS Active Time

25

ns

T4r

LOE Active Time

25

T5r

Data Valid to SRAMCS Active

ns
25

ns

T6r

Data Valid to LOE Inactive

25

ns

T7r

Data Read Hold Time from SRAMCS Inactive

0

25

ns

TSr

Read Data Hold Time from LOE Inactive

0

25

ns

1·350

Comments,

82595FX

LADDR[ 15:0]

Address Valid

Tlw

--+------(

LDATA[7:0]

T2w

,LWE,

281732-19

Figure 11-7. SRAM Timings-Write Cycle

Address Valid

LADDR[ 15:0]

Tlr

LDATA[7:0] .--+-----~

T2r

281732-20

Figure 11-8. S~AM Timings-Read Cycle

1-351

82595FX

11.6.2 FLASH/EPROM TIMINGS

• Flash/EPROM types supported are 16K, 32K,
64K, 128K, 256K, 512K, 1024K x 8.

• The 82595FX is designed to support a FLASH or
EPROM up to 200 ns access time.

Table 11·7. FLASH-AC Characteristics
Parameter

Description

Min

Max

Units

T1w

LADDR Setup Time to LWE Active

0

ns

T2w

LADDR Hold Time from LWE Active

75

ns

T3w

LWE Active Time

60

ns

T4w

BOOTeS Setup Time before LWEActive

20

ns

T5w

BOOTeS Hold Time from LWE Inactive

0

ns

T6w

Data Setup Time before LWE Inactive

50

ns

T7w

Data Hold Time from LWE Inactive

10

ns

T1r

LADDR Setup Time to BOOTeS Active

0

ns

T2r

LADDR Setup Time to LOE

0

ns

T3r

BOOTeS Active Time

225

ns

T4r

LOE Active Time

225

ns

T5r

BOOTeS Active to Data Valid

200

ns

T6r

LOE Active to Data Valid

200

ns

T7r

Data Hold Time from BOOTeS Inactive

0

40

ns

T8r

Data Hold Time from LOE Inactive

0

40

ns

Comments

LADDR[S:O]

LWE

LDATA[7:0]

-----------0(1

Data In

281732-22

Figure 11·10. FLASH Timings-Write Cycle

1·352

82595FX

LADDR[5:0]

LOE

LDATA[7:0] ---------~

281732-23

Figure 11-11. Flash Timings-Read Cycle
Table 11-8. EEPROM AC Characteristics
Parameter

Description

Min

Max

Units

Comments

T1 (css)

CS Setup Time

1.0

/ks

T2(skh)

SK High Time

3.0

/ks

T3(skl)

SK Low Time

3.0

/ks

T4(csh)

CS Hold Time

0

/ks

T5(cs)

CS Low Time

1.0

/ks

T6(dis)

01 Setup Time

0.4

/ks

T7(dih)

01 Hold Time

0.4

T8(do)

00 Valid Time

0.4

/ks

EEPROM Restriction

T9(df)

CS Inactive to 00 Floating

0.4

/ks

EEPROM Restriction

/ks

EEPROMes

EESK

EEDI

T8(do)

T9(df)

EEDO

281732-24

Figure 11-12. EEPROM Timings
1-353

82595FX

,11.7 Interrupt Timing
Table 11-9. Interrupt Timing
Parameter
T177

"

Description

Min

Interrupt Ack CMD Inactive to IRQ[0-7] Inactive

T178

IRQ[0-7] Inactive to IRQ[O-: 7] Active

T179

Tri-state CMD Inactive to IRQ[0-7J Tri-State

' Max

Units

500

ns

100

T177

Notes

ns
500

ns

T178

'J,"--,_ __

IRQO-7

T179
IRQO-7

.......................................................--

~>-

--------------------~--~

Figure 11-13. Interrupt Timing

1-354

281732-26

82595FX

11.8 RESET and SMOUT Timing
General Comments
• Both signals are asynchronous signals and have minimum pulse duration specification only.
• SMOUT during Hardware power down activation.
Table 11·10. RESET and SMOUT Timing
Parameter

Description

Min

T180

RESET Minimum Duration

32

Max

Units

Notes

ms

1

T181

SMOUT Minimum Duration

100

ns

2

T182

SMOUT Activation by Power Down Command

150

ns

3

T183

SMOUT Deactivation·

25

ns

3

NOTES:
1. Noise spikes of maximum TBD ns are allowed on Reset.
2. SMOUT is input.
3. SMOUT is. output after configuration.

RESET

/.

TISO

\

~

TISI

Jf

~

t

TIS2

.\
'-261732-27

Figure 11·14. SMOUT Timing

1·355

82595FX

11.9 JTAG Timing
Table 11·11. 82595FX JTAG Timing
Symbol

Parameter

Min

Max

Unit

T184

TMS'Set-Up Time

30

ns

T185

TMS Hold Time

30

ns

T186

TDI Set-Up Time

30

ns

T187

TDI Hold Time

30

ns

T188

Input Signals Set-Up Time

30

ns

T189

Input Signals Hold Time

30

T190

Outputs Valid Delay

T191

TOO Valid Delay

T192

TCK Cycle Time (Period)

Notes

ns
200

ns

40

ns

100

ns

50% Duty Cycle

TCK

T~S

TOI

Inpu~

Signals

Output

Signals

TOO
281732-28

Figure 11-15_ 82595FX JTAG Timing

1-356

82595FX

11.10 Serial Timings
Table 11-12. TPE Timings
Symbol

Parameter

t90

Number of TxD Bit Loss at Start of Packet

t91

Internal Steady State Propagation Delay

Min

Typ

Max

Unit

2

bits

400

ns

600

ns

1.5

3

ns

2

5

ns

99

100

101

ns

49

50

51

ns

t92

Internal Start UP Delay

t93

TDH and TDL Pairs Edge Skew (@ Vee/2)

t94

TDH and TDL Pairs Rise/Fall Times
(@ 0.5V to Vee - 0.5V)

t95

TDH and TDL Pairs Bit Cell Center to Center

t96

TDH and TDL Pairs Bit Cell Center to Boundary

t97

TDH and TDL Pairs Return to Zero from Last TDH

250

t98

Link Test Pulse Width

98

t99

Last TO Activity to Link Test Pulse

two

Link Test Pulse to Data Separation

400

ns

100

100

ns

8

13

24

ms

190

200

ns

~----------~7----------~
TDH

TDL

281732-29

TDH

--------- ----------II
1
--'~I-:_---II
-{...._____---Irr----..\..

TOL

~:_:_ _-'I\\-________~~

I

TDH

'99 --1--"', ---I

"00

--------------------------------------

-------------~::-:

TOL~:_:_ _ _ _ _ _-Jr-\~

_______________~

281732-30

Figure 11-16. TPE Transmit Timings (Link Test Pulse)

1-357

82595FX

Table 11-13. TPE Receive Timings
Symbol

Parameter

Max

Unit

19

bits

1

bits

AD to Internal Steady State Propagation Delay

400

ns

2.4 .

JLs

t105

AD to R~D Bit Loss at Start of Packet

t106

AD Invalid Bits Allowed at Start of Packet

t107

Min

Typ

4

t108

AD to Internal Start Up Delay

t109

AD Pair Bit Cell Center Jitter

±13.5

ns

t110

AD Pair Bit Cell Boundry Jitter

±13.5

ns

t111

AD Pair Held High from Last Valid
Position Transition

400

ns

;I

RD

t'11

230

I

LF\..J"\j....----.\L_ _------:--~--~
~13 =I

281732-31

Figure 11-17. TPE Receive Timings (End of Frame)
Table 11-14. TPE Link Integrity Timings
Symbol

Parameter

Min

Typ

Max

Unit

50

100

150

ms

t120

Last AD Activity to Link Fault
(Link Loss Timer)

t121

Minimum Fieceived Linkbeat Separation(1)

2

5

7

ms

t122

Maximum Aeceived Linkbeat Separation(2)

25

50

150

ms

NOTES:
1. Linkbeats closer in time to this value are considered noise and rejected.
2. Linkbeats further apart in time than this value are not considered consecutive and are rejected.

1·358

82595FX

RO pair

__________--j
1-\120

LlLED

~/r------------------------------281732-32

Figure 11-18. TPE Link Integrity Timings
Table 11-15. AUI Timings
Symbol

Parameter

Min

Typ

Max

Unit

t126

TRMT Pair Rise/Fall Times

3

5

ns

t127

Bit Cell Center to Bit Cell Center of
TRMT Pair

99.5

50

100.5

ns

t128

Bit Cell Center to Bit Cell Boundary of
TRMT Pair

49.5

50

50.5

ns

t129

TRMT Pair Held at Positive Differential at
Start of Idle

200

t130

TRTM Pair Return to ";:40 mVp from
Last Positive Transition

ns

8.0

I
TRMT

p..s

t130 - - - - - - - - I

~

po;, - - - - - - - - - - - - - '

i126-1

I--t'26

~------~----======~~~---1--t'29---1

~
127

128

281732-33

Figure 11-19. AUI Transmit Timings
Table 11-16. AUI Receive Timings
Symbol

Parameter

t135

RCV Pair Rise/Fall Times

t136

RCV Pair Bit Cell Center Jitter in Preamble

t137

RCV Pair Bit Cell Center/Boundary Jitter in Data

t138

RCV Pair Idle Time after Transmission

t139

RCV Pair Return to Zero from Last
Positive Transition

Min

Typ

Max

Unit

10

ns

±12

ns

±18

ns

8

p..s

160

ns

1-359

82595FX

Rev
pair

281732-34

Figure 11·20. AUI Receive Timings
Table 11·17. AUI Collision Timings
Symbol

Parameter

Min

Typ

80

t145

CLSN Pair .Cycle Time

t146

CLSN Pair Rise/Fall Times

t147

CLSN Pair Return to Zero from
Last Positive Transition

160

t148

CLSN Pair High/Low Times

35

Max

Unit

118

ns

10

ns
ns

70

ns

CLSN

pair

281732-35

Figure 11·21. AUI Collision Timings
Table 11·18. AUI Noise Filter Timings
Symbol

Parameter

Min

Typ

Max

Unit

t152

RCV Pair Noise Filter Pulse Width
Accept(@ -285 mV)

25

ns

t153

CLSN Pair Noise Filter Pulse Width
Accept (@ -285 mV)

25

ns

300mV
--- 285 mV

281732-36

Figure 11·22. AUI Noise Filter Timings

1-360

82595FX

Table 11-19. Jabber Timings
Symbol

Parameter

Min

Typ

Max

Unit

t165

Maximum Length Transmission before
Jabber Fault (TPE)

20

25

150

ms

t166

Maximum Length Transmission before
Jabber Fault (AUI)

10

13

18

ms

t167

Minimum Idle Time to Clear Jabber Function

250

275

750

ms

TRMT

0'
TO

281732-37

Figure 11-23. Jabber Timings
Table 11-20. LED Timings
Typ

Parameter

Min

t170

ACTLED On Time

50

t171

ACTLED Off Time

50

ms

t172

LlLED On Time

50

ms

t173

LlLED Off Time

100

ms

Symbol

Max

Unit

450

ms

281732-38

Figure 11-24. LED Timings

1-361

82595FX

Additional 82595FX Documentation·
This datasheet provides complete pinout .and pin
definitions, and electrical specifications and timings.
It also includes an overview of the various subsections listed in Figure 1. For more complete information on the 82595FX, please ask your local sales
representative for the 82595FX User's GUide. The
82595FX User's.Guide contains detailed information

1-362

on the 82595FX feature set, including register descriptions and implementation steps for various
82595FX ·functions (initialization, transmission, reception).
.

Design Example
The schematic on the next page shows a typical
82595FX design.

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intel·

AP-368 '
APPLICATION
NOTE

82557 10/100 Mbps PCI LAN
Controller
A Guide to 82596
Compatibility

Technical Marketing
Network Products Division

November 1995

Order Number: 644126·001

82557 10/100 Mbps PCI LAN CONTROLLER
A GUIDE TO 82596 COMPATIBILITY
CONTENTS

PAG~

1.0 INTRODUCTION ................... 1·366
2.0 THE 82557 LAN CONTROLLER ... 1·366
3.0 FEATURE CHANGES IN THE
82557 ............................... 1-367
4.0 FUNCTIONAL CHANGES BETWEEN
THE 82557 AND 82596 .............. 1-367
4.1 New Enhancements in the
82557 ............................ 1-367
4.2 Functions in the 82596 Not
Supported by the 82557 ........... 1-368

CONTENTS

PAGE

5.0 SOFTWARE INTERFACE
COMPARISONS ..................... 1-368
5.1 The 82557 Control Status Register
(CSR) .............................. 1-368
5.2 SCB Command Comparisons .... 1-372
5.3 SCB Status/Acknowledge
Comparisons ..................... 1-373 .
5.4 Action Command Comparisons .. 1-373
5.5 Configure Parameter
Differences ....................... 1-374
5.6 PORT Interface Comparisons .... 1-376
5.7 Statistical/Error Information
Comparisons ..................... 1-376

6.0 ADDITIONAL INFORMATION ..... 1-377

I

1-365

AP-368

1.0

INTRODUCTION

Over the last few years, the networking environment
has evolved to account for the needs of high-bandwidth. Fast Ethernet,· otherwise known as IEEE
looBASE-T, is a technology derived from 10BASE-T
Ethernet and was designed to address many of the performance bottlenecks associated with classic 10 Mbit
Ethernet networks. Intel's Fast Ethernet component
product solution includes the 82557 and 82553 components.
This application note provides information on the differences between the Intel 82596 and the Intel 82557
next generation family of LAN controllers. It explains
82596 to 82557 compatibility for Ethernet designers.
The application note can help designers transition from
an existing 82596 LAN solution to an 82557 solution.
For further information on the 82557, refer to the
82557 Data Sheet and the 82557 User's Manual, avail-

able from an Intel Sales Representative.

2.0 THE 82557 LAN CONTROLLER
The 82557 is Intel's first highly-integrated 32-bit PGI
LAN controller for 10 or 100 Mbps Fast Ethernet networks. The 82557 offers a high performance LAN solution while maintaining low-cost through its high-integration. It contains a high-performance 32-bit PCI Bus
Master interface to fully use the high bandwidth available (up to 132 Mbytes per second) to masters on the
PCI bus. The 82557 is optimized to support
twisted pair Ethernet, the required wiring media for
looBASE-T.
The 82557 contains a number of high-performance networking features that off-load time-critical tasks from
the CPU. Its bus master architecture can eliminate the
"intermediate copy" step in Receive (RCV) and Transmit (XMT) frame copies,· resulting in faster processing
of these frames. It maintains a similar memory structure to the Intel 82596 LAN Coprocessor, however,
these memory structures have been streamlined for better Network Operating System (NOS) interaction and
improved performance.
The 82557 contains two separate RCV and XMT
FIFOs, preventing data overruns or underruns while
waiting for access to the PCI bus. The FIFOs also enable back to back frame transmission within the minimum inter-frame spacing. Full support for up tci 1Mbyte

1-366

of FLASH provides remote Boot capability (a BIOS
extension stored in the FLASH which could allow a
node to boot itself off of a network drive). For
100 Mbps applications the 82557 contains an IEEE
MIl compliant interface to the Intel 82553 physical interface device (or other MIl compliant PHY) which
provides a complete LAN solution for 100/10 Mbps
networks. For 10 Mbps networks, the 82557 can be
interfaced to a standard ENDEC interface (such as the
Intel 82503 Serial Interface component), while maintaining software compatibility to 100 Mbps solutions.
The 82557 was designed to implement cost-effective,
high-performance PCI add-in adapters, or it can also be .
used directly on a PC motherboard designs. ItS combi. nation of high integration and low cost make it ideal for
either application.
82557 Feature Summary

• Glueless 32-bit PCI bus master interface (direct
. drive of bus)---compatible to PCI spec Rev 2.1
• 82596-like chained memory structure
• Improved dynamic transmit chaining for enhanced
performance
• Programmable transmit threshold for improved bus
utilization
• Early receive interrupt for concurrent processing of
receive data
• Built-in FLASH· interface with addressing up to
1 MByte
• On-chip receive and transmit FIFOs
• On-chip counters for network management
• Support for back to back transmit interframe spacing (IFS)
• Built in EEPROM interface
• Support for both 10 Mbps and 100 Mbps networks
• Interface to MIl-compliant physical interface such
as the Intel 82553 Serial Component for 10/100
Mbps designs-IEEE 802.3 looBASE-T compatible
• Interface to Intel 82503 for 10 Mbps designs-IEEE
802.3 10BASE-T compatible
• Autodetect and autoswitching for 10 or 100 Mbps
network speeds
• Full duplex capable at 10 and 100 Mbps
• 160 Lead QFP package

AP-368

3.0

FEATURE CHANGES IN THE
82557

The 82557 is a follow-on to the 82596 LAN controller.
Intel made a number of changes and enhancements in
the 82557 to increase performance while being cost sensitive. The following table highlights key functional and
physical changes between the 82557 and 82596:
Feature

82557

Maximum Serial
Speed

100r 100 Mbps

82596
10 Mbps

Mil

No

Bus Interface

32-Bit Local
Bus

Bus Bandwidth

106 Mbytes/
Sec. @33MHz

Architecture

Master

Shared Memory
Structures

Initialization
Root, SCB,
CBL,RFA

Transmit!
Receive
Structures

82586,
Simplified,
Flexible

Memory
Addressing

82586, 32-Bit
Segmented,
linear

FIFO

128 Byte RX,
64 Byte TX

Byte Ordering

little, Big
Endian

FLASH
Interface

No

Package

132-Pin PQFP,
PGA

Pin Compatible

No

Bursting

4 Dword

4.0

FUNCTIONAL CHANGES
BETWEEN THE 82557 AND
82596

This section lists primary functional changes between
the 82557 and the 82596. Some are functional enhancements, others are deletions of the 82596 functionality.

4.1

I

New Enhancements in the 82557

• FIFO size: the 82557 includes independent on-chip
Transmit and Receive FIFOs (3 Kbytes each); the
82596 includes 64 byte transmit and 128 byte receive on-chip FIFOs.
• General chip control structure changes: in the
82557, an on-chip CSR structure incorporates SCB,
Flash/EEPROM and MOl registers. In the 82596,
the shared memory SCB, ISCP, and SCP structures
were used for general chip control.
• Operational speed flexibility: the 82557 supports either 10 or 100 Mbit operation. The 82596 supports a
10 Mbit operation only (ignoring full duplex functionality in both).
• Reset functionality: the 82557 includes a selective
reset command which specifically resets CU and
RU without affecting the overall device configuration. The 82596 includes the CU_ABORT command which terminates the current CU activity and
returns the CU to a known (Idle) state.
• OMA resource tuning: in the 82557, Tx and Rx
OMA preempt counts allow direct manipulation of
OMA resources to reflect design biases towards either transmit or receive functions. The 82596 has a
fixed priority scheme for managing OMA resources.
• Statistical counters: the 82557 contains 16 on-chip
statistical counters that are automatically updated
with each transmit/receive command. The 82596
TCB stores statistical data which must be compiled
by the driver for each TCB before continuing to the
next command.
• MIl: the 82557 supports MIl interface compatibility
(includes MIl specific control and data signals and
MOl register). The 82596 includes a generic
ENOEC serial interface.
• PCI: the 82557 includes a full 32-bit PCI standard
interface. The 82596 includes a 32-bit local bus interface.
• Bus throughput: the 82557 allows a 132 Mbyte maximum parallel (PCI) bandwidth at 33 MHz. The
82596 allows a 106 Mbyte maximum parallel bandwidth at 33 MHz.
• Flash capable: the 82557 allows for a flash memory
interface (control and addressing up to I Mbyte).
The 82596 does not allow for designs requiring flash
memory devices.
• Full duplex: the 82557 is truly Full duplex capable
using FOX and FULHAL pins for controlling full
duplex functionality. The 82596 implements a limited full duplex capability.

1-367

AP-368

• Adaptive IFS: the 82557 supports an adaptive IFS.
algorithm which maximizes network throughput.
The 82596 includes a tunable IFS parameter for
manually adjusting IFS.
• Bursting: the 82557 allows bursting of 256 Dword
lengths. The 82596 allows bursting of 4 Dword
length.
• Early Transmit Completion Status: the 82557 reports a completion of a transmit command as soon
as the frame is copied from menioryso that the driver can reuse resources to prepare a new transmit
command.
• Transmit threshold: the 82557 incorporates a transmit threshold parameter which allows adjustment to
the FIFO level at which the Transmit process begins. The 82596 begins the Transmit process as soon
as the first Dword reaches the bottom of the transmit FIFO.
• Addressing modes: the 82557 uses an enhanced linear addressing mode for all operations. The 82596
uses either linear or 32-bit segmented (82586) addressing modes.

4.2 Functions in the 82596 not·
Supported by the 82557

5.0 SOFTWARE INTERFACE
COMPARISONS
Both the 82557 and 82596 use a shared memory com- .
munication system with the CPU. However, the 82557
uses only three parts that comprise the shared memory
structure: Control/Status Registers (CSR), Command
Block List (CBL), and the Receive Frame Area (RFA).
The 82:196 memory structure is divided into four parts:
the Initialization Root, the System Contro/Block. the.
Command Block List, arid the Receive Frame Area.
One of the main differences in the 82557 and 8259.6
memory structures is the 82557 System Control block
(SCB) residing on-chip (accessed by either I100r
memory .cycles) as part of the Control Status Register
(CSR). In the 82596, the channel attention signal is
used by the 82596 to access the System Configuration
Pointer (SCP) and the Intermediate System Configuration Pointer (ISCP). The ISCP then points to the SCB
(see Figure 2). However, the SCB serves the same purpose in both the 82596 and 82557. It is a central communication point for exchanging control and status information ,between the CPU and the 82557. The CPU
controls the state of the Command Unit (CU) and Receive Unit (RU) (e.g. Active, Suspended or Idle) by ,
writing commands to the SCB. The '82557 and 82596
updates the SCB Status Word to provide status.

• Byte Ordering: the· 82557 supports Little Endian
mode oilly (no Big Endian mode)..
• Addressing: the 82557 has no 82586 compatible ad-.
dressing modes.
• Adjustable frame length: the 82557 has rio Minimum Frame Length variable (82557 has a default
minimum frame length of 64 bytes).
• Monitor mode: the 82557 has no monitoring mode
for evaluating incoming frames.
• Adjustable slot time: the 82557 has no support for
an adjustable slot time parameter.
• Control structures: the 82557 does not include SCP,
SCB or ISCP shared memory structures (on-chip
CSR replaces SCB).
• CRC: CRC flexibility is not supported in the 82557
(No CRC and CRC-16/CRC-32 options are not
present).

1-368

5.1 The 82557 Control Status Register
(CSR)
The 82557 CSR registers, MOl, Flash, PORT, MDI
Control, and General Pointer allow the CPU to read to
and from an EEPROM, FLASH, Management Data
Interface (in the case of MDI, Flash, and MDI Control). They also point to various data structures in
memory, reset the 82557, etc. (for General Pointer and
PORT, respectively). In contrast, the 82596 does not
include FLASH or MDI in its SCB; it uses RFA Off-:
set/CBL Offset, as opposed to the 82557 General·
Pointer. The 82596 also uses T-ON and T-OFF parameters in its SCB, which the 82557.does not use. Additionally, the 82596· uses the PORT# pin to allow the
CPU to directly access it for certain function, as opposed to the 82557, which has a PORT register within
its SCB.

AP-368

82557 Registers

644216-1

Figure 1.82557 Shared Memory Structure·

1-369

AP-368

.(System Memory)

644216-2

Figure 2. 82596 Shared Memory Structure

1-370

AP-368

Upper Word

31
ACK

Lower Word

16 15

I x I cuc I R I

RUC

RFAOFFSET

I0 I0 I0 I0 I
I

STAT

10J

CUS

I

RUS

o

IT I 0 I 0 I 0

CBLOFFSET·

CRCERRORS
ALIGNMENT ERRORS
RESOURCE ERRORS
OVERRUN ERRORS
RCVCOT ERRORS
SHORT FRAME ERRORS

I

T-ONTIMER

T-OFFTIMER

Figure 3. 82596 System Control Block
31

Upper Word

16

15

I

SCB Command Word

Lower Word

o

SCB Status Word

SCB General Pointer
PORT

I

EEPROM Control Register

Flash Control Register

MOl Control Register

Figure 4. 82557 Control Status Register

The 82557 Command Block List (linked list of individual action commands) and Receive Frame Area (list of
free frame descriptors and data buffers) are very similar
to those of the 82596. Transmit commands can be programmed in either Simplified or Flexible memory
modes. The Receive Frame Area consists of Receive
Frame Descriptors (RFDs) and Receive Buffer De-

scriptors (RBDs). The 82596 RFD can be one two
types: Simplified or Flexible. For the 82557, its RFD
can be one of three types: Simplified, Flexible, or Header.
Detailed memory structure differences are highlighted
in Sections 5.2 through 5.7.

1-371

Ap·368

5.2
Type of c::ommand
Parameter
CPU Acknowledge
Events

Other

1-372

Reset (logically same as hardware
RESED
.

AP-368

5.3 SCB Status! Acknowledge Comparisons
Type of Status
82557
Interrupt Acknowledgment

82596
CX: CU finished executing a
command with its "I" bit set.

CX/TNO: CU finished executing a

command with "I" bit set, or
indicates transmit command ended
NOT OK. (configurable)
FR: RU finished receiving the frame,
or header part of frame.

FR: RU finished receiving a frame.

CNA: Command unit left the Active
state and entered the idle state.
(configurable)

CNA: Command unit left the active
state.

RNR: Receive unit left the Ready
state.

RNR: Receive unit left the Ready
state.
N/A

MDI: MDrread or*itecycleis
completed: (configurable)

........•..

S,,¥I: Software generated interrupt. ...' N/A
CU Status

.

Idle

Idle
.'

suspended .'
Active.···..•.....•.
RU Status

Suspended
Active

'"

..

. 1(i1a . . . . •.•. . . .•. . .•. . . . •. . ' '"
suspended>

..

'

Idle
Suspended

'

No Resources

No Resources

....

"

Rl;lady

... Ready
....•...

SusPElndedwith no moreH6Ds

NO (esolJrges que to no more R6Ds
ReadyWithnoRBDs present

N/A
No resources due to no more RBDs

...•.....

Ready with no RBDs present

5.4 Action Command Comparisons
Type of Command
Action Commands

82557

Op Code

82596

Op Code

..

000

001

IndiltidualAddr~ss Setup

001

Individual Address Setup

010

Q6nfigure

010

Configure

000

NOP

........

011

Multicast Address Setup

100

Transmit

."

Aes~rlted . · •.•.• ····

101
110
111

I

....

..'

Dump".'.
:.,
.... . .....
Diagnose ......• ..•........

NOP

011

Multicast Address Setup

100

Transmit

101

TDR

110

Dump

111

Diagnose

1-373

Ap·368

5.5 Configure Parameter Differences
Parameters

Configure Command
Parameters
FIFO/DMA Parameters

Op
Code

010

..'::

·'82557
.'

....

Op
Code

,

...

82596

010

··RX.FII=O Limit. ".

..

,

TXFIFO limit .,

.

FIFO Limit

.'.

FIFO Limit

Byte Count

N/A
N/A
N/A

Statistical/Error Parameters

Save Bad Frames

Frames
. N~A' .

'.'

:t.

N/ A (use Min. Frame length)

." .•, ' . : .,

.NtA ..'

,.

No CRC Insertion
CRC-16/CRC-32

r-----------------+-----I N. 1A~~~,-.:~. ~.:--~~'.-~:.~:----+-C-R-C-in-M--em-o-~~------~
Monitor Bits
y

N'!t...
IEEE Parameters

Il~ear PriorItY ':" ..

Monitor

"

Linear Priority

N/A
No Source Address Insertion
Backoff Method

.' "
".
;JIIIA
....................

: ..... .

Slot Time
Maximum

Ret~

Number

Disable Backoff
Exponential Priority

1-374

AP-368

5.5 Configure Parameter Differences (Continued)
Parameters

Op
Code

82596

1-375

AP·368

5.6 PORT Interface Comparisons
82596

82557

Software Reset

. Software Reset
...•

... Self·TMt

Self-Test

NI A (must use CU/RU Abort)

"Selective Resel

Dump,

Dump

N/A

...

SCP

5.7 Statistical/Error Information Comparisons
82596
Statistical/Error

. on chip C()uhter
. ,on chip counter·
,TrahsmitMultiple COllisions
"

"

1-376

' c

<0

".

c

, ' ,

Location in
MemoryIOn-Chip

N/A

N/A

Transmit Maximum Collisions
(number of collisions
experience per frame; used
with Transmit Attempt
Stopped)

in TCB (per frame)

Transmit Attempt Stopped
(stopped because number of
collisions exceeded max.
. number of retries)

in TCB (per frame)

Transmit Late Collision

in TCB (per frame)

Transmit Underrun

in TCB (per frame)

Transmit Lost Carrier Sense

in TCB (per frame)

Transmit Deferred

in TCB (per frame)

Use Transmit Max. Collisions

0" chip ci<>~nter
N/A

N/A

Receive CRC Errors

inSCB

Receive Alignment Errors

in SCB

Receive Resource Errors

in SCB

Receive Overrun Errors

in SCB

Receive Collision Detect Errors

in SCB

Receive Short Frame Errors

in SCB

Heartbeat Indicator

in TCB (per frame)

Transmit lost Clear to Send

in TCB (per frame)

AP-368

6.0

ADDITIONAL INFORMATION

For additional literature contact your local Intel sales
office or contact the Intel Literature Center by calling
1-800-548-4725. If you need design information, contact your local Intel Field Applications Engineer.

1-377

2
Telecommunication
Products

I

2910A
PCM CODEC fLlAW
8-BIT COMPANDED AID AND 01 A CONVERTER
a

•

Per Channel, Single Chip Codec

iil 78dB Dynamic Range, with Resolution

•
Microcomputer Interface with On-Chip
• Timeslot
Computation
Direct Mode Interface When
• Simple
Fixed Timeslots are Used
• ±S% Power Supplies: +12V, +SV, -SV

Equivalent to 12-Bit Linear Conversion
Around Zero

CCITT G711 and G712 Compatible, ATT
T1 Compatible with 8th Bit Signaling

III Precision On-Chip Voltage Reference
IiiIi Low Power Consumption 230 mW Typ.

Standby Power 33mW Typ.
[;!)

Fabricated with Reliable N-Channel
MOS Process

The Intel 2910A is a fully integrated PCM (Pulse Code Modulation) Codec (Coder·Decoder), fabricated with
N·channel silicon gate technology. The high density of integration allows the sample and hold circuits, the
digital-to·analog converter, the comparator and the successive approximation register to be integrated on the
same chip, along with the logic necessary to interface a full duplex PCM link and provide in·band signaling.

The primary applications are in telephone systems:
• Transmission

-T1 Carrier

• Switching
• Concentration

-Digital PBX's and Central Office Switching Systems
-Subscriber Carrier/Concentrators

The wide dynamic range of the 291 OA (78dB) and the minimal conversion time (80fLsec minimum) make it an
ideal product for other applications, like:
• Date Acquisition

• Telemetry

• Secure Communications Systems

0

Signal Processing Systems
CAP

'x

CLKc

CAP2l(

De

VFx

@

SIG x

®

VFx

TRANSMIT SECTION AID

AUTO

FS x

GRDA

0 AUTO
CD CAP lx
0 CAP2 x

@
Ox @
ClK x @
FS x @
TS x

SAMPLE
SUCCESSIVE
APPROXIMATION
REGISTER

&
HOLD

SIGH

FS R

voo

CLK R

""

PON
VFR

Vee
TS x

Ox

NC
NC

006785-1
1-L...'_+_Oe

@

r.---t-- Cl"c ®
L-,--J----jr-- PON ®
r-'--i---t.-OR

®

I--+__ CLK A @
r-t--FSR @

@

VFR_-t_C

®

~GR--t-------------------------------~

Figure 2. Pin
Configuration
CAP 1x, CAP 2x

Holding Capacitor

VFx

Analog Input

VFR

Analq9 Output

DR, Dc. SIGx

Digital Input

SIGR. Ox. TSx

Digital Output

CLKc, CLKx. CLKR

Clock Input

FSx. FSR

Frame Sync Input

AUTO

Auto Zero Output

VB8

Power (-5V)

GRDA

GRDD

Vee

Power (+5V)

®

@

VDD

Power ( + 12V)

PDN
GRDA

Analog Ground

QPINNLM&R

006785-2

Figure 1. Block Diagram

GRDD
NC

Power Down

Digital Ground
No Connect

Figure 3. Pin Names
The complete document for this product is available on Intel's "Data·on·Demand" CD·ROM product. Contact
your local Intel field sales office, Intel technical distributor, or call 1·800·548·4725.
November 1986
Order Number: 006785·002

2·1

2911A-1
PCM CODEC-ALAW
8-BIT COMPANDED AID AND DIA CONVERTER
Per Channel, Single Chip Codec
• CCITT
G711 and G732 Compatible,
• Even Order
Bits Inversion Included
Microcomputer Interface with On-Chip
• Time-Slot Computation
Simple Direct Mode Interface When
• Fixed
Timeslots Are Used
±5% Power Supplies: + 12V, +5V, -5V
•

dB Dynamic Range, with Resolution
• 66Equivalent
to 11-Bit Linear Conversion
Around Zero
On-Chip Voltage Reference
• Precision
Low Power Consumption 230 mW Typ.
• Standby Power 33 mW Typ.
with Reliable N-Channel
• Fabricated
MOS Process

The Intel 2911 A is a fully integrated PCM (Pulse Code Modulation) Codec (Coder·Decoder), fabricated with
N·channel silicon gate technology. The high density of integration allows the sample and hold circuits, the
digital·to·analog converter, the comparator and the successive approximation register to be integrated on the
same chip, along with the logic necessary to interface a full duplex PCM link.
The primary applications are in telephone systems:
• Transmission
• Switching
• Concentration

-

30/32 Channel Systems at 2.048 Mbps
Digital PBX's and Central Office Switching Systems
Subscriber Carrier/Concentrators

The wide dynamic range of the 2911A (66 dB) and the minimal conversion time (80 f-ts minimum) make it an
ideal product for other applications, like:
.
• Secure Communications Systems
• Signal Processing Systems

• Data Acquisition
• Telemetry

TRANSMIT SECTION AID

o

VF. --r---i
f4' AUTO
SAMPLE
""

CD CAP \
0 CAP2 x--t----I

&

r------l---J- TS.
1-----1

HOLD

0.

SUCCESSIVE
APPROXIMATION

,.

elK"

REGISTER

FS.

""
\!.:!I

@

r,w.

@

270158-1

Figure 1. Pin
Configuration
CAP 1x. CAP 2x
VFx
VFR

@
1--+-_CL"c@

L-r--.JI-1-- 'ON ®

Analog Output
. Digitallnput

DR. De
Ox. TSx
CLKe. CLKx. CLKR
FSx. FSR
AUTO

r...L..--,~-I._oc

Holding CapaCitor
Analog Input

\

r.L..-l-:--I--o"

Digital Output
Clock Input
Frame Sync Input

O/A

0

I--....._CLK.@
I--.....- F S . @

L...-_..J

Auto Zero Output

Vee

Power (-SV)

Vee
Voo
PDN
GRDA

Power(+SV)
Power (+ 12V)
PowerOown
Analog Ground

GRDD

Digital Ground

NC

No Connect

OPlNNLMIER

270158-2

Figure 3. Block Diagram

Figure 2. Pin Names
The complete document for this product is available on Intel's "Oata-on-Oemand" CD-ROM product. Contact
your local Intel field sales office, Intel technical distributor, or caI/1-800-S48-412S.
2-2

November 1986
Order Number: 270158-001

2912A
PCM TRANSMITIRECEIVE FILTER
Power Consumption:
• Low
60 mW Typical without Power

Gain in Both Directions
• Adjustable
Fully Compatible with the Industry
• Standard
Intel 2912
03/04 and CCITT G712 Compatible
• Common
Mode Op Amp Input Rejection
• 75 dB Typical
Direct Interface to the Intel
• 2910A/2911A
PCM Codecs Including

Amplifiers
80 mW Typical with Power Amplifiers
0.5 mW Typical Standby
Idle Channel Noise:
• 2LowdBrncO
Typical, Receive
6 dBrncO Typical, Transmit
Power Supply Rejection:
• 40Excellent
dB Typical on V
50 KHz

•

CC

@

30 dB Typical on Vee

@

Stand-By Power Down Mode
Interface with Transformer or
• Direct
Electronic Hybrids
with Reliable N-Channel
• Fabricated
MOS Process

50 KHz

Transmit Filter Rejects Low
Frequency Noise:
23 dB @ 60 Hz
25 dB @ 50 Hz
50 dB @ 16-2/3 Hz

The Intel 2912A 2nd generation PCM line filter is a fully integrated monolithic device containing the two filters
of a PCM line or trunk termination. It has improved key parameters of power consumption, idle channel noise,
and power supply rejection. A single part exceeds both AT&T* 03/04 and CCITT transmission specs, exceeds digital Class 5 central office switching system stringent specifications, and is fully compatible with the
2912. The primary application for the 2912A is in telephone systems for transmission, switching, or remote
concentration.
An advanced version of the switched capacitor technique used for the 2912 is used to implement the transmit
and receive passband filter sections of the 2912A. The.device is fabricated using Intel's reliable two layer
poly'silicon gate NMOS technology. (See Inte.1 Reliability Report RR-24 on the 2910A, 2911 A, and 2912.) The
combination of advances in the switched capacitor techniques first used on the 2912 and the NMOS technology results in a monolithic 2912A filter which is packaged in a standard 16-pin DIP.

F

YF.I·

0

Pin Names

~~

0v
x'·
(!)
GS,

VFICO@.

VF)(I·

VFJCO

VFxl-

GRDA

GS.

~b::

@PWRo"

0""Ro-

VFRO

YF"I@

I

PDN

elK

@
@

CLKO@

NRI YF"O

O,,··u....

®0

v.. Vee

0 0

PWRI

CLKO

•

PWRO·
PWRO-

VFRI

lie.

270159-2

GRDD GADA

@ @
270159-1

VFXI+, VFxl
GSx
VFxO
VFRI
VFRO
PWRI
PWRO+,PWRO
CLK
CLKO
PDN
Vee
VBB
GRDD.
GRDA

Analog Inputs
Gain Control
Analog Output .
Analog Input
Analog Output
Driver Input
Driver Output
Clock Input
Clock Selection
Power Down
Power (+5V)
Power (-5V)
. Digital Ground
Analog Ground

Figure 2. Pin Configuration

Figure 1. Block Diagram
-AT&T is a registered trademark of American Telephone and Telegraph Corporation.

The complete document for this product is available on Intel's "Data-on-Demand" CD-ROM product. Contact
your local Intel field sales office, Intel technical distributor, or cal/1-800-S48-412S.
September 1988
Order Number: 270159-002

2-3

2913 AND 2914
COMBINED SINGLE-CHIP PCM CODEC AND FILTER

•
•
•

2914 Asynchronous Clocks, 8th Bit
Signaling, Loop Back Test Capability

•

Pin Selectable p.-Law or A-Law
Operatior:'l

•

Two Timing Modes:
Data Rate Mode.
1.536, 1.544, or 2.048 MHz
- Variable Data Rate Mode
64 KHz 2.048 MHz

2913 Synchronous Clocks Only, 300 Mil
Package

AT&T D3/D4 and CCITT Compatible for
Synchronous Operation

Exceptional Analog Performance
• 28-Pin
Leaded Chip Carrier
• (PLCC)Plastic
for Higher Integration
Power HMOS-E Technology:
• -Low5 mW
Typical Power Down
-140 mW Typical Operating
Differential Architecture Enhances
• Fully
Noise Immunity
Auto Zero, Sample and Hold,
• On-Chip
and Precision Voltage References
Interface with Transformer or
• Direct
Electronic Hybrids

~ Fixed

The Intel 2913 and 2914 are fully integrated PCM codecs with transmit/receive filters fabricated in ahighly
reliable and proven N-channel HMOS silicon gate technology (HMOS-E). These devices provide the functions
that were formerly provided by two complex chips (2910A or2911 A and 2912A). Besides the higher level. of
integration, the perf()rmanceof the 2913 and 2914 is superior to that of the separate devices.
.
The. primary applications for the 2913 and 2914 are in telephone systems:
• Switching-Digital PBX's and Central Office Switching Systems
• Transmission-D3/D4 Type Channel Banks and Subscriber Carrier Systems
~

Subscriber Instruments-Digital Handsets and Office Workstations

The wide dynamic range of the 2913 and 2914 (78
products for other applications such as:

dB)a~d

the minimal conversion time make them ideal

• Secure Communications Systems
• Satellite Earth Stations

• Voice Store and Forward
• Digital Echo Cancellers

PLCC 28-Lead Rectangular

..

'"0 ~+ =< R<
:IE

v••

Vee

GS,

v..

Vee

PWAO+

PWRO+

GS,

PWRO-

VF.I-

PWROGS.

VF.I -

GS.

YF.I+

+

PiiN

GADA

OADA'

CLKSEL

PON

CLKSEL
OCLK.

0.
FS.
GRDD

VF.I

ASEL
TS.IDCLK x

.""

FS,

elK"

Ne

LOOP

SIG.IASEL

SIG.

TSxlDCLKx

DCLK"
D.

0,
FS,

FS.

eLK.

GADD

eLK"

210629-1
210629-2

I

.,

I'
VF.I-

NC
GS.

VFxl+

He

OADA
NC

iiiiN
CLKSEL

SIGxlASEL

LOOP

iixlDCLKx

SlO.

Ne

OCLI<"

0,

DR

NC

'Jrann;
g f .r
210629-3

Figure 1. Pin Configurations

The complete document for this product is available on Intel's "Oata-on-Oemand" CD-ROM product. Contact
your local Intel field sales office, Intel technical distributor, or calt 1-800-548-4725.
2·4

September 1993
Order Number: 210629'()04

iATC 29C48

FEATURE CONTROL COMBO
External and User Programmable
• Transmit
and Receive Gain
Programmable External Hybrid Balance
• Network Select
Programmable Analog, Digital and
• Subscriber
Loopback

Programmable pJ A-Law Select
• Secondary
Input Channel
• Low Power Analog
Consumption
• External Tone Injection to Receive Path
• SLD AlB Channel Select (for 16
• Channel Line Cards)

The Intel iATC 29C48 Feature Control Combo is a low cost, user-programmable, fully integrated PCM Codec
with transmit/receive filters fabricated in a CMOS technology. This technology is built on CHMOS and will
allow the 29C48 to realize the same excellent transmission performance as in the Intel 2913/2914 combo
while achieving the low power consumption typical of CMOS circuits.
The 29C48 supports the analog subscriber with a variety of added per-line features to the normal BORSCHT
functions associated with the analog line circuit. Some of these features include secondary analog input
channel, programmable transmit and receive gain, custom hybrid balancing network selection, and programmable J.J. or A-law conversions. Additionally, the 29C48 can operate on either the A or B channel of the SLD
interface, allowing two combos to be connected to one SLD link. In order to facilitate the SLiC interface in this
configuration, the 29C48 generates SLiC chip select signals for the proper routing of signaling information.
A unique feature of the 29C48 is programmable tone injection. This feature and its SLD interface makes it
particularly easy to use in conjunction with Intel's advanced transceivers, such as the iATC 29C53AA, in
subscriber equipment environments. The 29C53AA handles transfer of voice and feature control information
to the 29C48.

28-Lead Rectangular
Plastic Leaded Chip Carrier
;::::

"-

'"

18-Lead Plastic Dual-In-Line Package

Z

[D

I.&J

Vaa

a::::

.....

>

CD
II)

>

U
(.)

>

x

La..

>

vee

VfR

VfX

NC'

26

EBN3/TI

TG1

NC

25

TG2

EBN2

TG2

EBN2

24

NC

EBN1

23

NC

GNDA

NC

EBN

SAl

NC

SCS

SLD

NC

BIA

SDIR

GNDD

SCL
270153-1

N29C48

TG1

NC
21

GNDA

EBN1

SAl

EBN

NC

NC

SLD

IV>
U
V>

• Not connected

c
1<
"- C
III

Z

"

...J

u

V>

'"isV>
270153-2

Figure 1. Pin Configurations
The complete document for this product is available on Intel's "Data-on-Demand" CD-ROM product Contact
your local Intel field sales office, Intel technical distributor, or call1-BOO-54B-4725.
September 1993
Order Number: 270153·008

2-5

3
Communication /
Interface
Controllers

I

8251A
PROGRAMMABLE COMMUNICATION INTERFACE
Synchronous and Asynchronous
• Operation
5-8 Bit Characters;
• Synchronous
Internal or External Character

Baud Rate-DC to 19.2K
• Asynchronous
Baud
Full-Duplex, Double-Buffered
• Transmitter
and Receiver
Error Detection-Parity, Overrun and
• Framing
with an Extended Range of
• Compatible
Intel Microprocessors
DIP Package
• All28-Pin
Inputs and Outputs are TTL
• Compatible
in EXPRESS and Military
• Available
Versions

Synchronization; Automatic Sync
Insertion
Asynchronous 5-8 Bit Characters;
• Clock
Rate-1, 16 or 64 Times Baud
Rate; Break Character Generation; 1,
1%, or 2 Stop Bits; False Start Bit
Detection; Automatic Break Detect and
Handling
Baud Rate-DC to 64K
• Synchronous
Baud

The Intel 8251 A is the industry standard Universal Synchronous/Asynchronous Receiver/Transmitter
(USART), designed for data communications with Intel's microprocessor families such as MCS·48, 80, 85, and
iAPX-86, 88. The 8251A is used as a peripheral device and is programmed by the CPU to operate using
virtually any serial data transmission technique presently in use (including IBM "bi-syn.c"). The USART accepts
data characters from the CPU in parallel format and then converts them into a continuous serial data stream
for transmission. Simultaneously, it can receive serial data streams and convert them into parallel data characters for the CPU. The USART will signal the CPU whenever it can accept a new character for transmission or
whenever it has received a character for the CPU. The CPU can read the complete status of the USART at any
time. These include data transmission errors and control signals such as SYNDET, TxEMPTY. The chip is
fabricated using Intel's high performance HMOS technology.

TxADY

D,

D,

D1

D"

R,D

Vu..

GND

R,e

D,
D;
D"
D,

elK
hD

RD

RxRDY

Axe

RES[ T

WR
es

INTERNAL
DATA BUS

RTS
DSR

he

C/O

RxRDV

DTR

TxEMPTY

eTS
SYNDET/Bo

T)(RDY

205222-2

Figure 2. Pin Configuration

..... SYNOET

205222-1

Figure 1. Block Diagram
The complete document for this product is available on Intel's "Data-on-Demand" CD-ROM product. Contact
your local Intel field sales office, Intel technical distributor, or call 1-800-548-4725.
September 1993
Order Number: 205222-003

3-1

82050
ASYNCHRONOUS COMMUNICATIONS CONTROLLER
I/O Pins
• -Seven
Dedicated Modem I/O

Operation
• -Asynchronous
5- to 8-Bit Character Format
- Odd-, Even-, or No-Parity Generation
and Detection
- Serial Bit Rate: DC to 56 Kb/s
16-Bit Baud Rate
• Programmable,
Generator
Clock
• -System
On-Chip Crystal Oscillator
- Externally Generated Clock

•

28-Lead DIP and PLCC Packages

IBM PC (INS 16450/8250A) Software
• Compatible

- General Purpose I/O
No-TTL Interface to Most Intel
• Processors
Internal Diagnostics with Local
• Loopback
Interrupt and Status
• Complete
Reporting

•

CHMOS III Technology Provides
Increased Reliability and Reduced
Power Consumption

• Line Break Generation and Detection

The Intel CHMOS 82050 Asynchronous Communications Controller is a low cost, higher performance alternative to the INS 16450-it emulates the INS 16450 and provides 100% compatibility with IBM PC software. Its
28-lead package provides all the functionality necessary for an IBM PC environment while substantially decreasing board space requirements. The 82050's simpler system interface reduces TTL glue-especially for
higher frequency PC bus designs: The 82050 provides a low cost, high-performance integrated modem solution when combined with Intel's 89024 modem chip set. The compact 28-pin 82050 is fabricated using
CHMOS III technology for decreased power consumption and increased reliability.

vee
vss
TxD
A(2-0)
0(7-0)
1+-+--RxD

INT
RESET

R5

BUS
INTERFACE
UNIT

16X
TxC

16X
RxC

WR
CS

OUT2

iii
.L-_-DSR
MODEM

CLKXl

I/o

X2

+-+--DCD
DTR
RTS
CTS

-+--+

290137-1

Figure 1. Block Diagram

The complete document for this product is available on Intel's "Data-on-Demand" CD-ROM product. Contact
your local Intel field sales office, Intel technical distributor, or call 1-800-548-4725.
3-2

October 1994
Order Number: 290137-006

82510
ASYNCHRONOUS SERIAL CONTROLLER
MCS-51 9-Bit Protocol Support
• IBM
PC AT' (INS 8250A/16450)
• Software
Compatible
Control Character Recognition
• CHMOS III with Power Down Mode
• Interrupts Maskable at Two Levels
• Auto Echo and Loopback Modes
• Seven I/O Pins, Dedicated and General
• Purpose
• 28-Lead DIP and PLCC Packages

Operation
• -Asynchronous
5- to 9-Bit Character Format
- Baud Rate DC to 288k
- Complete Error Detection
Multiple Sampling Windows
• Two,
Independent, Four-Byte Transmit
• and Receive
FIFOs with Programmable
Threshold
16-Bit Baud Rate Generators/
• Two,
Timers
Clock Options
• -System
On-Chip Crystal Oscillator

(See Packaging Spec .. Order #: 231369)

- External Clocks, Low/High Speed
The Intel CHMOS 82510 is designed to increase system efficiency in asynchronous environments such as
modems or serial ports-including expanding performance areas: MCS-51 9-bit format and high speed async.
The functional support provided in the 82510 is unparqlleled-two baud rate generators/timers provide independent data rates or protocol timeouts; a crystal oscillator and smart modem I/O simplify system logic. New
features, dual FIFOs and Control Character Recognition (CCR), dramatically reduce CPU interrupts and increase software efficiency. The 82510's software versatility allows emulation of the INS8250Al16450 for IBM
PC AT' compatibility or a high-performance mode, configured by 35 control registers. All interrupts are maskable at two levels. The multipersonality I/O pins are configurable as desired. A DPLL and multiple sampling of
serial data improve data reliability for high-speed, asynchronous communication. The compact 28-pin 82510 is
fabricated with CHMOS III technology and includes a software powerdown option.

-

- f-+
Vss - f-+

SERIAL MODULE

Vcc

A(2-0)

D(7-0)
INT

: f-+

TX
MACHINE

RX
FIFO

~

RX
MACHINE

I-

-

cs -

RESET

r--+

TXD

- f-+
INT

4·

Rli
VIR

TX
FIFO

t:

BUS
INTERFACE
UNIT

~

rts L Jx

-~

Jx

T

M-r S Rt

INT
2

INTE:;;';;' BUS

~

I

TIMING
BLOCK
(BRGS. SYS CLOCK)

1X
RXC

+- -

lX
TXC

+- [ - ClK/Xl
+- I - OUT2/X2

I:=f=:

l- illjSClK

+-

MODEM
INTERFACE
MODULE

I - RXD

- f-+
J-+- f-+

DSR/TA/OUTO
OCO/IClK/OUT1
iITR/TB

RTS

I -m
290116-1

Figure 1. Block Diagram
'IBM and PC AT are trademarks of International Business Machines.

The complete document for this product is available on Intel's "Data-on-Demand" CD-ROM product. Contact
your local Intel field sales office, Intel technical distributor, or call 1-800-548-4725.
October 1994
Order Number: 290116-006

3-3

8273
PROGRAMMABLE HOLC/SOLC

PROTOCOL CONTROLLER

•

CCITT X.25 Compatible

• Full Duplex, Half Duplex, or Loop SDLC
• Operation

•

HDLC/SDLC Compatible

Up to 64K Baud Synchronous Transfers

•
Up to 9.6K Baud with On-Board Phase
• Locked
Loop
Automatic FCS (CRC) Generation and
Checking

Programmable NRZI Encode/Decode
• Two
• PortsProgrammable Modem Control
Digital Phase Locked Loop Clock
• Recovery
Minimum CPU Overhead
• Fully
Compatible with 8048/8080/
• 8085/8088/8086/80188/80186
CPUs
• Single + 5V Supply

The Intel 8273 Programmable HOLC/SOLC Protocol Controller is a dedicated device designed to support the
ISO/CCITT's HOLC and IBM's SOLC communication line protocols. It is fully compatible with Intel's new high
performance microcomputer systems such as the MCS 188/186. A frame level command set is achieved by a
unique microprogrammed dual processor chip architecture. The .processing capability supported by the 8273
relieves the system CPU of the low level real-time tasks normally associated with controllers.
REGISTERS
TxlNT RESULT

COMMAND

A.INT RESUL T

PARAMETER

TEST MODE

STATUS
RESULT

DATA
BUS
BUFFER

08 0 _ 7

hD

hl

hDAQ _ _ _ _-,
TxOACK - - - ,
RxORO - - - - ,

RTS

RxDACK

PB'_4

TxlNT
AxlNT

AD

PA 2 _ 4

WR

A,

r-.....:..~......_ _ R.D

RESEr

R.C

cs
elK - - - - - - '

1.-._ _

FLAG DET

CPU INTERFACE

210479-1

Figure 1. Block Diagram

The complete document for this product is available on Intel's "Data-on-Demand" CD-ROM product. Contact
your local Intel field sales office, Intel technical distributor, or call 1-800-548-4725.
3-4

December 1992
Order Number: 210479-004

8274
MULTI-PROTOCOL SERIAL CONTROLLER (MPSC)
Byte Synchronous and
• Asynchronous,
Bit Synchronous Operation
Independent Full Duplex
• Two
Transmitters and Receivers

•

Fully Compatible with 8048, 8051, 8085,
8088, 8086, 80188 and 80186 CPU's;
8257 and 8237 DMA Controllers; and
8089 I/O Proc.

4 Independent DMA Channels
• Baud
Rate: DC to 880K Baud
• Asynchronous:
• - 5-8 Bit Character; Odd, Even, or No
Parity; 1, 1.5 or 2 Stop Bits
- Error Detection: Framing, Overrun,
and Parity

Synchronous:
• -ByteCharacter
Synchronization, Int. or
Ext.
- One or Two Sync Characters
- Automatic CRC Generation and
Checking (CRC-16)
-IBM Bisync Compatible
Synchronous:
• -BitSDLC/HDLC
Flag Generation and
Recognition
- 8 Bit Address Recognition
- Automatic Zero Bit Insertion and
Deletion
- Automatic CRC Generation and
Checking (CCITT-16)
- CCITT X.25 Compatible

• Available in EXPRESS and Military

The Intel 8274 Multi-Protocol Series Controller (MPSC) is designed to interface High Speed Communications
Lines using Asynchronous, IBM Bisync, and SOLC/HOLC protocol to Intel microcomputer systems. It can be
interfaced with Intel's MCS-48, -85, -51; iAPX-86, -88, -186 and -188 families, the 8237 OMA Controller, or the
8089 I/O Processor in polled, interrupt driven, or OMA driven modes of operation~
The MPSC is a 40 pin device fabricated using Intel's High Performance HMOS Technology.

CHANNEL A

RE~I~IJ:RS 1.---'1....
RESEl---_-,

1

GOA

rnA

CLK-------,

CONTROLA
I<~===:::>I CHANNEL
LOGIC

RTS A
SYNDETA

OTR A
CHANNEL A

RE~~SAT~RS I L - - -.....
fi'O/TxDRQa
lPl/RxDRQa

INT
INTA

Ao
A,

I>

cs
Ill)

WR

CHANNEL B

1

SYNDETslRTS B
OTRs

RiC s
INTERNAL DATA BUS

SYSTEM INTERFACE

RxDs

NETWORK INTERFACE

170102-1

Figure 1. Block Diagram
The complete document for this product is available on Intel's "Data-on-Demand~' CD-ROM product. Contact
your local Intel field sales office, Intel technical dlstnbutor, or call 1-800-548-4725.
April 1995
Order Number: 170102-005

3-5

82530/82530-6
SERIAL COMMUNICATIONS CONTROLLER (SCC)
Independent Full Duplex Serial
• Two
Ch'annels
On Chip Crystal Oscillator, Baud-Rate
• Generator
arid Digital Phase Locked
Loop for Each Channel
for NRZ, NRZI or FM
• Programmable
Data Encoding/Decoding

in Express Version
• Available
Modes
• -Asynchronous
5-8 bit Character; Odd, Even or No
Parity; 1, 1.5 or 2 Stop Bits
- Independent Transmit and Receive
Clocks. lX, 16X, 32X or 64X
Programmable Sampling Rate
- Error Detection: Framing, Overrun
and Parity
- Break Detection and Generation

Diagnostic Local Loopback and
• Automatic
Echo for Fault Detection and
Isolation
Synchronous Modes
• -BitSDLC
Clock Rates:
Loop/Non-Loop Operation
• -System
4 MHz for 82530
-CRC-16 or CCITT Generation
- 6 MHz' for 82530-6
Detection
- Abort Generation and Detection
Max Bit Rate (6 MHz)
• - Externally Clocked: 1.5 Mbps
-I-field Residue Handling
Self-Clocked:
375 Kbps FM CODING
187 KbpsNRZI CODING
93 Kbps Asynchronous

•
in 40 Pin DIP and 44 Lead
• Available
PLCC

Interfaces with Any INTEL CPU, DMA or
I/O Processor

- CCITT X.25 Compatible

Synchronous Modes
• -ByteInternal
or External Character
Synchronization (1 or 2 Characters)'
- Automatic CRC Generation and
Checking (CRC 16 or CCITT)
-IBM Bisync Compatible

The INTEL 82530 Serial Communications Controller (SCC) is a dual-channel, multi-protocol data communications peripheral. It is designed to interface high speed communications lines using Asynchronous, Byte synchronous and Bit synchronous protocols to INTEL's microprocessors based systems. It can be interfaced with
Intel's MCS51 196, iAPX86/88/186 and 188 in polled, interrupt driven or DMA driven modes of operation.
The SCC is a 40-pin device manufactured using INTEL's high-performance HMOS' II technology.

• HMOS is a patented process of Intel Corporation.

The complete document for this product is available on Intel's "Oata-on-Oemand" CD-ROM product Contact
your local Intel field sales office, Intel technical distributor, or call 1-800-548-4125.
October 1987
Order Number: 230834-003

3-6
o

8291A
GPIB TALKER/LISTENER
Designed to Interface Microprocessors
MHz Clock Range
• (e.g.,
• 1-8
8048/49, 8051, 8080/85, 8086/88)
16 Registers (8 Read, 8 Write), 2 for
•
to an IEEE Standard 488 Digital
Data Transfer, the Rest for Interface
Interface Bus
Function Control, Status, etc.
Programmable Data Transfer Rate
Directly Interfaces to External Non• Complete Source and Acceptor
•
Inverting Tranceivers for Connection to
• Handshake
the GPIB
Talker and Listener
Provides Three Addressing Modes,
• Complete
• Allowing
Functions with Extended Addressing
the Chip to be Addressed
Either
as
a Major or a Minor Talker/
Service Request, Parallel Poll, Device
• Clear,
Listener with Primary or Secondary
Device Trigger, Remote/Local
Addressing
Functions
Handshake Provision Allows for
Selectable Interrupts
• DMA
• On-Chip
Bus Transfers without CPU Intervention
and Secondary
• Address Primary
Output Pin
Recognition
• Trigger
On-Chip
EOS (End of Sequence)
Handling of Addressing and
•
• Automatic
Message
Recognition Facilitates
Handshake Protocol
Handling of Multi-Byte Transfers
for Software Implementation
• ofProvision
Additional Features
The 8291A is an enhanced version of the 8291 GPIB Talker/Listener designed to interface microprocessors to
an IEEE Standard 488 Instrumentation Interface Bus. It implements all of the Standard's interface functions
except for the controller. The controller function can be added with the 8292 GPIB Controller.

.291A

T/Rl

Vee

TlA2

rot

I

NDAC
NRFD

GPIB CONTROL

TRIG

DAV

DR EO

0108
0107

TO NON·INVERTING

i5i"56

BUS TRANSCEIVERS

0105
0104

I

T/A CONTAOL

D2

i5i153
5i02
DiOi
SAO

D3

ATN

D4

"RE"N

D5

IFe
RS2

205248-1

07

RSl

Figure 1. Block Diagram
205248~2

Figure 2. Pin Configuration

The complete document for this product is available on Intel's "Data-on-Demand" CD-ROM product. Contact
your local Intel field sales office, Intel technical distributor, or caI/1-800-548-4725.
September 1993
Order Number: 205248·003

3-7

8292
GPIB CONTROLLER

/

• Complete IEEE Standard 488 Controller
Function

•

Complete Implementation of Transfer
Control Protocol

• Interface Clear (IFC) Sending Capability
Allows Seizure of Bus Control and/or
. Initialization of the Bus

•

Synchronous Control Seizure Prevents
the Destruction of Any Data
Transmission in Progress

• Responds to Service Requests (SRQ)

•

Connects with the 8291 to Form a
Complete IEEE Standard 488 Interface
Talker/ Listener/Controller

• Sends Remote Enable (REN), Allowing
Instruments to Switch to Remote
Control

The 8292 GPIB Controller is a microprocessor-controlled chip designed to function with the 8291 GPIB Talker/Listener to implement the full IEEE Standard 488 controller function, including transfer control protocol.
The 8292 is a preprogrammed Intel 8041 A.

MICROPROCESSOR SYSTEM BUS

IFCL

r--- ---.
I
I

I
I

OMA
CONTROLLER
(OPTIONAL)

X1

OACK

t------,,....

8291

OREO

GPIB
TALKERI
LISTENER

I
I
L ______ I

8292
GPIB
CONTROLLER

TiR1

BUS
TRANSCEIVERS

COUNT

X2

REN

RESET

OAV

Vee

Cs
T/R 2

Vee

IBFI
OBFI

GND

EOI

lUi

SPI

AD

Tel

WR

CIC

SYNC

NC

DO

ATNO

01

NC

02

CLTH

03

Vcc

04

NC

05

SYC

06

IFC

07

/lTNI

VSS

SRO

205250-2
GENERAL PURPOSE INTERFACE BUS

Figure 2. Pin Configuration
205250-1

Figure 1_ 8291, 8292 Block Diagram

The complete document for this product is available on Intel's "Data-on-Demand" CD-ROM product. Contact
your local Intel field sales office, Intel technical distributor, or call 1-800-548-4725.

3-8

September 1993
Order Number: 205250-003

8294A
DATA ENCRYPTION/DECRYPTION UNIT

•

5V ± 10% Power Supply
• Single
Fully Compatible with iAPX-86, 88,
• MCS-85,
MCS-80, MCS-51, and MCS-48

Certified by National Bureau of
Standards

400 Byte/Sec Data Conversion Rate
• 64-Bit
Processors
Data Encryption Using 56-Bit Key
• DMA Interface
Federal Information
• 3 Interrupt Outputs to Aid in Loading • Implements
Processing Data Encryption Standard
• and Unloading Data
• Encrypt and Decrypt Modes Available

•

7-Bit User Output Port

The Intel B294A Data Encryption Unit (DEU) is a microprocessor peripheral device designed to encrypt and
decrypt 64-bit blocks of data using the algorithm specified in the Federal Information Processing Data Encryption Standard. The DEU operates on 64-bit text words using a 56-bit user-specified key to produce 64-bit
cipher words. The operation is reversible: if the cipher word is operated upon, the original text word is produced. The algorithm itself is permanently contained in the B294A; however, the 56-bit key is user-defined and
may be changed at any time.
The 56-bit key and 64-bit message data are transferred to and from the B294A in B-bit bytes by way of the
system data bus. A DMA interface and three interrupt outputs are available to minimize software overhead
associated with data transfer. Also, by using the DMA interface two or more DEUs may be operated in parallel
to achieve effective system conversion rates which are virtually any multiple of 400 bytes/second. The B294A
also has a 7-bit TTL compatible output port for user-specified functions.
Because the B294A implements the NBS encryption algorithm it can be used in a variety of Electronic Funds
Transfer applications as well as other electronic banking and data handling applications where data must be
encrypted.

DATA
BUS

f\,

KEY

8

_

ROWR

csAo --

SRO--OAVCCMP--

RESET
SYNC - DMA
LOGIC

,_ x,--

~-

DRO
DACK

x,
+ 5V
POWER
GND ..

INTERNAL
BUS

210465-1

NC
Xl
X2
RESET
VCC
CS
GNO
RO
AO
WR
SYNC
DO
01
02
03
04
05
06
D7
GND

VCC
NC
DACK

ORO
SRO
OAV
NC
P6
P5
P4
P3
P2
Pl
PO
VOO
VCC
CCMP
NC
NC
NC

Figure 1. Block Diagram
210465-2

Figure 2. Pin Configuration
The complete document for this product is available on Intel's "Data-on-Demand" CD-ROM product. Contact
your local Intel field sales office, Intel technical distributor, or call 1-800-548-4725.
September 1993
Order Number: 210465-005

3-9

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~9~oS6~~~:t~~~i~e
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FAX: (818) 880-5510
Zeus Arrow
Electronics
6276 San Ignacio
Avenue
Suite E
San Jose 95119
Tel: (408) 629-4689
FAX: (408) 629-4792
Zeus Arrow
Electronics
6 Cromwell Street
Suite 100
Irvine 92718
Tel: (714) 581-4622
FAX: (714) 454-4355
COLORADO

Anthem Electronics
373 Inverness Dr. S.
Englewood 80112
Tel: (303) 790-4500
FAX: (303) 790-4532
Arrow/Schweber
Electronics
61 Inverness Dr East
Suite 105
Englewood 80112
Tel: (303) 799-0258
FAX, (303) 799-0730
Avnet Computer
9605 Maroon Circle
Englewood 80111
Tel: (800) 426-7999
Hall-Mark Computer
9605 Maroon Circle
Englewood 80111
Tel: (800) 409-1483
Hamilton Hallmark
12503 East Eucl~d Dr
Suite 20
Englewood 80111
Tel: (303) 790-1662
FAX: (303) 790-4991

Wyle Electronics
15370 Barranca Pkwy
Irvine 92713
Tel: (714) 753-9953
FAX: (714) 753-9877

Hamilton Hallmark
710 Wooten Road
Suite 28
Colorado Springs
80915
Tel, (719) 637-0055
FAX: (719) 637-0088

Wyle Electronics
15360 Barranca Pkwy
Suite 200
Irvine 92713
Tel: (714) 753-9953
FAX: (714) 753-9877

Blvd.
Suite 201
Englewood 80111
Tel: (303) 773-8090

Wyle Electronics
2951 SUnrise Blvd.
Suite 175
Rancho Cordova 95742
Tel: (916) 638-5282
FAX: (916) 638-1491

~~~~e~~e~~~ono~~Y!~~

Wyle Electronics
451 East 124th Avenue
Thornton 80241
Tel: (303) 457-9953
FAX: (303) 457-4831

CONNECTICUT

Anthem Electronics
61 Mattatuck Heights
Road
Waterburg 06705
Tel: (203) 575-1575
FAX: (203) 596-3232
ArrowlSchweber

Electronics

860 N. Main st. Ext.
Wallinglord 06492
Tel: (203) 265-7741
FAX: (203) 265-7988
Hall-Mark Computer
Still River Corporate Ctr
55 Federal Road
Danbury 0681 0
Tel: (800) 409-1483
Hamilton Hallmark
125 Commerce Court,
Unit 6
Cheshire 06410
Tel: (203) 271-2844
FAX: (203) 272-1704
Plonaer Standard
2 Trap Falls Road
Shelton 06484
Tel: (203) 929-5600
FLORIDA

Anthem Electronics
5200 NW 3rd Avenue
Suite 206
Ft. Lauderdale 33309
Tel: (305) 484-0990
Anthem Electronics
598 S. Northlake Blvd.
Suite 1024
Altamonte Sprgs 32701
Tel: (813) 797-2900
FAX: (813) 796-4880
Arrow/Schweber
Electronics
400 Fairway Drive
Suite 102
Deerfield Beach 33441
Tel: (305) 429-8200
FAX: (305) 428-3991
Arrow/Schweber
Electronics
37 Skyline Drive
Suite 3101
Lake Mary 32746

~~lx~(~M~~3:~~~0
ArrowlSchweber
Electronics

~~1t~ ~~~ Scout Dr.
Tampa 33607
Tel: (813) 873-1030
FAX: (813) 873-0077

Avnet Computer
541 S. Orlando Ave.
Suite 203
Mailland 32751
Tel: (800) 426-7999
Hall-Mark Computer
10491 72nd 51. North
Largo 34647
Tel: (800) 409-1483
Hall-Mark Computer
13700 58th SI. North
Suite 206
Clearwater 34620
Tel: (800) 409-1483
Hamilton Hallmark
3350 N.W. 53rd Street
Suite 105-107
Ft. Lauderdale 33309
Tel: (305) 484-5482
FAX: (305) 484-2995

inteJ®
NORTH AMERICAN DISTRIBUTORS (Cont'd)
Hamilton Hallmark
10491 72nd SI. North
Largo 34647
Tel: (813) 541-7440
FAX: (813) 544-4394
Hamilton Hallmark

7079 University Blvd.
Winter Park 32792
Tel: (407) 657-3300
FAX: (407) 678·4414
Pioneer Technologies

~~~':forthlake

Blvd
Suite 1000
Alia Monle Spgs 32701
Tel: (407) 834-9090
FAX: (407) 834-0865
Pioneer Technologies

~~~~uth

Military Trail
Deerfield Beach 33442
Tel: (305) 428-8877
FAX: (305) 481·2950
Wyle Electronics
1000 112th Circle North
SI. Petersburg 33716
Suite 800
Tel: (813) 579-1518
FAX: (813) 579-1518
Zeus Arrow
Electronics

~Td~kd'~:niuPt~i~~ 01
Lake Mary 32746
Suite 800
Tel: (407) 333-3055
FAX: (407) 333·9681
GEORGIA

Anthem Electronics
2400 Pleasant Hill Rd
Suites 9 & 10
Dululh 30136
Tel: (404) 931-3900
FAX: (404) 931-3902
Arrow/Schweber
Electronics
4250 E Riyergreen Pkwy
Suite E
Duluth 30136
Tel: (404) 497-1300
FAX: (404) 476·1493
Avnet Computer
3425 Corporate Way
SuiteG
Dululh 30136
Tel: (800) 426·7999
Hall-Mark Computer
3425 Corporate Way
Sune G
Duluth 30136
Tel: (800) 40~·1483
Hamilton Hallmark
3425 Corporate Way
Suite G & A
Duluth 30136
Tel: (404) 623·5475
FAX: (404) 623-5490
Pioneer Technologies

~~~~g Rivergreen Pkwy

Duluth 30136
Tel: (404) 623-1003
FAX: (404) 623·0665

Wyle Electronics
6025 The Corners Pkwy
Suite 111
Norcross 30092
Tel: (404) 441·9045
FAX: (404) 441-9086
ILLINOIS

Anthem Electronics
1300 Remington Road
Suite A
Schaumberg 60173
Tel: (708) 884-0200
FAX: (708) 885-0480

Arrow/Schwaber
Eloctronlcs

MARYLAND

ZousArrow
Electronics

1140 W Thorndale Rd
Itasca 60143
Tel: (708) 250-0500

Wyla Electronics
1325 East 79th Street

Anthem Electronics

25 Upton Drive
Wilmington 01887
Tel: (508) 658-4776
FAX: (508) 694-2199

Suite 1
Bloomington 55425
Tel: (612) 853-2280
FAX: (612) 853-2298

Avnot Computer
1124 Thorndale Ave
Bensenvillo 60106

Tel: (800) 426-7999
Hall-Mark Computer

1124 Thorndale Ave
Bensenville 60106
Tel: (800) 409-1483
Hamilton Hallmark
1130 Thorndale Ave
Bensenville 60106
Tel: (800) 426-7999
MTI Systems Sales
1140 West Thorndale
Avenue
Itasca 60143
Tel: (708) 250-8222
FAX: (708) 250-8275
Pioneer Standard
2171 Executive Drive
Suite 200
Addison 60101
Tel: (708) 495-9680
FAX: (708) 495-9831
Wyle Electronics
2055 Army Trail Road
Suite 140
Addison 60101
Tel: (800) 853·9953
Zeus Arrow
Electronics
1140 W Thorndale Ave
Itasca 60143
Tel: (708) 250-0500
INDIANA

Arrow/Schweber
Electronics
7108 Lakeview
Parkway West Drive
Indianapolis 46268
Tel: (317) 299·2071
FAX: (317) 299-2379
Avnet Computer
655 West Carmel Drive
Suite 160
Carmel 46032
Tel: (800)426-7999

7168A Columbia
Gateway Drive
Columbia 21046
Tel: (800) 239-6039

MICHIGAN

MISSOURI

Arrow/Schwaber

9800J Patuxent Woods
Drive
Columbia 21046
Tel: (301) 596-7800
FAX: (301) 596·7821

electronics
44720 Helm Street

Arrow/Schwaber
Electronics
2380 Schuetz Road

Plymouth 48170
Tel: (313) 462·2290
FAX: (313) 462-2686

St. Louis 63141
Tel: (314) 567-6888
FAX: (314) 567-1164

Avnat Computer
7172 ColUmbia
Gateway Drive
Suite G
ColumbIa 21045
Tel: (800) 426-7999

Avnet Computer
41650 Garden Brk Ad
Suite 120
Novi 48375
Tel: (800) 426·7999

:j~kTdo:~~i~r South
f:r~8~~j :~g~5999

Arrow/Schwaber
Electronics

Hall-Mark Computer
7172 Columbia
Gateway Drive
SuiteG
Columbia 21046
Tel: (800) 409·1483
Hamilton Hallmark
10240 Old Columbia
Road
Columbia 21046
Tel: (410) 988-9800
FAX: (410) 381-2036
North Atlantic
Industries
Systems Division
7125 RiVer Wood Drive
Columbia 21046
Tel: (301) 312-5800
FAX: (301) 312-5850
Pioneer Technologies
Group
15810 Gaither Road
Gaithersburg 20877
Tel: (301) 921·0660
FAX: (301) 670-6746
Wyle Electronics
9101 Guilford Road
Suite 120
Columbia 21046
Tel: (301) 490-2170
FAX: (301) 490-2190
MASSACHUSETTS

~f~'5~~~r~~nm~r~t~~
Suite 120
Novi 48375
Tel: (800) 409·1483
Hamilton Hallmark
44191 Plymouth Oaks
Blvd.
.
Suite 1300
Plymouth 48170
Tel: (313) 416-5806
FAX: (313) 416-5811
Hamilton Hallmark
41650 Garden Brk Rd
Suite 100
Novi 49418
Tel: (313) 347-4271
FAX: (313) 347-4021
Pioneer Standard
4505 Broadmoor S.E.
Grand Rapids 49512
Tel: (616) 698·1800
FAX: (616) 698-1831
Pioneer Standard
44190 Plymouth Oaks
Blvd.
Plymouth 48170
Tel: (313) 525-1 800
FAX: (313) 427·3720
MINNESOTA

Anthem Electronics
7646 Golden Triangle
Drive
Eden Prairie 55344
Tel: (612) 944-5454 .
FAX: (612) 944-3045

Hall-Mark Computer
655 West Carmel Drive
Carmel 46032
Tel: (800) 409-1483

Anthem Electronics
200 Research Drive
Wilmingto'n 01887
Tel: (508) 657-5170
FAX: (508) 657-6008

Hamilton Hallmark
655 West Carmel Drive
Suite 160
Carmel 46032
Tel: (317) 575-3500
FAX: (317) 575-3535

Arrow/Schweber
Electronics
25 Upton Drive
Wilmington 01887
Tel: (508) 658-0900
FAX: (508)694-1754

Pioneer Standard
9350 Priority Way W Dr
Indianapolis 46250
Tel: (317) 573·0880
FAX: (317) 573-0979

Avnet Computer
100 Centennial Drive
Peabody 01960
Tel: (800) 426-7999

East
Suite 410
Minnetonka 55343
Tel: (800) 426·7999

~~16~~rn~~~~rD~i:e

Hall-Mark Computer
9800 Bren Road East
Suite 410
Minnetonka 55343
Tel: (800) 409·1483

KANSAS

Arrow/Schweber
Electronics
9801 Legler Road
Lenexa 66219
Tel: (913) 541-9542
FAX: (913) 541·0328
Hall-Mark Computer
10809 Lakeview Ave
Lenexa 66219
Tel: (800) 409-1483
Hamilton Hallmark
10809 Lakeview
Avenue
Lenexa 66215
Tel: (913) 888·4747
FAX: (913) 888-0523

Peabody 01960
Tel: (800) 409-1483
Hamilton Hallmark
10 D Centennial Drive
Peabody 01960
Tel: (508) 531-7430
FAX: (508) 532·9802
Pioneer Standard
44 HartwelJ Avenue
Lexington 02173
Tel: (617) 861-9200
FAX: (617) 863-1547
Wyle Electronics
5 Oak Park Drive
Bedford 01803

~Mmm5:5~g9

Arrow/Schweber
Electronics
10100 Viking Orive
Suite 100
Eden Prairie 55344
Tel: (612) 941-5280
FAX: (612) 942-7803

:;~~~7~nmFfou~~~

Hamilton Hallmark
9401 James Ave South
Suite 140
Bloomington 55431
Tel: (612) 881·2600
FAX: (612) 881-9461
Pioneer Standard
7625 Golden Triangle
Drive
.SuiteG
Eden Prairie 55344
Tel: (612) 944-3355
FAX: (612) 944-3794

~~~~~~~~rc-rr~r~~~h
f:r~8~~j :g8~5483
Hamilton Hallmark
3783 Rider Trail South

f:r~3~~j ~2n~50

FAX: (314) 291-0362
NEW HAMPSHIRE

Avnet Computer
2 Executive Park Drive
Bedford 03102
Tel: (800) 426-7999
NEW JERSEY

Anthem Electronics
26 Chapin Road, Unit K
Pine Brook 07058
Tel: (201) 227-7960
FAX: (201) 227-9246
Arrow/Schweber
Electronics
4 East Slow Road
Unit 11
Marlton 08053
Tel: (609) 596·8000
FAX: (609) 596-9632
Arrow/Schweber
Electronics
43 Route 46 East
Pine Brook 07058
Tel: (201) 227-7880
FAX: (201) 227-2064
AVnet Computer
1-B Keystone Avenue

~~~~in~~F08003

Tel:

(~OO) 426-7999

Hall-Mark Computer
l·B Keystone Avenue

~~~~int~F08003
(~OO) 409-1483

Tel:

Hall-Mark Computer
10 Lanidex Plaza West
Parsippany 07054
Tel: (800) 409-1483
Hamilton Hallmark

~~,df~to~~ Avenue

Cherry II-iill 08003
Tel: (609) 424-0110
FAX: (609) 751-2552

Hamilton Hallmark
10 Lanldex Plaza West
Parsippany 07054
Tel: (201) 515-5300
FAX: (201) 515-1601
MTI Systems Sales
43 Route 46 East
brook 07058
Tel: (201) 882·8780
FAX: (201) 539-6430

Pine

NORTH AMERICAN DISTRIBUTORS (Cont'd)
PioneerStandard

Pioneer Standard

Hall·Mark Computer

Pioneer Technologies

14·A Madison Road

60 Crossway Pk West
Woodbury, Long Island
11797
Tel: (516) 921·8700
FAX: (516) 921·2143

777 Dearborn Pk Lane
Suite L
Worthington 43085
Tel: (800) 409·1483

Pioneer Standard
840 Fairport Park

5821 Harper Road

8905 Southwest
Numbus Ave,
Suite 160
Beaverton 97005
Tel: (503) 626·7300
FAX: (503) 626·5300

Solon 44139

Wyle Electronics

Fairport 14450
Tel: (716) 381·7070
FAX: (716) 381·5955

Tel: (216) 498·1100
FAX: (216) 248·4803

9640 Sunshine Court
Building G

Zeus Arrow
Electronics
100 Midland Avenue
Port Chester 10573
Tel: (914) 937·7400
FAX: (914) 937·2553

777 Dearborn Pk Lane
Suite L
Worthington 43085
Tel: (614) 888·3313
FAX: (614) 888·0767

Fairfield 07006

Tel: (201) 575·3510
FAX: (201) 575·3454
Wyle Electronics

115 Route 46. Bldg F
Mountain Lakes 07046

Tel: (201) 402·4970
NEW MEXICO
Alliance Electronics,

Inc.
3411 Bryn MawrN.E.
Albuquerque 87101
Tel: (505) 292·3360
FAX: (505) 275·6392
Avnst Computer
7801 Academy Road
Building 1, Suile 204
Albuquerque 87109
Tel: (800) 426·7999

NEW YORK
Anthem Electronics
47 Mall Drive
Commack 11725
Tel: (516) 864·6600
FAX: (516) 493·2244
ArrowlSchweber
Electronics
3375 Brighton Henrietta
Townline Road
Rochester 14623
Tel: (716) 427·0300
FAX: (716) 427·0735

NORTH CAROLINA
Anthem Electronics
4805 Greenwood
Suite 100
Raleigh 27604
Tel: (919) 782·3550
Arrow/Schweber
Electronics
5240 Greensdairy
Road
Raleigh 27604
Tel: (919) 876·3132
FAX: (919) 878·9517
Avnet Computer
4421 Stuart Andrew
Boulevard
Suite 600
Charlotte 28217
Tel: (800) 426·7999

Arrow/Schwaber
Electronics
20 Oser Avenue
Hauppauge 11788
Tel: (516) 231·1000
FAX: (516) 231-1072

Hall-Mark Computer
3510 Spring Forest Rd
Suite B
Raleigh 27604
Tel: (800) 409·1483

Avnet Computer
2 Penn Plaza
Suite 1245
New York 10121
Tel: (800) 426·7999

Hamilton Hallmark
3510 Spring Forest Rd
Suite B
Raleigh 27604
Tel: (800) 409·1483

Avnet Computer
1057 E. Henrietta Road
Rochester 14623
Tel: (800) 426·7999
Hall-Mark Computer
2 Penn Plaza
New York 10121
Tel: (800) 409·1483
Hal1~Mark Computer
1057 E Henrietta Road
Rochester 14623
Tel: (800) 409-1483

Hamilton Hallmark
933 Motor Parkway
Hauppauge 11788
Tel: (516) 434·7470
FAX: (516) 434·7491
Hamilton Hallmark
1057 E Henrietta Road
Rochester 14623
Tel: (716) 475·9130
FAX: (716)475·9119
Hamilton Hallmark
3075 Veterans
Memorial Hwy.
Ronkonkoma 11779
Tel: (516) 737·0600
FAX: (516) 737·0838
MTI Systems Sales
1 Penn Plaza
250 West 34th Street
New York 10119
Tel: (212) 643·1280
FAX: (212) 643·1288
Pioneer Standard
68 Corporate Drive
Binghamton 13904
Tel: (607) 722·9300
FAX: (607) 722·9562

Hamilton Hallmark

Hamilton Hallmark

MTI Systems Sales
23404 Commerce Pk
Road
Beachwood 44122
Tel: (216) 464·6688
FAX: (216) 464·3564
Pioneer Standard
4433 interpoin! Blvd
Dayton 45424
Tel: (513) 236·9900
FAX: (513) 236·8133
Pioneer Standard
4800 East 131s1 Sireet
Cleveland 44105
Tel: (2t6) 587·3600
FAX: (216) 663·1004
Wyle Electronics
6835 Cochran Rd.
Solon 44139
Tel: (216) 248·9996

OKLAHOMA
Arrow/Schwaber
Electronics
12101 Easl51st Street
Suite 106
Tulsa 74146
Tel: (918) 252·7537
FAX: (918) 254·0917

Suite 200
Beaverton 97005

Tel: (503) 643·7900
FAX: (503) 646·5466
PENNSYLVANIA
Anthem Electronics
355 Business Clr Drive
Horsham 19044
Tel: (215) 443·5150
FAX: (215) 675·9875
Avnet Computer
213 Executive Drive
Suile 320
Mars 16046
Tel: (800) 426·7999
Arrow/Schweber
Electronics
2681 Mosside Blvd
Suite 204
Monroeville 15146
Tel.: (412) 856·9490
Pioneer Technologies

~£~~ppa

Drive
Pittsburgh 15238
Tel: (412) 782·2300
FAX: (412) 963·8255
Pioneer Technologlos

~~g~terprise

Road
Keith Valley- BUs.Clr
Horsham 19044
Tel: (215) 674·4000

~~~~;I~~~~onlcs

Hamilton Hallmark
5234 Greens Dairy Rd
Raleigh 27604
Tel: (919) 878·0819

Hamilton Hallmark
5411 S. 125th E. Ave
Suile 305
Tulsa 74146
Tel: (918) 254·6110
FAX: (918) 254·6207

Suite 111
Marlton 08053-3185
Tel: (609) 985·7953
FAX: (609) 985·8757

Pioneer Technologies
Group
2200 Gateway Clr. Blvd
Suite 215
Morrisville 27560
Tel: (919) 460·1530

Pioneer Standard
9717 East 42nd Street
Suite 105
Tulsa 74146
Tel: (918) 665·7840
FAX: (918) 665·189t

Anthem Electronics
651 N. Piano Road
Suite 401
Richardson 75081
Tel: (214) 238·7100
FAX: (214) 238·0237

OHIO

OREGON

Arrow/Schwaber
Electronics
6573 Cochran Road
Suite E
Solon 44139
Tel: (216) 248·3990
FAX: (216) 248·1106

AlmacArrow
Electronics
9500 S.W. Nimbus Ave
Suite E
Beaverton 97008
Tel: (503) 629·8090
FAX: (503) 645·0611

Antham Electronics
14050 Summit Drive
Suite 119
Tel: (512) 388·0049
FAX: (512) 388·0271

Arrow/Schweber
Electronics
8200 Washington
Village Drive
Centerville 45458
Tel: (5t3) 435·5563
FAX: (513) 435·2049

Anthem Electronics
9090 SW Gemini Drive
Beaverton 97005
Tel: (503) 643·1114
FAX: (503) 626·7928

Avnet Computer
7764 Washington
Village Drive
Dayton 45459
Tel: (800) 426·7999
Avnet Computer
2 Summit Park Drive
Suite 520
Independence 44131
Tel: (800) 426·7999
Hall-Mark Computer
5821 Harper Road
Solon 44139
Tel: (800) 409·t483

Avnet Computer
9750 SW Nimbus Ave.
Beaverton 97005
Tel: (800) 426·7999
Hall~Mark Computer
9750 SW Nimbus Ave.
Beaverton 97005
Teto (800) 409·1483

Hamilton Hallmark
9750 SW Nimbus Ave.
Beaverton 97005
Tel: (503) 526·6200
FAX: (503) 641·5939

TEXAS

Arrow/Schweber
Electronics
Brake Ctr III. Bldg M1
11500 Metric Boulevard
Suite 160
Austin 78758
Tel; (512) 835·4180
FAX: (512) 832·5921
Arrow/Schweber
Electronics
3220 Commander Drive
Carrollton 75006
Tel: (214) 380·6464
FAX: (214) 248·7208
Arrow/Schweber
Electronics
19416 Park Row
Suite 190
Houston 77084
Tel: (713) 647·6868
FAX: (713) 492·8722
Avnet Computer
4004 Belt line
Suite 200
Dallas 75244
Tel: (800) 426·799

f~~:~~~~r~~~

West
Suite 525 .
Houston 77008
Tel: (800) 426·7999
Hall-Mark Computer

12211 Technology Blvd
Austin 78727
Tel: (800) 409·1483
Hall-Mark Computer

4004 Beltline Road
Suite 200

Dallas 75244
Tel: (800) 409·1483
Hall~Mark Computer
1235 North Loop West
Houston 77008
Tel: (800) 409·1483
Hamilton Hallmark
12211 Technology
Boulevard
Austin 78727
Tel: (512) 258·8848
FAX: (512) 258·3777
Hamilton Hallmark
11420 Page Mill Road
Dalias 75243
Tel: (214) 553·4300
FAX: (214) 553·4395
Hamilton Hallmark
8000 Westglen
Houston 77063
Tel: (713) 781·6100
FAX: (713) 953·8420
Pioneer Standard
18260 Kramer Lane
Austin 78758
Tel: (512) 835·4000
FAX: (512) 835·9829
Pioneer Standard
13765 Beta Road
Dalias 75244
Tel: (214) 263·3168
FAX: (214) 490·6419
Pioneer Standard
10530 Rockley Road
Suite 100
Houston 77099
Tel: (713) 495·4700
FAX: (713) 495·5642
Wyle Electronics
1810 Greenville Ave
Richardson 75081
Tel: (214) 235·9953
FAX: (214) 644·5064
Wyle Electronics
9208 Waterford Center
Blvd
Suite 150
Austin 78750
Tel: (512) 345·8853
FAX: (512) 345·9330
Wyle Electronics
2901 Wilcrest
Suite 120
Houston 77099
Tel: (713) 879·9953
FAX: (713) 879·9953
Zeus Arrow
Electronics
3220 Commander Dr
Carrollton 75006
Tel: (214) 380·4330
FAX: (214) 447·2222

UTAH
Anthem Electronics
1279 West 2200 South
Salt Lake City 84119
Tel: (801) 973·8555
FAX: (801) 973·8909
ArrowlSchwebar
Electronics
1946 West Parkway
Boulevard
Salt Lake City 84119
Tel: (801) 973·6913
FAX: (801) 972·0200

intel®
NORTH AMERICAN DISTRIBUTORS (Cont'd)
Avnet Computer
1100 East 6600 South

~~~~ele~6ThA~~o~~~.ies

ALASKA

ONTARIO

Suite 150

Suite 100

Salt lake City 84121
Tel: (800) 426-7999

Bellevue 98007
Tel: (206) 644-7500

Avnet Computer
1400 W Benson Blvd

Hall-Mark Computer

Wyle Electronics

Arrow/Schwaber
Electronics
36 Antares Drive
Unill00

1100 East 6600 South
Suite 150

15385 NE 90lh SI

Salt Lake City
Tel: (800) 409-1483

Tel: (206) 881-1150
FAX: (206) 881-1567

CANADA

WISCONSIN

ALBERTA

Arrow/Schwaber
Electronics
200 N. Patrick
Suite 100
Brookfield 53045
Tet: (414) 792-0150
FAX: (414) 792-0156

Avne! Computer
1144 29th Avenue NE
Suite 108
Calgary T2E 7Pl
Tel: (800) 387-3406

Hamilton Hallmark
1100 East 6600 South

Suite 120
Salt Lake City 84121
Tel: (801) 266-2022
FAX: (801) 263-0104
Wyle Electronics
1325 West 2200 South
Suite E
West Vaiiey 84119
Tel: (801) 974-9953
FAX: (801) 972-2524
WASHINGTON

AlmacArrow
Electronics
14360 S.E. Easlgale

ii'e~fevue 98007

Tel: (206) 643-9992
FAX: (206) 643-9709

Anthem Electronics
19017 .12Oth Ave N.E.
Suite 102
Bolhell 98011
Tel: (206) 483-1700
FAX: (206) 486-0571
Avnet Computer
8630 154th Ave, NE
Redmond 98052
Tel: (800) 426-7999
Hamilton Hallmark
8630 154th Avenue
Redmond 98052
Tel: (206) 881-6697
FAX: (206) 867-0159

Suite 400

~~~~~~aO~e4~~:~~99

Redmond 98052

Avnet Computer
2440 South 179th St
New Berlin 53416
Tel: (800) 426-7999
Hall-Mark Computer
2440 Soulh 1791h SI
New Berlin 53146
Tel: (BOO) 409-1483
Hamilton Hallmark
2440 Soulh 1791h SI
New Berlin 53146
Tel: (414) 797-7844
FAX: (414) 797-9259
Pionoor Standard
120 Bishops Way
Suite 163
Brookfield 53005
Tel: (414) 780-3600
FAX, (414) 780-3613
WyJe Electronics
150 North Patrick
Building 7, Suite 150
Brookfield 53045
Tel: (414) 879-0434
FAX: (414) 879-0474

Pioneer/Pioneer
560,1212-31 Ave. NE
Calgary T2E 7S8
Tel: (403) 291-1988
FAX: (403) 295-8714
BRITISH COLUMBIA

AlmacArrow
Electronics
8544 Baxter Place
Burnaby V5A 4T8
Tel: (604) 421-2333
FAX: (604) 421-5030
Hamilton Hallmark
8610 Commerce Court
Burnaby V5A 4N6
Tel: (604) 420-4101
FAX: (604) 420-5376
Pioneer/Pioneer
4455 North 6 Road
Rochmond V6V 1P6
Tel: (604) 273-5575
FAX: (604) 273-2413
MANITOBA

Pioneer/Pioneer
540 Marjorie Street
Winnipeg R3H OS9

~:F:(~~~~~l.~g503
FAX: (613) 723-2018

Arrow/Schwaber
Electronics
1093 Meyerside, Unit 2
Mississauga L5T 1M4
Tel: (416) 670-2010
FAX: (416) 670-5863
Avnet Computer
Canada System

Pioneer/Pioneer
155 Colonnade Rd .. S.
Suite 17

~:F{gM~~l.~~40

FAX: (613) 226-6352

QUEBEC

Arrow/Schwaber
Electronics
1100 Street Regis Blvd
Dorval H9P 2T5
Tel: (514) 421-7411
FAX: (514) 421-7430

Gates Arrow
Electronics
500 Soul.

~~fi~~~~~ig?BWd.

5~~b~~·~~~ti~W9Ave
Tel: (418) 871-7500
FAX: (418) 871-6816

Avnet Computer
190 Colonade Road

Avnet Computer
7575 Trans Canada
Suite 601
st. Laurent H4T 1V6
Tel: (800) 265-1135

Mississuaga L5T 2L 1
Tel: (800) 387-3406

~:F(~30~~~l.~~06
Canada System
Engineering Group
151 Superior Boulevard
Mississuaga L5T 2L 1
Tel: (800) 387-3406
Hamilton Hallmark
151 Superior Blvd.,
Unit 1-6
Mississauga L5T 2L 1
Tel: (416) 564-6060
FAX: (416) 564-6033
Hamilton Hallmark
190 Colonade Road
Nepean K2E 7J5
Tel: (613) 226-1700
FAX: (613) 226-1184
Pioneer/Pioneer
341 5 American Drive
Mississauga L4V 1T6
Tel: (416) 507-2600
FAX: (416) 507-2831

Hamilton Hallmark
7575 Transcanada Hwy
Suite 600
Sireet Laurent H4T 2V6
Tel: (514) 335-1000
FAX: (514) 335-2481
Pioneer/Pioneer
520 McCaffrey
Street Laurent H4T lNt
Tel: (514) 737-9700
FAX: (514) 737-5212

NORTH AMERICAN SERVICE OFFICES
Computervision
Intel Corporation's North American Preferred Service Provider
Central Dispatch: 1-800-876-SERV (1-800-876-7378)

ALABAMA

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Huntsville

ALASKA
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NORTH CAROLINA

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WASHINGTON D.C:

CANADA
Calgary
Edmonton
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Halifax
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Montreal
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Toronto
Vancouver, BC·
Winnipeg
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St.John's

9 781555 122560



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