IEEE Std 1800™ 2012 (Revision Of 1800 2009) Standard For SystemVerilog—Unified Hardware Design, Specification, And System Verilog Language Reference Manual
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- IEEE Std 1800-2012 Front cover
- Title page
- Notice to users
- Participants
- Introduction
- Contents
- Part One: Design and Verification Constructs
- Important notice
- 1. Overview
- 2. Normative references
- 3. Design and verification building blocks
- 4. Scheduling semantics
- 4.1 General
- 4.2 Execution of a hardware model and its verification environment
- 4.3 Event simulation
- 4.4 Stratified event scheduler
- 4.5 SystemVerilog simulation reference algorithm
- 4.6 Determinism
- 4.7 Nondeterminism
- 4.8 Race conditions
- 4.9 Scheduling implication of assignments
- 4.10 PLI callback control points
- 5. Lexical conventions
- 6. Data types
- 6.1 General
- 6.2 Data types and data objects
- 6.3 Value set
- 6.4 Singular and aggregate types
- 6.5 Nets and variables
- 6.6 Net types
- 6.7 Net declarations
- 6.8 Variable declarations
- 6.9 Vector declarations
- 6.10 Implicit declarations
- 6.11 Integer data types
- 6.12 Real, shortreal, and realtime data types
- 6.13 Void data type
- 6.14 Chandle data type
- 6.15 Class
- 6.16 String data type
- 6.17 Event data type
- 6.18 User-defined types
- 6.19 Enumerations
- 6.20 Constants
- 6.21 Scope and lifetime
- 6.22 Type compatibility
- 6.23 Type operator
- 6.24 Casting
- 6.25 Parameterized data types
- 7. Aggregate data types
- 8. Classes
- 8.1 General
- 8.2 Overview
- 8.3 Syntax
- 8.4 Objects (class instance)
- 8.5 Object properties and object parameter data
- 8.6 Object methods
- 8.7 Constructors
- 8.8 Typed constructor calls
- 8.9 Static class properties
- 8.10 Static methods
- 8.11 This
- 8.12 Assignment, renaming, and copying
- 8.13 Inheritance and subclasses
- 8.14 Overridden members
- 8.15 Super
- 8.16 Casting
- 8.17 Chaining constructors
- 8.18 Data hiding and encapsulation
- 8.19 Constant class properties
- 8.20 Virtual methods
- 8.21 Abstract classes and pure virtual methods
- 8.22 Polymorphism: dynamic method lookup
- 8.23 Class scope resolution operator ::
- 8.24 Out-of-block declarations
- 8.25 Parameterized classes
- 8.26 Interface classes
- 8.27 Typedef class
- 8.28 Classes and structures
- 8.29 Memory management
- 9. Processes
- 10. Assignment statements
- 10.1 General
- 10.2 Overview
- 10.3 Continuous assignments
- 10.4 Procedural assignments
- 10.5 Variable declaration assignment (variable initialization)
- 10.6 Procedural continuous assignments
- 10.7 Assignment extension and truncation
- 10.8 Assignment-like contexts
- 10.9 Assignment patterns
- 10.10 Unpacked array concatenation
- 10.11 Net aliasing
- 11. Operators and expressions
- 11.1 General
- 11.2 Overview
- 11.3 Operators
- 11.4 Operator descriptions
- 11.5 Operands
- 11.6 Expression bit lengths
- 11.7 Signed expressions
- 11.8 Expression evaluation rules
- 11.9 Tagged union expressions and member access
- 11.10 String literal expressions
- 11.11 Operator overloading
- 11.12 Minimum, typical, and maximum delay expressions
- 11.13 Let construct
- 12. Procedural programming statements
- 13. Tasks and functions (subroutines)
- 14. Clocking blocks
- 14.1 General
- 14.2 Overview
- 14.3 Clocking block declaration
- 14.4 Input and output skews
- 14.5 Hierarchical expressions
- 14.6 Signals in multiple clocking blocks
- 14.7 Clocking block scope and lifetime
- 14.8 Multiple clocking blocks example
- 14.9 Interfaces and clocking blocks
- 14.10 Clocking block events
- 14.11 Cycle delay: ##
- 14.12 Default clocking
- 14.13 Input sampling
- 14.14 Global clocking
- 14.15 Synchronous events
- 14.16 Synchronous drives
- 15. Interprocess synchronization and communication
- 16. Assertions
- 16.1 General
- 16.2 Overview
- 16.3 Immediate assertions
- 16.4 Deferred assertions
- 16.5 Concurrent assertions overview
- 16.6 Boolean expressions
- 16.7 Sequences
- 16.8 Declaring sequences
- 16.9 Sequence operations
- 16.10 Local variables
- 16.11 Calling subroutines on match of a sequence
- 16.12 Declaring properties
- 16.13 Multiclock support
- 16.14 Concurrent assertions
- 16.15 Disable iff resolution
- 16.16 Clock resolution
- 16.17 Expect statement
- 16.18 Clocking blocks and concurrent assertions
- 17. Checkers
- 18. Constrained random value generation
- 18.1 General
- 18.2 Overview
- 18.3 Concepts and usage
- 18.4 Random variables
- 18.5 Constraint blocks
- 18.6 Randomization methods
- 18.7 In-line constraints—randomize() with
- 18.8 Disabling random variables with rand_mode()
- 18.9 Controlling constraints with constraint_mode()
- 18.10 Dynamic constraint modification
- 18.11 In-line random variable control
- 18.12 Randomization of scope variables—std::randomize()
- 18.13 Random number system functions and methods
- 18.14 Random stability
- 18.15 Manually seeding randomize
- 18.16 Random weighted case—randcase
- 18.17 Random sequence generation—randsequence
- 19. Functional coverage
- 19.1 General
- 19.2 Overview
- 19.3 Defining the coverage model: covergroup
- 19.4 Using covergroup in classes
- 19.5 Defining coverage points
- 19.6 Defining cross coverage
- 19.7 Specifying coverage options
- 19.8 Predefined coverage methods
- 19.9 Predefined coverage system tasks and system functions
- 19.10 Organization of option and type_option members
- 19.11 Coverage computation
- 20. Utility system tasks and system functions
- 20.1 General
- 20.2 Simulation control system tasks
- 20.3 Simulation time system functions
- 20.4 Timescale system tasks
- 20.5 Conversion functions
- 20.6 Data query functions
- 20.7 Array querying functions
- 20.8 Math functions
- 20.9 Bit vector system functions
- 20.10 Severity tasks
- 20.11 Elaboration system tasks
- 20.12 Assertion control system tasks
- 20.13 Sampled value system functions
- 20.14 Coverage system functions
- 20.15 Probabilistic distribution functions
- 20.16 Stochastic analysis tasks and functions
- 20.17 Programmable logic array modeling system tasks
- 20.18 Miscellaneous tasks and functions
- 21. Input/output system tasks and system functions
- 22. Compiler directives
- 22.1 General
- 22.2 Overview
- 22.3 `resetall
- 22.4 `include
- 22.5 `define, `undef, and `undefineall
- 22.6 `ifdef, `else, `elsif, `endif, `ifndef
- 22.7 `timescale
- 22.8 `default_nettype
- 22.9 `unconnected_drive and `nounconnected_drive
- 22.10 `celldefine and `endcelldefine
- 22.11 `pragma
- 22.12 `line
- 22.13 `__FILE__ and `__LINE__
- 22.14 `begin_keywords, `end_keywords
- Part Two: Hierarchy Constructs
- 23. Modules and hierarchy
- 23.1 General
- 23.2 Module definitions
- 23.3 Module instances (hierarchy)
- 23.4 Nested modules
- 23.5 Extern modules
- 23.6 Hierarchical names
- 23.7 Member selects and hierarchical names
- 23.8 Upwards name referencing
- 23.9 Scope rules
- 23.10 Overriding module parameters
- 23.11 Binding auxiliary code to scopes or instances
- 24. Programs
- 25. Interfaces
- 26. Packages
- 27. Generate constructs
- 28. Gate-level and switch-level modeling
- 28.1 General
- 28.2 Overview
- 28.3 Gate and switch declaration syntax
- 28.4 and, nand, nor, or, xor, and xnor gates
- 28.5 buf and not gates
- 28.6 bufif1, bufif0, notif1, and notif0 gates
- 28.7 MOS switches
- 28.8 Bidirectional pass switches
- 28.9 CMOS switches
- 28.10 pullup and pulldown sources
- 28.11 Logic strength modeling
- 28.12 Strengths and values of combined signals
- 28.13 Strength reduction by nonresistive devices
- 28.14 Strength reduction by resistive devices
- 28.15 Strengths of net types
- 28.16 Gate and net delays
- 29. User-defined primitives
- 30. Specify blocks
- 31. Timing checks
- 31.1 General
- 31.2 Overview
- 31.3 Timing checks using a stability window
- 31.4 Timing checks for clock and control signals
- 31.5 Edge-control specifiers
- 31.6 Notifiers: user-defined responses to timing violations
- 31.7 Enabling timing checks with conditioned events
- 31.8 Vector signals in timing checks
- 31.9 Negative timing checks
- 32. Backannotation using the standard delay format
- 33. Configuring the contents of a design
- 34. Protected envelopes
- Part Three: Application Programming Interfaces
- 35. Direct programming interface
- 36. Programming language interface (PLI/VPI) overview
- 36.1 General
- 36.2 PLI purpose and history
- 36.3 User-defined system task and system function names
- 36.4 User-defined system task and system function arguments
- 36.5 User-defined system task and system function types
- 36.6 User-supplied PLI applications
- 36.7 PLI include files
- 36.8 VPI sizetf, compiletf, and calltf routines
- 36.9 PLI mechanism
- 36.10 VPI access to SystemVerilog objects and simulation objects
- 36.11 List of VPI routines by functional category
- 36.12 VPI backwards compatibility features and limitations
- 37. VPI object model diagrams
- 37.1 General
- 37.2 VPI Handles
- 37.3 VPI object classifications
- 37.4 Key to data model diagrams
- 37.5 Module
- 37.6 Interface
- 37.7 Modport
- 37.8 Interface task or function declaration
- 37.9 Program
- 37.10 Instance
- 37.11 Instance arrays
- 37.12 Scope
- 37.13 IO declaration
- 37.14 Ports
- 37.15 Reference objects
- 37.16 Nets
- 37.17 Variables
- 37.18 Packed array variables
- 37.19 Variable select
- 37.20 Memory
- 37.21 Variable drivers and loads
- 37.22 Object Range
- 37.23 Typespec
- 37.24 Structures and unions
- 37.25 Named events
- 37.26 Parameter, spec param, def param, param assign
- 37.27 Virtual interface
- 37.28 Interface typespec
- 37.29 Class definition
- 37.30 Class typespec
- 37.31 Class variables and class objects
- 37.32 Constraint, constraint ordering, distribution
- 37.33 Primitive, prim term
- 37.34 UDP
- 37.35 Intermodule path
- 37.36 Constraint expression
- 37.37 Module path, path term
- 37.38 Timing check
- 37.39 Task and function declaration
- 37.40 Task and function call
- 37.41 Frames
- 37.42 Threads
- 37.43 Delay terminals
- 37.44 Net drivers and loads
- 37.45 Continuous assignment
- 37.46 Clocking block
- 37.47 Assertion
- 37.48 Concurrent assertions
- 37.49 Property declaration
- 37.50 Property specification
- 37.51 Sequence declaration
- 37.52 Sequence expression
- 37.53 Immediate assertions
- 37.54 Multiclock sequence expression
- 37.55 Let
- 37.56 Simple expressions
- 37.57 Expressions
- 37.58 Atomic statement
- 37.59 Dynamic prefixing
- 37.60 Event statement
- 37.61 Process
- 37.62 Assignment
- 37.63 Event control
- 37.64 While, repeat
- 37.65 Waits
- 37.66 Delay control
- 37.67 Repeat control
- 37.68 Forever
- 37.69 If, if–else
- 37.70 Case, pattern
- 37.71 Expect
- 37.72 For
- 37.73 Do-while, foreach
- 37.74 Alias statement
- 37.75 Disables
- 37.76 Return statement
- 37.77 Assign statement, deassign, force, release
- 37.78 Callback
- 37.79 Time queue
- 37.80 Active time format
- 37.81 Attribute
- 37.82 Iterator
- 37.83 Generates
- 38. VPI routine definitions
- 38.1 General
- 38.2 vpi_chk_error()
- 38.3 vpi_compare_objects()
- 38.4 vpi_control()
- 38.5 vpi_flush()
- 38.6 vpi_get()
- 38.7 vpi_get64()
- 38.8 vpi_get_cb_info()
- 38.9 vpi_get_data()
- 38.10 vpi_get_delays()
- 38.11 vpi_get_str()
- 38.12 vpi_get_systf_info()
- 38.13 vpi_get_time()
- 38.14 vpi_get_userdata()
- 38.15 vpi_get_value()
- 38.16 vpi_get_value_array()
- 38.17 vpi_get_vlog_info()
- 38.18 vpi_handle()
- 38.19 vpi_handle_by_index()
- 38.20 vpi_handle_by_multi_index()
- 38.21 vpi_handle_by_name()
- 38.22 vpi_handle_multi()
- 38.23 vpi_iterate()
- 38.24 vpi_mcd_close()
- 38.25 vpi_mcd_flush()
- 38.26 vpi_mcd_name()
- 38.27 vpi_mcd_open()
- 38.28 vpi_mcd_printf()
- 38.29 vpi_mcd_vprintf()
- 38.30 vpi_printf()
- 38.31 vpi_put_data()
- 38.32 vpi_put_delays()
- 38.33 vpi_put_userdata()
- 38.34 vpi_put_value()
- 38.35 vpi_put_value_array()
- 38.36 vpi_register_cb()
- 38.37 vpi_register_systf()
- 38.38 vpi_release_handle()
- 38.39 vpi_remove_cb()
- 38.40 vpi_scan()
- 38.41 vpi_vprintf()
- 39. Assertion API
- 40. Code coverage control and API
- 41. Data read API
- Part Four: Annexes
- Annex A (normative) Formal syntax
- Annex B (normative) Keywords
- Annex C (normative) Deprecation
- Annex D (informative) Optional system tasks and system functions
- Annex E (informative) Optional compiler directives
- Annex F (normative) Formal semantics of concurrent assertions
- Annex G (normative) Std package
- Annex H (normative) DPI C layer
- Annex I (normative) svdpi.h
- Annex J (normative) Inclusion of foreign language code
- Annex K (normative) vpi_user.h
- Annex L (normative) vpi_compatibility.h
- Annex M (normative) sv_vpi_user.h
- Annex N (normative) Algorithm for probabilistic distribution functions
- Annex O (informative) Encryption/decryption flow
- Annex P (informative) Glossary
- Annex Q (informative) Bibliography