229 2116 2_360_30_FE_Handbook 2 360 30 FE Handbook
229-2116-2_360_30_FE_Handbook 229-2116-2_360_30_FE_Handbook
User Manual: 229-2116-2_360_30_FE_Handbook
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Field Engineering
Handbook
System/360 Model 30
'Ii' 10)0 'IY.i'
L!J~~
(i)
Field Engineering Handbook
System/360 Model 30
Address comments concerning the contents of this publication to:
IBM Corporation, FE Technical Operations, Department 793,
Endicott, New York 13760
CONTENTS
M2I GATE AND SELECTION LOGIC.
DIODE PACK - PIN 2391181. . .
DIODE LAYOUT - 32K ARRANGEMENT
ORIENTATION OF DIODE PACK (BY DIODE iI).
POWER RESISTOR LOCA TION. . . . . .
ARRAY LAYOUT . . . . . . . . . . .
MAIN ADDRESS REGISTER LAYOUT (M&N)
PLUG CHART - B1 BOARD . .
PLUG CHART - B2 BOARD . . .
M2 MAIN STORAGE ADDRESSING . .
ROS ADDRESSING BLOCK DIAGRAM
ROS ADDRESSING - CARD POSITIONS
ROS PARITY CHECK BITS
LOCAL STORAGE - CPU . . . . .
FORMA T FOR K ADDRESSABLE BYTES
TRACK FORMATS. . . . . . . . . . .
BETA GAP BIT CONFIGURATION. . . . .
HA AND ALPHA GAP BIT CONFIGURATION
PROGRAM STATUS WORD. .
CHANNEL STATUS WORD. .
TRAPS IN PRIORITY ORDER.
ROS ADDRESS . . . . . .
READ ONLY STORAGE CONTROL.
S-Reg., MC-Reg., H-Reg., ALU Controls
Micro-Word Format. . . . .
ROS Control Field Description.
ROS CONTROL FIELD CHART. .
SYSTEM/360 MOD 30 DATA FLOW
MULTIPLEX CHANNEL MICRO-PROGRAM
DATA FLOW/TIMING . . . . . .
ADDRESSING OF UCW - I/O FORMAT
UNIT CONTROL WORD. . . . . .
MULTIPLEX CHANNEL CONTROL .
STATUS-IN AND SERVICE-IN BRANCHES
SELECTOR CHANNEL CONTROL.
CPU CHANNEL LOGOUT . . .
MPX AND SX MICRO P!l.OGRAM .
1050 INTERFACE REGISTERS . .
REGISTER DISPLAY AND FUNCTION
IBM 1407 CONSOLE INQUIRY STATION
AND IBM 1447 CONSOLE MODELS 2 & 3
1401 OPERATION CODES.
1400 d MODIFIERS. . . . .
d Characters For Branch .
d Characters For Branch If
Wordmark Or Zone . . .
d Characters For Form Control
BCD TO CM6 CONVERSION - 1401 CODE TO
SYSTEM/360 CODE . . . . . . .
SUGGESTED STANDARD ADDRESSES . . .
I
2
2
3
3
4
5
6
10
10
12
13
13
14
15
16
17
18
19
19
20
25
26
26
27
28
29
30
31
31
32
32
35
36
37
38
40
41
42
42
43
43
44
45
CONTENTS
1400 COMPATIBILITY - PROGRAMMED AND
ERROR STOPS. . • • • • • • • • • . •
BIT ASSIGNMENTS FOR BYTES IN 1401 BUMP
LOCAL STORAGE - 1401 MODE . • • . . .
K ADDRESSABLE BYTE UTILIZATION • • .
DEFINITIONS OF ALD PAGE NUMBER PREFIXES.
1620 OP CODES • • • • • . • • • •
1620 PROGRAMMED AND ERROR STOPS.
ROS CONTROL FIELD CHANGES.
FUNCTIONAL DESIGNATIONS.
ROUTINE POINTERS • . .
INITIALIZATION MESSAGES .
DISK FORMAT CHANGES. • • • • • . . • • .
NUMERIC INPUT/OUTPUT CODES AND GRAPHICS. • •
ALPHAMERIC INPUT/OUTPUT CODES AND GRAPHICS.
ADDRESS CONVERSION .
ADDITIVE CARD CODE . • . . . . • • • • •
ROS PAGE ASSIGNMENTS • • • • • • • . • •
1400 COMPATIBILITY - ROS PAGE ASSIGNMENTS.
1620 COMPATIBILITY - ROS PAGE ASSIGNMENTS.
ROS FEATURE ASSIGNMENTS. • . . .
COMBINATION VERSION ASSIGNMENTS.
ALD VERSION ASSIGNMENTS .
R PQ VERSION ASSIGNMENTS. • • •
RPQ COMBINED VERSIONS. . . . •
SYSTEM/360 EBCDIC HEXIDECIMAL .
2821 HEX TO BCD TRANSLATION • •
2821 PRINT HAMMER DRIVER LOCATION.
INTERFACE CONNECTOR CHART . • .
2030 BOARD LOCATION . • • • • • .
SPECIFICATION OF SLT MODULES FOR
SYSTEM/360. • . • • • •
DIAGNOSTICS . • • . . • . . • . •
SENSE SWITCHES DMA4. . • • . .
SWITCH SETTINGS FOR CONSOLE OVERLAY DMA4.
ERROR MESSAGES DMA4 .
SYSTEM/360 DIAGNOSTICS.
1401 COMPATIBILITY.
1620 COMPATIBILITY. . .
MISCELLANEOUS . . . .
OPERATING PROCEDURE FOR SELECTOR CHANNEL
FLT'S. • • . • • . • • . .
OPERATOR'S FLOW - CHART A. . • . .
OPERATOR'S FLOW - CHART B. . • . •
DMA4 RESTART PROCEDURES - CHART C
INITIALIZE OUTPUT MESSAGE OF DMA4
INDEX. . . . . . . . . . . . . . . .
46
50
51
51
52
53
55
59
60
61
62
62
63
64
65
66
67
67
67
68
69
70
70
71
72
73
74
75
76
77
78
79
79
80
81
83
83
83
84
86
87
88
89
91
S32EF
Diodes
To 15 other Write Gates
To 15 other Write Gates
------4
DIODE PACK - PiN 2391181
Schematic - Each diode pack contains 4 diodes connected as follows:
Pin 6
Pin 2
---,--"--O--;--,----~-----------"'"-~-t_,_r_/ 98-2-B-7 \ A -
Pin 4,,-
I
I
I
:
I
Pin 1
L---I*--t-'I-o/~98-1-B-ll \AI:
L _________
~
The example shown is taken from MM870 X-Drive Diode Pin # 1.
DIODE LAYOUT - 32K ARRANGEMENT
1 ",:,:,:w/local storage :-:--34
W
/0
Ioea I storage
e
32
34
32K
w/o local storage
99-=-w/local storage':":132
2
8/360 MODEL 30
SLT Card Side
ORIENTATION OF DIODE PACK (BY DIODE #)
SIDE A
SIDE B
SIDE C
SIDE D
Count
Towards
Large
Card
Count
Top To
Bottom
(Evens)
Count
Towards
Large
Card
Count
Top To
Bottom
(Odds)
Diode Card 1
8/16/32K
99-132
36-98
1-34
35-97
Diode Card 1
32K W/O Local
97-128
34-96
1-32
33-95
Diode Card 2
8/16K
35-68
None
1-34
None
Diode Card 2
32K
99-132
36-98
1-34
35-97
Diode Card 2
32K W/O Local
97-128
34-96
1-32
33-95
POWER RESISTOR LOCATION
TOP OF FRAME
A
C
a Bit
1 Bit
2 Bit
6 Bit a-16K
7 Bit
P Bit
a Bit
1 Bit
2 Bit 16-32K
3 Bit
4 Bit
3 Bit
4 Bit a-16K
5 Bit
5 Bit
6 Bit
16-32K
7 Bit
P Bit
Y Read
Y Write
X Read 8 24K
X Write 16 32K
I
N
H
I
B
I
T
R
E
S
I
S
T
0
R
S
X-V
DRIVE
BOHOM OF FRAME
S/360 MODEL 30
3
.\RRAY LAYOUT
Y-Winding Goes
Through All 18 Planes
One X-Winding
(Second 16K)
Diode Cord N
locotlon
0
X lines
®
Side View
Printed X-Retum Wires for
4
8/360 MODEL 30
•
MAIN STORAGE ADDRESS REGISTER LAYOUT (M & N)
\
MAIN STORAGE ADDRESS REGISTER
8 14 12 1 1 8
4
2
1
1 1 1 1
P I 01112134
5
6
7
1 1 1
I
I
8 4
p
10
12
1
1
1
8
4
2
112 3 415
6
1
MS(
I
7 LS
)1
Sel ects A or B
Sense Inhibit
Selects one of 64 X drive
lines for each 16K
Selects one of 128 Y drive lines
T2" 0 - 8K Selection
T 28 - 16K
1 2" 16 - 24K
1224-32K
o Lower 32K
o Upper 32K
S/360 MODEL 30
5
NOTES: 1. BJB2 and BlA5 Sockets have 5803577 Installed if Memory is Highest Addressable CSU, Otherwise these Sockets are used for Intermemory Coble Chaining.
2. *Denotes Cable 5802515 Installed on 8, 16,32K, or 1st 32K But Not 2nd 32K.
A
BCD
E
F
G
M
N
o
I-
,-- ,--
EC
TERM
10
oc
EC
to
CPU
Dolo
r-;- Ie'
U
M
P
E
.
Store
REC
&
PWP
D
E
L
A
y
I-;
A
B
L
E
,
II
,-- ,---- ,-- -
N
V
T
L
I
N
E
,
TIM
OUT
DV'
r-::N
D
I
N
G
S
~;= ~;=~
EC
to
CPU
(TIM)
T
I
M
I
N
G
~ ~
0'
EC
TO
2ND
~
I
I
M
I
N
G
~
Bl to B2
XOVR CABLE
-
D
E
L
A
D
E
L
A
Y
Y
L
I
N
E
L
I
N
E
-
II
T
I
M
I
N
G
SA
OUT
DV'
II
S-Z
0
BIT
0-16
II
r - ,---- ,--- r - r S-Z
1
BIT
0-16
~
S-Z
6
BlT
0-16
S-Z
7
BIT
0-J6
S-Z
P
BIT
0-16
,---- S-Z
0
BIT
16-32
II
S-Z
1
BIT
J6-32
,---S-Z
2
BIT
16-32
II
I
,-- r - ,---- ,-- S-Z
3
BIT
J6-32
S-Z
4
BIT
16-32
Z
D S
E T
C ,
00
~
DB
E E
TIM
REC
&
PW,
&
V
0
L
T
A
G
E
,
E
G
V
,
E
G
~
line
5NS
Topes
~~~~
~~~
:=~~;=~~ ~~
S-Z
S-Z
S-Z
Sense
Sense Sense Sense
S-Z
S-Z
Sense
Sense
S-Z
S-Z
Gate
I
3
BIT
0-16
4
BIT
0-16
5
BIT
0-16
r;I
M
I
N
G
S-Z
2
BIT
0-J6
V
-
B1 to B2
XOVR CABLE
' - - '-------
II
-Z
BITS
0,1,2
0-8K
-Z
BITS
6,1,P
0-8K
-Z
BITS
3,4,5
8-16
-Z
BITS
0,1,
16-24
~
~ 7e:: ~
Sense
-Z
BITS
3,4,5
0-8K
-Z
BITS
0, J,2
8-16K
-
'-------
II
-Z
BITS
6,7,P
8-16K
-
-Z
BITS
3,4,5
16-24
~
-Z
BITS
6,1,P
16-24
-Z
BITS
3,4,5
24-32
5
BIT
16-32
6
BIT
16-32
7
BIT
16-32
P
BIT
16-32
t: ~
-Z
BITS
0,1,2
24-32
K
-Z
BITS
6,7,P
24-32
K
-~
II
D'
0-16
N
V
T
,
~ ~
DR
16-32
~
'-------
'-------
II
-
'-------
.':=--::
I
NOTES: 1. B2B2 Socket hos 5803577 Installed if Memory is Highest Addressable CSU, Otherwise This Socket is Used for Inlermemory Cable Chaining.
2. These Sockets Not Available for Cards.
A
I
G
B2 10 Bl
XOVR CA8LE
II
B2 to Bl
XOVR CABLE
M
II
, - - ,-- , - - r - r - r - r - r - r TERM
y
EC
to
CPU
(Addr)
roo-
X
DVR
0-16
oc
EC
Aod
PWR
to-Addr
REC
Aod
PWR
'----
I
Y
DVR
DVR
0
N
T
R
~
L
DVR
0
X
DVR
0-16
I
N
V
T
R
y
DVR
y
DVR
II
-
B
X
CTL
32K
0
A
y
ro-
'I
~
R
D
X
A
R
R
16K
D
I
D
I
0
0
D
E
D
E
B
B
0
A
0
A
R
D
R
D
'2
8K
A
Y
cn
'2
16K
R
R
A
y
II
'2
':::::: '== =-: '== <::--- '--
II
y
y
DVR
DVR
X
DVR
16-32
~
~
II
~
0
A
Note
~ .=;==~
r-y
y
DVR
DVR
R
D
A
R
R
A
y
'--
I
U
M
P
U
M
P
0
B
r;-
~
B
D
I
D
E
Note
~~
II
,-- r-- r - r - - r -
A
R
R
A
D
E
;::::;:=;==~;:=
r~
A
D
I
0
X
DVR
0-16
r--- , - -
v
Q
C
to
I
N
V
T
R
II
-
Y
2ND
;==;== ;::::
Addr
REC
X
DVR
0-16
N
cn
;:::: ;::::
X
DVR
16-32
D
V
R
'2
5
32K
With
Bump
U
R
C
E
5
Q
w/o Note
Bump
#2
'-- '--
II
~
~'--~
II
~
I
NOTES
S/360 MODEL 30
(
MAIN STORAGE ADDRESSING
2 MICRO-SECOND MEMORY
,-------1f
N REG. BITS
4,5,6, & 7
,----------A---
--i'-,------
,f-'
!:?::@8tI
N REG. BITS 2 & 3
WRITE 1
NOT M REG. 1 BIT
+L
GATE
TX
PHASE READ
16
(MS~51)
DECODE
y
GATE
DEC.
(MS)
(031)
LINES
+L GATE TX
16 DECODE liNES
4 SWITCHES
~
M REG 6 & 7
N REGO& 1
~""
~."
y
GATE
TRANS
MREG
2 BIT CONT.
(MS151)
y
8 DECODES
FOR 32K
Y
DRIVER
DEC.
R
(-L)
(1'*321<)
READ OR WRITE
W
(8+24K)
(MS 421
431)
(MS 401
128 LINES
128 LINES
411
Y
DRIVER
DEC.
8 DECODES
FOR 32K
f---'-----------i
16+32K)
READ OR WRITE
(8-24K)
W
DEC.
(MS
041)
(MS 151)
W
R
(-L)
Y
DRIVER
DEC.
(8+24K)
+~V
(1 '*32 K)
y
GATE
2 81T CONT.
R
y
GATE
TRANS
(MS 091)
MREG.
(MS 101)
MREG
BITS 3,4, &5
+L
GATE
TX
16
DECODE
LINES
+l GATE TX
16 DECODE LINES
:r
T
J
A~~~,~~~~~
GATE TERM
X DRIVER
DECODE
PHASE REV.
X GATE DECODE
BIT POSITION
DECIMAL
VALUE
OF BIT
M-REGISTER
S/360 MODEL 30
N-REGISTER
9
\
\
ROS ADDRESSING BLOCK DIAGRAM
3969-8
4001-0
Drive Words
lst BOARD
42nd BOARD
3937-6
EVEN
Bd.
No.
Hex
Pos.
0 - 0
000
2
018
4
030
6
048
IE- 065064 033 032 001 000
lElE-
IElElE-
'"~
;;:
i:5=
,,=tJ=
......
IflElE-
0
O
0
'"
If-
O
IE-
'"
16 LINES
T PULSES
!flE3949-8
3967-6
If-
095,094 063,062
«
Ucc«
Val
Ua:r.<{
c:Q«
Uco«
I
~ltH"'ltHgritl~N *Itl~rl~ gl+~I-
001 11
019
031
049
-
.~
Group
Decod.
A
r--
~
3 3
~
J
A
~
~
W31
3
4
5
6
7
1
2
1
Modul. 2
j C Decodej B Decode
S.1.
IE---- W - Reg
~I~ ~I~I~I~ :q
CNP, PS, PC CN = AOO
CNP, PS, PC
QB871
All Bits but PE PC
QB871
CN = 15FC
ci.
All Bits but PS PC
oS QB871
QB871
"" 0
Me;
CNP, PS, PC CN=1500
CNP, PS, PC
QB871
MPX Diag.
QB881
MPX Diag., w/Loop (80 in G)
QB881
1401 Soft Stop
QE691
IPL from 1402 1401 Mode
QE521
IPL from 1442 1401 Mode
QE521
IPL from 28xx 1401 Mode
QE521
1401 Start Reset
QE631
Micro Diagnostics
"
NOTE: ROS addresses can change depending upon the E. C. Level
of CCROS.
S/360 MODEL 30
19
READ ONLY STORAGE CONTROL
Field
Hex
Mnemonic
Old Form
Operation
0-5
CN
Shown in Hex on Right Side of Line 7 in the CLD Box.
Sets POSition 0 through 5 of the X-Register for
Next Address.
0-3
CH
Set 6th
Position
Shown on Left Side of Line 7 in the CLD Box.
Set X-6 to ZERO
Set X-6 to ONE
Set X-6 to the Condition of R-Register Position 0
Set X-6 to ONE, if the V-Register Positions 6 and 7
are ZERO
Status in (I/O)
OP in (I/O)
Set X-6 to ONE: if there is a Carry Out of ALU
Position 0
of
RO
VZ
RO
V=OO
8T
OP
AC
8TI
OPI
AC
80
81
82
84
86
80
81
82
84
86
GO
G2
G4
G6
GO
G2
G4
G6
X-Register
9
A
C
D
E
F
0-3
CL
Set 7th
Position
CAhh_W
W=CA
AI
8VI
R=VDD
AI
8VI
RVDD
IBC
IBC
Z=O
G7
83
85
87
Gl
G3
G5
INTR
Z=O
G7
83
85
87
WRITE
WRITE
STORE
STORE
IJ_MN
LJ
UV_MN
UV
of
X-Register
A
B
C
D
F
0-2
CM
Storage
Control
0-1
CU
Storage
Selection
20
G1
G3
G5
INTR
T_MN
T
'aa
K
YP
GUV
M8
L8
MPX
MEM
CPU
UCW
S/360 MODEL 30
}
Set X-6 to ONE, if the Tested Position of the
S-or G-Register is Equal to ONE
Shown on Left Side of Line 7 in the CLD Box-Example; CH, CL
Set X-7 to ZERO
Set X-7 to ONE
Set Value of CA Field into W-Register, Set X-7 to
ONE. bh is the Hex Value of the CA Field and AA
Field
Address in (I/O)Address)
Service in (I/O)
Set X-7 to ONE if the R-Register Contains Valid
Decimal Digits
Set X-7 to ONE if there is a Carry Out of ALU
Position One
Set X-7 to ONE if the Z-Bus (Bits 0-7) is ZERO
}
Set X-7 to ONE, if the Tested Position of the
S-or G-Register is Equal to ONE
Test for any Interrupt, Set X-7 to ONE if there is a
Interrupt
Shown on Left Side of Line 4 in the CLD Box
Write the Data in the R-Register into the Storage
Position Addressed by the M-and N-Registers
No Mnemonic-Compute Cycle, Storage not Used
Write NEW R-Register Data into the Storage Position Addressed by the M-and N-Registers
Set the M-and N-Registers to the Address in the land d-Registers and Read from Storage at that Address
Set the M-and N-Registers to the Address in the Uand V-Registers and Read from Storage at that Address
Set the N-Registers to the Address in the T-Register
and Read from Storage at that Address
Set the N-Register using the CK Field (Note 1)
Dummy Symbol-No Action or Can be Used in a diagnostic Area. (Old From was a Selector Channel
Code).
Shown on Right Side of Line 4 in the CLD Box
Addressing MAIN Storage
Addressing Auxiliary storage-LOCAL Store Section
Addressing Auxiliary storage-Multiplexor UCW Sect.
READ ONLY STORAGE CONTROL
(continued)
Field
Hex
0-1
CO
Mnemonic
Old Form
M/LS
M, C
GR
Use GR
FWX_WX
W=K
WX=FWX
Operation
Addressing MAIN Storage or LOCAL Store Section,
Depending on the OP Code-RR Format Selects LS
In 1400 Mode this Selects the Local Storage Area for
NPL Area
Storage
Selection
(Cont'd)
0-1
Alternate
CU
0-3
CA
A-Register
Source
Control
FT
TT
YA
Shown on Right Side of Line 4 in the CLD Box
No Action
Use the GR-Register in the Selector Channel in Place
of the R-Register for Storage Input and OUtput
Set the W-Register to the Hex Value of the CK Field
Set the W-and X-Registers to the Address in the
Multiplexor Back- Up Registers (FW and FX)
Shown on Left Side of Line 3 in the CLD Box
Multiplexor Channel Tags in
1050 Tags in
Dwnmy Symbol-No Action or Can be Used in a Diagnostic Area
Dummy Symbol-No Action or Cr..n be Used in a Diagnostic Area
Gate the S-Register to the A-Register Via the A-Bus
Gate the H-Register to the A-Register Via the A-Bus
Multiplexor Channel Bus In
FT
TT
YB
H
FI
R
FI
R
A
B
C
D
L
D
L
G
T
V
G
T
V
U
D
}
Gate the - Register to the A - Register Via the
A-Bus
E
0-3
Alternate
CA
Activated
by "AA"=l
FG
FG
MC
MC
YC
Q
Q
JI
Tl
JI
TI
Shown on Line 4 of the CLD Box
Gate the F-Register to the A-Register Via A-Bus
(External Interrupts).
Gate the F-and G-Switches to the A-Register Via the
A-Bus
Gate the Machine Check Register to the A-Register
Via the A-Bus
Dummy Symbol-No Action or Can be Used in the
Diagnostic Area
Gate the C-Register to the A-Register Via the A-Bus
(Interval Timer)
Gate the Q-Register to the A-Register Via the A-Bus
(Protect Storage)
Direct Data Channel Bus In
1050 Bus In
YD
YE
YF
YG
GR
GR
D
KZ GS
GS
E
KY GT
GT
KW GJ
GJ
R
R
D
D
K
K
0000
0001
0010
0000
0001
0010
A
}
0-1
CB
B-Register
Source
Control
0-3
CK
Emit Value
Dummy Symbols - No Action or Can be Used in
the Diagnostic Area
Gate the GR-Register (Selector Channel) to A-Register Via A-Bus
Gate the GS-Register (Selector Channel) to A-Register Via A-Bus
Gate the GT-Register (Selector Channel) to A-Register Via A-Bus
Gate the GJ-Register (Selector Channel) to A-Register Via A-Bus
Shown on Line 3 of the CLD Box
Gate the R-Register to the B-Register Via the B-Bus
Gate the L-Register to the B-Register Via the B-Bus
Gate the D-Register to the B-Register Via the B-Bus
Gate Hex Value of the CK Field to the B-Register Via
the B-Bus
Shown on Line 2 of the CLD Box
}
Binary Bit Form of the Hex Number is Routed to
the Selected Area When Requested.
S/360 MODEL 30
21
READ ONLY STORAGE CONTROL
(continued)
Field
0-3
CK
Emit Value
(Continued)
Hex
5
6
A
D
0-3
Alternate
CK
Activatcd
by"AK"=l
Mnemonic
Old Form
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
O __DrAG
RESET
DrAG
UV__WX
WRAP.... Y
WRAp....X6
HJ __ B
AC FORCE
YM
yr;;
1_0E
ASCII_XG
A
Ir;;T__X6,
X7
O_:\IC
Y__WRAP
D
O__LOAD
E
O_F
F=O
I __ FO
1"0=1
TE
TE
TE
JE
JE
Q
Q
TA
TA
S
R
D
D
A
G
G
D
V
U
J
T
E
0-2
CF
A-Register
to ALU
22
S/360 MODEL 30
Binary Bit Form of the Hex Number is Routed
to the Sclected Area When Requested.
Shown on Left Side of Line 6 of the CLD Box
Reset the Diagnostic Latch
Gate thc V-and V-Register to the W-and X-Registers
WX L'V
Via the \VX-Bus
RESTORE Gate the Wrap Buffer Latch to the Wrap Latch
WRAP
Sct X6 to ZERO if Wrap Latch is On
TEST
WRAP
Gate the H-and J-Switches to the B-Rcgister Via the
HJ
B-Bus
AC
Set X-Register to ZERO, if an ALU Carry Occurred
FORCE
in Previous
Dummy
Action or Used in Diagnostic Area,
Old Mnemonic was Reset 1050 Line Latch
Dummy Symbol-No Action or Used in Diagnostic
Area, Old Mnemonic was Set 1050 Line Latch
OE-I
Force an ALU Check (Note 3)
Sct X-6 to ZERO if the ASCII Latch is On
TEST
ASCII
TEST INT Set X-6 and X-7 per Stacked Interrupts (Note 4)
MC-O
STORE
WRAP
LOAD
0-3
CD
Destination
of ALI:
Output
Operation
V
1:
Set Machine Check Register to All ZEROS
Gate thc Wrap Latch to the Wrap Buffer Latch
Reset the LOAD, ODD/EVEN, and INTRODUCE ALl:
CHECK Latches
Reset the F-Register to ALL ONES, Note: The
Reset Condition of the I<'-Register is ALL ONES
Set the F-Register Position 0 to ZERO
Shown on Line 3 of the CLD Box
To Show That thc Z-Bus is the Only Place the Output
of the ALU is Routed
1050 Bus Out (Exit)
Direct Data Channel Bus Out (Exit). Set JE-Register
from D-Register, Z-Bus not "L'sed,
Gate the Output of the ALU to the Q-Register Via the
Z-Bus
1050 Tags Out
IG~te
the Output of the AL U to the _Register
Vla the Z-Bus
Shown on Line 3 of the CLD Box
Block A-Register Exit to the ALU, Route ALL ZEROS
to ALU Entry for the A-Register
Block High 4 Bits of A-Register. Route 4-ZEROS and
Bits 4-7 of A-Register to the ALU
READ ONLY STORAGE CONTROL
(continued)
Field
Hex Mnemonic
A-Register
to ALU
(Continued)
Old Form
H
H
SP
Xlf
Xlf
XL
XL
X
x
0-1
CG
I3-Regtster
to ALU
STOP
L
H
0-1
CV
Arithmetic
Functions
@
0-2
CC
Arithmetic
Controls
oc
Ie
CO
Cl
cc
CC
0-3
cs
I
Stat~
Operation
Block Low 4 Bits of A-Register, Route 4-ZEROS and
Bits 0-3 of A-Register to the ALU
Gate the Entire A-Register to the ALU
Conditional Machine Stop (Note
Bloek A-Register Bits 0-3 Exit
A-Register
Bits '1-7 to ALU Entry Bits 0-3 and 4-ZEROS to
Bits 4-7
Block A-Register Bits 4-7 Exit, Gate A-Register Bits
Bits 0-3 to ALU Entry Bits 4-7 and 4-ZEROS to Bits
0-3
Gatc A-Hegister Bits 0-3 to ALV Entry Bits 4-7 and
Gate A-Register Bits 417 to ALU Entry Bits 0-3
Shown on Linc 3 of the CLD Box
mock B-Register Exit to the ALU. Route All ZEROS
to the ALl: Entry for the B-Register
moek High 4-B1ts of the B-Register. Route 4-ZEROS
and Bits 4-7 of the B-Register to the ALU
Block Low 4 Bits of the B-Registers. Route 4-ZEROS
and Bits 0-3 of the B-Registcr to the ALU
Gate the Entire B-Register to the ALU
Shown on Linc 3 of the CLD Box
True Add B-Register Data
Complement Add B-Register Data
Binary Add or Subtract Depending on the Status of 50
Decimal Add or Subtract Depending on the Status of SO
Shown on Line 3 of the CLD Box
Block Carry
Insert Carry
A}fD Function-Chcck to See if Same Bits are Set to
O}fE in both the A-and B-Rcgister "csing thc ALU
OR Function-Check to See if Either Elt in the Same
Position of the A-and B-Register is Set to ONE
No
Set S3 to ONE if a Carrout Occurs
Insert
and Set S3 to ONE if a Carryout
Occurs
Allow Carryin from Carry Latch and Set S3 to ONE
if a Carryout Occurs
Exclusive OR Function-Check to See
A-or
B-Register has the Same Bit Position Set to ONE
Shown on Line 5 of the CLD Box
No Action
Set S5 to ONE if Bits 4-7 of the Z-Bus Are 0,
Reset S5 if Non-Zero
S4-LZ
Set S4 to ONE if Bits 0-3 of the Z-Bus are 0, Reset
S4 if Non-Zero
S4,S5=HZ, Combines the Conditions of CE Field Mnemonics
LZ
LZ S5 and HZ S4
S4,S5=0
Set S4 and S5 to ZERO
Sl=TREQ Set S1 to ONE if a 1050 Request has Occurred. Set
S1 to ZERO if no 1050 Request
SO-O
Set SO to ZERO
SO=1
Set SO to ONE
Sct S2 to ZERO
S2=0
S2 ANS}fZ Set S2 to ONE if the Output from the ALl.' is NonZero (Note 6)
S6 0
Set S6 to ZERO
S6=1
Set S6 to ONE
S7 oo 0
Set S7 to ZERO
S7=1
Set S7 to ONE
FB-K
Multiplexor Channel Tags Out
FA=K
Multiplexor Channel Tags Out
S5=LZ
Conditions
HZ __ S4
HZ--S4,
LZ __ S5
O__ S4,S5
TREQ __ S1
O--SO
0__ S2
A\'.rSN~2
A
C
D
E
F
I __ S6
0-87
1--S7
K __ FB
K __ FA
S/360 MODEL 30
23
READ ONL Y STORAGE CONTROL
(continued)
Field
}ox
Dummy Symbols
Kc-R
KD-R
KK__ R
KUV_KCD
R_KK
R __ KF
D
E
24
Operation
YH
YJ
KS_R
A
Note 1
Old Form
Shown on Line 5 of the CLD
9
N-Register
Set as Follows:
NO-Forced
toONE
NI-Forced
to ZERO
N2-CN OBit
N3-CK OBit
N4-Forced
to ONE
N5-CK lBit
N6-CK 2Bit
N7-CK 3Bit
Mnemonic
Hex
0-3
Alternate
CS
Selector
Channel
Activated
by"AS"=l
Selected
by
Hardware
R--KG
R--KU
R __KV
K.....MP POSITIONS 0
AC
ACS
1
1
2
3
2
3
•
ADDRESS 1M (I/O ADDRESS)
F
FA
F8
FG
FI
FT
FWX
EXTERNAL INTERRUPT REGISTER
MX CHANNEL CONTROL
MX CHANNEL CONTROL
SWITCHES FG
MX CHJl.NNEL BUSS IN
MX CHANNEL TAGS IN
MX CHANNEL BACKUP ROMAR
GR,
GS
GT
GUV
SX CH TAGS OUT CTRl
SX CH CONTROLS
SX CH COUNT REG
SX CH FLAG REG
SXCHCQMREG
SX CH CONTROLS
SX CH K FIELD CTRl A-REG ENTRY
SX CH PROT KEY REG
GROUP MARK-WORD MARK
SC CH DATA REG
SX CH " .... EG ENTRY
SX CH A-I:EG ENTRY
Sx CH DATA ADDR REG
HJ
H
HZ
SWITCHESHJ
HOLDING REGISTER-PRIORITY
HIGH ZB.USS
CH
1
•
7
8
•
10 11
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
o
2
3
o :,
2
12
13
15
..
0"
:;~~
A
",
C
D
E
F
S.
GO
G2
G'
G.
ZeO
G7
S3
55'
S7
GI
•
• :!
•
7
8
AC
SO
@
~f~s~r;:: !~)ctions When
R-VDD
R VALID DECIMAL DIGIT
STATUS IN (VO)
STOP
WRITE BUT DON'T SET R (CLEAR)
SERVICE IN (VO)
TE
Tt
TREQ
TT
TA
IOSO BUSS OUT (EXJn
IOSO BUSS IN
IOSO REQUEST
IOSOTAGS IN
IOSO TAGS OUT
MPXSTORAGE
VOl 00
tOAD
RESET LOAD, ODD/EVEN CTRl. INTRa ALU
CHK
GATE CA FlELD TO W STORAGE WRAP LATCH
STORAGE WRAP LATCH
WRITE AND SET R
OE
ODD, EVEN AND ALU CHECK CTRL
O"N(t/O)
,A
'N
Ps
ADDRESS PARITY (ROS ADDRESS)
NEXT ADDRESS PARITY
SAl1'.ARITY
Q
STORAGE PROTECT REGISTER
T~~~
..oa.... LT...
GUV
I
I
I
I
I
I
I
INT
CA·K
0,
STORE
IJ_MN
)
/
In
VZ
18C
ONE BIT CARRY
.no
AND
OR
EXCLUSIVE OR
¥-
MS
LS
M'X
M/LS
~:'@
M'X
MACHINE CHECK
MACHINE RESET
20 21
UV.MN
ftEB
DIRECT DATA CHANNEL BUSS OUT (EXJn
DIRECT DATA CHANNEL BUSS IN
MC
MRST
19
SVO
5
~o
VZ
ST
ST
STOR
SV
WRITE
17 18
NOTE: A! SETS WAIT LATCH ON
¥ ± SETS MACH CH MASK LATCH
FROM RS AND ASCII LATCH FROM R4.
"aa In Storage Control Meons 00 Is Low
Order Digits Of Effective Address Formed
1
0
1
2
2.
22 23 2' 25
FT
TT
YA
YB
1
27 28 2.
48
..
2
3
30
31
I,
32
51 52
CD
0
C
33 34
2
3 0
35
36
•
Z
TE
JE
K
Q
I
1
38 39
C
Q
JI
Tt
Selector Chan Option
58 5.
56
CV
ALT
62 63
CC
2
0
1
1
0
1
40
41
42 43 44
....
46
,
TA
H
S
R
D
L
G
T
V
U
J
I
0
64
SPARES
6566
68
+
A
A
S
K
1
2
"
48
4.
SO 5152 53 54 55 56 Sl 58
3
70
¥
H~S4
LZ"S5
a.S4,55
C
C
C
Decoder In PS Pari Iy
TREQ+Sl
....SO
I-SO
1 Ac;:tivates Alternate CS
0·52
ANS NZ+S2
0-S6
I....S6
I
5.
t'~~-~-,
Lz..SS
HZ...S4
"
I
C
A
A
0
1
:(DEC)
t(BIN)
L
H
CS
2
Decoder In PC Parit
'-----,
0....S7
1-+57
K-+fB
K-F
+-_.,
Ac:tivutes Alternate CA
Dec:ocler In PS Pari Iy
I
Selec:tor Channel Optlon _ _ _
I
{,-_L_~_W___W_X"""'f-----';"'~~--I
53 54
0
l
H
I
/
STAT
CONTROL
OPANDCARRY
CG
F
1
0
R
l
S
H
FI
R
D
L
G
T
V
U
J
I
/
ENTRY
CTRl
9PTIONS
,
CK
1 0
0
3
....
43 44
"!II 3.
CB
CA
0
ALU B
TRY
C NTROL
36 37
CU
2
STI
•
0
INTERRUPT
LOW Z BUSS
1
WRITE
0
1
2
3
INT
MAIN MEMORY
MAIN MEMORY OR LOC STOR - (LOC STOR
,.
0
0,
1
CAhh-W
AI
JE
JI
lZ
MS
M/LS'
CM
3
Alternate CPU Decoder Ac:tlvated By CM I- 3 - 7'-----<1>1>
w.... ,
32 33
~UA
DESTINATION
CONSTANT
AREG
INPUT
30 31
27 28
Cl
0
0100
STORAGE
CONTROL
SAlS
A
0000
COUNTER FOR INTERVAL TIMER
LOCAL STORAGE
GMWM
5
_RANCH
lOW
23 24 \
20
S
0001
0010
0011
C
LS
I.
5
ALTERNATE CS
ANSWER NON ZERO
PSWBIT 12
G8
•
ADDRESS CARRY (ALU CARRy)
AI
ANSNZ
ASCII
GCD
GF
GG
GH
GJ
GK
18
, ,
CN
ACU
ALTERNATE CU
AC FORCE SET X REG=() IF AC ON PREVIOUS WORD
GA
BRANCH
HIGH
NEXT ADDRESS
NUMBER
I
O"DlAG
IN+WX
WRAP...",
WRAP-X6
H~
AC"'FORCE
YM
Y!"
I.... OE
TEST ASCII X6
TEST INT X6X7
O-MC
Y...WRAP
....CAD
O_F
I-Fa
GUV-GCD
GR""'""<3K
GR-GF
GRo-GG
GR....GU
GR-GV
K-GH
GI-GR
K-GB
K-GA
~
Alternate CA Oec:oder
Activated By AA (Col 63)=1
Alternate CS Decoder
Ac:tivoted By As (Col 64)=1
Alternate CK Decoder
Ac:tivoted By AK (Col 65)=1
LOGIC BLOCK
BRANCH - - - - ,
IDENTIFIER
XX
NOTE: Only The Fields And lines
Necessary In A logic Bloc:k Are SpecIRed. Fields Not Specified Are Considered To be the Zero or Blank Combination as Required.
,--HEX
XXXX
ADDRESS
~~: ~~~ €~), CB, CG + C~~~~, ~E2)
CM, CU
[
CS
ACK
CH, CL
XX----XX
i
By The K Field
CO..QRDINATE
J
I
VERSION NO.
NEXT ADDRESS
XX
L.SERIAL NO.
LEG SELECTOR
8/360 MODEL 30
27
\
SY8TEM/360 - MOD 30 DATA FLOW
2540
peG (Non UCS)
28
8/360 MODEL 30
(
MULTIPLEX CHANNEL MlCRo-PROGHAM DATA FLOW/TIMING
START 10
INITIALIZATION
AND CCWCHK
CHANN L SETUP
& INTER ACE
SEQUENCE TO
RISE OF CMO-o
44 CYCLES
9 CYCLES
EXECUTE
CHANNEL
FINIS
CNL TUP
& INTtRFACE
SETUP &
** Device selection time
is a function of
priority position of device on interface.
Formula (T:::NX1.5)J. S) gives worst case
time for any priority position (N).
INTERFACE
SEQUENCE
30 CYCLES
SEQU NCE
21 CY lES
SET MULTIPlEX
SHARE INTERLOCK
BLANK CYCLE &
STORAGE OF CPU
REGISTERS
20 CYCLES
HARDWARE FORCED
I------+l~~~~ ~6:..~~
SETUP CHANNEL
FOR MULTIPLEX
r-_ _~~~T~~~~ENCE
"SHARE" ENTRY
Timing infonnation is
given in ROS cycles
rather than ,.u..SEC in
blocks where operation
time depends upon RQS
cycle timing. The diagram thus coven timings
for both the original and
improved versions of the
Model 30.
Cycle Times of RDS:
OrigInal l.u.S/Cycle
Improved .75 ..u..S/Cycle
f
15 CYCLES
POLLING RESUMED;
HARDwARE FORCE
"SHARE" ENTRIES
REMAIN INTERLOCKED
All indicated timings are for worst case paths in the Multiplex Channel
Control Micro-Progrcm. Some extension of the worst case times computed from this diagrcm con result from unit response delays in interface
signaling. The maximum value of this time it 32 micro seconds by specification. However, this much elongation will never occur on the Multiplex
Channel because all of the response sequences are overlapped with other
control sequences to some extent. Typically, this elongation {in initial
selectio.n) might Nn fran 0 to 10 micro seconds.
·This figure changes with inclusion of the following mochine features:
1. 64K Storage and No·Storage Protect -- 21 Cycles
2. 64K Storage and Storage Protect
-- 22 Cycles
3. Storage Protect and less than 64K
-- 20 Cycles
RESET
MPX SHARE
INTERLOCK
9/360 MODEL 30
29
ADDRESSING OF UCW - I/O FORMAT
INSTRUCTION FORMAT
o
Bit Pos.
7 8
15 16
OP CODE
BYTE 1
31
Bl
SI
BYTE 2
I
01
I
I
BYTE 3
BYTE 4
~----~vr------~
t
Start 1/0
Test 1/0
Halt 1/0
Test Ch.
,
I
9C
90
9E
9F
1
'{
SHARED SUB CHANNEL
-------OR
SINGLE SUB CH.
t
"
Note 1:
Address of byte within
UCW determined by
Micro Program.
V-REG
0= Single Sub Ch.
I
Note 2:
Not used to determ i ne
UCW Address of Shared
Sub-Chans. Used for
Addr. of 1/0 Unit.
ie - Tape Drive
~
10 10
I 01
T-REG
XXHXH XL
NOTE 1
BYTE 4
BYTE 3
A
oJoJoloJolx xix xix Ix [xlx [xJxlx
16117118119120121 22123 24125126127128129130131
r
~
11 11 10 11 10 11 11
'--v-i'v'
!
I
NOTE 2
~
Addr. of 1/0
0=UCWO_15
I=UCWI6_31
001
010
Ctrl. Unit &
UCW
--------....I,---',~,
I
I
I
10 10 10 I
XXH XH XL
Resetl Set by Commands
FB = K9, X
Ie:
S2_XL
1 ----. XH etc.
30
S/360 MODEL 30
0
)
I
Jill ~
1 = Shared Sub Ch.
~
I
SET TO ZERO
UNIT CONTROL WORD
Status
l
Count Count Data Addr
Flag
OP
Hi
La
Hi
La
Next
XO
Xl
X2
X3
X4
X5
X6
X8
X9
XA
XB
XC
XD
XE
0
7
or
0
1
2
3
4
5
6
7
Hex
CCW Addr
La
Hi
0-15
Addr
X7
Hex
Addr
XF
Local
Storage
16-31
0 ....7 0_7 0+70_7 0....,.. 70----.7 Bits
+
Indicates Data Addr. Wrap for 64K
Chain Data Address
Chain ommand
Suppress Incorrect Length -SIL
Skip Flag
'" Pro9ram Contro Interrupt - Pu
**Active Bit
OutPut
(1) Input
0
Decrement (1) Increment 0) (Data Addr.)
'" IPL Routine
**Set During Start I/O, Reset By I/O Interrupt or
Test I/O Instruction
Zero Count - 1050 Only
~
J-2
3
4
~
t+7
00
01
10
11
Channel Control Chec:k
Interface Contro Chec
Sub Channel Expects Data
Sub Channel Term. Data X Fer - Status Exp.
Status From Unit - Qued Bac - Inter. u er
"Active Bit"
Must Be On
ull
Status From Unit - Accepted - Now In Inter. Buffer
Wrong length Record
To Be
Meaningful.
Program Check
Protection Check
MULTIPLEX CHANNEL CONTROL
CKO.-+FA
CK1.-+FA
CK2_FA
CK4.-+FA
CK8_FA
CK Field
P 0 1 2 3
1
1
1
1
1
CK5~FB
0
0
1
1
CK6.-+FB
CKA~FB
CKC_FB
1
1
0
1
o0
CK3~FB
0
CK9~FB
0 1
o
Reset By
FA Reg Latches
Command Start
KO 0 FA
Fall of Serv or Stat In
Service Out
Fall of Addr Stat or Serv In
Command Out
Address Out
Buss Out Ctrl.
Fall of Add Ser or Cmd Out
NOTE: Some functions may be combined.
Blanks in CK Field Are Not Significant
Description
FB Reg Latches
0 1 Operational Out Ctrlls Op Out Line
Determines Chnl/CPU Error
1 0 MPX Op Latch
1 0 Suppress Out Ctl Ctrlls Supp Out
IB Full
01OJ. MPX Interrupt
Mask Latches
Controlled by RO
1 1 MPX Channel
Controlled by R1
Sell Channel
Sel 2 Channel
Controlled by R2
External Mask
Controlled by R7
Bump Addr Lat
0 1 XXH MPX 1
Controlled by SO
XL MPX 2
Contralled by S1
Controlled by S2
XH MPX 3
8/360 MODEL 30
31
MULTIPLEX CHANNEL CONTROL
FT - BUS - CONTROLLED BY CA FIELD
Function
Suppress Out (Diagnostic Use Only)
Hold - In Latch (Direct Data Channel)
Multiplexor Operation Latch
Multiplexor-Share-Request Signal
(if command start is off)
Initial - Program Load Latch
Select - In Interface Signal
Select - Out (Diagnostic Use Only)
Multiplexor Channel Interrupt Latch
2
3
4
5
6
7
STA TUS - IN and SERVICE - IN BRANCHES
Stat-In
1
{J
1
{J
Serv-In
1
1
{J
{J
Function
Operational-In is Down
Service-In and Operational-In
Status-In and Operational-In
None of the ahove, Note 1.
Up
Up
NOTE 1: Usually "OperatIOnal In" Up, and "ServICe In"
and "Status In" Down
SELECTOR CRANNEL CONTROL
CM Field
7
ALT CA Field
C
D
E
F
Diag. Control - (GUV_MN)
GR
GS
GT
GJ
ALT CS Field
6
7
8
9
A
B
C
D
E
F
GUV-- GCD (Count)
GR..... GK (prot. Key)
GR_ GF (Flags)
G:a-- GG (Command)
GR-+GU
GR ..... GV (Data Address)
K ..... GH*
GI -GR (Bus In)
K ..... GB*
K-+GA*
*
* Decode from SALS (others from Ctrl. Req.)
32
S/360 MODEL 30
SELECTOR CHANNEL CONTROL
K-~GB. K_HB CONTROLS
{continued]
CK FIELD
DECODE
'KO
REASON
NAME
Program Check
Kl (0 or 1)
K2
K3
K4
K5
SX2 Selection
Operational Out Reset
Reset PCl
Selector Interrupt Set
Channel Control Check
K6
K7
K8 (0 or 1)
K9 (0 or 1)
CPU Stored
COWlt Ready
Zero Count Except for TIC, Invalid
Memory Key, Memory Wrap, Three
Low Order Flag Bits Not Zero, First
CCW is a TIC, Two TICs in Succession
CCW Not on Word Boundaries or Invalid
Command.
D - SXl, 1 - SX2
A Macoine Check Trap (H Register 5
Latch On) Indicates Hardware Failure,
or an MN or GHYZ Parit.y Check During
a Selector Share Cycle.
Set GR to- Zero
o - Reset, 1 - Set
Channel Reset
Not Poll Control Reset,
Poll Control Reset
0- Reset, 1 - Set
0 Reset, 1 Set
0
1
KID (0 or 1) Suppress-Out
Kll (0 or 1) Poll Control
K12
Reset Select-Out
K13
Channel Busy
See Halt lja Latch
K14
K15
Interface Control Chk.
=
-Address Mismatch, No Response, Time
Out, Unit Busy on Chaining, Address
or Status Parity Error.
*(0 orl) Refers to the CK Field Parity Bit
GA or HA Reg (K_ GA)
CK Field Bit
CK
CK 1
CK 2
CK 3
Prog. Symbol
Bus Out Ctrl.
Address Out
Command Out
Service Out
GJ Entry into A- Reg (K........,...GJ)
K8
K4
K2
Kl
GR or HH Reg
EMIT
(K-~GH)
EMIT
K~
K 1
GG+GJ
K2
K3
K4
K5
K6
K7
K8
GD+GJ
GK~GJ
GE?o'GJ
}
SXl or 2 CtrlS-ioGJ}Diag,
SXI or 2 Tags .. GJ Ctrls
GO or HO --..GJ
A - Reg.
Parity
Ignored
K~ SXI, SX2 Mach. Reset}Diag .
Kl Set Diag. Mode
Ctrls
& Tag Ctrl
K2 Reset Diag. Tag Ctrl
K3
K4
K5
K6
K 7 Set Chain Detect
K12 Set Select Out
S/360 MODEL 30
33
SELECTOR CRANNEL CONTROL
rcontinued 1
Input to GJ Assembler
Bit
Diagnostic Controls Bus
GE Bus
Diag. Tags Bus
P
None
None
None
0
PCI
COlmt Ready, Not Zero
Input
1
Incorrect Length
SLl Flag
Suppress Out
2
Program Check
Output
SXI ROS Request
3
Protection Check
Count Ready, Zero
Address Out
4
Channel Data Check
Selector ChnL Data Trans.
Command Out
5
Channel Control Check
CC Flag
Service Out
6
Interface Control Chk.
Read Backward
Bus-Out Control
7
Not Used
Skip Flag
Operational Out
GS or HS Entry into A - Reg
GS¢. RS¢
GR Full
Chain Detect
Select Out
Interrupt Condition
CD Flag
SXI Gate (1 SXI Gate,
m
Interface Check
GT or HT Entry into A - Reg
GT¢. HT¢
Select In
Serv in & Not Serv Out
Poll Ctrl
Chnl Busy
Address In
Status In
SXl (or 2) Interrupt LA
Operational In
GR
or HR Entry into A - Reg
GR¢. HR¢
4
34
S/360 MODEL 30
Device Address
or
Device Status
CPU CHANNEL LOGOUT
f- CPU-l---- MPX------l
"-
80
.
1 ~--orI
81#
82
83
84
85
MACH CHECK
REGISTER
SIT CONDITION
A REG
0
1
B REG
2
MN REG
3
CR
4
SALS
S
ROAR
6 R REG/Q REG
7
AlU
86
INDICATOR
t0Jr
-I
SELl 1 -
I:ND'C
MeR I, MCR
OR
AlOR I,UN'T,
ADDR txjMCR
OR {ND'CA-I,UNIT
TOR
ADDR
CAT
CAT #
~
87
88
LOG-OUT C NT.
ItCCu~
6
-1
SA
NIT
ADDR
88
I7 I
INTERFACE STATE
BITS
00
fSET
1 ON
ANYTO
LOG-OUT
CONDITION
89
I
BYTE
101,12131.ls
r
SELl 2 - - - - 1
I:NDICAOR
TOR
CAT #
01
MEANING
INTRF CLEAR (OP IN DOWN)
AT ERR OCCURRENCE
HID RESET REQUIRED
AND SUCCESSFUL
10 SELECTIVE RESET REQUIRED
AND SUCCESSFUL
11 INTRF LOCKED UPi SELECTED
RESET FAILED
1 CATALOG NUMBER STORED} DETERMINES lNFORMATION
o MeK REGISTER STORED
TO BE STORED IN BYTES
81,85,or89.
"
t
MULTIPLEX CHANNEL,
HEX NO
20
31
41
so
Sl
70
77
80
90
AD
80
CATALOG NUMBERS
MEANING OR CONDITION eeN SOURCE
FALSE SHARE REQUEST,
Q(601 GG
CONS.
NO ADDR MATCH ON
INITIAL SELECTION
NO ADDR MATCH ON
INITIAL SELECTION
SELECTOR CHANNEL CATALOG NOS.
HEX NO
10
MEANING OR CONDITION
POLL CTRl TIME-OUT (SIO,
no,
OC051 GJ
20
QC051 GJ
30
~~E~~~~~~~~~~~~~NE
QC161 CE
FALSE REQUEST, WITHOUT
SELECT-IN PROPOGATED
DOUBLE SELECTION (CONSOLE AND OTHER
USED BY A NUMBER OF ICC
T!MEOUTS DURING THE
VARIOUS SEQUENCES. THE
EXIT WORD IS 500 AND IS
ENTERED BY WAY OF THE
AC FORCE MICRO COMM.AND. TO FIND THE ERROR,
SET SYSTEM TO EARLY
ROAR STOP ON ROS ADR
500.
DATA LOOP TIMED OUT.
NO RESPONSE FROM UNIT
NO UNIT RESELECTION ON
COMMAND CHAINING
NO SELECTION AND NO
SELECT IN
UNIT oro NOT STOP AS
TOLD AFTER CCW EXHAUSTED OR TERMINATED
OC211 EF
50
QC151 GE
60
70
80
QCOO1 NF
90
QC091 CD
AO
OC091 CD
80
QC081 lF
NO ADDR-IN, STATUS IN,
~~ii~-~~, (;1; O~II~)I:.
40
QC211ED
HIO.
~~6,Si:~~SHi6~.E-OUT
CO
EO
'FO
ADDR MISMATCH (SIO, TIO
HIO OR COMMAN 0
CHAIN.
NO STATUS-IN OR INITIAL SELECT (SIO, TlO,
HIO, OR COMMAND
CHAIN).
BAD ADDR, OR STATUS
BYTE ON I NITIAL SELECT
(510, TIO, HIO, OR
COMMAND CHAIN).
STATUS-IN TIME OUT ON
INITIAL SELECT (TIO)
STATUS-IN TIME-OUT ON
COMMAND CHAINING.
SELECT -IN ON CMD
CHAINING RESELECTION.
CONTROL UNIT BUSY
ON COMMAND
CHAINING
ADDRESS MISMATCH ON
TIO OR HALT 10
STATUS-IN OR OP-IN
CANNOT BE RESET ON
CSW STORE
POLL CTRL CANNOT BE
SET ON HIO
OP-IN CANNOT BE RESET
ON HIO
S/360 MODEL 30
35
MPX AND SX MICRO PROGRAM
Main fWlCtions of initial Selection of MPX and SX with the micro
Program Address where they are performed.
With ROAR STOP, one single cycle should be
done to perform the function.
Example:
MPX:
Addr.
Function
Address Out
Select Out
536
5A0
Test OP IN
Test Addr. IN
59D
5A8
Test Addr.
Match
Command Out
5A9
Test Status IN
Test Status 0
Service Out
5CI
604
609
5BD
Notes
Unit addr. Is displayed on Bus Out
If the Addr. Out has been recognized by a Ctrl. Unit, OP IN Is displayed
Addr. IN on Bus IN can be displayed
with FI (Switch E)
Command Out stays UP only few
microseconds and only Status In, as
an answer Is displayed. Status on
Bus IN can be displayed with FI.
Service Out stays Up only few microseconds and only Service IN as an
answer Is displayed.
,,1
SXI:
Address Out
93D
Select Out
9C7
Address IN
9B5
Command Out
94D
Status IN
'I '.' 9B3
Service Out
9B9
Service In
9C5
Note:
36
Unit addr. Is displayed In Data Reg.
Address Is displayed in A-Reg.
Command Is displayed In Data Reg.
Status Is displayed In R-Reg.
ROS Addresses can change, depending upon the
EC level of CCROS
S/360 MODEL 30
1050 INTERFACE REGISTERS AND TAG OPERA TIONS
REG.
Description
TI
TE
TT
Data to A from 1050
Data to 1050 from Z buss
Tags in to A entry
BITS
2
3
4
5
6
Cancel
RDR 2 Ready
End
1050 Operational
Home start
Intervention req.
Attention
Data check
REG.
Tags out Z buss to 1050
TA
BITS
0
2
3
4
Set home RDR start
Set RDR 2 to run
Force Share Request
Set proceed
Audible alarm
Set carrier return and line feed
A ttention reset
1050 Reset
T REQ to Sl, Set Sl on if 1050 share req.
S/360 MODEL 30
37
REGISTER DISPLAY AND FUNCTION
Note; "'Indicates that you cannot manually store data in the designated register.
Register
to be
Displayed
v
T
Where Displayed
Instruction Address (high-order bits)
A-register (also the high-order eight
bits of the main-storage address register if the allow-write indicator is
offj
Instruction Address (low-order bits)
A-register (also the low-order eight
bits of the main-storage address register if the allow-write indicator is
offj
Data Address (high -order bits)
A-register (also the high-order eight
bits of the main-storage address register if the allow-write indicator is
offj
Data Address (low-order bits)
A-register (also the low-order eight
bits of the main-storage address register if the allow-write indicator is
offj
Data Length
A-register
Auxiliary Storage Address
A-register
D
General Purpose Data Register
A-register
R
Storage Vata Register
A-register (Also has own display in
main-storage data-register indicators)
Status (CPLl
A-register
G
Instruction Operation Code
A-register
H
Priority Status Register
A-register
*FI
:\lultiplexor Channel Bus-In
A-register
*FT
Multiplexor Channel Tags
A-register
Storage-Protection key in PSW (High
4-bits) Storage-Protection key of
block of storage just used (low 4-bitS)
A-register
*C
Interval Timer Count
A-register
*F
External Interrupt: Interval Timer (bit
0) Console
1) Six direct-control
interrupts
2 through 7)
A-register
*TT
1050 Documentary Console Tags
A-register
*TI
1050 Documentary Console Bus-In
A-register
*JI
Direct Control Bus-In
A-register
*GS
Selector Channel One Status
A-register
Q
*GT
*GUV-GCD
38
Usual Function
Selector Channel One Tags
A-register
GUV contains storage address for data
for selector-channel one. GCD contains the current byte count for selectorchannel one
GUV in main-storage address reglater. GCD in count register (18 bits
each).
'HS
Selector Channel Two Status
A-register
'HT
Selector Channel Two Tags
A-register
S/360 MODEL 30
REGISTER DISPLAY Ai'W FUNCTION
(continued)
Register
to be
Displayed
*HUV-Hcn
Csuai Function
HUV contains storage address for data
for selector-channel two, Hcn contains the current byte count for selectorchannel two
Where Displayed
HUV in main-storage address register. HCD in count register (18
bits each)
Note: *Incticates that you cannot manually store data in the designated register,
8/360 MODEL 30
39
IBM 1407 CONSOLE INQUIRY STATION
AND IBM 1447 CONSOLE MODELS 2 AND 3
The functions of the 1407/1447 in run, character display, and
alter modes are available through equivalent procedures on the
IBM 1052 Printer Keyboard.
The following list gives the corresponding 1050 operations or
indications:
1407/1447 Functions
1050 Equivalents
Request key
Request key
Enter light
Proceed light
Respond key
Operate alternate code key and the
5-key
Type-out key
Not available
Clear key light
During a read-into-storage operation,
this function is performed by operating the alternate-code key and the
O-key.
During a write-out-of-storage operation, this function is not available.
Cancel key
Cancel key
Release key
EOB key
40
S/360 MODEL 30
1401 OPERATION CODES
2
3
4
5
6
8
9
A
B
C
D
E
F
H
K
L
M
N
P
Q
S
U
V
W
X
y
Z
0
/
%
#
@J
Read
Print
Print-Read
Punch
Read-Punch
Print- Punch
Print- Read- Punch
Read Release
Punch Release
Add
Branch
Compare
Move Digit
Edit
Form Control
Store B Star
Stacker Select
Load
Move
No Op
Move Record
Store A Star
Subtract
Unit Control
Branch _
WM or Zone
Branch - - Bit Equal
Move--Insert Zeros
Move Zone
Move Zero Suppress
Stop
Clear Wordmark
Clear Storage
Set Wordmark
Divide
Modify Address
Multiply
Zero and Add
Zero and Subtract
S/360 MODEL 30
41
1400 d MODIFIERS
d CHARACTERS FOR BRANCH
BIIld
d-Character
b
9
@
A
B
C
D
E
F
G
K
L
N
P
t
/
*
Q
R
S
T
U
V
W
X
Y
Z
%
Branch On
Unconditional
Carriage #9
Carriage Channel #12
"Last Card" Switch (Sense Switch A)
Sense Switch B*
Sense Switch C*
Sense Switch D*
Sense Switch E*
Sense Switch F*
Sense Switch G*
End of Reel * **
Tape Transmission Error*
Access Inoperable*
Reader Error if I/O Check Stop Switch is off**
Punch Error if I/O Check Stop Switch is off**
Printer Busy (print storage feature)*
Print Error if I/O Check Stop Switch is off**
Unequal Compare (B F A)
Inquiry Clear*
Inquiry Request*
Printer Carriage Busy (print storage feature)*
Equal Compare (B=A)*
Low Compare (B < A)*
High Compare (B > A)*
Read- Write Parity Check or Read- Back
Check Error*
Wrong-Length Record*
Unequal-Address Compare*
Any Disk- Unit Error Condition*
Overflow**
Processing Check with Process Check Switch off*'
* Special Feature.
** Conditions tested are reset by a BRANCH IF INDICATOR ON
instruction.
42
S/360 MODEL 30
d CHARACTERS FOR BRANCH
-IF WORD MARK OR ZONE
YIIIBBBd
d-Character
2
B
K
S
3
C
L
T
Condition
Wordmark
No zone (No-A, No-B bit)
12-zone (A-B bits)
11-zone (B, No-A bit)
Zero-zone (A, No-B bit)
Either a wordmark, or no zone
Either a wordmark, or 12-zone
Either a wordmark, or II-zone
Either a wordmark, or zero-zone
d CHARACTERS FOR FORM CONTROL
Fd
d
2
3
4
5
6
7
8
9
0
#
@
d
J
K
L
Immediate skip to
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
1
2
3
4
5
6
7
8
9
10
11
12
Immediate space
1 space
2 spaces
3 spaces
d
A
B
C
D
E
F
Skip after print to
0
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
d
After print- space
/
1 space
2 spaces
3 spaces
G
H
?
S
T
1
2
3
4
5
6
7
8
9
10
11
12
S/360 MODEL 30
43
)
BCD TO CM6 CONVERSION
1401 CODE TO 8Y8TEM/360 CODE
DEF i CARD
CHAR CODE
I BCD
CM6 CM6 DEFol'CARD:
WM
HARCODE
F==F==~===F=4~
Blank
40
C
00
J:(
[
<
'*
&
$
J
A
/
BA821
BA84
BA84 1
BA842
BA8421
BA
B 8 21
B 84
B 84 1
B 842
B 8421
11
B
v
0-1
0-3-8
0-4-8
0-5-8
\
0~6-8
,
%
b
#
@
?
A
B
C
D
E
F
G
H
44
12-3-8
12-4-8
12-5-8
12-6-8
12-7-8
12
11-3-8
11-4-8
11-5-8
11-6-8
11-7-8
0-7-8
2-8
3-8
4-8
5-8
6-8
7-8
12-0
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
A
1
A821
A84
A84 1
A842
A8421
A
8 21
84
84 1
842
8421
BA82
BA
1
BA 2
BA 21
BA 4
BA 4 1
BA 42
BA 421
BA8
8/360 MODEL 30
4B
4C
4D
4E
4F
50
5B
5C
5D
5E
5F
60
61
6B
6C
6D
6E
6F
7A
7B
7C
7D
7E
7F
CO
C1
C2
C3
C4
C5
C6
C7
C8
i
I
I OBOC I J!
t
I
i
i
I,
OD
K
OE
OF
L
M
10
1B
1C
0
lD
Q
N
P
1E
R
1F
20
21
2B
2C
2D
2E
2F
3A
3B
3C
3D
3E
3F
80
81
82
'"
83
84
85
86
87
88
5
T
U
V
W
X
Y
Z
0
1
2
3
4
5
6
7
8
9
BCD
CM6 CM6
WM
12-9 IBA8 1
11-0 'B 8 2
11-1
B
1
B
2
11-2
B
21
11-3
B 4
11-4
B 4 1
11-5
11-6
B 42
11-7
B 421
B 8
11-8
B 8 1
11-9
0-2-8 A8 2
0-2
A 2
0-3
A 21
0-4
A 4
0-5
A 4 1
0-6
A 42
A 421
0-7
0-8
A8
0-9
A8 1
8 2
o
1
2
3
4
5
6
7
8
9
1
2
21
4
4 1
42
421
8
8
1
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
89
90
91
92
93
94
95
96
97
98
99
EO
AO
E2
E3
E4
E5
E6
E7
E8
E9
A2
A3
DO
A4
A5
A6
A7
A8
A9
FO
BO
F1
F2
F3
F4
F5
F6
F7
F8
F9
B1
B2
B3
B4
B5
B6
B7
B8
B9
SUGGESTED STANDARD ADDRESSES
1412"f
1418
1419 Optical and Magnetic Sorter Readers
1428
1442 Card/Reader/Punch
1443 Printer
2540 Card Reader (1st)
2540 Card Punch (1st)
1403 Printer (1st)
1403 Printer (2nd)
1403 Printer (3rd)
2540 Card Reader (2nd)
2540 Card Punch (2nd)
2501 Card Reader
2520 Card Reader/Punch
1285 Roll Reader
1231 Page Reader
Channel-Channel Adapter
12671 Paper Tape Reader
1050 Console
2701/2702 Teleprocessing (1st)
2701/2703 Teleprocessing (2nd)
2400 Magnetic Tapes (1st TAU)
storage Control
2400 Magnetic Tapes (2nd TAU)
(1st)
(2nd)
08
09
OA
OB
OC
OD
OE
OF
10
12
13
14
15
16
17
18
07
IF
20
30
8X
9X
AX
S/360 MODEL 30
45
)
1400 COMPATIBILITY PROGRAMMED AND ERROR STOPS
On all stops at ROS address 10FF except for Set-IC and Sense
Switch operations, a coded digit is displayed in the main storage
data register (MSDR) to indicate the reason for the stop, and all
the ALU output register lights are off. The 1400 decimal instruction address is displayed in the BA register lights and the
1400 decimal A-address is displayed in the MN register lights.
The 1400 decimal B-address can also he displayed manually in
the UV registers by the Normal 2030 procedure.
MSDR
Reason for Stop
00
Normal stop, Appears wben the stop is caused by
pressing the stop key, ending an instruction-execute in
instruction-step mode, or getting a match in SAR
Delayed-Stop mode.
01
Attempted to use invalid 1400 B-address.
02
Attempted to use invalid 1400 A-address.
03
Attempted to use invalid 1400 A- and B-address.
04
Attempted to use invalid 1400 operation code.
05
Invalid I/o operation attempted; either unit selection or
unit number invalid.
06
Storage wrap occurred when address was used, which
was outside of system capacity.
07
Storage protection occurred in 1400 mode.
08
Attempted to switch to 2030 mode without the PMS
feature.
09
Invalid source or destination address on one of the
special PMS tape operations.
OA
Attempted to convert to binary an address that was less
than the bias (offset) address on a clear storage or
store STAR operation.
OB
storage wrap-around 1400-address 0000.
OC
Attempted to start a 1400 I-cycle at main storage
address 0000.
46
S/360 MODEL 30
1400 COMPATIBILITY PROGRAMMED AND ERROR STOPS
[continued 1
MSDR
Reason for Stop
OE
Attempted to index without advanced programming
comment in CID.
10
FILE - Read-back check stop.
11
1050 - Some other device attempted to take a multiplexor channel data cycle while in the data-transfer
portion of a 1050 operation.
20
FILE - No channel or device ends received.
21
Word mark missing from 1400 operation code during
I-Op.
22
TAPE-SM Channel - Wrong address sent back from
channel.
30
FILE - Wrong address sent back from the channel.
31
Word mark in A-address of an I/O instruction.
3F
2540 or 2501 reader error, or invalid character
occurred. *
40
FILE - Unit check status response to seek command.
41
An SF character was detected at an address other than
the offset address while in 1400 mode.
42
TAPE - SM Channel - Invalid channel status on data
transfer.
4F
1442 - Reader intervention required. *
2540 or 2501 - Reader intervention required.
50
FILE - Operational interlock.
51
An I/O operation was attempted on a device for which
the compatibility feature is not installed.
52
TAPE - SM Channel - Device end signal before encountering a GMWM or a tape write operation.
55
A 1400 start reset function was performed using the
console interrupt key.
5F
1442 - Punch intervention required. *
2540 - 2520 Punch intervention required.
*
*
S/360 MODEL 30
47 )
1400 COMPATIBILITY PROGRAMMED AND ERROR STOP
[continued 1
Reason for Stop
MSDR
60
Module mis-match detected
61
Sterling Process check marked misalignment.
62
TAPE - S Channel - Status in and service in on a
tape write.
M Channel - Operational in disconnect on a
tape write.
6F
1403 - 1443 - Printer intervention required.
71
Sterling Process check, invalid character.
7F
2540 - Select stacker instrnction given after maxi-
mmn time-out.
*
*
80
1442/1443 - Wrong address sent back from the
channel.
2540 (or 2501 and 2520)/1403 - No address compare,
or plUlch-transfer error.
81
Sterling marked in add or subtract pence or shilling
position.
82
TAPE - S Channel - Statns in and service in on a
read move operation.
8F
TAPE - SM Channel - Tape-unit intervention required. *
90
2540/2501 - Operation-in disconnect on reader.
1442/1443 - Invalid d-modifier
92
TAPE - SM Channel - Error on a 1400 tape initial
program load.
AO
1442/1443 - No GMWM in storage.
1403 - Operational-in disconnect
A2
TAP E - S Channel - Invalid channel statns was received on a branch if error operation.
BO
2540/2520 - Operational-in disconnect or punch.
1442 - Error on read or punch operation.
B2
TAPE - S Channel - Statns in and service in on a 1400
read load operation.
C2
TAPE - M Channel - Operational in disconnect on a
read operation.
48
S/360 MODEL 30
1400 COMPATIBILITY PROGRAMMED AND ERROR STOPS
[continued]
MSDR
Reason for Stop
CF
1050 - Intervention required. *
D2
TAPE - M Channel - Prematnre end to a sense operation.
DF
1050 - Alter or display stop. **
E2
TAPE - M Channel - Operational in disconnect on
mode set operation.
FO
A 1400 halt instruction performed satisfactorily.
Fl
A 1400 halt instruction performed satisfactorily.
(Address in B-Star is invalid)***
F2
A 1400 halt instruction performed satisfactorily.
(Address in A-Star is invalid)***
F3
A 1400 halt instruction performed satisfactorily.
(Address in A & B Star is invalid)***
FF
A 1400 halt and branch instruction has been executed.
*
On these stops the operator may correct the condition and
then try the instruction that caused the stop by again press-.
ing the 2030 console start key.
**
Restart by pressing the 2030 start key.
***
Information described in parentheses indicate the validity
of the A & B Star when a 1401 halt operation is performed.
These statements do not indicate a machine failure.
S
Sele cto r channel.
M
Mul tiplexor channel.
S/360 MODEL 30
49
)
BIT ASSIGNMENTS FOR BYTES IN 1401 BUMP
(2030 AUX. STaR.) K ADDRESSABLE BYTES
CPU
BIT
A-Last Card Sense Sw
8-Sense Switch
(-Sense Switch
D-5ense Switch
E-Sense Switch
F-Sense Switch
G-Sense Switch
"XX98"
KB
o
"XX99" 1
3 5-
==
1442/1443
1 51 Column
2
KI
~ I}
R,ad" Add""
I}
Reader 1 Address
o
Not Equal
2 T-La
K9
1402/1403
"XXB9"
U-Hi
/-1
MPX/UCW
BIT
"XXBA"
3
Equal
z- Overflow
6 Q- Inq Request
i
K2
TEMPORARY FORMS
INFORMATION
4
5 Initialize to 08
6
TEMPORARY FORMS
INFORMATION
Initialize to 00
7
o
"XX9A" 1
2
KlO
3
4
1 for 64K
1 for 32K, 64K
1 for 16K, 32K, 64K
I
1
"XXBB"
K3
5 I
6 I
7 1 exce t for 64K
o X-Uneguol Addr. Compare
"XX98" 1 \-A.ccess Busy
2 W-Wrong Length Record
3 V-Any Disk Cond
Kll
4 V-Disk Error
5 N-Access Inop
6 RBe Interlock
I
2
~Il
51>
"13" or "39" Char Bar
Punch Address
6
o 132
Print Pos
"XXBC" 1
2
3
K4
4
5
Printer Address
Reader 2 Address
7 End Alternate Trock
a
10 Check Stop
"XX9C" 1 Adv Prog Feature
2 Expanded Edit
3 Mode Swan Inv Dps
K12
4
5 Mode Swan Halt
6 Tape on SX2
7 Mode Swan Error Slo s
Mode Swan Inv 10 Dps
"XX9D" 1 Mode Swan Console Ops
2 Mode Swan Printer Ops
3 Mode Swan Rdr/Pch Dps
K13
4
5 Mode Sw on Tope Dps
6 Mode Swan Fi Ie Ops
o
"XXBD" 1 Temporary Stacker2 Select Information
3
K5
4 Initialize 10-
5 ID for 2540
6 OD for 2501-2520
7
o
last Op was Fwd Sp Rec.
"XX9A" 1 ThisOpis FwdSpRec.
Erase latch
KID
1050 Error
Reader Error
Punch Error
Printer Error
7
o
"XX9E"
1
Printer Address
"XX9F" 1
load Mode
Type "H" Balian 1052
2
KI5
KI4
~
5
6
~7
"XX9F"
K15
3 Alt 9 Track Mode
4 0
5 Allow 10 Traps
6 0
7 0
*
50
Addresses are as shown for CPU-l.S. or MPX - i.e. "XX9F" is address of K15 CPU-l.S.
S/360 MODEL 30
/
LOCAL STORAGE - 1401 MODE
0
UNITS
OX
00
TENS
HUNDS-LO
BIN DEC
IX
X
3X
4X
5X
6X
7X
8X
00
YIX
SCD NPL
{
1401 AUX
STORAGE
A - CPU
9X
BiT
SIGNIFICANT{
OP CODE
TABLES
AX
BX
CX
DX
EX
FX
OX
IX
2X
3X
4X
HUNDS - HI
5X
NPL BCD \
NOTES
6X
7X
1401 AUX
STORAGE
B-UCW
8X
9X
AX
8X
CX
DX
EX
FX
NOTES: 1.
2.
3.
1
2
3
103
14 X
lEX
+64)X (y+CB1X +2C X
23
84
6'
F2
F3
Fl
61
E2
E3
D
D3
D'
C,
C2
C3
TAPE
CARD
TAPE
TAPE
LOAD J LOAD I LOADJ
01
02
OA X
00
40
7A
60
50
Tape Ctl
CARD
LOAD I
4
04
(28)X
+90 X
46
F4
F4
6
05
06
3C X
Y+5B X
69
F6
E6
D6
C6
32X
+F4 X
F5
5
D5
C5
D4
C4
RPQ
WORKING STORAGE
? 'c
A '8
BOB
1)lD
""
ClF
90
00
05
K 29
'9
2 22
01
Z+C
Z+OO+C
Z+OO+C Z+Ol+C
00
40
40
40
4B
40
58
40
68
34
1\ ,
30
20
40
FILE
SENSE
0
FILE
UNIT 0
ADDR
CYC'
00
H
3A
05
1
"
:g ~~)
40
FILE
SENSE
1
UNIT 0
CVC
CYC fI
32
R
31
FILE
SENSE
2
FILE
UNIT 1
ADDR
CYC fI
OA
4
3 23
06
7B
FILE
SENSE
3
UNIT 1
CVC
E '6
N 06
3A
5 25
07
Z+Ol+C
4C
5C
6C
7C
40
40
40
40
40
40
FILE
UNIT 3
ADDR
CYC'
IE
10
67
7B
68
58
10
29
7C
6
5C
4C
4
DO
,
CO
2
4B
9
10
17
25
18
26
"
34
34
34
34
C9
3
,4
'5
23
34
% 'B
@IA
34
34
34
34
30
34
34
34
34
3'
34
3D
2D
3E
2E
3F
2F
.)04
40
40
40
40
38
40
~~~
40
40
28
3C
2C
61
34
14
4L
5T
6G
7 S
8
9
10
o
~}
3
4
5
6
7
8
9
'0
Ucw
ERROR CODE
USED BV
1402 -03
1442 -43
o STAR HI
o STAR LO
FILE UNIT 4 ADDR
UNIT 4 CYLINDER
i/o ERROR
"
12
13
14
15
16
17
18
19
20
21
S/360 MODEL 30
51
,
60
40
40
'0
'B
08
1C
lD
40
OC
OD
'E
OE
OF
0
1
2
3
4
5
6
7
UNIT 3
8
CVC
9
10
"
12
13
14
15
19
27
so (A)
4E (H)
20
28
21
29
22
40
4B
30
4C
23
31
56
Cye'
50
16
24
17
25
18
26
37
38
39
40
26
16
27
17
28
18
29
19
40
60
40
40
40
40
49
46
4F
5D
56
06
07
08
09
40
1~~l
40
40
44
5F
I
FO
4. A'" 1403 A Chain
H = 1403 H Chain
5. See 1443 Load Variations Table
CPU
FILE BR BYTE
1401 CONTROL
PMS CONTROL
D BACK-UP
ALLOW I/O TRAPS
WORKING STORAGE
WORKING STORAGE
WORKING STORAGE
WORKING STORAGE
CONSTANT IF
STERLING FEAT
34
34
I 36
X Indicates the quantity in parenthesis is crossed in the table
Z'" Memory Bias-Hi
Y '" Memory Bias-la
C = Carry from addition to get entry in Hunds-Lo Table
CPU
BACK-UP
BACK-UP
BACK-UP
BACK-UP
BACK-UP
BACK-UP
BACK-UP
BACK-UP
SENSE SW B'fTE
HI-LO EQ BYTE
MEM SIZE BYTE
34
34
Z+-03+C Z+03+C
K ADDRESSABLE BYTE UTILIZATION
01
lJ
2U
3V
5F
4F
7
22
Z+02+C
05
7D
6D
5D
4D
5
13
40
40
04
'0
'0
,4
7F
90
2'
29
Z+02+C
!
F7
10
10
52
7E
6
5E
4E
6
'2
40
40
cyc I j
46
'
F6
10
10
20
28
, 5
Z+Ol+C
UNIT 2 i
CVC
D
F5
'9
27
.02
09
03
02
10
04
25
15
01
C
F4
10
8 06
24
14
OA
F9
F9
D9
F3
10
'0
06
FO
EO
08
I""
40
44
B
FO
7 27
23
13
22
12
A
5A X
+84
17
9 06
35
21
13
I
FiLE
UNIT 2
ADDR
CYC'
14
DL
9
09
3B
6 26,
03
32
2A
lA
134
8
08
50 X
46X
+BC X +20 X
8
3'
F7
F
E8
E7
D
IDS
C7
C8
Tape Stat 0
9 T RK
TAPE
8
FLAG
16
24
34
H}Bl
pilE
Q)Fl
D '2
M 80
U 20
4 24
02
CVC
3C
DL
33
00
F 2A
7
W
Ilf
14
15
16
17
18
Il~
TAPE
UCW
RK IN ERROR
A HUNDS BACK-UP
B HUNDS BACK-UP
1050 STATUS
CYL '28
CYL'SA
PREVIOUS FILE OPER
RESERVED FOR 1402 -03
00
00
22
23
24
25
26
27
28
29
30
31
CPU
STERLING FEAT
STERLING FEAT
STERLING FEAT
1400 TAPE
CONSTANT -OF
CONSTANT-2E
RPQ
UCW
22
23
24
25
26
27
28
29
30
31
C
H
WORKING
WORKING
WOR KI NG
WORKING
WORKING
WORKING
WORKING
WORKING
STORAGE
STORAGE
STORAGE
STORAGE
STORAGE
STORAGE
STORAGE
STORAGE
DEFINITIONS OF ALD PAGE NUMBER PREFIXES
A.
B.
C.
D.
E.
52
Adders
1. Addressing Adder
2. IC Incrementer
3. Exponent Adder
4. Main Adder
5. Serial Adder
6. VFL and DEC Adder
F.
AA-AB
AC-AD
AE-AF
AM.,AQ
AS
AV-AW
Decoders
1. Op Decoders
2. FLP and Gen. Decoder'
3. Addressing and Pre FTH
4. Trap Decode
5. Reg Decode
6. ROM Decode
DN
DP
DA
DB
DG
DR-DS
Counters
1. Instruction ctrs,
2. Local Store Address Ctr.
3. Misc. ctr.
CA-CB
CC-CD
CE-CZ
Busing (Excluding Memory Bus)
BA-BZ
Registers
1. A-Reg.
2. BReg.
3. DReg.
4. E Reg.
5. F Reg.
6. GReg.
7. HReg.
8. JReg.
9. KReg.
10. L Reg.
11. MReg.
12. NReg.
13. P Reg.
14. QReg.
15. RReg.
16. SReg.
17. T Reg.
18. U Reg.
19. V Reg.
20. WReg.
21. X Reg.
22. VFL and Decoder Reg, Mod. 70
23. Direct Data Reg
24. MC Reg.
S/360 MODEL 30
RA
RB
RD
RE
RF
RG
RH
G.
Main Storage Registers and Controls
in CPU (Includes SDR Registers,
Storage Busses, SAR, SBI "OR", M
and N Regs in Mod. 30)
MA-MC
Controls
1. Advance or Seq Cntis
2. Branch and IC Cntis
3. Clock Cntis
4. 1 Exec (Mod 70) 1 Fetch &
Exec (Mod. 60)
5. Chan Cntrls
6. Fix Seq Cntis
7. Gen Reg Cntis
8. FLT Cntis
9. ROS Cntis
10. Local Store Cntis
11. Priori1
Termlnate/f
Terminate/.
Terminate/';:
@
Terminote/$
Terminate/"
Any Other
•
Printer
0
1
2
3
~
@
X84
08421
X8421
Cord
0
1
2
3
K
Q
Q
R
0-8-2
11-8-2
0-8-2
11-8-2
Blank/@
R
Terminate/Z
Terminate/W
Blank/@
Blan
0-8-7
12-8-7
Blank *
Terminate/G
Terminate/X
~::;~::~(2)
~
~
5
g
~
Notes: 1. If an ,nvalid input choracter is
encountered, the read-check
indicator (06) is turned on.
2. If on invalid output choracter
is encountered, the writecheck indicator (07) is turned
~
3. An x denotes any hexadecimal
character except 0 or 5.
1620
Compo!
1620
Char
Blank
,
Printer
Digit (Hex)
Typewriter
00
02
03
04
10
12
Blank
Blank
None
None
"
CX084
&
None
CXO
None
13
$
$
CXS21
X84
X
COl
None
None
None
(0821
%
084
(0842
821
C84
Card
21
22
23
24
26
33
34
35
41
50
51
61
62
70
71
OA
'it
A ..• J
J ... R
5 ... Z
0
1. .. 9
DB
,A
None
· .49
· .59
~o~~1
~~~~I
J ... R
None
· .69
· .79
®
56
OF
,F
5F
ill
@
None
#
@
None
"5A
•
Poper Tope
00
CV Any Other
5 ... Z
0
1. .. 9
,
None
None
None
"
.
,
None
None
'
Any Other
•
XOI •• eXOOI
CXI .. XBl
5 ... Z
CO2 .. 081
0
I .. C81
082
o or
12 - 0
1. .. 9
B -2orO-8-2
11 - 8 - 2
None
None
11 - B-2
None
0-8 - 7
None
12 - 8 - 7
Any Other
None
None
None
None
X82
None
08421
None
XB421
Blank
Blank
Blank
"
"
/
~
%
Blank
#
@
@
A ... J
5
A ••• J
1403 HN
Blank
Blank
>
~
~
>
/
/
Blank
Blank
iBlank
%
Blank
iBlank
@
@
A ... J
0
A ... J
A .•. J
0-8-2
•
1403 AN
0-8-2
11-8-2
$
#
~"
2
-
~
CO
~
c
~
ll-O
None
J ... R
None
Blank
1443
&
None
None
Card
Typewriter
Blank
None
X0821
14
20
Invai
Input
Inva id
Output
OUTPUT
INPUT
Feature
8e
~
J ... R
Z
J ... R
J ... R
J ... R
J ... R
~
e
5 ... Z
0
1. .. 9
5 ... Z
0
1. .. 9
5 ... Z
0 \
I .. 9
5 ... Z
0
1. .. 9
5 ... Z
0
1. .. 9
0
Terminate
Terminate
Terminate
Terminate
Terminate
Terminate
Terminate
Terminate
Terminate
0-8 - 2
0-8 - 2
0-8 - 2
0-8 - 2
11 - 8 - 2
11 - 8 - 2
0-8 - 7
0-8 - 7
12 - 8 - 7
Terminate
Terminate
Terminate
Terminate
Terminate
Terminate
Terminate
Terminate
Terminate
Blank
Blank
Any Other
•
~
>
~
ADDRESS CONVERSION
Converting 1620 Decimal Addresses to 1620-Mode Hexadecimal Addresses
a
b
d
c
1620 Digit
1620
Note
Address
1.
(Dec. )
00000/2 =
00843/2 =
19999/2 =
00000
00421
09999
a
(0)
(1)
(1)
f
e
1620
Address
(Dec.)
00000/8 =
00843/8 =
19999/8 =
0000
01AS
270F
Address
20K
Constant
(Hex.)
+ OEOO =
+ OEOO =
+ OEOO =
OEOO (h;gh)
01A5 (law)
350F (law)
20K
Constant
Address
+ 3600 =
+ 3600 =
+ 3600 =
3600, b;t 0
3669, b;, 3
3FC3, b;t 7
g
1620 Flag
Note
2.
00000
00105
02499
(0)
(3)
(7)
0000
0069
09C3
(Hex.)
Note 1: If there is a remainder, the digit portion of this 1620 character is placed
in the four high-order bits of the 2030 byte.
Note 2: The remainder of this division identifies the bit-position within the flag
byte.
Converting 1620-:\Iode Hexadecimal Effective Addresses to Actual 1620
Decimal Addresses (Digit and Flag Portions)
k
m
1620 D;g;t
Address
(Hex.)
20K
OEOO (h;gh)
OFA5 (law)
350F (law)
- OEOO =
- OEOO =
- OEOO =
3600, b;, 0
3669, b;, 3
3FC3, b;t 7
Note
1.
Constant
r
1620
Flag-Byte
Address
(Hex.)
p
n
0000
01A5
270F
00000
00421
09999
s
,
x2=
x 2:::
x 2=
00000 +0=
00842 +1=
19998 + 1 =
Ac'ual 1620
Address
(Decimal)
00000
00843
19999
u
Actual 1620
20K
Constont
Note
2.
- 3600 =
- 3600 =
- 3600 =
00000 +0=
00840 +3=
19992 +7=
0000
0069
09C3
00000
00105
02499
x8=
x8=
x8=
Address
(Decimal)
00000
00843
19999
Note 1: Add J if the 1620 address was contained in the low-order four bits of the
2030 d;g;, by,e.
Note 2: Add the bit-position number that represents the flag-bit's location within
the fl ag byte.
S/360 MODEL 30
65
/
ADDITIVE CARD CODE (ACC)
(ALD FEATURE ASSIGNMENTS)
Feature
Code
Basic
ADA
1051 Attachment
ADFT
1051, First on Line
ADLT
1051, Last on Line
BAE3
Basic to Board B-E3
CBSI
1401/1440/1460 Basic Compatibility
CHC
Channel to Channel Adapter
DCT
Direct Control
EIC
External Interrupt
SCO
Selector Channel, First
SCI
Selector Channel, Second
SCO*
No Selector Channel, Second
STO
Storage SK
Model C
STI
Storage 16K
Model D
ST2
Storage 32K
Model E
ST3
Storage 64K
Model F
STCO
Storage Protect and Sel Ch, First
STCI
Storage Protect and Sel Ch, Second
STP
storage Protection
TIM
Interval Timer
HSMX
High Speed MPXR Ch
HMCO
High Speed MPXR Ch or Sel Ch, First
HMCI
High Speed MPXR Ch or Sel Ch, Second
66
S/360 MODEL 30
ROS PAGE ASSIGNMENTS
QA001
QA161
QA261
QA311
QA411
-
QA151
QA251
QA301
QA401
QA501
QA511 - QA751
QA 761 - QA851
QA861
QB001
QB261
QB611
QC001
QC021
QC511
QC911
QC931
QD001
-
QA991
QB251
QB601
QB991
QCOll
QC501
QC901
QC921
QC991
QD301
Instruction Cycles
Branches, Storage Protect
Converts
Shifts
Fixed Point Arithmetic, Logics, Sign Ctrl.
Load, Store, Mple Load, Mple Store.
Fixed Point Multiple and Divide
Storage to Storage Moves and Logics, Pack
Unpack, Move With Offset, Translate,
Translate and Test
PSW and mise forced address routines
Decimal Option (* 19-21)
Floating Point Option (*33-37)
Micro-Diagnostics
Decoding of I/O OP Codes
Multiplex Channel
1050 Console and Features (*22-23)
Direct Control Feature
Unassigned
Selector Channel (*24-26)
1400 COMPATIBILITY -- ROS PAGE ASSIGNMENTS
QE001 - QE401
QE411 - QE501
QE511 - QE991
Instruction Cycle and Index
I/E Change
Trap and Interrupt Routine, Mode Switch
and Stops
QF001 - QF151
Multiply and Divide
QF161 - QF251
Edit
Add, Suh, and Compare
QF261 - QF401
QF411 - QF651
Moves, Loads, Set WM, Clear WM, Move
Record, Move and Zero Suppress, Move
Zone, Move Digit, Move Column Binary,
Reset Add and Suh.
QF661 - QF801
Branches
QF811 - QF991
Clear, Store Stars, Modify Address
QG001 - QG101
I/O Common
1050 Typewriter (*74-75)
QGll1 - QG251
1442 - 1443 (*71-73)
QG261 - QG501
1402 - 1403 (*71-73)
QG511 - QG751
QG761 - QG991
Tapes on Multiplex Channel (*76-78)
QH001 - QH251
Tapes on Selector Channel (* 76-78)
QH261 - QH751
Files (*79-84)
*DENOTES CROSS BOARD LOCATION
1620 COMPATIBILITY -- ROS PAGE ASSIGNMENTS
QJ001 - QM991
QP001- QP491
1620 Compatibility
Sterling
S/360 MODEL 30
67
)
ROS FEATURE ASSIGNMENTS
FEATURE
VERSo #
000
001
002
003
004
005
006
007
008
009
010
011
012
013
Basic (Leave Version Blank on basic pages)
8K Storage
16K Storage
32K Storage
64K Siorage
224 UCW's (Available only with 32K or 64K Storage)
Storage Protect
Decimal Option
Floating Point Option
Direct Control
1050 Console (Addr. IF unless Ver 012 or 013)
Audible Alarm for 1050
1050 Console w/Addr. 5F (Only w/16K, 32K, 64K)
1050 Con. w/ Addr. DF (Only w/32K, 64K,
& 224USW's)
Selecior Channel #1
Selecior Channel #2
1401 Compatibility
Tapes on Multiplex Channel
Tapes on Selecior Channel
1442 - 1443
1402 - 1403
Column Binary
1050 Console for 1401 Compatibility
Program Mode Switching
Files
50 Cycle (Int. Timer)
Sterling Feature
Period - Comma inversion feature
014
015
016*
017*
018*
019*
020*
021*
022"
023'
024*
025
026*
027*
028
029
030
031
032
033
034
035
036
037
038
039
040
1620 Compatibility
041
906
Storage Protect Diagnostic
914
Selector Channel Diagnostic
995
Local Storage Dump
996
R/W Storage Diagnostic 1. 5 us
997
Multiplex Channel Diagnostic
998
R/W Storage Diagnostic 2. 0 us
Available only as part of 1401 Compatibility Feature
*
68
S/360 MODEL 30
COMBINATION VERSION ASSIGNMENTS
VERSo
,00
AOI
A02
A03
A04
A05
A06
A07
\08
A09
AID
All
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
003,
004,
006,
014,
006,
006,
006,
001,
014
014
014
015
010
010, 0]2
010, 013
010
010,
005,
010,
010,
016,
016,
003,
004,
016,
001,
004,
004,
004,
004,
004,
016,
014,
005,
005,
005,
010,
007,
005,
010,
008,
018,
016,
016,
018,
021,
016,
016,
018,
014,
020,
018,
002,
021,
020,
019,
020,
018,
018,
017,
018,
018.
019,
013
006
011
012
023
025
005
005
026
006
006
006,
010,
010,
006,
027
030
010,
010,
010
011,
010
006,
011,
014
022
020
018
020
026
019
024
024
025
021
019
014
027
022
022
024
020,
023
023
026
019,
024
32K and Selr Chan #1
64K and Selr Chan #1
Storage Prot and Selr Chan #1
Selr Chan #1 and Selr Chan #2
Storage Prot, 1050 Console
Storage Prot, 1050 Console, Addr 5F
Storage Prot, 1050 Console, Addr DF
8K and 1050 Console
1050 Console, Addr DF
224 UC\\.'Ts*. Storage Prot
1050 Console, Audible Alarm
1050 Console, Addr 5F
1401 Compatibility. Prog Mode Switch
1401 Compatibility. 50 Cycle
32K and 224 DeW's
64K and 224 uew's
1401 Compatibility and Sterling Feature
32 UCW's* and Storage Prot
64K and Storage Prot
010, 012 64K and Storage Prot and 1050 Con. Addr 5F
012
64K and 1050 Console Addr 5F
64K and 1050 Console, Addr DF
013
010, 013 64K Storage Prot, 1050 Can., Addr DF
1401 Compatibility and period-comma inversion
Sel Chan #1, Hi Speed MPX Channel
013
224 UCW's, 1050 Console Addr DF
012
224 UCW's, 1050 Console Addr 5F
224 UCW's 1050 Console
012
1050 Aud Alarm, Adr. SF
Decimal, 1050
010
224 UCW' s, Storage Protect, Decimal
013
1050, Aud. Alarm, Addr. DF
Floating point, Sel. Channel #1
Tapes on Sel. Channel, 1050 col sole 1401
1401 Compatibility, 1402 - 1403
1401 Compatibility. Tapes on Sel. Channel
Tapes on Selector Channel, 1402 - 1403
Col. Binary, Sterling
1401 Compatibility, 1442 - 1443
1401 Compatibility. File
Tapes on Selector Channel, File
Selector Channel, 50 cycle
1402 - 1403, Col. Binary
Tape on Selector Channel, 1442 1443
16K and Selector Channel #1
Column Binary and Period, Comma Inversion
024
024
S/360 MODEL 30
69
)
COMBlNA TION VERSION ASSIGNMENTS
(continued)
*
32
uew's
means 8K (Ver 001)
96 DeW's means 16K 32K, or 64K without additional
(Ver 002, 003, or 004)
224 uew's means 32K, or 64K with additional
(Ver 002, 003, or 004 combined with 005)
Dew
uew option
option
Version -It can be located in CLD 1. D. Block, extreme right hand
bottom corner.
ALD VERSION ASSIGNMENTS
000
001
002
003
004
005
008
009
Basic
Retry (EC 126837)
Retry and Board )lA-E3 (see note)
Retry and 1. 5 us memory
1. 5 us memory
Conversion of )lB-E3 to )lA-E3
1..5 us memory and board )lA-E3
Retry, 1. 5 us memory and board )1A-E3
101
102
103
104
105
106
107
1620
1620
1620
1620
1620
RPQ
RPQ
200
RPQ 881650
Compatibility
Camp with 1. 5 us memory and without )lA-E3
Comp, 1. 5 us memory and )lA-E3
Camp and )lA-E3
Camp and 1. 5 us memory
E41376 - External Alarm Control
W12097 - Remote Interrupt
RPQ VERSION ASSIGN:vrENTS
No,
Description
101
102
RPQ W12173 - Branch on Zero
RPQ E39692 - 1050 Addr 09 (32K mach wlo 224
UCW's only)
RPQ W12378 - Provide 7th tape dr on Sel Chan
(1400 Compat)
RPQ E42126 - A Bit Compat (No charge)
RPQ F13141 - Group Mark Compat
RPQ W14479 - Branch on Column Binary
RPQ F14421 - Character Insert on Read Validity Error
Branch on Zero indicate with Compare Digit Only
Move Record to Lozenge Compat RPQ Y46595
RPQ E43217 - Putnam Fund
RPQ Y25092 - Inverse Move (WTC)
RPQ Y25108 - Inverse Move Compat
- Additional Index Registers
103
104
105
106
107
108
109
110
111
112
113
70
8/360 MODEL 30
RPQ COMBINED VERSIONS
No.
Description
HOI
J01
J02
J03
J04
J05
J06
J07
JOS
J09
JIO
Jll
J12
016-101-10S (logic only) (J14 & 016) (was J23)
01S-101 Tape Sel. Chan. & RPQ (Br. on 0)
023-101 PMS & RPQ (Br. on 0)
010-102 1050 & RPQ (1050 Addr.)
017-101 Tape :v1PX & RPQ (Br. on 0)
006-010102 Stor. Prot., 1050 & RPQ (1050 Addr.)
01S-103 Tape Sel. Chan. & RPQ (7th tape dr.)
020-104 1402 & A Bit Compat.
020-021-104 1402, Col. Bin, A Bit Compat.
020-1051402 & Group Mark Compat.
020-021-105 1402, col. bin., Group Mark Compat.
020-106 1402 & Branch on Col. Bin.
020-107 1402 & Character Insert on Read Validity
Error
016-106 Basic, 1402 & Branch on Col. Bin.
016-101 1400 and RPQ 101 (logic page only)
020-104-106-1071402, A Bit Compat., Branch on
Col. Bin., Char. Insert on Read Validity Error
020-106-1071402, Branch on Col. Bin, Char.
Insert on Read Validity Error
020-104-106 1402, A Bit Compat., Branch on Col.
Bin
101-10S Branch on Zero with Compat. Digit
016-10S Basic & Branch on Zero with Compat. Digit
(logic page only)
017-103 Tape MPX & RPQ 103 (logic only)
01S-10S Tape Sel. Chan., Branch on Zero with
Compat. Digit
017-10S Tape MPX, Branch on Zero with Compat.
Digit
014-040 1620 & Sel. Chan. (logic only)
016-110
016-112
01S-023-101
016-109
01S-019-103
020-101
020-10S
017-023-101
020-103
01S-020-103
016-113
020-110
J13
JI4
JI5
J16
J17
J1S
J19
J20
J21
J22
J23
J24
J25
J26
J27
J2S
J29
J30
J31
J32
J33
J34
J36
S/360 MODEL 30
71
)
DIGIT PUNCHES 1-7
ZONE
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PUNCHES
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12-9
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12-8-9
11-9
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12-8
12-11-9
11-8
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12-11-0-9
8
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12-0-0
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38
89
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70
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91
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12
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32
3A
33
38
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48
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68
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E
F
2821 PRINT HAMMER DRIVER LOCATIONS
Print
Position
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
74
Location
G-25
G-25
E-18
E-18
G-18
E-18
E-18
G-18
G-18
G-18
G-25
G-25
E-17
E-17
G-17
E-17
E-17
G-17
G-17
G-17
G-24
G-24
E-16
E-16
G-16
E-16
E-16
G-16
G-16
G-16
G-24
G-24
E-15
E-15
G-15
E-15
E-15
G-15
G-15
G-15
G-23
G-23
E-14
E-14
S/360 MODEL 30
Print
Position
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Location
G-14
E-14
E-14
G-14
G-14
G-14
G-23
G-23
E-13
E-13
G-13
E-13
E-13
G-13
G-13
G-13
G-22
G-22
E-12
E-12
G-12
E-12
E-12
G-12
G-12
G-12
G-22
G-22
E-11
E-11
G-11
E-11
E-11
G-11
G-11
G-11
G-21
G-21
E-10
E-10
G-10
E-10
E-10
G-10
Print
Position
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
Location
G-10
G-10
G-21
G-21
E-09
E-09
G-09
E-09
E-09
G-09
G-09
G-09
G-20
G-20
E-08
E-08
G-08
E-08
E-08
G-08
G-08
G-08
G-20
G-20
E-07
E-07
G-07
E-07
E-07
G-07
G-07
G-07
G-19
G-19
E-06
E-06
G-06
E-06
E-06
G-06
G-06
G-06
G-19
G-19
INTERFACE CONNECTOR CHART
D
0
B
2
3
4
5
6
7
8
9
10
11
12
13
9
•
+3
.
U
0
T
,
-3
9
0
Q
..
.
(,)
.. Q
•
+6
T
Q
•
0
G
J
0
• ,
.
+3
Q
0
T
0
• Q•
• Q•
+6
, Q
Q
0
Bus
Bus
Bus
Bus
Out P
Out ,0
Out 1
Out 2
Operational In
Status In
Address In
Bus
Bus
Bus
Bus
Bus
Out
Out
Out
Out
Out
Select In
Select Out
Address Out
Command Out
Suppress Ou'
3
4
5
6
7
Service In
Service Out
Signal
Q
-3
Q
CONNECTOR 2
Ground Shield
?
2
3
4
5
6
7
8
9
10
11
12
13
CONNECTOR 1
'"
CONNECTOR 1
Bus
Bus
Bus
Bus
In P
In f'J
In 1
In 2
Bus
Bus
Bus
Bus
Bus
In
In
In
In
In
3
4
5
6
7
CONNECTOR 2
Clock Out
Metering Out
Metering In
Request In
Hold Out
Operational Out
8/360 MODEL 30
75
/
2030 BOARD - LOCA TION
Console
76
8/360 MODEL 30
INPUT"
TWILIGHT ZONE
CIRCUIT
u;;-
Down
OUTPUT"
NORMAL
LIMITS
Un Down Un Down
AI
and - inverter
1.4
0.5
.3
3.0
AOI
and - or - inverter
2.0
0.9
.3
3.0
API
and - power - inverter
1.6
0.46
3.0
DCI
direct couplet-inverter 0.8
0.58
3.0
CIRCUIT FLYER
LOADED NOT LOADED
DELAY INS)
TURN ON TURN OFF
Nom· Max Nom* Max
T03 - AB
T03 - AA
25.0
35.0
21.0 35.0
T03 - AE
T03 - AD
34.0
60.0
21.0 32.0
0.3 T03 - AJ
T03 - AF
13.0
22.0
27.0 42.0
T05 - AB
T05 - AA
17.0
25.0
17.0 2S.0
}"
to
NONE
REMARKS
INV.
-~
-~
'"o
HPD
High powered driver
0.8
0.58
II
Isolating inverter
2.2
0.58
ID
SCR
2.0
LR
2.03
2.88
3.1 0.3
TIS - AA T15 - AE
0.0 to
505 - AH 505 - AS
0.3
17.0
-.-.~
.-~
SS5 - EG
Line sense amplifier
LTN
Line tenninator
1.8
PH
polarity }
1.4
XOR
Exclusive - OR
1.9
A
OR
- AND
+ OR
2.4
TD
Time delay
hold
data contr.
0
-
N
~-
17.0 ~5.0
40.0
50.0
--~-
-~-----
f-----
-
- -
LSA
25.0
._-
.-~-~
N
r--'-'
-----<--,-
506 - AN 506 - AK
_..
0.9
0.14
1.8
}"
T03 -_~
e----.~~.0.0 to
2.5 0.3
T03 - AI T03 - AP
2.0
* Varies with load etc. All values quoted are to upper limit of normal operation.
.
26.0
-~
IS.O
46.0
60.0
55.0
20.0
32.0 SO.O
40.0
64.0
._.
T03 - AC T03 - CE
545 - EA/SB
** All voltages quoted are positive (+).
(N.J.)
(N.I.)
(N.J.)
OE
---.-
DIAGNOSTICS
ICARD DESCRIPTION DMA4
Version 3 or higher
I SCT/DMI/O lEnd Card Minus 10)
Defines Loader- Input-Output Device (Users Guide)
I SCT-SRT (1st of 8 End Card Minus 8)
Defines System Configuration (Users Guide)
00
SCT-UDT lEnd Card Minus 15)
Defines I/o Equip on System (Users Guide)
IPL LOADER #1
1st Card DMA4 (Users Guide)
IPL LOADER #2
2nd Card DMA4 (Users Guide)
I ESD (1st Card Section Deck)
Gives Name, Origin, & Length of Program Section of Test Deck
'TXT (Follows IPL Loader 2)
Gives Text of Program in Monitor & Test Deck
IREP (Last Card Before RLD Crd)
Used to set Sense Switches, Used to Overlay Data (Users Guide)
RLD
Ignored DMA4
IDAT (Used in Place of LDT Cards)
Indicate to Monitor That Data Cards Follow-Must Proceed Each
Set of Data Cards. (Users Guide)
LDT (Last Card of Section Deck)
Load Terminate Card-If Missing Next Section Will Reject.
(Users Guide)
END - Ignored by DMA4
BLANK - Valid in DMA4
ILOAD DMA4 -
Users Guide (8400:34)
IHANG UP CONDITIONS DMA4 - Users Guide
1. If a section halts with an error, it can be restarted by depressing System Reset & hitting Start Key twice.
2. If a section halts with an error and you wish to bypass it,
hitting the Interrupt Key once will allow the machine to
continue from the point of error. Hitting the Interrupt Key
twice will terminate that section and start next section.
78
S/360 :vrODEL 30
SENSE SWITCHES D;vJ:A4
NUMBER
20
21
24
25
26
27
28
30
31
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
Dm Wi II Load Each Sect In Seq
Dm Will Halt After Each Sect
Short Format Error Msg's
Long Format Error Msg 's
Print All Msg S & T
Prevent Print S & T
No Halt After Error
Halt After Error
Nonmal
Cycle CE Run Request
Allow All Printing
Prevent All Printin!,)
No Cyc Prog Sect In Storage
Cycle Prog Sect In Storage
Print Error Msg's
Prevent Print Error Msg's
Nonmal DMA4 Output Msg Format
8 K System - No Effect 16 K or Larger Transfer Control to Message Editor to Print
DMA4 Messages
Each section has its won sense switch settings, they must be looked
up in section
SWITCH SETTINGS FOR CONSOLE OVERLAY DMA4
NORMAL
LOAD FROM
LOAD TO
EXECUTE
SW OFF
MONITOR
SECTION
SW ON
MONITOR
SECTION
CYCLE
ACTIVE
SELECT
PRINT SEC
PRINT MON
OUTPUT UNIT
ENTER SEC
ENTER MON
INITIALIZE
F
0
8
9
1
Do Not
Section
Section
Do Not
2
2
7 Sense Sw Number
8 Sense Sw Number
3
3
7 Sense Sw Number
8 Sense Sw Number
5
5
6
7
4
E
F
D
5 Do Not Care
6 Routine Number
Dump & Print Sect
Dump & Print Monitor
Ch Addr I/O Addr
To Change Section
To Change Monitor
Do Not Care
G
H
J
Care
Search Number
Search Number
Care
8/360 MODEL 30
79
)
ERROR MESSAGES DMA4
*PZZZL
*PZZZL CU
*DIO DMA4
*EIE
HLT
HLT PZZZL
*IOE
*ISC DMA4
*ISC PZZZL
*MCK DMA4
*MCKPZZZL
OIR
*PGM DMA4
*PGMPZZZL
PNF DMA4
REJ PZZZL
REL PZZZL
RNV PZZZL
S
PZZZL
SDO PZZZL
*SDO PZZZL
T
SVC Dl D2 Error Msg's
SVC D3 Error Msg
MonitDr I/O Error
External Interrupt Error
With Error Msg When Halt on
Error Indicated
SVC DA Halt Request
Prog Sect I/o Error
Invalid Supervisor Call
Interrupt Error in DM
Invalid Supervisor Call
Interrupt Error in Sect
Machine Check Interrupt
Error in Monitor
Machine Check Interrupt
Error in Section
Operator Intervention
Requested or Required
Program Interrupt
Error in Monitor
Program Interrupt
Error in Section
Program Not Found
Section Rejected
Reload
Requested Unit Not Found
Start of Section
Line. CPU is Optional
SVC DO Error ID Line
CUU is Optional
Terminal End of Section
T*
Abnormal Termination
*UIO PZZZL Unassigned I/O Interrupt Error
WTE DMA4 Wait Message
80
S/360 MODEL 30
SYSTEM/360 DIAGNOSTICS
Section #
32011
32021
32611
32621
32630
32640
32911
32921
32931
32E10
32E20
338FO
33900
33C90
34300
34470
344AO
34E10
F5011
F5022
F5032
F5042
F5051
F5061
F5071
F5081
F5091
F51A2
F51B2
F5211
F5221
F5231
F5241
F6002
F6011
F6021
F6031
F6041
F6051
F6061
F6071
F6081
F6091
F6101
F6111
F6121
F6131
Title
Search #
Standard Set 1 Sec 1
Standard Set 1 Sec 1
Standard Set 2 Sec 1
Standard Set 2 Sec 2
Standard Set 2 Sec 3
Standard Set 2 Sec 4
Float Point Section 1
Float Point Section 2
Float Point Section 3
Decimal Arith Sec 1
Decimal Arith Sec 2
Usage Meter
R/W Storage
Stor Prot
Chan Fnnction
Sel Chan 1 Fanlt Locating
Sel Chan 2 Fanlt Locating
Direct Ctrl
Tape Fnnction Sec 1
Tape Function Sec 2
Tape Function Sec 3
Tape Function Sec 4
Tape Function Sec 5
Tape Function Sec 6
Tape Function Sec 7
Tape Function Sec 8
Tape Function Sec 9
Error Detection Sec 1
CRC Generation Sec 1
ffiG (Write) Sec 1
ffiG (Read) Sec 2
ffiG (Write 8K) Sec 1
ffiG (Read 8K) Sec 2
2841/2311 Function Test
2841/2311 Function Test
2841/2311 Function Test
2841/2311 Function Test
2841/2311 Function Test
2841/2311 Function Test
2841/2311 Function Test
2841/2311 Function Test
2841/2311 Function Test
2841/2311 Function Test
2311 Diagnostic Test
2311 Diagnostic Test
2311 Diagnostic Test
2311 Diagnostic Test
201
202
261
262
263
264
291
292
293
2E1
2E2
38F
390
3C9
430
447
44A
4E1
501
502
503
504
505
506
507
508
509
51A
51B
521
522
523
524
600
601
602
603
604
605
606
607
608
609
610
611
612
613
S/360 MODEL 30
81
J
SYSTEM/360 DIAGNOSTICS
(continued)
Section iI
F8041
F8051
F8060
F8081
F8090
F80C4
F80D2
F8102
F8111
F8152
F8170
F8202
F8212
F8231
F8251
F8303
F8313
F8323
F8330
F8362
F8382
F8394
F83FO
F8500
F8510
F8520
F9000
F9010
F9020
*FOFF
*3FDO
*3FEI
*FCI
3447
Title
2821/2540 Reader Punch Scan
2821/2540 Buff Addr Test
2821/2540 Pnch Xlator Test
2821/1403 Non UCS Scan
2821/1403 Non UCS Scan
2821/1403 UCS Scan Rtn 1 & 2
2821/1403 UCS Scan Rtn 3 & 4
2540 Reader Function Sec 1
2540 Reader Function Sec 2
2540 Reader Col Bin
2540 Reader 14XX Mode
2540 Punch Function Sec 1
2540 Punch Function Sec 2
2540 Punch Feed Read
2540 Punch Col Bin
1403 Printer Function Test Sec 1
1403 Printer Function Test Sec 2
1403 Printer Function Test Sec 3
1403 Printer Function Test Sec 4
1403 Ripple Print
1403 Carriage Snse Channel 9 & 12
1403 Carriage Forms Space & Skip
1403 Selective Tape Lister
1404 Printer Function Test
1404 Printer Read Compare
1404 Printer Seq of Commds
1052 Basic op Test
1052 Mach Func Test
1052 Reader Keyboard Test
Tape Editor
I/O Exerciser
SEREP
8K Sys Test (SEVA)
Selector Channell Fault Locating
Search iI
804
804
804
808
80S
SOC
SOC
810
811
815
817
820
821
823
825
830
831
832
833
836
838
839
83F
850
851
852
900
901
902
OFF
FDO
FEI
FCI
447
* These programs are stand alone programs and will
not run with a monitor program.
82
S/360 MODEL 30
1401 COMPATIBILITY
Section II
3FOO
3F01
3F02
3F03
3F04
3F05
3F06
3F07
3F08
3F09
3FOC
3F10
3F13
3F16
3F19
3F1C
Title
Searchll
14XX Compatibility CPU
FOO
14XX Compatibility CPU Sec 1
F01
14XX Compatibility CPU Sec 2
F02
14XX Compatibility CPU Sec 3
F03
14XX Compatibility CPU Sec 4
F04
14XX Compatibility CPU Sec 5
F05
Prog Mode SW 1401 Compatibility F06
1402 Read-Punch 1401 Compat.
F07
1402 PFR 1401 Compatibility
F08
1402 Col Bin 1401 Compatibility
F09
1403 PRTR TST 1401 Compatibility FOC
1442 Read-Punch 1401 Compat.
FlO
1443 Bar Printer 1401 Compat.
F13
Mag. Tape Test 1401 Compat.
F16
F19
2311/1311 File Test 1401
Cons. Type Test 1401 Compat.
F1C
1620 COMPATIBILITY
Section II
3F40
3F41
3F42
3F43
3F44
3F45
3F46
3F47
3F48
3F49
3F4A
3F4B
3F4C
3351
Search II
Title
1620 Compatibility Feature
1620 Non Disk I/O
1620 Set Clear MV 20K Fig.
1620/360 Output Xlator
1620/360 Input Xlator
1620/360 Xlator Count
1620 CPU Tests
1620 Dsk Sk Cy Ovfl Ad Ck
1620 Init Rd Wr Chk Dsk
Rd Wr Chk Dsk 80K Sect
Disk Sect Data Movement
Disk Trk Data Movement
Set 40K & 60K 1620 Flags
1620 Micro Diagnostics
F40
F41
F42
F43
F44
F45
F46
F47
F48
F49
F4A
F4B
F4C
351
MISCELLANEOUS
Section II
3FC1
3FC2
3FDO
3FDl
3FE1
Search 1/
Title
Systems Test Description -ASystem Test Description -B3 Cd Hex Ldr & Gen 1-0 Ex
Ls Map Description
SEREP Description
FC1
FC2
FDO
FDl
FE1
S/360 MODEL 30
83
)
OPERATING PROCEDURE FOR SELECTOR CHANNEL FLT'8
Initialize the Tobie With
At least the Following:
Ve.
- Stol"Clge Protect Availability
- Moin Storoge Size
- DM Sense Switches
- loader Devi ce
- Output Device (See Note)
See User's Guide
NOTE:
The Output Device Cannot be Attached to the
Channel Under Test. If
it is, Refer to the Description, POl"Clgl"Clph 5.3.
See Page 1 of
10-3340
2030 Gote "G"
Test light
is Off
"X" is Current
Revision level
of FLT
"X" is Channel
Number
84
8/360 MODEL 30
OPERATING PROCEDURE FOR SELECTOR CHANNEL FLT'S
(oontinued)
Console
Switches
FGHJ Set
to 5601
Console
Switches
FGHJ Set
to 5600
No
* Description for SEL CHNL I: 103447
Description f?r SEL CHNL 2: 10344A
S/360 MODEL 30
85
)
CHART A
DMA4 OPERATOR'S FLOW CHART
NORMAL START
IDMA4
-I Description
l~:i·!...
___ _
:System/360
-IMod 30 User's
I Guide Section
t.:i:!!'.5"!!..~~t_
tions and can be
found under the
following program listing
headings;
1. DM Section
Reference
Tobie
Hex Loc 180
2. DMAI-O
Unit Definition Table
3. DMA Unit
Definition
Table
~ ~;~e~&~s~r's
n~~i~o~:t~on
I IInterrupt
: ~~~g~s__ _
I
I
I
J
86
8/360 MODEL 30
CHART B
DMA4 OPERATOR'S FLOW CHART
S/360 MODEL 30
87
J
CHART C
DMA4 RESTART PROCEDURES
1. The DMA4 restort PSW is loco ted ot locotion 0 ond ollows the operotor
to return to 0 predetermined point.
2. If the following method is followed, the need for reloading DMA4 will
be minimized.
88
5/360 :.10DEL 30
INITIALIZE OUTPUT MESSAGE OF DMA4
Any additional I/O units can be inserted into the
UDT starting at the specified address. Address in
this exam Ie is OlEO.
DM I/O units taken from DMIO card or
as implied by having the DMIO cord blank.
NOTE: It is recommended that the DMIO
card be left blank. If blank DMA4 will
assign:
1. LOADER - rPL Unit
2. OUTPUT - First 1052, 1403, 1443, 1404
found in the UDT
3. INPUT - 1052, 2540, 1442 in the above
order if in the UDT
Verifies the CPU options punched into
theSRTcard
31st
JJuI
tot~'J
Stocog.
po;otocCode)
whkhofpo;,"
first byteodd""
(Prog-Unit
each unit
definition table entry.
AVAIL
Program Unit Type
Channel and Unit Address
Optional Feature Digits
1. A two in this position indicates that the unit has been withdrawn from the UDT tobie, and will not
be assigned to any program section.
I
2. To withdraw any unit from the UDT, store a two in this position of the corresponding UOT entry.
( Example: Withdraw the 1052. Stare into loc 0102 A 20)
3. To add a withdraw unit, remove the two from that unit's UDT entry.
( NOTE: If loading from tape, never remove the two from the load device)
8/360 MODEL 30
89
/
INDEX
ADDITNE CARD CODE.
ADDRESS CONVERSION.
ADDRESS MARK BIT CONFIGURATION.
ADDRESSES - SUGGESTED STANDARD.
ADDRESSING - MAIN STORAGE
ADDRESSING - ROS BLOCK DIAGRAM.
ADDRESSING - ROS CARD POSITIONS .
ADDRESSING OF UCW - I/O FORMAT.
ALD PAGE NUMBER PREFIX DEFINITIONS.
ALPHAMERIC INPUT/OUTPUT CODES & GRAPHICS
ALU CONTROLS . . . . . . . . . . . .
ARRAY LAYOUT . . . . . . . . . . . .
BIT ASSIGNMENTS FOR BYTES IN 1400 BUMP.
BOARD LOCATION - 2030 .
CHANNELS - MPX. . . .
CHANNELS - SEL. . . .
CHANNEL STATUS WORD.
DATA FLOW SYSTEM/360 MOD 30
DATA FLOW/TIMING MULTIPLEX CHANNEL
MICRO-PROGRAM . . . . . . . . .
DIAGNOSTICS - 1401 COMPATIBILITY DIAGNOSTICS
DIAGNOSTICS - CARD DESCRIPTION - STOP
CONDITIONS. . . . . . . . . .
DIAGNOSTICS ERROR MESSAGES DMA4
DIAGNOSTICS - LISTING . . . . . .
DIAGNOSTICS - SENSE SWITCHES DMA4
DIODE LAYOUT - 32K ARRANGEMENT.
DIODE PACK - PIN 2391181
DISK FORMA T CHANGES . . . . . .
DMA4 ERROR MESSAGES. . . . . .
DMA4 INITIALIZE OUTPUT MESSAGE.
DMA4 RESTART PROCEDURES. . . .
DMA4 SENSE SWITCHES . . . . . .
DMA4 SWITCH SETTINGS FOR CONSOLE OVERLAY
EBCDIC HEXIDECIMAL CHART.
FUNCTIONAL DESIGNATIONS
H REGISTER . .
INITIALIZATION MESSAGES. .
INTERFACE CONNECTOR CHART.
K ADDRESSABLE BYTES - CPU .
K ADDRESSABLE BYTES 1400 COMPATIBILITY
LOCAL STORAGE - 1400 COMPATIBILITY
LOCAL STORAGE - CPU . .
LOGOUT CPU CHANNEL . . . . . . .
MACHINE CHECK REGISTER. . . . . .
MAIN ADDRESS REGISTER LAYOUT (M&N).
MAIN STORAGE ADDRESSING . .
MULTIPLEX CHANNEL CONTROL
MPX AND SX MICRO-PROGRAM .
M2I GATE AND SELECTION LOGIC
S/360 MODEL 30
. 66
. 65
. 15
. 45
. 9
. 10
. 10
. 30
. 52
. 64
. 25
. 4
. 50
.76
. 32
. 32
.18
.28
. 29
. 83
. 78
. 80
. 80
. 79
. 2
. 2
. 62
. 80
. 89
. 88
. 79
. 79
. 72
. 60
.25
. 62
. 75
. 13
. 51
.51
. 13
. 35
. 25
. 5
. 9
.32
. 36
91
J
INDEX
NUMERIC INPUT/OUTPUT CODES & GRAPHICS
OPERA TING PROCEDURE FOR SELECTOR
CHANNEL FLT'S . . . . . . . . . . .
OPERATOR'S FLOW CHART . . . . . . . ' .
ORIENTA TION OF DIODE PACK (BY DIODE iI) •
PLUG CHART - Bl BOARD .
PLUG CHART - B2 BOARD .
POWER RESISTOR LOCATION
PROGRAM STATUS WORD. .
READ ONLY STORAGE CONTROL.
REGISTER DISPLAY AND FUNCTION
REGISTERS S, MC, H . . . .
ROS CONTROL FIELD CHANGES . .
ROS CONTROL FIELD CHART . . .
ROS CONTROL FIELD DESCRIPTION
ROS FEA fURE ASSIGNMENTS
ROS MICRO-WORD FORMAT.
ROS PAGE ASSIGNMENTS. .
ROS PARITY CHECK BITS. .
ROS ROUTINE START ADDRESS
ROS TRAPS IN PRIORITY ORDER.
ROUTINE POINTERS. . . . .
RPQ COMBINED ASSIGNMENTS. .
RPQ VERSION ASSIGNMENTS . .
SELECTOR-CHANNEL CONTROL.
SPECIFICATION OF SLT MODULES FOR SYSTEM/360
MODEL 30 CPU. . . .
STA TUS REGISTER . . .
SYSTEM/360 DIAGNOSTICS
TRAP ADDRESSER. . . .
UNIT CONTROL WORD. .
WORD - CHANNEL STATUS
WORD - PROGRAM STATUS.
WORD - UNIT CONTROL . .
1050 INTERFACE REGISTERS
1400 COMPATIBILITY CONSOLE INQUffiY STATION.
1400 COMPATIBILITY - K ADDR. BYTES. . . . .
COMPA TIBILITY - LOCAL STORAGE . . . . . .
l400 COMPATIBILITY - PROGRAMMED AND ERROR
STOPS . . . . . .
1400 d MODIFIERS. . . . . . .
1400 OPERATION CODES . . . .
1401 CODE TO SYSTEM/360 CODE
1620 COMPATIBILITY . . . . .
1620 OP CODES. . . . . . . .
1620 PROGRAMMED AND ERROR STOPS .
2311/2841 FORMATS. . . . . . . . .
2821 HEX TO BCD TRANSLATION. . . .
2821 PRINT HAMMER DRIVER LOCATION
92
S/360 MODEL 30
. 63
. 84
.86
3
6
3
. 17
.20
. 38
.25
. 59
. 27
. 27
. 68
.26
. 67
. 12
. 19
. 19
. 61
. 71
.70
. 32
. 77
. 25
. 81
. 19
. 31
.18
.17
. 31
. 37
.40
. 51
. 51
.46
.42
.41
.44
.83
.53
.55
.14
.73
.74
CUT ALONG DOTTED LINE
IBM Field Engineering Handbook, System/360 -- Model 30, Form 229-2116-2
From _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Office No. _ _ _ _ _ __
Circle one of the comments and explain in the space provided:
Suggested Addition (page _ ) Suggested Deletion (page _ )
Explanation:
Error (page_)
-'~-'---'------------------------'-------------.-
FIRST CLASS
PERMIT NO. 10
ENDICOTT, NEW YORK
BUSINESS REPLY MAIL
NO POSTAGE STAMP
NECESSARY IF MAILED
IN
POSTAGE W ILL BE PAID BY
IBM Corporation
FE Technical Operations
Endicott, New York 13760
Attn: Department 793
U.S.A.
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