Evaluation Platform Board Manual IQ80960RM 27316003
User Manual: Evaluation Platform Board Manual IQ80960RM
Open the PDF directly: View PDF 
.
Page Count: 86
| Download | |
| Open PDF In Browser | View PDF |
IQ80960RM/RN Evaluation Platform Board Manual September 1998 Order Number: 273160-003 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The IQ80960RM/RN may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners. IQ80960RM/RN Evaluation Platform Board Manual Contents 1 Introduction ......................................................................................................................................1-1 i960® RM/RN I/O Processor and IQ80960RM/RN Features .....................................................1-3 Software Development Tools.....................................................................................................1-3 IxWorks Software Development Toolset....................................................................................1-4 1.3.1 IxWorks Real-Time Operating System .........................................................................1-4 1.3.2 TORNADO Build Tools .................................................................................................1-4 1.3.3 TORNADO Test and Debug Tools ...............................................................................1-4 CTOOLS Software Development Toolset..................................................................................1-5 1.4.1 CTOOLS and the MON960 Debug Monitor ..................................................................1-5 1.4.1.1 MON960 Host Communications...................................................................1-5 1.4.1.2 Terminal Emulation Method .........................................................................1-5 1.4.1.3 Host Debugger Interface (HDI) Method .......................................................1-5 About This Manual.....................................................................................................................1-6 Notational-Conventions .............................................................................................................1-7 Technical Support......................................................................................................................1-8 1.7.1 Intel Customer Electronic Mail Support ........................................................................1-8 1.7.2 Intel Customer Support Contacts..................................................................................1-8 1.7.3 Related Information ......................................................................................................1-9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 Getting Started.................................................................................................................................2-1 2.1 2.2 Pre-Installation Considerations..................................................................................................2-1 Software Installation ..................................................................................................................2-1 2.2.1 Installing Software Development Tools ........................................................................2-1 Hardware Installation .................................................................................................................2-2 2.3.1 Battery Backup .............................................................................................................2-2 2.3.2 Installing the IQ80960RM/RN Platforms in the Host System........................................2-2 2.3.3 Verify IQ80960RM/RN Platform is Functional ..............................................................2-2 Creating and Downloading Executable Files .............................................................................2-3 2.4.1 Sample Download and Execution Using GDB960........................................................2-3 2.3 2.4 3 Hardware Reference........................................................................................................................3-1 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 Power Requirements .................................................................................................................3-1 SDRAM......................................................................................................................................3-1 3.2.1 SDRAM Performance ...................................................................................................3-2 3.2.2 Upgrading SDRAM .......................................................................................................3-3 Flash ROM.................................................................................................................................3-3 3.3.1 Flash ROM Programming .............................................................................................3-3 Console Serial Port....................................................................................................................3-4 Secondary PCI Bus Expansion Connectors ..............................................................................3-4 3.5.1 PCI Slots Power Availability..........................................................................................3-4 3.5.2 Interrupt and IDSEL Routing.........................................................................................3-5 Battery Backup ..........................................................................................................................3-5 Loss of Fan Detect.....................................................................................................................3-5 Logic Analyzer Headers.............................................................................................................3-6 JTAG Header.............................................................................................................................3-7 User LEDs .................................................................................................................................3-8 3.10.1 User LEDs During Initialization .....................................................................................3-8 IQ80960RM/RN Evaluation Platform Board Manual iii 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 5 5.1 5.2 5.3 5.4 5.5 i960® RM/RN I/O Processor Overview ............................................................................................4-1 CPU Memory Map .....................................................................................................................4-2 Local Interrupts ..........................................................................................................................4-3 CPU Counter/Timers .................................................................................................................4-5 Primary PCI Interface ................................................................................................................4-5 Secondary PCI Interface ...........................................................................................................4-5 DMA Channels ..........................................................................................................................4-6 Application Accelerator Unit ......................................................................................................4-6 Performance Monitor Unit..........................................................................................................4-7 MON960 Support for IQ80960RM/RN .............................................................................................5-1 Secondary PCI Bus Expansion Connectors ..............................................................................5-1 MON960 Components ...............................................................................................................5-1 5.2.1 MON960 Initialization ...................................................................................................5-1 5.2.2 80960JT Core Initialization ...........................................................................................5-2 5.2.3 Memory Controller Initialization ....................................................................................5-2 5.2.4 SDRAM Initialization .....................................................................................................5-2 5.2.5 Primary PCI Interface Initialization................................................................................5-3 5.2.6 Primary ATU Initialization .............................................................................................5-3 5.2.7 PCI-to-PCI Bridge Initialization .....................................................................................5-4 5.2.8 Secondary ATU Initialization ........................................................................................5-4 MON960 Kernel.........................................................................................................................5-5 MON960 Extensions..................................................................................................................5-5 5.4.1 Secondary PCI Initialization..........................................................................................5-5 5.4.2 PCI BIOS Routines .......................................................................................................5-6 5.4.2.1 sysPCIBIOSPresent.....................................................................................5-6 5.4.2.2 sysFindPCIDevice........................................................................................5-7 5.4.2.3 sysFindPCIClassCode .................................................................................5-7 5.4.2.4 sysGenerateSpecialCycle ............................................................................5-8 5.4.2.5 sysReadConfigByte......................................................................................5-8 5.4.2.6 sysReadConfigWord ....................................................................................5-9 5.4.2.7 sysReadConfigDword ..................................................................................5-9 5.4.2.8 sysWriteConfigByte....................................................................................5-10 5.4.2.9 sysWriteConfigWord ..................................................................................5-10 5.4.2.10 sysWriteConfigDword.................................................................................5-11 5.4.2.11 sysGetIrqRoutingOptions ...........................................................................5-11 5.4.2.12 sysSetPCIIrq ..............................................................................................5-12 5.4.3 Additional MON960 Commands .................................................................................5-12 5.4.3.1 print_pci Utility............................................................................................5-12 Diagnostics / Example Code ...................................................................................................5-12 5.5.1 Board Level Diagnostics .............................................................................................5-12 5.5.2 Secondary PCI Diagnostics ........................................................................................5-12 A Bill of Materials............................................................................................................... A-1 B Schematics..................................................................................................................... B-1 C PLD Code....................................................................................................................... C-1 D Recycling the Battery ..................................................................................................... D-1 iv IQ80960RM/RN Evaluation Platform Board Manual Figures 1-1 1-2 3-1 4-1 4-2 4-3 4-4 4-5 IQ80960RM/IQ80960RN Platform Functional Block Diagram ...................................................1-1 IQ80960RN Platform Physical Diagram ....................................................................................1-2 LED Register Bitmap .................................................................................................................3-8 i960® RM/RN I/O Processor Block Diagram..............................................................................4-1 IQ80960RM/RN Platform Memory Map .....................................................................................4-2 i960® RM/RN I/O Processor Interrupt Controller Connections ..................................................4-4 i960® RM/RN I/O Processor DMA Controller ............................................................................4-6 Application Accelerator Unit.......................................................................................................4-7 Tables 1-1 1-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 5-1 A-1 A-2 B-1 B-2 Document Information ...............................................................................................................1-9 Cyclone Contacts.......................................................................................................................1-9 IQ80960RN Platform Power Requirements...............................................................................3-1 IQ80960RM Platform Power Requirements ..............................................................................3-1 SDRAM Performance ................................................................................................................3-2 SDRAM Configurations..............................................................................................................3-3 UART Register Addresses.........................................................................................................3-4 Secondary PCI Bus Interrupt and IDSEL Routing .....................................................................3-5 Logic Analyzer Header Definitions.............................................................................................3-6 JTAG Header Pinout..................................................................................................................3-7 Switch S1 Settings.....................................................................................................................3-7 Start-up LEDs MON960.............................................................................................................3-8 IQ80960RM/RN Connectors and LEDs .....................................................................................3-9 Initialization Modes ....................................................................................................................5-3 IQ80960RN Bill of Materials ..................................................................................................... A-1 IQ80960RM Bill of Materials ..................................................................................................... A-5 IQ80960RN Schematics List..................................................................................................... B-1 IQ80960RM Schematics List .................................................................................................... B-2 IQ80960RM/RN Evaluation Platform Board Manual v 1 Introduction This manual describes the IQ80960RM and IQ80960RN evaluation platforms for Intel’s i960® RM/RN I/O processor. The i960 RM/RN I/O processors combine an 80960JT core with two PCI bus interfaces, as well as a memory controller, DMA channels, an interrupt controller interface, and an I2C serial bus. The difference between the two processors is that the 80960RN utilizes 64-bit primary PCI and secondary PCI buses while the 80960RM utilizes both a 32-bit primary and secondary PCI bus. The IQ80960RM and IQ80960RN platforms are full-length PCI adapter boards and are 8.9” in height to accommodate four standard PCI connectors on the secondary PCI bus. The boards can be installed in any PCI host system that complies with the PCI Local Bus Specification Revision 2.1. PCI devices can be connected to the secondary bus to build powerful intelligent I/O subsystems. Figure 1-1. IQ80960RM/IQ80960RN Platform Functional Block Diagram Secondary PCI Slot 4 Secondary PCI Slot 3 Secondary PCI Slot 2 Secondary PCI Slot 1 Console Port SDRAM (x72) Battery Backup Support RS-232 Serial Port User LED Logic Analyzer Interface Flash ROM i960® RM/RN Secondary PCI I/O Processor Bus 32/64-bits Logic Analyzer Interface UART LED Register ROM Bus Primary PCI Bus 32/64-bits IQ80960RM/RN Evaluation Board Manual 1-1 Introduction Figure 1-2. IQ80960RN Platform Physical Diagram 64-Bit Secondary PCI Slots 168-Pin SDRAM DIMM Socket J4 J3 J2 RS-232 Serial Port J1 Flash Memory J5 SW1 J10 J11 J12 OFF J9 1234 J8 CR1 J6 CR2 CR3 CR4 CR5 J7 U9 U11 JTAG Port i960® U15 Logic Analyzer Connectors 1-2 64-Bit PCI NiCd Batteries IQ80960RM/RN Evaluation Board Manual Introduction 1.1 i960® RM/RN I/O Processor and IQ80960RM/RN Features The i960 RM/RN I/O processor serves as the main component of a high performance, PCI-based intelligent I/O subsystem. The IQ80960RM and IQ80960RN platforms allow the developer to connect PCI devices to the i960 RM/RN I/O processors using the four secondary PCI expansion connectors. The features of the IQ80960RM and IQ80960RN platforms are enumerated below and shown in Figure 1-1 and Figure 1-2. • • • • i960 RM/RN I/O processor Modified PCI long-card form factor 64-bit or 32-bit primary PCI bus interface (80960RM 32-bit only) 64-bit or 32-bit secondary PCI bus connected to the primary PCI interface with a PCI-to-PCI bridge (80960RM 32-bit only) • DMA channels on both PCI buses • I2C Serial Bus • 168-pin, 3.3V DIMM socket supporting 16 to 128 Mbytes of Synchronous DRAM organized x72 to support Error Correction Code (ECC) and clocked at 66 MHz (ships with 16 M/ECC installed) • Serial console port based on 16C550 UART • Eight user-programmable LEDs • 3 Indicator LEDs: processor has passed self-test, 3.3 V is supplied to SDRAM, and 3.3 V is supplied to secondary PCI slots • • • • • 1.2 Flash ROM, 2 Mbytes Logic analyzer connectors for SDRAM bus, ROM bus and secondary PCI arbitration signals Fan heatsink monitor circuit Battery backup for SDRAM JTAG header Software Development Tools A number of software development tools are available for the i960® processor family1. This manual provides information on two software development toolsets: Wind River System’s IxWorks* and Intel’s CTOOLS. If you are using other software development tools, read through the information in this chapter and in Chapter 2 to gain a general understanding of how to use your tools with this board. 1. To view the electronic tools catalog, access http://developer.intel.com/design/develop.htm/ from the web. IQ80960RM/RN Evaluation Board Manual 1-3 Introduction 1.3 IxWorks Software Development Toolset IxWorks is a complete toolset featuring an integrated development environment including a compiler, assembler, linker, and debugger. It also features a real-time operating system. 1.3.1 IxWorks Real-Time Operating System The IQ80960RM/RN platforms are equipped with Wind River Systems, Inc.’s IxWorks. IxWorks provides for the elements of the I2O standard: an event-driven driver framework, host message protocols, and executive modules for configuration and control. IxWorks also allows for the writing of basic device drivers and provides NOS-to-driver independence. TORNADO for I2O provides a visual environment for building, testing and debugging of I2O drivers. 1.3.2 TORNADO Build Tools TORNADO for I2O includes a collection of supporting tools that provide a complete development tool chain. These include the compiler, assembler, linker and binary utilities. Also provided is an I2O module builder, which creates I2O-loadable modules. 1.3.3 TORNADO Test and Debug Tools TORNADO for I2O test and debug tools include the dynamic loader, the CrossWind∗ debugger, the WindSh* interactive shell, and a system browser. The dynamic loader allows for interactive loading, testing, and replacement of individual object modules that comprise a driver. CrossWind is an extended version of GDB960. Using it you can debug I2O drivers by setting breakpoints on desired I2O components. A variety of windows display source code, registers, locals, stack frame, memory and so on. WindSh allows you to communicate to the IQ80960RM/RN platform via an RS-232 serial port. The IQ80960RM/RN platform supports port speeds from 300 to 115,200 bps. The shell can be used to: • • • • control and monitor I2O drivers format, send and receive driver messages examine hardware registers run automated I2O test suites The shell also provides essential debugging capabilities; including breakpoints, single stepping, stack checking, and disassembly. 1-4 IQ80960RM/RN Evaluation Board Manual Introduction 1.4 CTOOLS Software Development Toolset Intel’s i960 processor software development toolset, CTOOLS, features advanced C/C++ - language compilers for the i960 processor family. CTOOLS development toolset is available for Windows* 95/NT-based systems and a variety of UNIX workstation hosts. These products provide execution profiling and instruction scheduling optimizations and include an assembler, a linker, and utilities designed for embedded processor software development. 1.4.1 CTOOLS and the MON960 Debug Monitor In place of IxWorks, the IQ80960RM/RN platform can be equipped with Intel’s MON960, an on-board software monitor that allows you to execute and debug programs written for i960 processors in a non-I2O environment. The monitor provides program download, breakpoint, single step, memory display, and other useful functions for running and debugging a program. The IQ80960RM/RN platform works with the source-level debuggers provided with CTOOLS, including GDB960 (command line version) and GDB960V (GUI version). 1.4.1.1 MON960 Host Communications MON960 allows you to communicate and download programs developed for the IQ80960RM/RN platform across a host system’s serial port or PCI interface. The IQ80960RM/RN platform supports two methods of communication: terminal emulation and Host Debugger Interface (HDI). 1.4.1.2 Terminal Emulation Method Terminal emulation software on your host system can communicate to MON960 on the IQ80960RM/RN platform via an RS-232 serial port. The IQ80960RM/RN platform supports port speeds from 300 to 115,200 bps. Serial downloads to MON960 require that the terminal emulation software support the XMODEM protocol. Configure the serial port on the host system for 300-115,200 baud, 8 bits, one stop bit, no parity with XON/XOFF flow control. 1.4.1.3 Host Debugger Interface (HDI) Method You may use a source-level debugger, such as Intel’s GDB960 and GDB960V to establish serial or PCI communications with the IQ80960RM/RN platform. The MON960 Host Debugger Interface (HDI) provides a defined messaging layer between MON960 and the debugger. For more information on this interface, see the MON960 Debug Monitor User’s Manual (484290). HDI connection requests cannot be detected by MON960 if the user has already initiated a connection using a terminal emulator. In this case, the IQ80960RM/RN platform must be reset before the debugger can connect to MON960. IQ80960RM/RN Evaluation Board Manual 1-5 Introduction 1.5 About This Manual A brief description of the contents of this manual follows. 1-6 Chapter 1, “Introduction” Introduces the IQ80960RM and IQ80960RN Evaluation Board features. This chapter also describes Intel’s CTOOLS* and WindRiver Systems IxWorks* software development tools, and defines notational-conventions and related documentation. Chapter 2, “Getting Started” Provides step-by-step instructions for installing the IQ80960RM or IQ80960RN platform in a host system and downloading and executing an application program. This chapter also describes Intel’s software development tools, the MON960 Debug Monitor, IxWORKS, software installation, and hardware configuration. Chapter 3, “Hardware Reference” Describes the locations of connectors, switches and LEDs on the IQ80960RM and IQ80960RN platforms. Header pinouts and register descriptions are also provided in this chapter. Chapter 4, “i960® RM/RN I/O Processor Overview” Presents an overview of the capabilities of the i960 RM/RN I/O processor and includes the CPU memory map. Chapter 5, “MON960 Support for IQ80960RM/RN” Describes a number of features added to MON960 to support application development on the i960 RM/RN I/O processor. Appendix A, “Bill of Materials” Shows complete parts list IQ80960RM and IQ80960RN Evaluation Platforms. Appendix B, “Schematics” Complete set of schematics for the IQ80960RM and IQ80960RN Evaluation Platforms. Appendix C, “PLD Code” Example PLD code used on IQ80960RM and IQ80960RN evaluation boards for SDRAM battery backup. Appendix D, “Recycling the Battery” Information on the RBRC program and the locations of participating recycling centers. IQ80960RM/RN Evaluation Board Manual Introduction 1.6 Notational-Conventions The following notation conventions are consistent with other i960 RM/RN I/O processor documentation and general industry standards. # or overbar In code examples the pound symbol (#) is appended to a signal name to indicate that the signal is active. Normally inverted clock signals are indicated with an overbar above the signal name (e.g., RAS). Bold Indicates user entry and/or commands. PLD signal names are in bold lowercase letters (e.g., h_off, h_on). Italics Indicates a reference to related documents; also used to show emphasis. Courier font Indicates code examples and file directories and names. Asterisks (*) On non-Intel company and product names, a trailing asterisk indicates the item is a trademark or registered trademark. Such brands and names are the property of their respective owners. UPPERCASE In text, signal names are shown in uppercase. When several signals share a common name, each signal is represented by the signal name followed by a number; the group is represented by the signal name followed by a variable (n). In code examples, signal names are shown in the case required by the software development tool in use. Designations for hexadecimal and binary numbers In text, instead of using subscripted “base” designators (e.g., FF16) or leading “0x” (e.g., 0xFF) hexadecimal numbers are represented by a string of hex digits followed by the letter H. A zero prefix is added to numbers that begin with A through F. (e.g., FF is shown as 0FFH.) In examples of actual code, “0x” is used. Decimal and binary numbers are represented by their customary notations. (e.g., 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is added to binary numbers for clarity.) IQ80960RM/RN Evaluation Board Manual 1-7 Introduction 1.7 Technical Support Up-to-date product and technical information is available electronically from: • Intel’s World-Wide Web (WWW) Location: http://www.intel.com • IQ80960RM and IQ80960RN Product Information: http://developer.intel.com/design/i960 For technical assistance, electronic mail (e-mail) provides the fastest route to reach engineers specializing in IQ80960RM and IQ80960RN issues. Posting messages on the Embedded Microprocessor Forum at http://support.intle.com/newsgroups/ is also a direct route for IQ80960RM and IQ80960RN technical assistance. See Section 1.7.2. Within the United States and Canada you may contact the Intel Technical Support Hotline. See Section 1.7.1 for a list of customer support sources for the US and other geographical areas. 1.7.1 Intel Customer Electronic Mail Support For direct support from engineers specialing in i960® Microprocessor issues send e-mail in english to 960tools@intel.com. Questions and other messages may be posted to the Embedded Microprocessor Forum at http://support.intel.com/newsgroups/. 1.7.2 Intel Customer Support Contacts Contact Intel Corporation for technical assistance for the IQ80960RM/RN evaluation platform. Country United States 1-8 Literature Customer Support Number 800-548-4725 800-628-8686 Canada 800-468-8118 or 303-297-7763 800-628-8686 Europe Contact local distributor Contact local distributor Australia Contact local distributor Contact local distributor Israel Contact local distributor Contact local distributor Japan Contact local distributor Contact local distributor IQ80960RM/RN Evaluation Board Manual Introduction 1.7.3 Related Information To order printed manuals from Intel, contact your local sales representative or Intel Literature Sales (1-800-548-4725). Table 1-1. Document Information Product All 80960RM/RN Document Name Company/ Order # Developers’ Insight CD-ROM Intel # 273000 i960® RM/RN I/O Processor Developer’s Manual Intel # 273158 80960RM I/O Processor Data Sheet Intel # 273156 80960RN I/O Processor Data Sheet Intel # 273157 MON960 Debug Monitor User’s Guide Intel #484290 PCI Local Bus Specification Revision 2.1 PCI Special Interest Group 1-800-433-5177 Writing I2O Device Drivers in IxWorks Wind River Systems, Inc. #DOC-1173-8D-02 Wind River Systems, Inc. IxWorks Reference Manual #DOC-1173-8D-03 Wind River Systems, Inc. VxWorks Programmer’s Guide #DOC-11045-ZD-01 Wind River Systems, Inc. Tornado User’s Guide #DOC-1116-8D-01 Wind River Systems, Inc. Tornado for I2O #DOC-12381-8D-00 Tornado for I2O Compact Disk Rev. 1.0 #TDK-12380-ZC-00 Contact Cyclone Microsystems for additional information about their products and literature: Table 1-2. Cyclone Contacts Phone: 203-786-5536 Cyclone Microsystems 25 Science Park New Haven CT 06511 FAX: 203-786-5025 e-mail: info@cyclone.com WWW: http://www.cyclone.com IQ80960RM/RN Evaluation Board Manual 1-9 Getting Started 2 This chapter contains instructions for installing the IQ80960RM/RN platform in a host system and, how to download and execute an application program using Wind River System’s IxWorks∗ or Intel’s CTOOLS software development toolsets. 2.1 Pre-Installation Considerations This section provides a general overview of the components required to develop and execute a program on the IQ80960RM/RN platform. IQ80960RM/RN evaluation boards support two software development toolsets, Wind River System’s IxWorks and Intel’s CTOOLS. IxWorks is a complete toolset featuring an integrated development environment including a compiler, assembler, linker, and debugger. It also features a real-time operating system. If you are using the IxWorks operating system with the TORNADO* development environment, refer to the Wind River Systems, Inc. documentation referenced in Section 1.7.3. CTOOLS is a complete C/C++-language software-development toolset for developing embedded applications to run on i960 processors. It contains a C/C++ compiler, the gcc960 and ic960 compiler driver programs, an assembler, runtime libraries, a collection of software-development tools and utilities, and printed and on-line documentation. The MON960 Debug Monitor User’s Guide fully describes the components of MON960, including MON960 commands, the Host Debugger Interface Library (HDIL), and the MONDB.EXE utility. If you are using MON960 and the CTOOLS toolset, refer to section Section 2.2.1, “Installing Software Development Tools” on page 2-1. See Chapter 1 for more information on the IxWorks and CTOOLS features. The IQ80960RM/RN evaluation boards are supplied with IxWorks intelligent real-time operating system pre-loaded into the on-board Flash. You also have the option of installing the MON960 debug monitor, which is required if you are using the CTOOLS debugging tools, GDB960, GDB960V, or MONDB. Section 3.3.1 describes the Flash ROM programming utility, which allows you to load MON960 onto the platform or re-load IxWorks. 2.2 Software Installation 2.2.1 Installing Software Development Tools If you haven’t done so already, install your development software as described in its manuals. All references in this manual to CTOOLS or CrossWind assume that the default directories were selected during installation. If this is not the case, substitute the appropriate path for the default path wherever file locations are referenced in this manual. IQ80960RM/RN Evaluation Board Manual 2-1 Getting Started 2.3 Hardware Installation Follow these instructions to get your new IQ80960RM/RN platform running. Be sure all items on the checklist were provided with your IQ80960RM/RN. Warning: 2.3.1 Static charges can severely damage the IQ80960RM/RN platforms. Be sure you are properly grounded before removing the IQ80960RM/RN platform from the anti-static bag. Battery Backup Battery backup is provided to save any information in SDRAM during a power failure. The IQ80960RM/RN platform contains four AA NiCd batteries, a charging circuit and a regulator circuit. The batteries installed in the IQ80960RM/RN platform are rated at 600 mA/Hr. SDRAM technology provides a simple way of enabling data preservation through the self-refresh command. When the processor receives an active Primary PCI reset it issues the self-refresh command and drives the SCKE signals low. Upon seeing this condition, a PAL on the IQ80960RM/RN platform holds SCKE low before the processor loses power. The batteries maintain power to the SDRAM and the PAL to ensure self-refresh mode. When the PAL detects PRST# returning to inactive state, the PAL releases the hold on SCKE. The battery circuit can be disabled by removing the batteries. LED CR4 indicates when the SDRAMs have sufficient power. If the batteries remain in the evaluation platform when it is depowered and/or removed from the chassis, the batteries will maintain the SDRAM for approximately 30 hours. Once power is again applied, the batteries will be fully charged in about 4 hours. 2.3.2 Installing the IQ80960RM/RN Platforms in the Host System If you are installing the IQ80960RM/RN platform for the first time, visually inspect the board for any damage that may have occurred during shipment. If there are visible defects, return the board for replacement. Follow the host system manufacturer’s instructions for installing a PCI adapter. The IQ80960RM/RN platform is a full-length PCI adapter and requires a PCI slot that is free from obstructions. The IQ80960RM/RN platform is taller than specified in the PCI Local Bus Specification Revision 2.1. The extended height of the board will require you to keep the cover off of your PC. Refer to Chapter 3 for physical dimensions of the board. 2.3.3 Verify IQ80960RM/RN Platform is Functional These instructions assume that you have already installed the IQ80960RM/RN platform in the host system as described in Section 2.3.2. 1. To connect the serial port for communicating with and downloading to the IQ80960RM/RN platform, connect the RS-232 cable (provided with the IQ80960RM/RN) from a free serial port on the host system to the phone jack-style connector on the IQ80960RM/RN platform. 2. Upon power-up, the red FAIL LED turns off, indicating that the processor has passed its self-test. 3. If you have IxWorks installed in the flash ROM, the user LEDs display the binary pattern 99H. In the IxWorks development environment, raw serial input/output is not used. Instead, the Wind DeBug (WDB) protocol is run over the serial port, to allow communication with Tornado development tools. If the terminal emulation package is running at 115,200 baud, the letters “WDB_READY” display prior to launching in the WDB serial protocol. 2-2 IQ80960RM/RN Evaluation Board Manual Getting Started 4. If you have MON960 installed in the flash ROM, presson a terminal connected to the IQ80960RM/RN platform to bring up the MON960 prompt. MON960 automatically adjusts its baud rate to match that of the terminal at start-up. At baud rates other than 9600, it may be necessary to press several times. 2.4 Creating and Downloading Executable Files To download code to the IQ80960RM/RN platform running IxWorks, consult Wind River documentation on the supplied TORNADO for I2O CD-ROM. To download code to the IQ80960RM/RN platform, your compiler produces an ELF-format object file. To download code to the IQ80960RM/RN platform running CTOOLS, consult the CTOOLS documentation for information regarding compiling, linking, and downloading applications. During a download, MON960 checks the link address stored in the ELF file, and stores the file at that location on the IQ80960RM/RN platform. If the executable file is linked to an invalid address on the IQ80960RM/RN platform, MON960 aborts the download. 2.4.1 Sample Download and Execution Using GDB960 This example shows you how to use GBD960 to download and execute a file named myapp via the serial port. • Invoke GDB960. From a Windows 95/NT command prompt, issue the command: gdb960 -r com2 myapp This command establishes communication and downloads the file myapp. • To execute the program, enter the command from the GDB960 command prompt: (gdb960) run More information on the GDB960 commands mentioned in this section can be found in the GDB960 User’s Manual. IQ80960RM/RN Evaluation Board Manual 2-3 3 Hardware Reference 3.1 Power Requirements The IQ80960RM/RN platform draws power from the PCI bus. The power requirements of the IQ80960RM/RN platforms are shown in Table 3-1 and Table 3-2. The numbers do not include the power required by a PCI card(s) mounted on one or more of the IQ80960RM/RN platforms’ four expansion slots. Table 3-1. IQ80960RN Platform Power Requirements Voltage Typical Current Maximum Current +3.3 V 0 V* 0 V* +5 V 1.45 A 1.96 A +12 V 286 mA 485 mA -12 V 1 mA 1 mA NOTE: Does not include the power required by a PCI card(s) mounted on the IQ80960RN platform. * +3.3V for 80960RN Processor created on board from +5V. Table 3-2. IQ80960RM Platform Power Requirements Voltage Typical Current Maximum Current +3.3 V 0 V* 0 V* +5 V 1.32 A 1.86 A +12 V 284 mA 485 mA -12 V 1 mA 1 mA NOTE: Does not include the power required by a PCI card(s) mounted on the IQ80960RM platform. * +3.3V for 80960RM Processor created on board from +5V. 3.2 SDRAM The IQ80960RM/RN platform is equipped with a 168-pin DIMM socket formatted to accept +3.3V synchronous DRAM with or without Error Correction Code (ECC). The socket will accept SDRAM from 8 Mbytes to 128 Mbytes. 128 Mbyte SDRAMs are available in both x64 and x72 configurations. Note that 8 Mbyte SDRAMs are only for x64 or non-ECC memory. The SDRAM is accessible from either of the PCI buses, via the ATUs, and the local bus on the IQ80960RM/RN platform. IQ80960RM/RN Evaluation Board Manual 3-1 Hardware Reference 3.2.1 SDRAM Performance The IQ80960RM/RN platform uses 72-bit SDRAM with ECC or 64-bit SDRAM without ECC. SDRAM allows zero data-to-data wait state operation at 66 MHz. The memory controller unit (MCU) of the i960® RM/RN I/O processor supports SDRAM burst lengths of four. A burst length of four enables seamless read/write bursting of long data streams, as long as the MCU does not cross the page boundary. Page boundaries are naturally aligned 2 Kbyte blocks. 72-bit SDRAM with ECC allows a maximum throughput of 528 Mbytes per second. Both 16 Mbit and 64 Mbit SDRAM devices are supported. The MCU keeps two pages per bank open simultaneously for 16 Mbit devices and 4 pages per bank for 64 Mbit devices. Simultaneously open pages allow for greater performance for sequential access, distributed across multiple internal bus transactions. Table 3-3 shows read and write examples of a single 8 byte access and for a multiple 40 byte access. Table 3-3. SDRAM Performance Cycle Type Table Clocks Performance Bandwidth Read Page Hit (8 bytes) 7 76 Mbytes/sec Read Page Miss (8 bytes) 12 44 Mbytes/sec Read Page Hit (40 bytes) 11 240 Mbytes/sec Read Page Miss (40 bytes) 16 165 Mbytes/sec Write Page Hit (8 bytes) 4 132 Mbytes/sec Write Page Miss (8 bytes) 8 66 Mbytes/sec Write Page Hit (40 bytes) 8 330 Mbytes/sec Write Page Miss (40 bytes) 12 220 Mbytes/sec Note that if ECC is enabled and you attempt a partial write — less than 64 bits — you will incur a penalty. Because ECC is enabled, the MCU will translate the write into a read-modify-write transaction. Therefore, for a single byte write the clock count will be 11. 3-2 IQ80960RM/RN Evaluation Board Manual Hardware Reference 3.2.2 Upgrading SDRAM The IQ80960RM/RN is equipped with 16 Mbytes of SDRAM with ECC inserted in the 168-pin DIMM socket. The memory may be expanded by inserting up to a 128 Mbyte module into the DIMM socket. The various memory combinations are shown in Table 3-4. Only 168-pin +3.3V SDRAM modules with or without ECC rated at 10 ns should be used on the IQ80960RM/RN platform. The column labeled ECC determines if that particular memory configuration can be used with ECC. Table 3-4. SDRAM Configurations SDRAM Technology SDRAM Arrangement 2M x 8 16 Mbit 1M x 16 8M x 8 64 Mbit 4M x 16 3.3 # Banks 1 2 1 2 1 2 1 2 Row Column 11 9 11 8 12 9 12 8 ECC Total Memory SIze Yes 16 Mbytes Yes 32 Mbytes No 8 Mbytes No 16 Mbytes Yes 64 Mbytes Yes 128 Mbytes No 32 Mbytes No 64 Mbytes Flash ROM An E28F016S5 (2 Mbytes) Flash ROM is included on the IQ80960RM/RN platform. This Flash ROM contains IxWorks* and may be used to store user applications. 3.3.1 Flash ROM Programming Two types of Flash ROM programming exist on the IQ80960RM/RN platform. The first is normal application development programming. This occurs using IxWorks to download new software and the 80960JT core to write the new code to the Flash ROM. During this time the boot sectors (containing IxWorks) are write protected. The second type of Flash ROM programming is loading the boot sectors. You will not be required to load the boot sectors except: • To load MON960 • To load a new release of IxWorks • To change between the check build and the free build of IxWorks The following steps are required to program the Flash ROM boot sectors: 1. Set switch S1 #’s 1 and 2 to the on position. 2. Reset the board by cycling power on the workstation. 3. Run the Intel DOS-based flash utility to program the Flash ROM boot sectors. 4. Set switch S1 #’s 1 and 2 to the off position. 5. Reset the board by cycling power on the workstation. IQ80960RM/RN Evaluation Board Manual 3-3 Hardware Reference 3.4 Console Serial Port The console serial port on the IQ80960RM/RN platform, based on a 16C550 UART, is capable of operation from 300 to 115,200 bps. The port is connected to a phone jack-style plug on the IQ80960RM/RN platform. The DB25 to RJ-45 cable included with the IQ80960RM/RN can be used to connect the console port to any standard RS-232 port on the host system. The UART on the IQ80960RM/RN platform is clocked with a 1.843 MHz clock, and may be programmed to use this clock with its internal baud rate counters. The UART register addresses are shown in Table 3-5; refer to the 16C550 device data book for a detailed description of the registers and device operation. Note that some UART addresses refer to different registers depending on whether a read or a write is being performed. Table 3-5. UART Register Addresses Address 3.5 Read Register Write Register E000 0000H Receive Holding Register Transmit Holding Register E000 0001H Unused Interrupt Enable Register E000 0002H Interrupt Status Register FIFO Control Register E000 0003H Unused Line Control Register E000 0014H Unused Modem Control Register E000 0015H Line Status Register Unused E000 0016H Modem Status Register Unused E000 0017H Scratchpad Register Scratchpad Register Secondary PCI Bus Expansion Connectors Four PCI Expansion Slots are available on the IQ80960RM/RN platform. The IQ80960RM supports 32-bit PCI expansion and the IQ80960RN supports 64-bit PCI expansion. The slots are designed for +5V PCI signalling and accommodate PCI cards with +5V or universal signalling capabilities. 3.5.1 PCI Slots Power Availability Power from the Primary PCI bus, +3.3V, +5V, +12V, and –12V, is routed to the Secondary PCI bus expansion slots. +3.3V is only available at the secondary PCI slots if the host system makes +3.3V available on the Primary PCI slots. LED CR5 indicates if this power is available. 3-4 IQ80960RM/RN Evaluation Board Manual Hardware Reference 3.5.2 Interrupt and IDSEL Routing Table 3-6. Secondary PCI Bus Interrupt and IDSEL Routing 3.6 Connector IDSEL INTA# INTB# INTC# INTD# J11 SAD16 SINTA# SINTB# SINTC# SINTD# J12 SAD17 SINTB# SINTC# SINTD# SINTA# J13 SAD18 SINTC# SINTD# SINTA# SINTB# J14 SAD19 SINTD# SINTA# SINTB# SINTC# Battery Backup Battery backup is provided to save any information in SDRAM during a power failure. The IQ80960RM/RN platform contains four AA NiCd batteries, a charging circuit and a regulator circuit. The batteries installed in the IQ80960RM/RN platform are rated at 600 mA/Hr. SDRAM technology provides a simple way of enabling data preservation though the self-refresh command. When the processor receives an active Primary PCI reset it will issue the self-refresh command and drive the SCKE signals low. Upon seeing this condition a PAL on the IQ80960RM/RN platform will hold SCKE low before the processor loses power. The batteries will maintain power to the SDRAM and the PAL to ensure self-refresh mode. When the PAL sees PRST# returning to inactive state the PAL will release the hold on SCKE. The battery circuit can be disabled by removing the batteries. LED CR4 indicates when the SDRAMs have sufficient power. If the batteries remain in the evaluation platform when it is depowered and/or removed from the chassis, the batteries will maintain the SDRAM for approximately 30 hours. Once power is again applied, the batteries will be fully charged in about four hours. 3.7 Loss of Fan Detect The i960 RM/RN I/O processor can be cooled by an active heat sink mounted on top. The fan provides a square wave output that is monitored by a comparator circuit on the IQ80960RM/RN platform. The frequency of the fan output is approximately 9K RPM. If the frequency falls below approximately 8K RPM the circuit will provide an interrupt to the processor. Note: The standard production boards will be shipped with attached passive heat sinks. In the case of utilizing a passive heat sink, the processor never sees an interrupt from not having a fan. IQ80960RM/RN Evaluation Board Manual 3-5 Hardware Reference 3.8 Logic Analyzer Headers There are five logic analyzer connectors on the IQ80960RM/RN platform. The connectors are Mictor type, AMP part # 767054-1. Hewlett-Packard and Tektronix manufacture and sell interfaces to these connectors. The logic analyzer connectors allow for interfacing to the SDRAM and ROM buses along with secondary PCI arbitration signals. Table 3-7 shows the connectors and the pin assignments for each. Table 3-7. Logic Analyzer Header Definitions PIN J9 3 J12 J10 J8 4 DQ15 SDQM7 DQ31 RAD15 5 DQ14 SDQM6 DQ30 RAD14 6 DQ13 SDQM5 DQ29 RAD13 7 DQ12 SDQM4 DQ28 RAD12 8 DQ11 SDQM3 DQ27 RAD11 9 DQ10 SDQM2 DQ26 RAD10 10 DQ9 SDQM1 DQ25 RAD9 11 DQ8 SDQM0 DQ24 RAD8 12 DQ7 SCB7 DQ23 RAD7 13 DQ6 SCB6 DQ22 RAD6 14 DQ5 SCB5 DQ21 RAD5 15 DQ4 SCB4 DQ20 RAD4 16 DQ3 SCB3 DQ19 SCE0# RAD3 17 DQ2 SCB2 DQ18 SCE1# RAD2 18 DQ1 SCB1 DQ17 SBA1 RAD1 19 DQ0 SCB0 DQ16 SBA0 RAD0 20 DQ32 SA0 DQ48 SREQ0# RAD16 21 DQ33 SA1 DQ49 SREQ1# 22 DQ34 SA2 DQ50 SREQ2# 23 DQ35 SA3 DQ51 SREQ3# RALE 24 DQ36 SA4 DQ52 SREQ4# RCE0# 25 DQ37 SA5 DQ53 SREQ5# RCE1# 26 DQ38 SA6 DQ54 SGNT0# ROE# 27 DQ39 SA7 DQ55 SGNT1# RWE# 28 DQ40 SA8 DQ56 SGNT2# 29 DQ41 SA9 DQ57 SGNT3# 30 DQ42 SA10 DQ58 SGNT4# 31 DQ43 SA11 DQ59 SGNT5# 32 DQ44 33 DQ45 SWE# DQ61 34 DQ46 SCAS# DQ62 35 DQ47 SRAS# DQ63 36 3-6 J11 SDRAMCLK I_RST# DQ60 P_PCICLK RALE IQ80960RM/RN Evaluation Board Manual Hardware Reference 3.9 JTAG Header The JTAG header allows debugging hardware to be quickly and easily connected to some of the IQ80960RM/RN processor’s logic signals. The JTAG header is a 16-pin header. A 3M connector (part number 2516-6002UG) is required to connect to this header. The pinout for the JTAG header is shown in Table 3-8. The header and connector are keyed using a tab on the connector and a slot on the header to ensure proper installation. Each signal in the JTAG header is paired with its own ground connection to avoid the noise problems associated with long ribbon cables. Signal descriptions are found in the i960® RM/RN I/O Processor Developer’s Manual, 80960RM I/O Processor Data Sheet and the 80960RN I/O Processor Data Sheet. Table 3-8. JTAG Header Pinout Pin Signal Input/Output to 80960RM/RN Pin Signal 1 TRST# IN 2 GND 3 TDI IN 4 GND 5 TDO OUT 6 GND 7 TMS IN 8 GND 9 TCK IN 10 GND 11 LCDINIT# IN 12 GND 13 I_RST# OUT 14 GND 15 PWRVLD OUT 16 GND Table 3-9 describes switch setting options and defaults. These switch settings are sampled at Primary PCI Reset. See Table 5-1 “Initialization Modes” on page 5-3 for processor initialization configurations. Table 3-9. Switch S1 Settings Position a. Name S1-1 RST_MODE# S1-2 RETRY S1-3 32BITMEM_EN# S1-4a 32BITPCI_EN# Description Default Determines if the processor is to be held in reset. ON = hold in rest OFF = allows processor initialization OFF Determines if the Primary PCI interface will be disabled. ON = allows Primary PCI configuration cycles to occur OFF = retries all Primary PCI configuration cycles OFF Notifies Memory Controller of the SDRAM width. ON = Memory Controller utilizes 32-bit SDRAM access protocol OFF = Memory Contoller utilizes 64-bit SDRAM access protocol OFF Determines whether Secondary PCI bus is a 32- or 64-bit bus. ON = indicates Secondary PCI bus is a 32-bit bus OFF = indicates Secondary PCI bus is a 64-bit bus OFF This switch is active for IQ80960RN ONLY. IQ80960RM/RN Evaluation Board Manual 3-7 Hardware Reference 3.10 User LEDs The IQ80960RM/RN platform has a bank of eight user-programmable LEDs, located on the upper edge of the adapter board. These LEDs are controlled by a write-only register and used as a debugging aid during development. Software can control the state of the user LEDs by writing to the LED Register, located at E004 0000H. Each of the eight bits of this register correspond to one of the user LEDs. Clearing a bit in the LED Register by writing a “0” to it turns the corresponding LED “on”, while setting a bit by writing a “1” to it turns the corresponding LED “off”. Resetting the IQ80960RM/RN platform results in clearing the register and turning all the LEDs “on”. The LED Register bitmap is shown in Figure 3-1. The user LEDs are numbered in descending order from left to right, with LED7 being on the left when looking at the component side of the adapter. Figure 3-1. LED Register Bitmap 7 6 5 4 3 2 1 0 User LED 7 User LED 6 User LED 5 User LED 4 User LED 3 User LED 2 User LED 1 User LED 0 3.10.1 User LEDs During Initialization MON960 indicates the progress of its hardware initialization on the user LEDs. In the event that initialization should fail for some reason, the number of lit LEDs can be used to determine the cause of the failure. Table 3-10 lists the tests that correspond to each lit LED. Table 3-10. 3-8 Start-up LEDs MON960 LEDs Tests LED 0 SDRAM serial EEPROM checksum validated LED 1 UART walking ones test passed LED 2 DRAM walking ones test passed LED 3 DRAM multiword test passed LED 4 Hardware initialization started LED 5 Flash ROM initialized LED 6 PCI-to-PCI Bridge initialized LED 7 UART internal loopback test passed IQ80960RM/RN Evaluation Board Manual Hardware Reference Table 3-11 lists the connectors and LEDs. Table 3-11. IQ80960RM/RN Connectors and LEDs Item J1-J4 Description Secondary PCI bus expansion connector J5 168-pin SDRAM DIMM socket J6 JTAG connector J7 Serial port connector J8 Logic analyzer connector for flash ROM bus J10 J9, J11, J12 J13 Logic analyzer connector for Secondary PCI bus arbitration signals Logic analyzer connector for access to SDRAM bus Active heatsink connector for example fan monitor circuit CR1, CR2 Eight user LEDs CR3 Self-test fail LED CR4 Battery backup SDRAM, 3.3 V available CR5 S1 IQ80960RM/RN Evaluation Board Manual Indicates host system providing 3.3 V to Secondary PCI bus connectors DIP switch (Table 3-9) 3-9 i960® RM/RN I/O Processor Overview 4 This chapter describes the features and operation of the processor on the IQ80960RM/RN platform. For more detail, refer to the i960® RM/RN I/O Processor Developer’s Manual. Figure 4-1. i960® RM/RN I/O Processor Block Diagram Local Memory (SDRAM, Flash) I2C Serial Bus 80960 Core Processor Memory Controller Bus Interface Unit I2C Bus Interface Application Accelerator Internal Arbitration 64-bit Internal Bus Messaging Unit Two DMA Channels Address Translation Unit 64-bit/32-bit Primary PCI Bus Performance Monitoring Unit IQ80960RM/RN Evaluation Board Manual One DMA Channel PCI to PCI Bridge Address Translation Unit 64-bit/32-bit Secondary PCI Bus Secondary PCI Arbitration 4-1 i960® RM/RN I/O Processor Overview 4.1 CPU Memory Map The memory map for the IQ80960RM/RN platform is shown in Figure 4-2. All addresses below 9002 0000H on the IQ80960RM/RN platform are reserved for various functions of the i960 RM/RN I/O processor, as shown on the memory map. Documentation for these areas, as well as the processor memory mapped registers at FF00 0000H and the IBR, can be found in the i960® RM/RN I/O Processor Developer’s Manual. Figure 4-2. IQ80960RM/RN Platform Memory Map Flash ROM and Processor Registers Processor Memory Mapped Registers FF00 0000H Flash ROM F000 0000H On-board Devices FEE0 0000H Reserved E000 0000H F000 0000H Reserved LED Register (write only) UART B000 0000H DRAM E004 0000H E000 0000H A000 0000H Reserved 9002 0000H ATU Outbound Translation Windows 8000 0000H ATU Outbound Direct Addressing Window 0000 2000H Reserved 0000 1900H Peripheral Memory Mapped Registers 0000 0800H Reserved 0000 0400H Processor Internal Data RAM 0000 0000H 4-2 IQ80960RM/RN Evaluation Board Manual i960® RM/RN I/O Processor Overview 4.2 Local Interrupts The i960 RM/RN I/O processor is built around an 80960JT core, which has seven external interrupt lines designated XINT0# through XINT5# and NMI#. In the i960 RM/RN I/O processor, these interrupt lines are not directly connected to external interrupts, but pass through a layer of internal interrupt routing logic. Figure 4-3 shows the interrupt connections on the i960 RM/RN I/O processor. XINT0# through XINT3# on the 80960JT core can be used to receive PCI interrupts from the secondary PCI bus, or these interrupts can be passed through to the primary PCI interface, depending on the setting of the XINT Select bit of the PCI Interrupt Routing Select Register in the i960 RM/RN I/O processor. On the IQ80960RM/RN platform, XINT0# through XINT3# are configured to receive interrupts from the secondary PCI bus. XINT4# and XINT5# on the i960 RM/RN I/O processor may be connected to interrupt sources external to the processor. On the IQ80960RM/RN platform, XINT4# is connected to the loss of fan detect and XINT5# is connected to the 16C550 UART. XINT6#, XINT7# receive interrupts from internal sources. NMI# receives interrupts from internal sources and from an external source. Since all of these interrupts accept signals from multiple sources, a status register is provided for each of them to allow service routines to identify the source of the interrupt. Each of the possible interrupt sources is assigned a bit position in the status register. The interrupt sources for these lines are shown in Figure 4-3. On the IQ80960RM/RN platform, the NMI# interrupt is not connected to any external interrupt source and receives interrupts only from the internal devices on the i960 RM/RN I/O processor. Note that all error conditions result in an NMI# interrupt. IQ80960RM/RN Evaluation Board Manual 4-3 i960® RM/RN I/O Processor Overview i960® RM/RN I/O Processor Interrupt Controller Connections P_INTA# Output P_INTB# Output P_INTC# Output P_INTD# Output Figure 4-3. i960® RN/RM I/O Processor 80960 Outbound Doorbell 0 80960 Outbound Doorbell 1 80960 Outbound Doorbell 2 80960 Outbound Doorbell 3 S_INTD# Select bit S_INTC# Select bit S_INTB# Select bit S_INTA# Select bit S_INTA#/XINT0# m u x S_INTB#/XINT1# m u x S_INTC#/XINT2# m u x XINT0# XINT1# XINT2# XINT3# i960 Core Processor XINT4# XINT5# S_INTD#/XINT3# XINT6# XINT7# NMI# m u x Messaging Unit Interrupt Pending Primary ATU/Start BIST Interrupt Pending Bus Interface Unit Error Primary PCI Bridge Interface Error Secondary PCI Bridge Interface Error Primary ATU Error Secondary ATU Error Memory Controller Unit Error DMA Channel 0 Error DMA Channel 1 Error DMA Channel 2 Error Messaging Unit Error Application Accelerator Unit Error XINT7 Interrupt Latch I2C Bus Interface Unit Interrupt Pending NMI Interrupt Latch DMA Channel 0 Interrupt Pending DMA Channel 1 Interrupt Pending DMA Channel 2 Interrupt Pending Performance Monitor Unit Interrupt Pending Application Accelerator Interrupt Pending XINT6 Interrupt Latch XINT4# (Loss of Fan) XINT5# (UART) NMI# (N/C) 4-4 IQ80960RM/RN Evaluation Board Manual i960® RM/RN I/O Processor Overview 4.3 CPU Counter/Timers The i960 RM/RN I/O processor is equipped with two on-chip counter/timers which are clocked with the i960 RM/RN I/O processor clock signal. The i960 RM/RN I/O processor receives its clock from the primary PCI interface clock, generated by the motherboard. Most motherboards generate a 33 MHz clock signal, although the PCI specification requires a clock frequency between 0 and 33 MHz. The timers can be programmed for single-shot or continuous mode, and can generate interrupts to the processor when the countdown expires. 4.4 Primary PCI Interface The primary PCI interface on the IQ80960RM/RN platform provides the i960 RM/RN I/O processor with a connection to the PCI bus on the host system. Only the PCI-to-PCI bridge unit on the i960 RM/RN I/O processor is directly connected to the primary PCI interface. Devices installed on the expansion slots are connected to the PCI bus via the bridge unit on the i960 RM/RN I/O processor. The PCI-to-PCI bridge accepts Type 1 configuration cycles destined for devices on the secondary bus, and will forward them as Type 0 or Type 1 configuration cycles, or as special cycles. The IQ80960RN platform interfaces to a 64-bit PCI bus and the IQ80960RM platform interfaces to a 32-bit PCI bus. 4.5 Secondary PCI Interface The secondary PCI interface provided by the i960 RM/RN I/O processor is used to connect PCI cards via the expansion slots to the host system’s PCI bus. PCI cards are attached to the IQ80960RM/RN platform with a standard PCI connector and may contain up to four separate PCI devices. The i960 RM/RN I/O processor provides PCI-to-PCI bridge functionality to map installed PCI devices onto the host PCI bus, and supports transaction forwarding in both directions across the bridge. PCI devices connected via the expansion slots can therefore act as masters or slaves on the host system’s PCI bus. Additional PCI-to-PCI bridge devices are supported by the i960 RM/RN I/O processor on its secondary PCI interface and can be designed into add-on PCI cards. In addition, the i960 RM/RN I/O processor supports “private” PCI devices on its secondary bus. Private devices are hidden from initialization code on the host system, and are configured and accessed directly by the i960 RM/RN I/O processor. These devices are not part of the normal PCI address space, but they can act as PCI bus masters and transfer data to and from other PCI devices in the system. Unless designated as private devices, PCI devices installed on the secondary PCI interface of the IQ80960RM/RN platform are mapped into the system-wide PCI address space by configuration software running on the host system. No logical distinction is made at the system level between devices on the primary PCI bus and devices on secondary buses; all transaction forwarding is handled transparently by the PCI-to-PCI bridge. Configuration cycles and read and write accesses from the host are forwarded through the PCI-to-PCI bridge unit of the i960 RM/RN I/O processor. Master read and write cycles from devices on the secondary PCI bus are also forwarded to the host bus by the PCI-to-PCI bridge unit. IxWORKS allows secondary PCI devices to be configured as Public or Private. Public devices are configured by the PCI host. Private devices are configured by the IxWORKS kernel and the device-specific HDM. IQ80960RM/RN Evaluation Board Manual 4-5 i960® RM/RN I/O Processor Overview 4.6 DMA Channels The i960 RM/RN I/O processor features three independent DMA channels, two of which operate on the primary PCI interface, whereas the remaining one operates on the secondary PCI interface. All three of the DMA channels connect to the i960 RM/RN I/O processor’s local bus and can be used to transfer data from PCI devices to memory on the IQ80960RM/RN platform. Support for chaining, and scatter/gather is built into all three channels. The DMA can address the entire 264 bytes of address space on the PCI bus and 232 bytes of address space on the internal bus. Figure 4-4. i960® RM/RN I/O Processor DMA Controller Primary PCI Bus DMA Channel 0 80960 Local Bus DMA Channel 1 PCI to PCI Bridge DMA Channel 2 Secondary PCI Bus 4.7 Application Accelerator Unit The Application Accelerator provides low-latency, high-throughput data transfer capability between the AA unit and 80960 local memory. It executes data transfers to and from 80960 local memory and also provides the necessary programming interface. The Application Accelerator performs the following functions: • Transfers data (read) from memory controller • Performs an optional boolean operation (XOR) on read data • Transfers data (write) to memory controller The AA unit features: • • • • • • 4-6 128-byte, arranged as 8-byte x 16-deep store queue Utilization of the 80960RN/RM processor memory controller interface 232 addressing range on the 80960 local memory interface Hardware support for unaligned data transfers for the internal bus Full programmability from the i960 core processor Support for automatic data chaining for gathering and scattering of data blocks IQ80960RM/RN Evaluation Board Manual i960® RM/RN I/O Processor Overview Figure 4-5 shows a simplified connection of the Application Accelerator to the i960 RM/RN I/O Processor Internal Bus. Figure 4-5. Application Accelerator Unit Application Accelerator Unit Data Queue Boolean Unit Packing/ Unpacking Unit 80960 Bus Interface 4.8 64-bit Internal Bus Performance Monitor Unit The Performance Monitoring features aid in measuring and monitoring various system parameters that contribute to the overall performance of the processor. The monitoring facility is generically referred to as PMON – Performance Monitoring. The facility is model specific, not architectural; its intended use is to gather performance measurements that can be used to retune/refine code for better system level performance. The PMON facility provided on the i960 RM/RN I/O processor comprises: • One dedicated global Time Stamp counter, and • Fourteen (14) Programmable Event counters The global time stamp counter is a dedicated, free running 32-bit counter. The programmable event counters are 32-bits wide. Each counter can be programmed to observe an event from a defined set of events. An event consists of a set of parameters which define a start condition and a stop condition. The monitored events are selected by programming an event select register (ESR). IQ80960RM/RN Evaluation Board Manual 4-7 MON960 Support for IQ80960RM/RN 5 This chapter discusses a number of additions that have been made to MON960 to support the IQ80960RM/RN in an optional non-I2O capacity. For complete documentation on the operation of MON960, see the MON960 Debug Monitor User’s Guide. The IQ80960RM/RN evaluation platform ships with IxWorks* from Wind River Systems installed in flash firmware. To use CTOOLS and MON960 instead of IxWorks, you need to download MON960 into the onboard Flash. See Chapter 2 for more information on updating the onboard Flash. See Chapter 1 for descriptions of both IxWorks and CTOOLS. 5.1 Secondary PCI Bus Expansion Connectors The IQ80960RM/RN platform contains four secondary PCI bus expansion connectors to give users access to the secondary PCI bus of the i960® RM/RN I/O processor. Extensions to MON960 perform secondary PCI bus initialization including the establishment of a secondary PCI bus address map. Routines compatible with the PCI Local Bus Specification Revision 2.1 allow the software on the IQ80960RM/RN platform to search for devices on the secondary PCI bus and read and write the configuration space of those devices. 5.2 MON960 Components The remaining sections of this chapter assume that MON960 is installed in the onboard Flash, replacing IxWorks. The IQ80960RM/RN optional MON960 debug monitor consists of four main components: • Initialization firmware • MON960 kernel • MON960 extensions • Diagnostics/example code These four components together are referred to as MON960. 5.2.1 MON960 Initialization At initialization, MON960 puts the IQ80960RM/RN platform into a known, functional state that allows the host processor to perform PCI initialization. Once in this state, the MON960 kernel and the MON960 extensions can load and execute correctly. Initialization is performed after a RESET condition. MON960 initialization encompasses all major portions of the i960 RM/RN I/O processor and IQ80960RM/RN platform including 80960JT core initialization, Memory Controller initialization, SDRAM initialization, Primary PCI Address Translation Unit (ATU) initialization, and PCI-to-PCI Bridge Unit initialization. The IQ80960RM/RN platform is designed to use the Configuration Mode of the i960 RM/RN I/O processor. Configuration Mode allows the 80960JT core to initialize and control the initialization process before the PCI host configures the i960 RM/RN I/O processor. By utilizing Configuration Mode, the user IQ80960RM/RN Evaluation Board Manual 5-1 MON960 Support for IQ80960RM/RN is given the ability to initialize the PCI configuration registers to values other than the default power-up values. Configuration Mode gives the user maximum flexibility to customize the way in which the i960 RM/RN I/O processor and IQ80960RM/RN platform appear to the PCI host configuration software. 5.2.2 80960JT Core Initialization The 80960JT core begins the initialization process by reading its Initial Memory Image (IMI) from a fixed address in the boot ROM (FEFF FF30H in the i960 address space). The IMI includes the Initialization Boot Record (IBR), the Process Control Block (PRCB), and several system data structures. The IBR provides initial configuration information for the core and integrated peripherals, pointers to the system data structures and the first instruction to be executed after processor initialization, and checksum words that the processor uses in its self-test routine. In addition to the IBR and PRCB, the required data structures are the: • • • • • • • 5.2.3 System Procedure Table Control Table Interrupt Table Fault Table User Stack (application dependent) Supervisor Stack Interrupt Stack Memory Controller Initialization Since the i960 RM/RN I/O processor Memory Controller is integral to the design and operation of the IQ80960RM/RN platform, the operational parameters for Bank 0 and Bank 1 are established immediately after processor core initialization. Memory Bank 0 is associated with the ROM on the IQ80960RM/RN platform. Memory Bank 1 is associated with the UART and the LED Control Register. Parameters such as Bank Base Address, Read Wait States, and Write Wait States must be established to ensure the proper operation of the IQ80960RM/RN platform. The Memory Controller is initialized so as to be consistent with the IQ80960RM/RN platform memory map shown in Figure 4-2. 5.2.4 SDRAM Initialization SDRAM initialization includes setting operational parameters for the SDRAM controller, and sizing and clearing the installed SDRAM configuration. To configure the system properly, Presence Detect data is read from the EEPROM of the SDRAM module, using the 80960RM/RN I2C Bus Interface Unit. Presence Detect data includes the number and size of SDRAM banks present on the installed module. On power-up, 64 bytes of Presence Detect data are read and validated. The SDRAM controller is then configured by setting the base address of SDRAM, the boundary limits for each SDRAM bank, the refresh cycle interval, and the output buffer drive strength. Once the SDRAM controller is configured, the SDRAM is cleared in preparation for the C language runtime environment. The actual SDRAM size is stored for later use (e.g., to establish the size of the IQ80960RM/RN platform PCI Slave image). The SDRAM controller is initialized to be consistent with the IQ80960RM/RN platform memory map shown in Figure 4-2. 5-2 IQ80960RM/RN Evaluation Board Manual MON960 Support for IQ80960RM/RN 5.2.5 Primary PCI Interface Initialization The IQ80960RM/RN platform is a multi-function PCI device. On the primary PCI bus, two functions (from a PCI Configuration Space standpoint) are supported. • Function 0 is the PCI-to-PCI Bridge of the i960 RM/RN I/O processor, which optionally provides access capability between the primary PCI bus and the secondary PCI bus. • Function 1 is the Primary ATU which provides access capability between the primary PCI bus and the local i960 bus. The platform can be initialized into one of four modes. Modes 0 and 3 are described below. Table 5-1. Initialization Modes RST_MODE#/ SW1-1 RETRY/ SW1-2 Initialization Mode Primary PCI Interface i960 Core Processor 0/ON 0/ON Mode 0 Accepts Transactions Held in Reset 0/ON 1/OFF Mode 1 Retries All Configuration Transactions Held in Reset 1/OFF 0/ON Mode 2 Accepts Transactions Initializes 1/OFF 1/OFF Mode 3 (default) Retries All Configuration Transactions Initializes When the IQ80960RM/RN is operating in Mode 0, the processor core is held in reset, allowing register defaults to be used on the Primary PCI interface. This mode is used to program the onboard Flash with either IxWORKS* or MON960. When the IQ80960RM/RN platform is operating in Mode 3, the Configuration Cycle Disable bit in the Extended Bridge Control Register (EBCR) is set after IQ80960RM/RN processor reset. In this mode, the IQ80960RM/RN platform sends PCI Retries when the PCI host attempts to access the platform’s Configuration Space. This mode allows the IQ80960RM/RN processor time to initialize its internal registers. The processor remains in this mode until the Configuration Cycle Disable bit in the Extended Bridge Control Register (EBCR) is cleared. For this reason, and to prevent PCI host problems, Primary PCI initialization occurs at the earliest possible opportunity after Memory and SDRAM controller initialization. 5.2.6 Primary ATU Initialization Primary ATU (Bridge) initialization includes initialization by the 80960JT core and initialization by the PCI host processor. Local initialization occurs first and consists mainly of establishing the operational parameters for access to the local IQ80960RM/RN platform bus. The Primary Inbound ATU Limit Register (PIALR) is initialized to establish the block size of memory required by the Primary ATU. The PIALR value is based on the installed SDRAM configuration. The Primary Inbound ATU Translate Value Register (PIATVR) is initialized to establish the translation value for PCI-to-Local accesses. The PIATVR value is set to reference the base of local SDRAM. The Primary Outbound Memory Window Value Register (POMWVR) is initialized to establish the translation value for Local-to-PCI accesses. The POMWVR value remains at its default value of “0” to allow the IQ80960RM/RN platform to access the start of the PCI Memory address map, which is typically occupied by PCI host memory. Likewise, the Primary Outbound I/O Window Value Register (POIOWVR) remains at its default value of “0” to allow the IQ80960RM/RN platform to access the start of the PCI I/O address map. PCI Doorbell-related parameters are also established to allow for communication between the IQ80960RM/RN platform and a PCI bus master using the doorbell mechanism. IQ80960RM/RN Evaluation Board Manual 5-3 MON960 Support for IQ80960RM/RN By default, Primary Outbound Configuration Cycle parameters are not established. The ATU Configuration Register (ATUCR) is initialized to establish the operational parameters for the Doorbell Unit and ATU interrupts (both primary and secondary), and to enable the primary and secondary ATUs. The PCI host is responsible for allocating PCI address space (Memory, Memory Mapped I/O, and I/O), and assigning the PCI Base addresses for the IQ80960RM/RN platform. 5.2.7 PCI-to-PCI Bridge Initialization PCI-to-PCI Bridge initialization includes initialization by the 80960JT core and initialization by the PCI host processor. Local initialization occurs first and consists mainly of establishing the operational parameters for the secondary PCI interface of the PCI-to-PCI bridge. On the IQ80960RM/RN platform, the secondary PCI bus is configured to consist of private devices (not visible to PCI host configuration cycles). To support a private secondary PCI bus, the Secondary IDSEL Select Register (SISR) is initialized to prevent the secondary PCI address bits [20:16] from being asserted during conversion of PCI Type 1 configuration cycles on the primary PCI bus to PCI Type 0 configuration cycles on the secondary PCI bus. Secondary PCI bus masters are prevented from initiating transactions that will be forwarded to the primary PCI interface. The PCI host is responsible for assigning and initializing the PCI bus numbers, allocating PCI address space (Memory, Memory Mapped I/O, and I/O), and assigning the IRQ numbers to valid interrupt routing values. 5.2.8 Secondary ATU Initialization Secondary ATU (Bridge) initialization consists mainly of establishing the operational parameters for access between the local IQ80960RM/RN platform bus and the secondary PCI devices. The Secondary Inbound ATU Base Address Register (SIABAR) is initialized to establish the PCI base address of IQ80960RM/RN platform local memory from the secondary PCI bus. By convention, the secondary PCI base address for access to IQ80960RM/RN platform local memory is “0”. The Secondary Inbound ATU Limit Register (SIALR) is initialized to establish the block size of memory required by the secondary ATU. The SIALR value is based on the installed SDRAM configuration. The Secondary Inbound ATU Translate Value Register (SIATVR) is initialized to establish the translation value for Secondary PCI-to-Local accesses. The SIATVR value is set to reference the base of local SDRAM. The Secondary Outbound Memory Window Value Register (SOMWVR) is initialized to establish the translation value for Local-to-Secondary PCI accesses. The SOMWVR value is left at its default value of “0” to allow the IQ80960RM/RN platform to access the start of the PCI Memory address map. Likewise, the Secondary Outbound I/O Window Value Register (SOIOWVR) is left at its default value of “0” to allow the IQ80960RM/RN platform to access the start of the PCI I/O address map. On the secondary PCI bus, the IQ80960RM/RN platform assumes the duties of PCI host and, as such, is required to configure the devices of the secondary PCI bus. Secondary Outbound Configuration Cycle parameters are established during secondary PCI bus configuration. Secondary PCI bus configuration is accomplished via MON960 Extension routines. 5-4 IQ80960RM/RN Evaluation Board Manual MON960 Support for IQ80960RM/RN 5.3 MON960 Kernel The MON960 Kernel (monitor) provides the IQ80960RM/RN user with a software platform on which application software can be developed and run. The monitor provides several features available to the IQ80960RM/RN user to speed application development. Among the available features are: • Communication with a terminal or terminal emulation package on a host computer through a serial cable with automatic baud rate detection • Communication with a software debugger such as GDB960 (available from Intel) using the Host Debugger Interface (HDI) software interface • Communication with the host computer via the primary PCI bus • Downloads of ELF object files via the primary PCI bus or via the serial console port at rates up to 115,200 baud • • • • • 5.4 Downloads of ELF object files via the primary PCI bus On-board erasure and programming of Intel 28F016S5 Flash ROM Memory display and modification capability Breakpoint and single-step capability to support debugging of user code Disassembly of i960 processor instructions MON960 Extensions The monitor has been extended to include the secondary PCI bus initialization and also the BIOS routines which are contained in the PCI BIOS Specification Revision 2.1. 5.4.1 Secondary PCI Initialization MON960 extensions are responsible for initializing the devices on the secondary PCI bus of the IQ80960RM/RN platform. Secondary PCI initialization involves allocating address spaces (Memory, Memory Mapped I/O, and I/O), assigning PCI base addresses, assigning IRQ values, and enabling PCI mastership. MON960 does not support devices containing PCI-to-PCI bridges and hierarchical buses. IQ80960RM/RN Evaluation Board Manual 5-5 MON960 Support for IQ80960RM/RN 5.4.2 PCI BIOS Routines MON960 includes PCI BIOS routines to aid application software initialization of the secondary PCI bus. The supported BIOS functions are described in the subsections that follow. sysPCIBIOSPresent sysFindPCIDevice sysFINDPCIClassCode sysGenerateSpecialCycle sysReadConfigByte sysReadConfigWord sysReadConfigDword sysWriteConfigByte sysWriteConfigWord sysWriteConfigDword sysGetIrqRoutingOptions sysSetPCIIrq These functions preserve, as closely as possible, the parameters and return values described in the PCI Local Bus Specification Revision 2.1. Functions that return multiple values do so by filling in the fields of a structure passed by the calling routine. You can access these functions via a calls instruction. The system call indices are defined in the MON960 source file PCI_BIOS.H. The function prototypes are defined in the IQRP_ASM.H file. 5.4.2.1 sysPCIBIOSPresent This function allows the caller to determine whether the PCI BIOS interface function set is present, and the current interface version level. It also provides information about the hardware mechanism used for accessing configuration space and whether or not the hardware supports generation of PCI Special Cycles. Calling convention: int sysPCIBIOSPresent ( PCI_BIOS_INFO *info ); Return values: This function always returns SUCCESSFUL. 5-6 IQ80960RM/RN Evaluation Board Manual MON960 Support for IQ80960RM/RN 5.4.2.2 sysFindPCIDevice This function returns the location of PCI devices that have a specific Device ID and Vendor ID. Given a Vendor ID, a Device ID, and an Index, the function returns the Bus Number, Device Number, and Function Number of the Nth Device/Function whose Vendor ID and Device ID match the input parameters. Calling software can find all devices having the same Vendor ID and Device ID by making successive calls to this function starting with the index set to “0”, and incrementing the index until the function returns DEVICE_NOT_FOUND. A return value of BAD_VENDOR_ID indicates that the Vendor ID value passed had a value of all “1”s. Calling convention: int sysFindPCIDevice ( int device_id, int vendor_id, int index ); Return values: This function returns SUCCESSFUL if the indicated device is located, DEVICE_NOT_FOUND if the indicated device cannot be located, or BAD_VENDOR_ID if the vendor_id value is illegal. 5.4.2.3 sysFindPCIClassCode This function returns the location of PCI devices that have a specific Class Code. Given a Class Code and an Index, the function returns the Bus Number, Device Number, and Function Number of the Nth Device/Function whose Class Code matches the input parameters. Calling software can find all devices having the same Class Code by making successive calls to this function starting with the index set to “0”, and incrementing the index until the function returns DEVICE_NOT_FOUND. Calling convention: int sysFindPCIClassCode ( int class_code, int index ); Return values: This function returns SUCCESSFUL when the indicated device is located, or DEVICE_NOT_FOUND when the indicated device cannot be located. IQ80960RM/RN Evaluation Board Manual 5-7 MON960 Support for IQ80960RM/RN 5.4.2.4 sysGenerateSpecialCycle This function allows for generation of PCI Special Cycles. The generated special cycle is broadcast on a specific PCI Bus in the system. PCI Special Cycles are not supported on the IQ80960RM/RN platform secondary PCI bus. Calling convention: int sysGenerateSpecialCycle ( int bus_number, int special_cycle_data ); Return values: Since PCI Special Cycles are not supported by the IQ80960RM/RN platform, this function always returns FUNC_NOT_SUPPORTED. 5.4.2.5 sysReadConfigByte This function allows the caller to read individual bytes from the configuration space of a specific device. Calling convention: int sysReadConfigByte ( int bus_number, int device_number, int function_number, int register_number, UINT8 /* 0,1,2,...,255 */ *data ); Return values: This function returns SUCCESSFUL when the indicated byte was read correctly, or ERROR when there is a problem with the parameters. 5-8 IQ80960RM/RN Evaluation Board Manual MON960 Support for IQ80960RM/RN 5.4.2.6 sysReadConfigWord This function allows the caller to read individual shorts (16 bits) from the configuration space of a specific device. The Register Number parameter must be a multiple of two (i.e., bit 0 must be set to “0”). Calling convention: int sysReadConfigWord ( int bus_number, int device_number, int function_number, int register_number, UINT16 /* 0,2,4,...,254 */ *data ); Return values: This function returns SUCCESSFUL when the indicated word was read correctly, or ERROR when there is a problem with the parameters. 5.4.2.7 sysReadConfigDword This function allows the caller to read individual longs (32 bits) from the configuration space of a specific device. The Register Number parameter must be a multiple of four (i.e., bits 0 and 1 must be set to “0”). Calling convention: int sysReadConfigDword ( int bus_number, int device_number, int function_number, int register_number, /* 0,4,8,...,252 */ UINT32 *data ); Return values: This function returns SUCCESSFUL when the indicated long was read correctly, or ERROR when there is a problem with the parameters. IQ80960RM/RN Evaluation Board Manual 5-9 MON960 Support for IQ80960RM/RN 5.4.2.8 sysWriteConfigByte This function allows the caller to write individual bytes to the configuration space of a specific device. Calling convention: int sysWriteConfigByte ( int bus_number, int device_number, int function_number, int register_number, UINT8 /* 0,1,2,...,255 */ *data ); Return values: This function returns SUCCESSFUL when the indicated byte was written correctly, or ERROR when there is a problem with the parameters. 5.4.2.9 sysWriteConfigWord This function allows the caller to write individual shorts (16 bits) to the configuration space of a specific device. The Register Number parameter must be a multiple of two (i.e., bit 0 must be set to “0”). Calling convention: int sysWriteConfigWord ( int bus_number, int device_number, int function_number, int register_number, UINT16 /* 0,2,4,...,254 */ *data ); Return values: This function returns SUCCESSFUL when the indicated word was written correctly, or ERROR when there is a problem with the parameters. 5-10 IQ80960RM/RN Evaluation Board Manual MON960 Support for IQ80960RM/RN 5.4.2.10 sysWriteConfigDword This function allows the caller to write individual longs (32 bits) to the configuration space of a specific device. The Register Number parameter must be a multiple of four (i.e., bits 0 and 1 must be set to “0”). Calling convention: int sysWriteConfigDword ( int bus_number, int device_number, int function_number, int register_number, UINT32 /* 0,4,8,...,252 */ *data ); Return values: This function returns SUCCESSFUL when the indicated long was written correctly, or ERROR when there is a problem with the parameters. 5.4.2.11 sysGetIrqRoutingOptions The PCI Interrupt routing fabric on the IQ80960RM/RN platform is not reconfigurable (fixed mapping relationships); therefore, this function is not supported. Calling convention: int sysGetIrqRoutingOptions ( PCI_IRQ_ROUTING_TABLE *table ); Return values: This function always returns FUNC_NOT_SUPPORTED. IQ80960RM/RN Evaluation Board Manual 5-11 MON960 Support for IQ80960RM/RN 5.4.2.12 sysSetPCIIrq The PCI Interrupt routing fabric on the IQ80960RM/RN platform is not reconfigurable (fixed mapping relationships); therefore, this function is not supported. Calling convention: int sysSetPCIIrq ( int int int ); int_pin, irq_num, bus_dev Return values: This function always returns FUNC_NOT_SUPPORTED. 5.4.3 Additional MON960 Commands The following commands have been added to the UI interface of MON960 to support the IQ80960RM/RN platform. 5.4.3.1 print_pci Utility A print_pci command to MON960 is accessed through the MON960 command prompt. This command displays the contents of the PCI configuration space on a selected adapter on the secondary PCI interface or on the i960 RM/RN I/O processor itself. For more information on the meaning of the fields in PCI configuration space, refer to the PCI Local Bus Specification Revision 2.1. The syntax of this command is: pp 5.5 Diagnostics / Example Code IQ80960RM/RN platform diagnostic routines serve a twofold purpose: to verify proper hardware operation and to provide example code for users who need similar functions in their applications. Diagnostic routines fall into two categories: board level diagnostics and PCI expansion module diagnostics. 5.5.1 Board Level Diagnostics Board level diagnostics exercise all basic areas of the IQ80960RM/RN platform. Diagnostic routines include SDRAM tests, UART tests, LED tests, internal timer tests, I2C bus tests, and primary PCI bus tests. Primary PCI bus tests exercise the primary ATU, the PCI Doorbell unit, and the PCI DMA controller. Interrupts from both local and PCI sources are generated and handled. The PCI bus tests require an external test suite running on a PC to verify complete functionality of the IQ80960RM/RN platform. 5.5.2 Secondary PCI Diagnostics Secondary PCI diagnostics exercise the secondary PCI bus, thereby confirming hardware functionality, as well as illustrating the use of the PCI BIOS routines present in MON960. 5-12 IQ80960RM/RN Evaluation Board Manual Bill of Materials A This appendix identifies all components on the IQ80960RN Evaluation Platform (Table A-1), and the IQ80960RM Evaluation Platform (Table A-2). Table A-1. IQ80960RN Bill of Materials (Sheet 1 of 4) Item Qty Location Part Description Manufacturer Manufacturer Part # 1 1 U13 IC/SM 74ALS32 SOIC-14 National Semiconductor DM74ALS32M 2 1 U6 IC/SM 74ALS04 SOIC National Semiconductor DM74ALS04BM 3 1 U3 IC/SM 74ABT273 SOIC Texas Instruments SN74ABT273DW 4 2 U1,U2 IC/SM 74ABT573 SOIC Texas Instruments SN74ABT573DW 5 1 U16 IC/SM 74ALS08 SOIC National Semiconductor DM74ALS08M 6 1 U5 IC / SM 1488A SOIC National Semiconductor DS1488M 7 1 U7 IC / SM 1489A SOIC National Semiconductor DS1489AM 8 1 Q1 IC/SM Si9430DY SOIC-8 Siliconix Si9430DY 9 1 U9 IC/SM LVCMOS Fanout Buffr SSOP Motorola MPC9140 10 1 U10 IC/SM LM339 SOIC-14 National Semiconductor LM339M 11 1 U8 IC/SM MAX1651CSA SOIC-8 Maxim MAX1651CSA 12 1 U14 IC/SM MAX712CSE SOIC-16 Maxim MAX712CSE 13 1 U17 IC/SM MAX767CAP SOIC Maxim MAX767CAP 14 1 U15 PROCESSOR (from Intel) 80960RN Intel TL16C550AFN 15 1 U12 VLSI I/O UART 16C550 PLCC Texas Instruments 16 1 C65 CAP SM, 0.47 µF (1206) Philips Philips 12062F474Z9BB0 15 C2, C3, C10, C11, C18, C19, C26, C27, C55, C58, C61, C68, C77, C83, C96 CAP SM, 0.01 µF (0805) Kemet C0805C103K5RAC 17 IQ80960RM/RN Evaluation Board Manual A-1 Bill of Materials Table A-1. IQ80960RN Bill of Materials (Sheet 2 of 4) Item A-2 Qty Location Part Description Manufacturer Manufacturer Part # 18 79 C1, C4, C5, C6, C7, C8, C9, C12, C13, C14, C15, C16, C17, C20, C21, C22, C23, C24, C25, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C48, C49, C50, C51, C53, C59, C62, C66, C67, C69, C70, C71, C73, C79, C80, C81, C85, C86, C87, C94, C95, C97, C98, C99, C100, C101, C102, C103, C104, C105, C106, C107, C108, C109, C111, C112, C113, C115, C116, C114, C117 CAP SM, 0.1 µF (0805) Philips 08052R104K8BB2 19 1 C110 CAP SM, 18 pF (0805) Kemet C0805C180J5GAC 20 2 R27, R28 R/SM 1/10 W 5% 1 ohm (0805) Dale CRCW0805100JT 21 1 R60 R/SM 1/10 W 5% 10 ohm (0805) Dale CRCW08051000JT 22 1 R25 R/SM 1/10 W 5% 1 Kohm (0805) Dale CRCW08051001FRT 23 4 R35, R39, R58, R59 R/SM 1/10 W 5% 10 Kohm (0805) Dale CRCW08051002FRT 24 2 R24, R32 R/SM 1/10 W 5% 100 Kohm (0805) Dale CRCW08051003FRT 25 1 R20 R/SM 1/10 W 1% 150 ohm (0805) Dale CRCW08051500FRT 26 3 R14, R41, R42 R/SM 1/10 W 5% 1.5 Kohm (0805) Dale CRCW0805152JT 27 1 R18 R/SM 1/10 W 5% 1.6 Kohm (0805) Dale CRCW0805162JT 28 2 R50, R51 R/SM 1/10 W 5% 22 ohm (0805) Dale CRCW0805220JT 29 1 R34 R/SM 1/10 W 5% 22 Kohm (0805) Dale CRCW0805223JT 30 1 R37 R/SM 1/10 W 5% 24 ohm (0805) Dale CRCW0805240JT 31 1 R47 R/SM 1/10 W 5% 2.4 Kohm (0805) Dale CRCW0805242JT IQ80960RM/RN Evaluation Board Manual Bill of Materials Table A-1. IQ80960RN Bill of Materials (Sheet 3 of 4) Item Qty Location Part Description Manufacturer Manufacturer Part # 32 2 R2, R57 R/SM 1/10 W 5% 2.7 Kohm (0805) Dale CRCW0805272JT 33 1 R19 R/SM 1/10 W 5% 330 ohm (0805) Dale CRCW0805331JT 34 1 R29 R/SM 1/10 W 5% 36 ohm (0805) Dale CRCW0805360JT 35 1 R17 R/SM 1/10 W 5% 470 ohm (0805) Dale CRCW 0805 471JT 36 2 R48, R49 R/SM 1/10 W 1% 4.7 Kohm (0805) Dale CRCW08054701FRT 37 1 R53 R/SM 1/10 W 5% 47 Kohm (0805) Dale CRCW0805473JT 38 1 R26 R/SM 1/10 W 5% 68 Kohm (0805) Dale CRCW0805683JT 39 4 R30, R43, R54, R56 R/SM 1/8 W 5% 10 ohm chip 1206 Dale CRCW1206100FT 40 5 J8, J9, J10, J11, J12 CONN SM/TH Mictor 43P Recptcl AMP 767054-1 41 4 J1, J2, J3, J4 CONN PCI 64BIT 5 V/PCB ThruHole AMP 145166-4 42 1 J5 CONN DIMM 168P/RAng/Socket/TH Molex 73790-0059 43 1 J7 CONN TJ6 PCB 6/6 LP thru hole KYCON GM-N-66 44 1 J13 CONN/FAN ASSY/Socket/ThruHole AMP 173981-03 45 1 J6 CONN Hdr 16 pin/w shell, pcb AMP 103308-3 46 4 Z1, Z2, Z3, Z4 Jumper JUMP2X1 Molex 22-54-1402 47 1 L1 Inductor/SM 47µH 20% Coilcraft D03340P-473 48 1 L2 Inductor/SM 3.3 µH 20% Coilcraft D03316P-332 49 1 S1 Switch/SM DIP4 Mors# DHS-4S Mors DHS-4S 50 1 U4 OSC 1.8432 MHz 1/2 - Thru hole Kyocera KH0HC1CSE 1.843 51 1 U18 Clock Chip CY7B9910-7SC Cypress CY7B9910-7SC 52 1 CR5 LED Green Hewlett Packard HLMP-3507$010 53 1 CR3 LED-Red Hewlett Packard HLMP3301$010 54 1 CR4 LED Green LP Hewlett Packard HLMP4740#010 55 2 CR1, CR2 LED-Red-Small Group Dialight 555-4001 56 2 Q2, Q3 Transistor/SM N-Channel Harris RFD16N05LSM 57 1 Q4 Transistor 2N6109 (Thru Hole) Motorola 2N6109 58 1 U19 SOCKET PLCC20 LP Surface Mount AMP 822269-1 60 8 BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8 Battery Clips/PC/Snap-In/AA Keystone #92 61 1 U19 PALLV16V8Z-20JI AMD PALLV16V8Z-20JI 62 1 U11 MEM Flash E28F016S5-090 TSOP Intel E28F016S5-090 63 8 BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8 Battery AA NiCd @ 600 mA/Hour SAFT NIC-AA-600-SAFT IQ80960RM/RN Evaluation Board Manual A-3 Bill of Materials Table A-1. IQ80960RN Bill of Materials (Sheet 4 of 4) A-4 Item Qty Location Part Description Manufacturer Manufacturer Part # 64 1 U15 HeatSink/Fan Assy 80960RM/RN Panasonic UDQFNBEOIF 65 1 C84 CAP SM, 0.22 µF (1206) Philips 12062E224M9BB2 66 3 C60, C75, C78 CAP TANT SM 220 µF, 10 V (7343) AVX TPSE227K010R010 67 4 C89, C90, C91, C93 CAP TANT SM 47 µF, 16 V (7343) AVX TPSD476K016R015 68 1 C63 CAP TANT SM 33 µF, 10 V (7343) Sprague 293D336X9016D2T 69 4 C57, C76, C88, C92 CAP TANT SM 4.7 µF, 35 V (7343) Sprague 293D475X9035D2T 70 1 C47 CAP TANT SM 22 µF, 20 V (7343) Sprague 293D226X9020D2T 71 1 C74 CAP TANT SM 1 µF, 16 V (3216) Sprague 293D105X0016A2T 72 2 C52, C54 CAP TANT SM 10 µF, 25/35 V Sprague 293D1060025D2T 73 1 C56 CAP TANT SM 100 µF 10 V (7343) AVX TPSD107K010R0100 74 1 C64 CAP TANT SM 330 µF 6.3 V (7343 AVX TPSE337K063R0100 75 1 C82 CAP SM, 0.047 µF (0805) Kemet C0805C473K5RAC 76 1 R46 Res/SM 1 W 1% 0.012 ohm (2512) Dale WSL-2512-R012 77 1 R21 Res/SM 1 W 1% 0.05 ohm (2512) Dale WSL-2512-R050 78 1 R52 Resistor/SM 1/2 W 5% 100 ohm Beckmen BCR 1/2 101 JT R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R33, R36, R38, R44, R45, Resistor Pk SM RNC4R8P 2.7 Kohm CTS 742083272JTR 79 16 80 2 R40, R55 Resistor Pk SM RNC4R8P 22 ohm CTS 742083220JTR 81 2 R15, R16 Resistor Pk SM RNC4R8P 470 ohm CTS 742083471JTR 82 1 R13 Resistor Pk SM RNC4R8P 1.5 Kohm CTS 742083152JTR 83 2 R22, R23 Resistor Pk SM RNC4R8P 30 ohm CTS 742083300JTR CMPSH3 84 1 CR9 Diode CMPSH3 Surface Mount Central Semiconductor 85 2 CR6, CR7 Diode SM / MBRS340T3 Motorola MBRS340T3 86 1 CR8 Diode/SM 1N4001 (CMR1-02) Central Semiconductor CMR1-02 87 1 J5 SDRAM, DIMM, ECC, 2Mx72, 16 MB Unigen UG52S7408GSG IQ80960RM/RN Evaluation Board Manual Bill of Materials Table A-2. IQ80960RM Bill of Materials (Sheet 1 of 4) Item Qty 1 1 U13 IC/SM 74ALS32 SOIC-14 National Semiconductor DM74ALS32M 2 1 U6 IC/SM 74ALS04 SOIC National Semiconductor DM74ALS04BM 3 1 U3 IC/SM 74ABT273 SOIC Texas Instruments SN74ABT273DW 4 2 U1, U2 IC/SM 74ABT573 SOIC Texas Instruments SN74ABT573DW 5 1 U16 IC/SM 74ALS08 SOIC National Semiconductor DM74ALS08M 6 1 U5 IC / SM 1488A SOIC National Semiconductor DS1488M 7 1 U7 IC / SM 1489A SOIC National Semiconductor DS1489AM 8 1 Q1 IC/SM Si9430DY SOIC-8 Siliconix Si9430DY 9 1 U9 IC/SM LVCMOS Fanout Buffr SSOP Motorola MPC9140 10 1 U10 IC/SM LM339 SOIC-14 National Semiconductor LM339M 11 1 U8 IC/SM MAX1651CSA SOIC-8 Maxim MAX1651CSA 12 1 U14 IC/SM MAX712CSE SOIC-16 Maxim MAX712CSE 13 1 U17 IC/SM MAX767CAP SOIC Maxim MAX767CAP 14 1 U15 PROCESSOR (frm Intel) i960RM Intel 15 1 U12 VLSI I/O UART 16C550 PLCC Texas Instruments TL16C550AFN 16 1 C65 CAP SM, 0.47 µF (1206) Philips Philips 12062F474Z9BB0 15 C2, C3, C10, C11, C18, C19, C26, C27, C55, C58, C61, C68, C77, C83, C96 CAP SM, 0.01 µF (0805) Kemet C0805C103K5RAC 17 Location IQ80960RM/RN Evaluation Board Manual Part Description Manufacturer Manufacturer Part # A-5 Bill of Materials Table A-2. IQ80960RM Bill of Materials (Sheet 2 of 4) Item A-6 Qty Location Part Description Manufacturer Manufacturer Part # 18 79 C1, C4, C5, C6, C7, C8, C9, C12, C13, C14, C15, C16, C17, C20, C21, C22, C23, C24, C25, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C48, C49, C50, C51, C53, C59, C62, C66, C67, C69, C70, C71, C73, C79, C80, C81, C85, C86, C87, C94, C95, C97, C98, C99, C100, C101, C102, C103, C104, C105, C106, C107, C108, C109, C111, C112, C113, C114, C115, C116, C117 CAP SM, 0.1 µF (0805) Philips 08052R104K8BB2 19 1 C110 CAP SM, 18 pF(0805) Kemet C0805C180J5GAC 20 2 R27, R28 R/SM 1/10 W 5% 1 ohm (0805) Dale CRCW0805100JT 21 1 R60 R/SM 1/10 W 5% 10 ohm (0805) Dale CRCW08051000JT 22 1 R25 R/SM 1/10 W 5% 1 Kohm (0805) Dale CRCW08051001FRT R5, R6, R7 R8, R9, R10, R11, R12, R35, R39, R58, R59 R/SM 1/10 W 5% 10 Kohm (0805) Dale CRCW08051002FRT 23 12 24 2 R24, R32 R/SM 1/10 W 5% 100 Kohm (0805) Dale CRCW08051003FRT 25 1 R20 R/SM 1/10 W 1% 150 ohm (0805) Dale CRCW08051500FRT 26 3 R14, R41, R42 R/SM 1/10 W 5% 1.5 Kohm (0805) Dale CRCW0805152JT 27 1 R18 R/SM 1/10 W 5% 1.6 Kohm (0805) Dale CRCW0805162JT 28 2 R50, R51 R/SM 1/10 W 5% 22 ohm (0805) Dale CRCW0805220JT IQ80960RM/RN Evaluation Board Manual Bill of Materials Table A-2. IQ80960RM Bill of Materials (Sheet 3 of 4) Item Qty Location Part Description Manufacturer Manufacturer Part # 29 1 R34 R/SM 1/10 W 5% 22 Kohm (0805) Dale CRCW0805223JT 30 1 R37 R/SM 1/10 W 5% 24 ohm (0805) Dale CRCW0805240JT 31 1 R47 R/SM 1/10 W 5% 2.4 Kohm (0805) Dale CRCW0805242JT 32 1 R57 R/SM 1/10 W 5% 2.7 Kohm (0805) Dale CRCW0805272JT 33 1 R19 R/SM 1/10 W 5% 330 ohm (0805) Dale CRCW0805331JT 34 1 R29 R/SM 1/10 W 5% 36 ohm (0805) Dale CRCW0805360JT 35 1 R17 R/SM 1/10 W 5% 470 ohm (0805) Dale CRCW 0805 471JT 36 2 R48, R49 R/SM 1/10 W 1% 4.7 Kohm (0805) Dale CRCW08054701FRT 37 1 R53 R/SM 1/10 W 5% 47 Kohm (0805) Dale CRCW0805473JT 38 1 R26 R/SM 1/10 W 5% 68 Kohm (0805) Dale CRCW0805683JT 39 4 R30, R43, R54, R56 R/SM 1/8 W 5% 10 ohm chip 1206 Dale CRCW1206100FT 40 5 J8, J9, J10, J11, J12 CONN SM/TH Mictor 43P Recptcl AMP 767054-1 41 4 J1, J2, J3, J4 CONN PCI Slot 5V/PCB ThruHole AMP 145154-4 42 1 J5 CONN DIMM 168P/RAng/Socket/TH Molex 73790-0059 43 1 J7 CONN TJ6 PCB 6/6 LP thru hole KYCON GM-N-66 44 1 J13 CONN/FAN ASSY/Socket/ThruHole AMP 173981-03 45 1 J6 CONN Hdr 16 pin/w shell, pcb AMP 103308-3 46 4 Z1, Z2, Z3, Z4 Jumper JUMP2X1 Molex 22-54-1402 47 1 L1 Inductor/SM 47 µH 20% Coilcraft D03340P-473 48 1 L2 Inductor/SM 3.3 µH 20% Coilcraft D03316P-332 49 1 S1 Switch/SM DIP4 Mors# DHS-4S Mors DHS-4S 50 1 U4 OSC 1.8432 MHz 1/2 - Thru hole Kyocera KH0HC1CSE 1.843 51 1 U18 Clock Chip CY7B9910-7SC Cypress CY7B9910-7SC 52 1 CR5 LED Green Hewlett Packard HLMP-3507$010 53 1 CR3 LED-Red Hewlett Packard HLMP3301$010 54 1 CR4 LED Green LP Hewlett Packard HLMP4740#010 55 2 CR1, CR2 LED-Red-Small Group Dialight 555-4001 56 2 Q2, Q3 Transistor/SM N-Channel Harris RFD16N05LSM 57 1 Q4 Transistor 2N6109 (Thru Hole) Motorola 2N6109 58 1 U19 SOCKET PLCC20 LP Surface Mount AMP 822269-1 60 1 U11 SOCKET / SM / TSOP / 40 pin Meritec 980020-40-02 61 8 BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8 Battery Clips/PC/Snap-In/AA Keystone #92 IQ80960RM/RN Evaluation Board Manual A-7 Bill of Materials Table A-2. IQ80960RM Bill of Materials (Sheet 4 of 4) Item A-8 Qty Location Part Description Manufacturer Manufacturer Part # 62 1 U19 PALLV16V8Z-20JI AMD PALLV16V8Z-20JI 63 1 U11 MEM Flash E28F016S5-090 TSOP Intel E28F016S5-090 64 8 BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8 Battery AA NiCd @ 600 mA/Hour SAFT NIC-AA-600-SAFT 65 1 U15 HeatSink/Fan Assy 80960RN/RM Panasonic UDQFNBEOIF 66 3 C84 CAP SM, 0.22 µF (1206) Philips 12062E224M9BB2 67 3 C60, C75, C78 CAP TANT SM 220 µF, 10 V (7343) AVX TPSE227K010R010 68 4 C89, C90, C91, C93 CAP TANT SM 47 µF, 16 V (7343) AVX TPSD476K016R015 69 1 C63 CAP TANT SM 33 µF, 10 V (7343) Sprague 293D336X9016D2T 70 4 C57, C76, C88, C92 CAP TANT SM 4.7 µF, 35 V (7343) Sprague 293D475X9035D2T 71 1 C47 CAP TANT SM 22 µF, 20 V (7343) Sprague 293D226X9020D2T 72 1 C74 CAP TANT SM 1 µF, 16 V (3216) Sprague 293D105X0016A2T 73 2 C52, C54 CAP TANT SM 10 µF, 25/35 V Sprague 293D1060025D2T 74 1 C56 CAP TANT SM 100 µF 10 V (7343) AVX TPSD107K010R0100 75 1 C64 CAP TANT SM 330 µF 6.3 V (7343) AVX TPSE337K063R0100 76 1 C82 CAP SM, 0.047 µF (0805) Kemet C0805C473K5RAC 77 1 R46 Res/SM 1 W 1% 0.012 ohm (2512) Dale WSL-2512-R012 78 1 R21 Res/SM 1 W 1% 0.05 ohm (2512) Dale WSL-2512-R050 79 1 R52 Resistor/SM 1/2 W 5% 100 ohm Beckmen BCR 1/2 101 JT 80 7 R1, R31, R33, R36, R38, R44, R45 Resistor Pk SM RNC4R8P 2.7 Kohm CTS 742083272JTR 81 2 R40, R55 Resistor Pk SM RNC4R8P 22 ohm CTS 742083220JTR 82 2 R15, R16 Resistor Pk SM RNC4R8P 470 ohm CTS 742083471JTR 83 1 R13 Resistor Pk SM RNC4R8P 1.5 Kohm CTS 742083152JTR 84 2 R22, R23 Resistor Pk SM RNC4R8P 30 ohm CTS 742083300JTR 85 1 CR9 Diode CMPSH3 Surface Mount Central Semiconductor CMPSH3 86 2 CR6, CR7 Diode SM / MBRS340T3 Motorola MBRS340T3 87 1 CR8 Diode/SM 1N4001 (CMR1-02) Central Semiconductor CMR1-02 88 1 J5 SDRAM, DIMM, ECC, 2Mx72, 16 MB Unigen UG52S7408GSG IQ80960RM/RN Evaluation Board Manual Schematics B This appendix includes schematics for the IQ80960RN (Table B-1) and IQ80960RM (Table B-2). Table B-1. IQ80960RN Schematics List Page Schematic Title B-2 Decoupling and 3.3V Power B-3 Primary PCI Interface B-4 Memory Controller B-5 Flash ROM, UART, & LEDs B-6 Logic Analyzer I/F B-7 SDRAM 168-Pin DIMM B-8 Secondary PCI/960 Core B-9 Secondary PCI Bus 1/2 B-10 Secondary PCI Bus 3/4 B-11 SPCI Pull-ups B-12 Battery/Monitor IQ80960RM/RN Evaluation Board Manual B-1 D C B A 1 +5V CAP0805 0.1uF CAP0805 0.1uF C48 2 1 2 CAP0805 0.1uF C116 2 1 CAP0805 0.1uF C113 2 1 CAP0805 0.1uF CAP0805 0.1uF C87 2 1 CAP0805 0.1uF C71 2 1 CAP0805 0.1uF C44 2 1 CAP0805 0.1uF CAP0805 0.1uF C69 2 1 CAP0805 0.1uF C73 2 1 CAP0805 0.1uF C111 2 1 CAP0805 0.1uF C108 2 1 CAP0805 0.1uF C114 2 1 CAP0805 0.1uF C115 2 1 CAP0805 0.1uF C112 2 1 CAP0805 0.1uF C109 2 1 CAP0805 0.1uF C105 2 1 CAP0805 0.1uF C50 2 1 CAP0805 0.1uF C59 2 1 CAP0805 0.1uF C49 2 1 C107 1 CAP0805 0.1uF C106 2 1 2 CAP0805 0.1uF C117 2 1 CAP0805 0.1uF C99 2 1 CAP0805 0.1uF C62 2 1 +3V CAP0805 0.1uF C43 2 1 CAP0805 0.1uF C103 2 1 CAP0805 0.1uF C66 2 1 CAP0805 0.1uF C72 2 1 CAP0805 0.1uF C41 2 1 CAP0805 0.1uF C81 2 1 CAP0805 0.1uF C46 2 1 CAP0805 0.1uF C67 2 1 CAP0805 0.1uF C42 2 1 CAP0805 0.1uF C45 2 1 C80 1 CAP0805 0.1uF C79 2 1 2 CAP0805 0.1uF C70 2 1 C93 1 CAPT7343 47uF C85 2 1 2 +3V +5V C90 1 3 CAP0805 0.1uF CAP0805 0.1uF C1 2 1 CAP0805 0.1uF C7 2 1 CAP0805 0.1uF C8 2 1 CAP0805 0.1uF C9 2 1 CAP0805 0.1uF C15 2 1 CAP0805 0.1uF C16 2 1 CAP0805 0.1uF C17 2 1 CAP0805 0.1uF C23 2 1 CAP0805 0.1uF C24 2 1 CAP0805 0.1uF C25 2 1 CAP0805 0.1uF C31 2 1 CAPT7343 47uF C32 2 1 2 P33V {02,04,08,09} SPCI DECOUPLING 2 C91 1 4 CAP0805 0.1uF CAP0805 0.1uF C6 2 1 CAP0805 0.1uF C5 2 1 CAP0805 0.1uF C4 2 1 CAP0805 0.1uF C14 2 1 CAP0805 0.1uF C13 2 1 CAP0805 0.1uF C12 2 1 CAP0805 0.1uF C22 2 1 CAP0805 0.1uF C21 2 1 CAP0805 0.1uF C20 2 1 CAP0805 0.1uF C30 2 1 CAP0805 0.1uF C29 2 1 CAPT7343 47uF C28 2 1 C88 1 2 RAM3V {04,06,11} C33 1 5 CAP0805 0.1uF CAP0805 0.1uF C40 2 1 CAP0805 0.1uF C39 2 1 CAP0805 0.1uF C38 2 1 CAP0805 0.1uF C37 2 1 CAP0805 0.1uF C36 2 1 CAP0805 0.1uF C35 2 1 CAP0805 0.1uF C34 2 1 2 SDRAM DECOUPLING CAP0805 0.01uF C83 1 2 CAPT7343 4.7uF 5 R54 CAP1206 0.22uF C84 1 2 10 1/8W 5% 1 2 +5V 11 7 6 5 4 9 8 2 3 15 14 10 GND5 GND4 GND3 GND2 GND1 SYNC REF SS ON/OFF# VCC3 VCC2 VCC1 U17 6 DL LX DH BST FB CS PGND MAX767CAP 6 20 1 13 16 18 19 17 1 1 CAPT7343 220uF C60 1 2 3 2 3 2 2 CR9 3 CMPSH3 RFD16N05L Q2 RFD16N05L Q3 +5V 7 1 2 7 +3V 8 01 of 11 Sheet REV B 4/14/98 Date: 80960RN TP1 8 Name: DECOUPLING & 3.3V POWER Title: 1W 1% 0.012 NOTE: PINS 3-7 ARE VIAS 7 6 5 4 3 R46 1 2 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 MBRS340T3 C86 CR6 0.1uF CAP0805 1 2 2 4 L2 3.3uH COIL-SMT2 1 3 C75 1 2 1 IC DECOUPLING 2 CAPT7343 220uF C78 1 2 1 CAPT7343 220uF D C B A D C L5 P_FRAME L1 PDEVSEL# M5 PSTOP# P_LOCK P_RST 1 U18 16 18 Q0 Q1 7 8 Q4 15 11 Q3 Q2 10 Q5 Q6 CY7B9910-7 CLK 1 REF FB 13 3 FS 23 TEST Q7 19 B7 M4 RST# PLOCK# A7 PGNT# P_GNT E6 P_REQ PREQ# P_PAR N3 P_STOP H3 P_IDSEL PPAR PIDSEL L2 PTRDY# P_TRDY L3 P_IRDY PIRDY# P_DEVSEL V4 P_C/BE7 P_C/BE6 P_C/BE5 P_C/BE4 P_C/BE3 P_C/BE2 PC/BE7# V3 PC/BE6# PAD62 PFRAME# V1 W5 PC/BE4# PC/BE5# H4 PC/BE3# PAD61 D6 PAD31 P_AD31 C6 PAD30 P_AD30 PAD59 A6 P_AD29 PAD58 PAD29 B K1 PC/BE2# PAD60 Y4 PAD63 W2 P_AD63 W1 P_AD62 Y5 P_AD61 P_C/BE1 2 6 3 5 7 2 4 8 1 R40 22 6 3 R55 22 RNC4R8P 7 2 5 8 RNC4R8P 1 4 PAD47 U15 i960RN PRIMARY PCI SIGNALS PAD24 N5 H5 P_AD24 PC/BE1# H1 PAD23 Y3 P_AD60 E5 PAD28 P_AD28 G3 PAD27 PAD56 J5 PAD22 PAD57 P_AD59 P_AD27 PAD55 J3 PAD21 Y1 P_AD58 P_AD26 G2 PAD54 J2 PAD20 P_AD56 AA3 PAD53 P_AD55 AA2 PAD52 P_AD23 AA1 P_AD54 AB5 P_AD53 P_AD22 J1 PAD19 AA5 P_AD57 PAD26 P_AD19 AB4 P_AD52 P_AD21 PAD50 P_AD18 K5 PAD18 P_C/BE0 PAD17 R2 PAD16 P_AD20 0.1uF CAP0805 1 2 PAD51 AB3 P_AD51 AB1 P_AD50 PAD46 CLKD {09} CLKC {09} CLKB {08} CLKA {08} K4 P_AD17 K3 P_AD16 N2 P_AD15 N1 P_AD14 PAD14 PAD15 P_AD25 G1 PAD25 PAD49 P_AD49 AC5 C97 0.1uF CAP0805 1 2 PAD48 AC3 P_AD48 AC2 PAD45 P_AD46 AC1 AD5 P5 PAD13 PC/BE0# PAD12 P_AD47 C98 0.1uF CAP0805 1 2 PAD39 LOGIC_CLK {05} CLK_960 PAD11 PPCI PAD10 P_AD45 PAD41 PAD9 A PAD8 P_AD13 PAD42 AD1 PAD44 P_AD44 AD4 AD3 PAD40 AE3 PAD43 P_AD43 C100 0.1uF CAP0805 1 2 P_AD42 AE5 P_AD41 3 P4 P_AD12 P3 P_AD11 P1 P_AD10 R5 P_AD9 R3 P_AD8 R1 P_AD7 PAD7 P_AD40 PAD38 AE1 PAD37 PAD5 P_AD39 AE2 C101 0.1uF CAP0805 1 2 PAD4 P_AD38 PAD36 P_AD37 AF5 AF4 PAD35 AF3 PAD3 PAD33 PINTA# PINTB# PINTC# PINTD# PPAR64 PPERR# E8 D8 E7 C7 W3 M3 P_CLK C20 P_ACK64 V5 PACK64# P_SERR M1 PSERR# U5 PREQ64# P_REQ64 P_PERR P_PAR64 P_INTD P_INTC P_INTB P_INTA 27 +3V2 45 47 48 PAD12 PAD10 4 PACK64# PAD1 PAD3 AD5 +3V4 AD7 AD8 +5V1 62 +5V3 ACK64# 61 +5V2 60 59 GND5 58 AD1 57 56 AD3 55 54 P33V PAD5 53 PAD7 52 AD10 49 GND4 AD12 AD14 46 GND3 44 C/BE1# PAD14 +3V3 PC/BE1# 43 42 SERR# 41 40 PERR# 39 LOCK# PAD8 J14 5 36 35 34 33 TRDY# GND1 FRAME# +3V1 32 AD16 PREQ64# PAD0 PAD2 PAD4 PAD6 P33V PC/BE0# PAD9 PAD11 PAD13 P33V PAD15 PPAR P33V SBO# SDONE PAR AD11 AD6 +3V4 C/BE0# 62 61 60 59 +5V3 +5V2 REQ64# +5V1 AD2 58 AD0 57 AD4 56 GND5 55 54 53 52 GND4 49 AD9 48 47 +3V3 46 AD13 45 44 AD15 43 42 GND3 41 40 39 +3V2 STOP# 38 PSTOP# PTRDY# PFRAME# P33V PAD16 GND5 31 AD18 30 37 GND2 GND2 PPERR# P33V CONNPCI_B PAD18 38 +3V1 IRDY# GND1 PLOCK# PSERR# J14 +3V2 IDSEL AD22 29 AD20 28 PAD22 PAD20 27 26 P33V PIDSEL AD24 37 DEVSEL# 36 P33V PDEVSEL# 35 PIRDY# 34 33 C/BE2# 32 AD17 PAD17 AD19 31 +3V2 30 PC/BE2# P33V PAD19 AD23 C/BE3# +3V1 GND7 29 AD21 28 26 PAD23 PAD21 AD26 AD28 +3V1 AD30 GND3 GNT# +5V4 25 23 22 21 20 19 18 17 RST# GND2 GND1 24 GND4 PAD24 PAD26 PAD28 P33V PAD30 PGNT# 16 15 14 13 12 25 AD27 GND6 AD29 AD31 +5V3 REQ# GND5 CLK GND4 GND3 GND2 +5V3 +5V2 INTC# INTA# +5V1 TDI TMS +12V TRST# 24 AD25 PC/BE3# P33V PAD25 23 22 21 PAD29 19 18 17 16 15 14 13 12 20 PAD27 9 8 7 6 5 4 3 2 1 11 PRST# PINTC# PINTA# TD +5V 11 PRSNT2# CONNPCI_B 0.1uF CAP0805 1 2 10 PRSNT1# INTD# INTB# +5V2 +5V1 TDO GND1 TCK -12V N12V C95 10 PAD31 PREQ# 8 9 7 PINTB# 6 5 4 3 2 1 PINTD# TD +5V 5 6 J15 CONNPCI_A J15 CONNPCI_A 6 Z3 2 PRST# +5V PAD33 PAD35 PAD37 PAD39 PAD41 PAD43 PAD45 PAD47 PAD49 PAD51 PAD53 PAD55 PAD57 PAD59 PAD61 +12V AD53 AD55 GND3 AD57 AD59 +5V1 AD61 AD63 GND2 C/BE4# C/BE6# GND1 +5V2 AD49 AD51 AD41 AD35 2 1 94 93 92 91 3 J14 CONNPCI_B 7 68 PAD62 71 PAD58 74 PAD54 82 PAD44 7 74ALS08 U16 Sheet 8 02 of 11 4/14/98 REV B 11 8 6 J15 Date: 80960RN 13 12 74ALS08 U16 74ALS08 U16 SPARES 94 CONNPCI_A 8 Name: PRIMARY PCI INTERFACE Title: 9 10 AD32 93 GND8 92 91 AD34 90 GND7 GND6 88 AD36 87 89 5 +5V3 AD40 86 AD38 85 84 PAD32 RST# {11} AD48 GND4 AD44 83 AD42 PAD34 PAD36 PAD38 PAD40 PAD42 80 PAD46 AD46 81 GND5 79 AD50 77 PAD48 78 76 AD52 PAD50 +5V2 AD54 AD56 GND3 AD58 AD60 GND2 AD62 PAR64 +5V1 C/BE5# C/BE7# GND1 PAD52 75 73 PAD56 72 70 PAD60 69 67 PPAR64 66 65 63 64 4 +5V PC/BE5# PPCI PC/BE7# CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 74ALS08 U16 GND8 GND7 90 AD33 89 AD37 88 +5V3 87 GND6 86 AD39 85 84 GND5 83 AD43 82 AD47 81 AD45 80 79 78 77 76 GND4 75 74 73 72 71 70 69 68 67 66 PAD63 PC/BE4# 64 63 65 +5V 47uF CAPT7343 1 2 PC/BE6# JUMP1X2 1 C94 R58 P33V 4 C89 3 PAD2 P_AD6 T5 PAD6 P_AD36 C102 0.1uF CAP0805 1 2 P_AD35 C104 PAD32 P_AD32 AG2 PAD34 AF1 P_AD34 AG3 P_AD33 PAD1 T4 P_AD5 T3 P_AD4 T1 P_AD3 U3 P_AD2 U2 P_AD1 U1 P_AD0 PAD0 0.1uF CAP0805 1 2 10K 1/10W 5% 1 2 2 R39 1 10K 1/10W 5% 1 2 D C B A D C B 1 SCKE1 {06,11} SCKE0 {06,11} DCLKIN R50 1 C110 R51 1 1/10W 5% 22 2 1/10W 5% 22 2 18pF CAP0805 1 2 N29 N30 SA1 SA0 SBA0 SA0 SA1 SA2 SA3 SA4 SCE0 SDQM7 SCKE1 U30 M32 SDQM1 L29 SM2 SM1 SM0 SDQM0 SDQM2 U28 SDQM3 SM3 SDQM4 L28 SDQM6 M31 SDQM5 U29 V32 U32 SM4 SM5 SM6 SM7 M28 SCE1# SWE SCE1 T28 SCKE0 L32 M30 SWE# SCE0# SCAS SBA1 L30 N28 SA2 N32 SRAS P32 SA3 SA5 SA6 SCAS# P31 SA4 SRAS# P30 SA5 T30 P28 SA6 SA7 SA8 SA9 SA10 SA11 DCLKIN T31 R32 SA7 DQ61 DCLKOUT SBA1 R30 SA8 DQ63 DQ63 AH32 SBA0 R29 SA9 T32 R28 SA10 SA11 E21 A22 DQ62 AF28 DQ62 AF31 DQ61 DQ60 AE28 DQ60 DQ59 AE30 DQ59 DQ58 AD28 DQ58 DQ57 AD31 6 5 3 4 2 7 R13 1.5K 8 2 RNC4R8P 1 DQ54 S1 6 3 5 7 2 4 8 1 SWDIP4 AC32 DQ23 DQ57 DQ55 DQ56 DQ56 AC28 AC30 DQ31 AG32 DQ31 DQ30 AF30 DQ30 DQ29 AF32 DQ29 DQ28 AE29 DQ28 DQ27 AE32 DQ27 DQ26 AD30 DQ26 DQ25 AD32 DQ25 DQ24 AC29 DQ24 DQ53 DQ49 DQ50 U15 i960RN MEMORY CONTROLLER DQ55 DQ23 DQ48 3 RAD1/32BITPCI_EN# RAD2/32BITMEM_EN# RAD3/RETRY RAD6/RST_MODE# Y30 DQ18 Y32 DQ52 DQ54 DQ22 AB30 DQ22 DQ47 DQ18 DQ17 DQ17 DQ16 W29 DQ16 DQ15 J29 DQ15 1/10W 5% 24 DQ14 AB28 DQ52 DQ45 J32 DQ14 DQ53 AB31 AA28 DQ51 DQ51 AA30 DQ21 AB32 DQ21 DQ20 AA29 DQ20 DQ19 AA32 DQ19 Y28 DQ50 Y31 DQ49 W28 DQ48 J28 DQ47 DQ46 DQ46 J30 DQ44 DQ12 DCLKOUT DQ11 A DQ10 H28 DQ41 DQ9 DQ45 DQ43 DQ44 H31 G32 DQ40 DQ8 DQ13 H30 DQ13 DQ43 DQ42 A28 DQ42 C27 DQ41 A27 DQ40 R37 2 1 RAD15 RAD14 RAD14 D18 C18 RAD13 A18 RAD12 E17 RAD11 E15 RAD10 RAD9 C15 RAD7 RAD5 B13 4 RAD0 A13 RAD1/32BITPCI_EN# RAD4/STEST A14 E13 RAD3/RETRY RAD2/32BITMEM_EN# C13 RAD0 RAD1/32BITPCI_EN# RAD2/32BITMEM_EN# RAD3/RETRY RAD4/STEST RAD5 RAD6/RST_MODE# RAD7 E14 D14 C14 RAD8 A15 RAD8 RAD9 RAD10 RAD11 RAD12 RAD13 RAD16 RAD15 RAD16 E18 B19 A19 RALE E19 ONCE# RCE0# RCE1# C19 ROE# RWE# SCB0 K32 A20 SCB1 K30 D20 SCB3 SCB4 K31 SCB2 SCB5 K28 V31 SCB6 V30 W32 SCB7 W30 C21 ONCE RALE RCE1 RCE0 RWE ROE SCB0 SCB1 SCB2 SCB3 SCB4 SCB5 SCB6 SCB7 RAD6/RST_MODE# DQ5 DQ38 E25 DQ37 A25 DQ5 DQ38 DQ36 DQ4 D24 DQ4 DQ39 DQ39 C26 H32 DQ12 C28 DQ11 E27 DQ10 B27 DQ9 E26 DQ8 A26 DQ7 DQ7 DQ37 B25 DQ35 DQ3 A24 DQ3 SDRAM {05,06} DQ2 DQ6 E24 DQ36 C24 DQ35 DQ34 DQ34 E23 B23 DQ32 DQ32 E22 DQ33 DQ33 DQ1 C23 DQ2 A23 DQ1 D22 DQ0 DQ0 C25 DQ6 4 Z2 2 JUMP1X2 1 RAD {04,05} RAD0 TP2 RAD4/STEST 1 3 1.5K 1/10W 5% 1 2 2 5 R42 5 Z1 2 JUMP1X2 1 1/10W 5% 36 RWE# RCE1# ROMA18 SCL {06,07} SDA {06,07} ROMA {04} DCLKOUT R29 2 1 R41 1 1.5K 1/10W 5% 1 2 +3V 2.7K 1/10W 5% 1 2 11 R57 U6 SCLK SDA OE CLKIN 10 6 74ALS04 25 24 38 11 U9 13 12 13 5 4 2 1 U13 28 21 45 44 41 40 36 35 32 31 18 17 14 13 9 8 5 4 12 74ALS32 U13 74ALS04 U6 74ALS32 U13 74ALS32 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 MPC9140/CDC318 6 11 6 3 9 10 R22 30 RNC4R8P R23 30 RNC4R8P 8 4 3 2 1 4 3 2 1 7 Sheet 8 03 MEMORY CONTROLLER 4/14/98 Date: 80960RN DCLK3 {06} DCLK2 {06} DCLK1 {06} DCLK0 {06} DRAMCLK_LA {05} DCLKIN 8 Name: Title: SEL_LED# {04} CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 IOR# {04} 74ALS32 U13 IOW# {04} SELUART# {04} 5 6 7 8 5 6 7 8 7 of 11 REV B D C B A D C B A 1 RAD {03,05} 3 4 5 6 7 8 9 11 RAD15 RAD14 RAD13 RAD12 RAD11 RAD10 RAD9 RALE RALE RAD3/RETRY RAD4/STEST RAD5 1D OC LE 8D 7D 6D 5D 4D 3D 2D 1D 4D LE 8D RCE0# 1 OC 11 9 6D 8 7D 7 6 5D 5 2D 4 3D 3 RAD6/RST_MODE# 2 1 2 RAD16 2 U2 18 19 12 13 14 15 16 17 18 19 14 Z4 8Q 12 7Q 13 6Q 3Q 17 16 4Q 5Q 15 2Q 1Q 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 2 JUMP1X2 1 74ABT573 U1 74ABT573 4 3 RAD11 RAD10 +5V 8 13 14 A10 15 ROMA12 ROMA11 ROMA10 ROMA9 19 A5 20 21 A3 RAD5 RAD4/STEST RAD3/RETRY ROE# RWE# RAD0 RAD1/32BITPCI_EN# 3 A4 A6 A0 9 CE 37 OE 38 WE 24 A2 23 A1 22 18 RAD6/RST_MODE# RAD2/32BITMEM_EN# 17 RAD7 A7 16 A8 A9 A11 A12 A13 7 ROMA13 A14 6 A16 5 A15 4 ROMA14 ROMA15 ROMA16 A19 A18 3 A17 2 ROMA18 ROMA17 1 ROMA19 RAD8 ROMA17 ROMA18 ROMA19 ROMA20 U11 12 36 28 32 D2 27 26 D1 D0 25 D3 D4 D7 35 34 D6 D5 33 RP RY/BY RAD9 RAD10 RAD11 RAD12 RAD13 RAD14 RAD15 RAD16 4 3 1 4 74ALS04 U6 I_RST# {05,07} I_RST# {05,07} FAIL# {07} IOR# {03} IOW# {03} U6 2 5 SEL_LED# {03} 74ALS04 RAD9 U12 74ALS04 6 8D 7D 1 R17 1 U3 R18 1 1/10W 5% 330 R19 2 1 1/10W 5% 1.6K 2 1/10W 5% 470 2 CLR RXCLK RI CD 33 18 19 27 32 17 10 43 42 41 40 11 38 35 37 36 13 2 12 CR5 LED GREEN 1 2 CR4 +5V 6 LED4SM 6 P33V {01,02,08,09} +5V 6 1489A 3 1489A RAM3V {01,06,11} +5V LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 LED GREEN LP 1 2 CR3 LED RED 1 2 6Q 15 16 7Q 19 8Q 5Q 2Q 5 6 3Q 4Q 9 1Q DDIS 26 INT XTAL1 XTAL2 TXRDY RXRDY BAUDOUT 74ABT273 11 CLK RAD16 18 RAD15 17 RAD14 14 6D 5D 3D 8 4D 7 1D 4 2D 3 RAD13 13 RAD12 RAD11 RAD10 U6 5 RST IOW IOW IOR IOR CS0 CS1 CS2 A0 28 AS 39 21 20 25 24 14 ROMA9 16 15 +5V ROMA10 ROMA11 ROMA12 RAD0 A1 31 RXD OP1 ROMA13 D1 D2 D3 OP2 DTR RTS TXD RAD1/32BITPCI_EN# 30 VPP 11 5 RAD12 D4 D5 16C550 ROMA14 +12V 6 RAD13 D6 D7 DSR SELUART# {03} 7 RAD14 2 8 RAD15 RAD9 9 RAD16 RAD2/32BITMEM_EN# 29 A2 40 A20 U4 O 5 ROMA15 E28F016S5 E/D OSC1.8432MHz CTS ROMA20 ROMA {03} 1 D0 ROMA16 R59 U7 2 9 U7 5 2 5 RNC4R8P CR2 LED4SM 4 13 12 10 9 5 4 2 8 IN4B IN4A IN3B IN3A IN2B IN1B IN1A 74ALS04 U6 4 1 +5V U5 1488 CR2 3 OUTD OUTC OUTB OUTA 7 11 8 6 3 7 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 LED4SM 2 2 7 1 10K 1/10W 5% 1 2 8 7 LED7 1 8 6 5 LED6 7 CR2 LED4SM 4 5 CR2 LED4SM 1 8 CR1 LED4SM 3 6 CR1 LED4SM 4 5 U7 Sheet 8 04 of 11 4/14/98 REV B 13 Date: 80960RN U7 10 Name: FLASH ROM, UART, & LEDS Title: 11 1489A 8 J7 CONNJ6-6P 8 IRQUART# {07} 6 5 4 3 2 1 SPARES 1489A CR1 LED4SM 3 6 4 3 LED5 8 7 R16 470 2 1 LED4 RNC4R8P LED3 6 5 LED2 2 1 LED0 4 3 LED1 R15 470 CR1 9 12 D C B A D C B A 1 SDRAM {03,06} 1 SM1 SM0 SCB7 SCB6 SCB5 SCB4 SCB3 SCB2 SCB1 SCB0 9 10 11 12 13 14 15 16 17 18 19 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 2 SM2 8 DQ11 DQ55 DQ54 27 26 SA7 SA6 SA5 SA4 GND2 40 41 27 26 25 24 23 22 21 20 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 4 DQ56 28 SA8 28 DQ40 GND4 42 43 GND5 GND3 DQ57 29 SA9 29 DQ41 SA0 SA1 SA2 20 21 22 23 24 25 41 J11 GND4 42 43 GND5 GND3 GND2 40 DQ58 30 SA10 30 DQ42 39 DQ59 31 SA11 31 DQ43 GND1 DQ60 32 32 SA3 DQ61 33 SRAS# 33 DQ44 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ62 DQ45 34 SCAS# DQ63 DQ16 34 CLK1 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ46 35 MICTOR CLK0 SWE# 36 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 4 35 3 3 DQ47 J9 SM3 7 DQ12 39 SM4 6 CLK1 SM6 SM5 5 DQ14 DQ13 36 SM7 GND1 MICTOR CLK0 4 DRAMCLK_LA {03} DQ15 3 2 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 39 41 GND4 42 43 GND5 GND3 GND2 40 J12 CLK1 GND1 MICTOR CLK0 5 17 18 19 SCE1# SBA1 SBA0 CLK0 21 20 SREQ1# SREQ0# 22 SREQ2# 24 SREQ4# 23 25 SREQ5# SREQ3# 26 28 SGNT2# SGNT0# 29 SGNT3# 27 30 SGNT4# SGNT1# 31 SGNT5# 32 33 34 35 6 J10 GND1 39 40 GND2 41 GND3 42 GND4 43 GND5 MICTOR 6 36 CLK1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 SCE0# LOGIC_CLK {02} SPCI {07,08,09,10} 5 I_RST# {04,07} RAD {03,04} 7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 RAD16 RALE RCE0# RCE1# ROE# RWE# RALE RAD0 39 GND5 8 05 of 11 Sheet REV B 4/14/98 Date: 8 Name: LOGIC ANALYZER I/F 43 GND2 40 41 GND3 GND4 42 80960RN J8 CLK1 GND1 MICTOR CLK0 Title: 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 19 RAD1/32BITPCI_EN# 18 RAD2/32BITMEM_EN# 17 RAD3/RETRY RAD4/STEST RAD5 RAD6/RST_MODE# RAD7 RAD8 RAD9 RAD10 RAD11 RAD12 RAD13 RAD14 RAD15 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 7 D C B A D C B A 1 1 2 2 SDRAM {03,05} RAM3V {01,04,11} 3 4 5 DQ1 DQ2 DQ3 11 15 16 17 DQ12 DQ13 CB1 NC1 DCLK0 {03} SBA1 SA10 SA8 SA6 SA4 SA2 SA0 SCE0# 29 SM1 NC3 A6 SCB3 53 60 59 58 57 56 55 64 69 74 79 78 42 CLK0 VCC5 SDA 82 83 SCL VCC9 84 41 40 VCC4 81 NC10 80 CLK2 GND9 DQ29 75 76 DQ30 DQ31 77 DQ28 VCC8 73 DQ25 70 71 DQ26 DQ27 72 DQ24 DQ21 65 66 DQ22 67 DQ23 68 GND8 GND7 NC11 J5 DQ39 SCB2 52 4 SCL {03,07} SDA {03,07} DCLK2 {03} DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 SCKE1 {03,11} DQ20 DQ19 DQ18 DQ17 DQ16 DQ38 54 DQ37 DCLK1 {03} SA11 SBA0 SA9 SA7 SA5 SA3 SA1 SRAS# SCE1# SM5 SM4 SCAS# SCB5 SCB4 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ36 51 DQ35 DQ34 DQ33 DQ32 50 SM3 SM2 SCE0# 4 49 48 47 46 NC8 61 62 NC9 CKE1 63 DQ20 VCC7 DQ19 DQ18 DQ17 DQ16 GND6 CB3 CB2 NC7 NC6 VCC6 NC5 M3 M2 CS2 45 44 43 BA1 39 A8 38 A10 37 36 A2 35 A4 34 GND4 33 A0 32 31 30 CS0 M1 28 M0 SM0 WE 27 NC2 26 VCC3 25 24 23 GND3 22 DQ15 21 CB0 20 SWE# SCB1 SCB0 DQ15 DQ13 DQ12 DQ11 DQ10 DQ9 GND2 DQ8 DQ7 DQ6 DQ5 DQ4 VCC1 DQ3 DQ2 DQ1 NC4 GND5 SDRAM-DIMM168P DQ0 GND1 VCC2 19 DQ14 18 14 DQ11 DQ14 13 DQ9 DQ10 12 10 DQ6 DQ8 8 DQ5 DQ7 7 9 DQ4 6 2 1 DQ0 3 3 DQ45 DQ44 DQ43 DQ42 DQ41 GND2 DQ40 DQ39 DQ38 DQ37 DQ36 VCC1 DQ35 DQ34 DQ33 NC1 CAS M5 RAS A7 A11 CLK1 126 NC4 125 124 VCC4 123 A9 122 BA0 121 120 A3 119 A5 118 GND4 117 A1 116 115 114 CS1 113 112 M4 111 109 NC2 110 VCC3 108 106 CB5 107 GND3 DQ47 105 CB4 104 5 J5 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 148 153 158 163 162 167 VCC8 168 SA2 NC11 164 165 SA0 SA1 166 CLK3 GND9 DQ61 159 160 DQ62 DQ63 161 DQ60 VCC7 157 DQ57 154 155 DQ58 DQ59 156 DQ56 DQ53 149 150 DQ54 151 DQ55 152 GND8 GND7 NC8 145 146 NC9 NC10 147 DQ52 VCC6 DQ51 DQ50 DQ49 DQ48 GND6 CB7 CB6 NC7 NC6 VCC5 NC5 M7 M6 CS3 CKE0 GND5 SDRAM-DIMM168P DQ32 GND1 VCC2 103 DQ46 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 5 DCLK3 {03} DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 SCB7 SCB6 SM7 SM6 SCKE0 {03,11} SCE1# 6 6 7 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 7 Date: Name: Title: 4/14/98 Sheet 8 06 SDRAM 168-PIN DIMM 80960RN 8 of 11 REV B D C B A D C 1 AK19 SPAR S_PAR S_GNT5 S_GNT4 S_GNT3 S_GNT2 S_GNT1 S_GNT0 S_REQ5 S_REQ4 S_REQ3 S_REQ2 S_REQ1 AK12 S_PAR64 AK29 SGNT5# SPAR64 AM28 SGNT4# SAD61 SAD29 SAD30 SAD31 B AK28 SGNT3# SGNT0# AJ27 AJ29 AM26 SREQ5# AM27 AL28 SREQ4# SGNT1# AH28 SREQ3# SGNT2# AK27 SAD60 SAD28 SREQ2# SAD63 S_AD63 AH12 S_REQ0 SAD59 2 SAD27 AL26 SAD58 SAD26 AH27 SAD62 AM11 S_AD62 AK11 S_AD61 AJ11 S_AD60 AH11 S_AD59 AM10 S_AD58 SAD57 AL10 S_AD57 SAD55 SAD56 AH26 S_AD31 AM25 S_AD30 AK25 S_AD29 AJ25 S_AD28 AH25 S_AD27 AM24 S_AD26 AL24 S_AD25 AK24 S_AD24 SAD52 SAD53 AJ23 S_AD21 AH23 S_AD20 AM22 S_AD19 SAD19 SAD54 AM23 SAD24 SAD51 AL22 S_AD56 AK10 AH10 S_AD55 S_AD23 SAD23 SAD25 S_AD18 AK22 SAD18 AM9 S_AD54 SAD49 S_AD17 SAD17 SAD21 S_AD22 AK23 SAD22 SAD48 S_AD16 AH22 SAD16 SREQ1# 3 SAD14 S_AD53 AK9 AJ9 SAD47 S_AD15 AH19 SAD15 SAD20 SAD45 AM18 S_AD14 S_AD52 SAD44 SAD12 SREQ0# SAD11 S_AD51 AH9 SAD50 AM8 S_AD50 AL8 S_AD49 AK8 S_AD48 AH8 S_AD47 SAD46 S_AD46 AM7 U15 i960RN SECONDARY PCI SIGNALS SAD10 AK7 SAD41 SAD9 S_AD45 SAD43 S_AD44 AJ7 AH7 SAD40 SAD8 S_AD13 AL18 SAD13 S_AD43 SAD42 AM6 S_AD42 AL6 S_AD41 AK6 S_AD40 SAD39 S_AD39 AH6 AK18 S_AD12 AH18 S_AD11 AM17 S_AD10 AK17 S_AD9 AJ17 S_AD8 AM15 S_AD7 SAD7 SAD36 SAD37 +3V SAD33 SAD34 2 S_LOCK R43 1 R56 1 R30 1 1/8W 5% 10 2 1/8W 5% 10 2 AM19 AM20 AL20 AH21 AJ21 AK21 AM13 AK13 AJ13 AH13 AM12 AL12 AH24 AM21 AJ19 AH17 +5V AK20 S_RST AK26 AH20 S_PERR S_SERR S_DEVSEL S_STOP S_TRDY S_IRDY S_FRAME S_ACK64 S_REQ64 S_C/BE7 S_C/BE6 S_C/BE5 S_C/BE4 S_C/BE3 S_C/BE2 S_C/BE1 S_C/BE0 1/8W 5% 10 SAD5 SAD38 AM5 SAD35 AJ15 S_AD5 S_AD37 AK5 AH15 SAD4 S_AD38 S_AD6 AK15 SAD6 AJ5 S_AD36 S_AD4 AJ2 S_AD35 S_AD3 AM14 S_AD34 AH4 AH3 SAD2 4 1/2W 5% 100 R52 2 1 SLOCK# SPERR# SRST# SSERR# SDEVSEL# SSTOP# STRDY# SIRDY# SFRAME# SACK64# SREQ64# SC/BE7# SC/BE6# SC/BE5# SC/BE4# SC/BE3# SC/BE2# SC/BE1# SC/BE0# 4 0.01uF CAP0805 1 2 SAD3 S_AD33 SAD32 S_AD32 AH1 C77 C96 C61 0.01uF CAP0805 1 2 SAD1 AL14 S_AD2 AK14 S_AD1 AH14 S_AD0 SAD0 0.01uF CAP0805 1 2 4.7uF CAPT7343 1 2 4.7uF CAPT7343 1 2 3 C76 C92 C57 4.7uF CAPT7343 1 2 2 FAIL# {04} 5 IRQUART# {04} IRQFAN# {11} SINTD# SINTC# SINTB# SINTA# 5 5 4 5 4 NMI D26 B15 C22 VCCPLL3 VCCPLL2 VCCPLL1 E20 VCC5REF E12 FAIL A9 XINT4 D10 XINT5 C10 +5V 6 U15 i960RN JX CORE/I2C/JTAG 6 3 S_INTA/XINT0 7 2 R44 2.7K 8 1 C9 S_INTB/XINT1 E9 S_INTC/XINT2 A10 S_INTD/XINT3 B9 6 3 R3 2.7K 7 2 RNC4R8P 8 1 RNC4R8P 6 C8 A12 A21 B11 7 7 6 5 2 3 4 14 16 15 Sheet 8 07 of 11 4/14/98 REV B 80960RN I_RST# {04,05} Date: +3V 8 Name: SECONDARY PCI/960 CORE Title: 12 HEAD16SH 10 13 8 7 9 6 5 11 4 3 JTAG HEADER J6 2 1 8 1 R36 2.7K RNC4R8P SDA {03,06} SCL {03,06} CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 I_RST A11 LCDINIT TMS TRST C11 TDO E11 TDI TCK C12 SCL A8 SDA 7 R14 A SPCI {05,08,09,10} 1 1.5K 1/10W 5% 1 2 D C B A D C B A 1 C26 1 1 CLKB {02} CAP0805 0.01uF CAP0805 0.01uF C19 2 1 C18 2 1 STCK {09,10} N12V P33V {01,02,04,09} CLKA {02} CAP0805 0.01uF CAP0805 0.01uF C27 2 1 2 STCK {09,10} SPCI {05,07,09,10} B21 SAD29 B29 SAD21 C/BE3 J1 TCK +5V5 TDO TDI A5 GND10 CLK B24 SAD25 AD27 B30 SAD19 B31 B29 SAD21 B28 +3V4 AD19 AD21 GND12 B27 AD23 SAD23 C/BE3 B26 SC/BE3# AD25 B25 +3V3 B23 SAD27 AD29 B22 GND11 B21 +5V7 B20 AD31 B19 B18 REQ B17 B16 B15 GND9 B14 GND7 B13 GND8 A10 A9 A17 A24 A23 A26 AD18 GND5 A31 A30 A29 +3V2 A27 A28 AD20 AD22 IDSEL AD24 A25 GND4 AD26 AD30 A20 A21 +3V1 AD28 A22 GND3 A18 A19 GNT RST A15 A16 +5V4 A14 GND2 A13 GND1 +5V3 INTA A6 A7 INTC +5V2 A8 +5V1 A4 A12 2 A31 TRST A1 A2 +12V TMS A3 AD18 B12 J2 +3V2 AD22 A28 A29 AD20 GND5 A30 A27 A26 A25 A11 PRSNT1 A22 A21 A20 A19 A18 B11 PRSNT2 B10 B9 INTB B8 INTD B7 B6 +5V6 B5 B4 B3 GND6 B2 AD24 +12V P33V {01,02,04,09} SAD14 SC/BE1# SSERR# B40 SAD18 SAD20 SAD22 SAD17 SAD24 SAD26 SAD28 SAD30 SGNT1# SRST# SINTD# SINTB# SAD18 SAD20 SAD22 SAD16 SAD24 SAD26 SAD28 SAD30 SGNT0# 3 STDI {09,10} STMS {09,10} STRST# {09,10} SACK64# SAD1 SAD3 SAD5 SAD7 SAD8 SAD10 SAD12 SAD14 SC/BE1# SSERR# SPERR# SLOCK# SDEVSEL# SIRDY# SC/BE2# SAD17 SACK64# SAD1 SAD3 SAD5 SAD7 SAD8 AD07 AD08 GND9 AD10 AD12 GND8 AD14 C/BE1 +3V7 SERR +3V6 PERR LOCK GND7 DEVSEL +3V5 IRDY GND6 C/BE2 AD17 GND10 AD03 AD05 +5V6 J1 A53 A52 A49 A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 A33 +5V2 A61 A62 +5V3 REQ64 A60 AD06 A54 A55 AD04 A56 GND5 A57 AD02 A58 AD00 +5V1 A59 +3V4 C/BE0 AD09 GND4 AD11 AD13 +3V3 AD15 PAR GND3 SBO SDONE +3V2 STOP GND2 TRDY GND1 A32 +3V5 IRDY PERR AD10 +3V8 GND10 4 B62 B61 B60 B59 +5V6 +5V5 ACK64 +5V4 B58 AD01 B57 AD05 B56 AD03 B55 B54 AD08 B53 AD07 B52 B49 GND9 B48 AD12 AD14 B46 GND8 B47 B45 +3V7 B44 C/BE1 B43 +3V6 B42 SERR B41 B40 GND7 B39 LOCK B38 B37 DEVSEL B36 B35 J2 A36 A41 A40 A43 +3V3 A52 A55 A54 A57 +5V3 +5V2 A62 A61 AD00 A58 A59 +5V1 A60 REQ64 AD02 GND5 A56 AD04 AD06 +3V4 A53 C/BE0 AD13 A46 A47 AD11 A48 GND4 AD09 A49 A45 AD15 A44 PAR GND3 A42 SBO SDONE GND2 A37 A38 STOP +3V2 A39 TRDY GND1 A35 CONNPCI_64 B32 AD17 AD16 A32 B33 A33 C/BE2 +3V1 B34 GND6 FRAME A34 B62 ACK64 B61 +5V5 B60 AD01 B59 +5V4 B58 B57 B56 B55 +3V1 AD16 FRAME CONNPCI_64 B54 +3V8 B53 B52 B49 B48 B47 B46 B45 B44 B43 B42 B41 B39 B38 B37 B36 B35 B34 B33 B32 SPERR# +5V 4 SLOCK# SDEVSEL# SAD10 P33V {01,02,04,09} P33V {01,02,04,09} SIRDY# SC/BE2# SAD12 SRST# SINTC# SINTA# STDI {09,10} STMS {09,10} STRST# {09,10} SAD17 A17 +12V +5V 3 A16 AD26 A23 A24 GND4 AD28 +3V1 AD30 GND3 GNT +5V4 RST IDSEL CONNPCI_64 +3V4 B1 -12V B31 AD21 B30 AD19 SAD29 SAD31 SREQ1# SINTA# SINTC# SAD19 B27 SAD23 +3V3 AD23 B28 GND12 B26 SC/BE3# B25 B24 AD25 B23 AD27 SAD25 GND11 AD29 AD31 +5V7 REQ GND10 CLK SAD27 B22 B20 B19 B18 B17 B16 GND9 A15 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A14 GND2 GND1 +5V3 +5V2 INTC INTA +5V1 TDI TMS +12V TRST A1 B15 GND8 GND7 PRSNT2 PRSNT1 INTD INTB +5V6 +5V5 TDO GND6 TCK -12V CONNPCI_64 N12V B14 B13 B12 B11 B10 SAD31 SREQ0# B8 SINTD# B9 B7 B6 B5 B4 B3 B2 B1 SINTB# +5V 2 +5V SREQ64# SAD0 SAD2 SAD4 SAD6 SC/BE0# SAD9 SAD11 SAD13 SAD15 SPAR SSTOP# STRDY# SFRAME# SAD16 SREQ64# SAD0 SAD2 SAD4 SAD6 SC/BE0# SAD9 SAD11 SAD13 SAD15 SPAR SSTOP# STRDY# SFRAME# SAD16 5 5 P33V {01,02,04,09} P33V {01,02,04,09} SAD33 SAD35 SAD37 SAD39 SAD41 SAD43 SAD45 SAD47 SAD49 SAD51 SAD53 SAD55 SAD57 SAD59 SAD61 SAD63 SC/BE4# SC/BE6# SAD33 SAD35 SAD37 SAD39 SAD41 SAD43 SAD45 SAD47 SAD49 SAD51 SAD53 SAD55 SAD57 SAD59 SAD61 SAD63 SC/BE4# SC/BE6# +5V AD39 GND14 AD41 AD43 GND13 AD45 AD47 +5V5 AD49 AD51 GND12 AD53 AD55 GND11 AD57 AD59 +5V4 AD61 AD63 GND10 C/BE4 C/BE6 GND9 GND15 AD33 AD35 +5V6 C/BE6 AD63 GND10 AD57 AD47 +5V5 AD39 AD35 6 B94 B93 B92 B91 GND16 GND15 B90 AD33 B89 AD37 B88 +5V6 B87 B86 AD41 B85 GND14 B84 GND13 B83 AD43 B82 B81 AD45 B80 B79 AD51 B78 AD49 B77 AD53 B76 GND12 B75 GND11 B74 AD55 B73 B72 +5V4 B71 AD59 B70 B69 AD61 B68 B67 B66 C/BE4 B65 B64 GND9 B63 J1 J2 A86 A85 A84 A83 A82 A81 A80 A79 A78 A77 A76 A75 A74 A73 A72 A71 A70 A69 A68 A67 A66 A65 A64 A63 A63 A94 A68 A73 A72 AD50 A87 A86 A89 GND8 A94 A93 GND7 A90 A91 AD32 A92 AD34 AD36 A88 GND6 AD38 AD42 A83 A84 +5V3 AD40 A85 AD44 A82 GND4 A78 A79 AD48 A80 AD46 GND5 A81 A77 AD54 A74 A75 +5V2 AD52 A76 AD56 GND3 GND2 A69 A70 AD60 AD58 A71 AD62 PAR64 A67 C/BE7 A64 A65 C/BE5 +5V1 A66 GND1 GND8 A93 GND6 A87 A88 AD36 A89 AD34 A90 GND7 A91 AD32 A92 AD38 AD40 +5V3 AD42 AD44 GND5 AD46 AD48 GND4 AD50 AD52 +5V2 AD54 AD56 GND3 AD58 AD60 GND2 AD62 PAR64 +5V1 C/BE5 CONNPCI_64 B94 GND16 B93 B92 B91 B90 B89 B88 GND1 C/BE7 CONNPCI_64 B87 AD37 B86 B85 B84 B83 B82 B81 B80 B79 B78 B77 B76 B75 B74 B73 B72 B71 B70 B69 B68 B67 B66 B65 B64 B63 6 +5V 7 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 SAD32 SAD34 SAD36 SAD38 SAD40 SAD42 SAD44 SAD46 SAD48 SAD50 SAD52 SAD54 SAD56 SAD58 SAD60 SAD62 SPAR64 SC/BE5# SC/BE7# SAD32 SAD34 SAD36 SAD38 SAD40 SAD42 SAD44 SAD46 SAD48 SAD50 SAD52 SAD54 SAD56 SAD58 SAD60 SAD62 SPAR64 SC/BE5# SC/BE7# 7 Date: Name: Title: 4/14/98 Sheet 8 08 of SECONDARY PCI BUS 1/2 80960RN SPCI CONN 2 SPCI CONN 1 8 11 REV B D C B A D C B A 1 C2 1 1 CLKD {02} CAP0805 0.01uF CAP0805 0.01uF C3 2 1 2 STCK {08,10} N12V P33V {01,02,04,08} CLKC {02} CAP0805 0.01uF CAP0805 0.01uF C11 2 1 C10 2 1 STCK {08,10} SPCI {05,07,08,10} GND10 CLK GND12 TDO CLK REQ AD29 +3V3 B30 B31 B29 SAD19 B28 +3V4 AD19 AD21 GND12 C/BE3 B27 AD23 B26 B25 AD27 B24 AD25 B23 B22 GND11 B21 +5V7 B20 AD31 B19 B18 B17 GND10 B16 SAD21 SAD23 SC/BE3# SAD25 SAD27 SAD29 SAD31 GND8 GND7 PRSNT2 PRSNT1 B15 GND9 B14 B13 B12 B11 B10 B9 B8 INTD INTB +5V6 SINTC# B6 B5 +5V5 B4 TCK B3 GND6 B2 B7 SREQ3# J3 2 J4 A22 A21 A20 A19 A18 A17 A16 A29 A28 A4 A14 A13 A16 A23 A30 A29 A28 AD18 A31 GND5 AD20 AD22 GND4 A24 A25 AD24 A26 IDSEL +3V2 A27 AD26 AD30 A20 A21 +3V1 AD28 A22 A19 GNT A17 A18 GND3 +5V4 RST A15 GND2 GND1 A12 +5V3 A10 A11 A9 +5V1 A5 A6 INTA A7 INTC +5V2 A8 TDI TRST A1 A2 +12V TMS A3 GND5 A30 A31 AD18 AD20 AD22 +3V2 A27 A26 AD24 A25 AD26 A23 A24 GND4 AD28 +3V1 AD30 GND3 GNT +5V4 RST IDSEL CONNPCI_64 +3V4 B1 -12V B31 AD21 B30 AD19 B29 B28 C/BE3 B27 AD23 B26 SINTA# SAD19 SAD21 SAD23 SC/BE3# B24 AD25 B25 +3V3 B23 AD27 GND11 AD29 AD31 +5V7 REQ SAD25 B22 B21 B20 B19 B18 B17 GND9 A13 A12 A11 A10 +12V SAD18 SAD20 SAD22 SAD19 SAD24 SAD26 SAD28 SAD30 SGNT3# SRST# SINTB# SINTD# SAD18 SAD20 SAD22 SAD18 SAD24 SAD26 SAD28 SAD30 SGNT2# SRST# P33V {01,02,04,08} 3 STDI {08,10} STMS {08,10} P33V {01,02,04,08} STRST# {08,10} SACK64# SAD1 SAD3 SAD5 SAD7 SAD8 SAD10 SAD12 SAD14 SC/BE1# SSERR# SPERR# SLOCK# SDEVSEL# SIRDY# SC/BE2# SAD17 SACK64# SAD1 SAD3 SAD5 SAD7 SAD8 SAD10 SAD12 SAD14 SC/BE1# SSERR# AD07 AD08 GND9 AD10 AD12 GND8 AD14 C/BE1 +3V7 SERR +3V6 PERR LOCK GND7 DEVSEL +3V5 IRDY GND6 C/BE2 +5V4 +5V6 J3 A53 A52 A49 A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 A57 C/BE1 +3V7 SERR AD12 AD08 GND9 +5V5 ACK64 +5V4 4 B62 +5V6 B61 B60 B59 AD03 B57 GND10 B58 AD01 B56 +3V8 B55 AD05 B54 B53 AD07 B52 B49 B48 AD10 B47 AD14 B46 GND8 B45 B44 B43 B42 PERR B41 +3V6 B40 J4 A40 A45 A44 A47 +3V4 A53 A54 A61 A60 A59 +5V3 A62 +5V2 REQ64 +5V1 AD04 A55 A56 GND5 A57 AD02 AD00 A58 AD06 C/BE0 A52 GND4 A48 A49 AD09 AD11 AD13 A46 +3V3 AD15 PAR A43 SBO A41 A42 GND3 SDONE 5 SC/BE6# SAD33 SAD35 SAD37 SAD39 SAD41 SAD43 SAD45 SAD47 SAD49 SAD51 SAD53 SAD55 SAD57 SAD59 SAD61 SAD63 SREQ64# SAD0 SAD2 SAD4 SAD6 SC/BE0# SAD9 SAD11 SAD13 SAD15 SPAR SSTOP# STRDY# SFRAME# SAD16 SREQ64# SAD33 SAD35 SAD37 SAD39 SAD41 SAD43 SAD45 SAD47 SAD49 SAD51 SAD53 SAD55 SAD57 SAD59 SAD61 SAD63 SC/BE4# AD39 GND14 AD41 AD43 GND13 AD45 AD47 +5V5 AD49 AD51 GND12 AD53 AD55 GND11 AD57 AD59 +5V4 AD61 AD63 GND10 C/BE4 C/BE6 GND9 AD33 B91 GND15 B90 B88 +5V6 B89 AD35 GND10 +5V4 AD61 GND12 AD53 AD55 +5V5 AD45 AD41 +5V6 GND15 6 B94 GND16 B93 B92 B91 AD35 B90 AD33 B89 B88 AD39 B87 AD37 B86 B85 GND14 B84 GND13 B83 AD43 B82 B81 B80 AD47 B79 AD51 B78 AD49 B77 B76 B75 B74 AD57 B73 GND11 B72 B71 AD59 B70 B69 B68 AD63 B67 C/BE6 B66 C/BE4 B65 B64 GND9 B63 J3 J4 +5V1 A86 A85 A84 A83 A82 A81 A80 A79 A78 A77 A76 A75 A74 A73 A72 A71 A70 A69 A68 A67 A66 A65 A64 A63 A90 A63 A94 A93 A67 A79 A82 A86 GND8 AD32 A94 A93 A92 A91 GND6 A87 A88 AD36 A89 AD34 GND7 A90 AD38 AD42 A83 A84 +5V3 AD40 A85 AD44 AD46 A80 A81 GND5 AD48 AD56 A73 A74 AD54 A75 +5V2 A76 AD52 A77 AD50 GND4 A78 GND3 A72 AD62 A68 A69 GND2 A70 AD60 AD58 A71 PAR64 C/BE7 A64 A65 C/BE5 +5V1 A66 GND1 GND8 A92 AD32 A91 GND7 GND6 A87 A88 AD36 AD34 A89 AD38 AD40 +5V3 AD42 AD44 GND5 AD46 AD48 GND4 AD50 AD52 +5V2 AD54 AD56 GND3 AD58 AD60 GND2 AD62 PAR64 CONNPCI_64 B94 GND16 GND1 C/BE5 C/BE7 CONNPCI_64 B87 AD37 B86 B85 B84 B83 B82 B81 B80 B79 B78 B77 B76 B75 B74 B73 B72 B71 B70 B69 B68 B67 B66 B65 B64 B93 P33V {01,02,04,08} P33V {01,02,04,08} SC/BE4# SC/BE6# B63 A60 SAD0 SAD2 SAD4 SAD6 SC/BE0# SAD9 SAD11 SAD13 SAD15 SPAR SSTOP# STRDY# SFRAME# SAD16 +5V 6 B92 +5V 5 A59 +5V2 A61 A62 +5V3 REQ64 +5V1 AD00 A58 AD02 AD06 A54 A55 AD04 GND5 A56 +3V4 C/BE0 AD09 GND4 AD11 AD13 +3V3 AD15 PAR GND3 SBO SDONE +3V2 STOP GND2 TRDY GND1 A33 A32 CONNPCI_64 B32 AD17 AD16 A32 B33 A33 C/BE2 +3V1 B34 GND6 FRAME A34 B35 A35 IRDY GND1 B36 +3V5 TRDY A36 B37 A37 DEVSEL GND2 B38 A38 STOP GND7 B39 LOCK +3V2 A39 B62 ACK64 B61 +5V5 B60 B59 B57 GND10 B58 AD01 AD05 B56 AD03 B55 +3V1 AD16 FRAME CONNPCI_64 AD17 B54 +3V8 B53 B52 B49 B48 B47 B46 B45 B44 B43 B42 B41 B40 B38 B37 B36 SPERR# SDEVSEL# A9 A15 B16 P33V {01,02,04,08} B35 B34 B33 SC/BE2# SIRDY# B32 SAD17 B39 SINTA# SINTC# STDI {08,10} STMS {08,10} STRST# {08,10} +5V 4 SLOCK# +12V +5V 3 A8 A7 A6 A5 A4 A3 B15 GND2 GND1 +5V3 +5V2 INTC INTA +5V1 TDI TMS A2 A1 A14 GND8 GND7 PRSNT2 PRSNT1 INTD INTB +5V6 +5V5 TDO +12V TRST B14 B13 B12 B11 B10 CONNPCI_64 GND6 TCK -12V N12V SAD27 SAD29 SAD31 SREQ2# B8 SINTB# B9 B7 B6 B5 B4 B3 B2 B1 SINTD# +5V 2 +5V 7 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 SAD32 SAD34 SAD36 SAD38 SAD40 SAD42 SAD44 SAD46 SAD48 SAD50 SAD52 SAD54 SAD56 SAD58 SAD60 SAD62 SPAR64 SC/BE5# SC/BE7# SAD32 SAD34 SAD36 SAD38 SAD40 SAD42 SAD44 SAD46 SAD48 SAD50 SAD52 SAD54 SAD56 SAD58 SAD60 SAD62 SPAR64 SC/BE5# SC/BE7# 7 8 09 of 11 Sheet REV B 4/14/98 Date: 80960RN Name: SECONDARY PCI BUS 3/4 Title: SPCI CONN 4 SPCI CONN 3 8 D C B A D C B A 1 SPCI {05,07,08,09} 1 7 2 3 4 SREQ5# SACK64# SREQ64# 2 8 R31 2.7K RNC4R8P 5 6 5 6 1 7 8 SREQ4# R33 2.7K RNC4R8P 4 1 SREQ0# R38 2.7K 5 SREQ3# 4 SLOCK# 6 3 3 SPERR# 7 8 SREQ2# 2 SSERR# 2 1 SSTOP# RNC4R8P R45 2.7K 5 6 7 SREQ1# 4 SDEVSEL# 2 STRDY# 3 1 SFRAME# SIRDY# 5 4 STCK 8 6 3 STRST# RNC4R8P 7 2 R1 2.7K 8 1 STDI RNC4R8P STMS 2 +5V +5V 3 3 SAD51 SAD50 SAD49 SAD48 SAD47 SAD46 SAD45 SAD44 SAD43 SAD42 SAD41 SAD40 SAD39 SAD38 SAD37 SAD36 SAD35 SAD34 SAD33 SAD32 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 R8 2.7K RNC4R8P R9 2.7K RNC4R8P R10 2.7K RNC4R8P R11 2.7K RNC4R8P R12 2.7K RNC4R8P 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 4 +5V 4 SPAR64 SC/BE7# SC/BE6# SC/BE5# SC/BE4# SAD63 SAD62 SAD61 SAD60 SAD59 SAD58 SAD57 SAD56 SAD55 SAD54 SAD53 SAD52 5 5 R2 1 R4 2.7K RNC4R8P R5 2.7K RNC4R8P R6 2.7K RNC4R8P R7 2.7K RNC4R8P 1/10W 5% 2.7K 2 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 +5V 6 6 7 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 7 Date: Name: Title: 4/14/98 Sheet SPCI PULL-UPS 80960RN 8 10 8 of 11 REV B D C B A D C B 1 C54 1 2 CAPT7343 10uF R60 PWR J13 FAN 1 FAN CONN 10 1/10W 5% 1 2 2 GND 3 R28 C74 1 2 1 1 1/10W 5% 1/10W 5% 1 2 1 2 CAPT3216 1uF 68K 1/10W 5% 1 2 +5V R27 R26 R34 2 13 6 11 7 16 1 100K 1/10W 5% 1 2 22K 1/10W 5% 1 2 5 BATTU14 FASTCHG GND PGM3 PGM2 PGM1 PGM0 TLO CC TEMP REF DRV R20 BATT+ MAX712 VLIMIT V+ THI R24 1K 1/10W 5% 1 2 0.01uF CAP0805 1 2 47K 1/10W 5% 1 2 0.01uF CAP0805 1 2 R25 C68 R53 C58 0.01uF CAP0805 1 2 4.7K 1/10W 5% 1 2 C55 4.7K 1/10W 5% 1 2 R49 0.047uF CAP0805 1 2 3 12 8 10 9 4 3 2 Q4 2 2N6109 1 14 + CMR1-02 2 1 2 1 + 2 1 150 1/10W 5% 1 2 R48 C82 CR8 3 BATT_HLDR BT1 BT2 BATT_HLDR BATT_HLDR BT3 BT4 BATT_HLDR + 2 1 + 2 1 15 10uF CAPT7343 1 2 C52 + 6 7 - + 4 - 5 LM339 U10 LM339 U10 1 2 4 NOTE: VCC FOR LM339 IS +5V BATT_HLDR BT8 BT7 BATT_HLDR BATT_HLDR BT6 BT5 BATT_HLDR C65 2 1 2 1 0.47uF CAP1206 1 2 8 2 4 3 U8 MAX1651 IRQFAN# {07} GND FB REF SHDN OUT EXT CS V+ 1 7 6 5 BATTERY 5 5 4 0.05 1W 1% 1 2 CR7 MBRS340T3 8 SI9430 Q1 1 C53 L1 47uH +12V 4 R47 R21 1 2 3 5 6 7 2 7 6 5 4 3 2 6 C56 1 2 6 CAPT7343H 100uF C64 1 2 3 C51 2.4K 1/10W 5% 1 2 0.1uF CAP0805 1 2 1 2 1 2 1 10K 1/10W 5% 1 2 100K 1/10W 5% 1 2 22uF CAPT7343 1 2 R35 R32 C47 2 RST# {02} CAPT7343H 330uF A 1 33uF CAPT7343 1 2 C63 0.1uF CAP0805 1 2 U19 VCC F7 F6 F5 F4 F3 F2 F1 F0 20 19 18 17 16 15 14 13 12 8 - 9 + 10 - 11 + LM339 U10 LM339 U10 14 13 7 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 +5V SPARES PALLV16V8Z-20JI I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 RAM3V {01,04,06} 11 9 8 7 6 5 4 3 2 1 PART # 101-1950-01 7 Date: Name: Title: 4/14/98 Sheet 8 11 BATTERY/MONITOR 80960RN RAM3V {01,04,06} SCKE1 {03,06} SCKE0 {03,06} 8 of 11 REV B D C B A Schematics Table B-2. IQ80960RM Schematics List Page Schematic Title B-14 Decoupling and 3.3V Power B-15 Primary PCI Interface B-16 Memory Controller B-17 Flash ROM, UART, & LEDs B-18 Logic Analyzer I/F B-19 SDRAM 168-Pin DIMM B-20 Secondary PCI/960 Core B-21 Secondary PCI Bus 1/2 B-22 Secondary PCI Bus 3/4 B-23 Battery/Monitor IQ80960RM/RN Evaluation Board Manual B-13 D C B A 1 +5V CAP0805 0.1uF C103 2 1 CAP0805 0.1uF C99 2 1 CAP0805 0.1uF C59 2 1 CAP0805 0.1uF C69 2 1 CAP0805 0.1uF CAP0805 0.1uF C66 2 1 CAP0805 0.1uF C62 2 1 CAP0805 0.1uF C49 2 1 CAP0805 0.1uF C73 2 1 CAP0805 0.1uF C48 2 1 2 CAP0805 0.1uF C116 2 1 CAP0805 0.1uF C113 2 1 CAP0805 0.1uF C111 2 1 CAP0805 0.1uF C108 2 1 CAP0805 0.1uF C114 2 1 CAP0805 0.1uF C115 2 1 CAP0805 0.1uF CAP0805 0.1uF C87 2 1 CAP0805 0.1uF C71 2 1 CAP0805 0.1uF C44 2 1 CAP0805 0.1uF CAP0805 0.1uF C81 2 1 CAP0805 0.1uF C42 2 1 CAP0805 0.1uF C112 2 1 CAP0805 0.1uF C109 2 1 CAP0805 0.1uF C105 2 1 CAP0805 0.1uF C50 2 1 CAP0805 0.1uF C72 2 1 CAP0805 0.1uF C41 2 1 C107 1 CAP0805 0.1uF C106 2 1 2 CAP0805 0.1uF C117 2 1 CAP0805 0.1uF C46 2 1 CAP0805 0.1uF C67 2 1 +3V CAP0805 0.1uF C43 2 1 CAP0805 0.1uF C45 2 1 C80 1 CAP0805 0.1uF C79 2 1 2 CAP0805 0.1uF C70 2 1 C93 1 CAPT7343 47uF C85 2 1 2 +3V +5V C90 1 3 CAP0805 0.1uF CAP0805 0.1uF C1 2 1 CAP0805 0.1uF C7 2 1 CAP0805 0.1uF C8 2 1 CAP0805 0.1uF C9 2 1 CAP0805 0.1uF C15 2 1 CAP0805 0.1uF C16 2 1 CAP0805 0.1uF C17 2 1 CAP0805 0.1uF C23 2 1 CAP0805 0.1uF C24 2 1 CAP0805 0.1uF C25 2 1 CAP0805 0.1uF C31 2 1 CAPT7343 47uF C32 2 1 2 P33V {02,04,08,09} SPCI DECOUPLING C91 1 4 CAP0805 0.1uF CAP0805 0.1uF C6 2 1 CAP0805 0.1uF C5 2 1 CAP0805 0.1uF C4 2 1 CAP0805 0.1uF C14 2 1 CAP0805 0.1uF C13 2 1 CAP0805 0.1uF C12 2 1 CAP0805 0.1uF C22 2 1 CAP0805 0.1uF C21 2 1 CAP0805 0.1uF C20 2 1 CAP0805 0.1uF C30 2 1 CAP0805 0.1uF C29 2 1 CAPT7343 47uF C28 2 1 2 C88 1 2 RAM3V {04,06,10} C33 1 5 CAP0805 0.1uF CAP0805 0.1uF C40 2 1 CAP0805 0.1uF C39 2 1 CAP0805 0.1uF C38 2 1 CAP0805 0.1uF C37 2 1 CAP0805 0.1uF C36 2 1 CAP0805 0.1uF C35 2 1 CAP0805 0.1uF C34 2 1 2 SDRAM DECOUPLING CAP0805 0.01uF C83 1 2 CAPT7343 4.7uF 5 R54 CAP1206 0.22uF C84 1 2 10 1/8W 5% 1 2 +5V 11 7 6 5 4 9 8 2 3 15 14 10 GND5 GND4 GND3 GND2 GND1 SYNC REF SS ON/OFF# VCC3 VCC2 VCC1 U17 6 DL LX DH BST FB CS PGND MAX767CAP 6 20 1 13 16 18 19 17 1 1 CAPT7343 220uF C60 1 2 3 2 3 2 2 CR9 3 CMPSH3 RFD16N05L Q2 RFD16N05L Q3 +5V 7 1 2 7 +3V 8 01 of 10 Sheet REV B 4/14/98 Date: 80960RM TP1 8 Name: DECOUPLING & 3.3V POWER Title: 1W 1% 0.012 NOTE: PINS 3-7 ARE VIAS 7 6 5 4 3 R46 1 2 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 MBRS340T3 C86 CR6 0.1uF CAP0805 1 2 2 4 L2 3.3uH COIL-SMT2 1 3 C75 1 2 1 IC DECOUPLING 2 CAPT7343 220uF C78 1 2 1 CAPT7343 220uF D C B A D C PTRDY# E6 P_LOCK P_GNT B7 P_RST A7 M4 1 U18 16 18 Q0 Q1 7 8 Q4 15 11 Q3 Q2 10 Q5 Q6 CY7B9910-7 CLK 1 REF FB 13 3 FS 23 TEST Q7 19 RST# PGNT# PLOCK# P_REQ P_IDSEL N3 P_PAR H3 PREQ# PPAR PIDSEL PSTOP# P_DEVSEL P_FRAME L3 P_IRDY L2 P_TRDY M5 P_STOP L1 PDEVSEL# PIRDY# L5 PFRAME# D6 PAD31 P_AD31 C6 PAD30 P_AD30 A6 PAD29 P_AD28 E5 P_AD27 G3 PAD28 P_AD26 G2 PAD27 B P_C/BE3 P_C/BE2 U15 i960RM PRIMARY PCI SIGNALS 2 6 3 5 7 2 4 8 1 R40 22 R55 22 RNC4R8P 6 3 5 7 2 4 8 1 RNC4R8P P_AD25 H5 P_AD24 PAD24 H4 P_AD23 H1 PAD23 K1 P_AD22 J5 PC/BE3# P_AD21 J3 PAD22 PC/BE2# P_AD20 J2 PAD21 PAD26 P_AD29 0.1uF CAP0805 1 2 PAD20 P_C/BE1 PAD17 N5 CLKD {09} CLKC {09} CLKB {08} CLKA {08} K4 P_AD17 K3 P_AD16 N2 P_AD15 N1 P_AD14 PAD16 P_AD19 J1 PAD19 G1 C97 0.1uF CAP0805 1 2 P5 PAD15 PC/BE1# PAD12 P_C/BE0 LOGIC_CLK {05} CLK_960 PAD11 R2 PAD10 PC/BE0# PAD9 PPCI PAD8 P_AD18 K5 PAD18 PAD25 C98 0.1uF CAP0805 1 2 PAD14 C100 0.1uF CAP0805 1 2 3 P4 P_AD12 P3 P_AD11 P1 P_AD10 R5 P_AD9 R3 P_AD8 R1 P_AD7 PAD7 A PAD5 P_AD13 PAD13 C101 0.1uF CAP0805 1 2 PAD4 P_CLK P_SERR P_PERR P_INTD P_INTC P_INTB P_INTA C104 PINTB# PINTC# PINTD# PPERR# PSERR# D8 E7 C7 M3 M1 C20 PINTA# E8 P33V J14 5 9 8 7 6 5 4 3 2 1 21 RST# +3V1 IRDY# GND1 47 48 PAD12 PAD10 54 4 PAD1 PAD3 AD5 +3V4 AD7 AD8 +5V1 62 +5V3 ACK64# 61 +5V2 60 59 GND5 58 AD1 57 56 AD3 55 53 52 P33V PAD5 AD12 AD10 49 GND4 PAD7 PAD8 45 AD14 46 GND3 44 C/BE1# +3V3 PAD14 43 42 SERR# +3V2 PC/BE1# P33V 41 40 PERR# 39 LOCK# GND2 PPERR# 38 PLOCK# PSERR# J14 CONNPCI_B 37 DEVSEL# 36 P33V PDEVSEL# 35 PIRDY# C/BE2# 33 34 32 AD17 PAD17 PC/BE2# AD19 31 +3V2 30 PAD19 P33V 29 AD21 GND7 AD23 PAD21 28 27 PAD0 PAD2 PAD4 PAD6 P33V PC/BE0# PAD9 PAD11 PAD13 P33V PAD15 PPAR P33V PSTOP# PTRDY# PFRAME# P33V PAD16 PAD18 +3V2 GND1 FRAME# +3V1 STOP# SBO# SDONE PAR AD11 AD6 +3V4 C/BE0# 62 61 60 59 +5V3 +5V2 REQ64# +5V1 AD2 58 AD0 57 AD4 56 GND5 55 54 53 52 GND4 49 AD9 48 47 +3V3 46 AD13 45 44 AD15 43 42 GND3 41 40 39 +3V2 38 TRDY# 37 GND2 36 35 34 33 32 AD16 GND5 31 AD18 30 AD22 29 AD20 28 PAD20 27 P33V PAD22 IDSEL AD24 PAD23 26 25 C/BE3# PIDSEL 26 +3V1 PC/BE3# AD26 AD28 +3V1 AD30 GND3 GNT# +5V4 24 GND4 23 22 21 20 19 18 17 16 GND2 GND1 25 PAD24 PAD26 PAD28 P33V PAD30 PGNT# 15 14 13 +5V3 24 AD25 PAD25 AD27 GND6 AD29 AD31 +5V3 REQ# GND5 CLK GND4 GND3 12 +5V2 INTC# INTA# +5V1 TDI TMS +12V TRST# P33V 23 PAD27 22 20 PAD29 19 18 17 16 15 14 13 GND2 11 PRST# PINTC# PINTA# TD +5V 11 12 PRSNT2# CONNPCI_B 0.1uF CAP0805 1 2 10 PRSNT1# INTD# INTB# +5V2 +5V1 TDO GND1 TCK -12V N12V 5 C95 10 PAD31 PREQ# 8 9 7 6 5 4 3 2 1 PINTB# TD +5V PINTD# 4 6 J15 CONNPCI_A J15 CONNPCI_A 6 +12V C89 3 PAD3 2 PAD2 P_AD6 T5 PAD6 C102 0.1uF CAP0805 1 2 PAD1 T4 P_AD5 T3 P_AD4 T1 P_AD3 U3 P_AD2 U2 P_AD1 U1 P_AD0 PAD0 Z3 2 R58 2 1 7 U16 PPCI 3 9 5 4 4/14/98 Sheet 8 02 of 10 11 8 6 REV B 74ALS08 U16 74ALS08 U16 74ALS08 U16 SPARES RST# {10} 8 Date: 80960RM 13 12 10 R39 Name: PRIMARY PCI INTERFACE Title: 74ALS08 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 PRST# +5V JUMP1X2 1 7 10K 1/10W 5% 1 2 1 10K 1/10W 5% 1 2 47uF CAPT7343 1 2 0.1uF CAP0805 1 2 C94 D C B A D C B 1 SCKE1 {06,10} SCKE0 {06,10} DCLKIN C110 R51 1 1/10W 5% 22 2 1/10W 5% 22 R50 2 1 18pF CAP0805 1 2 N29 N30 SA1 SA0 SBA0 SA0 SA1 SA2 SA3 SA4 SCE1 SCE0 SDQM7 SCKE1 U30 M32 SDQM1 L29 SM2 SM1 SM0 SDQM0 SDQM2 U28 SDQM3 SM3 SDQM4 L28 SDQM6 M31 SDQM5 U29 V32 U32 SM4 SM5 SM6 SM7 M28 SCE1# SWE T28 SCKE0 L32 M30 SWE# SCE0# SCAS SBA1 L30 N28 SA2 N32 SRAS P32 SA3 SA5 SA6 SCAS# P31 SA4 SRAS# P30 SA5 T30 P28 SA6 SA7 SA8 SA9 SA10 SA11 DCLKIN T31 R32 SA7 DQ61 DCLKOUT SBA1 R30 SA8 DQ63 DQ63 AH32 SBA0 R29 SA9 T32 R28 SA10 SA11 E21 A22 DQ62 AF28 DQ62 AF31 DQ61 DQ60 AE28 DQ60 DQ59 AE30 DQ59 DQ58 AD28 DQ58 DQ57 AD31 6 5 3 4 2 7 R13 1.5K 8 2 RNC4R8P 1 DQ54 S1 6 3 5 7 2 4 8 1 SWDIP4 AC32 DQ23 DQ57 DQ55 DQ56 DQ56 AC28 AC30 DQ31 AG32 DQ31 DQ30 AF30 DQ30 DQ29 AF32 DQ29 DQ28 AE29 DQ28 DQ27 AE32 DQ27 DQ26 AD30 DQ26 DQ25 AD32 DQ25 DQ24 AC29 DQ24 DQ53 DQ49 DQ50 U15 i960RM MEMORY CONTROLLER DQ55 DQ23 DQ48 3 RAD2/32BITMEM_EN# RAD3/RETRY RAD6/RST_MODE# Y30 DQ18 Y32 DQ52 DQ54 DQ22 AB30 DQ22 DQ47 DQ18 DQ17 DQ17 DQ16 W29 DQ16 DQ15 J29 DQ15 1/10W 5% 24 DQ14 AB28 DQ52 DQ45 J32 DQ14 DQ53 AB31 AA28 DQ51 DQ51 AA30 DQ21 AB32 DQ21 DQ20 AA29 DQ20 DQ19 AA32 DQ19 Y28 DQ50 Y31 DQ49 W28 DQ48 J28 DQ47 DQ46 DQ46 J30 DQ44 DQ12 DCLKOUT DQ11 A DQ10 H28 DQ41 DQ9 DQ45 DQ43 DQ44 H31 G32 DQ40 DQ8 DQ13 H30 DQ13 DQ43 DQ42 A28 DQ42 C27 DQ41 A27 DQ40 R37 2 1 RAD15 RAD14 RAD14 D18 C18 RAD13 A18 RAD12 E17 RAD11 E15 RAD10 RAD9 C15 RAD7 RAD5 4 RAD0 RAD0 A13 RAD1 RAD1 RAD2/32BITMEM_EN# RAD3/RETRY RAD4/STEST RAD5 B13 RAD4/STEST A14 E13 RAD3/RETRY RAD2/32BITMEM_EN# C13 RAD6/RST_MODE# RAD7 E14 D14 C14 RAD8 A15 RAD8 RAD9 RAD10 RAD11 RAD12 RAD13 RAD16 RAD15 RAD16 E18 B19 A19 RALE E19 ONCE# RCE0# RCE1# C19 ROE# RWE# SCB0 K32 A20 SCB1 K30 D20 SCB3 SCB4 K31 SCB2 SCB5 K28 V31 SCB6 V30 W32 SCB7 W30 C21 ONCE RALE RCE1 RCE0 RWE ROE SCB0 SCB1 SCB2 SCB3 SCB4 SCB5 SCB6 SCB7 RAD6/RST_MODE# DQ5 DQ38 E25 DQ37 A25 DQ5 DQ38 DQ36 DQ4 D24 DQ4 DQ39 DQ39 C26 H32 DQ12 C28 DQ11 E27 DQ10 B27 DQ9 E26 DQ8 A26 DQ7 DQ7 DQ37 B25 DQ35 DQ3 A24 DQ3 SDRAM {05,06} DQ2 DQ6 E24 DQ36 C24 DQ35 DQ34 DQ34 E23 B23 DQ32 DQ32 E22 DQ33 DQ33 DQ1 C23 DQ2 A23 DQ1 D22 DQ0 DQ0 C25 DQ6 4 Z2 2 JUMP1X2 1 RAD {04,05} RAD0 TP2 RAD4/STEST 1 3 1.5K 1/10W 5% 1 2 2 5 R42 5 Z1 2 JUMP1X2 1 ROMA {04} DCLKOUT RWE# RCE1# SCL {06,07} U6 SCLK SDA OE CLKIN 10 6 U9 13 12 13 5 4 2 1 U13 28 21 45 44 41 40 36 35 32 31 18 17 14 13 9 8 5 4 12 74ALS32 U13 74ALS04 U6 74ALS32 U13 74ALS32 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 MPC9140/CDC318 6 74ALS04 25 24 38 11 R57 11 +3V ROMA18 1/10W 5% 36 R29 2 1 SDA {06,07} 1.5K 1/10W 5% 1 2 1 R41 2.7K 1/10W 5% 1 2 11 6 3 9 10 R22 30 RNC4R8P R23 30 RNC4R8P 8 4 3 2 1 4 3 2 1 7 Sheet 8 03 MEMORY CONTROLLER 4/14/98 Date: 80960RM DCLK3 {06} DCLK2 {06} DCLK1 {06} DCLK0 {06} DRAMCLK_LA {05} DCLKIN 8 Name: Title: SEL_LED# {04} CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 IOR# {04} 74ALS32 U13 IOW# {04} SELUART# {04} 5 6 7 8 5 6 7 8 7 of 10 REV B D C B A D C B RAD {03,05} 1 3 4 5 6 7 8 9 11 RAD15 RAD14 RAD13 RAD12 RAD11 RAD10 RAD9 RALE RALE RAD3/RETRY RAD4/STEST RAD5 1D OC LE 8D 7D 6D 5D 4D 3D 2D 1D 4D LE 8D U1 18 19 12 13 14 15 16 17 18 19 14 Z4 8Q 12 7Q 13 6Q 3Q 17 16 4Q 5Q 15 2Q 1Q 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 2 2 JUMP1X2 1 U2 74ABT573 RCE0# 1 OC 11 9 6D 8 7D 7 6 5D 5 2D 4 3D 3 RAD6/RST_MODE# 2 1 2 +5V ROMA20 40 A20 VPP 11 5 4 3 RAD12 RAD11 RAD10 14 A10 15 ROMA10 ROMA9 17 18 19 A5 20 RAD7 RAD6/RST_MODE# RAD5 RAD4/STEST ROE# RWE# RAD0 A0 9 CE 37 OE 38 WE 24 A2 23 A1 22 RAD2/32BITMEM_EN# RAD1 21 A3 RAD3/RETRY A4 A6 A7 16 A8 A9 A11 A12 A13 8 13 ROMA11 7 ROMA13 A14 ROMA12 6 A16 5 A15 4 ROMA14 ROMA15 ROMA16 A19 A18 3 A17 2 ROMA18 ROMA17 1 ROMA19 RAD8 ROMA17 ROMA18 ROMA19 ROMA20 3 U11 12 36 RAD12 RAD9 RAD10 RAD11 RAD13 28 RAD14 RAD15 RAD16 32 D2 27 26 D1 D0 25 D3 D4 D7 35 34 D6 D5 33 RP RY/BY 4 3 1 4 74ALS04 U6 I_RST# {05,07} I_RST# {05,07} FAIL# {07} IOR# {03} IOW# {03} U6 2 5 SEL_LED# {03} 74ALS04 RST IOW IOW IOR IOR CS0 CS1 CS2 A0 A1 U12 6 74ALS04 U6 8D 7D R17 1 U3 R18 1 1/10W 5% 330 R19 2 1 1/10W 5% 1.6K 2 1/10W 5% 470 2 CLR 5 1 RXCLK RI CD 33 18 19 27 32 17 10 43 42 41 40 11 38 35 37 36 13 2 12 LED0 CR5 LED GREEN 1 2 CR4 +5V LED4SM P33V {01,02,08,09} +5V 6 1489A 3 1489A RAM3V {01,06,10} +5V LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED GREEN LP 1 2 CR3 LED RED 1 2 6Q 15 16 7Q 19 8Q 5Q 2Q 5 6 3Q 4Q 9 1Q DDIS 26 INT XTAL1 XTAL2 TXRDY RXRDY BAUDOUT 74ABT273 11 CLK RAD16 18 RAD15 17 RAD14 14 6D 5D 3D 8 4D 7 1D 4 2D 3 RAD13 13 RAD12 RAD11 RAD10 RAD9 28 AS 39 21 20 25 24 14 ROMA9 16 15 +5V 31 30 DSR RXD OP1 OP2 DTR RTS TXD RAD2/32BITMEM_EN# 29 A2 ROMA10 ROMA11 ROMA12 16C550 CTS D1 D2 D3 D4 D5 D6 D7 D0 RAD0 +12V 6 RAD13 ROMA13 SELUART# {03} 7 RAD14 2 8 RAD15 RAD9 9 RAD16 RAD1 E28F016S5 U4 O 5 ROMA14 ROMA15 ROMA16 E/D OSC1.8432MHz 6 6 U7 9 U7 13 12 10 9 5 4 2 8 IN4B IN4A IN3B IN3A IN2B IN1B IN1A 74ALS04 U6 4 1 +5V U5 1488 OUTD OUTC OUTB OUTA LED4SM 5 2 5 2 RAD16 74ABT573 ROMA {03} 1 4 RNC4R8P CR2 LED4SM 3 CR2 2 11 8 6 3 7 2 7 A 1 10K 1/10W 5% 1 2 8 7 LED7 1 8 6 5 LED6 7 CR2 LED4SM 4 5 CR2 LED4SM 1 8 11 1489A 8 1489A 7 U7 13 10 Sheet 8 04 of 10 4/14/98 REV B 80960RM Date: 8 Name: FLASH ROM, UART, & LEDS Title: U7 J7 CONNJ6-6P IRQUART# {07} 6 5 4 3 2 1 SPARES CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 CR1 LED4SM 3 6 CR1 LED4SM 4 5 CR1 LED4SM 3 6 4 3 LED5 8 7 R16 470 2 1 LED4 RNC4R8P LED3 6 5 LED2 2 1 LED0 4 3 LED1 R15 470 CR1 9 12 R59 D C B A D C B A 1 SDRAM {03,06} 1 SM1 SM0 SCB7 SCB6 SCB5 SCB4 SCB3 SCB2 SCB1 SCB0 9 10 11 12 13 14 15 16 17 18 19 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 2 SM2 8 DQ11 DQ55 DQ54 27 26 SA7 SA6 SA5 SA4 GND2 40 41 27 26 25 24 23 22 21 20 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 4 DQ56 28 SA8 28 DQ40 GND4 42 43 GND5 GND3 DQ57 29 SA9 29 DQ41 SA0 SA1 SA2 20 21 22 23 24 25 41 J11 GND4 42 43 GND5 GND3 GND2 40 DQ58 30 SA10 30 DQ42 39 DQ59 31 SA11 31 DQ43 GND1 DQ60 32 32 SA3 DQ61 33 SRAS# 33 DQ44 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ62 DQ45 34 SCAS# DQ63 34 CLK1 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ46 35 MICTOR CLK0 SWE# 36 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 4 35 3 3 DQ47 J9 SM3 7 DQ12 39 SM4 6 CLK1 SM6 SM5 5 DQ14 DQ13 36 SM7 GND1 MICTOR CLK0 4 DRAMCLK_LA {03} DQ15 3 2 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 39 41 GND4 42 43 GND5 GND3 GND2 40 J12 CLK1 GND1 MICTOR CLK0 5 5 18 19 SBA1 SBA0 SPCI {07,08,09} 21 20 SREQ1# SREQ0# 22 SREQ2# 24 SREQ4# 23 25 SREQ5# SREQ3# 26 28 SGNT2# SGNT0# 29 SGNT3# 27 30 SGNT4# SGNT1# 31 SGNT5# 32 33 34 35 6 J10 GND1 39 40 GND2 41 GND3 42 GND4 43 GND5 MICTOR CLK0 36 CLK1 17 SCE1# LOGIC_CLK {02} 16 SCE0# 15 14 13 12 11 10 9 8 7 6 5 4 3 6 I_RST# {04,07} RAD {03,04} 7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 RAD16 RALE RCE0# RCE1# ROE# RWE# RALE RAD0 RAD1 39 GND5 8 05 of 10 Sheet REV B 4/14/98 Date: 8 Name: LOGIC ANALYZER I/F 43 GND2 40 41 GND3 GND4 42 80960RM J8 CLK1 GND1 MICTOR CLK0 Title: 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 19 18 RAD2/32BITMEM_EN# 17 RAD3/RETRY RAD4/STEST RAD5 RAD6/RST_MODE# RAD7 RAD8 RAD9 RAD10 RAD11 RAD12 RAD13 RAD14 RAD15 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 7 D C B A D C B A 1 1 2 2 SDRAM {03,05} RAM3V {01,04,10} 3 4 5 DQ1 DQ2 DQ3 11 15 16 17 DQ12 DQ13 CB1 NC1 DCLK0 {03} SBA1 SA10 SA8 SA6 SA4 SA2 SA0 SCE0# 29 SM1 NC3 A6 SCB3 53 60 59 58 57 56 55 64 69 74 79 78 42 CLK0 VCC5 SDA 82 83 SCL VCC9 84 41 40 VCC4 81 NC10 80 CLK2 GND9 DQ29 75 76 DQ30 DQ31 77 DQ28 VCC8 73 DQ25 70 71 DQ26 DQ27 72 DQ24 DQ21 65 66 DQ22 67 DQ23 68 GND8 GND7 NC11 J5 DQ39 SCB2 52 4 SCL {03,07} SDA {03,07} DCLK2 {03} DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 SCKE1 {03,10} DQ20 DQ19 DQ18 DQ17 DQ16 DQ38 54 DQ37 DCLK1 {03} SA11 SBA0 SA9 SA7 SA5 SA3 SA1 SRAS# SCE1# SM5 SM4 SCAS# SCB5 SCB4 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ36 51 DQ35 DQ34 DQ33 DQ32 50 SM3 SM2 SCE0# 4 49 48 47 46 NC8 61 62 NC9 CKE1 63 DQ20 VCC7 DQ19 DQ18 DQ17 DQ16 GND6 CB3 CB2 NC7 NC6 VCC6 NC5 M3 M2 CS2 45 44 43 BA1 39 A8 38 A10 37 36 A2 35 A4 34 GND4 33 A0 32 31 30 CS0 M1 28 M0 SM0 WE 27 NC2 26 VCC3 25 24 23 GND3 22 DQ15 21 CB0 20 SWE# SCB1 SCB0 DQ15 DQ13 DQ12 DQ11 DQ10 DQ9 GND2 DQ8 DQ7 DQ6 DQ5 DQ4 VCC1 DQ3 DQ2 DQ1 NC4 GND5 SDRAM-DIMM168P DQ0 GND1 VCC2 19 DQ14 18 14 DQ11 DQ14 13 DQ9 DQ10 12 10 DQ6 DQ8 8 DQ5 DQ7 7 9 DQ4 6 2 1 DQ0 3 3 DQ45 DQ44 DQ43 DQ42 DQ41 GND2 DQ40 DQ39 DQ38 DQ37 DQ36 VCC1 DQ35 DQ34 DQ33 NC1 CAS M5 RAS A7 A11 CLK1 126 NC4 125 124 VCC4 123 A9 122 BA0 121 120 A3 119 A5 118 GND4 117 A1 116 115 114 CS1 113 112 M4 111 109 NC2 110 VCC3 108 106 CB5 107 GND3 DQ47 105 CB4 104 5 J5 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 148 153 158 163 162 167 VCC8 168 SA2 NC11 164 165 SA0 SA1 166 CLK3 GND9 DQ61 159 160 DQ62 DQ63 161 DQ60 VCC7 157 DQ57 154 155 DQ58 DQ59 156 DQ56 DQ53 149 150 DQ54 151 DQ55 152 GND8 GND7 NC8 145 146 NC9 NC10 147 DQ52 VCC6 DQ51 DQ50 DQ49 DQ48 GND6 CB7 CB6 NC7 NC6 VCC5 NC5 M7 M6 CS3 CKE0 GND5 SDRAM-DIMM168P DQ32 GND1 VCC2 103 DQ46 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 5 DCLK3 {03} DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 SCB7 SCB6 SM7 SM6 SCKE0 {03,10} SCE1# 6 6 7 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 7 Date: Name: Title: 4/14/98 Sheet 8 06 SDRAM 168-PIN DIMM 80960RM 8 of 10 REV B D C B A D C B 1 AJ27 AM27 AK28 AM28 AK29 AK19 SGNT2# SGNT3# SGNT4# SGNT5# SPAR S_PAR S_GNT5 S_GNT4 S_GNT3 S_GNT2 S_GNT1 S_AD30 SGNT1# S_GNT0 S_REQ5 AH26 S_AD31 SAD31 AJ29 AM25 SAD30 AM26 S_AD29 AK25 SAD29 SGNT0# S_AD28 AJ25 SAD28 SREQ5# S_REQ4 S_AD27 2 AH25 SAD27 S_AD26 AM24 SAD26 S_AD25 AL24 SAD25 S_REQ3 SAD24 AL28 SAD23 AH28 AK24 S_AD24 AM23 S_AD23 AK23 S_AD22 AJ23 S_AD21 SAD21 SREQ4# SAD19 SREQ3# U15 i960RM SECONDARY PCI SIGNALS SAD18 S_REQ2 SAD17 S_REQ1 SAD16 AK27 3 AM22 S_AD19 AL22 S_AD18 AK22 S_AD17 AH22 S_AD16 AH19 S_AD15 AM18 S_AD14 SAD14 SAD15 S_AD20 AH23 SAD20 SAD22 S_AD13 AL18 SAD13 SREQ2# SAD12 S_REQ0 SAD11 AL26 SAD10 AH27 SAD9 S_AD4 +3V S_LOCK S_PERR S_RST S_SERR S_DEVSEL S_STOP S_TRDY S_IRDY S_FRAME S_C/BE3 S_C/BE2 S_C/BE1 S_C/BE0 2 R43 1 R56 1 R30 1 1/8W 5% 10 2 1/8W 5% 10 2 1/8W 5% 10 S_AD6 AJ15 S_AD5 SAD5 SREQ1# SAD8 AK15 AH15 SAD4 SAD6 AK18 S_AD12 AH18 S_AD11 AM17 S_AD10 AK17 S_AD9 AJ17 S_AD8 AM15 S_AD7 SAD7 S_AD3 AM14 SAD3 SREQ0# +5V AK20 AH20 AK26 AM19 AM20 AL20 AH21 AJ21 AK21 AH24 AM21 AJ19 AH17 1/2W 5% 100 R52 2 1 SLOCK# SPERR# SRST# SSERR# SDEVSEL# SSTOP# STRDY# SIRDY# SFRAME# SC/BE3# SC/BE2# SC/BE1# SC/BE0# 4 0.01uF CAP0805 1 2 SAD2 4 C77 C96 C61 0.01uF CAP0805 1 2 SAD1 AL14 S_AD2 AK14 S_AD1 AH14 S_AD0 SAD0 0.01uF CAP0805 1 2 4.7uF CAPT7343 1 2 4.7uF CAPT7343 1 2 3 C76 C92 C57 4.7uF CAPT7343 1 2 2 FAIL# {04} 5 IRQUART# {04} IRQFAN# {10} SINTD# SINTC# SINTB# SINTA# 5 5 4 5 4 NMI D26 B15 C22 VCCPLL3 VCCPLL2 VCCPLL1 E20 VCC5REF E12 FAIL A9 XINT4 D10 XINT5 C10 +5V 6 U15 i960RM JX CORE/I2C/JTAG 6 3 S_INTA/XINT0 7 2 R44 2.7K 8 1 C9 S_INTB/XINT1 E9 S_INTC/XINT2 A10 S_INTD/XINT3 B9 6 3 R3 2.7K 7 2 RNC4R8P 8 1 RNC4R8P 6 C8 A12 A21 B11 7 7 6 5 2 3 4 14 16 15 Sheet 8 07 of 10 4/14/98 REV B 80960RM I_RST# {04,05} Date: +3V 8 Name: SECONDARY PCI/960 CORE Title: 12 HEAD16SH 10 13 8 7 9 6 5 11 4 3 JTAG HEADER J6 2 1 8 1 R36 2.7K RNC4R8P SDA {03,06} SCL {03,06} CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 I_RST A11 LCDINIT TMS TRST C11 TDO E11 TDI TCK C12 SCL A8 SDA 7 R14 A SPCI {05,08,09} 1 1.5K 1/10W 5% 1 2 D C B A D C B A 1 SPCI CONN 2 SPCI CONN 1 1 2 2 CLKB {02} CAP0805 0.01uF CAP0805 0.01uF C19 2 1 C18 2 1 STCK {09} N12V P33V {01,02,04,09} CLKA {02} CAP0805 0.01uF CAP0805 0.01uF C27 2 1 C26 2 1 STCK {09} SPCI {05,07,09} GND12 INTB +5V6 GND8 GND7 PRSNT2 PRSNT1 REQ +3V3 B30 B31 B29 SAD19 B28 +3V4 AD19 AD21 GND12 C/BE3 B27 AD23 SAD21 SAD23 B26 B25 B24 AD25 SAD25 AD27 B23 AD29 B22 GND11 SAD27 +5V7 B20 AD31 B19 B18 CLK B17 GND10 B16 B15 GND9 B14 B13 B12 B11 B10 B9 B8 INTD B7 B6 TDO B5 +5V5 B4 TCK B3 GND6 B2 B21 SC/BE3# J1 J2 A22 A21 A20 A19 A18 A17 A4 A14 A13 A12 A19 A18 +3V1 A26 A25 3 +3V2 A27 A28 AD22 A29 AD20 A30 GND5 AD18 A31 IDSEL AD24 AD28 A22 A23 AD26 GND4 A24 A21 AD30 A20 GND3 RST A15 A16 +5V4 GNT A17 GND2 GND1 +5V3 A10 A11 A9 +5V1 A5 A6 INTA A7 INTC +5V2 A8 TDI TRST A1 A2 +12V TMS A3 AD18 A31 +3V2 A27 A28 AD22 A29 AD20 GND5 A30 A26 AD24 A25 AD26 A23 A24 GND4 AD28 +3V1 AD30 GND3 GNT +5V4 IDSEL CONNPCI_32 +3V4 B1 -12V B31 AD21 B30 AD19 B29 B28 C/BE3 B27 AD23 B26 SAD29 SAD31 SREQ1# SINTA# SINTC# SAD19 SAD21 SAD23 SC/BE3# B24 AD25 B25 +3V3 B23 AD27 GND11 AD29 AD31 +5V7 REQ GND10 CLK SAD25 B22 B21 B20 B19 B18 B17 A16 A15 RST A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A14 B16 GND9 GND2 GND1 +5V3 +5V2 INTC INTA +5V1 TDI TMS +12V TRST B15 GND8 GND7 PRSNT2 PRSNT1 INTD INTB +5V6 +5V5 TDO GND6 TCK -12V B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 CONNPCI_32 N12V SAD27 SAD29 SAD31 SREQ0# SINTD# SINTB# +5V 3 +12V +5V +12V SINTA# SAD18 SAD20 SAD22 SAD17 SAD24 SAD26 SAD28 SAD30 SGNT1# SRST# SINTD# SINTB# SAD18 SAD20 SAD22 SAD16 SAD24 SAD26 SAD28 SAD30 SGNT0# SRST# SINTC# STDI {09} STMS {09} STRST# {09} 4 P33V {01,02,04,09} STDI {09} STMS {09} STRST# {09} 4 2 R12 1 +5V P33V {01,02,04,09} 1/10W 5% 10K +5V P33V {01,02,04,09} 5 R10 1 1/10W 5% 10K 2 SAD1 SAD3 SAD5 SAD7 SAD8 SAD10 SAD12 SAD14 SC/BE1# SSERR# SPERR# SLOCK# SDEVSEL# SIRDY# SC/BE2# SAD17 SAD1 SAD3 SAD5 SAD7 SAD8 SAD10 SAD12 SAD14 SC/BE1# SSERR# SPERR# SLOCK# SDEVSEL# AD07 AD08 GND9 AD10 AD12 GND8 AD14 C/BE1 +3V7 SERR +3V6 PERR LOCK GND7 DEVSEL +3V5 IRDY GND6 C/BE2 AD17 +5V6 J1 A53 A52 A49 A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 A57 +5V3 A62 AD00 A58 A59 +5V1 A60 REQ64 +5V2 A61 AD02 AD06 A54 A55 AD04 GND5 A56 +3V4 C/BE0 AD09 GND4 AD11 AD13 +3V3 AD15 PAR GND3 SBO SDONE +3V2 STOP GND2 TRDY GND1 A33 A32 C/BE1 +3V7 SERR GND9 +3V8 AD03 +5V5 ACK64 +5V4 B62 +5V6 B61 B60 B59 GND10 B58 AD01 B57 B56 B55 AD05 B54 AD08 B53 AD07 B52 B49 AD12 B48 AD10 B47 AD14 B46 GND8 B45 B44 B43 B42 PERR B41 +3V6 B40 J2 A45 A44 A43 A52 A49 6 AD00 A58 A59 +5V1 A60 REQ64 A61 +5V2 +5V3 A62 AD02 A57 AD04 A55 A56 GND5 +3V4 A53 A54 AD06 C/BE0 AD09 AD13 A46 A47 AD11 GND4 A48 +3V3 AD15 PAR SBO A41 A42 GND3 SDONE A40 +5V 6 CONNPCI_32 B32 AD17 AD16 A32 B33 A33 C/BE2 +3V1 B34 GND6 FRAME A34 B35 A35 IRDY GND1 B36 +3V5 TRDY A36 B37 A37 DEVSEL GND2 B38 A38 STOP GND7 B39 LOCK +3V2 A39 B62 +5V4 B60 ACK64 B61 +5V5 B59 B57 GND10 B58 AD01 AD05 B56 AD03 B55 +3V1 AD16 FRAME CONNPCI_32 B54 +3V8 B53 B52 B49 B48 B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 SIRDY# B32 SAD17 +5V SC/BE2# 5 R9 1 2 R11 1 +5V P33V {01,02,04,09} 1/10W 5% 10K +5V P33V {01,02,04,09} 1/10W 5% 10K 2 SAD0 SAD2 SAD4 SAD6 SC/BE0# SAD9 SAD11 SAD13 SAD15 SPAR SSTOP# STRDY# SFRAME# SAD16 SAD0 SAD2 SAD4 SAD6 SC/BE0# SAD9 SAD11 SAD13 SAD15 SPAR SSTOP# STRDY# SFRAME# SAD16 7 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 SREQ5# SREQ4# SREQ3# SREQ2# SREQ1# SREQ0# SLOCK# SPERR# SSERR# SSTOP# SDEVSEL# SIRDY# STRDY# SFRAME# STCK STRST# STDI STMS 7 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 Sheet 8 08 of SECONDARY PCI BUS 1/2 4/14/98 80960RM +5V Date: 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 Name: Title: R31 2.7K RNC4R8P R33 2.7K RNC4R8P R38 2.7K RNC4R8P R45 2.7K RNC4R8P R1 2.7K RNC4R8P +5V 8 10 REV B D C B A D C B A 1 SPCI CONN 4 SPCI CONN 3 1 C10 1 C2 1 CLKD {02} CAP0805 0.01uF CAP0805 0.01uF C3 2 1 2 STCK {08} N12V P33V {01,02,04,08} CLKC {02} CAP0805 0.01uF CAP0805 0.01uF C11 2 1 2 STCK {08} SPCI {05,07,08} B24 TCK TDO +3V3 B30 B31 B29 SAD19 B28 +3V4 AD19 AD21 GND12 C/BE3 B27 AD23 SAD21 SAD23 B26 B25 AD27 B24 AD25 B23 AD29 B22 GND11 B21 SAD27 SAD25 REQ +5V7 B20 AD31 B19 B18 CLK J4 A19 A21 A26 A25 3 +3V2 A27 A28 AD22 A29 AD20 A30 GND5 AD18 A31 IDSEL AD24 AD28 A22 A23 AD26 GND4 A24 +3V1 AD30 A20 GND3 A18 GNT A17 B16 SAD29 SAD31 SREQ3# A13 A14 B17 GND10 +5V4 GND2 GND1 A12 +5V3 A10 A11 A9 RST A15 A16 GND8 GND7 PRSNT2 PRSNT1 A4 +5V1 A5 A6 INTA A7 INTC +5V2 A8 TDI TRST A1 A2 +12V TMS A3 AD18 A31 +3V2 A27 A28 AD22 A29 AD20 GND5 A30 A26 AD24 A25 B15 GND9 B14 B13 B12 B11 B10 B9 B8 INTD INTB +5V6 SINTC# B6 B5 +5V5 B4 B3 GND6 B2 J3 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AD26 A23 A24 GND4 AD28 +3V1 AD30 GND3 GNT +5V4 RST GND2 GND1 +5V3 +5V2 INTC INTA +5V1 TDI TMS +12V TRST 3 IDSEL CONNPCI_32 +3V4 B1 -12V B31 B7 SC/BE3# 2 GND12 AD21 B30 AD19 B29 B28 C/BE3 B27 AD23 B26 SINTA# SAD19 SAD21 SAD23 AD25 B25 +3V3 B23 AD27 GND11 AD29 AD31 +5V7 REQ SAD25 B22 B21 B20 B19 B18 GND10 CLK GND9 GND8 GND7 PRSNT2 PRSNT1 INTD INTB +5V6 +5V5 TDO GND6 TCK -12V CONNPCI_32 N12V SAD27 SAD29 SAD31 SREQ2# B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 SINTB# B6 B5 B4 B3 B2 B1 B7 +5V SINTD# SC/BE3# 2 +12V +5V +12V SAD18 SAD20 SAD22 SAD19 SAD24 SAD26 SAD28 SAD30 SGNT3# SRST# SINTB# SINTD# SAD18 SAD20 SAD22 SAD18 SAD24 SAD26 SAD28 SAD30 SGNT2# SRST# SINTA# SINTC# STDI {08} STMS {08} STRST# {08} 4 P33V {01,02,04,08} STDI {08} STMS {08} STRST# {08} 4 1/10W 5% 10K R8 2 1 +5V P33V {01,02,04,08} +5V P33V {01,02,04,08} R6 1 5 1/10W 5% 10K 2 SAD1 SAD3 SAD5 SAD7 SAD8 SAD10 SAD12 SAD14 SC/BE1# SSERR# SPERR# SLOCK# SDEVSEL# SIRDY# SC/BE2# SAD17 SAD1 SAD3 SAD5 SAD7 SAD8 SAD10 SAD12 SAD14 SC/BE1# SSERR# SPERR# SLOCK# SDEVSEL# AD07 AD08 GND9 AD10 AD12 GND8 AD14 C/BE1 +3V7 SERR +3V6 PERR LOCK GND7 DEVSEL +3V5 IRDY GND6 C/BE2 AD17 +5V4 +5V6 J3 A53 A52 A49 A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 A57 +5V3 A62 AD00 A58 A59 +5V1 A60 REQ64 +5V2 A61 AD02 AD06 A54 A55 AD04 GND5 A56 +3V4 C/BE0 AD09 GND4 AD11 AD13 +3V3 AD15 PAR GND3 SBO SDONE +3V2 STOP GND2 TRDY GND1 A33 A32 C/BE1 +3V7 SERR AD12 GND9 AD03 +5V4 +5V5 ACK64 B62 +5V6 B61 B60 B59 GND10 B58 AD01 B57 B56 +3V8 B55 AD05 B54 AD08 B53 AD07 B52 B49 B48 AD10 B47 AD14 B46 GND8 B45 B44 B43 B42 PERR B41 +3V6 B40 J4 A45 A44 A43 A52 A57 A56 AD00 A58 A59 +5V1 A60 REQ64 A61 +5V2 +5V3 A62 AD02 GND5 +3V4 A53 A54 AD06 AD04 A55 C/BE0 AD09 A49 AD13 A46 A47 AD11 GND4 A48 +3V3 AD15 PAR SBO A41 A42 GND3 SDONE A40 CONNPCI_32 B32 AD17 AD16 A32 B33 A33 C/BE2 +3V1 B34 GND6 FRAME A34 B35 A35 IRDY GND1 B36 +3V5 TRDY A36 B37 A37 DEVSEL GND2 B38 A38 STOP GND7 B39 LOCK +3V2 A39 B62 ACK64 B61 +5V5 B60 B59 GND10 B58 AD01 B57 AD05 B56 AD03 B55 +3V1 AD16 FRAME CONNPCI_32 B54 +3V8 B53 B52 B49 B48 B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 SIRDY# B32 SAD17 +5V SC/BE2# 5 6 +5V 6 R5 1 1/10W 5% 10K 2 SAD0 SAD2 SAD4 SAD6 SC/BE0# SAD9 SAD11 SAD13 SAD15 SPAR SSTOP# STRDY# SFRAME# SAD16 SAD0 SAD2 SAD4 SAD6 SC/BE0# SAD9 SAD11 SAD13 SAD15 SPAR SSTOP# STRDY# SFRAME# SAD16 +5V +5V P33V {01,02,04,08} 1/10W 5% 10K R7 2 1 P33V {01,02,04,08} 7 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 7 8 09 of 10 Sheet REV B 4/14/98 Date: 80960RM Name: SECONDARY PCI BUS 3/4 Title: 8 D C B A D C B 1 10uF CAPT7343 1 2 C54 R60 PWR J13 FAN 1 FAN CONN 10 1/10W 5% 1 2 2 GND 3 R28 C74 1 2 1 1 1/10W 5% 1/10W 5% 1 2 1 2 CAPT3216 1uF 68K 1/10W 5% 1 2 +5V R27 R26 R34 2 13 6 11 7 16 1 100K 1/10W 5% 1 2 22K 1/10W 5% 1 2 5 BATTU14 FASTCHG GND PGM3 PGM2 PGM1 PGM0 TLO CC TEMP REF DRV R20 BATT+ MAX712 VLIMIT V+ THI R24 1K 1/10W 5% 1 2 0.01uF CAP0805 1 2 47K 1/10W 5% 1 2 0.01uF CAP0805 1 2 R25 C68 R53 C58 0.01uF CAP0805 1 2 4.7K 1/10W 5% 1 2 C55 4.7K 1/10W 5% 1 2 R49 0.047uF CAP0805 1 2 3 12 8 10 9 4 3 2 Q4 2 2N6109 1 14 + CMR1-02 2 1 2 1 + 2 1 150 1/10W 5% 1 2 R48 C82 CR8 3 BATT_HLDR BT1 BT2 BATT_HLDR BATT_HLDR BT3 BT4 BATT_HLDR + 2 1 + 2 1 15 10uF CAPT7343 1 2 C52 + 6 7 - + 4 - 5 LM339 U10 LM339 U10 1 2 4 NOTE: VCC FOR LM339 IS +5V BATT_HLDR BT8 BT7 BATT_HLDR BATT_HLDR BT6 BT5 BATT_HLDR C65 2 1 2 1 0.47uF CAP1206 1 2 8 2 4 3 U8 MAX1651 IRQFAN# {07} GND FB REF SHDN OUT EXT CS V+ 1 7 6 5 BATTERY 5 5 4 0.05 1W 1% 1 2 CR7 MBRS340T3 8 SI9430 Q1 1 C53 L1 47uH +12V 4 R47 R21 1 2 3 5 6 7 2 7 6 5 4 3 2 6 C56 1 2 6 CAPT7343H 100uF C64 1 2 3 C51 2.4K 1/10W 5% 1 2 0.1uF CAP0805 1 2 1 2 1 2 1 10K 1/10W 5% 1 2 100K 1/10W 5% 1 2 22uF CAPT7343 1 2 R35 R32 C47 2 RST# {02} CAPT7343H 330uF A 1 33uF CAPT7343 1 2 C63 0.1uF CAP0805 1 2 U19 VCC F7 F6 F5 F4 F3 F2 F1 F0 20 19 18 17 16 15 14 13 12 8 - 9 + 10 - 11 + LM339 U10 LM339 U10 14 13 7 CYCLONE MICROSYSTEMS 25 SCIENCE PARK NEW HAVEN, CT 06511 +5V SPARES PALLV16V8-10JC I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 RAM3V {01,04,06} 11 9 8 7 6 5 4 3 2 1 PART # 101-1950-01 7 Date: Name: Title: 4/14/98 Sheet 8 10 BATTERY/MONITOR 80960RM RAM3V {01,04,06} SCKE1 {03,06} SCKE0 {03,06} 8 of 10 REV B D C B A PLD Code C MODULE BATT //TITLE SDRAM Battery Backup Enable //PATTERN 101-1809-01 //REVISION //AUTHOR J. Neumann //COMPANY Cyclone Microsystems Inc. //DATE 10/30/97 //CHIP PALLV16V8Z-20JI // 1/20/98 Modify target device to PALLV16V8Z-20JI //Initial release. PRSTn SCKE0 SCKE1 OUT0 OUT1 PIN 9;//Primary PCI reset PIN 13; //SDRAM bank 0 clock enable PIN 16; //SDRAM bank 1 clock enable PIN 14; //SCKE0 output enable PIN 17; //SCKE1 output enable EQUATIONS // If SDRAM clock enable goes low, SDRAM clock enable // must be held low to ensure that the SDRAM is held in auto refresh mode. // Reset going high will release the hold on SCKE. OUT0 = SCKE0.PIN & PRSTn //SCKE is the set term, PRSTn is the reset term # SCKE0.PIN & OUT0.PIN # !SCKE0.PIN & PRSTn; SCKE0 = 0; SCKE0.OE = !OUT0; //When OUT = 0, SCKE is grounded //When OUT = 1, SCKE is high impedance OUT1 = SCKE1.PIN & PRSTn # SCKE1.PIN & OUT1.PIN # !SCKE1.PIN & PRSTn; SCKE1 = 0; SCKE1.OE = !OUT1; END IQ80960RM/RN Evaluation Board Manual C-1 Recycling the Battery D The IQ80960RM/RN platform contains four AA NiCd batteries. Each battery has the logo of the Rechargeable Battery Recycling Corporation (RBRC) stamped on it. The recycling fees have been prepaid on these batteries. Do not dispose of a rechargeable battery with regular trash in a landfill. Rechargeable batteries contain toxic chemicals and metals that are harmful to the environment. Improperly disposing of rechargeable batteries is also illegal. The RBRC logo on a battery is a verification that recycling fees have been prepaid to the RBRC and such a battery can be recycled at no additional cost to the user. The RBRC is a non-profit corporation that promotes the recycling of rechargeable batteries, including NiCd batteries. Information on the RBRC program and the locations of participating recycling centers can be obtained by telephoning 1-800-8-BATTERY (in the USA), and following the recorded instructions. The information obtained from this telephone number is updated frequently, since the RBRC program is growing, the new recycling locations are being added regularly. IQ80960RM/RN Evaluation Board Manual D-1
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.2 Linearized : Yes Create Date : 1998:09:01 08:46:06 Producer : Acrobat Distiller 3.02 Title : Untitled Document Creator : FrameMaker 5.1.1P2c Modify Date : 1998:09:01 09:00:53 Page Count : 86 Page Mode : UseOutlinesEXIF Metadata provided by EXIF.tools