Evaluation Platform Board Manual IQ80960RM 27316003

User Manual: Evaluation Platform Board Manual IQ80960RM

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IQ80960RM/RN Evaluation
Platform
Board Manual
September 1998
Order Number: 273160-003
IQ80960RM/RN Evaluation Platform Board Manual
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The IQ80960RM/RN may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
IQ80960RM/RN Evaluation Platform Board Manual iii
Contents
1 Introduction......................................................................................................................................1-1
1.1 i960® RM/RN I/O Processor and IQ80960RM/RN Features .....................................................1-3
1.2 Software Development Tools.....................................................................................................1-3
1.3 IxWorks Software Development Toolset....................................................................................1-4
1.3.1 IxWorks Real-Time Operating System .........................................................................1-4
1.3.2 TORNADO Build Tools.................................................................................................1-4
1.3.3 TORNADO Test and Debug Tools ...............................................................................1-4
1.4 CTOOLS Software Development Toolset..................................................................................1-5
1.4.1 CTOOLS and the MON960 Debug Monitor..................................................................1-5
1.4.1.1 MON960 Host Communications...................................................................1-5
1.4.1.2 Terminal Emulation Method .........................................................................1-5
1.4.1.3 Host Debugger Interface (HDI) Method .......................................................1-5
1.5 About This Manual.....................................................................................................................1-6
1.6 Notational-Conventions .............................................................................................................1-7
1.7 Technical Support......................................................................................................................1-8
1.7.1 Intel Customer Electronic Mail Support ........................................................................1-8
1.7.2 Intel Customer Support Contacts..................................................................................1-8
1.7.3 Related Information ......................................................................................................1-9
2 Getting Started.................................................................................................................................2-1
2.1 Pre-Installation Considerations..................................................................................................2-1
2.2 Software Installation ..................................................................................................................2-1
2.2.1 Installing Software Development Tools ........................................................................2-1
2.3 Hardware Installation.................................................................................................................2-2
2.3.1 Battery Backup .............................................................................................................2-2
2.3.2 Installing the IQ80960RM/RN Platforms in the Host System........................................2-2
2.3.3 Verify IQ80960RM/RN Platform is Functional ..............................................................2-2
2.4 Creating and Downloading Executable Files.............................................................................2-3
2.4.1 Sample Download and Execution Using GDB960........................................................2-3
3 Hardware Reference........................................................................................................................3-1
3.1 Power Requirements .................................................................................................................3-1
3.2 SDRAM......................................................................................................................................3-1
3.2.1 SDRAM Performance ...................................................................................................3-2
3.2.2 Upgrading SDRAM .......................................................................................................3-3
3.3 Flash ROM.................................................................................................................................3-3
3.3.1 Flash ROM Programming.............................................................................................3-3
3.4 Console Serial Port....................................................................................................................3-4
3.5 Secondary PCI Bus Expansion Connectors ..............................................................................3-4
3.5.1 PCI Slots Power Availability..........................................................................................3-4
3.5.2 Interrupt and IDSEL Routing.........................................................................................3-5
3.6 Battery Backup ..........................................................................................................................3-5
3.7 Loss of Fan Detect.....................................................................................................................3-5
3.8 Logic Analyzer Headers.............................................................................................................3-6
3.9 JTAG Header.............................................................................................................................3-7
3.10 User LEDs .................................................................................................................................3-8
3.10.1 User LEDs During Initialization.....................................................................................3-8
iv IQ80960RM/RN Evaluation Platform Board Manual
4 i960® RM/RN I/O Processor Overview ............................................................................................4-1
4.1 CPU Memory Map.....................................................................................................................4-2
4.2 Local Interrupts..........................................................................................................................4-3
4.3 CPU Counter/Timers .................................................................................................................4-5
4.4 Primary PCI Interface ................................................................................................................4-5
4.5 Secondary PCI Interface ...........................................................................................................4-5
4.6 DMA Channels ..........................................................................................................................4-6
4.7 Application Accelerator Unit ......................................................................................................4-6
4.8 Performance Monitor Unit..........................................................................................................4-7
5 MON960 Support for IQ80960RM/RN.............................................................................................5-1
5.1 Secondary PCI Bus Expansion Connectors..............................................................................5-1
5.2 MON960 Components...............................................................................................................5-1
5.2.1 MON960 Initialization ...................................................................................................5-1
5.2.2 80960JT Core Initialization ...........................................................................................5-2
5.2.3 Memory Controller Initialization ....................................................................................5-2
5.2.4 SDRAM Initialization.....................................................................................................5-2
5.2.5 Primary PCI Interface Initialization................................................................................5-3
5.2.6 Primary ATU Initialization .............................................................................................5-3
5.2.7 PCI-to-PCI Bridge Initialization .....................................................................................5-4
5.2.8 Secondary ATU Initialization ........................................................................................5-4
5.3 MON960 Kernel.........................................................................................................................5-5
5.4 MON960 Extensions..................................................................................................................5-5
5.4.1 Secondary PCI Initialization..........................................................................................5-5
5.4.2 PCI BIOS Routines.......................................................................................................5-6
5.4.2.1 sysPCIBIOSPresent.....................................................................................5-6
5.4.2.2 sysFindPCIDevice........................................................................................5-7
5.4.2.3 sysFindPCIClassCode .................................................................................5-7
5.4.2.4 sysGenerateSpecialCycle............................................................................5-8
5.4.2.5 sysReadConfigByte......................................................................................5-8
5.4.2.6 sysReadConfigWord ....................................................................................5-9
5.4.2.7 sysReadConfigDword ..................................................................................5-9
5.4.2.8 sysWriteConfigByte....................................................................................5-10
5.4.2.9 sysWriteConfigWord ..................................................................................5-10
5.4.2.10 sysWriteConfigDword.................................................................................5-11
5.4.2.11 sysGetIrqRoutingOptions...........................................................................5-11
5.4.2.12 sysSetPCIIrq ..............................................................................................5-12
5.4.3 Additional MON960 Commands .................................................................................5-12
5.4.3.1 print_pci Utility............................................................................................5-12
5.5 Diagnostics / Example Code ...................................................................................................5-12
5.5.1 Board Level Diagnostics.............................................................................................5-12
5.5.2 Secondary PCI Diagnostics........................................................................................5-12
A Bill of Materials............................................................................................................... A-1
B Schematics.....................................................................................................................B-1
C PLD Code.......................................................................................................................C-1
D Recycling the Battery ..................................................................................................... D-1
IQ80960RM/RN Evaluation Platform Board Manual v
Figures
1-1 IQ80960RM/IQ80960RN Platform Functional Block Diagram...................................................1-1
1-2 IQ80960RN Platform Physical Diagram ....................................................................................1-2
3-1 LED Register Bitmap .................................................................................................................3-8
4-1 i960® RM/RN I/O Processor Block Diagram..............................................................................4-1
4-2 IQ80960RM/RN Platform Memory Map.....................................................................................4-2
4-3 i960® RM/RN I/O Processor Interrupt Controller Connections ..................................................4-4
4-4 i960® RM/RN I/O Processor DMA Controller ............................................................................4-6
4-5 Application Accelerator Unit.......................................................................................................4-7
Tables
1-1 Document Information ...............................................................................................................1-9
1-2 Cyclone Contacts.......................................................................................................................1-9
3-1 IQ80960RN Platform Power Requirements...............................................................................3-1
3-2 IQ80960RM Platform Power Requirements ..............................................................................3-1
3-3 SDRAM Performance ................................................................................................................3-2
3-4 SDRAM Configurations..............................................................................................................3-3
3-5 UART Register Addresses.........................................................................................................3-4
3-6 Secondary PCI Bus Interrupt and IDSEL Routing .....................................................................3-5
3-7 Logic Analyzer Header Definitions.............................................................................................3-6
3-8 JTAG Header Pinout..................................................................................................................3-7
3-9 Switch S1 Settings.....................................................................................................................3-7
3-10 Start-up LEDs MON960.............................................................................................................3-8
3-11 IQ80960RM/RN Connectors and LEDs.....................................................................................3-9
5-1 Initialization Modes ....................................................................................................................5-3
A-1 IQ80960RN Bill of Materials ..................................................................................................... A-1
A-2 IQ80960RM Bill of Materials..................................................................................................... A-5
B-1 IQ80960RN Schematics List..................................................................................................... B-1
B-2 IQ80960RM Schematics List ....................................................................................................B-2
IQ80960RM/RN
Evaluation Board Manual 1-1
Introduction
1
This manual describes the IQ80960RM and IQ80960RN evaluation platforms for Intel’s i960®
RM/RN I/O processor. The i960 RM/RN I/O processors combine an 80960JT core with two PCI
bus interfaces, as well as a memory controller, DMA channels, an interrupt controller interface,
and an I2C serial bus. The difference between the two processors is that the 80960RN utilizes
64-bit primary PCI and secondary PCI buses while the 80960RM utilizes both a 32-bit primary and
secondary PCI bus. The IQ80960RM and IQ80960RN platforms are full-length PCI adapter boards
and are 8.9” in height to accommodate four standard PCI connectors on the secondary PCI bus.
The boards can be installed in any PCI host system that complies with the PCI Local Bus
Specification Revision 2.1. PCI devices can be connected to the secondary bus to build powerful
intelligent I/O subsystems.
Figure 1-1. IQ80960RM/IQ80960RN Platform Functional Block Diagram
i960® RM/RN
I/O Processor
Flash
ROM
Logic
Analyzer
Interface
LED
Register
UART
Logic Analyzer Interface
Battery
Backup
Support
Primary PCI Bus 32/64-bits
SDRAM (x72)
Secondary PCI Slot 1
Secondary PCI Slot 2
Secondary PCI Slot 3
Secondary PCI Slot 4
Secondary PCI
Bus 32/64-bits
ROM Bus
User
LED
RS-232
Serial Port
Console
Port
1-2 IQ80960RM/RN
Evaluation Board Manual
Introduction
Figure 1-2. IQ80960RN Platform Physical Diagram
U15
64-Bit PCI NiCd Batteries
RS-232 Serial Port
Flash Memory
168-Pin SDRAM DIMM Socket
64-Bit Secondary PCI Slots
U11
J7
Logic Analyzer Connectors
U9
J8 J9 J10 J11 J12 J6 CR1 CR2 CR3 CR4 CR5
i960®
JTAG Port
J5
J4
J3
J2
J1
SW1
1 2 3 4
OFF
IQ80960RM/RN
Evaluation Board Manual 1-3
Introduction
1.1 i960® RM/RN I/O Processor and IQ80960RM/RN
Features
The i960 RM/RN I/O processor serves as the main component of a high performance, PCI-based
intelligent I/O subsystem. The IQ80960RM and IQ80960RN platforms allow the developer to
connect PCI devices to the i960 RM/RN I/O processors using the four secondary PCI expansion
connectors. The features of the IQ80960RM and IQ80960RN platforms are enumerated below and
shown in Figure 1-1 and Figure 1-2.
•i960 RM/RN I/O processor
•Modified PCI long-card form factor
•64-bit or 32-bit primary PCI bus interface (80960RM 32-bit only)
•64-bit or 32-bit secondary PCI bus connected to the primary PCI interface with a PCI-to-PCI
bridge (80960RM 32-bit only)
•DMA channels on both PCI buses
•I2C Serial Bus
•168-pin, 3.3V DIMM socket supporting 16 to 128 Mbytes of Synchronous DRAM organized
x72 to support Error Correction Code (ECC) and clocked at 66 MHz (ships with 16 M/ECC
installed)
•Serial console port based on 16C550 UART
•Eight user-programmable LEDs
•3 Indicator LEDs: processor has passed self-test, 3.3 V is supplied to SDRAM, and 3.3 V is
supplied to secondary PCI slots
•Flash ROM, 2 Mbytes
•Logic analyzer connectors for SDRAM bus, ROM bus and secondary PCI arbitration signals
•Fan heatsink monitor circuit
•Battery backup for SDRAM
•JTAG header
1.2 Software Development Tools
A number of software development tools are available for the i960® processor family1. This
manual provides information on two software development toolsets: Wind River System’s
IxWorks* and Intel’s CTOOLS. If you are using other software development tools, read through
the information in this chapter and in Chapter 2 to gain a general understanding of how to use your
tools with this board.
1. To view the electronic tools catalog, access http://developer.intel.com/design/develop.htm/ from the web.
1-4 IQ80960RM/RN
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Introduction
1.3 IxWorks Software Development Toolset
IxWorks is a complete toolset featuring an integrated development environment including a
compiler, assembler, linker, and debugger. It also features a real-time operating system.
1.3.1 IxWorks Real-Time Operating System
The IQ80960RM/RN platforms are equipped with Wind River Systems, Inc.’s IxWorks. IxWorks
provides for the elements of the I2O standard: an event-driven driver framework, host message
protocols, and executive modules for configuration and control. IxWorks also allows for the
writing of basic device drivers and provides NOS-to-driver independence. TORNADO for I2O
provides a visual environment for building, testing and debugging of I2O drivers.
1.3.2 TORNADO Build Tools
TORNADO for I2O includes a collection of supporting tools that provide a complete development
tool chain. These include the compiler, assembler, linker and binary utilities. Also provided is an
I2O module builder, which creates I2O-loadable modules.
1.3.3 TORNADO Test and Debug Tools
TORNADO for I2O test and debug tools include the dynamic loader, the CrossWind∗ debugger,
the WindSh* interactive shell, and a system browser.
The dynamic loader allows for interactive loading, testing, and replacement of individual object
modules that comprise a driver.
CrossWind is an extended version of GDB960. Using it you can debug I2O drivers by setting
breakpoints on desired I2O components. A variety of windows display source code, registers,
locals, stack frame, memory and so on.
WindSh allows you to communicate to the IQ80960RM/RN platform via an RS-232 serial port.
The IQ80960RM/RN platform supports port speeds from 300 to 115,200 bps. The shell can be
used to:
•control and monitor I2O drivers
•format, send and receive driver messages
•examine hardware registers
•run automated I2O test suites
The shell also provides essential debugging capabilities; including breakpoints, single stepping,
stack checking, and disassembly.
IQ80960RM/RN
Evaluation Board Manual 1-5
Introduction
1.4 CTOOLS Software Development Toolset
Intel’s i960 processor software development toolset, CTOOLS, features advanced
C/C++ - language compilers for the i960 processor family. CTOOLS development toolset is
available for Windows* 95/NT-based systems and a variety of UNIX workstation hosts. These
products provide execution profiling and instruction scheduling optimizations and include an
assembler, a linker, and utilities designed for embedded processor software development.
1.4.1 CTOOLS and the MON960 Debug Monitor
In place of IxWorks, the IQ80960RM/RN platform can be equipped with Intel’s MON960, an
on-board software monitor that allows you to execute and debug programs written for i960
processors in a non-I2O environment. The monitor provides program download, breakpoint, single
step, memory display, and other useful functions for running and debugging a program.
The IQ80960RM/RN platform works with the source-level debuggers provided with CTOOLS,
including GDB960 (command line version) and GDB960V (GUI version).
1.4.1.1 MON960 Host Communications
MON960 allows you to communicate and download programs developed for the IQ80960RM/RN
platform across a host system’s serial port or PCI interface. The IQ80960RM/RN platform supports
two methods of communication: terminal emulation and Host Debugger Interface (HDI).
1.4.1.2 Terminal Emulation Method
Terminal emulation software on your host system can communicate to MON960 on the
IQ80960RM/RN platform via an RS-232 serial port. The IQ80960RM/RN platform supports port
speeds from 300 to 115,200 bps. Serial downloads to MON960 require that the terminal emulation
software support the XMODEM protocol.
Configure the serial port on the host system for 300-115,200 baud, 8 bits, one stop bit, no parity
with XON/XOFF flow control.
1.4.1.3 Host Debugger Interface (HDI) Method
You may use a source-level debugger, such as Intel’s GDB960 and GDB960V to establish serial or
PCI communications with the IQ80960RM/RN platform. The MON960 Host Debugger Interface
(HDI) provides a defined messaging layer between MON960 and the debugger. For more
information on this interface, see the MON960 Debug Monitor User’s Manual (484290).
HDI connection requests cannot be detected by MON960 if the user has already initiated a
connection using a terminal emulator. In this case, the IQ80960RM/RN platform must be reset
before the debugger can connect to MON960.
1-6 IQ80960RM/RN
Evaluation Board Manual
Introduction
1.5 About This Manual
A brief description of the contents of this manual follows.
Chapter 1, “Introduction”
Introduces the IQ80960RM and IQ80960RN Evaluation Board features. This
chapter also describes Intel’s CTOOLS* and WindRiver Systems IxWorks*
software development tools, and defines notational-conventions and related
documentation.
Chapter 2, “Getting Started”
Provides step-by-step instructions for installing the IQ80960RM or IQ80960RN
platform in a host system and downloading and executing an application
program. This chapter also describes Intel’s software development tools, the
MON960 Debug Monitor, IxWORKS, software installation, and hardware
configuration.
Chapter 3, “Hardware
Reference”
Describes the locations of connectors, switches and LEDs on the IQ80960RM
and IQ80960RN platforms. Header pinouts and register descriptions are also
provided in this chapter.
Chapter 4, “i960® RM/RN
I/O Processor Overview” Presents an overview of the capabilities of the i960 RM/RN I/O processor and
includes the CPU memory map.
Chapter 5, “MON960
Support for IQ80960RM/RN” Describes a number of features added to MON960 to support application
development on the i960 RM/RN I/O processor.
Appendix A, “Bill of
Materials” Shows complete parts list IQ80960RM and IQ80960RN Evaluation Platforms.
Appendix B, “Schematics” Complete set of schematics for the IQ80960RM and IQ80960RN Evaluation
Platforms.
Appendix C, “PLD Code” Example PLD code used on IQ80960RM and IQ80960RN evaluation boards
for SDRAM battery backup.
Appendix D, “Recycling the
Battery” Information on the RBRC program and the locations of participating recycling
centers.
IQ80960RM/RN
Evaluation Board Manual 1-7
Introduction
1.6 Notational-Conventions
The following notation conventions are consistent with other i960 RM/RN I/O processor
documentation and general industry standards.
# or overbar In code examples the pound symbol (#) is appended to a signal name to
indicate that the signal is active. Normally inverted clock signals are
indicated with an overbar above the signal name (e.g., RAS).
Bold Indicates user entry and/or commands.
PLD signal names are in bold lowercase letters (e.g., h_off, h_on).
Italics Indicates a reference to related documents; also used to show emphasis.
Courier font Indicates code examples and file directories and names.
Asterisks (*) On non-Intel company and product names, a trailing asterisk indicates
the item is a trademark or registered trademark. Such brands and names
are the property of their respective owners.
UPPERCASE In text, signal names are shown in uppercase. When several signals share
a common name, each signal is represented by the signal name followed
by a number; the group is represented by the signal name followed by a
variable (n). In code examples, signal names are shown in the case
required by the software development tool in use.
Designations for
hexadecimal and
binary numbers
In text, instead of using subscripted “base” designators (e.g., FF16) or
leading “0x” (e.g., 0xFF) hexadecimal numbers are represented by a
string of hex digits followed by the letter H. A zero prefix is added to
numbers that begin with A through F. (e.g., FF is shown as 0FFH.) In
examples of actual code, “0x” is used. Decimal and binary numbers are
represented by their customary notations. (e.g., 255 is a decimal number
and 1111 1111 is a binary number. In some cases, the letter B is added to
binary numbers for clarity.)
1-8 IQ80960RM/RN
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Introduction
1.7 Technical Support
Up-to-date product and technical information is available electronically from:
•Intel’s World-Wide Web (WWW) Location: http://www.intel.com
•IQ80960RM and IQ80960RN Product Information: http://developer.intel.com/design/i960
For technical assistance, electronic mail (e-mail) provides the fastest route to reach engineers
specializing in IQ80960RM and IQ80960RN issues. Posting messages on the Embedded
Microprocessor Forum at http://support.intle.com/newsgroups/ is also a direct route for
IQ80960RM and IQ80960RN technical assistance. See Section 1.7.2.
Within the United States and Canada you may contact the Intel Technical Support Hotline. See
Section 1.7.1 for a list of customer support sources for the US and other geographical areas.
1.7.1 Intel Customer Electronic Mail Support
For direct support from engineers specialing in i960® Microprocessor issues send e-mail in english
to 960tools@intel.com.
Questions and other messages may be posted to the Embedded Microprocessor Forum at
http://support.intel.com/newsgroups/.
1.7.2 Intel Customer Support Contacts
Contact Intel Corporation for technical assistance for the IQ80960RM/RN evaluation platform.
Country Literature Customer Support Number
United States 800-548-4725 800-628-8686
Canada 800-468-8118 or 303-297-7763 800-628-8686
Europe Contact local distributor Contact local distributor
Australia Contact local distributor Contact local distributor
Israel Contact local distributor Contact local distributor
Japan Contact local distributor Contact local distributor
IQ80960RM/RN
Evaluation Board Manual 1-9
Introduction
1.7.3 Related Information
To order printed manuals from Intel, contact your local sales representative or Intel Literature Sales
(1-800-548-4725).
Contact Cyclone Microsystems for additional information about their products and literature:
Table 1-1. Document Information
Product Document Name Company/ Order #
All
Developers’ Insight CD-ROM
Intel # 273000
80960RM/RN
i
960®
RM/RN I/O Processor Developer’s Manual
Intel # 273158
80960RM I/O Processor
Data Sheet Intel # 273156
80960RN I/O Processor
Data Sheet Intel # 273157
MON960 Debug Monitor User’s Guide
Intel #484290
PCI Local Bus Specification
Revision 2.1 PCI Special Interest Group
1-800-433-5177
Writing I
2
O Device Drivers in IxWorks
Wind River Systems, Inc.
#DOC-1173-8D-02
IxWorks Reference Manual
Wind River Systems, Inc.
#DOC-1173-8D-03
VxWorks Programmer’s Guide
Wind River Systems, Inc.
#DOC-11045-ZD-01
Tornado User’s Guide
Wind River Systems, Inc.
#DOC-1116-8D-01
Tornado for I
2
O
Wind River Systems, Inc.
#DOC-12381-8D-00
Tornado for I
2
O Compact Disk
Rev. 1.0 #TDK-12380-ZC-00
Table 1-2. Cyclone Contacts
Cyclone Microsystems
25 Science Park
New Haven CT 06511
Phone: 203-786-5536
FAX: 203-786-5025
e-mail: info@cyclone.com
WWW: http://www.cyclone.com
IQ80960RM/RN
Evaluation Board Manual 2-1
Getting Started
2
This chapter contains instructions for installing the IQ80960RM/RN platform in a host system and,
how to download and execute an application program using Wind River System’s IxWorks∗ or
Intel’s CTOOLS software development toolsets.
2.1 Pre-Installation Considerations
This section provides a general overview of the components required to develop and execute a
program on the IQ80960RM/RN platform. IQ80960RM/RN evaluation boards support two
software development toolsets, Wind River System’s IxWorks and Intel’s CTOOLS.
IxWorks is a complete toolset featuring an integrated development environment including a
compiler, assembler, linker, and debugger. It also features a real-time operating system. If you are
using the IxWorks operating system with the TORNADO* development environment, refer to the
Wind River Systems, Inc. documentation referenced in Section 1.7.3.
CTOOLS is a complete C/C++-language software-development toolset for developing embedded
applications to run on i960 processors. It contains a C/C++ compiler, the gcc960 and ic960 compiler
driver programs, an assembler, runtime libraries, a collection of software-development tools and
utilities, and printed and on-line documentation. The MON960 Debug Monitor User’s Guide fully
describes the components of MON960, including MON960 commands, the Host Debugger Interface
Library (HDIL), and the MONDB.EXE utility. If you are using MON960 and the CTOOLS toolset,
refer to section Section 2.2.1, “Installing Software Development Tools” on page 2-1.
See Chapter 1 for more information on the IxWorks and CTOOLS features.
The IQ80960RM/RN evaluation boards are supplied with IxWorks intelligent real-time operating
system pre-loaded into the on-board Flash. You also have the option of installing the MON960
debug monitor, which is required if you are using the CTOOLS debugging tools, GDB960,
GDB960V, or MONDB. Section 3.3.1 describes the Flash ROM programming utility, which allows
you to load MON960 onto the platform or re-load IxWorks.
2.2 Software Installation
2.2.1 Installing Software Development Tools
If you haven’t done so already, install your development software as described in its manuals. All
references in this manual to CTOOLS or CrossWind assume that the default directories were
selected during installation. If this is not the case, substitute the appropriate path for the default
path wherever file locations are referenced in this manual.
2-2 IQ80960RM/RN
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Getting Started
2.3 Hardware Installation
Follow these instructions to get your new IQ80960RM/RN platform running. Be sure all items on
the checklist were provided with your IQ80960RM/RN.
Warning: Static charges can severely damage the IQ80960RM/RN platforms. Be sure you are properly
grounded before removing the IQ80960RM/RN platform from the anti-static bag.
2.3.1 Battery Backup
Battery backup is provided to save any information in SDRAM during a power failure. The
IQ80960RM/RN platform contains four AA NiCd batteries, a charging circuit and a regulator
circuit. The batteries installed in the IQ80960RM/RN platform are rated at 600 mA/Hr.
SDRAM technology provides a simple way of enabling data preservation through the self-refresh
command. When the processor receives an active Primary PCI reset it issues the self-refresh
command and drives the SCKE signals low. Upon seeing this condition, a PAL on the
IQ80960RM/RN platform holds SCKE low before the processor loses power. The batteries
maintain power to the SDRAM and the PAL to ensure self-refresh mode. When the PAL detects
PRST# returning to inactive state, the PAL releases the hold on SCKE.
The battery circuit can be disabled by removing the batteries. LED CR4 indicates when the SDRAMs
have sufficient power. If the batteries remain in the evaluation platform when it is depowered and/or
removed from the chassis, the batteries will maintain the SDRAM for approximately 30 hours. Once
power is again applied, the batteries will be fully charged in about 4 hours.
2.3.2 Installing the IQ80960RM/RN Platforms in the Host System
If you are installing the IQ80960RM/RN platform for the first time, visually inspect the board for
any damage that may have occurred during shipment. If there are visible defects, return the board
for replacement. Follow the host system manufacturer’s instructions for installing a PCI adapter.
The IQ80960RM/RN platform is a full-length PCI adapter and requires a PCI slot that is free from
obstructions. The IQ80960RM/RN platform is taller than specified in the PCI Local Bus
Specification Revision 2.1. The extended height of the board will require you to keep the cover off
of your PC. Refer to Chapter 3 for physical dimensions of the board.
2.3.3 Verify IQ80960RM/RN Platform is Functional
These instructions assume that you have already installed the IQ80960RM/RN platform in the host
system as described in Section 2.3.2.
1. To connect the serial port for communicating with and downloading to the IQ80960RM/RN
platform, connect the RS-232 cable (provided with the IQ80960RM/RN) from a free serial
port on the host system to the phone jack-style connector on the IQ80960RM/RN platform.
2. Upon power-up, the red FAIL LED turns off, indicating that the processor has passed its self-test.
3. If you have IxWorks installed in the flash ROM, the user LEDs display the binary pattern 99H.
In the IxWorks development environment, raw serial input/output is not used. Instead, the
Wind DeBug (WDB) protocol is run over the serial port, to allow communication with
Tornado development tools. If the terminal emulation package is running at 115,200 baud, the
letters “WDB_READY” display prior to launching in the WDB serial protocol.
IQ80960RM/RN
Evaluation Board Manual 2-3
Getting Started
4. If you have MON960 installed in the flash ROM, press <ENTER> on a terminal connected to
the IQ80960RM/RN platform to bring up the MON960 prompt. MON960 automatically
adjusts its baud rate to match that of the terminal at start-up. At baud rates other than 9600, it
may be necessary to press <ENTER> several times.
2.4 Creating and Downloading Executable Files
To download code to the IQ80960RM/RN platform running IxWorks, consult Wind River
documentation on the supplied TORNADO for I2O CD-ROM. To download code to the
IQ80960RM/RN platform, your compiler produces an ELF-format object file.
To download code to the IQ80960RM/RN platform running CTOOLS, consult the CTOOLS
documentation for information regarding compiling, linking, and downloading applications.
During a download, MON960 checks the link address stored in the ELF file, and stores the file at
that location on the IQ80960RM/RN platform. If the executable file is linked to an invalid address
on the IQ80960RM/RN platform, MON960 aborts the download.
2.4.1 Sample Download and Execution Using GDB960
This example shows you how to use GBD960 to download and execute a file named myapp via
the serial port.
•Invoke GDB960. From a Windows 95/NT command prompt, issue the command:
gdb960 -r com2 myapp
This command establishes communication and downloads the file myapp.
•To execute the program, enter the command from the GDB960 command prompt:
(gdb960) run
More information on the GDB960 commands mentioned in this section can be found in the
GDB960 User’s Manual.
IQ80960RM/RN
Evaluation Board Manual 3-1
Hardware Reference
3
3.1 Power Requirements
The IQ80960RM/RN platform draws power from the PCI bus. The power requirements of the
IQ80960RM/RN platforms are shown in Table 3-1 and Table 3-2. The numbers do not include the
power required by a PCI card(s) mounted on one or more of the IQ80960RM/RN platforms’ four
expansion slots.
3.2 SDRAM
The IQ80960RM/RN platform is equipped with a 168-pin DIMM socket formatted to accept +3.3V
synchronous DRAM with or without Error Correction Code (ECC). The socket will accept SDRAM
from 8 Mbytes to 128 Mbytes. 128 Mbyte SDRAMs are available in both x64 and x72 configurations.
Note that 8 Mbyte SDRAMs are only for x64 or non-ECC memory. The SDRAM is accessible from
either of the PCI buses, via the ATUs, and the local bus on the IQ80960RM/RN platform.
Table 3-1. IQ80960RN Platform Power Requirements
Voltage Typical Current Maximum Current
+3.3 V 0 V* 0 V*
+5 V 1.45 A 1.96 A
+12 V 286 mA 485 mA
-12 V 1 mA 1 mA
NOTE: Does not include the power required by a PCI card(s) mounted on the IQ80960RN platform.
* +3.3V for 80960RN Processor created on board from +5V.
Table 3-2. IQ80960RM Platform Power Requirements
Voltage Typical Current Maximum Current
+3.3 V 0 V* 0 V*
+5 V 1.32 A 1.86 A
+12 V 284 mA 485 mA
-12 V 1 mA 1 mA
NOTE: Does not include the power required by a PCI card(s) mounted on the IQ80960RM platform.
* +3.3V for 80960RM Processor created on board from +5V.
3-2 IQ80960RM/RN
Evaluation Board Manual
Hardware Reference
3.2.1 SDRAM Performance
The IQ80960RM/RN platform uses 72-bit SDRAM with ECC or 64-bit SDRAM without ECC.
SDRAM allows zero data-to-data wait state operation at 66 MHz. The memory controller unit
(MCU) of the i960® RM/RN I/O processor supports SDRAM burst lengths of four. A burst length
of four enables seamless read/write bursting of long data streams, as long as the MCU does not
cross the page boundary. Page boundaries are naturally aligned 2 Kbyte blocks. 72-bit SDRAM
with ECC allows a maximum throughput of 528 Mbytes per second.
Both 16 Mbit and 64 Mbit SDRAM devices are supported. The MCU keeps two pages per bank
open simultaneously for 16 Mbit devices and 4 pages per bank for 64 Mbit devices. Simultaneously
open pages allow for greater performance for sequential access, distributed across multiple internal
bus transactions. Table 3-3 shows read and write examples of a single 8 byte access and for a
multiple 40 byte access.
Note that if ECC is enabled and you attempt a partial write — less than 64 bits — you will incur a
penalty. Because ECC is enabled, the MCU will translate the write into a read-modify-write
transaction. Therefore, for a single byte write the clock count will be 11.
Table 3-3. SDRAM Performance
Cycle Type Table Clocks Performance Bandwidth
Read Page Hit (8 bytes) 7 76 Mbytes/sec
Read Page Miss (8 bytes) 12 44 Mbytes/sec
Read Page Hit (40 bytes) 11 240 Mbytes/sec
Read Page Miss (40 bytes) 16 165 Mbytes/sec
Write Page Hit (8 bytes) 4 132 Mbytes/sec
Write Page Miss (8 bytes) 8 66 Mbytes/sec
Write Page Hit (40 bytes) 8 330 Mbytes/sec
Write Page Miss (40 bytes) 12 220 Mbytes/sec
IQ80960RM/RN
Evaluation Board Manual 3-3
Hardware Reference
3.2.2 Upgrading SDRAM
The IQ80960RM/RN is equipped with 16 Mbytes of SDRAM with ECC inserted in the 168-pin
DIMM socket. The memory may be expanded by inserting up to a 128 Mbyte module into the
DIMM socket. The various memory combinations are shown in Table 3-4. Only 168-pin +3.3V
SDRAM modules with or without ECC rated at 10 ns should be used on the IQ80960RM/RN
platform. The column labeled ECC determines if that particular memory configuration can be used
with ECC.
3.3 Flash ROM
An E28F016S5 (2 Mbytes) Flash ROM is included on the IQ80960RM/RN platform. This Flash
ROM contains IxWorks* and may be used to store user applications.
3.3.1 Flash ROM Programming
Two types of Flash ROM programming exist on the IQ80960RM/RN platform. The first is normal
application development programming. This occurs using IxWorks to download new software and
the 80960JT core to write the new code to the Flash ROM. During this time the boot sectors
(containing IxWorks) are write protected.
The second type of Flash ROM programming is loading the boot sectors. You will not be required
to load the boot sectors except:
•To load MON960
•To load a new release of IxWorks
•To change between the check build and the free build of IxWorks
The following steps are required to program the Flash ROM boot sectors:
1. Set switch S1 #’s 1 and 2 to the on position.
2. Reset the board by cycling power on the workstation.
3. Run the Intel DOS-based flash utility to program the Flash ROM boot sectors.
4. Set switch S1 #’s 1 and 2 to the off position.
5. Reset the board by cycling power on the workstation.
Table 3-4. SDRAM Configurations
SDRAM
Technology SDRAM
Arrangement # Banks Row Column ECC Total Memory
SIze
16 Mbit
2M x 8 111 9 Yes 16 Mbytes
2 Yes 32 Mbytes
1M x 16 111 8 No 8 Mbytes
2 No 16 Mbytes
64 Mbit
8M x 8 112 9 Yes 64 Mbytes
2 Yes 128 Mbytes
4M x 16 112 8 No 32 Mbytes
2 No 64 Mbytes
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Hardware Reference
3.4 Console Serial Port
The console serial port on the IQ80960RM/RN platform, based on a 16C550 UART, is capable of
operation from 300 to 115,200 bps. The port is connected to a phone jack-style plug on the
IQ80960RM/RN platform. The DB25 to RJ-45 cable included with the IQ80960RM/RN can be
used to connect the console port to any standard RS-232 port on the host system.
The UART on the IQ80960RM/RN platform is clocked with a 1.843 MHz clock, and may be
programmed to use this clock with its internal baud rate counters. The UART register addresses are
shown in Table 3-5; refer to the 16C550 device data book for a detailed description of the registers
and device operation. Note that some UART addresses refer to different registers depending on
whether a read or a write is being performed.
3.5 Secondary PCI Bus Expansion Connectors
Four PCI Expansion Slots are available on the IQ80960RM/RN platform. The IQ80960RM
supports 32-bit PCI expansion and the IQ80960RN supports 64-bit PCI expansion. The slots are
designed for +5V PCI signalling and accommodate PCI cards with +5V or universal signalling
capabilities.
3.5.1 PCI Slots Power Availability
Power from the Primary PCI bus, +3.3V, +5V, +12V, and –12V, is routed to the Secondary PCI
bus expansion slots. +3.3V is only available at the secondary PCI slots if the host system makes
+3.3V available on the Primary PCI slots. LED CR5 indicates if this power is available.
Table 3-5. UART Register Addresses
Address Read Register Write Register
E000 0000H Receive Holding Register Transmit Holding Register
E000 0001H Unused Interrupt Enable Register
E000 0002H Interrupt Status Register FIFO Control Register
E000 0003H Unused Line Control Register
E000 0014H Unused Modem Control Register
E000 0015H Line Status Register Unused
E000 0016H Modem Status Register Unused
E000 0017H Scratchpad Register Scratchpad Register
IQ80960RM/RN
Evaluation Board Manual 3-5
Hardware Reference
3.5.2 Interrupt and IDSEL Routing
3.6 Battery Backup
Battery backup is provided to save any information in SDRAM during a power failure. The
IQ80960RM/RN platform contains four AA NiCd batteries, a charging circuit and a regulator
circuit. The batteries installed in the IQ80960RM/RN platform are rated at 600 mA/Hr.
SDRAM technology provides a simple way of enabling data preservation though the self-refresh
command. When the processor receives an active Primary PCI reset it will issue the self-refresh
command and drive the SCKE signals low. Upon seeing this condition a PAL on the
IQ80960RM/RN platform will hold SCKE low before the processor loses power. The batteries will
maintain power to the SDRAM and the PAL to ensure self-refresh mode. When the PAL sees
PRST# returning to inactive state the PAL will release the hold on SCKE.
The battery circuit can be disabled by removing the batteries. LED CR4 indicates when the
SDRAMs have sufficient power. If the batteries remain in the evaluation platform when it is
depowered and/or removed from the chassis, the batteries will maintain the SDRAM for
approximately 30 hours. Once power is again applied, the batteries will be fully charged in about
four hours.
3.7 Loss of Fan Detect
The i960 RM/RN I/O processor can be cooled by an active heat sink mounted on top. The fan
provides a square wave output that is monitored by a comparator circuit on the IQ80960RM/RN
platform. The frequency of the fan output is approximately 9K RPM. If the frequency falls below
approximately 8K RPM the circuit will provide an interrupt to the processor.
Note: The standard production boards will be shipped with attached passive heat sinks. In the case of
utilizing a passive heat sink, the processor never sees an interrupt from not having a fan.
Table 3-6. Secondary PCI Bus Interrupt and IDSEL Routing
Connector IDSEL INTA# INTB# INTC# INTD#
J11 SAD16 SINTA# SINTB# SINTC# SINTD#
J12 SAD17 SINTB# SINTC# SINTD# SINTA#
J13 SAD18 SINTC# SINTD# SINTA# SINTB#
J14 SAD19 SINTD# SINTA# SINTB# SINTC#
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Hardware Reference
3.8 Logic Analyzer Headers
There are five logic analyzer connectors on the IQ80960RM/RN platform. The connectors are
Mictor type, AMP part # 767054-1. Hewlett-Packard and Tektronix manufacture and sell
interfaces to these connectors. The logic analyzer connectors allow for interfacing to the SDRAM
and ROM buses along with secondary PCI arbitration signals. Table 3-7 shows the connectors and
the pin assignments for each.
Table 3-7. Logic Analyzer Header Definitions
PIN J9 J11 J12 J10 J8
3 SDRAMCLK
4 DQ15 SDQM7 DQ31 RAD15
5 DQ14 SDQM6 DQ30 RAD14
6 DQ13 SDQM5 DQ29 RAD13
7 DQ12 SDQM4 DQ28 RAD12
8 DQ11 SDQM3 DQ27 RAD11
9 DQ10 SDQM2 DQ26 RAD10
10 DQ9 SDQM1 DQ25 RAD9
11 DQ8 SDQM0 DQ24 RAD8
12 DQ7 SCB7 DQ23 RAD7
13 DQ6 SCB6 DQ22 RAD6
14 DQ5 SCB5 DQ21 RAD5
15 DQ4 SCB4 DQ20 RAD4
16 DQ3 SCB3 DQ19 SCE0# RAD3
17 DQ2 SCB2 DQ18 SCE1# RAD2
18 DQ1 SCB1 DQ17 SBA1 RAD1
19 DQ0 SCB0 DQ16 SBA0 RAD0
20 DQ32 SA0 DQ48 SREQ0# RAD16
21 DQ33 SA1 DQ49 SREQ1#
22 DQ34 SA2 DQ50 SREQ2#
23 DQ35 SA3 DQ51 SREQ3# RALE
24 DQ36 SA4 DQ52 SREQ4# RCE0#
25 DQ37 SA5 DQ53 SREQ5# RCE1#
26 DQ38 SA6 DQ54 SGNT0# ROE#
27 DQ39 SA7 DQ55 SGNT1# RWE#
28 DQ40 SA8 DQ56 SGNT2#
29 DQ41 SA9 DQ57 SGNT3# I_RST#
30 DQ42 SA10 DQ58 SGNT4#
31 DQ43 SA11 DQ59 SGNT5#
32 DQ44 DQ60
33 DQ45 SWE# DQ61
34 DQ46 SCAS# DQ62
35 DQ47 SRAS# DQ63
36 P_PCICLK RALE
IQ80960RM/RN
Evaluation Board Manual 3-7
Hardware Reference
3.9 JTAG Header
The JTAG header allows debugging hardware to be quickly and easily connected to some of the
IQ80960RM/RN processor’s logic signals.
The JTAG header is a 16-pin header. A 3M connector (part number 2516-6002UG) is required to
connect to this header. The pinout for the JTAG header is shown in Table 3-8. The header and
connector are keyed using a tab on the connector and a slot on the header to ensure proper installation.
Each signal in the JTAG header is paired with its own ground connection to avoid the noise problems
associated with long ribbon cables. Signal descriptions are found in the i960® RM/RN I/O Processor
Developer’s Manual, 80960RM I/O Processor Data Sheet and the 80960RN I/O Processor Data Sheet.
Table 3-9 describes switch setting options and defaults. These switch settings are sampled at
Primary PCI Reset. See Table 5-1 “Initialization Modes” on page 5-3 for processor initialization
configurations.
a. This switch is active for IQ80960RN ONLY.
Table 3-8. JTAG Header Pinout
Pin Signal Input/Output to 80960RM/RN Pin Signal
1 TRST# IN 2 GND
3 TDI IN 4 GND
5 TDO OUT 6 GND
7TMS IN 8GND
9TCK IN 10GND
11 LCDINIT# IN 12 GND
13 I_RST# OUT 14 GND
15 PWRVLD OUT 16 GND
Table 3-9. Switch S1 Settings
Position Name Description Default
S1-1 RST_MODE# Determines if the processor is to be held in reset.
ON = hold in rest
OFF = allows processor initialization OFF
S1-2 RETRY Determines if the Primary PCI interface will be disabled.
ON = allows Primary PCI configuration cycles to occur
OFF = retries all Primary PCI configuration cycles OFF
S1-3 32BITMEM_EN# Notifies Memory Controller of the SDRAM width.
ON = Memory Controller utilizes 32-bit SDRAM access protocol
OFF = Memory Contoller utilizes 64-bit SDRAM access protocol OFF
S1-4a32BITPCI_EN# Determines whether Secondary PCI bus is a 32- or 64-bit bus.
ON = indicates Secondary PCI bus is a 32-bit bus
OFF = indicates Secondary PCI bus is a 64-bit bus OFF
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Hardware Reference
3.10 User LEDs
The IQ80960RM/RN platform has a bank of eight user-programmable LEDs, located on the upper edge of
the adapter board. These LEDs are controlled by a write-only register and used as a debugging aid during
development. Software can control the state of the user LEDs by writing to the LED Register, located at
E004 0000H. Each of the eight bits of this register correspond to one of the user LEDs. Clearing a bit in the
LED Register by writing a “0” to it turns the corresponding LED “on”, while setting a bit by writing a “1”
to it turns the corresponding LED “off”. Resetting the IQ80960RM/RN platform results in clearing the
register and turning all the LEDs “on”. The LED Register bitmap is shown in Figure 3-1.
The user LEDs are numbered in descending order from left to right, with LED7 being on the left
when looking at the component side of the adapter.
3.10.1 User LEDs During Initialization
MON960 indicates the progress of its hardware initialization on the user LEDs. In the event that
initialization should fail for some reason, the number of lit LEDs can be used to determine the
cause of the failure. Table 3-10 lists the tests that correspond to each lit LED.
Figure 3-1. LED Register Bitmap
76543210
User LED 7
User LED 6
User LED 5
User LED 4
User LED 3
User LED 2
User LED 1
User LED 0
Table 3-10. Start-up LEDs MON960
LEDs Tests
LED 0 SDRAM serial EEPROM checksum validated
LED 1 UART walking ones test passed
LED 2 DRAM walking ones test passed
LED 3 DRAM multiword test passed
LED 4 Hardware initialization started
LED 5 Flash ROM initialized
LED 6 PCI-to-PCI Bridge initialized
LED 7 UART internal loopback test passed
IQ80960RM/RN
Evaluation Board Manual 3-9
Hardware Reference
Table 3-11 lists the connectors and LEDs.
Table 3-11. IQ80960RM/RN Connectors and LEDs
Item Description
J1-J4 Secondary PCI bus expansion connector
J5 168-pin SDRAM DIMM socket
J6 JTAG connector
J7 Serial port connector
J8 Logic analyzer connector for flash ROM bus
J10 Logic analyzer connector for Secondary PCI bus arbitration signals
J9, J11, J12 Logic analyzer connector for access to SDRAM bus
J13 Active heatsink connector for example fan monitor circuit
CR1, CR2 Eight user LEDs
CR3 Self-test fail LED
CR4 Battery backup SDRAM, 3.3 V available
CR5 Indicates host system providing 3.3 V to Secondary PCI bus connectors
S1 DIP switch (Tabl e 3-9)
IQ80960RM/RN
Evaluation Board Manual 4-1
i960
®
RM/RN I/O Processor Overview
4
This chapter describes the features and operation of the processor on the IQ80960RM/RN
platform. For more detail, refer to the i960® RM/RN I/O Processor Developer’s Manual.
Figure 4-1. i960® RM/RN I/O Processor Block Diagram
80960 Core
Processor
Memory
Controller Bus
Interface
Unit
I2C Bus
Interface
Application
Accelerator
Internal
Arbitration
I2C Serial Bus
Local Memory
(SDRAM, Flash)
64-bit Internal Bus
One DMA
Channel
Address
Translation
Unit
64-bit/32-bit Secondary PCI Bus
PCI to PCI
Bridge
Messaging
Unit Two DMA
Channels
Address
Translation
Unit
64-bit/32-bit Primary PCI Bus
Performance
Monitoring
Unit
Secondary
PCI
Arbitration
4-2 IQ80960RM/RN
Evaluation Board Manual
i960® RM/RN I/O Processor Overview
4.1 CPU Memory Map
The memory map for the IQ80960RM/RN platform is shown in Figure 4-2. All addresses below
9002 0000H on the IQ80960RM/RN platform are reserved for various functions of the i960
RM/RN I/O processor, as shown on the memory map. Documentation for these areas, as well as the
processor memory mapped registers at FF00 0000H and the IBR, can be found in the i960® RM/RN
I/O Processor Developer’s Manual.
Figure 4-2. IQ80960RM/RN Platform Memory Map
FF00 0000H
FEE0 0000H
E004 0000H
E000 0000H
B000 0000H
A000 0000H
9002 0000H
8000 0000H
0000 2000H
0000 0800H
0000 0400H
0000 0000H
F000 0000H
F000 0000H
E000 0000H
0000 1900H
Flash ROM
and
Processor Registers
On-board Devices
Reserved
DRAM
Reserved
ATU Outbound
Translation Windows
ATU Outbound
Direct Addressing Window
Reserved
Peripheral
Memory Mapped Registers
Reserved
Processor Internal Data RAM
Processor
Memory Mapped
Flash ROM
Reserved
LED Register
UART
Registers
(write only)
IQ80960RM/RN
Evaluation Board Manual 4-3
i960® RM/RN I/O Processor Overview
4.2 Local Interrupts
The i960 RM/RN I/O processor is built around an 80960JT core, which has seven external interrupt
lines designated XINT0# through XINT5# and NMI#. In the i960 RM/RN I/O processor, these
interrupt lines are not directly connected to external interrupts, but pass through a layer of internal
interrupt routing logic. Figure 4-3 shows the interrupt connections on the i960 RM/RN I/O processor.
XINT0# through XINT3# on the 80960JT core can be used to receive PCI interrupts from the
secondary PCI bus, or these interrupts can be passed through to the primary PCI interface,
depending on the setting of the XINT Select bit of the PCI Interrupt Routing Select Register in the
i960 RM/RN I/O processor. On the IQ80960RM/RN platform, XINT0# through XINT3# are
configured to receive interrupts from the secondary PCI bus.
XINT4# and XINT5# on the i960 RM/RN I/O processor may be connected to interrupt sources
external to the processor. On the IQ80960RM/RN platform, XINT4# is connected to the loss of fan
detect and XINT5# is connected to the 16C550 UART.
XINT6#, XINT7# receive interrupts from internal sources. NMI# receives interrupts from internal
sources and from an external source. Since all of these interrupts accept signals from multiple
sources, a status register is provided for each of them to allow service routines to identify the
source of the interrupt. Each of the possible interrupt sources is assigned a bit position in the status
register. The interrupt sources for these lines are shown in Figure 4-3. On the IQ80960RM/RN
platform, the NMI# interrupt is not connected to any external interrupt source and receives
interrupts only from the internal devices on the i960 RM/RN I/O processor. Note that all error
conditions result in an NMI# interrupt.
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i960® RM/RN I/O Processor Overview
Figure 4-3. i960® RM/RN I/O Processor Interrupt Controller Connections
XINT0#
XINT1#
XINT2#
XINT3#
XINT4#
XINT5#
XINT6#
XINT7#
NMI#
S_INTA#/XINT0# m
u
x
S_INTB#/XINT1# m
u
x
S_INTC#/XINT2# m
u
x
S_INTD#/XINT3# m
u
x
XINT4#
XINT5# (UART)
NMI# (N/C)
P_INTA# Output
DMA Channel 0 Error
80960 Outbound Doorbell 0
80960 Outbound Doorbell 1
80960 Outbound Doorbell 2
80960 Outbound Doorbell 3
I2C Bus Interface Unit Interrupt Pending
Messaging Unit Interrupt Pending
i960®RN/RM I/O Processor
Primary ATU Error
Secondary ATU Error
Secondary PCI Bridge Interface Error
Primary PCI Bridge Interface Error
NMI Interrupt
Latch XINT7 Interrupt
Latch
P_INTB# Output
P_INTC# Output
P_INTD# Output
XINT6 Interrupt
Latch
DMA Channel 1 Error
Primary ATU/Start BIST Interrupt Pending
DMA Channel 0 Interrupt Pending
DMA Channel 1 Interrupt Pending
DMA Channel 2 Interrupt Pending
DMA Channel 2 Error
Messaging Unit Error
Memory Controller Unit Error
i960 Core
Processor
(Loss of Fan)
S_INTD# Select bit
S_INTC# Select bit
S_INTB# Select bit
S_INTA# Select bit
Performance Monitor Unit Interrupt Pending
Application Accelerator Interrupt Pending
Bus Interface Unit Error
Application Accelerator Unit Error
IQ80960RM/RN
Evaluation Board Manual 4-5
i960® RM/RN I/O Processor Overview
4.3 CPU Counter/Timers
The i960 RM/RN I/O processor is equipped with two on-chip counter/timers which are clocked
with the i960 RM/RN I/O processor clock signal. The i960 RM/RN I/O processor receives its clock
from the primary PCI interface clock, generated by the motherboard. Most motherboards generate
a 33 MHz clock signal, although the PCI specification requires a clock frequency between 0 and
33 MHz. The timers can be programmed for single-shot or continuous mode, and can generate
interrupts to the processor when the countdown expires.
4.4 Primary PCI Interface
The primary PCI interface on the IQ80960RM/RN platform provides the i960 RM/RN I/O
processor with a connection to the PCI bus on the host system. Only the PCI-to-PCI bridge unit on
the i960 RM/RN I/O processor is directly connected to the primary PCI interface. Devices installed
on the expansion slots are connected to the PCI bus via the bridge unit on the i960 RM/RN I/O
processor. The PCI-to-PCI bridge accepts Type 1 configuration cycles destined for devices on the
secondary bus, and will forward them as Type 0 or Type 1 configuration cycles, or as special
cycles. The IQ80960RN platform interfaces to a 64-bit PCI bus and the IQ80960RM platform
interfaces to a 32-bit PCI bus.
4.5 Secondary PCI Interface
The secondary PCI interface provided by the i960 RM/RN I/O processor is used to connect PCI
cards via the expansion slots to the host system’s PCI bus. PCI cards are attached to the
IQ80960RM/RN platform with a standard PCI connector and may contain up to four separate PCI
devices. The i960 RM/RN I/O processor provides PCI-to-PCI bridge functionality to map installed
PCI devices onto the host PCI bus, and supports transaction forwarding in both directions across
the bridge. PCI devices connected via the expansion slots can therefore act as masters or slaves on
the host system’s PCI bus. Additional PCI-to-PCI bridge devices are supported by the i960 RM/RN
I/O processor on its secondary PCI interface and can be designed into add-on PCI cards. In
addition, the i960 RM/RN I/O processor supports “private” PCI devices on its secondary bus.
Private devices are hidden from initialization code on the host system, and are configured and
accessed directly by the i960 RM/RN I/O processor. These devices are not part of the normal PCI
address space, but they can act as PCI bus masters and transfer data to and from other PCI devices
in the system.
Unless designated as private devices, PCI devices installed on the secondary PCI interface of the
IQ80960RM/RN platform are mapped into the system-wide PCI address space by configuration
software running on the host system. No logical distinction is made at the system level between
devices on the primary PCI bus and devices on secondary buses; all transaction forwarding is
handled transparently by the PCI-to-PCI bridge. Configuration cycles and read and write accesses
from the host are forwarded through the PCI-to-PCI bridge unit of the i960 RM/RN I/O processor.
Master read and write cycles from devices on the secondary PCI bus are also forwarded to the host
bus by the PCI-to-PCI bridge unit.
IxWORKS allows secondary PCI devices to be configured as Public or Private. Public devices are
configured by the PCI host. Private devices are configured by the IxWORKS kernel and the
device-specific HDM.
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4.6 DMA Channels
The i960 RM/RN I/O processor features three independent DMA channels, two of which operate
on the primary PCI interface, whereas the remaining one operates on the secondary PCI interface.
All three of the DMA channels connect to the i960 RM/RN I/O processor’s local bus and can be
used to transfer data from PCI devices to memory on the IQ80960RM/RN platform. Support for
chaining, and scatter/gather is built into all three channels. The DMA can address the entire 264
bytes of address space on the PCI bus and 232 bytes of address space on the internal bus.
4.7 Application Accelerator Unit
The Application Accelerator provides low-latency, high-throughput data transfer capability
between the AA unit and 80960 local memory. It executes data transfers to and from 80960 local
memory and also provides the necessary programming interface. The Application Accelerator
performs the following functions:
•Transfers data (read) from memory controller
•Performs an optional boolean operation (XOR) on read data
•Transfers data (write) to memory controller
The AA unit features:
•128-byte, arranged as 8-byte x 16-deep store queue
•Utilization of the 80960RN/RM processor memory controller interface
•232 addressing range on the 80960 local memory interface
•Hardware support for unaligned data transfers for the internal bus
•Full programmability from the i960 core processor
•Support for automatic data chaining for gathering and scattering of data blocks
Figure 4-4. i960® RM/RN I/O Processor DMA Controller
Primary PCI Bus
Secondary PCI Bus
PCI to PCI Bridge
80960
DMA Channel 0
DMA Channel 1
DMA Channel 2
Local Bus
IQ80960RM/RN
Evaluation Board Manual 4-7
i960® RM/RN I/O Processor Overview
Figure 4-5 shows a simplified connection of the Application Accelerator to the i960 RM/RN I/O
Processor Internal Bus.
4.8 Performance Monitor Unit
The Performance Monitoring features aid in measuring and monitoring various system parameters
that contribute to the overall performance of the processor. The monitoring facility is generically
referred to as PMON – Performance Monitoring. The facility is model specific, not architectural;
its intended use is to gather performance measurements that can be used to retune/refine code for
better system level performance.
The PMON facility provided on the i960 RM/RN I/O processor comprises:
•One dedicated global Time Stamp counter, and
•Fourteen (14) Programmable Event counters
The global time stamp counter is a dedicated, free running 32-bit counter.
The programmable event counters are 32-bits wide. Each counter can be programmed to observe
an event from a defined set of events. An event consists of a set of parameters which define a start
condition and a stop condition. The monitored events are selected by programming an event select
register (ESR).
Figure 4-5. Application Accelerator Unit
64-bit
Data Queue
Application Accelerator Unit
Packing/
Unpacking
Unit
80960
Bus Interface Internal Bus
Boolean Unit
IQ80960RM/RN
Evaluation Board Manual 5-1
MON960 Support for IQ80960RM/RN
5
This chapter discusses a number of additions that have been made to MON960 to support the
IQ80960RM/RN in an optional non-I2O capacity. For complete documentation on the operation of
MON960, see the MON960 Debug Monitor User’s Guide. The IQ80960RM/RN evaluation
platform ships with IxWorks* from Wind River Systems installed in flash firmware. To use
CTOOLS and MON960 instead of IxWorks, you need to download MON960 into the onboard
Flash. See Chapter 2 for more information on updating the onboard Flash. See Chapter 1 for
descriptions of both IxWorks and CTOOLS.
5.1 Secondary PCI Bus Expansion Connectors
The IQ80960RM/RN platform contains four secondary PCI bus expansion connectors to give users
access to the secondary PCI bus of the i960® RM/RN I/O processor. Extensions to MON960
perform secondary PCI bus initialization including the establishment of a secondary PCI bus
address map. Routines compatible with the PCI Local Bus Specification Revision 2.1 allow the
software on the IQ80960RM/RN platform to search for devices on the secondary PCI bus and read
and write the configuration space of those devices.
5.2 MON960 Components
The remaining sections of this chapter assume that MON960 is installed in the onboard Flash,
replacing IxWorks. The IQ80960RM/RN optional MON960 debug monitor consists of four main
components:
These four components together are referred to as MON960.
5.2.1 MON960 Initialization
At initialization, MON960 puts the IQ80960RM/RN platform into a known, functional state that
allows the host processor to perform PCI initialization. Once in this state, the MON960 kernel and
the MON960 extensions can load and execute correctly. Initialization is performed after a RESET
condition. MON960 initialization encompasses all major portions of the i960 RM/RN I/O
processor and IQ80960RM/RN platform including 80960JT core initialization, Memory Controller
initialization, SDRAM initialization, Primary PCI Address Translation Unit (ATU) initialization,
and PCI-to-PCI Bridge Unit initialization.
The IQ80960RM/RN platform is designed to use the Configuration Mode of the i960 RM/RN I/O
processor. Configuration Mode allows the 80960JT core to initialize and control the initialization process
before the PCI host configures the i960 RM/RN I/O processor. By utilizing Configuration Mode, the user
•Initialization firmware •MON960 extensions
•MON960 kernel •Diagnostics/example code
5-2 IQ80960RM/RN
Evaluation Board Manual
MON960 Support for IQ80960RM/RN
is given the ability to initialize the PCI configuration registers to values other than the default power-up
values. Configuration Mode gives the user maximum flexibility to customize the way in which the i960
RM/RN I/O processor and IQ80960RM/RN platform appear to the PCI host configuration software.
5.2.2 80960JT Core Initialization
The 80960JT core begins the initialization process by reading its Initial Memory Image (IMI) from
a fixed address in the boot ROM (FEFF FF30H in the i960 address space). The IMI includes the
Initialization Boot Record (IBR), the Process Control Block (PRCB), and several system data
structures. The IBR provides initial configuration information for the core and integrated
peripherals, pointers to the system data structures and the first instruction to be executed after
processor initialization, and checksum words that the processor uses in its self-test routine. In
addition to the IBR and PRCB, the required data structures are the:
•System Procedure Table
•Control Table
•Interrupt Table
•Fault Table
•User Stack (application dependent)
•Supervisor Stack
•Interrupt Stack
5.2.3 Memory Controller Initialization
Since the i960 RM/RN I/O processor Memory Controller is integral to the design and operation of
the IQ80960RM/RN platform, the operational parameters for Bank 0 and Bank 1 are established
immediately after processor core initialization. Memory Bank 0 is associated with the ROM on the
IQ80960RM/RN platform. Memory Bank 1 is associated with the UART and the LED Control
Register. Parameters such as Bank Base Address, Read Wait States, and Write Wait States must be
established to ensure the proper operation of the IQ80960RM/RN platform. The Memory
Controller is initialized so as to be consistent with the IQ80960RM/RN platform memory map
shown in Figure 4-2.
5.2.4 SDRAM Initialization
SDRAM initialization includes setting operational parameters for the SDRAM controller, and sizing
and clearing the installed SDRAM configuration. To configure the system properly, Presence Detect
data is read from the EEPROM of the SDRAM module, using the 80960RM/RN I2C Bus Interface
Unit. Presence Detect data includes the number and size of SDRAM banks present on the installed
module. On power-up, 64 bytes of Presence Detect data are read and validated. The SDRAM
controller is then configured by setting the base address of SDRAM, the boundary limits for each
SDRAM bank, the refresh cycle interval, and the output buffer drive strength. Once the SDRAM
controller is configured, the SDRAM is cleared in preparation for the C language runtime
environment. The actual SDRAM size is stored for later use (e.g., to establish the size of the
IQ80960RM/RN platform PCI Slave image). The SDRAM controller is initialized to be consistent
with the IQ80960RM/RN platform memory map shown in Figure 4-2.
IQ80960RM/RN
Evaluation Board Manual 5-3
MON960 Support for IQ80960RM/RN
5.2.5 Primary PCI Interface Initialization
The IQ80960RM/RN platform is a multi-function PCI device. On the primary PCI bus, two
functions (from a PCI Configuration Space standpoint) are supported.
•Function 0 is the PCI-to-PCI Bridge of the i960 RM/RN I/O processor, which optionally
provides access capability between the primary PCI bus and the secondary PCI bus.
•Function 1 is the Primary ATU which provides access capability between the primary PCI bus
and the local i960 bus.
The platform can be initialized into one of four modes. Modes 0 and 3 are described below.
When the IQ80960RM/RN is operating in Mode 0, the processor core is held in reset, allowing
register defaults to be used on the Primary PCI interface. This mode is used to program the onboard
Flash with either IxWORKS* or MON960.
When the IQ80960RM/RN platform is operating in Mode 3, the Configuration Cycle Disable bit in
the Extended Bridge Control Register (EBCR) is set after IQ80960RM/RN processor reset. In this
mode, the IQ80960RM/RN platform sends PCI Retries when the PCI host attempts to access the
platform’s Configuration Space. This mode allows the IQ80960RM/RN processor time to initialize
its internal registers. The processor remains in this mode until the Configuration Cycle Disable bit
in the Extended Bridge Control Register (EBCR) is cleared. For this reason, and to prevent PCI
host problems, Primary PCI initialization occurs at the earliest possible opportunity after Memory
and SDRAM controller initialization.
5.2.6 Primary ATU Initialization
Primary ATU (Bridge) initialization includes initialization by the 80960JT core and initialization
by the PCI host processor. Local initialization occurs first and consists mainly of establishing the
operational parameters for access to the local IQ80960RM/RN platform bus. The Primary Inbound
ATU Limit Register (PIALR) is initialized to establish the block size of memory required by the
Primary ATU. The PIALR value is based on the installed SDRAM configuration. The Primary
Inbound ATU Translate Value Register (PIATVR) is initialized to establish the translation value for
PCI-to-Local accesses. The PIATVR value is set to reference the base of local SDRAM. The
Primary Outbound Memory Window Value Register (POMWVR) is initialized to establish the
translation value for Local-to-PCI accesses. The POMWVR value remains at its default value of
“0” to allow the IQ80960RM/RN platform to access the start of the PCI Memory address map,
which is typically occupied by PCI host memory. Likewise, the Primary Outbound I/O Window
Value Register (POIOWVR) remains at its default value of “0” to allow the IQ80960RM/RN
platform to access the start of the PCI I/O address map. PCI Doorbell-related parameters are also
established to allow for communication between the IQ80960RM/RN platform and a PCI bus
master using the doorbell mechanism.
Table 5-1. Initialization Modes
RST_MODE#/
SW1-1 RETRY/
SW1-2 Initialization
Mode Primary PCI Interface i960 Core
Processor
0/ON 0/ON Mode 0 Accepts Transactions Held in Reset
0/ON 1/OFF Mode 1 Retries All Configuration Transactions Held in Reset
1/OFF 0/ON Mode 2 Accepts Transactions Initializes
1/OFF 1/OFF Mode 3 (default) Retries All Configuration Transactions Initializes
5-4 IQ80960RM/RN
Evaluation Board Manual
MON960 Support for IQ80960RM/RN
By default, Primary Outbound Configuration Cycle parameters are not established. The ATU
Configuration Register (ATUCR) is initialized to establish the operational parameters for the
Doorbell Unit and ATU interrupts (both primary and secondary), and to enable the primary and
secondary ATUs. The PCI host is responsible for allocating PCI address space (Memory, Memory
Mapped I/O, and I/O), and assigning the PCI Base addresses for the IQ80960RM/RN platform.
5.2.7 PCI-to-PCI Bridge Initialization
PCI-to-PCI Bridge initialization includes initialization by the 80960JT core and initialization by the
PCI host processor. Local initialization occurs first and consists mainly of establishing the operational
parameters for the secondary PCI interface of the PCI-to-PCI bridge. On the IQ80960RM/RN
platform, the secondary PCI bus is configured to consist of private devices (not visible to PCI host
configuration cycles). To support a private secondary PCI bus, the Secondary IDSEL Select Register
(SISR) is initialized to prevent the secondary PCI address bits [20:16] from being asserted during
conversion of PCI Type 1 configuration cycles on the primary PCI bus to PCI Type 0 configuration
cycles on the secondary PCI bus. Secondary PCI bus masters are prevented from initiating
transactions that will be forwarded to the primary PCI interface. The PCI host is responsible for
assigning and initializing the PCI bus numbers, allocating PCI address space (Memory, Memory
Mapped I/O, and I/O), and assigning the IRQ numbers to valid interrupt routing values.
5.2.8 Secondary ATU Initialization
Secondary ATU (Bridge) initialization consists mainly of establishing the operational parameters
for access between the local IQ80960RM/RN platform bus and the secondary PCI devices. The
Secondary Inbound ATU Base Address Register (SIABAR) is initialized to establish the PCI base
address of IQ80960RM/RN platform local memory from the secondary PCI bus. By convention,
the secondary PCI base address for access to IQ80960RM/RN platform local memory is “0”. The
Secondary Inbound ATU Limit Register (SIALR) is initialized to establish the block size of
memory required by the secondary ATU. The SIALR value is based on the installed SDRAM
configuration. The Secondary Inbound ATU Translate Value Register (SIATVR) is initialized to
establish the translation value for Secondary PCI-to-Local accesses. The SIATVR value is set to
reference the base of local SDRAM. The Secondary Outbound Memory Window Value Register
(SOMWVR) is initialized to establish the translation value for Local-to-Secondary PCI accesses.
The SOMWVR value is left at its default value of “0” to allow the IQ80960RM/RN platform to
access the start of the PCI Memory address map. Likewise, the Secondary Outbound I/O Window
Value Register (SOIOWVR) is left at its default value of “0” to allow the IQ80960RM/RN
platform to access the start of the PCI I/O address map.
On the secondary PCI bus, the IQ80960RM/RN platform assumes the duties of PCI host and, as
such, is required to configure the devices of the secondary PCI bus. Secondary Outbound
Configuration Cycle parameters are established during secondary PCI bus configuration.
Secondary PCI bus configuration is accomplished via MON960 Extension routines.
IQ80960RM/RN
Evaluation Board Manual 5-5
MON960 Support for IQ80960RM/RN
5.3 MON960 Kernel
The MON960 Kernel (monitor) provides the IQ80960RM/RN user with a software platform on
which application software can be developed and run. The monitor provides several features available
to the IQ80960RM/RN user to speed application development. Among the available features are:
•Communication with a terminal or terminal emulation package on a host computer through a
serial cable with automatic baud rate detection
•Communication with a software debugger such as GDB960 (available from Intel) using the
Host Debugger Interface (HDI) software interface
•Communication with the host computer via the primary PCI bus
•Downloads of ELF object files via the primary PCI bus or via the serial console port at rates up
to 115,200 baud
•Downloads of ELF object files via the primary PCI bus
•On-board erasure and programming of Intel 28F016S5 Flash ROM
•Memory display and modification capability
•Breakpoint and single-step capability to support debugging of user code
•Disassembly of i960 processor instructions
5.4 MON960 Extensions
The monitor has been extended to include the secondary PCI bus initialization and also the BIOS
routines which are contained in the PCI BIOS Specification Revision 2.1.
5.4.1 Secondary PCI Initialization
MON960 extensions are responsible for initializing the devices on the secondary PCI bus of the
IQ80960RM/RN platform. Secondary PCI initialization involves allocating address spaces
(Memory, Memory Mapped I/O, and I/O), assigning PCI base addresses, assigning IRQ values, and
enabling PCI mastership. MON960 does not support devices containing PCI-to-PCI bridges and
hierarchical buses.
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MON960 Support for IQ80960RM/RN
5.4.2 PCI BIOS Routines
MON960 includes PCI BIOS routines to aid application software initialization of the secondary
PCI bus. The supported BIOS functions are described in the subsections that follow.
sysPCIBIOSPresent
sysFindPCIDevice
sysFINDPCIClassCode
sysGenerateSpecialCycle
sysReadConfigByte
sysReadConfigWord
sysReadConfigDword
sysWriteConfigByte
sysWriteConfigWord
sysWriteConfigDword
sysGetIrqRoutingOptions
sysSetPCIIrq
These functions preserve, as closely as possible, the parameters and return values described in the
PCI Local Bus Specification Revision 2.1. Functions that return multiple values do so by filling in
the fields of a structure passed by the calling routine.
You can access these functions via a calls instruction. The system call indices are defined in the
MON960 source file PCI_BIOS.H. The function prototypes are defined in the IQRP_ASM.H
file.
5.4.2.1 sysPCIBIOSPresent
This function allows the caller to determine whether the PCI BIOS interface function set is present,
and the current interface version level. It also provides information about the hardware mechanism
used for accessing configuration space and whether or not the hardware supports generation of PCI
Special Cycles.
Calling convention:
int sysPCIBIOSPresent (
PCI_BIOS_INFO *info
);
Return values:
This function always returns SUCCESSFUL.
IQ80960RM/RN
Evaluation Board Manual 5-7
MON960 Support for IQ80960RM/RN
5.4.2.2 sysFindPCIDevice
This function returns the location of PCI devices that have a specific Device ID and Vendor ID.
Given a Vendor ID, a Device ID, and an Index, the function returns the Bus Number, Device
Number, and Function Number of the Nth Device/Function whose Vendor ID and Device ID match
the input parameters.
Calling software can find all devices having the same Vendor ID and Device ID by making
successive calls to this function starting with the index set to “0”, and incrementing the index until
the function returns DEVICE_NOT_FOUND. A return value of BAD_VENDOR_ID indicates that
the Vendor ID value passed had a value of all “1”s.
Calling convention:
int sysFindPCIDevice (
int device_id,
int vendor_id,
int index
);
Return values:
This function returns SUCCESSFUL if the indicated device is located, DEVICE_NOT_FOUND if
the indicated device cannot be located, or BAD_VENDOR_ID if the vendor_id value is illegal.
5.4.2.3 sysFindPCIClassCode
This function returns the location of PCI devices that have a specific Class Code. Given a Class
Code and an Index, the function returns the Bus Number, Device Number, and Function Number of
the Nth Device/Function whose Class Code matches the input parameters.
Calling software can find all devices having the same Class Code by making successive calls to
this function starting with the index set to “0”, and incrementing the index until the function returns
DEVICE_NOT_FOUND.
Calling convention:
int sysFindPCIClassCode (
int class_code,
int index
);
Return values:
This function returns SUCCESSFUL when the indicated device is located, or
DEVICE_NOT_FOUND when the indicated device cannot be located.
5-8 IQ80960RM/RN
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MON960 Support for IQ80960RM/RN
5.4.2.4 sysGenerateSpecialCycle
This function allows for generation of PCI Special Cycles. The generated special cycle is broadcast
on a specific PCI Bus in the system.
PCI Special Cycles are not supported on the IQ80960RM/RN platform secondary PCI bus.
Calling convention:
int sysGenerateSpecialCycle (
int bus_number,
int special_cycle_data
);
Return values:
Since PCI Special Cycles are not supported by the IQ80960RM/RN platform, this function always
returns FUNC_NOT_SUPPORTED.
5.4.2.5 sysReadConfigByte
This function allows the caller to read individual bytes from the configuration space of a specific
device.
Calling convention:
int sysReadConfigByte (
int bus_number,
int device_number,
int function_number,
int register_number, /* 0,1,2,...,255 */
UINT8 *data
);
Return values:
This function returns SUCCESSFUL when the indicated byte was read correctly, or ERROR when
there is a problem with the parameters.
IQ80960RM/RN
Evaluation Board Manual 5-9
MON960 Support for IQ80960RM/RN
5.4.2.6 sysReadConfigWord
This function allows the caller to read individual shorts (16 bits) from the configuration space of a
specific device. The Register Number parameter must be a multiple of two (i.e., bit 0 must be set to “0”).
Calling convention:
int sysReadConfigWord (
int bus_number,
int device_number,
int function_number,
int register_number, /* 0,2,4,...,254 */
UINT16 *data
);
Return values:
This function returns SUCCESSFUL when the indicated word was read correctly, or ERROR when
there is a problem with the parameters.
5.4.2.7 sysReadConfigDword
This function allows the caller to read individual longs (32 bits) from the configuration space of a
specific device. The Register Number parameter must be a multiple of four (i.e., bits 0 and 1 must
be set to “0”).
Calling convention:
int sysReadConfigDword (
int bus_number,
int device_number,
int function_number,
int register_number, /* 0,4,8,...,252 */
UINT32 *data
);
Return values:
This function returns SUCCESSFUL when the indicated long was read correctly, or ERROR when
there is a problem with the parameters.
5-10 IQ80960RM/RN
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MON960 Support for IQ80960RM/RN
5.4.2.8 sysWriteConfigByte
This function allows the caller to write individual bytes to the configuration space of a specific device.
Calling convention:
int sysWriteConfigByte (
int bus_number,
int device_number,
int function_number,
int register_number, /* 0,1,2,...,255 */
UINT8 *data
);
Return values:
This function returns SUCCESSFUL when the indicated byte was written correctly, or ERROR
when there is a problem with the parameters.
5.4.2.9 sysWriteConfigWord
This function allows the caller to write individual shorts (16 bits) to the configuration space of a specific
device. The Register Number parameter must be a multiple of two (i.e., bit 0 must be set to “0”).
Calling convention:
int sysWriteConfigWord (
int bus_number,
int device_number,
int function_number,
int register_number, /* 0,2,4,...,254 */
UINT16 *data
);
Return values:
This function returns SUCCESSFUL when the indicated word was written correctly, or ERROR
when there is a problem with the parameters.
IQ80960RM/RN
Evaluation Board Manual 5-11
MON960 Support for IQ80960RM/RN
5.4.2.10 sysWriteConfigDword
This function allows the caller to write individual longs (32 bits) to the configuration space of a
specific device. The Register Number parameter must be a multiple of four (i.e., bits 0 and 1 must
be set to “0”).
Calling convention:
int sysWriteConfigDword (
int bus_number,
int device_number,
int function_number,
int register_number, /* 0,4,8,...,252 */
UINT32 *data
);
Return values:
This function returns SUCCESSFUL when the indicated long was written correctly, or ERROR
when there is a problem with the parameters.
5.4.2.11 sysGetIrqRoutingOptions
The PCI Interrupt routing fabric on the IQ80960RM/RN platform is not reconfigurable (fixed
mapping relationships); therefore, this function is not supported.
Calling convention:
int sysGetIrqRoutingOptions (
PCI_IRQ_ROUTING_TABLE *table
);
Return values:
This function always returns FUNC_NOT_SUPPORTED.
5-12 IQ80960RM/RN
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MON960 Support for IQ80960RM/RN
5.4.2.12 sysSetPCIIrq
The PCI Interrupt routing fabric on the IQ80960RM/RN platform is not reconfigurable (fixed
mapping relationships); therefore, this function is not supported.
Calling convention:
int sysSetPCIIrq (
int int_pin,
int irq_num,
int bus_dev
);
Return values:
This function always returns FUNC_NOT_SUPPORTED.
5.4.3 Additional MON960 Commands
The following commands have been added to the UI interface of MON960 to support the
IQ80960RM/RN platform.
5.4.3.1 print_pci Utility
A print_pci command to MON960 is accessed through the MON960 command prompt. This command
displays the contents of the PCI configuration space on a selected adapter on the secondary PCI interface or
on the i960 RM/RN I/O processor itself. For more information on the meaning of the fields in PCI
configuration space, refer to the PCI Local Bus Specification Revision 2.1. The syntax of this command is:
pp <bus number> <device number> <function number>
5.5 Diagnostics / Example Code
IQ80960RM/RN platform diagnostic routines serve a twofold purpose: to verify proper hardware operation
and to provide example code for users who need similar functions in their applications. Diagnostic routines
fall into two categories: board level diagnostics and PCI expansion module diagnostics.
5.5.1 Board Level Diagnostics
Board level diagnostics exercise all basic areas of the IQ80960RM/RN platform. Diagnostic routines
include SDRAM tests, UART tests, LED tests, internal timer tests, I2C bus tests, and primary PCI bus tests.
Primary PCI bus tests exercise the primary ATU, the PCI Doorbell unit, and the PCI DMA controller.
Interrupts from both local and PCI sources are generated and handled. The PCI bus tests require an external
test suite running on a PC to verify complete functionality of the IQ80960RM/RN platform.
5.5.2 Secondary PCI Diagnostics
Secondary PCI diagnostics exercise the secondary PCI bus, thereby confirming hardware
functionality, as well as illustrating the use of the PCI BIOS routines present in MON960.
IQ80960RM/RN
Evaluation Board Manual A-1
Bill of Materials A
This appendix identifies all components on the IQ80960RN Evaluation Platform (Table A-1), and
the IQ80960RM Evaluation Platform (Table A-2).
Table A-1. IQ80960RN Bill of Materials (Sheet 1 of 4)
Item Qty Location Part Description Manufacturer Manufacturer Part #
1 1 U13 IC/SM 74ALS32 SOIC-14 National
Semiconductor DM74ALS32M
2 1 U6 IC/SM 74ALS04 SOIC National
Semiconductor DM74ALS04BM
3 1 U3 IC/SM 74ABT273 SOIC Texas
Instruments SN74ABT273DW
4 2 U1,U2 IC/SM 74ABT573 SOIC Texas
Instruments SN74ABT573DW
5 1 U16 IC/SM 74ALS08 SOIC National
Semiconductor DM74ALS08M
6 1 U5 IC / SM 1488A SOIC National
Semiconductor DS1488M
7 1 U7 IC / SM 1489A SOIC National
Semiconductor DS1489AM
8 1 Q1 IC/SM Si9430DY SOIC-8 Siliconix Si9430DY
9 1 U9 IC/SM LVCMOS Fanout Buffr SSOP Motorola MPC9140
10 1 U10 IC/SM LM339 SOIC-14 National
Semiconductor LM339M
11 1 U8 IC/SM MAX1651CSA SOIC-8 Maxim MAX1651CSA
12 1 U14 IC/SM MAX712CSE SOIC-16 Maxim MAX712CSE
13 1 U17 IC/SM MAX767CAP SOIC Maxim MAX767CAP
14 1 U15 PROCESSOR (from Intel) 80960RN Intel
15 1 U12 VLSI I/O UART 16C550 PLCC Texas
Instruments TL16C550AFN
16 1 C65 CAP SM, 0.47 µF (1206) Philips Philips 12062F474Z9BB0
17 15
C2, C3,
C10, C11,
C18, C19,
C26, C27,
C55, C58,
C61, C68,
C77, C83,
C96
CAP SM, 0.01 µF (0805) Kemet C0805C103K5RAC
A-2 IQ80960RM/RN
Evaluation Board Manual
Bill of Materials
18 79
C1, C4, C5,
C6, C7, C8,
C9, C12,
C13, C14,
C15, C16,
C17, C20,
C21, C22,
C23, C24,
C25, C28,
C29, C30,
C31, C32,
C33, C34,
C35, C36,
C37, C38,
C39, C40,
C41, C42,
C43, C44,
C45, C46,
C48, C49,
C50, C51,
C53, C59,
C62, C66,
C67, C69,
C70, C71,
C73, C79,
C80, C81,
C85, C86,
C87, C94,
C95, C97,
C98, C99,
C100, C101,
C102, C103,
C104, C105,
C106, C107,
C108, C109,
C111, C112,
C113, C115,
C116, C114,
C117
CAP SM, 0.1 µF (0805) Philips 08052R104K8BB2
19 1 C110 CAP SM, 18 pF (0805) Kemet C0805C180J5GAC
20 2 R27, R28 R/SM 1/10 W 5% 1 ohm (0805) Dale CRCW0805100JT
21 1 R60 R/SM 1/10 W 5% 10 ohm (0805) Dale CRCW08051000JT
22 1 R25 R/SM 1/10 W 5% 1 Kohm (0805) Dale CRCW08051001FRT
23 4 R35, R39,
R58, R59 R/SM 1/10 W 5% 10 Kohm (0805) Dale CRCW08051002FRT
24 2 R24, R32 R/SM 1/10 W 5% 100 Kohm (0805) Dale CRCW08051003FRT
25 1 R20 R/SM 1/10 W 1% 150 ohm (0805) Dale CRCW08051500FRT
26 3 R14, R41,
R42 R/SM 1/10 W 5% 1.5 Kohm (0805) Dale CRCW0805152JT
27 1 R18 R/SM 1/10 W 5% 1.6 Kohm (0805) Dale CRCW0805162JT
28 2 R50, R51 R/SM 1/10 W 5% 22 ohm (0805) Dale CRCW0805220JT
29 1 R34 R/SM 1/10 W 5% 22 Kohm (0805) Dale CRCW0805223JT
30 1 R37 R/SM 1/10 W 5% 24 ohm (0805) Dale CRCW0805240JT
31 1 R47 R/SM 1/10 W 5% 2.4 Kohm (0805) Dale CRCW0805242JT
Table A-1. IQ80960RN Bill of Materials (Sheet 2 of 4)
Item Qty Location Part Description Manufacturer Manufacturer Part #
IQ80960RM/RN
Evaluation Board Manual A-3
Bill of Materials
32 2 R2, R57 R/SM 1/10 W 5% 2.7 Kohm (0805) Dale CRCW0805272JT
33 1 R19 R/SM 1/10 W 5% 330 ohm (0805) Dale CRCW0805331JT
34 1 R29 R/SM 1/10 W 5% 36 ohm (0805) Dale CRCW0805360JT
35 1 R17 R/SM 1/10 W 5% 470 ohm (0805) Dale CRCW 0805 471JT
36 2 R48, R49 R/SM 1/10 W 1% 4.7 Kohm (0805) Dale CRCW08054701FRT
37 1 R53 R/SM 1/10 W 5% 47 Kohm (0805) Dale CRCW0805473JT
38 1 R26 R/SM 1/10 W 5% 68 Kohm (0805) Dale CRCW0805683JT
39 4 R30, R43,
R54, R56 R/SM 1/8 W 5% 10 ohm chip 1206 Dale CRCW1206100FT
40 5 J8, J9, J10,
J11, J12 CONN SM/TH Mictor 43P Recptcl AMP 767054-1
41 4 J1, J2, J3,
J4 CONN PCI 64BIT 5 V/PCB ThruHole AMP 145166-4
42 1 J5 CONN DIMM 168P/RAng/Socket/TH Molex 73790-0059
43 1 J7 CONN TJ6 PCB 6/6 LP thru hole KYCON GM-N-66
44 1 J13 CONN/FAN ASSY/Socket/ThruHole AMP 173981-03
45 1 J6 CONN Hdr 16 pin/w shell, pcb AMP 103308-3
46 4 Z1, Z2, Z3,
Z4 Jumper JUMP2X1 Molex 22-54-1402
47 1 L1 Inductor/SM 47µH 20% Coilcraft D03340P-473
48 1 L2 Inductor/SM 3.3 µH 20% Coilcraft D03316P-332
49 1 S1 Switch/SM DIP4 Mors# DHS-4S Mors DHS-4S
50 1 U4 OSC 1.8432 MHz 1/2 - Thru hole Kyocera KH0HC1CSE 1.843
51 1 U18 Clock Chip CY7B9910-7SC Cypress CY7B9910-7SC
52 1 CR5 LED Green Hewlett
Packard HLMP-3507$010
53 1 CR3 LED-Red Hewlett
Packard HLMP3301$010
54 1 CR4 LED Green LP Hewlett
Packard HLMP4740#010
55 2 CR1, CR2 LED-Red-Small Group Dialight 555-4001
56 2 Q2, Q3 Transistor/SM N-Channel Harris RFD16N05LSM
57 1 Q4 Transistor 2N6109 (Thru Hole) Motorola 2N6109
58 1 U19 SOCKET PLCC20 LP Surface Mount AMP 822269-1
60 8
BT1, BT2,
BT3, BT4,
BT5, BT6,
BT7, BT8
Battery Clips/PC/Snap-In/AA Keystone #92
61 1 U19 PALLV16V8Z-20JI AMD PALLV16V8Z-20JI
62 1 U11 MEM Flash E28F016S5-090 TSOP Intel E28F016S5-090
63 8
BT1, BT2,
BT3, BT4,
BT5, BT6,
BT7, BT8
Battery AA NiCd @ 600 mA/Hour SAFT NIC-AA-600-SAFT
Table A-1. IQ80960RN Bill of Materials (Sheet 3 of 4)
Item Qty Location Part Description Manufacturer Manufacturer Part #
A-4 IQ80960RM/RN
Evaluation Board Manual
Bill of Materials
64 1 U15 HeatSink/Fan Assy 80960RM/RN Panasonic UDQFNBEOIF
65 1 C84 CAP SM, 0.22 µF (1206) Philips 12062E224M9BB2
66 3 C60, C75,
C78 CAP TANT SM 220 µF, 10 V (7343) AVX TPSE227K010R010
67 4 C89, C90,
C91, C93 CAP TANT SM 47 µF, 16 V (7343) AVX TPSD476K016R015
68 1 C63 CAP TANT SM 33 µF, 10 V (7343) Sprague 293D336X9016D2T
69 4 C57, C76,
C88, C92 CAP TANT SM 4.7 µF, 35 V (7343) Sprague 293D475X9035D2T
70 1 C47 CAP TANT SM 22 µF, 20 V (7343) Sprague 293D226X9020D2T
71 1 C74 CAP TANT SM 1 µF, 16 V (3216) Sprague 293D105X0016A2T
72 2 C52, C54 CAP TANT SM 10 µF, 25/35 V Sprague 293D1060025D2T
73 1 C56 CAP TANT SM 100 µF 10 V (7343) AVX TPSD107K010R0100
74 1 C64 CAP TANT SM 330 µF 6.3 V (7343 AVX TPSE337K063R0100
75 1 C82 CAP SM, 0.047 µF (0805) Kemet C0805C473K5RAC
76 1 R46 Res/SM 1 W 1% 0.012 ohm (2512) Dale WSL-2512-R012
77 1 R21 Res/SM 1 W 1% 0.05 ohm (2512) Dale WSL-2512-R050
78 1 R52 Resistor/SM 1/2 W 5% 100 ohm Beckmen BCR 1/2 101 JT
79 16
R1, R3, R4,
R5, R6, R7,
R8, R9,
R10, R11,
R12, R33,
R36, R38,
R44, R45,
Resistor Pk SM RNC4R8P 2.7 Kohm CTS 742083272JTR
80 2 R40, R55 Resistor Pk SM RNC4R8P 22 ohm CTS 742083220JTR
81 2 R15, R16 Resistor Pk SM RNC4R8P 470 ohm CTS 742083471JTR
82 1 R13 Resistor Pk SM RNC4R8P 1.5 Kohm CTS 742083152JTR
83 2 R22, R23 Resistor Pk SM RNC4R8P 30 ohm CTS 742083300JTR
84 1 CR9 Diode CMPSH3 Surface Mount Central
Semiconductor CMPSH3
85 2 CR6, CR7 Diode SM / MBRS340T3 Motorola MBRS340T3
86 1 CR8 Diode/SM 1N4001 (CMR1-02) Central
Semiconductor CMR1-02
87 1 J5 SDRAM, DIMM, ECC, 2Mx72, 16 MB Unigen UG52S7408GSG
Table A-1. IQ80960RN Bill of Materials (Sheet 4 of 4)
Item Qty Location Part Description Manufacturer Manufacturer Part #
IQ80960RM/RN
Evaluation Board Manual A-5
Bill of Materials
Table A-2. IQ80960RM Bill of Materials (Sheet 1 of 4)
Item Qty Location Part Description Manufacturer Manufacturer Part #
1 1 U13 IC/SM 74ALS32 SOIC-14 National
Semiconductor DM74ALS32M
2 1 U6 IC/SM 74ALS04 SOIC National
Semiconductor DM74ALS04BM
3 1 U3 IC/SM 74ABT273 SOIC Texas
Instruments SN74ABT273DW
4 2 U1, U2 IC/SM 74ABT573 SOIC Texas
Instruments SN74ABT573DW
5 1 U16 IC/SM 74ALS08 SOIC National
Semiconductor DM74ALS08M
6 1 U5 IC / SM 1488A SOIC National
Semiconductor DS1488M
7 1 U7 IC / SM 1489A SOIC National
Semiconductor DS1489AM
8 1 Q1 IC/SM Si9430DY SOIC-8 Siliconix Si9430DY
9 1 U9 IC/SM LVCMOS Fanout Buffr SSOP Motorola MPC9140
10 1 U10 IC/SM LM339 SOIC-14 National
Semiconductor LM339M
11 1 U8 IC/SM MAX1651CSA SOIC-8 Maxim MAX1651CSA
12 1 U14 IC/SM MAX712CSE SOIC-16 Maxim MAX712CSE
13 1 U17 IC/SM MAX767CAP SOIC Maxim MAX767CAP
14 1 U15 PROCESSOR (frm Intel) i960RM Intel
15 1 U12 VLSI I/O UART 16C550 PLCC Texas
Instruments TL16C550AFN
16 1 C65 CAP SM, 0.47 µF (1206) Philips Philips 12062F474Z9BB0
17 15
C2, C3,
C10, C11,
C18, C19,
C26, C27,
C55, C58,
C61, C68,
C77, C83,
C96
CAP SM, 0.01 µF (0805) Kemet C0805C103K5RAC
A-6 IQ80960RM/RN
Evaluation Board Manual
Bill of Materials
18 79
C1, C4, C5,
C6, C7, C8,
C9, C12,
C13, C14,
C15, C16,
C17, C20,
C21, C22,
C23, C24,
C25, C28,
C29, C30,
C31, C32,
C33, C34,
C35, C36,
C37, C38,
C39, C40,
C41, C42,
C43, C44,
C45, C46,
C48, C49,
C50, C51,
C53, C59,
C62, C66,
C67, C69,
C70, C71,
C73, C79,
C80, C81,
C85, C86,
C87, C94,
C95, C97,
C98, C99,
C100, C101,
C102, C103,
C104, C105,
C106, C107,
C108, C109,
C111, C112,
C113, C114,
C115, C116,
C117
CAP SM, 0.1 µF (0805) Philips 08052R104K8BB2
19 1 C110 CAP SM, 18 pF(0805) Kemet C0805C180J5GAC
20 2 R27, R28 R/SM 1/10 W 5% 1 ohm (0805) Dale CRCW0805100JT
21 1 R60 R/SM 1/10 W 5% 10 ohm (0805) Dale CRCW08051000JT
22 1 R25 R/SM 1/10 W 5% 1 Kohm (0805) Dale CRCW08051001FRT
23 12
R5, R6, R7
R8, R9,
R10, R11,
R12, R35,
R39, R58,
R59
R/SM 1/10 W 5% 10 Kohm (0805) Dale CRCW08051002FRT
24 2 R24, R32 R/SM 1/10 W 5% 100 Kohm (0805) Dale CRCW08051003FRT
25 1 R20 R/SM 1/10 W 1% 150 ohm (0805) Dale CRCW08051500FRT
26 3 R14, R41,
R42 R/SM 1/10 W 5% 1.5 Kohm (0805) Dale CRCW0805152JT
27 1 R18 R/SM 1/10 W 5% 1.6 Kohm (0805) Dale CRCW0805162JT
28 2 R50, R51 R/SM 1/10 W 5% 22 ohm (0805) Dale CRCW0805220JT
Table A-2. IQ80960RM Bill of Materials (Sheet 2 of 4)
Item Qty Location Part Description Manufacturer Manufacturer Part #
IQ80960RM/RN
Evaluation Board Manual A-7
Bill of Materials
29 1 R34 R/SM 1/10 W 5% 22 Kohm (0805) Dale CRCW0805223JT
30 1 R37 R/SM 1/10 W 5% 24 ohm (0805) Dale CRCW0805240JT
31 1 R47 R/SM 1/10 W 5% 2.4 Kohm (0805) Dale CRCW0805242JT
32 1 R57 R/SM 1/10 W 5% 2.7 Kohm (0805) Dale CRCW0805272JT
33 1 R19 R/SM 1/10 W 5% 330 ohm (0805) Dale CRCW0805331JT
34 1 R29 R/SM 1/10 W 5% 36 ohm (0805) Dale CRCW0805360JT
35 1 R17 R/SM 1/10 W 5% 470 ohm (0805) Dale CRCW 0805 471JT
36 2 R48, R49 R/SM 1/10 W 1% 4.7 Kohm (0805) Dale CRCW08054701FRT
37 1 R53 R/SM 1/10 W 5% 47 Kohm (0805) Dale CRCW0805473JT
38 1 R26 R/SM 1/10 W 5% 68 Kohm (0805) Dale CRCW0805683JT
39 4 R30, R43,
R54, R56 R/SM 1/8 W 5% 10 ohm chip 1206 Dale CRCW1206100FT
40 5 J8, J9, J10,
J11, J12 CONN SM/TH Mictor 43P Recptcl AMP 767054-1
41 4 J1, J2, J3,
J4 CONN PCI Slot 5V/PCB ThruHole AMP 145154-4
42 1 J5 CONN DIMM 168P/RAng/Socket/TH Molex 73790-0059
43 1 J7 CONN TJ6 PCB 6/6 LP thru hole KYCON GM-N-66
44 1 J13 CONN/FAN ASSY/Socket/ThruHole AMP 173981-03
45 1 J6 CONN Hdr 16 pin/w shell, pcb AMP 103308-3
46 4 Z1, Z2, Z3,
Z4 Jumper JUMP2X1 Molex 22-54-1402
47 1 L1 Inductor/SM 47 µH 20% Coilcraft D03340P-473
48 1 L2 Inductor/SM 3.3 µH 20% Coilcraft D03316P-332
49 1 S1 Switch/SM DIP4 Mors# DHS-4S Mors DHS-4S
50 1 U4 OSC 1.8432 MHz 1/2 - Thru hole Kyocera KH0HC1CSE 1.843
51 1 U18 Clock Chip CY7B9910-7SC Cypress CY7B9910-7SC
52 1 CR5 LED Green Hewlett
Packard HLMP-3507$010
53 1 CR3 LED-Red Hewlett
Packard HLMP3301$010
54 1 CR4 LED Green LP Hewlett
Packard HLMP4740#010
55 2 CR1, CR2 LED-Red-Small Group Dialight 555-4001
56 2 Q2, Q3 Transistor/SM N-Channel Harris RFD16N05LSM
57 1 Q4 Transistor 2N6109 (Thru Hole) Motorola 2N6109
58 1 U19 SOCKET PLCC20 LP Surface Mount AMP 822269-1
60 1 U11 SOCKET / SM / TSOP / 40 pin Meritec 980020-40-02
61 8
BT1, BT2,
BT3, BT4,
BT5, BT6,
BT7, BT8
Battery Clips/PC/Snap-In/AA Keystone #92
Table A-2. IQ80960RM Bill of Materials (Sheet 3 of 4)
Item Qty Location Part Description Manufacturer Manufacturer Part #
A-8 IQ80960RM/RN
Evaluation Board Manual
Bill of Materials
62 1 U19 PALLV16V8Z-20JI AMD PALLV16V8Z-20JI
63 1 U11 MEM Flash E28F016S5-090 TSOP Intel E28F016S5-090
64 8
BT1, BT2,
BT3, BT4,
BT5, BT6,
BT7, BT8
Battery AA NiCd @ 600 mA/Hour SAFT NIC-AA-600-SAFT
65 1 U15 HeatSink/Fan Assy 80960RN/RM Panasonic UDQFNBEOIF
66 3 C84 CAP SM, 0.22 µF (1206) Philips 12062E224M9BB2
67 3 C60, C75,
C78 CAP TANT SM 220 µF, 10 V (7343) AVX TPSE227K010R010
68 4 C89, C90,
C91, C93 CAP TANT SM 47 µF, 16 V (7343) AVX TPSD476K016R015
69 1 C63 CAP TANT SM 33 µF, 10 V (7343) Sprague 293D336X9016D2T
70 4 C57, C76,
C88, C92 CAP TANT SM 4.7 µF, 35 V (7343) Sprague 293D475X9035D2T
71 1 C47 CAP TANT SM 22 µF, 20 V (7343) Sprague 293D226X9020D2T
72 1 C74 CAP TANT SM 1 µF, 16 V (3216) Sprague 293D105X0016A2T
73 2 C52, C54 CAP TANT SM 10 µF, 25/35 V Sprague 293D1060025D2T
74 1 C56 CAP TANT SM 100 µF 10 V (7343) AVX TPSD107K010R0100
75 1 C64 CAP TANT SM 330 µF 6.3 V (7343) AVX TPSE337K063R0100
76 1 C82 CAP SM, 0.047 µF (0805) Kemet C0805C473K5RAC
77 1 R46 Res/SM 1 W 1% 0.012 ohm (2512) Dale WSL-2512-R012
78 1 R21 Res/SM 1 W 1% 0.05 ohm (2512) Dale WSL-2512-R050
79 1 R52 Resistor/SM 1/2 W 5% 100 ohm Beckmen BCR 1/2 101 JT
80 7
R1, R31,
R33, R36,
R38, R44,
R45
Resistor Pk SM RNC4R8P 2.7 Kohm CTS 742083272JTR
81 2 R40, R55 Resistor Pk SM RNC4R8P 22 ohm CTS 742083220JTR
82 2 R15, R16 Resistor Pk SM RNC4R8P 470 ohm CTS 742083471JTR
83 1 R13 Resistor Pk SM RNC4R8P 1.5 Kohm CTS 742083152JTR
84 2 R22, R23 Resistor Pk SM RNC4R8P 30 ohm CTS 742083300JTR
85 1 CR9 Diode CMPSH3 Surface Mount Central
Semiconductor CMPSH3
86 2 CR6, CR7 Diode SM / MBRS340T3 Motorola MBRS340T3
87 1 CR8 Diode/SM 1N4001 (CMR1-02) Central
Semiconductor CMR1-02
88 1 J5 SDRAM, DIMM, ECC, 2Mx72, 16 MB Unigen UG52S7408GSG
Table A-2. IQ80960RM Bill of Materials (Sheet 4 of 4)
Item Qty Location Part Description Manufacturer Manufacturer Part #
IQ80960RM/RN
Evaluation Board Manual B-1
Schematics B
This appendix includes schematics for the IQ80960RN (Table B-1) and IQ80960RM (Table B-2).
Table B-1. IQ80960RN Schematics List
Page Schematic Title
B-2 Decoupling and 3.3V Power
B-3 Primary PCI Interface
B-4 Memory Controller
B-5 Flash ROM, UART, & LEDs
B-6 Logic Analyzer I/F
B-7 SDRAM 168-Pin DIMM
B-8 Secondary PCI/960 Core
B-9 Secondary PCI Bus 1/2
B-10 Secondary PCI Bus 3/4
B-11 SPCI Pull-ups
B-12 Battery/Monitor
12345678
12345678
A
B
C
D
A
B
C
D
TP1
1
R46
0.012
1W 1%
1 2
3
4
5
6
7
L2
3.3uH
COIL-SMT2
1 2
CR6
MBRS340T3
1 2
Q2
RFD16N05L
2
1
3
Q3
RFD16N05L
2
1
3
C60
220uF
CAPT7343
21
C75
220uF
CAPT7343
21
C78
220uF
CAPT7343
21
C93
47uF
CAPT7343
2 1 C90
47uF
CAPT7343
2 1 C91
47uF
CAPT7343
2 1
C67
0.1uF
CAP0805
2 1
C79
0.1uF
CAP0805
2 1
C85
0.1uF
CAP0805
2 1
C40
0.1uF
CAP0805
2 1
C39
0.1uF
CAP0805
2 1
C38
0.1uF
CAP0805
2 1
C37
0.1uF
CAP0805
2 1
C36
0.1uF
CAP0805
2 1
C35
0.1uF
CAP0805
2 1
C34
0.1uF
CAP0805
2 1
C33
0.1uF
CAP0805
2 1
C6
0.1uF
CAP0805
2 1
C5
0.1uF
CAP0805
2 1
C4
0.1uF
CAP0805
2 1
C14
0.1uF
CAP0805
2 1
C13
0.1uF
CAP0805
2 1
C12
0.1uF
CAP0805
2 1
C22
0.1uF
CAP0805
2 1
C21
0.1uF
CAP0805
2 1
C1
0.1uF
CAP0805
2 1
C7
0.1uF
CAP0805
2 1
C8
0.1uF
CAP0805
2 1
C9
0.1uF
CAP0805
2 1
C15
0.1uF
CAP0805
2 1
C16
0.1uF
CAP0805
2 1
C17
0.1uF
CAP0805
2 1
C23
0.1uF
CAP0805
2 1
C24
0.1uF
CAP0805
2 1
C25
0.1uF
CAP0805
2 1
C31
0.1uF
CAP0805
2 1
C32
0.1uF
CAP0805
2 1
C20
0.1uF
CAP0805
2 1
C30
0.1uF
CAP0805
2 1
C29
0.1uF
CAP0805
2 1
C28
0.1uF
CAP0805
2 1
C116
0.1uF
CAP0805
2 1
C117
0.1uF
CAP0805
2 1
C111
0.1uF
CAP0805
2 1
C113
0.1uF
CAP0805
2 1
C105
0.1uF
CAP0805
2 1
C109
0.1uF
CAP0805
2 1
C106
0.1uF
CAP0805
2 1
C108
0.1uF
CAP0805
2 1
C114
0.1uF
CAP0805
2 1
C115
0.1uF
CAP0805
2 1
C112
0.1uF
CAP0805
2 1
C107
0.1uF
CAP0805
2 1
C45
0.1uF
CAP0805
2 1
C59
0.1uF
CAP0805
2 1
C46
0.1uF
CAP0805
2 1
C70
0.1uF
CAP0805
2 1
C99
0.1uF
CAP0805
2 1
C103
0.1uF
CAP0805
2 1
C81
0.1uF
CAP0805
2 1
C72
0.1uF
CAP0805
2 1
C80
0.1uF
CAP0805
2 1
C69
0.1uF
CAP0805
2 1
C87
0.1uF
CAP0805
2 1
C73
0.1uF
CAP0805
2 1
C49
0.1uF
CAP0805
2 1
C62
0.1uF
CAP0805
2 1
C66
0.1uF
CAP0805
2 1
C42
0.1uF
CAP0805
2 1
C41
0.1uF
CAP0805
2 1
C71
0.1uF
CAP0805
2 1
C43
0.1uF
CAP0805
2 1
C48
0.1uF
CAP0805
2 1
C44
0.1uF
CAP0805
2 1
C50
0.1uF
CAP0805
2 1
C86
0.1uF
CAP0805
21
C84
0.22uF
CAP1206
21
R54
10
1/8W 5%
1 2
C83
0.01uF
CAP0805
21
C88
4.7uF
CAPT7343
21
CR9
CMPSH3
2 3
U17
MAX767CAP 17
BST
1
CS
19
DH
16
DL
20
FB
4GND1
5GND2
6GND3
7GND4
11GND5
18
LX
3ON/OFF#
13
PGND
8REF
2SS
9SYNC
10VCC1
14VCC2
15VCC3
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RN
4/14/98 01 11
+5V
+5V
+5V +3V +3V +3V
+5V P33V {02,04,08,09}
RAM3V {04,06,11}
NOTE: PINS 3-7 ARE VIAS
SDRAM DECOUPLING
SPCI DECOUPLING
IC DECOUPLING
DECOUPLING & 3.3V POWER
12345678
12345678
A
B
C
D
A
B
C
D
U16
74ALS08
4
56
U16
74ALS08
9
10 8
U16
74ALS08
12
13 11
U16
74ALS08
1
23
R58
10K
1/10W 5%
1 2
R39
10K
1/10W 5%
1 2
Z3
JUMP1X2
1 2
PRIMARY PCI SIGNALS
U15
i960RN
C20
P_CLK
H3 P_IDSEL
N3 P_PAR
W3
P_PAR64
R2 P_C/BE0
N5 P_C/BE1
K1 P_C/BE2
H4 P_C/BE3
W5 P_C/BE4
V1 P_C/BE5
V3 P_C/BE6
V4 P_C/BE7
L1P_DEVSEL
L5P_FRAME
A7 P_GNT
E8
P_INTAD8
P_INTBE7
P_INTCC7
P_INTD
L3P_IRDY
M4P_LOCK
M3
P_PERR
E6 P_REQ
U5
P_REQ64
B7 P_RST
M1
P_SERR
M5P_STOP
L2P_TRDY
U1 P_AD0
U2 P_AD1
P1 P_AD10
P3 P_AD11
P4 P_AD12
P5 P_AD13
N1 P_AD14
N2 P_AD15
K3 P_AD16
K4 P_AD17
K5 P_AD18
J1 P_AD19
U3 P_AD2
J2 P_AD20
J3 P_AD21
J5 P_AD22
H1 P_AD23
H5 P_AD24
G1 P_AD25
G2 P_AD26
G3 P_AD27
E5 P_AD28
A6 P_AD29
T1P_AD3
C6 P_AD30
D6 P_AD31
AG2
P_AD32
AG3
P_AD33
AF1
P_AD34
AF3
P_AD35
AF4
P_AD36
AF5
P_AD37
AE1
P_AD38
AE2
P_AD39
T3P_AD4
AE3
P_AD40
AE5
P_AD41
AD1
P_AD42
AD3
P_AD43
AD4
P_AD44
AD5
P_AD45
AC1
P_AD46
AC2
P_AD47
AC3
P_AD48
AC5
P_AD49
T4P_AD5
AB1
P_AD50
AB3
P_AD51
AB4
P_AD52
AB5
P_AD53
AA1
P_AD54
AA2
P_AD55
AA3
P_AD56
AA5
P_AD57
Y1
P_AD58
Y3
P_AD59
T5P_AD6
Y4
P_AD60
Y5
P_AD61
W1
P_AD62
W2
P_AD63
R1 P_AD7
R3 P_AD8
R5 P_AD9
V5
P_ACK64
R55
22
RNC4R8P
8
7
6
54
3
2
1
R40
22
RNC4R8P
8
7
6
54
3
2
1
U18
CY7B9910-7 13
FB
3FS
1REF
23TEST
7
Q0
8
Q1
10
Q2
11
Q3
15
Q4
16
Q5
18
Q6
19
Q7
J15
CONNPCI_A
66+5V1
75+5V2
84+5V3
91AD32
89AD34
88AD36
86AD38
85AD40
83AD42
82AD44
80AD46
79AD48
77AD50
76AD52
74AD54
73AD56
71AD58
70AD60
68AD62
65C/BE5#
64C/BE7#
63GND1
69GND2
72GND3
78GND4
81GND5
87GND6
90GND7
93GND8
67PAR64
92
94
J14
CONNPCI_B
70+5V1
79+5V2
88+5V3
90AD33
89AD35
87AD37
86AD39
84AD41
83AD43
81AD45
80AD47
78AD49
77AD51
75AD53
74AD55
72AD57
71AD59
69AD61
68AD63
66C/BE4#
65C/BE6#
64GND1
67GND2
73GND3
76GND4
82GND5
85GND6
91GND7
94GND8
63
92
93
J15
CONNPCI_A
33+3V1
39+3V2
45+3V3
53+3V4
59+5V1
61+5V2
62+5V3
58AD0
47AD11
46AD13
44AD15
32AD16
57AD2
55AD4
54AD6
49AD9
52C/BE0#
34FRAME#
35GND1
37GND2
42GND3
48GND4
56GND5
43PAR
60REQ64#
41SBO#
40SDONE
38STOP#
36TRDY#
J15
CONNPCI_A
2+12V
21+3V1
27+3V2
5+5V1
8+5V2
10+5V3
16+5V4
31AD18
29AD20
28AD22
25AD24
23AD26
22AD28
20AD30
12GND1
13GND2
18GND3
24GND4
30GND5
17GNT#
26IDSEL
6INTA#
7INTC#
9
11
14
19
15RST#
4TDI
3TMS
1TRST#
J14
CONNPCI_B
36+3V1
41+3V2
43+3V3
54+3V4
59+5V1
61+5V2
62+5V3
60ACK64#
58AD1
48AD10
47AD12
45AD14
32AD17
56AD3
55AD5
53AD7
52AD8
44C/BE1#
33C/BE2#
37DEVSEL#
34GND1
38GND2
46GND3
49GND4
57GND5
35IRDY#
39LOCK#
40PERR#
42SERR#
J14
CONNPCI_B
25+3V1
31+3V2
5+5V1
6+5V2
19+5V3
1-12V
30AD19
29AD21
27AD23
24AD25
23AD27
21AD29
20AD31
26C/BE3#
16CLK
3GND1
12GND2
13GND3
15GND4
17GND5
22GND6
28GND7
7INTB#
8INTD#
9PRSNT1#
11PRSNT2#
18REQ#
10
14
2TCK
4TDO
C89
47uF
CAPT7343
21
C97
0.1uF
CAP0805
21
C98
0.1uF
CAP0805
21
C100
0.1uF
CAP0805
21
C101
0.1uF
CAP0805
21
C102
0.1uF
CAP0805
21
C104
0.1uF
CAP0805
21
C94
0.1uF
CAP0805
21
C95
0.1uF
CAP0805
21
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RN
4/14/98 02 11
PPCI
P33V
+12V
+5V N12V +5V
TD TD
PPCI PINTA#
PINTB# PINTC#
PINTD#
PAD63
PAD62
PAD61
PAD60
PAD59
PAD58
PAD57
PAD56
PAD55
PAD54
PAD53
PAD52
PAD51
PAD50
PAD49
PAD48
PAD47
PAD46
PAD45
PAD44
PAD43
PAD42
PAD41
PAD40
PAD39
PAD38
PAD37
PAD36
PAD35
PAD34
PAD33
PAD32
+5V +5V
PC/BE7#
PC/BE6# PC/BE5#
PC/BE4#
PRST# PPAR64
PAD63 PAD62
PC/BE0# PINTA# PGNT# PAD61
PC/BE1# PINTB# PREQ# PAD60
PC/BE2# PINTC# PAD59 PAD58
PC/BE3# PINTD# PAD31 PAD30 PAD57
PC/BE4# PAD29 P33V PAD56
PC/BE5# PPAR64 PAD28 PAD55 PAD54
PC/BE6# PPERR# PAD27 PAD26 PAD53
PC/BE7# PSERR# PAD25 PAD52
PREQ64# P33V PAD24 PAD51 PAD50
PFRAME# PACK64# PC/BE3# PIDSEL PAD49
PDEVSEL# PAD23 P33V PAD48
PIRDY# PAD22 PAD47 PAD46
PTRDY# PAD21 PAD20 PAD45
PSTOP# PAD19 PAD44
PIDSEL P33V PAD18 PAD43 PAD42
PPAR PAD41
PREQ# PAD17 PAD16 PAD40
PGNT# PC/BE2# P33V PAD39 PAD38
RST# PFRAME# PAD37
PLOCK# PIRDY# PAD36
P33V PTRDY# PAD35 PAD34
PDEVSEL# PAD33
PSTOP# PAD32
PLOCK# P33V
PPERR#
+5V
PAD31
PAD30
PAD29
PAD28
PAD27
PAD26
PAD25
PAD24
PAD23
PAD22
PAD21
PAD20
PAD19
PAD18
PAD17
PAD16
PAD15
PAD14
PAD13
PAD12
PAD11
PAD10
PAD9
PAD8
PAD7
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
PAD0
PSERR#
P33V PPAR
PC/BE1# PAD15
PAD14 P33V
PAD13
PAD12 PAD11 PRST#
PAD10 RST# {11}
CLK_960 PAD9
LOGIC_CLK {05} PAD8 PC/BE0#
CLK PAD7 P33V
P33V PAD6
PAD5 PAD4
PAD3
PAD2
CLKA {08} PAD1 PAD0
CLKB {08} PACK64# PREQ64#
CLKC {09}
CLKD {09}
SPARES
PRIMARY PCI INTERFACE
12345678
12345678
A
B
C
D
A
B
C
D
TP2
1
U13
74ALS32
12
13 11
U13
74ALS32
9
10 8
U13
74ALS32
4
56
U13
74ALS32
1
23
C110
18pF
CAP0805
21
R22
30
RNC4R8P
8
7
6
5 4
3
2
1
R23
30
RNC4R8P
8
7
6
5 4
3
2
1
R57
2.7K
1/10W 5%
1 2
R37
24
1/10W 5%
12
R29
36
1/10W 5%
12
R13
1.5K
RNC4R8P
8
7
6
54
3
2
1
R41
1.5K
1/10W 5%
1 2
R42
1.5K
1/10W 5%
1 2
Z2
JUMP1X2
1 2
Z1
JUMP1X2
1 2
U9
MPC9140/CDC318
11 CLKIN
38 OE
4
OUT05
OUT1
35
OUT1036
OUT1140
OUT1241
OUT1344
OUT1445
OUT1521
OUT1628
OUT17
8
OUT29
OUT313
OUT414
OUT517
OUT618
OUT731
OUT832
OUT9
25 SCLK
24 SDA
MEMORY CONTROLLER
U15
i960RN
E21 DCLKIN
T31SBA0
T30SBA1
C21
ONCE
D22 DQ0
A23 DQ1
E27 DQ10
C28 DQ11
H32DQ12
H30DQ13
J32DQ14
J29DQ15
W29DQ16
Y32DQ17
Y30DQ18
AA32 DQ19
C23 DQ2
AA29 DQ20
AB32 DQ21
AB30 DQ22
AC32 DQ23
AC29 DQ24
AD32 DQ25
AD30 DQ26
AE32 DQ27
AE29 DQ28
AF32 DQ29
A24 DQ3
AF30 DQ30
AG32DQ31
E22
DQ32
B23
DQ33
E23
DQ34
C24
DQ35
E24
DQ36
B25
DQ37
E25
DQ38
C26
DQ39
D24 DQ4
A27
DQ40
C27
DQ41
A28
DQ42
G32
DQ43
H31
DQ44
H28
DQ45
J30
DQ46
J28
DQ47
W28
DQ48
Y31
DQ49
A25 DQ5
Y28
DQ50
AA30
DQ51
AA28
DQ52
AB31
DQ53
AB28
DQ54
AC30
DQ55
AC28
DQ56
AD31
DQ57
AD28
DQ58
AE30
DQ59
C25 DQ6
AE28
DQ60
AF31
DQ61
AF28
DQ62
AH32
DQ63
A26 DQ7
E26 DQ8
B27 DQ9
B13
RAD1/32BITPCI_EN#
E15
RAD10
E17
RAD11
A18
RAD12
C18
RAD13
D18
RAD14
E18
RAD15
A19
RAD16
C13
RAD2/32BITMEM_EN#
E13
RAD3/RETRY
A14
RAD4/STEST
C14
RAD5
D14
RAD6/RST_MODE#
C15
RAD9
K32
SCB0
K30
SCB1
V31
SCB2
W32
SCB3
K31
SCB4
K28
SCB5
V30
SCB6
W30
SCB7
A22 DCLKOUT
A13
RAD0
E14
RAD7
A15
RAD8
B19
RALE
N30 SA0
N29 SA1
R28 SA10
T32SA11
N28 SA2
P32 SA3
P31 SA4
P30 SA5
P28 SA6
R32 SA7
R30 SA8
R29 SA9
T28SCKE0
U32 SCKE1
L29SDQM0
M32SDQM1
U30 SDQM2
U28 SDQM3
L28SDQM4
M31SDQM5
U29 SDQM6
V32 SDQM7
C19
RCE0E19
RCE1
D20
ROEA20
RWE
L30SCAS
M30SCE0
M28SCE1
N32 SRAS
L32SWE
S1
SWDIP4
1
2
3
4
8
7
6
5
R51
22
1/10W 5%
12
R50
22
1/10W 5%
12
U6
74ALS04
11 10
U6
74ALS04
13 12
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RN
4/14/98 03 11
+3V
SDRAM {05,06}
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DCLKIN
DCLKOUT DRAMCLK_LA {05}
DCLKOUT DCLK0 {06}
DCLK1 {06}
SCB7
DCLKIN SCB6
SCB5
SA11 SCB4
SA10 SCB3 DCLK2 {06}
SA9 SCB2
DCLK3 {06}
SA8 SCB1
SA7 SCB0 RAD {04,05}
SA6
SA5 ROE#
SA4 RWE#
SA3 RCE0# SDA {06,07}
SA2 RCE1# SCL {06,07}
SA1 RALE
SA0
ONCE#
SBA0 RAD16
SBA1 RAD15
SRAS# RAD14
SCAS# RAD13
SWE# RAD12 ROMA {04}
SCE0# RAD11 ROMA18
SCE1# RAD10 SELUART# {04}
SCKE0 {06,11} RAD9 RCE1#
RAD8
RAD7
SM7 RAD6/RST_MODE#
SCKE1 {06,11} SM6 RAD5 IOW# {04}
RWE#
SM5 RAD4/STEST
SM4 RAD3/RETRY
SM3 RAD2/32BITMEM_EN#
SEL_LED# {04}SM2 RAD1/32BITPCI_EN#
SM1 RAD0
SM0
IOR# {04}
DQ24
DQ19
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ23
DQ22
DQ21
DQ20
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
RAD6/RST_MODE#
RAD3/RETRY
RAD2/32BITMEM_EN# RAD4/STEST
RAD1/32BITPCI_EN#
RAD0
MEMORY CONTROLLER
12345678
12345678
A
B
C
D
A
B
C
D
R18
1.6K
1/10W 5%
12
CR4
LED GREEN LP
21
R59
10K
1/10W 5%
1 2
U11
E28F016S5
24A0
23A1
14A10
13A11
8A12
7A13
6A14
5A15
4A16
3A17
2A18
1A19
22A2
40A20
21A3
20A4
19A5
18A6
17A7
16A8
15A9
36
RY/BY
11
VPP
9CE
37OE
12
RP
38WE
25
D0
26
D1
27
D2
28
D3
32
D4
33
D5
34
D6
35
D7
Z4
JUMP1X2
1 2
R19
330
1/10W 5%
12
R17
470
1/10W 5%
12
CR3
LED RED
21
CR5
LED GREEN
21
U6
74ALS04
5 6
U6
74ALS04
3 4
U6
74ALS04
9 8
U6
74ALS04
1 2
CR1
LED4SM
87
CR1
LED4SM
21
CR1
LED4SM
43
CR1
LED4SM
65
CR2
LED4SM
21
CR2
LED4SM
43
CR2
LED4SM
87
CR2
LED4SM
65
R15
470
RNC4R8P
8
7
6
5 4
3
2
1
R16
470
RNC4R8P
8
7
6
5 4
3
2
1
U3
74ABT273
31D
42D
73D
84D
135D
146D
177D
188D
11CLK
1CLR
2
1Q 5
2Q 6
3Q 9
4Q 12
5Q 15
6Q 16
7Q 19
8Q
U2
74ABT573
21D
32D
43D
54D
65D
76D
87D
98D
11LE
1OC
19
1Q18
2Q17
3Q16
4Q15
5Q14
6Q13
7Q12
8Q
U1
74ABT573
21D
32D
43D
54D
65D
76D
87D
98D
11LE
1OC
19
1Q18
2Q17
3Q16
4Q15
5Q14
6Q13
7Q12
8Q
J7
CONNJ6-6P
1
2
3
5
4
6
U4
OSC1.8432MHz
1E/D 5
O
U5
1488
2IN1A
4IN1B
5IN2B
9IN3A
10IN3B
12IN4A
13IN4B
3
OUTA
6
OUTB
8
OUTC
11
OUTD
U7
1489A
13
12
11
U7
1489A
10
9
8
U7
1489A
1
2
3
U7
1489A
4
5
6
U12
16C550
31A0
30A1
29A2
14CS0
15CS1
25IOR
21IOW
39RST
10
RXCLK
11
RXD
18
XTAL1
28AS
42
CD
16CS2
40
CTS41
DSR
24IOR
20IOW
43
RI
2D0
3D1
4D2
5D3
6D4
7D5
8D6
9D7
33
INT
32
RXRDY
13
TXD
27
TXRDY19
XTAL2
17
BAUDOUT
26
DDIS
37
DTR
38
OP1
35
OP2
36
RTS
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RN
4/14/98 04 11
+5V
RAD16
ROMA {03} RAD15
RAD14
RAD {03,05} RAD13
RAD12 +5V
RAD11
RAD10
RAD16 ROMA16 RAD9
RAD15 ROMA15 RAD2/32BITMEM_EN#
RAD14 ROMA14 RAD1/32BITPCI_EN#
RAD13 ROMA13 RAD0
RAD12 ROMA12 +5V
RAD11 ROMA11 SELUART# {03}
RAD10 ROMA10
RAD9 ROMA9
RALE IOR# {03}
IOW# {03}
I_RST# {05,07} IRQUART# {07}RAD6/RST_MODE# ROMA20
RAD5 ROMA19
RAD4/STEST ROMA18
+12V
RAD3/RETRY ROMA17 +5V
ROMA20
ROMA19
ROMA18
ROMA17
RALE ROMA16 I_RST# {05,07}
ROMA15 RAD9 LED0
ROMA14 RAD10 LED1
ROMA13 RAD11 LED2
ROMA12 RAD12 LED3
ROMA11 RAD13 LED4
ROMA10 RAD14 LED5
ROMA9 RAD15 LED6
RAD8 RAD16 LED7
RAD7 SEL_LED# {03}
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
RAD6/RST_MODE#
RAD5
RAD4/STEST
RAD3/RETRY RAD16
+5V RAD2/32BITMEM_EN# RAD15
RAD1/32BITPCI_EN# RAD14
RAD0 RAD13
RAD12 +5V
RWE# RAD11 FAIL# {07}
RCE0# RAD10
ROE# RAD9
RAM3V {01,06,11}
P33V {01,02,08,09}
SPARES
FLASH ROM, UART, & LEDS
12345678
12345678
A
B
C
D
A
B
C
D
J12
MICTOR
4
25
24
23
22
21
20
5
6
3CLK0
36CLK1
7
8
9
10
39
GND1 40
GND2 41
GND3 42
GND4 43
GND5
11
12
13
14
15
16
17
18
19
35
34
33
32
31
30
29
28
27
26
J11
MICTOR
4
25
24
23
22
21
20
5
6
3CLK0
36CLK1
7
8
9
10
39
GND140
GND241
GND342
GND443
GND5
11
12
13
14
15
16
17
18
19
35
34
33
32
31
30
29
28
27
26
J10
MICTOR
4
25
24
23
22
21
20
5
6
3CLK0
36 CLK1
7
8
9
10
39
GND140
GND241
GND342
GND443
GND5
11
12
13
14
15
16
17
18
19
35
34
33
32
31
30
29
28
27
26
J8
MICTOR
4
25
24
23
22
21
20
5
6
3CLK0
36CLK1
7
8
9
10
39
GND1 40
GND2 41
GND3 42
GND4 43
GND5
11
12
13
14
15
16
17
18
19
35
34
33
32
31
30
29
28
27
26
J9
MICTOR
4
25
24
23
22
21
20
5
6
3CLK0
36CLK1
7
8
9
10
39
GND1 40
GND2 41
GND3 42
GND4 43
GND5
11
12
13
14
15
16
17
18
19
35
34
33
32
31
30
29
28
27
26
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RN
4/14/98 05 11
SDRAM {03,06} RAD {03,04}
DRAMCLK_LA {03}
DQ15 SM7 DQ31 RAD15
DQ14 SM6 DQ30 RAD14
DQ13 SM5 DQ29 RAD13
DQ12 SM4 DQ28 RAD12
DQ11 SM3 DQ27 RAD11
DQ10 SM2 DQ26 RAD10
DQ9 SM1 DQ25 RAD9
DQ8 SM0 DQ24 RAD8
DQ7 SCB7 DQ23 RAD7
DQ6 SCB6 DQ22 RAD6/RST_MODE#
DQ5 SCB5 DQ21 RAD5
DQ4 SCB4 DQ20 RAD4/STEST
SCE0#
DQ3 SCB3 DQ19 RAD3/RETRY
SCE1#
DQ2 SCB2 DQ18 RAD2/32BITMEM_EN#
SBA1
DQ1 SCB1 DQ17 RAD1/32BITPCI_EN#
SBA0
DQ0 SCB0 DQ16 RAD0
LOGIC_CLK {02} RALE
DQ47 SWE# DQ63
DQ46 SCAS# DQ62
DQ45 SRAS# DQ61
DQ44 DQ60 SPCI {07,08,09,10} SGNT5#
DQ43 SA11 DQ59 SGNT4#
DQ42 SA10 DQ58 SGNT3#
DQ41 SA9 DQ57 I_RST# {04,07}
SGNT2#
DQ40 SA8 DQ56 SGNT1#
DQ39 SA7 DQ55 RWE#
SGNT0#
DQ38 SA6 DQ54 ROE#
SREQ5#
DQ37 SA5 DQ53 RCE1#
SREQ4#
DQ36 SA4 DQ52 RCE0#
SREQ3#
DQ35 SA3 DQ51 RALE
SREQ2#
DQ34 SA2 DQ50 SREQ1#
DQ33 SA1 DQ49 SREQ0#
DQ32 SA0 DQ48 RAD16
LOGIC ANALYZER I/F
12345678
12345678
A
B
C
D
A
B
C
D
J5
SDRAM-DIMM168P
117A1
123A11
118A3
119A5
120A7
121A9
122BA0
111CAS
105CB4
106CB5
136
CB6137
CB7
128
CKE0
125CLK1
163
CLK3
114CS1
129
CS3
85GND1
96GND2
107GND3
116GND4
127
GND5
138
GND6
148
GND7
152
GND8
162
GND9
112M4
113M5
130
M6131
M7
108NC1
147
NC10
164
NC11
109NC2
126NC4
132
NC5
134
NC6135
NC7
145
NC8146
NC9
115RAS
165
SA0166
SA1167
SA2
90VCC1
102VCC2
110VCC3
124VCC4
133
VCC5
143
VCC6
157
VCC7
168
VCC8
86DQ32
87DQ33
88DQ34
89DQ35
91DQ36
92DQ37
93DQ38
94DQ39
95DQ40
97DQ41
98DQ42
99DQ43
100DQ44
101DQ45
103DQ46
104DQ47
139
DQ48140
DQ49141
DQ50142
DQ51
144
DQ52
149
DQ53150
DQ54151
DQ55
153
DQ56154
DQ57155
DQ58156
DQ59
158
DQ60159
DQ61160
DQ62161
DQ63
J5
SDRAM-DIMM168P
33A0
38A10
34A2
35A4
36A6
37A8
39BA1
21CB0
22CB1
52
CB253
CB3
63
CKE1
42CLK0
79
CLK2
30CS0
45
CS2
9DQ6
1GND1
12GND2
23GND3
32GND4
43
GND5
54
GND6
64
GND7
68
GND8
78
GND9
28M0
29M1
46
M247
M3
24NC1
80
NC1081
NC11
25NC2
31NC3
44
NC4
48
NC5
50
NC651
NC7
61
NC862
NC9
83
SCL
82
SDA
6VCC1
18VCC2
26VCC3
40VCC4
41VCC5
49
VCC6
59
VCC7
73
VCC8
84
VCC9
27WE
2DQ0
3DQ1
14DQ10
15DQ11
16DQ12
17DQ13
19DQ14
20DQ15
55
DQ1656
DQ1757
DQ1858
DQ19
4DQ2
60
DQ20
65
DQ2166
DQ2267
DQ23
69
DQ2470
DQ2571
DQ2672
DQ27
74
DQ2875
DQ29
5DQ3
76
DQ3077
DQ31
7DQ4
8DQ5
10DQ7
11DQ8
13DQ9
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RN
4/14/98 06 11
RAM3V {01,04,11}
SDRAM {03,05}
DQ0 DQ32 SCKE0 {03,11}
DQ1 SCE0# DQ33 SCE1#
DQ2 SM2 DQ34 SM6
DQ3 SM3 DQ35 SM7
DQ4 DQ36
DQ5 DQ37
DQ6 DQ38
DQ7 SCB2 DQ39 SCB6
DQ8 SCB3 DQ40 SCB7
DQ9 DQ16 DQ41 DQ48
DQ10 DQ17 DQ42 DQ49
DQ11 DQ18 DQ43 DQ50
DQ12 DQ19 DQ44 DQ51
DQ13 DQ45
DQ20 DQ52
DQ14 DQ46
DQ15 DQ47
SCB0 SCKE1 {03,11} SCB4
SCB1 SCB5
DQ21 DQ53
DQ22 DQ54
DQ23 DQ55
SWE# DQ24 SCAS# DQ56
SM0 DQ25 SM4 DQ57
SM1 DQ26 SM5 DQ58
SCE0# DQ27 SCE1# DQ59
SRAS#
DQ28 DQ60
SA0 DQ29 SA1 DQ61
SA2 DQ30 SA3 DQ62
SA4 DQ31 SA5 DQ63
SA6 SA7
SA8 DCLK2 {03} SA9 DCLK3 {03}
SA10 SBA0
SBA1 SA11
SDA {03,07}
SCL {03,07} DCLK1 {03}
DCLK0 {03}
SDRAM 168-PIN DIMM
12345678
12345678
A
B
C
D
A
B
C
D
R14
1.5K
1/10W 5%
1 2
JX CORE/I2C/JTAG
U15
i960RN
C12
TCK A12
TDI
B11
TMS
E20 VCC5REF
C22VCCPLL1
B15 VCCPLL2
D26VCCPLL3
A21
LCDINIT
A9 NMI
B9 S_INTA/XINT0
C9 S_INTB/XINT1
E9 S_INTC/XINT2
A10 S_INTD/XINT3
C11
TRST
C10XINT4
D10XINT5
C8
SDAA8
SCL
E11
TDO
E12 FAIL
A11
I_RST
SECONDARY PCI SIGNALS
U15
i960RN
AM13
S_ACK64
AL26S_REQ0
AH27 S_REQ1
AK27 S_REQ2
AH28 S_REQ3
AL28S_REQ4
AJ29 S_REQ5
AH14S_AD0
AK14 S_AD1
AM17S_AD10
AH18S_AD11
AK18 S_AD12
AL18 S_AD13
AM18S_AD14
AH19S_AD15
AH22S_AD16
AK22 S_AD17
AL22 S_AD18
AM22S_AD19
AL14 S_AD2
AH23S_AD20
AJ23 S_AD21
AK23 S_AD22
AM23S_AD23
AK24 S_AD24
AL24 S_AD25
AM24S_AD26
AH25S_AD27
AJ25 S_AD28
AK25 S_AD29
AM14S_AD3
AM25S_AD30
AH26S_AD31
AH1
S_AD32
AH3
S_AD33
AH4
S_AD34
AJ2
S_AD35
AJ5
S_AD36
AK5
S_AD37
AM5
S_AD38
AH6
S_AD39
AH15S_AD4
AK6
S_AD40
AL6
S_AD41
AM6
S_AD42
AH7
S_AD43
AJ7
S_AD44
AK7
S_AD45
AM7
S_AD46
AH8
S_AD47
AK8
S_AD48
AL8
S_AD49
AJ15 S_AD5
AM8
S_AD50
AH9
S_AD51
AJ9
S_AD52
AK9
S_AD53
AM9
S_AD54
AH10
S_AD55
AK10
S_AD56
AL10
S_AD57
AM10
S_AD58
AH11
S_AD59
AK15 S_AD6
AJ11
S_AD60
AK11
S_AD61
AM11
S_AD62
AH12
S_AD63
AM15S_AD7
AJ17 S_AD8
AK17 S_AD9
AK19 S_PAR
AK12 S_PAR64
AH17
S_C/BE0AJ19
S_C/BE1AM21
S_C/BE2AH24
S_C/BE3AL12
S_C/BE4AM12
S_C/BE5AH13
S_C/BE6AJ13
S_C/BE7
AM20
S_DEVSEL
AK21
S_FRAMEAJ21
S_IRDY
AK20
S_LOCK
AH20
S_PERR
AK13
S_REQ64
AM19
S_SERR
AL20
S_STOP
AH21
S_TRDY
AM26S_GNT0
AJ27 S_GNT1
AM27S_GNT2
AK28 S_GNT3
AM28S_GNT4
AK29 S_GNT5
AK26
S_RST
R36
2.7K
RNC4R8P
8
7
6
54
3
2
1
R3
2.7K
RNC4R8P
8
7
6
54
3
2
1
R44
2.7K
RNC4R8P
8
7
6
54
3
2
1
R52
100
1/2W 5%
12
J6
HEAD16SH
JTAG HEADER
1
10
11 12
13 14
15 16
2
3 4
5 6
7 8
9
R30
10
1/8W 5%
12
R56
10
1/8W 5%
12
R43
10
1/8W 5%
12
C61
0.01uF
CAP0805
21
C96
0.01uF
CAP0805
21
C77
0.01uF
CAP0805
21
C57
4.7uF
CAPT7343
21
C92
4.7uF
CAPT7343
21
C76
4.7uF
CAPT7343
21
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RN
4/14/98 07 11
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RN
4/14/98 07 11
SPCI {05,08,09,10}
SAD63
SAD62
SAD61
SAD60
SAD59
SAD58
SAD57
SAD56
SAD55
SAD54
SAD53
SAD52
SAD51
SAD50
SAD49
SAD48
SAD47
SAD46
SAD45
SAD44
SAD43
SAD42
SAD41
SAD40
SAD39
SAD38
SAD37
SAD36
SAD35
SAD34
SAD33
SAD32
+5V
SC/BE0#
SC/BE1#
SREQ0# SC/BE2#
SREQ1# SC/BE3#
SREQ2# SC/BE4#
SREQ3# SC/BE5#
SREQ4# SC/BE6#
SREQ5# SC/BE7#
SGNT0# SREQ64#
SGNT1# SACK64# SDA {03,06}
SCL {03,06}SGNT2# SFRAME#
SGNT3# SIRDY# +3V
SGNT4# STRDY#
SGNT5# SSTOP#
SDEVSEL# SINTA#
SPAR SSERR# SINTB#
SPAR64 SRST# SINTC#
SPERR# SINTD#
SLOCK#
IRQFAN# {11}
IRQUART# {04}
FAIL# {04}
I_RST# {04,05}
SAD31
SAD30
SAD29
SAD28
SAD27
SAD26
SAD25
SAD24
SAD23
SAD22
SAD21
SAD20
SAD19
SAD18
SAD17
SAD16
SAD15
SAD14
SAD13
SAD12
SAD11
SAD10
SAD9
SAD8
SAD7
SAD6
SAD5
SAD4
SAD3
SAD2
SAD1
SAD0
+5V
+3V
SECONDARY PCI/960 CORE
12345678
12345678
A
B
C
D
A
B
C
D
J1
CONNPCI_64
A66
+5V1
A75
+5V2
A84
+5V3
B70 +5V4
B79 +5V5
B88 +5V6
A91
AD32
B90 AD33
A89
AD34
B89 AD35
A88
AD36
B87 AD37
A86
AD38
B86 AD39
A85
AD40
B84 AD41
A83
AD42
B83 AD43
A82
AD44
B81 AD45
A80
AD46
B80 AD47
A79
AD48
B78 AD49
A77
AD50
B77 AD51
A76
AD52
B75 AD53
A74
AD54
B74 AD55
A73
AD56
B72 AD57
A71
AD58
B71 AD59
A70
AD60
B69 AD61
A68
AD62
B68 AD63
A63
GND1
B67 GND10
B73 GND11
B76 GND12
B82 GND13
B85 GND14
B91 GND15
B94 GND16
A69
GND2
A72
GND3
A78
GND4
A81
GND5
A87
GND6
A90
GND7
A93
GND8
B64 GND9
A67
PAR64
A92
A94
B63
B92
B93
B66 C/BE4
A65
C/BE5
B65 C/BE6
A64
C/BE7
J2
CONNPCI_64
A66
+5V1
A75
+5V2
A84
+5V3
B70 +5V4
B79 +5V5
B88 +5V6
A91
AD32
B90 AD33
A89
AD34
B89 AD35
A88
AD36
B87 AD37
A86
AD38
B86 AD39
A85
AD40
B84 AD41
A83
AD42
B83 AD43
A82
AD44
B81 AD45
A80
AD46
B80 AD47
A79
AD48
B78 AD49
A77
AD50
B77 AD51
A76
AD52
B75 AD53
A74
AD54
B74 AD55
A73
AD56
B72 AD57
A71
AD58
B71 AD59
A70
AD60
B69 AD61
A68
AD62
B68 AD63
A63
GND1
B67 GND10
B73 GND11
B76 GND12
B82 GND13
B85 GND14
B91 GND15
B94 GND16
A69
GND2
A72
GND3
A78
GND4
A81
GND5
A87
GND6
A90
GND7
A93
GND8
B64 GND9
A67
PAR64
A92
A94
B63
B92
B93
B66 C/BE4
A65
C/BE5
B65 C/BE6
A64
C/BE7
J2
CONNPCI_64
A33
+3V1
A39
+3V2
A45
+3V3
A53
+3V4
B36+3V5
B41+3V6
B43+3V7
B54+3V8
A59
+5V1
A61
+5V2 A62
+5V3
B59+5V4
B61+5V5
B62+5V6
A58
AD00
B58AD01
A57
AD02
B56AD03
A55
AD04
B55AD05
A54
AD06
B53AD07
B52AD08
A49
AD09
B48AD10
A47
AD11
B47AD12
A46
AD13
B45AD14
A44
AD15
A32
AD16
B32AD17
A35
GND1
B57GND10
A37
GND2
A42
GND3
A48
GND4
A56
GND5
B34GND6
B38GND7
B46GND8
B49GND9
A43
PAR
A40
SDONE
B60ACK64
A52
C/BE0
B44C/BE1
B33C/BE2
B37DEVSEL
A34
FRAME
B35IRDY
B39LOCK
B40PERR
A60
REQ64
A41
SBO
B42SERR
A38
STOP
A36
TRDY
J1
CONNPCI_64
A33
+3V1
A39
+3V2
A45
+3V3
A53
+3V4
B36+3V5
B41+3V6
B43+3V7
B54+3V8
A59
+5V1
A61
+5V2 A62
+5V3
B59+5V4
B61+5V5
B62+5V6
A58
AD00
B58AD01
A57
AD02
B56AD03
A55
AD04
B55AD05
A54
AD06
B53AD07
B52AD08
A49
AD09
B48AD10
A47
AD11
B47AD12
A46
AD13
B45AD14
A44
AD15
A32
AD16
B32AD17
A35
GND1
B57GND10
A37
GND2
A42
GND3
A48
GND4
A56
GND5
B34GND6
B38GND7
B46GND8
B49GND9
A43
PAR
A40
SDONE
B60ACK64
A52
C/BE0
B44C/BE1
B33C/BE2
B37DEVSEL
A34
FRAME
B35IRDY
B39LOCK
B40PERR
A60
REQ64
A41
SBO
B42SERR
A38
STOP
A36
TRDY
J2
CONNPCI_64
A2
+12V
A21
+3V1
A27
+3V2
B25 +3V3
B31 +3V4
A5
+5V1
A8
+5V2
A10
+5V3
A16
+5V4
B5+5V5
B6+5V6
B19 +5V7
B1-12V
A31
AD18
B30 AD19
A29
AD20
B29 AD21
A28
AD22
B27 AD23
A25
AD24
B24 AD25
A23
AD26
B23 AD27
A22
AD28
B21 AD29
A20
AD30
B20 AD31
B16 CLK
A12
GND1
B17 GND10
B22 GND11
B28 GND12
A13
GND2
A18
GND3
A24
GND4
A30
GND5
B3GND6
B12 GND7
B13 GND8
B15 GND9
A26
IDSEL
A9
A11
A14
A19
B10
B14
B2TCK
A4
TDI
B4TDO
A3
TMS
B26 C/BE3
A17
GNT
A6
INTA
B7INTB A7
INTC
B8INTD
B9PRSNT1
B11 PRSNT2
B18 REQ
A15
RST
A1
TRST
J1
CONNPCI_64
A2
+12V
A21
+3V1
A27
+3V2
B25 +3V3
B31 +3V4
A5
+5V1
A8
+5V2
A10
+5V3
A16
+5V4
B5+5V5
B6+5V6
B19 +5V7
B1-12V
A31
AD18
B30 AD19
A29
AD20
B29 AD21
A28
AD22
B27 AD23
A25
AD24
B24 AD25
A23
AD26
B23 AD27
A22
AD28
B21 AD29
A20
AD30
B20 AD31
B16 CLK
A12
GND1
B17 GND10
B22 GND11
B28 GND12
A13
GND2
A18
GND3
A24
GND4
A30
GND5
B3GND6
B12 GND7
B13 GND8
B15 GND9
A26
IDSEL
A9
A11
A14
A19
B10
B14
B2TCK
A4
TDI
B4TDO
A3
TMS
B26 C/BE3
A17
GNT
A6
INTA
B7INTB A7
INTC
B8INTD
B9PRSNT1
B11 PRSNT2
B18 REQ
A15
RST
A1
TRST
C19
0.01uF
CAP0805
2 1
C18
0.01uF
CAP0805
2 1
C27
0.01uF
CAP0805
2 1
C26
0.01uF
CAP0805
2 1
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RN
4/14/98 08 11
SPCI {05,07,09,10}
+12V
+5V +5V
N12V
+5V +5V +5V +5V
SC/BE7#
STRST# {09,10} SAD17 SAD16 SC/BE6# SC/BE5#
STCK {09,10} SC/BE2# P33V {01,02,04,09} SC/BE4#
STMS {09,10} SFRAME# SPAR64
STDI {09,10} SIRDY# SAD63 SAD62
P33V {01,02,04,09} STRDY# SAD61
SINTA# SDEVSEL# SAD60
SINTB# SINTC# SSTOP# SAD59 SAD58
SINTD# SLOCK# SAD57
SPERR# SAD56
SAD55 SAD54
SSERR# SAD53
SPAR SAD52
SC/BE1# SAD15 SAD51 SAD50
SAD14 SAD49
SRST# SAD13 SAD48
CLKA {02} SAD12 SAD11 SAD47 SAD46
SGNT0# SAD10 SAD45
SREQ0# SAD9 SAD44
SAD43 SAD42
SAD31 SAD30 SAD41
SAD29 P33V {01,02,04,09} SAD8 SC/BE0# SAD40
SAD28 SAD7 SAD39 SAD38
SAD27 SAD26 SAD6 SAD37
SAD25 SAD5 SAD4 SAD36
P33V {01,02,04,09} SAD24 SAD3 SAD35 SAD34
SC/BE3# SAD16 SAD2 SAD33
SAD23 SAD1 SAD0 SAD32
SAD22
SAD21 SAD20 SACK64# SREQ64#
SAD19
SAD18
+12V
N12V
STRST# {09,10} SAD17 SAD16 SC/BE7#
STCK {09,10} SC/BE2# P33V {01,02,04,09} SC/BE6# SC/BE5#
STMS {09,10} SFRAME# SC/BE4#
STDI {09,10} SIRDY# SPAR64
P33V {01,02,04,09} STRDY# SAD63 SAD62
SINTB# SDEVSEL# SAD61
SINTC# SINTD# SSTOP# SAD60
SINTA# SLOCK# SAD59 SAD58
SPERR# SAD57
SAD56
SSERR# SAD55 SAD54
SPAR SAD53
SC/BE1# SAD15 SAD52
SAD14 SAD51 SAD50
SRST# SAD13 SAD49
CLKB {02} SAD12 SAD11 SAD48
SGNT1# SAD10 SAD47 SAD46
SREQ1# SAD9 SAD45
SAD44
SAD31 SAD30 SAD43 SAD42
SAD29 SAD8 SC/BE0# SAD41
SAD28 SAD7 SAD40
SAD27 SAD26 SAD6 SAD39 SAD38
SAD25 SAD5 SAD4 SAD37
SAD24 SAD3 SAD36
SC/BE3# SAD17 SAD2 SAD35 SAD34
SAD23 SAD1 SAD0 SAD33
SAD22 SAD32
SAD21 SAD20 SACK64# SREQ64#
SAD19
SAD18
SPCI CONN 2
SPCI CONN 1
SECONDARY PCI BUS 1/2
12345678
12345678
A
B
C
D
A
B
C
D
J4
CONNPCI_64
A66
+5V1
A75
+5V2
A84
+5V3
B70 +5V4
B79 +5V5
B88 +5V6
A91
AD32
B90 AD33
A89
AD34
B89 AD35
A88
AD36
B87 AD37
A86
AD38
B86 AD39
A85
AD40
B84 AD41
A83
AD42
B83 AD43
A82
AD44
B81 AD45
A80
AD46
B80 AD47
A79
AD48
B78 AD49
A77
AD50
B77 AD51
A76
AD52
B75 AD53
A74
AD54
B74 AD55
A73
AD56
B72 AD57
A71
AD58
B71 AD59
A70
AD60
B69 AD61
A68
AD62
B68 AD63
A63
GND1
B67 GND10
B73 GND11
B76 GND12
B82 GND13
B85 GND14
B91 GND15
B94 GND16
A69
GND2
A72
GND3
A78
GND4
A81
GND5
A87
GND6
A90
GND7
A93
GND8
B64 GND9
A67
PAR64
A92
A94
B63
B92
B93
B66 C/BE4
A65
C/BE5
B65 C/BE6
A64
C/BE7
J3
CONNPCI_64
A66
+5V1
A75
+5V2
A84
+5V3
B70 +5V4
B79 +5V5
B88 +5V6
A91
AD32
B90 AD33
A89
AD34
B89 AD35
A88
AD36
B87 AD37
A86
AD38
B86 AD39
A85
AD40
B84 AD41
A83
AD42
B83 AD43
A82
AD44
B81 AD45
A80
AD46
B80 AD47
A79
AD48
B78 AD49
A77
AD50
B77 AD51
A76
AD52
B75 AD53
A74
AD54
B74 AD55
A73
AD56
B72 AD57
A71
AD58
B71 AD59
A70
AD60
B69 AD61
A68
AD62
B68 AD63
A63
GND1
B67 GND10
B73 GND11
B76 GND12
B82 GND13
B85 GND14
B91 GND15
B94 GND16
A69
GND2
A72
GND3
A78
GND4
A81
GND5
A87
GND6
A90
GND7
A93
GND8
B64 GND9
A67
PAR64
A92
A94
B63
B92
B93
B66 C/BE4
A65
C/BE5
B65 C/BE6
A64
C/BE7
J4
CONNPCI_64
A33
+3V1
A39
+3V2
A45
+3V3
A53
+3V4
B36+3V5
B41+3V6
B43+3V7
B54+3V8
A59
+5V1
A61
+5V2 A62
+5V3
B59+5V4
B61+5V5
B62+5V6
A58
AD00
B58AD01
A57
AD02
B56AD03
A55
AD04
B55AD05
A54
AD06
B53AD07
B52AD08
A49
AD09
B48AD10
A47
AD11
B47AD12
A46
AD13
B45AD14
A44
AD15
A32
AD16
B32AD17
A35
GND1
B57GND10
A37
GND2
A42
GND3
A48
GND4
A56
GND5
B34GND6
B38GND7
B46GND8
B49GND9
A43
PAR
A40
SDONE
B60ACK64
A52
C/BE0
B44C/BE1
B33C/BE2
B37DEVSEL
A34
FRAME
B35IRDY
B39LOCK
B40PERR
A60
REQ64
A41
SBO
B42SERR
A38
STOP
A36
TRDY
J3
CONNPCI_64
A33
+3V1
A39
+3V2
A45
+3V3
A53
+3V4
B36+3V5
B41+3V6
B43+3V7
B54+3V8
A59
+5V1
A61
+5V2 A62
+5V3
B59+5V4
B61+5V5
B62+5V6
A58
AD00
B58AD01
A57
AD02
B56AD03
A55
AD04
B55AD05
A54
AD06
B53AD07
B52AD08
A49
AD09
B48AD10
A47
AD11
B47AD12
A46
AD13
B45AD14
A44
AD15
A32
AD16
B32AD17
A35
GND1
B57GND10
A37
GND2
A42
GND3
A48
GND4
A56
GND5
B34GND6
B38GND7
B46GND8
B49GND9
A43
PAR
A40
SDONE
B60ACK64
A52
C/BE0
B44C/BE1
B33C/BE2
B37DEVSEL
A34
FRAME
B35IRDY
B39LOCK
B40PERR
A60
REQ64
A41
SBO
B42SERR
A38
STOP
A36
TRDY
J4
CONNPCI_64
A2
+12V
A21
+3V1
A27
+3V2
B25 +3V3
B31 +3V4
A5
+5V1
A8
+5V2
A10
+5V3
A16
+5V4
B5 +5V5
B6 +5V6
B19 +5V7
B1 -12V
A31
AD18
B30 AD19
A29
AD20
B29 AD21
A28
AD22
B27 AD23
A25
AD24
B24 AD25
A23
AD26
B23 AD27
A22
AD28
B21 AD29
A20
AD30
B20 AD31
B16 CLK
A12
GND1
B17 GND10
B22 GND11
B28 GND12
A13
GND2
A18
GND3
A24
GND4
A30
GND5
B3 GND6
B12 GND7
B13 GND8
B15 GND9
A26
IDSEL
A9
A11
A14
A19
B10
B14
B2 TCK
A4
TDI
B4 TDO
A3
TMS
B26 C/BE3
A17
GNT
A6
INTA
B7 INTB A7
INTC
B8 INTD
B9 PRSNT1
B11 PRSNT2
B18 REQ
A15
RST
A1
TRST
J3
CONNPCI_64
A2
+12V
A21
+3V1
A27
+3V2
B25 +3V3
B31 +3V4
A5
+5V1
A8
+5V2
A10
+5V3
A16
+5V4
B5 +5V5
B6 +5V6
B19 +5V7
B1 -12V
A31
AD18
B30 AD19
A29
AD20
B29 AD21
A28
AD22
B27 AD23
A25
AD24
B24 AD25
A23
AD26
B23 AD27
A22
AD28
B21 AD29
A20
AD30
B20 AD31
B16 CLK
A12
GND1
B17 GND10
B22 GND11
B28 GND12
A13
GND2
A18
GND3
A24
GND4
A30
GND5
B3 GND6
B12 GND7
B13 GND8
B15 GND9
A26
IDSEL
A9
A11
A14
A19
B10
B14
B2 TCK
A4
TDI
B4 TDO
A3
TMS
B26 C/BE3
A17
GNT
A6
INTA
B7 INTB A7
INTC
B8 INTD
B9 PRSNT1
B11 PRSNT2
B18 REQ
A15
RST
A1
TRST
C3
0.01uF
CAP0805
2 1
C2
0.01uF
CAP0805
2 1
C11
0.01uF
CAP0805
2 1
C10
0.01uF
CAP0805
2 1
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RN
4/14/98 09 11
SPCI {05,07,08,10}
+12V
+5V +5V
+5V N12V +5V +5V +5V
SC/BE7#
STRST# {08,10} SAD17 SAD16 SC/BE6# SC/BE5#
STCK {08,10} SC/BE2# P33V {01,02,04,08} SC/BE4#
STMS {08,10} SFRAME# SPAR64
STDI {08,10} SIRDY# SAD63 SAD62
P33V {01,02,04,08} STRDY# SAD61
SINTC# SDEVSEL# SAD60
SINTD# SINTA# SSTOP# SAD59 SAD58
SINTB# SLOCK# SAD57
SPERR# SAD56
SAD55 SAD54
SSERR# SAD53
SPAR SAD52
SC/BE1# SAD15 SAD51 SAD50
SAD14 SAD49
SRST# SAD13 SAD48
CLKC {02} SAD12 SAD11 SAD47 SAD46
SGNT2# SAD10 SAD45
SREQ2# SAD9 SAD44
SAD43 SAD42
SAD31 SAD30 SAD41
SAD29 P33V {01,02,04,08} SAD8 SC/BE0# SAD40
SAD28 SAD7 SAD39 SAD38
SAD27 SAD26 SAD6 SAD37
SAD25 SAD5 SAD4 SAD36
P33V {01,02,04,08} SAD24 SAD3 SAD35 SAD34
SC/BE3# SAD18 SAD2 SAD33
SAD23 SAD1 SAD0 SAD32
SAD22
SAD21 SAD20 SACK64# SREQ64#
SAD19
SAD18
+12V
N12V
STRST# {08,10} SAD17 SAD16 SC/BE7#
STCK {08,10} SC/BE2# P33V {01,02,04,08} SC/BE6# SC/BE5#
STMS {08,10} SFRAME# SC/BE4#
STDI {08,10} SIRDY# SPAR64
P33V {01,02,04,08} STRDY# SAD63 SAD62
SINTD# SDEVSEL# SAD61
SINTA# SINTB# SSTOP# SAD60
SINTC# SLOCK# SAD59 SAD58
SPERR# SAD57
SAD56
SSERR# SAD55 SAD54
SPAR SAD53
SC/BE1# SAD15 SAD52
SAD14 SAD51 SAD50
SRST# SAD13 SAD49
CLKD {02} SAD12 SAD11 SAD48
SGNT3# SAD10 SAD47 SAD46
SREQ3# SAD9 SAD45
SAD44
SAD31 SAD30 SAD43 SAD42
SAD29 SAD8 SC/BE0# SAD41
SAD28 SAD7 SAD40
SAD27 SAD26 SAD6 SAD39 SAD38
SAD25 SAD5 SAD4 SAD37
SAD24 SAD3 SAD36
SC/BE3# SAD19 SAD2 SAD35 SAD34
SAD23 SAD1 SAD0 SAD33
SAD22 SAD32
SAD21 SAD20 SACK64# SREQ64#
SAD19
SAD18
SPCI CONN 4
SPCI CONN 3
SECONDARY PCI BUS 3/4
12345678
12345678
A
B
C
D
A
B
C
D
R2
2.7K
1/10W 5%
12
R4
2.7K
RNC4R8P
8
7
6
54
3
2
1
R5
2.7K
RNC4R8P
8
7
6
54
3
2
1
R6
2.7K
RNC4R8P
8
7
6
54
3
2
1
R7
2.7K
RNC4R8P
8
7
6
54
3
2
1
R8
2.7K
RNC4R8P
8
7
6
54
3
2
1
R9
2.7K
RNC4R8P
8
7
6
54
3
2
1
R10
2.7K
RNC4R8P
8
7
6
54
3
2
1
R11
2.7K
RNC4R8P
8
7
6
54
3
2
1
R12
2.7K
RNC4R8P
8
7
6
54
3
2
1
R45
2.7K
RNC4R8P
8
7
6
54
3
2
1
R31
2.7K
RNC4R8P
8
7
6
54
3
2
1
R33
2.7K
RNC4R8P
8
7
6
54
3
2
1
R38
2.7K
RNC4R8P
8
7
6
54
3
2
1
R1
2.7K
RNC4R8P
8
7
6
54
3
2
1
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RN
4/14/98 10 11
SPCI {05,07,08,09}
+5V +5V +5V
SAD32 SAD52
STMS SAD33 SAD53
STDI SAD34 SAD54
STRST# SAD35 SAD55
STCK
+5V
SAD36 SAD56
SFRAME# SAD37 SAD57
STRDY# SAD38 SAD58
SIRDY# SAD39 SAD59
SDEVSEL#
SAD40 SAD60
SSTOP# SAD41 SAD61
SSERR# SAD42 SAD62
SPERR# SAD43 SAD63
SLOCK#
SAD44 SC/BE4#
SREQ0# SAD45 SC/BE5#
SREQ1# SAD46 SC/BE6#
SREQ2# SAD47 SC/BE7#
SREQ3#
SAD48 SPAR64
SREQ4# SAD49
SREQ5# SAD50
SACK64# SAD51
SREQ64#
SPCI PULL-UPS
12345678
12345678
A
B
C
D
A
B
C
D
R24
100K
1/10W 5%
1 2
R32
100K
1/10W 5%
1 2
R60
10
1/10W 5%
1 2
R28
1
1/10W 5%
1 2
R27
1
1/10W 5%
1 2
R53
47K
1/10W 5%
1 2
R49
4.7K
1/10W 5%
1 2
R48
4.7K
1/10W 5%
1 2
U19
PALLV16V8Z-20JI
1I0
2I1
3I2
4I3
5I4
6I5
7I6
8I7
9I8
11 I9 20
VCC
12
F0 13
F1 14
F2 15
F3 16
F4 17
F5 18
F6 19
F7
U10
LM339
9+
8-
14
U10
LM339
11 +
10 -
13
U10
LM339
7+
6-
1
U10
LM339
5+
4-
2
R35
10K
1/10W 5%
1 2
C82
0.047uF
CAP0805
21
R47
2.4K
1/10W 5%
1 2
C47
22uF
CAPT7343
21
C65
0.47uF
CAP1206
21
J13
FAN CONN
1
FAN
2GND
3PWR
C63
33uF
CAPT7343
21
Q4
2N6109
1
2
3
R21
0.05
1W 1%
1 2
R20
150
1/10W 5%
1 2
R26
68K
1/10W 5%
1 2
R34
22K
1/10W 5%
1 2
BT8
BATT_HLDR
2
1
BT6
BATT_HLDR
2
1
BT1
BATT_HLDR
2
1
BT3
BATT_HLDR
2
1
BT7
BATT_HLDR
2
1
BT5
BATT_HLDR
2
1
BT2
BATT_HLDR
2
1
BT4
BATT_HLDR
2
1
CR8
CMR1-02
12
C64
330uF
CAPT7343H
21
C56
100uF
CAPT7343H
21
U8
MAX1651
2FB
8GND
4REF
3SHDN
6
CS7
EXT
1
OUT
5
V+
U14
MAX712
11CC
13GND
3
PGM04
PGM19
PGM210
PGM3
7TEMP
5THI
6TLO
1VLIMIT
2
BATT+
12
BATT-
14
DRV
16REF
15V+
8
FASTCHG
L1
47uH
1 2
7
6
5
4
3
CR7
MBRS340T3
1 2
Q1
SI9430
5
6
7
8
4
1
2
3
R25
1K
1/10W 5%
1 2
C74
1uF
CAPT3216
21
C54
10uF
CAPT7343
21
C52
10uF
CAPT7343
21
C51
0.1uF
CAP0805
21
C53
0.1uF
CAP0805
21
C58
0.01uF
CAP0805
21
C55
0.01uF
CAP0805
21
C68
0.01uF
CAP0805
21
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RN
4/14/98 11 11
SCKE0 {03,06}
+12V
SCKE1 {03,06}
RST# {02}
RAM3V {01,04,06}
BATTERY
RAM3V {01,04,06}
+5V
+5V
IRQFAN# {07}
PART # 101-1950-01
NOTE: VCC FOR LM339 IS +5V
SPARES
+
+
+
+
BATTERY/MONITOR
IQ80960RM/RN
Evaluation Board Manual B-13
Schematics
Table B-2. IQ80960RM Schematics List
Page Schematic Title
B-14 Decoupling and 3.3V Power
B-15 Primary PCI Interface
B-16 Memory Controller
B-17 Flash ROM, UART, & LEDs
B-18 Logic Analyzer I/F
B-19 SDRAM 168-Pin DIMM
B-20 Secondary PCI/960 Core
B-21 Secondary PCI Bus 1/2
B-22 Secondary PCI Bus 3/4
B-23 Battery/Monitor
12345678
12345678
A
B
C
D
A
B
C
D
TP1
1
R46
0.012
1W 1%
1 2
3
4
5
6
7
L2
3.3uH
COIL-SMT2
1 2
CR6
MBRS340T3
1 2
Q2
RFD16N05L
2
1
3
Q3
RFD16N05L
2
1
3
C60
220uF
CAPT7343
21
C75
220uF
CAPT7343
21
C78
220uF
CAPT7343
21
C93
47uF
CAPT7343
2 1 C90
47uF
CAPT7343
2 1 C91
47uF
CAPT7343
2 1
C67
0.1uF
CAP0805
2 1
C79
0.1uF
CAP0805
2 1
C85
0.1uF
CAP0805
2 1
C40
0.1uF
CAP0805
2 1
C39
0.1uF
CAP0805
2 1
C38
0.1uF
CAP0805
2 1
C37
0.1uF
CAP0805
2 1
C36
0.1uF
CAP0805
2 1
C35
0.1uF
CAP0805
2 1
C34
0.1uF
CAP0805
2 1
C33
0.1uF
CAP0805
2 1
C6
0.1uF
CAP0805
2 1
C5
0.1uF
CAP0805
2 1
C4
0.1uF
CAP0805
2 1
C14
0.1uF
CAP0805
2 1
C13
0.1uF
CAP0805
2 1
C12
0.1uF
CAP0805
2 1
C22
0.1uF
CAP0805
2 1
C21
0.1uF
CAP0805
2 1
C1
0.1uF
CAP0805
2 1
C7
0.1uF
CAP0805
2 1
C8
0.1uF
CAP0805
2 1
C9
0.1uF
CAP0805
2 1
C15
0.1uF
CAP0805
2 1
C16
0.1uF
CAP0805
2 1
C17
0.1uF
CAP0805
2 1
C23
0.1uF
CAP0805
2 1
C24
0.1uF
CAP0805
2 1
C25
0.1uF
CAP0805
2 1
C31
0.1uF
CAP0805
2 1
C32
0.1uF
CAP0805
2 1
C20
0.1uF
CAP0805
2 1
C30
0.1uF
CAP0805
2 1
C29
0.1uF
CAP0805
2 1
C28
0.1uF
CAP0805
2 1
C116
0.1uF
CAP0805
2 1
C117
0.1uF
CAP0805
2 1
C111
0.1uF
CAP0805
2 1
C113
0.1uF
CAP0805
2 1
C105
0.1uF
CAP0805
2 1
C109
0.1uF
CAP0805
2 1
C106
0.1uF
CAP0805
2 1
C108
0.1uF
CAP0805
2 1
C114
0.1uF
CAP0805
2 1
C115
0.1uF
CAP0805
2 1
C112
0.1uF
CAP0805
2 1
C107
0.1uF
CAP0805
2 1
C45
0.1uF
CAP0805
2 1
C59
0.1uF
CAP0805
2 1
C46
0.1uF
CAP0805
2 1
C70
0.1uF
CAP0805
2 1
C99
0.1uF
CAP0805
2 1
C103
0.1uF
CAP0805
2 1
C81
0.1uF
CAP0805
2 1
C72
0.1uF
CAP0805
2 1
C80
0.1uF
CAP0805
2 1
C69
0.1uF
CAP0805
2 1
C87
0.1uF
CAP0805
2 1
C73
0.1uF
CAP0805
2 1
C49
0.1uF
CAP0805
2 1
C62
0.1uF
CAP0805
2 1
C66
0.1uF
CAP0805
2 1
C42
0.1uF
CAP0805
2 1
C41
0.1uF
CAP0805
2 1
C71
0.1uF
CAP0805
2 1
C43
0.1uF
CAP0805
2 1
C48
0.1uF
CAP0805
2 1
C44
0.1uF
CAP0805
2 1
C50
0.1uF
CAP0805
2 1
C86
0.1uF
CAP0805
21
C84
0.22uF
CAP1206
21
R54
10
1/8W 5%
1 2
C83
0.01uF
CAP0805
21
C88
4.7uF
CAPT7343
21
CR9
CMPSH3
2 3
U17
MAX767CAP 17
BST
1
CS
19
DH
16
DL
20
FB
4GND1
5GND2
6GND3
7GND4
11GND5
18
LX
3ON/OFF#
13
PGND
8REF
2SS
9SYNC
10VCC1
14VCC2
15VCC3
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RM
4/14/98 01 10
+5V +5V
+5V +3V +3V +3V
+5V P33V {02,04,08,09}
RAM3V {04,06,10}
NOTE: PINS 3-7 ARE VIAS
SDRAM DECOUPLING
SPCI DECOUPLING
IC DECOUPLING
DECOUPLING & 3.3V POWER
12345678
12345678
A
B
C
D
A
B
C
D
U16
74ALS08
1
23
U16
74ALS08
4
56
U16
74ALS08
9
10 8
U16
74ALS08
12
13 11
PRIMARY PCI SIGNALS
U15
i960RM
C20
P_CLK
H3 P_IDSEL
N3 P_PAR
R2 P_C/BE0
N5 P_C/BE1
K1 P_C/BE2
H4 P_C/BE3
L1P_DEVSEL
L5P_FRAME
A7 P_GNT
E8
P_INTAD8
P_INTBE7
P_INTCC7
P_INTD
L3P_IRDY
M4P_LOCK
M3
P_PERR
E6 P_REQ
B7 P_RST
M1
P_SERR
M5P_STOP
L2P_TRDY
U1P_AD0
U2P_AD1
P1P_AD10
P3P_AD11
P4P_AD12
P5P_AD13
N1P_AD14
N2P_AD15
K3P_AD16
K4P_AD17
K5P_AD18
J1P_AD19
U3P_AD2
J2P_AD20
J3P_AD21
J5P_AD22
H1P_AD23
H5P_AD24
G1P_AD25
G2P_AD26
G3P_AD27
E5P_AD28
A6P_AD29
T1P_AD3
C6 P_AD30
D6 P_AD31
T3P_AD4
T4P_AD5
T5P_AD6
R1P_AD7
R3P_AD8
R5P_AD9
J14
CONNPCI_B
36+3V1
41+3V2
43+3V3
54+3V4
59+5V1
61+5V2
62+5V3
60ACK64#
58AD1
48AD10
47AD12
45AD14
32AD17
56AD3
55AD5
53AD7
52AD8
44C/BE1#
33C/BE2#
37DEVSEL#
34GND1
38GND2
46GND3
49GND4
57GND5
35IRDY#
39LOCK#
40PERR#
42SERR#
J14
CONNPCI_B
25+3V1
31+3V2
5+5V1
6+5V2
19+5V3
1-12V
30AD19
29AD21
27AD23
24AD25
23AD27
21AD29
20AD31
26C/BE3#
16CLK
3GND1
12GND2
13GND3
15GND4
17GND5
22GND6
28GND7
7INTB#
8INTD#
9PRSNT1#
11PRSNT2#
18REQ#
10
14
2TCK
4TDO
J15
CONNPCI_A
33+3V1
39+3V2
45+3V3
53+3V4
59+5V1
61+5V2
62+5V3
58AD0
47AD11
46AD13
44AD15
32AD16
57AD2
55AD4
54AD6
49AD9
52C/BE0#
34FRAME#
35GND1
37GND2
42GND3
48GND4
56GND5
43PAR
60REQ64#
41SBO#
40SDONE
38STOP#
36TRDY#
J15
CONNPCI_A
2+12V
21+3V1
27+3V2
5+5V1
8+5V2
10+5V3
16+5V4
31AD18
29AD20
28AD22
25AD24
23AD26
22AD28
20AD30
12GND1
13GND2
18GND3
24GND4
30GND5
17GNT#
26IDSEL
6INTA#
7INTC#
9
11
14
19
15RST#
4TDI
3TMS
1TRST#
R58
10K
1/10W 5%
1 2
R39
10K
1/10W 5%
1 2
Z3
JUMP1X2
1 2
R55
22
RNC4R8P
8
7
6
54
3
2
1
R40
22
RNC4R8P
8
7
6
54
3
2
1
U18
CY7B9910-7 13
FB
3FS
1REF
23TEST
7
Q0
8
Q1
10
Q2
11
Q3
15
Q4
16
Q5
18
Q6
19
Q7
C89
47uF
CAPT7343
21
C97
0.1uF
CAP0805
21
C98
0.1uF
CAP0805
21
C100
0.1uF
CAP0805
21
C101
0.1uF
CAP0805
21
C102
0.1uF
CAP0805
21
C104
0.1uF
CAP0805
21
C94
0.1uF
CAP0805
21
C95
0.1uF
CAP0805
21
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RM
4/14/98 02 10
PPCI
P33V
+12V
+5V N12V +5V
TD TD
PPCI PINTA#
PINTB# PINTC#
PINTD#
PRST#
+5V
PC/BE0# PINTA# PGNT#
PC/BE1# PINTB# PREQ#
PC/BE2# PINTC#
PC/BE3# PINTD# PAD31 PAD30
PAD29 P33V
PFRAME# PPERR# PAD28 PRST#
PDEVSEL# PSERR# RST# {10}PAD27 PAD26
PIRDY# PAD25
PTRDY# P33V PAD24
PSTOP# PC/BE3# PIDSEL
PIDSEL PAD23 P33V
PPAR PAD22
PREQ# PAD21 PAD20
PGNT# PAD19
RST# P33V PAD18
PLOCK#
PAD17 PAD16
PC/BE2# P33V
PFRAME#
PIRDY#
P33V PTRDY#
PDEVSEL#
PAD31
PAD30
PAD29
PAD28
PAD27
PAD26
PAD25
PAD24
PAD23
PAD22
PAD21
PAD20
PAD19
PAD18
PAD17
PAD16
PAD15
PAD14
PAD13
PAD12
PAD11
PAD10
PAD9
PAD8
PAD7
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
PAD0
PSTOP#
PLOCK# P33V
PPERR#
PSERR#
P33V PPAR
PC/BE1# PAD15
PAD14 P33V
PAD13
PAD12 PAD11
PAD10
CLK_960 PAD9
LOGIC_CLK {05} PAD8 PC/BE0#
CLK PAD7 P33V
P33V PAD6
PAD5 PAD4
PAD3
PAD2
CLKA {08} PAD1 PAD0
CLKB {08}
CLKC {09}
CLKD {09}
SPARES
PRIMARY PCI INTERFACE
12345678
12345678
A
B
C
D
A
B
C
D
R57
2.7K
1/10W 5%
1 2
TP2
1
MEMORY CONTROLLER
U15
i960RM
E21 DCLKIN
T31SBA0
T30SBA1
C21
ONCE
D22 DQ0
A23 DQ1
E27 DQ10
C28 DQ11
H32DQ12
H30DQ13
J32DQ14
J29DQ15
W29DQ16
Y32DQ17
Y30DQ18
AA32 DQ19
C23 DQ2
AA29 DQ20
AB32 DQ21
AB30 DQ22
AC32 DQ23
AC29 DQ24
AD32 DQ25
AD30 DQ26
AE32 DQ27
AE29 DQ28
AF32 DQ29
A24 DQ3
AF30 DQ30
AG32DQ31
E22
DQ32
B23
DQ33
E23
DQ34
C24
DQ35
E24
DQ36
B25
DQ37
E25
DQ38
C26
DQ39
D24 DQ4
A27
DQ40
C27
DQ41
A28
DQ42
G32
DQ43
H31
DQ44
H28
DQ45
J30
DQ46
J28
DQ47
W28
DQ48
Y31
DQ49
A25 DQ5
Y28
DQ50
AA30
DQ51
AA28
DQ52
AB31
DQ53
AB28
DQ54
AC30
DQ55
AC28
DQ56
AD31
DQ57
AD28
DQ58
AE30
DQ59
C25 DQ6
AE28
DQ60
AF31
DQ61
AF28
DQ62
AH32
DQ63
A26 DQ7
E26 DQ8
B27 DQ9
B13
RAD1
E15
RAD10
E17
RAD11
A18
RAD12
C18
RAD13
D18
RAD14
E18
RAD15
A19
RAD16
C13
RAD2/32BITMEM_EN#
E13
RAD3/RETRY
A14
RAD4/STEST
C14
RAD5
D14
RAD6/RST_MODE#
C15
RAD9
K32
SCB0
K30
SCB1
V31
SCB2
W32
SCB3
K31
SCB4
K28
SCB5
V30
SCB6
W30
SCB7
A22 DCLKOUT
A13
RAD0
E14
RAD7
A15
RAD8
B19
RALE
N30 SA0
N29 SA1
R28 SA10
T32SA11
N28 SA2
P32 SA3
P31 SA4
P30 SA5
P28 SA6
R32 SA7
R30 SA8
R29 SA9
T28SCKE0
U32 SCKE1
L29SDQM0
M32SDQM1
U30 SDQM2
U28 SDQM3
L28SDQM4
M31SDQM5
U29 SDQM6
V32 SDQM7
C19
RCE0E19
RCE1
D20
ROEA20
RWE
L30SCAS
M30SCE0
M28SCE1
N32 SRAS
L32SWE
U13
74ALS32
12
13 11
U13
74ALS32
9
10 8
U13
74ALS32
4
56
U13
74ALS32
1
23
C110
18pF
CAP0805
21
R22
30
RNC4R8P
8
7
6
5 4
3
2
1
R23
30
RNC4R8P
8
7
6
5 4
3
2
1
R37
24
1/10W 5%
12
R29
36
1/10W 5%
12
R13
1.5K
RNC4R8P
8
7
6
54
3
2
1
R41
1.5K
1/10W 5%
1 2
R42
1.5K
1/10W 5%
1 2
Z1
JUMP1X2
1 2
Z2
JUMP1X2
1 2
U9
MPC9140/CDC318
11 CLKIN
38 OE
4
OUT05
OUT1
35
OUT1036
OUT1140
OUT1241
OUT1344
OUT1445
OUT1521
OUT1628
OUT17
8
OUT29
OUT313
OUT414
OUT517
OUT618
OUT731
OUT832
OUT9
25 SCLK
24 SDA
S1
SWDIP4
1
2
3
4
8
7
6
5
R51
22
1/10W 5%
12
R50
22
1/10W 5%
12
U6
74ALS04
11 10
U6
74ALS04
13 12
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RM
4/14/98 03 10
+3V
SDRAM {05,06}
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DCLKIN
DCLKOUT DRAMCLK_LA {05}
DCLKOUT DCLK0 {06}
DCLK1 {06}
SCB7
DCLKIN SCB6
SCB5
SA11 SCB4
SA10 SCB3 DCLK2 {06}
SA9 SCB2
DCLK3 {06}
SA8 SCB1
SA7 SCB0 RAD {04,05}
SA6
SA5 ROE#
SA4 RWE#
SA3 RCE0# SDA {06,07}
SA2 RCE1# SCL {06,07}
SA1 RALE
SA0
ONCE#
SBA0 RAD16
SBA1 RAD15
SRAS# RAD14
SCAS# RAD13
SWE# RAD12
ROMA {04}SCE0# RAD11 ROMA18
SCE1# RAD10 SELUART# {04}
SCKE0 {06,10} RAD9 RCE1#
RAD8
RAD7
SM7 RAD6/RST_MODE#
SCKE1 {06,10} SM6 RAD5 IOW# {04}
RWE#
SM5 RAD4/STEST
SM4 RAD3/RETRY
SM3 RAD2/32BITMEM_EN#
SEL_LED# {04}SM2 RAD1
SM1 RAD0
SM0
IOR# {04}
DQ24
DQ19
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ23
DQ22
DQ21
DQ20
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
RAD6/RST_MODE#
RAD3/RETRY
RAD2/32BITMEM_EN# RAD4/STEST
RAD0
MEMORY CONTROLLER
12345678
12345678
A
B
C
D
A
B
C
D
R18
1.6K
1/10W 5%
12
CR4
LED GREEN LP
21
R59
10K
1/10W 5%
1 2
U11
E28F016S5
24A0
23A1
14A10
13A11
8A12
7A13
6A14
5A15
4A16
3A17
2A18
1A19
22A2
40A20
21A3
20A4
19A5
18A6
17A7
16A8
15A9
36
RY/BY
11
VPP
9CE
37OE
12
RP
38WE
25
D0
26
D1
27
D2
28
D3
32
D4
33
D5
34
D6
35
D7
Z4
JUMP1X2
1 2
R19
330
1/10W 5%
12
R17
470
1/10W 5%
12
CR3
LED RED
21
CR5
LED GREEN
21
U6
74ALS04
5 6
U6
74ALS04
3 4
U6
74ALS04
9 8
U6
74ALS04
1 2
CR1
LED4SM
87
CR1
LED4SM
21
CR1
LED4SM
43
CR1
LED4SM
65
CR2
LED4SM
21
CR2
LED4SM
43
CR2
LED4SM
87
CR2
LED4SM
65
R15
470
RNC4R8P
8
7
6
5 4
3
2
1
R16
470
RNC4R8P
8
7
6
5 4
3
2
1
U3
74ABT273
31D
42D
73D
84D
135D
146D
177D
188D
11CLK
1CLR
2
1Q5
2Q6
3Q9
4Q12
5Q15
6Q16
7Q19
8Q
U2
74ABT573
21D
32D
43D
54D
65D
76D
87D
98D
11LE
1OC
19
1Q18
2Q17
3Q16
4Q15
5Q14
6Q13
7Q12
8Q
U1
74ABT573
21D
32D
43D
54D
65D
76D
87D
98D
11LE
1OC
19
1Q18
2Q17
3Q16
4Q15
5Q14
6Q13
7Q12
8Q
J7
CONNJ6-6P
1
2
3
5
4
6
U4
OSC1.8432MHz
1E/D 5
O
U5
1488
2IN1A
4IN1B
5IN2B
9IN3A
10IN3B
12IN4A
13IN4B
3
OUTA
6
OUTB
8
OUTC
11
OUTD
U7
1489A
13
12
11
U7
1489A
10
9
8
U7
1489A
1
2
3
U7
1489A
4
5
6
U12
16C550
31A0
30A1
29A2
14CS0
15CS1
25IOR
21IOW
39RST
10
RXCLK
11
RXD
18
XTAL1
28AS
42
CD
16CS2
40
CTS41
DSR
24IOR
20IOW
43
RI
2D0
3D1
4D2
5D3
6D4
7D5
8D6
9D7
33
INT
32
RXRDY
13
TXD
27
TXRDY19
XTAL2
17
BAUDOUT
26
DDIS
37
DTR
38
OP1
35
OP2
36
RTS
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RM
4/14/98 04 10
+5V
RAD16
ROMA {03} RAD15
RAD14
RAD {03,05} RAD13
RAD12 +5V
RAD11
RAD10
RAD16 ROMA16 RAD9
RAD15 ROMA15 RAD2/32BITMEM_EN#
RAD14 ROMA14 RAD1
RAD13 ROMA13 RAD0
RAD12 ROMA12 +5V
RAD11 ROMA11 SELUART# {03}
RAD10 ROMA10
RAD9 ROMA9
RALE IOR# {03}
IOW# {03}
I_RST# {05,07} IRQUART# {07}RAD6/RST_MODE# ROMA20
RAD5 ROMA19
RAD4/STEST ROMA18
+12V
RAD3/RETRY ROMA17 +5V
ROMA20
ROMA19
ROMA18
ROMA17
RALE ROMA16 I_RST# {05,07}
ROMA15 RAD9 LED0
ROMA14 RAD10 LED1
ROMA13 RAD11 LED2
ROMA12 RAD12 LED3
ROMA11 RAD13 LED4
ROMA10 RAD14 LED5
ROMA9 RAD15 LED6
RAD8 RAD16 LED7
RAD7 SEL_LED# {03}
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
RAD6/RST_MODE#
RAD5
RAD4/STEST
+5V RAD3/RETRY RAD16
RAD2/32BITMEM_EN# RAD15
RAD1 RAD14
RAD0 RAD13
RAD12 +5V
RWE# RAD11 FAIL# {07}
RCE0# RAD10
ROE# RAD9
RAM3V {01,06,10}
P33V {01,02,08,09}
SPARES
FLASH ROM, UART, & LEDS
12345678
12345678
A
B
C
D
A
B
C
D
J12
MICTOR
4
25
24
23
22
21
20
5
6
3CLK0
36CLK1
7
8
9
10
39
GND1 40
GND2 41
GND3 42
GND4 43
GND5
11
12
13
14
15
16
17
18
19
35
34
33
32
31
30
29
28
27
26
J11
MICTOR
4
25
24
23
22
21
20
5
6
3CLK0
36CLK1
7
8
9
10
39
GND140
GND241
GND342
GND443
GND5
11
12
13
14
15
16
17
18
19
35
34
33
32
31
30
29
28
27
26
J10
MICTOR
4
25
24
23
22
21
20
5
6
3CLK0
36 CLK1
7
8
9
10
39
GND140
GND241
GND342
GND443
GND5
11
12
13
14
15
16
17
18
19
35
34
33
32
31
30
29
28
27
26
J8
MICTOR
4
25
24
23
22
21
20
5
6
3CLK0
36CLK1
7
8
9
10
39
GND1 40
GND2 41
GND3 42
GND4 43
GND5
11
12
13
14
15
16
17
18
19
35
34
33
32
31
30
29
28
27
26
J9
MICTOR
4
25
24
23
22
21
20
5
6
3CLK0
36CLK1
7
8
9
10
39
GND1 40
GND2 41
GND3 42
GND4 43
GND5
11
12
13
14
15
16
17
18
19
35
34
33
32
31
30
29
28
27
26
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RM
4/14/98 05 10
SDRAM {03,06} RAD {03,04}
DRAMCLK_LA {03}
DQ15 SM7 DQ31 RAD15
DQ14 SM6 DQ30 RAD14
DQ13 SM5 DQ29 RAD13
DQ12 SM4 DQ28 RAD12
DQ11 SM3 DQ27 RAD11
DQ10 SM2 DQ26 RAD10
DQ9 SM1 DQ25 RAD9
DQ8 SM0 DQ24 RAD8
DQ7 SCB7 DQ23 RAD7
DQ6 SCB6 DQ22 RAD6/RST_MODE#
DQ5 SCB5 DQ21 RAD5
DQ4 SCB4 DQ20 RAD4/STEST
SCE0#
DQ3 SCB3 DQ19 RAD3/RETRY
SCE1#
DQ2 SCB2 DQ18 RAD2/32BITMEM_EN#
SBA1
DQ1 SCB1 DQ17 RAD1
SBA0
DQ0 SCB0 DQ16 RAD0
LOGIC_CLK {02} RALE
DQ47 SWE# DQ63
DQ46 SCAS# DQ62
DQ45 SRAS# DQ61
DQ44 DQ60 SPCI {07,08,09} SGNT5#
DQ43 SA11 DQ59 SGNT4#
DQ42 SA10 DQ58 SGNT3#
DQ41 SA9 DQ57 I_RST# {04,07}
SGNT2#
DQ40 SA8 DQ56 SGNT1#
DQ39 SA7 DQ55 RWE#
SGNT0#
DQ38 SA6 DQ54 ROE#
SREQ5#
DQ37 SA5 DQ53 RCE1#
SREQ4#
DQ36 SA4 DQ52 RCE0#
SREQ3#
DQ35 SA3 DQ51 RALE
SREQ2#
DQ34 SA2 DQ50 SREQ1#
DQ33 SA1 DQ49 SREQ0#
DQ32 SA0 DQ48 RAD16
LOGIC ANALYZER I/F
12345678
12345678
A
B
C
D
A
B
C
D
J5
SDRAM-DIMM168P
117A1
123A11
118A3
119A5
120A7
121A9
122BA0
111CAS
105CB4
106CB5
136
CB6137
CB7
128
CKE0
125CLK1
163
CLK3
114CS1
129
CS3
85GND1
96GND2
107GND3
116GND4
127
GND5
138
GND6
148
GND7
152
GND8
162
GND9
112M4
113M5
130
M6131
M7
108NC1
147
NC10
164
NC11
109NC2
126NC4
132
NC5
134
NC6135
NC7
145
NC8146
NC9
115RAS
165
SA0166
SA1167
SA2
90VCC1
102VCC2
110VCC3
124VCC4
133
VCC5
143
VCC6
157
VCC7
168
VCC8
86DQ32
87DQ33
88DQ34
89DQ35
91DQ36
92DQ37
93DQ38
94DQ39
95DQ40
97DQ41
98DQ42
99DQ43
100DQ44
101DQ45
103DQ46
104DQ47
139
DQ48140
DQ49141
DQ50142
DQ51
144
DQ52
149
DQ53150
DQ54151
DQ55
153
DQ56154
DQ57155
DQ58156
DQ59
158
DQ60159
DQ61160
DQ62161
DQ63
J5
SDRAM-DIMM168P
33A0
38A10
34A2
35A4
36A6
37A8
39BA1
21CB0
22CB1
52
CB253
CB3
63
CKE1
42CLK0
79
CLK2
30CS0
45
CS2
9DQ6
1GND1
12GND2
23GND3
32GND4
43
GND5
54
GND6
64
GND7
68
GND8
78
GND9
28M0
29M1
46
M247
M3
24NC1
80
NC1081
NC11
25NC2
31NC3
44
NC4
48
NC5
50
NC651
NC7
61
NC862
NC9
83
SCL
82
SDA
6VCC1
18VCC2
26VCC3
40VCC4
41VCC5
49
VCC6
59
VCC7
73
VCC8
84
VCC9
27WE
2DQ0
3DQ1
14DQ10
15DQ11
16DQ12
17DQ13
19DQ14
20DQ15
55
DQ1656
DQ1757
DQ1858
DQ19
4DQ2
60
DQ20
65
DQ2166
DQ2267
DQ23
69
DQ2470
DQ2571
DQ2672
DQ27
74
DQ2875
DQ29
5DQ3
76
DQ3077
DQ31
7DQ4
8DQ5
10DQ7
11DQ8
13DQ9
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RM
4/14/98 06 10
RAM3V {01,04,10}
SDRAM {03,05}
DQ0 DQ32 SCKE0 {03,10}
DQ1 SCE0# DQ33 SCE1#
DQ2 SM2 DQ34 SM6
DQ3 SM3 DQ35 SM7
DQ4 DQ36
DQ5 DQ37
DQ6 DQ38
DQ7 SCB2 DQ39 SCB6
DQ8 SCB3 DQ40 SCB7
DQ9 DQ16 DQ41 DQ48
DQ10 DQ17 DQ42 DQ49
DQ11 DQ18 DQ43 DQ50
DQ12 DQ19 DQ44 DQ51
DQ13 DQ45
DQ20 DQ52
DQ14 DQ46
DQ15 DQ47
SCB0 SCKE1 {03,10} SCB4
SCB1 SCB5
DQ21 DQ53
DQ22 DQ54
DQ23 DQ55
SWE# DQ24 SCAS# DQ56
SM0 DQ25 SM4 DQ57
SM1 DQ26 SM5 DQ58
SCE0# DQ27 SCE1# DQ59
SRAS#
DQ28 DQ60
SA0 DQ29 SA1 DQ61
SA2 DQ30 SA3 DQ62
SA4 DQ31 SA5 DQ63
SA6 SA7
SA8 DCLK2 {03} SA9 DCLK3 {03}
SA10 SBA0
SBA1 SA11
SDA {03,07}
SCL {03,07} DCLK1 {03}
DCLK0 {03}
SDRAM 168-PIN DIMM
12345678
12345678
A
B
C
D
A
B
C
D
JX CORE/I2C/JTAG
U15
i960RM
C12
TCK A12
TDI
B11
TMS
E20 VCC5REF
C22VCCPLL1
B15 VCCPLL2
D26VCCPLL3
A21
LCDINIT
A9 NMI
B9 S_INTA/XINT0
C9 S_INTB/XINT1
E9 S_INTC/XINT2
A10 S_INTD/XINT3
C11
TRST
C10XINT4
D10XINT5
C8
SDAA8
SCL
E11
TDO
E12 FAIL
A11
I_RST
SECONDARY PCI SIGNALS
U15
i960RM
AL26S_REQ0
AH27 S_REQ1
AK27 S_REQ2
AH28 S_REQ3
AL28S_REQ4
AJ29 S_REQ5
AH14 S_AD0
AK14 S_AD1
AM17S_AD10
AH18 S_AD11
AK18 S_AD12
AL18 S_AD13
AM18S_AD14
AH19 S_AD15
AH22 S_AD16
AK22 S_AD17
AL22 S_AD18
AM22S_AD19
AL14 S_AD2
AH23 S_AD20
AJ23 S_AD21
AK23 S_AD22
AM23S_AD23
AK24 S_AD24
AL24 S_AD25
AM24S_AD26
AH25 S_AD27
AJ25 S_AD28
AK25 S_AD29
AM14S_AD3
AM25S_AD30
AH26 S_AD31
AH15 S_AD4
AJ15 S_AD5
AK15 S_AD6
AM15S_AD7
AJ17 S_AD8
AK17 S_AD9
AK19 S_PAR
AH17
S_C/BE0AJ19
S_C/BE1AM21
S_C/BE2AH24
S_C/BE3
AM20
S_DEVSEL
AK21
S_FRAMEAJ21
S_IRDY
AK20
S_LOCK
AH20
S_PERR
AM19
S_SERR
AL20
S_STOP
AH21
S_TRDY
AM26S_GNT0
AJ27 S_GNT1
AM27S_GNT2
AK28 S_GNT3
AM28S_GNT4
AK29 S_GNT5
AK26
S_RST
R14
1.5K
1/10W 5%
1 2
R36
2.7K
RNC4R8P
8
7
6
54
3
2
1
R3
2.7K
RNC4R8P
8
7
6
54
3
2
1
R44
2.7K
RNC4R8P
8
7
6
54
3
2
1
R52
100
1/2W 5%
12
J6
HEAD16SH
JTAG HEADER
1
10
11 12
13 14
15 16
2
3 4
5 6
7 8
9
R43
10
1/8W 5%
12
R30
10
1/8W 5%
12
R56
10
1/8W 5%
12
C61
0.01uF
CAP0805
21
C96
0.01uF
CAP0805
21
C77
0.01uF
CAP0805
21
C57
4.7uF
CAPT7343
21
C92
4.7uF
CAPT7343
21
C76
4.7uF
CAPT7343
21
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RM
4/14/98 07 10
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RM
4/14/98 07 10
SPCI {05,08,09}
+5V
SREQ0# SC/BE0#
SREQ1# SC/BE1#
SREQ2# SC/BE2#
SREQ3# SC/BE3#
SREQ4#
SREQ5# SFRAME#
SIRDY#
SGNT0# STRDY#
SGNT1# SSTOP# SDA {03,06}
SCL {03,06}SGNT2# SDEVSEL#
SGNT3# SSERR# +3V
SGNT4# SRST#
SGNT5# SPERR#
SLOCK# SINTA#
SPAR SINTB#
SINTC#
SINTD#
IRQFAN# {10}
IRQUART# {04}
FAIL# {04}
SAD31
SAD30
SAD29
SAD28
SAD27
SAD26
SAD25
SAD24
SAD23
SAD22
SAD21
SAD20
SAD19
SAD18
SAD17
SAD16
SAD15
SAD14
SAD13
SAD12
SAD11
SAD10
SAD9
SAD8
SAD7
SAD6
SAD5
SAD4
SAD3
SAD2
SAD1
SAD0
I_RST# {04,05}
+5V
+3V
SECONDARY PCI/960 CORE
12345678
12345678
A
B
C
D
A
B
C
D
J1
CONNPCI_32
A33
+3V1
A39
+3V2
A45
+3V3
A53
+3V4
B36 +3V5
B41 +3V6
B43 +3V7
B54 +3V8
A59
+5V1
A61
+5V2A62
+5V3
B59 +5V4
B61 +5V5
B62 +5V6
A58
AD00
B58 AD01
A57
AD02
B56 AD03
A55
AD04
B55 AD05
A54
AD06
B53 AD07
B52 AD08
A49
AD09
B48 AD10
A47
AD11
B47 AD12
A46
AD13
B45 AD14
A44
AD15
A32
AD16
B32 AD17
A35
GND1
B57 GND10
A37
GND2
A42
GND3
A48
GND4
A56
GND5
B34 GND6
B38 GND7
B46 GND8
B49 GND9
A43
PAR
A40
SDONE
B60 ACK64
A52
C/BE0
B44 C/BE1
B33 C/BE2
B37 DEVSEL
A34
FRAME
B35 IRDY
B39 LOCK
B40 PERR
A60
REQ64
A41
SBO
B42 SERR
A38
STOP
A36
TRDY
J2
CONNPCI_32
A33
+3V1
A39
+3V2
A45
+3V3
A53
+3V4
B36 +3V5
B41 +3V6
B43 +3V7
B54 +3V8
A59
+5V1
A61
+5V2A62
+5V3
B59 +5V4
B61 +5V5
B62 +5V6
A58
AD00
B58 AD01
A57
AD02
B56 AD03
A55
AD04
B55 AD05
A54
AD06
B53 AD07
B52 AD08
A49
AD09
B48 AD10
A47
AD11
B47 AD12
A46
AD13
B45 AD14
A44
AD15
A32
AD16
B32 AD17
A35
GND1
B57 GND10
A37
GND2
A42
GND3
A48
GND4
A56
GND5
B34 GND6
B38 GND7
B46 GND8
B49 GND9
A43
PAR
A40
SDONE
B60 ACK64
A52
C/BE0
B44 C/BE1
B33 C/BE2
B37 DEVSEL
A34
FRAME
B35 IRDY
B39 LOCK
B40 PERR
A60
REQ64
A41
SBO
B42 SERR
A38
STOP
A36
TRDY
J2
CONNPCI_32
A2
+12V
A21
+3V1
A27
+3V2
B25 +3V3
B31 +3V4
A5
+5V1
A8
+5V2
A10
+5V3
A16
+5V4
B5 +5V5
B6 +5V6
B19 +5V7
B1 -12V
A31
AD18
B30 AD19
A29
AD20
B29 AD21
A28
AD22
B27 AD23
A25
AD24
B24 AD25
A23
AD26
B23 AD27
A22
AD28
B21 AD29
A20
AD30
B20 AD31
B16 CLK
A12
GND1
B17 GND10
B22 GND11
B28 GND12
A13
GND2
A18
GND3
A24
GND4
A30
GND5
B3 GND6
B12 GND7
B13 GND8
B15 GND9
A26
IDSEL
A9
A11
A14
A19
B10
B14
B2 TCK
A4
TDI
B4 TDO
A3
TMS
B26 C/BE3
A17
GNT
A6
INTA
B7 INTB A7
INTC
B8 INTD
B9 PRSNT1
B11 PRSNT2
B18 REQ
A15
RST
A1
TRST
J1
CONNPCI_32
A2
+12V
A21
+3V1
A27
+3V2
B25 +3V3
B31 +3V4
A5
+5V1
A8
+5V2
A10
+5V3
A16
+5V4
B5 +5V5
B6 +5V6
B19 +5V7
B1 -12V
A31
AD18
B30 AD19
A29
AD20
B29 AD21
A28
AD22
B27 AD23
A25
AD24
B24 AD25
A23
AD26
B23 AD27
A22
AD28
B21 AD29
A20
AD30
B20 AD31
B16 CLK
A12
GND1
B17 GND10
B22 GND11
B28 GND12
A13
GND2
A18
GND3
A24
GND4
A30
GND5
B3 GND6
B12 GND7
B13 GND8
B15 GND9
A26
IDSEL
A9
A11
A14
A19
B10
B14
B2 TCK
A4
TDI
B4 TDO
A3
TMS
B26 C/BE3
A17
GNT
A6
INTA
B7 INTB A7
INTC
B8 INTD
B9 PRSNT1
B11 PRSNT2
B18 REQ
A15
RST
A1
TRST
R12
10K
1/10W 5%
12 R11
10K
1/10W 5%
12
R9
10K
1/10W 5%
12
R10
10K
1/10W 5%
12
R45
2.7K
RNC4R8P
8
7
6
54
3
2
1
R31
2.7K
RNC4R8P
8
7
6
54
3
2
1
R33
2.7K
RNC4R8P
8
7
6
54
3
2
1
R38
2.7K
RNC4R8P
8
7
6
54
3
2
1
R1
2.7K
RNC4R8P
8
7
6
54
3
2
1
C19
0.01uF
CAP0805
2 1
C18
0.01uF
CAP0805
2 1
C27
0.01uF
CAP0805
2 1
C26
0.01uF
CAP0805
2 1
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RM
4/14/98 08 10
SPCI {05,07,09}
+12V
N12V
+5V +5V +5V +5V
STRST# {09} SAD17 SAD16
STCK {09} SC/BE2# P33V {01,02,04,09}
STMS {09} SFRAME#
STDI {09} SIRDY# +5V
P33V {01,02,04,09} STRDY#
SINTA# SDEVSEL#
SINTB# SINTC# SSTOP# STMS
SINTD# SLOCK#
SPERR# STDI
STRST#
SSERR# STCK
SPAR
SC/BE1# SAD15
SAD14
SRST# SAD13
CLKA {02} SAD12 SAD11 +5V
SGNT0# SAD10 SFRAME#
SREQ0# SAD9
STRDY#
SAD31 SAD30 SIRDY#
SAD29 P33V {01,02,04,09} SAD8 SC/BE0# SDEVSEL#
SAD28 SAD7
SAD27 SAD26 SAD6
SAD25 SAD5 SAD4
P33V {01,02,04,09} SAD24 SAD3
SC/BE3# SAD16 SAD2
SAD23 +5V SAD1 SAD0 +5V
SSTOP#
SAD22
SAD21 SAD20 SSERR#
SAD19 SPERR#
SAD18 SLOCK#
+12V
N12V
STRST# {09} SAD17 SAD16
STCK {09} SC/BE2# P33V {01,02,04,09}
STMS {09} SFRAME#
STDI {09} SIRDY#
P33V {01,02,04,09} STRDY# SREQ0#
SINTB# SDEVSEL# SREQ1#
SINTC# SINTD# SSTOP#
SINTA# SLOCK# SREQ2#
SPERR# SREQ3#
SSERR#
SPAR
SC/BE1# SAD15
SAD14
SRST# SAD13 SREQ4#
CLKB {02} SAD12 SAD11 SREQ5#
SGNT1# SAD10
SREQ1# SAD9
SAD31 SAD30
SAD29 SAD8 SC/BE0#
SAD28 SAD7
SAD27 SAD26 SAD6
SAD25 SAD5 SAD4
SAD24 SAD3
SC/BE3# SAD17 SAD2
SAD23 +5V SAD1 SAD0 +5V
SAD22
SAD21 SAD20
SAD19
SAD18
SPCI CONN 2
SPCI CONN 1
SECONDARY PCI BUS 1/2
12345678
12345678
A
B
C
D
A
B
C
D
J3
CONNPCI_32
A33
+3V1
A39
+3V2
A45
+3V3
A53
+3V4
B36 +3V5
B41 +3V6
B43 +3V7
B54 +3V8
A59
+5V1
A61
+5V2A62
+5V3
B59 +5V4
B61 +5V5
B62 +5V6
A58
AD00
B58 AD01
A57
AD02
B56 AD03
A55
AD04
B55 AD05
A54
AD06
B53 AD07
B52 AD08
A49
AD09
B48 AD10
A47
AD11
B47 AD12
A46
AD13
B45 AD14
A44
AD15
A32
AD16
B32 AD17
A35
GND1
B57 GND10
A37
GND2
A42
GND3
A48
GND4
A56
GND5
B34 GND6
B38 GND7
B46 GND8
B49 GND9
A43
PAR
A40
SDONE
B60 ACK64
A52
C/BE0
B44 C/BE1
B33 C/BE2
B37 DEVSEL
A34
FRAME
B35 IRDY
B39 LOCK
B40 PERR
A60
REQ64
A41
SBO
B42 SERR
A38
STOP
A36
TRDY
J4
CONNPCI_32
A33
+3V1
A39
+3V2
A45
+3V3
A53
+3V4
B36 +3V5
B41 +3V6
B43 +3V7
B54 +3V8
A59
+5V1
A61
+5V2A62
+5V3
B59 +5V4
B61 +5V5
B62 +5V6
A58
AD00
B58 AD01
A57
AD02
B56 AD03
A55
AD04
B55 AD05
A54
AD06
B53 AD07
B52 AD08
A49
AD09
B48 AD10
A47
AD11
B47 AD12
A46
AD13
B45 AD14
A44
AD15
A32
AD16
B32 AD17
A35
GND1
B57 GND10
A37
GND2
A42
GND3
A48
GND4
A56
GND5
B34 GND6
B38 GND7
B46 GND8
B49 GND9
A43
PAR
A40
SDONE
B60 ACK64
A52
C/BE0
B44 C/BE1
B33 C/BE2
B37 DEVSEL
A34
FRAME
B35 IRDY
B39 LOCK
B40 PERR
A60
REQ64
A41
SBO
B42 SERR
A38
STOP
A36
TRDY
J4
CONNPCI_32
A2
+12V
A21
+3V1
A27
+3V2
B25 +3V3
B31 +3V4
A5
+5V1
A8
+5V2
A10
+5V3
A16
+5V4
B5 +5V5
B6 +5V6
B19 +5V7
B1 -12V
A31
AD18
B30 AD19
A29
AD20
B29 AD21
A28
AD22
B27 AD23
A25
AD24
B24 AD25
A23
AD26
B23 AD27
A22
AD28
B21 AD29
A20
AD30
B20 AD31
B16 CLK
A12
GND1
B17 GND10
B22 GND11
B28 GND12
A13
GND2
A18
GND3
A24
GND4
A30
GND5
B3 GND6
B12 GND7
B13 GND8
B15 GND9
A26
IDSEL
A9
A11
A14
A19
B10
B14
B2 TCK
A4
TDI
B4 TDO
A3
TMS
B26 C/BE3
A17
GNT
A6
INTA
B7 INTB A7
INTC
B8 INTD
B9 PRSNT1
B11 PRSNT2
B18 REQ
A15
RST
A1
TRST
J3
CONNPCI_32
A2
+12V
A21
+3V1
A27
+3V2
B25 +3V3
B31 +3V4
A5
+5V1
A8
+5V2
A10
+5V3
A16
+5V4
B5 +5V5
B6 +5V6
B19 +5V7
B1 -12V
A31
AD18
B30 AD19
A29
AD20
B29 AD21
A28
AD22
B27 AD23
A25
AD24
B24 AD25
A23
AD26
B23 AD27
A22
AD28
B21 AD29
A20
AD30
B20 AD31
B16 CLK
A12
GND1
B17 GND10
B22 GND11
B28 GND12
A13
GND2
A18
GND3
A24
GND4
A30
GND5
B3 GND6
B12 GND7
B13 GND8
B15 GND9
A26
IDSEL
A9
A11
A14
A19
B10
B14
B2 TCK
A4
TDI
B4 TDO
A3
TMS
B26 C/BE3
A17
GNT
A6
INTA
B7 INTB A7
INTC
B8 INTD
B9 PRSNT1
B11 PRSNT2
B18 REQ
A15
RST
A1
TRST
R6
10K
1/10W 5%
12 R5
10K
1/10W 5%
12
R8
10K
1/10W 5%
12 R7
10K
1/10W 5%
12
C3
0.01uF
CAP0805
2 1
C2
0.01uF
CAP0805
2 1
C11
0.01uF
CAP0805
2 1
C10
0.01uF
CAP0805
2 1
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RM
4/14/98 09 10
SPCI {05,07,08}
+12V
N12V
+5V +5V +5V +5V
STRST# {08} SAD17 SAD16
STCK {08} SC/BE2# P33V {01,02,04,08}
STMS {08} SFRAME#
STDI {08} SIRDY#
P33V {01,02,04,08} STRDY#
SINTC# SDEVSEL#
SINTD# SINTA# SSTOP#
SINTB# SLOCK#
SPERR#
SSERR#
SPAR
SC/BE1# SAD15
SAD14
SRST# SAD13
CLKC {02} SAD12 SAD11
SGNT2# SAD10
SREQ2# SAD9
SAD31 SAD30
SAD29 P33V {01,02,04,08} SAD8 SC/BE0#
SAD28 SAD7
SAD27 SAD26 SAD6
SAD25 SAD5 SAD4
P33V {01,02,04,08} SAD24 SAD3
SC/BE3# SAD18 SAD2
SAD23 +5V SAD1 SAD0 +5V
SAD22
SAD21 SAD20
SAD19
SAD18
+12V
N12V
STRST# {08} SAD17 SAD16
STCK {08} SC/BE2# P33V {01,02,04,08}
STMS {08} SFRAME#
STDI {08} SIRDY#
P33V {01,02,04,08} STRDY#
SINTD# SDEVSEL#
SINTA# SINTB# SSTOP#
SINTC# SLOCK#
SPERR#
SSERR#
SPAR
SC/BE1# SAD15
SAD14
SRST# SAD13
CLKD {02} SAD12 SAD11
SGNT3# SAD10
SREQ3# SAD9
SAD31 SAD30
SAD29 SAD8 SC/BE0#
SAD28 SAD7
SAD27 SAD26 SAD6
SAD25 SAD5 SAD4
SAD24 SAD3
SC/BE3# SAD19 SAD2
SAD23 +5V SAD1 SAD0 +5V
SAD22
SAD21 SAD20
SAD19
SAD18
SPCI CONN 4
SPCI CONN 3
SECONDARY PCI BUS 3/4
12345678
12345678
A
B
C
D
A
B
C
D
R24
100K
1/10W 5%
1 2
R32
100K
1/10W 5%
1 2
R60
10
1/10W 5%
1 2
R27
1
1/10W 5%
1 2
R28
1
1/10W 5%
1 2
R53
47K
1/10W 5%
1 2
R49
4.7K
1/10W 5%
1 2
R48
4.7K
1/10W 5%
1 2
U19
PALLV16V8-10JC
1I0
2I1
3I2
4I3
5I4
6I5
7I6
8I7
9I8
11 I9 20
VCC
12
F0 13
F1 14
F2 15
F3 16
F4 17
F5 18
F6 19
F7
U10
LM339
9+
8-
14
U10
LM339
11 +
10 -
13
U10
LM339
7+
6-
1
U10
LM339
5+
4-
2
R35
10K
1/10W 5%
1 2
C82
0.047uF
CAP0805
21
R47
2.4K
1/10W 5%
1 2
C47
22uF
CAPT7343
21
C65
0.47uF
CAP1206
21
J13
FAN CONN
1
FAN
2GND
3PWR
C63
33uF
CAPT7343
21
Q4
2N6109
1
2
3
R21
0.05
1W 1%
1 2
R20
150
1/10W 5%
1 2
R26
68K
1/10W 5%
1 2
R34
22K
1/10W 5%
1 2
BT8
BATT_HLDR
2
1
BT6
BATT_HLDR
2
1
BT1
BATT_HLDR
2
1
BT3
BATT_HLDR
2
1
BT7
BATT_HLDR
2
1
BT5
BATT_HLDR
2
1
BT2
BATT_HLDR
2
1
BT4
BATT_HLDR
2
1
CR8
CMR1-02
12
C64
330uF
CAPT7343H
21
C56
100uF
CAPT7343H
21
U8
MAX1651
2FB
8GND
4REF
3SHDN
6
CS7
EXT
1
OUT
5
V+
U14
MAX712
11CC
13GND
3
PGM04
PGM19
PGM210
PGM3
7TEMP
5THI
6TLO
1VLIMIT
2
BATT+
12
BATT-
14
DRV
16REF
15V+
8
FASTCHG
L1
47uH
1 2
7
6
5
4
3
CR7
MBRS340T3
1 2
Q1
SI9430
5
6
7
8
4
1
2
3
R25
1K
1/10W 5%
1 2
C74
1uF
CAPT3216
21
C54
10uF
CAPT7343
21
C52
10uF
CAPT7343
21
C51
0.1uF
CAP0805
21
C53
0.1uF
CAP0805
21
C58
0.01uF
CAP0805
21
C55
0.01uF
CAP0805
21
C68
0.01uF
CAP0805
21
BREV
Title:
Name:
Date:
NEW HAVEN, CT 06511
25 SCIENCE PARK
CYCLONE MICROSYSTEMS
Sheet of
80960RM
4/14/98 10 10
SCKE0 {03,06}
+12V
SCKE1 {03,06}
RST# {02}
RAM3V {01,04,06}
BATTERY
RAM3V {01,04,06}
+5V
+5V
IRQFAN# {07}
PART # 101-1950-01
NOTE: VCC FOR LM339 IS +5V
SPARES
+
+
+
+
BATTERY/MONITOR
IQ80960RM/RN
Evaluation Board Manual C-1
PLD Code C
MODULE BATT
//TITLE SDRAM Battery Backup Enable
//PATTERN 101-1809-01
//REVISION
//AUTHOR J. Neumann
//COMPANY Cyclone Microsystems Inc.
//DATE 10/30/97
//CHIP PALLV16V8Z-20JI
// 1/20/98 Modify target device to PALLV16V8Z-20JI
//Initial release.
PRSTn PIN 9;//Primary PCI reset
SCKE0 PIN 13; //SDRAM bank 0 clock enable
SCKE1 PIN 16; //SDRAM bank 1 clock enable
OUT0 PIN 14; //SCKE0 output enable
OUT1 PIN 17; //SCKE1 output enable
EQUATIONS
// If SDRAM clock enable goes low, SDRAM clock enable
// must be held low to ensure that the SDRAM is held in auto refresh mode.
// Reset going high will release the hold on SCKE.
OUT0 = SCKE0.PIN & PRSTn //SCKE is the set term, PRSTn is the reset term
# SCKE0.PIN & OUT0.PIN
# !SCKE0.PIN & PRSTn;
SCKE0 = 0;
SCKE0.OE = !OUT0; //When OUT = 0, SCKE is grounded
//When OUT = 1, SCKE is high impedance
OUT1 = SCKE1.PIN & PRSTn
# SCKE1.PIN & OUT1.PIN
# !SCKE1.PIN & PRSTn;
SCKE1 = 0;
SCKE1.OE = !OUT1;
END
IQ80960RM/RN
Evaluation Board Manual D-1
Recycling the Battery D
The IQ80960RM/RN platform contains four AA NiCd batteries. Each battery has the logo of the
Rechargeable Battery Recycling Corporation (RBRC) stamped on it. The recycling fees have been
prepaid on these batteries. Do not dispose of a rechargeable battery with regular trash in a landfill.
Rechargeable batteries contain toxic chemicals and metals that are harmful to the environment.
Improperly disposing of rechargeable batteries is also illegal. The RBRC logo on a battery is a
verification that recycling fees have been prepaid to the RBRC and such a battery can be recycled
at no additional cost to the user. The RBRC is a non-profit corporation that promotes the recycling
of rechargeable batteries, including NiCd batteries.
Information on the RBRC program and the locations of participating recycling centers can be
obtained by telephoning 1-800-8-BATTERY (in the USA), and following the recorded
instructions. The information obtained from this telephone number is updated frequently, since the
RBRC program is growing, the new recycling locations are being added regularly.

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