Intel® 64 And IA 32 Architectures Software Developer’s Manual, Volume 3C: System Programming Guide, Part 3 326019 Sdm Vol 3c Guide P2
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- Chapter 23 Introduction to Virtual Machine Extensions
- Chapter 24 Virtual Machine Control Structures
- 24.1 Overview
- 24.2 Format of the VMCS Region
- 24.3 Organization of VMCS Data
- 24.4 Guest-State Area
- 24.5 Host-State Area
- 24.6 VM-Execution Control Fields
- 24.6.1 Pin-Based VM-Execution Controls
- 24.6.2 Processor-Based VM-Execution Controls
- 24.6.3 Exception Bitmap
- 24.6.4 I/O-Bitmap Addresses
- 24.6.5 Time-Stamp Counter Offset and Multiplier
- 24.6.6 Guest/Host Masks and Read Shadows for CR0 and CR4
- 24.6.7 CR3-Target Controls
- 24.6.8 Controls for APIC Virtualization
- 24.6.9 MSR-Bitmap Address
- 24.6.10 Executive-VMCS Pointer
- 24.6.11 Extended-Page-Table Pointer (EPTP)
- 24.6.12 Virtual-Processor Identifier (VPID)
- 24.6.13 Controls for PAUSE-Loop Exiting
- 24.6.14 VM-Function Controls
- 24.6.15 VMCS Shadowing Bitmap Addresses
- 24.6.16 ENCLS-Exiting Bitmap
- 24.6.17 ENCLV-Exiting Bitmap
- 24.6.18 Control Field for Page-Modification Logging
- 24.6.19 Controls for Virtualization Exceptions
- 24.6.20 XSS-Exiting Bitmap
- 24.7 VM-Exit Control Fields
- 24.8 VM-Entry Control Fields
- 24.9 VM-Exit Information Fields
- 24.10 VMCS Types: Ordinary and Shadow
- 24.11 Software Use of the VMCS and Related Structures
- Chapter 25 VMX Non-Root Operation
- 25.1 Instructions That Cause VM Exits
- 25.2 Other Causes of VM Exits
- 25.3 Changes to Instruction Behavior in VMX Non-Root Operation
- 25.4 Other Changes in VMX Non-Root Operation
- 25.5 Features Specific to VMX Non-Root Operation
- 25.6 Unrestricted Guests
- Chapter 26 VM Entries
- 26.1 Basic VM-Entry Checks
- 26.2 Checks on VMX Controls and Host-State Area
- 26.3 Checking and Loading Guest State
- 26.3.1 Checks on the Guest State Area
- 26.3.1.1 Checks on Guest Control Registers, Debug Registers, and MSRs
- 26.3.1.2 Checks on Guest Segment Registers
- 26.3.1.3 Checks on Guest Descriptor-Table Registers
- 26.3.1.4 Checks on Guest RIP and RFLAGS
- 26.3.1.5 Checks on Guest Non-Register State
- 26.3.1.6 Checks on Guest Page-Directory-Pointer-Table Entries
- 26.3.2 Loading Guest State
- 26.3.3 Clearing Address-Range Monitoring
- 26.3.1 Checks on the Guest State Area
- 26.4 Loading MSRs
- 26.5 Event Injection
- 26.6 Special Features of VM Entry
- 26.6.1 Interruptibility State
- 26.6.2 Activity State
- 26.6.3 Delivery of Pending Debug Exceptions after VM Entry
- 26.6.4 VMX-Preemption Timer
- 26.6.5 Interrupt-Window Exiting and Virtual-Interrupt Delivery
- 26.6.6 NMI-Window Exiting
- 26.6.7 VM Exits Induced by the TPR Threshold
- 26.6.8 Pending MTF VM Exits
- 26.6.9 VM Entries and Advanced Debugging Features
- 26.7 VM-Entry Failures During or After Loading Guest State
- 26.8 Machine-Check Events During VM Entry
- Chapter 27 VM Exits
- 27.1 Architectural State Before a VM Exit
- 27.2 Recording VM-Exit Information and Updating VM-Entry Control Fields
- 27.3 Saving Guest State
- 27.4 Saving MSRs
- 27.5 Loading Host State
- 27.5.1 Loading Host Control Registers, Debug Registers, MSRs
- 27.5.2 Loading Host Segment and Descriptor-Table Registers
- 27.5.3 Loading Host RIP, RSP, and RFLAGS
- 27.5.4 Checking and Loading Host Page-Directory-Pointer-Table Entries
- 27.5.5 Updating Non-Register State
- 27.5.6 Clearing Address-Range Monitoring
- 27.6 Loading MSRs
- 27.7 VMX Aborts
- 27.8 Machine-Check Events During VM Exit
- Chapter 28 VMX Support for Address Translation
- 28.1 Virtual Processor Identifiers (VPIDs)
- 28.2 The Extended Page Table Mechanism (EPT)
- 28.3 Caching Translation Information
- Chapter 29 APIC Virtualization and Virtual Interrupts
- 29.1 Virtual APIC State
- 29.2 Evaluation and Delivery of Virtual Interrupts
- 29.3 Virtualizing CR8-Based TPR Accesses
- 29.4 Virtualizing Memory-Mapped APIC Accesses
- 29.4.1 Priority of APIC-Access VM Exits
- 29.4.2 Virtualizing Reads from the APIC-Access Page
- 29.4.3 Virtualizing Writes to the APIC-Access Page
- 29.4.4 Instruction-Specific Considerations
- 29.4.5 Issues Pertaining to Page Size and TLB Management
- 29.4.6 APIC Accesses Not Directly Resulting From Linear Addresses
- 29.5 Virtualizing MSR-Based APIC Accesses
- 29.6 Posted-Interrupt Processing
- Chapter 30 VMX Instruction Reference
- 30.1 Overview
- 30.2 Conventions
- 30.3 VMX Instructions
- INVEPT— Invalidate Translations Derived from EPT
- INVVPID— Invalidate Translations Based on VPID
- VMCALL—Call to VM Monitor
- VMCLEAR—Clear Virtual-Machine Control Structure
- VMFUNC—Invoke VM function
- VMLAUNCH/VMRESUME—Launch/Resume Virtual Machine
- VMPTRLD—Load Pointer to Virtual-Machine Control Structure
- VMPTRST—Store Pointer to Virtual-Machine Control Structure
- VMREAD—Read Field from Virtual-Machine Control Structure
- VMRESUME—Resume Virtual Machine
- VMWRITE—Write Field to Virtual-Machine Control Structure
- VMXOFF—Leave VMX Operation
- VMXON—Enter VMX Operation
- 30.4 VM Instruction Error Numbers
- Chapter 31 Virtual-Machine Monitor Programming Considerations
- 31.1 VMX System Programming Overview
- 31.2 Supporting Processor Operating Modes in Guest Environments
- 31.3 Managing VMCS Regions and Pointers
- 31.4 Using VMX Instructions
- 31.5 VMM Setup & Tear Down
- 31.6 Preparation and Launching a Virtual Machine
- 31.7 Handling of VM Exits
- 31.8 Multi-Processor Considerations
- 31.9 32-Bit and 64-Bit Guest Environments
- 31.10 Handling Model Specific Registers
- 31.11 Handling Accesses to Control Registers
- 31.12 Performance Considerations
- 31.13 Use of The VMX-Preemption Timer
- Chapter 32 Virtualization of System Resources
- 32.1 Overview
- 32.2 Virtualization Support for Debugging Facilities
- 32.3 Memory Virtualization
- 32.4 Microcode Update Facility
- Chapter 33 Handling Boundary Conditions in a Virtual Machine Monitor
- 33.1 Overview
- 33.2 Interrupt Handling in VMX Operation
- 33.3 External Interrupt Virtualization
- 33.4 Error Handling by VMM
- 33.5 Handling Activity States by VMM
- Chapter 34 System Management Mode
- 34.1 System Management Mode Overview
- 34.2 System Management Interrupt (SMI)
- 34.3 Switching Between SMM and the Other Processor Operating Modes
- 34.4 SMRAM
- 34.5 SMI Handler Execution Environment
- 34.6 Exceptions and Interrupts Within SMM
- 34.7 Managing Synchronous and Asynchronous System Management Interrupts
- 34.8 NMI Handling While in SMM
- 34.9 SMM Revision Identifier
- 34.10 Auto HALT Restart
- 34.11 SMBASE Relocation
- 34.12 I/O Instruction Restart
- 34.13 SMM Multiple-Processor Considerations
- 34.14 Default Treatment of SMIs and SMM with VMX Operation and SMX Operation
- 34.15 Dual-Monitor Treatment of SMIs and SMM
- 34.15.1 Dual-Monitor Treatment Overview
- 34.15.2 SMM VM Exits
- 34.15.3 Operation of the SMM-Transfer Monitor
- 34.15.4 VM Entries that Return from SMM
- 34.15.4.1 Checks on the Executive-VMCS Pointer Field
- 34.15.4.2 Checks on VM-Execution Control Fields
- 34.15.4.3 Checks on VM-Entry Control Fields
- 34.15.4.4 Checks on the Guest State Area
- 34.15.4.5 Loading Guest State
- 34.15.4.6 VMX-Preemption Timer
- 34.15.4.7 Updating the Current-VMCS and SMM-Transfer VMCS Pointers
- 34.15.4.8 VM Exits Induced by VM Entry
- 34.15.4.9 SMI Blocking
- 34.15.4.10 Failures of VM Entries That Return from SMM
- 34.15.5 Enabling the Dual-Monitor Treatment
- 34.15.6 Activating the Dual-Monitor Treatment
- 34.15.7 Deactivating the Dual-Monitor Treatment
- 34.16 SMI and Processor Extended State Management
- 34.17 Model-Specific System Management Enhancement
- Chapter 35 Intel® Processor Trace
- 35.1 Overview
- 35.2 Intel® Processor Trace Operational Model
- 35.2.1 Change of Flow Instruction (COFI) Tracing
- 35.2.2 Software Trace Instrumentation with PTWRITE
- 35.2.3 Power Event Tracing
- 35.2.4 Trace Filtering
- 35.2.5 Packet Generation Enable Controls
- 35.2.6 Trace Output
- 35.2.7 Enabling and Configuration MSRs
- 35.2.7.1 General Considerations
- 35.2.7.2 IA32_RTIT_CTL MSR
- 35.2.7.3 Enabling and Disabling Packet Generation with TraceEn
- 35.2.7.4 IA32_RTIT_STATUS MSR
- 35.2.7.5 IA32_RTIT_ADDRn_A and IA32_RTIT_ADDRn_B MSRs
- 35.2.7.6 IA32_RTIT_CR3_MATCH MSR
- 35.2.7.7 IA32_RTIT_OUTPUT_BASE MSR
- 35.2.7.8 IA32_RTIT_OUTPUT_MASK_PTRS MSR
- 35.2.8 Interaction of Intel® Processor Trace and Other Processor Features
- 35.2.8.1 Intel® Transactional Synchronization Extensions (Intel® TSX)
- 35.2.8.2 TSX and IP Filtering
- 35.2.8.3 System Management Mode (SMM)
- 35.2.8.4 Virtual-Machine Extensions (VMX)
- 35.2.8.5 Intel® Software Guard Extensions (Intel® SGX)
- 35.2.8.6 SENTER/ENTERACCS and ACM
- 35.2.8.7 Intel® Memory Protection Extensions (Intel® MPX)
- 35.3 Configuration and programming Guideline
- 35.3.1 Detection of Intel Processor Trace and Capability Enumeration
- 35.3.2 Enabling and Configuration of Trace Packet Generation
- 35.3.3 Flushing Trace Output
- 35.3.4 Warm Reset
- 35.3.5 Context Switch Consideration
- 35.3.6 Cycle-Accurate Mode
- 35.3.7 Decoder Synchronization (PSB+)
- 35.3.8 Internal Buffer Overflow
- 35.3.9 Operational Errors
- 35.4 Trace Packets and Data Types
- 35.4.1 Packet Relationships and Ordering
- 35.4.2 Packet Definitions
- 35.4.2.1 Taken/Not-taken (TNT) Packet
- 35.4.2.2 Target IP (TIP) Packet
- 35.4.2.3 Deferred TIPs
- 35.4.2.4 Packet Generation Enable (TIP.PGE) Packet
- 35.4.2.5 Packet Generation Disable (TIP.PGD) Packet
- 35.4.2.6 Flow Update (FUP) Packet
- 35.4.2.7 Paging Information (PIP) Packet
- 35.4.2.8 MODE Packets
- 35.4.2.9 TraceStop Packet
- 35.4.2.10 Core:Bus Ratio (CBR) Packet
- 35.4.2.11 Timestamp Counter (TSC) Packet
- 35.4.2.12 Mini Time Counter (MTC) Packet
- 35.4.2.13 TSC/MTC Alignment (TMA) Packet
- 35.4.2.14 Cycle Count (CYC) Packet
- 35.4.2.15 VMCS Packet
- 35.4.2.16 Overflow (OVF) Packet
- 35.4.2.17 Packet Stream Boundary (PSB) Packet
- 35.4.2.18 PSBEND Packet
- 35.4.2.19 Maintenance (MNT) Packet
- 35.4.2.20 PAD Packet
- 35.4.2.21 PTWRITE (PTW) Packet
- 35.4.2.22 Execution Stop (EXSTOP) Packet
- 35.4.2.23 MWAIT Packet
- 35.4.2.24 Power Entry (PWRE) Packet
- 35.4.2.25 Power Exit (PWRX) Packet
- 35.5 Tracing in VMX Operation
- 35.6 Tracing and SMM Transfer Monitor (STM)
- 35.7 Packet Generation Scenarios
- 35.8 Software Considerations