Intel® 64 And IA 32 Architectures Software Developer’s Manual Volume 2D: Instruction Set Reference 334569 Sdm Vol 2d System Programming Guide P4
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334569-sdm-vol-2d_system_programming_guide_p4
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- Chapter 6 Safer Mode Extensions Reference
- 6.1 Overview
- 6.2 SMX Functionality
- 6.3 GETSEC Leaf Functions
- GETSEC[CAPABILITIES] - Report the SMX Capabilities
- GETSEC[ENTERACCS] - Execute Authenticated Chipset Code
- GETSEC[EXITAC]—Exit Authenticated Code Execution Mode
- GETSEC[SENTER]—Enter a Measured Environment
- GETSEC[SEXIT]—Exit Measured Environment
- GETSEC[PARAMETERS]—Report the SMX Parameters
- GETSEC[SMCTRL]—SMX Mode Control
- GETSEC[WAKEUP]—Wake up sleeping processors in measured environment
- Chapter 7 Instruction Set Reference Unique to Intel® Xeon Phi™ Processors
- PREFETCHWT1—Prefetch Vector Data Into Caches with Intent to Write and T1 Hint
- V4FMADDPS/V4FNMADDPS — Packed Single-Precision Floating-Point Fused Multiply-Add (4-iterations)
- V4FMADDSS/V4FNMADDSS —Scalar Single-Precision Floating-Point Fused Multiply-Add (4-iterations)
- VEXP2PD—Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error
- VEXP2PS—Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error
- VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint
- VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint
- VP4DPWSSDS — Dot Product of Signed Words with Dword Accumulation and Saturation (4-iterations)
- VP4DPWSSD — Dot Product of Signed Words with Dword Accumulation (4-iterations)
- VRCP28PD—Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error
- VRCP28SD—Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error
- VRCP28PS—Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error
- VRCP28SS—Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error
- VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error
- VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error
- VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error
- VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating- Point Value with Less Than 2^-28 Relative Error
- VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write
- VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write
- Appendix A Opcode Map
- A.1 Using Opcode Tables
- A.2 Key to Abbreviations
- A.3 One, Two, and THREE-Byte Opcode Maps
- A.4 Opcode Extensions For One-Byte And Two-byte Opcodes
- A.5 Escape Opcode Instructions
- A.5.1 Opcode Look-up Examples for Escape Instruction Opcodes
- A.5.2 Escape Opcode Instruction Tables
- A.5.2.1 Escape Opcodes with D8 as First Byte
- A.5.2.2 Escape Opcodes with D9 as First Byte
- A.5.2.3 Escape Opcodes with DA as First Byte
- A.5.2.4 Escape Opcodes with DB as First Byte
- A.5.2.5 Escape Opcodes with DC as First Byte
- A.5.2.6 Escape Opcodes with DD as First Byte
- A.5.2.7 Escape Opcodes with DE as First Byte
- A.5.2.8 Escape Opcodes with DF As First Byte
- Appendix B Instruction Formats and Encodings
- B.1 Machine Instruction Format
- B.2 General-Purpose Instruction Formats and Encodings for Non- 64-Bit Modes
- B.3 Pentium® Processor Family Instruction Formats and Encodings
- B.4 64-bit Mode Instruction Encodings for SIMD Instruction Extensions
- B.5 MMX Instruction Formats and Encodings
- B.6 Processor ExtendeD State INstruction Formats and EncodIngs
- B.7 P6 Family INstruction Formats and Encodings
- B.8 SSE Instruction Formats and Encodings
- B.9 SSE2 Instruction Formats and Encodings
- B.10 SSE3 Formats and Encodings Table
- B.11 SSsE3 Formats and Encoding Table
- B.12 AESNI and PCLMULQDQ INstruction Formats and Encodings
- B.13 Special Encodings for 64-Bit Mode
- B.14 SSE4.1 Formats and Encoding Table
- B.15 SSE4.2 Formats and Encoding Table
- B.16 AVX Formats and Encoding Table
- B.17 Floating-Point Instruction Formats and Encodings
- B.18 VMX Instructions
- B.19 SMX Instructions
- Appendix C Intel® C/C++ Compiler Intrinsics and Functional Equivalents