39072900D_1750_Data_and_Control_Terminal_DCT_CE_Manual_Nov70 39072900D 1750 Data And Control Terminal DCT CE Manual Nov70
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CONTROL DATA® 1750
DATA AND CONTROL TERMINAL (OCT)
GENERAL' DES~RI~TION
OPERATION AND' PROG,RAMMING
THEORY OF OPERATION'
MAINTENANCE
DIAGRAMS AND PARTS LIST
j ". •
".,
WIRE LIST
CONTROL DATA
CORPORATION
HARDWARE REFERENCE/
CUSTOMER ENGINEERING MANUAL
1750 DATA AND CONTROL TERMINAL (DCT)
HARDWARE REFERENCE/
CUSTOMER ENGINEERING MANUAL
Publication No. 39072900
November 1970
CONTROL DATA CORPORATION
LA JOLLA SYSTEMS DIVISION
La Jolla, California
REVISION RECORD
REVISION
A
DESCRIPTION
Manual released
_(9/66)
B
Manual revised
{2/68)
C
(9/69)
Manual revised with the following ECO/FCOs for Equipment No. 38924100Revision F:
DS11116, DS11228, DS11264, DS11277, DS11304, DS11305,
DS11316, DS11417, DS11451, DS11455, DS11457, DS11463, DS11484,
DS11536, DS11554, DS11560, DS11594, DS11597, DS11625, DS11660,
DS11676, DS11688, DS11696, DS11764, DS11775, DS11796, DS11807,
DS11920, DS12034, DS12086, DS12107, DS12304, DS12463, DS12473,
DS12519, DS12569, DS12574, DS12579, DS12591, DS12596, DS12622,
DS12756, and DS12805.
D
(11/70)
Manual revised with the following ECO/FCOs for Equipment No. 38924100 Revision G:
DS12988 and DS12932
-
PUBLICATION NO.
39072900
ADDITIONAL COPIES OF THIS MANUAL MAY BE
OBTAINED FROM THE NEAREST CONTROL DATA
CORPORATION SALES OFFICE.
PRINTED IN THE UNITED STATES OF AMERICA
ADDRESS COMMENTS CONCERNING THIS MANUAL TO: .
CONTROL DATA CORPORATION
LAJOLLA SYSTEMS DIVISION
4455 EASTGATE MALL
LA JOLLA, CALIFORNIA
OR USE COMMENT SHEET IN THE BACK OF THIS MANUAL.
TABLE OF CONTENTS
PAGE
xi
INTRODUCTION .
Section One
GENERAL DESCRIPTION
1.1
GENERAL.
1.1
1.2
OPERATIONAL DESCRIPTION .
1.1
1.2. 1
Connect/Addressing Requirements
1. 2. 2
Addressing
1. 2. 3
Interrupt Lines .
1. 2.4
Program Protect
1.3
OPTIONS
1.3
1. 11
.
'.
1. 14
1. 14
.
1. 16
.
1. 16
1. 3.1
1574 Sequential Addressing Unit
1. 3. 2
1572 Programmable Sample Rate Unit
1. 3. 3
1573 Line Synchronized Timing Generator .
1. 17
1. 3. 4
1577 Stall Alarm
1. 17
1.4
SYSTEM OPTIONS
.
1.5
PHYSICAL DESCRIPTION.
.
1. 16
1. 17
1. 18
1. 18
1. 5.1
General
1. 5. 2
Dimensions .
1. 20
1. 5. 3
Cooling
1. 20
1..6
.
.
ELECTRICAL REQUffiEMENTS .
1. 20
1. 6.1
Power.
1. 20
1.6.2
Logic Levels
1. 20
39072900/28B
iii
TABLE OF CONTENTS (Continued)
PAGE
Section Two
OPERATION AND PROGRAMMING
2.1
2.1
GENERAL.
2.2
DATA TRANSFER OPERATIONS
.
2.1
2.2. 1
Digital Output .
2.1
2.2.2
Digital Input.
2.1
2.2.3
Analog Output .
2.2
2.2.4
Analog Input.
2.2
2.3
2.2
COMMAND FORMATS.
2.3.1
Connect/Function Commands .
2.4
2.3.2
Status and Connect
2.8
2.3.3
Data Transfer Commands
2.3.4
Sequential Operation Commands .
2.4
.
2.10
2.13
2.15
INTERRUPTS USAGE .
Section Three
THEORY OF OPERATION
GLOSSARY OF TERMS.
3.2
3.1
GENERAL.
3.4
3.2
TYPICAL DATA AND CONTROL BUS INPUT
AND OUTPUT CONFIGURATION .
3.4
3.2.1
Input Configuration
3.4
3.2.2
Output Configuration .
3.4
3.3
FUNCTIONAL DESCRIPTION
3.7
3.3.1
A-Register Interface.
3.7
3.3.2
Q-Register Receivers
3.7
3.3.3
PROTECT and EQUIPMENT NUMBER Switches.
3.7
iv
39072900/28B
TABLE OF CONTENTS (Continued)
PAGE
.
3.7
3.3.4
Response Control Logic
3.3.5
Function Control Logic
3.7
3.3.6
Interrupt Interface .
3.8
3.3.7
A-Write Line Drivers.
3.8
3.3.8
A -Read and Status Terminators
3.8
3.3.9
CiS Line Drivers
3.8
3.3.10
End of Sequence.
3.8
3.3.11
Control Line Drivers .
3.8
3.3.12
Address Decoder
3.8
3.3.13
1574 Sequential Addressing Unit
3.8
3.4
DATA AND CONTROL BUS
3.10
3.5
PROGRAM PROTECT AND EQUIPMENT NUMBER
SWITCH LOGIC (CARD 7) .
3.19
3.5.1
EQUIPMENT NUMBER Switch .
3.19
3.5.2
PROTECT Switch
3.19
3.5.3
Clear and Master Clear
3.19
3.6
A-WRITE LINE DRIVERS (CARD 8)
3.22
3.7
LINE TERMINATORS (CARD 9) .
3.24
3.7.1
A-Read Lines
3.24
3.7.2
Status Lines .
3.24
3.7.3
Interrupt Lines .
3.24
3.7.4
Q-Register Receivers.
3.24
3.7.5
Miscellaneous Logic Elements (Card 9) .
3.24
3.7.6
Miscellaneous Logic Elements (Card 11)
3.26
3.7.7
Miscellaneous Logic Elements (Card 13)
3.28
3.7.8
Miscellaneous Logic Elements (Card 15)
3.30
3.8
A-REGISTER INTERFACE
39072900/28B
3.32
v
TABLE OF CONTENTS (Continued)
PAGE
3.8.1
Receivers
3.32
3.8.2
Transmitters
3.32
3.9
FUNCTION CONTROL LOGIC (CARD 17)
3.38
3.9.1
Local Station False (LST AF)
3.38
3.9.2
Station Addresses "0" and "1"
3.38
3.10
RESPONSE CONTROL LOGIC (CARD 18)
3.43
3.10.1
Basic Response Timing.
3.43
3.10.2
Command Formats
3.44
3.10.3
Normal Response Sequence
3.45
3.10.4
Device Protect Sequence
3.46
3.10.5
Internal Reject Sequence
3.48
3.10.6
Device Rejects Execution Command Sequence
3.49
3.10.7
Device Here But Not Ready Sequence
3.50
ADDRESS CONTROL LOGIC (CARD 19) .
3.52
3.11
3.11.1
No-Address (NAD)
3.52
3. 11. 2
Station Address (STAT) .
3.52
3. 11. 3
Channel Address (CHLT)
3.52
3. 11. 4
Write Ready (WR YF) .
3.52
3. 11. 5
Q07A.
3.52
3. 11. 6
Q15F.
3.52
3.11. 7
Read Execute (REXT) and Write Execute (WEXT)
3.53
3. 11. 8
QOOA and QOOB
3.53
3. 11. 9
Simulate Response
3.53
3.11.10
Sequential Address Setup or Status (SASS).
3.53
3.11. 11
SAM1T and SAM2T
3.53
3.11. 12
Random Address and Lockup (RAL) .
3.53
3.11.13
ADD1A and ADD1B
3.54
vi
39072900/28B
TABLE OF CONTENTS (Continued)
PAGE
3.12
LONG-LINE DRIVERS (CARDS 20 AND 21) .
3.56
3.13
ADDRESS DECODER (CARD 22) .
3.60
3.13.1
No Address .
.
3.60
3.13.2
Enable Data Transfer.
3.60
3.13.3
Random Access Lockup .
3.60
3.13.4
End of Sequence.
3.60
.
.
.
Section Four
MAINTENANCE
4.1
GENERAL . . . . . . . . . . . . . . . . . . .
.
4.1
4.2
PREVENTIVE MAINTENANCE PROCEDURES.
.
4.1
4.3
TROUBLE SHOOTING PROCEDURES.
4.4
PREVENTIVE MAINTENANCE INDEX
.
.
.
.
.
.
.
4.1
4.2
Section Five
DIAGRAMS AND PARTS LIST
5.1
GENERAL.
.
5.1
Section Six
WffiE LIST
6.1
GENERAL.
APPENDIX A
39072900/D
J
6.1
INTERRUPT USAGE IN THE 1700 OPERATING SYSTEM
vii
I
LIST OF ILLUSTRATIONS
PAGE
FIGURE
1.1
SYSTEM BLOCK DIAGRAM.
1.2
RESPONSE TIMING DIAGRAM.
3.1
TYPICAL DCB INPUT CONFIGURATION
3.5
3.2
TYPICAL DCB OUTPUT CONFIGURATION
3.5
3.3
DATA AND CONTROL TERMINAL BLOCK DIAGRAM .
3.9
3.4
DCT CABLING.
.
3.11
3.5
DATA AND CONTROL BUS.
3.12
3.6
DCB CONNECTOR (CARD POSITION 2).
3.7
DCB CONNECTOR (CARD POSITION 3) .
3.8
DCB CONNECTOR (CARD POSITION 4).
3.9
DCB CONNECTOR (CARD POSITION 5) .
3.16
3.10
DCB CONNECTOR (CARD POSITION 6) .
3.17
3.11
PROTECT AND EQUIPMENT NUMBER SWITCH LOGIC
(CARD 7). . . . . . . . . .
3.21
3.12
A-WRITE LINE DRIVERS (CARD 8).
3.23
3.13
DATA AND CONTROL BUS, INTERFACE 1 (CARD 9) .
3.25
3.14
DATA AND CONTROL BUS, INTERFACE 2 (CARD 11).
3.27
3.15
DATA AND CONTROL BUS, INTERFACE 3 (CARD 13).
3.29
3.16
DATA AND CONTROL BUS, INTERFACE 4 (CARD 15).
3.31
3.17
A-REGISTER INTERFACE: BITS 12-15 (CARD 10) .
3.33
3.18
A-REGISTER INTERFACE: BITS 8-11 (CARD 12)
3.34
3.19
A-REGISTER INTERFACE: BITS 4-7 (CARD 14)
3.35
3.20
A-REGISTER INTERFACE: BITS 0-3 (CARD 16)
3.36
3.21
FUNCTION CONTROL LOGIC (CARD 17)
3.41
3.22
RESPONSE TIMING DIAGRAM.
3.43
3.23
NORMAL RESPONSE CYCLE .
3.47
3.24
DEVICE PROTECT CYCLE.
3.47
viii
.
.
.
1.2
1. 13
.
.
3.13
.
3.14
3.15
.
.
.
.
.
.
39072900/28B
LIST OF ILLUSTRATIONS (Continued)
PAGE
FIGURE
3.25
INTERNAL REJECT CYCLE .
3.48
3.26
DEVICE REJECT CYCLE .
3.49
3.27
DEVICE HERE BUT NOT READY CYCLE
3.28
RESPONSE CONTROL LOGIC (CARD 18).
3.29
ADDRESS CONTROL LOGIC (CARD 19)
3.55
3. 30
LONG-LINE DRIVERS (CARD 20)
3.57
3.31
LONG-LINE DRIVERS (CARD 21)
3.59
3.32
ADDRESS DECODER (CARD 22) .
3.61
5.1
BALANCED LINE INTERFACE (AV) CARD, BOARD LAYOUT.
5.2
5.2
RESPONSE CONTROL (BB) CARD, BOARD LAYOUT
.
5.4
5.3
ADDRESS DECODER (BE) CARD, BOARD LAYOUT.
.
5.6
5.4
PROTECT AND EQUIPMENT SELECT (BG) CARD, PANEL
ASSEMBLY . . . . . . . . . . . . . . . . .
5.5
.
3.50
3.51
.
5.8
PROTECT AND EQUIPMENT SELECT (BG) CARD, BOARD
LAYOUT
................ .
ADDRESS CONTROL (BH) CARD, BOARD LAYOUT.
5.7
DATA AND CONTROL BUS INTERFACE (BJ) CARD, BOARD
LAYOUT
. . ..
.............
5. 8
LONG-LINE DRIVERS (BM) CARD, BOARD LAYOUT
5.9
FUNCTION CONTROL (BN) CARD, BOARD LAYOUT
.
.
5.12
.
.
5.14
5.16
5. 18
LI ST OF TABLES
NUMBER
1.1
EQUIPMENT CODE ASSIGNMENTS.
1.2
DCT STATION ADDRESSES
1.3
CHANNEL ADDRESSES.
1.4
MAXIl\1UM DCT STATION AND CHANNEL ASSIGNMENTS
.
1. 10
1.5
RESPONSE CONDITIONS
.
1. 12
39072900/C
.
.
.
1.4
1.5
.
.
1.8
.
.
.
.
.
.
.
.
.
I
5.10
5. 6
.
I
ix
I
LIST OF TABLES (Continued)
PAGE
NUMBER
.
1. 15
1.6
INTERRUPT LINE ASSIGNMENTS
.
2.1
DCT COMMAND STRUCTURE
3.1
DCT SIGNAL AND PIN ASSIGNMENTS.
3.2
RESPONSE CONTROL LOGIC (CARD 18)
3.43
3.3
TYPICAL TRUTH TABLES
3.60
5.1
PARTS LIST - BALANCED LINE INTERFACE (AV) CARD .
5.3
5.2
PARTS LIST - RESPONSE CONTROL (BB) CARD
5.5
5.3
PARTS LIST - ADDRESS DECODER (BE) CARD
5.7
5.4
PARTS LIST - PROTECT AND EQUIPMENT SELECT (BG) PANEL
ASSEMBLY. . . . . . . . . . . . . . .
. ..
5.9
2. 16
.
3.10
.
5.5
PARTS LIST - PROTECT AND EQUIPMENT SELECT
5.11
5.6
PARTS LIST - ADDRESS CONTROL (BH) CARD
5.13
5.7
PARTS LIST - DATA AND CONTROL BUS INTERFACE (BJ)
CARD . . . . . . . . . . . . . . . . .
5.15
5.8
PARTS LIST - LONG-LINE DRIVERS (BM) CARD.
5.17
5.9
PARTS LIST - FUNCTION CONTROL (BN) CARD .
5.10
MODULE ASSEMBLY PARTS LIST.
x
.
.
.
.
.
.
.
5.19
.
5.20
39072900/28C
INTRODUCTION
This manual contains logic diagrams, circuit descriptions, and programming information
for the CONTROL DATA ® * 1750 Data and Control Terminal (DCT). References are made
in the text to Control Data manuals which describe invididual equipments in greater detail.
Following is a list of Control Data publications that are applicable to the DCT.
1700 MAIN FRAME MANUALS
Publication NO.
Input/Output Specification Manual
60165800
Computer Reference Manual .
60153100
System Manual . . . . . . .
60152900
1500 SERIES/MISCELLANEOUS PERIPHERAL MANUALS
1572 Programmable Sample Rate Generator . .
39070900
1573 Line Synchronized Timing Generator.
39071000
1574 Sequential Addressing Unit
39073200
1577 Stall Alarm . . .
84781600
DTL Intebrid ® Logic
84785000
*Registered trademark of Control Data Corporation
39072900/28B
xi
Section One
GENERAL DESCRIPTION
1.1
GENERAL
The CONTROL DATA 1750 Data and Control Terminal (DCT) provides the control and
interface to allow communication between the computer and CONTROL DATA® 1500
Series I/O Peripheral Equipment. If optional devices, such as the CONTROL DATA ® 1574
Sequential Addressing Unit, 1572 Programmable Sample Rate Unit, 1573 Line Synchronized
Timing Generator, and the 1577 Stall Alarm are used in the system, they are contained in
the DCT module rack.
Following are brief functional descriptions of these optional
devices. Complete descriptions of the optional equipment can be found in their respective
manuals. The remainder of this manual describes the DCT in detail.
1.2
OPERATIONAL DESCRIPTION
.The Data and Control Terminal connects to a CONTROL DATA ® 1705 Interrupt/Data
Channel and provides a specialized interface for attaching industrial control and data
acquisition equipment (see Figure 1. 1). The DCT simplifies the logical decoding task of
all devices attached to it by providing the following features which are time shared by all
devices attached to the Data and Control Bus (DCB).
a.
Computer Interface. The DCT provides party-line transmitters and
receivers for all lines to the 1705 Interrupt/Data Channel, including transmitters for all
15 interrupt lines. (Refer to publication NO. 84785000 for details on party lines.)
b. Responses. All responses to Read and Write signals from the computer are
predetermined by the DCT. No response is sent (resulting in an internal reject within the
computer after a preset delay time of 4 microseconds) if the addressed device is not in the
system or if it is too slow in acknowledging a data transfer. A Reject is sent if the addressed
device is not ready. A Reply is sent only when the operation has been executed successfully.
39072900/28B
1.1
I
TO/FROM
LOW-SPEED
DEVICES
.......
I
I
COMMON
SYNC
1704 COMPUTER
..
...
....
A/Q
CHANNEL
"
INTERRUPTS
I
I
I
1577
Ir-STALL
ALARM
I
ST ATrON ADDRESS
DEVICE
........
--
1573
LINE SYNC
LTIMIN~ENERATOR_
I
DATA AND CONTROL BUS (DCB)
FROM
OTHER
PERIPHERALS
1572
PROGRAMMABLE
SAMPLE RATE UNIT
~--DATA AND
CONTROL
TERMINAL
(DCT)
4--
0 THER
DS A
UNITS
,h
~~
-
......
....
1705 INTERRUPT/DATA CHANNEL
TO/FROM
OTHER
PERIPHERALS
T O/FROM
DIRECT STORAGE
...ACCESS (DSA)
I
--
1574
SEQUENTIAL
ADDRESSING UNIT
~ ..
...
-""
~,
.
....
STATION AND
CHANNEL DEVICE
....
....
1797
BUFFERED rio
INTERFACE
(ST ATION ADDRESS)
......
1571
CHAINING BUFFER
CHANNEL
(ST ATION ADDRESS)
....
IIIIIIII
.h
BUFFERED DATA
AND CONTROL
BUS (BDCB)
(CHANNELS)
~,
CHANNEL ADDRESS
DEVICE
1-2537
....
.....
......
BUFFERED UNITS
STATION AND
CHANNEL ADDRESSES
TO/FROM OTHER
1500 SERIES SUBSYSTEMS
FIGURE 1.1. SYSTEM BLOCK DIAGRAM
1. 2
39072900/28B
1. 2.1
Connect/Addressing Requirements
The nCT must be assigned an equipment number, usually Equipment NO. 8 or NO.9.
Equipment NO.8 is for nCT NO.1; Equipment NO.9 is for nCT NO.2. The neT is also
assigned station addresses (0 and 1).
Each device attached to the nCT is assigned a
station address andior channel addresses. A Connect command, which includes the equipment number and a station address, must be sent by the computer. A Continue command is
sent for channel addresses.
Following are brief descriptions of an equipment, station,
channel, Connect command, and Continue command.
a.
Equipment. An equipment is any device which occupies a position on the
1705 from the CONTROL nATA® 1700 Computer. A maximum of eight equipments can be
attached.
A maximum of 16 addresses (0 through F) are available.
(Refer to Table 1. 1
for recommended equipment codes.)
b.
Station.
A station is contained within an equipment. Up to 128 station
addresses are possible within the nCT.
(Refer to Table 1.2 for recommended station
assignments. )
c.
Channel. A channel is contained within an equipment.
(Refer to Table 1. 3
. for channel assignments.)
d.
Connect command.
Execution of the Connect command allows addressing of
a specific equipment and a station within that equipment.
e.
Continue command.
Execution of Continue commands allows channel Read
and Write instructions to be issued to channels within a specific equipment.
(Refer to
Section Two for Connect and Continue command formats.)
The station and channel assignments in the following tables are
recommended only.
The standard addresses listed in Tables 1. 2 and 1. 3 allow for a system equal to or less
than the maximum listed in Table 1.4. Hardware restrictions may prevent these maximums
from being realized.
39072900/28B
For systems exceeding the maximum in one or more areas, it is
1. 3
TABLE 1. 1. EQUIPMENT CODE ASSIGNMENTS
HEXADECIMAL
DESCRIPTION
EQUIPMENT CODES
o
Unassigned
1
Low-Speed I/O Equipment (e.g., 1711, 1713, 1721, 1729)
2
1731 Magnetic Tape Controller
3
1751 Drum Interface/1738 Disk Pack Controller
4
1742 Line Printer
5
1749 Communications Terminal Controller
6
Remote I/O Controller NO. 2
7
Remote I/O Controller NO. 1
8
nCT NO.1
9
DCT NO.2
A
B
C
D
E
F
1.4
39072900/28B
TABLE 1.2. DeT STATION ADDRESSES
STATION
ADDRESS
0]
01
Fixed
02
Address
03
INPUT
COMMAND
EQUIPMENT ASSIGNED
OUTPUT
COMMAND
neT
1750 Status
1750 Function
nCT
System Status
Acknowledge Interrupt
from 1573
Status
Function
Acknowledge Interrupt
1572 Programmable Sample Rate unit)
1 device
1572 Programmable Sample Rate Unit
04
05
06
07
08
09
1577 Stall Alarm
OA
1575 Llmll Compar;son unit}
DB
1575 Limit Comparison Unit
OC
1575 Limit Comparison Unit
on
1575 Limit Comparison Unit
1 device
DE
OF
10
1549 Interrupt Interface NO. 1 (00-15)
Status
11
1549 Interrupt Interface NO. 2 (00-15)
Status
Acknowledge Interrupt
12
1549 Interrupt Interface NO. 3 (00-15)
Status
Acknowledge Interrupt
Acknowledge Interrupt
13
1549 Interrupt Interface NO. 4 (00-15)
Status
14
1549 Interrupt Interface NO. 1 (00-15)
--
Set Mask
15
1549 Interrupt Interface NO. 2 (00-15)
--
Set Mask
16
1549 Interrupt Interface NO. 3 (00-15)
Set Mask
17
1549 Interrupt Interface NO. 4 (00-15)
---
18
1549 Interrupt Interface NO. 5 (00-15)
Status
19
1549 Interrupt Interface NO. 6 (00-15)
Status
Acknowledge Interrupt
lA
1549 Interrupt Interface NO. 7 (00-15)
Status
Acknowledge Interrupt
IB
1549 Interrupt Interface NO. 8 (00-15)
Status
Set Mask
Acknowledge Interrupt
Acknowledge Interrupt
lC
1549 Interrupt Interface NO. 5 (00-15)
10
1549 Interrupt Interface NO. 6 (00-15)
---
IE
1549 Interrupt Interface NO. 7 (00-15)
--
Set Mask
IF
1549 Interrupt Interface NO. 8 (00-15)
--
Set Mask
20
1547 Event Counter Interface NO. 1 (O-F)
Status
21
1547 Event Counter Interface NO. 1 (O-F)
--
22
1547 Event Counter Interface NO. 2 (O-F)
Status
23
1547 Event Counter Interface NO. 2 (O-F)
--
24
1547 Event Counter Interface NO. 3 (O-F)
Status
25
1547 Event Counter Interface NO. 3 (O-F)
--
26
1547 Event Counter Interface NO. 4 (O-F)
Status
27
1547 Event Counter Interface NO. 4 (O-F)
--
28
1547 Event Counter Interface NO. 5 (O-F)
Status
29
1547 Event Counter Interface NO. S (O-F)·
--
39072900/D
Set Mask
Set Mask
Acknowledge Interrupt
Set Mask
Acknowledge Interrupt
Set Mask
Acknowledge Interrupt
Set Mask
Acknowledge Interrupt
Set Mask
Acknowledge Interrupt
Set Mask
1.5
I
TABLE 1. 2. DCT STATION ADDRESSES (Continued)
STATION
ADDRESS
1.6
EQUIPMENT ASSIGNED
INPUT
COMMAND
2A
1547 Event Counter Interface NO. 6 (O-F)
Status
2B
1547 Event Counter Interface NO. 6 (O-F)
--
2C
1547 Event Counter Interface NO. 7 (O-F)
Status
2D
1547 Event Counter Interface NO. 7 (O-F)
--
2E
1547 Event Counter Interface NO. 8 (O-F)
Status
--
OUTPUT
COMMAND
Acknowledge Interrupt
Set Mask
Acknowledge Interrupt
Set Mask
Acknowledge Interrupt
2F
1547 Event Counter Interface NO. 8 (O-F)
30
1581/1583 Typewriter Interface NO. 1
Data
,31
1581/1583 Typewriter Interface NO. 1
Status
Function
32
1581/1583 Typewriter Interface NO. 2
Data
Data
33
1581/1583 Typewriter Interface NO. 2
Status
Function
Set Mask
Data
34
1581/1583 Typewriter Interface NO. 3
Data
Data
35
1581/1583 Typewriter Interface NO. 3
Status
Function
36
1581/1583 Typewriter Interface NO. 4
Data
Data
37
1581/1583 Typewriter Interface NO. 4
Status
Function
38
1581/1583 Typewriter Interface NO. 5
Data
Data
39
1581/1583 Typewriter Interface NO. 5
Status
Function
3A
1581/1583 Typewriter Interface NO. 6
Data
Data
3B
1581/1583 Typewriter Interface NO. 6
Status
Function
3C
1581/1583 Typewriter Interface NO. 7
Data
Data
3D
1581/1583 Typewriter Interface NO. 7
Status
Function
3E
1581/1583 Typewriter Interface NO. 8
Data
Data
3F
1581/1583 Typewriter Interface NO. 8
Status
Function
40
1581/1583 Typewriter Interface NO. 9
Data
Data
41
1581/1583 Typewriter Interface NO. 9
Status
Function
42
1581/1583 Typewriter Interface NO. 10
Data
Data
43
1581/1583 Typewriter Interface NO. 10
Status
Function
44
1581/1583 Typewriter Interface NO. 11
Data
Data
45
1581/1583 Typewriter Interface NO. 11
Status
Function
46
1581/1583 Typewriter Interface NO. 12
Data
Data
47
1581/1583 Typewriter Interface NO. 12
Status
Function
48
1558 Latching Relay Output Interface (1024)
Status
Function
49
1558 Latching Relay Output Interface (1024)
Status
Function
4A
1558 Latching Relay Output Interface (1024)
Status
Function
4B
1558 Latching Relay Output Interface (1024)
Status
Function
4C
1558 Latching Relay Output Interface (1024)
Status
Function
4D
1558 Latching Relay Output Interface (1024)
Status
Function
4E
1538 High-Speed, High-Level Analog Input Interfac3 NO. 1
Status
Function
4F
1538 High-Speed, High-Level Analog Input Interface NO. 2
Status
Function
39072900/28B
TABLE 1.2. DCT STATION ADDRESSES (Continued)
STATION
ADDRESS
EQUIPMENT ASSIGNED
INPUT
COMMAND
OUTPUT
COMMAND
50
1538 High-Speed, High-Level Analog Input Interface NO.3
Status
Function
51
1538 High-Speed, High-Level Analog Input Interface NO.4
Status
Function
52
1561 High-Speed Analog Output Interface NO. 1
Status
Function
53
1561 High-Speed Analog Output Interface NO.2
Status
Function
54
1561 High-Speed Analog Output Interface NO.3
Status
Function
1561 High-Speed Analog Output Interface NO.4
Status
Function
1530A, 1530B, or 1534 NO. 1 Analog Input Interface (1024/256)
Status
Function
S7
1530A, 1530B, or 1534 NO. 2 Analog Input Interface (1024/256)
Status
Function
58
1530A, 1530B, or 1534 NO. :3 Analog Input Interface (1024/256)
Status
Function
S9
1530A, 1530B, or 1534 NO.3 Analog Input Interface (1024/256)
Status
Function
SA
160A I/O Channel NO. 1
Status
Function
5B
160A I/O Channel NO. 2
Status
Function
60
1797 Buffered I/O Interface NO.1
Status
Start
61
1797 Buffered I/O Interface NO. 2
Status
Start
62
1797 Buffered I/O Interface NO.3
Status
Start
63
1797 Buffered I/O Interface NO.4
Status
Start
64
1797 Buffered I/O Interface NO. 5
Status
Start
65
1797 Buffered I/O Interface NO. 6
Status
Start
66
1797 Buffered I/O Interface NO.7
Status
Start
67
1797 Buffered I/O Interface NO. 8
Status
Start
68
1797 Buffered I/O Interface NO. 1
Next Address
Function
69
1797 Buffered I/O Interface NO
2
Next Address
Function
6A
1797 Buffered I/O Interface NO.3
Next Address
Function
6B
1797 Buffered I/O Interface NO.4
Next Address
Function
6C
1797 Buffered I/O Interface NO. 5
Next Address
Function
6D
1797 Buffered I/O Interface NO.6
Next Address
Function
56
5C
5D
SE
5F
6E
1797 Buffered I/O Interface NO. 7
Next Address
Function
6F
1797 Buffered I/O Interface NO. 8
Next Address
Function
70
No Address Commands
7F
No Address Commands
39072900/28B
1.7
TABLE 1.3. CHANNEL ADDRESSES
CHANNEL
ADDRESS
EQUIPMENT ASSIGNED
DIGITAL
OOO-OFF (R)
1544 Digital Input Interface: 256 words (16 controllers with
16 words each) = 4096 bits
000-07F (W)
1553 External Register Output Interface: 128 words (8 words
per controller) = 128 DAC's or 2048 contact closure outputs
less 2 words for each digital display
080-1FF (W)
1558 Latching Relay Output Interface: 384 words (64 words per
controller) = 384 DAC' s or 6144 contact closure outputs.
Each DAC relay module (16 DAC's) requires 16 words, and
each contact closure relay module (128 contact closures)
requires 8 words even if the modules are partially filled.
Assign the least significant addresses to the DAC' s.
200-27F (R & W)
1547 Event Counter Interface: 16 counters per controller for
8 controllers = 128 counters
3FE
Not As signed
3FF (R & W)
160A I/O Channel
100-IFF (R)
Not Assigned (256)
280-3FD (R & W)
Not Assigned (382)
1.8
39072900/28B
TABLE 1. 3.
CHANNEL
ADDRESS
CHANNEL ADDRESSES (Continued)
EQUIPMENT ASSIGNED
LOW-SPEED ANALOG
800-BFF
1530A, 1530B, or 1534 Analog Input Interface NO.1: (1024 points)
256 or 1024 per controller
COO-FFF
1530A, 1530B, or 1534 Analog Input Interface NO.2: (1024 points)
256 or 1024 per controller
HIGH-SPEED ANALOG
400-7FF (R)
1538 High-Speed, High-Level Analog Input Interface: (1024 points)
256 per controller
400-7FF (W)
1561 High-Speed Analog Output Interface: (1024 points) 256 per
"
controller for 4 controllers = 1024
39072900/28B
1.9
TABLE 1.4. MAXIMUM DCT STATION AND CHANNEL ASSIGNMENTS
QUANTITY
EQUIPMENT
4096
Digital inputs
6144
Latching contact closure outputs or 384 latching DAC outputs or
a combination
2048
External register relay outputs or 128 DAC outputs less two
words/digital display or a combination
128
Event counters
128
External interrupts
12
2048
Analog input relay multiplexer channels
1024
1538 High-Speed, High-Level Analog Input Interface channels
1024
1561 High -Speed DAC Output Interfaces
1
1577 Stall Alarm
1
1573 Limit Comparison Unit (optional)
1
1572 Programmable Sample Rate Unit (optional)
1
1797 Buffered I/O Interface
2
160A I/O Channels
10
382
1.10
I/O typewriters
Unassigned station addresses
Unassigned channel addresses
39072900/28B
recommended that additional devices be assigned in the unassigned areas, even though
addresses for a particular class of equipment may not be contiguous.
All responses to Read or Write signals from the computer through the 1705/DCT interface
are controlled by the response control logic of the DCT. Conditions existing either at the
DCT or at devices connected to the Data and Control Bus (DCB), determine the response
to the Read or Write signal. The response conditions are arranged in Table 1.5 in order of
precedence. The condition with the highest order of precedence determines the response,
and all lower precedence conditions are ignored.
A device must be installed in the system (Here) and available (Ready) at the time of
receipt of a Read or Write command. If either of these conditions is not established at the
start of a Read or Write pulse or if a protect fault exists, the command is not executed.
The device acknowledges receipt of the Read or Write execute signal from the DCT by
dropping its ready line. If the ready line does not drop within 2 microseconds after the
leading edge of the Read or Write pulse, no response is sent to the computer.
If the computer receives a Reply or a Reject or if no response has been received prior to
the end of the Internal Reject delay time, the computer drops the Read or Write Ready input
to the DCT and the response logic is cleared allowing the response control logic of the DCT
to reset to the Ready state for the next input/output command. Timing of responses is
determined by fixed delays with the response control logic.
The basic response timing is
summarized in Figure 1. 2.
1.2.2
Addressing
All addresses are partially decoded in the DCT for easy recognition by connected devices.
The Address Decoder is designed to decode the least Significant bits (QO through Q11) of the
address; this is done by binary decoding of the bits, two at a time, to form four addressing
signals for each two bits. If the 1574 Sequential Addressing Unit is installed, the Address
Decoder (Card 22) must be removed. The 1574 can be instructed to increment the address
39072900/28B
1.11
TABLE 1. 5 RESPONSE CONDITIONS
PRECEDENCE
CONDITION
RESPONSE
1
Not connected and not a Connect command
None
2a
Unprotected command and PROTE CT switch in position 2
Reject
2b
Unprotected command and PROTE CT switch in position 3
Reply and
Interrupt
3a
Addressed device Here and Ready:
Generate REX or WEX and wait 2 I1sec from
leading edge of Read or Write, then:
If Ready drops in time and RJT is false
Reply
If Ready drops in time and RJT is true
Reject
If Ready does not drop in time
None
3b
Addressed device Here but not Ready
Reject
3c
Addressed device not Here
None
4
1574 Sequential Addressing Unit not in system:
Sequential Setup or Sequential Status command
None
Random Address command in mode 2 or 3
Reject
Any No-Address command
Reject
5a
Station Address 00 and Write (set DCT functions)
Reply
5b
Station Address 00 and Read (present DCT status)
Reply
5c
Station Address Oland Write (1573 Line Synchronized
Timing Generator):
5d
If 1573 not in system
None
If 1573 interrupt sent
Reply
If 1573 interrupt not sent
Reject
Station Address Oland Read (present system status)
Reply
NOTE: Cases 4 and 5 are special cases of 3.
1.12
39072900/28B
I
Q-REGISTER LINE
0.1 Ilsec
_ _ ~MAXIMUM
I
I
~
L ___ _
I
I
I
: 11-------11
..
ADDRESS LINES
I
7
READ HERE (RHR) OR
WRITE HERE (WHR)
__ ....I
7
READ READY (RRY) OR
WRITE READY (WRY)
...J
I
I
I
:
,1
II L
/ I
~
1. 0 Ilsec MAXIMUM
L-_
__
_
r-1 jl
/
0.45 Ilsec MAXIMUM
/
I
i
I
REPLY
A
/ I
I
V
:·_·V
...J
--I-
I
I
~
\
I
I
--------- I
READ EXEC UTE (REX) OR
WRITE EXEC UTE (WEX)
0.5 Ilsec
MAXIMUM
I
I
READ OR WRITE
\
/
/
I
/ \_. .:
. --\ I
t I
~~I
__
I
I
~~I
-
NOTES:
A REJECT IS SENT INSTEAD OF A REPLY IF RJT IS TRUE WHEN READY DROPS.
A REJECT IS SENT INSTEAD OF AN EXECUTE IF THE ADDRESSED DEVICE IS HERE AND NOT READY.
NO RESPONSE IS SENT IF THE ADDRESSED DEVICE IS NOT HERE.
NO RESPONSE IS SENT IF READY DOES NOT DROP IN TIME (WITHIN 4.0 fLSEC OF READ OR WRITE).
ADDRESS BEING INCREMENTED FOR SEQUENTIAL OPERATION (NO-ADDRESS COMMAND ONLY).
1-1347B
FIGURE 1.2. RESPONSE TIMING DIAGRAM
39072900/C
1. 13
after each data transfer and to cycle repeatedly between programmed first and last
addresses. The CONTROL DATA® 1797 Buffered I/O Interface/1571 Chaining Buffer
Channel system (optional equipment) contains its own incrementing logic. A brief description of these options can be found at the end of this section.
1.2.3
Interrupt Lines
Fifteen interrupt lines are available for use by the nCT and all devices connected to the
nCB. The priority of the interrupt lines is controlled by the computer program by use of
the interrupt mask. The interrupt line(s) of any device can be connected to any interrupt
line (01 through 15) by proper installation of jumpers on the interrupt plugboard of the
device. No control or inhibit of the interrupts from devices connected to the nCB is maintained by the nCT, except for the interrupt status of the nCT. Provision for jumpering
interrupts from options housed in the DCT module (refer to Section Three) is available on
card position 5.
The basic 1705 Interrupt/Data Channel transfers the address information to the nCT on the
Q-register lines and inputs or outputs data on the A-register lines. nata is input or output
upon Read or Write commands issued by the computer on the A-Read or A-Write lines,
respectively.
Table 1.6 lists the recommended line assignments. These assignments may be changed to
meet particular system requirements.
1.2.4
Program Protect
The nCT and all other devices connected to the nCT contain a three-position PROTECT
switch. The switch positions are labeled and function as follows:
a. OFF (Posi!ion 1). The Program Protect bit is ignored, no protect faults
are recognized, and the Program Protect status bit is false.
b. REJE CT (Position 2). A Reject signal is transmitted if the command is not
protected, and the faulting
1. 14
comm~nd
is not executed.
39072900/28B
TABLE 1.6. INTERRUPT LINE ASSIGNMENTS
lNTERRUPT LINE
NUMBER
EQUIPMENT
o
Memory Protect/Parity
1
Low-Speed I/O
2
1573 Line Synchronized Timing Generator
3
1731 Magnetic Tape Controller
4
1751 Drum Interface/1738 Disk Pack Controller
5
1749 Communications Terminal Controller
6
1584 I/O Typewriter
7
1545 Digital Input Sync Unit
8
1530/1534 Analog Input Interface
9
1558 Latching Relay Output Interface
10
1547 Event Counter Interface
11
Unassigned
12
Unassigned
13
Unassigned
.14
Unassigned
15
Unassigned
39072900/28B
1. 15
c.
INTERRUPT (Position 3). A Reply signal is transmitted if the command is not
protected, but the faulting command is not executed, and the interrupt output becomes true.
1.3
OPTIONS
The DCT module provides. space for the addition of up to three optional units.
While these
do not form a part of the DCT itself, they occupy the same module as the DCT. The units
are the 1574 Sequential Addressing Unit, 1572 Programmable Sample Rate Unit, 1573 Line
Synchronized Timing Generator, and the 1577 Stall Alarm.
1. 3.1
1574 Sequential Addressing Unit
This unit provides automatic scanning of channel addressing and is an alternate replacement unit for the Address Decoder.
The 1574 and the Address Decoder are controlled by
common Signals and perform similar, but not identical, functions; they cannot both be used
with the same DCT.
The 1574 must be provided with a first channel address (FCA) and a
last channel address plus one (LCA) , which are specified by the program.
A counter in the
1574 starts at the first channel address and is successively incremented until the last channel
address is reached. The counter then recycles, starting again at the first channel address.
Random Address commands can be executed to sample a single address without disturbing
the sequence, and a sequence can be modified to skip or repeat a group of channels at any
time under the program control.
1. 3. 2
1572 Programmable Sample Rate Unit
The 1572 Programmable Sample Rate Unit can be operated either as an elapsed:...time
accumulator or as an interval generator.
In the Elapsed -Time mode, it accumulates
counts from a time base, and the counter is examined under program control.
In the
Interval mode, the program specifies a count value, and the 1572 accumulates the time
base until the specified count value is reached; at this point an interrupt is generated.
1.16
39072900/28B
A timing signal is also generated and distributed to the peripherals via the DCB. The 1572
obtains its time base from the 1573 Line Synchronized Timing Generator, a self-contained
oscillator, or an external source.
1. 3. 3
1573 Line Synchronized Timing Generator
The 1573 Line Synchronized Timing Generator provides a timing pulse output and interrupts
at selectable frequencies between 60 Hz and 7680 Hz that are multiples of and synchronous
with the 60 Hz power line. The interrupt can be used to initiate computer programs. The
timing pulse can be used by the 1572 Programmable Sample Rate Unit or by other peripheral devices.
1.3.4
1577 Stall Alarm
The 1577 Stall Alarm detects system malfunctions caused by nonterminating loops or
similar errors in the computer program; it also detects power failures.
The stall alarm
contains a "watchdog timer" that must be periodically reset by the computer program by
means of a function command. If the program fails to reset the timer within a given
. period, the 1577 produces a Stall condition. A Stall condition causes a computer interrupt,
actuates an audible alarm, produces a contact closure for controlling external equipment,
and may inhibit further data transfers to some of the I/O systems. In the case of a power
failure, the 1577 causes an interrupt to inform the computer of the failure.
1.4
SYSTEM OPTIONS
The 1571 Chaining Buffer Channel is a system option that is used in conjunction with the
1797 Buffered I/O Interface. The 1571 is similar to the 1574 Sequential Addressing Unit in
that it also provides automatic sequential channel addressing. The 1571, however, can be
operated in a Buffered or Nonbuffered mode. The Buffered mode is via the Direct Storage
Access (DSA) bus, and the Nonbuffered mode is via the A/Q channel and the DCB. If a
1571 is used in the system, a 1574 is not used.
39072900/28B
1. 17
1.5
PHYSICAL DESCRIPTION
1. 5.1
General
The DCT is contained within a standard Control Data 19 -inch module.
The module provides
connectors and card guides for the DCT and for the following additional logic units (see
Figure 1. 3 for a card position diagram) :
a. Address Decoder (standard for the DCT) .
b.
1572 Programmable Sample Rate Unit.
c.
1573 Line Synchronized Timing Generator.
d.
1574 Sequential Addressing Unit.
e.
1577 Stall Alarm.
The card connectors are numbered from left to right, 01-42, as viewed from the front of
the module.
The connector pins are numbered from top to bottom, 01-50. Assignment
and wiring of the connectors for the units listed above are as follows:
a.
Connectors 02, 04, 06
U sed as cable connectors for the DCT (DCB).
b.
Connector 05
U sed to jumper interrupts from within DCT
module to desired interrupt lines.
c. Connectors 07 -21
Contain the D CT logic cards.
d.
Connector 22
Contains the Address Decoder card (if used) .
e. Connectors 23 -28
Contain the 1574 Sequential Addressing Unit
(if used).
f.
Connectors 29-31
Spare connectors.
g.
Connectors 32 -33
Contain the 1573 Line Synchronized Timing
Generator (if used) .
h.
Connectors 34-39
Contain the 1572 Programmable Sample Rate
Unit (if used) .
1. 18
i.
Connector 40
Spare connector.
j.
Connector 41
Oscillator card (1572).
k.
Connector 42
Contains stall alarm logic.
39072900/28B
.~
01
02
1577 St:lll Al:1rm .Tu IT
03
Je "ts
DCB
O~
Option Interrupt Jumpers
05
06
(~~
(
,:
Protect and Equipment Select (BG) Card
Long-Line Driver (BM) Card
Data and Control Bus. Interface 1 (BJ) Card
Balanced Line Interface (A V) Card
Data and Control Bus. Interface 2 (BJ) Card
Balancen Line Interface fA V) Card
Data and Control Bus. Interface 3 (BJ) Card
Balanced Line Interface (A V) Card
Data and Control Bus Interface 4 (BJ) Card
Balanced Line Interface (A V) Card
Function Control (BN) Card
Resnonse Control (BB) Card
Address Control (BID Card
Long-Line Driver (BM) Card
Lonl!-Line Driver (BM) Card
Address Dp(>()npr (BE) Card*
Seauence Control (BP) Card
Counter (BQ) Card
Counter (BQ) Carn
......
DCT
t
\\
16
17
\
19
\
20
'"
21
'\
\
22
~~
23
26
~()l1nt~r
28
r.()l1ntpr fRO\ r.:lrn
Counter (BQ) Card
IHc)\
~~rn
1574
(optional)
29
)0
35
36
37
38
39
Oscillator (CA) Card
Counter (CB) Card
Counter and Comnarator (CM) Card
r.onntAr and r.omn:lrator (CM) Card
Counter and Comparator (CM) Card
Counter and Comparator (CM) Card
Control No. 2 Timer (DY) Card
Control No. 1 Timer (DX) Card
1573
(optional)
1572
(optional)
~o
~
1
G
Oscillator (P A) Card
1577 St~ 11 A 1~ rl'n IHP\ earn
{f'",+~" ... "
1\
* Remove Card 22 before installing a 1574 unit.
FIGURE 1.3.
39072900/28B
CARD LOCATION DIAGRAM
1. 19
1.5.2
Dimensions
Width
Standard 19 -inch RETMA relay rack mounting
Height
Standard 7 -inch RETMA relay panel
Depth
16 inches
Weight
35 pounds
1. 5.3
Cooling
Cooling for the module is provided by fans mounted in the rack. All operating specifications
are met with an ambient air temperature of 40°F. to 120°F. and a relative humidity of
o percent to
95 percent excluding conditions where condensation takes place in and on the
equipment in the form of water and/or frost.
1.6
ELECTRICAL REQUffiEMENTS
1.6.1
Power
Two integral power supplies are included in the module. Primary power to these supplies
-is 208V, 3-phase, 400-Hz which is provided by a self-contained MG set or is customer
supplied. Power supplied to the printed circuit cards is ground, + 6 volts, and -
~
volts.
The + 6 VDC and ground lines are distributed by bus bars. The -6 VDC is wired from
connector to connector using wire-wrap techniques. The back plane (chassis) is also used
for ground, and pins 2 and 50 of each connector are connected directly to the ground plane.
Supplied by a cable from the computer is ±20 volt terminator power for the computer interface.
1.6.2
Logic Levels
Logic levels within the DCT are as follows:
False or "0"
True or "1"
39072900/28B
= +0.9 to +1. 1 VDC
= +1. 8 to +3. 0 VDC (nominal)
1. 20
Section Two
OPERATION AND PROGRAMMING
2.1
GENERAL
The Data and Control Terminal is programmed using the Input-to-A and Output-from-A
commands. For the programming descriptions following, it is assumed that the programmer is familiar with CONTROL DATA 1700 Computer System programming formats and
all general 1700 programming procedures. For further information on programming, refer
to the CONTROL DATA 1700 Computer Reference Manual and System Manual.
2.2
DATA TRANSFER OPERATIONS
There are four types of data transfer operations: digital output, digital input, analog output,
and analog input. Any of these can be executed using Random Address commands or, if the
1574 Sequential Addressing Unit is present, No Address commands can be used.
2.2.1
Digital Output
A digital output consists of transferring one 16 -bit word which can be used as a binary
quantity, in the form of 16 discrete "0" or "1" values or any combination thereof.
The
combination is determined only by the output's use by equipment external to this system.
The 16 bits are usually stored in flip-flops or relays in a digital output unit or in external
equipment.
2.2.2
Digital Input
A digital input can be any combination of binary values and discrete bits making up the 16 -bit
word. Each bit or group of bits meaning is determined only by the source of information.
39072900/28B
2.1
2.2.3
Analog Output
An analog output is similar to a digital output, except that the significant bits are stored in
the holding register of a digital-to-analog converter. The command is rejected if a conversion is in progress at the time.
2.2.4
Analog Input
Analog input operations require more sophisticated programming techniques because an
analog-to-digital (A/D) conversion takes longer than the 4 microseconds allowed by the
computer. The data transferred when an analog input command is executed is the result of
the previous A/D conversion. The command is rejected if a conversion is in progress at
the time. Another A/D conversion is started at the specified address except when the input
command is a Random Address command with mode equal to "0" or a No-Address command
with a "1" in bit
2.3
o.
COMMAND FORMATS
In general, command formats recognized by the DCT are analogous to those used by other
equipments connected to the computer (refer to the Computer Reference Manual). Accordi~gly, f~ur
command formats are possible on the A/Q channel, i. e., Connect/Function,
Status and Connect, Data Transfer, and Sequential Operations. The function and status bit
assignments for the DCT and associated equipment are summarized below.
2.2
39072900/28B
15 14 13 12 11 10 9
8
7
6
5
4
3 2
1
0
A-Register
1
t
Enable 1573 Interrupt
Disable 1573 InterruptEnable 1573 Output to
Sync 1 Line
Disable 1573 Output from
Sync 1 Line------~
Enable External Sync to Sync 2 Line
Disable External Sync from Sync 2 Line
Not Used
Clear DCT Analog-toDigital Controllers
Reset Protect Fault Interrupt
Reset End -of -Sequence Interrupt
Reset External Sync Interrupt
Disable End -of -Sequence Interrupt
Enable End-of-Sequence Interrupt
Disable External Sync Interrupt
Enable External Sync Interrupt
NotUsed--------------------------~
FUNCTION WORD BIT ASSIGNMENTS (STATION 00 OUTPUT)
10 9
15
8
7
6
5
4
3 2
1
0
Not
A-Register
Assigned
t
Ready
Protect Fault Interrupt
End-of-Sequence Interrupt (1574)
External Sync Interrupt
Line Synchronized Timing Interrupt
(1573)
1574 Present in System
1573 Present in System
External Sync Enabled to Sync 2 Line
Protected
End-of-Sequence 1574
STATUS WORD BIT ASSIGNMENTS (STATION 00 INPUT)
39072900/28B
2.3
3
15
2
1
0
Not Assigned
A-Register
f
Inte rrupt present (1572)
Interru pt (stall condition,
1577)
Interrupt (power failure, 1577)
STATUS WORD BIT ASSIGNMENTS (STATION 01 INPUT)
2.3.1
Connect/Function Commands
When the contents of the Q-register conform to the format for a Connect command as shown
below, the contents of the A -register control the functions of the DCT.
For Function and
Connect commands, the W -field must be "0", and the station address must be "0" to
address the DCT. The E-field must contain the equipment number of the DCT.
The DCT
contains a thumbwheel switch for setting the equipment number (usually set to equipment
NO. 8 'for DCT NO. 1 and equipment NO.9 for DCT NO.2). When an Output-from-A
command is executed under these conditions, Function and Connect command is executed.
15
11 10
Converter
Address (W)
Q-Register
7
Equipment
Number (E)
o
6
Station Address (S)
o
15
A-Register
Assigned Function Bits
CONNECT /FUNCTION COMMAND FORMAT
2.4
39072900/28B
When the Connect/Function command is executed, the equipment number in the E -field sets
the Connect flip-flop in the DCT and connects the DCT to the computer. A data transfer
cannot take place unless the DCT is connected. The Connect flip-flop stays set regardless
of the number of new Connect commands as long as the E -field contains the equipment
number of the DCT (8 or 9) and the station address is for the DCT or one of the attached
devices. The Connect flip-flop is reset by any Connect command addressed to an equipment
other than the DCT. The Connect flip-flop is not reset by a clear function.
When the computer executes the Output-from-A instruction, the bits in the A-register
control the functions of the addressed station.
Refer to the appropriate module manuals for
function bit assignments.
STATION ADDRESSES
Bits 0 through 6 of a Connect command are defined as a station address. Station addresses
are used to communicate with subsystem interfaces and other devices connected directly to
the DCT. Station address 00 is reserved for commands (function and status) directed to the
DCT itself.
Execution of an input to station 01 is used to input status from the 1572 and 1577.
Execution
of an output to station address 01 is used to acknowledge an interrupt from the 1573. The
A-register is not used for this operation. No response is sent if the 1573 is not present.
A Reply is sent if the 1573 is present, has sent an interrupt, and the interrupt is reset.
A Reject is sent if the 1573 is present but has not sent an interrupt.
Station addresses 02 and 03 are reserved for use by the 1572 option within the DCT module.
Station addresses 60 through 6F (hexadecimal) are reserved for use by devices connected
to the 1797 Buffered I/O Interface.
The values 70 through 7F are not allowed as station addresses because of the restriction
that a command with a "1" in bits 4, 5, and 6 is a No Address Data Transfer command.
39072900/28B
2.5
The remaining 92 station addresses, 04 through 5F (hexadecimal), are reserved for assignment to individual stations connected to the DCT.
FUNCTION CODES
Clear DCT Analog-to-Digital Subsystems Controller (AO = "1.")
This code clears all interrupt selections and signals, error indications, and other clearable
conditions. It cannot be used in conjunction with other function codes. This is the same as
a Master Clear, except that the DCT is connected.
Clear Protect Fault Interrupt (AI
=
"1")
This code clears the interrupt signal generated by a protect fault.
The code can be used in
conjunction with other function codes. This interrupt can also be reset by clearing the
controller or by a Master Clear ..
Clear End-of-Sequence Interrupt (A2 = "1")
This code clears the interrupt signal generated by the completion of a sequential addressing
operation by the 1574 option. This interrupt can also be reset by clearing the controller or
by a Master Clear.
Clear External Sync Interrupt (A3 = "1 If)
This code clears the interrupt received from an external synchronizing source.
Disable End-of-Sequence Interrupt (A4
= "1")
This code disables the interrupt sent by the 1574 upon completion of an addressing sequence.
The interrupt is prevented from reaching the computer, but bit 8 of the DCT status is set
by End of Sequence.
2.6
39072900/28B
Enable End-of-Sequence Interrupt (A5 = "1")
This code enables the interrupt sent by the 1574 at the end of a sequence. The interrupt is
sent to the computer, and bits 2 and 8 of the DCT status are set.
Disable External Synchronizing Interrupt (A6
= "1")
This code disables the interrupt sent by an external synchronizing source. The interrupt is
prevented from reaching the computer, but bit 3 of the DCT status is set.
Enable External Synchronizing Interrupt (A7 = "1")
This code enables the interrupt generated by an external synchronizing source. The interrupt is sent to the computer, bit 3 of the DCT status is set, and a signal mayor may not be
sent on the SYNC2 line of the DCB depending on whether or not that signal is enabled or
disabled.
Disable External SYNC from SYNC2 Line (A10 = "1")
This code prevents the transmission of a signal received from an external synchronizing
source to the SYNC2 line of the DCB.
Enable External SYNC to SYNC2 Line (All = "1")
This code enables an external sync signal to be transmitted on the SYNC2 line of the DCB.
Disable 1573 Output from SYNC1 Line (A12 = "1")
This code prevents the transmission of a signal received from a 1573 Line Synchronized
Timing Generator to the SYNC1 line of the DCB.
Enable 1573 Output to SYNG1 Line (A13 = "1")
This code enables the signal from a 1573 to be transmitted on the SYNC1 line of the DCB.
39072900/28B
2.7
Disable 1573 Interrupt (A14 = "1")
This code disables the interrupt sent by the 1573. The interrupt is prevented from reaching
the computer, but bit 4 of the DCT status is set.
Enable 1573 Interrupt (A15 = "1")
This code enables the interrupt sent by the 1573. The interrupt is sent to the computer,
and bit 4 of the DCT status is set.
2.3.2
Status and Connect
When the contents of the Q-register conform to the format for Function and Connect
commands, the status of the DCT is loaded into the A -register when an Input-to-A command
is executed. For Status and Connect commands, the W-field must be 00, the station must
be 00, and the E -field must contain the equipment number of the DCT.
Execution of this command connects the DCT to the computer.
If station address bits are present when the computer executes the Input-to-A instruction,
the status of the addressed station is loaded into the A -register. Refer to the appropriate
manuals for status word bit assignments for particular units (stations).
STATUS CODES (STATION 00)
DCT Ready (AO
= "1")
The DCT is always Ready, i. e., any allowable operation can be performed on request,
except while being reset by a Master Clear. Thus, this bit is always set in the status word
except when the MASTER CLEAR button on the DCT is depressed.
2.8
39072900/28B
Protect Fault Interrupt (AI
= "1 If)
Bit Al is set whenever an unprotected I/O command is received by the DCT and the
PROTECT switch is in position 3. An interrupt is generated and a Reply is sent; however,
no other action is taken. This bit is cleared when the interrupt signal is cleared.
End-of-Sequence Interrupt (A2
= "1")
Bit A2 is set when the 1574 has generated an interrupt upon completion of an addressing
sequence, the interrupt was enabled, and the interrupt has not been acknowledged.
External Sync Interrupt (A3 = If 1If)
Bit A3 is set when a synchronizing interrupt has been received by the DCT from an external
sync source. Bits in the station 00 function word enable an external sync signal to cause an
interrupt and/or cause the signal to be transmitted on the SYNC2 line of the DCB. The
station 00 function word is also used to reset these interrupts.
Line Synchronized Timing Interrupt (A4
= "1")
Bit A4 is set when a synchronizing interrupt has been received by the DCT from the 1573
Line Synchronized Timing Generator. Bits in the DCT station 00 function word enable the
1573 to send interrupts and/or send a signal on the SYNC1 line of the DCB. A Write
command at DCT station address 01 is used to acknowledge an interrupt from the 1573.
(Bit A4 is present as a status bit regardless of whether the interrupt is enabled or disabled.)
1574 in the System (A5
= "1")
Bit A5 is set whenever a 1574 is connected to the DCT.
1573 in the System (A6 = "1")
Bit A6 is set whenever a 1573 is connected to the DCT.
39072900/28B
2.9
Protected (A 7 = "1")
This bit is set whenever the DCT' s PROTE CT switch is in position 2 or 3.
End of Sequence (AS
= "1")
Bit AS is set when the 1574 is precisely at the end of an addressing sequence.
External Sync Enabled to SYNC2 Line (A9
= "1")
Bit A9 is set when the external synchronizing input has been connected to the SYNC2 line of
the DCB. This bit is reset when the external sync is disabled from the SYNC2 line.
2.3.3
Data Transfer Commands
Data Transfer commands are used for Read or Write operations at specified channel
addresses.
The channel address may be specified in the command (Random Address) or it
may have been previously set up (No Address commands) if a 1574 Sequential Addressing
Unit is in the system.
DATA TRANSFER COMMAND FORMAT
The general format for data transfer commands is shown below. In Data Transfer
command the Q-register contains a "1" in bit 15 and an Input-to-A or Output-from-A
command is executed indicating the "connected" flip-flop of the DCT is set. If a Connect
command has not been previously executed, the DCT does not respond and the computer
generates an Internal Reject.
o
15 14 13 12 11
Q-Register
Channel Address
15
A-Register
o
Data
CHANNEL DATA TRANSFER COMMAND FORMAT
2.10
39072900/2SB
RANDOM ADDRESS COMMANDS
Random Address commands are Data Transfer commands with a "0" in bit 14. The
channel address is always specified by bits 0 through 11 of the Q-register. Bits 12 and 13
specify 1 of 4 operating modes as follows:
a. Random Address Read Only (Mode = 00) . This mode causes data to be read
from the indicated channel without starting another conversion. The sequence of a sequential operation using the 1574 is not affected. No execute signal is generated in this mode.
b. Random Address Execute (Mode = 01). This mode causes a data transfer to
be executed at the specified channel. The sequence of a sequential operation using the 1574
is not affected.
c. Random Address and Lockup (Mode = 02) . This mode is rejected if the
1574 is not present in the system. A data transfer is executed at the specified channel
address and the next address in the sequence is set equal to the specified address.
d. Random Address and Increment (Mode
= 03).
This mode is rejected if the
. 1574 is not present in the system. A data transfer is executed at the specified channel
address and the next address in the sequence is set equal to one greater than the specified
address.
CHANNEL ADDRESSES
Bits 0 through 11 of a Data Transfer command are defined as a channel address.
Channel
addresses are used to communicate with units connected to the stations. Bits 10 and 11
of the channel address select the type of unit to be addressed as illustrated below.
39072900/28B
2.11
Channel Address
,
(---------------~--------------~
I
II
Ii
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
l
Q-Register
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
I
J
~--.-~~--r-~-~------------------------~J
"1" = Continue
J
L
o
o
1
1
o
o
o
0
0
1
o
1
0
1
0
1
Channel Address
(1024)
= Digital I/O
= ANAl (Solid-State Multiplexer) (1024)
= ANA2 Relay Multiplexer NO. 1 (1024)
= ANA3 Relay Multiplexer NO.2 (1024)
o
= Random Address - Read Only No Execute
1
= Random Address Execute - Transfers Data
o
1 = Requires 1574 Sequential Address
CHANNEL ADDRESS UNIT TYPE BIT ASSIGNMENTS
Unique channel addresses (bits 0-9) must be assigned to all channels connected to stations
of the same type.
NO ADDRESS COMMANDS
As No Address command is a command with "1's" in bits 4,5, and 6 as shown below.
15
Q-Register
I
11 10
W = "0"
7
E = neT
6
5
4
3
11 1 1I
x
2
1
0
A
S N
o
15
Data
A-Register
x = Enable A
A = Analog/Digital
S = Step Address Counter of 1574
N = Inhibit Read Execute Signal
NO ADDRESS DATA TRANSFER COMMAND FORMAT
2.12
39072900/28B
Bits 0 through 3 specify special operating conditions.
The channel address for sequential
operations is controlled by the 1574 Sequential Addressing Unit; No Address commands are
rejected if the 1574 is not in the system.
Bits 2 and 3 can be used to change from an analog channel to a digital channel of the same
address or vice versa.
No change is made if bit 3 is "0;" however, if bit 3 is "1," bit 2 is
temporarily substituted for bit 10 of the address previously set up if bit 11 of that address
is"O."
A "1" in bit 1 causes the channel address to be incremented after the data transfer.
Bit 0 indicates that the Read Execute signal should be inhibited.
A No Address input
command with a "1" in bit 0 may be used to read the result of an analog-to-digital conversion without starting another conversion.
No response is sent to a No Address output
command with a "1" in bit O.
2.3.4
Sequential Operation Commands
. Sequential addressing operations are made possible by the 1574 Sequential Addressing Unit
or the 1571 Chaining Buffer Channel.
A reject is sent from the DCT when Sequential
Operation commands are executed if a 1574 or 1571 is not in the system.
The A-register is
used for addresses instead of for function or status bits when Sequential Address commands
are executed.
Sequential operations for data transfer are executed in the Direct mode using No Address
commands (1574 only).
The channel address may be incremented (for the 1574) on each
data transfer or at selected times as desired.
1571 is automatic after initial setup.
Incrementing of channel addresses using the
Bits 10 and 11 of the channel address are never
incremented since they are used to select the type of unit instead of for channel selection.
Random Address operations can be executed in modes zero or one without disturbing the
sequence of a sequential operation.
Random Address operations in modes two or three are
used only by the 1574 and can be used to change the sequence at any time.
39072900/28B
2.13
SEQUENTIAL SETUP
The A-and Q-register formats for Sequential Operation Setup commands are shown below.
Sequential setup is accomplished when bit 14 and' bit 15 are" l' s," the registers are loaded
as indicated, and the computer executes an Output-from -A command.
Bit 15 indicates the
channel address; bit 14 indicates a sequential address setup. Since setup commands are in
the form of a Data Transfer command, the DCT must have been connected previously.
o
15 14 13 12 11 10 9
Analog
Q-Register
1
1 Unit
/'
First Channel Address
Digita
Continue Command
I
Sequential Address Stu
e p
00
01
10
11
-
1574 Sequential
1571A Chaining
1571B Chaining
1571B Chaining
Addressing Unit
Buffer Channel
Buffer Channel NO. 1
Buffer Ch~nnel NO.2
o
15
Last Channel Address + 1
A-Register
SEQUENTIAL OPERATION SETUP COM1\1AND FORMATS
SEQUENTIAL STATUS
The A-and Q-register formats for Sequential Operation Status commands are shown below.
When the Q-register is loaded as indicated and the computer executes an Input-to-A
command, the A-register receives the next channel address from the 1574 in bits 0 through
11.
The same word as used for a Sequential Setup may be left in the Q-register, since
bits 0 through 11 are ignored.
This status command can be executed while a sequential
operation is in progress to determine how much of a block has been transferred.
2.14
39072900/28B
o
15 14 13 12 11
Not Used
Q-Register
o
15
A-Register
Next Channel Address
SEQUENTIAL OPERATION STATUS COMMAND FORMATS
Table 2 . 1 summarizes all allowable nCT commands.
2.4
INTERRUPTS USAGE
Refer to Appendix A for a discussion of nCT interrupts usage.
39072900/28B
2.15
TABLE 2.1. nCT COMMAND STRUCTURE
INPUT
OR
OUTPUT
OPERATION
TO/FROM 'A-REGISTER
15114113112
III
1 10
9181716151413121110
Functions
FROM Q-REGISTER
15\14\ 13 1 12
11
10\ 9\ Sl7
6\5\4\3\2\110
1
Function
Out
2
Device Status
In
3
Start··
Out
4
Next Memory
Address··
In
5
Direct I/O
No Address
I/O
6
Random Address
Read Only
In
Data
1000
Channel Address
7
Random Address
Execute
I/O
Data
1001
Channel Address
8
Random Address
Lock lip
I/O
Data
1010
Channel Address
9
Random Address
Increment
I/O
Data
1011
Channel Address
10
Sequential Setup
Out
1574B
Last Channel Address
1100
First Channel Address
11
Sequential Setup
Out
1571 (1)
Last Channel Address
1101
First Channel Address
12
Sequential Status
In
1571 (1)
1l0I
Ignored
13
Sequential Setup
Out
1571 (2)
1110
First Channel Address
14
Sequential Status
In
1571 (2)
1110
Ignored
15
Sequential Setup
Out
1571 (3)
III 1
First Channel Address
16
Sequential Status
In
1571 (3)
Device Status
Station Address·
W ="0"
E = Ec
Station Address·
Station Address.
Next Memory Address
\V == "0"
Station Address·
W
Next Channel Address
Next Channel Address
Last Channel Address
I
c
W == "0"
Last Channel Address
I
E=E
Starting Memory Address
Data
I
W ="0"
Next Channel Address
==
"0"
1111
• Station addresses zero and one are used by the DCT; station addresses 60 through 6F are reserved for the 1797;
station addresses 70 through 7F are No Address data transfer .
•• Used by buffered devices connected to 1797.
••• Definitions:
X == enable A; A = analog/digital: S = step address counter after data transfer; N = inhibit execute signal.
No Address commands apply only to modules with sequential channel addressing capability (1574 or 1571).
E==E
•••
c
1 1 1 X A S N
Ignored
Section Three
THEORY OF OPERATION
-
GLOSSARY OF TERMS
DEFINITION
INPUT /OUTPUT
SIGNAL NAME
SIGNAL NAME
INTERNAL CONTROL SIGNALS (Continued)
INPUT SIGNALS TO DCT FROM 1705
QO-Q15
7,9,11,13,15,18,19
DEFINITION
INPUT /OUTPUT
Q-Register Inputs
WEX
17, 19
Write Execute
ADDIB
9, 19
Add "]" to 1574 Register (No
19
No Address
AO-AI5
10,12,14,16
A-Register Inputs
WEZ
7
W-Field Equals Zero
Address· QOl)
MCL
7
Master Clear
NAD
PRO
7
Program Protect Bit
SRS
19
Status Read
PR~2
7, 18
PROTECT Switch in Position 2
READ
18
Read Command
WRITE
18
Write Command
OUTPUT SIGNALS TO 1705 FROM DCT
15
Character Input
RPY
18
Reply
RJT
18
Reject
NTOI-NTI5
9, l1, 13, 15
Interrupt Lines 01-15
AOO-A15
10,12,14,16
A-Register Outputs
S1771
---------
1573 Grounds This Signal
S1785
23-28
1574 Grounds This Signal
S1788
QOOA-QI5B
ADDIA
--------{ 7, 9, 11 , 13, 15,
19,22,25,26,28
19
PR()3
7, 18
PROTECT Switch in Position 3
CNCT
7
Connect
C~NR
7
Reset
ADDRESS DECODER SIGNALS
CSAO-CSA3
20, 22
Decoded Address Bits 8,9
CSBO-CSB3
8, 17, 21, 22
Decoded Address Bits 6,7
CSCO-CSC3
8, 17,21,22
Decoded Address Bits 4,5
CSDO-CSD3
8, 17, 21, 22
Decoded Address Bits 2,3
CSEO-CSE3
8, 17, 21, 22
Decoded Address Bits 0, 1
DIGT
22
Digital Input or Output
(Address OXX)
1572 Grounds This Signal
ANAl
22
Analog 1 (Address 4XX)
Condition Q-Register Bits
ANA2
22
Analog 2 (Address 8XX)
Add "1" to 1574 Register
ANA3
22
Analog 3 ( Address CXX)
E()S
22
End of Sequence (Grounded by
(Q12 . Q14 . Q15)
WHR
19
Write Here
SYNI
9, 13
Sync Source NO. 1
SYN2
9, 17
Sync Source NO. 2
FNCT
7, 20
Function
PR~T
2, 7, 42
Protect
MCL
7
Master Clear
REX
19
Read Execute
This Card)
DDT
18, 22
Disable Data Transfer
EDT (NAD + RAL)
RDT
22
Reject Data Transfer
EDT (NAD + RAL)
EDT
22
Enable Data Transfer (Grounded
by Cards 23 -28)
GLOSSARY OF TERMS (Continued)
SIGNAL NAME
DEFINITION
INPUT /OUTPUT
SIGNAL NAME
DEFINmON
INPUT/OUTPUT
DCT INPUT AND OUTPUT LINES
1574 SEQUENTIAL ADDRESSING UNIT SIGNALS
Compare
CHL
20
Channel Address
SASS
Sequential Address and Setup
STA
20
Station Address
SAMI
Sequential Address Module 1
E~
23
End of Sequence
Sequential Address Module 2
SAM 1
20, 42
Sequential Addressing Module 1
SAM2
SAM2
20, 42
Sequential Addressing Module 2
REX
20
Read Execute
WEX
20
Write Execute
C~MP
23-28
NAD
No Address
NLK
1574 Interlock
RAL
Random Address and Lockup
PR~
20
Protected Command
E~S
End of Sequence
UNPF
20
Unprotected (False)
NA
Next Address Register
SYN1
20
Sync NO. 1
SYN2
17
Sync NO. 2
MCL
7
Master Clear
CINF
15
Character Input (False)
PA
Present Address Register
FA
First Address Register
LA
Last Address Register
CARY
Carry from Preceding Stage of
Register
RJTF
18
Reject Unconditionally (False)
RHRF
18
Read Here (False)
RRYF
18
Read Ready (False)
RNA
Read Next Address Register
WHRF
18
Write Here (False)
NAPA
Copy Next Address to Present
WRYF
18
Write Ready (False)
Address Register
Copy First Address to Present
FAPA
Address Register
PAN A
Copy Present Address into Next
Address Register and Add "1"
QTPA
Copy Q-Register Bits into
Present Address Register
RNAR
23-28
Read Next Address Register
CSAO-CSE3
20, 21
Decoded Address Lines
DIG
20
Digital
ANAl
20
Analog NO. 1
ANA2
20
Analog NO. 2
ANA3
20
Analog NO. 3
AROOF-AR15F
9, 11, 13, 15
A-Read Lines 00-15 (False)
STOOF-ST15F
9,10,11, 13, 15
Status Lines 00-15 (False)
AWOO-AW15
8
A-Write Lines 00-15
NT01F-NT15F
9, 11, 13, 15
Interrupt Lines 01-15 (False)
PR~SF
7
PROTECT Switch in DCT Off
3.1
TYPICAL DATA AND CONTROL BUS INPUT AND OUTPUT
3.2
GENERAL
CONFIGURATIONS
The 1750 Data and Control Terminal receives function and addressing information in
3.2.1
Input Configuration
the form of line-to-line differential voltages of the order of 0.5 volts with a complete
Figure 3.1 shows the typical configuration of input lines from devices connected to
voltage reversal distinguishing a "1" from a "0. "
the DCT.
Each input line forms a continuous AND gate because of the connection of
For a logical "0," the odd numbered line of the pair (e.g., AI) is at +0.25V and
the input signals through the output diodes of the line drivers within the devices.
the even numbered line of the pair (e. g. , A2) is at - O. 25V.
Since inverted logic levels are provided for the output signals from the devices. the
For a logical "1,"
these voltages reverse so that the even numbered line is at +0. 25V and the odd
net effect is the formation of a continuous OR. The gate implemented by this config-
numbered line is at -0. 25V.
uration performs an OR operation on the incoming signals from the devices, and the
output of the receiver within the DCT is the logical sum of all the input signals. This
The Q-register and the A-register configurations of the 1700 Computer are trans-
output is a "1" if the output frqm any device is a "0" state signal.
mitted to the DCT with the Q-register containing the W-field, the equipment number
in the E-field, and the address (if applicable) in the lower order 7 bits.
A-register contains either the function code or the address.
The
3.2.2
Output Configuration
Table 2.1 defines the
configuration of the A- and Q-registers during input/output operations.
Figure 3.2 shows the typical configuration of the output line connections for devices
connected to the DCT.
Each DCT line output driver is capable of driving 40 diode
In addition to the A- and Q-register transfers, inputs are provided for 15 interrupt
input loads.
lines.
device connected to the DCT.
These interrupts can be generated within the DCT or within any of the
devices connected to the DCT.
An isolation diode must be provided for each signal line within each
for each input signal.
A maximum of two loads are used within any device
DEVICE WITHIN
OCT MODULE
DCT MODULE
OCT MODULE
DEVICE WITHIN DeT MODULE
A+B+C+
D+E+F
B
D
F
MAXIMl'M 2 LOADS
PER DEVICE
1-1332-A
1-1333-A
FIGURE 3.1.
TYPICAL DCB INPUT
CONFIGURATION
FIGURE 3.2.
TYPICAL DCB OUTPUT
CONFIGURATION
3.3
and the PROTECT and EQUIPMENT NUl\lBER switch logic. These bits provide the
FUNCTIONAL DESCRIPTION
basic connect and addressing configuration which are decoded to form the various
Information received by the DCT is handled by the A-register interface, the
basic control signals.
Q-register receivers (Address Control), and the PROTECT and EQUIPMENT
NUMBER switch logic. Control of information flow during input/output information
3.3.3
PROTECT and EQUIPMENT NUMBER Switches
transfers is maintained by the function control and response control logic.
Addressing of devices connected to the DCT is established by either the Address
The remaining Q-register bits, the Master Clear, W = "0," and the Program
Decoder or the 1574 Sequential Addressing Unit.
These are mutually exclusive
Protect bits are received by this logic block, changed to logic level signals, and
If both or parts of both are
compared to the switch settings to originate control signals used by the function and
options and only one should be installed in any DCT.
accidentally installed, a logical interlock system inhibits data transfers until the
duplication is eliminated.
response control logic blocks.
The interrupts from the DCT and its connected devices
are transmitted to the 1705 by the interrupt line transmitters. The function of each of
3.3.4
Response Control Logic
the logic blocks shown in Figure 3.3 is briefly described in the following paragraphs.
This block of logic receives the Read or Write command from the 1705 and the Here,
3.3.1
A-Register Interface
Ready, and Character Input signals from the DCB.
The bipolar signals received
from the stations connected to the DCB are received as logic levels, and, in some
The A -register interface logic provides an interface for all data and status informa-
cases, AND'ed with control signals from the function control logic, then changed to
tion between the 1705 and the stations and channels connected to the DCT. The bipolar
bipolar signals and transmitted to the 1705.
inputs are received from the A-register transmitters of the 1705, changed to logic
to be transmitted to the computer.
levels (0 volts = "0," +3 volts = "1") for transmission to the devices connected to
has occurred, a response is simulated.
This block provides the final response
In cases where no execution of the instruction
the DCT. Signals originating at the stations are received by line terminators,
changed to bipolar levels by the transmitters, and transmitted to the 1705. Control
3.3.5
Function Control Logic
of this information flow is maintained by the DCT function and response control logic
with initiation of control by the computer Read/Write signals.
This logic controls the basic functions of the DCT for transmission, generation, and
retrieval of information.
3.3.2
Q-Register Receivers
the DCB.
Inputs are received from all other logic blocks and from
The inputs are decoded, interpreted, and combined to control the flow of
information to and from the devices connected to the DCT.
Decisions regarding
Q-register bits QOO through Q06 and Qll through Q15 are received by this logic
disposition of all information transfers are made in this block, with the control
block, changed to logic level signals, and output to the Address Decoder, the 1574,
information from all other blocks.
3.3.6
Interrupt Interface
3.3.11
Control Line Drivers
The interrupt interface provides line terminators for interrupts generated. at the
stations or the DCT and transmitters to change these inputs to bipolar signals for
This block of drivers provides amplification for the control signals transmitted to
transmission to the computer.
the stations. The inputs to this block are provided by the function control and
Address Decoder logic blocks.
3.3.7
The input control signals are received, in some
cases inverted, and amplified for transmission on the DCB lines.
A-Write Line Drivers
This block receives the logic level outputs of the A-register interface block and
3.3.12
Address Decoder
transmits the A-register configuration to the stations continually except during
transmission of A-read or status information to the 1705.
This block provides decoding for the lower bits of the Q-register.
The bits are
decoded two at a time to provide four control outputs for each two bits.
3.3.8
A-Read and Status Terminators
These
outputs are labeled CSAO through CSE3, with CSEO through CSE3 decoded from the
two lowest order bits of the Q-register.
This block of logic receives the logic level inputs from the stations which are gated
by control signals into the A-register interface block.
Qll is also decoded for special functions within this block.
This block and the 1574
are mutually exclusive, and if the 1574 is installed, this block, which is
3.3.9
cis
implemented by Card 22, should be removed.
Line Drivers
This is a block of line drivers which receives the
cis
(Channel/Station Address)
3.3.13
1574 Sequential Addressing Unit
inputs from either the Address Decoder or the 1574 and transmits the address
control signals to the stations.
This is an alternate option to the Address Decoder and is used instead of, but not in
addition to, the Address Decoder. The 1574 is implemented on cards in poSitions 23
3.3.10
End of Sequence
through 28, all of which must be removed if the 1574 is not used. The 1574 provides
a group of four interconnected registers to retain the addresses during sequential
A single line driver is provided for the End-of-Sequence signal from the 1574. This
addressing operations. The four 8-bit registers are labeled Last Address register,
driver is located on a 1574 card and is not used if the 1574 is not installed.
First Address register, Next Address register, and Present Address register.
A-WRITE LINE DRIVERS
A-REGISTER INTERFACE
ANOO-AW03
AROO-AR03
STOO-ST03
1IT9>0-STSO 3
TO/FROM
A-REGISTER
AWOO-AWlS
CARD 8
~A~~_ ..Q.RD..,li. _
AWO-4-AW07
AR04-AR07
STO-4-!n'C·7
IIT9>-4-STS07
~A~AO_7_ _
~!!...AW08-AWlI
AR08-ARll
ST08-BTll
1IT9>8-STSII
~A~A.!L _~RD....!!._
AW12-AWlS
AR12-ARlS
STI2-BTlS
CARD 10
STS12-STSlS
READ TERMINATORS
-
II'l'SO-STSl5
r--
~
~
II:
- --CARll 11
~l!..-
FROM
Q-REGIBTER
~
~
ADDRESS DECODE OPTIONS
FUNCT:ON CONTROL
.
i
-
L __
_ _ ~RD~ _
i
-.5~ 22-.J
iSEQUE~LMm~~
CARD 17
ADDRESS CONTIWL
QOO, Q04-Q06, Q12-Q15
CARll 1.
~D;;SS-;-EC-;;;E;
l!
- - - - - --
lill
MODULE
I
-SA.!!£S ~2!...J
-
A-ilEAl>
LDlEB
SYSTEM
STATUS
LINES
CARD
UNE DRIVERS
CSBO-CSE3
r----
-
~A~l_
CSAO-CSA3, ANAI-ANA3, DIG
SYNCl, SAMl, SAM2
READ EXECUTE
WRITE EXECUTE
PROGRAM PROTECT
CHANNEL ADDRESS
WTA.I!..ON2!2PR~ ~ L E~~E~
PROGRAM PROTECT AND
EQUIPMENT SELECT SWITCIIES
CARD 7
Q07-QIO
-
-- - - -•
AR12-ARIS
STl2-STlS
CARD 9
_QO.,L _ _ _CAl!!! 11- _
CARD 15
ARO-4-ARD7
CARD 13
S1'04-81'07
f------AR08-ARll
CARDU
81'08-STll
NAOO-NAll
r--"----INTERFACE TO
170S
INTJ;RRUPT/
DATA CHANNEL
--------
STOO-STlS
Q-REGmTERINTERFACE
Q02
AROO-AR03
S1'OO-ST03
.....
AROO-ARlS
~
f--QO~-
A-WRITE
LDlEB
AWOO-AWlS
ADDREIII
UNES
CONTROL
UNES
~22a
SYNC 2
~1,!f---- - - - CARD 7
MASTER CLEAR
•
EXTERNAL SYNC
CONTROL INTERFACE
W = 0, MASTER CLEAR,
PROGRAM PROTECT
TO/FROM
CONTROL
~-
CONTROL TERf,UNA TORS
RESPONSE CONTROL
CARD2..._
-READ, WRITE
UNCONDITIONAL REJECT
READ IIERE, WRITE READY,
~EAD READY, V.1UTE HERE
~
Z
REPLY, RE.TECT
~--
-
CARD IS
~..!L_
~----
1
CHARACTER INPUT
CARD 15
RESPONSE INPUT U NES
-- --.CAIUl 13
CHARACTER INPUT
CARD 15
~
~RRUPTINTERFACE
-- -- -- - - --- - - -- -r--- - - - - - - -f---
INTERRUPT
TO{
UNESOl-lS
----1LTOl, NT05, N1'09, NTI3_ _
__
r---
__
~T06~,~
~,
---
NT07, NTll, NT15 _ _
NTn4' NTOIl. NT12
--
C~ 9
-- - - -- - - -- -- - - - - -- -- -- ---- -- -- -- -
~RD_l_l_
CARD 13
CARD 15
-
• CARD Z2 IS REMOVED IF TilE 1574 MODULE IS INSTALLED.
FIGURE 3.3. DATA AND CONTROL TERMINAL BLOCK DIAGRAM
INTERRUPT UNES
INTERFACE
TO DATA
AND
CONTROL
BUS
3.4
DATA AND CONTROL BUS
All communications to and from the computer are via the A/Q cables connected to
TABLE 3. 1. DCT SIGNAL AND PIN ASSIGNMENTS
DATA CABLE SIGNAL
PIN
Data Bit 00
01
02
03
04
05
06
07
08
To/From
09
A-Register
10
11
12
13
14
Data Bit 15
Reply
Reject
Character Input
Priority*
AI, 2
3, 4
5, 6
7, 8
9, 10
B1, 2
3,4
5, 6
7, 8
9, 10
C1, 2
3,4
5, 6
7, 8
9, 10
D1, 2
3,4
5, 6
7, 8
9, 10
r EI ,2
3,4
5, 6
7, 8
< 9, 10
FI, 2
3,4
5, 6
7, 8
'- 9, 10
ADDRESS CABLE SIGNAL
the DCT. Each interrupt is cabled separately from the DCT to the computer. (See
Table 3. 1 for DCT pin assignments and Figure 3.4 for DCT cabling.) All communication between the DCT and 1500 Series Peripherals is via the Data and Control Bus
(DCB) which originates at the DCT.
The DCB is a two-way communication bus that originates at the DCT in card positions 2, 4, and 6. The DCB is connected to each cabinet rack that contains a
controller and is connected from controller to controller in a serial fashion by 50-pin
wired connectors (see Figure 3.5). Terminator boards are installed in card positions 2, 4, and 6 of the last controller rack of the serial string.
Figures 3.6 through 3. 10 list the signal and pin assignments for the DCB connectors
that are in card positions 2 through 6. Master Clear (MCL) originates from four
parallel diodes of a standard logic element in the DCT and appears in true orientation
on the DCB. All other signals originate from four parallel diodes of standard logic
elements in devices on the DCB; these signals appear in inverted orientation on the
DCB. Card position 3 contains the jumpering for the 1577 Stall Alarm channel/
station lines, interrupts, and status. Card position 5 contains the jumpering for
signals and interrupts for other optional equipment.
Not Defined
All of the channel/station lines (CSAX, CSBX, CSCX, CSDX, and CSEX) are
jumpered from various card positions in the controller module rack to the required
Termination Power
Address Bit 00
01
02
03
04
05
06
07
08
09
10
11
From
Q-Register
}
12
13
W
14
Address Bit 15
Read
Write
Master Clear
Program Protect
Buffer Active*
Timing Pulse
Spare
Spare
Not Defined
Not Defined
Not Defined
Not Defined
W=O
Termination Power
DCB lines. (Refer to individual controller manuals for station/channel selection
examples and jumpering positions.) Interrupts and multiplexer assignments are
jumpered to the DCB lines in the same manner. All other signals are back-plane
wired to the DCB lines.
* These signals exist in the cables from a BDC only and are for use with devices
which use the BDC channel exclusively.
~
to
0
~
~
to
0
0
tj
INTERRUPT LINES
4
0
J14
8
3
0
J13
7
2
0
0
12
11
10
0
J22
0
0
15
14
13
0
0
0
J25
J21
J24
Jll-J25:
CONNECTOR RECEPTACLE
17896900
0 0
0 0
5
I
0
JIG
J15
9
0
J20
J23
J37, 40, 41
Jll
6
0
J17
0
J12
0
J18
A/Q CHANNEL
J31
DATA
~
J19
J30
ADDRESS
8
J36. 40.
I
~
0
a
120 VAC
CORD
J40
-6V
TO OTHER
-6V USERS
J30-J33:
30 TWISTED-PAIR WIRE CONNECTOR
38956900
0
0
J39
·n
8
(SRG:"Cl)
(40)
(SRG-Q)
(39)
SAMPLE
RATE
GENERATOR
8
J35
8
POWER
(SRG-C2)
EXT SYNC (IN)
J34
J38
TERMINATOR
POWER
J38-J40:
CONNECTOR RECEPTACLE
38925500
EITHER ONE OF THE DATA, ADDRESS, Ar·m TERMINATOR POWER CONNECTOJt PAIRS CAN BE USED FOR IN. OR OUT WHEN THE LCA
IS PART OF A CHAIN ON THE 1700 COMPUTER.
IF THE LCA IS TilE LAST UNIT ON 1700 PARTY LINES, VACANT RECEPTACLES J30 OR J31
RESISTIVE TERMINATOR PLUG (NO. 30001201) INSTALLED.
FIGURE 3.4.
nCT CABLING
A~
J:.l2 OR J33 MUST HAVE A
1
-
CABLED TO SECOND RACK CABINET
IF REQUJHED; IF LAST MODULE,
INSTALL TERMINATOR BOARDS
CONTROLLERS OR OTHER
SUBSYSTEM UNITS
-
__---A'----...
(
-
'I
5
-
-
\
r-
\
\
\
\
DATA AND
CONTROL BUS
POSITIONS
1 THROUGH 6
'\
\
\
9
\
13
-
-
\
t-
\
\
\
\
-
\
17
-
-
-
\
-
\
\
\
\
-
\
21
-
\11
5 \6
\
I
DCB
ORIGINATION
POSITIONS
2, 4, AND 6
2
\
I
I
I
I
I
4
-
CONTROLLER'S
AND ASSOCIATED
UNITS
\
25
DATA AND CONTROL
TERMINAL AND
OPTIONS
(
6
7
'-
-
)
42
29
-
33
-
BLOWER
(MG SET IN REAR IF USED)
-
-
FILTER
1-2525
FIGURE 3.5. DATA AND CONTROL BUS
3.12
39072900/28B
PIN
SIGNAL
FROM CARDS
TO CARDS
PIN
SIGNAL
TO CARDS
GROUND
2
GROUND
3
CSAO
4
DIG
5
CSA1
~2fi
6
ANAl
7
CSA2
J
8
ANA2
9
CSA3
10
ANA3
12
SAMl
23
14
SAM2
23
CSB2
16
REX
17.. 18.24.38
CSB3
18
WEX
17 23 32311 A2
CSCO
17,3
20
PR0
SYN1
1
11
13
15
17
19
CSBO
CSBI
j
17,3
~
3
FROM CARDS
r.
20
,....
21
CSC1
3
22
23
CSC2
3
24
SYN2
25
CSC3
3
26
MCL
27,42
28
PR0SF
2
7
STALL
42
42
27
29
CSDO
21
I
17,3
3
30
CSD2
3
32
CSD3
3
34
35
CSEO
17, 3
36
37
CSE1
17-,- 3
38
39
CSE2
39~
40
41
CSE3
39, 3
43
CHL
45
STA
47
E0S
GROUND
31
33
49
CSD1
3
17, 18, 18, 42
17
7
42
~
20
44
20
46
CINF
15
23, 22
48
RJTF
GROUND
18
50
NOTE: Pins 28, 32, and 34 are spare pins for signals originating in the DCT; pins 38, 40, 42 and 44 are spare pins for
signals originating outside the DCT; pin 36 is used for E{l>PF in the 1571.
FIGURE 3.6. DCB CONNECTOR (CARD POSITION 2)
GROUND
C".:)
1--4
~
Q
C:J
Q
Q
GJ
0
G
G
0
C".:)
~
0
-:]
I:\:)
DSABL
CSBl
CSBO
From Pin 26
G
8
GJ
G
CSBX
G
G
GiJ
NT08F
GJ
NT02F
G;J
NT09F
NT03F
GJ
CSC2
~
~
G
0
G
G
B
G
G
G
CSCl
CSCO
CSD3
G
CSD2
0
G
CSDl
E]
CSDO
0
CSE3
[;]
CSE2
B
B
0
GJ
CSDX
CSEX
CSEO
B
EJ
G
NTllF
NT06F
B
NTl3F
NT07F
El
NTl4F
NT04F
NT05F
PFLNF
STLNF
G
To Pin 28
~
0
0
"I:\:)
00
OJ
G
G
NTOlF
CSC3
cscx
CSEl
FIGURE 3.7. DCB CONNECTOR (CARD POSITION 3)
El
EJ
EJ
NTlOF
NTl2F
NTl5F
FIELD
GROUND
PIN
SIGNAL
1
GROUND
3
AROOF
5
AROIF
FROM CARDS
TO CARDS
I,
~
11
,
\
15
37
PIN
SIGNAL
TO CARDS
2
GROUND
4
AWOO
37, 39, 42
6
AWOl
37, 39
8
AW02
37
7
AR02F
{
9
AR03F
I)
I)
10
AW03
37
11
AR04F
II
11
12
AW04
36
13
AR05F
\
14
AW05
36
16
AW06
36, 39
1;:$
;:$0
15
AR06F
17
AR07F
I)
I)
18
AW07
36, 39
AR08F
II
I,
20
AW08
35, 39
\
22
AW09
35, 39
24
AW10
35, 39
19
21
I
I
AR09F
11
J
35
FROM CARDS
I"",
8
23
ARI0F
25
ARIIF
I)
I)
26
AW11
35, 39
27
AR12F
11
11
28
AW12
32, 34, 39
29
AR13F
\
30
AW13
32, 34, 39
32
AW14
32, 34, 39
34
AW15
32, 34, 39
WHRF
18
9
WRYF
18, 42
19
31
AR14F
33
AR15F
J
::J
34
f
)
,)
35
RHRF
18
13
36
37
RRYF
18
11
38
39
40
41
42
43
44
45
46
47
48
49
GROUND
50
GROUND
NOTE: Pins 39 through 48 are not continuous in the DeB Connector.
FIGURE 3.8. DCB CONNECTOR (CARD POSITION 4)
I.....
PIN
SIGNAL
TO CARDS
FROM CARDS
PIN
SIGNAL
TO CARDS
1
2
3
4
5
6
NTOIF
3, 6, 9
23
8
NT02F
3, 6, 11
32
10
NT03F
3. 6. 13
39
12
NT04F
3, 6, 15
17
14
NT05F
3, 6, 9
NT06F
3, 6, 11
7
9
11
13
E~SNF
LSCNF
SRGNF
EXSNF
5
5
5
5
FROM CARDS
Jumpered from
signals on
nins ::It 1Aft
15
ESOSNF
5
16
17
LSCNF
5
18
NT07F
3. 6. 13
19
SRGNF
5
20
NT08F
3, 6
5
22
NT09F
3, 6, 9
23
24
NTI0F
3, 6, 11
25
26
NTI1F
3, 6, 13
27
28
NT12F
3, 6, 15
29
30
NT13F
3, 6, 9
31
32
NT14F
3, 6, 11
33
34
Jumpered from
signals on
NT15F
3, 6, 13
l1in.R at 1Aft
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
21
EXSNF
15
GROUND
NOTE: For standard interrupt line assignments, insert jumpers as follows:
pin 9 (line 2).
Line Sync Clock (LSC) pin 8 to
FIGURE 3.9. DCB CONNECTOR (CARD POSITION 5)
PIN
1
3
SIGNAL
FROM CARDS
TO CARDS
PIN
SIGNAL
TO CARDS
G..K.UUNlJ
2
GROUND
UNPF
4
STOOF
i)
6
STOIF
~
15
11
j""I
5
NTOIF
9
7
NT02F
11
8
ST02F
9
NT03F
13
10
ST03F
(
LJ
11
NT04F
15
12
ST04F
rl
9
14
ST05F
11
16
ST06F
13
18
ST07F
l.J
20
ST08F
11
ST09F
13
15
17
19
NT05F
NT06F
NT07F
NT08F
5
15
1
~
NT09F
9
22
23
NTI0F
11
24
STI0F
25
NTIIF
13
26
STIIF
LJ
ST12F
fl
27
NT12F
15
28
29
NT13F
9
30
ST13F
31
NT14F
11
32
ST14F
13
34
33
NT15F
.,/
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
GROUND
50
ST15F
39
1!1
II
11
i
~
{
)
GROUND
NOTE: Pins 35 through 48 are not continuous in the DCB Connector.
FIGURE 3.10. DCB CONNECTOR (CARD POSITION 6)
42
42
(
21
FROM CARDS
9
3.5
PROGRAM PROTECT AND EQUIPMENT NUMBER SWITCH LOGIC
The Progra~ Protect bit is received, changed to a logic level signal, and provided
(CARD 7)
as an output (PR0T) to other blocks of logic. The output of the receh·er is also
connected to the common pin of the PROTECT switch. The three positions of the
This block of logic is implemented by the printed circuit card at card position 7 (see
switch provide control and status signals as descrived below.
Figure 3.11), which contains a hexadecimally-coded thumbwheel switch (EQUIPMENT
NUMBER), a three-position rotary switch (PROTECT), and logic elements for
a.
OFF (Position 1)
decoding Q7 through Q10, W = "0," Program Protect, and the Master Clear signal
In this position the Program Protect bit is ignored, no protect faults occur, and the
to provide control signals.
Program Protect status bit (STS07, indicating switch positions 2 and 3) is false.
The output to the nCT (PR0SF) is true when the switch is in this position.
3.5.1
EQUIPMENT NUMBER Switch
b.
REJECT (Position 2)
The Q-register bits Q7 through Q10 are received, changed to logic levels for output
In this position the PR02 output is the protect bit of the command. the PR03 output
to other logic blocks within the nCT module, and decoded by the equipment select
is true, and the PR0SF output is false. When PR02 is false, a protect fault exists,
logic to provide a Connect (CNCT) output. When the setting of the hexadecimal
and the faulting command is rejected. For further explanation of this mode. refer
thumbwheel switch matches the E -field (Q7 through Q10) and the W = "0" signal is
to paragraph 3. 10.
true, the Connect (CNCT) output is true.
c.
The "C" and
"e"
contacts of the EQUIPMENT NUMBER switch are mutually
exclusive and provide selection of the output of Q7 through Q10, either as they
INTERRUPT (Position 3)
In this position the PR03 output is the protect bit of the command. the PR02 output
is true, and the PR0SF output is false. When PR03 is false, a protect fault exists,
appear on the output of the receivers or inverted, but not both. When the Q7 through
and the response is a Reply and Interrupt transmission to the computer.
Q10 configurations, and the EQUIPMENT NUMBER switch setting are identical, only
faulting command is not executed.
The
For further explanation, refer to paragraph 3. 10.
"1" state signals are connected to the output. These signals are AND'ed with the
W = "0" signal to form the Connect (CNCT) output.
3.5.3
When the switch setting does not match the E -field identically or when the W -field is
The Master Clear signal is received in inverted form, changed to a logic level signal,
not "0," the nCT is not connected to the 1705, and the instruction and address is
and provided as an input to the AND gate at the input to inverter n4B. The MASTER
Clear and Master Clear
ignored, unless the DCT was connected by a previous operation and bit 15 of the
CLEAR pushbutton provides another input to the AND gate. The manual switch dis-
Q-register is a "1" (Continue commands).
charges the capacitor, providing a 30-millisecond Clear signaL A 3D-millisecond
signal is also provided when power is turned on. .
3.5.2
PROTECT Switch
When either the Master Clear from the computer or the switch goes false. the input
The PROTECT switch is a three-position rotary switch used to select the Program
to D4B is false, and the Connect flip-flop reset (C0NR) is true. The Connect reset
Protect response to an unprotected command.
provides a reset pulse for the Connect flip-flop and an input to inverter C4.
When either C¢NR is true or the Clear signal (FNCT AND'ed with AOO and provided
as input FNCTO) is true, the output of inverter C4 is false.
The output of C4
The output of C4 is inverted by D4A, which provides an input to the line driver A.
The output of line driver A provides a Master Clear signal for other devices
provides control outputs MCLFI through MCLF5 and a false signal for status bit 00
connected to the DCT. Figure 3.11 is a diagram of the PROTECT and EQUIPMENT
(STSOO, which indicates a Ready state if true).
NUMBER switch logic.
PROGRAM PROTECT
Ql0A
B9
BID
B7
QB
:{:!J PR¢2
lB
I~PR¢3
lB
I
14
010
C2
Q9
20
09
Cl
Ql0
PR;lT
22.23
Ql0B
23
Q09A
22.24
Q09B
24
QOBA
22.24
I
ADDRESS
CABLES
J32. J33
1
2
3
I
OFF
REJECT
INTERRUPT
AND REPLY
.2
I
:5
I
I
I
BB
6
QOBB
24
Q07A
22.25
Q07B
25
2
B
B5
B6
Q7
w=O
F7
FB
t
14
1.21(
MCL
16.17 FNCTO
ADDRESS CABLES J32. J33
+6V
I"
iW
IN
OUT
6
40 LOGIC
LOAD
SCHEMATIC FOR DISCRETE CIRCUIT
~
CNCT
ADDRESS
CABLES
J32. J33
07
DB
L---------8
t.':O
NOTES:
&-sv
STSOO
16
MCLFI
17
MCLF3
23
MCLF4
32
MCLF5
39
lB
MASTER CLEAR
I.
2.7.42
lB
R'O
SWI IS EQUIPMENT NUMBER
SW2 IS PROGRAM PROTECT
SW3 IS MASTER CLE.AR
~+6V
~
1
2
3
4
5
A
ROIA
ROIA
ROlA
ROIA
ROIA
B
ROlA
ROIB
ROIB
ROIB
ROIA
C
ROIB
D24
D24
148
ROIB
D
ROIB
E
D24
ROIB
DCKT
Ql-Q15
Q-Register Inputs
PR03
PROfECT Switch in Position 3
QlOA-Ql5B
Condition Q-Reglster Bits
CARD TYPE: BG
STSJO-STS15
Local Status Bits 00-15
FUNCTO
FWlction at Station Address Zero
CARD TITLE: Protect and Equipment Select
PROOF
PROfECT Switch in DCT Off
CNCT
Connect
CARD DRAWING NO.: 38882400
MCL
Master Clear·
PROf
Protect
LOOIC DRAWING NO.: 38952600. Sheet 7
L-_CO_N_R
_ _ _...L..._Re_se_t_ _ _ _ _ _ _ _ _ _U-_P_R_02
_ _ _...l-_P_R_O_T_E_C_T_5',o,_itc_h_in_Po_S_it_io_n_2--...J
FIGURE 3.11. PROTECT AND EQUIPMENT NUMBER SWITCH LOGIC (CARD 7)
3.6
A-WRITE LINE DRIVERS (CARD 8)
The inputs to this card exactly duplicate the configuration of the computer A-register
except during the time required for transmission of data or status information
The logic elements contained on the printed circuit card at pOSition 8 (FigurE:! 3.12)
to the computer.
provide line drivers for the A-write outputs to the DCT. Each of the noninverting
amplifiers contained in this block can drive up to 40 loads. Inputs to these ampli-
The outputs of the amplifiers are connected directly to the connectors to the DCT,
fiers are provided by one of the outputs from the A-register interface logic.
and the AW lines are output directly to modules connected to the DCT.
~
~
Col:)
CD
0
~
l\:)
It)
ti5A 45
CD
0
0
..........
tj
10
F
47 AWlS
tv'
AI4A 44
¢ . .Jl.
]4,4<;
14-
46 AWI4. 4- 32
.
~4,41.
14
~
37
~
3'
AO:l4 25
AXA 23
J
C
27 AW07
21 AW06
~36.J
~36)
10
~
10
AI2A~AWIZ
4,32:
W04
14-
,?.36
+6V
f~J 4Z,
r----~------------~-----t
@
,2
R3
AIIA~IIWI/
240A
1/4W. •
RI
12K
1/8W
/6
12
~ R6
I
71.2K
I
CR3:
,-'\. . -r-_____ r,r~.J
~ 1/8W
IN;'
12
~'~'
SCHEMATIC FOR DISCRETE. CIRCUIT
~
@
flo
AOM
f29L-.~AWQ9 ~ 3 ..~
~
f-+-----._-_--_~C)
.
f(P
---
---a-
J?
~
V '
A
B
I
~K1A
2
CKT&
Ct.Tc
3
4
!S
6
C
E
D
IC.TG C~r.N
KTH :r"TF
C"T[l
O:TE
KT J
KTK 1"KTQ
KTl CKTP:
C~TF
l(i~
CARD TYPE: BM
CARD TITLE: Long Line Drivers
CARD DRAWING NO.: 38897100
LOGIC DRAWING NO.: 38952600, Sheet 8
AOO-A15
A-Register Inputs
AWOO-AWl5
A- Write Lines 00-15
FIGURE 3.12. A-WRITE LINE DRIVERS (CARD 8)
3.7
LINE TERMINATORS (CARD 9)
within a station connected to this line, the interrupt is transmitted to the 1705 interrupt input as described above.
The printed circuit cards located in card positions 9, 11, 13, and 15
provid~
line
terminators for the A -read lines (AROO through AR15) , system status lines (STOO
3.7.4
Q-Register Receivers
through ST 15), and interrupt lines (NTO 1 through NT15). The remainder of the logic
elements on these cards are used for miscellaneous functions as described below.
Receivers are provided for Q-register bits Q1, Q2, Q3, and Qll on the logic cards
in locations 9, 11, 13, and 15. The Q-register signals are received, converted to
3.7.1
A-Read Lines
logic level signals, and provided as outputs to the address decoding and/or function
control logic blocks.
The A-read signals received from stations on the DCB are inverted by the line terminators to provide inputs to AND gates located on the A-register interface cards.
Q01 is also used for the ADD1B output to the 1574 logic when the 1574 is used.
The A-read line signals are AND'ed with control signals from the function control
The ADDIB signal is used to increment the Present Address and Next Address
logic, which controls the data transmission to the 1705.
registers of the 1574.
3.7.2
Status Lines
The System Status signals received from the stations on the DCB are gated to the
3.7.5
Miscellaneous Logic Elements (Card 9)
S1788
A-register interface transmitters by the function control logic as described above.
This input is generated by the Sample Rate Generator (Card 9) when this option is
3.7.3
Interrupt Lines
installed (see Figure 3.13). The 1788 input is inverted and provided as an input to
the function control logic (SYN2T) and as an output to the DCT line drivers (SYN1B).
Interrupt lines 02 through 15 are received from the DCB stations, inverted, and
transmitted directly to the 1705 interrupt inputs.
LOCAL WRITE HERE (LWHR1)
Interrupt line NT01 is used for interrupts within the DCT module and for stations on
An inverter is provided for the LWHR1 input, from the function control logic.
the Decoded Data Channel. When an interrupt occurs either within the DCT or
providing an input (WHRF) to the response control logic.
t.A:l
~
0
-.:J
20
l\:)
~
0
0
.:>:J
S17f18
~ 3V
ALL BU6S AI2E \\Ot.'OL\ Tt11C
SYNI-SYjl,~
. C:I-.'L£:':' MA(,,-G) NIHI A ' ...
CARD TYPE: DJ
CARD TITLE: Daisy Chain Interface
CARll DRAWING NO.: 38897000
LOGIC DRAWING NO.: 38952600. Sheet 9
NTOIF-NTI5F
QO-QI5
LWHRI
QOOA-QI5B
ADDIB
WHR
FIGURE 3.13. DATA AND CONTROL BUS, INTERFACE 1 (CARD 9)
1572 Grounds This Signal
A-Read Unes 00-15 (False)
Status Unes 00-15 (False)
Sync Source NO. 1. 2
Interrupt Unes 01-15 (False)
Q- Register Inputs
Local Write Here (False)
Condition Q-register Bits
Add "1" to 157 ~ Register
(No Address· QOl)
Write Here (False)
3.7.6
Miscellaneous Logic Elements (Card 11)
In addition to the elements described in the preceding descriptions, Card 11
UNP3, which are used by the response control logic; and (2) LRRY1 is received
(Figure 3.14) provides circuit elements for the follOwing signals:
from the function control logic, inverted, and provided as an output to the response
(1) UNPF is
received from the DCB stations and inverted to provide output signals UNP2 and
control logic block.
c..:>
LINES
c.o
0
-.J
I:'-'
1.'3
6
14-
~b
c.o
0
0
...........
18
tj
IlRI IT
12
-Sb
10
12
12
12
z
It:.
Q2
/IS
27
• At;;
J~Jj.i .J
17
23
LRRYI
I-----~-----_:;.(
II
K~
YF
18
12.
f41!'---~-I-'>=:'
*
-CDV
NOTE: INVERTER
WITH FOUR OUTPUT
DIODES TIED TOGETHER
c.~
~-
-hs~
T
l~9 ~--+--+-~ +G.V
r'
+
T
1-1 Tel
~I.uF
135'1
c.z
lAAF
3SV
I
I
ALL W6S A[:C ...·\DIVOLI-rnIC
UtvLE~S MAICk.E.D WIT/-1 A " . "
---- -
, I
rz
~
L4
,IS
c
olI
A
B
TOIA- T31 :I48 :I4S!J:48
TOIA- nl! H8 148 024
TOIAl" T311 H8 146 14a
'TalA' T31! 14a :I48 140
ROIIt' ROt 148 I,4B
CARD TYPE: BJ
CARD TITLE: Daisy Chain Interface
CARD DRAWING NO,: 38897000
LOGIC DRAWING NO.: 38952600. Sheet 11
UNPF
AROO-AR15
STOO-STl5
NT01-NTI5
QO-QI5
LRRY
QOOA-Q15B
RRYF
FIGURE 3.14. DATA AND CONTROL BUS, INTERFACE 2 (CARD 11)
Unprotected (False)
A-Read Lines 00-15
Status Lines 00-15
Interrupt Lines 01-15
Q-Register Inputs
Local Read Ready
Condition Q-Register Bits
Read Ready (False)
3.7.7
Miscellaneous Logic Elements (Card 13)
(STS04 and STS06) and as an input to the nCT (SYNIA).
indicating a line sync interrupt when true.
In addition to the elements described in the preceding description, Card 13
STS04 is the status bit 04,
STS06 is the status bit 06, indicating
that the 1573 module is present in the system.
(Figure 3. 15) provides circuit elements for the following signals.
S1771
LRHRI
This signal is received from the 1573 Line Synchronized Timing Generator, if
This signal is received from the Function Control logic and inverted for use by the
installed, and is inverted and provided as an output signal to the status transmitters
response control logic.
14-~
..:
LINES
14
IS
S;C
2.0
14II
~~
ROt:T
~A.ea', -;-
4,36
14
14-
7
.s;6
.~
3
~-6
6'
14
~Q03A
t-------~~'~~Q03.5
......-~
Q3
Z7
I---;-:::~-
Z3
17
LI?/l1?1
C-"D
~9
0
.
~
. 22
II
10
•
-
23
T
E2B/2
*
ALL E:UbS ALE .\.\C>l\)("\L-I'i\-IIC,
UNLES!> MA12k£.C .v111~ A " ...
CARD TYPE: BJ
CARD TITLE: Daisy Chain Interface
CARD DRAWING NO.: 38897000
LOGIC DRAWING NO.: 38952600, Sheet 13
---~~~RHRF
I{J
NOTE: INVERTER
WITH FOUR OUTPUT
DIODES TIED TOGETHER
S1771
AROO-ARl5
STOO-STl5
ST910-STSI5
SYNI
NTOI-NTI5
LRHR
QOOA-QI5B
RHRF
FIGURE 3.15. DATA AND CONTROL BUS, INTERFACE 3 (CARD 13)
1573 Grounds This Signal
A-Read Lines 00-15
Status Lines 00-15
Local Status Bits 00-15
Sync Source NO. 1
Interrupt Lines 01-15
Local Read Here
Condition Q-Register Bits
Read Here (False)
3.7.S
Miscellaneous Logic Elements (Card 15)
h.
STS05 is the status bit indicating that the 1574 Sequential Addressing
Unit is present in the system.
In addition to the elements described in the preceding sections, Card 15 (Figure 3.16)
c.
STSOS is the status bit that indicates the end of sequence for the 1574.
provides circuit elements for the following signals.
CINF
NLK5
The CINF (Character Input) signal is received from the DCB stations, inverted, and
NLK5 (Interlock 5) is received from the 1574 Sequential Addressing Unit, inverted,
and provided as status output signals as follows.
a.
STS02 is the 1574 Sequential Addressing Unit interrupt hit.
AND'ed with the CS0NT (Connect) signal to provide an input to the character input
transmitter to the 1705.
The Character Input signal. when true, indicates that the
information being transmitted is a character and not a word of input data.
~
c.o
24
NLK5
STS02
16
STS05
14
STSOB
12
AR03T
16
CHARACTER INPUT
2
CINF
1B
C¢NT
07
DB
J30
J31
0
-.;:J
I.\:)
c.o
0
0
4,37
AR03F
INTERRUPT LINES
.........
I.\:)
00
to
4,37
AR02F
AR02T
16
4,37
AR01F
AR01T
16
4, 37
AROOF
6
6
5, 6
NT12F
5,6
NTOBF
5,6
NT04F
Q11
C3
C4
J22-A
J22-B
J1B--A
J18-B
12
B
16
J14-A
J14-B
4
16
ST03F
ST02F
16
Q11A
22, 23
Q11B
23
J32, J33
6,42
ST01 F
16
911
~
22
6,39
p'
10"
..s:-:l
E28/2 f-----~~------~
16
STOOF
*"
1
2
3
4
5
A
TOIA
TOIA
TOIA
TOIA
ROIB
-
B
T31B
T31B
T31B
T31B
ROIA
C
145
145
145
145
145
D
145
145
145
145
145
E
145
D24
145
145
CARD TYPE: BJ
CARD TITLE: Daisy Chain Interface
CARD DRAWING NO.: 38897000
LOGIC DRAWING NO.: 38952600, Sheet 15
NLK5
AROO-AR15
STOO-STI5
STSOO-STS15
CINF
CONT
NTOI-NTI5
QO-QI5
QOOA__~15B
NOTE: INVERTER
WITH FOUR OUTPUT
DIODES TIED TOGETHER
1574 Interlock 5
A-Read Lines 00-15
System Status Lines 00-15
Local status Bits 00-15
Character Input (False)
Connect Signal
Interrupt Lines 01-15
Q-Register Inputs
Condition Q-Re.zister Bits
FIGURE 3.16. DATA AND CONTROL BUS, INTERFAqE 4 (CARD 15)
3.8
A-REGISTER INTERFACE
the STSOO - STS15 input gates are enabled. If the STS input to the gates are true,
a "1" will be transmitted to the 1705.
The A-register interface is implemented by circuit cards in card positions 10, 12,
SYSTEM STATUS (STOOT - STI5T)
14, and 16 (see Figures 3.17 through 3.20). These cards contain both transmitters
and receivers for all A-register interfacing.
System Status information, received from stations connected to the DCB, will be
3.8.1
Receivers
transmitted when the Read-Station-One command is executed. During this command
the RSIFI through RSIF4 inputs will be false, the outputs of the D3 inverters will be
The informatiori is received from the 1705 in the form of bipolar differential signals.
true, and the STOOT - ST15T input gates will be enabled. If the STXXT input is true,
The receivers accept the 16A -register bits, change the bipolar signals to logic
a "1" will be transmitted to the 1705.
levels, provide the logic level outputs for use by the DCT logic, and provide
A-READ LINE INFORMATION (AROOT - ARI5T)
inputs to the A-write line drivers (Card 8). The receivers are constantly accepting
the A-register contents except during transmission of information from any device
Input information, received from the DCB, will be transmitted when a Read command
on the DCB.
with the appropriate station or channel address is executed. During these commands
3.8.2
Transmitters
the RARFI - RARF4 inputs to the A-register interface will be false.
If the other
inputs to the B3 inverters (RSO FX, RS IFX, and RN AFX) are also all false, the output
Information transmissions to/from the DCT occur as described below.
of the B3 inverters will be true and the ARXXT input gates are enabled.
If the
ARXXT input is true, a "1" will be transmitted to the DCT. If one or more of the
other inputs to the B3 inverters is true, the ARXXT lines will not be transmitted.
The transmitters receive information from the DCB, the 1574, and the DCT.
Control of the transmission is maintained by the function control logic (Card 17),
SEQUENTIAL ADDRESSING UNIT NEXT ADDRESS REGISTER
the response control logic (Card 18), and the sequential address control (Card 23)
(NAOO - NAll)
if the 1574 is installed.
LOCAL STATUS (STSOO-STSI5)
If the 1574 Sequential Addressing Unit is installed in the DCT package replacing the
Address Decoder, the NAOO - NAll information (contents of the Next Address
Local Status information, from the DCT or devices contained within the DCT module,
register of the 1574) is transmitted when a Read-Sequential-Status command is
will be transmitted when the Read-Station-Zero command is executed. During this
executed. During this command the RNAFI - RNAF4 inputs to the A-register inter-
command the RSOFI through RSOF4 inputs to the A-register interface cards will be
face are false, the output of the C3 inverters is true, and the NAXX input gates are
false. The input to the E3 inverter (RSOFX) is false, the output of E3 is true, and
enabled.
If the NAXX input is true, a "1" is transmitted to the 1705.
~
CD
0
-:::a
9
ST15T
9
AR15T
9
ST14T
9
AR14T
9
ST13T
9
AR13T
~
CD
0
0
"~
ex>
to
A
3
B
RDIB
ROIA
145
C
TOIA
T3lB
148
D
RDIB
ROIA
148
E
T(tIA
T3lB
148
4
5
ROIB
ROIA
TOIA
T3lB
ROIB
ROIA
TOIA
T3lB
I
2
CARD TYPE: AV
CARD TITLE: Balance Line Interface
CARD DRAWING NO.: 38874900
LOGIC DRAWING NO.: 38952600, Sheet 10
STOO-ST15
ARDO-AR15
RS> Fl- RS> F 4
RSl Fl-RSI F4
RNA
RARFl
AO-Al5
FIGURE 3.17. A-REGISTER INTERFACE: BITS 12-15 (CARD 10)
Status Lines 00-15
A-Read Lines 00-15
Gate Local Status (Address Zero)
Gate System Status (Address One)
Read Next Address
Read Data Enable
A-Register Oltputs
GRD
Vj
Vj
11
STIlT
23
NAIl
11
ARlIT
~
12
13
II
14
AlIA
6
AllB
17
C3
GRD
11
23
C4
ST10T
12
11
AR10T
17
STS09
11
ST09T
24
NA09
11
AR09T
15,23
STS06
11
ST06T
24
NA06
11
AR06T
17
RSOF2
Al0A
6
Al0B
17
14
Cl
(A1Q)
C2
12
II
J30. J31
13
NA10
II
(All)
A09A
6
A09B
24
J30, J31
13
14
B9
Bl0
12
II
A06A
6
A06B
24
J30. J31
13
14
GRD
B7
B6
17
(A9)
(A6)
J30. J31
RS1F2
GRD
24
RNAF2
16
RARF2
25
~-6V
~+6V
CI:l
~
0
-:J
I:\:)
~
0
0
~
A
1
2
3
4
5
B
ROIB
ROIA
145
ROIB
ROlA
C
TOIA
T31B
148
TOIA
T3IB
D
ROIB
ROIA
148
ROIB
ROlA
E
TOIA
T31B
148
TOlA
T3lB
CARD TYPE: AV
CARD TITLE: Balance Line Interface
CARD DRAWING NO.: 38874900
LOGIC DRAWING NO.: 38952600. Sheet 12
STOO-STI5
NAOO-NAll
AROO-AllI5
STSOO-STSI5
RSO Fl- RSO F4
RSI FI-RSI F4
RNA
RAHF2
AOO-AI5
'-..
I:\:)
00
td
FIGURE 3.1B. A-REGISTER INTERFACE: BITS 8-11 (CARD 12)
Status Lines 00-15
Next Address 00-11
A- Read Lines 00-15
Local Status Bits 00-15
Gate Local Status (Addref'!s Zero)
Gate System Status (Address One)
Read Next Address
Read Data Enable
A- Register Outputs
c,...,
7
STS07
CD
0
13
ST07T
12
~
I:\:)
CD
0
0
25
NA07
13
AR07T
13
STS06
13
ST06T
II
A07A
8
A079
25
A07C
17
13
14
...........
I:\:)
00
to
95
B6
12
25
NA06
13
AR06T
15
STS05
II
A06A
8
A069
25
A06C
17
13
ST05T
NA05
14
13
AROST
13.32
STS04
13
ST04T
B4
12
26
NA04
13
AR04T
17
RSOF3
II
J30. J31
13
93
26
(A07)
(Aa»
A05A
8
A059
26
AOSC
23
J30.J31
13
14
91
92
12
13
II
14
GRD
(AOS) J30. J31
A04A
8
A049
26
A04C
23
A9
(A04)
J30. J31
A10
17
RS1F3
24
RNAF3
18
RARF3
A
1
2
3
4
5
B
ROIB
ROIA
145
ROIB
ROIA
FIGURE 3.19.
C
TOIA
T3lB
148
TOIA
T31B
D
ROIB
ROIA
148
ROIB
ROIA
E
TOIA
T3lB
148
TOIA
T3lB
Local Status Bits 00-15
STSlO-STSl5
Status Lines 00-15
STOO-ST15
Next Address 00-11
NAOO.-NAlI
A-Read Lines 00-15
AROO-AlU5
Gate Local Status (Address Zero)
R9JF1-RSOF4
Gate System Status (Address One)
RSlFhRSlF4
CARD TYPE: AV
Read Next Address
CARD TITLE: Balance Line Interface
RNA
Read Data Enable
CARD DRAWING NO.: 38874900
RARF4
LOGIC DRAWING NO.: 38952600, Sheet 14 L..-A_0_0_-_Al_5_ _-,-_A_-_R_e..=gt_"s_te_r_Ol_tp..;;.....ut_s_ _ _ _ _ _....J
A-REGISTER INTERFACE: BITS 4-7 (CARD 14)
17
STS03
15
ST03T
12
27
NA03
15
AR03T
15.23
STS02
15
ST02T
"
A03A
8
A038
27
A03C
17
13
14
A7
A8
12
27
NA02
15
AR02T
17
STSOI
15
STOlT
II
A02A
8
A028
27
A02C
23
14
NAOI
AROIT
CA21
J30. J31
AS
12
15
J30. J31
13
AS
28
CA31
"
AOIA
8
A018
28
AOIC
17
13
14
A3
A4
12
"
13
14
CAll
J30. J31
AOOA
8
AOO8
28
FNCTO
7
AI
A2
A
1
2
3
4
5
B
ROIB
ROIA
145
ROIB
ROlA
C
TOIA
T31B
148
TOlA
T31B
D
ROIB
ROIA
148
ROlB
ROIA
E
TOIA
T31B
148
TOIA
T3lB
CARD TYPE: AV
CARD TITLE: Balance Line Interface
CARD DRAWING NO.: 38874900
LOGIC DRAWING NO.: 38952600. Sheet 16
STSOO-STSI5
STOO-STI5
NAOO-NA11
AROO-ARI5
RSO Fl- RSl F4
RSI Fl-RSI F4
RNA
RARF3
AOO-AI5
FNCTO
FIGURE 3.20. A-REGISTER INTERFACE: BITS 0-3 (CARD 16)
IAOI
J30. J31
Local Status Bits 00-15
status Lines 00-15
Next Address 00-11
A-Read Lines 00-15
Gate Local Status (Address Zero)
Gate System status (Address One)
Read NeAt Address
Read Data Enable
A-Register Outputs
Function at Station Address Zero
3.9
FUNCTION CONTROL LOGIC (CARD 17)
READ STATION ADDRESS "0"
The function control logic is implemented by the circuit card in position 17 (see
When the address is "0," D2B provides a true output to enable the input gate to
Figure 3.21).
inverter A2. If the command is a Read command, Read Execute (REX) is true, and
Inverters and drivers incidental to function control are located on
other cards and described in other sections. The "L" prefix used in this description
the input to A2 is true and the output of A2 is false. The output of A2 provides RSOF1
implies a local control signal (station addresses 0-3), pertaining to devices located
through RSOF4 outputs (these are used in the false state to gate local status informa-
within the DCT module package, and includes the DCT logic and the Sequential Setup
tion to the A-read line drivers and transmitters) and provides an input to inverter
and Sequential Status commands.
D3B. The output of inverter D3B provides a true input for the input gate to D3A.
The functional descriptions are divided into
sections based on the function being described.
These sections are not mutually
exclusive, but descriptions are carried only as far as required to describe adequately each function.
The delay input to the D3A gate provides a time delay which is fixed to provide a true
Local Read Ready (LRRY1) output for 1. 0 microsecond after the leading edge of the
Time-to-Execute pulse (REX is timed by TEX). This timing insures sufficient time
for transmission of information, and the Ready signal drops at the end of this timed
3.9.1
Local Station False (LST AF)
delay and remains false until REX goes false.
This output, when false, indicates that the station address being used is addressing
READ STATION ADDRESS "1"
a local station. When a station is addressed (STA true) and when the address is less
than 04 (CSBO, CSCO, and CSDO all true), the input to inverter E 1B is true and the
The sequence for address "1" is the same as described above for address "0," except
E1B output is false.
for the inverters used. The outputs RS1F1 through RS1F4 are false as described for
LSTAF is used in the false state to control station addresses 02
and 03. If the device address is not a station (STA false) or if the address is larger
RSOF1 through RSOF4. The RS1Fl through RS1F4 outputs are used in the false state
than 04 (one or more of the CSBO, CSCO, or CSDO inputs are false), the input to
to gate System Status (status of devices connected to the DCT) to the transmitters.
inverter E1B is false and the output is true.
The status word bit assignments for station addresses "0" and "1" are listed below.
LSTAF in the true state indicates that
a loc.al station is not being addressed.
a.
Input at Station Address "0" (DCT Status).
A-Register Bit
3.9.2
o
Station Addresses "0" and "1"
If the LSTAF output is false, the input to inverter E1A is false and the output of E1A
is true, which enables the input gates to inverters C2A and D2A. When the address
is "0" (CSEO true), the input to D2A is true and the output of D2A is false.
If the
address is "1" (CSE1 true), the input to C2A is true and the output of C2A is false.
When the address is either "0" or "1," a false input is provided for the input gates
of inverters C3A, C3B, and D3A. These inverters provide read or write control
outputs for stations within the DCT module; read is controlled by the Read Execute
(REX), and write is controlled by the Write Execute (WEX), as described below.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function (and source if not DCT)
Ready
Protect Fault Interrupt
End-of-Sequence Interrupt (1574)
External Sync Interrupt
Line Sync Clock Interrupt (1573)
1574 Present in System
1573 Present in System
Protected (PR.OTECT switch in position 2 or 3)
End of Sequence (1574)
External Sync Enabled to Sync Line 2
b. Input at Station Address "1" is used to read the system status lines
EXTERNAL SYNC CONTROL, EXTERNAL SYNC, AND PROTECT
on the DCB.
FAULT INTERRUPT CONTROL
WRITE STATION ADDRESS "0"
The functions performed with station address "0" include control of four flip-flops
used for External Sync Enable (B4) , External Sync Interrupt Enable (C4), External
When the station address is "0," the false output of inverter D2A starts at the local
Sync Interrupt (D4), and the Protect Fault Interrupt. Various control signals and
read or write cycles (outputs LRRY, LRHR, and LWHR become true), and the LWRY
A-register bits are used for these control functions, as described below. For these
output gate and the A5B inverter input gate are enabled. The output of A5A is
functions, the station address must be "0" and WEX must come true as described
normally true; therefore, LWRY goes true at this time. When the Write Execute
above.
(WEX) input goes true, the input to A5B is true and the output of A5B is false. The
that the FNCTO (Function at Station Address "0") output is true.
A5B false output provides the FNTF1 through FNTF3 outputs (used in the False state
the flip-flops are enabled by the FNCTO signal.
The following descriptions assume that these conditions have been met and
Input gates to all
to indicate a Function (Write) for devices within the DCT) and provides a false input
to inverter A4. The true output of A4 enables the input gates to the sync and Inter-
Master Clear
rupt flip-flops, provides an input to the A5A gate, and provides the FNCTO (Function
at station 0 address) output. The time delay input to the A5A gate provides a 1. 5-
The Master Clear Input (MCLF1, used in the False state to indicate a Master Clear)
microsecond delay and causes the A5A inverter to remain true for 1. 5 microseconds
when false, provides a false input to inverter E5B. The output of E5B goes true and
after WEX comes true.
clears (resets) all four flip-flops.
This delay allows time for the function to be executed.
When the 1.5-microsecond delay time elapses, the LWRYoutput goes false and
remains false until WEX goes false.
The functions at station address "0" are as
Sync Enable Flip-Flop
listed in the table below.
a.
Set
Output at Station Address "0" (DCT Functions)
When FNCTO is true and the A11B input is true (A-register bit 11), flip-flop B4 is
A-Register Bit
o
2
3
4
5
6
7
set.
Clear DCT
Reset Protect Fault Interrupt
Reset End-of-Sequence Interrupt
Reset External Sync Interrupt
Disable End-of-Sequence Interrupt
Enable End-of-Sequence Interrupt
Disable External Sync Interrupt
Enable External Sync Interrupt
The set side of B4, when in the True state, enables the input gate to line
driver A and provides a true output for status bit 09 (STS09).
indicates that the External Sync is connected to SYN2.
STS09, when true,
When the EXTSN (External
Sync Input) goes true, all inputs to the AND gate at the input to the SYN2 line driver
are true (C5A output is normally true), and the SYN2 output goes true.
After 300
nanoseconds the output of C5A goes false, and the SYN2 output goes false.
8
9
10
11
12
13
14
15
Disable External Sync from Sync 2 Line
Enable External Sync to Sync 2 Line
Disable 1573 Output from Sync I Line
Enable 1573 Output to Sync 1 Line
Disable 1573 Interrupt
Enable 1573 Interrupt
b.
Reset
When FNCTO is true and the AIOB input is true (A-register bit 10) or MCLFI is
false as described above, flip-flop B4 resets and remains reset until set again with
a FNCTO command.
When set, the C4 flip-flop provides a true set output which enables the input gate to
following paragraph. The set output provides a true output for the protect fault
the C5B line driver. This line driver provides an output to the interrupt lines and can
status bit which is STSOI.
be OR'ed with one or more other interrupt outputs. With the input gate enabled, the
b. Reset
input to C5B goes true whenever an External Sync Interrupt occurs (flip-flop D4 set)
and remains true until D4 and/or C4 is reset by a FNCTO command as described above.
When FNCTO is true and the AOIC input is true (A-register bit 01), or MCLFI is
false as described above, flip-flop E4 resets and remains set until it is set by PFNS
External Sync Interrupt Flip-Flop
as described above.
a.
Set
During the set state of E4, the reset output provides a false output to inverter
When the EXTSN (External Sync Input) input goes true, flip-flop D4 is set (C5A
E5A.
output is normally true), and a true input is provided for the input gate to inverter
with one or more other NTOI inverter outputs.
C5A.
as long as E4 is set.
C5A acts as a leading edge detector to provide a sync pulse for a period of
300 nanoseconds.
E5A provides a true output connected to interrupt line 01 and may be OR'ed
The input to E5A remains true
At the end of the 300-nanosecond period, the input to C5A goes
true and the C5A output goes false.
C5A thus produces a 300-nanosecond, positive-
going pulse at the leading edge of the EXTSN pulse.
When true, the set side of the
Provision is made to OR another input to E5A via pin 39.
When false, the input
on pin 39 also provides a true output on NTOIT as long as it remains false.
As
D4 flip-flop provides a true input to the line driver C5B. If the input gate of C5B is
pin 39 is not currently connected to any input, it can be disregarded but should not
enabled (enable flip-flop C4 is set), the input to C5B goes true and remains true
be tied to ground.
until D4 and/or C4 is reset.
WRITE STATION ADDRESS "1"
b.
Reset
When the station address is "1," both inputs to the gate at C2A are true, the input to
When FNCTO is true and the A03C input comes true (A-register bit 03) or when the
C2A is true, and the C2A output is false. This false output provides an input for the
MCLFI input goes false as described above, the External Sync Interrupt flip-flop D4
local Read and Write controls as described above; it also provides false input to C2B.
resets and remains reset until the next EXTSN pulse occurs.
The output of C2B is true, providing the LST41 output.
Protect Fault Interrupt Flip-Flop
This command is used to
acknowledge an interrupt from the 1573 Line Synchronized Timing Generator.
The
A-register is not used for this operation.
a.
Set
No response is sent if the 1573 is not present.
A Reply is sent if the 1573 is present
When a protect fault interrupt occurs (in other words, the PFNS input is true),
and has sent an interrupt, and the interrupt is reset. A Reject is sent if the 1573 is
flip-flop E4 sets.
present but has not sent an interrupt.
Flip-flop E4 remains set until it is reset as described in the
21
CSEI
20
STA
-::J
21
CSSO
t\:)
(0
21
CSCO
21
CSDO
21
CSEO
20
12
c...:>
(0
LSTAF
39
FNTFI
23
FNTF3
32
WEX
LWRY
19
AIlS
FNCTO
0
0
0
"""()
REX
20
7
STS09
10
Al0S
18
PFNS
16
AOIC
LRHRF
23,39
12
LWHRF
23, 32, 39
16
LRRYF
23, 38
1UI
3300pf
+6V
14
A07C
14
A06C
9,39
SYN2T'
tI
I Ir--
+6V
2
R3
2401l
R4
30011.
~;~
RI
1.2 K
16
1I
A03C
MCLFI
R5
~+6V
NOTE:
*
NOTE:
"*
300Jl
~-6V
F:\CTU
STSOO-STSl5
NTOI-NT15
SYK~
B
C
D
148
148
D24
D24
D24
D24
148
D34
F24
F24
D24
F24
A
NOTE'
INVERTERS WITH
FOUR OUTPUT DIODES
TIED TOGETHER.
INVERTERS WITH FOUR OUTPUT
DIODES TIED TOGETHER.
E
024
DCKT
F24
D24
CARD TYPE: BN
CARD TITLE: Functitm Control
CARD DRAWING NO.: 3~905500
LOGIC DRAW1NG NO.: 38952600, Sheet 17
EXS!'lF
REX
LRIIR
L\\llR
LRRY
EXTSN
LSTAI
RSOFl-RSOF4
RSI Fl-RSI F4
JUMPER -
Function at Station Address Zero
Loc;ll Status Bits Oll-15
Interrupt Lines UI-15
S)llC Source KO. 2
External Sync Interrupt l False)
Head Execute
Loca Read Here
Local Write lIere
Local Head Ready
External Sync Input
Local Station Address NO. I
Gate Local Status (Address Zero)
Gate System Status (Address One)
FIGURE 3.21. FUNCTION CONTROL LOGIC (CARD 17)
f-i'~
Ti=,
I
~
QI
7
I1
OUT
!~
-6V-=
**
BOARD IS SUPPLIED WITH JUMPERS
BETWEEN INPUT a OUTPUT TERMINALS
OF DISCRETE CIRCUIT E I
JUMPER TO
BE REPLACED BY SIGNAL CONDITIONING CIRCUIT ASDE TERMINED BY E~GR
CSEO-CSE3
STA
CSBO-CSll3
CSCO-CSC3
CSDO-CSD3
V·/EX
AlOB-AOiC
PFNS
MCLFI
LSTAF
LWRY
FNTFl, FNTF2
Decoded Address Bits 0, I
Station Addres3
Decoded Address Bits 6, ..
Decoded Address Bits 4, 5
Decoded Address Bits 2, 3
Write Execute
A-Register Bits
Protect Fault lnterrupt Status
!llaster Clear Input
Local Station (False)
Local Write Ready
Function False I, 2
3.10.1
RESPONSE CONTROL LOGIC (CARD 18)
3.10
The response control logic (Card 18), with the function control logic, maintains
Basic Response Timing
When a device is addressed, a response [Read Here (RHR) or Write Here (WHR)] is
control of the responses sent to the computer. These responses include data inputs
transmitted to the neT. The addressed device transmits a Read Ready (RRY) or
and the Reply, Reject, Character Input, and the Interrupt signal used by the nCT
Write Ready (WRY) if ready to perform the specified operation. Upon receipts of a
module. Table 3.2 lists the responses in order of precedence.
Read or Write command from the computer, the nCT examines the RHR, WHR, RR Y,
The condition with
the highest precedence determines the response; all other conditions are ignored.
and WRY lines. If the device is both Here and Ready, a Read Execute (REX) or Write
Execute (\VEX) is transmitted to the device. The device acknowledges the Execute
TABLE 3.2. RESPONSE PRIORITIES
signal by dropping the Ready line, and a Reply (RPy) is transmitted to the computer.
PRECEDENCE
CONDITION
RESPONSE
This description assumes the nCT is connected, no protect fault exist, and a Reject
is not generated by the device. See Figure 3.22 for basic response timing.
1
Not connected and not a Connect command
None
2a
Unprotected command and PROTECT switch in position 2
Reject
2b
Unprotected command and PROTECT switch in position 3
Reply and
Interrupt
3a
Addressed device Here and Ready:
Q-REGISTER LINE
7
0.1 !,sec
__ __ ~J\!AXIMUM
\
--l
I
L ___ _
ADDRf:SS LINES
Generate REX or WEX and wait 2 ",sec from
leading edge of Read or Write, then:
If Ready drops in time and RJT is false
Reply
If Ready drops in time and RJT is true
Reject
If Ready does not drop in time
None
3b
Addressed device Here but not Ready
Reject
3c
Addressed device not Here
None
4
1574 Sequential Addressing Unit not in system:
Sequential Setup or Sequential Status command
__ -1
READ READY (RRY) OR
WRITE READY (WRY)
Reject
Any No-Address command
Reject
Station Address 00 and Write (set DCT functions)
Reply
5b
Station Address 00 and Read (present DCT status)
Reply
I~L _ _ _ _ _ _ _
J
I
READ EXECUTE (REX) OR
WRITE EXECUTE (WEX)
1. 0 !,sec
l\!AXn!t;~!
I
:
":
/\1-..:..
1- - -
pi
.
0.45 !,sec
;\!AXI~!ml
/
~I------
~,---I
NOTES:
A REJECT IS SENT INSTEAD OF A REPLY IF RJT IS TRUE WHEN READY DROPS.
5d
If 1573 not in system
None
If 1573 interrupt sent
Reply
NO RESPONSE IS SENT IF THE ADDRESSED DEVICE IS NOT HERE.
If 1573 interrupt not sent
Reject
NO RESPONSE IS SENT IF READY DOES NOT DROP IN TIJ\!E (WITHIN 4.0 fLSEC OF READ OR WRITE).
Station Address Oland Read (present system status)
Reply
A REJECT IS SENT INSTEAD OF AN EXECUTE IF THE ADDRESSED DEVICE IS HERE AND NOT READY.
ADDRESS BEING INCREMENTED FOR SEQUENTIAL OPERATION (NO-ADDRESS Co:.l;\IA~'D ONL'tl.
1-1347B
NOTE: Cases 4 and 5 are special cases of 3.
FIGURE 3.22.
..j
j! / '\
REPLY
Station Address 01 and Write (1573 Line Synchronized
Timing Generator):
I
I
\
_______..J1;
READ OR WRITE
Random Address command in mode 2 or 3
I
I
None
5a
5c
7
READ HERE (RHR) OR
WRITE HERE (WHR)
RESPONSE TIMING DIAGRAM
-
I
.
~
3.10.2
of BIB is true, and if a Read or Write input is true, the connected flip-flop is set.
Command Formats
When true, the set output of E1 provides an enable input to the CIA inverter gate and
provides the connect
CONNECT
(C~NT)
output.
This output is used on Card 15 to enable the
Character Input transmitter gate. The reset output of E1 provides a false signal for
The format for Connect commands is shown below.
A Connect command is defined
one input to the E2 inverter.
as any command whose W-field is "0" and whose E-field matches the equipment
number of the nCT.
When any command is executed, a flip-flop in the nCT is set
which allows Continue commands to be recognized.
b.
Reset
This "connected" flip-flop is
reset by any command addressed to another equipment or by a Master Clear.
It is
If the Connect (CNCT) input is false and the Q15F input (Not Continue) is true, or if
the Connect Reset
not reset by a clear function.
(C~NR)
input is true, the Connected flip-flop is reset and remains
reset until set as described above.
W="O"
E
StaHon Address
J
CONTINUE
The general format for Continue commands is shown below. A Continue command is
defined as any commandwith a "I" in bit 15 when the connected flip-flop is set.
CONNECT COMMAND FORMAT
The mode field is used by the 1574 Sequential Addressing Unit and 1571 Chaining
Buffer Channel and must be "0" or "I" if the 1574 is not present in the system.
Connect Flip-Flop
a.
Set
Channel Address
When the Connect (CNCT) input is true, the output of inverter B1A is false to inhibit
resetting the connected flip-flop (E1). The input to inverter BIB is false, the output
CONTINUE COMMAND FORMAT
J
3.10.3
Inverter B3 acts as an inverted AND gate for the output of E5B (false at this time)
Normal Response Sequence
and the output of CIA, which goes false at the end of the 250-nanosecond delay.
During this sequence it is assumed that the DCT is connected, the device is Here and
When both of these inputs are false, the output of B3 comes true, providing a true
Ready, and no protect faults occur.
state TEX (Time-to-Execute pulse), which is transmitted to the device.
When the Read or Write pulse goes true, the
output of the Read or Write receivers goes true, providing one true input to inverter
E5B. A true input is also provided to enable the input gates to inverter E4B (Device
Since the Device-Not-Ready reset output enabled the WEXT and REXT gates, and the
Response).
Read Here or Write Here inputs provided a true input to these gates, the Write
The Read Ready or Write Ready signals provide another true input to
the E4B gate, and the output of E4B goes false and remains false until the Read or
Write Ready line is dropped.
Execute (WEXT) or Read Execute (REXT) ouput comes true at the leading edge of the
Time-to-Execute pulse, and TEX, WEXT or REXT remain true until the ready line
is dropped by the device.
E5B provides a false input to the TEX inverter (B3). The output of the E5B inverter
also provides a false input to E4A (Read or Write) and the output of E4A comes true
The response control logic of the DCT now waits forthe addressed device to drop the
to start the 500-nanosecond Read or Write pulse delay and to start the 3.4-micro-
Read Ready (RRYF comes true) or the Write Ready (WRYF comes true) line.
second Internal Reject Delay at the input to the E4B inverter. Inverter D2A provides
the ready line drops, the input to the Device Response inverter (E4B) goes false and
the 500-nanosecond Read or Write delay.
The Read or Write pulse is delayed 500
When
the output of E4B becomes true, providing a true input to set the Reply (E3) flip-flop.
nanoseconds after the leading edge of the Read or Write command pulse; then the
The delay at the input of the set gate provides a 50-nanosecond delay which acts as a
output of D2A goes false, the output of D2B goes true and provides the input to start
noise filter for the Reply flip-flop.
the Read or Write pulse at the input to E2, and the time-to-execute delay at the input
true and the Reject flip-flop has not been set, a 450-nanosecond delay at the input to
to inverter CIA.
the Reply transmitter (D4 and C4) is started to allow the Reply flip-flop to settle.
When the set output of the Reply flip-flop comes
After the 200-nanosecond delay time has elapsed, the input to the Reply transmitter
When the E2 inverter output comes true, the reset input gates to the Device-Not-
comes true and the reply is transmitted to the computer.
Ready flip-flop (D3) are enabled. Since the device is both Here and Ready, all inputs
to either the Read gate or the Write gate are true and the Device-Not-Ready (D3)
After the computer receives the reply, the Read or Write command line is dropped,
flip-flop is reset.
causing the output of E5B to go true dropping TEX and WEXT or REXT, and resetting
the Reply flip-flop.
The Read or Write pulse output of E2 remains true for 60 nanoseconds, as determined by the delay, and drops false after the delay time has elapsed.
E5B also provides a true input to E4A, the false output of E4A provides an input to
D2A.
The true output of D2A sets the Device-Not-Ready (D3) flip-flop, which dis-
When the output of D2B goes true, the input to CIA is delayed for 250 nanoseconds,
ables the REXT and WEXT output gates.
as determined by the delay, and the output of CIA remains true during the 250-nano-
provides a true input to D2B, and the output of D2B goes false.
second delay time to inhibit the Time-to-Execute (TEX) inverter B3.
the Ready state for the next command.
The D2A output is coming true and also
The DCT is now in
I
3.10.4
DEVICE PROTECTED WHEN AN UNPROTECTED COMMAND OCCURS
Device Protect Sequence
The unprotect false (UNPF) line of the decoded data channel is used to inhibit the
normal use of the DCT PROTECT switch.
PROTECT Switch in Position 2
When this input is false (0 volts), the
addressed station accepts all commands with the proper station address.
With the PROTECT switch in position 2, the input to inverter CIB (the Program
Protect bit of the command PR02) is false, and the output of CIB is true, disabling
If the device has a Program Protect switch, the switch controls the protect re-
the DIB inverter (Disables Execute) and enabling the input gate to the reject trans-
sponses. If the device has no switch and accepts unprotected commands, the UNPF
mitter.
line is false when the device is addressed.
(TEX) . During this response cycle, the Ready lines from the device, and the state
This allows a Reject to be transmitted directly during Time-to-Execute
of the Device Ready inverter (E4B) are ignored, the Device-Not-Ready flip-flop (D3)
If the UNPF line is true when a station is addressed, the station is protected against
is not reset, and the response cycle proceeds normally, except for these alterations:
protect faults by the PROTECT switch in the DCT.
the Reply and Reject flip-flops are not set and the Reject signal is transmitted during
The UNPF line, when false,
provides the response control logic inputs (UNP2 and UNP3). Both these inputs are
TEX time.
true when the UNPF line is false.
DCT cycles out, resetting the response logic to the Ready state for the next command.
If the UNP2 and UNP3 inputs are true and the device addressed is a station, the
AND gate inputs to inverters CIB and E5A are both true.
PROTECT Switch in Position 3
The outputs of these
inverters provide false inputs for the Execute Enable inverter (DlB). Since the DDT
input is normally false, the output of DIB is true.
The computer responds by dropping the Read or Write command and the
The result of this is that the
With the PROTECT switch in position 3, the response cycle proceeds as described
above except that the output of inverter E5A provides a true signal to enable the set
PROTECT switch on the DCT (providing inputs PR02 and PR03) is ignored, and the
input of the Reply flip-flop and to enable the Protect Fault Interrupt (PFNS) output
Enable Execute is true regardless of the state of the Program Protect bit during
gate.
the present command.
Protect Fault Interrupt output comes true and is transmitted to the computer.
When the Read or Write pulse comes true, the Reply flip-flop is set, and the
The
Reject flip-flop (C3) is not set during this cycle, so the input gate to the Reply transWhen the UNPF input is in the true state, the addressed device is protected by the
mitter is enabled.
PROTECT switch of the DCT.
nanosecond delay time has elapsed, a Reply is sent to the computer. The computer
If the UNPF line is true, UNP2 and UNP3 are false,
and the AND gate inputs to inverters CIB and E5A are disabled.
In this condition
When the Reply flip-flop set output comes true and after the 200-
responds by dropping the Read or Write command, and the DCT cycles out to the
the response depends upon the setting of the DCT PROTECT switch as described
Ready state for the next command.
below, with normal responses occurring unless there is a protect fault.
described above.
Figure 3.24 shows the timing of both sequences
A
TIME DELAYS
,
RIlY OR WRY
1
13
0
'I
r-
C
E
F
I
I I
--1
'I
WRlT~E
iI
II II
I
--- -lI\.f--
'I
I
(' I
___ ,I-L-
'I
1 1
D2A INYEnTER. _ _ _ _ _-+,_-I~
I
,II
--+-I~v 1
D2B INYERTER _ _ _ _
1
(E2)
1 1
~
I'
iii
DVR (E4B)
1 1
I
1
I
I
1
"
1
,
,.L..
1- - - -V I
I
II
1- - - ~
1
1 1
I
,
"
------+:--I.~
FLIP-FLOP (D3.:..,)
~;~)AND
:1
l: i
-1--1-4-~-I--~r
(REXTI...l.I.0BIIo..,I;I,W"""""-IEXT",-1
II
-+--+'-+-'__4-_ _I,...J)1
RPY FLIP-FLO...
P ____
REPLY
__
I; I;
:- ---H,- - -
it-
~I- - - 1"'L--
-.l-.---Ij'--L.-~---+--"I:L..----J
j
1
-- -
n-
TIME DELAY DESCRIPTIONS
A
500 'Is
B
60
'Is
n
A
DELAYS
,
on
IlHY
WHY
IN(;OHED
HEAD
on
H
I ,
1
I ]"-1- - - l - - \ - - - - - - - -l-II I
- - - - - - 71------ ,- ----l---L----------II I 1
, - - - - - - - - - - - ~
C ---,
WIUn:
OVH
HiNOHED
1
I'
---~I- ~t--
I
-l- -
-r -- - ---
1I
--1-1--
- - - - - - -'-,-,- - -,- - -' - - - - - - - -1l- ~I
02A
I
:--...J1 :
::: : : : : :: : :: : : :
:::D OR WHlT_E_D_E_L_A_YE_D_ _ _ _
~
, 1
---41-0---1-1--11-+1------1: ___ J-L1
1 1
,
I I
READ OR WRIT.w..E. l,;":PJlo:..;\lL,, ,"SEl<.,_
DNR
TI~IE
I I
::::::~~~I~,---I~~~~I__~
INPUT COJIIMAND
)
READ OR
_ _ _- J
If
(;
-r:~
II - - - - - - - - - - - ~
READ/WHITE _ _ _- - - - J
1
I
DNR FLIP-FLOP
-----------~----'--,
1
I
---I - - - - - - - - - - - ++1
,
---:-----.:.h--+-:---Ir -+-1
TEX
n
: : : 'FF
PROTECT SWlTCH
IN POSITION 3
I
,
(
)
I
: :: : : : : : : : : : :
~
~
I 1--1 ___________ ~r-
REPLY
PROTECT SWITCH
IN POSITION 2
-- -- --
":':'; :RE~JEC':" T~II--1-:
!
+-:-----J
I
rl
-
-
-
-
-
-
I I
-
-
-
-
I't-~
.
I
ALLOWS CONNECT FLIP-FLOP TO SETTLE.
TIME DELAY DESCRIPTIONS
LEADING EDGE DETECTOR PULSE USED AS STROBE.
A
500 'Is
ALLOWS CONNECT FLIP-FLOP TO SETTLE.
C
250 'Is
COMBINED WITH TIME DELAY B, ALLOWS 250 'Is FOR DNR FLIP-FLOP TO SETTLE.
D
0-2 fLsec
WAITING FOR RESPONSE.
B
60 'Is
E
50 'Is
NOISE FILTER FOR REPLY.
C
250 'Is
COMBINED WITH TIME DELAY B, ALLOWS 250 'Is FOR DNR FLIP-FLOP TO SETTLE.
F
200 'Is
ALLOWS RPY FLIP-FLOP TO SETTLE.
D
0-2 fLsec
WAITING FOR RESPONSE.
G
INDETERMINATE
COMPUTER RESPONSE TIME TO DROP READ OR WRITE.
E
50 'Is
NOISE FILTER FOR REPLY.
REPLY (F) DELAY DISCHARGE.
F
200 'Is
ALLOWS RPY FLIP-FLOP TO SETTLE.
G
INDETERMINATE
COMPUTER RESPONSE TIME TO DROP READ OR WRITE.
H
::20 'Is
REPLY (F) DELAY DISCHARGE.
H
:: 20 'Is
1-1331A
. LEADING EDGE DETECTOR PULSE USED AS STROBE.
1-1328
FIGURE 3.23. NORMAL RESPONSE CYCLE
FIGURE 3.24. DEVICE PROTECT CYCLE
3.10.5
Internal Reject Sequence
RRY OR WRY
output goes false as described in the normal response sequence, and the timing
B
II
I
1
1 1
I
~
-------1
If the addressed device responds as Here and Ready, the Device Ready inverter (E4B)
sequence proceeds as in the normal sequence.
.\
TIME DEL.\YS
C ----,
~
DVR
come true.
::
READ/WRITE DELAYED
-----------~
N-
+I-~( I
- -- - - - -- -- -
D3A INVERTER _ _ _ _ _ _
The DCT is then waiting for the device to drop the ready line to acknowledge execuIf the device never drops the ready line during the 2-micro-
-HI
. .__----'
..
READ/WRITE PU=L_S;.;;E_ _ _ _ _l-'
-
I
second interval specified, the Device Ready inverter (E4B) remains inhibited by the
3.4-microsecond delay. The output of E4B never comes true, the Reply flip-flop is
- - - -' - --.~,
-----------fi
: ~:
D2A INVERTER
I
I I
-+-:--I~
DNR FLiP-FLO.,:..P_ _ _ _
never set, and the computer does not receive a response.
TEX AND
1 1
-----------~I,I---
I
:
(REXT~OR;.;. \.;.;.V; :.:EX.:. :T.J. .)---+I--+I-+I----J'r - - - - - - - - - ~
-+I_...I......I---T"l
I
the computer drops the Read or Write command. The Response logic then cycles out
to the Ready state, as described in the normal response sequence.
shows the timing of this internal reject sequence described above.
"
1
I--L-----------,
- - - - - - - - : - ,----:-","T'"I
1-1329A
1
---1-1 -- --- - - - -- -I-r-
REPLY
ates an Internal Reject signal for use by the program for recognition of the fault, and
-.vr' I
1 __________
REPLY FLlP-F...;;L;.;;;O.;..P_ _ _ _
Mter the time delay set for Internal Reject within the computer, the computer gener-
'I
~O HESI'()~SE
-----------n-
II
/
the Device-Not-Ready flip-flop is reset, and the REX and WEXT or REXT outputs
tion of the command.
WITII
___--J·Irt-I--+-,1+-11--+
READ OR WRITE
A Read or Write pulse is generated,
I
COMP('TEH THIES O!'T
NOTE:
FOR TIME DELAY DESCRIPTIONS, SEE FIGURE 3.24.
Figure 3.25
FIGURE 3.25. INTERNAL REJECT CYCLE
3.10.6
Device Rejects Execution Command Sequence
IUlYIJIl WHY
Stations can inhibit execution of commands by the Reject False (RJTF) input. When
the RJTF input is false (indicating of execution), the output of the Reject inverter
(D lA) is true, enabling the set input gate to the Reject flip-flop (C3).
A
TIME DELAYS
I 1
I
"C---,
::::.:.:~
HEAD OH WnITE
DVH
signal comes true, the Reject false input goes true in the device and is transmitted
to the DCT.
The output of DIA, now true, is AND'ed with the output of E4B (Device
I---i 1
1
I I
I
1
VI
I
1 I
I
I I
yl
I
I
I 1
1
I I
I
I
I I
I
I
\
1- --
I 1
1 I
1 1
I
1
I
~I
I
I I
1
READ OR WRITE DELA YED
n
READ OR WRITE PULSE
1
I i
NOTE:
I I
I .\
I
I ---.:II
I---~ 1
I I
1 I
1 I
I-
1
1"
r
1-1327A
I
11
I---{ I
1 1
REJ
Figure 3.26 shows the timing during the device reject sequence described above.
1
1
1 ___
Y
mitter, to allow the Reject flip-flop to settle.
\
1
1 1
-- -I I
I
and the set output starts a 200-nanosecond delay/reject at the input of the trans-
REPLY
~---L--_
I
1 1
II
. ---------tt---f-RJT FLlP-FLO~ - - - - - - 1 T - - - T - -'
the Read or Write command as described in the normal sequence description.
I
I
1
~I
D3A INVERTER
REJECT
I I
I
1 1
I
Reject signal is transmitted to the computer, and the computer responds by dropping
1
I
~
TEX AND (REXT OR WEXn
When the delay time has elapsed, the
I
1 I
DNR FLIP-FLOP
The Reject flip-flop reset output (now false) inhibits the Reply transmitter input gate,
I
I
G
1 1
I I
Response) and the reset output of the Device-Not-Ready flip-flop (D3), setting the
Reject flip-flop.
I
A
D2A INVERTER
The first portions ofthe timing cycle are normal, but when the TEX (time-to-execute)
D
R
1
-- II II
1,1
1 1
\
I
I
I
1
I
I
I
I
II
I
I,
I
I
FOR TIME DELAY DESCRIPTIONS, SEE FIGURE 3.2·1.
FIGURE 3.26. DEVICE REJECT CYCLE
1,1
I1
II
3.10.7
Device Here But Not Ready Seguence
If the addressed device is Here But Not Ready, the RRYF input (Read Ready false)
remains true and the output of inverters D5A (Write Ready) or D5B (Read Ready)
remains false causing the Device Ready inverter (E4B) output to remain true.
The Read or Write pulse is generated as in the normal sequence, and the Time-toExecute (TEX) output comes true, but the WEXT or REXT gates are not enabled
(since the Device-Not-Ready flip-flop was not reset), and the WEXT or REXT outputs
remain false.
With the Device-Not-Ready flip-flop still set and the Device Here inverter, Read
Here (C5A) or Write Here (C5B) output true, the Reject flip-flop set input gate is
enabled, and the flip-flop is set when TEX comes true. The Reply is inhibited by the
'reset side of the Reject flip-flop (now false), and the set side starts the delay at the
input to the reject transmitter.
After the delay time, the Reject signal is trans-
mitted and the computer responds by dropping the Read of Write command.
1 A I BI
I
r
i
C
,
1
HIli OIl WIlY
------) II
IlE.-\O OIl WIUTE
1 I I
Dva
I 1I
I 1I
D2A INVERTER
I ,I
READ OR WRITE DELAYED
I I I
D3A INVERTER
I
I Ij I
I
1 I I
READ/WIUTE PULSE
I 11
I
I
I I 1
DNR FLIP-FLOP
I 11
I
1
1
1
1
TEX (ONLY)
(
1 11
IlEPLY
I II
1
I 11
REJ
Y
I
1
I
I
REJECT
TIME DELAYS
The
response logic cycles out to the Ready state as described in the normal sequence.
Figure 3.27 shows the timing of the device here and not ready sequence described above.
1-1330A
Figure 3.28 is a logic diagram of Card 18.
I II
NOTE:
I
F
G
I" I
1I
------~
I
I -------rtI
I I
1_______ J-t-
:-------~
I
I I
I-------+tI
11
I-------+t-
:-_n-UhI--------W-
1-------""lL
r-------\L
FOR TIllIE DELAY DESCRIPTIONS, SEE FIGURE 3.2,1.
FIGURE 3.27. DEVICE HERE BUT NOT READY CYCLE
I I
I'.EX-'-
20
REXT
20
03
04
+6V
A
1
2
3
4
5
T31B
ROIA
ROIA
B
D24
TOIA
148
ROIB
ROIB
C
D24
D24
F34
T31B
D24
D
D34
024
F24
TOIA
D24
E
F24
148
F24
D34
D24
NOTE: RESISTOR
R 23 IS TO BE SELECTED FOR A DELAY
OF 3.3usTO 3.:Jus.
RHRF
WHRF
RARFl-RARF4
CONT
RDT
CARD TYPE: BB
CARD TITLE: Response Control
CARD DRAWING NO.: 38896800
LOGIC DRAWING NO.: 38952600, Sheet 18
TEX
WEX
PFNS
RPYT, RPYF
REPLY
.---().-~------+-----~Z9
P FNS
17
1--~-----~24
RPYT
23
9 1---------~21
RPY F
23
J30. J31
"-----~
Read Here (False)
Write Here (False
Read Data Enable
Connect Signal
Reject Data Transfer EDT
(NAD + RAL)
Time-to-Execute Pulse
Write Execute
Protect Fault Interrupt Status
Reply True, False
FIGURE 3.28. RESPONSE CONTROL LOGIC (CARD 18)
SRSFI. SRSF2
REX
CNCT
QO-Q15
COlm
UNP2, UNP3
PRO.2, PROJ
DDT
...,RYF
RRYF
Simulate Response Signals
Read Execute
Connect
Q-Register Inputs
Reset
Vnprotected
PROTECT S-.itcb in Positions 2, 3
Disable Data Transfer EDT
(NAD + RALI
Write Ready (False)
Read Ready (False)
ADDRESS CONTROL LOGIC (CARD 19)
3.11
output of the Q14 receiver provides a false input to the other gate of C4A. With both
input gates having false signals, the output of C4A (CHLT) is true.
The address control logic is implemented by the printed circuit card in position 19
(see Figure 3.29) and provides decoding for QOO, Q04 through Q06, and Q12 through
Q15.
These inputs from the Q-register of the computer are combined in various
3.11.4
Write Ready {WRY F)
ways described below to form the control signals to determine the addressing modes.
The Write Ready False (WRYF) output is normally true. A Local Write Ready signal
No-Address (NAD)
3.11.1
(LWRY going true or LWRYF going false) creates a Write Ready condition causing
WRYF to go false.
It is necessary for Write Ready to drop (WRYF going true) to
When Q04, Q05, and Q06 are all true and Q15 is false, the input to inverter C4B is
cause a response. This is inhibited if the output of inverter D4B is true. The output
true. The output of C4B, when false, disables the input gates to C4A, and the STAT
of D4B is true for any Read Only command, as determined by the inputs to E3A, NAD
output gate. The output of C4A is inverted by D5A to provide a true NAD output and
to
ena~.le
the input gate to E3A. The NAD output, when true, specifies a No-Address
data transfer command used for direct
3.11.2
I/o
(No-Address) AND'ed with QO (Inhibit Execute) and Random Address Read only (Q15
set and Q12, Q13, and Q14 reset).
with no address.
Station Address (STAT)
3.11.5
The Station Address true (STAT) output is true if the NAD output is false and Q15 is
This output is connected with the output of another inverter at the input of logic cards
false.
in positions 22 (Address Decoder) and 25 (1574 Sequential Addressing Unit). The two
This output indicates that the device being addressed is a station and is true
only during Function and Connect or Status and Connect commands.
The STAT out-
inputs to these cards (Q15 and Q07) are AND'ed to form the final input signal.
put is transmitted on the DCB and is also used to enable the inhibit gate for the
protect fault reject logic on Card 18.
When Q15 is false, the Q07 input to the cards is inhibited from the decoding logic.
Since a station address consists only of bits QOO through Q06, the Q07 bit is only
3.11.3
Channel Address (CHL T)
inhibited during those commands associated with station addresses.
When the
address is a channel, the Q07 bit is used in the address decoding.
The Channel Address True (CHLT) output indicates that a channel is being addressed
and is true for direct I/O commands and all random -addressing commands.
3.11. 6
The output of inverter C4B provides a false input to both gates of inverter C4A when-
For this output Q15 is inverted and is provided as·an output to the response control
ever the direct I/O commands are used.
logic (Card 18).
This makes the CHLT output true during
these commands.
Q15F in the True state enables the reset input gate to the Connect
flip-flop. allowing the Connect flip-flop to be reset. Q15F in the False state inhibits
the .reset gate of the Connect flip-flop, and thus specifies a Continue command, as
When Q15 is true, the output of inverter E4 is false, providing a false input to one of
Q15F is false only during those commands when Q15 is true (Random Addressing and
the gates to C4A. If Q14 is false, which it is during Random Address commands, the
Sequential Addressing).
3.11. 7
Read Execute (REXT) and Write Execute (WEXT)
3.11.10
Sequential Address Setup or Status (SASS)
The Read Execute (REXT) and Write Execute (WEXT) outputs are used for all data
This control signal is used when a sequential address module is being addressed. It
transfers, unless inhibited, and are false only during direct I/O commands with QOO
is used by the 1574 as well as by other sequential addressing modules external to the
false or during Random Address Read Only commands.
DCT package (e.g., 1797/1571).
In all other cases either
REXT or WEXT is true for a time specified by the response control logic. They
will come true at the leading edge of the Time-to-Execute (TEX) pulse, unless
When both Q14 and Q15 are true, the inputs to E2B and E4 inverters are true, and
inhibited by a Read Only command.
the outputs provide false inputs to inverter E3B.
output (SASS) is true.
The conditions creating a false output for these signals are described above in the
With both these inputs false, the
When Q15 is true and Q14 is false (during Random Address
mode commands), the SASS output is false.
WRYF descriptions.
3.11. 8
QOOA and QOOB
3.11.11
The QOO outputs are true whenever the Q-register bit 00 is true.
They are used to
SAl\I1T and SAM2T
These two signals are used for control of special sequential addressing modules other
inhibit execution of commands in the No-Address mode as described above and also to
than the 1574 (1797/1571).
provide outputs used by the Address Decoder and the 1574 Sequential Addressing Unit.
the Sequential Setup and Sequential Status formats, which are defined as commands
When the Address Decoder is installed, QOO is combined with Q01 to form the CSEO-
inverters E2B and E4 (both false at this time) provide inputs to inverter E3B, which
Commands controlling these modules are programmed in
having both Q14 and Q15 set ("l's"). When both Q14 and Q15 are true, the outputs of
CSE3 addressing outputs. When the 1574 is installed, QOO is used as the set input to
acts as an inverted AND gate for False State signals and provides a true output (SASS).
the least significant bit of the address registers.
The Sequential Address or Setup (SASS) output enables the output gates for SAl\I1T
and SAM2T. If Q12 is true, the SAM1T output is true, and if Q13 is true, the SAM2T
3.11.9
Simulate Response
output is true.
The Simulate Response signals (SRSF1 and SRSF2) are normally true, enabling the
normal responses described above.
and REXT outputs are inhibited.
3.11.12
Random Address and Lockup (RAL)
However, for any Read Only command, WEXT
Therefore, the addressed device does not respond
During the Random Address and Lockup commands, which are rejected if the 1574
by dropping its· Ready signal (RRY or WRY going false). The input gate to D4B (Read
Sequential Addressing Unit is not installed, a data transfer is executed at the speci-
Only and TEX) causes SRSFI and SRSF2 to go false when the Time-to-Execute (TEX)
fied address and the next address is set equal to the address specified by the
pulse occurs.
current command.
The SRSF1 and SRSF2 outputs go to Card 18 to cause the AR lines to
be gated to the A-read line transmitters and to provide inputs to simulate the RRYF
output to go true (Read Ready dropping).
.
~
During the Random Address and Increment commands, also rejected if the 1574 is
not installed, a data transfer is executed at the specified channel address and the
This group of control signals is used for all sequential addressing modules.
next address is set to one greater than the address specified by the current command.
The RAL signal is gated by the Address Decoder logic (Card 18) to cause a Reject
3.11. 13
ADD 1A and ADD 1B
Data Transfer (RDT) and a Disable Data Transfer (DDT) if the Address Decoder is
These outputs are used to increment the Address register of the 1574 during the RAL
installed in addition to the 1574.
commands described above. ADD1A is true during Random Address commands when
Q12 is true and increments the Next Address register during RAL commands
The RAL output is decoded from Q13, Q14, and Q15.
When Q13 is true, Q14 is
(Random Address and Increment).
false, and Q15 is true, all three inputs to the RAL gate are true, and the RAL signal
is available for gating on other logic cards. If anyone or more of the inputs is false,
ADD1B and Q01 are AND'ed at the input to the 1574 (Card 27) and increment the Next
the RAL output is disabled.
Address register when Q01 is true during a No Address command.
C..:l
CO
SAMIT
20
QI2
C5
C6
ADDIA
28
QI3
C7
C8
RAL
QI4
C9
CIO
0
~
I:\:)
CO
0
0
SAM2T
..........
I:\:)
00
0:1
Q07A
7
QI5
01
02
22. 23
20
22.25
23
QOOA
22.28
QOOB
28
18
REXT
20
WEXT
20
SRSFI
18
20
QO
AI
A2
SRSF2
ADDRESS
CABLES
J32.{33
Q4
Q5
OS
NAD
A9
AIO
BI
B2
133
B4
Q04A
22.26
Q04B
26
Q05A
22. 26
QOSB
26
Q06A
22. 25
Q06B
25
LWRYF
17
LWRY
18
TEX
ADDIB
28
WRYF
18
RI4
II
23
18
22.23
*
42
*
INVERTERS WITH FOUR
OUTPUT DIODES TIED TOGETH£R
~+6V
~-6V
SAMlT
AnOIA
1
2
3
4
5
A
ROlA
ROlA
ROlA
ROlA
ROlA
B
ROlA
ROlA
ROlA
ROlB
ROlB
C
ROlB
ROlB
ROlB
D24
145
D
ROIB
ROlB
ROlB
D2-l
024
E
D2-l
D2-l
1-18
CARD TYPE: BH
CARD TITLE: Address Control
CARD DRAWING NO.: 38896900
LOGIC DRAWING NO.: 38952600. Sheet 19
FIGURE 3.29.
QO-QI5
RAL
SAM2T
QOOA-QI5B
SASS
Sequential Address Module 1
Add "1" to 1574 Register
(Q12 • Q14 • Q15)
Q- Register Inputs
Random Address and Lockup
Sequential Address Module 2
Condition Q-register Bits
Sequential Address and Setup
ADDRESS CONTROL LOGIC (CARD 19)
STA
CHL
NAD
AnDIB
LWRY
SRSFl. 2
WRYF
Station Address
Channel Address
No Address
Add "1" to 1574 Register
(No Address· QOl)
Last Address Write Ready
Simulate Response Signals.
Write Ready (False)
3.12
LONG-LINE DRIVERS (CARDS 20 AND 21)
Bus.
Figures 3.30 and 3.31 are logic diagrams of the Long-Line Drivers
(Cards 20 and 21).
The line drivers provide sufficient amplification for
The line drivers provided on the printed circuit cards in card positions 20 and 21
driving 40 normal loads.
provide noninverting amplification of the signals connected to the Data and Control
load on each line.
An isolation diode must be provided for each
GJ
22.Jl3I)/~7~f)/G
z
2
7
I'
Z
l.2.J
1"3'
LS
~
I'~~T 37
E
40 PR¢ Z
Z2,23
L
39 OIL l
2?L4
C.'i4PT~CShO
"
I:)
Z
+6V
r-- --
~
CHL.T 36
AN113~hNh3
R3
240A
1/4W.
Z
2
R6
• SAMI
~
30
K
32 SAMI
1.J23
lZ.I
l4
C"'Z~C5A2
~1.2K
r Ilaw
CR3:
':)- _6 ______ [;{~.J
2
IN2
SCHEMATIC FOR DISCRETE CIRCUIT
I'J
SAMlT~
EJ
~
0
31 SAM2
~Z3
ZZ.J
24
cr''''~CSA3
Z
~0
A
B
I
2
3
""J(T A
CKTB
CKTC
4
enD
5
CKT£
""K1F
6
C
FIGURE 3.30.
D
E
CKTG itKHI
CKTH CKTP
CKT J
CKTK ~KTQ
KTl ~KTR
c~n~
CARD TYPE: BM
CARD TITLE: Long Line Drivers
CARD DRAWING NO.: 38897100
LOGIC DRAWING NO.: 38952600, Sheet 20
LONG-LINE DRIVERS (CARD 20)
REX
WEX
SYNI
PRO
CHL
STA
SAMI-SAM2
DIG
ANAI-ANA3
CSAO-CSA3
Read Execute
Write Execute
Sync Source NO. 1
Protected Command
Channel Address
Station Address
Sequential Addressing Module 1. 2
Digital Input or Output (Address OXX)
Analog NO.1. 2. 3
Decoded Address Bits 8, 9
·
~
[S8~~CS/5.s
2
ZZ,Z7
r----~---------------------~------~
llJB
CSE~CS£O
2.
RI
2./17
R3
Z40n
1/4W.
R4
300.n.
1/4W
1.2K
119W
OUT
40 LOGIC
LOADS
'2, /7
SCHEMATIC FOR DISCRETE CIRCUIT
~
- --
-a-
~~----------~~~
~
I--_-__-_--_-~> +0 V
A
8
C
DIE
I
cn~
2
3
4
',..:nc
~
C~~
CtT 1-1 KT"
!::TD
CKT K)C(f Q
5
"nE
""KT licn ~
6
CKT F
CKTMi
CK"T
C"-T J'
CARD TY PE: BM
CARD TITLE: Long Line Drivers
CARD DRAWING NO.: 38897100
LOGIC DRAWING NO.: 38952600, Sheet 21
FIGURE 3.31. LONG-LINE DRIVERS (CARD 21)
CSBO-CSB3
CSCO-CSC3
CSDO-CSD3
CSEO-CSE3
Decoded
Decoded
Decoded
Decoded
Address
Address
Address
Address
Bits
Bits
Bits
Bits
6,
4,
2,
0,
7
5
3
1
3.13.2
ADDRESS DECODER (CARD 22)
3.13
Enable Data Transfer
The Address De.coder (Card 22) provides inverters and gates for partially
The EDT (Enable Data Transfer) is a pin which is grounded by each card of the
decoding the Q-register inputs; these inputs have, in some cases, terms AND'ed
1574, thus providing a false signal input to the Address Decoder when the 1574
for additional control features and are not the actual A-Register contents.
is also installed.
Each
set of four inverters decodes two input bits in straight binary fashion as shown
3.13.3
in Table 3. 3.
TABLE 3.3. TYPICAL TRUTH TABLES
Random Access Lockup
The RAL input is the Random Access Lockup signal used for the 1574 and is not
used in the Address Decoder.
EDT, NAD, and HAL inputs.
TRUE
TRUE
QOIA
QOOA
OUTPUT
COMBINATION
QllA
QIOA
0
0
CSEOT
QOIA QOOA
0
0
0
1
CSEIT
QOIA QOOA
0
1
0
CSE2T
QOIA QOOA
1
1
1
CSE3T
QOIA QOOA
1
1
OUTPUT
The B2A inverter acts as a NOR gate for the
COMBINATION
If RAL or NAD come true or if the EDT input is held at ground by any of the
DIGT
QllA QIOA
1
ANA IT
QllA QIOA
1574 cards installed, the DDT (Disable Data Transfer) and the RDT (Reject Data
0
ANA2T
QllA QIOA
Transfer) outputs of the card are true, thus disabling and rejecting any transfer
ANA3T
QllA QIOA
of data. ·This interlocking system provides protection for misplacement of hardware and programming errors.
Two additional inverters and several input and output pins are used to provide
interlocking controls for the Address Decoder (see Figure 3.32).
3.13.1
No Address
3.13.4
End of Sequence
The E¢)S output pin is grounded by the Address Decoder to provide a continuously
false E~S output when the Address Decoder is installed. This output and DDT and
The NAn input (No Address is decoded from the Q-register bits to indicate a direct
RDT outputs disable the 1574 if the Address Decoder is installed.
I/O command with no address associated with the command.
bilateral protection for both the Address Decoder and the 1574.
This provides
DIGT
20
CSCOT
21
ANA2T
20
CSC2T
21
~
to
0
-.;J
~
to
0
0
"
~
00
IJ:f
Q11A
15
Q10A
7
ANA1T
20
7
ANA3T
20
40
QOSA
19
CSC1T
21
CSC3T
21
Q04A
19
CSDOT
21
CSAOT
20
CSA2T
20
Q09A
7
CSD2T
21
Q03A
13
CSD1T
21
CSA1T
20
CSA3T
20
Q08A
7
Q02A
11
CSD3T
21
21 ~------------~
CSBOT
21
CSEOT
21
CS82T
21
CSE2T
21
Q01A
9
CSE1T
21
CS81T
21
CS83T
21
QOOA
19
CSE3T
21
8t------~
DDT
18
RDT
18
NOTE:
THIS CARD IS REMOVED
WHEN THE SEQUENTIAL ADDRESSING
OPTION IS ADDED TO THE 1750.
QOOA-Q15B
EDT
A
1
2
3
4
5
B
D34
D34
D34
C
D
D34
D34
D34
D34
D34
E
034
D34
D34
D34
D34
CARD TYPE: BE
CARD TITLE: Address Decoder
CARD DRAWING NO.: 38882200
LOGIC DRAWING NO.: 38925600. Sheet 22
NAD
RAL
DIGT
ANAIT
ANA2T
ANA3T
CSAOT-CSA3T
Condition Q-Regtster Bits
Enable Data Transfer (Grounded by
Cards 23-28)
No-Address
Random Address and Lockup
Digital Input or Output (Address OXX)
Analog 1 (Address 4XX) (True)
Analog 2 (Address 8XX) (True)
Analog 3 (Address CXX) (True)
Decoded Address Bits 8. 9 (True)
FIGURE 3.32. ADDRESS DECODER (CARD 22)
CSBOT-CSB3T
DDT
RDT
CSCOT-CSC3T
CSDOT-CSD3T
CSEOT-CSE3T
EOS
Deexided Address Bits 6. 7 (True)
Disable Data Transfer EDT
(NAD+RAL)
Reject Data Transfer EDT
(NAD+RAL)
Decoded Address Bits 4. 5 (True)
Decoded Address Bits 2. 3 (True)
Decoded Address Bits O. 1 (True)
End of Sequence (Grounded by
this card)
Section Four
MAINTENANCE
4.1
GENERAL
Corrective maintenance procedures, parts removal, and parts replacement can be found in
Control Data publication NO. 84785000. This section provides only fundamental preventive
maintenance instructions and procedures. Since the DCT is located in a cabinet that includes
other modules, some maintenance procedures include the other modules as well as the DCT.
4.2
PREVENTIVE MAINTENANCE PROCEDURES
P~eventive
maintenance includes two basic pro.cedures:
a.
Inspect modular cabinet MG air filters and clean as necessary every two to
three weeks.
b.
Check output of MG power supply at least once a month.
The MG power
supply contains a variac with which the output voltage can be varied to compensate for additional module loading. Whenever modules are added or deleted, check output voltage and
adjust the variac for 208 volts output.
4.3
TROUBLESHOOTING PROCEDURES
There are no normal troubleshooting procedures besides chasing" 1 'sIt and "0 's. "
The response control Card 18 (Figure 3.28) contains the response delay for the Reply
signal.
Resistor R23 is selected to adjust for a nominal response delay of from 3. 3
to 3. 5 microseconds.
39072900/28B
4.1
4.4
PREVENTIVE MAINTENANCE INDEX
TIME
EST. MINS.
LEVEL
PREVENTIVE MAINTENANCE
ITEM
5
Monthly
1.1
Clean Air Filter
5
Monthly
1.2
Check Cooling
2
Monthly
1.3
Check Power Supplies
Bi-Monthly
2.1
Voltage Margins
40
"This PM! is the recommended frequency of performing preventive maintenance on this equipment. Scheduling of this preventive maintenance is a site responsibility. Scheduling may
I
include variations in the recommended frequency due to individual site conditions (e. g., usage,
environment, time, etc.)."
CLEAN AIR FILTER
CHECK/Conditions
Action
1. 60 Hz power off.
2. Snap plate at front bottom of cabinet
removed
1. Vacuum both sides of filter element thoroughly.
a. If filters are very dirty, wash them in a
mild detergent-water solution.
b.
4.2
Place filters vertically while drying to
avoid damage.
39072900/D
CHECK COOLING
Action
CHECK/ Condition
1.
60 Hz power off.
CHECK: Is the red light on at the
bottom of the cabinet?
Yes
No - - - - - - - - 1... 1.
2.
Check operation of vane switch.
Check for presence of 60 Hz or 400 Hz on
either side of lamp. 400 Hz on one side
turns on the lamp, while 60 Hz at the other
side keeps it off.
2. 60 Hz power turned on.
CHECK: Does air circulate upwards
through entire cabinet?
Yes
No -------....,1> 1. Verify blower is operating.
2. Check for any unnatural obstructions.
3. Verify there is a proper allowance for air to
move under cabinet, through -filters and up.
Next Item
CHECK POWER SUPPLIES
CHECK/ Condition
1.
Action
Verify power supplies are creating
+6 VDC and -6 VDC.
39072900/D
4.3
CHECK: Is the proper voltage present?
Yes
No
--------I.~
1
1. Check fuse.
2.
Check 400 Hz supplied to power supply.
3. Check for 'any wiring shorts.
2. Verify termination power (±20 VDC)
is supplied to the module.
RUN VOLTAGE MARGINS
Action
CHECK/ Condition
1., Insure system is configured for running
of appropriate diagnostic for equipment
on 1750. (Interrupts equipment number,
proper inputs or outputs for diagnostic
used, . '.. )
2. Optional testing could be performed to
verify operation of master clear button,
equipment number switch and protect
switch depending on whether customer
desires to use these features as variables.
3.
Run the diagnostic and shock test the
1750 module*
CHECK: Are there any errors?
No
+
Yes --------.~ 1. Isolate and/or replace shock sensitive card
or component.
4. Re-run the diagnostic at ±10% power
supply margins.
CHECK: Are there any errors:
No
+
Yes - - - - - - - -•• 1. Isolate· and/or replace marginal card or
component.
End of PMP
*Equipment that has not been shock tested regularly, should be approached with caution as large
scale failures are possible in older modules.
4.4
39072900/D
.Section Five
DIAGRAMS AND PARTS LI ST
5.1
GENERAL
Included in this section are board layout diagrams for· all cards in the nCT (see Figures 5. 1
through 5. 9).
These diagrams illustrate the positions of the components on each board.
I
Following each diagram is a parts list for that board. Table 5.10 is a module assembly
parts list.
39072900/C
5.1
\
11824400
TOIA
11824500
T31B
11823400
11824400
11824500
148
TOIA
T31B
11827000
11826900
11823400
11827000
11826900
ROIB
ROIA
148
ROIB
ROIA
11824400
11824500
11823400
11824400
11824500
TOIA
T31B
148
TOIA
T31B
11827000
11826900
11823300
11827000
11826900
ROIB
ROIA
145
ROIB
ROIA
Cl
o
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FIGURE 5.1
5.2
BALANCED LINE INTERFACE (AV) CARD, BOARD LAYOUT
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11823600
11823600
11823600
11823600
11823600
D34
D34
D34
D34
D34
11823600
11823600
11823600
11823600
11823600
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D34
D34
D34
11823600
11823600
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FIGURE 5.3.
5.6
ADDRESS DECODER (BE) CARD, BOARD LAYOUT
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FIGURE 5.4.
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EQUlPIIlEI\1'
NUMBER
I
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@*OFF
0- -
REJECT
9
•
8
(COM)
-
I
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PROTECT AND EQUIPMENT SELECT (BG) CARD, PANEL ASSEMBLY
INTERRl"PT
-r
TABLE 5.4. PARTS LIST
PROTECT AND EQUIPMENT SELECT (BG) PANEL ASSEMBLY
PART NO.
QTY.
24523001
1
Switch, Push, SPST (S3)
38923002
1
Swi tch, Rotary (S2)
38851400
1
Switch, Hexadecimal (S1)
24500050
1
Resistor, Composite, 3000, 1/4w, 5% (R11)
39072900/C
DESCRIPTION
5.9
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FIGURE 5.5.
5.10
PROTECT AND EQUIPMENT SELECT (BG) CARD, BOARD LAYOUT
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ORIGINAL
PRIORITY
LE\'EL IS REESTABLISHED
FIGURE 1. SIM:PLIFIED FLOWCHART FOR SCHEDULING A REQUESTED PROGRAM
PROGRAM
a. Parameters to be passed to the program.
b. Request code.
c. Completion priority of the program.
d. Program address.
e. A pointer to the next entry on the thread.
Programs are threaded in order of increasing priority so that the top entry on the full thread
holds the highest priority program. If two or more programs have the same priority level,
programs in this priority level are threaded on a first-come, first-served basis. When a
program in the scheduler stack is removed to be executed, the thread entry point is
added to the list of entries on the empty thread. If a program is requested when no entries
remain on the empty thread (i. e., the stack is full), Q is set negative on the return to the
requester and the request is ignored.
The scheduler stack is built when the Operating System is assembled. The length should be .
four times the number of timer calls and scheduler requests that may be active at anyone
time. As a rule of thumb, 4 x 25 10 or 100 10 usually provides an adequate scheduler
stack. The form of the stack is shown on pages A.13 and A.14.
While the scheduler is determining whether to put a requested entry in the scheduler stack
or to put the running program in the interrupt stack, interrupts are inhibited and the running
program parameters are assigned to volatile. Volatile is a specified area of the system
table region designated at assembly time. It is used by re-entrant program for storage of
necessary parameters and intermediate results.
If the requested program is of higher
priority, the running program parameters are transferred to the interrupt stack and the
requested program is executed. If the requested program is of the same or lower priority,
the· entry parameters are threaded on the scheduler stack. After the determination is made,
the interrupts are re-enabled and the interrupt mask is set to correspond to the current
running priority level.
A.6
The chosen program is then put into execution.
39072900/28B
Interrupt Stack, Interrupt Trap, and Interrupt Mask
The interrupt stack (see Figure 2) consists of up to 16 five-word entries. Each entry holds
data pointers for programs that have been interrupted. The stack is a push -down, pop-up
type. The top-of-the-stack pointer is located at location $B8. It points to the first word of
the next available entry.
The size of the interrupt stack should be the number of interrupt lines used (N) times 5.
Normally this is 16 10 x 5, or 90 locations. The stack size is determined at operating
10
program assembly time. A stack smaller than the full number of interrupt lines times five
is subject to overflow .
. When the interrupt stack entry is due to scheduling up in priority, some parameters from the
interrupted program are saved in the volatile area. The I -register entry in the interrupt stack
holds the address of that portion of volatile which has the remaining program parameters.
Volatile is not released until the higher priority program is terminated and the requesting
program is resumed. The new priority level is established as in the hardware interrupt case.
The interrupt mask is set to the new priority level before entering the requested program.
The ip.terrupt mask allows only interrupts of higher priority than the running programs to
be processed.
All other interrupt lines are suppressed.
The suppressed interrupt lines
remain activated until the mask is reset to the priority level of the interrupt line (or lower).
Dispatcher Operation to Find Next Program
As higher priority programs are completed, they exit to the dispatcher. The next program
is picked off the top of the interrupt or scheduler stack (see Figure 3). The priority level
is lowered by the dispatcher to the level of the proposed program to be executed and the
Mask register is reset.
39072900/28B
A.7
>
ACTIVATE
INTERRUPT
LINE
YES
INHmlT INTERRUPTS.
GO .TO COMMON
INTERRUPT HANDLER
NO
CONDITION
IN UNIT)
HARD'VARE OPERATION
WITHIN INTERRUPTIKG
UNIT AND 1100 CO!\IPl"TER
WAIT UNTIL
PRIORITY IS
LOWERED TO
INTERRUPT
PRIORITY LEVEL
COMMON INTERRUPT HANDLER
1
STORE CU RRENT
PROGRAM ON
INTERRUPT STACK
SET MASK
TO LEVEL OF
INTERRUPT LINE
ENABLE
INTERRUPTS
J
\
EXIT
)
(VIA
INTERRUPT
RESPONSE
ROUTINE)
1-2536
FIGURE 2. SIMPLIFIED INTERRUPT LINE PROCESSING FLOW DIAGRAM
SOFTWARE
$B8
I
POINTER
INTERRUPT STACK
r
SCHEDULEH STACK
SCHTOP
I
POINTER
MASK REGISTER
~
PRIORITY
LEVEL P 3
PRIORITY
LEVEL P 2 \
~
FULL
>STACK
~
PRIORITY
~
LEVEL PI
-
I
It
INTERRUPT TRAP
1
J
TOP OF
FULL
THREAD
LINE J
f-
PRIORITY
f-
LEVEL P4
-
LINE MASKED AT
LEVEL P 3
-
LINE MASKED AT
LEVELS PI- P 2 P 3 AND P 4
4
EMPTY
> STACK
LINE K
PRIORITIES SHOWN AT THE END OF THE PREVIOUS PROGRAM.
-
-
PRIORITY
LEVE-L P 5
PREVIOUS PROGRAM RAN AT LEVEL P 3 > (PI' P 2 , P 4 , OR P 5).
SELECTION OF NEXT PROGRAM PROCEEDS IN TWO STAGES:
a. COMPARE PI TO P 2 . IF PI 2! P 2 , NEXT PROGRAM 1 COMES FROM PI; OTHERWISE PROGRAM COMES FROM P 2 ·
b.CHANGE MASK LEVEL AND CHECK INTERRUPTS AT NEW LEVEL.
LOWER MASK TO NEW LEVEL (PI OR P 2).
IF P 4 2! NEW LEVEL, LINE J INTERRUPTS PUTS NEXT PROGRAM 1 ONTO THE INTERRUPT STACK, THE INTERRUPT LINE IS
ACKNOWLEDGED, THE MASK IS SET TO P 4 LEVEL, AND THE PROGRAM ASSOCIATED WITH P 4 IS EXECUTED. IF P 4 < NEW PRIORITY
LEVEL, LINE J REMAINS MASKED.
LINE K REMAINS MASKED IN ALL CASES SINCE P 5 < (PI' P 2 , P , OR P ).
3
4
1-2538
>
FIGURE 3. SELECTION OF NEXT PROGRAM WHEN PREVIOUS PROGRAM IS COMPLETED
When the ~ask is reset, it may include one or more active interrupt
lines. Those lines are processed. The propose~ next program is moved
to the interrupt stack and the program associated with the interrupting
line is put into execution.
INTERRUPT LINE PRIORITY ASSIGNMENT
For maximum efficiency, the used interrupt lines should be assigned priorities' on a scale
of decreasing order of importance, i. e., line n + l's priority
~
line n's priority. Assign-
ment is made this way because interrupting lines which have been masked are processed in
·line number order when several active lines are unmasked at the same time. In other words,
an interrupt on line 0 is processed before an interrupt on line 1, which in turn is processed
before an interrupt on line 2, etc., when all these active interrupt lines are unmasked at
the same time. Assume, for example, a program operating at priority level 9 ends and the
next highest entry in either interrupt or scheduler stack is priority 3. At the same time,
three interrupt lines are active:
Line
Priority
5
6
10
4
7
8
In this case, the program with priority 3 becomes the next scheduled.
The mask is set to
priority level 3. As soon as interrupts are enabled, all three lines are capable of interrupting.
Line 5 is processed first.
Interrupts are inhibited, the associated priority 4
program is scheduled, the next scheduled program is transferred to the interrupt stack, the
mask is set to level 4, and the interrupts are enabled.
The same processes are repeated
for line 6. Line 6 interrupts, interrupts are inhibited; the level 4 program goes to the
interrupt stack, and the mask is raised to level 7. When the interrupts are again enabled,
the process is repeated.
Line 10 interrupts, interrupts are inhibited, the level 7 program
is added to the interrupt stack, the mask is raised to level 8, and interrupts are again
enabled.
A.10
This program is the next to be executed.
39072900/28B
Two disadvantages to this type of interrupt line assignment are apparent:
a. Each interrupt processing cycle requires 40 to 50 microseconds.
b. The interrupt stack is unnecessarily filled with programs that might have as
well remained masked.
If, in the example given, the lines were assigned priority on a decreasing scale of priorities,
the first interrupt would have been line 5 at priority 8, and the associated program would
have been executed as soon as the interrupt mask was reset.
STACK ORGANIZATION
Two types of stack organization are discussed, threaded and push down/pop up. Both are
described below.
Threaded Stacks
The address of the top of the threaded scheduler stack is held in SCHTOP. Assume programs are requested as shown:
Program
Priority
Temporal Sequence
of Requests
A
6
1
L +0
B
10
2
L+4
C
9
3
L+8
D
10
4
L+C
E
8
5
L + 10
F
6
6
L + 14
Location of First
Word of Entry
The programs are loaded into the stack in the order of column 3 with the top of each entry
shown in column 4. They are threaded as follows:
39072900/28B
A.l!
POINTER
Pointer
SCHTOP
FffiSTWORD
OF ENTRY
L
L +,4
SCHTOP
L+4
Thread
L+7
L+C
L +14
Thread
L +2
L + 14
L +18
Thread
L + 16
L' + 18
L+4M
Thread
L+A
L+C
Thread
Last
FFFF*
* Indicates entry
is at the end of
stack.
As programs are removed from the stack the pointer ($B4) is moved consecutively through
L + 4 -..L + C -..L + 8
~L
+ 12 -.. L +0 -.. L + 14. It can then be reinitialized to
L + 0 awaiting a new schedule of programs.
A.12
39072900/28B
The form of the scheduler stack is shown below:
15
9
I
N
$B4
14
RC = 9
7
8
I I
4
o
3
I
CP
C
Address of
top entry
on full
thread
Thread
Q
N+4
N +8
CP = Completion priority (level at which this entry runs) .
Thread = Points to address of first word of next less important entry.
RC
=
9
=
Request code 9 (schedule) (refer to Control Data Publication
No. 60170400, Paragraph 3.2.5)
Q
=
Contents of the Q-register at the time of request.
C = Program
add~ess.
Push-Down, Pop-Up Stacks
In the push-down, pop-up interrupt stack, entries are added to the top of the stack and the
pointer is moved to the next available entry. When an entry is removed, it is always the top
(last) entry and the pointer is moved back five words.
39072900/28B
A.I3
N
Filled
Entries
N +5
Pointer Word
for Stack
N + 5 (n)
$BS
N+A
I
.......
N+F
N + 14
~
Co)
Unused
Entries
t..s
~
rI.l
'+-4
0
~
N + 19
0
~
N + IE
~~
The structure of an entry is shown below:
Entry for
interrupted
program A
N
Q-Register
N+l
A-Register
N+2
I-Register
N+3
N +4
*
Address P
Priority Level of Program A
P = Execution address. when program A was interrupted
* Overflow indicator (bit 15)
A.14
39072900/2SB
The structure of the in1:errupt trap is
($100 + 4n)
Line n
interrup
trap
*
Address P
RTJ to $FE
Priority Level of Interrupt
Address R
R = Address of the program that responds to the. interrupt.
* Overflow indicator (bit 15)
39072900/28B
A.15
Significant parameters and tables are
$FE
. Address of Common ~terrupt Handler
15 14 13 12 11 10
MASKT'
A.16
-1
9
8
7
6
5
4' 3
2
1
o~Internal
Line Number
1111100000111111
o
1
1
1
1
10
0
0
0
0
1
1
1
1
1
1
+1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
+2
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
+3
0
0
0
1
1
0
0
0
0
0
1
1
1
1
1
1
. +4
0
0
0
1
1
0
0
0
0
0
1
1· 1
1
1
1
+5
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
+6
0000000000111111
+7
0000000000111111
+8
o
0
0
'0
0
0
0
0
0
0
0
0
0
1
1
1
+9
o
0
0
0
0
0
o·
0
0
0
0
0
0
1
1
1
+10
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
+11
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
+12
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1· 1
+13
0
0
O' 0
0
0
0
0
0
0
0
00
0
0
1
. +14
0
0
o. 0
0
0
0
0
0
0
0
0
0
0
0
1
+15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
39072900/28B
LINE/PRIORITY
LEVEL
LINE
PRIORITY LEVEL
0
15
1
13
2
13·
3
B
4
B
5
B
6
MASKED
7
MASKED
B
MASKED
9
MASKED
10
MASKED
11
5
12
5
13
3
14
3
15
2
LINES CAN NEVER
BE PROCESSED
MASK REGISTER
Entry from MASKT table corresponding
the current priority level
$BB
Address of highest priority entry on
the interrupt· stack
39072900/2BB
A.17
COMMENT SHEET
MANUALTITLE __~1~7~5~0~DuA~T~A~AN~D~CQQ~N~T~R~Q~L~T~E~R~NIT~NuA~Lw(~DQC~T~)~_____________________
PUBLICATION NO. __3_9...;.0...;.,7_2_90.-.0..-.-________ REVISION _ _ _....;;D~___________"·
FROM
NAME: ________________________________________________________________________
BUSINESS ___________________________________________________________________
ADDRE~:
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