AT49F512 512K (64K X 8) 5 Volt Only Flash Memory 49F512

AT49F512 EPROM 49F512 Race Drivin' Y2K Fix

User Manual: 49F512

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Features

•Single Voltage Operation

– 5V Read

– 5V Reprogramming

•Fast Read Access Time - 50 ns

•Internal Program Control and Timer

•8K Bytes Boot Block With Lockout

•Fast Erase Cycle Time - 10 seconds

•Byte-by-Byte Programming - 10 µs/Byte

•Hardware Data Protection

•DATA Polling For End Of Program Detection

•Low Power Dissipation

– 30 mA Active Current

– 100 µA CMOS Standby Current

•Typical 10,000 Write Cycles

Description

The AT49F512 is a 5-volt-only in-system programmable and erasable Flash Memory.

Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with

Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 50

ns with a power dissipation of just 165 mW over the commercial temperature range.

When the device is deselected, the CMOS standby current is less than 100 µA.

To allow for simple in-system reprogrammability, the AT49F512 does not require high

input voltages for programming. Five-volt-only commands determine the read and

programming operation of the device. Reading data out of the device is similar to

reading from an EPROM. Reprogramming the AT49F512 is performed by erasing the

entire 512K of memory and then programming on a byte by byte basis. The typical

byte programming time is a fast 10 µs. The end of a program cycle can be optionally

Rev. 1027D–04/99

512K (64K x 8)

5-volt Only

Flash Memory

AT49F512

512K (64K x 8)

5-volt Only

CMOS Flash

Memory

Pin Configurations

Pin Name Function

A0 - A15 Addresses

CE Chip Enable

OE Output Enable

WE Write Enable

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

DIP Top View

A15

A12

I/O0

I/O1

I/O2

GND

VCC

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

PLCC Top View

I/O0

A14

A13

A11

A10

I/O7

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O6

A12

A15

VCC

VSOP Top View (8 x 14 mm) or

TSOP Top View (8 x 20 mm)

Type 1

A11

A13

A14

VCC

A15

A12

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

(continued)

AT49F512

detected by the DATA polling feature. Once the end of a

byte program cycle has been detected, a new access for a

read or program can begin. The typical number of program

and erase cycles is in excess of 10,000 cycles.

The optional 8K bytes boot block section includes a repro-

gramming write lock out feature to provide data integrity.

The boot sector is designed to contain user secure code,

and when the feature is enabled, the boot sector is perma-

nently protected from being reprogrammed.

Block Diagram

Device Operation

READ: The AT49F512 is accessed like an EPROM. When

CE and OE are low and WE is high, the data stored at the

memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state whenever CE or OE is high. This dual-line

control gives designers flexibility in preventing bus conten-

tion.

ERASURE: Before a byte can be reprogrammed, the 64K

bytes memory array (or 56K bytes if the boot block featured

is used) must be erased. The erased state of the memory

bits is a logical “1”. The entire device can be erased at one

time by using a 6-byte software code. The chip erase code

consists of 6-byte load commands to specific address loca-

tions with a specific data pattern (please refer to the Chip

Erase Cycle Waveforms).

After the chip erase has been initiated, the device will inter-

nally time the erase operation so that no external clocks

are required. The maximum time needed to erase the

whole chip is tEC. If the boot block lockout feature has been

enabled, the data in the boot sector will not be erased.

BYTE PROGRAMMING: Once the memory array is

erased, the device is programmed (to a logical “0”) on a

byte-by-byte basis. Please note that a data “0” cannot be

programmed back to a “1”; only erase operations can con-

vert “0”s to “1”s. Programming is accomplished via the

internal device command register and is a 4 bus cycle

operation (please refer to the Command Definitions table).

The device will automatically generate the required internal

program pulses.

The program cycle has addresses latched on the falling

edge of WE or CE, whichever occurs last, and the data

latched on the rising edge of WE or CE, whichever occurs

first. Programming is completed after the specified tBP cycle

time. The DATA polling feature may also be used to indicate

the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device

has one designated block that has a programming lockout

feature. This feature prevents programming of data in the

designated block once the feature has been enabled. The

size of the block is 8K bytes. This block, referred to as the

boot block, can contain secure code that is used to bring up

the system. Enabling the lockout feature will allow the boot

code to stay in the device while data in the rest of the

device is updated. This feature does not have to be acti-

vated; the boot block’s usage as a write protected region is

optional to the user. The address range of the boot block is

0000H to 1FFFH.

Once the feature is enabled, the data in the boot block can

no longer be erased or programmed. Data in the main

memory block can still be changed through the regular pro-

gramming method. To activate the lockout feature, a series

of six program commands to specific addresses with spe-

cific data must be performed. Please refer to the Command

Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software

method is available to determine if programming of the boot

block section is locked out. When the device is in the soft-

ware product identification mode (see Software Product

Identification Entry and Exit sections) a read from address

location 00002H will show if programming the boot block is

locked out. If the data on I/O0 is low, the boot block can be

programmed; if the data on I/O0 is high, the program lock-

FFFFH

2000H

1FFFH

0000H

AT49F512

out feature has been activated and the block cannot be

programmed. The software product identification code

should be used to return to standard operation.

PRODUCT IDENTIFICATION: The product identification

mode identifies the device and manufacturer as Atmel. It

may be accessed by hardware or software operation. The

hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for

the Atmel product.

For details, see Operating Modes (for hardware operation)

or Software Product Identification. The manufacturer and

device code is the same for both modes.

DATA POLLING: The AT49F512 features DATA polling to

indicate the end of a program cycle. During a program

cycle an attempted read of the last byte loaded will result in

the complement of the loaded data on I/O7. Once the pro-

gram cycle has been completed, true data is valid on all

outputs and the next cycle may begin. DATA polling may

begin at any time during the program cycle.

TOGGLE BIT: In addition to DATA polling the AT49F512

provides another method for determining the end of a pro-

gram or erase cycle. During a program or erase operation,

successive attempts to read data from the device will result

in I/O6 toggling between one and zero. Once the program

cycle has completed, I/O6 will stop toggling and valid data

will be read. Examining the toggle bit may begin at any time

during a program cycle.

HARDWARE DATA PROTECTION: Hardware features

protect against inadvertent programs to the AT49F512 in

the following ways: (a) VCC sense: if VCC is below 3.8V (typ-

ical), the program function is inhibited. (b) Program inhibit:

holding any one of OE low, CE high or WE high inhibits

program cycles. (c) Noise filter: Pulses of less than 15 ns

(typical) on the WE or CE inputs will not initiate a program

cycle.

Notes: 1. The 8K byte boot sector has the address range 0000H to 1FFFH.

2. Either one of the Product ID exit commands can be used.

Command Definition (in Hex)

Command

Sequence Bus

Cycles 1st Bus

Cycle 2nd Bus

Cycle 3rd Bus

Cycle 4th Bus

Cycle 5th Bus

Cycle 6th Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 Addr DOUT

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr DIN

Boot Block

Lockout(1) 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

Product ID

Entry 3 5555 AA 2AAA 55 5555 90

Product ID

Exit(2) 3 5555 AA 2AAA 55 5555 F0

Product ID

Exit(2) 1 XXXX F0

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to VCC + 0.6V

Voltage on OE

with Respect to Ground ...................................-0.6V to +13.5V

AT49F512

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

3. VH = 12.0V ± 0.5V.

4. Manufacturer Code: 1FH, Device Code: 03H

5. See details under Software Product Identification Entry/Exit.

Note: 1. In the erase mode, ICC is 90 mA.

DC and AC Operating Range

AT49F512-50 AT49F512-70 AT49F512-90

Operating

Temperature (Case)

Com. 0°C - 70°C0°C - 70°C0°C - 70°C

Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C

VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10%

Operating Modes

Mode CE OE WE Ai I/O

Read VIL VIL VIH Ai DOUT

Program(2) VIL VIH VIL Ai DIN

Standby/Write Inhibit VIH X(1) XXHigh Z

Program Inhibit X X VIH

Program Inhibit X VIL X

Output Disable X VIH XHigh Z

Product Identification

Hardware VIL VIL VIH

A1 - A15 = VIL, A9 = VH, A0 = VIL(3) Manufacturer Code(4)

A1 - A15 = VIL, A9 = VH, A0 = VIH(3) Device Code(4)

Software(5) A0 = VIL, A1 - A15 = VIL Manufacturer Code(4)

A0 = VIH, A1 - A15 = VIL Device Code(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

ILI Input Load Current VIN = 0V to VCC 10 µA

ILO Output Leakage Current VI/O = 0V to VCC 10 µA

ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC

Com. 100 µA

Ind. 300 µA

ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3mA

CC(1) VCC Active Current f = 5 MHz; IOUT = 0 mA Com. 30 mA

Ind. 40 mA

VIL Input Low Voltage 0.8 V

VIH Input High Voltage 2.0 V

VOL Output Low Voltage IOL = 2.1 mA 0.45 V

VOH1 Output High Voltage IOH = -400 µA 2.4 V

VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

AT49F512

AC Read Waveforms(1)(2)(3)(4)

Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.

2. OE may be delayed up to tCE - tOE, after the falling edge of CE without impact on tCE or by tACC - tOE after an address change

without impact on tACC.

3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and

Measurement Level

tR, tF < 5 ns

Output Test Load

Note: 1. This parameter is characterized and is not 100% tested.

AC Read Characteristics

Symbol Parameter

AT49F512-50 AT49F512-70 AT49F512-90

UnitsMin Max Min Max Min Max

tACC Address to Output Delay 50 70 90 ns

tCE(1) CE to Output Delay 50 70 90 ns

tOE(2) OE to Output Delay 30 35 0 40 ns

tDF(3)(4) CE or OE to Output Float 0 25 0 25 0 25 ns

tOH Output Hold from OE, CE or

Address, whichever occurred first 000ns

Pin Capacitance

f = 1 MHz, T= 25°C(1)

Symbol Typ Max Units Conditions

CIN 46pFV

IN = 0V

COUT 812pFV

OUT = 0V

AT49F512

AC Byte Load Waveforms

WE Controlled

CE Controlled

AC Word Load Characteristics

Symbol Parameter Min Max Units

tAS, tOES Address, OE Set-up Time 0 ns

tAH Address Hold Time 50 ns

tCS Chip Select Set-up Time 0 ns

tCH Chip Select Hold Time 0 ns

tWP Write Pulse Width (WE or CE)90ns

DS Data Set-up Time 50 ns

tDH, tOEH Data, OE Hold Time 0 ns

tWPH Write Pulse Width High 90 ns

AT49F512

Program Cycle Waveforms

Chip Erase Cycle Waveforms

Note: OE must be high only when WE and CE are both low.

Program Cycle Characteristics

Symbol Parameter Min Typ Max Units

tBP Byte Programming Time 10 50 µs

tAS Address Set-up Time 0 ns

tAH Address Hold Time 50 ns

tDS Data Set-up Time 50 ns

tDH Data Hold Time 0 ns

tWP Write Pulse Width 90 ns

tWPH Write Pulse Width High 90 ns

tEC Erase Cycle Time 10 seconds

PROGRAM CYCLE

INPUT

DATA

ADDRESS

5555 5555

2AAA

tBP

tWPH

tWP

A0-A15

DATA

tAS tAH tDH

tDS

80 10

55 55

5555 5555 5555

BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5

2AAA 2AAA

tWPH

tWP

A0-A15

DATA

tAS tAH

tEC

tDH

tDS

5555

AT49F512

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec in AC Read Characteristics.

Data Polling Waveforms

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec in AC Read Characteristics.

Toggle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling

input(s)

2. Begining and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

Data Polling Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay (2) ns

tWR Write Recovery Time 0 ns

HIGH Z

An An An An An

I/O7

A0-A15

OEH

Toggle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tOEHP OE High Pulse 150 ns

tWR Write Recovery Time 0 ns

AT49F512

Software Product Identification Entry(1)

Software Product Identifcation Exit(1)

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. A1 - A15 = VIL.

Manufacture Code is read for A0 = VIL;

Device Code is read for A0 = VIH.

3. The device does not remain in identification mode if pow-

ered down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 1FH

Device Code: 03H

Boot Block

Lockout Enable Algorithm(1)

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. Boot block lockout feature enabled.

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 90

ADDRESS 5555

ENTER PRODUCT

IDENTIFICATION

MODE(2)(3)(5)

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA F0

ADDRESS 5555

EXIT PRODUCT

IDENTIFICATION

MODE(4)

LOAD DATA F0

ANY ADDRESS

EXIT PRODUCT

IDENTIFICATION

MODE(4)

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 80

ADDRESS 5555

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 40

ADDRESS 5555

PAUSE 1 second(2)

AT49F512

Note: 1. The AT49F512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices

with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block to be in the higher

address range should contact Atmel.

Ordering Information(1)

tACC

(ns) ICC (mA) Ordering Code Package Operation Range

Active Standby

50 30 0.1 AT49F512-50JC

AT49F512-50PC

AT49F512-50TC

AT49F512-50VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

40 0.3 AT49F512-50JI

AT49F512-50PI

AT49F512-50TI

AT49F512-50VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

70 30 0.1 AT49F512-70JC

AT49F512-70PC

AT49F512-70TC

AT49F512-70VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

40 0.3 AT49F512-70JI

AT49F512-70PI

AT49F512-70TI

AT49F512-70VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

90 30 0.1 AT49F512-90JC

AT49F512-90PC

AT49F512-90TC

AT49F512-90VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

40 0.3 AT49F512-90JI

AT49F512-90PI

AT49F512-90TI

AT49F512-90VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

Package Type

32J 32-lead, Plastic, J-leaded Chip Carrier Package (PLCC)

32P6 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

32T 32-lead, Thin Small Outline Package (TSOP) (8 x 20 mm)

32V 32-lead, Thin Small Outline Package (VSOP) (8 x 14 mm)

AT49F512

Packaging Information

.045(1.14) X 45˚ PIN NO. 1

IDENTIFY

.025(.635) X 30˚ - 45˚

.012(.305)

.008(.203)

.021(.533)

.013(.330)

.530(13.5)

.490(12.4)

.030(.762)

.015(.381)

.095(2.41)

.060(1.52)

.140(3.56)

.120(3.05)

.032(.813)

.026(.660)

.050(1.27) TYP

.553(14.0)

.547(13.9)

.595(15.1)

.585(14.9)

.300(7.62) REF

.430(10.9)

.390(9.90)

AT CONTACT

POINTS

.022(.559) X 45˚ MAX (3X)

.453(11.5)

.447(11.4)

.495(12.6)

.485(12.3)

1.67(42.4)

1.64(41.7) PIN

.566(14.4)

.530(13.5)

.090(2.29)

MAX

.005(.127)

MIN

.065(1.65)

.015(.381)

.022(.559)

.014(.356)

.065(1.65)

.041(1.04)

.630(16.0)

.590(15.0)

15 REF

.690(17.5)

.610(15.5)

.012(.305)

.008(.203)

.110(2.79)

.090(2.29)

.161(4.09)

.125(3.18)

SEATING

PLANE

.220(5.59)

MAX

1.500(38.10) REF

*Controlling dimensions: millimeters

INDEX

MARK

18.5(.728)

18.3(.720)

20.2(.795)

19.8(.780)

0.25(.010)

0.15(.006)

0.50(.020)

BSC 7.50(.295)

REF

8.20(.323)

7.80(.307) 1.20(.047) MAX

0.15(.006)

0.05(.002)

5REF

0.70(.028)

0.50(.020)

0.20(.008)

0.10(.004)

*Controlling dimensions: millimeters

INDEX

MARK

12.5(.492)

12.3(.484)

14.2(.559)

13.8(.543)

0.25(.010)

0.15(.006)

0.50(.020)

BSC 7.50(.295)

REF

8.10(.319)

7.90(.311) 1.20(.047) MAX

0.15(.006)

0.05(.002)

5REF

0.70(.028)

0.50(.020)

0.20(.008)

0.10(.004)

32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-016 AE

32P6, 32-lead, 0.600" Wide, Plastic Dual Inline

Package (PDIP)

Dimensions in Inches and (Millimeters)

32T, 32-lead, Plastic Thin Small Outline Package

(TSOP)

Dimensions in Millimeters and (Inches)*

32V, 32-lead, Plastic Thin Small Outline Package

(VSOP)

Dimensions in Millimeters and (Inches)*

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are

not authorized for use as critical components in life support devices or systems.

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1027D–04/99/xM

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AT49F512 512K (64K X 8) 5 Volt Only Flash Memory 49F512

AT49F512 EPROM 49F512 Race Drivin' Y2K Fix

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