690 18365 002_Altos_1086_2086_Maintenance_Jan87 002 Altos 1086 2086 Maintenance Jan87
690-18365-002_Altos_1086_2086_Maintenance_Jan87 690-18365-002_Altos_1086_2086_Maintenance_Jan87
User Manual: 690-18365-002_Altos_1086_2086_Maintenance_Jan87
Open the PDF directly: View PDF .
Page Count: 569
Download | |
Open PDF In Browser | View PDF |
1086/2086 Maintenance Altos Computer Systems 1086/2086 Maintenance Copyright Notice Manual Copyright©1986 Altos Computer Systems Programs Copyright©1986 Altos Computer Systems All rights reserved. Printed in U.S.A. Unless you request and receive written permission from Altos Computer Systems, you may not copy any part of this document or the software you received, except in the normal use of the software or to make a backup copy of each diskette you received. Trademarks The Altos logo, as it appears in this manual, is a registered trademark of Altos Computer Systems. UNIX8 is a registered trademark of AT&T Bell Laboratories. UNIX System IIl'M is a trademark of AT&T Bell Laboratories. XENIX8 is a registered trademark of Microsoft Corporation. MULTIBUS8 is a registered trademark of Intel Corporation. IBM8 is a registered trademark of International Business Machines Corporation. PC/AT8 is a registered trademark of IBM Corporation. System 34 Double Density (MFM)8 is a registered trademark of IBM Corporation. Scotch8 is a registered trademark of 3M Corporation. 3279/SNA is an Altos Implementation of ACCESS/SNA developed by Communications Solutions, Inc. WorkNet8 is a registered trademark of Altos Computer Systems. Limitations Neither Altos nor its suppliers make any warranty with respect to the accuracy of the information in this manual. Altos Computer Systems reserves the right to make changes to the product described in this manual at any time and without notice. FCC Warning This equipment generates, uses, and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual, may cause interference to radio communications. It has been tested and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference when operated in a commercial environment. Operation of this equipment in a residential area is likely to cause interference in which case the user, at his own expense, will be required to take whatever measures may be required to correct the interference. ABOUT THIS MANUAL This manual contains detailed service information for the technician who is trained in digital electronics, microcomputers, and operating systems. The purpose of this manual is to describe the operation of the 1086/2086 Computer System and provide specific instructions to enable the technician to effectively service the 1086/2086. Careful attention to the preventive and corrective maintenance information contained in this manual will ensure maximum trouble-free operation from the Altos 1086/2086 Computer System. This manual is organized into the following chapters: Chapter 1 System OVerv i " • describes the features and capabilities of the system • provides a hardware overview of the major circuits and peripherals • lists and shows the location of the field replaceable assemblies comprising the system • describes and shows the dedicated and recommended expansion plug-in printed circuit board (PCB) locations • describes and shows the locations of the front and rear-panel controls, connectors, and indicators • discusses the software available for the system Chapter 2 Specifications • lists the pertinent electrical, environmental, and physical specifications for the system iii About This Manual • shows the overall physical dimensions of the' system Chapter 3 Principles of Operation • explains how the pI ug-in PCB subsystems inte,rface to the system through the system bus • describes how the system is initialized or programmed at power-up • describes the programmed steps performed in the main operational sequences • lists the addresses for each device that can be accessed • includes bit definitions for the ports and external registers • includes pertinent timing diagrams and general programmable array logic (PAL) information' Chapter 4 Maintenance' • includes 115/23rtJ VAC conversion instructions • provides cleaning procedures • provides removal and replacement procedures. • provides shipping information Chapter 5 Troubleshooting • discusses troubleshooting aids and techniques • includes detailed troubleshooting procedures using power-up, system-confidence, and field-service diagnostics iv About This Manual Appendices Includes jumper pinning, loopback connector assembly, storage device specifications, and utility program information. Glossary Includes an alphabetical list and definitions of specialized terms and acronyms used in this manual. Index Includes an alphabetical list of names, subjects, or topics contained in this manual with the page numbers where they occur. RELATED PUBLICATIONS The following is a list of publications that contain additional information relating to the 1986/2986 system. The 1186/2186 OWner's Guide is shipped with the system. The remaining publications are optional and are divided into three types: (1) basic (run-time) system manuals that contain information for installing and using the operating system, (2) development system manuals that include reference and tutorial material for programs available in the development system, (3) supplemental information manuals that are referenced in the text of this manual and contain additional information required to understand the operation of the 1986/2986 system. The publications listed here are available through your Altos distributor or directly from integrated circuit manufacturers. Shipped with 1086/2086 Altos 1986/2986 Owner's Guide (Altos part no. 699-16447-XXX) v About This Manual Basic System • Installing XENIX on Your 1086/2086 System (Altos part no. 690-16630-XXX) • Introduction to XENIX (Altos part no. 690-13449XXX) • Directory of XENIX Commands (Altos part no. 690-1664- XXX) Development System Altos Development System set (Altos part no. 583-13801XXX) Supplemental Information • Altos 1086/2086 System Reference Manual (Altos part no. 690-15623-XXX) • Altos 1086/2986 Illustrated Parts List (Altos part no. 699-15625-XXX) • Altos 1086/2086 Remote Diagnostics Instructions (Altos part no. 690-17072-001) • IEEE 796 System Bus Specification (Mu1tibus) • Intel IAPX 286 programmer's Reference Manual • Intel Microsystem Components Handbook • Intel Microprocessor and peripheral Handbook • Intel 8254 Data Book (Mode 2) • National Semiconductor 58167 Applications Note Data Handbook • Advanced Micro Devices 9517 Technical Reference Manual • Zi10g Data Handbook/Technical Manual vi About This Manual • Hitachi HD68459 Data Book • Hitachi Microcomputer Handbook • National Cash Register 5385 SCSI Protocol Controller Data Sheet • Archive QIC-92 1/4-Inch Tape Drive Interface Standard • Archive QIC-24 1/4-Inch Cartridge Tape Drive Format Standard • Archive QIC-36 Basic 1/4-Inch Cartridge Streaming Tape Drive Interface Standard • NEC PD765 Data Sheet • NEC Data Handbook • ANSI X3T9.2/82-2 SCSI Small Computer System Interface • National Cash Register Data Handbook SPECIAL SYMBOLS AND NOTATIONS The following is a list of the special symbols and notations used in this manual. vii About This Manual Symbol/Notation Description * (Asterisk) Used following a capitalized mnemonic or signal name to indicate a nnot n (complement) function or an active low signal. Example: PERR* h Used after a number to indicate that the number is a hexadecimal notation. Example: 25h d Used after a number to indicate that the number is a decimal notation. Example: l6d b Used after a number to indicate that the number is a binary notation. Example: 0lb viii About This Manual • • • 02000 AI tos 1886/2886 Computer System ix j '\ ) '\ j TABLE OF CONTENTS 1 SYSTEM OVERViEW SYSTEM DESCRIPTION • •• • • • • • • • • • Characteristics • . • • • • • • • • • • • • Architecture • • • • • • . • • • • • • • • Configurations. • • • • • • • • • • • • • • Networking. • •• •• • • • • • • • • • Communications. • • • • • • • • Diagnostics • • • • • • • • • • • • • • • • Power-Up Tests • • • • • • • • • User System-Confidence Tests •••• Field-Service Diagnostics. • • • • •• • Hardware • • • • • • • • • • • • • • • • • System Bus • • . • • • • • • • • • • • • Central Processing Unit (CPU) PCB • • • Memory PCB •• • • • • • • • • • • • Communications PCB • •••••••• File Processor PCB • • • • • • • • • • • Controller PCB • • • • • •• • • • • FIELD REPLACEABLE UNITS • • • • • • • • • CONTROLS, CONNECTORS, AND INDICATORS • • • • • Front Panel • • • • • • • • • • • • • • • • Rear Panel • • • • • • • • • • • • • • PLUG-IN PRINTED CIRCUIT BOARD,LOCATIONS. • SYSTEM SOFTWARE. • • • • • • • • • • • • • • • Operating System Programs • • • Address Translation • • • • •••• Disk Performance • • • • • • • • • •.• • Serial Port Performance. • • • • •• Compatibility. • • • • • • • •• • • Diagnostics. • • • • • • • • • • • • • • 2 1-3 1-3 1-3 1-4 1-4 1-5 1-5 1-6 1-6 1-6 1-7 1-7 1-8 1-8 1-8 1-9 1-1~ 1-11 1-12 1-13 1-13 1-15 1-15 1-15 1-17 1-17 1-17 1-17 1-18 SPECIFICATIONS INTRODUCTION • • • • • • • • • • • ELECTRICAL SPECIFICATIONS. • • • ENViRONMENTAL SPECIFICATIONS • PHYSICAL SPECIFICATIONS. • •• xi • • • • 2-3 • • • • • 2-3 2-8 • • 2-8 Table of Contents 3 PRINCIPLES OP OPERATION INTRODUCTION • • • • • • • • • • • • • • • • • BLOCK DIAGRAM DESCRIPTION. • • • • • • • • • • System Bus. • • • • • • . • • • • • • • Central processing unit (CPU) ••• System Memory • • • • • •••• • • • • Communications. • • • • • • • • • • File Processor • • • • • • • • • • • • • • • Controller • • • . • • • • • • • • • • • • • DETAILED CIRCUIT OPERATION • • 0 0 0 • 3-5 3-5 3-5 3-6 3-7 3-7 3-8 3-8 3-9 NOTE For convenience, each of the following PCB subsystem descriptions have a red locator tab on the right edge of the first page. System Bus Interface. • ••• Bus Masters. • • • • • • • • • • • • • • Bus Slaves • • • • • • • • • • • Bus Signals. • • • • • • • • • • • • Data Transfer Operations ••• • Interrupt Operation. • • • • Bus Exchange Lock Operation • • • • • • • • • Timing • • • • Central processing Unit (CPU) PCB • • • CPU Initialization • • • • • • • • • • • Microprocessor . • • • • • ••• • • Microprocessor Address Decoder Logic • • 80286 Memory Map • • • . • • • • • • • • Local Bus Control Logic. • • • • •• Local Bus. • • . . • • • • • • • • • • Calendar Clock • • • • • • • • • • • • • Interrupt Controller • • • • • • . • • • System Memory Accessing and Address Translation • • • • • • • • • • • • • • Tag and Translation RAM Control Logic. • Cache Memory Organization. • • • • • System Bus Arbiter and priority Encoding Logic • • • • • • • • • • • • Microprocessor Ready Generator • • • • • Jumper Descriptions •• Timing Diagrams. • • • 0 0 • • • 0 • • • • • • • • • • 0 xii 0 •• 0 • 0 • '0 • • 0 0 • • 0 ••• • • • 3-11 3-12 3-12 3-12 3-16 3-18 3-19 3-20 3-20 3-27 3-27 3-28 3-28 3-28 3-29 3-33 3-35 3-35 3-35 3-37 3-38 3-41 3-42 3-42 3-44 Table of Contents Memory PCB. • • • • • • • • • • • • System Bus Interface • • • • Row/Column Address Decoder • • ••• Memory Transceiver Control • • • • • • • Memory Arbiter • • • • • • • • • • • RAM Refresh • . • • • • • • • • • . • • • Address Space Allocation • ••• • . Timing Diagrams. • • • • • • • • Communications (SIO) PCB. • ••..•• I/O Microprocessor • • . • • • • • • • . Local Arbiter. • . • • • •••• System Bus Interface • • • • • . Local Bus Controller • • • • • •• • Local Bus Interface. • • • • • • • • • • Local Bus Transceiver Controller Local Memory • • • • • • • • • •• • Local Memory Decoder • • • •• ••• System Memory Page Register • • • • • • • Accessing System Memory. •• •• • • I/O Port Addressing. • • • •• .•• DMA Controller • • • • • • • • • • • • • DMA Synch/Refresh Controller • • • • • • DMA Read/Write Controller. • •• DMA Page Register. . •• • ••••• Serial I/O Ports • • • • • • •••• Network Channel. • • • • • • •• SCC Recovery • • . • • • • • Programming Precautions. • • • • • • Counter/Input/Output • •• .•••• CIa Programming Notes. • • •••• • Interrupt Priorities • • • • • • •• Jumper Selectable Options. • • • • • • • I/O Connectors • • • • • • • • • • • • • Timing Diagrams. • • • • ••• • • • File Processor PCB. • • • . •• • • • • System Interface • • •• • • • • • • System Bus Control Logic •••••• Microprocessor • • •• •• . • • • • Interrupts • • • • • • • • • • • • • • • Memory Organization. • • • • Memory Options • • • • • • • • • • • • • RAM Control Logic. • • • •• •• • • parity Errors. • • . • • • • . • • • •• Common Control and Status. • • • • • • • Interrupt Logic.. • • • • • • • • • Timer. • • • • • • • • • • • • • • • • • Burst Logic. • • • • • • ••• • xiii 3-55 3-55 3-57 3-57 3-58 3-58 3-59 3-59 3-63 3-63 3-63 3-64 3-65 3-65 3-66 3-66 3-68 3-68 3-69 3-79 3-75 3-77 3-77 3-78 3-79 3-82 3-83 3-83 3-85 3-88 3-99 3-92 3-93 3-95 3-195 3-195 3-196 3-196 3-197 3-107 3-109 3-109 3-109 3-109 3-112 3-116 3-117 Table of Contents DMA Controller • • • • • • • • • • • • • Ping-Pong Buffer • • • • • • • • • • • • ping-Pong Buffer Control Logic • • • Controller Interface • • • • • • • • • • Controller PCB Read/Write Control Logic. Printer Controller • • • • • • • • • • • SCSI Controller. • • • • • • • • • • • • File Processor Initial Program Load (IPL) Process. • • • • • • • • •• Timing Diagrams. • • . •••.•• • Controller PCB. • • • • • • • • • • Controller Initialization • • • • • • • • Hard Disk Controller • • • • • • • • • • Floppy Disk Controller • • • • • • • Tape Controller • • • • • • • • • • • . • 4 3-117 3-118 3-129 3-121 3-122 3-122 3-124 3-126 3-126 3-137 3-137 3-137 3-149 3-143 MAINTENANCE INTRODUCTION • . • • • • • • • • • • • . • • • SELECTING 115/238 VAC OPERATION • • . •• PREVENTIVE MAINTENANCE • •• • •••• Cleaning. • . . • • • • • •• • 'Dust Filters. • • • • • • • • ••• Tape Heads • • • • • • • • • • • Floppy Disk Drive. • • • • • • • Exterior • • • • • • • .••••• • Interior • • • • • • ••• • • • • • CORRECTIVE MAINTENANCE • ••• • • • • • • Removal and Replacement • • •• • • • • Removing the Front Panel • • • • • • • • Removing the Side Panels • • • • • • • • Removing the Tape Drive. • • • • • • • • Replacing the Tape Drive • . • • • • • • Removing the Floppy Drive. . • • • • • • Replacing the Floppy Drive • • • • • Removing the Hard Disk Drive • • • • • • Replacing a Hard Disk Drive. • • • • • • Removing the Plug-In Printed Circuit Boards. • • • . . • • • • • • • • Removing the Main Power Supply • • Removing the Backplane PCB • • • • • • • Removing the Low-Pass Filter PCB (Early Version Only) • • • • • • • • • • Removing the LED PCB • • • • • • • • • • Removing the Clock Battery • • • • • • • xiv 4-3 4-3 4-5 4-6 4-6 4-9 4-11 4-12 4-12 4-13 4-13 4-13 4-15 4-16 4-18 4-19 4-21 4-22 4-24 4-26 4-27 4-28 4-38 4-31 4-31 Table of Contents SHIPPING A FIELD REPLACEABLE packaging the System Unit packaging Storage Devices packaging Printed Circuit 5 UNIT. • • • • • • ••••••••• • • • •• • • Boards • • • • • • 4-35 4-35 4-36 4-36 INTRODUCTION • • • • • • • • • • • • • TROUBLESHOOTING AIDS • • • • • • • • • System Overview • • • • • • • • •• • • principles of Operation • • • • • • • • • • Diagnostics • • • • • • • • • • • • •• Diagrams. • • • • • • • • • • • •• • • Field Replaceable Unit Locations.. • • TROUBLESHOOTING CONSIDERATIONS • • • • • • • • Handling Static-Sensitive Devices • • • • • Soldering Techniques and Equipment. • • Removing Integrated Circuits. • • • •• TROUBLESHOOTING PROCEDURES • • • • •• •• Low-level Tests • • • • • • • • • • • • • • power-Up Tests. • • • • • • • • • • • • System power-Up Sequence • • • • • • • • Communications power-Up Tests.. • • CPU Power-Up Tests • • • • • • • • • • • File Processor and Controller Power-Up Tests • • • • • • • • • • • • • • • • • CPU and File Processor Communication • • Interrupt Signals. •• • • • • • • • Communication Protocol • • • •• •• System-Conf idence Tests • • • • • • • • • • Booting the SDX Disk • • • • • • • • • • Field-Service Tests • • • • • • • • • • • • SDX Field Service Menu • • • • • • • • • CPU Test Menu. • • • • • • • • • File Processor and Controller Board Test 5-3 5-3 5-3 5-4 5-4 5-4 5-5 5-5 5-5 5-6 5-7 5-11 5-13 5-15 5-17 5-18 5-19 TROUBLESHOOTING Menu. • • •• 5-37 5-41 5-41 5-41 5-43 5-43 5-47 5-47 5-52 • • • • • • • • • • • 5-56 SIO Test Menu. •• • • • • • • • • • File Processor and Controller PCB Circuit Level Test Menu • • • • • • • • Debugger Tests. • • • • • • • • • • • • • • CPU Debugger Commands. • • • • • • • •• Communications Debugger Commands (Software Mode) • • • • • • • • • • • • Communciations Debugger Commands (Hardware Mode) • • • • • • • • • • • • xv 5-61 5-67 5-89 5-89 5-97 5-101 Table of Contents APPENDICES A JUMPERING INTRODUCTION • • • • • • • • • . • . . . . • . A-3 MEMORY PCB JUMPERING • • • • . . . . . . . A-3 COMMUNICATIONS PCB JUMPERING • . . . • . . . . A-12 B S~RAGE DEVICE SPECIFICATIONS INTRODUCTION • • • • • • • • CARTRIDGE TAPE DRIVE • • • • Electrical Specifications FLOPPY DISK DRIVE. • • • • • Electrical Specifications HARD DISK DRIVE. • • • • • • Electrical Specifications C • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• • • • • • • • • • • B-3 • • B-3 B-3 • • B-4 • • B-4 • • B-5 • • B-6 UTILITY PROGRAMS INTRODUCTION •• • • • • • • • • • • • • • BOOTING '!HE SDX DISK • • • ••• • • • FLOPPY FORMAT. • • • • • • • • • • • • • • • • FLOPPY COPY. • • • • • • • • • • • • • • • WORKING WITH HARD DISK BAD SECTORS • • • • • • Terminology • • • • • • • • • • • • • • • • Determining the Drive Number • • • • • • • • DISPLAY HARD DISK CONFIGURATION TABLE. • • • • SCAN HARD DISK FOR BAD SECTORS • • • • • • • • FLAG HARD DISK BAD SECTORS • • • • • • • • • • Drive Serial Number • • • • • • • • • • • • Entry Mode. • • • • • • • • • • • • • • • • Unflagging a Bad Sector • • • • • • • • • • HARD DISK FORMAT. • • • ••••• I •••• RECONFIGURE HARD DRIVE • • • • • • • • • • • • D C-3 C-3 C-6 C-8 C-l2 C-l2 C-l4 C-l4 C-l6 C-l9 C-29 C-29 C-24 C-24 C-26 LOOPBACK CONNECTORS INTRODUCTION • • • • • • • • • • • • • \. • • • D-3 xvi Table of Contents E ADJOSTIlENT PROCEDURES . . . . . . . E-l . . . . . . . . . . . . . . . . . . . . G-l . . . . . . . . . . . . . . . . . . . . I-I TAPE PHASE LOCK LOOP ADJUSTMENT. GLOSSARY. INDEX • • List of Illustrations Figure Title 1-1 1-2 1-3 Field Replaceable Units • • • • • • • 1-12 Controls, Connectors, and Indicators • 1-14 Recommended Plug-In PCB Locations. • • 1-16 2-1 Maximum Overall Dimensions • • 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-11iJ 3-11 3-12 81iJ286 Memory Map • • • • • •• • • Cache Memory Organization. • • • • • • Cache Memory Search. • •• • • • • CPU PCB Timing Diagrams.. • • • • Memory PCB Timing Diagrams • • • • • • Local Memory Map • • • • • • • • • • • System Memory Page Register. • • • • • Local I/O Map • • • • • • • • • • • • • DMA page Register Block Diagram • • • • Communications PCB Timing Diagrams • • 81iJ86 Memory Address Map. • • • • • • • 81iJ86 System Memory Addressing. • • • • 4-1 Il5/231iJ VAC Selection (Main Power Supply) • • • • • • • • • • • • • • • Il5/231iJ VAC Selection (Hard Disk Drive) • • • • • • • • • • • • • • • • Removing/Replacing the Front Panel Filter) • • • • • • • • • • • • • • • Removing/Replacing the Bottom Filter. Cleaning the Tape Head • • • • • • • • Removing/Replacing the Front Panel • • Removing/Replacing the Side Panels • • 4-2 4-3 4-4 4-5 4-6 4-7 xvii ... • 2-9 3-31iJ 3-38 3-41iJ 3-44 3-61iJ 3-67 3-69 3-71 3-78 3-95 3-l1iJ8 3-l1iJ8 4-4 4-5 4-7 4-9 4-lliJ 4-14 4-15 Table of Contents Figure Title 4-8 Locking/Unlocking the Tape Drive Mounting Screw. • • Removing/Replacing the Tape Drive. Locking/Unlocking the Floppy Drive Mounting Screw. • • Removing/Replacing the Floppy Drive. Removing/Replacing the Hard Disk AC Connector. Unlocking/Locking the Hard Disk Drive Mounting Screws • Removing/Replacing the PI ug-In PCBs. • Removing/Replacing the Main Power Supply. • • • Removing/Replacing the Backplane Removing/Replacing the Clock Battery Cable Interconnections • • 4-9 4-HJ 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 5-1 5-2 5-3 5-4 5-5 · · · · · · · ·· ·· 4-16 4-17 · · · · · · · · ·· 4-19 4-29 · · · · · · · · · · · · 4-23 4-24 · · · · · · · · 4-26 · · · · · · · · · · ·· · ·· 4-28 4-29 4-32 · 4-33 ···· · · Removing ICs (Cut pin Method). 5-8 · · · · Removing IC Pins · · Plated-Through · · · · · · · · · 5-9 Removing Solder from Holes . • · • • • · 5-19 · · · • from · • Lead · • ·Connection Removing Solder Pads. . • · · · • • · · • • · 5-11 · • • • Test System Power-Up Sequence Block Diagram · · · · · • · · · · · · · · 5-16 Memory PCB Jumper-Pin Connectors A-4 Jumpers for One 1M Byte Memory PCB· · · A-5 Jumpers for Two 1M Byte Memory PCBs.· ·• A-5 ,; A-I A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-19 A-II A-12 A-13 ·· Jumpers for One 2M Byte Memory PCB Jumpers for 2M and 1M Byte Memory PCBs • • • • Jumpers for Two 2M Byte Memory PCBs. • Jumpers for Three 2M Byte Memory PCBs. Jumpers for One 4M Byte Memory PCB Jumpers for 4M and 1M Byte Memory PCBs • • Jumpers for 4M and 2M Byte Memory PCBs • • • Jumpers for 4M, 2M, and 1M Byte Memory PCBs Jumpers for Two 4M Byte Memory PCBs. Reference Jumpers for 1M Byte Memory PCBs • • • • A-6 · · · · · · · · · A-6 A-7 · · · · A-7 A-8 ·· · · · · · · · · A-8 · · · · · · · · · A-9 · · · · · · · · · ·· A-9 A-19 · · · · · · · · A-19 xviii Table of Contents Figure Title A-I4 A-17 Reference Jumpers for 2M Byte Memory PCBs • • • • • • • • • Reference Jumpers for 4M Byte Memory PCBs • • • • • • • • • Jumpers for SIO Communications PCBs (Factory Setting) • • • • • • Jumpers for SIO Communications A-I8 Jumpers for SIO Communications A-19 A-20 Jumpers for SIO Communications COMM 2 • • • • • • • • • • • Jumpers for SIO Communications COMM 3 • • • • • • • • • • • C-l Hard-Disk Terminology. • • • • D-l D-2 Parallel Printer Port Loopback Connector • • • • • • • • • • • • • • D-3 Serial Communications (SIO) Loopback Connector • • • • • • • • • • • • • • D-4 E-l E-2 E-3 Channel A and B Waveforms. • • • • • • E-2 Channel B Waveform • • • • • • • • • • E-3 Jumper and Test Point Locations (Controller PCB). • • • • • • • • • • E-4 A-IS A-16 · . . • A-II · . . • A-II · . A-13 COMM" COMM 1 ••••••••••• •••••••• • • • • • A-IS · . • • A-16 · . • • A-17 · . . . A-18 · . . • C-12 List of Tab! es Table Title 2-1 2-2 2-3 Electrical Specifications. • • • • • • 2-3 Environmental Specifications • • • • • 2-8 Physical Specifications • • • • • • • • 2-8 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 Input Status-Port Bit Definitions • • • output-Latch Bit Definitions • • • • • Interrupt Request Levels • • • • • • • Translation-Table Addresses. • • • • • Translation-Table Bit Definitions • • • Tag-Memory Bit Definitions • • • • • • Jumper Descriptions. • • • • • • • • • I/O Port Assignments • • • • • • • • • Communications Controller References • xix 3-33 3-34 3-35 3-36 3-37 3-41 3-43 3-71 3-79 Table of Contents Table 3-lIiJ 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 5-1 5-2 5-3 Title Asynchronous-Channel Handshake Lines • Synchronous-Channel Handshake Lines. • CIa Port Descriptions. • • • • • • • • Interrupt Daisy Chain. • • • • • • • • Jumper Descriptions. • • • • • • • • • Connector/Controller Configuration • • Connector Pin Assignments. • • • • • • Control and Status Port Assignments. . , Control and Status Bit Assignments • • Nonmaskable Interrupts • • • • • • • • Interrupt controller Port Assignments. Maskable Interrupts. • • • • • • • • • DMA Controller Port Assignments. • • • Printer Port Assignments • • • • • • • Printer Status Port Bit Assignments. • SCSI Controller Port Assignments • • • Hard Disk Controller Port Assignments. Hard Disk Controller Bit Assignments • Floppy Disk Controller Port Assignments • • • • • • • • • • • • • Floppy Disk Control-Register Bit Assignments • • • • • • • • • • • • • Tape-Controller Port Assignments • • • Tape-Controller Bit Assignments. • • • 5-10 Low-Level Trouble Analysis • •• • Power Supply DC Voltages • • • • • • • CPU Failure Status at Output Latch Port. • • • • • • • • • • • •• Hard Disk Controller Error Register Bit Descriptions • • • • • • Hard Disk Controller Status Register Bit Descriptions • • • • • • Floppy Disk Controller Status Register 0 Bit Descriptions • • • • • Floppy Disk Controller Status Register 1 Bit Descriptions • • • • • Floppy Disk Controller Status Register 2 Bit Descriptions • • • • • Floppy Disk Controller Status Register 3 Bit Descriptions • • • • • SDX Trouble Analysis • • • • • • • • • A-I SIO PCB Jumper Descriptions. 5-4 5-5 5-6 5-7 5-8 5-9 ... xx 3-81 3-82 3-86 3-90 3-92 3-93 3-94 3-110 3-110 3-113 3-114 3-114 3-118 3-123 3-123 3-126 3-138 3-139 3-141 3-141 3-143 3-144 5-13 5-14 5-82 5-28 5-29 5-32 5-33 5-35 5-36 5-72 • A-12 Table of Contents Table Title B-1 Cartridge Tape Drive Specifications. Floppy Disk Drive Specfications. • • 5BM Byte Hard Disk Drive Specifications. • • • • • • • • • • 8BM Byte Hard Disk Drive Specifications. • • • • • • • 19BM Byte Hard Disk Drive Specifications. • • • • • • • • • • B-2 B-3 B-4 B-5 • B-4 • B-5 • B-6 . . B-5 xxi • B-1B CHAPTER 1 SYSTEM OVERVIEW SYSTEM DESCRIPTION. • • • • • • • • • • • • • Characteristics. • • • • • • • • • Architecture • • • • • • • • • • • • • Configurations • • • • • • • • • • • • • • • • Networking • • • • • • • • • • • • • • • • Communications • • • • • • • • • • • • • • Diagnostics. •• • • • • • • • • • • • • • Power-Up Tests. • • • • • • • • • • • • • • User System-Confidence Tests. • • • • • • • Field-Service Diagnostics • • • • • • • • • Hardware • • • • • • • • • • • • • • • • • • • System Bus. • • • • • • • • • • • • • • • • Central Processing Unit (CPU) PCB • • • • • Memory PCB. • • • • • • • • • • • • • • • • Communications PCB. • • • • • • • • • • File Processor PCB. • • • • • • • • • • Controller PCB. • • • • • • • •• • • • FIELD REPLACEABLE UNITS • • • • • • • • • • • • • CONTROLS, CONNECTORS, AND INDICATORS. • • • • • • Front Panel • • • • • • • • • • • • • • • • • • Rear panel • • • • •• •••••• •• PLUG-IN PRINTED CIRCUIT BOARD LOCATIONS • • • • • SYSTEM SOFTWARE • • • • • • • • • • • • • • • • • Operating System Program • • • • • • • • • Address Translation • • • • • • • • • • • • Disk Performance • • • • • • • • • • • • • • Serial Port Performance • • •• • • • • Compatibility • • • • • • • • • • • • • • • Diagnostics. • • • • • • • • • • • • • • • 1-1 1-3 1-3 1-3 1-4 1-4 1-5 1-5 1-6 1-6 1-6 1-7 1-7 1-8 1-8 1-8 1-9 1-10 1-11 1-12 1-13 1-13 1-15 1-15 1-15 1-17 1-17 1-17 1-17 1-18 System Overview SYSTEM DESCRIPTION The Altos lB86/2B86 Computer System is a floor-standing computer designed for general processing, office automation, and network fileserver applications. The system contains a CPU, system memory, I/O connections, mass storage, streaming tape backup, and a floppy disk drive. Characteristics The following are some of the main characteristics of the IB86/2B86: • exceptional modularity for easy system expansion • 8 MHz Intel 8B286 main microprocessor • optional high-speed Intel 8B287 floating-point processor • up to 451M bytes of formatted internal hard disk storage • up to 8M bytes of RAM system memory • 6BM byte streaming cartridge tape drive • storage expansion beyond 45lM bytes via a small computer system interface (SCSI) channel. (-BB2 version of file processor subsystem only.) • high-speed 32-bit expanded Multibus[tm] • remote diagnostics (with optional modem) for rapid fault isolation to field replaceable units Architecture The modular system architecture allows for convenient service. The printed circuit boards (PCBs) are easily removed or replaced without disassembling the system. 1-3 System Overview The cartridge tape, floppy disk, and hard disk drive mass storage subassemblies are easily installed or replaced by removing the front panel and sliding the subassemblies in or out of the chassis. The three available hard disk drive subassemblies plug directly into the backplane. The system can contain up to eight plug-in PCB subsystems (five PCBs are used for a minimum 19-user system) and five magnetic media storage subassemblies. All of the plug-in PCBs slide into the back of the chassis and connect to the system backplane PCB located in the center of the chassis. The mass storage subassemblies slide into the front of the chassis and also connect to the backplane PCB. The backplane PCB serves as the medium for data interchange between the processors, system memory, and mass storage subassembl ies. Configurations The 1986/2986 system can be configured in a variety of ways. The smallest possible configuration (or minimum system) could be made with 1M byte of random access memory (RAM), 19 RS-232 ports, a 59M byte hard disk drive, and a 1.6M byte floppy disk drive. More system memory, hard disk capacity, and RS-232 ports can be added. A larger system configured to support 29 or 39 could contain a 2M byte or 4M byte memory PCB, three 19-port communications PCBs, a 199M byte disk drive, a 1.6M byte floppy disk drive, and byte cartridge streaming tape drive. users two or hard a 69M Networking The 1986/2986 hardware supports local area networking (LAN). The networking hardware runs at two speeds: 759K and 1.4M bits per second. The slower speed allows the 1986/2986 to talk to Altos l86~ 486, 586/586T, and 986/986T networks. The higher speed allows the 1986/2986 to talk to other 1986/2986 systems. A simple low-cost, twisted-pair, RS-422 interface is used at the hardware level. 1-4 System Overview The 108612086 uses the same type of WorkNet software that runs on most Altos systems. The WorkNet software allows transparent remote file access and remote processor execution. Communications The 1086/2086 system supports several serial communications protocols which are down-loaded to the serial communications PCB. These communications protocols are run by the 8086 microprocessor on the communications PCB, which removes this burden from the main cpu. By using multiple communications PCBs, multiple communications protocols can be run at the same time. The software for running the communications protocols is downloaded into the RAM on the communications PCB. The software for 3270, 3780, X.25, and SNA protocols will run on the 1086/2086. The system is capable of supporting asynchronous modems for dial-up data base services or offsite communications and bisynchronous modems for IBM 3780 emulation. WorkNet can also be supported through one port via a software command communicating at 1.4M bits per second or 750K bits per second (used to connect compatibles to Altos processors). The optional communications PCB subsystem, configured with 32K bytes of RAM, supports certified X.25 or IBM/SNA software protocols. Diagnostics The 1086/2086 performs three major categories of diagnostic tests. The first category is the built-in hardware tests contained in the power-up monitor program. (Refer to System Software in this chapter for additional diagnostics information.) The second category of tests is the user systemconfidence tests. The final category is the fieldservice diagnostics (SDX) tests which can be run either from a floppy disk or remotely with the optional communications modem. (Refer to the 1886/2886 Remote Diagnostics manual for remote diagnostics information.) 1-5 System Overview Power-Up Tests The power-up tests are ROM-based and reside on the CPU, communications, and file processor PCBs. These power-up tests are always performed when power is applied to the system to check the minimum hardware configuration on its particular PCB, identify any missing or failed assemblies, and then confirm communication with the system. These tests are always performed on power-up. The CPU power-up tests include programmable read-only memory (PROM), cache memory, translation and tag RAM memory, clock, floating-point numeric processor, interrupt, and system bus checks. The file processor power-up tests include local RAM and PROM, interval timer, system bus, DMA controller, and magnetic media controller checks. The communications PCB power-up tests consist of local RAM and PROM, I/O integrated circuits, DMA controller, interrupt, and system bus checks. User System-Confidence Tests The user system-confidence tests allow a system user to test the functionality of the system. These tests are menu driven. A full set of tests can be run with only one or two keystrokes on the system console. More detailed and flexible tests are also available for the service technician. A full set of system utilities for handling system configuration and mass storage devices is incl uded. Field Service Diagnostics The field-service diagnostics can be run either from the SDX floppy disk supplied with the system or from a remote service depot through the optional communications modem. The principle advantage of the remot'e method of performing diagnostics is that only one PCB (one of the communications PCBs) needs to be working in order to begin testing. In most multi-board systems, the CPU PCB, system memory PCB, controller PCB, and communications PCB must be working before diagnostic testing can start. 1-6 System Overview In the lB86/2B86, the communications (SID) PCB contains a full l6-bit microprocessor that acts as a diagnostic controller on the system bus. Thus, each PCB can be called up and tested separately, or the full system can be enabled and exercised to isolate and identify failures for repair or replacement. Another advantage of the remote diagnostic method is that the tests are run by highly trained technicians at the main Altos facility or at designated service centers. The full expertise of Altos is available on the spot to evaluate a problem without waiting for a service technician to arrive. The remote facility can call up specific PCB monitors or debuggers, or transmit the latest circuit-level diagnostics, with no interaction required from the user. The failed unit can, upon isolation, be easily replaced by the user or by the system administrator. Hardware The system hardware is partitioned so that each major function is performed by a single PCB. The five required PCBs for the minimum lB-user system are the CPU, system memory, communications, file processor, and controller. All of these PCBs, except the controller, connect to the 32-bit system bus. Refer to Chapter 3 for a description of the system hardware operation. System Bus The system bus is asynchronous and has 32 data lines and 24 address lines that can support a maximum data transfer rate of 3BM bytes per second. Up to 16M bytes of RAM can be accessed and data transfers can be 8-, 16-, or 32-bits wide. The system bus supports one of up to eight bus masters. All the processors in the system communicate with each other via system memory and I/O channel attentions and interrupts. 1-7 System Overview Central Processing Unit (CPU) PCB The CPU PCB contains an 8e286 microprocessor (running at 8 MHz,), an interrupt controller, and a calendar clock with battery backup. Also available on the -ee2 version of the CPU PCB is an optional 8e287 floating-point numeric processor. The 8e286 is aided by a 4K byte instruction and data cache memory. When operating out of cache memory, the 8e286 runs with zero wait states. When a memory write on the system bus occurs, the cache control hardware searches the cache. If there is a cache hit, then that location in the cache is marked as invalid. This feature of the cache makes it fully coherent with system memory at all times. The cache hit rate has been measured at 88%, under typical use env ironments. The CPU PCB contains memory mapping hardware that splits up system memory into 4K byte pages to speed up task switching and prevent memory fragmentation problems. Memory PCB The memory PCB comes in three sizes: 1M, 2M, or 4M bytes. The system memory is organized into long words of 32 bits and memory transfers can be made in 8, 16, or 32-bit quantities. The memory PCB uses lSe nanosecond dynamic RAM integrated circuits (ICs) and features a typical access time of 24e nanoseconds with a typical cycle time of 4ee nanoseconds .Mul tiple memory PCBs can be installed in the le86/2e86 system. Communications PCB The communications PCB handles all of the serial communications for the le86/2e86 system and supports asynchronous and synchronous RS-232, and RS-422 network communi ca tions. 1-8 System Overview The communications PCB supports up to 10 asynchronous ports1 three of which can be software-switchable to support two synchronous channels and one networking port. The operating software for the communications processor is down-loaded at boot time so that the communications PCB becomes fully programmable. The networking port is fully compatible with Altos B00K bit WorkNet, 186, 486, 586, and 986 systems and can run at a faster 1.4M bit per second rate when communicating with other 1086/2086 and Altos 3068 systems. Several synchronous communications packages, which include the X.25 and SNA protocols, are available to run on the communications PCB. An Intel 8086 microprocessor (running at 8 MHz,) manages all the data flow, I/O interrupts, DMA channels, and communications with the CPU. File Processor PCB The file processor PCB manages the data flow to/from the Centronics parallel port and all of the mass storage devices in the system. The mass storage devices include the floppy disk, hard disk, and cartridge streaming tape drives, and all the peripherals connected to the SCS I channel. NOTE The -001 version of the file processor PCB does not support small computer system interface (SCSI) operation. The -002 version of the file processor PCB includes SCSI. Some of the main characteristics of the file processor are: • supports up to three internal hard disk drives and additional drives connected via the SCSI channel • supports a DMA-driven Centronics parallel port for high-speed line and laser printers 1-9 System Overview • concurrent transfer of the printer, tape, floppy disk, and hard disk data (only one hard disk at a time) • performs overlapped seeks when more than one disk drive is connected • performs reads and writes to consecutive sectors on the hard disk, even though data may be scattered in system memory. Controller PCB The controller PCB contains the device controllers for the floppy disk, hard disk, and streaming tape drives. All of these device controllers take commands from the file processor. The hard disk controller accommodates disk drives with ST506 or ST412HP interfaces and can handle data transfer rates up to 5M bits per second. The hard disk controller can support up to three internal hard disk drives. The tape controller can interface with Altos cartridge streaming tape drives with the QIC-36 interface and uses the QIC-24 format for putting data on the tape. The tape streams at 90 inches per second and has a maximum capacity of 60M bytes. The floppy disk controller interfaces with a dual-speed floppy disk drive which uses either normal or high capacity disks. The normal disks are fully compatible with the floppy disks used on the Altos 186, 486, and 586 systems. 1-10 System Overview FIELD REPLACEABLE UNITS The 1086/2086 Computer System contains the following field replaceable units (FRUS) (see Figure 1-1): • • • • • • • • • • • • main power supply streaming tape drive hard disk drive floppy disk drive central processing unit (CPU) PCB memory PCB communi ca ti ons PCB file processor PCB controller PCB backplane PCB light-emitting diode (LED) PCB low-pass filter PCB (early versions only) 1-11 System Overview PLUG·IN PCBs (SEE PLUG·IN PRINTED CIRCUIT BOARD LOCATIONS) MAIN POWER _ _ __ SUPPLY BACKPLANE PCB _ _...... CARTRIDGE TAPE DRIVE FLOPPY DISK_-I\Il~ DRIVE LOW·PASS FILTER PCB (EARLY VERSION ONLY) LED PCB HARD DISK - - - + t !.." " DRIVE 01311 Figure 1-1. Field Replaceable Onits CONTROLS, CONNECTORS, AND INDICATORS Refer to Figure 1-2 for the locations of the front and rear-panel controls, connectors, and indicators. The following is a description of the controls, connectors, and indicators indexed to the numbers in Figure 1-2: 1-12 System Overview Front Panel 1 RESET/ROB Switch. Key-operated switch that resets (boots) the system when turned to RESET and back to RUN. Allows normal system operation when set to RUN. If the key is turned to RESET and removed, the system will remain in the reset condition and will not operate. 2 POWER Indicator. Green light-emitting diode (LED) indicator that lights when power is applied to the system (rear panel POWER switch is in the on position) • 3 DD 1, DD 2, and BD 3. Yellow LED indicators that light to indicate which hard disk drive is selected. Rear Panel 4 POWER Switch. Rocker switch that applies power to the system when placed in the on position (green LED indicator 2 on the front panel is lit). The system will boot when the POWER switch is placed in the off, then on, position while the RESET/RUN switch 1 on the front panel is in the RUN position. S Fuse Bolder. Holder that contains the main linevoltage fuse (Refer to Chapter 2 for the proper fuse rating). 6 AC IBPOT Connector. Three pin AC connector for attaching an AC power cord to the system. 7 DPS Jack. Jack for connecting a power fail status signal from an external uninterruptable power source device to the system. 8 PRINTER Connector. Connector for attaching a printer with a Centronics parallel interface to the system. 1-13 System Overview 9 Serial I/O Ports. Ports 0 through 9 on the communications PCB provide 10 asynchronous RS-232 ports for connecting terminals or printers to the system. Refer to the communications PCB description in Chapter 3 for details on the serial I/O port capabilities. rr lieJI IEiI 1 I~ IIIl!1Io J III 111f II ~991 e e, e, e II 2 3 ~ T ~ 02002 Figure 1-2. Controls, Connectors, and Indicators 1-14 System Overview PLUG-IN PRINTED CIRCUIT BOARD LOCATIONS The CPU, file processor, and controller PCBs are dedicated to slots A, G, and B respectively in the back of the 1986/2986. The remaining slots, B through F, are electrically identical which allows memory and communications PCBs to be installed in any order in these five slots. However, software requires that the memory and communications PCBs be jumpered according to their logical assignment in the system (see jumper description information in Chapter 3 and Appendix A). SYSTEM SOFTWARE The system software supplied with the 1986/2986 consists of the operating system, utility, and diagnostic programs. Operating System Program The 1986/2986 Computer System is specifically designed for the XENIX 3.2 operating system. The XENIX operating system supports the following development tools and programming ,functions: • large Model C compiler with 1M byte of address space per program • shared data that allows programs to share a common memory space • semaphores that provide a synchronization tool for cooperating programs • source code control system for easy program maintenance • full suite of development tools, such as, vi, csh, nroff, lint, and adb 1-15 System Overview [ () 3: () () 'V m c: s::: 0s::: 03: 0 s::: 3: ::D c: c: () () 'TI 0 0 r= gl s::: 3: m ~I 3: 3: 'V ::D. c: c: -< Z Z Z Z 0::D 0r 0 0 0 0 () m rm :I> :I> :I> :I> (I) -I ::D -I -I -I (5 (5 (5 (5 0(/) Z Z Z (I) (I) Co) 110) (I) ... "- "- "- Z ::D (I) 0 3: 3: 3: m mm 3: 3: 3: 0 0 0 ::D ::D ::D -< -< -< HIGHEST CAPACITY, _ _...J LOWEST ADDRESSED MEMORY PCB PRIMARY COMMUNICATIONS PCB MEMORY OR 2ND COMMUNICATIONS PCB NEXT HIGHEST CAPACITY MEMORY OR 4TH COMMUNICATIONS PCB L...-_ _ _ MEMORY OR 3RD COMMUNICATIONS PCB 02003 Figure 1-3. Recommended Plug-In PCB Locations 1-16 System Overview Address Translation XENIX uses the sophisticated address translation logic on the 1886/2886 to improve performance as follows: • Scatter Loading. Loads user programs into noncontiguous 4K byte pages of system memory for more efficient use with less swapping • Faster context Switching. When context switching, the per process data area is mapped by loading a table entry instead of copying the data around memory as in standard XENIX • Dynamic Stack Growth. locate stack space Programs do not preal- Disk Performance The 1886/2886 hard and floppy disks are controlled by the file processor PCB which removes much of the processing work from XENIX. The Altos XENIX also supports a lK byte block file system that maximizes disk throughput. Serial Port Performance The 1886/2886 serial ports are controlled by the communications PCB which offloads interrupts and processing from XENIX. Each communications PCB is down-loaded with a code that handles the asynchronous ports, WorkNet, and any other communication protocols (SNA, X.25, 3788, and 3278). Compatibility The! XENIX operating system on the 1886/2886 can read and write floppy disks and execute programs that run on the most Altos systems. Tapes created on the Altos 986T can also be read on the 1886/2886. 1-17 System Overview Diagnostics The System Diagnostic Executive (SDX) Program is on a floppy disk included with the 1986/2986 system. The SDX program performs a series of user system-conf idence tests. Refer to Chapter 5 for information on the SDX user system-confidence tests. Field-service diagnostics are also available on the SDX floppy disk. Additional information on the SDX fieldservice diagnostics is provided in Chapter 5. (Refer to the 1886/2886 Remote Diagnostics manual for detailed remote diagnostics procedures.) 1-18 CHAPTER 2 SPECIFICATIONS INTRODUCTION. • • • • • • • • ELECTRICAL SPECIFICATIONS • • ENVIRONMENTAL SPECIFICATIONS. PHYSICAL SPECIFICATIONS • • • 2-1 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 2-3 2-3 2-8 2-8 Specifications INTRODUCTION The electrical specifications listed in Table 2-1 apply when the 1086/2086 Computer System has been operating for at least 15 minutes at an ambient temperature between +40 and +95 degrees Fahrenheit (+5 and +35 degrees Celsius). The environmental and physical specifications are listed in Tables 2-2 and 2-3. ELECTRICAL SPECIFICATIONS Table 2-1 lists the electrical specifications for the Altos 1086/2086 Computer System. ~able 2-1. Electrical Specifications Olaracteristic Performance Requirement Subsystem Central Processing Unit (CPU) Microprocessor Floating-Point Microprocessor (Optional) Clock Frequency System Data Size System Address Size CPU Data Size CPU Address Size Data and Instruction Cache Data Block Size Data and Instruction Cache Memory Size CPU to Memory Transfer Rate 2-3 80286 80287 8 MHz, 32 24 16 24 bits bits Bits Bits 32 Bits '\ 4K bytes 10M bytes/second Specifications Table 2-1. Electrical Specifications (Cont.) Performance Requirement Characteristic Subsystem (Cont.) System Memory Addressable Space Standard 1M, 2M, or 4M bytes/board ! rtJ 86. 1.ul6. 1M byte 2M bytes 8M bytes, maximum* Capable of 1, 2, or 4 byte (32 bit) parallel transfers Optional Transfer Word Length Access Time From Memory Read/Write Command Typical Maximum nanoseconds nanoseconds (with ref resh) 39rtJ nanoseconds 24rtJ 55rtJ Typical Cycle Time S10 Communications Microprocessor Clock Frequency Total I/O Ports Configurable Synchronous Ports Configurable Network Ports RAM Standard Optional WorkNet Data Transfer Maximum Rate/Distance 8rtJ86 8 MHz lrtJ 2 1 l28K bytes 5l2K bytes 75rtJK bits/second: 25rtJrtJ feet/trunk segment 1.4M bits/second: l5rtJrtJ feet/trunk segment. Extendable to 45rtJrtJ feet with repeaters * Hardware can support up to 16M bytes of system memory. Currently, Altos supports up to 8M bytes of system memory. 2-4 Specifications ~able 2-1. Blectrical Specifications (Cont.) Characteristic Performance Requirement Subsystem (Cont.) File Processor Microprocessor Clock Frequency Total External Ports Parallel Printer Port SCSI Port (-002 Only) Total Internal Ports Tape Floppy Disk Hard Disk Maximum Transfer Rates Tape Floppy Disk Hard Disk SCSI Printer 8086 8 MHz, 2 1 1 5 1 1 3 90K bytes/second 63K bytes/second SM bits/second 1.SM bytes/second 50K bytes/second Storage Devices (See Appendix B for additional drive specifications) Cartridge Tape Drive Number of Drives Number of Tracks Number of Channels Capacity Backup Time Media Recording Mode Data Transfer Rate (Tape Speed) Format Interface 2-5 1 9 2 60M bytes/cartridge 15 minutes (60M byte tape) 1/4 inch Scotch[tm] DC-600A cartridge NRZI (nonreturn-to-zero invert) 90 inches/second QIC-24 QIC-36 Specifications ~able 2-1. Electrical Specifications (Cont.) I Characteristic Performance Requirement Storage Devices (Cont.) Floppy Disk Drive Number of Drives Form Factor Size Formatted Size High Density Low Density Unformatted Size High Densi ty Low Density Data Transfer Rate 1 dual-speed, double-sided, double-density drive 5-1/4 inches 1.2M bytes 729K bytes 1.6M bytes 1M byte 259K or 599K bits/second Hard Disk Drive Number of Drives Form Factor Size Formatted Capacity Standard Optional Unformatted Capacity Minimum Maximum Interface Data Transfer Rate Average Seek Time (Incl udes Settl ing Time) 59M Byte Drive 89M Byte Drive 199M Byte Drive 2-6 1 to 3 5-1/4 inches ~ 1.ta2. 63M bytes 49M bytes 159M bytes 63M bytes li.aQ. ll!l6. 89M bytes 59M bytes 199M bytes 89M bytes ST-596 5M bits/second 28 milliseconds 28 milliseconds 39 milliseconds Specifications 7able 2-1. Electrical Specifications (Cont.) I Performance Requirement Characteristic Main Power Supply DC Output voltages Accuracy Current (Continuous) Maximum Minimum Peak (399 ms, Pulsed Load) Regulation (Line/ Load/Temp. ) Ripple/Noise (P-P) Overvoltage AC Line Voltage Range 115 VAC (Nominal) 239 VAC (Nominal) Line Frequency Range Power Consumption Maximum Continuous Maximum BTU Output Maximum Current (RMS) _______±12______-=12 ±19% Adj. ±5%. ~ 49 A 15 A 4 A 9.1 A 9.5 A 9.95 A N/A 6 A N/A ±3% 59 mV ±5%. 199 mV ±19% 159 mV Shutdown Shutdown & cycle & cycle N/A Power 99-125 VAC 195-259 VAC 47-63 Hz 768 W 559 W 1,876 6.4 A at 69 Hz, nominal 115 VAC line 3.6 A at 69 Hz, nominal 239 VAC line Fuse Type 19 A, normal-blowing type 115 VAC (Nominal) 239 VAC (Nominal) 5 A, normal-blowing type Logic signal input from uninterruptable power source via UPS phone jack on rear panel. UPS monitor must be nonconducting when AC power is present and conducting when UPS is on 9.5 V maximum 1.6 rnA DC Power Fail Status Vbltage (Vce) Current (Ic) 2-7 Specifications ENVIRONMENTAL SPECIFICATIONS Table 2-2 lists the environmental specifications for the Altos 1986/2986 Computer System. Table 2-2. Characteristic Temperature Operating Storage Gradient Maximum wet Bulb Relative Humidity Environmental Specifications Performance Requirement +49 to +95 degrees Fahrenheit (+5 to +35 degrees Celsius) -4 to +149 degrees Fahrenheit (-29 to +69 degrees Celsius) Not to exceed 19 degrees Fahrenheit/hour (5 degrees Cel si us/ho ur ) +78 degrees Fahrenheit (+26 degrees Celsius) 29 to 89% non-condensing PHYSICAL SPECIFICATIONS Table 2-3 lists the physical specifications for the Altos 1986/2986 Computer System. Table 2-3. Characteristic Weight Net (Operating) Shipping Dimensions Physical Specifications Description Approximately 68 to 86 lbs (31 to 38.5 kg) 95 lbs (43 kg) maximum (includes peripherals and container) See Figure 2-1 2-8 Specifications • • • • !.- B.SIN. ~ .... ... - - - - - - 22.6 IN. - - - - -..... ~I (57.4 CM.) 121.6 CM.) 02004 Figure 2-1. IlaximUDl OVerall Dimensions 2-9 CHAPTER 3 PRINCIPLES OF OPERATION INTRODUCTION. • • • • • • • • • • BLOCK DIAGRAM DESCRIPTION • • • • System Bus • • • • • • • • • • Central Processing Unit (CPU). System Memory. • • • • • • • • Communications • • • • • • • • File Processor • • • • • • • • Controller • • • • • • • • • • DETAILED CIRCUIT OPERATION. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 3-5 3-5 3-5 3-6 3-7 3-7 3-8 3-8 3-9 NOTE For convenience, each of the following PCB subsystem descriptions have a red locator tab on the right edge of the first page. System Bus Interface • • • • • • • • • • • • • Bus Masters • • • • • • • • • • • • Bus Slaves. • • • • • • • . • • • • • • • • Bus Signals • • • • • • • • • • •••• Data Transfer Operations. •• • • • • • Interrupt Operation • • • • • • • • • • • • Bus Exchange. • • • • • • • • • • • • • Lock Operation. • • • • • • • • • • • • • • Timing. • • • • • • • • • • • • • • • • • • Central Processing Unit (CPU) PCB • • • • • • • CPU Initial ization. • • • • • • • • •• Microprocessor • • • • • • • • • • • • • • • Microprocessor Address Decoder Logic. • 89286 Memory Map. • • • • • • • •••• Local Bus Control Logic • • • • •• Local Bus • • • • • • • • • • • • • • • Calendar Clock. • • • • • • • • •••• Interrupt Controller. • • • • • • • • • • • System Memory Accessing and Address Translation. • • • • • • • • • • • Tag and Translation RAM Control Logic • • • Cache Memory Organization • • • • • • • • • 3-1 3-11 3-12 3-12 3-12 3-1-6 3-18 3-19 3-29 3-29 3-27 3-27 3-28 3-28 3-28 3-29 3-33 3-35 3-35 3-35 3-37 3-38 Principles of Operation System Bus Arbiter and priority Encoding Logic. • • • • • • • • • • • • • • • • • • Microprocessor Ready Generator. • • • • • • Jumper Descriptions • • • • • • • • • • • • Timing Diagrams • • • • • • • • • • • • • • Memory PCB • • • • • • • • • • • • • • • • • • System Bus Interface. • • • • • • • • • • • Row/Column Address Decoder • • • • • • • • • Memory Transceiver Control. • • • • • • " Memory Arbiter. • • • • • • • • • • • • RAM Refresh • • • • • • • • • • • • Address Space Allocation. • •• •••• Timing Diagrams • • • • • • • • • • • • Communications (SIO) PCB • • • • • • • • • • • I/O Microprocessor. • • • • • • • • • • Local Arbiter • • • • • • • • • • • • • • • System Bus Interface. • • • • • • • • • • • Local Bus Controller. • • • • • • • • • •• Local Bus Interface • • • • • • • • • • • • Local Bus Transceiver Controller • • • • • • Local Memory. • • • • • • • • • • • • • • • Local Memory Decode r. • • • • • • • • • • • System Memory Page Register •• • • • • Accessing System Memory • • • • • • • • • • I/O Port Addressing • • • • • • •• • • DMA Controller • • • • • • • • • • • • • • • DMA Synch/Refresh Controller • • • • • • • • DMA Read/Write Controller • • • • • • • • • DMA Page Register. • ••••••••• Serial I/O Ports • • • • • • • • • Network Channel • • • • • • • • • • • • • • SCC Recovery • • • • • • • • • • • • • • • • Programming Precautions • • • • • • • • • • Counter/Input/Output. • • • • • • • CIO Programming Notes • • • •• •••• Interrupt Priorities • • • • • • • Jumper Selectable Options • • • •••• I/O Connectors. • • • • • • • • • • • • • • Timing Diagrams • • • • • • • • • • • • • • File Processor PCB • • • • • • • • • • • • System Interface. • • • • • • • • • • • System Bus Control Logic. • •• •••• Microprocessor. •• • • •• • • • • Interrupts. • • • •• •• • • • Memory Organization • • • • • • • • • • • • Memory Options. •• •••• • • • • • • RAM Control Logic • • • • • • • • • • • • • 3-2 3-41 3-42 3-42 3-44 3-55 3-55 3-57 3-57 3-58 3-58 3-59 3-59 3-63 3-63 3-63 3-64 3-65 3-65 3-66 3-66 3-68 3-68 3-69 3-71ii 3-75 3-77 3-77 3-78 3-79 3-82 3-83 3-83 3-85 3-88 3-91ii 3-92 3-93 3-95 3-11ii5 3-11ii5 3-11ii6 3-11ii6 3-11ii7 3-11ii7 3-11ii9 3-11ii9 Principles of Operation Parity Errors • • • • • • • • • • • • • • • Common Control and Status • • • • • Interrupt Logic • • • • • • • • • • •• Timer • • • • • • • • • • • • • • • • • • • Burst Logic • • • • • • • • • • • • • • • • DMA Controller. • • • • • • • • • • • • ping-Pong Buffer • • • • • • • • • • • • • • ping-Pong Buffer Control Logic. • • • • • • Controller Interface. • • • • • • • • • • • Controller PCB Read/Write Control Logic • • Printer Controller. • • • • • • • • • • • • SCSI Controller • • • • • • • • • • • • • • File Processor Initial Program Load (IPL) Process. • • • • • • • • • • • • • • Timing Diagrams • • • •• • • • • • • • Controller PCB • • • • • • • • • • • • • • • • Controller Initialization • • ••••• Hard Disk Controller. • • • • • • • • • • • Floppy Disk Controller. • • • • • • • • Tape Controller • • • • • • • • • • • • • • 3-3 3-1e9 3-1e9 3-112 3-116 3-117 3-117 3-118 3-12e 3-121 3-122 3-122 3-124 3-126 3-126 3-137 3-137 3-137 3-14e 3-143 Principles of Operation INTRODUCTION This chapter describes the operation of the Altos 1986/2986 Computer System and begins with a general description of the system operation and continues with a detailed description of the system bus interface and the plug-in printed circuit board (PCB) subsystems. Where applicable, the manufacturer's publications are referenced for additional information concerning the integrated circuits used on the subsystems. The 1986/2986 uses the following major subsystems. Each of these subsystems is contained on a single PCB except the system bus. • • • • • • system bus central processing unit (CPU) system memory communications (SIO) file processor controller BLOCK DIAGRAM DESCRIPTION The following block diagram description discusses the overall operation of the 1986/2986 system. Refer to the block and schematic diagrams in the Schematic Diagrams supplement to this manual. System Bus The system bus is a 32-bit data, 24-bit address bus which is an extension of the IEEE 796 system bus (Mu1tibus). The system bus has separate memory and I/O address spaces and can handle asynchronous signal transfers between multiple masters or master and slave. 3-5 Principles of Operation A bus master can perform either single or unlimited system bus transfers. A bus slave decodes addresses and acts upon commands from bus masters. The memory PCB is the only slave. Eight bus masters (subsystem PCBs) are supported by prioritized parallel bus arbitration. A bus clock provides bus arbitration and general-purpose timing. Different master-slave subsystems can operate at different clock rates. The CPU, file processor, and communications PCBs are bus masters which can acquire the system bus through bus exchange logic and generate command, address, and data signals (during writes). The bus signals are divided into the following signal lines: • control lines • address lines • data lines • interrupt lines • bus exchange lines Central Processing Unit (CPU) The CPU PCB executes all the system and applications programs. The CPU PCB contains an 80286 16-bit microprocessor, programmable read-only memory (PROM), a cache memory, and a system bus interface. Also included is a calendar clock with battery backup that keeps time and generates system time-slice interrupts. The 80286 microprocessor includes memory management and supports an optional 80287 floating-point microprocessor. The 80286 microprocessor can operate at 8 MHZ! and executes code out of either PROM, cache memory, 3-6 Principles of Operation or system memory. The microprocessor mainly operates out of the cache memory which eliminates most wait states. The local bus on the CPU PCB transfers address, data, status, and control signals to/from the PROM, calendar clock, interrupt controller, input status port, and control-bit output port. System Memory The memory PCB contains either 1M, 2M, or 4M bytes of memory depending on whether 64K byte or 256K byte RAMS are used. Memory is organized into 32-bit long words or 64-bit double long words, depending upon which version of the memory PCB is used. (There are two versions of the memory PCB as described in the Memory PCB section of this chapter.) Data transfer is in 8-, 16-, or 32-bit quantities. Communications The communications (SIO) PCB is an intelligent input/output (I/O) processor that relieves the CPU of all communications functions. The communications PCB contains an 8086 microprocessor, a system bus interface, a four-channel DMA controller, a local bus controller, 32K to 5l2K bytes of dynamic RAM, 16 to 256K bytes of PROM, a general-purpose counter/timer, and up to 10 serial ports. Seven of the serial ports are dedicated to RS-232 asynchronous communications, one is independently software selectable between asynchronous RS-232 and synchronous RS-422 networks, and the remaining two can support either' asynchronous or synchronous RS-232 communi ca ti ons. Functionally, the communications PCB is a complete computer with the necessary initial program load (IPL)/diagnostic firmware, RAM, and serial I/O ports. Since the' communications PCB is closest to the terminal(s), its on-board firmware has several diagnostic functions that provide power-up confidence 3-7 Principles of Operation tests of all local functions and low-level tests on other parts of the system (on the system bus), including system memory. File Processor The file processor PCB is an intelligent controller that manages data flow to/from a floppy disk drive, a cartridge tape drive, up to three hard disk drives, the centronics parallel printer interface, and additional disk or tape drives through the Small Computer System Interface (SCSI) channel. The file processor PCB contains an 8986 microprocessor, a four-channel DMA controller, a system bus interface, a local bus controller, 32K to 512K bytes of dynamic RAM, 16 bytes to 256K bytes of PROM, a counter/timer, a disk and printer interface, and a SCSI controller. Controller The controller PCB contains three independent controllers for hard disk, floppy disk, and cartridge tape drives. All controllers receive commands from the file processor PCB. The hard disk controller can support three internal disk drives with either ST596 or ST412HP interfaces and can accommodate serial data rates to 5M bits per second. The hard disk controller is capable of seek-overlap operation when multiple devices are used. The floppy disk controller supports one internal, double-density, double-sided, 96 track per inch (TPI), floppy disk drive. The tape drive controller supports Altos cartridge tape drives with QIC-36 interfaces, and uses the QIC-24 format to input data on the tape. 3-8 Principles of Operatfon DETAILED CIRCUIT OPERATION The remainder of this chapter provides a more detailed description of the system bus and plug-in PCB subsystem operation. To help locate the integrated circuits in the schematic diagrams and on the PCB, the location designation for certain integrated circuits is included in parenthesis after the first mention. Refer to Locating a PCB Part in the front of the Scbematic Diagrams supplement in the back of this manual for instructions on how to use the part location designations. NOTE Use the red index tabs on the outside edge of the page to quickly locate the desired subsystem description. 3-9 Principles of Operation (BLANK) 3-10 Principles of Operation System Bus Interface The 1086/2086 system bus is an extension of the IEEE 796 system bus (Mu1tibus). The following are the major differences between the 1086/2086 system bus and the IEEE 796 system bus: • data bus expanded to 32 bits • address bus is 24 bits • parallel bus arbitration • additional control signals The system bus has separate address spaces for memory and I/O. For memory operations, up to 16M bytes can be directly addressed. For I/O operations, a minimum of 64K 8-bit I/O ports or 32K 16-bit I/O ports can be addressed. The bus can handle asynchronous signal transfers between multiple masters or master and slave. Eight bus masters (PCBs) are supported by prioritized parallel bus arbitration. A 9.83 MHz bus clock is provided for bus arbitration and general-purpose use. Due to the asynchronous bus structure, different master-slave subsystems can operate at different clock rates. The maximum bus data transfer rate is 30M bytes per second. There are four subsystem PCBs that interface through the system bus: • central processing unit (CPU) PCB • memo ry PCB • file processor PCB • communications (SID) PCB The floppy disk, hard disk, and tape controllers on the controller PCB are connected to the file processor PCB by a dedicated interconnect bus and not to the system bus. 3-11 Principles of Operation Bus Masters The CPU, file processor, and communications PCBs are bus masters. These three subsystems can acquire the system bus through bus exchange logic and generate command, address, and data signals (during writes). A bus master can operate in single bus transfer per bus unlimited bus transfers per BUSY* signal asserted. See maximum time the bus can be two modes: mode 1 for connect and mode 2 for bus connect by keeping the Bus Lock Timing for the held. Bus Slaves The memory PCB is a bus slave. This subsystem decodes addresses and acts upon commands from bus master subsystems. Bus Signals The bus signals are divided into five groups based upon the function performed. The five groups are: • control lines • address lines • data lines • interrupt lines • bus exchange lines COntrol Lines. control lines: BCLK* The following signals are classified as Bus Clock. A 9.83 MHz 59/59 duty cycle clock used to synchronize the bus contention logic. Only one master can generate this clock. The CPU PCB contains the bus clock generation circuitry. 3-12 Principles of Operation MWT* Memory Write. Asserted by the bus master. Indicates a valid memory address is on the bus. The data can have -3B nanoseconds setup time to the command. See Timing. MRD* Memory Read. Asserted by the bus master. Indicates a valid memory address is on the bus. IOWT* I/O write. Asserted by the bus master. Indicates a valid I/O adtlress and data is on the bus. IORD* I/O Read. Asserted by the bus master. Indicates a valid I/O address is on the bus. XACK* Transfer Acknowledge. Asserted by the addressed slave to acknowledge that data has been placed or accepted on the data lines. AACK* Advance Transfer Acknowledge. Asserted by the addressed slave before the transfer is completed. AACK* helps eliminate wait states due to control synchronization. See Timing. ERR* Error. On memory read operations, ERR* is asserted if a parity error is detected by the memory PCB. ERR* is asserted by the 8B286 microprocessor on the CPU PCB if a bus timeout occurs. MRST* Manual Reset. Input from front panel reset switch. The 8B286 microprocessor on the CPU PCB generates a system reset on the REST* signal line when MRST* is asserted. REST* System Reset. Asserted during power-up and in response to a manual reset. Asserted for at least 5 milliseconds after power supplies are within tolerance. Only the 8B286 microprocessor on the CPU PCB may drive this line. 3-13 Principles of Operation PF* Power Fail. Asserted by the power supply when AC line falls below 99 VAC for l15V systems and 189 VAC for 229V systems. This signal is asserted at least 5 milliseconds before the +SV supply falls out of tolerance. UPSS* Uninterruptible Power Supply Status. Asserted by an optional UPS when loss of input power is detected. This signal is asserted a minimum of 29 minutes before the system input power is out of tolerance. LOCK* Lock. Asserted by the master in control of the bus during read-modify-write operations. The current master keeps the bus by holding BUSY* asserted. Only the bus owner can access a multiported memory when LOCK* is asserted. Lock can be asserted for a maximum of 8 microseconds. Address Lines. address lines: The following signals are classified as A99*-A23* Address bits 99-23. A99* is the l~ast significant bit (LSB) and A23* is the most significant bit (MSB). Address lines are driven by bus masters. The 24 address bits can directly address 16M bytes. HBEN* High Byte Enable. Used with A99*, A9l*, and HWEN* for data transfer width and byte steering. HWEN* High Word Enable. Used with A99*, A9l*, and HBEN* for data transfer width and byte steering. See Data Transfer width for decoding A99*, A9l*, HWEN*, and HBEN*. Data Lines. data lines: The following signals are classified as 3-14 Principles of Operation 099*-031* Data bits 99 through 31. 099* is the LSB and 031* is the MSB. Eight, sixteen, and thirty-two bit transfers are allowed. The bus master drives data lines on write operations while the addressed slave drives the data lines on read operations. Interrupt Lines. The following signals are classified as interrupt lines: INT9*INT6* Interrupt Requests 9-6. Interrupts are divided into seven prioritized classes with INT9* having the highest priority. Interrupts are requested by asserting one of the seven interrupt request lines. Bus Exchange Lines. The following signals are classified as bus exchange lines: BRQ9*BRQ7* Bus Requests 9-7. A master wanting control of the bus asserts a bus request. A parallel priority resolution circuit on the CPU PCB is used to resolve the highest priority bus request. BRQ9* has the highest priority. BPN9*BPN7* Bus priority In 9-7. A master receives a BPNx when it is the highest priority master requesting the bus. A master looks for the same level bus grant as bus request (a master requesting on BRQ3* looks for the grant on BPN3*) • CBRQ* Common Bus Request. Any master wanting the bus but does not own it, asserts CBRQ*. If CBRQ is clear, the current bus owner can keep the bus until it is set. BUSY* Busy*. Asserted by the master in control of the bus to indicate the bus is in use. All other masters monitor BUSY* to determine the state of the bus. 3-15 Principles of Operation Data Transfer Operations There are four types of data transfer operations: • memory read • memory write • I/O read • I/O write write Operations. The bus master starts the operation by placing the memory or I/O address on the address lines and the data on the data lines. When the address and data are valid , the bus master asserts a MWT* (memory write) or IOWT* (I/O write) command which activates the appropriate bus slave. The addressed slave accepts the data from the data lines and asserts XACK* (transfer acknowledge) and AACK* (advance transfer acknowledge). The bus master then removes the command and clears the address and data lines to complete the data transfer. The following is the basic write timing: address V valid address V valid data V /\ /\ data V /\ /\ MWT* or IOWT* \ AACK* / / \ XACK* \ Slaves must assert both AACK* and XACK*. 3-16 / Principles of Operation Read Operations. The bus master starts the operation by placing the memory or I/O address on the address lines. When the address is valid, the bus master asserts a MRD* (memory read) or IORD* (I/O read) command which activates the appropriate bus slave. The addressed slave places the data on the data lines then asserts XACK* and AACK*. The bus master completes its cycle by reading the data from the data lines, removes the command, and clears the address lines. The following is the basic read timing: address V valid address V-_~/\~----------------------------------~/'--- MRD* or IORD* data AACK* \~----------------~I V valid data V ----------------~/\~----------------~/\~-----\~----------------~I XACK* \~ __________...JI Slaves must assert both AACK* and XACK*. Bus Timeout. The 89286 microprocessor on the CPU PCB will monitor data transfer operations and generate a bus timeout and assert ERR*, AAtK* and XACK* if any command· (MRD*, MWT*, IORD*, or IOWT*) is active for more than 4 microseconds. . Data Transfer Width. There are two 8-bit, one 16- bit, and one 32-bit data transfer widths. HWEN*, HBEN*, A91*and A99* decode which byte(s) the data is transferred on: 3-17 Principles of Operation 0 0 X 0 8 1 0 1 X 1 8 2 0 1 X 0 16 2,1 1 1 0 0 32 4,3,2,1 = true or active state or inactive state X = either state 1 o = false Data Formats. The following are the data formats: MSB EVEN ••••••••••••••••••••••••••••••••••••••••••••••••••••• BYTE MSB ono BYTE WORD •••.•.....•...••••..•......•••..•.• 115 17 LSB byt e l •• 0 LSB byte 2 8 1 •••••••••••••••• MSB LSB ••••••••••••••••••••••••••••••••••• 115 byte 2 •• 817 •• byte 1 •• 0 MSB LONG LSB 31 •• byte 4 •• 24123 •• byte 3 •• 16115 •• byte 2 •• 817 •• byte 1 •• 0 WORD Interrupt Operation The system bus uses nonbus vectored interrupts and is not used because no interrupt vector address is placed on it. An interrupting PCB asserts one of the interrupt request lines (INT0*-INT6*) to generate an interrupt request. The interrupt requests are prioritized with INT0* the highest and INT6* the lowest. Two interrupt acknowledge methods can be used: 1. The CPU PCB can write to the bus slave to reset the interrupt. 3-18 Principles of Operation 2. Software handshaking. The interrupt request indicates an interrupt vector is in memory. The CPU PCB would read the vector and set a flag indicating the slave can reset the interrupt request. Bus Exchange The system bus can accommodate eight bus masters. Each master requests the bus on a bus request line (BRQx*). BRQ9* has the highest priority while BRQ7* has the lowest. Parallel priority arbitration is used. The highest priority request receives its bus priority in signal (BPNx*). When BUSY* is cleared and BPNx* is asserted, the bus switches to the new master. The following is the basic bus exchange timing: BCLK* BRQx* I \ BPNx* \ CBRQ* \ BUSY* old master I I I \ new master All bus exchange lines are asserted on the falling edge of BCLK*. 3-19 Principles of Operation Lock Operation The system bus may be lockeq for a maximum of 8 microseconds. The LOCR* signal is set and BUSY* is held asserted during locked bus operations. BUSY* held asserted is the mechanism for locking the system bus. LOCR* is required during read-modify-write operations to multiported memories to hold off accesses by other processors. Timing All timing is referenced at the input/output pins of the backplane PCB slot. The bus propagation and settling time of 4 nanoseconds is added to ALL timing calculations. Slaves drive both AACK* and XACK*. Read Timing_ diagrams: The following is the read timing 3-29 Principles of Operation 1<---MRD* or IORD* -->1 -- / ns min -->1 1<-valid address V -------./\ o ->1 1<- AACK* -->1 / XACK* 1<-1<- -->1 \ 100 ns max ->1 data V /\ 10 ns max / 1<- -->1 valid data ->1 1<- '-\ 1<-- 0 ns min V /\ \ 100 ns max -->1 o ns min ->1 ERR* ----->1 \ 30 ns min address 100 ns min 1<-- 65 ns max / 1<-- 65 ns max / 1<-- 65 ns max 1<-- 65 ns max V /\ -->1 / / (asserted by slave on MRD* if parity error occurs) 3-21 Principles of Operation I/O Write Timing. timing diagrams: The following is the I/O write 1<----- 100 ns .in ---->1 IOWT* 30 address 30 data 1 \ ns .in -->1 -->1 1<-- 30 ns .in valId address V V 1\~--------------------------~/\~-----ns .in -->1 1<-- -->1 valid data V V 1\~--------------------------~/\~------ o ns .in -->1 AACK* 1<-- -->1 1<-- 65 ns max 65 ns .ax \~--------~----~/----~I 100 ns .ax -->1 o ns min -->1 XACl{* 1<-- 1<-1<-- -->1 1<-- \~--------~/----~I 3-22 Principles of Operation Memory Write Timing. timing diagrams: The following is the memory write 1<----- 100 ns min ---->1 \~----------------~I MWT* 30 ns min address -->1 1<-- -->1 valid address V V ------~/\~----------------------------~1\ 30 ns max -->1 data 1<-- -->1 valid data V 1\ o ns min -->1 1<-- 30 ns min V 1\ 1<-- -->1 1<-- 65 ns max 65 ns max \ ~______________-JI____~1 AACK* 100 ns max o ns min -->1 XACK* 1<-- 30 ns min -->1 1<-1<-- -->1 1<-- \~--------~/----~1 NOTE Data can have -30 nanoseconds setup to MWT*. 3-23 Principles of Operation Bus Ezcbange Timing. A 9.83 MHz bus clock is used for bus control timing. All bus exchange timing is referenced by the falling edge of BCLK*. The following is the bus exchange timing diagrams: I I I_I BCLK* 35 ns max ->1 BRQx* I I I_I I I I_I -->1 1<-- I I I_I I 1- 1<-- 35 ns max '--' 25 ns min -->1 , BPNx* , 1<-- 25 ns min ~--------~/----~/--------------- 1<-- 60 ns max , , -->1 70 ns max -->1 1<->1 1<-- 70 ns max I I' ' .....__--__--:-__--_ 60 ns max -->1 CBRQ* -->1 1<-- 1<-- ~--------~/--~I BUSY* old master new master NOTE 1. A bus requester can receive bus priority and then lose bus priority before the bus is released (BUSY* deasserted) if a higher priority bus master has requested the bus before BUSY* was deasserted. 2. A bus master can assert its bus request, then deassert its bus request without taking ownership of the bus. Bus Lock Timing. The current bus owner can keep the system bus indefinitely, by holding BUSY* asserted, if no other bus master requests the bus. If another bus master requests the bus, by asserting CBRQ*, the current bus master must release the bus within 8 microseconds. 3-24 Principles of Operation NOTE The file processor is the only exception to releasing the bus in 8 microseconds. The file processor can hold the bus up to 299 microseconds regardless of how long the CBRQ* signal is asserted. The LOCK* signal is used during read-modify-write operations to multiported memories. The addressed slave only allows access to the system bus owner when LOCK* is asserted. The following is the bus lock timing diagram: -' ,- VV V ----1\~_____________~ ~__________-JI'-I\..."...J\ address--V MWT* or MRD* ,, I \ XACK* I- " \ BUSY* - \ ' -_ _ _ _ _ _ _ _ _ __ \ '--_ _--'1-- _____ , ,- - - - - 1<-100 ns min-> 1 LOCK* \' -_ _ _ _ _--'1 ~/- 1<-100 ns min-> 1 \~---------"---_ _ _ _--~I 1<---------------- 8 us max ---------------->1 Bus Timeout Timing. timing diagram: ERR* The following is the bus timeout ,~------------~/ 30 ns min -->1 XACK* and AACK* 1<-- ,'--------/ 3-25 Principles of Operation (BLANK) 3-26 Principles of Operation Central Processing Unit (CPU) PCB The function of the CPU PCB is to execute all the system and applications programs. Refer to the Schematic Diagrams supplement to this manual for the block and schematic diagrams of the CPU PCB. The CPU PCB uses an 80286 microprocessor, an optional 80287 80-bit floating-point numeric processor extension (installed on the -002 version of the CPU PCB), PROM, local RAM, a calendar clock with battery back up, and a system bus interface. The CPU PCB uses four major circuits: 80286 (and optional 80287 numeric processor), three independent controller units that control the local bus interface; translation table and tag RAM memory interfaces; and the cache and 32-bit system bus interface. CPU Initialization The 80286' microprocessor operates in two modes: real address and protected mode. When power-up or system reset occurs, the 80286 microprocessor powers up in the real address mode. The 80286 cannot be fully initialized without first switching to protected mode because the 80286 has no knowledge of the 16M byte addressing space and cannot access all of the areas of the memory map. Refer to the Intel IAPX 286 Programmer's Reference Manual for additional details on the 80286 initialization and protected-mode operation. The cache, tag, and translation table memories all contain random data at power-up and must be initialized. To initialize the cache, all the valid bits of the tag RAM are written as invalid, which invalidates all data in the cache. The address translation table RAM must be written to assure proper system memory accesses. All of the control bits in the output latch port are set low at power-up. Only one bit enables/disables the cache memory_ Thus, all accesses to system memory will not use the cache until these bits are enabled. 3-27 Principles of Operation The clear error status (CLR ERR STATUS*) bit will also be low which means that no nonmaskable interrupts (NMls) can occur until this bit is set high. Microprocessor The CPU PCB uses a l6-bit 89286 microprocessor that provides memory management and support for the optional 80287 floating-point numeric processor. The 89286 microprocessor runs at 8 MHZ! and executes programs out of either PROM, cache, or system memory. The 89286 runs out of the cache memory with no wait states most of the time because most system and application programs address memory sequentially. Microprocessor Address Decoder Logic The address decoder PAL (7A) decodes the microprocessor address space into seven major decodes. The local bus decodes (LBS) signal is further decoded into four select signals. All input/ output (I/O), local and system, is memory mapped. All decodes except the bus I/O (BID) are latched. The READY signal provides the window for the mapped address latch enable (MALE) signal to latch the proper decode. Refer to Timing Diagrams at the back of this section for detailed timing information. 80286 Memory Map The 89286 memory map is shown in Figure 3-1. The local peripherals include the calendar clock, interrupt controller, output latch port, and input status port. The memory map also contains areas that include the translation table, cache memory, and tag RAMs. The accessibility of these RAMs provides the ability to change the address map and perform cache diagnostics. The two remaining areas in the memory map are the system bus I/O space and the system bus memory space. When accessing the system bus I/O space, the I/O address is formed by using the lower 16 bits of the 80286 24-bit address. System memory accessing is discussed later. 3-28 Principles of Operation Local Bus Control Logic The local bus is controlled by the local bus controller PAL (19C). This PAL is a state machine with eight operating states. Any Ts bus state starts the state machine. In state one, the cycle is qualified by the EPROM, LBS (local bus select), INTA (interrupt acknowledge), or 80287 numeric processor decodes. The state machine continues to operate if a local bus cycle is detected, otherwise it returns to the idle state. The controller asserts the local bus synchronous ready (LBSR) signal when finished and waits for the READY signal to be asserted and terminate the cycle. The LBS signal decode includes the clock/calendar, status port, control port, and interrupt controller. Refer to Timing Diagrams at the back of this section for detailed timing information. 3-29 Principles of Operation FFFFFFh Monitor FFDfJfJ2h Start of Monitor Code FFDfJfJfJh Monitor Revision Nmnber Diagnostics Start of Diagnostic Code FFCfJfJ2h FFCfJfJfJh Start of PROM and Diagnostic Revision Nmnber p 42fJfJfJfJh Empty System Bus I/O 4 HHtJfJ0h Empty Local RAM 404fJ00h Cache RAM 403000h Monitor RAM Diagnostic Data Monitor Data Stack 4020fJfJh 40l80fJh Empty .. _ Tag RAM 40l000h 4008fJ0h Translation RAM v 0/ Figure 3-1. 88286 Memory Map 3-30 Principles of Operation - I"\- ~f1- 4rlJrlJ8rlJrlJh Empty 4rlJrlJ3rlJlh Input Latch Port 4rlJriJ3rlJriJh Empty 4rlJriJ2riJ4h ICW2, ICW3, ICW4 4rlJriJ2rlJ2h ICWl 4rlJriJ2rlJrlJh Empty 4rlJriJlrlJlh Output Latch Port 4rlJriJlrlJrlJh Empty 4rlJrlJrlJ3rlJh Clock I/O 'Test Mode Standby Interrupt Go Command Status Bit RAM Reset Counters Reset Interrupt Control Register Interrupt Status Register 4rlJrlJrlJ21h 4rlJrlJrlJ21h Figure 3-1. ... I.t- 88286 Memory Map (Cont.) Clock RAIl 3-31 Principles of Operation -I"'- Month Day of Month Day of Week Hours Minutes Seconds Hundredths and Tenths Ten Thousandths of Seconds 4BBBllh----~--------------------------~ Clock Month Day of Month Day of Week Hours lrlinutes Seconds Hundredths and Tenths Ten thousandths of Seconds 4BBBBlh----~--------------------------~ Empty 4BBBBBh----~--------------------------~ System Bus Memory BBBBBBh----~--------------------------~ Figure 3-1. 88286 Memory Map (Cont.) 3-32 Principles of Operation Local Bus The local bus on the CPU PCB handles data transfers for the PROM, calendar clock IC, interrupt controller, input status port, and output latch port. The bit definitions of the input status port and the output latch port are listed in Tables 3-1 and 3-2. Boot and initialization programs are contained in the PROM. The CPU PCB can support either 16K or 32K bytes of boot program (use 32K bytes when out of program space on 16K bytes). ~able Bit Logic Level 00 1 01 fa 1 02 fa 1 03 fa 1 04 3-1. fa 1 05 1 Input Status-Port Bit Definitions Description Jumper installed between pins 7 and 8 of connector E2. Enables diagnostic loop-on-error No jumper between pins 7 and 8 of E2 Jumper installed between pins 5 and 6 of connector E2 No jumper between pins 5 and 6 of E2 Jumper installed between pins 3 and 4 of connector E2 No jumper between pins 3 and 4 of E2 Jumper installed between pins 1 and 2 of connector E2 No jumper between pins 1 and 2 of E2 System bus timeout* bit inactive System bus timeout bit active (bus timeout occurred) Uninterruptable supplying power Uninterruptable supplying power condi tion) 3-33 power source (UPS) (normal operation) power source (UPS) (power-fail Principles of Operation ~able Bit 3-1. Input Status-POrt Bit Definitions (Cont.) Logic Level Description D6 9 1 Latched UPS power-fail condition inactive Latched UPS power-fail condition active (power-fail occurred) D7 9 1 Latched bus error bit inactive Latched bus error bit active (bus error occurred)** * Timeout occurs when any bus command (lORD, IOWT, MRD, MWT) exceeds 4 microseconds. ** Bus error set: (1) by memory PCB on a read if a parity error is detected, or (2) when a CPU generated bus timeout has occurred on memory operations only. 7able 3-2. Output-Latch Bit Definitions Bit* Level Description DO 9 1 Cache disabled Cache enabled Dl 9 1 System bus INT6 inactive System bus INT6 active D2 9 1 System bus INT5 inactive System bus INT5 active D3 D4 Not connected D5 Forces system bus write on cache search D6 D7 9 1 CLR ERR STATUS active CLR ERR STATUS inactive * All these bits are used by power-up diagnostics. 3-34 Principles of Operation Calendar Clock The calendar clock is a National 58167 IC that keeps time and generates system time slice interrupts. Refer to the National 58167 Applications Note Data Handbook for operating details. Interrupt Controller The interrupt controller is an Intel 8259A-2 IC. Refer to the Intel Microsystem Components Handbook for additional operating details. The interrupt controller takes interrupts from the calendar clock IC and system bus interrupt lines. The interrupt request levels are described in Table 3-3. ~able priority 1 2 3 4 5 6 7 8 3-3. Interrupt Request Levels Ie Pin Description lRO lRl lR2 lR3 lR4 IRS lR6 IR7 Calendar clock interrupt System bus INT9 System bus INTI System bus INT2 System bus INT3 System bus INT4 System bus INT5 System bus INT6 System Memory Accessing and Address Translation The 89286 microprocessor, in protected mode, has a virtual address space of lG (giga) byte and physical address space of 16M bytes. The 89286 internal memory management makes the translation from virtual to physical memory. Refer to the Intel IAPX 286 Programmer's Reference Manual for a description of the 80286 memory management operation. The 16M byte physical address space is used for all I/O and memory accessing except transfer to/from the optional 80287. floating-point processor. 3-35 Principles of Operation A memory map for the physical address space is shown in Figure 3-2. The translation RAM can be set up to access memory anywhere within the 16M byte physical address space. Note that the low 4M bytes of the 80286 physical address space is mapped into the system bus memory address space. The system-bus memory address is formed by concatenating the lower 12 bits of the 80286 physical address with the 12-bit output of the translation RAM. The low order bits of the 80286 form bits 0-11 of the system bus address and the 12 bits from the translation RAM form bits 12-24 of the system bus address. Each location in the translation table covers 4K bytes of the system memory address space. There are 1024 locations in the translation table. The contents of the translation table are treated as memory mapped and are accessible as part of the 80286 address space. The translation table memory must be read and written with 16 bit transfers; no byte transfers are allowed. The translation table contents are initialized as described in Table 3-4. Table 3-5 lists the translation-table bit definitions. if'able 3-4. Translation-Table Addresses Block 000 001 002 Port Address (Hex) 81286 Address Range (Hex) 400800 400802 400804 000000 - 000FFF 001000 - 001FFF 002000 - 002FFF • • • . 3FF • 3FF000 - 3FFFFF 400FFE 3-36 Principles of Operation NOTE During system operation, the block numbers and 80286 address range are not mapped one-to-one. 'table 3-5. Translation-Table Bit Definitions Bit Description 0 1 2 3 4 5 6 7 8 9 10 11 System System System System System System System System System System System System bus bus bus bus bus bus bus bus bus bus bus bus memory memory memory memory memory memory memory memory memory memory memory memory address address address address address address address address address address address address bit bit bit bit bit bit bit bit bit bit bit bit 12 13 14 15 16 17 18 19 20 21 22 23 Tag and Translation RAM Control Logic The tag and translation RAM control logic is contained in the tag and translation RAM controller PAL (2B). The state machine PAL (lB) starts on CPU system memory, tag and translation RAM I/O, and non-CPU system memory write operations. During CPU memory operations, the tag and translation table data are compared for a match (hit) which indicates that the cache is saving that address. r On CPU reads, a hit indicates that the cache data is valid and, thus, the cache data is read instead of system memory. A miss causes system memory to be accessed. On CPU writes, no operation is performed. System bus memory writes (non-CPU) are monitored for a CPU cache hit. If a hit occurs, the corresponding tag for the cache data is invalidated because cache data and system memory are not the same. During tag and translation table I/O operations, the appropriate 3-37 PrInciples of Operation address and data buffer enable, and RAM control signals are generated. Refer to Timing Diagrams at the back of this section for detailed timing information. Cache Memory Organization The cache memory on the CPU PCB is a 4K byte singleset associating cache (directly mapped) with a block size of 4 bytes that includes both instructions and data. The cache memory will cache data from anywhere in the 16M byte address space of the system bus (if the translation table is appropriately set up). The cache memory uses three bit fields of the 24 bit system bus memory address as shown in Figure 3-2. These bit fields are the tag field, the offset field, and the byte-select field. SYSTEM MEMORY SYSTEM MEMORY ADDRESS TAG Ipage 1° 2147 ;;. ~ Page 2 BITS NOTE • Tag field specifies the page number. • Offset field specifies the block location within the page. • Byte-select field specifies the byte within the block. Page 1 Page " 01071 Figure 3-2. caChe Memory Organization 3-38 Principles of Operation The tag field effectively breaks up the memory space into a number of pages. The byte location within a page is specified by the offset and byte-select fields. When a block from system memory is stored in the cache memory, the offset field specifies where in the cache that particular block will be stored. The offset field also specifies where in the tag memory the tag for the memory location should be stored. The value loaded into the tag memory is the page number from which the memory block came. When a memory read occurs, the offset field will specify a location in the tag memory. If the page number in the tag memory matches the page number in the translation table, then a hit occurs and a copy of the desired memory location resides in the cache memory. This operation is called a cache memory search as shown in Figure 3-3. A write-through technique keeps the data in cache memory identical to the data in system memory during CPU writes. The cache memory is written whenever a memory write with a cache hit occurs or when a memory read with a cache miss occurs. When a memory-read cache miss occurs, a 4 byte block is loaded into the cache memory. Since the 80286 fetches instructions 16 bits at a time, sequential accesses should produce a cache hit for every other memory read. The cache control logic is contained in the cache control PALs (17C, 18C). The state machine PAL (17C) starts on a cache RAM I/O, bus memory, or bus I/O operation and finishes when the READY signal is asserted. There are 8K bytes of local RAM memory with 4K bytes used for the cache memory and the remaining 4K bytes are for general-purpose use. All 8K bytes of local memory are accessible with a cache RAM I/O (CIa) operation. If a hit occurs during a memory read, the cache RAM is read instead of system memory. If a miss occurs during a memory read, system memory is read and the tag RAM is updated. If a hit occurs during a memory write, both the cache RAM and system memory are written. If a miss occurs during a memory write, only system memory is written. 3-39 Principles of Operation SYSTEM BUS MEMORY ADDRESS 12 11 12 BITS TAG RAM HIT TO CPU 02001 Figure 3-3. cacbe Memory Searcb If the CPU does not own the system bus, a bus request (BUSREQ) signal is generated for all bus I/O and system memory write and read (miss) operations. Refer to Timing Diagrams at the back of this section for detailed timing information. 3-40 Principles of Operation The cache control logic also guarantees cache data coherency with system memory by performing cache searches for all system memory writes generated by other system bus masters, such as, I/O serial or file processors. If such a cache search produces a hit, then that cache memory location will be marked as invalid which guarantees that only valid data can be read from the cache. The tag and cache memories can be directly read and written by the 89286 for diagnostic and initialization purposes. The address locations of the tag and cache memories are shown in Figure 3-2. The tag memory must be read and written with l6-bit transfers, no byte transfers are allowed. The cache memory can be accessed as either bytes or words. The bit definitions for accessing the tag memory are listed in Table 3-6. ~able 3-6. Tag-Memory Bit Definitions Bit Description 09 01 02 03 04 Page number Page number Page number Page number Page number Page number Page number Page number Page number Page number Page number Page number Valid bit * 05 06 07 08 09 b19 011 012 bit bit bit bit bit bit bit bit bit bit bit bit 9 1 2 3 4 5 6 7 8 9 19 11 * The cache data is valid when the valid bit is 9 and invalid when the valid bit is 1. System Bus Arbiter and Priority Encoding Logic The system bus arbiter and priority encoder PAL (110) arbitrates and encodes the system bus requests from the bus masters. 3-41 Principles of Operation When a bus master wants the bus, its bus request and common bus request signals are asserted. The highest priority request is encoded in the A, B, and C outputs and decoded externally to give a bus grant to the requesting master. While the bus master has the bus, the BUSY signal is asserted. The common bus request (CBRQ) signal is used to determine if another bus master wants the bus. When BUSY is cleared and a bus grant (BPN8-7) signal is asserted the bus can be acquired by another bus master. Refer to ~iming Diagrams at the back of this section for detailed timing information. Microprocessor Ready Generator The ready generator for the 88286 microprocessor is contained in the ready generator PAL (9D). Clock land 2 are phase synchronized with the mapped address latch enable (MALE) and READY signals. The READY signal is asserted when either the local bus ready (LBSR), tag or translation table synchronous ready (TTSR), or cache synchronous ready (CSR) signals is asserted or, on the second phase of Tc, when the advanced transfer acknowledge (AACK) signal from the system bus is asserted. Jumper Descriptions The CPU PCB has eight jumper connectors designated El through E8. These jumpers are properly installed at the factory and should not be changed. Table 3-7 describes the functions of the jumper connectors. The descriptions apply for both the -801 and -882 versions of the CPU PCB unless specified otherwise. Refer to Appendix A for detailed jumpering information. 3-42 Principles of Operation Table 3-7. Jumper Descriptions Connector DeSignation Description EI Generates a manual NMI (pins I and 2 jumpered) E2 Used by software. Provides configuration bit 3 (pins I and 2 jumpered); configuration bit 2 (pins 3 and 4 jumpered); configuration bit I (pins 5 and 6 jumpered); forces power-up diagnostics to loop on error (pins 7 and 8 jumpered) E3 Enables priority bus arbiter for the system (pins I and 3 jumpered). Disables priority bus arbiter for the slave CPU (pins 2 and 4, and 5 and 6 jumpered) E4 Enables the CPU reset to drive the system reset (pins I and 2 jumpered) E5 Adds bus grant no. 6 to the priority bus arbiter for the slave CPU (pins I and 2 jumpered) E6 -882 version only. Divides the 88286 clock by 3 (5.33 MHz) for use by the 88287-3 numeric processor (pins I and 2, and 4 and 6 jumpered). Supplies the clock generated by the 8284, which is 24 MHz divided by 3 (8 MHz,) for use by the 88287-8 numeric processor (pins I and 3, and 5 and 6 jumpered) E7 Enables the system bus clock (pins I and 2 jumpered) E8 Testability jumper. Automatic test equipment (ATE) generates an 88286 micrpprocessor clock during testing 3-43 Principles of Operation Timing Diagrams The major timing diagrams for the CPU PCB are shown in Figure 3-4. Sample Period Magn if i cati on Magnify About Cursor Moves [ J] 250.0 nS/div 10.0121 nS/clk 5.1211121 IJS 0 to x 0 . . .· ... ·1·.·' . _ _ _ _ _ _ -·······,·········,····, ···,·········1· 7A - Address Decoder PAL Sample Period Magnification Magnify About Cursor Moves [ J] 11210.121 nS/div 1121.0121 nS/clk 23121.0 nS 0 to x 0 - - _ • • . • • • • • • ; • • • • • • • • • ; • • • • • • • , . , • • • • • • • • • 1 • • • • • • • • • • • • • • • • • • • , • • • • • • • • • ; • • • • • • • • • ; • • • • • • • • • ; •• 19C - Local Bus State Machine PAL (PROM Read Cycle) Figure 3-4. CPU PCB Timing Diagrams 3-44 Principles of Operation Sample Period Magnification Magnif\,J About Cur'sor Moves [ t ] 100.0 nS/div 20.08 nS/clk 588.8 nS 0 to x x 0 19C - Local Bus State Machine PAL (88287 Write Cycle) Sample Period Magnification Magnif\,J About Cursor Moves [ J.] 288.0 nS/div 20.00 nS/clk 2.768 I-lS 0 to x 0 . . I····'····r·········,···· ...... , ........ , ...... _-- 19C - Local Bus State Machine PAL (calendar Clock Read Cycle) Figure 3-4. CPO PCB Timing Diagrams (Cont.) 3-45 PrincIples of Operation Sample Period Magnification Magnif;"l About Cursor Moves 200.0 nS/div 28.80 nS/clk 1. 600 f,.lS 0 to x [ .J. ] . . ·I··'·····'I·-·····_.~-·I·········I····'····I·······_.,. 19C - Local Bus State Machine PAL (calendar Clock write Cycle) Sample Period Magnification Magnify About Cursor Moves [ .!.] 0 180.8 nS/div 10.00 nS/clk 4.960 IJS 0 to x x 19C - Local Bus state Machine PAL (Status Port/Control Port/priority Interrupt COntroller Read Cycle) Pigure 3-4. CPU PCB Timing Diagrams (Cont.) 3-46 Principles of Operation Sample Period Magnification Magnify About 100.0 nS/div 10.00 nS/clk 5.030 fl5 0 to x Cursor Moves [ J, ] 19C - Local Bus State Machine PAL (Status Port/Control Port/Priority Interrupt Controller Write Cycle) Sample Period Magnification Magnify About 200.0 nS/div 20.00 nS/clk 760.0 nS x to Cursor Moves ( .J, ] 0 o x ., .............. _-- Interrupt Acknowledge Cycle Figure 3-4. CPO PCB Timing Diagrams (Cont.) 3-47 Principles of Operation Sample Period Magnification Magnify About Cursot' Moves .1 ~] 100.0 nS/div 10.00 nS/clk 5.040 IJS 0 to x 0 . . ·1·········,·····,··.,·,·······1· 1B, 2B - Tag state Machine PALs (System Memory Read Miss) Sample Period Magnification Magnify About Cursor Moves [ !] 108.0 nS/div 10.00 nS/clk 5.040 IJS 0 to x x 0 . " _~···'I········,····'····,·········,·········I·· 1B, 2B - Tag State Machine PALs (System Memory Read Bit) Figure 3-4. CPO PCB Timing Diagrams (Cont.) 3-48 Principles of Operation Sample Period Magn i fi cat ion Magnify About Cursor Moves [ .t.] 50.00 nS/div 10.00 nS/clk 5.110 IJS 0 to x x 0 lB, 2B - Tag state Machine PALs (~stem Bus write Monitoring) Sample Period Magnification Magnify About Cursor Moves [ !] 50.00 nS/div 10.00 nS/clk 4.970 IJS 0 to )( x 0 IBr 2B - Tag State Machine PALs (Tag/Translation Table I/O Read CYcle) Figure 3-4. CPU PCB Timing Diagrams (Cont.) 3-49 Principles of Operation Sample Period Magnification Magnify About Cursor Moves [ J, ] 513.1313 nS/div 113.1313 nS/clk 4.9713 fJS 0 to x 0 .. . . . . . . . . , ........ , I········ ., ........ , ..... , .. " ....... .-...-.,., ... , ......... 1.···.·· .. 1.· .... , .. , ........ '1.' lB, 2B - Tag state Machine PALs (Tag/Translation Table I/O Write cycle) Sample Period Magnification Magnify About Cursor Moves [ !] 11313.13 nS/div 113.1313 nS/clk 5.13213 I-lS 0 to x x 0 . . . ··,·········1· , . . . . --_··,·········,·········1···.···.·,.·· .. ····,· l7C, l8C - Cache state Machine PALs (System Memory Read Bit cycle) Figure 3-4. CPO PCB Tiaing Diagrams (Cont.) 3-50 Principles of Operation Sample Period Magnification Magnify About Cursor Moves [ .\.] 108.0 nS/div 10.00 nS/clk 5.030 JJS 0 to x x 0 l7C, lSC - Cache state Machine PALs (System Memory Read Miss Cycle) Sample Period Magnification Magnify About Cursor Moves [ .\.] 100.0 nS/div 20.00 nS/clk 10.10 jJ.S 0 to x x 0 . . . .. ·········1·········,········1··'······1········_·····, ........ , ......... / .. . l7C, ISC - Cache state Machine PALs (System Memory Write Hit Cycle) Figure 3~4. CPU PCB Timing Diagrams (Cont.) 3-51 PrInciples of Operation Sample Period Magnification Magnify About Cursor Moves [ J.] 188.8 nS/div 28.80 nS/clk 18.14 f,.IS 0 to x 0 . . . . . . . . •••••••.• , .•••••••. , ••••••••• , • . • • • . • • ,. ~""""I"""""'-"""I""""'I""""'_"'" l7C, .1BC - Cache state Machine PALs (System Memory write Miss Cycle) Sample Period Magnification Magnify About Cursor Moves [ J.] 188.8 nS/div 28.80 nS/clk 9.828 f,.IS 0 to x x 0 . ........... , ..•..•... ! . . . l7C, lBC - Cache state Machine PALs (System Bus I/O Write Cycle) Figure 3-4. . . . • . . • . . , • . . . . . . • • , • . • . . • .- - • • • . • • • . • • • • • • • • , . • • • • • • . • , •• .: • • • • • . , . . • • • . . • • , •• CPU PCB Timing Diagrams (Cont.) 3-52 Principles of Operation Sample Period Magnification Magnify About Cursor Moves [ .l. ] 100.0 nS/div 10.00 nS/clk 5.0913 I-lS 0 to )( 0 _--1········1·········1·········.·· 17C, 18C - Cache state Machine PALs (Cache I/O Read CYcle) Sample Period Magnification Magnify About Cursor Moves [ !] 11313.8 nS!'div 18.013 nS!'clk 5.8913 I-lS 0 to x 0 . . . . . . . _ _ ,·········,·········,·····,···,·· .. ·····1·· ~·,······,,········I·"······I·········I········_, 17C, laC - Cache state Machine PALs (Cache I/O Write cycle) Figure 3-4. CPU PCB Timing Diagrams (Cont.) 3-53 Principles of Operation Sample Period Magnification Magnify About Cursor Moves [ J. ] 0 x 250.0 nS/div 18.00 nS/clk 5.000 I-lS 0 to x System Bus Arbitration Sample Period Magnification Magnify About Cursor Moves [ J.] 100.0 nS/div 10.00 nS/clk 5.040 I-lS 0 to x x 0 . . . . . . . . . ·········,·········1·········1·········1·····_-_···1.········1·········1········,1·'·······.· 9D - Ready Generator PAL Pigure 3-4. CPO PCB Timing Diagrams (Cont.) 3-54 Principles of Operation Memory PCB The function of the memory PCB is to provide 1M, 2M, or 4M bytes of dynamic RAM for the system. There are two versions of the the memory PCB used in this system: version 1 (part no. 615-l5l46-XXX) and version 2 (part no. 615-l65B9-XXX). Both versions are nearly identical. The following information applies to both versions with information for version 2 included in parenthesis. Refer to the Schematic Diagrams supplement to this manual for the block and schematic diagrams of the applicable memory PCB. The memory PCB uses 64K x 1 bit dynamic RAMs to provide 1M byte of system memory or 256K x 1 bit dynamic RAMs to provide 2M or 4M bytes of system memory. Multiple memory PCBs with different capacities can be used to expand system memory to 16M bytes (provided the necessary PCB slots are available in the existing configuration). Each version of the memory PCB is fully compatible with the others, which allows the system to be upgraded in the field. System memory is organized into long words of 32 bits with byte parity detection. (Version 2 is organized into double long words of 64 bits with byte parity detection. The double long words are multiplexed onto the system bus by two sets of 32-bit transceivers.) Transfers to/from memory can be made in 8, 16, or 32-bit widths as required by the bus master. Each memory read cycle causes all 32 (or 64) bits to be checked for proper parity, although not all the bits may be transferred to the bus master. Refresh for the dynamic RAMs is handled on each memory PCB, and is fully transparent to the bus master. This makes the memory look static to the requestor. System Bus Interface Since it is possible to have multiple memory PCBs in the system, a board-select comparator on each memory PCB is set (by jumpers on connectors El and E2) to uniquely address each PCB within the system memory space. 3-55 Principles of Operation When multiple PCBs are used, the proper jumper configuration ensures that, when viewed from any bus master, a single contiguous memory space exists regardless of the number or type of memory PCBs. Data transfer to/from a memory PCB is initiated by either a memory read command and a board-select address match or a memory write command and a board-select address match. Once the transfer is initiated, 1, 2, or 4M bytes of data are transferred to/from the memory PCB depending upon the state of four bus signals: HWEN* (high word enable), HBEN* (high byte enable), Al* (address bit 1), and A0* (address bit 0). These four Signals control the data transceivers to/from the system bus, as well as the write-enable lines to the RAMs. (Version 2 has six bus signals: HWEN*, HBEN*, HLWEN* (high long word enable), A0, AI, and A0.) The selected memory PCB also produces three signals to indicate the status of the data transfer: 1. AACK* - Advanced data transfer acknowledge 2. XACK* - Data transfer acknowledge 3. ERR* - Error Signal AACK* goes true before the transfer of valid data is complete, and acts as an advanced version of XACK* to signal the bus master when the requested bus transaction is about to be completed. Signal AACK* is used by some bus masters (CPU, file processor, or communications subsystems) to reduce wait states. Signal XACK* goes true to acknowledge transfer and signal the bus master that valid data has been placed or accepted on the bus. Signal ERR* is the general bus error signal, which the selected memory PCB drives with the results of the on-board parity Checkers. Signal ERR* is only active during memory read cycles when a parity error is detected, and will be valid about 25 nanoseconds after XACK* goes true. Signal ERR* is monitored by each bus master to determine if an error occurred during the bus cycle. 3-56 Principles of Operation NOTE Four bytes (version 2 - eight bytes) are parity checked during each memory read, regardless of the state of HWEN* and HBEN*. This means that, during memory initialization, a group of 4 (or 8) bytes at a time must be initialized (written to) before reading any of them back. Failure to observe this precaution will generate false parity errors. Row/Column Address Decoder The row/column address decoder PAL (14C) (version 2 l6C) inputs system bus addresses A18-A29 and generates two 1-of-4 memory block enables; one for the row address strobe and one for the column address strobe. The memory PCB is divided into four blocks of memory that get enabled one at a time depending upon the address. (Version 2 is divided into two half-blocks of memory that get enabled one half-block at a time depending upon the address.) Input signals HALF and 64KS are jumper selectable to indicate the size of the RAMs installed and whether the PCB is fully or partially populated. The HALF and 64KS signals determine which two of the four address lines will be decoded. Memory Transceiver Control The memory transceiver control PAL (llF) (version 2 19F and 29F) inputs signals A9, AI, (and A2 for version 2), HBEN (high byte enable), HWEN (high word enable), (HLWEN*, high long word enable, for version 2), and MWT* (memory write) from the system bus. This PAL enables one, two, or four of the data transceivers between the memory array and the system data bus. 3-57 Principles ·of Operation Signals AB and AI, (and A2 and HLWEN* for version 2), HBEN, HWEN, and MWT* control the four (or eight for version 2) write enable signals (WENB*-WEN3*) (or WENB*-WEN7* for version 2) to the RAM array. Together, the signals select either 1, 2, or 4 bytes for transfer to/from the system bus. The byte-swap enable outputs (BSENB* and BSENl*) (or BSENB*-BSEN3* for version 2) enable two (or four for version 2) data transceivers to do byte swapping so that data from bits DB through DIS on the system data bus is transferred to address MD16 through MD3l (and, depending on A2 and HLWEN*, MD48 through MD63 for version 2) in the memory array. Memory Arbiter The memory arbiter PAL (15C) (version 2 - l7C) is a state machine that generates timing signals for the memory PCB. Memory read or write commands from the system bus produce outputs at the row address strobes RAS and RASB ,advanced acknowledge clock ACKCLK, and write transfer acknowledge clock WXACK. Refresh cycles, identified by input signal RFCY true, generate RAS, RASB, and RFEN (refresh enable) signals to the memory PCB. Refer to Timing Diagrams at the back of this section for detailed timing information. RAM Refresh Each memory PCB has its own refresh control logic that ensures that the entire RAM array on each PCB is refreshed about every 4 milliseconds. Refresh is accomplished by simply dividing down the system bus clock (about lB MHz) to a 15 microsecond rate, which ensures that all of the 256 rows within the RAM get refreshed within 4 milliseconds. Since the refresh timer is free-running, a bus master may request a memory transfer at the same time a refresh cycle is taking place (or is about to take place) • 3-58 Principles of Operation On-board arbitration ensures that the potential conflict between refresh and system-bus-cycle request is properly cued and executed. The arbitration is totally transparent to the requesting bus master, except for the additional wait-states that may occur as a result of waiting for a refresh cycle to complete. Address Space Allocation The memory PCB has two jumper connectors designated E1 and E2 located near the top center of the board. Each of these connectors has 19 pins (five positions). Jumper connector El is jumpered according to the type of memory PCB (1M, 2M, or 4M bytes of RAM on the PCB). Jumper connector E2 is jumpered to set the address space that the memory PCB will occupy within the system. The jumpers are properly installed at the factory for the shipped configuration, and should not need to be changed unless additional memory PCBs are added or the type of .memory PCBs are changed in the field. The jumpers should be installed so that: (1) the sum of all the address space available on the memory PCBs present a single, contiguous, memory space to the CPU, and (2) address space is allocated beginning with the memory PCB that has the largest memory capacity and progressing contiguously to the memory PCB with the smallest memory capacity (refer to Plug-In Printed Circuit Board Locations in Chapter 1 for the recommended memory PCB locations). Refer to Appendix A for specific jumpering information. Timing Diagrams The major memory PCB timing diagrams are shown in Figure 3-5. 3-59 Principles of Operation Sample Period Magnification Magnify About Cursor Moves .... 11313.13 nS/div 10.1313 nS/clk 4113.13 nS x to [ ! ] 0 o ·1 el I:! III• • •: fe -. iii ., 11M . :i .. ···.·········1······ l5C (17C)- Memory Arbiter PAL (Normal Refresh cycle - No Arbitration) Period Magnification Magnify About Cursor Moves Sample -'• [ 1 ] 100.0 nS/div 10.00 nS/clk 280.0 nS x to x 0 o -In j: : 1 . . - '_ ' - - - - : - _ - : - i: --:--:-ni"~,~:==~!~: : -:--:-:--:-: 1M iil·_.:-~-T--' n: : .lJ .... 1M l5C (17C) - Memory Arbiter PAL (Memory cycle - No Refresh Arbitration) Figure 3-5. Memory PCB Timing Diagrams 3-60 Principles of Operation Sample Period Magnification Magnify About Cursor Moves 100.0 nS/div 10.00 nS/clk 620.0 nS x to .' [ ! ] 0 o II L IU···~ 1M • 1M n - 1<--__-'- 15C (17C) - Memory Arbiter PAL (Memory/Refresh Request Arbitration - Refresh Runs First) Sample Period Magnification Magnify About Cursor Moves [ ! J x w,· I' 100.0 nS/div 10.08 nS/clk 270.0 nS x. to 0 o U '8' 1M • '15C (17C) Memory Arbiter PAL (Memory/Refresh Request Arbitration - Refresh Runs Second) Figure 3-5. Memory PCB Timing Diagrams (Cont.) 3-61 Principles of Operation (BLANK) 3-62 Principles of Operation Communications PCB The function of the communications (SIO) PCB is to manage all of the serial communications for the 1986/2986 system. Refer to the Schematic Diagrams supplement to this manual for the block and schematic diagrams of the communications (SIO) PCB. I/O Microprocessor The communications (SIO) PCB uses an Intel 8986 microprocessor (running at 8 MHz) as an input/output processor (lOP) that initializes and maintains all the functions on the communications (SIO) PCB. The lOP performs interrupt processing from the direct memory access (OMA) controller and each serial channel, and I/O buffer management and communication with the rest of the system. Local Arbiter The local arbiter resolves contention between the 8986 lOP, dynamic RAM refresh, and OMA controller for the local bus and decodes lOP bus cycles targeted for the system bus. There are three possible conditions which require concurrent management to ensure that only one device gets the local bus at a time: 1. lOP wants access to the local bus. 2. OMA controller wants access to the local bus. 3. Ref resh controller wants the local RAM for refresh. The lOP is permitted to access the system bus at the same time the previous three conditions are taking place (since they are occurring on separate buses). These three conditions must be made mutually exclusive since they each take control of the local bus. 3-63 Principles of Operation The local arbiter PAL integrated circuit (lIe) monitors the refresh and DMA requests, and decodes the lOP bus cycle to determine if the lOP bus cycle is intended for the local or system buses. This PAL establishes the following priorities for the local bus requests: 1. DMA controller. 2. Refresh. 3. Local bus cycles initiated by the lOP. Refer to Timing Diagrams at the back of this section for detailed timing diagrams. System Bus Interface The lOP has the capability to become a system bus master and perform memory reads and writes to system memory. Input/output (I/O) reads and writes to any I/O device (addressed lower than 8999h) on the system bus can also be performed which permits the communications peB to generate channel attention signals. Channel attention signals from the system bus intended for the communications (SIO) PCB generate a maskable, vectored, interrupt to the lOP. The system bus interface also allows the lOP to access the system bus for communicating with system memory. The 8986 lOP is the ONLY means of communication. It is NOT possible for any device on the system bus to directly affect the operation of anything on the communications (SIO) PCB, nor is it possible for any other device on this board (such as the local DMA controller) to access the system bus. lOP access to the system bus is controlled first through the local arbiter PAL (lIe) and then via the 8289 system bus arbiter. The 8289 arbiter manages lOP requests for the system bus. The system bus is essentially like the Intel Multibus but with wider data and address paths. Although the system bus is capable of double-word (32-bit) transfers, data transfers to/from the communications (SIO) PCB are restricted to 8 or 16 bits. 3-64 Principles of Operation Local Bus Controller The local bus controller PAL (l5C) generates the necessary timing for the strobes that are the result of any lOP-generated I/O reads or writes, memory reads or writes, or interrupt acknowledge. This PAL is enabled only when the lOP grant signal (IOPGNT*) is low which gives the lOP access to the local bus. The local bus controller PAL monitors the lOP latched status lines (LSB* - LS2*) and provides IO read and IO write strobes for the I/O cycles. The memory cycle (MEMCY*) signal is low for any local memory cycle1 memory write (MEMW*) is the status line that signals a read or write to local memory. Data strobe (DS*) is used by other logic to control the data transceiver enables. Refer to Timing Diagrams at the back of this section for detailed timing diagrams. Local Bus Interface The wait-state generator PAL (lBC) is only active for lOP-generated local bus cycles. This PAL monitors the lOP latched status lines and various chip select lines to determine the number of wait states for a local bus cycle. The RAM read and write" cycles require one wait state1 PROM accesses require two wait states; I/O write cycles to the SCCs require one wait state1 I/O read cycles to the SCCs require three wait states. The number of wait states for the SCC accesses may be increased by the recovery wait (RWAIT*) signal if a given SCC's recovery time has not elapsed. Interrupt acknowledge cycles cause two wait states for the interrupt acknowledge I (INTAl) signal (allows the interrupt daisy chain to settle) and one wait state for the interrupt acknowledge 2 (INTA2) signal (the cycle that actually reads the interrupt vector from the highest priority device). Refer to Timing Diagrams at the back of this section for detailed timing diagrams. 3-65 Principles of Operation Local Bus Transceiver Controller The local transceiver controller PAL (14C) performs the following functions: • monitors which device has control over the local bus (lOP, DHA, and refresh) • manages the data transceiver enables and directions between the local bus and the lOP • performs byte swaps between the upper and lower local da ta bus • controls write enable and two column address strobe (CAS*) enable signals to the local RAM Byte swapping occurs only during the bus cycles generated by the DMA controller for those data transfers between an odd memory addresses and an I/O device. Write enable (WE*) is a status line that is true throughout the entire memory write cycle. The two column address strobe (CAS*) signals enable data to be read or written from even and/or odd memory. Local Memory Initial Program Load (IPL) PROM. The communications PCB can support up to 256K bytes of PROM. Upon communications (SIO) PCB (or system) power-up or reset, the lOP begins execution at address FFFFBh (16 bytes from the absolute top of the lOP 1M byte memory space) which is at the top of the PROM. Address FFFFBh contains a jump instruction to the actual location of the initialization code, also within PROM. This code is executed upon system (or PCB) power-up or reset to perform local power-up confidence tests and initialization of the communications (SID) PCB. Then the PROM attempts to load the actual communications executive program from system memory into local RAM. See Figure 3-6 for the local memory map. 3-66 Principles of Operation FFFFFh FFFF9h start Address PROM (16K to 256K) C9999h Window Into System Memory ( 256K) 89999h Local RAM (32K to 5l2K) 99999h in system memory (offset by the system memory page register) 99999h Figure 3-6. Local Memory Map If the entire system does not power-up, or if any error is detected within the communications (SIO) PCB, a small set of interactive diagnostics are available which may be run from the channel 9 serial port (which the PROM has initialized to 9699 baud). Once the operating system has been loaded, channel 9 will be reconfigured to whatever the system software dictates. The IPL PROM also contains the necessary code to handle memory parity errors. Local and system RAM generate and check parity. Several PROM sizes are supported, depending upon software requirements. Type 2732, 2764, or 27128 PROMs can all be supported by simply changing a jumper (see JUMper Selectable Options in this section for additional jumper information). 3-67 Principles of Operation Local RAM. The local RAM is used by the lOP for program execution and also as a buffer to support communications and terminal/printer I/O. The basic system contains 32K bytes (16K words) of local RAM comprised of four 16K x 4 bit dynamic RAMs. Optional 64K x 4 bit dynamic RAMs can increase the memory to S12K bytes (2S6K words). Byte parity is also present. No error correction is done, nor is there any hardware to log the error address. Parity errors cause an NMI at the lOP. The NMI causes an error-handling routine to take control. At system initialization, the lOP firmware will attempt to load the actual lOP communications software from system memory into local RAM. Local Memory Decoder The local memory decoder PAL (19E) performs the following functions: • monitors local bus control lines, memory cycle (MEMCY*), memory write (MEMWR*), and the five high order address lines (AIS-Al9) • decodes four equal-sized blocks of RAM to provide row address strobe 9 through 3 (RAS9* - RAS3*) signals • provides a PROM chip select (PROMCS*) signal when accessing PROM The refresh grant (REFGNT*) signal is also input, which forces all four blocks of RAM to be refreshed. Jumper connector E8 is an input that determines the size of the address space that each block of RAM occupies. System Memory Page Register The system memory page register is a 6-bit write-only register which provides address bits A18 through A23 for lOP accesses to system memory as illustrated in Figure 3-7. 3-68 Principles of Operation Accessing System Memory To access system memory, the system memory page register determines the position of a 256K byte window into system memory. 8178h SYS PAGE (write strobe) S 6 DI2I-5 6 bits 6 J J 7 J 812186 Microprocessor A19 A18 ~i 3 Y S Al 8 T E M Must be set to bit code 1121 to access system RAM. A17 1,8 1 I M E M o Ai7 R Y AI2I A AI2I D D R Figure 3-7. For any value access system determine the register, use System Memory Page Register Block Diagram of the page register, the rop can only memory within a 256K byte range. To value to be programmed into the page the following formula: Page register value= integer portion of (system memory address/256K) Expressed in binary: 3-69 Principles of Operation Page register value= (system memory address) shifted right IS bits For example: System memory address= S0,000h= 1000 0000 , 0000 0000 0000b shifted right IS bits= 0000,00l0b= 2d Thus, the page register should be programmed with 2d. To determine the system memory address, the lOP will access with a given page register value: System memory address= (lOP address) - (S0,000h) + (page register or (lOP address) - (5l2K) + (page register * * 40,000h) 256K) For example: Assuming: 1. Page register= 3. 2. lOP addresses memory at Sl,000h. Then system memory will be accessed at address (Sl, 000h - (S0,000h) + (3 * 40,000h) = 1,000h + C0,000h = Cl,000h 1/0 Port Addressing The I/O port addressing space is allocated as illustrated in Figure 3-S. 3-70 Principles of Operation FFFFh----~--------------------------------------; Local I/O System memory page reg. DMA page reg. DMA control Seel See0 See4 See3 See2 eIO select 8000h----~----------------------------------~ System I/O (32K) Any I/O to this address space will go out to the system bus. 0000h----~------------------------------------~ Figure 3-8. Local I/O Map NOTE The local I/O space is not fully decoded. Accessing I/O space other than those described in Table 3-8 is not recommended. Table 3-8. Port (Hez) R/w I/O Port Assignments Description 0000 - 7FFF System I/O ports 8000 - 80FF Reserved for future use CIO (miscellaneous I/O control bits and counters/timers) 8109 8191 R/w R/w Port e data register Port B data register (used for output flags) 3-71 Principles of Operation '!'able 3-8. I/O Port Assignments (Cont.) Port (Hex) R/w 8192 R/w 8193 R/w IOeser iption Port A data register (used for input bits) Control registers for CIO Do not use 8194 - 8l9F SCC2 (first group of asyncbronous ports) 8119 8111 R/w R/w 8112 8113 R/w R/w Channel B control register(s) Channel B data register (channel 4) Channel A control register(s) Channel A data register (channel 5) Do not use 8114 - 8llF seC3 (second group of asynChronous ports) 8129 8121 R/w R/w 8122 8123 R/w R/w Channel B control register(s) Channel B data register (channel 2) Channel A control register(s) Channel A data register (channel 3) Do not use 8124 - 812F SCC4 (third group of asyncbronous ports) 8139 8131 R/w R/w 8132 8133 R/w R/w Channel B control register(s) Channel B data register (channel 9) Channel A control register(s) Channel A data register (channell) 3-72 Principles of Operation 'rable 3-8. Port (Hex) I/O Port Assignments (Cont.) R/w Description IDo not use 8134 - 8l3F SCC" (network and 1st RS-232 ports) 8140 8141 R/w R/w 8142 8143 R/w R/w Channel B control register(s) Channel B data register (channel 8 - asynchronous/ sysnchronous channel with half-duplex DMA support) Channel A control register(s) Channel A data register (network/channel 9) Do not use 8144 - 8l4F SCCI (synchronous and asynchronous ports) 8150 8151 R/w R/w 8152 8153 R/w R/w Channel B control register(s) Channel B data register (channel 6) Channel A control register(s) Channel A data register (channel 7 - asynchronous/ synchronous channel with full-duplex DMA support) Do not use 8054 - 805F DNA (DNA controller) 8160 8161 W R W R Channel 0 - Used for network channel (SCC0-A): Base and current address Current address Base and current word count Current word count 3-73 Principles of Operation ~able Port (Hez) 3-8. I/O Port Assignments (Cont.) R/w Description DNA (DNA controller) (Cont.) W R Channel 1 - Used for halfduplex synchronous channel (SCCD-B) : Base and current address Current address Base and current word count Current word count W R W R Channel 2 - Used for receive side of full-duplex synchronous channel (SCCl-A): Base and current address Current address Base and current word count Current word count W R W R Channel 3 - Used for transmit side of full-duplex channel (SCCl-A) : Base and current address Current address Base and current word count Current word count 8162 W R 8163 8164 8165 8166 8167 8168 8169 816A 8l6B 8l6C 816D 8l6E 816F W R W W W W W R W W DMA Status Registers: Command register Status register Request register Single mask register bit Mode register Clear byte pointer flip flop Master clear Temporary register Clear mask register Write all mask register bits 3-74 Principles of Operation ~able Port (Hex) 3-8. I/O Port Assignments (Cont.) R/w Description Miscellaneous Registers Not used 8176 - 8177 8178 w System memory page register (provides memory addresses A18-A23 during access to system memory). See System Memory Page Register in this section 8179 w DMA memory page register, (provides memory addresses A16-Al9 during DMA to system memory). See DNA Page Register in this section 8l7A - 8l7F Reserved for future use 8186 - FFFF Do not use J DMA Controller The DMA controller is a four-channel device capable of simultaneously managing DMA to/from four separate I/O sources through serial communications controllers (Sees) as follows: • high-speed network on channel A of See6 • RS-232 serial port on channel B of See6 • receive side of the synchronous channel on Seel-A • transmit side of the synchronous channel on Seel-A The local bus and its arbiter are designed so that data transfers on the local bus (between I/O devices and memory that are controlled by the DMA controller) and data transfers on the system bus (initiated by the lOP) can occur simultaneously. 3-75 Principles of Operation This capability is necessary since the lOP may experience significant delays (on the order of milliseconds) before gaining access to the system bus. Thus, DMA transfers on the local bus (as the result of network data or synchronous communications) can continue uninterrupted. To conserve local bus bandwidth and latency, a hidden refresh is performed at the beginning of each DMA cycle. This does not delay any DMA transfer because hiding the refresh within the DMA cycle reduces the likelyhood of lOP-refresh contention. Because of the hardware implementation, the following must be observed: 1. The back of the Advanced Micro Devices 9517 Technical Data Sbeet lists a number of common problems, some of which can be caused by improper software management of the DMA controller. Read the list! 2. The DMA controller operates in the fly-by mode, which means that data is transferred from the peripheral to memory in the same cycle. Thus, it is not possible to do a DMA transfer to just any I/O device. The only devices supported are serial communications controllers SCC9-A, SCC9- B, and SCCI-A as follows: • DMA Channel 9: SCC9-A, the network • DMA Channell: SCC9-B, RS-232 channel 8 • DMA Channel 2: SCCI-A, the receive side of the synchronous port • DMA Channel 3: SCCI-A, the transmit side of the synchronous port 3. Because of restrictions in the hardware implementation, it is not possible to perform memory-tomemory transfers. 4. Because of the time-critical nature of the high-speed network channel, it is recommended that fixed-priority mode be used. 5. The DMA controller should be programmed for the single-cycle transfer mode which transfers only 3-76 Principles of Operation one byte per DMA bus cycle. (Block-transfer mode should NOT be used, since it would totally tie up the local bus during the time the block was being transfer red. ) 6. All DMA request (DREQ) inputs from the I/O devices are active low. The DMA controller must be programmed to accept this polarity. 7. All DMA acknowledge (DMAK) outputs to the I/O devices must be programmed active low. 8. Use normal cycle timing and late write timing. 9. There is no automatic power-up reset to the DMA controller IC. Software is responsible for generating a DMA reset using the control output bit from the counter/input/output (CIO) to reset the DMA controller at power-up and/or initialization. DMA Synch/Refresh Controller The DMA synch/refresh controller PAL (15D) synchronizes the DMA grant (DMAGNT*) signal, the DMA ready line, and the DMA hold request (BRQ) line. This PAL also generates one wait state for most I/O cycles (or more if SCC recovery is necessary when RWAIT* is low). Refresh requests that occur because of a 15 microsecond timer are latched and presented to the local bus arbiter. The beginning of every DMA cycle also generates a refresh request and resets the 15 microsecond refresh timer to allow a hidden refresh cycle to be executed. Refer to ~iming Diagrams at the back of this section for detailed timing diagrams. DMA ReadlWrite Controller The DMA read/write controller PAL (16C) synchronizes the DMA controller I/O read (IORD*), I/O write (IOWR*), memory read (MRD*), and memory write (MWR*) command lines to the 8 MHz system clock. 3-77 Principles of Operation This PAL also generates bus control signals similar to those generated by the local bus controller PAL. Refer to ~iming Diagraas at the back of this section for detailed timing diagrams. DMA Page Register The DMA page register is a four-bit write-only register which provides address bits A16 through A19 during DMA accesses to local memory as illustrated in Figure 3-9. Since the DMA controller only generates 16 bits of address, the DMA page register removes the 64K byte address space restriction and allows the DMA controller to access local memory in 64K byte pages that start on any 64K byte boundary. There is only one page register that functions identically for all four DMA channels. 8l79h DMAPAGE (write st robe) L D0-3 4 , '" 4 bits , 4 J' ~\:9 o Al 6 A C L M E M o A15 DMA controller 1 A0 R 16 y A15 ,....,./---.t .;" A0 A D D R • Figure 3-9. DMA Page Register Block Diagram 3-78 Principles of Operation Serial 1/0 Ports There are a total of 19 serial I/O ports on the communications (SIO) PCB that are supported by five 8539 SCCs. The 8539 serial communications controllers are capable of both synchronous and asynchronous support, . although this design only provides enough RS-232 line drivers and receivers to support two synchronous channels. Each of the controllers has two complete communication channels, including independently programmable baud-rate generators for each channel. Each controller is also capable of generating vectored interrupts to the rap. Refer to the lilog Data Handbook/ Technical Manual for detailed information on the SCCs. The controllers are referenced as described in Table 3-9. ~able Channel 3-9. Communications Controller References IC 9 SCC4-B 1 2 3 4 5 6 7 SCC4-A SCC3-B SCC3-A SCC2-B SCC2-A SCCl-B SCCl-A 8 SCC9-B 9 SCC9-A capability Asynchronous RS-232 (boot channel) Asynchronous RS-232 Asynchronous RS-232 Asynchronous RS-232 Asynchronous RS-232 Asynchronous RS-232 Asynchronous RS-232 Synchronous or asynchronous RS-232 (full duplex DMA) Synchronous or asynchronous RS-232 Asynchronous RS-232 or highspeed network RS-422 3-79 Principles of Operation Each port has the following capabilities: • interrupt driven • baud-rate programmable from 75 to 19,299 baud (other baud rates possible, if desi red): 19,299 9,699 4,899 • • 2,499 2,999 1,299 699 399 159 134.5 119 75 selectable number of stop bits: 1, 1-1/2, or 2 selectable number of bits/character: 5, 6, 7, or 8 • TxD input (transmitted data) • RxD output (received data) • DTR input (e.g., device busy) • DSR output (input buffer full) NOTE CTS, RTS and DCD are NOT supported on channels 9 through 6 or 9. The synchron~us ports support all of the above, plus: • RxC input (synchronous receive clock) • TxC input (synchronous transmit clock) • RTS input (request to send) • CTS output (clear to send) Channel 7 (SCCl-A) has the ability to be full-duplex DMA driven. Channel 9 can be run at 1.4M baud (halfduplex mode only) supported by the highest-priority channel of the DMA controller. 3-89 Principles of Operation It is possible to have all four DMA channels (channel 9 through 3) running simultaneously. For example: 1. 1.4M baud on SCC9-A. 2. Up to 19,299 baud RS-232 (half duplex) on SCC9-B. 3. 9699 baud (full duplex) on SCCI-A. The asynchronous RS-232 I/O ports are implemented with the data terminal ready (DTR) and full data set ready (DSR) handshake lines as described in Table 3-19. Input and output (I/O) are referenced to the communications (SIO) PCB. ~able 3-11. AsynChronous-Channel Handshake Lines RS-232 Signal Transmitted Data Received Data Data Terminal Ready Data Set Ready Signal Ground I/O I 0 I 0 SCC IC Signal RaDle RxD TxD CTS RTS (receive data) (transmit data) (clear to send) (request to send) The serial communications controller CTS and RTS (instead of DCD and DTR) signals are used as the handshaking lines for two reasons: 1. Although it is desirable to make all serial channels consistent in their use of control signals, DTR is used for the second DMA request line for the receive side of SCCI-A. This eliminates the possibility of using DTR to control the RS-232 DSR line. 2. Using the CTS and RTS lines permits the software to take advantage of the auto-enables feature of the SCC. Handshaking is the same for the synchronous channels with the addition of several more signals as described in Table 3-11. Input and output (I/O) are referenced to the communications (SIO) PCB. 3-81 Principles of Operation IJ'able 3-11. Syncbronous-Cbannel Handsbake Lines RS-232 Signal Transmitted Data Received Data Data Terminal Ready Data Set Ready Sync Rx Clock Sync Tx Clock Request To Send Clear To Send Signal Ground I/O I o I o I I I .0 sec Ie Signal Bame RxD (receive data) TxD (transmit data) CTS (clear to send) RTS ( r eq ue s t to se nd) RTxC (external receiver clock) TRxC (external transmitter clock) DCD (data carrier detect) Prov ided by the CIO Network Channel Channel 9 (which uses SCCD-A) works the same as any other asynchronous channel when the RS-422 control flag in the CIO is cleared. Whenever the RS-422 flag is set, the RS-232 line receiver is disabled and the RS-422 line receiver for RxD of that channel is enabled. In addition, software selects the external transmit and receive clocks to the SCC as the baud-rate source, and sets the network clock enable (NETCLKEN*) bit (from the CIO) low to enable the 1.4 MHz oscillator, which is used as the transmit clock source. The SCC's DTR output requests that the network data and clock line drivers be enabled. When the SCC DTR bit is high (DTR* pin is low) and the carrier sense circuit (a 5 microsecond timer) has determined that there is no carrier presently on the network, the drivers are automatically enabled (regardless of the state of the RS-422 flag from the CIO). Therefore, software ensures that the SCC's DTR bit is low, except during network transmit. When the network channel line drivers are driving the network, the DCD* input will go high (DCD bit in the register will go to D). Software uses this bit to determine when it has gained access to the network. 3-82 Principles of Operation Setting the DTR bit in the register low will cause the line drivers to disable immediately, which will also cause the DeD* pin to go low and possibly generate an interrupt if external/status interrupts were enabled. No attempt is made to hardware-disable the RS-232 DTR, DSR, and received data lines (eTS, RTS, and TxD at the See). The network port must NOT be plugged into an RS-232 and RS-422 device at the same time. see Recovery The see recovery PAL (3e) monitors the I/O accesses to See9 and Seel that occur because of lOP or DMA cycles. This PAL ensures that successive accesses to a given see do not violate the see recovery requirement of 1.3 microseconds. After each valid see access, a counter is reset. A later access to the same see is prohibited by this PAL until the see's associated counter has counted for 1.3 microseconds. Refer to Timing Diagrams at the back of this section for detailed timing diagrams. Programming Precautions The following precautions must be considered when programming the communications (SIO) PCB: 1. The sees and eIO have a recovery requirement which means that successive selects to a given Ie must not occur within 1.25 microseconds of each other (this does not apply to interrupt acknowledge). To meet this requirement, hard ware has been added to See9 and Seel (only) to prevent violating the recovery specification because conditions can arise (especially with DMA) that software cannot guard against. However, for the remaining sees and the eIO, it is the responsibility of software to insure the recovery specification is met. Thus, it is NOT possible to do the following since it would violate the recovery specification: 3-83 Principles of Operation MOV: OUT OUT DX,AL,DX or IN AL,DX or IN MOV! OUT Nap Nap OUT DX, AL,DX 7Setup port no. AL,DX 7Do I/O AL, DX 7 twice ; This may not work either! AL,DX This will work properly: MOV: OUT PUSH POP OUT 2. DX, AL,DX AX ; Make sure there is a bus cycle AX ; between the output AL,DX ; instructions All I/O ICs are on the local D9-7·data bus. Unlike normal 8986 microprocessor convention, A9 DOES participate in the port selection process. (Normally all I/O would be done to all even or all odd addresses.) Byte-swap logic on the communications (SIO) PCB takes care of this transparently. MINOR SOFTWARE PRECAUTION: any. I/O reads or writes must be BYTE operations using AL. For example: MOV: OUT DX, ;Setup port number AL,DX 7Send out data The following will produce unpredictable resul ts: MOV: OUT DX, AX,DX 7 A l6-bit data transfer So will this: MOV: OUT DX, AH,DX ;Output the high byte only 3-84 Principles of Operation 3. Although it is documented in the Zilog see Technical Manual, be sure to leave the internal byte pointers in such a state that the ICs internal interrupt logic is not left disabled. 4. Do not use the published baud-rate generator divisors. Those numbers apply only when a 4 MHz! clock is being used. You must recal cuI ate all divisors based upon a 6 MHz clock. (This will produce a 2.4%, error at 19,2BB baud.) Counter/Input/Output The 8536 CIO is used for general-purpose counter(s)/timer(s) and also provides bit set/test functions. The CIa acts as an interrupt controller for miscellaneous inputs, such as, system channel attention, RAM parity error flags (one for local RAM, one for system RAM), system bus timeout error, DMA end-of-process interrupt, and three general-purpose inputs (jumper selectable) for software-determined use. One of the general-purpose inputs is used to identify the PCB that contains the boot channel for computer systems that have more than one communications (SIO) PCB. Refer to Table 3-12 for CIa port descriptions. There are three internal counter/timers that can generate vectored interrupts. Two of these are unimplemented and are reserved for any uses that software may determine (implementing timeouts, etc.). These counter/timers are only accessible through software and can be used individually or cascaded. The third counter/timer is accessible on I/O signal lines PCB-PC3 (currently undefined, but reserved for future use by hardware). Refer to the Zilog Technical Reference Manual for detailed information on the 8536 CIa operation. 3-85 Principles of Operation Table 3-12. Bit I SigDal _ Name CIO Port Descriptions pulse/ Level Description Port A (inpots) PA9 BT1MEOUT* pulse A system bus timeout error has occurred PAl CHANATTN* pulse Channel attention from system bus PA2 DMAEOP* pulse DMA end-of-process interrupt PA3 LOCPERR* pulse A parity error has occurred in local RAM PA4 SYSERR* pulse Either a system RAM parity error or a system bus timeout error has occurred while accessing the system bus PAS LOOPERR* level Jumper installed between pins 3 and 4 of connector El (logic 9) indicates that the 1PL PROM firmware should enter a stand-alone mode PA6 PR1MARY* level Jumper installed between pins land 2 of connector El (logic 9) indicates that this is the master (9) communications (S10) PCB level Not used PA7 3-86. Principles of Operation ~able Bit 3-12. Signal Name CIO Port Descriptions (Cont.) pulse/ Description Level Port B (outputs) PB0 NMICLR level A logic 1 will clear the parity error NMI. Must be set to 0 to allow more parity errors (and NMI) to be detected PBl SYSINT 0-1-0 Causes a system interrupt to be ated. Software drive this line o to 1 to 0 PB2 DMARESET 0-1-0 Causes a hardware reset of the DMA controller. Software must drive this line from logic 0 to 1 to bus genermust to logic o PB3 RS422A level A logic 1 causes SCC0-A to disable the RS-232 RxD receiver and enable the RS-422 RxD receiver PB4 NETCLKEN* level A logic 0 enables the 1.4 MHz oscillator for the network transmit clock PBS CSTA* level A logic 0 asserts the RS232 CTS output for the SCCl-A channel. PB6 CSTB* level A logic 0 asserts the RS232 CTS output for the SCC0-B channel. PB7 REDLED level A logic 1 turns on the red LED. 3-87 Principles of Opera#on Table 3-12. Bit Signal Name CIO Port Descriptions (Cont.) pulse/ Level Description Port C (I/O or counter/timer) PC0PC3 (reserved for future use) elo Programming Notes PA0 - BTIMEOUT* This CIO input must be programmed to "catch" a I-to0-going pulse, and generate a vectored interrupt. If true, it indicates that an attempt was made to access some device (memory or I/O) on the system bus that did not respond within 100 milliseconds. This condition may be caused by attempting to access a nonexistent device/PCB or attempting to access a nonfunctional dev ice/PCB. Normally this error should not occur since the CPU PCB also monitors excessively long bus transactions and asserts the bus error signal after about 10 microseconds. PAl - CHANATTN* This CIO input must be programmed to catch a l-to-0going pulse and generate a vectored interrupt. If true, it indicates that some device on the system bus has generated a channel attention signal intended for the communications (SIO) PCB. (Multiple communications (SIO) PCBs in the system each have their own unique channel attention signal.) 3-88 Principles of Operation PA2 - DMAEOP* This CIO input must be programmed to catch a 1~to-0going pulse and generate a vectored interrupt. If true, it indicates that the end-of-process (EOP) signal from the DMA controller has gone true. Since there is only one EOP output from the DMA controller, software must further test the condition of the DMA status registers to determine which DMA channel caused the interrupt. PA3 - LOCPERR* This CIO input must be programmed to catch a l-to-0going pulse and should not generate a vectored interrupt. When this signal is true, it indicates that a parity error has been detected while accessing local RAM and an NMI has been generated to the 8086 microprocessor. The CIO input should be used only as a status bit to determine the source of the NMI. Once the source of the NMI is determined, the NMICLR signal must be driven false to clear the NMI latch. PA4 - SYSERR* This CIO input must be programmed to catch a l-to-0going pulse. It should not generate a vectored interrupt since SYSERR* also generates an NMI to the 8086 microprocessor. If this signal is true, it indicates that a bus error has occurred while attempting to access the system bus. A bus error can occur: 1. If a system memory parity error is detected while accessing system memory. 2. The host CPU has determined that a system bus timeout has occurred (the bus transaction has not been acknowledged within about 10 microseconds). This input should be used only as a status bit to determine the source of the NMI. Once the source of 3-89 Principles of Operation the NMI is determined, the NMICLR signal must be driven true, then false to clear the NMI latch. PAS and PA6 (General-Purpose Inputs) These CIO inputs are simple status inputs which sense the state of a three-position jumper connector. These inputs tate. Input for hardware should enter indicate the system. may be used for any use software may dicPAS is used during power-up initialization debug to indicate that the firmware should a stand-alone mode. Input PA6 is used to master (9) communications (510) PCB in the Interrupt Priorities Interrupt priorities are organized in a daisy-chain as described in Table 3-13. ~ab1e Priority (BigbestLowest) 3-13. Interrupt Daisy Chain Ie Description 1 CIO Counter/timer 3 Port Port A (inputs) Counter/timer 2 Port B (outputs) Counter/timer 1 2 SCC9 Channel A (the network channel, or RS-232 channel 9) Rx Tx External/status Channel B (the half-duplex DMA-driven synchronous channel) - (channel 8) 3-99 Principles of Operation ~able priority (BigbestLowest) 3-13. Interrupt Daisy Chainr (Cont.) IC Description 3 SCC1 Channel A (the full-duplex DMA-driven synchronous channel) - (channel 7) Channel B - (channel 6) 4 SCC2 Channel A (channel 5) Channel B (channel 4) 5 SCC3 Channel A (channel 3) Channel B (channel 2) 6 SCC4 Channel A (channell) Channel B (channel 0 - boot channel) Each of the ICs listed in Table 3-13 can be programmed to interrupt with an eight-bit vector unique to that rc. All of the rcs in Table 3-13 have a status-affects-vector capability which allows the specific cause of the interrupt to participate in generating a unique vector. Refer to the lilog and Advanced Micro Devices data books and technical manuals for specific capabilities. The 8086 microprocessor allows up to 256 unique interrupt vectors. The use of certain vectors has been predefined by the microprocessor as follows: vector o 1 2 3 4 Use Divide by zero error Single-step interrupt Nonmaskable interrupt One-byte interrupt instruction Overflow Intel further reserves a block of 27 interrupt vectors (5 through 31d) for its use. The remaining vectors are available for any use software may dictate. vector 255 3-91 Principles of Operation (0FFh) is reserved as a general-purpose hardware error trap, since a hardware failure in the interrupt vectorgenerating mechanism generally causes this vector. Jumper Selectable Options Table 3-14 describes the jumper selectable options for the communications (SIO) PCB. Refer to Appendix A for specific jumpering information. Table 3-14. Connector nesignation Jumper Descriptions Description El General-purpose input port. Jumpered only on the master (0) communications PCB. Not jumpered on any other communications PCBs installed in the 1086/2086 system. E2 Selects the size of PROMs installed (2732, 2764, or 27128). 2764 PROMs are normally installed. E3 AACK. Enables the advanced acknowledge (AACK) signal from the system memory (reduces wait states). Also used for local reset (testing only). Normally jumpered for enabling AACK. E4 BPRN (Bus Priority Input). Used to determine the arbitration priority when the communications (SIO) PCB(s) wish to access the system bus. ES BPRO (Bus Priority Output). See BPRN. E6 CHANATTN. Selects the port number that the communications (SIO) PCB responds to for channel attention signals generated on the system bus. 3-92 Principles of Operation Table 3-14. Connector Designation Jumper Descriptions (Cont.) Descr iption E7 INT. Selects the bus interrupt vector level that the communications (SID) PCB generates. E8 LARGE*. Must be jumpered if 256K dynamic RAMs are installed. 1/0 Connectors The communications (SID) PCB has IB rear-panel serial I/O connectors (port B through 9) supported by five serial communications controller (SCC) ICs. All channels use a 9-pin, D-type, subminiature connector (DE-9P male plug). Table 3~15 describes the connector/controller conf iguration. Table 3-15. Connector/Controller Configuration Connector Designation Serial Olannel PIB B PII Pl2 Pl3 Pl4 PIS Pl6 Pl7 I 7 Pl8 8 Pl9 9 2 3 4 S 6 Description Asynchronous RS-232 (Boot Channel) Asynchronous RS-232 Asynchronous RS-232 Asynchronous RS-232 Asynchronous RS-232 Asynchronous RS-232 Asynchronous RS-232 Synchronous or Asynchronous RS-232 (with full-duplex DMA support) Synchronous or Asynchronous RS-232 Asynchronous RS-232 or HighSpeed Network RS-422 3-93 Principles of Operation Depending upon how the Channel is configured, the connector pins have slightly different functions as described in Table 3~16. I (input) and 0 (output) are referenced to the communications (SIO) PCB. 'rable 3-16. Pin I/O Connector Pin Assignments Signal Name Pl. !hrougb Pl6-Asyncbronous Olannel 1 2 3 4 5 6 7 8 9 I o o I o (Do Not Use) Transmitted Data Received Data Data set Ready Signal Ground Data Terminal Ready Pullup to +12V Not Used Not Used Pl7 or Pl8-Syncbronous Channel 1 2 3 4 5 6 7 8 9 I I o o I o I I Synchronous Receive Clock Transmitted Data Received Data Data Set Ready Signal Ground Data Terminal Ready Clear to Send Request to Send Synchronous Transmit Clock Pl9-Network Channel 1 2 3 4 5 6 7 8 9 I/O I o o I I/O I/O I/O ANET Clock + RS-232 Transmitted Data RS-232 Received Data RS-232 Data Set Ready Signal Ground RS-232 Data Terminal Ready ANET Data + ANET Data ANET Clock - 3-94 Principles of Operation Timing Diagrams The major communications PCB timing diagrams are shown in Figure 3-1~. Sample Period 100.0 nS/div 10.00 nS/clk 870.0 nS :x to rh~Jnification l'1agn if,,) f,b 0 u t Cun;or' t'l(1ves (I jib IIC - Local Arbiter PAL (Local Bus Cycle - I/O Read) Sarnp 1e Pet-· i od .. -.--.-r ' 100.0 nS/div 10.00 nS/clk 250.0 nS >< to f'lagnification f'laqn i fq About Cu;~sor-'- ~'lo\ies [ J J >< 0 o LrlJL__• JILJ~LJLJl ---___J-. 1_• •-------- ,.M.· -i---'--:----'---i--'-----'------'----'- J Idm. 1111" llC Local Arbiter PAL (Refresh Grant After lOP Cycle) Figure 3-18. Communications PCB Timing Diagrams 3-95 Principles of Operation Sample Period Magnification Magnify About Cursor f'loves [ t ] -, -M 100.0 nS/div 10.00 nS/clk 250.0 nS x to J L r.. . . 0 o . ,. :. I :I "","II·IID"_·:-:-_:-~---Ir'''--:-·~·--: ---.- . L: 1M,,: ........ ; .".,.,.:-i-:-:. .'"'"' ..,.,., ...,-, ..-:-,.-.~.-:-c-:.. -.. -,, ... . . . . . • . . -:-7. ; -:-:. . -:-:-. r .. llC LOcal Arbiter PAL (DMA-Induced Refresh Cycle) Sample Period Magnification Magnify About Cursor f'loves 250.0 nS/div 10.00 nS/clk 1. 750 wS x to [ t ] WI (I o rLJlJlJUUULJL - i -.J llC LOCAL ARBITER PAL (Simultaneous DNA, Refresh, and System Bus Cycle) Figure 3-18. Communications PCB Timing Diagrams (Cont. ) 3-96 Principles of Operation ~;amp 1e Pt~r' i ad !'lagn j f i CO.t ion 11aqn i ftJ AbOl.lt ell ~~, (I t- [ J ] w· 100.0 nS/div 10.00 nS/clk 880.0 nS :< to "'110 ve 2; · n r-'l----.ln -. 1--, . -.T1- Ct o >< rLSL- rLJLJl' . '.-'- L_-,_· I 1-• • I: L....;-'_ - - - ; - ' -_ _ L!+======= l '---'- IiIllplD ~ ~R411".--__ -.-__::-.-.~----~~L~:_~ 15C ~farnp : __ Local Bus Controller PAL (PROII - Read) 1e F)et .. i od 100.0 nS/div 10.00 nS/clk 620.0 nS x to a Magnification Maqnify About Cu~sor·Moves [ J ] 0 >( - -J·-L-c~LJ-ULSLrL-.J~JLJ :r-- _ _-+-_--'--C..----.---~ __. - ; II I' ---'-----1 L• ' • : ! J ~ ' L---'· l, II l__•___ . ~.' !I- 15C - Local Bus Controller PAL (Local RAM - Read) Figure 3-11. Communications PCB Timing Diagrams (Cont. ) 3-97 Principles of Operation Sample Period Magnification 11agn i fy About Cursor Moves 100.0 nS/div 10.00 nS/clk 630.0 nS x to [ l ] WI 0 o x I • II!!. : I· '1114• •;-:-=:=:;;...1 .,. l5C - Local Bus Controller PAL (Local RAM - Write) Samp I e Per· i od Magn i f i cati on Magnify About Cursor Moves ( ! ] 100.0 nS/div 10.00 nS/c!k 870.0 nS >( to 0 we lSC Figure 3-11. Local Bus Controller PAL (Local I/O - Read) Communications PCB Timing Diagrams (Cont. ) 3-98 Principles of Operation Samp I e Per' i od Magnification Maqnif~ About 100.0 nS/div 10.00 nS/clk 750.0 nS x to Cu~sor'Moves [ 1 ] x 0 0 -1-_JL~~J~__rLJ~l~.-IL .·":--i'' L - . J ~ r m---U II I' 1M' l5C Local Bus Controller PAL (Local I/O - Write) Sa.rnp I e Per i od Magnification i'1agnif',l About 250.0 nS/div 10.00 nS/clk 1.750 115 x to Cursor i1o\/f.?s [ J ] x ""U1JIJ1J1JlJUlJlJJ tt 0 o h __ ~ li all-~i J1 : ,---I-,------,-,I I.------:----~l I' IIUDl •'---1 -+---,-----,- t l II , , ,I ~_:""_~_'~======~==:j=:==~:::;-~Jr---+_~_~ Igjll' '---~-----'-' , [14 ----_., ~":-:•.."..-:-:' ••••• .. I . . . . . . . , .• l5C - Local Bus Controller PAL (Interrupt Acknowledge Cycle) Figure 3-18. Communications PCB Timing Diagrams (Cont.) 3-99 Principles of Operation Sample Period ~lagn i f i cat jon Magnify About Cursor ~Joves ..- [ ! ] ".p 100.0 nS/div 10.86 nS/clk 880.0 nS x to 0 x o Sl u S-! '111I14A: lr I I i j: II· 1;U1 - J U ........L lee - Wait-State Generator PAL (PROM - Two Wait States) Samp le Per lod Magnification Magnify About Cursor Moves [ ! ] 100.0 nS/dlv 10.00 nS/clk 620.0 nS x to 0 x IWI - ,M 111111_1:--1,--7---'--":'~11 : IUd 1 i : :---~========~~~~~ .................. ,J : :U .. ~,..,.,....,.....,.... ,. ,.:...-:-:-:. IIC - Wait-State Generator PAL (DMA Chip Select - One Wait state) Figure 3-11. Communications PCB Timing Diagrams (Cont. ) 3-HHJ Principles of Operation Sample Period Magnification l'lagn i fy About .., Cur~30r ~lo'v'es [ J ] - 250.0 nS/div 10.00 nS/elk 1. 500 IJS )< to x 1 L 0 0 Jl J"-Ul"Jl1iUnn n n n n n n nrunIU" nlLJlJliIUU n rL L -..lULJUUULJI_ _ ~_.--H-L ____' ,'. III··~__-"-u-l . . . ·1 1 ': :1 1 .,-. .r 1·1 - - - . - - - - ' t - -..-~.-~======~==~--~--~'i·~==~===== t• •, .: .: . . . I-.-al--·~~.L~··~--~'~--~--~~':~I :--r' IMUD - - :-~ I'~n ·:1 __~~ -U...-----:-~ Ir-:-l' u: r: :r ~. --"-' 1,: 11.....-;c,-.-.~-_ " . ". 1. . . llC - Wait-State Generator PAL (SCC I/O Cycle With Recovery) Sample Period f1agnificat ion l'1agnify About Cursol" l'loves [ 1 ] )( 250.0 nS/div 10.00 nS/elk 2.340 IJS )( to 0 o "'.' :Jl'JJUL.J· n n flJl·JUD. . :. . ,, ~ -Lt,uLJL.JLJlilSLJLJLJt '''''''''IIA· ..... M IIIIIM ~~ ;1 . 1111-·: 11,1111 I ~ .. ~ I I : ~ I l5D - DNA Refresh PAL (DNA Request/Grant Synchronization) Figure 3-11. Communications PCB Timing Diagrams (Cont. ) 3-101 Principles of Operation Sample Period Magnification Magnify About Cursor Moves 250.0 nS/div 10.00 nS/clk 1.750 pS x to [I. ] 0 o ee n n n n n: nJ1JUUUL: • • ~ ~ ~~ , ~ ~ ~ ~ 111,,1 j • " • , nst I..i ~~~~~-~-.,I I -I ~! •••. ! ..---t---:--:---:-~~ -'1" 1IIIl!IIM--:..--+---'---"-----:---.-:.-· I IMI' 'i .; •• . ••••• I • 16C - DMA Read/Write PAL (DMA I/O Read/Memory Write Cycle) Sample Period Magnification Magnify About Cursor Moves [ ! ] 250.0 nS/div 10.00 nS/clk 1 . 750 [is x too o x nJLn_ I" ·'JLJl· ,.1' .!I . . . , . . "I -p' J 'M 16C - DMA Read/Write PAL (DMA I/O Read/I/O Write Cycle) Figure 3-18. Communications PCB Timing Diagrams (Cont. ) 3-102 Principles of Operation Sample Period Magnification Magnify About 500.0 nS/div 10.00 nS/clk 1. 500 fjS x to Cur"sor Moves [ ! ] .- 0 x lliUUUlllJ L Ill" ,.11 3C - Recovery PAL (Three Consecutive I/O Reads - Second Read Required Recovery) Figure 3-18. Communications PCB Timing Diagrams (Cont. ) 3-193 Principles of Operation (BLANK) 3-104 Principles of Operation File Processor PCB The function of the file processor is to manage the data transfer between system memory and the tape, floppy, printer, hard disk, and small computer system interface (SCSI) peripheral devices. Refer to the Schematic Diagrams supplement to this manual for the block and schematic diagrams of the file processor PCB. NOTE The -001 version of the file processor PCB DOES NOT support SCSI operation. The -002 version of the file processor PCB includes SCSI. System Interface The file processor uses 16 of the available 32 data lines on the system bus. The file processor has the highest system bus priority (0) and uses bus request line 0 for bus requests and interrupt line 0 to interrupt the host 80286 microprocessor. The 89286 uses channel attention (address 099Eh) to interrupt the file processor. The file processor contains an Intel 8986 microprocessor and a Hitachi 68450 direct-memory access (OMA) controller that can read or write anywhere in system memory with 24-bit addressing. The 8986 uses a 6-bit system memory page register to specify the upper address bits when accessing system memory. NOTE The file processor PCB has the highest system bus priority. Thus, the file processor 8986 system-bus accesses should be kept to a minimum to allow sufficient bandwidth for the PCBs with lower bus priority. The OMA controller allows concurrent transfer of data for tape, floppy, printer, and either hard disk or 3-105 Principles of Operation SCSI. The maximum transfer rates for tape, floppy, printer, and hard disk/SCSI are 9~K, 32K, 5~K, and 1.5M bytes per second respectively. System Bus Control Logic There are two system bus control PALs (160 and 18B) that perform system bus interface logic functions. The system bus controller PAL 1 (160) generates memory read or write, high byte enable (HBEN), high word enable (HWEN), and address (A~9) signals. The combination of HWEN, HBEN, and A9~ determines the data transfer widths. Refer to System Bus Interface at the front of this chapter for additional details. The system bus controller PAL 2 (18B) handles the bus exchange control and provides data steering to the system bus by enabling the appropriate transceivers. Refer to Timing Diagrams at the back of this section for 8986 read from/write to system memory timing. Also refer to Timing Diagrams for data transfer between system memory and tape, floppy, printer controllers, or ping-pong buffer timing. Microprocessor The file processor 8986 microprocessor runs at 8 MHzl in Minimum Mode and manages the printer and SCSI controllers on the file processor PCB, and also the floppy, tape, and hard disk controllers on the controller PCB. The 8986 runs continuously except when the OMA controller is using system memory. The 8986 executes out of PROM for file processor confidence tests and booting, out of local RAM for normal processing, and out of system memory to receive file processor commands and to report status. Refer to Timing Diagrams at the back of this section for 8986 read/write timing. 3-1~6 Principles of Operation Interrupts The 8~86 responds to nonmaskable interrupts (NMIs) such as, power failure, system memory error, and local memory parity error; and lower priority maskable interrupts such as the host 8~286, DMA controller, real-time clock, and peripheral controllers. Memory Organization Both the DMA controller and the 8~86 microprocessor use memory, but only one can address memory at a time. In case of ties between the 8~ 86 and DMA controller, the DMA controller has priority over the 8~86. Both the DMA controller and the 8~86 have byte and word addressing capability. The 8~86 can address PROM, RAM, and system memory while the DMA controller can only address the system memory. The 8~86 has 2~ address lines. The two most significant bits select which memory type the 8~86 will access: bit code ~~ will access local RAM, bit code l~ will access system memory, and bit code 11 will access PROM (bit code ~l is not used). The memory space of the 8~86 is organized as shown in Figure 3-11. The addresses between 4~~~~h and 8~~~~h are mapped into system memory and are movable by changing a value stored in the system memory page register. Figure 3-12 shows the 8986 system memory address logic and the function of the system memory page register. 3-l~7 Principles of Operation FFFFFh PROM (8K to 16K) FEfiHH~h Not Used C0000h Unaddressab1e 80000h System Memory ( 256K) 00000h: Offset by the system memory page register. 40000h Not Used 08000h Local RAM (32K to 128K) Figure 3-11. 8886 Memory Address Map l 9600h (W} _ _ _ _----, UPADDRLD S 6 FPD0- 5 ---7/'----l~ y S T System Memory Page Regis. E M Must be set to bit code 10 to access system memory. A19 A18 A17 8086 18 t A17 1----+/-----.+ I A0 A0 M E M o R y A D D R Figure 3-12. 8886 System Memory Addressing 3-108 Principles of Operation Memory Options In the basic system, the address space for the PROM memory is 8K bytes and 32K bytes for the RAM memory. The PROM memory in the basic system is composed of two 4K x 8 bit PROMs and the local RAM is composed of four 16K x 4 bit RAMs. The PROM memory is expandable to 16K bytes with two 8K x 8 bit PROMs and the RAM memory is expandable to 128K bytes with four 64K x 4 bit RAMs. RAM Control Logic The RAM control logic is contained in the RAM controller PAL (24B) which performs the following functions: • generates row address strobe (RAS) and column address strobe (CAS) signals for the RAM • arbitrates the local memory access and refresh cycles • inserts wait states to the • decodes the upper two address bits of the 8~86 microprocessor for access to either the local RAM or system memory 8~86 microprocessor Refer to Timing Diagrams at the back of this section for 8~86 read from/write to local memory timing. Parity Errors Local RAM parity errors cause an NMI at the 8886 microprocessor. System memory parity error and system memory access out-of-bounds error also cause an NMI at the 8~86. Common Control and Status The common control and status ports are the file processor command register, disk mode register, and file processor status port. Refer to Tables 3-17 and 3-189 Principles of Operation 3-18 for the control and status port assignments and control and status bit assignments. ~able 3~l7. Control and Status Port Assignments Address (Hex) R/w Signal Assignment 0608 W CMDLD* File processor command register 060C 0700 W DSKLD* FPSTATUS* Disk mode register File processor status port ~able Bits R 3-18. Control and Status Bit Assignments Signal Punction Pile Processor Command Register FPD00FPD07 FPD08 Not used CLRST* FPD09 Clears controller PCB. Duration at least 25 microseconds Not used FPD10 INT286 Interrupts 80286 on interrupt line 0 FPDll ENNMI Enables nonmaskable interrupt (NMI) to 8086 FPD12 BURSTEN Enables DMA controller burst logic , FPD13 MBLDCR System bus lock (debugging aid) 3-110 Principles of Operation Yable 3-18. Control and Status Bit Assignments (Cont.) Bits Signal Function FPD14 INPUT PRIME* Causes printer to be prepared for operation FPD15 PENABLE Enables data to be transferred from printer controller to printer Disk Mode Register FPDlH~ Not used FPDe7 FPDeS MBREAD I System bus read mode. Sets mode for information to flow from system bus to file processor FPDe9 SCSIMD SCSI mode; connects SCSI controller to ping-pong buffer; when low, connects hard disk controller to ping-pong buffer FPDle INITBUF* Initializes ping-pong buffer FPDll FPD12 BUFMDl BUFMDe F.E.1U.2. e e 1 1 UlUl e 1 " 1 BYtie I. S iz.~ 2K bytes lK bytes 1.5K bytes 512 bytes FPD13 SCS ICTLRST* Resets SCSI controller; no minimum pulse duration FPD14 SCS IBUSRST* Resets devices on SCSI bus; duration at least 25 microseconds FPD15 Not used 3-111 Principles of Operation ~able 3-18. Bits Control and status Bit Assignments (Cont.) Signal Function File Processor Status Port FPD99FPD97 Not used FPD98 PWRFAIL power-failure interrupt occurred FPD99 MEMERR Memory parity-error or memory address out-ofbounds interrupt occurred FPDl9 PERR Local RAM parity-error interrupt occurred FPDII SCSIRST External reset on SCSI bus occurred FPDl2 MBOONE* System bus data transfer done FPDl3 SCSIAVAIL SCSI controller present on file processor PCB FPD14,15 Grounded Interrupt Logic The interrupts used by the file processor are divided into two classes: nonmaskable and maskable. Nonmaskable Interrupts. At initialization time, a reset causes the ENNMI signal (bit 11 at the file processor command register) to be low, which blocks the NMI. After initialization, the ENNMI signal goes high to allow normal operation. When a nonmaskable interrupt occurs, the 8986 samples the file processor status port to determine the type of NMI. 3-112 Principles of Operation Then the 8986 takes appropriate action and, if possible, clears the error conditions by generating an ERRCLR signal with I/O write address 9696h. Table 3-19 lists the nonmaskable interrupts. ~able 3-19. Ronmaskable Interrupts Type Signal Description Power fail ure PWRFAIL Power supply reports marginal or no power; causes 8986 to hal t processing at earliest opportunity. System memory MEMERR System memory reports parity error or circuit on CPU PCB reports system memory out-of-bounds error. File processor local RAM parity error PERR File processor reports local RAM pa r i ty error. Maskable Interrupts. The maskable interrupts are handled by programmable interrupt controller 8259A operating in the edge mode. Table 3-29 lists the interrupt controller port assignments and Table 3-21 lists the maskable interrupts. Refer to the Intel iii crosystems Components Handbook for th e 8259 A bi t assignments and programming information. 3-113 Principles of Operation Yable 3-21. Interrupt Controller Port Assignments Address (Hex) Mode riJ5riJriJ riJ5riJriJ avC3 (RR=l,RIS=riJ) avC3 (RR=l, RIS=l) R riJ5riJ2 W riJ5riJ2 R priority 1 I Descr Iption Ian, 1m2, 1m3 Interrupt request register (IRR) In-service request (ISR) 1m2, 1m3, lCW4 , DCWl Interrupt mask request (IMR) W R riJ5riJriJ Table 3-21. I R/w Maskable Interrupts I Type Signal Hard disk controller interrupt DINT Asserted by hard disk controller WD2riJ10 on completion of a command; remains high until status register is read or a new command is written into the WD2010 command register HD6845riJ DMA interrupt DMAINT Indicates termination of channel operation for one of the four channels. Refer to Hitachi Microcomputer Data Book for additional information 3-114 Descr iption Principles of Operation ~able Priority 3-21. Maskable Interrupts (Cont.) I Type Signal Description 2 SCSI controller interrupt SCSINT Interrupt for SCSI bus conditions that requi re service. Refer to National cash Register NCR 5385 SCS I Protocol Controller Data Sheet for additional information 3 Tape controller interrupt TINT Indicates tape ready or tape exception condition. Refer to Archive QIC-12 1/4-Incb cartridge Tape Drive Interface Standard for additional information 4 Timer ra interrupt TMRra* Real-time interrupt. Refer to Intel Micros¥stem Components Handbook for additional 8254 (mode 2) information 5 8ra286 microprocessor interrupt 286INT Attention interrupt (rararaEh) to file processor PCB 3-115 Principles of Operation ~able Priority 6 7 3-21. I Type Floppy controller interrupt Maskable Interrupts (Cont.) Signal I Description FINT Indicates floppy disk controller needs serivce. Refer to BEC PD765 Data Sbeet for additional information o Grounded Timer Timer 8254 contains three programmable timers (0, 1, and 2). The addresses of timers 0,1, and 2 are 400h, 402h, and 404h respectively. (Refer to the Intel lIicrosystem COJDponents Handbook for the 8254 programming details.) Timer 0 is a real-time clock that decrements each microsecond. Timer 0 should be used in mode 0 or 3 only. When timer 0 reaches its limit, it interrupts programmable interrupt controller 8259A-2 (see Table 3-22) • Timer 1 limits the number of consecutive DMA accesses to the system bus when it is operating in the burst mode and decrements each time the file processor is granted a bus cycle until the timer's limit is reached (called burst-on time). Then timer 1 switches control to timer 2. Timer 1 should be programmed in mode 2 only. Timer 2 determines how long the file processor DMA remains off the system bus when operating in the burst mode and decrements during the burst-off time until the timer's limit is reached. Then timer 2 switches control back to timer 1. Timer 2 should be programmed in mode 2 only. 3-116 Principles of Operation Burst Logic The burst logic limits the use of the system bus by the file processor, since the file processor could lock out the lower priority PCBs. When the burst enable (BURSTEN) signal (bit 12 from the file processor command register) is low, the file processor operates normally. When BURSTEN is high, the file processor accesses system memory in bursts. The burst logic is automatically turned off at reset. The burst logic uses the two timers located in the 8254 timer. Timer 1 is a burst-on timer that regulates the number of system memory cycles, stops when the timer limit is reached, and then passes control to timer 2. Timer 2 is a burst-off timer that decrements each microsecond until its limit is reached, and then passes control back to timer 1. The address of timer 1 and 2 is 492h and 494h respectively. (Refer to the Intel lIicrosystem Components Handbook for the 8254 programming details.) DMA Controller The DMA controller is a four-channel, 8 MHz, Hitachi HD68459-8 integrated circuit that operates in single-addressing mode (data is transferred around rather than through the DMA controller). The channel assign ments beginning with the highest priority are: Channel 9 = tape, channel 1 = floppy disk, channel 2 = printer, and channel 3 = hard disk/SCSI. The DMA controller performs byte transfers on channels 9 through 2 with byte steering to the upper or lower byte position accomplished on the fly. The DMA controller performs word transfers on channel 3 in bursts governed by the burst logic. Table 3-22 lists the DMA controller port assignments for the internal registers. Refer to the Hitacbi Microcomputer Data Book for register bit assignments and additional programming information. Refer to Timing Diagrams in the back of this section for data transfer between system memory and tape, floppy, printer, and hard disk controllers timing. 3-117 Principles of Operation Also, refer to Timing Diagrams for BBB6 read from/write to DMA controller timing. ~able Ch " 3-22. Address (Hex) Ch 1 Ch 2 DMA Controller Port AssigDJDents Ch 3 I R/W Registers "2"" "2U "2"4 (1'2"5 " 240 " 241 " 244 " 245 0280 " 281 " 284 "285 o2C" "2Cl "2C4 02C5 R/W R R/W R/W "2"6 "246 "286 "2C6 R/W 0207 "247 "287 "2C7 R/W 02"A 024A 028A 02CA R/W "20C 024C 028C 02CC R/W "20E "24 E "28E "2CE R/W "214 "254 " 294 "2D4 R/W 0216 0256 "296 "2D6 R/W "21A "25A 029A "2DA R/W 021C "25C "29C "2DC R/W "21E 025E "29E 02DE R/W "225 "227 022D 0265 "267 "26D "2A5 "2A7 "2AD 02E5 "2E7 02ED R/W R/W R/W 0229 0231 0239 0269 "271 0279 02A9 "2Bl "2B9 02E9 02Fl 02F9 R/W R/W R/W Channel status register (CSR) Channel error register (CER) Device control register (DCR) Operation control register (OCR) Sequence control register (SCR) Channel control register (CCR) Memory transfer counter (MTC)--Word Memory address register (MAR)--high word Memory address register (MAR)--low word Device address register (DAR)--high word Device address register (DAR)--low word Base transfer counter (BTC)-high word Base address register (BAR)-high word Base address register (BAR)-low word Normal interrupt vector (NIV) Error interrupt vector (EIV) Channel priority register (CPR) Memory function code (MFC) Device function code (DFC) Base function code (BFC) R/W General control register (GCR) 02FF Ping-Pong Buffer The ping-pong buffer has a pair of sector buffers that are used for hard disk and SCSI traffic. The main function of the ping-pong buffer is to provide contin- 3-llB Principles of Operation uous data transfer by allowing one buffer to load while the other is unloading data. There are four independent control devices that interact with the ping-pong buffer: system bus sequencer, hard disk controller WD2010, SCSI sequencer, and disk buffer sequencer. When the ping-pong buffer is operating, the system bus and buffer sequencers are active and either the hard disk controller or the SCSI sequencer is active. The system bus sequencer controls the transfer of bytes between the ping-pong buffer and the system bus by packing bytes into words and unpacking words into bytes. The hard disk controller loads or unloads its side of the ping-pong buffer. In addition, the hard disk controller may edit the data before relinquishing the buffer. The SCSI sequencer loads and unloads its side of the ping-pong buffer for the SCSI controller. The disk buffer sequencer waits for the sequencers on both sides of the ping-pong buffer to finish loading or unloading their respective buffer, then the disk buffer sequencer flips the ping-pong buffer. Bits FPD08 through FPD12 of the disk mode register control the ping-pong buffer. Refer to Table 3-18 for the disk mode register control-bit assignments. The definitions of the control signals described in Table 3-18 are discussed in more detail as follows. The system bus read (MBREAD) signal (bit 8) determines the direction of data flow for the ping-pong buffer. When MBREAD is high, data is read from the system bus into the ping-pong buffer and then written to the hard disk or SCSI controller. When the SCSI mode (SCSIMD) signal (bit 9) is high, the SCSI controller is connected to the ping-pong buffer. When SCSIMD is low, the hard disk controller is connected to the ping-pong buffer. When the initialize buffer (INITBUF*) signal is low, the ping-pong buffer is initialized. The buffer mode (BUFMD0 and 1) signals select the size of the ping-pong buffer (512, lK, 1.5K, or 2K bytes). 3-119 Principles of Operation Ping-Pong Buffer Control Logic The majority of the control logic for the ping-pong buffer is implemented by the following PALs: • disk register gating PAL (13D) • disk buffer sequencer PAL (14D) • disk buffer gating PAL 1 and 2 (12C and 12D) • DMA arbitration PAL (11C) The heart of the ping-pong buffer control logic is contained in the disk buffer sequencer PAL. In addition to the state sequence logic, the disk buffer sequencer contains an AFF, disk-done (DISKDONE), SCSI-done (SCSIDONE), and system-bus-done (MBDONE) flip-flop. The purpose of this PAL is to manage the toggling of the ping-pong buffer. When initialized (via the INITBUF signal), the sequencer goes to the idle state and the AFF is reset (for read) or set (for write). When AFF is set, the A side of the ping-pong buffer is facing the disk controller (WD2010) and the SCSI controller. The B side of the ping-pong buffer is facing the system bus. Also, at initialization time, the ping-pong buffer counters are loaded with a count specified by the BUFMD0 and BUFMDI signals. When each buffer counter reaches its limit (as a result of the buffer being loaded or emptied), the appropriate DONE flip-flops are set. When the MBDONE flip-flop and either the DISKDONE or the SCSIDONE flip-flops are set, the sequencer generates a flip-buffer signal which toggles the buffer, loads the counters, resets the DONE flip-flops, and changes the state of the AFF flip-flop. Then the process repeats. Another section of the ping-pong buffer is called the system bus sequencer. The system bus sequencer uses a combination shift-register and disk-register gating PAL to move data between the ping-pong buffer and the disk register. The system bus sequencer begins operation when the DTACK signal occurs to indicate that a system memory cycle is complete. The sequencer then starts to 3-120 Principles of Operation move two bytes between the disk register and the ping-pong buffer. When finished, the sequencer waits for another DTACK signal to repeat the cycle. The SCSI sequencer operates the same as the system bus sequencer, except that the cycle begins when the SCSIDREQ signal occurs. Then the SCSI sequencer transfers one byte between the SCSI controller and the ping-pong buffer. The method of data transfer between the disk controller (WD2~1~) and the ping-pong buffer is determined by the WD2~1~ protocol. Refer to the western Digital WD28lB Data Handbook for additional details. The disk-buffer gating PALs use the signals generated by the various sequencers to make the read, write, and increment signals for the ping-pong buffer. The data transfer between the ping-pong buffer and system memory is pipelined. Thus, the first and last words transferred require special handling by the DMA arbitration PAL. The DMA arbitration PAL performs this function by raising and dropping the DMA request at precise times determined by the states of the registers. Refer to Timing Diagrams at the back of this section for ping-pong buffer timing. Controller Interface The controller interface provides the interface between the file processor and controller PCBs. The controller interface has two data buses and a set of miscellaneous control lines. The primary data bus (BD~-7) is an a-bit bidirectional bus used for sending commands and receiving status from the tape, floppy disk, and hard disk controllers on the con troller PCB. In addition, the primary data bus is used to transfer data between the file processor and the tape or floppy disk controllers. The secondary data bus (DD9-7) is an a-bit bidirec tional bus used by the hard disk controller to transfer data to/from the ping-pong buffer. 3-121 Principles of Operation The control lines can be divided into three groups. The first group contains the interrupt lines (DINT*, TINT*, and FINT*) that are connected between the hard disk, tape, and floppy disk controllers respectively. When asserted, these control signals indicate which controller is interrupting the file processor. The second group contains the address latch enable and controller reset (ALE and CTLRST*) signals that load the address latch and reset the controller PCB. The third group contains the controller read, write, and chip select (CTLRD*, CTLWR*, and DFTCS*) lines that are used to access all the controllers and ports on the controller PCB. Refer to the Controller PCB discussion later in this chapter for addressing and programming the hard disk, floppy disk, and tape controllers. Controller PCB ReadlWrite Control Logic The controller PCB read/write control logic is contained in the DMA read/write control PAL (12B) which performs the following functions: • generates read and write signals for the controller PCB • controls the DMA data transfer for the floppy disk and tape drives • controls the direction of the controller data transceiver Refer to ~iming Diagrams in the back of this section for data transfer between system memory and floppy disk or tape controller timing. Also, refer to ~iming Diagrams for 8986 read from/write to hard disk controller timing. Printer Controller The printer controller contains the printer logic PAL (2lA) which generates the DATA STROBE signal to the parallel printer interface. The printer logic PAL keeps the DMA data transfer rate for the printer under 3-122 Principles of Operation 50K bytes per second so that enough bandwidth remains for ping-pong buffer data transfers. The printer controller has a centronics interface that allows any peripheral device with a centronics interface to connect to the system. The interface consists of the printer data register for transmitting information and the printer status port for receiving status from a peripheral device. The printer data can be loaded via programmed I/O or from the DMA controller. The transfer rate, when connected to the DMA controller, is a maximum of 59K bytes per second. The programmed I/O is used during boot diagnostics to report the file processor hardware status. Refer to Tables 3-23 and 3-24 for the printer port and status port bit assignments. Refer to Timing Diagrams at the back of this section for data transfer between system memory and printer timing. Table 3-23. Printer Port Assignments Addresses (Hex) R/W Description 0602 0704 W R Printer data register Printer status port Table 3-24. Printer Status Port Bit Assignments Bits Signal Function FPD00 ACK Acknowledge pulse (2-5 microseconds) which indicates either the receipt of a data character by a peripheral device or the end of a functional operation 3-123 Principles of Operation ~able Bits 3-24. Printer Status Port Bit Assignments (Cont. ) Signal I Function BUSY Level which indicates that the peripheral device cannot receive data FPDB2 PE (Paper Empty) Level which indicates that the printer is out of paper FPDB3 SELECT Level which indicates that the peripheral is selected FPDB4 FAULT* (Page Faul t*) Level which indicates a paper empty, light detect, or deselect condition FPDB5 PREQ* Not-printer request; when low, requests the printer data register to be refilled; when high, the printer data register is full FPDB6, FPDB7 Ground Always low FPDB8FPD15 Not used SCSI Controller The SCSI controller is a general-purpose controller that provides an external connection to the industry standard SCSI bus. The SCSI bus allows a maximum of seven peripheral devices to be connected to the SCSI controller at the same time, provided software drivers are in place. The peripheral devices may consist of disk drives, tape drives, printers, etc. The maximum transfer rate of the SCSI bus is 1.5M bytes per second. Refer to the ANSI X3T9.2/82-2 SCSI Small 3-124 Principles of Operation Computer System Interface specification for detailed characteristics of the SCSI bus. The heart of the SCSI controller is a National Cash Register (NCR) 5385E SCSI protocol controller integrated circuit. The 5385E integrated circuit has address 9 on the SCSI bus and performs all the SCSI protocols on the SCSI bus for the 8986 microprocessor. The 5385E interrupts the 8986 microprocessor after completion of each task. The reset logic for the SCSI controller and bus is external to the SCSI controller integrated circuit. Two control signals for resetting the SCSI controller and bus are described in the Disk Mode Register portion of Table 3-18. Also, logic is provided to detect any external reset pulse that occurs on the SCSI bus. When an external reset occurs, a latch presets which causes bit 12 of the file processor status port to go high (see the File Processor Status Port portion of Tabl e 3-18). Thus, the software can detect a reset on the SCSI bus by sampling the file processor status port. After the status is noticed, the software can clear the latch by performing a read to address 9792h (see Table 3-25 for the SCSI port assignments). The SCSI controller does not directly notify the ping-pong buffer that data transfer has been completed. Instead, the SCSI controller interrupts the 8986 microprocessor via the SCSI interrupt integrated circuit. Then the software must generate a SCSI-done strobe (see Table 3-24 for the printer status port bit assignments) which causes the ping-pong buffer to finish the SCSI bus data transfer. Table 3-25 describes the SCSI controller port assignments. Refer to the Rational cash Register (RCR) Data Handbook for additional programming information on the NCR 5385E SCSI protocol controller. Refer to Timing Diagrams at the back of this section for data transfer between SCSI controller and ping-pong buffer timing. 3-125 Principles of Operation ~able Address (Hex) 3-25. SCSI COntroller Port Assignments R/w Assignment R/w R/w R/w R/w 0300 0302 0304 0306 0308 030A 030C 030E 0312 0318 03lA 03lC R/W R/W Data register Command register Control register Destination ID register Auxiliary status register ID register Interrupt register Source ID register Diagnostic status Transfer counter (MSB) Transfer counter (2nd byte) Transfer counter (LSB) 0604 9702 W R SCSI done strobe Clear SCSI reset status R R R R R R/w File Processor Initial Program Load (IPL) Process At power-up time, a reset occurs that clears all logic, blocks the nonmaskable interrupts, and causes the 8086 microprocessor to jump to location FFFF0h of the PROM. Then firmware determines the boot process. Timing Diagrams The major timing diagrams for the file processor PCB are shown in Figure 3-13. 3-126 Principles of Operation Sample Period 250.0 nS/dl\l 10.00 nS/clk 1. 120 ~S 0 to " ~lagniflc;at Lon if.~ About Ma.:Jn Gw,;; 0 r r'1o ve.s [ L ] . - .~ +---1 Cycle ~ '" HctilJe Low Signais 8186 Read From System Memory Sample 258.0 nS. cilV n'3/c I v fJS 0 t.o Ihgnificatlon f'h.gn it') About Cur"sor ~loves , ." * *... 8186 Write to System Memory Figure 3-13. File Processor PCB Timing Diagrams 3-127 Principles of Operation Sample Period Magnification Magn 1 f'J About Cursor 110ves [ t ] 100.0 nS/dlv 10.00 nS/clk 500.0 nS 0 to x * * .~ t - - l Cycle ---+ 8886 Read From Local RAM Sa.mple Per iod Magnification f1agnlf'J About Cur'sor 110ve8 [ L ] 100.0 nS.dili 1iJ . 00 n ';,c 1 k 500.0 nS (I to .~ *." t-- 1 Cye I e ---+ 8886 Write to Local RAM Figure 3-13. File Processor PCB Timing Diagrams (Cont. ) 3-128 Principles of Operation Sarnp I e Per \ IJd Maqnlflcatlon Ma~n\fy About 580.8 n';/div 20.00 nS/clk 2.500 ~S X to Cursor Moves [ -L 1 X 0 0 i!l·-mUlIlrlHJUljUlnJlHHIUUUlIlJUUlftIUlfUlJl.IUUUU1HJU1HJWul lIIliM_ _ - n Il n _ I ' -_ _ _J ~ _____' L,.I .-c-_ _ _ _, - :1 ~~i!l.~I·....·;----~I~_~--~----~rr·=~~ IilI,WII"O_II.:-;---~ I ;« *1!"1I8·11....: ______ *11" ~1================~~ L_! r-- 1Ii~_.:;--~I- ____~-==~~~~-~~~,i +--1 Cycle --+ * Active Low Signai;3 8886 Read From DNA Controller '3amp 1e Per loa 500.0 nS/d I ' i ;:0.80 n'3/c lk r'1..~CHI1flC,~.t lon r1a~ln if') Ab,Jut Cur 'sor- f"0o\/es [ J J 2. X. 14~J ~':I X t:J :J 0 tmtWru'UU1mUUlJlflJlfU1J1Ilfu1J1JulfulJUIJlJu1JnJlfUU1JlflJlJlRrtfLllJl -d-~LJL ~l iL i1 ii i ! M * l1li. C-----~I I - l1li1111"• • t 'L-,_ - ' - -_ _ _ ---ii ~1ilI-.;:---:11 i -. 1!lII!!IIIIIl • • •:----.....;..~=============)LJ~ 1IJ:mt·-···----L r---- ~ ------'-----'---~ +--1 Cycle --+ 8886 Write to DMA Controller Figure 3-13. File Processor PCB Timing Diagrams (Cont. ) 3-129 Principles of Operation SamplE! PE!riod Magnification Magnify About Cursor Moves .1], _"I. ~ 100.0 nS/div 10.00 nS/clk 750.0 nS 0 to T~ T~ ~.LJ.LJ n' TW, TW,...-1 T';,-..j T4 x x LJ,LJ.~ LJ ir-L 11111-: I * Iil!lmll'-~ , , ,I , :~ .-.'---.-+==]1,-'-------,_,-:-,-:--' ,I ' 'r-- ! 8186 Read From Bard Disk Controller Sample Per'lo'] ~lagnificatlon 100.0 nS/d i '" 10.00 (lS,'C lk 7'50.D nS tJ to ;{ Magn 1 fl,l About Cursor ['lo',/es [ 1 J O T1 I T2 1 T3 I T.... I T-.. I '1IIIII·-_J-~l~LJl~L-.JILFLJLJL .... ~ ==~;I--~,1L.' liIi-, L ______~ ,IL *[ilI"I·• •~: * .m_I'--~--j'---:---'----'----_~ ~ * lAIr 8186 write to Bard Disk Controller Figure 3-13. File Processor PCB Timing Diagrams (Cont. ) 3-130 Principles of Operation Sampie Period 250.0 nS/diV lD.00 nS, ell< 0.0 ;.IS ::< to 1'1agn I i icat ion 11.39n 1 f'j About Cur"sor ~lo",ies [ ~ fJ ] '. -* i~ « * * " '~ ._--.....r !_ _ .~ -----~ , Actiue Low Signals Data Transfer From System Memory to Floppy Disk Controller Samp 1e Per- 1 Dd ['lagn i f i cat Ion 2S0.i3 nS,"dlV 118,gn 1 f9 About 10.1313 n'3.-'cik 0.0 ~S' to Cur-sal- ~lo'·./e3 [ t ] I) * '" '" -* '" il< i.~ *-* * --~~ ------,' , Data Transfer From Floppy Disk Controller to System Memory Figure 3-13. File Processor PCB Timing Diagrams (Cont. ) 3-131 Principles of Operation Sample Period f1agnificatlon ~1agn i fy About Cursor Moves [ t ] 500.0 nS/div 10.00 nS/clk 0.0 IJ.S x to 0 * I .~ * Active low Signals Data Transfer From System Memory to Tape Controller '3amp J e Per i od Magnification f18gn I F INE:CTOR JC • 01061 Figure 4-18. Cable Interconnections 4-33 Maintenance NOTES CONTD [2] ~~N~~ PJP,1i"'J~N~l'1mOM ~ I\ \ ""DE. CONNECT TO BACKPLANE AT J7. CONNECT TO BIICKPlANE AT J 3CONNECT TO TAPE LD'N PASS I'ILTER BO. 01070 Figure 4-18. Cable Interconnections (Cont.) 4-34 Maintenance SHIPPING A FIELD REPLACEABLE UNIT Always contact Altos Customer Service before returning a unit for factory service. If service is required, a customer service technician will assign you a Return Authorization (RA) number. Do not send in a unit for repair without an RA number. Also supply the following: • model number of your system • serial number of your system • date purchased or sent for service • specific problem • name, address and telephone/telex number of your company and name of a responsible technical person whom Altos service may contact if necessary CAUTION Make sure you back up any hard disk data you wish to save before sending the hard disk drive for repair. The test procedure destroys the data on the hard disk. Altos cannot guarantee the integrity of data on hard disks whiCh are sent for repair. Packaging the System Unit Use the original shipping container and packing if possible. If you do not have an Altos container, contact your dealer to see if one is available. If you still cannot obtain the correct container, ship the unit in a foam-padded heavy-duty corrugated shipping carton. Place a head protection sheet (shipped with the floppy drive) over the drive heads. Seal the carton securely and mark it FRAGILE. Remember to write the Return Authorization (RA) number on the outside and to insure the package. Altos cannot be responsible for lost or damaged shipments. 4-35 Maintenance Packaging the Storage Devices For best results, package tape, floppy disk, or hard disk drives in a sturdy foam-padded shipping carton if you do not have Altos packaging. If you are shipping a floppy drive, insert a head protection sheet over the drive heads. Seal the carton securely and mark it FRAGILE. Remember to write the Authorization number on the outside and to insure the package. Altos cannot be responsible for lost or damaged shipments. Packaging Printed Circuit Boards If you are shipping a printed circuit board (PCB) and you do not have Altos packaging, wrap the unit in an anti-static cushioning material (such as Air Cap TH-249 available from Sealed Air Corporation, Hawthorne, New Jersey). Do not package PCBs using foam padding. Enclose the PCB in a heavy-duty corrugated shipping carton. Seal the carton securely and mark it FRAGILE. Remember to write the Return Authorization (RA) number on the outside and to insure the package. Altos cannot be responsible for lost or damaged shipments. 4-36 CHAPTER 5 TROUBLESHOOTING INTRODUCTION. • . • • • • • • . ••.•••• TROUBLESHOOTING AIDS. • • • • • • • • . • System Overv iew. • • • • • • . • • Principles of Operation. • •• Diagnostics. • . . • • • • • •• •• • • • Diagrams . . . . . . . . . . . . . . . . . 5-4 Field Replaceable Unit Locations • • • • • • • TROUBLESHOOTING CONSIDERATIONS. . •• •••• Handling Static-Sensitive Devices.. • •• Soldering Techniques and Equipment • • • • • • Removing Integrated Circuits . • • • • TROUBLESHOOTING PROCEDURES. • • • • • • •• • Low-level Tests. • • • . • • • • •• ••• Power-Up Tests • • • • . • • • • • • • • • • • System Power-Up Seq uence. • • • • • • . • • Communications Power-Up Tests • •... CPU Power-Up Tests. • • • • • • • • • . • • File Processor and Controller Power-Up Tests. • . • • • • . . • • . • . • • • • . CPU and File Processor Communication. • • • Interrupt Signals • . • • • • ••••• Communication Protocol. . ••••••• System-Confidence Tests. • . • • • Booting the SDX Disk. • • • . ••••• Field-Service Tests. • • •• ••••••• SDX Field Service Menu. . • • • . • • • . . CPU Test Menu • • . . • • . . • • • • • • . File Processor and Controller Board Test Menu • • • • • • • . • • . • • • • SIO Test Menu • • • • • • • • • • • • • File Processor and Controller PCB Circuit Level Test Menu. • • • • • Debugger Tests • • • • • • • . • • • • • • • • CPU Debugger Commands • • • • • • • • • • • Communications Debugger Commands (Software Mode) • • • • • • • • • • Communciations Debugger Commands (Hardware Mode) • • • • • • • • . • . • ·. 5-1 5-3 5-3 5-3 5-4 5-4 5-5 5-5 5-5 5-6 5-7 5-11 5-13 5-15 5-17 5-18 5-19 5-37 5-41 5-41 5-41 5-43 5-43 5-47 5-47 5-52 5-56 5-61 5-67 5-89 5-89 5-97 5-HH Troubleshooting INTRODUCTION This chapter contains a discussion of troubleshooting aids, techniques, and detailed procedures to assist service personnel when a trouble is suspected in the Altos 1086/2086 Computer System. Most troubles can be located quickly by following the troubleshooting information in this chapter. However, if problems persist, contact your nearest Altos distributor for assi stance. NOTE Altos supports repair to the fieldreplaceable unit (FRU) level only. Printed circuit board repair should be performed by qualified service personnel. TROUBLESHOOTING AIDS Troubleshooting aids are included throughout this manual and in related publications. The following information is intended to acquaint service personnel with portions of this manual and related publications that contain useful troubleshooting and repair information. System Overview A thorough understanding of the 1086/2086 system operation is the most important aid when troubleshooting. The system overv iew information in 'Chapter 1 incl udes an introduction to the 1086/2086 system and a list of related publications that contain additional operation information. 5-3 Troubleshooting Principles of Operation Detailed electrical operation of each circuit is described in Chapter 3. Additional details on integrated circuit (IC) operation are contained in the integrated circuit manufacturer's data handbooks referenced in Chapter 3. Diagnostics power-up, system-confidence, and field-service diagnostic test programs are available in the system firmware and on the System Diagnostics Executive (SOX) floppy disk supplied with the system. These programs are designed to quickly locate a faulty field replaceable unit (FRU) or a failed part. The troubleshooting procedures in this chapter provide detailed instructions for performing the diagnostic tests. Remote diagnostic capability is also available with the optional Altos modern. Complete instructions for performing remote diagnostic tests are provided in the 1186/2186 Remote Diagnostics manual (see Related Publications in the front of this manual for information about obtaining this manual) • Diagrams Block, schematic, and PCB assembly diagrams are contained in the Schematic Diagrams supplement at the back of this manual. PCB assembly diagrams are provided to help you rapidly locate the electrical parts shown on the schematic diagram(s). 5-4 Troubleshooting Field Replaceable Unit Locations The locations of all the field replaceable units (FRUs) are shown in Chapter 1. The 1186/2186 Illustrated Parts List manual also shows the FRU locations and lists all of the component parts of the le86/2e86 system. TROUBLESHOOTING CONSIDERATIONS Consider the following information before troubleshooting the le86/2e86 Computer System. Handling Static-Sensitive Devices Certain precautions must be taken when working with static-sensitive devices, such as, microprocessors, field-effect transistors (FET), complimentary metal-oxide semiconductors, (CMOS), and other large-scale integration (LSI) devices that use metal-oxide semiconductor (MOS) technology. Static charge buildup in a person's body or leakage from an improperly grounded soldering iron can cause static-sensitive device failure. Before handling a static-sensitive device or a PCB with such devices attached to it, ground any static voltage that may have accumulated in your body by touching an object that has been earth grounded. A bare wire wrapped around your wrist and attached to an earth ground is effective when working extensively with static-sensitive devices. When soldering on a static-sensitive device, use a soldering iron with a properly grounded three-wire cord. (Refer to Soldering Techniques and Equipment for a discussion of recommended soldering irons and procedures.) 5-5 Troubleshooting A static-sensitive device may appear defective due to leakage on a PCB. Observe the precautions for grounding static voltages described in the preceding paragraph and clean both sides of the PCB with flux remover or an eraser before replacing what may be a good static-sensitive device. For discrete FET devices, clean thoroughly between the gate, drain, and source leads. static-sensitive devices may be packaged in conductive foam or have a protective shorting wire attached to the pins. Remove the conductive foam just prior to inserting the device in its socket or soldering to a PCB. Remove the shorting wire only after the device is inserted in its socket or after all the leads are soldered in place. Soldering Techniques and Equipment Observe the following recommendations when removing or replacing components soldered to a PCB. Poor soldering practices can damage a PCB or heat-sensitive electrical components. Choosing the proper soldering iron is essential before attempting to remove or replace soldered-in components. Excessive heat is a common cause of damage to a component or PCB. However, transient voltages from solder guns or improperly grounded soldering irons can also damage certain voltage-sensitive semiconductor devices. Refer to Static-Sensitive Devices for more specific information. A 15- to 27-watt pencil-tip soldering iron is recommended to avoid separating the etched circuit wiring from the board material and to avoid damaging active components. A temperature-controlled soldering station rated at 7BB degrees Fahrenheit with a fine cone or a very fine chisel tip can also be used. 5-6 Troubleshooting CAUTION Solder guns are not recommended for removing or replacing soldered-in components on a printed-circuit board. The added possibility for over-heating and the large transient voltage induced by the soldering gun could cause damage to heat- or voltage-sensitive devices. The following additional equipment is recommended for removing and replacing soldered-in components. • Solder Sucker - Hand-operated vacuum tool used to remove liquified solder from the PCB. • Solder Wick - Resin-soaked copper braid used for removing excess solder from the lead connections on the PCB. See Removing Integrated Circuits for precautions relating to the use of a solder wick on a multilayer PCB with plated-through holes. • Flux Remover - Non-corrosive chemical used to clean foreign material from the PCB before soldering, and to remove any flux residue where components have been replaced. Flux remover is also used to clean any foreign material from the PCB during preventive maintenance. Isopropyl alcohol is also recommended as a cleaner. • Acid Brush - Small stiff-bristled paint or toothbrush used with flux remover to clean flux and other foreign material from the PCB. Removing Integrated Circuits The easiest and safest method for removing soldered-in integrated circuits (ICs) from a PCB is to cut off each pin as close to the IC case as possible with a tip dyke (diagonal cutter) as shown in Figure 5-1. 5-7 Troubleshooting DIAGONAL CUTTER 01068 Figure 5-1. Removing ICs (Cut Pin Method) Use the proper soldering iron as previously described under Soldering Techniques and Equipment. Then, to avoid excessive heat buildup in one area of the PCB, apply heat directly to each pin in a random order. Remove the loosened pin with the tip of the soldering iron or with the needle-nose pliers as shown in Figure 5-2. Allow a moment for the PCB to cool before proceeding to the next pin. Apply just enough heat to remove any stubborn pins. 5-8 ifoubleshooffng SOLDERING IRON Figure 5-2. Removing IC Pins For a multilayer PCB with plated-through holes, use a solder sucker to remove the remaining solder from inside each hole as shown in Figure 5-3. If possible, suck the solder from the opposite side of the PCB from where the heat is applied. 5-9 Troubleshooting SOLDERING IRON SOLDER SUCKER ~ SOLDER SUCKER PREFERRED METHOD ALTERNATE METHOD 01064 Pigure 5-3. Removing Solder from Plated-Through Boles Use a solder wick to remove excess solder from around the lead connection pads on the top and/or bottom surface of the PCB as shown in Figure 5-4. CAUTION Do not use a solder wick to remove solder from inside plated-through holes. The heat required for the solder wick to remove the solder from inside the hole could damage the PCB. 5-H!J Troubleshooting SOLDERING I RON SOLDER WICK 01065 Figure 5-4. Removing Solder fram Lead Connection Pads TROUBLESHOOTING PROCEDURES This section contains detailed troubleshooting procedures that use diagnostic programs available in the 1~86/2~86 system firmware or from the Altos Service Diagnostics Executive (SOX) floppy disk included with the system. These procedures are divided into low-level, power-up, system-confidence, field-service and debugger tests. In addition to these five tests, remote diagnostic tests can also be performed with an optional Altos communications modem. The remote diagnostic tests are not included in this manual but are in the 1886/2886 Remote Diagnostics manual (see Related Publications in the About This Manual section for information on obtaining this manual) • 5-11 Troubleshooting Which of the test procedures described here will quickly locate a trouble depends on the type of trouble and whether you wish to locate a faulty FRU or electrical component of the FRU. Carefully read the test procedures to help determine which one is most applicable for you. Refer to the Schematic Diagrams supplement to this manual to help troubleshoot the 1~86/2~86 system. CAUTION Before attempting to troubleshoot, be sure that the main power supply and hard-disk drive power supply are set for the proper AC line voltage. (Refer to Chapter 4 for the main and hard-disk power supply conversion instructions. ) NOTE To quickly locate the test procedures, look for the red tab along the right-hand edge of the first page of each procedure. 5-12 Troubleshooting Low-Level Tests Use Table 5-1 to perform the low-level tests. These tests are appropriate when the system fails to power-up or boot and the diagnostic tests will not run. Most of these tests do not require qualified service personnel. Table 5-1. No display on terminal. System seems dead Low-Level Trouble Analysis Probable cause Remedy a. Screen has cycled off Press return key b. Brightness or contrast too low Adjust controls c. No power to system Plug in a lamp or appliance to ver ify the power source d. Power cable loose or defective, or fuse blown. Replace fuse or power cord. CAUTION If the fuse blows repeatedly, there is a short circuit in the system. Refer this trouble to qualified service personnel. Display appears on terminal, but no response from keyboard Terminal operation normal, but system seems dead. a. System "hung" Push system reset switch. b. Terminal or system trouble Verify terminal by plugging into another system, or checking other terminals on the system. a. Power cable loose or defective, or fuse blown. Replace fuse or power cord. WARNING Hazardous voltages are present in the power supply. Use extreme caution when measuring voltages. Only qualified service personnel should attempt to check the power supply. 5-13 Troubleshooting Table 5-1. Low-Level Trouble Analysis (Cont.) Symptom Remedy Probable cause NOTE The power supply is a switching type and must be checked under load to ensure accurate results. Terminal operation normal, but system seems dead. (Cont.) b. Power supply DC voltages out of tolerance. Check power supply voltages with a digital voltmeter. (Refer to Table 5-2 for power supply output voltages.) Power supply malfunctions. Power supply defective. Repair or replace power supply. If the power supply output voltages are out of tolerance, we recommend that the power supply be returned to the factory for repair or replacement. Table 5-2. Power Supply DC Voltages IRange. Voltage Measured At +5 J5, Pin 4 +5.9 to +5.2 +12 J5, Pin 6 +11.4 to +12.6 -12 J5, Pin 3 -11.4 to +12.6 Refer to Chapter 4 for detailed assembly removal and replacement procedures. 5-14 Troubleshooting Power-Up Tests The power-up tests use the ROM-based diagnostic tests contained on the CPU, communications, and file processor PCBs. The power-up tests are always performed when power is applied or the system is reset. Refer to Figure 5-5 for a block diagram of the power-up test sequence. These tests check the hardware configuration on each PCB, identify any missing or failed assemblies, and then confirm communication with the system as follows: • communications (SIO) tests check local RAM and PROM, I/O integrated circuits, DMA controller, interrupts, system bus, and initialize memory • CPU tests check the PROM, cache RAM, local RAM, translation and tag RAM, clock, optional floating-point processor, interrupts, and system bus • file-processor tests check the local RAM and PROM, interval timer, system bus, DMA controller, and magnetic-media controllers 5-15 Troubleshooting , I I ., I I COMMO it P.: (_ INTERNAL TESTS 'td ef-Ic, ",:U 6,1 lt4# eyt ... ~ ~ c.. J.,t.., - 68020 OR 80286 CPU INTERNAL TESTS ~ I COMM 1 INTERNAL TESTS INTERNAL TESTS COMM2 I INTERNAL TESTS CHECK INPUT FOR REMOTE BOOT I , REMOTE SWITCH BAUD, AND CONSOLE I • I , NO REMOTE I .... .... < ~ .... .... < ~ < ~ < ~ MAIN MEMORY TEST t CHANNEL A TTEN r- REPORT INTERNAL RESULTS PRINT RESULTS 1- CHANNELATTEN CHANNEL A TTEN r- START EXTERNAL TEST PRINT RESULTS ~ CHANNEL ATTEN CHANNEL A TTEN FINISH TESTS PRINT RESULTS SET FLAG ;....foV'!!!.· CHANNEL ATTEN REPORT RESULTS PRINT RESULTS SET FLAG ,i""t CHANNEL ATTEN REPORT RESULTS PRINT RESULTS SET FLAG l CHANNEL ATTEN GET BOOT CODE l WAITING FOR COMMANDS AUTO BOOTING WAITING FOR COMMANDS I WAITING FOR COMMANDS WAITING FOR COMMANDS 02138 Figure 5-5. System Power-Up Test Sequence 5-16 Troubleshooting System Power-Up Sequence During power-up, the master communications (SIO) PCB firmware proceeds in the following sequence. 1. After internal verification, the communications PCB firmware sends a COMMUNICATIONS BOARD POWER-UP TESTS message to port B (main console). 2. After internal verification, the master communications PCB tests the system memory. 3. After the internal and external tests are completed, the master communications PCB sets up a firmware protocol block and sends a channel attention to the CPU PCB. The communications PCB. will timeout if the CPU does not respond in a few seconds. 4. After receiving acknowledgement from the CPU PCB, the communications PCB displays its power-up test results on the main console (port B) • 5. The master communications PCB performs the same test requests for the file processor PCB. If there is a file processor error, a corresponding error message is displayed. 6. Other communications (SIO) PCBs are checked for availability. 7. The auto boot from the hard disk (highest logical priority device) is performed, unless the user presses a key to interrupt the process. 8. If the boot operation is successful, control is transferred. Otherwise, an error message is displayed with a new menu to allow the user to either boot from a particular device or enter the debugger routine (see Debugger Program for additional details). 9. If a floppy disk boot is requested, the CPU PCB tries a slow-speed check for dual-speed floppy disk drives. If this fails, then a high-speed check is attempted. If both of these checks fail, then the boot menu is displayed. 5-17 11 Troubleshooting Communications Power-Up Tests The communications monitor program has two menus: one for debugging the hardware, and the other for debugging software. At power-up time the monitor is in the software mode. The hardware mode is a hostile environment and is not intended for normal use. To switch modes, type the key, then the key at the command level. 1. Cbecksum the PROMs The PROMs are summed separately to determine which one(s) to replace. A failure of the checksums is considered a maj or fail ure beca use the integr i ty of the PROMs is in doubt. No other tests can be trusted since they may pass from unknown changes in the firmware. 2. Local Bus Data Ripple The main RAM is on a l6-bit bus. The first word is used to test the data lines. A 1 bit is rippled through the data lines, then a 9 bit is rippled through. 3. Local Bus Content March The local RAM is tested with two patterns, 5555 and AAAA. This test simply marches through RAM one word at a time. After each location is tested, it is cleared with a 9. 4. CIO The internal registers are loaded and checked for valid data. 5. SCCl The internal registers are loaded and checked for val id data. 6. SCC2 The internal registers are loaded and checked for valid data. 5-18 Troubleshooting 7. SCC3 The internal registers are loaded and checked for valid data. 8. SCC4 The internal registers are loaded and checked for val id data. 9. sces The internal registers are loaded and checked for val id data. 11. DMA COntroller The internal registers are loaded and checked for val id data. 11. System Memory The system memory is sized in 64K byte blocks. Then each block is tested with the standard patterns of 5555 and AAAA. After a location is tested it is cleared. CPU Power-Up Tests The monitor program is executed whenever the system is powered up or reset. The power-up sequence starts with a series of tests that validate the system as follows: 1. Checksum the PROMs The PROMs are summed separately. A failure of the checksums is considered a major failure because the integrity of the PROMs is in doubt. No other tests can be trusted. If any other tests pass, it may be from some unknown change in the firmware. 5-19 Troubleshooting 2. cache RAM Data Ripple The cache RAM is organized as two sets of words. The data ripple test must read and write a test word to locations 9 and 2. The cache RAM is located from 492999 to 493FFE. Thirty-two data bits are tested. A I bit is rippled through the data lines, then a 9 bit is rippled through. 3. cache RAM Address Ripple The cache RAM is loaded with a background pattern. Then selected locations are tested for this pattern. It should be noted that a bad RAM can look like a bad address bus. Therefore, this test assumes the cache RAM is good. There are four RAMs in the cache memory, and they are addressed with the two lower address lines. Then the next 11 addresses select the byte in the cache RAM. Each RAM is tested individually to check the addresses going to each one. 4. cache RAM Content March The cache RAM is tested with two patterns: 99 and" FF. This test marches through RAM one byte at a time. If a particular address location fails, then the test loops on that address location. This test leaves all zeros in the cache RAM. 5. Translation RAM Data Ripple The translation RAM is located from address 499899 to 499FFE. Twelve data bits are tested. The first location is used to test the data lines. A I bit is rippled through the data lines, then a 9 bit is rippled through. 5-29 Troubleshooting 6. Translation RAM Address Ripple The translation RAM is loaded with a background pattern of incrementing words. Then selected locations are tested for this pattern. It should be noted that a bad RAM can look like a bad address bus. There fore, this test assumes the translation RAM is good. There are only nine address lines to test. Address line 9 is not toggled here because all translation RAM addresses are even. 7. Translation RAM Content March The translation RAM is tested with two patterns: 9999 and FFFF. If the test passes, then the translation RAM is initialized for a one-to-one mapping. This test marches through RAM one word at a time. If a particular location fails, then the test loops on that location. If the system has additional translation RAM, then it is also tested and initialized. 8. Tag RAM Data Ripple The tag RAM is lK words long and is located from address 491999 to 491FFE. Twelve data bits are tested. The first location is used to test the data lines. A 1 bit is rippled through the data lines, then a 9 bit is rippled through. 9. Tag RAM Address Ripple The tag RAM is loaded with a background pattern of incrementing words, then selected locations are tested for this pattern. "It should be noted that a bad RAM can look like a bad address bus. Therefore, this test assumes the tag RAM is good. There are only nine address lines to test. 5-21 Troubleshooting NOTE Address line 0 is not toggled here because all tag RAM addresses are even. 11. Tag RAM content March The tag RAM is tested with two patterns: 0000 and FFFF. If the test passes, then the tag RAM is initialized for a one-to-one mapping. This test marches through RAM one word at a time. If a particular location fails, then the test loops on that location. This test leaves all ones in the tag RAM to invalidate all tags. 11. Not Performed 12. Not performed. 13. Not performed. 14. Not performed. 15. 88287 Numeric Processor Extension The 80287 is initialized and the status is read. The status will be all zeros if 80287 is functioning. If the status is good, two BCD numbers in memory are added and the result placed in another location. The result is then checked for the correct answer. 16. Interrupt Controller Test Using Clock The interrupt controller is set up for the normal mode of operation, then interrupts 6 and 7 are introduced through the hardware output port. After these two interrupts pass, the clock interrupt is tested. Interrupts 1 through 5 are not tested because there is no way to produce them. The clock-control register is set to interrupt every 1/10th of a second, then the clock is reset. 5-22 Troubleshooting 17. Write cache Miss The tags are made invalid by setting the invalid bits. Then 4K of system-bus memory is written to with an FFFF pattern while the cache is disabled. The cache has already been set to zeros from the cache content test. After the system-bus memory is written, the cache is disabled and checked to verify that it still contains the zeros. The cache should never be updated during a write to system-bus memory. 18. Read cache Miss The cache is enabled from the start of the test. The tag invalid bits are set to invalid for all the tags. A 4K byte block of system-bus memory is initialized to all ones. The system-bus memory block is then read at every fourth location. The cache is then compared to verify that it contains all ones like the memory block. Then the tags are checked for the proper addresses and the valid bits are set. 19. Write cache Bit The tags are all valid from the previous test. The cache is enabled and a 4K byte block of system-bus memory is initialized with a 9B9B data pattern. The cache is then disabled. The system-bus memory block is read, but the data is ignored. Then the cache memory is read and compared to the 9B9B data pattern. If the cache compares, then this test fails. 28. Read Cache Bit The tags are valid. The cache is disabled and loaded with a F4F4 data pattern. The cache is then enabled. The system bus memory is read again, but the data should corne from cache RAM instead of system-bus memory. The data read back should equal the F4F4 data pattern. 5-23 ffoubleshoofing 21. cache Execution A 4K byte block of system bus memory is loaded with "inc dx" instructions and a far return at the end. The cache is enabled, then a call is made to the code and it executes. Then cache is disabled and checked to verify that it matches the code in memory. The dx register is also checked for the proper value.l. 22. Tag update With Diagnostic Bit Settings The cache is enabled from the start of the test. The tag invalid bits are reset to validate all the tags. The diagnostic test bit is set to simulate a write from another bus master. A 4K byte block of system bus memory is initialized to all ones. The tags are checked to verify that the valid bits are set to invalid. 23. Alternating I/O and Memory Read Cacbe This test is intended to check the hardware as different machine states are introduced. The cache is enabled and a sequence of reads are done. The translation RAM is read from, then the system bus memory is read from, and the cache RAM is checked to verify that the data was transferred. This sequence is repeated for the monitor and tag RAMs also. Then the order is reversed so that the system bus memory is read from first and the other RAMs second. The cache is always checked last to ensure that the data was transferred. Once the preceding tests have been performed, the CPU waits until the communications (SIO) PCB is ready to get the results. 5-24 ffoubleshooffng If the power-up tests pass, the first test summary messages to appear on the system console should be: Each dot on the bottom line of the displayed message equals 256K bytes of system memory. After about 35 seconds, the next test summary messages similar to the following should appear: * If there is a second SIO installed. If your system has more than two communications PCBs, you will see more than one SIO message, such as SIO 12 passed, etc. (SIO is an abbreviation for serial input/output.) 5-25 Troubleshooting If the CPU power-up test failed, the following message appears: No response f rom the CPU Table 5-3 lists the power-up test failure status monitored at the output latch port at location 25A on the CPU PCB. ~able 5-3. CPO Failure StatuB at OUtput Latch Port -rest Ro. 1 2 3 4 5 6 7 8 9 1" 11 12 13 14 15 16 17 18 19 2. 21 22 23 2 7 5 6 6 5 9 4 12 3 ••" •" ••• •• • • •" • ""• "" " "" " "" """ "• "" "" "" X"" X• X X X X 1 1 1 1 X X X 1 1 1 1 1 X X 1 X X X X X X X X X 15 2 16 1 1 1 • " "" X " X 1 1 1 1 X X •" " " X " X 1 1 1 1 X X 19 • "•" "" "• ""• X X X X Pin -.bers Bit Positions PROM checksum test Cache data ripple Cache address ripple Cache content Translation data ripple Translation address ripple Translation content Tag data ripple Tag address ripple Tag content Not performed (illegal) Not performed (illegal,) Not performed. (illegal) Not performed (illegal) 8"287 NPX test Interrupt controller test Write cache miss Read cache miss Write cache hit Read cache hit Cache execution test Tag update Alternate I/O and memory " ••" " "" "" •• " •" '" " '" " " "" '" " " '" "'" '" '" " •'" ''"" '" " '" '" " all power-up tests have passed, 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 If the message ~pe any Character to interrupt autoboot appears. Press any key within the next five seconds. The screen then displays a boot menu similar to: 5-26 Troubleshooting If you did not press a key within five seconds, the system will attempt a default boot (autoboot) from the hard disk. This is normal start-up procedure after you install the operating system software. If the autoboot failed or if you entered a 1, and the boot from the hard disk failed, a message similar to the following will appear: Status bytes 1 through 5 in the preceding Boot failed, status: II II II II II message indicates the hard disk status as follows: RBSULTS BftE 1: rIJ 1 2 3 4 5 6 FF = No error = General error = Device not supported = Device not present = Invalid command = Interrupt/DMA operations error Digital WD2rlJlrIJ hard disk controller command error Command accepted, but not yet finished = western = RESULTS BftE 2: Contains the contents of the WD2rlJlrIJ error register. Refer to Table 5-4 for a detailed description of the error register bits. RESUL~ BftE 3: Contains the contents of the WD2rlJlrIJ status register. Refer to Table 5-4 for a detailed description of the status register bits. 5-27 Troubleshooting RESULTS BYTB 4: Cylinder. RESULTS BYTE 5: Cylinder. Tables 5-4 and 5-5 provide a detailed description of the hard disk controller (WD2BlB) error and status register bits. Refer to the western Digital WD28li Data Book for additional information. Table 5-4. Bard-Disk Controller Error Register Bit Descriptions Bitl Bit No. _ Name ISymbol Description set when an 1D field has been found with a bad block mark (used for bad sectors) 7 Bad Block Detect BBD 6 CRC/ECC CRC/ECC Data Field Error 5 Reserved 4 1D Not Found 3 Reserved 2 Abort Command 1 set when a CRe error occurs in the data field 1D Set to indicate that the correct cylinder head, sector, and size parameter could not be found AC Command is aborted and this bit is set if; DRDY has not been asserted, or WF has been asserted, or the command issued has an unidentified command code Track Zero TK Command Set during Restore command when TKBB input has not indicated that the head has reached track BB (in 2B47 steps) 5-28 Troubleshooting Table 5-4. Bard-Disk Controller Error Register Bit Descriptions (Cont.) I Bit Bit No. _ Name Data Symbol Descr iption DM Set during a Read sector command if the data address mark is not found following the proper sector ID Table 5-5. Bard-Disk Controller Status Register Bit Descriptions I Bit Bit No. _ Name I Symbol Description 7 Busy BSY Asserted when a command is written to the command register and, except for the Read command, is deasserted at the end of the command 6 Ready RDY Reflects the status of DRDY. When zero (9), the command is aborted and the status of the bit is latched 5 Write Fault WF Reflects the status of the write fault. When one (1), the command is aborted, INTRQ is asserted, and the status of the bit is latched 4 Seek Compo sc Tells the hard disk controller that the seeking drive has finished seek and informs the controller that the seek has been completed 5-29 Troubleshooting Table 5-5. Bard-Disk Controller Status Register Bit Descriptions (Cont.) Bit I Bit No. _ RaDle Symbol I Description 3 Data Request ORO Asserted by the hard disk controller when the sector buffer is written to or read from 2 Data Corrected OWC When one (1), and error has been detected during the ECC mode and the data in the sector buffer has been corrected 1 Command in Progress CIP set by the hard disk controller to indicate that a command is being executed and indicates to the file processor that no other commands should be loaded Error ERR Indicates that a nonrecoverable error has occurred. When the host reads the status and finds this bit set, it must read the error register to determine the type of error 5-39 Troubleshooting If you entered a 2 and the boot from floppy disk failed, a message similar to the following will appear: status bytes 1 through 5 in the preceding Boot failed, status: XX XX xx xx XX message indicate the following floppy disk status: RESULTS BftB 1: 8 1 -2 3 _4 5 6 FF = No error = General error = Device not supported = Device not present = Inval id command - Itl. ''-fl'','.'' 1".,.. • .. = Interrupt/DMA operations error = NEC PD765 floppy disk controller command/ status error = Command accepted, but not yet finished RESULTS BftB 2: Contains the contents of the PD765 status register 8. Refer to Table 516 for a detailed description of the status register bits. RESULTS BYTB 3: Contains the contents of the PD765 status register 1. Refer to Table 5-7 for a detailed description of the status register bits. . RESULTS BYTB 4: Contains the contents of the PD765 stat~s register 2. Refer to Table 5-8 for a detailed description of the status register bits. RESULTS BYTB 5: Not used. 5-31 Troubleshooting Tables 5-6 through 5-9 provide a detailed description of the floppy disk controller (P0765) status register 9 through 3 bits. Refer to the NEC PD765 Data Book for additional information. Table 5-6. Floppy Disk Controller Status Register 8 Bit Descriptions Bit No. 7 I Bit Name Interrupt Code I Splbol Description IC 07 and 06 = 9. Normal termination of command (NT). Command complete and properly executed 07 = 9 and 06 = 1. Abnormal termination of command (AT). Execution of command started but not successfully completed 6 07 = 1 and 06 = 9. Invalid command issued. Command was issued but not started 07 and 06 = 1. Abnormal termination caused by the Ready line from FOO changing states during command execution 5 Seek End SE When the FOC has completed a seek, the SEEK command line = 1 4 Equipment Check EC Asserted if the fa~lt signal is received from the FOO, or if the track 9 signal fails to occur after 77 step pulses (recal ibrate) 5-32 Troubleshooting Table 5-6. Floppy Disk Controller Status Register e Bit Descriptions (Cont.) Bit No. I Bit Name Symbol Description 3 Not Ready NR Asserted when FOO is in the not ready state and a read or write bit is set. Command occurs if a read or write is issued to side 1 of a single-sided drive, then flag is set 2 Head Address HO Flag used to indicate the state of the head at interrupt I Unit Select 1 USI Flag used to indicate a drive unit at interrupt Unit Select use Flag used to indicate a drive unit at interrupt Table Bit No. Ii) 5-7~ Floppy Disk Controller Status Register I Bit Descriptions I Bit Name I SyJIbol Description EN Set when FOC tries to access a sector beyond the final sector of a cylinder 07 End of Cylinder 06 ------- 05 Oata Error OE Set when FOC detects a CRC error in either the (IO) or data fields 04 Overrun OR Set if the FOC is not serviced within a certain time during data transfers by the main system Not used. Always zero (0) 5-33 Troubleshooting Table 5-7_ Ploppy Disk Controller status Register 1 Bit Descriptions (Cont.) Bit Ro. I Bit Rame D3 ------- D2 No Data D2 (Cont. ) Spbol Description Not used. Always zero (0) set if, during execution of the READ DATA, WRITE DELETED, or SCAN commands, the FDC cannot find the sector specified in the IDR register ND Set if, during execution of the RE~ ID command, the FDC cannot read the ID field without an error Set if, during execution of the READ or CYLINDER commands, the starting sector cannot be found D1 Not Writable NW Set if, during execution of WRITE DATA, WRITE DELETED DATA, or FORMAT A CYLINDER, the FDC detects a write protect signal from FDD D0 Missing Address MA Set if the FDC cannot detect the data address mark or deleted data address mark. Also, at the same time, the MD (missing address mark in data field) in status register 2 is set. Also set if FDC cannot detect ID address mark during two index pulses 5-34 Troubleshooting Table 5-8. Floppy Disk Controller Status Register 2 Bit Descriptions Bitl Bit NO •. Raae ISymbol Description Not used. Always zero (9) 7 6 Control Mark CM Set if, during execution of the READ DATA or SCAN commands, the FDC encounters a sector that contains a deleted data address mark 5 Data Error Data Field DD Set if the FDC detects a CRe error in the data field 4 Wrong Cylinder WC Related to ND. Set when the content of C on the medium is different from that stored in lDR 3 Scan Equal Hit SH Set if, during execution of the SCAN command, the condition of nequal" is satisfied 2 Scan Not Satisfied SN Set if, during execution of the SCAN command, the FDC cannot find a Sector on the cylinder that meets the condition of nequal n in the above command I Bad Cylinder BC Related to ND. Set when the content of C on the medium is different from that stored in the lDR and the content of C is FF Missing Address Mark in Data Field MD Set if, when data is read from the medium, the FDC cannot find a Data Address Mark or Deleted Data Address Mark 5-35 Troubleshooting Table 5-9. Floppy Disk Controller Status Register 3 Bit Descriptions Bitl No. Bit Name I Description Symbol NOTE The following data is available in the parameter block and is not written to the screen D7 Fault FT Indicates the status of the Fault signal from FDD D6 write Protect WP Indicates the status of the Write Protect signal from FDD D5 Ready RY Indicates the status of the Ready signal from FDD D4 Track 0 T0 Indicates the status of the Track 0 signal from FDD D3 Two Side TS Indicates the status of the Two Side signal from FDD D2 Head Address HD Indicates the status of the Side Select signal to FDD Dl unit Select 1 USI Indicates the status of the Unit Select 1 signal to the FDD D0 unit Select 0 US0 Indicates the status of the Unit Select 0 signal to the FDD 5-36 Troubleshooting Entering a 3 from the boot menu (or from the menu that appears when the boot fails) gets you into the CPU monitor debugger and a message from the communications PCB similar to the following appears: Entering a 4 from the boot menu gets you the SIO monitor debugger and a message fram the communications PCB similar to the following will appear: If a failed message appears in the power-up test summary, determine which tests in the SDX Field Service Menu are applicable and run the tests. If desired, use the boot menu to select the CPU or SIO debuggers (monitors) and perform the debugger procedures as described at the back of this chapter in the Debugger 'rests section. File Processor and Controller Power-Up Tests The file processor and controller firmware consists of power-up diagnostic tests that verify the operation of major components on the file processor and controller PCBs. The firmware performs the following tests upon power up. Tests 1 through 12 are done internally within the 5-37 Troubleshooting file processor PCB while tests 13 and 14 are performed after the file processor gets the first channel attention signal. For tests 1 through 4, the firmware loops on each failed test, and will not proceed to the next test. For the rest of the tests, the firmware will not loop on each failed test. The firmware attempts to report the power-up status via the printer port (e6e2h). The upper four bits of the printer port are used for indicating the test number of the first failed test, while the lower four bits are for displaying the test number of the the last test. 1. PROM Checksum The firmware is located on two 4K x 8 bit PROMS. The checksum byte is written to the last byte of each PROM. Each PROM is checked separately. The sum should be e by adding up all the bytes of each PROM. 2. Local RAM Data Bus Ripple This test checks the integrity of the local RAM data bus. A e bit pattern is written to location eeee. It then ripples a 1 bit across the data bus to ensure adjacent bits are not stuck. 3. Local RAM Address Bus Ripple This test checks the integrity of the local RAM address bus. A data pattern of decimal 14 is written to local memory location 4eeeh. Then the data pattern is decremented by 1 and written to the next location by rippling a 1 bit across the address line. The last location written is eeeeh. Each written byte is checked by reading out the written data pattern, writing the complement of that data pattern, and reading back again to verify. 5-38 Troubleshooting 4. Local RAM COntent March Each memory word is first filled with a data pattern of 5555h. Each of the 16K words is checked for the data pattern and the complement AAAAh is written back to the same word and verified. 5. Local Memory Parity Error This test checks the local memory parity. For each location tested, an even data pattern (already writ ten during the content march) is read, then the odd data pattern (7676h) is written and dummy read back to verify that a parity error has been generated. 6. 8254 This test programs counter B of interval timer 8254 for mode ~, loads counter ~, and starts the count. After a short delay, the counter is read back to verify that the counter has been decremented. 7. DNA Controller This test programs interval timer 8254 to generate an interrupt signal to the IRO pin of the interrupt controller 8259. The interrupt controller is then verified. 8. SCSI COntroller Upon power-up or reset, the controller will perform self-diagnostics. When self-diagnostics are complete and if no error was detected, the diagnostic-status register is checked for bit pattern I~BBBBBB which verifies the SCSI controller. 9. DNA Controller This test first clears each channel-status register by writing FFh into the register. Then a 5678h pattern is written to the memory-transfer counter for each DMA channel and each memory-transfer counter is verified later. 5-39 Troubleshooting 11. Ploppy Disk Controller To verify the floppy-disk interface, the firmware first issues a SPECIFY command to set the initial values for each of the three internal timers (head unload time, step rate time, and head load time) • Then it issues a RECALL command to initialize the drive and retract the heads. If no error is detected, the interface is verified. 11. Bard Disk Controller This test first writes a 9 pattern to the SDH register of the hard disk controller on the controller PCB and reads it back to verify. Then the complement is written back to the SDH register and read to verify again. 12. Streaming Tape Controller . r The interface is verified by checking that reset/power (bit 9) is set in status byte 1. 13. System RAM Data-Bus Ripple This test checks the system RAM data bus. A 9 pattern is written to system-memory word 99999. Then a 1 bit is rippled across the data bus to ensure that adjacent bits are not stuck. 14. System RAM Address-Bus Ripple This test checks the system RAM address bus. A data pattern of decimal 19 is written to local memory location 89999h. Then the data pattern is decremented by 1 and written to the next location by rippling a 1 bit across the address line. The last location written is 99999h. Then each byte is checked by reading the data pattern, writing the complement of that data pattern, and reading back again to verify. 5-49 Troubleshooting CPU and File Processor Communication Software interface between the CPU PCB and file processor PCB is by means of a parameter block. At initialization, location lFFFCh to lFFFFh in system memory may contain a pointer to this parameter block. The first time the file processor is interrupted, the pointer is read to locate the parameter block. Interrupt Signals The basic communications interface between the CPU PCB and file processor PCB is via two signals: 1. 286INT (channel attention to file processor). When this signal is asserted, the file processor is informed that a control block created by the CPU PCB is available or the previous command request from the file processor has been executed. 2. INT286 (channel attention to CPU PCB). When this signal is asserted, the CPU PCB is informed that a control block created by the file processor is available or the previous command request from the CPU PCB has been executed. Communication Protocol Upon completion of all internal tests, the file processor waits for the first channel attention from the communications (SIO) PCB. As soon as channel attention occurs, the file processor gets the control block pointer in system memory location lFFFC and obtains all the information from the control block. The device number (word) and the command (word) should be 12 (file processor) and 9 (power-up initialization) respectively. The file processor writes a hexadecimal value of FF to the result (word) indicating that the command has been accepted. Then the file processor performs a system data-bus and system address-bus ripple test. 5-41 ffoubleshooffng Upon completion, the file processor puts the power-up test result message in the message buffer, stores the status in the result word, clears the command pending bit (bit 15 of the command word). The file processor then remains in an idle state and waits for the subsequent CPU attention. When the next CPU attention occurs, the file processor obtains the command information from the control block, writes a hexadecimal value of FF to the result word for acknowledging, branches to the appropriate routine for executing the command, puts the status in the result word, clears the command pending bit, and sends an interrupt to the CPU PCB. Then the file processor goes back to the idle state and waits for a channel attention from the CPU PCB. 5-42 Troubleshooting System-Confidence Tests The system-confidence tests use diagnostic programs contained on the Altos Service Diagnostic Executive (SDX) floppy disk included with the 1~86/2~86. The system-confidence tests are designed for the more experienced technician to perform a series of menu-driven tests that are more thorough than the previous power-up tests. The system-confidence tests contain a set of system utilities for handling system configuration and magnetic media. The system-confidence tests dynamically test the following: • • • • • • • • floppy disk drive hard disk drive controller serial communication channels central processing unit (CPU) system memory file processor interrupt controller System-confidence tests should be run if you are not sure there is a problem, or to determine if a problem is hardware or software related. System-confidence tests take about 15 minutes and verify most of the hardware, but only give a pass-fail indication. Booting the SOX Disk Perform the following procedure to boot the SDX floppy into memory to enable you to run the system-confidence tests: 1. Insert the SOX disk into the floppy drive and obtain the boot menu as described in the preceding Power-Up Tests section. 5-43 Troubleshooting 2. Type 2 to boot from the SDX floppy disk. the SDX menu to appear as follows: wait for 3. Type R and press . The following SDX Field Service Menu will appear: 5-47 Troubleshooting 3. Type the appropriate command from the Field Service Menu to perform the following test functions: b (brief). Displays a brief description of all the SDX tests with their test number and enabled or disabled status. c (clear). Clears the error history buffer and resets the pass count and error count to zero. d (disable). Allows you to disable any selected tests executed by the t command as follows: a. Enter the test number(s), separated by commas. b. Press . e (enable). Allows you to enable tests to be executed by the t command as follows: a. Enter the test number(s), separated by commas. b. Press . b (halt). Allows you to choose from two options for running the t tests: (a) the tests halt when an error occurs and (b) the program continues after an error is discovered or until the end of the test. 5-48 Troubleshooting I (loop). Allows you to select the maber of times a test will run by pressing the key to end the test • (.eDD). Allows you to select from four menu options which are displayed during the execution of the t tests: (a) disPlays all the menus, (b) stops the help menu from appearing after each command is entered, (c) stops the test menus from being displayed after the t command has been typed, and (d) allows the test or help menus to be displayed if a? or b is typed. • p (paraaeter). Allows you to change the floppy drive or S10 parameters from their default settings as follows: a. The following Parameter Menu appears after the p is typed. b. To change the floppy disk test parameters, press 2 to obtain the following Floppy Disk Test Parameters display: 5-49 ffoubleshooffng c. To change the SIO parameters, press 1 to obtain the following SIO Parameters display: d. Press B. The following prompt will appear: 5-50 Troubleshooting e. Enter the number of the communications (SIO) PCB that you want to test followed by a . The following display will then appear: f. Answer the prompts in the order presented and follow each entry with a . When the last prompt is answered, the SIO Parameters display will then appear so that you can recheck your SIO parameter changes. If you made a mistake or need to change any of the entries, repeat steps a through f. r (report). Displays the error history of specif ied tests. s (summary). Displays the name and number of all tests run, the number of passes run, and the number of errors detected. t (test). Begins running any tests in the order specified. u (utility). ? (belp). x (exit). Displays the utility menu. Displays the SDX Field Service Menu. Returns to the Main Menu. z (debugger). Enters the debugger. 5-51 Troubleshooting CPU Test Menu Perform the following procedure to obtain the CPU Test Menu: 1. Press t while in the SDX Field Service Menu. first menu displayed is the CPU Test Menu: 2. Type the appropriate command from the CPU Test Menu to perform the following test functions: 1 PROM Checksum Test. the correct checksum. The Verifies the firmware for 2 Cache RAM Test. Writes data patterns of AAAAh and 5555h into cache RAM, and checks the. data integrity word by word. 3 Translation RAM Test. Fills each of the addresses in the translation RAM with the locations of a 4K page of physical memory. The addresses are written to the translation RAM, read back, and verified. 5-52 Troubleshooting There are 1024 word entries in the translation RAM. Each word represents a 4K byte page for a total of 16M bytes of system memory. This test runs for about 8 minutes per loop and, during the test, the physical and logical addresses are each displayed as the test runs. 4 CPO Yimer and Interrupt ~st. Generates an interrupt to the CPU every 3 milliseconds via a software loop and measures the response time. If the response time is excessive, the test will fail. This test also checks the real-time clock (displays the time when the operating system is installed). The following clock verification display will appear: 5 Memory Management Unit Test. Tests the ability of the circuitry to detect violations in the access rights to mapped pages of memory. This test first creates an access to memory which is not allowed, and then tests to see whether the violation is detected. If the interrupt indicates that the violation was detected, the test passes. 6 Ruaerical Processor Test. Tests the optional 80287 numerical processor. The first part of this test involves detection of the numerical processor, followed by initialization if the optional numerical processor is present. Then the diagnostic has the numerical processor do arithmetic operations on 6 different data types including: word integer (16 bits), short integer (32 bits), long integer (64 bits), packed decimal 5-53 Troubleshooting (72 bits), short real (32 bits), and long real (64 bi ts) • 7 Main Memory Parity Test. Uses the DMA circuitry to write 8K of random data patterns from the hard disk into 8K of system memory. The data is then read back and checked for parity errors. If there were any errors, a message reports the location of the errors. Next, another 8K block of data from the hard disk is written into the next 8K of system memory. This process is repeated until the entire system memory is tested. This test shows the pass count, and the memory address of any failures. 8 Main Memory March Test. Writes a pattern of AAAA into system memory, reads it back, and verifies. Next, a pattern of 5555 is written, then read back, and verified to ensure that each of the memory cells can store a digital high or low, and are not open or grounded. As the test runs, this message is displayed: If the test fails, this error message is displayed: 5-54 Troubleshoo#ng As an example of how the memory march test displays a failure: Assume that the address pins of the RAM at location 21H were shorted together. The test detects the problem and displays the message: Next, the test will display: a. Press y and the unit asks for further information: b. Enter the size of the memory in the memory PCB that you are testing. The location of the failed RAM will be shown by a representation of the PCB. The failed RAM will be shown by two Xs at the failed RAM location. 5-55 Troubleshooting c. Replace the failed RAM and press 8 to repeat the test. 9 Main Memory Refresh Test. Tests the refresh capability of the dynamic RAMs. This test runs for approximately two minutes. If there are failures, the physical address of the failure is displayed, along with the data pattern which could not be stored at the given location in memory. File Processor and Controller Board Test Menu Perform the following procedure to obtain the File Processor and Controller Test Menu: 1. Press Nand and note that the second menu displayed is the File Processor and Controller Test Menu: 2. Type the appropriate command from the File Processor and Controller Board Test Menu to perform the following tests: 5-56 Troubleshooting 18 Floppy Randoa Seek ~est. Verifies that the floppy disk drive is working. The -Floppy Random Seek Test does 188 seeks and lists the number of cylinder and head errors at the end of the test. Three retries are allowed. Error messages for this test list the number of seek errors, but not the location of the errors. For example: Assume that the Seek Complete signal at the disk controller (uPD765) was shorted to ground. The following error message would be displayed: 11 Floppy write/Read Test. Determines if the floppy disk drive can transfer data correctly. To run this test you need a formatted disk that does not contain any valuable data. This test destroys any data on the floppy disk. However, you can also run this as a read-only test by pressing n in reply to the prompt at the start of this test: If the test fails, the error message gives the failing cylinder, head, and sector. The data pattern that was expected to be found, and the data pattern that was actually found is also listed. For example: Assume that the Write Data line for the 7486 on the controller PCB was shorted to ground. This test would then display the error message: 5-57 Troubleshooting 12 Bard Disk Random Seek Test. Verifies that the hard disk drive is working. Press the appropriate number from the following display to select which drive is to be tested: The Hard Disk Random Seek Test does 1~9 seeks and lists the number of hard and soft errors at the end of the test. Three retries are allowed. Error messages for this test list the number of seek errors, but not the location of the errors. For example: Assume that the Seek Complete signal at the disk controller (WD29l9) was shorted to ground. The following error message would be displayed: 5-58 Troubleshooting 13 Bard Disk Write/Read and Append Yest. This test writes over and destroys any operating system that has been installed on the hard disk (e.g. XENIX). The following prompt will appear to warn you: 14 Streaming ~ape Write/Read ~est. Tests the streaming tape drive using all nine tracks. For example: Assume that the Write Data line on the controller integrated circuit was open. Then the following error message will appear: 15 Streaming ~ape Append ~est. A failed Streaming Tape Append Test is indicated by an error message specifying the location of any unrecoverable data errors. The test first seeks to the beginning of the tape, then erases the tape. Next, the test writes 1 block of test data and a file mark. Then, the test writes another I block of test data and goes back to verify the filemark. 16 Concurrent DNA ~est. Tests to determine if the DMA can read from hard disk and write to streaming tape at the same time. Ability to transfer is tested, but the data itself is not checked. Error messages might state that the data was transferred but not received, or display a general 5-59 Troubleshooting message and then lock up the unit to further input. For example: Assume that an address pin on the communications PCB was floating. The test might display the following error message: 17 Printer Test. Tests a parallel printer. This test starts with the following message about the setup: 5-60 Troubleshooting 510 Test Menu Perform the following procedure to obtain the SIO Test Menu: 1. Press Rand and note that the third menu displayed is the SIO Test Menu: 2. Type the appropriate command from the SIO Test Menu to perform the following tests: 18 SIO PROM Checksum Test. Checks whether the 8086 can execute the code out of local memory. During this test the PROMs are summed separately so that the individual failing PROM can be isolated. A PROM failure is considered a major failure since the integrity ,of the firmware is in doubt. 5-61 Troubleshooting 19 SIO Memory March and Refresh Test. Tests the 16K x 4 bit local dynamic RAM memory and refresh on the communications PCB. A data pattern of 5555h is written into memory and verified. Then a data pattern of AAAAh is written into memory and verified. Finally, parity is checked by toggling the parity bit through the memory. 28 SIO LSI Chips Access Test. Ports 0 to port 9 of the SCC integrated circuits (ICs), the DMA IC and the CIO IC registers are tested to see whether they can be accessed (except the port where the modem is connected). Failures in this test are shown as a channel address location, which is to be changed to a message detailing the failing address and port number. For example, if a data pin pf any SCC was open, the error message displayed would be: Or another example: If a data pin of the DMA controller on the communications PCB was open, the error message displayed would be: 21 SIO Internal Loopback Test. Alternates data patterns between 00 and FF, and uses 256 bytes of the above data patterns to test the selected port internal loopback mode at a default baud rate setting of 9600. The maximum number of errors using this method is 511 errors. If you receive 5-62 Troubleshooting this error count, the internal SIO circuitry is not working. For example, if a data pin of the SCCl or SCC2 or SCC3 IC was open, the error message displayed would be Compare Error = 518 or Compare Error = 511. NOTE You should test the ports at various baud rates in the following tests 21,22, and 24. To change the baud rate, obtain the Field Service Menu and select the p (parameter) command as described under SDX Field Service Renu at the front of this section. Then follow the procedure for changing the SIO parameters. 22 Barber Pole Test. Runs a complete set of characters across the terminal screen. This test requires you to connect a terminal to the port that you wish to test. If the test is running correctly, the complete character set streams continuously across the terminal screen. watch the test carefully for the character set to be complete. There are no error messages in this test, if there is a hardware problem, the test will not run. 23 Echo visual Verification Test. Echos whichever character is typed in at a baud rate of 9600. This test also requires you to hook up a terminal to the port that you wish to test. While the test is being run, the following message is displayed: 5-63 lfoubleshoonng Press 2 to display the characters received and those not received: All the characters and functions received (typed in) are displayed after the Characters(s) received: message. The remaining available characters and functions are displayed after the Characters(s) not received: message. 24 SIO External Loopback Test. This test requires the use of a loopback connector which connects the DTR/DSR and Tx/Rx data signals as the following prompt informs you: Refer to Appendix D for the loopback connector assembly instructions. This test checks the handshake signals, then transmits and verifies 512 bytes through a selected port. An error count is kept and the maximum number of failures is 519. 5-64 Troubleshooting 25 SIO Interrupt vector ~st. Checks the ability of the SIO IC group to respond to different levels of interrupt priorities. Specifically, the SIO Rxbuf received interrupt, the SIO Txbuf empty interrupt, the SIO ext/status interrupt and timer A,B,C interrupt are each tested. If the test passes, then the flag is greater than zero. But if the test fails, then the flag equals zero. The failed interrupt will be displayed, as well as the port location at which it failed. 26 SIO DMA Test. Uses port 7 in full duplex, internal loopback mode. The DMA IC uses two channels of its four channel capability to first transmit, then receive, a test data pattern. Channel 3 transmits the data, and channel 2 receives the data back from the SCC. The test data pattern increments between 00 and FF four times with 256 bytes of test data. The test data is stored in local memory by the DMA IC. Two buffers are used to compare and verify that the test data patterns were transferred correctly. The test also verifies that the DMA end-of-process (EOP) interrupt is working correctly. Error messages in this test state that data was transmitted but not received. For example, if an address pin on the DMA controller is open on the communications (SIO) PCB, the SIO DMA test displays the message: Other error messages are less complete. For example, if an address pin of the DNA address latch is open, the following error message is displayed: 5-65 Troubleshooting And then the system locks up. Reboot (reset) the system to continue these tests. 27 SIO WorkNet Loopback Test. Tests the ability of port 9 to handle asynchronous and synchronous data link control (SDLC) data transmissions via RS-422. This port must work correctly for the local area network (LAN) to function. Disconnect the WorkNet cable, if one is connected, as the displayed prompt informs you: This test consists of two parts. In the first part, external clock circuitry clocks data out of port 9 at 1.42 MHz and the asynchronous data transmission mode is tested. In the second part, an internal clock for port 9 clocks data out at 38.4 kHz and the SDLC data transmissions are tested. The error messages in this test show the first test as a high speed test and the second test as a low speed test. Error messages also give compare error (CMP) messages and framing errors (a SCC error message in which the SCC internally detects a wrong bit within a SDLC message format). For example, if the ANETCLK buffer (LS125) is removed from the communications (SIO) PCB, the SIO WorkNet Loopback Test fails, and the following error message appears: 5-66 Troubleshooting Or another example: If the the ANETD lines were grounded, the following error message appears: 28 CIO Timer Test. Tests the parallel input/ output device as well as the internal timers. error message for this test might be: The File Processor and Controller PCB Circuit Level Test Menu Perform the following procedure to obtain the- File Processor and Controller Board Circuit Level Test Menu: 1. Press Nand and note that the last menu displayed is the File Processor and Controller Board Circuit Level Test Menu: 5-67 lfoubleshooffng 2. Type the appropriate command from the File Processor and Controller Circuit Level Test Menu to perform the following tests: 29 Bard Disk Controller Chip Test. This test has two parts. The first part writes an 81 data pattern into the registers of the western Digital 2818 IC. Then, the pattern is read back and compared to ensure that the two patterns match. The pattern is rotated and the previous procedure is repeated for all possible bit positions in the pattern. The second part tests the drive select circuitry. The first part of this test involves attempting to select a non-existent drive 3. If the status shows any drive selected, an error will be displayed showing that drive as being selected. The test then tries to select an installed drive, and gives an error message if any other drive was mistakenly selected. 5-68 Troubleshooting 3. Pile Processor SCSI (hip Test. Tests the 5385E SCSI protocol controller on the file processor PCB. First the 5385E is reset, and then the status of the diagnostic status register is read. The 5385E SCSI protocol controller must pass its internal power-up tests which include: (1) attempting an unconditional branch, (2) setting and resetting the data register full status bit in the interrupt register, (3) testing initial conditions and initial command registers, (4) resetting the internal diagnostic flag, and (5) flushing several bytes of data through the data pa ths of the IC. If the previous sequence of tests passes, the test goes on to try writing and then reading data patterns of 55 and AA into the data registers. 31 Pile Processor Timer Test. Tests the file processor timing with the following messages: 32 Pile Processor PROM O1eckslml Test. Sums the PROMS in the file processor PCB, and checks for correct checksums. 33 Printer Port Test. This test requires a printer port loopback connector to be placed over the loopback port as the following prompt informs you: 5-69 Troubleshooting This test checks the printer port signals using the loopback connector to loop back the signal s so they can be read. Refer to Appendix 0 for instructions on assembling the parallel printer loopback connector. If you do not connect a loopback connector, the test fails with the following error message: 34 Tape Controller Chip set Test. Ini ti al iz es the tape LSI controller, then resets, and the status of the controller board is read. The test begins with the following prompt: If this process is working correctly you should hear the streaming tape unit reset. If an error was detected, an error message will be displayed, and if not the test will continue. 5-79 Troubleshooting Next, the test sends a self test command 1 to the tape controller. Self test 1 consists of four parts: (1) LSI controller chip test, (2) 16K RAM chip buffer test, (3) data separator logic test, and (4) 8155 PIA chip test. 35 Pile Processor Interrupt Test. Saves the firmware interrupt vectors and installs the test routine vectors. Next, the first interrupt to be tested is the channel 0 interrupt vector followed by the hard disk, SCSI, tape, DMA, and floppy interrupt. Each of these interrupts must have been successfully acknowledged, and the results are displayed. At the end of the test, the firmware interrupt vectors are re-installed and the test is finished. 36 Ping Pong Buffer Test. Tests a pair of sector buffers for the ability to handle hard disk and SCSI traffic. The ping-pong buffer's principle advantage is its capacity to provide continuous data transfer by allowing one buffer to load while the other is unloading data. This test consists of two parts. First, a 512word data pattern is set up in system memory and a DMA transfer is performed from the system memory to the ping-pong buffer. If an error occurs, a message is displayed and the test stops. Then the system memory segment is cleared. Next, a SCSI-done (SCSIDONE) signal is issued to reset the buffer sequencer. A DMA transfer is performed from the ping-pong buffer to system memory. The contents of system memory is verified with the original 5l2-word data pattern. 37 Burst Logic Test. Verifies the ability of the burst logic circuitry to limit the file processor's use of the system bus. This test consists of two parts. First, a 5l2-word DMA transfer is performed with the burst logic disabled from system memory to the ping-pong 5-71 Troubleshooting buffer. If an error occurs, a message is displayed and the test stops. Then the system memory segment is cleared. Next, a DMA transfer is performed, with the burst logic enabled, from the ping-pong buffer to system memory. The burst-on time is set for 64 words and the transfer is terminated after one burst on/off cycle. The contents of system memory is verified to be a pattern with the same length as the burst-on time. ~able Test 5-11. SDX ~rouble Error Message Analysis IprObable cause CPO and System Memory PCBs (1) PROM Checksum (high/low/both) byte(s) of CPO PROM failed PROMs (2lC-A, 2lC-B) (2) Cache RAM cache failed at Illl:x Cache RAM (23C-26C) Tag RAM (lA-4A) Cache data buffer (23B-25B, 28B) Tag data buffer (6A, llA) (3) Translation RAM Failed at Translation Translation RAM (8CRAM Location = 41xxxxb l0C) (logical page = xxxxh) System memory Memory Address = xxxxxxh Table data buffers (physical page = xxxxb (12A, l6C) Expected Data = xxxxh Received Data = xxxxb 5-72 Troubleshooting Table Test S~l •• SDX Trouble Analysis (Cont.) Error Message Probable cause CPU and System Memory PCBs (Cont.) (4) CPU Timer and Interrupt Clock chip (address/ da ta) fail ure Clock (28A) Clock chip internal RAM failure Clock (28A) Clock chip counter/ interrupt failure 8259 interrupt controller (210) Clock (28A) Wrong exception interrupt occurred in response to MHO violation 88286 processor (16B) 8259 interrupt controller (210) General protection exception did not occur 88286 processor (16B) 8259 interrupt controller (210) (6) Numerical Processor Arithmetic error from numerical processor 88287 processor (12B) (7) Main Memory Parity Bard disk read error W02818 controller (6C) Hard disk drive (5) Memory Management Unit NOTE Some early systems used the hard disk for random data. If this error message appears, test the file processor/controller hard disk ci rcui try. 5-73 Troubleshooting ~able Test 5-18. SDX Trouble Analysis (Cont.) Error Message I Probable cause CPO and System Memory PCBs (Cont.) (7) Main Memory parity (Cont. ) Memory parity error parity checker/generators (11E-14E, 15E) Data buffers (12F-17F) System memory RAM (8) Main Memory March Failed at memory address = x System memory RAM Address buffers (19C, 29C, 19E, 19F, 29F, 29J) Data buffers (12F-17F) The RAM I.C. in the xxx memory board row x column x of main memory does not contain the expected data System memory RAM Address buffers (19C, 29C, 19E, 19F, 29F, 29J) Data buffers (12F-17F) Communications (SI0) PCB (18) SID PROM Checksum S10 PROM checksum error Odd Checksum = xxxxh Even Checksum = xxxxb (19) SID 510 local memory fail Memory March at x = xh and Refresh Expected Data = xxxxh Received Data = xxxxh 510 local memory parity error at x 5-74 SID PROM (29C-A or 29C-B) Address buffers (13F Address buffers (16F, 17F, 19E) RAM (2J-9J, 11J-18J) Memory parity (1J, 19J) RAM (2J-9J, 11J-18J) Address buffers (16F, 17F, 19E) Troubleshooting Table 5-11. SDX Trouble Analysis (Cant.) Test Error Message IProbable Cause Communications (510) PCB (Cont.) (20) SIO LSI Chips Access (21) SIO Internal Loopback SIO DMA chip registers write/read error DMA controller (170) Address latch (130, l5F) Local bus control (150, l6C, 20C, l7C) SIO SCC chip registers write/read error at port x (Port Address = xxxxb SCCs (lB, 3B-6 B) 510 CIO chip registers write/read error at port x CIO (2B) Receive character timeout at the xxxx character SCCs (lB, 3B-6B, lAlOA) Colnpare error ( 24) SIO External Loopback =x SCCs (lB, 3B-6B) RTS/CTS handshake not responding SCCs (lB, 3B-6B, lAlOA) No loopback connector Receive character timeout at the xxxx character SCCs (lB, 3B-6B, lAlOA) No loopback connector Compare error =x SCCs (lB, 3B-6B) Handshake signal changed unexpectedly xx time(s) SCCs (lB, 3B-6B, lAlOA) 5-75 Troubleshooting Table Test 5~18. SDX Trouble Analysis (Cont.) Error Message I Probable cause Communications (SIO) PCB (Cont.) (25) S 10 Interrupt vector (26) S 10 DMA Port x fail interrupt SCCs (lB, 3B-6B, lAl0A) SIO memory (interrupt vector area) Port x ax interrupt fail SCCs (lB, 3B-6B, lAl0A) SIO memory (interrupt vector area) Port x ext/status interrupt fail SCCs (lB, 3B-6B, lAl0A) SIO memory (interrupt vector area) Timer xx interrupt fail CIa (2B) TX SIO DNA Test Bas Compare DMA controller (170) Errors (DNA Tx and Rx SCCs (lB, 3B) IX Byte Data) SIO memory (Rx or Tx 1. Tx Data = xxxxh ax buffers) (lA-6A) Data = xxxxh 2. Tx Data = xxxxh ax Data = xxxxh DNA EOP interrupt fail (27) SIO WorkNet Loopback DMA controller (17B) CIa (2B) High speed WorkNet loop- DMA controller (170) SCC0 (lB) back (transmit 768 RS-422 loopback ckt. bytes) (3A, 4A, lC) COmpare error = x External clock (2E, 4E, 3D, 4C) 5-76 Troubleshooting ~able 5~11. Test SDX Trouble Analysis (Cont.) Error Message Probable cause Communications (SIO) PCB (Cont.) (27) SIO WorkNet Loopback (Cont.) High speed WorkNet Parity error=x OMA controller (170) (lB) RS-422 loopback ckt. (3A, 4A, lC) SCC~ High speed WorkNet Overrun error = x OMA controller (170) (lB) RS-422 loopback ckt. (3A, 4A, lC) External clock (2E, 4E, 30, 4C) High speed WorkNet Framing error = x OMA controller (170) SCC~ (lB) RS-422 loopback ckt. (3A, 4A, lC) External clock (2E, 4E, 30, 4C) Higb speed WorkNet DTR timeout = x OMA controller (170) SCC0 (lB) RS-422 loopback ckt. (3A, 4A, lC) Carrier sense ckt. (10, 20, 80) Higb speed WorkNet Tx empty timeout = x OMA controller (170) (lB) RS-422 loopback ckt. (3A, 4A, lC) External clock (2E, 4E, 80, 30, 4C) Higb speed WorkNet Receive character timeout = x SCC~ 5-77 SCC~ SCC~ (lB) RS-422 loopback ckt. Troubleshooting Table 5-11. SDX Trouble Analysis (Cont.) Error lIessage Test =-oJ Probable cause Communications (SIO) pm (Cont.) (27) SIO WorkNet Loopback (Cont. ) (28) CIa Timer Low speed WorkNet loop- SCC0 (lB) back (transmit 256 b¥tes) RS-422 loopback ckt. CRC error = x Low speed WorkNet Compare error = x SCC0 (lB) RS-422 loopback ckt. Low speed WorkNet Overrun error = x SCC0 (lB) RS-422 loopback ckt. Low speed WorkNet DTR timeout = x SCC0 (lB) RS-422 loopback ckt. Carrier sense ckt. (lD, 2D, 8D) Low speed WorkNet Tx empty timeout = x SCC0 (lB) RS-422 loopback ckt. Low speed WorkNet Underrrun timeout = x SCC0 (lB) RS-422 loopback ckt. Low speed WorkNet Receive character timeout = x RS-422 loopback ckt. SCC0 (Port 9) (lB) CIO. timer registers write/read error CIa (2B) CIO timer countdown error CIa (2B) 5-78 Troubleshooting Table 5-11. SDX Trouble Analysis (Cont.) Test Error Message I Probable cause File Processor and Controller PCBs (19) Floppy Random Seek Operation timeout error (DNA or INT) Floppy disk Floppy drive Circuitry between floppy and DMA controllers (11) Floppy Write/Read Compare error cyl= x, bead= x sector= x Floppy disk Floppy dr i ve Circuitry between floppy and DMA controllers System memory (read/write) error: cyl = x, bead = x, sector = x Floppy disk Floppy dr i ve Circuitry between floppy and DMA controllers System memory Diskette is write protected Protected floppy disk Floppy drive (12) Hard Disk Random Seek Operation timeout error CDMA or INT) Hard disk Circuitry between WD2919 and DMA controllers (13) Hard Disk Write/ Read No bard disks detected Recalibration error Hard disk power Hard disk 5-79 Troubleshooting ~able 5~11. Test SDX Trouble Analysis (Cont.) Error Message I Probable cause File Processor and Controller PCBs (Cont. ) (14) (15) Streaming Tape Write/ Read and Append (16) Concurrent DMA (29) Hard Disk Controller Unrecoverable data error Streaming tape Streaming tape drive CPU 8931 tape controller (2lA) File processor DMA controller (2lD) Cartridge is write protected Cartridge is not in place Streaming tape write protected Tape drive Tape missing Read error, no data detected Tape drive CPU 8931 tape controller (2lA) Streaming tape error Tape missing Streaming tape Streaming tape drive Hard disk DMA or INT error DMA controller (2lD) WD2910 controller (6C) Hard disk Verify error checking 2111 sector (count/ number) register WD29l0 controller (6C) WD2919 command or data transceivers (6E, 7E) WD29l0 local bus 5-89 Troubleshooting ~able Test 5-18. SDX Trouble Analysis (Cont.) Error Message lprobable cause File Processor and Controller PCBs (Cont. ) (29) Hard Disk Controller (Cont. ) Status port failed to detect a select for drive Ext.SDH latch (5E) Drive select drivers (3C, 9C, 12E, 14E) System backplane (pins P1-A27, A29, C27) Hard disk Controller status port Detected,drive select Ext. SDH latch (5E) Drive select drivers (3C, 9C, 12E, 14E) System backplane (pins P1-A27, A29, C27) Hard disk Controller status port External sdb register Ext. SDH latch (5E) written with 38 hex to Drive select drivers select non-existent drive (3C, 9C, 12E, 14E) 3, status port detected System backplane (pins P1-A27, A29, C27) a select for drive Hard disk Controller status port (3B) File Processor SCS I Chip Unconditional branCh failure in internal sequencer SCSI controller (IC) SCSI command or data transceivers (2B, 4A, 3A, 7A, 9A, 7B, IBC, 1BA) Data register full bit failure in interrupt register SCS I controller (IC) SCSI command or data transceivers (2B, 4A, 3A, 7A, 9A, 7B, 1BC, 1BA) 5-81 Troubleshooting ~able Test 5-18. SDX Trouble Analysis (Cont.) Error Message I Probable cause File Processor and Controller PCBs (Cont.) (3B) File Processor SCSI Chip (Cont.) Ini tial conditions in wrong state SCSI controller (IC) SCSI command or data transceivers (2B, 4A, 3A, 7A, 9A, 7B, IBC, IBA) Initial command bits incorrect SCSI controller (IC) SCSI command or data transceivers (2B, 4A, 3A, 7A, 9A, 7B, IBC, IBA) Diagnostic flag failure SCSI controller (IC) SCSI command or data transceivers (2B, 4A, 3A, 7A, 9A, 7B, IBC, IBA) Data turnaround failure SCSI controller (IC) SCSI command or data transceivers (2B, 4A, 3A, 7A, 9A, 7B, IBC, IBA) Dnused error bit setting in status register SCSI controller (IC) SCSI command or data transceivers (2B, 4A, 3A, 7A, 9A, 7B, IBC, IBA) CSI chip status shows self diagnostic not complete 5-82 SCS I controller (IC) SCSI command or data transceivers (2B, 4A, 3A, 7A, 9A, 7B, IBC, IBA) Troubleshooting Table 5-11. SDX Trouble Analysis (Cont.) Test Error Message Probable cause File Processor and Controller PCBs (Cont. ) (39) File Processor SCSI Chip (Cont. ) SCSI auxiliary status register not reset SCSI controller (lC) SCSI command or data transceivers (2B, 4A, 3A, 7A, 9A, 7B, 19C, 19A) SCSI interrupt not detected 8259 interrupt controller (8B) SCSI controller (IC) SCSI interrupt line to 8259 interrupt controller Interrupt latch or gate (25C and 4B) SCSI status shows command not ~mplete 8259 interrupt controller (8B) SCSI controller (lC) SCSI interrupt line to 8259 interrupt controller Interrupt latch or gate (25C and 4B) SCSI data register not full after completion of diagnostic command 8259 interrupt controller (8B) SCSI controller (IC) SCSI interrupt line to 8259 interrupt controller Interrupt latch or gate (25C and 4B) 5-83 Troubleshooting Table Test 5~1'. SDX Trouble Analysis (Cont.) Error Message I Probable cause File Processor and Controller PCBs (Cont. ) (30) File Processor SCSI Chip (Cont. ) Internal turnaround 8259 interrupt failure with data pattern controller (8H) (AA/55) SCSI controller (IC) SCSI interrupt line to 8259 interrupt controller Interrupt latch or gate (25C and 4B) SCSI Chip unknown status error code 8259 interrupt controller (8H) SCSI controller (IC) SCSI interrupt line to 8259 interrupt controller Interrupt latch or gate (25C and 4B) SCSI Chip (initial/final) SCS I controller (IC) turnaround miscompare SCSI command or data failure transceivers (2B, 4A, 3A, 7A, 9A, 7B, 10C" lOA) SCSI Chip turnaround bad parity failure SCSI controller (IC) SCSI command or data transceivers (2B, 4A, 3A, 7A, 9A, 7B, 10C, lOA) SCSI data register returned incorrect data pattern SCSI controller (IC) SCSI command or data transceivers (2B, 4A, 3A, 7A, 9A, 7B, 10C, lOA) 5-84 Troubleshooting Table 5-18. SDX Trouble Analysis (Cont.) Test Error Message IprObable cause File Processor and Controller PCBs (Cont. ) (31) File Processor Timer Channel I counter failed to (set/clear) all bits 8254 timer (25B) Clock divider (33B) Channel 8 counter was too 8254 timer (25B) (slow/fast) or problem Clock divider (33B) with timer interrupt logic (32) File Processor PROM Checksum File processor (odd/even) PROM (9H, checksmn error (33) Printer Port Data strobe, input prime, Printer port pins or printer status acknow- shorted or open ledge stuck Loopback connector Printer drivers (16A, 33D) l7A) Printer data port (19A) Printer status port (29A) Input prime * or printer status acknowledge stuck high Printer port pins shorted or open Loopback connector Printer drivers (16A, l7A) Printer data port (19A) Printer status port (29A) 5-85 Troubleshooting ~able 5~ll. Test SDX Trouble Analysis (Cont.) Error Message I Probable cause File Processor and Controller PCBs (Cont. ) (33) Prin- Printer data line (lor ter Port 2/3 or 4/5 or 6/7 or 8) logic (high/low) ,should (Cont. ) be logic (low/high) Printer port pins shorted or open Loopback connector Printer drivers (16A, 17A) Printer data port (19A) Printer status port (2riJA) (35) File Processor Interrupt Timer channel I interrupt not detected 8259 interrupt controller (8H) 8254 timer (25B) Interrupt line from timer to interrupt controller Hard disk interrupt not detected WD2riJlriJ controller (6C) 8259 interrupt controller (8H) Interrupt line from WD2riJlriJ to 8259 interrupt controller (8H) on file processor PCB Interrupt line driver (IriJC) on controller PCB Bard disk controller is busy and unable to accept a command WD2riJlriJ controller (6C) 5-86' Troubleshooting ~able 5~11. Test SDX Trouble Analysis (Cont.) Error Message [prObable cause File Processor and Controller PCBs (Cont. ) (35) File Processor Interrupt (Cont. ) SCSI status shows self diagnostic not complete SCSI interrupt not detected SCS I controller (IC) SCSI controller (IC) Interrupt line from SCSI controller to 8259 interrupt controller Interrupt latches and gates (4B and 25C) on file processor PCB Unable to test the tape interrupt logic Unable to perform read tape status command Floppy disk controller interrupt not detected Floppy disk controller ( 8C) Interrupt line to 8259 interrupt controller from file processor to controller PCB 8259 interrupt controller (8H) on file processor PCB DMA controller interrupt not detected 8259 interrupt controller (8H) DMA controller (2ID) DMA interrupt line Hot interrupt detected 8259 interrupt controller (8H) on file processor PCB Interrupt controller mask 8259 interrupt conregister verify error with troller (8H) on file processor PCB data = (00/FF) 5-87 Troubleshooting Table 5-18. SDX Trouble Analysis (Cont.) Test Error Message IprObable cause File Processor and Controller PCBs (Cont. ) (36) Ping- DNA controller operation Pong Buf- not complete fer Data miscompare on transfer from ping-pong buffer OMA controller (210) ping-pong buffer (70, 40, 50, 30, 20, 10,. 6B, 90, .9C, .60, .80, 8C, 7C, 8B, 13A, 120, 12C, 140, 2H, 130, 110, .11A, llC) OMA controller (210) DNA error (37) OMA Burst Logic OMA controller (210) OMA bus Burst (on/off) logic error Burst logic lCs (31B, 32B, 260) 8254 timer controller (25B) DNA controller operation not compl ete 5-88 OMA controller (210) Troubleshooting Debugger Tests The debugger test program is a development tool included in the monitor for troubleshooting user programs by allowing the user to single step a code segment and control execution by means of a breakpoint. A breakpoint allows the user to control execution by placing a software interrupt in the object code at locations specified by the user. The breakpoint transfers control to the debugger and allows the user to replace the original object code at any location and to view the current status. CPU Debugger Commands The CPU debugger commands are: A B C D F G H I L M o R S U W Z ? denotes a carriage return. • Upper or lower case letters are accepted. • All memory addresses are six hexadecimal digits long. • All Ilo addresses are four hexadecimal digits long. The CPU debugger commands are executed as follows: A Alter Memory This command allows the user to change the memory contents beginning with the given address. Syntax: a_xxxxxx_hh_hh_ •• _ •• a: xxxx: hh: . . ... B Al te r command Beginning memory address to be altered Hex byte val ues Up to 22 bytes at a time Display/Change/Clear Breakpoint This command allows the user to either view, change, or clear the current breakpoint address. 5-90 Troubleshooting Syntax: b b_xxxxxx bc bcl bc2 b: Breakpoint command xxxxxX: Breakpoint memory address C CPO Register Contents This command allows the user to either view or change current register contents. Syntax: c crr_hhhh cad_xxxxxx Display memory command xxxxxx: Beginning memory address to be displayed ~: 11: Byte count (module 16) For example: d_xxxxxx : Display one line (16 bytes) of memory data. d_xxxxxx_ff : Display one screen full of memory data. d_xxxxxx_ffff : This command displays the entire 65K bytes of memory data on a full-screen and pause. Pressing the spacebar will continue to display another full screen of memory data. However, entering any other keys will complete the command and return to the debugger. Also, the display will wrap around on the same segment. F Fill Memory Contents This command fills the memory contents starting at the given address with the given byte count. Syntax: f_xxxxxx_llll_hh f: xxxxxx: 1111: hh: Fill memory command Beginning memory address to be filled Byte count (0000=maximum of 64K bytes) Hex character 5-92 Troubleshooting G Go This command allows user to start executing program based on the values in the code segment (cs) and instruction pointer (ip) registers. Syntax: g B Go to SIO Monitor for Remote Downloading This command is for remote diagnostics. I Input Fram Port This command allows the user to read in the word value of the port, designated in the given address. Syntax: i: xxxx: Input port command Port address is_xxxx il c_xxxx ilf_xxxx L Remote Download This command is for remote diagnostics. M Move Memory This command moves memory data from a source to any destination in system memory. Syntax: m: xxxxxx_yyyyyy_zzzz 5-93 Troubleshooting o Output To Port This command allows the user to output a word value to the port designated by the given address. Syntax: 0: xxxx: yyyy: yy: Output port command I/O port address Word value to be written Byte value to be written os_xxxx_yy olc_xxxx_yyyy olf_xxxx_yyyy R