700121_Extension_Of_The_PDP 11_Instruction_Set 700121 Extension Of The PDP 11 Instruction Set

User Manual: 700121_Extension_Of_The_PDP-11_Instruction_Set

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\

PDP-K Technical Memoranda #~ 2
Title:

Extension of PDP-ll Instruction Set
•

Author (s) :

Ad van de Goor

Index Keys:

Instruction Sets
Opcode Space
Modes

Stack Operations
Distribution Keys:

K

Revision:

None

Obsolete:

None

Date:

21 January 1970

-1-

0.0

ABSTRACT
Scver~l

sot ore

methods of extending the PDP-Il instruction
di~cussed.
Coding comparisons are made.

Subject to the trivial weighting scheme used, two
solutions were excluded from further analysis
because of their poor performance. The "multiply/
divide" subsolution as discussed in sections 4.4
and 5e4 was the best performer.

-21.0

INTRODUCTJON
A more elaborate vers·ion of the PDP-l1/20 is
considered as a possible candidate-for the

PDP-K. It is felt that if the PDP-K is a
member of the PDP-Il family, sUbstantial
gains could be" obtained from:
1.1

upw-arda program compat.ibili ty

For DEC this would mean a lower total
software investment., and new machin.s
could be introduced mo~e easily as
present PDP-l! software would run on
PDp-x.

For customers this would mean that they
could move to a larger machine without
the direct need for reproqramming.
1.2

Peripheral compatrbility

only one line of peripheral devices" has
to be built. The introd~ction. of a
new machine could be done more easily
for thi. reason. Any new peripheral

device would b. available for the whole
f_l~y.

-3-

2.0

PROBLEMS IN ADAPTING TIlE PDP-ll ARCiITECTURE TO
BIGGER MACHINE

Au

~o

important problems of the PDP-ll have to be
sol ved in order to meet the PDP-I( requ:ir aments.

2.1

Limited number of instructions and Itmited
amoUilt of opcode apace left.

For the PDP-K

. three more class.. of instructions
conaidered:

are

2 .1.1. BAE ins truc:tiona , i .•. , rotate/

shift and multiply/divid~ for
16-bit word.~
2.1.2

Double Precision Integer

Ari~~c

Instruction••

2.2

Liaited Address

Spa~

The total amount of addre.sable core ....ory
on the PDP-ll/20 is 65K (l~ • i . 1024) bytes,
or 32K 16-bit words. Por a big 32-bi~
version of the. PDP-ll· this would only mean
l6l( 32-bit word. could be addr•••ed, which
is certainly not adequate for auch •
machill••

-4-

3.0

PUR~OSE OF MEMORANDUM

The purpose of this memol:;andum is to examine the
suggested methods -of solving the first problems:

extending the basic PDP-ll instruction set. An
acceptable solution. subject to several constraints,
will be sought.
3.1

program compatibility at
language level..

3.2

~oa.t

on the as.embly

•

in programming by .in~1zin9 ~.
number o£ instruction format. and restrictions
S~licity

imposed on inatructions •
. 3.3

3.4

opcode .pace left for future tlXpaftuion.
Opcod•• of the largest member of the family
have to fit ill the added iD.truction set. thus
miniaiziAq the Dumber of fOrllAta. and making
progr~nq

.a.ier.

-5-

4.0

POSSIBLE SOLUTIONS
If

_

....

Four possible solutions to the opcode space problem are
shown below. l~ey are followed by a discussion in
se\.~tion

4.1

5: o.

Implement new instructions as "pure stack"
instructions (i.e .. , zero address). Each new"
instrnction can

l'lOW

be specified with one

combination out of 216. This allows for hundreds
of new instructions. Any binary operation (like
multiply, diviae, etc.), would'take the ~o
operands from t.he top of the stack, and leave the

.,:-:

result on the top of the stack.

Register 6

would be used as the implied stack pointer.

4.2

Introduce a flag to indicate that the remainder
of the word contai.ninqthe flag (note: remainder
can be == 0) and the next word form a new
instruction. Depending on the length of the

flag. two cases exist. •

Inatruction
",.".,-_._""..,

[.,.::. . ==W~=~d=::~=:]
... ...,16-Bit Flag

4.2~2

.

1.....
- _-_-w=or_d-_-5=+=2=1
L

.....

Bar Instruction

Partial Word Plaq

...

.....

Flag

~New Instruction

iJ.'he advan'tage of thl.. technique ia that
t!wa 1l.8W' instn"Lctiona can have the SUie
aource-dest:ination forma~ as the stand41rd
(i ••• # currrent PDP-ll/20) # instructions.

-6-

The disadvantage .is that every new
instruction takes two words.

The

partial word flag case offers the
adva~tage of a greater number of
new instructions at the expense of
somewhat more complicated hardware.
4.3

Modes

mode is a (hardware) state of the processor
to allow instructions to be interpreted
differently. Basically two kinds of mod••
have to be recognized:
A

4.3.1

~ter

4.3.2

Enter mod•• for a specified number of
instruction. after which the mode is
switched back to the standard mode
autOlftatically.

and leave modes only with dedicated
commands (i .. e., only switch modes when
an instruction specifi.a to do 80).

The advantage ~of IROde8 i . that instructions
in any mode are only 1 word long. The
disadvantage is that .peeial inatructions have
to be given to enter. and in the ca•• of 4.3.1.
to leave the mode.
4.4

u•• R•••rved lIultiply!Divide Space
'these two opeode apac.. are not uaed in the
PDP-ll/20.

The to-be-added two-operand

instruction. can be implemented •• aourced •• tiAation instructions where the' .f:ack is
one implied operand, and the 8.econd operand
is .pacified with the full 6-bit dEtstinaticm
field ot the instruction. One of the.e 6
bits can be used .s a direction bit such that
operations can have either ~eir source or
destination as the implied stack. This allO\l's
for 32nf'!W instructions to be specified ..

-75.0

EVALUATION OF

PROPOS~p

SOLUTIONS

When e~aluating the proposed solutions, the irnplementatio:'l
of a 32-bit version of t.he POP-Ii should be included.. Fer
such a" machine. double-preci~ion floating point instruct:i:ons,
together with EAE instructions, operating on 32-bit
registers a.ce desirable, (assuming that these instructions
can operate on registers). This means that opcode space

for those instructions has to be regerved to provide for
their efficient operation.
Simplicity in programming and machine organization dictate
that the number of instruction formats for the three
classes of new instructions. (as discussed in section
2.1), should be minimal. In order to ~ake the extended
instruction set more acceptable, it is very desirable to
make the added instructions fit in currently existing
formats, or add at Most a single new format. Several
coding comparisons are done to assist in the evaluation,
The five problems below (Pl-PS), are considered
representative" The a ••umptions made in codinq the
problems can be deduced frca the listed code i.n Appendi.xes
A-D.
The variable. A, B. C, D and E are considered
single precision floating point (32-bit numbers).
P]: A"-B*C

P2:
P3:
P4:
P5:

Af
(B+C) * (J>+E)
A (i} .....a (i) *e (1')
A(i) ...B.(i+3) *C{i*5)
A (i, j)+-A (i. j) +8 (i.Jc.) *C (k, j)

/sillple case
ltemporary variable case
/aubscripted case
/mixed arithmetic (::ase
Imultl-d~en8~onal

array case
PS is an exaaple of the inner-loop 8tat.eraent of the
array mul tiplication:
~]...-1)1
* [cJ. l·t is a.swned
that the array bounds are declared frCD 0 to u. For

array B this would be: Real Array 8 (0 - bul, 0 - bti2) ."
The first index of IS 90es t.o bul. the second to bu2.
It will be •••umed that the index•• are in registers
R:L. Rj. and Rk.

Assuming'that the index•• i and j are in register Ri
and Rj, the value B (i. j) will be address as follows:
Location of B(i.j) :c location of B (i.e., starting
location of aatrix) + i*bul+j).

-8--

5.1

,;.

Pure Stack Operations

In order to make the pure stack operations efficient,
one of the opcode spaces reser"ed for lrtul tiply/d i vide
has to be used for a double move (MOVD' instructions.
MOVD:Move 2 words

(32 bit!')

from S (OU":cc) D (estination) .

Thia instruction is required especially in a 32-bit
machine. The one bina:cy op::ode .pat.;f! left can be
used to implement the EAE instructions. 1 Theinstruction format would be as foll'Ns:
OPERATION

DESTINATION

wI

3 (6 -:]

...."

3

3

......................___-""'f'"

RifGISTER

This saae format 1. uae4 for t).e JSR (IIUbroutine eall)
instruction. '!'be EAE instruc1.iona are made to o~rate
on regiat.er8 only.. The regist.er involved is
•
• peqifi~ by the 3 " reg iaterr.{ bib.

The value of the effective 4.id4r•• a of the ttd•• t.inat;ion
decerain•• the number of p:isitions to be shifted or
rotated~
Because the aute,·ina_ent and autodecrement mod•• do not; apply to these in.t.r1.l.ctions,
one of the 2 NOde bit. can b. u.ed to specify a
.ingle or caatbined operati.on, (1 .... " aea PDP-lO
LSH. LSHC, etc.). Ther.... ining .p"ea can be
used to implement in.truC1l;i0D8 like EXCHANGE,
REPEAT, etc.

Appendix A give. the coding axaaplea for the fiva
probl.... The handling of ault;.-d~n.ional arrays
i . very cwabersocae becau.. the nddre". computations
have to be done on the stack. Introducing a
aec:cm4 Nt of 16-blt IlNltiply/divicle instructions
iapl. . .nted aa the above EA.B ir..atructions will
solve thi. preble. at t:be expI:~.Cl of a BlOre complex
instruction •• t. SubcolUBl Tel'!; 1 MPD of Section
6 show. the iaprov.aent gained b~' thia ..

lExcept for 16-bit mult~ly/divid.

U

-9-

5.2

Fl199ed Instructions
Th~~

coding examples shown in Ap.Pf,-lndix B are the
same for alternativ£!s 4 . 2.1 and 4.2.2. 4.2.2 Is
proferable only if the additional opcode space is
neE!ded..
It is su99ttsted that tl'le EAE multiply/
divide instruction \1i11 be implel'lented in the
space "reserved" fo~c them. The EAE rotate/shift
ins'cructions have t f j be implemer ted as .t fla9ged u
instructions, the format would }:'. similar to that
dis~~ssed in section 5~1.1 eXCGlt for the f~ag.

The doUble precision integer an, floating point
inst.ructi
7.3

The. most p remising solution thi"i far is the
"multiply/div·id." subsolution.. It consistentl~l
scorad highest or second highest

-19-

APPENDIX A
PURE STACK CODING
EXAMPLES
.
.

pl:

'.

now

c, -

ItOVD

B. -

/move C to the stac:k
/fMlve B to the .tack
/floating .nltiply B*C
latore result in A

(SP)
(SP)

}'MUL

(SP) +,A

~OVD

P2:

}\.

....

---(SiC)

M(\1D

* (D+E)

8. -. (SP)
c, - (SP)

M(lD

/f19atiog add B+C

F}!)D

D,
(SP)
E, -(SPj

MelD
MO'D

/float.iDg add 0+.
/flo&t1ng lMIltiply (I>+E). (:a+e)

FAC
"1,

MOD
P3~

A(.i) ~-8
..
(1) *c (1)

MOV)
MOV)

C (Ri) .. B (R1), -

/a.~

(S')
(8P)

/110".

indeK i 1. in register ai

C(i) to the .tack

PMtl~

MOV)

P4:

...

+, A CRi)

(SP)

A(i, ~-B (1+3) *C (1*5)

Ri.a.

MOV
AD!>
M'J\'l'

*3.
Ra
8 (Ra).

MOV

Ai. -

MOV

.s~

-

/iadex
-

(I.)

(S.'

(IP)

lHUL
MOV

1+3 fOftle4

MOVD

(SP)+. RII
C(Ra). - (SP)

FMUL
MOVD

(SP)+, A(ai)

/caapu~e 1*5 .ad
OD top of af:ack

/st:ore renlt

1.... 1 word result

-20APPEND IX A (CONT • )

P5:

A(i, j)......- A{i, j) +8 (i,k) *C(k, j)

MOV
MOV
IMUL
MOV
ADD

--

Ri,
#bul.

(SP)

(SP) +,
Rk, Rs

(SP)

Ra

MOV

B(Rs), - (SP)
Rk. - (SP)

MOV

#cul,

MOVD

-

lMUL
MOO

ADD

R.i,

C(Rs)

MOV

(SP)

(SP) +, Rs

MOVD

FMUL
MOY

IRs contains index for array C

R8
I

a'"-, -

#aul,

lMUL

- (SP)
(SP)
(SP)

-

ADD

+, Ra
Rj, Rs

MOV'D

A(R8).

MOV

IRs contain. index for array B
/put B (i,k) on stack

(SP}

-.

/R- contain. index for array C
(5P)

FADD
MOW

(SP) +, A(Rs}

I.tore r ••ult

-21APP~IX

B

FLAGGED INSTRUCTIONS CODING EXAMPLES

PI:

A

~

MOVD

FMUL
p2:

FADD

B,A
C,A

MOVD

D, - (SP)

P5:

/A =- B+C now

FADD

c,

FMUL

(SP) +,A

(SP)

/top of the stack is C+D

A{i} .......
------B(i).C(i)

MOVD
FADD
P4:

/move B to A

B,A
C,A

A .....
- - - - - - ( B + C ) * (D+E)

MOVO

P3:

B*C

B(Ri), A(Ri)
C(Ri), A(Ri)

ACi) ......
------B(i+3)*C(i*5)

NOV

Ri,

ADD

*3, b

B(Ra), A(Rl)

NO"

MOL

Rt, Rs
*5, R.a

FMUL

C(Ra), A(Ri)

A(l, j) .......
----A(i. j)+ 8 (l,1tl

.a

MOV

al,

MUL
ADO

1IN1, ...

MOVD

B(R.). - (SP)

MOV

Jtlc. •••
#cul, Ita

alt. . .

FMUL
r«:JlI

Rj, R8
C (Ra), (SP)·
Iti. R8

NUL

kul, .a

ADD

Rj. R8
(8P) +, A(R8)",

PADD

•

IRa i . a acratch regiater

as

MOVD·

KUL
ADD

/move.B(i) to A(i)

/index for B (1+3) exaputed

*

C(k, j) ,

linda for .(i,k) ccaputed

/ index 10% C (k, j) COIIIp\lted

lineSex

-22-

APPENDIX C
MODE CODING EXPMPLES
pl:

A'"

R*C

/enter extended mode

EEM
B.A
C,A

MOVD

FMUL

/leave extended mode

LEM

p2:

A ..

(B+C)

* (D+E)
/enter extended mode

EEM
a,A
C,A

MOVD

FADD
MOVD

D" - (SP)
c, (SP)
(SP) +, A

!'ADD
PMUL
LEM
P:i:

A(1)

...

/leave extended 1BOd.
& (1)

*c (i)

BDI

1*4:

IIOVD

.(al), A(Ri)

!'MOt:..
LEN

e{ltl), A (Ili)

A(i) ...

B (i+3) *C(i*S)

MOV

Ri,Ra

ADD

.3,

RtI

£EM

. J«>VO
LEN
MOV
MOL
EEN
FMUL

LDl

.

p';,,' •

A(.i, j)

MOY
MOL

• (as) ,

A(Ri)

Ri, R8

*5"

.

R8

C(R.), A(Ril'
ACi, j) + Bti,x)

*bul, b

Rk, ••.

MOVO

BCRa), -

LEN
MUL
ADD

Rk. RII
*<:aI, b

B (i,k)

/index for

C (k, j) coaputed

c01I.pUted

-

Itj, b
C(RS)~

lindex for
(SP)
•

EDt
F'r.1UL

C(k,j)

-Ri, b

ADD
£EM

MaV

*

(SP)

-23AVPENDIX C
MODE CODING

P5:

EX~lPLES

Cont.
LEM
MOV
MUL
ADD

Ri, Rs
#aul, Rs
Rj, Rs

EEM
FADD

(s P) + ,

LEM

/index for A(i,j) computed
A ( Rs )

. T'

pi:

A ....... -

.-

~10\''D

R, - (SP)

""~ove

FMUL

c,

/multiply c with t0P of t::e
,/move result to A

A

.....

MOVD

B,-(SP)

FADD

c,

MOVl)

D,-eSP)
L, (SP)
(Sr·') +, (SP)

MOVD
A

(i~ . - -

(:;p~

+,1\

B (i)

*

C (i)

-

t-10VD

A{i) ....

SCi"'3) + C(i* 5)

MOV

Hi, Rs
:: 3, Rs
B(Rs), - (SP)

FMUL

AD;)
MOVV

/index i+) in Rs

~'1()V

Ri,

- (SP)

I~~t;L

;t5,

(SP)

~·~C-J

(SP) +, Rs
C (Rs) , (SP~
(SP) +, A (Ri)

/index i*5 in Rs

.l\{i,j) + B(i,k)

'*

F~~;

rr

.J-,-"

r-tOVD

P5:

(SP)

B (Ri) ,
(SP)
C (Ri) , (SP)
(SP) +" A (Ri)

MOVD

P4:

B to the sta·~k

(B+C) * (D+E)

FADD
FMUL
p3:

(~~P)

(SP)+,A

MOVD

p2:

~~*C

A{i, j) .....

-

-

MOV

Ri,

11-ruL

~ibul,

(SP)
( SP)

Me)V

(S p) +,

ADD

Rk, Rs

MOVD
MOV

(SP)
B{Rs),
Rk.,
(SP)

lMUL
MOV

~cul,

ADD

Rj, Ps
C(Rs), (SP)
Ri,
(SP)

FMUL
MO\t

IMUL
MOV
ADD

FADD
MOV'!)

-

C',k,j)

Rs

/index f.or B(i,1<) comput(';!d

-

{SPj

(SP)-+-, Rs

/index for C(k,j' computed

-

~nulk

(SP)
(SP) +,Rs

Rj, Rs
A(Rs), (SP)
(5 P) 4o, A(Rs)

,Jindex for A (i., j) computed

:~t(L·".



---

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