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Sun-2/50
Field Service Manual
Sun
~l1crosystems,
Inc.
•
2550 Garcia Avenue
•
Mountain View, CA 94043
•
415-960-130Cl
SO of 31 October 195-i
Pan Number 800-1111-01
Copyright C 1984 by Sun Microsystems.
This publication is protected by Federal Copyright Law. with all rights reserved. No part of this publication may be
reproduced. stored in a retrieval system. translated. transcribed. or transmitted. in any fonn. or by any means manual,
electric. electronic. electro-magnetic, mechanical, cheJI)ical, optical, or otherwise. without prior explicit written permission from Sun Microsystems.
Contents
Preface _______________._______________.____...._.........___.................
iv
Chapter 1 Theory of Operations .... ____ ....................................................................
3
1.1. Printed Circuit Boards ..................................................................................................
1.2. Monitor ..................................................................................................................................
1.3. Power Supply .... _..............................................................................................................
4
31
Chapter 2 Diagnostics and Troubleshooting ........................................................
35
2.1. Overview ..........................................._................................................................................
2.2. S)111ptom Analysis ..........................................................................................................
2.3. Observing the Startup Procedure ............................................................................
35
36
37
2.4. PROM Diagnostics (PDlAG) ...................................................................................
2.5. Standalone Programs .....................................................................................................
2.6. Quick Reference Troubleshooting Guide ..................................._....................
42
51
52
Chapter 3 Maintenance ........................................................................................................
55
3.1.
3.2.
3.3.
3.4.
Printed Circuit Board Removal ........ _....................................................................
31
Monitor Removal from Chassis .-........................................-......... __.................
Olassis Cover Removal ..._______................................................ _....................
RFI Shield Removal ....................___ ...._._........_..................._ ...... _...... __.........
56
59
61
62
3.5. Power Supply Removal ................................................. __ ..........................................
63
3.6. Cooling Fan Removal ............................._...._..............................................................
3.7. Backplane Removal ..........._..........._._ ........................ _........................ __..................
6~
65
3.8. Miscellaneous Pans Removal ..........................................................._..................
65
Contents - Continued
Appendix A Glossary of Sun Terms .__... ______ ............................................
77
Appendix B Printed Circuit Board Layouts ..... _................................................:.
83
Appendix C Printed Circuit Board Connector Pinouts ._..~ ___....__ ........
89
Appendix D Select Jumper Options __________.__...__..____...... _ ........_...
93
Appendix E Manufacturer's Component Data ._______._...... __......__ ..
99
Appendix F RS-423 P-Diag Jumper Pinout .........................._.............................. 107
Appendix G Ethernet Cable Connections ............................................................... 111
Appendix H MUX Box Specification ........................................................................ 115
H.1. Installation Requirements ...............................-.........................................................
116
H.2. r-.flJX Box (2110) Installation .................................................................................
116
H.3. 2110-BO Module Installation ...................................................................................
117
H.4. 211O-A0/211O-BO Module Operation .................................................................
117
H.S. Specifications ....................................................................................................................
118
Appendix I Vampire Transceiver Box Installation .................................. ;....... 121
1.1. Tools and Equipment Required ................................................................................
122
1.2. Transceiver Installation .................................................................................................
122
Index .............................................................._......................................................................................
127
Preface
The Sun-2/Sa is a microprocessor-based workstation. capable of operating
stand-alone or as pan of a local area network. Offering IMbyte of dynamic
memory in its standard configuration. the Sun-2/S0 may be expanded to a maximum of 4Mbytes with the addition of one of several memory expansion boards.
Memory architecture. based on the concepts of vinual memory. provides access
to significantly greater amounts of data storage than is resident on the workstation itself; while integral Ethernet. RS-423 and VME bus interfaces supply data
links to a number of systems environments.
The information presented in this manual is designed to give the reader some
insight into the workings of Sun-2/Sa logic. provide assistance in troubleshooting
problems and, finally, offer step-by-step procedures for the removal and replacement of system components. Figure 1-1 provides an overview of the Sun-2/50 in
a typical system environment.
Preface - Continued
2/170
FILE
SERVER
2/50
2/&0
son
Figure 0-1
Sun-2150 System Overview
son
Preface - Continued
Assumptions About Reader
Knowledge
In presenting the infonnation contained in this manual. it is assumed that the
reader is familiar with TIl.. and EQ..logic. and with the Motorola MC68010
Microprocessor. The reader should also have a working knowledge of Local Area
Networks, Sun-2 vinual memory management architecture and the VME bus
specification.
List of Applicable Documents
This list provides additional sources of infonnation to be used in conjunction
with the Sun-2/S0 Service Manual.
- Motorola MC68010 Databook (Motorola PIN ADI 942)
- Hardware Installation Manual for the
Sun-USO Desktop SunStation
(Sun PIN 800-1143-01)
- VMEbus Specification Manual (VME Manufacturers
Group, Rev. B.Aug. 1982)
- Monitenn Monitor Service Manual for the
Sun-2 Family of Workstations (Sun PIN
800-1147-01)
- Philips Electronics Ltd.
Video Display Products
Service/Operator Manual
19" Video Display Unit Model: M19P114A1S102
- System Managers Manual for the Sun WorkstationModels 120/170 (Sun PIN 8QO..ll1 0-01)
- RS 423 Interface Specification
- System Release 1.1. Rev. C. release date 3-12-84
- 1.3 Manual for the Sun Workstation (Sun PIN
800-1159-01)
Figures
Figure 0-1 Sun-USO System Overview _...... _ ................................. _.............................
v
Figure 1-1 Sun-2/50 Circuit OvelView ... _........................................................................
5
Figure 1·2 CPU Logic ........ _....................................._..............................................................
5
Figure 1·3 Power-on!Reset Logic ........................................................................................
6
Figure 1-4 Clock Circuits ......................................................................._................................
8
Figure 1·5 Data Transfer and Bus Error Logic ............................................................
10
Figure 1·6 Sun·2/50 Bus Architecture ..............................................................................
11
Fi gure 1·7 I/O Data Bus ...._................................................................_._._.............................
14
Figure 1·8 Video Logic ..............................................................................................................
15
Figure 1·9
~U
Logic ........................................._..................................................................
20
Figure 1·10 Sun·2 Memory Management .......................................................................
21
Figure 1-11 Memory Address Decode Logic ..............._...............................................
22
Figure 1·12 DVMA Control Logic ..._................................................................................
23
Figure 1·13 DVMA Memory Refresh Logic _._............................................................
24
Figure 1·14 Serial Communications Logic _.................................................................
. Figure 1-15 .Ethernet Interface logic ___......__ ....__......... _ ...___._....___ ..............
25
27
Figure 1-16 VME Bus Data Transfer Sequence -_ ..._.........._ ......_..........._..._........
30
Figure 3·1 Rear Panel Securing Screws .............................-......................_._.................
57
Figure 3·2 Releasing Backplane Connectors ............................. _ ..._ .................. _......
58
Figure 3·3 Removing Rear Panel Assembly from Chassis ...................................
59
Figure 3-4 Monitor Mounting ..........__ ..............._ ........._ ......... _ ......._... __..................
60
Figure 3·5 Positioning Monitor for Removal ................................................................
61
fi~ures -
Continued
Figure 3-6 OWsis Cover Removal .____._____...________.........__......... _
62
Figure 3-7 RFl Shield Removal ..._____.__._________...._......____ ...__..
63
Figure 3-8 Power Supply Removal .._. ___...___....____........._ .........._.__.__.........
Figure 3-9 Backplane Removal ____________ ... ______._..
64
65
Figure 3-10 Sun-USO IDustrated Pans Breakdown .______._...______........
66
Figure 3-11 Sun-USO IDustrated Pans Breakdown _____._...______ .....
67
Figure 3-12 Sun-USO IDustrated Pans Breakdown ______..._______ .....
68
Figure 3-13 Sun-2/50 IDustrated Pans Breakdown .______.................._...........
69
Figure 3-14 Sun-USO IDustrated Pans Breakdown ._____ ... _ .........___...._..
70
Figure 3-1S Sun-USO IDustrated Pans Breakdown ._....................................... _......
71
Figure 3-16 Sun-USO IDustrated Pans Breakdown ...................................................
72
Figure 3-17 Sun-2/50 illustrated Pans Breakdown ........_................_.......................
73
Figure 3-18 Sun-2/S0 illustrated Pans Breakdown ...................................................
74
Figure H-I Network Configurations ...................................................................................
116
Figure I-I Tap Block ........_ ....................................................... _...............................................
122
Figure 1-2 Shim Placement ......._.............................................................................................
123
Figure 1-3 Transceiver Installation ......................................................................................
124
Figure 1-4 TCL Coring Tool Kit ......_............_......._ ............._............................................
12S
(
1
Theory of Operations
Theory of Operations ... __ ............__ ...__ ......... _...... __.................._............__.____ ..
3
1.1. Printed Circuit Boards ........................ _.............. _........................................................
4
CPU Logic .........:..............................................................................................................
4
Microprocessor .........................................................................................................
4
Pov..er-OnlReset Logic .........................................................................................
5
Boot PROMs ..............................................................................................................
7
Function Code PAL ...............................................................................................
7
Clo.::k Circuits ............................................................................................................
7
InteITUpt Logic ..........................................................................................................
8
ID PRO!o.1 ................................................................................................._.................
9
Processor B us Errors .............................................................................................
9
Data Transfers ..................................................._ ................................._.................
10
Address Error Cycle ...............................................................................................
10
Bus Architecture ............................................................................................................
11
Processor Data and Address Buses ....... _.....................................................
11
1/0 Data Bus ................... __...............................___.....................____...........
12
Memory (P2) Bus ............................................_................................._.................
12
Parity Error Logic .........._ ........._ .................. __............ _...................................
13
Video Logic .....................................................................................................................
15
Video Memory and Address Decoding ........................................................
15
Video Memory Controller .........................._............................___.................
16
Video Sync Control Circuitry ..........................................................................
16
Video Shift Logic ......................... ..........................................................................
16
Video Interface to the Memory (P2) Bus ..._............._............... _._.........
17
Video Write Cycles .......... _............................ _.......__......._...._...........................
Video Read Cycles ........................................................___ .........________
17
17
Video Refresh Cycle .....__.............................. _............ __......_......... _...........
17
Video to Memory (P2) Bus Data Transfers ..............................................
Interrupts ______...__......_..._ ......_____.________
18
18
Memory ..__..........._...... _..........__......... _..__.........._._. ____................__.___...__
Overview of Sun·2 Memory Architecture .___________..
Memory Management Unit (MMU) ........_______________........
19
19
Main Memory ............................................__............._...__ ......_....... ___...........
Direct Virtual Memory Acces$ (DVMA) ............____.......__..._...._..
21
22
Interface Logic ......._.........__..._..._.............._...................................._......_...........
25
Serial Communications ................................... _...................................................
Ethernet Interface ..................................................._......._..........................._........
25
26
Ethernet D\'~1A Cycle .........................................................................................
V}t.1E (PI) Bus Interface ......................................................................................
\'It.1E Bus Arbitration and Request Logic .................................................
V}t.1E Master Interface ..........................................................................................
27
\'It.1E Slave Interface .............................................................................................
29
V}t.1E Interrupt Control .........................................................................................
30
1.2. }"1onitor ..................................................................................................................................
31
1.3. Po\\'er Supply .....................................................................................................................
31
Vid~
19
28
28
29
1
Theory of Operations
This section offers a brief operational overview of the Sun-2/S0 SunStation. For
the purpose of this overview, all Sun-2/S0 components will be separated into
three functional groupings: printed circuit boards (CPU board and optional
Memory Expansion board), the monitor and the power supply.
3
SO of 31 October 1984
4
Sun·2!50 Field Service Manual
1.1. Printed Circuit Boards
A single CPU board contains all of the logic necessary to operate the Sun-2/s0 in
its standard configuration. Memory capabilities may be enhanced with the addition of the optional Memory Expansion board.
The following logic description applies primarily to the CPU board. Information
pertaining to the Memory Expansion board is contained in the section titled
"Main Memory". 1be logic resident on both circuit boards is represented by the
functional block diagram in Figure 1-2.
CPU board logic may be separated into the following functional blocks: CPU
logic. Video Control circuitry. Memory and Interface logic. Each of these blocks,
as well as the interconnecting bus architecture. will be described in the following
paragraphs.
CPU Logic
The CPU logic block consists of the microprocessor and the following associated
circuitry (refer to Figure 1-3 for a functional block diagram supporting this
logic):
•
•
•
•
•
•
•
Microprocessor
Power-On/Reset Logic
Clock Circuitry
Interrupt Logic
BootPROMs
JDPROM
Function Code PAL
Bus and Address Error Logic
The CPU logic is designed around the Motorola 68010 microprocessor. The
68010 is a 16-bit, virtual memory microprocessor with an asynchronous bus
structure supporting 24-bit addresses and 16-bit data words. Refer to Appendix E
for pinouts and signal definitions for the 68010.
500[31 October 1984
Chapta' 1 - Theory of Operations
5
CPU
Figure 1-1
Sun-2150 Circuit Overview
IlITtRRVPT
LOCIC
Lo:;rc
POlitR-ON/I-_ _ _1
R.£S£T
LOCIC
tRROR
LOCIC
Figure 1-2
Power-OnlReset Logic
CODE
PAl..
l=======~
CPU Logic
The power-on/reset logic provide a means of starting a processor and/or system
initialization sequence. This sequence is initiated in response to fluctuations in
the supply Voltage. a reset signal from an external bus. or a halt in a CPU processing cycle.
Microprocessor reset signals are generated by the PAL at U 102 as the result of a
power-on reset. an external reset. or a watchdog reset (refer to Appendix A).
Inputs to the PAL are provided by the power-on reset generator (POR). the VME
SO onl October 1984
6
Sun·2/50 Field Service Manual
bus (SYSR) and the 68010 (HALT).
Initialization and power-on-reset pulses are supplied by a power-onlpower-off
reset generator. This generator is composed of a dual comparator (UI33), reference voltage diode (0101), charge capacitor (KlOO) and resistor nctworlc (RlOO107).
The comparator acting as the power-on reset generator compares the voltage
from the charge capacitor with the +1.2V reference voltage provided by the
diode. The comparator will assen its output until the capacitor voltage reaches
+4.SV.
The comparator acting as the power-off reset generator compares the +S.OV supply voltage with the +1.2V reference. The comparator output will be assened
when the +S.OV supply voltage drops below a threshold value of +4.SV.
The comparator outputs are combined to produce a power-on-reset (POR) signal
when either comparator output is assened.
An external reset will be generated when the Sun-2/50 is configured as a "reset
slave" and a VME system reset (SYSR) is received. Both POR and SYSR are
ORed at UI08 and input to the PAL as PORI.
A watchdog reset is generated when the microprocessor stops during a nonnal
cycle and asserts the HALT signal. The PAL will respond by assening RESET to
continue the processing cycle.
Refer to Figure 1-4 for a functional block diagram supporting the Power-Onl
Reset logiC.
POIlER-ON
/PO\rt.R-Off
COI'.PARATOR
(lII33)
-
r---11
POR
-
~
\1108
R~~
PAL
RES!:'!'
CP'U
(lII00)
(lII02)
. SYSR
Figure 1-3
Power-on/Reser Logic
50 of 31 October 1984
CMpter 1 -Theory of Opcraticms
Boot PROMs
7
The boot code used by the CPU during reset. "boot state" and nonnal code- fetch
cycles is stored in two 16.384 word by 8-bit PROMs. These PROMs
(USOO.USOl) are addressed directly with the low-order address bits from the
CPU (AOI-14). Both PROMs are constantly chip-enabled and their outputs are
controlled by an output enable signal (OE.PROM) from the PAL at UI01.
Function Code PAL
The PAL at UIOI controls a number of processes which are designated as "spedal cycles" (refer to Appendix A). Special cycles are operations in which the
68010 function code is neither program DOr data. Examples of special cycles are
CPU and MMU space cycles and boot PROM read cycles. The PAL receives
function code data (p.FCO-2) from the 68010 which indicates the state (user or
supervisor) and the cycle type cumntly being executed.
Clock Circuits
The clock logic provides the timing necessary for internal data processing and for
communication with external devices; such as the Ethernet. keyboard. mouse and
monitor.
All system clocks are derived from four independent oscillators. located on the
CPU board. The output of the 19.6608MHz oscillator (U200) is divided by two,
producing a lOMHz clock for the CPU (UlOO) and for the DVMA Request! Arbitration machine (U213-) S). These clocks are funher divided to supply .
4.9152MHz timing pulses to the Interrupt Request Timer (US04) and to the
Serial Communications Controllers (U600/U60l).
The 16.0000MHz oscillator (U202) is used to produce 8MHz timing pulses for
the Ethernet Controller (U700). as well as providing a system clock to the VME
bus.
The l00.0000MHz oscillator at Ul800 supplies clock pulses to the video shift
circuit (U1807-8).
The output of the 24.0000MHz oscillator (U20l) is divided by two to produce a
12MHz clock designed for special applications.
Refer to Figure 1-5 for a functional block diagram representing the Oock logic.
SO of 31 October 1984
8
Sun-2/S0 Field Service Manual
011
(V. . .)
_-.urI
...---------..,r-------W"OU"
t---------t--------TIII':".'"
11 'Utr
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _
2400001CH~
os:
("'''l
Figure 1-4
;)tcrrupr Logic
H
":.:.s:;.:;~J.::.;.._
_ _ _ _ _ _ _ _ _ _ nIt
IUS
12POt2
J.....-_ _ _....I
Clock Circuits
The Sun-2/S0 interrupt logic provides a means of prioritizing requests for processor attention from both internal and extemallogic groups.
The interrupt logic consists of a timer at US04 and an interrupt PROM at UI 05.
The timer provides five 16-bit counters for the main logic board and is driven by
a 4.9152MHz clock pulse derived from the 19.6608MHz oscillator at U200. Processor address bit AOl selects the count source and the read and write strobes are
supplied by the read/write decoders at U401 and U402 respectively. The timer
outputs a level 7 interrupt request (IRQ7) and four level 5 interrupt requests
(IRQ5).
50 of31 October 1984
9
Chapter 1 - Theory of Operations
The interrupt PROM receives inputs from the timer (JRQS, IRQ7), from the bus
error logic (EN.lNTl-3), from the video controller logic (V .IRQ-), from the ethernet controller (E.IRQ) and from the Serial Communications Controllers
(JRQ6·).
The interrupt PROM outputs three interrupt control signals to the microprocessor
(IPLO-2-), which contain the encoded priority level of the device requesting the
interrupt. Level 7 is the highest priority interrupt and cannot be masked. Interrupt
levels are defined as follows:
~el
7
6
5
4
3
1,2,3
IDPROM
AI~ng
NMI (Non Maskable Interrupt)
Serial Communications Controllers
Interrupt Timer
Video
Ethernet
INT
The ID PROM (US 10) contains basic infonnation on the type and configuration
of the Sun·2/50 in which it is installed. This infonnation includes the serial
number of the CPU board, the machine Ethernet address and the specific impJe.
mentation of Sun-2 architecture used. Refer to Appendix A for a listing of the ID
PROM contents.
If the original CPU board is removed and a replacement board installed. the ID
PROM from the original board must be reinstalled on the new board.
Processor Bus Errors
A bus error (BERR) signal to the microprocessor indicates that a problem exists
with the data transfer currently being executed. A bus error may be caused by
page or protection errors in the Memory Management Unit (refer to Appendix
A), parity errors, VMEbus errors, or a timeout.
.The eight signals used to generate a bus error are ANDed together at U130. The
output of this register (ERROR), when assened, provides disable lines for the
read/write strobe decoder (U400) and for the 1/0 decoder (U403). ERROR is
also presented to the PAL at UI03, which then generates the signals BERR,
BERRCLK and PARCLK.
BERR is the processor bus error signal. BERRCLK latches the error condition
into the bus error register at U511. PARCLR clears the parity error registers at
U424, in the event that they were set. Refer to Figure 1-6 for a functional block
diagram illustrating the bus error logic.
500(31 October
19~
10
Sun·2JSO Field Service Manual
The CPU uses a number of handshake signals to generate the timing required by
the devices it is accessing. Upon completion of any data transfer cycle, a data
transfer acknowledge signal (DTACK) is presented to the CPU by an eight -toone multiplexer at Ul18.lnputs to the multiplexer are provided by PALs at UI01
and UI06.
Data Transfers
When the CPU receives DTACK during a read cycle, the data is latc:hed one
clock cycle later and the bus cycle is terminated. When DTACK is received duringa write cycle. the write strobes are deassened and the bus cycle is terminated.
Devices requesting the bus from the CPU assert the signal Bus Request (BO).
The CPU relinguishes the bus with the signal Bus Grant (BG). Refer to Figure
1-6 for a functional block diagram of the data transfer logic and to Appendix E
for CPU signal definitions.
Address Error Cycle
An address error cycle is handled by the CPU much like an internally generated
bus error. The address strobe (AS) is assened and a normal cycle is executed. but
no data is transferred because neither of the data strobes (UDS.LDS) are assened.
Note that the statistic bits in the Memory Management Unit (M.MU) are still
updated during this cycle (see the section describing the MMt:).
'AC
If...
(Ulel,
106)
'A:.
C7II
(UIOO)
,[:u
(VICl)
0;':-
r}t-,
:,~
.-
",
I
:1
IV: OIAO:
lib''''
STa:.£
c£:e:[l
(lJ4:0)
~::
D.o~
etI\lC\J<
lEO
MU)
_at;
tlO
_=0
PAI:n
(U40")
(U.,.,
Figure 1·5
'MCLA
Data Transfer and Bus Error Logic
SO of 31 OclOber 1984
Chapter 1 - 'I'heClry of Operations
11
Sun-2/S0 bus architecture supports a number of serial interfaces, as well as direct
vinual memory access (DVMA) of the VMEbus by either the CPU or the Ethernet controller. The internal buses include the processor data and address buses,
the memory data and address buses. and the VO data bus. The VME bus is
described in the Interface Loaic section. Refer to Fiawe 1·7 for an overview of
the Sun·2/S0 bus architecture•
Bus Architecture
• 10.,_,.::1:
P2 DA':'"
e.::
II CJ':'
I.IM
Figure 1-6
Processor'Data and Address
Buses
Sun-2150 Bus Architecture
The 68010 utilizes a 23-bit address bus (p.AOl-23) to provide addresses to the
Memory Management Unit (MMU), the boot PROMs, the VME bus interface
and to the Ethernet interface. Addresses transmitted to main, video and expansion memory are sent via the P2 bus.
The processor data bus (p.DOO-IS) is connected to the I/O data bus OO.DOO-15)
through a pair of bidirectional transceivers at U 110 and UIII. All on-board dat:l
transfers, with the exception of infonnation se~t to the parity error logic, are carried out on the I/O data bus.
.
Data transmitted between the CPU board and the optional memory expansion
board is seen as P.DOO-15 by the CPU and as P2.DOO-IS by the memory.
~~~,.,n
so of 31 October 1984
1~
Sun-2150 Field Service Manual
The I/O data bus (10.000-15) provides a data path between the CPU and the
MMU. the VME bus data pon and all input/output devices. The I/O devices serviced by this bus include the boot PROMs (USOO,USOl). the Ethernet control
logic (U700,U716.U717), the interrupt timer (U504) as well as the
keyboardlmouse and RS-423 interfaces (U600 and U601 respectively). Refer to
Figure 1-8 for a functional block diagram of the I/O data bus.
1/0 Data Bus
Individual I/O devices are selected by a comparator at U403. The comparator. in
conjunction with the AND gate at U433. produces the chip enable signal
"CE.lO-". This signal is presented to the bus decoder (U400) and to the
read/write decoders (U40t.U402) which then decode mapped address lines to
select one of eight possible devices.
Processor data is placed on the I/O data bus via the transceivers at UIIO and
UttI. These transceivers receive readlwrite strobes from the PAL at UI02.
The I/O data bus is driven by the processor data bus on all processor-write and
DVMA read-cycles. The processor data bus is driven by the I/O data bus during
all DVMA-write and processor-read cycles generated by the I/O devices, the
MMU and the VME bus.
Memory
~)
Bus
The P2 bus allows addresses and data to be transferred between the CPU and the
main memory, video memory and the optional expansion memory. The P2 bus
consists of address lines (p2.AOO-23). bidirectional data lines (P2.DOO-15) and
miscellaneous control signals. The memory control signals include the row
address strobes (RAS. RASa. RASl). the column address strobe (CAS), the read
strobe (RD) and the write strobes (WEL,WEU).
RAS is assened when the processor address strobe and clock are both active.
This is the case when the processor has reached a specified state. Once RAS has
been asserted. it is latched until a later specified state or until the address strobe is
deassened.
CAS is assened at a specified processor state on non-special cycles only. During
a special cycle (refer to Appendix A), CAS is inhibited by the signal SPECIAL.
The column address is inhibited because. during memory management updates. it
is not guaremeed to be stable and could result in invalid memory decoding.
The write strobes (WEL,WEU) are the product of the memory write signal
(P2. WR -) from the decoder at U400. and the upper and lower data strobes
(LDS,UDS). The write strobes are asserted with a specified processor state and
while the data strobe (DS-) is active. The write strobes are turned off when LDS
and UDS are deassened.
P2 bus access is controlled by the decoder at U400. A read or write reference to
the P2 bus is generated when the following conditions are met: the page type
field is 0 or 1 (refer to the description of the MMU logic), the data strobe is
assened. the specified processor state is assened and no bus error conditions
exist.
During a memory bus read-modify-write cycle. the processor address strobe. as
well as the row and column address strobes. are assened for the entire cycle.
50 of 31 OclOber 1984
13
Chapter 1 - Theory of Operations
Both RAS and CAS are assened before the page map type field is decoded by
U400 and before the protection field is evaluated. As a result. CAS will indicate a
valid address. but not necessarily a valid reference. The read/ write strobes
(RD.WEL.WEU) qualify the reference.
Parity Error Logic
The parity error logic generates and checks parity during ~wtite cycles to
main or expansion memory. This logic is not used during any other bus cycle and
is not used during read/write cycles to the video memory.
Odd parity is generated. during memory write cycles. by the parity generators at
U420 and U421. Inputs to these genemol'S are supplied by the processor data bus
(p.DOO-lS) and by the system enable register at US12 (EN PARGEN).
Parity is monitored during read operations by the parity checkers at U422 and
U423. A parity error (even parity) results in the assenion of the EVEN output
from one or both of the checkers. These signals are clocked into a pair of parity
error flipflops (U424) during the memory read cycle. which in tum generate the
parity error signals PARERRU- and PARERRL-.
The parity error signals are ORed at U130 with other error conditions to produce
ERROR. which is used by the PAL at U103 to assen a bus error state (BERR) to
the processor.
Parity errors. unlike other bus errors. cannot abort the current CPU cycle.
Because a parity error can only be detected at the end of the read cycle. its
existence is not recognized by the processor in time to abort the cycle. The parity
error logic provides a means of retaining the error state until it can be recognized
by the processor.
In order to ackowledge a bus error (caused by a pending parity error). the CPU
must execute a non-special cycle. During this cycle. the PAL at U103 will assen
the signal BERRQK. which clocks the parity error state into the parity error
register at U511. PARCLR is also assened by the PAL to clear the parity error
ftipflops at U424.
SOof31 October
19~
14
Sun·21S0 Field Service Manual
-Figure 1-7
110 Data Bus
SO of 31 October 1984
Chaptet 1 -
Theory of Operations
15
The video logic consists of 128K bytes of memory. the memory controller. the
video sync control circuitry. address decode logic. memory (P2) bus interface
logic and the video shifter. Figure 1-9 provides a functional block diagram illustrating the video logic .
Video Logic
..
".,
..-",::
.,,--
(V _ _ •
II
tD Jr.ftJ'foa
lU,a.,)
v::t:
£-:, ..
s.. • .. :
tt,,-;: ..
U)C;::
(VII04'"
p..,.
att;:r.o
....
C:Ch";l:;_
(Vln4)
Figure 1-8
Video Memory and Address
Decoding
tUIIJO)
Video Logic
Video memory (U1700-1707. U1710-1717) is located on the CPU board and is
configured as 16K words of 64 bits each. The memory is dual ported to allow
access by both the processor and the video refresh logic. Processor update cycles
read 16 bits at a time. and write either 8 or 16 bits. Video refresh cycles read 64
bits at a time.
Processor cycle addresses are transmitted via the P2 bus. with the incoming row
and column addresses stored in registers at U1632 and U1633 respectively. The
video cycle addresses are generated by address counters at U1630 and U163 J,
and input to a pair ofregisters at Ul640 and Ul641. During video refresh, the
address counters are incremented every 640nsec with an output enable Signal
from the decoder at Ul728. The refresh counters are reset with the signal V
RESET. generated by the video controller register at U1812.
Data is transmitted between the video memory and the P2 bus by the bidirectional bus transceivers at U1730-1737. Outgoing data, to the video shift logic, is
latched by registers U 1720-1727.
SO of 3 J October
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16
Sun·2/50 Field Service Manual
Video Memory Controller
The video memory controller supplies timing pulses to the memory and its associated logic. The memory controller is a state machine consisting of two PROMs
(U1604. Ul605) and a pair of registers (U1606. Ul607). The state machine has a
total of 16 states (STATE 0-15). which are continuously executed in sequence.
Each state has a duration of 4Onsec. making the entire 16-state sequence 640nsec
long. Timing for this control logic is provided by clock pulses derived from the
lOOMHz oscillator at Ul800.
The memory controller is capable of executing three typeS of cycles: idle. processor update and video refresh (refer to Appendix A). Idle and processor update
cycles are executed in the first eight states; the refresh cycle is executed in the
last eight. If no memory requests are pending, the memory controller will execute
idle cycles. During these cycles no memory control signals are asserted.
A synchronous request (V SREQ). output from the request flipftops at U1624.
causes the memory controller to execute a processor update cycle. During this
cycle. the controller outputs the enable signals PRA and PCA to the row and
column address registers (U1632. UI633). These signals ensure that both address
registers are enabled in time for the video row and column address strobes
(V.RAS. V.CAS).
Video Sync Control Circuitry
The video sync control circuitry is composed of the horizontal and venical state
machines (U181O-1811 and UI813-1815 respectively) and the video controller
latch (U1812). This logic generates horizontal and venical sync signals for use
by the video monitor.
The horizontal counter at U 1810 is incremented every 64Onsec. on the falling
edge of the memory controller signal V.HCLK. Counter outputs are presented to
the horizontal decode PROM at U1811. along with VBLM'K from the venical
state machine. The decode PROM generates the control signals horizontal clear
(V.HCLR). horizontal sync (V.HSYNC) and display enable (V.DISPEN).
V.HCLR provides a reset signal to the counter at U1810. V.HSYNC is used to
clock the venical state machine. V.DISPEK is sent to the video shift logic.
The venical counter (U1813. U1814) is incremented on the falling edge ofhorizontal sync (V.HSYNC). Counter outputs are presented to the venica] decode
PROM at U1815. which decodes the counter Slates to produce the signals V.VO3. These. signals are latched by the video controller latch (U1812) and output as
vertical sync (V.SYNC). video clear (V.CLR). vertical blank (V.VBLMl]() an':
video reset (V.RESET).
\'iJco Shift Logic
The video shift ]ogic is composed of a pair of 50MHz shift registers (U 1805.
U1806), a TIL-to-ECL convener (VI 807) and a lOOMhz shift register (UI809),
Video data (V.DOD-07) is output from the video memory. via registers at U17201727. and loaded into the shift registers at U 1805 and U 1806. These registers
shift out the even (U180S) and odd (UI806) bits. outputting them as V.VIDO and
V.VIDI respectively. Each pair of even and odd bits. together with IOnsec and
20nsec clock pulses (derived from the lOOMHz oscillator at U1800). is loaded
into the ITL-to-ECL convener at U 1807. This convener outputs both true and
invened EeL data to the shift register at U1809. The shifted differential outputs
SO of 31 OclOber 1984
Chapter 1 - Theory of Operations
17
(VlDEO+. VIDEO-) are tenninated with 3900hm resistors at R1800 and RI80t.
Video Interface to the Memory
(P2) Bus
The video interface to the memory bus consists of data input/output registers, the
video control registers and associated lOgic. Data ttansmitted over the P2 bus to
the video logic is latched by the data input registers at Ul600 and Ul60l. Video
data sent to the P2 bus is latched by data output registers U 1602 and UI603. The
data input strobe (V.REQ) and the data output register enable line (V .RD-) are
generated by the Conttol PAL at U1620. The output register clock (V .ACK) and
the input register enable signal (V.WU-) are produced by the video memory controller and the RAS decoder PAL (U1616). respectively.
The video logic responds to three types of memory accesses: direct reads, direct
writes and copy writes. Direct reads and writes are selected via the bus select
decoder at U162I. The decoder uses the four most significant P2 bus address bits
(P2.A20-23) to generate the video bus select signal V.BSEL. V.BSEL is input to
the control PAL at U1620, which then generates a video request signal (V.REQ).
A copy write is executed when two conditions are satisfied: the copy comparator
at U1623 successfully matches P2 address bits A.17-22 with video base address
bits V.BASEI-6, and the control PAL (UI620) is in copy mode.
Following a successful address match, the copy comparator asserts the select signal V.CSEL-. This signal is input to the control PAL, along with P2 address bit
AI7, to generate read/write strobes (V.WLC.V.WUC) for the control registers at
U1610 and U161 1.
Video Write Cycles
Data is wrinen to the video memory when the external write strobes (LDS.t:DS)
are assened by the request latch at U161S. These signals are input to the RAS
decoder PAL at U 1616. The decoder PAL generates enable signals (V. \\ 'U.
V.\\'L) for the bus transceivers (U1730-1737) and data input registers (UI6001601), as well as row address strobes (RAS0-3) for the memo!)'. Refer to Figure
1-9 for a block diagram supponing this logic.
P2 bus data (p2.DOO-lS) is received by the data input registers and is driven, via
the bus transceivers, to the video memory .
Video Read Cycles
. A read cycle is executed if no write strobes (LDS,UDS) are asserted. The request
latch (U161S) outputs bank select signals J and 2 (V.BSl.2). which are decoded
by the PAL at U1616 to address a word in memory.
The video data is transmined from memory to the bus transceivers at U17301737. The transceiver output (V.BOO-lS) is strobed into the data output registers
(U1602,1603), and onto the P2 bus, by V.ACK from the memory controller (refer
to Figure 1-9).
Video Refresh Cycle
A video refresh cycle is perfonned during the last eight states of every memory
controller execution sequence in order to refresh the data storcd in the d)'nami~
RAM. During this cycle, the signals video row address (VRA-) and vidco column
address (VCA-), from the memory controllcr, provide output enables for the
video address registers at U 1640 and U 1641 respective})·. Wi th the assenion of
these signals. the address registers latch values from the address counters
50 of 31 October
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Sun·2150 Field Service Manual
(U 1630.1631) and transmit them to memory.
Video to Memory (P2) Bus Data
Transfers
All write data is stored in a set of registers. allowing the processor to write to
memory without waiting for a pon to become available. The write cycle is
automatically completed when the register data is strobed into memory.
A second write cycle can only be initiated after the first write operation has been
completed. The signal n.WAlT, output by the latch at U1816, inhibits subsequent writes until the current write operation is completed.
n.WAlT is also used during the unbuffered read cycle to inhibit the processor
read-data request until the data is available. This is also the case when a read
request is pending while a write cycle is still in progress.
The video read/write handshake is implemented by the register control PAL at
U1620. The PAL receives bus select signals V.BSEL and V.CSEL. from the bus
access decoder (U1621) and copy comparator (U1623) respectively. These signals are used to assen the video request line V.REQ. which clocks addresses and
control infonnation into the processor address registers (U1632. UI633). and mto
the request latch (U161S). V.REQ is also input to the sync request registers at
U1624 to produce the video state request signal V.SREQ. The state request signal is, in tum. presented to the memory controller logic. where it determines what
cycle (processor or idle) will be perfonned.
Video Interrupts
Video interrupts are generated by the flipflop at U1803. The flipflop is clocked on
the leading edge of V. VBLAl\'K. from the vertical state machine. The outputs are
assened whenever the interrupt enable signal (V.IJ\"TE!\l), from the video control
register, is active. The interrupt signals V.INTREQ and V.IRQ are output to the
video control register and the processor respectively.
50 of 3 J October 1984
Chapter 1 - Theory of Operations
Memory
Sun-2/S0 memory is composed of the following logic:
•
•
•
•
Overview of Sun-2 Memory
Architecture
19
Memory Management Unit
Direct Virtual Memory Access Logic
Physical Memory (Main and Expansion)
Address Decoding
Sun-2/S0 memory architecture is based on the concept of virtual memory. in
which the physical memory resident on the PCBs (l-4MB) represents only a
small amount of the memory space addressable by the CPU. The balance of the
maximum virtual memory space is located on a secondary storage device (e.g. a
large capacity disk drive) located elsewhere on the network.
When the CPU attempts to access a virtual memory address location that is not
currently residing in physical memory. the access is temporarily suspended until
the data is fetched from the secondary storage device. When the physical
memory is updated. the suspended access is completed.
Addressable memory is arranged in 2K byte pages. with 16 pages comprising a
32K byte segment Eight contexts may be mapped concurrently. each context
having a maximum vinual address space of 16M bytes.
Memory Management Unit
(~1..\1C)
The MMU consists of a user context register (U300). a system context register
(U30l), a user/system context multiplexor (U302), the segment map RAMs
(U303, U304). the page map RAMs (U305-31O) and associated logic. Refer to
Figure 1-10 for a functional block diagram supponing this logic and to Appendix
A for definitions of MMU terms.
The MJ.-1U is accessed by the lower and upper byte decoders (U322 and U323
respectively) and by the read decoder (U324). All three decoders use the processor address bits P.AOl-3 to generate read and write decode signals for the MMU
logic.
During an address translation cycle. the function code from the CPU is used to
select either the user or the supervisor context. The context value. output from
either the user or supervisor context registers (U300 and U301 respectively). is
presented to the multiplexor at U302. The multiplexor outputs. together with processor address lines P.AlS-23, are input to the segment map RAMs at U303 and
U304. The segment map RAMs use these inputs to produce a page map entry
group, which in conjunction with address lines P.A11-14, is used to index the
page map RAMs (U305-310). The page map RAMs generate an output composed of mapped address lines and a number of status bits (refer to Figure 1-10)
which provides addresses to the CPU and to memory.
The validity of the protection field (pROT 0-5) is checked by the multiplexor at
U315. If the protection bits are not set in accordance with the state of read/write
line and the processor function codes. the output PROTERR (protection error) is
asscned. This signal is presented to the bus error register at U130.
The accessed and modi fied bits (refer to Figure 1-11) are updated on all nonspecial cycles. The upjate is initialed when the current type field is input to the
update register at U316. The update PAL at U103 assens WR.UPDATE. which
supplies ~ write enable signal to the page map RA.\1 at U307. as well as
500(31 OclOber 198-!
20
Sun·l/SO Field Service Manual
WR.STAT which output enables the update register. The update register then
writes the new data (TYPED, TYPEl) to the page map RAM.
t
---
..
-.-
." •• ~u
TC
_-.1)
,..:~-.
It,
t:-
:A~"
e cax:c:t
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1-_ _11
Figure 1·9
TO JK: i:bCle
TO IUS
a&:II.
'.rm:.."'TI~.
tal:'
Sia:~
101::::
(V'lii
MMU Logic
500f31 October 1984
tc.-_""
Chapu::r 1 -
Conle.'
Registe,
Theory of Operations
21
."..,...
....
SegmenlMap
Page MAP
"
p
"~
s
..,•.,.1 ......,.
" •••,...
T,tM • 0 Mllft ...... or'
¥. Va'" I"
, • P,... ctl.,. Cr • ., ...
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Figure 1-10
Main Memory
s....",,, '.ce/ .....
',p•• ,: Iftpul/Outpul
',po. I . " .., 0 '''8
',po I: " .., •. ,. ...
0
Sun-2 Memory Management
This circuit description is applicable to both the main memory and to the
optional expansion memory. Main memory is located on the CPU board and provides the system with IMbyte of dynamic RAM. The expansion memory is
located on the Memory Expansion board and supplies up to 4Mbytes of additional dynamic RAM storage.
Both main and expansion memory are organized as eight banks of eighteen chips
each. for a total of 144 chips. Each bank is capable of storing a 16-bit data word
along with two parity bits. The dynamic RAM may be either 64K or 2S6K bits
. per Chip. providing memory capacity ranging from 1 to 4Mbytes.
The memory is arbitrarily divided into IMbyte sections: The first megabyte is
always enabled. the second megabyte is enabled when pins 1 and 2, on select
jumper 11201, are shunted. The third and fourth megabytes are selected as a pair.
when pins 3 and 4 of select jumper 11201 are shunted. Refer to Appendix B for
the location of the select jumper.
Address decoding for main and expansion memory is virtually identical: The
memory select decoder at V1200 uses the three most Significant bits from the P:!
bus (p2.A20-22). as well as the configuration of select jumper 11201. to determine if the section being addressed is enabled. If the se1ected section is enabled.
the decoder will output a memory select Signal (M.SEL) to the CAS decoder at
U120 I, and to the read/write decoder at U1202. The read/write decoder will then
enable the read/write buffers (U121O-1214) via either M.RD or M.\\'R. allowin,!;
so of 31 OclOber 19&4
2:!
Sun·21S0 Field Service Manual
data to be transferred to and from memory over the P2 bus.
Note that the row address sttobe (RAS) is not enabled during the bank select
operation. Because of the pipelined RAS-CAS access. the address bits used to
select which bank of memory is accessed are only available in time for the
column address sttobe (CAS).
Each bank of RAM receives an eight-bit address (AO-7) and the control signals
RAS. CAS. WEL and WEU. The address is output from the readlwrite buffers
(U121O-1214) and driven to the RAM inputs by line drivers (U1319.1339.1359
and 1379) through 330hm series terminators (U1318. 1338.1358 and 1378).
CAS signals for each bank (M.CAS0-7) are driven directly to the RAM by the
CAS decoder at V1201. RAS signals (P2.RAS,O.1) from the RAS generation
logic. and the upper and lower byte write strobes (WEL. WEU) from the
read/write decoderat U400. are driven to the RAM via a bank ofline drivers
(U1220,l222,1224 and 1226). Referto Figure 1-12 for a functional block
diagram supporting this logic.
Figure 1-11
Direct. Vinual Memory Access
(DVMA)
Memory Address Decode Logic
Direct vittual memory access allows other devices to read from and write to the
Sun·2/50 memory without interrupting the current CPU process. The DVMA
controller logic obtains the processor bus from the CPU and performs the
read/write cycle for the requesting device. The DVMA logic accepts requests
from the memory refresh logic. the Ethernet controller and the VME bus.
The DVMA control logic is composed of the request flipflops (U207, 203). the
request arbitrator latch (U213), the controller PAL (U214) and the strobe PAL
(U2lS).
The request flipfiops receive clock pulses from the memory refresh)ogic
(R.REQ), the Ethernet control circuitry (E.DS) and the VME bus slave interface
50 of 31 October
19~
Chapter 1 - Theory ofOpentions
23
(X.DMA). When one of the clock pulses is assened. the flipflops p:uerate the
appropriate DMA request and present it to the DVMA request artJitta10r latch at
U213. The latched request signal is input to the DVMA controller PAL (U214).
which prioritizes the request and issues a bus request signal (BR)ID Ibe CPU.
The CPU responds with a bus grant signal (BG) and the deassenian of the processor address strobe (P.AS). The controller PAL then sends DMA enable signals
to the requesting device and to the strobe PAL at U21S.The strobe PAL provides
the function code for the processor. as well as address and data SlJobes for the
requesting device. Refer to Figure 1-13 for a functional block diagram of the
DVMA control logic.
Memory refresh cycles are generated every 12.8usec by the 8-bit counter at
U211. The counter output provides a clock for the request flipflop. U207. which
issues a refresh DMA request signal (R.DMAREQ) to the associated DVMA
control logic. The control logic outputs a DMA enable signal (RDMAEN) to the
refresh counter at U21O. causing a "row address" refresh address to be presented
to the dynamic RAMs. The PAL at UI06 insures that both banks of memory are
enabled during the refresh cycle by asserting the signals BANKO and BA.1\1\.1 to
the RAS generation logic (U218-20). The RAS logic transmits the signals RA.S.
RASO and RAS 1 to the RAM. Refer to Figure 1-14 for a functional block
diagram illustrating the refresh logic.
.,,
r.-.
AAD.1:.... :;;.1II
CUll)}
~V'I..A
.'
ca""a.:_Ll:II
lUlU)
t·,"V
'''' ..
~t.
(11216'
ar :-. t..1i
tTt':-.. A
lEI<
Figure 1-12
DVMA Control Logic
500f31 October
19~
24
Sunol/SO Field Service Manual
-
,".IT
CUtl41
---
-
(UI'.-20)
Figure 1-13
DVMA Memory Refresh Logic
SO 001 oao'ber 1984
Chapter 1 -
Theory of Operations
25
Interface Logic
The interface logic consists of the serial pons for keyboard. mouse and RS-423
communication. as well as the Ethernet and VME bus interfaces.
Serial Communications
Serial communications between the Sun-USO and the keyboard. mouse and RS423 interface is provided by a pair of ZSS30 Serial Communication Controllers
(SCes). The SCC at U600 controls the keyboard and mouse. while the SCC at
U601 suppons the RS-423 interface.
Timing for both SCCs is provided by a 4.91S2MHz clock. derived from the
19.6608MHz oscillator at U200. Chip select lines fordle sees are supplied by
processor address lines P.AOI and P.A02. Read/write control signals are provided by the read/write decoders at U401 and U402. Owmels A and B. of the
SCC at U600. are assigned to the keyboard and mouse respectively. Channels A
and B. of the SCC at U601. correspond to ports A and B of the RS-423 interface.
Data being sent off-board is recejved by the SCCs over the I/O data bus as
10.008-15. This data is convened from parallel to serial and transmitted to the
selected device via dedicated RXD and TXD lines. For incoming serial data, the
process is reversed.
Incoming RS-423 data is driven onto the board by the line receivers at U606 and
U607. Outgoing data is driven onto the RS-423 interface by line drivers at U609
and U611. The line receiver at U615 is shared between channels A and B in order
to suppon synchronous SCC applications.
Refer to Figure 1-15 for a functional block diagram supporting the serial communications logic.
Figure 1-14
Serial Communications Logic
500f31 October 1984
26
Sun·USO Field Service Manual
Ethernet Interface
The Ethernet interface consists of the Ethernet controller (U700). a phase lock
loop decoder (U701). the control registers (U716-7) and associated logic. Refer
to Figure 1-16 for a functional block diagram supporting the Ethernet interface
logic.
Ethemet control is provided by an Intel 82586 Local Area Network Coprocessor.
'This device implements the Carrier-Sense-Multiple-Access-with-CollisionDetection method of link management (refer to Appendix A). which allows multiple worlcstations to access the local area network (LAN) at will.
The phase lock loop decoder at U701 acts as an Ethernet encoder/decoder circuit.
'This decoder connects the Sun-2/S0 directly to an external Ethernet transceiver.
Outgoing 1TL-level data is encoded as transceiver-level code and placed on the
Ethernet Incoming Ethernet data is decoded into 1TL-level data and clock signals. The decoding method employs a phase-locked loop approach with 10 samples per bit cell. Sample rate timing is provided by an external crystal (X700) and
its associated tank circuit. which provide a lOOMHz clock to the decoder's internal oscillator. Either Ethernet level 1 or level 2 interface characteristics may be
supponed via the select jumper at J704. Refer to Appendix B for the select
jumper location.
The Ethernet control registers (U716, U717) manage the overall operation of the
Ethernet interface. Inputs to these registers include an error signal from the bus
error register (U719) and four bits from the I/O data Bus. The control registers
generate interrupt. DVMA request, loopback and reset signals for the Ethernet
interface lOgic.
SO of 31 October 1984
Chapter 1 - Theory of Operations
27
..,.
'-:;::
DlO'
''''7U I)
.'"
I
(&nl"
C'_-..:.~
v;:-:
Figure 1-15
Ethernet DV,MA Cycle
o;.u~!
o.-.!~:
Ethernet Interface logic
An Ethernet memory access is initiated by the assenion of a read (RD) or write
(WR) signal by the Ethernet controller (U700). These signals are ORed at U718
to produce an Ethernet data strobe (OS), which is used to clock the DVM A
request flipflop at U207. The flipflop outputs the request signal E.DMAREQ to
the DVM A control logic. The control logic also receives the Ethernet request signal E.REQ. TIlis signal is the result of ANDing HOLD, from the Ethernet controller and E.ERR, from the bus error register. With these signals assened. the
DVMA arbitrator (U213) will continuously request the bus from the CPU until
'the Ethernet controller deasserts HOLD.
The Ethernet data strobe (OS) is also used. via the register at U713. to produce an
address strobe. The address strobe (AS) latches the 24-bit Ethernet address
(p.AOl·23) into the address registers at U702-4 when the enable signal
E.DMAEN is assened by the DVMA control logic.
During an Ethernet write to memory, the DVMA control logic will provide an
output enable signal (E.OE) to the write data buffers at U707 and U708. Dat::,
from the Ethernet controller (U700) is input to the buffers and driven onto the
I/O data bus as 10.000·15.
During an Ethernet read from memory. data is latched into the read buffers a:
U705 and U706 by the write enable signal E.\VE. The b4ffers are output enabled,
driving I/O bus data to the Ethernet controller inputs, by the Ethernet read line
(E.RD) issued from the DVMA control logic.
so or 31 OclDbcr 19~
28
Sun·2150 Field Service Manual
The Ethernet read and write buffers are byte swapped between the lIO data bus
and the Ethernet data bus: JJO bus data bits 0-7 conespond to Ethernet bus data
bits 8-1S and vice versa.
Ethernet bus errors are flagged by the bus error register at U719. In the event of a
bus error, this register transmits the error signal E.ERR to the Ethernet control
registers (U716-7) and to the DVMA request register (U207). The E.ERR signal
inhibits any future DVMA requests from being sent to the DVMA control logic.
DVMA requests are inhibited until the bus error register is cleared by a reset signal (RESET) from the Ethernet conttol registers.
VME (PI) Bus Interface
The VME bus interface provides the Sun-USO with bidirectional data access to
any device attached to the, VME bus. As the bus master, the CPU may access any
of the slaves on the bus. As a bus slave. the Sun-21S0 may be accessed by other
VME bus masters. Refer to Figure 1-17 for an illustration of the VME bus data
transfer sequence.
The VME bus interface logic is composed of the arbitration and request circuitry,
the VME master interface and the VME slave interface.
VME bus utilities are implemented using four control lines: system clock
(SYSCLK), AC fail (ACFAll..), system reset (SYSR) and system fail (SYSF).
SYSCLK is derived from the 16MHz oscillator at U202.TIlis signal is driven
onto the VME bus by a high-current driver at U817. TIlis clock signal has no
phase relationship to other VME bus signals and may be disconnected by removing the shunt from pins 1S and 16 of select jumper J900. Refer to Appendix B for
the location of the select jumper.
ACFAll.. is derived from the power-on/reset signal POR and is driven onto the
VME bus by the driver at U818.
System reset (SYSR) is driven onto the bus by the driver at U818 and is assened
whenever processor reset (p.RESET) is active. When configured as a bus master,
the Sun-2/S0 issues a reset signal to the VME bus with RESOUT. RESOUT is
assened as the result of a power-on reset, a processor reset or a watchdog reset.
As a bus slave, the Sun-2!SO receives a reset signal (RESIN) from the VME bus.
Vl\'1E Bus Arbitration and
Request Logic
The arbitration and request logic consists of two PALs (US11, U8l4) and a pai r
of registers (U812, U813). Bus request levels are monitored and requests ami·
trated using a level daisy chain (refer to Appendix A). A CPU bus request (in
order to perfonn a readlwrite cycle, or to ackowledge an interrupt) is initiated
with the assenion of a bus select signal (BSEL) to the PAL at U8Il. If the arbitor
does not have control of the bus, it will request mastership by assening the VME
bus request signal BREQ and implement a normal bus arbitration sequence. If
the arbitor cunently controls the bus, it will keep control until another bus master
requests it.
50 of 31 OclOber 19&4
Chapter 1 - Theory of Operations
VME Master Interface
29
Once the arbitration logic has obtained bus mastership. the VME master interface
allows the CPU board to access any slaves on the VME bus. The master interface
is composed of address/address modifier latches (U940-03). a bank of address
drivers (U900-03), write data registers (U910-11). write data drivers (U912-13),
read data buffers (U908-09) and a comrolline driver (U817).
The VME slave device being addressed will respond to the data transfer with
either an acknowledge signal (DTACK) or a bus elTOr flag (BERR). These signals are latched at U81S and input to the PAL at U816, where they are transmitled to the CPU.
The VME master interface utilizes its backoff/rerun capability in response to
VME bus deadlocks and VME accesses that take longer than 2-3usec. A VME
bus deadlock results when the CPU attempts to access the VME bus while
another bus master is concurrently trying to access the CPU as a slave device.
Because the VME bus has no rerun capability, it requests that the CPt: resolve
the deadlock.
When a VME access is not completed within the specified time limit, or the bus
is deadlocked, the state of the VME interface is frozen and a CPU rerun cycle is
initiated. During the rerun cycle. the processor may relinguish the bus to the Ethernet interface or to the refresh logic. allowing those devices to execute their
functions. The rerun cycle is then ended and the processor continues with the
VME access. Rerun cycles are transparent to the VME bus and may also be per- .
formed while the CPU is waiting for bus mastership.
Conditions requiring a rerun cycle are recognized by the PAL at U81O. which
issues a bus rerun signal (B RERUJ'I.'). This signal is input to the PAL at U102,
which generates bus error (BERR) and halt (p.HALT) signals for the processor.
Rerun operations are monitored by a counter at U809. When the count reaches
128, a TIMEOUT signal is assened to the bus error register (U130).
\'~1E
Slave Interface
The VME slave interface allows the CPU board to be accessed by other VME
bus masters. A number of conditions must be met before the slave interface is
enabled: The address comparator at U930 must successfully match the 4-bit
VME bus address (pl.A20-23) to four bits from the switch-selectable base
.address (X.A0-3) The VME address modifiers must be specified and set. The
VME interrupt acknowledge signal (pl.IACK) must be deassened. The CPU
board cannot currently be the bus master, and both the VME address (X.AS) and
data (X.UDS,xLDS) must be asserted. When all of the preceding conditions are
met. the signal X.DMA is assened by the comparator. indicating that a V11E
slave interface is pending.
When another bus master requests access to the CPU board, the DVMA control
logic treats the access as an external DVMA request. When the DVMA control
logic receives X.DMA, it initiates an on-board fetch cycle using the external
DVMA address held in the registers at U904-06.
During a VME bus write cycle. VME data is placed onto the I/O data bus via the
data buffers at U908 and U909. During a VME bus read cycle. data from
memory is latched in registers at U910 and U911 and driven onto the VME bus
so or 31 October 19&!
30
Sun·2!sO Field Service Manual
by data buffers at U912 and U913. The data transfer handshake is completed on
the trailing edge of the enable signal OCDMAEN) from the DVMA control logic.
The handshake register at U931 win then assert either an acknowledge signal
(X.DTACK) or. in the event of a bus error. the error signal X.BERR 1be transfer
signal X.DMA. from the comparator at U93O, remains asserted until the VME
bus master deasserts the data strobes. The handshake register (U931) is cleared
on the falling edge of X.DMA.
VME Interrupt Control
'There are seven VME bus interrupt lines. designated PIlRQl-7. All seven lines
pass through a select jumper at ]800 (refer to Appendix B). allowing any combination of interrupt levels to be selected. TIle selected interrupt lines are input to
the priority decoder at U800. which prioritizes the imerrupt requests IUd outputs
the encoded imenupt lines B.IPLO-2. These lines are combined with on-board
interrupt requests at the inputs of PROM VIOS. which produces the processor
interrupt signals IPLO-2.
Upon receiving an interrupt request. the CPU generates the appropriate function
code for the PAL at U101 and transmits the interrupt level being acknowledged
on address lines AOl-3. The multiplexor at U802 monitors AOl-3 and the inter·
rupt lines IRQ 1-7. to determine if the pending interrupt is from an external
source.
cru-TO-"'"
YIlt
C'lCtJ:
L--~_'~i_~~_C...J>-1. . _..._c_.tr_--'H
,--~_r.r..::_;:_i'-,>-1
DATun
fMC
To·av 0:: E
"",c~'>-1
H-~.. >l
ADO ,.
WA .,~
na:t.~:=~
Jr.-~~r.
. 1
:I
I
PlIOIUTY
I£alIlU
Figure 1-16
I"' ....
VME Bus Data Transfer Sequence
50 oUI OclOber 19&4
Chapter 1 - Theory of Qperations
31
The Sun-2/50 is configured with either a Phillips or a Monitenn monitor. While
there are minor differences between the two, both monitors receive the following
inputs:
• Horizontal Sync (HSYNC)
• Vertical Sync (VSYNC)
• EO.. Video (VIDEO+,·)
• 1201240AC
The video monitors share the following operational characteristics:
1.2. Monitor
Visual Display-
900 borizontallines with 1152 pixels per line (Version A)
Video Oock·
Horizontal CycleVenical CycleHorizontal RetraceVenical Retrace-
1024 borizontallines with 1024 pixels per line (Version B)
lOnsec from l00MHz oscillator
16.00usec 62.5KHz.
15000usec 66.67Hz
4.48usec
600usec
Monitor adjustment procedures are provided in Chapter 2, Diagnostics and
Troubleshooting. Comprehensive hardware deSCriptions and maintenance procedures are to be found in the monitors' respective service manuals (refer to the
list of applicable documents).
1.3. Power Supply
Power for the Sun-2/S0 is provided by a single-board power supply, located in
the workstation chassis. The supply generates three regulated voltages, +5VDC.
+ 12VDC and -12VDC, which are available at the system backplane. Refer to the
power supply removal procedure in chapter 3 for a wiring diagram showing the
supply outputs and their respective voltages.
.
The power supply operating specificatiOns are as follows:
AC Inputs-
1IS/230VAC, 47-70Hz field selectable (Nominal)
9O-I32/180-264VAC (Operating Range)
DC Outputs-
Output 1, +SVDC +/-1% steady state at 22 amps
Output 2. +12VDC +/-1% steady state at I.S amps
Output 3, -12VDC +/-1% steady state at 0.5 amps
.~!!
50 of 31 October
19~
2
Diagnostics and Troubleshooting
Diagnostics and Troubleshooting ........_.._...____ ...___............________ ........
35
2.1. OveIViev.' ..............................................................................................................................
2.2. Symptom Analysis ..........................................................................................................
Local Problems ..............................................................................................................
Ethernet Problems ........................................................................................................
File SeIVer Problems ...................................................................................................
2.3. ObseIVing the Stanup Procedure ............................................................................
35
36
36
Stanup Tests ....................................................................................................................
Boot Device .......... ..........................................................................................................
UNIX Kernel ...................................................................................................................
2.4. PROM Diagnostics (pDIAG) ...................................................................................
38
39
37
37
37
40
42
Installing PRO~ls .........................................................................................................
Using the Diagnostics .................................................................................................
Automatic Tests ........................................................................_...........................
42
Menu Mode .........................................................................................._....................
Test Descriptions ..........._...........................__........._...__.___._________
45
46
Context Tests ......................................_. __._....................._. ___..._..._............_
Startup Tests .._......................................._.............._...__._ ...___.___..._............
46
Segment Tests ...................................................... _...................................................
47
Page Tests ....................................................................................................................
Memory Tests .................................................................................._.................. _..
47
48
Parity Tests ........................................................................................""._"."..".""."
Video Menu Tests ...................................................................................................
48
50
43
43
47
Ethernet Menu Tests ............................:............... _...... _____ ............_..._......
Memory Menu Tests ....................... _._.__.........________.__ ...._____..
2.5. Standalone Programs _...._.........__._............_.__...________....__.__.__..
SO
51
51
Environment ...._..........__............_...____........._..._.......____._._._._._....__.....
51
2.6. ,Quick Reference Troubleshooting Guide ...........___......._.......__.___...__
S2
2
Diagnostics and Troubleshooting
2.1. Overview
This chapter describes how to diagnose and repair problems on your Sun 2/50
workstation. It provides help for many levels of problems. ranging from simple
items like checking power cords and switches. through complicated procedures
like running standalone programs and PROM-based diagnostic programs.
This chapter is divided into five sections, each of which provides a different
method of solving the problem. The choice of which to use depends on the
nature of the problem, your experience, and the resources available.
The sections are:
• A symptom/action table - this provides a list of possible problems followed
by instructions describing what to do about them.
• Observing the unit during startup - this section describes what the workstation goes through when it stans, what it needs to complete the process. and
how to detennine what's wrong by interpreting the messages displayed during
this process.
• PROM diagnostics (pdiags) - a set of PROM chips, available from Sun, perfonn an extensive series oftests on the system hardware. These tests usualJy
pinpoint the source of a hardware problem.
• Standalone programs - these are programs designed to be booted from the
system monitor when UNIX is not present They are designed to get at and
test resources that are unaccessible when U1\lX is present For standalone programs to run, the system must be able to communicate with its file server.
• A quick reference troubleshooting guide - this is a ftowchan which provides
two kinds of help. In some cases, it acts as a pointer. leading me user to the
other troubleshooting and repair sections in this manual; in other cases it actually guides the user through the troubleshooting and repair routine itself.
The chapter "Theory of Operations" includes a procedure for checking the power
supply levels. This is sometimes included as pan of the above procedures.
Chapter 3, Maintenance, describes how to replace defective or damage field
replacable units (FRUs).
35
50 of 31 October
19~
36
Sun·21S0 Field Service Manual
2.2. Symptom Analysis
This section contains a list of the more common problem indications, followed
by actions to correct them.
Sometimes, the solutions here refer the user to the other troubleshooting sections
in this chapter. or to other manuals. This procedure assumes the user will take the
corrective measures indicated there.
Local Problems
Problem
Action
System is inen: nothing happens
when attempting to stan it
Cleck, in this order:
Power switch ON
Power cord plugged in
Wall power ON
System fuse OK (see procedure)
Power supply OK (see procedure)
System won't complete autoboot
procedure properly.
Check it as per "Stanup Problems"
section in this chapter.
Video display shows spumous
blips, or doesn't redraw correctly.
Check video cable and connections
Run pdiags
Check power supply levels
Video display wavy, dim or uneven.
Cleck and adjust video monitor and
power supply as per procedure in
the ftowchan in this chapter.
Memory parity error reports.
If repon includes address, check to
see if address is within CPU's
memory range (usually but not
always 1 Megab)1e). If address is
greater, swap memory expansion
board and run pdiag.
If no address is present, or if address
is within CPU's memory address
range, run pdiag
Bus error reports. EXAMPLE:
Panic bus error
syncing disk .•.
444444 .•. done
dumping to dev NNN,
offset XXX
durr.p succeeded
rebooting
Allow system to reboot and proceed
with normal use. If bus errors persist, .run pdiag
500n1 October 1984
CIla.P'« 2 - Oiapostics _ Troubieshootin,
37
Ethernet Problems
fil~
Problem
Acrion
Enor reports prefaced by "ieO", or
cursor displays a question mark '"
during boot procedure and booting
won't continue, NOTE: When the
cursor alternates between an equal
sign and question mark during
startup, it is searching for a bootable
copy of UNIX, Give it some time
before assuming problems; the Ethernet may be slow due to heavier
than nonnal use.
Cleek connectors and cables including Ethernet connector on back
panel of workstation. A picture of
the connector appears in Appendix
Problem
Action
File server doesn't respond, or during startup procedure, cursor on
workstation screen continues to
display a question mark then an
equal sign (7 =) while staying in
same location.
Verify that file server system is runDing correctly as per "System
Administration for the SlDl Workstation".
File system damage for more than
one client
Verify that file server system is runDing correctly as per "System
Administration for the Sun Workstation.
Messages containing prefix "nd".
such as "nd outpUt enor SS"
Check file /etc/nd.local as described
in "System Administration for the
Sun Workstation",
File system damage for 0l\'LY Ol\'E
client (who has Sun workstation!)
Suspect client's CPU - run pdiags
G,
Cleek other stations, if accessable,
to see ifthey'Je experiencing Ether-
net problems.
Correct Ethernet as per Ethernet
instruction manual.
Server Problems
2.3. Observing the Startup
Procedure
After power-on or reset, the Sun USO workstation goes through a series of steps
designed to bring it up piece by piece. testing and taking inventory as it goes.
The boot PRO!-.1 contains a program called the monitor, which performs some
routine hardware tests, attempts to boot the UJ\'IX kernel, then passes control to
it.
The user can interrupt the monitor after it finishes its stanup tests but before it
passes control to tn-.'IX. This causes the monitor to enter an interactive mode,
SO of 31 OclDber 1984
38
Sun-2J5.0 Field Service Manual
enabling the user to load and execute (boot) programs other than UNIX.
If the user does not interrupt the monitor. and the Ethernet and tile server are
working correctly. the monitor boots the UNIX kernel and passes coruroJ to it.
The messages generated during this procedure provide clues as to how the system
is working and what (if anything) is wrong.
If the startup tests pass. die monitor displays the following message on the
screen. or on a terminal if one is attached (dashes"-" indicate variables):
Startup Tests
Self Test completed successfully
Sun Workstation, Model Sun-2/S0 or Sun-2/160, Sun-2 Keyboard
ROM Rev -, -MB memory installed
Serial f --, Ethernet address -: -: --: -: - :.-Probing I/O bus: ie
Auto boot in progress
If this message does not appear. the selftest failed. To confirm this, check the
CPU LEOs and note the pattern displayed. They should either display one pattern constantly. or cycle through a series of patterns starting with the beginningof-lest (all clear).
In either case. the LEOs provide information about the failed test. If the panern
remains constant. the monitor is cycling on one test; that should be the one that
failed. If the LEOs are cycling through a number of patterns then returning to
all-clear, the last panern visible before the all-clear should be the test that failed.
In either case, identify the failed test by matching the pattern to the tests, as
shown below.
Table 2-1
LED Displays During Startup Selftest
LEDs
*=on,o=off
Hex
**** ****
FF
Reset - no tests running.
CPU or DIOIlitor
PROMs
0000 0000
00
Stanup tests complete
All tests passed
0000 *000
04
Blinks if NMI OK
System seems OK
0000 00*0
02
Entering user watchdog routine
Software bug
000* 000*
11
Context registers
CPU
00*0 000*
21
Oata lines in segment map
CPU
00*0 00*0
22
Address dependencies in
segment map
CPU
Test in progress
Suspect if LEDs stuck
or cycling to here
50001 October
19~
39
Chapter 2 - Diagnostics and TfC!I!IWsbooting
Table 2-1
Boot Device
LED Displays During Startup Selftest- Continued
Susp«t if LEDs stuck
or cycling 10 here
LEDs
,*=on,o=of!
Hex
00,*,* 000,*
31
Constant data in page map
CPU
00** 00*,*
33
CPU
00,*,* 00,*0
32
Data lines in page map
Address dependency in page
map
0,*00 0000
40
PROM contents
CPU or monitor
PROMs
0*0* 0000
so
see chips
0**,* 0000
70
Sizing memory
CPU
CPU or memory exp:msion
0*** 000*
71
Memory constant data
CPU or memory expansion
0*** 00*0
72
Memory address dependency
CPU or memory expansion
0*** ****
7F
Parity circuit
CPU or memory expansion
*000 000*
81
Timer chip
CPU
0000 000*
01
Selftest done; perparing to
boot
CPU or memory expansian
0000 00**
03
After local memory verified
CPU
0000 0***
07
Setting up-diagnostics complete
CPU
**** 000*
F1
Setting up memorydiagnostics complete
CPU
**** 00*0
F2
CPU
'**** 00**
F3
Setting up maps-diagnostics
complete
Setting up frame buffer
**** 0*00
F4
Setting up NMI or keyboard
Test in progress
CPU
CPU or video/video
frame buffer
CPU
If the selftests complete successfully. the monitor attempts to boot UNIX over
the Ethernet. It displays the following message:
SO of 31 OclOber
19~
40
Sun·2150 Field Service Manual
Probing Ilo bus: ieO
Auto-boot in progress
Boot: ie(O,O,O)VMUNIX
Load: ie(O,O,O)boot
Boot: ie(O,O,O)VMUNIX
Size: NNNNNN, NNNNN, NNNNN bytes
Sun UNIX 4.2 ...
Before the Auto-boot in progress" is displayed, the system checks to ensure that
it has a keyboard cormected. If it does not, it doesn't panic. it simply infonns the
user with the message:
It
Using RS232-A Input
right before
Auto-boot in progress
If you think you have a keyboard anached. this message indicates a defective
connection or keyboard. It will cause the stanup procedure to abon later if no
terminal is connected to RS232 pon A.
The monitor looks for a bootable copy of Ul'HX on local disk. local tape. and
then on the server over the Ethernet. While it is looking. it displays an alternating question mark. then an equal sign inside the cursor on the workstation screen.
Since the 2/50 doesnOl normally have a local disk or tape. the Ethernet copy gets
booted.
If the Ethernet is not working correctly. this message or one like it appears:
Probing I/O bus: ieO
Auto-boot in progress
Boot: ie(O,O,O)VMUNIX
ie xmit failed: Nh~
ie Ethernet jammed
ie xmit failed: NNNN
ie Ethernet jammed ...
If this happens, check the Ethernet cormector on the back of the system, or the
Ethernet 'itself, as per it's instruction manual. The Ethernet connector appears in
AppendixG.
If the Ethernet is working but the monitor cannot find something to boot. it con-
tinues to display the alternating question mark and equal sign. Check to ensure
the file server is working correctly and a bootable copy of UNIX lives in
/vmunix. See "System Administration for the Sun Workstation".
C:\lX Kernel
Assuming the Ethernet is working. and the monitor was not interrupted, the sys·
tern searches out the file /Vmunix on the server and downloads it over the ELhernet into local memory. This file should be a bootable 'lJ!\lX kernel: the m0n110;
passes control to it when it is loaded.
50 oDl Ocmber 1984
Chapter 2 -
Diagnostics and Troubteshooting
41
The kernel takes over the task of bringing the worlcstation on line. It conducts a
search of available resources and displays the results on the screen with a display
similar to the following (where Xs and Ns are variables):
Boot: ie(O,O,O)vmunix
Load: ie(O,O,O)boot
Boot: ie(O,O,O)vmunix
Load: ie(O,O,O)boot
Boot: ie(O,O,O)vmunix
Size: NNNNNN+NNNNN+NNNNN
Sun UNIX 4.2 Release Kn (XXXXXX-CLIENT) IX: Tue Oct 23 18:3C::
Copyright (c) 1984 by Sun Microsystems, Inc.
mem - NNNNK (OxOnOOOO)
avail mem - nnnnnnn
Ethernet Address - N:N:NN:N:N:NN
zsO at virtual nnnNNN pri 3
zsl at virtual nnnNNN pri 3
isO at virtual nnNNNN pri 3
bwtwoO at obio N pri N
using NN buffers containing NNNNNN bytes of main memory
Automatic reboot in progress
DDD MMM DD HH:~~:SS TTT YYYY
/dev/ndO: NNN files, NNNN used, NNNN free {~~ flags, NN~~ t:::
DDD ~~ DD HH:MX:SS TTT YYYY
System went down at DDD ~~ DD HH:MM:SS TT~ YYYY
D~~p time is DDD MMM DD HH:MM:SS TTT YYYY
local daemons: local sendmail portwrap
preserving editor files
clearing /tmp
standard daemons: update cron printer accoun~ing
Starting network at: inet
DDD ~~ DD HH:Y~:SS TTT YYYY
NID."N1-~
login:
After the "Automatic reboot in progress"line, a program checks to ensure file
system integrity, and attempts to repair any inconsistancies. If this progr.lm does
any repairs, it repons its activities, then resets the system, causing the entire reset
sequence to repeat This condition is most likely if the system was shut down or
reset without using /etc/halt to do it correctly.
The later half of the above message may vary according to the conditions and
system configuration. Cenain trivial system problems may generate error repons
that do not substantially effect the procedure.
The following line in the above message represents a data and time repon:
DDD MMM DD HH:MM:SS:TTT YYYY
for example:
Fri Dec 21 13:35:22 PST 1984
so of 31 October 19~
42
Sun-2/50 Field Service Manual
Now, the UNIX controls the workstation. This presents a whole new spectrum of
possible problems that are beyond the scope of this manual. For instructions, see
the Sun UNIX documentation and consult your local UNIX expen.
2.4. PROM Diagnostics
(pDIAG)
A set of two PROM chips, labeled 0 and 8. contain the most comprehensive diagnostic program available for the Sun-USO. 1bese PROMs are normally not
present: they must be installed in place of the normal boot PROMs (USOO and
USOl) for the diagnostic effort. Then, when the workstation is powered-on, they
take over operation. allowing no other program to nm.
Using these diagnostics requires
a)
powering down the workstation.
b) opening the case and installing the PROMs,
c)
powering it on, and
d) inteIpreting the results.
The following procedures provide instructions.
Installing PRO~ls
1)
• A phillips screwdriver
• An ASCII tenninal, set up as follows:
• Full Duplex
• 9600baud
• XON and XOFF
• An RS232 cable connected as follows:
• Cross-connect 2 and 3
• Loop back S and 6 at both ends
• Connect 7 straight through
A set of diagnostic PROMs labeled 0 and 8
2)
Power-dov,n the workstation. If UJ\'IX is running. use /etc/halt.
3)
Unplug the power cord.
4) Remove the PC board as described in Chapter 3. Maintenance, in this
manual.
S) Locate the boot PROMs, USOO and USOl, on the main PC board.
6) Replace these with the two diagnostic PROMs.
a)
Install the diagnostic PROMs in the correct pads. Both the pads and the
PROMs are labeled "0" and "8"; make sure they match. 0 goes in
PROMO and 8 goes in PROM8.
b) Install the diagnostic PROMs in the right direction. Line the V-shaped
depression in the PROM chip with the V-shaped indentation silkscreened around the PROM holder.
c) Handle PROM chips carefully! Avoid bending or damaging: pins. and
place the PROMs in an anti-static pad when not using them.
50001 CKlOber 198-:
Chapter 2 - Diagnostics and Troubleshooting
43
7) Replace the main PC board and close up the workstation. Again, refer to the
Chapter 3 for details.
8)
Connect the terminal's RS232 cable to the connector labelled SIO·A on the
rear panel of the workstation.
9) Plug in and power up the terminal.
10)
Plug in and power up the worlcstation.
11)
The diagnostics should stan automatically. Refer to the procedure "Using
the Diagnostics" in this section for details.
12)
When the diagnostic is completed, repeat steps 3 through 7, replacing the
diagnostic PROMs with the boot PROMs. OBSERVE ALL CAUTIO~S!
l'sing the Diagnostics
The diagnostic program (pdiag) stans automatically when the workstation is
powered-on with the PROMs installed. It runs through the first series of tests (11
through 41), then enters menu mode. In menu mode. the user can allow it to run
a default series of tests, or can interrupt it and then control it via the menu.
Because the video monitor may not be working, the diagnostics send all output
messages to the terminal. However, the video monitor should be connected, so it
can be tested. and because some of the tests display panerns on it
Automatic Tests
The diagnostic program displays the following message on the terminal as it
completes the automatic tests:
50 of 31 October 198.<
44
Sun-21S0 Field Service Manual
Model 50 Prom Diagnostic REV 1.7 10/23/84 Sun Micro
T21(segcons) T22(seg uniq) T23(seg check)
T24(pagecons) T25(page uniq) T26(page check)
OxONOOOO bytes of memory found
T31(cons mem) T32(mem uniq) T33(mem rand) T34(mem check)
T37(page aIm bits) T38(pageon) T39(pageoff) T40(valid) T41(ints)
Starting Menu
Press key to stop default tests
Model SO diagnostic Menu REV 1.3 10/16/84
Video menu REV 1.2 9/25/84
enable: video 1/1 copy % int 0/0
base Ox2/0x2
jumper: blO a 0 color 0 lK 0
Pass1
Pass2
Pass3
Pass4
Pass5
Pass6
Pass7
Passe
Pass9
PasslO
Passl ...
The tests generate the above message as they pass. If they fail, the sequence is
interrupted: the resulting indications are listed in ''Test Descriptions"later in this
section.
The words "Staning Menu" in the above message signal the transition from the
automatic portion of the tests to the menu portion. Pressing any key after this
message causes the program to interrupt its sequence; it can then be controlled as
described in the "Menu Mode" description a bit later.
The menu ponion runs through the following automatic sequence if allowed to
continue uninterrupted (no key is pressed and no test fails):
50 of 31 OclOber'19&4
Chapter 2 - Diagnostics II\d Troubleshooting
45
Start
Tests 11 through 41 (crawlout tests)
Menu Mode Automatic Defaults as follows:
video tests:
Reqister test
Memory test, 10 passes - prints "Passl, Pass2, etc" 0:1 t.;.
and displays different patterns on the workstatic:'l sc~e.;;.
Copy test, 10 passes - prints "Passl, Pass2," etc on the
displays different patterns on the workstation screen.
Ethernet:
Diagnose
Local Loopback
Encoder loopback
Returns to beginning of diagnostic
p~ogram
and starts ove:
After the diagnostic program displays the words "Starting Menu". pressing any
key interrupts the automatic test sequence and causes it to enter menu mode.
Menu Mode
The men~s allow the user to select individual tests from the groups Video. Ethernet, and Memory. and to select some parameters. To display the current menu
enter "1"; to display the current test and parameters, enter a . To run a
single test. enter the test letter from the list below; to run a series of tests, enter a
series of letters from the list, separated by commas.
The following list shows the menus and tests. For details of each test, see "Test
. Descriptions" later in this section.
Table 2-2
Menu Ust
so of31 October 19&4
~
46
Sun·2J50 Field Service Manual
Items in Menu
Menu Type
Top Menu
v
e
m
Video Menu
?
Register
Memory
Copy
Up to main menu
Display menu
d
1
Local loop
r
m
c
u
Ethernet Menu
e
E
D
U
?
Memory Menu
Video
Ethernet
Memory
m
p
a
r
m
b
u
?
Diagnose
Encoder loop
External loop
Dump
Up to main menu
Display Menu
Map
Pattern
Address unique
Random
Change Modes
Bang
Up to main menu
Display menu
Test Descriptions
The following list describes each individual test. and the messages and indica·
tions generated if it fails. The tests stan at Test 11.
Context Tests
Test 11:
Supervisor Context Register- Tests ability to read and write the
supervisor context register by writing. then reading the values 0 to 7.
Non-matching values cause a fatal write/read loop. Uses byte access
in fc3.
Failure Mode - Tests 11 through 15 repeat indefinitely upon
failure. Test 16 repeats for (about) 5 minutes. then allows the
test suite to continue. As ~ach test runs (and repeats!) it
displays its test number in binary on the CPU LEOs; these
numbers can be convened to hexadecimal to yield the test
number.
Test 12:
~~ ~!~J!
User Context Register - Tests ability to read and write the user
context register by writing. then reading the values 0 to 7. 1'\onmatching values cause a fatal write/read loop. Uses byte access in
fc3.
50 of 31 October 1984
Chapccr2 -
.
Stanup Tests
Segment Tests
Diagnostics and TN "
aring
47
Test 13:
UserJSupervisor Context Register - Writes the value 7 in the user
context register while the writing the values 7 to 0 ia abe supervisor
context register, then decrements the value in the uscraaext register to 6 and again writes 7 to 0 in the supervisor COIlCa register. It
continues until both registers contain O. Uses word KIIZSS in fc3.
Test 14:
Supervisor/User Context Register - Same test as IIIoIe. only the
user and supervisor context registers are reversed. Uses ,",rd access
infe3
Test 15:
Check Function 6 and PROM - Checks to see that u data fetched
in function code S (supervisor instruction - feS) spa.c:e .ulChes the
data fetched in fc6 (supervisor data space). Failure causes a fatal
read/Write loop from fcS followed by a read from f~ a1he failing
address. Uses byte access in feS and fc6 spaces.
Test 16:
Initiate UART - This test initializes the UARTs and attempts to
print the PROM revision level. If it fails, the test loops for about 5
minutes, then the program continues to the next test. h attempts to
write to the UART; however, it may not succeed.
Test 21:
Segment Constants - This writes the values Oxaa, ()x(X). Oxff and
Ox23 to the segment map starting at context 7 and working dov.n to
.
O.
Failure Mode - Tests 21 through 23 perform dIree actions
upon failure: a) they repeat the failed action indefinitely, b) the)
display the test number in binary on the CPU I...EDs. and c) they
attempt to write a failure message to the terminal.. 1fie message
identifies the test, and what was expected and obtained.
(EXAMPLE - Segment NNN Exp NNN Obs YYY)
Page Tests
Test 22:
Segment Address Unique - This test writes the values OXOO
through Oxff in each context to the segment maps, tbeo reads back
the result. This test may miss MSB (256 values over 512 entries) 0:context decoding problems, but the checkenest should catch those.
Uses byte access in fc3.
Test 23:
Segment Oleckenest -This test writes a pattern of ODS then Oxaa
onthe area under test. then doubles the size of the pIIltm and
repeats the test until the pattern =In times the area. h reads back
the area to ensure it returns the right pattern.
Test 24:
Page Constants - ntis test writes the values Oxaauuaa.
OxOOOxxOOO. Oxfffxxfff, 0x555xx555 and 0x213xx731 to the page
maps, then reads them. verifying that it receives what it wrote. Note
that in page maps, the middle two numbers (xx) are undefined. US~~
long access in fc3 space.
Failure Mode: When page tests (tests 24, 25, and 26) find an
error, they continue to test the offendiDg address while displaying the test number in binary on the CPU LEDs. Theyattemp:
50 of 31 October 19~
48
Sun-2/S0 Field Service Manual
to write a message to the terminal; this identifies the test. what
was expected. and what was observed.
Memory Tests
Test 25:
Page Unique - Writes the values OxOOOxxfff through OxOOO.uOOO
to the page maps to determine that page decoding is unique. Uses
access in fe3 space.
Test 26:
Page Checkenest - This runs the same as Test 23. except uses
Oxaaaxxaaa pattern on page maps. Uses long access in fe3.
Test 30:
Memory Sizing -This test determines the amount of memory
installed by mapping the first 4 Mbytes. then doing a byte write to
the last location of each 1 Mbyte chunk., staning at 4 Mbytes and
working 'backwards. The first Mbyte found is the memory size.
which is reported on the tenninal and used for subsequent memory
tests. If it finds no memory. it prints the address of the last read, the
page map involved, and the virtual address of the attempt.
Failure Mode: Memory errors in tests 30 through 34 cause the
program to enter a loop which repeats 64K times, prints the last
value it received out to the terminal, then continues. While the
program is repeating, the user can a) type a "b" to cause the
diagnostics to start over, b) type an "s" to skip memory tests
(skips to Test 35), or c) type any other key to continue to the
next memory test. If left alone, the tests loop indefinitely when
they find failures.
Paril)' Tests
Test 31:
Memory Constants - This test writes, then reads a series of constants to or from memory. It uses long accesses in fc6 space.
Test 32:
Memory Unique - This test writes the virtual address of every location to that location, then reads back that address. it uses long
accesses in fc6 space.
Test 33:
Random Addressing - This test writes random numbers to memory
then reads them back. It uses long accesses in fc6 space.
Test 34:
to main memory. It uses a pattern Oxaaaaaaaa, and takes a long time
to complete. especially in machines with.1arge memories. It uses a
long access in fc6 space.
Test 35:
Parity Function - This test writes the values OxOOOQ, Ox(xx) I,
OxlOOO and OxlOOl to memory. then checks for parity errors. Then
it sets the parity generator bit in the system enable register to caus;! a
parity error, and re-writes the same four values to memory. Now it
checks to ensure that the right parity error is generated for each
value. Uses word accesses in fc6.
Failure Mode: If test 3S passes, it indicates that the parity circuit is working; if this test fails, finding the cause requires
skilled investigation; as many different conditions can cause it
to fail.
50 of31 October 19S4
Chapter 2 - Diagnostics and Troubleshooting
49
On the positive side. except for the menu tests and the memory
lests, virtually any failures indicate problems on the CPU board.
In the case of parity problems, detennining exactly where the
failure is on the CPU board is NOT easy or straightforward.
When it encounters a failure. the parity function test returns a
message:
Unexpected bus error - XXXXXX
Test 36:
Parity validity - This lest writes odd and even parity combinations
to all of memory and checks to ensure parity protection works.
Failure Mode: The parity validity test reads then decodes the
buss error register; it repons one of the following:
lower parity
upper parity
timeout
protection error
Pl master
page invalid.
Test 37:
Page map access/modify bits - This test maps in a page of memory
and performs both read and write access to it. The test checks to
ensure that the proper accessed and modified bits are set
Failure Mode: If it finds errors, test 37 prints either:
access test exp NNN obs YYY, or
modify test exp NNN obs YYY
Test 38:
Page permissions on - This test tums on permission bits, then tries
a number of accesses to ensure permission bits allow accesses.
Failure Mode: When test 38 finds an error, it prints:
buserror berrNN spaceNN writeNN pageOxAA
Test 39:
Page permiSSions off - This test tums off permission bits, then
tries a number of accesses to ensure permission bits disallow
accesses.
Failure Mode: When test 39 finds an error, it prints:
mismatch berrNN expNN fcNN wNN pageOxAA
no buserror!! fcNN wNN pageOxAA
Test 40:
Page invalid - This test anem,pts an access to an invalid page, then
verifies the bus error.
Failure Mode: \\'hen test 40 finds an error, it prints:
SOof31 October
19~
50
Sun·USO Field Service Manual
mismatch berr NN expNN paqeOxAA
no buserror!! paqeOxAA
Test 41:
Interrupts - This test checks interrupt levels 1 thorugh 3 and 5
through 7 to ensure they occur. Level 7 uses the 9513 timer
(ourS), level 6 uses the sec, level Suses the 9S13 again (OlIT4),
and levels 1 through 3 use the system enable register to FlCrate
their interrupts.
Failure Mode: When test 40 finds an enor, it prims:
Got level X instead of Y, or
No interrupt on level X
Video Menu Tests
Register test
sets the video, copy, and inteffilpt enables, and the copy base. It reads these
and the other known bits in the video control register back, then checks to
ensure that the settable bits read the way they were written.
(Video) memory test
runs a series of general memory tests on the video frame buffer. TIllS TEST
CA USES PATTERNS TO APPEAR ON THE VIDEO MONITOR.
(Video) copy test
runs a series of general memory tests on the video frame buffer using copy
mode. It then checks both the frame buffer and the memory written. THIS
TEST CAUSES PATTERNS TO APPEAR ON THE VIDEO MOJ\'ffOR.
Ethernet Menu Tests
Diagnose
The diagnose test sets the 82586 chip initialization then tries to do it. If the
reset fails, the test loops on the reset.
Loop tests (local, encoder, external) - These tests do localloopbaoo.
local
does internalloopbacks in the 82586
encoder
does loopback through the 8502 (sends headers only)
external
does loopback through the Ethernet cable (sends headers only and requires
cable and functioning Ethernet).
Failure Mode: Loop tests note any deviation from expected results and
dump relevant data structures. External loop test fails if Ethernet is not
connected right.
Dump test
dumps the data and command structures used ty the 82586 in memory. The
results of this test are beyond the scope of this document.
50 of 3 J October 1984
Chapter 2 - Diagnostics Ind Troubleshooting
Memory Menu Tests
S1
map - Detail to be provided
pattern - details to be provided
.'i
address/unique - details to be provided
Failure Mode: Memory tests loop when they detect failures.
2.S. St3nda1one Programs
Standalone programs get their name from the fact that they run in a standalone
environment, without UNIX. They are booted manually while the workstation is
under control on the monitor. after irs autoboot procedure is interrupted.
As troubleshooting tools. standalone programs have two major advantages over
programs that run under UNIX:
a) UNIX restricts access to facilities that these programs need, and
b) often when standalone programs are required, the system isn't running well
enough for U1\lX to run properly.
Em'ironment
Standalone programs require a fairly high level of system functionality to run
effectively. The monitor program must run, and the path to the standalone programs over the Ethernet must be functioning. If these conditions cannot be met,
use other troubleshooting tools described in this chapter.
To activate the monitor's command interpreter, power-on or reset the system.
When the message:
Auto-boot in progress
appears, press either:
Ll-a
(while holding down "LI", press "a") from the keyboard,
kl (press "k", "}", then ""-;.:3
;'.1
~OO'O15
:-: y~
~cc
~
pr~{ ":'
5~I"s
"'::
....
(
M68:0
pe"o~I"I\
t
i..=
~
,;,
~
-
!
:.
;
~
~
)
"
5'91'10' "'amt
.. . .....
-. '::wa
..
::
I : c', '7
.
il".!
L
:,
...
...
.. : , .. j ..... ~=:!
i ,':, .... :. :: ... O~I:'\
1-=_: :-':~-
"'C.,......"
'.
:"'; ... '
c:-;
~
Le .. t
...
..-... "
0.':"
o·
,'': ... :
f":
CI.J~~ ... ~
._.;.
.
'
I
~.f
..::::.s!.
;""I~"'''''I -CoO'e!s
""'~O:~ :., Ce:o '..It:;,Jl
C, .. <"
1··t?~C""
"."'"
...
..
lr:: ...
... - ... '
~-
0
•
Out:u\
.. e:". . ",,
F:=:
--==
:.
w
: ... :: ..
R'V';
, =.' "'t;::.::s:-..... ,
:: .. 1
C.::,
:
~;
:. :.,.. :a'3 .::~~
.:"'S·~· .. :.,.·0 .... t":;!
~"":
II"I0u"0"I::>ul
:':
~~
1/,"1f
:.. ::'!"
Con,'oo
MnemoniC
-.:.: ... ..s e. 0
.. '! .!
_c.:
"
ContrOl
~'nt."uct
..
< -..
ContrOl
.
}B~$ A,Oolflloon
-.
~
Svst.'" "
.. : :.~!..!
lI"s
CGI"'OI
;-:-l
ConltO:
-
'
--::. ,
'.-"
........
I
1":_
Inp ... ·
In: ...
At:,..."
-- "
... :
.
5:atf
...
;'~.lO
...
..,
..
.~
..
"'~
VtS
-0
.~
..
.
-
Le·.
::."
..
~O
...
.0lC'"
Lo.....
.
lnO;.;~/OI.o.·:_:
lo ...
1>,,:-
.",:
l"OIJ~fO..::: 11
~e""
,,"c'
"c'
0,,10 ... t
Ou'c.'
~Ie·
~o
I
I"Cwl
LO"
I
O_tOwl
".;~
I
C~~
I
l"'O~t
"-9-,
rO#lllrI!'° "'':) ... 1
"CC
C':: • .,:
Go,:::;
I
I
Ino..,;
I
,":J",'
Ne
"'~
..
I
....
,..
~c"";_i.
'f'
.:
I
-.
.:~- F -'
c-
'r'f!!
\·o'·.l~:"C
~:
Z
0' ""-I.. .
I
f
""c,
.... !
I
"'c
I
... ·5
i
,
I
• ::.:;IIIt~ 0,.·"
.so of 31 OclOber 1984
Appendix E - Manufacturer's Component Data
101
Z8530 Serial Communications
Controller
F.atur••
CeDerc:1
Desc:nptlo::1
• Two Incependent. 0 to 1M bd/second. Jull·
duplex cnanneis. eacn with a separate
crystal oscillator. baud rate generalor. and
OI:;I:al Phase· Locked Loop for clock
recovery.
• Multl·protocol o;:erahon under pr:cram
ccn:ro!: programmable lor NRZ. NRZI. or
fM cata enco::ilnc;.
• Asynchronous mode with hve to eight bits
and o:o:e. one anc one·ho!l. e: two stop c:!s
per cne~e:::!er: progl'om:naeie clock jae:::::
brea~ oe:e:::::::n a::.c c;enerolio:-:: p<'lrl:y.
overl'..:n. and lrarnJnCjl errer Cet£ctlon.
the :::3: S.:~ Serial Cor::.mum:::<'Itlons
CO:lIrc;;e: IS a cuaj·c:i':a::.::.ei. r::.uitl prolo::o!
da!:! c:::::':::'1.ln:calle::s pe::t:herai cet:c;nec lor
use WI!:: e:::we::.tlcnal non·multlple1.ec cuses.
The S~C h.:n:::t:c::.s as a senai·to·pa::lliei.
.. .
. CC:"lve:"te:"/co:",.:~c:.e·. ,roe
pa:-c!ue
. ·to . s~r~3:
S=C c.!~ be sc:tware-con:;;u:-e:::l to Se~ls.:y a
-
,~
.... T. IUS 1 ___
.us
1=
0-
ttO"
c,
.,OA ...--1 DAt.
1'r."n
~,
ar:n _'ca.oe- .. ,
-1
c.
0,
~
• tto.
c,
iT."i(w.
~,
am
0,
no
Ii!:
".M'lIte
.... D"'SIT ( - i"i
... i
Ci
CO_TAO"
1 - 00
1--...
m&
hOI
~=
,Nn ••
u.,
I sr-'AL
--- t CM ..... [L
1= -'
•• 01
r.r.n
i'i":'ri
s;;:.
I~
w:ii":i
'f'
'10
".'.'''1
lin.
ace
·n ."0
m.
,
em
Rii
e .. &
• eM ....d\.
_lOA'.
'L
Co.,aOLI
~O. IOOOE ••
0 ..... 0.
-
0''''''
t:l
~=.,
ii;5
•• 0 _ _
- - t C ....f11I~ ...
____ • CLOCA.S
~
.0I.e,
c: '
.. e 1
., c·
;;t C •
• -.;.&
I sr.'AL
-It
wlce variety 0: senai co:r.mu::'lcaIlO::'s .PJ'hc<'l·
ho::.s. The deYlce co::.:a;ns a varle!y oj new.
sophls:lcated I:'!:e~r:el 1'...l:1ct;c::.s mciuc~l'I:;
on·chlp bauQ rale c;:er:.eratcrs. O:cllal PhaseLcckeo Locos. arlC crys:al os=:l;a!o~s that
dr<'l:::.atlc/lliY re:-..:ce :::e nee: l::r extemai
10:;;1::.
... =,
C
=
OT"llll
e ........
• Local Loepeac;; and Au!o Echo modes.
0,
'"
c.
:,
i;
;0
ICO
f Olll.oa
,oa "00'_.
-,
• SOl.C/HOLC mode with comprehenslYe
frame· level control. automatic zero lnSerhon
end deietlon. I· field reslaue handline;. aaOl't
qene:atlon ana ae!eC!lon. eRe c;enerahon
and cnecitlng. and S::"C Lecp moo.
operahon.
C'
.. ,.:;..'.. C:'
c: •
I co·.. aot.S
__
• Synchronous mode with Internal or extemol
character synchronlutlon en one or twO
synchronous characters and CRC qenera·
bon and cnecitlng with CRe·IS or
CRC·ecrrr preset 10 either 11 or Os.
fa."C&
e ..·•
'I
')
t: ,.
C·,
iii"~=
t •••
iiii
'.
C"
iCiii
C"
mac,,·
~.
..I
;J
uno
aee
to
="'0
....-0.
~.
ii7Ci
-.0.
'"i':Ci
hDI
0......
tiiii
Fii
iiii
~u
Flgur. I. PID r uftcllofta
Flgut. 2. PI. A...' ••••,.
so 001 October 1984
102
Sun-USO Field Service Manual
AM78073 System Timing
Controller
DlsnNcnVE CHARACTERISTICS
• F",.
GENERAL DESCRIPnON
The AmZ8073 System TimIng Controller IS an LSI areull de
SIgned to seMCe many types of Counllng. St'Quenclng and t,,,,,.
in9 aPf)lltalions n provlOes the caoaDtkly 10< programmCle Ire
Quencv SynlheS'S. hlgn resotuhon programma01e CIItV cyel,
..avelorms. rel"ggeraOfe 1I'9<1a1one-snals. '.me-ot-1 t>,.
II.-G:;'·P)
..... -.----~
~--------------------------------
iiiiiiiiiiiiiiiiiilt:=Jl~l
fJ.i}....
" iiIiiiiiiii.i-""
,fo' lee." Iype .no.. connectors. SOl.,.' ~rnte'
conductor If! conlact 9'00..e CIOS. access oPt'n.,,;
B.
5.
W,lh CS.eleCl"e 'u", i.g I"", chelectric 10 dimension
conduCIOr to c:"mens.on "0." Asse",ble
Intem,l o-fing seals Ind Spacer, when prov,ded, as
shOwn Oelo.., When clble poSlhon.ng .nsulators .re
used Id,uSI tllm code c"menslOns IS "hown belOw, and
ass.m!)I' as rnd'Clled
"c." Cut cenler
CODE
2011.
221A
TRI"- CODE r.HART
J
I
e
I
CO,
\?
n7
I
,"0
--l..~
A
l~ •
h~
.371
',,,
so of 31 October 198.!
J
H
MUX Box Specification
MUX Box Specification ....................................................................._..._....... _.._................. lIS
H.l. Installation Requirements ..................................................................................... _...
116
H.2. ML'X Box (2110) Installation .................................................................................
116
H.3. 211 O-BO Module Installation ............................................................................_.....
117
HA. 2110-A0!2110-BOModule Operation ........................... _....................................
117
H.5. Specifications ....................................................................................................................
118
H
MUX Box Specification
This appendix supplies information on the installation and operation of the 2110
Multipon Transceiver (MUX box). The MUX box is used to expand the number
of stations per transceiver in an Ethernet local area network. A single 2110 Mt:X
box can operate an independent network of up to eight stations. NIne MUX boxes
may be cascaded to create a 64-station network, which can operate either
independently or connected to the Ethernet (via a TCL Model 20lOE series transceiver. see Appendix I)
115
so of31 October 198-!
,ll,6
Sun·21S0 Field Service Manual
• 11SV, 60Hz power supply
• Appropriate transceiver cables (refer to MUX box specifications).
• TCL Model 21IOE series transceiver (if MUX box is to be connected to an
Ethernet cable).
• TCL Model 211O-AI mininet adapter(ifMUX box is to be operated as an
independent network).
• Sufficient airspace surrounding the MUX box to allow for adequate ventilation.
H.1. Installation
Requirements
H.2. MUX Box (2110)
Installation
1. Refer to Figure H-I for acceptable netwolt configurations. Note that MUX
boxes whose 2IIO-AO modules are connected to a 2IIO-BO module of
another MUX box can only have stations connected to their 2110-80
modules. Multiport transceivers whose 21lo:.AO module is connected to
either a 2110-AI 'mininet adapter or to a 20lOE series transceiver may have
either stations or a MUX box connected to its 21IO-BO module.
211Q
CCIIN[M 211 o-ao MOCUU!
TO [JTP.[' 2110-A1 O~
TO TAAHSC&lVU UBU
2CIO
'rV.NSCUVU
ItTH!:RN!,;':'
COAXIAl.
CAaU
ALL CONN!!C'TIORS ,WITI TDE UC'EnIOli OP
Tae 2110-Al ADAPTER walea CONN~
DIRtt'TLl' J ME MADE WITI TRANSCErvat
CJUlLES .,BOSE AAUHUM U:NC1'8 11 S' IlEnAS
Figure H-l
Network Configurations
2. Use transceiver cables to connect the stations. multiport transceivers and
series transceivers as required. Transceiver cable length must not exceed 50
meters. If the installation is an independent network. connect the mininct
SOor31 October 1984
Appendix H - MUX BOlt Specification
117
adapter directly to the 211O-AO module.
3.
H.3. 2110·80 Module
Installation
H.~.
2110·AO/2110·BO
Module Operation
Apply power. Note that the transceiver cables may be installed and removed
with power applied to the MUX box.
1. Remove the blank face plate (2110-00) by unfastening the screws at the top
and bottom of the panel.
2.
Insert the 2110-BO module in the multipart transceiver chassis with the
screws removed in step 1.
3.
Blank face plates (2110-00) should be installed over all unused module slots
to ensure compliance with the FCC regulations governing radio frequency
interference.
When power is applied, the LED in the 211O-AO module will light. indicating
that the unit is operating correctly. If the LED fails to light, first check the fuse
and then verify that the correct voltage is present If these checks fail to uncover
the problem, the module is faulty.
An unlit LED on the 2110-BO module indicates one of the follOwing conditions
- the module is not connected to a station
- the station the module is connected to is in continuous transmission mod..:- station power is turned off
SO of 31 October
19~
118
Sun·2/S0 Field Service Manual
H.S. Specifications Function
2110/
211O-AO
Nominal
DC Offset
Signal
Range
Load
Resistance
Output
Transmit+
Transmit-
+4V
+4V
+/.fJ.6 to +/.fJ.9V
+/.fJ.6 to +1.().9V
780hm
780hm
Input
Receive+
Receive-
+/-IOV·
+I-IOV·
+/.fJ.5 to +1-1.0V
+/.fJ.5 to +/-1.0V
780hm
780hm
Input
Collision+
Collision-
+/-IOV·
+/-lOV·
+/-O.S to +/-l.OV
780hm
780lun
+/-0.5 to +/-l.OV
Connector: IS-pin D-subminiture female with slide lock Power: 100-130\'.
60Hz. 27VA Size: IS.S"W x 8.S"H x 8.0"0 Weight: 13.Slbs LED: No light
indicates no power.
Function
211O-BO/
DC Offset
Nominal
Range
Signal
Resistance
Load
Input
Transmit+
Transmit-
+lOV·
+10V*
+/-O.S to +/-I.OV
+/-0.5 to +/-1.0V
780hm
780hm
Output
Receive+
Receive-
+/4V
+/-4 V
+/-0.6 to +/-D.9V
+/-0.6 to +/.fJ.9V
780hm
780hm
Output
Collision+
Collision-
+/-4V
+/-4V
+/-0.6 to +/-0.9V
+/-0.6 to +/~0.9V
780hm
780hm
Connector: IS-pin O-subminiture male with locking posts Power: 9.8 to
lS.5VOC. 450ma MAX. Size: l.S"W x 6.7S"H x 3/8"0 Watchdog Timer: 40 to
80msec LED: No light means no power/transmission from station exceeds
SOmsec nominal/intemal fault detected Collision Presence Test: 0.3 to 3.Ouscc
following end of reception. three cycles minimum
• Input circuits will track the common mode voltage or the received signals.
50 oDI OclObcr 1984
I
Vampire Transceiver Box Installation
Vampire Transceiver Box Installation ......................................................................... 121
1.1. Tools and Equipment Required .................................... _..........................................
122
1.2. Transceiver Installation ......................................... _..............................................._.....
122
I
Vampire Transceiver Box Installation
This procedure provides the infonnalion necessary to install additional Ethernet
(Vampire) transceivers in the field.
121
so of31 OclObe~ 19&!
J22
Sun·2150 Field Service Manual
1.1. Tools and Equipment
Required
• 9/16" open-end or adjustable wrench
• TO. Coring Tool Kit (TCL AOOO3-DS-O)
• Vampire Transceiver Box (To. 2010ECS)
1.2. Transceiver
1.
Installation'
Oamp the tap block (TCL AOOO3-CO-l) to the Ethernet cable with the
threaded hole in the block facing upwards. Refer to Figure 1-1.
2. Place the clear plastic shim (TCL AOOO3-HO-O) on the Ethernet cable with
the gap in the shim facing upwards. Center the tap block on the shim (refer
to Figure 1-2). wcare the tap block in an area where it will not contact
grounded objects. such as conduit or piping.
Figure 1-1
Tap Block
50 of 31 October
19~
Appendix I - Vampire Transceiver Box Installation
Figure 1-2
1:!3
Shim Placement
TAP BLOCK
I
SHIM
3.
Tighten the 9/16" tap block nut.
4.
Screw the cable coring tool (TCL AOOO3-DO-l) into the threaded hole in the
tap block until the tool bottoms out, then remove the tool from the tap block.
Repeat this process several times.
S.
Insen the shield removal tool (TCL AOOO3-DI-O) into the hole in the tap
block. Rotate the tool to cut through the cable shielding. Use a scribe to
remove any shielding material or ground braid remaining in the hole.
Failure to remove loose ground braid from the hole may cause a shon in the
Ethernet cable when the transceiver is installed. This condition will bring
dOVon the entire network.
6.
Screw the piercing tool (TCL AOOO3-02-0) into the threaded hole in the tap
block until it bottoms out. Contact with the conductor should be felt
Remove the tool and verify that a pinpoint of metal is visible through a
small hole in the insulation.
7.
Remove the protective cover from the stinger on the vampire transceiver box
and install the O-ring on the threaded stinger housing (refer to Figure 1-3).
SO of 31 October 19S-!
12.-
Sun-21S0 Field Se1Viee Manual
Figure 1-3
Transceiver Installation
8.
Carefully insen the stinger housing. on the transceiver box. into the hole in
the tap block. Screw the tranceiver into the tap block until the O-ring is
seated. Do not ovenighten the transceiver.
9.
Verify that there is +12VDC at pin 13 of the interface connector, on the transceiver box.
10. Insen the male interface cable connector into the corresponding female connector on the transceiver box (refer to Figure 1-3). Use the slide lock, on the
interface cable connector, to secure the cable to the box.
11. When power is applied to the transceiver box, the LED located on the rear
panel of the box should light. If the LED fails to light, there is a problem
with the transceiver and it should be replaced.
so of31 October 1984
J
System Block Diagram
System Block Diagram ......._..___.__._.__........__......__.... ___.__...._._._______ 129
J
System Block Diagram
POR
~i DTACK
- RST
J9R
~BG
~6ACK
953
I
l'~
eLK CIRCUIT
I
TIMER
ClJ\4S,152
MHz
129
500[31
OcLObc~
19&4
133
134
134
134
134
134
...... ~· •• u •••••••• u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... .
..............................................................................................
134
135
;.•.....•......•..•....•.................................................•..............
135
.. ·.. ··· .. ·..··..··..······ ..·.. ·..·..·.. ·..·..·..·..·..··............... .
135
St~·~~······
135
135
==::::=="::::==="::=::====::::===:"=:
136
K
Specifications
This appendix provides a summary of Sun-2JSO specifications mel features.
133
so of 31 October 19&4
13~
Sun·2J50 Field Service Manual
K.I. CPU
- M68010 16-bit. virtual memory microprocessor
K.2. Memory
- 1MB (64K) or 1M/4MB (2S6K) of main memory
- 1MB (64K) or 1M/4MB (2S6K) of expamion memory
- high-speed, no-wait state operation
- transparent hardware memory refresh
- byte parity error detection
- up to 128KB of EPROM
- software-readable ID PROM
K.3. Memory Management
Unit
- Sun-2 memory architecture
- two-level. multiprocess, virtual memory management
- full suppon for demand paging
- 16MBs of virtual address space per process
- separate address space for supervisor and user
- valid. accessed and modified tags to assist paging algorithms
- separate read. write and execute tags for user and supervisor
- direct virtual memory access (DVMA) from VME bus
KA. Display Subs~'stem
- dedicated. dual-poned video memory
- 1152 pixel x 900 line display fonnat
- l00MHz video clock
- 67Hz non-interlaced video refresh
K.S. Ethernet Interface
- VLSI Ethernet controller
- digital phase-locked decoder
- packets transferred directly in and out of main memory
- extensive diagnostic capabilities
K.G. Serial 110 Ports
- two programmable serial I/O ports
- based on synchronous communications controllers
- software-programmable baud rates (75 baud to 19.2 Kbaud)
- synchronous, asynchronous and bit-stuffing protocols
- two serial pons for keyboard and mouse
so of 31 OclOber 1984
Appendix K - specifications
K.7. Diagnostic Features
- diagnostic LED display
- bus error register
- watchdog reset timer
- bus timeout timer
K.S. VMEBus
Specification
Master Capabilities
- 8-bit/l6-bit data bus
- 16-bit/24-bit address bus
- l00usec timeout option
- '-level, jumper-selectable interrupt handler
-level 3 release-on-request option
135
Slave Capabilities
- 8-bitlI6-bit data bus
- 24-bit address bus
- no interrupter options
.H 3 "System Controller Capabilities"
- 16~1Hz jumper-selectable clock option
-level 3 bus request level
K.9. Power Monitor
Capabilities
- ASFAIL signal assened when voltage is below 4.5VDC
- system reset (SYSR) assened during CPU reset
- system fail (SYSFAIL) may be inhibited
K.IO. Environmental
Characteristics
- operating temperature 10-55 degrees C
- humidity 0-90% non-condensing
K.ll. Power
Characteristics
- 12.0 amp max at +5.0VDC +/-5%
- 0.5 amp max at +12VDC +/-5%
- 0.5 amp max at -12VDC +/-5%
500f31 Oct.ober
19~
136
Sun·2/S0 Field Service Manual
PhvsicaJ
~ Ch-aracteristics
• height SS.tern (21.7")
• width 53.3cm (21.0")
- depth 43.7cm (17.2")
- weight 20.4kg (4S1b)
500(31 October 1984
27
DIAGNOSTICS AND TROUBLESHOOTING
2.7. VIDEO MONITOR ADJUSTMENTS
This chapter describes how to perform video monitor adjustments. These adjustments may be
used to correct video problems, such as vertical scrolling or an incorrect image size, or they may
be used to simply improve the quality of the video image.
NOTE: This section is referred to as
in this chapter.
'-"3- in the Quick Reference TroubleshootiDg Guide-
These adjustments do NOT correct problems in the video controller circuits on the CPU board.
The Sun 50 comes with two types of video monitor; one by Phillips and the other by Moniterm.
In this procedure, both are treated the same; however, for further information, each has its own
manual. For manual part numbers, see the introductory material at. t.he beginning of this pre>cedure.
.
Both video monitors meet the following specifications:
Video Input -- Balanced EeL
Video Display - 1152 X 900 pixel display (1024 X 1024 optional)
Video Clk - 10 nsec, 100 MHz
Horizontal SYDC - 16000 usee, 62.5KHz
Vertical Sync - 15000 usee, 66.66kHz
Horizontal Retrace -- 4.48 usee
Vertical Retrace - 600 usec
WARNING: The video circuitry generatea extremely higb voltages, particularly
the output of tbe PKT hilh voltage lupply and the anode connection to the
CRT. To avoid injur)" be lure all power to the monitor is OFF before attempting repair••
CAUTION: To avoid damaging the video circuit., DO NOT ule a standard
.crewdriver to turn adjultment potl. Instead, u.e a Don-metallic adjudment
tool, allo called a pot adjuster or a tweeking tool.
NOTE: This manual only covers basic adjustments which do Dot require removing the mesh
screen inside the monitor rear housing. For more information, read the appropriate "ideo
screen manual.
The adjustments are on the defiection board mounted vertically to t.he right of the video screen
looking in from the back of the system with the rear panel removed.
1) Remove the set screws holding the rear cover on the workstation.
2) Read the description following this procedure, and perform any adjustments indicated.
3) When the adjustments are complete, replace the workstation rear cover.
4) If the adjustment fails to correct the problem, refer to the monitor's manual or return the
system to Sun.
DESCRIPTlO~
OF VIDEO MONITOR ADJUSTMENTS
Rey: A of 31 October 1984
Sun Microsysterru, Inc.
The Sun-2/50 Service Manual
28
NOTE: See Figure 2-1 lor adjustment pot loca.tions.
PI
HorllOS,.l VS.Ll
P2
IorUou.l
P3
'01.
Ver'lcal '01.
P4
V,rt.lcal .Iat
Pi
Vert.lc.l \op/)ot\Ce ls"arS'1
PI
Vtr'lcal lS,.arS'7
••
E
,.,
DC font
PI
IrS,,,....
rt
V,r'lcal DC
PIO
V,nlC&1 'J1IUle font
(f,c\orr
tae" 0111)
P11
IIorl_\al .,..ute font
ee'''rt',
ad, ••
(fae\orr adlutatn 01111)
•
II
Ii'
P'
•
•
10 •
Ijillilli'
•s ••
) •
Sfiljii
Figure 2-1: Adjustment Pots
PI - Horizontal width. This controls the horizontal left/right width of the visible display on
the screen. Turning the adjustment screw clockwise expands the frame; counter-clockwise
reduces the size of the video frame.
P2 - Horizontal hold. This controls the horizontal left/right movement of the video frame
on the CRT screen. Clockwise adjustment moves the image to the left; counter-clockwise
adjustment moves it to the right.
P3 - Vertical hold. This controls the top-to-bottom movement of the video frame as follows:
a) Turn P3 adjustment pot in one direction until the picture goes ouf.-.of-sync (rolls up or
down the screen).
b) Counting the number of turns you make, adjust P3 in the opposite direction until the
screen goes into sync, then out-of-sync in the opposite direction.
c) Turn P3 back in the original direction by half this Dumber of turns.
NOTE: This procedure provides a.n average position between the two extremes o{ vertical sync. The return adjustment usually requires around 5 or 6 turns.
P4 - Vertical size. Controls the top-to-bottom size of the video frame. Clockwise motion
expands the video frame; counter-clockwise motion contracts it.
P5 - Vertical top-t.<>-bottom linearity. Controls the relative size of the image at. the top and
bottom of the screen compared to the image in the middle of the screen. Clockwise adjustments make the top and bottom images relatively larger; counter-clockwise adjustments
SUD
Microsystems, Inc.
Rev: A of 31 October 1984
DIAGNOSTICS AND TROUBLESHOOTING
29
m~ke them relatively smaller.
P6 - Vertical linearity. Controls the size of the image ofer the entire screen area. Clockwise adjustment moves the top and bottom edges away from the center; counter-clockwise
adjustment moves them closer.
P7 - DC focus. Controls the sharpness of t.he overall image. Fill t.he screen with aD image,
then turn the pot until the image is sha.rpest. (generally around t.he center of t.he adjustment).
P8 - Brightness. Controls the contrast. betweeD the light and dark areas of t.he screen.
This adjuatmeDt ahould Dot Dormall7 be performed ID the field, u illcorred
adjultmeDt caD damale the picture tube. The remot.e brightDess adjust.ment pot,
located on the exterior of the Model 50, is normally used for adjusting brightness.
pg - Vertical DC centering. Controls the up-down position of the video frame on the
screen, Turning the pot clockwise moves the ima.ge down, and turning it counter-clockwise
moves the image up.
PlO - Vertical dynamic focus. NOT FIELD ADJUSTABLE
Pll - Horizontal dynamic focus. NOT FIELD ADJUSTABLE.
NOTE: Bleeding characters indicate possible dyna.mic focus problems. Adjusting P1 sometimes corrects this problem.
.
Rey: A of 31 O('tober 1984
Sun Micros)'St.ems, Inc.
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