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MAINTENANCE
MANUAL
J
;
8025 CRT TERMINAL
MAINTENANCE MANUAL
OMRON CORPORATION OF AMERICA
INFORMATION PRODUCTS DIVISION
432 TOYAMA DRIVE, SUNNYVALE, CA. 94086
(408) 134-8400 TWX 910-339-9341
No information contained herein may be
reproduced or disseminated to any person
or company without the express written
permission of Omron Corporation of
America. Information Products Division.
October 1, 1975
OMRON PIN 88-036-XXX
(U)
FOREWORD
This manual gives accurate, usable information to help you get the best
service from your 8025 CRT Terminal.
It supplies you with the details needed to:
•
become thoroughly familiar with the 8025
•
operate the 8025
understand how the 8025 operates
•
service the 8025
We have taken care to make this manual as complete, accurate,' and understandable as possible. Your comments and suggestions for increasing its quality
and effectiveness will be most welcome. A convenient, pre-addressed "Publication
Change Request" form for this purpose is provided on the next page.
To receive updated materials, ~our manual must be registered with Omron.
A pre-addressed form is also supplied for this purpose.
(iii)
TABLE OF CONTENTS
PAGE
SECTION
1
List of Figures
xiv
List of Tables
xvi
·
General Information
·
_1.1 General Description
1.2
1-1
1-1
1.1.1 Functional Description
1.1. 2 Mechanical Description
1.1. 3 Basic Operation
Specifications
1. 2.1
·
·····
....
.....
Standard Terminal Specifications
1.4
1. 3.1
1. 3.2
1. 3. 3
1. 3. 4
1. 3. 5
Repair
Claim for Transit Damage
Statement of OM RON Warranty
Warranty Claims Against OMRON
OMRON Designated Facility
Suppliers Warranties
and Return of Equipment
1. 4.1
1. 4.2
1. 4.3
P"olicy · · ·
·
·
Equipment Failure
·
Non-repairable Determination
Equipment Return Procedure
Packing and Packaging Procedure
·
1-4
1-4
·· ·· ..
Warranty Information
1.5
1-1
1-2
1-3
Of
1.3
1.4.4
1. 4.5
2
···
·····
1-8
1-8
1-8
1-8
1-9
1-9
1-10
·
1-10
1-10
1-10
1-10
1-10
· ·
List of OMRON Mnemonics
1-12
Installation and Checkout
2-1
2.1
Unpacking Procedure
2-1
2-1
2-1
2.2
Inspection
Unpacking
·
•
Off-line Checkout
2.3
2.2. 1 Mechanical Inspection
2.2.2 Operational Check
Installation .
2.1.1
2.1.2
····
2.3.1
2.3.2
2.3.3
2.3.4
2.4
2-2
··
2-7
....
·
Physical Requirements
Electrical Requirements
External Connections
RS-232 Speed Adjustment
On-line Checkout
2-2
2-7
....
..• .
·······
Ox)
2-7
2-7
2-8
2-8
2-8
TABLE OF CONTENTS
(continued)
SECTION
P
3 Operating Instructions
3.1
3-
Operating Controls.
3.1.1
3.1.2
3.1.3
3.1.4
3-
...
On-Off Switch.
Brightness Control
Baud Rate Switch
Parity Switch
333-
3-
3.2
The Display Screen.
3-
3.3
Audio Indicators.
3-
3.3.1
3.3.2
33-
The Click Sound
The Beep Sound
3.4
Visual Indicators
3-.
3.5
Basic Operating Modes
3-,
3.5.1
3.5.2
3.6
3-:
3-:
....
.. (-{
Keyboard Keys
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
3.7
KSR Mode
ASR Mode
Operating Features
"Typewri ter" Keys . .
Numeric Pad Keys
Escape (ESC) and Control (CTRL) Keys
Cursor Control Keys . . . . • • .
Next Line (.J) Key . . . . .
Function Keys and Indicators
I~dividua1
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7
3.7.8
3~7.9
3.7.10
3.7.11
3.7.12
3.7.13
3.7.14
3.7.15
3.7.16
3.7.17
3.7.18
3.7.19
3.7.20
.
3- i
'C~',)-i
•
3-L1
3-4
3-4
3-4
3-4
Key Descriptions
3-5
A1phanumeric-Punctuation-Symbo1 Keys
Store Input Key/Indicator . . .
Storage Transmit Key/Indicator
KSR Mode Key/Indicator
Print Key
Store Key . . . .
Read Key . . . .
Keyboard Disabled Indicator.
Received Parity Error Indicator
Frame Transmit Key
Local Copy Key/Indicator
Break Key . . • •
Reset Key . . . • .
Screen Erase Key
Control (Cl'RLJ Key
Shift Key
Lock Key
Space Bar.
Tab Key.
Line Feed Key
(x)
3-5
3-5
3-5
3-5
3-6
3-6
3-6
3-6
3-6
3-7
3-7
3-7
3-7
3-7
.... 0
.' .
3-7
. . Ii.....:8
. V8
3-8
TABLE OF CONTENTS
(continued)
SECTION
3.7.21
3.7.22
3.7.23
3.7.24
3.8
PAGE
Carriage Return (CR) Key
Delete (DEL) Key . . • .
Backspace (BS) Key
Cursor Control (HOME and Arrow) Keys
3-8
3-8
3-8
3-8
Operating Procedures . . . . .
3.8.1
3.8.2
Turning the Terminal Qn and Off
Clear/Reset Functions
....
4 Theory of Operation
4.1
4.2
4.4
3-11
3-11
4-1
Terminal Block Diagram Analysis
4-1
4.1.1
4.1.2
4-1
4-4
Timing, Control, and Data Signals.
Typical Operating Sequences . . •
8025 CRT Terminal Input/Output Structure
4.2.1
4.2.2
4.2.3
4.3
3-11
Memory Cards . . . . . . . . . .
Program-Processor Controlled I/O Cards
DMA Transfer I/O Cards
....
4-6
4-6
4-16
4-16
Character Generation . . . .
4-17
4.3.1
4.3.2
4-17
4-20
Upper Case Characters
Lower Case Characters
Card/Section Descr"iptions
4-21
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
4.4.10
4.4.11
4.4.12
4.4.13
4-21
4-23
4-29
4-39
4-45
4-47
4-48
4-56
4-58
4-62
4-67
4-71
4-79
Power Supply
CRT Display . . . .
Timing Control Card
Processor Card
PROM Card . . . . .
Buffered RAM (Refresh) Memory Card
Refresh Buffer Card.
Refresh Control Card
Cursor Control Card
Video Control Card
The Keyboard
RS-232 Interface Card
Terminator Card . . .
5
(Not Applicable to 8025G Terminal)
6
Maintenance and Repair
6-1
6.1
Preventive Maintenance
6-1
6.1. 1
6.1.2
6.1. 3
6.1.4
6-1
6-1
Obj ecti ve . . • .
Required Equipment and Materials
General Procedure .
Specific Procedures . .
(xi)
6-1
6-2
TABLE OF CONTENTS
(continued)
. SECTION
6.2
Field Maintenance
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.3
6-3
Objective . . • . • .
Required Equipment
Rules of Good Maintenance . . .
Field Troubleshooting Procedure . .
Removal and Replacement Procedures
6-3
6-3
6-4
6-4
6-13
Bench Maintenance
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
"'-6.3.6
6.3.7
6.3.8
7 Adjustments
8
PAGE
6-19
Objective . • . . . . . • . . • •
Required Equipment and Materials
Rules of Good Maintenance .
Replaceable Parts . . . • . . • .
Workmanship . • . . . . • • • • . .
General Troubleshooting Procedure
Specific Troubleshooting Procedures
Removal and Replacement Procedures
•
.6-19
6-19
6-20
6-20
6-20
6-21
6-22
6-52
"#
.
7.1
Required Equipment
7.2
+5 V dc Regulated Output
7.3
Click/Beep Volume
7.4
CRT Disp1ay.Adjustments
7-2
7.4. 1 Preliminary Procedure .
7.4".2 +55 V dc (B+) Adjust
7.4.3 Video Gain .• • . • .
7.4.4 Vertical Adjustments
7.4.5 Horizontal Adjustments
7.4.6 Centering Adjustments
7.4.7 Yoke Adjustments
7.4.8 Focus . . • • .
7-2
7-3
7-3
7-5
7-5
7-12
7-12
7-12
"
Drawings
7-1
8-1
CUl'sor Control Card
Display Monitor
Keyboard . .
L.E.D . . . .
Mother Board
Power Supply
Processor Card
PROM Card
RAM Card . . •
Refresh Buffer Card
Refresh Control Card
Regulator Card .
RS-232 Interface Card
.
8-1
"
8-3
8-5
8-7
8-9
8-11
8-15
:~"
8-21
g
8-27
(xii)
TABLE OF CONTENTS
(continued)
SECTION
PAGE
Terminator Card
Timing Control Card
Video Control Card .
9 Component Parts List
8-29
8-31
8-33
. . • .
9-1
Cursor Control Card
Keyboard •.
.. • •
L.E.D . . . •
Mother Board
Power Supply •
Processor Card •
PROM Card
RAM Card . . •
Refresh Buffer Card
Refresh Control Card
Regulator Card . • •
RS-232 Interface Card
Terminator Card
Timing Control Card
Video Control Card
9-1
. . . ..
9-11
9-12
9-13
9-14
9-15
9-16
9-18
10 References
10-1
10.1 EIA Standard RS-232.C
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
10.1.6
10.1.7
10.1.8
9-3
9-4
9-4
9-5
9-6
9-7
9-9
10-1
Transmit Vata (BA), Pin 2
Receive Vata (BB), Pin 3
Request to Send (CA), Pin 4
Clear to Send (CB), Pin 5 .
Data Set Ready (CC), Pin 6
Received Line Signal Detector (CF), Pin 8 .
Data .Terminal Ready (CD), Pin 20
Ring Indicator (CE), Pin 22 .
10.2 ISO Character Assignments
10-1
10-1
. 10-1
10-1
10-1
10-1
. 10-1
10-2
10-3
10.2.1 Mne~onics and Their Definitions
10.2.2 The ASCII Code
10.2.3 Tape Track Assignments
10-3
10-4
10-5
List of Abbreviations
A-I
Glossary
G-1
(xi it)
LIST OF FIGURES
FIGURE
PAGE
....
1-1
Keyboard arrangement • • • • •
1-2
1-3
Exterior of 8025 CRT terminal
1-2
Interior of 8025 CRT terminal
1-3
8025 CRT terminal, simplified block diagram
1-3
Cabinet mounting screws (front)
2-1
Cabinet mounting screws (rear) . • • • • •
2-2
CRT display high voltage circuits (mounted below Monitor
Deflection Board) ••• • • , • • • •
2-3
Printed circuit card locations • • •
2-4
Monitor Deflection Board connections (viewed from top of terminal) • 2-4
Flat cable connections • • • • • •
2-5
Flat-line connector configurations •
2-6
8025 CRT terminal: rear panel connectors
8025 CRT terminal keyboard • • • • •
3-9
4C;
8025 CRT terminal block diagram
Example of upper case character (H)
4-18
Example of upper case character (V)
4-19
Example of lower case character (h)
4-20
Example of lower case character (p)
4-21
Power supply block diagram
4-22
CRT display block diagram
4-24
CRT waveforms
4-26
Timing control card block diagram
4-31
Timing control card timing diagram .
4-33
Timing control card timing diagram
4-35
Processor card block diagram • • . •
4-40
Processor card (CPU) timing diagram
4-43
Buffered PROM board block diagram •
4-45
Buffered RAM memory card block diagram •
4-47
Refresh buffer card block diagram
Refresh buffer/control card timing diagram •
Refresh control card block diagram • •
Cursor control card block diagram
4-59
(xiv)
1-4
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
1-1
2C-
..
..
4-C
..
:~~
fIGURE
.-20
4-21
4-22
4-23
6-1
6-2
6-3
6-4.
6-S
6-6
7-1
7-2
7-3
7-4
7-S
7-6
7-7
7-8
7-9
LIST OF FIGURES
(continued)
Video control card block diagram •
4-62
Keyboard block diagram .
RS-232 interface card block diagram
. . . . . . . .
Terminator card block diagram
• • • • • • • .
Cabinet mounting screws (front)
• . • • • .
Cabinet mounting screws (rear) • •
. • • .
Card cage
• • . •
Keyboard mounting screw locations
Monitor Deflection Board interconnections and mounting screws
CRT mounting bolts and high voltage connector
Regulator Card: +5 V de adjustment and test point locations •
Cursor Control Card click/beep volume adjustment location
Normal 8025 CRT presentation . . . . • .
• . • .
Monitor Deflection Card: CRT adjustment and "test point" locations
Vertical linearity adjustment (R109) incorrectly set .
Height adjustment (Rl07) incorrectly set . . • •
Vertical hold adjust~ent (RI03) incorrectly set
Vertical hold adjustment (Rl03) incorrectly set
Horizontal width adjustment (LI04) incorrectly set, brightness
4-68
control too high . . . . . . . . . . . . . . . . . . . . . . . .
7-10
7-11
7-12
7-13
7-14
7-1S
10-1
PAGE
4-72
4-79
6-14
6-14
6-15
6-16
6-18
6-54
7-1
7-2
7-3
7-4
7-6
7-7
7-8
7-9
7-10
Severe misadjustment of horizontal centering adjustment (R143)
7-11
Linearity sleeve inserted part way under yoke
7-13
Example of a horizontal centering problem caused by incorrect
setting of the horizontal centering adjustment (R143) or of the
raster ce~tering magnet discussed in paragraph 7.4.6 • . . • •
7-14
Correct setting of the horizontal (video) centering adjustment
(R143) and the raster centering magnets . • • • •
• • • • 7-15
Raster centering magnets • • . • . • •
7-16
Deflection yoke incorrectly set
. . . • • •
7-17
Tape track assignments for ISO/ASCII codes • •
• • 10-5
(xv)
LIST OF TABLES
TABLE
1-1
2-1
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13'
6-1
10-1
10-2
10- 3
p
8025 CRt terminal specifications .
Terminal-system interconnection
Visual Indicator On-Off States •
Control code generation in the 8025 terminal .
Sources and distribution of signals in the 8025 CRT terminal
I/O command decoder truth table
PROM.chip location vs. memory address
RAM chip location vs. memory address •
Video status functions • . . • . • .
Character generator ROM selection
• •
Video modification register (XC4) input-output parameters
X-v matrix switches and their functions
LED Keyboard indicators . . . . • . • . . • . . . •
•
"#
•
1-4
2-8
3-3
• •
....
3-1
4-9
4-3
4-4
4-4
4-5'
4-6.
4-6:
· . ~:
· . elf
Inputs and output states of command decoder (X02)
pi'
Status bits
• • • • • 4-7~
UA CLK Configuration for various baud rates
4-7f.
Program re?tart addresses provided by El-E6 jumper options
4-8(
Symptoms vs: probable malfunctions in 8025 terminal . . . .
6-7
RS-232C Pin Number - Signal Flow - Nomenclature relationship
. 10-2
ISO/ASCII Mnenonics and their definitions
• • 10-4
ISO Code . . . . . . • . . . .'. • . . . .
• 10-7
(xvi)
GENERAL INFORMATION
1.1
SECI'ION 1
GENERAL DESCRIPTION
The 8025 CRT Terminal is a versatile, simple-to-operate, self-contained
cathode ray tube (CRT) display with keyboard entry that is capable of performing
data processing functions. Capabilities of the 8025 cover a broad spectrum ••• from
simple teletype (TTY) replacement to ~tand-alone operations.
Primary application for the 8025 is as a remote intelligent interactive
terminal. In this role, it provides direct input of source data via keyboard entry,
in addition to editing, information retrieval, and visual display of both transmitted and received data.
1.1.1
Functional Description
The 8025 CRT Terminal is a computer system designed around an internal
1IIi.croprocesor (CPU) interfaced to memory. The CPU allows the terminal to be easily
adapted to many applications and functional routines without hardware changes. In
addition, data bus organization permits the 8025 to be interfaced to a wide selection of peripherals such as communications modems, auxiliary storage devices, and
. printers.
The 8025 Terminal has an ASCII (American Standard Code for Information
Interchange)96- or 64-character keyboard. Keyboard arrangement, shown in Figure 1-1,
conforms with the QWERTY format. In addition, there are 14 special function keys and
~ basic cursor control keys.
The terminal also has a l2-key numeric pad.
Figure 2-2.
Keyboard arrangement
1-1
GENERAL INFORMATION
SEcrrON
On 24-line-per-page terminals, up to 1,920 characters (80 charactersC,r
line) can be displayed on a IS-inch CRT display. Up to 960 characters can be nlSplayed on 12-1ine-per-page termdnals. The basic memory consists of a 1,024 byte
RAM (random access memory) refresh memory and a 2,048 byte PROM (programmed read
only memory) or ROM (read only memory) program memory. Communications I/O (input/
output) interfacing conforms with Electronic Industries Association (EIA) Standard
RS-232C. Additional RS-232 interfaces are included to interface the terminal with
a printer and an auxiliary m~mory.
Paragraph 1.2 gives complete specifications for the terminal.
1.1.2
Mechanical Description
External. Figure 1-2 shows tha ou~side of the 8025. The terminal is con
tained within a two-piece, free-standing plastic housin,. Its size, weight, and
design make the unit ideal for table or desk-top installation. Interfacing with
external equipment and primary power is done at the rear panel. Only five screws
need to be removed to take off the ~op sectlon of the housing. With this section
removed, the internal assemblies are easy to reach.
Internal. Figure 1-3 shows the inside of the 8025. Most of its circuitr
is contained in a card cage that accommodates up to 18 plug-in circuit cards. Immediately above the cage is the CRT electronic circuitry. CRT electronics are ('"
mounted on the chassis and circuit cards. A removable power supply assembly is ,yC;
ted behind the card cage, below the CRT. The keyboard assembly is also removable.
Figure 1-2.
Exterior of 8025 CRT terminal.
1-2
GENERAL INFORMATION
SECTION 1
Figure 1-3.
1.1. 3
Interior of 8025 CRT terminal.
Basic Operation
A simplified block diagram of the basic 8025 terminal is shown in Figure
1-4. For simplicity, the diagram shows internal communications taking place over
only one data-address bus.
MODEM
RS232
INTERFACE
-
AUXILIARY
STORAGE
RS232
INTERFACE
PRINTER
RS232
INTERFACE
t
t
DATA· ADDRESS BUS
•
MICRO
PROCESSOR
(CPU)
I
t
KEYBOARD
I
RAM
REFRESH
MEMORY
PROM
PROGRAM
MEMORY
CRT
DISPLAY
Figure 1-4.
8025 CRT terminal, simplified block diagram.
1-3
GENERAL INFORMATION
SECTION 1
Nearly all operations in the terminal are controlled by the CPU accorqf'~
to instructions stored in the program memory. Typical operation is briefly desc~e
in the following paragraphs.
The CPU periodically polls the I/O cards and other functional modples on
the bus to find whether any are ready to send or receive data. Assume the keyboard
has data for the CPU. The keyboard intercepts a poll and identifies itself to the
CPU. The CPU then enters the keyboard routine in program memory and enables the key
board to transfer the data.
Following program instructions, the CPU processes the data. If the data
is a character for display, the CPU determines where the next character is to be dis
played and stores it at that location in the refresh memory. The refresh memory can
then supply the data to the CRT display. If the data is a function code (e.g.,
carriage return), the CPU executes the instructions to move the cursor to the start
of the line in refresh memory.
"#
A data transfer from an I/O interface is performed in the same manner. In
this case, the interface intercepts the poll and identifies itself to the CPU. The
CPU enables the transfer and processes the data as if it came from the keyboard.
Assume the CPU has data for the interface. The CPU addresses, enables, an
sets" up the interface for the transfer. When the interface responds to the next
poll, the CPU places the data on the bus for the interface.
1.2
SPECIFICATIONS
1. 2.1
Standard Terminal Specifications
Specificati'ofls for the 8025 CRT Terminal are given in Table 1-1.
Table 1-1.
PARAMETER
8025 CRT terminal specifications
SPECIFICATION
8025 CRT Display
Screen Size
Nominal 8" x 10", 15" diagonal.
Safety 'Glass
Integral part of CRT face.
Phosphor
P4 (white, medium persistence).
Deflection Angle
Re fresh Rate
60 Hz.
Resolution
1,000 TV lines at 40 fL, center.
800 TV lines at 40 fL, corner.
0.010" diameter spot at center.
1-4
(l
o
GENERAL INFORMATION
7:'able 1-1.
SECTION 1
8025 CRT terminal specifications (continued)
PARAMETER
SPECIFICATION
Radiation
Complies with DHEW Rules 42-CFR-Part 78.
Mechanical
Integral part of 8025 Terminal.
Display Format
Scanning
Modified raster, 60 frames/sec.
Symbol Formation
Upper case and numerics, 7 x 7 dot matrixf 14 x 7
effective dot matrix with 1/2 dot shift provides
more natural-looking charactersf lower case, 7 x 9
dot matrix (7 x 7 displayable) •
Character Size
0.125" x .0875" (H x W).
Page Format
80 characters/line, 24 lines/frame (1,920 characters/frame max. displayable) or 80 characters/line,
12 lines/frame (960 characters/frame max. displayable) •
Character Set
ASCII, 64 or 96 characters.
Memory System
Display Refresh
RAM, 1,024 bytes.
Program
PROM or ROM, 2,048 bytes.
Keyboard
I/O Code
ASCII, 64 or 96 alphanumeric character.
Arrangement
QWERTY.
Numeric Pad
l2-key including decimal point and comma.
Cursor Type
Nondestructive blinking underline.
Cursor Control
6-way--up, down, left, right, home, and return left
to next line on "Next Line" (....J) conmand.
1-5
sEcrrON'
GENERAL INFORMATION
Table 1-1.
8025 CRT terminal specifications (continued)
PARAMETER
SPECIFICATION
Control Keys
14--carriage return, line feed, tab, delete, shift
lock, cursor controls, escape, and control.
Special Function Keys
l2--store input, storage transmit, KSR mode, frame
transmit, print, store, break, backspace, local
copy, read, reset, and screen
erase •
•#
Indicator Lights
6--receive parity error, keyboard disabled, KSR
mode, local copy, storage transmit, and store.
Input/Output
Modem Interface
RS-232 asynchronous - 110, 300, 1,200, 1,800 and
2,000, switch selectable.
ASR/KSR half/full duplex.
II-bit character, 110 baud.
10-bit character, all other rates.
Parity - odd, even, or none, switch selectable.
Printer Interface
RS-232 asynchronous - 1,200 baud standard; 110,
300, 1,200, 1,800, 2,000 selectable by internal
jumper option.
Auxiliary Storage Interface
RS-232 asynchronous - 1,200 baud standard; 110,
300, 1,200, 1,800, 2,000 selectable by internal
jumper opt.ion.
Operating Features
N-Key Rollover
No data loss when two or more keys are simultaneously depressed .
•
Acoustic Feedback
Programmable beep indicates that an event has
taken place, or is taking place, in the terminal
(e.g., end of line).
Automatic Repeat
Character repeats 15 times/sec if key is depressed
for 0.5 sec or longer.
(~
ir
Tab
Transmits TAB code in KSR mode.
Editing
Automatic character insertion at position indicated by cursor replaces previously recorded character.
/- C"
GENERAL INFORMATION
Table 1-1.
SECTION 1
8025 CIrr terminal sped !ications (continued)
PARAMETER
SPECIFICJlTION
Electrical
Input Power
115 V ± 11.5 V ac, 59-61 Hz, 300 watts.
Mechanical
Size
16" height, 17.5" width, 23" depth.
Weight
50 lb.
Mounting
Free standing.
Cabinet
Plastic, beige finish.
Environmental
Temperature
Operating, +5° C to 40° C ambient.
Storage, -40 0 C to +65° C.
Humidity
5 to 80%, noncondensing.
Altitude
10,000 feet maximum.
1-7
GENERAL INFORMATION
1.3
WARRANTY INFORMATION
SECTION
This section contains OMRON's warranty and explains the warranty policy
as it pertains to your 8025 CRT Terminal. Your 8025 Terminal was fully inspected
and tested for workmanship and proper operation prior to shipment.
1. 3.1
Claim for Transit Damage
It is important that the instrument be inspected for physical damage an
tested for proper operation (see Section 3) upon arrival at its destination. If i
does not operate properly, or is damaged in any way, a claim should be filed immediately with the carrier. A complete report of the damage should be furnished the
claim agent and a copy forwarded to OMRON. Do not proceed with repair; OMRON wil
advise you of the disposition to be made of the terminal and arrange for repair or
replacement. Please include name of equipment, model ffumber, serial number and
your purchase order number in any correspondence regarding the terminal.
1. 3. 2
Statement of OMRON Warranty
OMRON warrants to the original purchaser, for a period of three (3) mon'
from the date of shipment, that the 8025 CRT Terminal shall be free from defects il
material and workmanship, but does not cover shipping damage, physical abuse, fire
theft, damage incurred during field repair, or damage as a result of not fOllO~
. ~. .
proper preventive maintenance procedures.
~}
All parts and labor will be provided free of charge for three (3) ~~h:
at the OMRON-designated facility (see Paragraph 1. 3.4) with shipping being pa~lti.n
both directions by the customer.
The custo~er has the option of returning either the complete terminal,
individual assemblies, or components. All items will be system tested before return to the customer. A Merchandise Return Authorization should be used for this
purpose. (See the sample on page 1-11).
This warranty does not apply to fuses, lamps and other such parts for
which normal periodic replacement is required.
Vendor-supplied subassemblies and sealed units are subject to their individual warranties and cannot be opened or repaired by the customer during the
warranty period without voiding their warranties. Paragraph 1.3.5 provides informa
tion on such items used in the 8025 Terminal .
•
This warranty is in lieu of all other warranties, expressed or implied,
statutory or otherwise, including any implied warranty of merchantability. OMRON
shall not otherwise be liable to any inquiries, loss or damage direct or consequential arising out of the use or inability to use the equipment.
1.3.3
Warranty Claims Against OMRON
When making a warranty claim on your 8025 CRT Terminal, follow the rO
pair and return policies outlined in Paragraph 1.4 of this manual.
1-8
SECTION 1
GENERAL INFORMATION
If damage to the 8025 Terminal has been caused by improper use, abnormal operating conditions, improper maintenance or other factors excluded by the
warranty, repairs will be billed at cost. In such cases an estimate will be submitted before the work starts.
OMRON Designated Facility
1.3.4
The following facility is authorized to repair the 8025 CRT
Terminal:
OMRON Corporation of America
Information Products Division
Field Service Department
432 Toyama Drive
Sunnyvale, Ca. 94086
1.3.5
Suppliers Warranties
Vendor-supplied subassemblies and units used in the 8025 CRT Terminal
which are covered by supplier warranties are as follows:
Item
CRT Display
Supplier
Miratel
1-9
Warranty Period
12 months
GENERAL INFORMATION
1.4
SECTION 1
REPAIR AND RETURN OF EQUIPMENT
1.4.1
Policy
OMRON shall provide maintenance (labor and parts) and shall keep the
equipment in good operating condition. Maintenance shall not include repair of
damage resulting from accident, transportation between sites, neglect, misuse,
failure of electrical power or air conditioning or humidity control, or cause
other than ordinary use.
1.4.2
Equipment Failure
When equipment failure occurs, regardless of cause, and the equipment is
determined to be non-repairable on-site, it shall be returned to OMRON.
1.4.3
Non-repairable Determination
Normally, the determination of non-repairable equipment will be made with
an OMRON representative present. If a representative is not available, authorization to return non-repairable equipment must be received from this repair facility:
OMRON Corporation of America
Information Products Division
Field Service Department
432 Toyama Drive
Sunnyvale, Ca. 94086
(408) 734-8400 TWX 910-339-9341
1.4.4
Equipment Return Procedure
The OMRON representative, whether present on-site or using communicatio.
media, will prepare the appropriate Merchandise Return Authorization (Form No. MRA83-001) .. This authorization must be individually numbered. It must properly identify the non-repairabl~_equipment by description, part number, and serial number.
The reason or reasons for return must also be stated in adequate detail. A sample
Merchandise Return Authorization appears on page 1-11. A copy of the Authorization
shall be filed at the returnee's site. The remaining copies will be attached to
the shipping crate as shown on the form.
1.4.5
Packing and Packaging Procedure'
After proper completion of MRA form, return the equipment as follows:
1. Pack the unit in a container appropriate for the method of shipment.
Ideally, use a package similiar to the one in which the unit was delivered. Attach the MRA to the container.
2 .• Ship the unit, transportation prepaid, to the address mentioned in
paragraph 1.4.3. All sub-assemblies and parts described in the
warranty will be replaced if OMRON's examination discloses that the
defects are within the limits of the warranty. If damage or defect(s) are not covered by the warranty, the returnee will be told
what repairs are required and how much they will cost. The unit will
be repaired and returned upon agreement.
1-10
OMRON CORPORATION OF AMERICA
Information Products Division
009
"32 TOYAMA DRIVE
SUNNYVALE, CALIF. 94086
(4081 734-8400 TWX 910-339-9341
MERCHANDISE RETURN AUTHORIZATION
~OMER:
Mr. Ron J. Fejeran
Date:
~O~C~A~~~~~~~~--------
9-8-75
9401 Indian Head Highway
Oxon Hill, MD 20022
l
'LEASE COMPLETE THIS FORM AND RETURN IT TO OMRON CORPORATION OF AMERICA, INFORMATION PRODUCTS
DIVISION, ATTACHED TO THE SHIPPING CRATE.
1 SHIP PREPAID TO:
u.s, SHIPMENTS
EX-U_S_ SHIPMENTS
.#
OMRON CORPORATION OF AMERICA
INFORMATION PRODUCTS DIVISION
432 TOYAMA DRIVE.
SUNNYVALE, CALIFORNIA 94086
'. MRA Authorized by:
ITEM
OTY
1
1
PART NO.
99-399-001
ION
501
REASON FOR RETURN :_-!...--LD~QJ.le~s::L.'nnuo.:t;t-I:t:..tr:..;au:nuSiIIDJ:LJL:'tt:--______________________
Go ve rnmen t tlark e ti ng Ngj..jr......L.----,9?---W-B_-..J.7....S:..-_
AUTHORIZED BY:
Title
Dille
Title
Date
RECEIVED BY:
Name
ROUTE TO:
Quality Assurance for evaluation.
CUSTOMER FILE COpy
GENERAL INFORMATION
1.5
SECTION 1
LIST OF OMRON MNEMONICS
The following list defines the various mnemonics developed for the 8025
CRT Terminal.
ADBO-7:
A Data Bus bits.
BA:
RS 232 signal used by modem.
BDBO-7:
B Data Bus bits.
BEEP:
Decode of CPU 170 command; triggers beep circuit which produces
audible output whenever a Keyboard key •is
depressed .
#
BLANK:
Blanks screen under program control.
BLINK:
Signal from Refresh Buffer to enable blink function on Video
Control Card.
CA:
RS 232 signal used by modem.
CD:
RS 232 signal used by modem.
CGO-7:
Character generator input bits; 8-bit ASCII code.
CLK RDY:
Clock ready; synchronous 8008 Ready with IC clock.
CLRF:'
Cle~r
CNT 80:
Indicates next line shift register is loaded.
COMP BLNK:
Composite blanking signal.
CPU BUSY:
Indicates CPU is using memory busses.
CP:
Clock pulse; Keyboard encoder clock at H40 rate.
CPU R/W:
CPU read/write; signal controlling writing of data into memories
by CPU.
CSO-3:
Video status bits; CSO, CSI, CS2 and CS3 control video on/off,
block/off, cursor underline, control/character display and half
line mode.
CURS LINE:
Cursor line; defines the scan line in each character row on
which cursor is displayed.
DSO:
Data strobe out; indicates Keyboard wants to send a character.
'F'; clears video attribute register on Video Control card
at end of each scan line.
1-12
GENERAL INFORMATION
SECTION 1
EOP:
End of page; timing signal used to control the update of hardware parameters from 6 fixed locations in memory.
EOR:
End of row; timing signal used to control loading of character
display shift register.
EXT ADRS:
External address; allows an external device to address memory.
HI:
Timing signal; 7.488 MHz, one-half HF CLK.
H2:
Timing signal; 3.744 MHz, one-fourth HF CLK.
H4:
Timing signal; 1.872 MHz, one-eighth HF CLK.
H8:
Timing signal; character clock, 670 nsec
HlO:
Timing signal; two character clock periods (1.34 usee).
H20:
Timing signal; four character clock periods (2.68 usee).
H40:
Timing signal; eight character clock periods (5.36 usee).
H80:'
Timing signal; 16 character clock periods (10.72 usee),
equals horizontal blanking time.
H160:
Timing signal; period equals 1/3 of horizontal scan line
(21.44 usee).
H320:
Timing signal; period equals 1/2 of horizontal scan line
(32.16 usec)'._
HF CLK:
Basic timing signal; provides reference for all terminal
timing signals.
period~
1-1
LINE:
Horizontal line; 15,000 Hz (63.32 usec), horizontal frequency.
1-1
SYNC:
Timing signal at scan line rate used to drive scan circuits in
monitor (same as II DRIVE).
IC CLK:
l~!l
LO:
Timing signal in sync with alternate 02 clocks; indicates 2nd
half of CPU cycle.
Inhibit load; inhibits loading of video parallel-to-serial
converter when Refresh Memory is accessed by anything other
than the video generator.
lOB:
Decode of CPU I/O command INP3; initiates data transfer to or
from peripheral without resetting the interface.
Jon:
Decode of CPU I/O command INPI; initiates data transfer to or
from peripheral with reset of the interface.
1-13
GENERAL INFORMATION
SECTION I
KDBO-7:
Keyboard data bus bits; data out of Keyboard.
LCLSB:
Load count least significant bits; loads row position stored
in Refresh Memory into cursor row register on Cursor Control Card.
LCMSB:
Load count most significant bits; loads column position stored in
Refresh Memory into cursor column register on Cursor Control Card.
LDCNT:
Load count; clocks two-character delay, clocks write command
to Refresh Memory.
LITEI-12:
Interconnect circuits for Keyboard LED indicators.
LOAD F:
Decode of video attribute character on CGO-7;controls loading
of video attribute register.
MAO-IS:
Memory address bits.
MATCH:
Signal generated whenever outputs from video counter and cursor
position register are equal; used to generate cursor.
NULL:
Detection of blank "character" in row (1. e., blank memory).
OE:
Output enable; resets DSO and enables Keyboard output register
for next key depression.
PC6:
06 output of CPU during T2 state; one of two bits that define
CPU cycle type.
PC7:
07 output of CPU during T2 state; second of two bits that define
CPU cyCle type.
poc:
Power on clear; initializes Terminal when power is applied.
POLL:
Decode of CPU I/O command. (INPO); poll signal initiates selection of peripheral device for data transfer.
POS TIME:
Position time; occurs at scan line rate (see timing diagrams in
Section 4).
RATE:
5 pps clock; controls video blink rate.
RC:
Row carry; blanks CRT during vertical retrace.
ROO-7:
Data bits into Refresh Memory.
READ CLK:
Read clock; used as a reference to generate timing signals for
ROM memories.
REF ADRS:
Refresh address; indicates refresh memory is being accessed.
1-14
GENERAL INFORMATION
SECTION 1
REF R/W:
Refresh read/write; controls writing of data into Refresh Memory.
RESYNC:
CPU SYNC c·utput reclocked with 9J2.
RMO-7:
Output data bits from Refresh Memory.
RPT:
Repeat; signal to Keyboard telling it to repeat last character
transferred as long as the key is depressed.
RS CLK:
Clock used to generate timing reference for I/O data transfer
RS 232 cards,
RSTO-2:
Restart command bits; inserts program address into CPU.
SET LDFF:
Set load flip-flop; output of load
to-serial converter.
SPKR:
Speaker; produces audible energy generated by BEEP oscillator
circuit.
SR COUNT:
Indicates refresh logic has control of memory bus.
SRINH:
Shift register inhibit; controls loading of display shift
register in half line mode.
STAT:
Status; decode of CPU I/O command (INP2).
SYNC:
Output of CPU; indicates CPU is on second half of a timing state.
T2 SYNC:
Second hilI of CPU T2 timing state.
T3':
Early T3 timing state; synced with IC CLK.
T3 SYNC:
Second half of CPU T3 timing state.
UA ClK:
Universal asynchronous clock; clocks transmitter-receiver on
RS 232 Interface card.
UNO BlNK:
Undelayed blanking signal.
UPDATE:
pulse occuring at frame rate controlling updating of hardware
parameter from 6 fixed locations in memory.
VI, V2, V4:
Timing signal;
defines scanning lines one through eight
(character row lines are numbered 0 through 9) .
V8:
Timing signal; defines scan line nine (8) by itself, defines
scan line ten (9) in conjunction with VI.
VlO:
Differentjatcs between even and odd vertical rows.
flip-flop~loads
.
1-15
video parallel-
GENERAL INFORMATION
SECTION 1
VIDEO:
Signal which drives the monitor to produce the white areas
on screen which form characters, video attributes, etc.
V DRIVE:
Vertical drive.
V SYNC:
Timing signal at frame rate used to drive scan circuits in
monitor (same as V DRIVE).
WAIT:
CPU timing state; indicates READY was low prior to end of T2
state.
WAIT SYNC:
Second half of CPU WAIT state.
01, 02:
Timing signal that provides timing reference for all data transfer on memory busses.
1-16
INSTALLATION AND CHECKOUT
SECTION 2
Every 8025 CRT terminal is fully inspected and tested before shipment to
ensure that it meets specifications. It is packaged for safe transit under normal
freight-handling conditions. The terminal should normally arrive ready for use.
Claims with the carrier should be filed within 15 days from delivery.
OMRON therefore recommends that you unpack and test the terminal upon receipt.
Terminal installation should be made as outlined in this section.
2.1
UNPACKING PROCEDURE
2.1.1
Inspection
Before unpacking the terminal, inspect the shipping container for signs of
Possible damage to the unit during transit.
2.1.2
Unpacking
Set the crate "Right End Up" and use a knife blade, 1/4" or less long, to
open the top of the crate. Save the shipping container and packing materials in
case the terminal must someday be returned to OMRON or shipped to a repair facility.
"--~--,.
-+---
--
.-- .. ~-
..
..
!. ..- -
----.-------~
CABINET
Figure 2-l.
SCREWS
Cabinet mounting screws (front).
2-1
SECTION 2
INSTALLATION'AND CHECKOUT
2.2
OFF-LINE CHECKOUT
2.2.1
Mechanical Inspection
External Inspection. Inspect the terminal for external damage such as broltell
keys or cracked cabinet. Should there be any damage, refer to paragraph 1.3.1 in
Section 1.
If there is no damage, perform the operational check described in paragraph'
2.2.2. Proceed with installation if the terminal is operating correctly. Should the
terminal not operate correctly, first check that line voltage is present and the fuses
are intact. Then remove the cabinet and make an internal inspection.
Cabinet Removal. To take off the top of the cabinet, remove the five
screws (three on the front, two on the back) as shown in Figure 2-1 and Figure
2-2. Lift the cabinet top straight up. With the top portio« of the cabinet
removed, the internal assembly is easily reached.
Figure 2-2.
Cabinet mounting screws (rear).
2-2
INSTALLATION AND CHECKOUr
SECTION 2
Internal Inspection. Inspect the entire terminal for physical damage. Especially check around the neck of the cathode ray tube (CRT) and the Monitor Deflection Card (see Figures 2-3 and 2-5). If there is damage, refer to paragraph 1.3.1
in Section 1.
Make sure all circuit boards are properly seated and that the terminal has
a full complement of cards, as shown in Figure 2-4. From left to right these are:
Regulator Card, Cursor Control Card, Video Control Card, Refresh Buffer Card, Timing
Control Card, Refresh Memory Card, Refresh Control Card, Processor Card, PROM Card,
RS-232 Interface Card, Auxiliary Storage RS-232 Interface Card, Printer RS-232 Interface Card, and Terminator Card.
CAUTION:
MOS ELEMENTS USED ON CIRCUIT CARDS ARE EASILY DAMAGED BY
STATIC DISCHARGE. ALWAYS HANDLE CARDS SO THAT ANY DISCHARGE
WILL NOT FLOW THROUGH THE CARD. BEFORE TOUCHING A CARD,
PLACE ONE HAND ON THE TERMINAL CHASSIS AND USE THE OTHER
HAND FOR THE CARD.
Figure 2-3. CRT display high, voltage circuits
(mounted below Monitor Deflection Board.)
2-3
INSTALLATION AND CHECKOUT
Figure 2-4.
SECTION 2
Printed circuit card locations.
Figure 2-5. Monitor Deflection Board connections
(viewed from top of terminal).
2-4
INSTALLATION AND CHECKOUT
SECTION 2
Figure 2-6 shows the correct routing of all flat-line interconnect cables in
the terminal. Cable routing is as follows:
1)
The cable on the far right (a l6-conductor flat-line) connects the
Printer RS-232 Interface Card to J203, mounted on the rear panel of
the terminal.
2)
The second cable from the right (a l6-conductor flat-line) connects
the Auxiliary Storage RS-232 Interface Card to J202, mounted on the
rear panel of the terminal.
3)
The next card, the Communications (Modern) RS-232 Interface Card, has
two cables. A l4-conductor flat-line (top-connector) connects it to
the Baud Rate Switch mounted on the rear. panel of the terminal. A
l6-conductor flat-line (just below the Baud Rate cabte) connects the
card to J201 mounted on the rear panel of the terminal.
4)
The cable on the far left (a l6-conductor flat-line) connects the
Cursor Control Card to the keyboard. This cable is routed along the
right side of the terminal (viewed from front).
5)
The cable running to the top of the photo (a l6-conductor flat-line)
connects the Video Control Card to the Monitor Deflection Board.
6)
The remaining cable (a l4-conductor flat-line) connects the Refresh
Buffer Card to the keyboard indicator lights. This cable is routed
along the right side of the terminal (viewed from front).
Figure 2-6.
Flat cable connections.
2-5
INSTALLATION AND CHECKOUT
SECTION 2
Figure 2-7 illustrates flat-line connector configurations. Each flat line
connector is labeled with pin numbers on the back. Pin I should be inserted into
pin 1 on the socket.
If all cards are properly installed, interconnect cabling is correct, and
there is no visible damage, replace the cabinet top and the screws.
Figure 2-7.
Flat-line connector configurations.
INSTALLATION AND CHECKOUT
2.2.2
SECTION 2
Operational Check
The purpose of the operational check is to determine that the terminal is
operational as a stand-alone unit. To perform this check, proceed as follows:
1)
Make certain that the Baud Rate Switch on the rear of the terminal is
in the correct position for your application.
2)
Connect the power cord to the NEMA-approved three-contact grounding
outlet that supplies 117 V ac ±10%, 60 Hz, 1 ~ or the voltage specified on the identification label located on the bottom of the terminal. The outlet must provide at
least 400 Watts of noise-free power. (If only a two-contact outlet is available, use
a properly grounded two-wire-to-three-wire adapter or some other appropriate means
to ensure chassis grounding).
3)
Turn the terminal on with the On-Off Switch at the extreme upper left
of the keyboard.
4)
Listen for the sound of the cooling fans. If you cannot hear them,
turn the terminal off and refer to paragraph 1.3.1. in Section 1.
5)
Advance the Brightness Control (located to the immediate right of the
On-Off Switch) all the way up. When the raster appears, reduce brightness until the
~aster disappears but characters are visible.
6)
Allow the terminal to operate for a few minutes. Until the raster appears on the CRT, be alert to any abnormal sounds or odors. If you detect any, turn
the terminal off and refer to paragraph 1.3.1 in Section l~
7)
Check out all keyboard functions (e.g., cursor and screen movements,
edit functions, escape sequences~ and alpha-numeric-symbo1 keys) for proper operation.
Refer to Section 3.
2.3
INSTALLATION
2.3.1
Physical Requirements
Place the terminal on a stable platform at a height suitable for operator
comfort in a place that falls within the environmental specifications for the terminal.
(Refer to Table 1-1 in Section 1.)
2.3.2
Electrical Requirements
The terminal must be connected to a noise-free power line with the characteristics specified in Table 1-1 in Section 1.
Connect power cord to a NEMA-approved three-contact grounding outlet to ensure that the terminal chassis is grounded.
NOTE 1:
If only a two-contact outlet is available, use a properly
grounded two-wire-to-three-wire adapter or some other
appropriate means to ensure chassis grounding.
NOTE 2:
The use of extension cords is not recommended.
2-7
INSTALLATION AND CHECKOUT
2.3.3
SECTION 2
External Connections
All external connections are made at the rear of the terminal. Figure 2-8
identifies the external connectors. Table 2-1 defines the terminal-data system interconnects.
Figure 2-8.
Table 2-1.
8025 CRT Terminal: rear panel
connectors.
Terminal-system interconnection .
.
-8025 CRT TERMINAL
REAR PANEL CONNECTOR
J201
J202
J203
J206
2.3.4
CONNECTS TO
Communications modem
storage
Printer
117 V ac line
Auxiliar~
RS-232 Speed Adjustment
The Auxiliary Storage and Printer RS-232 interface cards are set for 1,200
baud, parity off. The speed for these cards can also be set for 110, 300, 1,800 and
2,000 baud. If a speed change is required, refer to Section 7.
2.4
ON-LINE CHECKOUT
Connect the 8025 CRT Terminal into the system. Use the system terminal
operating procedure to determine that the 8025 terminal operates correctly in the
system.
2-8
OPERATING INSTRUCTIONS
3.1
OPERATING CONTROLS
SECTION 3
All day-to-day operating controls are located on the keyboard of the terminal. (See Figure 3-1.) Completely familiarize yourself with these controls. Read
this section and use the controls while observing their effect on the display.
3.1.1
On-Off Switch
As shown in Figure 3-1, the ON-OFF switch is located in the extreme upper
left corner of the keyboard panel. Press down on the upper end of the switch to
turn the terminal on. Press down on the lower end to turn the terminal off.
3.1.2
Brightness Control
The BRIGHTNESS control is located next to the ON-OFF switch. Like the
brightness control on a TV set, it controls the overall brightness of the white
areas on the display screen.
For maximum brightness, move the control up until the stop is reached.
For minimum brightness, move the control down until the stop is reached (dark
Screen) .
There is no specific set-point for the brightness control. Continuous
operation at a very high setting, however, can shorten CRT life. A recommended
setting is one that makes the screen easy to read and comfortable for the eyes. Be
sure to eliminate the raster.
3.1. 3
Baud Rate Switch
The Baud Rate switch is located on the rear panel of the terminal. This
Switch sets the transmission rate for the modem interface (primary RS-232 Interface Card). Rates of 110, 300, 1,200, 1,800, and 2,000 baud are selectable with this
control.
NOTE:
3.1. 4
Terminals with 2,400 baud option will have 2,400 baud in place
of 2,000.
Parity Switch
The Parity· switch is also on the rear panel of the terminal. The setting
of this switch estab lishes the parity mode for the modem interface of the terminal.
Odd parity, even parity and parity bff are selectable with this control. The Parity Switch controls both transmitted and received data.
When the Switch is in the OFF position, all characters are transmitted
with bit 8 low. (NOTE: Transmission with bit 8 high can be elected with a jumper
OPtion on the RS-232 Interface Card.) Parity in received characters is ignored.
In the ODD position, all characters are transmitted with odd parity; that
is, bit 8 is set high when there is an even number of highs iri bits 1 through 7.
~eceived characters are checked for odd parity; that is, the number of highs in
3-1
OPERATING INSTRUCTIONS
SECI'rON 3
bits 1 through 8 is odd.
In the EVEN position, all characters are transmitted with even parity;
that is, bit 8 is set high when there is an odd number of highs in bits 1 through
7. Received characters are checked for even parity; that is, the number of highs
in bits 1 through 8 is even.
3.2
THE DISPLAY SCREEN
The display screen is the primary means through which the terminal communicates with you. Data entries into the terminal, regardless of source, will
normally be displayed on the screen. Thus, you can proof information entered from
the keyboard, read information supplied from an external device, fill in forms,
and in general readily converse with other equipment in a data communications
..
system.
3.3
AUDIO INDICATORS
Audio indicators provide a secondary means through which the terminal communicates specific information to you. Two such indicators are built into your
8025 terminal: a "click" sound and a "beep" sound.
3.3.1
The Click Sound
A click tells you that the terminal accepted a key stroke.
3.3.2
The Beep Sound
A beep indicates one of two everits: 1) the ASCII code "BEL" was received
or 2) the terminal was unable to accept a key stroke •. The second event occurs when
the terminal is busy or when an unacceptable operation is requested.
3.4
VISUAL INDICATORS
Indicator lights are built into six of the special function keys located
in the two top rows of the left-hand key pad. Table 3-1 defines the on-off states
for each indicator.
3-2
OPERATING INSTRUCTIONS
Table 3-1. Visual Indicator On-Off States
SECTION 3
INDICATOR
STATE
STORE INPUf
ON
OFF
Store input function active
Store input function inactive
STORAGE
TRANSMIT
ON
OFF
Transmit from auxiliary storage function active
Transmit from auxiliary storage function inactive
KSR MODE
ON
OFF
Terminal in KSR transmission mode
Terminal in ASR transmission mode
KEYBOARD
DISABLED
ON
OFF
Terminal is busy; keyboard entries ignored
except certain function keys (see t~xt)
Terminal available to keyboard
RECEIVED
PARITY ERROR
ON
OFF
Parity error detected in received characters
No parity error detected
LOCAL
COPY
ON
OFF
Keyboard entries displayed (half duplex operation)
Received data only displayed (full duplex operation)
3.5
3.5.1
INDICATION
BASIC OPERATING MODES
.
The 8025 CRT terminal has two basic operating modes:
KSR and ASR.
KSR Mode
In KSR (keyed send and receive) mode,. the terminal operates as a basic
character-by-character key entry device. Each character entered on the keyboard
is transmitted immediately to the communications line. If the character is displayable, it is also entered onto the screen.
Displayable data received from the communications line is also displayed
on the screen and Tay be intermixed with keyboard-originated data.
Note that data received from the line is checked for parity according
to the setting of the parity switch. A (~) parity error character is substituted
for any character received with incorrect parity.
3.5.2
ASR Mode
In ASR (automatic send and receive) mode, the terminal operates as a block
transmit device. Characters entered on the keyboard are not transmitted to the communications line as entered. Displayable characters are "saved" on the screen and
transmitted under control of the FRAME TRANSMIT key (see 3.7.10). Received data
is ignored unless STORE INPUT is selected (see 3.7.2).
3-3
OPERATING EXPENSES
3.6
SECTION 3
KEYBOARD KEYS
Figure 3-1 shows the keyboard arrangement.
3.6.1
Operating Features
Automatic Repeat. This feature causes a character to repeat itself about
15 times per second if the key is held down for more than one-half second. Repetition continues until the key is released.
N-Key Rollover. This feature allows several keys to be struck at the
same time without loss of characters or commands. Data entry, however, is in the
order of actual key switch closures. (NOTE: It is virtually impossible to strike
more than one key so that switch closures will be simultaneous.)
3.6.2
"Typewriter" Keys
This group of keys includes the alphabetical, numerical, punctuation,
and symbol keys plus SHIFT/LOCK, Space Bar, TAB, CR (Carriage Return), and LINE
FEED. They are arranged as shown in Figure 3-1. Individually they perform many
of the same functions as on a typewriter or a teletype machine.
3.6.3
Numt)ri c Pad Keys
Some terminals have a numeric pad, shown in Figure 3-1. These keys duplicate the numerical, comma, and period (decimal point) keys in the "typewriter" grouping. That is, striking a key in the numeric pad has the same effect as striking the
corresponding key in the "typewriter" group.
3.6.4
Escape (ESC)
ana
Control (CTRL) Keys
The escape (ESC) and control (CTRL) keys are each used with one or more
other keys to initiate functions or characters for which special function keys are
not provided.
3.6.5
Cursor Control Keys
The five cursor control keys, labeled with heavy arrows and HOME, control
cursor movement. The cursor moves in the direction of the arrows or to its home
position (top left corner of screen) .
•
3.6.6
Next Line (.J) Key
This key moves the cursor to the start of the next line, or to the start
of the first line if the cursor is in the last line when the key is depressed.
3.6.7
Function Keys and Indicators
The remaining keys are special function keys. They initiate commonly
used operations. Some include indicator lights to show terminal status. These
keys are identified in Figure 3-1.
3-4
OPERATING INSTRUCTIONS
SECTION 3
3.7
INDIVIDUAL KEY DESCRIPTIONS
3.7.1
Alphanumeric-Punctuation-Symbol Keys
These keys enter the applicable character into the terminal.
3.7.2
STORE INPUT Key/Indicator
Pressing STORE INPUT (shifted or unshifted) to turn the indicator light
on activates the store input function and disables the keyboard (KEYBOARD DISABLED
indicator on). RESET and STORE INPUT remain enabled. All data received from the
host system is placed in the auxiliary storage.
NOTE:
It may also be necessary to actuate a control on the
storage device being used. For example, a TECHTRAN
4100 series tape cassette drive requires that the WRITE
control be pressed to space the tape over the leader
when the tape is on clear leader.
If the terminal is in KSR, this data is also displayed on the CRT screen.
In ASR mode, the screen is not disturbed.
Pressing STORE INPUT (shifted or unshifted) to turn the indicator off
switches the store input function off and enables the keyboard again.
3.7.3
STORAGE TRANSMIT Key/Indicator
Pressing this key (shifted or unshifted) to turn the indicator light on
activates the storage transmit function and disables the keyboard (KEYBOARD DISABLED indicator on). RESET and STORAGE TRANSMIT remain enabled. A record in the
auxiliary storage is displayed on the screen and also transmitted to the host.
Pressing STORAGE TRANSMIT (shifted or unshifted) to turn the indicator
off switches the storage transmit function off and reenables the keyboard. The keyboard is enabled after the last character in the record is transmitted.
3.7.4
KSR MODE Key/Indicator
Pressing KSR MODE (shifted or unshifted) to turn the indi cator Ii ght on
sets the terminal for KSR operation. Data entered from the keyboard is displayed
on the screen and transmitted character-by-character to the host. Received data
is also displayed. Wi~h parity on, a received parity error turns the RECEIVED
PARITY ERROR indicator light on. Also, a backward question mark (f) is displayed
on the screen in place of the character.
Pressing KSR MODE (shifted or unshifted) to turn the indicator off sets
the terminal to ASR mode.
NOTE:
The terminal will enter KSR mode only if a carrier
indication is being received from the communications
line.
3-5
OPERATING INSTRUCTIONS
3.7.5
SECTION 3
PRINT Key
Pressing PRINT (shifted or unshifted) transfers data on the CRT screen
to the printer and disables the keyboard. Data from the cursor home position (upper
left corner of screen) to the cursor is printed. If the cursor is in its home position, the entire screen is printed. When the transfer is completed, the keyboard
. is re-enabled.
3.7.6
STORE Key
Pressing STORE (shifted or unshifted) transfers data on the CRT screen
to the auxiliary storage and disables the keyboard. Data from the cursor home position (upper left corner of screen) to the cursor is transferred. If the cursor is
in its home position, the entire screen of data is transferred.
"#
NOTE:
3.7.7
It may also be necessary to actuate controls on the
storage device being used. For example, a TECHTRAN
4100 series tape cassette drive requires that, 1) the
WRITE control be pressed to space the tape over the
leader when the tape is on clear leader and, 2) the
END MODE control be pressed if the drive just completed
a read command.
READ Key
Pressing READ (shifted or unshifted) transfers data from the auxiliary
storage to the CRT screen and disables the keyboard. Data in storage will be read
until a stop read command is transferred or the end of file is encountered on the
medium. (The'exact sequenc~ depends on the characteristics of the storage device).
NOTE:
host must supply the start and stop commands when
data was entered into the auxiliary storage with the
STORE INPUT function. Data entry with the STORE key
includes terminal-supplied start and stop command.
~e
The keyboard is automatically enabled after the record
is trans ferred.
3.7.8
KEYBOARD DISABLED Indicator
This key position functions only as an indicator. When the light is on,
keyboard input is not allowed. Exceptions (explained earlier): RESET, STORE INPUT,
and STORAGE TRANSMIT. That is, the terminal will not accept key strokes. The keyboard is enabled when the indicator is off.
3.7.9
RECEIVED PARITY ERROR Indicator
This key position serves only as an indicator, and it operates only if
parity is enabled (see paragraph 3.1.4). When the indicator is on, it signifies
that a parity error was detected in a received character.
3-6
OPERATING INSTRUCTIONS
NOTE:
3.7.10
SECTION 3
A "~,, is displayed on the CRT screen in place of the character.
The indicator stays on lDltil it is cleared by a reset flDlction
as described in paragraph 3.8.2
FRAME TRANSMIT Key
Pressing FRAME TRANSMIT (shifted or unshifted) ASR transmits data on the
CRT screen to the host and disables the keyboard. Data from the cursor home position (upper left corner of screen) to the cursor is transmitted. If the cursor is
in its home position, the entire screen is transmitted. The keyboard is automatically enabled at the end of transmission.
3.7.11
LOCAL COpy Key/Indicator
This key is used only in KSR mode. The key directs~ata entries to both
the communications system and the display screen when pressed to turn the indicator
light on (LOCAL COpy on for half-duplex operation). If the light is off (LOCAL COpy
off for full-duplex operation) after pressing the key, data entries are sent only to
the communications line.
3.7.12
BREAK Key
Pressing this key places a 200-250 millisecond space on the communications
This key functions the same as the "interrupt" or "attention" key on other
~erminals .
line.
3.7.13
RESET Key
This key is used to perform the input-out and master reset operations described in paragraph 3.8.3.'
3.7.14
SCREEN ERASE Key
Pressing SCREEN ERASE (shifted or unshifted) clears the entire display
screen to nulls and places the cursor at its ~ome position (upper left corner of
screen).
3.7.15
Control (CTRL) Key
The CTRL key, when used with an alphanumeric, punctuation or symbol key
(shifted or unshifted) initiates function or enters a character, as defined in
Table 3-2. The cbntrol key must be depressed first and held down while the other
key, or keys, are operated.
3.7.16
SHIFT Key
This key shifts from lower case to upper case as on a typewriter. On dual
character keys, it shi fts from one character to another. Press the key to produce
upper case characters.
3.7.17
LOCK Key
This key locks the SHIFT key in the upper case pOSition, as on a typewriter.
3-7
OPERATING INSTRUCTIONS
3.7.18
Space Bar
SECTION 3
space bar.
The space bar (at the bottom of the keyboard) functions as a typewriter
Striking this key enters a space character into the terminal memory.
3.7.19
TAB Key
Striking TAB transmits an HT character in KSR mode.
The display is not
changed.
3.7.20
LINE FEED Key
Striking LINE FEED moves the cursor down one line. This is equivalent
to a teletype line-feed action. No character is entered into the s.creen .
.
3.7.21
Carriage Return (CR) Key
Striking CR moves the cursor to the start of the line in which it resides.
This is equivalent to a teletype carriage return action. A carriage return symbol
(+) is entered into the screen.
If a CR is followed by a line feed, the line on which the CR was entered
is cleared from the character position following the CR to the end of the line.
When multiple CRs are entered and followed by a line feed, the line is cleared from
the character position following the first CR entered to the end of the line.
3.7.22
Delete (DEL) Key
Striking DEL generates the ASCII seven-bit delete (DEL) character.
3.7.23
Backspa~e
(BS) Key
Striking BS moves the cursor one position to the left and transmits an
ASCII backspace to the communications line.
3.7.24
Cursor Control (HOME and Arrow) Keys
Six keys control cursor movement.
They are HOME and the 5 keys with arrows.
Striking the HOME key moves the cursor to its home position--the first
character space ~n the upper left corner of the CRT screen.
To move the cursor up, down, left, or right, stroke the applicable "arrow"
key. Each time you press the key, the cursor moves one space in the direction you
wish--one space horizontally or one line vertically. Should the cursor be at the
start of a line, cursor left normally moves the cursor to the end of the preceding
line. Striking cursor right when the cursor is at the end of a line normally moves
the cursor to the start of the following line.
When the cursor is in its home position, cursor left moves the cursor to
the end of the last line. The reverse is true if the cursor is at the· end of the
last line and you strike cursor right.
3-8
·
·
eJ..
,,
.....•.
: ..
.
SECTION 3
--~.---.-
ON
OFF
j
t
B
R
J
G
H
.
.
~
. ..
"
,
'
,
',/
..
•
~..
.\
.
.
;
········'·
w
.'
..
T
I
Figure 3-1.
CRT terminal keyboP·
.
3-9
OPERATING INSTRUCTIONS
SECTION 3
If the cursor is on the first line, cursor up moves the cursor to the
same position in the last line. Cursor down performs the reverse action if the
cursor is in the last line.
Striking the next line key (.J) moves the cursor to the start of the
following line. If the cursor is already on the last line, it moves to the HOME
position.
3.8
OPERATING PROCEDURES
3.8.1
Turning the Terminal On and Off
Turn the terminal on as follows: 1) Apply power by pressing down on
the upper end of the ON-OFF switch, 2) Allow the terminal to warm up for two or
three minutes, 3) Hold any character key down, and 4) Adjust the BRIGHTNESS control as desired (raster should not be visible). Table 3-2 tells how to initiate
operating functions.
When the terminal is turned on, it automatically sets to ASR mode.
To turn the terminal off, press down on the lower end of the ON-OFF
'i tch. It is not necessary to reduce the brightness. You can leave the terminal
on if ypu wish, but turn the BRIGHTNESS control down (dark screen) to extend CRT
Ii fee
3.8.2
Clear/Reset Functions
I/O Reset. Press CTRL.and RESET at the same time to stop all input/output (I/O) operations. This actiort resets all I/O interfaces to off, sets the terminal to ASR mode, and r.esets the parity error indicator. It does not clear memory.
Master Clear (or Reset). Press CTRL, SHIFT, and RESET at the same time
to clear memory, position the cursor at its home position, reset all I/O interfaces,
set the terminal to ASR mode, and clear parity error 'indicator. A master clear is
performed automatically whenever the terminal is turned on.
Clear Screen. Strike SCREEN ERASE to clear the memory and place the cursor at its home position.
~-1l
OPERATING INSTRUCTIONS
Table 3-2.
SECTION 3
Control code generation in the 8025 terminal
ACTION
CODE
SPECIAL
FUNCTION
KEY
CONTROL
SEQUENCE
(CTRL plus)
Start of heading
SOH
a
Start of text
STX
b
End of text
ETX
c
End of transmission
EOT
d
Enquiry
ENQ
e
Acknowledge
ACK
f
Bell
BEL
g
Backspace
BS
BS
h
Horizontal tab
HT
TAB
i
Line feed
LF
Vertical tab
LINE FEED
j
VT
k
Form Feed
FF
1
Carriage return
CR
Shift out
SO
n
Shift in
SI
0
Data link escape
OLE
p
•
Device control 1
DCI
q
Device control 2
DC2
r
Device control 3
DC3
s
Device control 4
DC4
t
-
3-12
CR
m
OPERATING INSTRUCTIONS
Table 3-2.
SECTION 3
Control code generation in the 8025 terminal (contd)
CODE
ACTION
SPECIAL
FUNCTION
KEY
CONTROL
SEQUENCE
(CTRL plus)
u
Negative Acknowledge
NAK
Synchronous idle
sm
End of transmission block
ETB
w
Cancel
CAN
x
End of medium
EM
Y
Substitute
SUB
z
Delete
DEL
Escape
ESC
File separator
FS
I
GS
{
Group separator
.
-
Record separator
RS
unit separator
US
..
ESC
.
v
\
=
DEL
SCREEN
ERASE
Clear screen
Master clear l
SHIFT+RESE'T
RESET
I/O reset
FRAME
TRANSMIT
Frame transmtt
Next line
.J
STORE INPUT
(light on)
STORAGE
TRANSMIT
(light on)
Store Input on
Storage transmit on
3-13
OPERATING INSTRUCTIONS
Table 3-2.
SECTION 3
Control code generation in the 8025 terminal (contd)
ACTION
CODE
SPECIAL
FUNCTION
CONTROL
SEQUENCE
(CTRL plus)
KEY
KSR MODE
(light on)
KSR mode on
Print on
PRINT
Store on
STORE
Read on
READ
LOCAL COpy
(light on)
LOCAL COpy
(light off)
BREAK
Local copy on
Local copy off
Break
3-14
•
THEORY OF OPERATION
4.1
TERMINAL BLOCK DIAGRAM ANALYSIS
SECTION 4
A simplified block diagram of the 8025 CRT Terminal is shown in Figure 4-1.
Table 4-1 outlines signal sources and their distribution. These signals are defined
or described in Section I, as well as at first mention in the text.
The 8025 CRT terminal is built around a central processing unit (CPU) located
on the processor card. Data travels between the CPU and the rest of the terminal via
three buses: an address bus (MA Data Bus), an input data bus (A Data Bus), and an output data bus (B Data Bus). Timing and control signals are generated and distributed
as shown on the block diagram.
4.1.1
Timing, Control, and Data Signals
The basic clock and timing signals for the 8025 CRT Terminal are produced by
circuits on the Timing Control Card.
The timing generator produces the clock signals and (T) and also drives another timing circuit which generates the horizontal (H) and vertical (V) timing signals used throughout the terminal as indicated.
V and H signals are also used to produce vertical and horizontal sync (V and
H respectively), composite sync (C), and composite blanking (C B) signals. Both Vs and
HS drive the CRT Display, and Vs is used to res"et part of the video counter on the
Cursor Control Card. Cs is combined on the Video Control Card with a composite video
signal for use by an external display. CB is used by the Video Control Card to blank
out sweep retraces on the CRT display as well as to reset part of the video counter
on the Cursor Control Card.
Circuits on the Timing Control Card also decode CPU-generated I/O command
signals for distribution to the Cursor Control and RS-232 Interface Cards.
The timing· control card also contains the power-on clear (POC) generator.
Whenever power is applied to the terminal, this circuit produces a pulse that clears
and resets clocks and registers on the processor, refresh buffer, and RS-232 interface
cards.
Most operations on the terminal are controlled by the CPU on the Processor
Card. Data to and from the CPU travels over the three data buses shown. Outputs
from the CPU are decoded in the control logic to provide a number of control signals (PCL)' Another CPU output is combined with a T signal to generate a clock
signal (IC CLK) for 'use by the RS-232 Interface and Refresh Buffer cards .
•
Programmed read-only memory (PROM) circuits on the PROM Card or marked Read
Only Memory (ROM) on the ROM card contain the basic control program for the 8025 CRT
terminal. Data is read our of memory to the A Data Bus and the memory is addressed
via the MA Data Bus. The address sector circuit allows the card to respond only to
a certain range of addresses, while memory circuit selections, as defined by MA inputs, is done by the chip selector.
The Refresh Memory Card contains a number of random access memory (RAM) circuits which temporarily store data from either the CPU or a direct memory access
COMA) device such as a cassette tape deck. The stored data can subsequently be read
4-1
THEORY OF OPERATION
SECTION 4
out for use by the CRT display or a DMA device. One section of the memory is reserved for specifying special terminal related functions such as. cursor position and
page base. As shown, data is written into memory via the B Data Bus, and read out
through an output gated to the RM Data Channel. A control signal (RCL) from the
Refresh Control Card determines if data is to be read into or out of memory.
The RAM circuits on the Refresh Memory card are addressed via the MA Data
Bus. With an address on the MA Data Bus, the address sector circuit puts out a refresh address signal (RA) which controls the RM gate on the Refresh Buffer Card.
The address sector circuit also applies a signal to the chip selector which selects
the addressed RAM circuit and enables the data readout gate.
The Refresh Buffer Card has two primary functions: temporary data storage
and video refresh. Working with the Refresh Control Card, the Refresh Buffer Card
reads data from the Refresh Memory Card one line at a time. It temporarily stores
each line of data while transmitting it repeatedly (10 times) t~ the Video Control
Card for display.
'
The data from the refresh memory, coming in on the RM Data Channel, includes characters to be displayed as well as video modification characters (e.g.,
turn video on or off). When the latter are detected, a strobe signal to the video
status latch causes them to be stored until the end of the current display line.
On/Off data for the keyboard indicator lights are stored in the LED latch
and made available to the Keyboard on the LED Data Channel.
Two SO-character shift registers provide refresh data over the CG Data
Channel. Data from the refresh memory may be used either by the processor or by
the Refresh Memory for screen refresh. In either case control signal RA enables
the RM gate to' allow passage of data on the RM Data Channel. The half-line gate
remains enabled unless the t~minal uses a 40-character-per-line display format.
The beep decode circuit on the Refresh Buffer Card decodes MA Data Bus,
IC, and I/O inputs to produce a signal that activates the beep portion of the
click-beep circuit on the Cursor Control Card.
The Refresh Control Card controls addressing and reading of the refresh
memory by the refresh buffer. It contains two counters, one of which controls the
addressing while the other counts characters. For each line of characters displayed
(10 repetitions), the memory is read SO times. In addition, the eight fixed positions at the end of memory (addresses 377708 - 37777 S) are read during vertical retrace.
The Cursor Control Card includes cursor control, acoustic feedback (clickbeep), and keyboard interface circuits.
Cursor control circuitry produces the MATCH signal used by the Video Control Card to create the cursor display. A Video counter, counting in sync with the
sweep, defines the current position of the electron beam on the CRT. The cursor position specified by the refresh memory. When the outputs of the two are equal, the
comparator sends a MATCH signal to the video modification logic on the Video Control
Card, which intensifies the video. The resulting cursor display shows the position
of the next character to be displayed.
4-2
THEORY OF OPERATION
SECTION 4
The keyboard interface controls data transfer from the keyboard to the CPU.
To transfer data, the keyboard encoder sends a strobe signal to the keyboard interface, which leads to the following sequence of events. Upon receipt of a POLL I/O
command from the CPU, the interface responds with its address over the A Data Bus.
When the CPU in turn responds with an I/O command, the interface gates KB Data to
the A Data Bus, and signals the encoder that the data was transferred. If a key is
depressed for more 'than one-half second, the interface also signals the encoder to
repeat the last character transferred until the key is released.
Each time the keyboard interface transfers KB Data to the A Data Bus, it
causes the click/beep circuit to produce an output pulse heard on the keyboard speaker
as a click. When the click-beep circuit receives a signal fro~~ the beep decode circuit on the Refresh Buffer Card, it produces an output heard on the speaker as a
beep.
Circuits on the Video Control Card generate the signals that produce and
control the display on both the terminal CRT Display and an optional external display.
Characters stored in the character generator ROM are addressed for display
by d'ata from the shift register on the Refresh Buffer Card. The line to be displayed
in the character row is specified by the V inputs to the ROM. Parallel data out of
the ROM is converted into serial form and gated, under video modification control,
t6 two mixer drivers. In one of these, the video is mixed with the blanking signal
(CB) for use by the CRT display. In the second, the video is mixed with the compsync signal (CS) for use by an external display.
Video modification. data from the shift register on the Refresh Buffer Card
is stored in the video modification register. The video modification logic decodes
the register outputs, video status data on the CS Data channel, and the other input
signals shown to produce modification commands. These commands are applied to the
video gate to modify the video display as required (e.g., reverse video, underline,
etc.).
The Keyboard Card contains an X-V switch matrix, a shift and control circuit, and an encoder. An X output from the encoder is connected to a Y input to the
encoder when a key is depressed. The encoder converts the X-V coordinates into an
ASCII code, which it places on the KB Data Channel. At the same time, the encoder
sends a strobe signal to the keyboard interface on the Cursor Control Card to indicate that the keybQard has data for the CPU. After the data is transferred, the
interface sends a signal to the encoder to reset the strobe selector and enable the
encoder for the next key stroke. Shift and control inputs to the encoder initiate
keyboard shift action and control character code generation.
The RS-232 Interface Card provides for compatability between the 8025 Terminal and a data communications system. Parallel data supplied by the CPU via the
MA Data Bus is converted into serial form in the receiver-transmitter, and then transmitted, under control of the control logic, to the data communications system (output
BA). Incoming serial data (BB) goes through the control logic to the receiver-transmitter where it is converted into parallel form. The control logic enables the received data gate to transfer the data to the A Data Bus for entry into the CPU.
4-3
THEORY OF OPERATION
SECTION 4
As shown in the block diagram, the control logic also controls: 1) gating
of the interface card's address to the A Data Bus; 2) gating of error status, such
as parity and overrun, to the A Data Bus; and 3) gating of card and modem status,
such as data set ready and transmitter-received status, to the A Data Bus. In addition, the logic control provides the necessary interface for data communications signals such as request to send (CA) and clear to send (CB).
The rate, or speed, of data transmission is set by the clock, which is
driven by the T input. Any of five clock frequencies may be selected at the rear
panel of the terminal.
The Terminator Card performs two functions: (1) it provides resistive loading and terminations for the data bus and control lines driven by open-collectordrivers, and (2) it selects one of eight addresses at which the processor program
restarts after an interrupt.
4.1. 2
Typical Operating Sequences
Keyboard Entry. Assume the "A" key on the keyboard is struck. The corresponding X-Y coordinates from the X-Y switch matrix, are decoded by the encoder and
converted into the 8-bit ASCII code for an "A". (See Section 10, Reference Information.) After conversion, the character is stored in the encoder'S output buffer,
while the encoder sends a data strobe output (DSO) signal to the keyboard interface.
The CPU on the Processor Card periodically sends out an I/O command (POLL)
to 'determine if any peripheral devices require data transfer. When the POLL command
arrives at the keyboard interface and the DSO signal is present, the interface does
three things: (1) prevents further propagation of the POLL, (2) selects itself for
the next data transfer to the CPU, and (3) identifies itself by putting the keyboard
address on the A Data Bus.
Upon receiving the keyboard address, the CPU responds with another I/O command (100), which allows the interface to transfer the keyboard data (character
"A") to the A Data Bus and to deselect itself. At the time it transfers the keyboard
data, the interface also activates the click-beep circuit to produce an audible click
from the keyboard speaker. The 100 command also' causes the interface to send an output enable (OE) signal to the encoder to reset DSO and enable the encoder for the
next key stroke. At this point all keyboard operations related to the character "A"
are finished.
During these keyboard operations, the CPU addresses (over the MA Data Bus)
the cursor location.in the refresh memory to determine where the next character should
appear.
After receIvlng the cursor position, the CPU processes the information and
stores the ASCII-coded "A" at the appropriate address in refresh memory. At the same
time, the CPU adds one to the cursor position in the Refresh Memory in readiness for
the next character. (Addressing is done via the MA Data Bus; cursor pOSition and the
ASCII code for the "A" are entered into memory over the B Data Bus.) The cursor
change will automatically update the cursor position register on the Cursor Control
Card via the RM Data Channel.
The CPU is now finised with the "A" transfer, and, after performing various
4-4
THEORY OF OPERATION
SECTION 4
housekeeping tasks, will send out another POLL command.
Ouring display time, the address counter on the Refresh Control Card sequentially scans the refresh memory over the MA Data Bus. When the address for the "A"
is reached, the stored ASCII code is read out of memory through the output gate to
the Refresh Memory Card. Here the "A" goes through the RM and half-line gates to the
shift register for transmission over the CG Data Channel.
Full addressing of the character generator ROM on the Video Control Card
includes CG data plus vertical timing signals (V). The former defines the "A"; the
latter specifies the scanning line in the character row to be displayed. The character generator ROM decodes the line and character information for the "A" and puts
out the data in parallel form.
After conversion in the parallel-to-serial converter, a video signal containing horizontal line segments of an "A" is gated to the vidlo mixer/driver. This
circuit combines the video with the composite blanking signal (C B) for application
to the CRT display.
Let's assume now, that.instead of an "A" the keyboard character entered is
a video modification character specifying reverse video (black characters on a white
backgro1:md) .
For a video modification character the operating sequence is the same as
that for the "A" with these exceptions: (1) the character leaving the refresh shift
register contains information identifying it as a video modification character; (2)
the character contains reverse video commands that go to the video modification register on the video control card; (3) outputs from the register are decoded by the
video modification logic; and (4) the logic output alters the video signal to display black on' white until ~ither the next video modification character arrives or
the end of the line is reached.
Finally, let's assume the NEW LINE key is struck. After determining that
the character is nondisplayable, the CPU addresses the ROM program via the MA Data
Bus anJ receives program instructions over the A Data Bus. In this case the CPU is
instructed to move the cursor position down to· the next character row and to the
left side of the display. The CPU then updates, via the B Data Bus, the cursor
location in the refresh memory's fixed-position address block. The new cursor position will subsequently update the cursor position register on the Cursor Control
Card so as to change the cursor position on the CRT screen.
RS-232 I~terface Transfers. Data transfer from the RS-232 Interface Card
basically the same as a keyboard entry. In this case, however, data can be transferred in either direction.
i~
Assume the RS-232 Interface Card wants to transfer an "A" from a modern to
the CPU for display on the CRT. The "A" received in serial form from the modern on
the BB line, is fed to the receiver-transmitter. On the RS-232 Card, the receiver
converts the serial data into parallel form and puts the "A" in a local register.
When it intercepts a POLL command from the CPU, the interface stops further propagation of the POLL, places its address on the A Data Bus, and selects itself for the
next data transfer. An 100 signal from the CPU in response .causes the interface to
deselect itself and gates the "A" to the A Dat~ Bus for transfer to the CPU. The re
4-5
THEORY OF OPERATION
SECTION 4
lIIainder of the operation to display the ItAIt is identical to 'a keyboard entry, and the
same is true for a non displayable character, received by the RS-232 Interface Card.
Assume now that the CPU wants to send an "A" to the RS-232 Interface Card
for transmission. The CPU, under program instruction, puts the card's address on
the MA Data Bus and sends a STAT I/O command to enable and set up the card and modem
for the transfer. In turn, the card responds to the CPU over the A Data 8us with
its status (e.g., receiver ON or OFF; ready for data transfer, etc.). When the transmitter is turned on and its buffer register is empty, it can respond to the next POLL
command in the same way as the receiver. Data from the MA 8us enters the buffer register in the transmitter and is shifted out serially. When the serial data transfer
is complete, the transmitter will again answer a POLL. command. The card can be turned
off with a STAT signal if no more data is available for transfer.
4.2
,8025 CRT TERMINAL INPUT/OUT STRUCTURE
.'
The 8025 CRT Terminal input/output structure is built around a data bus consisting of 14 memory address lines (MA Data Bus), eight data input lines (A Data Bus),
eight data output lines (Bdata Bus), a priority signal, and a number of timing and
cont'rol signals.
The terminal card cage has numbered slots for up to 17 cards. The first 7
slots 'are occupied by basic function cards, with slot 7 being used for the basic
processor (CPU). Slot 8 is generally used for the program card, which may be a PROM,
ROM, ROM/PROM, or PROM/RAM. For some configurations, the DMA processor must be located next to the CPU, in which case the program card is moved over to slot 9 (the
wiring of slots 8 and 9 is the sa~e).
After the program card, the cage accepts either memory or input-output cards
in any order or combination. The position of a card relative to the basic processor,
however, determines the card's priority for responding to a POLL I/O command. The
Terminator Card appears in the last (leftmost) occu~ied slot of the card cage.
4.2.1
Memory Cards
Memory cards can be of either the ROM (storing programs or data) or RAM
read/write variety.
Up to l6,384 bytes of memory can be addressed. Memory can consist of PROM,
ROM, or RAM, and includes 1-15 kilobytes of RAM used for video refresh. The display
RAM must occupy the highest part of memory and, because of the restart instructions.
the program must occupy the lowest part. Since memory is normally packaged with
4,096 bytes per card, a maximum of four memory cards may be installed. The PROM/ROM
-qrd can hold up to 4K of ROM and 2K of PROM for a total of 6K.
Each memory card has the most significant two bits of its address wired to
the memory-desired sector, and in most cases the ROM card is wired to sector 0
(address 0 - 4096) with additional ROM s
4-6
'
8
• ••
EORY OP OPERATION
RS232 INTERFACE CARD
(3 EACH)
CLICK/BEEP
LEO DATA CHi
CURSOR CONTROL CARD
_~~~R~EF~R~E~S~H~B~U~F_F_E_R~C_A_R_D__~I______~
KEYBOARD CARD
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T
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SECTION 4
T_
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••••••
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CARD
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F1gure 4-l. 8025 CRT
bloCk d1agram.
te~nal
4-7
THEORY OF OPERATION
Table 4-1.
SECTION 4
Sources and distribution of signals in the 8025 CRT Termdnal.
SIGNAL USED
BY
SIGNAL
SOURCE
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"
4-9
THEORY OF OPERATION
Table 4-1.
SECTION 4
Sources and distribution of signals in the 8025 CRT Terminal.
SIGNAL USED
BY
QJ
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X
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X
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X
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X
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X
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X
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-
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X
X X X
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X X
X
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X X
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X X
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X X
X
X
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X X
X X
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X X
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X
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to 11-1... 110 0 0
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X
X
X
THEORY OF OPERATION
Table 4-1.
SECTION 4
Sources and distribution of signals in the 8025 CRT Terndnal.
SIGNAL USED
BY
r-I
Processor
"
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X X
X
X X
X
X X
X X
X
X
X X
X
X X
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X X
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).
REF ADRS
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X
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4-11
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U
THEORY OF OPERATION
Table 4-1.
SECTION 4
Sources and distribution of signals in the 8025 CRT Terminal.
SIGNAL USED
BY
0
~
.jJ
c::
SIGNAL
SOURCE
0
u
~
SIGNAL
MNEMONIC
Refresh Buffer
-0-4
f:l
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8
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~
~
0
III
III
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U
0
~
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X
X
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X
X
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X
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CGl
CG2
CG3
CG4
. CGS
CG6
CG7
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X
X
X
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-CS3
X
X
EXT ADRS
X
INHLD
X
X
LCLSB
LCMSB
X
X
X
LITE 1
LITE 2
LITE 5
4-12
~
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BLANK
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U
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ell
~
THEORY OF OPERATION
Table 4-1.
SECTION 4
Sources and distribution of signals in the 8025 CRT TerDdnal.
SIGNAL USED
BY
>.
.-f
~
0
~
4J
SIGNAL
SOURCE
~
u0
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SIGNAL
MNEMONIC
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..
X
X
SR COUNT
CNT 80
X
MAO
X
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MA4
X
X
X
X
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X
. MA6
MAIO
X
X
X
X
X
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X
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X
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X
X
X
X
X
X
X
X
X
MA2
MA3
..
.
.
MA7
MA8
MA9
•
REF
-RDO
R/W
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"
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4-13
~
4J
0
LITE 11
LOAD "F"
~
~
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LITE 10
LITE 12
~
4J
8
2
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B
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a.
III
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C
5
THEORY OF OPERATION
Table 4-1.
SECTION 4
Sources and distribution of signals in the 8025 CRT Termdnal.
SIGNAL USED
BY
SIGNAL
SOURCE
....
e
-g
0
u
-RD7
+
Q:l
III
III
.s::
III
X
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X
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X
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MATCH
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X
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POLL
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X
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X
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X
X
X
X
X
X
X
X
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KDB2
KDB3
KDB4
KDBS
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N
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•
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"
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Q:l
11-1
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X
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Q)
....
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c::
0
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III
III
X
VIDEO
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Video Control
.
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m
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cu
11-1
11-1
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cu cu cu
0
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SIGNAL
MNEMONIC
Refresh Control
>J..I
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KDB7
4-14
THEORY OF OPERATION
Table 4-1.
SECTION 4
Sources and distribution of signals in the 8025 CRT Terminal.
SIGNAL USED
BY
Q.)
r-I
0
~
u
0
Ul
Ul
Ql
tJ>
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0.-1
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til
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p::
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ADB7
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-ADB3
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RS-232 Interface
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+12 V (Reg. )
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u
e
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-RSTO
X
-RSTI
-RST2
X
X
•
4-15
THEORY OF OPERATION
4.2.2
Program-Processor Controlled I/O Cards
SECTION 4
The RS-232 Interface Card is an example of a program-processor controlled
I/O card. This type of I/O card transfers data to and from the CPU one character
at a time. The transfer is performed under program control of the CPU.
Four types of I/O commands are used in the transfer: POLL, 100, lOB, and
STAT (status). POLL, 100, and lOB are general commands; STAT is a specific command.
These commands are summarized as follows:
POLL (Produced by INP a wi.thin CPU). The POLL command is used to determine
if any device on the data bus has data to be transferred in either direction. As the
command travels down the bus from the CPU, it passes through each of the interface
cards in turn. The first device along the way which is ready for data transfer in
effect selects itself by inhibiting further travel of the command. The selected device returns its address (in the lower-order five bits of eigh~ bit bytes) to the
CPU's register. The higher-order three bits sent to the CPU contains device status
information which varies with the device. If no device requires service, the CPU
receives an address of zero.
When a non-zero address appears, the processor determines what kind of I/O
device requires service and responds with an appropriate set of commands. For the
actual data transfer, in either direction, the processor sends an lOB or 100 command
to the interface. Output data is placed in the CPU's A register prior to 100 or lOB,
while input data appears in the register upon completion of 100 or lOB.
100 (Froduced by INP 1 within CPU). With the 100 command the contents of
trre CPU's A register becomes available to the device and the device may specify the
new contents of the register. 100 also causes the device to deselect itself. Every
POLL is followed in succession by an 100 tc prevent system lock up; that is, only
one device at a time can be selected.
lOB (Produced by INP- 3 within CPU). The lOB command is essentially the same
as the 100 except that lOB does not cause the card to deselect itself. Deselection
is accomplished wi t"h an 100 cr STATUS command.
STATUS (Produced by INP within CPU). With the STATUS command the five
lower-order bits of the CPU's A register are interpreted as a device address. The
three higher-order bits of the register are interpreted as status bits to be written
into the device's status register. Typically these bits are: on/off device, on/off
POLL response, and disable writing of the first two bits. The CPU's A register is
respecified as the current contents of the addressed device'S status register. At
least three of the eight status register bits will be: on/off device, on/off POLL
response, and device ready regardless of on/off status.
.
.
In general, the three bits of status included in a device's response to a
POLL will also be included in its response to a STATUS.
4.2.3
OMA Transfer I/O Cards
OMA (direct memory access) transfer I/O cards work with a D~~ Processor
Card to transfer data between the Refresh Memory and high-speed, block-oriented devices. Examples of such devices include tape cassette drives. and line printers. OMA
transfers can move data from or to memory at rates up to 600,000 bytes per second
4-16
THEORY OF OPERATION
without Processor Card Control.
SECTION 4
The CPU sets up a DMA transfer by sending the I/O card a status command and
control information. Once the operation is set up, the DMA Processor and I/O cards
assume full control of addressing and other data transfer functions, including the
control of bus priority. The data bus is available for DMA transfers whenever the
Processor Card does not need it (approximately 80% of the time during normal operation).
In general, DMA operations transfer memory data in blocks. The starting
address and number of words in the block are sent to the DMA processor via a normal program-processor data transfer. Once this information is in the DMA Processor,
the transfer can begin and is then transferred sequentially, beginning with the starting address. The address is incremented (or decremented) for each transfer until
the number of tra!1sfers defined by the block length is complet,ed. When the transfer
is complete the I/O card becomes ready. That is, it will answer a POLL command and
either be turned off to wait for more data or reset to transfer a new block of data.
4.3
CHARACTER GENERATION
An understanding of how characters are formed on the 8025 CRT screen will
help'in following the card descriptions presented later in this section.
The CRT screen can be thought of as a large matrix of small light elements,
or dots, that can be turned on and off. In this context the overall video presentation is made up of light and dark dots.
The.basic display format for the 8025 Terminal is 80 characters per line
with a maximum of 24 line~ per frame (page). Thus, up to 1920 characters can be
displayed per page. Some terminals are configured for a 12 line page format with
a maximum of 960 displayed chara~ters per page.
A 10 x 10 dot area on the screen is allotted for each character displayed.
Consequently, each row of characters consisting of eighty 10 x 10 dot areas, requires
ten horizontal scan lines.
'
To provide for both character and row spacing, only nine dot lines (L) and
seven dot columns (C) are allotted for character generation. Only seven of the dot
lines, however, are displayable.
In addit\on, a half-dot horizontal shift feature creates an effective 7 x 14
(L x C) dot area for character generation. The function of this shift feature is explained in Section 4.3.1.
The eighth dot in each scan line is not displayed.
dot, as explained in Section 4.3.2.
4.3.1
It is used as a control
Upper Case Characters
5, D, E, F, H, I, K, L, M, N, P, R, T, W, X, and~. In Fi.t',ure -1-2, "H" is
used as an example of how characters in this group are formed. As stated earlier,
nine lines are allotted for each character, with only seven lines being displayable.
4-17
THEORY OF OPERATION
SECTION 4
Hence, the character generator must be addressed nine times to complete a character.
A three-bit octal code is used for line addressing (000 through Ill), which provides
eight lines. The ninth line is obtained by incrementing the eighth-line address back
to the first line (000).
As shown in Figure 4-2, dot formation (C-3 through C-9) for producing the
"H" is contained in the character generator for the first seven lines (L-O through
L-6, address 000 through 110). No dot information is contained in the eighth line
(L-7, address Ill), and no dots ever exist in c-o through C-2. Incrementing L-7
back to L-O makes the ninth line (L-8) dot information identical to L-O. For this
group of characters, however, L-8 dot information is blanked out and does not appear
on the CRT screen.
COLUMN
o
LI~E
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
oooe oooooe
oooeoooooe
oooeoooooe
oooeeeeeee
0 .ooe oooooe
OOO_oooooe
OOO_oooooe
LINE
ADDRESS CHARACTER I NFORMAT I ON
.
0000000000.
0000000000
0000000000
e·
Figure 4-2.
000
Yes
001
Yes
010
Yes
011
Yes
100
Yes
101
Yes
110
Yes
III
No (Increment to 000)
000
Yes, same as l-O but
blanked
illuminated dot
Example of upper case character (H).
4-18
THEORY OF OPERATION
SEC1'ION 4
A, C, G, J, 0 Q, 5, U, V, and Y. In Figure 4-3 "V" is used as an example
of how characters in this group are formed. The basic operations for creating the
other upper case characters also apply to this group. But in this group a non-displayable control dot can exist in C-2, L-l through L-6.
As shown in Figure 4-3, whenever a control dot is present in a line, CL-I,
L-2, and L-S), that line is shifted one-half dot position to the right. (Note that
a control dot is never used in L-O for this group of characters.) This feature makes
the characters displayed in this group more natural looking by creating an effective
7 x 14 dot area in an actual 7 x 7 dot area.
..
COLUMN
o
lI~E
2
3
4
5
6
7
8
9
2
3
4
·5
6
7
8
9
oooe oooooe
oo@eooooe 0
ooooeoooeo
oo@oeooeo a
ooooo:eoeoo
oo@ooeeooo
000000_000
0000000000
0000000000
0000000000
e.
Illuminated dot
Figure 4-3.
LI NE
ADDRESS CHARACTER INFORMATION
000
Yes
001
Yes, plus Bit 8 control
dot
Yes
010
011
100
Yes, plus 81t 8 control
dot
Yes
110
Yes, plus 8it 8 control
dot
Yes
111
No (Increment to 000)
000
Yes, same
blanked
101
~ • control dot
Example of Upper case character (V).
8S
L-O but
THEORY OF OPERATION
4.3.2
SECTION 4
Lower Case Characters
Characters Without Descenders. As shown in Figure 4-4, lower case characters without descenders (e.g., "h") are formed in the same way as the first group of
upper case character~ (8, D, E, etc.) discussed in Section 4.3.1.
COLUMN
LI NE
o
2
3
4
5
6
7
8
9
o
2
3
5
6
7
8
9
LI HE
ADDRESS
000_000000
000_000000
oooeoeeeoo
oooeeoooeo
oooeoooooe
oooeoooooe
oooeoooooe
0000000000
0000000000
0000000000
e·
CHARACTER INFORMATION
000
Yes
001
Yes
010
Yes
OIl
Yes
100
Yes
101
Yes
110
Yes
III
No
000
Yes, same as L-O but
blanked
(Increment to 000)
illuminated dot
Figure 4-4.
Example of lower case character (h).
Characters With Descenders (g, j, p, q, and y). Using "p" as an example,
Figure 4-5 shows how lower-case characters with descenders are. formed. Again, the
same basic operations as for the other lower-case characters apply. For this group,
however, a control dot in C-2, L-O, in addition to producing the half-dot shift, indicates.that dot formation in L-O will be used in the ninth line (L-S) of the display. That is, when L-7 (111) is incremented to L-S (000), the dot information in
L-O will not be blanked out as it would for lower-case characters without descenders.
Note that, since the control dot in C-2, L-O produces the half-dot shift, all other
scan lines in the character must Also be shifted if the character has a vertical
straight line.
4.. 20
THEORY OF OPERATION
SECTION 4
COLUMN
LI NE
o
o
2
4
3
5
6
7
8
9
LINE
ADDRESS
CHARACTER INFORMATION
OOO@ftOOOOO
000
0000000000
Yes, but blanked, plus
control dot
001
No
2
ooo@eeeeeo
010
Yes
3
0000eOOOOe
011
Yes
4
OOO~
100
Yes
101
Yes
110
Yes
Yes (Increment to 000)
6
eooooe
ooo@eooooe
ooo@eeeeeo
7
ooo~eooooo
111
8
ooo~eooooo
000
9
0000000000
5
e
=
il'l-uminated dot
Figure 4-5.
~
Yes, same as L-O but
unblanked
=
control dot
Example of lower case character (p).
4.4
CARD/SECTION DESCRIPTIONS
4.4.1
Power Supply
Except for the de voltages used in the CRT Display, the Power Supply provides
all voltages required by the 8025 CRT Terminal.
Block Diagram Analysis. As shown by the simplified block diagram in Figure
4-6, the Power Supply consists of a power supply assembly and a regulator card.
The
~ectified
output voltage of Tl is applied to the 5-vo1t regulator, which
4-21
THEORY OF OPERATION
SECTION 4
maintains a constant 5 V dc output with the aid of the current shunt transistor.
Regulated ±12 V dc outputs are produced by T2, a bridge rectifier, and
two voltage regulators. Another section of T2 supplies a 6.3 V ac output as well
as the input voltage to another bridge rectfier that provides an unregulated 80 V dc.
,-
REGULA~-l
CARD
FULL
WAVE
RECTIFIER
BRIDGE
RECTIFIER
IL _____ J
I
I
BRIDGE
RECTIFIER
+80
v de
..
6.3 V de
Figure 4-6.
Circuit Description.
o
Power supply block diagram.
Refer to schematic diagrams in Section 8.
With the terminal on/off switch closed, primary power is applied through
fuse F201 to the fans assembly and to the primary windings of step-down transformer
T2. Power is also applied via fuse F202 to the primary of step-down transformer TI.
One secondary winding (10, 11) of T2 supplies 6.3 V ac for the display CRT
filament via J61-3,4. The 80 V dc output for the 8025 CRT Display is derived from
the voltage across another secondary winding (8, 9) of T2. This voltage is rectified
by bridge rectifier (CR4) and filtered by C4.
Bridge rectifier eR3, connected across the third secondary winding (12, 14)
of T2, is the source for the +12 and -12 V dc supplies.
4-22
THEORY OF OPERATION
SECTION 4
The positive output of CR3, filtered by C3, is fed to the regulator assembly
via J6-5 and motherboard lines 53-56. The negative output is filtered by C2 and
applied to J62-4 and motherboard lines 17-20. Two IC voltage regulators, Z2 and
Z3, provide regulated -12 V dc and +12 V dc, respectively. Capacitors C7 and C8 provide additional filtering. Output bypass capacitors, ClO and Cll, improve response
time by attenuating transients.
The voltage across the secondary of Tl is rectified by full-wave rectifier
CRI and CR2, filtered by CI, and applied to J63-1,2,3, and motherboard lines 59-62.
The voltage on lines 59-62 is applied to IC voltage regulator Zl, which
maintains a constant voltage on motherboard lines 71-80, and 65-66 at currents below
700 milliamps. The level of this output is set by R4 while C6 provides additional
filtering of the input to Zl and C9 improves transient response. The voltage drop
across Rl controls the current through Ql.
4.4.2 CRT Display
The CRT Display in the terminal is basically a IS - inch television monitor.
It provides visual readout of input data from the keyboard or from external devices.
Block Diagram Analysis. As shown by the simplified block diagram in Figure
4-7; the CRT Display is made up of four major sections: video, vertical sweep, horizontal sweep, and low-voltage regulator.
An adjustable closed-loop voltage regulator provides a constant output to
all stages in the CRT Display. The X-ray protection circuit prevents any X-radiation
due to line voltage surges or regulator failure. Under those conditions, the circuit
disables the horizontal drive multi-vibrator.
Video inputs are amplified and inverted by the video amplifier driver. The
video amplifier output is coupled directly to the video output stage, which provides
a low-impedance source for driving the cathode of the CRT.
The vertical oscillator is a relaxatiqn oscillator synchronized to the vertical interval which is s'et by the vertical drive input. A sawtooth output from the
oscillator is directly coupled to a driver amplifier, the output of which is applied
to the vertical output. 'fhe vertical output in turn is transformer coupled to the
yoke.
Horizontal drive pulses, after being delayed by an ~djustable delay circuit, are applied to the horizontal drive one-shot. This delay compensates for inherent deflection-circuit delays. The output of the one-shot is coupled to the
horizontal output stage, which supplies the correct horizontal scanning currents
and the high-voltage pulses for the high-voltage supply.
Circuit Description. Refer to schematic diagram 95-146-02 in Section 8
and to the voltage waveforms shown in Figure 4-8.
The video section consists of QI03 and Ql04 with their associated circui try.
THEORY OF OPERATION
SECTION 4
The video amplifier consists of Ql02 and its associated circuitry. The
incoming video signal (typically 4 V P-P) is applied to the base of Q103. The gain
of this stage can be varied from 12 to 25 with Rl19. the video gain adjustment. QI03
operates as a class B amplifier and remains cut off until a dc-coupled. positivegoing signal arrives at its base and turns the transistor on. Rl18 and R1l9 add series feedback to make the voltage gain relatively independent of transistor variations.
This feedback also stabilizes against voltage and current changes caused by ambient
temperature variations.
The negative-going signal at the collector of Ql03 is dc coupled to the
base of Ql04. the video output. Ql04 is an emitter follower that supplies a low
source impedance for driving the cathode of the CRT. Class-B biasing of the video
output allows a maximum available contrast ratio by providing a large video output
signal to modulate the CRT cathode. Typically a video output of about 25 V P-P is
required for optimum contrast.
Overall brightness of the display is determined by the negative potential
at the grid of VI. The normal adjustment range of CRT grid voltage is from +10 to
-100 V dc. This voltage is set with the brightness control located on the terminal
keyboard.
.
The vertical sweep section is made up of QlOl. Ql02. and Q122.
QlOl. a programmable unijunction transistor, with its associated circuitry
forms a relaxation oscillator operating at the vertical sweep rate. Timing is determined by RC network RI06-108, CI03. and CI04. When power is applied, Cl03 and CI04
charge toward +SS V dc through RI06 and Rl07. The charging rate is set by the time
constant of the network. Capacitors CI03 anrl CI04 continue charging until the anode
voltage of QlOI is within 0.6 V of the gate voltage. When this occurs. QIOI fires,
and Cl03 and CI04 rapidly discharge through QIOI and LIOI to near ground. QlOl then
turns off and· allows CI03 ~d CI04 to recharge to the firing potential.
The gate threshold voltage for QIOl is developed across RIOS, the level
being established by the network RI03. CRIOI, CRI02, and RIOS. This voltage, variable with the vertical hold control (RI03), is typically 4.6 V. Thus CI03 and CI04
must charge to approximately 4 V before QIOI fires.
..
VIDEO INPUT
FROM VIDEO CONTROL CARD
VERTICAL DRIVE
~
FROM TIMING CARD
VERTICAL
OSCillATOR
101011
VIDEO
AMPLIFIER
DRIVER
VERTICAL
DRIVE
AMPLIFIER
~
..
FROM TIMING CARD
10109 1121
~
101021
ADJUSTABLE
DElAY
~
~
~
VIDEO
OUTPUT
CQl041
!01031
•
HORIZONT Al DRIVE
~
HORIZONTAL
DRIVE
MUl TlVIBRATOR ~
!0114,1151
T
VERTICAL
OUTPUT
101221
HORIZONTAL
OUTPUT
101231
~I
HI VOLTAGE
SU1'I'l Y
~
X RADIATION
PROTECTION
!0111
+50 VOC
lOW VOL TAGE
- -........ ,
REGULATOR
1
r::I
L::.J
+55 VOC
10121,0105 1081
Figure 4-7.
CRT display block diagram.
4-24
THEORY OF OPERATION
SECTION 4
QlDl can also be fired by rapidly lowering the gate voltage to within 0.6 V
of the anode voltage. This is done by applying a negative synchronization pulse
through RlOl, ClOl, CRIOl, and CRI02 to reduce or stop current flow through RIDS.
When a synchronization pulse is applied, the voltage across RIDS instantly drops
one or two volts below the gate threshold potential. Such a drop at the gate of
QlOl causes it to fire, providing the timing network has charged to about 4 volts.
In summary, QlOl can be fired by (1) allowing the anode voltage to rise
within 0.6 V of the gate potential, or (2) rapidly lowering the gate potential to
within 0.6 V of the anode voltage. Without vertical synchronization pulses, QlOl
oscillates by anode voltage changes. With vertical synchronization it is operated
by gate voltage changes.
The amplitude of the sawtooth waveform developed at the anode of Q101 is
determined by C102, Rl06, and R107. R107, the height adjustmerr~, varies the RC time
constant and, in consequence, the voltage applied to the oscillator circuit. This
voltage, developed across Cl02, is typically 14 V. The sawtooth output at the anode
of QlOl is directly coupled to the base of vertical drive amplifier Ql02.
Because the slope and linearity of the sawtooth input to QI02 would produce a distorted vertical sweep, wave-shaping is needed. Capacitors C103 and Cl04
improve linearity, and the slope is modified as follows: The sawtooth output of
QlO2' is fed back to CI04, through RllO and Rl09. Capacitor C104 shapes this feedback into a parabola and adds it to the input of QI02 to change the slope. Potentiometer RI09, the vertical linearity adjustment, determines the slope change rate.
Consequently, emitter follower Ql02 supplies a suitable sawtooth waveform of about
5 V amplitude to the base of Q122.
The .vertical output stage, Q122, operates as a class-B amplifier with output transformer-coupled to provide a proper impedance match with the yoke (L124).
During retrace time, a large 'positive pulse (typically 300 V) is developed across
T102. This pulse r.everses the current through the yoke and moves the beam from the
bottom of the screen to the top. Resistor Rl21 prevents oscillations by providing
damping across the vertical deflection coils. Network CRI03, C107, and Rl13 keeps
the collector voltage of Q122 at safe levels du!ing retrace.
The horizontal sweep section consists of QI09 through QllS and Q123.
The horizontal output transistor, Q123, has a storage period of several
microseconds. To compensate for this period, a drive pulse that occurs a few microseconds before flyback is needed. Such a pulse is obtained by delaying the synchronization input nearly one full horizontal sweep. This delay effectively provides a few
microseconds lead time for the drive pulse. The circuits that provide the delay
are one-shot Q109, Qlll and amplifier, Q112.
The positive horizontal sync input signal is differentiated by R140, C115,
and Rl37 so that the positive-going edge of the signal triggers Q1IO on. The reSulting negative pulse at the collector of QIIO triggers the one-shot (QI09, Ql11),
and the collectors of Qlll and Ql09 go low and high, respectively. After one-half
horizontal line, the one-shot returns to its stable state (collectors of Qlll and
Ql09 high and low respectively). This change generates a negative gate"which is
applied through C117 to the base of Q1l2. Transistor Q112 in turn generates a 15 V
positive gate at its collector. After one-third line, C117 discharges through R144
4-25
THEORY OF OPERATION
SECI'ION 4
~I~'--------------------H--------------------~.I
I
HORIZONTAL
DRIVE
I
~~~j F~
r------
I
t,Jf: :. ....---------------~II4~'-.,--------------......;-;-I.~~
+4".IIV~
I
I
00.2 'O,ZV
I
r'-- HIGH
~'O.7••- - .
LOW LEVEL DURING TIME OF NO CRT DISPLAY OUl1'lJT
HIGH LEVEL DURING TIME OF CRT DISPLAY OUTPUT
_ _ BLANKING
TIME
I~
n.sv
VERTICAL
DRIVE
00.2 -O.ZV
I
I
~
I
•
VIDEO
INFORMATION
!~ .HORIZONTA~
I
+4
LOW
~2.7..
I
HORIZONTAL
BLANKING
HIGH
~I
I
V
1~'_. . F-·~"~·
I
~
LOW
..
I
I I
HIGH
LOW
288., ,. SCAN LINES)
I
~I~~-----------V'-------------~~~I
I
16.117•• 160 Hz) Z60 SCAN' LINES
I
I
+4 • , 5V
I
OR ZOo. 150 Hz) 312 SCAN LINES
HIGH
1m••.
VERTICAL
BLANKING
120 SCAN LINES)
..
~
+0.2 -0.2V
jfl
I
,
VERTICAL
~BLANKING
I
TIME
VIDEO
INFORMATION
~
LOW
I
,~I
-
I
NOTES
H .. time from ttIIrt of one hne to It1ft at""t Ii,..
V • time from mrt of one fiekl to star1 of .... , f;.ki.
Figure 4-8.
CRT waveforms.
and R143 to terminate the positive gate at the collector of Ql12. Horizontal centering adjustment R143 varies the one-third line delay by changing the time constant
of the Cl17 discharge path. The trailing edge of the positive gate is differentiated
by C12l and R153 to trigger the horizontal drive one-shot (Ql14, Ql15).
In the staple state o~ the horizontal drive one-shot, Ql14 is held at saturation (low state) by virtue of the base current flowing through RlS2 and CR109.
Consequently Ql15 is at cutoff (high state). When the negative-going differentiated
pulse from Ql12 is applied to the base of Ql14, Ql14 is driven to cutoff to produce
a positive pulse at the base of QllS. Qll5 then becomes saturated (low state). The
resulting negative feedback through R157, R156, C122, and CRl09 to the base of Ql14
holds that transistor at cutoff. After approximately one-half line, C122 discharges
through R152 t causing Ql14 to conduct (low state). Transistor QllS, consequently, is
cut off to produce a IOO-volt gate at its collector with an additional IOO-volt transientat the leading edge. This positive gate is clipped and limited to approximately
55 V by Rl57 and CRIIO and reduced to approximately 2S V by divider network RlS6 and
RISS. Feedback through CI22 initiates regeneration and holds Ql14 in conduction
until the next trigger pulse arrives.
4-26
THEORY OF OPERATION
SECTION 4
The phasing and turns ratio of transformer TlOl are such that a negative
100-volt gate at the collector of Q115 creates a negative gate of several volts at
the base of the horizontal output transistor (Q123).
When Qll5 conducts, energy is stored in TlOl and the voltage at the secondary is negative, so that Q123 is cut off. When the primary current of TlOl is interrupted by collector cutoff of Q115, the secondary voltage of nOl reverses polarity,
causing Q123 to start conducting. The collector current of Q123 slowly increases a
sawtooth pattern during the remaining period of the horizontal line scan. Although
Q123 will be at collector saturation, current flow is determined by the collector
load (yoke inductance and flyback transformer). Typically the peak sawtooth current
through Ql23 is 2 to 3 amperes, depending upon line rate and length of the horizontal
sweep.
The horizontal output stage has three main functions:.. (1) supply the yoke
(LIOI) with the correct horizontal scanning currents, (2) develop 17 kV dc for the
CRT. anode, and (3) develop +800 V dc and -100 V dc for the CRT bias.
Transistor Q123 acts as a switch that is turned on or off by the rectangular waveform on its base. When Ql23 is turned on, the supply voltage plus the charge
onC135 causes L124 current to increase in a linear manner to move the beam from
near center screen to the right side. At this time, Ql23 is turned off by a negative' voltage on its base, which causes the output circuit to complete one-half cycle
of sine-wave oscillation. A positive flyback voltage pulse--several microseconds in
d~ration, several hundred volts in amplitude, and in the form of a half-cycle sine
wave--is developed by the combined inductance of L124 and TI03 plus Cl~7. The peak
inducti ve energy stored in L124 during the sweep time is then transferred to e127 and
the distributed capacity in L124. During this cycle the beam is returned to the
center of the·screen.
.
Capacitor C127 and the distributed capacity in L124 now discharge into L124,
which induces a cutrent in a direction opposite to the current in the previous part
of the cycle. The magnetic field thus created arowd L124 moves the scanning beam to
the left of the screen.
After one half cycle, the voltage aCl'OSS C127 drops below ground potential,
which causes damper diode CRl16 to conduct and thus keeps the flyback pulse from
oscillating. The inductive energy stored in the yoke by the discharge of its distributed capacity and C127 is now released to provide sweep for the first half of
the scanning line. The released energy also charges C135 through CR116.The cycle
repeats itself whep the base voltage of Q123 is driven positive again.
Capacitor C135, in series with L124, also serves to block dc through L124
and provide "5" shaping of the current waveform. "5" shaping compensates for the
stretching that would occur at the left and right sides of the CRT because the curvature of its face and the deflected beam do not describe the same arc.
The width control, Ll04, is placed in series with L124. The setting of
Ll04 determines the amowt of deflection current flowing through L124 and thus controls the width of the horizontal sweep.
The positive flyback pulse developed during the horizontal retrace time
is rectified by CRl14 and filtered by e125. This produces approximately 600 V dc,
4-27
THEORY OF OPERATION
SECTION 4
which is coupled through the focus control, R167, to the focusing grid (C4) of the
CRT (VI). Network CRl12, CRl13, C123, and C124 forms a voltage doubler that delivers approximately 1000 V dc to divider R163, R170. This divider provides approximately 800 V dc for the first anode (G2) of the CRT. The flyback pulse is also
transformer-coupled to the secondary of Tl03, and the stepped-up pulse is rectified
by CRlOO and CRl15 to produce approximately 17 kV dc and -100 V dc, respectively.
The 17 kV dc is the anode voltage for the CRT; the -100 V dc serves as the source
voltage for the brightness control.
Returning to the delay circuit (Ql09-Qlll), note that a separate and lower
supply voltage is used. A series dropping resistor, R15l, reduces the +55 V dc
supply voltage to approximately 25 V dc. This arrangement serves two purposes: (1)
it guards against the production of X-rays during an over-voltage condition, and
(2) it prevents triggering of Q123 by random drive pulses when the terminal is turned
on or off.
The circuitry that guards against X-ray production consists of SCR Q123,
zener diode VRl02, and associated components. Assume that the +55 V dc regulator
circuit fails and the output voltage exceeds approximately 60 V dc. The voltage
drop across divider network R147, R148, and R149 will also increase, causing current
to flow through VR102 and R150. The voltage developed across Rl50 then causes SCR
Ql13 to fire and to discharge Cl18. This effect drops the entire supply voltage
across R15l and disables Ql09-Qlll. Without drive, the horizontal output stage
and high-voltage supply are disabled also.
A separate, lower supply line also protects against triggering of the horizontal output transistor (Q123) by random drive pulses during turn-on or turn-off.
Normally, several ac cycles are required after turn-on to bring the +55 V dc bus up
to level. By virtue of the component values selected for Ql09, Qlll, and R15l, the
delay one-shot will not trigger until the regulator voltage exceeds approximately
+30 V dc. This dc voltage is adequate to provide stable operation of the horizontal drive one-shot and to supply adequate base drive to Q123. In this way, random
drive pulses and' poor collector saturation of Q123 are avoided.
During turn-off this separate supply line also offers some degree of protection against CRT spot burn. After power is turned off, Cl13 is rapidly discharged by the load current. The +55 V dc regulator output consequently decays rapidly
to 30 V de and Ql09, Qlll will fail to trigger below this level. As a result, Ql23
and the high-voltage circuit are disabled, reducing the discharge current from C113
to approximately one-third its former rate. The energy thus retained by Cl13 is
used mainly by the vertical deflection circuit for a significantly longer discharge
period. CRT beam energy is consequently distributed along the vertical axis to prevent spot burn w~ile the high voltage stored in the CRT aquadag is discharged.
The low voltage regulator circuit consists of Ql05-Q108, Q121, and related circuitry.
The +80 V dc at Pl02-l is dropped to +55 V dc by series regulator Q12l,
whose output is sampled by voltage divider R133, R134, and R13S. Approximately +7 V
dc, tapped from R134, is applied to the base of Ql08, while a reference voltage developed across VRIOI is applied to the emitter of Ql08. Th~s transistor develops
an error current that flows through Rl30 to the base of QI06 and the collector of
QI08 by QlOS, used as a dc current generator. 'The bias current tends to shift the
4-28
THEORY OF OPERATION
SECTION 4
base of QI06 in a positive direction while the current from QI08 tends to shift the
base in the negative direction. Thus, the error current from the collector of Ql08
controls QI06, which in turn controls Q12l. As a result, the output voltage is
maintained at +55 V dc despite variation in load or input voltage.
Foldback current limiting is provided by Ql07, R127, R128, and R129. Bias
current flowing through R127 and R129 to ground provides a drop of approximately 2.4
V dc across R127. Load current through R128 provides a vOltage drop that is proportional to the load current. If the load current exceeds 2.4 amperes, the emitter of
Ql07 is biased approximately 3 volts below the emitter of Ql2l, assuming a drop of
2.4 volts across Rl28 and 0.6 volt across CRl06. Since the base of Ql07 is biased
below the emitter of Ql21, Ql07 will conduct. The drop across Ql05 consequently
increases so as to reduce the output voltage of the power supply, and thereby limit
the peak current to approximately 2.4 amperes.
..
Should a short-circuit occur on the +55 V de line, the output voltage will
drop to near zero, and the short-circuit current will be limited to approximately
100 rnA. Removing the short-circuit allows the regulator to resume normal operation.
The average current through Ql21 is approximately 0.5 amp. Combined peak currents
of the horizontal and vertical deflection circuits, however, may be much greater
than the average current, even though electrolytic capacitors are used across the
+55 V dc line.
4.4.3
Timing Control Card
The timing control card supplies the basic clock and timing signals for
the 8025 CRT terminal. TIlis card is also the source of a power-on clear signal and
the four input/output signals used in the terminal .
.
Block Diagram Analysis. As shown by the simplified block diagram in Figure 4-9, the Timing Control Card consists of three basic circuits: the I/O (input/
output) command decoder, the power on clear (POC) circuit, and the basic timing generator for the terminal.
The decoder decodes I/O commands generated by circuits on the processor
card. Oecoded outputs are used on the cursor control card and the I/O interface
cards.
When power is applied to the terminal, the power-on clear circuit generates
a poe signal to clear the terminal. As indicated, poe is used by the processor,
refresh buffer, an~ I/O interface cards.
A hasic HF (high frequency) clock signal of 14.976 ~fHz is produced by dividing the master oscillator output of 29.952 ~~z with a divide-by-two counter.
The HF clock frequency is then counted down to provide the following clock signals:
HI - H LINE, RS ClK, ~l and ~2. and READ eLK (derived from 02).
Horizontal clock signals HI-H LINE are used to generate the timing signals hori: ontal sync (B SYNC), a composi te sync (CONP SYNC), composi te blanking (CO~fP
BLNK). and horizontal blanking - needed for the video presentation. The H BLNK
(horizontal blanking) output from the horizontal blanking generator is also inverted
to produce POS TIME.
4-29
THEORY OF OPERATION
SECTION 4
.
A vertical clock output, synchronized by H BLNK, produces basic vertical
timing signals (VI, V2, V4, V8, and VlO). VlO is counted down in a divide-by-26
counter to generate Re, which becomes a component of COMP BLNK. It is also divided
by 12 to supply RATE CLK.
Other timing logic on the card uses horizontal and vertical clock inputs
to supply additional timing signals. Three of these signals define the end of a
character row (EOR). the end of 24 character rows (EOP), and the line in the character row used for the cursor display (CURS LINE). The fourth signal (SET LDFF)
controls loading of a parallel-to-serial converter on the video control card.
NOTE:
Gates are described by package reference and output
pin number. Thus, XFS-4 means that gate in package XFS
which has its output on pin 4.
Circuit Description. Refer to schematic diagram 96-452-01 in Section 8,
and Figures 4-10 and 4-11 for signal timing.
Gates XFS-4 and -10 and XES-6 plus a BCD-to-decimal decoder (XE4) make
up the I/O command decoder. To get an output from the decoder, all inputs to XES-6
must be high and 170 must be low. Thus MA9 and MAIO levels determine which I/O
command is generated. The truth table for the decoder is shown as Table 4-2.
The POC circuit consists of a one-shot (XA6) with its associated circuitry. When power is turned on, C14 charges through Rll to +S V dc to fire the
one-shot. The Q output of XA6 is then inverted to provide the POC pulse on pin 72 •
. The balance of the schematic is devoted to the generation of timing signals for the terminal. - Ql, Q2 and their related components form a crystal-controlled
master clock at 29.9S2 MHz. Its output is coupled through XBI-8 to XAI-II, which
divides the clock frequency by two to supply HF CLK (high-frequency clock). HF CLK
(14.976 MHz) is applied to the character clock divider (XOS), RS clock divider (XB3,
XB2), and the first horizontal frequency clock (XE6).
HF CLK is divided by 10 in XOS, the character clock divider, to produce
H8 (1.497 MHz). H8 has a period of 670 nsec, the time allowed for a character scan
line. HI, H2, H4, and H8 outputs from XOS are used as indicated on the schematic.
A 1.497 MHz carry output (XOS-lS) enables the first counter (XE6) in the
horizontal clock to count on every tenth HF clock pulse. Thus, the ~haracter clock
frequencyis divided by 16 in XE6 and 6 in XC2 to supply H LINE, the horizontal frequency (lS.6 kHz).
HF CLK is divided by 4 and 13 in XB3 and XB2, respectively, to provide an
RS CLK of 288 kHz. XR3, a decade counter, is preset to a count of six so that it
operates as a divide-by-four counter. XB2 is a basic divide-by-16 counter. By presenting it to a count of 3, it operates as a divide-by-13 counter. These two counters
in combination, divide HF CLK by S2 to provide a 288 kHz output at XCS-2.
The ~l clock signals are derived from H4, HlO, and RiO with a J-K masterslave flip-flop (XC4) and its associated gates. The,2 clock signals are derived
from HI, H2, H8, and HIO with another J.-K flip-flop (XC4). In both circuits the J
and K inputs and the trailing edge of HF CLK determine the positive-going and
4-30
THEORY OF OPERATION
SECTION 4
Table 4-2.
CPU
I/O command decoder truth table.
ACTIVE OUTPUTS
INPUTS
COMMAND
CODE
MA8
MAll - 13, WAIT, I/O
MAg
MAIO
INPO
H
L
L
L
L
INPI
H
L
H
L
H
INP2
H
L
L
H
INP3
H
L
H
H
FROM
CPU
--..
I/O
COMMAND
DECODER
HSYNC
r+- VSYNC
COMPOSITE
-.
SYNC
POLL. STAT. lOB. 100
~
fo
VIDEO
CONTRtL CARD
•
HORIZONTAL
FREQUENCY
:16&6
MASTER
CLOCK
1311 MH,I
~
HF
CLOCK
+
"- ~
RS
CLOCK
97"98
10 "4 NAVY
TO!232
"1.82
CLOCKS
•
"-
.......
....... 1
~
+5 V dc---.,.
POWER
ON
CLEAR
VERTICAL
CLOCK
0.
~
H
L
H
H
H
H
L
H
H
H
H
L
.
TO
VIDEO
r--. CONTROL
~~~SOR
INVERTER
ROW
CARRY
COUNTER
13
r-~ POSTIME
~
RATE
CLOCK
12
r-+
READ
CLOCK
Poe
Timing control card block diagram.
4-31
lOB
H
OUT
Figure 4-9.
STAT
H
TO VIDEO CONTROL CARD
+
OTHER
TIMING
LOGIC
100
CARDS
l
CHARACTER
CLOCK
1O
+
t
HORIZONTAL
BLANKING
GENERATOR
J
:2
,
COMPOSITE
BLANKING
2-CHARACTER
DELAY
POLL
--.
TO
PROCESSOR.
REFRESH
BUFFER"
VIDEO CONTROL
CAR OS
THEORY OF OPERATION
SECTION 4
negative-going transitions of the clock pulses, respectively. Each clock circuit
operates to provide an output pulse for every 20 HF clock pulses. Thus, '1 and
'2 pulses occur at the rate of 748.8 kHz. They do not overlap, however, since
different horizontal timing signals are used for each circuit. For the same reason,
'1 and ,2 have different pulse widths--402 nsec and 335 nsec, respectively.
READ CLK (read clock) is produced by an edge-triggered D-type flip-flop
(XC3-6). Signal 12 at XC3-3 determines the positive-going transition of READ CLK.
HI, H8, and HlO are NAND-gated by XES-8 to preset XC3-6 low. Thus, the preset input to XC3 determines the negative-going transition of READ CLK. The timing of HI,
H8, HID, and 12 produces a square-wave clock signal at the '2 rate, 748.8 kHz.
Horizontal timin~ signals for the video presentation are generated in XBS-S
(J-K flip-flop) and XC3-S (edge triggered D-type flip-flop).
H BLNK (horizontal blanking) is produced at XBS-S. On the negative edge
of H LINE, XBS-S is set high and remains high until XBS is cleared by the output on
XF2-l2. The timing of the clear operation depends upon the jumper arrangement (E3
through E7) at the input to XF2. Normally, E3 and E4 are connected; other jumper
arrangements are used for special terminal configurations.
With only E3 and E4 connected, XBS is cleared when H160 goes high. This
event produces a 10.72 usec, 15.6 Hz H BLNK pulse used with the standard 80-characterper-line display and the optional 40-character-per-line display.
H BLNK is inverted by XCS-12 to become POS TIME. H BLNK is also used for
the J-K inputs to the XBS-2 flip-flop, which produces the horizontal component of
composite sync (COMP SYNC). The negative edge of H40 sets XBS. Eight character
periods later it·is reset by HI60 at XBS-13 to produce a 5.36 usee pulse. The output on XB5-2 is OR-gated by XE2:ll to the 20 input of XE3, a two-Character-period
delay register. This delay compensates for the time between character addressing
and the character display on the CRT. Note that XE3 is clocked by the output on
pin 8 of XE2. This clock pulse is developed from H2, H4, and HlO to clock XE3 every
other character period.
Horizontal sync (H SYNC) is generated at pin 8 of XC3. XC3 is set by the
gated output of H40, HSO, H320, and H LINE on XD3-8. It is reset by XBS-2 8.04 usec
later to supply the H SYNC input to XE3 at the line rate of 15.6 kHz.
The vertical timing signals for the video presentation are generated by
XCI, XC2, and XD2 whiph, count-down H BLNK pulses.
XCI divides by 10 or 12, depending on the power-line frequency, to provide
VI, V2, V4 and V8. For 60 Hz operation, XCI is loaded by VI and V8 through XF2-S.
It is loaded by VI, V2 (jumper ES-E9 connected), and V8 for 50 Hz operation. (Note
that at 50 Hz there are 2 extra lines between character rows and 52 extra lines per
frame). The output of XF2-8 also becomes the EOR (end of row) signal at XFl-IO.
EOR is a 63.6 usec pulse occurring at a 1.56 kHz rate.
The V8 output of XCI is divided by 2 and 13 in XC2 and XD2, respectively,
with XC2 supplying VIO and XD2 providing RC (row carry). RC is a 1.28 millisecond
pulse occurring at a 60 Hz rate.
4-32
THEORY OF OPERATION
SECTION 4
HFCLK
Hl
H2
H4 - - -...
HiJ - - - - - - - - .
H9 ------------~
C,
Hl0 - - - - - -_____...,
H4~ -------------~~------------_+----------------~----------
sEnti F/F - - - - - - - . . . . ,
02
---------t----..
01 - - -......
[0 cNf - - - - - -____~-....
..
READ CLOCK _ _ _ _ _ _ _.....
F.1gure 4-10.
TiC.ontrol card timing d.1agram.
4-33
SECTIOt-.: 4-
H100
------------~
H320
-----------4---------..."
H LINE
POS TIME
---------f
HBLNK ----------~
H DRIVE
HSVNC
Figure 4-11a.
T1m!!rg con!!Ol card t1m1ng d1agram.
4-35
SECTIm: 4
THEORY OF OPERATD
Vl
V2 - - - - - '
V4 _ _ _ _ _ _ _...1
va
V10
EaR
-----------------4---------.J
-----------------4----------------4
-----------------4----------~
CURS LINE - - - - -_________4-_______.J
RC------------------+--------------~
EOP
--------~------~---------------+--------------~------------~
+ ______________+-__________....J
V DRIVE ______________
COMP SYNC
----,..-1..--
CaMP
BLANKING
Figure 4-11b.
Timrffg control card tlndng diagram.
4-37
THEORY OF OPERATION
SECTION 4
rue.
RC is inverted by XD6-14 to
RC blanks the CRT during vertical retrace,
which occurs during the last two character rows in a frame. It is also divided by
12 in XD6 to produce the RATE (rate clock) at 5 Hz.
Vertical sync (V SYNC) signals are derived by gating V4, V8, RC and VIO
through XEl-'IO and -13 and XE2 to the two-character delay, XE3. V SYNC, with a
350 usec pulse width, occurs at a 60 Hz rate.
Composite sync (COMP SYNC) is obtained by OR-gating the horizontal sync
and vertical equalization pulses in XE2-11 to the 2D input of XE3. Vertical components are gated through to XDI-8 during V DRIVE when V4 and H SYNC at XC3-8 are
high. Thus, during the display position of the field of COMP SYNC pulses are 8.04
usee long, occuring once every horizont.al line. During the vertical sync period
there are four 54 usec pulses at the horizontal frequency. COMP SYNC is also
applied to XE3.
Composite blanking (COMP BLNK) is the OR-gated combination of H BLNK,
vertical blanking (RC), and 10th through 12th lines of ea~h character row (SO Hz
version only). The 10th through 12th line input to OR gate XD3 (pin 4) is low when
VI and V2 are high at XEl-S and -6. Composite blanking is applied to the twocharacter delay (XE3) and also to an inverter (XF3-l2) to supply an undelayed hlanking
(UND BLNK) signal.
The remaining signals generated on the Timing Control Card are cursor
line (CURS LINE), end of page (EOP), and set load flip-flop (SET LDFF).
Cursor line is produced by XDI (pin 6) whenever VI and V2 are low at
pins 5 and 6 of XEl and V8 is high. EOP is generated by decoding RC, VIO, and EOR
in XF2-6. A 63.6 usec output pulse, with a 60 Hz rate, appears at XF3-8 at the end
of every 24 character rows. SET LDFF is the NAND combination of HI and H8 at XC6-6.
This signal has a pulse width of 67 nsec and an H8 repetition rate (1.497 MHz).
4.4.4
Processor Card
The processor card controls nearly all terminal operations. It polls cards
on the A Data Bus to determine whether a card is ready to transfer data in either
direction. When a card is ready, the processor--working with the terminal memory-interprets and processes the data and enables the transfer.
Block Diagram Analysis. A simplified block diagram of the processor card
is provided in Figure 4-12. The processor card centers around an IC central processor
unit (CPU) designed to work with an external memory. Data enters and leaves the
CPU on an internal time-multiplexed data bus. The CPU has eight timing states,
labeled and defined as follows:
TI:
Time used to load least significant eight bits o~ ,ddress into external memory and increment CPU program
counter.
T2:
Time used to load most significant six bits of address
and two control bits into external memory; also to increment CPU program counter with a carry from Tl.
4-39
THEORY
SECfION 4
OF OPERATION
~R~;~T
1-_ _ _ _ _ _ _...
BOATA IUS
T3
MABUS
.,2 ....
--1. _~_~_AG_~
.......
AEAOCLOCK
----.....I
iiffiNc
'-------.4-.---------+ PCM7
ICCLK
CPUBUSV
T3 SYNC
~
iTo
Cl'URIW
Figure 4-12.
Processor card block diagram.
T3:
Time used to transfer data into or out of the CPU, obtain and decode instruction, or acknowledge READY:
refresh CPU internal memories.
T4,T5:
Time used by CPU to execute instruction.
TIl:
CPU acknowledgement of interrupt signal; replaces Tl
when CPU is interrupted.
STOPPED: Indicates CPU received a HALT instruction.
WAIT:
Indicates CPU READY line was low prior to end of T2
cycle.
Data on the A Data Bus comes in to the CPU through
ing T3. A precharge circuit decreases the input rise time.
CPU is placed on the B Data Bus during T3 and on the MA Data
or TIl. In addition, data from other sources can be applied
CPU is not transferring data.
the input drivers durOutput data from the
Bus during T2 and Tl
to the buses when the
Output-state signals from the CPU are decoded to provide the previously
described timing states.
4-40
THEORY OF OPERATION
SECTION 4
____ ~terrupt is used to restart the CPU program at a memory address specified
by RSTO-RST2. The interrupt sequence can be initiated by a POC, an interrupt signal (INT), or a decoded STOPPED signal. During an interrupt, the restart circuit
enters a restart address into the CPU to define the start location of the program.
A voltage reducer lowers the -12 V dc supply to -9 V dc for the CPU.
Circuit Description. Refer to
and to Figure 4-13 for signal timing.
s~hematic
diagram 96-369-01
in Section 8,
.
The control~u!s to the CPU (XC2) are ~l and'~2 clock signals, READY,
lnterrupt (TNT), and RSTO-2 (restart). The ~l and the ~2 inputs provide a 748.8
kHz two-phase, non-overlapping clock signal for the CPU.
READY inhibits the CPU when the external memory is not available for data
transfer. This input is not used in the 8025 CRT Terminal, since the memory is
always available.
The CPU can recognize interrupt only at certain times.
thus required to meet the timing requirements.
Control logic is
When TNT goes low, the negative~going edge--inverted by XBS--sets flipflop XA6 at pin 3. The leading edge of IC CLK (IC Clock) from XB6-11 sets the
other XA6 flip-flop at pin 11. The output on XA6-9 enters an INTERRUPT signal
into the CPU. When the CPU replies with a TII (decoded from SO, Sl, and S2), TIl
sets flip-flop XA4 at pin 1. This flip-flop enables the six interrupt NAND gates
(XC3, XC4) to restart the CPU during T3. Flip-flops XA6 and XA4 are reset at the
end and start of T3 at pins 1 and 4, respectively.
A PaC-initiated in):errupt is accomplished in the following manner. When
power is applied to the terminal pac goes high and is inverted by XBS-IO to reset
flip-flop XA3 at pin 10. The next low RATE pulse at pin 9 of XBS sets the XA3
flip-flop at pin 9.
Since RATE occurs at 5 pps, it produces an interrupt 0.2 sec
after power is applied. This delay allows the CPU to clear all its registers and
preset all its flip-flops before interrupt res~arts the program. Note that POC
also resets XA4 at pin 10, XAS at pin I, and XA6 at pin 13.
An interrupt can also be ~enerated when the CPU enters the stopped (STOP)
state; STOP sets flip-flop XA6 at pin 4. On the leading edge of IC CLK, the other
XA6 flip-flop is set at pin 11 to produce an interrupt signal at XA6-9.
The states of RSTO-2 specify the program restart address supplied to the
CPU when the interrupt gates are open during T3. For INf and STOP interrupts, one
of eight addresses can be specified (Oa, 108' 208' 30 g , 408' 5° 8 ,6° 8 , and 70 g ).
One of only four restart addresses (1~30a' 50 g , ana 708) can be specified for a
POC interrupt. This is true because RSTO is hela high by the output on pin 6 of XC4.
Thus, the least significant bit of the restart command is always low for a pac interrupt.
The SYNC output from the CPU indicates that it is on the second half of
the timing state represented by SO, 51, and 52. SO, 51, and 52 are decoded in XB2,
a BCn-to-decimal decoder, to indicate the state of the CPU at any time in the instruction cycle.
4-41
THEORY OF OPERATION
SECl'ION 4
Data on the A Data Bus is transferred to the CPU through eight opencollector TTL input drivers (XE3, XF3), which are enabled during T3 to gate data
into the CPU. A precharge circuit (QI, R7 through Rl6, and CRl through CRB) is
used to decrease the input rise time. This circuit switches in R7-14 during the
time (T3) data is entering the CPU. During the rest of the time, these resistors
are disconnected by CRI-B. Thus, the CPU does not have to drive the load presented by R7-14. The precharge circuit is switched in when T3 sets XA4 at pin II
to make XA4-6 high. Disconnect is performed when XA4 is reset at pin B by T2
SYNC and TIl or T2 SYNC when XCS-8 is high (CPU in read mode).
Data out of the CPU is OR-gated through XEl and XE2 to bus output drivers
XFl and XF2, and latch registers XD2 through XDS.
CPU data is placed on the B Data Bus when the bus output drivers are enabled by a high output from XF6-S. XF6-S is high whenever the CPU can trans fer
data in either direction (CPU BUSY and EXT ADDR are high).
The data transfer occurs during a READ instruction, the second half of
T2 or WAIT, or T3. The drivers are disconnected from the bus when the CPU cannot
transfer data (CPU BUSY or EXT ADDR are low)._ .This frees the bus. fox Il4A-type data
transfers.
.
During Tl or TIl, output data is loaded into the XD2 and XD4 registers to
provide the least significant eight bits of an address. The most significant six
bits are loaded into XD3 and XDS during T2. Data out of the registers is placed
on the MA Data Bus via drivers XE4, XES, and XFS. These drivers are also enabled
when the CPU can transfer data in either direction. Note that the two most significant bits located into XDS contain CPU cycle-type information.
GATE,
'Other contro~ signals generated on the processor card are RESYNC, READ
CPU R/W and -IC CLK.
"flO,
(pin 3).
RESYNC, at X06-12, is the SYNC pulse rec10cked with ~2 in flip-flop XA3
It is required because SYNC is delayed up to 700 nsec in the CPU after ~2.
READ GATE, at XES-S, is the second half of T2 or WAIT AND-gated with
READ CLOCK.
I/O (input/output) results from a decoding in XF6 of the CPU cycle-type
information contained on the D6 and D7 outputs of the CPU during T2. CPU R/W (CPU
read, not write) is the AND-gated combination of T3 SYNC and a decoding of PC6 and
PC7 at XCS-9. XCS-9 is low when the CPU writes data into memory. Thus, the CPU
writes data into or reads data out of memory when CPU R/W is low and high, respectively.
IC CLK is derived by NAND-gating the SYNC output from the CPU with
,This supplies a 33S nsec pulse at 374.4 kHz.
~2.
Q2 and its associated circuitry reduces the -12 V dc supply to -9 V dc,
the voltage needed for the CPU. A reference voltage of 9 V for regulator Q2 is
developed across R22 and CR9; thus Q2, operating as an emitter follower, maintains
the output level at 9 volts.
4-42
SECTION 4
TIiEORY OF OPERATION
...
J
--.
RESVNC
IC CLOCK
..
1.33 "sec
11
I
I
21
r
12
1
I
I
11
I
I
I
12
r;l
22
J
11
I
-I
T2
11
J
,
J
22
12
T
21
1" ,
r.
1
21
j1
....,j
T1
,
J
h
22
12
J
I
I']
J
I
I
I
1
I
I
-
..
-
I
WAIT
,
, ..
I
I
"
. ,\' 1;\ .~\yi,i:'ii·,
,
,
j
J
T3
DATA IN ROW
..
-
CPU R/W
(WRITE
COMMAND)
I
"
.
I
,
1/0 (If I/O
INSTRUCTION)
,
~
~
I'
0,
Tl'SYNC
.
WAIT'SYNC
I
READ GATE
J
I
~
I
CPU BUSY
I.:
ADDRESS IN
' I
-
-
DATA OUT
i\
I
,
\
1
I
I
4-43'
Figure 4-13.
Processor card (CPU) tlndng dlagram.
THEORY OF OPERATION
4.4.5
SECTION 4
PROM Card
The PROM card serves as the program memory for the 8025 CRT Terminal.
Memory chips on this card contain all instructions needed by the CPU,to control
terminal operations.
Block Diagram Analysis. As shown by the simplified block diagram in
Figure 4-14, the PROM card has three major sections: an address sector gate, a
chip selector, and a memory that consists of sixteen 256-byte PROM chips. Full
addressing of the card is done on MAO-IS, with the state ~f MA14 and 15 always
held constant.
MA12-15
ito
Ii!!A8-11
..
..
.
ADDRESS
SECTOR
GATE
CHIP
SELECTOR
..
PROM
MEMORY
CHIPS
1161
A DATA BUS
t
MAO-7
Figure 4-14. Buffered PROM card block diagram.
The address sector gate defines the range of addresses to which the card
can respond. For addresses outside the range, the sector gate disables all the PROM
chips by inhibiting one of two enable inputs required by each chip. For addresses
within the defined range, MA12-IS will satisfy the gate, and it partially enables
all of the chips.
Assuming the sector gate is satisfied, the chip selector supplies the
second enable input to the PROM chips specified on MAS-II. This second enable input, plus addressing on MAO-7, defines the mem~ry location of the data to be read
out on the A Data Bus.
Circuit Description.
Refer to Schematic diagram 96-434-XX
in Section 8.
The maximum capacity of the PROM card is 4,096 bytes (32 chips) of memory.
If fewer than 4,096 bytes are needed for a particular version of the terminal, the
unused chips are eliminated. For example, if only 2,048 bytes are used, rows A and
C of chips are eliminated.
Four inverters (XFS pins,2, 8, 10 and 12), header XF6 and NAND gate XE6-8
The four most significant address bits
(MA12-IS) are wired on the header to define the address sector for the card. For
the card shown, jumpers E2-E1S, F.4-E13, ES-E12 and E7-E10 are in place to define
address sector
(addresses 08 to 3777 8),
form the address sector gate circuit.
°
The six highest bits of address are transferred during CPU state T2. Addresses are changing during T1 and T2, but are stable throughout T3. ~~I4 and 15
are hard"wired at a high level for this system.
4-45
THEORY OF OPERATION
SECfION 4
For any address between Os and 3777 S' MA12 and 13 are low. Inversion
through XF6 places high inputs on pins 11 and 12 of gate XE6. MA14 and 15 are
also high at the input to XE6-S with 170 also high, XE6-8 applies a low partial enable input to C52 (pin 14) of each PROM chip. Any change in the inputs to the address sector gate will cause the output of XE6-8 to go high to inhibit all chips.
Inputs MAS-II select the PROM chips to be addressed. These inputs are
converted in two BCD-to-decimal decoders (XE4 and XES), and each output of the
decoder is applied to the
inputs (pin 13) of two PROM chips (e.g., the output
at XES-l is applied to PROM chips XBI and XDl). A low input at
selects the two
chips for reading. The lower four and higher four data bits are stored in the XB
and XD series PROM chips, respectively.
as
as
Eight bits of address (MAO-7) plus a low input at both
the data stored in the two chips to be read onto the A Data Bus.
as and
C5 2 allow
Table 4-3 gives PROM chip location as a function of memory address.
Table 4-3.
PROM chip location VB. memory address.
PROM CHIP COORDINATES
MOST
SIGNIFICANT
BITS
.
MEMORY ADDRESS
LEAST
SIGNIFICANT
BITS
(in octal)
XD1
XB1
00000 - 00377
XD2
XB2
00400 - 00777
XD3
XB3
01000 - 01377
XD4
XB4
01400 - 01777
XDS
XBS
02000 - 02377
XD6
XB6
02400 - 02777
XD7
XB7
03000 - 03377
XDB
XBB
03400 - 03777
XCI
XE1
04000 - 04377
XC2
XE2
04400 - 04777
4-46
THEORY OF OPERATION
4.4.6
SECTION 4
Buffered RAM (Refresh) Memory Card
Block Diagram Analysis. A simplified block diagram of the RAM (refresh)
memory card is shown in Figure 4-15.
ADDRESS
SECTOR
MAl2-1S.,
GATE
RfFAODRS
I
~I
"' ~ lihil r----l
MAlO-ll
RDDATA"I
MAO-9
~
RAM
CPURIW ~
faH) IPS
I
OUTPUT
t------~~'__ _G_AT_E_......
A DATA BUS .....
......
'---_
Figure 4-15.
Buffered RAM memory card block diagram.
As with the program memory, the address sector gate defines the range of
addresses to which the card responds. Data can be read into the memory from the
RD Data lines when a CPU read signal is applied to the RAM chips. Data is read out
of the memory through the output gate on the A Data Bus. The chip selector controls
the output gate and selects the memory chips to be addressed.
Circuit Description. Refer to Schematic diagram 96-433-XX
and to Figure 4-17 for signal timing.
in Section 8,
Maxi~um capacity of the RAM card is 4,096 bytes (32 chips) of memory.
Since only 2,048 .bytes (16 chips) are used in the standard 8025 CRT terminal, the
XA and XB chips are eliminatea.
Four inverters (XF5 pins 2, S, 10 and 12) header XF6, and NAND gate XE6-8
fonn the address sector gate. The four most significant address bits (~fA12-15) are
wired on the header to define the address sector for the card. For the card shown,
jumpers EI-EI6, E3-E14, E5-E12, and E7-EIO are 1n place to define address sector 3
(addresses 34000 8 to 37777 8),
For any address between 34000 S and 37777 8 , MAl2 and MAl3 are high. MAl4
and MA15 are hard-wired at a high level for this system. Thus, NAND gate XE6-S is
enabled when T70 is high and applies a low input to XE5-12. Because this card is
used as the refresh memory, the A-B jumper is in place, and consequently, the input to XES-12 also serves as REF ADDR.
The inputs to XES (MAIO, ~1All, 170, and REF ADDR) define the memory chips
to be addressed. ~~lO and MAll in the combinations high-low and high-high enable
the XC and XD chips, respectively, assuming that T70 is high and XES-12 is low.
Nine bits of address, plus a low level at pin 13 of each RAM chip in a
given row, allow data from the RD Data Channel to be entered into the memory when
CPU R/Wat pin 65 is low. If CPU R/W is high, data is read out of the memory through
the output gate to the A Data Bus. The output gates are enabled by the output of
the XE6-6 NOR gate when the memory chips are enabled.
4-47
THEORY OF OPERATION
SECTION 4
Table 4-4.
RAM chip location vs. memory address.
RAM CHIP COORDINATES
MEMORY ADDRESS
(in octal)
BIT POSITIONS
27
26
25
24
23
22
21
2°
C8
08
C7
07
C6
06
CS
05
C4
04
C3
03
C2
02
C1
01
4.4.7
34000 - 35777
36000 - 37777
Refresh Buffer Card
The refresh buffer card provides refresh data for the video display, temporarily stores video status and keyboard indicator light (LED) data, and decodes
a beep signal.
Block Diagram Analysis.
in Figure 4-16.
A simplified block diagram of the card is shown
Video status data is stored at address 377718 in the refresh memory. When
called from memory, at the end of each page, the data_is placed on RMO-3 in order
to update the video status latch. The BLANK and CSO-3 outputs control block and
underline cursor, video on-off, and control character blanking.
RMO·7
LED
LATCH
rrN
RMO 3
-
, '1
I
LOADLSB
BUFFER
~to
1-1 1-1
o +.I
I-I..-l
Q) 0
011-1
1-111-1
+.I ::l
I::: III
0
U .c
1-1
+.I El I:::
s:::: Q) 0
0 ::;: U
U
~
El
1-1
.>t ..-l>to
~~
1-1 0
.c
f1l
.-i
U
0' ::;:
ofJ) 1-10
'0 +.I
a.
\.I .~ 1-1 \.I fJ)
.cfJ) {/) p..
fJ) 0'
Q) Q) .~
N III )
~
0 o (1J s:::: Q) QI (1J~ M 0 Ul '0 .~ 0
fJ)
QI \.I .~
N .0
0 f1l
~ U
~
1-1'0 ~ S
0 ::;:
>t >tuI::: QJ
:::I .~ QJ .~ (1J OJ \.I
~
U:> ~ ~ ~ ~ p.. ~ ~ ~ ~ r.l ~ U
SYMPTOM
~
~
~
,
~
A U D I B L E
1-1
~
+.I
8: .-If1l
:::l ::l
Ul
(1J
Q)
~
.c
u
B
f1l
+.I
.~
..-l
~
::l
0'
Ul
O'Q)
\.I ~
:>
(1J
r...
r...
0
fJ)
........
~
:>
N
p.. U"l .-I
Ul
:::I
r...
:z:
OJ
..-l
OJ
OJ
..-l ..-l
~{l
+.IU {l {l
f1l
U
I::: 1-1
.~
S
\.I
OJ
U
(1J
+.I
• I:::
~
:::l
.~
~
1<1; p..
N
0
0
ElM
:::I
.~
0 Ul
,
N
M
QlN N
"-1'0 '0
I
{/)
QJ
0 Eo< U :> ::;:
~
~
S Y M P TOM S
,
II
Beep response inoperative
X
X
X
Continuous beep
X
X
X
Beep response, all keys
X
X
Beep and click responses inoperative
X
Click response inoperative
X
Continuous click after terminal
power is applied*
X
X
X
X
X
X
X
XX
X
Rapid click response
X
Varying click/repeat rate
X
X
X
Continuous click with character
repeat after terminal power
is applied
X
X
Cooling fans inaudible
------------------------------------ - *
-- _._------- ---
-- ._--
-~--
-- -- -- ----
To locate bad key switch, individually depress each key for more than one- ha If
second. Bad key will be inactive after this period.
6-7
-'--
-
MAINTENANCE AND REPAIR
SECTION 6
Table 6-1 (continued)
MALFUNCTION PROBABLY IN
.
~
~.-!
.-!
SYMPTOM
0 .-! (IJ 0 ~ ~
~ 0 44 ~ 0 +J
+J ~ IH +J
s::
s:: +J ::s s:: ID 0
0 s:: ttl 0 ;:!!; U
U 0
U
~
0
III
~
::s
u ..c
0- til til
....
s::
(IJ
(IJ
14 .... 14
....
......
~
~
o
~
E
~
E-<
~
(IJ
(IJ~
M
~
U
N
0..
~
~
~
·M
rU )
~
Q)
~
Q)
>.
~ ~
u
s::
~
Q)
~
bl
U
~
~
~ :>
0
0..
LI)
U
N
(IJ
+J
·M
~
r..
r..
til
t::
·M
.-!
~
)
0
Ul +J U
:>
M
+J
Ul
..c
0
>. o +J
>.M +J til
til 0- rUM
.-!
M ::s
::s 00Ul
III
0- (IJ
M
~
0 Ul 'tl ..l<: 0
0 rU
.g,
~
g.
~
III ~
til 0.. N
Q)
~
~
'tl
14 0
..c
0- ;:!!;
U
0
'tl +J
'tl 44 S 44 44 0 ;:!!; I
(IJ
(IJ 14
Ul
u :>
CURSOR
..c ..c
III
0
(IJ
0
M
>. 0
Q)
0
S
til, ~
::s
r..
Z
0
(IJ
~
(IJ
~ ~
U U
otil
0
::s
·M 0
Q)
~'tl
X
X X X
X X
No block cursor in protect mode
Non-blinking cursor
X X
Cursor at home; no keyboard response
X
X
cursoridisplayed character out
of sync
-
X
X
Cursor movement abnormally
limited
X
X
X
X
X
Cursor moves down two or more
lines when CR key is struck
X
X X
C H A R ACT E R S Y M P TOM S
Constant character jitter
X X X X
Character jitter, every key
stroke
X
Character flicker
X X
Deformed character(s)
X
X
X
X
6-8
E
(IJ
'tl
E-< U :> ;:!!;
SYMPTOMS
No cursor, characters displayed
(IJ
.-! M
X
~
~
Q)
+J
• s::
·M
::s ~
~
~
N
,
0..
~
N
M
M
N
N
I
Ul Ul
~
~
MAINTENANCE AND REPAIR
SECTION 6
Table 6-1 (continued)
MALFUNCTION PROBABLY IN
.
~
..-I
0..-1
~ 0
+l
~
s:: +l
0 s::
u 0
SYMPTOM
~
o
1/1
~
.
..c=
0
Q)
~
Miss~ng
1/1
Q)
'0 ~
OM CD
0::
SYMPTOMS
No upper or lower case characters
0
>~
l1s::
u
s::
OM
o~
~
0
Q.I
~
~
~
ffi
s::
~ '0
~
u ~ g~
+l
ii
0
~
.c ..c=
0>1/1
1/1
Q.I
~ ~
~ ~
1/1 ~
1/1 p.. N
Q)~
U
0
~
&&p..
'0 +l
~ M
~
.....
0.
~
~ 1/1
Q) Q) oM
'0 ..!<: 0
~
lIS
I >- >- 8 Q)
~
0.
~ ~ ~ tj U) u
I"l
g
N
lIS
0
.0
>-
~
0. lIS
g. ::s
..-I
~
~
p..
0
..c=
..-I
OM
0 +l
lIS
..-I +l
U)
+l
~
0>
::s
t.n
~
0>
Q)
&:>0::
:>
U
+l
I:z.t
Q)
1/1
..... I:z.t::s
N
U)
0
+l
lIS
s::
..-I
Q)
~ ~U UlIS ~ p..
~
.Q
~
OM 0
~
N
~ ~e8 :> ::.: ~
~
0
Q)
ffi
"CI '0
OM 0
N
I"l I"l
N
I
N
I
U)
0::
X
X
X
X
X
Display filled with one character
XX
X
X
o T HER DISPLAY S Y M P TOM S
No raster
X
X
X XX
X
Intermittent raster
X
X
X XX
X
Raster flicker
X
X
X X X
X
X
X X
Small raster/blooming/dim/video
loss of sync
X X
Radical blooming
Lightning-like flashes on display
screen
• s::
>< OM
X
Displayed character alternates
between correct and incorrect
character
Raster wiggle/drift
Q)
..-I ..-I
1/1
0
~
Q)
+l
Q)
~
~
(continued)
X X
character set
Character is displayed simUltaneously on two or more lines' .
..-I
g 0 ::.:~
~
~
U
8 :>
CHARACTER
~
Q)
0
..-I
Open Brightness Control
X
6-9
X
MAl NTENANCE AND REPAI R
SECTION 6
Table 6-1 (continued)
MALFUNCTION PROBABLY IN
.
~
M
M
0
M
Ql
~
Oll-l
t:
~
~
0
SYMPTOM
H M
u
~
0
~
~
~
~
OJ
0
:<: u
.c00
.c00 .c00
0
u
0
Ql
00
Ql
~
t1>
H t1> ~
-M
&&
o
THE R
DISPLAY
S Y M P TOM S
Blank display; raster present
X X X X X
Repetitive garbled data displayed
r
I
~
III :J Ql
0 til 'tl
0
.0
g~ ~>< ~><
u
t:
J:ll
fJ:
~
~
OJ
M
H
0
~
III
t:
-,-t
~
OJ
Eo<
~
U
~
Ql
~
• t:
OJ
M
OJ
M
~ ~
U U
X -,-t
::1 H
oet:
e
N
M
N
M
N
o
0
8
:> :<: ~
~
N
00 OJ
H 'tl 'tl I
-M 0
I
Ul
0::
(continued)
X
X
X
X
X
X
·X
X X
Display pages flip once or
repeatedly
X
S Y M P TOM S
No keyboard response
Incorrect keyboard response
Keyboard locked out
M
N
U
~
~ .,-t
X
X
Blink functions inoperative
KEY BOA R D
~
'tl
U
X
X
Only one line (usually short)
displayed
-
Field modification functions
occur without command
~
til
.c
III
~
-,-t
III III III M
M
::1
:J
til
::1 t1>
III
~ 00 til t1> OJ
Ql -,-t
OJ 0::
r...
..:.: 0 ~ 0::
r...
III
OJ
:> OJ 0
OJ
:>
00"N
~
::1 :z
U III til M r... 0
M
X
X X X
All field modification functions
inoperative
0
.c
~
0
~
Defective Brightness Control
Brightness control ineffective
Garbled data display
'tl
0
00 H
00 III N
t: Ql OJ Ql
~
U
~ 'tl II-l E II-l ~ 0
H
::1 -M OJ -M
III
u :> 0:: Eo<
0
:>.. 0
:>....-i ~
Ql
~
o
H
E
j
E t:
HII-l
::1 t:
t: Ol 0
U
......
0
H
0
o~ H
X X
X
X
X X X X
X
X
X X X
X X
6-10
XX X X
X
X
X
XX
MAINTENANCE AND REPAIR
SECTION 6
Table 6-1 (continued)
MALFUNCTION PROBABLY IN
.-l
M .-l >- 0
.-..
0 .-l Q) 0 M M
M Oll-l M 0 4.J
~
4.J M II-l 4.J
c::
M
c:: +'
c:: ffi 0
0 c:: ~ 0 :<: u M 00 0
u
u 0
U .c:
.c: .c: !II M
!II tJI !II III III p..
M
0 0 Q) c:: Q) Q) Q) ......
.-l
SYMPTOM
.... M M
.... ~ ....Eo!e II-l~ II-l~
M
101 '0 II-l
III
Q)
8 :>
KEYBOARD
S Y
~
0
M ~
p.. IX:
ffi
"Cl
0
E "Cl
N
M
N
I
.-l
4.J
M .... M
Q)
1\1
0.
c::
~
....
M !II
.8>- ~>- "Cl0u ~
~ ~ ~
X
Q)
0.
I/)
a
~
u
.c:
+' III
....4.J
0 4.J
~ :::10- g,
I/)
Q)
Q)
M IX:
~
:J
.-l
:>
IX:
:>
N
p.. an ..-t
Ii.
Q)
!II
:::1
r..
• c::
Q)
.-l
Q)
Q)
~~
.-l .-l
.Q .Q
1\1
U U
~
....c::
~
"- ~
6
M
Q)
4.J
U
1\1 .-l
I/)
I/)
eC
:::1 M
0« p..
-N
M
N
N
M
N
I
I
u :> :<: ~ ~
:::1
X
X
X
Repeat function inoperative
>.-l
>1\1
.c:u
4.J
M
M 0
(continued)
P TOM S
Keyboard mode (case/control) incorrect
U
.-..
---0. ,...,
X
X
X
X
Single key inoperative
Multiple character display per
stroke
X
X
r
Multiple character display, ail
or group of keys
X
Two different characters displayed per stroke
X
Wrong character consistently
displayed per stroke
C LEA R
FUN C T ION
X
X
S Y M P TOM S
X
Incomplete clear
Power on clear (POC) function
inoperative
Display filled with one character
after terminal clears
X
X
X
XX
X
X
6-11
X
XX
SECTION 6
MAINTENANCE AND REPAIR
Table 6-1 (continued)
MALFUNCTION PROBABLY IN
.
~
..-l
..-l
I-l..-l :>"0
O..-l Q) 0 I-l I-l
I-l 0 11-1 I-l 0+1
+I I-lII-I +I
s::
s:: +I :l s::
8l
•.-!
Eo!
8l
I-l
I-l 0
:>., 0 +I
:>.,..-l +I til
..-l
til 0..
..-l 0..
:l
00.. :l
~
i
w
'0
I-l 0
..c
U
I-l 0- ~
0 0
'0 +I
!II I-l
I-l •.-! I-l I-l !II
Ql Ql •.-!
til
!II Po. N
M
Ql
'0 ~ 0
N
U
0 III
0 ~ I :>., :>., U Q)
Ql I-l
s:: 0..
~ III U
0:: 0..
~
.8
~
~ &!
0
+I
~
:2 :2
t:
..c
U
+I
6,
Ql
I-l ~
Ql
~
:>
8l
:>
Ql
!II
N
0
:l
0.. ~ ..-l ~
~
I-l
(I)
+I
• •.-!s::
~
~
N
I
lQ
I
III
~
SYMPTOMS
Transmits garbled data
X
XXX
Receives garbled data
X
X XX
Receives garbled data when terminal should not be receiving
X
XX
X
XX X
No I/O with communications system
X
MIS C ELL A N E 0 U S
S Y M TOM S
X)
Intermittent, correct operation
Intermittent, incorrect operation
X~ ~ ~ ~ ~ ~ ~ ~ X X
Intermittent communications
X
X
X
XX
XX X
X
XX
Smoke/arcing/burning odor
X
Cannot turn terminal on
XX
X
Cannot turn terminal off
Terminal locked up
X
No I/O function
Escape functions inoperative
XX
XX
X
6-12
XXX
XX
X
XXX
MAINTENANCE AND REPAIR
SECTION 6
Table 6-1 (continued)
MALFUNCTION PROBABLY IN
~
o~
+l
..-I
..-I
)..l..-l
0..-1 , 0
)..l
ffi
u
SYMPTOM
~
otil
0
U
.c:
0
Q)
til
u
e ~
c
.c: .c:
", '0
~
0
til
Q)
~
0..-i
~
~
u :>
8!
Eo<
ex:
& Il<
0...-1 :1
°04
~
0
~
U
~
~
...,
N
N
g~
I
:>,0 +l
:>, ..-I +l II!
III 0.'" ..-I
.c:U
'0 +'
~ °rot
III
~
° ..-I
~
Ql
0. :1 :1
~ til (/)
Ql 004
'0 ~ 0
0 III
:>, :>, U Q)
c:: 0.
~ ~ ~ (/) U
.8
~
~
cv
~
0
t1>
Ql
ex:
:>
U
+'
t1>
(/)
Q)
ex:
:>
N
Il< LO ..-I
QJ
~
0
+l
III
4-1 c::
4-1 °04
Q)
0
)..l
::;:
ex: ex:
(continued)
XX
No composite video at video
jack (J15)
6.2.5
.c:
(/)
X XXX
Program malfunction
Terminal inoperp.tive; raster
present
t1>
~
S Y M P TOM S
Escape functions operate incorrectly
~
t1> til til til Il<
C Ql Q) Q)
~ '0 4-1 e 4-1 4-1 0
004 Cl)
~
:1 004
M I S C ELL A N E 0 U S
0
)..l
~
0 +l
C +l :1 c::
0
o c:: III 0 ::;: U
~
~
X
XX
-
X
X
Removal and Replacement Procedures
Cabinet Removal and Replacement. To take the top section of the cabinet
off, remove the five screws (three on the front, two on the back) shown in
Figure 6-1 and 6-2. Lift the cabinet straight up.
To replace the top section of the cabinet, lower it straight down over
the internal assembly. Replace the five screws shown in Figure 6-1 and 6-2.
Circuit Card Removal and Replacement. The 8025 CRT Terminal contains
removable circuit cards housed in a card cage with a capacity of 18 cards. The
card slots are numbered REG, 1, 2, 3, 4, 5, 6, 7, 8, ~-------9, from left to right.
Each card is equipped with an ejector tab to help removal. The tabs are marked
with the slot location. The card cage, with no cards installed, is shown in
Figure 6- 3.
6-1 :;
MAINTENANCE AND REPAIR
SECTION 6
Figure 6-1.
Cabinet mounting screws (front).
Figure 6-2.
Cabinet mounting screws (rear).
6-14
MAINTENANCE AND REPAIR
SECTION 6
Figure 6-3.
CAtITION
# 1:
CAtrrION #2:
Card cage.
NEVER REMOVE OR REPLACE A CIRCUIT CARD
WHEN THE TERMINAL IS TURNED ON.
MOS ELEMENTS ARE EASILY DAMAGED BY STATIC
DISCHARGE. ALWAYS HANDLE CARDS SO THAT NO
DISCHARGE FLOWS THROUGH THE CARD.
BEFORE TOUCHING A CARD, PLACE ONE HAND ON
THE SURFACE CONTACTING THE CARD. USE THE
OTHER HAND FOR THE CARD.
NOTE:
To unplug ribbon cables, use only an IC puller,
or use a small screwdriver to lever the plug
out from both ends. NEVER PULL ON THE CABLE
OR THE LID OF THE PLUG.
When picking up a card, first place one hand against the surface on which
the card rests. Then pick the card up with your other hand.
To put a card down, first place the hand not holding the card against the
surface on which you want to place the card. This precaution discharges body static,
so that you can safely lay the card down.
To remove a card from the card cage, proceed as follows:
1.
Place one hand on the CRT face and the mounting band or the terminal
chassis.
2.
Grasp the pull tab on the 'card with the other hand.
3.
Pull the card partially out of the slot.
4.
Disconnect the card connector(s).
6-15
MAINTENANCE AND REPAIR
5.
SECTION 6
After the card is completely clear of the terminal, remove your other
hand from the equipment.
To replace a card in the card cage, proceed as follows:
1.
Hold the card in one hand.
2.
Place your other hand on the CRT face and the mounting band or the terminal chassis.
3.
Insert the card partially into the correct slot.
4.
Plug in the connector(s).
5.
Push the card in until it is properly seated.
NOTE:
6.
The DIP plug is numbered on the lid. Make sure
it is oriented the same way as the socket into
which it is being inserted.
After the card is seated and the connector(s) plugged in, remove the
hand holding the CRT face or the terminal chassis.
Keyboard Removal and Replacement. Removal of the keyboard from the terminal
is done this way:
1.
Remove the top section of the cabinet as described earlier.
~.
From underneath, remove the four keyboard mounting screws shown in
Figure 6-4~
NOTE:
Do not remove the angle brackets attached to the
keyboard.
3.
Undo the cable clamps.
4.
Remove the two connectors on the left-hand side of the machine and unplug the ribbon cable from the Refresh Buffer Card in slot #3.
S.
Lift the keyboard straight up.
Figure 6-4.
Keyboard mounting screw locations.
6-16
AND REPAIR
To replace the keyboard, proceed as follows:
~tAINTENANCE
SECTION 6
1.
Place the keyboard in position and plug in the connectors.
2.
Replace the four keyboard-mounting screws shown in Figure 6-3. Drive
the screws only far enough to hold the keyboard loosely in place.
3.
Lower the top section of the cabinet into place and align the keyboard
within the opening in the cabinet.
4.
Carefully remove the top section of the cabinet so that you do not move
the keyboard.
5.
Tighten the four keyboard-mounting screws, again taking care not to move
the keyboard.
6.
Replace the top section of the cabinet as described earlier.
Key Cap/Switch Removal and Replacement.
as follows:
To remove a key switch, proceed
1.
Remove the key cap by pulling straight up with a key cap removal tool.
2.
Remove the keyboard as described earlier.
3.
Locate the two leads of the defective switch on the back of the circuit
card.
4.
Unsolder both switch leads, sucking all solder from the mounting holes.
5.
Lift the"switch straight up, if possible.
6.
If the lead solder connection is too strong, try wiggling each of the
leads with needle-nose pliers to break the connection. Then lift the
switch straight up.
7.
If the switch still is not free after Step 6, reheat each lead alternately while wiggling the switch until it is free.
Replace a key switch as follows:
1.
Clear excess solder from the mounting holes in the circuit board.
2.
Insert new switch leads to the appropriate depth and solder them into
place.
NOTE:
Switch leads are mechanically configured to pre\'ent incorrect installation.
6-1:-
t-1AINTENANCE AND REPAI R
SECfrON 6
3.
Replace the keyboard as described earlier.
4.
Push the key cap down onto the key switch.
Keyboard Encoder Removal and Replacement. The keyboard encoder (an integrated circuit) is located on the keyboard printed circuit card (see Figure 6-3). It
is installed in an integrated circuit socket. The caution concerning static discharg
given for circuit cards applies to removing or replacing the encoder.
Fuse Removal and Replacement. The terminal is protected by two fuses hous~
ed on the back panel, a 3/4 amp (F20l) and a 2 amp (F202). To remove them, disconnect the power cord, turn the post cap counterclockwise, and pull straight out.
Remove the old fuse from the cap. To install a fuse, insert it in the post cap,
push it into the post, and turn it clockwise to lock it in place.
Monitor Deflection Board Removal and Replacement. The Monitor Deflection
Board is located above the neck of the CRT. To remove the board, disconnect EIOI
through EI04 and PI02 through Pl12, excluding PI09, (see Figure 6-5). Then remove
four screws indicated in Figure 6-5 and lift the board off the chassis.
To install the board, position it on the chassis to aligh the mounting holes.
Replace the four mounting screws and reconnect all interconnects. Refer to the terminal wiring diagram in Section 8 if in doubt about correct interconnection.
Figure 6-5. Monitor Deflection Board i.nterconnections and
mounting screws.
6-18
MAINTENANCE AND REPAIR
6.3
SECI'ION 6
BENCH MAINTENANCE
This paragraph tells how to isolate malfunctions in the 8025 CRT Terminal
to component level. Included are general and specific troubleshooting procedures.
Information also includes removal and replacement procedures normally used in bench
maintenance.
NOTE:
6.3.1
Only qualified electronics technicians should perform bench
maintenance of the terminal.
Objective
Bench maintenance is intended to make the terminal operational by correcting malfunctions that cannot be fixed in the field with the procedures in Paragraph
6.2 This objective is best met by isolating the problem to a component on a circuit
card or assembly and replacing it with a good component. A secondary objective is
safety. Thus, CRT removal and replacement are recommended bench service procedures.
,6.3.2
Requi red Equipment and Materials
NOTE:
Equivalent substitutes may be used.
Oscilloscope, Tektronix 465
~1ul timeter,
Triplet t 310
Digital voltmeter, Fluke BOOOA
·Logic probe, Hewlett-Packard 10525T
ErA i.nterface monitor. International Data
~Iodel
60
Extender cards. 2 ea .• m1RON 99- 381-01
"Dip Clip". Pomona Electronics 3916
•
Illuminated magnifier
Handtools
~1iniature
sO'ldering iron, controlled heat, 47 watts maximum
Solder removal kit. "Wickit"
Industrial alcohol
8025 CRT Terminal service manual
6-19
SECJ'ION 6
MAINTENANCE AND REP AI R
6.3.3
Rules of Good Maintenance
Observing the following general rules of good maintenance will help minimize down time, prolong terminal life, and reduce the chances of personal injury.
•
Use procedures, aids, and technical information in
this manual to locate and repair malfunctions
•
Check the "obvious" (e. g., disconnected power cord) before investigating more difficult-to-locate causes of
malfunction.
•
When a tlial-and-error replacement approach must be
used, start with the easiest-to-verify alternative.
•
Do not remove or replace fuses with power cord connected.
Do not remove or replace circuit cards when terminal
power is on.
•
Consider temperature possibilities when investigating
an intermittent problem.
•
Transistor failure is often caused by failure of another
component. Investigate this possibility before replacing a transistor.
•
Keep terminal clean, inside and out.
Solder qulckly and use heat shunts to prevent heat
. damage.
•
6.3.4
Avoid excessive card extraction and insertion.
Replaceable Parts
Replaceable parts are listed in Section 9.
NOTE:
6.3.5
Use OMRON or OMRON-approved parts only. The use of
other parts can void the manufacturer's warranty.
Workmanship
Bench maintenance recommendations and procedures presume high workmanship standards. Any damage caused by the use of improper tools, carelessness, mistreatment, or substandard workmanship voids the manufacturer's warranty, as will
using component leads for studs and making unauthorized modifications.
6-20
SECTION 6
MAINTENANCE AND REPAIR
6.3.6
General Troubleshooting Procedure
A general procedure for locating a faulty component follows:
1.
Evaluate all complaints and symptoms together, rather than individually.
2.
Determine the section, or sections, in the terminal that are
operating incorrectly. The terminal contains the following
sections:
Cursor Control Card (S lot 1)
Video Control Card (Slot 2)
Refresh Buffer Card (Slot 3)
Timing Control Card (Slot 4)
Refresh Memory Card (Slot 5)
Refresh Control Card (Slot 6)
Processor Card (Slot 7)
Program Memory Card (Slot 8)
RS232 Interface Card Modem (Slot 9)
RS232 Interface.Card, Storage (Slot 10)
RS232 . Interface Card, Printer (Slot 11)
Terminator Card (Slot 12)
Regulator Card (Slot REG)
LED Assembly
Keyboard Assembly
Power Supply Assembly
CRT Monitor Assembly
Such determinations can usually bE' made by visual inspection,
ohserving the display, and listening to the sounds of the
terminal. Also use Tahle 6-1 to assist you in isolating a
faulty section.
6- 21
MAINTENANCE AND REPAIR
SECfION 6
3.
Determine the defective circuit or subsection of the faulty
section. (NOTE: all sections in the terminal can be broken
down into subsections and circuits. Refer to block diagrams in
Section 4.) Visually inspect the section and check operating
events, voltages, logic levelS, waveforms, and resistances.
Look for discrepancies between measurements and the data supplied in this section and Sections 4 and 8. Troubleshooting
procedures for each section in the terminal are detailed later
in Paragraph 6.3.7.
4.
After narrowing the problem down to a circuit or subsection,
determine the defective component or components. The defect
can be found through visual inspection; measurement of voltage,
logic level, and resistance; waveform analysis; or replacement
of the suspected component or components. Also, many of the
section troubleshooting procedures detailed later in Paragraph
6.3.7 relate malfunctions to possible component failures.
Visual Inspection. Visually inspect the terminal and suspect sections
before starting a dynamic procedure to isolate a problem. Look for loose or
broken connections, damaged cards or components, and so forth. Examine printed
circuit boards under an illuminated magnifier and check for imperfections, excessive heating, cracked conductive paths, solder bridges, broken leads, and
other abnormal conditions. Visible troubles usually have an obvious remedy.
Dynamic Testing. Procedures for isolating problems to the component
level in each section of the terminal are given in Paragraph 6.3.7. In many cases,
malfunctions are related to possible component failure. These procedures should
always be used with trye information supplied in Sections 4 and 8. If the problem
still exists after you~xhaust the applicable procedure, contact OMRON Field
Service for assistance.
6.3.7
Specific Troubleshooting Procedures
Most circuit cards and subassemblies in the 8025 CRT Terminal are repairable on a component level. Such maintenance, however, is recommended only for
"emergency" repairs. OMRON does not consider this type of service to be equal to
maintenance performed in its own service fad Ii ty.
OMRON service includes complete automatic diagnostic testing that cannot easily be duplicated in the field. Repairs are made with preconditioned components, and the workmanship is subject to stringent quality control monitoring.
Also, repaired cards and subassemblies are environmentally seasoned and undergo
full system testing.
CAtrrION 1:
WHEN HIGH CURRENT DRAIN IS INDICATED (BLOWN FUSE,
CIRCUIT BOARD DISCOLORATION, HEAT DAMAGED HARNESS
WIRES, BURNT OR DISCOLORED COMPONENTS, UNUSUAL
ODORS, OR A DRASTIC DROP IN POWER SUPPLY VOLTAGE),
DO NOT TROUBLESHOOT WITH THE POWER ON. FIND AND
CORRECT THE CAUSE BEFORE DYNAMIC TESTING.
6-22
MAINTENANCE AND REPAIR
CAUTION 2: BEFORE INSERTING A CARD IN THE CARD CAGE, CHECK
FOR ZERO (0) OHMS BETWEEN PINS 79 and 80 OF EDGE
CONNECfOR, ZERO (0) OHMS BETWEEN PINS I AND 2,
AND 50 OHMS (LOWEST METER RANGE) BETWEEN PINS 1
AND 80. TO AVOID DAMAGING OTHER CARDS IN THE
TERMINAL, DO NOT INSERT ANY CARD NOT MEETING
THESE REQUlRE~mNTS.
NOTE 1:
Waveforms supplied in this paragraph a~e consecutively
numbered. These numbers appear on the waveform photos
and in the photo captions. Correspondingly numbered
call outs on the applicable schematic indicate where
the waveform can be observed. Waveforms are referenced
to chassis ground.
NOTE 2:
Should the insertion of any circuit card lock out the
keyboard, return the card to Or-fRON for repair.
SECTION 6
MAINTENANCE AND REPAIR
SECTION 6
Video Control Card. Plug the card onto the extender card and insert
in the terminal. Connect the ribbon connector. Check for the following signals
in the order given.
WAVEFORM l:
BLANK
Oscilloscope Settings:
Vertical, 2 V/crn
Horizontal, 2 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT, CHECK:
XE6-6, Timing Control Card,
Refresh Buffer Card
WAVEFORM 2:
BLANK
Oscilloscope Settings:
Vertical, 2 V/cm
Horizontal, 10 usec/cm
Synchronization, internal
IF SIGNAL IS INCORREct..QR
ABSENT, CHECJ(.;
XE6-6, Timing Control Card,
Refresh Buffer Card
WAVEFORM 3:
Clock Timing
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 0.1 usec/em
Synchronization, internal
IF SIGNAL IS INCORRECT OR
ABSENT, CHECK:
XE4, XE2-8, Timing Control Card
6-24
MAINTENANCE AND REPAIR
WAVEFORM 4:
SECTION 6
MATm
Oscilloscope Settings:
Vertical, 2 V/cm
Horizontal, 0.5 usec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT "oR
ABSENT, CHE CK :
XD4-S, X05-11, XES-4, XD3-S,
XD2-10, Timing Control Card,
Cursor Control Card, Refresh
Buffer Card.
WAVEFORM 5:
Video
Oscilloscope Settings:
Vertical, I V/cm
Horizontal, 2 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECI' OR
ABSENT, mECK: .
CR3, XOl-6, XEI-6, XEl-B, XEl-1I,
XEI-3 and circuitry related to
these components.
WAVEFORM 6:
Video
Oscilloscope Settings:
. Vertical, I V/cm
Horizontal, 10 usec/cm
Synchroni zation, internal
IF SIGNAL IS INCORRECT OR
ABSENT, CHECK:
CR3, XOl~6, XEI-6, XEI-S, XEI-ll,
XEI-3 and circuitry related to
these components.
6-25
MAINTENANCE AND REPAIR
SECTION 6
WAVEFORM 7
(Not applicable to 8025G Terminal)
WAVEFORM 8
(Not applicable to 8025G Terminal)
WAVEFORM 9:
Parallel-to-serial
converter output
Oscilloscope Settings:
Vertical, 1 Vlcm
Horizontal, 2 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR
ABSENT I CHECK:
XA2, XA4, Refresh Buffer Card
6-26
MAINTENANCE AND REPAIR
WAVEFORM 10:
SECTION 6
Parallel-to-serial
converter output
Oscilloscope Settings:
Vertical. 1 V/cm
Horizontal. 0.1 usec/cm
Synchronization. internal
IF SIGNAL IS INCORRECf OR
ABSENT. CHECK:
XA2. XA4. Refresh Buffer Card
WAVEFORM 11:
Clock Timing
Oscilloscope Settings:
Vertical, I V/cm
Horizontal, 0.1 usec/cm
Synchronization. internal
tF SIGNAL IS tNEORRECf OR
ABSENT .. CHECK:
Timing Control Card .
WAVEFORM 12:
Clock Timing
Oscilloscope Settings:
Vertical. I V/cm
Horizontal. 0.2 msec/cm
Synchronization, internal
IP SIGNAL IS INCORRECf OR
ABSENT, CHECK:
Timing Control Card
6-27
[
MAINTENANCE AND REPAIR
WAVEFORM 13:
SECTION 6
HF CLK
Oscilloscope Settings:
Vertical, IV/em
Horizontal, 0.1 usec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR
ABSENT, CHECK:
Timing Control Card
WAVEFORM 14:
H8 Clocks
Oscilloscope Settings:
Vertical, 0.2 V/cm
Horizontal, 0.1 usee/em
Synchronization, internal
IF SIGNAL is INCORRECT O,R
ABSENT, CHECK:
XES-6, Timing Control Card
6-28
SECTION 6
MAINTENANCE AND REPAIR
Refresh Buffer Card. Plug the caTd onto the extender card and insert in
the terminal. Connect the ribbon connector. Check for the following signals in the
order given:
WAVEFORM 15:
Each CG bus line,
one-hal f page data
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 2 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
OIECK:
XEl-3, 6, 8, and 11; XDl-3, 6,
8 and 11.
WAVEFORM 16:
Each CG bus line,
one-half page data
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, O.S msec/cm
Synchroni zation, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
.
XEl-3, 6, 8, and 11; XDl-3, 6,
8 and 11.
WAVEFORM 17:
Refresh shift register
outputs, one-half page
data
Oscilloscope Settings:
Vertical, 2 V/cm
Horizontal, 0.1 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XE2, XD2, REG 2 Clock and load
circuitry .
6-29
MAINTENANCE AND REPAIR
WAVEFORM 18:
Next-line shift register outputs, onehalfpage data
Oscilloscope Settings:
Vertical, 2 V/cm
Horizontal, 0.1 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XE3, XD3, REG 1 clock circuitry
WAVEFORM 19:
Next-line shift register inputs, onehalf page data
Oscilloscope Settings:
Vertical 1 V/cm
Horizontal, 2 usec/em
Synchronization, internal
IF SIGNAL "IS INCORRECT OR ABSENT,
CHECK:
.
XE 4-1, 4, 10, 13 ; XD4 -1, 4, 10, 13;
XB6-2; XC4-3, 6, 8, 11; XB4-3, 6,8,·
11; XD6-12, Refresh Memory Card
WAVEFORM 20:
CPU BUSY
Oscilloscope Settings:
Vertical, 2 V/cm
Horizontal, 10 usec/cm
Synchronization, internal
IF SIGNAL IS INCORRECl' OR ABSENT,
CHECK:
XB6-8, Processor Card
SECTION 6
MAINTENANCE AND REPAIR
WAVEFORM 21:
SECTION 6
BLINK
Oscilloscope Settings:
Vertical, 2 V/cm
Horizontal, 50 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECI' OR ABSENT,
a-tECK:
XC6-6, XCS, XDS-l1, XDS-3,
Timing Control Card
WAVEFORM 22:
REG 1 CLK
Oscilloscope Settings:
Vertical, 2 V/cm
Horizontal, 0.1 msec/cm
Synchronization, internJ1
IF SIGNAL IS INCORRECI' OR ABSENT,
OIECK:
XBS-8 and related input circuitry
6-31
MAINTENANCE AND REPAIR
SECTION 6
Timing Control Card. Plug the card onto the extender card and insert in the
terminal. Check for the following Signals in the order given:
WAVEFORM 23: I/O Couunand
Oscilloscope Settings: .
Vertical, 1 V/cm
Horizontal, 10 usec/em
Synchronization, internal
IF SIGNAL IS INCORRECI' OR ABSENT,
CHECK:
XES-6, XFS-4, XFS-IO,- Processor
Card
WAVEFORM t4:
V SYNC
Oscilloscope Settings:
Verticle, IV/em
Horizontal, 10 usee/cm
Synchcnization, internal
.
IF SIGNAL IS INCORRECI' OR ABSENT,
CHECK:
XF4-12, XE3, circuitry related to
pin 4 of XE3
WAVEFORM 25:
H SYNC
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 0.2 usec/cm
Synchronization, internal
IF SIGNAL IS INCORRECI' OR ABSENT,
CHECK:
XF4-10, XE3, circuitry related to
pin 13 of XE3
6-32
MAINTENANCE AND REPAIR
WAVEFORM 26:
SECTION 6
Vertical Timing (VI,
V2, V4, V8)
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 0.2 usec/em
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
OfECK:
XFI-2, 4, 6, 8; XCI; H BLNK
circuitry
WAVEFORM 27:
POLL
Oscilloscope Settings:
Vertical, I V/cm
Horizontal, SO usec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR AB,SENT,
CHECK:
XD4-6. XE4
WAVEFORM 28:
POLL
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, I usec/cm
. Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XD4-6, XE4
6-33
MAINTENANCE AND REPAIR
WAVEFORM 29:
.
Master Clock, 29.952
Klz
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 0.1 usec/cm
Synchronization, internal
SIGNAL IS INCORRECT OR ABSENT,
CHECK:
IF
XBl-8, Q2, QI, YI and related components.
WAVEFORM 30:
LDCNT
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 10 usec/em
Synchronization, internal
IF SIGNAL -IS INCORRECT OR ABSENT,
CHECK:
.
XE2-8, XE6,
WAVEFORM 31:
XF6~4,
XFS-l3, XDS
H320
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 10 usec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XC2
SECTION 6
MAINTENANCE AND REPAIR
WAVEFORM 32:
SECTION 6
HF CLK
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 0.1 usec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
OIECK:
XBI-3, XBl-ll, XAI
Refresh Control Car-d. Plug the card onto the extender card and insert in
the terminal. Check for the following signals in the order given:
WAVEFORM 33:
Each RD bus line
Oscilloscope Settings:
Vertical, I V/cm
Horizontal, I usec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XEI-4, 6, 8, 10; XE2-4, 6, 8, 10
6-35
MAINTENANCE AND REPAIR
WAVEFORM 34:
SECTION 6
Each MA bus line
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, I usec/cm
Synchronization, internal
IF SIGNAL IS INCORREcr OR ABSENT,
CHECK:
XE3-3, 6,8,11; XE4-3, 6,8,11;
XES-3, 6, 8, 11; XE6-3, 6, 8, 11;
related input circuitry
WAVEFORM 3S:
Address COW'lter
(XC4) outputs
Oscilloscope Settings:
Vertical, I V/cm
Horizontal, I msec/cm
Synchronization, internal
IF SIGNAL IS INCORREcr OR ABSENT,
CHECK:
XC4, XC 3, XA3-11., XB4- 3, XB4- 6,
XB6-8, XD4-2, XD3-2, XE2-l2,
Timing Control Card
WAVEFORM 36:
RM-4,S,6,7
Oscilloscope Settings:
Vertical, I V/cm
Horizontal, I usec/cm
Synchronization, internal
IF SIGNAL IS INCORREcr OR ABSENT,
CHECK:
Refresh Memory Card
6-36
MAINTENANCE AND REPAIR
WAVEFORM 37:
SECTION 6
Address counter
(XCS) outputs
Oscilloscope Settin~s:
Vertical, 1 V/cm
Horizontal, 2 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XCS
WAVEFORM 38:
RMO,l,2,3
Oscilloscope Settings:
Vertical, 1 V/crn
Horizontal, 2 usee/ern
Synchronization, internal
IF SIGNAL IS
CHECK:
IN~ORRECT
OR ABSENT,
Input circuitry to XCS, Refresh
Memory Card
WAVEFORM 39:
Address counter
(XC3) outputs
Oscilloscope Settings:
Vertical, 1 V/crn
Horizontal, 2 usee/em
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XC3
6-37
MAINTENANCE AND REPAIR
WAVEFORM 40:
SECTION 6
RMO,1,2,3
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 2 usec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
Refresh Memory Card
WAVEFORM 41:
MA bus enable
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 1 usec/cm
Synchronization, internal
IF SIGNAL. IS INCORRECT OR ABSENT,
CHECK:
XB4-3, XB4-6, related input
circuitry
WAVEFORM 42:
RM-4, 5, 6, 7
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 2 usee/em
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
Refresh Memory Card
6-38
MAINTENANCE AND REPAIR
SECTION 6
Processor Card. Plug the card onto the extender card and insert in the
terminal. Check for the following signals in the order given:
WAVEFORM 43:
(
IC CLK
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 0.5 usec/cm
Synchronization. internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XC6-2, XC2, Timing Control Card
WAVEFORM 44:
CPU Timing
Oscilloscope Settings:
Vertical, lV/em
Horizontal, 2 usec/cm
Synchroni~tion, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XA4, XB2, circuitry related to
inputs to XA4
WAVEFORM 45:
Each
MA bus
line
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, I usec/cm
Synchronization. internal
IF SIGNAL IS INCORRECT OR ABSENT,
OIECK:
XF6-8; XE4-3,6,8,ll; XF4-3,6,8,llj
XE5-3,6; XFS-3,6,8,1Ij XD2j XD4i
XD3; XDSj input circuitry related
to XD2. XD4, XDS and XDS
6-39
MAINTENANCE AND REPAIR
WAVEFORM 46:
SECTION 6
Each B Data Bus line
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 2 Usec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
QIECK:
XFl-3, 6, 8, 11; XF2-3, 6, 8, 11:
related input circuitry
WAVEFORM 47:
CPU BUSY
Oscilloscope Settings:
Vertical, I V/cm
Horizontal, 2 usec/cm
Synchronization, internal
IF SIGNAL I S INCORRECT OR ABSENT,
CHECK:
.
XE6-8 and related input circuits
WAVEFORM 48:
T2 .
Oscilloscope Settings:
Vertical, I V/cm
Horizontal, 2 usec/em
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT.
CHECK:
XB4-6, XA2-3, input circuitry related to XA2- 3
6-40
SECTION 6
MAINTENANCE AND REPAIR
WAVEFORM 49:
WAIT
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 2 usee/em
Synchronization, internal
IF SIGNAL IS INCORREef OR ABSENT,
CHECK:
XE5-ll, XAS
WAVEFORM 50:
SYNC
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 0.5 usec/cm
Synchronization, internal
IF SIGNAL IS INtORREef OR ABSENT,
CHECK:
•
XC2
6-41
MAINTENANCE AND REPAIR
SECTION 6
RS-232 Interface. Plug the card onto the extender card and insert in the
terminal. Connect the ribbon cables. Check for the following waveforms in the
order given:
WAVEFORM 51:
Each A Data Bus line
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 1 msec/cm
Synch ronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
mECK:
XEl-3, 6, 8, 11; XGl-3, 6, 11;
related input circuitry to XEl
and XG1; Timing Control Card
WAVEFORM 52:
POLL
om
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, SO msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR- ABSENT,
CHECK:
XG6-3 and related input circuitry, Timing Control Card
WAVEFORM 53:
Reset Command
(MAl,2,3,4)
Oscilloscope Settings:
Vertical, lV/em
Horizontal, 2 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
Processor Card
6-42
SECTION 6
MAINTENANCE AND REPAIR
WAVEFORM 54:
STAT
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 1 usec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
DIECK:
XG4-8, Timing Control Card
WAVEFORM 55:
RS CLK
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 1 usec/em
Synchronization, internal
IF SIGNAL IS INCORRECT OR
mECK:
AB5~NT,
XBl-2, Timing Control Card
WAVEFORM 56:
Address comparator
output
Oscilloscope Settings:
Vertical, 0.2 V/cm
Horizontal, SO msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XD3-3, 4, 10, 11
6-43
MAINTENANCE AND REPAIR
SECTION 6
Cursor Control Card. Plug the card onto the extender card and insert
in the terminal. Connect the ribbon cable. Check for the following waveforms in
the order given:
WAVEFORM 57:
050
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 1 usec/em
Synchonization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
QIECK:
XD3-2, Keyboard Card (encoder)
WAVEFORM 58:
DSO
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 2 msec/cm
Synchronization, int~rnal
IF SIGNAL IS INCORREt1' OR ABSENT,
OIECK:
XD3-2, Keyboard Card (encoder)
WAVEFORM 59:
KYBD STROBE
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal 0.1 usec/cm
Synchronization, internal
IF SI GNAL IS INCORREt1' OR ABSENT,
OIECK:
XD3-6, XB2-6, circuitry related
to pin 4 of XB2, Timing Control
Card
SECTION 6
MAINTENANCE AND REPAIR
WAVEFORM 60;
MATCH
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 20 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
OIECK:
XCS-3,4,lO,11; XDS-3,4,lO,ll;
XES-3,4,10,ll; input circuitry to
XCS, XDS and XES
WAVEFORM 61:
H40 (CP) Clock
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, 20 usec/cm
Synch~onization, internal
IF SIGNAL IS INCORRECT OR
CHECK:
ABSE~T,
XD3-4, Timing Control Card
WAVEFORM 62:
Click
Oscilloscope Settings:
Vertical, 2 V/cm
Horizontal, 10 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XAl
6-45
MAINTENANCE AND REPAIR
WAVEFORM 63:
SECTION 6
Click
Oscilloscope Settings:
Vertical, 2 V/cm
Horizontal, 0.2 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XAI
WAVEFORM 64:
Beep
Oscilloscope Settings:
Vertical, 1 V/crn
Horizontal, 0.1 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XA4-l0, Ql, XAl, Refresh Buffer
Card
WAVEFORM 65:
Beep
Oscilloscope Settings:
Vertical, 5 V/cm
Horizontal, 10 msec/cm
Synchronization, internal
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
XA4-l0, Ql, XAl, Refresh Buffer
Card
6-46
MAINTENANCE AND REPAIR
SECTION 6
Refresh Memory Card. Do not perform bench maintenance on this card.
place with an operational card and return the faulty card to OMRON for repair.
Re-
Program (PROM) Memory Card. Do not perform bench maintenance on this card.
Replace with an operational card and return the faulty card to OMRON for repair.
Keyboard Card. Except for key switch and encoder replacement (refer to
Pgragraph 6.2), do not perform bench service on this card. Replace with an operational card and return the faulty card to OMRON for repair.
Motherboard. Do not perform bench service on this board. Replace with
an operational board and return the faulty board to OMRON for repair.
LED Assembly. Except for damage to the printed circuit card, a nonoperational LED (light emitting diode) is the only malfunction that can exist in
this assembly.
To test LEOs, apply 5 V dc to pin 8 or 9 of P24. Then individually ground
the cathode of each LED. Replace any LED that does not turn on. If an operational
, LED does not turn on under normal terminal operation, the problem is probably on
the Refresh Buffer Card.
Power Supply Assembly and Regulator Card. Basic power supply and regulator circuitry is used in the terminal. Use standard voltage and resistance measurement techniques to isolate problems in these two sections.
Terminator Card. The Terminator Card consists of five integrated-circuit
resistive networks (Xl through XS). A malfunction in a network is detected by measuring the res~stance between pin 16 and each of the other pins (1 through 15). The
readings should be 330 ohms on Xl through X4 and 470 ohms on XS.
CRT Display. Once a malfunction is narrowed to the CRT Display section,
the fault can be further isolated to a circuit and component as follows:
NOTE:
Before troubleshooting the CRT display, be sure the problem
is not caused by incorrect adjustment settings (refer to
Section 7) or absence of terminal inputs to the display.
1.
Many malfunctions can be narrowed to a section or circuit by analyzing the display presentation. When you are able to locate the problem area with this technique, proceed to Step 3.
2.
Measure +55 V dc. Connect the positive lead to the cathode of CRI06
and the negative lead to ground.
NOTE:
If +55 V dc is correct, go immediately to Step 3.
a.
If the voltage is too high, Ql13 may fire erratically and cause
raster "tearing".
b.
A short ci rcui t causes the regul ator to "foldback" to 1imi t the
current. Thi~ condition is indicated by a low or zero voltage
at the cathode of CR}06.
MAINTENANCE AND REPAIR
3.
WAVEFORM 66:
SECTION 6
c.
If the voltage cycles from low to high at high rate (about
1,000 times per second), the horizontal output stage (Ql23) is
probably faulty. A low, audible buzz is often associated with
this problem.
d.
If the voltage cycles from low to high at or near the vertical
rate, excessive pulse current is probably being drawn by the
vertical output amplifier (QI22).
e.
Disconnect Pl04 to isolate Ql22 and PlIO to isolate Ql23 and
the flyback transformer (TI03). Use a short alligator-clip lead
between the chassis and anode of VRlOl to re-establish ground
connection.
f.
If the regulator continues to perform abnormally, the problem
is probably a shorted electrolytic capacitor or defective components in the regulator circuit.
g.
If the regulator performs. normally, isolate the problem to individual stages as outlined in Step 3.
Check for the following waveforms in the order given.
Q10l Anode
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, field rate
Synchroni zation; external
with leading edge ot V SYNC
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
R106-108, C103 and Cl04, R102-104,
CRI01 and 102, QIOl
WAVEFORM 67:
Ql22 Base
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, field rate
Synchronization; external
with leading edge of V SYNC
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
RI09 and 110, Q102
6-48
MAINTENANCE AND REPAIR
WAVEFORM 68:
SECTION 6
Q122 Emitter
Oscilloscope Settings:
Vertical, 1 V/cm
Horizontal, field rate
Synchronization; external
with leading edge of V SYNC
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
R114
WAVEFORM 69:
Q122 Collector
OScilloscope Settings:
Vertical, 50 V/cm
Horizontal, field rate
Synchronization; external
with leading edge of V SYNC
IF SIGNAL IS INCORRECT OR ABSENT,
OIECK:
CRl03, RI13 and CI07, RI2l
WAVEFORM 70:
Ql09 Collector
Oscilloscope Settings:
Vertical, 5 V/cm
Horizontal, line rate
Synchronization; external
with leading edge of H SYNC
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
R142 and Cl16, Cl14, QllO, Q109
andQlll
6-49
MAINTENANCE AND REPAIR
WAVEFORM 71:
SECTION 6
Ql12 Collector
Oscilloscope Settings:
Vertical,S V/cm
Horizontal, line rate
Synchronization; external
with leading edge of H SYNC
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
C117, CRlOS, Rl43 and R144, Ql12
WAVEFORM 72:
Ql14 Collector
Oscilloscope Settings:
Vertical, 0.5 V/cm
Horizontal, line rate
Synchronization; external
with leading edge of H SYNC
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
.
C121, R153, R156 and R157, C122,
CRl09, R152, C122, Qll4 and Ql15
WAVEFORM 73:
Ql15 Collector
Oscilloscope Settings:
Vertical, SO V/cm
Horizontal, line rate
Synchronization; external
with leading edge of H SYNC
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
CRllO, Q1l5
6-50
MAINTENANCE AND REPAIR
WAVEFORM 74:
SECTION 6
Q123 Collector (horizontal flyback pulse)
Oscilloscope Settings:
Vertical, 100 V/cm
Horizontal, line rate
Synchronization; external
with leading edge of H SYNC
IF SIGNAL IS INCORRECT OR ABSENT J
CHECK:
TIOl, Q123
WAVEFORM 7S:
Radiated Pulse from
Tl03, 10:1, probe held
2" away, AC coupled
Oscilloscope Settings:
Vertical, 50 V/cm
Horizontal, line rate
Synchronization; external with
leading e~ge of H SYNC
IF SIGNAL IS INCORRECT OR ABSENT,
OIECK:
CRl16 and C127, Ll24, Tl03
WAVEFORM 76:
CRllS Cathode
Oscilloscope Settings:
Vertical, 50 V/cm
Horizontal, line rate
Synchronization; external with
leading edge of H SYNC
IF SIGNAL IS INCORRECT OR ABSENT,
OIECK:
C130, CRltS
6-51
MAINTENANCE AND REPAIR
WAVEFORM 77:
SECTION 6
CRT (VI) Cathode
Oscilloscope Settings:
Vertical, 10 V/cm
Horizontal, line rate
Synchronization; external with
leading edge of H SYNC
IF SIGNAL IS INCORRECT OR ABSENT,
CHECK:
Ql03, QI04 and related components
6.3.B
Removal and Replacement Procedures
Circuit Card Removal and Replacement. The procedure for removing and replacing circuit cards is given in Paragraph 6.2.5.
CAUTION:
IMPROPER HANDLING CAN DAMAGE CIRCUIT CARDS.
REFER TO PARAGRAPH 6.2.5.
Printed Circuit Card Components. To remove or install components, other
than semiconductor components, proceed as follows:
1.
Scrape away any coating from the card pads with a sharp-edged instrument.
2.
Use a heat sink (shunt) to protect adjacent components.
3.
With a contrOlled-heat solderl.ng iron, remove component and clear
excess solder from mounting holes as quickly as possible.
4.
Bend replacement component leads to fit the distance between mounting
holes and insert leads.
5.
Use a heat sink to protect the replacement component and adjacent components.
6.
Solder and clip leads l/B" mm1mum above the pad.
cleanly, using as little solder as possible.
Semiconductor Components.
proceed as follows:
Solder quickly and
To remove or install semiconductor components,
1.
Note the pin arrangement when removing the component.
2.
Isolate the component from the soldering iron with a heat sink (shunt).
6-52
MAINTENANCE AND REPAIR
SECTION 6
3.
With a controlled-heat soldering iron (47 watts maximum), remove the
component and clear excess solder from the mounting holes as quickly
as possible.
4.
Insert the new component pins to match the arrangement of the old
component.
5.
Solder quickly and cleanly, using as little solder as possible.
Integrated Circuit Removal and Replacement. Integrated circuit (IC) components are installed in IC sockets. To remove, use an IC puller. ~~en installing
these components, make sure the IC is oriented the same way as the socket into which
it is being installed.
CAUTION:
TO PREVENT DAMAGE BY STATIC DISCHARGE, HANDLE IC
COMPONENTS IN THE SAME WAY AS CIRCUIT CARDS. REFER
TO PARAGRAPH 6.2.5.
Cathode Ray Tube (CRT) Removal and Replacement.
the CRT, proceed as follows:
To remove and install
1.
Turn the terminal off and remove the ac plug.
2.
Wait 2 to 3 minutes for the high voltage (H.V.) supply to drain.
3.
Remove the top section of the cabinet (refer to Paragraph 6.2.5).
4.
Peel the H. V., cap on the red lead back from the CRT (see Figure 6-6).
5.
Discharge H.V. by shorting the H.V. lead and CRT anode button to
ground. Also short the anode button to the aquadag coating on the
CRT.
6.
Remove the H.V. lead from the CRT' by pinching the two spring wires
together.
7.
Disconnect Pl06 (yellow and green wires) and PIll (red and blue \\'ires)
from the Moni tor Deflection Board (see Figure 6-5). ~1ake sure the
wires are free of any cahling or clamps.
8.
Remove the CRT socket.
9.
Remove the upper two bolts and loosen the lower two bolts shOl·;n in
Figure 6-6.
10.
Support the CRT face and remove the lower two bolts in Figure 6-6.
WARNING:
WEAR SAFETY GOGGLES AND HEAVY GLOVES WHEN REMOVING
OR INSTALLING THE CRT.
MAINTENANCE AND REPAIR
Figure 6-6.
11.
SECTION 6
CRT mounting bolts and high voltage connector.
Face the screen and carefully pull the CRT with the yoke assembly
toward you.
WARNING 1:
DO NOT STRIKE OR SCRATCH OR USE MORE THAN MODERATE
PRESSURE WHEN HANDLING THE CRT.
WARNING -2:
STRESS IN THE CRT NECK CAN BREAK THE CRT AND CAUSE
SERIOUS PERSONAL INJURY. HOLD THE CRT BY THE RIM
OF THE FACE, NEVER BY THE NECK. YOU MAY GENTLY
SUPPORT THE NECK, BUT ONLY TO STEADY AND GUIDE THE
CRT.
12.
Place the CRT face down on a soft grit-free surface.
13.
Loosen the yoke-mounting screw (refer to Figure 7-14 in Section 7)
and pull the yoke straight up and off the CRT neck.
WARNING:
14.
NEVER PRY THE YOKE OFF THE CRT NECK.
SCRATCH OR BREAK THE CRT.
TO DO SO MAY
To replace the CRT, install the deflection yoke and repeat steps
1 through 11 in reverse.
NOTE 1:
Replace the CRT so that the anode button is on the right
side as viewed from the front of the terminal.
NOTE 2:
Make sure the CRT adjustments are correctly set (refer to
Section 7).
6-54
SECTION 7
A.DJUSTMENTS
REQUIRED EQUIPMENT
7.1
The following test equipment is needed to make adjustments in the 8025 CRT
Terminal:
Triplett 310 Multimeter or equivalent
Tektronix 422 Oscilloscope or equivalent.
7.2
+5 V dc REGULA.TED OUTPUT
NOTE:
Check that the line voltage is 117 V ac + 10% before you
make this adjustment.
The +5 V dc regulated output adjustment is located on the Regulator Card
(see Figure 7-1). This card is installed in the first card cage slot (left side as
viewed from the rear of the terminal).
Connect the positive and negative leads of the multimeter to test points TP
+5 REG and TP GND respectively. Set R4 to provide 5.00 + 0.10 V dc if required .
..TP+5V
REG.
Figure 7-1. Regulator Card:
point locations.
7.3
+5 V dc
adjustn~nt
and test
CLICK/BEEP VOLUME
The click/beep volume adjustment is located on the Cursor Control Card (see
Figure 7-2). This card is installed in the second slot from the left end (as viewed
from the rear of the terminal) of the card cage.
7-1
ADJUSTMENTS
SECTION 7
Set R25 for the desired click/beep volume.
for both click and beep.
This adjustment sets the volume
Figu~e
7-2. Cursor Control Card click/beep
volume adjustment location.
7.4
CRT DISPLAY ADJUSTMENTS
NOTE:
All display adjustments are made with the terminal operating,
the screen filled with data, and the cabinet removed.
WARNING:
7.4.1
DANGEROUSLY HIGH VOLTAGES ARE PRESENT IN THE CRT AREA.
Preliminary Procedure
Turn the terminal on and enter characters from the keyboard to fill the
screen completely. The pattern shown in Figure 7-3 gives a good picture for making
CRT display adjustments.
With an oscilloscope, check that horizontal and vertical sync signals are
a nominal +4 volts peak-to-peak. Horizontal sync is available at pin 6, and vertical sync at pin 9, of Pl12 (the plug connected to the edge connector of the Monitor
Deflection Board). Pins 1 and 10 of Pl12 are at ground.
NOTE:
A significantly lower amplitude indicates a possible
problem in the Timing Control Card or the Video Card.
ADJUSTMENTS
Figure 7-3.
SECTION 7
Normal 8025 CRT presentation. (24 line display shown)
If required, adjust the BRIGHTNESS control on the keyboard to just "extinguish" the raster. Figure 7-3 illustrates the correct setting. Figures 7-9 and
7-13 show displays for which the BRIGHTNESS control is set too high.
7.4.2
+55 V de (B+) Adjust
The B+ adjustment (R134) is located on the Monitor Deflection Board (see
Figure 7-4).
Connect the positive lead of the multimeter to the cathode of CRl06, and
the negative lead to the anode of VRlOl (see Figure 7-4). Set R134 to provide +55
volts de.
7.4.3
Video Gain
The video gain adjustment (Rl19) is located on the Monitor Deflection Board
(see Figure 7-4).
Adjust Rl19 (see Figure 7-4) just enough for maximum contrast between the
characters and the black background.
SECTION .
ADJUSTMENTS
HORIZONTAL
WIDTH
FOCUS
GROUND
B+ ADJUST
+55Vdc
VERTICAL
HEIGHT
HORIZONTAL
CENTERING
Figure 7-4. Monitor Deflection Card: CRT
adjustment and "test point" locations.
7-4
ADJUSTMENTS
Vertical Adjustments
7.4.4
SECTION 7
All vertical adjustments are located on the Monitor Deflection Board (see
Figure 7-4).
NOTE:
The heightl vertical hold l and vertical linearity
adjustments tend to interact. Changing one may
affect the others.
Figures 7-S through 7-8 show CRT presentations with incorrect settings of
the vertical adjustment. Figure 7-3 illustrates a normal display.
7.4.S
1.
If the presentation is not centered verticallYI refer to paragraph
7.4.6.
2.
Set Rl03 (vertical hold) near the center of its rotation range.
3.
Adjust RI07 (height) for vertical size indicated in Figure 7-3.
4.
Adjust Rl09 (vertical linearity) for best overall linearity from
top to bottom. Use the spaces between character rows as a guide.
S.
Short the input end of RIOI to ground and set R103 (vertical hold)
until the video presentation rolls down slowly.
6.
Remove the short used in Step 4.
7.
Recheck height and vertical linearity.
Horizontal. Adjustments
Except for the horizontal linearity adjustment l all horizontal adjustments
are located on the Monitor Deflection Board (see Figure 7-4). You will find the
horizontal linearity adjustment sleeve on the neck of the CRT I beneath the deflection yoke.
NOTE #1: No horizontal hold adjustment is used.
NOTE #2: Raster width is a function of both the horizontal width
and the linearity adjustments.
NOTE #3: Horizontal centering is a function of both the horizontal
(video) centering adjustment described in this paragraph
and the raster centering adjustments described in paragraph 7.4.6.
Figures 7-9 and 7-10 show CRT presentations with incorrect horizontal adjustment settings. Figure 7-3 shows a normal display.
7-5
ADJUSTMENTS
SECTIO~
Figure 7-5. Vertical linearLty adjustment
(R109) incorrectly set.(24 line display shown)
7-6
ADJUST~1ENTS
SEen 0\ 7
Figure 7-6. Height adjustment (RI07) incorrectly set. (24 line display shown)
7-7
SECTlO:\ 7
AD.J usn'IENTS
Figure 7-7. vertical hold adjustment (R103)
incorrectly set. (24 line display shown)
ADJUSTf\lE:-.JTS
SLCT I O~~ 7
... til'"
"
•
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incorrectl~l
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set. (24 line display S}lOv;:1)
ADJUSTMENTS
SECTION 7
Figure 7-9. Horizontal width adjustment (L104)
incorrectly set. Bri ghtness control too hi gh •
(24 line display shown)
7-10
ADJUSTMENTS
SECTION 7
Figure 7-10. Severe misadjustment of hori;z:ontal
centering adjustment (R143). Note foldover on
right side. (24 line display shown)
7-11
ADJUSTMENTS
1.
SECTION 7
Insert the horizontal linearity sleeve (see Figure 7-11) about onethird of its length under the deflection yoke.
2.
Adjust Ll04 (width) for the horizontal size indicated in Figure 7-3.
3.
Slide the linearity sleeve further. under the yoke to get the best
overall linearity from left to right. Use character widths as a
guide. Do not use this adjustment to set horizontal width. It is to
be used only to optimize linearity.
CAUTION:
7.4.6
INSERTING THE LINEARITY SLEEVE FURTHER THAN NECESSARY
CAN DAMAGE THE HORIZONTAL OUTPUT CIRCUIT.
4.
Readjust LI04 for correct horizontal size.
5.
Make fine adjustments of the linearity sleeve and L104, if required,
for optimum linearity and width (refer to Figure 7-3).
6.
If the presentation is not centered horizontally as shown in Figure
7-12, turn the BRIGHTNESS control up until the raster is visible (see
Figure 7-13).
7.
If the video is not centered horizontally within the raster, center
the video with R143 (horizontal centering).
8.
If the raster is not centered horizontally, refer to paragraph 7.4.6.
'Centering Adjustments
:.;'"
'j;
Two ring magnets mounted on the neck;·of the CRT (see Figure 7-14) position
the raster on "the CRT face. Rotate the centering magnets to center the raster vertically and horizontally. Correct raster placement positions the video as shown in
Figure 7-3.
7.4.7
Yoke Adjustments
If the presentation is tilted (see Figure 7-15), the deflection yoke is not
positioned correctly on the neck of the CRT. Loosen the yoke-mounting screw (see
Figure 7-14) and rotate the yoke so that the presentation appears as shown in Figure 7-3.
7.4.8
Focus
Adjust R167 (focus) to obtain the sharpest overall presentation possible.
Use characters in the corners and center of the display as a guide. Figure 7-3 shows
a presentation with correct focus.
7 -12
SECTION 7
6J)JUSTMENTS
Figure 7-11. Horizontal linearity is positioned
on neck of CRT for best overall linearity from
left to right.
7-13
ADJUSTMENTS
SECTION 7
Figure 7-12. Example of a horizontal centering problem
caused by incorrect setting of the horizontal centering
adjustment (R143) or of the raster centering magnet discussed in paragraph 7.4.6. (24 line display shown)
7-14
SECTION 7
ADJUSTMENTS
Figure 7-13. To determine which centering adjustment
is incorrectly set, turn the control up until the
raster is visible. The photo illustrates the correct
setting of the horizontal (video) centering adjustment
(Rl43) and the raster centering magnets. Note that
the vertical linearity adjustment; (RI09) is incorrectly set. (24 line display shown)
ADJUSTMENTS
SECTION 7
Figure 7-14. Raster centering magnets are used to
center the raster vertically and horizontally on
the CRT screen. The deflection yoke is used to correct
raster tilt.
7-16
sr.cnON
rigure 7-15.
Deflection yoke incorrectlY set.
(24 line display shown)
7
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,4
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1. 5~ GATE~; ~-1(Eh,.6,'.IO
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CCw
tRT
.0
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te,
1,2.~4,~,"
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XE~.4"IO~~"tl)
"'1IOO-1IC.2, I,t~
740&- le.!, ~'''io,II,r1,I' lI.D?,I,1.'
I. A88A~,ATIONS (NON 'lTANDARO)
1.U- 1("',11,1'2,1'
CJ-(LOCK~18IT. CLR-CLEAR
•• O-FA~l DOWN,
'l-~RlAl.INP\JT. S/1.0-~IFT/I.OAO. H~I~·_''OmL O.'v',
NOTES: UN\.ES~ OTHERWISE SPEC.I.IEO
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8-33
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"'DEO CO~OL.
COMPONENT PARTS LIST
SECTION 9
CURSOR CONTROL CARD
REF. DES.
ASSEMBLY 99-376-01C
I
I
DESCRIPTION
OMRON PIN
CAPACITORS
C18, C19
.001UF, 100V, 10\, Disc
80-320-90
C21, C22
.005UF, 100V
Disc
80-320-92
C2,3,4,5,7,8,9,
10,11,12,14,20
.01UF, 100V
Disc
80-320-93
• 047UF, 100V
Mylar
80-312-58
C23
.lUF,50V
Disc
80-319-01
C16
4.7UF,10V
'rant
80-310-41
C26,27
10OF, 25V
Elect
C24
39OF,10V
'rant
·80-302-08
C13,15,25
10OF,25V 10\
, Elect
80-305-21
Tant
80-311-58
. C17
'C6,C1
150UF,15V,
..
80-305-29
DIODES
CRl-5,7-11
IN914/IN4148
VRI
Zener IN5227A
80-404-03
,
80-404-11
. INTEGRATED CIRCUITS
XC1,XC2, XB2
7400N
80-460-22
XB3,XB4,XBS
7403N
80-460-59
XD3
7404N
80-460-18
XB1
7408N
80-460-50
XE2,XD2,XC3
7474N
80-460-34
XE6
7493N
80-460-39
XE1, XD1, XA1
74123N
80-460-52
XD6,XC6
74161N/9316
80-460-58
XE4,XD4,XC4
74175N
80-460-64
XES,XD5,XC5
8242/9386
80-460-88
XA4
72747N
80-460-86
COMPONENT PARTS LIST
SECTION 9
CURSOR CONTROL CARD
REF. DES.
ASSEMBLY 99-376-01C
I
I
DESCRIPTION
OMRON PIN
RESISTORS
R26
10on,1/4W,5\
80-211-01
R6,R7
2200,1/4W, 5\
80-212-21
RS,lS,19,34,33,12
1Kn,1/4W,5\
80-211-02
RB,13,16,21,24
2. 2KO,1/4W,5\
80-212-22
Rl,27,28,30
2.7Kn,1/4W;5\
80-212-72
R31,32
12KO, 1/4W,5\
80-211-23
R9,10,22
10Kfl, 1/4W,5\
80-211-03
Rl1,14,17
15Kfl, 1/4W,5\
80-211-53
Rl8,20,23
22Kfl, 1/4W,5\
80-212-23
R3,4,29
39Kfl, 1/4W,5\
80-213-93
R25
ADJ,lOK, Cermet Trimpot
80-270-52
XB6
Pack 4.7K, 1/4W,5\
80-290-50
J23
Socket, 16 Pin Dip
80-676-04
TRANSISTORS
22, 3,4,5
2N4401
80-419-01
Q1
2N4403
80-423-02
Ejector
40-109-01
9-2
SECTION 9
:QMPONENT PARTS LIST
lCEYBOARD ASSEMBLY
REF. DES.
Assembly 99-453-XXA
I
I
DESCRIPTION
OMRON PIN
CAPACITORS
C1,C2
lO&F, 25V, Electrolytic
80-305-21
C3,C4
.01UF, 100V, Disc
80-320-93
C5
1000PF, 1KV, Disc
80-319-05
CRl thru CR67
CR69 thru CR90
CRJO thru 35,40,
41,42,60,62,63
Removed -02
Diod~,
80-404-03
IN914/IN4148
INTEGRATED CIRCUITS
Xl
MM5740 BEE/N
80-460-95
xl,X3
SN7404N
80-460-18
INTEGRATED CIRCUIT SOCKETS
J71
16 Pin Dip
80-676-04
Xl
40 Pin Dip
80-675-10
R1,R2
Resistor, 4700, 1/4W, 5\ Carbo Compo
,
80-214-71
SWITCHES
51
Space, Form A
80-932-10
53-514, 516-594
558-569 Remove-02
Single, Form A
.
Shift & Lock
80-932-02
52-515
80-932-03
SECTION 9
COMPONENT PARTS LIST
L.E.D. DISPLAY
REF. DES.
ASSEMBLY 99-393-XXC
I
I
DESCRIPTION
CRl, CR2, CR5-CR8
L.E.D. (Fairchild FLV 104)
MOTHER BOARD
REF. DES.
OMRDN PiN
80-400-01
ASSEMBLY 99-4l4-XXB
I
I
DESCRIPTION
OMRDN
PIN
CAPACITORS
C1
220UF, 10WV,Tant
80-310-51
C2-Cl1
22UF, lSWV, Tant
80-311-53
REG J1-J4
PWB, Connector, 80 Pin
80-612-12
9-4
SECTION 9
COMPONENT PARTS LIST
POWER SUPPLY ASSEMBLY
ASSEMBLY 07-041-01C
I
OMRON PIN
REF. DES.
DESCRIPTION
CAPACITORS
C1
40,00OMFD, 20WVDC
80-305-23
C2,C3
3,900MFD, 35WVDC
80-300-67
C4
1,700MFD, 100WVDC
80-307-13
CR1,CR2
RECTIFIER ASSEMBLY
07-046-01
TRANSFORMERS
T1
Transformer
85-023-01
T2
Transformer
85-021-01
POWER SUPPLY ASSEMBLY
ASSEMBLY 07-041-02A
I
OMRON PIN
REF. DES.
\
DESCRIPTION
CAPACITORS
C1
40,000 lJ,F, 20WVDC
80-305-23
C2,C3
3,900 ).IF, 35WVDC
80-300-67
C4
1,700 lJ,F, 100WVDC
80-307-13
TRANSFORMERS
T1
Transformer
85·-023-01
T2
Transformer
.
Rectifier, Center Tapped Bridge
85-021-01
CRl,CR2
-"..
8-5
80-412-11
COMPONENT PARTS LIST
SECTION 9
PROCESSOR CARD
REF. DES.
ASSEMBLY 99-369-01C
I
I
DESCRIPTION
OMRON PIN
CAPACITORS
C2
10UF, 2SV, 10\, Elect
80-305-21
C3
.001UF,
80-320-90
C4-C11,C13-C17
.01UF, 100V, Cer Disc
80-320-93
C12, C1
lS0MF, 10V, Tant
80-311-58
CRl-CR9
Diodes, IN914/IN4148
80-404-03
~OOV,
Cer Disc
INTEGRATED CIRCUITS
.
-
XB4, XB6, XCS
7400N
XC3,XC4,XE3, XF3
7403N
80-460-59
XB5, XD6
7404N
80-460-18
XC6
7406N
80-460-73
XE6
7410N
80-460-19
7438N
80-461-22
XE4,XE5,XF1,
. XF2,XF4,XFS
-
.80-460-22
XF6
7440N
XB2
74L42N
80-460-70
XAS,XA6
7474N
80-460-34
XD2,XD3,XD4,XD5
7475N
80-460-38
XA3,XA4
74107N
80-460-46
XC2
8008
80-460-90
XA2,XB3,XE1,XE2
8T380
80-461-07
80-460-42
RESISTORS
R23
2700 ,S\,1/4W
80-212-71
R22
1K, 5\,1/4W
80-211-02
R1,R3-R21,R24
2.7K, S\,1/4W
80-212-03
R2
10K, 5\, 1/4W
80-211-03
Q1,Q2
Transistor, 2N4403
80-423-02
XC2
I.C. Socket, 18 Pin Dip
80-675-09
Ejector
40-109-07
9-6
l
SECTION 9
COMPONENT PARTS LIST
.
-.~
PROM CARD
ASSEMBLY 99-434-0lA
I
REF. DES.
I
DESCRIPTION
OMRON PiN
CAPACITORS
Cl
l50UF, 10V, Tant;,
80-311-058
C2 thru C14
.01U, 100V Cer. Disc
80-320-093
INTEGRATED CIRCUITS
XF5
7404
80-460-018
XE3,XF4
7407
80-461-036
XE6
7430
80-460-045
XE4,XE5
7442
80-460-031
XF3
Resistor Pak 2.2K
80-290-051
Socket (16 Pin Dip)
80-676-04
XA1
XB1
XC1
XD1
XF6
thru
thru
thru
thru
XAB
XB8
XC8
XDB
.
<
COMPONENT PARTS LIST
SECTION 9
ASSEMBLY 99-436-36A
PROM CARD
I
REF. DES.
I
DESCRIPTION
OMRON PIN
CAPACITORS
C1
15OUF, lOV Tant
80-311-058
C2 thru C14
.01U, 100V Cer. Disc
INTEGRATED CIRCUITS
80-320-093
XB1 LOOOO-0377
825126
22-011-59
XD1 HOOOo-0377
825126
22-011-60
XB2 L0400-0777
825126
22-011-61
XD2 H0400-0777
825126
22-011-62
XB3 L1000-1377
825126
22-011-63
XD3 H1000-1377
825126
22-011-64
XB4 L1400-1777
825126
22-011-65
.XD4 H1400-1777
825126
22-011-66
XB5 L2000-2377
825126
22-011-67
XDS H2000-2377
825126
22-011-68
XB6 L2400-2777
825126
22-011-69
XD6 H2400-2777
825126
22-011-70
XB7 L3000-3377
825126
22-011-71
XD7 H3000-3317
825126
22-011-72
XB8 L3400-3777
825126
22-011-73
XD8 H3400-3777
825126
22-011-74
XF5
7404
80-460-018
XE3,XF4
7407
80-461-036
XE6
7430
80-460-045
XE4,XES
7442
80-460-031
Buffered Prom Sub-Assy.
99-434-02
Ejector
40-109-08
XF3
Resistor Pak 2.2K
80-290-051
XF6
Socket Adapter
80-625-03
Socket (16 Pin Dip)
80-676-04
XAI
XB1
XC1
XDI
XF6
thru
thru
thru
thru
XA8
XB8
XC8
XDS
9-8
COMPONENT PARTS LIST
SECTION 9
ASSEMBLY 99-44S-XXB
RAM CARD
REF. DES.
IDESCRIPTION
OMRON pIN
CAPACITORS
C6
ls0UF, 10V Tant
80-311-058
C1-CS, C7-C38
C1-Cs, C7-C22
.01UF,10OV Cer. Disc
80-320-093
INTEGRATED CIRCUITS
,
XA1-XA8
XB1-XB8
XC1-XC8
XD1-XD8
2102-2
80-460-91
XE2, XF2
74HOO
80-460-35
XE2, XF2
7438
80-461-22
XES
7442
80-460-031
XFS
7404
80-460-018
XE6
7420
80-460-017
XF1, XF3, XE4
7407
80-461-036
EJECTORS
Ejector
40-109-05
Ejector
40-109-09
Buffered Ram Sub-Assembly
99-433-01
XE3,XE1
Resistor Pak 2.2K
80-290-051
Rl
Resistor 4. 7K, 1/ 4W, 5\·
80-214-72
Socket (16 Pin Dip)
80-675-008
E2,F2
I.C. Socket, 14 Pin Dip
80-675-007
XF6
Socket Adapter
80-625-03
Al
B1
C1
01
thru
thru
thru
thru
A8
B8
C8
08, F6
9-9
COMPONENT PARTS LIST
SECTION 9
ASSEMBLY 99-433-XXC
RAM CARD
REF. DES.
I
I
DESCRIPTION
OMRON PIN
CAPACITORS
C6
150UF lOV TANT
80-311-058
CI-C5, C7"'C38
C1-C5, C7-C22
.01UF 100V Cer. Disc.
80-320-093
INTEGRATED CIRCUITS
XES
7442
80-460-031
XFS
7404
80-460-018
XE6
7420
80-460-017
XFl,XF3,XE4
7407
80-461-036
E2,F2
I.C. Socket, 14 Pin Dip
80-675-007
Rl
Resistor, 4.7K, 1/4W, 5%
80-214-72
XE3, XEl
Resistor Pak 2.2K
80-290-051
Al thru A8
Socket (16 Pin· Dip)
80-675-008
Socket Adaptor
80-625,,03
B1 thru B8
C1 thru C8
Dl thru D8
F6
XF6
9-10
COMPONENT PARTS LIST
SECTION 9
REFRESH BUFFER CARD
REF. DES.
ASSEMBLY 99-415-01D
t
T
DESCRIPTION
OMRON PIN
CAPACITORS
.C2-C8, C9, C10, C12
Cere , O.OlUF, 100V
80-320-93
C13
E1ec. , 10UF, 25V
80-305-21
C11
150UF, lOW, Tant
80-311-58
INTEGRATED CIRCUITS
XB6, XES
7404N
80-460-18
XA4, XB4, XC4
7438N
80-461-22
XD6
7427N
80-460-61
XD2,XD3,XE2,XE3
2532B
80-461-34
XE6
7430N
80-460-45
XB5,XDS
7400N
80-460-22
XD4,XE4
7402N
80-460-62
XAS
7410N
80-460-19
XC5
7474N
80-460-34
XA6
74107N
80-460-46
XB2,XB3,XC:2,XC3
74175N
80-460-64
XA2
7442N
80-460-31
XA3
74161N
80-460-58
XB1,XC1
7406N
80-460-73
XC6,XD1,XE1
7408N
80-460-50
XC6
74H08
80-461-49
RESISTORS
Rl-Rl2
lOon, 1/4W, 5\
80-211-01
Rl3,14,1S,16
1K, 1/4W,S\
80-211-02
SOCKETS
J1
14 Pin Dip
80-676-03
XE2,XD2
16 Pin Dip
80-676-01
9-11
COMPONENT PARTS LIST
SECTION 9
ASSEMBLY 99-457-018
REFRESH CONTROL CARD
REF. DES.
I
I
DESCRIPTION
OMRON PIN
CAPACITORS
C2-C6, C8-C12
.OlUF, 10OV., Cere Disc.
80-320-93
Cl
.10OF, 25V., 10\ Elec.
80-305-21
C7
150MF, 15V, Tant
80-311-55
INTEGRATED CIRCUITS
XA3,XC2
7400N
80-460-22
X03-XD6
7404N
80-460-18
XB3,XB4
7408N
80-460-50
XDl
7420N
80-460-17
XCl
7427N
80-460-61
XA2,XB5,XB6
7430N
80-460-45
XD2,XE3-XE6
7438N
80-461-22
XA4
74107N
80-460-46
kBl,XB2
74161N
80-460-58
XC3-XC6
74163N
80-460-79
XEl,XE2 .
7414N
.
Card Ejector
80-461-45
40-109-06
Rl,R4
Resistor, lK,5\, 1/4W
80-211-02
9-12
COMPONENT PARTS LIST
SECTION 9 .
ASSEMBLY 99-402-01B
REGULATOR CARD
REF.DES.
I
DESCRIPTION
OMRON PIN
CAPACITORS
C5
150MF, 15 VDC Tant'·
80-311-55
C6,C7,C8
1.0MF, SO VDC, c~r.
80-319-06
C9,CI0,C11
10MF, 15 VDC, Tant
80-311-56
C12
0.lUF,20%, Cere Disc.
80-319-01
RESISTORS
Rl
Fixed, WW, 20,8W,±S%
80-258-03
R2
Fixed, WW, 3. 9S'2, lW, 5%
80-251-18
R3
Fixed, lK, 1/4W, 5%
80-211,02
R5
47C>n,5%, 1/4W
80-214-71
REGUlATORS
Zl
780SCP
80-464-02
Z3
7812CP
80-464-03
Z2
7906CP
80-464-05
CR1
Diode Zener
80-403-08
R4
Pot, -Trim, lOOn
80-270-15
Card Ejector
40-109-10
.
9-13
COMPONENT PARTS LIST
SECTION 9
i
RS232 INTERFACE CARD
REF. DES.
ASSEMBLY 99-451-00lA
I
DESCRIPTION
OMRON PIN
CAPACITORS
Cs-C10,C12-C14
C23,C24
.0IUF,100V, Cere Disc.
Cll
• 001UF,sOOV, Cere Disc.
80-320-090
C4
300PF,lKV, Cere Disc.
80-319-016
80-320-093
.<
~ ..
,
.;:;.
.
~"
:; 1
i
~
C21,C22,CI6
400PF,1KV, Cere Disc.
80-319-003
1
C17-C20
sOOPF,1KV, Cere Disc.
80-319-002
':c
C1-C3,C2s
1SOUF,1sV, Tant, Dip
80-311-055
CIS
39UF,10V, Tant
80-302-008
j
INTEGRATED CIRCUITS
XB1,XD4
7404
80-460-018
XB3,XB4
74161
80-460-058
XBS
1489
80-460-084
XB6
1488
80-460-083
XC1,XC4,XF4
7400
80-460-022
XC3
7402
80-460-062
XCS
7432
80-461-054
XD2,XE1,XE2
XF1,XG1
7403
80-460-059
XD3
9386
80-460-088
XD6
74123
80-460-052
XE4
7442
80-460-031
XES
9314
80-461-029
XE6,XFS,XG6
7408
80-460-050
XF6,XGS
74107
80-460-046
XG2
74175
80-460-064
XG3
TRI602A
80-460-098
XG4
7407
80-461-036
XC6
7410
80-460-019
9-14
;
~
'I·"
COMPONENT PARTS LIST
SECTION 9
RS232 INTERFACE CARD
REF. DES.
ASSEMBLY 99-4S1-00lA
DESCRIPTION
OMRON PIN
RESISTORS
Rl
Fixed, 10K, 1/4W, ,!S\
80-211-003
R2
Fixed, 27on,1/4W, ±S\
80-212-071
Rl,RS
Fixed, 3300,1/4W, ~S\
80-213-031
R4
Fixed, 22on, 1/4W, tS\
80-212-021
R6
Fixed, 22K, 1/4W,~S'
SOCKETS
40 Pin Dip
80-212-023
80-675-010
14 Pin Dip
80-676-003
(REF
G3)
(REF J20 (A6) )
,
(REF
J21 (AS»
16 Pin Dip
80-676-004
(REF
A2)
16 Pin Dip
80-676-001
Card Ejector
40-109-009
CRl,CR2
Diode, IN914/IN4148
80-404-003
XB2,XC2
Resistor Pack, 2.2K (760-1)
80-290-051
TERMINATOR
REF. DES.
ASSEMBLY 99-394-01B
CARD
I
DESCRIPTION
OMRON PIN
CAPACITORS
C1,C2
150UF,10WV, Tant
80-311-58
C3-C6
• 01UF,100V, 10\, Cere Disc
80-320-93
RESISTOR PACK
X1-X4
(898-1-Rl30) 330Q
80-290-53
X5
(893-3-R470) 470Q
80-290-54
9-15
COMPONENT PARTS LIST
SECTION 9
TIMING CONTROL CARD
REF. DES.
ASSEMBLY 99-4S2-01C
I
I
DESCRIPTION.
OMRON PIN
CAPACITORS
C3
lSOMF, lSV, Tant
ci
33PF, 100V, Silver Mica
80-320-87
C14
39UF, lOV, Tant
80-302-08
C2
lUF, SOV, Disc. Cere
80-319-01
C4-C12,C1S
.01UF, ioov, Disc. Cere
INTEGRATED CIRCUITS
80-320-93
XE2
7400
80-460-22
XB1,XC6
74HOO
80-460-35
XE1
7402
80-460-62
XB4,XF1, XF3, XF6,
7404
80-460-18
XCS, XF4
7406
80-460-73
XD1, XES, XF2
7410
80-460-19
XD3
7420
80-460-17
XE4
7442
80-460-31
XC3
74}4
80-460-34
XA1
74H74
80-460-77
XC2,XD6.
7492
80-461-15
XFS
74L02
80-460-t67
XBS, XC4
74107
80-460-46
XA6
74121
80-460-94
XB3,XD5
74160
80-460-76
XC1,XD1,XE6,
XB2
74161
80-460-58
XE3
74175
80-460-64
·80-311-55
~4
RESISTORS
R3
27oQ,5\ 1/4W
80-212-71
R4-RlO,Rl2-R18
2.7K,S\ 1/4W
80-212-72
Rl1
4.7K,5\ 1/4W
80-214-72
R2
10K,S' 1/4W
80-211-03
Rl
15K,S' 1/4W
80-211-53
9-16
COMPONENT PARTS LIST
SECTION 9
'
.. -
TIMING CONTROL CARD
~.
"
DES •
ASSEMBLY 99-452-01C
t
DESCRIPTION
1
OMRON PIN
.Yl
Crystal, 29.952 MHZ
80-967-93
CRl
Diode, IN914
80-404-03
Ejector
40-109-04
Ll
Inductor, 2.2UH
80-501-40
Ql,Q2
Transistor, 2N3904
80-422-11
-
9-17
COMPONENT PARTS LIST
SECTION 9
VIDEO CONTROL CARD
REF. DES.
ASSEMBLY 99-454-0LA
IDESCRIPTION
OMRON PIN
CAPACITORS
C4-C15
.01MF,10OV,10\, Cer. Disc.
80-320-93
C1-C3
150MF, 15V, Tant
80-311-55
CHARACTER GENERAL
A2,A4
ROM Lower Case
A2
Upper Case (PROM)
22-003-035
22-012-07
DIODES
CR4
IN752A
80-404-12
CR3
IN914/IN4148
80-404-03
INTEGRATED CIRCUITS
XD3,XD5,XE6
7400N
80-460-22
XE3
7402N
80-460-62
XD1,XE1
7403N
80-460-59
XB6,XD2,XE5
7404N
80-460-18
·XC3
7410N
80-460-19
XD4
7420N
80-460-17
XC5,XC6
7427N
80-460-61
XE4
74H74N
80-460-77
XE2
7486N
80-460-54
XB2
74166N
80-460-63
XC4,XD6
74175N
80-460-64
XC2
74HOON
80-460-35
XB4,XB5
7408N
80-460-50
XB3
7432N
80-461-54
9-18
COMPONENT PARTS LIST
SECTION 9
ASSEMBLY 99-4S4-01A
VIDEO CONTROL CARD
REF. DES.
I
I
DESCRIPTION
OMRON PIN
RESISTORS
Rl6
lofl,1/4W,S\
80-211-00
Rl8
27ofl,1/4W, 5%
80-212-71
Rl7
33ofl,1/4W, S%
80-213-02
R3S,R36
1IOl,1/4W, S\
80-211-02
Rl3, Rl9
56ofl,1/4W, S\
80-21S-61
R34
2.7K,1/4W, 5\
80-212-72
R20
1. 5K,1/4W, 5\
80-211;"52
Ejector
40-103-02
XAI
Resistor Pack, 1K,760-1-1K-13
80-290-60
J22
Socket, (16 Pin Dip)
80-676-04
Socket, 24 Pin Dip
80-675-11
Transistor 2N4401
80-419-01
Q3
-
,
9-19
REFERENCES
SECTION 10
EIA STANDARD RS-232C
10.1
The EIA standard RS-232C*ensures equipment compatability and interchangeability between vendors by defining the electrical and mechanical interface between
the modem and the data terminal. Specifically, the standard sets the minimum voltage (5 volts) and the maximum (15 'volts) that can be present at the interface. It
also establishes the "handshaking" routine and timing.
Table 10-1 shows the re~ationship between pin numbers, direction of signal
flow, RS-232C nomenclature, and Bell Telephone nomenclature,.
Circuit descriptions for the RS-232C nomenclature in Table 10-1 follow.
10.1.1 .
Transmit Data (BA) , Pin 2
Data from the terminal is transmitted to the remote end.
a "mark" (negative VOltage) between characters.
~0.1.
2
Line is held at
Receive Data (BB), Pin 3
Data from the remote end comes through the modem to the terminal.
held at a mark between characters.
lQ.1.3
Line is
Request to Send (CA) , Pin 4
A si~al from the terminal tells the modem that it wants to transmit data.
This signal allows the modem to prepare for data transmission by turning on the
carrier, if necessary, allowing the carrier to stabilize, and permitting the remote carrrer to·synchronize.
10.1. 4
Clear to
S~nd
(CB), Pin 5
A signal from the modern in response to CA indicates that it is ready to
receive data. Various CB delays and options are available to permit the modern to
perform different functions.
10.1.5
Data Set Ready (CC), Pin 6
Interlock to terminal indicates that the modem is in an operational state.
The terminal should never try to pass data if this signal is absent.
10.1. 6
Recei ved Line Signal Detector (CF), Pin 8
This signal indicates that the local modem/is receIVIng a carrier from the
remote modem. The terminal should not read Receive Data line unless CF is present.
10.1. 7
Data Terminal Ready (CD), Pin 20
A signal from the terminal activates the modem. It is gonerally impossible to pass data in either direction without this signal.
* "Interface Between Data Terminal Equipment and Data Communication Equipment Employing Serial Binary Data Interchange"
10-1
REFERENCES·
SECTION 10
10.1. 8
Ring Indicator (CEJ. Pin· 22
.
This signal is used in conjunction with auto-answer options. The local
modem uses it to indicate that a ringing signal was received from the remote modem.
This line may be used with special purpose peripherals for other purposes.
Table lO-l.
--
...
~
....
~
~
..
~
6
(CC)
....
7
8
.
9
10
....
....
11
12
13
~
14
Z
H
&
~
15
16
17
18
.-
~
(BA)
(BB)
5
a.-
-
(M)
(CA)
(CB)
.....
~
1
2
3
4
.....
..
1-1
0
RS-232C
NOMENCLATURE
PIN
NO.
SIGNAL
FLOW
-
RS-232C pin number-signal flow-nomenclature relationship
..
....
Protective Ground
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
Signal Ground
(CF) Recei ved Line
Signal Detector
Reserved--Modem Testing
Reserved--Modem Testing
Unassigned
(SCF) Secondary Receive
Line Signal Detect
(SCS) Secondary Clear to
Send
(SBA) Secondary Transmit Data
(AB)
. (DB)
(IT)
(SG)
(CO)
Interlock
Signal Ground
Carrier On
(+12V) Positive Battery
(-12V) Negative Battery
Not Used
Not Used
Not Used
(NS)
New Sync
(SCR) Serial Clock
Receiver
(OCR) Debit Clock
Receiver
(RR)
Remote Re lease
Recei ver Signal
Element Timing
Unassigned
(CD)
25
(SR)
(CS)
(DO)
20
24
(RO)
Frame Ground
Send Data
Recei ve Data
Send Request
Clear to Send
(SCT) Serial Clock
Transmitter
(OCT) Debit Clock
Transmitter
(SCA) Secondary Request
to Send
22
23
(FG)
(SO)
Transmitter Signal
Element Timing
(SBB)*Secondary Receive
Data
19
21
BELL TELEPHONE
NOMENCLATURE
Data Terminal
Ready
(CG) Signal Quality
Detector
(CE)
Ring Indicator
(CH/CI) Data Signal Rate
Selector
COA) Transmitter Signal
Element Timing
Unassigned
(RC)
Remote Control
(ROY)
Ready
(RG1) Ring Indicator
(RG2) Ring Indicator
(SCTE) Serial Clock Transmitter External
Not Used
*Oata Access Arrangement (Bell Telephone)
10-2
REFERENCES
SECI'ION 10
10.2
ISO CHARACTER ASSIGNMENTS
This paragraph provides ISO (International Standard Organization) code and
character assignments for information interchange. Contained within the ISO code
are the ASCII (American Standard Code for lnformation Interchange) character assignments.
10.2.1
Mnemonics and Their Definitions
Table 10-2 defines the mnemonics used in conjunction with the ISO and ASCII
codes.
Table 10-2. ISO/ASCII mnemonics and their definitions
ANSI
ECMA
ALTERNATE
3-ClIARACTER
MNEMONIC
MNEMONIC-IF
CONTROL
2-ClIARACTER
DEFINITION
DIFFERENT
7-BIT CODE
MNEMONIC
8-BIT CODE
ACK
BEL
BS
CAN
(AK)
(BL)
(an
CR
DCl
DC2
DC3
DC4
(01)
(02)
(03)
(04)
(OT)
DEL
DLE
EM
ENQ
(EQ)
EOT
ESC
(ET)
(EC)
.
CD
CI
CIF
CIN
CLC
EEL
esc
EED
DCL
ICL
-
COL)
EO
ESI
ESO
ETB
ETX
FF
(EB)
(EX)
FS
GS
RPM
FHL
RHL
APM
HF
HLF
HLR
HN
HT
HTC
HTS
LCF
LCN
10-3
Acknowledge
Bell
Backspace
Cancel
Character Delete
Character Insert
Character Insert Off
Character Insert On
Clear Line from Cursor
Carriage Return
Clear Screen from Cursor
Device Control 1
Device Control 2
Device Control 3
Device Control 4
Delete
Data Link Escape
End of Medium
Enquiry
Eight Ones
End of Transmission
Escape
Extended Shift In
Extended Shift Out
End of Transmission Block
End of Text
Form Feed
File Separator
Group Separator
Highlight Off
Half Line Feed
Half Line Reverse Feed
Highlight On
Horizontal Tab
Horizontal Tab Clear
Horizontal Tab Set
Local Copy Off-full duplex
Local Copy On-half duplex
REFERENCES
SECTION 10
"able 10-2.
3-CliARAC'l'E R
CONTROL
7-BIT CODE
ISO/ASCII mnemoni cs and thei r defini dons (cont' d)
ALTERNATE
2-CHARACTER
MNEMJNIC
ANSI
MNEMONIC
8-BIT CODE
ECMA
MNEMJNIC-IF
DIFFERENT
LD
DL
L1
IL
LF
NAK
(NK)
NUL
(NU)
NP
PO
PFF
PFN
PH
PL
PM
PP
PR
PT
PU
RLF
CUO
CUH
CUB
CUF
CUU
RS
SO
S1
SO
SOH
SP
STX
(SH)
(SX)
SU
SUB
SYN
US
(SB)
(SY)
VT
VTC
VTS
10.2.2
DEFINITION
Line Delete
Line Feed
Line Insert
Negative Acknowledge
Next Page
Null
Cursor (Pointer) Down
Protect Fo~at Off
Protect Fo~at On
Cursor (Pointer) Home
Cursor (Pointer) Left
Cursor (Pointer) Return
Previous Page
CUrsor (Pointer) Right
Cursor (Pointer) Tab
CUrsor (Pointer) Up
Reverse Line Feed
Record Separator
Scroll Down
Shift In
Shift Out
Start of Heading
Space (a blank)
Start of Text
Scroll up
Substitute
Synchronous Idle
Unit Separator
Vertical Tab
Vertical Tab Clear
Vertical Tab Set
.
The ASCI I Code
Table 10-3 defines the ISO code that incorporates the ASCII code. Columns
2 through 5 define the ASCII 64-character set, 2 through 7 the ASCII 96-character set,
and 2 through 9 the ASCII l28-character set.
10-14
.,
SECTION 10
REFERENCES
10.2.3
Tape Track Assignments
Track Assignments for 25.40 DUn (1 inch) punched paper tape and 12.70 m
(0.5 inch magnetic tape as related to serial transmission of the ISO and ASCII codes
as shown in Figure 10-1.
r,-,t ·f. t 1, f f f
5 • , • 1J
Even Parlty--J
Odd
P~ri
tYt!l'
r r r r l' r II
"76539
1
----------
8
2]
Track of 8-track
Paper Tape
Channel of 9-track
Magnetic Tape
Obi is first bit sent In serial transmission,
then b2, etc. to b', (b,l. then pilrlty.
Figure 10-1.
Tape track assignments for ISO/ASCII codes.
Notes for Table 10-3.
1.
Columns 2 through 7 - These 12 positions are variable--2 for currency, 7 for
primary national usage, and 3 for secondary usage which'are diacritical marks
used for alphabetical extension when preceded by BS. Positions 2/7 and 2/12
are invariant but also serve as diacritical marks. Presently known assignments
are given in Table E-3, Page E-7.
2.
Columns 2 through 5 - Define the ASCII 64-Character set.
3.
Columns 2 through 7 - Define the ASCII 96-character set.
4.
Columns 2 through 9 - Define the ASCII 128-character set.
S.
Columns 4 and 5 - (ESC.) (CHAR.)
6.
Columns 4 through 9 - Soft Copy
7.
Columns 8 and 9 - (SINGLE CHAR.)
8.
Columns 8 through 15 - JSCII (Japanese Industrial Standard Code for Information
InterChange) is an 8-bit code consisting of the ISO characters plus the Kata
Kana characters shown in upper row positions of Columns 10-13. (Columns 8 and 9
are reserved for additional controls. and 14 and 15 for additional graphics.)
Contro~s.
..
GOST 13052.67 defines the USSR set shown in lower row entry positions of Columns
12~lS.
Tho standard .defines
these char.~tera
for Gplumns 4~7 of a 7-bit set
: '
..
*."
~.
>".
•
, .
REFERENCES
SECI'rON 10
(SO • Russian register, SI = Latin register).
Columns
8-11
are identical to
0-3.
9.
10.
Columns 3 through 7 - Alternate controls in these 5 cqlumns are achieved by
preceding a regular character with an ESCape.
Hollerith card code for 256 characters
12
11
8
0
9
= 256] is constructed
1 or 2 or 3 ••• or 7 or blank
(no punch).
[8 x 32 (2 5 )
!!!E!
any combination of 12, 11, 0,
8 and 9 (from none to all).
For historical reasons, assignments present little in the way of a regular
pattern, but they are the key for translation to and from IBM EBCDIC.
___ .... 180_
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13
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r-:.-
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t.
:
•
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ISO Code
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