900064D_930_Reference_Feb66 900064D 930 Reference Feb66

900064D_930_Reference_Feb66 900064D_930_Reference_Feb66

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TRAINING GROUP FilE COpy
FROf-EBT\' GF SD ~
TRAINING DEPT.

Sil

ItS

SCIENTIFIC DATA SYSTEMS

Reference Manual

SDS 930 BASIC INSTRUCTIONS
Page

Mnemanic

Octal Code

Name

.w.

CENTRAL PROCESSOR

A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T

35
36
37
62
71
75
76
77

Store A
Store B
Store Index
Exchange M and A
Load Index
Load B
Load A
Copy Effective Address
into index

54
55
56
57
61
63
64
65

Subtract M from A
AddMtoA
Subtract with Carry
Add with Carry
Memory Increment
Add A to M
Multiply
Divide

10
9
10
9
9
9
10

14
16
17

Extract
Merge
Exclusive Or

11
11
11

8
8
8
9
8
8
8
8

ARITHMETIC
SUB
ADD
SUC
ADC
MIN
ADM
MUL
DIV

A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T

11

LOGICAL
ETR A, T
MRG A, T
EOR A, T

REGISTER CHANGE
CLA
CLB
CAB
CBA
XAB
CBX
CXB
XXB
STE
LDE
XEE
CXA
CAX
XXA
CNA
BAC
ABC
CLR
CLX

04600001
04600002
04600004
04600010
04600014
04600020
04600040
04600060
04600122
04600140
04600160
04600200
04600400
04600600
04601000
04600012
04600005
04600003
24600000

Octal Code

Name

Page
Ref.

BRANCH

LOAD, STORE
STA
STB
STX
XMA
lOX
LDB
LDA
EAX

Mnemonic

BRU
BRX
BRM
BRR

A, T
A, T
A, T
A, T

01
41
43
51

Branch Unconditionally
Increment Index & Branch
Mark Place & Branch
Return Branch

14
14
15
15

Skip if Signal Not Set
Skip if A Equa Is M
Skip if M and B Do Not Compare Ones
Skip if M Negative
Reduce M, Skip if < 0
Skip if A = M on B Mask
Skip if M and A Do Not Compare Ones
Skip if A Greater Than M
Difference Exponents; Skip

27
15
16
16
16
15
16
15
16

TEST/SKIP
SKS
SKE
SKB
SKN
SKR
SKM
SKA
SKG
SKD

A
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T

40
50
52
53
60
70
72
73
74

SHIFT
LRSH
RSH
RCY
LSH
LCY
NOD

N, T
N, T
N, T
N, T
N, T
N, T

06624XXX Logical Right Shift AB
06600XXX Right Shift AB
06620XXX Right Cycle AB
06700XXX Left Shift AB
06720XXX Left Cycle AB
06710XXX Normalize; Decrement X

17
17
17
18
18
18

00
20
23

18
19
19

CONTROL
HLT
NOP
EXU A, T

Halt
No Operation
Execute

BREAKPOINT TESTS
Clear A
Clear B
Copy A into B
Copy B into A
Exchange A and B
Copy B into Index
Copy Index into B
Exchange Index and B
Store Exponent
Load "Exponent
Exchange Exponents
Copy Index into A
Copy A into Index
Exchange Index and A
Copy Negative into A
Copy B into A, Clear B
Copy A into B, Clear A
Clear AB
Clear X

12
12
12
12
12
13
13
13
i3
14
14
13
13
13
14
13
13
12
13

BPT
BPT
BPT
BPT

4
3
2
1

OVERFLOW
ROV
REO
OVT

04020040
04020100
04020200
04020400

Breakpoint
Breakpoint
Breakpoi.[lt
Breakpoint

00220001
00220010
04020001

Reset Overflow
Record Exponent Overflow
Overflow Test; Reset

19
18
19

= address;

*A

= indirect address;

Test
Test
Test
Test

00220002
00220004
00220020
04020002
04020004

Enab Ie Interrupts
Disable Interrupts
Arm Interrupts
Interrupt Disabled Test
Interrupt Enabled Test

23
23
23
23
23

Set Extension Register
Extension Register Test

19
20

19
19
19
19

INTERRUPT
EIR
DIR
AIR
!DT
lET

MEMORY EXTENSION
006200SR
0404000T

Legend:
A

No.4
No.3
No. 2
No. 1

T = tag field; N

= number of shifts

SOS 930 INPUT/OUTPUT INSTRUCTIONS
Mnemonic

Octal Code

Name

Page
Ref.

INPUT/OUTPUT INSTRUCTIONS

02
06

MrN
MIY
PIN
POT
WIM
YIM

A, T
A, T
A, T
A, T
A,T
A,T

12
10
33
13
32
30

Energize Output M
Energize Output to Direct Access
Channel
Memory into W when Empty
Memory into Y when Empty
Parallel Input
Parallel Output
W into Memory when Full
Y into MemQry when Full

38
39
41
41
39
39

00250000
00200000
002 14000
04020010
04020020
04021000
04022000
002 12000
040 14000
04011000
040 10400
040 12000

Alert Channel
Disconnect Channel
Terminate Output
Buffer Error Test W
Buffer Error Test Y
Buffer Ready Test W
Buffer Ready Test Y
Alert to Store Address
Channel Active Test; Skip if Inactive
Channel Error Test; Skip if no Error
Channel Inter-Record Test
Channel OCount Test; Skip if Count=O

33
33
33
37
37
37
37
33
37
37
38
38

26
27

CHANNEL
ALC
DSC
TOP
BET
BET
BRT
BRT
ASC
CAT
CET
CIT
CZT

C
C
C
W
Y
W
Y
C
C
C
C
C

PERIPHERAL DEVICE INSTRUCTIONS AND TESTS
Octal Codes given are for the W Channel, device number 0 (bits 2123), and 4 character/word mode (bits 15, 16).

C,U,CC 00202604
C,U,CC 00200644
C,U,CC 00202644

Read Paper Tape
Punch Paper Tape, Leader
Punch Paper Tape, No Leader

49
49
49

CARD
CRT
FCT
RCD
RCB

C,U
C,U
C,U,CC
C,U,CC
eFT C,U
SRC C,U
CPT C,U
PBT C,U
PCD C,U,CC
PCB C,U,CC

Page
Ref.

TRT
FPT
BTT
TGT
ETT
DT2
DT5
DT8
TFT

C,U
C,U
C,U
C
C,U
C,U
C,U
C,U
C

040 10410
04014010
04012010
04012610

040 11010
040 16210
04016610
04017210

040 13610
040 10210
RTD C,U,CC 00202610
RTB C,U,CC 00203610
RTS C
002 14000
00213610
SRR C
SFD C,U,CC 00202630
SFB C,U,CC 00203630
SRD C,U,CC 00206630
SRB C,U,CC 00207630
WTD <;,U,CC 00202650
WTB C,U,CC 00203650
EFT C,U,CC 00203670
ERT C,U,CC 00207670
002 14010
REW C,U

Tape Ready Test
File Protect Test
Beginning of Tape Test
Tape Gap Test
End of Tape Test
Density Test, 200 BPI
Density Test, 556 BPI
Density Test, 800 BPI
Tape EOF Test
MAGPAK Test
Read Tape Decimal (BCD)
Read Tape Binary
Convert READ to Scan
Sk ip Remainder of Record
Scan Forward Decimal (BCD)
Scan Forward Binary
Scan Reverse Decimal (BCD)
Scan Reverse Binary
Write Tape Decimal (BCD)
Write Tape Binary
Erase Forward Tape
Erase Reverse Tape
Rewind

57
57
57
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58

Pri nter Ready Test
End of Page Test
Pri nter Fau ItT est
Print Off-Line
Printer Skip to Channel N
Printer Space N Lines
Print Line Printer

63
63
63
63
63
63
63

Read Keyboard
Write Typewriter

46
46

LINE PRINTER
PRT
EPT
PFT
POL
PSC
PSP
PLP

C,U
C,U
C,U
C,U
C,U,N
C,U,N
C,U,CC

040 12060
04014060
04011060
002 10260
002 lN460
0021N660
00202660

TYPEWRITER

PAPER TAPE
RPT
PTL
PPT

Name

MAGNETIC TAPE

GENERAL
EOM A
EOD A

Octal Code

Mnemonic

040 12006
040 14006
00202606
00203606
04011006

002 12006
04014046
04012046

00202646
00203646

Card Reader Ready Test
First Column Test
Read Card Decimal (Hollerith)
Read Card Binary
Card Reader EOF Test
Skip Remainder of Card
Card Punch Ready Test
Punch Buffer Test
Punch Card Decimal (Hollerith)
Punch Card Binary

53
53
53
.53
53
53
53
53
53
53

RKB
TYP

C,U,CC 00202601
C,U,CC 00202641

OCTAL CODE CHANNEL SELECTION
Channel

EOM (02)

SKS (40)

W
Y
C
D
E
F
G
H

00000000
00000100
20000000
20000100
00400000
00400100
20400000
20400100

00000000
00000100
20000000
20000100
00040000
00040100
20040000
20040100

Add the appropriate entry to the octal code to select the channel.
Example: PCD (i. e., 00202646) for channel G is 20602646.

Legend:
A=address; T = tag field; C = channel number; U = unit number; CC = character/word count; N = number.

Price:

$2.50

SOS 930 COMPUTER
REFERENCE MANUAL

February 1966

&1'·1&
SCIENTIFIC DATA SYSTEMS/1649 Seventeenth Street/Santa Monica, CaHfornia/(213)UP1-0960

Printed in U.S.A.

@1965. 1966

Scientific Data Systems, Inc.

REVISIONS

This publication, SDS 9000 64D, dated February 1966, is

a

revision of the SDS 930

Computer Reference Manual, SDS 9000 64C. Changes to the previous manual are
indicated by a vertical Iine in the margin of the page.

RELATED PUBLICATIONS .

ii

Title of Manual

Publication
Number

SDS ALGOL 60 Reference

900699

SDS 900 Series FORTRAN II Reference

900003

SDS 900 Series FORTRAN II Operations

900587

SDS MONARCH Reference

900566

SDS SYMBOL and META-SYMBOL Reference

900506

SDS 920/930 Programmed Operators Technical

900020

SDS 930 Computer EXAMINER Diagnostic System Technical

900097

SDS 900 Series Utility and Debug Package (AID)

01 20 13

SDS Project Management System Reference

900818

SDS SORT/MERGE Reference

900997

SDS Business Language Reference

90 1022

CONTENTS

I.

IV.

GENERAL DESCRIPTION . . . . . . . . • . . .
Introduction . . . . . . . . . . . . . . . . . • .
SDS 930 Registers. . . . . . .
SDS 930 Memory . . . . . . . . . . . . . • .
Memory Word Formots .. . . . . . . . . • .
Special Characteristics .. . . . . . • • . . . ..

II.

MACHINE INSTRUCTIONS

......•...•..

(Continued)
Peripheral Equipment Description

3
4
4
6

.•....

49

Paper Tape Input/Output • • . • . . . . . •.
Card Input/Output . • . . . . . . . . . . .
Magnetic Tape Input/Output . . • . . .
Line Printer . . . • . . . . . • . • .

49
52
56
62

8

APPENDICES
Introduction . . . . . . . . • . . . . . . . . . . .. 8
8
Load/Store Instructions . . . . .
9
Arithmetic Instructions
11
Logical Instructions . . • . . . .
12
Register Change Instructions
14
Branch Instructions . . . . . . . . . . . . . .
15
Test and Skip Instructians
17
Shift Instructions . . . . . . .
Control Instructions . . . . . . . . . . . . . . . 18
Breakpoint Tests . . . . . . . . . .
19
19
Overflow Instructions . . . . . .
19
Memory Extension Instructions .
Floating Point Operations ..
.20
III.

INTERRUPT SYSTEM . . . . . . .

. 21

Priority Interrupt System. . . . .
.
Priority Interrupt Operations. . . .
.
Interrupt Control. . . . . . . . . . . .
.
Non-Interruptable Instructions . . . . . . . . . .
Enable/Disable Interrupt Instructions . . . . .
Arming Feature (Optional) . . . . . . . . . . . .
Channel Interrupt Designations . . . . . . . . .
End -of-Word/End -of-Transmission Interrupt
Operations; Compatible Mode. .
.
Count Equals Zero/End-of-Record;
Extended Mode . . . . . . . . . . .
.
IV.

INPUT/OUTPUT INSTRUCTIONS . . .

SDS Character Codes . . . . . . . . . . . . . . . . .
Table of Powers of Two . . . . . . . . . . . . . . .
Octal-Decimal Integer Conversion Tobie
.•
Octal-Decimal Fraction Conversion Table
.
Two's Complement Arithmetic . . • • . . . . . . . .
Optional Equipment . . . . . . . . . . . . . . . • . .
Data Multiplexing System . . . . . . • . • . . . .
Memory Interface Connection . . . . • . . . • . .
Automatic Power Fail-Safe
.......•....
Memory Parity Interrupts . . . . . . . . . • . . . .
Real-Time Clock . . . . . . . . .
. .....
Programmed Operator Instructions
.•....
Channel Memory Access Priority
..•..
Division Instruction . . . . . . . . . . . . . . . . • .
Instruction List - Functional Categories
..
Instruction List - Numerical Order
..
Instruction List - Alphabeti cal Order . . . . . . .

21
21
22
22
22
23
24

A-I
A-2
A-3
A-7
A-I0
A-II
A-II
A-15
A-15
A-15
A-16
A-17
A-19
A-19
A-20
A-25
A-29

FIGURES

24.
24

. .. 25

Introduction . . . . . . . . . . . . . .
. .. 25
Direct Memory Access System
. . . . . 26
Primary Input/Output Instructions
. . . . . 26
Communication Channel Input/Output
.28
Communication Channel EOM . . . . . . . . . 31
Standard EOM/EOD Instructions . . . . . . . 33
Compatible/Extended Input/Output Modes
34
Input/Output Class EOM/EOD . . . .
34
Termina I Functions; Extended Mode .
35
Channel ond Device SKS . . . . . .
37
Single-Word Data Transfer Via
Channels Wand Y . . . . . . . . .
38
Direct Parallel Input/Output Instructions . . . 41
Single-Bit Input/Output . . . . . . . .
41
Communication Channel Programming
42
Control Console . . . . . . . . . . . . . .
44

1-1
1-2
4-1
4-2
4-3
4-4
4-5
A-I

SDS 930 Computer (Frontispiece) . . . . . . . . . . iv
SDS 930 Computer Configuration . . . . . . . . . . 2
3
Basic Register Flow Diagram . . . . . . . . . . . .
SDS 930 Time-Multiplexed Communication
Channel, Block Diagram . . . . . . . . .
29
SDS 930 Direct Access Communication
Channel, Block Diagram . • . . . . . . .
30
45
SDS 930 Computer Control Panel . . . . . . .
Card Read Into Memory in Hollerith . . . . .
52
Printer Control Indicator Lights and Switches .. 62
SDS 930 Computer Overall Configuration. .. A-12

TABLES

3-1
4-1
4-2

Interrupt Location Assignments
Unit Address Codes . . . . . . .
Format Control Characters .. .

22
32
65

iii

t
r ......... .::. ':-.

5DS 930 Computer

iv

I. GENERAL DESCRIPTION
INTRODUCTION

•

Optional powerfail-safe feature permits saving contents
of memory and programmable registers in case of power
fai lure.

•

Up to four I/O communication channels (with optional
interlacing capability), time-multiplexed with computer operation, providing input/output rates of up to
one word per 3.5 microseconds

•

An optional Direct Memory Access System that allows
input/output transfer to occur simultaneously with
computer memory access, providing input/output rates
of up to one word per 1.75 microseconds

•

One to four Direct Access Communication Channels
that incorporate the Direct Memory Access System

•

Data Multiplex Channel that uses direct memory access
connection and accepts/transmits information from external devices, or subchannels, which may operate
simultaneously; thus, externally controlled and sequenced equipment may perform input/output buffering
and control operotions rather than the computer.

•

Time-Multiplexed Input/Output Channels operate upon
either words or characters. A 6-bit character is the
standard character size; 6- and 12-bit characters, or
6-, 12-, and 24-bit characters can be specified as desired. Direct Access Channels operate upon words and
characters. These channels accept 6-, 8-, 12-, and
24-bit characters. The number of characters per word
is specified by the external device.

•

Input/output with Scatter-Read and Gather-Write
facility

•

Standard input/output

The SDS 930 is a high-speed, low-cost, general-purpose digital computer with the following characteristics:
•

24-bit word plus parity bit

•

Binary arithmetic

•

Single address instructions with
Index Register
Indirect Addressing
Programmed Operators

•

Basic core memory 4,096 words, expandable to 32,768
words, all addressable with
0.7 microsecond access time
1.75 microsecond cycle time

•

Memory overlap between Central Processor and I/O
with two memory banks

•

Memory available in 4, 8, and 16 K banks

•

Multi-precision programming facility

•

Typical execution .times (including memory access and
indexing)
Fixed-Point Operations (in microseconds)
Add
Multiply

3.5
7.0

Floating-Point Operations (in microseconds)
Time-Multiplexed Communication Channel (without
interlace)

24-bit Fraction
39-bit Fraction
(plus 9-bit Exponent) (plus9-bit Exponent)
Add
Multiply

77
54

92
147

•

Program interchangeabi I ity with other SDS 900 Series
Computers

•

Parity checking of all memory and input/output
operations

•

Pri ori ty Interrupt System

Control Console
•

Optional input/output devices
Automatic typewriter
Photoelectric paper-tape reader and paper-tape punch,
and spooler mounted on cart
MAGPAK Magnetic Tape System
Magnetic-tape units (IBM-compatible; binary and
BCD)
Punched-card equipment

SDS I/O Options Interrupts 2 levels standard,
38 optional
System Interrupts, 896 optional

Line printers, graph plotters
Typewriter with electromechan ica I paper-tape reader
ond punch, auxi liary disc fi les

Up to 896 System Priority Interrupts

I I
I
I I··· •••. • •.•• I
EOM

Operands
SDS 930

SKS

Computer

Instructions

Core

Time-

Memory

4096 words
expandable to
32K

Multiplexed
I/O

POT/PIN

I Second Memory Path
I
(Optional)
I

24-bit Word
Parallel

I
I

Y
Time-Multiplexed
Communi cati on
Channels

E, F, G, H

I
I

\
\

I Data Multiplex System
I
I
I
I

Direct Access
Communication
Channels

\
\

GS~~

I

See Appendix A-II for complete
description of Data Multiplex System

* W-Buffer

Standard;
W Channel optional

Figure 1-1.

2

I

Subchannels

SDS 930 Computer Configuration

The P Register is a 14-bit register that contains the memory
address of the current instruction. Unless modified by the program, the contents of P increase by one at the completion of
each instruction.

Communications equipment, teletype consoles, display oscilloscopes
A/D converters, digital multiplexer equipment, and
other special system equipment
•

FORTRAN II and symbolic assembler as part of complete
. software package

•

All-silicon semiconductors

•

Operating temperature range: 100 to 40°C

•

Dimensions: 124 inches x 25-1/2 inches x 65 inches

•

Power: 3 kva

The Memory Extension Registers, EM3 and EM2, are 3-bit regi-I
sters that specify the portion of extended memory being used .
NOT AVAILABLE TO THE PROGRAMMER (see Fig. 1-2, light
lines)
The S Register is a 14-bit register that contains the address of
the memory location to be accessed for instructions or data.
The address is augmented by one of the Memory Extension
Registers.

SOS 930 REGISTERS
The 930 Central Processor contains the following arithmetic
and control registers. They are full-word, 24-bit registers except as noted.
AVAILABLE TO THE PROGRAMMER (see Fig. 1-2, dark lines)

The C Register is an arithmetic and control register used in
multiply, divide, and other operations. All instructions come
from memory to the C Register before decoding. Address modification and parity generation/detection take place in the
C Register.

The A Register is the main accumulator of the computer. The
B Register is an extension of the A Register. The B Register
contains the less significant portion of double-length numbers.

The 0 Register is a 6-bit register that contains the instruction
code of the instruction being executed.

The Index Register, X, used in address modification, is a fullword register. Indexing operations occur only with the least
significant 14 bits.

The M Register is a 24-bit register that holds each word as it
comes from memory. Recopying of a word into memory takes
place from the M Register.

A Register
(Main Accumulator)'

B Register

X Register

(Extended Accumulator)

(Index)

•

•

0
Reg.
(Instruction)

P Register

C Register

M Register

(Program Counter)

(Arithmetic and Control)

(Memory Access)

S Register
(Memory Address) r---------~-----------

EM3

Memory

EM2

Figure 1-2.

Basic Register Flow Diagram

.3

SOS 930 MEMORY

Example 2.

EM3 setting is 5; EM2 setting is 7:

ADD 34000 yields

Core memory is expandable from 4,09.6 to 32,768 words. Word'
length is 2:4 bits plus parity.
addressfield i~ the instruction
format is 14 bits long, allowing direct access of up to 16,384
words. The Memory Extension System provides direct access to
the total 32,768 words.

The

Memory isavailable in 4,096-, 8, 192~, and 16,384-word banks.
As an optional feature, if a power loss is detected, the computer 'may be interrupted and the transient, programmable registers stored to provide complete fail-safe capability. With this
option, power failure causes no loss of information.
Even parity is automatically generated or checked during each
read/write cycle. A control panel switch may be set to halt the
computer automatically in case of parity error detection.
The memory iscyclic, or "wrap-around", for each 16,384 words
being addressed. An attempt to access from a location whose address is greater than that avai lable resu Its inan access of a II zeros.
An attempt to store i nto ~uch a location results in a "no-op" oper'ation, with the next instruction in sequence being executed.
MEMORY EXTENSION SYSTEM
The Memory Extension System, containing two memory extension
registers, allows addressing of memories greater than 16,384
words. The program loads either or both of the Extend Memory
Registers and activates them as desired. Each register contains
3 bits, or one octal digit, that can become the most significant,
or fifth, digit of any operand address.
EM3

EM2

ITO

[IIJ

012

The program always addresses the first 8,192 words of core,
00000-17777, directly without regard to the Extend Memory
Registers. Whenever the operator initia Iizes the computer
(presses START), the computer presets a 3 in EM3 and a 2 in
EM2. This allows the programmer to address the first 16,384
words of core, 00000-37777, without being concerned with the
extension system.
Example 1. By previously setting EM2 to 4, the program adds
the contents of location 43300 to the A Register by executing
ADD 23300. The "2" calls for register EM2:

(EM2)
"ADD 43300" ..

4

2

3300

1

"ADD 54000" •

i~54000I

When (EM3) 13, the computer lights theEM31ight on the control
panel. When (EM2) 12, the computer lights the EM21ight on the
control panel. When executing the MARK PLACE AND BRANCH
(BRM) instruction, the computer' records the contents of EM3, EM2,
and the Overflow Indicator in the mark location. BRM stores
overflow in bitO of the mark; it stores the contents of EM3 in
bits 3 through 5 and the contents of EM2 in bits 6 through 8.
Bits 1 and 2 are unpredictable; bit 9 is zero.
Memory Write Lock-Out Feoture (Optional)
Permanent memory protection for selected areas of memory in
the SDS 930 Computer is provided/by a memory lock-out feature, which is controlled either manually by switches or by the
program with a lock-out register, protects the contents of
memory from inadvertent d!lstruction by operating pr6groms.
The entire memory isdivided into 2048 word blocks. This first
block, from 0000 to 2047, is furtherdivided intofour subblocks
of 512 words each. Each of these blocks can be individually
protected by turning on the appropriate switch with the manualcontrolled option or placing a one in the appropriate position
of the lock-out register with the program-controlled option.
Read operationsarealways allowed, but if a program or I/O channel attempts to store or write intoa protected block of memory, an
internal interrupt occurs to octal location 35. The memory cell
referenced is not altered. Therefore, not only is memory protected, but ,also the supervisory program is notified that an attempt to write into an interlocked area has occurred.

MEMORY WORD FORMATS

012

The program uses the first extension register, EM3, by calling
for an address with aI, 1 in the mo;t and next most significant
address bits, respectively (a "3" for the most significant octal
digit). The program calls for EM2, the second extension register, by setting the same two address bits to 1,0 (a "2" for the
most significant octal digit). Via memory extension instructions,
the program can set each of the registers to a desired "5th
digit" and can test the current setting of each register. Once
set, the contents of either register remain set until changed by
program or by pressing the S TART button.

ADD 23300 yields

(EM3)

4000

3

I

~43300

A computer word is 24 binary digits (bits) long.

Io

1111111

1I111111111111111

1 2 - - - - - - - - - - - - - - - - - - - - 23
00
01
02
03
04
05
06
07
The format above numbers the bits from the left, or most significant end of the word, to the right, or least significant end
of the word. This numbering format is the basis of references
to bit positions or bit numbers. Octal notation most easily describes the contents of the 24 bits of'a word. Thus, one octal
digit, 0 through 7, represents three binary digits. For example,
the octal number, 01234567, represents its binary equivalent,
000001 010011 100 101 110 Ill.
The computer instruction word format is:

IRIX II~struction Code II I
012
00

I
01

8910
02
03

Address Field

I
04

I
05

06

23
07

Bit position 0 contains the Relative Address Bit. Standard loading programs use this bit; central processor decoding logic does
not use or sense th is bi t. A l-bi t (octlaces to be shifted. Shift timing is:

LRSH

o

1 2 3

This instruction may perform scaling of floating-point
numbers by use of indexing, where the difference of
exponents is in the Index Register as positive quantity.
LOGICAL RIGHT SHIFT AB
66
I

C
23

LRSH performs a logical right shift. It shifts the contents of AB
right the number of places sp~i£ied in bits 15 through 23 of the
effective address. The bits in the sign position of A and the
sign position of B shift with the rest of the number. Vacated bits
on the left fill with zeros. Bits shift out of A23 into BO' Bits
sh ifti ng past B23 are lost.
Registers Affected: A, B
RCY

RIGHT CYCLE AB
66

o

Timing: 2-7

123

I

C
23

RCY shifts the contents of the AB Register right the number of
places specified in bits 15 through 23 of the effective address.
The bit in the sign position of B shifts like any other bit in B.
~its shifting out of A23 shift into BO' Bits from bit position 23

17

of B go into bit position 0 of A. The computer treats the doublelength register as if it were circular and cycles it onto itself; it
loses no bi ts.

NOD

67
I

Timing: 2-7

Registers Affected: A, B

NORMALIZE AND DECREMENT

I II

10

8 9 10

I

I

C

1415

23

EXAMPLE:
NOD shifts the contents of the AB Register left until (1) a bit
appears in position 1 of A that is not equal to the bit in the sign
position of A; or (2) until C shifts occur. The computer keeps
count of the number of places shifted and when the normalize
operation is completed, it subtracts the count from the contents
of the Index Register and places the result back into the Index.
[f, in the attempt to normalize, shifting exceeds 48 places,
the contents of the AB Register were initially zero. In this
case, the computer subtracts 48 from the Index Register. Zeros
fi II the vacated positions.

The instruction is: RCY 00017

A

B

Before Execution

61235703

41537701

After Execution

37701612

45703416

LSH

LEFT SHIFT AS
67

00

I

I

C
23

J15

LSH shifts the contents of the AB Register left the number of
places specified in bits 15 through 23 of the effective address.
Bits shift left through the sign position of A, but when a bit, different in value from the original sign, shifts into the sign position' the computer sets the Overflow Indicator. Bits shifting
out of BO go into A23' Bits shifting past position 0 in A are
lost. Zeros fill the vacated bit positions on the right end of
the B Register.
Registers Affected: A, B, Overflow Indicator

The number, C, placed in address bit positions 15 through 23,
is an upper limit for the number of left shifts that will occur.
The programmer must ensure that C is sufficiently large to
permit a complete normalization.
EXAMPLE:
NOD 30

Timing: 2-5

EXAMPLE:

6.

~

Before Execution

00004632

76124035

00000000

After Execution

23153705

20164000

77777765

X

Timing: 2-5

Registers Affected: A, B,X

The instruction is: LSH 00022

B

A
Before Execution

46712370

64132711

After Execution

70641327

11000000

REO

RECORD EXPONENT OVERFLOW
20010

02
LCY

o
C

o

1 2 3

I

23

1415

LCY shifts the contents of the AB Register left the number of
places specified in bits 15 through 23 of the effective address.
The bits in the sign positions of A and B shift like any other
bits in the number. Bits shifting out of So shift into A23 . The
instruction copies bits that shift from bit position 0 of A into
bit position 23 of S. The computer treats the double-length
register as if it were circular and cycles it onto itself. It loses
no bits.

I

This instruction is normally used after a normalize operation to
record a floating-point exponent overflow. See Floating-Point
Operations, this section.
Registers Affected: Overflow

Timing:

1

CONTROL INSTRU CTIONS
HLT

HALT

Timing: 2-5

Registers Affected: A, B

00

EXAMPLE:
The instruction is: LCY 00011

18

I

23
12 3
This instruction causes the Overflow Indicator to be turned on
if the content of bit 14 of the Index Register is not equal to the
content of bit 15 of the Index Register.

LEFT CYCLE AS

67

I

A

B

Before Execution

71432560

34156723

After Execution

32560341

56723714

o

I

23

When the computer executes this instruction, it halts computation and lights the HALT indicator in the console. Before halting, the computer increments the P Register and brings the next

instruction to the C Register to be displayed. To resume computation, the operator must first set the RUN-IDLE-STEP switch
to IDLE, then back to RUN.
The computer then executes the next instruction, according to
the P Register, and turns the HALT light off when the switch is
set to either the RUN or STEP position.

BREAKPOINT TESTS
This instruction tests the status of the Breakpoint switches singly
or in any combination. If anyone of the Breakpoint switches
tested is reset, the computer skips the next location in sequence
and executes the following instruction. If none of the Breakpoint switches tested is reset, the computer executes the next
instruction in sequence.

Indirect addressing and i ndexi ng do not appl y to th i s instruction.

Mnemonic
BPT
BPT
BPT
BPT

When the computer executes HLT, a" internal computation
ceases at the end of the present instruction being executed.
If an input/output operation is in progress, it continues until
completed. Computation automatically resumes with the
occurrence of a program interrupt, if the RUN-IDLE-STEP
switch is still in the RUN position and the interrupt system is
enabled.
Registers Affected: None

1
2
3
4

No.1
No.2
No.3
No.4

Octal Configuration

Timing: 1 + wait

o 40 20400
o 40 20200
o 40 20100
o 4020040

Test
Test
Test
Test

Registers Affected: None

Timing: I, if no skip
2, if skip

OVERFLOW INSTRUCTIONS
OVT

NOP

Name of Instruction
Breakpoint
Breakpoint
Breakpoint
Breakpoint

OVERFLOW INDICATOR TEST AND RESET

NO OPERATION

20001

40

I

I

23

20

I

23

Executing NOP does not affect the A Register, B Register,
X Register, or memory. Indirect addressing and indexing do
not apply to this instruction.
Registers Affected: None

Timing: 1

This instruction tests the status of the Overflow Indicator, skips
or not accordingly, and turns the indicator off. If the indicator
is off, the computer skips the next instruction in sequence and
executes the following instruction. If the indicator is on, the
computer executes the next instruction in sequence.
Registers Affected: Overflow
Indicator
RESET OVERFLOW

ROV
EXU

EXECUTE
23

I
0

M

I

23

EXU causes the contents of the effective memory location to
be executed as an instruction without altering the contents of
the Program Counter. If the effective location is not a Branch,
Skip, or another Execute instruction, the computer executes the
next instruction in sequence following the Execute instruction,
after it executes the contents of the effective location.
If the contents of the effective memory location are a Branch
instruction, program control goes to the effective address of
the branch and not to the next instruction in sequence following the Execute instruction.
If the contents of the effective memory location are a skip
instruction, then, depending on the skip decision, program
control returns to the next instruction, or the next instruction
plus one, following the Execute instruction.
If the contents of the effective memory location are another
Execute instruction, the above process continues identica"y,
with the normal return being the initial Execution location plus
one. This process can cascade indefinitely.

Registers Affected: None

Timing: 1

Timing: I, if no skip
2, if skip

02

0
J3

I

J9

I

20001

I

23

ROV unconditionally resets the Overflow Indicator (clears to
zero).
Registers Affected: Overflow

Timing: 1

MEMORY EXTENSION INSTRUCTIONS

o

SET EXTENSION REGISTER

06 200SR

06

I

161

18

2021

23

Th is instruction sets (or loads) Memory Extension Register 3 and/
or 2 with the contents of fields R3 and R2, respectively.
If 53, position 16, is a I, the computer sets the contents of R3,
bit positions 18 through 20, into EM3. This destroys the previous contents of EM3. If 53 is a 0, 5ET does not affect EM3.
If 52, position 17, is a I, the computer sets the contents of R2,
bit positions 21 through 23, into EM2. This destroys the pre- .
vious contents of EM2. If 52 is a 0, 5ET does not affect EM2.
If both 53 and 52 are I, 5ET loads both EM3 and EM2 simultaneously. If both 53 and 52 are 0, 5ET is effectively a "no-op"
instruction.
Registers Affected: EM3, EM2

Timing:

1

19

o

EXTENSION REGISTER TEST

40 4000T

,

40

This instruction tests the contents of the extension register as
follows:

No test. The computer executes the next instruction in
sequence.
Test EM2. If (EM2) 12, the computer skips the next i nstruction in sequence. If (EM2) = 2, the computer executes the
next instruction in sequence.

2

Test EM3. If (EM3)13, thecomputerskips the next instruction in sequence. If (EM3) =3, the computer executes the
next instruction in sequence.

3

Test EM3 and EM2. If (EM3) 13 or (EM2) 12, the computer skips the next instruction in sequence. When
(EM3) = 3 'and (EM2) = 2, the computer executes the next
instruction in sequence.
Timing: 1, if no skip
2, if skip

. Registers Affected: None

FLOATING POINT OPERATIONS
Floating-point operations are performed via Programmed Operator subroutines in either single or double-precision. Doubleprecision is used when accuracy of approximately 11 decimal
digits must be maintained. Single-precision permits faster
execution times with approximately seven decimal digits of
accuracy.
These standard Programmed Operators assume that the most
significant word is in A, or stored in location M + I, while
the less significant word is in B, or memory location M. See
Section I, Floating-Point Format.
DOUBLE-PRECISION FLOATING-POINT OPERATIONS
Double-precision floating-point operations are performed using a fractional number of 39 bits (38 bits plus sign) and an
exponent of nine bits (eight bits plus sign). Numbers are represented with a fraction equal to 11 decimal digits plus sign
and a multiplier as high as 1O±77.
The Programmed Operator subroutines that perform doubleprecision, floating-point operations are:
Designation

20

Single-precision, floating-point operations are performed using
a fractional number of 24 bits (23 bits plus sign) and an exponent
of nine bits (eight bits plus sign). Numbers are represented with
a fraction equal to six decimal digits plus sign and an exponent
as high as 1O±77.
The Programmed Operator subroutines that perform singleprecision floating-point operations are:

I

o

SINGLE-PRECISION, FLOATING-POINT OPERATIONS

Approx.
Execution Time

Name

Function

FLA

Floating
Add

Floating (A, B)
+ (M+l,M) +A,B

92 flsec

FLS

Floating
Subtract

Floating (A, B)
- (M+l, M) +A, B

101 flsec

FLM

Floating
Multiply

Floating (A, B)
x (M+liM)+A,B

147 flsec

FLO

Floating
Divide

Floating (A, B)
.;. (M+l,M)+A,B

157 flsec

Designation

Name

Function

Approx.
Execution
Time

FSA

Floating Add,
Single-Precision

Floating (A) + (M+ 1) ~A 77 flsec
Exponent in B,M

FSS

Floating Subtract,
Single-Precision

Floating (A) - (M+ 1) ~A
Exponent in B,M

FSM

F.loating Multiply, Floating (A) x (M+ 1) +A 54 flsec
Exponent in B, M
Single-Precision

FSD

Floating Divide,
Single-Precision

80 flsec

Floating (A).;. (M+1)+A 101 flsec
Exponent in 8, M

SDS 930 INSTRUCTIONS FOR
FLOATING-POINT OPERATIONS
To mainta in accuracy in floating-poi nt operations, a II fractiona I
numbers must be in normalized form, that is, shifted to the left
to eliminate leading insignificant digits. Whenafloating-point
arithmetic operation has been performed, the fractional number
must be normalized and the exponent adjusted to reflect the
c.hange in the fractiona I number. NORMALIZE AND DECREMENT X is used to:
(a) shift the fractional number to the .left to eliminate
leading insignificant digits.
(b) adjust the exponent (contained in the X Register)
for each bit position shifted.
To determine whether the adjusted exponent has overflowed the
15th bit in the Index Register during the above normalize operation, the instruction, RECORD EXPONENT OVERFLOW
(REO), is used. This instruction causes the Overflow Indicator
to be turned on if (X I4 ) 1 (X I5 ).
When performing floating-point addition and subtraction, it is
necessary to al ign the numbers so that the exponents are equal
before the arithmetic is performed. The single instruction,
DIFFERENCE EXPONENTS AND SKIP (74):
(a) determines which of the numbers is to be shifted, and
(b) determines the number of positions to be shifted to
al ign the numbers. AI ignment is performed using
SHIFT AB, Index bit equal to one, with the number
of shifts located in the X Register.
Manipulation of the exponent is required in all floating-point
operations. Capability is included in the Register Change
instruction to:
(a) transfer the exponent portion of the word to and from
the A, B, and X Registers, and
(b) clear exponent bits when arithmetic is to be performed.
These operations can be performed in effective combinations in
one machine cycle .

III. INTERRUPT SYSTEM
PRIORITY INTERRUPT SYSTEM
SDS 900 Series Computers contain a priority interrupt system
that provides added program control of input/output operations,
aids in programming simultaneous input/output and compute
operations, and allows immediate recognition of special external conditions.
Interrupts, as specified by the program, can signal when a single
word or a block of words has been transmitted. When received,
the internal logic examines the interrupt signal and causes the
computer to interrupt the program sequence at the end of the
execution cyc Ie of the current instruction. Without disturbing
the Program Counter Register, the computer transfers program
control to one of a selected set of memory locations. A MARK
PLACE AND BRANCH'(BRM) instruction in this location saves
the contents of the program counter, EM3, EM2, and overflow
indicator and transfers to the particular interrupt servicing routine required. Entrance to the proper service routine occurs
since each interrupt has a unique interrupt location. To exit
from the routine, a BRANCH UNCONDITIONALLY (BRU) instruction using indirect addressing returns control to the next
instruction in proper sequence in the main program; it also
clears the interrupt. Note that when an interrupt occurs causing the execution of the BRM in the interrupt level, the address
stored in the mark location is the location plus one of the instruction that was interrupted. In other words, the computer
increments. the program counter prior to inspecting its registers
for an interrupt condition.
The priority interrupt system has up. to 896 System interrupt levels. The levels are numbered upward from 200 and have priority according to number; the higher priority levels have a
smaller number. See Table 3-1, Interrupt Locations, for the
spec ific assignment.
The two standard as well as the additional interrupts obtained
with SDS optional hardware are located at interrupt levels
numbered from 30. In general, these have priority according to number like the System interrupts. Note that interrupts 30-77 have priority over any System interrupt (200 or
more). The Power Fail-Safe option interrupts (in locations
36 and 37) are "out-of-order" interrupts; they have the highest priority of all.
When an interrupt has occurred and its service subroutine has
been entered, an interrupt of higher priority can interrupt the
subroutine and gain program control for the servicing of its
more important-operation. But an interrupt of lower priority
cannot interrupt an interrupt-processing subroutine of a higher
level. Thus, the priority interrupt system allows interrupts to
be arranged according to their importance and/or according to
their need for speedyservicing.
The above type of interrupt is called a normal priority interrupt
to differentiate from another interrupt feature, the single-

instruction interrupt. This different kind of interrupt causes the
execution of only one instruction before automatically clearing
itself and returning to the program that it interrupted. For
example, if an external clock source is connected to the computer so that it pulses an interrupt line at set intervals, the
program can maintain a programmed real-time clock. Each
time the external pulse causes an interrupt, the program
executes the single instruction, MEMORY INCREMENT (MIN),
to add one to the memory word selected for use as the programmed real-time clock. The main program can examine this
memory location whenever necessory to determine how many
time increments have elapsed since the clock was started.
If the single instruction that is executed is a branch instruction,
and the branch occurs, the interrupt is cleared but there is no
return to the program that was interrupted. This type of interrupt needs no branch instruction to clear it.

Since the single-instruction interrupt performs just one instruction and clears itself, it can be sandwiched into a priority system without disturbance. Anyof the optiona I System interrupts
(200-1777) can be single- or normal-instruction interrupts in
any combination desired.

PRIORITY INTERRUPT OPERATIONS
A normal priority interrupt level has three operational states:
Inactive, Waiting, and Active.
In the inactive state, no interrupt signal has been received
into the level and none is currently being processed by its
interrupt servicing subroutine.
In the woiting state, an interrupt has been received into the
level, but is not being processed. This situation may be due
to an interrupt of higher priority being processed at this time.
When all higher waiting interrupts have been processed, this
level goes to the active state.
In the active state, the interrupt has caused the main program
to recognize its presence and has transferred to its assigned interrupt location where it is being processed. When the interrupt processing is completed, a BRANCH UNCONDITIONALLY (BRU) instruction with indirect addressing exits from the
service subroutine by transferring control to the proper return
location. This branch instruction also sets the inter:rupt level
to the inactive state.
:..
A single-instruction interrupt operates in the same way as the
normal priority interrupt in the inactive and waiting states.
However, when acknowledged, this interrupt enters the active
state, and remains there during the execution of one instruction. At the completion of the one instruction, the singleinstruction interrupt returns to the inactive state without the
aid of a branch instruction. The single instruction must have a
two-cycle or greater execution time.

21

INTERRUPT CONTROL
Two program control features are available in the interrupt
system. These features are Arm/Disarm and Enable/Disable.
Arm/Disarm controls whether an interrupt can proceed from the
inactive state to the waiting state. When armed, an interrupt
signal sets the interrupt to the waiting state. The disarmed condition causes that level to retain no record of an interrupt signa I enteri ng the Ieve I.
Enable/Disable operates on the entire interrupt system. When
the interrupt system is enabled, the System interrupts (200-1777)
are enabled; when the interrupt system is disabled, the system
interrupts are disabled. Enable/Disable operates differently for
the interrupts obtained with SDS options (30-:77). Enable/
Disable has no effect on the Power Fail-Safe interrupts; they
are always enabled and armed. See the last two subsections of
this section for a description of how the channel interrupts are
affected.
The control of the optional Arm/Disarm feature operates on individual System interrupt levels, t~at is,:.,), ,c, hosen, interrupt
0 M
I /) 1(..
" !~

(c::.

r

r

/.J

level may be selectively armed or disarmed. But the instruction structure for Arm/Disarm allows operation on these interrupts in groups of sixteen.

NON·INTERRUPTABLE INSTRUCTIONS
Three instructions prohibit interrupts following their execution.
If a branch occurs, an interrupt cannot occur between the execution of INCREMENT INDEX AND BRANCH (BRX) and the
instruction to which BRX branches. An interrupt cannot occur
between the execution of ENERGIZE OUTPUT M (EOM) and
the instruction following it or between the execution of
ENERGIZE OUTPUT TO DIRECT ACCESS CHANNEL (EOD)
and the instruction following it.

ENABLE/DISABLE INTERRUPT INSTRUCTIONS
Three instructions are avai lable for setting, resetting, and
testing the state of the INTERRUPT ENABLED indicator.

I;

;:;

,

Table 3-1.

Interrupt Location Assignments

30

Channel Y

Count Equals Zero (End-of-Word)

31

Channel W

Count Equals Zero (End-of-Word)

32

Channel Y

End -of-Record (End -of-Transmission)

33

Channel W

End -of-Record (End-of-Transmission)

36

Power ON

Power Fai I-safe interrupt: Power Return

37

Power OFF

Power Fai I-safe interrupt: Power below safe limit

60

Channel C

Count Equals Zero (End-of-Word)

61

Channel C

End-of-Record (End-of- Transmission)

62

Channel D

Count Equals Zero (End-of-Word)

63

Channel D

End-of-Record (End -of-Transmission)

64

Channel E

Count Equals Zero

65

Channel E

End -of -Record

66

Channel F

Count Equals Zero

67

Channel F

End-of-Record

70

Channel G

Count Equals Zero

71

Channel G

End-of-Record

72

Channel H

Count Equals Zero

73

Channel H

End-of-Record

74

Clock Sync. }

75

Clock Pulse

Locations 74, 75 are for the real-time clock

200}
217

Group 0 Optional General-Purpose Interrupts

220}
237

Group 1 Optional General-Purpose Interrupts
etc.

22

EIR

ARMING FEATURE (Optional)

ENABLE INTERRUPT

02

20002

I

I

1

23

EIR unconditionally sets the INTERRUPT ENABLED indicator
and enables the interrupt system. If any interrupt levels are
waiting, the one with the highest priority becomes active.
Registers Affected: None

DIR

The arming feature is controlled for a group of 16 interrupts by
a word sent to the group with the ARM INTERRUPTS (AIR) instruction followed by the PARALLEL OUTPUT (POT) instruction.
AIR operates on Iy on System interrupts (200-1777).
AIR

Timing:

ARM INTERRUPTS

o0

J

20020

02

I

1

3

23

AIR prepares the arm interrupt control unit to receive a control
word for a group of 16 interrupt levels. A PARALLEL OUTPUT
(POT) must always follow AIR, or an unpredictable operation
results.

DISABLE INTERRUPT

02

20004

I

I

Registers Affected: None

Timing: 1

23

DIR unconditionally resets the INTERRUPT ENABLED indicator
and disables the interrupt system. This instruction does not
change the current state of any interrupt level.

Section IV, Input/Output System, contains a discussion of
PARALLEL OUTPUT (POT). The word that the POT instruction
addresses has the following format:

Registers Affected: None

I

Timing: I

Address

IC I

I

5 6 7 81

o
lET

INTERRUPT ENABLED TEST;
SKIP IF INTERRUPT SYSTEM ENABLED

40

20004

I

I

23

If the priority interrupt system is enabled, the computer skips
the next instruction in sequence and executes the following
instruction. If the priority interrupt system is disabled, the
computer executes the next instruction in sequence.
Registers Affected:

!DT

None

Timing: I, if no skip
2, if skip

INTERRUPT DISABLED TEST;
SKIP IF INTERRUPT SYSTEM DISABLED

40

I

Registers Affected:

None

Timing: I, if no skip
2, if skip

I

23

The control operations are:

Bit
Octal Octal
Position Position Value

Function

02

00

o

Not used

01

2

Arm all interrupt levels that are
sel ected by a I in b it positions
8 - 23

10

4

Disarm all interrupt levels that are
selected by a 0 in bit positions
8 - 23

11

6

Arm all interrupts sel ected by a I
and disarm all interrupts selected
by a 0 in b it positions 8 - 23.

23

If the priority system is disabled, the computer skips the next
instruction in sequence and executes the following instruction.
If the priority interrupt is enabled, the computer executes the
next instruction in sequence.

1

The address field in bit positions 0 through 5 identifies which
group of 16 interrupts in the system is being addressed. Address 00 refers to the group of locations 200-217. The C field
controls what is done to the particular interrupt levels selected
in bit positions 8 through 23. Bit position 8 refers to the lowestnumbered level of the group, therefore the one with highest
priority. Bit position 23 refers to the last or highest-numbered
level, the one with lowest priority. For example, a word of
00240000 arms level number 201.

6-7

20002

I

Interrupt Select Bits

I

23

CHANNEL INTERRUPT DESIGNATIONS
As shown in the Interrupt Location Table, each I/O channel
has two interrupt levels. These reflect the two distinct uses of
interrupts during channel input and output. Also, each W, Y,
C, and D channel level has two names that reflect their use in the
ExtendedorCompatible I/O Modes (see Section IV, Compatible/
Extended Input/Output Modes.

END-OF-WORD/END-OHRANSMISSION INTERRUPT
OPERATIONS; COMPATIBLE MODE
A program can use Channels Wand Y as single-word, direct,
program-controlled, input/output buffers. Special I/O
instructions appl icable to Channe Is Wand Y control th is type
of operation (see Section IV). In this mode, the program can
specify that interrupts occur as each word is transferred from
the buffer to the periph'eral device on output, or as soon as the
buffer is filled from the peripheral device on input. This is the
End-of-Word interrupt. The program can spec ify that an Endof-Transmission interrupt occurs when the buffer detects a
signal such as End-of-Record from magnetic tape. During both
input and output operations, this interrupt occurs when the
peripheral device used in the transmission disconnects and the
buffer becomes ready for another input/output operation.

from memory. The End-of-Record interrupt occurs when the
channel receives an End-of-Record signal (gap). Input/output
functions can alter this latter occurrence for use with magnetic
tapes.
EFFECTS OF THE ENABLE/DISABLE FEATURE 0 N ARMABLE
INTERRUPTS
When operating an Input/Output Channel in the extended mode,
the interrupt Enable feature controls the Armable interrupts
(Count Equals Zero and End-of-Record). If a channel generates
an extended mode I/O interrupt while the system is disabled,
the designated interrupt level goes to the Waiting state. When
the program again enables the interrupt system, the interrupt
goes to the Active state when its priority allows.
This feature allows the programmer great ease in handl ing
multiple channel operations. The interrupt processing subroutine for one channel can disable the interrupt system whi Ie
it processes the interrupt. During this time, the system receives
all other interrupts in their respective levels and goes to the
Waiting state until the system is again enabled.

These two interrupts also can control input/output termination
for any communication channel when the program is operating
the buffers in the block transmission or "interlaced" compatibl
mode (optional system). The End-of- Transmission interrupt
operates in the fashion described above. In this mode, the Endof-Word interruptonlyoccurson input. The End-of-Word interrupt
occurs after the channel has read the number of words specified
and then another word fills the buffer. If the program encounters
the last word before an End-of- Transmission interrupt, the Endof-Word interrupt occurs after the next word is read. If an
End-of-Record condition occurs first, the End-of- Transmission
interrupt occurs. No End-of-Word interrupt occurs during
output.

INACTIVE

e

The Enable or Disable instructions "enable and arm" or "disable and disarm" the End-of-Word and End-of-Transmission interrupts when the channel is not operating in the extended
interlace mode. When the EIR instruction is executed, the
interrupt system is enabled and these interrupts are also armed;
when DIR is executed, the system is disabled and these interrupts are also disarmed.

Proceed if ARMED

WAITING

Proceed if Proper Priori ty

Proceed if ENABLED

COUNT EQUALS ZERO/END-OF-RECORD; EXTENDED MODE
When the SDS 930 Input/Output System uses channels within
its full capabilities, SDS 930 input/output functions control
interlaced block transmission operations (see Input/Output
Functions, Section IV). The interrupts used with the extended
input/output function control are Count Equals Zero and Endof-Record. The Count Equals Zero interrupt occurs when the last
of the number of words specified is placed into or brought

24

ACTIVE

Figure 3-1.

Interrupt Arm-Enable Response

IV. INPUT/OUTPUT INSTRUCTIONS
INTRODUCTION

COMMUNICATION CHANNELS

The SDS 930 has a flexible, input/output system to complement
its high, internal processing speed and versatile instructions.
This system can transmit data in word, character, or single-bit
form to and from the computer at the speed of internal computation. The input/output system assumes control of conditions
imposed by different characteristics of a wide variety of
devices, but leaves a high degree of input/output control to
the programmer.

Using Channels Wand Y, characters and words can be transmitted between memory and peripheral devices under the direct
control of single instructions. Each channel has associated with
it two instructions to facilitate direct control operations. For
Channel W, W INTO MEMORY (WIM) causes a word from a
peripheral transmission to be taken from the Channel W buffer
register and placed directly in the specified memory location
without disturbing any internal registers. MEMORY INTO W
(MIW) causes a word to be taken from a specified memory location and placed in the Channel W buffer register to be read
out to the currently operating peripheral device connected to
the channel. WIM and MIW are preceded by instructions from
the EOM group that set up the input/output operation. YIM
and MIY instructions function in an analogous manner for channel Y. The general test instruction, SKIP IF SIGNAL NOT
SET (SKS) provides the faci Iity for testing error indications and/
or for testing various peripheral device indicators.

This system inc ludes the following types of input/output:
Buffered input/output of data words, each under direct
program control
Communication channel input/output of characters or
words, time-shared with memory and multiplexed with
computation.
Communication channel input/output of characters or
words, fully buffered and simultaneous with computation.
Direct parallel input/output of up to 24 bits of information to and from external equipment, completelycontrolled
and sequenced externally.
Direct parallel input/output of up to 24-bit words to
and from external static registers under program control.
Single-bit input/output, such as equipment on/off status,
sense switches, and pulsing and sensing of special devices.
DATA FLOW PATHS
The SDS 930 includes as standard equipment one Time-Multiplexed Communication Channel (TMCC), without interlacing
capability, as well as provision for three additional channels.
The interlace unit is available as an option. The Wand Y
channels are avai lable with or without interlacei the C and D
channels are available only with interlace. These channels
are capable of automatically controlling the flow of data to
and from memory at rates up to one word every 3.5 microseconds. These channels run independently of the central processor
and only communicate with it to transferdata toorfrom memory.
In addition to the Time-Multiplexed Channels, a Direct Memory
Access System is available. This system uses a path to memory
separate from those used by the central processor. Up to four
Direct Access Communication Channels (with direct access
memory connections) can be attached to the Direct Access
System. These channel operate like the time-multiplexed
Channels except that they are faster and provide for a true
overlap of input/output with processing.
A Data Multiplex System, which uses the direct access memory
connection, is also available as an option. This system consists
of a Data Multiplex Channel that accepts/transmits data words
and memory addresses'from many external devicesorsubchannels,
all of which may be in operation at the same time. The system
is capable of transmitting up to 572,000 words per second
simultaneous with computation (see Appendix A-ll).

Additionally, using any channel including Channels Wand Y with
interlace,data can be transmitted to and from core storage under
channel control. Operation of a channe I is i ni tiated by the execution of a sequence of instructions in the centra I processor. Once
started, the channel operates independently of the central processor, automatically transferring each word at the correct time.
Four instructions control the process of transmitting and receiving data between channel peripheral equipment and the central
processor. These instructions are:
EOM

ENERGIZE OUTPUT M

EOD

ENERGIZE OUTPUT TO DIRECT ACCESS
CHANNELS

POT

PARALLEL OUTPUT

SKS

SKIP IF SIGNAL NOT SET

EOM instructions activate one of Channels W, Y, C, or D, to
select the periphera I device to be used, and to set up the initial conditions of the data transmission, including the peripheral operation to be performed. EOD instructions activate one
of Channels E, F, G, or H. The other functions of EOD are
simi lar to EOM. An EOM (EOD) instruction a Iso specifies terminal conditions for an operation.
PARALLEL OUTPUT (POT) sends out to the channel the number of
words in the transmission and the address at wh ich the output begins.
SKIP IF SIGNAL NOT SET (SKS) can test the Error indicators,
End-of-Transmission indicators, and other input/output control
indicators, such as printer end-of-form or card hopper empty.
The general order of use of these instructions for interlaced
operation is:
Instruction

EOM

Function
to address the channel, connect the peripheral device, specify various input/output
conditions, and alert the optional channel
interlace (see Communication Channel
Input/Output)

25

Instruction

Function

EOM

to specify the terminal conditions and interrupts desired during the transmission

POT

to transmit to the channel a word containing
the transmission starting address and block
length

Bits 0 through 9 of this latter word contain the ten lower order
bits .of the word count; bits 10 through 23 contain the 14 bits
of the starting address. The second EOM contains the highorder bits of the word count and starting address when needed.

ternally controlled and sequenced devices may present data
and addresses to the direct access connectors, thus allowing
input/output operations or other memory accesses to be performed independently of the computer.
These special input/output systems present an address and
various timing and control signals to the connector. External
data may be stored in any specified location, or read from any
location specified by the external unit. For example, the
external equipment may provide an interface register, thereby
allowing an entire block of data to be entered into or read
from memory. Telemetry data may be automatically decommutated, thus obviating sorting and sequencing within the
computer.

DIRECT PARALLEL INPUT/OUTPUT
The direct parallel input/output (POT/PIN) facility allows any
word in core memory to be presented, in parallel, at any special system connector or applicable standard peripheral connector; or, conversely, allows signals sent to a connector to be
stored in any core memory location. EOM and SKS instructions
control parallel input/output operations in the same way as in
channel operations. POT/PIN instructions also generate or
check for correct parity with each word transmitted.
See Direct Parallel Instructions, this section, for a detailed
description of parallel input/output.
SINGLE-BIT INPUT/OUTPUT
EOM and SKS instructions also perform single-bit input/output
and testing for special or standard devices. The execution of
an EOM transmits a single signal of approximately 1.4 microseconds duration to an external connector and also provides the
connector with a 15-bit address for the destination of this signal. SKS tests whether a similar signal is present on an external connector and skips accordingly. See Single-Bit Transmission,
this section, for further description of single-bit input/output.

DIRECT MEMORY ACCESS SYSTEM
This optional system provides direct transmission between peripheral devices and cor~ memory. Two access paths to the
memory module are available. The standard path connects to
the central processor; the other path connects to Direct Access
Communication Channels on the Direct Memory Access Connection. Direct memory access allows data to be transmitted
at the rate of' one 24-bit word every 1.75 microseconds, thus
sustaining an input/output rate of 572,000 words (equivalent to
2,284,000 characters) per second in parallel with full-speed
computation.
Communication Channels, E, F, G, and H, if present in a system, require the Direct Memory Access System, and therefore,
are called Direct Access Communication Channels. Operation
of these channels is discussed in Communication Channel Input/
Output, th is section.
Note that the Direct Memory Access System moy be obtained
separately and used to incorporate special-purpose input/output
equipm~nt instead of the standard Direct Access Channels. Ex-

26

PRIMARY INPUT/OUTPUT INSTRUCTIONS
EOM

ENERGIZE OUTPUT M
02

I
02

04

03

05

06

23
07

The major instruction for preparing Channel W (orY, C,
D) and an attached peripheral device to perform a data
transmission or other peripheral activity is the multi-purpose
instruction, ENERGIZE OUTPUT M (EOM). It operates in
four distinct modes with many functional configurations. These
modes are Buffer Control, Input/Output Control, Internal Control, and System Control. In the third and fourth modes, EOM
controls and initiates non-communication channel operations
such as special systems transmissions. Each of the frequently
used EOM instruction configurations has a mnemonic tag used
with standard SDS assemblers. These mnemonics appear in this
manual with the description of the specified configurations.
The different modes of operation are program-selectable by the
setting of two bits (10, 11 of octal position 3) within the EOM
instruction format:
Octal
Value
0

Bit Position 10
0

Bit Position 11
0

Buffer Contro I

0

Interna I Contro I

0
2
3

Area

Input/Output Control

System Control

A Buffer Control mode EOM operates essentially as a set-up or
preparation fcc i Iity for data transmissions or other periphera I
activities using the channel. The channel to be used, the
peripheral unit on that channel, the operation to be performed,
and the type of character format to be used are all detailed·
within this EOM. It also detai Is the use of BCD or binary data
transmission, the allowance or not of a leader(asinpapertape),
and theditection of operation (as in forward direction for
mognetic tape). Execution of such an EOM "connects" the
spec ifiedperiphera I unit to the channel. An EOM inthismode
can also alert the interlace, which is the optional, automatic
buffer control for input/output.

An EOM in the Input/Output mode directs peripheral devices
to perform non-transmitting operations such as rewind magnetic
tape and upspace the printer. This EOM selects certain channel operations such as interrupt response and input/output terminal function desired. It alerts peripheral devices that a
PARALLEL INPUT (PIN) or ,PARALLEL OUTPUT (POT) instruction follows. It also can give an extension of the word
count to 15 bits for the number of words to be transmitted and
an extension of the address specification to 15 bits. Without
disturbing the associated channel, this EOM can also set up
the interlace unit. It is with the input/output mode EOM that
the user selects his I/O operation as compatible or extended
. I/O modes (described later in this section).
This coding sequence initiates such an interlaced channel
operation (compatible mode):
Instruction

Function

EOM (Input/
Output Control
Mode)

Alert the interlace

POT

transmit starting address and
block length to interlace

EOM (Buffer
Control Mode)

address channel, connect
peripheral device, specify
various input/output conditions,
start transmission

Initiating an interlaced input/output operation via this sequence
of instructions facilitates checkout by allowing the programmer
to single-step through this portion of the program. The first
two instructions, EOM (Ioc) and POT, set up the interlace
with data address and block length. Therefore, single-stepping
through the sequence a I lows the interlaced channel to complete the input/output operation. When a single EOM (Buffer
Control mode) sets up the channel and interlace with a POT
instruction following, the programmer cannot step through the
sequence since the input/output operation proceeds before the
next stepped instruction (POT) places the address and block
length in the interlace.
An EOM in. the Internal Control mode enables and disables the
interrupt system. EOM in this mode also can prepare the system for the selective arming and disarming of the system interrupt
levels. This mode does not directly concern the input/output
programmer.
An EOM in the System Control mode is specifically coded for
a given installation and system. Address capability is 15 bits
or 32,768 combinations for these special system designations.
Note: If an interrupt occurs during the execution of an EOM
in any mode, no acknowledgement occurs unti I the completion
of the execution of the instruction following the EOM.

EOD

o

ENERGIZE OUTPUT TO DIRECT ACCESS CHANNEL

06
I

1 2 3

23

The EOD instruction operates in the Buffer Control and Input/
Output Control modes. It refers to Channels E, F, G, and H,
when present, and performs the same functions gnd operations
as on EOM on these channels.
SKIP IF SIGNAL NOT SET

SKS

40

o

I

1 2 3

00

01

23
02

03

05

04

06

07

The principal instruction for testing the states and responses of
data channels and their attached peripheral devices, as well
as testing internal and external indicators, is the multi-purpose
instruction, SKIP IF SIGNAL NOT SET (SKS). SKS is a "skip
c lass" instruction yielding a dec ision and transfer capabi I ity to
all channels, devices, indicators, and systems that require it.
It operates in four distinct modes: Special Internal Test, Channel and Device Test, Internal Test, and Special System Test.
In the second mode, SKS tests channel-oriented, input/output
functions. Each of the frequently used SKS instruction configurations has a mnemonic tag, used with SDS assemblers. These
mnemonics appear in this manual with the description of the
specific configuration.
These different modes of operation are program-selectable by
the setting of two bits (10, 11 of octal position 3) within the
SKS instruction format:
Bit Positions
11
10
0

0

Octal
Value

Timing

Specia I Interna I Test

1,2

Channel and Device Test

2,3

2

Internal Test

1,2

3

Special System Test

2,3

0

0
0

Area

In the Channel and Device Test mode, S KS tests a channel for
channel Ready (not active), interlace Wond Count Equal to
Zero, and Error. This mode also tests peripheral devices directly.
These include testing indicators in a magnetic tape unit suchas
Beginning-of-Tape, End-of-Tape, File-Protect Ring present,
and End-of-File. For example, an SKS instruction might address an indicator within the printer to determine whether the
paper is at the End-of-Form.
In the Interna I Test mode, SKS tests whether the interrupt system
is enabled or disabled, whether a breakpoint switch is set, and
whether Overflow is set.
In the Special Internal and Special System Test modes, SKS
tests signals of special configuration as the specific system
requires.

27

COMMUNICATION CHANNEL INPUT/OUTPUT
GENERAL INFORMA nON
SDS Communication Channels provide fully buffered, input/
output control and transmission, multiplexed or simultaneous
with computation. Up to eight data channels can connect to
the central processor, all operating independently of each
other.
Each channel can control as many as 30 input/output devices
and automatically handles character, word assembly and disassembly, input/output parity detection and generation, data
transmission to and from memory, and End-of-Transmission
detection.
All channels are bi-directional and can communicate with
6-bit character devices or word devices of up to 24 bits. In
the case of character-oriented devices, the program specifies
the number of characters to be contained in each word during
the transmission.
A channel buffer assembles and disassembles data words as they
are transmitted between core memory and the peripheral equipment. The buffer maintains control of operations such as
characters per word transmitted and direction of peripheral
operation (as in magnetic tape forward/reverse).
A Buffer Control mode EOM or EOD sets up the channel
buffer for operation. The execution of this EOM sets theoperation controls, places the unit address in the buffer, and initiates data assembly/disassembly. The presence of the unit
address activates the buffer, causing it to look for data coming
from the peripheral device or from memory, asdete,rminedbythe
unit address.
When in use, a channel interlace controls the transfer of the
data words going through the associated channel buffer. This
interlace supplies the memory address of data coming from or
going to memory and maintains the word count determining the
number of words transferred. The terminal interrupts, End-ofRecord and Zero Word Count, come from the interlace and are
under its control. The interlace controls input/output termination functions during interlaced operation.
Two EOM instructions and a POT instruction alert and set up a
channel interlace. The first EOM alerts the interlace that is
activates the interlace and instructs it to expect a wo:d count'
and starting address to be sent to it by the POT instruction.
The second EOM is an Input/Output mode EOM that specifies
the interrupt and the terminal function to be used. This EOM
also can specify a 15th address bit and five more high-order
word count bits expanding the word count from 10 bits to 15.
This sequence is written: EOM (Alert), EOM (I/O), and POT.
When the channel buffer is being set up at the same time, the
buffer control EOM can alert the interlace. When the buffer
is already set up, during a continuing I/O operation, the programmer may use the I/O EOM, ALERT CHANNEL (00250000),
to alert the interlace.
'
When the programmer does not desire to program the Extended Mode with the input/output terminal functions,
interrupts, and additional count or address, only the EOM
(Alert) and the POT are necessary to set up the channel
interlace (Compatible mode).

28

In the Extended Mode, the eight channels are programmed in the
same way, though there is a distinction between Channels W
through D and Channels E through H. The former group are TimeMultiplexed Channels; the latter are Direct Access Channels.
The Time-Multiplexed Channels use the memory logic of the
central processor to facilitate input and output of data words.
The transfer of each word between a time-multiplexed channel
buffer and memory requires two memory cycles. During this time,
computation stops in the central processor. Priority for the use
of the word input/output logic is in the order: Channel D, C,
Y, W. Any Time-Multiplexed Channel operating with interlace
has priority over the central processor for memory access.
Each Direct Access Channel has its own independent memory
logic. When memory access is needed to read or store a data
word, computation stops for one cycle. When two or more
Direct Access Channels require memory access simultaneously,
determination of priority is as described in Appendix A-19.
Transmission to and from Direct Access Chanl)els and core
memory are under the control of the channel. At the onset of
each memory cycle, the control unit interrogates all Direct
Access Channels to determine whether any channel requires a
transfer to or from computer memory; each channel gets priority
on the basis of need. If, during a channel transmission, a
transfer to or from computer memory is to take place, the computer connects the memory bank to the selected Direct Access
Channel. If, simultaneously, the computer requires access to
the same memory bank, the channel takes precedence and there
is a delay of one memory cycle. If the computer is not accessing the same memory bank as the direct access channel, the
transfer takes place without affecting computation speed. Thus,
internal computation and direct access channel transmissions
occur simultaneously and independently when the computer and
channel are accessing separate memory banks. Channel control
logic permits the transfer of only one word per memory cycle to
and from the computer memory independent of the number of
operating channels connected to the computer. Thus, the maximum transfer rate for the channel system is equa I to one word
every memory cycle, or approximately 572,000 words per second, or in excess of two and one-quarter million characters per
second for direct access channels.
COMMUNICATION CHANNEL DESCRIPTION
Figures 4-1 and 4-2 conta in block diagrams of the channels, the
functional control of information between the channels, the Data
Multiplexing System, the memory bank, and the external devices.
Up to 30 peripheral devices may be connected to one channel.
Each of these devices has a unique, two-digit, octal address
by which it is selected for an input/output operation. Toselect
the peripheral device, the program loads the proper unit address
into the 6-bit Unit Address Register (UAR) in the channel buffer.
Th is address selects both the device and, if appropriate, the function to be performed. Placing a non-zero unit address in the Unit
Address Register "connects" the peripheral unit addressed to the
channel and it becomes "active". When the UAR contains a zero
address, or any time that a termina lor initia I condition cl ears the
contents of UAR, the channel is "inactive." The zero in UAR also
means that it is not connected to a peripheral un it.
When the channel and the peripheral unit to be used have been
connected, the channel must have information pertaining to the
location in memory of the data to be transmitted or received
and pertaining to the number of data words in the transfer.

Channel W
Other
Sc

Communication

R

6-Bit + Parity

Channels

r .,
I
I

I

I
I
I
I

I
I
I
I

L..

U
A
R

6-Bit Unit
Function Address

W
A
R

Data

..J

rn

M
A
R

Add ress Li nes

I

Device
Control

(Y, C, D)

24-Bit

TMCC

Control Logic

Request

Control

Line

Unit

Address
Data

To
Memory
Via
CPU

Figure 4-1. SDS 930 Time-Multiplexed Communication Channel, Block Diagram
TIME-MUlTIPLEXED CHANNEL REGISTERS

the interlaced channel automatically places the word in memory when assembled.

In the Time-Multiplexed Channels W through D, there are two
registers important .to the programmer, the Word Assembly Register (WAR) and the Sing Ie-Character Register (SCR). The
WAR, a 24-bit, word-sized buffer, contains the word of data
actively being received or transmitted during an input or output operation. During input, 6-bit characters (plus parity)
enter the Single-Character Register where the channel buffer
assembles them, one at a time, into the WAR. Then the completed word is placed in memory. Depending on the number of
characters per word specified, the word assembled and placed
in memory during input has the form:
Word in Memory
One character per word mode
Unpredictable

I

o

1st

I

23

Two characters per word mode
Unpredictable

1

I

0

I

1st
11112

I

2nd
)18

I

23

Three characters per word mode
Unpred

I

5 16

1st

2nd

I

I

)12
Four characters per word mode

0

I
0

1st
I

)6

2hd
I

3rd
)18

3rd
)12'

I

)18

I

4th
I

When the end of an information record is detected by a buffer,
the buffer automatiCally disengages from the deviCe and is then
"ready" for another operation. The buffer logic is reset, except
that the state of the error indicator is maintained and the last
word of the input is still in the word register. If the number of
characters in the input record was not a multiple of the number
of characters assembled into each computer word, then zeros
are automatically forced into the least signifiCant positions of
the last' word. This last word can then be stored in memory by
a BUFFER INTO M WHEN READY WIM or YIM instruction
after the buffer has disengaged. If the number of characters in
the input record was a multiple of the number of characters assembled into each computer word, then the word remaining in
the W buffer is either the last group of characters from the input device; if they were not previously transferred to memory
by a BUFFER INTO M WHEN READY WIM or YIM, or zeros if
the last group of characters had been transferred to memory. In
either case, it is safe to issue one such instruction after the
buffer hilS disengaged without "hanging up" the computer.
During output, words come from memory into the WAR where
the chanriel buffer disassembles them into the SCR one 6-bit
character at a time. Depending on the characters per word
mode specified, the 6-bit characters within the word are output as follows:
Function

23

I

23

The unfilled character positions contain unprediCtable data.
When assembled during a single-word operatioh,a WIM instruction places the word into memory. Under interlace control,

Output one character from bits
o through 5
Output two characters from bits
o through 5, 6 through 11
Output three characters from bits
0-5,6-11, 12-17
Output four characters from bits
0-5, 6-11, 12-17, 18-23

Mode
One character per word
Two characters per word
Three characters perword
Four characters perword

29

the interlace allows any further data to fill the channel buffer
and generates the End-of-Word interrupt, if enabled.

As required, the characters are transferred into the SingleCharacter Register and output with generated parity. After
each character transfer, the word in the WAR is shifted left six
bits to be ready for the next transfer. Only those characters
needed from each word are used; when required, a new word
is brought to the WAR for the next character. For special
applications, a Time-Multiplexed Channel may be equipped
with a 12- or 24-bit Single-Character Register. The external
device which has a character size greater than 6 bits specifies
to the channel what its size is,12 or 24 bits. Standard 6-bit
devices are unaffected by the installation of a wider SCR.

The Memory Address Register (MAR) contains the starting destinationor source address in memory of the transmitted data. The memory locations to orfrom wh ich data words are to be tran'smi tted enter
the MAR at the same time the word count does. During transmission
of data, the interlace increments the contents of the MAR after each
word as it decrements the contents of the WCR. These two registers
provide the interlace control of block transmissions. The highorder 15th address bit comes from the second EOM, also.
DIRECT ACCESS CHANNEL REGISTERS

Interlace Regi sters
In the Direct Access Channels E through H, two other important registers are the Word Assembly Register (WAR) and the
Input/Output Register (JOR). The Word Assembl y Register is
a 24-bit word-sized buffer which, during a transmission, contains the information actively being transmitted to, or received
from, the external device. Information is assembled into, or
disassembled from, the WAR in one of four character sizes, 6, 8,
12 or 24 bits. The 6-bit mode is the normal mode of operation.
A device with a larger character size will send the channel a
signal to indicate its character size. It is the programmer's
responsibil ity to select a character/word count suitable for the
character size.

A channel interlace contains two working registers, the Word
Count Register (WCR) and the Memory Address Register (MAR).
In the set-up sequence -- EOM, EOM, POT -- for an interlaced input/output operation, the POT instruction transmits
to the interlace a data word made up of the word count (that
is, length) and the starting address of the data block. The
15-bit Word Count Register (WCR) contains the data word
count during a data transfer. The number of data words is
decremented by one and the new count replaces the old one
in the WCR for each word transmitted.
The count is assembled into the WCR from two places: the
least significant 10 bits is from the i'POTted" word and the
most significant 5 bits is from the "HI COUNT" field of the
second EOM. The form of the "POTted" word is:

Io

Word Count

(Time-Multiplexed channels can handle only 6-bit characters,
standard. There are, however, two options which will increase
the acceptable character size to 12 bits and to 24 bits. As with
the DACCs the external device signals the TMCC with its
character size.)

Start Address

I

I

When receiving 6-bit characters from a peripheral device
(operation is similar for other character sizes), the first character of a word enters the WAR into bit positions 18 through
23. When the WAR receives the next character, the first

23

When the word count is equal to zero, the transmission is complete. During output, .this causes a termination; during input,
Channel E
Character Input
6-Bit + Parity
(8-, 12-, 24-bit optional)

Other
Communication
I

o

Channels

Data

R ~~L~in-e-s-------'

(F, G, H)

Character Output
6-Bit + Parity
(8-, 12-, 24-bit optional)

I

Up to 30 I/O
U
__--~----~~A
Devices

R

W
C
R

~

Address

R

Lines

Address
Channel
Device
Control

Control Logic

Request
Line

Control
Unit

Data

Figure 4-2. SDS 930 Direct Access Communication Channel, Block Diagram

30

SOS
930
Memory
Modules

six bits in positions 18 through 23 shift into bit positions
12 through 17 and the incoming character is placed into bit
positions 18 through 23. The next incoming character causes
the two 6-bit characters in bit positions 12 through 23 to be
shifted to bit positions 6 through 17 and the incoming character
is placed into bit positions 18 through 23. The next character
causes another 6-bit left shift and then the character is placed
in the vacated bit positions 18 through 23. At this point, there
are 24 bits completely filling the WAR. This information is
now copied into the lOR to be placed into the proper memory
location.
The above procedure occurs when the programmer specifies
four characters per data word for the data transmission. If the
specification is three characters, the data word contains
three 6-bit characters in bit positions 6 through 23 and unpredictable information in bit positions 0 through 5 are transmitted
to the lOR. The next incoming character is accepted as the
first of another set of three characters. If the programmer
specifies two characters, the data word contains two 6-bit
characters in bit positions 12 through 23 and random data in
bit positionsO through 11 are transmitted to the lOR. If the
specification is one character, the data word transmitted to the
lOR contains only one character in bit positions 18 through 23.
When transmitting data using the character format mode, characters are taken from the WAR from the most significant end.
If the programmer specifies one character per word, the 6-bit
character in bit positions 0 through 5 is transmitted to the external device and then another full word of information is received from the lOR. If the programmer specifies two characters
per word, the 6-bit character in bit positions 0 through 5 is
transmitted. Then the contents of bit positions 6 through 23
shift left into bit positions 0 through 17, the new 6-bit character in bit positions 0 through 5 is transmitted and another word
is accepted from the lOR to be processed. If the programmer
specifies three characters, the 6-bit character'in bit positions
o through 5 is transmitted. The contents shift left six bits and
the new contents of bit positions 0 through 5 are transmitted.
The contents shift left six bits again and the third character
from bit positions 0 through 5 is transmitted. Then another
word is received from the lOR to be processed. If the programmer specifies four characters, the above process continues to
one more 6-bit left shift and the fina I six bits of the word are
transmitted before the next word is accepted from the lOR.
The Input/Output Register (lOR) is a 24-bit register which is a
full-word buffer between the WAR and memory. The Direct
Access Channel control unit places words into the lOR, await;"
ing their transfer to the WAR to be output. During input,the
lOR receives full words from the WAR and places them into
memory under control of the word count and memory address
being used in the transmission. During multiple data word
transfers, the WAR and the lOR simultaneously contain data
i nformat ion.

Bit
Octal Octal
Designation Position Value
00

B2

05

02

01-2

02

I/N

03

4

A I-bit in position 9 alerts
the buffer interlace.

00

03

o

Bit positions 10 and 11
contain the EOM mode indicator for the Buffer Control mode.

F/R

04

4

Bit position 12 specifies
the direction in which the
peripheral device will operate. A "0" specifies the
forward direction. A "1"
specifies the reverse
direction.

L/N

04

2

Bit position 13 specifies
whether the device should
be started with a leader as
in paper tape. A "0" specifies a start with leader.
A "I" specifies a start without leader.

D/B

04

Bit position 14 specifies the
mode of character format.
A "0" specifies BCD format.
A "1 " specifies Binary
format.

C/W

05

Bit positions 15 and 16specify the number of characters to be assembled into,
or disassembled from, each
transmitted word. One
character per word is specified by 00 (octal 0),
two by01 (octal 2), three
by 10 (octal 4) and four
by 11 (octal 6).

o

1 2 3
00
01

02

8 9 10 1112131415161718
03
04
05
06

2

4
6
UNIT

23
07

Channel W is numbered 00,
Channel Y is 01, Channel
C is 10, and Channel D
is 11.

o

The ENERGIZE OUTPUT M (EOM) used in the Buffer Control
mode addresses and connects the specified Channel W, Y, C,
or D, and selects the desired unit address. The detailed instruction format is:
Unit
I

Bit positions 1 and 17
specify the channel to
be activated.

Bl

COMMUNICATION CHANNEL PROGRAMMING

02
I

2

Function

06-7

Bit positions 3 through 8
contain 02, the instruction code for EOM.

Bit positions 18 through 23
specify the unit and the
function to be performed
with that unit.

31

Table 4-1.

00

Disconnect

40

01

Type Input No.

41

Type Output No.

02

Type Input No. 2

42

Type Output No. 2

03

Type Input No, 3

43

Type Output No. 3

04

Paper Tape Input No,

44

Paper Tape Punch Output No. 1

05

Paper Tape Input No. 2

45

Paper Tape Punch Output No. 2

06

Card Reader Input No.

46

Card Punch Output No.

07

Card Reader Input No: 2

47

Card Punch Output No. 2

10

Magnetic Tape Input No. 0

50

Magnetic Tape Output No. 0

11

Magnetic Tape Input No.

51

Magnetic Tape Output No.

12

Magnetic Tape Input No. 2

52

Magnetic Tape Output No. 2

13

Magnetic Tape Input No. 3

53

Magnetic Tape Output No. 3

14

Magnetic Tape Input No.4

54

Magnetic Tape Output No. 4

15

Magnetic Tape Input No. 5

55

Magnetic Tape Output No. 5

16

Magnetic Tape Input No.6

56

Magnetic Tape Output No. 6

17

Magnetic Tape Input No. 7

57

Magnetic Tape Output No. 7

20

60

High-Speed Printer Output No.

21

61

High-Speed Printer Output No. 2

22

62

23

63

24

64

Incremental Plotter Output No.

25

65

Incremental Plotter Output No. 2

66

Disc Fi Ie Output No. 1

26

32

Unit Address Codes

Disc File Input No.

27

Disc File Input No.2

67

Disc File Output No.2

30

Scan Magnetic Tape No. 0

70

Magnetic Tape Erase No. 0

31

Scan Magnetic Tape No.

71

Magnetic Tape Erase No.

32

Scan Magnetic Tape No. 2

72

Magnetic Tape Erase No. 2

33

Scan Magnetic Tape No. 3

73

Magnetic Tape Erase No. 3

34

Scan Magnetic Tape No.4

74

Magnetic Tape Erase No. 4

35

Scan Magnetic Tape No. 5

75

Magnetic Tape Erase No. 5

36

Scan Magnetic Tape No. 6

76

Magnetic Tape Erase No. 6

37

Scan Magnetic Tape No.7

77

Magnetic Tape Erase No. 7

EOD

Mnemonic

ENERGIZE OUTPUT TO DIRECT ACCESS CHANNEL

DSC
DSC
DSC
DSC
DSC
DSC
DSC
DSC

The EOD instruction used in the Buffer Control mode alerts
and connects the specified Direct Access Channel (E, F, G, H)
and the desired unit address. The instruction format is:
06

o

Unit

1 2 3

00

01

02

89101112131415161718
03
04
05
06

Bit
Octal Octal
Designation Position Value
Bl

00

B2

05

2

I

23
07

W
Y
C
D
E
F
G
H

Registers Affected:
Bit positions 1 and 17 specify the channel to be
activated. Channel E is
numbered 00, Channel Fis
01, Channel G is 10, and
Channel H is 11.

00200000
00200100
20200000
20200100
00600000
00600100
20600000
20600100

None

Timing:

ASC

ALERT TO STORE ADDRESS FROM CHANNEL
02

Several EOM and EOD function configurations have standard
uses. These have standard, assembler-type mnemonics and are
separate instructions.
.

23

ASC is always used in conjunction with PIN to determine the
current status of a peripheral operation being performed by the
selected channel. The two instructions are written together:

ALERT CHANNEL
02

12000

I

I

ASC alerts an interlaced channel so the PIN instruction
that follows can store the contents of the Memory Address
Register. This instruction affects the operation of the channel
in no other way. SE;le Direct Parallel Instructions, this section,
for a detailed discussion of PIN.

STANDARD EOM AND EOD CHANNEL INSTRUCTIONS

ASC

n

PIN

m, x

50000

I

23

ALC alerts the channel interla~e. This instruction does not
disturb the channel buffer in any way. ALC has no effect on
W or Y Buffers without interlace.

When the program executes these two instructions, the contents of the effective memory location designated by the PIN
instruction are:
Bit Positions

The channel Alerts are:
Mnemonic

Alert Channel

Instruction

ALC 0
ALC 1
ALC 2
ALC 3
ALC4
ALC 5
ALC 6
ALC 7

W

002-50000
00250100
20250000
202501OQ.
00650000
00650100
20650000
20650100

Y
C
D

E
F
G
H

Registers Affected:

None

Timing:

o through 9

Zero

10 through 23

Contents of channel's
Memory Address Register

1

TOP

00000

I

23

DSC disconnects the channel. It unconditionallysets the Unit
Address Register to 00 regardless of whether the channel iscurrently addressing a device. This instruction disconnects any
device which may be connected to. the channel. It also unconditionally makes the channel Ready (Inactive) and clears
the Error indicator.
.
.

o

0

Instruction

Channel

W
Y
C
D
E
F
G
H

ASC 0
ASC 1
ASC 2
ASC 3
ASC4
ASC 5
ASC 6
ASC 7
Registers Affected:

02

Contents

Mnemonic

DISCONNECT CHANNEL

I

0
1
2
3
4
5
6
7

Instruction

Function

All other indicators in the EOD are identical with EOM and
function in the same way.

ALC

Disconnect Channel

002 12000
002 12100
202 12000
202 12100
006 12000
00612100
206 12000
206 12100
Timing:

None

TERMINATE OUTPUT .oF CHANNEL

J

3

02

I

14000

8 9

I

23

When the last word of a block enters the channel, TOP terminates channel output. After the execution of this instruction,
the following occurs. When the channel buffer delivers the
last character to the peripheral device, the buffer disconnects.

33

TOP always terminates a non-interlaced channel output operation. It may be used with all communication channels if the
particular function selected is terminal function 11 but no
further data output is required (see Terminal Functions, this
section).

Mnemonic
TOP 0
TOPI
TOP2
TOP3
TOP4
TOP5
TOP 6
TOP7
Registers Affected:

Terminate Output
on Channel
W

Y
C
D
E
F
G
H

Instruction
002 14000
002 14100
202 14000
202 14100
00614000
006 14100
206 14000
206 14100

None

Bit.
Octal Octal
Designation Position Value

o
00
05

02/06

01-02 02/06

Bit positions 3 through 8
contain 02/06, the instruction code for EOM/EOD.

01

03

Bitpositions lOand 11 contain the EOM/EOD indicator for the Input/Output
control mode.

IA

04

COM PATIBLE/EXTENDED INPUT I OUTPUT MODES
The termination of an I/O operation and the interrupts that may
be associated with that termination fall into two classes: Compatible and Extended. The choice of one of these two "modes"
of input/output operation determines how the system behaves
when the termination of an I/O operation occurs.
As mentioned in Section III, Interrupt System, interrupts
occurring at the same level (e.g., location 30, 31, etc.) can
have different names (e. g., Count Equal Zero and End-ofWord). These names reflect the different I/O mode in operation when the interrupt occurs. The differences include the
timing of interrupt occurrence relative to the I/o operation
and type of interrupt requested.

In particular, the Interrupt Arm (IA) bit determines whether
any of the Extended functions operate; that is, a "0" in IA
means that the other Extended m~de controls, bits 13, 14, 15
and 16, have no effect.

INPUT IOUTPUT CLASS EOM/EOD
The Input/Output EOM (EOD) selects the I/O operation mode.
When the Extended mode is selected, this EOM also selects
(arms) which interrupts are tobe operational and selects the
desired terminal function. This EOM appl ies to Channels W, Y,
C, and D. EOD appl ies to Channels E, F, G, and H.

34

2
1

4

Bit positions 1 and 17 specify the chcnnel.

Bit position 12 selects the
mode of I/O operation. A
"0" specifies the Compatible
mode. The operation of bits
13, 14, 15, and 16aredisallowed. ChannelsW, Y, C
and D operate in this mode
which iscompletelySDS 920compatible. If interrupts
are required, the user enables
the Interrupt System, thus
enabling and arming the
End-of-Word and End-: in this section.

The unbuffered card punch operates similarly.
It generates the End-of-Record response after
punching each row. If any faults occur
during the punch ing of the entire card, the
card punch sends a signal to the channel
that sets the channel error indicator; th is
occurs after punching the last row (row 9).
NOTE:

Bit position 18 is the
high-order address bit.

A

HI Count

Bitpositions 19 through 23
contain the most significant four bits of the 15bit word count. These
positions specify a word
count greater than 1023.

Bit
Octal
Configuration Value
IOSD

A 2-bit function code in the Input/Output EOM (EOD) controls the termination of input/output operation in the extended
mode. These functions are described below with the letter C
representing the specified word count of the transmission.
Bit
Octal
Configuration Value
INPUT/OUTPUT OF A
RECORD AND DISCONNECT
Input

Output

00

Write C words. When C equals zero, output
is terminated (i. e./the device is signaled
that the last characters have been transmitted). When the peripheral device has
generated the end of record and, if necessary, checked the validity of the record, it
sends an End-of-Record response to the
Channel buffer. When received by the
buffer, the End-of-Record signal gener'ates
an End-of-Record interrupt (if armed) and
disconnects the channel.
The I ine printer generates the End-ofRecord response when it completes the
printing of a I ine. If the printer encounters
any print errors or faults, it sends a signal to
the channel that sets the channel error indicator; th is can occur since the printer has

01

2

Write C words. When C equals zero and
when the lost character has been transm itted,
the channel disconnects the device and becomes inactive. If an End-of-Record signal
is received before the count reaches zero,
the channel will disconnect immediately.

o

Read C words. If C equals zero before the Endof-Record is detected, the rest of the record is
ignored. At the End-of-Record, the peripheral
device is disconnected and the channel becomes
inactive.

INPUT/OUTPUT UNTIL SIGNAL
THEN DISCONNECT

Read C words. When C equals zero or when
the End-of-Record is encountered, the device
is disconnected and the channel becomes inactive. If the channel disconnects because
of a zero count,an EOR interrupt (if armed)
will be generated in addition to the count
equal zero interrupt. If both are armed,
C=O will occur first.

TERMINAL FUNCTIONS; EXTENDED MODE

lORD

A program should not use lORD with devices that do
not have End-of-Record conditions on input (e. g.,
typewriter) or generate End-of-Record responses upon
output term ination, (e. g., devices such as the paper
tope punch and typewriter). These devices do terminate output but give the program no indication
when they receive the last characters.

NOTE:

IORP

The IOSD is designed for use on devices which are
normally operated on the basis of the word count
only. Typewriters and paper tape devices are of
th is type, as are the printer and card punch when the
user does not wish to stay connected until the operation is complete.
INPUT/OUTPUT OF A
RECORD AND PROCEED

10

4

Read C words. If the channel counts C down
to zero before the peripheral device encounters the End-of-Record (EOR), the channel
ignores the rest of the record (to the End-ofRecord). When the peripheral device sends
the End-of-Record signal to the channel, the
channel sets its End-of-Record Indicator; this
signal sets the End-of-Record interrupt (if
armed). The channel does not disconnect.
The channel is now in on "Inter-record"
condition.

35

When the peripheral device is magnetic tape,
the tape continues to move when the tape
handler encounters the End-of-Record. The
End-of-Record occurs when the tape readheads encounter tape gap; this also causes a
If the
Tape Gap signal to "come high".
program executes a new read tape or scan
tape EOM during the inter-gap time (approximately .75 millisecond while the Tape Gap
signal is high), the tape remains in motion
and proceeds to read or scan the next record.
If the program executes no such EOM before
the Tape Gap signal drops, the channel disconnects and the tape comes to a stop. No
additional interrupt occurs. This is the only
condition that causes a channel to disconnect
automatically.
All other input devices remain connected until
the program takes further action. The paper
tape reader remains in motion; the program
should issue a "disconnect channel" instruction if the program is not reading any more
tape. To proceed after the End-of-Record
occurs, the program first executes a Buffer
Control mode EOM to re-initiolize the Channel Unit Address Register and then reloads the
interlace portion of the channel (the progral'T]
can alert the Interlace via the Buffer Control
EOM). Otherwise, the channel immediately
terminates any attempt to use its interlace
portion since the channel is aware that it is
still active and in the End-of-Record condition. When the program continues from an
Inter-record condition,the program shou Id use
an extended mode terminal function. An
IORP should not be used to read devices which
do not have EOR signals (e. g., the typewriter
and paper tape reader).
Write C words. When the channel interlace
counts C down to zero, the Interloce notifies
th~ channel buffer that it has received the
last word that is to be output; when the buffer
outputs this last word, it sends a signal to the
connected peripheral device indicating that
the device has the last word now. When the
peripheral device "receives, outputs ond
checks the validity of" this last word, it sends
an End-of-Record response to the channel
buffer. When received by the buffer, the
End-of-Record signal generates an End-ofRecord interrupt (if armed) and sets the Interrecord indicator; the channel does not
disconnect.
When the peripheral device is magnetic tape,
the tape continues to move after it signa Is
End-of-Record. As in reading tape, the signal causes the Tape Gap signal to come high.
If the program executes a new write tape or
erase tape EOM during the inter-gap time
(approximately one millisecond), the tape remains in motion and proceeds to write or erase
a new record. If the program executes no
such EOM before the Tape Gap signal drops,
the channel disconnects and the tape comes to

36

a stop. No interrupt occurs at this time. This
is the only condition which causes a channel
to disconnect automatically.
To proceed after the End-of-Record occurs,
the program first executes a Buffer Control
mode EOM to re-initialize the Channel Unit
Address Register and then reloads the interlace portion of the channel (the program can
alert the Interlace via the Buffer Control
EOM). Otherwise, the channel immediately
terminates any attempt to use its interlace
portion, since the channel is aware that it is
still active and in the End-of-Record condition.
When the program continues from an Interrecord condition, the program should use an
extended mode terminal function.
A program should not use IORP with devices
that do not generate End-of-Record responses
upon output termination; such devices are
paper tape and typewriter. These devices do
terminate output but give the program no indication when they receive the last characters.
The IORP should also not be used with the printer
and card punch since these devices expect the
channel to disconnect after they send EOR.
IOSP

INPUT/OUTPUT UNTIL
SIGNAL THEN PROCEED

Bit
Configuration

11

Octal
Value

6

Read C words. If the channel counts C down
to zero before the periphera I device encounters the End-of-Record, the channel generates
a Count Equals Zero interrupt (if armed). The
program should reload the interlace portion of
the channel to continue reading the record.
As far as the peripheral device knows, nothing
happens at this time. Failure to reload the
Interlace before the peripheral device sends
enough characters to overfill the channel
buffer causes a rate error; th i s sets the channe I
error indicator.
When the peripheral device encounters the
End-of-Record, IOSP operates identically
Iike the IORP command.
Write C words. When the channel counts C
down to zero, the cbannel generates a Count
Equals Zero interrupt (if armed); the channel
does not terminate output. The program should
reload the interlace portion of the channel to
continue writing in the same record. Fai lure
to reload the Interlace before the buffer transmits all of the characters in its registers and
before the peripheral device requests the next
character from the buffer results in a rate
error; this sets the channel error indicator.
If the program executes a TERMINATE OUTPUT
(TOP) instruction after the channel has counted
C down to zero, the channel terminates the
output and operates identically like the IORP
from this point on.

CHANNEL AND DEVICE SKS
Mnemonic
The Channel and Device Test mode SKIP IF SIGNAL NOT SET
(SKS) tests the indicators in a channel as well as devices attached to it. To test the channel, use unit address 00. The
instruction format is:

CAT
CAT
CAT
CAT
CAT
CAT
CAT
CAT

CHANNEL TESTS
40

o

1 2 3

00

I

I

8910112131415161718
23
01
02
03
04
05
06
07
00
Bit
Octal Octal
Designation Position Value
Function
01-02

40

01

03

Cl
C2
C3

03
00
05

40

Bit positions 10 and 11
contain the mode selection.
4
2
1

R

C

Bit positions 3 through 8
contain 40, the SKS instruc tion code.

BitsCl, C2, C3, usedasan
octal address, specify the
channel to be tested. Channel W is 0, Channel Y is I,
and soon, Channel H being 7.

04

2

E

4

00

Test for Inter-record
condition.
Bit positions 18 through 23
are zero to spec ify a channel test. Each of these tests
causes a skip when the test
condition is true.

Several SKS function configurations have standard uses. These
have standard, assembler-type mnemonics and are always used
as shown.
CHANNEL ACTIVE TESTi

0

J

3

40

I

None

Timing: 2, ifnoskip
3, if skip

BRTW

04021000

W BUFFER READY TEST

BRTY

0 40 22000

Y BUFFER READY TEST

Registers Affected: None

Timing: I, if no skip
2, if skip

The indicator that CAT tests is reset only by the next EOM that
connects and alerts the same channel.
CHANNEL ERROR TEST;

40

11000

I

I

I

23

CET tests the error indicator in the channel for being in the set
condition. If the error indicator has not been set, the computer skips the next instruction in sequence and executes the
following instruction. If the error indicator has been set, the
computer executes the next instruction in sequence.
Channel
Error Test

Mnemonic
CET 0
CET 1

W

CEl
CET
CET
CET
CET
CET

2

C

3
4
5
6
7

D
E
F
G
H

Reg isters Affected:

SKIP IF CHANNEL NOT ACTIVE

o

040 14000
04014100
240 14000
24014100
04054000
04054100
24054000
24054100

The following SDS 920- compatible instructions make the identical test as the above instructions on Channels Wand Yi

Test if indicator for Word
Count Equal to Zero is set.
A I-bit selects the test.
Skip if word count zero.

STANDARD SKS INSTRUCTIONS

CAT

W
Y
C
D
E
F
G
H

SKIP IF NO ERROR ON CHANNEL

Test for error indicator reset. A I-bit selects the
test. Skip if no error.
05

Instruction

0
1
2
3
4
5
6
7

Registers Affected:

CEl

Test for ready. A 1-bit
selects the test. Skip if
Ready or Inactive.

Channel
Active Test

Y

None

Instruction
040 11000
040 11100
240 11000
24011100
04051000
04051100
24051000
24051100
Timing: 2, ifnoskip
3, if skip

The following SDS 920-compatible instructions make the identical test of Channels Wand Y:

14000

I

23

If the channel is ready to accept a new input/output instruction, the computer skips the next instruction in sequence and
executes the following instruction. If the channel is active,
or in the process of disconnecting a peripheral unit, the computer executes the next instruction in sequence.

BETY

04020020

Y BUFFER ERROR TEST

BETW

04020010

W BUFFER ERROR TEST

Registers Affected:

None

Timing: I, if no skip
2, if skip

The indicator that CET tests is reset only by the next EOM that
connects and alerts the same channel.

37

CZT

CHANNEL ZERO COUNT TEST;

DEVICE TESTS

SKIP IF CHANNEL WORD COUNT IS ZERO

The SKIP IF SIGNAL NOT SET (SKS) below, used in the
Channel and Device Test mode, tests the condition of the peripheral devices in the system directly. The peripheral device
sections contain the individual instruction descriptions.

40

12000

I

I

I

23

CZT tests whether the contents of the Word Count Register in
the channel have been reduced to zero. If the contents of
WCR are zero, the computer skips the next instruction in sequence and executes the following instruction. If the contents
of the WCR are non-zero, the computer execute~ the next
instruction in sequence.
Mnemonic

Channel Zero
Count Test

Instruction

CZTO
CZTl
CZT 2
CZT 3
CZT 4
CZT 5
CZT6
CZT 7

W
Y
C
D
E
F
G
H

04012000
040 12100
24012000
240 12100
04052000
04052100
24052000
2 4052100

Reg isters Affected:

None

01
Bit
Designation

Octal Octal
Position Value

Cl

03

4

Bit positions 9, 1, and 17
are used as an octal digit
to specify the channel.

C2

00

2

Channel W is 0, Channel
Y is 1, and so on.

C3

05

40

01-02

01

03

Bit positions 10 and 11 contain the mode selection.

Unit Tests

04-05

Bit positions 12 through 16
sel ect the particular test
and are system dependent.

Un it Add ress

06-07

Bit positions 18 through 23
spec ify the un it address.

40

CHANNEL INTER-RECORD TEST i
SKIP IF INTER-RECORD INDICATOR IS SET
40

10400

I

I

I

Mnemonic
CIT
CIT
CIT
CIT
CIT
CIT
CIT
CIT

Channel InterRecord Test

0
1
2
3
4
5
6
7

Registers Affected: None

W
Y
C
D

E
F
G
H

Bit positions 3 through 8
contain the SKS instruction
code 40.

SINGLE·WORD DATA TRANSFER VIA CHANNELS WAND Y
23

CIT tests the Inter-record indicator in the selected channel. If
the Inter-record indicator is set, the computer skips the next
instruction in sequence and executes the follow ing instruction.
If the ind icator is reset, the computer executes the next instruction in sequence. (See IORP instruction description under
TERMINAL FUNCTIONS for Inter-record definition).

Instruction
040 10400
040 10500
240 10400
240 10500
04050400
04050500
24050400
24050500
Timing: 2, if no skip
3, if skip

The Inter-record indicator is set only during extended mode operation when using a Proceed Function; the indicator is set for
an inter-record or zero count condition, The indicator is reset
by the next alert and connect EOM.

38

3

Timing: 2, if no skip
3, if skip

The indicator that CZT tests is reset only by a POT instruction
to set up the word count and data address in the same channel.
CIT

40

INSTRUCTIONS
Channels Wand Y can be programmed as single-word input/
output buffers. Data transfer is performed under direct program
control or with the aid of the interrupt system. Interlace is
not used with these instructions.
The following two instructions perform data transfer using
Channel W.
MIW

MEMORY INTO CHANNEL W WHEN EMPTY
12

o

1 2 3

II I

M

8 9 10 I

23

MIW transfers the contents of the effective memory location
into the Channel W word buffer. If necessary, the central
processor "hangs up" until the buffer is empty and ready to
accept the data word.
The W buffer must be connected to the desired peripheral device by a previous "connect" EOM instruction that selects the
buffer, the unit address, and all appropriate control functions.
Registers Affected:

None

Timing: 2 + wait

WIM

o

CHANNEL W INTO MEMORY WHEN FULL

1 2 3

32
I

SINGLE-WORD OPERATIONS

M

23

8 9 10

WIM transfers contents of the Channel W word buffer into the
effective memory location. If necessary, the central processor
"hangs up" until the buffer is full and ready to deliver the
data word.
Registers Affected: M

MIY

MEMORY INTO CHANNEL Y WHEN EMPTY

M

10

o

Tim ing:3 + wait

123

I

23

MIY transfers the contents of the effective memory location
into the Channel Y word buffer. If necessary, the central
processor "hangs up" until the buffer is empty and ready to
accept the data word.
Registers Affected:

YIM

None

Use of the priority interrupt system el iminates the tie-up of the
central processor. The interrupt system allows the program to
connect the device to be used in the transfer, to enable the
interrupt, and then to continue processing in the main program.
When the buffer is ready to receive from, or transfer to,
memory, the End-of-Word interrupt to the corresponding
interrupt location notifies the program that the buffer is Ready.
A service routine entered via a BRANCH AND MARK PLACE
(BRM) instruction in the appropriate interrupt location processes
the interrupt. This routine contains the instruction (MIW or
WIM, for example) that can execute immediatel y without computer tie-up.
During single-word operations, a parity error or incorrect
timing error sets the buffer error indication in the channel.
The incorrect timing error occurs when characters enter the
buffer during input before the removal of the previous word;
during output, buffer error indication occurs if characters are
needed for output before the buffer rece ives the next word.
The transmission does not terminate upon detection of any of
these errors.

Timing: 2 + wait

CHANNEL Y iNTO MEMORY WHEN FULL
M

30

o

The single-word buffer operations are used in two ways. Data
words transfer between the channel and memory under direct
program control. The "connect" EOM and the input or output
channel instruction are in sequence and the computer "hangs
up" until the buffer is ready to perform the transfer. This delay
is usually due to buffer tie-up while the buffer is actively
transmitting or receiving the previously requested data word.

1 2 3

I

23

8 9 10

YIM transfers the contents of the Channel Y word buffer into
the effective memory location. If necessary, the central processor "hangs up" until the buffer is full and ready to del iver
the data word.
Registers Affected:

M

Timing: 3 + wait

The interrupt system can detect an End-of-Record termination.
During output, use of TERMINATE OUTPUT (TOP) after the
final MIW (MIY) causes an interrupt to the appropriate End-ofTransmission location when that final data word has been processed by the buffer. This interrupt takes the place of the
End-of-Word interrupt; the End-of- Transmission condition
inhibits the End-of-Word interrupt. During input, the End-ofTransmission interrupt is sent to the End-of- Transmission location when the End-of-Record is detected. During input from
devices which do not generate an End-of-Record, an EOM
disconnects (DSC) the channel to terminate the transmission.
This termination generates no End-of- Transmission interrupt.

39

EXAMPLE:

WIM
This program reads a block of binary paper tape of any length, using the W buffer without interlace. There is an
integral multiple of four characters in the block. This subroutine uses the End-of-Word and End-of-Transmission
interrupts of the W buffer and reads data into memory beginning in a table at location 1024.

Location

Instruction

H

PZE

This is an assembler instruction used to reserve the entry
location by filling H with Zero.

EIR

This instruction enables the interrupts. An End-of-Word
interrupt will be received after each word is assembled in
the W buffer.

TABLE

Comments

RPT

0, I, 4

This instruction initiates the paper tape read on Channel
W, four characters per word (see Paper Tape Input/
Output, this section).

BRR

H

Return to the main program while awaiting the filling of
the buffer with the first word read from tape.

00002000

This location contains the input table starting address.

When the buffer fills with the first word, it generates the End-of-Word interrupt to location 31.

31

BRM

HI

PZE

HI

This branch and mark instruction transfers to the read
routine.
Reserved entry location.

WIM

*TABLE

This instruction transfers the contents of the W buffer into
the location specified in the contents of location TABLE.
The * indicates indirect addressing. If desired, indexing
can be used.

MIN

TABLE

This instruction increments the location for the next
input word.

BRU

*Hl

This instruction transfers indirectl y back to the main program to await the next End-of-Word interrupt and clears
the currently active interrupt.

The above procedure continues until the end of the block. When gap is detected, the remaining character
positions of the word being assembled in the buffer fill with zeros, and the End-of- Transmission interrupt to
location 33 inhibits the End-of-Word interrupt.

33

BRM

H2

PZE

H2

This instruction transfers and marks to location H2.
This instruction reserves an entry location.

BET

o

This instruction tests for the occurrence of an error
during the input operation. If there were none, the
next instruction is skipped and the following one is
executed.

BRM

ERR

This instruction transfers to an assumed error routine.

BRU

*H2

This instruction returns to the main program.
operation is complete.

The read

Since in this example the input record has integral word-length, no characters are i~ the buffer when the
End-of-Record is reached. If there are one, two, or three characters in the buffer when it detects the gap,
an additional WIM has to be executed to place these characters into memory.

40

DIRECT PARALLEL INPUT/OUTPUT INSTRUCTIONS

POT

Two instructions, PARALLEL OUTPUT (POT) and PARALLEL
INPUT (PIN), permit any word in core memory to be presented
in parallel at a connector; or, inversely, permit signals sent to
a connector to be stored in any core memory location. The
execution of a POT or PIN instruction causes a signal to be
sent to the external device involved in the input/output operation. This signal notifies the device to send its data word as
soon as it is operational. When the device becomes operational
during a Read or PIN operation, it transmits a Ready signal to
the central processor while at the same time presenting its data
word. The computer places the received data word into a
specified memory location without disturbing any arithmetic
registers. The computer "hangs up" during the execution of
PIN until it receives the Ready signal from the external device.
During the execution of a POT instruction, . the central processor transmits a signal to the external device, alerting it to
receive a data word. When the device becomes operational,
it transmits a Ready signal to the central processor, which
releases the data word to the external device. The computer
"hangs up" during the execution of POT until it receives the
Ready signal from the external device.
For special system requirements, POT ond PIN cart be used
effectively with other instructions to produce high-speed,
synchronized, data transfers between the central processor and
external devices without the use of 0 communication c~annel.
Selective input/output to and from these devices is accomplished by precedingPOTor PIN with an EOMto alert the
desired device by specific address. By preceding the POT or
PIN with an SKS, the Ready signal of the special device can
be tested after the execution of the EOM but priorto execution of the parallel transfer instruction; a possible computer
"hang-up" can thereby be avoided. If the Ready signal from
the external dev ice sets one of the priority interrupts, parallel
input/output operation can occur os soon as the external device
is able to transmit or receive. Since the Ready signal initiating
the interrupt is present through the POT or PIN execution, no
computer" hang-up" occurs.
PIN

PARALLEL INPUT

33

o

1 2 3

I

,

13

o

12 3

M

8910

23

POT transmits the contents of the effective m,emory location in
parallel to 24 output I ines of an external device.
Registers Affected: None

Timing: 3 + wait

SINGLE-BIT INPUT IOUTPUT
Operating in the System mode, the two instructions, ENER""
GIZE OUTPUT M (EOM) and SKIP IF SIGNAL NOT SET (SKS),
provide single-bit input/output transmissions.
Execution of a System Mode EOM causes a signal of approximately 1.4 microseconds to be transmitted to one of a possible
16,384 signal destinations. The System Mode EOM format is:

EOM

ENERGIZE OUTPUT M

02

o

1 ,2 3

I

23

Bit position 3 through 8 contain the EOM instruction code, 02.

Bit positions lOand 11 contain the System Mode indicator.

Bit positions 12 through 23 contain the 12-bit address field
that specifies the special system destinations.

Bit position 2 contains O.

M

8 9 10

23

PIN stores the contents of 24 input I ines in parallel in the
effective memory location.
Registers Affected: M

PARALLEL OUTPUT

Timing: 4

+ wait

Bit positions 0 and 1 are reserved for special system address
bits.
Registers Affected: None

Timing: 1

41

Execution of a System Test Mode SKS causes a 14-bit address
to be presented to the collection of special system devices.
If the addressed external device is supplying a set signal to the
central processor, the computer executes the next instruction
in sequence from the SKS. If no signal is set, the computer
skips the next instruction in sequence and executes the following instruction.

COMMUNICATION CHANNEL PROGRAMMING
EXTENDED MODE
Programming a block transmissionof data using the full facil ity
of the input/output system includes these instructions: EOM
(Alert), EOM (I/o Control), and POT (PARALLEL OUTPUT).

The SKS System Test format, which has each corresponding
bit-set identical to the System EOM format, is:
SKS

II o

SKIP IF SIGNAL NOT SET

01

1

1 2 3

I

40

I

23

Registers Affected: None

Timing: 2, if no skip
3, if skip

A sample sequence of instructions from a magnetic tape read operation follows.

The octal configuration

of each instruction is given.

42

Location

Instruction

1000

00242610

This EOM specifies Channel W, bits 1 and 17, (no 2 in
00, no 1 in 05) alerts the interlace, bit 9 (a 4 in 03)
is in the Buffer Control mode (no 2 or 1 in 03) specifies
forward direction of tape motion with no leader and BC D
character format; bits 12, 13, 14, (a 4, no 2 and no 1
in 04) selects four characters per word.assembly mode,
bits 15, 16, (a 6 in 05) and connects the unit function
address 10 to read tape nu mber O.

1001

002 15001

This EOM is in the Input/Output Control mode, selects
the channel interrupt mode, bit 12,(a 4 in 04) disarms
the End-of-Record interrupt, bit 13, (no 2 in 04) arms
the Zero Count interrupt, bit 14, (a 1 in 04) selects
terminal function 00, bits 15, 16, (no 4 or 2 in 05) and
specifies high order word count of 01 (bits 20 through 23).

1002

031 01020

This POT transmits to the channel the contents of location 1020. The location contains the word count and
the starting location for data input.

1020

003 13500

Bit positions 0 through 9 of this location contain the low
order 10 bits of the word count. Bit positions 10 through
23 contain the 14 bits of the starting address

Comments

The channel assembles the starting address from the EOM, bit
18, and from the word transmitted by the POT. In this sample,
the starting address for the read operation is 135008. The word
count is assembled from the same EOM, bits 19 through 23, and
from the word transmitted by the POT. In this sample, the word
count is 020068' This is assembled as follows. Bits 19 through
23 of the EOM in location 1001 are 00001; bits 0 through 9 of
the transmitted word are 0 000 000 110. Assembling these bits
into one 15-bit count, 000010 000 000 110, the word count
becomes 02006 8 ,

These three instructions read one magnetic tape record of 2006word length into memory starting at location 13500. When the
word count equals zero during the transmission, an interrupt is
sent to Channel W interrupt level 31. Any further information

is ignored and when the tape reaches the End-of-Record, it is
stopped, disconnected, and the channel becomes inactive.
COMPATIBLE MODE
In the Compatible mode of channel operation, the second EOM
may be omitted if the word count is less than 1023 (17778)
words and the starting addresses are less than 16383 (377778)'
The End-of-Word and End-of-Transmission interrupts are used
when interrupts are desired. They can be armed/enabled or
disarmed/disabled by the Enable/Disable instructions. Since
the Extended input/output functions that are specified in the
second EOM cannot be used, the latter two interrupts are used
along with SKS tests to determine the terminal conditions of
input/output transmissions. This I/O mode operates onl y for
Channels W, Y, C, D.

A sample line print sequence programmed in the compatible mode follows:

Comments

Location

Instruction

1000

00242660

This EOM specifies Channel W, alerts the interlace, specifies four
characters per word, and connects the unit function address 60 for
Pr inter N umbe r 1.

1001

031 01030

This POT transmits to the channel the contents of location 1030.

1030

02042000

The location contains the word count and the starting address for
outpuL Bits 0 through 9 contain the word count of 41 8 ; the starting address is 20008 ,

Since the input/output facil ity is less comprehensive in this
mode, the user should be aware of the terminal conditions that
will occur. For output, the mode is equivalent to functions 00
and 01; tha't is, when C words have been transm itted, the output
terminates, and when the last character has been sent, the device disconnects. If the interrupt system is enabled, an Endof-Transmission interrupt to location 33 occurs when the device
disconnects. No interrupt occurs on level 31.

For input, this mode is equivalent to functions 00 and 01 if the
End-of-Record is encountered before the word count is reduced
to zero. If the word count is reduced to zero before the Endof-Record is encountered, the interlace portion of the channel
disengages all control of the channel buffer. The buffer con-

tinues to assemble characters until a word is completed. If the
interrupt system is enabled, the buffer then generates an Endof-Word interrupt on level 31. The program has approximatel y
1.5 character times to reload the interlace if reading is to continue. On Channel W (or Y) the contents of the buffer at this
time can be stored with the WIM (YIM) instruction.

If this form (EOM, POT) is used with Channels E through H,
the Terminal Function mode is 00 with no interrupts armed.

This mode of channel operation should generally not be used
on input unless the record length of the input records is fixed
and known.

43

CONTROL CONSOLE
The basic SDS 930 Computer System providesa console for operator control. This console connects directly to the centra I processor, contains switches for operation, and displays the contents of
operationa I registers.
DISPLAYS
The registers displayed on the console directly reflect the contents
of the hardware registers. If the operator changes or clears a disp lay, the contents of the actua I register a Iso change identica lIy.
PROGRAM LOCATION
The program counter is a 14-bit register that contains the location
of the next instruction to be executed. The programmer may change
the counter by inserting a BRU into the Instruction Register and executing it. When the computer is in the ID LE state, this register
displays the location of the instruction to be executed next.
INPUT/OUTPUT
The UNIT lights contain the unit address of the peripheral device
currently connected to the selected channel.
The ERROR light reflects the status of the channel error indicator. Setting the I/O DISPLAY SELECT thumbwheel switch selects the channel to be displayed.
MEMORY EXTENSION
There are two memory extension indicators. The left one lights
when EM3does not contain three (3); the right one lights when
EM2 does not contain two (2).

To change the contents of the selected register, press the indicator
button(s) in the corresponding bit posi tions. The computer must be
in the IDLE state and the registerpreviouslycleared. Pressing a
button places a l-bit into the selected position of the register.
MEMORY PARITY
If an operand or instruction access from memory encounters a
parity error, this light turns on. Setting the MEMORY PARITY
switch to CONTINUE clears the indicator and turns off the light.
INTERRUPT ENABLED
The INTERRUPT ENABLED light is on whenever the interrupt
system is enabled.
SWITCHES
POWER
The POWER switch turns the computer system power on or off.
When power is on, the switch is lit.
FILL
The operator has the option of four input media to initially load
or "fi II" the computer. The pairof three-position, spring-loaded,
center-return, toggle FILL switches are labeled: PAPER TAPE ~
MAG TAPE and CARDS-DRUM. For example, to select and initiate filling from paper tape on Channel W, set the first toggle
switch to PAPER TAPE and release.
The fill procedure is:
a)

Set up the selected input device with the input program. The initial portion of the program contains the
"bootstrap" (the short-load program).

b)

Set the RUN-IDLE-STEP switch in the IDLE position.

HALT
The HALT light is on whenever the computer executes an HLT
instruction while in the RUN position. To clear this indicator,
set the RUN-IDLE-STEP switch to IDLE.
OVERFLOW
This display shows the status of the Overflow Indicator.
REGISTER DISPLAY
This display consists of 24 binary indicators with a clear button
for the entire register and a set button for each indicator. The
REGISTER thumbwheel switch selects the internal register whose
contents are to be displayed. The selectable registers are:

44

C

C Register, which contains the full instruction immediately prior to its execution

A

A Register

B

B Register

X

Index Register X

c)

Press the START switch.

d)

Set the RUN-IDLE-STEP switch in the RUN position.

e)

Press one of the four FILL switches. This will cause a
WIM 2 (03200002) instruction to be inserted into the
Instruction Register and will load the Index Register
with 77777771. Depending on which switch is pressed,
activation of one of the following four devices on
Channel W will occur:
Paper Tape Reader No. 1 - Unit Address 04
Card Reader No. 1 - Unit Address 06
Disc Fi Ie No. 1 - Unit ,Address 26
Magnetic Tape Unit No. 0 - Unit Address 10
The FILL switch also prepares the channel to operate
in the forward, binary, four characters per word mode.

A "bootstrap" program must be in position to be read as the first
input from the device. A typical bootstrap program is:

- - - - I',PUT OUTPUT - - - -

_II
~

flUltlP!
'.;.4'

._--- --

- - - - - - PROCRAM lOCA110N

t'A'VTY'

M.

2Z

POWER

I

e
\

.

REGIS1ER

- - - - - - - - - - - - - - - - - R[GISIER !)ISPlAY - - - - - - - - - - - - - - - - -

WIlOflY

H' 1

0

0
~q

Figure 4-3. SDS 930 Control Panel

"'P"ORY tUM

13

lOt!

location

Instruction

Address

00002

WIM

00012, 2

00003

BRX

00002

00004

LDX

00011

00005

WIM

00000, 2

00006

SKS

21000

00007

BRX

00005

00010

BRU

BEGIN

00011

OCT

Starting address with
indirect address "tag"

The WIM 00002 instruction that is forced into the Instruction
Register stores the first word of the" bootstrap" program in
location 2. The computer then executes the contents of
location 2. The Index Register, which contains -7, modifies
the WIM in 2. The effective address of the WIM is then 00003
so that the second word is stored in3. This word is a BRX back
to the WIM.

I/O DISPLAY SELECT Switch
This eight-position, thumbwheel switch selects the channel
from which the unit address and error indicator are displayed
in the INPUT-OUTPUT lights.
INTERRUPT ENABLED Switch

If this switch is in the COMPUTER position, the Interrupt
System may be enabled or disabled under program control.
Placing the switch in the ENABLE position enables the Interrupt
System regard less of program operations. The switch is stationary in the COMPUTER position and momentary in the ENABLE
position.
MEMORY PARITY Switch
If this switch is in the HALT position, the computer enters an
Idle state whenever a memory parity error occurs. If this
switch is in the CONTINUE position, the computer does not
change state when memory parity occurs.
BREAKPOINT Switches

These two instructions then load the remainder of the "bootstrap"
program. The remaining six words can be those needed for the
specific loading that is to be done. The one shown loads a
record of any length. The Buffer Ready test in location 6 skips
when the End-of-Record has been reached. In "bootstrapping"
from paper tape or magnetic tape, the record may be of any
length. From cards, the record is 40 words.
RUN-IDLE-STEP Switch
This is a three-position, toggle switch with two stationary
positions and a spring-loaded, momentary position in STEP.
In the RUN position, computation occurs at machine speed.
In the IDLE position, the computer idles immediate Iy after an
instruction has been read from memory. If the REGISTER switch
is in the "C" position, the REGISTER DISPLAY shows the complete instruction. In the STEP position, the computer executes
the instruction and returns to the Idle state. Release the switch
to the IDLE position before performing another step.
HOLD Switch

The program may detect the status of these four switches by
using a breakpoint test. The switches, labeled RESET and SET,
control pre-determined options within the program.
MEMORY CLEAR Switches
To clear first 16 K words of memory, press the START switch and
then press both MEMORY CLEAR switches simultaneously. To
clear from 16 K through 24 K, set the Extend Memory Registers
EM2 = 4 and EM3 = 5, then press these two switches simultaneously. To clear from 24 K to 32 K, set EM2 = 6 and EM3 = 7,
then press both switches simultaneously.
INPUT/OUTPUT TYPEWRITER
The control console contains an electric, input/output typewriter for operator control, error or status messages, and simi lar
functions. The Typewriter is connected to Channel W, has the
input unit address 01, and the output unit address 41. Appendix
A -1 Iists the typewri ter codes.

When the HOLD switch is on, the current contents of the
program counter are he Id. Instructions inserted into the C
Register and executed do not step the program counter (i.e.,
it is inhibited from counting).

The typewriter control instructions follow. These sample
instructions use Typewriter Number 1 on Channel W with four
characters per word mode.

START Switch

RKB

This switch initializes the control section of the computer. It
resets all channels, clears the P Register, Overflow Indicator,
Memory Parity Error Indicator, and sets up a HALT (00) instruction in the C Register. The RUN-IDLE-STEP switch must be in
IDLE and the REGISTER SELECT switch must be at C when
pressing this switch. It clears all interrupts and disables the
interrupt system. The EM3 register is set to 3 and the EM2
register is set to 2.
REGISTER Select Switch
This four-position, thumbwheel switch selects the register to
be shown on the Register Display lights.

46

0, 1, 4 READ KEYBOARD WI,
4 characters/word

002 02601

This instruction alerts Channel Wand connects Typewriter
Number 1 to it. RKB prepares the channel to read input from
the keyboard. It also lights the input indicator on the typewriter.
TYP

0, 1, 4 WRITE TYPEWRITER WI,
4 characters/word

00202641

This instruction alerts Channel Wand connects it to Typewriter
Number 1. TYP prepares the channel to write output to the
typewri ter.

PROGRAMMING EXAMPLES
These examples present a straightforward sample of reading and
writing with the typewriter under program control.
EXAMPLE:

Typewriter Output
This routine causes the following message
ASSEMBLY DONE
ENTER NEW PROGRAM
to be typed out under program control. The computer stores the internal codes for fhese characters in m"emory
beginning in location 2000. The routine inserts the carriage return code, 52, and the space code, 12, where needed
and requests End-of-Record interrupt. It is written as a c lased subroutine using interrupts, and uses Channel Wand Typewriter Number 1.
Location
1000

WRITE

Comments

Instruction
PZE

This instruction is an assembler instruction, used here as
a convenient way to reserve the entry location for subroutine use.

CLR

Th is c I ears the A and B Regi sters.

STA

SWiCH

This clears the location called SWiCH. SWICH later
indicates to the main program that output is complete.

TYP

*0, 1, 4

This instruction connects Typewriter Number 1 to Channel
W for output, specifies four characters per word mode, and
alerts Channel W interlace. The instruction is an EOM
with octal configuration, 00242641.

EXU

WRITE

This instruction causes the Input/Output EOM in location
WRITE to be executed.

POT

WRITE + 1

This instruction sends the word count and starting address
in WRITE + 1 to the channel.

BRR

1000

This instruction branches back to the main program.

EOM
0040.3720

16200

This EOM specifi es termi nal outputfunction code 0 1 (IOSD)
and the End -of-Record interrupt. The word in WRITE + 1
speci fi es that ei ght words wi II output from memory begi nni ng
in location 2000. According to terminal function 01, when
the word count equals zero during the transmission, the
output terminates, and when the last character is out, the
device disconnects; at this time, the interrupt occurs.
"

The computer processes the main program while the channel performs the output operation. When finished with the output, an interrupt to interrupt level 33, the End-of-Record location for Channel W, occurs.
33

BRM

OKAY

PZE

OKAY

This instruction, placed in location 33, branches and
marks to location OKAY elsewhere in memory.
This instruction saves the entry location.

MIN

SWICH

This instruction increments location SWICH as an indicator for the main program.

BRU

* OKAY

This instruction branches to the main program and clears
the active interrupt.

47

This is the internal code for the output message:

2000

A

S

S

E

M

B

L

Y

Sp

0

0

N

E

C/R

E

N

21

62

62

25

44

22

43

70

12

24

46

45

25

52

25

45

E

R

Sp

N

E

W

Sp

P

R

0

G

R

A

M

Sp

25

51

12

45

25

66

12

47

51

46

27

51

21

44

12

T
2004

EXAMPLE:

63

Typewriter Input
The operator requests control to input four control characters. The subroutine is assumed to have been entered under
program control. There is no request for terminal interrupts in this example.
Location
INPUT

CHARS

48

Instruct ion

Comments

PZE

This instruction saves the entry location.

RKB

*0, 1, 4

This instruction connects Channel W to Typewriter Number 1, specifies the four characters per word mode, and
alerts the interlace. The input request light is lit. The
octal configuration of the instruction is 0 02 42601. The
asterisk prefixed to the address of read and write controlling EOM instructions indicates the setting of the interlace alert bit (9) ..

EXU

CHARS

This instruction executes the instruction at location
CHARS.

POT

CHARS + 1

This instruction transmits to the channel the word count
and starting address.

CAT

o

This instruction tests for channel not active. If the channel is active when the computer executes CAT, it executes the next instruction in sequence. If the channel is
inactive, the computer skips the next instruction and
executes the following one.

BRU

$-1

This instruction branches to the CAT instruction. The
dollar sign and accompanying signed integer in the address field is an assembler dec laration for the indicated
number of locations prior to or following the current one.
Plus indicates following.

BRU

CHECK

This instruction branches to an assumed routine to determine what characters were typed in.

EOM
00047640

14200

This EOM specifies terminal input function 01 and no interrupt at the end of transmission. The word in CHARS + 1
specifies that one word can be input into location 4000.
Only one word is accepted before the channel disconnects
and goes inactive. The Count Equals Zero causes channel disconnect.

PERIPHERAL EQUIPMENT DESCRIPTION

EXAMPLES:
This instruction

Communication channels facilitate a wide rangeof input/output
operations. Combinations of input/output functions can perform
Scatter-Read and Gather-Write operations. A channel may read
many records into one contiguous area of memory, or skip portions of records and read subsequent portions.

PPT 0, 1, 1

prepares the punch on Channel W to punch without
leader. It sets the channel to operate with one
character per word.

This section describes some of the input/output devices, available in the computer system and explains their use.

This instruction

PAPER TAPE INPUT/OUTPUT

PTL 0, 1, 4

Paper tape used with the computer is one-inch wide, affording
space for eight data holes and a sprocket hole in each frame of
information. There are ten frames per inch of paper tape. Six
hole positions contain information, one contains the odd parity
check, and the eighth is unused.
Frame of Inform~
00

p

:
•

0

00
0

: .\ .... ~ .. ~p.
)

,
0

0

Sprocket H"/(Ies
000 00
00
0

00000

gg
·og· .. Q~. ~~. ·g·o· ·ggo·· .... \
0

0

- - Direction of Travel

g

0

0

00

0

0

00
0

0

(
I

I
1 Block of Information

The organization of information on the tape is in blocks. A
block is a'group of frames set off by a gap of at least one blank
frame (in which only the sprocket hole ispunched) ateitherend.
Blocks may be of variable lengths.
For some operations a tape may consist of only one block, such
as a source language tape prepared off-line. In this case, the
program need not read the entire block at one time, but may
stop the reader between frames, and then start again to read
the remainder or another ,portion of the block.

00200644

prepares the punch and produces about 12 frames
of leader. It sets the channel to operate with four
characters per word.
No channel terminal function produces End-of-Record gap after
punching a block. The EOM instruction that addresses the punch
can only generate gap.
The punch operates at 60 characters per second, asynchronously.
If the channel does not supply characters to the punch fast
enough for operation at 60 cps, the punch waits for each character, losing no data and making no errors.
Programming
There are no status tests for the Paper Tape Reader or Punch,
that is, they are always ready for operation. When a channel
addresses either device, the device starts to send or accept data
within approximately one character time. The reader and punch
operate only in the binary mode and the forward direction; they
ignore any different mode specified, and use the forward-binary
mode. Unit addresses of 04 and 05 are for Paper Tape Readers
1 and 2, respectively, and unit addresses 44 and 45 are for
Paper Tape Punches 1 and 2.
Paper Tape Instructions
The following instructions use Channel W, Paper Tape Number
1, with four characters per word format.
RPT 0, 1, 4

All channel functions may be used in reading paper tape. An
input/output function that terminates because of a zero count
stops the tape between frames. A subsequent paper tape "read"
starts the reader and allows the next frame to be reod. An input/output function that terminates because of gap (End-ofRecord) stops the tape after the first blank frame of the gap.
When the tape starts, the tape reader ignores any leading blank
frames. After reading information from the tape, the reader
recognizes a blank frame as gap and signals the channel with an
End-of-Record indication.

00202644

READ PAPER TAPE

00202604

RPT initiates a paper tape read operation on tape read station
number 1 connected to Channel W in the four characters per
word format.
PH 0, 1, 4

PUNCH PAPER TAPE WITH LEADER

00200644

PTL initiates a paper tape punch operation on tape punch station
number 1 connected to Channel W in the four characters per
word mode. It generates approximately twelve frames of leader
preceding the first punched frame.
PPT 0, 1, 4 PUNCH PAPER TAPE WITH NO LEADER 0 02 02644

Punching
When a channel addresses the paper tape punch, the punch motor
also starts (if not already on). If the punch instruction so indicates, the punch unit punches a segment of leader (gap, or
blank frames). Bit position 13 of a Channel EOM or EOD instruction, which addresses the punch, contains a "0" to punch
leader; bit position 13 contains a "1" to punch without leader.

PPT initiates a paper tape punch operation on tape punch station number 1 connected to Channel W in the four characters
per word format. It generates no leader preceding the first
punched frame.
The desired EOM, POT combination follows each of these instructions to control the input/output of data.

49

I

EXAMPLE:

Punch Paper Tape
This program punches one block of 20 words beginning in location 2000. A twelve-frame leader precedes the block.
The routine is a closed subroutine that uses interrupts.
Location

Instruction

1000

PZE

This instruction saves a place for the entry location.

CLR

This instruction clears the A and B Registers.

PUN20

Comments

STA

WHERE

This instruction clears a switch location used as an indicator to the main program for completion of the punch
operation.

PTL

*0, I, 4

This instruction connects Channel W to Paper Tape Punch
Number I, specifies four characters per word mode, and
alerts the interlace. The instruction specifies leader to
be punched, and if not already on, turns the punch motor
on. The octal configuration of this EOM is 0 02 40644.

EXU

PUN20

This instruction executes the I/O Control EOM that sets
the interrupt and selects output function 00.

POT

PUN20 + I

This instruction transmits to the chonnel the word count
and starting address of the transmission.

BRR

1000

This instruction branches back to the main program.

EOM
01202000

16000

The EOM specifies terminal outputfunction 00 (lORD) and
the End-of-Record interrupt. The word in PUN20 + I specifi es 20 words of output from memory to the punch begi nni ng
at location 2000 (0120 is 0248 shifted right one place; it
is merged with 02000 to moke the "POTted" control word).
According to terminal output function 00, when the word
count equals zero during the transmission, the output terminates. The last word has not been fully transmitted at
this time. When it is and the output is complete, the channel disconnects and the interrupt occurs.

When the Count Equals Zero interrupt occurs:

50

Location

Instruction

33

BRM

END

PZE

Comments
END

This instruction branches and marks to END.
This instruction saves a place for the entry location.

MIN

WHERE

This instruction increments WHERE as a flag.

BRU

*END

This instruction returns to the main program and clears the
interrupt Ieve I.

EXAMPLE:

Read Paper Tape

This program reads a block of 64 characters from paper tape. The routine uses the four characters per word mode,
making the input 16 words. It turns the tape station on and requests a Count Equals Zero interrupt, level 31, for
the operation on Channel W. The routine is a closed subroutine.
location

Instruction

1000

PZE

This instruction saves a place for the entry location.

CLR

This instruction clears the A and B Registers.

REED

31

FNISH

Comments

STA

SWICH

This instruction clears location SWICH used as an inputfinished indicator.

RPT

* 0, I, 4

This instruction connects Paper Tape Reader Number 1 to
Channel W, specifies the four characters per word mode,
and alerts the interlace. The octal configuration of this
EOM instruction is 0 02 42604.

EXU

REED

This instruction executes the EOM at location REED.

POT

REED + 1

This instruction transmits to the channel the word count
and starting address.

BRR

1000

This instruction branches back to the main program for
processing while the input operation is in progress.

EOM
01003720

15200

This EOM specifies terminal input funct;on 01 (IOSD)and
the Count Equa Is Zero i nterrupl. The word in REED + 1
specifies that input into memory begins in location 2000
and that 16 words wi II be read before the operati on terminates. When the word count equals zero, the interrupt
occurs. Then the channel disconnects. When the tape
read operation is complete, the Count Equals Zero interrupt occurs at level 31.

BRM

FNISH

This instruction, in location 31 for this example, branches
and marks to location FNISH.

PZE

This instruction saves the entry location.

MIN

SWICH

This instruction sets an input-finished switch for use by
the main program.

BRU

*FNISH

This instruction branches back to the main program and
clears interrupt level 31 from the active state.

The programmer can make a test to the channel, CET, for parity error during the read operation before the BRU
instruction.

51

CARD INPUT/OUTPUT
The card reader scans the card, column by column, starting with
column one, and transmits either ao or 160 characters to the
channel depending on the mode of operation. When power is
on and cords are in the hopper, the operator mokes the card
ready by pressing the START button. During program operation,
the program must test for the ready condition before initiating
a card read operation. Once an EOM instruction starts the card
read, the desired channel function (EOM, POT) may control
the flow of information into memory. In the Hollerith mode,
any column read that is not punched in one of the 64 combinations listed in Appendix A-I results in a Validity check. The
presence of a Validity check causes an error signal to be sent
to the channel and lights theVALIDITY CHECK light on the
reader.

The computer uses aO-column cards .in two formats. The card
reader reads Hollerith-coded information from cards and transmitsthe corresponding SDS character codes to memory. In this
mode, each column contains the equivalent of one 6-bit internal character. Appendix A-I lists the character codes.
The card reader reads binary-coded information from the card
with two 6-bit characters per column. In binary mode, two
columns form a word. The top six rows (12-3) of column 1, for
example, form the first character and the bottom six (4-9) the
next character. The reader reads from column 1 to ao in this
top-bottom order. A single card holds 160 characters or 40
binary words.

If the stacker shou Id become fu II, or the hopper empty, the
reader is not ready and the NOT READY indicator lights. The
card reader remains in the NOT READY state until the operator
corrects the situation and presses the START button. Upon read-.
ing the last card, the reader sets an End-of-File signal if the
EOF ON switch is on. The central processor con test the Endof-File condition to determine if more cards are in the hopper.

Figure 4-4 shows the relation of Hollerith information on a .card
and in memory. Hollerith output to the punch is identically the
reverse.

Memory

Card A

....

m
0·w~

~

". cc

~"'l"'~

~

~

i- ....
,,~

=~
~~

-

....
....
....
........
....
....

~

~

=~
~~

~~
~~

'"

~~

....
.... '"
~

.... '"
.... '"

~~

";:0=
t.~ (Q

.... '"
........ '"

~cc

=~
~~

~~
~~

-... -... - -'.
... -

...

-- --.- --N

~

.......

...
....... ... ..........
... .......'"

....
'" ....
'"

....

~~ (,Cl

'"

'"
'"
'"

~

"~
"~
"~

=

-......

...
....... ......
.... ...
....
....... ...
~

...

....
....

.-~wQ
-. Q

-~_

... · 0

-;:;.0

•

V?
-i

B

S
62

T
63

A
21

R
51

B+

T
63

-6
60

C
23

R
51

T
63

-6
60

1)

1)

60

60

0
00

73

1
01

-6
60

n

;0

-i
(")
;0

-i

-J::O

-t:_

-;-

_~o

s:'

-;;c::I

-:::l=
-;;=
-;;=
-~Q
-~CI

...,
'"
...,
....

-OQ
-"Q
-.Q
-.Q
-MQ

9

-~Q
-~Q

-tlCI

-~'"
-~=

I/O

~
B + 19

.

<~

~

o~
,,~

~~

=~

~~

;:;:CD

~

c.;'<:C\

co

=~
,,~

~~

~

E~

co

....
....
....
....
....
'"
...
'"
...
....
......
....
....
......
....
....
'"
'" ...
.... '" '"
....
.... ...'" '"en .......

......
...... ...
...... .......
... ....
w

,

N

--------

1)

60

OQ
OQ
~Q

=Q
=Q
=Q
~Q

"Q
~Q

-'::::"Q

~_0iI=
~-

C)

Figure 4-4. Card Reod Into Memory in Hollerith

52

I
I

I
I
I
I
I

I
I

I
0
00

1
01

0
00

Punching

RCD 0, 1,4

The card punch punches cards a row ata time, starting with row
12. The punch coupler, in both the Hollerith and binary modes,
automatically rearronges the information to be punched. The
card punch program must present the entire card image, 80 or
160 characters, to the punch 12 times for each card. This is
necessary because of the way the punch operates. Aseach row
of the card approaches the punch station, the coupler exam ines
every character of the image to determine which column positions in that row should be punched. After the 12th output,
the card punch punches row 9 and completes the card cycle.

RCD alerts the card reader, couses a card to feed from the
hopper, and selects the Hollerith mode (as each column is read
it is translated to an SDS internal code). This mode can read
up to 80 characters (20 words) from a card.

The card punch is Ready to punch if there are cards in the
magazine, the stacker is not full, and the operator has pressed
the START button. The punch remains Ready as 19n9 as the above
conditions are true. A Punch Card instruction given when the
punch is Ready causes a card to feed past the punch station.
The program must then address the punch and give the same
instructions 12 times to transm it the card image to the coupler.

RCB 0, 1,4

READ CARD DECIMAL (Hollerith)

READ CARD BINARY

00202606

00203606

RCB a lerts the card reader, causes a card to feed from the
hopper and selects the binary mode (as each column is read it
is transmitted as two 6-bit binary characters). This mode can
read up to 160 characters (40 words) from a card.
SRC 0, 1

SKIP REMAINDER OF CARD

002 12006

This instruction causes the reader to stop transmission of
characters to the channel. The remaining characters are not
checked for val id ity, but a read check, feed check, or endof-record condition still cause an End-of-Record interrupt and
disconnect the card reader from the channel.

Programm ing Instructions
Card Punch Instructions
The Card Reader and Punch instructions follow. They use unit
number 1 on Channel W with the four characters per word trans, mission mode.
Card Read Instructions
CRT 0,1

CARD READER READY TEST

o 40

12006

This test determines if the selected card reader is Ready to read.
If so, the computer skips the next instruction in sequence and
executes the following instruction. If the reader is Not Ready,
the computer executes the next instruction in sequence.

PBT 0, 1

FIRST COLUMN TEST

CARD READER END-OF-FILE TEST

12046

CARD PU NCH READY TEST

04014046

040 14006

This test determines if the first column is about to be read by
the card reader. Since the time elapsing between the execution of a card reader EOM and the reading of the first column
is approximately 85 milliseconds (48,450 computer cycles),
th is test allows the computer to perform other operations
during this time. If FCT is executed less than 1.2 millisecond~
(approximately 685 computer cycles) before the first column is
due to be read, the computer skips the next instruction in
sequence ane' executes the following instruction. If FCT is
executed 1.2 milliseconds (or more) before the first column
is due to be read, the computer executes the next instruction
in sequence (does not skip).
CFT 0, 1

o 40

This instruction is used to test the status of the punch buffer.
If the punch buffer is clear (empty) and ready for loading
when PBT is executed, the computer skips the next instruction
in sequence ond executes the following instruction. If the
punch buffer is not clear when PBT is executed, the computer
executes the next instruction in sequence (does not skip). The
punch buffer is always clear if the punch is ready to feed and
punch.
CPT 0, 1

FCT 0,1

PUNCH BUFFER TEST

040 11006

This test determines if the End-of-File condition from the card
reader has been detected. If not, the computer skips the next
instruction in sequence and executes the following instruction.
If the EOF cond ition has been detected, the computer executes the next instruction in sequence.
The reader remains in the End-of-File condition until the operator adds cards to the hopper or turns off the EOF ON switch.

This test determines if the selected card punch is Ready to
punch. If so, the computer skips the next instruction in
sequence and executes the following instruction. If the punch
is Not Ready, the computer executes the next instruction in
sequence.
Before the punch is Ready, the operator must place blank cards
in the magazine and press the START button.
PCD 0, 1,4

PUNCH CARD DECIMAL (Hollerith)

00202646

PCD alerts the punch, causes a card to feed past the punch
station, and selects the Hollerith mode. A transmission of 80
characters (20 words) must follow this instruction. The instruction PCD followed by the transmission instructions for 80 characters per card is repeated 12 times.
PCB 0, 1,4

PUNCH CARD BINARY

00203646

PCB alerts the punch, causes a card to feed past the punch station, arid selects the binary mode. A transmission of 160 characters (40 words) must follow this instruction. The instruction
PCB followed by the transmission instructions for 160 characters
per cord is repeated 12 times.

53

EXAMPLE:

Card Read
This program reads one card in Hollerith mode. It is a closed subroutine that uses interrupts; assume the interrupt
system is enabled.
Location

Instruction

1000

PZE

CRT

Comments
This is ah assembler instruction. It conveniently reserves
a location for the subroutine entry.

0, 1

This instruction is the card reader Ready test for Card
Reader Number 1 on Chanhel W.

If Not Ready, the computer executes the next instruction.
If Ready, the computer skips the next one and executes
the following instruction. The octal configuration is
040 12006.

READ

BRU

$-1

This instruction branches back to the test on Not Ready.
The programmer can put an exit to a Not-Ready corrective routine here.

RCD

* 0, 1, 4

This instruction connects Card Reader 1 to Channel W,
alerts the interlace, starts a card moving toward the read
station, and specifies Hollerith mode. The octal configuration for this instruction is 0 02 42606.

EXU

READ

This instruction executes the I/O Control EOM atlocation READ.

POT

READ + 1

This instruction transmits to the channel the word count
and starting address.

BRR

1000

This instruction branches back to the main program.

EOM
01203720

15200

This EOM specifies terminal input function 01 (IOSD)and
the Count Equals Zero interrupt. The word in READ + 1
specifies that a record will be read into memory beginning at location 2000and specifies a 20-word limit.

The computer processes the main program whi Ie the channel performs the card read operation. When finished with the
input, transmission of an interrupt wi II occur to the interrupt level 31, the Count Equals Zero location for Channel W.

54

31

BRM

TEST

PZE

TEST

This instruction, placed in location 31 for this example,
branches and marks to location TEST.
This instruction saves a location for the routine entry.

CET

o

This instruction tests for an error on Channel W. Its octal
configuration is 040 11000.

BRM

ERR

The computer executes this instruction if there is an error
on Channel W. Assume that ERR is the entry to a corrective subroutine.

BRU

* TEST

This instruction returns control to the main program and
clears interrupt level 31. The computer executes this
instruction if no error is detected.

EXAMPLE:

Card Punch
This pragram punches one card in Hollerith mode. It is a closed subroutine that uses interrupts. The Index Register
counts the 12 times the program presents the card image to the punch.
Location
1000

MCRDS

GETRW

PNCH

Instruction

Address

PZE

Saves the location for the subroutine entry.

CLR

Clears the A and B Registers.

STA

SWICH

Clears a switch for later use.

LDA
STA

1000
ENTR2

This pair of LDA and STA place the main program mark address in
location ENTR2.

MIN

ENTR2

MIN adds one to the stored contents.

LDX

ROWS

Initializes the Index Register with 00077765 (octal), which is -11
decimal.

CPT

0, 1

Tests the card punch for a Ready condition. The card punch is Number
1 on Channel W.

BRU

$-1

The computer executes this instruction if the punch is Not Ready. It
branches back to the test, CPT 0, 1. The programmer can place an
exit to a time loop here with the facility to tell the operator that the
card punch wi II not become Ready.

PCD

* 0, I, 4

The computer executes this instruction if the punch is Ready. It alerts
Channel W with interlace, connects Card Punch Number 1 to Channel
W, starts a card moving toward the punch station, and specifies four
characters per word and Hollerith mode.

EXU

PNCH

Executes the EOM located in PNCH.

POT

PNCH + 1

Transmits to the channel the word count and starting address.

BRU

ENTR2

Branches back to the main program.

EOM

16000

This EOM specifies terminal output function 00 (lORD) and the End-ofRecord interrupt. The word in PNCH +1 specifies that 20 words will be
output from memory beginning in locotion 2000.

01203720

ROWS

Comments

Note that the program must send the card image to the channel twelve
times to punch a card.

00077765

The computer processes the main program whi Ie the channel performs the output. When Finished with the output, transmission of an interrupt will occur to the interrupt level 33, the End-oF-Record location for Channel W.
33

BRM

ENTR2

PZE

ENTR2
Saves a location for routine entry.

BRX

GETRW

Increments the index by one. If the base has not been incremented
through zero, the next instruction executed is at location GETRW.
When the base increments to zero, the computer executes the next instruction in sequence. The Index counts row times on the card.

MIN

SWICH

Sets a switch to indicate to the main program that the punch operation is
complete.

BRU

* ENTR2

Returns control to the main program and clears the interrupt.

55

MAGNETIC TAPE INPUT/OUTPUT
Format
Magnetic tape units used in SDS computer systems are IBM-compatible. The tape is one-half inch wide, Mylar base material,
1.5 mils thick. Tape reels (10 1/2-inch, plastic) contain up to
2400 feet of tape. A reflective marker, placed on the back of
the tape approximately ten feet from the beginning of it, indicates the load point. The leading ten feet leave space for
threading tape through the guides on the unit. The load point
marker is on the Mylar side of the tape along the edge nearest
the operator when the tape is mounted. A similar marker is
along the other edge of the tape to mark the end-of-reel. About 14 feet of tape are reserved between the End-of-Reel
marker and the end of the tape. This space includes at least
ten feet of leader and enough tape to hold a record of 9,600
characters in 200 bpi density after sensing of the End-of-Reel
marker.
Character recording on tape is in seven parallel tracks. A
change in the magnetic flux in a track records a I-bit for a
given character position. No change in magnetic flux indicates a O-bit. Six of the tracks are for information; the seventh
track is a parity check. The system allows both even and odd
parity, as needed. Binary recording uses odd parity. In this
mode, the tape unit records the six-bit characters from the
channel without change. Binary-coded decimal (BCD) recording uses even parity. In this mode, the tape control unit transforms characters from the channel to conform to standard IBM,
BCD interchange code (see Appendix A-I).
Arrangement of information on tape is in blocks that may contain one or more records. Only the capacity of available core
storage in the computer I imits block length. An inter-record
gap (section of blank tape) about 3/4-inch long separates blocks
of records on tape. In writing, the tape unit automatically produces gap at the end of a record or block. Reading begins wi th
the first character sensed after the gap and continues until encountering the next gap.
An inter-record gap, followed by a special, single-character
record, marks the end of a file of information. The character
is a Tape Mark (0001111). Writing a one-word record in BCD
with one-character-per-word format can record such a mark.
A reel of tape may contain one or more files. On reading an
End-of-File record, the tape control unit stops the tape and
sets its End-of-File indicator, which the program may test.
The tape control unit considers any record that contains only
Tape Mark (0001111) characters an End-of-Fi Ie. The tape unit
reads such' characters into memory like any other characters.
As the tape unit writes information it makes an odd-even count
of the number of I-bits in each track. At the end of each
record it writes a bit for each track such that the total number
of I-bits in each track is even. This parity check sum is always even whether the character parity is even or odd. The
character containing these check bits is the longitudinal parity character; the tape unit writes it slightly past the end of
recorded information in the block.
The longitudinal check character always reflects an even parity check for each channel. In the BCD mode, the check character itself always has an even number of I-bits. In the binary
mode, however, the check character may have either an even
'or an odd number of I-bits. This means that a reverse scan
over a binary record may result in turning on the error indicator

56

in the channel even though the record is correct. As a general
rule, the program ignores the error indicator after a reverse
operation.
It is possible to write tape in a 1-, 2-, or 3-character-perword mode provided that the rate of characters is sufficient. On
reading, however, the tape unit uses the character count to
ascertain when it has read two characters and can look for gap.
If a l-character-per-word "read" is in operation, a single
noise character will stop the tape. In reverse scan a l-character-per-word operation causes the tape to stop after detecting
the longitudinal check character at the end of the record. This
means that the tape stops in the recorded information.

All scan operations must be in 3- or 4-character-per-word mode
or the tape does not stop when it reaches gap.
As a general rule, the user should program tape units for three
or four characters per word, if possible. The write-tope-mark
operation is an exception to this rule.
Use of the TAPE READY TEST (TRT) between tape operations
of opposite direction ensures that the tape unit stops and reverses. It is an advisable programming practice to terminate tape
writing by several inches of erasure whenever subsequent resumption of recording is anticipated. This eliminates the effects
of a possible extraneous character that might arise through subsequent tape repositioning.
Reading
Once a tape starts with a Read Binary or Read BCD EOM or EOD,
it continues until the tape unit detects an End-of-Record gap.
If the computer does not instruct the tape unit to continue, it
stops in the middle of that gap. When the tape stops, the tape
unit disconnects from the channel. If the tape encounters an
End-of-File, the tape control unit sets its EOF indicator. The
central processor can test this indicator, which remains set unti I the tape unit control receives a new EOM/EOD on that
channel. The tape always stops after the Tape Mark.
At the end of the file the program reads the EOF character
(0001111) into memory along with its check character. In a
four-character-per-word "read", this appears in the first word
of the input area as a 17170000 word.
When the tape unit is writing on tape, it may transmit flux
disturbing surges ahead of the current writing positions; these
surges affect previously written records further down the tape.
This means that a record in the middle of a file cannot be updated or rewritten if the records that follow it are to be read.
Any errors detected either by the channel in the character
parity check or by the control unit with longitudinal parity
check sets the error indicator in the channel. When detecting
such an error in reading, the routine should backspace the
tape over the erroneous record and attempt to reread the record.
The tape unit backspaces over records using the Scan feature.
A Scan reverse EOM or EOD starts the tape in reverse. The
program then waits for the channel to become ready or waits
for the End-of-Transmission (if enabled). When the buffer
becomes ready or the End-of-Transmission interrupt occurs, the

tape stops in front of the backwardly traversed record. If the
program hs enabled the interrupts, the End-of-Word (11) interrupt occurs prior to the End-of-Transmission interrupt; executing a WIM to a dummy location and clearing the interrupt
with a BRU indirect ignore the interrupt.
A Scan operation is simi lar to a Read operation except that the
channel shifts the characters read through its Word Assembly
Register, but does not consi der a word camplete unti I it encounters a tape gap. When the tape reaches the gap, the
channel uses the last four characters in the word assembly as
the only word read from the record. When scanning in reverse,
the word consists of the last four characters scanned, whi ch
are the first four logi cal characters of the record. This operation assembles these characters in reverse. For example, if
the first four characters of the record are 1234 and the tape is
scanning the record in reverse, these appear as 4321 in the
word stored for that record.
The same operation occurs in the forward scan with the last
four characters of the record forming the word stored. The
Scan is useful for reverse searching on the first word of the
records in the file being searched. In this case, the routine
starts the tape in a reverse scan and loads the channel interlace with a terminal function 10 with a word count of 1 and
arms the Count Equals Zero interrupt. When the tape reaches
the beginning of the record, the channel stores the first word
and interrupts the program which checks the key word against
a search key. If they agree, then the program need only wait
for the channel to become inactive (ready) and the routine
reads the record forward. If the record is not the desired one,
the program gives another "scan reverse" without waiting for
the channel to become inactive, and reloads the channel interlace to scan the next record.
If the tape encounters the End-of-Reel marker whi Ie reading,
the tape logic sets the End-of-Reel indicator in the tape unit;
the program can test this at any time. An End-of-File normally indicates the end of recorded information on tape. It
is possible, however, to USto the End-of-Reel indicator to mark
the last record on the reel.

Once a tape unit is ready and the file-protect ring is on th!!!
tape reel, that is, the file-protect test is false, a Write operation can begin. The write tape EOM starts tape motion; the
tape remains in motion until it receives the termination signal
from the buffer. The tape control unit then writes the remaining characters of the r!!!cord and writes the longitudinal check
character. When the read-after-writ!!! head reads this check
character, the tape signals the channel it has reached gap. If
the unit receives no further writ!!! instruction within one mi.llisecond, the tape stops and disconnects.
If the user wishes to backspace or rewind and then to return at
some later time to record additional information at the end of
the previous series of records, the routine shou Id write an Endof-Fi Ie character or erase a segment of tape after the series of
written records. This practice provides positive identification
of the end of a record and facilitates return. to a specific location on the tape. If the programmer does not use this method,
the tape may not subsequently stop in the same location at the
end of the series of records as it did when writing the last record.
This would leave a segmentof tape in the gap which has not been
written and may cause erroneous operation when reading the tap!!!.

In addition to writing under program control, the program can
also erase magnetic tape. When using an erase EOM with an
erase unit address, the tape unit operates as though it were in
a Write mode, except that it records no information. The program or interlace supplies the count of the number of words to
be erased.
This type of erase is useful for the correction of !J write error.
When a write error occurs, an ERASE TAPE REVERSE (ERT)
starts the tape in reverse. The same count, used to write
the record originally, controls the erase. This procedure ensures that the tape always returns to the beginning of the erroneous record, even if a bad spot on the tape might appear as a
gap. The routine may now rewrite the record. If the Write still
produces an error, the routine erases the record backward and
then erases it foward, using the same count, and by-passes the
section of tape where the difficulty occurred. The routine may
now rewrite the record on a new section of tape.
The erase procedure can produce the required 3.75 inches of
-blank tape between the load point and the first record. This is
done by erasing 150 words at 200 bpi density, 417 words at
556 bpi density, or 600 words at 800 bpi density.
Use of a one-character-per-word, BCD, Write instruction
writes an End-of-File record. Then the program loads the channel interlace with a count of 1 and loads the address of a word
containing the Tape Mark character (17) in the left-most position. EOM or EOD instructions to the tape units specify startwithout-leader since the tape unit automatically generates gap
at the end of all records for leader. A magnetic tape program
should never include a leader instruction because an attempt
to generate leader may cause an erroneous operation.
Programming
The SKS and EOM instructions for normal tape operationsfollow. EOM instructions use four character per word format for
units on Channel W.
TRT O,n

TAPE READY TEST

0401041n

TRT 0 tests tape unit number n on Channel W for Not Ready.
If th!!! tape is Not R!!!ady, it skips th!!! next instruction in sequ!!!nce and ex!!!cut!!!S the following instruction. If the tape is
Ready, it !!!x!!!cutes the next instruction in sequence.
A tape is Not Ready if: (1) there is no physical unit set to the
logical unit number being tested, (2) the selected unit is not
in the Automatic mode, or (3) the tape is in motion for any
operation.
FPT O,n

FILE PROTECT TEST

040 1401n

Tests tape unit number n on Channe I W for fi Ie protect. If the
file-protect ring is present, the computer skips the next instruction in sequence and executes the following instruction. If not
inserted, it executes the next instruction in sequence. The skip
does not occur if there is no logical unit n on the channel.

BTT

O,n

BEGINNING OF TAPE TEST

040 1201n

Tests tape unit number n on Channel W for the beginning of the
tape. If not positioned on the load point marker, the computer
skips the next instruction in sequence and executes the following instruction. If positioned on the load point marker, it executes the next instruction in sequence. The skip does not occur
if there is no logical unit n on the channel.

57

ETT 0, n,

END OF TAPE TEST

040nOlri

Tests whether tap~ u'nit f)umber non Chann~1 W is,'not positioned
a(the end of the tape. If the tape unit has not sensed the Endof-Reel marker, the computer skips the next instruction i.n sequence and executes the foi lowing instruCtion. If the End":of.:.
Reel marker has been sensed, it executes the next instruction in
sequence. The End-of-Reel condition is reset when the tape unit
moves the tape backward over the End-of-Reel marker. The skip
does not OCClJr if there is no logical unit n on the channel.
DT2 0, n

DENSITY TEST" 200 BPI

040 1621n

Tests tape unit number n on Channel W for being set at 200 bpi
density. If not, the computer skips the next instruction in sequence and executes the f?lIowing instruction. If so, it exe-'
cutes the next instruCtion in sequence.
DT5 0, n

DENSITY TEST, 556 BPI

040 1661n

Tests tape unit number n on Channel W for being set at 556'bpi
density. If not, the computer skips the next instruction in sequence and executes the following instruction. Ifso, it
executes the rext instructi on in sequence.

WTD 0,n,4

Starts tape unit n on ,Channel W in a BCD Write mode.
EFT 0, n, 4

DENSITY TEST, SOOBPI

Starts tape unit ~ on Channel W in an Erase mode.
ERT 0, n, 4

Starts tape unit n on Channel W in reverse. inan Erase mode.
RTB 0, n, 4

RID 0, n! 4

READ TAPE IN DECIMAL (BCD)

SFB 0, n, 4

SCAN FORWARD IN BINARY

04013610

SRB 0,11,4

REW 0, n

0401261n

Tests whether tape unit n on Channel W has encountered gap
since it received the last EOM/EOD instrpction. If not, the
~omputer wi II skip the next instruction in sequence and execute
the following instruCtion. If so, it executes the next instruction in sequence. TGT wi II execute the next instruction during
the approximately 0.75 millisecond that the tape-gap indicator
is "true"I.
0401021n'

Tape unit n is tested for being a MAGPAK. If the tape unit is
not a MAGPAK, the computer skips the next instruction in sequence and executes the following instruction. If the tape' unit
is a MAGPAK"the computer executes the next inst~uction in
sequE1nce.
WTB 0, n, 4

WRITE TAPE IN BINARY

0

BCD Scan mode.

SCAN REVERSE IN BINARY

0020763n

SCAN REVERSEIN DECIMAL (BCD)

002 0663n

Starts tape unit n on Channel W in reverse in a BCD Scan mode.
REWIND

0021401n

Starts tape unit n on Channel W in a Rewind.
the channel.
RTS 0

CONVERT READ TO SCAN

REWdoes not use

002 14000

The tape unit currently in a read mode on the channel is instructed,to convert from the read mode of operation to the scan
mode of operati on.
SRR 0

SKIP REMAINDER OF

~ECORDt

00213610

The tape unit'currently on the channel is instructed to skip the
remainder .ofthe record being read.

0020365n

Storts tape unit n on Channel W in a Binary Write mode.

58

Binory Scan mode.

Starts tape unit n on Channel W in reverse in a Binary Scan
mode.

The End-of-Fi Ie indi cator remains set unti I the program ca lis for
another tape operation.

MAGPAK TEST

0

0020363n

SCAN FORWARDIN DECIMAL(BCD) 002 0263n

Starts tape unit n on Channel W forward in

SRD 0, n, 4

TAPE GAP TEST

0020261n

Starts tape unit n on Channel W in a BCD Read mode.

Test~ whether a tape unde~ control of the tape cOJltrol unit on
Channel W encountered an End-of-Fi Ie during the last Read or
Scan operation. If not, the computer skips the next instruction
in sequence and executes the following instruction. If so, it
executes the next instruction in sequence.

TGT 0, n

0020361n

READ TAPE IN BINARY

Starts tape unit n on Channel Win a Binary Read mode.'

SFD 0, n, 4

TAPE EN D-O F-FJ LE TEST

0020767n

ERASE TAPE IN REVERSE

040 1721n

Tests tape unit number n .on Channel W for being set at 800 bpi
density. If not, the computer skips the next instruction in sequenceand executes the following instruction. If so, it
executes the next instruction in sequence.
TFTO

0020367n

ERASE TAPE FORWARD

Starts tape unit.n on Channel W forward in
DT8 0, n

0020265n

WRITE TAPE IN DECIMAL (BCD)

t Note: This instruction applies only to 41.7-kc and 96-kc
'magnetic tape systems.

MAGNETIC TAPE EXAMPLE PROGRAMS
The following examples show samples of complete input/output programs for magnetic tape.
EXAMPLE:

Magnetic Tape Read
This program reads one record from Magnetic Tape Number 1 on Channel W.

It uses the End-of-Record interrupt.

The

tape is not at its beginning or end.
Location
1000

Instruction

Comments

PZE
TRT

Saves a location for the subroutine entry.
0,1

Tests Ready Magnetic Tape 1 on Channel W.

If Magnetic

Tape 1 is ready to perform an input/output operation, the
computer executes the next instruction in sequence.

If not,

it skips the next instruction and executes the following one.
The octal configuration is 040 10411.
BRU

$+2

Skips one instruction.

BRU

$-2

Branches back to TRT 0, 1.

The programmer can place here

an exit to a routine that determines reasons for the NonReady condition.

RTD

*0,1,4

Addresses Channel W, alerts the interlace, connects it to
Magnetic Tape 1, specifi es four characters per word and
BCD modes, and starts tape motion.

REDTP

EXU

REDTP

Executes the EOM located in location REDTP.

POT

REDTP+l

Transmits to the channel the word count and starti ng address.

BRR

1000

Branches back to the main program.

EOM
06203720

16000

This EOM specifies terminal input function 00 (lORD) and
the End-of-Record interrupt. The word in REDTP + 1 spec ifies that one record or 100 words, whichever is smaller,
will be read into memory beginning in location 2000. Any
remaining words in the record after the first 100 will be ignored. (0620 is equal to 1448 shifted right one place; it
is merged with 03720 to generate the "POTted" word.)

The main program continues while the channel performs the input operation. When finished, the End-of-Record interrupt
goes to location 33.

33

BRM

COMPL

PZE

COMPL

This instruction in interrupt location 33 branches and marks
to COMPL to finish the read operation.
Saves a location for the routine entry.

CET

o

Tests for error in Channel W. If it detects an error, the computer executes the next instruction in sequence. If not, it
skips the next one and executes the following instruction.
The octal configuration is 040 22000.

BRM

ERTST

Branches to an assumed routine to re-read the block a number
of times and, if the error continues, to notify the operator.

BRU

* COMPL

Returns control to the main program and clears interrupt level
33.

59

EXAMPLE:

Gather-Write Magnetic Tape
The program writes one record on magnetic tape. The gathering of the data written in that record is from three non-contiguous areas of memory. This program isa closed subroutine that uses the Count Equals Zero interrupti it uses Channel W
and Magnetic Tape Number 1 on Channel W with interlace.
A similar program can perform a scatter-read operation. The difference is the exchange of the read instruction (RTD) with
the write instruction (WTD) and the deletion of the file-protect testing instruction.
Location

Instruction

1000

PZE

Saves a location for the subroutine entry.

CLR

Clears the A and B Registers.

FAST

60

Comments

STA

COUNT

Clears location COUNT for use later as a switch.

TRT

0, 1

Tests whether Magnetic Tape 1 on Channel W is Ready.

BRU

$+2

Branches two locations ahead. The computer executes it if
the magnetic tape unit is Ready.

BRU

$ - 2

Branches back to the Ready test.

FPT

0, 1

Tests whether the file-protect ring is present on the tape reel.
If so, the computer skips the next instruction and executes the
following one. The octal configuration is 040 14011.

BRM

OPER

Branches and marks to an assumed routine to call the operator
qnd instruct him to insert file-protect ring on Magnetic Tape L

LOA
STA
MIN

1000
FAST
FAST

These three instructions place the marked subroutine entry
location plus one into location FAST.

WTD

0, I, 4

Connects Magnetic Tape 1 to Channel W, specifies BCD
transfer mode and four characters per word, and starts the
tape moving. The octal configuration is 0 02 02651.

BRU

FAST + 1

Branches around location FAST.

PZE

Saves a location for entry to the multiple write area of the
subroutine.

LOX

COUNT

Loads the Index Register with the contents of COUNT, which
picks up the proper input/output control instructions.

LDA
LOB
SKM
BRU
BRU

OKAY
MASK
COUNT

These five instructions determine when the write operation
is complete. When it is, location COUNT contains the number 6 and the active interrupt, level 31, is cleared. Locat ion MASK contains 77777777S.

ALC

o

Alerts the interlace in Channel W for subsequent loading.

EXU

A, 2

Executes the EOM located in address A modified by the Index.

POT

A + 1,.2

Transmits to the channel the word count and starting address.

MIN
MIN

COUNT
COUNT

These instructions add two to the contents of COUNT.

BRU

* FAST

Branches back to the main program.

$+2
* FAST

The main program continues while the channel performs the output. When finished, the Zero Word Count interrupt goes
to interrupt location 31.
Location
31

Instruction
BRM

Comments
FAST

Branches and marks at location FAST.

The routine repeats this for the output words in A + 2 and in A + 4. Then the test in location FAST + 4 causes a final
Branch to clear interrupt (BRU) back to the main program.

Location

Comments

Instruction

A

EOM
06203720

15600

This EOM specifies terminal output function 11 (IOSP) and
the Count Equals Zero interrupt. The word in A + 1 specifies that 100 words will be read out from memory beginning
in location 2000.

A+2

EOM
14404740

15600

This EOM specifies terminal output function 11 (IOSP) and
the Count Equals Zero interrupt. The word in A+3 specifies 200 words from memory beginning in location 2500.

A+4

EOM
06205670

15000

The EOM specifies terminal output function 00 (lORD) and
the Count Equals Zero interrupt. The word in A+5 specifies 100 words from memory beginning in location 3000.
Upon completion of the output of this sub-record, the channel disconnects.

OKAY

00000006

This is the stored number 6 used in the completion test above.

NOTE: This sample program is for clarification of magnetic tape programming. It does not include extra programming to
save the contents of the A or the Index Register for the main program.

61

LINE PRINTER
SDS buffered line printers are capable of printing up to 1000
lines per minute at 132 characters per line, with a standard set
of 56 characters. Printing is accomplished by means of a rotating character drum and a bank of 132 print hammers. The
drum passes 56 different characters, in lines of 132 each, past
the hammer bank. Upon command from the computer, the selected print hammers drive the paper against the ribbon and
onto the appropriate character typeface as it passes the print
position. The characters are transmitted sequentially for storage in the printer buffer before printing. A programmable format tape loop provides fixed (or preselected) space control.
Upspacing of 1 to 7 lines, as well as page control, may be accomplished by program instructions.
An optional, off-line facility allows the program or the operator to initiate card-to-printer or magnetic tape-to-printeroperations simultaneous with computation (see Off-Line Printing).
Printer Controls
The printer controls, Figure 4-5, for SDS line printers consist
of eight switches and indicators.

f
(

ON

l

READY

)

POWER

~r::::J

~~

Figure 4-5. Printer Control Indicator Lights and Switches
The POWER/ON switch is an alternate action switch. The computer must be turned on for this switch to be activated. Pressing POWER/ON lights the top half of the indicator, turns on
the motors and hammer driver power supply, and starts a timer
• that allows the motors to reach proper speed. After 20 seconds
the bottom half lights, indicating that the printer is operable.
When the printer is initially turned on, the READY indicator is
off. When pressed, it is turned on if:
1.

paper is loaded in the line printer,

2.

the lower half of the POWER/ON switch is lighted, and

3.

the hammer power supply is on.

62

This indicator autamatically goes off when the above conditions are not realized. The printer is ready for either online or off-line operation when READY is turned on. Ready
is reset to preclude computer intervention whi Ie changing
paper or ribbon, or operating the TOP OF FORM or SINGLE
SPACE switches.
Pressing TOP OF FORM causes the printer to position paper
accordi ng to format tape channe I 1. Th i sind i cator is lighted
only when the format tape is positioned at channell, that
is, top-of-form on a standard tape loop. This switch is operative when there is paper in the printer and the READY indicator is off.
Pressing SINGLE SPACE causes the printer to upspace paper
one single space, independently af the vertical format tape.
This switch is operative when there is paper in the machine and
READY is off.
The FAULT indicator lights when the printer detects a parity
error as information transfer from the buffer to the print hammers, or when it detects a parity error in incoming data from
magnetic tape or cards during an off-line operation. It remains
lighted until the next EOM addresses the printer. The condition
of the light corresponds to the status of a program-testable fault
indicator in the printer.
MANUAL/OFF LINEt is a combination of a switch and two
independent indicators. The program or the operator may
initiate off-line operation, which is indicated by the illumination of OFF LINE (the bottom half of this switch). If the
operator presses this switch to initiate off-line operation,
MANUAL (the top half of the switch) is also lighted and
remains lighted until the operator presses the switch again.
OFF LINE is normally reset when the end-of-file is detected
from the input unit. Pressing READY also resets OFF LINE,
that is, by switching the printer from the "ready" to the "not
ready" state.
The FORMAT/SPACE t switch is used in off-line operation.
, The operator may use either mode, spacing a single space after
each line of print, or using the first character stored on tape or
cards as a ver'tical format character.
The TAPE/CARD t switch selects the desired input device.
Paper Tape Format Loop
A paper tape format loop, placed in the printer, allows upspacing to proceed to prespecified vertical positions on the print
page. The format loop is an eight-channel paper tape. Putting a punch in the specified channel at the desired vertical
spacing selects the channel upspace. Channell is the top-ofform channel, channel 7 is the bottom-of-farm channel, and
channel 0 is the single-upspace channel. In the off-line mode
with SPACE control, channel 0 controls single spacing. When
printing with no format loop inserted in the printer, single upspacing occurs regardless of the channel specified.
tif an off-line coupler is not attached to the printer, the
MANUAL/OFF LINE, FORMAT/SPACE, and TAPE/CARD indicators neither light nor affect printer operation.

Line Printer Instructions
PLPO,1,4

PRINT LINE PRINTER

00202660

This instruction connects the line printer to channel Wand
ifies a character transmission of 4 characters per word.

The following control instructions are coded for Channel W
using unit number 1:
PRINTER OFF-LINE

002 10260

This instruction places the printer off-line and initiates an offline print operation. The selected input device (card reader 1
or magnetic tape unit 7) also goes off-line (See Off-Line
Printing).
PSC 0, 1,n

PRINTER SKIP TO FORMAT
CHANNEL n

Paper is loaded in the machine,

2.

The lower half of the POWER/ON switch is lighted, and

3.

The hammer power supply is on.

SPE.C-

This instruction is followed by the transmission of up to 132
characters. If the character count is less than 132, the characters are printed left-justified on the page. If the character
count is more than 132, the printer produces an undetectable error.

POL 0, 1

1.

0021n460

This instruction causes the printer to eject paper until the paper
tape format loop detects the first punched hole in the channel
specified by the number n (0 to 7). (See PSP for timing.)

If the printer is ready when PRT is executed, the computer skips
the next instruction in sequence and executes the following instruction. If the printer is not ready, the. computer executes
the next instruction in sequence (does not skip). Since the
printer tests ready whi Ie ejecting paper, the program should
allow a definite time interval to pass (see PSP) after a PSC or
PSP instruction before executing a new PSC or PSP. A dummy
PLP instruction may be issued between two space instructions
(PSC or PSP). This instruction will provide the timing required.
A ready test may be used to determine when the second paper
space instruction may be sent.
EPT 0, 1

END OF PAGE TEST
(Skip if not End of Page)

040 14060

This instruction tests the printer for paper position. If the paper
is positioned at the end of page (specified by formot channel 7)
the computer executes the next instruction in sequence (does
not skip). If the paper is. not positioned at the specified end
of page, the computer skips the next instruction in sequence
and executes the following instruction.
Terminating Line Printer Output

PSP O,l,n

PRINTER UPSPACE n LINES

002 1n660

This instruction causes the printer to upspace n (0 to 7) lines.
Consecutive upspace instructions must be separated by a sufficient time delay. Otherwise, the two PSP instructions may be
merged by the printer.

When the single-word mode of transmission is used for printing
on the line printer, each character transmission for a line must
be followed by a TERMINATE OUTPUT (TOP) instruction. TOP
is automatically generated with interlaced outputs.
Error Conditions

Approximate completion times for PSP (from initiation of instruction to paper stop) ore:

1.

Pri nt fault - parity error during transfer of character
information from print buffer to print hammers.

2.

Buffer error - parity of character rate error during transfer of information through buffer.

3.

Input fault - parity error in incoming data from cards or
magnetic tape (during off-line operation only).

Upspace 1 line: 25 mi IIiseconds (14,275 cycles)
Upspace more than 1 line: add 10 mi IIiseconds (5,690
cycles) for each additional line.
Line Printer Tests
The line printer tests to follow are coded for channel W using
unit number 1:

PFT 0,1

PRINTER FAULT TEST
(Skip if no Printer Fault)

04011060

This test determines if the printer has detected a parity error
during a transfer of information from the printer buffer to the
print hammers. If .such an error occurs, a fault detector is set
and the FAULT indicator is lighted. If the fault detector is set
when PFT is executed, the computer executes the next instruction in sequence (does not skip). If the fault detector is not
set, the computer skips the next instruction in sequence and
executes the following instruction.
PRT 0,1

PRINTER READY TEST
(Skip if Printer Ready)

04012060

This instruction tests the printer for a "ready" condition. The
criteria for a printer "ready" condition are:

Off-Line Printing
The optional, off-line facility allows the line printer to produce
printed records from card or magnetic tape sources without computer attention. The character transmission proceeds directly
from the source to the printer and the channel may sti II be used
by the computer for other input/output operations (e.g., card
reading on card reader 2, card punch, paper tape read/punch,
disk read/write, etc.). Once initiated, the printing operation
is controlled by the source and proceeds unti I the source generates an end-of-file signal (see card input and magnetic tape
input for appropriate end-of-file conditions).
The FAULT indicator lights when a parity error is detected during the reading of a tape record; the off-line printer rereads the
record in an attempt to read good data. If this reread record
contains an error, FAULT lights, the off-line operation terminates, and the printer goes back on-line if physi cally connected

63

EXAMPLE: Print Two Lines
This program positions the paper at the top of the page and prints two lines with a single upspace between them. It assumes
that the printer is ready to print o.r is becoming ready after a print operation. This.program, written as a closed subroutine,
uses channel W, Line Printer 1, and the Count Equals Zero and End-of-Record interrupts.
Location

Instruction

1200

PZE

Address

Reserves a location for subrouti ne entry.

CLR

PRINT

Comments

Clears the A and B Registers.

STA

SWICH

Initializes a location, SWICH, which indicates that printing is completed.

PRT

0,1

Tests for printer ready.

BRU

$-1

Returns controJ to the ready test; if the printer is not ready, the computer executes
this instruction.

PSC

0,1,1

Instructs the printer to move paper to the top of the page.
this instruction is 0 02 11460.

PLP

*0, 1,4

Connects Printer 1 to Channel W, and specifies four characters per word transfer mode,
and alerts the interlace. The octal configuration for this instruction is 0 0242660.

EXU

PRINT

Executes the EOM located in location PRINT.

POT

PRINT+l

Transmits the word count and starting address.

BRR

1200

Branches back to the main program while the line is being printed.

EOM
02043720

16200

This EOM specifies output function 01 and the. End-of-Record interrupt. The word in
PRINT + 1 speci fi es that 33 words wi II be output from memory begi nni ng in locati on 2000.

The octal configuration for this instruction is 0 40 12060.

The octal configuration for

The main program continues while the data transfer and printing is being completed. When completed, the End-of-Record interrupt goes to interrupt level 33. Thisindicdtes that aH the data from memory has been obtained, and that the printing of the
line has been completed.
33

BRM

UPSPC

PZE

UPSPC

Branches and marks to location UPSPC elsewhere in memory.
Reserves a bcation for an entry.

PRT

0,1

Tests for printer reac:\y condition.
wi II be ready.

BRU

*-1

Returns to the test.

PSP

0, 1, 1

Causes the printer to upspace one line. The octal configuration is 0 02 11660.

PLP

*0,1,4

'Sets up the printer with interlace.

EXU

PRNT

Executes the EOM in location PRNT.

POT

PRNT +1

Transmits to the channel the word count and s,tarting address.

BRU

*UPSPC

Branches and clears the interrupt to the mai n program to await completion of the data
transfer.

31

BRM

DONE

Branches and marks to location DONE elsewhere in memory.

DONE

PZE

HEAR

PRNT

Since the current line has been'printed, the printer

This pseudo operation reserves a location for an entry.

MIN

SWICH

Sets the printing complete flag.

BRU

*DONE

Branches back to the main program and clears interrupt 31.

EOM
02043761

15000

This EOM specifies terminal output function OO(iORD) and the Count Equals Zero interrupt. The word in PRNT +1 specifies that 33 words will be read out. from memory beginningin location 2033. The channel disconnects at the end of the output.

This is the final exit.

At location HEAR, note that the computer executes the instructions to print and control the printing before the printing has had
time to completely upspace the paper as requested. The i:nstructions cause an immediate transfer of data into the Print Buffer
and printing begins immediately after completion of upspacing.

64

to the computer and the MANUAL indictor is off. When a
validity check occurs during a card read, FAULT lights, the
operation terminates, and the printer goes back on-line if the
MANUAL indicator is off. The next EOM addressing the printer resets FAULT if the printer is on-line. If the MANUAL indicator is on, the error condition may be cleared by pressing
READY off and then on again. If a fault occurs in an off-line
operation initiated by the computer, the usual method for cleari ng the error is:

1.

Press MANUAL on.

2.

Press READY off.

3.

Press READY on.

4.

Press MANUAL off.

Off-line printing can be formatted as desired through the use of
a single upspace or the format control mode (see Table 4-2).
Off-line printing terminates by an end-of-file indicator from
either device. Upon termination of an off-line operation, a
physically connected off-line printer system returns on-line,
provided the MANUAL indicator is off.
Format Control Characters

Code

Character

Function

00
01
02
03
04
05
06
07
40
41
42
43
44
45
46
47

0
1
2
3
4
5
6
7
- (hyphen)
J
K
L
M
N

Skip to format channel
Skip to format channel
Skip to format channel
Skip to format channel
Skip to format channel
Skip to format channel
Skip to format channel
Skip to format channel
Do not space
Upspace 1 line
Upspace 2 lines
Upspace 3 lines
Upspace 4 lines
Upspace 5 lines
Upspace 6 lines
Upspace 7 lines

0
P

The procedure for operator control of off-line printing is:

1.

Switch on the desired input device. (Magnetic tape is
selected by dialing it to logical tape number 7.)

2.

Place paper at top of form, as desired, by means of the
TOP OF FORM switch.

3.

Select desired input device by means of the TAPE/CARD
switch.

4.

Select either the FORMAT or SPACE mode as required.

5.

Press MANUAL/OFF LINEswitch.

6.

Press READY switch on, which initiates actual data transfer.l

Printing Off-Line Under Computer Control

In a manual Iy i niti ated off-I i ne operation, steps 1 and 4 are not
required.

Table 4-2.

Printing Off-Line Under Operator Control

0
1
2
3
4
5
6
7

The procedure for computer control of off-line printing is:

1.

Turn the equipment on.

2.

Prepare the desired input device for operation.

3.

Select desired input device by means of the TAPE/CARD
switch.

4.

Select either the FORMAT or SPACE mode as required.

5.

Press the READY switch on.

6.

Under program control, test the tape or card unit and the
line printer for "ready" condition.

7.

Then, to start transfer of data, give the POL instruction to
print off-line.

.

Off-Line Print Termination
Off-line printing terminates when an end-of-file indicator from
the magnetic tape unit or card reader occurs. When printing
from magnetic tape, the print operation terminates when the
first character read from a record is the end-of-file code, octal 17.
When printing from cards, the print operation terminates when
the end-of-file signal comes from the reader. This occurs when
the card hopper becomes empty and the EOF ON switch on the
reader is on (END OF FILE indicator lights). If the hopper becomes empty when EOF ON is not lighted, the printer waits
for more cards to be placed in the hopper and the reader to become ready. When the reader is again ready, printing resumes.

65

I

SDS CHARACTER CODES

Characters
Printer

o

SDS
Internal
Code

Card
Code

Magnetic Tape
BCD Code
on Tape

12

40

11

40

01

41

11-1

41

SDS
Internal
Code

Card
Code

Magnetic Tape
BCD Code
on Tape

00

o

01

Characters
Typewriter

Printer

2

2

02

2

02

K

K

42

11-2

42

3

3

03

3

03

L

L

43

11-3

43

M

M

44

11-4

44

4

4

04

4

04

5

5

05

5

05

N

N

45

11-5

45

6

6

06

6

06

o

o

46

11-6

46

7

7

07

7

07

P

P

47

11-7

47

Q

50

11-8

50

R

51

11-9

51

8

8

10

8

10

Q

9

9

11

9

11

R

Blank

12

8-2

12@

# or =

13

8-3

13

@: or'

14

8-4

14

Space

>

& or +

Car. Ret.

!CD !0

$

0

52

11-0

53

11-8-3

53

52

54

11-8-4

54

11-8-5

55

15

8-5

15

55

>

16

8-6

16

56

11-8-6

56

J

17

8-7

17

57

11-8-7

57

+

20

12

60

{,

20

21

12-1

61

/

A

Blank

60

Blank

/

61

0-1

21

5

62

0-2

22

B

22

12-2

62

C

23

12-3

63

T

T

63

0-3

23

D

24

12-4

64

U

U

64

0-4

24

25

12-5

65

V

V

65

0-5

25

W

66

0-6

26

26

12-6

66

W

G

G

27

12-7

67

X

X

67

0-7

27

H

H

30

12-8

70

Y

Y

70

0-8

30

I

I

31

12-9

71

Z

Z

71

0-9

31

*CD

*0

72

0-8-2

32

73

0-8-.3

33

74

0-8-4

34

75

0-8-5

35

76

0-8-6

36

0-8-7

37

Backspace?C0

?0

II or )

32

12-0

0

72

33

12-8-3

73

34

12-8-4

74

35

12-8-5

75

<

36

'" Stop

37

0

NOTES:

CD

o

®

8)

o

The characters? ! and

12-8-6

76

12-8-7

77

* are for input only.

Tab

% or (

\
.. Delete

770

The functions Backspace, Carriage Return, or Tab always occur on output.

On the off-line paper tape preparation unit, 37 serves as a stop code and 77 as a code delete.
The internal code 12 is

writte~

on tape as a 12 in BCD. When read, this code is always converted to 00.

The codes 12-0 and 11-0 are generated by the card punch; however, the card reader will also accept 12-8-2
for 32 and 11-8-2 for 52 to.maintain compatibility with earlier systems.
For.the 64-character printers only.

A-J

TABLE OF POWERS OF TWO
n

1
2
4
8

0
1

1.0

2.
3

0.25
o. 125

16
32
64
128

4
5
6
7

0.062 5
0.03125
0.015625
0.007 812 5

256
512
1 024
2048

8
9
10
11

0.00390625
0.001 953 125
0.000 976 562 5
0.00048828125

4 096
8 192
16 384
32768

12
13
14
15

0.000 244140 625
0.0001220703125
0.000 061 035 156 25
0.000 030 517 578 125

O. 5

65
131
262
524

536
072
144
288

16
17
18
19

0.000
0.000
0.00.0
0.000

1
2
4
8

048
097
194
388

576
152
304
608

20
21
22
23

0.00000095367431640625
0.000 000476 837 158 203 125
0.000 000 238418 579101 5625
0.000 000 119 209 289 550 781 25

16
33
67
134

777
554
108
217

216
432
864
728

24
25
26
27

0.000 000 059 604 644775390 625
0.000 000 029 802322387 695 312 5
0.000000014901161 19384765625
0.000 000 007 450 580596 923 828 125

268435
536 870
1.073 741
2147483

456
912
824
648

28
29
30
31

0.000
0.000
0.000
0.000

000 003
000 001
000000
000 000

725 290 298 461 914062 5
862645149 230 957031 25
931 322574615478 515625
465 661 287307 739 257 812 5

296
592
184
368

32
33
34
35

0.000
O. qoo
0.000
0.000

000 000
000 000
000000
000 000

232830643 653
116 415321 826
058 207660 913
029 103830456

68 719 476 736
137438 953 472
274 877 906 944
549 755 ~13 888

36
37
38
39

0.000 000 000 014 551 915 228 366 851 806640 625
0.0000000000072759576141834259033203125
0.000 000 000 003 637978 807 091 712 951 660 156 25
0.000 000 000 001 818989403 545856 475 830 078 125

776
552
104
208

40
41
42
43

0.000 000 000 000 909494 701 772 928 237 915
0.000000000000454747350886464118957
0.000 000000000 227373 675443 232059478
0.000 000 000 000 113 686 837 721 616 029 739

592186 044416
184372 088 832
368 744 177 664
737488355328

44
45
46
47

0.000 000 000 000
0.000 000 000 000
0.000 000 000000
0.000000000 000

281 474 976 710 656

48

0.000 000 000 000 003 552713 678 800 500 929355621 337890 625

4 2'H
8 589
17 179
34359

1 099 511
2 199 023
4398046
8 796 093
17
35
70
140

A-2

2"

967
934
869
738

627
255
511
022

015
007
003
001

258 7890625
629 394 531 25
814697 265625
907 348 632812 5

056
028
014
007

869628 906
934814453
467407 226
733 703 613

843 418 860808014
421 709 430 404 007
210 854 715 202003
105427357.601 001

25
125
562 5
281 25

039
519
759
379

062 5
531 25
765.625
882812 5

869 689 941 4.06 25
434 844.970 703 125
717422485351 5625'
858 711 242675781 25

OCTAL -DECIMAL INTEGER CONVERSION TABLE

0000

0000

to
0777
IOctal)

0511

to

(Decimo/)

Octal Decimal

10000- 4096
20000- 8192
30000- 12288
40000 • 16384
50000 • 20480
60000- 24576
70000 • 28672

l~O

to
1777
(Octo!)

I

0512

to
1023
IOecimol)

0

1

2

3

4

5

6

7

0000
0010
0020
0030
0040
0050
0060
0070

0000
0008
0016
0024
0032
0040
10048
0056

0001
0009
0017
0025
0033
0041
0049
0057

0002
0010
0018
0026
0034
00'42
0050
0058

OOO;!
0011
0019
0027
0035
0043
0051
0059

0004
0012
0020
0028
0036
0044
0052
0060

0005
0013
0021
0029
0037
0045
0053
0061

0006
0014
0022
0030
0038
0046
0054
0062

0007
0015
0023
0031
0039
0047
0055
0063

0400
0410
0420
0430
0440
0450
0460
0470

0100
0110
0120
0130
0140
0150
0160
0170

0064
0072
0080
0088
0096
0104
0112
Oi20

0065
0073
0081
0089
0097
0105
0113
0121

0066
0074
0082
0090
0098
0106
0114
0122

0067
0075
0083
0091
0099
0107
0115
0123

0068
0076
0084
0092
0100
0108
0116
0124

0069
0077
0085
0093
0101
0109
0117
0125

0070
0078
0086
0094
0102
0110
0118
0126

0071
0079
0087
0095

0200
0210
0220
0230
0240
0250
0260
0270

0128
0136
0144
0152
0160
0168
0176
0184

0129
0137
0145
0153
0161
0169
0177
0185

0130
0138
0146
0154
0162
0170
0178
0186

0131
0139
0147
0155
0163
0171
0179
0187

0132
0140
0148
0156
0164
0172
0180
0188

0133
0141
0149
0157
0165
0173
0181
0189

0134
0142
0150
0158
0166
0174
0182
0190

0300
0310
0326
0330
0340
0350
0360
0370

0192
0200
0208
0216
0224
0232
0240
0248

0193
0201
0209
0217
0225
0233
0241
0249

0194
0202
0210
0218
0226
0234
0242
0250

0195
0203
0211
0219
0227
0235
0243
0251

0196
0204
0212
0220
0228
0236
0244
0252

0197
0205
0213
0221
0229
0237
0245
0253

0

1

2

3

4

5

0

1

2

3

4

5

6

7

0256
0264
0272
0280
0288
0296
0304
0312

0257
0265
0273
0281
0289
0297
0305
0313

0258
0266
0274
0282
0290
0298
0306
0314

0259
0267
0275
0283
0291
0299
0307
0315

0260
0268
0276
0284
0292
0300
0308
0316

0261
0269
0277
0285
0293
0301
0309
0317

0262
0270
0278
0286
0294
0302
0310
0318

0263
0271
0279
0287
0295
0303
0311
0319

0500 0320 0321
0510 0328 0329
05~0 0336 0337
0530 0344 0345
0540 0352 0353
0550 0360 0361
0560 0368 0369
0570 0376 0377

0322
0330
0338
0346
0354
0362
0370
0378

0323
0331
0339
0347
0355
0363
0371
0379

0324
0332
0340
0348
0356
0364
0372
0380

0325
0333
0341
0349
0357
0365
0373
0381

0326
0334
0342
0350
0358
0366
0374
0382

0327
0335
0343
0351
0359
0367
0375
0383

0167
0175
0183
0191

0600
0610
0620
0630
0640
0650
0660
0670

0384
0392
0400
0408
0416
0424
0432
0440

0385
0393
0401
0409
0417
0425
0433
0441

0386
0394
0402
0410
0418
0426
0434
0442

0387
0395
0403
0411
0419
0427
0435
0443

0388
0396
0404
0412
0420
0428
0436
0444

0389
0397
0405
0413
0421
0429
0437
0445

0390
0398
0406
0414
0422
0430
0438
0446

0391
0399
0407
0415
0423
0431
0439
0447

0198
0206
0214
0222
0230
0238
0246
0254

0199
0207
0215
0223
0231
0239
0247
0255

0700
0710
0720
0730
0740
0750
0760
0770

0448
0456
0464
0472
0480
0488
0496
0504

0449
0457
0465
0473
()oI81
0489
0497
0505

0450
0458
0466
0474
0482
0490
0498
0506

0451
0459
0467
0475
0483
0491
0499
0507

0452
0460
0468
0476
0484
0492
0500
0508

0453
0461
0469
0477
0485
0493
0501
0509

0454
0462
0470
0478
0486
0494
0502
0510

0455
0463
0471
0479
0487
0495
0503
0511

6

7

0

1

2

3

4

5

6

7

0518
0526
0534

1400
1410
1420
1430
1440
1450
1460
1470

0768
0776
0784
0792
0800
0808
0816
0824

0769
0777
0785
0793
0801
0809
0817
0825

077Q
0778
0786
0794
0802
0810
0818
0826

0771
0779
0787
0795
0803
0811
0819
0827

0772
0780
0788
0796
0804
0812
0820
0828

0773
0781
0789
0797
0805
0813
0821
0829

0774
0782
0790
0798
0806
0814
0822
0830

0775
0783
0791
0799
0807
0815
0823
0831 '
0839

01~

0111
0119
0127
0135
0143
0151
01~9

1000
1010
1020
1030
1040
1050
1060
1070

0512
0520
0528
0536
0544
0552
0560
0568

0513
0521
0529
0537
0545
0553
0561
0569

0514
0522
0530
0538
0546
0554
0562
0570

0515
0523
0531
0539
0547
0555
0563
0571

0516
0524
0532
0540
0548
0556
0564
0572

0517
0525
0533
0541
0549
0557
0565
0573

0550
0558
0566
0574

0519
0527
0535
0543
0551
0559
0567
0575

1100
1110
1120
1130
1140
1150
1160
1170

0576
0584
0592
0600
0608
0616
0624
0632

0577
0585
0593
0601
0609
0617
0625
0633

0578
0586
0594
0602
0610
0618
0626
0634

0579
0587
0595
0603
0611
0619
0627
0635

0580
0588
0596
0604
0612
0620
0628
0636

0581
0589
0597
0605
0613
0621
0629
0637

0582
0590
0598
0606
0614
0622
0630
0638

0583
0591
0599
0607
0615
0623
0631
0639

1500
1510
1520
1530
1540
1550
1560
1570

0832
0840
0848
0856
0864
0872
0880
0888

0833
0841
0849
0857
0865
0873
0881
0889

0834
0842
0850
0858
0866
0874
0882
0890

0835
0843
0851
0859
0867
0875
0883
0891

0836
0844
0852
0860
0868
0876
0884
0892

0837
0845
0853
0861
0869
0877
088S
0893

0838
0846
0854
0862
0870
0878
0886
089(

0855
0863
0871
0879
0887
0895

1200
1210
1220
1230
1240
1250
1260
1270

0640
0648
0656
0664
0672
0680
0688
0696

0641
0649
0657
0665
0673
0681
0689
0697

0642
0650
0658
0666
0674
0682
0690
0698

0643
0651
0659
0667
0675
0683
0691
0699

0644
0652
0660
0668
0676
0684
0692
0700

0645
0653
0661
0669
0677
0685
0693
0701

0646
0654
0662
0670
0678
0686
0694
0702

0647
0655
0663
0671
0679
0687
0695
0703

1600
1610
1620
1630
1640
1650
1660
1670

0896
0904
0912
0920
0928
0936
0944
0952

0897
0905
0913
0921
0929
0937
0945
0953

0898
0906
0914
0922
0930
0938
0946
0954

0899
0907
0915
0923
0931
0939
0947
0955

0900
0908
0916
0924
0932
0940
0948
0956

0901
0909
0917
0925
0933
0941
0949
0957

Og02
0910
09,18
0926
0934
0942
0950
0958

0903
0911
0919
0927
0935
0943
0951
0959

1300
1310
1320
1330
1340
1350
1360
1370

0704
0712
0720
CJ728
0736
0744
0752
0760

0705
0719
0721
0729
073'1
0745
0753
0761

0706
0714
0722
0730
0738
0746
0754
0762

0707
0715
0723
0731
0739
0747
0755
0763

0708
0716
0724
0732
0740
0748
0756
0764

0709
0717
0725
0733
0741
0749
0757
0765

0710
0718
0726
0734
0742
0750
0758
0766

0711
0719
0727
0735
0743
0751
0759
0767

1700
1710
1720
1730
1740
1750
1760
1770

0960
0968
09'76
0984
0992
1000
1008
1016

0961
0969
0977
098S
0993
1001
1009
1017

0962
0970
0978
098-6
0994
1002
1010
1018

0963
0971
0979
0987
0995
1003
1011
1019

0964
0972
0980
0988
0996
1004
1012

0965
0973
0981
0989
0997
1005
1013
1020 1021

0966
0974
0982
0990
0998
1006
1014
1022

0967
0975
0983
0991
0999
1007
1015
1023

0542

08~7

A-3

Octal-Decimal Integer Conversion Table

1

2

3

4

5

6

7

2400
2410
2420
2430
2440
2450
2460
2470

1280
1288
1296
1304
1312
1320
1328
1336

1281
1289
1297
1305
1313
1321
1329
1337

1282
i290
1298
1306
1314
1322
1330
1338

1283
1291
1299
1307
1315
1323
1331
1339

1284
1292
1300
1308
1316
1324
1332
1340

1285
1293
1301
1309
1317
1325
1333
1341

1286
1294
1302
1310
1318
1326
1334
1342

1287
1295
1303
1311
1319
1327
1335
1343

1095
1103
1111
1119
1127
1135
1143
1151

2500
2510
2520
2530
2540
2550
2560
2570

1344
1352
1360
1368
1376
1384
1392
1400

1345
1353
1361
1369
1377
1385
1393
1401

1346
1354
1362
1370
1378
1386
1394
1402

1347
1355
1363
1371
1379
1387
1395
1403

1348
1356
1364
1372
1380
1388
1396
1404

1349
1357
1365
1373
1381
1389
1397
1405

1350
1358
1366
1374
1382
1390
1398
1406

1351
1359
1367
1375
1383
1.391
1399
1407

1158
1166
1174
1182
1190
1198
1206
1214

1159
1167
1175
1183
1191
1199
1207
1215

2600
2610
2620
2630
2640
2650
2660
2670

1408
1416
1424
1432
1440
1448
1456
1464

1409
1417
1425
1433
1441
1449
1457
1465

1410
1418
1426
1434
1442
1450
1458
1466

1411
1419
1427
1435
1443
1451
1459
1467

1412
1420
1428
1436
1444
1452
1460
1468

1413
1421
1429
1437
1445
1453
1461
1469

1414
1422
1430
1438
1446
1454
1462
1470

1415
1423
1431
1439
1447
1455
1463
1471

2700
2710
2720
2730
2740
2750
2760
2770

1472
1480
1488
1496
1504
1512
1520
1528

1473
1481
1489
1497
1505
1513
1521
1529

1474
1482
1490
1498
1506
1514
1522
1530

1475
1483
1491
1499
1507
1515
1523
1531

1476
1484
1492
1500
1508
1516
1524
1532

1477
1485
1493
1501
1509
1517
1525
1533

1478 1479
1486 1487
149~ 1495
1502 1503
1510 1511
1518 1519
1526 1527
1534 1535

0

I

2

3

4

5

6

7

1

2

3

4

5

6

7

2000
2010
2020
2030
2040
2050
2060
2070

1024
1032
1040
1048
1056
1064
1072
1080

1025
1033
1041
1049
1057
1065
1073
1081

1026
1034
1042
1050
1058
1066
1074
1082

1027
1035
1043
1051
1059
1067
1075
1083

1028
1036
1044
1052
1060
1068
1076
1084

1029
1037
1045
1053
1061
1069
1077
1085

1030
1038
1046
1054
1062
1070
1078
1086

1031
1039
1047
1055
1063
1071
1079
1087

2100
2110
2120
2130
2140
2150
2160
2170

1088
1096
1104
1112
1120
1128
1136
1144

1089
1097
1105
1113
1121
1129
1137
1145

1090
1098
1106
1114
1122
1130
1138
1146

1091
1099
1107
1115
1123
1131
1139
1147

1092
1100
1108
1116
1124
1132
1140
1148

1093
1101
1109
1117
1125
1133
1141
1149

1094
1102
1110
1118
1126
1134
1142
1150

2200 1152 1153 1154
2210 1160 1161 1162
2220 1168 1169 1170
2231) 1176 1177 1178
2240 1184 1185 1186
2250 1192 1193 1194
2260 1200 1201 1202
2270 1208 1209 1210

1155
1163
1171
1179
1187
1195
1203
1211

1156
1164
1172
1180
1188
1196
1204
1212

1157
1165
1173
1181
1189
1197
1205
1213

1216
1224
1232
1240
1248
1256
1264
1272

1217
1225
1233
1241
1249
1257
1265
1273

1218
1226
1234
1242
1250
1258
1266
1274

1219
1227
1235
1243
1251
1259
1267
1275

1220
1228
1236
1244
1252
1260
1268
1276

1221
1229
1237
1245
1253
1261
1269
1277

1222
1230
1238
1246
1254
1262
1270
1278

1223
1231
1239
1247
1255
1263
1271
1279

0

1

2

3

4

5

6

7

3000
3010
3020
3030
3040
·3050
3060
3070

1536
1544
1552
1560
1568
1576
1584
1592

1537
1545
1553
1561
1569
1577
1585
1593

1538
1546
1554
1562
1570
1578
1586
1594

1539
1547
1555
1563
1571
1579
1587
1595

1540
1548
1556
1564
1572
1580
1588
1596

1541
1549
1557
1565
1573
1581
1589
1597

1542
1550
1558
1566
1574
1582
1590
1598

1543
1551
1559
1567
1575
1583
1591
1599

3400
3410
3420
3430
3440
3450
3460
3470

1792
1800
1808
1816
1824
1832
1840
1848

1793
1801
1809
1817
1825
1833
1841
1849

1794
1802
1810
1818
1826
1834
1842
1850

1795
1803
1811
1819
1827
1835
1843
1851

1796
1804
1812
1820
1828
J836
1844
1852

1797
1805
1813
1821
J829
1837
1845
1853

1798
1806
1814
1822
1830
1838
1846
1854

1799
1807
1815
1823
1831
1839
1847
1855

3100
3110
3120
3130
3140
3150
3160
3170

1600
1608
1616
1624
1632
1640
1648
1656

1601
1609
1617
1625
1633
1641
1649
1657

1602
1610
1618
1626
1634
1642
1650
1658

1603
1611
1619
1627
1635
1643
1651
1659

1604
1612
1620
1628
163.6
1644
1652
1660

1605
1613
1621
1629
1637
1645
1653
1661

1606
1614
1622
1630
1638
1646
16'>4
1662

1607
1615
1623
1631
1639
1647
1655
1663

3500
3510
3520
3530
3540
3550
3560
3570

1856
1364
1872
1880
1888
1896
1904
1912

1857
1865
1873
1881
1889
1897
1905
1913

1858
1866
1874
1882
1890
1898
1906
1914

1859
1867
1875
1883
1891
1899
1907
1915

1860
1868
1876
1884
1892
1900
1908
1916

1861
1869
18.77
1885
1893
1901
1909
1917

1862
1870
1878
1886
1894
1902
1910
1918

181i3
187.1
1879
1887
1895
1903
1911
1919

3200
3210
3220
3230
3240
3250
3260
3270

1664
1672
1680
1688
1696
1704
1712
1720

1665
1673
1681
1689
1697
1705
1713
1721

1666
1674
1682
1690
1698
1706
1714
1722

1667
1675
1683
1691
1699
1707
1715
1723

1668
1676
1684
1692
1700
1708
1716
1724

1669
1677
1685
1693
1701
1709
1717
1725

1670
1678
1686
1694
·1702
1710
1718
1726

1671
1679
1687
1695
1703
1711
1719
1727

3600
3610
3620
3630
3640
3650
3660
3670

1920
1928
1936
1944
1952
1960
1968
1976

1921
1929
1937
1945
1953
1961
1969
1977

1922
1930
1938
1946
1954
1962
1970
1978

1923
1931
1939
1947
1955
1963
1971
1979

1924
1932
1940
1948
1956
1964
1972
1980

1925
1933
1941
1949
1957
1965
1973
1981

1926
1934
1942
1950
1958
1966
1974
1982

1927
1935
1943
1951
1959
1967
1975
1983

3300
3310
3320
3330
3340·
3350
3360
3370

1728
1736
1744
1752
1760
1768
1776
1784

1729
1737
1745
1753
1761
1769
1777
1785

1730
1738
1746
1754
1762
1770
1778
1786

1731
1739
1747
1755
1763
1771
1779
1787

1732
1740
1748
1756
1764
1772
1780
1788

1733
1741
1749
1757
1765
1773
1781
1789

1734
1742
1750
1758
1766
1774
1782
1790

1735
1743
1751
1759
1767
1775
1783
1791

3700
3710
3720
3730
3740
3750
3760
3770

1984
1992
2000
2008
2016
2024
2032
2040

1985
1993
2001
2009
2017
2025
2033
2041

J986
1994
2002
2010
2018
2026
2034
2042

1987
1995
2003
.2011
2019
2027
2035
2043

1988
1996
2004
2012
2020
2028
2036
2044

1989
1997
2005
2013
2021
2029
2037
2045

1990
1998
2006
2014
2022
2030
2038
2046

1991
1999
2007
2015
2023
2031
2039
2047

2300
2310
2320
2330
2340
2350
2360
2370

A-4

0

0

2000
to
2777

(Octol)

1024
to

1535
(De~imol)

Octal Decimal

10000 -4096
20000 -.8192
30000·,·12288
40000· 16384
5.0000 - 20480
6POOO - 24576
70000 • 28672

3000

1536

to
3777

2047

(Oclol)

(Decimal)

to

Octal-Decimal Integer Conversion Table

4000

2048

to

10

4777

2559

(Oclol)

lDN;mol)

Octal

Decimal

10000· 4096
20000· 8192
30000· 12288
40000·16384
50000 • 20480
60000·24576
70000·28672

1

2

3

4

5

6

7

2305
2313
2321
2329
2337
2345
2353
2361

2306
2314
2322
2330
2338
2346
2354
2362

2307
2315
2323
2331
2339
2347
2355
2363

2308
2316
2324
2332
2340
2348
2356
2364

2309
2317
2325
2333
2341
2349
2357
2365

2310
2318
2326
2334
2342
2350
2358
2366

2311
2319
2327
2335
23043
2351
2359
2367

2119
2127
2135
2143
2151
2159
2167
2175

4500 2368 2369 2370
4510 2376 2377 2378
4520 2384 2385 2386
4~30 2392 2393 2394
4540 2400 2401 2402
4550 2408 2409 2410
4560 2416 2417 2418
4570 2424 2425 2426

2371
2379
2387
2395
2403
2411
2419
2427

2372
2380
2388
2396
2404
2412
2420
2428

2373
2381
2389
2397
2405
2413
2421
2429

2374
2382
2390
2398
2406
2414
2422
2430

2375
2383
2391
2399
2407
2415
2423
2431

2182
2190
2198
2206
2214
2222
2230
2238

2183
2191
2199
2207
2215
2223
2231
2239

4600
4610
4620
4630
4640
4650
4660
4670

2432
2440
2448
2456
2464
2472
2480
2488

2433
2441
2449
2457
2465
2473
2481
2489

2434
2442
2450
2458
2466
2474
2482
2490

2435
2443
2451
2459
2467
2475
2483
2491

2436
2444
2452
2460
2468
2476
2484
2492

2437
2445
2453
2461
2469
2477
2485
2493

2438
2446
2454
2462
2470
2478
2486
2494

2439
2447
2455

2246
2254
2262
2270
2278
2286
2294
2302

2247
2255
2263
2271
2279
2287
2295
2303j

4700 2496
4710 2504
4720 2512
473012520
474012528
4750 2536
4760,2544
i 4770! 2552

2497
2505
2513
2521
2529
2537
2545
2553

2498
2506
2514
2522
2530
2538
2546
2554

2499
2507
2515
2523
2531
2539
2547
2555

2500
2508
2516
2524
2532
2540
2548
2556

2501
2509
2517
2525
2533
2541
2549
2557

2502
2510
2518
2526
2534
2542
2550
2558

2503
2511
2519
2527
2535
2543
2551
2559

0

1

2

3

4

5

6

7

0

0

1

2

3

4

5

6

7

4000
4010
4020
4030
4040
4050
4060
4070

2048
2056
2064
2072
2080
2088
2Q96
2104

2049
2057
2065
2073
2081
2089
2097
2105

2050
2058
2066
2074
2082
2090
2098
2106

2051
2059
2067
2075
2083
2091
2099
2107

2052
2060
2068
2076
2084
2092
2100
2108

2053
2061
2069
2077
2085
2093
2101
2109

2054
2002
2070
2078
2086
2094
2102
2110

2055
2063
2071
2079
2087
2095
2103
2111

4400 2304
4410 2312
4420 2320
4430 2328
4440 2336
445012344
4460 2352
4470 2360

4100
4110
4120
4130
4140
4150
4160
4170

2112
2120
2128
2136
2144
2152
2160
2168

2113
2121
2129
2137
2145
2153
2161
2169

2114
2122
2130
2138
2146
2154
2162
2170

2115
2123
2131
2139
2147
2155
2163
2171

2116
2124
2132
2140
2148
2156
2164
2172

2117
2125
2133
2141
2149
2157
2165
2173

2118
2126
2134
2142
2150
2158
2166
2174

4200
4210
4220
4230
4240
4250
4260
4270

2176
2184
2192
2200
2208
2216
2224
2232

2177
2185
2193
2201
2209
2217
2225
2233

2178
2186
2194
2202
2210
2218
2226
2234

2179
2187
2195
2203
2211
2219
2227
2235

2180
2188
2196
2204
2212
2220
2228
2236

2181
2189
219':
2205
2213
2221
2229
2237

4300
4310
4320
4330
4340
4350
4360
4370

2240
2248
2256
2264
2272
2280
2288
2296

2241
2249
2257
2265
2273
2281
2289
2297

2242
2250
2258
2266
2274
2282
2290
2298

2243
2251
2259
2267
2275
2283
2291
2299

2244
2252
2260
2268
2276
2284
2292
2300

2245
2253
2261
2269
2277
2285,
2293
2301

,
I

0
.5000
10

I

2560
1o

.5777

3071

(0,101)

We6mol)

1

2

3

4

5

6

7

24~3

2471
2479
2487
2495

5000
5010
5020
5030
5040
5050
5060
5070

2560
2568
2576
2584
2592
2600
2608
2616

2561
2569
2577
2585
2593
2601
2609
2617

2562
2570
2578
2586
2594
2602
2610
2618

2563
2571
'2579
2587
2595
2603
2611
2619

2564
2572
2580
2588
2596
2604
2612
2620

2565
2573
2581
258\1
2597
2605
2613
2621

2566
2574
:<:5'82
2590
2598
2606
2614
2622

25671
2575
2583
2591 1
2599
2607
2615
2623

5400
5410
5420
54'30
5440
5450
5460
5470

2816
2824
2832
2840
2848
2856
2864
2872

2817
2825
2833
2841
2849
2857
2865
2873

2818
2826
2834
2842
2850
2858
2866
2874

2819
2827
2835
2843
2851
2859
2867
2875

2820
2828
2836
2844
2852
2860
2868
2876

28?1
2829
2837
2845
2853
2861
2869
2877

2822
2830
2838
2846
2854
2862
2870
2878

2823
2831
2839
2847
2855
2863
2e71
287\1

5100
5110
5120
5130
5140
5150
5160
5170

2624
2632
2640
2648
2656
2664
2672
2680

2625
2633
2641
2649
2657
2665
2673
2681

2626
2634
2642
2650
2658
2666
2674
2682

2627
2635
2643
2651
2659
2667
2675
2683

2628
2636
2644
2652
2660
2668
2676
2684

2629
2637
2645
2653
2661
2669
2677
2685

2630
2638
2646
2654
2662
2670
2678
2686

2631
2639
2647
2655
2663
2671
2679
2687

5500
5510
5520
5530
5540
5550
5560
5570

2880
2888
2896
2904
2912
2920
2928
2936

2881
2889
2897
2905
2913
2921
2929
2937

2882
2890
2898
2906
2914
2922
2930
2938

2883
2891
2899
2907
2915
2923
2931
2939

2884
2892
2900
2908
2916
2924
2932
2940

2885
2893
2901
2909
2917
2925
2933
2941

2886
2894
2902
2910
2918
2926
2934
2942

2887
2895
2903
2911
2919
2927
2935
2943

5200 2588
5210 2696
5220 12704
5230 1 2712
5240 , 2720
5250 !2728
5260 12736
5270 2744

2689
2697
2705
2713
2721
2729
2737
2745

2690
2698
2706
2714

2691
2699
2707
2715
2722 '2723
2730 2731
2738 2739
2746 2747

2692
2700
2708
2716
2724
2732
2740
2748

2693
2701
2709
2717
2733
2741
2749

2694
2702
2710
2718
2726
2734
2742
2750

2695
2703
2711
2719
2727
2735
2743
2751

5600
'5610
5620
5630
5640
5650
5660
5670

2944
2952
2960
2968
2976
2984
2992
3000

2945
2953
2961
2969
2977
2985
2993
3001

2945
2954
2962
2970
2978
2986
2994
3002

2947 2948 2949 2950
2955 2956 2957 2958
2963 2964 2965 2966
2971 2972 2973 2974
2979 2980 2981 2982
2987 2938 2989 2990
2995 2996 2997 2998
3003 3004 3005 3006

2951
2959
2967
2975
2983
2991
2999
3007

5300
5310
5320
5330
5340
5350
5360
5370

2753
2761
2769
2777
2785
2793
2801
2809

2754
2762
2770
2778
2786
2794
2802
2810

275-5
2763
2771
2779
2787
2795
2803
2811

2756
2764
2772
2780
2788
2796
2804
2812

2757
2765
2773
2781
2789
2797
2805
2813

2758
2766
2774
2782
2790
2798
2806
2814

2759
2767
2775
2783
2791
2799
2807
2815

:;700
5710
5720
5730
5740
5750
5760
5770

3008
3016
3024
3032
3040
3048
3056
3064

3009
3017
3025
3033
3041
3049
3057
3065

3010
3018
3026
3034
3042
3050
3058
3066

3011
3019
3027
3035
3043
3051
3059
3067

3014
3022
3030
3038
3046
3054
3062
3070

3015
3023
3031
3039
3047
3055
3063
3071

2752
2760
2768
2776
2784
2792
2800
2808

2725

3012
3020
3028
3036
3044
3052
3060
3068

3013
3021
3029
3037
3045
3053
3061
3069

A-5

Octal-Decimal Integer Conversion Table
0

I

2

3

4

5

6

1

2

3

4

5

6

7

3080
3088
3096
3104
3112
3120
3128

3081
3089
3097
3105
31!3
3121
3129

3082
3090
3098
3106
3114
3122
3130

3083
3091
3099
3107
3115
3123
3131

3084
3092
3100
3108
3116
3124
3132

3085
3093
3101
3109
3117
3125
3133

3086
3094
3102
3110
3118
3126
3134

3087,
3095
3103
3111
3119
3127
3135

6400
6410
6420
6430
6440
6450
6460
6470

3328
3336
3344
3352
3360
3368
3376
3384

3329
3337
3345
3353
3361
3369
3377
3385

3330
3338
3346
3354
3362
3370
3378
3386

3331
3339
3347
3355
3363
3371
3379
3387

3332
3340
3348
3356
3364
3372
3380
3388

3333
3341
3349
3357
3365
3373
3381
3389

3334
3342
3350
3358
3366
3374
3382
3390

3335
3343
3351
3359
3367
3375
3383
3391

6100 3136
6110 i 3144
612013152
6130 i 3160
6140 3168
6150 3176
6160 3184
6170 3192

3137
3145
3153
3161
3169
3177
3185
3193

3138
3146
3154
3162
3170
3178
3186
3194

3139
3147
3155
3163
3171
3179
3187
3195

3140
3148
3156
3164
3172
3180
3188
3196

3141
3149
3157
3165
3173
3181
3189
3197

3142
3150
3158
3166
3174
3182
3190
3198

3143
3151
3159
3167
3175
3183
3191
3199

6500
6510
6520
6530
6540
6550
6560
6570

3392
3400
3408
3416
3424
3432
3440
3448

3393
3401
3409
3417
3425
3433
3441
3449

3394
3402
3410
3418
3426
3434
3442
3450

3395
3403
3411
3419
3427
3435
3443
3451

3396
3404
3412
3420
3428
3436
3444
3452

3397
3405
3413
3421
3429
3437
3445
3453

3398
3406
3414
3422
3430
3438
3446
3454

3399
3407
3415
3423
3431
3439
3447
3455

16200 3200 3201 3202 3203 3204 3205 3206 3207

3208
3216
13224
3232
3240
3248
3256

3209
3217
3225
3233
3241
3249
3257

3210
3218
3226
3234
3242
3250
3258

3211
3219
3227
3235
3243
3251
3259

3212
3220
3228
3236
3244
3252
3260

3213
3221
3229
3237
3245
3253
3261

3214
3222
3230
3238
3246
3254
3262

3215
3223
3231
3239
3247
3255
3263

6600
6610
6620
6630
6640
6650
6660
6670

3456
3464
3472
3480
3488
3496
3504
3512

3457
3465
3473
3481
3489
3497
3505
3513

3458
3466
3474
3482
3490
3498
3506
3514

3459
3467
3475
3483
3491
3499
3507
3515

3460 3461 3462
3468 3459 3470
34'16 3477 3478
3484 3485 3486
3492 3493 3494
3500 3501 3502
3508 3509 3510
3516 3517 3518

3463
3471
3479
3487
3495
3503
3511
3519

5300 3264
6310 3272
6320 3280
6330 3288
6340 3296
6350 3304
636013312
6370 3320

3265
3273
3281
3289
3297
3305
3313
3321

3266
3274
3282
3290
3298
3306
3314
3322

3267
3275
3283
3291
3299
3307
3315
3323

3268
3276
3284
3292
3300
3308
3316
3324

3269
3277
3285
3293
3301
3309
3317
3325

3270
3278
3286
3294
3302
3310
3318
3326

3271
3279
3287
3295
3303
3311
33191

6700
6710
6720
6730
6740
6750
6760
6770

3520
3528
3536
3544
3552
3560
3568
3576

3521
3529
3537
3545
3553
3561
3569
3577

3522
3530
3538
3546
3554
3562
3570
3578

3523
3531
3539
3547
3555
3563
3571
3579

3524
3532
3540
3548
3556
3564
3572
3580

3525
3533
3541
3549
3557
3565
3573
3581

3526
3534
3542
3550
3558
3566
3574
3582

3527
3535
3543
3551
3559
3567
3575
3583,

0

1

2

3

4

5

6

7

2

3

4

5

6

7000
7010
7020
7030
7040
7050
7060
7070

3584
3592
3600
3608
3616
3624
3632
3640

3585
3593
3601
3609
3617
3625
3633
3641

3586
3594
3602
3610
3618
3626
3634
3642

3587 3588 3589
3595 3596 3597
3603 3604 3605
3611 3612 3613
3619 3620 3621
3627 3628 3629
3635 3636 3637
3643 3£44 3645

3590
3598
3606
3614
3622
3630
3638
3646

3591
3599
3607
3615
3623
3631
3639
3647

7400
7410
7420
7430
7440
7450
7460
7470

3840
3848
3856
3864
3872
3880
3888
3896

3841
3.849
3857
3865
3873
3881
3889
3897

3842
3850
3858
3866
38'14
3882
3890
3898

3843
3851
3859
3867
3875
3883
3891
3839

3844
3852
3860
386B
3876
3884
3892
3900

3845
3853
3861
3869
3877
3885
3893
3901

3846
3854
3862
3S70
3878
3886
3894
3902

3847
3855
3863 1
3871
3879
3887
3895
3903

7100
7110
7120
7130
7140
7150
7160
7170

3648
3656
3664
3672
3680
3688
3696
3704

3649
3657
3665
3673
3681
3689
3697
3705

3650
3658
3666
3674
3682
3690
3698
3706

3651
3659
3667
3675
3683
3691
3699
3707

3652
3660
3668
3676
3684
3692
3700
3708

3653
3661
3669
3677
3685
3693
3701
3709

3654
3662
3670
3678
3686
3694
3702
3710

3655
3663
3671
3679
3687
3695
3703
3711

7500
7510
7520
7530
7540
7550
7560
7570

3904
3912
3920
3928
3936
3944
3952
3960

3905
3913
3921
3929
3937
3945
3953
3961

3906
3914
3922
3930
3938
3946
3954
3962

3907
3915
3923
3931
3939
3947
3955
3963

3908
3916
3924
3932
3940
3948
3956
3964

3909
3917
3925
3933
3941
3949
3957
3965

3910
3918
3926
3934
3942
3950
3958
3966

3911
3919
3.927
3935
3943
3951
3959
3967

7200 3712
7210 3720
7220 3728
7230 3736
7240 ~7';·~
720 3752
17260 1:1750
7270 3'168

3713
3721
3([29
3737
3745
3753
3761
3769

3714
3722
3730
3738
3746
3754
3762
3770

3715
3723
3731
3139
3741
3755
3763
3771

3716
3724
3732
3740
3748
3756
3764
3772

3717
3725
3733
3741
3749
3757
3765
3773

3718
3726
3734
3'742
3750
3758
3766
3774

3719
3727
3735
3743
3751
3759
3767
3775

7600
7610
7620
7630
7640
7650
7660
7670

3968
3976
3984
3992
4000
4008
4016
4024

3969
3977
3985
3993
4001
4009
4017
4025

3970
3978
3986
3994
4002
4010
4018
4026

3971
3979
3987
3995
4003
4011
4019
4027

3972
3980
3988
3996
4004
4612
4020
4028

3973
3981
3989
3997
4005
4013
4021
4029

3974
3982
3990
3998
4006
4014
1022
4030

3975
3983
3991
3999
4007
4015
4023
4031

3777
3785
3793
3801
3809
3817
3825
3833

3778
3786
3794
3802
3810
3818
3826
3834

3779
3787
3795
3803
3811
3819
3827
3835

3780
3788
3796
3804
3812
3820
3828
3836

3781
3789
3797
3805
3813
3821
3829
3837

3782
3790
3798
3806
3814
3822
3830
3838

3783
3791
3799
3807
3815
3823
3831
3839

7700
7710
7720
7730
7740
7750
7760
7770

4032
4040
4048
4056
4064
4072
4080
4088

4033 4034 4035 4036
4041 4042 4043 4044
4049 4050 4051 4052
40~7 4058 4059 4060
4065 4066 4067 4068
4073 4074 4075 4076
4081 4082 4083 4084
4089 4090 4091 4092

4037
4045
4053
4061
4069
4077
4085
4093

4038
4046
4054
4062
4070
4078
4086
4094

4039
4047
4055
4063
4071
4079
4087
4095

6000 3072 3073 3074 3075 3076 3077 3078 3079

6010
6020
6030
6040
6050
6060
6070

6210
6220
6230
6240
6250
6260
6270

7300
7310
7320
7330
7340
7350
7360
7370

A-6

0

7

3776
3784
3792
3800
3808
3816
3824
3832

~

~

I

0

6000
to

6777
(Octol)

!

3072
to

3583

I (Decimol)

Octol Decimol
10000· 4096
20000· 8192
30000· 12288
40000 • 16384
50000 • 20480
60001)·24576
70000· 28672

7

7000

3584

to

to

7777

4095

(Octal)

(Decimal)

OCTAL· DECIMAL FRACTION CONVERSION TABLE
OCTAL

DEC.

OCTAL

DJ::C.

OCTAL

DEC.

OCTAL

m:c.

.000
.001
.002
.003
.004
.005
.006
.007
.010
.011
.012
.013
.014
.015
.016
.017
.020
.021
.022
.023
.024
.025
.026
.027
.030
.031
.032
.033
.034
.035
.036
.037
.040
.041
.042
.043
.044
.045
.046
.047
.050
.051
.052
.053
.054
.055
.056
.057
.060
.061
.062
.063
.064
.065
.066
.067
.070
.071
.072
.073
.074
,075
.076
.077

.000000
.001953
• d"03906
.005859
.007812
.009765
.011718
.013671
.015625
.017578
.019531
.021484
.023437
.025390
.027343
.029296
.031250
.033203
.035156
.037109
.039062
.041015
.042968
.044921
.046875
.048828
.050781
.052734
.054687
.056640
.058593
.060546
.062500
.064453
.066406
.068359
.010312
.072265
.074218
.076171
.078125
; 080078
.082031
.083984
.085937
.087890
.089843
.091796
.093750
.095703
.097656
.099609
.101562
.103515
.105468
.107421
.109375
.111328
.113281
.115234
.117187
.119140
• 121093
.123046

.100
.101
.102
.103
.104
.105
.106
.107
.110
.111
.112
.113
.114
.115
.116
.117
.120
.121
.122
.123
.124
.125
.126
.127
.130
.131
.132
.133
.134
.135
.136
.137
.140
.141
.142
.143
.144
.145
.146
.147
.150
.151
.152
.153
.154
.155
.156
.157
.160
.161
.162
.163
.164
.165
.166
.167
.170
.171
.172
.173
.174
.175
.176
.177

.125000
.126953
.128906
.130859
.132812
.134765
.136718
.138671
.140625
.142578
.144531
.146484
.148437
1150390
.152343
.154296
.156250
.158203
.160156
.162109
.164062
.166015
.167968
.169921
.171875
.173828
.175781
.1'17734
.179687
.181640
.183593
.185546
.187500
.189453
.191406
.193359
.195312
.197265
.199218
.201171
.203125
.205078
.207031
.208984
.210937
.212890
.214843
.216796
.218750
.220703
.222656
.224609
.226562
.228515
.230468
.232421
.234375
.236328
.238281
.240234
.242187
.244140
.246093
.248046

.200
.201
.202
.203
.204
.205
.206
.207
.210
.211
.212
.213
.214
.215
.216
.217
.220
.221
.222
.223
.224
.225
.226
.227
.230
.231
.232
.233
.234
.235
.236
.237
.240
.241
.242
.243
.244
.245
.246
.247
.250
.251
.252
.253
.254
.255
.256
.257
.260
.261
.262
.263
.264
.265
.266
.267
.270
.271
.272
.273
.274
.275
.276
.277

.250000
.251!l53
.253!l06
.255859
.257812
.259765
.261718
.263671
.265625
.267578
.269531
.271484
.273437
; 275390
.277343
.279296
.281250
.283203
.285156
.287109
.289062
.291015
.29296'8
.294921
.296875
.298828
.300781
.302734
.304687
.306640
.308593
.310546
.312500
.314453
.316406
.318359
.320312
.322265
.324218
.326171
.328125
.330078
.332031
.333984
.335937
.337890
.339843
.341796
.343750
.345703
.347656
.349609
.351562
.353515
.355468
.357421
.359375
.361328
.363281
.365234
.367187
.369140
.371093
.373046

.300
.301
.302
.303
.304
.305
.306
.307
.310
.311
.312
.313
.314
.315
.316
.317
.320
.321
.322
.323
.324
.:J25
.326
.327
.330
.331
.332
.333
.334
.3:j5
.336
.337
.340
.341
.342
.343
.3.44
.345
.346
.347
.350
.351
.352
.353
.354
.355
.356
.357
.360
.361
.362
.363
.364
.365
.366
.367
.370
.371
.372
.373
.374
.375
.376
.377

.375000
.376953
• 378!l06
.380859
.382812
.384765
.386718
.388671
.390625
.392578
.394531
.396484
.398437
.400390
.402343
.404296
.406250
.408203
.410156
.412109
.414062
.416015
.417968
.419921
.421875
.423828
.426781
.427734
.429687
.431640
.433593
.435546
.437500
.439453
.441406
.443359
.445312
.447265
.449218
.451171
.453125
.455078
.457031
.458984
.460937
.462890
.464843
.466'196
.468750
.470703
.472656
.474609
.416562
.478515
.460468
.482421
.484375
.486328
.4882l!1
.490234
.492187
.494140
.496093
.498046

A-7

Odal-Decimal Fraction Conversion Table

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC •

• 000000
.000001
.000002
.000003
.000004
.000005
.000006
.000007

.000000
.000003
.000007
.000011
.000015
.000019
.000022
.000026
.000030
.000034
.000038
.000041
.000045
.000049
.000053
.000057
.000061
.000064
.000068
.000072
.000076
.000080
.000083
.000087
.000091
.000095
.000099
.000102
.000106
.000110
.000114
.000118
.000122
.000125
.000129
.000133
.000137
.000141
.000144
.000148

.000100
.000101
.000102
.000103
.000104
.000105
.000106
.000107
,000110
.000111
.000112
.000113
.000114
.000115
.000116
.000117
.000120
,000121
.000122
,000123
.000124
.000125
.000126
.000127
.000130
.000131
.000132
.000133
.000134
.000135
.000136
.000137
.000140
,000141
.000142
.000143
.000144
.000145
.000146
.000147

.000244
.000247
.000251
.000255
.000259
.000263
.000267
.000270
.000274
.000278
.000282
.000286
.000289
.000293
.000297
.000301
.000305
.000308
.000312
.000316
.000320
.000324
.000326
.000331
.000335
.000339
.000343
.000347
.000350
.000354
.000356
.000362
.000366
.000370
.000373
.000371
.000381
.000385
.000389
.000392

.000200
.000201
.000202
.000203
.000204
.000205
.000206
.000207
.000210
.000211
.000212
.000213
.000214
.000215
.000216
.000217

.000488
.000492
.000495
.000499
.000503
.000507
.000511
.000514

.000300
.000301
.000302
.000303
.000304
.000305
.000306
.000307

.000518
.000522
.000526
.000530
.000534
.000537
.000541
.000545

.000310
.000311
.000312
.000313
.000314
.000315
.000316
.000317
.000320
.000321
.000322
.000323
.000324
.000325
.000326
.000327
.000330
.000331
.000332
.000333
.000334
.000335
.000336
.000337
.000340
.000341
.000342
.000343
.000344
,000345
,000346
.000347

.000732
.000736
.000740
.000743
.000747
.000751
.000755
.000759
.000762
.000766
.000770
.000774
.000778
.000782
.000785
.000789

.000152
.000156
.000160
.000164
.000167
.000171
.000175
.000179
.000183
.000186
.000190
.000194
.000198
.000202
.000205
.000209
.000213
.000217
.000221
.000225
.000228
.000232
.000236
.000240

.000150
.000151
.000152
.000153
.000154
.000155
.000156
.000157
.000160
.000161
.000162
.000163
.000164
.000165
.000166
.000167
.000170
.000171
.000172
.000173
.000174
.000175
.000176
.000177

.000396
.000400
.000404
.000408
.000411
.000415
.000419
.000423
.000427
.000431
.000434
.000438
.000442
.000446
.000450
.000453
.000457
.000461
.000465
.000469
.000473
.000476
.000480
.000484

.000250
.000251
.000252
.000253
.000254
.000255
.000256
.000257
.000260
.000261
.000262
.000263
.000264
.000265
.000266
.000267
.000270
.000271
.000272
.000273
.000274
.000275
.000276
.000277

.000010
.000011
.000012
.000013
.000014
.000015
.000016
.000017
.000020
.000021
.000022
.000023
.000024
.000025
.000026
.000027
.000030
.000031
.000032
.000033
.000034
.000035
.000036
.000037
.000040
.000041
.000042
.000043
.000044
.000045
.000046
.000047
.000050
.000051
.000052
.000053
.000054
.000055
.000056
.000057
.000060
.000061
.000062
.000063
.000064
.000065
.000066
.000067
.000070
.000071
.000072
.000073
.000074
.000075
.000076
.000077

A-8

.000220
.000221
.000222
.000223
.000224
.000225
.000226
,000227
.000230
.000231
.000232
.000233
.000234
.000235
.000236
.000237
.000240
.000241
.000242
.000243
.000244
.000245
.000246
.000247

.000549
.000553
.000556
.000560
.000564
.000568
.000572
.000576
.000579
.000583
.000587
.000591
.000595
.000598
.000602
.000606
.000610
.000614
.000617
.000621
.000625
.000629
.000633
.000637
.000640
.000644
.000648
.000652
.000656
.000659
.000663
.000667
.000671
.000675
.000679
.000682
.000686
.000690
.000694
.000698
.000701
.000705
.000709
.000713
.000717
.000720
.000724
.000728

.000350
.000351
.000352
.000353
.000354
.000355
.000356
.000357
.000360
.000361
.000362
.000363
.000364
.000365
.000366
.000367
.000370
.000371
.000372
.000373
.000374
.000375
.000376
.000377

.000793
.000797
.000801
.000805
.000808
.000812
.000816
.000820
.000823
.000827
.000831
.000835
.000839
.000843
.000846
.000850
.000854
.000858
.000862
,000865
,000869
,000873
,000877
,000881
,000885
.000888
.000892
.000896
.000900
.000904
.000907
.000911
.000915
.000919
.000923
.000926
.000930
.000934
.000938
.000942
.000946
.000949
.000953
.000957
.000961
.000965
.000968
.000972

Octal-Decimal Fraction Conversion Table

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC •

.000400
.000401
.000402
.000403
.000404
.000405
.000406
.000407
.000410
.000411
.000412
.000413
.000414
.000415
.000416
.000417

.000976
.000980
.000984
.000988
.000991
.000995
.000999
.001003
.001007
.001010
.001014
.001018
.001022
.001026
.001029
.001033

• 000500
.000501
.000502
.000503
.000504
.000505
.000506
.000507
.000510
.000511
.000512
.000513
.000514
.000515
.000516
.000517

.001220
.001224
.001228
.001232
.001235
.001239
.001243
.001247
.001251
.001255
.001258
.001262
.001266
.001270
.001274
.001277

.000600
.000601
.000602
.000603
.000604
.000605
.000606
.000607
.000610
.000611
.000612
.000613
.000614
.000615
.000616
.000617

.001464
.001468
.001472
.001476
.001480
.001483
.001487
.001491
.001495
.001499
.001502
.001506
.001510
.001514
.001518
.001522

.000700
.000701
.000702
•. 000703
.000704
.000705
.000706
.000707
.,000710
.000711
.000712
.000713
.000714
.000715
.000716
.000717

.001708
.001712
.001716
.001720
.001724
.001728
.001731
.001735
.001739
.001743
.001747
.001750
.001754
.001758
.001762
.001766

.000420
.000421
.000422
.000423
.000424
.000425
.000426
.000427
.000430
.000431
.000432
.000433
.000434
.000435
.000436
.000437
.000440
.000441
.000442
.000443
.000444
.000446
.000446
.000447
.000450
.000451
.000452
.000453
.000454
.000455
.000456
.000457
.000460
.000461
.000462
.000463
.000464
.000465
.000466
.000467
.000470
.000471
.000472
.000473
.000474
.000475
.000476
.000477

.001037
.001041
.001045
.001049
.001052
.001056
.001060
.001064
.001068
.001071
.001075
.001079
.001083
.001087
.001091
.001094
.001098
.001102
.001106
.001110
.001113
.001117
.001121
.001125
.001129
.001132
.001136
.001140
.001144
.001148
.001152
.001155
.001159
.001163
.001167
.001171
.001174
.001178
.001182
.001186
.001190
.001194
.001197
.001201
.001205
.001209
.001213
.001216

.000520
.000521
.000522
.000523
.000524
.000525
.000526
.000527
.000530
.000531
.000532
.000533
.000534
.000535
.000536
.000537
.000540
.000541
.000542
.000543
.000544
.000545
.000546
.000547
.000550
.000551
.000552
.000553
.000554
.000555
.000556
.000557
.000560
.000561
.000562
.000563
.000564
.000565
.000566
.000567
.000570
.000571
.000572
.000573
.000574
.000575
.000576
.000577

.001281
.001285
.001289
.001293
.001296
.001300
.001304
.001306
.001312
.001316
.001319
.001323
.001327
.001331
.001335
.001338
.001342
.001346
.001350
.0'01354
.001358
.001361
.001365
.001369
.001373
.001377
.001380
.001384
.001388
.001392
.001396
.001399
.001403
.001407
.001411
.001415
.001419
.001422
.001426
.001430
.001434
.001438
.001441
.001445
.001449
.001453
.001457
.001461

.000620
.000621
.000622
.000623
.000624
.000625
.000626
.000627
.000630
.000631
.000632
.000633
.000634
.000635
.000636
.000637
.000640
.000641
.000642
.000643
.000644
.000645
.000646
.000647
.000650
.000651
.000652
.000653
.000654
.000655
.000656
.000657
.000660
.000661
.000662
.000663
.000664
.000665
.000666
.000667
.000670
.000671
.000672
.000673
.000674
.000675
.000676
.000677

.001525
.001529
.001533
.001537
.001541
.001544
.001548
.001552
.001556
.001560
.001564
.001567
.001571
.001575
.001579
.001583
.001586
.001590
.001594
.001598
.001602
.001605
.001609
.001613
.001617
.001621
.001625
.001628
.001632
.001636
.001640
.001644
.001647
.001651
.001655
.001659
.001663
.001667
.001670
.001674
.001678
.001682
.001686
.001689
.001693
.001697
.0017.01
.001705

.000720
.000721
.000722
.000723
.000724
.000725
.000726
.000727
.000730
.000731
.000732
.000733
.000734
.000735
.000736
.000737
.000740
.000741
.000742
.000743
.000744
.000745
.000746
.000747
.000750
.000751
.000752
.000753
.000754
.000755
.000756
.000757
.000760
.000761
.000762
.000763
.000764
.000765
.000766
.000767
.000770
.0(1.0771
.000772
.000773
.000774
.000775
.000776
.000777

.001770
.001773
.001777
.001781
.001785
.0017H9
.001792
.001796
.001800
.001804
.001808
.001811
.001815
.001819
.001823
.001827
.001831
.001834
.001838
.001842
.001846
.001850
.001853
.001857
.001861
.001865
.001869
.001873
.001876
.001880
.001884
.001888
.001892
.001895
.001899
.001903
.001907
.001911
.001914
.001918
.001922
.001926
.001930
.001934
.001937
.001941
.001945
.001949

A-9

TWO'S COMPLEMENT ARITHMETIC
SDS computer systems hold negative numbers in memory in
binary two's complement form. The two's complement of a binary number is formed by adding one to the one's complement
(logical inverse) of the number. This convention allows the
sign of a number to be used as an integral part of the number
in all arithmetic operations and obviates the need for keeping
track of a detached sign with computer logic.

2.

In SDS systems, the sign bit is in the first bit position to the left
of the most significant magnitude bit. Thus, ifanSDScomputer
word was only 6 bits long instead of 24, some comrrion decimal
values would be represented in binary format as foll~ws:

The following examples show how two's complement numbers
automatically yield the correct result when used arithmetically
in the computer.

To find the decimal equivalent of a binary two's complement number:
a.

Express as an octal number

b.

Subtract one and form the complement

c.

Find the decimal equivalent.

The negative of the result is the decimal equivalent.

De.cimal
Number
Decimal
Number

Octal
Equivalent

3
2
1
0
-1
-2
-3
31
-31

03
02
01
00
(-}01
(-}02
(-}03
37
(-}37

Complement
Plus 1

Binary
Equivalent

77

000 011
000010
000001
000000
III 111
III 110
III 101
011 111
100001

76
75
41

+ 20

-=..QL
+17

1.

To find the binary, two's complement of a negative decimal number:
a.

Find the octal equivalent of the absolute of the
number

b.

Form the complement and add one

c.

Express as a binary number.

The result is the binary, two's complement equivalent.

A-l0

010 100

+ III 101
1010011 = 21 8= 17 10
Llost carry

Note that the carry out of the most significant (sign bit) position is
lost. Nevertheless, the value remaining is the correct answer.
Decimal
Number

Binary
Equivalent

- 32

100000
011 000
III 000-(-}10 8 =-8 10

+ 24

---:a
This table suggests the following algorithms:

Binary
Equivalent

When performing additions or subtractions in the computer, carries out of the sign bit do not always signify a true overflow
condition or cause the OVERFLOW indicator to be set. In an
addition, it is impossible to produce an overflow if the signs of
the operands are unlike. The computer sets the OVERFLOW indicator in an addition only when the signs of the two operands
are the same, but the sign of the result is opposite. In a subtraction, which in the computer is accomplished by forming the
two's. complement of the subtrahend and then adding to the
minuend, the .test for overflow is simi lar to that for addition.
That is, overflow occurs when both numbers hdve the same sign
after the subtrahend has been complemented but the sign of the
result is opposite.

OPTIONAL EQUIPMENT
DATA MULTIPLEXING SYSTEM
The standard I/O systems provided with the SDS 930 Computer
provide for operation with all standard SDS peripheral equipments and for high-performance special devices. The Data
Multiplexing System provides an alternate I/O system that isof
particular use in dealing with multiple source of data and for
systems which may have very high data rates (see Figure A-I).
The SDS 930 Computer has essentially two major paths along
which I/O data can flow to and from memory. The first path
is the same that is used by the main frame itself. The PIN/
POT operations use the first path. All Time-Multiplexed Communication Channels also use this path. In addition to this
path, which is primarily under the control of the main frame,
there is an optional second path that is completely under the
control of the units attached to it. The second path has priority over the first for access to memory. This path is made
available with the installation of the Multiple Access to Memory Feature.
/lAULTIPLE ACCESS TO MEMORY FEATURE (MAM)
The Multiple Access feature provides the necessary modules on
both main frame and memory to permit memories to be accessed
via the second path. A word can be transferred over the path
in either direction in one cycle. If the computer is equipped
with two or more memories and the main frame is communicating with one memory while some other device is using the second path to another memory, then there is no interference with
computation. If both the main frame and an I/O device using
the second path address the sarTie memory, the second path has
priority; the program loses one cycle while the second path
transmi ts.
The Multiple Access feature is required for the attachment of
Direct Access Communication Channels (DACC), Data Multiplex Channels (DMC), or Memory Interface Connections (MIC).
These devices all incorporate a priority scheme for determining the assignment of the second path. (See Figure A-I.)
Only four DACCs can be attached to one computer system;
Memory Interface Connections, and Data Multiplex Channels,
however, are unlimited in number.
A practically unlimited number of MICs in addition to the four
DACCs and the Data Multiplexing System (DMS) can be attached to a computer system. Each MIC has the necessary pri0rity control to operate with other MICs and DACCs and the
DMS. Both MICs and DACCs can be arranged so as to produce
any required configuration of priorities.
DATA MULTIPLEXING BASIC ELEMENTS
A Data Multiplexing System consists of two basic elements:

1. The Data Multiplex Channel (DMC) for communicating with several data sources/destinations and for synchronizing I/O operations with memory, MICs, DACCs, and other DMCs.

2. One or more Data Subchannels (DSC) for interfacing
between peripheral devices and systems and the DMC.
Data Multiplex Channel (DMC)
The Data Multiplex Channel is the basic unit for the Data
Multiplexing System. It connects to the second path to memory via the Multiple Access to Memory feature. A DMC consists of 24-bit register and control logic. All addresses
and data are transmitted between the DMC and subchannels
via a bus system. The data and address are connected to
memory via the MAM only when a transfer is to be made.
All program control required for a given I/O operation operates directly on the individual subchannel, not the DMC.
The DMC is equipped with an internal interlace feature. This
feature allows a subchannel to specify the address of a word in
memory where the data address and count are to be found.
When operating with internal interlace, the subchannel supplies the address of its interlace word instead of the actual
data address. The DMC reads out the interlace word, increments the address portion, decrements the count, restores the
word and then accepts the data from or transmits the data to
the subchannel. The DMC also supplies a signal to the subchannel if the decremented count is zero.
The format of the internal interlace word or word pair is as
shown:

I

o

WORD COUNT
I
I
8 9

DATA ADDRESS
I
I

23

The 9-bit word count allows for block lengths to 512 words.
With the 930, transmissions using internal interlace require 3
cycles per word.
The DMC also provides for automatic memory incrementing.
The counting capability of the DMC register is such that the
entire 24-bit register or either the upper 12 bits or the
lower 12 bits may be incremented. When such a memory increment operation is to be performed, the subchannel signals
the DMC with a special increment line and supplies the address. The DMC reads out the word, increments it and then
restores. If the word was zero after the incrementing, the
DMC signals the subchannel which may then interrupt the program. The maximum incrementing rate is 1 count every 2 cycles. Parity generation and detection are available.
Data Subchannels (DSC-N)
There are a number of subchannels wh ich can be attached to
the DMC. A full word, 24 bits plus parity, is available for
the 930. Words (24 bits) are assembled in two 12-bit characters. Subchannels can control and generate program interrupts
but do not include the interrupt levels themselves. The signals must be routed to optional interrupt levels if the interrupt
features are to be used.

A-II

......
_~_~_ITMiCI

...

PIN

....._ _~ITMCC

y

Main Frame

POT

.-

I---First Path ------,
Additional
Optional
Memories

...

.....- -.......-t

TMCC

C

......-r---.......-t TMCC

D

(Optional)
Memory

Memory

Multiple Access
to Memory
Feature

Multiple Access
to Memory
Feature

~

--- Second Path --It

,

---r----------.--~----_.--------~,_--------_.--------~r_------__.---

r ---- ----.,

1

1-:

1-

MIC
r-------------JI
MIC

I
I
I

DMC

I-! ~D"""A

It

DAi C 1_

EL:!-CC=--"'I_

I

1... _ _ _ _ _ _ _ _ _ _ _ _ _ ,

Data

I
I

Multiplexing System

I

I

I

It

I
I

----

---

:

I

I

I

:I
I

Priority
Control

It

Optionall- EIN

I

~I

DSC

It

1- - ~I
I

I

DSC

Priority
Control

I
I
I
I

,

1-- -d DSC 1---- :Priority Interrupts
I

I

I

I

Figure A-I. SDS 930 Overall Computer Configuration

A-12

The subchannels use a priority scheme to determine which may
transmit to the DMC at any given time. This is similar to the
scheme used by the MICs, DMCs, and in transmitting to memory. Up to 128 DSCs can be connected to a DMC. A DSC
can use the internal interlace feature of the DMC to control
its transmission or it can be equipped with an external interlace (EIN).
A DSC using internal interlace has two words assigned to it.
These two words are ad jacent even/odd locations and are fixed
for a given subchannel. The program can select either the
even or odd location. If the even location is selected, the
subchannel will automatically switch to the odd location when
the count field of the even word is zero. The program can also
select whether or not the subchannel will switch back to the
even word when the count field of the odd word is zero. The
subchonnel will generate an interrupt signal when the count
field of either word reaches zero. Transmission termination
occurs when the odd word's count equals zero if the subchannel
does not switch back to the even word.
The two-word internal interlace allows a subchannel to handle
continuous data by alternately working from one memory area
or another. By allowing the subchannel toswitch automatically from one interlace word to the other, the program is
relieved of the necessity for making real-time responses to the
zero count condition. Using first the even then the odd interlace word allows maximum word count of 1024 for a pair of
interlace words.
CHARACTER SUBCHANNEL (DSC-I)
The DSC-I contains a 12-bit data register that can assemble
and disassemble two 6-bit characters, and transm it one or two
6-bit characters or one 12-bit character. It checks and generates the parity of characters to enable it to couple with
standard SDS peripherals. The DSC-I has a unit address register. For the 9300, it can be used for mu Itiple typewriters
or other character-oriented devices. However, it only uses
12 bits of the full 24-bit word.
The subchannel can operate with either internal or external
interlace. It has one mode of output and two modes of input.
During output, it transmits until the odd internal interlace
word count is zero and then terminates if interlace cycling is
not requested. The output can also be terminated if the device sends an END signal to the channel. This END signal
may cause the DSC-I to generate an interrupt to the program.
Input, like output, can always be terminated due to an external END signal. The program can also specify if the DSC
is to terminate and disconnect on zero count or disconnect
only on the END signal. In either case, however, all transmission to memory is terminated after the odd interlace count
reaches zero if interlace cycling is not requested.

Its operation in this respect is identical to that of the DSC-1.
The DSC-II also contains control logic to facilitate memory
increment operations in conjunction with the DMC.
EXTERNAL INTERLACE
The external interlace (EIN) can be attached to the DSC to
control the transmission of its data to/from memory. The EIN
consists of a 15-bit address register and a 9-bit count register.
These registers are loaded automatically when the subchannel
is activated, the information coming from the internal interlace memory locations. Once the EIN is set up, it will control the transmissions of the DSC at a maximum rate of 1 word
per memory cycle. After each word is transmitted, the EIN
increments its address register and decrements its count. When
the count equals zero, the EIN signals the DSC, which can
then generate a program interrupt and/or notify the externa I
device. Transmission normally terminates on zero count.
Sequencing of interlace words is identical to the sequence of
operation performed for internal interlace, except that only
two memory cycles are used for interlace word processing. The
first is to access the interlace word initially; the second is to
restore the interlace word when the count reac hes zero.
PROGRAM CONTROL OF DATA SUBCHANNELS
Transmission of data between a DSC and computer memory is
controlled by two 24-bit interlace control words unique to the
DSC and wired into fixed adjacent locations in memory. During a transmission the DMC/DSC uses the two interlace control
words for determination of transmission address and record
length.
The DSCs are num bered from 0 to 0376 in even octal numbers;
this permits a maximum of 128 subchannels. The memory locations of the interlace control word pairs associated with the
DSCs are numbered XOOOO, X0001 for DSC-O, X0002, X0003
for DSC-2 ... X0376, X0377 for DSC-376. DSC-I numbering
need not be contiguous, but DSC-II's are configured one or
two in a modu Ie and are numbered with ad jacent numbers. If
a system contains multiple DSC-II modules (each with 1 or 2
subchannels), the module numbering need not be contiguous;
4,0 and 0224, 0220 and 0314 is a typical possibility for five
DSC-II subchannels. Transmissions to and from the DSC and
memory may be under internal interlace control or, when so
equipped, under external interlace control.
INTERNAL INTERLACE
During an internal interlace transmission, the DMC controls
the interlacing operation in the following order:
1.

Access Interlace Word
The DMC accesses the interlace word assigned to the
requesting subchannel.

FULL-WORD SUBCHANNEL (DSC-II)
2.
The DSC-II is a general purpose subchannel designed to allow
communication with word-oriented input/output units such as
analog-digital and digital-analog converters. It contains no
storage for data. The external device must be capable of
holding the data during the transmission to/from the DMC. (An
A-to-D converter would have such capabi I ity). Like the DSC-l,
the DSC-II can operate with either internal or external interlace.

Process Interlace Word
The DMC increments the 15-bit address portion of the
word and decrements the 9-bit word count.

3.

Test for Zero and Set Ind icator
Next, the DMC tests the word count for zero and if it is
zero, sets an indicator in the pertinent DSC.

A-13

4.

The DMC then places the new word count/address values
back into memory using the assigned address of requesting
subchannel.

Bit positions 16-23 contain the DSC number being alerted;
these numbers are the even numbers from 0 to 0376 for the
DSC and the C field (bits 13, 14) specifies one of three modes
to which the DSC is alerted. When followed by a POT instruction, the modes have the following meaning:

Access/Store as Requested

C

Effect

The DMC accesses or stores the transmitted word as requested using the incremental address (see above).

00

The subchannel decodes the lower 12 bits (12-23)
of the "POTted" word as the lower 12 bits of a
buffer control mode EOM.

Restore

5.

6.

Stop or Continue

For DSC-I, this will select a device with the unit
address field, set the character/word count,
specify binary or BCD format, forward or reverse,
and leader or no leader.

The DSC checks its zero count indicator and
a., if zero and working on the even interlace word, the
DSC continues operation using the odd interlace word,

For DSC-II, the 12 bits activate the subchannel
and select the proper unit (if more than one is
attached to the DSC).

b.

if zero, working on the odd interlace word and the
cycle bit is set, the DSC continues using the even
interlace word,

c.

if zero, working on the odd interlace word and the
cycle bit is reset, the DSC terminates the operation
on a DSC-II or responds as required by the function
control on a DSC-I.

d.

if not zero, the DSC returns operation to the DMC
to continue at 1 (above).

01

The subchannel decodes the lower 12 bits of the
"POTted" word as the lower 12 bits of an input/
output control mode EOM. If bits 18 through 23
are zero, the "POTted" word addresses the selected
DSC.
For DSC-I, these bits perform such functions as
rewind tape, space paper, etc.

Note that the first address used is the "address specified plus
one" and the first word count is the "word count specified
minus one". In particular, an initial word count of zero
causes a 512-word block to be transmitted.

For DSC-II, these bits perform such functions as
required by the selected device attached to the
DSC.
10

EXTERNAL INTERLACE
During transmissions utilizing external interlace control, the
interlacing operation proceeds as described above except that
when the DSC is activated, the DSC with external interlace
(EIN) requests the DMC to access the desired interlace control
word. The interlace control word is sent to the EIN. Thereafter, data transmissions to and from the DSC to memory utilize
the interlace address and word count supplied by the EIN.

The subchannel decodes the lower 12 bits of the
"POTted" word for controll ing the interlace and
interrupts. The control type EOM should precede
the buffer control EOM.
For DSC-I the form is:

0

0

12

Data transmissions using the EIN require only one cycle while
those data transmissions using internal interlace require three
cycles. Should a transmission result in the EIN detecting a
zero word count condition, the DSC-EIN will restore the external interlace word and will proceed according to 6 (above).
Any termination of a DSC operation prior to zero word count
due to any externally derived halt signal also causes a restoring of the EIN interlace control word.

1718

For DSC-lI, the form is:

0
An EOM, POT sequence selects, alerts, and controls the subchannel; an EOM, SKS sequence selects and tests the status
and conditions of the subchannel.

11 0 1

o

I

1 2 3

I

and is referred to as the "select EOM".

A-14

12

Bit
Position

EOM

23

FC is a 2-bit function code similar to the TMCC/
DACC terminal function codes. The remaining
bits function as described below for DSC-U.

DSC PROGRAMMING

The EOM has the form:

E Z
E
FC OW C/
R C
0

0

E Z C E
0 00 W y/
R C
0
1718

23

Function

20

A 1 in the EOR bit arms the End-of-Record interrupt for th is c hanne I.

21

A 1 in the ZWC bit arms the Zero Word Count
interrupt.

23

Bit
Position

When testing the subchannel, the U NIT field is set to 00. The
TEST field contains the same testing format as SKS for testing a
TMCC.

Function
A 1 in the CY bit (cycle) sets the cycle mode such
that the interlace will switch from the odd word
back to the even word at the zeroing of the odd
word count. If ZWC and CY are set, a zero count
interrupt is generated each time the interlace
sw itches (to either word - even or odd). If CY is
set to 0, the interlace will not proceed after the
count of the odd word is zero; and a zero count
interrupt occurs only when the count of the odd
word is zero.

22

A 0 in the E/O bit selects the even interlace word
as the first insterlace word in a transmission; note
that when starting on the even word, the interlace
always switches to the odd word for further control
when the even word count goes to zero. A 1 in
E/O sets the odd interlace word as the first interlace word in a transm iss ion; the interlace ceases
control when the odd word count reaches zero
unless the C bit is set to cycle.

23

TERMINATING DSC INPUT/OUTPUT
Once the cycle bit has been set, the interlace continues to
cycle back and forth between the even/odd interlace words.
An EOM, POT sequence is used to term inate the cycle. The
EOM is:

o

I

23

89

1112

23

141516

The lower 12 bits of the "POTted" word must be:

o

2

o
23

12

The interlace term inates the next time the count reaches zero
in the odd interlace word.
For example, to term inate the cycle on DSC 4, use the following sequence:
EOM 071004
POT 010000

o

23

I

TEST

8 9

1112

MEMORY INTERFACE CONNECTION
Once a computer is equipped with a multiple access to memory
feature, one or more memory interface connections (MIC) can
be attached. The MIC is a general interface between the computer and the outside world that allows special devices to be
connected to the computer. The MIC converts between the
4-volt logic levels used in the computer and the 8 volts used
outside. It preserves the integrity of the memory by generating
the parity of incoming data words. It will also check the parity
of words read from memory to indicate memory failures. If
incoming data is supplied with parity, the MIC will check for
odd parity as it generates the internal memory parity and
respond with a signal that indicates if the transmission was
correct. The device that is connected to the MIC must store
both the data and the address until the transmission to/from
memory is completed.

The computer core memory holds its information with all power
removed, but information in the computer registers is destroyed
by loss of power. Upon failure of main power to the computer,
this system provides that the contents of all registers and other
volatile information are automatically stored in core memory;
also, further writing into core storage is inhibited during the
decay period of the computer de power supply oui-puts. Erroneous memory control is prevented during power-off and power-on
operations. Power-oH/-on interrupt routines permit proper
resumption of a program, automatically, after power is restored.
Th is sol id-state system consists of ac power-sensing and memorysequencing circuitry, two high-priority interrupt channels, and
a "shut-down/start-up" programm ing sequence.
The SKIP IF SIG NAL NOT SET (SKS) instruction is an aid in
programming this option. Its address is 024000. If the OFF
interrupt (37) has just occurred, the computer executes the next
instruction in sequence (does not skip).

SDS computers incorporate an extensive memory parity checking
system. The inclusion of parity generation and checking circuitry assures the integrity of data and instructions transferred
among the memory, the central processing unit, and input/output
channels.

The SKS to test subchannels has the form:
SKS

SKS 071000

MEMORY PARITY INTERRUPTS

010000 00000200

o

EOM 070004

AUTOMATIC POWER FAIL-SAFE SYSTEM

DSC

EOM

For example, to test DSC 4 for errar, use the following sequence:

I

UNIT
161718

I

23

A select EOM with C equal to zero (C = 0) permits the SKSto
be directed to the subchannel or to the device attached to it.
The UNIT field specifies the device to be tested; the TEST
field is defined for the particular device.

In normal operation a switch on the computer console specifies
the action to be performed by the computer when a memory parity error is detected. Two actions are available: the computer
halts with the parity indicator lighted; or the computer ignores
the parity error and proceeds with the program.
In many real-time applications it is desirable to keep the computer running when a parity error is detected. Also, the program must be notified of the error without stopping computation.

A-15

An optional feature provides this capability by means of two
levels of enabled interrupts. One interrupt level is associated with the central processor; the other interrupt level
with the Direct Access Communication Channels and the
Data Multiplexing System. Memory parity errors detected
from these two sources produce a priority interrupt associated with the cause. The processing routine associated with
the interrupt can then take appropriate action, such as reinitiate the failed operation, notify the operator, or enter
a diagnostic routine. Such action allows memory parity errors to be recognized and handled properly without hindering the computer's performance of real-time or on-line
cal cu lati ons.

REAL-TIME CLOCK
The Real-Time Clock (RTC) provides a flexible time-orientation
system for the SDS 930 Computer. It derives time pulses from
the 60-cycle computer power supply. These pulses are then
used to produce a timing mark every 16.67 milliseconds, or
optionally every 8.33 milliseconds. The Real-Time Clock can
also accept timing marks from a customer-supplied input,
thereby allowing time measurement to any required resolution
for special applications. These timing marks are supplied at
standard SDS logic levels to the computer's RTC circuitry.
The timing marks are then used by the computer and its interrupt system to provide either an elapsed-time counter or a
continuously incrementing time counter depending on the needs
of the customer. The RTC operates in either mode depending
on lyon the computer's stored program.
Location

Type

Computer

Description

074

Normal

930

CLOCK SYNC

075

Single Instruction

930

CLOCK PULSE

The Clock Pu Ise and Clock Sync interrupts function together
to prov ide e lapsed-t ime, event cou nter, or t ime-of-day clocks.
The Clock Pu Ise interrupt is a single-instruction interrupt.
(Note: See Single Instruction Interrupts in Section 3.) AnMIN
instruction is usually placed in the Clock Pulse interrupt location. When MIN is used as a single-instruction interrupt

A-16

subroutine, it causes the contents of the effective address to be
incremented by one. Furthermore, if the new (incremented)
contents of the effective address is 0000, a Clock Sync interrupt is generated. The Clock Sync interrupt can be generated
in no other way.
ELAPSED-TIME CLOCK
The elapsed-time clock times the length of a program or subroutine, or initiates or discontinues processing at programdetermined time intervals. An arbitrary memory location is
reserved as a counter. When initialized, this cell contains
the 2's complement of the number of time intervals to be
counted. The Clock Pu Ise interrupt location contains an SKR
instruction.
Each Clock Pulse interrupt results in decrementing the clock
count by one. When the count is finished, an interrupt to the
Clock Sync location occurs. A su pervisory or other appropriate
control program can then be entered to perform the customerdesired operation.
CONTINUOUSLY INCREMENTING CLOCK
The continuously incrementing clock maintains "time-of-day"
for the computer. One memory location serves to count the
timing marks. In this case, the Clock Pulse is used to increment this location. (The Clock Pulse interrupt location contains an MIN instruction.) A simple, straightforward subroutine
can be entered to reconstruct the exact time-of-day from this
twenty-four bit count.
ARM/DISARM
The Clock Pulse interrupt can be armed and disarmed with these
instructions.
EOM Effective Address

Action

20200

Disarm Clock Pulse
Interrupt

20100

Arm Clock Pulse Interrupt

The Clock Sync interrupt is always armed.

PROGRAMMED OPERATOR INSTRUCTIONS
The SDS Programmed Operator enables a programmer to code a
subroutine call with a single instruction, just as if the subroutine were an actual machine instruction. Other computers
usually perform standard subroutine calls by executing a transfer to the starting location of the subroutine and, at the same
time, preserving a return address. This procedure requires an
operation code (indicating a transfer) and an operand address
(indicating the starting address of the subroutine). If the subroutine should require an additional operand, as in a floating
point add subroutine, for example, the calling sequence must
be longer to accommodate the specification of the operand.
The SDS Programmed Operator (abbreviated POP) uses the operation code to indicate the transfer address. When the computer
detects a "one" in bit position 2 of an instruction, bit positions
2 through S are not interpreted as a normal instruction, but instead, are treated as an address to which the computer transfers control. Thus the operand address field is free to designate
an address for use by the subroutine. There are 64 (decimal)
locations [(100)S through (177)S] to which a transfer may occur. These 64 locations constitute a I inkage table; theynormally contain appropriate unconditional transfer instructions
(BRU) to maintain the communication link between the POP
code and the subroutine being called by it.

By judicious useof the programmed operator principle, a one-toone correspondence may be maintained between SDS 930 instructions and SDS 925 instructions. For example, XMA is a 930
machine instruction; its function may be simulated on the SDS
925bya subroutine, and this subroutine maybe called by means of
a programmed operator. Thus, the main program requires the
same number of instructions for either the SDS 925 or 930.
Another advantage of the programmed operator is the ability to
change the arithmetic mode of a program without recoding the
arithmetic portions of the program. For example, if the programmer codes all arithmetic instructions as programmed operators, he could simply change the arithmetic subroutine package
and, hence, the arithmetic mode of the main program.
The following operations take place when thecomputer detects
a programmed operator:
1.

(P) ~ (~0-23

save P Register for return address

2.

1 ~( A

2

8

STA

35

STORE A

(A) -3i>M

3

8

LDB

75

LOAD B

(M)-3i> B

2

8

STB

36

STORE B

(B)~M

3

8

LOX

71

LOAD INDEX

(M)-3i>X

2

8

STX

37

STORE INDEX

(X)~M

3

8

XMA

62

EXCHANGE M AND A

(A)~(M)

3

9

EAX

77

COPY EFFECTIVE ADDRESS INTO
INDEX REGISTER

Effective

2

8

ADD

55

ADD M TO A

(A)+(M)~A

2

9

ADC

57

ADD WITH CARRY

(A)+ (M)+ Carry~A

2

9

ADM

63

ADD A TO M

(A)+ (M)--3i>M

3

9

MIN

61

MEMORY INCREMENT

(M)+1~M

3

9

SUB

54

SUBTRACT M FROM A

(A)-(M)-7A

2

10

SUC

56

SUBTRACT WITH CARRY

(A)-(M)-Carry ~A

2

10

MUL

64

MULTIPLY

(A)x(M}-7A, B

4

10

DIV

65

DIVIDE

(A, B).;.(M)-7A, R----?B

10

11

ETR

14

EXTRACT

(A) and (M)~A

2

11

MRG

16

MERGE

(A) or (M)-7A

2

11

EOR

17

EXCLUSIVE OR

(M)(A) or (M)(A) ~A

2

11

Address~X

ARITHMETIC

LOGICAL

REGISTER CHANGE
CLA

04600001

CLEAR A

0-3i>A

12

CLB

04600002

CLEAR B

O~B

12
12

CLR

04600003

CLEAR AB

0-3i>A, B

CAB

04600004

COPY A INTO B

(A) -3i>B

12

CBA

04600010

COpy B INTO A

(B)~A

12

XAB

04600014

EXCHANGE A AND B

(A)~(B)

12

BAC

04600012

COPY B INTO A, CLEAR B

(B)-7A,O-3i>B

13

ABC

04600005

COpy A INTO B, CLEAR A

(A)~B, 0--3i>A

13

CLX.

24600000

CLEAR INDEX REGISTER

0--3i>X

13

CXA

04600200

COPY INDEX INTO A

(X)--3i>A

13

A-20

Mnemonic

Instruction Code

Name

Function

Timing

Page
Ref.

REGISTER CHANGE (cont. )
CAX

04600400

XXA

COpy A INTO INDEX

(A)-3-X

13

04600600

EXCHANGE INDEX AND A

(X)~(A)

13

CBX

04600020

COPY B INTO INDEX

(B) -7X

13

CXB

04600040

COpy INDEX INTO B

(X)-7B

13

XXB

04600060

EXCHANGE INDEX AND B

(X)~(B)

13

STE

04600122

STORE EXPONENT

(B15-23)~X15-23

13

0~B15_23' X 15 -3-X O_ 14

LOE

04600140

LOAD EXPONENT

(X15_23)-7B15_23

14

XEE

046 00160

EXCHANGE EXPONENTS

(B15-23~(X15-23)

14

CNA

04601000

COPY NEGATIVE INTO A

-(A)-7A

14

006200SR

SET EXTENSION REGISTER

SR-7ME

19

0404000T

EXTENSION REGISTER TEST

(ME)T=O

MEMORY EXTENSION

2,3

20

BRANCH
14

BRU

01

BRANCH UNCONDITIONALLY

M-7P

BRX

41

INCREMENT INDEX AND BRANCH

(X)+1-3-X
If X Neg., M-7P
If X Pos., P+1-3-P

1
2

14

BRM

43

MARK PLACE AND BRANCH

(P)-?M;M+1~P

2

15

BRR

51

RETURN BRANCH

(M)+1-?P

2

15

SKE

50

SKIP IF A EQUALS M

If (A)!(M), P+1~P
If (A)=(M), P+2----3l-P

2
3

15

SKG

73

SKIP IF A GREATER THAN M

If (A)::;(M), P+ 1----3l-P
If (A)>(M), P+2----3l-P

2
3

15

SKM

70

SKIP IF A=M ON B MASK

If (B)(A)i(B)(M), P+1-7P
If (B)(A)=(B)(M), P+2-7P

2
3

15

SKA

72

SKIP IF M AND A.DO NOT COMPARE
ONES

If (A)(M)!O, P+ 1-3-P
If (A)(M)=O, P+2----3l-P

2
3

16

SKB

52

SKIP IF M AND B DO NOT COMPARE
ONES

If (B)(M)!O, P+ 1----3l-P
If (B)(M)=O, P+2----3l-P

2
3

16

SKN

53

SKIP IF M NEGATIVE

If (M)~, P+1----3l-P
If (M)M
If (M) Pos., P+1~P
If (M) Neg., P+2----"7P

3

16

TEST AND SKIP

A-21

Mnemonic

Instruction Code

Name

Function

Timing

Page
Ret·

TEST AND SKIP (cont.)
SKD

SKS

74

40

DIFFERENCE EXPONENTS AND SKIP

SKIP IF SIGNAL NOT SET

I{B15-23)-{M15_23)!-7X15_23
If Difference is Pos., P+ 1---7P
If Difference is Neg. f P+2---7P
If Signal=l, P+ 1-7P

If Signal=O, P+2---7P

16
2
3
2
3

27,37
38,42

SHIFT

RSH

06600XXX

RIGHT SHIFT AB

AB Shift Right N Places

2-7

17

RCY

06620XXX

RIGHT CYCLE AB

AB Cycled Right N Places

2-7

17

LRSH

06624XXX

LOGICAL RIGHT SHIFT AB

AB Shift Right N Places

2-7

17

LSH

06700XXX

LEFT SHIFT AB

AB Shift Left N Places

2-5

18

LCY

06720XXX

LEFT CYCLE AB

AB Cycled Left N Places

2-5

18

NOD

06710XXX

NORMALIZE AND DECREMENT INDEX

AB Left and X-l---7X
unti I AriA l' or N Sh ifts

2-5

18

Ha Its Computation

CONTROL
HLT

00

HALT

NOP

20

NO OPERATION

EXU

23

18
19

EXECUTE

Instruction M is Performed,
P is Unchanged

19

BREAKPOINT TESTS
BPTl

04020400

BREAKPOINT NO. 1 TEST

Test Breakpoint Switch

1,2

19

BREAKPOINT NO.2 TEST

Test Breakpoint Switch

1,2

19

BPT2

04020200

BPT3

04020100

BREAKPOINT NO.3 TEST

Test Breakpoint Switch

1,2

19

BPT4

04020040

BREAKPOINT NO.4 TEST

Test Breakpoint Switch

1,2

19

04020001

OVERFLOW INDICATOR TEST AND
RESET

Test Overflow Indicator

1,2

19

OVERFLOW
OVT
ROV

00220001

RESET OVERFLOW

Turn Off Overflow Indicator

19

REO

002 20010

RECORD EXPONENT OVERFLOW

1-70verflow Indicator
if X14#15

18

EIR

00220002

ENABLE INTERRUPT SYSTEM

23

DIR

00220004

DISABLE It'HERRUPT SYSTEM

23

lET

04020004

INTERRUPT ENABLED TEST

Skip if Interrupt System
Enabled

1,2

23

IDT

·04020002

INTERRUPT DISABLED TEST

Skip if Interrupt System
Disabled

1,2

23

INTERRUPT

, "''''':-c.:,

AIR

A-22

00220020

ARM INTERRUPTS

23

Mnemonic

Instruction Code

Name

Function

TIming

Page
Ref.

CHANNEL CONTROL
ALC 0

002 SOOOO

ALERT CHANNEL W

DSC 0

00200000

DISCONNECT CHANNEL W

ASC 0

002 12000

ALERT TO STORE ADDRESS IN
CHANNEL W

(For other channel codes,
see page 3S. )

33

TOP 0

002 14000

TERMINA TE OUTPUT ON CHANNEL W

(For other channel codes,
see page 3S. )

33

CAT 0

040 14000

CHANNEL W ACTIVE TEST; SKIP IF
CHANNEL INACTIVE

(For other channel codes,
see page 39. )

2,3

37

CET 0

040 11000

CHANNEL W ERROR TEST; SKIP IF NO
ERROR

(For other channel codes,
see page 39. )

2,3

37

b

040 10400

CHANNEL W INTER-RECORD TEST

(For other channel codes,
see page 40. )

2,3

38

CZTO

040 12000

CHANNEL W ZERO COUNT TEST;
SKIP IF COUNT EQUALS ZERO

(For other channel codes,
see page 40. )

2,3

38

(For other channel codes,
see page 3S. )
3
(For other channel codes,
see page 3S. )

33
33

CHANNEL TESTS

CIT

IN.PUT/OUTPUT
MIW

12

MINTO W BUFFER WHEN EMPTY

{M)~W

2 + wait

38

MIY

10

MINTO Y BUFFER WHEN EMPTY

{M)~Y

2 + wait

39

WIM

32

W BUFFER INTO M WHEN FULL

{W)~M

3 + wait

39

YIM

30

Y BUFFER INTO M WHEN FULL

{Y)--7M

3 + wait

39

PIN

33

PARALLEL INPUT

{Unit M)~M in Parallel

4 + wait

41

POT

13

PARALLEL OUTPUT

{M)~Unit M in Parallel

3 + wait

41

EOM

02

ENERGIZE OUTPUT M

26,31

EOD

06

ENERGIZE OUTPUT TO DIRECT
ACCESS CHANNEL

27,33

BETW

04020010

W BUFFER ERROR TEST

1,2

37

BETY

04020020

Y BUFFER ERROR TEST

1,2

37

BRTW

04021000

W BUFFER READY TEST

1,2

37

BRTY

04022000

Y BUFFER READY TEST

1,2

37

RKB 0,1,4

00202601

READ KEYBOARD

46

TYP 0, 1,4

00202641

WRITE TYPEWRITER

46

RPTO,I,4

00202604

READ PAPER TAPE

49

PTL 0,1,4

00200644

PUNCH PAPER TAPE WITH LEADER

49

PPTO;1,4

00202644

PUNCH PAPER TAPE WITH NO LEADER

49

TYPEWRITER

PAPER TAPE

A-23

Mnemonic

Name

Instruction Code

Function

Timing

Page
Ref.

~

PUNCHED CARD
CRT 0,1

04012006

CARD READER READY TEST

2,3

53

CFT 0, 1

040 11006

CARD READER END-OF-FILE TEST

2,3

53

RCD 0,1,4

00202606

READ CARD DECIMAL (HOLLERITH)

53

RCBO,1,4

00203606

READ CARD BINARY

CPT 0, 1

040 14046

CARD PUNCH READY TEST

PCD 0, 1,4

00202646

PUNCH CARD DECIMAL (HOLLERITH)

53

PCB 0, 1,4

00203646

PUNCH CARD BINARY

53

FCT 0, 1

04014006

FIRST COLUMN TEST

2,3

53

PBT 0, 1

040 12046

PUNCH BUFFER TEST

2,3

53

SRC 0,1

002 12006

SKIP REMAINDER OF CARD

TRT 0, n

0401041n

TAPE READY TEST

2,3

57

FPT 0, n

040 1401n

FILE PROTECT TEST

2,3

57

BTT 0, n

040 1201n

BEGINNING OF TAPE TEST

2,3

57

ETT 0, n

040 1101n

END OF TAPE TEST·

2,3

58

DT20,n

040 1621n

DENSITY TEST, 200 BPI

2,3

58

DT5 0, n.

040 1661n

DENSITY TEST, 556 BPI

2,3

58

DT8 0, n

040 1721n

DENSITY TEST, 800 BPI

2,3

58

TFT 0

04013610

TAPE END-OF-FILE TEST

2,3

58

TGT O,n

040 1261n

TAPE GAP TEST

2,3

58

WTB 0,n,4

0020365n

WRITE TAPE IN BINARY

58

WTD O,n,4

0020265n

WRITE TAPE IN DECIMAL (BCD)

58

EFT 0,4

0020367n

ERASE TAPE FORWARD

58

ERT 0, n,4

0020767n

ERASE TAPE IN REVERSE

58

RTB 0, n,4

0020361n

READ TAPE IN BINARY

58

RTD 0,n,4

0020261n

READ TAPE IN DECIMAL (BCD)

58

SFB 0, n,4

0020363n

SCAN FORWARD IN BINARY

58

SFD 0, n,4

0020263n

SCAN FORWARD IN DECIMAL (BCD)

58

SRBO, n, 4

0020763n

SCAN REVERSE IN BINARY

58

SRD 0, n,4

0020663n

SCAN REVERSE IN DECIMAL (BCD)

58

REW O,n

002 1401n

REWIND

58
58

53
2,3

53

53

MAGNETIC TAPE

040 1021n

MAGPAK TEST

RTS 0

00214000

CONVERT READ TO SCAN

58

SRR 0

002 13610

SKIP REMAINDER OF RECORD

58

PRT 0, 1

040 12060

PRINTER READY TEST

2,3

63

EPT 0, 1

040 14060

END OF PAGE TEST

2,3

63

PFT 0, 1

040 11060

PRINTER FAULT TEST

2,3

63

POL 0, 1

002 10260

PRINTER OFF-LINE

PSC 0, l,N

002 IN460

PRINTER SKIP TO CHANNEL N

63

2,3

PRINTER

·;.\-24

63

PSPO,l,N

002 lN660

PRINTER SPACE N LINES

63

PLP 0,1,4

00202660

PRINT LINE PRINTER

63

SDS 930 INSTRUCTION LIST-NUMERICAL ORDER
Instruction Code

Mnemonic

Name

Page References

00

HLT

HALT

18

01

BRU

BRANCH UNCONDITIONALLY

14

02

EOM

ENERGIZE OUTPUT M

25,26,27,28,31, 34,41
33

DSC 0

DISCONNECT CHANNEL W

00202601

RKB 0,1,4

READ KEYBOARD

46

00202641

TYP 0, 1,4

WRITE TYPEWRITER

46

00200644

PTL 0,1,4

PUNCH PAPER TAPE WITH LEADER

49

00202604

RPT 0,1,4

READ PAPER TAPE

49

00200000

For other channel codes see page

00202606

RCD 0,1,4

READ CARD DECIMAL (HOLLERITH)

53

0020261n

RTD O,n,4

READ TAPE IN DECIMAL (BCD)

58

0020263n

SFD 0, n,4

SCAN FORWARD IN DECIMAL (BCD)

58

00202644

PPT 0, 1,4

PUNCH PAPER TAPE WITH NO LEADER

49

00202646

PCD 0, 1,4

PUNCH CARD DECIMAL (HOLLERITH)

53

0020265n

WTD 0, n,4

WRITE TAPE IN DECIMAL (BCD)

58

00202660

PLPO,1,4

PRINT LINE PRINTER

63

00203606

RCB 0,1,4

READ CARD BINARY

53

0020361n

RTB 0, n, 4

READ TAPE IN BINARY

58

0020363n

SFB 0, n, 4

SCAN FORWARD IN BINARY

58

00203646

PCBO,1,4

PUNCH CARD BINARY

53

0020365n

WTB 0, n,4

WRITE TAPE IN BINARY

58

0020367n

EFT n,4

ERASE TAPE FORWARD

58

0020663n

SRD 0, n, 4

SCAN REVERSE IN DECIMAL (BCD)

58

0020763n

SRB 0, n, 4

SCAN REVERSE IN BINARY

58

0020767n

ERT 0, n, 4

ERASE TAPE IN REVERSE

58

002 10260

POL 0,1

PRINTER OFF-LINE

63

002 12000

ASC 0

ALERT TO STORE ADDRESS IN
CHANNEL W

For other channel codes, see page

33

002 12006

SRC 0

SKIP REMAINDER OF CARD

53

002 13610

SRR 0

SKIP REMAINDER OF RECORD

58

002 14000

TOPO

TERMINATE OUTPUT ON
CHANNEL W

00214000

RTS 0

For other channel codes, see page

34

CONVERT READ TO SCAN

58

002 1401n

REW 0, n

REWIND

58

002 1N460

PSC 0, I, N

PRINTER SKIP TO CHANNEL N

63

002 1N660

PSP 0, I, N

PRINTER SPACE N LINES

63

00220001

ROV

RESET OVERFLOW

19

00220002

EIR

ENABLE INTERRUPT SYSTEM

23

00220004

DIR

DISABLE INTERRUPT SYSTEM

23

00220010

REO

RECORD EXPONENT OVERFLOW

18

A-25

Instruction Code

Name

Mnemonic

00220020

AIR

ARM INTERRUPTS

00250000

ALC 0

ALERT CHANNEL W

EOD

ENERGIZE OUTPUT TO DIRECT ACCESS
CHANNEL

06
006200SR

Page References
23
For other channel' codes, see page 33
27,28,33,34

SET EXTENSION REGISTER

19
39

10

MIY

MINTO Y BUFFER WHEN EMPTY

12

MIW

MINTO W BUFFER WHEN EMPTY

38

13

POT

PARALLEL OUTPUT

41

14

ETR

EXTRACT

11

16

MRG

MERGE

11

17

EOR

EXCLUSIVE OR

11

20

NOP

NO OPERATION

19

23

EXU

EXECUTE

19

30

YIM

Y BUFFER INTO M WHEN FULL

39

32

WIM

W BUFFER INTO M WHEN FULL

39

33

PIN

PARALLEL INPUT

41

35

STA

STORE A

8
8
8

36

STB

STORE B

37

STX

STORE INDEX

40

SKS

SKIP IF SIGNAL NOT SET

040 1021n

MAGPAK TEST

27, 37, 38, 42
58

040 10400

CIT 0

CHANNEL W INTER-RECORD TEST

0401041n

TRT 0, n

TAPE READY TEST

040 11000

CET 0

CHANNEL W ERROR TEST; SKIP IF
NO ERROR

040 11006

CFT 0, 1

CARD READER END-OF-FILE TEST

53

040 1101n

ETT 0, n

END OF TAPE TEST

58

040 11060

PFT 0,1

PRINTER FAULT TEST

63

040 12000

CZT 0

CHANNEL W ZERO COUNT TEST;
SKIP IF COUNT EQUALS ZERO

for other channel codes, see page 38
57
For other channel codes, see page 37

For other channel codes, see page 38

040 .12006

CRT 0,1

CARD READER READY TEST

53

040 1201n

BTT 0, n

BEGINNING OF TAPE TEST

57

o 40

PBT 0, 1

PUNCH BUFFER TEST

53
63

12046

040 12060

PRT 0,1

PRINTER READY TEST

040 1261n

TGT O,n

TAPE GAP TEST

58

04013610

TFT 0

TAPE END-Of-FILE TEST

58

040 14000

CAT 0

CHANNEL W ACTIVE TEST; SKIP IF
CHANNEL INACTIVE

For other channel codes, see page 37

040 14006

FCT 0, 1

FIRST COLUMN TEST

53

o 40

1401n

FPT 0, n

FILE PROTECT TEST

57

040 14046

CPT 0, 1

CARD PUNCH READY TEST

53

040 14060

EPT 0,1

END OF PAGE TEST

63

040 1621n

DT2 0, n

DENSITY TEST, 200 BPI

58

040 1661n

DT5 0, n

DENSITY TEST, 556 BPI

58

A-26

Instruction Code

Mnemonic

Name

Page References

o 40 1721n
o 40 20001

DT8 0, n

DENSITY TEST, 800 BPI

58

OVT

OVERFLOW INDICATOR TEST AND RESET

19

04020002

!DT

INTERRUPT DISABLED TEST

23

04020004

lET

INTERRUPT ENAB~ED TEST

2~

04020010

BETW

W BUFFER ERROR TEST

37

·04020020

BETY

Y BUFFER ERROR TEST

37

04020040

BPT4

BREAKPOINT NO.4 TEST

19

04020100

BPT3

BREAKPOINT NO.3 TEST

19

04020200

BPT2

BREAKPOINT NO.2 TEST

19

04020400

BPTl

BREAKPOINT NO. 1 TEST

19

04021000

BRTW

W BUFFER READY TEST

37

04022000

BRTY

Y BUFFER READY TEST

37

EXTENSION REGISTER TEST

20

INCREMENT INDEX AND BRANCH

14

0404000T
41

BRX
BRM

MARK PLACE AND BRANCH

15

04600001

CLA

CLEAR A

12

04600002

CLB

CLEAR B

12

04600003

CLR

CLEAR AB

12

04600004

CAB

COpy A INTO B

12

04600005

ABC

COpy A INTO B, CLEAR A

13

04600010

CBA

COPY B INTO A

12

04600012

BAC

COPY B INTO A, CLEAR B

13

04600014

XAB

EXCHANGE A AND B

12

04600020

CBX

COPY B INTO INDEX

13

04600040

CXB

COPY INDEX INTO B

13

04600060

XXB

EXCHANGE INDEX AND B

13

04600122

STE

STORE EXPONENT

13
14

43

04600140

LDE

LOAD EXPONE NT

04600160

XEE

EXCHANGE EXPONENTS

14

04600200

CXA

COPY INDEX INTO A

13

04600400

CAX

COPY A INTO INDEX

13

04601000

CNA

COPY NEGATIVE INTO A

14

24600000

13

CLX

CLEAR INDEX REGISTER X

50

SKE

SKIP IF E EQUALS M

15

51

BRR

RETURN BRANCH

15

52

SKB

SKIP IF M AND B DO NOT COMPARE ONES

16

53

SKN

SKIP IF M NEGATIVE

16
10

54

SUB

SUBTRACT

55

ADD

ADD M TO A

56

SUC

SUBTRACT WITH CARRY

57

ADC

ADD WITH CARRY

60

SKR

REDUCE M, SKIP IF NEGATIVE

61

MIN

MEMORY INCREMENT

9
10
9
16
9

A-V

Instruct.ion Code

p,oge Reference.s .

62.

XMA

EXCHANGE M AND A .

9

63

ADM

ADD A·TO M

9

64

MUL

MULTIPLY

65

DIV

DIVIDE

11

RSH

RIGHT SHIFT AB

17

RCY

RIGHT CYCLE AB

17

LRSH

LOGICAL RIGHT SHIFlAB

LSH

LEFT SHIFT AB

18

NOD

NORMALIZE AND DECREMENT INDEX

L8

LCY

LEFT CYCLE AB

18

70

SKM

SKIP IF A=M ON B MASK

71

LOX

LOAD INDEX

72

SKA

SKIP IF M AND A DO NOT COMpARE ONES

16

73

SKG

SKIP IF A GREATER THAN M

15

74

SKD

DIFFERENCE EXPONENTS AND SKIP

16

75

LOB

LOAD B

8

76

LOA

LOAD A

8

77

EAX

COPY EFFECTIVE ADDRESS INTO INPEX REGISTER

8

o 6600XXX
o 6620XXX
o66'24XXX
o 6700XXX
o 6710XXX
o 6720XXX

A-28

N~me

Mnemonic

.~.

10

;

")

\",'

,

.,

17

15
8

SDS 930 INSTRUCTION LIST - ALPHABETICAL ORDER
Mnemonic

Instruction Code

ABC

04600005

Name
COpy A INTO B, CLEAR A

Page References
13

ADD WITH CARRY

9

55

ADD M TO A

9

63

ADD A TO M

9

ADC

57

ADD
ADM
AIR

00220020

ARM INTERRUPTS

ALC 0

00250000

ALERT CHANNEL W

For other channel codes, see page 33

ASC 0

002 12000

ALERT TO STORE ADDRESS IN
CHANNEL W

For other channel codes, see page 33

23

BAC

04600012

COpy B INTO A, CLEAR B

1·3

BETW

04020010

W BUFFER ERROR TEST

37

BETY

04020020

Y BUFFER ERROR TEST

37

BPTl

04020400

BREAKPOINT NO. 1 TEST

19

BPT2

04020200

BREAKPOINT NO. 2 TEST

19

BPT3

04020100

BREAKPOINT NO. 3 TEST

19

BPT4

04020040

BREAKPOINT NO.4 TEST

19

BRM

43

MARK PLACE AND BRANCH

15

BRR

51

RETURN BRANCH

15

BRTW

04021000

W BUFFER READY TEST

37

BRTY

04022000

Y BUFFER READY TEST

37

BRU

01

BRANCH UNCONDITIONALLY

14

BRX

41

INCREMENT INDEX AND BRANCH

14

BHO,n

040 1201n

BEGINNING OF TAPE TEST

57

CAB

04600004

COPY A INTO B

12

CAT 0

04014000

CHANNEL W ACTIVE TEST; SKIP IF
CHANNEL INACTIVE

For other channel codes, see page 37
13

CAX

04600400

COpy A INTO INDEX

CBA

04600010

COpy B INTO A

12

CBX

04600020

COpy B INTO INDEX

13

CET 0

040 11000

CHANNEL W ERROR TEST; SKIP IF
NO ERROR

CFT 0, 1

040 11006

CARD READER END-OF-FILE TEST

CIT 0

04010400

CHANNEL W INTER-RECORD TEST

CLA

04600001

CLEAR A

12

CLB

04600002

CLEAR B

12

CLR

04600003

CLEAR AB

12

CLX

24600000

CLEAR INDEX REGISTER X

13

CNA

046 01000

COpy NEGATIVE INTO A

14

CPT 0, 1

040 14046

CARD PUNCH READY TEST

53

CRT 0, 1

040 12006

CARD READER READY TEST

53

For other channel codes, see page 37
53
For other channel codes, see page 38

A-29

Name

Page References

Mnemonic

Instruction Code

CXA

04600200

COPY INDEX INTO A

13

CXB

04600040

COPY INDEX INTO B

13

CZT 0

040 12000

CHANNEL W ZERO COUNT TEST;
SKIP IF COUNT EQUALS ZERO

38

DIR

00220004

DISABLE INTERRUPT SYSTEM

23

DIVIDE

11

DIV

65

DSC 0

00200000

DISCONNECT CHANNEL W

DT2 0, n

040 1621n

DENSITY TEST, 200 BPI

58

DT5 0, n

040 1661n

DENSITY TEST, 556 BPI

58

DT8 0, n

040 1721n

DENSITY TEST, 800 BPI

58

EAX

77

For other channel codes, see page

33

COpy EFFECTIVE ADDRESS INTO
INDEX REGISTER

8

EFT n,4

0020367n

ERASE TAPE FORWARD

58

EIR

00220002

ENABLE INTERRUPT SYSTEM

23

EOD
EOM
EOR

06
02

ENERGIZE OUTPUT M

27,28,33,34
25,26,27,28,31,34,41

EXCLUSIVE OR

11

EPT 0,1

040 14060

END OF PAGE TEST

63

ERT O,n,4

0020767n

ERASE TAPE IN REVERSE

58

EXTRACT

11

END OF TAPE TEST

58

EXECUTE

19

ETR
ETT 0, n
EXU

17

ENERGIZE OUTPUT TO DIRECT ACCESS
CHANNEL

14
040 1101n
23

FCT 0, 1

040 14006

FIRST COLUMN TEST

53

FPT 0, n

040 1401n

FILE PROTECT TEST

57

HALT

18

HLT

00

IDT

04020002

INTERRUPT DISABLED TEST

23

lET

04020004

INTERRUPT ENABLED TEST

23

lORD

I/O OF A RECORD AND DISCONNECT

35

IORP

I/O OF A RECORD AND PROCEED

35

IOSD

I/O UNTIL SIGNAL THEN DISCONNECT

35

IOSP

I/O UNTIL SIGNAL THEN PROCEED

36

LEFT CYCLE AB

18

LCY

06720XXX

lOA

76

LOAD A

lOB

75

LOAD B

lOE
LDX

04600140
71

LRSH

06624XXX

I:SH

06700XXX

LOAD EXPONENT
LOAD INDEX

8
8
14
8

LOGICAL RIGHT SHIFT AB

17

LEFT SHIFT AB

18

MIN

61

MEMORY INCREMENT

MIW

12

MINTO W BUFFER WHEN EMPTY

38

MIY

10

MINTO Y BUFFER WHEN EMPTY

39

MRG

16

MERGE

11

A-30

9

Mnemonic
MUL
NOD
NOP

Instruction Code
64
067 lOXXX
20

Name

Pa~e

References

MULTIPLY

10

NORMALIZE AND DECREMENT INDEX

18

NO OPERATION

19

OVT

o 40 20001

OVERFLOW INDICATOR TEST AND RESET

19

PBT 0, 1

020 12046

PUNCH BUFFER TEST

53

PCB 0,1,4

00203646

PUNCH CARD BINARY

53

PCD 0, 1,4

00202646

PUNCH CARD DECIMAL (HOLLERITH)

53

PFT 0, 1

040 11060

PRINTER FAULT TEST

63

PARALLEL INPUT

41

PIN

33

PLP 0, 1,4

00202660

PRINT LINE PRINTER

63

POL 0, 1

002 10260

PRINTER OFF LINE

63

PARALLEL OUTPUT

41

POT

13

PPTO,1,4

00202644

PUNCH PAPER TAPE WITH NO LEADER

49

PRT 0, 1

040 12060

PRINTER READY TEST

63

PSC 0, 1,N

002 lN460

PRINTER SKIP TO CHANNEL N

63

PSP 0, 1,N

002 lN660

PRINTER SPACE N LINES

63

PTL 0, 1,4

00200644

PUNCH PAPER TAPE WITH LEADER

49

RCB 0, 1,4

00203606

READ CARD BINARY

53

RCD 0,1,4

00202606

READ CARD DECIMAL (HOLLERITH)

53

RCY

06620XXX

RIGHT CYCLE AB

17

REO

00220010

RECORD EXPONENT OVERFLOW

18

REW O,n

002 1401n

REWIND

58

RKB 0, 1,4

00202601

READ KEYBOARD

46

ROV

00220001

RESET OVERFLOW

19
49

RPT 0,1,4

00202604

READ PAPER TAPE

RSH

06600XXX

RIGHT SHIFT AB

17

RTBO,n,4

0020361n

READ TAPE IN BINARY

58

RTD 0, n,4

0020261n

READ TAPE IN DECIMAL (BCD)

58

RTS 0

002 14000

CONVERT READ TO SCAN

58

SFB 0, n, 4

0020363n

SCAN FORWARD IN BINARY

58

SFD 0, n,4

0020263n

SCAN FORWARD IN. DECIMAL (BCD)

58

SKA

72

SKIP IF M AND A DO NOT COMPARE
ONES

16

SKB

52

SKIP IF M AND B DO NOT COMPARE
ONES

16

SKD

74

DIFFERENCE EXPONENTS AND SKIP

16

SKE

50

SKIP IF A EQUALS M

15

SKG

73

SKIP IF A GREATER THAN M

15

SKM

70

SKIP IF A=M ON B MASK

15

SKN

53

SKIP IF M NEGATIVE

16

SKR

60

REDUCE M, SKIP IF NEGATNE

16

A-31

Mnemonic
SKS

Instruction Code

40

Name
SKIP IF SIGNAL NOT SET

Page References
27,37,38,42

SRB 0, n, 4

0020763n

SCAN REVERSE IN BINARY

58

SRC 0,1

002 12006

SKIP REMAINDER OF CARD

53

SRD 0, n, 4

0020663n

SCAN REVERSE IN DECIMAL (BCD)

58

SRR 0

002 13610

SKIP REMAINDER OF RECORD

58

STA
STB
STE

35

STORE A

36

STORE B

04600122

STORE EXPONENT

8
8
13

STX

37

STORE INDEX

SUB

54

SUBTRACT

10

56

8

SUBTRACT WITH CARRY

10

040 13610

TAPE END-OF-FILE TEST

58

TGT O,n

040 1261n

TAPE GAP TEST, CHANNEL W

58

TOP 0

002 14000

TERMINATE OUTPUT OF CHANNEL W

TRT O,n

0401041n

TAPE READY TEST

57

TYP 0,1,4

00202641

WRITE TYPEWRITER

46

W BUFFER INTO M WHEN FULL

39

SUC
. TFT 0

WIM

32

33,34

WTBO,n,4

0020365n

WRITE TAPE IN BINARY

58

WTD 0,n,4

0020265n

WRITE TAPE IN DECIMAL (BCD)

58

XAB

04600014

EXCHANGE A AND B

12

XEE

04600160

EXCHANGE EXPONENTS

14

XMA

62

XXA

04600600

XXB

04600060

YIM

A-32

30

EXCHANGE M AND A

9

EXCHANGE INDEX AND A

13

EXCHANGE INDEX AND B

13

Y BUFFER INTO M WHEN FULL

39

"

SCIENTIFIC DATA SYSTEMS

1649 Seventeenth Street· Santa Monica, California· Phone (213) UP 1- 0960



---

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