900505C_SDS_92_Reference_Jun65 900505C SDS 92 Reference Jun65
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SCIENTIFIC DATA SYSTEMS
Reference Manual
SOS 92 BASIC INSTRUCTIONS (CENTRAL PROCESSOR)
Mnemonic
Octal Code
Name
LOAD/STORE
LDA
LDB
STA
STB
XMA
XMB
A, T
A, T
A, T
A, T
A, T
A, T
64
24
44
04
74
34
XMF A, T 17
LDF A, T 57
0044
SFT
SFF
0042
INF
0046
Load A
Load B
Store A
Store B
Exchange Memory and A
Exchange Memory and B
Exchange Memory and F
Load F
Set Flag True
Set Flag False
Invert Flag
ARITHMETIC
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
62
22
63
23
60
20
61
21
76
36
16
56
13
53
52
12
Add to A
Add to B
Add with Carry to A
Add with Carry to B
Subtract to A
Subtrac t to B
Subtract with Carry to A
Subtract with Carry to B
Memory Plus A to Memory
Memory Plus B to Memory
Memory Plus One to Memory
Memory Plus Flag to Memory
Multiply A (Optional)
Multiply B (Optional)
Divide AB (Optional)
Divide BA (Optional)
LOGICAL
ANA
ANB
ORA
ORB
EOA
EOB
MAA
MAB
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
65
25
67
27
66
26
75
35
AND to A
AND to B
OR to A
OR to B
Exclusive OR to A
Exclusive OR to B
Memory AND A to Memory
Memory AND B to Memory
45
05
47
07
46
06
Compare
Compare
Compare
Compare
Compare
Compare
BRU
BRC
BRL
BFF
BFT
BDA
BAX
BRM
BMC
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A, T
37
Branch Unconditionally
Branch, Clear Interrupt, and Load Flag
Branch and Load Flag
Branch on Flag False
Branch on Flag True
Branch on Decrementing A
Branch and Exchange A and B
Branch and Mark Place
Branch, Mark Place, and Clear Flag
42
02
43
03
02 or 42
43
03
Cycle
Cycle
Cyc Ie
Cycle
Cycle
Cycle
Cycle
73
32
33
31
71
70
30
77
SHIFT
CYA
CYB
CFA
CFB
CYD
CFD
CFI
A, T
A, T
A, T
A, T
A, T
A, T
A, T
A
B
Flag and
Flag and
Double
Flag and
Flag and
A
B
Double
Double Inverse
CONTROL
EXU A, T 72
0041 or
HLT
00000000
Execute
Halt
TRAP
SCT
RCT
TCT
0061
0060
0160
Set Program-controlled Trap
Reset Program-controlled Trap
Test Program-controlled Trap
BREAKPOINT TESTS
BPT
BPT
BPT
BPT
1
2
3
4
0144
0145
0146
0147
Breakpoint
Breakpoint
Breakpoint
Breakpoint
0051
0050
0150
00020001
Enab Ie Interrupt
Disab Ie Interrupt
Interrupt Enabled Test
Arm Interrupts
No.
No.
No.
No.
1 Test
2 Test
3 Test
4 Test
INTERRUPTS
EIR
DIR
lET
AIR
COMPARISON
COA
COB
CMA
CMB
CEA
CEB
Name
Octal Code
BRANCH
FLAG
ADA
ADB
ACA
ACB
SUA
SUB
SCA
SCB
MPA
MPB
MPO
MPF
MUA
MUB
DVA
DVB
Mnemonic
Ones with A
Ones with B
Magnitude of Memory with A
Magnitude of Memory with B
Memory Equa I to A
Memory Equal to B
Legend:
A = address; * A = indirect address; =A = immediate address; T = index tag
SOS 92 COMPUTER
REFERENCE MANUAL
June 1965
Ell' -\I!J
SCIENTIFIC DATA SYSTEMS/1649 Seventeenth Street/Santa Monica, Cal ifornia
@1965 Scientific Doto Systems, Inc.
Printed in U.S.A.
REVISIONS
Th is pu bl ication, 90 05 05C, supersedes the SDS 92 Computer Reference Manual, 900505B.
Revisions, corrections, and clarifications to the previous edition are indicated by a vertical
I ine in the left or right marg in of the page.
ii
CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . .
SDS 92 Registers . . . . . . . . . . . . .
SDS 9.2 Memory . . . . . . . . . . . . . .
Memory Word Formats . . . . . . . . . .
Addressing Facil ities . . . . . . . . . .
Trapping Facil ity . . . . . . . . . . . . .
II
1-1
APPENDIX A
1-3
1-4
1-4
1-4
SDS Character Codes
Table of Powers of Two . . . . . . . . . . . . .
Octal-Decimal Integer Conversion Table ..
Octal-Decimal Fraction Conversion Table .
Two's Complement Arithmetic . • . . . . . . .
1-6
2-1
MACHINE INSTRUCTIONS
Load;Store Instructions . . . . . . . . .
Flag Instructions . . . . . . . . . . . . .
Logical Instructions . . . . . . . . . . .
Comparison Instructions . . . . . . . . .
Branch Instructions . . . . . . . . . . . .
Shift Instructions . . . . . . . . . . . . .
Control Instructions
Trapping Instructions
..........
Breakpo i nt Tests . . . . . . . . . . . . .
III
.
.
.
.
.
.
APPENDIXES
1-1
.
.
.
.
.
.
Optional Equipment
Real-Time Clock
Automatic Power Fail-Safe . . . . . . . . .
Data Mu Itiplexing System . . . . . . . . .
Memory Parity Interrupts . . . . . . . . . .
Trapping Return Subroutine Example . . . . .
SDS 92 Memory Allocation
......... .
92 Instruction List - Functional Categories .
92 Instruction List - Numerical Order . . . .
92 Instruction List - Alphabetical Order
2-2
.
.
INPUT/OUTPUT SYSTEM . . . . . . . . . . . .
3-1
Introdu ct ion . . . . . . . . . . . . . . . . .
Data Transfer Instructions . . . . . . . .
I/O Channel Operation . . . . . . . . . .
EOM Instructions . . . . . . . . . . . . . .
SES Instructions . . . . . . . . . . . . . . .
Interlace . . . . . . . . . . . . . . . . . . .
POT/BPO, PIN/BPI Instructions
Single Bit Input/Output . . . . . . . . . .
I/O Termination Programming Notes ..
Priority Interrupt System (Optional) ..
Control Console . . . . . . . . . . . . . . .
Peripheral Equ ipment Description . . . .
Input/Output Typewriter . . . . . . .
Paper Tape Input/Output . . . . . . .
Card Input/Output . . . . . . . . . . .
Magnetic Tape Input/Output
Line Printer . . . . . . . . . . . . . . .
3-1
3-2
3-3
3-5
3-6
3-7
3-8
3-9
3-9
A-3
A-7
A-lO
I
B-1
B-1
B-1
B-1
B-4
I
APPENDIX B
2-1
2-3
2-4
2-4
2-5
2-6
2-7
2-7
A-1
A-2
B-5
B-6
B-7
B-11
B-15
FIGURES
1-1
1-2
3-1
3-2
3-3
3-4
3-5
3-6
3-10
3-13
3-15
3-15
3-17
3-18
3-21
3-25
SDS 92 Computer (Frontispiece)
......
SDS 92 Computer Configuration
......
Basic Register Flow Diagram . . . . . . . . .
ROT/RIN Data Transmission . . . . . . . . .
SDS 92 Channel Buffer . . . . . . . . . . . .
Interrupt Arm-Enable Response . . . . . . .
SDS 92 Computer Control Panel
......
Card Read into Memory in Hollerith . . . .
Printer Control Indicators and Switches
.
.
.
.
.
.
.
.
iv
1-2
1-3
3-2
3-3
3-12
3-14
3-19
3-25
TABLES
3-1
3-2
3-3
iii
Unit Address Codes
Interrupt Location Assig nments . . . . . . . .
Format Control Characters . . . . . . . . . . .
3-4
3-11
3-26
,
•
J
Iliin
~"
SDS 92 Computer
iv
I. GENERAL DESCRIPTION
INTRODUCTION
•
6-bit characters, 286,000 characters/second,
parity checked and packed 1 per word
The SDS 92 is a small, high-speed, very low-cost, generalpurpose computer designed especially to include application
in the following areas:
•
High-speed computer-based systems featuring speed
and flexibility
•
Format conversion featuring complete versatility in
formats and equipment involved
•
Three standard I/O modes:
6-bit characters, 286,000 characters/second,
parity checked and packed 2 per word
12-bit parallel words, 572,000 words/second,
parity checked
Small, general-purpose applications featuring repetitive, high-speed computation
•
I/O transfer of 12-bit characters, 286,000 characters/
second, parity checked, optional
•
Four console sense switches
•
Optional features
Interlace feature for standard I/O buffer
The SDS 92 has the following characteristics:
High-speed multiply and divide instructions,
5 and 13 cycles, respectively
•
The first commercia I computer using monolithic integrated circuits; all fl ip-flops are integrated
•
12-bit word plus parity bit
•
1.75 jJsec memory cyc Ie
•
Binary, integer arithmetic
•
12- and 24-bit instructions
•
Immediate, direct and indirect addressing
Keyboard/printer (teletype) with or without
paper tape reader and punch, 10 cps
•
2048-word basic memory
Paper tape reader and punch, 300 and 60 cps,
respectively
•
Memory expandable to 4096, 8192, 16,384 or 32,768
words, all directly addressable
MAGPAK Magnetic Tape System
Many-channel Data Multiplexing System using
a second, independent path to memory
24-bit parallel I/O
Up to 256 levels of true priority interrupt
Automatic power fai I-safe
Memory parity checking
Real-time clock
•
Peripheral equipment for the SDS 92
All equipment in SDS standard peripheral line
•
Two independent arithmetic registers, either of which
may be an accumulator
•
True Index Register; adds no time to execution
•
Instruction set comparable to medium-scale computer;
includes shift instructions
•
Software
Basic uti lity package
•
•
•
Symbolic assembler
I/O packages for optional peripheral equipment
Mathematical subroutines, including floatingpoint arithmetic, fixed-point multiply and divide,
and elementary mathematical functions
4096 single-bit control outputs; 4096 single-bit sense
inputs
•
All silicon semiconductors
Independent I/O buffer with automatic assembly/
disassemblyof 6-bit characters to/from words (standard)
•
O perating temperature range:
•
Dimensions: 65 in. x 30 in. x 25-1/2 in.
I/O block transfer standard
•
Power: 1 kva
1-1
0
100 to 40 C
Priority Interrupt
up to 256 Levels
I
I
I J
•
t t t
EOM
•
•
t
2048 Words
Expandable to :
SES
Core
Memory
SDS 92
Computer
12-bit Word POT/PIN
Para II e I,
Single Word BPO/BPI
or Bloc k
(24-bit Single
Word 0 ptional)
t
I
I
I
I
I
I
I
I
Basic I/O Channel
.--_
I
..
L__
I
6 bits
I
Second Memory Path
I
~
12 bits
Optional
4K
8K
16K
32K
I
12 bits
WOT;WIN
ROT/RIN
(plus parity) {}
~
t
I
f
t
I
t
External
Devices
!
Data Multiplex System
I
f
• • •
I
f
Subchannels
(6-bit, 12-bit, or 24-bit)
Items with dotted lines (---) are optional.
Figure 1-1.
t
4
SDS 92 Computer Configuration
1-2
SDS 92 REGISTERS
The Flag Bit Register is a one-bit register used for arithmetic
carry, storage and testing.
The 92 Central Processor contains the following arithmetic and
control registers. They are full-word, 12-bit registers except
as noted.
NOT AVAILABLE TO THE PROGRAMMER (light lines)
The S Register is a 15-bit register that contains the address of
the memory location being accessed for instructions or data.
AVAILABLE TO THE PROGRAMMER (dark lines)
The C Register, is a 12-bit register that is used in arithmetic and
control operations.
The A Register and the B Register are two independent, 12-bit
accumulators. The A Register is also the index register.
The 0 Register is a 6-bit register that contains the operation
code of the instruction being executed.
The P Register is a 15-bit register that contains the memory
address of the current instruction. Unless modified by the program, the contents of P increase by one during one-word instructions and increase by two during two-word instructions.
The M Register is a 13-bit register that holds each word as it
comes from memory. Recopying of a word into memory takes
place from the M Register.
B
(Accumu lator)
1
Flag B;,
j
F
I
A
(Accumulator and/
or Index)
j
Adder
,
--
S
(Memory Address)
P
(Program Counter)
,
C
(Arithmetic and
Control)
-
--
M
(Memory Access)
Memory
--------------------~
Figure 1-2.
Basic Register Flow Diagram
1-3
o
(Opcode)
offers great versatility both in addressing and indexing capabilities. In most cases, the instruction can select either the A or
B for use as the accumulator.
SDS 92 MEMORY
The basic 92 memory contains 2048 words, consisting of 12{,its
plus parity. Memory is available in 4096-, 8192-, 16,384and 32,768-word sizes. The central processor can directly address all memory. Addresses for memory words extend from locations 00000 to 77777 (octal). If the address of the next
instruction to be executed is outside of available memory (for
less than 32,768-word memories), the 92 executes a halt instruction (00000000); the P Register wi II contain the requested
address + 2. For example, assume a 3777-word memory and
Bit Position
Meaning
o
Register Selection:
1-5
Instruction Code
6
Scratch Pad Bit
1 = A Register
B Register
o=
1.
the instruction "Branch-to" 4000, or
7
Indirect Address Bit
2.
the instruction "Load A" whose location is 3777.
8
Index Register Bit
9-11
Part of the Address Field
In both cases, a halt occurs after execution of the instruction
and the P Register contains 4002 which is outside of available
memory. Note that the P Register responds as if there were
always 32,768 words of memory. With a 32,768-word memory,
the memory is a "wrap-around" or circular memory where the
next location after 77777 is 00000. An attempt to read from a
location whose address is not avai lable causes zeros to be read.
An attempt to store into such a location essentially results in a
"no-op" operation, with the next instruction in sequence being
executed. A program can use th is property to determine the
core size avai lable in the machine.
r
The flexibility of addressing in the 92 allows bits 7, 8, and 9
through 11 to be used in more than one way as explained below.
ADDRESSING FACILITIES
The 92 has one-word or two-word instructions with the length
depending on the addressing mode being used. The addressing
modes are:
Addressing Area
A power fai I-safe option is avai lable such that: before accessing each memory word, the co;"puter checks the power to ensure that it can complete the entire read/write cycle.
If it
detects a power loss, the computer halts.
Direct, Two Words
Indirect, One Word
Indirect, Two Words
Direct, One Word
Immediate, One Word
With the memory parity option, the computer automatically
generates even parity or checks for it during each read/write
cycle (optional). Setting a control panel pa~ity switch causes
the computer to halt automatically in case of parity error
detection.
Full Memory
Indirect Through Scratch Pad
Indirect Through Full Memory
Scratch Pad
Next Location
Indirect addressing can be cascaded indefinitely.
The standard assembler forms for instructions are:
MEMORY WORD FORMATS
Form
Type
A computer word is 12 binary digits (bits) long:
Label
Label
Label
Label
IIIIIII" IIII
o
2
3
4
5
6
7
8
9
The word format numbers the bits from the left, or most significant end of the word, to the right, or least significant end of
the word. This numbering format serves as a basis of reference
to bit positions or bit numbers. Octal notation most easi Iy describes the contents of the 12 bits of a word. Thus, one octal
digit, 0 through 7, represents three binary digits. For example,
the octal number, 0123, represents its binary equivalent,
000 001 010 011.
The programmer selects direct addressing by setting both bits 6
and 7 to zero. Bits 9 through 11 of the first word combine with
the entire second word to form a 15-bit address to directly address up to 32,768 words. Bit 8 of the first word can specify
indexing.
y
6
7
8
9
n is a label or a 1- to 5-digit number,
c is a 1- to 4-digit number «4096).
Direct Addressing
I
5
Direct, One and Two Words
Direct, Two Words, Index
Indirect, One and Two Words
Immediate
The following section describes the bit configurations that the
octal programmer or the symbolic assembler must provide to
select the various addressing modes.
The 92 instruction word:
o
n
n, 1
*n
=c
10 11
where
Opcode
Opcode
Opcode
Opcode
Qpcode
r The multiply instructions are exceptions.
10 11
1-4
Note:
Instruction Form:
Although the A Register is only 12 bits long, the top
three bits of the address will be modified by indexing
if a "borrow" occurs.
HI
Scratch Pad Addressing
LOW
o
2
3
4
5
6
7
8
9
Memory locations 00001 to 000378 are referred to as the
"scratch pad" memory and are special only in that they can be
addressed more si mply.
10 11
Direct Addressing With No Indexing
When the programmer sets the Scratch Pad Indicator (bit 6) to 1, the
instruction addresses one of the 31 scratch pad locations. This allows
a complete instruction in a single word. The form of the instruction is:
The computer constructs the 15-bit direct address from bits 9,
10, 11 of the instruction word and bits 0 through 11 of the
next location.
Example
1:
1
Opcode
o
0
Opcode
I RI
0
I
5
1 101
6
3
0
1
7
8
1M
9 10 11
2' 3
0
4
0
0
0
51 6
7
8
1
9
5
16
7
8
Example: Assume
.--location
34
IM+ 1
I
9
I
10 11
10
,
Contents
2333
Then the instruction:
10 11
LDB
2
Assembler Form:
Scratch Pad
Address
The value of n must be in the range 1 ~ n ~ 31
.. 32000
2
I
.,
034
4
LDB 024300
0
Machine Language Form:
2
yields (8)
3
4
5
I
6
7
7
4
8
I
9 1011
= 2333
2
4
2
Immediate Addressing
4
3
o
When the programmer sets the Scratch Pad Indicator to 1 and
sets bits 7 through 11 to 00, the instruction acquires its address
by adding one to the current contents of the $ Register. That
is, the next location contains the operand. The computer
automatically increments the Program Counter by an additional
one to take the next instruction from the word following the
immediate operand word.
o
234
Note:
5
6
7
8
9
10 11
In the standard assembler, a 0 precedes any octal number; noth i ng precedes a dec i ma I number written as a
literal (i. e., immediate).
Direct Addressing With Indexing
The form of the instruction is:
1
When the programmer sets the Index Bit (number 8) to 1, the
computer subtracts the contents of the A Register from the direct address to obtain the effective address.
I
I
I
o 0 o 0
Opcode
OPERAND
MMMMM
NNNN
Effective Address
2 3
4
5
6
7 8
9 10 11
The standard assembler form is: LDA =, where
the following number literally".
Example 2: Assume (A)=OOOl
Assembler Form:
t
o
"=" means
"take
Example:
- - LDA = 04311
LDB 024300,
Machine Language Form:
6
o
2
2
M
4
o
M+ 1
4
o
10 11
2 3
4
5
6
7 8
9 10 11
In the standard assembler, a 0 precedes any octal number;
nothing precedes a decimal number written as a literal (i. e.,
immediate).
This instruction loads the contents of location
24277 into the B Register.
1-5
Take LDB
Indirect Addressing
The indirect addressing facility provides two ways of specifying
the IIpointing II address.
Indirect From Scratch Pad
0
First, the single-word instruction specifies that the pointing
address is within the second 16 locations of the Scratch Pad
area (locations 208 through 378). The specified pointing address used in the standard assembler form must be in the range:
20.::; n ::; 36, n even.
4
2
3
2
0
0
0
2 : 3 4
5 : 6
7
8: 9
10 11
The logic reinitializes addressing and
( 14020) :or: 2200----B
The two Pointer words can specify all forms of addressing.
TRAPPING FACILITY
Program-Control Ied
4
The program-controlled trapping facility permits the calling of
subroutines with a single instruction of the same form as builtin, machine instructions. The trapping is controlled by the
status of the Program-Controlled Trap (PCT) bit. When PCT is
a 0, the computer decodes the eight trapping Opcodes as special instructions and executes the Opcode in the unique trapping location determined by the Opcode. When PCT is a 1,
the computer decodes the eight Opcodes as normal instructions.
The Opcodes, their normal names, and their respective trapping locations follow.
where bit 6 is 0 and bits 7 and 8 are l.
Bits 8 9 10 11 and C form a five-bit address that selects
the fi;st ~f t~o c~ntiguous address words. The computer always
supplies a least significant fifth bit (C) that is zero, making all
such Scratch Pad addresses even. When the addressing logic
selects the even address, it reinitiates addressing and interprets
that location and the next one as an instruction word-pair without an instruction code. These two (or one) words can specify
all forms of addressing.
Bit 8 of the instruction does not effect indexing in this operating mode.
Example:
0002
0010
Since the 0 in bits 6,7,8 of location 34 indicates direct addressing, the instruction does the following:
=
POT
BPO
WOT
ROT
PIN
BPI
WIN
RIN
RESET PROGRAM-CONTROLLED TRAP (RCT)
TEST PROGRAM-CONTROLLED TRAP (TCT)
!: I~ I: !
HI
Multiply and Divide
When the high-speed multiply/divide option is not prese~t in a
system, an attempt to execute the associated instruction code
causes a transfer to a special trap location. These locations
are:
Location
Mnemonic
Opcode
2 3 4 5 6 7 8 9 10 11
o
where the 0 in bit 8 specifies that the pointing address consists
of a 15-bit address constructed as in Direct Addressing.
MUA
MUB
DVA
DVB
Example: Assume
32000
32001
14020
130
132
134
136
140
142
144
146
SET PROGRAM-CONTROLLED TRAP (SCT)
The second form of indirect addressing is:
Location
10
50
0004~B
Indirect Full Addressing
OP:Ode
Normal Mnemonic
One of the "branch and mark place" instructions BRM or BMC
placed in the trapping location (and location plus one) by the
programmer branches to the associated subroutine. The mark
information provides the subroutine I inkage back to the main
program, i. e., the address stored in the mark is the address of
the instruction that caused the trap. The program sets, resets,
and tests the PCT bit via the instruction:
yields reinitialized addressing on locations 34, 35.
(20010)
Trapping Location
51
14
54
15
55
*034
34
35
Opcode
11
Conte~ts
0002
0010
0004
Location
34
35
20010
Then,
LDB
2
(32000) = 0001
(32001) = 4020
Opcode
2 13
!
This yields:
In this mode, the instruction bits have the form:
o
*032000 which is
Contents
0001
4020
2200
13
53
52
12
124
126
122
120
When the option is absent, the trapping process is always active and cannot be inhibited by the programmer.
1-6
Appendix-B-5 contains a complete trap-subroutine example.
that is useful as a guide to writing subroutine return code.
Trapp i ng Notes
When a trap occurs, the P counter is not incremented. It is
therefore mandatory that only branch instructions be placed in
the trap instructions; otherwise, the program goes into an unrecoverable loop:
Nomenclature
Assume there is no multiply option.
124 L~A
Throughout the following discussions, the term "next locati~n"
refers to the location immediately following the location of the
instruction under discussion. The simi lar term "next address"
is also used.
1000
1200 MUA 5000
If MUA is executed, the execution sequence is:
1200 MUA
124 LDA
1200 MUA
124 LDA
The term "effective memory location" describ~s the location in
memory from which the computer takes the final operand at the
conclusion of all indirect addressing and indexing. The effective memory location is the location whose address is the effective address.
1-7
II. MACHINE INSTRUCTIONS
STORE A (STORE B)
STA (STB)
This section describes SDS 92 instructions; they are presented
in functional groups. Lists of instructions in functional, numerical and alphabetical order are in Appendices B-7 through
B-17.
44(04)
a
The following statements apply to the instruction descriptions.
Y
I
5 6
789
11
STA stores the contents of the A Register in the effective memory location.
All instruction times are in memory cycles, where
each cycle is 1.75 microseconds.
Timing: 2
Registers Affected: M
All timings assume that the instruction addresses operands in scratch-pad memory (even though the instruction may, in fact, preclude this mode of addressing).
For more comprehensive addressing, add cycles to the
given execution times as follows:
Addressing
74(34)
a
Cycles
a
Immediate
EXCHANGE M AND A (EXCHANGE M AND B)
XMA (XMB)
I
56789
11
XMA loads the contents of the effective memory location into
the A Register and stores the contents of the A Register in the
effective memory location.
Direct Full
Direct Full with Indexing
Registers Affected: A(B), M
Indirect Addressing One-Word,
even scratch-pad address
P
Indirect Addressing Two-Word,
Fu II add ress
1+ P
Timing: 3
FLAG INSTRUCTIONS
XMF
where P is the number of cyc les required to process
the indirect address pair.
EXCHANGE M AND FLAG
17
I
a
Parentheses denote IIcontents of ", as, for example,
(A) represents the contents of the A Register.
56789
11
a
a
XMF loads the content of the Flag Bit into bit of the effective
memory location and loads the content of bit into the Flag
Bit; it leaves bit positions 1 through 11 of the effective memory
location the same as they were.
The interrupt system (optional) can interrupt the program sequence at the end of any instruction except as
noted.
Registers Affected: F, M
Those instructions that apply to the A and the B Registers appear with the B Register operation code and
mnemonic in parentheses.
LDF
With each instruction description is a diagram depicting the instruction format. Preceding this diagram is the mnemonic code
and the instruction name. In the diagram, S stands for Scratch
Pad Bit, I stands for Indirect Address Bit, X stands for Index Bit,
and Y stands for part of the address. The letter M depicts a general memory location.
Timing: 3
LOAD FLAG
57
I
a
5
6
LDF loads the content of bit
into the Flag Bit.
7
8
9
11.
a of the effective memory
Registers Affected: F
location
Timing: 3
LOAD /STORE INSTRUCTIONS
SFT
LDA (LDB)
SET FLAG TRUE
LOAD A (LOAD B)
00
64(24)
a
I
a
56789
11
I
44
5
6
I
11
SFT unconditionally sets the Flag Bit to a one.
LDA loads the contents of the effective memory location into
the A Register.
SFT cannot be interrupted.
Registers Affected: A(B)
Registers Affected: F
Timing: 2
2-1
Timing: 3,4
SFF
SUA (SUB)
SET FLAG FALSE
42
I
00
o
I
5 6
60(20)
o
11
SFF unconditionally resets the Flag Bit to a zero.
Timing: 3,4
Registers Affected: F
00
46
I
I
5
6
8
9
11
Timing: 2
Example: Assume
(A) = 3003
(10) =·4010
(F) = 0
11
INF unconditionally inverts the Flag Bit.
it to a Oi if it is a 0, INF sets it to a 1.
If it is a 1, INF sets
Performing SUB 010
(A) = 6773
(F) = 1
INF cannot be interrupted.
Timing: 3,4
Registers Affected: F
ADD TO A (ADD TO B)
o
yields
SUBTRACT WITH CARRY TO A (SUBTRACT WITH
CARRY TO B)
SCA (SCB)
ARITHMETIC INSTRUCTIONS
ADA (ADB)
7
Registers Affected: A(B), F
INVERT FLAG
o
5 6
SUA subtracts the contents of the effective memory location
from the contents of A and places the result in Ai it stores the
carry from bit 0 in the Flag (F) bit. [(M) > (A) sets Fi (A) ~ (M)
resets F.J
SFF cannot be interrupted
INF
SUBTRACT TO A (SUBTRACT TO B)
61(21)
I
5
6
7
8 9
]]
62(22)
o
I
5
6
7
8
9
SCA subtracts the content of the effective memory location from
the contents of the A Register, then subtracts the content of F from
the least significant end of the difference and places the result in
A. It places the carry from bit 0 in the Flag (F) bit. [(M) +F >(A)
sets Fi (A)~(M)+FresetsF.]
11
ADA adds the contents of the effective memory location to the
contents of A and stores the result in Ai it stores the carry from
bit 0 of the addition in the Flag Bit.
Timing:
Registers Affected: A(B), F
MPA (MPB)
Example: Assume
(A) = 4300
(1000)
3700
(F) = 0 , Flag Bit
Performing ADA 01000
(A) = 0200
(F)
ACA (ACB)
=
o
yields
ADD WITH CARRY TO A (ADD WITH CARRY
TO B)
76(36)
I
6
7
8
9
11
o
ACA adds the contents of the effective memory location to the
contents of Ai it also adds the content of the Flag Bit to bit
position 11 of the result. ACA places the final result in Aand
records the carry from bit 0 in the Flag Bit.
Registers Affected: A(B), F
5 6
7
8 9
11
Timing: 3
Registers Affected: M, F
MPO
5
MEMORY PLUS A TO MEMORY (MEMORY PLUS
B TO MEMORY)
MPA adds the contents of the effective memory location to the
contents of A and places the result in the effective memory location; it stores the carry from bit 0 in the Flag Bit.
1
63(23)
o
2
Timing: 2
Registers Affected: A(B), F
MEMORY PLUS ONE TO MEMORY
16
I
56789
11
MPO increments the contents of the effective memory location
by one and places the result back into the same location; it
places the carry bit from bit 0 in the Flag Bit.
Timing: 2
Registers Affected: M, F
2-2
Timing: 3
o
Exampl e: Assume
(A) = 0027
(B) = 4335
(1000) = 0036
MEMORY PLUS FLAG TO MEMORY
MPF
234
5
6
7
8
9
10 11
PerformingDVA01000
(B) = 6217
(A) = 0033
MPF adds the content of the Flag Bit to the contents of the
effective memory location at bit position 11 and places the
result back into the effective location. The carry from bit
o of the addition goes into the Flag Bit.
MULTIPLY A
The div is ion is performed as follows:
B
Registers Affected: M, F
MUA
(Optional)
Y
13
I
/
6
7
8
J
I 0 10 13 16 1 I0 I0 1217 H
A
*
151
B
LOGICAL INSTRUCTIONS
11
MUA multiplies the contents of A by the contents of the effective memory location and places the product in A and B with
the more significant portion in A.
5
A
Timing: 3
1000
o
yields
9
ANA (ANB) AND TO A (AND TO B)
65(25)
Timing:
Registers Affected:. A, B
5
o
Performing MUA 01000
(A) = 0077
(B) = 2420
MULTIPLY B
6
7 8
9
11
Registers Affected: A, (B)
yields
ORA (ORB)
(Optional)
53
Timing: 2
OR TO A (OR TO B)
67(27)
I
o
5
ANA performs a logical AND with the contents of the A Register and the contents of the effective memory location; it
places the result in A. The previous contents of A are lost.
Example: Assume
(A) = 3411
(1000) = 0220
MUB
I
56789
o
11
MUB multiplies the contents of B by the contents of the effective memory location and places the product in A and B with
the more significant portion in A.
Registers Affected: A, B
I
5
6
7 8
9
11
ORA performs a logical "inclusive OR II with the contents of
the A Register and the contents of the effective memory location; it places the result in A. The previous contents of A are
lost.
Timing: 5
Registers Affected: A, (B)
Timing: 2
DIVIDE AB (DIVIDE BA) (Optional)
DVA(DVB)
52(12)
o
I
EOA (EO B)
5
6
7
8
9
DVA(DVB) divides the contents of the A and B Registers (B and
A Registers) I treated as a double-precision number I by the
contents of the effective memory location and places the quotient in the B Register I with the remainder in the A Register.
The A Register (B Register) must initially contain the more
significant half of the dividend. The contents of the effective
memory location must be greater than the contents of A (B).
Registers Affected: A, B
EXCLUSIVE OR TO A (EXCLUSIVE OR TO B)
11
66(26)
o
I
56789
11
EOA performs a logical "exclusive OR II with the contents of
the A Register and the contents of the effective memory location; it places the result in A. The previous contents of A are
lost.
Timing: 13
Registers Affected: A, (B)
2-3
Timing: 2
MAA(MAB)
BRANCH INSTRUCTIONS
MEMORY AND A TO MEMORY (MEMORY AND
B TO MEMORY)
BRU
t
o
BRANCH UNCONDITIONALLY
Y
75(35)
5
6
7 8
9
73
11
o
MAA performs a logical AND with the contents of the A Register and the contents of the effective memory location; it
places the result in the effective memory location. The previous contents of the memory location are lost; MAA leaves the
contents of A undisturbed.
Registers Affected: M
I
5
6
7 8
9
11
The computer takes the next instruction from the location determined by the effective address. BRU cannot be interrupted.
Registers Affected: None
Timing:
1
Timing: 3
BRC
BRANCH, CLEAR INTERRUPT AND'LOAD FLAG
COMPARISON INSTRUCTIONS
COA(COB)
32
COMPARE ONES WITH A (COMPARE ONES
WITH B)
o
I
56789
11
COA compares the contents of the A Register,
the contents of the effective memory location.
of A and the contents of the effective location
in corresponding bit positions, COA resets the
there is no such corresponding pair of one bits,
Flag Bit.
Registers Affected: F
5
6
7
8
11
9
The computer takes the next instruction from the location determined by the effective address; it also clears the currently
active interrupt level. If BRC uses direct addressing, it clears
the Flag Bit and sets the PCT bit. If it uses indirect addressing,
BRC places into the Flag Bit and PCT bit the content of bits 0
and 1 of the first word of the last indirect address pair.
45(05)
o
I
bit by bit, with
If the contents
have any ones
Flag Bit. If
COA sets the
Registers' Affected: F, PCT
BRL
Timing: 3
BRANCH AND LOAD FLAG
Timing: 2
33
'CMA(CMB)
o
COMPARE MAGNITUDE OF M WITH A
(COMPARE MAGNITUDE OF M WITH B)
47(07)
I
5
6
7 8
9
o
If the contents of the A Register are arithmetically less than the
contents of the effective memory location, CMA resets the Flag
Bit. Otherwise, it sets the Flag Bit.
CEA(CEB)
56789
11
BRL transfers to the effective memory location. If BRL uses
direct addressing, it clears the Flag Bit and sets the PCT bit.
If it uses indirect addressing, BRL places into the Flag Bit and
the PCT bit the content of bits 0 and 1 of the first word of the
last indirect address pair. BRL cannot be interrupted.
11
Registers Affected: F
I
Registers Affected: F, PCT
Timing: 2
BRANCH ON FLAG FALSE
BFF
COMPARE M EQUAL TO A (COMPARE M
EQUAL TO B)
Timing:
31
o
I
5
6
7
8 9
11
46(06)
o
I
56789
If the content of the Flag Bit is zero, the computer takes the
next instruction from the location determined by the effective
address. If the content is one, the ~omputer executes the next
instruction in sequence. If a branch occurs, there can be no
interrupt.
11
If the contents of the A Register are equa I to the contents of
the effective memory location, CEA resets the Flag Bit. Otherwise, it sets the Flag Bit.
Registers Affected:
Registers Affected: F
Timing: 2
2-4
None
Timing:
1 if Branch
2 if No Branch
BFT
o
BRANCH ON FLAG TRUE
BMC
71
37
I
I
5
6
7
8
9
o
11
If the content of the Flag Bit is one, the computer takes the next
instruction from the location determined by the effective address.
If the content is zero, the computer executes the next instruction
in sequence. If a branch occurs, there can be no interrupt.
Timing:
Registers Affected: None
BOA
1 if Branch
2 if No Branch
BRANCH ON DECREMENTING A
56789
11
Registers Affected: A
Timing:
6
7
8
9
11
M, M + 1, F, PCT
Timing: 3
The single or double shift is determined via bit 7 of the effective address; it is a 0 for single-register shift and a 1 for doubleregister shift.
10 11
BAX exchanges the contents of A with the contents of B; then
it branches to the location determined by the effective memory
address. BAX cannot be interrupted. If this instruction specifies indexing, the indexing wi II be performed before the interchange of IIA II and liB. II
The conventional address formats are:
One-Word Address
Timing: 1
Registers Affected: A, B
BRM
8 9
Shift instructions operate on. the A, B, and Flag Registers. The
shifts can be single or double register. All sh ifts are to the
left. The number of shifts N is specified in the least significant 4 bits of the effective address. The maximum number of
shifts is 15 (178); zero is allowed. N is written in the 4 bits,
in onels complement form (i .e., a shift N =7 appears as 10 ),
8
1 if Branch
2 if No Branch
30
5
7
SHIFT INSTRUCTIONS
BRANCH AND EXCHANGE A AND B
2 I 3 4
6
Note that the BMC instruction is the one normally executed
when an interrupt occurs. The add ress stored in th i s case is
the location of the next instruction to be executed in the main
program.
BOA decrements the contents of the A Register by one. It then
tests the result unequal to 77778 , If unequal, the computer
takes the next instruction from the location determined by the
effective address. If equa I, the computer executes the next
instruction in sequence. t If a branch occurs, there can be no
interrupt. If this instruction specifies indexing, the indexing
is performed before A (the index register) is decremented.
o
5
Registers Affected:
I
BAX
y
BMC stores the contents ofthe Program Counter in bits 9 through 11
of the effective memory location and bits 0 through 11 of the effec ..
tive location plus one. It stores the contents of the Flag Bit in bit 0
and the contents of the PCT bit in bi t 1 of the effective location;
bits 2 through 5 of the effective location are unpredictable. Bits 6
through 8 of the effective location are cleared. The Flag Bit is
cleared and the PCTbit isset. BMCthen branches to the effective
memory location plus two. Immediate addressing is not allowed.
70
o
BRANCH, MARK PLACE, AND CLEAR FLAG
BRANCH AND MARK PLACE
11
77
o
I
5
6
7
8
9
Two-Word Address
11
BRM stores the contents of the Program Counter (which contains
the address of the next instruction in sequence) in bits 9 through
11 of the effective memory location and bitsO through 11 of the effective location plusone. It stores the content of the Flag Bit in bit 0 and
the content of the PCT bit in bit 1 of the effective location; bits 2
through 5 of the effective location are unpredictable. Bits 6 through
8 of the effective location are cleared. BRM then branches to the
effective memory location plus two. Immediate addressing is not
allowed.
Registers Affected: M, M+ 1
Timing: 3
tAs with any instruction, when using immediate addressing with
a BOA, the phrase lithe next instruction in sequence II refers to
the instruction two locations beyond the BOA.
2-5
Opcode
0=1 lis Complef
o
11
Shift Timing
Shift Count (Decimal)
Timing (Cycles)
0-3
3
4-6
4
7-9
5
10 - 12
6
13 - 15
7
CYA(CYB)
CFI
CYCLE A (CYCLE B)
CYCLE FLAG AND DOUBLE INVERSE
o3
42 (02)
o
56
7
8
9
o
11
CYA shifts the contents of the A Register N places to the left.
All bits shifting past position 0 shift into position 11. The
one's complement of N, the number of positions to be shifted,
is placed in the least significant 4 bits of the effective address.
7
A(B)
CYCLE FLAG AND A (CYCLE FLAG AND B)
11
r0j_B---,H,--_A-----h
CONTROL INSTRUCTIONS
EXU
43 (03)
o
9
o
Registers Affected: A, B,F
CFA(CFB)
8
CFI shifts the contents of the B and A Registers and the F lag Bit,
taken as a single 25-bit register, N places to the left. Bits
shift from position 0 of A into position 11 of B, from position
of B into the Flag Bit, and from the Flag Bit into position 11
of A. The one's complement of N is placed in the least significant 4 bits of the effective address.
d b
Registers Affected: A(B)
5 6
EXECUTE
11
72
CFA shifts the contents of the A Registerand the Flag Bit, taken
as a single 13-bit register, N places to the left. All bits shifting past position 0 shift into the Flag Bit, bits from the Flag Bit
go into position 11. The one's complement of N is placed in
the least significant 4 bits of the effective address.
rEH
Registers Affected: A(B), F
CYD
I
A(B)
02 or 42
I I[I I
5
56
X
7
8
9
b
I
y
HLT
CYD shifts the contents of the A and B Registers N places to the
left. All bits shifting out of position 0 of A shift into position
11 of B; all bits shifting out of position 0 of B shift into position 11 of A. The one's complement of N is placed in the least
significant 4 bits of the effective address.
Registers Affected: A, B
CFD
8
9
11
Timing:
HALT
1 + time of
instruction
execution
41
00
I
o
_B_h
H. . . .
o
4 3
5
11
6
o
o
o
o
2
3
5
6
8
9
11
HLT halts instruction execution and lights the HALT light. To
resume computation, the operator sets the mode switch to IDLE
and then to RUN or STEP at which time the computer executes
the instruction in the location addressed by the contents of the
Program Counter. (This wi II be the instruction following the
ti LT instruction if the operator has not changed the contents of
the Program Counter. )
11
CFD shifts the contents of the A and B Registers and the Flag
Bit, taken as a single 25-bit register, N places to the left.
Bits shift from position 0 of B into position 11 of A, from position 0 of A into the Flag Bit, and from the Flag Bit into position 11 of B. The one's complement of N is placed in the least
significant 4 bits of the effective address.
Registers Affected: A, B, F
7
One Word
CYCLE FLAG AND DOUBLE
o
6
Registers Affected: None
11
A
·5
EXU executes the instruction in the effective memory location.
Then the computer executes the next instruction following EXU. If
the effective memory location contains a branch, control goes
to the branch-to location. If the effective location contains
another EXU, the process repeats with control always returning
to the next location after the first EXU or to the branch-to 10-'
cation if the last instruction is a branch instruction. Immediate
addressing is not allowed on EXU (this restriction does not apply to the instruction executed}. No "trappable" instruction that
wi II trap can be executed.
CYCliDOUBli
o
I
o
If an interrupt occurs while halted by a HALT (while still in
RUN), the computer acknowledges the interrupt and computation resumes. (The instruction following the HLT instruction
will be executed following the processing of the interrupt.)
r0j,---A---,H,--_B-b
Registers Affected: None
2-6
Timing: 3,4
TRAPPING INSTRUCTIONS
SCT
TEST PROGRAM-CONTROLLED TRAP
TCT
SET PROGRAM-CONTROLLED TRAP
00
61
I
I
o
01
60
I
I
11
SCT unconditionally sets the PCT bit to a one.
TCT tests the status of the PCT bit. If PCT is a one, it sets the
Flag Bit to a one. If PCT is a zero, it sets the Flag Bit to a
zero.
SCT cannot be interrupted.
Registers Affected:
o
5
Registers Affected:
RCT
11
PCT
Timing: 3,4
I
)6
60
I
Mnemonic
11
Coding
BPT 1
BPT2
BPT 3
BPT 4
RCT cannot be interrupted.
PCT
Timing: 3,4
This instruction tests the status of the Breakpoint switches. If
the selected switch is set, the Flag Bit is set to a 1. If the
switch is reset, the Flag is set toa O.
RCT unconditionally sets the PCT bit to a zero.
Registers Affected:
F
BREAKPOINT TESTS
RESET PROGRAM-CONTROLLED TRAP
00
o
6
Timing: 3,4
Regi sters Affected:
2-7
0144
0145
0146
0147
F
Timing: 3,4
III. INPUT/OUTPUT INSTRUCTIONS
INTRODUCTION
Central
Processor
The SDS 92 has a comprehensive input/output system to complement its high internal processing speed. This system can transmit data in word, character, and single-bit form to and from
the computer at the speed of internal computation. The input/
output system is of great variety and can assume control of
conditions imposed by a wide range of input/output j special
system devices; but the computer always leaves a high degree
of flexible input/output control to the programmer.
Memory
The system contains:
Buffered input/output of data words, under program con.trol in blocks or as single words.
Input/output of blocks of data via subchannels; up to 64
channels simultaneously operating through a multiplexing system (optional).
WOT causes a word to be taken from the specified memory location and placed in the I/O Channel to be output when requested by the currently active peripheral device.
Direct parallel input/output of 12-bit words, singly or
in blocks, to and from external statiC registers.
·Single bit input/output, such as equipment on/off status,
sense switches, and pulsing and sending of special signals.
Central
Processor
Memory
I/O CHANNEl
The I/O Channel, standard equipment in the computer, performs input/output of words singly or in blocks. On output,
the I/O channel transmits words in 6-bit characters, one or
two characters per word as selected, or in 12-bit (optional)
single character form. On input, the I/O channel receives
words in 6-bit characters, one or two per word, or 12-bit
(optional) characters as desired. This channel transmits single
words or blocks. The program places the block count in the A
Register prior to the transfer and the computer counts this down
to 7777 automatically to terminate the transfer operation.
To transfer blocks of data words via the I/O channel, the
program uses the same EOM configuration to set the channel
for operation; the program specifies the number of words in the
transfer.by placing the word count minus one in the A Register
((A) + 1 = N). The RECORD OUT (ROT) instruction causes
the computer to output words from the effective address M
through the effective address plus the contents of A (M through
M + (A)). The RECORD IN (RIN) instruction causes the computer to input from the actively transmitting peripheral device;
the operation terminates when the computer receives N words,
or when it receives an "end-of-record" from the peripheral
device •. RIN and ROT tie up the computer during the entire
input/output transmission.
SINGLE WORD TRANSMISSION
Using the I/O Channel, a progrdm can transmit data words between memory and peripheral devices under single instruction
control. To do this, the program first activates the channel and
the peripheral device with an energize or "alert" instruction
(one of the configurations of the multi -purpose instruction,
ENERGIZE OUTPUT M (EOM)). WOT is the WORD OUT instruction; WIN is the WORD IN instructi.on. WIN causes a
word from a peripheral device to be taken from the I/O channel and placed directly into the specified memory location
witho.ut disturbing any internal registers ..
3-1
Central
Processor
For a PIN, EOM alerts the sending device, PIN stores the least
significant 12 bits, the high-order bits fill the extender, EOM
a Ierts the extender, and another PIN stores the contents of the
extender. Ne i ther of these cod i ng sequences can be interrupted.
See the Interrupt System paragraphs for the Alert Extender EOM
for both POT and PIN.
Memory
o
SINGLE BIT INPUT/OUTPUT
N-1
The EOM and SES instruction provide a general single bit
transmitting and sensing facility for use as test and control
signals with special systems and standard peripheral devices.
(A) = N-1
DATA TRANSFER INSTRUCTIONS
No interrupt can occur between any of these instructions and
the instruction following it.
Figure 3-1. ROT/RIN Data Transmission
WOT
Two instructions control the process of transmitting and receiving data-between peripheral equipment and the central proces\ sor using the I/O Channel. These instructions are:
EOM
ENERGIZE OUTPUT M
S-ES
SENSE EXTERNAL SIGNAL
WORD OUT
o
5
6
7
8
9
11
WOT transfers the contents of the effective memory location
into the I/O channel buffer. If the buffer is not ready, the
central processor IIhangs Upll unti I the buffer empties from a
previous instruction and is ready to accept the new data word.
The EOM instructi on activates the I/O Channel, selects the
peripheral device, and requests the desired operation. The programmer uses the SES instruction to test for all input/outputoperational conditions; SES is multipurpose like the EOM. Later
sections describe the exact configurations of EOM and SES.
Timi ng: 4 + wait
Registers Affected: None
ROT
RECORD OUT
DIRECT PARALLEL INPUT/OUTPUT, 12 BIT
The parallel input/output facility allows full, 12-bit words to
be transmitted directly out of and into the memory. After activating the peripheral device or special system device with an
activating EOM, the PARALLEL OUTPUT (POT) and PARALLEL
INPUT (PIN) cause any selected word in core memory to be
presented to the peripheral device connector; or conversely,
cause a word (12-bit signa I) received into the device connector
to be stored in the selected location. POT/PIN also check or
generate correct memory parity with each word transmitted.
The system provides a block transfer form of POT and PIN with
the instructions, BLOCK PARALLEL IN (BPI) and BLOCK PARALLEL OUT (BPO). By placing the word count N minus one in
the A Register, BPI and BPO provide the identical function of
PIN and POT, respectively, on N consecutive words.
o
51
I
5
6
7
8
9
11
Starting with the effective memory location, ROT transfers N
sequential words into the I/O channel buffer. The contents of
the A Register are the word count N minlfs one; ROT can output to 4096 words per execution. The central processor must
wait as with WOT before it transfers the first word to the buffer;
it also must wait for the buffer to clear between each word
transfer. ROT completely ties up the computer until the Nth
word transfers into the channel buffer. The next instruction
executes before the Nth word transfers out of the channel buffer to the connected peripheral device.
Timing: 2 + 2N + wait
Registers Affected: A
Parity checking/generating is automatic for these operations on
machines equipped with the memory parity feature.
WORD IN
WIN
See POT/BPO, PIN/BPI Instructions in this section.
o
DIRECT PARALLEL INPUT/OUTPUT, 24-BIT (Optional)
15
I
5
6
7
8
9
11
WIN transfers the contents of the channel buffer into the effective memory location. If the buffer is not already fi lied, the
central processor IIhangs Upll unti I the buffer fi lis with the
word being received from the peripheral device.
A 12-bit register is available to extend the word for POT/PIN
operations to 24 bits. For a POT, the device operates as follows: EOM to activate the extender, POT to place the most
significant 12 bits in the extender, EOM to activate the externa I device to get the data, and POT to transmit the lower
-12 bits. This last POT transmits the entire 24 bits.
Registers Affected: M
3-2
Timing: 5 + wait
RIN
RIN. To place data into the channel buffer so that the channel can
transmit it to the waiting peripheral device, the program uses
WORD OUT (WOT), or its block transfer equivalent, ROT.
RECORD IN
55
o
I
5
6
7
8
9
I/O CHANNEL BUFFER DESCRIPTION (See Figure 3-2.)
11
During the execution of ROT/RIN, the computer is completely
tied up whi Ie it handles the data transfers, increments the memory location address for the data transfers, and tests for transfer termination using the word count N (by decrementing A
by one whenever a word is transferred).
Starting with the effective memory location, RIN transfers N
words from the channel buffer into sequential locations. The contents of the A Registerare the word count N minus one; RIN can input up to 4096 words per execution. The centra I processor
must wait as with WIN before it receives the first word from
the channel buffer; it also must wait for the buffer to fill between each word transfer. RIN completely ties up the computer until the Nth word is in memory. This input will also terminate if the computer receives an END signal from the peripheral device before the Nth word. In either case, the computer
executes the next instruction after RIN terminates.
Registers Affected: M to M + (A), A
I/o
Each of the 30 devices which can be attached to a buffer has a
unique, two-digit, octal address by which it is chosen for an
input/output operation. To choose the peripheral device, the
program loads the proper unit address into the 6-bit Un it Address
Register (UAR). This address selects both thedeviceand, if appropriate, the function to be performed. Placing a non-zero unit
address in the Unit Address Register "connects" the peripheral
unit addressed to the buffer and the buffer becomes "active tl •
When the UAR contains a zero address, or any time that a terminal or initial condition clears the contents of UAR, the buffer is "inactive", and it is not connected to a peripheral unit.
Timing: 3 + 2N + wait
CHANNEL OPERATION
The Word Assembly Register (WAR) and the Single Character
Register (SCR) comprise the active portion of a buffer. The
Word Assembly Register, a 12-bit, word~sized buffer, contains
the word of data actively being received or transmitted during
an input or output operation. During input, 6-bit characters
(plus parity) come into the Single Character Register where the
channel assembles them, one at a time, into the WAR. Depending on the number of characters per word specified, the
word assembled during input has the form:
The I/O Channel can control up to 30 input/output devices;
it automatically handles character, word assembly/disassembly,
and input/output parity detection and generation.
The channel is bi-directional and communicates with 6-bit
character devices (12-bit optional). The program specifies
whether one or two characters are to be assembled/disassembled
in each word during the transmission.
The program uses a Buffer Control EOM to set the operation
controls such as forward/backward tape direction, to place
the unit address in the channel, and to initiate the proper
assembly/disassembly mode. The presence of the unit address
activates the channel causing it to look for data coming from a
peripheral device or from memory, as determined by the unit
address (see the Unit Address Code, Table 3-1).
Word
1st
I
o
To get data from the channel buffer after it is received there
from a peripheral device during input, the program uses a
WORD IN (WIN) instruction, or its block transfer equivalent,
o
~~~~~J
I
I
I
I
J6
2nd
I
~ o
I
I
Parity
Error
Character Count
E1
Word
Assembly '--_ _ _ _~_ _ _ _~
11
5 6
o
L _____ _
-0-
I
One character
per word
11
Two characters
per word
11
----------,
I
r- - - - - - - - - - - - - - - - - - - - - - - - - - - - To I/O Device
:
I
Unpredictable
5 6
1st
I
Mode
o
•
I
I
I
5
I
I
I
_J
Figure 3-2.
SDS 92 Channel Buffer
3-3
I
Table 3-l. Unit Address Codes
00
Disconnect
40
01
Type Input No. 1
41
Type Output No. 1
02
Type Input No.2
42
Type Output No.2
03
Type Input No.3
43
Type Output No.3
04
Paper Tape Input No.
44
Paper Tape Punch Output No.
05
Paper Tape Input No.2
45
Paper Tape Punch Output No.2
06
Card Reader Input No. 1
46
Card Punch Output No. 1
07
Card Reader Input No.2
47
Card Punch Output No.2
10
Magnetic Tape Input No. 0
50
Magnetic Tape Output No. 0
11
Magnetic Tape Input No.1
51
Magnetic Tape Output No.1
12
Magnetic Tape Input No.2
52
Magnetic Tape Output No.2
13
Magnetic Tape Input No.3
53
Magnetic Tape Output No.3
14
Magnetic Tape Input No.4
54
Magnetic Tape Output No.4
15
Magnetic Tape Input No.5
55
Magnetic Tape Output No.5
16
Magnetic Tape Input No.6
56
Magnetic Tape Output No.6
17
Magnetic Tape Input No.7
57
Magnetic Tape Output No.7
20
60
High-Speed Printer Output No.
21
61
High-Speed Printer Output No.2
22
62
23
63
24
64
Incremental Plotter Output No.
25
65
Incremental Plotter Output No.2
26
Disc File Input No.
66
Disc File Output No. 1
27
Disc File Input No.2
67
Disc File Output No.2
30
Scan Magnetic Tape No. 0
70
Magnetic Tape Erase No. 0
31
Scan Magnetic Tape No.1
71
Magnetic Tape Erase No.1
32
Scan Magnetic Tape No.2
72
Magnetic Tape Erase No.2
33
Scan Magnetic Tape No.3
73
Magnetic Tape Erase No.3
34
Scan Magnetic Tape No.4
74
Magnetic Tape Erase No.4
35
Scan Magnetic Tape No._5
75
Magnetic Tape Erase No.5
36
Scan Magnetic Tape No.6
76
Magnetic Tape Erase No.6
37
Scan Magnetic Tape No.7
77
Magnetic Tape Erase No.7
3-4
An unfi lied character position is unpredictable. When assembled during a single-word operation, a WIN instruction places
the word into memory. With RIN, the computer places each
word in memory when assembled.
The Buffer Control EOM operates essentially as a setup or
preparation facility for data transmissions or other peripheral
functions using the I/O Channel. The Input/Output Control EOM directs peripheral devices directly in such operations as rewind tape and upspace the printer. EOM in the
Internal Control mode performs internal control operations
such as activating the (optional) 24-bit PIN/POT extender
logic. The System EOM is specifically concerned with special systems; the system determines the particular uses. EOM
in any of the last three modes also can alert a device for
a POT or PIN type operation.
During output, words come from memory into the WAR where
the channel disassembles them into the SCR, one 6-bit character at a time. Depending on the characters per word mode
specified, the channel transmits the 6-bit characters (with
generated parity) as follows:
Mode
Function
Output one character from bits
o through 5
One character per word
NOTE: If an interrupt occurs during the execution of an EOM,
no acknowledgement occurs until the completion of the execution of the instruction following the EOM.
Output two characters from bits
5, 6 through 11
Two characters per word
o through
Registers Affected: None
After the first character transfer, the word in the WAR shifts
left six bits to be ready for the next transfer, when two characters from each word are used. Under ROT control, a new
word contail")ing the next characterls) comes to the WAR when
it is required.
BUFFER CONTROL EOM (effective address)
U N I T
o
(OM INSTRUCTIONS
(opcode 00)
2
Designation
BASIC CONFIGURATION
The EOM instruction is a multipurpose instruction that operates
in four distinct modes with many functional configurations. The
modes are Buffer Control, Input/Output Control, Internal
Function Control, and System Control.
EOM
ENERGIZE OUTPUT M
4
5
6
7
8
9 10
11 1213 14
Function
Bit position 0 specifies Interlace operation.
A "0" specifies no Interlace operation. A "1"
alerts the Interlace.
00
Bit positions 1 and 2 contain the EOM mode
indicator for the Buffer Control mode.
F/R
Bit position 3 specifies the direction in which
the peripheral device operates. A "0" specifies
the forward direction. A "1" specifies the reverse direction.
L/N
Bit position 4 specifies whether the device
should be started with a leader as in paper
tape. A "0" specifies a start with leader. A
"1" specifies a start without leader.
D/B
Bit position 5 specifies the mode of character
format. A "0" specifies BCD format. A "1"
specifies Binary format. When this is not appropriate, ,bit 5 provides special control.
o
Bit position 6 is unassigned. '
C/W
Bit position 7 specifies the number of characters
to be assembled into, ordisassembled from, each
transmitted word. 0 specifies one character per
word, 1 specifies two. One character per word,
0, is used for full-word (12-bit characters)
transmission (optional).
o
o
5
234
6
8
7
9 10 11
Effective Address
Io !
3
I/N
Instruction Word
o
Timing: 3,4
\
2 3
4
5
I
6 7
I
8 9
10
11
12
13
14
The EOM uses the 15 bit configurations of the effective memory
address asa control word to select the different control modes
and toselectall additional control functions. EOM allows
a II addressing modes in obtaining the effective address.
Setting the two bits (1, 2) in the address determines the mode
of the EOM:
2
Control Mode
0
0
Buffer
0
1
Input/Output
0
Internal
Bit position 8 must always be 1.
UNIT
System
3-5
Bit positions 9 through 14 specify the unit and
the function to be performed with that unit.
INPUT/OUTPUT CONTROL EOM (effective address)
I
IIYNlo 1 FUN CT ION 11
01
2
345
'
6
I
Designation
I
UN IT
10
789
111
12
13
4.
14
Function
I/N
Bit 0 specifies Interlace operation. A "0" specifies no Interlace. A "I" alerts the Interlace.
01
Bits 1, 2 specify the Input/Output Control mode.
FUNCTION
a.
b.
ASC
Bits 3 through 7 specify control peculiar to
each device.
I/o
Channel itself.
DISCONNECT CHANNEL
o
4
7
10
13
Registers Affected: None
o
Registers Affected: None
SES INSTRUCTIONS (opcode
The SES is a multipurpose test instruction used for testing responses to the input/output channel and attached peripheral
devices as well as for testing internal and external indicators.
Timing: 3, 4
o
10
SES
13
Ii
14
o
During output when the last word of a block goes to the channel, TOP terminates output. After execution of TOP, the following occurs. When the channel del ivers the last character
to the peripheral device, the channel disconnects.
Registers Affected: None
o
o
10
13
14
Timing: 3, 4
7
8 19
10 111 12 13 14
2 I 3
4
5
IsII\x!
6
7
8
9
10
I
11
0
1
0
1
Test Mode
Buffer
Input/Output
Internal
System
When executed, an SES tests for a specified condition and sets
or resets the Flag Bit in response to the condition. The program determines the Flag Bit status via one of the branch-onflag instructions. SES allows all addressing modes in obtaining
the effective address.
After TIP isgiven during an input operation, the following occurs:
2.
3.
1
5 6
0
0
0
1
1
TIP or DSC should always terminate a channel input operation.
1.
4
1 1..
During input when the last (desired) word has been stored in
memory, TI P term i nates input.
Registers Affected: None
3
Like the EOM, the SES uses the bit configuration of the effective address to select the different tests and also operates in
four modes that are selected by address bits 1 and 2:
TERMINATE INPUT ON THE CHANNEL
o
i
0
Timing: 3, 4
o
2
Effective Address
TOP must always terminate a channel output operation.
TIP
SENSE EXTERNAL SIGNAL
Instruction Word
I
o
11'12
01)
BASIC CONFIGURA nON
TERMINATE OUTPUT ON THE CHANNEL
o
Timing: 3, 4
13 14
10
DSC disconnects the I/o Channel. This instruction unconditionally sets the UNIT Address Register to 00 regardless of
whether the channel is currently addressing a device. DSC
disconnects any device connected to the channel; it unconditionally makes the channel inactive and clears the error indicator.
TOP
14
NOTE: The above sequence must be consecutive; no other instruction should be interposed.
o
o
o
stores the current contents of the COUNT register into location M. See Interlace Option, this section.
These EOM effective address configurations have standard uses.
o
5
ASC
PIN
STANDARD EOM INSTRUCTIONS
DSC
o
ASC alerts the interlace option that the PIN to follow is a request for the contents of the current COUNT contents. The
sequence:
Bits 9 through 14 contain the Unit Address of
the specified device.
A Unit Address of 00 refers to the
ALERT TO STORE INTERLACE COUNT
o
Bit 8 must be l.
UNIT
Interlace operations store no more words.
Non-interlace operations give no more End-of-Word
(11) Interrupts.
The above "scanning-type" sequence continues until the
End-of-Record at which time:
a. The End-of-Record (12) Interrupt is sent (if armed).
b. The channel disconnects.
c. The channel becomes inactive.
The I/o channel receives any further characters from the
input device - as before.
All error checks are performed - as before.
However, the Word Assembly Register is never again
considered "full". This means:
The Buffer and Input/Output Test SESs are the complement
of the Buffer and Input/Output Control EOMs; they sense
3-6
the conditions of the I/o Channel and its connected peripheral devices.
the data address as needed, and counting the number of words
in the record. Usually, when the count goes through zero, the
operation is completed and the program can use the newly
entered data and/or can reset the Interlace for another independent, I/O transm ission .
INPUT/OUTPUT TEST SES (effective address)
IIYNI
0
1I
CO
ND
11
I
UNIT
The Interlace contains two registers: the 12-bit COU NT register to contain the record count and the 15-bit ADDRESS
reg ister to conta in the data address. When load ing the record
count (N), the program places N-l (one less than the record
count) in the COUNT register.
1
o 1 2 3 4 5 6 7 8 9 10 11'12 13 14
Function
Designation
Bit 0 specifies Interlace operation. A "0"
specifies no Interlace. A "1" alerts the
Interlace.
I/N
The program can use any I/O or Buffer Control EOM to "alert"
the Interlace for operation. A l-bit in bit pos it ions 0 and 8 of the
effective address generated by the EOM will alert the Interlace.
Bits 1 and 2 specify the Input/Output Test
mode.
01
The standard assembler form for alerting the Interlace is an
asterisk (*) in the first column of the address of the EOM that
activates the peripheral device in the I/O transmission. For
example, to alert the Interlace while activating the magnetic
tape unit number 1 to read tape decimal, one could write:
Bits 3 through 7 specify conditions to be
sensed.
COND
Bit 8 must be 1.
RTD *1, 2
Bits 9 through 14 contain the Unit Address
of the specified device.
UNIT
A special EOM to alert only the Interlace,
ALC
ALERT CHANNEL INTERLACE
STANDARD BUFFER SES INSTRUCTIONS (effective address)
has the address form 50100; no 11*.. is needed.
CAT
CHANNEL ACTIVE TEST; SET FLAG IF NOT ACTIVE
o
4
1
o
2 34
o
5 16
7
The PARALLEL OUTPUT (POT) instruction transmits the starting
address and record count to the Interlace. The three II POTs"
that are needed function as follows (RTD * 1, 2 is used as the
alerting EOM):
I
13 14
8'9
RTD
POT
POT
POT
If the channel is ready to accept a new input/output instruction,
CAT sets the Flag Bit. If the channel is active, CAT resets the
Flag Bit. (The channel wi II test active during an input operationeven after the peripheral has terminated its operation - until all
meaningful data words in the character buffer have been stored
in memory.)
*1,2
HIADDR
LOWADDR
NLESSONE
(NOTE: This sequence must be consecutive; no other instructions shou Id be interposed.)
Timing: 3,4
Registers Affected: F
where:
CET
CHANNEL ERROR TEST; SET FLAG IF ERROR
o
o
o
10 11112
o
The least significant bits of the contents of
location HIADDR form the high or most significant three bits of the starting address,
I
13 14
the contents of location LOWADDR form
the least significant 12 bits of the 15-bit
starting address, and
CET tests the error indicator in the I/O Channel for being set.
If set to no error, CET resets the Flag Bit. If set to error, CET
sets the F lag Bit.
Registers Affected: F
the contents of NLESSONE are the record
length minus one (N-1).
Timing: 3,4
INTERLACE
In each case, the POT transmits the information into the proper
Interlace register.
The I/O Channel interlace is an optional hardware device that
can control and perform input/output operations independent
of, and simu Itaneous with, central processor program execution.
In using the interlace, the program sets up a starting address for
data in or out, sets up a record length of the data to be read
or written, and starts the interlaced operation. The program
then continues computation while the interlace monitors the
I/O operation, accessing memory when necessary, incrementing
The termination of an interlace operation can be determined by
using a CAT, CHANNEL ACTIVE TEST; or the progress of an
operation may be monitored through the use of the ALERT TO
STORE INTERLACE COU NT.
ASC (10500) alerts the Interlace that a PIN is to follow to get
a record of the current COU NT contents.
3-7
Note:
The sequence:
ASC
PIN M
If 11 is armed, the Interlace does not terminate
the channel on COUNT passing zero; instead
an 11 interrupt is generated. This allows the
program to re-initiate the COU NT and starting
ADDRESS in the Interlace and continue performing the same I/o operation.
alerts the Interlace and IPINs" the current contents of the
COU NT register into location M. The contents of COU NT
are N-1 minus the number of words of the record already
transm itted .
I/O CHANNEL INTERRUPTS OPTION
The Channel always disconnects when the endof-record occurs with no regard to the interrupt arms.
Two interrupts 11 and 12 are directly associated with the I/O
channel. These are priority interrupts with 11 having priority
over 12.
Note: When armed by ARM X, an interrupt condition occuring
on 11 or 12 causes the interrupt level to go to the Waiting
state. If the Interrupt System is Enabled, the respective
interrupt will go to the Active state as its priority
perm its. If the Interrupt System is Disabled, the interrupt
stays in the Waiting state indefinitely.
When 11 is requested, it interrupts each time the I/O channel
buffer empties or fi lis; that is, when requested it occurs on
input each time the buffer collects a word, or it occurs on
output each time the buffer transmits a complete word.
When 12 is requested, it interrupts when an End-of-Record
occurs; that is, it interrupts only after a complete record is
input or output.
POT/BPO, PIN/BPI INSTRUCTIONS
Two instructions, PARALLEL OUTPUT (POT) and PARALLEL
INPUT (PIN), cause any word in core memory to be presented in
parallel at a connector; or, inversely, cause signals sent to a
connector to be stored in any core memory location. The execution of a POT or PIN instruction causes a signal to be sent
to the external device involved in the input/output operation.
During a PIN, this signal tells the device to send its data word
as soon as it is operational. Wehn a device becomes operational duringaREADorPIN operation, ittransmitsaReady signal to the central processor while at the same time presenting
its data word. The computer places the received data word
into a specified memory location without disturbing any arithmetic registers. The computer II hangs Up" during the execution
of PIN until it receives the Ready signal from the external device.
11 and 12 are always enabled (as described in the Interrupt
Paragraphs, Input/Output Section of this manual).
I
A special instruction, EOM 11XOO, arms/disarms these interrupts. The values of X are:
X
Function
Disarm 11 and 12
3
Arm 11, disarm 12
5
Arm 12, disarm 11
7
Arm 11 and 12
During the executionofa POT 'instruction, the central processor
transmits a signal to the external device alerting it to receive
a data word. When the device becomes operational, it transmits a Ready signal to the central processor which releases the
data word to the external device. The computer II hangs Up"
during the execution of POT until it receives the Ready signal
from the external device. The block transfers forms of these
instructions are BLOCK PARALLEL INPUT (BPI) and BLOCK
PARALLEL OUTPUT (BPO).
The instruction EOM 13XOO, as a terminate output EOM, can
be used effectively in conjunction with the arming feature. For
"instance, EOM 13500 terminates output, arms 12 and disarms
11. It functions like this: When the current output from the
I/O channel is finished and the Jlo buffer is free, the 12
interrupt occurs.
The standard assembler mnemonic and instruction form is:
ARM
During input, this means that the peripheral continues
to the end-of-record, but no more input words are
stored in memory.
X
Special system requirements demand that complete words of
control or data information be transferred between the central
processor and the special external devices. The PIN or POT
preceded by the activating EOM gives exactly this facil ity.
The EOM alerts the system device by specific address and the
PIN or POT transfers the requ i red word. That is, the EOM activates andalertsthespecialdevice and the PIN/POT transfers
12 bits to or from the effective memory location specified. To
avoid a posssible computer II hang ... up", the SES instruction can test
the Ready signal of the specia I device prior to the EOM and PIN/
POT. If the Ready signal from the external device sets one of
the priority interrupts (optional), parallel input/output operation
can occur as soon as the external device is able to transmit or
receive. Since the Ready signal initiating the interrupt persists through the POT or PIN execution, no IIhang-up ll occurs.
where X is as described above.
Interrupts Used with the Interlace Option
During Interlace operation, the basic interrupts function
according to the names they are given below:
11 is COU NT EQUAL 77778
12 is END OF RECORD
When requested, 11 occurs when COU NT goes through zero.
When requested, 12 occurs when an End-of-Record occurs.
On output or input:
If 11 is not armed, the Interlace terminates the
channel (i. e., effects a~ automatic TOP or TIP)
when the COU NT goes throug h zero.
No interrupt can occur during the execution of, or between any
of these instructions and the instruction following it.
3-8
POT
SYSTEM MODE EOM (effective address)
POT PARALLEL OUTPUT
o
o
4
I
Y
5 6
7
8
9
10
Registers Affected:
5
o
o
4
Y
5
6
7
8
9
o
11
10
PIN
Pin stores the contents of 12 input I ines in parallel in the
effective memory location.
Registers Affected: M
o
BLOCK PARALLEL INPUT
4
6
7
8
9
10 11
Starting with the effective memory location, BPI transfers N
words from the 12 input lines in parallel into sequential locations. The contents of the A Register are the word count N
minus one; BPI can input up to 4096 words per execution. The
input lines fill and empty under the control of the Ready signal
and BPI.
Registers Affected: M to M + (A), A
Timing: 3,4
3
J
3
10
13
14
There is a test to see whether the I/O channel is ready to
accept a new input/output instruction - the CHANNEL
ACTIVE TEST (CAT).
2.
Following the termination of an input operation by an Endof-Record, the channel remains active until all significant
data words have been stored by the program or interlace.
3.
Following the termination of a non-magnetic tape output
operation by TERMINATE OUTPUT (TOP), the channel
remains active unti I the last cha racter has been del ivered
to the peripheral device.
4.
Following the term ination of a magnetic tape output operation by TOP, the channel remains active unti I the magnetic
tape un it commences stopping. Th is is long after the last
character has been del ivered to the magnetic tape un it.
5.
The End-of-Record (12) Interrupt is never sent unti I the
I/O channel becomes inactive.
Y
5
None
1.
Timing: 5 + wait
(h igh-speed)
and 5,6 + wait
4
13 14
I/O TERMINATION PROGRAMMING NOTES
o
5
12
The SES System Test Format is identical to the System EOM
Format. Timing is 3,4 cycles.
Timing: 3 + N + wait
(high-speed)
and 2,3 + 2N + wait
PARALLEL INPUT
BPI
d
Execution of an SES (System Test Mode) causes an address to
be presented to the collection of special system devices. If
the addressed external device is supplying a set signal to the
central processor, the Flag Bit is set. If there is no signal,
the Flag Bit is reset.
Starting with the effective memory location, BPO transfers the
contents of N sequential locations in parallel to 12 output lines
of an external device. The contents of the A Register are the
word count N minus one; BPO can output up to 4096 words per
execution. The output lines fi II and empty under control of
BPO and the Ready signa I .
Registers Affected: A
10
SYSTEM MODE SES (effective address)
BLOCK PARALLEL OUTPUT
BPO
1678 1 9
Bit positions 3 through 14 contain the address field that specifies the special system destinations.
Timing: 4 +.wait
(h igh-speed)
and 4,5 + wait
None
I
Bit positions 0-2 contain the System Mode Indicator.
POT transm its the contents of the effective memory location in
parallel to 12 output lines of an external device.
Registers Affected:
3
012345
11
Thus, an input program (using End-of-Word, 11, Interrupts
for example) must take care to store every input character
presented to it by the I/O channel (in our example, every
11 Interrupt must result in a II WI Nil or "DSC" or "TIP"). If
not, the input devicewill proceed to End-of-Record and stop,
but no 12. Interrupt will ever be given and the channel will
never go inactive.
Timing: 4 + N + wait
(h igh-speed)
and 3,4+ 2N + wait
The programmer has several options after he has read as much
of a record desired:
"
SINGLE BIT INPUT/OUTPUT
Operating in the System mode, the two instructions, ENERGIZE
OUTPUT M (EOM) and SENSE EXTERNAL SIGNAL (SES), provide single-bit input/output transmissions.
Execution of an EOM (System Mode) causes a 1.15-microsecond
signal to be transmitted to one of a possible 4096 signal destinations. The system EOM format is:
3-9
1.
Disconnect (DSC) - but not if the peripheral device is a
magnetic tape.
2.
Do nothing - but only if no more words remain in the
record (i.e., the entire record has been read).
3.
Give TIP - the input peripheral device wi" continue to
End-of-Record with all normal error checks on the
remainder of the record.
4.
TERMINATE INPUT (TIP) and TERMINATE OUTPUT (TOP)
have the same octal configuration - the I/O channel differentiates TIP and TOP according to the type of operation
it is performing.
5.
The programmer can have no problem by giving a TIP when
the input device is concurrently sending an End-of-Record
signal or when the channel is already inactive.
6.
Additional interrupts obtained with SDS optional hardware are
located at interrupt levels numbered from 150a. In general,
these also have priority according to number. Note that interrupts 150 through 176 have priority over any System interrupt
(200 or more).
When an interrupt has occurred and its service subroutine has
been entered, an interrupt of higher priority can interrupt the
subroutine and gain program control for the servicing of its
more important operation. But an interrupt of lower priority
cannot interrupt an interrupt-processing subroutine of a higher
level. Thus, the priority interrupt system allows interrupts to
be arranged according to their importance and/or according to
their need for speedy servicing.
Improper programming (especially on input) can leave the
I/O channel in an active state.
THE 11 INTERRUPT
A non-interlace, non-character-interrupt I/O program should
disarm the 11 Interrupt. If this disarming is not effected, spurious 11 Interrupts may result:
1.
On output, the first Il Interrupt is generated immediately
following the activating EOM.
2.
During ROT/RIN (and WOTjWIN), Il Interrupts may be
generated -even though the I/O channel is being properlyattended to by the ROT/RIN command.
The above type of interrupt is called a normal priority interrupt
to differentiate it from another interrupt feature, the singleinstruction interrupt. This is a different kind of interrupt that
causes the execution of only one instruction before automaticallyclearing itself and returning to the program which it interrupted. If the executed instruction is a branch instruction
which branches (i.e., BRM or BMC), the interrupt is cleared
but control does not return to the interrupted routine. Th is
type of interrupt needs no branch instruction to clear it. For
example, by connecting an external clock source to the computer, the program can maintain a programmed real-time clock.
Each time the external pulse causes an interrupt, the program
executes the single instruction, MEMORY PLUS ONE TO
MEMORY, to add one to the selected memory word. The main
program examines this location whenever necessary to determine how many time increments have elapsed since the clock
was started. No new interrupt can occur between any singleinstruction interrupt and the return to the main program.
This disarming does not create many programming problems or
compatibility problems-the RESET button clears both I/O channel interrupt arms. Thus, only programs which use both the
interrupt and the non-interrupt modes of I/O programming need
take heed.
PRIORITY INTERRUPT SYSTEM (Optional)
INTRODUCTION
Any of the optional, system interrupts can be single- or normalinstruction interrupts in any combination desired.
As an option, the SDS 92 may contain a priority interrupt system. This system provides added program control of input/
output operations, aids in programming multiplexed operations,
and'allows immediate recognition of special external conditions.
PRIORITY INTERRUPT OPERATIONS
A normal priority interrupt level has three operational states:
Inactive, Wai ting, and Active.
When an interrupt is received, the internal logic examines the
interrupt signal and causes the computer to interrupt the
program sequence at the end of the execution cycle of the
current instruction. Without disturbing the Program Counter
Register, the computer transfers program control to one of
a selected set of memory locations. One of the branch and
mark place BRM or BMC instructions in this location saves
the contents of the Program Counter, Flag, and PCT. It
also transfers to the particular interrupt servicing routine
required. This enters the proper service routine since each
interrupt has a unique interrupt location. To exit from the
routine, a BRANCH AND CLEAR INTERRUPT (BRC) instruction using indirect addressing returns control to the next instruction in proper sequence in the main program; it also
clears the interrupt and restores the original contents of the
Flag and PCT.
In the inactive state, no interrupt signal has been received into
the level and none is currently being processed by its interrupt
servicing subroutine. No record is maintained if the interrupt
cannot go into the waiting state.
In the waiting state, an interrupt request signal has been received into the level, but is not being processed. This situation may be due to an interrupt of higher priority being
processed at this time. When the system is enabled and all
higher waiting interrupts have been processed, this level goes
to the active state.
In the active state, the interrupt has been acknowledged, meaning it has caused the main program to recognize its presence
and has transferred to its assigned interrupt location and/or
routine where it is being processed. When the interrupt processing is completed, execution of a BRANCH AND CLEAR
(BRC) sets the interrupt level to the inactive state.
The priority interrupt system has up to 256 System interrupt
levels. The levels, numbered evenly upward from 200a, have
priority according to number, with the higher priority levels
having a smaller number.
A single-instruction interrupt operates in the same way as the
normal priority interrupt in the inactive and waiting states.
However, when acknowledged, this interrupt enters the active
3-10
state, and remains there during the execution of one instruction.
At the completion of the one instruction, the single-instruction
interrupt returns to the inactive state without the aid of a
branch and clear instruction.
Table 3-2. Interrupt Location Assignments
150
152
154
156
INTERRUPT CONTROL
Two program control features are available in the interrupt
system. These features are Enable/Disable and Arm/Disarm.
Arm/Disarm (optional hardware) controls whether an interrupt
can proceed from the inactive state to the waiting state. The
disarm conditionofan interrupt level prohibitsan interrupt signal
entering the level from causing the interrupt to enter "waiting"
from II inactive ll •
160
162
164
166
170
172
174
176
200
With Enable/Disable, the entire set of interrupts in the system
can be enabled and disabled under program control. When the
interrupt system is enabled, interrupts can proceed from the
waiting state to the active state.
l
1177
Power On (always armed)
Power Off (always armed)
Main Frame Parity Error (armed via a console switch)
Data Multiplexing System Parity Error (armed via a
console switch)
Unassigned
Unassigned
Interrupt, Clock Sync (always armed)
Interrupt, Clock Pulse (arm furnished)
11 (arm furn ished)
12 (arm furnished)
Unassigned
Unassigned
System Interrupts (arms optional, single instruction
discretionary)
l
System Interrupts
The following interrupts are exceptions and are always enabled:
ENABLE/DISABLE INTERRUPT INSTRUCTIONS
1.
Power fa ii-safe (2 interrupts)
Three instructions are available for setting, resetting, and
testing the state of the INTERRUPT ENABLED indicator.
2.
Memory parity error (2 interrupts)
3.
Real-time clock (2 interrupts)
4.
I/O Channel (2 interrupts)
EIR
ENABLE INTERRUPT
51
00
o
I
5 6
I
11
The control of the optional Arm/Disarm feature operates on
individual interrupt levels of the System interrupts (200-1176),
that is, any chosen interrupt level may be selectively armed
or disarmed. But the instruction structure for Arm/Disarm
allows these interrupts to be operated on in groups of sixteen.
EIR unconditionally sets the INTERRUPT ENABLED indicator
and enables the interrupt system. At the end of the next interruptable instruction, if any interrupt levels are waiting, the one
with the highest priority becomes active.
SINGLE INSTRUCTION INTERRUPTS ROUTINES
EIR cannot be interrupted.
Only the following instructions will be meaningfully interpreted
as single-instruction interrupt routines:
Registers Affected:
DIR
None
Timing: 3,4
DISABLE INTERRUPT
1.
EOM
2.
BMC, BRM
3.
MPO - MPO, in this case, will not alter the Flag.
However, if the restored, incremented operand equals
00008, a different interrupt pu Ise wi II be generated (see
Real-Time Clock Option, Appendix B-1).
DIR unconditionally resets the INTERRUPT ENABLED indicator
and disables the interrupt system. The current state of all
interrupt levels is unchanged by this instruction.
EXU - Can only execute the above-listed instructions.
DIR cannot be interrupted.
4.
50
00
o
I
5 6
NON-INTERRUPTABLE INSTRUCTIONS
Registers Affected:
An interrupt cannot occur between the execution of ENERGIZE
OUTPUT M (EOM) and the instruction following it. This is
also true for the input/output instructions, POT/BPO, PIN/BPI,
WOT/ROT, and WIN/RIN. No interrupt can occur between a
single-instruction interrupt and the return to the main program.
When these instructions branch, an interrupt cannot occur
between their execution and the execution of the branch-to
instruction:
lET
o
I
11
None
Timing: 3,4
INTERRUPT ENABLED TEST; SET FLAG
IF INTERRUPT SYSTEM ENABLED
01
50
I
I
11
If the priority interrupt system is enabled, lET sets the Flag Bit. If
the priority interrupt system is disabled, lET resets the Flag Bit.
BRU
BRL
BDA
BAX
BFF
BFT
Registers Affected:
3-11
F
Timing: 3,4
ARMING FEATURE
The two words which the PARALLEL OUTPUT (POT) instructions
address have the following format:
The arming feature is controlled for a group of 16 interrupts at
one time. (The 24-bit POT/PIN option is a prerequisite for the
arming feature. )
High-Order 12-bit Word
Address
The sequence of instructions required to arm the selected interrupts is:
EOM
POT
I
23
The address field in bit positions 0 through 5 identifies wh ich
group of 16 interrupts in the system is being addressed. The C
field controls what is done to the particular interrupt levels
selected in bit positions 8 through 23. Bit position 8 refers. to
the lowest-numbered level of the group, therefore the one with
the highest priority. Bit position 23 refers to the last or highestnumbered level, the one with lowest priority. The first group
of 16 is group 0, For example, words of 0024 and 0000 arm
level number 202 (the level of second highest priority),
Transmjt entire 24 bits to the arming chassis and arms selected interrupts
II
the extender to accept the next POTarming chassis that a 24-bit control
POT that follows. The second POT
transmission.
The control operations are:
6-7
The effective address of the Extender Alert EOM (an internal
type) is:
AIR
Not used
01
Arm all interrupt levels that are selected by a 1
in bit positions 8-23
Disarm all interrupt levels that are selected by a
in bit positions 8-23
Arm all interrupts selected by a 1 and disarm all
interrupts selected by a 0 in bit positions 8-23
o
o
11
o
INACTIVE
ARM INTERRU PTS
o
2
o
o
4
Function
00
10
2
o
I
2
4
5
I
6
7
+
+
,
Proceed if ARMED
o
I
3
8
11
12
EXTENDER ALERT EOM
The Extender EOM alerts
ted"word. AIR alerts the
word is coming with the
triggers the entire 24-bit
I
Select Bits
Arm interrupts
LOWTWELVE
78
Low-Order 12-bit Word
Load most significant 12 bits into
extender
AIR
Interrupt
56
Alert the extender
HITWELVE
POT
I
o
I
9
WAITING
10 11 12 13 14
Proceed if PROPER PRIORITY
+
AIR prepares the arm interrupt control unit to receive a control
word for a group of 16 interrupt levels. A PARALLEL OUTPUT
(POT) must always follow AIR, or an unpredictable operation
results.
Proceed if ENABLED
+
ACTIVE
AIR cannot be interrupted.
Registers Affected:
None
Timing: 3,4
Figure 3-3.
3-12
Interrupt Arm-Enable Response
CONTROL CONSOLE
ENABLE
ENABLE lights whenever the interrupt system is enabled.
The basic computer system includes a console for operator
control. This console connectsdirectly to the central processor,
contains switches for operation, and displays the contents of
operational registers.
FLAG
The FLAG indicator consists of a single binary indicator.
FLAG is lit when the Flag Bit is a 1.
DISPLAYS
The registers displayed on the console directly reflect the contents of the hardwa re reg isters. If the operator clears or changes
a display, the contents of the actual reg ister change identically.
SWITCHES
PROGRAM LOCATION
The POWER switch turns the computer system power on or off.
When power is on, the switch is I it.
POWER
This display consists of 15 binary indicators with a CLEAR button for the entire register and a set button for each indicator.
The program counter contains the location of the next instruction to be executed. The operator may change the contents of
the program counter via the CLEAR and set buttons. When the
operator places the computer in RU N, the first instruction comes
from the location shown in the PROGRAM LOCATION display.
FILL
To initiate a
II
fill ",
1.
Press the RESET button.
INPUT -OUTPUT
2.
Hold down the FILL switch correspond ing to the peripheral
dev ice from wh ich a fi II is desired.
The UNIT lights contain the unit address of the peripheral
device currently connected to the I/O Channel.
3.
Move the RUN/IDLE/STEP switch from IDLE to RUN while
continuing to hold the appropriate FILL.
The ERROR I ight reflects the status of the I/O Channel error
indicator.
4.
Release the FILL switch.
HALT
Fill causes the following:
The HALT light lights whenever the computer executes a halt
instruction while in the RUN position. Setting the RUN/IDLE/
STEP switch to IDLE clears the halt.
1.
Bit 0 = 0
REGISTER DISPLAY
Bit 1 =0
This display consists of 12 binary indicators with a CLEAR button for the entire register and a set button under the P Register
indicators that also serve the A, B, and C Registers. The Register switch selects the internal register to be displayed. The
selectable registers are:
C
C Register, which usually contains the contents of the
memory word whose address is in the program counter
A
A Register
B
B Register
An EOM opcode is generated.
I
~
_ _ _ Buffer Control Mode
Bit 2 = 0
Bit 3= 0 - - - Forward Direction
Bit 4 = 0
Bit 5 = 1
---.~
Binary Mode
Bit 6 = 0
Bit 7 = 1 ---~. Two Characters per Word
Bit a = 1
Placing the computer in IDLE, clearing the register, and then
pressing the button in the corresponding bit positions under the
indicators sets the contents of the selected register. Pressing a
button places a 1-bit into the selected position of the register.
Bit 9 - Bit 14 = The unit address of the indicated
peripheral:
Paper Tape
04a
Cards
06
Mag Tape
lOa
Disc
26
a
MEMORY PARITY
If an operand or instruction access from memory encounters
a parity error and the memory switch is in the HALT position
MEMORY PARITY lights. Setting the memory parity switch to
CONTINUE clears the indicator and turns off the light.
3-13
a
INT(RRUPT
--fllL-W
I
PAP(Jt
TAPE
CARDS
..AC
O"UM
.l>-
•
(NABLEO
HALT
I
MEMORY
PARITY
- - - - INPUT OUTPUT - - - _ _ _ _ UNIT _ _ _ _
fLAC
I
•
[RROR
CLUIt
TAPE
=1
• INTERRUPT
-------••• •••• • ••••
REGISTER DISPLAY
PROGRAM lOC. liON
"
RE SET
• HALT
• CONTINUE
" "
p.
• SET
BREAKPOIN T
Figure 3-4.
SDS 92 Computer Contro l Ponel
- MEM ORY
OtH
HO
•
RESE T
INCRE MENT
RUN IDLE ·
STEP.
2.
9 words (or to End-of-Record) read into memory starting in
location 00000 .
MEMORY PARITY
8
3.
Computation begins at location 00000 .
4.
NOTE: The I/O Channel is still active and the input
peripheral device is sti II sending characters to the channel. (If the fill routine is less than 9 words, the End-ofRecord makes the channe I inactive; computation sti II goes
to 00000.)
In the HALT position, this switch causes the computer to enter
the Idle state whenever a memory parity error occurs. In the
CONTINUE position, the computer does not change state when
a memory parity occurs. In the INTERRUPT state, any memory
parity will result in one of two interrupts (optional).
8
BREAKPOINT
The four BREAKPOINT switches are externally controlled, internally testable program switches. Breakpoint test instructions
test them.
RUN/IDLE/STEP
MEMORY OUT
The RUN/IDLE/STEP switch is a three-position, toggle switch
with two stationary positions and a spring-loaded momentary
position in STEP. In the RU N position, computation occurs at
machine speed. In the IDLE position, the computer idles immediately after an instruction has been read from memory. If
the Register switch is in the C position, the first word of an instruction may be viewed in the REGISTER DISPLAY. Depressing the switch to STEP reaccesses and executes the instruction;
the computer returns to the Idle state. To "step" another instruction, the operator releases the switch to the IDLE position
and then depresses it again to STEP. No interrupts can occur
(i.e., go into the active state) while stepping.
This is a momentary switch that causes the computer, in IDLE,
to place the contents of the location specified by the program
counter into the C Register.
MEMORY IN
Th is is a momentary swi tch that causes the computer, in ID LE, to
place into the location specified in the program counter fhe
contents of the C Register.
PERIPHERAL EQUIPMENT DESCRIPTION
This section describes some of the input/output devices thatcan
be attached to a buffer and explains their use.
HOLD/INCREMENT
Placing the HOLD/INCREMENT switch in the "up" position
causes the current contents of the program counter to be held.
This inhibits the program counter from counting.
INPUT/OUTPUT TYPEWRITER
The control console may contain an electric, input/output typewriter for operator control, error or status messages, and similar functions. The typewriter connects to the I/O Channel, has
the input unit address 01, and the output unit address 41. Appendix 1-1 contains the typewriter codes.
Momentarily placing the HOLD/INCREMENT switch in the
INCREMENT position increments the program counter by one
and brings the contents of the newly addressed location to the
C Register.
The typewriter control instructions follow. The sample instructions use Typewriter No. 1 with 2 characters per word mode.
RESET
This switch initializes the control section of the computer. It
resets the I/O Channel, clears the FLAG, sets PCT, clears the
INTERRUPT ENABLED, clears any parity error indication, clears
all interrupts arms, and clears a II interrupt levels. The operator must set the RUN/IDLE/STEP switch to IDLE before pressing this switch.
RKB 1,2
READ KEYBOARD
2 Characters/Word
02301t
This instruction activates the I/O Channel and connects to it
Typewriter No. 1. RKB readies the channel to read input from
the keyboard. This instruction lights the input light on the
typwriter.
Switch Select
TYP 1,2
This two-position toggle (labeled C and P) selects which REGISTER DISPLAY/PROGRAM LOCATION will be affected by the
C LEAR and set buttons.
WRITE TYPEWRITER
2 Characters/Word
02341
This instruction activates the I/O Channel and connects to it
Typewriter No.1. TYP readies the channel to write output to
the typewriter.
Register Select
This three-position switch selects the register to be shown on
the REGISTER DISPLAY lights.
t
3-15
This octal number is the EOM or SES effective address configuration.
EXAMPLE: Typewriter Output
This example types the following message:
DO
from location OUTWD; the internal codes for these characters are in this location.
routine assumes the channel to be initially inactive.
Location
IN
Instruction
Comments
RES
2
This assembler directive reserves two locations for the mark entry.
TYP
1,2
This EOM instruction connects Typewriter No. 1 to the channel for output
and spec ifies two characters per word. The octal configuration of the EOM
address is 02341.
WOT
OUTWD
This instruction transfers the contents of location OUTWD to the I/O Channel.
The new contents of the channel are output to the typewriter as two 6-bit charactersand typed. The next instruction in sequence is executed as soon as the
word is placed in the channel.
Th is instruction terminates output on the channel. When the channel and the
Sing Ie Character Register are c lear of characters to be output, the channel sets
its Unit Address Register to zero; th is disconnects the channel. When accessed,
this instruction executes immediately; the next instruction in sequence is then
executed. The octal configuration of this EOM address is 12100.
TOP
BRU
OUTWD
The routine uses Typewriter No.1; the
*IN
24 46
This instruction transfers to some other program area.
This word contains the internal code for the characters DO.
EXAMPLE: Typewriter Output then Input
PROG
This example types out the message:
then awaits the input of a single character. Input terminates with a carriage return typed by the operator; the housekeeping
necessary to determine when the carriage return has been input is not given.
IN
RES
2
TYP
1,2
Connect channel to Typewriter No. 1.
WOT
MSSGE
Output first word of message.
WOT
MSSGE+l
The central processor "hangs Up" on this instruction until the second character from the preceding instruction has cleared the channel buffer into the
Single Character Buffer for output. Then this WOT executes filling the
channel buffer with contents of location MSSGE + 1.
TOP
TEST
Terminate output when channel system is clear.
CAT
The program "hangs Up" here unti I the channel transmits the last character.
BFF
TEST
RKB
1,1
This instruction connects Typewriter No. 1 to the channel for input and
specifies one character per word. The octal configuration is 02101.
WIN
KEYWD
The computer "hangs Up" on this instruction until a characterentersthechannel from the keyboard; then the word in the channel buffer is placed into location KEYWD. The input character is in bit positions 0 through 5 of KEYWD.
Bit position 6 through 11 are unpredictable
At this point, the word in KEYWD is placed elsewhere in memory and the routine returns to the WIN above. When executed,
a test is made to determine if the new input character is the carriage return code. Indexing or indirect addressing can be
used with the WIN to facilitate input. When the carriage return is detected, the following is executed.
This instruction disconnects the channel by immediately clearing the Unit Address register to zero. The octa I configuration of the EOM address is 00100.
DSC
BRU
*IN
Return to main program.
3-16
frames). Bit position 4 of the EOM that addresses the punch
contains a "0" to punch leader; bit position 4 contains a "1"
to punch without leader.
PAPER TAPE INPUT/OUTPUT
Format
The paper tape used is one-inch wide, affording space for
eight data holes and a sprocket hole in each frame of information. There are ten frames per inch of paper tape. Six hole
positions are used for information, one is used for an odd
parity check, and the eighth is unused.
The EOM instruction that addresses and alerts the punch produces gap. No terminal punch operation produces gap after
punching a block.
The punch operates asynchronously. If the channel does not
supply characters to the punch fast enough, the punch waits
for each character, losing no data and creating no errors.
p
0
B
A
B
0 0
'0' ..
00
0
000 00
0
0
0
0
0
..0 .... . .0'0 .
0
0
00
00
Programming
00000
00
00
00
0
0
0
There are no status tests for the reader or punch, that is, they
are always ready for operation. When the channel addresses
either device, the device starts to send or accept data within
approximately one character time. The reader and punch operate only in the binary mode and the forward direction. The
reader or punch ignores any different mode specified, and uses
the forward-binary mode. Unit address of 04 is for Paper Tape
Reader 1, and unit address 44 is for Paper Tape Punch 1.
'000
00
0
i
~
Direction of Travel
Block of Information
Information is organized on the tape in blocks. A block is a
group of frames set off by a gap of at least one blank frame
(in which only the sprocket hole is punched) at either end.
Blocks may be of variable lengths.
Paper Tape Instructions
The following instructions use the I/O channel, Paper Tape
Number 1 with two characters per word format.
In some operations, a tape may consist of only one block, such
as a source language tape prepared off-line. In this case, the
program need not read the entire block at one time, but may
stop the reader between frames, by disconnecting via DSC, and
then start again to read the remainder or another portion of the
block.
RPT 1, 2
READ PAPER TAPE
02304
This instruction initiates a paper tape read operation on tape
read statioA number 1 connected to the channel in the two
characters per word format.
PTL 1, 2
A program reads paper tape in a straightforward way, using RIN or
a WIN in a read loop unti I the desired number of words are input or until gap is detected. The tape stops in less than on~
frame; this means that no frame is missed between subsequent read
operations. An input operation that terminates because of gap
(End-of-Record) stops the tape after the first blank of the gap.
When starting the tape for reading, the tape reader ignores any
leading blank frames. After reading a meaningful data word
(one or two characters as defined by the program) from the tape,
the reader recognizes the next blank frame as gap and signals
the channel with an End-of-Transmission indication.
PUNCH PAPER TAPE
WITH LEADER
00344
This instruction initiates a paper tape punch operation on tape
punch station number 1 connected to the channel in the two
characters per word format. It generates approximately twelve
(12) frames of leader preceding the first punched frame.
PPT 1, 2
PUNCH PAPER TAPE
WITHOUT LEADER
02344
Punching
The EOM to alert the tape punch also turns on the punch motor
(if not already on). If the punch instruction (EOM) so indicates,
the punch unit punches a segment of leader (gap, or blank
This instruction initiates a paper tape punch operation on tape
punch station number 1 connected to the channel in the two
characters per word format. It generates no leader preceding
the first punched frame.
3-17 -
EXAMPLE: Punch Paper Tape
This routine punches one block of eight words (16 characters) from locations 02000 thro~gh 02007.
precedes the block. The routine is a closed subroutine.
Location
FRST
Instruction
Address
A twelve-frame leader
Comments
RES
2
This instruction is an assembler mnemonic used for convenience to reserve the
subroutine entry locations.
PTL
1,2
This instruction connects the channel to Paper Tape Punch No. 1 and specifies
two characters per word mode. The instruction asks for leader to be punched.
The octal configuration for this EOM is 00344.
LDA
=7
This instruction sets (A) equal to 7.
ROT
02000
This instruction transfers each word as needed to the channel beginning in location 02000.
TOP
BRU
This instruction is executed in 4 or 5 cyc les and then the computer executes the next
instruction. The execution of TOP causes the channel to disconnect when the last
character shifts out of the buffer and transmits out of the Sing Ie Character Register.
*FRST
This instruction returns to the main program.
EXAMPLE: Read Paper Tape
This routine reads a 64-character block from paper tape into memory beginning at location 02000.
character per word mode, making the input 32 words. The routine is a 'c losed subroutine.
FRST
The routine uses the two
RES
2
This assembler instruction reserves the entry locations.
RPT
1,2
This instruction connects to the channel the Paper Tape Reader No. 1 and specifies
two characters per word mode. The octa I configuration for this EOM is 02304.
LDA
=33
The 33 represents two more than the expected record size.
RIN
02000
This instruction receives each word in the block beginning in location 02000 and
going through 02037 ,
8
When the channel detects the End signal (gap) following the block during the input transmission, the RIN finishes execution
and the computer goes to the next instruction.
CARD INPUT/OUTPUT
one of the 64 combinations listed in Appendix 1-1 results in a
Validity check. Presence of a Validity check causes an error
signal to be sent to the channel and lights the VALIDITY CHECK
Iight on the reader. If the stacker shou Id become fu II, or the
hopper empty, the reader goes Not Ready and Iights the NOT
READY light. The card reader remains in the Not Ready state
until the operator corrects the situation and presses the START
button. Upon reading the last card, the reader sets an End-ofFile signal if its EOF ON switch is on. The central processor
can test the End-of-Fi Ie signal which determines if more cards
are in the hopper.
Format
The computer uses 80-columncards in two formats: Hollerithand
binary. The reader reads Hollerith-coded information from cards
and the corresponding SDS character codes go into memory. In th is
mode, each card column contains the equivalent of one 6-bit internal character. The character codes are in Appendix I-l.
Binary-coded information goes onto the card with two 6-bit
characters per column. In binary mode, one column forms a word.
The reader reads the card from column 1 to 80 in a top-bottom order. A single card holds 160 characters.
Punching
Figure 3-5 shows the relation of Hollerith information on a card
and in memory.
The punch punches cards a row at a time, starting with row 12.
The punch coupler in both Hollerith and binary modes automatically rearranges the information to be punched. The card
punch program must present the entire image, 80 or 160
characters, to the punch 12 times for each card. The punch
operates in the following manner. As each row of the card approaches the punch station, the coupler examines every character of the image to determine which column position in that
row shou Id be punched. After the 12th output, the punch
punches row 9 and completes the card cyc Ie.
Reading
The card reader scans the card, column by column, starting with
column one, and transmits either 80 or 160 characters depending
on the mode of operation. With poweron and cards in the hopper,
the operator readies the reader by pressing the START button.
During program operation, the program must test for the Ready
condition before initiating a card-read. A Read EOM instruction starts the card-reading operation; then the program controls the flow of information into memory via a RIN or WIN
loop. The end of the card sets the End-of-Record condition.
In the Hollerith mode, any column-read that is not punched in
The card punch is Ready to punch if there are cards in the magazine, the stacker is not full, and the START button has been
3-18
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Figure 3-5. Card Read Into Memory in Hollerith
pressed. The punch remains Ready as long as the above conditions are true. A punch card instruction given when the punch
is Ready causes a card to feed past the punch station. The program must then give the same instructions 12 times to transmit
the card image to the coupler.
RCB 1,2 READ CARD BINARY
RC B a Ierts the card reader, causes a card to feed from the hopper
and selects the binary mode (as each column is read it is transmitted as two 6-bit binary characters). This mode reads up to
160 characters (80 words) from a card.
Programming Instructions
Card Punch Instructions
The card reader instructions below use unit number 1 with the
two characters per word transmission mode.
CRT 1
CARD READER READY TEST
CPT 1
CARD READER END-OF-FILE TEST
CARD PUNCH READY TEST
the computer resets the Flag Bit.
The operator makes the punch Ready by placing blank cards in
the magaz ine and pr-essi ng the START button.
11106
PC D 1,2 PUNCH CARD DECIMAL (Hollerith)
This test determines if the End-of-File condition from the card
reader has been detected. If not, the computer sets the Flag
Bit. If the EOF condition has been detected, the computer resets the Flag Bit.
PCB 1,2
READ CARD DECIMAL (Hollerith)
02346
PC D alerts the punch, causes a card to feed past the punch station and selects the Hollerith mode. A transmission of 80 characters (40 words) must follow this instruction. The instruction PC D
followed by the transmission instructions for 80 characters per
card must be repeated 12 times.
The reader remains in the End-of-Fi Ie condition unti I cardsare
added to the hopper or until the EOF ON switch is turned off.
RCD 1,2
14146
This test determines if the selected card punch is Ready to punch.
If so, the computer sets the Flag Bit. If the punch is Not Ready,
12106
This test determines if the selected card reader is Ready to read.
If the reader is Not Ready, the computer resets the Flag Bit.
CFT 1
03306
PUNCH CARD BINARY
03346
02306
PCB alerts the punch, causes a card to feed past the punch station and selects the binary mode. A transmission of 160 characters (80 words) must follow this instruction. The instruction
PCB followed by the transmission instructionsfor 160 characters
per card must be repeated 12 times.
RCD alerts the card reader, causes a card to feed from the hopper, and selects the Hollerith mode (as each column is read, it
is translated to an SDS internal code). This mode reads up to
80 characters (40 words) from a card.
3-19
EXAMPLE: Card Read
This program reads one card in Hollerith mode. It is a closed subroutine. The program enters the routine via a BRM.
Location
Instruction
FRST
RES
TEST
CRT
Comments
Address
2
This assembler instruction reserves locations for the subroutine entry.
This instruction is the card reader Ready test for Card Reader Number 1.
It sets the Flag Bit if ready.
BFF
TEST
This instruction branches back to the test on Not Ready. An exit to
a Not Ready corrective routine can be put here.
RCD
I, 2
This instruction connects the Card Reader 1 and starts a card moving
toward the read station. Hollerith mode is specified. The octal configuration for this instruction is 02306.
LDA
=39
This is the repeat count for RIN.
RIN
READ
Beginning in READ, this instruction transfers words from the channel
into the locations until the entire card is read.
BRU
"'FRST
This instruction branches back to the main program.
EXAMPLE: Card Punch
The program punches one card in Hollerith mode beginning from location 03740.
the program presents the card image to the punch.
FRST
TEST
GEE
RES
2
LDB
=11
This instruction reserves the locations for the subroutine entry.
This instruction tests the card punch for a Ready condition. It sets the
F lag Bit if Ready.
CPT
BFF
TEST
This instruction branches back to the test, CPT I, if the Flag is reset.
An exit to a time loop with .the facility to tell the operator that the
card punch wi II not become Ready can be placed here.
PCD
I, 2
This instruction executes if the punch is Ready. It connects the channel
to the Card Punch Number I, and starts a card moving toward the punch
station. The two characters per word and Holleriih mode are specified.
LDA
=39
Starting with location 03740, ROT transmits 40 words to the Punch.
ROT
03740
This terminates output.
TOP
CTEST
The B Register counts the 12 times
CAT
Wait for the last character to be transmitted.
BFF
CTEST
SUB
=1
BFF
GEE
BRU
*FRST
SUB decrements (B) by one and sets F if the new (B) is equal to 7777 ,
8
Note that the card image must be sent to the channel twelve times to
punch a card.
Return to main program via location FRST.
3-20
The longitudinal check character always reflects an even parity
check for each channel. In the BCD mode, the check character
itself always has an even number of 1-bits. In the binary mode,
however, the check character may have either an even or an
odd number of 1-bits. This means that a reverse scan over a
binary record may result in turning on the error indicator in the
buffer even though the record itself is correct. As a general
rule, the program ignores the error indicator after a reverse operation.
MAGNETIC TAPE INPUT/OUTPUT
Magnetic tape units used in SDS computer systems are IBMcompatible. The tape is one-half inch wide, Mylar base material, 1.5 mils thick. Tape reels (10 1/2 inch, plastic) contain up to 2400 feet of tape. A reflective marker, placed on
the back of the tape approximately ten feet from the beginning
of it, indicates the load point. The leading ten feet leave
space for threading tape through the guides on the unit. The
load point marker is on the My-Iar side of the tape along the
edge nearest the operator when the tape is mounted. A similar
marker is along the other edge of the tape to mark the end-ofreel. About 14 feet of tape are reserved between the end-ofreel marker and the end of the tape. This space includes at
least ten feet of leader and enough tape to hold a record of
9,600 characters in 200 bpi density after the end-of-reel
marker is sensed.
Routines should always place a TAPE READY TEST (TRT) between
tape operations of opposite direction to ensure that the tape
unit stops and reverses. Good programming terminates tape
writing by several inches of erasure whenever subsequent resumption of recording is anticipated. This eliminates the effects
of a possible extraneous character that might arise through subsequent tape repositioning.
Characters are recorded on tape in seven parallel tracks. A
change in the magnetic flux in a track records a 1-bit for a
given character position. No change in magnetic flux indicates
a O-bit. Six of the tracks contain information; the seventh track
is a parity check. The system allows both even and odd parity,
as needed. Binary recording uses odd parity. In this mode, the
tape records the six-bit charcicters from memory without change.
Binary-coded decimal (BCD) recording uses even parity. In
this mode, the tape control unit transforms characters from the
channel to conform with standard IBM, BCD interchange code
(see Appendix A-1).
A Read Binary or Read BCD EOM starts a tape which continues
until the tape unit detects an End-of-Record gap. If the computer does not instruct the tape unit to continue, it stops in the
middle of that gap. When the tape stops, the tape unit disconnects from the channel. If the tape encounters an End-of-File,
the tape control unit sets its EOF indicator. The central processor can test this indicator which remains set until the tape
unit control receives a new EOM. The tape always stops after
the Tape Mark.
At the end of the file, the program reads the EOF character
(0001111) into memory along with its check character. In a
two character per word read, this appears in the first word of
the input area as a 1717 word.
Only the capacity of available core storage in the computer
limits block length. A record gap (section of blank tape) about
3/4-inch long separates blocks on tape. In writing, the tape
automatically produces gap at the end of a record. Reading
begins with the first character sensed after the gap and continues until the next gap is encountered.
When the tape unit is writing on tape, it may transmit flux disturbing surges ahead of the current writing position; these surges
affect previously written records further down the tape. This
means that a record in the middle of a fi Ie cannot be updated
or rewritten if the records that follow it are to be read.
An inter-record gap, followed by a special, single-character
record, marks the end of a file of information. The character
is a Tape Mark (0001111). Writing a one-word record in BCD
with one-character-per-word format can record such a mark.
Any error detected either by the channel in the character parity check or by the control unit with the longitudina I parity
check sets the channel error -indicator. When detecting such
an error in reading, the routine should backspace the tape over
the erroneous record and attempt to lire-read II the record.
A program may write one or more files on a reel of tape. On
reading an End-of -File record, the tape control unit stops
the tape and sets its End-of-File indicator which may be tested
by the program.
The tape backspaces over records using the Scan feature. A
Scan reverse EOM starts the tape in reverse. A TERMINATE
INPUT (TIP) EOM should immediately follow. The program
then waits for the channel to become inactive (or awaits the
End-of-Transmission interrupt if armed and the interrupt system
is enabled). When the channel becomes inactive (or the Endof-Transmission interrupt occurs), the tape stops in front of the
backwardly traversed record.
The tape control unit considers any record containing only Tape
Mark (0001111) characters an End-of-File. The tape reads such
characters into m-emory like any other characters.
As the tape unit writes information, it makes an odd-even count
of the number of 1-bits in each track. At the end of each record, it writes a bit for each track such that the total number of
1-bits in each track is even. This parity check sum is always
even whether the character parity is even or odd. The character containing these check bits is the longitudinal parity character; the tape unit writes it slightly past the end of recorded
information in the block.
A Scan operation is similar to a Read operation except that the
channel shifts the characters read through its Word Assembly
Register, but does not consider a word complete unti I a tape
3-21
gap is encountered. When the tape reaches the gap, the
channel uses the last two characters in the word assembly as
the only word read from the record. When scanning in reverse,
the word consists of the last two characters scanned that are
the first two logical characters of the record. This operation assembles these characters in reverse. For example, if
the first two characters of the record are 12 and the tape scans
the record in reverse, these appear as 21 in the word stored for
that record.
In addition to writing under program control, the program can
also erase tape. When an Erase EOM with an erase unit address is used, the tape operates as though it were in a Write
mode, except that it records no information. The program
counts the number of words to be erased.
The use of this type of erase is for the correction of a Write error. When a Write error occurs, an ERASE REVERSE TAPE starts
the tape in reverse. Then the same count used to write the record originally controls the erase. This procedure ensures that
the tape always returns to the beginning of the erroneous record, even if a bad spot on the tape might appear as a gap.
The routine may now rewrite the record. If the Write still produces an error, the routine erases the record backward and
then erases it forward, using the same count and bypassing the
section of tape where the difficulty occurred. The routine may
now rewrite the record on a new section of tape.
The same operations occurs in the forward scan with the last
two characters of the record forming the word stored. The
Scan is useful for reverse searching on the first word of the records in the fi Ie being searched. In this case, the routine
starts the tape in a reverse scan and IIhangs Upll on a WIN.
When the tape reaches the beginning of the record, the first
word of the record transfers to the buffer. The WIN stores the
first word and the program checks the key word against the
search key. If they agree, then the program need only wait
for the channel to become inactive and the routine reads the
record forward. If the record is not the desired one, the program gives another Scan reverse without waiting for the channel to become inactive.
The erase procedure is used to produce the required 3.75 inches
of blank tape between the load point and the first record. A
routine does this by erasing 300 words at 200 bpi density, 834
words at 556 bpi density, or 1200 words at 800 bpi density.
EOM instructions to the tape units specify start-without-Ieader
since the tape un it generates gap at the end of a" records for
leader. A leader instruction should never be included in a
magnetic tape program because an attempt to generate leader
may cause an erroneous operation.
If the tape encounters the End-of-Reel marker while reading,
the tape logic sets the End-of-Reel indicator in the tape unit;
the program can test this at any time. An End-of-File normally indicates the end of recorded information on tape. Possibly,
however, the End-of-Reel indicator may mark the last record
on the reel.
Programming
Writing
A Write routine writes tape after testing the tape unit for
Ready and testing for the fi Ie protect ring on the tape reel
(i.e., the flag was set by the test). The Write tape EOM starts
tape motion; the tape remains in motion unti I it receives the
termination signal from the channel. The tape control unit
then writes the remaining characters of the record (those in the
channel buffer) and writes the longitudinal check character.
When the read-after-write head reads this check character,
the tape signals the channel that it has reached Gap. If the
tape receives no further Write instruction within one millisecond, the tape stops and disconnects.
The SES and EOM instructions for normal tape operations are
Iisted below. The EOM instructions use two characters per
word format.
If the user wishes to backspace or rewind and then to return at
some later time to record additional information at the end of
the previous series of records, the routine should write an Endof-File character or erase a segment of t~pe after the series of
written records. This practice provides positive identification
of the end of file and facilitates return to a specific location
on the tape. If the programmer does not use this method, the
tape may not subsequently stop in the same location at the end
of the series of records as it did when writing the last record.
This would leave a segment of tape in the gap which has not
been written and may cause erroneous operation when reading
the ,tape.
if there is no physical unit set to the logical unit number
be i ng tested,
TRT n
TAPE READY TEST
1051n
TRT test tape unit number n for Not Ready. If the tape is Not
Ready, the computer sets the Flag Bit. If the tape is Ready,
the computer resets the Flag Bit.
A tape is Not Ready:
if the selected unit is not in the Automatic mode, or
if the tape is in motion for any operation.
a
FPT n
FILE PROTECT TEST
1411n
FPT tests tape unit number n for file protect ring. If the file
ring is inserted, the computer sets the Flag Bit. If not inserted, the computer resets the Flag Bit. The reset will occur if
logical unit n is absent from the channel line.
3-22
BTT n
BEGINNING OF TAPE TEST
1211n
END OF TAPE TEST
RTB n,2
DENSITY TEST, 200 BPI
11lln
RTD n,2
DENSITY TEST, 556 BPI
SFB n,2
DENSITY TEST, 800 BPI
SFD n,2
I
TAPE END-OF-FILE TEST
SRB n,2
1671n
WRITE TAPE IN DECIMAL (BCD)
SCAN FORWARD IN DECIMAL (BCD)
SCAN REVERSE IN BINARY
SRD n,2
REW n
1731n
0233n
0733n
SCAN REVERSE IN DECIMAL (BCD)
0633n
REWIND
1411n
REW starts tape unit n in a Rewind.
RTS
a
CO NVERT READ TO SCAN
14100
RTS converts an in-process Read operation to a Scan. If the interrupts are disabled when the gap is encountered and the program is hanging on a WIN (executed after RTS, but before the
gap), the WIN brings into memory the last two characters from
the channel buffer. If the interrupts are enabled, an End-ofWord (11) interrupt occurs when the gap is encountered by the
tape unit; the last character is avai lable via a WIN. If another
Read or Scan EOM is executed within 1 millisecond of the gap
occurrence, the tape does not stop and no End-of-Record (I2)
interrupt occurs; if not, an 12 interrupt occurs when the tape is
actively stopping (1 millisecond).
13710
0335n
Note:
WTB starts tape unit n in a Binary Write mode.
WTD n,2
0333n
SRD starts tape unit n in reverse in a BCD Scan mode.
The End-of-File indicator remains set until another tape operation is requested.
WRITE TAPE IN BINARY
SCAN FORWARD IN BINARY
SRB starts tape unit n in reverse in a Binary Scan mode.
TFT test the tape control unit for a tape under its control encountering an End-of-Fi Ie during the last Read or Scan operation.
If the End-of-File indicator is reset, the computer sets the Flag
Bit. If the End-of-File indicator is set, the computer resets
the Flag Bit.
WTB n,2
0231n
SFD starts tape unit n forward in a BCD Scan mode.
1631n
DT8 tests tape unit number n for being set at 800 bpi density.
If not, the computer sets the Flag Bit. If so, the computer resets the Flag Bit.
TFT
READ TAPE IN DECIMAL (BCD)
SFB starts tape unifn forward in a Binary Scan mode.
DT5 tests tape unit number n for being set at 556 bpi density.
If not, the computer sets the Flag Bit. If so, the computer resets the Flag Bit.
DT8 n
0331n
RTD starts tape unit n in a BCD Read mode.
DT2 tests tape unit number n for being set at 200 bpi density.
If not, the computer sets the Flag Bit. If so, the computer resets the Flag Bit.
DT5 n
READ TAPE IN BINARY
RTB starts tape unit n in a Binary Read mode.
ETT tests whether tape unit number n is not positioned at the
end of the tape. If the tape unit has not sensed the End-ofReel marker, the computer sets the Flag Bit. If the End-ofReel marker has been sensed, the computer resets the Flag Bit.
The End-of-Reel condition is reset when the tape is moved
backward over the End-of-Reel marker. The reset will occur
if logical unit n is absent from the channel line.
DT2 n
0737n
ERT starts tape unit n in reverse in an Erase mode.
BTT tests tape unit number n for the beginning of the tape. If
it is not positioned on the load-point marker, the computer sets
the Flag Bit. If positioned at the load-point marker, the computer resets the Flag Bit. The reset will occur if logical unit
n is absent from the channel line.
ETT n
ERASE REVERSE TAPE
ERT n,2
0235n
All scans must be in the 2 characters/word mode. This
necessarily implies that the read operation preceding
an "RTS" must have been in the 2 characters/word mode.
WTD starts tape unit Wn in a BCD Write mode.
MAGNETIC TAPE EXAMPLE PROGRAMS
EFT n,2
ERASE FORWARD TAPE
0337n
The following examples show samples of complete input/output
programs for magnetic tape.
EFT starts tape unit n in an Erase mode.
3-23
EXAMPLE: Magnetic Tape Read
This program reads one record from Magnetic Tape No. 1 on the I/O Channel.
tape is not at the beginning or the end of the tape.
The program is a closed subroutine.
Location
Comments
Instruction
FRST
RES
TEST
TRT
2
The
This instruction reserves locations for the subroutine entry.
This instruction tests Ready Magnetic Tape No. 1.
the command is 10511.
The octal configuration for
BFT
TEST
This instruction branches back to TRT if the F lag is set. An exit to a routine that determines reason for the non-Ready condition can be placed here.
RTD
1,2
This instruction activates the channel, connects it to Magnetic Tape No.1, and
starts tape motion. The two characters per word and BCD modes are specified.
LDA
=99
This count is for the RIN instruction to read 100 words.
RIN
03000
Read 100 words starting at location 03000.
TIP
BRU
Terminate input.
*FRST
This instruction branches back to the main program via FRST.
EXAMPLE: Write Magnetic Tape
This program writes one record on magnetic tape.
FRST
RES
TEST
TRT
BFT
2
BRML
This instruction reserves locations for the subroutine entry.
This instruction tests whether Magnetic Tape No. 1 is ready.
TEST
Thi s tests the Flag True. Thi s instruction branches back to the Ready test if the Flag
is set.
This instruction tests whether the fi Ie protect ring is present on the tape reel. If so,
the computer sets the Flag Bit. The octa I configuration of the address is 14111.
FPT
CTEST
The program is a closed subroutine; it uses Magnetic Tape No. 1.
BFF
BRML
If the Flag is reset, branch to BRML.
WTD
1,2
This instruction connects the channel to Magnetic Tape No.1, specifies BCD
transfer mode, and starts the tape moving. Two characters per word mode is
specified. The octal configuration of the instruction is 02351.
LDA
=99
The 100 is the block length.
ROT
02000
Starting at location 02000, ROT writes 100 words.
TOP
This terminates output.
CAT
Wait for channel to disconnect.
BFF
CTEST
BRU
*FRST
This instruction branches back to the main program via FRST.
BRM
OPER
This instruction branches and marks to an assumed routine to call the operator
and instructs him to insert file-protect ring on Magnetic Tape No. 1.
3-24
LINE PRINTER
preclude computer intervention while changing paper or ribbon,
or operating the TOP OF FORM or SINGLE SPACE switches.
SDS buffered line printers are capable of printing up to 1000
lines per minute at 132 characters per line, with a standard
set of 56 characters. Printing is accompl ished by means of a
rotating character drum and a bank of 132 print hammers. The
drum passes 56 different characters, in Iines of 132 each, past
the hammer bank. Upon command from the computer, the
selected print hammers drive the paper against the ribbon and
onto the appropriate character typeface as it passes the print
position. The characters are transmitted sequentially for
storage in the printer buffer before printing. A programmable
format tape loop provides fixed (or preselected) space control.
Upspac ing of 1 to 7 I ines, as well as page control, may be
accomplished by program instructions.
Pressing TOP OF FORM causes the printer to position paper
according to format tape channell. This indicator is lighted
only when the format tape is positioned at channell, that is,
top-of-form on a standard tape loop. Th is switch is operative
when there is paper in the printer and the READY indicator isoff.
Pressing SINGLE SPACE causes the printer to upspace paper
one single space, independently of the vertical format tape.
Th is switch is operative when there is paper in the machine and
READY is off.
The FAULT indicator lights when the printer detects a parity
error as information transfers from the buffer to the print
hammers, or when it detects a parity error in incoming data
from magnetic tape or cards during an off-I ine operation. It
remains lighted unti I the next EOM addresses the printer. The
condition of the I ight corresponds to the status of a programtestable fau It ind icator in the printer.
An optional, off-I ine faci Iity allows the program or the operator
to initiate card-to-printer or magnetic tape-to-printer operations simu Itaneous with computation (see Off-Line Printing).
Printer Controls
The printer controls, Figure 3-6, for SDS Iine printers consist
of eight switches and indicators.
(
P~%ER
(
READY)
)
MANUAL OFF LINEt is a combination switch and indicator for
off-I ine operation. The computer or the operator may initiate
off-I ine operation, which is indicated by the illumination ofthe
bottom half of this switch. If the operator presses this switch
to initiate off-line operation, the top half is also lighted. This
indicator is normally reset when the end-of-file is detected
from the input unit. Pressing READY when it is lighted also
resets it, that is, by switching the printer from the "ready"
to the "not ready" state.
t
The FORMAT/SPACE switch is used in off-I ine operation.
The operator may use either mode, spacing a single space after
each Iine of print, or using the first character stored on tape
or cards as a vertical format character.
t
The TAPE/CARD switch selects the desired input device.
Paper Tape Format Loop
fl- . . .:~. :. .;~:. :. ~E=-D- -1)
(
FAUL T
)
Figure 3-6. Printer Control Indicator Lights and Switches
The POWER ON switch is an alternate action switch. The
computer must be turned on for this switch to be activated.
Pressing POWER ON lights the top half of the indicator,
turns on the motors and hammer driver power supply, and
starts a timer that allows the motors to reach proper speed.
After 20 seconds the bottom half lights, indicating that the
printer is operable.
A paper tape format loop, placed in the printer, allows upspacing to proceed to prespecified vertical positions on the
print page. The format loop is an eight.:.channel paper tape.
Putting a punch in the specified channel at the desired vertical spacing selects the channel upspace. Channel 1 is the
top-of-form channel, channel 7 is the bottom-of-form channel,
and channel 0 is the single-upspace channel. In the off-I ine
mode with SPACE control, channel 0 controls single spacing.
When printing with no format loop inserted in the printer,
single upspacing occurs regardless of the channel specified.
Terminating Line Printer Output
When the sing Ie-word mode of transmission is used for printing
on the line printer, each character transmission for a line must
be followed by a TERMINATE OUTPUT (TOP) instruction. TOP
is automatically generated with interlaced outputs.
When the printer is initially turned on, the READY indicator
is off. When pressed, it is turned on if:
1.
paper is loaded in the line pri nter,
2.
the lower half of the POWER ON switch is lighted, and
3.
the hammer power supply is on.
This indicator automatically goes off when the above conditions are not real ized. The printer is ready for either on-I ine
oroff-I ine operation when READY is turned on. Ready is reset to
Error Conditions
1.
Print fault - parity error during transfer of character
information from print buffer to print hammers.
2.
Buffer error - parity or character rate error during transfer of information through buffer.
t If an off-I ine coupler is not attached to the printer, the
MANUAL OFF LINE, FORMAT SPACE, and TAPE CARD
indicators neither light nor affect printer operation.
3-25
3.
Input fau It - parity error in incoming data from cards or
magnetic tape (during off-I ine operation only).
Off-Line Printing
The optional, off-I ine facil ity allows the Iine printer to
produce printed records from card or magnetic tape sources
without computer attention. The character transm ission proceeds directly from the source to the computerfor other input/
output operations (e.g., card reading on card reader 2, card
punch, paper tape read/punch, disk read/write, etc.). Once
initiated, the printing operation is controlled by the source
and proceeds until the source generates an end-of-file signal
(see card input and magnetic tape input for appropriate endof-file conditions).
The FAU LT indicator Iights when a parity error is detected
during the reading of a tape record; the off-I ine printer rereads
the record in an attempt to read good data. If th is reread record
contains an error, FAULT lights, the off-line operation terminates, and the printer goes back on-I ine if physically connected
to the computer and the MANUAL indicator is off. When a
val idity check occurs during a card read, FAU LT Iights, the
operation terminates, and the printer goes back on-line if the
MANUAL indicator is off. The next EOM addressing the
printer resets FAULT if the printer is on-line. If the MANUAL
indicator is on, the error condition may be cleared by pressing
READY off and then on again. If a fault occurs in an off-line
operation initiated by the computer, the usual method for
clearing the error is:
1.
Press MANUAL on.
2.
Press READY off.
3.
Press READY on.
4.
Press MANUAL off.
Off-line printing can be formatted as desired through the use
of a single upspace or the format control mode (see Table 3-3).
Off-line printing terminates by an end-of-file indicator from
either device. Upon termination of an off-line operation, a
physically connected off-line printer system returns on-line,
provided the MANUAL indicator is off.
Format Control Characters
Code
Character
Function
00
01
02
03
04
05
06
07
40
41
42
43
44
45
46
47
0
1
2
3
4
5
6
7
- (hyphen)
Skip to format channel 0
Skip to format channell
Skip to format channel 2
Skip to format channel 3
Skip to format channel 4
Skip to format channel 5
Sk ip to format channel 6
Skip to format channel 7
Do not space
Upspace 1 line
Upspace 2 lines
Upspace 3 lines
Upspace 4 lines
Upspace 5 lines
Upspace 6 lines
Upspace 7 lines
J
K
L
M
N
0
P
1.
Switch on the desired input device. (Magnetic tape is
selected by dial ing it to logical tape number 7.)
2.
Place paper at top of form, as desired, by means of the
TOP OF FORM switch.
3.
Select desired input device by means of the TAPE/CARD
switch.
4.
Select either the FORMAT or SPACE mode as required.
5.
Press MANUAL OFF LINE switch.
6.
Press READY switch on, which initiates actual data transfer.
Printing Off-Line Under Computer Control
The procedure for computer control of off-I ine printing is:
1.
Turn the equipment on.
2.
Prepare the desired input device for operation.
3.
Select desired input device by means of the TAPE/CARD
switch.
4.
Select either the FORMAT or SPACE mode as required.
5.
Press the READY switch on.
6.
Under program control, test the tape or card unit and the
I ine printer for II ready" cond ition.
7.
Then, to start transfer of data, give the POL instruction
to print off-line.
Programming
In a manually-initiated off-line operation, steps 1 and 4 are
not required.
Table 3-3.
Printing Off-Line Under Operator Control
The procedure for operator control of off-I ine printing is:
SES and EOM instructions that have spec ial use with the printer
follow. For convenience, assume that the instructions address
the channel and connect, test, or use Line Printer Number 1 on
the channel.
PRT 1
PRINTER READY TEST
12160
This instruction tests the printer for a Ready condition. If the
printer can accept a I ine to be printed, or accept a skip or
space instruction, it is Ready. If the printer is Ready, the
computer sets the Flag Bit. If the printer is Not Ready, the
computer resets the Flag Bit.
When the printer is upspac ing paper, PRT tests for Ready before the
dpw
rnmnlp.tp..
Thp.rp.fnrp..
seoaratina
- . - . - ic;
----·'1-----. . - - - - - - - , .PRT
- - -is
' ineffective
_ .. - for
I
- two
successive upspace operations. The second upspace specified may
override the first one un less suffic ient de lay is inserted (see PSP).
EPT 1
END OF PAGE TEST
14160
This instruction tests the printer for having paper positioned at
the End-of-Page, which is marked by a punch in channel 7. If
not at End-of-Page, the computer sets the Flag Bit. If at Endof-Page, the computer resets the Flag Bit.
PFT 1
PRINTER FAU LT TEST
11160
This instruction tests whether the PRINT FAULT indicator isset.
If not set, the computer sets the Flag Bit. If set, the computer
resets the Flag Bit.
3-26
PRINTER OFF-LINE
POL 1
I
Approximate completion times for PSP (from initiation of
instruction to paper stop) are:
10360
This instruction places the printer off-line to begin an off-line
print operation. The card reader and/or magnetic tape attached
to the channel also goes off-line (see Off-line Printing).
PSC 1, n
Upspace 1 line: 25 milliseconds
Upspace more than 1 line: Add 10 milliseconds for each
additional line.
Off-line Print Termination
PRINTER SKIP TO FORMAT CHANNEL n 1n560
Off-line printing terminates when an end-of-file indicator from
the magnetic tape unit or card reader occurs. When printing
from magnetic tape, the print operation terminates when the
first character read from a record is the end-of-fi Ie code,
octal 17.
The printer sk ips to format contro I channe I n, where n denotes
a channel number from 0 to 7. The format control is an eightchannel paper tape loop that is as long as the paper being used.
(See PSP for timing.)
PSP 1, n
PRINTER UPSPACE n LINES
When printing from cards, the print operation terminates when
the end-of-file signal comes from the reader. This occurs when
the card hopper becomes empty and the EOF ON switch on the
reader is on (END OF FILE indicator lights). If the hopper
becomes empty when EOF ON is not Iighted, the printer waits
for more cards to be placed in the hopper and the reader to
become ready. When the reader isagain ready, printing resumes.
1n760
The printer upspaces from 0 to 7 I ines as specified by n.
Consecutive upspace instructions must be separated by a sufficient time delay. Otherwise, the two PSP instructions may be
merged by the printer.
EXAMPLE: Print Two Lines
This program prints two I ines at the top of a page with a single upspace between. Assume that the printer is Ready or is
becoming Ready after a print operation. The program is a closed subroutine for printer number 1.
Location
FRST
TSTl
TST2
TST3
Instruct ion
Address
Comments
RES
2
Saves locations for subroutine entry.
LDA
= 65
Load A with 65 for the length of a line image.
This instruction tests for printer Ready. If not Ready, the computer
resets the Flag Bit. If Ready, the computer sets the Flag.
PRT
Not Ready, retu rn to the test.
BFF
TSTl
PSC
1,
This instructs the printer to move paper to the top of the page. The
octal configuration is 11560.
PLP
1, 2
Connect line printer to the channel, specify 2 character/word mode.
ROT
LINE1
Output 66 words from line 1 image area.
TOP
Terminate output.
CAT
Wait for channe I to disconnect
BFF
TST2
LDA
= 65
PRT
Reload A with 65.
Wait for printer to become ready after printing first line.
BFF
TST3
PSP
1,
Upspace printer 1 line. The octal configuration is 11760.
PLP
1, 2
Address printer.
ROT
LINE2
Output image for line 2.
TOP
BRU
Terminate.
*FRST
Exit the subroutine via the BRU.
3-27
SDS CHARACTER CODES
Characters
Typewriter
Printer
o
SDS
Internal
Code
Card
Code
00
o
Magnetic Tape
BCD Code
on Tape
01
2
2
02
SDS
Internal
Code
Card
Code
Magnetic Tape
BCD Code
on Tape
12
40
11
40
01
41
11-1
41
K
42
11-2
42
2
02
Characters
Typewriter
K
Printer
3
3
03
3
03
L
L
43
11-3
43
4
4
04
4
04
M
M
44
11-4
44
5
5
05
5
05
N
N
45
11-5
45
6
6
06
6
06
o
o
46
11-6
46
7
7
07
7
07
P
P
47
11-7
47
8
8
10
8
10
Q
Q
50
11-8
50
9
9
11
9
11
R
R
Blank
12
8-2
# or =
13
8-3
13
@or
14
8-4
14
15
8-5
15
Space
I
12 0
Car. Ret. ! 0
!0
$
51
11-9
52
11- 0
53
11-8-3
53
54
11-8-4
54
55
11-8-5
55
51
0
52
>
>
16
8-6
16
56
11-8-6
56
.J
.J
17
8-7
17
57
11-8-7
57
& or +
+
20
12
60
t)
60
Blank
20
A
.A.
21
12-:1
61
/
/
61
0-1
21
B
B
22
12-2
62
s
S
62
0-2
22
C
C
23
12-3
63
T
T
63
0-3
23
D
D
24
12-4
64
U
U
64
0-4
24
E'
25
12-5
65
V
V
65
0-5
25
F
26
12-6
66
W
W
66
0-6
26
G
27
12-7
67
X
X
67
0-7
27
G
Blank
H
H
30
12-8
70
Y
Y
70
0-8
30
I
I
31
1®
12-9
71
Z
z
71
0-9
31
32
12-0
72
Tab * 0
*®
72
Cl-8-2
32
33
12-8-3
73
73
0-8-3
33
34
12-8-4
74
74
0-8-4
34
Backspace?0
Il or)
0
35
12-8-5
75
<
36
12-8-6
76
• Stop
37
12-8-7
77
NOTES:
o
@
CD
0
The characters? ! and
* are for input only.
% or (
\
4
1662
1607
1615
1623
1631
1639
1647
1655
1663
3500
3510
3520
3530
3540
3550
3560
3570
1856
1864
1872
1880
1888
1896
1904
1912
1857
1865
1873
1881
1889
1897
1905
1913
1858
1866
1874
1882
1890
1898
1906
1914
1859
1867
1875
1883
1891
1899
1907
1915
1860
1868
1876
1884
1892
1900
1908
1916
1861
1869
1877
1885
1893
1901
1909
1917
1862
1870
1878
1886
1894
1902
1910
1918
18'53
1871
1879
1887
1895
1903
1911
1919
1665
1673
1681
1689
1697
1705
1713
1721
1666
1674
1682
1690
1698
1706
1714
1722
1667
1675
1683
1691
1699
1707
1715
1723
1668
1676
1684
1692
1700
1708
1716
1724
1669
1677
1685
1693
1701
1709
1717
1725
1670
1678
1686
1694
1702
1710
1718
1726
1671
1679
1687
1695
1703
1711
1719
1727
3600
3610
3620
3630
3640
3650
3660
3670
1920
1928
1936
1944
1952
1960
1968
1976
1921
1929
1937
1945
1953
1961
1969
1977
1922
1930
1938
1946
1954
1962
1970
1978
1923
1931
1939
1947
1955
1963
1971
1979
1924
1932
1940
1948
1956
1964
1972
1980
1925
1933
1941
1949
1957
1965
1973
1981
1926
1934
1942
1950
1958
1966
1974
1982
1927
1935
1943
1951
1959
1967
1975
1983
1729
1737
1745
1753
1761
1769
1777
1785
1730
1738
1746
1754
1762
1770
1778
1786
1731
1739
1747
1755
1763
1771
1779
1787
1732
1740
1748
1756
1764
1772
1780
1788
1733
1741
1749
1757
1765
1773
1781
1789
1734
1742
1750
1758
1766
1774
1782
1790
1735
1743
1751
1759
1767
1775
1783
1791
3700
3710
3720
3730
3740
3750
3760
3770
1984
1992
2000
2008
2016
2024
2032
2040
1985
1993
2001
2009
2017
2025
2033
2041
1986
1994
2002
2010
2018
2026
2034
2042
1987
1995
2003
2011
2019
2027
2035
2043
1988
1996
2004
2012
2020
2028
2036
2044
1989
1997
2005
2013
2021
2029
2037
2045
1990
1998
2006
2014
2022
2030
2038
2046
1991
1999
2007
2·015
2023
2031
2039
2047
0
1
2
3
4
5
6
7
2000
2010
2020
2030
2040
2050
2060
2070
1024
1032
1040
1048
1056
1064
1072
1080
1025
1033
1041
1049
1057
1065
1073
1081
1026
1034
1042
1050
1058
1066
1074
1082
1027
1035
1043
1051
1059
1067
1075
1083
1028
1036
1044
1052
1060
1068
1076
1084
1029
1037
1045
1053
1061
1069
1077
1085
1030
1038
1046
1054
1062
1070
1078
1086
1031
1039
1047
1055
1063
1071
1079
1087
2100
2110
2120
2130
2140
2150
2160
2170
1088
1096
1104
1112
1120
1128
1136
1144
1089
1097
1105
1113
1121
1129
1137
1145
1090
1098
1106
1114
1122
1130
1138
1146
1091
1099
1107
1115
1123
1131
1139
1147
1092
1100
1108
1116
1124
1132
1140
1148
1093
1101
1109
1117
1125
1133
1141
1149
1094
1102
1110
1118
1126
1134
1142
1150
2200
2210
2220
2230
2240
2250
2260
2270
1152
1160
1168
1176
1184
1192
1200
1208
1153
1161
1169
1177
1185
1193
1201
1209
1154
1162
1170
1178
1186
1194
1202
1210
1155
1163
1171
1179
1187
1195
1203
1211
1156
1164
1172
1180
1188
1196
1204
1212
1157
1165
1173
1181
1189
1197
1205
1213
2300
2310
2320
2330
2340
2350
2360
2370
1216
1224
1232
1240
1248
1256
1264
1272
1217
1225
1233
1241
1249
1257
1265
1273
1218
1226
1234
1242
1250
1258
1266
1274
1219
1227
1235
1243
1251
1259
1267
1275
1220
1228
1236
1244
1252
1260
1268
1276
0
1
2
3
3000
3010
3020
3030
3040
3050
3060
3070
1536
1544
1552
1560
1568
1576
1584
1592
1537
1545
1553
1561
1569
1577
1585
1593
1538
1546
1554
1562
1570
1578
1586
1594
3100
3110
3120
3130
3140
3150
3160
3170
1600
1608
1616
1624
1632
1640
1648
1656
1601
1609
1617
1625.
1633
1641
1649
1657
1664
1672
1680
1688
1696
1704
3~60 1712
3270 1720
3300
3310
3320
3330
3340
3350
3360
3370
3200
3210
3220
3230
3240
3250
1728
1736
1744
1752
1760
1768
1776
1784
A-4
2000
1024
to
to
2777
1535
(Octal)
(Decimal)
Octal
Decimal
10000· 4096
20000· 8192
30000· 12288
40000 - 16384
50000 • 20480
60000 • 24576
·70000 • 28672
3000
1536
to
to
3777
2047
(Octal)
(Decimal)
Octal-Decimal Integer Conversion Table
4000
2048
to
10
4777
2559
(Oclol)
tDecimal!
Octal Decimal
10000· 4096
20000· 8192
30000 • 12288
40000 • 16384
50000 • 20480
60000·24576
70000 • 28672
0
1
2
3
4
5
6
7
2305
2313
2321
2329
2337
2345
2353
2361
2306
2314
2322
2330
2338
2346
2354
2362
2307
2315
2323
2331
2339
2347
2355
2363
2308
2316
2324
2332
2340
2348
2356
2364
2309
2317
2325
2333
2341
2349
2357
2365
2310
2318
2326
2334
2342
2350
2358
2366
2311
2319
2327
2335
23<43
2351
2359
2367
2119
2127
2135
2143
2151
2159
2167
2175
4500 2368 2369 2370
4510 2376 2377 2378
4520 2384 2385 2386
4~30 2392 2393 2394
4540 2400 2401 2402
4550 2408 2409 2410
4560 2416 2417 2418
4570 2424 2425 2426
2371
2379
2387
2395
2403
2411
2419
2427
2372
2380
2388
2396
2404
2412
2420
2428
2373
2381
2389
2397
2405
2413
2421
2429
2374
2382
2390
2398
2406
2414
2422
2430
2375
2383
2391
2399
2407
2415
2423
2431
2182
2190
2198
2206
2214
2222
2230
2238
2183
2191
2199
2207
2215
2223
2231
2239
4600
4610
4620
4630
4640
4650
4660
4670
2246
2254
2262
2270
2278
2286
2294
2302
2247
2255
2263
2271
2279
2287
2295
2303j
0
1
2
3
4
5
6
7
4000
4010
4020.
4030
4040
4050
4060
4070
2048
2056
2064
2072
2080
2088
2Q96
2104
2049
2057
2065
2073
2081
2089
2097
2105
2050
2058
2066
2074
2082
2090
2098
2106
2051
2059
2067
2075
2083
2091
2099
2107
2052
2060
2068
2076
2084
2092
2100
2108
2053
2061
2069
2077
2085
2093
2101
2109
2054
2002
2070
2078
2086
2094
2102
2110
2055
2063
2071
2079
2087
2095
2103
2111
4400 2304
4410 2312
4420 2320
4430 2328
4440 2336
445012344
4460 2352
4470 2360
4100
4110
4120
4130
4140
4150
4160
4170
2112
2120
2128
2136
2144
2152
2160
2168
2113
2121
2129
2137
2145
2153
2161
2169
2114
2122
2130
2138
2146
2154
2162
2170
2115
2123
2131
2139
2147
2155
2163
2171
2116
2124
2132
2140
2148
2156
2164
2172
2117
2125
2133
2141
2149
2157
2165
2173
2118
2126
2134
2142
2150
2158
2166
2174
4200
4210
4220
4230
4240
4250
4260
4270
2176
2184
2192
2200
2208
2216
2224
2232
2177
2185
2193
2201
2209
2217
2225
2233
2178
2186
2194
2202
2210
2218
2226
2234
2179
2187
2195
2203
2211
2219
2227
2235
2180
2188
2196
2204
2212
2220
2228
2236
2181
2189
219';'
2205
2213
2221
2229
2237
4300
4310
4320
4330
4340
4350
4360
4370
2240
2248
2256
2264
2272
2280
2288
2296
2241
2249
2257
2265
2273
2281
2289
2297
2242
2250
2258
2266
2274
2282
2290
2298
2243
2251
2259
2267
2275
2283
2291
2299
2244
2252
2260
2268
2276
2284
2292
2300
2245
2253
2261
2269
2277
2285.
2293
2301
-
2432
2440
2448
2456
2464
2472
2480
2488
2433
2441
2449
2457
2465
2473
2481
2489
2434
2442
2450
2458
2466
2474
2482
2490
2435
2443
2451
2459
24,67
2475
2483
2491
2436
2444
2452
2460
2468
2476
2184
2492
2437
2445
2453
2461
2469
2477
2485
2493
2438
2446
2454
2462
2470
2478
2486
2494
2439
2447
2455
4700 2.496
4710 2504
4720 2512
4730 2520
474012528
4750 2536
4760,2544
14770! 2552
2497
2505
2513
2521
2529
2537
2545
2553
2498
2506
2514
2522
2530
2538
2546
2554
2499
2507
2515
2523
2531
2539
2547
2555
2500
2508
2516
2524
2532
2540
2548
2556
2501
2509
2517
2525
2533
2541
2549
2557
2502
2510
2518
2526
2534
2542
2550
2558
2503
2511
2519
2527
2535
2543
2551
2559
1
2
3
4
5
6
7
24~3
2471
2479
2487
2495
---'1
0
5000
2560
to
to
5777
3071
(Oclol)
(Decimol)
2
3
4
5
6
7
I
5000
5010
5020
5030
5040
5050
5060
5070
2560
2568
2576
2584
2592
2600
2608
2616
2561
2569
2577
2585
2593
2601
2609
2617
2562
2570
2578
2586
2594
2602
2610
2618
2563
2571
'2579
2587
2595
2603
2611
2619
2564
2572
2580
2588
2596
2604
2612
2620
2565 2566 25671
2573 2574 2575
2581 25~2 2583
258~ 2590 2591
2597 2598 2599
2605 2606 2607 1
2613 2614 2615
~21 2622 2623
5100
5110
5120
5130
5140
5150
5160
5170
2624
2632
2640
2648
2656
2664
2672
2680
2625
2633
2641
2649
2657
2665
2673
2681
2626
2634
2642
2650
2658
2666
2674
2682
2627
2635
2643
2651
2659
2667
2675
2683
2628
2636
2644
2652
2660
2668
2676
2684
2629
2637
2645
2653
2661
2669
2677
2685
2630
2638
2646
2654
2662
2670
2678
2686
2631
2639
2647
2655
2663
2671
2679
2687
5200 2688
5210 2696
522012704
5230\2712
5240,2720
5250 ! 2728
5260 2736
5270 2744
2689
2697
2705
2713
2721
2729
2737
2745
2690
2698
2706
2714
2722
2730
2738
2746
2691
2699
2707
2715
2723
2731
2739
2747
2692
2700
2708
2716
2724
2732
2740
2748
2693
2701
2709
2717
2725
2733
2741
2749
2694
2702
2710
2718
2726
2734
2742
2750
5300
5310
5320
5330
5340
5350
5360
5370
2753
2761
2769
2777
2785
2793
2801
2809
2754
2762
2770
2778
2786
2794
2802
2810
2755
2763
2771
2779
2787
2795
2803
2811
2756
2764
2772
2780
2788
2796
2804
2812
2757
2765
2773
2781
2789
2797
2805
2813
2758
2766
2774
2782
2790
2798
2806
2814
2752
2760
2768
2776
2784
2792
2800
2808
A-5
0
540012816 2817 2818 2819 2820 2821 2822 2823
54101282' 2825 2826 2827 2828 2829 2830 2831
5420
5430
5440
5450
5460
5470
2832
2840
2848
2856
2864
2872
2'333
2841
2849
2857
2865
2873
2834
2842
2850
2858
2866
2874
2835
2843
2851
2859
2867
2875
2836
2844
2852
2860
2868
2876
2837
2845
2853
2861
2869
2877
2838
2846
2854
2862
2870
2878
2839
2847
2855
2863
2871
287U
5500
5510
5520
5530
5540
5550
5560
5570
2880
2888
2896
2904
2912
2920
2928
2936
2881
2889
2897
2905
2913
2921
2929
2937
2882
2890
2898
2906
2914
2922
2930
2938
2883
2891
2899
2907
2915
2923
2931
2939
2884
2892
2900
2908
2916
2924
2932
2940
2885
2893
2901
2909
2917
2925
2933
2941
2886
2894
2902
2910
2918
2926
2934
2942
288"/
2895
2903
2911
2919
2927
2935
2943
2695
2703
2711
2719
2727
2735
2743
2751
5600 2944
-5610 12952
562012960
5630 2968
564012976
5650 2984
5660 2992
5670 3000
2945
2953
2961
2969
2977
2985
2993
3001
2945
2954
2962
2970
2978
2986
2994
3002
2947
2955
2963
2971
2979
2987
2995
3003
2948
2956
2964
2972
2980
2988
2996
3004
2949
2957
2965
2973
2981
2989
2997
3005
2950
2958
2966
2974
2982
2990
2998
3006
2951
2959
2967
2975
2983
2991
2999
3007
2759
2767
2775
2783
2791
2799
2807
2815
5710
5720
5730
5740
5750
5760
5770
3008
3016
3024
3032
3040
3048
3056
3064
3009
3017
3025
3033
3041
3049
3057
3065
3010
3018
3026
3034
3042
3050
3058
3066
3011
3019
3027
3035
3043
3051
3059
3067
3012
3020
3028
3036
3044
3052
3060
3068
3013
3021
3029
3037
3045
3053
3061
3069
3014
3022
3030
3038
3046
3054
3062
3070
3015
3023
3031
3039
3047
3055
3063
3071
~700
Octal-Decimal Integer Conversion Table
1
2
3
4
5
6
7
3328
3336
3344
3352
3360
3368
3376
3384
3329
3337
3345
3353
3361
3369
3377
3385
3330
3338
3346
3354
3362
3370
3378
3386
3331
3339
3347
3355
3363
3371
3379
3387
3332
3340
3348
3356
3364
3372
3380
3388
3333
3341
3349
3357
3365
3373
3381
3389
3334
3342
3350
3358
3366
3374
3382
3390
3335
3343
3351
3359
3367
3375
3383
3391
6500 3392
6510 3400
652013408
6530 3416
6540 3424
6550 3432
6560 3440
6570 3448
3393
3401
3409
3417
3425
3433
3441
3449
3394
3402
3410
3418
3426
3434
3442
3450
3395
3403
3411
3419
3427
3435
3443
3451
3396
3404
3412
3420
3428
3436
3444
3452
3397
3405
3413
3421
3429
3437
3445
3453
3398
3406
3414
3422
3430
3438
3446
3454
3399
3407
3415
3423
3431
3439
3447
3455
16200 3200 3201 3202 3203 3204 3205 3206 3207
3208
3216
3224
3232
3240
3248
3256
3209
3217
3225
3233
3241
3249
3257
3210
3218
3226
3234
3242
3250
3258
3211
3219
3227
3235
3243
3251
3259
6600
6610
6620
6630
6640
6650
6660
6.670
3456
3464
3472
3480
3488
3496
3504
3512
3457
3465
3473
3481
3489
3497
3505
3513
3458
3466
3474
3482
3490
3498
3506
3514
3459
3467
3475
3483
3491
3499
3507
3515
3460
3468
3476
3484
3492
3500
3508
3516
3461
3469
3477
3485
3493
3501
3509
3517
3462
3470
3478
3486
3494
3502
3510
3518
3463
3471
3479
3487
3495
3503
3511
3519
6300 3264
6310 3272
6320 3280
6330 3288
6340 3296
6350 3304
636013312
6370 3320
3265
3273
3281
3289
3297
3305
3313
3321
3266
3274
3282
3290
3298
3306
3314
3322
6700
6710
6720
6730
6740
6750
6760
6770
3520
3528
3536
3544
3552
3560
3568
3576
3521
3529
3537
3545
3553
3561
3569
3577
3522
3530
3538
3546
3554
3562
3570
3578
3523
3531
3539
3547
3555
3563
3571
3579
3524
3532
3540
3548
3556
3564
3572
3580
3525
3533
3541
3549
3557
3565
3573
3581
3526
3534
3542
3550
3558
3566
3574
3582
3527
3535
3543
3551
3559
3567
3575
3583
a
1
0
1
2
3
4
5
6
7
7000
7010
7020
7030
7040
7050
7060
7070
3584
3592
3600
3608
3616
3624
3632
3640
7100
7110
7120
7130
7140
7150
7160
7170
3648
3656
3664
3672
3680
3688
3696
3704
0
0
1
2
3
4
5
6
7
3072
3080
3088
3096
3104
3112
3120
3128
3073
3081
3089
3097
3105
3113
3121
3129
3074
3082
3090
3098
3106
3114
3122
3130
3075
3083
3091
3099
3107
3115
3123
3131
3076
3084
3092
3100
3108
3116
3124
3132
3077
3085
3093
3101
3109
3117
3125
3133
3078
3086
3094
3102
3110
3118
3126
3134
3079
3087
3095
3103
3111
3119
3127
3135
6400
6410
6420
6430
6440
6450
6460
6470
6100 3136
6110 i 3144
612013152
6130,3160
6140 3168
6150 3176
6160 3184
6170 3192
3137
3145
3153
3161
3169
3177
3185
3193
3138
3146
3154
3162
3170
3178
3186
3194
3139
3147
3155
3163
3171
3179
3187
3195
3140
3148
3156
3164
3172
3180
3188
3196
3141
3149
3157
3165
3173
3181
3189
3197
3142
3150
315B
3166
3174
3182
3190
3198
3143
3151
3159
3167
3175
3183
3191
3199
6000
6010
6020
6030
6040
6050
6060
6070
06210
6220
6230
6240
6250
6260
6270
3213
3221
3229
3237
3245
3253
3261
3214
3222
3230
3238
3246
3254
3262
3215
3223
3231
3239
3247
3255
3263
3267
3275
3283
3291
3299
3307
3315
3323
3212
3220
3228
3236
3244
3252
3260
0
3268
3276
3284
3292
3300
3308
3316
3324
3269
3277
3285
3293
3301
3309
3317
3325
3270
3278
3286
3294
3302
3310
3318
3326
3271
3279
3287
3295
3303
3311
33191
2
3
4
5
6
7
3585
3593
3601
3609
3617
3625
3633
3641
3586
3594
3602
3610
3618
3626
3634
3642
3587
3595
3603
3611
3619
3627
3635
3643
3588
3596
3604
3612
3620
3628
3636
3644
3589
3597
3605
3613
3621
3629
3637
3645
3590
3598
3606
3614
3622
3630
3638
3646
3591
3599
3607
3615
3623
3631
3639
3647
7400
7410
7420
7430
7440
7450
7460
7470
3840
3848
3856
3864
3872
3880
3888
3896
3841
3.849
3857
3865
3873
3881
3889
3897
3842
3850
3858
3866
3874
3882
3890
3898
3843
3851
3859
3867
3875
3883
3891
38il9
3844
3852
3860
3868
3876
3884
3892
3900
3845
3853
3861
3869
3877
3885
3893
3901
3846
3854
3862
3S70
3878
3886
3894
3902
3847
3855
3863
3871
3879
3887
3895
3903
3649
3657
3665
3673
3681
3689
3697
3705
3650
3658
3666
3674
3682
3690
3698
3706
3651
3659
3667
3675
3683
3691
3699
3707
3652
3660
3668
3676
3684
3692
3700
3708
3653
3661
3669
3677
3685
3693
3701
3709
3654
3662
3670
3678
3686
3694
3702
3710
3655
3663
3671
3679
3687
3695
3703
3711
7500
7510
7520
7530
7540
7550
7560
7570
3904
3912
3920
3928
3936
3944
3952
3960
3905
3913
3921
3929
3937
3945
3953
3961
3906
3914
3922
3930
3938
3946
3954
3962
3907
3915
3923
3931
3939
3947
3955
3963
3908
3916
3924
3932
3940
3948
3956
3964
3909
3917
3925
3933
3941
3949
3957
3965
3910
3918
3926
3934
3942
3950
3958
3966
3911
3919
3927
3935
3943
3951
3959
3967
7200
7210
7220
7230
7240
7250
3712
3720
3728
3736
37044
3752
7260 :1750
7270 3168
3713 3714 3715
3721 3722 3723
3q29 3730 3731
3737 3738 3739
3745 3746 374'1
3753 3754 3755
3761 3762 3763
3769 3770 3771
3716
3724
3732
3740
3748
3756
3764
3772
3717
3725
3733
3741
3149
3757
3765
3773
3718
3726
3734
3'742
3750
3758
3766
3774
3719
3727
3735
3743
3751
3759
3767
3775
7600
7610
7620
7630
7640
7650
7660
7670
3968
3976
3984
3992
4000
4008
4016
4024
3969
3977
3985
3993
4001
4009
4017
4025
3970
3978
3986
3994
4002
4010
4018
4026
3971
3979
3987
3995
4003
4011
4019
4027
3972
3980
3988
3996
4004
4012
4020
4028
3973
3981
3989
3997
4005
4013
4021
4029
3974
3982
3990
3998
4006
4014
\022
4030
3975
3983
3991
3999
4007
4015
4023
4031
7300
7310
7320
7330
3777
3785
3793
3801
3809
3817
3825
3833
3780
3788
3796
3804
3812
3820
3828
3836
3781
3789
3797
3805
3813
3821
3829
3837
3782
3790
3798
3806
3814
3822
3830
3838
3783
3791
3799
3807
3815
3823
3831
3839
7700
7710
7720
7730
7740
7750
7760
7770
4032
4040
4048
4056
4064
4072
4080
4088
4033
4041
4049
4057
4065
4073
4081
4089
4034
4042
4050
4058
4066
4074
4082
4090
4035
4043
4051
4059
4067
4075
4083
4091
4036
4044
4052
4060
4068
4076
4084
4092
4037
4045
4053
4061
4069
4077
4085
4093
4038
4046
4054
4062
4070
4078
4086
4094
4039
4047
4055
4063
4071
4079
4087
4095
3776
3784
3792
3800
~340 3808
73)0 3816
7360 3824
7370 3832
3778
3786
3794
3802
3810
3818
3826
3834
3779
3787
3795
3803
3811
3819
3827
3835
3~
A-6
6000
to
6777
(Octal)
I
3072
to
3583
I (Decimal)
Octal Decimal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
7000
3584
to
10
7777
4095
(Octal)
(Decimal)
OCTAL· DECIMAL FRACTION CONVERSION TABLE
'OCTAL
DEC.
OCTAL
Dl::C.
OCTAL
DEC.
OCTAL
m:c.
.000
.001
.002
.003
.004
.005
.006
.007
.010
.011
.012
.013
.014
.015
.016
.017
.020
.021
.022
.023
.024
.025
.026
.027
.030
.031
.032
.033
.034
.035
.036
.037
.040
.041
.042
.043
.044
.045
.046
.047
.050
.051
.052
.053
.054
.055
.056
.057
.060
.061
.062
.063
.064
.065
.066
.067
.070
.071
.072
.073
.074
.075
.076
.077
.000000
.001953
.1t03906
.005859
.007812
.009765
.011718
.013671
.015625
.017578
.019531
.021484
.023437
.025390
.027343
.029296
.031250
.033203
.035156
.037109
.039062
.041015
.042968
.044921
.046875
.048828
.050781
.052734
.054687
.056640
.058593
.060546
.062500
.064453
.066406
.068359
.070312
.072265
.074218
.076171
.078125
.080018
.082031
.083984
.085937
.087890
.089843
.091796
.093750
.095703
.097656
.099609
.101562
.103515
.105468
.107421
.109375
.111328
.113281
.115234
.117187
.119140
.121093
.123046
.100
.101
.102
.103
.104
.105
.106
.107
.110
.111
.112
.113
.114
.115
.116
.117
.120
.121
.122
.123
.124
.125
.126
.127
.130
.131
.132
.133
.134
.135
.136
.137
.140
.141
.142
.143
.144
.145
.146
.147
.150
.151
.152
.153
.154
.155
.156
.157
.160
.161
.162
.163
.164
.165
.166
.167
.170
.171
.172
.173
.174
.175
.176
.177
.125000
.126953
.128906
.130859
.132812
.134765
.136718
.138671
.140625
.142578
.144531
.146484
.148437
.150390
.152343
.154296
.156250
.158203
.160156
.162109
.164062
.166015
.167968
.169921
.171875
.173828
.175781
.177734
.179687
.181640
.183593
.185546
.187500
.189453
.191406
.193359
.195312
.197265
.199218
.201171
.203125
.205078
.207031
.208984
.210937
.212890
.214843
.216796
.218750
.220703
.222656
.224609
.226562
.228515
.230468
.232421
.234375
.236328
.238281
.240234
.242187
.244140
.246093
~ 248046
.200
.201
.202
.203
.204
.205
.206
.207
.210
.2ll
.212
.213
.214
.215
.216
.217
.220
.221
.222
.223
.224
.225
.226
.227
.230
.231
.232
.233
.234
.235
.236
.237
.240
.241
.242
.243
.244
.245
.246
.247
.250
.251
.252
.253
.254
.255
.256
.257
.260
.261
.262
.263
.264
.265
.266
.267
.270
.271
.272
.273
.274
.275
.276
.277
.250000
.251953
.253906
.255859
.257812
.259765
.261718
.263671
.265625
.267578
.269531
.271484
.273437
.275390
.277343
.279296
.281250
.283203
.285156
.287109
.289062
.291015
.29296'8
.294921
.296875
.298828
.300781
.302734
.304687
.306640
.308593
.310546
.312500
.314453
.316406
.318359
.320312
.322265
.324218
.326171
.328125
.330078
.332031
.333984
.335937
.337890
.339843
.341796
.343750
.345703
.347656
.349609
.351562
.353515
.355468
.357421
.359375
.361328
.363281
.365234
.367187
.369140
.371093
.373046
.300
.301
.302
.303
.304
.305
.306
.307
.310
.311
.312
.313
.314
.315
.316
.317
.320
.321
.322
.323
.324
.375000
• 37G953
.378906
.380859
.382812
.384765
.386718
.388671
.390625
.392578
.394531
.396484
.398437
.400390
.402343
.404296
.406250
.408203
.410156
.412109
.414062
.416015
.417968
.419921
.421875
.423828
.425781
.427734
.. 429687
.431640
.433593
.435546
.437500
.439453
.441406
.443359
.445312
.447265
.449218
.451171
.453125
.455078
.457031
.458984
.460937
.462890
.464843
.466"196
.468750
.470703
.472656
.474609
.416562
.478515
.460468
.482421
.484375
.486328
.48821\1
.490234
.492187
.494140
.496093
.498046
..
'
A-7
.~25
.326
.327
.330
.331
.332
.333
.334
.335
.336
.337
.340
.341
.342
.343
.344
.345
.346
.347
.350
.351
.352
.353
.354
.355
.356
.357
.360
.361
.362
.363
.364
.365
.366
.367
.370
.371
.372
.373
.374
.375
.376
.377
Octal-Decimal Fraction Conversion Table
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC •
• 000000
.000001
.000002
.000003
,000004
.000005
.000006
.000007
.000010
.000011
.000012
.000013
.000014
.000015
.000016
.000017
.000020
.000021
.000022
,000023
.000024
.000025
.000026
.000027
.000030
.000031
.000032
.000033
.000034
.000035
.000036
.000037
.000040
.000041
.000042
.000043
.000044
.000045
.000046
.000047
.000050
.000051
.000052
.000053
.000054
.000055
.000056
.000057
.000060
.000061
.000062
.000063
.000064
.000065
.000066
.000067
.000070
.000071
.000072
.000073
.000074
.000075
.000076
.000077
.000000
.000003
,000007
.000011
.000015
.000019
.000022
.000026
.000030
.000034
.000038
.000041
.000045
.000049
.000053
• QOO057
.000061
.000064
.000068
.000072
.000076
.000080
.000083
.000087
.000091
.000095
.000099
.000102
.000106
.000110
.000114
.000118
.000122
.000125
.000129
.000133
.000131
.000141
.000144
.000148
.000152
.000156
.000160
.000164
.000167
.000171
.000175
.000179
.000183
.000186
.000190
.000194
.000198
.000202
.000205
.000209
.000213
.000217
.000221
.000225
.000228
.000232
.000236
.000240
.000100
.000101
.000102
.000103
.000104
.000105
.000106
.000107
,000110
.000111
.000112
.000113
.000114
.000115
.000116
.000117
,000120
.000121
.000122
,000123
.000124
.000125
.000126
.000127
.000130
,000131
.000132
.000133
.000134
.000135
.000136
.000137
.000140
.000141
.000142
.000143
.000144
.000145
.000146
.000147
.000150
.000151
.000152
.000153
.000154
.000155
.000156
.000157
.000160
.000161
.000162
.000163
.000164
.000165
.000166
.000167
.000170
.000171
.000172
.000173
.000174
.000175
.000176
.000177
.000244
.000247
.000251
.000255
.000259
.000263
.000267
.000270
.000274
.000278
.000282
.000286
.000289
.000293
.000297
.000301
.000305
.000308
.000312
,000316
.000320
.000324
,000328
.000331
.000335
.000339
.000343
.000347
.000350
.000354
.000358
.000362
.000366
.000370
.000373
.000371
.000381
.000385
,000389
.000392
,000396
.000400
.000404
,000408
.000411
.000415
.000419
.000423
.000427
.000431
.000434
.000438
.000442
.000446
.000450
.000453
.000457
.000461
.000465
.000469
.000473
.000476
.000480
.000484
.000200
.000201
.000202
.000203
.000204
.000205
.000206
.000207
.000210
.000211
.000212
.000213
.000214
.000215
.000216
.000217
.000220
.000221
,000222
,000223
.000224
.000225
.000226
,000227
.000230
.000231
.000232
.000233
.000234
.000235
.000236
.000237
.000240
.000241
.000242
.000243
.000244
,000245
,000246
.000247
.000250
.000251
.000252
.000253
.000254
.000255
.000256
.000257
.000260
.000261
.000262
.000263
.000264
.000265
.000266
.000267
.000270
.000271
.000272
.000273
.000274
.000275
.000276
.000277
.000488
.000492
.000495
.000499
.000503
.000507
.000511
.000514
.000518
.000522
.000526
.000530
.000534
.000537
.000541
.000545
.000549
.000553
.000556
.000560
.000564
.000568
.000572
.000576
.000579
.000583
.000587
.000591
.000595
.000598
.000602
.000606
.000610
.000614
.000617
.000621
.000625
.000629
.000633
.000637
.000640
.000644
.000648
.000652
.000656
.000659
.000663
.000667
,000671
.000675
.000679
.000682
.000686
.000690
.000694
.000698
.000701
.000705
.000709
.000713
.000717
.000720
.000724
.000728
.000300
.000301
.000302
.000303
.000304
.000305
.000306
.000307
.000310
.000311
.000312
.000313
.000314
.000315
.000316
.000317
.000320
.000321
.000322
.000323
.000324
.000325
.000326
.000327
.000330
.000331
.000332
.000333
.000334
.000335
.000336
.000337
.000340
.000341
.000342
.000343
.000344
.000345
.000346
.000347
.000350
.000351
.000352
.000353
.000354
.000355
.000356
.000357
.000360
.000361
.000362
.000363
.000364
.000365
.000366
.000367
.000370
.000371
.000372
.000373
.000374
.000375
.000376
.000377
.000732
.000736
.000740
.000743
.000747
.000751
.000755
.000759
.000762
.000766
.000770
.000774
.000778
.000782
.000785
.000789
.000793
.000797
.000801
.000805
.000808
.000812
.000816
.000.820
.000823
.000827
.000831
.000835
.000839
.000843
.000846
.000850
.000854
.000858
.000862
.000865
.000869
.000873
.000877
.000881
.000885
.000888
.OG0892
.000896
.000900
.000904
.000907
.000911
.000915
.000919
.000923
.000926
.000930
.000934
.000938
.000942
.000946
.000949
.000953
.000957
.000961
.000965
.000968
.000972
A-a
Octal-Decimal Fradion Conversion Table
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
.000400
.000401
.000402
.000403
.000404
.000405
.000406
.000407
.000410
.000411
.000412
.000413
.000414
.000415
.000416
.000417
.000976
.000980
.000984
.000988
.000991
.000995
.000999
.001003
.001007
.001010
.001014
.001018
.001022
.001026
.001029
.001033
.000500
.000501
.000502
.000503
.000504
.000505
.000506
.000507
.000510
.000511
.000512
.000513
.000514
.000515
.000516
.000517
.001220
.001224
.00122-8
.001232
.001235
.001239
.001243
.001247
.001251
.001255
.001258
.001262
.001266
.001270
.001274
.001277
.000600
.000601
.00060'2
.000603
.000604
.000605
.000606
.000607
.000610
.000611
.000612
.000613
.000614
.000615
.000616
.000617
.001464
.001468
.001472
.001476
.001480
.001483
.001487
.001491
.001495
.001499
.001502
.001506
.001510
.001514
.• 001518
.001522
.000700
.000701
.000702
.000703
.000704
.000705
.000706
.000707
.000710
.000711
.000712
.000713
.000714
.000715
.000716
.000717
.001708
.001712
.001716
.001720
.001724
.001728
.001731
.001735
.001739
.001743
.001747
.001750
.001754
.001758
.001762
.001766
.000420
.000421
.000422
.000423
.000424
.000425
.000426
.000427
.000430
.000431
.000432
.000433
.000434
.000435
.000436
.000437
.000440
.000441
.000442
.000443
.000444
.000446
.000446
.000447
.000450
.000451
.000452
.000453
.000454
.000455
.000456
.000457
.000460
.000461
.000462
.000463
.000464
.000465
.000466
.000467
.000470
.000471
.000472
.000473
.000474
.000475
.000476
.000477
.001037
.001041
.001045
.001049
.001052
.001056
.001060
.001064
.001068
.001071
.001075
.001079
.001083
.001087
.001091
.001094
.001098
.001102
.001106
.001110
.001113
.001117
.001121
.001125
.001129
.001132
.001136
.001140
.001144
.001148
.001152
.001155
.001159
.001163
.001167
.001171
.001174
.001178
.001182
.001186
.001190
.001194
.001197
.001201
.001205
.001209
.001213
.001216
.000520
.000521
.000522
.000523
.000524
.000525
.000526
.000527
.000530
.000531
.000532
.000533
.000534
.000535
.000536
.000537
.000540
.000541
.000542
.000543
.000544
.000545
•• 000546
.000547
.000550
.000551
.000552
.000553
.000554
.000555
.000556
.000557
.000560
.000561
.000562
.000563
.000564
.000565
.000566
.000567
.000570
.000571
.000572
.000573
.000574
.000575
.000576
.000577
.001281
.001285
.001289
.001293
.001296
.001300
.001304
.001308
.001312
.001316
.001319
.001323
.001327
.001331
.001335
.001338
.001342
.001346
.001350
.0'01354
.001358
.001361
.001365
.001369
.001373
.001377
.001380
.001384
.001388
.001392
.001396
.001399
.001403
.001407
.001411
.001415
.001419
.001422
.001426
.001430
.001434
.001438
.001441
.001445
.001449
.001453
.001457
.001461
.000620
.000621
.000622
.000623
.000624
.000625
.000626
.000627
.000630
.000631
.000632
.000633
.000634
.000635
.000636
.000637
.000640
.000641
.000642
.000643
.000644
.000645
.000646
.000647
.000650
.000651
.000652
• QO{)653
.000654
.000655
.00'0656
.000657
.000660
.000661
.000662
.000663
.000664
.000665
.000666
.000667
.000670
.000671
.000672
.000673
.000674
.000675
.000676
.000677
.001525
.001529
.001533
.001537
.001541
.001544
.001548
.001552
.001556
.001560
.001564
.001567
.001571
.001575
.001579
.001583
.001586
.001590
.001594
.001598
.001602
.001605
.001609
.001613
.001617
.001621
.001625
.001628
.001632
.001636
.001640
.001644
.001647
.001651
.001655
.001659
.001663
.001667
.001670
.001674
.001678
.001682
.001686
.001689
.001693
.001697
.0017.Dl
.001705
.000720
.000721
.000722
.000723
.000724
.000725
.000726
.000727
.000730
.000731
.000732
.000733
.000734
.000735
.000736
.000737
.000740
.000741
.000742
.000743
.000744
.000745
.000746
.000747
.000750
.000751
.000752
.000753
.000754
.000755
.000756
.000757
.000760
.000761
.000762
.000763
.000764
.000765
.000766
.000767
.000770
.00.0771
.000772
.000773
.000774
.000775
.000776
.000777
.001770
.001773
.001777
.001781
.001785
.0017t19
.001792
.001796
.001800
.001804
.001808
.0018ll
.001815
.001819
.001823
.001827
.001831
.001834
.001838
.001842
.001846
.001850
.001853
.001857
.001861
.001865
.001869
.001873
.001876
.001880
.001884
.001888
.001892
.001895
.001899
.001903
.001907
.001911
.001914
.001918
.001922
.001926
.001930
.001934
.001937
.001941
.001945
.001949
A-9
TWO'S COMPLEMENT ARITHMETIC
SDS computer systems hold numbers in memory in two's complement form. Single-precision numbers have 23 magnitude bits
and a sign bit. The sign bit is in the first bit position to the
left of the most significant of the magnitude bits. Thus, the
sign bit actually is a part of the number in all arithmetic operations. A "0" bit denotes a positive sign and a 11111 bit denotes
a negative sign. In this system, the negative of a number is its
two's complement.
As the examples indicate, the sign bit is an integral part of
the number to which it is attached and its value, plus or minus,
is automatically taken care of during the use of two's complement arithmetic. This property is used when numbers of different length are added. For example, assume that these two
signed, two's complemented, negative numbers of 6-bit at.1d
3-bit length are added:
Decimal
An algorithm for finding the two's complement of a binary number with attached sign bit is:
To find the two's complement of the binary number B
that has.!l significant bits including the sign bit, subtract
it from the number 2 n expressed in binary form. This
latter number is a "1 11 followed by nzeros.
EXAMPLES:
The following example indicates the two's complement
of binary numbers held in five bits plus a sign bit.
Their decimal equivalents are on the left.
Decimal
Binary
Number Equivalent
000010
- 2
111110
+14
001110
-14
110010
101011
101
-24
11 0000 = - 16 10
Notice that the third least significant bit of the first number
is added to the sign bit of the second number causing an erroneous result. This error is corrected by filling in the empty,
most significant bit positions with the value of the sign bit of
the shorter number:
Negative of
Two's Complement
Decimal Number of Binary Equivalent
,+ 2
-21
-03
Decimal
Binary
-21
-03
101011
111101
-24
101000
= -24 10
Th is property suggests:
In the addition example below, decimal notation is on
the left and binary notation on the right.
+20
-03
+17
1)
Fill ing the empty bit positions with the sign value
of a positive number, that is, zeros, has no changing effect on the result,and
2)
If the two's complement is taken by the method
suggested, where n is the larger number's length,
the sign value is ~tomatically appended to the
smaller number. For instance, in the above example,
if the complement of 03 is taken using n = 6,
010100
.lll!Ql
010001
In the computer, 24-bit numbers are written as eight octal
digits for convenience. The following example shows three
forms of the same addition -- decimal, binary, and octal,
respectivel y. The binary number is assumed to be an integer.
Decimal
Binary
Octal
+21
-03
+18
000000000000000000010101
111111111111111111111101
000000000000000000010010
00000025
77777775
00000022
1000000
011
111101
the sign is properly appended to the number.
This procedure is called lI extending li the sign of a number.
A-lO
OPTIONAL EQUIPMENT
REAL-TIME CLOCK
CONTINUOUS LY INCREMENTING CLOCK
The Real-Time Clock (RTC) provides a highly flexible timeorientation system for the SDS 92 Computer. It derives time
pulses from the 60-cycle computer power supply. These pulses
are then used to produce a timing mark every 16.67 mi II iseconds
or optionally every 8.33 milliseconds. The Real-Time Clock
can also accept timing marks from a customer-supplied input,
thereby allowing time measurement to any required resolution
for special applications. These timing marks are supplied at
standard SDS logic levels to the computer's RTC circuitry.
The continuously incrementing clock maintains "time-of-day"
for the computer. Two memory locations serve to count the
timing marks. In this case, the Clock Pulse is used to increment the least significant twelve bits of the count. (The Clock
Pulse interrupt location contains an MPO instruction.) The
Clock Sync is used to increment the most significant twelve
bits of the count. (The Clock Sync interrupt subroutine includes an MPO instruction.) A simple, straightforward subroutine can be entered to reconstruct the exact time-of-day from
this twenty-four bit count.
The timing marks are then used by the computer and its interrupt system to provide either an elapsed-time counter or a continuously incrementing time counter depending on the needs of
the customer. The RTC wi II operate in either mode depending
only on the computer's stored program.
ARM/DISARM
The Clock Pulse interrupt can be armed and disarmed with these
instructions:
Two pairs of locations of priority interrupts are provided with
the RTC. These are as follows:
Location
164
166
Normal
Single Instruction
Computer
Description
92
CLOCK SYNC
92
Action
EOM Effective Address
20200
Disarm Clock Pulse Interrupt
20100
Arm Clock Pu Ise Interrupt
The Clock Sync interrupt is always armed.
AUTOMATIC POWER FAIL-SAFE SYSTEM
The computer core memory holds its information with all power
removed, but information in the computer registers is destroyed
by loss of power. Upon fai lure of main power to the computer,
this system provides that the contents of all registers and other
volati Ie information are automatically stored in core memory;
also, further writing into core storage is inhibited durrng the
decay period of the computerdc power supplyoutputs. Erroneous
memory control is prevented during power-off and power-on
operations. Power-off/-on interrupt routines permit proper resumption of a program, automatically, after power is restored.
CLOCK PULSE
The Clock Pulse and Clock Sync interrupts function together to
provide elapsed-time, event-counter or time-of-day clocks.
The Clock Pulse interrupt is a single-instruction interrupt.
(Note: See Single Instruction Interrupts in Section III.) An
MPO instruction is usually placed in the Clock Pulse interrupt
location. When MPO is used as a single-instruction interrupt
subroutine, it causes the contents of the effective address to be
incremented by one but it does not alter the current content of
the flag. Furthermore, if the new (incremented) contents of
the effective address is 0000, a Clock Sync interrupt is generated. The Clock Sync interrupt can be generated in no other
way.
The system consists of relay-controlled, ac power-sensing and
memory-sequencing circuitry, two high-priority interrupt channels, and a "shut-down/start-up" programming sequence.
The Sense External Signal (SES) instruction is an aid in programming this option. Its effective address is 24000. If the
OFF interrupt (152) has just occurred, this SES sets the Flag.
ELAPSED-TIME CLOCK
DATA MULTIPLEXING SYSTEM
The elapsed-time c lock times the length of a program or subroutine, or initiates or discontinues processing at programdetermined time intervals. An arbitrary memory location is reserved as a counter. When initialized, this cell contains the
2's complement of the number of time intervals to be counted.
The Clock Pulse interrupt location contains an MPO instruction.
INTRODUCTION
The standard I/O systems provided with the SDS 92 Computer
provide for operation with all standard SDS peripheral equipments and for high-performance special devices. The Data
Multiplexing System provides an alternate I/O system that is
of particular use in dealing with multiple sources of data and
for systems which may have data rates from low to very high.
Each Clock Pulse interrupt results in incrementing the clock
count by one. When the count is finished, an interrupt to the
Clock Sync location occurs. A supervisory or other appropriate
control program can then be entered to perform the customerdesired operation.
The SDS 92 Computer has essentially two major paths along
wh ich I/O data can flow to and from memory. The fi rst
path is the same that is used by the main frame itself. The
B-1
Priority
Interrupts
• • •
PIN
BPI
POT
BPO
Basic I/O
Channel
Central
Processor
First Path
Memory
..--
Fixed Location Interlace Contro
DSCs
1--"-'-- Words for the Attached
1-----....
- ...
Memory Parity.
Checking Option
Data Multiplexing System
I
-- -- -- -- -- -- --
-~e::;
P:;- -- -- -- -- -- --I
I
Data Multiplex Channel
Address Register
I
I
I
I
I
I
I
Data Register
Input
1. Data
2. Addresses
3. 4-Bit Function
Codes
Output
1. Data
2. Control
6-Bit Characters
(lor 2 per 12-Bit Word)
12-Bit Characters
• • •
I
ElN
I
I
Priority Interrupt
I
I
DSC-I
12- or 24-Bit
Characters
DSC Priority
Data Register
I --------P-ri-o~i-tY-I~t-e-rr-u~~
I
1
t
DSC 11*
• • •
-·-·~I
...
Data/contm~
~--.-----~------
Char. Register
""'--"-"~
ElN
IUnitAddress
I
I/O DEVICE
* No storage reg i sters.
- ---,'
I
I
I
1
L
I
I
_ _ _ _ _ _ _ _ _ _ ~~S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
Priority
Interrupt
SDS 92 Computer Configuration
B-2
------.1
a memory increment operation is to be performed, the subchannel signals the DMC with a special increment line and
supplies the address. For memory increments, the DMC accesses memory, increments it, and then restores the word.
If a memory increment operation results in an all-zero word
(or double word), the DMC signals the subchannel. The
zero signal may then be used to interrupt the program.
Memory increments require two cycles.
PIN/POT operations use the first path. The basic I/O channel also uses this path. In addition to this path, which is primari Iy under the control of the main frame, there is an optional
second path that is completely under the control of the units
attached to it. The second path has priority over the first for
access to memory. This path is made available with the installation of a Data Multiplexing System.
The Data Multiplexing System (DMS) consists of a Data Multiplex Channel (DMC) and one or more Data Subchannels (DSC).
A maximum of 64 subchannels are allowed. Transmission between a DSC and computer memory is controlled by two interlace control word-pairs unique to the DSC and wired into
fixed, adjacent locations in memory. During a transmission,
the controlling DMC uses these two word-pairs for control of
address and record length. Four DSCs (one DSC-I and three
DSC-IIs) could be placed in a system as follows. The DSCs
are numbered from 100, 104, ... to 1148' Control word quads
assoc i ated wi th the DSCs are numbered accord i ng Iy: 100-103
for DSC-100, etc.
Control of the various DMC functions is achieved by four Function Code Iines from the subchannels. The DMC, in conjunction with the main frame Memory Parity Checking Option,
insure the integrity of data transmissions. Words read from
memory are checked for parity; parity is generated for words
stored in memory; words received by the DMC are checked
for proper parity; a parity error signal is generated by the DMC
and sent to the subchannel when an input parity discrepancy
is detected.
DATA SUBCHANNELS (DSC-N)
DATA MULTIPLEX CHANNEL (DMC)
The Data Multiplex Channel is a basic unit for the Data MultiSystem. It connects to the SDS 92 Computer via the
second path to memory. The DMC contains a 13-bit Data
Register, 15-bit Address Register, and control logic to enable
the DMS to perform a variety of functions. The data and address are connected to memory when a transfer of information
is imminent. Program control required for input/output operates
directly on the individual Data Subchannel (DSC), not on the
DMC.
A number of subchannels can be attached to the DMC. The
two described below are standard subchannels. Subchannels
can control and generate program interrupts, but do not include the interrupt levels themselves. The signol,s must be
routed to optional interrupt levels.
pexing
The subchannels use a priority scheme to determine which
may transmit to the DMC at any given time. Up to 64
DSCs may be connected to a DMC. A DSC may use the
internal interlace feature of the DMC to control its transmission, or it may be equipped with an External Interlace
(EIN).
When external data addresses are provided to the DMC, the
DMC transmissions require one cycle for each 12-bit word
transmitted and two cycles for each 24-bit double word transmitted.
A DSC using internal interlace has two word pairs assigned to
it. These two word pairs are located in contiguous memory
locations and are fixed for a given subchannel. The program
may select either the even word pair or odd word pair location.
If the even word pair location is selected, the subchannel wi II
automatically switch to the odd word pair location when the
count field of the even word pair word is zero. The program
can also select whether the subchannel switches back to the
even word pair when the count field of the odd word pair is
zero. The subchannel generates an interrupt signal when the
count field of either word pair reaches zero. Transmission
termination occurs when the odd word pair's count equals zero,
if the subchannel does not switch back to the even word pair.
The DMC has an internal interlace feature. This feature allows
subchannels to specify the addresses of word pairs in memory
where the data address and count are located. When operating
with internal interlace, the subchannel supplies the address of
its associated interlace control words instead of the actual data
address. The DMC accesses the interlace word pair, increments
the address portion, decrements the word count, restores modified words, and then accepts data from, or transmits data to,
the requesting subchannel. The DMC also supplies a signal to
the subchannel, if the decremented word count is zero.
The format of the'internal interlace word pair is:
I--Word N + 1 - - 1
I
'Word Count
o
I
8 9-11 10
The two word pai~ internal interlace allows a subchannel to
hand Ie continuous data by alternately working from one memory area or another. By allowing the subchannel to switch
automatically from one interlace word pair to the other, the
program is relieved of the necessity for making real-time responses to the zero count condition. Using first the even pair
then the odd pair interlace words allows a maximum transmission of 1024 words or double words.
Word N - - - - I
Data Address
11
The 9-bit word count permits block lengths to 512 words.
Transmissions using internal interlace require five cycles, if
the required transmission is for a 12-bit word, and six cyc les, if the required transmission is for a 24-bit double
word.
CHARACTER SUBCHANNEL (DSC-I)
The DMC provides for automatic memory incrementing. The
counting capability of the DMC Data Register permits an externally specified memory word to be incremented. When such
The DSC-I contains a 12-bit data register that can assemble and
disassemble two 6-bit characters, and transmit one or tw06-bit
characters or one 12-bit character. (DSC-I has a unit address
B-3
memory cycle. After each word is transmitted, the EIN increments its address register and decrements its count. When
the count equals zero, the EIN signals the DSC, which can
then generate a program interrupt and/or notify the external
device. Transrn:ssion normally terminates on zero count.
Sequencing of interlace words is identical to the sequence of
operations performed for internal interlace, except that only
four memory cyc! es are used for interl ace word processi ng. The
first istoaccess the interlace word pair initiallYi the second is
to restore the interlace word pair when the count reaches zero.
register.) It checks and generates the parity of characters to
enable it to couple with standard SDS peripheral equipment.
The subchannel may operate with either internal or external
interlace. It has one mode of output and two modes of input.
During output, it transmitsuntil the odd internal interlace word
'pair count is zero and then terminates, if interlace cycl ing is
not requested. The output may also be terminated ifthedevice
sends an END signal to the channel. This END signal may
cause the DSC-I to generate an interrupt to the program.
MEMORY PARITY INTERRUPTS
Input, like output, may always be terminated due to an
external END signal. TheprogramcanalsospecifythattheDSC
terminates and disconnects on zero count, or disconnects only
on the END signal. In either case, however, all transmission
to memory is terminated after the odd interlace count reaches
zero, if interlace cycling is not requested.
SDS computers incorporate an extensive memory parity checking
system. The inclusion of parity generation and checking circu itry assures the integrity of all data and instructions transferred
among the memory, the central processing unit, and input/output
channels.
FULL WORD SUBCHANNEL (DSC-II)
In normal operation a switch on the computer console specifies
the action to be performed by the computer when a memory
parity error is detected. Two actions are avai lable: the computer halts with the parity indicator lightedi or the computer
ignores the parity error and proceeds with the program.
The DSC-II is a general-purpose subchannel, designed to allow
any device to be connected to it. It contains no storage for data .
Depending on the Function Code provided to the DMC, the
DSC-II will permit 12- or 24-bit (plus parity) transmission
between the DMC and external devices connected to the DSC-II.
The external device must be capable of holding the data during
the transm ission to/from the DMC. (An A-to-D converterwou Id
have such capability.) Like the DSC-I, the DSC-II can operate
with either internal or external interlace. Its operation in this
respect is identical to the DSC-I. The DSC-II also contains
control logic to facilitate memory increment operations in
conjunction with the DMC.
In many real-time appl ications it is desirable to keep the
computer running when a parity error isdetected. Also, the
program must be notified of the error without stopping
computat ion.
An optional feature provides this capability by means of two
levels of armed interrupts. One interrupt level is associated
with the central processor and the Time-Multiplexed
Communication Channelsi the other interrupt level with the
Direct Access Communication Channels and the Data Multiplexing
System. Memory parity errors detected from these two sources
produce a priority interrupt associated with the cause. The
processing routine associated with the interrupt can then take
appropriate action, such as re-initiate the failed operation,
notify the operator, orenter a diagnostic routine. Such action
allows memory parity errors to be recognized and handled
properly without hindering the computer's performance of realtime or on-I ine calculations.
EXTERNAL INTERLACE (EIN)
The External Interlace can be attached to the DSC to control
the transmission of its data to/from memory. The EIN consists
of a 15-bit address register and a 9-bit count register. These
registers are loaded automatically when the subchannel is
activated, the information coming from the internal interlace
memory locations. Once the EIN is set up, it will control the
transm ission of the DSC at a maximum rate of one word per
B-4
TRAPPING RETURN SUBROUTINE EXAMPLE
has the form:
The following code determines how many cells (one or two)
the trapped instruction used: it then increments the subroutine entry accordingly to provide the proper return address.
MUASIM
o
DATA
DATA
TRUE
ACK
2
3
4
5
6
.7
8
9
10 11
which marks the Flag and PCT bits in 0, 1, zeros in bits 6
through 8, and the trap instruction address in bits 9, 10, 11 to
MUASIM and in bits 0 through 11 in MUASIM + 1.
Executing an instruction containing the MUA operation code
causes the BRM MUASIM to be executed. The marked place
PLUSONE
I 3 bits
12 bits
Assume (1) the trap instruction is a multiply simulator at
location 124, and (2) the branch in location 124 is BRM
MUASIM. Assume also that MUA hardware is not present in
the machine.
MUASIM
o
F I'CTI Unpredictable I
The subroutine return routine follows:
LOB
*MUASIM
Load trapped instruction.
LOA
=1
Load an incrementer.
COB
=040
BFT
TRUE
COB
=037
BRU
ACK
COB
=010
BFT
ACK
Branch if bit 8 is reset (i.e., if F is set to 1 which implies two
word-full address with no index).
COB
=020
F = 0 if indirect address, single precision; F = 1 if two word
indexed
ACA
=0
Add 1 to A if two word (add 0 if one word).
MPA
MUASIM+1
Add 1 or 2 to the subroutine entry.
MPF
MUASIM
This is for address overflow correction.
Branch if bit 6 is reset.
F = 1 if address was an immediate address (two words); F = 0 if it
was direct single precision.
B-5
SOS 92 MEMORY ALLOCATION
0000
Unassigned
0001 - 0037
Scratch Pad
0040 - 0077
Unassigned
0100 - 0117
DSC Interlace Control Word Pairs
0120
Trap 12
0122
Trap 52
0124
Trap 13
0126
Trap 53
0130
Trap 10
0132
Trap 50
0134
Trap 11
0136
Trap 51
0140
Trap 14
0142
Trap 54
0144
Trap 15
01'46
Trap 55
0150
Interrupt, POWER ON (always arm"'ed)
0152
Interrupt, POWER OFF (always armed)
0154
Interrupt, MAIN FRAME PARITY (armed via console switch)
0156
Interrupt, OAT A MU LTIPLEXING SYSTEM PARITY (armed via console switch)
0160
Unassigned
\
Is
Ir\
0162
Unassigned
0164
Interrupt, CLOCK SYNC (always armed)
0166
Interrupt, CLOCK PULSE (arm furnished, I. type)
0170
Interrupt, Il (arm furnished)
I
0172
Interrupt, 12 (arm furnished)
0174
Unassigned
0176
Unassigned
0200 - 1177
System Interrupts (up to 256 levels; any may be of I. type if desired)
I
I. --- Single Instruction Interrupt
I
Ir --- Interrupt system must be enabled before interrupt goes active.
Is -
Interrupt always proceeds from Waiting to Active
B-6
SDS 92 INSTRUCTION LIST - FUNCTIONAL CATEGORIES
Mnemonic
Instruction
Code
Name
Function
Timing*
LOAD!...STORE
LDA
64
LOAD A
(M) - - A
2
LDB
24
LOAD B
(M) - - B
2
STA
44
STORE A
(A) - - M
2
(B) - - M
. 2
STB
04
STORE B
XMA
74
EXCHANGE M AND A
(A)---(M)
3
XMB
34
EXCHANGE M AND B
(B)---(M)
3
17
EXCHANGE M AND F
(M)O---F
3
FLAG
XMF
LDF
57
LOAD F
(M)O - - F
SFT
0044
SET FLAG TRUE
1--F
3,4
SFF
0042
SET FLAG FALSE
o --F
3,4
INF
0046
INVERT FLAG
If (F)=l, 0 --F; if (F)=O, 1--F
3,4
ADA
62
ADD TO A
(A)+ (M) - - A; Carry -
ADB
22
ADD TO B
(B)+ (M) ---- B; Carry - - - F
2
ACA
63
ADD WITH CARRY TO A
(A)+ (M)+ F - - A; Carry - - F
2
ACB
23
ADD WITH CARRY TO B
(B)+ (M)+ F -
2
SUA
60
SUBTRACT TO A
(A) - (M) - - - A; Carry - - - F
2
SUB
20
SUBTRACT TO B
(B) - (M) -
2
SCA
61
SUBTRACT WITH CARRY TO A
(A) - (M) - F ---A; Carry - - - F
2
SCB
21
SUBTRACT WITH CARRY TO B
(B) - (M) - F - - - B; Carry - - - F
2
MPA
76
MEMORY PLUS A TO MEMORY
(M)+ (A) - - - M; Carry - - F
3
3
ARITHMETIC
F
B; Carry - - - F
B; Carry - - F
2
MPB
36
MEMORY PLUS B TO MEMORY
(M)+ (B) --M; Carry - - F
3
MPO
16
MEMORY PLUS ONE TO MEMORY
(M)+l ---M; Carry~F
3
MPF
56
MEMORY PLUS FLAG TO MEMORY
(M)+ (F) - - - M; Carry - - - F
3
MUA
13
MU LTIPL Y A (Optional)
(A)x (M) --AB
5
MUB
53
MULTIPLY B (Optional)
(B)x(M) ---AB
DVA
52
DIVIDE AB (Optional)
(AB)+(M) - B ; R--A
13
DVB
12
DIVIDE BA (Optional)
(BA)+(M) - - - B; R - - A
13
ANA
65
AND TO A
(A) and (M) - - A
2
ANB
25
AND TO B
(B) and (M) - - B
2
ORA
67
OR TOA
(A) or (M) - - A
2
ORB
27
OR TO B
(B) or (M) --B
2
EOA
66
EXCLUSIVE OR TO A
(M)(A) or (M)(A) - - - A
2
5
LOGICAL
*See page 2-1 for interpretation and use of the Timing column.
B-7
SDS 92 INSTRUCTION LIST - FUNCTIONAL CATEGORI,ES (continued)
Instruction
Code
Mnemonic
Name
Function
26
EXCLUSIVE OR TO B
(M)(B) or (M)(B) --B
MAA
75
MEMORY AND A TO MEMORY
(M) and (A) - - M
3
MAB
35
MEMORY AND B TO MEMORY
(M) and (B) - - M
3
45
COMPARE ONES WITH A
If (A)(M) = 0, set Fi if (A)(M) 10, reset F
2
Timing
LOGICAL (continued)
EOB
2
COMPARISON
COA
COB,
05
COMPARE ONES WITH B
If (B)(M)=O, set Fi if (B)(M)IO, reset F
2
CMA
47
COMPARE MAGNITUDE OF M WITH A
If .(A) ~(M), set Fi if (A) <(M), reset F
2
CMB
07
COMPARE MAGNITUDE OF M WITH B
If (B) ~(M), set Fi if (B) «M), reset F
2
CEA
46
COMPARE M EQUAL TO A
If (M) I(A), set F; if (M) =(A), reset F
2
CEB
06
COMPARE M EQUAL TO B
If (M)I(B), set Fi if (M)=(B), reset F
2
BRU
73
BRANCH UNCONDITIONALLY
M ---P
BRC
32
BRANCH, CLEAR INTERRUPT, AND
LOAD FLAG
M --- Pi c lear Interrupt (see page 2-4)
BRL
33
BRANCH AND LOAD FLAG
M --- Ii (see page 2-4)
BFF
31
BRANCH ON F LAG FALSE
If F = 0, M ---- Pi
if F = 1, take next instruction
1
2
BFT
71
BRANCH ON F LAG TRUE
If F = 1, M ---- Pi
1
2
BRANCH
if F = 0, take next instruction
BDA
70
BRANCH ON DECREMENTING A
BAX
30
BRANCH AND EXCHANGE A AND B
BRM
77
BRANCH AND MARK PLACE
BMC
37
(A) - 1---A
If (A) 177778, M --- Pi
If (A) = 7777 , take next instruction
8
(A)~ (B)i (M) --- P
3
1
2
(P) ---M, M+1i M+2---Pi
(F) -MO; (PCT)--- M1
3
BRANCH, MARK PLACE, AND CLEAR
FLAG
(See page 2-5)
3
SHIFT
CYA
42*
CYCLE A
A cycled left N places
3-7
CYB
02*
CYCLE B
B cycled left N places
3-7
CFA
43*
CYCLE FLAG AND A
F,A cycled left N places
3-7
CFB
03*
CYCLE FLAG AND B
F, B cycled left N places
3-7
CYCLE DOUBLE
A, B cycled left N places
3-7
CYD
02/42* **
CFD
43*
CYCLE FLAG AND DOUBLE
A, B, F cycled left N places
3-7
CFI
03*
CYCLE FLAG AND DOUBLE INVERSE
B, A, F cycled left N places
3-7
72
EXECUTE
Instruction M is performed, P unchanged
HALT
Ha Its computation
CONTROL
EXU
HLT
0041/00000000**
*See page 2-5 for indication of the instruction structure and code redundancy.
** A slash (/) indicates that either instruction code can be used to perform the same operation.
B-8
3,4
SDS 92 INSTRUCTION LIST - FUNCTIONAL CATEGORIES (continued)
Mnemonic
Instruction
Code
Name
Timing
TRAPPING
SCT
0061
SET PROGRAM-CONTROLLED TRAP
1-PCT
3,4
RCT
0060
RESET PROGRAM-CONTROLLED TRAP
O-PCT
3,4
TCT
0160
TEST PROGRAM-CONTROLLED TRAP
If PCT = 0, O-F; if PCT = 1,
3,4
l~F
BREAKPOINT TESTS
BPT 1
0144
BREAKPOINT NO.1 TEST
Test Breakpoint Switch
3,4
BPT 2
0145
BREAKPOINT NO.2 TEST
Test Breakpoint Switch
3,4
BPT 3
0146
BREAKPOINT NO.3 TEST
Test Breakpoint Switch
3,4
BPT 4
0147
BREAKPOINT NO.4 TEST
Test Breakpoint Switch
3,4
EIR
0051
ENABLE INTERRUPT
3,4
DIR
0050
DISABLE INTERRUPT
3,4
lET
0150
INTERRUPT ENABLED TEST; SET FLAG
IF INTERRUPT SYSTEM ENABLED
3,4
ARM INTERRUPTS
3,4
INTERRUPTS
AIR
00020001
CHANNEL CONTROL AND TESTS
DSC
00000100
DISCONNECT CHANNEL
3,4
TOP
00012100
TERMINATE OUTPUT ON CHANNEL
3,4
TIP
00012100
TERMINATE INPUT ON CHANNEL
3,4
ALC
00050100
ALERT CHANNEL INTERLACE
3,4
ASC
00010500
ALERT TO STORE INTERLACE COU NT
3,4
CAT
01004100
CHANNEL ACTIVE TEST; SET FLAG IF
NOT ACTIVE
3,4
01001100
CHANNEL ERROR TEST; SET FLAG IF ERROR
3,4
CET
INPUTLOUTPUT
WIN
15
WORD IN
(Channel)- M
RIN
55
RECORD IN
(Channel
WOT
11
ROT
5 + wait
3 + 2N + wait
WORD OUT
d )_M
N wor s
(M)- Channel
51
RECORD OUT
(M
2 + 2N + wait
PIN
14
PARALLEL INPUT
d ) - Channel
N wor s
(Unit M)_ M in parallel
POT
10
PARALLEL OUTPUT
(M)_Unit M in parallel
BPI
54
BLOCK PARALLEL INPUT
(Unit M)_ M in parallel,
N sequential locations.
4 + N + wait, and
3,4+2N+wait
BPO
50
BLOCK PARALLEL OUTPUT
(M)_ Unit M in parallel,
N sequential locations
3 + N + wait, and
2,3 + 2N + wait
EOM
00(40)*
ENERGIZE OUTPUT M
3.5 fJsec pulse to points addressed
SES
01(41)*
SENSE EXTERNAL SIGNAL
If Signal = 1, set Flag Bit;
if Signal
*Codes EOM 40 and SES 41 are reserved for use in special system applications.
B-9
=
0, reset Flag Bit
4 + wait
5 + wait,
and 5,6 + wait
4 + wait,
and 4,5 + wait
3,4
3,4
SDS 92 INSTRUCTION LIST - NUMERICAL ORDER
Instruction Code
Mnemonic
Name
Paae Reference
3-5,3-6,3-9
00(40)*
EOM
ENERGIZE OUTPUT M
00000000/0041**
HLT
HALT
2-6
00000100
DSC
DISCONNECT CHANNEL
3-6
00010500
ASC
ALERT TO STORE INTERLACE COUNT
3-6
00012100
TIP
TERMINATE INPUT ON CHANNEL
3-6
00012100
TOP
TERMINATE OUTPUT ON CHANNEL
3-6
3-12
00020001
AIR
ARM INTERRUPTS
00050100
ALC
ALERT CHANNEL INTERLACE
3-7
0042
SFF
SET FLAG FALSE
2-2
0044
SFT
SET FLAG TRUE
2-1
0046
INF
INVERT FLAG
2-2
0050
DIR
DISABLE INTERRUPT
3-11
0051
EIR
ENABLE INTERRUPT
3-11
0060
RCT
RESET PROGRAM-CONTROLLED TRAP
2-7
0061
SCT
SET PROGRAM-CONTROLLED TRAP
2-7
01(41)*
SES
SENSE EXTERNAL SIGNAL
01001100
CET
CHANNEL ERROR TEST; SET FLAG IF ERROR
3-7
01004100
CAT
CHANNEL ACTIVE TEST; SET FLAG IF NOT ACTIVE
3-7
0144
BPT 1
BREAKPOINT NO. 1 TEST
2-7
0145
BPT 2
BREAKPOINT NO. 2 TEST
2-7
0146
BPT 3
BREAKPOINT NO.3 TEST
2-7
0147
BPT 4
BREAKPOINT NO.4 TEST
2-7
0150
lET
INTERRUPT ENABLED TEST; SET FLAG IF INTERRUPT
SYSTEM ENABLED
0160
TCT
TEST PROGRAM-CONTROLLED TRAP
2-7
02***
CYB
CYCLE B
2-6
02/42** ***
CYD
CYCLE DOUBLE
2-6
03***
CFB
CYCLE FLAG AND B
2-6
03***
CFI
CYCLE FLAG AND DOUBLE INVERSE
2-6
04
STB
STORE B
2-1
05
COB
COMPARE ONES WITH B
2-4
06
CEB
COMPARE M EQUAL TO B
2-4
07
CMB
COMPARE MAGNITUDE OF M WITH B
2-4
3-6,3-7,3-9
3-11
10
POT
PARALLEL OUTPUT
11
WOT
WORD OUT
3-2
12
DVB
DIVIDE BA (Optional)
2-3
13
MUA
MULTIPLY A (Optional)
2-3
3-7,3-8,3-9,3-12
*Codes EOM 40 and SES 41 are reserved for use in spec ial system appl ications.
** A slash (/) indicates that either instruction code can be used to perform the same operation.
***See page 2-5 for indication of the instruction structure and code redundancy.
B-ll
SDS 92 INSTRUCTION LIST - NUMERICAL ORDER (continued)
Instruction Code
Mnemonic
Name
Pa~e
Reference
14
PIN
PARALLE L INPUT
3-8,3-9
15
WIN
WORD IN
3-2
16
MPO
MEMORY PLUS ONE TO MEMORY
2-2
17
XMF
EXCHANGE M ANDF
2-1
20
SUB
SUBTRACT TO B
2-2
21
SCB
SUBTRACT WITH CARRY TO B
2-2
22
ADB
ADD TO B
2-2
23
ACB
ADD WITH CARRY TO B
2-2
24
LDB
LOAD B
2-1
25
ANB
AND TO B
2-3
26
EOB
EXCLUSIVE OR TO B
2-3
27
ORB
OR TO B
2-3
30
BAX
BRANCH AND EXCHANGE A AND B
2-5
31
BFF
BRANCH ON FLAG FALSE
2-4
32
BRC
BRANCH, CLEAR INTERRUPT, AND LOAD FLAG
2-4
33
BRL
BRANCH AND LOAD FLAG
2-4
34
XMB
EXCHANGE M AND B
2-1
35
MAB
MEMORY AND B TO MEMORY
2-4
36
MPB
MEMORY PLUS B TO MEMORY
2-2
37
BMC
BRANCH, MARK PLACE, AND CLEAR FLAG
2-5
42*
CYA
CYCLE A
2-6
43*
CFA
CYCLE FLAG AND A
2-6
43*
CFD
CYCLE FLAG AND DOUBLE
2-6
44
STA
STORE A
2-1
45
COA
COMPARE ONES WITH A
2-4
46
CEA
COMPARE M EQUAL TO A
2-4
47
CMA
COMPARE MAGNITUDE OF M WITH B
2-4
50
BPO
BLOCK PARALLEL OUTPUT
51
ROT
RECORD OUT
3-2
52
DVA
DIVIDE AB (Optiona I)
2-3
53
MUB
MULTIPLY B (Optional)
2-3
54
BPI
BLOCK PARALLEL INPUT
55
RIN
RECORD IN
3-3
56
MPF
MEMORY PLUS FLAG TO MEMORY
2-3
57
LDF
LOAD F
2-1
60
SUA
SUBTRACT TO A
2-2
61
SCA
SUBTRACT WITH CARRY TO A
2-2
62
ADA
ADD TO A
2-2
*See page 2-5 for indication of the instruction structure and code redundancy.
B-12
3-8,3-9
3-8,3-9
SDS 92 INSTRUCTION LIST - NUMERICAL ORDER (continued)
Instruction Code
Mnemonic
Name
Page Reference
63
ACA
ADD WITH CARRY TO A
2-2
64
LDA
LOAD A
2-1
65
ANA
AND TO A
2-3
66
EOA
EXCLUSIVE OR TO A
2-3
67
ORA
OR TO A
2-3
70
BDA
BRANCH ON DECREMENTING A
2-5
71
BFT
BRANCH ON FLAG TRUE
2-5
72
EXU
EXECUTE
2-6
73
BRU
BRANCH UNCONDITIONALLY
2-4
74
XMA
EXCHANGE M AND A
75
MAA
MEMORY AND A TO MEMORY
2-1
"
2-4
76
MPA
MEMORY PLUS A TO MEMORY
2-2
BRANCH AND MARK PLACE
2-5
77
BRM
B-13
SDS 92 INSTRUCTION LIST - ALPHABETICAL ORDER
Mnemonic
Name
Instruction Code
Paae Reference
ACA
63
ADD WITH CARRY TO A
2-2
ACB
23
ADD WITH CARRY TO B
2-2
ADA
62
ADD TO A
2-2
ADB
22
ADD TO B
2-2
AIR
00020001
ARM INTERRUPTS
ALC
00050100
ALERT CHANNEL INTERLACE
3-7
ANA
65
AND TO A
2-3
ANB
25
AND TO B
2-3
ASC
00010500
ALERT TO STORE INTERLACE COUNT
3-6
BAX
30
BRANCH ON DECREMENTING A
2-5
BDA
70
BRANCH AND DECREMENTING A
2-5
BFF
31
BRANCH ON FLAG FALSE
2-4
BFT
71
BRANCH ON FLAG TRUE
2-5
BMC
37
BRANCH, MARK PLACE, AND CLEAR FLAG
2-5
BPI
54
BLOCK PARALLEL INPUT
3-8,3-9
BPO
50
BLOCK PARALLEL OUTPUT
3-8,3-9
BPT 1
0144
BREAKPOINT NO. 1 TEST
2-7
BPT 2
0145
BREAKPOINT NO.2 TEST
2-7
BPT 3
0146
BREAKPOINT NO.3 TEST
2-7
BPT 4
0147
BREAKPOINT NO.4 TEST
2-7
BRC
32
BRANCH, CLEAR INTERRUPT, AND LOAD FLAG
2-4
BRL
33
BRANCH AND LOAD FLAG
2-4
BRM
77
BRANCH AND MARK PLACE
2-5
BRU
73
BRANCH UNCONDITIONALLY
2-4
CAT
01004100
CHANNEL ACTIVE TEST; SET FLAG IF NOT ACTIVE
3-7
CEA
46
COMPARE M EQUAL TO A
2-4
CEB
06
COMPARE M EQUAL TO B
2-4
CET
01001100
CHANNEL ERROR TEST; SET FLAG IF ERROR
3-7
CFA
43*
CYCLE FLAG AND A
2-6
CFB
03*
CYC LE FLAG AND B
2-6
CFD
43*
CYCLE FLAG AND DOUBLE
2-6
CFI
03*
CYCLE FLAG AND DOUBLE INVERSE
2-6
CMA
47
COMPARE MAGNITUDE OF M WITH A
2-4
CMB
07
COMPARE MAGNITUDE OF M WITH B
2-4
COA
45
COMPARE ONES WITH A
2-4
3-12
COB
05
COMPARE ONES WITH B
2-4
CYA
42*
CYCLE A
2-6
CYB
02*
CYCLE B
2-6
*See page 2-5 for indication of the instruction structure and code redundancy.
B-15
SDS 92 INSTRUCTION LIST - ALPHABETICAL ORDER (continued)
Mnemonic
Name
Instruction Code
Paae Reference
2-6
CYD
02/42* **
CYCLE DOUBLE
DIR
0050
DISABLE INTERRUPT
DSC
00000100
DISCONNECT CHANNEL
3-6
DVA
52
DIVIDE AB (Optional)
2-3
DVB
12
DIVIDE BA (Optional)
2-3
EIR
0051
ENABLE INTERRUPT
EOA
66
EXCLUSIVE OR TO A
2-3
EOB
26
EXCLUSIVE OR TO B
2-3
EOM
00(40)***
ENERGIZE OUTPUT M
EXU
72
EXECUTE
2-6
HLT
00000000/0041**
HALT
2-6
lET
0150
INTERRUPT ENABLED TEST; SET FLAG IF INTERRUPT
SYSTEM ENABLED
3-11
3-11
3-5,3-6,3-9
3-11
2-2
INF
0046
INVERT FLAG
LDA
64
LOAD A
2-1
LDB
24
LOAD B
2-1
LDF
57
LOAD F
2-1
MAA
75
MEMORY AND A TO MEMORY
2-4
MAB
35
MEMORY AND B TO MEMORY
2-4
MPA
76
MEMORY PLUS A TO MEMORY
2-2
MPB
36
MEMORY PLUS B TO MEMORY
2-2
MPF
56
MEMORY PLUS FLAG TO MEMORY
2-3
MPO
16
MEMORY PLUS ONE TO MEMORY
2-2
MUA
13
MULTIPLY A (Optional)
2-3
MUB
53
MULTIPLY B (Optional)
2-3
ORA
67
OR TOA
2-3
ORB
27
OR TO B
2-3
PIN
14
PARALLEL INPUT
POT
10
PARALLEL OUTPUT
RCT
0060
RESET PROGRAM-CONTROLLED TRAP
2-7
3-8,3-9
3-7,3-8,3-9,3-12
RIN
55
RECORD IN
3-3
ROT
51
RECORD OUT
3-2
SCA
61
SUBTRACT WITH CARRY TO A
2-2
SCB
21
SUBTRACT WITH CARRY TO B
2-2
SCT
0061
SET PROGRAM-CONTROLLED TRAP
2-7
SES
01 (41)***
SENSE EXTERNAL SIGNAL
SFF
0042
SET FLAG FALSE
2-2
SFT
0044
SET FLAG TRUE
2-1
*See page 2-5 for indication of the instruction structure and code redundancy.
**A slash
V)
indicates that either instruction code can be used to perform the same operation.
***Codes EOM 40 and SES 41 are reserved for use in special system appl ications.
B-16
3-6,3-7,3-9
SDS 92 INSTRUCTION LIST - ALPHABETICAL ORDER (continued)
\
Mnemonic
Instruction Code
Name
Pase Reference
STA
44
STORE A
2-1
STB
04
STORE B
2-1
SUA
60
SUBTRACT TO A
2-2
SUB
20
SUBTRACT TO B
2-2
TCT
0160
TEST PROGRAM-CONTROLLED TRAP
2-7
TIP
00012100
TERMINATE INPUT ON CHANNEL
3-6
TOP
00012100
TERMINATE OUTPUT ON CHANNEL
3-6
WIN
15
WORD IN
3-2
WOT
11
WORD OUT
3-2
XMA
74
EXCHANGE M AND A
2-1
XMB
34
EXCHANGE M AND B
2-1
XMF
17
EXCHANGE M AND F
2-1
B-17
SOS 92 INPUT/OUTPUT INSTRUCTIONS
Mnemonic
Octal Code
Name
Mnemonic
Octal Code
Name
Buffer Instructions and Tests
BUFFER CONTROL
EOM A, T
DSC
TOP
TIP
ASC
ALC
00 or 40
00000100
00012100
00012100
00010500
00050100
BUFFER TESTS
Energize Output M
Disconnect Channel
Terminate Output on Channel
Terminate Input on Channel
Alert to Store Interlace Count
Alert Channel Interlace
SES
CAT
CET
A, T
01 or 41
01004100
01001100
Sense External Signal
Channel Active Test
Channel Error Test
DAT A TRANSFER
PARALLEL INPUT/OUTPUT
POT
BPO
PIN
BPI
A,
A,
A,
A,
T
T
T
T
10
50
14
54
Parallel Output
Block Parallel Output
Parallel Input
Block Parallel Input
WOT
ROT
WIN
RIN
A, T
A, T
A,T
A, T
11
51
15
55
Word Out
Record Out
Word In
Record In
Peripheral Device Instructions and Tests
°TYPEWRITER
RKB
TYP
1,2
1,2
°LINE PRINTER (cont. )
00002301
00002341
Read Keyboard
Write Typewri ter
1,2
1,2
1,2
00002304
00000344
00002344
Read Paper Tape
Punch Paper Tape with Leader
Punch Paper Tape, No Leader
1,2
1,2
1
1,2
1,2
01012106
01011106
00002306
00003306
01014146
00002346
00003346
Card Reader Ready Test
Card Reader EOF Test
Read Card Dec imal (Hollerith)
Read Card Binary
Card Punch Ready Test
Punch Card Decimal (Hollerith)
Punch Card Binary
01012160
01014160
01011160
00010360
Pri nter Read y Tes t
End of Page Test
Printer Fault Test
Printer Off-line
PSC
PSP
PLP
1, n
1, n
1,2
0001n560
0001 n760
00002360
Printer Skip to Format Channel n
Pri nter Space n Li nes
Print Line Printer
°PAPER TAPE
MAGNETIC TAPE
RPT
PTL
PPT
°CARD
CRT
CFT
RCD
RCB
CPT
PCD
PCB
° LINE PRINTER
PRT
EPT
PFT
POL
TRT
FPT
BTT
ETT
DT2
DT5
DT8
TFT
WTB
WTD
EFT
ERT
RTB
RTD
SFB
SFD
SRB
SRD
REW
RTS
n
n
n
n
n
n
n
n,2
n,2
n,2
n,2
n,2
n,2
n,2
n,2
n,2
n,2
n
0
0101051n
0101411n
0101211 n
0101111n
0101631n
0101671n
0101731n
01013710
0000335n
0000235n
0000337n
0000737n
0000331n
0000231n
0000333n
0000233n
0000733n
0000633n
0001411 n
00014100
Legend
A = address; *A = indirect address; =A = immediate address; T = index tag; n = number (0-7)
°Mnemonics and Octal Codes are given for device number 1 in a two-character/word mode.
Tape Ready Test
File Protect Test
Beginning of Tape Test
End of Tape Test
Density Test, 200 BPI
Density Test, 556 BPI
Density Test, 800 BPI
Tape End-of-File Test
Write Tape in Binary
Write Tape in Decimal (BCD)
Erase Forward Tape
Erase Reverse Tape
Read Tape in Binary
Read Tape in Decimal (BCD)
Scan Forward in Binary
Scan Forward in Decimal (BCD)
Scan Reverse in Binary
Scan Reverse in Decimal (BCD)
Rewind
Convert Read to Scan
SC1ENrrIFIC DATA SYSTEMS
1649 Seventeenth Street · Santa Monica, California · Phone (2 13) UP 1- 0960
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2010:06:09 15:14:46-08:00 Modify Date : 2010:06:09 15:20:08-07:00 Metadata Date : 2010:06:09 15:20:08-07:00 Producer : Adobe Acrobat 9.32 Paper Capture Plug-in Format : application/pdf Document ID : uuid:c643fb66-23a2-4e18-96a8-c3eb7317f4d9 Instance ID : uuid:8b2a6cea-0a76-4ff9-b603-31ff7ca51471 Page Layout : SinglePage Page Mode : UseOutlines Page Count : 78EXIF Metadata provided by EXIF.tools