901013A_7371_7372_7374_Magtape_Maint_Oct68 901013A 7371 7372 7374 Magtape Maint Oct68
901013A_7371_7372_7374_Magtape_Maint_Oct68 901013A_7371_7372_7374_Magtape_Maint_Oct68
User Manual: 901013A_7371_7372_7374_Magtape_Maint_Oct68
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SDS 901013A
$8.50
TECHNICAL MANUAL
MAGNETIC TAPE SYSTEM
MODEL 7371/7372/7374
October 1968
SCIENTIFIC DATA SYSTEMS. 701 South Aviation Boulevard. EI Segundo, Calif., 90245 • 213/772-4511
@1968, SCientific Data Systems, Inc.
SDS 901013
Effective Pages
1
I LIST OF EFFECTIVE PAGES
I
Total number of pages is 266, as follows:
Page No.
Title •••.•.••...••.•...••••.••.••
A ••..•.••••.•.••••...•••.••..•••
i thru x ••.•.•.•.••••.•••..••...•.
1-1 thru 1-6 •• ~ ..•.••......•....•
2-1 thru 2-14 ••..•....••••••.••••
3-1 thru 3-148 •••.•..•.••.•.•.•••
4-1 thru4-86 •....•...•.••...•.••
A
Issue
Original
Original
Original
Original
Original
Original
Original
Page No.
Issue
SDS 901013
Contents
TABLE OF CONTENTS
Title
Section
GENERAL DESCRIPTION... •...•• ..••. ••. ••• •. • .•.• •.•. •... .•. . .•.• .••. • . •• .•. ••• ••• .• ••••
1-1
Introduction ••......•.••.••..•.....•..••.••......••••.•.•••..•...••.•.•••••••••••
Scope of Manual ••.•••...•••.•.•.•.••••.••••••...•..•••.•.•..•••...••.•.•.•••
Related Publications •••.••••••••..••..•..••••••••....•••...••••.•.•.•••..•.•••
Purpose and Brief Description •••.••••••......•.•......••••••...•.....••...•..••
Physical Description ••..•.....••••••....•....•.•....•.•.•.•..•.•..•...•.••••.....•
General ••....•••..•..•••......•.•....•.•.••••.•.•.•.•••..•.•....•.•.•.••...•
Magnetic Tape Station ••••.•.•....•..•••...•....•...•••.........•.......•...••
Transport Assembly •...•..•.•......•...••.....•..•.••...•....•.•.•..•....••
Operator Control Panel ••..••••...•...•....•.•...•.......•.•..•....•...•.••
Vacuum System ••.•...••••...••...•...•..•..••....•.••.•.•....••..•..•.••
Positive Pressure System ••.•...••..••.••.•.•.••.•.••...•.•••••...••..•.•.••
Blower Shelf Assembly ••..•.•.•....•.•..•.•.•..•.....•••••......•••••....•
Relay Chassis Assembly ••..•.•.•.......••..•..•.....•.••.•...••.••.•...•.••
Power Suppl ies ••.•.........•.....•.......•...•..........................•
Power Distribution Chassis ••......•.•..•.•.•....•......•.•....•...••.••..••
Transport Drive Electronics ••.•......•......••......•.......•.•..•.••.•.•..•
Station Electronics •••......•..•.••..••••••....•.••.....•.•..•..•...•••..•
Magnetic Tape Controller •••.•.•.••........•...•....•................•.......••
Functional Description •••.....•.....•...•.•..•.•.••...•...•••..•....•.•.•......•.•
Magnetic Tape Station .•......•....•......•.•...•..•....•..••..•..•...•.•..•••
Magnetic Tape Controller ••............•......•.•....••.......•.••..•.•...•.••
Tape Format ••.........•...•.•...............•.......•.............•...•...•.
Specifications and Leading Particulars •....................•.•....•.•......•.•......•
General Requirements •...•••..•.•.•.......•.•...••.•.••.•.•••.•..•..•...••...•
Fuse and Lamp Complement ••...•..•...••.......•..•.•.•••.......•.•.•.....•..•
1-1
1-1
1-1
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-6
OPERA nON AND PROGRAMMING ....................................................... .
2-1
2-1
2-2
2-1
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
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1-18
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1-20
1-21
1-22
1-23
1-24
1-25
II
Page
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-18
2':'17
2-18
2-19
2-20
'2-21
2-22
Controls and Indicators ......•.•...........................•..........•....•......•
Operator Control Panel Switches •....................•.........................
Auxi I iary (Maintenance) Control Panel Switches ................................. .
Swinging Front Door Interlock Switch ......•............•...•......•......•.•.••
Power Distribution Chassis Switches .•...••...•..•............•........•.......•.
Power Supply Switches and Fuses ••.........•........•..•........•.....•.... -:- ...
Manually Operated Interlock Switches .........•.•..•...•.•.•..•....... '••......•.
Operati ng Instructions .•......•......................•....•.•........•...•......••
Initial Turn-On Procedure ••.•.•..•..•....••..•...•.•..•......•.•....•.......••
Tape Preparation ••...........•........•......•.•..•........•.•...•.••.•.••.••
Reflective Markers •..•••....••.•..........•.....•.•.•.....••.•...•.•.... ;
Fi Ie Protect Ring •....•...............•........•..•..........•..•....•..••
Push-On, Pull-Off (POPO) Hub Assembly •...........•....•.•......•....•..••
Loadi ng the Tra nsport .....•...........................•..........••.•.......••
On-Line Operation •....•...•.••..........•••.••......•...•.••...•........•..•
Turnoff Procedure •......•.............••.......••.....•..•.••.•.......••.....•
PrQsramm·i·ng .•...........••..•.•..•.•.••••.•.•..•.•...•.•..•....•.•...••...•.•••
. Magnetic Tape System I/O Instructions and Responses •••...•...........•.••.•...•.•
Start Input/Output (SIO) ••.•....•.•..•. ' ..•.••...••••.••••......••......•••
Halt Input/Output (HIO) ••......•.•....•......•.•....•••........••.•.•....
Test Input/Output (TIO) ••.•..•...••...•.•.••.....•.••.....••.•.•.•..•.••.
Test Device (TDV) ••.••.•.•.•.•..•.•.....•..•....•....•.•...•.•.••.•..•.••
1-1
1-1
1-1
1-1
1-1
1-3
1-3
1-3
1-3
2-1
2-1
2-1
2-4
2-4
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2-6
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2-6
2-7
2-7
2-7
2-8
2-8
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2-9
2-9
2-10
SDS 901013
Contents
TABLE OF CONTENTS (Cont.)
Title
Section
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
2-32
2-33
2-34
2-35
2-36
2-37
III
ii
Acknowledge Input/Output Interrupt (AIO) ••••••••••••.••••••••••••••••••••••
Magnetic Tape System Conditions •••••••••.••••••••••.••••••.•••••••••••••.•.•••
Input/Output Address Recognition ••••••••••••••••••••••••••••••••••••.•••••
Station Operational ••••••••••••••••••.••••••••••••••••••••••••••••••.•••••
Station Ready •••••••••••.•••••••••••••••••••••••.••.•••••••••••••••.•••••
Control Ier Ready •••••.•••••••••••••.•••••••••••••.••••••••.••••••••••••••
Station Automatic. • • • . • • •• • • • • •• • • • . • • • • • • • • •• . •.•••••••••••.•••••••••••
Magnetic Tape System Orders •••.•.••••••••••••••••••••••••••••••••••••••.•••••
Order Codes •••••••••.••••••.••••••.•••••••••••••.•••••••••.•••••••.•••••
Order Descriptions ••••••••••.••••••••••••••••••••••••••••••••••••••.•••••
Termination of Order and Error Indications •••••••••••.•••••••••••••••••.•••••
Example of Control Line Programming ••••••.•••••••••••.••••••.••••••.•••...••••
Directive Sequencing •••••••••••••••••.•••••••••••.•••.•.•••••••••••.•••••
Program Execution ••••.••••.•.••••••••••••.••.••••.•••••••••••••••••.•••••
Control Line •••..•••.•••.••.••••••••.••.•••••••..•.••••.••••••.•.•.•.•••
Page
2-10
2-10
2-11
2-11
2-11
2-11
2-11
2-11
2-11
2-11
2-12
2-13
2-13
2-13
2-13
PRINCIPLES OF OPERA TION •••••••....•••••..•.•.•..•••.•••.••.•.••••••.•••••••••••..••••
3-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
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3-10
3-11
3-12
3-13
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3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
3-36
3-37
3-38
3-1
3-1
3-1
3-1
3-1
3-1
3-4
3-4
3-9
3-9
3-9
3-9
3-9
3-12
3-12
3-14
Introduction ••••..•••.••••••..••.••..••.•.••••.••.•.••••..•••••••••••••••••.•.•••
General Information ••.••.•••.•••..•••.•..•.••••••••••••...••••.•••.••••••••••.•••
Data Transfer Modes ••.•••.••.•.•..•.••••••••.••••••••.••••.••••••••.•••.•••••
Binary Mode ••.•••••••••••••.•.••••••.••••••.•••..•.•.••••••••.••••.•.•••
Binary Coded Decimal Mode •••.•.••.•••.••.••..•...••.•••••••••••••..•••••
Packed Binary Mode •••••••••••••••••••••••..•••••.••.•••..•••..••••..•••.
Power Circuits •.•.•••••••.•.••••••.•••••••••.••••••••••.•.•••••••••••.•.•..••
Primary Power ••••••••.•.•.•.••••...••.••••.••••..••••.••.•.•....••.•.•.•
Power Distribution •.••.••.••..••••••••••.••••••.•..•.••••••••••..•••.•••••
Turn-On Sequence •.•.••••...••••••.••.•.•..•••.•.••••.•••.••••.••...••••
Turnoff Sequence •••.•••••....•.•.•••••.•.••.••••.•.•.••••.••••.•......••
Station
Pneumatics •.....•••••..•.•••••..••••.•.••.•.•.••••.••••••.•.••.•••••••..••••
Positive Pressure System ••......••••••••.••.•.••••...•.••••.••••••.•....•••
Vacuum System •...•..•••.•....••••.•.•.•....••.•.•.•.••••...••••......••
Mechanics •....•.•...••..••.....••..••.•.•••.•.••••..•.•.••••.•••.•.••.•.•••
Capstan Moti on •••.••.•.••••.•.••.•••.•..••..•••..•.••••••.•..•.••..•..••
Reel Motion •.••....••••..••••.•....•.•.•.••.•.•.•••..•...••.•......•••••
Fast Motion ••••.•..•.•.••••.•••••••••..•••••••••.•.•.•••••.••..•...••.••
Load Opera ti on ••••••.•.••••.•••..•..•••.••.•.•.•.•.••.•••.•••••.....•.••
Heads •.•..•...............•.••.•.•..•.•.•....•..•.••..•..•.•.•....•....•...•
Read/Write Head •.•.••.•••••..•.•.••.•••.••.•••....•••.••.•.••.•.....••.•
Erase Head ••.•....••..•..•.•.••.•.•..•••.•.•••••.•••..•••.•.••••.•.•••••
Photosense Head ••..•..••.•...•••.••...••.••••••..•..••••.••••••.••.....•
Motion Electronics •.•......•.••..•••.•.•..•.•.•.••••...••••••.••••.•.••.•.•.•
Delay Count Register •••.•.••....•••.••.•.•••.••••.••.•.•.•.••••.••.....•••
State Counter ••.•••.•.•••••••.•••••••••.•.•.•.•...••..••••.•••...••.•...•
Station Selection •...•...••••••..•...••••••.•.•.••.•.•..•••.••.•.•.••...•.
Station Deselection ••..••..••..••.••••.•.•....•.•......•.••.•.•..•...•.•.•
Rewind Operation •..•.•••.••.•..•.•.•••.••.••.•.•.•••.••..•••••.••...•.••
Erase Operation ••..•...••...•.•..•.•.•.••••....•...•....••••..••••..•.••
Spacing Operation •••..•.••.•.•.•••.••.••••••••.•••••.....•.•..•.•..•...•
Controller •....•...••••••.•...•••••..•••.••••.••••••.•..•...•.••..•.•••.......•.•
Interface •.••••...•••.••...•..•••.•.••••..••.•••...•••••....••.•.•••••..•.•••
Data Path •......••••.••.••...•••••.•.••••••.•..•.•.•.••••.••.•.•.•.•••••
lOP-Controller Si gna Is •••••...••.•.•••••••...•••...••.•.••.•.••••.•.•.•••
Controller-Station Si gna Is •••..••••••.••..••..•••••.•.•.•.•..•••.•••..•.•••
Interface Disconnect •.•.••••.••••••.•.•••••.••.••.•.••.•.••..••..•..••.••
3-14
3-23
3-29
3-30
3-33
3-34
3-34
3-34
3-34
3-34
3-38
3-41
3-41
3-42
3-45
3-46
3-46
3-47
3-49
3-49
3-54
3-55
50S 901013
Contents
TABLE OF CONTENTS (Cont.)
Title
Section
3-39
3-40
3-41
3-42
3-43
,MAINTENANCE AND PARTS LIST ........................................................•
3-56
3-56
3-60
3-62
3-64
3-64
3-64
3-64
3-71
3-71
3-71
3-76
3-80
3-83
3-83
3-88
3-90
3-91
3-95
3-95
3-95
3-101
3-105
3-105
3-106
3-107
3-110
3-110
3-119
3-130
3-131
3-133
3-136
3-136
3-138
3-143
4-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-1
4-1
4-1
4-6
4-6
4-9
4-9
4-9-4
4-9 '-.
4-10
4-10
4-10
4-10
4-10
4-10
4-11
4-11
4-11
4-11
3-44
3-45
3-46
3-47
3-48
3-49
3-50
3-51
3-52
3-53
3-54
3-55
3-56
3-57
3-58
3-59
3-60
3-61
3-62
3-63
3-64
3-65
3-66
3-67
3-68
3-69
3-70
3-71
3-72
3-73
3-74
IV
Communication Cycles •.•.•....•.•....•.....•....................•.••.....•.••
Start Input/Output (510) .•.••••.•.••••....•.•..•.•••..•.•....•••••.•....••
Acknowledge Input/Output {AIO) •••.•.....•...•....•.....•.•..•..........•.
Acknowledge Service Call (ASC) ••.•..•.•..•.•.....•............•.•.•......
Service Cycles .•.••.•..•.•..•...•....•...............•.......•..•...•......•.
Order Input •..•.•.•.•..•••.•.•.....••.•..••.....•...........•.•.......•.
Order Output ........•..•.•....•......•.............•........•.........•.
Data Input and Data Output ••.•.•..•......................•..•••.•......••
Terminal Order .•.•....•.......••••.•............•.....•................•
States •...••....•......••.......•....•......•......•.............•........••
OOFOOU, Idle or Ready ••...........•......••......•........•...•........•.
01 F01 U, Order Output •......••...................•...•..•......•.........
01 F02U, Waiti ng for Device Ready ••........................................
01 F03U, Waiting for Device Proceed ••..............•.....•.•...............
03F03U-02U, Data Transfer .•...•...•......................................
03F01 U, Order Finalization .........•......................................
03FOOU, Station Fina lization •....•.......................................•.
01 FOOU, Order Input ..•..................•.........•.............•........
Magnetic Tape System Functions •.•.................................................
Station Data Electronics ...................................................... .
Writi ng Operation ....•...........................•.......................
Reading Operation ..•..................................•.................
Controller Data Electronics •...................................................
Genera I Description .....................................................•
Mode Control •...........................................................
Memory Access ......•...........................•.......................
Clock Signal ........................................................... .
Write Operations ......•..........................•.......................
Read Opera ti ons •....•......................................•..•.........
Pack Mode ..........................•...........•...............•.....••
Error Detecti on •.....•....•.•.•..•...............•.•......•.............•
BCD-EBCDIC Conversion Charts ...........................•.......•......•.
Glossary ofrl:erms ........•.........•.................•......................•
S and~Chassis Terms ••.....•....•.•......•••...........•................•
Yand Z Chassis Terms ••.................................................•
V and W Chassis Terms •.......•....•....................................••
Page
Introduction ................................................................... .
Cabling ................................................................... .
Module Location ............................................................ .
Preventive Maintenance .......................................................... .
Cleaning Procedures ......................................................... .
Corrective Maintenance .......................................................... .
Preliminary Checks .........................................................••
Resistance Checks ....................................................... .
Voltage Check .......................................................... .
Mechan.ical Adjustments ..............•......... '.............................•.
Vacuum Chamber Door Adjustment .....•....................................
Vacuum Level Adjustment ...................•............................•
Vacuum Valve Adjustment ................................................•
Write Enable (Fi Ie Protect) Switch Adjustment ...............................•
Positive Pressure Adjustment •.............................................•
Head Cover Actuator Adjustment ...................•......................•
Fi Ie Reel Hub Holddown Adjustment ........................................•
Fixed Reel Check ...................•............•.......................
Reel Motor Drag Torque .•........................•.....................•.
iii
SDS
Contents
901013
TABLE OF CONTENTS (Cont.)
Title
Section
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42
4-43
4-44
4-45
4-46
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iv
Electrical Adjustments, Transport •••••••••.•..••••••••••••••.•••••••.•••••••••••
Transport Clock Adjustment ••.•••.•••••••••.•.••••.•.•••••••••..••.•••••••
Photosense Lamp Current, BOT and EOT Adjustments •••..••••••.••••••••••••••
Capstan Dead Band Adjustment •••.••.•.••••.••••••.•.••••••.•••••••••.•••••
Preliminary Capstan Speed Adjustment ••••••••••....••••••.••••••••.•••..••••
Oscillation Check •••••.•••••••••.••••.•••.••.•••.••••.••••..•••••••••.•••
Reel Servo Amplifiers Zero Adjustment ••••.••••.•.•••••••.•••••.•.••.•.•••••
Fixed Reel Servo Amplifier Tape Loop Positioning Adjustment •..•.•.••••.•.•••••
File Reel Servo Amplifier Tape Loop Positioning Adjustment •.•••..••••.•••.•.••
Load One-Shot Adjustment (SAS and 0.22 Sec One-Shots) •.•••• ~ ••••.•.••••
Load Function Test •.•..•••.•.••••.•..••••••••.••••.••••••••.•.••••••.••••
Rewind One-Shot Adjustment (0.8 Sec 0-5, Both Delay, Backups, and F Delay) •••
Write Enable (Fi Ie Protect) Check ••••.••••••••.•..••••••••••.••••••••.•••••
Electrica I Adjustments, Controller ••..•.•.•.••.••.•••.....•...•••••••••.••••.•.•
Module Location •.••..•••...•••..•••.•.••.•.•...••.•.•.••.••...•••.••.••
Clock Osci llator Check ••••...•.•••.••••.••.•.•.•.•..•••.••.•.•.••.••••.••
Controller Checkout Wi th lOP •••.••.••••...••.•.•.••••......•••.•.......•.
Station Logic Adjustments •..•••••••••...••.••.•.•••...•.•••••••..••••••••..•••
Tape Tracking ...•.•.•.•......••.•..•...•. ' •..•••..••..••••••••••....•..••
Capstan Speed Check and Adjustment ••..•..••.••.•..••••....••••••.••.•••••
Ramp Adjustment for Acceleration and Deceleration •••....•.•.••.•.•.•.••••.••
Master Clock .••........••••..••.••.•..••.••...•...••..•.•••.••••.•.•••••
De lay Counter •....•.•........•..•....•.•..•...•...•.••••..•...••••.•.•••
Device Ready Latch •.•.••..••.••.•..•.•.•.•••..•...•.••.•••.•..•.•...•.••
Station Address Selecti on ...•...•..••.•...•••••......••..••.•........•••••
Station Connect •................•.•.•.....•.•..............••..........••
Starting Delay Check .•....•...•....•....•.......... " ....••......•.•...••
Read/Write Ampl ifiers •.•.•...........•.............•.•...••...••...•...••
Threshold Adjustment For Read Amplifiers ..•......................•...•...•••
Deskew Adjustment •................•.....•.............•..•.......•..•.••
Forward Read Deskew •......••......•.•••..•..........•........•.••...•.••
Reverse Read Deskew .•........•......•..•.•.....••............•....•...••
Write Deskew •••.....•..•.•......•.•.••.•.•.••.•••...•..•......•..••..•••
Ending Delay Check ..•.........•........•.••....••..•.•.••••.•.....•...••
Operator Control Panel Indicator Check .•..•..•.•..... " .•......•.•......••.
Peripheral Equipment Tester Operation .......••...............................••
Prep~ration and Connection ••................•.............•••.•••..•.....•
Overlay ......................................................•..•....••
On-Line/Off-Line Switch .•........•.............•........•..•...•.•..••••
Write Operation ..................•...•.•......••..•...................••
Read Forward Operation ••.•........•....•......•••........••...........••
Space Reverse Operation ........•......•.•..•.....•......•....•.........••
Removal and Replacement Procedures ........•......•........•...............•..
Tape Guide Removal and Replacement ••....•...•..•.•.••..........•.•.•..••.
Write Enable Switch Removal and Replacement ••....•.•..•.......••.•.•....••
Reel Motor Brake Removal and Replacement ••.•....••.........•••.....•....•.
Reel Motor Brake Adjustment ••........•.......•...•••......•••..•........••
File Reel Holddown Knob Removal and Replacement .•••..•.•.•..•........•..•.
Fixed Reel Removal and Replacement •••......•.••.•.•...........•.•....•....
Reel Tachometer Removal and Replacement .•....•..•...•......•.•....•.•..••
Capstan Motor Removal and Replacement ••.•.••...•...••.•••....•....•••.•••
Capstan Tachometer Removal and Replacement .•.....................•........
Positive Pressure Pump Removal and Replacement •.......•.......•...........••
Reel Motor Removal and Replacement ••...•...•..•.•.•.•..•........•.••...••
Read/Write Head Removal and Replacement •.•••....•••.•.•......•..•.......•
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SDS 901013
Conte nts-I II ustrat ions
TABLE OF CONTENTS (Cont.)
Title
Section
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Photosense Removal and Replacement •........•...........•.•.•....•........•
Erase Head Removal and Replacement ........•........•..........•.•.......••
Parts Li st ...•.......•.................................•...................•......
Tabular Listings •......•.•.............•......•........•...............•..••..
III ustrations ••...................••.•.•..•.................•.•.•....•.•.......
Manufacturer Code Index •••.......•....•.............•.•......................
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LIST OF ILLUSTRA nONS
Figure
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Title
Magnetic Tape System Model 7371/7372/7374, Front and Side Views ......•......•.....•.........
Magnetic Tape System Model 7371/7372/7374, Rear View .•..•..........•..... " .............. .
Magnetic Tape System Block Diagram .•.•...............•....•...•••....•....................
Physical Spacing on Tape •.................................................................
Operator Control Panel, Front View •...............•........................................
Interlock Network •...........•....•...............................•............•..•......
Location of Reflective Tape Markers ....................•.............•.•..........•.........
Fi Ie Reel and Fi Ie Protect Ring ••............................................................
papa Hub Assembly .................................................•....................
Tape Path ........•..........•...............•.................•..........................
Control Line, Flow Chart ..............•....•...............................•..............
Data Representation on Tape, Binary Mode ...................................................•
Data Representation on Tape, Decimal Mode .............. " ................................. .
Data Representation, Packed Binary Mode ................................................... .
Power Distribution Chassis, Schematic Diagram ............................................... .
Power Sequence, Timing Diagram •...........................................................
Magnetic Tape Transport, Back View .........................................•..............
Pressure Regulator ........................................................................ .
Tape Guide ..................•......................•....................................
Head Cover Actuator ............................................................•........•
Positive Pressure Switch ....................•..............................................
Write Enable Switch Actuator .........................•....................................
Relay and Interlock Functional Diagram ................................•.....................
Station Transport Motion Control, Block Diagram ....................................•.........
Station Motion, Functional Dia!=jram ....................•...................................•
Direction Latch .......................................................................... .
Capstan Servo, Functiona I Diagram ......................................................... .
Reel Servo, Functional Diagram •............................................................
Vacuum Chamber, Tape Position Switches ..................................................•..
Vacuum Switch ............................•..............................................
POPO Hub Assembly ....................................................•.................
Load, Functiona I Diagram •.................................................................
Station Status, Functional Diagram .......................•........................•.........
De lay Counter, Logi c Di agram .•............................................................
State Counter, Logic Diagram ..............................................................•
Device Selection and Device Ready, Logic Diagram ....................•.......................
Rewind On-Line With Interrupt, Block Diagrarri .•..............................................
Magnetic Tape Controller, Block Diagram .................•....•..•..........................
Magnetic Tape Controller States, Simpl ified Block Diagram. " ....................•............•
Subcontroller, Simplified Functional Block Diagram •......................•....................
Typical I/O Interconnection ...•............................................................
lOP-Interface Signal Lines Diagram ........................................................ .
Connect/Disconnect Timing ............................................................... .
Communication and Service Cycle Sequence ..........•......................................•
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v
I II ustrati ons
SDS 901013
LIST OF ILLUSTRA nONS (Cont.)
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Title
SIO, HIO, no, and TDV, Flow Diagram ••••...••..•..••••••.....•..••.••••.•.••••••.•...••.•
SIO, HIO, no, and TDV Interface Signal Sequencing •.•.•..••.•...•.•.•••.••.•.•..•..•••.•.•••
AIO Operation, Flow Diagram •...•..••••.•.••.•.....•••....•..........•.•.••••.•••....•...•
AIO Interface Signal Sequencing ••...•••• : •.••••.•.•..•••...•..•.•.•..••••••••..••...•..•..•
ASC Operation, Flow Diagram (Prior to Service Connection) ••.••...•••.••.•••.•..•..••.••.•.•.•
FSC Interface Signal Sequencing •.......••.•.••••••.••••••.•.•••..•.••••••.•.•..••...•..•.••
Service Cycles, Timing Diagram ••.....•....•••.••....••••......•.•.•••....•..•...•.•.•.•..••
Service Cyc Ie, Timing Sequence (One Byte) ••...•.........•.....•.•..•...•..•..............••
Order Input Operation, Flow Diagram ••.•...••.•••••...••.•••..•...••••••••.••..••....•.•.•••
Order Output Operation, Flow Diagram ••.•....•••.•.••••.•.•.••.•.•.••••.•••....•.•..•.•.•••
Data Input Operation, Flow Diagram ..•.•..•...•••.•..•••.••••.•••...••.•.••••••.••.•.•.•.•.•
Data Output Operation, Flow Diagram ........••••....•••••.••••.••.•...••••••••••...••.•...•
Terminal Order Operation, Flow Diagram ••.•..••••••.•••.....•••..••...•.•.•.•..•.•.••.•...•
Magnetic Tape Controller States, Flow Diagram •.•.•.•.••••.•.•..•.•.•••••••••.•...•.•••.••.•.
SIO Operation, Flow Diagram .•.......•••.•...••...•.•••.•..•.•.•••.••••..•..•..•.•.•.••.••
OOFOOU State, Timing Diagram ........ '..•.••.•.•....•.•.•...••.•......••••••...•.•.•••..•...
01 F01 U State, Flow Diagram ..•........••••....•.....•••....••.....•.•...••.•....•....••.••
01F01U State, Timing Diagram ••.....•....•.•.•••••.•.•••••..•...•.•.•..•••••........•.•.•.•
01F02U State, Flow Diagram .•.•.........•.•.•••.••.••••...•..•...•.•..•••••.•.••...•.•...•
01 F02U State, Timing Diagram .•........•.•....•.....••••...••.•.•...•..•..•••..••.........•
01 F03U State, Flow Diagram •....•.•..........•..•...••..•.•..•••.•...••.•........•.•..•..•
01 F03U State, Timing Diagram ....•...••.•••..•.•.•....•.•.•..•........•...•..•......•.•...•
03F03U-02U State, Flow Diagram ......•..•....••.....••....••••........••••••...•.•......•.
03F03U State (Space Fi Ie), Timing Diagram ..•.•.••.•.•.•.•..•.•.•......•..•.•................
03F03U State (Space Record), Timing Diagram .•.•••..•.•.•...•..•............••.•••..........•
03F01 U State, Flow Diagram •........•.•....•.••.•.•.••...•••......•.•.•••••..•.......•....
03F01 U State, Timing Diagram ............................................................. .
03FOOU State, Flow Diagram ..........•....•........•.•......•............•................
01 FOOU State, Flow Diagram ........................•....................................•.
01FOOU State, Timing Diagram .........•...•....•......•...................•...........•....
Read/Write Operation, Flow Diagram ...•...............•••..•..........•......•........•...•
Write Operation, Flow Diagram .•.............•••......•.•..•........•...•.•..•........•....
Write Deskew and Write Head Interconnect, Logic Diagram ••..............•....•......•.•.•....
Read Operation, Flow Diagram ••........•.•...................••.....•.....••.•........•...•
Read Head Interconnect, Logic Diagram •........•....•••..••.••...•......•.•........•........
Controller, Block Diagram ...•........••.......••....•..•...............••.•..............••
Memory Access (Controller and Station), Timing Diagram ••........•.....•......•...............
Write Start (800 bpi), Timing Diagram ..........................•..•......•..........•......•.
Write Operation (800 bpi), Timing Diagram .•..........•.•....•.•....•.••....•..•........•....
Write Finish BIN or BCD Mode (800 bpi), Timing Diagram ••.•.............•.•.••...........•....
Write Finish Pack Mode (800 bpi), Timing Diagram ••......•.•..•...••.....•...•......•....•...•
Write Tape Mark (800 bpi), Timing Diagram ••.....•.•..••.••.•.•.•.•.•••.....•................
Read Start, Timing Diagram .•...................•....•......•.•........•...•....•...........
Read Operation, Timi ng Diagram .......•...••.•••.•.••••••..•.....•.••••.•.•......•.........
Read End (BIN, BCD, or Pack, 4n Characters Read), Timing Diagram •............•....•.....••....
Read End (Pack, Not 4n Characters Read), Timing Diagram •..................•.•................
Station Interconnection Diagram .......•.•......•.•.•..•.••••...•.•........••...•.•....•...•
Magnetic Tape Station Wiring Diagram ••.....•..••.......•......•....•.....••.•.............•
Module Location Chart ..........•.......•.•...•.....•.•.•.•..•...•.•.....•......•..•....••
Waveforms, Capstan Speed Adjustments •••....•.•••....••••...•......•••.••.•...•......•.••...
Waveforms, Ramp Adj ustment •..•....•.•••.••.•••.•..•.•.•..•..••.•.........•.•...•..•.••..•
PET Magnetic Tape Overlay No. 12 ••........•.••.•...•••....•......•.•.•..•...............•
Reel Motor Brake, Exploded View .•.....•...•..••.....•.•.••••........•.•.••...•.•....•...•.
Reel Motor Brake, Reassembly •......•.••........•.•.•..•.•.•••••••.......•.•.•.............•
File Reel Hub .•......•....•........•••.•..•.••.•.•.•.••.••.••••.•.....•.•.•....•.••••••.•
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SDS 901013
IIlustrations-Tables
LIST OF ILLUSTRA nONS (Cont.)
Figure
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Title
Capstan Tachometer Mounti ng Position ••••••••••.••••••.••••.•••.••••••••.••••••.•.•.•••••••
Transport Front View •••..•••.••.•..••.•.••••••.••••••••.••••.••••••••.••.•.•••.••••.•••••
Transport Rear View ••.•..•.•.•.••.••••••••••..•••.•••.••••••.•••.••••••••••••••••••••..••
Transport Wiring Diagram •..•.....•..••••••.•••••.••••••••.••••...•••••••••••••••.••••••.••
Photosense Assembly •••••..•••••.•.•••..•.••••••.••••••••.•.•••••••••••••.••••.•.•.•••..••
Capstan Motor Assembl y ••.•.••••••••••.•••.•••••••••.•.•.•••••••••••.••••.•.••••••••.•••••
Erase Head Assembly •••.••...•.••••.•.•........•••••••••.•.•••.•••••••••.•.••••••.••.•••••
Read/Wri te Head Assembl y ••.••..•.•.••••••.••...•••.•••.•.••....•.••••••••.•••.•.••••.•••
Auxiliary Control Panel Assembly •••••.•••••••..•..•••.••••...•••.••.•.••••.•.•••••••....•••
Reel Tachometer Assembly .•...•.•••..•••.••••••.•••••••••••••.•....•.•.••••.•••..•.•....••
Blower Shelf Assembly ••.••.••••.•.•.•.•.•.••.•.•.•..•.•.•.•..•...••••.•••••.••••.•••••.••
Blower Shelf Schematic •....•...••••••...••••.••••••.••••••••.•••••••••••••••••..•••.•..•.
Operator Control Panel Assembly •.•.••••••..••.••.•.•.•••••••••..•..•.••••.•••••.••.•....••
Operator Control Panel Schematic .......•.•••..•...•.......••••..•.••.•.••••.••••••••.....•
Power Distribution Chassis Assembly ••..•••••••.••..•••.••••.••••.•.•.•.••.•.•.••....••.•.•.•
Relay Chassis Assembly ••.....•......••...•.•.•.•.....••.•.•.•........•.......•...•.•.•..•.
Relay Chassis Schematic •...•.•.......•.•.•.•..•......•.•••..•••••.••••.••...•••.••••••..••
Transport Drive Electronics Assembly ........••••...•.•.•..•.••••..••.•••••••••••.•••.•.••.••
Transport Drive Electronics Schematic ..•.•.•.•..•••.•..•.•.•..•...•.••••.••••••••.•.••.•..••
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4-60
4-61
4·-63
4·-64
4-67
4-71
4-72
4-75
4-76
LIST OF TABLES
Table
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
4-1
4-2
4-3
4-4
4-5
4-6
4-7
Title
General Requirements •...•..•........•.•.••••...••...•••••.•....•.•.•....•..•..••.•...•••
Parameter Definitions and Specifications •..••.•.••.••.•.•••••••...•...•••••.....•..••..•.•.•.
Operator Control Panel Switches and Indicators ••..•.•••.••••.•.•••...••.•....•...•.••...•....
Auxi I iary Control Panel Switches ..•.........••••..••..••.••••....•.•.•........•........••••
Power Distribution Chassis Switches •......•.•.•....•.•.•••..•.••...•.•••••.••..•...•..••••••
Manually Operated Interlock Switches •.•.••••.•...••••••••.•..•....•••......•...••....•.•••
Status Responses, SIO, HIO, and TIO Instructions ••..••..••..•..........•.•....•.•........•.••
Status Responses, TDV Instruction •.....•..••••..•......•..••.•••...•••.••....•••..........••
Status Responses, AIO Instruction ..•.......•....•...•..•.•.••••••.••••••.••...•.•.••••••..•.
Input/Output Order Bytes ••..............•....•...••...•.•.•.•....••••••••••.•.••..•••••..
BCDIC to EBCDIC Conversion ...........................•.•.•.•••..•...•...••.••••••••...••
Delay Count Register Data ............•.••••.•.•......•••..••..••.....•.•.••.•...•.••.•...•
State Counter Data ..•••..........••.•..•••••.•.••...•.•..•.•.•..•••.•..•••••••.••.•••..••
Subcontroller Connector/Cable/Module Identification •.•.••••.•••....•.•.••••.•••....•.•.•...•
Subcontroller Interface •..........•.....••••....•.•.•.•••....•....•.•.••...•.••...•.......•
Transport Modes ..•.....•...............••.•.....•...••...•.......•...••.......•.......••
Magnetic Tape System Interface Signals ••......•.....•.••.•..•.•.....••........•..•...•.....
Buffer Register Status During Write Pack Mode ••........... " .•......•...•...•.•............•.
Buffer Register Status During Read Pack ................•.•..•.•.•....•.••••...••..•..•••••••
EBCDIC-BCDIC Conversion (62 Set} •...••..•.•••...•...•.•.•.•••....•...•••..••' ••...•..••...
Sigma BCD-EBCDIC Conversion Chart ..•..•......•...•..•.•..•..•..•..•......•.............•
Sand U Chassis Glossary of Terms •...•..•...•..•...•........•....•••.••..•.••.•.•....•...••
Yand Z Chassis Glossary of Terms ••........•.•.....••.•.•....•......•.•....•.•... , ........ .
V and W Chassis Glossary of Terms •........••...•...••...•.•••.••.••••.•.••..•..•.••......•.
Tools and Test Equipment ••.......•..........•....•...•.•..•.•.•.••...•....•••.•.•..•.....•
Cleaning Equipment ••...•.•.........••.•••••.•.•.•....•....•.•...•.••.....•.•..•..•••....
Station Interconnecting Cables •...•......•••..•.•.......•...•.•••.•...........••..•.••.•..•
Visual Inspection Information •........••.•••.•.•..•••.•...•..•.•.••...•.......••.•..••••.••
Preventive Maintenance Schedule •...•.•••••.••....••••••.....•••..•.•••.••••.....••.•.•.••
Tektronix Oscilloscope Control Desi gnations ••.••.•..•..••.••.••.......•.•.••••......••..•...
Rewind One-Shot Adjustments •.......••.••••••••.•••..•.•.•.•.••••••.••.•........•.•.•.....
Page
1-6
1-6
2-2
2-4
2-5
2-5
2-9
2-10
2-10
2-11
3-4
3-34
3-38
3-47
3-51
3-54
3-54
3-117
3-129
3-133
3-134
3-136
3-138
3-143
4-1
4-1
4-5
4-6
4-8
4-10
4-14
vii
Tables
SDS
901013
LIST OF TABLES (Cont.)
Table
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42
4-43
4-44
4-45
viii
Title
Delay Counter Access ••..•...•..•.•••.••.•••.••••••••••••..••.•.•.•.••.•.•.••••••.••••••••
Address Selection ...••.......•....•.••••..•.••••.•.••.•.•..•.•••.•.••.•.•...•.•••••.••..••
Station Connect Test •.•..•.•.•....•.••...•...•.•.•.••.•.•.••..•..•....•.•.••••.•••.•••..••
Read and Write Amplifier Access Pins ••••••.•...••••.•••••.•.••••.•...••••••.••••••••••••••••
Deskew Access Pins ••••.••..•..••...•••••••.•••..•••.•••••..•.•....•.•••.••.•••.•....•.•••
Write Deskew Switches ..•.•....•..•.•.•.•••..••.•••••••.•.•....•..••.•••••..••.•••..••..••
Ending Delay Logic Terms •.•....••....•..•••••••..•.••••.•.•••.••••.••••.••..•••••••••••.••
PET Data Patterns ........•••••..•.•.•......•••• ~ •.•.•••.••.•.••.....•..•.••••••••...••.•••
PET Functions •...•.•.•...•.•••..••.••••.••••••.••.•.•••.••••.•.••.•••••....•.•.•••••••••.
Overlay Indicators ....•.•...•...•••.••.•.•...•..•.....•.•..•.•..•.•.••••.••••••••.•.•••.••
Magnetic Tape System •••.....•..•.••••••••.•.••••..•.••..•.••••.•••••••••.•.••..•.•.•••••.
Magnetic Tape Transport Assembly, Replaceable Parts •.•.•.•..•....•.•.••••••.•.••••••••.••.•••
Photosense Assembly, Replaceable Parts •••.••.•.••.•••.....•..•.••.....•..•.•...•......••••.•
Capstan Motor Assembly, Replaceable Parts •.•..•.•..•••.••••••••.•.....••.•.•..•..••...••..•.
Reel Motor Brake Assembly ..•••...•.•••.••.•.••.•.•...•..•.••.•.•......•••.•••.••.•.••••.•
Auxil iary Control Panel Assembly, Replaceable Parts .•..••.•..••••••.•..•.•...•..•.•.•....•.••.
Tachometer Assembly, Replaceable Parts ••...••...•.•.•.••••••••..•.•...••.•....••.•..•.••••..
Fixed Vacuum Chamber Assembly, Replaceable Parts ••..•.••.•••.•.•....•••.•.•..•.•..•...•.•••
Fi Ie Vacuum Chamber Assembly, Replaceable Parts ••.•...•••.••.•.........•.•.•..•.•.•••.••..•.
Blower Shelf Assembly, Replaceable Parts •.•...•.••.•..••••....•.••.•...•..•........•.•••••.•.
Operator Control Panel Assembly, Replaceable Parts .•....•......••..•..•.•....•.•........•.•••
28" Cabinet Assembly, Replaceable Parts ..•....••....•..•...•..•.•....•.•.•..••....•..•••.••
Power Distribution Chassis Assembly, Replaceable Parts •••.•..••...•...•..•.•••...••...••.••••••
Relay Chassis Assembly, Replaceable Parts ••...•..•.••.•..•............•.••.•...•••......•..•.
Transport Drive Electronics Assembly, Replaceable Parts •..................•....•.•....•...•...•
Forced Convection Heatsink Assembly, Replaceable Parts •.••........•...•......••.....•..•...••
Rectifier Heatsink Assembly ......................•..•.•....•.................•........•..••
Swing Frame Assembly, Replaceable Parts ....................•....•........................••
Station Electronics Assembly, Replaceable Parts •................................•.............
Station Electronics Chassis S Assembly, Replaceable Parts •.............................•......•.
Station Electronics Chassis U Assembly, Replaceable Parts •.................•......•........•....
Controller Electronics Assembly, Replaceable Parts •..•....•..•.......................•.......•.
Controller Chassis V Assembly, Replaceable Parts .........••........•...............•.•......••
Controller Chassis W Assembly, Replaceable Parts •........•......•.•.•...................•.•..
Controller Chassis Y Assembly, Replaceable Parts ..••...•......•........•.....................
Controller Chassis Z Assembly, Replaceable Parts ••.•.............•.•......•.........•......••
Front Door Assembly, Replaceable Parts ••..........•....•............•....•......•..•.......•
Manufacturer Code Index .•.............•.............•...•..••....•..........•...•........
Page
4-18
4-19
4-19
4-21
4-22
4-23
4-23
4-29
4-29
4-30
4-40
4-43
4-47
4-51
4-55
4-56
4-57
4-58
4-58
4-59
4-62
4-65
4-65
4-69
4-73
4-77
4-77
4-78
4-78
4-79
4-80
4-81
4-81
4-82
4-83
4-84
4-84
4-85
SDS 901013
Related Publ ications
LIST OF RELATED PUBLICATIONS
The following publications contain information not included in this manual, but necessary
for a complete understanding of the Magnetic Tape System Model 7371/7372/7374.
Publication Title
Publication No.
Power Supply Model PTl6 Technical Manual
901080
Power Supply Model PT18 Technical Manual
900866
Power Supply Model PTl9 Technical Manual
900867
Peripheral Equipment Tester Model 7901
Technical Manual
901004
Sigma Computer Systems Interface Design Manual
900973
SDS Si gma 2 Computer Reference Manual
900964
SDS Sigma 5 Computer Reference Manual
900959
SDS Sigma 7 Computer Reference Manual
900950
SDS Sigma 2 Computer Technical Manual
900630
SDS Sigma 5 Computer Technical Manual
901172
SDS Sigma 7 Computer Technical Manual
901060
Sigma 5 and 7 Magnetic Tape Test (7-Channel)
Diagnostic Program Manual
901165
Sigma 2 Magnetic Tape Test (7-Channel)
Diagnostic Program Manual
901536
7-Track Magnetic Tape Systems Models
7361/7362/7371/7372 Reference Manual
for SDS Sigma Computers
900978
Diagnostic Control Program for Sigma 5 and
Sigma 7 Computer Peripheral Devices Reference
Manual
900712
ix/x
Paragraphs 1-1 to 1-8
SDS 901013
SECTION I
GENERAL DESCRIPTION
1-1 INTRODUCTION
the four additional chassis (V, W, Y, and Z) that comprise
the magnetic tape controller. (See figures 1-1 and 1-2.)
1-2 SCOPE OF MANUAL
This publication describes the Magnetic Tape System Model
7371/7372/7374 (figures 1-1 and 1-2), designed and manufactured by Scientific Data Systems for use with Si gmaseries computers.
1-3 RELATED PUBLICA nONS
The publications listed in the front matter contain information necessary for a complete understanding of the magnetic
tape system.
1-4 PURPOSE AND BRIEF DESCRIPTION
The magnetic tape system provides medium-speed (75 ips)
input/output faci I ities for SDS Si gma-series computers. It
may be used for program storage, as inputs to sorts and
merges, for large data processing files, or as scratch or
working tapes. Data is written and read in IBM-compatible
tape format. The magnetic tape system records data on and
reads data from standard 1/2-i nch, seven-channe I magnetic
tape having a recording density of 200, 556, or 800 bits
per inch. Binary and decimal (BCD) are the two standard
read and write modes of operation for the model 7371/7372;
packed binary reading and writing is an optional feature
(model 7374).
The basic magnetic tape system is made up of the Magnetic
Tape Controller Model 7371 and the Magneti c Tape Station
Model 7372. A more extensive system may be formed by
interconnecting up to eight magnetic tape stations, with
complete control of the system originating from the magnetic tape station that contains the magnetic tape controller.
In this manual, the 7371 magnetic tape controller will be
referred to as lithe magnetic tape controller" or lithe controller ll ; the 7372 magnetic tape station will be identified
as lithe magnetic tape station" or lithe station."
1-5 PHYSICAL DESCRIPTION
1-6 GENERAL
The basic magnetic tape system is contained in a standard
Sigma cabinet 63-1/2 inches high, 29-1/4 inches wide, and
35 inches deep, having front and rear access. The tape
transport mechani sm is mounted at the front of the cabi net.
Access to the tape handling portion is provided through a
sliding glass door. A swing frame at the rear of the cabinet
holds the two chassis of station electronics (S and U) and
When more than one station is used in the system, they are
bolted together, side by side, and side panels are provided
for the two outside ends only. The station containing the
controller is located nearest the center of the system. The
weight of a magnetic station alone is approximately 850
pounds; the weight of the basic system (magnetic tape
station with controller) is approximately 950 pounds.
1-7 MAGNETIC TAPE STATION (See figures 1-1, 1-2,
and 3-6)
The station consists of the main components described in
paragraphs 1-8 through 1-17.
1-8 Transport Assembly
The transport assembly is mounted on the top front portion
of the station. It includes the following:
a. Main transport casting on which the transport
components are mounted (figure 1-2)
b. Reel hub assemblies, reel motors, and reel tachometers (figure 3-6)
c. Tape drive capstan, capstan motor, and tachometer
(figure 1-1)
d. Read/write head assembly (includes tape cleaner)
(fi gure 1 - 1)
e.
Tape guides (figure 4-11)
f.
Ph~rosense
g.
Write enable switch (figure 1-2)
h.
Magnetic head cover actuator (figure 1-2)
i.
Positive pressure switch (figure 3-10)
j.
Swinging door interlock switch (figure 1-1)
k.
Auxiliary control panel (figure 1-1)
assembly (figure 4-11)
1-1
16
:=:]17
2
.
I
3
8
4
13
5
(/')
o
(/')
-.0
o
14
o
w
15
C
::J
c..
FRONT VIEW
SIDE VIEW
(/')
0:
(J)
<
1. FIXED REEL HUB
7. FILE REEL HUB
13. BLOWER SHELF
III
2. CAPSTAN AND TACHOMETER
8. STATION TRANSPORT
14. TRANSPORT DRIVE ELECTRONICS
3. TOP DOOR SWITCH
9. READ;WRITE HEAD ASSEMBLY
15. POWER SUPPLY PTl9
4. FIXED TAPE STORAGE VACUUM CHAMBER
10. SWINGING DOOR INTERLOCK
16. RE LAY CHASSIS
5. BOTTOM DOOR SWITCH
11. AUXILLARY CONTROL PANEL
17. STATION ELECTRONICS
6. OPERATOR CONTROL PANEL
12. FILE TAPE STORAGE VACUUM CHAMBER 18. CONTROLLER MODE L 7371
~.
SDS 901013
Paragraphs 1-9 to 1 - 12
POWER SUPPLY PTl6
TRANSPORT
CASTING
1
STATION
j_ELECTRONICS
WRITE
ENABLE
SWITCH
V""~
W
HEAD
COVER
ACTUATOR
CONTROLLER
ELECTRONICS
Y
z
POSITIVE
PRESSURE
PUMP
POWER DISTRIBUTION CHASSIS
POWER
SUPPLY
PT19
901013A.102
Figure 1-2. Magnetic Tape System Model 7371/7372/7374, Rear View
1-9 Operator Control Pane I (Fi gure 1-1)
c.
Vacuum switches (Figure 3-6)
The operator control panel is mounted on the front of the
station above the station transport main casting. The panel
consists of switches for operating the station and lamp
indicators for displaying the current status and condition
of the station. It provides the necessary control signals for
address selection, loading, unloading, and rewinding, as
well as the signals needed for switching the station on-line
or off -Ii ne.
d.
Vacuum plenum {located at bottom front of station)
1-10 Vacuum
1-11 Positive Pressure System (Figure 1-2)
Positive air pressure is generated by the positive pressure
pump and is fed to the air plenum in the main casting. The:
plenum supplies air to the tape guides and operating
pressure for the head door actuator and positive pressure
interlock.
Syste~
1-12 Blower Shelf Assembly (Figure 1-1)
The vacuum system includes the following:
a.
Vacuum blower (fi gure 3-6)
b.
Tape storage chambers (figure 1-1)
The blower shelf assembly is mounted at the front center
portion of the station behind the tape vacuum chambers.
Mounted on the blower shelf assembly are the positive
pressure pump and the vacuum blower.
1-3
Paragraphs 1-13 to 1 -24
SOS 901013
1-13 Relay Chassis Assembly (Figures 1-1 and 4-25)
The relay chassis assembly is mounted at the top left center
side of the main frame. It contains the ac interlock, ready,
speed, rewind, dc interlock, and file protect relays.
by the nonreturn to zero, change on ones recording method
(NRZ 1). In thi s method, the write head current causes the
state of flux in the tape to be switched from one level of
saturation to the opposite level each time a binary one is
recorded. The absence of such a change represents a binary
zero.
1-14 Power Supplies (Figure 1-1)
There are three power suppl ies: PT19, PT18, and PT16.
Power supply PT19 is located at the bottom rear of the station. It generates the 2000 Hz power that is used as input
for both the PT16 and PT18 supplies. The PT18 supply is
mounted on the bottom left-hand side of the swinging frame
assembly. This supply generates +25 Vdc and -25 Vdc
voltages. The PT16 supply is mounted at the top left-hand
side of the swinging frame assembly. This supply generates
+4 Vdc, +8 Vdc, and -8 Vdc voltages.
1-20 MAGNETIC TAPE STATION
The tape transport moves the tape across a read/write head
in response to commands from the computer or signals generated from the operator control pane I. In a write operation, the data electronics translates the information from
the tape controller and drives the write head to record the
data on the tape. In a read operation, the information
detected by the read head is amplified and then transferred
to the controller.
1-15 Power Distribution Chassis (Figure 1-2)
The power distribution chassis is mounted near the bottom
front left-hand corner of the station. It provides necessary
ac power controls to properly operate the station and
devices connected in the system.
1-16 Transport Drive Electronics (Figure 1-2)
The transport drive electronics contains power suppl ies and
power amplifiers for driving the capstan motor and the reel
motor. It is contained in one assembly mounted near the
bottom rear of the station cabinet, behind the tape vacuum
chamber and below the motors.
1-21 MAGNETIC TAPE CONTROLLER
In automatic operation, all operating commands and read/
write data transfers for the tape station are handled by the
magnetic tape controller. Data to be recorded is received
from the computer through the lOP and is routed to the
magnetic tape controller and then to the selected tape
station. The data flow follows a reverse sequence during a
read operation. Refer to figure 1-3 for an overall functional
block diagram of the magnetic tape system.
1-22 TAPE FORMAT
1 -17 Stati on Electronics (Fi gure 1-2)
The station electronics are mounted in module chassis Sand
U on the swinging frame assembly. Chassis S includes the
modules that contain circuitry to handle the station data
operations. Chassis U includes the modules that contain
circuitry for control of the station motion operations.
1-18 MAGNETIC TAPE CONTROLLER (Figure 1-2)
The controller is compri sed of module chassis V, W, Y, and
Z. Chassis V and W enclose the modules which contain
circuitry for handling the system data operations. The
modules which contain circuitry for control of the system
motion operations are included in chassis Y and Z.
1-19 FUNCTIONAL DESCRIPTION
The magnetic tape system communicates with the computer
through the input/output processor (lOP), which controls
tape system operation. It may store data on the magnetic
tape (write operation) or retrieve it (read operation). The
information is recorded on seven parallel tracks along the
length of the tape at a selectable density of 200, 556, or
800 bytes per inch. Each byte consists of seven bits (six
data bits plus one parity bit), which form a row across the
width of the tape. (See fi gure 1-4.) The bits are formed
1-4
The tape data format conforms to IBM 729, seven-track
format (see figure 1-4). Information on tape is arranged
in records. Each record may contain any number of bytes,
limited only by the length of the usable portion of tape.
Records are separated on tape by an i nterrecord gap of
approximately 0.750 inches. When a write operation is
initiated from the load point, a gap of approximately 0.94
inches in length is automatically inserted between the
beginning of tape (BOT) marker and the first record. At
the end of each record three blank characters are written,
followed by a longitudinal redundancy check character
mark (LRC). A group of one or more consecutive records
forms a fi Ie of information. Adjacent fi les are separated
by a tape mark record, which consists of a single byte. An
LRC character occurs three spaces after the tape mark.
1-23 SPECIFICATIONS AND LEADING PARTICULARS
1-24 GENERAL REQUIREMENTS
Tables 1-1 and 1-2 list the general requirements and
specifications for the magnetic tape system.
SDS 901013
CONTROLLER
- -
-STATION -
I
-
I
I I
READ/
..- DATA ---- I I ..- DATA
I
I
REGISTERS
AMPLIFIER
WRITE
HEADS
I I
DATA
I
-- II -. INTERFACE
I I
I
TAPE
I
...
.. MOTION - I I ..- TRANSPORT - -.
I
SERVO
MECHANISM
CONTROL
I I
I
I
I I
I
I
I I
I
'.
CONTROL
I
I I
I
PANELS
I
I I
I
L _________ --1 L ________ ---1
-
lOP
I
- I
H
901013A.l03
Figure 1-3. Magnetic Tape System Block Diagram
INITIAL
GAP
0.94 IN.
TAPE EDGE
NEAREST TRANSPORT
P'
0
1,
2
3
4'
5.
~-------:1
L!:.0AD POINT
MARKE~
-------
I
.
TAPE MOTION
RECORD
LRC\.
I I I
I I I
I
I
I
I
I
I I
I I
I I
I I
I I
'I'
I
I I I
I I I
I I I
I I I
I I I
I I I
I I I
I
I
RECORD
INTERRECORDS
GAP 0.75 IN.
I
I
I
I
I
I
I
I I
I I
I I
I
I
I
I
I
I
•
1
I
I
I
I
I
I
I
\13 CHARACTER SPACES
901013A.l04
Figure 1-4. Physical Spacing on Tape
1-5
SDS 901013
Paragraph 1-25
Table 1-2. Parameter Definitions and
Specifications (Cont.)
Table 1-1. General Requirements
Characteri sti cs
Specifications
Parameter
Definition
Specification
Power requirements
Primary
108-127 Vac, 30A
45-66 Hz, 1~ *
Secondary
±25 Vdc (± 10%)
±8 Vdc (± 10%)
+4 Vdc (± 10%)
Environmental requirements
Temperature range
o
o
50 F-140 F
Humidity range
5% -80%
Logic levels
True
+4.0 ±0.4 Vdc
False
+0.25 ±0.25 Vdc
Tape characteristics
Recording density
200, 556, or 800 bpi
Width
1/2 in.
Type
1.5 mi I base, Mylar
Reel size
10.5 in. diameter
3.688 in. hub (IBM)
Nominal
tape
speed
The speed at which the tape
moves across the read/write
heads for purposes of reading
and writing
Total
speed
variation
The maximum deviation from
±8%
the nominal tape speed at any
time after start time and previous to a stop command
Fast
tape
speed
The speed at wh i ch the tape
moves for purposes other than
reading and writing
Stop
time
The time interval between the 5.0 ms max
receipt of a stop command and
the cessati on of tape moti on
Stop
distance
The distance traversed by a
point on the tape during the
stop time
Skew
The displacement of a bit from
a line across the tape drawn
perpendicular to the direction
of ideal tape motion at the
head assembly
Static
skew
The nonvaryi ng portion of
skew contributed by the
mechanical tolerances of
the tape, transport, and
head assembly
225 fJin max
The portion of skew contributed by time-variant
tape motion not parallel to
the ideal tape path
225 fJi n (p-p)
* 50 Hz operation requires the 50 Hz modification
kit part No. 137746
Table 1-2. Parameter Definitions and Specifications
Parameter
Definition
Specification
Start
time
The time interval between
the receipt of a start command and the attainment of
a tape speed that is within
8% of nominal speed
5.0 ms max
Dynamic
skew
Start
distance
The di stance traversed by a
point on the tape during the
start time
0.190 ±0.01 in.
1-25 FUSE AND LAMP COMPLEMENT
1-6
75 ips
250 ips ±5%
0.190 ±0.01 in.
The fuses and lamps used in the magnetic tape system are
listed and described in table 2-1. Refer to table 4-28 for
lamp location and identification.
SDS 901013
Paragraphs 2-1 to 2-4
SECTION II
OPERATION AND PROGRAMMING
2-1 CONTROLS AND INDICATORS
2-3 AUXILIARY (MAINTENANCE) CONTROL PANEL
SWITCHES (See figure 1-1)
The following information defines the operation and function of all the controls and indicators in the station.
Manual control of the tape station is provided by switches
located in one of the following:
a.
Operator control panel
b.
Auxi liary control panel-
c.
Interlock system
d.
Power distribution chassis
e.
Power supply PT19 and PT16 chassis
All indicators are contained on the operator control panel.
They display the current status and conditions of the tape
system.
2-2 OPERATOR CONTROL PANEL SWITCHES
(See figure 2-1)
During normal operation, the only controls accessible to
the operator are those on the control panel. This panel is
mounted on the front of the tape station, above the transport
main casting. The names, reference designators, types, and
functions of the control switches are listed in table 2-1.
The auxiliary control panel is inset directly below the
lower ri ght-hand corner of the station transport main
casting. It is accessible from the front of the station when
the swinging front door is open. The panel is equipped
with three switches, labeled FORWARD, REVERSE, and
FAST. The switches are used for motion control of the
station transport when the station is being operated in the
manual mode.
The FORWARD and REVERSE switches are used to control
tape directional motion at a speed of 75 ips. For fast tape
motion, the direction switch selected is used in conjunction with the FAST switch, which causes the fast tape speed
circuitry to be energized, producing a 250 ips tape movement.
2-4 SWINGING FRONT DOOR INTERLOCK SWITCH
The swinging door interlock switch is a part of the auxi I iary
control panel. Since this switch is in the door interlock
system, the door must be closed for the station to become
ready. The switch may be actuated with the door open for
maintenance purposes by pulling outward on the pushrod.
Under normal operating conditions, the switch opens when
the swinging door is swung outward and closes when the
swinging door is shut. Table 2-2 lists the auxiliary panel
switches and their functions.
9OJ013A. 201
Fi gure 2-1. Operator Control Pane I, Front View
2-1
5D5901013
Table 2-1.
Name
Reference
Designator
Operator Control Panel Switches and Indicators
Function
Type
POWER
Switch
51
Dpdt, alternate action
pushbutton switch
Controls the primary power to the drive electronics and to the
motors and blowers in the positive pressure and vacuum systems. It is effective only if the circuit breaker (CB 1) is
closed on the power distribution chassis
Indicator
DS1
Incandescent 28-Vdc
midget lamp
Lights when the circuit breaker on the power distribution
chassis is set to ON and the POWER switch is pressed on the
operator control panel
Switch
52
Dpdt, momentary contact
pushbutton switch
Causes the transport to load tape automatically into the vacuum chambers. Actuation of thi s switch feeds tape from the
file reel into both the file and fixed vacuum chambers. The
tape is then driven to the load point (BOT marker), at which
time the tape motion ceases and the unit becomes ready. The
switch is pressed after loading a new tape onto the file reel.
When the BOT marker is detected, the LOAD indicator lights
on the operator control panel
Indicator
DS2
Incandescent 28-Vdc
midget lamp
Lights whenever the tape reaches the load poi nt position. Thi s
position is reached with tape motion stopped and the beginning
of tape reflective marker (BOT) positioned directly under the
photosense head
Switch
53
Dpdt, momentary contact
pushbutton switch
Initiates an off-line rewind operation, provided the station is
not in the automatic mode. When this switch is activated,
fast reverse tape motion takes place and the tape rewinds unti I
the BOT marker is detected, at which point tape motion ceases,
and the LOAD indicator lights on the operator control panel.
When this switch is pressed, with the tape in the load point
position, an unload operation is initiated. The unload operation is performed to unwi nd the porti on of tape ahead of the
BOT marker from the fixed reel
Indicator
DS3
Incandescent 28-Vdc
midget lamp
Lights throughout the duration of a rewind operation. It goes
out when the beginning of the tape marker is detected by the
photosense head. It also lights when fast tape motion is initiated from the auxi liary (maintenance) panel
Switch
54
Dpdt, momentary contact
pushbutton switch
Pressing this switch when the station is not in automatic sets a
latch that provides a device interrupt to the processor when
the station is switched into automatic. Pressing this switch
when the station is in automatic has no effect
Indi cator
DS4
Incandescent 28-Vdc
midget lamp
Lights when the ATTENTION switch is pressed while the station is not in the automatic mode. It remains on until the
interrupt call si gna I comes true from the controller
LOAD
REWIND
ATTENTION
(Continued)
2-2
SDS 901013
Table 2-1. Operator Control Panel Switches and Indicators (Cont.)
I:>
Name
Reference
Designator
Type
Function
FILE PROTECT
Indicator
DS5
Incandescent 2S-Vdc
midget lamp
Lights when the write enable ring is not installed in the file
reel. This constitutes a file protect condition. No writing
can take place under these circumstances
Switch
S6
Dpdt, momentary contact
pushbutton switch
Places the station in the automatic mode, provided the station
is ready (all interlocks closed)
Indicator
DS6
Incandescent 2S-Vdc
midget lamp
Lights when the station is in automatic. In this mode, the station may respond to tape motion commands from the controller
Switch
57
Dpdt, momentary contact
pushbutton switch
Tests all panel indicator bulbs with the exception of the
POWER light. Pressing this switch should cause all the indicators except POWER and RESET to light
Indicator
DS7
Incandescent 2S-Vdc
midget lamp
Lights when the station is operational, but not busy. The station is operational if all the voltages are present, the interlocks are closed, and no reset, load, or tape backup operation
is taking place. The station is busy if it has been selected
for any operati on
DSS
Incandescent 2S-Vdc
midget lamp
Lights when the station is operational and busy. The station
is operational if all the voltages are present, the interlocks
are closed, and no reset, load, or tape backup operation is in
progress. The station is busy only if it is performing an operation in response to a command from the controller
59
Dpdt, momentary contact
pushbutton switch
Resets the station to the manual mode. In this condition
tape motion is stopped and the station no longer responds to
tape motion commands from the processor
511
Rotary, 9-position, 3-deck
The positioning of this switch determines the station number
(0-7). There may be S stations connected to a controller. It
is the station number that determi nes which station responds
to a given command from the processor. The command includes a station address number, which is compared with the
number specified by the UNIT SELECTswitch. No two stations
connected to a controller can have the same switch setting.
The UNIT SELECT switch also has an OFF position. With the
switch set to OFF, the particular station does not respond to
the station address line from the controller. Status checks
may be made on a station in manual or automatic mode by
addressing the station. Because of this, the only way a station
may be taken off-line is to set the UNIT SELECT switch to
OFF
START
READY
BUSY
Indicator
RESET
Switch
UNIT SELECT
Switch
(Continued)
2-3
SDS 901013
Paragraphs 2-5 to 2-7
Table 2-1. Operator Control Panel Switches and Indicators (Cont.)
Reference
Designator
Name
Function
Type
SEGMENTED
Indicator
DS10
Incandescent 2S-Vdc
midget lamps (7 bulbs)
Shows the number (0-7) selected for a particular unit or
indicates the off-line position
S12
Rotary, 3-position
This switch permits the selection of one of three operating
densities: 200, 556, or SOO bpi
DENSITY
SELECT
Switch
Table 2-2. Auxiliary Control Panel Switches
Function
Type
Name
FORWARD
Spdt momentary contact pushbutton switch
Moves tape forward at 75 ips
REVERSE
Spdt momentary contact pushbutton switch
Moves tape in reverse at 75 ips
FAST
Spdt momentary contact pushbutton switch
Used in combination with FORWARD or
REVERSE switch to move tape at 250 ips
Swi ngi ng front door i nte rlock
2-5 POWER DISTRIBUTION CHASSIS SWITCHES
(See fi gure 1 -2)
The power distribution chassis is mounted near the bottom
front left-hand corner of the tape station. See paragraph
3-9 for detailed theory of operation.
There are two manual controls mounted on the power distribution chassis. These controls are a circuit breaker
switch (CB1) and a toggle switch (51) with LOCAL, REMOTE, and OFF positions. The two switches are accessible
from the rear of the station. Table 2-3 describes these
switches and their functions.
In normal operation, the switch opens when
the swi ngi ng door is swung outward. This
opens the i nterl ock network and prevents
the station from being ready
the swinging frame assembly; the PT18 power supply is
mounted on the bottom left-hand side of the swinging frame
assembly (figure 1-2). There is an ON-OFF circuit breaker
on both the PTl9 and PTl6 power supplies. The H-L-L
switches on the PTl8 and PTl6 supplies are used by maintenance personnel only. The fuses on the supplies are listed
in the power supply manual listed in the front matter. The
fuse in the PTl9 supply is accessible only after removing
the top cover of the supply. Refer to the list of related
publications for manuals that give a detailed description of
these supplies.
2-7 MANUALLY OPERATED INTERLOCK SWITCHES
(See figure 1-1)
2-6 POWER SUPPLY SWITCHES AND FUSES
Three power supplies are used in the tape station: the PTl9,
PTl6, and PTlS power supplies. The PT19 power supply is
located at the bottom rear of the stati on (fi gure 1 -1); the
PTl6 power supply is mounted on the top left-hand side of
2-4
The tape station interlock system consists of manually
operated switches: the top door switch, the swinging door
switch, and the bottom door switch. Table 2-4 lists the
switches, how they are actuated, and their functions; fi gure 2-2 shows the functions of the switches.
SDS 901013
Table 2-3. Power Distribution Chassis Switches
Name
Reference
Designator
ON-OFF
LOCALOFFREMOTE
Type
Function
CB1
Circuit breaker,
15A, 1 pole
When placed in the ON position connects 115 Vac power to the positive pressure
system pump, the vacuum system blowers, and the servo power suppl ies in the
transport drive electronics, if ac power is connected to the power distribution
chassis at P1, and the LOCAL-OFF -REMOTE switch is not in the OFF position
S1
Toggle, dpdt,
9V
Determines whether the 115 Vac power to the power distribution chassis is controlled by the processor control panel or is applied locally when 115 Vac is
connected at Pl. Can also be set to OFF to remove all ac power into the power
distribution chassis. When set to LOCAL, the power is connected to the station
as soon as 115 Vac is connected to Pl on the power distribution chassis. When set
to REMOTE, ac power is connected to the station only after the POWER switch is
set on the central processor control panel, if 115 Vac is connected to Pl on the
power distribution chassis
Table 2-4. Manually Operated Interlock Switches
Switch
How Actuated
Function
Top door
switch
This switch is closed only when the sliding glass door is
completely shut
Prevents the station from being ready if the sliding glass door is open
Swinging
door
switch
This switch is closed when the swinging door is completely shut. For maintenance purposes it may be closed
by pulling outwards on the switch pushrod
Prevents the station from becoming ready when
open
Bottom door
Switch
This switch closes when the sliding glass door is lowered
to the fully open position
When this switch is closed, it connects brake
power to the reel motors to release the brakes and
shut off the vacuum and positive pressure systems
r-----l
L
i-------; 51 :
~
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r------,
j----l r-----,
r--------,
:
I
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:
I
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I
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I
I
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:
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I
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OPEN I
I
I I
I
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AC
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INTERLOCK
I
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I
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./
I
I./"I
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1 RELAY
I
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~~ j
1
I DOOR AT TOP I
SWINGING
I
I
I
:
:
I
I
SWITCH
I
DOOR:
:*INTERLOCK:
: ;INTERLOCK I
I POSITIVE PRESSURE SW I
115V
KID
: (FUNCTION I
SWITCH
I I
B
I
I
A
I
I
(FUNCTION OF
I
I
SLIDING
I
(OPEN IF
I
FILE
~F1XEDI
I
POS. PRESSURE
I
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DOOR IS
I
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CHAMBER
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I
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L i.0 2! Tl0.!:!)---.J L _ Q.P~Nl_ J
1
1
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I'"'O-J I
c--<>
i i
JJ
L _______ J
Kl
'25V--~~
K2
READY
RELAY
DC
INTERLOCK
RELAY
NOTES:
1. THE BOTTOM DOOR SWITCH IS NOT SHOWN
2. RELAYS SHOWN IN DE-ENERGIZED POS:TlO~~
iNPUT FALSE EXCEPT
FOR POWER FAILURE
901013A. 203
Fi gure 2-2. Interlock Network
2-5
Paragraphs 2-8 to 2-13
SDS 901013
-..-----10
o
1
BEGINNING
OF
TAPE
L
3/16 IN.
(+1 ) FT
-0
----I~
'---r--~~--
1 - - 1 IN.---1
I
T
1/32 IN. BETWEEN
TAB AND EDGE
OF TAPE
I
ACTUAL TAB
DIMENSIONS
CHANNEL A
BOT TAB
EDGE
NEAREST
TRANSPORT
Q
END
T~~E
MYLAR
SIDE
OF
TAPE
900837A. 5
Figure 2-3. Location of Reflective Tape Markers
2-13 Push-On, Pull-Off (POPO) Hub Assembly (Figure 2-5)
2-8 OPERATING INSTRUCTIONS
2-9 INITIAL TURN-ON PROCEDURE
To completely energize the magnetic tape system, execute
the followi ng steps:
a. Place the circuit breakers on the PTl6 and PTl9
power supplies to the ON position.
b.
Place circuit breaker CBl (ON-OFF) and switch
51 (LOCAL-OFF-REMOTE), in the power distribution
chassis, to the ON and REMOTE positions, respectively.
c.
panel.
The station is equipped with a POPO hub assembly, which is
attached to the shaft of the file reel motor, and upon which
is mounted the fi Ie reel. The POPO hub simpl ifies the procedure for mounting or removing the file reel from the station transport. To install a file reel, hold the reel with both
hands, slip the reel over the hub assembly, and then push
the reel inward on the hub as far as possible. To prevent
tape damage while installing the reel, apply the pressure
only on the reel flange nearest the tape transport. To remove the reel, pu II it outward with both hands on the outer
flange.
Press the POWER switch on the operator control
2-10 TAPE PRE PARA nON
2-11 Reflective Markers (Figure 2-3)
Reflective markers are placed on the tape to enable sensing
the beginning and end of the usable portion of the tape.
The reflective markers are plastic strips coated on one side
with adhesive and on the other with vaporized aluminum.
They are placed on the base or uncoated side of the tape for
detection by the photosensing circuits.
2-12 File Protect Ring
A circular slot around the hub opening on the back of each
tape reel is designed to accept a plastic file protect ring
(figure 2-4). A write operation is permissible only when a
file protect ring is present on the supply reel. The FILE
PROTECT indicator on the operator control panel is lit when
a file protect ring is not present on the supply reel.
,.
2-6
Figure 2-4. File Reel and File Protect Ring
SDS 901013
Paragraphs 2-14 to 2-16
SUDING SHOE
HUB ASSEMBL V-COVER REMOVED
HUB ASSEMBL V
90 1084A. 202
Figure 2-5. POPO Hub Assembly
2-14 LOADING THE TRANSPORT
The procedure for loading the tape from the file reel to the
fixed reel after the file reel has been mounted is as follows:
a. Close the swinging front door and lower the sl iding
glass door to the fully open position.
b. After determining that the write enable ring is in
place if file protect is not required, push the supply reel
onto the fi Ie reel hub.
c.
Unwind five to six feet of tape leader from the fi Ie
3. The tape loops settle to their standby positions
in the vacuum chambers. This completes the transport
loading operation.
Note
If forward motion does not stop when the load
point is reached, press the RESET switch to
stop the transport and check the position of
the BOT marker (see fi gure 2-3).
2-15 ON-LINE OPERATION
reel:
d. Thread the tape along the path shown in figure 2-6.
Wind two to four turns of tape onto the fixed reel. Because
the transport provides an automatic tape loading feature, it
is not necessary to feed tape manually into the vacuum
chambers.
e. Raise the sliding glass door to the fully closed
position, then press the LOAD switch on the operator control panel. This initiates the following load sequence:
1. The capstan and the reels move forward,
serving tape into the vacuum chamber.
After loadi ng the transport and closing all interlock switches
(see table 2-4 and figure 2-2), the system becomes fully
operational. To put the station on-line, set the UNIT
SELECT switch to the proper station number, as displayed
by the segmented indicator (DS10), then press the START
switch. If an interrupt is desired, to let the CPU know
that the station is avai lable, the ATTENTION switch should
be pressed before the START switch is activated. These
switches are all located on the operator control panel (see
fi gure 2-1).
2-16 TURNOFF PROCE DURE
If the removal of all power from the magnetic tape system
2. The moving tape arrives at load point, forward
motion ceases, and the LOAD indicator on the control panel
lights.
is desired, the opposite directions of the turn-on procedure
should be executed and the steps followed in reverse
sequence.
2-7
SDS 901013
Paragraphs 2-17 to 2-19
FIXED REEL
AIR-CUSHIONED
TAPE GUIDES
(5 PLACES)
FILE REEL
REA D/WRIT E
CAPSTAN ~EAD
..
TAPE
~7°
PHOTOSENSE
HEAD
FIXED REEL TACH
FILE REEL TACH
ERASE HEAD
o
o
o
o
FILE
FIXED
L . - -_ _
VACUUM CHAMBERS---J
90 1084A. 201
Figure 2-6. Tape Path
2-17 PROGRAMMING
This portion of the manual describes the magnetic tape
system orders, error i ndi cati ons, and i nput/output (I/O)
instructions and responses. Specific procedures for programming on-line test routines are available in the magnetic
tape test diagnostic program manuals, SDS publications
901536 and 901165. Further information is found in the
diagnostic control program reference manual, SDS 900712.
For off-line operation and trouble analysis, the peripheral
equi pment tester (PE T) is recommended. Instructi ons for
PET operation are provided in SDS publication 901004.
2-18 MAGNETIC TAPE SYSTEM I/o INSTRUCTIONS
AND RESPONSES
The CPU communicates with the magnetic tape system
through the following five instructions:
Instruction Name
Mnemonic
2-19 Start Input/Output (SIO)
The CPU executes an SIO to initiate an input/output operation with the device specified by the I/O address. The
addressed controller sets up the condition codes (CC 1 and
CC2) in the lOP for the CPU to examine, as follows:
Start input/output
SIO
CC 1
CC2
Halt input/output
HIO
o
0
Test input/output
TIO
Test device
TDV
Acknowledge I/O
AIO
An ei ght-bit I/O address must be provided by the I/O
processor (lOP) to select a device for the SIO, HIO, TIO,
and TDV instructions. For the AIO instruction, the device
selected by the priority chain to process its interrupt presents
2-8
its eight-bit address to the lOP. The assignment of an address for the magnetic tape controller is performed by setting
up switches on the LT26 module in the subcontroller portion
of the controller (chassis V). The magnetic tape controller
and the station respond to each I/O instruction with a set
of condition codes and with status information for the CPU
to examine. This information is contained in bit positions
zero through seven of the status response byte (see tables
2-5, 2-6, and 2-7). The symbols CCl and CC2 refer to
condition code bits when the interface is with Sigma 5 and
7 computers. The symbols 0 (overflow) and C (carry)
correspond to CC 1 and CC2, respectively, when the interface refers to Sigma 2 computers.
o
Interpretati on
I/O address recognized and SIO accepted
(tape station has advanced to busy condition)
I/O address recognized but SIO not accepted
(tape station already busy or device interrupt
pending)
o
Tape system attached to a busy selector lOP
(not applicable to Sigma 2)
I/O address not recognized
SDS 901013
I/O address recognition indicates that the addressed station
is on-line. The magnetic tape controller accepts the SIO
and indicates a successful SIO only if the controller is not
busy with a previous operation, if the station addressed is
operational and ready, and if neither the controller nor the
addressed station has an interrupt pending.
Paragraphs 2-20 to 2-21
Table 2-5. Status Responses, SIO, HIO, and
TIO Instructions
Bit
Posi ti on
Bit
State
o
1
1, 2
0, 0
Device ready. The selected station
is operational and is not connected to
the magnetic tape controller for an
operation
0, 1
Device not operational. The addressed
station has developed some condition
that does not allow it to proceed
1, 0
Not used
1, 1
Device busy. The addressed station is
operational and either is connected to
the magnetic tape controller for an
operation, or is rewinding
2-20 Halt Input/Output (HIO)
Upon execution of an HIO, the addressed station immedihalts all current operations. The magnetic tape controller itself, if busy, returns to the ready state. If the HIO
is addressed to the active station that has a transmission
interrupt pending in the controller, this interrupt is reset.
An HIO instruction is used only in special cases, and the
tape position of a busy station so halted is undefinable.
The condition codes for an HIO are as follows:
atey
CC 1
CC2
o
0
o
Interpretati on
I/O address recognized and tape station
not busy when halt occurred
I/O address recognized and tape station
busy when halt occurred
I/O address not recognized
3
o
Manual mode. A successful SIO is possible. The station will delay any order
requiring tape movement unti I the operator sets it in the automatic mode
4
1
Unusual end. The magnetic tape controller has encountered an unusual
condition after having accepted the
last order
5, 6
0, 0
Device controller ready. The addressed
magnetic tape controller, if on-line, is
in standby but may have an interrupt
pending
0, 1
Not used
1, 0
Not used
1, 1
Device controller busy. The addressed
magnetic tape controller is on-line and
is engaged in performing an operation
The CPU uses a TIO instruction to gai n access to the status
information of the selected lOP, magnetic tape controller,
and station, without affecting their operations. The condition codes for a TIO are as follows:
CC2
o
0
o
Interpretation
I/O address recognized and SIO can be
accepted (station ready with no interrupt
pending)
I/O address recognized but SIO cannot
be accepted
o
Interrupt pending. Either the addressed
station has requested an interrupt or
the magnetic tape controller has set an
interrupt after having received a request from the lOP that was associated
with previous data transmission to the
addressed station. An SIO is not possible whi Ie a controller interrupt is
pending, but command chaining may
occur
Automatic mode. A successful SIO is
possible. The station is under program
control
2-21 Test Input/Output (TIO)
CC 1
Description
Tape system attached to a busy selector
lOP (not applicable to Sigma 2)
I/o address not recogni zed
7
Not used
Status response information for the SIO, HIO, and TIO
instructions is given in table 2-5.
2-9
Paragraphs 2-22 to 2-24
SDS 901013
2-22 Test Device (TDV)
2-23 Acknowledge Input/Output Interrupt (AIO)
The CPU uses a TDV instruction to obtain a more detai led
status report from the magnetic tape system. The execution
of a TDV does not alter the operation of the addressed lOP,
magnetic tape controller, or station. The condition codes
for the TDV instruction are as follows:
The CPU executes an AlO to acknowledge an I/O interrupt
and to identify the source of the interrupt condition. The
condition codes for AlO are as follows:
Interpretati on
CC1
CC2
o
o
I/O address recognized
o
Tape station is attached to a busy selector
lOP (not applicable to Sigma 2)
I/O address not recognized
CCl
CC2
o
o
Bit
Position
o
1
2
3
Bit
State
1
Description
Write permitted. Writing may be
performed
o
Write protected. The addressed station
is write protected; only reading may be
performed
1
Write protect violation error. The addressed station receives a write order
while write protected
1
End of fi Ie. Ei ther the BOT marker has
been detected or the last record read or
spaced was a tape mark record
4
Not applicable
5
Load point. The addressed station is
positioned at the BOT marker
6
End of tape. The addressed station has
passed the EOT marker
7
Rewind on-line. The addressed station is
rewinding in the automatic mode
2-10
Unusual interrupt condition present
No interrupt condi ti on present
Status response information for the AIO instruction is given
in table 2-7.
Table 2-7. Status Responses, AIO Instruction
Bit
Posi ti on
Bit
State
o
Rate error. The addressed magnetic tape
controller has detected a data transfer
rate error during the last read or write
operation. This condition is caused by
equipment malfunction or by the I/o
data rate exceedi ng the system limits.
When a rate error occurs during writing,
dummy characters are written unti I further bytes are avai lable, at which time
normal writing resumes
1
Normal interrupt condition present.
Channel end or zero byte count
o
Status response information for the TDV instruction is given
in table 2-6.
Table 2-6. Status Responses, TDV Instruction
Interpretation
Descri pti on
Rate error. The magnetic tape controller has detected a data transfer rate
error during the~last read or write operation. This condition exists when the
total I/O data transfer rate exceeds
the system limits. If a rate error occurs
during writing, dummy characters are
written unti I further bytes are available, at which time normal writing
resumes
o
Controller interrupt. In response to an
lOP request, an interrupt is generated
through a terminal order
Device end interrupt. An interrupt is
generated when either a station has
just completed a rewind and interrupt
order or it has been manually placed
in the automati c mode
2
Write protect violation error. The
addressed station receives a write
orde r wh iI e write protec ted
3
End of file. Either the BOT marker has
been detec ted or the last record read
or spaced was a tape mark record
2-24 MAGNETIC TAPE SYSTEM CONDITIONS
Some of the status levels and conditions referred to in tables
2-5, 2-6, and 2-7 comprise a priority chain that must be
satisfied before the system can operate in conjunction with
SDS 901013
Paragraphs 2-25 to 2-32
Table 2-8. Input/Output Order Bytes
the lOP. Paragraphs 2-25 through 2-29 briefly explain
these conditions and modes of operation.
2-25 Input/Output Address Recognition
This condition exists unless the system does not have its
power on or unless the UNIT SELECT switch on the operator
panel is in the OFF position.
2-26 Station Operational
The station is operational if all vacuum and interlock requirements are satisfied. A not-operational condition exists
when the vacuum or positive pressure falls too low, the tape
goes off its path, or either the door or window is not closed.
2 -27 Stati on Ready
The station is considered ready when it can accept and
execute an SIO instruction. The station must be operational and not busy. It may be in either the manual or the
automatic mode and sti II be considered ready.
2-28 Controller Ready
BIT POSITIONS HEXADECIMAL
3 4 5 6 7 EQUIVALENT
o 0 o0 o 0 1 0
o 0 000 1 1 0
o 0 001 1 1 0
o 0 o0 o 0 o 1
o 0 o 0 010 1
o 0 o0 1 1 o 1
o 1 1 1 o0 1 1
o0 o0 1 1 o0
o0 o0 o 1 o0
0 o 0 000 1 1
o 0 o 1 001 1
0 o 1 000 1 1
0 o 1 100 1 1
02
Read pac ked mode
06
Read binary mode
OE
Read BC D mode
01
Write packed mode
05
Write binary mode
OD
Write BCD mode
73
Write tape mark
0 1 0 000 1 1
rot
used. Applicable to nine-track
tape systems only
13
Rewind and interrupt
23
Rewind off-I ine
33
Rewind on-line
43
Space record forward
1
4B
Space record reverse
1
53
Space fi I e forward
0 1 0 1 1 0 1 1
5B
Space fi Ie reverse
63
Set erase
0 1 0
The controller has only two states, ready and busy. It is
busy if it has accepted an SIO but has not processed the
instruction because of a prevailing condition in the addressed station. The controller becomes ready when the
addressed station starts and conditions allow another SIO
to be accepted.
ORDER
o12
0 1 0
0 1 1
o1 o1
1 o0 1
o0 o1
1
2-32 Order Descriptions
2-29 Station Automatic
The station is in the automatic mode when the START
switch is pressed, after all previous conditions have been
met. The station changes to the manual mode when either
the RESET switch is pressed, a not-operational condition
arises, or a rewind off-I i ne order occurs.
2-30 MAGNETIC TAPE SYSTEM ORDERS
An input/output operation is begun when the magnetic tape
system accepts an SIO instruction. The controller then
proceeds to request an order from the lOP. The orders,
coded in the byte presented by the lOP, are interpreted
by the controller as definite functions to be performed.
2-31 Order Codes
There are 15 orders that specify the magnetic tape system
operations. The order bytes and their respective names
are listed in table 2-8. Orders other than those listed
result in either an unusual end or an undefined operation.
The operations associated with the order codes used with the
magnetic tape system are described below. A more detai led
functional description is presented in section III of this
manual.
WRITE. When a write order is received, the tape station
starts forward tape motion. After a 7 ms delay, information
is recorded on the tape in one of three program-selected
modes: bi nary, packed bi nary, or BC D (see paragraph 3-3).
When the desired number of characters has been recorded,
data transfer terminates, the LRC character is recorded, and
tape motion stops. If another write order arrives before the
tape comes to a complete stop, motion resumes immediately
but writing begins only after the 7 ms delay has elapsed.
If the order is a wri te tape mark, the same process outl i ned
above takes place. The only difference is that the record
written consists of a single character (the BCD character v),
generated locally, with a preceding 3.5 in. erased gap,
instead of norma II y tra nsferred data.
READ. When a read order is received, the tape station starts
forward tape motion. As soon as the portion of tape containing information reaches the read head, the detected
2-11
Paragraphs 2-33
SOS 901013
characters are transmitted sequentially to the lOP. The
tape is read in binary, packed binary, or BCD. The controller checks vertical parity as each character passes the
read head. Reading continues !Jntil the interrecord gap is
detected. If no further order is pending, tape motion stops
with the write head located in the middle of the interrecord
gap. If another read order arrives before the tape comes to
a complete stop, motion and reading resume without delay.
When an LRC character is read, longitudinal parity is
checked in the controller. If an error is detected, a transmission data error indicator is set. If no error is detected,
a channel end indication occurs.
The same reading operation applies to tape mark records,
except that an unusual end indication is generated as soon
as the LRC character has been read.
SPACE. The effect of a space order is to move the tape,
with respect to the heads, in a forward or reverse direction.
The length of tape that passes the heads depends on the
length of the record or fi Ie that is to be spaced. Four
orders determine the type of spacing to be performed: space
record forward, space record reverse, space fi Ie forward,
and space file reverse.
When a space record order is received, the tape is spaced
over one record in the forward or reverse di rection, as
specified by the order. If no further order is received, the
tape stops with the write head located in the center of the
gap following or preceding the record spaced. A channe I
end indication is then generated.
When a space fi Ie order is received, the tape is spaced over
one file in the forward or reverse direction, as specified by
the order. The tape stops when a tape mark is detected,
with the write head located in the center of the gap following the tape mark. A channel end indication is then generated. If no tape mark is detected wh i Ie the tape is being
spaced in the reverse direction, the tape stops at the load
point.
REWIND. The effect of a rewind order is to move the tape
in the reverse direction and to stop it when the BOT marker
is detected. Several tape stations in the system may perform a rewind operation simultaneously. There are three
kinds of rewind orders: rewind on-line, rewind and interrupt, and rewind off-line.
When a rewind on-line order is received, if the selected
station is not busy, channel end is indicated. The station
2-12
then proceeds to rewind and enters into a busy condition,
unti I tape motion stops.
A rewind and interrupt order produces the same events as a
rewind on-line order, except that an I/O device interrupt is
requested after the operation is completed.
A rewind off-line order is similar to a rewind on-line order,
except that it switches the station to the manual mode.
Operator intervention is then requi red to place the station
back on-line.
ERASE. The only function of this order is to set an indicator
that enables the station to erase 3-1/2 inches of tape preceding a record upon receipt of a write order. If the next
order received is not a write order, this indicator is immediately reset.
2-33 Termination of Order and Error Indications
After executing an order, the magnetic tape controller signals
the lOP by sending a channel end indication, an unusual
end indication, or both, and the error indications accumulated during the order execution. Error indi cators are cumulative if there is command chaining.
CHANNEL END. A channel end indication is reported
after each order executi on, except when any of the fo lIowing conditions is present:
a. An order out service cycle terminates with an lOP
error halt indication.
b. A space record reverse or space fi Ie reverse order is
received by a station in which the tape is at the load point.
c. A write o_rder is received by a station that is write
protected.
UNUSUAL END. An unusual end indication is reported
when any of the conditions noted in the previous paragraph
is present, and also when the following conditions exist:
a. The lOP signals an lOP error halt, except when a
terminal order follows the order in.
b.
record.
An attempt is made to read over a tape mark
c.
record.
A space record order is executed over a tape mark
SDS 901013
Paragraphs 3-1 to 3-6
SECTION III
PRINCIPLES OF OPERATION
3-1 INTRODUCTION
This section presents the principles of operation for the
magnetic tape system. The overall functional concepts are
described in respect to the basic components of the system:
the station and the controller. The primary functions of the
system are then explained in detail, by tracing the signals
and associated circuitry that determine the system operations. A glossary of terms is provided at the end of the
section.
Some of the special characters in EBCDIC format are
changed to fit the BCDIC character set.
3-6 Packed Binary Mode
3-2 GENERAL INFORMATION
During a write operation in the packed binary mode, each
group of three 8-bit bytes from memory results in the recording of four 6-bit characters on tape (see figure 3-3).
Whi Ie being transferred, each bit is preserved in its relative
location. The last tape character recorded consists of zeros
if the CPU does not send a number of bytes which is a multiple of three. Parity in the packed mode is always odd.
3-3 DATA TRANSFER MODES
The write packed end conditions are these:
The standard magnetic tape system (model 7371/7372) writes
and reads data in either of two program-selected modes:
binary or binary coded decimal (BCD). When the binary
packing option (model 7374) is added, a packed binary
mode is also avai lable to the program. The mode of operation selected is determined by the order codes.
a. If the record contains 3N bytes, 4N characters are
recorded on tape.
3 -4 Binary Mode
When a write operation is executed in the binary mode,
data is transferred from the lOP to the controller in the
same order as it is arranged in memory (see figure 3-1).
The two most si gnificant bits of each byte (bit positions 0
and 1) are discarded at the controller. During a read
operation, the 6-bit byte read from the tape is reconstructed
as it originally appeared in memory, with the two most
significant bits substituted by zeros, before it is transferred
to the lOP. Parity is always odd in binary mode.
3-5 Binary Coded Decimal Mode
When a write operation is executed in the BC D mode, data
is recorded in standard 6-bit binary coded decimal interchange code (BCDIC). The 8-bit byte from the CPU, as
presented by the lOP to the controller, is interpreted as
being in the standard 62 character set of the 8-bit extended
binary coded decimal interchange code (EBCDIC). The
EBCDIC information is translated in the controller to an
equivalent 6-bit character in the BCDIC format and then
recorded on tape (see fi gure 3-2). Duri ng a read operati on,
the 6-bit character read from the tape is translated from
BCDIC to the 8-bit EBCDIC format before it is transferred
to the lOP. Parity on tape is always even in the BCD mode.
Table 3-1 shows the conversion of BCDIC to EBCDIC. Control codes are read and recorded as undefi ned characters.
b. If the record contains 3N+1 bytes, 4N+2 characters are recorded, the last character containing zeros in the
four least significant bit positions.
c. If the record contains 3N +2 bytes, 4N +3 characters are recorded, the last character containing zeros in the
two least significant bit positions.
Duri ng a read operati on, 6-bit bi nary characters read from
tape are packed sequentially in descending order (left to
right). Four tape characters are packed into exactly three
bytes and transmitted to the lOP, each bit kept in its relative location. If a multiple of four tape characters is not
read, the additional characters after 4N are left adjusted
within the proper three byte group in memory. The last
byte transmitted is completed with an even number of zeros.
The last memory byte transmitted contains eight zeros if 4N
characters are not read from tape.
The read packed end conditions are these:
a. If 4N characters are read from tape, 3N bytes are
sent to the lOP.
b. If 4N + 1 characters are read from tape, 3N + 1 bytes
are sent to the lOP, the last byte containing zeros in the
two least significant bit positions.
c. If 4N +2 characters are read from tape, 3N +2 bytes
are sent to the lOP, the last byte containing zeros in the
four least significant bit positions.
d. If 4N +3 characters are read from tape, 3N +3
bytes are sent to the lOP, the last byte containing zeros in
the four least si gnificant bit positions.
3-1
SDS 901013
BYTE 1
BIT POSITIO N
MEMORY/I/O SYSTEM
BYTE 2
0 1 2
3 ': 4 5 6
7 0
1 2
1 1
0 0 0 1
1
0
0 0 1
1
1
1 0
CONTROLLER
1
5 6
7
0 1
0
0
1 1
1 0
1
1 1
1
1 0
0
2 3
1
0
n
)
4
1 I
0 1 1
I
I
I
3 4
BYTE
5
6
0
0 1
7
0 0 1
I
J
I
~
, I
WRITE TAPE BINARY
PARITY
~TAPE
(ODD)~,)
,;,....,-" ...
,
MOTION
(
(LEAST SIGNIFICANT BIT)
•
•
, EDGE NEAREST TRANSPORT FRAM E
0
1
0
0
-'
0
1
1.
1
0
2
0
1
1
1 .•••.• 1
3
4
0
1
0
1
0
0
5
1
0
1
,
,
I
t
"
READ TAPE BINARY
.r
CONTROLLER
I/O SYSTEM/MEMORY
BIT POSITION
1 0
0 0
2
3
!
!
1 1 ;1
1
1
1
0
0
4 5 6
7
0
1 2
0 0 1 0 0
0 1
1
1
I
I
I
BYTE 1
0
1
0 1
1. 1 0
'.
3! 4
5
I
I
0
0
1: 1 0 0
1
;
1 0
0 0
0 1 ,: 1
0 0
1
6
0 1
2 3 4
5
7
7
BYTE 2
6
BYTE N
901013A. 301
Figure 3-1. Data Representation on Tape, Binary Mode
3-2
SDS 901013
BYTE 2
BYTE 1
BIT POSITION
MEMORY/I/O SYSTEM
0
1 2
5 6 7
3 4
0
1 1
1 1 0 1 ,0 1 0 1
1 0 0 1
CONTROLLER
I
CHARACTER
1 2
0 1
I
liN II
BYTE n
3
4
5
6
7
0
0
0 1
1
0
1
1 0 1
1
0
.....
l
IIFII
I
!
,
,
0 1
2 3
4
5
6 7
0 1
0
1
1 0
1 1
1 0
1 0
1 1
l
I
11$11
WRITE TAPE DECIMAL
,
,
, EDGE NEAREST TRANSPORT FRAME
1
0
0
0
1
1
(
1
0
1
1
0
)
2
0
PARITY (EVEN):- r'
~TAPE
3
1
4
0
0 ••. ···1
1
0
1
1
(LEAST SIGNIFICANT BIT) 5
1
0
1
,
,.
MOTION
,~
READ TAPE DECIMAL
,
I
CHARACTER
I
I
N
CONTROLLER
1
0
0 1 0 1
I/O SYSTEM/MEMORY
1 1 0
1
0 1
0 1
1 1
0
0 1
3
4 5
6 7
0
BIT POSITION
2
BYTE 1
0
1
1 0
0 0
1
1 0
2 3 4
5
6
1 1
1
I
F
I
.......
7
BYTE 2
I
$
1
0
1
0
1 1
1 1
0
1
0
1 1
0
0
1
2
3 4
5 6
7
BYTE N
901013A. 302
Figure 3-2.
Data Representation on Tape, Decimal Mode
3-3
SDS 901013
Paragraphs 3-7 to 3-8
Table 3-1. BCDIC to EBCDIC Conversion
EBCDIC
Character
EBCDIC
Code
Hexadecimal
BCD
Code
Octal
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
E2
E3
E4
E5
E6
E7
E8
E9
61
62
63
A
B
C
D
E
F
G
H
I
J
K
L
M
N
0
P
Q
R
S
T
U
V
W
X
y
Z
BCD
Character
EBCDIC
Character
EBCDIC
Code
Hexadecimal
BCD
Code
Octal
BCD
Character
A
B
C
D
E
F
G
H
I
J
K
6
7
8
9
F6
F7
F8
F9
06
07
10
11
6
7
8
9
Blank
40
4A
4B
4C
4D
4E
4F
50
5A
5B
5C
5D
5E
5F
60
61
6A
6B
6C
6D
6E
6F
7A
7B
7C
7D
7E
7F
20
72
73
74
75
76
77
60
52
53
54
55
56
57
40
21
32
33
34
35
36
37
12
13
14
15
16
17
Blank
? or backspace
64
65
66
67
70
71
41
42
43
44
45
46
47
50
51
22
23
24
25
26
27
30
31
L
M
N
0
P
Q
R
S
T
U
V
W
X
y
Z
I-
.
<
(
+
I
&
!
$
*
)
;
--,
/
None assi gned
,
%
-
>
?
0
1
2
3
4
5
FO
F1
F2
F3
F4
F5
12
01
02
03
04
05
0*
1
2
3
4
5
:
#
@
,
=
II
) or n
[
<
*
+ or &
! or carriage return
$
*
]
;
D.
- (dash or minus)
/
:f or tab
,
(or %
IV'
\
4#
0*
# or
=
@ or'
:
>
-It
*During writing, both X 'FO' and '7A' are recorded as 128 on tape. Duri ng readi ng, 128 is a Iways read and translated
as X 'FO'
tA tape record consisting of only J characters is defined as a tape mark
The following byte count conditions exist in the lOP after
the same record has been written and immediately read in
the pac ked mode:
Bytes Sent
3-4
Bytes Received
3N
3N
3N + 1
3N + 2
3N + 2
3N + 3
3-7 POWER CIRCUITS
3-8 Primary Power (See fi gure 3-4)
Primary power is derived from an external 117 Vac, 60 Hz,
30A source. The 117 Vac are connected to TB 1 on the power
distribution chassis. When power is applied to TB 1, the
muffin fan assembly, at top and bottom of the module cage,
and the PT19 converter power supply are energized. The
2000 Hz output from the PT19 power supply is used as the
input power source for the PT16 and PT18 power supplies,
which generates the necessary dc voltages for the system.
SDS 901013
BYTE 1
BYT,E 2
I
\
BYTE 3
5(6
7
8 9 10 11 ./12 13 14 15 16 17 118 19 20 21 22 23
1
1
1 0
1 1 .1
0 1 0
1 1 0
1
1 0
0 0' 1
I
1
1 0
1 1 1 0 1 0
1 1 0
1
1 0 0 1
BIT POSITION
0 1 2
3 4
MEMORY/I/O SYSTEM
1 1 0
0
0
CONTROLLER
1 1 0
0
0
1
I
0 1
WRITE TAPE PACKED
EDGE NEAREST TRANSPORT FRAME
0
PARITY(ODD).:- 0
0
1
1
0
0
0
1
0
1
3
0
0
0
4
0
(LEAST SIGNIFICANT BIT) 5
0
TAPE
----MOTION
2
1
0
0
READ TAPE PACKED
\
CONTROLLER
1 1 0
0 0
o\ 1
1
1 0
1 1 \11
0
1 0
1 1i 0
1
1 0 0
1
1 1
1 0
1 1 )1
0
1 0
1 1· 0
1
1 0
0
1
\
I/O SYSTEM/MEMORY
1 1
0
0
0
oi
I
BIT POSITION
0 1 2
3 4
5
i
6
7
8 9 10 11 112 13 14 15 16 17,18 19 20 21 22 23
l
:
BYTE 1
\
BYTE 2
I
I
BYTE 3
\
90 10 13A. 303
Figure 3-3. Data Representation, Packed Binary Mode
3-5/3-6
SDS 901013
If
TBIB
AC HOT
7....
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LEGEND
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17
18
THERMAl TIME-DELAY RELAY
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,
_ _ _ _ _ _ _ _ -l
Figure 3-4. Power Distribution Chassis,
Schematic Diagram
901084A.711
3-7/3-8
Paragraphs 3-9 to 3-13
SDS 901013
One side of the primary power line is routed from the power
distribution chassis to the POWER switch on the operator
control panel. Pressing the POWER switch to the ON position energizes relay K6 and thereby connects 117 Vac to
the following parts of the system:
a. The vacuum motor. When power is applied, the
motor starts rotati ng.
K5 also connects the ac return line to the SCR's, which are
not yet conducting.
d. Relay K7 pulls in after a 100 to 200 ms delay and
turns on the SCR's. This delay is determined by capacitor
C7.
c. The positive pressure pump. It starts functioning
if the sliding door is closed.
e. The servo power supply capacitors are charged
while the current is limited by choke L1. Relay K9 energizes after a O.B to 2.8 second delay, causing relay KlO to
energize and short out the choke coil Ll. This delay is
determined by capacitor C6 in series with resistor R7 in the
Q1 base bias circuit and the 5.6V zener diode in the Q3
base bias circuit. After relay K9 energizes, Q3 is shunted
by contacts K9-6 and K9-7.
3-9 Power Distribution (See figures 3-4 and 4-24)
3-11
The power distribution chassis has the following purposes:
When the POWER switch is pressed to the OFF position, the
following events take place:
b. The transport drive electronics assembly (if the
circuit breaker on the power distribution chassis is closed)
and the servo amplifier power supplies.
a. To provide a means of controlling ac power into
the stati on.
b. To apply power in the station by stages. This
action diminishes current surges and minimizes noise
transi ents.
c. To provide a delay before ac power is applied to
the next station in the system. This ensures that the stations
are energized in sequence rather than simultaneously,
which would produce an undesirable current surge.
3-10 Turn-On Sequence
After the ac cord is plugged in, relay K3 turns on the power
for the blower and the PTl9 power supply. Relay K3 is controlled by the LOCAL-OFF-REMOTE switch 51 on the power
distribution panel. If this switch is in the OFF position,
power cannot be turned on. If the switch is in the LOCAL
position, relay K3 energizes immediately after the power
cord is plugged in. If the switch is in the REMOTE position, relay K3 energizes after approximately one second.
Time delay relay K1 with R6 provides a one second delay
(see figure 3-4). This delay prevents the simultaneous
energizing of all the stations in the system.
Power to the vacuum blower, positive pressure pump, and
servo power supply is switched on by relay K5 and SCR's
Q4 and Q5, which are operated by the control circuits and
relays. When the POWER switch on the operator control
panel is actuated, the following events take place:
Turnoff Sequence
a. Re lay K6 opens and removes power from the primary of the transformer.
b. Re lay K7 drops out shortly after step a occurs,
removing the forward bias from the SCR's.
c.
zero.
The SCR I s stop conducti ng after the current reaches
d. Relay K9 opens after the power supply capacitors
are discharged through the K9 coi I, wh ich in turn opens
relay K10.
e. Relay KB opens after the voltage across capacitor
C5 reaches approximately 15V. Relay K5 is then deenergized and opens both ac I ines to the vacuum blower, positive pressure pump, and servo power supply. The timing
diagram shown in figure 3-5 indicates the power turn-on
and turnoff sequence.
3-12 STATION
The station consists basically of pneumatic and mechanical
devices, with associated sensing and control electronics,
which allow proper handling of the magnetic tape. Figure
3-6 shows the mai n components of the tape transport. The
station also contains the necessary transducers and motion
and data electronics to store and detect information on
tape. The data electronics is described under the heading
Magnetic Tape System Functions, paragraph 3-57.
a. Relay K6 energizes, which applies primary power
to the transforme r.
3-13 PNEUMATICS
b. Relay KB energizes after a small delay, which in
turn energizes relay K5.
c. Re lay K5 connects the ac hot I ine to the vacuum
blower positive pressure pump and servo power supply.
There are two separate but related pneumatic networks in
the station: the positive pressure system and the vacuum
system.
3-9
SDS 901013
1. TURN-ON SEQUENCE FOR K1 AFTER REMOTE POWER IS TURNED ON
K1
________________~ft~,--~III~III~III1~III~III~IIII~III~IIII~III
0.7 SEC
2 SEC
2. TURN-ON SEQUENCE AFTER POWER SWITCH IS PRESSED WITH POWER OFF
K8
111111111111111
20 MS
80 MS
K5
11111111111111111
20 MS
90 MS
111111111111111111111111
100 MS
200 MS
K7
K10
-------------------~},~I--~I~IIII~IIII~III~IIII~IIII~III~1I11~1I11~1I1~1I11~1111~111I
0.8 SEC
3.
~
l~
TURNOFF SEQUENCE AFTER POWER SWITCH IS PRESSED WITH POWER ON
__________________________________________________
8 MS
K8
2.8 SEC
'~III~""~
30 MS
__________________________________
60 MS
K5111
~I~III~III~_________________________________
30 MS
K10
70 MS
'LIoI.I"I~III.L.L.L.II"Iu..u.III.l.l.lJIlIlu...1~_ _ _ _ _ _ _ _ _ _ _ _ _ __
60 MS
140 MS
901084A.313
Figure 3-5. Power Sequence, Timing Diagram
3-10
SDS 901013
MAIN
FILE REEL
TRANSPORT MOTOR
CASTING AND BRAKE
TB1 T
FIXED REEL
MOTOR AND
BR.AKE
APSTAN
MOTOR
HEAD COVER
ACTUATOR
WRITE ENABLE
SWITCH
POSITIVE PRESSURE
REGULATOR
VACUUM SWITCHES
POSITIVE PRESSURE
PUMP
901013A.307
Figure 3-6. Magnetic Tape Transport, Back View
3-11
Paragraphs 3-14 to 3-15
SDS 901013
3-14 Positive Pressure System
Air pressure is generated by the positive pressure pump and
fed to the air plenum, which forms part of the transport
casting. The air plenum supplies air to the tape guides, the
head cover actuator, and the positive pressure switch. The
amount of pressure is controlled by a regulator connected
to the air plenum (see figure 3-7).
ROLL
PIN
SPRING
WASHER
TAPE
PATH
CAP
I
TAPE GUIDES. (See figures 2-6 and 3-8.) The tape guides
provide a continuous flow of air from thei r hollow cores
(connected to the air plenum) to the surface facing the tape.
The air flow is regulated to provide a cushion of air between
tape and tape guide. This air layer ensures that only the
read/write heads touch the recording surface of the tape.
HEAD COVER ACTUATOR. (See figures 3-6 and 3-9.) The
head cover actuator consists of a piston and plunger assembly mounted in an airtight cylinder. When positive pressure
is applied to the cylinder, the piston presses a return spring,
which closes the head cover with the plunger. When no .
pressure is applied to the cylinder, the head cover remains
open.
POSITIVE PRESSURE SWITCH. (See figures 3-6 and 3-10.)
The positive pressure switch is connected to the air plenum
and located above the vacuum blower. This switch provides
a means of sensing a minimum of pressure in the air plenum,
as determined by the adjustment of the positive pressure
regulator. The switch is in series with interlocks A and B
in the vacuum chambers (see figure 2-2). When the positive
pressure reaches a specified value of 5 Ib/in 2 the switch
closes. The station becomes ready if interlocks A and Bare
closed.
Figure 3-8. Tape Guide
3-15 Vacuum System
A vacuum is created by the vacuum blower that is located to
the right of the blower shelf (see figure 3-6). The vacuum
blower is connected to the vacuum plenum at the bottom
front of the station through a solenoid-operated valve. The
vacuum plenum provides a vacuum to the vacuum storage
chambers, the write enable switch, and the tape cleaner.
The vacuum blower is also connected to the capstan motor
housing for cooling purposes.
rr:
~t----·~~
==1
IN.
MAX 2.81
EXPANSION
r--I
2. 56 IN.
r \ _ MIN
--------~~
0.750 IN.
DIA
t
90 10 13A. 308
Fi gure 3-7. Pressure ReglJ lator
3-12
901013A.309
VACUUM VALVE. The vacuum valve is connected between
the vacuum blower and the vacuum plenum. The valve is
open or closed depending on whether the station is in a
ready or not-ready condition. The vacuum valve is controlled by a solenoid, which is connected in series with the
bottom door switch (SN1). The solenoid is closed only
when the sliding door is fully closed. When SN 1 is closed,
and the station is in a ready condition, the solenoid is
energized and the valve opens.
VACUUM STORAGE CHAMBERS. (See fi gures 1-1 and
3-18.) The tape transport uses tape loops to reduce to a
minimum the tape mass handled by the capstan during start
and stop times. The loops, located at both sides of the
capstan, are stored in two chambers associated with the
fixed reel and the file reel (see figure 2-6).
When tape movement is required, the capstan pulls the tape
from the loop in one chamber and places it in the other
chamber, to form the other loop. As tape is drawn from the
file chamber, it is replaced by the file reel. As tape is fed
into th;"fixed chamber, the fixed reel takes up the slack.
The net effect is, first, that inertia is minimized in the capstan system, so that the system on Iy has to acce Ierate the
SDS 901013
mass of a few feet of tape. Second, the tape loops in the
vacuum storage chambers effectively separate the capstan
movements from the reel movements. This allows the capstan to accelerate at hi gh rates without requiring the reels
to rotate at exactly the same rate.
The sensing holes placed across the length of the chamber
actuate the vacuum interlock switches and the tape loop
position switches. These vacuum switches function as protection and control devices, respecti ve Iy. The vacuum
interlock switches interrupt the reel drive circuits, which
in turn stop the reel motors when either the vacuum fails or
the tape is in an abnormal position. Figures 3-6 and 3-18
show the location of these switches, while figures 3-13 and
4-13 show their function in the control circuits. A detai led
operation of these switches, in association with the servo
electronics, is given in paragraph 3-18.
ACTUATOR
ROD
SPRING
PISTON
PISTON
COVER
DIAPHRAGM
901013A. 310
Figure 3-9. Head Cover Actuator
-I
0.750 IN.
IN.
~0.875
~
COM
The vacuum storage chambers also produce and maintain
proper tape tension along the tape path. Each loop fits
snugly into the chamber, effectively dividing it into two
sections. The bottom portion of the chamber is connected
to the vacuum plenum and is therefore under reduced pressure. The upper part is at atmospheric pressure, which
pushes the tape down and provides the necessary pressure
on the loop.
~
WRITE ENABLE SWITCH. The function of the write enable
switch is to permit or prevent recording on tape. This function is called file protection and depends on the presence
or absence of a fi Ie protect ri ng in the file reel (see paragraph 2-12). The file protection function is performed by
the write enable switch actuator (see fi gures 3-11 and 4-2)
and the write enable vacuum switch (see figure 3-6).
The write enable switch actuator assembly is mounted
immediately below the file reel hub. This assembly contains
a pi ston with a pushrod connected to one end. The pushrod
extends through the front of the transport casti ng. The fi Ie
reel contains an inner groove into which a file protect ring
can be inserted. When the fi Ie reel is mounted, the fi Ie
protect ring, if installed, makes contact with the pushrod
on the actuator, and the piston is pressed. This causes holes
to close around the circumference of the actuator cylinder
housing. When this occurs, pressure in the cylinder approaches a vacuum, which is produced by a hose connecting
the write enable switch actuator to the vacuum plenum.
Another hose connects the write enable switch actuator to
the write enable vacuum switch mounted at the back of the
transport casting. This switch is of a diaphragm type and
c loses when the pressure in the actuator cyl i nder approaches
a vacuum.
When the file protect ring is not installed in the file reel,
the holes around the actuator's cylinder housing are exposed
to the atmosphere. Under these conditions, pressure on both
sides of the write enable switch diaphragm is the same, and
therefore the contacts are open.
N. O.
CIRCUIT DIAGRAM
901013.A.311
Figure 3-10. Positive Pressure Switch
Vvhen the write enable switch is closed, a ground is provided to one side of the coil in file protect relay K6. This
re lay is mounted on the re lay chassis assembly (see figure
3-12). The other si.de of the re lay K6 coi I is connected to
3-13
Paragraphs 3-16 to 3-17
PISTON
SDS 901013
HOUSING
write heads, to the other reel. Motion during a space operation is the some as for a read operation.
Tape motion is determined by a single capstan. The tape is
continuously in contact with the capstan and moves only
when the capstan rotates. The reel and capstan movements
are isolated from each other by the loops in the vacuum
storage chambers. Therefore, the capstan and the reels,
with their respective tachometers, form separate but related
mechanical systems. Figure 3-13 shows a block diagram of
both the reel and capstan control electronics.
3-17 Capstan Motion (See figures 3-13 and 4-10)
RETAINING RING
SPRING
901013A. 304
Figure 3-11. Write Enable Switch Actuator
+25 Vdc. Relay K6 is therefore energized, which causes
the following to occur:
a. The +25 Vdc write current source is connected to
the write heads. This enables the heads to write on tape.
b. A ground is placed on the write permit line to the
controller. This line is designated file protect in the
controller.
c. A ground is removed from the FILE PROTECT indicator on the operator control panel. This turns the indicator
off.
With the file protect ring removed from the file reel, the
write enable switch cannot close, and relay K6 is not
energized. Therefore, the following conditions exist:
a.
No write current is avai lable to the write heads.
b.
The write permit line is floating.
c. A ground is provided to the FILE PROTECT indicator. This turns the indicator on.
TAPE CLEANER. The tape cleaner, contained in the head
assembly, consists of a slightly curved surface over which
the oxide side of the tape passes. The curved surface has
a sharp-edged hole pattern that removes dirt and forei gn
particles from the tape. Vacuum is connected to the rear
of the hole pattern to dispose of the dirt and foreign
particles.
3-16 MECHANICS
Three fundamental tape motions are necessary during normal
station operation: forward, reverse, and rewi nd. Forward
and reverse motions are performed during read or write
operations. The tape is moved from one reel, past the read/
3-14
The capstan system consists of a reference generator, ramp
generator, tachometer, preamplifier, ampl ifier, and capstan
motor. Capstan motions are controlled, through a feedback
loop, by the capstan servo electronics. When a motion order
is received from the controller, the reference generator
triggers a ramp in the ramp generator. This ramp closely
matches the output voltage of the capstan tachometer. The
voltage difference between the ramp and the tachometer
output is amplified by the preamplifier and the power amplifier. The amplified difference signal slows or accelerates
the capstan motor. This change in motor speed affects the
output voltage of the tachometer, which is mechanically
coupled to the capstan motor. The increment in tachometer
output is compared with the ramp, closing the feedback
loop, and the process is repeated.
Capstan motion may be initiated in manual or automatic
mode. When in manual, the CAPSTAN FWDS or REVS signal comes true, depending on the switch pressed on the
operator or auxiliary control panel. Figure 3-14 shows the
logic involved in this operation.
When motion is initiated in the automatic mode, the RVRC
line, from the controller, comes true for reverse motion, or
false for forward motion. This causes RVRS or NRVRS to be
true, respectively. These two terms are AND-gated with
term OSCTS on separate gates on the station logic (see figure 3-15). Term OSCTS comes true when the station enters
state 0 after being selected. The outputs of these two gates
cause the RVSS term to be true for reverse or false for forward motion. RVSS is AND-gated with START CONTR to
produce term REVS. START CONTR is true if the station is
in the automatic mode.
When reverse motion is specified by RVRS coming true, the
RVSS term is latched true by NRVRS. This latch allows the
controller to drop the RVRC direction control line to a
particular station and still have motion maintained in that
station. This action is required during motion delays.
Term REVS is true when reverse motion is required or false
when forward tape motion is required. Terms REVS and
NRVSS are AN D-gated with the activate motor si gnal ACMS:
ACMS
=
START CONTR FS1 S
Terms CAPSTAN FWDS and CAPSTAN REVS are originated
from two separate branches of this circuit, as is shown in
figure 3-14.
SDS 901013
~HEllATIC TRANSPORT)
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NOTE: REFERENCE SOS OWG: 135531-1A
A
Figure 3-12. Re lay and Interlock
Functional Diagram
901013A.312
3-15/3-16
SDS 901013
FROM TAPE
DIRECTION
CIRCUITRY
t--FO_R_W_A_RD_ _~CD HTl2
REVERSE
t-Ir-----~
CAPSTAN
TACH
CD OTlD
REFERENCE
GENERATOR
RAMP
GENERATOR
14U
15U
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CD HTl3
CAPSTAN
PREAMPL
19U
I
.....----..-+1
IL
CAPSTAN
POWER
AMPL
I
CAPSTAN
POWER
SUPPLY
I
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MOTOR
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REVERSE
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I FIXED REEL ..-f-----+-____~
I POWER
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f(3)---,
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I
I
FILE REEL
POWER
AMPL
L_
I
I
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FORWARD
REVERSE
CD
PHOTO
SENSE
HTl9
FIXED REEL !4--...:........--------iI--\- CAPSTAN REVS
I
-21
REWIND RELAY 0
NORMAL
RELAY AND INTERLOCK)
( FUNCTIONAL 01 AGRAM
I
~ _.:_~o.!~.:-Q....~-~-~h-~-~-t-:-~~~--4Jo.;.;...---l
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-21
(REEL SERVO FUNCTIONAL)
DIAGRAM
(~~~~lL I~~~~AO~K)
6U30
Figure 3-14. Station Motion, Functional Diagram
NOTE: REFERENCE SOS OWG: 135S011
901013A.314
3-19/3-20
SDS 901013
OSCT . : ;:3: . , 7_ _-.
37
>---.............. RVSS
OSCTS
~3~6_ __
19S
RVRS 35
~--"
NRVSS
46
START CONTR
18S
50 _ __
REVS
901013A.315
o
_
Figure 3-15. Direction Latch
START CONTR enable is true if the station is in the automatic mode. FSl S in the state counter is set on any operation that moves tape except off-line rewind. Therefore,
NRVSS is true when REVS is false; and so either
CAPSTAN FWDS or CAPSTAN REVS is true when tape
movement is to take place. These signals are applied as
inputs to the reference generator.
output signal from the ramp generator. When accelerating
to nominal speed, the ramp goes from zero to maximum
amplitude in about 4 ms. During high-speed operation, the
ramp goes from zero to maximum in approximately 1.7 seconds, in order to decrease the acceleration and a Ilow the
reel servo to maintain the loops in the vacuum chambers.
REFERENCE GENERATOR. The reference generator is
contained in module HTl2, chassis U. It is shown in figure 3-16 as part of the capstan circuitry. A buffer is
connected to the reverse input line and an inverter to thOe
forward input Iine. The output stage consi sts of a noninverting operational amplifier.
The ramp generator is contained in module ono, chassis U.
It consists of a diode bridge and an inverting high gain
operational amplifier. If the input to the bridge is positive,
a certain amount of current exists from the +25V supply into
the amplifier. This produces a reverse tape motion condition. If the input is negative, a current path is established
from the -25V supply into the amplifier. This produces a
forward tape motion condition.
When a capstan direction signal is received in pin 22 for
forward or pin 47 for reverse, either the buffer or inverter
causes a reference current to appear at the summing point
of the operational amplifier. Potentiometers R15 and R16
provide tape velocity adjustment. The voltage at the output of the operational amplifier is negative for forward
motion and positive for reverse motion. This output, at pin
10 of 14U, is connected to the input of the ramp generator,
pin 37 of 15U.
RAMP GENERATOR. (See figure 3-16.) Capstan acceleration and deceleration is determined by the slope of the
The ampl itude and slope of the ramp are determi ned by a
combination of resistors and capacitors in a feedback loop
that is switched by relay K3 (see figure 3-12). For 75 ips
operation, K3 is deenergized. This decreases the amplitude
of the ramp and increases its slope. For 250 ips, high-speed
operation, K3 is energized. This increases the amplitude
and decreases the slope of the ramp. The output of the ramp
generator is connected to the capstan preampl ifier through
the capstan tachometer.
3-21
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FROM
I1U-29
FILE RS -ltV
FIXED RfJ REV seR DR
IMOTION FUNCTIONAL)
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DIAGRAM
SASB
~ TB2H-4
16U
I
,R.UIP GEN
'ACH HI
(CAfl'STAN
~
OZ_Z_U_-_19~___________________~C-E-FI-L-E-R-M-B--S-eR-GA-T-E+_~---------OT82o-12
CAP FWDS
MOT ION
.............L--;----=i
3.5 18U
(
FUNCTlONAL DIA'~
PWR TURN ON UMIT FWD
CAPSTAN SERVO \
FUNCTIONAL DIAGRAMI
17 18U
CAP REVS
!
~
TBIT-S
TIIT-4
I
DIAGRAM
FIXED REEL
MOTOR
F
R
W
E
'-
I6U-4 TO
FILE RS
17U-7
LOAD DISABLE
16U-44
-
16U-23
FILE R S
17U-2
" 2V ZZ
PS
I U
~~
r AMP BIAS
FilE SERVO
ZERO ADJ '""""-
FILE RS-FWD POSIT
BIAS 16U':'4Z
O:::S")Too_R_A-r--+_+-___+-__-IIN-_-O
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R34
~--.JVt.f'r---~
IOU-50
TBIT-7
FILE RS+ ltV
FROM
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.---
S5~fOo---2-4U00---21-~~~~-~~RNI5~--~
17U-34
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-"'
B
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Lr,:;;-. 9
+II.ZV 15
16U-43
_ _ _ _ _ __
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~ RESISTO~
18
r--~~~---~----~A~__~F~IL~E~~~~~____-r--i16U~~~
~::"TT~:-5 24U-12
16U
KZ
~ READY
RELAY
-'P-
~I
17U-25
• RI8
Figure 3-17. Reel Servo, Functional Diagram
901013A.317
3-25/3-26
SDS 901013
FIXED
CHAMBER
FILE
CHAMBER
I
I
INTERLOC~
Sl F
B
K_ r'
SHORT LOOP SENSORS
SlC 'V-;NTERLOCK
A
~ _I
A
ft
S2C
0-- - ---1. 10 VELOCITY
S2F
-~
S~ ___ --0.9 VELOCITY _____ ~F
DEAD BAND
S4C
S4F
0------0.9 VELOCITY - - - - - ~
S5C
0- - - -
o~
V
S5F
--1. 10 VELOCITY - - - - -
~
LONG LOOP SENSORS ' -
"'lIIr'O
~
Fi gure 3-1B. Vacuum Chamber, Tape Position Switches
1
3.000 IN.
-
T0.500 IN.
DIA TYP
--L
L...o
2
CIRCUIT DIAGRAM
901013A.319
Figure 3-19. Vacuum Switch
Both tachometers function in a similar manner. When the
tape reel is mounted on the transport, the Mylar (back) side
of the tape is threaded around the tachometer pulley. When
the reel is in motion, tape movement causes the tachometer
to rotate and generate a voltage proportional to the tape
speed. The tachometer output is applied to the summing
junction of the respective reel servo amplifier through a
velocity adjustment potentiometer.
REEL SERVO ELECTRONICS. (See figure 3-17.) The fixed
reel servo is an HT19 module located in 17U. The file reel
servo is an HTlB module located in 16U. The reel servo
modules receive the followi ng input si gna Is:
a. L FILE FWD on pin 40 of the HTlB module. This
signal is received from the load logic when the loading
sequence is in progress.
b. A reference input (RAMP GEN H1) on pin 44 of the
HTl8 module and pin 31 of the HTl9 module. This is the
si gnal from the ramp generator that is fed to the summi ng
amplifier input junction through the tape position switches.
c. The tachometer inputs on pin 3 of the HTl8 module
and pin 4 of the HT19 module.
When a forward motion operation takes place, the ramp
generator produces a positive ramp that is applied simultaneously to the capstan preampl i fi er and the ree I servo
electronics input. This initiates the following sequence
of events:
a. The capstan begi ns to rotate forward, taki ng tape
from the fi Ie chamber and depositing it into the fixed
chamber at a rate determi ned by the slope of the ramp.
1.640 IN.
~
1
TACHOMETER. (See figure 3-17.) There are two tachometers in the reel system, the fixed reel tachometer and the
fi Ie ree I tachometer. The ree I tachometers are mounted
between the reel and vacuum chamber (see fi gure 3-13).
_ _-J
900837A.l0
VACUUM
ORIFICE
Switches S2F, S3F, S4C, and S5C are active during forward
tape motion; S2C, S3C, 54F, and S5F are active during
reverse motion. When the transport is in standby condition,
the tape loop in the file chamber is positioned between S3F
and S4F, and the loop in the fixed chamber is between S3C
and S4C. This area is called the tape motion dead band.
A holding bias is applied to the summing junctions to prevent amplifier drift and tape creepage.
b. When the file chamber loop is drawn up past S3F,
the switch closes and the ramp signal appears at the summing junction input of the file amplifier, where it is
inverted and fed into a buffer amplifier. (The output of the
fi rst ampl i fier is actually sent to a buffer and an inverter,
but the inverter is biased to reject the negative going
si gnal.) The ramp is inverted again and fed to the gate
of Q2, enabling it to drive the file reel forward.
3-27
SDS 901013
c. The file reel tachometer is set into motion by the
moving tape and a voltage is generated opposite in polarity
to the reference input. When the velocity of the tape going
into the chamber is 90% of the velocity of the tape leaving
the chamber, the tachometer output is enough to cance lout
the ramp voltage at the summing junction and remove the
accelerating drive from the file reel motor.
d. The tape is still leaving the file chamber faster
than it is being replaced by the fi Ie reel; consequently, the
loop moves up to S2F, and S2F is closed. When S3F and
S2F are both closed, the ramp voltage at the summing junction is raised to the point that the file reel velocity has to
be increased unti I the tachometer output is great enough to
cancel out the ramp. The velocity of the tape going into
the chamber is then 110% of the velocity of the tape
leaving the chamber.
e. With tape now being fed into the fi Ie chamber
faster than it is being taken out, the tape loop descends.
below S2F and allows S2F to open. The file reel then slows
the tape to its 90% velocity, the loop is drawn up by the
capstan again, and the cycle keeps repeating as long as the
capstan is moving forward.
The same sequence appl ies also to the fixed reel and
chamber. The tachometer and reel functions are the same
for both forward and reverse operations. In reverse operation, the polarity of the input si gnal changes and certain
assignments in the servo electronics are transferred to different components, as follows:
a. Fixed reel motion is begun when the tape loop in
the fixed chamber is pulled up across S3C, which allows
the ramp signal to proceed to the input of the fixed servo
electronics. Switches S3C and S2C then operate alternately, keeping the tape loop between them during the
tape motion.
b. File reel motion is initiated when the loop in the
file reel chamber drops below S4F, allowing the ramp signal to proceed to the input of the file servo electronics.
Switches S4F and S5F then operate alternately, keeping the
tape loop between them during tape motion.
c. The summing amplifier output is inverted and fed
to the gate of the reverse SCR, enabl ing it to drive the reel
in the reverse direction.
POWER CONTROL. (See figure 3-17.) All reel motor
power control is achieved through the use of SCR's. Q1
and Q2 control file reel motor reverse and forward motions.
Q3 and Q4 control fixed reel forward and reverse motions.
Q5 connects the 50 Vdc power supply to the reel motor
circuits during normal speed operation; Q5 is off during
high-speed operations. Q6 connects the 30 Vdc power
supply in series with the 50 Vdc power supply during highspeed operation; Q6 is off during normal speed operations.
Q7 and Q8 permit the reels to decelerate gradually after
a motion takes place. During standby, Q7 and Q8 provide
3-28
a small steady current to the reel motors so that they pull
the tape in opposite directions with enough force to compensate for the pull in the vacuum chambers.
The outputs from the reel servo electronics in modules HT18
and HT19 are applied to the motion control SCR's from the
following points:
a.
b.
pin 26.
File reel reverse amplifier output, on HTl8 pin 1.
Fixed reel reverse amplifier output, on HT19
c.
File reel forward amplifier output, on HTl8 pin 38.
d.
Fixed reel forward amplifier output, on HT19 pin 8.
To prevent undesired reel motion when the transport is not
ready for operation, the reel servo outputs are clamped to
ground by diodes through the normally closed contacts 8
and 9 of ready relay K2. When K2 is energized, the servo
electronics outputs are ungrounded.
Power Turn-On Limit. The function of the power turn-on
Iimit circuit is to prevent the reel motion control SCR ' s from
being turned on at the peaks of the power supply voltage.
This avoids excessive turn-on current surges and resulting
transients. The circuit is contained in module WT18,
located at U20.
The pulsating dc voltage of the 50V power supply is sensed
and input at pin 39. Whenever the pulsating voltage
reaches a 30V level, the power turn-on limit outputs (pins
34, 35, 30, 33, 21, and 22) are raised from a ground potential to +8 Vdc. This voltage is applied to the drivers of Q1,
Q2, Q3, Q4, Q7, and Q8, preventi ng them from turni ng on
the SCR's. As soon as the pulsating voltage cycles to a
level lower than 30V, the drivers are again enabled to
trigger the SCR's. Once an SCR is turned on, it remains on
regardless of gate drive.
Coast Enable. The function of the coast enable circuit is to
switch Q7 and Q8 on or off at the times when a change of
tape motion is required. Q7 and Q8, in turn, partially
energize the reel motor reverse and forward windings, to
provide adequate deceleration. Duri ng standby, Q7 and
Q8 provide a current of 1A to their respective motor windings in order to keep the tape motionless.
When the capstan is being driven forward, the tape position
switches cause the file reel to rotate in the same direction
unti I the reel velocity exceeds the capstan velocity. At
this time the file reel forward SCR driver signal goes to
zero, and the following events take place in the logic
circuit:
a. The low input signal from the file reel forward SCR
drivers fed to the inverter on pin 38, slot 18U, results in a
high output, which feeds to the input of an AND gate.
Paragraph 3-19
SDS 901013
b. The high capstan forward signal on pin 30, slot 6U,
feeds to the other gate input, pin 28, slot 18U, enabling
the gate to feed a high input to the buffer.
c. The buffer output enables SCR Q7, allowi ng current to flow through the reverse winding of the file reel
motor. This current is limited by the series resistor to a
value that permits the reverse winding to decelerate the
motor gradual Iy.
When the capstan is driven in the reverse direction, the
inputs are on pins 9 and 19, and Q8 is enabled to allow
limited current flow through the forward winding of the
fixed reel motor, which causes the motor to decelerate
gradually. When there is no capstan drive command present,
the direction ONS signal from pin 19, slot 6U, is low. This
causes pin 21, slot 18U, in the WTl6 coast enable module
to be low. The output of the inverter connected to pin 21,
slot 18U, goes true. This causes Q7 and Q8 to be forward
biased, thereby producing approximately 1 amp of current
through the fi Ie reel motor reverse and the fixed reel motor
forward windings. The torque developed by the 1 amp of
current plus the brake drag is enough to counteract the tape
tension due to the vacuum. This keeps the tape motionless
in the tape motion dead-band portion of the chamber.
MOTOR AND BRAKE. (See figures 4-7 and 4-12.) The reel
is driven by a dc series motor with separate field windings
to control forward and reverse motion. A friction brake is
attached to the rear of the motor. Ree I moti on is prevented
when no power is applied to the brake. This situation exists
when ready re lay K2 is deenergized and the sl idi ng front
door is closed or when transport power is lost.
Reel motion is permitted when power is applied to the brake.
This situation exists when K2 is energized, or when K2 is
deenergized and the sliding front door is pushed down to
the fully open position, thereby closing the bottom door
switch.
REEL SERVO POWER SUPPLY. (See figures 3-17 and 4-28. )
The reel servo power supply is located in the tape transport
drive electronics chassis. It furnishes driving power for the
reel motors and brakes. Circuit protection is provided by
dc interlock relay K1. Dc power comes from two full-wave
rectifier circuits, providing 50 volts and 30 volts, respectively. The 50 Vdc supply is used to drive the motors at
nominal speed and to supply brake power. For high-speed
operation, the two supplies are cascaded to provide greater
dri vi ng power.
a. Contacts 8 and 9 open. This leaves the gate of Q5
open (see figure 3-17).
b. Contacts 15 and 16 close. This turns on Q6, which
turns off Q5 and places the 30V and the 50V supplies in
series.
c. Contacts 12 and 13 close. This provides a dc
enable signal to the backup circuitry in the station motion
control logic (see figure 3-14).
d. Contacts 6 and 7 close. This disables the load
point AND gate that turns on the LOAD indicator driver
(see figure 3-22).
During a normal speed operation, K4 remains energized
unti I the tape stops with the BOT marker located at the
sensing head. At the end of a rewind operation, the BOT
marker is detected, but due to the high speed of the tape,
the BOT marker overshoots the photosense head before it
stops. Therefore, the tape has to be moved back unti I the
BOT marker is located at the sensing head. To prevent a
false load point indication, K4 is kept energized until the
BOT marker is backed up.
REWIND CIRCUIT. (See figure 3-14.) During an on-line
rewind, the term REWS is AND-gated with signal DIRECTION ON, which causes the term FASTRONS to go true.
When the BOT marker is first detected while rewinding,
term REWS goes false, making FASTRONS go false.
During an on-I ine rewind operation, when the BOT marker
is detected, the FAST signal from 4U-9 goes low, causing
FASTRONS to go false. Enable 45SS is true. When
FASTRONS goes low, K4 is deenergized and the backup
circuit is disabled after a 500 ms delay produced by a single
shot-designated F delay. This action provides enough time
for the tape to dece lerate.
BACKUP CIRCUIT. (See figure 3-14.) The function of the
backup circuit is to produce a forward movement that places
the BOT marker over the photosense head after a rewi nd
operation. The backup circuitry is uti lized only during fast
reverse tape motion. When the leadi ng edge of the BOT
marker is detected after a fast reverse tape motion operation, the term BOTH comes true. This enables the BOTH
de lay si ngle shot:
BOTH DELAY
BOTH REWIND RELAY OFFS
3-19 Fast Motion
The term REWIND RELAY OFFS is true when K4 is
energized.
When an on-line rewind operation is to be initiated or
when fast tape motion is started from the auxiliary control
panel, the term FASTRONS comes true (see figure 3-14).
This enables the fast motion circuitry by making the K4
relay driver go false. The coil of K4 is then provided with
a return path and K4 is energized (see figure 3-12). Under
this condition, the following events take place:
The trailing edge of the BOT marker triggers the BOTH
delay. This takes place approximately 4 I-IS after the
leading edge of the BOT marker is detected. The BOTH
DELAY single shot goes true for 500 ms. The purpose of
this delay is to allow the tape to decelerate before the
backup motion begins. The output of the BOTH delay single
shot is AND-gated with an enable signal that is true when
3-29
Paragraph 3-20
SDS 901013
K4 is energized. This output is fed to a 500 I-'s single shot
delay that produces term BACKUPS:
BACKUPS
=
BOTH DELAY REWIND RELAY ONS
The REWIND RELAY ONS enable is true as long as the fast
relay is energized. The fast relay remains energized until
the fast relay delay times out.
The equation for BACKUPS denotes that terms BOTH DELAY
and REWIND RELAY ONS must come true to provide a
trigger to the one-shot. However, the one-shot is triggered
only when one of the two input terms goes false. Neither
term goes false unti I approximately 350 ms have elapsed
after the detection of the BOT marker. This is enough time
to allow the tape to decelerate. The 10 I-'s BACKUPS single
shot is then tri ggered.
When the BACKUPS term comes true, it is AND-gated with
term REV OFF to produce the BACKUPS B input to the FWD
flip-flop reset terminal. The REV OFF term comes true
whenever the BOT marker is detected. Therefore, the FWD
flip-flop is reset to apply capstan forward motion when the
term BOTH DELAY times out, since the rewind relay stays
energized. The capstan moves the tape forward unti I the
BOT marker is again detected. At this time, the BOTEOTH
enable comes true and sets the FWD fl ip-flop. Capstan
power is then removed and the tape stops.
causes interlocks A and B to open. The clock input to the
load flip-flop comes from the controller during normal operation. When the LOAD switch is pressed, an input is also
provided to tri gger the SAS one-shot, which goes true for
500 ms. This provides a signal to the fixed reel servo preamplifier in slot 17U that prevents the fixed reel from
turning. This one-shot is also input to an inverter on the
set input to the load flip-flop. As long as the one-shot is
timing out, it will not provide a true input to the set side
of the load flip-flop. With the load flip-flop reset, the
following occurs:
a. The reset output of the load flip-flop provides an
enable to the relay driver in slot 28U that drives the ready
relay regardless of the interlock system. The ready re lay is
energized, which causes power to be applied to the reel
servo brakes. This action releases the brakes.
POPO HUB
PIVOT ARM
PIVOT PIN
3-20 Load Operation
Loading the transport with a tape reel initiates the functional operation of the magnetic tape system. The loading
procedure is described in paragraph 2-14. The main features
of the load operation are the push-on, pull-off (PO PO)
reel hub and the automatic loadi ng function.
POPO HUB. (See figure 3-20.) The baseplate of the hub
assembly is attached to the reel turntable by shoulder
screws that permit I imited movement between the hub and
turntable. Wi thi n the assembly three equally spaced radial
arms form knuckle joints with a center post connected to
the turntable. The outer ends of the arms are pivoted to
sliding blocks, or shoes, that are guided in radial channels
and retained by a circumferential rubber ring. In an unloaded condition, the assembly is held away from the turntable by pivot arm movements resulting from ring pressure
on the shoes. When a tape reel is slipped over the assembly
and pressed agai nst the baseplate flange, axial movement
pivots the arm to force the shoes outward and compresses
the ring between the shoes and the reel hub. Continued
axial movement causes toggle action of the arms to lock
the assembly agai nst the turntable.
LOAD FUNCTION. (See figure 3-21.) When the LOAD
switch is pressed, an input is applied to reset the load flipflop to the load state, provided that the swinging front door
is shut and the ready relay is deenergized. The station
should not be ready when a load operation is begun because
ina ready condition the vacuum chambers are empty, which
3-30
SIDE SECTION - LOCKING POSITION
SIDE SECTION - UNLOCKING POSITION
90 1084A. 306
Figure 3-20. POPO Hub Assembly
SDS 901013
LOAD OFF
(REEL SERVO FUNCTIONAL DIAGRAM)
II (S/LOAD OFF)
ALL INT-t-":::;-I
( RELAY AND INTERLOCK)
\{UNCTIONAL DIAGRAM
3
CLKGS
(STATUS FUNCTIONAL\
"
DIAGRAM
)
J
(STATUS FUNCTIONAL
DIAGRAM)
IE
·22
RESETS
STATUS FUNCTIONAL)
(
DIAGRAM
,
.
lilT 8 SW
(RELAY AND INTERLOCK)
\!UNCTIONAL DIAGRAM
15
------"'L..
I-
--'1
§MOWN
IN
~
t1r~
IDEEIIERGIZED POS.
S ~ I -12
-,
~ 32UI
/RnAy "liD INTE"-OCK\'6 -40 I
I
\FaCTIONAL OtAGAAM;
.- -
I
l~
-24
28
(INTBI)
L CAPSTAN FWD
(MOT ION
FUNCTIONAL DIAGRAM)
(.225[( O/S)
,.
IIU
ADJ R3-3 TO 220 MS
-l+ 4
ILOAD PUSHBUTTON
_ -- __ 1- _ (OCp)
U (.EADY ,RELAY) 14
-L
5
13
~EEL SERVO FUNCTIONAL DIAGRAM)
SASB
22
~---~o.zz
LO-AD OFF
(STATUS FUNCTIONAL DIAGRAM)
LOAD
RELAY AND INTERLOCK FUNCTIONAL DIAGRAM)
BOTEOTH
•
R READY
(RELAY AND INTERLOCK\
\FUIICTIONAL DIAGRAM
LOAD OFF
L FILE REEL
FWD
(REEL SERVO FUNCTIONAL
DIAGRAM)
23
30
.
SAS
JI
12
-R READY
L _____ +4J (RELAY
N LOADS
STATUS FUNCTIONAL
DIAGRAM
LOADS
AND INTERLOCK\
\.FUNCTIONAL. DIAGRAM)
•
(5. DOOR sw T83T-9) - - - -......1 __ >----L-OA.-.D INHIBIT
(RELAY AND INTERLOCK
\FUIKTIONAL DIAGRAM
IIIT·8·SW
(RELAY AND INTERLOCK"
\'FUNCTIONAL DIAGRAM)
NOTE: REFERENCE SOS DWG: 01.,...·
Figure
3-21. Load, Functional Diagram
901013A.321
3-31/3-32
SDS 901013
b. The set output of the load flip-flop causes the
output of an inverter in slot 7U to go true. This provides a
forward file reel signal to be applied to the fi Ie reel servo
in slot 16U. The file reel starts turning in the forward
(clockwise) direction, thereby feeding tape into the file
reel vacuum chamber.
c. The set output of the load flip-flop disables the
gate in slot 3U that produces term OPERATIONAL CONTR.
This prevents the station from performing any operation until
the load operation is completed.
d. The set output of the load fl ip-f1op disables the
input to an inverter in the coast enable circuitry in slot
18U. The output of this inverter goes true and enables the
reverse servo circuitry in the file reel servo. This allows
the file reel to decelerate under full power. Deceleration
under full power is necessary because the file reel motor is
accelerated up to approximately 100 ips before the tape
reaches interlock B. When interlock B closes, the capstan
forward signal controls both the capstan speed and reel
motor speed. Because the reel motor speed is much higher
than the 75 ips, the low decelerating torque applied by the
count system is not great enough to bring the reel motor
speed down to 75 ips within the avai lable chamber length.
e. When the tape enters the fi Ie vacuum chamber,
the INTB (interlock B) vacuum interlock switch closes and
initiates the followi ng:
1. A true INTB1 input is provided, which triggers
a 220 ms one-shot located in slot 11 U. The one-shot goes
true for 220 ms. This provides a signal to the fixed reel
servo in slot 17U that prevents the fixed reel from turning.
Tape is thereby safeguarded from being pulled out from the
fixed chamber while it is being loaded. This 11U one-shot
is also input to an inverter on the set input to the load fl ipflop. As long as this one-shot is timing out, it does not
provide a true input to the set side of the load flip-flop.
2. An INTB enable is AND-gated with the reset
output of the load flip-flop to provide a capstan forward
signal to the capstan direction and velocity circuitry. The
capstan starts accelerating in the forward (counterclockwise)
di rection, which feeds tape into the fixed reel vacuum
chamber.
3. An INTB enable is provided to an inverter in
slot 7U, the output of which is the file reel forward signal.
The inverter output goes false, which removes the file reel
forward si gnal from the servo and allows the ramp generator
tachometer high signal to take over control of the reel servo.
f.
When the tape enters the fixed vacuum chamber,
the interlock A (INTA) vacuum interlock switch closes.
This completes the interlock network, which causes a
ground to be connected through the ac interlock relay, top
door switch, swinging door switch, INTB = INTA, and
positive pressure switch to the input of an inverter in slot
7U. The output of this inverter, all interlocks closed (ALL
Paragraph 3-21
INT), goes true. Term ALL INT is applied as an input to an
inverter on the set input to the load flip-flop to prevent it
from setting before the BOT tab is reached.
g. The tape settles into the fixed and fi Ie vacuum
chambers and continues to move in a forward direction under
capstan control unti I the BOT marker is detected. When
the BOT marker is detected, the load operation has been
functionally completed and must be terminated by the setting
of the load flip-flop to the load off condition. BOT detection causes term BOTEOTH to come true, which sets the
load flip-flop. When the load flip-flop is set, the folIowing
occurs:
1. The capstan forward signal goes false, which
stops tape motion.
2. The disable is removed from the operational
control gate.
3. The load enable is removed on the input to
the ready relay driver. The ready relay should not deenergize, however, because of the ALL INT signal being true
at th i s time.
4. The LOAD indicator on the control panel
should light. At this point, the complete load operation
is finished.
Protective logic circuitry is provided to terminate the load
operation if one of the following malfunctions exists:
a. Interlock B is not closed because tape was not fed
properly into the file vacuum chamber. The 500 ms SAS
single shot times out and resets the load flip-flop.
b. Interlock B is closed properly, but interlock A is
not closed because tape was not fed properly into the fixed
chamber. The 220 ms single shot times out and resets the
load flip-flop.
c. At the time that both single shots time out, the
ready relay remains energized and the interlock network is
open. Terms R READY and ALL INT are false and the load
flip-flop is set.
d. The BOT marker is not detected. The tape moves
in the forward direction until the EaT marker is detected
or the RE SE T sw i tc his pressed on the operator contra I pane I.
3-21 HEADS
There are three heads in the magneti c tape stati on: the
read/write head, the erase head, and the photosense head.
The read/write head handles data detection and recording.
The erase head permits the erasing of previously recorded
data. The photosense head detects the beginning and end
of the useable porti on of tape. The heads are located
along the tape path on the tape transport, as shown in
figure 2-6.
3-33
Paragraphs 3-22 to 3-26
SDS 901013
3-22 Read/Write Head (See fi gure 4-17)
The read and write heads comprise a single assembly that
includes a tape cleaner. Each head consists of a stack of
seven coils with laminated cores. The core gaps are aligned
perpendicularly to the transport casting, within a maximum
deviation of 150 jJin. Both heads are placed side by side
with the gap lines separated by approximately 0.30 in.
The read head is placed after the write head, relative to
forward tape motion, so that information can be detected
by the read head 4 ms after it is written on the tape, at a
tape speed of 75 ips.
is given under the heading Magnetic Tape System Functions,
paragraphs 3-57 th rough 3-60.
3-26 De lay Count Regi ster (See fi gure 3-23)
The purpose of the delay count register is to provide various
delay times necessary for the correct operation of the magnetic tape station. The delay counter consists of 12 gated
fl ip-flops and their associated input logic. The fI ip-flops
are designated FC01S through FC12S.
The initialize count register term, ICRS, comes true when
the delay count register is to be used:
3-23 Erase Head (See figure 4-16)
ICRS
The erase head, energized during write operations only,
removes all information previously recorded on the tape.
The erasure takes place from the Mylar (uncoated) side of
the tape and across the full width of the tape •. Erasing is
accomplished when the tape comes into contact with the
head gap while the head coil is energized with a specified
current of 60 mAo The resultant erasure leaves a trace of
the previously recorded data. The ratio of the residual
signal voltage to the originally recorded level is greater
than -40 dB.
3-24 Photosense Head (See figures 3-22 and 4-14)
The photosense head consists of a light source and two
photoelectric transducers. These transducers are photosensitive transistors which detect the light reflected by the
markers placed at the beginning and end of tape. The BOT
marker actuates one of the photoe lectri c elements and the
EOT marker actuates the other (see figure 2-3).
BOT DETECTION. When the BOT marker passes over the
lamp, light is reflected from the marker to one of the two
photoelectric transistors. The transistor detects this light
and provides an input to the BOT sense amplifier module,
AT28, located at 13U. The sense amplifier then produces
the following signals: BOTH, LOAD POINT CONTR, LOAD
POINT INDICATOR, and BOT EaT H. These signals are
used to initiate a backup operation (after rewind), light the
LOAD indicator, and stop tape motion.
EaT DETECTION. When the EOT passes over the lamp,
light is reflected from the marker to the other phototransistor. The transistor detects this light and provides an
input to the EaT sense amplifier located at 13U. The sense
amplifier then produces the signals EOT CONTR and BOT
EaT H, which are used to stop tape motion. Figure 3-22
shows the functi ona I ge nerati on of these te rm S.
3-25 MOTION ELECTRONICS
The electronic circuits and their operations described in
paragraphs 3-26 through 3-32, are located in the modules
contained in chassis S of the station electronics (see figure
1-2). The operation and description of the station data
electronics, located in the modules contained in chassis U,
3-34
=
OSC TS + 07SS
Enable OSCTS is true in state O. Enable 07SS is true in
state 7. Therefore, the count register is initialized whenever the station enters state 0 or 7. When ICRS comes
true, flip-flops FC05S through FC12S are reset, and flipflops FC01S through FC04S are set. This configuration
constitutes the initialized condition.
FC01 S through FC 12S are connected as a binary counter,
with FC125 producing the least significant count. The
maximum delay obtainable is approximately 70 ms. However, the maximum delay used in the station is approximately
51 ms. This is the delay required for an erase operation.
The delay counter is clocked by the master clock signal
input to FC12S. This signal originates in the controller and
produces a count approximately every 16 jJS. The delays
are generated by using different configurations of the
counter. The delay times and associated states and instructions are listed in table 3-2.
Table 3-2. De lay Count Regi ster Data
Instruction
State
Delay Time
0
16.71-'s
Rewi nd off-I ine/on-I i ne,
with interrupt
0
16.7 I-'S
Read, wri te, space forward
0
16.7 I-'S
Wri te, space reverse
6
51.3 ms
Erase, BOT read
6
6.5 ms
6
29.9 ms
6
5.5 ms
Read/space
3
5.3 ms
Forward ending delay
6
2.9 ms
Reverse delay
2
5.3 ms
Reverse endi ng delay
Write
BOT read/space
SDS 901013
BOTH
13
BOT PHOTO (ELL H
INTERLOCK \
\fUKtTIOMAL DIAC,RAM J
(MOTIO
IRELAY ,
DRDS _ _--yo_3_9--t2.
31
-V5, C-8v
RELAY &. tNT ERLOCK)
\FUNCTIONAL DIAGRAM
READY INDICATOR D
(SCHEM.OPERATOR (ONT ROL ~NEL)
STARTS
EOT PHOTO CELLtt
I
I
t
--L
_
RELAY & INTERLOCK)_
( F UHe TIOI'tAL OIA.G RA t.t
DIAGR"M)
ST4RTS
r;.-;;;~;U;-~;-,
>-3~5"'___+-L_0_AD_QPOINT (ONTR
I
MOllON
FUNCnoNAL
">-4~5~-::--=_--(>
EOT (ONTR
32~
I
~ ~~I~~~__~
. -:!:-
rf-~~U
jZ7U-36 21U
I=~~R) :
L _________ ..J
FUW-TIONAl DIAGRAM)
r------___- _____- - - - - - - - - '
-=
I
. _ BOT PHOTO tELL-tl ..
I
U-1
LOAD POINT
21 -19
LOAD INDICATOR 0
SCHEM.OPERATOR CONTROL
PANEL
SHOWN IN DEENEAGIZED I
POSITION
(rcr~~~~E~~(~M)
: ___________ _
L-
I
BOT EaT H
JI
(MOTION FUN:TIONAL DIAGRAM)
80T+[OT
BOT EaT H
EOT PHOTO CELL H
LOAD FUNCTIONAL D~~GRAM)
FAST A OMS
(IiCTION FUNCTIONAl)
--..--ICATOR
. (SCHEN OPE R~ TOR CONTROL PANEL)
FAST R ONS REV
----=--I
. DIAGRAM
47
ATTENTiON INDICATOR 0
lSCHEN OPER~TOR CONTROL PANEL)
25
32U-7
- - - - -.. UHITSELECT OFF
4
F/N4N
A READY
I PEUY & INTERLOCK \
..
\FUNCTIONAL DIAGRAMJ
MOTION
FUNCTIONAL
DIAGRAM
5
27U-7
UNIT
SElECT OfFS
ATTENTION CONTROLLER
FILE PROTECT
14
MANUAL ENABLE
(MOTION FUNCTIONAL DIAGRAM)
CLKGS
AUTO INDICATOR
41
ROFS
36 (SCHEN OPERATOR CONTROL E NEL
27U-4O
(IIOTI>N FUNCTIONAl DIAGRAM)
12
46
15
START CONTR.
, RESET
ROFS
r-- --- - -"'M- - -- - - -, (LOAD
' .
I
I
5
I
-=-
32lJ.4)
1_
A- :o--..._w.....--'
I
:\_LAYI. INTERLOCK FUNCTlONAL) I
I
---IL...-_ _ _ _~
DIAGRAM
K2 READY RELAY
I
I SHOWN
IN DEENERGIZED P05ITION
L ______________ -'I
15
OPERATIONAL CONTR
OIKANI)
+4
I fR£EL SERVO FlH:TlOMl
I DIAGRAM)
27 12
, t4
_
I
16
LOAD OFF
FUNCTI01W.
os
.-----~ UNJT SELECT COMMON
READY 8
21U-1I
RESETS
r----------l
I RESET PUSHBUTTON I
I
-L
I
I
~
~-'---O-----C>--"'=t
I
Z7U-17
-=
I (SCHEM OPERATOR)
I
I
CONTAOL PANEL
I
L~~I~~~~l!°NAL)
24
RESETS
(MOTION FUNCTIONAL)
DIAGA~
Figure 3-22. Station Status, Functional Diagram
L _ _ _ _ _ _ _ ...J
-NOTE: REFERENCE
50S
DWG: 135509-1 B
901013A.322
3-35/3-36
"'" A
6.,1cr
r)
~ of" V.e :r---......
FC06S-L--_ _
FCOI S,-",--_~
FC04S~r---.....
OSCTOO6SS
FC03S "
SFS3S
GNDt
NFS1S----_-"'4
GND22S
M
03SS
FSIS
07SS
RVSS
FF
FS3S
8S
CFS3S
FS2S---~+_--="1
FS3S
E
E
-45SS
CLFS
OPERA1I0NAl
CONTROL
FS3S,-.,.-+-+----="'-_-'
NFS25--I-+-+--......::=r----..,
NFSIS
CFSIS
NFS3S--.__I-I-....lit--03SS
NFS3S
OSC15
025S
CLFS
""),IICz..--.. OSCTS
NFS2
065
NFS3S
POST RECORD DELAY
06SS
NfCTS
NF51S~8S
NFS2S
18S
B
01SS
075
F53S
07SS
NlYSS
ENDS
clIes
,
Figure 3-24. State Counter, Logic Diagram
TRVS
901013A.323
3-39/3-40
SDS 901013
STATE COUNTER FUNCTION DURING REWIND OPERATION. When an on-line rewind without interrupt is desired,
lines WN1C and WN2C come true from the controller to the
stati on. Th i s causes the WN 1Sand WN2S line rece i ver
output terms to be true and the inverted NWN 1Sand
NWN2S terms to be false. Term WN1S is AND-gated with
OSCTS on the set input to the FS1 S flip-flop in the state
counter. OSCTS is also applied as a clock enable to the
FS1S flip-flop. OSTS comes true in the selected station.
Therefore, the FS1S flip-flop is set to on-line without
interrupt operation. The FS2S and FS3S flip-flops remain
reset. This state counter configuration places the station
in state 4. The station will remain in state 4 until the completion of the rewind because the 45SS NBOTS latch gate
on FS1S holds FS1S set until the BOT marker is detected, at
which time the set input is disabled and the 45SS ClKS
input clocks FS1S to the reset state. The 45SS enable is
true instate 4 or state 5.
When an on-line rewind with interrupt is to be initiated,
the WN1C line is true and the WN2C line is false from the
controller to the station. This causes term WNl S and inverted term NWN2S to be true and the WN2S and inverted
NWN1S terms to be false in the station logic. Term
NWN2S is AND-gated with OSCTS on the set input to the
FS 1S fI ip-flop in the state counter. OSCTS is also appl ied
as a clock enable to the FS1S flip-flop. OSCTS comes true
in the selected station. Therefore, the FS1S flip-flop is set
to on-line rewind with interrupt operation.
Terms WN1 Sand NWN2S are AND-gated with OSCTS to
produce, through a network of gates, an SFS3S input to the
set side of flip-flop FS3S in the state counter:
Paragraphs 3-28 to 3-29
The DSCS enable is the output of the device select call
circuitry. This circuitry compares the station number (0
through 7) determined by the unit select switch on the control panel with the DVXR, unit number, and line from the
controller. No two units on a given controller wi II have
the same unit select switch setti ng; therefore, only one unit
responds to the particular DVXR I ine. The true DVXR line
is determined from a command issued by the CPU. The DSSS
enable is true from the controller to all connected stations.
It indicates than an operation is to be performed, e.g., read,
or write. The DRDS enable is the output of the device
ready circuitry in the station logic (see figure 3-25):
DRDS
The operational control enable originates in the transport
logic station. It is true if the station is not involved in a
rewind, tape load, or reset operation and if the ready relay
in the transport control circuitry is energized. The ready
relay is energized if proper voltages are present and all the
interlocks are closed. Enable NFCTS is true if the connect
flip-flop is reset. This enable essentially indicates that the
station is not already selected for a previous operation.
Enable NFS 1S is true except when the FS 1S fl ip-flop is set
during a forward prerecord delay, reverse postrecord delay,
space, rewind, read, or write operation.
There are latch gates on both DSGS and DRDS terms. The
latch gate in both cases is enabled by a signal from the
controller. With all the above conditions true, the DSGS
station selected term comes true, enabling the set input to
FCTS, and the term is transmitted to the controller:
C/FCTS
s/FS3s
3-28 Station Selection
Station selection is performed during on-line operations.
To select a station for a particular operation, the FCTS
connect fl ip-flop must be set:
DSGS NFCTS
The DSGS enable is the output of the device selection gate
(see figure 3-25):
DSGS
DSlS
SFS3S FCTS
The FCTS enable is true because the FCTS flip-flop is set in
the station selected for the rewind operation. The state 0
OSCTS enable, which is true in the selected station, is
AND-gated with the master clock from the controller, ClKS,
to provide a clock input that sets fl ip-f1op FS3S. The FS2S
flip-flop remains reset. Therefore, an on-line rewind with
interrupt operati on causes the state counter to be set to an
FS1S set, FS2S reset, and FS3S set configuration. This state
counter confi guration places the station in state 5, where
the rewind operation is initiated. When the BOT marker is
detected, the 45SS NBOTS latch gate on FS1S is disabled,
and the 45SS clock input causes FS 1S to reset. At th is time,
FS3S is sti II set and the station enters state 1.
s/FCTS
Operational control NFCTS NFSl S
DSC S DSSS DRDS
The device select line, DSlS, comes true from the controller
after the controller responds to the selected signal, DSGS,
from the tape station. Therefore, if all the above conditions
are met, the FCT select flip-flop will set. The FCTS flipflop remains set unti I the completion of the operati on,
except in the case of a rewind. The resetting of FCTS is
known as station deselection.
3-29 Station Deselection
A station remai ns selected unti I the completion of the operation being performed, except in the case of a rewind
operation. To deselect a station at the termination of an
operation, the FCTS connect flip-flop must be reset:
C/FCTS
ENDS ClKS
The ENDS enable comes true from the controller after the
completion of the operation being performed. This is true
for either successful or unsuccessful terminations. Enable
ClKS is the output of the free-running master clock circuitry in the controller:
s/FCTS
DSGS NFCTS
3-41
SDS 901013
Paragraph 3-30
DEVICE SELECTION GATE
DSCS
DSSS
DRDS
~--~
DSGS
DST
DEVICE READY
OPERATIONAL CONTROL
NFCTS
NFS1S
~~----------~----~. DRDS
NTSHS
NDRDS
901013A. 327
Figure 3-25. Device Selection and Device Ready, logic Diagram
Enable NFCTS, on the set input, is false because the FCTS
fl i p-flop was set at the start of the operati on. Therefore,
the FCTS flip-flop is reset when ENDS comes true from the
controller, thereby causing the station to be deselected.
A station remains selected until the termination of any
operation other than a rewind. In the case of a rewi nd
operation, this is not necessary, so the FCTS connect flipflop is reset at the start of the rewind operation:
prevents any data line interference from the rewinding station with another station that may be selected by the
controller during rewind time. Therefore, in a rewind operation, the station is selected for only the short period of
time that the FCTS flip-flop is set. During this time, the
rewind logic is triggered, and the controller assumes that
fast reverse tape motion has been initiated. The controller
can therefore service other units duri ng rewi nd time.
3-30 Rewind Operation
C/FCTS
OSCT WNS ClKS
OSCT WNS
OSCTS WNI02S
The ClKS enable is produced by the free-running master
clock in the controller. Term NWN1S, NWN2S, or both
are false from the controller, making the WNI02S enable
true when a rewind operation is to take place. The OSCTS
enable is true in the selected station. Therefore, term
OSCTWNS comes true, producing a clock input to the FCTS
flip-flop. When the FCTS flip-flop was set during station
selection, the NFCTS enable to the FCTS set input went
false. At OSCTWNS clock time, therefore, the set input is
disabled and FCTS is reset. This ensures that the FCTS
enable to the read amp cable drivers is removed. This
3-42
The th ree types of rew i nd operati on that may be performed
on the tape station are these:
a.
Rewind on-line without interrupt
b.
Rewind on-line with interrupt
c.
Rewind off-line
REWIND ON-LINE WITHOUT INTERRUPT. The state
counter is set to an FS 1 S set, FS2S reset, and FS3S reset,
state 4 configuration for an on-line rewind without interrupt
operation. FSl S is AND-gated with NFS2S to produce term
SDS 901013
45SS, which, in turn, is applied as an input to the gate that
produces rewind signal REWS. The FS1 S flip-flop is set
(FS1 S) and the FS2S flip-flop is reset (NFS2S) only when
the station is to perform a rewind:
REWS
NBOTS 45SS
Enable NBOTS is true if the BOT marker is not being detected by the photosense head. This enable ensures that a
rewind cannot be initiated if there is no more tape to wind.
When the REWS signal comes true, it is applied as an enable
to the fast tape motion circuitry.
backup time. To leave state 1, the FS3S fl ip-flop must be
reset:
C/FS3S
CFS3S
CFS3S
01 SS OPERATIONAL CONTROL ClKS
The 01 SS enable is true in state 1. The operational control
enable, however, is inhibited for approximately 800 ms
after the detection of the BOT marker:
OPERA 1I0NAl CONTROL
= lOAD OFF
RESET OS
READY B
Term REWS is input to a two-term AND gate that produces
term FASTRONS:
FASTRONS
REWIND
COMPLETED
REWS DIRECTION ONS
The DIRECTION ONS enable is true as a result of the capstan REVS (reverse) line being true. Term REVS comes true
in state 4 when the active motor signal ACMS is ANDgated with the true reverse line from the controller. When
the FASTRONS term comes true, the fast tape speed circuitry is enabled. When REVS comes true in state 4 along
wi th the activate motor si gnal (ACMS), reverse power is
appl ied to the capstan motor to produce reverse motion.
REWIND ON-LINE WITH INTERRUPT. The FS1 S flip-flop
is set, FS2S is reset, and FS3S is set immediately after
station selection during a rewind on-line with interrupt.
This places the station in state 5. In state 5 the activate
motor signal, ACMS is AND-gated with the reverse signal
from the controller to initiate reverse tape motion. The fast
circuitry is also energized so that the tape moves at 250 ips.
This action is initiated in the same manner as for the rewind
without interrupt operation. Figure 3-26 shows a block
diagram of the rewind on-line with interrupt operations.
REWIND COMPLETED
BRC
BRC
0.8 sec O/S (timed
out) + FAST ON REV
The above equation indicates that if the 0.8 sec one-shot is
triggered, the operational control is false. The 0.8 sec oneshot is triggered by the trailing edge of the term FAST R
ONS, which occurs when BOT is detected. Therefore, the
FS3S fl ip-flop cannot be reset and the station cannot leave
state 1 for 800 ms. Thi s is enough time for tape backup to
take place.
Interrupt to Controller. When the FS3S flip-flop resets, an
NFS3S enabie is provided to an AND gate in the INTDS
interrupt latch circuitry:
INTDS
INTS
INTS
(Inverter) NINTS
NINTS
The difference between the two on-line rewinds is that with
interrupt, the lOP wants to know when the rewind has been
completed so that it may service the station. In this case,
the station must transmit an interrupt signal to the controller
at the completion of the rewind operation. This is accomplished as follows: the FS1 S flip-flop in the state counter
has been set whi Ie t~pe is rewi nding in state 5:
S/FS1S
SFS1S
SFS1S
(Inverter) NF S3S I NGS B
+ (NGNTS NTSHS START CONTR)
The interrupt gating enable, INGS, comes true in state 1
every 16 f-IS because of the 0155 ClK input gate. Enable
NTSHS is true from the processor if the controller is not
currently responding to an SIO, TIO, or HIO instruction.
NGNTS is true if the controller is not currently requesting
device addresses from interrupting stations. The START
CONTR enable is true if the station is on-line •
. 45SS NBOTS
The 4555 enable is true in state 5. The NBOTS enable is
true unti I the BOT marker is detected, at which time NBOTS
goes false, disabling the set input on FS1S. Term 4555 provides a clock input to FS1 5, and it resets, dropping motor
power (NACMS). This action leaves only FS3S set, which
causes the stati on to enter state 1.
The purpose of entering state 1 is to prevent an interrupt
signal from being transmitted to the controller during
The same clock that resets the FS3S flip-flop to exit state 1
provides an INGS input to the interrupt circuitry. Term
INGS is latched as long as LINGS is true. When OPERATIONAL CONTR or NRSTS goes false or the DSCS AIOCDS
gate is enabled, the INGS interrupt gate goes false. If the
NGNTS, NTSHS, and START CONTR terms are true at this
time, an INTDS interrupt signal is transmitted to the controller. This interrupt signal is latched by an INTS INGS
gate. The interrupt si gnal is transferred through the controller to the processor.
3-43
SDS 901013
SELECT SIGNALS
FROM CONTROLLER
STATION SELECTED
FC TS
N FS1S
NF S2S
NF S3S
STATION
STATE 0
t
ONLINE REWIND
WITH INTERRUPT
NF CTS
FS 1S
NF S2S
FS3 S
{
1. INITIALIZE DELAY COUNTER
2. RESET SELECT FLIP-FLOP (FCTS)
TO ENTER STATE 5
~
STATION
STATE 5
~
,.
ALLOW FOR TAPE BAC KUP
BEFORE SENDING INTERRUPT
NF CTS
NF SlS
NF S2S
FS 3S
1. INITIATE CAPSTAN REVERSE MOTION
2. LATCH IN STATE 5 UNTIL BOT DETECTED
3. WHEN'~Qt DETECTED, ,TRIGGER 0.8 \
SEC ONE-SHOT FOR OPERATIONAL
CONTROLINHIBIT4. RESET FS1S TO ENTER STATE 1
~
1. WAIT FOR 0.8 SEC ONE -SHOT TO
TIME OUT. (DURING THIS TIME
TAPE IS BACKED UP.)
2. AFTER DELAY ONE-SHOT TIMES OUT,
OPERATIONAL CONTROL COMES TRUE
3. RESET FS3S TO ENTER REST CONDITION
4. TRANSMIT INTERRUPT TO CONTROLLER
STATION
STATE 1
800 MS
~
••
NFCTS
NF SlS
NF S2S
NF S3S
,.
STATION
REST
'"
1. CONTROLLER RECOGNIZES INTERRUPT
AND ISSUES AIO
2. STATION RECOGNIZES AIO AND TURNS
ON STATION ADDRESS LINE
3. CONTROLLER STORES ADDRESS
AND TERMINATES AIO
4. WHEN AIO TERMINATES, STATION
TURNS OFF INTERRUPT
901084A.314.
Figure 3-26. Rewind On-Line With Interrupt, Block Diagram
3-44
Paragraph 3-31
SDS 901013
Interrupting Unit Number to Controller. After interrupt line
acknowledgement, the processor issues an acknowledge
interrupt instruction (AIO), causing the GNTS line to come
true from the controller to the station. Term GNTS is
applied as an enable to device-number-to-address-line
gating circuitry in all the stations connected to the particular controller. The station address lines to the controller
are desi gnated DVODS through DV7DS. For the purpose of
explanation, it is assumed that station 0 is the interrupting
station:
DYODS
GNTS UNIT SELECT SWOC INTS
GNTS is true from the controller. The UNIT SELECT SWOC
enable is true from the unit select switch on the operator
control panel in the unit that has been allotted number o.
Enable INTS is true if the rewind on-line with interrupt
operation has been completed. The DYODS address line,
therefore, comes high to the controller. This line informs
the controller that station 0 is interrupting. During the
acknowledge interrupt instruction, the AIOCDS I ine comes
true from the controller. This causes the AIOCDS DSCS
gate to be enabled, which removes the interrupt latch,
thereby dropping the interrupt line from the station. It
should be noted that more than one station may have the
interrupt line high at any given moment. In this case, more
than one of the address lines comes high when the AIO
instruction is generated. The station interrupt from the
lowest station address is recognized by the controller. The
controller recognizes the highest priority address line, with
station 0 having the highest priority and station 7 the lowest
pri ority.
is initiated, and the following occurs: with the erase flipflop set in the controller, the erase term, RASC, is true
from the controller, which causes RASS to be true in the
station. Term RASS is applied as an input to the tape erase,
ERSS, circuitry:
ERSS
NERSS
NERSS
RASOBOTS DSCTS + ERSS FCTS
Enable RASOBTS is true if the erase flip-flop is set in the
controller. Enable OSCTS comes true when the station
enters state 0 after being se lected by the write order following the erase order. When ERSS comes true, it is latched
by a gate with input enables FCTS and ERSS. The FCTS
connect flip-flop is set throughout the write operation.
The following describes the difference between the erase
before write and the normal write operation. The essential
difference is in the starting delay time (state 6). The station exit from state 6 to state 7 ina write operation takes
place in 6.5 ms. In the erase before write operation, the
exi t from state 6 to state 7 does not take p lace for 51.3 ms.
To exit from state 6 to state 7, the FS3S fl ip-flop must be
set:
FS3S
SFS3S FCTS
FCTS
True in selected station
SFS3S
0655 (state 6) ERSS (erase) TERS
TERS
FC04S FC03S NFC02S FC01S
b.
The station remains in state O.
c.
The station is placed in the manual mode.
The delay counter that began counting when the station
entered state 6 does not reach a FC04S, FC03S, NFC02S,
and FCD1 5 configuration for 51.3 ms. Therefore, the FS3S
fl ip-flop is not set, and the station does not exit state 6
until 51.3 ms have elapsed. Throughout this 51.3 ms period,
the write enable term, WENS, is true, which causes erase
head current to flow, and results in 3.5 inches of tape being
erased. Write head current also flows at this time, which
erases the portion of tape between the write and erase
heads.
This order gives the programmer the abi I ity to rewi nd a unit
and place it in the manual mode. It could be used to protect a tape upon which information had just been written.
LOAD POINT (BOT), AUTOMATIC ERASE. The ERSS tape
erase circuitry is also enabled by LOAD POINT CONTR,
which is true with the tape positioned at load point:
REWIND OFF-LINE. The rewind off-line order from the
lOP causes the followi ng to occur:
a. Term ROFS comes true, to store the rewind order
in the station transport reverse and rewind flip-flops.
3-31
Erase Operation
A programmed erase operation takes place when a portion
of tape must be erased before new data can be written onto
tape. An erase operation also takes place automatically
when tape is in the load point (BOT) position and a write
operation is initiated. In this case, approximately 3-1/2
inches is erased.
PROGRAMMED ERASE BEFORE WRITE. If an erase order is
issued by the processor, the erase flip-flop is set in the
controller. If this order is immediately followed by a write
or write tape mark order, the station is selected, tape motion
ERSS
NERSS
NERSS
RASOBOTS OSCTS
Enable RASOBOTS is true if the tape is positioned at load
point. Enable OSCTS comes true when a station enters
state 0 after being selected. When ERSS comes true, it is
latched by the ERSS and FC TS gate. When the station
enters state 6 on a write operation with the tape at load
point, it does not exit to state 7 for 51.3 ms, 3-1/2 inches
of tape is erased, and a gap of 0.94 inches of erased tape
is left between the BOT marker and the first data character.
3-45
Paragraphs 3-32 to 3-33
SDS 901013
motion operations. Figure 3-27 shows a block diagram of
the magnetic tape controller.
3-32 Spacing Operation
The space record and space file operations are identical in
all respects to a read operation at the station. In either
case, the data read from tape to the controller is not transferred to the lOP. This transfer inhibit is a function of the
space order.
The mai n functions of the controller are to send and receive
data from the CPU through the lOP, and to control the tape
motions by directing appropriate orders to the stations.
These functions are carried out in eight conceptual states
as determined by the state counter. Figure 3-28 shows a
block diagram of the controller states.
3-33 CONTROLLER
The controller portion of the magnetic tape system consists
entirely of the modules contained in chassis V, W, Y, and
Z (see figure 1-2). Chassis V and W enclose the modules
which contain circuitry for handling the system's data transfer operations. Chassis Y and Z enclose the modules which
contain circuitry for controlling the system's interface and
The magnetic tape controller can be functionally divided
into three main circuit units: interface, motion, and data.
The interface operation, communication and service cyc les,
and controller states are described in paragraphs 3-34
through 3-56. The data handling circuits are described
under the heading Magnetic Tape System Functions (paragraphs 3-57 through 3-70).
CONTROLLER
~--~~
.---- STATION
I
------------~
.....,.--I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _M_O_T_IO_N_ _ _- r -_ _ _ _ _ _ _ _ _ _ _--"TI.CONTROLLER
STATUS
STATION
STATUS
L ______ _
'---------------------------------~ORDERS
lOP
-,
I
I
I
SUBCONTROLLER
PEAK DETECTOR
AND
DESKEW
8-BYTE
MEMORY
STATION
DATA
BUFFER
REGISTER
WRITE DRIVERS
CONTROLLER
DATA
I
I
L
901013A.325
Figure 3-27. Magnetic Tape Controller, Block Diagram
3-46
Paragraph 3-34
SDS 901013
OlF
OOU
ORDER
INPUT
+
OOF
OOU
IDLE OR
READY
---+
O1F
OlU
ORDER
OUTPUT
r---+
OlF
02U
DEVICE
SELECT
r---+
OlF
03U
WAIT FOR
DPR
~
03F
03U-02U
DATA
TRANSFER
r---+
03F
03F
OlU
OOU
r------+
STATION
ORDER
FINALIZATION
FINALIZATION
9Ol013A.326
Figure 3-28. Magnetic Tape Controller States, Simplified Block Diagram
3-34 INTERFACE
The lOP-controller interface permits all device controllers
to operate simultaneously by time-sharing interface signals
wi th the lOP. The interface functi on for the magnetic
tape controller is handled by a group of modules located in
chassis Y. These modules constitute an assembly which is
part of each Sigma peripheral controller and is called a
device subcontroller (DS). Figure 3-29 shows a block diagram of the subcontroller with the main signals identified.
To carry out its interface function, the subcontroller contains the following logic circuits and components:
a. Cable drivers and receivers that link the eight-bit
data path i nte rface from the lOP
b. Logic circuitry to determine priority during ASC
and AIO operations
c. Eight address determining switches and logic
circuits, which determine and compare the controller number for lOP detection during 510, HIO, TIO, and TDV
operations
d. Service connect flip-flop (SCF) and associated
logic circuitry, to indicate that the controller is connected
for service
e. Relay logic, under remote control, for connection or removal of the subcontroller during system on/off
operations
The subcontroller modules, their associated cables and
connector locations, as well as module descriptions are
given in table 3-4.
Table 3-4. Subcontroller Connector/Cable/Module Identification
Connector
Location
Module
Type
Cable Designation
Module Description
23
LT25
Special logic module. Contains service call latch circuits, data line
(received) inverters, a toggle switch (to indicate on-line or off-line),
and other subcontroller functions
24
LT26
Special logic module. Contains 8 toggle switches for device controller
address selection and two 4-bit comparators to compare selected address
with lOP output address during 510, HIO, and TDV instructions
Reserved: A Tl7 takes two slots
25
26
ATl7
27
LT24
28
ATlO
29
AT41
30
All 1
31
LT43
32
ATl2
J4
Cable driver-receiver and power on-off relay to which the input and
output priority determination cable connectsJoccupies two module
positions)
Special logic module. Contains function response line buffers with 3way OR gates and other subcontroller circuits
J3
Cable receiver to which one cable from the lOP connects
Special logic module. Contains some priority determination logic,
service-connect flip-flop (FSC), TSH, and TTSH
J2
Cable driver-receiver to which one cable from the lOP connects
Special logic module. Contains some priority determination logic and
various subcontroller circuits
J1
Cable driver to which one cable from the lOP connects
3-47
SDS 901013
•
[SIOR, HIOR, TIOR, TDVR ]
. .. DAOR-DA7R DAPR
...
FSR, RSAR, RSTR, ESR, EDR
~
TO CIRCUITS IN THE
SUBCONTROLLER
....
DAO-DA7
...
ED
....
...
T
....
DAOR-DA7R
TOANO
FROM I/o
[ DAOD-DA7D, DAPD,
]
RSD, EDD, lORD, DORD ...
III
DCA
ADDRESS SELECTION
AND RECOGNITION
...
~
FRO-FR7, IC, SC, RS, FSL
~
SWAO-SWA7
ES, RSA, FS, RST
r
...
FUNCTION INDICATORS
~
FROD-FR7D
....
STATUS LOGIC
TDVR
TOANO FROM{
AVI, AVO, HPI, HPS
OTHER DEVICE ....
CONTROLLERS
CABLE
RECEIVERS/
DRIVERS
T
HIOR, SIOR,
TIOR, TOVR
.
....
...
~
...
......
FUNCTION lOGIC
r-
TSH STATUS
TOV STATUS
FSD
~
TTSH
TOANO
FROM
DEVICE
CONTROLLER
I
"""-
SCD
~
....
ICD
ASCR
AIOR
HPIR
HPSR
FSlD
~
INI
...
...
~
...
~
SERVICE/INTERRUPT
PRIORITY lOGIC
.
~
......
•
INC
CSl
CIl
FSC
AIOC
INI
INC
~
...
.
RELAY lOGIC
~ CONNECT/DiSCONNECT
PT1aS
....
.....
901063A. 51
Figure 3-29. Subcontroller, Simpl ified Functional Block Diagram
3-48
SOS 901013
3 -35 Data Path
The lOP provides three connectors and cables for transmission of all signals to and from the controller. These
cables are routed to each peripheral device, in a bus
fashion, by means of the shortest path. An additional pri0rity cable interconnects the controllers to the lOP in a
trunktail fashion, with the first controller in the chain
having priority during service and interrupt calls. Figure
3-30 shows a typical data path interconnection diagram.
The cables consist of 14 shielded wires with a characteristic
impedance of 33 ohms. There are c·able driver and cable
receiver circuits connected to each cable. The cable
drivers consist of emitter followers presenting 16.5 ohms
output impedance for a logic one and high impedance for
3-36 lOP-Controller Signals
The signal exchange between the lOP and the controller is
carried via cable receiver module ATlO (Y28), cable
driver and receiver module ATl1 (Y30), and cable driver
module A Tl2 (Y32). The interface si gnal I ines interconnecting the lOP and controller are shown and identified in
figure 3-31. The status for the response and data lines is
given in table 3-5, where the corresponding system functions are described and identified.
DEVICE CONTROLLER
NO.2
PRIORITY
NO.4
PRIORITY
rX
DEVICE CONTROLLER
NO.5
PRIORITY
SUBCONTROLLER
WXX l ===3 I
nJ1 nJ2 nJ3 nJ4
nJ1 nJ2nJ3nJ4
~J
~ l~)
I
•
SUBCONTROLLER
IlJ1 nJ2 IlJ3 nJ4
lOP
a logic zero. The cable receivers are amplifiers with an
input discrimination level of approximately +1 volt. The
signal levels are +2 volts for a logic one and zero volts
for a logic zero.
DEVICE CONTROLLER
SUBCONTROLLER
D<
D<
D<
Paragraphs 3-35 to 3-36
I
I I
I
I
I
l~)
LrJ
---
~
~
1.;1
~
I
I
~ ~
n
I I
r~1
I
h M ()
LJJ1 LJJ2 LJJ3 LJJ4
---
I
0
f
LJJ1 LJJ2 LJJ3LJJ4
1=~
rh
,
r;l I--')
LJJ1 LJJ2 LJJ3 LJJ4
SUBCONTROLLER
SUBCONTROLLER
SUBCONTROLLER
DEVICE CONTROLLER
DEVICE CONTROLLER
DEVICE CONTROLLER
HIGHEST
PRIORITY
LOWEST
PRIORITY
NO.3
PRIORITY
NOTES: UNLESS OTHERWISE SPECIFIED
CD
o
o
HIGHEST PRIORITY CONTROLLER TERMINATES
THE PRIORITY CABLE WITH SPECIAL TERMINATOR
SDS 128047.
4. ALL CABLE ASSEMBLIES ARE SDS 127314.
5. CABLING BETWEEN CONNECTORS J1, J2, AND
J3 FOLLOWS THE SHORTEST ROUTE
LOWEST PRIORITY CONTROLLER IS CONNECTED
TO THE lOP J4.
(1) DESIGNATES STANDARD TERMINATOR SDS
127315.
6. CABLING BETWEEN J4 CONNECTORS IS ROUTED
IN RESPECT TO PRIORITY; THE CONTROLLER
CLOSEST TO THE lOP HAS LOWEST PRIORITY
900973C.12
Figure 3-30. Typical I/O Interconnections
3-49
HIGHEST PRIORITY
DEVICE CONTROLLER
,.....
I-
-
r-
-
LOWEST PRIORITY
DEVICE CONTROLLER Jl
r-
,-...
SIGNAL DIRECTION
- -
-
'--
II-
-
co
..,c
-
-
-
-
-
CD
'--
I-
I
~
0
"
5"
I
....
..,CD
CO
-
-
-
-
-
CD
-
~
::l
CD
VI
0
c·
co
..,
c
3
..
FSL
(1) FUNCTiON STROBE LEADING ACKNOWLEDGE
(I) INTERRUPT CALL
(2) TWO-BYTE, FOUR-BYTE INTERFACE REQUEST
IC
DX2,DX4
'-'
l-
r-.
I--
--
r-.
...
--
-
-
r
- 1="""~
-1- -1- -
- -- -
L-
-,.....~
--1- L
-
r-
-
--
'-'
--
.....
-
I-
- - - --
-
"
..
CD
---- - -
V
-
-- r -
r~
.....
.....
-
,.....
.....
J6
r-
...
LEGEND
.....
CR CABLE RECEIVER
CD CABLE DRIVER
PC
DOR
(ll
(I)
SC
(I)
(1)
PARITY CHECK
DATA/ORDER REQUEST
SERVICE CALL
SPARE
(I)
RESET VO
1.024 MHZ CLOCK
RST
CLI
ES
RSA
SIO
HIO
TDV
AIO
END SERVICE
REQUEST STROBE ACKNOWLEDGE
START Vo
HALT VO
(I) TEST DEVICE
(1) ACKNOWLEDGE INTERRUPT
ASC
FS
TiO
ZBCI
(I)
(1)
(1)
(I)
ACKNOWLEDGE SERVICE
FUNCTiON STROBE
TEST VO
ZERO-BYTE COUNT INTERRUPT
WADR
(1)
WORD-ALIGNED DATA REQUIRED
SPARE
(1)
(I)
(I)
(I)
(I)
(I)
- - - -
-
---
-
---
AVI
AVI
(1)
(1)
ALWAYS HIGH
ALWAYS HIGH
FAST
AVO
(I)
(1)
FAST DEVICE CONTROLLER
ABORT Vo OPERATION
-
-- --- --------- D80-DB7
(8)
'-'
..
DC4-DC7
(4) DATA LINES, BYTE 2
000-007
(8)
SPARE
(2)
~
DATA LINES, BYTE 3
w
-S~""
I
I
I
I
I
I
_ _ _ _ _ ..J
DATA LINES, BYTE I
(1) ENABLE TWO-BYTE INTERFACE
(4) DATA LINES, BYTE 2
(1) ENABLE FOUR-BYTE INTERFACE
~
o
NOTE 2
EDX2
DCO-DC3
EDX4
r
,-...
.....
'-'--
NOTES:
1. FOR CLARITY, CABLE TERMINATORS ARE NOT SHOWN
2. PRIORITY CABLE IS SHOWN IN DASHED LINE - - -
---
..
.....
EXTRA TWO CABLES
FOR 32-BIT lOP
INTERFACE
-
REQUEST STROBE
INPUT OUTPUT REQUESI
DATA LINES, BYTE 0 ODD PARITY
END DATA
~-
r r
HPS (1) HIGH PRIORITY SERVICE
HPI (1) HIGH PRIORITY INTERRUPT
:=~-V>-~C -:=~-- -- - -
-~
-
:=-J= .....-1
_r- __
(1)
DAO-DA7, DAP (9)
(1)
ED
-
::l
~
..
-
-
(8)
lOP
PURPOSE
FUNCTION RESPONSE LINES
(1)
-
-
~
CO
E:
I-
NO.
WIRES
RS
lOR
'-'
.oL
-
W
-
...
l-
,.....
r-
~
I-
-
~
I-
r-
..
SIGNAL
FRO-FR7
FUNCTION
DATA LINES
FUNCTION RESPONSE LINES
I/O ORDERS
DAO DAl DA2 DA3 DA4 DA5 DA6 DA7
FRO FRl FR2 FR3 FR41FR5 FR61FR7
DOR lOR DAP PCD ED ESR
,
I
¥
DESCRIPTION
J
1
Order (0 =*data)
I
1
Output (0 =*input)
1
0
0
Service
(ASC)
0
1
0
1
1
0
1
0
1
0
End data
0
0
0
1
Write packed
0
1
0
1
Write binary
1
1
0
1
Write BCD
0
0
1
0
Read packed
0
1
1
0
Read binary
1
1
1
0
Read BCD
1
1
Rewind and interrupt
(on-I i ne)
1
Rewind off-line (manual
mode)
0
0
0
D
1
1
1
Order
out
Device
number
1
Rewind (rewinds to load
point on automatic)
Space record (D = 0=*
forward; D = 1 =*
1
backw~rd)
1
0
1
1
1
0
1
1
1
D
0
1
1
1
1
1
1
Space fi Ie (D = 0 =*
forward; D = 1=*
backward)
Set erase (to be used with
next write)
Write tape mark
1
Transm ission error
t
1
1
Order
in
1
Incorrect length
Chaining modifier - not
used in mag tape system
Channel end
1
Unusual end
f
-
,
,
Qi
0-
eD
w
I
~
Vl
C
00
Vl
0
VI
...
~
2.,CD
w
0
::J
.,
::J
.,CD
~
c
0
CD
0
DATA LINES
FUNCTION
I/o ORDERS
FUNCTION RESPONSE LINES
DAO DAl DA2 DA3 DA4 DA5 DA6 DA7
FRO FRl FR2 FR3 FR4 FR5 FR6 FR7
~
,•
1
DOR lOR DAP PCD ED ESR
I
Interrupt
1
Count done
1
1
1
1
Service
(ASC)
Command chain
lOP error halt
Order
out
(termini ate)
Device
number
Disregard last byte or error
- not used in mag tape
system
1
j
~
DESCRIPTION
•
J
,
I
,
J
W
/10
1
t
,
Data parity
Check parity
1
1
End of service
-f
C
0(I)
(,.)
Interrupt pending
~
Vl
C
0
0
Device ready
0
1
Device not operational
1
0
Device unavai lable - not
used in mag tape system
0-
1
1
Device busy
1
Automatic mode
1
SIO
TIO
Device
number
DCA
HIO
Unusual end
0
0
Device controller ready
0
1
Device controller not
operational - not used in
mag tape system
1
0
Device controller unavailable - not used in mag
tape system
1
1
Device controller busy
1
Address recognition
{ SIO successful
1
,
,
ill
,
,
•
/10
:.
,
S stem
y
ready:
HIO when device
not busy
TIO when SIO
can be accepted
n
0
::J
....
0
.,m-
....
::J
.,(I)
cr
n
(I)
n0
t
Vl
0
Vl
-0
e
e
(,.)
DAO DAl DA2 DA3 DA4 DA5 DA6 DA7
,
•
"
I
.
I/O ORDERS
FUNCTION RESPONSE LINES
DATA LINES
FUNCTION
•
DOR lOR DAP PCD ED ESR
FRO FRl FR2 FR3 FR4 FR5 FR6 FR7
I
,
1
Rate error
',>
Address recognition
1
1
Device
number
DCA
End of file
j
,
-.
~
1
,
oIto
Load point
1
End of tape
1
,
I
Write protect violation
1
1
,
Abnormal condition does not
exist (device operational)
Write permitted
1
TDV
DESCRIPTION
Rewind on-line
1
,
y
~
J
Device end
No unusual end condition
detected
Write protect violation
End of file
1
Rate error
1
Q:
(I)
w
~
Vl
C
c-
o
0
AIO recognition
1
1
1
~
.,a
£.
~
S'"
.....
.,
(I)
0'
0
(I)
n
0
;:,
2:.
AIO
,
Device
number
Vl
0
Vl
-0
0
0
w
SDS 901013
Paragraph 3-37
ATll (32Z), cable driver module ATl2 (26Z), and cable
receiver module AT10 (28Z).
3-37 Controller-Station Signals
The controller has two sets of connectors for attachment to
the stations. One of these connects the controller to the
station electronics located in the controller cabinet. The
other set of connectors is used to connect the adjacent
stations, each of the stations being the beginning of a trunktail connection that extends to the last station of the system.
Control and status lines are connected between the station
and the transport. The status lines indicate the current
condition of the transport. The control lines determine the
transport mode of operation (see table 3-6).
Table 3-7 shows the interface signals between the controller
and the station, and between the station and the transport.
Refer to the glossary, at the end of the section, for a
description of terms.
The signals between the controller and the station are
carried by cables connected to modules contained in chassis
Z. These modules are cable driver and receiver module A
Table 3-6. Transport Modes
MODE OF OPERATION
CONTROL TERM
Forward
Reverse
Rewind
REVS
0
1
1
0
ACMS
1
1
1
0
REWS
0
0
1
0
ROFS
0
0
0
1
Rewind Off-Line
Table 3-7. Magnetic Tape System Interface Signals
Transport
Station
------
Device ready indicator
Devi ce busy i ndi cator
---
Attention indicator
Reverse/forward
----
Actuate Moto r
Rewind/off-line
Fast/normal
Unit select switch OC
•
lC
2C
3C
4C
5C
•
6C
Unit select switch 7C
ATTENTION CONTR
START CONTR
-----------------
---
---
OPERA TIONAl CONTR---
--
Station
DRDS
RVRS
DBSS
WNl
ATNS
WN2
REVS
WRT
ACMS
RASS
ROFS
DSS
REWS
DST
UNIT SELECT SW OC
DSL
~
lC
END
2C
DVOD
3C
4C
5C
6C
INPS
DRDS
------
REV
WNl
WN2
----
WRT
----
DSl
~
-----
---------
UNIT SELECT SW 7C
DBSS
ATTENTION CONTR
AUTS
START CONTR
ARGS
OPERA lIONAl CONTR
WPMS - - -
(Continued)
3-54
DV7D
Controller
---
FRS
DSS
DST
END
DVOR
DV7R
INPS
DRDS
DBSS
AUTS
ARGS
WPMS
SDS 901013
Paragraph 3-38
Table 3-7. Magnetic Tape System Interface Signals (Cont.)
FILE PROTECT
EOT CONTR
Station
Station
Transport
--
----
BTSS
FILE PROTECT
ENTS
EOT CONTR
LOAD POINT CONTR -
LOAD POINT CONTR
LSPS
LSPS
HSPS
25VWP1
25VWP2
POWER FAILURE IN*
-----------
--
*
POWER FAILURE OUT ----
LSPS
LSPS
INTS
25VWP2
POWER FAILURE IN
*
POWER FAILURE OUT*
ENTS
WNDS
BOTS
25VWP1
BTSS ..,
WNDS _ _
HSPS
HSPS
-----
Controller
DSGS
DPRS
DVOR
---------
HSPS
BOTS
INTS
DSGS
DPRS
---DVOD
DV7R
___ DV7D
GNT
-GNT
RST
---RST
ATO, HlTD
_ATO, HlTD
AIOCD
-AIOCD
NTSH
~NTSH
ClK
---- ClK
*Utilized only if the station and the controller occupy a common cabinet
3-38 Interface Disconnect
The device subcontroller contains circuits for connecting and
disconnecting the device controller from the lOP interface
in a transient-free manner when power is applied or removed
from the device controller. Although the subcontroller
provides the proper connect and disconnect sequencing, the
controller actually provides the signal to initiate the operation. Figure 3-32 shows a timing diagram for the connect/
disconnect operation.
DISCONNECT OPERATION. The DS is disconnected from
the lOP interface whenever the ON-OFF switch located on
the LT25 module is positioned to OFF, or the controller removes the ground source from the connect/disconnect circuits. The ON-OFF switch on the OS is connected in series
with the ground source to the connect/disconnect circuits.
When the ground source to these circuits is removed, the
following sequence occurs:
a. Approximate Iy 1.6 mi lIiseconds after the ground
source is removed, all service and interrupt calls to the lOP
are inhibited. (Refer to figure 3-30.) This is accomplished
by grounding the INC term and letting NINC go true
through relay and transistor logic.
b. Approximately 4.2 milliseconds after INC is
grounded, the term INI is grounded through a set of relay
contacts. AVI also becomes shorted to AVO through a second set of relay contacts at this time. The timing of the two
sets of contacts can vary by as much as 250 microseconds.
c. Approximately 0.5 mi Iii seconds after INI is grounded, NINI is allowed to go true. When INI is grounded, the
subcontroller is considered disconnected from the lOP interface, since INI grounds all input to the subcontroller cable
drivers. AVI is short circuited to AVO, so that the DS is
still physically connected to the priority cable of the lOP
interface without interfering in the operation of the priority
cable.
CONNECT OPERATION. When the device subcontroller
is to be connected to the lOP interface, the ON/OFF
switch on the OS must be positioned to ON and a ground
source must be applied to the connect/disconnect circuits.
The ground source to the circuits should be applied after all
voltages have reached the specified operating level. When
the ground source is appli~d to the connect/disconnect
circuits, the following sequence occurs:
a. Approximate Iy 4.5 mi IIi seconds after the ground
source is applied, a set of relay contacts is closed and term
NINI is grounded. (Refer to fi gure 3-30.)
3-55
SDS 901013
Paragraphs 3-39 to 3-40
b. Approximately 0.5 milliseconds later, term INI is
allowed to go true. The short circuit between AVI and
AVO is removed at this time.
function is given as an illustration (see figure 3-33). The
controller internal operations during these communication
cycles are described in the Controller States portion of
this section, paragraphs 3-48 through 3-56.
c. Approximately 120 microseconds after INI goes
true, term INC goes true and term NINe is grounded.
When INI and INC have reached the true state, the controller is connected to the lOP interface, and the service
call, interrupt call, and cable driver lines become active.
3-40 Start Input/Output (SIO)
To initiate data transfer with the magnetic tape system, the
CPU executes an SIO instruction. The lOP then receives a
command word that contains a controller address, a device
address, and a memory location that defines the starting
point for the list of commands to be carried out. The lOP
then raises the SIO function line that goes to the controllers.
After priority determination and se lection, the magnetic
tape controller responds accordi ng to the current conditions
in the magnetic tape system (see paragraph 2-19). This
response is associated to the previous operation performed
by the controller, and it is undefined if the SIO is the first
instruction after initial turn-on. Figure 3-34 shows a flow
diagram of the SIO, HIO, no, and TDVoperations.
3-39 COMMUNICA nON CYCLES
The 10P-controlier interface involves signals going from
the lOP to the controller and from the controller to the
lOP. The controller-to-IOP direction defines a communication cycle. The 10P-to-controller direction defines a
service cycle.
During a communication cycle, the lOP raises different
function lines as a result of the instructions executed by.
the CPU. These are the functions:
The controller receives the function strobe and function
indicator (SIO), along with the device address. There are
two strobe signals generated by the lOP: request strobe
and function strobe. The strobe signals are acknowledged
in a closed-loop manner. That is, the strobe signal is
appl ied unti I an acknowledge si gnal is received. Then
the acknowledge signal remains applied until the strobe
si gnal is removed, at which time the acknowledge si gnal
is removed.
a. The start or halt of each station under program
control (SIO and HIO)
b. Status testing of the controller, the station, or
both (TIO and TDV)
c.
Service or interrupt acknowledgement (AIO)
d.
The transfer of orders or data from the lOP (ASC)
The controller acknowledges the FS signal with a maximum
delay of 100 ns. If it is in the OOFOOU state (idle or ready)
the controller raises FSL and supplies status information on
the function response lines (see table 3-5).
The sequence of controller operations for SIO, HIO, no,
and TDV functions is similar, as far as the lOP-controller
interface is concerned. Therefore, a description of the SIO
REMOTE SWITCH -+BV
TO GROUND
INI
Ir--5 MS~
f <
II
',
Ir-5.8
II
r
I
0.5 MS----j
NINI
5O~SIt--
I
INC
0.5 MS
50 !JS----1
AVI SHORTED
TOAVO
~
I
11--
I I
, I
f<
' I
I
NINC
MS--j
I I
,flI
q
II
I 1--4 . 2 MSI
-1
I
I
I
I
I250 ~S----j
~1.6 MS
I--
I
900973C. 315
Figure 3-32. Connect/Disconnect Timing
3-56
SOS 901013
DC DISCONNECTS
CPU EXECUTES
SIO INSTRUCTIONS
-
DC ISSUES sc
!
1
f-
ASC
COMMUNICA nON
CYCLE
lOP ACKNOWLEDGES SC WITH
ASC (DC CONNECTED AND
SERVICE CYCLE STARTED)
ADDRESSED lOP MAKES MEMORY
ACCESS FOR ADDRESS OF
DEVICE, DC,AND FIRST COMMAND
!
-
1
SIO
f-COMMUNICATION
CYCLE
lOP COMMUNICATES WITH DC.
DC SENDS STATUS AND
CONDITION CODE TO lOP
1
DC SPECIFIES DATA OUT
ES
ED
lOP SENDS STATUS AND
CONDITION CODE TO CPU
I
NED NES
•
- ( DATA IS EXCHANGED BETWEEN
DC AND lOP (4 BYTES MAX)
1
)J
DATA OUT
SERVICE CYCLE
lED NES
TERMINAL ORDER
SPECIFIES COUNT DONE
DC DISCONNECTS
DC ENTERS BUSY STATE
(DC STARTED AND SIO CONCLUDED)
-
-.I
J
-
DC ISSUES SERVICE CALL (SC)
ASC
!
I- COMMUNICA TlON
CYCLE
lOP AC KNOWLEDGES SC WITH ASC
(DC CONNECTED AND SERVICE
CYCLE STARTED)
~
ASC
COMMUNICA TlON
CYCLE
lOP AC KNOWLEDGES SC WITH
ASC (DC CONNECTED AND
SERVICE CYCLE STARTED)
-
1
-
DC ISSUES sc
1
1
-
DC SPECIFIES CHANNEL END
BY ORDER IN
DC SPECIFIES ORDER OUT
!
lOP MAKES MEMORY ACCESS FOR
FIRST COMMAND (SENDS ORDER TO DC)
f-
ORDER OUT
SERVICE CYCLE
1
TERMINAL ORDER
(SERVICE CYCLE CONCLUDED)
(DC DISCONNECTS)
1
]
~t
~
l
f-
ORDER IN
SERVICE CYCLE
TERMINAL ORDER
!
NO COMMAND
CHAINING
-
I/O OPERATION CONCLUDED.
DC RETURNS TO READY STATE
COMMAND CHAINING
NOTE: DC = DEVICE CONTROLLER
901515A.329
Figure 3-33. Communication and Service Cycle Sequence
3-57
50S 901013
OS
... ....
IDS- -
I
I
I
L
AVI HIGH
....
. . . r;S
-
-
>...;..;;.;~~ RAISE FRO-FR7(STATUS), FSL
'"
'" '"
DC(SEENOTE 4) - - - RAISE OCR, lOR
--I
RAISE AVO
I
(AVI TO NEXT LOWER
I
PRIORITY CONTROLLER) I
_______ -.J
lOP
ABORT OPERATION
r----I OS
I
----...,
DROP AVO
IL _ _ _ _ _ _ _ _ _
I
INITIATE NO ACTION
I
-.JI
OS
DROP FSL, FRO-FR7
DOR, lOR
lOP MUST NOW WAIT FOR
AVO-FSL PLUS 100 NSEC
PRIOR TO RAISlf'lG A NEW
FUNCTION INDICATOR
DC
DC
INITJA TE NO ACTION
INITIATE NO ACTION
- - - APPLIES TO NON-ADDRESSED DC'S
PROCEED TO BUSY
NOTES:
I.
FOR SIGNALS ARRIVING FROM lOP, All TIMING IS MEASURED AT OUTPUT OF
DEVICE CONTROLLER CABLE RECEIVER.
3.
ONLY ONE FUNCTION INDICATOR (SIO, HIO, TIO, TOV, AIO, OR ASC) CAN
BE HIGH AT ANY TIME.
2.
BEFORE STROBING INPUT SIGNAL LINES AFTER RECEIVING FSL OR RS SIGNAL,
lOP MUST COMPENSATE FOR WORST-CASE SIGNAL DISPERSION CAUSED BY
CABLES, lOP RECEIVERS, lOP LOGIC, PLUS 60 NSEC.
.
4.
DOR AND lOR REPRESENT CONDITION CODES NCCI AND NCC2, RESPECTIVELY,
AT THIS TIME. RAISE lOR (NCC2) ONLY IF APPLICABLE.
5.
AVI TO THE HIGHEST PRIORITY DEVICE CONTROLLER IS ALWAYS HIGH.
900973C. El
Fi gure 3-34. 510, HIO, TIO, and TDV, Flow Diagram
3-58
SDS 901013
DEVICE PRIORITY. When a device controller has been
activated by an SIO instruction, it may make service calls
to the lOP unti I it halts itself or is halted by an HIO instruction. Since many controllers may be connected to one
lOP, a priority chain is established to enable the lOP to
determi ne which controller wants service.
For controllers, with only one device, the following form is
used:
A priority cable is connected between each controller in
the chain and between the lowest priority controller and
the lOP. Four signals are carried on the cable:
The subcontroller compares the contents of the data lines
(DAOR through DA7R) against the outputs of the eight address switches. Terms DCA and DCA47 come true during a
successful comparison:
DAxR lines
Data line
0
Contents
Data,byte
0
1
2
3
4
5
6
7
Device number
a.
HPI - High priority interrupt
b.
HPS - High priority service
c.
AVO -Available output
+ NDA1R SWA1 + DA1R NSWA1
+ NDA2R SWA2 + DA2R NSWA2
d.
AVI -Available input
+ NDA3R SWA3 + DA3R NSWA3) NFSC
N(NDAOR SWAO + DAOR NSWAO
DCA
N(NDA4R SWA4 + DA4R NSWA4
DCA47
The first two signals (HPI and HPS) constitute a signal bus
that is tapped and driven by each controller. Signal AVO
is an output from each controller that is sent to the next
lower priority controller in the chain; it is a logical function of AVI (the input priority signal). Signal AVI is always
true for the first (highest priority) controller in the chain.
Signal AVI for each subsequent controller in the chain is
equal to AVO from the preceding controller.
When more than one controller has made a service request
at the same time, only one may be connected for service.
When the lOP acknowledges the service call, the requesting controller with the highest priority responds to the lOP
acknowledgement.
If a controller has no service request pending, it passes on
signal AVO when it detects signal AVI. If a controller has
a service request pendi ng, the controller passes on si gnol
AVO only if signal HPS is true, or if the controller service
request is of a low priority (that is, t~e controller has not
generated the HPS itself).
If a controller has a service request pending, the controller
does. not pass on si~nal AVO when it detects signal AVI if
it has generated the HPS itself, or if the HPS is not true.
If, during the execution of an 510, TIO, TDV, or HIO, a
controller does not sense its own address, it wi II pass on
signal AVO when it detects signal AVI.
DEVICE SELECTION. When the lOP raises the 510, HIO,
TIO, or TDV function indicators, the device number is supplied as a byte on the DAxR lines. The address number in
the case of multiple devices is in the following form:
DAxR lines
Data line
0
Contents
Data byte
1
1
2
3
Device
controller number
+ NDA5R SWA5 + DA5R NSWA5
+ NDA6R SWA6 + DA6R NSWA6
+ NDA7R SWA7 + DA7R NSWA7)
When the controller is used with a signal tape station, the
outputs of signals DCA and DCA47 must be interconnected
to achieve the full eight-bit device number comparison.
DCA is held farse when FSC is true.
After the lOP raises the function strobe, FS, the subcon. troller suppl ies terms FSL or AVO, dependi ng on the state
of DCA:
FSD
Function strobe de layed
BSYC
ASCM FSR AVIR ASCR
+ AIOM FSD AVIR AIOR
AVOD::::
TTSH NDCA FSR AVIR + •••
The subcontroller also supplies two control terms, TSH and
TTSH:
TSH
DCA (SIOR + HIOR + TIOR)
TTSH
TIOR + TDVR + SIOR + HIOR
When status is apF?lied to the function response lines (FRO
through FR7), the'controller suppl ies term FSD. After FS
goes low, FSD drops, and the controller status information
is gated into the function response lines:
FROD
TSH FSD STSHOO + TDVR DCA FSD STDVOO
+ •••
FR7D
TSH FSD STSH07 + TDVR DCA FSD STDVOO
+ •••
4 5 6 7
Device
number
DAxR lines 1, 2, and 3 specify the device controller number, and lines 4, 5, 6, and 7 specify the device number.
. DCA FSD TTSH + BSYC
FSLD
Terms STSHOO through STSH07 represent status information
supplied by the controller during 510, HIO, or TIO operations. Terms S TDVOO through 5 TDV07 are supp lied duri ng TDV.
3-59
50S 901013
Paragraph 3-41
If the controller address does not agree with the address on
the DAxR lines, signal DCA remains false, and AVO is sent
to the next lower priority controller in the priority chain.
If the controller address does agree with the address on the
DAxR lines, the status report is put on the function response
lines. When the status report is detected, the controller is
connected to the lOP for service.
If, when addressed, the controller is not connected to the
interface cables, or it has its power removed, the AVO signal .is eventually received by the lOP. The lOP then aborts
the operation. Figure 3-35 illustrates the signal sequencing
for 510, HIO, TIO, and TDV functions.
LIl is followed by the high priority interrupt line lCD,
while LIH is followed by HPID.
When the CPU acknowledges the interrupt call, the lOP
raises the AIO function indicator. At this time, the terms
LIl, LIH, and HPIl are latched. HPIl continuously monitors
the state of the high pri ority interrupt line:
NHPIl
=
NAIOR HPIR + HPIl AIOR
When the lOP raises FS, the highest priority controller
examines LIl, LIH, and HPIl to determine whether the AIO
instruction may be accepted. If the AIO cannot be accepted, AVO is sent to the next lower priority controller:
3-41 Acknowledge Input/Output (AIO)
AVOD
The CPU sends an AlO instruction to acknowledge an I/O
interrupt, and to identify the source and the cause of the
interrupt. Figure 3-36 shows a flow diagram of an AlO
interface operation.
The controller raises the term CIl when an interrupt call is
required. CIl is kept raised during the AIO function by
latching circuit LIl:
LIl
INC NAIOR CIl + LIl AIOR INI NRSTR
The controller provides the term CIH for high priority
interrupt calls. CIH is latched by circuit LIH:
LIH
INC NAIOR CIl CIH + LIH AIOR INI
NRSTR
=
NAIOM =
NAIOM AIOR FSR AVIR + •••
LIH + LIl NHPIl
AVIR is true at all times if the controller has the highest
priority. If it does not, AVIR comes true only after all
higher priority controllers have applied AVO.
The action of sequentially sending AVO from higher priority controllers to lower priority controllers continues
until AIOM is found true. AVOD is then inhibited and
FSl is raised:
FSlD
BSYC + •••
BSYC
AVIR AI OR FSD AIOM + ...
DATA LINES (DC)
FROM lOP
FUNCTION INDICATOR
(SIO, HIO, TIO, OR TDV)
FROM lOP
FUNCTION STROBE (FS)
FROM lOP
lEADING FUNCTION STROBE
ACKNOWLEDGE (FSl)
FROM ADDRESSED DC
STATUS OR TEST INFO TO
FUNCTION RESP LINES
FROM ADDRESSED DC
j
ENTER BUSY STATE (510, CC2)
ADDRESSED DC
ENTER READY STATE (HIO)
ADDRESSED DC
901013A. 333
Figure 3-35. SIO, HIO, TIO, and TDV Interface Signal Sequencing
3-60
SDS 901013
f'"oS" - - - - - - ,
I
>---..;..........
RAISE AVO(AVI TO
:
NEXT LOWER PRIORITY I
CONTROLLER)
I _
I..
_ _ _ _ _ _ JI
NOTES:
1.
FOR SIGNALS ARRIVING FROM lOP, ALL TIMING IS
MEASURED AT OUTPUT OF DEVICE CONTROLLER CABLE
RECEIVER.
2.
BEFORE STROBING INPUT SIGNAL UNES AFTER RECEIVING
FSL OR RS SIGNAL, lOP MUST COMPENSATE FOR WORSTCASE SIGNAL DISPERSION CAUSED BY CABLES, lOP
RECEIVERS, lOP LOGIC, PLUS 60 NSEC•
.3.
DOR AND lOR REPRESENT CONDITION CODES NCCl AND
NCC2, RESPECTIVELY, AT THIS TIME. RAISE lOR (NCC2)
ONLY IF APPUCABLE.
4.
AVI TO THE HIGHEST PRIORITY DEVICE CONTROLLER IS
ALWAYS HIGH.
STROBE FRO-FR7,
DAO-FA7,
DOR, lOR
rDc- - - - - - -,
rDS-- - - - --,
I
I
INITIA TE NO ACTION
:
L _______ .J
OS
RESET INTERRUPT
REQUEST CIl. CIH
DROP AVO
I
IL _ _ _ _ _ _ _ JI
OS
DROP IC
DELAY MAX 60 NSEC
---APPUES TO DC'S THAT DO NOT
ACKNOWLEDGE AIO
lOP MUST NOW WAIT FOR NAVO. NFSL
PLUS 100 NSEC PRIOR TO RAISING
A NEW FUNCTION INDICATOR
900973C. E2
Figure 3-36. AlO Operation, Flow Diagram
3-61
SDS 901013
Paragraph 3-42
The controller raises the term CSL when a service call is
required. The subcontroller latches CSL by latching circuit
At this time, the subcontroller presents the controller and
station address numbers on the response lines (FROD through
FR7D). Term AlOe is 0150 supplied, which indicates that
the interrupt call is being ackndWledged:
Aloe
=
lSL:
LSL
CSL INC NFSC NASCR
+ LSL NFSC NRSTR ASCR INI
AVIR AlOR AlOM + AIOC FSD INI NRSTR
ASCR
"The controller continues to hold CIL and CIH high until
AlOC is raised. It then uses AlOC and FSR to reset CIL,
. CIH, and any interrupt indicators that may be set. While
AIOC is high, the controller provides status and condition
codes on the DOR and lOR lines.
For high priority service calls, the controller provides the
term CSH, which is then latched by LSH:
LSH
When FSL is high, the lOP drops FS and 100 ns later drops
AIO. This 'completes the AlO function. Figure 3-37 shows
the interface signal sequence for AIO.
During the ASC function, the controller with the highest
priority sets its service connect and resets its service call
logic •. After the ASC operation is completed, the controller
whose service connect flip-flop is set gets connected to the
lOP until the connection is terminated by service acknowledgement. Fi gure 3-38 illustrates the flow of an ASC
interface operation.
FUNCTION INDICATOR (AIO)
SCD
LSL
HPSD
LSH
The lOP, detecting SC raised, acknowledges this by raising
ASC. At this time, the subcontroller latches the condition
of LSL, LSH, and HPSL:
RESET ONLY WHEN
RECOGNIZED (FROM DC)
I
t
I
I
---1~
FUNCTION STROBE (FS)
-,i
INHIBIT NEW INTERRUPTS
HPSR NASCR + HPSL ASCR
NHPSL =
I
INTERRUPT CALL (IC)
CSH CSL NFSC INC NASCR
+ LSH NFSC NRSTR ASCR INI
. The service cal1 I ine follows LSL, and the high priority line
follows LSH:
3-42 Acknowledge Service Call (ASC)
INTERRUPT FLIP-FLOP
ASC
=
FROM DC
FROM lOP
,,-
I
I
III
I
DELAYED BY EACH DC
I
I
FROM INTERRUPTING DC
I
FROM lOP
•
AVAILABLE
LEADING FUNCTION STROBE
AC KNOW LEDG E (FS L)
INTERRUPT STATUS-DATA LINES
DC NO. -FUNCTION RESP LINES
I
-,
I
901013A.335
Figure 3-37. AlO Interface Signal Sequencing
3-62
SDS 901013
DC MUST HOLD SC HIGH .
(BY MEANS OF CSL) UNLESS
TERMINATED BY AN HIO.
SC SHOULD BE DROPPED
WITHIN 100 NSEC AFTER FS
DROPS DURING THE HIO.
r[)S---------,
I
~:.=..z~~
I
L
RAISE AVO (AVI TO
I
NEXT LOWER PRIORITY I
CONTROLLER)
I
________ ..J
NOTES:
ABORT OPERATION
1.
FOR SIGNALS ARRIVING FROM lOP, ALL TIMING IS MEASURED AT OUTPUT OF
DEVICE CONTROLLER CABLE RECEIVER.
2.
BEFORE STROBING INPUT SIGNAL LINES AFTER RECEIVING FSl OR RS SIGNAL, lOP
MUST COMPENSATE FOR WORST-CASE SIGNAL DISPERSION CAUSED BY CABLES,
lOP RECEIVERS, lOP LOGIC, PLUS 60 NSEC.
3.
AVI TO THE HIGHEST PRIORITY DEVICE CONTROLLER IS ALWAYS HIGH.
roc--------., ;05-- -
>-:':"'--4~
INITIATE NO ACTION
l
L _________ J
I
- - --I
DROP AVO
L _________
I
~
lOP MUST WAIT FOR NAVO,
NFSL PLUS ldtNSEC PRIOR
TO RAISING A NEW FUNCTION
INDICATOR
---APPLIES TO DC'S THAT
DO NOT ACKNOWLEDGE ASC
PROCEED TO SERVICE
OPERATIONS
(FIG. 3-Q THRU 3-45)
901013A.380
Figure 3-38. ASC Oper~tion, Flow Diagram (Prior to Service Connection)
3-63
SDS 901013
Paragraphs 3-43 to 3-46
When the lOP raises FS, the controller examines LSL, LSH,
and HPSL to determine whether any ASC may be accepted.
If the ASC cannot be accepted, AVO is sent to the next
lower priority controller:
AVOD
NASCM
=
=
NASCM ASCR FSR AVIR
lSM + LSL NH1'SL
Priority determination and device selection then take
place in the same manner as for the AIO function.
After FSL is rai sed, the lOP drops FS. The subcontroller,
having ASCM high, sets FSC with the trailing edge of FS:
S/FSC
ASCB
C/FSC
FSR NFSC + •••
ASCB
AVIR ASCR FSR ASCM
+ ASCB NFSC INI NRSTR
When FSC is high, the controller proceeds with the service
operation by raising RS and its associated signal lines:
3-43 SERVICE CYCLES
When the magnetic tape controller has been connected to
the lOP, and after FSC is set, a service cycle is initiated.
There are four types of service cycles: order in, order out,
data in, and data out. The signals present in lines DOR and
lOR of the interface (CC 1 and CC2 at the lOP) determine'
the type of service cycle for any instruction. Figure 3-40
shows a signal sequence after an SIO in which the service
cycles are identified.
An order input cyc Ie occurs when the controller reports
either channel end or unusual conditions to the lOP. An
order output cycle occurs when the controller requests an
order from the lOP. The data in and data out service cycles
refer to the transfer of data to and from the lOP. After a
service cycle is completed, a terminal order is initiated by
the controller. Figure 3-41 illustrates the timing sequence
for a service cycle after FSC is set.
RSD
FSC NRSARC
3-44 Order Input
RSARC
RSAR + FSCL
FSCL
FSC ESR RSAR + FSCL FSC
The order in cycle takes place when the controller must
report errors, unusual end, channel end, etc. to the lOP.
This information is presented to the lOP on the data lines
(DAO through DA7).
'
The term NRSARC prevents switching transients on the
request strobe line, RS, if FSC is slow in resetting.
FSC remains set until ES is raised. This occurs at the
trailing edge of RS:
R/FSC
ESR FSC
C/FSC
RSD FSC
The controller continues to hold CSL and CSH until FSC is
set, unless halted by an HIO. Before FSC is set, the controller removes CSL and CSH. A typical equation for CSL
or CSH is CSL = CSU. CSU is a delay circuit with the
following characteristics:
FSC
~~------------~/,~/------~I
--t5~rCSLI
~
_________
100 NS
MAX
t--
-~______~/LI
,r________________~r-901013A.336
The purpose of CSLI is to prevent controller logic switching
transients from appearing on the service call line.
After FSC is set, the ASC function is completed and communication between the controller and the lOP is established.
3-64
Figure 3-39 shows the interface signal sequence for the FSC
function.
The controller first generates a service call and waits for
FSC to be set. At this time, the request strobe, order request, and data lines are driven. After detecting the service
cycle information, the lOP responds by presenting the ASC
signal. If the lOP does not generate ES during the order
input cycle, the controller requests a terminal order by
raising a request strobe. Figure 3-42 shows a flow diagram
for the order input cycle.
3-45 Order Output
The order output cycle takes place when the controller requests a new order to the lOP. The controller sends a service call to the lOP and then waits for FSC to be set. At
this time, the request strobe, order request, output request,
and end data lines are driven. The lOP responds by raising
RSA and presenting the requested order information on the
data lines. If a terminal order is required by the lOP, the
controller sends one more request strobe signal to the lOP.
Figure 3-43 shows a flow diagram for an order output.
3-46 Data In put and Data Output
The data input/output cycle takes place wh'en the controller
is ready to send or receive data, and also whenthe controller is ready to accept control information for a space
operation. After: FSC is set, the request strobe, input/output, and ~ata lines are driven. The lOP responds by
accepti n9 or presenti ng the data' on the data lines. The
controller continues sending request strobe signals until the
lOP sends ES. If a terminal order is necessary at this time,
the lOP sepds not ES, but a count done indication. Figures
3-44 and 3-45 show flow diagrams for the data input and
data output cycles, respectively.
SDS 901013
RESET QNL Y WHEN
_____~---RECOGNIZED
SERVICE -REQUEST (CSL)
FROM DC
SERVICE CALL (SC)
FUNCTION INDICATOR (ASC)-----4/
,~I
LFROMIOP
__
I I
FUN,CTlON STROBE (FS)
FROM lOP
-....;....------...:..I-.. .
INHIBIT NEW SERVICE CALLS - - - - . '
.......
1
I
III
AVAILABLE
t.-.--EACH DC
DELAYED BY EACH DC
"'"-----
LEADING FUNCTION STROBE
AC KNOWLEDGE (FSL)
FROM
RE~OGNIZED
'-----
I
DC
SET WHEN S£RVICE CALL HAS
BEEN RECOGNIZED
SERVICE CONNECT FLIP-FLOP_(.;...F_SC..;..)_ _---:.__________
- 901013A.337
Figure 3-39. FSC Interface Signal Sequencing
SIO
~-
lOR
r---l. . . ___--'r-- -1L-_ _ _--'r---1L-_ _ _ _--'r-- 1 ....._·__
~ ___ n
__ II
__ Jl
~
I L___ ~
L__ ~
L___ -.J
L___ ....r-L
~ ___ --.lUlJ1JL __ ._~ ___ ~ ______
ED
_____
ES
_ _ _rL___
T.O.
____________rL ___________
SC
ASC
FSC
n
~
r-
1
1ORDER OUT
SIO·
+T.O.
•
-----~-----~
________rL ______rL _______
__
I
~
fL ____-------lrL___
~DATA OUT-1
r--- (4 BYTES) I
~
. fL ___ ~
_ _ _rL ___ ~
~
~DATA our-1
, - (4 BYTeS) I
L
[-
DATA OUT --.J
(4 BYTES +T. 0.)
I
901515A.33O
Figure 3-40. Service Cycles, Timing Diagram
3-65
SDS 901013
I
RESET AT END
OF SERVICE
1
I
t
FROM lOP
1
FROM lOP
REQUEST STROBE (RS)
~
I
DATA/ORDER, INPUT/OUTPUT
~
FROM DC
DATA (INPUT)
~
FROM DC
DATA (OUTPUT)
-----1
FROM lOP
SERVICE CONNECT FLIP-FL9P (FSC)
~
t
FUNCTION INDICATOR (ASC)
FUNCTION STROBE (FS)
®
I
FROM DC
FROM lOP
REQUEST STROBE AC KNOWLEDGE
_..;...,1 -®.=,2-U-9L_"l_1
I
I
1
END DATA
_ _ _0_1
-...
'......... POSSIBLE
. / COMBINA lIONS
END SERVICE--./'"
"'-1
1
I"
--------:.1...:..'\----.:..11 I
LEGEND:
CD
@
@
r-
MORE DATA TO FOLLOW
LAST BYTE TERMINAL ORDER
TO FOLLOW
END OF SERVICE
901013A.339
Figure 3-41.
3-66
Servic~
Cycle, Timing Sequence (One Byte)
SDS 901013
r:--------,
DC
I
~~--t"1
FROM ASC FLOW DIAGRAM
(FIG. 3-38)
INITIATE NO ACTION
I
L _ _ _ _ _ _ _ .J
DC
RAISE: DAO-DA7 (STATUS),
DOR,ED
DC - "iAiSERS- - -
NOTES:
1.
FOR SIGNAlS ARRIVING FROM lOP, ALL TIMING IS
MEASURED AT OUTPUT OF DEVICE CONTROLLER CABLE
RECEIVER.
2.
BEFORE STROBING INPUT SIGNAL UNES AFTER RECEIVING
FSL OR RS SIGNAL, lOP MUST COMPENSATE FOR WORSTCASE SIGNAL DISPERSION CAUSED BY CABLES, lOP
RECEIVERS, lOP LOGIC, PLUS 60 NSEC.
3.
AVI TO THE HIGHEST PRIORITY DEVICE CONTROLLER IS
ALWAYS HIGH.
DROP RS, ED, DOR,
DAO-DA7.
STROBE ED, ES
DC
PROCEED TO FIG. 3-.c6
EXAMINE THE FOLLOWING BITS:
IF ORDEII/IN REPORT
EXAMINE
CHANNEL END
DAO (INTERRUPT)
DA2 (COMMAND CHAIN)
DA3 (lOP HALT)
UNUSUAL END
~
DAO (INTERRUPT)
- - - APPUES TO DC'S THAT ARE NOT CONNECTED TO lOP FOR SERVICE
/
901013A. 384
Figure 3-42. Order Input Operation, Flow Diagram
3-67
50S 901013
IDC- - -
>-----......
FIIOM ASC FLOW DIAGRAM.:.....o______"
(fIG. 3-31)
DC
- -
- -
-,
INITIATE NO ACTION :
L _________
~
lIAISE 0011. 1011, ED
lIAISE liS
LOOK FOR INVALID
14----0RDER (IF APPLICABLE)
DC
PROCEED TO FIG. 3-<46
>~--""'EXAMINE THE FOLLOWING
BITS: DAO (INTERRUPT)
DAl (lOP HALT)
- - -APPLIES TO DC'S THAT ARE NOT CONNECTED TO THE lOP FOR SERVICE
NOTES:
1.
FOR SIGNALS ARRIVING FROM lOP, ALL TIMING IS MEASlJIED AT OUTPUT OF DEVICE CONTROLLER CABLE RECEIVER.
2.
BEFORE STROBING INPUT SIGNAL LINES AFTER RECEIVING FSL OR RS SIGNAL, lOP MUST COMPENSATE FOR WORSTCASE SIGNAL DISPERSION CAUSED BY CABLES, lOP RECEIVERS, lOP LOGIC, PLUS 60 NSEC.
l.
AVI TO THE HIGHEST PRIORITY DEVICE CONTROLLER IS ALWAYS HIGH.
Figure 3-43. Order Output Operation, Flow Diagram
3-68
901013A.383
SOS 901013
FROM ASC FLOW
DIAGRAM (FIG. 1-.)
r,-------,
>----.....L1
DC
I
INTIATE NO ACTION
I
______ J
DC
RAISE ED(IF LAST DATA
.!.Y!!) £A~ -.E~ (~T~)
DC- RAISE RS
lOP
RAISE ED (IF LAST DATA
BYTE), ES (LAST DATA BYTE
AND NO TERMINAL ORDER
DC IS NOW
DISCONNECTED
FROM lOP
OS
RESET FSC(WITH FALLING
EDGE OF RS)
NOTES: I. FOR SIGNALS ARRIVING FROM lOP,
ALL TIMING IS MEASURED AT OUTPUT
OF DEVICE CONTROLLER CABLE RECEIVER.
2. BEFORE STROBING INPUT SIGNAL LINES
AFTER RECEIVING FSL OR RS SIGNAL,
lOP MUST COMPENSATE FOR WORST-CASE
SIGNAL DISPERSION CAUSED BY CABLES,
lOP RECEIVERS, lOP LOGIC, PLUS 60 NSEC.
DC
PROCEED TO FIG. 3--46
EXAMINE THE
FOLLOWING BITS:
DAO (INTERRUPT)
DAI (COUNT DONE)
DA3 (lOP HALT)
3. AVI TO HIGHEST PRIORITY DEVICE
CONTROLLER IS ALWAYS HIGH.
----APPLIES TO DC'S THAT ARE NOT
CONNECTED TO THE lOP FOR SEVICE
901013A.381
Fi gure 3-44. Data Input Operati on, F low Diagram
3-69
SOS 901013
IOC'-------,
>-----I~I INITIATE NO ACTION :
FROM ASC FLOW DIAGRAM
(FIG. 3-38)
L _______ J
DC
RAJSE"I~
ED (If LAST
.E.A!!-..!Y!!l_ _ __
DC
RAISE lIS
lor
RAISE DAo-DA7 (DATA),
ED (IF LAST DATA IYTE),
ES (LAST DATA IYTE AND
NO TERMINAL ORDER)
NOTES:
DC
DROP RS, ED, lOR.
STROlE DAo-DA7,
ED, ES
1.
FOR SIGNALS ARRIVING FROM lOP, ALL TIMING IS
MEASURED AT OUTPUT OF DEVICE CONTROLLER CABLE
RECEIVER.
2.
BEFORE STROBING INPUT SIGNAL UNES AFTER RECEIVING
FSL OR RS SIGNAL, lOP MUST COMPENSATE FOR WORSTCASE SIGNAL DISPERSION CAUSED BY CABLES, lOP
RECEIVERS, lOP LOGIC, PLUS 60 NSEC.
3.
AVI TO THE HIGHEST PRIORITY DEVICE CONTROLLER IS
ALWAYS HIGH.
---APPUES TO DC'S THAT ARE NOT CONNECTED
TO THE lOP FOR SERVICE
DC IS NOW DISCONNECTED
FROM lOP
os
RESET FSC (WITH
FALUNG EDGE OF RS)
DC
PROCEED TO FIG. 3-46
>-;..;.;;.__.... EXAMINE THE FOLLOWING BITS:
DAO
DA 1
DA3
DA4
(INTERRUPT)
(COUNT DONE)
(lOP HALT)
(IGNORE LAST DATA
BYTE)
901013A.382
Figure 3-45. Data Output Operation, Flow Diagram
3-70
SDS 901013
c.
3-47 Terminal Order
A terminal order may be carried out by the controller after
any service cycle. The controller initiates the order if ED
is high and ES is low. Under these conditions, the controller sends a request strobe signal. The lOP then presents the
terminal order information on the data lines.
The next operation of the controller is determined by the
data I ines that are currently raised, as follows:
Data Line
o
Operation
lOP halt
2
3
Paragraphs 3-47 to 3-49
Controller Action
Data transfer stops and
unusual end or channe I
end is reported
The CPU executes a halt instruction.
d. The lOP indicates a halt by a terminal order
(unusual end).
e. Channel end takes place without command
chaining.
f. The RESET switch on the station has been activated
(unusual end, if busy).
g.
An unusual end condition arises.
h. Channel end and device end do not occur at the
same time.
Command chain
An order output cycle is
initiated after device end
During this state, the controller is in an idle or ready condition. It can generate new interrupts or accept an SIO if
no interrupts are pending. Upon acceptance of an SIO, the
controller advances to the next state. See figure 3-48 for
a flow diagram of the SIO operation.
Count done
An order input cycle is
initiated after channei
end and devi ce end
The controller enters state OOFOOU when FF1, FF2, FU1, and
FU2 are false:
An interrupt call is
initiated
Interrupt
The end data and end service lines control the termination
of a service cycle in the following manner:
Definition
End Data
End Service
o
o
More data to follow
o
Last byte. Terminal
order requested
OOF
NFFl NFF2
OOU
NFUl NFU2
E/FFl
RSTA
E/FF2
RSTA
RSTA
DACFDD HLTD + RSTS
DACFDD
DACFD FSR + ATO DACFDD
DACFD
(FDl DA5R) + (NFDl NDA5R)
(FD2 DA6R) + (NFD2 NDA6R)
End of service
x
(FD3 DA7R) + (NFD3 NDA7R)
The end data line can be raised by either the controller or
the lOP to indicate a last byte condition. The end service
line is controlled by the lOP only. The controller resets
FSC when ES is raised. Figure 3-46 shows a flow diagram
for a terminal order.
FSR
Function strobe receiver. Receiver
output from lOP signal FS
ATO
(BANDO
3-48 STATES
HLTD
NFSR ATO
NFSR
Inverted output of FSR receiver
RSTS
(RSTR + NINI) NMAN
RSTR
Receiver output from lOP signal RST
(I/O reset signal)
NINI
Inverted output of switch contact
signal source INI. (Diode clamp
gate for power fai Iure or initialize)
3-49 OOFOOU, Idle or Ready
NMAN
NMANC
The controller enters the OOFOOU state for any of the
following reasons:
NMANC
Selector toggle switch output for
PET panel
The controller goes through eight different states in the
performance of its functions. The controller states are determined by the condition of four flip-flops: fFl, FF2, FU1,
and FU2. FFl and FF2 are located in 16Yi FUl and FU2 are
located in 17Y. FFl and FF2 determine the F phase, whi Ie
FUl and FU2 determine the U phase. The four flip-flops
and their associated logic circuits constitute the state
counter. Figure 3-47 shows a block diagram of the state
counter conditions and state transitions.
a.
Power is initially applied.
E/FUl
RSTS
b.
The I/O reset is generated by the CPU.
E/FU2
RSTS
FSD) + (A TO HIOR)
3-71
SDS 901013
FROM SERVICE FLOW DIAGRAMS
(FIG. 3-42 THRU 3-.c5)
NOTES: 1. FOR SIGNALS ARRIVING FROM lOP, ALL TIMING IS MEASURED AT OUTPUT OF
DEVICE CONTOLLER CABLE RECEIVER.
2. AVI TO THE HIGHEST PRIORITY DEVICE CONTROLLER IS ALWAYS HIGH.
901013A.385
Figure 3-46. Terminal Order Operation, Flow Diagram
3-72
SOS 901013
NO COMMAND CHAINING
OOFOOU
IDLE OR READY STATE
, COMMAND CHAINING (NO UNUSUAL END OR lOP HALT)
01FOOU
ERASE ORDER (WITH OR WITHOUT TERMINAL ORDER)
ORDER OUTPUT STATE
01F01U
ORDER
INPUT
STATE
...
"
-
lOP HALT ON TERMINAL ORDER (DA3R), OR UNUSUAL END
1. NOT AN ERASE ORDER
2. NOT lOP HALT ON TERMINAL ORDER
.
•
WAITING STATE
FOR DEVICE READY
01F02U
...
UNUSUAL END CAUSED BY AN INVALID ORDER
1. TAPE MOTION ORDER (DEVICE IS SELECTED)
2. NOT UNUSUAL END
•
WAITING STATE FOR
DEVICE PROCEED
OlF03U
a. REWIND
REWIND ORDER. (ON-LINE WITH OR WITHOUT INTERRUPT, OR OFF-LINE)
b. END OF STARTING
DELAY
-
1. NOT A REWIND ORDER
2. UNUSUAL END
LONG GAP DETECTION ON READ ORDER (SHORT RECORD)
DATA TRANSFER STATE
TAPE MARK DETECTION ON SPACE FILE ORDER
a. WRITE DATA OUTPUT
03F
b. READ DATA INPUT
03U-02U LONG GAP DETECTION ON SPACE RECORD ORDER
UNUSUAL END
c. SPACE (RECORD OR FILE)
d. WRITE TA~ MARK
,
'-.
."
---.
WRITE
LONG GAP DETECTION ON WRITE TAPE MARK ORDER
COUNT DON E ON TERMINAL ORDER (DA 1R)
lOP HALT ON TERMINAL ORDER (DA3R)
...
COUNT DONE ON TERMINAL ORDER (DA1R)
~
READ
lOP HALTON TERMINAL ORDER (DA3R)
DEVI CE NOT BUSY
ORDER
FINALIZA TION
STATE
03FOlU
BEGINNING OF TAPE DETECTION ON REVERSE TAPE MOTION
LONG GAP DETECTION ON READ AFTER WRITE
LONG GAP DETECTION ON READ ORDER
UNUSUAL END (STATION NOT IN AUTOMl'TIC)
...
03FOOU
STATION
FINALIZA TION
STATE
901013A.347
Figure 3-47. Magnetic Tape Controller States, Flow Diagram
3-73
II
"-----'
o
V)
o
"i
a...
o·
.;:J
"TI
f
o
o·
cc
a3
rY 21V)
o
V)
'0.
l"lA~
'-----~-~..~
- ~-....
'
--
o
o
.w
SDS 901013
When flip-flops FF1, FF2, FU1, and FU2 are reset, the controller raise's CRD (controller ready) if there are no pending
interrupts:
NTSH NMAN OOF + OOF NMAN CRD
CRD
NSIOR NHIOR NTIOR NDCA
NTSH
The controller is now ready to accept an SIO from the lOP.
When the SIO arrives, SIOR (receiver output from lOP signal SIO) is made true. See figure 3-49 for a timing diagram
of the OOFOOU state.
,
The lOP raises the device designation on the DA5R, DA6R,
and DA7R lines. These lines are connected to the set inputs
of flip-flops FD1, FD2, and FD3, respectively:
S/FDl
DA5R
C/FDl
GBS FSD
M/FDl
PETDAl MAN
PETDAl
PETDA1C
E/FDl
RSTA
S/FD2
DA6R
C/FD2
GBS FSD
M/FD2
PETDA2 MAN
PETDA2
=
E/FD2
RSTA
S/FD3
DA7R
C/FD3
GBS FSD
M/FD3
PETDA3 MAN
. PETDA3
PETDA3C
E/FD3
RSTA
PETDA1C, PETDA2C, and PETDA3C are used for the PET
panel.
The set inputs of the flip-flops selected by the DA lines
. (F D1,' F D2, or F D3) are a I so made true by the DA lines. The
lOP raises FS, and FSR (receiver output from lOP signal FS)
is made true. The controller now raises FSD, which makes
the clock inputs of FD1, FD2, and FD3 true. When the controller drops FSD, the three flip-flops are clocked, and the
ones that have their set inputs true are set. The output from
these flip-flops is connected to a decoder. The output of the
decoder (DFDO through DFD7) is routed through other gating
circuitry and sent to the lOP as DVOD through DV7D. TheSe
I ines indicate to the lOP that the correct device has been
selected and is now waiting for the next command.
After device selection takes place, term DCA comes true
and in turn causes GBS to come true. GBS and FSD cause
RESIN to come true. They are also connected to'the set
and clock inputs of fl ip-flops FF2 and FU2.
PETDA2C
OOF
CRD
SIOR
GBS
FSR
- - - - - - -----------'
FSD
LOAD DEY ADDR (FDl - FD3)
SET FF2
SET FU2
RESET FUl
901083A.36O
Figure 3-49. OOFOOU State, Timing Diagram
3-75
Paragraph 3-50 .
SDS 901013
RESIN
RSTB + BAN D05
S/FF2
(GBS NFF2) + •••
RSTB
RSTA
BAND05
GBS FSD
C/FF2
(GBS FSD) + •••
S!FU2
(ESR 01 FOOU) + (NESR 01 FOI U)
+ GBSODST
When OlFOl U comes true and if term ESR is false, flip-flops
.
FUN, FCN, FPE, FLE, and FlO are reset:
E/FUN
BOR03
BOR03
RSTB + BAN 006
RSTB
RSTA
BAND06 -
01FOI U NESR
ESR
ESRC NMAN + BOR05 MANA
RSD1
E/FCN
BOR03
ESRC
Receiver output of IOPls ES·
E/FPE
BOR03
BOR05
BAND28 + FU3
E/FLE
RSTB
MANA
MANC (selector toggle switch
output)
E/FIO
RSTA
RSDI
RSD
01F01U
Control Ier state
GBSODST
GBS + DST
C/FU2
CFU2
CFU2
CSL
CSLX
BAND22
WRITE NWTM FUI
SRIPA
MD3 DLCP
CFU2X
01FOOU + 01F01U + BAND24
NFU3
BAND20 FU3 + BAND19 + 03F
END
(01F01U + 01FOOU) + (BAND22
BAND24
FU1 READ
BAND30
BMT NFUN
CSLI
Service request inhibit signal
The lOP then raises ASC (acknowledge service call), FS
(function strobe), and AVI (available input). These si gnals
are used to generate the set input for service connect flipflop FSC:
S/FSC
RESIN then resets direct-connected (dc) data logic circuits
NCRE, RATE, and DATE. When FSD goes false, it clocks
both FF2 and FU2 and they set, which advances the controller to the next state.
CSLX CSLI
BAN D30 + BAN D24 BAN 030)
BAND05 + BAND22 SRIPA
+ CFU2X RSD + CFU2Y CLK
CFU2Y
The controller also raises CSl:
ASCB
ASCB
ASCR FSR AVIR ASCM
ASCR
Acknowledge service call receiver
output sig~al from IOPls ASC
FSR
Function strobe receiver output signal from IOp ls FS
AVIR
Available signal receiver output
ASCM
LSH + LSL NHPSL
LSH
CSH CSL NFSC INC NASCR
3-50 01 F01 U, Order Output
The controller advances to state 01 F01 U for either of the
following reasons:
a.
An SIO has been accepted from the lOP.
b. The controller has reported channel end with
command chaining.
In this state, the controller requests service from the lOP
by raising signalCSL. After the controller is connected to
the lOP for service, the order for the function to be 'performed is sent from the lOP. After the order is received,
the controller advances to state 01F02U. Refer to figure
3-50 for a flow diagram of the 01 FOI U state.
3-76
+ LSH NRSTR ASCR INI NFSC
LSL
CSL INC NFSC NASCR
+ LSL NRSTR NFSC ASCR INI
NHPSL
NH PSR NASCR + NASCR NH PSL
SDS
9010q
Olr01U STATI
lRSD
SET FOI -F05
STROBE ORDER
FROM DATA LINES
901083A.359/1
Figure 3-50. OlF01U State, Flow Diagram (Sheet 1 of 2)
3-77
SDS 901013
D
YES
SET flO
INTERRUPT FF
SET FUN
UNUSUAL END
SET FCN
CHANNEL END FF
OlfOOU
NEXT STATE
901083A. 359/2
Figure 3-50. 01 F01 U State, Flow Diagram (Sheet 2 of 2)
3-78
SDS 901013
The set and clock inputs for FSC are made true. When FSR
goes false, fSC is clocked and sets. At this time, the RSD
(request strobe driven),. DORD (order request), lORD (output
request), and EDD (end data) lines are made true:
DORD
(DA6R DAlR) DA2R + (N DA6R
+ N DA7R) DA6R
(DA6R DAlR) DA3R + (N DA6R
S/F05
+ N DA7R) DA7R
BANDOS + BANDl3 + BANDOl
+ DCA TTSH ARG
01F01U NFU3 RSD
BANDl3 =
01FOOU NFU3 RSD
TTSH
SIOR + HIOR + TlOR + TDVR
ARG
Address recognized by station
01 FOl U NFU3 RSD
C/FOlC/F05
•
BANDOS =
lORD
S/F04·
When 01 FOl U, NFU3, and RSD are true, the lOP raises RSA
(request strobe acknowledge); at that time, RSD goes false
and clocks the flip-flops:
RSD
NRSAR RSDX + •••
(DRD TDVR DCA) + (DCA TDVR DBS)
+ IORDY + BANDOS-·+ (NFUN
BANDOl) + (BAND22 BANDl6) + GBS,
+ [BAN D04 (CRD
i-
NDACFD)]
TDVR
Test device line receiver output
DBS
Device busy signal (from station)
IORDY
(DCA TlOR DRD) (NDBS NINTPEND
CRD)
BANDl6 =
NFU3 RSD
BAN 004 =
DCA HIOR
The flip-flops set to the order on their set inputs. The controller now performs its logic functions and advances to one
of two possible states, either 01 FOOU (order input) or 01 F02U
(device selection), depending upon the order that is i'n flipflops FO 1 through F05.
If the order in the controller is an erase order, the lOP
raises ESR (end service). Flip-flops FCN (channel end) and
FRS (erase) are set, and FU2 and FSC (service connect) are
rese~
.
S/FCN
SFCN.
NFCN + SFCN
[(NFU3 BAND09 BAND11)
EDDX + BAND08 + FSCC EDB BAND31
+ (BAND11 BAND12 FRS)]
EDDX
BANDl3
+ BAND19 + 03FOOU
EDB
BMTC MCOl
BAN009
DA1R DA2R NDA3R DA6R DA7R
BAND3l =
FUl NFU3 READ
BANDll
01FOl U ESR
EDD
S/FRS
The DORD and lORD lines are used by the controller to
specify to the lOP the type of communication which is to
take place. The DOR,D and lORD line designations are as
follows:
SFRS
SFCROFRS + BAND09. BANDlO
SFCROFRS=
(NBOR06 + NESR) 01FOOU
BANDI0
OlFOl U NFU3
C/FRS
Order out
o
Order in
Data out
o
Data in
o
DORD and lORD are both true in this phase, which is an
order out cycle.
The order that the lOP places on the DAO through DA7 lines
is impressed on the set inputs of flip-flops F01 through FO!>:
S/FOl
DA6R DAlR
S/F02
DA4R
S/F03
(DA6R DA7R) DAlR + (NDA6R
+ N DAlR) DA5R
CFRS
CFRS
CFRSX RSD
CFRSX
NFRS BANDlO + FRS 01FOOU
M/FRS
o
SFRS
(M/FRS)
(M/FRS)
DST FOl345
FOl345
FOl F03 F04 F05
E/FRS
RSTA
C/FU2
CFUX RSD + •••
C/FSC
RSD FSC + •••
R/FSC
ESRC FSC
When RSD goes false, FCN and FRS are clocked and set,
and FU2 and FSC are clocked and reset. The controller
then advances to the next state, 01 FOOU (order input).
3-79
Paragraph 3-51
SDS 901013
If a terminal order had been required, the lOP would not
FOl345
FO 1 F03 F04 F05
F05NF014
F05 NFOl NF04
NFPETl
FI ip-flop output for PET panel
BAND20 DSG NFU3
S/FU2
(FOl345 + F05NF014) NFPETl
WRT
have raised ·ESR immediately. Then, FU3 (terminal order)
would have sel, and FU2 and FSC would have remained
set when RSD went false:
+ EDR NESR FSCC
BAND20
DST NFUN
If the controller does not contain a write order, FRS (erase
DST
OlF02U
flip-flop) remains reset. IVO (invalid order) comes true for
the following reasons:
DSG
Device selected signal (from station)
The controller raises RSD again, and the lOP raises RSA
a. BTSC (load point control) in the station F01, and
and ESR. When RSA goes true, RSD goes false and clocks
F02 are true:
and resets flip-flops FU2, FU3, and FSCj the controller
1..
again advances to state 01FOOU. If the lOP gives an inter~
IVO = BTS F01 F02 (Reverse function at BOT)
rupt to the controller in the terminal order (DAO true), fl ip- A
flop FlO (interrupt) sets when RSD goes false.
r
b. Arriving orders are not used in the 7371 mode:
"b. . .
S/FIO
ft'"
DAOR SFIO
=
IVO
NF04 NF05 (F01 NF03 + NFOl)
........
SFIO
FU3 NDST
c.
If the lOP gives a halt command to the controller in the
terminal order (DA3R true), flip-flop FUN (unusual end)
sets when RSD goes false:
SFUN
SFUNX + CFUNX
SFUNX
FU3 NDST ESR DA3R
WRT and NWPM are true:
IVO
=
WRT NWPM (Write when fi Ie protected)
If WRT and NWPM are true, FPE (write protect violation) is
set when ClK goes false:
SFUN
S/FUN
i1I~
NWPM WRT
S/FPE
If there is an erase order in the controller, FC N sets when
RSD goes false. Flip-flops FU2 and FSC reset when RSD
goes false and the controller has advanced to the next
state, 01 FOOU.
NWPM
Not file protected
WRT
Write operation
ClK BANDl7
C/FPE
If there is not an erase order in the controller, flip-flop FUl
BANDl7
DST NOR01 AUT
sets, and FU2 and FSC reset when RSD goes false:
DST
OlF02U
NOROl
(NDCA + NTTSH) NAIOR
S/FUl
SFUl
SFU1
SFU 1X + 03FOOU
SFU1X
(BAND22 NBAND23 FSCC)
+ (NBAND23 BAND24 FSCC)
+ (NFU3 NBAND09 BAND1l)
+ (BAND11 BAND12 F0134NF051)
If IVO is true, FUN (unusual end) sets when ClK goes false:
j1 ~ ~tf\
The controller then advances to 01F02U (waiting for device
ready). Figure 3-51 shows a timing diagram for the 01 F01 U
state.
S/FUN
IVO BAND17 + •••
C/FUN
ClK CFUNX + •••
FU1 resets the next time that ClK goes false, and the controller now advances to state 01 FOOU (order input) on an
invalid order.
3-51 01 F02U, Waiting for Device Ready
In this state, the controller separates valid and invalid
orders and connects the device for operation. The controller
then advc:;mces to state 01 F03U (waiting for device proceed).
See figure 3-52 for a flow diagram of the 01F02U state.
Assume that the order in the controller is correct. DSS
(device select) is then true:
= NIVO BAND17
-A~DSS
The controller enters the 01 F02U state, and DST (device
select time) comes true:
~-!:.''.'. ~
SG (device select gate) from the station comes true, and
I.
~;,'V\ DST
f\~
.
=
01F02U
If the controller contains a write order when entering the
01F02U state, WRT comes true:
3-80
"tb
'\~~f'
F~sets when
~~
.'~
S/FU3
C/FU3
ClK goes false:
=
DSG BAND20 NFU3 + .••
ClK DST + ...
SDS 901013
L
I ____
01 F01 U
RESET FUN, FeN,
FPE, FLE, FlO
1
L..._ _ _ _
L _ _ _ ,_______
L ____ L
CSL
I
L
. __
i _____
FSC
RSD
- -- - - ------'
____________11__---'0____
RSAR
DORD
- - - - - ------'
lORD
------------- - -----
EDD
I
ESR
-
,...----
___ _
1L
- - - - . . . & ..1 -.....' , _ - - - - 1.
I
L
LOAD ORDER (F01-F05) _ _ _ _ _ _ _ _ _ _ _I_,_ _ _ _ _ _ __
FU3
- - - - - -______1_- ____
I _~__
SET FRS IF ERASE
ORDER
SET FCN IF ERASE
ORDER
SETFUNIFIOPHALT ___________________________~~_______
RESET FU2i SET FU1
IF NOT ERASE ORDER
90 I083A. 361
Figure 3-51. 01 F01 U State, Timing Diagram
3-81
SDS 901013
1 ClK
RESET FU3
lClK
YES
(ORDER INPUT)
(WAIT FOR DEVICE PROCEED)
901013A.352
Figure 3-52. 01 F02U State, Flow Diagram
3-82
SDS 901013
DSL comes true the next time that CLK comes true:
Paragraphs 3-52 to 3-53
S/FF1
DPRNWN + •••
C/FF1
ClK 01F03U
~
DSL
CLK FU3 DST
When CLK goes false, FU3 resets, DSL goes false, and FU2
sets. When DSL goes false, it sets FCT (device connect
flip-flop) in the station. When FU2 is set, the controller
advances to the next state, 01 F03U (wait for device proceed), on a device select order. Figure 3-53 shows a
timi ng diagram for the 01 F02U state.
3-52 01 F03U, Waiting for Device Proceed
The controller advances to the 01 F03U state and enters a
waiting phase for a device proceed order. This phase ends
with either a rewind order or an end of starti ng delay. See
figure 3-54 for a flow diagram representation of the 01 F03U
state.
REWIND. When the controller enters state 01 F03U, RES is
made true:
RES
01 F03U NDPR + •••
RES is used as one of the reset signals for the data logic
circuits.
DPRNWN =
DPR NWN102
When ClK comes true, it makes the clock input of FF1 come
true; when ClK goes false, FF1 is clocked and sets. The
controller now advances to state 03F03U (data transfer).
When the 01 F03U state is entered, if DCA or TTSH is fa Ise,
AlOR is false, and AUTO is not true, FUN (unusual end) is
clocked and set.
C/FUN
BAND29 01 F03U + •••
BAND29
NOR01 NAUT
NOR01
(NDCA + NTTSH) NAIOR
When FUN comes true, it makes the set input of FF1 true:
S/FF1
FUN + •••
When C lK comes true, it makes the clock input of FF 1 true;
and when ClK goes false, FF1 is clocked and sets. The
controller now advances to state 03F03U (data transfer) on
an unusual end order. Figure 3-55 shows a timing diagram
for the 01 F03U state.
3-53 03F03U-02U, Data Transfer
When DPR (device proceed) in the station comes true, it is
AND-connected with the rewind order (WN102) at the
clock inputs of FCN,. FU1,and FU2:
WN102
'WN1 + WN2
WN1
F01 NF03 F05
WN2
F01 NF03 F04
C/FCN
ClK CFCNX + •••
The controller advances to state 03F03U-02U and may enter
one of the following phases: write, read, space file, or
space record. The write and read functions are described in
the last part of this section under the heading Magnetic
Tape System Functions (paragraphs 3-57 through 3-70). The
space fi Ie and space record phase description is given below.
Figure 3-56 shows a flow diagram for the 03F03U-02U state.
SPACE FILE ORDER. When the controller advances to state
03F03U-02U and it contains a space file order, WRT is false
and F01 and SPF are true:
CFCNX
BAND19 + •••
BAND19 =
01F03U DPR WN102
S/F01
DA6R DA7R
ClK CFU1Z + •••
SPF
BAND21 F05
C/FU1
CFU1Z
C/FU2
CFU2Y
BAND19 + •••
ClK CFU2Y
BAND19 + •••
When ClK goes false, it clocks and sets FCN, and resets
FU1 and FU2. The controller now advances to the OlFOOU
state (order input), on a rewind order.
END OF STARTING DELAY (NOT A REWIND). When' the
controller enters state 01F03U, RES is made true. When
DPR in the station comes true, it makes the set input of FF1
true (when the operation is not a rewind):
BAND21
03F F01 F03 NF04
When the tape mark record is detected, TM comes true.
When CLK comes true, it makes the clock input of FU1 true;
when it goes false, it clocks and resets FU1. See figure 3-57
'for a timing diagram of the space file operation.
C/FU1
ClK SPF TM + ••.
The controller now advances to state 03F01 U on a space fi Ie
order.
If TM does not come true on a space fi Ie order, LG comes
true and causes RES to come true:
RES
NTM LG SPF + •••
RES is used as a reset signal in the data logic circuits.
3-83
SDS 901013
.J
DST
(NDCA+NTTSH) NAIOR
AUT
,,...------------
IVO
SET FPE IF WRT NWPM
FUN
DOTTED
INVALID
ORDER
EXIT
r----·--I
RESET FU1
DSS
L
DSG
FU3
DSl
________________
___
I
SET FU2 IF NFUN
elK (60 KHZ)
~rl~
-1l~
__~n___~n~__
901013A.386
Figure 3-53. 01F02U State, Timing Diagram
3-84
SDS 901013
01 F03U.STATE
YES
RES
RESET TO DATA lOGIC
YES
SET FUN UNUSUAL END
SET FFl
ClKL
ClK
1-
SET FFl
SET FCN CHANNEL END
ClK
1-
RESET FU2
(DATA TRANSFER)
RESET FUl
OlFOOU NEXT STATE
(ORDER INPUT)
901013A.354
Figure 3-54. OlF03U State, Flow Diagram
3-85
SDS 901013
01F03U
L __________ L
RES
L ___ _
I
DPR
SET FCN; RESET FU1 AND FU2 (IF REWIND)
~-----------------------------------SET FFl IF NOT REWIND
SET FUN IF (NDCA+ NTTSH) NAlOR+AUT
DOTTEDUNUSUAl{----------~-------------------------
SET FFl IF FUN
END EXIT
ClK (60 KHZ)
901083A.367
Figure 3-55. 01 F03U State, Timing Diagram
3-86
SDS 901013
NO
ru1r-____________
1.
SET FIN
(ORDER FlNA~ZATlON)
901013A.356
Figure 3-56. 03F03U-.02U S,tate, Flow Diagram
SPF FUl
TM (TAPE MARK ¢,R BOT)
nt (}11
'
RES IF SPF NTM lG ::::.
If ~ 0t1
-~-----'
f
RESET FUr
elK (60 KHZ)
901013A.388
Figure 3-57. 03F03Y State (Space File), Timing Diagram
3-87
50S 901013
Paragraph 3-54
SPACE RECORD ORDER. When the control-Ier advances to
state 03F03U-02U and it contains a space record order,
WRT and SPF are false and SPR is true:
BAND21 NF05
SPR
03F FOl F03 NF04
BAND21
lG is connected to the clock input of FU1. When lG and
ClK come true, the clock input of FUl is made true; when
ClK goes false, FUl is clocked and resets:
SPR lG ClK + •••
C/FUl
The controller now advances to state 03FOl U on a space
re~ord order. See figure 3-58 for a timing diagram of the
space record operation.
If TM comes true (before lG), unusual end flip-flop FUN
sets:
S/FUN
TM READ FUl + •••
C/FUN
TM READ FUl ClK + •••
TM is connected to the set and clock inputs of FUN. When
TM comes true, it makes the set input of FUN true. When
ClK comes,trtJe, it makes the clock input of FUN true;
when it goes false, it clocks and sets FUN.
FUN is connected to the clock input of FU1. When ClK
comes true, it makes the clock input of FUl true. When
ClK goes false, FUl is clocked and resets. The controller
has now advanced to state 03FOl U on a space record error:
C/fUl
=
FUN ClK NFSCC 03F + •••
UNUSUAL END. If fUN (unusual end) is true and FSC
(service connect) is false when the controller enters state
03F03U-02U, it immediately advances to state 03F01U.
FUN is connected to the clock inputs of FUl and FIN:
C/FUl
fUN ClK NFSCC 03F + •••
C/FIN
fUl FUN 03F + •••
When ClK comes true, the clock input of FUl is made true,
and when it goes false, it clocks and resets FUl. When
fUl goes false, it clocks and sets FIN. The controller now
advances to state 03FOl U on an unusual end condition.
When the controller advances to state 03f03U-02U, DCA,.
TTSH, AIOR, and AUTO are false and FUN sets:
C/FUN
BAND29
03F BAND29 ClK
NDCA NTTSH NAIOR NAUT
When ClK comes true, it makes the set input of fUN true;
when it goes false, it clocks and sets fUN. fUN is connected to the clock input of FU1; when it goes false, it
resets fUl, which advances the controller to state 03FOl U.
3-88 '
3-54 03FOl U, Order Finalization
The 03f01U state is the order finalization (or terminate
process) state. In this state, the read, write, space record,
and space fi Ie orders from the preceding state (03f03U02U) are terminated. Figure 3-59 shows a flow diagram
for the 03F01U state.
When the controller enters the 03f01 U state on a read or
write order, that order remains true.
If FUN is true on a read order, however, it will dc-set flE
(length error fl ip-flop), indicating a long record:
M/FlE
READ 01 U FUN + •••
If FUN is false and BMT is true on a read order, FlE is
dc-set by BMT:
M/FlE
READ 01U BMT + •••
lG DETECTION ON READ OR READ-AfTER-WRITE
ORDERS. When the controller enters this phase, if lG
comes true, END comes true:
END
03F NfU1 ENDX
ENDX
ENDY + BAND29
ENDY
lG + (f02 FO 1 BOT)
BAND29
NDCA NTTSH NAIOR NAUT
END is connected to the clock input of FU2:
C/FU2
elK END 03f + ••.
See figure 3-60 for a timing diagram of the t-:.oninate
operation.
proces~
When ClK comes true, it makes the clock input of fU2 true;
when it goes false, it c locks and resets FU2, advancing the
controJ\er to state 03fOOU (station finalization).
BEGINNING OF TAPE DETECTION ON REVERSE TAPE
MOTION. If F02 FOl (reverse order) is true when the
controller enters this state and BOT (beginning of tape)
comes true, END comes trUe:
END
03F NFUl (F02 FOl B.OT + ••• )
END is connected to the clock input of FU2:
C/FU2
ClK END 03F + ••.
-When ClK comes true, it makes the clock input of fU2 true;
when it goes false, it clocks and resets fU2, which advances
the controller to state 03fOOU.
SDS 901013
IL
SPR FUl
___ _
lG
r-
TM
I
r-
FUN
I
I·
RESET FUl IF NFSC FUN + lG
ClK (60 KHZ)
__---,n___. . . .n____. . .1L
Jl_~n,--"",,--~n
901083A.371
Figure 3-58. 03F03U State (Space Record), Timing Diagram
03F01U STATE
WRITE
READ
FLE
LENGTH ERROR
LONG RECORD
FUN
UNUSUAL END
901013A.359
Figure 3-59. 03FOl U State, Flow Diagram
3-89
Paragraph 3-:55
SOS 901013
03F NFUl
.-J
L
FU2
L
03F OOU
END IF lG + F02 F01 BOT + (NDCA
+ NTTSH NAJaR) NAVT
I
L
RESET FU2
SET FCN
I
RESET FF1 IF (NDCA + NTTSH NAIOR) NDBS
_----'n___fL
ClK (60KHZ)
WRITE
WTM
READ
----------- ------- --,
I
- - - -- -- - - - - - -
- - - - - - -- - - --,
L-
--------------------------,I
-
901013A. 387
Figure 3-60. 03F01 U State, Timing Diagram
UNUSUAL END (STATION NOT IN AUTO). If, when the
controller advances to state 03F01 U, DCA, TTSH, AlaR '
and AUTO are false, FUN sets and END comes true:
03F BAND29 ClK + •••
C/FUN
BAND29
NDCA NTTSH NAIOR NAUT
03F NFU1 BAND29
END
When ClK comes true, it makes the clock input of FUN true,
and when it goes false, it clocks and sets FUN. END is
connected to the clock input of FU2:
c/Fu2
=
ClK END 03F
When ClK comes true, it makes the clock input of FU2 true,
and when it goes false, it clocks and resets FU2,which
advances the controller to state 03FOOU.
3-55 03FOOU, Station Finalization
end condition. See figure 3-61 for a flow diagram of the
03FOOU state.
When the controller enters this state, if DCA, TTSH, AlaR,
and DBS (device busy) are false and AUTO is true, the
following events occur: FF1 is reset, FCN (channel end)
is set, and the controller advances to the 01 FOOU state
(order input):
C/FF1
NOR01
C/FCN
3-90
NDCA NTSTH NAIOR
ClK 03FOOU + •••
When ClK comes true, it makes the clock inputs of FF1 and
FCN true; when it goes false, it clocks and resets FF1 and
sets FCN. The controller then advances to state 01FOOU
(order input).
If, however, AUTO is false, FUN (unusual end) is set:
C/FUN
The 03FOOU state is the station finalization state. In this
state, the read and write orders are either carried through
to the next state (order input) in a command chaining
operation, or the operation is terminated on an unusual
03FOOU NOR01 NDBS ClK
BAND29
BAND29 ClK 03F
NDCA NTTSH NAJaR NAUT
When ClK comes ture, it makes the clock input of FUN
true; when it goes false, it clocks and sets FUN.
SDS 901013
IParagraph 3-56
03FOOU STATE
ClK
.1.
SET FeN
CHANNEL END
~-------------------------------r~~
YES
SET FUN
UNUSUAL END
RESET FFl
901013A.361
Figure 3-61. 03FOOU State, Flow Diagram
3-56 01 FOOU, Order Input
The 01 FOOU state is the order input state. The controller
enters this state when it must report errors, unusual end,
and channel end to the lOP, or when the command chaining
order must be sent to the state Ql F01 U. Figure 3-~2 shows
a flow diagram for the 01FOOU state.
The lOP receives its input orders during this state on the
following DA lines:
.
Input Order
DA Line
Unusual end
DA4
Channel end
DA3
Input Order
DA Line
Chaining modifier
DA2
Incorrect length
DA1
Transmission error
DAO
Figure 3-63 shows a timing diagram for the 01 FOOU state.
UNUSUAL END. When the controller enters this state, it
generates a service call by raising CSl:
CSL
01FOOU + •••
3-91
SDS 901013
RESET FSC
SEMCE CONNECT FF
RESET FF2
RESET FRS
ERASE Ff
c
901013A.362/1
Figure 3-62. 01FOOU State, Flow Diagram (Sheet 1 of 2)
3-92
SDS 901013
c
SET flO
INTERRUPT FF
RSDt
RESET FF2
OOFOOU
NEXT STATE
(WAIT
FOR ORDER)
901013A.362/2
Fi gure 3-62. 01 FOOU State, F low Diagram (Sheet 2 of 2)
3-93
SDS 901013
IL __ _
01 FOOU
_________ ---1
CSL
L ____ L ___ _
L. ____ L __ _
FSC
-------- ----------'
RSD
- - ---- ------------'
RSAR
----------------_.....
DORD
- - -- --------------'
EDD
-----------------'
ESR
_______________
DAOD IF
DA1 D IF
DA3D IF
DA4D IF
RATE OR DATE
FLE
FCN
FUN
r -_
-____'
---il~
I
L
____ _
- --------- --------'
SET FlO IF DAOR (INTERRUPT)
SET FUN IF DA3R (lOP HALT) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_ __
RESET FCR, FRS IF FUN OR lOP HALT
SET FU2
RESET FF2 IF NO TERMINAL ORDER,
lOP HALT, FUN, OR NO COMMAND CHAIN
901083A.358
Figure 3-63. 01FOOU State, Timing Diagram
3-94
SDS 901013
The lOP acknowledges the service call request by raising
ASC, FS, and AVI. The set and clock inputs of service
connect fl ip-flop FSC are made true, and when FSR (from
the lOP) goes false, FSC is clocked and sets. At the same
time, RSD, DORD, EDD, and DA4 are made true.
The lOP accepts the data and rai ses ESR and RSA (request
strobe acknowledge). RSAR (receiver output from RSA) then
comes true. When RSAR comes true, RSD goes false. When
RSD goes false, it clocks and resets FSC. If there is no
terminal order, RSD also resets FF2, and if there is an
unusual end condition, it resets FRS (erase flip-flop):
C/FRS
RSD 01FOOU FRS +
C/FF2
RSD 01 FOOU + •••
The controller now advances to state OOFOOU (ready state),
where it waits for the next order.
CHANNEL END AND INTERRUPT. The controller raises
CSL, and the lOP acknowledges the service call request
by raising ASC, FS, and AVI. FSC is clocked and set by
FSR (from the lOP), and RSD, DORD, EDD, and DA3 are
made true. The lOP accepts the data and raises RSA, and
RSAR comes true. When RSAR comes true, RSD goes false.
When RSD goes false, it clocks and sets FU3:
C/FU3
RSD FSCC
The lOP drops RSA, and RSD comes true again. The lOP
raises ESR and RSA, and RSD goes false. When RSD goes
false, it clocks and resets FSC and FU3.
If DAO (interrupt) is true, FlO is set when RSD goes false:
C/FIO
(FU3 NDST) ESR RSDl NflO + •••
If DA3 is true, FUN is set, and FCR, FRS, and FF2.are reset
when RSD goes false.
The controller then advances to state OOFOOU (ready) on
a channel end or interrupt.
COMMAND CHAINING. The controller raises CSL, and
the lOP acknowledges the service call request by raising
ASC, FS, and AVI. FSC is clocked and set by FSR (from the
lOP), and RSD, DORD, EDD, and DA2 are made true. The
lOP accepts the data and raises RSA, and RSAR comes true.
When RSAR comes true, RSD goes false. When RSD goes
false, it clocks and sets FU3. The lOP drops RSA, and RSD
comes true again. The lOP raises ESR and RSA, and RSD
goes false. When RSD goes false, it clocks and resets FSC
and FU3.
If lOP halt (DA3) and FUN are false and command chain
(DA2) is true, FU2 sets when RSD goes false, and the controller advances to state 01 F01 U (order output) on a command chai n order:
C/FU2
OlFOOU RSD
\Paragraphs 3-57 to 3-59
The controller now continues with the order that it contains
(read or write) unti I the particular operation is completed.
3-57 MAGNETIC TAPE SYSTEM FUNCTIONS
The main functions of the magnetic tape system are to write
and read data on tape. The logic circuits that perform these
functions are the station data electronics and the controller
data electronics. The station data electronics is comprised
of the modules contained in chassis S. The controller data
electronics is comprised of the modules contained in chassis
V and W. The description that follows covers the write and
read functions in two parts: station data electronics and
. controller data electronics.
3-58 STATION DATA ELECTRONICS
The station data electronics performs all the'dataj>rocessing
required to enable the station to write and read i·rtformation
on tape. This dat!J is provided by the controller as
determined by the program. Figure 3-64 shows a flow
diagram of the station states and differen.t operations for
read and write functions.
3-59 Writing Operation
'J)b~'3'Z-1:.
I/o
,,0
Before the actual recording of informatijin on tape can take
place, one of the eight stations must be selected. After
selection, the station is in state 0 with FCTS set and FSl S
through FS3S reset. The station remains in state 0 for 16.7
fJs (one clock time) and then enters the forward prerecord
delay, state 6. (State 6 is referred to as the prewrite delay
when a write operation is specified in the text.) The activate motor signal, ACMS, comes true and forward tape
motion is initiated. Figure 3-65 shows a flow diagram of
the write operation'I\'}11t~
One of the signals received from the controller during a
write operation is WRT, which is applied to a gate that
produces write enable term WENS:
WENS
OSCTS WRT START CONTR
~1"'lA
Enable OCTS is true in the selected station. Enable START
CONTR is true if the station is in the on-line mode. WENS
is applied along with the set and reset outputs of the write
flip-flops to write drivers that connect to the write head.
Prior to WENS coming true, the write flip-flops were all
set. This occurs because NWENS, on the dc-set input, is
true prior to the write operation or because NWLRSC
inhibited the reset gates at write time. All that is required
at this time to record on tape is for data to be transferred
from the controllar to the station on the WRXS data lines.
Before the controller can begin sending data to the station,
it must first receive the device proceed signal, DPRSD,
from the station:
DPRSD
DPRS FCTD
3-95
SDS 901013
REVERSE
FORWARD
r-----------
--------,---1
I STATE 6
I
I
I
I
I
I
I
L __________ '____________ --1I
READ NOT
FROM
LOAD POINT
READ FROM
LOAD POINT
WRITE
WITH
ERASE
WRITE
WITHOUT
ERASE
IS,7,-E7 - -- - - - - --,
I
I
I
I
I
I
I
I
I
I
I
YES
PRESENT
FORWARD
I INSTRUCTION
INSTRUCTION I
REVERSE
FORWARD I I
L __________
.J I
-
-
I
-
-
-
-
-
-
-
-
-
-l
I
I
NEXT INSTR
REVERSE
(BYPASS DELAY)
I
I
L
-
-
-
I
I IsTME3
I
NEXT INSTR
I
I I NOT
FORWARD 1----..
----l
NO
.....---tl---PR-E-SE-N;..;;.T<
STATE 6
2.9 MS
IsTATE-2- -
NOT END
-
IF DURING DELAY
STATION SELECTED
AND FORWARD
MOTION SPECIFIED -
I
...J
-
-
-
-
I
I
I
I
5.3 MS
I
IF DURING DELAY
STATION SELECTED
AND REVERSE
MOTION SPECIFIED
I
NEXT INSTR
FORWARD
(BYPASS DELAY)
I
I
L ______ .J
-
901013A.364
Figure 3-64. Read/Write Operation, Flow Diagram
3-96
SDS 901013
SElECT SIGNALS
FROM CONTROLLER
J,3~
STATION SELECTED
~1""!>'
~I\"
1-(01
FCTS
NFS1S
NFS2S
NFS3S
STATION
STATE 0
1. INITIALIZE DELAY COUNTER
{ 2. ENTER STATE 6
(05)
,"
FCTS
FS1S
FS2S
NFS3S
PRERECORD DELAY
STATION
STATE 6
obS~
{
1. INITIATE CAPSTAN FORWARD MOTION
2. TURN ON WRITE ENABLE (WENS)
3. REMAIN IN STATE 6 FOR APPROXIMATELY 5 MS UNTIL
PRERECORD WRITE DELAY TIMES OUT
A~~II~
~
FCTS
FS1S
FS2S
FS3S
WRITE
STATION
STATE 7
01"'> ~
1. TRANSMIT DEVICE PROCEED (DPRS) TO CONTROLLER
2. ACCEPT DA TA FROM CONTROLLER AND WRITE
ONTO TAPE
3. WHEN NUM BER OF BYTES SPECIFIED BY ORDER HAVE
BEEN TRAN SMITTED, CONTROLLER TURNS ON ENDS
4. START DELA Y COUNTER AND ENTER STATE 3
{
''C'' 1\1"
~
NFCTS
NFS1S
FS2S
FS3S
FORWARD STOP DELA Y
STATION
STATE 3
O"!>~ ~
t<~'j
NOT SELECTED
1. STATION MAYBE SELECTED (FCTS) FOR ANOTHER
OPERATION WHILE IN STATE 3
2. IF NEW OR DER SPECIFIES TAPE MOTION IN SAME
DIRECTION, STATION STAYS IN STATE 3 FOR 5. 1 MS
TO ALLOW FOR DECElERATION
3. IF NEW OR DER SPECIFIES REVERSE TAPE MOTION,
STATION EXITS STATE 3 WITHOUT WAITING FULL 5. 1 MS
4. ENTER REST CONDITION IF NOT SELECTED
5. ENTER STAT E 0 IF SELECTED
SELECTED
1
NFCTS
NFS1S
NFS2S
NFS3S
STATION
REST
FCTS
NFS1S
NFS2S
NFS3S
STATION
STATE 0
901084A. 317
Figure 3-65. Write Operation, F low Diagram
3-97
SOS 901013
Enable FCTO is true because the FCT fl ip-flop is set in the
se'lected station. Enable OPRS comes true if the state
counter enters state 7; this causes term 07SS to come true.
The state counter wi II not set the FS3S fI ip-flop and enter
state 7 unti I after the forward prerecord delay time has
elapsed:
S/FS3S
SFS3S FCTS
FCTS
True in selected station
SFS3S
06SS NERSS TWRS
06SS
True in state 6
NERSS
True if the erase signal is false from
the controller
TWRS
WRTS FC05S FC09S NFC04S
Enable WRTS is true from the controller during a write
operation.
START PRERECORD DELAY. For the delay counter to reach
a FCOSS, FC09S, NFC04S configuration it takes approximately 6.S ms after the initiation of a write operation.
Therefore, the FS3S flip-flop cannot be set, and it takes
approximately 6.S ms to exit state 6 and enter state 7 on
a write operation. This delay is known as the start prerecord delay, which is necessary to ensure the attainment
of proper tape speed and to have a proper gap between
records.
When the FS3S flip-flop sets, the station enters state 7,
term 07SS comes true, and the device proceed signal,
DPRSO, goes to the controller. When the controller receives
DPRSD, the data is transferred from controller to station.
CONTROLLER TO STATION WRITE DATA FLOW. Information to be written on tape is transferred by characters
via cables from write register output cable drivers in the
controller to cable receivers in the tape station. The outputs of these cable receivers are desi gnated WROS through
WR7S and WRPS. The receiver inputs from the controller
are designated WROCD through WR7CD and WRPCD. The
The WRxS data signals are AND-gated with the SWOAx,
-Bx, and -Cx outputs of the assoc iated wri te deskew
switches and clocks.
WRITE DESKEW CIRCUITS. (See figure 3-66) The write
deskew switches decode one of eight binary write deskew
counts from the output of a counter located in the controller. These counter terms are desi gnated WOC lCD
through WDC3CD. The WDCxCD term is transferred via
cables from write deskew counter cable drivers in the controller to the input of one of the line receivers in the tape
stati on, desi gnated WDC 1S through WDC3S. The outputs
of WDC 1S through WDC3S are parallel input to three write
deskew switches on the barred and unbarred inputs to each
of the C/WDRx buffered AND gates (a total of 27 switches).
These switches are positioned during the deskewing adjustment. They are set for individual channels so that one of
3-98
eight binary counts is selected for input to the associated
C/WDR buffered data cable receiver. The clock term on
the inputs to the C/WDR buffered AND gates also originates
in the controller. Its function is to strobe all the data inputs from the controller at the same time. This action suppresses the effect of any parasitic variations on the data or
write skew count Ii nes. Therefore, the output of a particular
C/WDR buffered AND gate goes true at clock time if a one
bit is present on the WRXS data line and the appropriate
write skew count has been reached.
WRITE FLIP-FLOPS. The outputs of the C/WDRQ through
C/WDR7 and C/WDRP write deskew buffered AND gates
are applied to the clock input of the WDRO through WDR7
and WORP write driver flip-flops. These fl ip-flops are also
referred to as write toggles. The clock input to ~hese write
toggles is true only if a one bit is to be written on tape. A
clock pulse is necessary to change the state of a write flipflop. Therefore, the write flip-flops toggle on a one bit
from the controller and do not change state with a zero bit
from the controller.
To set or reset the write flip-flops, the WRDE toggle enable
term must be true. This term originates in the controller and
is a function of the two most significant flip-flops in the
write deskew counter. The toggle enable comes true during
the last quandrant of the bit time while writing. The set
output of each write flip-flop is connected to the reset
input of the same flip-flop and the reset output is connected
to the set input. Therefore, at toggle enable time (WRDE)
and at the trailing edge of the clock input (a one bit to be
written),any write flip-flop will set if it is in the reset state
or reset if it is in the set state.
WRITE DRIVERS. The set and reset outputs of the write flipflops are connected to separate two-tenn NAND gates on
the input to write-drivers located on the same module as
the write flip-flops. The other enable on these gates is term
WENS, which came true at the start of the write operation
when the station entered state 0 (OSCTS true). It should be
noted that before the write operation, all the write fI ipflops were set because term NWENS was true or because term
NWLRCS was false.
WRITE DRIVERS TO WRITE HEAD. The outputs of the write
driver NAND gates, designated WDRX, are connected
through a resistor module and cable to opposite ends of one
of the seven write head coils. The center tap of each write
head coil is connected through a resistor module to a write
current source. The +2SV write current source is connected
through the write enable relay.
With tenn WENS true, one of the two NAND gates em the
inputs to the write drivers is enabled. The state of the write
flip-flop, set or reset, determines which gate is enabled.
The output of the enabled gate is at a ground potential.
Therefore, current flows from the write current source
through one side of the write head coi I to ground, provided
by the enabled NAND gate. As long as term WENS remains
5DS 901013
WRITE D£SKEW SWITCHES
22S
WDCI
12
a
21S
-
WDCIS
I
~
26
WDC2C
CI
:
:11.. WDC2S
25
.23 NWDC2S
~--.-.-.=----r-~t----i;r--,..4......-
I
215
WDC3S
II
-.21 NWDC3S
"-'
101
I
ClKS
SWQAO
"'il
______________~~~"_~
!
WItOC
22S
CIl"
235
~""t---
IzJ'"L.___
24S ./
\...L
235
I
~
,
~h.:.......-r----""
J
M" I'rFF
31
ClWDRO
~. C 245
I >-~--------~~~--------_;r_--------~q-
215
I
23S
WUCCD
5
'--______. . ;WR.;.:.::;D.=. E__________--,,.......
r--....
WROS
r26S1
NWb~5
I
235
41
r--;.19~--=.SW:.:.OCO=:..-._ _ _ _ _ _ _ _.::::q4:l
61
"I
22S
I
12
r-~I~~~~sw~O~~~
I
21S
I
WDCX:o--":IIo...ICI
I
~'-'O·...:..2
• ..:.NW=DC=IS~_ _T""""'3~d--,
________________,-~~II~'
22S
::=
FCTS
r--iSS--l
21S
CR~~6~_W_~_C-S-~I~__~
r--Y
~22 NWLRCS r--;J
I
I
I
I
I
245
WDRO
.. A
US
•
121
281
. '
271
'22
25VWPI
I
...
2-45
245
I
I
WRITE HEADS
17S
WTHDOC21
WTHDOI
_
r-
~~'i-+-fJ _
..221
---L...U~"7'""'II-_..J
~
TRACK 0
~.~5....;NW~DRO~~2~~----~12--3-WT-:-R~-N-OO-~
It
'--_..J
22S
ClOCKC
~
CIl
-.22 CLOCKS
2.tS
WEN5
I ..--~---"""
1~____________~~-+-+-+~.~I-.....IT
20
B '".>-_ _........
I
I
I
I
.llL..
. ! ~
11
SWOAI
7: ' -.....-----:I~I..~...:S;.;.;W;.;::OI;;;.;.;..I~·- - - - - - - - - - - t - t i - - - - . .
,
lIZ.
I
I
I
I
1,1
131
.l_
,
I
,
235
22S
WRICD
:w
I
WRIS ....
CIl~a.....;.;.;;;.;.;;..
WDRI
C/WDII
I
-
; ...
- .....- ....
t
I
.2!
SWOA2
211
SWQC2
.................-,;......-......
I
26i
,:
I
225
---
WR2CD
CIl
17 WR2S
'
I
,
I
~
I
36
f.6I
-]
~
IDS
~
I
~
134
S
:
1
]
2..S
SWOAJ
I
1. ___
~~-+~3611--,'
I
331
22S
WR3CD
CR.t2
WIl3S
r
r-
[
)--G>L=105
1l1li
lOS
I
1
~t----IJ
I
47
2 ..5
o~
)-L
Y
.31
_._
r-~';r-t'
'33
WTHDII
NWDRI 371
134
WTHDIA
WDR2
140
WTHD2C
~
:...J
TRACK 1
.LU-
1WRGND1~
UU-
275
24S
2
24S
F,-R_~
24S
~
'--__--'
-
_40
_",,","'1-1'-4-
24S
TRACK 2
~.~3~NW~D~R2~45~I----~·4~2~W~TH~D-~--~
I
I
L.. _ _ _ _
JI
WRGND2
r-2is-l
_
It--I~-+-r--~
J
471
~·~·,~~_P4~I~W~TH~D-2~8-4U -4JJ_
2SVWPI~' ....
~
,
NW1ENS
SM
~ f:-......----~:=:-....;SW=SW~~=3--------------f.I:~-2-3S-~....
:3S 39
w-----C/W::::....;;:.:DR3;.:;::...--------+-;-----.--_
. . -__-_. . ._. . .JL.,~c lIs
6-11---4-....:::"::..:.11_
I---.~-f'-~
1, ........
I
-
-
p-
- '] -Lr245
WTHDIC
NW1ENS
28... C 245
........- - 1
lOS
245
C/WDR2
[
I....
4.
___--....
,
-
23S
I
~~-+.-=--!o
2Si--'
23'
I
I
!H
131
~
25VWPI
245
39f
I
I
~
~
~::'~--II~I:~~~S=W=0~~~---------~~~~23S
I
-
~ ~S ~~R_~01~~~-J;--~-5~
t-
I
I
I
III
151
I
SWOCI
275
2-45
23S
2.tS
245
J--
2..S
2"S
.10
WDR3
I
171
I
25VWP2 lsi
I
NWDRJ 1..'
I
I
I
I
1
I
•
19
•
110
I
III
I
I
I,
275
WTHD3C
13
.... _
...----H::-tl -
WTHD38 ~1....J
J
TRACK 3
l.i.J
WTHDlA ......15
WRGND3oil~1--~
I
I
L ___ J
t
I
TO OTHER CHANNELS
Figure 3-66. Write Deskew and Write Head
Interconnect, Logic Diagram
901013A. 366
3-99/3-100
Paragraph 3-60
SOS 901013
true and the write flip-flop does not change state, the write
current continues to flow in the same direction through the
assoc iated wri te head coil. These condi ti ons cause the
magnetic flux for the associated track on the magnetic tape
to be aligned in one direction.
WRITING ON TAPE. When a one bit is received from the
controller, the state of the write flip-flop changes. This
causes the write current ground to switch from one end of
the write coil to the other. Therefore, a current path is
provided through the opposite side of the write coi I, which
causes the direction of the write current to reverse. This
in turn causes the flux on the magnetic tape to change
di recti on by 1800 • In the non return -to-zero (NRZ) method
of magnetic recording, this change in flux direction is
recognized as a one bit. Thus, each one bit of data from
the controller causes the write toggles to change state,
which causes a one bit to be recorded on tape. The write
toggles do not change state with a zero data bit from the
controller (no clock). Therefore, the direction of current
through the write coil does not change, causing a zero bit
to be written on tape.
END OF WRITE DETECTION. In this manner, seven-bit
data characters are recorded on tape. After writing the
last character, the controller waits three byte times and
then transmits an all-ones character to the station. This
all-ones character is used in the generation of the lRC
(longitudinal redundancy character).
lRC CHARACTER GENERATION. When the lRC character
is to be written, the WlRC term (write longitudinal redundancy character) comes true from the controller. With
WLRC true, the inverted NWLRC term goes false. This
inhibits the reset side of all the write flip-flo~ When the
all-ones byte is received from the controller, a C/WDR
clock term is produced to all the write flip-flops. The
particular write flip-flop may be set or reset before writing
the lRC character. The NWLRC reset inhibit and the clock
produced by the all-ones byte cause all the write flip-flops
that are reset to set at the time LRC is to be written. This
change to the set state causes the config~ration in the write
flip-flops to be written on tape as thelRC character.
CONTROLLER WRITE TERMINATION. After the lRC character has been written and transferred back to the controller
by the read after write operation, the controller transmits
the ENDC signal to the station. When the ENDC signal is
received from the controller, term ENDS comes true and is
AND-gated with ClKS to clock the FCTS connected flipflop to the reset (not connected) state. This disconnects
the station from the controller, thereby terminating the
write operation as far as the controller is concerned. Term
ENDS is also applied to a three-term gate on the clock
input to the FS1S flip-flop in the state counter:
C/FS1S
0155 NRVSS ENDS
Upon being disconnected from the controller, the station
is in state 7; therefore, 0755 is true. Enable NRVSS is true
because forward motion is always specified i'n a write operation. Therefore, when ENDS comes true, an input is
produced that c locks the FS 15 fl ip-flop to the reset state.
The FS2S and FS3S flip-flops are still set, which cause the
station to enter state 3. As the station leaves state 7,
capstan motor power is removed (NACMS) and the delay
counter begins to count. (The delay counter was reset on
entering state 7.)
FORWARD STOP DELAY. State 3 is known as the forward
stop delay. Its purpose is to 'provide a delay for the capstan
to decelerate after the forward operation is completed. In
order to leave state 3 and enter state 0, or the idle state
(NFCTS, NFS 15, NFS2S, NFS3S), it is necessary for the
FS2S and FS3S flip-flops to be clocked to the reset state:
CFS2S
C/FS2S
0355 R03SS
CFS2S
CFS3S
C/FS3S
CFS3S
0355 R03SS
R03SS
TSPS
TSPS
FC08S FC07S NFC04S
The delay counter, which was initialized on entering state
3, reaches an FC07S, NFC04S configuration in approximately 5.3 ms. Enable 0355 is true in state 3. Therefore, the
station remains in state 3 for 5.3 ms and then enters state 0
or idle except in the following circumstances:
a. When the FCTS connect flip-flop was reset at the
time the station received the ENDS signal, which 'was before
entering state 3. Therefore, the station can be selected by
another order from the lOP while in state 3. If this new
order specifies tape motion in the same direction, it is not
necessary to stay in state 3 for the entire 5.3 ms because
the tape can be accelerated to nominal speed without first
coming to a stop. There is a clock gate on both the FS2S
and FS3S flip-flops with input enables 0355 and R03SS:
R03SS
FCTS RNVRS
b. When enable FCTS comes true after the station is
selected.
c. When enable NRVRS is true after the new order
specifies tape motion in the forward direction. This is the
direction in which the tape is already moving. Therefore,
the station exits from state 3 to state 0 after a forward read
as soon as it is selected if the tape motion specified by the
new order is in the forward direction.
3-60 Reading Operation
Before information can be read from tape, one of the eight
possible stations must be selected. The station after selection is in state 0 with FCTS set and FS 15 through F535 reset.
The station remains in state 0 for 16.7 I-IS (one clock time)
and then enters the forward prerecord de lay, state 6, by
FS 15 and FS2S being set. Figure 3-67 shows a flow diagram
for the read operation.
3-101
SDS 901013
SELECT SIGNALS
FROM CONTROLLER
FCTS
NFSIS
NFS2S
NFS3S
STATION
STATION SELECTED
STATION
PRERECORD DELAY
FCTS
FSIS
FS2S
NFS3S
STATE 0
1. INITIALIZE DELAY COUNTER
{ 2. EXIT TO STATE 6 IN ONE CLOCK TIME
REMAIN IN STATE 6 FOR APPROXIMATELY 5.4 MS UNTIL
PRERECORD READ DELAY TIME EXPIRES. (THIS STATE
ALLOWS TIME FOR TAPE TO ACCELERATE )
STATE 6
II
FCTS
FSIS
FS2S
FS3S
SPACE READ OR WR ITE
STATE 7
NFCTS
NFSIS
FS2S
FS3S
FORWARD STOP DE LAY
STATION
REST
C'
STATION
STATE 3
NOT SElECTED
NFCTS
NFSIS
NFS2S
NFS3S
TRANSMIT DEVICE PROCEED (DPRS) TO CONTROLLER
2. READ DATA FROM TAPE AND TRANSFER TO CONTROLLER
3. CONTROLLE R TRANSMITS ENDS TO STATION WHEN
LONG GAP IS DETECTED BETWEEN RECORDS
4. RESET FCTS TO ENTER STATE 3. (AS STATION LEAVES
STATE 7, DE LAY COUNTER IS INITIALIZED)
STATION
~
,. 1. STATION MAYBE SELECTED (FCTS) FOR ANOTHER
OPERATION WHILE IN STATE 3
2. IF NEW OR DER SPECIFIES REVERSE TAPE MOTION,
STATION STAYS IN STATE 3 FOR 5. 1 MS TO ALLOW
FOR DECELE RATION
3. IF NEW ORO ER SPECIFIES TAPE MOTION IN SAME
DIRECTION, STATION EXITS STATE 3 WITHOUT
WAITING FULL 5. 1 MS
4. ENTER REST CONDITION IF NOT SELECTED.
~ 5. ENTER STAT E 0 IF SELECTED
SELECTED
FCTS
NFSIS
NFS2S
NFS3S
STATION
STATE 0
901013A. 367
Figure 3-67. Read Operation, Flow Diagram
3-102
50S 901013
State 6 is referred to as the pre read delay when a read
operation is specified in the text. The activator motor signal, ACM5, comes true and forward tape motion is initiated.
The purpose of state 6 on a forward read is to prevent noise
generated during gap time from being interpreted as data in
the controller. This is accomplished by delaying the generation of the device proceed signal, DPRS, to the controller
for a period of 5.5 ms. This delay prevents the controller
from enteri ng the read state for 5.5 ms.
For the controller to read information, it is first necessary
that it receive the device proceed signal, DPRS, from the
station:
DPRSD
DPRS FCTD
Enable FCTD is true because the FCT flip-flop is set in the
selected station. Enable DPRS comes true if the state
counter enters state 7, causing term 07SS to come true. The
FS3S flip-flop does not set to place the station in state. 7
unti I after the forward prerecord delay time has expired:
S/FS3S
SF535 FCT5
FCTS
True in selected station
SFS3S
065S TRDD5 + •••
06SS
True instate 6
TRDDS
NWRTS TRDS
NWRTS
True in a read operation
TRDS
NFC04S FC09S FC06S NERSS
NERSS
True in a read operation except when
the beginning of the tape marker is
detected
For the delay counter to reach an FC06S, FC09S, NFC04S
configuration, it takes approximately 5.5 ms after the initiation of a read operation. Therefore, the FS3S fl ip-flop
cannot be set, and it takes 5.5 ms to exit state 6 and enter
state 7 on a read operation. This delay is known as the
start prerecord delay.
When the station enters state 6 on a read operation with the
tape at load point, it does not exit to state 7 for 29.9 ms.
This is because of the following set input to the FS3S flipflop. It is necessary to set FS3S to enter state 7:
S/FS3S
SFS3S FCTS
FCTS
True in selected station
SFS3S
ISFS35
ISFS3S
NWRTS (true in a read) ERSS (true
because tape at BOT) 06SS (state 6)
TBDS
TBDS
NFC01S FC02S FC03S
Note
The delay counter is inhibited until the tape
is moved off BOT sensor.
The delay counter which began counting when the station
entered state 6 does not reach an NFC01 S, FC02S, and
FC03S configuration for 29.9 ms. Therefore, the FS3S flipflop is not set, and the station does not exit state 6 until
29.9 ms have elapsed. During this 29.9 ms period, reading
is prevented for approximately 2.1 inches after the BOT
marker, where noi se and bad tape may exi st.
When the FS3S fl ip-flop sets, the station enters state 7
. (FS 1S, FS2S and FS3S), term 07SS comes true, thereby
enabling the device proceed signal, DPRSD, to the controller. When the controller receives DPRSD, it enters a
state where it can receive data from the station and transmit
data to the lOP.
The preread delay is always less than the write delay. The
station, therefore, leaves state 6 before readi ng the first
byte of a record on tape. This ensures that the controller
has received DPRSD and is ready to receive data before the
read head sensing the first byte of a record on tape. At this
time, tape has attained a speed of 75 ips and the controller
is in a state in which it may receive data.
READ DATA FLOW. (See figure 3-68) As the magnetic
tape passes over the read head, signals are induced in the
coi Is of the read head. These signals are designated
RDH DO-5 (A, B, and C) for read heads 0 through 5 and
RDHDP(A, B, and C) for read head parity. The letters A,
B, and C pertai n to the two ends and center tap of an i ndividual read head coil. The RDHDO-5 and RDHDP signals
are transferred through a cable and cable connecting module joining the read head coi I to one of the associated read
ampl ifiers, desi gnated RD AMP OS through RD AMP 5S and
RD AMP PS.
Read Amplifiers. The read amplifier responds only to signals
that exceed the threshold voltage level. Each read amplifier has a threshold adjustment that determines the minimum
amplitude necessary for signal recognition.
The 20 to 30 flV read signals from the read head are amplified, rectified, and then clipped in the read amplifiers.
The resultant signal at the test point in the read amplifier
is approximately 1.6V for an all ones pattern on tape and
1.9V for a single one bit.
Read Amplifiers to Controller. The RD AMP OS through
RD AMP 5S and RD AMP PS outputs of the read amplifiers
are applied as inputs to two-term input AND gates on
buffered cable driver circuits designated RD AMP 0 SO
through RD AMP 5 SO and RD AMP P SO, respectively. The
other enabling term on these gates is common enable term
FCTS.
3-103
SDS 901013
READ HEADS
rZT33-'
I
I
I
I J2S
RDHD4A
34
RDHD4B
30
RDHD4C
38
26
24
22
28
RDHDOA
RDHDOB
RDHDOC
RDHDIA
31
RDHDIC
21
19
17
15
17
READ AMPUFIER
24
(HTln
23
3S
34
39
READ AMPUFIER
-46 ROAM' IS
(HTln
.c.s
TO
CONTROLLER
RDHD2A
RDHD28
RDHD2C
22
19
18
READ AMPUFIER
(HTl7)
17
READ AMPUFIER
(HTI7)
23
ROAMP 2S0
8
ROAMP PS
ROAM' PSO
IS
RDGNDP
TP
RDHD3A
34
RDHD38
RDHD3C
31
29
39
READ AMPUFIER
(HT17)
46·RD AMP 3S
ROAMP 3SD
3S
RDGND3
RDHD58
RDHD5C
21
TP
25
RDHD5A
3 RO AMP2S
IS
RDGND2
24
42
44
IDAMPOSD
ROAM' ISO
'Il
39
43
ROAMPOS
RDGNDI
RDHDPA
40
8
TP
RDHDPB
RDHDPC
41
RDAMp I4S0
'Il
'Il
23
29
6
TP
RDGNDO
RDHDIB
ROAM,.U
4S
RDGND4
35
33
37
3
18
TP
27
24
23
17
READ AMPLIFIER
(HTl7)
8 RO AMP5S
7
ROAMP 5SD
4S
RDGND5
FCTS
FCTD
901013A.368
Figure 3-68. Read Head Interconnect, logic Diagram
The outputs of these AND gates are input to the driver portion of the particular RD AMP X SD buffered cable driver.
The outputs of the buffered cable drivers feed cables that
transfer data from the tape station to the associated peak
detect counter in the magnetic tape controller. There are
seven peak counters, one for each of the cable driver
outputs.
disconnects the station from the controller, thereby terminati ng the forward read operation as far as the controller
is concerned.
Term ENDS is also applied to a gate on the clock input to
the FSIS flip-flop in the state counter:
C/FSIS
END OF READ DETECTION. For tape deceleration to be
initiated, the ENDC signal must come true from the controller. It would not be desirable for ENDC to be transmitted to the station as soon as the read termination signals
are received by the controller from the lOP because the
read/write head may be positioned somewhere between the
start and end of a record of information on tape.) Therefore,
the ENDC signal is not transmitted from the controller until
the controller detects a long gap on tape. When the ENDC
signal is received from the controller, term ENDS comes
true and is AND-gated with ClKS to c'lock the FCTS
connect flip-flop to the reset (not connected) state. This
3-104
07SS NRVSS ENDS
The station is in state 7, so 07SS is true. Enable NRVSS is
true because forward motion is specified. Therefore, ENDS
produces an input to clock FSIS to the reset state. This
makes ACMS go false, removing capstan motor power. The
FS2S and FS3S flip-flops are still set, which causes the
stati on to enter state 3. As the station leaves state 7, the
delay counter is initialized.
FORWARD STOP DELAY. State 3 is known as the forward
stop delay. Its purpose is to provide a delay for the capstan to decelerate after the read operation is completed.
Paragraphs 3-61 to 3-62
SDS 901013
In order to leave state 3 and enter state 0 or the idle state
(NFCTS, NFS1S, NFS2S, NFS3S), it is necessary for the
FS2S and FS3S flip-flops to be clocked to the reset state:
C/FS2S
CFS2S
CFS2S
03SS R03SS
C/FS3S
CFS3S
CFS3S
03SS R03SS
R03SS
TSPS
TSPS
FC06S NFC04S
TJ:te delay counter, which started counting, on entering
state 3 reaches an FC06S, NFC04S configuration in approximatey 5.3 ms. Enable 03SS is true in state 3. Therefore,
the station remains in state 3 for 5.3 ms and then enters
state 0 or idle, except in the following circumstance.
EXIT FROM STATE 3 BEFORE 5.3 MS. The FCTS connect
flip-flop was reset at the time the station received the
ENDS signal before entering state 3. Therefore, the station
can be selected by another order, from the lOP, whi Ie in
state 3. If this new order specifies tape motion in the same
direction, it is not necessary to stay in state 3 for the entire
5.3 ms because the tape can be accelerated to nominal
speed without first coming to a stop. There is a clock gate
on both the FS2S and FS3S flip-flops with input enables
03SS and R03SS:
R03SS
FCTS NRVRS
Enable FCTS comes true when the station is selected.
Enable NRVRS is true if the new order specifies tape motion
in the forward direction. This is the direction in which the
tape is already moving. Therefore, the station exits from
state 3 to state 0 afte r a forward read as soon as it is
selected if the tape motion specified by the new order is in
the forward direction.
REVERSE POSTRECORD DELAY. The 2.9 ms delay in state 6
is provided to allow the last bit read to move close to the
write head before any tape deceleration takes place. As
soon as the FS1S flip-flop is reset, the station exits state 6
and enters state 2. The ACMS signal goes false, removing
motor power. State 2 is known as the reverse stop delay.
The purpose of state 2 is to provide a delay for the capstan
to decelerate after the reverse read operation is completed.
To leave state 2, the FS2S flip-flop must be clocked to the
reset state:
C/FS2S
CFS2S
CFS2S
02SS TSPS TRVS,
TSPS
FC06S NFC04S
TRVS
FC05S FC08S FC07S
Enable 02SS is true in state 2. The binary combination of
the TSPS and TRVS delays equals 5.3 ms. Therefore, the
station remains in state 2 for 5.3 ms. It then enters state 0
if the station has been selected, or the idle state except in
the following circumstance.
The FCTS connect flip-flop was reset at the time the station
received the ENDS signal, which was before entering state
6. However, the station can be selected by another order
from the lOP while in state 2. If this new order specifies
tape motion in the same (reverse) direction, it is not necessary to stay in state 2 for the entire 5.3 ms period because
the tape can be accelerated to nominal speed without
coming to a complete stop. There is a c lock gate on the
FS2S flip-flop with input enables 02SS, FCTS and RVRS:
C/FS2S
CFS2S
CFS2S
02SS FCTS RVRS
The FCTS enable is true if the station is selected. The 02SS
enable is true in state 2. The RVRS enable is true if reverse
motion is specified. Therefore, the station exits from state
2 in one clock time if it is selected, and the tape motion
specified by the new order is in the reverse direction.
3-61 CONTROLLER DATA ELECTRONICS
The seven-track controller data chassis is available in two
confi gurations: one with and one without the packing
option. The model 7371 controller contains the controller
chassis (Y and Z) and the data chassis (V and W). The
packing option (model 7374) consists of four modules and
an interchassis cable which interconnects the Y, Z, and W
chassis. The model 7371 is always wired for the packing
option. However, only if the model 7374 modules are inserted wi \I the packing function be effected.
3-62 General Descri ption
A description of the controller data logic follows. A block
diagram of the controller is shown in figure 3-69.
Previous to any operation, a reset si gnal is sent by the controller to initialize all registers and counters. In write
operations, bytes are requested from the lOP and stored in
the eight-byte memory, to be transferred to the buffer
register as directed by the data logic. The buffer register
provides the intermediate storage interval during which the
byte to be recorded is modi fied as requi red by the mode
logic.
During the write interval, the character to be recorded is
transferred from the buffer register via the write cable to
the write drivers in the selected station, and is then recorded
on tape. The accuracy of the written material is checked
by the read logic, which monitors the read amplifiers,
deskews the data output, and checks for lateral parity,
longitudinal parity, and skew errors.
During read operations, the data appearing at the read
ampl ifier is deskewed and assembled at the assembly register.
3-105
Paragraph 3-63
SDS 901013
At the end of the skew interval, the character is checked
for parity, transferred to the longitudinal check register and
is transferred to the buffer register. In the buffer register,
the character is modified according to the mode of operation (BCD, binary or packed) and transferred to the memory
for subsequent transfer to the lOP.
the data electronics. The controller flip-flops F02 and
F03 determine the mode as follows:
F02
F03
o
o
Mode
Pack
o
Binary
Error checking is done in the longitudinal check register for
longitudinal parity errors, and in the assembly register for
lateral parity errors.
o
Pack
BCD
The pack mode signal is formed in the packing option logic:
3-63 Mode Control
In conjunction with the write and read signals, the controller
must transmit information to define the mode of operation of
DPAK
NF03 OPER
OPER
WNTME + READ
LONGITUDINAL
CHECK REGISTER
BCD TO
EBCDIC
CONVERTER
PREVIOUSLY
ASSEMBLED REGISTER
\
'-i----,----------..J I \ - - - _
-r--------...i L_-,
I
I
I
8 BYTE
MEMORY
BUFFER
REGISTER
I
PEAK AND
DETECTOR
DESKEW
P
IL ___ _
7
I
--4
FROM READ
AMPLIFIER
STATION
I
I
lOP
I
I
I
I
~
I
I
PARITY
CHECK
o
ASSEMBLY
REGISTER
P
PACK MODE
-------------,
BIN MODE
- ---------..,
BCD MODE
I
- - ----,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
5
IEBC~ Iii
BCD
L--..L.LT
I
I
PARITY
GENERATOR
I
I
I
TO WRITE
DRIVERS
STATION
L ______ -.
5
READ - - -
WRITE CABLE
DRIVERS
WRITE -----
901013A. 379
Figure 3-69. Controller, Block Diagram
3-106
Paragraph 3-64
SDS 901013
The binary and BCD modes are formed from the pack signal:
DBIN
NDPAK NF02 OPER
DBCD
NDPAK F02 OPER
In the event that the program calls for the pack mode and
the packing option is not installed, the binary mode is
selected automatically. This occurs because the term
NDPAK is formed within the packing option logic,and if
the option is not installed, NDPAK remains true.
3-64 Memory Access
An eight-byte memory provides intermediate buffering betWeen the lOP and the data electronics. Access to memory,
from either the station electronics or the controller, is controlled by a priority flip-flop, MSTA, and a memory clock
cycle control, MCLK.
STATION ACCESS. The station access request signal,
MARS, is driven by either WMAR, the write memory access
request, or RCHP, the read access request. Assuming that
the controller is not making a request, MARS sets MSTA
true. MCLK is also set, which starTs the memory clock
cycle:
MARS
WMAR MCCA + RCHP NRCPA
NMFUL
During write operations, MARS in inhibited if there are no
bytes in memory. During read operations, MARS is inhibited
if memory is full:
The address of the memory location is controlled by the
mode signals: memory to controller, MMTC; memory to
buffer regi ster, MM TB; controller to memory, MCTM; or
buffer register to memory, MBTM:
MMTB
MSTA WRITE
MBTM
MSTA READ
MCTM
MCON WRITE
MMTC
MCON READ
The memory address comes from either the write memory
register, when loading bytes into memory from the buffer
-register or the controller data lines, or from the read memory register, when loading either the buffer register or the
controller data lines.
The read and write address registers are each three-bit
binary counters that are incremented each time a read or
write memory access cycle is completed:
MADO
+ MW03 (MBTM + MCTM)
+ MR03 (MMTB + MMTC)
MADl
+ MW02 (MBTM + MCTM)
+ MR02 (MMTB + MMTC)
MAD2
+ MW01 (MBTM + MCTM)
+ MROl (MMTB + MMTC)
S/MR03
NMR03
C/MR03
MRCL
S/MR02
NMR02
C/MR02
MR03
M/MSTA
MARS NMARC NDLAC
M/MCLK
MARS NDLAC + MARC NDLAC
S/MROl
NMROl
S/MCLK
NMCLK
C/MROl
MR02
C/MCLK
DLDP
MCLK drives a series of 50 ns delay lines which provide
the memory timing:
DLA2
MCLK delayed by 50 ns
DLA 1
DLA2 delayed by 50 ns
DLA2
DLA3 delayed by 50 ns
+ MARC MCON DLA1
+ MARS MSTA DLA1
DLAC
DLA1
DLAP
MCLK NDLA1
DLBP
DLAP delayed by 50 ns
DLCP
DLBP delayed by 50 ns
DLDP
DLCP delayed by 50 ns
DLA1 is held true until the request currently being processed is removed; this provides a time lapse for the memory
cycle to prevent timing conflicts.
MRCL
DLA1 ~MMTB + MMTC)
S/MW03
NMW03
C/MW03
MWCL
S/MW02
NMW02
C/MW02
MW03
S/MWOl
NMW01
C/MW01
MW02
MWCL
DLA 1 (MBTM + MCTM)
When the time interval DLDP is true, the data is written
into the memory if the cycle is a write cycle. If it is a
read cycle, the memory outputs are loaded into the buffer
register:
WRITE MEMORY
DLDP (MBTM + MCTM)
LOAD BUFFER REGISTER
XMEM
XMEM
WRITE MMTB DLDP NWLCC
3-107
SDS 901013
DLDP resets WMAR, if the cycle is a write access request
during write· operations, or sets RCPA, if the cycle is a read
access request during read operations:
C/WMAR
+ MMTB DLDP + ••• (Reset clock)
S/RCPA
NRCPA
C/RCPA
+ NRCPA DLDP MBTM + •••
Either WMAR being reset or RCPA being set allows MARS
to go false, after which DLA1 and DLAC are dropped:
DLA1
MARS MSTA DLA1 + •••
DLAC
DLA1
I
A four-stage counter is used to monitor the number of bytes
in the memory and to signal the controller or station when
service is required to load or unload the memory. The
counter MCCA, -B, -C, -D is a modified binary counter
operating as follows:
Stage (MCC X)
A
B
C
D
Bytes in Memory
0
0
0
0
None
0
0
0
1
0
0
0
DLA1 goes false and resets MSTA, which enables the controller to access memory:
0
MSTA
C/MSTA
MSTA DLA1
3
4
0
0
R!MSTA
2
5
0
6
0
0
7
8
The fall of DLA1 also increments the address registers:
MRCl
DLA1 (••• )
MWCL
DLA1 (••• )
After DLA1 goes false, NDLAC goes true to allow a new
access cycle to begin. NDLAC provides a time lapse in
the priority cycle to permit completion of the previous
cycle.
CONTROLLER ACCESS. The controller access request signal, MARC, is driven by the service request signal from the
controller:
MARC
SRIP NSRPD
SRPD
+ WRITE MFUL + READ MC01 NBMTC
The SRIP delay signal, SRPD, is normally used only in operations involving a selector lOP. During write operations,
SRIP is delayed if the memory has eight bytes in it; during
read, SRIP is delayed until there is more than one character
in the memory. Once MARC is allowed to go true, the
access process is identical with that of a station access.
At the time of DLCP, the acknowledge signal is sent to the
controller. During read operations, the signal is RDOL,
read data on-line. During write operations, the signal is
SRPA, SRIP acknowledge:
RDOl
+ DLCP MCON
+ SRIP RDOL
SRPA
NRDOL
The fall of SRPA indicates to the controller that the memory
has taken the data. RDOL is held true unti I the controller
acknowledges the data by releasing SRIP.
3-108
The counter is incremented by MWCL each time a byte is
loaded into the memory from either the controller or the
station. The counter is decremented by MRCL each time a
byte is read from the memory:
S/MCCA
NMCCA
C/MCCA
+ NMCCA MWCl
+ MCCA MCOl MRCL
S/MCCB
NMCCB MCCC
C/MCCB
+ MCCC MCCD MWCL
+ NMCCC NMCCD MRCL
S/MCC
NMCCC
C/MCCC
+ MCCD MWCL
+ NMCCD NMCOl MRCL
S/MCCD
NMCCD
C/MCCD
+ MCCA MWCL
+ NMC01 MRCL
MCOl
MCCA NMCCB NMCCC NMCCD
If a write operation is in progress and the memory contains
less than five bytes, a service request signal is sent to the
controller. If a read operation is in progress and the memory
contains more than four bytes, a service request is sent to
the controller:
BMTC
+ WRITE NMCCB
+ READ MCCB
+ •••
Figure 3-70 shows a timing diagram for the memory access
operation.
SDS 901013
10 NS--1
t---
SRIP OR WMAR OR RCHP~
-.J
---.J
MARC OR MARS
MCLM
MCLK
NDLA3
NDLA2
NDLAl
DLAP
DLBP
DLCP
DLDP
DLAl
NDLAC
(MSTA)
;
'---------------
MBTM, MCTM ETC
IL.... _ _ _ _ _ _ _ _ _ _ _ _
MAD1, 2,3
SRPA
IF NMSTA
{
MR01, MWOl ETC
RDOL
-------'
- - - - - - - C U R R E N T ADDRESS-----...........
I·---INCREMENTED
901013A.369
Figure 3-70. Memory Access (Controller and Station), Timing Diagram,
3-109
SDS 901013
Paragraphs 3-65 to 3-66
3-65 Clock Signal
Position
The master clock signal is derived from a 3.84 mc crystal
oscillator. The frequency is chosen so that the character
interval at 800 bpi may be divided evenly into 32 parts.
With this method, one clock cycle equals 39.0625 Ilin. of
tape.
Si nee the controller is capable of operati ng with anyone of
three different speed transports, 150 ips, 75 ips, or 37.5 ips,
the clock signal is available in three frequencies, produced
by a counter: 3.84 mc, 1.92 mc, and 0.96 mc. These frequencies are for the 150 ips, 75 ips, or 37.5 ips transports,
respectively. These frequencies are chosen so that 32 clock
cycles are equal to the specified distance between characters at 800 bpi. Thus~ in every case, one clock cycle is
equal to 39.0625 Ilin. of tape.
The c lock equations are these:
F384
3.84 mc oscillator output
S/F192
NF192
R/F192
F192
C/F192
F384
S/F096
NF096
R/F096
F096
C/F096
F192
ClOK
+ V150 F384
+ V075 F192
+ V037 F096
1.92 me
0.96 mc
3-66 Write Operations
WRITE DESKEW COUNTER. The write deskew counter is an
eight-stage binary counter with a variable reset state. The
counter provides the timing for the write logic, the write
deskew comparators in the station, and the clock signal for
the controller and station.
The counter is always running, the least significant stage,
WDC7, being clocked by the ClOK signal. The seven
least significant stages, WDC1 through WDC7, are used to
provide the write timing signals.
The most significant stage, WDC8, is used in deriving the
controller clock signal, ClKS.
The variable reset feature enables the counter to provide
the correct timing intervals for the three recording densities. As can be seen from the table below, the state
from which the counter is reset is always 177. The initial
state is 000 when recording at 200 bpi, is 122 at 556 bpi,
and is 140 at 800 bpi.
3-110
2
0
0
0
0
3
0
0
0
4
5
6
7
Description
1
last count
0
0
1
0
No station selected
0
0
0
0
200 bpi initial state
0
0
0
556 bpi initial state
0
0
0
0
800 bpi initial state
0
0
0
Write deskew interval
Reset state
The WDC counter reset terms are controlled by the density
switch setting of the station selected. If no station is
selected, the WDC counter resets on a combination of 200
bpi and 556 bpi settings. Since each clock period is
equivalent to 39.1 microinches of tape, the period of the
WDC counter is as follows:
Nominal Density Actual Density
(bpi)
(bpi)
Clock Cycles Distance
200
200
128
5000 Ilin.
556
556.5
46
1796 Ilin.
800
800
32
1250 Ilin.
The eighth stage, WDCS, toggles each time the WDC
counter resets during operations at 556 bpi, and remains
set at 200 or 800 bpi.
The state of WDC8 is used to determine the station and
controller clock frequency, ClKS:
ClKS
+ WDC8 WDC4 WDC3
+ NWDC8 WDC4 NWDC3
The interval WDC3 WDC4 has a period of 32 clock cycles.
During 200 bpi operations, there are 128 clock cycles each
WDC period; therefore, there are exactly four intervals of
ClKS per period. At 800 bpi there are 32 clock cycles each
WDC period, resulting in one ClKS interval per period.
At 556 bpi, the WDC period is 46 clock cycles. By using
WDC8 to alternately select the normal or complement side
of WDC3, the effective period of ClKS is 30.6 clock cycles.
With no station selected, the period of the WDC is 110 clock
cycles, and hence the period of ClKS averages 27.5 clock
cycles.
The density settings and the respective frequencies of ClKS
are given below:
.
ClKS Period
(Clock Cycles)
C lKS Frequency
Density
60 kHz
32
200
62.6 kHz
30.6
556
800
32
60 kHz
51.5"J
1
(
0 1 1 0 1 1 1 1
o 1 1 1 1 1 1
? -fft:*.
1 1 1 1 101
+
[
<
._.
o 1 1 1 1 010
o 0 1 0 1 o 0
:
1 1 1 1 110
I
~
o 1 1 1 1 o 1 1
o 0 1 0 1 1 1
#
#
&
&
o 1 1 1 1 1 00
o 0 1 1 000
@
@
o1
1 1 1 1
1 1
-
Only
o 0 000
1 o 1 o 1
1 o 1 1 0
1
1*
o 1 1 1 1 1 0 1
001 1 0 1 1
$
$
o 1 1 1 1 1 1 0
o 0 1 1 1
o1
*
*.
o 1 1 1 1 1 1 1
o 0 1 1 1 1 0
1 0
0 1 0 1 1 0 1 1
1 0
o1o1
1 0 1 1 0
o0
i
1 2 3 4 5 P
1 1 1 0 1 1 1
0 1 0 1 1 0 1 0
1 1
Blank
READ
3 4 5 6 7-
V
-~.,.... ~,.,'-
E
0 1
--- o
CHARACTER
BCDIC
WRITE
CHARACTER
READ
1 1 1 0
1 1 1
------ o
EBCDIC
BCDIC
WRITE
* These characters are only included in the 88 graphic
set; however, if they are sent, they wi 1\ be converted as
shown
I
o1
\'
,,'
ot
:
=
II
.--"..••..
>
/*
*These characters are only included in the 88 graphic
set; however, if they are sent, they wi \I be converted as
shown
tOn write only. 128 during read gives zero
tOn write only. 128 during read gives zero
Table 3-11. Sigma BCD-EBCDIC Conversion Chart
LEAST SIGNIFICANT DIGIT
I-
(5
HEXADECIMAL
0
1
2
3
4
5
6
7
8
0
1>
A
B
C
D
E
HT
F
G
J
K
L
M
N
NL
0
/
S
fs
T
si
U
V
W
,9
A
H
EOM
I
?
P
Q
R
X
Y
Z
B
C
D
E
F
)
[
<
$
(5
I-
z
«
~
!=;
Null
1
Z
0
v;
2
l-
~
-
ds
Vl
0
&
3
4
ss
0
1
2
3
4
5
6
7
8
9
1>
A
B
C
D
E
F
G
H
I
blank
(Continued)
3-134
1
$
*
]
;
6.
*
,
%
(T)
\
itt
ot
#
@
J
?
.
<
>
<
i
)
:
[
(
+
*
I
SDS 901013
Table 3-11. Sigma BCD-EBCDIC Conversion Chart (Cont.)
LEAST SIGNIFICANT DIGIT
HEXADECIMAL
5
6
7
I-
(5
0
1
2
3
4
5
6
7
8
9
A
B
C
0
&
&
J
K
L
M
N
0
P
Q
R
!
!
$
$
*
*
)
-
-
/
/
S
0
1
2
T
3
U
4
V
5
W
6
X
7
y
8
Z
9
,
,
*
#
#
0*
:
Ci
8
I-
Z
«
u
9
~
Z
~
A
V;
l-
1>
&
A
a
B
b
C
c
D
d
E
e
F
J
K
k
L
M
m
N
n
0
S
i
B
~
C
D
E
F
0
G
g
H
h
I
i
P
p
Q
R
q
r
%
F
;
;
-,
t::.
-+t+-
\
>
>
('I)
%
@
@
-
)
[
<
*
?
:
I
?
=
II
!
$
*
]
;
t::.
('I)
\
-tt+
-
/
T
t
U
w
X
x
Y
u
V
v
W
S
y
Z
z
:f
,
%
0
1
2
3
4
5
6
7
8
9
0*
#
@
:
>
I
1>
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
I
I
?
)
[
<
:$
&
J
J
K
K
L
L
M
M
N
N
0
0
P
P
Q
Q
R
R
!
$
*
]
;
t::.
-
/
S
S
T
T
U
U
V
V
W
W
X
X
Y
Z
Z
i
,
%
('I)
Y
\
-H+
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0*
#
@
:
>
Vl
0
I
f
]
E
I
CD
* Codes XI3AI, 17AI, IBAI, and IFAI are recorded and read back as BCD 10 1
NOTES:
The chart shows the BCD character that is recorded on tape for the EBCDIC code sent. If an EBCDIC character
is assigned, it is shown below the BCD character
1.
2.
The characters enclosed within the heavy lines are the standard SDS 62-graphic set
3. During read, only those codes and their appropriate characters that are enclosed in the heavy lines are 'sent to
the I/O system, regardless of the code that was sent by the computer
4.
See appendix A in the Sigma com'puter reference manuals for the functions of the control codes included in this
chart
3-135
SDS 901013
Paragraphs 3-71 to 3-72
<
Table 3-12. Sand JlChassis Glossary of Terms (Cont.)
3-71 GLOSSARY OF TERMS
.(
3-72 Sand..t1 Chassis Terms
Table 3-12 is a glossary of terms for chassis Sand U.
Table 3-12. 5 and ~haSSis Glossary of Terms
Term
Description
Term
Description
CLKS
Station clock (from controller)
CLOCKS
Write toggle register clock
(from data)
DBSC
Device busy signal (to
controller)
DBSS
Device busy signal
.22 sec O/S
Load interlock time de lay
.8 sec O/S
Rewind completed delay
In the following,
n = 0-7, P
01SS
Station state counter in state 1
DJAnSD
02SS
Station state counter in state 2
Deskew jumper A to channe I
n (to data)
03SS
Station state counter in state 3
DJAnS
Deskew jumper A to, channe I
n (to data)
06SS
Station state counter in state 6
DJBnSD
07SS
Station state counter in state 7
Deskew jumper B to channel
n (to data)
OSCTS
Station state counter in state 0
DJBnS
45SS
Station state counter in state 4
or 5
Deskew jumper B to channel
n (to data)
DJCnSD
Deskew jumper C to channel
n (to data)
DJCnS
Deskew jumper C to channel
n (to data)
DPRSD
Device proceed si gnal (to
controller)
DPRS
Device proceed si gnal
DRDC
Device ready si gnal (to
controller)
DRDS
Device ready signal
DSOTH2S
Device select lines 0, 1, and
2 and unit select switch positi ons 0, 1, and 2 match
DSOTH5S
Device select lines 0-5 and
unit select switch positions
0-5 match
DS3TH5S
Device select lines 3-5 and
unit select switch positions
3-5 match
DSCS
Device select lines 0-7 and
unit select switch positions
0-7 match
ACMS
Actuate motor signal
AIOCDS
Acknowledge interrupt signal
(from controller)
ALLINT
All transport interlocks closed
ARGC
Address recogni zed by stati on
(to controller)
ATNS
Attention signal latch
ATOC
HIO operation starting
ATTENTION CONTR
Attention pushbutton pressed
AUTC
Station in automatic mode
(to controller)
AUTO
Station in automatic mode
BACKUPS
Return to loadpoint after rewind
BOTH
Beginning of tape signal
BOTH DELAY
Delay prior to setting backups
BOTSD
Addressed station at beginning
of tape
BRC
Rewind operation completed
BRR
Ready relay enable signal
DSCDS
Buffered DSCS
BSL
Load cycle - tape now in
chambers
DSGC
Device selected si gnal (to
controller)
BTSC
Beginning of tape signal for TDV
(to controller)
DSGS
Device selected si gnal
CLFS
Interrupt latch clear signal
DSLS
CLKGS
Transport clock
Device selected clock {from
controller}
~
(Continued)
3-136
SDS 901013
{
Table 3-12. S andYc'hassis Glossary of Terms (Cont.)
Term
Table 3-12. S
Description
<
and~Chassis Glossary of Terms (Cont.)
Descri pti on
Term
DSSS
Device selection gate enable
(from controller)
INPC
Interrupt pendi ng duri ng TDV
(to controller)
DSTS
Device selection time (from
controller)
INTB
Interlock B closed (file
chamber)
DVxC
Device select I ine x (from controller) x = 0-7
INTC
Interrupt si gnal set (to
controller)
DVxDS
Device select I ine x driver
INTS
Interrupt signal set
DVxRS
Device select I ine x receiver
INTDS
Interrupt si gnal set, buffered
EDR
Erase head power
LATOS
Halt signal being processed
ENDC
End operation signal (from controller)
LINGS
Latch interrupt signal
LOAD
Load tape cycle in progress
ENDS
End operation signal
LOAD INHIBIT
ENTC
End of tape signal (to controller)
Prevent loading if door not
raised
ENTS
End of tape signal
LOAD OFF
Load cycle not in progress
ERSS
Erase operation in process
LOADS
Load button pressed
FAST
Move capstan at high speed in
manual
LSPS
Transport is 37.5 ips unit
MAN
Station in manual mode
FAST RONS
Capstan moving at high speed
MANUAL ENABLE
FASTS
FAST pushbutton pressed when
capstan in motion
Station in manual and interlocks mode
NORMAL
FSnnS
Station read/write delay counter
(nn = 01-12)
Move capstan at normal speed
in manual
OPERA 1I0NAL CONTR
FCTS
Station connected to controller
Station is operational (from
transport)
FCTD
Buffered FC TS
OPRS
Station is operational
F DELAY
De lay interval to allow capstan
to stop from high speed
OSCLKA
Station clock (in manual mode)
OSCLKB
Station clock (in manual mode)
FS1S
Station state counter is in stage 1
RASOBOTS
Erase order or at BOT
FS2S
Station state counter is in stage 2
RASS
Erase order being received
FS3S
Station state counter is in stage 3
RDAMPxS
FWD
Move capstan forward in manual
Read ampl ifier output channel x
FWDS
Forward button pressed
RDAMPxSD
GNTS
Gate unit address to device address I ines if interrupt set
Read amplifier output (to data
chassis)
READY B
Ready relay energized
HLTDC
Halt signal being received (from
controller)
RESETFR
Reset FWD and REV manual
when START pushed
HLTDS
Halt signal being received
RESETOS
RESET button pressed
HSPS
Transport is a 150 ips unit
RESETS
RE SE T button pressed
ICRS
Initialize delay counter
REV
INGS
Interval during which interrupt
may be set
Move capstan reverse in
manual
(Continued)
3-137
SDS 901013
Paragraph 3-73
Table 3-12. S
<
and~hassis Glossary of Terms (Cont.)
1
Table 3-12. Sand Jd"Chassis Glossary of Terms (Cont.)
Description
Term
Description
Term
REVS
Move capstan in reverse in
automatic
WLRCS
Write longitudinal check
character interval
REWI
Rewind indicator signal
WN1S
REWS
Rewind signal in automatic
Rewi nd and interrupt order
(from controller)
ROFS
Rewind off-I ine order
WN2S
Rewind off-line order (from
controller)
RSTS
Station reset signal (from
controller)
WNDC
Addressed device is rewinding
RVRS
Reverse si gnal (from controller)
RVSS
Reverse operati on in progress
SAS
Load cycle, primary safety
interval
SASB
load cyc Ie, secondary safety
interval
SEll
Buffered FCTS signal
SElZ
Buffered FC TS si gna I
STARTS
START button pushed
SWOAx
Write deskew switch A, channel
x
SWOBx
Write deskew switch B, channel x
SWOCx
Write deskew switch C, channel x
TBDS
Delay counter has reached BOT
delay count
OOF
Delay counter has reached erase
delay count
Controller state counter,
phase 0
01F
Delay counter has reached read
delay count
Controller state counter,
phase 1
03F
De lay counter has reached
reverse de lay count
Controller state counter,
phase 2
OOU
Delay counter has reached stop
delay count
Controller state counter,
subphase 0
OlU
Delay counter has reached write
delay count
Controller state counter,
subphase 1
02U
Controller state counter,
subphase 2
progress
03U
Write deskew counter output
stage 1 (from data)
Controller state counter,
subphase 3
OlFOOU
Order input state
01F01U
Order output state
01F02U
Receive and decode order
01F03U
Wait for device proceed (DPR)
signal
03FOOU
Terminate read/write operatior1
TERS
TRDS
TRVS
TSPS
TWRS
TSHS
WDC15
no,
Write deskew counter output
stage 2 (from data)
WEC35
Write deskew counter output
stage 3 (from data)
WDRx
Wri te head dri ver, channe I x
WENS
Write enable signal .\
-
Addressed device is fi Ie
protected
WRxS
Write data, channe I x (from
controller)
WRDE
Write driver toggle regi ster
enable
WRTS
Write operation in progress
3-73 Y and Z Chassis Terms
Table 3-13 is a glossary of terms for chassis Y and Z.
Table 3-13. Y and Z Chassis Glossary of Terms
Term
510, or HIO operation in
WDC25
,
WPMC
Descri ption
(Continued)
3-138
SDS 901013
Table 3-13. Y and Z Chassis Glossary of Terms (Cont.)
Term
Description
Clock signal for FCN
CFCR
Clock signal for FCR
CFCRX
Clock signal for FCR
CFCRY
Clock signal for FCR
CFF1
Clock signal for FF1
CFF1X
Clock signal for FF1
CFF2
Clock si gnal for FF2
CFIO
Clock signal for FlO
CFlE
Clock si gnal for FlE
CFPET5
Clock si gnal for FPET5
CFRS
Clock si gnal for FRS
CFRSX
Clock signal for FRS
CFSCM
Clock signal for FSC
CFU1
Clock signal for FUl
CFU1X
Clock signal for FUl
CFU1Y
Clock signal for FU1
CFU1Z
Clock signal for FU1
CFU1ZA
Clock si gnal for FUl
CFUZ
Clock signal for FUZ
CFUZX
Clock signal for FUZ
CFUZY
Clock signal for FUZ
CFU3
Clock signal for FU3
CFUNX
Clock signal for FUN
CIH
High priority interrupt signal
CIl
low priority interrupt signal
ClB
Miscellaneous logic terms
(XX == 02-07)
Clock si gnal for FRSD and
FRSDD
ClK
Buffered FSD signal (for status
transfer logic)
General clock signal (from
data electronics)
CORE
Correctable read error
CRD
Controller ready for order
CSH
High priority service request
CSl
low priority service request
CSLI
Service request inhibit (100
nsec delay of NFSC)
CTl
Control order being
interpreted
Data enab Ie, read mode, controller to lOP
AlOR
Acknowledge interrupt signal
from lOP
AlOC
Acknowledge interrupt si gna I,
miscellaneous logic
AlOM
Acknowledge interrupt signal,
miscellaneous logic
AlOCD
Acknowledge interrupt signal,
miscellaneous logic
ARG
Address recognized by station
ASCR
Acknowledge service call signal
from lOP
ASCM
Acknowledge service call logic,
m i sce II aneous
ASCB
Acknowledge service call logic,
miscellaneous
AIO
Initiates HIO operation in
controller
AUT
Station in automatic mode (from
station)
AVI
Available signal input (from
preceding controller)
AVO
Available signal output (to
succeedi ng controll er)
AVIR
Available signal receiver (for
controller use)
AVOD
Available signal driver (from
controller logic)
BAND XX
Miscellaneous logic terms
(XX == 01-32)
BFSD
Description
Term
CFCNY
ABD
BOR XX
Table 3-13. Y and Z Chassis Glossary of Terms (Cont.)
BMT
Data electronics memory needs
service (from data)
BOT
Addressed station at beginning
of tape (from stati on)
BSYC
Controller busy processing an
order
BTS
Beginning of tape response signal
for TDV (from station)
CFCNX
Clock signal for FCN
(Conti nued)
3-139
SDS 901013
Table 3-13. Yond Z Chassis Glossary of Terms (Cont.)
Term
Table 3-13. Y and Z Chassis Glossary of Terms (Cont.)
In the following,
n = 0-7, P
Description
Term
Description
DVxC
DVxD
DAnD
Data line n to/from lOP and
controller
Data line n to driver
Device address I ine (to/from
station)
Device address line driver
input
DVxR
Device address line receiver
output
ED
End data line (to/from lOP
and controller)
EDB
Less than 4 bytes in data
memory at long gap
EDD
End data line driver
EDR
End data line receiver
END
End operation signal to station
ENT
End of tape signal from station
ES
End service line (to/from lOP
and controller)
ESR
End service signal
EXTCLK
Clock signal (to PET panel)
EXTRES
Reset signal (to PET panel)
FCD
AIO being processed
FCN
Channe I end si gnal storage
FCR
Set correction si gnal storage
FD1
Device in operation address bit 1
FD2
Device in operation address bit 2
FD3
Device in operation address bit 3
FFl
Phase counter stage 1
FF2
Phase counter stage 2
FlO
Interrupt si gnal storage
FLE
Incorrect length error storage
DAn
DAnR
Data line n to receiver
DAnC
Data line n to/from station
and controller
DACFD
Devi ce address compares wi th
device in operation
Addressed device to be given
halt signal
DACFDD
DAI5
Device number transferring to
FR lines
DAI6
Device number transferring to
FR lines
DAI7
Device number transferring to
FR lines
DATE
Data error signal (from data)
DBS
Device busy signal (from station)
DCA
Controller address recognized
DCA47
Station address recognized
In the following,
x = 0-7
DFDx
Data lines have octo I code of x
Device in operation is octal x
DaR
Data/order line to/from lOP
DORD
Data/order line driver
DORR
Data/order line receiver
DPR
Device proceed si gnal (from
station)
DPRNWN
Device proceed, not rewi nd
order
DRD
Device ready signal (from
station)
DDAx
DSG
Device selected si gnal (from
station)
FOl
Order code register stage 1
(MSB)
DSL
Device selected clock signal
(to station)
F02
Order code register stage 2
F03
Order code regi ster stage 3
DSS
Device selection gate enable
(to station)
F04
Order code regi ster stage 4
DST
Device selection time (to
station)
F05
Order code register stage 5
(LSB)
(Continued)
3-140
SDS 901013
Table 3-13. Yond Z Chassis Glossary of Terms (Cont.)
Term
Table 3-13. Yond Z Chassis Glossary of Terms (Cont.)
Description
Term
Descri ption
FPE
Write protect violation occurred
GBS
FPETl
PET panel record counter, stage
1 (MSB)
GDA
FPET2
PET panel record counter, stage
2
GFD
FPET3
PET panel record counter, stage
3
Gate active device number
to device lines except during
an FS response
GFI
PET panel record counter, stage
4
Gate interrupt latch to highest priority device during Ala
GNT
PET panel record counter, stage
5 (LSB)
Gate all interrupting devices
to interrupt latch in Ala
GNDXXX
Ground signal
GRDXXX
Ground signal
HIO
HIO signal line (from lOP)
HLTD
Halt signal to be sent to
station
FPET4
FPET5
Controller now busy
Gate data lines to device
I ines during FS
FPET6
PET panel byte counter, stage. 6
(MSB)
FPET7
PET panel byte counter, stage 7
FPETa
PET panel byte counter, stage a
(LSB)
HPI
High priority interrupt level
FPETIE
Error insertion signal in PET
operations
HPS
High priority service level
FRx
Function response line (to lOP)
IC
Interrupt line (to lOP)
FRxD
Function response line driver
ICD
Interrupt line driver
FRS
Erase order storage
INx
Interrupt latch, stati on x
FRSD
Request strobe delay 1
INC
Initialize controller signal
FRSDD
Request strobe delay 2
INI
Initialize controller signal
FS
Function strobe (from lOP)
INP
Addressed device has interrupt pending
FSC
Controller connected to lOP for
service
INT
Device interrupt is occurring
FSCC
Controller connected for service
lOR
Input/output signal line (to/
from lOP)
FSCL
Extend RSAR until FSC is reset
lORD
Input/output signal line driver
FSCM
Controller connected to PET for
service
IVa
Invalid order received in
controller
FSD
Function strobe drive
LG
FSL
Function strobe leading signal
(to lOP)
Long gap detected by data
electronics
LIH
High priority interrupt latch
FSLD
Function strobe leading signal
driver
LIL
Low priority interrupt latch
FSA
Function strobe recei ver
LIRS
Inhibit new request strobe
unti I disconnected
FU1
Subphase counter, stage 1
LSH
FU2
Subphase counter, stage 2
High priority service request
latch
FU3
Subphase counter, terminal order
next
LSL
Low priority service request
latch
FUN
Unusual end storage
MAN
Controller operating from PET
(Conti nued)
3-141
SDS 901013
Table 3-13. Y and Z Chassis Glossary of Terms (Cont.)
Term
Table 3-13. Y and Z Chassis Glossary of Terms (Cont.)
Term
Description
Description
RSARC
Request strobe acknowledge
line receiver
RSAR
Request strobe acknowledge
signal
RSD
Request strobe signal
RSDD
Request strobe signal delayed
RST
Controller reset si gna I
RVRC
Reverse operation in progress
(to station)
RWFIN
Read/write data transmission
completed
SC
Service call line (to lOP)
SCD
Service call line driver
SIO
Start input/output I ine (from
lOP)
SIOR
Start i nput/output line
receiver
SPF
Space record forward operation in progress
SPR
Space record reverse operation in progress
SRIP
Memory access request (to
data)
Parity signal for comparison in
PET
SRIPA
Memory access request acknow ledge (from data)
RxB
Data I ine x from data electronics
(x = 0-7, P)
SWAx
Address code switch x
TDV
Test device line (from lOP)
RxBA
Data I ine x to PET (x
TDVR
Test device line receiver
RASC
Erase si gnal (to station)
TIO
Test controller line (from lOP)
RATE
Rate error signal (from data
chassi s)
TIOR
Test controller line receiver
RDP
Read data on line (from data
chassis)
TM
Tape mark has been detected
(from data)
READ
Read operation in progress
TSH
TIO, SIO, or HIO operation
in progress
RES
Genera I reset si gna I (to data
chassis)
TTSH
TDV, TIO, 510, or HIO operation in progress
RESIN
SIO reset signal to data chassis
WDC45C
Clock signal from data chassis
REV
Reverse operation in progress
WNl
RS
Request strobe I ine (to lOP)
Rewind and interrupt code in
order register
RSDA
Request strobe line driver
WN1C
RSA
Request strobe acknowledge line
(from lOP)
Rewind and interrupt code to
station
PC
Check parity on transmitted byte
PETCx
PET counter, stage 0-7
PETCD
PET counter reset
PETCMPA
Strobe pulse to compare data in
PET
PETCTR
PET data control signal
PETDA 1
PET data control si gnal
PETDA2
PET data control signal
PETDA3
PET data control si gnal
PETFB
Write/read a fixed number of
records
PETPATA
PET data control signal
PETPATB
PET data control signal
PETPATC
PET data control signal
PETPATD
PET data control signal
PETPATX
PET data control signal
PETRP
Repeat cycle signal from PET
PETST
Start si gnal from PET
PETWDx
Data signal for comparison in
PET
PETWDP
Parity signal from PET
PETWDPA
= 0-7,
P)
(Contmued)
3-142
SDS 901013
Table 3-13. Y and ZChassis Glossary of Terms (Cont.)
WN2
Rewind off-line code in order
register
WN2C
Rewind and interrupt code to
station
WN102
Rewind code in order register
WND
Station in rewind
Y
Station in write protect mode
Write operation in progress (to
data)
WRITE
Table 3-14. V and W Chassis Glossary of Terms (Cont.)
Description
Term
WPM
Paragraph 3-74
Description
Term
ACVC
Assembly period counter state
ACVD
Assembly period counter state
ACVE
Assembly period counter state
ACVF
Assembly period counter state
ACVG
Assembly period counter state
ACVH
Assembly period counter state
ACVI
Assembly period counter state
ACVJ
Assembly period counter state
WRT
Write operation in progress
ACVK
Assembly period counter state
WRTC
Write operation si gnal (to
station)
ACVL
Assembly period counter state
ACVM
Assembly period counter state
WTM
Write tape mark operation in
progress
ACVN
Assembly period counter state
ACVP
Assembly period counter state
APOl
Assembly period counter, stage
1 (MSB)
AP02
Assembly period counter,
stage 2
AP03
Assembly period counter,
stage 3
AP04
Assembly period counter,
stage 4
AP05
Assembly period counter,
stage 5
AP06
Assembly period counter,
stage 6
AP07
Assembly period counter,
stage 7
AP08
Assembly period counter,
stage 8
AP09
Assembly period counter,
stage 9
AP10
Assembly period counter,
stage 10 (LSB)
APOA
First bit detector for assembly
peri od counter
APOB
Assembly period counter clock
enable
APCZ
Assembly period counter reset
3-74 V and W Chassis Terms
Table 3-14 is a glossary of terms for chassis V and W.
Table 3-14. V and W Chassis Glossary of Terms
Term
Description
AC02
Assembly period counter count
AC03
Assembly period counter count
AC04
Assembly period counter count
AC05
Assembly period counter count
AC06
Assembly period counter count
AC07
Assembly period counter count
AC08
Assembly period counter count
AC09
Assembly period counter count
AC10
Assembly period counter count
ACll
Assembly period counter count
AC12
Assembly period counter count
AC13
Assembly period counter count
AC14
Assembly period counter count
AC15
Assembly period counter count
ACVA
Assembly period counter state
ACVB
Assembly period counter state
ASRO
ASRl
Assembly register, bit position
o (MSB)
Assembly register, bit position 1
(Continued)
3-143
SDS 901013
Table 3-14. V and W Chassis Glossary of Terms (Cont.)
Term
Table 3-14. V and W Chassis Glossary of Terms (Cont.)
Description
Term
Descri pti on
BCDIC code for zero
ASR2
Assembly register, bit position 2
BZER
ASR3
Assembly register, bit position 3
In following terms, n=O, 1,2,3,4,5, P
ASR4
Assembly register, bit position 4
CnB1
ASR5
Assembly register, bit position 5
Channel n bit crowdi ng counter,
stage 1
ASR6
Assembly register, bit position 6
(lSB)
CnB2
Channel n bit crowdi ng counter,
stage 2
ASRP
Assembly register, bit position
parity
CnB3
Channel n bit crowding counter,
stage 3
BAMP
BCDIC code for ampersand
CnBC
Channel n bit crowding counter,
output
BBlN
BCDIC code for blank
CnCl
Channel n clock signal
BDSH
BCDIC code for dash
CnD1
Channel n deskew counter, stage 1
BMTC
Memory empty signal (to controller)
CnD2
Channel n deskew counter, stage 2
BaTS
Beginning of tape si gnal (to
controller)
CnD3
Channel n deskew counter, stage 3
BROO
Buffer register stage 0
CnD4
Channel n deskew counter, stage 4
BR01
Buffer register stage 1
CnD5
Channel n deskew counter, stage 5
BR02
Buffer register stage 2
CnDZ
Channel n deskew counter reset
BR03
Buffer register stage 3
CnJ1
Channel n deskew i umper, stage 1
BR04
Buffer register stage 4
CnJ2
Channel n deskew jumper, stage 2
BR05
Buffer regi ster stage 5
CnJ3
Channel n deskew jumper stage 3
BR06
Buffer register stage 6
CnPl
Channe I n peak detector stage 1
BR07
Buffer register stage 7
CnP2
Channel n peak detector, stage 2
BR08
Buffer register stage 8
CnP3
Channel n peak detector, stage 3
BR09
Buffer register stage 9
CnP4
Channel n peak detector, stage 4
BR10
Buffer regi ster stage 10
CnP5
Channel n peak detector, stage 5
BR11
Buffer register stage 11
CnP6
Channel n peak detector, stage 6
BRAE
Buffer register stages 0-7 erase
signal
CnPQ
Channel n peak qualified signal
CnPT
Channe I n peak transfer signal
"
'
BRCl
Buffer register 'shift clock
CHNn
Channel n read amplifier signal
BRIO
Buffer register stage 0 mark input
ClKS
Clock si gnal (to station)
BRIl
Buffer register stage 1 mark input
ClOKl
Clock si gnal
BRI2
Buffer register stage 2 mark input
ClOK2
Clock si gnal
BRI3
Buffer register stage 3 mark input
ClOK3
Clock signal
BRI4
Buffer register stage 4 mark input
DAOR
Data line bit 0 (from controller)
BRI5
Buffer register stage 5 mark input
DA1R
Data line bit 1 (from controller)
BRI6
Buffer register stage 6 mark input
DA2R
Data line bit 2 (from controller)
BRI7
Buffer regi ste r stage 7 mark input
DA3R
Data Ii ne bit 3 (from controller)
BSlS
BCDIC code for slash
DA4R
Data line bit 4 (from controller)
(Continued)
3-144
SDS 901013
Table 3-14. V and W Chassis Glossary of Terms (Cont.)
Term
Table 3-14. V and W Chassis Glossary of Terms (Cont.)
Descri pti on
Term
Descri pti on
F02C
Command register bit 2 (from
controller)
FICL
Data finished signal clock (from
controller)
FINC
Data finished signal - controller
FINS
Data finished signal (to control ler}
H001-H038
Miscellaneous jumpers in data
logic
LCRO
Longitudinal check character
register, bit 0
LCR1
Longitudinal check character
register, bit 1
LCR2
Longitudinal check character
register, bit 2
LCR3
Longitudinal check character
register, bit 3
LCR4
Longitudinal check character
register, bit 4
LCR5
Longitudinal check character
register, bit 5
Device proceed si gnal (from station
to controller)
LCRP
Longitudinal check character
register, bit P
DWTM
Write tape mark mode of operation
LCRZ
Longitudinal check register reset
EAMP
EBCDIC code for ampersand
MACL
EAP1A
End of assembly period, first clock
Memory character counter, stage
A clock
EAP1B
End of assembly period, first clock
MADO
Memory character address, bit 0
EAP2
End of assembly period, second
clock
MAD1
Memory character address, bit 1
MAD2
Memory character address, bit 2
DA5R
Data line bit 5 (from controller)
DA6R
Data line bit 6 (from controller)
DAlR
Data line bit 7 (from controller)
DATE
Data error (to controller)
DBCD
BCDIC mode of operation
DBIN
Binary mode of operation
DEN2
200 bpi density selected
DEN5
556 bpi density selected
DEN8
800 bpi density selected
DLA1
Delay signal in memory access logic
DAL2
Delay signal in memory access logic
DLAC
Delay signal in memory access logic
DLAP
Delay pulse for memory access
DLBP
Delay pulse for memory access
DLCP
Delay pulse for memory access
DLDP
Delay pulse for memory access
DPAK
Packed mode of operation
DPRS
EAPA
End of assembly period, first clock 200 bpi
MARC
Memory access request controller
EAPB
End of assembly period, first clock 556 bpi
MARS
Memory access request - data
MBCL
EAPC
End of assembly period, first clock 800 bpi
Memory character counter, stage
B clock
MBTM
EBLN
EBCDIC code for blank
Transfer control, buffer regi ster
to memory
EDBC
End data signal (to controller)
MCOl
One character in memory
EDSH
EBCDIC code for dash
MCCA
EZER
EBC DIC code for zero
Memory character counter, stage
A
F096
960 kHz frequency clock signal
MCCB
Memory character counter, stage
B
F192
1920 kHz frequency clock si gnal
MCCC
F384
3840 kHz frequency clock si gnal
Memory character counter, stage
C
(Conti nued)
3-145
SDS 901013
Table 3-14. V and W Chassis Glossary of Terms (Cont.)
Term
Table 3-14. V and W Chassis Glossary of Terms (Cont.)
Description
Description
Term
MCCD
Memory character counter, stage D
MSTA
MCCl
Memory character counter, stage C
clock
Memory be i ng accessed by data
electronics
MW01
Write memory character address,
bit 1
MW02
Write memory character address,
bit 2
MW03
Write memory character address,
bit 3
MWCl
Write memory character address clock
OPER
Operate mode, read or write, not
tape mark
MClK
Memory access cycle enable
MClM
Mark input to MClK
MCON
Memory beingaccessed by controller
MCTM
Transfer control, controller to
memory
MDCl
Memory character counter, stage D
clock
MFUl
Eight characters in memory
MINO
Memory input signal, bit 0
PACl
Parity error register clock
MIN1
Memory input signal, bit 1
PARO
MIN2
Memory input signal, bit 2
Previously assembled character
register, bit 0
MIN3
Memory input signal, bit 3
PAR1
Previously assembled character
register, bit 1
MIN4
Memory input signal, bit 4
PAR2
MIN5
Memory input signal, bit 5
Previously assembled character
register, bit 2
MIN6
Memory input signal, bit 6
PAR3
MIN7
Memory input signal, bit 7
Previously assembled character
register, bit 3
MMTB
Transfer control, memory to buffer
register
PAR4
Previously assembled character
regi ster, bit 4
MMTC
Transfer control, memory to
controller
PAR5
Previously assembled character
register, bit 5
MOUO
Memory output si gnal, bit 0
PARP
Previously assembled character
register, parity
MOUl
Memory output si gnal, bit 1
PARE
Parity error storage register
MOU2
Memory output si gnal, bit 2
PCHO
MOU3
Memory output signal, bit 3
Pack mode character counter,
state 0
MOU4
Memory output si gnal, bit 4
PCH1
MOU5
Memory output si gnal, bit 5
Pack mode character counter,
state 1
MOU6
Memory output si gnal, bit 6
PCH2
Pack mode character counter,
state 2
MOU7
Memory output si gnal, bit 7
PEVN
MROl
Read memory character address,
bit 1
Parity of buffer register bits 2-7
is even
PODD
MR02
Read memory character address,
bit 2
Parity of buffer register bits 2-7
is odd
RATE
Rate error occurred
MR03
Read memory character address,
bit 3
RBDO
Deskewed read data output, bit 0
MRCl
Read memory character address clock
RBD1
Deskewed read data output, bit 1
RBD2
Deskewed read data output, bit 2
(Conti nued)
3-146
SDS 901013
Table 3-14. V and W Chassis Glossary of Terms (Cont.)
Term
Table 3-14. V and W Chassis Glossary of Terms (Cont.)
Description
Term
,
Description
,
,
RBD3
Deskewed read data output, bit 3
TMCl
Tape mark detect clock
RBD4
Deskewed read data output, bit 4
TMKD
Tape mark has been detected
RBD5
Deskewed read data output, bit 5
TMRK
Tape mark signal to controller
RBDP
Deskewed read data output, pari ty
V037
Transport in operation is 37.5 ips
RBDC
First deskewed bit in character has
arrived
V075
Transport in operation is 75 ips
V150
Transport in operation is 150 ips
RCCl
Read character present acknowledge
clock
WBCD
Write BC DIC code characters
RCHP
Buffer register ready for transfer to
memory
WBIN
Write bi nary code characters
WCCl
Write control logic clock
RCPA
Buffer register ready signal acknowledge
WCDO
Write data cable driver (to
station), bit 0
RCPD
Buffer register ready signal delay
WCD1
RDOl
Read data on-line (to controller)
Write data cable driver (to
stati on), bit 1
READ
Read mode in operati on
WCD2
Write data cable driver (to
stati on), bi t 2
READE
Read mode signal (from controller)
WCD3
RES1
General reset signal
Write data cable driver (to
station), bit 3
RES2
Genera I reset si gna I
WCD4
RES4
General reset signal
Write data cable driver (to
stati on), bi t 4
RESC
General reset signal (from
controller)
WCD5
Write data cable driver (to
stati on), bit 5
RESN
SIO reset si gnal (from controller)
WCDP
Write data cable driver (to
station), parity
RETM
Reset signal composed of general
and SIO reset
WD14
Write deskew counter states
140-147
RlCC
Longitudinal check character is to
be read
WD16
Write deskew counter state 163
RWFIN
Data finished signal (from
controller)
WDC1
Write deskew counter, stage 1
(MSB)
RXF1
First character transferred from
assembly register
WDC2
Write deskew counter, stage 2
WDC3
Write deskew counter, stage 3
WDC4
Write deskew counter, stage 4
WDC5
Write deskew counter, stage 5
WDC6
Write deskew counter, stage 6
WDC7
Write deskew counter, stage 7
(lSB)
RXF2
Second character transferred from
assembly register
SHF1
Pack mode shift counter, stage 1
SHF2
Pack mode shift counter, stage 2
SHGP
Short gap reached
SRIP
Controller wants access to memory
WDC8
SRPA
Controller access request acknowledge
Write deskew counter, stage 8
(556 only)
WDFL
Write deskew counter state 177
SRPD
Controller access request delay
WDHF
Write deskew counter state XX7
TMCH
Assembly register contains tape
mark character
WDMR
Write deskew counter state 143
(Conti nued)
3-147
SDS 901013
Table 3-14. V and W Chassis Glossary of Terms (Cont.)
Table 3-14. Vand W Chassis Glossary of Terms (Cont.)
Term
Description
Term
Description
WDWI
Wri te deskew counter states
170-177
XMI2
Miscellaneous jumper in memory
input transfer
WENA
Write control logic enable signal
XMI4
WENB
Write control logic enable follower
Miscellaneous jumper in memory
input transfer
WFIN
Last data character to be written
XMI6
Miscellaneous jumper in memory
input transfer
WLCC
Longitudinal check character to be
written
XPAK
Transfer data in packed code to
write dri ver
WMAR
Memory access request, write mode
XTMC
WMCL
Memory access request clock
Transfer tape mark code to buffer
regi ster
WNTME
Wri te, not tape mark mode (from
controller)
XWIO
Miscellaneous jumper in write
data transfer
WPAK
Write packed code characters
XWl1
Miscellaneous jumper in write
data transfer
WRT1
Write mode
Write mode
ZARP
Parity of assembly register is odd
WRT2
Write mode (from controller)
ZARW
WRITE
Parity of assembly register (bits
0, 1, and 2) is odd
XASR
Transfer assembly register to buffer
register
ZARY
Parity of assembly register (bits
3, 4, and 5) is odd
XBCD
Transfer data in BCDIC code to
write drivers
ZBAP
Parity of buffer register (bits 0-5)
is odd
XBIN
Transfer data in binary code to
write drivers
ZBBP
Parity of buffer register (bits 2-7)
is odd
XLCC
Transfer longitudinal check code to
buffer register
ZBRW
Parity of buffer register (bits 0, 1,
and 2) is odd
XMEM
Transfer memory output character to
buffer register
ZBRX
Parity of buffer register (bits 3, 4,
,'and 5) is odd
XMIO
Miscellaneous jumper in memory
input transfer
ZBRY
Parity of buffer register (bits 2, 6,
and 7) is odd
3-148
Paragraphs 4-1 to 4-3
SDS 901013
SECTION IV
MAINTENANCE AND PARTS LIST
Table 4-1. Tools and Test Equipment (Cont. )
4-1 INTRODUCTION
This section contains information necessary to check out,
maintain, and repair the magnetic tape station and procedures necessary to remove and replace tape station components. Replaceable parts for the assembl ies and components used in the tape station are shown in assembly drawings
and parts list tables. They are identified by name on the
drawi ngs and by part number and circuit desi gnators in the
parts list tables.
Power and environmental requirements are given beginning
with paragraph 1-23. Table 4-1 Iists the special tools and
test equipment required to check out, maintain, and repair
the station. (Common tools such as pliers, screw drivers,
and soldering irons, however, are not listed.) Table 4-2
lists the cleaning agents and lubricants required to maintain and repair the station.
Table 4-1. Tools and Test Equipment
Name
Type
Controller, test
SDS model 7371
Gauge, pressure
2
0-15Ib/in.
(±2% at 8 Ib/in. 2 )
Gauge, thickness
Starrett No. 66
Gauge, vacuum
0-30 in. of water
(±2% at 16 in.)
Kit, special tool
SDS model 9298
Fixture, POPO alignment
SDS No. 131157
Tape, master speed
SDS No. 131956
Wrench, POPO adjustment
5DS No. 117569
Name
Overlay, PET
Type
5 DS No. 136975
Pliers, C-ring internal
(Circlip)
Power supply
0-40V, 300 mA
Spring scale, 500 grams
Chatillion 16 Eg
Tape, speed test and
alignment test
SDS No. 131956-001
Tachometer alignment
fixture
SDS No. T802896
Peripheral equipment
tester
SDS model 7901
Table 4-2. Cleaning Equipment
Item
Type
Alcohol
Denatured
Head cleaner brush
SDS approved
Tissues
Lint-free
4-2 CABLING
Modu Ie extenders (2)
SDS No. 117037
Module, switch ST28
S DS No. 128254
Multimeter
Triplett No. 630
Osc ill oscope
Tektronix model 545 with
model CA dual trace preamplifier or equivalent
The controller has two sets of cables for attachment to the
stations. The cables from the controller to the stations have
been kept as short as possible to increase response speed.
Table 4-3 lists the station interconnecting cables. Figures
4-1 and 4-2 show the cable interconnections.
4-3 MODULE LOCA nON
Figure 4-3 shows the module location for the magnetic tape
system.
4-1/4-2
SDS 901013
AS5W OPERATOR CONTROL '-PEL
UST WIIII£
133666
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13370.
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131297
131298
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105-
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124422
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AS" POWP OIST CHAS$I$
I.IST WI"!
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132368
132361
m
Figure 4-1. Station Interconnection Diagram
9010 13A. 408
4-3
SDS 901013
.....- - - - RELAY CHASSIS - - - - - - - - - - - .
REEL
SCR GATE CURRENT
HI SCR COMMAND
LO SCR COMMAND
RI-I
K4-16
K4-8
GNO
Fa BRAKE
SCR BIAS
GND
FL BIAS SCRCOM
33
0
36
0
KI- ~
K3-1O
1<1-4
40
43
0
0
47
0
J
T82M
I
3
14
18
Z6
1<1-7
t-+-t--K~S
BOTTOM
DOOR SW
34
FEED BAC-K
GND
10
0
Z2
0
-
- REWIND OFF
-CAP SPEED DELAY
-CAP SPEED
-CAP SPEED DELAY
- R READY
R3-2
-+4V
1(1 - 9
1<6-12
-INT""Z'
-FL PROT .ND
WRITE PERMIT
-WRITE CURRENT
-REW ON
-'NT ""I·
1(6-6
1<6-10
K4-12
IU-12
-
K2-4
-
R6-Z
1C6- 4
-+Z5V AC INT RELAY
1(6-9
1(3- I
- +25V WRITE CURRENT
-i25V
WRITE CURRENT
1<6-10
1<6-6
3ZU
38
~
-
IC2-t,
21
4
28
+25
- LOAD INHIBIT
-CAP SPEED
K4-4
K4-6
K3-8
1<3-16
K3-9
4
+25V RETURN
-REEL SERVO
k'-II
R7-Z
AC HOT
BRAKE POWER
BRAKE PWR TO ROY RLY
FX BIAS SCR COM
FL REV COM
FL FWD COM
FX PEV COM
FX FWD COM
FL BRAKE
--
K~e
k3-4
4Z
0
4!1
50
0
0
FILE TACH
flLf PROTECT S 6 F "
VAC
r- -- --
I INT-B·Slf
Z7~1
I
-
rB I
START
040
ATTENTION
08
06
I
I
PWR OUT PZ
START .ND
READY INO
8USY
INO
47
REWIND
LOAD
I
I
+25V
Lcw) POINT INO
REWIND IND
ATTN IND
fiLE PROT INO •
--~---~----+O36
PWR IN PI
I
---o--.. .
04
019
°ZI
OZ8
043
0'03
07
33
'----TOZ4
10
014
~
-
t:::+~ -----+-+-----+-<1-- :
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,
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I
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~
~
~
~
"
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~~--~------'
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21
__--+-+-IT
12
r-
116980
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53T
l:::!EV:::
I
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t
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..........
I.
LOAD INHIBIT
50
I
I
-1
-
-
-
-
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I
DSI
I,
1
, 111776 REF
I
I
....
I
I
I
I
.....
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I
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<~
II
tAlI
I
I
1 ~
47
45
38
f--9
L
~
7
40
....
~
TB5T
....-:-
~
16
30
34 o-Ifo----.--J
I
I
I
~
33
_ _ _I:......f~r--I-
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:I
r---:. ~
S4C
I
S5C
SIC INT-A-'
~~~~I------
Z6
'T
::;"L-/:=--=:::J
•
~~flr=~~~~~~':t=
Z8
~
+1-----1.------+--------1~Q~t-h"":"__+-,J ....-------ll-------+-~_o
~ '---~
~
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I
,,
,
--,
1rr=~~CAPSTAN
2 ~
r. - - - TACH
-- ,
--'--1----+-------11------+0-
~
I
I-~~
II
14()-i
-1--_ _ _ _--'
6
18
,
'---I-~tI
24
I
3
7
TACH
,..----- ~
S2C
r----I-i--I6
T83T
ZZ
POS PRES SW rA"O--II----+-------1I-------t-~Q
US COM
USO
USOFF
US 7
U S6
3
: ~
~-+----------~~~
.....:?-~
:I r--+
~ FIXED
,..--------+-t-1~
~----~~~
r-------~~~
J'Oo
-'"
i!
PZ06
....-41--+----+017
READY
-:;....:
:::-:::::~
L- __ __ __ __
OPERATOR CONTROL PANEL-t
RESET
:: -=tih
:::~~~~~----~
52f
S3f
S4F
S5F
I
TBIIC
r-
~T
1
I
T84T
Z4U
P209
ZZU
VAC MOTOR
L
~, JCRI
- -
I
1
ICRZ 1
-
....l
Tz
~134
-~~-----~
420-1---------'
~
~--------------------_r~~ ~
JUt
MAG TAPE TRANSPORT-------------------------~.I
L....j~--+012
018
oll
I
OZ6
ie--POWER DISTRIBUTION---I
CHASSIS
010
034
~----+O38
NOTES: I. USE THIS DRAWING WITH FIGURE 4-1.
2. REFERENCE SOS OWG: 13551O-1A
045
US5
U S4
US3
US2
US I
IN
Figure 4-2. Magnetic Tape Station
Wiring Diagram
POWE R FAILURE
OUT
90 108-iA. i'06
4-4
SDS 901013
Table 4-3. Station Interconnecting Cables
Cable
From
P205
U32
TBIN in relay chassis
Connects relay chassis to the station electronics
P206
U27
Operator control panel
Provides signal paths between the operator control panel
and the station electronics
P208
U24
Station transport casting
Provides signal paths between the station transport casting
(TB2-TB5) and the station electronics
P209
U22
Station transport drive electronics
Provides signal paths between the capstan and reel power
amplifiers and the station electronics
P223
S2
Read/write head
Provides si gnal paths between the read head and the station electronics
P224
527
Read/wri te head
Provides signal paths between the write head and the station electronics
32
31
ZT
24
To
J() 'B
AT RT
'0 11
{:
STATION
AT
FT
36
FT
36
AT
IT
12
43
10
CONTROllER
33
RT
P
206
2S
24
23
22
21
20
19
18
17
16
15
14
XT ST
RT
IT
AT
LT
ST
LT
15
11
18
10
10
14
AT LT
'0 36
36
LT
36
LT
36
LT AT
36 10
P XT
209 10
wr
HT
wr
HT
HT OT HT
AT
18
13
16
19
18
10
12
28
FT
36
FT
FT
15
FT
FT
FT
LT
35
FT
36
10
10
12
ZT
45
26
14
IT
P
11
208
FT
36
FT
35
LT
11
10
9
AT
BT
IT
FT
7
BT
6
FT
11
15
11
12
11
12
OT OT
BT
IT
14
14
11
13
IT
IT
FT
FT
12
IT
36
10
10
10
FT
39
FT
FT
FT
DT
26
12
12
16
IT
36
BT
IT
13
10
13
12
AT
'0
HT HT
ZT
HT
17
17
33
17
BT
BT
FT
BT
BT
HT
17
17
10
11
17
55
FT
BT
BT
BT
FT
11
11
11
18
11
26
AT
27
IT
IT
IT
FT
FT
ZT
36
IT
11
IT
10
18
12
26
12
.45
IT
36
IT
IT
FT
ZT
11
15
12
.45
V
FT
15
AT
15
14
FT
36
10
28 '0
XT ZT
Function
AT
35
FT
36
IT
BT
11
BT
lB
IT
71
11
AT IT
AT IT
AT
11
10
17
LT
IT
10
11
FT
41
10
24
FT
71
FT
36
IT
IT
FT
CT
FT
FT
FT
IT
IT
IT
18
18
35
10
10
10
12
15
10
11
IT
IT
IT
IT
BT
BT
ZT
BT
IT
IT
10
10
10
IT
36
FT
2S
IT
36
FT
26
12
12
11
.45
11
10
10
AT
BT
BT
BT
AT
AT
IT
~
IT IT
11
17
17
12
10
12
10
36
10
35
\
II
IT
36
NOTE: CHASSIS SAND U ON All STAno S.
CHASSIS V, W, Y, AND Z ON MASTE STATIONS ONLY.
IT
36
IT
36
IT
36
IT
36
IT
36
FT
IT
IT
11
20
11
<:
LT
36
IT
36
IT
BT
FT
-,'/
FT' LT
IT
11
10
10
10
~
,V
~
13
S
~
V
W
Y
Z
J
t-
'-
901013A. 402
Figure 4-3. Module Location Chart
4-5
SDS 901013
Paragraphs 4-4 to 4-5
4-4 PREVENTIVE MAINTENANCE
A program of preventive maintenance is the most effective
method of ensuring efficient station operation and reliability. Table 4-4 provides information necessary for visual
inspection of the station. Since the need for this inspection is determined by environmental conditions, no absolute
checking intervals are specified.
loaded washer and make sure that it rests flush on the
shoulder of the guide body. Do not remove the ceramic
cap on the guide when cleaning.
c. Read/write head. Dampen a tissue with alcohol
and clean both heads.
d. Tape cleaner. Dampen a tissue with alcohol and
gently wipe the tape cleaner face. Make sure that the
tissue is not torn by the cleaning holes, as any lint or tissue
fragments may c log the c leaning holes.
A prescribed maintenance schedule is presented in table
4-5. Since all bearings in the station are prepacked and
sealed, no periodic lubrication is necessary.
4-5 CLEANING PROCEDURES
The following cleaning procedures should be performed at
the intervals specified in table 4-5 with the cleaning
equipment listed in table 4-2.
a. Capstan. Dampen a tissue with alcohol and ger:-tly
wipe around the rubber surface until all foreign particles
and tape oxide are removed. Allow capstan to dry for at
least one minute.
b. Tape guides. (See figure 3-8.) Dampen a tissue
with alcohol and wipe the body of the guide, making sure
that the corner between the guide body and the ceramic
cap is completely free of dirt or oxide. Clean the spring
e. Vacuum chambers. Open the vacuum chamber
doors and clean the corners of the chamber with a brush
soaked in alcohol. Soak a tissue in alcohol and clean the
chamber bases and the door glass.
f. Reel tachometer pulleys. Dampen a tissue with
alcohol and clean the faces and corners of the pulleys.
g. Erase head. Dampen a tissue with a Icohol and
c lea n the head.
h. Cabinet. When dusty, the cabinet and transport
surface should be wiped with a clean, alcohol-moistened
cloth.
Table 4-4. Visual Inspection Information
Item to be Inspected
Power cable
Capacitors
Resistors
Transformers
Corrective Procedure
Inspect For
Defective plug pins
Replace plug
Frayed or damaged cable
Replace cable
Damaged container
Replace capacitor
Loose terminal connections
Tighten
Cracks, charred surface
Replace resistor
Poor solder connections
Resolder
Burned insulation or evidence of overheating
Replace transformer
Note
Before applying power to new transformer, check the rectifier(s), filter
capacitors and choke(s), or resistors.
Replace the defective components
Loose mounti ng hardware
Tighten
Semiconductors
Loose terminal connections
Resolder connections
Switches
Defective contact; loose toggle
Replace switch
(Continued)
4-6
SDS 901013
Table 4-4. Visual Inspection Information (Cont.)
Terminal blocks
Correcti ve Procedure
Inspect For
Item to be Inspected
Loose or broken terminals or wires
Terminals (on terminal boards, Accumulated dirt
terminal blocks, transformers,
etc.)
Replace terminal block
Clean with an approved cleaning agent such
as trichlorethylene or isopropyl alcohol
Loose term i na Is
Tighten
Poor solderi ng
Resolder
Shorted wiring or potential sources of shorted
wiring such as loose screws and bare wire in
close proximity to metal chassis
Insulate bare wire where necessary, and
tighten loose hardware
Connectors
Bent pins
Straighten
Printed circuit modules
Oxidation film on board terminals
C lean with approved cleaning agent such as
trichlorethylene or alcohol
Tape tracking
Tape entry into the chambers from the reel
tachometers should be unimpeded
See paragraph 4-38
Power supply chassis wiring
Tape guide spring washers, except on the 2
outer guides, should be resting against the
inner tape edge. If the washers are pressed
and tilted, they may hang up on the guide
body, resulting in a loss of tape tracking
Note
Except on the 2 outer guides, the outer
edge of the tape will always be spring
loaded against the ceramic tape guide
caps. The tape should enter the tape
reels without excessive rubbing of the
tape edges agai nst the reel flanges.
The position of the reels is set during
manufacture of the transport, so adjus tment should not be required
Erase head
Erase head should be mounted perpendicular
to the tape. Tape should be as close as
possible to erase head but should not touch
head
See paragraph titled Tape Heads under
paragraph 4-8
Relay chassis
All relays should be properly mounted and
the ground strap should be properly connected between TB 1-9 and chassis
See fi gure 4-25
Tape creepage or vibration
in vacuum chambers
Movement of tape in vacuum chambers
Fixed reel: adjust R34 on U16 for zero volts.
Place scope probe on test point U17-23
File reel: adjust R31 on U16 for zero volts.
Place scope probe on test point U16-18
(Continued)
4-7
SOS 901013
Table 4-4. Visual Inspection Information (Cont.)
Item to be Inspected
Inspect For
Corrective Procedure
Tape creepage at capstan
motor
Movement of tape at capstan dri ve
Ad just R30 on U14 for zero vo Its. Place
voltmeter leads on contacts 14 and 15 on
T81T. (Use low range on voltmeter; 10-volt
range or lower)
Read/write head
Check for proper slack in the head cable at
the connector and head stack. Check the
head surface for scratches, imperfections,
and dirt
See paragraph titled Tape Heads under
paragraph 4-8
Table 4-5. Preventive Maintenance Schedule
CLEAN
ITEM
REPLACE
PARAGRAPH REFERENCE
Hours of Operation
Capstan
8
4-5
Tape guides
8
4-5
Read/write head
8
4-5
Erase head
8
4-5
Tape cleaner
8
4-5
Vacuum chambers
8
4-5
Reel tachometer pulleys
8
4-5
Tape tracking
8
4-38
Vacuum system
500
4 - 11 th r u 4 - 13
Positive pressure system
500
4-15
Holddown knob
500
4-67
Holddown knob rubber ring
500
8,000
500*
Capstan velocity ramp generator
4-67
4-40
Reel servo
2,000
4-26 thru 4-28
Head cover actuator
2,000
4-16
Reel brake friction discs
8,000
4-65
Reel motor brushes
8,000
4-73
Capstan motor
8,000
4-70
Positive pressure pump
8,000
4-72
Reel motor
8,000
4-73
Cabinet
*Check
4-8
ADJUST
As required
Paragraphs 4-6 to 4-9
SDS 901013
4-6 CORRECTIVE MAINTENANCE
4-7 PRELIMINARY CHECKS
In the event of station failure, or if a complete checkout
is desired, the following power distribution resistance and
voltage checks should be made.
Erase head resistance is measured at TB1 on the magnetic
head cable assembly (figure 4-12), and should be 25
(± 1.25) ohms. If out of tolerance, it must be replaced. (See
fi gure 4-16.) For remova I and replacement procedure, see
paragraph 4-76.
Note
The read and write heads are actually stacks
of seven heads, and measurements must be
performed on each section of each head.
Therefore, if any section of the head is defective, the entire head must be replaced. Pin
connections for the head connectors are shown
in figure 4-17.
4-8 Resi stance Checks
POWER DISTRIBUTION. Resistance checks are made as
follows:
a.
Turn off all ac and dc power in station.
b. Set the circuit breaker on the power distribution
chassis to the ON position and the LOCAL/AUTO switch
to the LOCAL position.
Resi stance of the read head coi Is should be 25 (± 1.25) ohms.
For removal and replacement procedure, see paragraph 4-74.
c. Use a multimeter (RX1 scale) to check for shor~
c i rcu its betwee n a II power bus bars and ground. If shorts
exist, the most probable cause is contact pins touching.
Visual inspection will usually determine the location of
trouble.
4-9 Voltage Check
d. Measure the resistance between pins 1 and 2 on
TB 1. The resistance should be infinite. If it is not, check
relays K3 and K4 and replace defective parts. (See fi gures
3-4 and 4-24.)
b. Set the ac distribution chassis circuit breaker to
ON, and the LOCAL/AUTO switch to LOCAL.
e. Measure the resistance between terminals 6 and 7
on TB2. The resistance should be approximately 1 ohm. If
it is infinite, check the input transformer, and replace it if
defective.
f. Measure the resistance between terminals 9 and 10
on TB2. It should be infinite. If it is 470 ohms, relay K2
is defective.
Note
In the following test, CR18 will be in parallel
with the meter. Therefore, polarity of the
multitester leads is critical.
Measure resistance between terminals 15 and 16 on TB2.
The resistance should be 70 ohms. If resistance is more
than 77 ohms or less than 63 ohms, replace relays K6 and
CR18.
TAPE HEADS. The tape head resistance checks should be
made only if tape head difficulties are suspected. Resistance checks of tape heads are made as follows:
i:
CAUTION!
The voltage presented to the test leads by the
internal multitester battery may be enough to
damage the tape head wi ndings. Therefore,
use a low voltage ohmmeter, if avai lable.
Station voltages are checked as follows:
a.
c.
panel.
d.
Connect the ac power to the station.
Press the POWER switch on the operator control
Measure the voltages at the pins indicated:
Pin
Module Shelf
Voltage
0, 16, 32, 48
S, U
0
50
S, U
-8
51
S, U
+8
49
S, U
+4
45
U
+25
41
U
-25
e. If voltages are more than 10% out of tolerance,
readjust the affected power supply.
The contents of this section include step-by-step procedures
for adjustment, removal, replacement, and repair of the
tape station.
Note
Some of the adjustments in th is section require the use of an osci Iloscope. The
instructions given are intended for use with
a Tektronix oscilloscope model 545 with a
model CA plug-in preamplifier and X10
probes. When other oscilloscopes are used,
4-9
Paragraphs 4-10 to 4-15
SDS 901013
Note (Cont.)
their controls must be set to the same values
as those called out for the Tektronix 545.
The Tektroni x control desi gnati ons may be
different than those of some other makes of
equipment; therefore, table 4-6 shows the
Tektronix designation followed by the generic term for the function.
Table 4-6. Tektronix Oscilloscope Control Designations
Generic Term
Designation
VOLTS/CM
Vertical sensitivity
TIME/CM
Sweep rate
TRIGGERING MODE
Sync mode
TRIGGER INPUT
Sync input
4-10 MECHANICAL ADJUSTMENTS
c. Start the station and manually move the tape loops
halfway between the four loop sensing switches in each
vacuum chamber.
d. Adjust the variable impedance valve mounted at
the exhaust outlet of the capstan motor housing. This is
done by loosening the locking screw located at one side of
the exhaust outlet and by turning the butterfly spindle
located on the opposite side. Rotation of the butterfly
spindle wi 1\ result in a vacuum change. Set the vacuum tq
16 (±1/2) inches of water.
e. After setting the vacuum, tighten the butterfly
spindle locking screw, remove the vacuum gauge, and
replace the plastic tubing.
4-13 Vacuum Valve Adjustment
Adjust the vacuum valve as follows:
a.
Remove the vacuum valve return spring.
b. Make sure that the solenoid plunger moves freely
during several valve operations. If the plunger sticks,
adjust the coil position.
4-11 Vacuum Chamber Door Adj ustment
c.
Replace the return spri ng.
The vacuum chamber door is adjusted as follows:
4-14 Write Enable (File Protect) Switch Adjustment
a.
Place short tape loops in each vacuum chamber.
Adjust the write enable switch as follows:
b. Connect the vacuum side of the blower directly to
the vacuum chamber plenum.
c.
doors.
d.
Slacken hinge mounting screws on both chamber
Apply vacuum to the chambers.
e. Press the chamber doors at various points a long
their length to ensure that they are seated against the
chamber side rai Is.
f. Tighten the chamber door hinge screws and measure
the vacuum in the plenum. The vacuum should measure a
minimum of 25 inches of water.
g. Reconnect the vacuum side of the blower to the tee
junction and the vacuum line from the junction to the
plenum.
4-12 Vacuum Level Adjustment
The vacuum level is adjusted as follows:
a. Disconnect the plastic tube at the nipple mounted
on the vacuum chamber plenum closest to the blower side
of the cabi net.
b.
4-10
Connect vacuum gauge to this nipple.
a. Using a tape reel with a segment removed, check
the location of the write enable switch sensing pin. This
pin should protrude into the annular cutout in the reel without touc hi ng the ree I.
b. Using a tape reel with a write enable ring in place,
check for correct action of the write enable piston and
electrical contact in the vacuum switch.
c. If the write enable switch is incorrectly positioned,
adjust it by means of a collet c lamp. See paragraph 4-64
for the removal and replacement procedure.
4-15 Positive Pressure Adjustment
Adjust the positive pressure system as follows:
a. Disconnect the plastic tubing to the head cover
actuator.
b. Connect the pressure gauge to the plastic tubing
just removed.
c. Loosen the locknut on the pressure regulator located on the main casting above the positive pressure pump.
See fi gures 4-12 and 3-7.
Paragraphs 4-16 to 4-22
SDS 901013
d. Start the station, making sure that the tape loops
are halfway between four loop sensing switches in each
vacuum chamber.
e. Adjust the regulator adjusting screw until the
gauge reads 5 (± 1/2) Ib/in 2 •
f. Set the positive pressure interlock switch (located
below the capstan motor on the main casting) so that contact is made at 5 Ib/in 2 • This may be done by connecting
continuity tester leads to the switch arm and the unused,
normally closed contact. At 5 Ib/in 2, the switch should
actuate. (Actuation pressure is adjusted by a knurled screw
on the switch assembly.)
g. Disconnect the pressure gauge and replace the
plastic tube on the head cover actuator.
See paragraph 4-72 for the positive pump removal and
replacement procedure. Drain the condensation trap every
500 hours.
4-16 Head Cover Actuator Adjustment
d.
Remove the fixture and replace the cover.
e. Unlock the hub. Verify uniform positioning of
shoes against rubber ring. Place the reel on the hub and
lock the hub. Rotate the reel by hand. The hub should
rotate with the ree I.
f. For removal and replacement procedure, see paragraph 4-67.
4-18 Fixed Reel Check
Check reel wobble and tape entry. If irregularities exist,
replace defective parts. See paragraph 4-68 for removal
and replacement procedures.
4-19 Reel Motor Drag Torque
Adjust reel motor torque as follows:
a. With reel motor brakes energized, rotate the shaft
of each reel motor shaft to check for smooth operation.
Drag torque should be uniform with no perceptible irregularities.
Adjust the head cover actuator as follows:
f
CAUTION
I
Turn off the tape station power before making
this adjustment.
b. If tight spots exist, check and readjust the reel
motor brake armature gap to 0.010 in. (paragraph 4-66).
See paragraph 4-65 for removal and replacement procedures.
4-20 ELECTRICAL ADJUSTMENTS, TRANSPORT
a. Loosen the locknut on actuator housing assembly
at the back of the transport casti ng.
b. Remove the plastic tube connecti ng the actuator
to the pressure source.
4-21 Transport Clock Adjustment
The transport clock is adjusted as follows:
a.
c. Turn the actuator until the head cover is approximately 600 open.
d.
Tighten locknut on actuator housing assembly.
e.
Reconnect plastic tube connection.
Ground the following points:
Pin 41 on U8 (DRDS)
Pin 12 on U5 (ROFS)
Pi n 38 on U7 (REVS)
Pin 12 on U6 (REWS)
Pin 38 on U8 (ACMS)
4-17 Fi Ie Reel Hub Holddown Adjustment
Adjust as follows:
a.
b. With the transport in ready and local modes, use
an oscilloscope to observe the waveforms at pin 42 on U11
(OSCLKA). The waveform should be a symmetrical square
wave with a 100 fJs period. Adjust R3-1 on U11 to obtain
50 fJs positive, and R3-2 on U11 to obtai n 50 fJs off.
Remove reel and cover from hub.
4-22 Photosense Lamp Current, BOT and EOT Adjustments
b. With hub in unlocked position (pulled out), place
the push-on/pull-off (Papa) alignment fixture on the hub
and lock hub.
c. Using the papa adjustment wrench, adjust each
shoe arm one-half turn at a time unti I the outside of the
rubber ring touches the inside of the fixture. Shoe positions
should be uniform in relation to the contact poi nt with the
rubber ring. Rotate the fixture by hand to determine whether
the shoe fit is snug.
Adjust the BOT and EaT as follows:
a. Remove the wire from TB5T -5 on the transport
casting (figure 4-1).
b. Connect a multimeter on the 100 mA range between
TB5T-5 and the disconnected wire.
c.
Adjust R27 on U20 for 100 (±2) rnA reading.
4-11
Paragraphs 4-23 to 4-27
d.
Turn off station power. This is imperative.
e.
Replace the wire on TB5T -5.
f.
Turn on the station power.
SDS 901013
g. Adjust R21 on U13 to obtain equal voltage on pins
22 and 23 on U13. The voltage should not be less than 15V
or more than 18V.
h.
Adjust R20 on U13 to obtain 13V on pin 21 on U13.
i. See paragraph 4-75 for photosense head removal
and replacement.
3.
TRIGGERING MODE to INT +
4.
AC/DC switch to DC
5.
Vertical MODE switch to A a NL Y
b. Connect oscilloscope channel A probe to pin 19 on
U15, the ramp generator.
c. Press the FORWARD button on the auxiliary control pane I to start tape forward moti on. Observe the osc i 1loscope for osci lIations. Press the RESET button on the
operator control panel to stop tape motion. Press the
REVERSE button on the auxil iary control panel to start tape
reverse motion. Observe oscilloscope for osci lIations.
Press RESET on operation control panel to stop tape motion.
4-23 Capstan Dead Band Adjustment
The following adjustment is to prevent capstan motion when
the station is in idle. This adjustment should be made whenever a new HTl2 reference generator is installed in U14. or
if capstan motion is observed when station is in idle.
a.
d. Repeat step c with the oscilloscope connected to
the following pins:
1.
Pin 18 on Tl6 (file reel servo)
2.
Pin 23 on Tl7 (fixed reel servo)
Remove the tape from the capstan.
b. Place service loops in both vacuum chambers so
that the bottom of each loop is positioned between loop
sensing switches S3 and 54.
c. Connect a vacuum tube voltmeter between TB1T-14
and TBlT-15 on the transport casting. The voltmeter is now
directly across capstan motor.
d. Adjust R30 on U14 so that the voltmeter reads 0
(±O.Ol) Vdc. The capstan should be motionless.
e. Oscillations should not be present in any of the
above tests. (Oscillations could be caused by a faulty
tachometer, a high resistance ground, or a defective transistor in the transport drive electronics [see figure 4-27]).
4-26 Reel Servo Amplifiers Zero Adjustment
Adjust the reel servo amplifiers as follows:
a.
Set the oscilloscope controls as shown below:
1.
VOL TS/CM to 0.5
2.
TIME/CM to 1 MILLI SEC
3.
TRIGGERING MODE to AUTO
4.
AC/DC switch to DC
5.
Vertical MODE switch to A ONLY
4-24 Preliminary Capstan Speed Adjustment
Preliminary capstan speed adjustments are made as follows:
a.
Connect VTVM to 19 on U15.
b. Press FORWARD on auxiliary control panel and
adjust R15 on 14T to read +1.6 (+0.1) V.
c.
Pre ss RE SE T on the operator contro I pane I.
d. Press REVERSE on the auxi Iiary control panel and
adjust R16 on 14T to read -1.6 (±0.1) V.
e.
Press RESET on the operator control panel.
For accurate speed and ramp adjustments, see paragraphs
4-39 and 4-40.
4-25 asci Ilation Check
Perform the oscillation check as follows:
a.
Set the oscilloscope controls as follows:
1. - VOLTS/CM to 1.5
2.
4-12
TIME/CM to 1 MILLI SEC
b. Connect the oscilloscope channel A probe to pin
18 on U16.
c.
Adjust R31 on U16 for an osci 1I0scope reading of
o (±0.2) Vdc.
d. Connect the oscilloscope channel A probe to pin
230nU17.
e.
Adjust R34 on U16 for an oscilloscope reading of
o (±0.2) Vdc.
4-27 Fixed Reel Servo Amplifier Tape Loop
Positioning Adjustment
With the transport in manual mode (press RESET), adjust the
tape loop position as follows.
Paragraphs 4-28 to 4-30
SDS 901013
a. Press FAST and FORWARD on the auxiliary control
pane I to obtai n tape fast forward motion.
4-29 Load One-Shot Adjustment (SAS and 0.22 Sec
One-Shots)
b. Adjust R15 on U17 so that the tape loop stays
between switches S4C and S5C on the fixed reel vacuum
chamber. Turning R15 clockwise corrects upward drift, and
counterclockwise corrects downward drift.
SASe Adjust SAS as follows:
a.
c. Press RESET on the operator control panel to stop
tape motion.
d. Press FAST and REVERSE on the auxiliary control
panel or REWIND on the operator control panel to obtain
tape fast reverse motion.
e. Adjust R4 on U17 so that the tape loop stays between switches S2C and S3C. Turning R4 clockwise corrects upward drift, and counterclockwise corrects downward
dri ft.
f. If adjustment e disturbs adjustment b, repeat these
steps and adjust R4 until drift is about equal but opposite
for each direction. Adjust R15 so that tape loop stays
steadily between S2C and S4C in reverse direction and
between S4C and S5C in forward direction. Repeat the
above operations until steady tape loop travel is obtained.
g.
Turn R15 on U17 three full turns clockwise.
b.
Set osci Iloscope controls as shown below:
1.
VOLTS/CM to 2
2.
TIME/CM to 0.5 MILLI SEC
3.
TRIGGERING MODE to INT +
4.
AC/DC switch to DC
5.
Vertical MODE switch to A ONLY
Install an empty reel on the file reel hub.
c. Connect oscilloscope channel A probe to pin 8
on U10.
d. Continually press and release the LOAD switch
whi Ie observi ng waveforms on the oscilloscope.
e.
Adjust R3-3 on UlO for 500 (±10) ms pulse width.
0.22 Sec One-Shot. Adjust the one-shot as follows:
4-28 File Reel Servo Amplifier Tape Loop
Positioning Adjustment
a. Connect the oscilloscope channel A probe to pin 8
on Ull.
With the transport in manual mode, adjust the tape loop
positioning of the file reel servo amplifier as follows:
b. Continually press and release the LOAD switch
while observing waveforms on the oscilloscope.
a. Press FAST and REVERSE on the auxi Iiary control
panel or REWIND on the operator control panel to obtain
fast reverse tape motion.
b. Adjust R4 on U16 so that the tape loop stays
between switches S4F and S5F on the fi Ie reel vacuum
chamber. Turning R4 clockwise corrects upward drift, and
counterclockwise corrects downward drift.
c. Press RESET on the operator control panel to stop
tape motion.
d. Press FAST and FORWARD on the auxiliary control
panel to obtain fast forward tape motion.
e. Adjust R16 on U16 so that the tape loop stays
between switches S2F and S3F. Turning R16 clockwise
corrects upward drift, and counterclockwise corrects downward drift.
f. If adjustment e disturbs adjustment b, repeat these
steps and adjust R16 until drift is about equal but opposite
in each direction. Repeat the above operations unti I a
steady tape loop is obtained.
g.
Turn R4 three full turns clockwise.
c.
Adjust R3-3 on Ul1 for 200 (± 10) ms pulse width.
4-30 Load Function Test
Test the load function as follows:
a.
Unload all tape from the machine.
b. Lower the sl idi ng glass window to fully release the
reel motor brakes.
c. Load the tape by threading it on the normal path
and wind two to four turns on the fixed reel. Make sure
that the tape does not get caught on the vacuum chamber
edge.
d. Raise the sliding glass window to the fully closed
position.
e. Press the LOAD switch and observ;' the tape movement. The tape should first go into the file vacuum
chamber. When the loop reaches the interlock switch, the
capstan should start to turn forward, allowing tape to go
into the fixed chamber. The tape will continue to move
unti I the BOT mark reaches the photosense heads. At that
time the tape wi II stop.
4-13
Paragraphs 4-31 to 4-35
SDS 901013
Note
In case of tape breakage or marker loss, information required for replacement is found
in figure 2-3.
4-31
Rewind One-Shot Adjustment (0.8 Sec O-S, Both
De lay, Backups, and F Delay)
c. Remove the fi Ie protect ri ng from the file ree I,
reload, and put the station in the ready mode (all interlocks closed).
d. The voltage at pins 10 and 50 on U32 should now
be zero.
e. The write enable relay is K6 on relay chassis
(figure 4-26).
Adjust the one-shots as follows:
a.
Set the oscilloscope controls as follows:
Turn off the power and remove the jumpers installed in
paragraph 4-21, step a.
1.
VOL TS/CM to 2
4-33 ELECTRICAL ADJUSTMENTS, CONTROLLER
2..
TIME/CM to 2 MILLI SEC
This section pertains to units equipped with the model 7371
controller, which consists of module chassis V through Z.
3.
TRIGGERING MODE to EXT +
4.
AC/DC switch to DC
5.
Vertical MODE to A ONLY
The associated Magnetic Tape Station Model 7372 should be
completely checked out and adjusted as delineated in paragraphs 4-7 through 4-32 and 4-37 through 4-54.
b. Put the station into manual mode by pressing the
RESET switch.
Visually inspect the controller as called out in the applicable portions of table 4-3.
4-34 Module Location
c. Connect the oscilloscope channel A probe as
shown in table 4-7. Adjust one-shots as shown in the table.
The one-shots are triggered each time the station goes from
stop to rewind. Proper tape motion for the adjustments may
be obtained by using the RESET switch for stop action, and
the REWIND switch.
Figure 4-3 shows the module location for the controller.
4-35 Clock Oscillator Check
Check out clock oscillator
d. The outputs of the one-shots should not have extra
spikes at leading or trailing edges.
a.
One-Shot
Oscilloscope Probe
Connection
Adjust
Adjust For
R3-4
800 (± 10) ms
0.8 sec
one-shot
Pin 6 on U10
BOTH delay
Pin 42 on U10
R3-1
500 (± 10) ms
Backups
Pin 29 on U10
R3-2
500 (±50) ms
F delay
Pin 6 on U11
R3-4
350 (± 10) ms
as follows:
Set the controls on the osci Iloscope as follows:
1.
Table 4-7. Rewind One-Shot Adjustments
cno in slot W22
2.
to 2 flSEC.)
VOLTS/eM to 1V
TIME/CM to .1 tJSEC. (After step h, change
3.
TRIGGERING MODE to INT +
4.
AC/DC swi tch to DC
5.
Vertical MODE switch to A ONLY
,...,
c. Remove module cno, insert module ZT10 into
slot W22, insert cno into ZTlO.
b.
Turn station.., power off •
d•
Turn stati on power o~.r
e.
Put the oscilloscope channel A probe on test point
f.
Adjust L1 for maximum amplitude.
g.
Put oscilloscope channel A probe on pin 34.
"
4-32 Write Enable (File Protect) Check
Check the write enable system as follows:
a. Load the file reel with the file protect ring
insta lied.
b. Using a multimeter, check for +25V at pins 10
and 50 of U32.
4-14
A on
cno.
SDS 901013
h. Adjust R16 for a positive pulse duration time of
130 ns. The period of the cycle should be 261 ns.
Paragraphs 4-36 to 4-39
4-38 Tape Tracking
Note
i. Check signal ClKS at pin 45 of W14. It should
have a period of 16.0 fJS, the positive portion being 4.0 fJS,
with a small amount of jitter.
Although this test is mechanical in nature, it
is important that tracking and alignment be
as accurate as possible before the tests that
follow this one are performed.
j.
Connect a jumper from pin 44 to 48 on W25.
k.
The ClKS period should be 16.7 fJs with no jitter.
Adjust tape tracking and alignment as follows:
I.
Turn station power off.
a. Make sure that all tape path elements are clean
and free of tape oxide deposits. See paragraph 4-5.
m.
Remove module ZTlO and replace CTlO in W22.
n.
Remove jumper on W25.
o.
Turn station power on.
-
b. Make sure that on all tape guides the spring loaded
washer is flush with the shoulder of the guide body.
c. Operate the station in forward and reverse directions. Except for the two outer guides, the edge of the tape
should contact the ceramic guide cap at all times.
4-36 Controller Checkout With lOP
The following test requires that the controller be connected
to a Sigma series computer.
d. Tape should enter both vacuum chambers without
tape edges touching the chamber base or the inside face of
the chamber cover.
Check as follows:
a. Set the toggle switch on LT25 at Y23 to the ONLINE position.
e. If adjustment is necessary, adjust the position of
the ree I servo tachometers. See paragraph 4-69.
4-39 Capstan Speed Check and Adjustment
b. Set up the desired controller address with SWAO
through SWA3 toggle switches on l T26 at Y24. SWAO in
the ON position, and SWA1 through SWA3 in the OFF
position correspond to a controller address of X8. The X is
the station address, which can be set to 0 through 7 by the
UNIT SELECT switch.
c. Test the controller by running the appropriate
program shown below.
Computer
Program
Sigma 5 or 7
704026-83* or 704026-84t
Sigma 2
704057-83* or 704051-84t
* On punched paper tape
tOn punched cards
Adjust the capstan speed as follows:
a. An acc urate osc ill oscope ti me base setti ng is mandatory for this procedure. Set oscilloscope controls as
follows:
1.
VOL TS/CM to 1V
2.
TIME/CM to 10 fJSEC
3.
TRIGGERING MODE to INT -
4.
AC/DC switch to DC
5.
Vertical MODE to ALTERNATE
b. Connect channel A probe to pin 13 on S 13 (ClKS
output of ClKS line receiver). Term ClKS is from 60 kHz
master clock in the controller.
c. Connect a jumper between pins 44 and 48, slot
W25 on the controller. Channel A waveform should go
false approximately every 16.7 fJs.
4-37 STATION lOGIC ADJUSTMENTS
The following adjustments require that the station be connected to a model 7371 controller, and a Peripheral
Equipment Tester{PET) Model 7901 with a front panel overlay No. 135781. Instructions for the connection of these
devices are found in paragraph 4-56 and in the instruction
manual for this equipment.
d. Adjust TIME/CM VARIABLE so that a negative
transition occurs at each centimeter marker.
Note
Do not disturb the TIME/CM VARIABLE setting during the following tests.
4-15
50S 901013
Paragraph 4-40
e.
f.
on 51.
Load master speed
~hecking
tape on station.
Connect channel B oscilloscope probe to pin 46
b.
AC/DC switch to DC
5.
Vertical MODE to ALTERNATE
Connect the osci lIoscope probes as follows:
g. Press FORWARD switch on auxiliary control panel.
A negative-goi ng transition should appear at each centimeter marker. (Instantaneous speed variations cause some
jitter. This is normal.) The display on the oscilloscope
should be as shown in figure 4-4.
h. If the negative-going transitions do not coincide
with the centimeter markers, adjust R16 on U14 until the
waveform resembles the one shown in figure 4-4.
4.
1.
Channel A to pin 19 on U15
2.
Channel B to pin 46 on 51
3.
Trigger input to pin 17 on 58
c.
Load the test tape with all ones recorded.
d.
Move the tape past the BOT marker.
k.
Press the RESET switch to stop tape motion.
e.
Open the door interlock.
I.
Press the REVERSE switch on the auxiliary control
f.
Install the jumpers as follows:
panel.
1.
m. Repeat steps i and j, adjusting R15 on U14 for
proper waveform placement.
n.
2.
(RESET PB)
Stop tape motion by pressing the RESET button.
Pin 25 on 58 (NFC01S) to pin 22 on U7
3. Pin 32 on 55 (Ground) to pin 30 on 55
(NOPRNAUTS)
Note
g.
Ramp adjustment (paragraph 4-40) must always
be performed after capstan speed adj ustment.
Adjust ramp acceleration and de~eleration as follows:
Set the osci 1I0scope controls as follows:
1.
VOL TS/CM to .5
2.
TIME/CM to 1 MIlLI SEC
3.
TRIGGERING MODE to EXT +
Close all interlocks.
h. The tape should move forward for 34 ms and stop
for 34 ms. After cycling has started, adjust R4 on U15 to
make the channel A waveform reach maximum amplitude
4 ms after the start of the forward ramp. Thi s should cause
the channel B waveform to reach maximum amplitude in
approximately 5 ms. Ramp adjustment waveforms are illustrated in fi gure 4-5.
4-40 Ramp Adjustment for Acceleration and Deceleration
a.
Pin 17 on 58 (FC01S) to pin 15 on U7
(FWD PB)
i.
Open the door interlock, stopping tape motion.
j.
Repeat steps f, g, h, and i, changing jumpers and
adjustment potentiometers as follows.
513-13
ClKS SIGNAL
S 1-3
READ AMPLIFIER
CHANNEL 2
I
o
I
2
I
3
I
4
I
5
6
CENTIMETERS
CENTER NEGATIVE TRANSITION JITTER ON CENTIMETER MARKS
Figure 4-4. Waveforms, Capstan Speed Adjustments
4-16
901013A.407
SDS 901013
FORWARD FORWARD REVERSE
START
STOP
START
4 MS
4 MS
4 MS
+4V _
OV
I
I
r-,~
'I
ri Iri r
\'
II
Vi
APPR OX +1. 6V
REVERSE
STOP
4 MS
1
II
. I
--....:.I-I----4{§ ~I~---...,J J---J.
I-
'1-....;.1----:.,1_ _
I,
I
'~- - - -
FORWARD INPUT
REVERSE IN PUT
(15U-19)
-
-
-
APPROX -1.6V
I
CHANNEL B
~11l'lli~ ~~I: llWl~"_",,__ ~~~p~~~FIER
I I
I
I
OUTPUT (IS-I)
.j5 MS L.J5 MS L~5 MS ~J5 MSL
FORWARD
START
FORWARD
STOP
REVERSE
START
REVERSE
STOP
90 1084A. 409
Fi gure 4-5. Waveforms, Ramp Adjustment
4-17
Paragraphs 4-41 to 4-43
SDS 901013
1. Move the jumper end on pin 15 on U7 to pin
7 on U7. Adjust R3 on U15. The tape wi II move in reverse.
k.
Press the RESET switch to stop tape motion.
4-41 MasterClock
The master clock is checked as follows:
a.
3.
TRIGGERING MODE to INT +
4.
AC/DC switch to DC
5.
Vertical MODE to A ONLY
c. Connect the osci lIoscope to the outputs of each
stage and determine that the counter is working correctly.
Each stage should have twice the period of the preceding
stage. The waveform at pin 17 of 58 should be 68.4 ms.
The stages are listed in the order shown in table 4-8.
Set the osci lIoscope controls as follows:
Table 4-8. Delay Counter Access
1.
VOL TS/CM to .2
2.
TIME/CM to 5 ~SEC
3.
TRIGGERING MODE to INT +
4.
AC/DC switch to DC
5.
Vertical MODE to A ONLY
LOCATION
STAGE
b. Put the station in manual mode by pressing the
RESET switch.
c. Connect the oscilloscope channel A probe to pin
13 on 513.
d. The waveform should be an unsymmetrical squarewave with a period of 16 ~S; 4 ~s true (+4V) and 12 I-'s false
(OV), with a sma II amount of jitter.
e.
g.
Remove the jumper on W25.
4-42 Delay Counter
Adjust the delay counter as follows:
a. Put the station in the manual mode by pressing the
RESET switch.
b.
4-18
Set the osci Iloscope controls as follows:
1.
VOL TS/CM switch to .2
2.
TIME/CM switch as required
Module
FC12S
36
S6
FC11S
24
S6
FClOS
27
S6
FC09S
38
S6
FC085
23
S6
FC07S
11
S6
FC06S
17
S6
FC05S
7
S6
FC04S
24
S8
FC03S
27
58
FC02S
23
58
FC01S
17
58
I
Connect a jumper from pin 44 to pin 48 on W25.
f.
The jitter should disappear and the period should
increase to 16.7 I-'s; 4.1 ~s true and 12.6 ~s false.
Pin
d. Move the tape to the BOT marker. The delay
counter should stop counting.
4-43 Device Ready Latch
Check the device ready latch as follows:
a. Set I'he osc ill oscope control s as in paragraph 4-42,
item b.
b. Connect oscilloscope channel A probe to pin 37
on S16 (DRDS).
c.
Waveform should indicate true (+4V) condition.
d. Press RESET switch. The waveform should indicate
a false (OV) condition as long as the RESET switch is held
down.
Paragraphs 4-44 to 4-45
SDS 901013
4-44 Station Address Selection
4-45 Station Connect
This test requires the use of the peripheral equipment tester
(PET) described in table 4-1, and the osci 1I0scope controls
set as in paragraph 4-42, step b.
This test requires the use of the peripheral equipment tester
described in table 4-1, and the oscilloscope controls set as
in paragraph 4-31, item a. Check the station connect as
follows:
Check station address selection as follows:
a. Set the PET controls to write all zeros (paragraph
4-59, step e1).
b. Set the UNIT SELECT switch on the operator control panel to position O.
a.
Connect a jumper from pin 37 of S14 to ground.
b.
Remove the tape from the capstan.
c.
Press the RESET and the START switches.
c. Set all three DEV ADDR switches on the PET to
the down position.
d. Set the PET controls for the write operation (paragraph 4-59).
d. Press the START button on the PET. If the address
selection logic is operating properly, the station will start
writing.
e. Connect the oscilloscope TRIGGERING INPUT to
pin 37 on S15.
e. Repeat steps b, c, and d, using the switch positions
shown in table 4-9.
f.
Connect the osci 1I0scope channel A probe to the
pins designated in table 4-10, which gives the term to be
observed and the expected waveform for each depression of
the START button on the PET.
Table 4-9. Address Selection
Unit Desired
DEV ADDR*
a
000
1
001
2
010
3
all
4
100
5
101
6
110
7
111
*0
=.
g. Move the tape so that the BO T marker is at the
photose nse.
h. ERSS at pin 31 on S18 goes true when OSCTS (pin
34 on S7) goes true.
i.
Move the tape so that the BOT marker is away
from the photosense.
j.
Set the PET controls as follows:
1•
Read forward (paragraph 4-60)
2.
Push START button on PET
WENS at pin 31 on S15 will go true after OSCTS goes true.
k.
Down posi ti on; 1 = Up position
Set PET control for space reverse (paragraph 4-61).
I. Push START button on PET. RVSS at pin 37 on 517
wi II go true after OSCTS goes true.
Table 4-10. Station Connect Test
Term
Pin Location
Waveform
DSGS (device select gate)
Pin 37 on slot S15
True for 16.7 to 33.4l-1s
DSTS
Pin 40 on slot 513
True for 16.7 to 33.4 I-IS
DSLS
Pin 42 on slot 513
True for 4.1 I-IS when D5TS is true
FCTS (connect flip-flop)
Pin 38 on slot S08
True at trailing edge of DSLS
DRDS (device ready)
Pin 37 on slot S16
False when the FCTS fl ip-flop gets set
OSCT5 (state a)
Pin 34 on slot S07
True for 16.7 I-Is after the FCTS flip-flop gets set
WRTS
Pin 34 on slot S 13
True
WENS (write enable)
Pin 31 on slot S 15
Goes true after term 05CTS goes true if the previous order was a read
NRVSS (not reverse)
Pin 33 on slot S17
Goes true after OSCT5 goes true if the previous order was a reverse
4-19
Paragraphs 4-46 to 4-47
SDS 901013
4-46 5tarting Delay Check
This test requires the use of the peripheral equipment tester
described in table 4-1, and the osci Iloscope controls set as
described in paragraph 4-31, item a. Check starting delay
as follows:
a. Connect the osci Iloscope TRIGGER INPUT probe
to pin 34 on 57 (05CT5).
b.
5et the DEN5ITY switch to 800 bpi.
c.
Remove the tape from the capstan.
d.
Press the RE5ET and 5TART switches.
e.
Move the tape away from the BOT marker.
f.
4-59).
5et PET controls for write operation (paragraph
g. Using the oscilloscope channel A probe, check for
the following:
1. The state 6 term, 0655, at pin 13 on 517
shou Id go true for 6.5 ms.
2. The state 7 term, 0755, at pin 12 on 57 should
go true after term 0655 goes false.
3. If 0655 does not go true, the enables for the
tape write delay signal, TWR5, should come true. These
enables appear on pin 2 on 57 and pin 27 on 510.
h. 5et the PET controls for the read forward operation
(paragraph 4-60).
1. The state 6 term, 0655, on pin 13 on 517
should go true for 51 ms.
2. If 0655 does not go true, the enables (TER5)
at pin 13 on 57 and pin 46 on 510 should come true.
o. 5et the PET controls for read forward operation
(paragraph 4-60).
p. Using the oscilloscope channel A probe, check
that the state 6 term 0655 at pi n 13 on 517 goes true for
29.3 ms. If 0655 does not go true, check that the enable
(TBD5) at pin 34 on 514 goes true.
q. Remove the ground jumpers at pin 37 on 514 and
pin 30 on 518.
4-47 Read/Write Amplifiers
Using the PET and the oscilloscope, the read/write amplifiers are checked as follows:
a. Connect jumper pin 15 on Y8 (PET CD) to ground.
This writes a continuous record without gaps.
b.
5et the DEN5ITY switch to 800 bpi.
c.
Put the tape on the capstan.
d. Close all interlocks and press the RE5ET and
5TART switches.
e. 5et the PET controls for write operation with ones
in all channels (paragraph 4-59, step e-2).
i.
Using the osci Iloscope channel A probe, check for
the following:
f.
Using the oscilloscope, check for the output at
each channel. Refer to table 4-11.
1. The state 6 term, 0655 at pin 13 on 517 should
go true for 5.5 ms.
g. While observing the oscilloscope pattern for each
channel, switch the PATTERN CTR switch for that channel
from ONE to ZERO and back repeatedly. The read amplifier output should change from one to zero with the switch
action.
2. The state 7 term, 0755, at pin 12 on 57 should
go true after term 0655 goes false.
3. If 0655 does not go true, the enables for the
tape read delay si gnal, TRD5, should come true. These
enables appear on pin 45 on 57 and pin 14 on 510.
j. 5et the PET controls as for the space reverse operation (paragraph 4-61).
h. If there is no output at the read ampl ifier, check
the write driver output signals (WDR and NWDR). Pin
locations for these terms are shown in table 4-11. The
desired waveforms for WDR and NWDR are shown below:
k. Using the osci Iloscope channel A probe, check that
the state 7 term, 0755, on pin 12 of 57 goes true after
05CT5, pin 34 on 57, goes false.
I.
Connect jumper pin 30 on 518 (NER55) to ground.
16.7 1-15
m. 5et the PET controls for the write operation (paragraph 4-59).
901 084A. 411
n. Using the osci Iloscope channel A probe, check for
the following:
4-20
i.
Remove the jumper from pin 15 of Y8 to ground.
SDS 901013
Paragraph 4-48
Table 4-11. Read and Write Amplifier Access Pins
READ AMPLIFIER
WRITE DRIVER
THRESHOLD OUTPUT
SLOT U1 PIN
CHANNEL
Module
Out Pin
0
S3
3
1
S3
2
TP Pin
Module
WRD Pin
NWRD Pin
1
S24
6
5
8
8
17
S24
4
1
11
S1
46
39
S24
2
3
15
3
S1
3
1
S24
10
9
18
4
S1
8
17
S29
6
5
20
5
S3
46
39
S29
4
1
23
P
S4
46
39
S29
10
9
4
4-48 Threshold Adjustment For Read Amplifiers
Using the PET and the oscilloscope, the threshold level of
the read amplifiers should be adjusted whi Ie writi ng a long
record pattern of 100010001000 ••• on a new tape. The
threshold level is adjusted as follows:
a. Set the following PET switches to the ON position:
PATA, PATB, all RECORD LENGTH, and PET ON.
b. Adjust each of the threshold potentiometers for an
output voltage of -5.5V. The potentiometers are located
in slot U1, and are arranged vertically with the parity
channel on top, followed by channels 0, 1, 2, 3, 4, and 5.
(See table 4-11.)
c.
Set the oscilloscope controls as follows:
1.
Change the vertical input probes to Xl
2.
VOL TS/CM to
3.
TIME/CM to 5 '"' SEC
4.
TRIGGERING INPUT to EXT +
5.
AC/DC switch to DC
6.
Dual trace MODE to A ONLY
7.
Connect TRIGGER INPUT probe to channel
h. Connect the osci 1I0scope channel B probe to the
read amplifier test point (table 4-11) for the channel under
adjustment. Signal amplitude should be approximately 1.9V.
Adjust the VOLTS/CM VARIABLE control so that the waveform is four divisions high, as shown below.
READ AMP TEST POINT
A
CHANNEL B
901 013A. 409
i.
Set the osci 1I0scope dual trace MODE to ADDED
ALGEBRAICALL Y.
j. Adjust the threshold potentiometer (table 4-11)
unti I the pattern shown below is attained. Then set the
threshold for 25%.
ALGEBRAIC ADDITION
OF CHANNELS A AND B
.5
PORTION ABOVE
READ AMPLIFIER OUTPUT ~
CHANNEL A AND B
A input
d. Connect the osci 1I0scope channel A probe to the
read amplifier output (table 4-11) for the channel under
observation.
e.
f.
28 ,",s.
g.
Press the START switch on the PET.
The duration of the output signal should be 25 to
Set the oscilloscope dual trace mode to B ONLY.
901013A. 410
k.
Repeat steps d through j for all channels except
parity.
I. Set PET switches CTR and anyone of the PATTERN
CTRls to the up position to record the same pattern in the
pari ty channel.
m.
Adjust the parity channel using steps d through j.
4-21
50S 901013
Paragraphs 4-49 to 4-50
4-49 Deskew Adjustment
The deskew adjustments are made in three consecutive steps:
a. Forward read deskew, using the speed test align-:ment tape (paragraph 4-50).
b. Reverse read deskew, using the speed test alignment tape (paragraph 4-51).
c. Write deskew, while writing on blank tape (paragraph 4-52).
g. Connect the osc ill oscope channe I A probe and the
TRIGGER INPUT probe to pin 2 on W19 (read bit deskew
common).
h. Adjust the oscilloscope triggering controls so that
the first pulse does not have a trace at the ground line as
shown below. If more than five pulses appear, check head
alignment and the tape guide position.
ITITl
CHANNEL A
(RBDC)
4-50 Forward Read Deskew
901013A.411
Make the forward read deskew adjustment as follows:
a. Make sure that the read/write head and all tape
guides are clean.
b. !:mov!. the jumper module ~from slot
.lli..
c. On a ST28 switch module, set all switches marked
SWOA through SWP'A, and SWOB through SW8B to 0 (open). ,
Set all switches marked SWOC through SW8C to 5 (short)~'\i"'Ii~)
Insert module ST28 into slot 531.
-
-
Note
The above setting for each channel corresponds
to a deskew count of 4. The 4 is expressed in
binary. The deskew count of 4 is the center of
the adjustment range. For channels that are
late, an early deskew count is required (from 1
to 3). For channels that are early, a late de.skew is required (from 5 to 7). A deskew setting
of 0 (zero) must not be used. If the channels
cannot be deskewed withi n the range of 1 to 7
(1.8 ,",s), the read/write head is not mounted
properly.
d.
-----
Mount the master speed alignment tape.
...
I CAUTION
J
The FILE PROTECT indicator on the operator
control panel must light when the station
becomes ready (all interlocks closed).
e. Set the PET controls for a re~d forward operation
(paragraph 4-60).
f.
4-22
PINV17-2
Set the osci lIoscope controls as follows:
1.
VOL TS/CM to .5
2.
TIME/CM to .5 ,..SEC
3.
TRIGGERING MODE to EXT +
4.
AC/DC switch'to DC
5.
Vertical MODE to CHOPPED
i.
Connect the oscilloscope channel B probe to pin 15
on V 15 (read bit deskew 0). Observe the waveform, and
compare the timing with channel A. Increase or decrease
the deskew count (using the ST28 switches) until it is as
close to the time of the channel A waveform as possible.
j.
Repeat step i for channels 1 through p, using
table 4-12.
Table 4-12. Deskew Access Pins
Read Bit Deskew Channel Out
Slot V16 Pin
RBD 0
01
RBD 1
03
RBD 2
05
RBD 3
07
RBD 4
09
RBD .J
11
RBD P
13
k. After all channels have been adjusted, look at the
switch settings on ST28. If the settings are all to one side
of 4, add or subtract an equal count from each channel to
move them c loser to 4.
I. Repeat steps i, j, and k until the tota I skew cannot
be further reduced.
m. Transfer the switch settings established on the ST28
switch module to the ZT24 jumper module. This is done by
cutting out the forward jumper (identified by an F) that
correspon~s with each switch in the 0 position.
n. Insert ZT24 module into slot 531. Read the skew
(steps i and j) to ensure that the switch settings have been
properly transferred to the jumper module. If the skew
does not agree with the previous reading, recheck the
switches and jumpers.
Paragraphs 4-51 to 4-53
SDS 901013
4-51 Reverse Read Deskew
f. Remove extender cards from the ST14 modules and
rei nsert them in slots S20 and S25. It is very important that
the modules not be reversed, and that the switch settings
not be di sturbed.
Make reverse read deskew adjustments as follows:
a.
Repeat paragraph 4-50 steps a through d.
b. Set the PET controls for the space reverse operati on (paragraph 4-61).
c. Repeat paragraph 4-50 steps f through I. The total
skew must not exceed five pulses or 2.6 fJs.
d. Transfer the switch setti ngs establ ished on the ST28
switch module to the ZT24 jumper module. This is done by
cutting out the reverse jumper (identified by an R) that
corresponds with each switch in the 0 position.
e.
Repeat paragraph 4-50 step n.
g. Set the PET controls to write 16 long records with
ones in all channels and to reverse space the record just
written. With switch RP on, the tape will move forward and
reverse. Check reverse read skew (paragraph 4-51) agai nst
read after write skew (paragraph 4-52) for each channel.
The difference should be no more than one pulse (0.52 fJs).
4-53 Ending Delay Check
The ending delay check is made as follows:
a.
b.
step c.
4-52 Write Deskew
Close all interlocks, and press the START switch.
Set the oscilloscope controls as in paragraph 4-48,
Make write deskew adjustments as follows:
a. Put STl4 modules at slots S20 and S25 on extender
cards and reinsert them into slots.
c. Set the PET controls for the write operation (paragraph 4-59).
Switches FB and RP should be OFF.
b. Set a binary count of 4 on each.set switch. This
is done by setting all SWOA and SWOB switches to 0 and
all SWOC switches to 1. Switch locations are determined
from table 4-13.
Table 4-13. Write Deskew Switches
SWITCH NUMBERS
WRITE
MODULE
CHANNEL LOCATION Sl-SWOA
S1-SWOC
S1-SWOB
(lsb)
(msb)
Note
Table 4-14 lists logic terms and their locations. These terms are referred to in this
check procedure.
Table 4-14. Ending Delay Logic Terms
Term
Pin
Module
ENDS
13
Sl1
OSCTS
34
S7
TSPS
35
15
S7
S10
TRVS
46
28
S7
S10
0
S25
5
10
15
1
S25
4
9
14
2
S25
3
8
13
3
S25
2·
7
12
4
S20
5
10
15
5
S20
4
9
14
02SS
14
S7
P
S20
1
6
11
03SS
33
S7
06SS
13
S17
c.
Load a new blank tape on the station.
d. Set the PET controls to write binary, all ones in all
channels. Make sure the REV switch is off. (See paragraph
4-59, step e2.)
d. Connect the TRIGGER INPUT of the osci Iloscope
to ENDS.
e. Whi Ie writing on tape, repeat paragraph 4-50 steps
f through I (forward read deskew) adjusting the ST14 modules instead of the ST28. The total skew must not exceed
five pulses, or 2.6 fJS.
e. Using the channel A probe of the oscilloscope, do
the following.'
4-23
50S 901013
Paragraphs 4-54 to 4-56
1. Check that ENDS goes true for 16.7 to 33.4
I-'s after the write operation starts.
2.
Connect a jumper from pin 47 on 518 to
ground.
3. Check that 0355 goes true not later than 16.7
I-'s after ENDS and that it remains true for 5.3 ms. If 0355
does not go true, check TSPS.
4.
After 0355 goes false, OSCTS goes true for
5.
Remove the jumper from pin 47 of 518.
6.
Check that 0355 goes true for 67 I-'s.
d. ATTENTION. When the indicator is pressed and
the machine is in the manual mode and operating.
e. FILE PROTECT. When the file protect ring is
absent.
f.
AUTO. When the station is in the automatic mode.
(The AUTO indicator illuminates the START button.)
g. BU5Y. When the station is in the automatic mode,
and the controller is using the machine.
16.7I-'s.
7. After 0355 goes false, check that 05CT5 goes
true for 16.7 I-'s.
h. READY. When all power is on, all power supplies
are functioning, vacuum and pressure pumps are operati ng,
tape is properly loaded, and all interlocks are closed.
Pressing the READY indicator activates a lamp test switch,
which lights the lamps in all of the indicators except RESET
and POWER. (The RE5ET switch has no lamp.)
4-55 PERIPHERAL EQUIPMENT TE5TER OPERATION
Note
The T5P5 delay will be short if a new order is
issued by the controller and the new order is
for tape motion in the same direction. If reversal of direction is ordered, 03S5 will remain
true for 5.3 ms.
5et the PET controls for space reverse operation.
f.
Using the oscilloscope, do the following:
1. Check that 06SS goes true not later than 16.7
I-'s after END5 and remains true for 1.9 ms. If 06SS does not
go true, check TRV5.
2. Connect a jumper from pin 13 on 5B to pin 23
on 515. Read reverse will not run continuously. Press the
5 TAR T button for a new order.
The Peripheral Equipment Tester (PET) Model 7901 is used
with the tape system, as described in paragraphs 4-56
through 4-61.
4-56 Preparation and Connection
To perform the tests described in,this section, connect the
PET to the controller as follows:
a. Connect the power plug to '115 Vac single phase.
Make sure that the POWER switch is OFF.
b. Connect the P 1BO-P 1B1 cable from the PET to
controller slot Y6.
c. Connect the P 1B2-P 1B3 cable from the PET to
controller slot YB.
3. After 0655 goes false, check that 02SS goes
true for 5.3 ms.
Note
4.
Remove the jumperi n step 2.
If the PET is a portable unit, P180 and P1B2
plug in wiring side up. If the PET is a rack
5.
Check that 0255 goes true for 50 I-'s.
mounted unit, P1BO and P182 plug in wiring
side down.
6. After 0255 goes false, check that OSCTS goes
true for ]6.7 I-'s.
Check PET connection and voltages as follows:
4-54 Operator Control Panel Indicator Check
a.
Turn on power to the PET and tape system.
The following operator control panel indicators should light
under the conditions indicated (see figures 4-22 and 4-23):
a.
b.
head.
c.
4-24
POWER. When primary power is applied to station.
LOAD. When the BOT tab is over the photosense
REWIND. When the transport is rewinding.
b. Check the logic supply voltages in the PET and
the tape system. Settings in the shaded area monitor the
voltages generated in the PET, while the rest of the setti ngs monitor the voltages in the controller. Be sure all
voltages are normal at this time. There should be no
indication in positions TV01 and TV02.
SDS 901013
g. If monitoring of data channels is desired, patch
from the desired monitor jack (BFRO to BFR7) to either AUX
1 or AUX 2. Place LATCH/ONE-SHOT in the up position.
(See table 4-17~)
Do not use the PET voltmeter to adjust any
power supplies.
h. To stop the operation, momentari Iy move PET ONOFF/RESET to the OFF/RESET position.
4-57 Overlay
Figure 4-6 is a full-size drawing of the magnetic tape
No. 12 overlay. This overlay should be used for the
tests in this manual. In the event that the overlay is
unavai lable, figure 4-6 may be removed from this book
and used for the overlay.
4-58 On-Line/Off-Line Switch
The on-line/off-line switch on the LT25 module located in
slot Y23 must be placed in the OFF-LINE position for the
PET to operate •. J
,
.a.£ .....
"-~/(.JS ~ ..,...., •
4-59 Write Operation
The write operation is set up on the PET as follows:
a. Set the PET ON-OFF/RESET switch to the OFF/
RESET position.
b. Select the desired station with the DEV ADDR
switches.
c.
Set the command switches to OOlOl{X
Or)
d. Select the number of bytes per record using the
RECORD LENG TH switches. All switches in the off (down)
position wi II cause ei ght bytes per record to be written,
switch 20 will cause 16 bytes to be written, and so forth.
e.
Select the data pattern as follows:
1. All zero pattern. Place all PATTERN CTR
switches in the ZERO position. Place CTR and all DATA
PATTERN switches in off (down) positi on.
2. All one pattern. Place all PATTERN CTR
switches in the ONE position. Place CTR and all DATA
PATTERN switches in the off position.
3. Binary pattern. Data for each channel wi II
correspond to the counter output. Place all PATTERN CTR
switches in the COUNT position. Place CTR switch and
RECORD LE NG TH 27 switches in the on (up) positi on. Set
all DATA PATTERN switches to the off position.
4. Patterns A through D. The combination of
DATA PATTERN switches will determine the data pattern
for each channel, with parity generated automatically.
The switch positions for the avai lable pattern are shown in
table 4-15. Place CTR in off position, and all PATTERN
CTR switches to ZERO.
f.
Paragraphs 4-57 to 4-63
Select the mode of operation from table 4-16.
4-60 Read Forward Operation
The read forward operation is set up on the PET as follows:
a.
Set the PET ON-OFF/RESET switch to OFF/RESET.
b. Set the COMMAND switches to the"6i 169 O( e~
position.
00-440
~
\
(X 0(;/
c.
Select the mode of operation from table 4-16.
d. Move the PET ON-OFF/RESET switch to the ON
position.
e~
Press and release the START pushbutton to initiate
an operation.
f.
To stop the operation, momentarily move the PET
ON-OFF/RESET switch to OFF/RESET.
4-61 Space Reverse Operation
The space reverse operation is set up on the PET as follows:
a.
Set the PET ON-OFF/RESET switch to OFF/RESET.
b. Set the COMMAND switches to the 11100 (X 1C)
position.
c.
Select thE: mode of operation from table 4-16.
d.
Move the PET ON-OFF/RESET switch to ON.
e. Press and release the START pushbutton to begin
operation.
f.
To stop the operation, momentarily move the PET
ON-OFF/RESET switch to the PET ON position.
4-62 REMOVAL AND REPLACEMENT PROCEDURES
Paragraphs 4-63 through 4-76 give step-by-step instructions
for removi ng and replaci ng the major components of the
magnetic tape transport.
4-63 Tape Guide Removal and Replacement (See figure 3-8
The following should be done for removing and replacing
the tape guides:
a.
Remove the screw securing the ceramic cap.
b. Remove the O-ring inside the ceramic cap and
examine for damage. If damaged, replace.
4-25/4-26
SDS 901013
PATA
PATB
PATC
PATO
oAI
OA2
OA3
01
02
03
04
o
05
(
PETON
)
.....Cr---D-AT-A-PA-T-T-E-R-N-:::J------[r--O-E-V-A-DDR-·-],......--,..':===:'-C-O-M-M-A-N-O-----.:.::-'
o
(~-------r"")
210
29
28
26
25
23
RP
I~-------------------RECOROLENGTH------_ _ _ _~I
OlO
24
22
21
)
C
, ____________________________________________________________- '
CTR
CO
CI
C2
C3
C4
C5
C6
~
ONE
ZERO
C7
BUFFER REGISTER
BFRI
BFR2
BFR3
BFR4
BFR5
BFR6
i
BFR7
,PHASE,
FFI
FF2
S
04
SC
RF
10
02
RP
RB
RD
WP
LSB
i
01
OC
05
WO
00
rSUB-PHASE,
FUI
00
FU2
FU3
o
02
06
OE
01
WB
to
o
NORMAL
7-TRACK
c'---__________)
BfRO
W
RB
00
COUNTER
RESET
9-TRACK
....---------PATTERN CTR - - - - -...,
START
RUNN ING MODE
NORMAL
27
ST
CJ 00
PET OFF /RESET
20
2"
rERROR,
DATE
RATE
LATCH
C~____________________________~=
(
FB
AUX I
COMMON
SRF
SRB
SFF
SFB
E
WM
RI
RO
R
14
IC
15
10
16
17
II
12
13
)
AUX2
)
CLOCK
PET
MAG TAPE
NO.12
o
Figure 4-6. PET Magnetic Tape Overlay No. 12
901013A. «>1
4-27/4-28
SDS 901013
c. Remove the special screw inside the air guide
housing.
d.
Table 4-15. PET Data Patterns
Remove the housing, spring, and washer.
1234567891011 12 13 14 15 16
e. Carefully examine the washer for wear. If there
are si gns of the tape edge havi ng cut into the washer,
replace the washer.
f.
BYTE NUMBER
SWITCH UP
o10
PATA
Clean all parts thoroughly with alcohol.
g. When reassembling the tape guide, ensure that the
radiused edge of the washer is adjacent to the guide housing
shoulder.
1 ,0 1 0 1 0 1 0
I
1 0
1 0
1
1 0
0
1
1
PATB
001100110 0
PATA & PATB
010001000 1 0
0
0
1 0
0
PATC
000011110 0
0
0
1
1
1
PATD
o10
1 1 0 100 1 0
1
1 0
1
1
1 0
Table 4-16. PET Functions
Overlay Designation
Pane I Desi gnati on
COMMAND
DATA CONTROL
01
7
02
8
03
9
04
10
05
11
Function
Functions indicored on PET overlay and the chart below
..
Hexidecimal
Abbreviation
RP
RB
RD
WP
WB
WD
SRF
SRB
SFF
SFB
E
WM
RI
RO
R
Command
Read packed
Qb
Read binary
Read BCD
Write packed
Write binary
Write BCD
Space record forward
Space record backward
Space fi Ie forward
Space fi Ie backward
Set erase
Wri te tape mark
Rewind and interrupt
Rewind off-I ine
Rewind on-line
Re~resentation
02
-ee--OE
01
05
OD
14
lC
15
ID
16
17
11
12
13
Switch
Position*
00010
011QQ
01110
00001
00101
01101
10100
11100
10101
11101
10110
10111
10001
10010
10011
~ 40
* 1 = up; 0 = down
CTR
COUNTER
OUTPUT 0
Must be in up position for PATTERN CTR switches to be effective. If
CTR is in down position, data pattern is controlled by DATA PATTERN
switches
DEV ADDR
DAl
DA2
DA3
DATA CONTROL
4
5
6
Selects station address. DAl is most significant switch, and DA3 is
least significant switch. Station address is selected by the binary
setting of the DEV ADDR switches and the UNIT SELECT switch on the
station operator control panel
DATA PATTERN
DATA CONTROL
Determines data patterns for all station channels. See table 4-15 for
switch combinations
PATA
PATB
PATC
PATD
o
1
2
3
(Conti nued)
4-29
SDS 901013
Table 4-16. PET Functions (Cont.)
Function
Overlay Desi gnati on
Panel Desi gnation
PATTERN CTR
COUNTER OUTPUT
4
5
6
7
CO
C1
C2
C3
C4
C5
C6
C7
Determines data for channels 0-7. If switch setting is ONE or ZERO,
sets up data. If switch setting is COUNT, data to channel corresponds
to coun ter output
8
9
10
11
0
Determines record length for a write operation. Switch 2 is the most
significant, and switch 211 the least significant switch. With all
switches UP, 8 bytes are written on tape. Write count can be incremented in multiples of 8 bytes. In the packed mode, 4 characters on
tape are equivalent to 3 bytes from the PET/lOP
COUNTER RESET
RECORD LENGTH
2y
f
20
11
PET ON-PET OFF/
RESET
SELECTOR
In OFF position, resets controller. In ON position, enables PET
operations
RUNNING MODE
DEBOUNCED
Controls tape motion as follows: RP ON, FB OFF. Continuous mode.
Selected operation is repeated until RP is turned OFF or tape runs
out. Tape wi II not stop at EOT marker
1
2
RP
FB
RP OFF, FB ON. Single cycle mode. Selected operation is repeated
16 times, tape spaces backward 16 times, and unit returns to idle state
RP ON, FB ON. Continuous cycle mode. Same as single cycle mode
except unit repeats operation continuously rather than going into idle
state
RP OFF, FB OFF. Single order mode. One operation is executed
and unit returns to idle state
ST/START
Initiates selected operation. Operation is started when switch is
released
3
NORMAL/COUNTER
RESET
RESET DEV/INT
Connects device reset signal to 12-stage binary counter. Must always·
be in UP position
NORMAL CLOCK
COUNTER CLOCK
DEV/INT
Allows device clock to increment counter in PET. Must always be
in UP positi on
Table 4-17. Overlay Indicators
,
Overlay
DATE
FF1
Description
PET
14
Data error. A data parity error may consist of a lateral or longitudinal parity error in
both read and read after write, or of a cyclic redundancy check mismatch error during
reading
9
Ma jor phase determ i nate. It is used in conjunction with FF2 to determine major phase
of controller
(Conti nued)
4-30
SDS 901013
Paragraph 4-64
Table 4-17. Overlay Indicators (Cont.)
Overlay
PET
Description
Ma jor pha se determ i na te. It is used in conjunction with FF1 to determine major phase of
controller. The indications show the major phase the controller is in
10
FF2
FF1
FF2
Major Phase
0
0
OOF
0
1
01F
1
1
03F
-
FU1, FU2, FU3
11, 12, 13
-
Subphase or minor phase determinate of controller. The various combinations below are
possible:
FU1
FU2
Minor Phase
0
0
OOU
0
1
01U
1
0
02U
1
1
03U
RATE
15
Rate error. A rate error can occur during a read or write operation
BFRO-BFR7
0-8
Read data. Used to indicate data pattern being read in each of 9 channels. Due to
frequency and pulse width, indicators do not turn on. It is necessary to patch into oneshot circuit. (AUX1 or AUX2) to get an indication of the data pattern
Note
To keep the tape path aligned and to prevent
loss of air pressure, the casting and guide base
must be absolutely clean before replacement.
h. After applying a thin coot of silicone grease to the
base of the guide to ensure an airtight seal, replace the
spring and secure the guide housing to the main casting.
I
CAUTION}
To assure an unimpeded flow of cushioning air
and to prevent tape contamination, the ceramic
cap and guide upper surface must be absolutel y
clean before replacement.
i.
Replace the ceramic cap and tighten the guide
mounting screw until the O-ring is compressed.
Note
Guide housings are not interchangeable due to
the different tape wrap positions, so the correct
guide mtlst be speci fied during replacement. All
other parts are identical for each assembly.
4-64 Write Enable Switch Removal and Replacement
(See fi gure 3-11)
To completely remove the write enable switch .assembly,
the reel motor-ree I brake assembly must fi rst be removed.
(See paragraph 4-73.) Proceed as follows:
a. Disconnect the two plastic tubes connected to the
write enable switch housing at the rear of the main casting.
b.
Loosen one of the collet mounti ng screws.
c.
Loosen the collet clamping screw.
d.
Remove write enable switch assembly.
e. Using internal circlip pliers, remove the circlip
from write enable switch housing.
f.
Remove piston rod assembly and spring.
g. Assemble with replacement parts by reversing this
procedure.
h. The front face of the write enable switch assembly
should be set by means of the collet approximately 0.03 in.
from the rear face of the holddown knob housing, with the
holddown knob assembly in its pressed position.
4-31
SDS 901013
Paragraphs 4-65 to 4-66
m.
Note
The position of the write enable switch assembly may be adjusted without removing any
parts by means of the collet ciampi ng screw
and collet mounting screw.
Replace the drag brake spring.
n. Install the replacement outer friction disc, holding
the disc against the spring by means of a piece of string
(see figure 4-8).
Note
4-65 Reel Motor Brake Removal and Replacement
(See fi gures 4-7, 4-8, and 4-12)
Only one face of the inner and outer friction
disc will wear, due to the drag brake. The
life of the friction discs may be extended by
reversing the discs duri ng replacement.
The following test equipment is required for this procedure:
a. Dc power supply, 40 volts at 0.3 amp (the +25 and
-25 internal station supply may be used).
b.
0.010-in. thickness gauge.
c.
0- to 16-oz spring scale.
The procedure for removal and replacement is as follows:
a.
Open the sliding front door.
b. Disconnect the reel motor brake electrical connecti ons. (See fi gure 4- 13.)
c. Connect the brake electrical connections to an
external power supply or across the +25 Vdc and -25 Vdc
i nterna I sta ti on supp I y.
d. With power applied, remove the four screws from
the rear of the brake housing. Remove the brake assembly
from the ree I motor.
I
CAUTION
i
The drag brake spring will release the outer
friction disc from the spl i ne hub once the
magnet and sleeve assembly are removed.
e. Remove the drag brake spring, fixed spacer, and
inner friction disc.
f.
Remove the four mounting screws from the end
plate. Secure the end plate to the brake housing, using
the four long screws.
g.
Power may now be safely removed.
h.
Apply power to the replacement brake assembly.
i.
Remove the four long screws from the rear of
brake assembly.
j.
Remove the end plate from the brake assembly and
install the plate on the reel motor.
4-32
k.
Install the replacement inner friction disc.
I.
Replace the fixed spacer.
o. With power applied to the brake, a second person
should mount the magnet and adjusting sleeve assembly
while the outer friction disc is held in place.
p. The string should pass through the slots in the
adjusting sleeve, so that it can easily be withdrawn once
the magnet and sleeve assembly are mounted.
q.
Remove the stri ng.
r. Adjust the air gap between the armature and magnet pole piece, as described in paragraph 4-66.
s.
Reconnect electrica I connections.
4-66 Reel Motor Brake Adjustment
Adjust the reel motor brake as follows:
a. With no power applied to the brake, measure the
air gap between the magnet pole piece and the armature,
using a feeler gauge inserted through one of the four cutouts around the brake adjustment sleeve. The gap should
be .0lD in.
b. Usi ng i nterna I or externa I power, energi ze the
brake (dc power supply 40V at 0.3 amp if external power
is used).
c. Slacken the four screws at the rear of the brake
housi ng approximately three turns each.
d. To increase the air gap between the magnet pole
piece and armature, rotate the adjustment sleeve clockwise
as viewed from the rear (counterclockwise wi II decrease the
gap). A quarter turn of the adjustment sleeve approximates
a change of .015 in. in the gap between the magnet pole
piece and the armature.
e. Tighten the four brake housing screws and remove
power to the bra ke .
Never remove power to the brake un less the
four brake housing screws are secure.
f. Check the armature air gap and repeat the procedure if necessary until the gap is .0lD in.
SDS 901013
REEL MOTOR
SPLINE HUB \
END PLATE
./
FIXED
SPACER
DRAG BRAKE
OUTER
FRICTION
DISC
SPRING
Figure 4-7. Reel Motor Brak e, Exploded V·lew
4-33
SDS 901013
-STRING---~'
~-~---
FIXED SPACER
END PLATE
OUTER
FRICTION
DISC
ADJUSTING
SLEEVE
/
/
900837A. 17
Figure 4-8. Reel Motor Broke, Reassembly
4-34
SDS 901013
Paragraph 4-67
4-67 File Reel Holddown Knob Removal and Replacement
(See figures 4-9 and 2-5)
Note
The slider pins have a slight taper with a 1/8in. long parallel portion at one end. This end
is nearest the turntable and care should be taken
to reassemble in the same position.
Perform the following steps:
a.
Remove the three screws holding the cover.
f. Remove the three screws holding the slider pins
and withdraw the slider pins from the housing. The housing
is now loose.
b. Withdraw the cover locating pin assembly and
shim located behi nd the cover.
c. Remove the locating pin from the cover only if
replacement is required.
g. Remove the rubber ring from the housing only if
replacement is required.
d. Remove the three-shoe pivot, pin pivot arm
assembl ies.
h. It is not necessary to remove the pivot arm post to
remove the reel brake assembly from the transport. If removal of the pivot arm post is required, remove the three
screws, then remove the post.
Note
Do not turn pivot arm unless necessary; if the
arm is turned, the unit wi II have to be readjusted on assembly.
i. All parts should be thorough Iy c leaned before
replacement.
e. Dismantle the shoe pivot, pin pivot arm assembly
only if replacement is required.
j.
Replace parts by reversing thi s procedure.
LOCATING
PIN
PIVOT ARM
POST
COVER
PIVOT ARM
SHIM
PIVOT PIN
SLIDER
PIN
SHOE
RUBBER
RING
HOUSING
TURNTABLE
MOTOR
SHAFT
900837A. 18
Figure 4-9. File Reel Hub
4-35
SOS 901013
Paragraphs 4-68 to 4-69
Note
k. Apply a thin coot of silicone grease to the slider
pins, pivot arm knuckle joints, and locating pin before
replacement.
I. If the rubber ring shows signs of wear at the point
where the shoes react, rotate the rubber ri ng 60 degrees
with respect to the housing.
m. Before tightening the slider pin screws, locate the
adjustment fixture reference pin in the pivot arm post to
maintain concentricity between the housing and the pivot
arm post.
n.
For reel replacement only, the adapter assembly need not be removed.
4-69 Reel Tachometer Removal and Replacement
(See fi gure 4-19)
The following test equipment is required for this procedure:
a.
Special alignment fixture
b.
0.015-i n. thickness gauge
Insert shoe pivot, pi n pivot arm assembl ies.
Note
If no replacements have been made on the
shoe pivot, pin pivot arm assembly, no adjustment will be required during assembly.
However, if any part of the assembly has
been replaced, the adjustment fixture must
be used to reset the correct length of the
pivot arm.
o. The correct length of the pivot arm is set by rotating the pivot arm, which is threaded into the pivot pin.
Flats are provided on the pivot arm for this purpose.
Perform the following procedure for removal and replacement:
a.
screws.
Note
Only one of the two reel tachometer collet
mounting screws will be readily acce~sible;
looseni ng either will suffice.
b.
p. After assembly, the holddown knob should be
tested for holding torque greater than the reel brake torque,
and for concentricity of the reel during rotation.
q. Individual adjustment of the pivot arms determines
the concentricity of the reel, and equal adjustment of all
the pivot arms determines the reel holding torque. Both
conditions are satisfied if the adjustment fixture is used.
Loosen one of the reel tachometer collet mounting
Loosen the collet clamping screw.
Note the polarity of the electrical connections. The tachometer terminals are marked
1 and 2; be careful during replacement not
to switch the lead connections.
c. Remove the electrical connections to the tachometer at the rear of the mai n casti ng. (See fi gure 4-13.)
Note
d.
Only the cover-locating pin assembly and
shim need be removed to adjust the holddown
knob using the adjustment fixture.
4-68 Fixed Reel Removal and Replacement
Proceed as follows:
4-36
a.
Remove the three screws holding the cover.
b.
Withdraw the cover and the backup washer.
c.
Remove the fi xed ree I.
d.
Remove the adapter assembly.
e.
Replace parts by reversing this procedure.
e.
pulley.
Remove the tachometer pulley assembly.
Loosen the tachometer pulley screw and remove the
f. Attach the pu Iley to the replacement tachometer
using a O.015-in. feeler gauge to set the gap between the
pulley flange and the front flange of the tachometer.
g. Place the tachometer pulley assembly in the collet
and tighten the collet clamping screw so that the tachometer
pulley assembly can just slide within the collet with a small
force appl ied.
h. Remove the four screws holding the top outer cover
of the chamber.
i. Set the position of the tachometer pulley assembly,
using the special alignment fixture.
SDS 901013
Note
Never
pulley
on the
pulley
adjust the position of the tachometer
by adjusting the position of the pulley
tachometer shaft. Always adjust the
position by means of the collet.
j. The special alignment fixture sets the position of
the lower inside tachometer pulley flange with respect to
the chamber base.
k.
Tighten the collet clamping screw.
I.
Ti ghten the collet mounti ng screw.
m. Replace the tachometer electrica I connections
{note polarity~.
n.
g. Remove the four screws holding the capstan motor
while a second person holds the motor assembly at the rear
of the transport; then place the motor on a workbench.
h. Remove the two screws holding the capstan motor
housing cover and remove the cover.
i.
Remove the two cover spacers.
j. Remove the seven screws holding the capstan motor
cooling shroud and remove the shroud.
k. Loosen the tachometer coupl i ng screw and remove
the tachometer and coupl i ng.
I.
Remove the capstan tachometer mount.
m.
Remove the rubber gasket from the capstan motor.
Replace the top outer cover of the chamber.
o. Using a length of tape pulled tightly across the
tachometer pulley and the adjacent guide, check to determine that the tape edge does not interfere with the chamber
base or cover.
4-70 Capstan Motor Removal and Replacement
(See fi gure 4-10)
Proceed as follows to remove and replace the capstan
motor:
a. Remove the fixed reel, following the procedure
listed in paragraph 4-68.
b. Remove the overlay panel directly behi nd the
capstan by removi ng the three screws at the rear of the
transport casting.
c.
Paragraphs 4-70 to 4-71
n. Use new rubber gasket on the replacement capstan
motor, making sure that the windows in the gasket correspond to the cooling hole segments in the motor.
o. Replace the tachometer coupling and the tachometer. (See capstan tachometer removal and replacement
procedure in paragraph 4-71.)
p.
Replace the tachometer mount.
q.
Replace the cover spacers and cover.
r.
Replace the cooling shroud.
s.
Mount the motor.
t. Replace the capstan, using two new rubber
washers.
u.
Replace the overlay panel.
v.
Reconnect the vacuum tubing.
Remove the capstan securing screw.
f : ~AUTION ~
f
Two flats on the capstan motor shaft immedibehind the capstan enable the shaft to
be held by an adjustable wrench. In making
adjustments, never hold the capstan, as it
can easily be damaged.
atey
d. Remove the capstan and two rubber washers, one
on either side of the capstan.
e. Disconnect the two flexible tubes from the capstan motor cooling shroud nipples.
Note the polarity of connections.
f. Disconnect the motor and tachometer electrical
connecti ons a t the term ina I boards.
w. Reconnect the motor and tachometer electrical
connections.
4-71 Capstan Tachometer Removal and Replacement
(See fi gure 4-10)
Proceed as follows to remove and replace the capstan
tachometer:
a. Remove the two screws holding the capstan motor
housing cover.
L
CAUTION
I
Note the polarity of the electrical connections. The tachometer terminals are marked
1 and 2; be careful during replacement not
to switch the lead connections.
b. Remove the electrical connections to the
tachometer.
4-37
Paragraphs 4-72 to 4-73
SOS 901013
CAPSTAN MOTOR
HOUSING
CAPSTAN MOTOR HOUSING
COVER
TACHOMETER
MOUNT
'-'--=-~-TT-----ir---
TAC HOMETE R
BLACK WIRE
TACH
COUPLING
TACHOMETER
(DWG 111606C)
900837A.19
Fi gure 4-10. Capstan Tachometer Mounting Position
c.
Loosen the tachometer coupling screw.
d. Remove the tachometer, sliding the mount grommet
across the tachometer housing.
e. Insta II the replacement tachometer by reversi ng
this procedure.
f
CAUTIO~
1
The position of the capstan tachometer and
tachometer coupling is important. (See
figure 4-10.)
4-72 Positive Pressure Pump Removal and Replacement
(See fi gure 4-20)
Proceed as follows:
a.
outlet.
Disconnect the plastic tube fitting at the pump
b. Disconnect the electrical connections to the pump
at terminal board A, pins 5 and 7. (See figure 4-21.)
c.
4-38
Remove the four screws holding the pump.
d.
Remove the air filter from the pump inlet.
e.
Replace the air fi Iter on the replacement pump.
f.
Reverse this procedure for pump replacement.
i
CAUTION
I
Exami ne the nylon 01 ive at the pump output
fitting for damage. If it is damaged, replace it.
4-73 Reel Motor Removal and Replacement
(See fi gure 4-12)
Proceed as follows to remove and replace the reel motor:
a. Remove the electrical connections from the reel
motor and brake.
b. Before removing the file reel motor, remove the
file reel (paragraph 4-67).
c. Before removing the fixed reel motor, remove the
fixed reel (paragraph 4-68).
SDS 901013
Paragraphs 4-74 to 4-78
d. Remove the motor brake by following the procedure listed in paragraph 4-65 steps a through d.
4-75 Photosense Removal and Replacement
(See figure 4-14)
e. Remove the four corner screws that secure the
motor mounting bracket to the main casting, and lift the
motor away from the casti ng.
Proceed as follows for photosense removal and replacement:
f. Insta II the replacement motor by reversi ng the
remova I procedure.
4-74 Read/Write Head Removal and Replacement
(See fi gure 4-17)
CAUTIO~ ~;
Care must be taken at all times to avoid
damage to faces of the read/wri te heads.
a. Disconnect the electrical connections to the photosense at terminal board TB5T, pins 4to 11, inclusive.
b. Remove the photosense mounting screw from the
rear of the main casting.
c. Remove the photosense assembly, passing the electrical leads and connectors through the clearance hole in
the main casting.
d. Install the replacement photosense assembly by
reversing this procedure.
e. Adjust the lamp intensity as descri bed in paragraph 4-22.
Proceed as follows:
a. Disconnect the two read/write head connectors
at rear of transport casti ng.
b. Remove the overlay panel directly behind the
capstan (three screws at the rear of the transport casti ng).
c. Remove the three screws holdi ng the read/write
head assembly.
d. Remove the read/write head assembly by passing
the connectors through the openi ng in the transport casti ng.
e. Remove the four screws holding the head cover to
the baseplate.
f.
Remove the head cover.
g.
Remove the tape c leaner assembly (one screw).
h. Mount tape cleaner assembly on the replacement
head assembly.
i.
Replace the head cover assembly.
j. Pass the connectors through the opening in the
transport casting.
k.
Secure the read/wri te baseplate to casti ng.
I.
Connect the read/write head connectors.
m.
Replace the overlay panel.
Note
No mechanical shimming is required after
replacement of the read/write assembly.
Note
Damaged photosense assemblies should be
returned to SDS for repair.
4-76 Erase Head Removal and Replacement
(See fi gure 4-16)
Proceed as follows to remove and replace the erase head:
a. Disconnect the erase head wires from TB 1 on the
head cable assembly. (Observe polarity.)
b. Remove the erase head mounting screw from the
front of the tra nsport.
c. Remove the erase head, passing the wires and terminals through the clearance hole in the main casting.
d. Install the replacement head by reversing this
procedure.
e. Adjust the erase head position as described in
table 4-4.
4-77 PARTS LIST
The tables and figures in this section list and illustrate the
replaceable parts in the magnetic tape system.
4-78 TABULAR LISTINGS (Tables 4-18 through 4-44)
The replaceable parts are arranged in parts I ist tables.
Table 4-18 lists the main assemblies of the equipment.
Each main assembly is then broken down into subassemblies
or component parts. Breakdown by table continues until
all replaceable parts down to a field replaceable level
4-39
SDS 901013
Paragraphs 4-79 to 4-80
have been listed and illustrated. Each parts list table is
arranged in six columns, as follows:
f.
The quantity of the part used per assembly
4-79 ILLUSTRA nONS (Figures 4-11 through 4-28)
a.
The figure number of the listed part
b.
A brief description of the Part
Each parts list is accompanied by a figure showing parts
placement for that list. Also shown in some cases are
schematic diagrams for assemblies.
c. The reference designator of the part as shown on
the schematic diagram for that part
d.
The manufacturer's code for the part
e.
The manufacturer's part number for the part
4-80 MANUFACTURER CODE INDEX (Table 4-45)
The manufacturers of parts Iisted in this section are indicated by code numbers. Their names and addresses are
shown in the manufacturer code index (table 4-45).
Table 4-18. Magnetic Tape System
Fig. No.
Description
Reference
Designator
Manufacturer
Part No.
Qty
Magnetic Tape System 7371/7372/
7374 *
5DS
133665
1
· Tape Transport Assembly (See table 4-19
for replaceable parts)
5DS
131296
1
4-20
· Blower Shelf Assembly (See table 4-27
for replaceable parts)
SDS
113779
1
4-22
· Operator Control Panel Assembly (See
table 4-28 for replaceable parts)
SDS
123145
1
• 28" Cabinet Assembly (See table
4-29 for replaceable parts)
SDS
124361
1
· Front Door Assembly (See table 4-44
rep laceab Ie parts)
SDS
124371
1
4-11, 4-12
1-1, 1-2
1-1
*See figure 4-2 for wiring diagram
4-40
SDS 901013
PHOTOSENSE
WRITE-ENABLE
SWITCH
ACTUATOR
TAPE GUIDE (-004)
TAPE GUIDE (-002)
CAPSTAN
ERASE HEAD
REEL TACHOMETER
(2 REQUIRED)
TAPE GUIDE (-005)
"
'"
~
\,
,,~
SWI NGI NG DOOR
INTERLOCK
VACUUM CHAMBER
(FIXED)
"
"
VACUUM
CHAMBER
(FI LE)
~,
NOTE: REFERENCE SOS DWG: 131296-10
901 084A. 601
Figure 4-11.
Transport Front View
4-41
SDS 901013
DIODE
IN3189
CAPACITOR
0.01 \JF
CAPACITOR
o. 1 \JF
TRANSPORT
CASTING
REEL MOTOR
AND BRAKE
(2 REQUIRED)
TERMINAL
BLOCK (-017)
CAPSTAN MOTOR
REEL TACHOMETER
(2 REQUIRED)
PRESSURE
REGULATOR
PRESSURE
SWITCH
AUXILIARY
CONTROL PANEL
•
SWINGING DOOR./"
INTERLOCK
/
TERMINAL
BLOCK (-016)
TERMINAL
BLOCK (-011)
AIR FILTER
MAGNETIC
HEAD COVER
ACTUATOR
NOTE: . REFERENCE SDS DWG: 131296-2D
901084A.602
Figure 4-12.
4-42
Transport Rear View
SDS 901013
Table 4-19. Magnetic Tape Transport Assembly, Replaceable Parts
Reference
Designator
Part No.
Qty
SDS
131296
Ref
• Photosense Assembly (See table 4-20
for replaceable parts)
SDS
111776
1
4-15
• Capstan Motor Assembly (See table 4-21
for replaceable parts)
SDS
111599
1
4-12
Brake Assembly (See table
·4-22ReelforMotor
replaceable parts)
SDS
111469
2
4-18
• Auxi liary Control Pane I Assembly
(See table 4-23 for replaceable parts)
SDS
116080
1
4-19
• Reel Tachometer Assembly (See
table 4-24 for replaceable parts)
SDS
116220
2
4-11
· Fixed Vacuum Chamber Assembly (See
table 4-25 for replaceable parts)
SDS
113485
1
4-11
· Fi Ie Vacuum Chamber Assembly (See
table 4-26 for replaceable parts)
SDS
114589
1
3-9
• Actuator, head cover
SDS
116111
1
· Assembly, head cable
SDS
123146
1
• Block, terminal, 2-screw
(5 DS 100094-011)
51
141
3
• Block, terminal, 2-screw
(SDS 100094-016)
51
141
1
• Block, terminal, 2-screw
(SDS 100094-017)
51
141
1
• Capacitor, Mylar, O. 0 1 tJ F 10010, 80V
(5 DS 100308- 103)
25
64F
1
· Capacitor, Mylar, 0.01 tJF 10010, 80V
(SDS 100308-104)
25
64F
1
· Capstan, 2.8 in. dia
SDS
107827
1
· Diode, silicon (SDS 101164)
5
IN3189
2
3-8
• Guide, tape
SDS
111342-001
1
3-8
• Guide, tape
SDS
111342-002
1
3-8
• Guide, tape
SDS
111342-003
1
Fig. No.
Description
4-11, 4-12
Magneti c Tape Transport (See table 4-18
for next higher assembly)*
4-14
Manufacturer
* See figure 4-13 for wiring diagram
(Continued)
4-43
SDS 901013
Table 4-19. Magnetic Tape Transport Assembly, Replaceable Parts (Cont.)
Description
Fig. No.
4-44
Reference
Designator
Manufacturer
Part No.
Qty
3-8
· Guide,
tape
SDS
111342-004
1
3-8
• Guide, tape
SDS
111342-005
1
4-16
• Head, erase
SDS
123381
1
4-17
• Head, magnetic, 7-channel
SDS
134019
1
3-7
• Regulator, pressure (SDS 111765)
360
AA325
1
3-10
• Switch, pressure (SDS 113707-001)
361
· Switch, snap action
SDS
109372
1
• Switch, snap action
SDS
114285
1
3-19
• Switch, vacuum
SDS
113691-100
1
3-11
• Switch, write enable
SDS
111767
1
222-240-9591
1
SDS 901013
1I
FILE
MOTOR
l2
BRAKE
TBID-E- e
BRAKE
FIXED
YOTO"
TBID-E-IO
BLUE
GREEN
TBID- E-4
TBID- E-~
GREY
GREY
GREEN
BLUE
CR4
CI
T910-E -7
---,
r---S6T
POS. PRES. SWITCH
r- -- ---1
t
r------,
S5T
I
r-----,
I
I
I
I
I
I
I
I
I
S2C
SWINGING
!
DOOR SW
.N~C~~______~
I
I
S4T
&---~------~
NO
I
116080 REF
FWD
ISIT
I
I
I
IS2 T .......--o---+-_---J
~-+-t-P208-47
I
SIC
IS3T
L __ _
114589 RE F.
L _______
J'
TB2T-IO
P208-22
L
113485 REF.
I
_____ J
NOTE: REFERENCE SDS DWG: 131298-1C
Figure 4-13. Transport Wiring Diagram
90 1084A. 705
4-45/4-46
SDS 901013
Table 4-20.
Photosense Assembly, Replaceable Parts
Reference
Designator
Part No.
Oty
SDS
111776
Ref
• Board, terminal
SDS
113170
1
• Cover, photosense
SDS
111780
1
363
D39
1
5
21DF2
(1)
2
Fig. No.
Description
4-14
Photosense Assembly (See table 4-19 for
next higher assembly)
• Lamp, incandescent, 5V
unbased (SDS 111778)
• Transistor, npn, photocondi tioned
(SDS 224)
DS1
01, 02
Manufacturer
4-47/4-48
SDS 901013
LAMP,
INCANDESCENT
: : :J
3
2
4
5
6
IBI
,_
FOR WIRING REF ONLY
TRANSISTOR Q1
~--21
1 I N. REF
IN.
~-----------25IN.REF----·-----------------------
tMRE~
,
r 1
TERMINAL BOARD
IS
, '
I
I
,-,
1
II~II
2
3
__ ~~\~QA3_-
4
5
6
I
I
I
I
7
1
I
I
8
I
I
I
I
I
I
1 I
In ,J
~~::::::...
I
!y, rI
-::. =.~~=
SOL
<)
ID
II
12
13
14
INSERT
SOLDER
T::R~t
SOL
FRQ\1
TO
iTERM "'II~~ TYPE
U;)
DSIT-E-i
T 81-E-3 SOL
DSiT-E-2 T &1-:::-4
QIT-£-E
T81-E-1
QIT-E-C
TSI-:::-2
Q2T-E-( TBI-:::-5
Q2T-E-C TBI-::-6 SOL
T81-E-3 T85T-;4 ~D
T81- E-4 TB5H-5
TS5T-E-7
T81- E-I
5
T81- E-2 .. T85T-E-6
TB5T-=-9
TBI-~5
T65T- E-8
TE~I-E-6
IJ
SHI!:L-R- ~T-E-C
!I
C,HltLO
T E">T-"-II fill
."
CC..DR II()TE.S
TAG
~HITE
A-
6LACI< ~.~
NHITE
BLACK ~
Q2
QI A6
VIEW 1~-13
NOTES: 1. RED DOT INDICATES COLLECTOR LEAD.
USE CLEAR TEFLON TUBING OVER RED DOT
2. REFERENCE SOS OWG: ll1n6-lE
Figure 4-14.
Photosense Assembly
90 1084A. 606
4-49/4-50
SDS 901013
Table 4-21.
Fig. No.
4-15
Capstan Motor Assembly, Replaceable Parts
Description
Reference
Designator
Manufacturer
Part No.
Qty
Capstan Motor Assembly (See table 4-19
for next higher assembly)
SDS
111599
Ref
• Butterfly, motor housing
SDS
116713
1
• Coupling, tachometer
SDS
111606
1
• Gasket, manifold
SDS
111601
1
• Grommet, rubber, housing cover
SDS
100720-005
1
• Grommet, rubber, tachometer
SDS
100720-010
1
• Motor, capstan
SDS
108057
1
• Mount, tachometer
SDS
111605
1
• Spacer, capstan housing
SDS
116143
2
• Spindle, motor housing
SDS
116714
1
• Tachometer, capstan
SDS
111829
1
4-51
TACHOMETER
MOUNT
SPACER
TACHOMETER
GROMMET
TACHOMETER
MANIFOLD GASKET
HOUSING
COVER
GROMMET
"'T1
BLACK WIRE
cO'
c
CD
,
~
lT1
\
CAPSTAN MOTOR
WIRE
NO.
FROM
FRONT MTG HOLE REF
DESTINATION
Vl
1.5°1
~_~=Cl~O
COLOR
CODE
TBlT -E-15
2
TBIT-E-14
RED
3
SHIELD
TBIT -E-13
WHITE
4
ITEM 4
TERM 2
TB5T -E-l
WHITE
2.00
TB5T -E-2
BLACK
6
SHIELD
TB5T -E-3
WHITE
NOTE: REFERENCE SDS DWG: 111599-1C
WIRE NO.1
lit\..
~-tL
WIRE NO.6
t '" WIRE NO.4
WIRE NO.5
lTEM 4
TERM 1
.
~ WIRE NO.2
~I WIRE NO.3
BLACK
5
Vl
CJ
-0
MOTOR HOUSING
---
1
TACHOMETER
COUPLING
CENTER HOLE ON
MOTOR CASE
o
o
(,J
BUTTERFLY
r
:1
0950~ 0470'
~
f
e
0.125
i
----r
+0.005
~ 0.116 -0.004
FUll R
TYP
"T1
co
c
'--_ _ l.S00 _ _ _~_ _ _ _ _ 1O·00±0.25
CD
TYP
~
I
?'
a
0.225
CD
.,.---
~
+0.005
0.540 -0.000
o
I
1.125
Vl
-.0
========~~~~-------c~o
0.28 MAX
TYP 1
~
0.835
t
0.25 MIN
t
NOTE s:
iJ
~
1--0.250
1. INSULATED RING TONGUE TERMI NAL FOR #6-32NC
2. TOLERANCES TO BE XX 0.010
XXX 0.005
3. NORTH SEEkiNG END OF COMPASS WILL SEEK THIS
CORE HALF WHEN CURRENT ISAPPLIED
4. REFERENCE SDS DWG. 123381 F
Vl
a
3
m
1.50±0.12
TYP
-.-r 0.28 MAX
-.
TYP
o
o
w
SDS 901013
GUIDE SOCKET
PIN 'A' REF
GUIDE SOCKET
~
MOUNTING PLATE
(TANGENT POINT
OF STACK RADIUS)
CHANNEL
P
HEAD COVER
1
TAPE ClEANER
'}
iJDO NOT IIIAIIIC ON
~
FACE 0' """T.
3
4
READ
WRITE
COLOR HEAD TO PI HEAD TO P2
WHT
B
B
BLK
D
A
A
B/W
D
F
F
E
J
E
J
L
L
N
K
j(
N
R
R
P
T
P
T
V
V
X
U
X
U
Z
5
HEAD GATE REMOVED FROM THIS
VIEW FOR CLARITY
6
WHT
BLK
B/W
GRD
-
Z
Y
BB
DD
CC
FF
BB
Y
DD
FF
CC
C
C
B/W IS CENTERTAP
NOTES: UNLESS OTHERWISE SPECIFIED
WRITE CABLE LENGTH IS 8.00 %0.50 MEASURED FROM
SURFACE "A" TO THE END OF THE CONNECTOR
CABLE CLAMP
FOR MAG HEAD SPEC SEE DWG 134022
DIMENSION TO CENTERLINE OF ACTIVE CHANNEL NO.6
WHEN THE HEAD GATE IS IN THE CLOSED POSITION.
THE MYLAR SIDE OF THE MAGNETIC TAPE (INCLUDING
SPLICES, REFLECTIVE TAPE ETC) SHALL NOT TOUCH THE
SURFACE OF THE HEAD GATE OR SHIELD.
MAINTAIN A MINIMUM CLEARANCE OF 0.010 INCH
CHANNEL NO.6 IS THE ACTIVE CHANNEL FARTHEST
FROM THE BASE PLATE
o
TAPE WRAP ANGLE TO BE 80 ~:/~ FOR ALL TESTS
NO HARDWARE OR OTHER OBJECTS SHALL
PROTRUDE BELOW SURFACE -A-
EACH TRACK AND TOLERANCE SHALL REFERENCE TO
THE BOTTOM OF THE BASEPLATE
TRACK NO. AND TO BASEPLATE
P
0.8950
± 0.0015
0.9650
± 0.0015
I
± 0.0015
1.035
2
1. 105
%.0.0015
3
4
1.175
± 0.0015
5
1.245
± 0.0015
±.0.0015
6
1. 315
COVER GATE SHALL BE HELD CLOSED BY EXTERNAL
ACTUATOR. GATE TRAVEL SHALL BE 6(1J WITH
POSITIVE STOP IN OPEN POSITION
READ CABLE LENGTH IS 9.00 ± 0.50 MEASURED FROM
SURFACE "A" TO THE END OF THE CONNECTOR
CABLE CLAMP
II.
REFERENCE SDS DWG : 134019-lC
901013A. 403
Figure 4-17.
4-54
Read/Write Head Assembly
SDS 901013
Table 4-22.
Fig. No.
4-12
Reel Motor Brake Assembly
Description
Reference
Designator
Manufacturer
Part No.
Qty
Reel Motor Brake Assembly
(See table 4-19 for next higher assembly)
SDS
111469
Ref
. Disc, friction
SDS
132779
2
,
,
(
4-55
SDS 901013
Table 4-23. Auxiliary Control Panel Assembly, Replaceable Parts
Fig. No.
4-18
Description
Reference
Designator
Manufacturer
Part No.
Qty
Auxiliary Control Panel
(See table 4-19 for next higher
assembly)
SDS
116080
Ref
• Bumper, rubber
SDS
116083-005
1
SDS
116082
1
• Switch, interlock
SDS
111757
1
• Switch, pushbutton, spdt
113
101076-001
3
·
Push rod, door interlock
SWINGING DOOR
INTERLOCK SWITCH
INTERLOCK SWITCH
MOU NTI NG BRAC KET
RUBBER
BUMPER
PUSHBUTTON
SWITCH
(3 REQUIRED)
NOTE: REFERENCE SDS DWG: 116080-1 E
90 I084A. 608
Figure 4-18. Auxi I iary Control Panel Assembly
4-56
SDS 901013
Table 4-24. Tachometer Assembly, Replaceable Parts
Fig. No.
4-19
Reference
Designator
Description
Manufacturer
Part No.
Qty
Reel Tachometer Assembly (See
table 4-19 for next higher assembly)
SDS
116220
Ref
• Collar, mounting
SDS
111608
1
• Pu Iley, ree I tachometer
SDS
111598
1
REEL
TACHOMETER
MOUNTING
COLLAR
SET
SCREW
CAP SCREW
o
c:= -_-_-=:J
900837A. 36
Figure 4-19. Reel Tachometer Assembly
4-57
SDS 901013
Table 4-25.
Fixed Vacuum Chamber Assembly, Replaceable Parts
Fig. No.
Description
Reference
Designator
4-11
Fixed Vacuum Chamber (See table 4-19
for next higher assembly)
Part No.
Qty
SDS
113485
Ref
Manufacturer
· Switch, vacuum
Sl
SDS
113691-400
1
· Switch, vacuum
S2, S3
SDS
113691-100
2
· Switch, vacuum
S4, S5
SDS
113691-200
2
Table 4-26.
Fi Ie Vacuum Chamber Assembly, Replaceable Parts
Fig. No.
Description
Reference
Designator
4-11
Fi Ie Vacuum Chamber (See table 4-19
for next higher assembly)
4-58
Part No.
Qty
SDS
114589
Ref
Manufacturer
· Switch, vacuum
Sl
SDS
113691-300
1
· Switch, vacuum
S2, S3
SDS
113691-100
2
· Switch, vacuum
S4, S5
SDS
113691-200
2
SOS 901013
Table 4-27.
Blower Shelf Assembly, Replaceable Parts
Fig. No.
Description
4-20
Blower Shelf Assembly (See table 4-18
for next higher assembly) *
• Block, terminal, molded barrier
(50S 100094-011)
Reference
Designator
TBl
• Blower, vacuum
Part No.
Qty
SOS
113779
1
51
141
1
SOS
111843
1
Manufacturer
• Capaci tor, ac, 25 fJF, 165V, 60 Hz
C1
50S
135116
1
• Capacitor, oi I impregnated, 1000 Vdc,
120 Vac, 60 Hz, bathtub
(5 OS 100992-005)
C2
189
CP53
1
· Elbow, connection (SOS 116702-001)
255
269-P
1
· Fi Iter, air
362
SYC1Z-1338
1
• Pump, positive pressure
SOS
111842
1
* See figure 4-21 for schematic
4-59
SDS 901013
CONNECTING
AIR FILTER
MOUNTING
BRACKET
TERMINAL
BLOCK
COVER
TERMINAL
BLOCK
TBl
CAPACITOR
"\RE
NO.
Tl':~M
FROM
TO
CIA-E-I
CI tI-E-2.
(9
(9
TBIA-E"-I
Z
~
ME:CH
T!31 A-E'2
TS:A-£-3
T8IA-E-4
TBIA-EO-5
TSIA-E"-5
Te:A-E-6
I
T3;1I-1:·2.
'l4IRE
TERM i"1PC:
5"JL
ff
SC.
~i)
Wle:::~
(Z4)
1
IT
T
(z4)
6
TI3I"-E- 7
TBIA-E-3
,
1
TBIA-E-e
T B IA-E"- 9
MEl:ti
4
5
I
-
0
8
BI A -£-8..',:::
TelA-E-1
'i
-00
C)
BIA-E"- R'3:0
TBIA-f:-2
"!
10
\I
1'2
13
14
BIAE"-'n,:,-.
TBIA-E-4
?
-
2
j~
L
VIEW
VACUUM
BLOWER
C2
10\- 10\
B2A-E-.·.H TB,A-E-5
8
-
MIOCH
B2AE- :=:_K
T6IA-E:-7
8
TAG
KIN-E-I
'("IN-E'- 2-
TSIA-E-€.
-
-
T8,A- E- 1
-
TAG
-
-
IS
ME:CH o2A-E-G<. ...
T:'IA-E-II
Ib
MEG.. TBIA-E- "
TBIA-::-~~D
"'E~H
17
50L
TBIAE.-"
('9)
12f
IS
SOL
TBIA'E:-7
q)
~
C2"'-E-I
C2A-E,- 2
8
~
NOTE: REFERENCE SDS DWG: 113779-1G
90 1084A. 604
Figure 4-20.
4-60
Blower Shelf Assembly
SDS 901013
TBIA
o
0
z
3
5
0
6
r---,
7
o
8
o
9
o
10
I
I
I
I 12
I
I
L _ _ _ --l
BOTTO" DOOR
SWITCH (REF)
I
0
I
L __ -1
SOLENOID
MOUNTED ON
VAC.PLENUM.
110
o
NOTE: REFERENCE SDS DWG: 130776-18
901084A. 703
Figure 4-21.
Blower Shelf Schematic
4-61
SOS 901013
Table 4-28. Operator Control Panel Assembly, Replaceable Parts
Fig. No.
Description
4-22
Operator Control Panel (See table 4-18
for next highest assembly) *
Reference
Designator
Part No.
Qty
SDS
133666
Ref
Cable Plug Module Assembly
P206
SDS
133028-023
1
Board, diode mounting
TB1
SDS
124802
1
232
SDS 115833
2
5
lN3189
7
203
lOE series
9
104
700-0135-004
1
Knob, skirted, black (SDS 126876)
364
PS-70SL-2 Blk
2
Lampholder, midget, flanged base
(5D5 116284-001)
203
10E series
9
Lamp, incandescent, 28V, midget
flanged base (S DS 101922)
83
CM387
16
Connector, 14-pin, coax-to-pw board
Diode, silicon, 200V, 750mA (5DS
101154)
CR1-CR7
Housing, lampholder (SDS 116283-001)
Indicator, segmented, red window
(SDS 126619)
DS10
SDS
133667
1
51
203
10EF3
1
52, 53, 54,
56, 57, 59
203
10EFl
6
Switch, rotary, 9-position, 3-deck
511
55
SDS 129857
1
Switch, rotary, 3-position
S12
55
SDS
111456-003
1
Panel, control, mag tape
Swi tch, 01 ternate action, dpdt,
(SDS 111455)
Switch, momentary, dpdt, (SDS 111459)
* See figure 4-23 for schematic
4-62
Manufacturer
SDS 901013
MOMENTARY SWITCH, LAMP,
LAMPHOLDER HOUSING AND
LAMPHOLDER
PANEL
MOMENTARY SWITCH, LAMPHOlDER
HOUSING AND LAMPHOLDER
KNOB
,8
A
Ne
0
~
NO
NO
0
•
c
c
•
•
II 5D5
ALTERNATE ACTION SWITCH, .
~MP, LAMPHOLDER H_OUSING
AND LAMPHOlDER
LA.~Pti()!DER HQ.~SI~G
LAMP,_
I I I II
CRi£NTA"TlOtJ Of SI
RE'AR VIew
&
A
NO
"0
•
0
He
He
INDICATOR
•
0
c
e
•
AND LAMPHOLDER
FRONT VIEW
•
-,...p QRIENTATION
OF S2,s~ 54,
S", 97 • $9
REAR. V1£W
CONNECTOR ASSEMBLY
2.011
,
3
tl
..
8
0
P206
0
'4
7
6
DIODE MTG BOARD TB1
2,1
S
9
~
DIODE (7 REQUIRED)
@
LON&-LEAD
10
5-12.
eEARVIEW
$11
REA~
VIEW
ROTARY SWITC H
C2
c::II
2
B
Ie
10
I
2
2
B 18
IA
I
2
c:::::II
TYPICAL PIN LOCATION
OF DS'
OSI
SI
052
52
053
DS4
S3
S4
055
DS6
S6
OS7
S7
DS8
THRU
OS8
S9
511
TOP VIEW
512
Figure 4-22.
Operator Control Panel Assembly
NOTE: REFERENCE SOS OWG: 133666- 1G,2E
90 10 13A• .u>6
4-63
SOS 901013
POWER
OSI
1
UW)POINT
REWIND
i
DS3
a
FILE PROTECT
ATTENTION
I~
if
i
'1
OSlO.!:
AUTO
~____f • • •
__
.---------------------------+----~
••
=~••F-Fi7
CR3
ATTE
FRONT VIEW
slIe
START
ION
S4~
56&"'-""
--- -'--
-
'--
H28-tI ~
1'128-17 -
I~,
2",\ 9
ioo--
~~
r-
4
°
I 12 II
2~IO
10
3o.~
4.~-i
56 7
1
I
"
~
~
7
10
~
}4
13
12
~
N
II
3
2~
S
-409
4' ,\
6 7
REAR VIEW
REAR VIEW
~ B e
p
~ ~ F G H K L
I
tt~12
I
~
2
3
g-.-J.
8~~c~
5
76
5118
SUA
FRONT VIEW
4
·24
19
12
21
~
28
47
43
40 38 42
36
B
17
6
4S
50
N
.n
>
iii
...>«nZ
W
0
...o
z
~-
z
I&J
e
~
~
I
3 7
K> 14 18 22 2630 34
~
;
~e
o°t;j,..co
~t-"'-tu u x u
"'~"'Nt-
u
w~U)w
W
""we""
.~
~ ~ V) Z ~4
~!::!::5!::
wzza:z
fI)~~C!)~
.."
t-
Z
~
Figure 4-23. Operator Control Panel Schematic
NOTE: REFERENCE 50S OWG: 1337091
901013A. «)5
4-64
SDS 901013
Table 4-29. 28" Cabinet Assembly, Replaceable Parts
Reference
Designator
Description
Fig. No.
Manufacturer
Part No.
Qty
1-1, 1-2
28" Cabinet Assembly (See table 4-18
for next higher assembly)
SDS
124361
Ref
4-24
• Power Distribution Chassis Assembly
(See table 4-30 for replaceable parts)
SDS
132365
1
4-25
• Relay Chassis Assembly
(See table 4-31 for replaceable parts)
SDS
130409
1
· Power Supply, PTl9
SDS
127160
1
4-27
• Transport Drive Electronics Assembly
(See table 4-32 for replaceable parts)
SDS
123120
1
1-2
• Swing Frame Assembly (See table 4-35
for replaceable parts)
SDS
127598
1
• Fi Iter
SDS
128344
1
Part No.
Qty
Table 4-30.
Reference
Designator
Description
Fig. No.
4-24
Power Distribution Chassis Assembly, Replaceable Parts
Manufacturer
Power Distribution Chassis Assembly
(See table 4-29 for next higher assembly) *
SDS
132365
Ref
• Assembly, modu Ie, board, power
control uni t
SDS
131982
1
· Block, terminal, stack
(SDS 109432-001)
TB2B
107
1492 series
20
• Block, terminal, stack
(SDS 109432-007)
TBIB
107
1492 series
3
43F/86F
4
• Capacitor, electrolytic, 630 fJF, large
can-type (SDS 108474-018)
· Capacitor, all paper, 1fJF, 120 Vac
bathtub (SDS 100992-005)
C3, C4
C5, C7
25
C8, C9, CI0
189
CP53
3
· Choke
Ll
SDS
132370
1
• Circuit breaker, 15A, I-pole
(SDS 105016)
CBl
105
AM-12-15
Curve 4
1
107
1492 Series
4
• Clip, retaining (SDS 109432-005)
* See figure 3-4 for schemati c
(Continued)
4-65
5DS 901013
Table 4-30.
Description
Fig. No.
4-24
(Cont. )
Power Distribution Chassis Assembly, Replaceable Parts (Cont.)
Manufacturer
Part No.
Qty
• Contacter, 3-pole, 30A, 600 Vac
with 120 Vac coil (SDS 130422-001)
K4, KI0
106
CRA-130-U
120 Vac
XB2001
2
• Contacter, 3-pole, 30A, 600 Vac
with 25 Vac coil (SDS 130422-002)
K5
106
CRA-130-U
24 Vdc
XB2000
1
5
IN4003
2
365
5256
1
C30BX35
2
• Diode, silicon, rectifier, SDS 113,
200V, 750 mA (50S 101154)
• Receptacle, female, 3-contact, 15A,
125V, grounding type (50S 101430)
CR18, CR19·
Jl
• Rectifier, thyristor, SCR, 200V, 16A;
50S 229 (50S 113977)
Q4, Q5
5
• Relay, dpdt, lOA, 115 Vac coil
(SDS 130132)
K2, K3
164
KA3310
2
K6
164
GA 11024Vdc
1
• Relay, 24 Vdc coil, dpdt, 5A
(SOS 130540)
• Relay (50S 106994)
3
K7, K8, K9
R3, R4
244
F203
• Resistor, 470 ohm 2"/0, fixed fi 1m, 1W,
(S OS 110996-471)
R6
73
MF7C
· Resistor, 2.5k 5%, ww, power, 20W,
(50S 101155-252)
R13
244
F203
· Resistor, 15 ohm 5%, ww, power, 20W,
(SOS 101155-150)
R15
244
F203
• Resistor, fixed, 200 ohm 5%, ww,
power, 20W, (50S 101155-201)
4-66
Reference
Designator
• Socket, relay
50S
106843-001
• Socket, relay, time delay for 129681
(S OS 129682)
366
4309
· Relay, start, thermionic time delay,
spst, 115 Vac (SOS 129681)
K1
366
FS2
• Switch, 9V, toggle, dpdt
(SDS 130462)
51
106
83028
• Transformer
Tl
SDS
132369
2
3
1
LOCAL-REMOTE
SWITCH Sl
(SEE DETAIL H)
j\
1
j\
1
~II
K9
J:. \.3 1··~'6~
Ii
K4
KIO
KS
~I'
SEE DETAIL F
FOR TERM. CONFIGURATIONS
FOR K4, K5 AND K10
o
COVER REMOVED FOR CLARITY
RECEPTACLE
FEMALE, Jl
TERMINAL BLOCK
STACK, TB2B
RETAINING
CLIP
e
~
~ ~~CIt
. 10
---~
91
@
en rb
j
16>
I
I
I
0,
f)@ere~(f)1,
o
-T'1,
,"j-"'jrTj-"Tj'rj
SOCKET, RELAY
(SEE DETAIL E)
,
~
V
@
I@
1
i@
(t)'
I
TERMINAL BLOCK
STACK, TBl B
RETAINING
CLIP
VIEW ~\ - ~\
RELAY, K6
(SEE DETAIL D)
.3
I~
~ 7~ 7~'
bd t::j. ~
4 ~ i
4 5
1
r-----'
=,4
e::!14
c:::J 1 6
1 Ie::!
ZI=
e::!'~
1
c:::I'
I
3 1=
I
c::::Il &
I
I
c:::::I
~
NO CONNECTIONS
THIS SIDE
BOARD, POWER
CONTROL UNIT
RELAY, DC
Ie::!
1 c:::J
Z I
Q
COVER, POWER
DISTRIBUTION
~
r-----,
CIRCUIT BREAKER, CBl
j
DETAIL H
PIN LOCATION ON K4, K5, Kl0
DETAIL I:
3
2
I
I
I
I
I
I
I
I
I
I
I
=16 =9
t:I
10
il!
\I
1=l -.,...,.- ~ 8
1 L=
=·8
-'-T--.1
14c::J
I..~MTG STUD
I.-""-...MTG STUD
12
~
Vl
7~(t)
1=
o
Vl
-.0
L--_---l
~
cc
c
CD
DETAIL (:
PIN LOCATION
TYP ON K2, K3
~
DETAIL I]
PIN LOCATION
ON K6
C
()~
:r~
C
•
II'
DETAIL IE
PIN LOCATION
ON K7, Ka, K9
@
a
a
w
@
G
-. 0
@
VI
.."
VI
>~
CD
VI
~
..,
3 0
TRANSFORMER
c- -.
-
_.
c-
VI
'< ::f
c
t
~
~
I
0ex>
~
~
~
~
N
::z:
o
::l
NOTES I
UNLESS OTHERWISE SPEC If lED
1. IDENTifY PART PER SDS SPEC 100198.
2. INSTALL RELAYS USING SPRING CLIPS SUPPLIED
PRIOR TO SUBMITTING TO TEST.
3.
MOUNT Cl0 ON TOP OF C9.
". REFERENCE SOS OWG: 132365-10, 20, 3D
5. FOR SCHEMATIC SEE FIGURE 3-4
ALL CONFIGURATIONS ARE SHOWN
SELECT THE ONE THAT IS APPLICABLE
VIEW
II-II
SDS 901013
Table 4-31.
Relay Chassis Assembly, Replaceable Parts
Reference
Designator
Part No.
Qty
50S
130409
Ref
5DS
133028-022
1
• Bar, re lay mounting
5DS
130193
2
• Block, terminal, molded
(S DS 1005 13-009)
51
141-Y
2
·
Bracket, mounting
SDS
130199
1
Chassis, re lay
SOS
130408
1
• Diode, si licon, rectifier, SDS 113,
200V, 750 rnA (SDS 101154)
5
1N3189
2
· Hinge, chassis mounting
SOS
130194
1
TF-154-4C
6
Fig. No.
Description
4-25
Relay Chassis Assembly (See table 4-29
for next higher assembly) *
• Cable Plug Module Assembly
P208
Manufacturer
• Relay, dc (SDS 106994)
K1-K6
• Resistor, fixed film, 1W, 120 ohm
(S OS 110996- 121)
R1, R2
36
CES-L-32
2
R3, R4, R5
36
L07, CCM,
OM
3
• Resistor, fixed fi 1m, 1W, 1K
(SOS 11 0996-102)
R6
36
CES-L-32
1
• Resistor, fixed, ww, 20W 5%
(SOS 101155-401)
R7
53
8450
1
79
30055-4
6
· Resistor, fixed fi 1m,
(SOS 116447-472)
1/4W 5%, 4. 7K
· Socket, relay (50S 106843)
* See figure 4-26 for schematic
4-69/4-70
SDS 901013
,
I
__ -=-=-__
•
:blh9~--ltl
,
.
I
o·
I
I
I
I
RESISTOR
TERMINAL BLOCK
MOUNTING BRACKET
COVER
RESISTOR
RELAY
CHASSIS
~~~++r---RE~Y
Kl-K6
TERMINAL
RESISTOR
BLOCK
(2 REQ)
RELAY CHASSIS
MOUNTING HINGE
CABLE PLUG
MODULE
(LOCATED IN
SLOT U-32)
COMPONENT
SIDE
RE~Y
MOUNTING
BAR
P208
---,.\
Figure 4-25.
NOTE: REFERENCE SOS OWG: 130409-1C
Relay Chassis Assembly
901084A.605
4-71
SDS 901013
AC
INTERLOCf(~l
REAOY~~i
CR .. ,
I
I
K3
SPEED
REW'M>
4
1-------1
I
I
I
I
J
I
K.I1:,
FILE PROTECT
I
J
I
.
~
,I
I
~r~ ~ -f1-n -' -rll~
R2 :
K6~:
~
.~:
R3
TBIN
-
I
+80V
2
GROUND
:3
4
READY BRAKE POWER
5
6
LO SPEED SCR GATE
7
HI
8
117VAC
SPEED seR GATE
9
TB2N
I
2
:3
INTLK GROUND
4
READY BRAKE POWER
5
6
7
8
9
6
A
M
I
7
18
19
12
H
I~
G
E
13
7
2
14
43
21
3~p
2
8
8
4
~45
4
C
7
~~A
RO
19u
z
0
x
u
o
Z
III
~
Z
&L.
&L.
o
0
~
~
..
1&1
a:
>
i
+
~
1&1
o
z
a:
~
a::
0
i
III
>
If)
N
+
t:
~
a:::
'"
w
~
~
a:::
~
a:
>
."
l
3
0
~
Z
a::
+ '"
a:
N
B
:)
v
III
~
«
~
~
~
u
1&1
~
~
~
1&.1
::!
lL
Figure 4-26. Relay Chassis Schematic
NOTE: REFERENCE SOS DWG: 132413-1A
901084A. 710
4-72
SDS 901013
Table 4-32.
Fig. No.
4-27
Transport Drive Electronics Assembly, Replaceable Parts
Description
Reference
Designator
Manufacturer
Part No.
Qty
Transport Drive Electronics Assembly
(See table 4-29 for next higher
assembly) *
SDS
123120
Ref
• Forced Convection Heatsink Assembly
(See table 4-33 for breakdown)
SDS
111671
1
• Rectifier Heatsink Assembly (See
table 4-34 for breakdown)
SDS
115757
1
SDS
123123
1
• Assembly, cable plug module
P209
· Block, terminal, molded barrier
(SDS 100513-018)
TB 1, TB2
51
141-Y
2
· Capacitor, JC, electrolytic, 65 O C,
large can-type, 27,000 mfd
(SOS 100594-002)
C10-C40
25
43F
4
189
CP53
1
79
CNAS
2
• Capacitor, oi I impregnated, 1000 Vdc,
120 Vac, bathtub (SOS 100992-005)
· Relay, spst, 50A, 115 Vac
(S OS 10 1664)
C6
K 1, K2
· Resistor, fp, fixed, ww
(50S 101517-053)
R1
182
MC-500
1
· Transformer, power, special
TlD
SDS
113770
1
* See figure 4-28 for schematic diagram
4-73/4-74
SDS 901013
TERMINAL
BLOCK TB1
HEATSINK
FORCED CONV
o
TERMINAL
BLOCK
TB2
HEAT SINK
RECTIFIER
RELAY, Kl
CAPACITOR,
C1 THRU C4
RESISTOR Rl
POWER
TRANSFORMER
T1D
CAPACITOR,
VIEW
,.\-~\
C6
CABLE PLUG
MODULE P209
(MODULE LOCATION U22)
NOTE: REFERENCE SOS OWG: 123120-10
Figure 4-27. Transport Drive
Electronics Assembly
90 1084A. 603
4-75
C8G.
R20H !!!H
A21 H
~
.........
R22H
.........
-""".
000+--------------..
0-+--------------,
00-+-----------__
11II 6I
-If--
I
2
C5G
C3G
I
F£EL FORWARD
FlXED
3
REEL REVERSE
FILE
4
REEL FORWARD
FILE
5
CAPSTAN
...aTOR POWER
~~
~
~
TalO
REEL REVERSE
R~ii' ~5G
~
2
~OM~
MOTOR C
R~
~
-If-
I
2 GAJI
R3G
,.
/XQ3G
~~-C4G
~
~~
SCR BIAS
BRAKE PO.NER.
1--------+--+-0 TO READY RElAY
------+---+-----......X
10
FILE seR
~-~~+---~------_+--;------~~~ FWD ~MAND
X
II
FIXED SCR
.....-t-~
4-~-----+_-+-----
CRI4G
L..
,...-
12
o
Z=Ei
FIXED REEL
BIAS SCR cx:MvWI)
9
FILE SCR
-+--t-'I REV COMMAND
POWER
AIC COM-
8
L--------1--t-------t--t-o
T820-E14
AlC--~
5
o
7
1
gl
4
L.;~~-t-t---------"'-1------1~6
+x
~y
BRAKE
PCMlER GND.'--~91----+-.......~~a:.:
BRAKE
SCR
HI
GATE CURRENT
~MAtC)
~~~--~~--~----~--~~~~~3 ~T~~~~
...I\IV'y
CRI5G
--'I
T820
tJJ
RIG
FAN 111
CRI3G
J...
REV COMMAND
12 - FIXED SCR
L--01------+---+---__--t.......~ FWD COMMAt('QIG
~--+----~--_+---------~ BIAS~~
~(C7G
17
~H~..RJ9H
17
18
<+3
~.
4+1 ~
TB2H
GND
FILE REEL
16
~
• r
I~
r -~ I + 25V
~R.IH
-,-
~KID
..,...C6
TBIH
•
~
.~
~
INT.
-22 V
l
~I
r
I
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SDS 901013
Table 4-33.
Fig. No.
4-27
Forced Convection Heatsink Assembly, Replaceable Parts
Reference
Designator
Description
Manufacturer
Part No.
Qty
Ref
-H
SDS
111671
• Capacitor, Mylar, O. 22 \-IF 10:'10, 80V
(SDS 100308-224)
C1-C2
191
CTM
2
• Capacitor, Mylar, 0.33 \-IF 10:'10, 80V
(SDS 100308-224)
C3-C4
191
CTM
2
5
A40B
2
144
BS2107F
1
1
2N3055
10
Forced Convection Heatsink Assembly
(See table 4-32 for next higher assembly)
• Diode, 50S 121 (SDS 111660)
• Fan, cooling, 100CFM (SDS 107742)
CR1-CR2
B1
• Transistor, SDS 225 (SDS 107820)
Q1-QlO
• Resistor, ww, 110 ohms 1%, SOW
R1, R9
182
MC500
2
• Resistor, ww, 0.2 ohms 1%, SOW
R2, R4-R7,
R10, R12-R15
182
MC500
10
• Resistor, fi 1m 4.7 ohms 5%, 1/2W
R3, R11
36
BW 20
2
· Resistor, ww, 3.3 ohms 5%, 1W
R16
36
KNR
1
• Resistor, ww, 10 ohms 1%, SOW
R17-R22
182
MC500
6
· Resistor, ww, 4.7 ohms 5%, 1W
R8
36
KNR
1
Table 4-34. Rectifier Heatsink Assembly
Fig. No.
4-27
Description
Reference
Designator
tv', _mufacturer
Part No.
Qty
Rectifier Heatsink Assembly (See
table 4-32 for next higher assembly)
-G
SDS
115757
Ref
Capacitor, Mylar (SDS 100308-334)
0.33 \-IF 10010, 80V
C1-C8
191
CTM
8
CR1-CR20
5
A40B
20
• Rectifier, silicon control
S DS 236 (S DS 132495)
Q1-Q4
1
2N689
4
• Rectifier, silicon control
S DS 229 (S DS 113977)
Q5-Q8
1
2N685
4
R1-R8
96
E009
8
• Diode, SDS 121 (SDS 111660)
• Resistor, fi 1m, 1k 2%, l/2W
(5DS 100111-102)
4-77
SDS 901013
Table 4-35. Swing Frame Assembly, Replaceable Parts
Part No.
Qty
Swing Frame Assembly (See table 4-29
for next higher assembly)
SDS
135721
Ref
• Station Electronics Assembly (See
table 4-36 for replaceable parts)
SDS
• Controller Electronics Assembly (See
table 4-39 for replaceable parts)
SDS
134049
1
• Top Fan Assembly
SDS
123943
1
• Bottom Fan Assembly
SDS
117320
1
• Power Supply PTl8
SDS
127137
1
• Power Supply PTl6
SDS
117264
Description
1-2
Table 4-36.
Fig. No.
4-3,
1-2
4-78
Reference
Designator
Manufacturer
Fig. No.
1
1
Station Electronics Assembly, Replaceable Parts
Description
Reference
Designator
Manufacturer
Part No.
Qty
Station Electroni cs Assembly
(See table 4-35 for next higher
assembly)
SDS
• Station Electronics Chassis S
Assembly (See table 4-37 for
replaceable parts)
SDS
116231
1
• Station Electronics Chassis U
Assembly (See table 4-38 for
replaceable parts)
SDS
116231
1
Ref
SDS 901013
Table 4-37.
Fig. No.
Station Electronics Chassis S Assembly, Replaceable Parts
Reference
Designator
Part No.
Qty
SDS
116231
Ref
Sl, 53, 54
SDS
128170
3
52, 527
SDS
130908
2
55, S 19, 530, 532
SDS
129862
4
56, 58
SDS
117028
2
• Band Gate BT 11
57
SDS
116029
1
• Nand/Nor Gate IT 11
59
SDS
116994
1
• Gated Buffer BT 15
510
SDS
117389
1
• Cable Driver A Tll
511
SDS
123019
1
513, 522
SDS
123018
2
Description
Station Electronics Chassis 5 Assembly
(See table 4-36 for next higher assembly)
• Read Amplifier HTl7
• Cable Plug Module ZT33
• Buffered Cable Driver AT27
• Gated Flip-Flop FTl2
• Line Receiver A Tl 0
Man u fac turer
• Logic Element LT36
S14, 515, 516,
517, 518
SDS
131328
5
• Buffered Cable Driver AT27
519, 530, S32
SDS
129862
3
520, 525
SDS
123008
2
• Switch Module STl4
• Logic Element LT10
521
SDS
116017
1
• Band Gate BTl8
523
SDS
126613
1
• Write Driver RTll
524, 529
SDS
128126
2
• Resistor Module XTl5
526, 528
SDS
128116
2
• Cable Plug Module ZT33
527
SDS
130908
1
• Jumper Module ZT24
531
SDS
128252
1
4-79
SDS 901013
Table 4-38. Station Electronics Chassis U Assembly, Replaceable Parts
Fig. No.
Reference
Designator
Part No.
Qty
SDS
116231
Ref
Ul
SDS
145928
1
U2, U5, U6
SDS
126330
3
U3, U8, U25
SDS
116029
3
• Basic Flip-Flop FTlO
U4
SDS
116380
1
• Inverter Matrix IT 13
U7
SDS
117000
1
Ul0, Ul1
SDS
129920
2
• Photosense Amplifier AT28
U13
SDS
130080
1
• Reference Generator HTl2
U14
SDS
123186
1
• Ramp Generator OTl 0
U15
SDS
123193
1
• Fi Ie Ree I Servo HTl8
U16
SDS
129849
1
• Fixed Reel Servo HTl9
U17
SDS
129851
1
• Coast Enable WTl6
U18
SDS
129854
1
• Capstan Preamplifier HTl3
U19
SDS
123200
1
• Power Turn-On Limit WTl8
U20
SDS
130474
1
• Logic Terminator XTlO
U21
SDS
116257
1
• Cable Plug Module P209
U22
SDS
123123
1
• Cable Plug Module P208
U24
SDS
123118
1
• Cable Plug Module P206
U27
SDS
115833
1
• Relay Driver RTl4
U28
SDS
132061
1
• Cable Plug Module P205
U32
SDS
115833
1
Description
Station Electronics Chassis U Assembly
(See table 4-36 for next higher assembly)
Assy, PW, Read Threshold Adjust HT55
• Gated Buffer BTl7
• Band Gate BT11
• One-Shot OTl4
4-80
Manufacturer
SDS 901013
Table 4-39.
Fig. No.
1-2, 4-3
Controller Electronics Assembly, Replaceable Parts
Manufacturer
Part No.
Qty
Controller Electronics Assembly (See
table 4-35 for the next higher
assembly)
SDS
134049
Ref
• Controller Chassis V Assembly (See
table 4-40 for replaceable parts)
SDS
116231
1
• Controller Chassis W Assembly (See
table 4-41 for replaceable parts)
SDS
116231
1
• Controller Chassis Y Assembly (See
table 4-42 for replaceable parts)
SDS
116231
1
• Controller Chassis Z Assembly (See
table 4-43 for replaceable parts)
SDS
116231
1
Manufacturer
Part No.
Qty
SDS
116231
Ref
Table 4-40.
Fig. No.
Reference
Designator
Description
Controller Chassis V Assembly, Rep laceable Parts
Description
Reference
Designator
Controller Chassis V Assembly (See
table 4-39 for next higher assembly)
• Buffered Cable Driver AT27
V1
SDS
129862
1
• Buffered Latch FT26
V2
SDS
126856
1
• Band Gate BT 11
V3, V5
SDS
116029
2
• Band Gate BT 18
V4
SDS
126613
1
V6, V7
SDS
117021
2
V8, V14
SDS
116380
3
V9
SDS
116017
1
• Buffered And/Or Gate BT 10
V10
SDS
T16056
1
• Logic Element LT36
V11
SDS
131617
1
• Parity Generator LTl2
V12
SDS
117382
1
• Gated F Iip-F lop FTl2
V13
SDS
117028
1
• Peak Detector FT35
V18, V20, V22,
V25, V29, V30
SDS
130178
6
• Deskew Register FT36
V19, V21, V23,
V26, V28, V31
SDS
130187
6
V24
SDS
136547
1
V27, V32
SDS
123018
2
· High Speed Count FT 11
• Basic F lip-F lop FT 10
• Logic Element LTlO
• LogicElementLT71
• Cable Receiver ATlO
4-81
SDS 901013
Table 4-41.
Fig. No.
Controller Chassis W Assembly, Replaceable Parts
Description
Reference
Designator
Controller Chassis W Assem b Iy (See
table 4-39 for next higher assembly)
Qty
SDS
116231
Ref
• Ribbon Cable ZT 45
W1, W14
SDS
133218
2
• Gated Flip-Flop FTl2
W2, W10
Wll, W18
SDS
117028
4
• Buffered Latch FT26
W3, W12
SDS
126856
2
W4
SDS
117382
1
• Nand Gate ITl8
W5, W24, W25
SDS
126372
3
• Nand Gate ITl1
W6, W15, W26
SDS
116994
3
• Logic Element LT36
W7
SDS
131617
1
• Logic Element LTl 0
W8, W16
SDS
116017
2
• Delay Element DTl6
W9
SDS
128172
1
• Fast Access Memory FT39
W13
SDS
131072
1
• Gated Buffer BTl5
W17
SDS
117389
1
• Basic Flip-Flop FTlO
W19
SDS
116380
2
• Clock Oscillator CTl 0
W22
SDS
123491
1
· Peak Detector FT35
W23
SDS
130178
1
• Band Gate BTl8
W27
SDS
126613
1
• Band Gate BT 11
W28
SDS
116029
1
• Logic Element LT71
W29
SDS
136547
1
• Deskew Register FT36
W30, W31
SDS
130187
2
· Cable Receiver A Tl 0
W32
SDS
123018
1
• Parity Generator LTl2
4-82
Part No.
Manufacturer
SDS 901013
Table 4-42.
Fig. No.
Controller Chassis Y Assembly, Replaceable Parts
Description
Reference
Designator
Controller Chassis Y Assembly (See
table 4-39 for next higher assembly)
Ribbon Cable ZT45
• Gated Flip-Flop FTl2
Y1
Y2, Y16, Y17
Part No.
Qty
SDS
116231
Ref
SDS
133218
2
SDS
117028
3
Manufacturer
• Gated Inverter IT15
Y3
SDS
117375
1
• Nand Gate IT 11
Y4
SDS
116994
1
• Logi c Element LT36
Y5, Yl0, Y18, Y19
SDS
131617
4
• Buffered And/Or Gate BTlO
Y7, Y20, Y21, Y22
SDS
116056
4
Y9
SDS
116407
1
• Logic Element LTlO
Y11, Y12
5D5
116017
2
• Band Gate BT11
Y13, Y15
5DS
126613
2
• Gated Flip-Flop FTl2
Y16, Y17
5DS
117028
2
• Logic Element LT25
Y23
sDS
126712
1
• swi tch Comparator LT26
Y24
SD5
126982
1
Y25, Y26
sDS
126714
2
• Logic Element LT24
Y27
sDS
126710
1
• Cable Receiver ATl 0
Y28
sDs
123018
1
• Logic Element LT41
Y29
SDS
133392
1
• Cable Driver/Receiver A Tll
Y30
SDS
123019
1
• Logic Element LT43
Y31
SD5
133657
1
• Cable Driver AT12
Y32
sDS
124629
1
• Buffered Matrix BT 13
• Cable Driver/Receiver A Tl7
4-83
SDS 901013
Table 4-43. Controller Chassis Z Assembly, Replaceable Parts
Fig. No.
Reference
Designator
Part No.
Qty
SDS
116231
Ref
Z 1, Z22
SDS
116017
2
Z5
SDS
123016
1
Z6, Z7
SDS
116380
2
• Band Gate BT 11
Z8, Z21
SDS
116029
2
• Nand Gate ITl1
Z9
SDS
116994
1
• Logic Element LT36
Z10, Zl1, Z15,
Z16, Z17, Z18,
Z19, Z20, Z24
SDS
131617
9
• Logic Element LTll
Z 12
SDS
116324
1
• Gated Inverter IT20
Z 13
SDS
126747
1
• High Speed Count FT11
Z 14
SDS
117021
1
• Buffered And/Or Gate BTlO
Z25
SDS
116056
1
• Cable Driver AT 12
Z26
SDS
124629
1
• Cable Receiver ATl 0
Z28
SDS
123018
1
• Decoder BTl 2 .
Z29
SDS
115965
1
Z30, Z31
SDS
126330
2
Z32
SDS
123019
1
Description
Manufacturer
Controller Chassis Z Assembly (See
table 4-39 for next higher assembly)
• Logic Element LTl 0
• Buffer Inverter 1, LT13
• Basic Flip-F lop FTl 0
• Gated Buffer BTl7
• Cable Driver/Receiver A Tl1
Table 4-44.
Fig. No.
1-1
4-84
Description
Front Door Assembly, Replaceable Parts
Reference
Designator
Manufacturer
Part No.
Qty
Ref
Front Door Assembly
(See table 4-18 for next higher
assembly)
SDS
124371
• Switch (SDS 114285)
113
K3-4
1
• Switch (SDS 109372)
162
V3-15
1
SDS 901013
Table 4-45.
Manufacturer Code Index
Name
Code No.
Address
1
Motorola Semiconductor Products, Inc.
p. O. Box 2953, Phoenix, Ariz. 85002
5
General Electric Co., Semiconductor Product Div.
Electronics Park, Syracuse, N. Y. 13201
25
General Electric Co., Capacitor Dept.
p. O. Box 158, Irmo, S. C. 29063
36
International Resistance Co.
401 N. Board St., Philadelphia, Po. 19108
51
Cinch Manufacturing Co.
1026 S. Homan Ave., Chicago, III. 60624
53
Ohmite Manufacturing Co.
3635 Howard St., Skokie, III. 60076
55
Centralab Electronics
900 E. Keefe Ave., Mi Iwaukee, Wisc. 53201
73
Electra Manufacturing Co.
800 North 21, Independence, Kans. 67301
79
Allied Control Co., Inc.
2 East End Ave., New York, N. Y. 10021
83
Chicago Miniature Lamp Works
Dept. E, 4433 Ravenswood Av~., Chicago, III. 60640
96
Amperex E lectroni c Corp.
230 Duffy Ave., Hi cksvi lie, N. Y. 11802
104
Dialight Corp.
60 Stewart Ave., Brooklyn, N. Y. 11237
105
Heinemann Electric Co.
2636 Brunswick Pike, Trenton, N. J. 08602
106
Arrow-Hart & Hegeman E lectri c Co.
103 Hawthorne St., Hartford, Conn. 06106
107
Allen-Bradley Co.
1201 Second St., Mi Iwaukee, Wisc. 53204
113
Controls Co. of Ameri ca
9655 Spreng Ave., Schiller Park, III. 60176
144
IMC Magneti cs Corp.
570 Main St., Westburn, N. Y. 11590
162
Honeywe II, Mi cro Switch Div.
11 W. Spri ng St., Freeport, III. 61033
164
Potter & Brumfield, Div. AMF
1200 E• Broadway, Box 322, Princeton, Ind. 47570
182
California Resistor
1631 Colorado Ave., Santa Monica, Calif. 90404
189
Cornell-Dubilier Electronics
50 Ave. "L ", Newark, N. J. 07101
191
Dearborn Electronics, Inc.
Box 350, Orlando, Fla. 32802
203
Moster Specialties Co.
15020 Figueroa, Gardena, Calif. 90247
244
Hardwick, Hindle Products
Huntington, Ind. 46750
255
Ducommun
4890 S. Alameda, Los Angeles, Calif. 90000
360
Gost Manufacturing,
C/O Brenner Fieldler & Assoc.
7563 Melrose Ave., L. A., Calif. 90046
361
United Electrical Controls
423 S. Brookhurst, Anaheim, Calif. 92800
362
Be II and Gosse tt
8200 N. Austin, Morton Grove, III. 60053
363
Precision Lamp Engineers, "Goldlamp" Div.
809 San Antonio Rd., Palo Alto, Cali f. 94300
364
Buckeye Stamping Co.
555 Marion Road, Columbus, Ohio 43207
365
Harvey Hubbe II, Inc.
Harvey St. & Bostwi ck, Bridgeport, Conn. 06600
366
Bryant Computer Products
850 Ladd Rd., Walled Lake, Mich. 48088
4-85/4-86
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