A_1670D A 1670D
A_1672D A_1672D
User Manual: A_1670D
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Discontinued Product—Support Information Only This literature was published years prior to the establishment of Agilent Technologies as a company independent from Hewlett-Packard and describes products or services now available through Agilent. It may also refer to products/services no longer supported by Agilent. We regret any inconvenience caused by obsolete information. For the latest information on Agilent’s test and measurement products go to: www.agilent.com/find/products Or in the US, call Agilent Technologies at 1-800-452-4844 (8am–8pm EST) The HP 1670-Series Benchtop Logic Analyzers Technical Data Identifying the cause of problems in The combination of deep memory, embedded microprocessor system large internal disk drive, and LAN designs can be difficult. The make the HP 1670-series of benchHewlett-Packard 1670-series bench- top logic analyzers especially well top logic analyzers have the feasuited to solving your integration tures to help the embedded system problems. design team find hardware and software defects quickly. • Mass storage is provided by an internal hard drive which provides quick With 64K of acquisition memory storage and retrieval of files. (1M optional) the HP 1670-series logic analyzers are the first bench- • The 3.5-inch high-density flexible top logic analyzers which display disk drive supports both DOS and processor mnemonics and verify LIF formats. critical hardware timing relationships over a long period of time. • The LAN interface enables access to the logic analyzer files via FTP or With the standard Ethernet LAN NFS. Use X11 windows to control or interface, the software designer can view the logic analyzer on a PC or now capture a real-time microproworkstation. The LAN interface cessor trace and time-correlate it to includes both Ethertwist (10BASE-T) source code in C++ or other highand ThinLan (10BASE 2) connectors. level languages on a PC or workstation. For time-correlation of source • Store data as ASCII files and screen code, order the HP B3740A images in TIFF, PCX, and EPS Software Analysis package. (encapsulated PostScriptTM) formats. Logic Analyzer Key Specifications and Characteristics _______________________________________________________________________ Model Number HP 1670D HP 1671D HP 1672D _______________________________________________________________________ State and Timing 136 102 68 Channels _______________________________________________________________________ Timing Analysis Conventional: 125 MHz all channels, 250 MHz half channels _______________________________________________________________________ State Analysis 100 MHz, all channels Speed _______________________________________________________________________ State Clocks/ 4 4 4 Qualifiers _______________________________________________________________________ Memory Depth 64K per channel, 128K in timing half-channel mode per Channel (1M per channel optional memory, 2M in timing half-channel mode) _______________________________________________________________________ Get to the root cause of problems quickly • New graphical trigger macros make trigger setup easier. • Centronics, RS-232, HP-IB and LAN communication ports make connecting to other devices easier than ever. All of these come standard on all models of the HP 1670-series. • The HP 1670-series operating system includes System Performance Analysis (SPA). SPA provides state histograms, state overview, and time interval analysis. • The HP E2450A Symbolic Download Utility is included with the HP 1670series. This utility provides the capability to extract symbolic information from popular object module formats. PostScriptTM is a trademark of Adobe Systems Incorporated. 2 HP 1670-Series General-Product Information _________________________ Human Interface _________________________ Front Panel A knob and keypads make up the frontpanel human interface. Keys include control, menu, display navigation, and alpha-numeric entry functions. _________________________ Mouse A DIN mouse is shipped as standard equipment. It provides full instrument control. Knob functionality is replicated by holding down the right button and moving the mouse left or right. _________________________ Keyboard The logic analyzer can also be operated using a DIN keyboard. Order the HP Logic Analyzer Keyboard Kit, model number HP E2427B. _________________________ Input/Output, Control, and Printing _________________________ I/O Ports All units ship with a Centronics parallel printer port, RS-232, and HP-IB as standard equipment. _________________________ LAN Interface An Ethernet LAN interface is standard with the HP 1670-series. The LAN interface comes with both Ethertwist (10BASE-T) and ThinLan (10BASE 2) connectors.The LAN supports FTP and PC/NFS connection protocols. It also works with X11 window packages. _________________________ Software Analysis Capability The HP B3740A Software Analyzer provides true source line referencing and symbol download capabilities. Standard object module formats are supported. _________________________ _________________________ _________________________ Programmability Screen Image Files Each instrument is fully programmable from a computer via HP-IB and RS-232 connections. This feature is standard on all models. _________________________ HP Printer Printers which use the Support HP Printer Control Language (PCL) and have a parallel Centronics, RS-232 or HP-IB interface are supported: HP DeskJet, LaserJet, QuietJet, PaintJet, and ThinkJet models. _________________________ Alternate Printer Supported The Epson FX80, LX80 and MX80 printers with an RS-232 or Centronics interface supported in the Epson 8-bit graphics mode. _________________________ Hard Copy Output Screen images can be printed in black and white from all menus using the Print field. State or timing listings can be printed in full or part (starting from center screen) using the Print All selection. _________________________ Mass Storage Files and Software _________________________ Updating the The operating system Operating resides in Flash ROM System and can be updated from the flexible disk drive or the hard disk drive. _________________________ Mass Storage Is supported by an internal hard disk drive and by a 1.44 Mbyte, 3.5-inch flexible disk drive. Supports DOS and LIF formats. A disk drive provides quick storage and retrieval of files. _________________________ An image file of any display screen can be stored to disk via the display's Print field. Black & white TIFF, PCX, Encapsulated PostScript (EPS) , and gray-scale TIFF file formats are available. _________________________ ASCII Data Files State or timing listings can be stored as ASCII files on a flexible disk via the display's Print field. These files are equivalent in character width and line length to hardcopy listings printed via the Print All selection. _________________________ Configuration Logic analyzer files and Data Files that include configuration and data information (if present) are encoded in a binary format. They can be stored to or loaded from the hard disk drive or a flexible disk. _________________________ Recording of Acquisition and Storage Times Binary format configuration/data files are stored with the time of acquisition and the time of storage. _________________________ Acquisition Arming _________________________ Initiation Arming is started by Run or the Port In BNC. _________________________ Cross Arming The analyzer machines can cross-arm each other. _________________________ Output An output signal is provided at the Port Out BNC. _________________________ HP 1670-series Logic Analyzer Specifications and Characteristics _________________________ Port In/Out _________________________ PORT IN Signal and Connection Port In is a standard BNC connection. The input operates at TTL logic signal levels. Rising edges are valid input signals. _________________________ PORT OUT Signal and Connection Port Out is a standard BNC connection with TTL logic signal levels. A rising edge is asserted as a valid output. _________________________ Arming Times _________________________ PORT IN Arms Logic Analyzer [1] 15 ns typical delay from signal input to a don't care logic analyzer trigger. _________________________ 3 _________________________ Physical Factors _________________________ Weight 28.6 lbs. (13 kg) _________________________ Dimensions See figure 1 _________________________ Safety IEC 348/ HD 401, UL 1244, and CSA Standard C22.2 No. 231 (series M-89) _________________________ EMC CISPR 11:1990/EN 55011 (1991): Group 1 Class A IEC 801-2:1991/EN 50082-1 (1992): 4kV CD, 8 kV AD IEC 801-3:1984/EN 50082-1 (1992):3V/m IEC 801-4:1988/EN 50082-1 (1992): 1kV _________________________ Logic 120 ns typical delay Analyzer from logic analyzer Arms PORT trigger to signal OUT [1] output. _________________________ 13.0 in. 14.5 in. (330 mm) (367 mm) Operating Environment _________________________ Power 115 Vac or 230 Vac, –22% to +10%, single phase, 48-66 Hz, 320 VA max _________________________ Temperature Instrument, 0° to 50° C (+32° to 122° F). Disk media, 10° to 40° C (+50° to 104°F). Probes and cables, 0° to 65° C (+32° to 149° F) _________________________ Instrument, up to 95%, relative humidity at +40° C (+140° F). Disk media and hard drive, 8% to 85% relative humidity. _________________________ 8.1 in. (205 mm) 17.3 inches (440 mm) Weight 28.6 lb. (13kg) Humidity Altitude To 3,048 m (10,000 ft) _________________________ Vibration: Operating Random vibrations 5–500Hz, 10 minute per axis, ~ 0.3 g (rms). _________________________ Vibration: Random vibrations Non Operating 5–500 Hz,10 minutes per axis,~ 2.41 g (rms); and swept sine resonant search, 5–500 Hz, 0.75 g (0-peak), 5 minute resonant dwell @ 4 resonances per axis. _________________________ Figure 1 _________________________ Logic Analyzer Probes _________________________ Input 100 kΩ ±2% Resistance _________________________ Input approx. 8 pF Capacitance (see figure 2) _________________________ RT = 250Ω CTG = 1 pF CCOMP = 7.5 pF RIN = 100kΩ Z0 = 150Ω High Frequency Model for Probe Inputs Figure 2 _________________________ Minimum 500 mV peak-to-peak Input Voltage Swing _________________________ Minimum 250 mV or 30% of input Input amplitude, whichever is Overdrive greater _________________________ Threshold –6.0 V to +6.0 V in 50-mV Range increments _________________________ Threshold Threshold levels may be Setting defined for pods (17-channel groups) on an individual basis _________________________ Threshold ± (100 mV +3% of Accuracy* threshold setting) _________________________ Input ± 10 V about the Dynamic threshold Range _________________________ Maximum ± 40 V peak Input Voltage _________________________ +5 V 1/3 amp maximum Accessory per pod Current _________________________ Channel Each group of 34 Assignment channels (a pod pair) can be assigned to Analyzer 1, Analyzer 2 or remain unassigned. ______________________________ [1] Time may vary depending upon the mode of logic analyzer operation. * Warranted Specification 4 _________________________ State Analysis _________________________ Maximum 100 MHz State Speed _________________________ Channel Count [2] HP 1670D 136/68 HP 1671D 102/51 HP 1672D 68/34 _________________________ Memory Depth per Channel _________________________ _________________________ State Clock Qualifier Time Tagging [4] Measures the time between stored states, relative to either the previous state or to the trigger. Max. time between states is 34.4 sec. Min. time between states is 8 ns. Time Tag Value 8 ns to 34.4 seconds ± (8 ns + 0.01% of time tag value) The high or low of the clocks can be ANDed or ORed with the clock specification. _________________________ Setup/Hold [3] one clock, 3.5/0 ns to 0/3.5 ns one edge (in 0.5 ns increments) one clock, 4.0/0 ns to 0/4.0 ns both edges (in 0.5 ns increments) multi-clock, 4.5/0 ns to 0/4.5 ns multi-edge (in 0.5 ns increments) _________________________ Standard 64K (65,536) samples Time Tags On 32K (32,768) samples) Compare Mode On 32K (32,768) samples) Minimum 3.5 ns State Clock Pulse Width [3] _________________________ Minimum 10 ns Master to Master Clock Time [3] _________________________ Compare 32K Mode and (32,768) samples) Time Tags On Minimum 10 ns Slave to Slave Clock Time [3] _________________________ Option 030 1M (1,032,192) samples Time Tags On 500K (507,904) samples Minimum 0.0 ns Master to Slave Clock Time [3] _________________________ Compare Mode On 250K (245,760) samples Compare 120K Mode and (114,688) samples Time Tags On _________________________ State Clocks HP 1670D HP 1671D HP 1672D 4 clocks 4 clocks 4 clocks Clocks can be used by either one or two state analyzers at any time. Clock edges can be ORed together and operate in single phase, two-phase demultiplexing, or twophase mixed mode. Clock edge is selectable as positive, negative, or both edges for each clock. _________________________ Minimum 4.0 ns Slave to Master Clock Time [3] _________________________ Clock 4.0/0 ns (fixed) Qualifiers Setup/Hold [3] _________________________ State Tagging [4] State Tag Count Counts the number of qualified states between each stored state. Measurement can be shown relative to the previous state or relative to trigger. Max. count is 4.29 × 109. Time Tag 8 ns or 0.1% Resolution (whichever is greater) _________________________ Timing Analysis _________________________ Conventional Data stored at selected Timing sample rate across all timing channels. Maximum Timing Speed [2] 125 MHz/250 MHz Channel Count [2] HP 1670D HP 1671D HP 1672D Sample Period [2] 8 ns/4 ns minimum 41 µs/10 µs maximum Memory Depth per Channel [2] 64K standard 64K/128K samples (65,536/131,072) 136/68 102/51 68/34 1M option 1M/2M samples (1,032,192/2,080,768) _________________________ Time Covered Sample period × by Data [2] memory depth _________________________ 0 to 4.29 × 109 State Tag 1 count Resolution _________________________ [2] Full Channel /Half Channel Modes [3] Specified for an input signal VH= – 0.9V, VL = – 1.7V, slew rate = 1V/ns, and threshold = –1.3V [4] Time or-state-tagging (Count Time or Count State) is available in the full-channel state mode. There is no speed penalty for tag use. Memory is halved when time or state tags are used unless a pod pair (34channel group) remains unassigned in the Configuration menu. 5 ________________________ Time Interval Accuracy ________________________ Sample ± 0.01% Period Accuracy ________________________ Channel-to- 2 ns typical, Channel 3 ns maximum Skew ________________________ Time Interval ± (Sample Period Accuracy + channel-to-channel skew + 0.01% of time interval reading) ________________________ Maximum Delay After Triggering Sample Period 4-8 ns : 8.389 ms Sample Period > 8 ns: 1,048,575 × sample period _______________________ Trigger Specifications ________________________ Trigger Macros Trigger setups can be selected from a categorized list of trigger macros. Each macro is shown in graphical form and has a written description. Macros can be chained together to create a custom trigger sequence. ________________________ Pattern Each recognizer is the Recognizers AND combination of bit (0,1, or X) patterns in each label. Pattern Recognizers 10 Pattern Width HP 1670D 136/68 (in channels) HP 1671D 102/51 [2] HP 1672D 68/34 ________________________ Minimum Pattern and Range Recognizer Pulse Width 125 MHz and 250 MHz Timing Modes: 13 ns + channel-to-channel skew ≤ 125 MHz Timing Modes : 1 sample period + 1 ns + channel-to-channel skew + 0.01% ________________________ ________________________ _________________________ Range Recognizers Recognize data which is numerically between or on two specified patterns (ANDed combination of zeros and/or ones). Qualifier Range Recognizers 2 Range Width 32 channels _________________________ Edge/Glitch Trigger on glitch or Recognizers edge on any channel. Edge can be specified as rising, falling or either. Edge/Glitch Recognizers 2 (in timing mode only) Edge/Glitch HP 1670D Width (in HP 1671D channels) [2] HP 1672D Branching Each sequence level has a branching qualifier. When satisfied, the analyzer will branch to the sequence level specified. _________________________ Occurrence Counters 136/68 102/51 68/34 Edge/Glitch Recovery Time Sample Period 4-8 ns: 28 ns Sample Period > 8 ns: 20 ns + sample period _________________________ Greater than Sample period 4-8 ns: Duration 8 ns to 8.389 ms. (timing only) Accuracy is –2 ns to +10 ns Sample period > 8 ns: (1 to 220) × sample period. Accuracy is –2 ns + sample period + 2 ns ± 0.01% _________________________ Less than Duration (timing only) A user-specified term that can be any state, no state, any recognizer, (pattern, ranges or edge/glitch), any timer, or the logical combination (NOT, AND, NAND, OR, NOR, XOR, NXOR) of the recognizers and timers. _________________________ Sample period 4-8 ns: 8 ns to 8.389 ms. Accuracy is –2 ns to +10 ns. Sample period > 8 ns: (1 to 220) × sample period. Accuracy is 2 ns + sample period – 2 ns ± 0.01% _________________________ Sequence qualifier may be specified to occur up to 1,048,575 times before advancing to the next level. Each sequence level has its own counter. Maximum 1,048,575 Occurrence Count _________________________ Storage Each sequence level Qualification has a storage qualifier (state only) that specifies the states that are to be stored. _________________________ Maximum Sequencer Speed 125 MHz State Sequence Levels 12 Timing 10 Sequence Levels _________________________ [2] Full Channel /Half Channel Modes 6 _________________________ _________________________ Timers Timers may be Started, Paused, or Continued at entry into any sequence level after the first. Activity Indicators Timers 2 Timer Range 400 ns to 500 seconds Timer Resolution 16 ns or 0.1% whichever is greater Timer Accuracy ± 32 ns or ± 0.1%, whichever is greater Timer 70 ns Recovery Time _________________________ Data In to 110 ns typical Trigger Out BNC Port _________________________ Acquisition, Measurement and Display Functions _________________________ Arming Each analyzer can be armed by the Run key, the other analyzer, or the Port In. _________________________ Run Starts acquisition of data in specified trace mode. _________________________ Stop Stop halts acquisition and displays the current acquisition data. _________________________ Trace Mode Single mode acquires data once per trace specification; repetitive mode repeats single mode acquisitions until Stop is pressed or until pattern time interval or compare stop criteria are met. _________________________ Trigger Displayed as a vertical dashed line in the timing waveform, state waveform and X-Y chart displays and as line 0 in the state listing and state compare displays. _________________________ Provided in the Configuration, State Format, and Timing Format menus for monitoring deviceunder-test activity while setting up the analyzer. _________________________ Labels Channels may be grouped together and given a 6-character name called a label. Up to 126 labels in each analyzer may be assigned with up to 32 channels per label. Trigger terms may be given an 8-character name. _________________________ are kept only when both patterns can be found in an acquisition. Statistics are minimum x to o time, maximum x to o time, average x to o time, and ratio of valid runs to total runs. _________________________ Compare Mode Functions Performs post-process ing bit-by-bit comparison of the acquired state data and Compare Image data. Compare Image Created by copying a state acquisition into the compare image buffer. Allows editing of any bit in the Compare Image to a 1, X or O. Compare Image Boundaries Each channel (column) in the compare image can be enabled or disabled via bit masks in the Compare Image. Upper and lower ranges of states (rows) in the compare image can be specified. Any data bits that do not fall within the enabled channels and the specified range are not compared. Measurement Functions _________________________ Markers Two markers (x and o) are shown as dashed lines in the display. _________________________ Time Intervals The x and o markers measure the time interval between events occurring on one or more waveforms or states. Available in state when time tagging is on. _________________________ Delta States The x and o markers measure the number of tagged states between any two states (state only). _________________________ Patterns The x or o marker can be used to locate the nth occurrence of a specified pattern before or after trigger, or after the beginning of data. The o marker can also find the nth occurrence of a pattern before or after the x marker. _________________________ Statistics x to o marker statistics are calculated for repetitive acquisitions. Patterns must be specified for both markers, and statistics Stop Repetitive acquisitions Measurement may be halted when the comparison between the current state acquisition and the current Compare Image is equal or not equal. _________________________ Compare Reference Listing Mode display shows the Displays Compare Image and bit masks; Difference Listing display highlights differences between the current state acquisition and the Compare Image. _________________________ 7 _________________________ Data Entry/Display _________________________ Display Modes State Listing, State Waveforms, State Chart, State Compare Listing, Compare Difference Listing, Timing Waveforms, Timing Listing, interleaved time-correlated listing of two state analyzers (time tags on), and time-correlated State Listing with Timing Waveforms on the same display. _________________________ State X-Y Plots value of a speciChart Display fied label (on y-axis) versus states or another label (on xaxis). Both axes can be scaled. Markers Correlated to State Listing, State Compare, and State Waveform displays. Available as pattern, time, or statistics (with time counting) and states (with state counting on). Accumulate Chart display is not erased between successive acquisitions. _________________________ State Waveform Display Displays state acquisitions in waveform format. States/div 1 to mem length/8 Delay ± Accumulate Waveform display is not erased between successive acquisitions. Overlay Mode Displayed Waveforms memory length Multiple channels can be displayed on one waveform display line. 24 lines maximum on one screen. Up to 96 lines may be specified and scrolled through. ________________________ ________________________ ________________________ Timing Waveform Display Displays timing acquisition in waveform format. Symbols Sec/div [2] 1 ns to 4.4 sec/div/ 1 ns to 2.2 sec/div Delay – 2,500 s to + 2,500 s Accumulate Waveform display is not erased between successive acquisitions. Overlay Mode Multiple channels can be displayed on one waveform display line. When waveform size set to large, the value represented by each waveform is displayed inside the waveform in the selected base. Pattern Symbols User can define a mnemonic for the specific bit pattern of a label. When data display is SYMBOL, mnemonic is displayed where the bit pattern occurs. Range Symbols User can define a mnemonic covering a range of values. When data display is SYMBOL, values within the specified range are displayed as mnemonic + offset from base of range. Number of 1000 maximum. Symbols ________________________ Displayed Waveforms 24 lines maximum on one screen. Up to 96 lines may be specified and scrolled through. ________________________ System SPA includes state Performance histogram, state Analysis overview and time interval measurements to aid in the software optimization process. These tools provide a statistical overview of your synchronous design. For additional information, refer to HP 10390A System Performance Software technical data sheet, pub no. 5091-7850E. ________________________ Bases Binary, Octal, Decimal, Hexadecimal, ASCII (display only), symbols, two's compliment. ________________________ [2] Full Channel /Half Channel Modes Ordering Information HP 1670D-Series Benchtop Logic Analyzers _____________________________________________________ HP 1670D 136-Channel 100-MHz State/250-MHz Timing with 64K Memory Depth and Ethernet LAN ________________________________________________________________ HP 1671D 102-Channel 100-MHz State/250-MHz Timing with 64K Memory Depth and Ethernet LAN ________________________________________________________________ HP 1672D 68-Channel 100-MHz State/250-MHz Timing with 64K Memory Depth and Ethernet LAN ________________________________________________________________ Additional HP 1660C/CS and 1670D-Series Product Options _____________________________________________________ Opt 030 Extended Memory depth to 1M samples/channel (ordered at the time of purchase) ________________________________________________________________ Opt 0B3 Add Service Manual ________________________________________________________________ Opt 1CM Rack Mount Kit ________________________________________________________________ Opt UK9 Front Panel Cover ________________________________________________________________ Opt W30 3-Year extended repair service ________________________________________________________________ Opt W50 5-Year extended repair service ________________________________________________________________ Opt OBF Add Programming Manual ________________________________________________________________ Accessory Software _____________________________________________________ HP B3740A Software Analyzer Opt AJ4 IBM, 3.5-inch Media/Documentation Opt AAY HP 9000 Series 700 Media/Documentation Opt AAV SUN (Solaris and SUN OS) Media/Documentation Opt UDY IBM Single User License Opt UBY HP 9000 Series 700 Single User License Opt UBK SUN (Solaris and SUN 0S) Single User License ________________________________________________________________ HP 10391B Inverse Assembler Development Package ________________________________________________________________ For more information on Hewlett-Packard Test & Measurement products, applications or services please call your local Hewlett-Packard sales offices. A current listing is available via Web through AccessHP at http://www.hp.com. If you do not have access to the internet, please contact one of the HP centers listed below and they will direct you to your nearest HP representative. United States: Hewlett-Packard Company Test and Measurement Organization 5301 Stevens Creek Blvd. Bldg. 51L-SC Santa Clara, CA 95052-8059 1 800 452 4844 Canada: Hewlett-Packard Canada Ltd. 5150 Spectrum Way Mississauga, Ontario L4W 5G1 (905) 206 4725 Europe: Hewlett-Packard European Marketing Centre P.O. Box 999 1180 AZ Amstelveen The Netherlands HP 1670D-Series Upgrades _____________________________________________________ Japan: Hewlett-Packard Japan Ltd. Measurement Assistance Center 9-1, Takakura-Cho, Hachioji-Shi, Tokyo 192, Japan Tel: (81-426) 56-7832 Fax: (81-426) 56-7840 HP E2471D Upgrade HP 1670D-Series from 64K to 1M of memory Opt 001 Upgrades HP 1670D from 64K to 1M of acquisition memory Opt 002 Upgrades HP 1671D from 64K to 1M of acquisition memory Opt 003 Upgrades HP 1672D from 64K to 1M of acquisition memory ________________________________________________________________ HP E2427B Add keyboard with DIN connector (PC style) ________________________________________________________________ Latin America: Hewlett-Packard Latin American Region Headquarters 5200 Blue Lagoon Drive, 9th Floor Miami, Florida 33126, U.S.A. (305) 267 4245/4220 State/Timing Analyzer Probes & Lead Sets _____________________________________________________ Australia/New Zealand: Hewlett-Packard Australia Ltd. 31-41 Joseph Street Blackburn, Victoria 3130 Australia 1 800 629 485 HP 5959-9333 5 Grey Probe Leads for HP 1670D-Series ________________________________________________________________ HP 5959-9334 5 Short Ground Leads for HP 1670D-Series ________________________________________________________________ HP 5959-9335 5 Long Ground Leads for All State and Timing Analyzers ________________________________________________________________ HP 01650-61608 16-Channel Probe Lead Set for State and Timing Analyzers ________________________________________________________________ HP 01650-63203 Termination Adapter for State and Timing Analyzers ________________________________________________________________ HP 1810-1278 9-Channel IC Termination DIP ________________________________________________________________ HP 1810-1588 Termination IC SIP ________________________________________________________________ HP 1251-8106 2 × 10, 0.1-inch Center Header (Similar to 3M p/n 2520-6002) ________________________________________________________________ HP 5090-4356 Surface-Mount Grabbers (package of 20) ________________________________________________________________ HP 5959-0288 Throughhole Grabbers (package of 20) ________________________________________________________________ Other Accessories for HP Logic Analyzers _____________________________________________________ HP 1180B Testmobile for the HP 1670-Series ________________________________________________________________ HP 92199B Power Strip ________________________________________________________________ HP 5041-9456 Front Cover for HP 1670-Series ________________________________________________________________ HP 5062-7379 Rack Mount Kit for HP 1670-Series ________________________________________________________________ Asia Pacific: Hewlett-Packard Asia Pacific Ltd 17-21/F Shell Tower, Times Square, 1 Matheson Street, Causeway Bay, Hong Kong Fax: (852) 2506 9285 Technical information in this document is subject to change without notice. 5964-3666E Printed in the U.S.A. Copyright© Hewlett-Packard Company 1996 9/96
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