A 5958 4362 9_Series_300_Display_Color_Card_Theory_of_Operation_Oct85 9 Series 300 Display Color Card Theory Of Operation Oct85

User Manual: A-5958-4362-9_Series_300_Display_Color_Card_Theory_of_Operation_Oct85

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HEWLETT-PACKARD
NOTE:

!'his page provides a running histery ef changes fer a mUlti-page
drawing which cannot conveniently be re-issued cempletely after
each change. When making a change, list fer each page all beforeand-after numbers (within reasen; use judgement,and use
"extensive" revisien nete if less ef past histery is tolerable, or
retype cemplete page) and asseciate with each a symbel made up ef
the change letter and a serial subscript to appear here and on the
page involved (there enclesed in a circle, triangle, er other
attentien-getting outline).

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REVISIONS

INITIALS

DATE
(0 -, '1

As Issued

1
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Title

Theory of Oper a tio n

Description
By

9320-3246

Oete

Brad Reak

1

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HEWLETT ~ PA.CKARD CO.

SERIES 300 DISPLAY COLOR CARD
(

The6ry of operation

FINAL

B.t:'ad Reak

Hewlett Packard Company
Fort Collins Systems Division

See Pg. 1 for
DESCRIPTION

Rev~.

Theory of OP

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Scope

-t-------------------.----.--

This is the Theory of Cperatior: for the 98545A and 98543A displaJ'
cards. These cards provide bitmapped color displays for the Series
300 Technical Workstations produced at FSD.
The following documents and· specifications are

ref~renced:

TopcAT ERS descriDes the operation of the Topcat display
controller chip.
Document nu~ber A-lFH2-2001-7

RODAN Specification describe~ the low resolution color monitor to
be OEM'ed by the Roseville Terminal Divjsion.
D~cument
A-35741-90004-l.
JACKPOT Specirication describes the low resolution mohochrome
monitor to be OEM'ed by the Roseville Terminal Division.
A-35731-90004-1
DIO Bus specification is the cu~rent 10 standard for HP's series
200 line of deskt0p computers.

NEREID ERS desc~ibes the operation of the Nereid color mapping
display chip.
Document number h-1FF3-2001-7.
Allegro specification describes the interface to the High
resolution color monitor OEM'ed by FSD.
Document number
A-1150-9007-1.

FSP Display Rom Definition Describes the FSD standard display
board architectur€ for series 200 computers.

I
I

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See Pg. 1 for Revs,
DESCRIPTION

Theory of OP

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No.A-5958-4362-:-,9

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--------_._-------------------_._------GENERAL DESCRIPTION

ChaptEl' 2

The Series 300 color bo&r-d is all upgrade to the low end BOBCAT
system ~ith monochrome display.
Series 300 color will have four
plane color mapping wi t.h 8 bit DACs.
This allows the user t..::.,
display 16 colors from a palette of 16,777,216 colors.
Buyers
have a choice of low r~301ution or high resolution.
The low
resolution version displays 512 X 400 pixel pairs and drives the
Rodan monitor currently being specified at Roseville Terminal
Division.
The hi resolution version displays l02~ X 768
individual pixels and uses the Allegro monitor b$ingdevelo~ed at
FSD.
Th~

color card achieves its high level of functionality by makil~g
extensive use of LSI.
At its heart is the TOPCAT chip.
Topc~t
is an N:t-10S III .ctdp that provides an integra. ted bi t mapped
display with window move hardware and frkme buffer support.
Color mapping is entirely handled by another NMOS III chip called
NEREID.
Nereid does the color mapping and D to A conversion.
V-ideo-memory uses the 4'-i16 nibble wide DRAM.

Sea Pg. 1 ~or Revs.

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DESCRIPTION

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FUNCTIONAL DESCRIPTION

Cl1~ptel'

3

1_ _ _ _
.-

3.1

Topcats and Video

R~rn

The Topcat is the h~art of the display board.
Topcat can best be
descri~ed as a Frame Buffer memory manager and window ttover.
It
takes memor.y date:. in the on board frame buffer and Cl-'ea"Ces pixel
data.
This 0peration is essentially invisible to the rest 0f th0
~ysteffi.
To the system) the i'r·ame buffer memory appe-~rs a nc,r'r:lal
system ram but organized in a format that makes graprlics
manipulation easier.
The c~lor boa~d uses the TMS 4416 nibb:e wide DRAM as described
in tile TOPCAT ERS.
Both high and low resolution boards have 1',}-JI
planes of memory.
The low res board uses eight memo~y chips ~~~
plane (U 01 to U 08). Hi resolution uses 16 m~mory chips ~~r
plane (U-01 to U-16).
Series damping resistors R 01 to R d4 and
RP 01, damp the RAM address, RAS and CAS lines.
R-05 TO F.-Q7 i:ee~.
th; Topcat DIP port inactive during normal board ~peratio~ bUT
'
allow a 3065 board tester to use the DIP port· for trouble!hoOTin.
TOPCATS.
Topcat organizes the l'ramebuffer into an array fixed to 1024
pixels across and either 512,1024 or 2048 lines.
It is possible
to select the number 01' displayed lines via programm.able Topca t
registers.
The 98543A card displays 1024 individual pixels
across and 40D lines down.
This leaves 112 lines of undisp:ay~d
frame buffer available for' temporary' storage of graphics
information.
Since single horizontal pixels would far exceed th
bandwidth 0 f mos t low cos t r.1.Oni tors, it is so ftwares '
responsibility to always use double pixels.
The effect is to
give horizontal resolution better than 512 pixels without
exceeding monitor bandwidth specs.
Single pixel snifting is
allowed but there must always be at least 2 pixels between
adjacent horizontal dots.
The 98545A uses a much higher performance mon'itor and therefcre
does not require software to use double pixel algorithms.
3.2

Nereia Color Map
The color board has four plane colormapping.
Mapping
under control of the NEREID chip.
See the Nereid ERS
particulars on its operation.
Since only four pl,anes
and Nereid supports eight, the top four planes remain

is entirel
for
are used
unused and

Sea Pg. 1 for Rell&.
DESCRIPTION

Theory of OP

Dwg

No,A-5958-4362-9

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Due to peculiarities in the N0reid colormap, it is

pos~~~:e

~o

d

a write read cycle to Ner'eid to fast. This is esps-I-:~l.). .i. :':'::t!'t'''t
with a combinaticn or fast processor and low resol~~l~n (j5~12Y
card~
The pi."'irr. c.Y'y l"eason for this is that the c:l-:.:(.'l'. J.S not f::ls"t
enough to clec.i.I' l';e:::'t;ids bl~SY bit i:::efoI'e another :0:L"'J cycle (;;:":1
start.
The error 1s seen as a bus error t~m~out at the CPU.
Th~ fix is
to use a NOP or ot~.er delay technique to prevent cC·!l==~~'..~tive
Nereid access cycl~s.
Nereid needs at least 16 dot clock cycles
~etween accesses.
In the case of the low ~esolution displ~y
~35.904MHz clock) this is 445ns before starting another Nereid.
access.
In the future, raster p:::'c1ccssors may make tr.is shew ':lp
on even the Hi resolution card.
It is advisable to always che~k
the 16 cycle rule as stated 3.be;vE' \·:heu '\'lriting code 1'02"' Ne-reia..
Nereid uses older NMOS techliOlogy so therefore re;L~i!"'f.!s r.,:):-,".; -... l"~a
.SV and -2V.
U4 is a voltage regulator that suppl~e~ Nerei~ wit
6.5V at Vclk and Aclk.
Aclk js isolated from Vclk t·y trte lOKpas
:filter 1.1 and C28. This keeps noise generated by ·\"~.il': fl'C'Ii:
coupling directly to ~he ou~puts via an internal Nereid ~a~h.
1/4 of U2, QIC and Q8 compose 2 3.75V regulato~ tc su,ply Nereid
VI supply. 1/4 of U2 with Ol~ and reference voltag~ so~r~e ~1
suppiy the -2V needs of' N~r'eid ::.nd the res to tbe t;02.l'·j,

Nereid requires a con.s-:ant ~·:i.:"'I'.=:nt .source to establist a
reference f'or the DAC' s.
'l'Lts"2.,:, 2.~,:,:omplished using or a!1:p V')
and the resistor netw·ork co;..p:-;~:.~.j~).~' .~·-{I~, R6, Rl1, R12, Hl.:~ ,:'\.l ~~
R14.
The nominal value is ·~~t; mi(':.I·':I.::4A:~p;;) into Irei' v;j 1;:n ::L\' ~,_ '.f!
node or R4 and R6.
3.3

Logic Interface to CPU
The internal section of the ~isplay card is isolated a~d b~ffere
from the CPU bus via Ul0, U15, U21, u26 and'U32. The Data
buffers UI0 and U15 always point from the CPU to the displ~y cal" \
unless there is a read request to the board from the processor.
Decoding is accomplished by the 6ustom PAL U19 and decoder u36.
u36 with U31 and U38 create a progranunable register 3 in the
middle of the display ROM address space. A write of any value t
register,l forces the card to reset its interrupts by clearing
U38. V37 Returns 0 for unused planes during a read from the
frame buffer. Supposedly, this makes software easier to
implement.
Topcats used together are very sensitive to anythi,ng that may
cau~e the~ to become urisynchronized.
This could happen by doing

See Pg. 1 for ReV$.
DESCRIPTION

Theory

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a chi p S f' lee t at a t.i m€' \-\T hen :i n d i v i d l,.Ut 1 ~ r..r:::- pc at s mayo r !iI :i Y !; C t
see the select :::ignal.
Ie's being'rhat they are" soine m:!;';fli; :::t:':e
the select and some might not. '.:-;:;15 \'lo'u,ld cause considerc:~b.l€;
video diztortion.
US cor!'ects tr::i~ problem by synchronizing NCS,
NSUDS and NSLDS to Topcats clock.
Topcats and Nereids generate their own DTACK and this is f~d to
the CPU bus thr~ U14 and U9.
Requ~sts to read ROM U20 or wri~~
to register 1 01" registe'r 3 are DTACKed by walking a 1 tbru sl"~ift
register U1S.
~he 9S5~5A and 9854JA boards will generally confo~m ~o DIO
specifications~ with the following exceptions.
(

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Shape factor will be Series 300.

2.
Interrupts
r'egis ter 3.

3.

allo~

all 7 levels to be programmed

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Edge connector is Series 300 CPU pinout not standard DIO.

4.
IMA is generated but not brought to the connectdr (See U9
pin S) •

•4

Video Amplifies and Output
Typical video levels seen at the BNe connectors are shown in
appendix C.
It is important to reme~ber that the video sig~al
rides on a 1.5 volt DC level. The video level is adjusted by pot
R6 which c~ntrols the current source ~ha~ supplies Nereids Iref
pin.
For the purposes of this explanation, the green amplifier will be
explained because the red and blue are similar but withQut the
sync.
The transistor Q6 with resistor Rsb and R24 form a current
to voltage' converter that converts the current sink of Nereids
output to a voltage that varies fr6~ 9.7 volts to 9.0 volts
nominal at the base of Q3.
The video drive stage is a simple
emi tter follol'ler that drives the moni tor through zener CR3 'and
the common mode chock T2.
T2 serves to prevent a conunon mode
signal from escaping to the outside world and causitig RFI
problems.
Zener CR3 drops a constant 6.8 volts to bring the
nominal level no signal level to about 1 volt~
Since most
monito~s use composite sync on green, it is necessary to mix the
0.3 volt sync signal with the video.
This is accomplished with
the resistor R38 acting to suck out enough current to lower the
voltage a the base of Q3 by 0.3 volts during ,horizontal or
vertical sync as controlled by the XOR gate corinect~d to Ul1.
Zener CR9 biases the t~ansistors Q5, Q6, Q7, and~9 into

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DESCRIPTION

Theory of OP

Owg No.A-5958-:-4362-9

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