ARM Architecture Reference Manual ARMv8, For ARMv8 A Profile AArch64
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- ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
- Contents
- Preface
- About this manual
- Using this manual
- Part A, Introduction and Architecture Overview
- Part B, The AArch64 Application Level Architecture
- Part C, The A64 Instruction Set
- Part D, The AArch64 System Level Architecture
- Part E, The AArch32 Application Level Architecture
- Part F, The AArch32 Instruction Sets
- Part G, The AArch32 System Level Architecture
- Part H, External Debug
- Part I, Memory-mapped Components of the ARMv8 Architecture
- Part J, Appendixes
- Conventions
- Additional reading
- Feedback
- Part A: ARMv8 Architecture Introduction and Overview
- A1: Introduction to the ARMv8 Architecture
- A1.1 About the ARM architecture
- A1.2 Architecture profiles
- A1.3 ARMv8 architectural concepts
- A1.4 Supported data types
- A1.5 Floating-point and Advanced SIMD support
- A1.6 Cryptographic Extension
- A1.7 The ARM memory model
- Part B: The AArch64 Application Level Architecture
- B1: The AArch64 Application Level Programmers’ Model
- B2: The AArch64 Application Level Memory Model
- B2.1 Address space
- B2.2 Memory type overview
- B2.3 Caches and memory hierarchy
- B2.4 Alignment support
- B2.5 Endian support
- B2.6 Atomicity in the ARM architecture
- B2.7 Memory ordering
- B2.8 Memory types and attributes
- B2.9 Mismatched memory attributes
- B2.10 Synchronization and semaphores
- B2.10.1 Exclusive access instructions and Non-shareable memory locations
- B2.10.2 Exclusive access instructions and Shareable memory locations
- B2.10.3 Marking and the size of the marked memory block
- B2.10.4 Context switch support
- B2.10.5 Load-Exclusive and Store-Exclusive instruction usage restrictions
- B2.10.6 Use of WFE and SEV instructions by spin-locks
- Part C: The AArch64 Instruction Set
- C1: The A64 Instruction Set
- C2: A64 Instruction Set Overview
- C2.1 Branches, Exception generating, and System instructions
- C2.2 Loads and stores
- C2.2.1 Load/Store register
- C2.2.2 Load/Store register (unscaled offset)
- C2.2.3 Load/Store Pair
- C2.2.4 Load/Store Non-temporal Pair
- C2.2.5 Load/Store Unprivileged
- C2.2.6 Load-Exclusive/Store-Exclusive
- C2.2.7 Load-Acquire/Store-Release
- C2.2.8 Load/Store scalar SIMD and floating-point
- C2.2.9 Load/Store Vector
- C2.2.10 Prefetch memory
- C2.3 Data processing - immediate
- C2.4 Data processing - register
- C2.5 Data processing - SIMD and floating-point
- C2.5.1 Common features of SIMD instructions
- C2.5.2 Floating-point move (register)
- C2.5.3 Floating-point move (immediate)
- C2.5.4 Floating-point conversion
- C2.5.5 Floating-point round to integral
- C2.5.6 Floating-point multiply-add
- C2.5.7 Floating-point arithmetic (one source)
- C2.5.8 Floating-point arithmetic (two sources)
- C2.5.9 Floating-point minimum and maximum
- C2.5.10 Floating-point comparison
- C2.5.11 Floating-point conditional select
- C2.5.12 SIMD move
- C2.5.13 SIMD arithmetic
- C2.5.14 SIMD compare
- C2.5.15 SIMD widening and narrowing arithmetic
- C2.5.16 SIMD unary arithmetic
- C2.5.17 SIMD by element arithmetic
- C2.5.18 SIMD permute
- C2.5.19 SIMD immediate
- C2.5.20 SIMD shift (immediate)
- C2.5.21 SIMD floating-point and integer conversion
- C2.5.22 SIMD reduce (across vector lanes)
- C2.5.23 SIMD pairwise arithmetic
- C2.5.24 SIMD table lookup
- C2.5.25 Cryptography extensions
- C3: A64 Instruction Set Encoding
- C3.1 A64 instruction index by encoding
- C3.2 Branches, exception generating and system instructions
- C3.3 Loads and stores
- C3.3.1 AdvSIMD load/store multiple structures
- C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
- C3.3.3 AdvSIMD load/store single structure
- C3.3.4 AdvSIMD load/store single structure (post-indexed)
- C3.3.5 Load register (literal)
- C3.3.6 Load/store exclusive
- C3.3.7 Load/store no-allocate pair (offset)
- C3.3.8 Load/store register (immediate post-indexed)
- C3.3.9 Load/store register (immediate pre-indexed)
- C3.3.10 Load/store register (register offset)
- C3.3.11 Load/store register (unprivileged)
- C3.3.12 Load/store register (unscaled immediate)
- C3.3.13 Load/store register (unsigned immediate)
- C3.3.14 Load/store register pair (offset)
- C3.3.15 Load/store register pair (post-indexed)
- C3.3.16 Load/store register pair (pre-indexed)
- C3.4 Data processing - immediate
- C3.5 Data processing - register
- C3.5.1 Add/subtract (extended register)
- C3.5.2 Add/subtract (shifted register)
- C3.5.3 Add/subtract (with carry)
- C3.5.4 Conditional compare (immediate)
- C3.5.5 Conditional compare (register)
- C3.5.6 Conditional select
- C3.5.7 Data-processing (1 source)
- C3.5.8 Data-processing (2 source)
- C3.5.9 Data-processing (3 source)
- C3.5.10 Logical (shifted register)
- C3.6 Data processing - SIMD and floating point
- C3.6.1 AdvSIMD EXT
- C3.6.2 AdvSIMD TBL/TBX
- C3.6.3 AdvSIMD ZIP/UZP/TRN
- C3.6.4 AdvSIMD across lanes
- C3.6.5 AdvSIMD copy
- C3.6.6 AdvSIMD modified immediate
- C3.6.7 AdvSIMD scalar copy
- C3.6.8 AdvSIMD scalar pairwise
- C3.6.9 AdvSIMD scalar shift by immediate
- C3.6.10 AdvSIMD scalar three different
- C3.6.11 AdvSIMD scalar three same
- C3.6.12 AdvSIMD scalar two-reg misc
- C3.6.13 AdvSIMD scalar x indexed element
- C3.6.14 AdvSIMD shift by immediate
- C3.6.15 AdvSIMD three different
- C3.6.16 AdvSIMD three same
- C3.6.17 AdvSIMD two-reg misc
- C3.6.18 AdvSIMD vector x indexed element
- C3.6.19 Crypto AES
- C3.6.20 Crypto three-reg SHA
- C3.6.21 Crypto two-reg SHA
- C3.6.22 Floating-point compare
- C3.6.23 Floating-point conditional compare
- C3.6.24 Floating-point conditional select
- C3.6.25 Floating-point data-processing (1 source)
- C3.6.26 Floating-point data-processing (2 source)
- C3.6.27 Floating-point data-processing (3 source)
- C3.6.28 Floating-point immediate
- C3.6.29 Floating-point<->fixed-point conversions
- C3.6.30 Floating-point<->integer conversions
- C4: The AArch64 System Instruction Class
- C4.1 About the System instruction and System register descriptions
- C4.2 The System instruction class encoding space
- C4.2.1 Principles of the System instruction class encoding
- C4.2.2 System instruction class encoding overview
- C4.2.3 Op0==0b00, architectural hints, barriers and CLREX, and PSTATE access
- C4.2.4 Op0==0b01, cache maintenance, TLB maintenance, and address translation instructions
- C4.2.5 Op0==0b10, Moves to and from debug, trace, and Execution environment System registers
- C4.2.6 Op0==0b11, Moves to and from non-debug System registers and special-purpose registers
- C4.2.7 Reserved control space for IMPLEMENTATION DEFINED functionality
- C4.3 PSTATE and special purpose registers
- C4.3.1 CurrentEL, Current Exception Level
- C4.3.2 DAIF, Interrupt Mask Bits
- C4.3.3 DLR_EL0, Debug Link Register
- C4.3.4 DSPSR_EL0, Debug Saved Program Status Register
- C4.3.5 ELR_EL1, Exception Link Register (EL1)
- C4.3.6 ELR_EL2, Exception Link Register (EL2)
- C4.3.7 ELR_EL3, Exception Link Register (EL3)
- C4.3.8 FPCR, Floating-point Control Register
- C4.3.9 FPSR, Floating-point Status Register
- C4.3.10 NZCV, Condition Flags
- C4.3.11 SP_EL0, Stack Pointer (EL0)
- C4.3.12 SP_EL1, Stack Pointer (EL1)
- C4.3.13 SP_EL2, Stack Pointer (EL2)
- C4.3.14 SP_EL3, Stack Pointer (EL3)
- C4.3.15 SPSel, Stack Pointer Select
- C4.3.16 SPSR_abt, Saved Program Status Register (Abort mode)
- C4.3.17 SPSR_EL1, Saved Program Status Register (EL1)
- C4.3.18 SPSR_EL2, Saved Program Status Register (EL2)
- C4.3.19 SPSR_EL3, Saved Program Status Register (EL3)
- C4.3.20 SPSR_fiq, Saved Program Status Register (FIQ mode)
- C4.3.21 SPSR_irq, Saved Program Status Register (IRQ mode)
- C4.3.22 SPSR_und, Saved Program Status Register (Undefined mode)
- C4.4 A64 system instructions for cache maintenance
- C4.4.1 DC CISW, Data or unified Cache line Clean and Invalidate by Set/Way
- C4.4.2 DC CIVAC, Data or unified Cache line Clean and Invalidate by VA to PoC
- C4.4.3 DC CSW, Data or unified Cache line Clean by Set/Way
- C4.4.4 DC CVAC, Data or unified Cache line Clean by VA to PoC
- C4.4.5 DC CVAU, Data or unified Cache line Clean by VA to PoU
- C4.4.6 DC ISW, Data or unified Cache line Invalidate by Set/Way
- C4.4.7 DC IVAC, Data or unified Cache line Invalidate by VA to PoC
- C4.4.8 DC ZVA, Data Cache Zero by VA
- C4.4.9 IC IALLU, Instruction Cache Invalidate All to PoU
- C4.4.10 IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
- C4.4.11 IC IVAU, Instruction Cache line Invalidate by VA to PoU
- C4.5 A64 system instructions for address translation
- C4.5.1 AT S12E0R, Address Translate Stages 1 and 2 EL0 Read
- C4.5.2 AT S12E0W, Address Translate Stages 1 and 2 EL0 Write
- C4.5.3 AT S12E1R, Address Translate Stages 1 and 2 EL1 Read
- C4.5.4 AT S12E1W, Address Translate Stages 1 and 2 EL1 Write
- C4.5.5 AT S1E0R, Address Translate Stage 1 EL0 Read
- C4.5.6 AT S1E0W, Address Translate Stage 1 EL0 Write
- C4.5.7 AT S1E1R, Address Translate Stage 1 EL1 Read
- C4.5.8 AT S1E1W, Address Translate Stage 1 EL1 Write
- C4.5.9 AT S1E2R, Address Translate Stage 1 EL2 Read
- C4.5.10 AT S1E2W, Address Translate Stage 1 EL2 Write
- C4.5.11 AT S1E3R, Address Translate Stage 1 EL3 Read
- C4.5.12 AT S1E3W, Address Translate Stage 1 EL3 Write
- C4.6 A64 system instructions for TLB maintenance
- C4.6.1 TLBI ALLE1, TLB Invalidate All entries, EL1
- C4.6.2 TLBI ALLE1IS, TLB Invalidate All entries, EL1, Inner Shareable
- C4.6.3 TLBI ALLE2, TLB Invalidate All entries, EL2
- C4.6.4 TLBI ALLE2IS, TLB Invalidate All entries, EL2, Inner Shareable
- C4.6.5 TLBI ALLE3, TLB Invalidate All entries, EL3
- C4.6.6 TLBI ALLE3IS, TLB Invalidate All entries, EL3, Inner Shareable
- C4.6.7 TLBI ASIDE1, TLB Invalidate by ASID, EL1
- C4.6.8 TLBI ASIDE1IS, TLB Invalidate by ASID, EL1, Inner Shareable
- C4.6.9 TLBI IPAS2E1, TLB Invalidate by Intermediate Physical Address, Stage 2, EL1
- C4.6.10 TLBI IPAS2E1IS, TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable
- C4.6.11 TLBI IPAS2LE1, TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
- C4.6.12 TLBI IPAS2LE1IS, TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable
- C4.6.13 TLBI VAAE1, TLB Invalidate by VA, All ASID, EL1
- C4.6.14 TLBI VAAE1IS, TLB Invalidate by VA, All ASID, EL1, Inner Shareable
- C4.6.15 TLBI VAALE1, TLB Invalidate by VA, All ASID, Last level, EL1
- C4.6.16 TLBI VAALE1IS, TLB Invalidate by VA, All ASID, EL1, Inner Shareable
- C4.6.17 TLBI VAE1, TLB Invalidate by VA, EL1
- C4.6.18 TLBI VAE1IS, TLB Invalidate by VA, EL1, Inner Shareable
- C4.6.19 TLBI VAE2, TLB Invalidate by VA, EL2
- C4.6.20 TLBI VAE2IS, TLB Invalidate by VA, EL2, Inner Shareable
- C4.6.21 TLBI VAE3, TLB Invalidate by VA, EL3
- C4.6.22 TLBI VAE3IS, TLB Invalidate by VA, EL3, Inner Shareable
- C4.6.23 TLBI VALE1, TLB Invalidate by VA, Last level, EL1
- C4.6.24 TLBI VALE1IS, TLB Invalidate by VA, Last level, EL1, Inner Shareable
- C4.6.25 TLBI VALE2, TLB Invalidate by VA, Last level, EL2
- C4.6.26 TLBI VALE2IS, TLB Invalidate by VA, Last level, EL2, Inner Shareable
- C4.6.27 TLBI VALE3, TLB Invalidate by VA, Last level, EL3
- C4.6.28 TLBI VALE3IS, TLB Invalidate by VA, Last level, EL3, Inner Shareable
- C4.6.29 TLBI VMALLE1, TLB Invalidate by VMID, All entries at stage 1, EL1
- C4.6.30 TLBI VMALLE1IS, TLB Invalidate by VMID, All entries at stage 1, EL1, Inner Shareable
- C4.6.31 TLBI VMALLS12E1, TLB Invalidate by VMID, All entries at Stage 1 and 2, EL1
- C4.6.32 TLBI VMALLS12E1IS, TLB Invalidate by VMID, All entries at Stage 1 and 2, EL1, Inner Shareable
- C5: A64 Base Instruction Descriptions
- C5.1 Introduction
- C5.2 Register size
- C5.3 Use of the PC
- C5.4 Use of the stack pointer
- C5.5 Condition flags and related instructions
- C5.6 Alphabetical list of instructions
- C5.6.1 ADC
- C5.6.2 ADCS
- C5.6.3 ADD (extended register)
- C5.6.4 ADD (immediate)
- C5.6.5 ADD (shifted register)
- C5.6.6 ADDS (extended register)
- C5.6.7 ADDS (immediate)
- C5.6.8 ADDS (shifted register)
- C5.6.9 ADR
- C5.6.10 ADRP
- C5.6.11 AND (immediate)
- C5.6.12 AND (shifted register)
- C5.6.13 ANDS (immediate)
- C5.6.14 ANDS (shifted register)
- C5.6.15 ASR (register)
- C5.6.16 ASR (immediate)
- C5.6.17 ASRV
- C5.6.18 AT
- C5.6.19 B.cond
- C5.6.20 B
- C5.6.21 BFI
- C5.6.22 BFM
- C5.6.23 BFXIL
- C5.6.24 BIC (shifted register)
- C5.6.25 BICS (shifted register)
- C5.6.26 BL
- C5.6.27 BLR
- C5.6.28 BR
- C5.6.29 BRK
- C5.6.30 CBNZ
- C5.6.31 CBZ
- C5.6.32 CCMN (immediate)
- C5.6.33 CCMN (register)
- C5.6.34 CCMP (immediate)
- C5.6.35 CCMP (register)
- C5.6.36 CINC
- C5.6.37 CINV
- C5.6.38 CLREX
- C5.6.39 CLS
- C5.6.40 CLZ
- C5.6.41 CMN (extended register)
- C5.6.42 CMN (immediate)
- C5.6.43 CMN (shifted register)
- C5.6.44 CMP (extended register)
- C5.6.45 CMP (immediate)
- C5.6.46 CMP (shifted register)
- C5.6.47 CNEG
- C5.6.48 CRC32B, CRC32H, CRC32W, CRC32X
- C5.6.49 CRC32CB, CRC32CH, CRC32CW, CRC32CX
- C5.6.50 CSEL
- C5.6.51 CSET
- C5.6.52 CSETM
- C5.6.53 CSINC
- C5.6.54 CSINV
- C5.6.55 CSNEG
- C5.6.56 DC
- C5.6.57 DCPS1
- C5.6.58 DCPS2
- C5.6.59 DCPS3
- C5.6.60 DMB
- C5.6.61 DRPS
- C5.6.62 DSB
- C5.6.63 EON (shifted register)
- C5.6.64 EOR (immediate)
- C5.6.65 EOR (shifted register)
- C5.6.66 ERET
- C5.6.67 EXTR
- C5.6.68 HINT
- C5.6.69 HLT
- C5.6.70 HVC
- C5.6.71 IC
- C5.6.72 ISB
- C5.6.73 LDAR
- C5.6.74 LDARB
- C5.6.75 LDARH
- C5.6.76 LDAXP
- C5.6.77 LDAXR
- C5.6.78 LDAXRB
- C5.6.79 LDAXRH
- C5.6.80 LDNP
- C5.6.81 LDP
- C5.6.82 LDPSW
- C5.6.83 LDR (immediate)
- C5.6.84 LDR (literal)
- C5.6.85 LDR (register)
- C5.6.86 LDRB (immediate)
- C5.6.87 LDRB (register)
- C5.6.88 LDRH (immediate)
- C5.6.89 LDRH (register)
- C5.6.90 LDRSB (immediate)
- C5.6.91 LDRSB (register)
- C5.6.92 LDRSH (immediate)
- C5.6.93 LDRSH (register)
- C5.6.94 LDRSW (immediate)
- C5.6.95 LDRSW (literal)
- C5.6.96 LDRSW (register)
- C5.6.97 LDTR
- C5.6.98 LDTRB
- C5.6.99 LDTRH
- C5.6.100 LDTRSB
- C5.6.101 LDTRSH
- C5.6.102 LDTRSW
- C5.6.103 LDUR
- C5.6.104 LDURB
- C5.6.105 LDURH
- C5.6.106 LDURSB
- C5.6.107 LDURSH
- C5.6.108 LDURSW
- C5.6.109 LDXP
- C5.6.110 LDXR
- C5.6.111 LDXRB
- C5.6.112 LDXRH
- C5.6.113 LSL (register)
- C5.6.114 LSL (immediate)
- C5.6.115 LSLV
- C5.6.116 LSR (register)
- C5.6.117 LSR (immediate)
- C5.6.118 LSRV
- C5.6.119 MADD
- C5.6.120 MNEG
- C5.6.121 MOV (to/from SP)
- C5.6.122 MOV (inverted wide immediate)
- C5.6.123 MOV (wide immediate)
- C5.6.124 MOV (bitmask immediate)
- C5.6.125 MOV (register)
- C5.6.126 MOVK
- C5.6.127 MOVN
- C5.6.128 MOVZ
- C5.6.129 MRS
- C5.6.130 MSR (immediate)
- C5.6.131 MSR (register)
- C5.6.132 MSUB
- C5.6.133 MUL
- C5.6.134 MVN
- C5.6.135 NEG
- C5.6.136 NEGS
- C5.6.137 NGC
- C5.6.138 NGCS
- C5.6.139 NOP
- C5.6.140 ORN (shifted register)
- C5.6.141 ORR (immediate)
- C5.6.142 ORR (shifted register)
- C5.6.143 PRFM (immediate)
- C5.6.144 PRFM (literal)
- C5.6.145 PRFM (register)
- C5.6.146 PRFUM
- C5.6.147 RBIT
- C5.6.148 RET
- C5.6.149 REV
- C5.6.150 REV16
- C5.6.151 REV32
- C5.6.152 ROR (immediate)
- C5.6.153 ROR (register)
- C5.6.154 RORV
- C5.6.155 SBC
- C5.6.156 SBCS
- C5.6.157 SBFIZ
- C5.6.158 SBFM
- C5.6.159 SBFX
- C5.6.160 SDIV
- C5.6.161 SEV
- C5.6.162 SEVL
- C5.6.163 SMADDL
- C5.6.164 SMC
- C5.6.165 SMNEGL
- C5.6.166 SMSUBL
- C5.6.167 SMULH
- C5.6.168 SMULL
- C5.6.169 STLR
- C5.6.170 STLRB
- C5.6.171 STLRH
- C5.6.172 STLXP
- C5.6.173 STLXR
- C5.6.174 STLXRB
- C5.6.175 STLXRH
- C5.6.176 STNP
- C5.6.177 STP
- C5.6.178 STR (immediate)
- C5.6.179 STR (register)
- C5.6.180 STRB (immediate)
- C5.6.181 STRB (register)
- C5.6.182 STRH (immediate)
- C5.6.183 STRH (register)
- C5.6.184 STTR
- C5.6.185 STTRB
- C5.6.186 STTRH
- C5.6.187 STUR
- C5.6.188 STURB
- C5.6.189 STURH
- C5.6.190 STXP
- C5.6.191 STXR
- C5.6.192 STXRB
- C5.6.193 STXRH
- C5.6.194 SUB (extended register)
- C5.6.195 SUB (immediate)
- C5.6.196 SUB (shifted register)
- C5.6.197 SUBS (extended register)
- C5.6.198 SUBS (immediate)
- C5.6.199 SUBS (shifted register)
- C5.6.200 SVC
- C5.6.201 SXTB
- C5.6.202 SXTH
- C5.6.203 SXTW
- C5.6.204 SYS
- C5.6.205 SYSL
- C5.6.206 TBNZ
- C5.6.207 TBZ
- C5.6.208 TLBI
- C5.6.209 TST (immediate)
- C5.6.210 TST (shifted register)
- C5.6.211 UBFIZ
- C5.6.212 UBFM
- C5.6.213 UBFX
- C5.6.214 UDIV
- C5.6.215 UMADDL
- C5.6.216 UMNEGL
- C5.6.217 UMSUBL
- C5.6.218 UMULH
- C5.6.219 UMULL
- C5.6.220 UXTB
- C5.6.221 UXTH
- C5.6.222 WFE
- C5.6.223 WFI
- C5.6.224 YIELD
- C6: A64 SIMD and Floating-point Instruction Descriptions
- C6.1 Introduction
- C6.2 About the SIMD and floating-point instructions
- C6.3 Alphabetical list of floating-point and Advanced SIMD instructions
- C6.3.1 ABS
- C6.3.2 ADD (vector)
- C6.3.3 ADDHN, ADDHN2
- C6.3.4 ADDP (scalar)
- C6.3.5 ADDP (vector)
- C6.3.6 ADDV
- C6.3.7 AESD
- C6.3.8 AESE
- C6.3.9 AESIMC
- C6.3.10 AESMC
- C6.3.11 AND (vector)
- C6.3.12 BIC (vector, immediate)
- C6.3.13 BIC (vector, register)
- C6.3.14 BIF
- C6.3.15 BIT
- C6.3.16 BSL
- C6.3.17 CLS (vector)
- C6.3.18 CLZ (vector)
- C6.3.19 CMEQ (register)
- C6.3.20 CMEQ (zero)
- C6.3.21 CMGE (register)
- C6.3.22 CMGE (zero)
- C6.3.23 CMGT (register)
- C6.3.24 CMGT (zero)
- C6.3.25 CMHI (register)
- C6.3.26 CMHS (register)
- C6.3.27 CMLE (zero)
- C6.3.28 CMLT (zero)
- C6.3.29 CMTST
- C6.3.30 CNT
- C6.3.31 DUP (element)
- C6.3.32 DUP (general)
- C6.3.33 EOR (vector)
- C6.3.34 EXT
- C6.3.35 FABD
- C6.3.36 FABS (vector)
- C6.3.37 FABS (scalar)
- C6.3.38 FACGE
- C6.3.39 FACGT
- C6.3.40 FADD (vector)
- C6.3.41 FADD (scalar)
- C6.3.42 FADDP (scalar)
- C6.3.43 FADDP (vector)
- C6.3.44 FCCMP
- C6.3.45 FCCMPE
- C6.3.46 FCMEQ (register)
- C6.3.47 FCMEQ (zero)
- C6.3.48 FCMGE (register)
- C6.3.49 FCMGE (zero)
- C6.3.50 FCMGT (register)
- C6.3.51 FCMGT (zero)
- C6.3.52 FCMLE (zero)
- C6.3.53 FCMLT (zero)
- C6.3.54 FCMP
- C6.3.55 FCMPE
- C6.3.56 FCSEL
- C6.3.57 FCVT
- C6.3.58 FCVTAS (vector)
- C6.3.59 FCVTAS (scalar)
- C6.3.60 FCVTAU (vector)
- C6.3.61 FCVTAU (scalar)
- C6.3.62 FCVTL, FCVTL2
- C6.3.63 FCVTMS (vector)
- C6.3.64 FCVTMS (scalar)
- C6.3.65 FCVTMU (vector)
- C6.3.66 FCVTMU (scalar)
- C6.3.67 FCVTN, FCVTN2
- C6.3.68 FCVTNS (vector)
- C6.3.69 FCVTNS (scalar)
- C6.3.70 FCVTNU (vector)
- C6.3.71 FCVTNU (scalar)
- C6.3.72 FCVTPS (vector)
- C6.3.73 FCVTPS (scalar)
- C6.3.74 FCVTPU (vector)
- C6.3.75 FCVTPU (scalar)
- C6.3.76 FCVTXN, FCVTXN2
- C6.3.77 FCVTZS (vector, fixed-point)
- C6.3.78 FCVTZS (vector, integer)
- C6.3.79 FCVTZS (scalar, fixed-point)
- C6.3.80 FCVTZS (scalar, integer)
- C6.3.81 FCVTZU (vector, fixed-point)
- C6.3.82 FCVTZU (vector, integer)
- C6.3.83 FCVTZU (scalar, fixed-point)
- C6.3.84 FCVTZU (scalar, integer)
- C6.3.85 FDIV (vector)
- C6.3.86 FDIV (scalar)
- C6.3.87 FMADD
- C6.3.88 FMAX (vector)
- C6.3.89 FMAX (scalar)
- C6.3.90 FMAXNM (vector)
- C6.3.91 FMAXNM (scalar)
- C6.3.92 FMAXNMP (scalar)
- C6.3.93 FMAXNMP (vector)
- C6.3.94 FMAXNMV
- C6.3.95 FMAXP (scalar)
- C6.3.96 FMAXP (vector)
- C6.3.97 FMAXV
- C6.3.98 FMIN (vector)
- C6.3.99 FMIN (scalar)
- C6.3.100 FMINNM (vector)
- C6.3.101 FMINNM (scalar)
- C6.3.102 FMINNMP (scalar)
- C6.3.103 FMINNMP (vector)
- C6.3.104 FMINNMV
- C6.3.105 FMINP (scalar)
- C6.3.106 FMINP (vector)
- C6.3.107 FMINV
- C6.3.108 FMLA (by element)
- C6.3.109 FMLA (vector)
- C6.3.110 FMLS (by element)
- C6.3.111 FMLS (vector)
- C6.3.112 FMOV (vector, immediate)
- C6.3.113 FMOV (register)
- C6.3.114 FMOV (general)
- C6.3.115 FMOV (scalar, immediate)
- C6.3.116 FMSUB
- C6.3.117 FMUL (by element)
- C6.3.118 FMUL (vector)
- C6.3.119 FMUL (scalar)
- C6.3.120 FMULX (by element)
- C6.3.121 FMULX
- C6.3.122 FNEG (vector)
- C6.3.123 FNEG (scalar)
- C6.3.124 FNMADD
- C6.3.125 FNMSUB
- C6.3.126 FNMUL
- C6.3.127 FRECPE
- C6.3.128 FRECPS
- C6.3.129 FRECPX
- C6.3.130 FRINTA (vector)
- C6.3.131 FRINTA (scalar)
- C6.3.132 FRINTI (vector)
- C6.3.133 FRINTI (scalar)
- C6.3.134 FRINTM (vector)
- C6.3.135 FRINTM (scalar)
- C6.3.136 FRINTN (vector)
- C6.3.137 FRINTN (scalar)
- C6.3.138 FRINTP (vector)
- C6.3.139 FRINTP (scalar)
- C6.3.140 FRINTX (vector)
- C6.3.141 FRINTX (scalar)
- C6.3.142 FRINTZ (vector)
- C6.3.143 FRINTZ (scalar)
- C6.3.144 FRSQRTE
- C6.3.145 FRSQRTS
- C6.3.146 FSQRT (vector)
- C6.3.147 FSQRT (scalar)
- C6.3.148 FSUB (vector)
- C6.3.149 FSUB (scalar)
- C6.3.150 INS (element)
- C6.3.151 INS (general)
- C6.3.152 LD1 (multiple structures)
- C6.3.153 LD1 (single structure)
- C6.3.154 LD1R
- C6.3.155 LD2 (multiple structures)
- C6.3.156 LD2 (single structure)
- C6.3.157 LD2R
- C6.3.158 LD3 (multiple structures)
- C6.3.159 LD3 (single structure)
- C6.3.160 LD3R
- C6.3.161 LD4 (multiple structures)
- C6.3.162 LD4 (single structure)
- C6.3.163 LD4R
- C6.3.164 LDNP (SIMD&FP)
- C6.3.165 LDP (SIMD&FP)
- C6.3.166 LDR (immediate, SIMD&FP)
- C6.3.167 LDR (literal, SIMD&FP)
- C6.3.168 LDR (register, SIMD&FP)
- C6.3.169 LDUR (SIMD&FP)
- C6.3.170 MLA (by element)
- C6.3.171 MLA (vector)
- C6.3.172 MLS (by element)
- C6.3.173 MLS (vector)
- C6.3.174 MOV (scalar)
- C6.3.175 MOV (element)
- C6.3.176 MOV (from general)
- C6.3.177 MOV (vector)
- C6.3.178 MOV (to general)
- C6.3.179 MOVI
- C6.3.180 MUL (by element)
- C6.3.181 MUL (vector)
- C6.3.182 MVN
- C6.3.183 MVNI
- C6.3.184 NEG (vector)
- C6.3.185 NOT
- C6.3.186 ORN (vector)
- C6.3.187 ORR (vector, immediate)
- C6.3.188 ORR (vector, register)
- C6.3.189 PMUL
- C6.3.190 PMULL, PMULL2
- C6.3.191 RADDHN, RADDHN2
- C6.3.192 RBIT (vector)
- C6.3.193 REV16 (vector)
- C6.3.194 REV32 (vector)
- C6.3.195 REV64
- C6.3.196 RSHRN, RSHRN2
- C6.3.197 RSUBHN, RSUBHN2
- C6.3.198 SABA
- C6.3.199 SABAL, SABAL2
- C6.3.200 SABD
- C6.3.201 SABDL, SABDL2
- C6.3.202 SADALP
- C6.3.203 SADDL, SADDL2
- C6.3.204 SADDLP
- C6.3.205 SADDLV
- C6.3.206 SADDW, SADDW2
- C6.3.207 SCVTF (vector, fixed-point)
- C6.3.208 SCVTF (vector, integer)
- C6.3.209 SCVTF (scalar, fixed-point)
- C6.3.210 SCVTF (scalar, integer)
- C6.3.211 SHA1C
- C6.3.212 SHA1H
- C6.3.213 SHA1M
- C6.3.214 SHA1P
- C6.3.215 SHA1SU0
- C6.3.216 SHA1SU1
- C6.3.217 SHA256H2
- C6.3.218 SHA256H
- C6.3.219 SHA256SU0
- C6.3.220 SHA256SU1
- C6.3.221 SHADD
- C6.3.222 SHL
- C6.3.223 SHLL, SHLL2
- C6.3.224 SHRN, SHRN2
- C6.3.225 SHSUB
- C6.3.226 SLI
- C6.3.227 SMAX
- C6.3.228 SMAXP
- C6.3.229 SMAXV
- C6.3.230 SMIN
- C6.3.231 SMINP
- C6.3.232 SMINV
- C6.3.233 SMLAL, SMLAL2 (by element)
- C6.3.234 SMLAL, SMLAL2 (vector)
- C6.3.235 SMLSL, SMLSL2 (by element)
- C6.3.236 SMLSL, SMLSL2 (vector)
- C6.3.237 SMOV
- C6.3.238 SMULL, SMULL2 (by element)
- C6.3.239 SMULL, SMULL2 (vector)
- C6.3.240 SQABS
- C6.3.241 SQADD
- C6.3.242 SQDMLAL, SQDMLAL2 (by element)
- C6.3.243 SQDMLAL, SQDMLAL2 (vector)
- C6.3.244 SQDMLSL, SQDMLSL2 (by element)
- C6.3.245 SQDMLSL, SQDMLSL2 (vector)
- C6.3.246 SQDMULH (by element)
- C6.3.247 SQDMULH (vector)
- C6.3.248 SQDMULL, SQDMULL2 (by element)
- C6.3.249 SQDMULL, SQDMULL2 (vector)
- C6.3.250 SQNEG
- C6.3.251 SQRDMULH (by element)
- C6.3.252 SQRDMULH (vector)
- C6.3.253 SQRSHL
- C6.3.254 SQRSHRN, SQRSHRN2
- C6.3.255 SQRSHRUN, SQRSHRUN2
- C6.3.256 SQSHL (immediate)
- C6.3.257 SQSHL (register)
- C6.3.258 SQSHLU
- C6.3.259 SQSHRN, SQSHRN2
- C6.3.260 SQSHRUN, SQSHRUN2
- C6.3.261 SQSUB
- C6.3.262 SQXTN, SQXTN2
- C6.3.263 SQXTUN, SQXTUN2
- C6.3.264 SRHADD
- C6.3.265 SRI
- C6.3.266 SRSHL
- C6.3.267 SRSHR
- C6.3.268 SRSRA
- C6.3.269 SSHL
- C6.3.270 SSHLL, SSHLL2
- C6.3.271 SSHR
- C6.3.272 SSRA
- C6.3.273 SSUBL, SSUBL2
- C6.3.274 SSUBW, SSUBW2
- C6.3.275 ST1 (multiple structures)
- C6.3.276 ST1 (single structure)
- C6.3.277 ST2 (multiple structures)
- C6.3.278 ST2 (single structure)
- C6.3.279 ST3 (multiple structures)
- C6.3.280 ST3 (single structure)
- C6.3.281 ST4 (multiple structures)
- C6.3.282 ST4 (single structure)
- C6.3.283 STNP (SIMD&FP)
- C6.3.284 STP (SIMD&FP)
- C6.3.285 STR (immediate, SIMD&FP)
- C6.3.286 STR (register, SIMD&FP)
- C6.3.287 STUR (SIMD&FP)
- C6.3.288 SUB (vector)
- C6.3.289 SUBHN, SUBHN2
- C6.3.290 SUQADD
- C6.3.291 SXTL
- C6.3.292 TBL
- C6.3.293 TBX
- C6.3.294 TRN1
- C6.3.295 TRN2
- C6.3.296 UABA
- C6.3.297 UABAL, UABAL2
- C6.3.298 UABD
- C6.3.299 UABDL, UABDL2
- C6.3.300 UADALP
- C6.3.301 UADDL, UADDL2
- C6.3.302 UADDLP
- C6.3.303 UADDLV
- C6.3.304 UADDW, UADDW2
- C6.3.305 UCVTF (vector, fixed-point)
- C6.3.306 UCVTF (vector, integer)
- C6.3.307 UCVTF (scalar, fixed-point)
- C6.3.308 UCVTF (scalar, integer)
- C6.3.309 UHADD
- C6.3.310 UHSUB
- C6.3.311 UMAX
- C6.3.312 UMAXP
- C6.3.313 UMAXV
- C6.3.314 UMIN
- C6.3.315 UMINP
- C6.3.316 UMINV
- C6.3.317 UMLAL, UMLAL2 (by element)
- C6.3.318 UMLAL, UMLAL2 (vector)
- C6.3.319 UMLSL, UMLSL2 (by element)
- C6.3.320 UMLSL, UMLSL2 (vector)
- C6.3.321 UMOV
- C6.3.322 UMULL, UMULL2 (by element)
- C6.3.323 UMULL, UMULL2 (vector)
- C6.3.324 UQADD
- C6.3.325 UQRSHL
- C6.3.326 UQRSHRN, UQRSHRN2
- C6.3.327 UQSHL (immediate)
- C6.3.328 UQSHL (register)
- C6.3.329 UQSHRN
- C6.3.330 UQSUB
- C6.3.331 UQXTN, UQXTN2
- C6.3.332 URECPE
- C6.3.333 URHADD
- C6.3.334 URSHL
- C6.3.335 URSHR
- C6.3.336 URSQRTE
- C6.3.337 URSRA
- C6.3.338 USHL
- C6.3.339 USHLL, USHLL2
- C6.3.340 USHR
- C6.3.341 USQADD
- C6.3.342 USRA
- C6.3.343 USUBL, USUBL2
- C6.3.344 USUBW, USUBW2
- C6.3.345 UXTL
- C6.3.346 UZP1
- C6.3.347 UZP2
- C6.3.348 XTN, XTN2
- C6.3.349 ZIP1
- C6.3.350 ZIP2
- Part D: The AArch64 System Level Architecture
- D1: The AArch64 System Level Programmers’ Model
- D1.1 Exception levels
- D1.2 Exception terminology
- D1.3 Execution state
- D1.4 Security state
- D1.5 Virtualization
- D1.6 Registers for instruction processing and exception handling
- D1.7 Process state, PSTATE
- D1.8 Program counter and stack pointer alignment
- D1.9 Reset
- D1.10 Exception entry
- D1.11 Exception return
- D1.12 The Exception level hierarchy
- D1.13 Synchronous exception types, routing and priorities
- D1.14 Asynchronous exception types, routing, masking and priorities
- D1.15 Trapping functionality to higher Exception levels
- D1.15.1 Trapping to EL1 using AArch64
- Traps to EL1 of EL0 accesses to cache maintenance operations
- Traps to EL1 of EL0 execution of WFE and WFI instructions
- Traps to EL1 of EL0 execution of DC ZVA instructions
- Traps to EL1 of EL0 accesses to the PSTATE.{D, A, I, F} interrupt masks
- Traps to EL1 of EL0 accesses to AArch32 deprecated functionality
- Traps to EL1 of EL1 and EL0 System register accesses to the trace registers
- Traps to EL1 of EL1 and EL0 accesses to SIMD and floating-point functionality
- Traps to EL1 of EL0 accesses to the Debug Communications Channel (DCC) registers
- Traps to EL1 of EL0 accesses to Performance Monitors registers
- D1.15.2 Trapping to EL2 using AArch64
- Traps to EL2 of System register access instructions
- Traps to EL2 of Non-secure EL1 accesses to virtual memory control registers
- Disabling Non-secure state execution of HVC instructions
- Traps to EL2 of Non-secure EL1 and EL0 execution of DC ZVA instructions
- Traps to EL2 of Non-secure EL1 execution of TLB maintenance instructions
- Traps to EL2 of Non-secure EL1 and EL0 execution of cache maintenance instructions
- Traps to EL2 of Non-secure EL1 and EL0 accesses to the Auxiliary Control Register
- Traps to EL2 of Non-secure EL1 and EL0 accesses to lockdown, DMA, and TCM operations
- Traps to EL2 of Non-secure EL1 execution of SMC instructions
- Traps to EL2 of Non-secure EL1 and EL0 reads of ID registers
- Traps to EL2 of Non-secure EL1 and EL0 execution of WFE and WFI instructions
- Traps to EL2 of Non-secure EL1 accesses to SIMD and floating-point functionality
- Traps to EL2 of EL2, and Non-secure EL1 and EL0, System register accesses to the trace registers
- Traps to EL2 of Non-secure EL1 and EL0 accesses to the T32EE configuration registers, from AArch32 state only
- Generic trapping to EL2 of Non-secure EL1 and EL0 accesses to System registers, from AArch32 state only
- Traps to EL2 of Non-secure EL1 and EL0 System register accesses to debug registers
- Traps to EL2 of Non-secure EL1 and EL0 accesses to Performance Monitors registers
- D1.15.3 Trapping to EL3 using AArch64
- Traps to EL3 of System register access instructions
- Traps to EL3 of monitor functionality from Secure EL1 using AArch32
- Traps to EL3 of EL2, EL1, and EL0 execution of WFE and WFI instructions
- Traps to EL3 of Secure EL1 accesses to the Counter-timer Physical Secure timer registers
- Enabling EL3, EL2, and EL1 execution of HVC instructions
- Disabling EL3, EL2, and EL1 execution of SMC instructions
- Trapping to EL3 of EL2 accesses to the CPTR_EL2 or HCPTR, and EL1 and EL0 accesses to the CPACR_EL1 or CPACR
- Traps to EL3 of all System register accesses to the trace registers
- Traps to EL3 of all accesses to the SIMD and floating-point registers
- Traps to EL3 of EL2, EL1, and EL0 System register accesses to debug registers
- Traps to EL3 of EL2, EL1, and EL0 accesses to Performance Monitors registers
- D1.15.1 Trapping to EL1 using AArch64
- D1.16 System calls
- D1.17 Use of the ESR_EL1, ESR_EL2, and ESR_EL3
- D1.17.1 Encoding of ISS[24:20] when used for a condition code and valid bit
- D1.17.2 Exceptions with an unknown reason
- D1.17.3 Exception from a WFI or WFE instruction, from AArch32 or AArch64 state
- D1.17.4 Exception from an MCR or MRC access from AArch32 state
- D1.17.5 Exception from an MCRR or MRRC access from AArch32 state
- D1.17.6 Exception from an LDC or STC access to CP14 from AArch32 state
- D1.17.7 Exception from an access to SIMD or floating-point registers, from AArch32 or AArch64
- D1.17.8 Exception from an illegal Execution state, misaligned PC, or misaligned stack pointer
- D1.17.9 Exception from HVC or SVC instruction execution
- D1.17.10 Exception from SMC instruction execution in AArch32 state
- D1.17.11 Exception from SMC instruction execution in AArch64 state
- D1.17.12 Exception from MSR, MRS, or System instruction execution in AArch64 state
- D1.17.13 Exception from an Instruction abort
- D1.17.14 Exception from a Data abort
- D1.17.15 Floating-point exceptions
- D1.17.16 SError interrupt
- D1.17.17 Breakpoint exception or Vector Catch exception
- D1.17.18 Watchpoint exception
- D1.17.19 Software Step exception
- D1.17.20 Software Breakpoint Instruction exception
- D1.18 Mechanisms for entering a low-power state
- D1.19 Self-hosted debug
- D1.20 Performance Monitors extension
- D1.21 Interprocessing
- D1.22 Supported configurations
- D2: Debug Exceptions
- D2.1 Introduction to debug exceptions
- D2.2 Legacy debug exceptions
- D2.3 Understanding the descriptions for AArch64 state and AArch32 state
- D2.4 Software Breakpoint Instruction exceptions
- D2.4.1 About Software Breakpoint Instruction exceptions
- D2.4.2 Breakpoint instructions in the ARMv8-A architecture
- D2.4.3 Exception syndrome information provided by the PE
- D2.4.4 Breakpoint instructions as the first instruction in an IT block
- D2.4.5 Pseudocode description of Software Breakpoint Instruction exceptions
- D2.5 Breakpoint exceptions
- D2.5.1 About Breakpoint exceptions
- D2.5.2 Enable controls for Breakpoint exceptions
- D2.5.3 Conditions for generating a Breakpoint exception
- D2.5.4 About Breakpoint Control Registers
- D2.5.5 Breakpoint types and linking of breakpoints
- D2.5.6 Instruction address comparisons for Breakpoint exception generation
- D2.5.7 Specifying the halfword-aligned address that an address comparison is successful on
- D2.5.8 Context comparisons for Breakpoint exception generation
- D2.5.9 Linked comparisons for Breakpoint exception generation
- D2.5.10 Using breakpoints
- D2.5.11 Summary of breakpoint matching for different breakpoint types
- D2.5.12 Pseudocode descriptions of Breakpoint exceptions taken from AArch64 state
- D2.5.13 Pseudocode descriptions of Breakpoint exceptions taken from AArch32 state
- D2.6 Watchpoint exceptions
- D2.6.1 About Watchpoint exceptions
- D2.6.2 Enable controls for Watchpoint exceptions
- D2.6.3 Conditions for generating a Watchpoint exception
- D2.6.4 About Watchpoint Control Registers
- D2.6.5 Linking of watchpoints
- D2.6.6 Data address comparisons for Watchpoint exception generation
- D2.6.7 Taking into account the size of the data access
- D2.6.8 Programming a watchpoint with eight bytes or fewer
- D2.6.9 Programming a watchpoint with eight or more bytes
- D2.6.10 Programming dependencies of the BAS and MASK fields
- D2.6.11 Linked comparisons for Watchpoint exception generation
- D2.6.12 Determining the memory location that caused a Watchpoint debug event
- D2.6.13 Using watchpoints
- D2.6.14 Summary of watchpoint matching
- D2.6.15 Pseudocode description of Watchpoint exceptions taken from AArch64 state
- D2.6.16 Pseudocode description of Watchpoint exceptions taken from AArch32 state
- D2.7 Vector Catch exceptions
- D2.7.1 About Vector Catch exceptions
- D2.7.2 Enable controls for Vector Catch exceptions
- D2.7.3 Exception vectors that Vector Catch exceptions can be enabled for
- D2.7.4 Generation of Vector Catch exceptions
- D2.7.5 Constraints to consider when programming vector catch
- D2.7.6 Pseudocode description of Vector Catch exceptions
- D2.8 Software Step exceptions
- D2.8.1 About Software Step exceptions
- D2.8.2 Enable controls for software step
- D2.8.3 The software step state machine
- D2.8.4 Rules for enabling software step
- D2.8.5 Entering the active-not-pending state
- D2.8.6 Behavior in the active-not-pending state
- D2.8.7 Entering the active-pending state
- D2.8.8 Behavior in the active-pending state
- D2.8.9 Stepping T32 IT instructions
- D2.8.10 Syndrome information that the PE provides
- D2.8.11 Additional considerations
- D2.8.12 Pseudocode description of Software Step exceptions
- D2.9 Synchronization and debug exceptions
- D3: The Debug Exception Model
- D3.1 About debug exceptions
- D3.2 The debug exceptions enable controls
- D3.3 Routing debug exceptions
- D3.4 Enabling debug exceptions from current Exception level and Security state
- D3.5 The effect of powerdown on debug exceptions
- D3.6 Summary of permitted routing and enabling of debug exceptions
- D3.7 Debug exception behavior
- D3.8 Pseudocode descriptions of debug exceptions
- D4: The AArch64 System Level Memory Model
- D4.1 About the memory system architecture
- D4.2 Address space
- D4.3 Mixed-endian support
- D4.4 Cache support
- D4.4.1 General behavior of the caches
- D4.4.2 Cache identification
- D4.4.3 Cacheability, cache allocation hints, and cache transient hints
- D4.4.4 Behavior of caches at reset
- D4.4.5 Cache enabling and disabling
- D4.4.6 Non-cacheable accesses and instruction caches
- D4.4.7 Cache maintenance operations
- D4.4.8 Cache maintenance instructions
- Instruction cache maintenance instructions (IC*)
- Data cache maintenance instructions (DC*)
- General requirements for the scope of maintenance instructions
- Effects of instructions that operate to the point of coherency
- Effects of instructions that do not operate to the point of coherency
- Effects of virtualization and security on the cache maintenance instructions
- Boundary conditions for cache maintenance instructions
- Ordering and completion of data and instruction cache instructions
- Performing cache maintenance instructions
- D4.4.9 Data cache zero instruction
- D4.4.10 Cache lockdown
- D4.4.11 System level caches
- D4.4.12 Branch prediction
- D4.5 External aborts
- D4.6 Memory barrier instructions
- D4.7 Pseudocode details of general memory system instructions
- D5: The AArch64 Virtual Memory System Architecture
- D5.1 About the Virtual Memory System Architecture (VMSA)
- D5.2 The VMSAv8-64 address translation system
- D5.2.1 About the VMSAv8-64 address translation system
- D5.2.2 Controlling address translation stages
- D5.2.3 Memory translation granule size
- D5.2.4 Translation tables and the translation process
- D5.2.5 Overview of the VMSAv8-64 address translation stages
- D5.2.6 The VMSAv8-64 translation table format
- D5.2.7 The algorithm for finding the translation table entries
- D5.2.8 The effects of disabling a stage of address translation
- D5.2.9 The implemented Exception levels and the resulting translation stages and regimes
- D5.2.10 Pseudocode details of VMSAv8-64 address translation
- D5.2.11 Address translation operations
- D5.3 Translation table walk examples
- D5.3.1 Examples of performing the initial lookup
- D5.3.2 Full translation flows for VMSAv8-64 address translation
- The address and properties fields shown in the translation flows
- Full translation flow using the 4KB granule and starting at the zero level
- Full translation flow using the 4KB granule and starting at the first level
- Full translation flow using the 64KB granule and starting at the first level
- Full translation flow using the 64KB granule and starting at the second level
- D5.4 VMSAv8-64 translation table format descriptors
- D5.5 Access controls and memory region attributes
- D5.5.1 Memory access control
- D5.5.2 Memory region attributes
- D5.5.3 Combining the stage 1 and stage 2 attributes, Non-secure EL1&0 translation regime
- Combining the stage 1 and stage 2 data access permissions
- Combining the stage 1 and stage 2 instruction execution permissions
- Combining the stage 1 and stage 2 memory type attributes
- Combining the stage 1 and stage 2 cacheability attributes for Normal memory
- Combining the stage 1 and stage 2 shareability attributes for Normal memory
- D5.6 MMU faults
- D5.7 Translation Lookaside Buffers (TLBs)
- D5.8 Caches in a VMSA implementation
- D6: The Performance Monitors Extension
- D6.1 About the Performance Monitors
- D6.2 Accuracy of the Performance Monitors
- D6.3 Behavior on overflow
- D6.4 Attributability
- D6.5 Effect of EL3 and EL2
- D6.6 Event filtering
- D6.7 Performance Monitors and Debug state
- D6.8 Counter enables
- D6.9 Counter access
- D6.10 Event numbers and mnemonics
- D6.11 Performance Monitors Extension registers
- D6.12 Pseudocode details
- D7: The Generic Timer
- D8: AArch64 System Register Descriptions
- D8.1 About the AArch64 System registers
- D8.2 General system control registers
- D8.2.1 ACTLR_EL1, Auxiliary Control Register (EL1)
- D8.2.2 ACTLR_EL2, Auxiliary Control Register (EL2)
- D8.2.3 ACTLR_EL3, Auxiliary Control Register (EL3)
- D8.2.4 AFSR0_EL1, Auxiliary Fault Status Register 0 (EL1)
- D8.2.5 AFSR0_EL2, Auxiliary Fault Status Register 0 (EL2)
- D8.2.6 AFSR0_EL3, Auxiliary Fault Status Register 0 (EL3)
- D8.2.7 AFSR1_EL1, Auxiliary Fault Status Register 1 (EL1)
- D8.2.8 AFSR1_EL2, Auxiliary Fault Status Register 1 (EL2)
- D8.2.9 AFSR1_EL3, Auxiliary Fault Status Register 1 (EL3)
- D8.2.10 AIDR_EL1, Auxiliary ID Register
- D8.2.11 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register (EL1)
- D8.2.12 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register (EL2)
- D8.2.13 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register (EL3)
- D8.2.14 CCSIDR_EL1, Current Cache Size ID Register
- D8.2.15 CLIDR_EL1, Cache Level ID Register
- D8.2.16 CONTEXTIDR_EL1, Context ID Register
- D8.2.17 CPACR_EL1, Architectural Feature Access Control Register
- D8.2.18 CPTR_EL2, Architectural Feature Trap Register (EL2)
- D8.2.19 CPTR_EL3, Architectural Feature Trap Register (EL3)
- D8.2.20 CSSELR_EL1, Cache Size Selection Register
- D8.2.21 CTR_EL0, Cache Type Register
- D8.2.22 DACR32_EL2, Domain Access Control Register
- D8.2.23 DCZID_EL0, Data Cache Zero ID register
- D8.2.24 ESR_EL1, Exception Syndrome Register (EL1)
- D8.2.25 ESR_EL2, Exception Syndrome Register (EL2)
- D8.2.26 ESR_EL3, Exception Syndrome Register (EL3)
- D8.2.27 FAR_EL1, Fault Address Register (EL1)
- D8.2.28 FAR_EL2, Fault Address Register (EL2)
- D8.2.29 FAR_EL3, Fault Address Register (EL3)
- D8.2.30 FPEXC32_EL2, Floating-point Exception Control register
- D8.2.31 HACR_EL2, Hypervisor Auxiliary Control Register
- D8.2.32 HCR_EL2, Hypervisor Configuration Register
- D8.2.33 HPFAR_EL2, Hypervisor IPA Fault Address Register
- D8.2.34 HSTR_EL2, Hypervisor System Trap Register
- D8.2.35 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0
- D8.2.36 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1
- D8.2.37 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0
- D8.2.38 ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1
- D8.2.39 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0
- D8.2.40 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1
- D8.2.41 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0
- D8.2.42 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1
- D8.2.43 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0
- D8.2.44 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1
- D8.2.45 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0
- D8.2.46 ID_DFR0_EL1, AArch32 Debug Feature Register 0
- D8.2.47 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0
- D8.2.48 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1
- D8.2.49 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2
- D8.2.50 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3
- D8.2.51 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4
- D8.2.52 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5
- D8.2.53 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0
- D8.2.54 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1
- D8.2.55 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2
- D8.2.56 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3
- D8.2.57 ID_PFR0_EL1, AArch32 Processor Feature Register 0
- D8.2.58 ID_PFR1_EL1, AArch32 Processor Feature Register 1
- D8.2.59 IFSR32_EL2, Instruction Fault Status Register (EL2)
- D8.2.60 ISR_EL1, Interrupt Status Register
- D8.2.61 MAIR_EL1, Memory Attribute Indirection Register (EL1)
- D8.2.62 MAIR_EL2, Memory Attribute Indirection Register (EL2)
- D8.2.63 MAIR_EL3, Memory Attribute Indirection Register (EL3)
- D8.2.64 MIDR_EL1, Main ID Register
- D8.2.65 MPIDR_EL1, Multiprocessor Affinity Register
- D8.2.66 MVFR0_EL1, Media and VFP Feature Register 0
- D8.2.67 MVFR1_EL1, Media and VFP Feature Register 1
- D8.2.68 MVFR2_EL1, Media and VFP Feature Register 2
- D8.2.69 PAR_EL1, Physical Address Register
- D8.2.70 REVIDR_EL1, Revision ID Register
- D8.2.71 RMR_EL1, Reset Management Register (if EL2 and EL3 not implemented)
- D8.2.72 RMR_EL2, Reset Management Register (if EL3 not implemented)
- D8.2.73 RMR_EL3, Reset Management Register (if EL3 implemented)
- D8.2.74 RVBAR_EL1, Reset Vector Base Address Register (if EL2 and EL3 not implemented)
- D8.2.75 RVBAR_EL2, Reset Vector Base Address Register (if EL3 not implemented)
- D8.2.76 RVBAR_EL3, Reset Vector Base Address Register (if EL3 implemented)
- D8.2.77 S3_<op1>_<Cn>_<Cm>_<op2>, IMPLEMENTATION DEFINED registers
- D8.2.78 SCR_EL3, Secure Configuration Register
- D8.2.79 SCTLR_EL1, System Control Register (EL1)
- D8.2.80 SCTLR_EL2, System Control Register (EL2)
- D8.2.81 SCTLR_EL3, System Control Register (EL3)
- D8.2.82 TCR_EL1, Translation Control Register (EL1)
- D8.2.83 TCR_EL2, Translation Control Register (EL2)
- D8.2.84 TCR_EL3, Translation Control Register (EL3)
- D8.2.85 TEECR32_EL1, T32EE Configuration Register
- D8.2.86 TEEHBR32_EL1, T32EE Handler Base Register
- D8.2.87 TPIDR_EL0, Thread Pointer / ID Register (EL0)
- D8.2.88 TPIDR_EL1, Thread Pointer / ID Register (EL1)
- D8.2.89 TPIDR_EL2, Thread Pointer / ID Register (EL2)
- D8.2.90 TPIDR_EL3, Thread Pointer / ID Register (EL3)
- D8.2.91 TPIDRRO_EL0, Thread Pointer / ID Register, Read-Only (EL0)
- D8.2.92 TTBR0_EL1, Translation Table Base Register 0 (EL1)
- D8.2.93 TTBR0_EL2, Translation Table Base Register 0 (EL2)
- D8.2.94 TTBR0_EL3, Translation Table Base Register 0 (EL3)
- D8.2.95 TTBR1_EL1, Translation Table Base Register 1
- D8.2.96 VBAR_EL1, Vector Base Address Register (EL1)
- D8.2.97 VBAR_EL2, Vector Base Address Register (EL2)
- D8.2.98 VBAR_EL3, Vector Base Address Register (EL3)
- D8.2.99 VMPIDR_EL2, Virtualization Multiprocessor ID Register
- D8.2.100 VPIDR_EL2, Virtualization Processor ID Register
- D8.2.101 VTCR_EL2, Virtualization Translation Control Register
- D8.2.102 VTTBR_EL2, Virtualization Translation Table Base Register
- D8.3 Debug registers
- D8.3.1 DBGAUTHSTATUS_EL1, Debug Authentication Status register
- D8.3.2 DBGBCR<n>_EL1, Debug Breakpoint Control Registers, n = 0 - 15
- D8.3.3 DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 - 15
- D8.3.4 DBGCLAIMCLR_EL1, Debug Claim Tag Clear register
- D8.3.5 DBGCLAIMSET_EL1, Debug Claim Tag Set register
- D8.3.6 DBGDTR_EL0, Debug Data Transfer Register, half-duplex
- D8.3.7 DBGDTRRX_EL0, Debug Data Transfer Register, Receive
- D8.3.8 DBGDTRTX_EL0, Debug Data Transfer Register, Transmit
- D8.3.9 DBGPRCR_EL1, Debug Power Control Register
- D8.3.10 DBGVCR32_EL2, Debug Vector Catch Register
- D8.3.11 DBGWCR<n>_EL1, Debug Watchpoint Control Registers, n = 0 - 15
- D8.3.12 DBGWVR<n>_EL1, Debug Watchpoint Value Registers, n = 0 - 15
- D8.3.13 DLR_EL0, Debug Link Register
- D8.3.14 DSPSR_EL0, Debug Saved Program Status Register
- D8.3.15 MDCCINT_EL1, Monitor DCC Interrupt Enable Register
- D8.3.16 MDCCSR_EL0, Monitor DCC Status Register
- D8.3.17 MDCR_EL2, Monitor Debug Configuration Register (EL2)
- D8.3.18 MDCR_EL3, Monitor Debug Configuration Register (EL3)
- D8.3.19 MDRAR_EL1, Monitor Debug ROM Address Register
- D8.3.20 MDSCR_EL1, Monitor Debug System Control Register
- D8.3.21 OSDLR_EL1, OS Double Lock Register
- D8.3.22 OSDTRRX_EL1, OS Lock Data Transfer Register, Receive
- D8.3.23 OSDTRTX_EL1, OS Lock Data Transfer Register, Transmit
- D8.3.24 OSECCR_EL1, OS Lock Exception Catch Control Register
- D8.3.25 OSLAR_EL1, OS Lock Access Register
- D8.3.26 OSLSR_EL1, OS Lock Status Register
- D8.3.27 SDER32_EL3, AArch32 Secure Debug Enable Register
- D8.4 Performance Monitors registers
- D8.4.1 PMCCFILTR_EL0, Performance Monitors Cycle Count Filter Register
- D8.4.2 PMCCNTR_EL0, Performance Monitors Cycle Count Register
- D8.4.3 PMCEID0_EL0, Performance Monitors Common Event Identification register 0
- D8.4.4 PMCEID1_EL0, Performance Monitors Common Event Identification register 1
- D8.4.5 PMCNTENCLR_EL0, Performance Monitors Count Enable Clear register
- D8.4.6 PMCNTENSET_EL0, Performance Monitors Count Enable Set register
- D8.4.7 PMCR_EL0, Performance Monitors Control Register
- D8.4.8 PMEVCNTR<n>_EL0, Performance Monitors Event Count Registers, n = 0 - 30
- D8.4.9 PMEVTYPER<n>_EL0, Performance Monitors Event Type Registers, n = 0 - 30
- D8.4.10 PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear register
- D8.4.11 PMINTENSET_EL1, Performance Monitors Interrupt Enable Set register
- D8.4.12 PMOVSCLR_EL0, Performance Monitors Overflow Flag Status Clear Register
- D8.4.13 PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set register
- D8.4.14 PMSELR_EL0, Performance Monitors Event Counter Selection Register
- D8.4.15 PMSWINC_EL0, Performance Monitors Software Increment register
- D8.4.16 PMUSERENR_EL0, Performance Monitors User Enable Register
- D8.4.17 PMXEVCNTR_EL0, Performance Monitors Selected Event Count Register
- D8.4.18 PMXEVTYPER_EL0, Performance Monitors Selected Event Type Register
- D8.5 Generic Timer registers
- D8.5.1 CNTFRQ_EL0, Counter-timer Frequency register
- D8.5.2 CNTHCTL_EL2, Counter-timer Hypervisor Control register
- D8.5.3 CNTHP_CTL_EL2, Counter-timer Hypervisor Physical Timer Control register
- D8.5.4 CNTHP_CVAL_EL2, Counter-timer Hypervisor Physical Timer CompareValue register
- D8.5.5 CNTHP_TVAL_EL2, Counter-timer Hypervisor Physical Timer TimerValue register
- D8.5.6 CNTKCTL_EL1, Counter-timer Kernel Control register
- D8.5.7 CNTP_CTL_EL0, Counter-timer Physical Timer Control register
- D8.5.8 CNTP_CVAL_EL0, Counter-timer Physical Timer CompareValue register
- D8.5.9 CNTP_TVAL_EL0, Counter-timer Physical Timer TimerValue register
- D8.5.10 CNTPCT_EL0, Counter-timer Physical Count register
- D8.5.11 CNTPS_CTL_EL1, Counter-timer Physical Secure Timer Control register
- D8.5.12 CNTPS_CVAL_EL1, Counter-timer Physical Secure Timer CompareValue register
- D8.5.13 CNTPS_TVAL_EL1, Counter-timer Physical Secure Timer TimerValue register
- D8.5.14 CNTV_CTL_EL0, Counter-timer Virtual Timer Control register
- D8.5.15 CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register
- D8.5.16 CNTV_TVAL_EL0, Counter-timer Virtual Timer TimerValue register
- D8.5.17 CNTVCT_EL0, Counter-timer Virtual Count register
- D8.5.18 CNTVOFF_EL2, Counter-timer Virtual Offset register
- D8.6 Generic Interrupt Controller CPU interface registers
- D8.6.1 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Register (0,0)
- D8.6.2 ICC_AP0R1_EL1, Interrupt Controller Active Priorities Register (0,1)
- D8.6.3 ICC_AP0R2_EL1, Interrupt Controller Active Priorities Register (0,2)
- D8.6.4 ICC_AP0R3_EL1, Interrupt Controller Active Priorities Register (0,3)
- D8.6.5 ICC_AP1R0_EL1, Interrupt Controller Active Priorities Register (1,0)
- D8.6.6 ICC_AP1R1_EL1, Interrupt Controller Active Priorities Register (1,1)
- D8.6.7 ICC_AP1R2_EL1, Interrupt Controller Active Priorities Register (1,2)
- D8.6.8 ICC_AP1R3_EL1, Interrupt Controller Active Priorities Register (1,3)
- D8.6.9 ICC_ASGI1R_EL1, Interrupt Controller Alias Software Generated Interrupt group 1 Register
- D8.6.10 ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0
- D8.6.11 ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1
- D8.6.12 ICC_CTLR_EL1, Interrupt Controller Control Register (EL1)
- D8.6.13 ICC_CTLR_EL3, Interrupt Controller Control Register (EL3)
- D8.6.14 ICC_DIR_EL1, Interrupt Controller Deactivate Interrupt Register
- D8.6.15 ICC_EOIR0_EL1, Interrupt Controller End Of Interrupt Register 0
- D8.6.16 ICC_EOIR1_EL1, Interrupt Controller End Of Interrupt Register 1
- D8.6.17 ICC_HPPIR0_EL1, Interrupt Controller Highest Priority Pending Interrupt Register 0
- D8.6.18 ICC_HPPIR1_EL1, Interrupt Controller Highest Priority Pending Interrupt Register 1
- D8.6.19 ICC_IAR0_EL1, Interrupt Controller Interrupt Acknowledge Register 0
- D8.6.20 ICC_IAR1_EL1, Interrupt Controller Interrupt Acknowledge Register 1
- D8.6.21 ICC_IGRPEN0_EL1, Interrupt Controller Interrupt Group 0 Enable register
- D8.6.22 ICC_IGRPEN1_EL1, Interrupt Controller Interrupt Group 1 Enable register
- D8.6.23 ICC_IGRPEN1_EL3, Interrupt Controller Interrupt Group 1 Enable register (EL3)
- D8.6.24 ICC_PMR_EL1, Interrupt Controller Interrupt Priority Mask Register
- D8.6.25 ICC_RPR_EL1, Interrupt Controller Running Priority Register
- D8.6.26 ICC_SEIEN_EL1, Interrupt Controller System Error Interrupt Enable register
- D8.6.27 ICC_SGI0R_EL1, Interrupt Controller Software Generated Interrupt group 0 Register
- D8.6.28 ICC_SGI1R_EL1, Interrupt Controller Software Generated Interrupt group 1 Register
- D8.6.29 ICC_SRE_EL1, Interrupt Controller System Register Enable register (EL1)
- D8.6.30 ICC_SRE_EL2, Interrupt Controller System Register Enable register (EL2)
- D8.6.31 ICC_SRE_EL3, Interrupt Controller System Register Enable register (EL3)
- D8.6.32 ICH_AP0R0_EL2, Interrupt Controller Hyp Active Priorities Register (0,0)
- D8.6.33 ICH_AP0R1_EL2, Interrupt Controller Hyp Active Priorities Register (0,1)
- D8.6.34 ICH_AP0R2_EL2, Interrupt Controller Hyp Active Priorities Register (0,2)
- D8.6.35 ICH_AP0R3_EL2, Interrupt Controller Hyp Active Priorities Register (0,3)
- D8.6.36 ICH_AP1R0_EL2, Interrupt Controller Hyp Active Priorities Register (1,0)
- D8.6.37 ICH_AP1R1_EL2, Interrupt Controller Hyp Active Priorities Register (1,1)
- D8.6.38 ICH_AP1R2_EL2, Interrupt Controller Hyp Active Priorities Register (1,2)
- D8.6.39 ICH_AP1R3_EL2, Interrupt Controller Hyp Active Priorities Register (1,3)
- D8.6.40 ICH_EISR_EL2, Interrupt Controller End of Interrupt Status Register
- D8.6.41 ICH_ELSR_EL2, Interrupt Controller Empty List Register Status Register
- D8.6.42 ICH_HCR_EL2, Interrupt Controller Hyp Control Register
- D8.6.43 ICH_LR<n>_EL2, Interrupt Controller List Registers, n = 0 - 15
- D8.6.44 ICH_MISR_EL2, Interrupt Controller Maintenance Interrupt State Register
- D8.6.45 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register
- D8.6.46 ICH_VSEIR_EL2, Interrupt Controller Virtual System Error Interrupt Register
- D8.6.47 ICH_VTR_EL2, Interrupt Controller VGIC Type Register
- Part E: The AArch32 Application Level Architecture
- E1: The AArch32 Application Level Programmers’ Model
- E1.1 About the Application level programmers’ model
- E1.2 Additional information about the programmers’ model in AArch32 state
- E1.3 Advanced SIMD and floating-point instructions
- E1.3.1 Floating-point standards, and terminology
- E1.3.2 The Advanced SIMD and floating-point register file
- E1.3.3 Data types supported by the Advanced SIMD implementation
- E1.3.4 Advanced SIMD and Floating-point system registers
- E1.3.5 Trapping of floating-point exception
- E1.3.6 Floating-point data types and arithmetic
- E1.3.7 Floating-point exceptions
- E1.3.8 Implications of not including Advanced SIMD and floating-point support
- E1.3.9 Pseudocode details of floating-point operations
- Generation of specific floating-point values
- Floating-point negation and absolute value
- Floating-point value unpacking
- Floating-point exception and NaN handling
- Floating-point rounding
- Selection of ARM standard floating-point arithmetic
- Floating-point comparisons
- Floating-point maximum and minimum
- Floating-point addition and subtraction
- Floating-point multiplication and division
- Floating-point fused multiply-add
- Floating-point reciprocal estimate and step
- Floating-point square root
- Floating-point reciprocal square root estimate and step
- Floating-point conversions
- E1.4 Coprocessor support
- E1.5 Exceptions and debug events
- E2: The AArch32 Application Level Memory Model
- E2.1 Address space
- E2.2 Memory type overview
- E2.3 Caches and memory hierarchy
- E2.4 Alignment support
- E2.5 Endian support
- E2.6 Atomicity in the ARM architecture
- E2.7 Memory ordering
- E2.8 Memory types and attributes
- E2.9 Mismatched memory attributes
- E2.10 Synchronization and semaphores
- E2.10.1 Exclusive access instructions and Non-shareable memory locations
- E2.10.2 Exclusive access instructions and Shareable memory locations
- E2.10.3 Marking and the size of the marked memory block
- E2.10.4 Context switch support
- E2.10.5 Load-Exclusive and Store-Exclusive instruction usage restrictions
- E2.10.6 Use of WFE and SEV instructions by spin-locks
- Part F: The AArch32 Instruction Sets
- F1: The AArch32 Instruction Sets Overview
- F1.1 Unified Assembler Language
- F1.2 Branch instructions
- F1.3 Data-processing instructions
- F1.3.1 Standard data-processing instructions
- F1.3.2 Shift instructions
- F1.3.3 Multiply instructions
- F1.3.4 Saturating instructions
- F1.3.5 Saturating addition and subtraction instructions
- F1.3.6 Packing and unpacking instructions
- F1.3.7 Parallel addition and subtraction instructions
- F1.3.8 Divide instructions
- F1.3.9 Miscellaneous data-processing instructions
- F1.4 Status register access instructions
- F1.5 Load/store instructions
- F1.6 Load/store multiple instructions
- F1.7 Miscellaneous instructions
- F1.8 Exception-generating and exception-handling instructions
- F1.9 Coprocessor instructions
- F1.10 Advanced SIMD and floating-point load/store instructions
- F1.11 Advanced SIMD and floating-point register transfer instructions
- F1.12 Advanced SIMD data-processing instructions
- F1.12.1 Advanced SIMD parallel addition and subtraction
- F1.12.2 Bitwise Advanced SIMD data-processing instructions
- F1.12.3 Advanced SIMD comparison instructions
- F1.12.4 Advanced SIMD shift instructions
- F1.12.5 Advanced SIMD multiply instructions
- F1.12.6 Miscellaneous Advanced SIMD data-processing instructions
- F1.13 Floating-point data-processing instructions
- F2: About the T32 and A32 Instruction Descriptions
- F2.1 Format of instruction descriptions
- F2.2 Standard assembler syntax fields
- F2.3 Conditional execution
- F2.4 Shifts applied to a register
- F2.5 Memory accesses
- F2.6 Integer arithmetic in the T32 and A32 instruction sets
- F2.7 Encoding of lists of general-purpose registers and the PC
- F2.8 Additional pseudocode support for instruction descriptions
- F3: T32 Base Instruction Set Encoding
- F3.1 T32 instruction set encoding
- F3.2 16-bit T32 instruction encoding
- F3.3 32-bit T32 instruction encoding
- F3.3.1 Data-processing (modified immediate)
- F3.3.2 Modified immediate constants in T32 instructions
- F3.3.3 Data-processing (plain binary immediate)
- F3.3.4 Branches and miscellaneous control
- F3.3.5 Load/store multiple
- F3.3.6 Load/store dual, load/store exclusive, table branch
- F3.3.7 Load word
- F3.3.8 Load halfword, memory hints
- F3.3.9 Load byte, memory hints
- F3.3.10 Store single data item
- F3.3.11 Data-processing (shifted register)
- F3.3.12 Data-processing (register)
- F3.3.13 Parallel addition and subtraction, signed
- F3.3.14 Parallel addition and subtraction, unsigned
- F3.3.15 Miscellaneous operations
- F3.3.16 Multiply, multiply accumulate, and absolute difference
- F3.3.17 Long multiply, long multiply accumulate, and divide
- F3.3.18 Coprocessor, Advanced SIMD, and floating-point instructions
- F4: A32 Base Instruction Set Encoding
- F4.1 A32 instruction set encoding
- F4.2 Data-processing and miscellaneous instructions
- F4.2.1 Data-processing (register)
- F4.2.2 Data-processing (register-shifted register)
- F4.2.3 Data-processing (immediate)
- F4.2.4 Modified immediate constants in A32 instructions
- F4.2.5 Multiply and multiply accumulate
- F4.2.6 Saturating addition and subtraction
- F4.2.7 Halfword multiply and multiply accumulate
- F4.2.8 Extra load/store instructions
- F4.2.9 Extra load/store instructions, unprivileged
- F4.2.10 Synchronization primitives
- F4.2.11 MSR (immediate), and hints
- F4.2.12 Miscellaneous instructions
- F4.3 Load/store word and unsigned byte
- F4.4 Media instructions
- F4.5 Branch, branch with link, and block data transfer
- F4.6 Coprocessor instructions, and Supervisor Call
- F4.7 Unconditional instructions
- F5: T32 and A32 Instruction Sets Advanced SIMD and floating-point Encodings
- F5.1 Overview
- F5.2 Advanced SIMD and floating-point instruction syntax
- F5.3 Register encoding
- F5.4 Advanced SIMD data-processing instructions
- F5.5 Floating-point data-processing instructions
- F5.6 Extension register load/store instructions
- F5.7 Advanced SIMD element or structure load/store instructions
- F5.8 8, 16, and 32-bit transfer between general-purpose and extension registers
- F5.9 64-bit transfers between general-purpose and extension registers
- F6: ARMv8 Changes to the T32 and A32 Instruction Sets
- F6.1 The A32 and T32 instruction sets
- F6.2 Partial Deprecation of IT
- F6.3 New A32 and T32 Load-Acquire/Store-Release instructions
- F6.4 New A32 and T32 scalar floating-point instructions
- F6.4.1 A32 and T32 floating-point conditional select
- F6.4.2 A32 and T32 floating-point minimum and maximum numeric
- F6.4.3 A32 and T32 floating-point to integer conversion
- F6.4.4 A32 and T32 floating-point conversion between half-precision and double-precision
- F6.4.5 A32 and T32 floating-point round to integral
- F6.5 New A32 and T32 Advanced SIMD floating-point instructions
- F6.6 New A32 and T32 cryptography instructions
- F6.7 New A32 and T32 System instructions
- F7: T32 and A32 Base Instruction Set Instruction Descriptions
- F7.1 Alphabetical list of T32 and A32 base instruction set instructions
- F7.1.1 ADC (immediate)
- F7.1.2 ADC (register)
- F7.1.3 ADC (register-shifted register)
- F7.1.4 ADD (immediate, T32)
- F7.1.5 ADD (immediate, A32)
- F7.1.6 ADD (register, T32)
- F7.1.7 ADD (register, A32)
- F7.1.8 ADD (register-shifted register)
- F7.1.9 ADD (SP plus immediate)
- F7.1.10 ADD (SP plus register, T32)
- F7.1.11 ADD (SP plus register, A32)
- F7.1.12 ADR
- F7.1.13 AND (immediate)
- F7.1.14 AND (register)
- F7.1.15 AND (register-shifted register)
- F7.1.16 ASR (immediate)
- F7.1.17 ASR (register)
- F7.1.18 B
- F7.1.19 BFC
- F7.1.20 BFI
- F7.1.21 BIC (immediate)
- F7.1.22 BIC (register)
- F7.1.23 BIC (register-shifted register)
- F7.1.24 BKPT
- F7.1.25 BL, BLX (immediate)
- F7.1.26 BLX (register)
- F7.1.27 BX
- F7.1.28 BXJ
- F7.1.29 CBNZ, CBZ
- F7.1.30 CDP, CDP2
- F7.1.31 CLREX
- F7.1.32 CLZ
- F7.1.33 CMN (immediate)
- F7.1.34 CMN (register)
- F7.1.35 CMN (register-shifted register)
- F7.1.36 CMP (immediate)
- F7.1.37 CMP (register)
- F7.1.38 CMP (register-shifted register)
- F7.1.39 CPS
- F7.1.40 CPY
- F7.1.41 CRC32, CRC32C
- F7.1.42 DBG
- F7.1.43 DCPS1, DCPS2, DCPS3
- F7.1.44 DMB
- F7.1.45 DSB
- F7.1.46 EOR (immediate)
- F7.1.47 EOR (register)
- F7.1.48 EOR (register-shifted register)
- F7.1.49 ERET
- F7.1.50 HLT
- F7.1.51 HVC
- F7.1.52 ISB
- F7.1.53 IT
- F7.1.54 LDA
- F7.1.55 LDAB
- F7.1.56 LDAEX
- F7.1.57 LDAEXB
- F7.1.58 LDAEXD
- F7.1.59 LDAEXH
- F7.1.60 LDAH
- F7.1.61 LDC, LDC2 (immediate)
- F7.1.62 LDC, LDC2 (literal)
- F7.1.63 LDM/LDMIA/LDMFD (T32)
- F7.1.64 LDM/LDMIA/LDMFD (A32)
- F7.1.65 LDMDA/LDMFA
- F7.1.66 LDMDB/LDMEA
- F7.1.67 LDMIB/LDMED
- F7.1.68 LDR (immediate, T32)
- F7.1.69 LDR (immediate, A32)
- F7.1.70 LDR (literal)
- F7.1.71 LDR (register, T32)
- F7.1.72 LDR (register, A32)
- F7.1.73 LDRB (immediate, T32)
- F7.1.74 LDRB (immediate, A32)
- F7.1.75 LDRB (literal)
- F7.1.76 LDRB (register)
- F7.1.77 LDRBT
- F7.1.78 LDRD (immediate)
- F7.1.79 LDRD (literal)
- F7.1.80 LDRD (register)
- F7.1.81 LDREX
- F7.1.82 LDREXB
- F7.1.83 LDREXD
- F7.1.84 LDREXH
- F7.1.85 LDRH (immediate, T32)
- F7.1.86 LDRH (immediate, A32)
- F7.1.87 LDRH (literal)
- F7.1.88 LDRH (register)
- F7.1.89 LDRHT
- F7.1.90 LDRSB (immediate)
- F7.1.91 LDRSB (literal)
- F7.1.92 LDRSB (register)
- F7.1.93 LDRSBT
- F7.1.94 LDRSH (immediate)
- F7.1.95 LDRSH (literal)
- F7.1.96 LDRSH (register)
- F7.1.97 LDRSHT
- F7.1.98 LDRT
- F7.1.99 LSL (immediate)
- F7.1.100 LSL (register)
- F7.1.101 LSR (immediate)
- F7.1.102 LSR (register)
- F7.1.103 MCR, MCR2
- F7.1.104 MCRR, MCRR2
- F7.1.105 MLA
- F7.1.106 MLS
- F7.1.107 MOV (immediate)
- F7.1.108 MOV (register, T32)
- F7.1.109 MOV (register, A32)
- F7.1.110 MOV (shifted register)
- F7.1.111 MOVT
- F7.1.112 MRC, MRC2
- F7.1.113 MRRC, MRRC2
- F7.1.114 MRS
- F7.1.115 MRS (Banked register)
- F7.1.116 MSR (immediate)
- F7.1.117 MSR (register)
- F7.1.118 MSR (Banked register)
- F7.1.119 MUL
- F7.1.120 MVN (immediate)
- F7.1.121 MVN (register)
- F7.1.122 MVN (register-shifted register)
- F7.1.123 NEG
- F7.1.124 NOP
- F7.1.125 ORN (immediate)
- F7.1.126 ORN (register)
- F7.1.127 ORR (immediate)
- F7.1.128 ORR (register)
- F7.1.129 ORR (register-shifted register)
- F7.1.130 PKH
- F7.1.131 PLD, PLDW (immediate)
- F7.1.132 PLD (literal)
- F7.1.133 PLD, PLDW (register)
- F7.1.134 PLI (immediate, literal)
- F7.1.135 PLI (register)
- F7.1.136 POP (T32)
- F7.1.137 POP (A32)
- F7.1.138 PUSH
- F7.1.139 QADD
- F7.1.140 QADD8
- F7.1.141 QADD16
- F7.1.142 QASX
- F7.1.143 QDADD
- F7.1.144 QDSUB
- F7.1.145 QSAX
- F7.1.146 QSUB
- F7.1.147 QSUB8
- F7.1.148 QSUB16
- F7.1.149 RBIT
- F7.1.150 REV
- F7.1.151 REV16
- F7.1.152 REVSH
- F7.1.153 RFE
- F7.1.154 ROR (immediate)
- F7.1.155 ROR (register)
- F7.1.156 RRX
- F7.1.157 RSB (immediate)
- F7.1.158 RSB (register)
- F7.1.159 RSB (register-shifted register)
- F7.1.160 RSC (immediate)
- F7.1.161 RSC (register)
- F7.1.162 RSC (register-shifted register)
- F7.1.163 SADD8
- F7.1.164 SADD16
- F7.1.165 SASX
- F7.1.166 SBC (immediate)
- F7.1.167 SBC (register)
- F7.1.168 SBC (register-shifted register)
- F7.1.169 SBFX
- F7.1.170 SDIV
- F7.1.171 SEL
- F7.1.172 SETEND
- F7.1.173 SEV
- F7.1.174 SEVL
- F7.1.175 SHADD8
- F7.1.176 SHADD16
- F7.1.177 SHASX
- F7.1.178 SHSAX
- F7.1.179 SHSUB8
- F7.1.180 SHSUB16
- F7.1.181 SMC (previously SMI)
- F7.1.182 SMLABB, SMLABT, SMLATB, SMLATT
- F7.1.183 SMLAD
- F7.1.184 SMLAL
- F7.1.185 SMLALBB, SMLALBT, SMLALTB, SMLALTT
- F7.1.186 SMLALD
- F7.1.187 SMLAWB, SMLAWT
- F7.1.188 SMLSD
- F7.1.189 SMLSLD
- F7.1.190 SMMLA
- F7.1.191 SMMLS
- F7.1.192 SMMUL
- F7.1.193 SMUAD
- F7.1.194 SMULBB, SMULBT, SMULTB, SMULTT
- F7.1.195 SMULL
- F7.1.196 SMULWB, SMULWT
- F7.1.197 SMUSD
- F7.1.198 SRS
- F7.1.199 SSAT
- F7.1.200 SSAT16
- F7.1.201 SSAX
- F7.1.202 SSUB8
- F7.1.203 SSUB16
- F7.1.204 STC, STC2
- F7.1.205 STL
- F7.1.206 STLB
- F7.1.207 STLEX
- F7.1.208 STLEXB
- F7.1.209 STLEXD
- F7.1.210 STLEXH
- F7.1.211 STLH
- F7.1.212 STM (STMIA, STMEA)
- F7.1.213 STMDA (STMED)
- F7.1.214 STMDB (STMFD)
- F7.1.215 STMIB (STMFA)
- F7.1.216 STR (immediate, T32)
- F7.1.217 STR (immediate, A32)
- F7.1.218 STR (register)
- F7.1.219 STRB (immediate, T32)
- F7.1.220 STRB (immediate, A32)
- F7.1.221 STRB (register)
- F7.1.222 STRBT
- F7.1.223 STRD (immediate)
- F7.1.224 STRD (register)
- F7.1.225 STREX
- F7.1.226 STREXB
- F7.1.227 STREXD
- F7.1.228 STREXH
- F7.1.229 STRH (immediate, T32)
- F7.1.230 STRH (immediate, A32)
- F7.1.231 STRH (register)
- F7.1.232 STRHT
- F7.1.233 STRT
- F7.1.234 SUB (immediate, T32)
- F7.1.235 SUB (immediate, A32)
- F7.1.236 SUB (register)
- F7.1.237 SUB (register-shifted register)
- F7.1.238 SUB (SP minus immediate)
- F7.1.239 SUB (SP minus register)
- F7.1.240 SUBS PC, LR and related instructions
- F7.1.241 SVC (previously SWI)
- F7.1.242 SXTAB
- F7.1.243 SXTAB16
- F7.1.244 SXTAH
- F7.1.245 SXTB
- F7.1.246 SXTB16
- F7.1.247 SXTH
- F7.1.248 TBB, TBH
- F7.1.249 TEQ (immediate)
- F7.1.250 TEQ (register)
- F7.1.251 TEQ (register-shifted register)
- F7.1.252 TST (immediate)
- F7.1.253 TST (register)
- F7.1.254 TST (register-shifted register)
- F7.1.255 UADD8
- F7.1.256 UADD16
- F7.1.257 UASX
- F7.1.258 UBFX
- F7.1.259 UDF
- F7.1.260 UDIV
- F7.1.261 UHADD8
- F7.1.262 UHADD16
- F7.1.263 UHASX
- F7.1.264 UHSAX
- F7.1.265 UHSUB8
- F7.1.266 UHSUB16
- F7.1.267 UMAAL
- F7.1.268 UMLAL
- F7.1.269 UMULL
- F7.1.270 UQADD8
- F7.1.271 UQADD16
- F7.1.272 UQASX
- F7.1.273 UQSAX
- F7.1.274 UQSUB8
- F7.1.275 UQSUB16
- F7.1.276 USAD8
- F7.1.277 USADA8
- F7.1.278 USAT
- F7.1.279 USAT16
- F7.1.280 USAX
- F7.1.281 USUB8
- F7.1.282 USUB16
- F7.1.283 UXTAB
- F7.1.284 UXTAB16
- F7.1.285 UXTAH
- F7.1.286 UXTB
- F7.1.287 UXTB16
- F7.1.288 UXTH
- F7.1.289 WFE
- F7.1.290 WFI
- F7.1.291 YIELD
- F7.2 General restrictions on system instructions
- F7.3 Encoding and use of Banked register transfer instructions
- F7.4 Alphabetical list of system instructions
- F7.4.1 CPS (T32)
- F7.4.2 CPS (A32)
- F7.4.3 ERET
- F7.4.4 HVC
- F7.4.5 LDM (exception return)
- F7.4.6 LDM (User registers)
- F7.4.7 LDRBT, LDRHT, LDRSBT, LDRSHT, and LDRT
- F7.4.8 MRS
- F7.4.9 MRS (Banked register)
- F7.4.10 MSR (Banked register)
- F7.4.11 MSR (immediate)
- F7.4.12 MSR (register)
- F7.4.13 RFE
- F7.4.14 SMC (previously SMI)
- F7.4.15 SRS (T32)
- F7.4.16 SRS (A32)
- F7.4.17 STM (User registers)
- F7.4.18 STRBT, STRHT, and STRT
- F7.4.19 SUBS PC, LR and related instructions (T32)
- F7.4.20 SUBS PC, LR and related instructions (A32)
- F7.4.21 VMRS
- F7.4.22 VMSR
- F7.1 Alphabetical list of T32 and A32 base instruction set instructions
- F8: T32 and A32 Advanced SIMD and floating-point Instruction Descriptions
- F8.1 Alphabetical list of floating-point and Advanced SIMD instructions
- F8.1.1 AESD
- F8.1.2 AESE
- F8.1.3 AESIMC
- F8.1.4 AESMC
- F8.1.5 F*, former floating-point instruction mnemonics
- F8.1.6 SHA1C
- F8.1.7 SHA1H
- F8.1.8 SHA1M
- F8.1.9 SHA1P
- F8.1.10 SHA1SU0
- F8.1.11 SHA1SU1
- F8.1.12 SHA256H
- F8.1.13 SHA256H2
- F8.1.14 SHA256SU0
- F8.1.15 SHA256SU1
- F8.1.16 VABA, VABAL
- F8.1.17 VABD, VABDL (integer)
- F8.1.18 VABD (floating-point)
- F8.1.19 VABS
- F8.1.20 VACGE, VACGT, VACLE, VACLT
- F8.1.21 VADD (integer)
- F8.1.22 VADD (floating-point)
- F8.1.23 VADDHN
- F8.1.24 VADDL, VADDW
- F8.1.25 VAND (immediate)
- F8.1.26 VAND (register)
- F8.1.27 VBIC (immediate)
- F8.1.28 VBIC (register)
- F8.1.29 VBIF, VBIT, VBSL
- F8.1.30 VCEQ (register)
- F8.1.31 VCEQ (immediate #0)
- F8.1.32 VCGE (register)
- F8.1.33 VCGE (immediate #0)
- F8.1.34 VCGT (register)
- F8.1.35 VCGT (immediate #0)
- F8.1.36 VCLE (register)
- F8.1.37 VCLE (immediate #0)
- F8.1.38 VCLS
- F8.1.39 VCLT (register)
- F8.1.40 VCLT (immediate #0)
- F8.1.41 VCLZ
- F8.1.42 VCMP, VCMPE
- F8.1.43 VCNT
- F8.1.44 VCVT (between floating-point and integer, Advanced SIMD)
- F8.1.45 VCVT, VCVTR (between floating-point and integer, floating-point)
- F8.1.46 VCVT (between floating-point and fixed-point, Advanced SIMD)
- F8.1.47 VCVT (between floating-point and fixed-point, floating-point)
- F8.1.48 VCVT (between double-precision and single-precision)
- F8.1.49 VCVT (between half-precision and single-precision, Advanced SIMD)
- F8.1.50 VCVTA, VCVTN, VCVTP, VCVTM (between floating-point and integer, Advanced SIMD)
- F8.1.51 VCVTA, VCVTN, VCVTP, VCVTM (between floating-point and integer, floating-point)
- F8.1.52 VCVTB, VCVTT
- F8.1.53 VDIV
- F8.1.54 VDUP (scalar)
- F8.1.55 VDUP (general-purpose register)
- F8.1.56 VEOR
- F8.1.57 VEXT
- F8.1.58 VFMA, VFMS
- F8.1.59 VFNMA, VFNMS
- F8.1.60 VHADD, VHSUB
- F8.1.61 VLD1 (multiple single elements)
- F8.1.62 VLD1 (single element to one lane)
- F8.1.63 VLD1 (single element to all lanes)
- F8.1.64 VLD2 (multiple 2-element structures)
- F8.1.65 VLD2 (single 2-element structure to one lane)
- F8.1.66 VLD2 (single 2-element structure to all lanes)
- F8.1.67 VLD3 (multiple 3-element structures)
- F8.1.68 VLD3 (single 3-element structure to one lane)
- F8.1.69 VLD3 (single 3-element structure to all lanes)
- F8.1.70 VLD4 (multiple 4-element structures)
- F8.1.71 VLD4 (single 4-element structure to one lane)
- F8.1.72 VLD4 (single 4-element structure to all lanes)
- F8.1.73 VLDM
- F8.1.74 VLDR
- F8.1.75 VMAX, VMIN (integer)
- F8.1.76 VMAX, VMIN (floating-point)
- F8.1.77 VMAXNM, VMINNM
- F8.1.78 VMLA, VMLAL, VMLS, VMLSL (integer)
- F8.1.79 VMLA, VMLS (floating-point)
- F8.1.80 VMLA, VMLAL, VMLS, VMLSL (by scalar)
- F8.1.81 VMOV (immediate)
- F8.1.82 VMOV (register)
- F8.1.83 VMOV (general-purpose register to scalar)
- F8.1.84 VMOV (scalar to general-purpose register)
- F8.1.85 VMOV (between general-purpose register and single-precision register)
- F8.1.86 VMOV (between two general-purpose registers and two single-precision registers)
- F8.1.87 VMOV (between two general-purpose registers and a doubleword extension register)
- F8.1.88 VMOVL
- F8.1.89 VMOVN
- F8.1.90 VMRS
- F8.1.91 VMSR
- F8.1.92 VMUL, VMULL (integer and polynomial)
- F8.1.93 VMUL (floating-point)
- F8.1.94 VMUL, VMULL (by scalar)
- F8.1.95 VMVN (immediate)
- F8.1.96 VMVN (register)
- F8.1.97 VNEG
- F8.1.98 VNMLA, VNMLS, VNMUL
- F8.1.99 VORN (immediate)
- F8.1.100 VORN (register)
- F8.1.101 VORR (immediate)
- F8.1.102 VORR (register)
- F8.1.103 VPADAL
- F8.1.104 VPADD (integer)
- F8.1.105 VPADD (floating-point)
- F8.1.106 VPADDL
- F8.1.107 VPMAX, VPMIN (integer)
- F8.1.108 VPMAX, VPMIN (floating-point)
- F8.1.109 VPOP
- F8.1.110 VPUSH
- F8.1.111 VQABS
- F8.1.112 VQADD
- F8.1.113 VQDMLAL, VQDMLSL
- F8.1.114 VQDMULH
- F8.1.115 VQDMULL
- F8.1.116 VQMOVN, VQMOVUN
- F8.1.117 VQNEG
- F8.1.118 VQRDMULH
- F8.1.119 VQRSHL
- F8.1.120 VQRSHRN, VQRSHRUN
- F8.1.121 VQSHL (register)
- F8.1.122 VQSHL, VQSHLU (immediate)
- F8.1.123 VQSHRN, VQSHRUN
- F8.1.124 VQSUB
- F8.1.125 VRADDHN
- F8.1.126 VRECPE
- F8.1.127 VRECPS
- F8.1.128 VREV16, VREV32, VREV64
- F8.1.129 VRHADD
- F8.1.130 VRINTA, VRINTN, VRINTP, VRINTM (Advanced SIMD)
- F8.1.131 VRINTA, VRINTN, VRINTP, VRINTM (floating-point)
- F8.1.132 VRINTX (Advanced SIMD)
- F8.1.133 VRINTX (floating-point)
- F8.1.134 VRINTZ (Advanced SIMD)
- F8.1.135 VRINTZ, VRINTR (floating-point)
- F8.1.136 VRSHL
- F8.1.137 VRSHR
- F8.1.138 VRSHRN
- F8.1.139 VRSQRTE
- F8.1.140 VRSQRTS
- F8.1.141 VRSRA
- F8.1.142 VRSUBHN
- F8.1.143 VSEL
- F8.1.144 VSHL (immediate)
- F8.1.145 VSHL (register)
- F8.1.146 VSHLL
- F8.1.147 VSHR
- F8.1.148 VSHRN
- F8.1.149 VSLI
- F8.1.150 VSQRT
- F8.1.151 VSRA
- F8.1.152 VSRI
- F8.1.153 VST1 (multiple single elements)
- F8.1.154 VST1 (single element from one lane)
- F8.1.155 VST2 (multiple 2-element structures)
- F8.1.156 VST2 (single 2-element structure from one lane)
- F8.1.157 VST3 (multiple 3-element structures)
- F8.1.158 VST3 (single 3-element structure from one lane)
- F8.1.159 VST4 (multiple 4-element structures)
- F8.1.160 VST4 (single 4-element structure from one lane)
- F8.1.161 VSTM
- F8.1.162 VSTR
- F8.1.163 VSUB (integer)
- F8.1.164 VSUB (floating-point)
- F8.1.165 VSUBHN
- F8.1.166 VSUBL, VSUBW
- F8.1.167 VSWP
- F8.1.168 VTBL, VTBX
- F8.1.169 VTRN
- F8.1.170 VTST
- F8.1.171 VUZP
- F8.1.172 VZIP
- F8.1 Alphabetical list of floating-point and Advanced SIMD instructions
- Part G: The AArch32 System Level Architecture
- G1: The AArch32 System Level Programmers’ Model
- G1.1 About the AArch32 System level programmers’ model
- G1.2 Exception levels
- G1.3 Exception terminology
- G1.4 Execution state
- G1.5 Instruction Set state
- G1.6 Debug state
- G1.7 Security state
- G1.8 Virtualization
- G1.9 AArch32 PE modes, general-purpose registers, and the PC
- G1.10 Instruction set states
- G1.11 Handling exceptions that are taken to an Exception level using AArch32
- G1.11.1 Exception vectors and the exception base address
- G1.11.2 Exception priority order
- G1.11.3 Overview of exception entry
- G1.11.4 PE mode for taking exceptions
- G1.11.5 PE state on exception entry
- G1.11.6 Routing general exceptions to EL2
- G1.11.7 Routing Debug exceptions to Hyp mode
- G1.11.8 Exception return to an Exception level using AArch32
- G1.11.9 Wait For Event and Send Event
- G1.11.10 Wait For Interrupt
- G1.12 Asynchronous exception behavior for exceptions taken from AArch32 state
- G1.13 AArch32 state exception descriptions
- G1.13.1 Reset
- G1.13.2 Undefined Instruction exception
- G1.13.3 Hyp Trap exception
- G1.13.4 Supervisor Call (SVC) exception
- G1.13.5 Secure Monitor Call (SMC) exception
- G1.13.6 Hypervisor Call (HVC) exception
- G1.13.7 Prefetch Abort exception
- G1.13.8 Data Abort exception
- G1.13.9 Virtual Abort exception
- G1.13.10 IRQ exception
- G1.13.11 Virtual IRQ exception
- G1.13.12 FIQ exception
- G1.13.13 Virtual FIQ exception
- G1.13.14 Additional pseudocode functions for exception handling
- G1.14 The conceptual coprocessor interface and system control
- G1.15 Advanced SIMD and floating-point support
- G1.16 AArch32 control of traps to the hypervisor
- G1.16.1 General information about traps to the hypervisor
- G1.16.2 Trapping ID mechanisms
- G1.16.3 Trapping accesses to lockdown, DMA, and TCM operations
- G1.16.4 Trapping accesses to cache maintenance operations
- G1.16.5 Trapping accesses to TLB maintenance operations
- G1.16.6 Trapping accesses to the Auxiliary Control Register
- G1.16.7 Trapping accesses to the Performance Monitors Extension
- G1.16.8 Trapping use of the SMC instruction
- G1.16.9 Trapping use of the WFI and WFE instructions
- G1.16.10 Trapping accesses to the T32EE configuration registers
- G1.16.11 Trapping accesses to coprocessors
- G1.16.12 Trapping writes to virtual memory control registers
- G1.16.13 Generic trapping of accesses to CP15 system control registers
- G1.16.14 Trapping CP14 accesses to debug registers
- G1.16.15 Trapping CP14 accesses to trace registers
- G1.16.16 Summary of trap controls
- G2: The AArch32 System Level Memory Model
- G2.1 About the memory system architecture
- G2.2 Address space
- G2.3 Mixed-endian support
- G2.4 Cache support
- G2.4.1 General behavior of the caches
- G2.4.2 Cache identification
- G2.4.3 Cacheability, cache allocation hints, and cache transient hints
- G2.4.4 Behavior of caches at reset
- G2.4.5 Cache enabling and disabling
- G2.4.6 The ARMv8 cache maintenance functionality
- G2.4.7 Branch predictors
- G2.4.8 Cache maintenance instructions
- Instruction cache maintenance instructions (IC*)
- Data cache maintenance instructions (DC*)
- General requirements for the scope of cache and branch predictor maintenance instructions
- Effects of instructions that operate to the point of coherency
- Effects of instructions that do not operate to the point of coherency
- Effects of virtualization and security on the cache maintenance instructions
- Boundary conditions for cache maintenance instructions
- Ordering of cache and branch predictor maintenance instructions
- Performing cache maintenance instructions
- G2.4.9 Cache lockdown
- G2.4.10 System level caches
- G2.5 ARMv8 CP15 register support for IMPLEMENTATION DEFINED features
- G2.6 External aborts
- G2.7 Memory barrier instructions
- G2.8 Pseudocode details of general memory system instructions
- G3: The AArch32 Virtual Memory System Architecture
- G3.1 Execution privilege, Exception levels, and AArch32 Privilege levels
- G3.2 About VMSAv8-32
- G3.3 The effects of disabling address translation stages on VMSAv8-32 behavior
- G3.4 Translation tables
- G3.4.1 Translation table walks for memory accesses using VMSAv8-32 translation regimes
- G3.4.2 Information returned by a translation table lookup
- G3.4.3 Determining the translation table base address in the VMSAv8-32 translation regimes
- G3.4.4 Control of translation table walks on a TLB miss
- G3.4.5 Access to the Secure or Non-secure physical address map
- G3.5 The VMSAv8-32 Short-descriptor translation table format
- G3.5.1 VMSAv8-32 Short-descriptor translation table format descriptors
- G3.5.2 Memory attributes in the VMSAv8-32 Short-descriptor translation table format descriptors
- G3.5.3 Control of Secure or Non-secure memory access, VMSAv8-32 Short-descriptor format
- G3.5.4 Selecting between TTBR0 and TTBR1, VMSAv8-32 Short-descriptor translation table format
- G3.5.5 Translation table walks, when using the VMSAv8-32 Short-descriptor translation table format
- G3.6 The VMSAv8-32 Long-descriptor translation table format
- G3.6.1 Overview of VMSAv8-32 address translation using Long-descriptor translation tables
- G3.6.2 VMSAv8-32 Long-descriptor translation table format descriptors
- G3.6.3 Memory attributes in the VMSAv8-32 Long-descriptor translation table format descriptors
- G3.6.4 Control of Secure or Non-secure memory access, VMSAv8-32 Long-descriptor format
- G3.6.5 Selecting between TTBR0 and TTBR1, VMSAv8-32 Long-descriptor translation table format
- G3.6.6 VMSAv8-32 Long-descriptor translation table format address lookup levels
- G3.6.7 Translation table walks, when using the VMSAv8-32 Long-descriptor translation table format
- G3.7 Memory access control
- G3.8 Memory region attributes
- G3.8.1 Overview of memory region attributes for stage 1 translations
- G3.8.2 Short-descriptor format memory region attributes, without TEX remap
- G3.8.3 Short-descriptor format memory region attributes, with TEX remap
- G3.8.4 VMSAv8-32 Long-descriptor format memory region attributes
- G3.8.5 EL2 control of Non-secure memory region attributes
- G3.9 Translation Lookaside Buffers (TLBs)
- G3.10 TLB maintenance requirements
- G3.11 Caches in VMSAv8-32
- G3.12 VMSAv8-32 memory aborts
- G3.13 Exception reporting in a VMSAv8-32 implementation
- G3.13.1 About exception reporting
- G3.13.2 Reporting exceptions taken to PL1 modes
- G3.13.3 Fault reporting in PL1 modes
- G3.13.4 Summary of register updates on faults taken to PL1 modes
- G3.13.5 Reporting exceptions taken to Hyp mode
- G3.13.6 Use of the HSR
- G3.13.7 Summary of register updates on exceptions taken to Hyp mode
- G3.14 Virtual Address to Physical Address translation operations
- G3.15 About the System registers for VMSAv8-32
- G3.16 Organization of the CP14 registers in VMSAv8-32
- G3.17 Organization of the CP15 registers in VMSAv8-32
- G3.17.1 CP15 32-bit register summary by coprocessor register number, CRn
- VMSAv8-32 CP15 c0 register summary
- VMSAv8-32 CP15 c1 register summary
- VMSAv8-32 CP15 c2 and c3 register summary
- VMSAv8-32 CP15 c4 register summary
- VMSAv8-32 CP15 c5 and c6 register summary
- VMSAv8-32 CP15 c7 register summary
- VMSAv8-32 CP15 c8 register summary
- VMSAv8-32 CP15 c9 register summary
- VMSAv8-32 CP15 c10 register summary
- VMSAv8-32 CP15 c11 register summary
- VMSAv8-32 CP15 c12 register summary
- VMSAv8-32 CP15 c13 register summary
- VMSAv8-32 CP15 c14 register summary
- VMSAv8-32 CP15 c15 register summary
- G3.17.2 Full list of VMSAv8-32 CP15 registers, by coprocessor register number
- G3.17.3 Views of the CP15 registers
- G3.17.1 CP15 32-bit register summary by coprocessor register number, CRn
- G3.18 Functional grouping of VMSAv8-32 System registers
- G3.18.1 Identification registers, functional group
- G3.18.2 Other system control registers, functional group
- G3.18.3 Virtual memory control registers, functional group
- G3.18.4 Virtualization registers, functional group
- G3.18.5 Security registers, functional group
- G3.18.6 Exception and fault handling registers, functional group
- G3.18.7 Reset management registers, functional group
- G3.18.8 Thread and process ID registers, functional group
- G3.18.9 Cache maintenance operations, functional group
- G3.18.10 TLB maintenance operations, functional group
- G3.18.11 Address translation operations, functional group
- G3.18.12 Lockdown, DMA, and TCM features, functional group
- G3.18.13 Performance Monitors Extension registers, functional group
- G3.18.14 Generic Timer Extension registers, functional group
- G3.18.15 Generic Interrupt Controller CPU interface registers, functional group
- G3.18.16 Legacy feature registers, functional group
- G3.18.17 IMPLEMENTATION DEFINED registers, functional group
- G3.18.18 Floating-point registers, functional group
- G3.18.19 Debug registers, functional group
- G3.19 Pseudocode details of VMSAv8-32 memory system operations
- G4: AArch32 System Register Descriptions
- G4.1 About the AArch32 System registers
- G4.2 General system control registers
- G4.2.1 ACTLR, Auxiliary Control Register
- G4.2.2 ADFSR, Auxiliary Data Fault Status Register
- G4.2.3 AIDR, Auxiliary ID Register
- G4.2.4 AIFSR, Auxiliary Instruction Fault Status Register
- G4.2.5 AMAIR0, Auxiliary Memory Attribute Indirection Register 0
- G4.2.6 AMAIR1, Auxiliary Memory Attribute Indirection Register 1
- G4.2.7 APSR, Application Program Status Register
- G4.2.8 ATS12NSOPR, Address Translate Stages 1 and 2 Non-secure Only PL1 Read
- G4.2.9 ATS12NSOPW, Address Translate Stages 1 and 2 Non-secure Only PL1 Write
- G4.2.10 ATS12NSOUR, Address Translate Stages 1 and 2 Non-secure Only Unprivileged Read
- G4.2.11 ATS12NSOUW, Address Translate Stages 1 and 2 Non-secure Only Unprivileged Write
- G4.2.12 ATS1CPR, Address Translate Stage 1 Current state PL1 Read
- G4.2.13 ATS1CPW, Address Translate Stage 1 Current state PL1 Write
- G4.2.14 ATS1CUR, Address Translate Stage 1 Current state Unprivileged Read
- G4.2.15 ATS1CUW, Address Translate Stage 1 Current state Unprivileged Write
- G4.2.16 ATS1HR, Address Translate Stage 1 Hyp mode Read
- G4.2.17 ATS1HW, Address Translate Stage 1 Hyp mode Write
- G4.2.18 BPIALL, Branch Predictor Invalidate All
- G4.2.19 BPIALLIS, Branch Predictor Invalidate All, Inner Shareable
- G4.2.20 BPIMVA, Branch Predictor Invalidate VA
- G4.2.21 CCSIDR, Current Cache Size ID Register
- G4.2.22 CLIDR, Cache Level ID Register
- G4.2.23 CONTEXTIDR, Context ID Register
- G4.2.24 CP15DMB, CP15 Data Memory Barrier operation
- G4.2.25 CP15DSB, CP15 Data Synchronization Barrier operation
- G4.2.26 CP15ISB, CP15 Instruction Synchronization Barrier operation
- G4.2.27 CPACR, Architectural Feature Access Control Register
- G4.2.28 CPSR, Current Program Status Register
- G4.2.29 CSSELR, Cache Size Selection Register
- G4.2.30 CTR, Cache Type Register
- G4.2.31 DACR, Domain Access Control Register
- G4.2.32 DCCIMVAC, Data Cache line Clean and Invalidate by VA to PoC
- G4.2.33 DCCISW, Data Cache line Clean and Invalidate by Set/Way
- G4.2.34 DCCMVAC, Data Cache line Clean by VA to PoC
- G4.2.35 DCCMVAU, Data Cache line Clean by VA to PoU
- G4.2.36 DCCSW, Data Cache line Clean by Set/Way
- G4.2.37 DCIMVAC, Data Cache line Invalidate by VA to PoC
- G4.2.38 DCISW, Data Cache line Invalidate by Set/Way
- G4.2.39 DFAR, Data Fault Address Register
- G4.2.40 DFSR, Data Fault Status Register
- G4.2.41 DTLBIALL, Data TLB Invalidate All entries
- G4.2.42 DTLBIASID, Data TLB Invalidate by ASID match
- G4.2.43 DTLBIMVA, Data TLB Invalidate entry by VA
- G4.2.44 ELR_hyp, Exception Link Register (Hyp mode)
- G4.2.45 FCSEIDR, FCSE Process ID register
- G4.2.46 FPEXC, Floating-Point Exception Control register
- G4.2.47 FPSCR, Floating-Point Status and Control Register
- G4.2.48 FPSID, Floating-Point System ID register
- G4.2.49 HACR, Hyp Auxiliary Configuration Register
- G4.2.50 HACTLR, Hyp Auxiliary Control Register
- G4.2.51 HADFSR, Hyp Auxiliary Data Fault Status Register
- G4.2.52 HAIFSR, Hyp Auxiliary Instruction Fault Status Register
- G4.2.53 HAMAIR0, Hyp Auxiliary Memory Attribute Indirection Register 0
- G4.2.54 HAMAIR1, Hyp Auxiliary Memory Attribute Indirection Register 1
- G4.2.55 HCPTR, Hyp Architectural Feature Trap Register
- G4.2.56 HCR, Hyp Configuration Register
- G4.2.57 HCR2, Hyp Configuration Register 2
- G4.2.58 HDFAR, Hyp Data Fault Address Register
- G4.2.59 HIFAR, Hyp Instruction Fault Address Register
- G4.2.60 HMAIR0, Hyp Memory Attribute Indirection Register 0
- G4.2.61 HMAIR1, Hyp Memory Attribute Indirection Register 1
- G4.2.62 HPFAR, Hyp IPA Fault Address Register
- G4.2.63 HRMR, Hyp Reset Management Register
- G4.2.64 HSCTLR, Hyp System Control Register
- G4.2.65 HSR, Hyp Syndrome Register
- G4.2.66 HSTR, Hyp System Trap Register
- G4.2.67 HTCR, Hyp Translation Control Register
- G4.2.68 HTPIDR, Hyp Thread Pointer / ID Register
- G4.2.69 HTTBR, Hyp Translation Table Base Register
- G4.2.70 HVBAR, Hyp Vector Base Address Register
- G4.2.71 ICIALLU, Instruction Cache Invalidate All to PoU
- G4.2.72 ICIALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
- G4.2.73 ICIMVAU, Instruction Cache line Invalidate by VA to PoU
- G4.2.74 ID_AFR0, Auxiliary Feature Register 0
- G4.2.75 ID_DFR0, Debug Feature Register 0
- G4.2.76 ID_ISAR0, Instruction Set Attribute Register 0
- G4.2.77 ID_ISAR1, Instruction Set Attribute Register 1
- G4.2.78 ID_ISAR2, Instruction Set Attribute Register 2
- G4.2.79 ID_ISAR3, Instruction Set Attribute Register 3
- G4.2.80 ID_ISAR4, Instruction Set Attribute Register 4
- G4.2.81 ID_ISAR5, Instruction Set Attribute Register 5
- G4.2.82 ID_MMFR0, Memory Model Feature Register 0
- G4.2.83 ID_MMFR1, Memory Model Feature Register 1
- G4.2.84 ID_MMFR2, Memory Model Feature Register 2
- G4.2.85 ID_MMFR3, Memory Model Feature Register 3
- G4.2.86 ID_PFR0, Processor Feature Register 0
- G4.2.87 ID_PFR1, Processor Feature Register 1
- G4.2.88 IFAR, Instruction Fault Address Register
- G4.2.89 IFSR, Instruction Fault Status Register
- G4.2.90 ISR, Interrupt Status Register
- G4.2.91 ITLBIALL, Instruction TLB Invalidate All entries
- G4.2.92 ITLBIASID, Instruction TLB Invalidate by ASID match
- G4.2.93 ITLBIMVA, Instruction TLB Invalidate entry by VA
- G4.2.94 JIDR, Jazelle ID Register
- G4.2.95 JMCR, Jazelle Main Configuration Register
- G4.2.96 JOSCR, Jazelle OS Control Register
- G4.2.97 MAIR0, Memory Attribute Indirection Register 0
- G4.2.98 MAIR1, Memory Attribute Indirection Register 1
- G4.2.99 MIDR, Main ID Register
- G4.2.100 MPIDR, Multiprocessor Affinity Register
- G4.2.101 MVBAR, Monitor Vector Base Address Register
- G4.2.102 MVFR0, Media and VFP Feature Register 0
- G4.2.103 MVFR1, Media and VFP Feature Register 1
- G4.2.104 MVFR2, Media and VFP Feature Register 2
- G4.2.105 NMRR, Normal Memory Remap Register
- G4.2.106 NSACR, Non-Secure Access Control Register
- G4.2.107 PAR, Physical Address Register
- G4.2.108 PRRR, Primary Region Remap Register
- G4.2.109 REVIDR, Revision ID Register
- G4.2.110 RMR (at EL1), Reset Management Register
- G4.2.111 RMR (at EL3), Reset Management Register
- G4.2.112 RVBAR, Reset Vector Base Address Register
- G4.2.113 SCR, Secure Configuration Register
- G4.2.114 SCTLR, System Control Register
- G4.2.115 SPSR, Saved Program Status Register
- G4.2.116 SPSR_abt, Saved Program Status Register (Abort mode)
- G4.2.117 SPSR_fiq, Saved Program Status Register (FIQ mode)
- G4.2.118 SPSR_hyp, Saved Program Status Register (Hyp mode)
- G4.2.119 SPSR_irq, Saved Program Status Register (IRQ mode)
- G4.2.120 SPSR_mon, Saved Program Status Register (Monitor mode)
- G4.2.121 SPSR_svc, Saved Program Status Register (Sup. Call mode)
- G4.2.122 SPSR_und, Saved Program Status Register (Undefined mode)
- G4.2.123 TCMTR, TCM Type Register
- G4.2.124 TEECR, T32EE Configuration Register
- G4.2.125 TEEHBR, T32EE Handler Base Register
- G4.2.126 TLBIALL, TLB Invalidate All entries
- G4.2.127 TLBIALLH, TLB Invalidate All entries, Hyp mode
- G4.2.128 TLBIALLHIS, TLB Invalidate All entries, Hyp mode, Inner Shareable
- G4.2.129 TLBIALLIS, TLB Invalidate All entries, Inner Shareable
- G4.2.130 TLBIALLNSNH, TLB Invalidate All entries, Non-Secure Non-Hyp
- G4.2.131 TLBIALLNSNHIS, TLB Invalidate All entries, Non-Secure Non-Hyp, Inner Shareable
- G4.2.132 TLBIASID, TLB Invalidate entry by ASID match
- G4.2.133 TLBIASIDIS, TLB Invalidate entry by ASID match, Inner Shareable
- G4.2.134 TLBIIPAS2, TLB Invalidate entry by Intermediate Physical Address, Stage 2
- G4.2.135 TLBIIPAS2IS, TLB Invalidate entry by Intermediate Physical Address, Stage 2, Inner Shareable
- G4.2.136 TLBIIPAS2L, TLB Invalidate entry by Intermediate Physical Address, Stage 2, Last level
- G4.2.137 TLBIIPAS2LIS, TLB Invalidate entry by Intermediate Physical Address, Stage 2, Last level, Inner Shareable
- G4.2.138 TLBIMVA, TLB Invalidate entry by VA
- G4.2.139 TLBIMVAA, TLB Invalidate entry by VA, All ASID
- G4.2.140 TLBIMVAAIS, TLB Invalidate entry by VA, All ASID, Inner Shareable
- G4.2.141 TLBIMVAAL, TLB Invalidate entry by VA, All ASID, Last level
- G4.2.142 TLBIMVAALIS, TLB Invalidate entry by VA, All ASID, Last level, Inner Shareable
- G4.2.143 TLBIMVAH, TLB Invalidate entry by VA, Hyp mode
- G4.2.144 TLBIMVAHIS, TLB Invalidate entry by VA, Hyp mode, Inner Shareable
- G4.2.145 TLBIMVAIS, TLB Invalidate entry by VA, Inner Shareable
- G4.2.146 TLBIMVAL, TLB Invalidate entry by VA, Last level
- G4.2.147 TLBIMVALH, TLB Invalidate entry by VA, Last level, Hyp mode
- G4.2.148 TLBIMVALHIS, TLB Invalidate entry by VA, Last level, Hyp mode, Inner Shareable
- G4.2.149 TLBIMVALIS, TLB Invalidate entry by VA, Last level, Inner Shareable
- G4.2.150 TLBTR, TLB Type Register
- G4.2.151 TPIDRPRW, Thread Pointer / ID Register, Privileged Read-Write
- G4.2.152 TPIDRURO, Thread Pointer / ID Register, Unprivileged Read-Only
- G4.2.153 TPIDRURW, Thread Pointer / ID Register, Unprivileged Read-Write
- G4.2.154 TTBCR, Translation Table Base Control Register
- G4.2.155 TTBR0, Translation Table Base Register 0
- G4.2.156 TTBR1, Translation Table Base Register 1
- G4.2.157 VBAR, Vector Base Address Register
- G4.2.158 VMPIDR, Virtualization Multiprocessor ID Register
- G4.2.159 VPIDR, Virtualization Processor ID Register
- G4.2.160 VTCR, Virtualization Translation Control Register
- G4.2.161 VTTBR, Virtualization Translation Table Base Register
- G4.3 Debug registers
- G4.3.1 DBGAUTHSTATUS, Debug Authentication Status register
- G4.3.2 DBGBCR<n>, Debug Breakpoint Control Registers, n = 0 - 15
- G4.3.3 DBGBVR<n>, Debug Breakpoint Value Registers, n = 0 - 15
- G4.3.4 DBGBXVR<n>, Debug Breakpoint Extended Value Registers, n = 0 - 15
- G4.3.5 DBGCLAIMCLR, Debug Claim Tag Clear register
- G4.3.6 DBGCLAIMSET, Debug Claim Tag Set register
- G4.3.7 DBGDCCINT, DCC Interrupt Enable Register
- G4.3.8 DBGDEVID, Debug Device ID register 0
- G4.3.9 DBGDEVID1, Debug Device ID register 1
- G4.3.10 DBGDEVID2, Debug Device ID register 2
- G4.3.11 DBGDIDR, Debug ID Register
- G4.3.12 DBGDRAR, Debug ROM Address Register
- G4.3.13 DBGDSAR, Debug Self Address Register
- G4.3.14 DBGDSCRext, Debug Status and Control Register, External View
- G4.3.15 DBGDSCRint, Debug Status and Control Register, Internal View
- G4.3.16 DBGDTRRXext, Debug Data Transfer Register, Receive, External View
- G4.3.17 DBGDTRRXint, Debug Data Transfer Register, Receive, Internal View
- G4.3.18 DBGDTRTXext, Debug Data Transfer Register, Transmit, External View
- G4.3.19 DBGDTRTXint, Debug Data Transfer Register, Transmit, Internal View
- G4.3.20 DBGOSDLR, Debug OS Double Lock Register
- G4.3.21 DBGOSECCR, Debug OS Lock Exception Catch Control Register
- G4.3.22 DBGOSLAR, Debug OS Lock Access Register
- G4.3.23 DBGOSLSR, Debug OS Lock Status Register
- G4.3.24 DBGPRCR, Debug Power Control Register
- G4.3.25 DBGVCR, Debug Vector Catch Register
- G4.3.26 DBGWCR<n>, Debug Watchpoint Control Registers, n = 0 - 15
- G4.3.27 DBGWFAR, Debug Watchpoint Fault Address Register
- G4.3.28 DBGWVR<n>, Debug Watchpoint Value Registers, n = 0 - 15
- G4.3.29 DLR, Debug Link Register
- G4.3.30 DSPSR, Debug Saved Program Status Register
- G4.3.31 HDCR, Hyp Debug Control Register
- G4.3.32 SDCR, Secure Debug Configuration Register
- G4.3.33 SDER, Secure Debug Enable Register
- G4.4 Performance Monitors registers
- G4.4.1 PMCCFILTR, Performance Monitors Cycle Count Filter Register
- G4.4.2 PMCCNTR, Performance Monitors Cycle Count Register
- G4.4.3 PMCEID0, Performance Monitors Common Event Identification register 0
- G4.4.4 PMCEID1, Performance Monitors Common Event Identification register 1
- G4.4.5 PMCNTENCLR, Performance Monitors Count Enable Clear register
- G4.4.6 PMCNTENSET, Performance Monitors Count Enable Set register
- G4.4.7 PMCR, Performance Monitors Control Register
- G4.4.8 PMEVCNTR<n>, Performance Monitors Event Count Registers, n = 0 - 30
- G4.4.9 PMEVTYPER<n>, Performance Monitors Event Type Registers, n = 0 - 30
- G4.4.10 PMINTENCLR, Performance Monitors Interrupt Enable Clear register
- G4.4.11 PMINTENSET, Performance Monitors Interrupt Enable Set register
- G4.4.12 PMOVSR, Performance Monitors Overflow Flag Status Register
- G4.4.13 PMOVSSET, Performance Monitors Overflow Flag Status Set register
- G4.4.14 PMSELR, Performance Monitors Event Counter Selection Register
- G4.4.15 PMSWINC, Performance Monitors Software Increment register
- G4.4.16 PMUSERENR, Performance Monitors User Enable Register
- G4.4.17 PMXEVCNTR, Performance Monitors Selected Event Count Register
- G4.4.18 PMXEVTYPER, Performance Monitors Selected Event Type Register
- G4.5 Generic Timer registers
- G4.5.1 CNTFRQ, Counter-timer Frequency register
- G4.5.2 CNTHCTL, Counter-timer Hyp Control register
- G4.5.3 CNTHP_CTL, Counter-timer Hyp Physical Timer Control register
- G4.5.4 CNTHP_CVAL, Counter-timer Hyp Physical CompareValue register
- G4.5.5 CNTHP_TVAL, Counter-timer Hyp Physical Timer TimerValue register
- G4.5.6 CNTKCTL, Counter-timer Kernel Control register
- G4.5.7 CNTP_CTL, Counter-timer Physical Timer Control register
- G4.5.8 CNTP_CVAL, Counter-timer Physical Timer CompareValue register
- G4.5.9 CNTP_TVAL, Counter-timer Physical Timer TimerValue register
- G4.5.10 CNTPCT, Counter-timer Physical Count register
- G4.5.11 CNTV_CTL, Counter-timer Virtual Timer Control register
- G4.5.12 CNTV_CVAL, Counter-timer Virtual Timer CompareValue register
- G4.5.13 CNTV_TVAL, Counter-timer Virtual Timer TimerValue register
- G4.5.14 CNTVCT, Counter-timer Virtual Count register
- G4.5.15 CNTVOFF, Counter-timer Virtual Offset register
- G4.6 Generic Interrupt Controller CPU interface registers
- G4.6.1 ICC_AP0R0, Interrupt Controller Active Priorities Register (0,0)
- G4.6.2 ICC_AP0R1, Interrupt Controller Active Priorities Register (0,1)
- G4.6.3 ICC_AP0R2, Interrupt Controller Active Priorities Register (0,2)
- G4.6.4 ICC_AP0R3, Interrupt Controller Active Priorities Register (0,3)
- G4.6.5 ICC_AP1R0, Interrupt Controller Active Priorities Register (1,0)
- G4.6.6 ICC_AP1R1, Interrupt Controller Active Priorities Register (1,1)
- G4.6.7 ICC_AP1R2, Interrupt Controller Active Priorities Register (1,2)
- G4.6.8 ICC_AP1R3, Interrupt Controller Active Priorities Register (1,3)
- G4.6.9 ICC_ASGI1R, Interrupt Controller Alias Software Generated Interrupt group 1 Register
- G4.6.10 ICC_BPR0, Interrupt Controller Binary Point Register 0
- G4.6.11 ICC_BPR1, Interrupt Controller Binary Point Register 1
- G4.6.12 ICC_CTLR, Interrupt Controller Control Register
- G4.6.13 ICC_DIR, Interrupt Controller Deactivate Interrupt Register
- G4.6.14 ICC_EOIR0, Interrupt Controller End Of Interrupt Register 0
- G4.6.15 ICC_EOIR1, Interrupt Controller End Of Interrupt Register 1
- G4.6.16 ICC_HPPIR0, Interrupt Controller Highest Priority Pending Interrupt Register 0
- G4.6.17 ICC_HPPIR1, Interrupt Controller Highest Priority Pending Interrupt Register 1
- G4.6.18 ICC_HSRE, Interrupt Controller Hyp System Register Enable register
- G4.6.19 ICC_IAR0, Interrupt Controller Interrupt Acknowledge Register 0
- G4.6.20 ICC_IAR1, Interrupt Controller Interrupt Acknowledge Register 1
- G4.6.21 ICC_IGRPEN0, Interrupt Controller Interrupt Group 0 Enable register
- G4.6.22 ICC_IGRPEN1, Interrupt Controller Interrupt Group 1 Enable register
- G4.6.23 ICC_MCTLR, Interrupt Controller Monitor Control Register
- G4.6.24 ICC_MGRPEN1, Interrupt Controller Monitor Interrupt Group 1 Enable register
- G4.6.25 ICC_MSRE, Interrupt Controller Monitor System Register Enable register
- G4.6.26 ICC_PMR, Interrupt Controller Interrupt Priority Mask Register
- G4.6.27 ICC_RPR, Interrupt Controller Running Priority Register
- G4.6.28 ICC_SEIEN, Interrupt Controller System Error Interrupt Enable register
- G4.6.29 ICC_SGI0R, Interrupt Controller Software Generated Interrupt group 0 Register
- G4.6.30 ICC_SGI1R, Interrupt Controller Software Generated Interrupt group 1 Register
- G4.6.31 ICC_SRE, Interrupt Controller System Register Enable register
- G4.6.32 ICH_AP0R0, Interrupt Controller Hyp Active Priorities Register (0,0)
- G4.6.33 ICH_AP0R1, Interrupt Controller Hyp Active Priorities Register (0,1)
- G4.6.34 ICH_AP0R2, Interrupt Controller Hyp Active Priorities Register (0,2)
- G4.6.35 ICH_AP0R3, Interrupt Controller Hyp Active Priorities Register (0,3)
- G4.6.36 ICH_AP1R0, Interrupt Controller Hyp Active Priorities Register (1,0)
- G4.6.37 ICH_AP1R1, Interrupt Controller Hyp Active Priorities Register (1,1)
- G4.6.38 ICH_AP1R2, Interrupt Controller Hyp Active Priorities Register (1,2)
- G4.6.39 ICH_AP1R3, Interrupt Controller Hyp Active Priorities Register (1,3)
- G4.6.40 ICH_EISR, Interrupt Controller End of Interrupt Status Register
- G4.6.41 ICH_ELSR, Interrupt Controller Empty List Register Status Register
- G4.6.42 ICH_HCR, Interrupt Controller Hyp Control Register
- G4.6.43 ICH_LRC<n>, Interrupt Controller List Registers, n = 0 - 15
- G4.6.44 ICH_LR<n>, Interrupt Controller List Registers, n = 0 - 15
- G4.6.45 ICH_MISR, Interrupt Controller Maintenance Interrupt State Register
- G4.6.46 ICH_VMCR, Interrupt Controller Virtual Machine Control Register
- G4.6.47 ICH_VSEIR, Interrupt Controller Virtual System Error Interrupt Register
- G4.6.48 ICH_VTR, Interrupt Controller VGIC Type Register
- Part H: External Debug
- H1: Introduction to External Debug
- H2: Debug State
- H2.1 About Debug state
- H2.2 Halting the PE on debug events
- H2.2.1 Halting allowed and halting prohibited
- H2.2.2 Halting debug events
- H2.2.3 Breakpoint and Watchpoint debug events
- H2.2.4 Other debug exceptions
- H2.2.5 Debug state entry and debug event prioritization
- H2.2.6 Forcing entry to Debug state
- H2.2.7 Summary of actions from debug events
- H2.2.8 Pseudocode details of Halting on debug events
- H2.3 Entering Debug state
- H2.4 Behavior in Debug state
- H2.4.1 Process state (PSTATE) in Debug state
- H2.4.2 Executing instructions in Debug state
- H2.4.3 Debug state unallocated decode tables
- H2.4.4 Instructions that debuggers might use in Debug state
- H2.4.5 Security in Debug state
- H2.4.6 Privilege in Debug state
- H2.4.7 Debug state instructions, DCPS, DRPS, MRS, MSR
- H2.4.8 Exceptions in Debug state
- H2.4.9 Accessing registers in Debug state
- H2.4.10 Accessing memory in Debug state
- H2.5 Exiting Debug state
- H3: Halting Debug Events
- H3.1 Introduction to Halting debug events
- H3.2 Halting Step debug event
- H3.2.1 Overview of a Halting Step debug event
- H3.2.2 The Halting Step state machine
- H3.2.3 Using Halting Step
- H3.2.4 Detailed Halting Step state machine behavior
- H3.2.5 Synchronization and the Halting Step state machine
- H3.2.6 Stepping T32 IT instructions
- H3.2.7 Disabling interrupts while stepping
- H3.2.8 Syndrome information on Halting Step
- H3.2.9 Pseudocode details for Halting Step debug events
- H3.3 Halt Instruction debug event
- H3.4 Exception Catch debug event
- H3.5 External Debug Request debug event
- H3.6 OS Unlock Catch debug event
- H3.7 Reset Catch debug event
- H3.8 Software Access debug event
- H3.9 Synchronization and Halting debug events
- H4: The Debug Communication Channel and Instruction Transfer Register
- H5: The Embedded Cross Trigger Interface
- H6: Debug Reset and Powerdown Support
- H7: The Sample-based Profiling Extension
- H7.1 Sample-based profiling
- H7.1.1 The implemented Sample-based profiling registers
- H7.1.2 Reads of the External Debug Program Counter Sampling Registers
- H7.1.3 Reads of the External Debug Virtual Context Sample Register
- H7.1.4 Accuracy of sampling
- H7.1.5 Sample-based Profiling and security
- H7.1.6 Pseudocode details of Sample-based Profiling
- H7.1 Sample-based profiling
- H8: About the External Debug Registers
- H8.1 Relationship between external debug and System registers
- H8.2 Supported access sizes
- H8.3 Synchronization of changes to the external debug registers
- H8.4 Memory-mapped accesses to the external debug interface
- H8.5 External debug interface register access permissions
- H8.5.1 External debug over powerdown and locks
- H8.5.2 External access disabled
- H8.5.3 Behavior of a not permitted access
- H8.5.4 Trapping software access to debug registers
- H8.5.5 External debug interface register access permissions summary
- H8.5.6 implementation defined registers
- H8.5.7 optional CoreSight management registers
- H8.5.8 Reserved and unallocated registers
- H8.6 External debug interface registers
- H8.7 Cross-trigger interface registers
- H8.8 Reset and debug
- H8.9 External debug register resets
- H9: External Debug Register Descriptions
- H9.1 Introduction
- H9.2 Debug registers
- H9.2.1 DBGAUTHSTATUS_EL1, Debug Authentication Status register
- H9.2.2 DBGBCR<n>_EL1, Debug Breakpoint Control Registers, n = 0 - 15
- H9.2.3 DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 - 15
- H9.2.4 DBGCLAIMCLR_EL1, Debug Claim Tag Clear register
- H9.2.5 DBGCLAIMSET_EL1, Debug Claim Tag Set register
- H9.2.6 DBGDTRRX_EL0, Debug Data Transfer Register, Receive
- H9.2.7 DBGDTRTX_EL0, Debug Data Transfer Register, Transmit
- H9.2.8 DBGWCR<n>_EL1, Debug Watchpoint Control Registers, n = 0 - 15
- H9.2.9 DBGWVR<n>_EL1, Debug Watchpoint Value Registers, n = 0 - 15
- H9.2.10 EDACR, External Debug Auxiliary Control Register
- H9.2.11 EDCIDR0, External Debug Component Identification Register 0
- H9.2.12 EDCIDR1, External Debug Component Identification Register 1
- H9.2.13 EDCIDR2, External Debug Component Identification Register 2
- H9.2.14 EDCIDR3, External Debug Component Identification Register 3
- H9.2.15 EDCIDSR, External Debug Context ID Sample Register
- H9.2.16 EDDEVAFF0, External Debug Device Affinity register 0
- H9.2.17 EDDEVAFF1, External Debug Device Affinity register 1
- H9.2.18 EDDEVARCH, External Debug Device Architecture register
- H9.2.19 EDDEVID, External Debug Device ID register 0
- H9.2.20 EDDEVID1, External Debug Device ID register 1
- H9.2.21 EDDEVID2, External Debug Device ID register 2
- H9.2.22 EDDEVTYPE, External Debug Device Type register
- H9.2.23 EDECCR, External Debug Exception Catch Control Register
- H9.2.24 EDECR, External Debug Execution Control Register
- H9.2.25 EDESR, External Debug Event Status Register
- H9.2.26 EDITCTRL, External Debug Integration mode Control register
- H9.2.27 EDITR, External Debug Instruction Transfer Register
- H9.2.28 EDLAR, External Debug Lock Access Register
- H9.2.29 EDLSR, External Debug Lock Status Register
- H9.2.30 EDPCSR, External Debug Program Counter Sample Register
- H9.2.31 EDPIDR0, External Debug Peripheral Identification Register 0
- H9.2.32 EDPIDR1, External Debug Peripheral Identification Register 1
- H9.2.33 EDPIDR2, External Debug Peripheral Identification Register 2
- H9.2.34 EDPIDR3, External Debug Peripheral Identification Register 3
- H9.2.35 EDPIDR4, External Debug Peripheral Identification Register 4
- H9.2.36 EDPRCR, External Debug Power/Reset Control Register
- H9.2.37 EDPRSR, External Debug Processor Status Register
- H9.2.38 EDRCR, External Debug Reserve Control Register
- H9.2.39 EDSCR, External Debug Status and Control Register
- H9.2.40 EDVIDSR, External Debug Virtual Context Sample Register
- H9.2.41 EDWAR, External Debug Watchpoint Address Register
- H9.2.42 ID_AA64DFR0_EL1, Debug Feature Register 0
- H9.2.43 ID_AA64DFR1_EL1, Debug Feature Register 1
- H9.2.44 ID_AA64ISAR0_EL1, Instruction Set Attribute Register 0
- H9.2.45 ID_AA64ISAR1_EL1, Instruction Set Attribute Register 1
- H9.2.46 ID_AA64MMFR0_EL1, Memory Model Feature Register 0
- H9.2.47 ID_AA64MMFR1_EL1, Memory Model Feature Register 1
- H9.2.48 ID_AA64PFR0_EL1, Processor Feature Register 0
- H9.2.49 ID_AA64PFR1_EL1, Processor Feature Register 1
- H9.2.50 MIDR_EL1, Main ID Register
- H9.2.51 OSLAR_EL1, OS Lock Access Register
- H9.3 Cross-Trigger Interface registers
- H9.3.1 ASICCTL, CTI External Multiplexer Control register
- H9.3.2 CTIAPPCLEAR, CTI Application Trigger Clear register
- H9.3.3 CTIAPPPULSE, CTI Application Pulse register
- H9.3.4 CTIAPPSET, CTI Application Trigger Set register
- H9.3.5 CTIAUTHSTATUS, CTI Authentication Status register
- H9.3.6 CTICHINSTATUS, CTI Channel In Status register
- H9.3.7 CTICHOUTSTATUS, CTI Channel Out Status register
- H9.3.8 CTICIDR0, CTI Component Identification Register 0
- H9.3.9 CTICIDR1, CTI Component Identification Register 1
- H9.3.10 CTICIDR2, CTI Component Identification Register 2
- H9.3.11 CTICIDR3, CTI Component Identification Register 3
- H9.3.12 CTICLAIMCLR, CTI Claim Tag Clear register
- H9.3.13 CTICLAIMSET, CTI Claim Tag Set register
- H9.3.14 CTICONTROL, CTI Control register
- H9.3.15 CTIDEVAFF0, CTI Device Affinity register 0
- H9.3.16 CTIDEVAFF1, CTI Device Affinity register 1
- H9.3.17 CTIDEVARCH, CTI Device Architecture register
- H9.3.18 CTIDEVID, CTI Device ID register 0
- H9.3.19 CTIDEVID1, CTI Device ID register 1
- H9.3.20 CTIDEVID2, CTI Device ID register 2
- H9.3.21 CTIDEVTYPE, CTI Device Type register
- H9.3.22 CTIGATE, CTI Channel Gate Enable register
- H9.3.23 CTIINEN<n>, CTI Input Trigger to Output Channel Enable registers, n = 0 - 31
- H9.3.24 CTIINTACK, CTI Output Trigger Acknowledge register
- H9.3.25 CTIITCTRL, CTI Integration mode Control register
- H9.3.26 CTILAR, CTI Lock Access Register
- H9.3.27 CTILSR, CTI Lock Status Register
- H9.3.28 CTIOUTEN<n>, CTI Input Channel to Output Trigger Enable registers, n = 0 - 31
- H9.3.29 CTIPIDR0, CTI Peripheral Identification Register 0
- H9.3.30 CTIPIDR1, CTI Peripheral Identification Register 1
- H9.3.31 CTIPIDR2, CTI Peripheral Identification Register 2
- H9.3.32 CTIPIDR3, CTI Peripheral Identification Register 3
- H9.3.33 CTIPIDR4, CTI Peripheral Identification Register 4
- H9.3.34 CTITRIGINSTATUS, CTI Trigger In Status register
- H9.3.35 CTITRIGOUTSTATUS, CTI Trigger Out Status register
- Part I: Memory-mapped Components of the ARMv8 Architecture
- I1: Memory-Mapped System Register Descriptions
- I1.1 Introduction
- I1.2 Performance Monitors registers
- I1.2.1 PMAUTHSTATUS, Performance Monitors Authentication Status register
- I1.2.2 PMCCFILTR_EL0, Performance Monitors Cycle Counter Filter Register
- I1.2.3 PMCCNTR_EL0, Performance Monitors Cycle Counter
- I1.2.4 PMCEID0_EL0, Performance Monitors Common Event Identification register 0
- I1.2.5 PMCEID1_EL0, Performance Monitors Common Event Identification register 1
- I1.2.6 PMCFGR, Performance Monitors Configuration Register
- I1.2.7 PMCIDR0, Performance Monitors Component Identification Register 0
- I1.2.8 PMCIDR1, Performance Monitors Component Identification Register 1
- I1.2.9 PMCIDR2, Performance Monitors Component Identification Register 2
- I1.2.10 PMCIDR3, Performance Monitors Component Identification Register 3
- I1.2.11 PMCNTENCLR_EL0, Performance Monitors Count Enable Clear register
- I1.2.12 PMCNTENSET_EL0, Performance Monitors Count Enable Set register
- I1.2.13 PMCR_EL0, Performance Monitors Control Register
- I1.2.14 PMDEVAFF0, Performance Monitors Device Affinity register 0
- I1.2.15 PMDEVAFF1, Performance Monitors Device Affinity register 1
- I1.2.16 PMDEVARCH, Performance Monitors Device Architecture register
- I1.2.17 PMDEVTYPE, Performance Monitors Device Type register
- I1.2.18 PMEVCNTR<n>_EL0, Performance Monitors Event Count Registers, n = 0 - 30
- I1.2.19 PMEVTYPER<n>_EL0, Performance Monitors Event Type Registers, n = 0 - 30
- I1.2.20 PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear register
- I1.2.21 PMINTENSET_EL1, Performance Monitors Interrupt Enable Set register
- I1.2.22 PMITCTRL, Performance Monitors Integration mode Control register
- I1.2.23 PMLAR, Performance Monitors Lock Access Register
- I1.2.24 PMLSR, Performance Monitors Lock Status Register
- I1.2.25 PMOVSCLR_EL0, Performance Monitors Overflow Flag Status Clear register
- I1.2.26 PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set register
- I1.2.27 PMPIDR0, Performance Monitors Peripheral Identification Register 0
- I1.2.28 PMPIDR1, Performance Monitors Peripheral Identification Register 1
- I1.2.29 PMPIDR2, Performance Monitors Peripheral Identification Register 2
- I1.2.30 PMPIDR3, Performance Monitors Peripheral Identification Register 3
- I1.2.31 PMPIDR4, Performance Monitors Peripheral Identification Register 4
- I1.2.32 PMSWINC_EL0, Performance Monitors Software Increment register
- I1.3 Generic Timer registers
- I1.3.1 CNTACR<n>, Counter-timer Access Control Registers, n = 0 - 7
- I1.3.2 CNTCR, Counter Control Register
- I1.3.3 CNTCV, Counter Count Value register
- I1.3.4 CNTEL0ACR, Counter-timer EL0 Access Control Register
- I1.3.5 CNTFID0, Counter Frequency ID
- I1.3.6 CNTFID<n>, Counter Frequency IDs, n = 1 - 23
- I1.3.7 CNTFRQ, Counter-timer Frequency
- I1.3.8 CNTNSAR, Counter-timer Non-secure Access Register
- I1.3.9 CNTP_CTL, Counter-timer Physical Timer Control
- I1.3.10 CNTP_CVAL, Counter-timer Physical Timer CompareValue
- I1.3.11 CNTP_TVAL, Counter-timer Physical Timer TimerValue
- I1.3.12 CNTPCT, Counter-timer Physical Count
- I1.3.13 CNTSR, Counter Status Register
- I1.3.14 CNTTIDR, Counter-timer Timer ID Register
- I1.3.15 CNTV_CTL, Counter-timer Virtual Timer Control
- I1.3.16 CNTV_CVAL, Counter-timer Virtual Timer CompareValue
- I1.3.17 CNTV_TVAL, Counter-timer Virtual Timer TimerValue
- I1.3.18 CNTVCT, Counter-timer Virtual Count
- I1.3.19 CNTVOFF, Counter-timer Virtual Offset
- I1.3.20 CNTVOFF<n>, Counter-timer Virtual Offsets, n = 0 - 7
- I1.3.21 CounterID<n>, Counter ID registers, n = 0 - 11
- I2: System Level Implementation of the Generic Timer
- I2.1 About the Generic Timer specification
- I2.2 Memory-mapped counter module
- I2.3 Counter module control and status register summary
- I2.4 About the memory-mapped view of the counter and timer
- I2.5 The CNTBaseN and CNTPL0BaseN frames
- I2.6 The CNTCTLBase frame
- I2.7 Providing a complete set of counter and timer features
- I2.8 Gray-count scheme for timer distribution scheme
- I3: Recommended Memory-mapped Interfaces to the Performance Monitors
- I3.1 About the memory-mapped views of the Performance Monitors registers
- I3.1.1 Differences in the memory-mapped views of the Performance Monitors registers
- I3.1.2 Synchronization of changes to the memory-mapped views
- I3.1.3 Performance Monitors memory-mapped register views
- I3.1.4 Access permissions for memory-mapped views of the Performance Monitors
- I3.1.5 Power domains and Performance Monitors registers reset
- I3.1 About the memory-mapped views of the Performance Monitors registers
- Part J: Appendixes
- A: Architectural Constraints on UNPREDICTABLE behaviors
- A.1 AArch32 CONSTRAINED UNPREDICTABLE behaviors
- A.1.1 Overview of the constraints on ARMv7 UNPREDICTABLE behaviors
- A.1.2 CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instructions
- BFC
- BFI
- BKPT
- CLZ
- CMP (register)
- CRC32, CRC32C
- HLT
- IT
- LDC/LDC2 (literal)
- LDM/LDMIA/LDMFD (T32)
- LDM/LDMIA/LDMFD (A32)
- LDMDA/LDMFA
- LDMIB/LDMED
- LDMDB/LDMEA
- LDR (immediate, T32)
- LDR (immediate, A32)
- LDR (register, A32)
- LDRB (immediate, T32)
- LDRB (immediate, A32)
- LDRB (register)
- LDRBT
- LDRH (immediate, T32)
- LDRH (immediate, A32)
- LDRH (register)
- LDRHT
- LDRSB (immediate)
- LDRSB (register)
- LDRSBT
- LDRSH (immediate)
- LDRSH (register)
- LDRSHT
- LDRT
- LDR (literal)
- LDRB (literal)
- LDRH (literal)
- LDRSB (literal)
- LDRSH (literal)
- LDRD (immediate)
- LDRD (register)
- LDRD (literal)
- LDREX
- LDREXH
- LDREXB
- LDAEX
- LDAEXH
- LDAEXB
- LDREXD
- LDAEXD
- MOV (register, T32)
- MRRC, MRRC2
- MSR (register)
- POP (T32)
- POP (A32)
- PUSH
- RBIT
- REV
- REV16
- REVSH
- SBFX
- UBFX
- SDIV
- UDIV
- SMULL
- SMLAL
- SMLALBB, SMLALBT, SMLALTB, SMLALTT
- SMLALD
- SMLSLD
- UMULL
- UMAAL
- UMLAL
- STC, STC2
- STM (STMIA, STMEA)
- STMDA (STMED)
- STMIB (STMFA)
- STMDB (STMFD)
- STR (immediate, T32)
- STR (immediate, A32)
- STR (register)
- STRB (immediate, T32)
- STRB (immediate, A32)
- STRB (register)
- STRBT
- STRH (immediate, T32)
- STRH (immediate, A32)
- STRH (register)
- STRHT
- STRT
- STRD (immediate)
- STRD (register)
- STREX
- STREXB
- STREXD
- STREXH
- STLEX
- STLEXB
- STLEXD
- STLEXH
- VCVT (between floating-point and fixed-point)
- VLD1 (multiple single elements)
- VLD1 (single element to all lanes)
- VLD2 (multiple 2-element structures)
- VLD2 (single 2-element structure to one lane)
- VLD2 (single 2-element structure to all lanes)
- VLD3 (multiple 3-element structures)
- VLD3 (single 3-element structure to one lane)
- VLD3 (single 3-element structure to all lanes)
- VLD4 (multiple 4-element structures)
- VLD4 (single 4-element structure to one lane)
- VLD4 (single 4-element structure to all lanes)
- VLDM
- VPOP
- VMOV (between two general-purpose registers and two single-precision registers)
- VMOV (between two general-purpose registers and a doubleword extension register)
- VST1 (multiple single elements)
- VST2 (multiple 2-element structures)
- VST2 (single 2-element structure from one lane)
- VST3 (multiple 3-element structures)
- VST3 (single 3-element structure from one lane)
- VST4 (multiple 4-element structures)
- VST4 (single 4-element structure from one lane)
- VSTM
- VPUSH
- VTBL, VTBX
- A.1.3 CONSTRAINED UNPREDICTABLE behavior, A32 and T32 system instructions
- A.1.4 CONSTRAINED UNPREDICTABLE behavior in Debug state
- A.1.5 Using R13
- A.1.6 Using R15
- A.1.7 SBZ or SBO fields in instructions
- A.1.8 CONSTRAINED UNPREDICTABLE behavior in an IT block
- A.1.9 Branching into an IT block
- A.1.10 Syndrome register handling for CONSTRAINED UNPREDICTABLE instructions treated as UNDEFINED
- A.1.11 Unallocated values in register fields of CP14 and CP 15 registers and translation table entries
- A.1.12 Unallocated CP14 and CP15 instructions
- A.1.13 Loads and Stores to unaligned locations
- A.1.14 Branching to an unaligned PC
- A.1.15 Unpredictable CPACR and NSACR settings
- A.1.16 Instruction fetches from Device memory
- A.1.17 Multi-access instructions that load the PC from Device memory
- A.1.18 Out of range virtual address
- A.1.19 Translation Table Base Address alignment
- A.2 Constraints on AArch64 state UNPREDICTABLE behaviors
- A.1 AArch32 CONSTRAINED UNPREDICTABLE behaviors
- B: Recommended External Debug Interface
- B.1 About the recommended external debug interface
- B.2 PMUEVENT bus
- B.3 DBGCPUDONE
- B.4 Recommended authentication interface
- B.4.1 Pseudocode details for AArch32 Self-Hosted Secure Privileged Invasive Debug Enabled
- B.4.2 Pseudocode details for External Invasive Debug Enabled
- B.4.3 Pseudocode details for External Secure Invasive Debug Enabled
- B.4.4 Pseudocode details for External Non-invasive Debug Enabled
- B.4.5 Pseudocode details for External Secure Non-invasive Debug Enabled
- B.5 Management registers and CoreSight compliance
- C: Recommendations for Performance Monitors Event Numbers for IMPLEMENTATION DEFINED Events
- D: Example OS Save and Restore sequences
- E: Additional Guidance
- F: Barrier Litmus Tests
- F.1 Introduction
- F.2 Load-Acquire, Store-Release and barriers
- F.3 Load-Acquire Exclusive, Store-Release Exclusive and barriers
- F.4 Using a mailbox to send an interrupt
- F.5 Cache and TLB maintenance operations and barriers
- F.6 ARMv7 compatible approaches for ordering, using DMB and DSB barriers
- G: ARMv8 Pseudocode Library
- G.1 Library pseudocode for AArch64
- G.1.1 aarch64/debug
- G.1.2 aarch64/exceptions
- G.1.3 aarch64/functions
- G.1.4 aarch64/instrs
- aarch64/instrs/branch/eret
- aarch64/instrs/countop
- aarch64/instrs/extendreg
- aarch64/instrs/float/arithmetic/max-min/fpmaxminop
- aarch64/instrs/float/arithmetic/unary/fpunaryop
- aarch64/instrs/float/convert/fpconvop
- aarch64/instrs/integer/arithmetic/rev/revop
- aarch64/instrs/integer/bitfield/bfxpreferred
- aarch64/instrs/integer/bitmasks
- aarch64/instrs/integer/ins-ext/insert/movewide/movewideop
- aarch64/instrs/integer/logical/movwpreferred
- aarch64/instrs/integer/shiftreg
- aarch64/instrs/logicalop
- aarch64/instrs/memory/memop
- aarch64/instrs/memory/prefetch
- aarch64/instrs/system/barriers/barrierop
- aarch64/instrs/system/hints/syshintop
- aarch64/instrs/system/register/cpsr/pstatefield
- aarch64/instrs/system/sysops/sysop
- aarch64/instrs/vector/arithmetic/binary/uniform/logical/bsl-eor/vbitop
- aarch64/instrs/vector/arithmetic/unary/cmp/compareop
- aarch64/instrs/vector/crypto/enabled
- aarch64/instrs/vector/logical/immediateop
- aarch64/instrs/vector/reduce/reduceop
- G.1.5 aarch64/translation
- G.2 Library pseudocode for AArch32
- G.3 Common library pseudocode
- G.3.1 shared/debug
- shared/debug/CONTEXTIDR_GEN
- shared/debug/ClearStickyErrors
- shared/debug/DebugTarget
- shared/debug/DoubleLockStatus
- shared/debug/FindWatchpoint
- shared/debug/authentication
- shared/debug/cti
- shared/debug/dccanditr
- shared/debug/halting
- shared/debug/haltingevents
- shared/debug/interrupts
- shared/debug/pmu
- shared/debug/samplebasedprofiling
- shared/debug/softwarestep
- G.3.2 shared/exceptions
- G.3.3 shared/functions
- shared/functions/aborts
- shared/functions/common
- shared/functions/crc
- shared/functions/crypto
- shared/functions/exclusive
- shared/functions/float
- shared/functions/gray
- shared/functions/integer
- shared/functions/memory
- shared/functions/registers
- shared/functions/sysregisters
- shared/functions/system
- shared/functions/unpredictable
- shared/functions/vector
- G.3.4 shared/translation
- G.3.1 shared/debug
- G.1 Library pseudocode for AArch64
- H: ARM Pseudocode Definition
- H.1 About the ARM pseudocode
- H.2 Pseudocode for instruction descriptions
- H.3 Data types
- H.4 Expressions
- H.5 Operators and built-in functions
- H.5.1 Operations on generic types
- H.5.2 Operations on Booleans
- H.5.3 Bitstring manipulation
- Bitstring length and most significant bit
- Bitstring concatenation and replication
- Bitstring extraction
- Logical operations on bitstrings
- Bitstring count
- Testing a bitstring for being all zero or all ones
- Lowest and highest set bits of a bitstring
- Zero-extension and sign-extension of bitstrings
- Converting bitstrings to integers
- H.5.4 Arithmetic
- H.6 Statements and program structure
- H.7 Miscellaneous helper procedures and functions
- H.7.1 ArchVersion()
- H.7.2 EndOfInstruction()
- H.7.3 GenerateAlignmentException()
- H.7.4 GenerateCoprocessorException()
- H.7.5 Hint_Debug()
- H.7.6 Hint_PreloadData()
- H.7.7 Hint_PreloadDataForWrite()
- H.7.8 Hint_PreloadInstr()
- H.7.9 Hint_Yield()
- H.7.10 IntegerZeroDivideTrappingEnabled()
- H.7.11 IsExternalAbort()
- H.7.12 IsAsyncAbort()
- H.7.13 JazelleAcceptsExecution()
- H.7.14 LSInstructionSyndrome()
- H.7.15 ProcessorID()
- H.7.16 RemapRegsHaveResetValues()
- H.7.17 ThisInstr()
- H.7.18 ThisInstrLength()
- I: Pseudocode Index
- J: Registers Index
- J.1 Introduction and register disambiguation
- J.2 Alphabetical index of AArch64 registers and system instructions
- J.3 Functional index of AArch64 registers and system instructions
- J.3.1 Special-purpose registers
- J.3.2 VMSA-specific registers
- J.3.3 ID registers
- J.3.4 Performance monitors registers
- J.3.5 Debug registers
- J.3.6 Generic timer registers
- J.3.7 Generic Interrupt Controller CPU interface registers
- J.3.8 Cache maintenance system instructions
- J.3.9 Address translation system instructions
- J.3.10 TLB maintenance system instructions
- J.3.11 Base system registers
- J.4 Alphabetical index of AArch32 registers and system instructions
- J.5 Functional index of AArch32 registers and system instructions
- J.5.1 Special-purpose registers
- J.5.2 VMSA-specific registers
- J.5.3 ID registers
- J.5.4 Performance monitors registers
- J.5.5 Debug registers
- J.5.6 Generic timer registers
- J.5.7 Generic Interrupt Controller CPU interface registers
- J.5.8 Cache maintenance system instructions
- J.5.9 Address translation system instructions
- J.5.10 TLB maintenance system instructions
- J.5.11 Legacy feature registers and system instructions
- J.5.12 Base system registers
- J.6 Alphabetical index of memory-mapped registers
- J.7 Functional index of memory-mapped registers
- Glossary