AD5304/AD5314/AD5324 (Rev. I) 5314 AD5304 5324
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2.5 V to 5.5 V, 500 μA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead Packages AD5304/AD5314/AD5324 Data Sheet FEATURES GENERAL DESCRIPTION AD5304: 4 buffered 8-Bit DACs in 10-lead MSOP and 10-lead LFCSP A, W Version: ±1 LSB INL, B Version: ±0.625 LSB INL AD5314: 4 buffered 10-Bit DACs in 10-lead MSOP and 10-lead LFCSP A, W Version: ±4 LSB INL, B Version: ±2.5 LSB INL AD5324: 4 buffered 12-Bit DACs in 10-lead MSOP and 10-lead LFCSP A, W Version: ±16 LSB INL, B Version: ±10 LSB INL Low power operation: 500 μA @ 3 V, 600 μA @ 5 V 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes Power-down to 80 nA @ 3 V, 200 nA @ 5 V Double-buffered input logic Output range: 0 V to VREF Power-on reset to 0 V Simultaneous update of outputs (LDAC function) Low power-, SPI®-, QSPI™-, MICROWIRE™-, and DSPcompatible 3-wire serial interface On-chip, rail-to-rail output buffer amplifiers Temperature range −40°C to +105°C Qualified for automotive applications The AD5304/AD5314/AD53241 are quad 8-, 10-, and 12-bit buffered voltage output DACs in 10-lead MSOP and 10-lead LFCSP packages that operate from a single 2.5 V to 5.5 V supply, consuming 500 μA at 3 V. Their on-chip output amplifiers allow rail-to-rail output swing to be achieved with a slew rate of 0.7 V/μs. A 3-wire serial interface is used; it operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards. The references for the four DACs are derived from one reference pin. The outputs of all DACs can be updated simultaneously using the software LDAC function. The parts incorporate a power-on reset circuit, and ensure that the DAC outputs power up to 0 V and remains there until a valid write takes place to the device. The parts contain a power-down feature that reduces the current consumption of the device to 200 nA @ 5 V (80 nA @ 3 V). The low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing to 1 μW in power-down mode. APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process controls 1 Protected by U.S. Patent No. 5,969,657. FUNCTIONAL BLOCK DIAGRAM VDD AD5304/AD5314/AD5324 REFIN LDAC BUFFER INPUT REGISTER DAC REGISTER STRING DAC A INPUT REGISTER DAC REGISTER STRING DAC B INPUT REGISTER DAC REGISTER STRING DAC C INPUT REGISTER DAC REGISTER STRING DAC D VOUTA BUFFER SYNC INTERFACE LOGIC SCLK VOUTB BUFFER DIN VOUTC BUFFER POWER-DOWN LOGIC GND 00929-001 POWER-ON RESET VOUTD Figure 1. Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5304/AD5314/AD5324 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 14 Applications ....................................................................................... 1 Functional Description .............................................................. 14 General Description ......................................................................... 1 Power-On Reset .......................................................................... 14 Functional Block Diagram .............................................................. 1 Serial Interface ............................................................................ 14 Revision History ............................................................................... 2 Power-Down Mode .................................................................... 16 Specifications..................................................................................... 3 Microprocessor Interfacing ....................................................... 16 AC Characteristics ........................................................................ 4 Applications Information .............................................................. 18 Timing Characteristics ................................................................ 5 Typical Application Circuit ....................................................... 18 Absolute Maximum Ratings ............................................................ 6 Decoding Multiple AD5304/AD5314/AD5324s .................... 19 ESD Caution .................................................................................. 6 Power Supply Bypassing and Grounding ................................ 20 Pin Configurations and Function Descriptions ........................... 7 Outline Dimensions ....................................................................... 22 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 23 Terminology .................................................................................... 12 Automotive Products ................................................................. 23 REVISION HISTORY 5/2017—Rev. H to Rev. I Changes to Figure 4 .......................................................................... 7 Changes to Address and Control Bits Section ............................ 15 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 23 9/2011—Rev. G to Rev. H Changes to Table 4 ............................................................................ 6 5/2011—Rev. F to Rev. G Added W Version ............................................................... Universal Added EPAD Notation to Figure 4................................................. 7 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 23 Added Automotive Products Section........................................... 23 5/2005—Rev. D to Rev. E Added 10-lead LFCSP package ......................................... Universal Changes to Title .................................................................................1 Changes to Ordering Guide .............................................................4 8/2003—Rev. C to Rev. D Added A Version ................................................................ Universal Changes to Features ..........................................................................1 Changes to Specifications .................................................................2 Changes to Absolute Maximum Ratings ........................................4 Changes to Ordering Guide .............................................................4 Changes to Figure 6 ........................................................................ 11 Added OCTALS Section to Table 2.............................................. 15 Updated Outline Dimensions ....................................................... 16 9/2006—Rev. E to Rev. F Updated Format .................................................................. Universal Changes to Specifications Section .................................................. 3 Changes to Table 5 ............................................................................ 7 Updated Outline Dimensions ...................................................... 22 Changes to Ordering Guide .......................................................... 23 Rev. I | Page 2 of 24 Data Sheet AD5304/AD5314/AD5324 SPECIFICATIONS VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter DC PERFORMANCE 3, 4 AD5304 Resolution Relative Accuracy Differential Nonlinearity 1 A, W Version 2 Min Typ Max Min B Version2 Typ Max Unit 8 ±0.15 ±0.02 ±1 ±0.25 8 ±0.15 ±0.02 ±0.625 ±0.25 Bits LSB LSB AD5314 Resolution Relative Accuracy Differential Nonlinearity 10 ±0.5 ±0.05 ±4 ±0.5 10 ±0.5 ±0.05 ±2.5 ±0.5 Bits LSB LSB AD5324 Resolution Relative Accuracy Differential Nonlinearity 12 ±2 ±0.2 ±16 ±1 12 ±2 ±0.2 ±10 ±1 Bits LSB LSB Offset Error Gain Error Lower Dead Band ±0.4 ±0.15 20 ±3 ±1 60 ±0.4 ±0.15 20 ±3 ±1 60 % of FSR % of FSR mV Offset Error Drift 5 –12 –12 Gain Error Drift5 –5 –5 –60 200 Test Conditions/Comments Guaranteed monotonic by design over all codes Guaranteed monotonic by design over all codes Guaranteed monotonic by design over all codes See Figure 2 and Figure 3 See Figure 2 and Figure 3 Lower dead band exists only if offset error is negative –60 ppm of FSR/°C ppm of FSR/°C dB ΔVDD = ±10% 200 µV RL = 2 kΩ to GND or VDD 45 >10 –90 V kΩ MΩ dB Normal operation Power-down mode Frequency = 10 kHz 0.001 0.001 V Maximum Output Voltage6 VDD – 0.001 VDD – 0.001 DC Output Impedance Short Circuit Current 0.5 25 16 2.5 0.5 25 16 2.5 Ω mA mA µs 5 5 µs DC Power Supply Rejection Ratio5 DC Crosstalk5 DAC REFERENCE INPUTS5 VREF Input Range VREF Input Impedance Reference Feedthrough OUTPUT CHARACTERISTICS5 Minimum Output Voltage 6 Power-Up Time 0.25 37 VDD 45 >10 –90 0.25 37 VDD Rev. I | Page 3 of 24 Measurement of the minimum and maximum V drive capability of the output amplifier VDD = 5 V VDD = 3 V Coming out of powerdown mode VDD = 5 V Coming out of powerdown mode VDD = 3 V AD5304/AD5314/AD5324 Parameter LOGIC INPUTS5 Input Current VIL, Input Low Voltage 1 VIH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 7 VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V Data Sheet A, W Version 2 Min Typ Max Min B Version2 Typ Max ±1 0.8 0.6 0.5 2.4 2.1 2.0 Unit Test Conditions/Comments ±1 0.8 0.6 0.5 µA V V V V V V pF VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V 5.5 V 2.4 2.1 2.0 3 2.5 3 5.5 2.5 600 500 900 700 600 500 900 700 µA µA VIH = VDD and VIL = GND VIH = VDD and VIL = GND 0.2 0.08 1 1 0.2 0.08 1 1 µA µA VIH = VDD and VIL = GND VIH = VDD and VIL = GND See the Terminology section. Temperature range (A, B, W Version): −40°C to +105°C; typical at +25°C. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5304 (Code 8 to Code 248); AD5314 (Code 28 to Code 995); AD5324 (Code 115 to Code 3981). 5 Guaranteed by design and characterization, not production tested. 6 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. 7 IDD specification is valid for all DAC codes; interface inactive; all DACs active; load currents excluded. 1 2 AC CHARACTERISTICS VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1, 2 Output Voltage Settling Time AD5304 AD5314 AD5324 Slew Rate Major-Code Transition Glitch Energy Digital Feedthrough Digital Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion 1 2 3 A, B, W Version 3 Min Typ Max 6 7 8 0.7 12 1 1 3 200 –70 8 9 10 Unit µs µs µs V/µs nV-sec nV-sec nV-sec nV-sec kHz dB See the Terminology section. Guaranteed by design and characterization, not production tested. Temperature range (A, B, W Version): −40°C to +105°C; typical at +25°C. Rev. I | Page 4 of 24 Test Conditions/Comments VREF = VDD = 5 V ¼ scale to ¾ scale change (0x40 to 0xC0) ¼ scale to ¾ scale change (0x100 to 0x300) ¼ scale to ¾ scale change (0x400 to 0xC00) 1 LSB change around major carry VREF = 2 V ± 0.1 V p-p VREF = 2.5 V ± 0.1 V p-p; frequency = 10 kHz Data Sheet AD5304/AD5314/AD5324 TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 Limit at TMIN, TMAX VDD = 2.5 V to 3.6 V VDD = 3.6 V to 5.5 V 40 33 16 13 16 13 16 13 5 5 4.5 4.5 0 0 80 33 Unit ns min ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time 1 Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90 % of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 2. 2 t1 SCLK t8 t3 t4 t2 t7 SYNC DIN DB15 t5 DB0 Figure 2. Serial Interface Timing Diagram Rev. I | Page 5 of 24 00929-002 t6 AD5304/AD5314/AD5324 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter1 VDD to GND Digital Input Voltage to GND Reference Input Voltage to GND VOUTA through VOUTD to GND Operating Temperature Range Industrial (A, B, W Version) Storage Temperature Range Junction Temperature (TJ max) 10-Lead MSOP Power Dissipation θJA Thermal Impedance θJC Thermal Impedance 10-Lead LFCSP Power Dissipation θJA Thermal Impedance Reflow Soldering Peak Temperature (Pb-free) Peak Temperature (non Pb-free) Time at Peak Temperature 1 Rating –0.3 V to +7 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.3 V –40°C to +105°C –65°C to +150°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION (TJ max – TA)/ θJA 206°C/W 44°C/W (TJ max – TA)/ θJA 84°C/W 260°C 220°C 10 sec to 40 sec Transient currents of up to 100 mA do not cause SCR latch-up. Rev. I | Page 6 of 24 Data Sheet AD5304/AD5314/AD5324 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUTC 4 REFIN 5 TOP VIEW (Not to Scale) 10 SYNC 9 SCLK 8 DIN 7 GND 6 VOUTD 2 VOUTB 3 VOUTC 4 AD5304/ AD5314/ AD5324 10 SYNC 9 SCLK 8 DIN TOP VIEW 7 (Not to Scale) 5 6 GND VOUT D NOTES 1. THE EXPOSED PAD IS THE GROUND REFERENCE POINT FOR ALL CIRCUITRY ON THE PART. IT CAN BE CONNECTED TO 0V OR LEFT UNCONNECTED PROVIDED THERE IS A CONNECTION TO 0V VIA THE GND PIN. Figure 3. 10-Lead MSOP Pin Configuration 00929-004 VOUTB 3 AD5304/ AD5314/ AD5324 1 REFIN 00929-003 VDD 1 VOUTA 2 VDD VOUTA Figure 4. 10-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD VOUTA VOUTB VOUTC REFIN VOUTD GND DIN 9 SCLK 10 SYNC Exposed Paddle1 1 Description Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply can be decoupled to GND. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Reference Input Pin for All Four DACs. It has an input range from 0.25 V to VDD. Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each write cycle. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Ground Reference Point for All Circuitry on the Part. Can be connected to 0 V or left unconnected provided there is a connection to 0 V via the GND pin. For the 10-Lead LFCSP only. Rev. I | Page 7 of 24 AD5304/AD5314/AD5324 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 0.2 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 0.1 0 –0.1 –0.5 0 50 100 150 200 250 CODE –0.3 00929-005 –1.0 0 50 150 200 250 CODE Figure 5. AD5304 Typical INL Plot Figure 8. AD5304 Typical DNL Plot 3 0.6 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 2 0.4 DNL ERROR (LSB) 1 0 –1 –2 0.2 0 –0.2 –0.4 0 200 400 600 800 1000 CODE –0.6 00929-006 –3 0 200 400 600 800 1000 CODE Figure 6. AD5314 Typical INL Plot 00929-009 INL ERROR (LSB) 100 00929-008 –0.2 Figure 9. AD5314 Typical DNL Plot 1.0 12 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 8 DNL ERROR (LSB) 0 –4 0 –0.5 –12 0 500 1000 1500 2000 2500 3000 CODE 3500 4000 –1.0 0 500 1000 1500 2000 2500 3000 CODE Figure 7. AD5324 Typical INL Plot Figure 10. AD5324 Typical DNL Plot Rev. I | Page 8 of 24 3500 4000 00929-010 –8 00929-007 INL ERROR (LSB) 0.5 4 Data Sheet AD5304/AD5314/AD5324 0.2 0.50 TA = 25°C VDD = 5V MAX INL MAX DNL 0 MIN DNL –0.25 GAIN ERROR 0 ERROR (%) 0.25 ERROR (LSB) TA = 25°C VREF = 2V 0.1 –0.1 –0.2 –0.3 –0.4 MIN INL OFFSET ERROR 0 1 2 3 4 5 VREF (V) –0.6 00929-011 –0.50 0 0.4 3 4 5 6 Figure 14. Offset Error and Gain Error vs. VDD 5 VDD = 5V VREF = 3V 5V SOURCE 4 0.3 MAX INL 0.2 0.1 VOUT (V) ERROR (LSB) 2 VDD (V) Figure 11. AD5304 INL and DNL Error vs. VREF 0.5 1 00929-014 –0.5 MAX DNL 0 MIN DNL –0.1 3V SOURCE 3 2 –0.2 MIN INL –0.3 5V SINK 3V SINK 1 0 40 80 120 TEMPERATURE (°C) 0 00929-012 –0.5 –40 0 2 3 4 5 6 SINK/SOURCE CURRENT (mA) Figure 12. AD5304 INL Error and DNL Error vs. Temperature 1.0 1 00929-015 –0.4 Figure 15. VOUT Source and Sink Current Capability 600 VDD = 5V VREF = 2V 500 TA = 25°C VDD = 5V VREF = 2V 0.5 IDD (µA) GAIN ERROR 0 300 200 OFFSET ERROR –0.5 –1.0 –40 0 40 80 120 TEMPERATURE (°C) 0 ZERO SCALE FULL SCALE CODE Figure 13. AD5304 Offset Error and Gain Error vs. Temperature Figure 16. Supply Current vs. DAC Code Rev. I | Page 9 of 24 00929-016 100 00929-013 ERROR (%) 400 AD5304/AD5314/AD5324 Data Sheet 600 TA = 25°C VDD = 5V VREF = 5V –40°C 500 CH1 +25°C 400 VOUTA IDD (µA) +105°C 300 SCLK 200 CH2 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) CH1 1V, CH2 5V, TIME BASE = 1µs/DIV 00929-017 0 2.5 Figure 17. Supply Current vs. Supply Voltage 00929-020 100 Figure 20. Half-Scale Settling (¼ to ¾ Scale Code Change) 0.5 TA = 25°C VDD = 5V VREF = 2V IDD (µA) 0.4 CH1 VDD CH2 VOUTA 0.3 –40°C 0.2 +25°C 0.1 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV 00929-018 0 2.5 Figure 18. Power-Down Current vs. Supply Voltage Figure 21. Power-On Reset to 0 V 1000 TA = 25°C VDD = 5V VREF = 2V TA = 25°C 900 VOUTA CH1 800 VDD = 5V 700 600 CH2 SCLK VDD = 3V 400 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VLOGIC (V) 5.0 Figure 19. Supply Current vs. Logic Input Voltage CH1 500mV, CH2 5V, TIME BASE = 1µs/DIV Figure 22. Exiting Power-Down to Midscale Rev. I | Page 10 of 24 00929-022 500 00929-019 IDD (µA) 00929-021 +105°C Data Sheet AD5304/AD5314/AD5324 0.02 350 400 450 500 550 600 IDD (µA) 0.01 0 –0.01 –0.02 0 1 2 3 4 5 6 VREF (V) Figure 23. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 26. Full-Scale Error vs. VREF 2.50 VOUT (V) 1mV/DIV 2.49 1µs/DIV 150ns/DIV Figure 24. AD5324 Major-Code Transition Glitch Energy Figure 27. DAC-to-DAC Crosstalk 10 0 –10 (dB) –20 –30 –40 –60 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 00929-025 –50 Figure 25. Multiplying Bandwidth (Small-Signal Frequency Response) Rev. I | Page 11 of 24 00929-027 2.47 00929-024 2.48 00929-026 300 VDD = 5V 00929-023 FREQUENCY VDD = 3V FULL-SCALE ERROR (V) VDD = 5V TA = 25°C AD5304/AD5314/AD5324 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. Typical INL vs. code plots can be seen in Figure 5, Figure 6, and Figure 7. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL vs. code plots can be seen in Figure 8, Figure 9, and Figure 10. Offset Error This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. Offset Error Drift This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in decibels. VREF is held at 2 V and VDD is varied ±10%. DC Crosstalk This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another DAC. It is expressed in microvolts. Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in decibels. Major-Code Transition Glitch Energy Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device when the DAC output is not being written to (SYNC held high). It is specified in nV-s and is measured with a worstcase change on the digital input pins (for example, from all 0s to all 1s or vice versa.) Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is expressed in nV-s. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with the LDAC bit set low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels. Rev. I | Page 12 of 24 Data Sheet AD5304/AD5314/AD5324 GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE IDEAL ACTUAL NEGATIVE OFFSET ERROR DAC CODE GAIN ERROR PLUS OFFSET ERROR DEAD BAND CODES OUTPUT VOLTAGE AMPLIFIER FOOTROOM (1mV) ACTUAL NEGATIVE OFFSET ERROR 00929-028 POSITIVE OFFSET DAC CODE Figure 28. Transfer Function with Negative Offset Figure 29. Transfer Function with Positive Offset Rev. I | Page 13 of 24 00929-029 IDEAL AD5304/AD5314/AD5324 Data Sheet THEORY OF OPERATION FUNCTIONAL DESCRIPTION R The AD5304/AD5314/AD5324 are quad, resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. Each contains four output buffer amplifiers and is written to via a 3-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/μs. The four DACs share a single reference input pin. The devices have programmable power-down modes, in which all DACs can be turned off completely with a high impedance output. R TO OUTPUT AMPLIFIER R 00929-031 R R Figure 31. Resistor String Digital-to-Analog DAC Reference Inputs The architecture of one DAC channel consists of a resistor-string DAC followed by an output buffer amplifier. The voltage at the REFIN pin provides the reference voltage for the DAC. Figure 30 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by There is a single reference input pin for the four DACs. The reference input is not buffered. The user can have a reference voltage as low as 0.25 V or as high as VDD because there is no restriction due to the headroom or footroom requirements of any reference amplifier. It is recommended to use a buffered reference in the external circuit (for example, REF192). The input impedance is typically 45 kΩ. VOUT = VREF × D 2N Output Amplifier where D = decimal equivalent of the binary code that is loaded to the DAC register: 0–255 for AD5304 (8 bits) 0–1023 for AD5314 (10 bits) 0–4095 for AD5324 (12 bits) The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 V to VDD when the reference is VDD. It is capable of driving a load of 2 kΩto GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in the plot in Figure 15. The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at eight bits) of 6 μs. N = DAC resolution. REFIN POWER-ON RESET DAC REGISTER RESISTOR STRING VOUTA OUTPUT BUFFER AMPLIFIER 00929-030 INPUT REGISTER Figure 30. DAC Channel Architecture Resistor String The resistor string section is shown in Figure 31. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. The AD5304/AD5314/AD5324 are provided with a power-on reset function, so that they power up in a defined state. The power-on state uses normal operation and an output voltage set to 0 V. Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. SERIAL INTERFACE The AD5304/AD5314/AD5324 are controlled over a versatile, 3-wire serial interface that operates at clock rates up to 30 MHz and are compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. Rev. I | Page 14 of 24 Data Sheet AD5304/AD5314/AD5324 A1 BIT0 (LSB) A0 PD LDAC D7 D6 D5 D4 D3 D2 D1 D0 0 0 X X DATA BITS 00929-032 BIT15 (MSB) Figure 32. AD5304 Input Shift Register Contents A1 A0 PD LDAC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DATA BITS 00929-033 BIT0 (LSB) BIT15 (MSB) Figure 33. AD5314 Input Shift Register Contents A1 BIT0 (LSB) A0 PD LDAC D11 D10 D9 D8 D7 D6 D5 D4 D3 DATA BITS D2 D1 D0 00929-034 BIT15 (MSB) Figure 34. AD5324 Input Shift Register Contents Input Shift Register The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. See Figure 2 for the timing diagram of this operation. The 16-bit word consists of four control bits followed by 8, 10, or 12 bits of DAC data, depending on the device type. Data is loaded MSB first (Bit 15) and the first two bits determine whether the data is for DAC A, DAC B, DAC C, or DAC D. Bit 13 and Bit 12 control the operating mode of the DAC. Bit 13 is PD, and determines whether the part is in normal or power-down mode. Bit 12 is LDAC, and controls when DAC registers and outputs are updated. Table 6. Address Bits A1 0 0 1 1 A0 0 1 0 1 DAC Addressed DAC A DAC B DAC C DAC D 0: All four DACs go into power-down mode, consuming only 200 nA at 5 V. The DAC outputs enter a high impedance state. 1: Normal operation. LDAC The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while SYNC is low. To start the serial data transfer, take SYNC low, observing the minimum SYNC to SCLK falling edge setup time, t4. After SYNC goes low, serial data shifts into the device’s input shift register on the falling edges of SCLK for 16 clock pulses. Any data and clock pulses after the 16th falling edge of SCLK are ignored because the SCLK and DIN input buffers are powered down. No further serial data transfer occurs until SYNC is taken high and low again. SYNC can be taken high after the falling edge of the 16th SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t7. Address and Control Bits PD corresponding to 0 V output and all 1s corresponding to full-scale output (VREF − 1 LSB). 0: All four DAC registers and, therefore, all DAC outputs updated simultaneously on completion of the write sequence. 1: Only addressed input register is updated. There is no change in the content of the DAC registers. It is not recommended to set the PD and LDAC control bits simultaneously. Depending on the SPI transmission rate, this causes the data transferred to be loaded into the DAC register if the LDAC control bit was previously set. After the end of the serial data transfer, data automatically transfers from the input shift register to the input register of the selected DAC. If SYNC is taken high before the 16th falling edge of SCLK, the data transfer is aborted and the DAC input registers are not updated. When data has been transferred into three of the DAC input registers, all DAC registers and all DAC outputs are simultaneously updated by setting LDAC low when writing to the remaining DAC input register. Low Power Serial Interface To reduce the power consumption of the device even further, the interface fully powers up only when the device is being written to, that is, on the falling edge of SYNC. As soon as the 16-bit control word has been written to the part, the SCLK and DIN input buffers are powered down. They power up again only following a falling edge of SYNC. The AD5324 uses all 12 bits of DAC data; the AD5314 uses 10 bits and ignores the 2 LSB Bits. The AD5304 uses eight bits and ignores the last four bits. The data format is straight binary, with all 0s Rev. I | Page 15 of 24 AD5304/AD5314/AD5324 Data Sheet Access to the DAC register is controlled by the LDAC bit. When the LDAC bit is set high, the DAC register is latched and hence the input register can change state without affecting the contents of the DAC register. However, when the LDAC bit is set low, all DAC registers are updated after a complete write sequence. This is useful if the user requires simultaneous updating of all DAC outputs. The user can write to three of the input registers individually and then, by setting the LDAC bit low when writing to the remaining DAC input register, all outputs update simultaneously. These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5304/AD5314/AD5324, the part updates the DAC register only if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk. POWER-DOWN MODE AMPLIFIER RESISTOR STRING DAC VOUT 00929-035 The AD5304/AD5314/AD5324 DACs have double-buffered interfaces consisting of two banks of registers—input registers and DAC registers. The input register is directly connected to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC register contains the digital code used by the resistor string. The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the powerdown mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 μs for VDD = 5 V and 5 μs when VDD = 3 V. This is the time from the falling edge of the 16th SCLK pulse to when the output voltage deviates from its power down voltage. See Figure 22 for a plot. POWER-DOWN CIRCUITRY Figure 35. Output Stage during Power-Down MICROPROCESSOR INTERFACING AD5304/AD5314/AD5324 to ADSP-21xx Figure 36 shows a serial interface between the AD5304/AD5314/ AD5324 and the ADSP-21xx family. The ADSP-21xx is set up to operate in the SPORT transmit alternate framing mode. The ADSP-21xx sport is programmed through the SPORT control register and must be configured as follows: internal clock operation, active-low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each rising edge of the DSP’s serial clock and clocked into the AD5304/AD5314/ AD5324 on the falling edge of the DAC’s SCLK. The AD5304/AD5314/AD5324 have low power consumption, dissipating only 1.5 mW with a 3 V supply and 3 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, selected by a 0 on Bit 13 (PD) of the control word. When the PD bit is set to 1, all DACs work normally with a typical power consumption of 600 μA at 5 V (500 μA at 3 V). However, in power-down mode, the supply current falls to 200 nA at 5 V (80 nA at 3 V) when all DACs are powered down. Not only does the supply current drop, but also the output stage is internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the output is three-stated while the part is in power-down mode, and provides a defined input condition for whatever is connected to the output of the DAC amplifier. The output stage is illustrated in Figure 35. Rev. I | Page 16 of 24 ADSP-21xx* TFS DT SCLK AD5304/ AD5314/ AD5324* SYNC DIN SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. 00929-036 Double-Buffered Interface Figure 36. AD5304/AD5314/AD5324 to ADSP-21xx Interface Data Sheet AD5304/AD5314/AD5324 Figure 37 shows a serial interface between the AD5304/AD5314/ AD5324 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5304/AD5314/AD5324, while the MOSI output drives the serial data line (DIN) of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for the correct operation of this interface are as follows: the 68HC11/68L11 is configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/ 68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5304/ AD5314/AD5324, PC7 is left low after the first eight bits are transferred, a second serial write operation is performed to the DAC, and PC7 is taken high at the end of this procedure. SCK SCLK MOSI SYNC TxD SCLK RxD DIN *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 38. AD5304/AD5314/AD5324 to 80C51/80L51 Interface Figure 39 shows an interface between the AD5304/AD5314/ AD5324 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock, SK, and is clocked into the AD5304/AD5314/AD5324 on the rising edge of SK, which corresponds to the falling edge of the DAC’s SCLK. DIN *ADDITIONAL PINS OMITTED FOR CLARITY. P3.3 MICROWIRE* Figure 37. AD5304/AD5314/AD5324 to 68HC11/68L11 Interface AD5304/ AD5314/ AD5324* AD5304/AD5314/AD5324 to 80C51/80L51 Interface CS SYNC Figure 38 shows a serial interface between the AD5304/AD5314/ AD5324 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5304/AD5314/AD5324, while RxD drives the serial data line of the part. The SYNC signal is again derived from a bit-programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the AD5304/AD5314/ AD5324, P3.3 is taken low. The 80C51/80L51 transmits data SK SCLK SO DIN Rev. I | Page 17 of 24 *ADDITIONAL PINS OMITTED FOR CLARITY. 00929-039 SYNC AD5304/ AD5314/ AD5324* AD5304/AD5314/AD5324 to MICROWIRE Interface AD5304/ AD5314/ AD5324* PC7 80C51/80L51* 00929-037 68HC11/68L11* only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD5304/ AD5314/AD5324 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine takes this into account. 00929-038 AD5304/AD5314/AD5324 to 68HC11/68L11 Interface Figure 39. AD5304/AD5314/AD5324 to MICROWIRE Interface AD5304/AD5314/AD5324 Data Sheet APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT Bipolar Operation Using the AD5304/AD5314/AD5324 The AD5304/AD5314/AD5324 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0 V to VDD. More typically, these devices are used with a fixed, precision reference voltage. Suitable references for 5 V operation are the AD780 and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference would be the AD589, a 1.23 V band gap reference. Figure 40 shows a typical setup for the AD5304/ AD5314/AD5324 when using an external reference. The AD5304/AD5314/AD5324 have been designed for single supply operation, but a bipolar output range is also possible using the circuit in Figure 41. This circuit gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. R2 = 10kΩ +6V TO +16V +5V R1 = 10kΩ 0.1µF 10µF AD820/ OP295 +5V VDD = 2.5V TO 5.5V REF195 AD5304 VIN VOUT 10µF GND EXTERNAL REFERENCE REFIN VOUTA SCLK VOUTB DIN VOUTC SYNC VOUTD GND 1µF AD790/REF192 WITH VDD = 5V OR AD589 WITH VDD = 2.5V A0 SCLK SYNC SERIAL INTERFACE Figure 41. Bipolar Operation with the AD5304 GND SERIAL INTERFACE VOUTD DIN 00929-040 VOUT –5V VOUTB 1µF VOUTC AD5304/AD5314/ AD5324 VIN REFIN Figure 40. AD5304/AD5314/AD5324 Using External Reference If an output range of 0 V to VDD is required, the simplest solution is to connect the reference input to VDD. As this supply is not very accurate and can be noisy, the AD5304/AD5314/AD5324 can be powered from the reference voltage; for example, using a 5 V reference such as the REF195. The REF195 can output a steady supply voltage for the AD5304/AD5314/AD5324. The current required from the REF195 is 600 μA supply current and approximately 112 μA into the reference input. This is with no load on the DAC outputs. When the DAC outputs are loaded, the REF195 also needs to supply the current to the loads. The total current required (with a 10 kΩload on each output) is The output voltage for any input code can be calculated as follows: (REFIN × D / 2 N ) × (R1 + R2) VOUT = − REFIN × (R2 / R1) R1 where: D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. REFIN is the reference voltage input: 712 μA + 4 (5 V/10 kΩ) = 2.70 mA The load regulation of the REF195 is typically 2 ppm/mA, resulting in an error of 5.4 ppm (27 μV) for the 2.7 mA current drawn from it. This corresponds to a 0.0014 LSB error at eight bits and 0.022 LSB error at 12 bits. Rev. I | Page 18 of 24 REFIN = 5 V, R1 = R2 = 10 kΩ VOUT = (10 × D/2N) − 5 V 00929-041 0.1µF ±5V VOUTA VDD Data Sheet AD5304/AD5314/AD5324 Opto-Isolated Interface for Process Control Applications DIN VCC 0.1µF CODED ADDRESS 10kΩ 1Y1 1B 1Y2 1Y3 SYNC DIN SCLK DGND VOUTA VOUTB VOUTC VOUTD AD5304 SYNC DIN SCLK VOUTA VOUTB VOUTC VOUTD AD5304 SYNC DIN SCLK VOUTA VOUTB VOUTC VOUTD SCLK A digitally programmable upper/lower limit detector using two DACs in the AD5304/AD5314/AD5324 is shown in Figure 44. The upper and lower limits for the test are loaded to DAC A and DAC B, which, in turn, set the limits on the CMP04. If the signal at the VIN input is not within the programmed window, an LED indicates the fail condition. Similarly, DAC C and DAC D can be used for window detection on a second VIN signal. VDD REFIN AD5304 10kΩ VOUTA SYNC 5V VOUTB 0.1µF 10µF VIN 1kΩ 1kΩ VOUTC VREF 00929-042 Figure 42. AD5304 in an Opto-Isolated Interface REFIN SYNC DIN SCLK 1/2 CMP04 DIN SCLK GND VOUTB *ADDITIONAL PINS OMITTED FOR CLARITY. Rev. I | Page 19 of 24 PASS/FAIL SYNC DECODING MULTIPLE AD5304/AD5314/AD5324S The SYNC pin on the AD5304/AD5314/AD5324 can be used in applications to decode a number of DACs. In this application, all the DACs in the system receive the same serial clock and serial data, but SYNC can only be active to one of the devices at any one time, allowing access to four channels in this 16-channel system. The 74HC139 is used as a 2-to-4-line decoder to address any of the DACs in the system. To prevent timing errors, the enable input must be brought to its inactive state while the coded address inputs are changing state. Figure 43 shows a diagram of a typical setup for decoding multiple AD5304 devices in a system. PASS VOUTA 1/2 AD5304/AD5314/ AD5324* DIN GND FAIL VDD VOUTD Figure 44. Window Detection 1/6 74HC05 00929-044 VDD 10kΩ DIN AD5304 1Y0 1A AD5304/AD5314/AD5324 as a Digitally Programmable Window Detector VDD SYNC 1G 74HC139 VOUTA VOUTB VOUTC VOUTD Figure 43. Decoding Multiple AD5304 Devices in a System 10µF VDD SYNC DIN SCLK VDD ENABLE 5V REGULATOR POWER SCLK AD5304 SCLK 00929-043 The AD5304/AD5314/AD5324 have a versatile 3-wire serial inter-face, making them ideal for generating accurate voltages in process control and industrial applications. Due to noise, safety requirements, or distance, it might be necessary to isolate the AD5304/AD5314/AD5324 from the controller. This can easily be achieved by using opto-isolators, which provide isolation in excess of 3 kV. The actual data rate achieved is limited by the type of optocouplers chosen. The serial loading structure of the AD5304/AD5314/AD5324 makes them ideally suited for use in opto-isolated applications. Figure 42 shows an opto-isolated interface to the AD5304 where DIN, SCLK, and SYNC are driven from optocouplers. The power supply to the part also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5304. AD5304/AD5314/AD5324 Data Sheet POWER SUPPLY BYPASSING AND GROUNDING the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5304/AD5314/AD5324 is mounted is designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5304/AD5314/AD5324 are in a system where multiple devices require an AGND-to-DGND connection, the connection is made at one point only. The star ground point is established as close as possible to the device. The AD5304/AD5314/AD5324 has ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor has low effective series resistance (ESR) and effective series inductance (ESI), like The power supply lines of the AD5304/AD5314/AD5324 use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks are shielded with digital ground to avoid radiating noise to other parts of the board, and are never run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to a ground plane while signal traces are placed on the solder side. Table 7. Overview of AD53xx Serial Devices Part No. SINGLES Resolution No. of DACs DNL Interface Settling Time (μs) Package Pins AD5300 AD5310 AD5320 AD5301 AD5311 AD5321 DUALS 8 10 12 8 10 12 1 1 1 1 1 1 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 SPI SPI SPI 2-Wire 2-Wire 2-Wire 4 6 8 6 7 8 SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 AD5302 AD5312 AD5322 AD5303 AD5313 AD5323 QUADS 8 10 12 8 10 12 2 2 2 2 2 2 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 SPI SPI SPI SPI SPI SPI 6 7 8 6 7 8 MSOP MSOP MSOP TSSOP TSSOP TSSOP 8 8 8 16 16 16 AD5304 AD5314 AD5324 AD5305 AD5315 AD5325 AD5306 AD5316 AD5326 AD5307 AD5317 AD5327 OCTALS 8 10 12 8 10 12 8 10 12 8 10 12 4 4 4 4 4 4 4 4 4 4 4 4 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 SPI SPI SPI 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire SPI SPI SPI 6 7 8 6 7 8 6 7 8 6 7 8 MSOP, LFCSP MSOP, LFCSP MSOP, LFCSP MSOP MSOP MSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP 10 10 10 10 10 10 16 16 16 16 16 16 AD5308 AD5318 AD5328 8 10 12 8 8 8 ±0.25 ±0.5 ±1.0 SPI SPI SPI 6 7 8 TSSOP TSSOP TSSOP 16 16 16 Rev. I | Page 20 of 24 Data Sheet AD5304/AD5314/AD5324 Table 8. Overview of AD53xx Parallel Devices Part No. SINGLES AD5330 Resolution DNL VREF Pins Settling Time (μs) 8 ±0.25 1 6 AD5331 10 ±0.5 1 7 AD5340 12 ±1.0 1 8 ✓ AD5341 12 ±1.0 1 8 ✓ ✓ DUALS AD5332 8 ±0.25 2 6 AD5333 10 ±0.5 2 7 ✓ AD5342 12 ±1.0 2 8 ✓ AD5343 12 ±1.0 1 8 QUADS AD5334 8 ±0.25 2 6 AD5335 10 ±0.5 2 7 AD5336 10 ±0.5 4 7 AD5344 12 ±1.0 4 8 BUF ✓ Additional Pin Functions GAIN HBEN CLR Pins ✓ ✓ TSSOP 20 ✓ ✓ TSSOP 20 ✓ ✓ TSSOP 24 ✓ TSSOP 20 ✓ TSSOP 20 ✓ ✓ TSSOP 24 ✓ ✓ TSSOP 28 ✓ TSSOP 20 ✓ TSSOP 24 ✓ TSSOP 24 ✓ TSSOP 28 TSSOP 28 ✓ ✓ ✓ ✓ ✓ Rev. I | Page 21 of 24 Package AD5304/AD5314/AD5324 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 45. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 6 0.50 0.40 0.30 5 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 10 1.74 1.64 1.49 EXPOSED PAD 0.05 MAX 0.02 NOM 0.30 0.25 0.20 1 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF Figure 46. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-10-9) Dimensions shown in millimeters Rev. I | Page 22 of 24 PIN 1 INDICATOR (R 0.15) 121009-A PIN 1 INDEX AREA Data Sheet AD5304/AD5314/AD5324 ORDERING GUIDE Model 1, 2 AD5304ARM AD5304ARMZ AD5304ARMZ-REEL7 AD5304ACPZ-REEL7 AD5304BRMZ AD5304BRMZ-REEL AD5304BRMZ-REEL7 AD5304BCPZ-REEL7 AD5314ACPZ-REEL7 AD5314ARM-REEL7 AD5314ARMZ AD5314ARMZ-REEL7 AD5314WARMZ-REEL7 AD5314BCPZ-REEL7 AD5314BRM AD5314BRM-REEL7 AD5314BRMZ AD5314BRMZ-REEL AD5314BRMZ-REEL7 AD5324ACPZ-REEL7 AD5324ARM AD5324ARMZ AD5324ARMZ-REEL7 AD5324BCPZ-REEL7 AD5324BRM AD5324BRM-REEL7 AD5324BRMZ AD5324BRMZ-REEL AD5324BRMZ-REEL7 EVAL-AD5324DBZ 1 2 Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP 10-Lead LFCSP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Package Option RM-10 RM-10 RM-10 CP-10-9 RM-10 RM-10 RM-10 CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 CP-10-9 RM-10 RM-10 RM-10 RM-10 RM-10 CP-10-9 RM-10 RM-10 RM-10 CP-10-9 RM-10 RM-10 RM-10 RM-10 RM-10 Branding DBA D9W D9W DBA# DBB# DBB# DBB# DBB# DCA# DCA DCA# DCA# DCA# DCB# DCB DCB DCB# DCB# DCB# DDA# DDA D8F D8F DDB# DDB DDB DDB# DDB# DDB# Z = RoHS Compliant Part; # denotes lead-free product can be top or bottom marked. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5314WARMZ-REEL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. Rev. I | Page 23 of 24 AD5304/AD5314/AD5324 Data Sheet NOTES ©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00929-0-5/17(I) Rev. I | Page 24 of 24
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No ADI Prelim : Data Sheet ADI Pub Year : 2011–2017 ADI Pubcode : D00929-0-5/17(I) ADI Rev : I ADI Template : 3.5RC4 ADI Title : AD5304/AD5314/AD5324 Author : Analog Devices, Inc. Category : Datasheet Create Date : 2017:05:04 09:31:10-04:00 Keywords : "8-bit, 10-bit, 12-bit, DAC, digital-to-analog converter" Modify Date : 2017:05:04 17:29:31-04:00 Source Modified : D:20170504132850 Has XFA : No Language : EN-US Tagged PDF : Yes XMP Toolkit : Adobe XMP Core 5.4-c006 80.159825, 2016/09/16-03:31:08 Metadata Date : 2017:05:04 17:29:31-04:00 Creator Tool : Acrobat PDFMaker 11 for Word Document ID : uuid:2b7a23e8-fa05-4c0b-8332-2ea39554d97b Instance ID : uuid:b22b3c3b-e44b-4603-88af-23a1a35eb9c6 Format : application/pdf Title : AD5304/AD5314/AD5324 (Rev. I) Description : 2.5 V to 5.5 V, 500 μA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead Packages Creator : Analog Devices, Inc. Subject : 8-bit, 10-bit, 12-bit, DAC, digital-to-analog converter Producer : Adobe PDF Library 11.0 ADI0020 Rev : I ADI0020 Title : AD5304/AD5314/AD5324 ADI0020 Prelim : Data Sheet ADI0020 Pubcode : D00929-0-5/17(I) ADI0020 Pub 0020 Year : 2011–2017 ADI0020 Template : 3.5RC4 Headline : 2.5 V to 5.5 V, 500 μA, Quad Voltage Output 8-/10-/12-Bit ADCs in 10-Lead Packages Page Layout : OneColumn Page Mode : UseOutlines Page Count : 24 Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools