AD9361 Reference Manual (Rev. A)

User Manual:

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General Information
Table of Contents
Revision History
Introduction
- Terminology
- Register and Bit Syntax
Initialization and Calibration
- Overview
- Initalization Calibrations
- BBPLL VCO Calibration
- RF Synthesizer Charge Pump Calibration
- RF Synthesizer VCO Calibration
- Baseband Rx Analog Filter Calibration
- Baseband Tx Analog Filter Calibration
- Baseband Tx Secondary Filter
- Rx TIA Calibration Equations
- Rx ADC Setup
- Baseband DC Offset Calibration
- Baseband DC Offset Tracking
- RF DC Offset Calibration
- Rx Quadrature Tracking Calibration
- Tx Quadrature Calibration
Reference Clock Requirements
- Overview
- DCXO Setup and Operation
- Reference Clock Setup and Operation
- Phase Noise Specification
RF and BBPLL Synthesizer
- Overview
- RFPLL Introduction
- AD9361 PLL Architecture
- Reference Block
- Main PLL Block
- Charge Pump Current
- RFPLL Loop Filter
- VCO Configuration
- VCO Calibration
- VCO Vtune Measurement
- Lock Detector
- Synthesizer Look Up Table
- TDD Mode Faster Lock Times
- External LO
- Baseband PLL (BBPLL)
- BBPLL VCO
- BBPLL Charge Pump
- BBPLL Loop Filter
Fast Lock Profiles
- Overview
- Fast Lock Initial Wider BW Option
- Configuring and Using a Fast Lock Profile
- Fast Lock Pin Select
Enable State Machine Guide
- Overview
- ENSM State Definitions
- Modes of Operation
- Sleep State
  - Sleep Procedure (Assumes Current State = ALERT)
  - Calibrations After Waking from SLEEP
Filter Guide
- Overview
- Tx Signal Path
- Tx Digital Filter Blocks
- Tx Analog Filter Blocks
  - Tx BB LPF
  - Tx Secondary LPF
- Rx Signal Path
- Rx Analog Filter Blocks
  - Rx TIA LPF
  - Rx BB LPF
- Rx Digital Filter Blocks
- Digital Rx Block Delay
  - Example—LTE 10 MHz
Gain Control
- Overview
- Gain Control Threshold Detectors
- LMT Overload Detector
- ADC Overload Detector
- Low Power Threshold
- Average Signal Power
- Settling Times
- Peak Overload Wait Time
- Settling Delay
- Gain Table Overview
- Full Table Mode
- Split Table Mode
- Digital Gain
- MGC Overview
- Slow Attack AGC Mode
- Slow Attack AGC Gain Update Time
- Overloads in Slow Attack AGC Mode
- Slow Attack AGC and Gain Tables
- Hybrid AGC Mode
- Fast Attack AGC Mode
- State 0: RESET
- State 1: Peak Overload Detect
- State 2: Measure Power and Lock Level Gain Change
- State 3: Measure Power and Peak Overload Detect
- State 4: Unlock Gain
- State 5: Gain Lock and Measure Power
Custom Gain Tables
- Overview
- RF DC Cal Bit
- Maximum Full Table/LMT Table Index
- External LNA
Received Signal Strength Indicator (RSSI)
- Overview
- Mode Select and Measurement Duration
- RSSI Weighting
- RSSI Delay and RSSI Wait
- RSSI Preamble and RSSI Symbol
- RSSI RFIR
- RSSI Gain Step Calibration
  - Programming Gain Step Errors in the Field
Transmit Power Control
- Overview
- Tx Attenuation Words
- Attenuation Word Update Options
Tx Power Monitor
- Overview
- Tx Power Monitor Description
- Input Matching/Attenuation Network
- Tx Power Monitor Gain Control
- TPM Dynamic Range
- Example of TxMon Configuration and Measurement of TPM Transfer Function
- TPM Test Mode
RF Port Interface
- Overview
- Rx Signal Path Interface
- Tx Signal Path Interface
Factory Calibrations
- Overview
- Internal DCXO
- Tx RSSI (Tx Monitor)
- Rx RSSI
- Rx GM/LNA Gain Step Calibration
- Tx Power Out vs. Tx Attenuation and Tx Power Out vs. Carrier Frequency
Control Output
- Overview
- Description of Control Output Signals
- 0x035 = 0x00 (Calibration Busy and Done)
  - Control Output 7 (Cal Done)
  - Control Output 6 (Tx CP Cal Done)
  - Control Output 5 (Rx CP Cal Done)
  - Control Output 4 (Rx BB Filter Tuning Done)
  - Control Output 3 (Tx BB Filter Tuning Done)
  - Control Output 2 (Gain Step Cal Busy)
  - Control Output 1 (Rx Synth VCO Cal Busy)
  - Control Output 0 (Tx Synth VCO Cal Busy)
- 0x035 = 0x01 (PLL Lock)
  - Control Output 7 (Tx RF PLL Lock)
  - Control Output 6 (Rx RF PLL Lock)
  - Control Output 5 (BBPLL Lock)
  - Control Output 4 Through Control Output 0
- 0x035 = 0x02 (Calibration Busy)
  - Control Output 7 (BB DC Cal Busy)
  - Control Output 6 (RF DC Cal Busy)
  - Control Output 5 (CH1 Rx Quad Cal Busy)
  - Control Output 4 (CH1 Tx Quad Cal Busy)
  - Control Output 3 (CH2 Rx Quad Cal Busy)
  - Control Output 2 (CH2 Tx Quad Cal Busy)
  - Control Output 1 (Gain Step Cal Busy)
  - Control Output 0 (Tx Mon Cal Busy)
- 0x035 = 0x03 (Rx Gain Control)
  - Control Output 7 (CH1 ADC Low Power)
  - Control Output 6 (CH1 Lg LMT Ovrg)
  - Control Output 5 (CH1 Lg ADC Ovrg)
  - Control Output 4 (CH1 Sm ADC Ovrg)
  - Control Output 3 (CH2 Low Power)
  - Control Output 2 (CH2 Lg LMT Ovrg)
  - Control Output 1 (CH2 Lg ADC Ovrg)
  - Control Output 0 (CH2 Sm ADC Ovrg)
- 0x035 = 0x04 (Rx Gain Control)
  - Control Output 7 Through Control Output 3 (CH2 Rx Gain [6:2])
  - Control Output 2 (CH2 Lg LMT Ovrg)
  - Control Output 1 (CH2 Lg ADC Ovrg)
  - Control Output 0 (CH2 Gain Lock)
- 0x035 = 0x05 (Rx Gain Control)
  - Control Output 7 (CH2 Gain Change)
  - Control Output 6 (CH1 Gain Change)
  - Control Output 5 (CH2 Low Power)
  - Control Output 4 (CH2 Lg LMT Ovrg)
  - Control Output 3 (CH2 Lg ADC Ovrg)
  - Control Output 2 (CH2 Gain Lock)
  - Control Output 1 (CH2 Energy Lost)
  - Control Output 0 (CH2 Stronger Signal)
- 0x035 = 0x06 (Rx Gain Control)
  - Control Output 7 (CH1 ADC Low Power)
  - Control Output 6 (CH1 Lg LMT Ovrg)
  - Control Output 5 (CH1 Lg ADC Ovrg)
  - Control Output 4 Through Control Output 0 (CH1 Rx Gain[6:2])
- 0x035 = 0x07 (Rx Gain Control)
  - Control Output 7 (CH1 ADC Low Power)
  - Control Output 6 (CH1 Lg LMT Ovrg)
  - Control Output 5 (CH1 Lg ADC Ovrg)
  - Control Output 4 (CH1 Sm ADC Ovrg)
  - Control Output 3 Through Control Output 1 (CH1 AGC SM[2:0])
  - Control Output 0 (CH1 Gain Lock)
- 0x035 = 0x08 (Rx Gain Control)
  - Control Output 7 (CH1 Stronger Signal)
  - Control Output 6 (CH1 Gain Lock)
  - Control Output 5 (CH1 Energy Lost)
  - Control Output 4 (CH1 Gain Change)
  - Control Output 3 (CH2 Stronger Signal)
  - Control Output 2 (CH2 Gain Lock)
  - Control Output 1 (CH2 Energy Lost)
  - Control Output 0 (CH2 Gain Change)
- 0x035 = 0x09 (RxOn, TxOn, RSSI)
  - Control Output 7 (RxON)
  - Control Output 6 (CH1 RSSI Preamble Ready)
  - Control Output 5 (CH1 RSSI Symbol Ready)
  - Control Output 4 (TxON)
  - Control Output 3 (CH2 RSSI Preamble Ready)
  - Control Output 2 (CH2 RSSI Symbol Ready)
- 0x035 = 0x0A (Digital Overflow)
  - Control Output 7 (CH1 Tx Int3 Overflow)
  - Control Output 6 (CH1 Tx HB3 Overflow)
  - Control Output 5 (CH1 Tx HB2 Overflow)
  - Control Output 4 (CH1 Tx QEC Overflow)
  - Control Output 3 (CH1 Tx HB1 Overflow)
  - Control Output 2 (CH1 Tx FIR Overflow)
  - Control Output 1 (CH1 Rx FIR Overflow)
- 0x035 = 0x0B (Calibration and ENSM States)
  - Control Output 7 Through Control Output 4 (Cal Seq State [3:0])
  - Control Output 3 Through Control Output 0 (ENSM[3:0])
- 0x035 = 0x0C (Gain Control)
  - Control Output 7 (CH1 Energy Lost)
  - Control Output 6 (CH1 Reset Peak Detect)
  - Control Output 5 (CH2 Energy Lost)
  - Control Output 4 (CH2 Reset Peak Detect)
  - Control Output 3 (Gain Freeze)
  - Control Output 2 (CH1 Digital Sat)
  - Control Output 1 (CH2 Digital Sat)
- 0x035 = 0x0D (Tx Quadrature and RF DC Calibration Status)
  - Control Output 7 and Control Output 6 (CH1 Tx Quad Cal Status[1:0])
  - Control Output 5 (CH1 Tx Quad Cal Done)
  - Control Output 4 (RF DC Cal Busy)
  - Control Output 3 and Control Output 2 (CH2 Tx Quad Cal Status[1:0])
  - Control Output 1 (CH2 Tx Quad Cal Done)
- 0x035 = 0x0E (Rx Quadrature and BB DC Calibration Status)
  - Control Output 4 (BB DC Cal Busy)
- 0x035 = 0x0F (Gain Control)
  - Control Output 7 Through Control Output 5 (CH1 AGC State[2:0])
  - Control Output 4 (CH1 Reset Peak Detect)
  - Control Output 3 (CH2 Reset Peak Detect)
  - Control Output 2 and Control Output 1 (CH1 RF DC Cal State[1:0])
- 0x035 = 0x10 (Gain Control and RSSI)
  - Control Output 7 Through Control Output 5 (CH2 AGC State[2:0])
  - Control Output 4 (CH2 Enable RSSI)
  - Control Output 3 (CH1 Enable RSSI)
  - Control Output 2 and Control Output 1(CH2 RF DC Cal State[1:0])
- 0x035 = 0x11 (AuxADC Digital Output)
  - Control Output 7 Through Control Output 0 (AuxADC Output[11:4])
- 0x035 = 0x12 (Gain Control, Power Word Ready)
  - Control Output 7 (CH1 Filter Power Ready)
  - Control Output 6 (CH1 Gain Lock)
  - Control Output 5 (CH1 Energy Lost)
  - Control Output 4 (CH1 Stronger Signal)
  - Control Output 3 (CH1 ADC Power Ready)
  - Control Output 2 Through Control Output 0 (CH1 AGC State[2:0])
- 0x035 = 0x13 (Gain Control, Power Word Ready)
  - Control Output 7 (CH2 Filter Power Ready)
  - Control Output 6 (CH2 Gain Lock)
  - Control Output 5 (CH2 Energy Lost)
  - Control Output 4 (CH2 Stronger Signal)
  - Control Output 3 (CH2 ADC Power Ready)
  - Control Output 2 Through Control Output 0 (CH2 AGC State[2:0])
- 0x035 = 0x14 (Digital Overflow)
  - Control Output 7 (CH2 Tx Int3 Overflow)
  - Control Output 6 (CH2 Tx HB3 Overflow)
  - Control Output 5 (CH2 Tx HB2 Overflow)
  - Control Output 4 (CH2 Tx QEC Overflow)
  - Control Output 3 (CH2 Tx HB1 Overflow)
  - Control Output 2 (CH2 Tx FIR Overflow)
  - Control Output 1 (CH2 Rx FIR Overflow)
  - Control Output 0
- 0x035 = 0x15 (DC Offset Tracking)
  - Control Output 7 (CH1 SOI Present)
  - Control Output 6 (CH1 Update DCRF)
  - Control Output 5 (CH1 Measure DCRF)
  - Control Output 4 (CH1 DC Track Count Reached)
  - Control Output 3 Through Control Output 0
- 0x035 = 0x16 (Gain Control)
  - Control Output 7 (CH1 Gain Lock)
  - Control Output 6 Through Control Output 0 (CH1 Rx Gain[6:0])
- 0x035 = 0x17 (Gain Control)
  - Control Output 7 (CH2 Gain Lock)
  - Control Output 6 Through Control Output 0 (CH2 Rx Gain[6:0])
- 0x035 = 0x18 (DC Offset Tracking, Power Word Ready)
  - Control Output 7 (CH2 SOI Present)
  - Control Output 6 (CH2 Update DCRF)
  - Control Output 5 (CH2 Measure DCRF)
  - Control Output 4 (CH2 DC Track Count Reached)
  - Control Output 3 (CH2 Enable Dec Pwr)
  - Control Output 2 (CH2 Enable ADC Pwr)
  - Control Output 1 (CH1 Enable Dec Pwr)
  - Control Output 0 (CH1 Enable ADC Pwr)
- 0x035 = 0x19 (Charge Pump Calibration States)
  - Control Output 7 Through Control Output 4 (Rx Syn CP Cal[3:0])
  - Control Output 3 Through Control Output 0 (Tx Syn CP Cal[3:0])
- 0x035 = 0x1A (Rx VCO and ALC Calibration States)
  - Control Output 7 (Rx Syn VCO Tuning[8])
  - Control Output 6 Through Control Output 0 (Rx Synth VCO ALC[6:0])
- 0x035 = 0x1B (Tx VCO and ALC Calibration States)
  - Control Output 7 (Tx Syn VCO Tuning[8])
  - Control Output 6 Through Control Output 0 (Tx Synth VCO ALC[6:0])
- 0x035 = 0x1C (Rx VCO Calibration States)
  - Control Output 7 Through Control Output 0 (Rx Syn VCO Tuning[7:0])
- 0x035 = 0x1D (Tx VCO Calibration States)
  - Control Output 7 Through Control Output 0 (Tx Syn VCO Tuning[7:0])
- 0x035 = 0x1E (Gain Control, Temp Sense Valid, AuxADC Valid)
  - Control Output 7 (CH1 Low Thresh Exceeded)
  - Control Output 6 (CH1 High Thresh Exceeded)
  - Control Output 5 (CH1 Gain Upd Count Exp)
  - Control Output 4 and Control Output 3 (CH1 AGC State[1:0])
  - Control Output 2 (CH1 Gain Change)
  - Control Output 1 (Temp Sense Valid)
  - Control Output 0 (AuxADC Valid)
- 0x035 = 0x1F (Gain Control)
  - Control Output 7 (CH2 Low Thresh Exceeded)
  - Control Output 6 (CH2 High Thresh Exceeded)
  - Control Output 5 (CH2 Gain Upd Count Exp)
  - Control Output 4 and Control Output 3 (CH2 AGC SM[1:0])
  - Control Output 2 (CH2 Gain Change)
AuxADC/AuxDAC/GPO/Temp Sensor
- Overview
- AuxDAC
- AuxADC
- Internal Temperature Sensor
- General Purpose Output Control
  - GPO Auto Toggle
  - GPO Voltage Level, Drive Strength
Baseband Synchronization
- Overview
- Multichip Synchronization
- Procedure
- Synchronization Verification
Digital Interface Specification
- Overview
- CMOS Mode Data Path and Clock Signals
  - P0_D[11:0] and P1_D[11:0]
  - DATA_CLK
  - FB_CLK
  - RX_FRAME
  - TX_FRAME
  - ENABLE
  - TXNRX
- CMOS Maximum Clock Rates and Signal Bandwidths
- Single Port Half Duplex Mode (CMOS)
- Single Port TDD Functional Timing (CMOS)
- Single Port Full Duplex Mode (CMOS)
- Single Port FDD Functional Timing (CMOS)
- Dual Port Half Duplex Mode (CMOS)
- Dual Port TDD Functional Timing (CMOS)
- Dual Port Full Duplex Mode (CMOS)
- Dual Port FDD Functional Timing (CMOS)
- Data Bus Idle and Turnaround Periods (CMOS)
- Data Path Timing Parameters (CMOS)
- LVDS Mode Data Path and Clock Signals
- LVDS Mode Data Path Signals
  - DATA_CLK
  - FB_CLK
  - Rx_FRAME
  - Rx_D[5:0]
  - Tx_FRAME
  - Tx_D[5:0]
  - ENABLE
  - TXNRX
- LVDS Maximum Clock Rates and Signal Bandwidths
- Dual Port Full Duplex Mode (LVDS)
- Data Path Functional Timing (LVDS)
- Data Path Timing Parameters (LVDS)
- Serial Peripheral Interface (SPI)
  - SPI Functional Layer
  - SPI Data Transfer Protocol
  - Timing Diagrams
- Additional Interface Signals
  - CLOCK_OUT
  - CTRL_IN[3:0]
  - CTRL_OUT[7:0]
  - EN_AGC
  - GPO[3:0]
  - RESETB
  - SYNC_IN
Power Supply and Layout Guide
- Overview
- PCB Material And Stack Up Selection
- RF Transmission Line Layout
- Fan-out and Trace Space Guidelines
- Component Placement and Routing Guidelines
- Power Management and System Noise Considerations
- Power Distributions for Different Power Supply Domains
  - Rx and Tx Synthesizer Supplies
  - Tx Balun DC Feed Supplies
- Rx LO Frequency Deviations Due to Power Supply Transients
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