AD9361 Register Map Reference Manual UG 671
User Manual:
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Page Count: 72
- General Description
- Table of Contents
- Revision History
- General Setup and Digital Data Port Configuration
- Chip Level Setup Registers (Address 0x000 Through Address 0x007)
- SPI Register 0x000—SPI Configuration
- SPI Register 0x001—Multichip Sync and Tx Monitor Control
- SPI Register 0x002—Tx Enable and Filter Control
- SPI Register 0x003—Rx Enable and Filter Control
- SPI Register 0x004—Input Select
- SPI Register 0x005—RFPLL Dividers
- SPI Register 0x006—Rx Clock and Data Delay
- SPI Register 0x007—Tx Clock and Data Delay
- Clock Control Registers (Address 0x009 Through Address 0x00A)
- Temperature Sensor Registers (Address 0x00C Through Address 0x00F)
- Parallel Port Configuration Registers (Address 0x010 Through Address 0x012)
- Enable State Machine (ENSM) Registers (Address 0x013 Through Address 0x017)
- AuxDAC Registers (Address 0x018 Through Address 0x01B)
- Auxiliary ADC Registers (Address 0x01C Through Address 0x01F)
- GPO, AuxDAC, AGC Delay, and Synth Delay Control Registers (Address 0x020 Through Address 0x033)
- SPI Register 0x020—Auto GPO
- SPI Register 0x021—AGC Gain Lock Delay
- SPI Register 0x022—AGC Attack Delay
- SPI Register 0x023—AuxDAC Enable Control
- SPI Register 0x024—Must be x02
- SPI Register 0x025—Must be x02
- SPI Register 0x026—External LNA Control
- SPI Register 0x027—GPO Force and Init
- SPI Registers 0x028 Through 0x02B—GPOn Rx Delay[7:0]
- SPI Register 0x02C Through SPI Register 0x02F—GPOn Tx Delay[7:0]
- SPI Register 0x030 Through SPI Register 0x033—AuxDACn Rx/Tx Delay[7:0]
- Control Output Registers (Address 0x035 Through Address 0x036)
- Product ID Register (Address 0x037)
- Reference Clock Cycles Register (Address 0x03A)
- Digital IO Control Registers (Address 0x03B Through Address 0x03E)
- BBPLL Control Registers (Address 0x03F Through Address 0x04E)
- SPI Register 0x03F—BBPLL Control 1
- SPI Register 0x040—Must be 0
- SPI Register 0x041[D7:D5]—Set to 0
- SPI Register 0x041[D4:D0] Through SPI Register 0x044—Fractional and Integer BB Freq Words
- SPI Register 0x045—Ref Clock Scaler
- SPI Register 0x046—CP Current
- SPI Register 0x047—MCS Scale
- SPI Register 0x048 through SPI Register 0x04A—Loop Filter
- SPI Register 0x04B—VCO Control
- SPI Register 0x04C—Set to 0x86
- SPI Register 0x04D—BBPLL Control 2
- SPI Register 0x04E—BBPLL Control 3
- Power Down Override Registers (Address 0x050 Through Address 0x058)
- SPI Register 0x050—Rx Synth Power Down Override
- SPI Register 0x051—Tx Synth Power Down Override
- SPI Register 0x052—Control 0
- SPI Register 0x053—Must be 0
- SPI Registers 0x054 and 0x055—Rx1 and Rx2 ADC Power Down Override
- SPI Register 0x056—Tx Analog Power Down Override 1
- SPI Register 0x057—Analog Power Down Override
- SPI Register 0x058—Misc Power Down Override
- Overflow Registers (Address 0x05E Through Address 0x05F)
- Chip Level Setup Registers (Address 0x000 Through Address 0x007)
- Transmitter Configuration
- Tx Programmable FIR Filter Registers (Address 0x060 Through Address 0x065)
- Tx Monitor Registers (Address 0x067 Through Address 0x071)
- SPI Register 0x067—Tx Mon Low Gain
- SPI Register 0x068—Tx Mon High Gain
- SPI Register 0x069 and SPIRegister 0x06A[D1:D0]—Tx Mon Delay Counter
- SPI Register 0x06A—Tx Level Threshold
- SPI Register 0x06B Through SPIRegister 0x06D—Tx RSSI n
- SPI Register 0x06E—TPM Mode Enable
- SPI Register 0x06F—Temp Gain Coefficient[7:0] for Tx Mon
- SPI Register 0x070 and SPI Register 0x071—Tx Mon n Config
- Tx Power Control and Attenuation Registers (Address 0x073 Through Address 0x07C)
- Tx Quadrature Calibration Phase, Gain, and Offset Correction Registers (Address 0x08E Through Address 0x09F)
- SPI Register 0x08E—Tx1 Out 1 Phase Corr
- SPI Register 0x08F—Tx1 Out 1 Gain Corr
- SPI Register 0x090—Tx2 Out 1 Phase Corr
- SPI Register 0x091—Tx2 Out 1 Gain Corr
- SPI Register 0x092—Tx1 Out 1 Offset I
- SPI Register 0x093—Tx1 Out 1 Offset Q
- SPI Register 0x094—Tx2 Out 1 Offset
- SPI Register 0x095—Tx2 Out 1 Offset Q
- SPI Register 0x096—Tx1 Out 2 Phase Corr
- SPI Register 0x097—Tx1 Out 2 Gain Corr
- SPI Register 0x098—Tx2 Out 2 Phase Corr
- SPI Register 0x099—Tx2 Out 2 Gain Corr
- SPI Register 0x9A—Tx1 Out 2 Offset I
- SPI Register 0x09B—Tx1 Out 2 Offset Q
- SPI Register 0x09C—Tx2 Out 2 Offset I
- SPI Register 0x09D—Tx2 Out 2 Offset Q
- SPI Register 0x09F—Force Bits
- Tx Quadrature Calibration Configuration Registers (Address 0x0A0 Through Address 0x0AE)
- SPI Register 0x0A0—Quad Cal NCO Freq and Phase Offset
- SPI Register 0x0A1—Quad Cal Control
- SPI Register 0x0A2—Set to 0x7F
- SPI Register 0x0A3—Tx NCO Frequency
- SPI Register 0x0A4—Set to 0xF0
- SPI Register 0x0A5 and SPI Register 0x0A6—Mag Ftest Thresh and Mag Ftest Thresh2
- SPI Register 0x0A7 and SPI Register 0x0A8 Quad Cal Status Tx1 and Tx2
- SPI Register 0x0A9—Set to 0xFF
- SPI Register 0x0AA—Tx Quad Full/LMT Gain
- SPI Register 0x0AB—Must be 0
- SPI Register 0x0AC— Must be 0
- SPI Register 0x0AD— Must be 0
- SPI Register0x 0AE—Tx Quad LPF Gain
- Tx Baseband Filter Registers (Address 0x0C2 Through Address 0x0CC)
- Tx Secondary Filter Registers (Address 0x0D0 Through Address 0x0D3)
- Tx BBF Tuner Configuration Registers (Address 0x0D6 Through Address 0x0D7)
- Receiver Configuration
- Rx Programmable FIR Filter Registers (Address 0x0F0 Through Address 0x0F6)
- Gain Control General Setup Registers (Address 0x0FA Through Address 0x10E)
- SPI Register 0x0FA—AGC Config 1
- SPI Register 0x0FB—AGC Config 2
- SPI Register 0x0FC—AGC Config 3
- SPI Register 0x0FD—Max LMT/Full Gain
- SPI Register 0x0FE—Peak Wait Time
- SPI Register 0x100—Digital Gain
- SPI Register 0x101—AGC Lock Level
- SPI Register 0x103—Gain Step Config 1
- SPI Register 0x104—ADC Small Overload Threshold
- SPI Register 0x105—ADC Large Overload Threshold
- SPI Register 0x106—Gain Step Config 2
- SPI Register 0x107—Small LMT Overload Threshold
- SPI Register 0x108—Large LMT Overload Threshold
- SPI Register 0x109—Rx1 Manual LMT/Full Gain
- SPI Register 0x10A—Rx1 Manual LPF Gain
- SPI Register 0x10B—Rx1 Manual Digital Gain
- SPI Register 0x10C Through SPI Register 0x10E—Manual Gain Registers
- Fast Attack AGC Setup Registers (Address 0x110 Through Address 0x11B)
- SPI Register 0x110—Config 1
- SPI Register 0x111—Config 2 and Settling Delay
- SPI Register 0x112—Energy Lost Threshold
- SPI Register 0x113—Stronger Signal Threshold
- SPI Register 0x114—Low Power Threshold
- SPI Register 0x115—Don’t Unlock Gain if Stronger Signal
- SPI Register 0x116—Final Overrange and Opt Gain
- SPI Register 0x117—Energy Detect Count
- SPI Register 0x118—AGCLL Max Increase
- SPI Register 0x119—Gain Lock Exit Count
- SPI Register 0x11A—Initial LMT Gain Limit
- SPI Register 0x11B—Increment Time[7:0]
- Slow Attack and Hybrid AGC Registers (Address 0x120 Through Address 0x12A)
- SPI Register 0x120—AGC Inner Lower Threshold
- SPI Register 0x121—LMT End Overload Counters
- SPI Register 0x122—ADC Overload Counters
- SPI Register 0x123—Gain Step 1
- SPI Register 0x124 and SPI Register 0x125—Gain Update Counter
- SPI Register 0x128—Digital Sat Counter
- SPI Register 0x129—Outer Power Thresholds
- SPI Register 0x12A—Gain Step 2
- External LNA Gain Word Registers (Address 0x12C Through Address 0x12D)
- AGC Gain Table Registers (Address 0x130 Through Address 0x137)
- Mixer SubTable Registers (Address 0x138 Through Address 0x13F)
- SPI Register 0x138—Mixer Subtable Word Address
- SPI Register 0x139—Mixer Subtable Gain Word Write
- SPI Register 0x13A—Mixer Subtable Bias Word Write
- SPI Register 0x13B—Mixer Subtable Control Word Write
- SPI Register 0x13C Through Register 0x13E—Mixer Subtable Word Reads
- SPI Register 0x13F—Mixer Subtable Config
- Calibration Gain Table Registers (Address 0x140 Through Address 0x144)
- General Calibration Registers (Address 0x145 Through Address 0x149)
- RSSI Measurement Configuration Registers (Address 0x150 Through Address 0x15D)
- Power Word Registers (Address 0x161 Through Address 0x163)
- Rx Quadrature Calibration Registers (Address 0x169 Through Address 0x16B)
- Rx Phase and Gain Correction Registers (Address 0x170 Through Address 0x182)
- SPI Register 0x170—Rx1A Phase Corr
- SPI Register 0x171—Rx1A Gain Corr
- SPI Register 0x172—Rx2A Phase Corr
- SPI Register 0x173—Rx2A Gain Corr
- SPI Register 0x174 and SPI Register 0x175[D1:D0]—Rx1A Q DC Offset
- SPI Register 0x175[D7:D2] and SPI Register 0x176[D3:D0]—Rx1A Offsets
- SPI Register 0x176[D7:D4] and SPI Register 0x177[D5:D0]—Rx2A Q Offset
- SPI Register 0x177[D7:D6] and SPI Register 0x178[D7:D0]—Rx2A I Offset
- SPI Register 0x179 through SPI Register 0x181—B and C Inputs
- SPI Register 0x182—Force Bits
- Rx DC Offset Control Registers (Address 0x185 Through Address 0x194)
- SPI Register 0x185—Wait Count
- SPI Register 0x186—RF DC Offset Count
- SPI Register 0x187—RF DC Offset Config 1
- SPI Register 0x188—RF DC Offset Attenuation
- SPI Register 0x18B—DC Offset Config2
- SPI Register 0x18C—RF Cal Gain Index
- SPI Register 0x18D—RF SOI Threshold
- SPI Register 0x190—BB DC Offset Shift
- SPI Register 0x191—BB DC Offset Fast Settle Shift
- SPI Register 0x192—BB Tracking Fast Settle Dur
- SPI Register 0x193—Must be x3F
- SPI Register 0x194—BB DC Offset Attenuation
- Rx BB DC Offset Registers (Address 0x19A Through Address 0x1A5)
- RSSI Readback Registers (Address 0x1A7 Through Address 0x1AC)
- Rx TIA Registers (Address 0x1DB Through Address 0x1DF)
- Rx BBF Registers (Address 0x1E0 Through Address 0x1F5)
- SPI Register 0x1E0—Rx1 BBF R1A
- SPI Register 0x1E1—Rx2 BBF R1A
- SPI Register 0x1E2—Rx1 Tune Control
- SPI Register 0x1E3—Rx2 Tune Control
- SPI Register 0x1E4—Rx1 BBF R5
- SPI Register 0x1E5—Rx2 BBF R5
- SPI Register 0x1E6—Rx BBF R2346
- SPI Register 0x1E7 and SPI Register 0x1E9—Rx BBF C1 and C2 MSB
- SPI Register 0x1E8 and SPI Register 0x1EA—Rx BBF C1and C2 LSB
- SPI Register 0x1EB—Rx BBF C3 MSB
- SPI Register 0x1EC—Rx BBF C3 LSB
- SPI Register 0x1ED—Rx BBF CC1 Ctr
- SPI Register 0x1EE—Must be 0x60
- SPI Register 0x1EF—Rx BBF CC2 Ctr
- SPI Register 0x1F0—Rx BBF Pow Rz Byte1
- SPI Register 0x1F1—Rx BBF CC3 Ctr
- SPI Register 0x1F2—Rx BBF R5 Tune
- SPI Register 0x1F3—Rx BBF Tune
- SPI Register 0x1F4 and SPI Register 0x1F5—Rx1/Rx2 BBF Man Gain
- Rx BBF Tuner Configuration Registers (Address 0x1F8 Through Address 0x1FC)
- Rx Analog Registers
- Rx Synthesizer Registers (Address 0x230 Through Address 0x251)
- SPI Register 0x230— PFD Config
- SPI Register 0x231, SPI Register 0x232[D2:D0] and SPI Register 0x233 Through SPI Register 0x235—VCO Frequency Words
- SPI Register 0x232
- SPI Register 0x236—Force ALC
- SPI Register 0x237—Force VCO Tune 0
- SPI Register 0x238—Force VCO Tune 1
- SPI Register 0x239—ALC/Varactor
- SPI Register 0x23A—VCO Output
- SPI Register 0x23B—CP Current
- SPI Register 0x23C—CP Offset
- SPI Register 0x23D—CP Config
- SPI Register 0x23E—Loop Filter 1
- SPI Register 0x23F—Loop Filter 2
- SPI Register 0x240—Loop Filter 3
- SPI Register 0x241—Dither/CP Cal
- SPI Register 0x242—VCO Bias 1
- SPI Register 0x243—Must be 0x0D
- SPI Register 0x244—Cal Status
- SPI Register 0x245—Must be 0x00
- SPI Register 0x246—Must be 0x02
- SPI Register 0x247—CP Ovrge/VCO Lock
- SPI Register 0x248—Must be 0x0B
- SPI Register 0x249—VCO Cal
- SPI Register 0x24A—Lock Detect Config
- SPI Register 0x24B—Must be 0x17
- SPI Register 0x24C—Must be 0
- SPI Register 0x24D—Must be 0
- SPI Register 0x250—Must be 0x70
- SPI Register 0x251—VCO Varactor Control 1
- Rx Fast Lock Registers (Address 0x25A Through Address 0x25F)
- Rx LO Generation Register (Address 0x261)
- Tx Synthesizer Registers (Address 0x270 Through Address 0x291)
- DCXO Registers (Address 0x292 Through Address 0x294)
- Tx Synth Fast Lock Registers (Address 0x29A Through Address 0x29F)
- Tx LO Generation Register (Address 0x2A1)
- Master Bias and Band Gap Configuration Registers (Address 0x2A6 and Address 0x2A8)
- Reference Divider Registers (Address 0x2AB and Address 0x2AC)
- Rx Gain Read Back Registers (Address 0x2B0 Through Address 0x2B9)
- Control Register (Register 0x3DF)
- Digital Test Registers (Address 0x3F4 Through Address 0x3F6)
- Rx Synthesizer Registers (Address 0x230 Through Address 0x251)