Micropower Circuits Using The LM4250 Programmable Op Amp AN 0071

User Manual: AN-0071

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National Semiconductor
Application Note 71
George Cleveland
July 1972

INTRODUCTION
The LM4250 is a highly versatile monolithic operational amplifier. A single external programming resistor determines
the quiescent power dissipation, input offset and bias currents, slew rate, gain-bandwidth product, and input noise
characteristics of the amplifier. Since the device is in effect
a different op amp for each externally programmed set current, it is possible to use a single stock item for a variety of
circuit functions in a system.
This paper describes the circuit operation of the LM4250,
various methods of biasing the device, frequency response
considerations, and some circuit applications exercising the
unique characteristics of the LM4250.

Referring to Figure 1 , Q1 and Q2 are high current gain lateral PNPs connected as a differential pair. R1 and R2 provide
emitter degeneration for greater stability at high bias currents. Q3 and Q4 are used as active loads for Q1 and Q2 to
provide high gain and also form a current inverter to provide
the maximum drive for the single ended output into Q5. Q5 is
an emitter follower which prevents loading of the input stage
by the succeeding amplifier stage.
One advantage of this lateral PNP input stage is a common
mode swing to within 200 mV of the negative supply. This
feature is especially useful in single supply operation with
signals referred to ground. Another advantage is the almost
constant input bias current over a wide temperature range.
The input resistance RIN is approximately equal to 2b (RE
a re) where b is the current gain, re is the emitter resistance of one of the input lateral PNPs, and RE is the resistance of one of the 10 kX emitter resistor. Using a DC beta
of 100 and the normal temperature dependent expression
for re gives:

CIRCUIT DESCRIPTION LM4250
The LM4250 has two special features when
other monolithic operational amplifiers. One
externally set the bias current levels of the
the other is the use of PNP transistors as
input pair.

compared with
is the ability to
amplifiers, and
the differential

FIGURE 1. LM4250 Schematic Diagram
C1995 National Semiconductor Corporation

TL/H/7382

RRD-B30M115/Printed in U. S. A.

AN-71

TL/H/7382 – 1

Micropower Circuits Using the LM4250 Programmable Op Amp

Micropower Circuits Using
the LM4250 Programmable
Op Amp

RIN & 2 MX a 2

kT
qlB

grated circuit chip. In applications where the regulation of
the V a supply with respect to the V b supply (as in the case
of tracking regulators) is better than the V a supply with
respect to ground the set resistor should be connected from
Pin 8 to V b. RSET is then:
V a a lVb l b0.5
(4)
RSET e
ISET
The transistor and resistor scheme shown in Figure 3b allows one to switch the amplifier off without disturbing the
main V a and Vb power supply connections. Attaching C1
across the circuit prevents any switching transient from appearing at the amplifier output. The dual scheme shown in
Figure 3c has a constant set current flowing through RS1
and a variable current through RS2. Transistor Q2 acts as an
emitter follower current sink whose value depends on the
control voltage Vc on the base. This circuit provides a meth-

(1)

where lB is input bias current. At room temperature this formula becomes:
RIN & 2 MX a

52 mV
lB

(2)

TL/H/7382–2

FIGURE 2. Input Resistance vs ISET
Figure 2 gives a typical plot of RIN vs Iset derived from the
above equation.
Continuing with the circuit description, Q6 level shifts downward to the base of Q8 which is the second stage amplifier.
Q8 is run as a common emitter amplifier with a current
source load (Q12) to provide maximum gain. The output of
Q8 drives the class B complementary output stage composed of Q15 and Q18.
The bias current levels in the LM4250 are set by the amount
of current (Iset) drawn out of Pin 8. The constant current
sources Q10, Q11, and Q12 are controlled by the amount of
Iset current through the diode connected transistor Q9 and
resistor R9. The constant collector current from Q10 biases
the differential input stage. Therefore, the level Q10 is set at
will control such amplifier characteristics as input bias current, input resistance, and amplifier slew rate. Current
source Q11 biases Q5 and Q6. The current ratio between Q5
and Q6 is controlled by constant current sink Q7. Current
source Q12 sets the currents in diodes Q13 and Q14 which
bias the output stage to the verge of conduction thereby
eliminating the dead zone in the class B output. Q12 also
acts as the load for Q8 and limits the drive current to Q15.
The output current limiting is provided by Q16 and Q17 and
their associated resistors R16 and R17. When enough current is drawn from the output, Q16 turns on and limits the
base drive of Q15. Similarly Q17 turns on when the LM4250
attempts to sink too much current, limiting the base drive of
Q18 and therefore output current. Frequency compensation
is provided by the 30 pF capacitor across the second stage
amplifier, Q8, of the LM4250. This provides a 6 dB per octave rolloff of the open loop gain.

TL/H/7382 – 4

TL/H/7382 – 3

3b

3a

TL/H/7382 – 5

TL/H/7382 – 6

3c
3d
FIGURE 3. Biasing Schemes
od of varying the amplifier’s characteristics over a limited
range while the amplifier is in operation. The FET circuit
shown in Figure 3d covers the full range of set currents in
response to as little as a 0.5V gate potential change on a
low pinch-off voltage FET such as the 2N3687. The limit
resistor prevents excessive current flow out of the LM4250
when the FET is fully turned on.

BIAS CURRENT SETTING PROCEDURE
The single set resistor shown in Figure 3a offers the most
straightforward method of biasing the LM4250. When the
set resistor is connected from Pin 8 to ground the resistance
value for a given set current is:

FREQUENCY RESPONSE OF A
PROGRAMMABLE OP AMP
This section provides a method of determining the sine and
step voltage response of a programmable op amp. Both the
sine and step voltage responses of an amplifier are modified
when the rate of change of the output voltage reaches the
slew rate limit of the amplifier. The following analysis devel-

V a b0.5
(3)
ISET
The 0.5 volts shown in Equation 3 is the voltage drop of the
master bias current diode connected transistor on the inteRSET e

2

ops the Bode plot as well as the small signal and slew rate
limited responses of an amplifier to these two basic categories of waveforms.
SMALL SIGNAL SINE WAVE RESPONSE

VO e Vp sin 2qf t

(6)

d VO
e 2q f Vp cos 2q f t
dt

(7)

À

The key to constructing the Bode plot for a programmable
op amp is to find the gain bandwidth product, GBWP, for a
given set current. Quiescent power drain, input bias current,
or slew rate considerations usually dictate the desired set
current. The data sheet curve relating GBWP to set current
provides the value of GBWP which when divided by one
yields the unity gain crossover of fu. Assuming a set current
of 6 mA gives a GBWP of 200,000 Hz and therefore an fu of
200 kHz for the example shown in Figure 4 . Since the device has a single dominant pole, the rolloff slope is b20 dB
of gain per decade of frequency (b6 dB/octave). The dotted line shown on Figure 4 has this slope and passes

d VO
e 2q f Vp
dt teo

(8)

Sr e 2q fMAX VP

(9)

where:
VO e output voltage
Vp e peak output voltage
d VO
Sr e maximum
dt
The maximum sine wave frequency an amplifier with a given
slew rate will sustain without causing the output to take on a
triangular shape is therefore a function of the peak amplitude of the output and is expressed as:
Sr
(10)
2q Vp
Figure 5 shows a quick reference graphical presentation of
this formula with the area below any Vpeak line representing
an undistorted small signal sine wave response for a given
frequency and amplifier slew rate and the area above the
Vpeak line representing a distorted sine wave response due
to slew rate limiting for a sine wave with the given Vpeak.
fMAX e

TL/H/7382 – 7

FIGURE 4. Bode Plot
through the 200 kHz fu point. Arbitrarily choosing an inverting amplifier with a closed loop gain magnitude of 50 determines the height of the 34 dB horizontal line shown in Figure 4 . Graphically finding the intersection of the sloped line
and the horizontal line or mathematically dividing GBWP by
50 determines the 3 dB down frequency of 4 kHz for the
closed loop response of this amplifier configuration. Therefore, the amplifier will now apply a gain of b50 to all small
signal sine waves at frequencies up to 4 kHz. For frequencies above 4 kHz, the gain will be as shown on the sloped
portion of the Bode plot.

TL/H/7382 – 8

FIGURE 5. Frequency vs Slew Rate Limit vs Peak
Output Voltage
Large signal step voltage changes at the output will have a
rise time as shown in equation 5 until a signal with a rate of
output voltage change equal to the slew rate of the amplifier
occurs. At this point the output will become a ramp function
with a slope equal to Sr. This action occurs when:
Vstep
(11)
Sr s
tr

SMALL SIGNAL STEP INPUT RESPONSE
The amplifier’s response to a positive step voltage change
at the input will be an exponentially rising waveform whose
rise time is a function of the closed loop 3 dB down bandwidth of the amplifier. The amplifier may be modeled as a
single pole low pass filter followed by a gain of 50 wideband
amplifier. From basic filter theory*, the 10% to 90% rise
time of a single pole low pass filter is:
0.35
(5)
f3 dB
For the example shown in Figure 4 the 4 kHz 3 dB down
frequency would give a rise time of 87.5 ms.
tr e

SLEW RATE LIMITED LARGE SIGNAL RESPONSE
The final consideration, which determines the upper speed
limitation on the previous two types of signal responses, is
the amplifier slew rate. The slew rate of an amplifier is the
maximum rate of change of the output signal which the amplifier is capable of delivering. In the case of sinosoidal signals, the maximum rate of change occurs at the zero crossing and may be derived as follows:

TL/H/7382 – 9

*See reference.

FIGURE 6. Slew Rate vs Rise Time vs Step Voltage
3

Figure 6 graphically expresses this formula and shows the
maximum amplitude of undistorted step voltage for a given
slew rate and rise time. The area above each step voltage
line represents the undistorted low pass filter type response
mode of the amplifier. If the intersection of the rise time and
slew rate values of a particular amplifier configuration falls
below the expected step voltage amplitude line, the rise
time will be determined by the slew rate of the amplifier. The
rise time will then be equal to the amplitude of the step
divided by the slew rate Sr.

The 3 dB down (gain of b7.07) frequency observed for this
configuration was approximately 300 Hz which agrees fairly
closely with the 3.5 kHz GBWP divided by 10 taken from an
extrapolation of the data sheet typical GBWP versus set
current curve.
Peak-to-peak output voltage swing into a 100 kX load is
0.7V or g 0.35V peak. An increase in supply voltage to
g 1.35V such as delivered by a pair of mercury cells directly
increases the output swing by g 0.35V to 1.4V peak-topeak. Although this increases the power dissipation to approximately 1 mW per battery, a power drain of 15 mW or
less will not affect the shelf life of a mercury cell.

FULL POWER BANDWIDTH
The full power bandwidth often found on amplifier specification sheets is the range of frequencies from zero to the
frequency found at the intersection on Figure 5 of the maximum rated output voltage and the slew rate Sr of the amplifier. Mathematically this is:
Sr
(12)
2q Vrated
The full power bandwidth of a programmable amplifier such
as the LM4250 varies with the master bias set current.
The above analysis of sine wave and step voltage amplifier
responses applies for all single dominant pole op amps
such as the LM101A, LM1107, LM108A, LM112, LM118,
and LM741 as well as the LM4250 programmable op amp.
ffull power e

500 MANO-WATT X10 AMPLIFIER
The X10 inverting amplifier shown in Figure 7 demonstrates
the low power capability of the LM4250 at extremely low
values of supply voltage and set current. The circuit draws
260 nA from the a 1.0V supply of which 50 nA flows
through the 12 MX set resistor. The current into the b1.0V
supply is only 210 nA since the set resistor is tied to ground
rather than Vb. Total quiescent power dissipation is:
PD e (260 nA) (1V) a (210 nA) (1V)
(13)
PD e 470 nW
(14)
The slew rate determined from the data sheet typical performance curve is 1 V/ms for a .05 mA set current. Samples
of actual values observed were 1.2 V/ms for the negative
slew rate and 0.85 V/ms for the positive slew rate. This
difference occurs due to the non-symmetry in the current
sources used for charging and discharging the internal 30
pF compensation capacitor.

TL/H/7382 – 10

FIGURE 7. 500 nW x 10 Amplifier
MICRO-POWER MONITOR WITH HIGH CURRENT
SWITCH

Figure 8 shows the combination of a micro-power comparator and a high current switch run from a separate supply.
This circuit provides a method of continuously monitoring an
input voltage while dissipating only 100 mW of power and
still being capable of switching a 500 mA load if the input
exceeds a given value. The reference voltage can be any
value between a 8.5V and b8.5V. With a minimum gain of
approximately 100,000 the comparator can resolve input
voltage differences down into the 0.2 mV region.

TL/H/7382 – 11

FIGURE 8. m –Power Comparator with
High Current Switch
4

The bias current for the LM4250 shown in Figure 8 is set at
0.44 mA by the 200 MX Rset resistor. This results in a total
comparator power drain of 100 mW and a slew rate of approximately 11 V/ms in the positive direction and 12.8 V/ms
in the negative direction. Potentiometer R1 provides input
offset nulling capability for high accuracy applications.
When the input voltage is less than the reference voltage,
the output of the LM4250 is at approximately b9.5V causing diode D1 to conduct. The gate of Q1 is held at b8.8V by
the voltage developed across R3. With a large negative voltage on the gate of Q1 it turns off and removes the base
drive from Q2. This results in a high voltage or open switch
condition at the collector of Q2. When the input voltage exceeds the reference voltage, the LM4250 output goes to
a 9.5V causing D1 to be reverse biased. Q1 turns on as
does Q2, and the collector of Q2 drops to approximately 1V
while sinking the 500 mA of load current.
The load denoted as ZL can be resistor, relay coil, or indicator lamp as required; but the load current should not exceed
500 mA. For V a values of less than 15V and IL values of
less than 25 mA both Q2 and R2 may be omitted. With only
the 2N4860 JFET as an output device the circuit is still capable of driving most common types of indicator lamps.

THE COMPLETE NANOAMMETER
The complete meter amplifier shown in Figure 10 is a differential current-to-voltage converter with input protection, zeroing and full scale adjust provisions, and input resistor balancing for minimum offset voltage. Resistor R’f (equal in
value to Rf for measurements of less than 1 mA) insures
that the input bias currents for the two input terminals of the
amplifier do not contribute significantly to an output error
voltage. The output voltage Vo for the differential current-tovoltage converter is equal to b2 IfRf since the floating input
current IIN must flow through Rf and R’f. R’f may be omitted

IC METER AMPLIFIER RUNS ON TWO FLASHLIGHT
BATTERIES
Meter amplifiers normally require one or two 9V transistor
batteries. Due to the heavy current drain on these supplies,
the meters must be switched to the OFF position when not
in use. The meter circuit described here operates on two
1.5V flashlight batteries and has a quiescent power drain so
low that no ON-OFF switch is needed. A pair of Eveready
No. 950 ‘‘D’’ cells will serve for a minimum of one year
without replacement. As a DC ammeter, the circuit will provide current ranges as low as 100 nA full-scale.
The basic meter amplifier circuit shown in Figure 9 is a current-to-voltage converter. Negative feedback around the
amplifier insures that currents IIN and If are always equal,
and the high gain of the op amp insures that the input voltage between Pins 2 and 3 is in the microvolt region. Output

TL/H/7382 – 13

TL/H/7382 – 14

FIGURE 10. Complete Meter Amplifier
Resistance Values for
DC Nano and Micro Ammeter
I FULL SCALE

Rf [X]

R’f [X]

100 nA
500 nA
1 mA
5 mA
10 mA
50 mA
100 mA

1.5M
300k
300k
60k
30k
6k
3k

1.5M
300k
0
0
0
0
0

for Rf values of 500 kX or less, since a resistance of this
value contributes an error of less than 0.1% in output voltage. Potentiometer R2 provides an electrical meter zero by
forcing the input offset voltage Vos to zero. Full scale meter
deflection is set by R1. Both R1 and R2 only need to be set
once for each op amp and meter combination. For a 50
microamp 2 kX meter movement, R1 should be about 4 kX
to give full scale meter deflection in response to a 300 mV
output voltage. Diodes D1 and D2 provide full input protection for overcurrents up to 75 mA.
With an Rf resistor value of 1.5M the circuit in Figure 10
becomes a nanommeter with a full scale reading capability

TL/H/7382 – 12

FIGURE 9. Basic Meter Amplifier
voltage Vo is therefore equal to bIfRf. Considering the
g 1.5V sources ( g 1.2V end-of-life) a practical value of Vo
for full scale meter deflection is 300 mV. With the master
bias-current setting resistor (Rs) set at 10 MX, the total quiescent current drain of the circuit is 0.6 mA for a total power
supply drain of 1.8 mW. The input bias current, required by
the amplifier at this low level of quiescent current, is in the
range of 600 pA.

5

of 100 nA. Reducing Rf to 3 kX in steps, as shown in Figure
10 increases the full scale deflection to 100 mA, the maximum for this circuit configuration. The voltage drop across
the two input terminals is equal to the output voltage Vo
divided by the open loop gain. Assuming an open loop gain
of 10,000 gives an input voltage drop of 30 mV or less.

A 10 mV TO 100V FULL-SCALE VOLTMETER
A resistor inserted in series with one of the input leads of
the basic meter amplifier converts it to a wide range voltmeter circuit, as shown in Figure 12 . This inverting amplifier has
a gain varying from b30 for the 10 mV full scale range to
b 0.003 for the 100V full scale range. Figure 12 also lists
the proper values of Rv, Rf, and R’f for each range. Diodes
D1 and D2 provide complete amplifier protection for input
overvoltages as high as 500V on the 10 mV range, but if
overvoltages of this magnitude are expected under continuous operation, the power rating of Rv should be adjusted
accordingly.

CIRCUIT FOR HIGHER CURRENT READINGS
For DC current readings higher than 100 mA, the inverting
amplifier configuration shown in Figure 11 provides the required gain. Resistor RA develops a voltage drop in response to input current IA. This voltage is amplified by a
factor equal to the ratio of Rf/RB. RB must be sufficiently
larger than RA, so as not to load the input signal. Figure 11
also shows the proper values of RA, RB and Rf for full scale
meter deflections of from 1 mA to 10A.

Resistance Values for a DC Voltmeter

Resistance Values for DC Ammeter
I FULL SCALE

RA [X]

RB [X]

Rf [X]

1 mA
10 mA
100 mA
1A
10A

3.0
.3
.3
.03
.03

3k
3k
30k
30k
30k

300k
300k
300k
300k
30k

V FULL SCALE

RV [X]

Rf [X]

R’f [X]

10 mV
100 mV
1V
10V
100V

100k
1M
10M
10M
10M

1.5M
1.5M
1.M
300k
30k

1.5M
1.5M
1.5M
0
0

TL/H/7382 – 16

TL/H/7382–15

FIGURE 12. Voltmeter

FIGURE 11. Ammeter

6

TL/H/7382 – 17

FIGURE 13. Pulse Generator
The output buffer Q1 presents a constant load to the op
amp output thereby preventing frequency variations caused
by VHIGH and VLOW voltages changing as a function of load
current. The output of Q1 will interface directly with a standard TTL or DTL logic device. Reversing diode D1 will invert
the polarity of the generator output providing a series of
negative going pulses dropping from a 5V to the saturation
voltage of Q1.

LOW FREQUENCY PULSE GENERATOR USING A
SINGLE a 5V SUPPLY
The variable frequency pulse generator shown in Figure 13
provides an example of the LM4250 operated from a single
supply. The circuit is a buffered output free running multivibrator with a constant width output pulse occurring with a
frequency determined by potentiometer R2.
The LM4250 acts as a comparator for the voltages found at
the upper plate of capacitor C1 and at the reference point
denoted as Vr on Figure 13 . Capacitor C1 charges and discharges with a peak-to-peak amplitude of approximately 1V
determined by the shift in reference voltage Vr at Pin 3 of
the op amp. The charge path of C1 is from the amplifier
output, which is at its maximum positive voltage VHIGH (approximately V a b0.5V), through R1 and through the potentiometer R2. Diode D1 is reverse biased during the charge
period. When C1 charges to the Vr value determined by the
net result of VHIGH through resistor R5 and V a through the
voltage divider made up of resistors R3 and R4 the amplifier
swings to its lower limit of approximately 0.5V causing C1 to
begin discharging. The discharge path is through the forward biased diode D1, through resistor R1, and into Pin 6 of
the op amp. Since the impedance in the discharge path
does not vary for R2 settings of from 3 kX to 5 MX, the
output pulse maintains a constant pulse width of 41 ms
g 1.5 ms over this range of potentiometer settings. Figure
14 shows the output pulse frequency variation from 6 kHz
down to 360 Hz as R2 places from 100 kX up to 5 MX of
additional resistance in the charge path of C1. Setting R2 to
zero ohms will short out diode D1 and cause a symmetrical
square wave output at a frequency of 10 kHz. Increasing the
value of C1 will lower the range of frequencies available in
response to the R2 variation shown on Figure 14 . Electrolytic capacitors may be used for the larger values of C1 since it
has only positive voltages applied to it.

TL/H/7382 – 18

FIGURE 14. Pulse Frequency vs R2
The change in output frequency as a function of supply voltage is less than g 4% for a V a change of from 4V to 10V.
This stability of frequency versus supply voltage is due to
the fact that the reference voltage Vr and the drive voltage
for the capacitor are both direct functions of V a .
The power dissipation of the free running multivibrator is
300 mW and the power dissipation of the buffer circuit is
approximately 5.8 mW.

7

Note 1: Quiescent PD e 10 mW
Note 2: R2, R3, R4, R5, R6 and R7 are 1% resistors
Note 3: R11 and C1 are for DC and AC common mode rejection adjustments

TL/H/7382 – 19

FIGURE 15. c 100 Instrumentation Amplifier

X100 INSTRUMENTATION AMPLIFIER
The instrumentation amplifier circuit shown in Figure 15 has
a full differential input center tapped to ground. With the
bias current set at approximately 0.1 mA, the impedance
looking into either VIN1 or VIN2 is 100 MX with respect to
ground, and the input bias current at either terminal is 0.2
nA. The two non-inverting input stages A1 and A2 apply a
gain of 10 to the input signal, and the differential output
stage applies an additional gain of b10 for a net amplifier
gain of b100:
VO e b100(VIN1 b VIN2).
(15)
The entire circuit can run from two 1.5V batteries connected
directly (no power switch) to the V a and Vb terminals. With
a total current drain of 2.8 mA the quiescent power dissipation of the circuit is 8.4 mW. This is low enough to have no
significant effect on the shelf life of most batteries.
Potentiometer R11 provides a means for matching the gains
of A1 and A2 to achieve maximum DC common mode rejection ratio CMRR. With R11 adjusted to its null point for DC
common mode rejection the small AC CMRR trimmer capacitor C1 will normally give an additional 10 to 20 dB of
CMRR over the operating frequency range. Since C1 actually balances wiring capacitance rather than amplifier frequency characteristics, it may be necessary to attach it to
Pin 2 of either A1 or A2 as required. Figure 16 shows the
variation of CMRR (referred to the input) with frequency for
this configuration. Since the circuit applies a gain of 100 or
40 dB to an input signal, the actual observed rejection ratio

TL/H/7382 – 20

FIGURE 16. AV and CMRR vs Frequency
is the difference between the CMRR curve and AV curve.
For example, a 60 Hz common mode signal will be attenuated by 67 dB minus 40 db or 27 dB for an actual rejection
ratio of VIN/VO equal to 22.4.
The maximum peak-to-peak output signal into a 100 kX
load resistor is approximately 1.8V. With no input signal, the
noise seen at the output is approximately 0.8 mVRMS or
8 mVRMS referred to the input. When doing power dissipation measurements on this circuit, it should be kept in mind
that even a 1 MX oscilloscope probe placed between
a 1.5V and b 1.5V will more than double the power drawn
from the batteries.

8

2N registration such as 2N3252 has a BVEBO at 10 mA
specified as 5.5V minimum, 6.5V typical, and 7.0V maximum. Using a diode connected 2N3252 as a reference, the
regulator output voltage changed 78 mV in response to an
8V to 36V change in the input voltage. This test was done
under both no load and full load conditions and represents a
line regulation of better than 1.6%.
A load change from 10 mA to 50 mA caused a 1 mV change
in output voltage giving a load regulation value of 0.05%.
When operating the regulator at load currents of less than
25 mA, no heat sink is required for Q1. For load currents in
excess of 50 mA, Q1 should be replaced by a Darlington
pair with the 2N3019 acting as a driver for a higher power
device such as a 2N3054.

5V REGULATOR FOR CMOS LOGIC CIRCUITS
The ideal regulator for low power CMOS logic elements
should dissipate essentially no power when the CMOS devices are running at low frequencies, but be capable of delivering full output power on demand when the CMOS devices are running in the 0.1 MHz to 10 MHz region. With a 10V
input voltage, the regulator shown in Figure 17 will dissipate
350 mW in the stand-by mode but will deliver up to 50 mA of
continuous load current when required.
The circuit is basically a boosted output voltage-follower referenced to a low current zener diode. The voltage divider
consisting of R2 and R3 provides a 5V tap voltage from the
6.5V reference diode to determine the regulator output.
Since a standard 6.5V zener diode does not exhibit good
regulation in the 2 mA to 60 mA reverse current region, Q2
must be a special device. An NPN transistor with its collector and base terminals grounded and its emitter tied to the
junction of R1 and R2 exhibits a well-controlled base emitter
reverse breakdown voltage. A National Semiconductor process 25 small signal NPN transistor sorted to a

REFERENCES
Millman, J. and Halkias, C.C.: ‘‘Electronic Device and Circuits,’’ pp. 465 – 466, McGraw-Hill Book Company, New
York, 1967.

TL/H/7382 – 21

FIGURE 17. 350 mW Quiescent Drain 5 Volt Regulator

9

Micropower Circuits Using the LM4250 Programmable Op Amp
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AN-71

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Fax: 81-043-299-2408

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.



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File Type                       : PDF
File Type Extension             : pdf
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PDF Version                     : 1.3
Linearized                      : Yes
Create Date                     : 1995:10:18 19:35:40
Producer                        : Acrobat Distiller 2.0 for Windows
Title                           : Micropower Circuits Using the LM4250 Programmable Op Amp
Subject                         : AN-71
Author                          : 
Keywords                        : Application Notes, Operational
Modify Date                     : 2001:04:23 19:28:22+05:30
Page Count                      : 10

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