Signed Integer Arithmetic On The HPC AN 0603

User Manual: AN-0603

Open the PDF directly: View PDF PDF.
Page Count: 12

TL/DD10395
Signed Integer Arithmetic on the HPC AN-603
National Semiconductor
Application Note 603
Raj Gopalan
July 1989
Signed Integer Arithmetic
on the HPCTM
This report describes the implementation of signed integer
arithmetic operations on the HPC. HPC hardware support
for unsigned arithmetic operation. In order to support signed
integer arithmetic operations on the HPC, the user can rep-
resent negative numbers in two’s complement form and
perform the signed arithmetic operations explicitly through
software.
The following signed integer arithmetic routines are imple-
mented in the package:
Multiplication:
16 by 16 yielding 16-bit result
32 by 32 yielding 32-bit result
Division:
16 by 8 yielding 16-bit quotient and 16-bit remainder
32 by 16 yielding 16-bit quotient and 16-bit remainder
32 by 32 yielding 16-bit quotient and 16-bit remainder
Addition:
16 by 16 yielding 16-bit
Subtraction:
16 by 16 yielding 16-bit
Comparison:
16 by 16 for greater to, less than or equal to.
REPRESENTATION OF NEGATIVE NUMBERS:
For binary numbers, negative numbers are represented in
two’s complement form. In this system, a number is positive
if the MSB is 0, negative if it is 1.
The decimal equivalent of two’s complement number is
computed the same as for an unsigned number, except that
weight of the MSB is b2**nb1 instead of a2**nb1.
The range of representable numbers is b(2**nb1)
through a(2**nb1b1).
The two’s complement of a binary number is obtained by
complementing its individual bits and adding one to it.
The advantage of representing a negative number in two’s
complement form is that addition and subtraction can be
done directly using unsigned hardware.
.title SIMUSL
.sect code,rom8,byte,rel
;Signed multiply (16 by 16)
; B Multiplicand
; A Multiplier
; X;A return
;
.public signed mult 16
.local
signed mult 16:
st a,0.w
mult a,b ;do unsigned multiplication.
sc
ifbit 7,(1).b ;if multiplier is negative
subc x,b
sc
ifbit 7,(Ba1).b ;if multiplicand is negative
subc x,0.w
$exit:
ret
.endsect
HPCTM is a trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
MULTIPLICATION
Method 1:
Signed multiplication can be achieved by taking care of the
signs and magnitudes of the multiplicand and multiplier sep-
arately.
Perform the multiplication on the magnitudes alone.
The sign of the result can be set based on the signs of the
multiplier and the multiplicand.
Method 2:
This method does not require finding the magnitude of the
operands. Multiplication can be done using unsigned hard-
ware on the two’s complement numbers. The result will be
signed based on the signs of the operands.
The algorithm is as follows:
Step 1. Result eop1 *op2
Step 2. If op1 k0 then subtract op2 from upper half of the
result.
Step 3. If op2 k0 then subtract op1 from upper half of the
result.
Now the Result will yield the correct value of the multiplica-
tion on two’s complement numbers.
Method 3:
By sign extending the multiplier and multiplicand to the size
of the result one can always obtain the correct result of
signed multiplication using unsigned multiplication.
.title SIMULL
.sect code,rom8,byte,rel
;Multiply (Signed or Unsigned are the same)
;32 bit
; K:A Multiplicand
;14:6[SP]Multiplier
; K:A return
;
.public multiply 32
.local
multiply 32:
push x ;(Argument now at 16:8[SP])
st a,0.w
ld a,k ;Multiply hi reg*lo stack
mult a,18[sp].w
x a,0.w ;hold, retrieve lo reg
push a ;(argument now at 18:10[SP])
mult a18[sp].w ;Multiply lo reg*hi stack
add 0.w,a ;add into hi partial
pop a ;(Argument now at 16:8[SP])
mult a,18[sp].w ;Multiply lo reg*lo stack
add x,0.w ;add in hi partial
ld k,x ;Position
pop x ;Restore
ret
.endsect
2
DIVISION
Similar to multiplication method 1, one can perform the division on the magnitudes of the dividend and divisor.
The sign of the quotient can be set based on the signs of the dividend and the divisor.
The sign of the remainder will be same as the dividend.
.title SIDVSS
.sect code,rom8,byte,rel
;Division & Remainder
;16,8 bit (signed only, unsigned uses inline code)
; A Dividend
;14[SP]Divisor
; A return
;
.public signed divide 8,signed remainder 8
.public signed divide 16,signed remainder 16
.local
signed divide 8:
jsr $shared 8 ;Uses shared routine
ret
;
signed remainder 8:
jsr $shared 8 ;Uses shared routine
ld a,k ;Return remainder
ret
;
$shared 8:
ifgt a,#0x7f
or a,#0xff00
st a,k ;Get arguments
ld a,16[sp].w
ifgt a,#0x7f
or a,#0xff00
jp $shared
;
signed divide 16:
jsr $shared 16 ;Uses shared routine
ret
;
signed remainder 16:
jsr $shared 16 ;Uses shared routine
ld a,k ;Return remainder
ret
;
$share 16:
st a,k ;Get arguments
ld a,16[sp].w
$shared
ifeq a,#0
ret ;division by zero
push x
ifgt a,#0x7fff
jp $unknown negative ;unknown/negative
x a,k
ifgt a,#0x7fff
jp $negative positive ;negative/positive
div a,k ;Positive/positive is plus,plus
jp $positive positive
3
$unknown negative: ;Unknown/negative
comp a
inc a
x a,k
ifgt a,#0x7fff
jp $negative negative ; negative/negative
div a,k ;Positive/negative is minus,plus
comp a
inc a
$positive positive:
ld k,x
jp $exit
$negative positive: ;Negative/positive is minus,minus
comp a
inc a
div a,k
comp a
inc a
jp $negate remainder
$negative negative: ;Negative/negative is plus,minus
comp a
inc a
div a,k
$negate remainder:
x a,x
comp a
inc a
st a,k
ld a,x
$exit:
pop x
ret
.endsect
4
.title SIDVLS
.sect code,rom8,byte,rel
;Division & Remainder
;Signed 32 by 16 divide
; X;A Dividend
; K Divisor
; X,A return (remainder and quotient)
;
.public signed div 32
.local
signed div 32:
sc
ifeq k,#0
ret ;Divide by zero, set carry and return
$shared signed:
ifbit 7,x01.b
jp $negative dividend
jsr $process divisor ;Skipping return
ret ;0/040,0
$negate quotient:
comp a
inc a
ret ;0/14 1,0
$negative dividend;
comp a
add a,#01
x a,x
comp a
adc a,#0
x a,x
jsr $process divisor ;skipping return
jsr $negate quotient ;1/041,1
$negate remainder: ;1/140,1
x a,x
comp a
inc a
x a,x
ret
$process divisor:
ifbit 7,k01.b
jp $negative divisor
divd a,k ;?/0
ret
$negative divisor:
x a,k
comp a
inc a
x a,k
divd a,k ;?/1
retsk
.endsect
5
.title SUDVLL
.sect code,rom8,byte,rel
;Division & Remainder
;Signed 32 by 32 Divide
; K:A Dividend
;14:6[SP]Divisor
; K:A return
;
;Stack frame as built and used consists of
;top:
; 0, initial subtrahend hi /dividend shifts into subtrahend
; 0, initial subtrahend lo /becomes remainder
; k, dividend hi /dividend shifts into subtrahend, and
; a, dividend lo /quotient shifts into dividend
; b preserved
; x preserved
; return address
; sp-4 12, divisor hi
; sp-6 12, divisor lo
;Sign flag (0 4negative, 1 4positive, for test sense at exit)
;bit 0, divisor sign (1 4negative)
;bit 1, dividend sign (1 4positive)
;Inc of flag causes bit 1 4(bit 1 xor bit 0) by carry/nocarry out of bit 0
;so that two positives (010) or two negatives (001) indicate a positive
;quotient (011 or 010) in bit 1. Bit 1 always indicates sign if remainder.
;Operation is indicated by bit 3 of the flag, 1 4remainder.
;
.public signed divide 32, signed remainder 32
.public unsigned divide 32, unsigned remainder 32
.local
signed divide 32:
ld 1.b,#0x02
jp $shared signed
;
signed remainder 32:
ld 1.b,#0x0a
$shared signed:
ifbit 7,k01.b ;Check dividend
jsr $negate ;Negate dividend and note sign
ifbit 7,1603[sp].b ;Check divisor
jp $negate divisor
jmp $shared
;
$negate divisor:
xa,16[sp].w ;Negate divisor and note sign
comp a
add a,#1
xa,16[sp].w
xa,14[sp].w
comp a
adc a,#0
xa,14[sp].w
sbit 0,1.b
jp $shared
;
unsigned divide 32:
ld 1.b,#0x02
jp $shared
;
unsigned remainder 32:
ld 1.b,#0x0a
6
$shared:
push x ;Preserve registers
push b
ld b,sp ;Place dividend, becomes quotient
push a
push k
ld x,sp ;Set subtrahend, becomes remainder
clr a
push a
push a
ld k,#118 ;Access divisor argument
add k,sp
ld a,[k].w
or a,2[k].w
ifeq a,#0
jmp $zero ;division by zero
ld 0.b,#32 ;Set counter
$loop:
ld a,[b].w ;Shift Dividend:Quotient
shl a
xs a,[b0].w
nop
ld a,[b].w
rlc a
xs a,[b1].w
nop
ld a,[x].w
rlc a
xa,[x0].w
ld a,[x].w
rlc a
xa,[x1].w
ifc
jp $subtract ;Carry out 1dividend divisor
sc ;Check for dividend divisor
ld a,[x0].w
subc a,[k].w
ld a,[x1].w
subc a,2[k].w
ifnc
jp $count ;dividend divisor
$subtract:
ld a,[x].w ;Subtract out divisor (c is set)
subc a,[k].w
xa,[x0].w
ld a,[x].w
subc a,2[k].w
xa,[x1].w
sbit 0,[b].b ;Set quotient bit
$count:
decsz 0.b ;Count 32 shifts
jmp $loop
$zero:
pop k ;Get Remainder and/or Quotient
pop a ;and clear working off stack
pop x
pop b
ifbit 3,1.b
jp $exit ;want remainder, have it
ld a,b ;Want Quotient
ld k,x
inc 1.b ;Divisor’s sign Xors Dividend’s
7
$exit:
pop b ;Restore registers
pop x
ifbit 1,1.b
ret ;positive result
$negate:
comp a ;Negate K:A
add a,#1
x a,k
comp a
adc a,#0
x a,k
rbit 1,1.b ;Note sign (for entrance)
ret
.endsect
8
ADDITION
Two’s complement numbers can be added by ordinary binary addition, ignoring any carries beyond the MSB. The result will
always be the correct sum as long as the result doesn’t exceed the range.
If the result is the same as for the subtrahend, then overflow has occurred.
.title SIADD
.sect code,rom8,byte,rel
;Signed add (16 by 16)
; A Operand1
; B Operand2
; Carry Return
.public sign add
.local
sign add:
ld 0.b,#00
ifbit 7,(A01).b
inc 0.b
ifbit 7,(B01).b
inc 0.b
;if bit 0 of 0.b 41 then op1 and op2 have different sign
;if bit 0 of 0.b 40 then op1 and op2 sign are same
;then if bit 1 of 0.b 40 both operands are positive
;else both operands are negative.
add a,b ;Perform unsigned addition
rc
ifbit 0,0.b ;both operands are different sign
ret
ifbit 1,0.b ;both op1 and op2 are negative
jp $negatives
$positives: ;both op1 and op2 are positive
ifbit 7,(A01).b ;if result sign is negative then
set overflow bit
sc ;overflow
ret
$negatives:
ifbit 7,(A01).b ;if sign bit of result is
negative, then no overflow
ret
sc ;overflow
$exit:
ret
.endsect
9
SUBTRACTION
Subtraction can be achieved by negating the subtrahend and perform the addition operation.
Overflow can be detected as mentioned before by checking the signs of minuhend and the negation of the subtrahend and that
of the sum.
.title SISUB
.sect code,rom8,byte,rel
;Signed subtract (16 by 16)
; B Operand1
; A Operand2
; Carry,A Return
.public sign sub
.local
sign sub:
ld 0.b,#00 ;initialize sign flags
ifbit 7,(B01).b
inc 0.b
$negate A:
comp A
inc A
$ngative comp A:
ifbit 7,(A01).b
inc 0.b
;if bit 0 of 0.b 41 then op1 and op2 have different sign
;if bit 0 of 0.b 40 then op1 and op2 sign are same
;then if bit 1 of 0.b 40 both operands are positive
;else both operands are negative.
add A,B ;Perform unsigned addition
rc
ifbit 0,0.b ;both operands are different sign
ret
ifbit 1,0.b ;both op1 and op2 are negative
jp $negatives
$positives: ;both op1 and op2 are positive
if bit 7, (A01).b ;if result sign is negative then
set overflow bit
sc ;bit 0 of byte 0.b is set to
indicate overflow
ret
$negatives:
ifbit 7, (A01).b ;if sign bit of result is
negative, then no overflow
ret
sc ;sign bit of result is positive,
hence overflow.
$exit:ret
.endsect
10
.title NSISUB
.sect code,rom8,byte,rel
;Signed sub (16 by 16)
; A Operand1
; B Operand2
; Carry Return
.public sign sub
.local
sign sub:
ld 0.b,#00
ifbit 7,(A01).b
inc 0.b
ifbit 7,(B01).b
inc 0.b
;if bit 0 of 0.b 41 then op1 and op2 have different sign
;if bit 0 of 0.b 40 then op1 and op2 sign are same
;then if bit 1 of 0.b 40 both operands are positive
;else both operands are negative.
sc
subc a,b ;Perform unsigned addition
rc
ifbit 0,0.b ;both operands are different sign
jp $chkovf
ret ;both operands are same sign,
can’t produce overflow
$chkovf:
ifbit 7,(B01).b
jp $negminu
$posminu:
ifbit 7,(A01).b
sc
ret
$negminu:
ifbit 7,(A01).b
sc
ret
.endsect
11
AN-603 Signed Integer Arithmetic on the HPC
COMPARISON
To do signed comparison on n bit two’s complement numbers first add 2**(n b1) to the numbers. This will basically shift
the numbers from b(2**nb1) to a(2**nb1b1) range to 0 to 2**nb1.
Now comparison operations on the numbers will produce the correct result.
.title SICMP
.sect code,rom8,byte,rel
;Signed compare (16 by 16)
; A Operand1
; B Operand2
; 0.b Return400 if a 4b
;02ifa
l
b
;01ifa
k
b
signed compare:
push a
push b
add a,#08000
add b,#08000
ifgt a,b
jp $great
ifeq a,b
jp $equ
$less:
ld 0.b,#01
pop b
pop a
ret
$great:
ld 0.b,#02
pop b
pop a
ret
$equ:
ld 0.b,#00
pop b
pop a
ret
.endsect
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor
Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd.
2900 Semiconductor Drive Livry-Gargan-Str. 10 Sumitomo Chemical 13th Floor, Straight Block, Rue Deputado Lacorda Franco Building 16
P.O. Box 58090 D-82256 F4urstenfeldbruck Engineering Center Ocean Centre, 5 Canton Rd. 120-3A Business Park Drive
Santa Clara, CA 95052-8090 Germany Bldg. 7F Tsimshatsui, Kowloon Sao Paulo-SP Monash Business Park
Tel: 1(800) 272-9959 Tel: (81-41) 35-0 1-7-1, Nakase, Mihama-Ku Hong Kong Brazil 05418-000 Nottinghill, Melbourne
TWX: (910) 339-9240 Telex: 527649 Chiba-City, Tel: (852) 2737-1600 Tel: (55-11) 212-5066 Victoria 3168 Australia
Fax: (81-41) 35-1 Ciba Prefecture 261 Fax: (852) 2736-9960 Telex: 391-1131931 NSBR BR Tel: (3) 558-9999
Tel: (043) 299-2300 Fax: (55-11) 212-1181 Fax: (3) 558-9998
Fax: (043) 299-2500
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Page 1 of 12 - Signed Integer Arithmetic On The HPC AN-0603
Page 2 of 12 - Signed Integer Arithmetic On The HPC AN-0603
Page 3 of 12 - Signed Integer Arithmetic On The HPC AN-0603
Page 4 of 12 - Signed Integer Arithmetic On The HPC AN-0603
Page 5 of 12 - Signed Integer Arithmetic On The HPC AN-0603
Page 6 of 12 - Signed Integer Arithmetic On The HPC AN-0603
Page 7 of 12 - Signed Integer Arithmetic On The HPC AN-0603
Page 8 of 12 - Signed Integer Arithmetic On The HPC AN-0603
Page 9 of 12 - Signed Integer Arithmetic On The HPC AN-0603
Page 10 of 12 - Signed Integer Arithmetic On The HPC AN-0603
Page 11 of 12 - Signed Integer Arithmetic On The HPC AN-0603
Page 12 of 12 - Signed Integer Arithmetic On The HPC AN-0603

Navigation menu