Signed Integer Arithmetic On The HPC AN 0603
User Manual: AN-0603
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National Semiconductor Application Note 603 Raj Gopalan July 1989 This report describes the implementation of signed integer arithmetic operations on the HPC. HPC hardware support for unsigned arithmetic operation. In order to support signed integer arithmetic operations on the HPC, the user can represent negative numbers in two’s complement form and perform the signed arithmetic operations explicitly through software. The following signed integer arithmetic routines are implemented in the package: Multiplication: 16 by 16 yielding 16-bit result 32 by 32 yielding 32-bit result Division: 16 by 8 yielding 16-bit quotient and 16-bit remainder 32 by 16 yielding 16-bit quotient and 16-bit remainder 32 by 32 yielding 16-bit quotient and 16-bit remainder Addition: 16 by 16 yielding 16-bit Subtraction: 16 by 16 yielding 16-bit Comparison: 16 by 16 for greater to, less than or equal to. .title SIMUSL .sect code,rom8,byte,rel ;Signed multiply (16 by 16) ; B Multiplicand ; A Multiplier ; X;A return ; .public signed mult 16 .local signed mult 16: st a,0.w mult a,b sc ifbit 7,(1).b subc x,b sc ifbit 7,(B a 1).b subc x,0.w $exit: ret REPRESENTATION OF NEGATIVE NUMBERS: For binary numbers, negative numbers are represented in two’s complement form. In this system, a number is positive if the MSB is 0, negative if it is 1. The decimal equivalent of two’s complement number is computed the same as for an unsigned number, except that weight of the MSB is b2**n b 1 instead of a 2**n b 1. The range of representable numbers is b(2**n b 1) through a (2**n b 1 b 1). The two’s complement of a binary number is obtained by complementing its individual bits and adding one to it. The advantage of representing a negative number in two’s complement form is that addition and subtraction can be done directly using unsigned hardware. Signed Integer Arithmetic on the HPC Signed Integer Arithmetic on the HPC TM ;do unsigned multiplication. ;if multiplier is negative ;if multiplicand is negative .endsect AN-603 HPCTM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/DD10395 RRD-B30M75/Printed in U. S. A. The algorithm is as follows: MULTIPLICATION Step 1. Result e op1 * op2 Method 1: Signed multiplication can be achieved by taking care of the signs and magnitudes of the multiplicand and multiplier separately. Perform the multiplication on the magnitudes alone. The sign of the result can be set based on the signs of the multiplier and the multiplicand. Step 2. If op1 k 0 then subtract op2 from upper half of the result. Step 3. If op2 k 0 then subtract op1 from upper half of the result. Now the Result will yield the correct value of the multiplication on two’s complement numbers. Method 3: By sign extending the multiplier and multiplicand to the size of the result one can always obtain the correct result of signed multiplication using unsigned multiplication. Method 2: This method does not require finding the magnitude of the operands. Multiplication can be done using unsigned hardware on the two’s complement numbers. The result will be signed based on the signs of the operands. .title SIMULL .sect code,rom8,byte,rel ;Multiply (Signed or Unsigned are the same) ;32 bit ; K:A Multiplicand ; 14:6[SP] Multiplier ; K:A return ; .public multiply 32 .local multiply 32: push x st a,0.w ld a,k mult a,18[sp].w x a,0.w push a mult a18[sp].w add 0.w,a pop a mult a,18[sp].w add x,0.w ld k,x pop x ret ;(Argument now at 16:8[SP]) ;Multiply hi reg* lo stack ;hold, retrieve lo reg ;(argument now at 18:10[SP]) ;Multiply lo reg* hi stack ;add into hi partial ;(Argument now at 16:8[SP]) ;Multiply lo reg* lo stack ;add in hi partial ;Position ;Restore .endsect 2 DIVISION Similar to multiplication method 1, one can perform the division on the magnitudes of the dividend and divisor. The sign of the quotient can be set based on the signs of the dividend and the divisor. The sign of the remainder will be same as the dividend. ;Division ;16,8 bit ; ; ; ; .title .sect SIDVSS code,rom8,byte,rel & Remainder (signed only, A 14[SP] A unsigned uses inline code) Dividend Divisor return .public signed divide 8,signed remainder 8 .public signed divide 16,signed remainder 16 .local signed divide 8: jsr $shared 8 ret ; signed remainder 8: jsr $shared 8 ld a,k ret ; $shared 8: ifgt a,#0x7f or a,#0xff00 st a,k ld a,16[sp].w ifgt a,#0x7f or a,#0xff00 jp $shared ; signed divide 16: jsr $shared 16 ret ; signed remainder 16: jsr $shared 16 ld a,k ret ; $share 16: st a,k ld a,16[sp].w $shared ifeq a,#0 ret push x ifgt a,#0x7fff jp $unknown negative x a,k ifgt a,#0x7fff jp $negative positive div a,k jp $positive positive 3 ;Uses shared routine ;Uses shared routine ;Return remainder ;Get arguments ;Uses shared routine ;Uses shared routine ;Return remainder ;Get arguments ;division by zero ;unknown/negative ;negative/positive ;Positive/positive is plus,plus $unknown negative: comp inc x ifgt jp div comp inc $positive positive: ld jp $negative positive: comp inc div comp inc jp $negative negative: comp inc div $negate remainder: x comp inc st ld $exit: pop ret ;Unknown/negative a a a,k a,#0x7fff $negative negative a,k a a ; negative/negative ;Positive/negative is minus,plus k,x $exit ;Negative/positive is minus,minus a a a,k a a $negate remainder ;Negative/negative is plus,minus a a a,k a,x a a a,k a,x x .endsect 4 .title .sect SIDVLS code,rom8,byte,rel ;Division & Remainder ;Signed 32 by 16 divide ; X;A Dividend ; K Divisor ; X,A return (remainder and quotient) ; .public signed div 32 .local signed div 32: sc ifeq k,#0 ret ;Divide by zero, set carry and return $shared signed: ifbit 7,x01.b jp $negative dividend jsr $process divisor ;Skipping return ret ;0/040,0 $negate quotient: comp a inc a ret ;0/14 1,0 $negative dividend; comp a add a,#01 x a,x comp a adc a,#0 x a,x jsr $process divisor ;skipping return jsr $negate quotient ;1/041,1 ;1/140,1 $negate remainder: x a,x comp a inc a x a,x ret $process divisor: ifbit 7,k01.b jp $negative divisor divd a,k ;?/0 ret $negative divisor: x a,k comp a inc a x a,k divd a,k ;?/1 retsk .endsect 5 .title .sect SUDVLL code,rom8,byte,rel ;Division & Remainder ;Signed 32 by 32 Divide ; K:A Dividend ; 14:6[SP] Divisor ; K:A return ; ;Stack frame as built and used consists of ;top: ; 0, initial subtrahend hi /dividend shifts into subtrahend ; 0, initial subtrahend lo /becomes remainder ; k, dividend hi /dividend shifts into subtrahend, and ; a, dividend lo /quotient shifts into dividend ; b preserved ; x preserved ; return address ; sp-4–12, divisor hi ; sp-6–12, divisor lo ;Sign flag (0 4 negative, 1 4 positive, for test sense at exit) ;bit 0, divisor sign (1 4 negative) ;bit 1, dividend sign (1 4 positive) ;Inc of flag causes bit 1 4 (bit 1 xor bit 0) by carry/nocarry out of bit 0 ;so that two positives (010) or two negatives (001) indicate a positive ;quotient (011 or 010) in bit 1. Bit 1 always indicates sign if remainder. ;Operation is indicated by bit 3 of the flag, 1 4 remainder. ; .public signed divide 32, signed remainder 32 .public unsigned divide 32, unsigned remainder 32 .local signed divide 32: ld 1.b,#0x02 jp $shared signed ; signed remainder 32: ld 1.b,#0x0a $shared signed: ifbit 7,k01.b ;Check dividend jsr $negate ;Negate dividend and note sign ifbit 7,1603[sp].b ;Check divisor jp $negate divisor jmp $shared ; $negate divisor: x comp add x x comp adc x sbit jp ; unsigned divide 32: ld jp ; unsigned remainder 32: ld a,16[sp].w a a,#1 a,16[sp].w a,14[sp].w a a,#0 a,14[sp].w 0,1.b $shared ;Negate divisor and note sign 1.b,#0x02 $shared 1.b,#0x0a 6 $shared: push push ld push push ld clr push push ld add ld or ifeq jmp ld x b b,sp a k x,sp a a a k,#118 k,sp a,[k].w a,2[k].w a,#0 $zero 0.b,#32 ;Preserve registers a,[b].w a a,[b0].w ;Shift Dividend:Quotient ;Place dividend, becomes quotient ;Set subtrahend, becomes remainder ;Access divisor argument ;division by zero ;Set counter $loop: ld shl xs nop ld rlc xs nop ld rlc x ld rlc x ifc jp sc ld subc ld subc ifnc jp $subtract: ld subc x ld subc x sbit $count: decsz jmp $zero: pop pop pop pop ifbit jp ld ld inc a,[b].w a a,[b1].w a,[x].w a a,[x0].w a,[x].w a a,[x1].w ;Carry out 1 dividend divisor ;Check for dividend divisor $subtract a,[x0].w a,[k].w a,[x1].w a,2[k].w $count ;dividend divisor a,[x].w a,[k].w a,[x0].w a,[x].w a,2[k].w a,[x1].w 0,[b].b ;Subtract out divisor (c is set) 0.b $loop ;Count 32 shifts k a x b 3,1.b $exit a,b k,x 1.b ;Get Remainder and/or Quotient ;and clear working off stack ;Set quotient bit ;want remainder, have it ;Want Quotient ;Divisor’s sign Xors Dividend’s 7 $exit: pop pop ifbit ret b x 1,1.b comp add x comp adc x rbit ret a a,#1 a,k a a,#0 a,k 1,1.b ;Restore registers ;positive result $negate: ;Negate K:A ;Note sign (for entrance) .endsect 8 ADDITION Two’s complement numbers can be added by ordinary binary addition, ignoring any carries beyond the MSB. The result will always be the correct sum as long as the result doesn’t exceed the range. If the result is the same as for the subtrahend, then overflow has occurred. .title SIADD .sect code,rom8,byte,rel ;Signed add (16 by 16) ; A Operand1 ; B Operand2 ; Carry Return .public sign add .local sign add: ld 0.b,#00 ifbit 7,(A01).b inc 0.b ifbit 7,(B01).b inc 0.b ;if bit 0 of 0.b 4 1 then op1 and op2 have different sign ;if bit 0 of 0.b 4 0 then op1 and op2 sign are same ;then if bit 1 of 0.b 4 0 both operands are positive ;else both operands are negative. add a,b rc ifbit 0,0.b ret ifbit 1,0.b jp $negatives $positives: ifbit 7,(A01).b ;Perform unsigned addition ;both operands are different sign ;both op1 and op2 are negative ;both op1 and op2 are positive ;if result sign is negative then set overflow bit ;overflow sc ret $negatives: ifbit 7,(A01).b ;if sign bit of result is negative, then no overflow ret sc ;overflow $exit: ret .endsect 9 SUBTRACTION Subtraction can be achieved by negating the subtrahend and perform the addition operation. Overflow can be detected as mentioned before by checking the signs of minuhend and the negation of the subtrahend and that of the sum. .title .sect SISUB code,rom8,byte,rel ;Signed subtract (16 by 16) ; ; ; B Operand1 A Operand2 Carry,A Return .public sign sub .local sign sub: ld ifbit inc 0.b 0.b,#00 7,(B01).b ;initialize sign flags $negate A: comp A inc A $ngative comp A: ifbit 7,(A01).b inc 0.b ;if bit 0 of 0.b 4 1 then op1 and op2 have different sign ;if bit 0 of 0.b 4 0 then op1 and op2 sign are same ;then if bit 1 of 0.b 4 0 both operands are positive ;else both operands are negative. add A,B ;Perform unsigned addition rc ifbit 0,0.b ;both operands are different sign ret ifbit 1,0.b ;both op1 and op2 are negative jp $negatives $positives: ;both op1 and op2 are positive if bit 7, (A01).b ;if result sign is negative then set overflow bit sc ;bit 0 of byte 0.b is set to indicate overflow ret $negatives: ifbit 7, (A01).b ;if sign bit of result is negative, then no overflow ret sc ;sign bit of result is positive, hence overflow. $exit:ret .endsect 10 .title .sect NSISUB code,rom8,byte,rel ;Signed sub (16 by 16) ; ; ; A Operand1 B Operand2 Carry Return .public sign sub .local sign sub: ld 0.b,#00 ifbit 7,(A01).b inc 0.b ifbit 7,(B01).b inc 0.b ;if bit 0 of 0.b 4 1 then op1 and op2 have different sign ;if bit 0 of 0.b 4 0 then op1 and op2 sign are same ;then if bit 1 of 0.b 4 0 both operands are positive ;else both operands are negative. sc subc a,b ;Perform unsigned addition rc ifbit 0,0.b ;both operands are different sign jp $chkovf ret ;both operands are same sign, can’t produce overflow $chkovf: ifbit jp 7,(B01).b $negminu ifbit sc ret 7,(A01).b ifbit sc ret 7,(A01).b $posminu: $negminu: .endsect 11 Signed Integer Arithmetic on the HPC COMPARISON To do signed comparison on n bit two’s complement numbers first add 2**(n b 1) to the numbers. This will basically shift the numbers from b(2**n b 1) to a (2**n b 1 b 1) range to 0 to 2**n b 1. Now comparison operations on the numbers will produce the correct result. .title .sect SICMP code,rom8,byte,rel ;Signed compare (16 by 16) ; A ; B ; 0.b ; ; signed compare: push push add add ifgt jp ifeq jp $less: ld pop pop ret $great: ld pop pop ret $equ: ld pop pop ret Operand1 Operand2 Return400 02 01 if a 4 b if a l b if a k b a b a,#08000 b,#08000 a,b $great a,b $equ 0.b,#01 b a 0.b,#02 b a 0.b,#00 b a .endsect LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: AN-603 1. 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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : Yes Create Date : 1995:07:03 18:28:17 Producer : Acrobat Distiller 2.0 for Windows Title : Signed Integer Arithmetic on the HPC Subject : AN-603 Author : Keywords : Application, Notes Modify Date : 2001:11:23 11:46:02+05:30 Page Count : 12EXIF Metadata provided by EXIF.tools