AP 49_Serial_IO_and_Math_Utilities_for_the_8049_Microcomputer_Jan79 49 Serial IO And Math Utilities For The 8049 Microcomputer Jan79

User Manual: AP-49_Serial_IO_and_Math_Utilities_for_the_8049_Microcomputer_Jan79

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APPLICATION
NOTE

Ap·49

January 1979

© Intel Corporation 1979

I

9800904

AP-49
INTRODUCTION
The Intel@ MCS-48 family of microcomputers marked
the first time an eight bit computer with program
storage, data storage, and 1/0 facilities was available on
a single LSI chip. The performance of the initial
processors in the family (the 8748 and the 8048) has
been shown to meet or exceed the requirements of most
current applications of microcomputers. A new member
of the family, however, has been recently introduced
which promises to allow the use of the single chip
microcomputer in many application areas which have
previously required a multichip solution. The In·
tel'" 8049 virtually doubles processing power available
to the systems designer. Program storage has been increased from 1K bytes to 2K bytes, data storage has
been increased from 64 bytes to 128 bytes, and processing speed has been increased by over 80%. (The 2.5
microsecond instruction cycle of the first members of
the family has been reduced to 1.36 microseconds.)
1\ is obvious that this increase in performance is going
to result in far more ambitious programs being written
for execution in a single chip microcomputer. This article will show how several program modules can be
designed using the 8049. These modules were chosen
to illustrate the capability of the 8049 in frequently encountered design situations. The modules included are
full duplex serial 1/0, binary multiply and divide routines,
binary to BCD conversions, and BCD to binary conversion. It should be noted that since the 8049 is totally
software compatible with the 8748 and 8048 these
routines will also be useful directly on these processors. In addition the algorithms for these programs
are expressed in a program design language format
which should allow them to be easily understood and
extended to suit individual applications with minimal
problems.

however, is more economic than technical; these same
peripheral chips which are such a bargain when coupled
to a microprocessor such as the MCS-85 or 86, have a
significant cost impact on a single chip microcomputer
based system. The high speed of the 8049, however,
makes it feasible to implement a serial link under software control with no hardware requirements beyond two
of the 1/0 pins already resident on the microcomputer.
There are many techniques for implementing serial 1/0
under software control. The application note "Application Techniques for the MCS-48 Family" describes
several alternatives suitable for half duplex operation.
Full duplex operation is more difficult, however, since it
requires the receive and transmit processes to operate
concurrently. This difficulty is made more severe if it is
necessary for some other process to also operate while
serial communication is occurring. Scanning a keyboard
and display, for example, is a common operation of
single chip microcomputer based system which might
have to occur concurrently with the serial receiveltransmit process. The next section will describe an algorithm
which implements full duplex serial communication to
occur concurrently with other tasks. The design goal
was to allow 2400 baud, full duplex, serial communication while utilizing no more than 50% of the available
processing power of the high speed 8049 microcomputer.
The format used for most asynchronous communication
is shown in Figure 1. It consists of eight data bits with a
leading 'START' bit and one or more trailing 'STOP' bits.
The START bit is used to establish synchronization between the receiver and transmitter. The STOP bits ensure that the receiver will be ready to synchronize itself
when the next start bit occurs. Two stop bits are normally used for 110 baud communication and one stop
bit for higher rates.

FULL DUPLEX SERIAL
COMMUNICATIONS
Serial communications have always been an important
facet in the application of microprocessors. Although
th is has been partially due to the necessity of connecting a terminal to the microprocessor based system
for program generation and debug, the main impetus
has been the simple fact that a large share of microprocessors find their way into end products (such as intelligent terminals) which themselves depend on serial
communication. When it is necessary to add a serial link
to a microprocessor such as the Intel@ MCS-85 or 86 the
solution is easy; the Intel@ 8251A USART or 8273 SDLC
chip can easily be added to provide the necessary protocol. When it is necessary to do the same thing to a
single chip microcomputer, however, the situation
becomes more difficult.
Some microcomputers, such as the Intel 8048 and 8049
have a complete bus interface built into them which
allows the simple connection of a USART to the processor chip. Most other single chip microcomputers,
although lacking such a bus, can be connected to a
USART with various artificial hardware and software
constructs. The difficulty with using these chips,

2

STOP

START
BIT
01

02

03

04

05

06

07

08

BIT

IL....--'---.J'---'----'---..L-..L-----L---'---.J

Figure 1.

The algorithm used for reception of the serial data is
shown in Figure 2. It uses the on board timer of the 8049
to establish a sampling period of four times the desired
baud rates. For 2400 baud operation a crystal frequency
of 9.216 MHz was chosen after the following calculation:
f

=480N(2400)(4)
where 480

2400
4
N

is the factor by which the crystal frequency is divided within the processor
to get the basic interrupt rate
is the desired baud rate
is the required number of samples per
bit time
is the value loaded into the MCS-48
timer when it overflows

I

AP-49
The value N was chosen to be two (resulting in f = 9.216
MHz) so that the operating frequency of the 8049 could
be as high as possible without exceeding the maximum
frequency specification of the 8049 (11 MHz).

; STfI!T If" RECEI'r1: ROOTINE

i====::Z:==
; 1 IF RECEI'r1: FLRG=8 T1£H
,2
IF SERIIi. IIf'UT=5I'OCE TI£H
,3
RECEI'r1: FLAG:=1
;3
BYTE FIHISIED FLAG: =6
;2
EII)IF
,1 ELSE
SINCE RECEI'r1: FLAG=1 TI£H
;2
IF SVN: FLRG=8 TI£N
;3
IF SERIIi. 1If'UT=5I'OCE TI£H
,4
SVN: FLAG: =1
,4
DATA: =8IJl
,4
SfWL£ CNTl/: =4
,3
ELSE
SINCE SERIII. IIf'UT=IIfI!K 1l£N
;4
RECEI'IE FLAG:=6
;3
EII)IF
;2
ELSE
SINCE SOC FLAG--J. TI£H
;3
SII!Pl.E crumR:=SII!Pl.E CWHER-1
;3
IF SII!Pl.E crumR=8 TI£N
;4
SII!Pl.E ClJlMER: =4
;4
IF B't'TE FlNISI£D FLAG=e TI£H
;5
CfI!RY :=SER III. IIf'UT
;5
SlfIFT DflTA RIGHT WITH CfI!RY
;5
IF CARRY=1 T1£N
.6
IJIF
;2
ENDIF
.1 ENDIF
Figure 2

The timer interrupt service routine always loads the
timer with a constant value. In effect the timer is used io
generate an independent time base of four times the reo
quired baud rate. This time base is free running and is
never modified by either the receive or transmit programs, thus allowing .both of them to use the same
timer. Routines which do other time dependent tasks
(suCh as scanning keyboards) can also be called periodically at some fixed multiple of this basic time unit.
The algorithm shown in Figure 2 uses this basic clock
plus a handful of flags to process the serial input data.

Once the meaning of these flags are understood the
operation of the algorithm should be clear. The Receive
Flag is set whenever the program is in the process of
receiving a character. The Synch Flag is set when the
center of the start bit has been checked and found to be
a SPACE (if a MARK is detected at this point the receiver
process has been triggered by a noise pulse so the program clears the Receive Flag and returns to the idle
state). When the program detects synchronization it
loads the variable DATA with 80H and starts sampling
the serial line every four counts. As the data is received
it is right shifted into variable DATA; after eight bits
have been received the initial one set into DATA will
result in a carry out and the program knows that it has
received all eight bits. At this point it will transfer all
eight bits to the variable OKDATA and set the Byte
Finished Flag so that on the next sample it will test for a
valid stop bit instead of shifting in data. If this test is
successful the Data Ready Flag will be set to indicate
that the data is available to the main process. If the test
is unsuccessful the Error Flag will be set.
The transmit algorithm is shown in Figure 3. It is executed immediately following the receive process. It is a
simple program which divides the free running clock
down and transmits a bit every fourth clock. The variable
TICK COUNTER is used to do the division. The Transmitting Flag indicates when a character transmission is in
progress and is also used to determine when the START
bit should be sent. The TICK COUNTER is used to determine when to send the next bit (TICK COUNTER MODULO 4 = 0) and also when the STOP bits should be sent
(TICK COUNTER = 9 4). After the transmit routine completes any other timer based routines, such as a keyboard/display scanner or a real time clock, can be
executed.

,STfI!T If" TRfIIS!IIT ROOTINE

,1
.• 1 Tic!( crumR: =Tic!( C!lJflER+l
; 1 IF Tic!( crumR III) 4=6 TI£H
;2
IF TRfIIS!IITTING FLAG=1 TI£H
;3
IF TICK CWfTER=88 1919 99 BIlBY TI£H
;4
TRANSltnTlNG FLAG:~
,3
ELSE
IF Tic!( CWfTER=88 1991 99 BIlBY TI£H
,4
SEll) END IH!f(
;4
TRfIIS!IITTING FLAG >II
,3
ELSE
SIt«:[ TIC!( crumROT1£ IIIO'IE CWfT TI£H
;4
SEND NEXT BIT
;3
ENDIF
;2
ELSE
SIt«:[ TRANSIIITIING FLAG=e Tl£N
;3
IF TRfIIS!IIT REIllEST FLAG--J. TI£H
;4

XIITBVT: =NXTBVT

;4
;4
;4
;4

TRANSltIT REIllEST FLAG:=6
TRANSltITTlNG FLAG:=1
TICK COONTER: =8
SEND SYNC BIT (SI'ACE)
;3
ENDIF
;2
OOIF
; 1 ENDIF
Figure 3

All mnemonics copyrighted © Inlel Corporation 1979.

I

3

AP-49
Figure 4 shows the complete receive and transmit pro·
grams as they are implemented in the instruction set of

ISJ~:-!l

MCS-43.'UPI-41

i'lAC~O

LeI( OBJ

the 8049. Also included in Fig. 4 is a short routine which
was used to test the algorithm.

ASSEMBLER, '.2 II

50I.lR([ STATEMENT
i ******.t:+-:+:t;*tlt"t,;f'**:t:t*:f.*';;*fi:t**t:U.******:f,::fo'''*+-"*:f:f·*:~*.f:*;u,****:t:·t:***.******"t'+':******i:*

.*
" *

2

4 ,.

THIS l'I1or.f'AM TESTS THE FULL L"4)PW: COI1I1UPHCATION SiJFTj.lARE

5 i ********·.uw•••. ,· ••••••••• ***tt.,..**·••••·H· ••*.***t**.,.t**.*·~*~·.**.********H.·** ....
6 '
7 $INCLlJl'>E(Fl.IJIITEST prt)
9 '
HI.'

STRPT Cf '1 EST ROUTINE

=====================

11,
12 '

n,

14
15 '
16 '1 ERPOR COliNT =3
1, ,1 ~EF'EAT
18 .'::
PATTERN =0
19 2
INn IfiliZE TIMER
2i3 ,2
CLEAR FLAGB','TE
21 i 2
FLAG1 =11AP"
22 :2
REPEAT
,
?"
~~ u
IF TRFflStllT REQUEST FLAG=~ Tt£N
24 ,4
r;,;rB'r'TE .=PATTERN
2~, ,4
TPflNSl'I1l REQUEST FLAG=l
26, j'
ENDIF
27 ,:;
IF DATA READY FL~G=l THEN
28 ,4
PATTERN. =O¥DATA

29 ,4
J3 '3

0000 C5

[!ilTA PEArN FL AI,

~

ENDIF
31 ,2
UNTIL ERROR FLAG OR OVERRUN FLAG
}2 ,~
INCPEMENT ERROR COLINT
is ,1 UNTIL FOREVER
34 EOF
:5 I'EJECT
36
ORG
\}
]7 ,1 SELECT PEGI5TEP BAN!( 0
:>8
SEl
RBIit
~;9 ,1 GaTO TEST
40
JMF
TEST
41 i
INCLLI(JE(F1IJAH)
42·
4} ;

44
45
46
47
48
49

,
"
'
,
,

AS,~lCHl?lJNOIJS

PECEIVE/TRANSMIT ROLITINE

==================================
THIS Rcm HlE RECEIVES SERIAL emE USING PIN TO AS RXD
AND CONCIJPREN1LY TRANSMITS lISING PIN P27
NOTE.
THIS ROIJTlNE IJSES FLAG 1 TO BLFFEP THE TRAN5MITTW
Figure 4

All mnemonics copyrighted © Intel Corporation 1979.

4

I

AP-49
LOC

[If,.l

SOIEE STRTEI'IENT

SEll

50· 1 DRTA LINE. THIS flIPlINflTES THE JITTER THAT
51 ,1 WiJ.1lD BE CRUSED BY ',WIflTIOIIS IN THE RECEIVE
52 ·1 TIMING. NO OTHEP f'\,'OORAM 11Ft'!' USE FLAIJ 1 WHILE
53 .1 THE TlMEP HlTEl1PlJ1'T IS ENAt.'lED
54 ,
55 •

St.;
57 .
58 .
59 .
60 ;
61 ;

PEG ISTEP ASSIGlft:NTS-BANKl
=======================

62·
63 flTENP
64 FL GBI'T
65
66
67 SAI'ICTP
68 TCKf.T11
69 REGO

7B.
71·
,~

f<

0020
0021
0022
0023

73
?4
:'5
76
77
78
79

• USED TO SAVE AWJl'll.LA1~ CONTENTS WRlNG INTERRlII'T
; CONTAINS I/A~I()IJS FLAGS IJSl:lI 10 CONTROL 1HE kECEI't'E
• AtID TR~N91lT P~OCESS. SEE CONSTANT Dl::F INITIONS FOR
• THE "'E~IHNG OF EACH BIT
SAI'I'LE C~TEP F~ Tf( REC IEIIE f'ROCES~
SAMPLE COIJNTER FOI1 THE TRAN5l1IT PReUSS
IJSED 8~ PDINTEII R!:I3ISTER

EQlJ
ErnJ

E~J

EQtJ
E()U
PAM A551GtlMENTS

.
•

•
I'IOI'OOT
MOffTA
I'IXI'ITSV
ltliiTBY
SEJECT

E(lI)
EQU
EIlI)
EQIJ

20H
21H
22H
23H

;
·
·
;

IlECEI'iE RETURNS VAlID DmR IN THIS B'ffE
RECEIVE ACCtlI'IUlATES OOlA IN THIS BI'TE
CONTAINS B','TE ~IP¥.i TRA.'lSMIlTED
CONlAII',': THE NE'XT B'~TE TO BE TRANSMITTED

j

00.
Sl .

82

CONSTANTS

<'

83.
B4 •
BJ •

THE FOLLl).lm:; CONSTANTS ARE USED TO ACCESS THE
IN REG ISTER FUlEYT

37 RCVFLG Eau

91H

B:3

0008

B9 SI'NFLG EW
ge
91 BVFNFL EIlI.!
92
93 OWr'FL ~IAJ

OOHl

94
95 ERRFlG EOfJ

lBH

00<''0

%
97 TRRIlFL EQIJ

2(t!

82H
84H

;
•

98H

9S3

99

0049
0089

= 100
= 191 TRIG"L EQIJ
= 102
= 103 OVRUN Eau
= 104

4!lH

,
,

8811

•

FL~

BITS CONTIiINED

SH WHEN ST~T BIl IS FI"'~ T DETECTED
RESET WHEN REcmE I'k(ICESS IS COOPLETE
SET r.JHEN SlA11T BIT IS VEIIIFIED
RESET WHEN RECEIVE PROCESS IS COO'LETE
RESET WHEN STAf.iI ~IT IS FIJ
RESET BY TRANSMIT PIIOCESS r.lliEN BYTE IS ACCf:.PTED
SET WHEN TRANSMISSION OF A B'flE STARTS
RESET WHEN STOP ~IT IS TRANSI'IllTED
SET B'" RECEIVE PROCESS WHEN OYERUN OCCURRS
SHOULD BE RESET S'T' !'lAIN PROGRAI'I IKN SAMPLED

Figure 4 (continued)
All mnemonics copyrigh1ed © Intel Corporation 1979.

I

5

AP-49
lOC 00.7

SEQ

SI:I.ME STATEI£NT

= 195 )
= 196 i
= 197
= 1.98

i

EQlJ

= 119 SPACE EIlU
= 111 STPBTS EQIJ
= 112
= 113
= 114 ;
= 115 $EJECT
= 116 ;

9IlOO

COIISTANTS

i

= 109 I'ftRI(

9989
FF7F

GE~RfI..

==============

= 1f? ;
= 118 ;
= 119 i

START

i3'Jl
USED TO GENEI1ATED A I'IflRI(
t«lT 88H; lISE[) TO GENERATE A SPACE
0
, CONTRttS THE tulBER ~ SIIJ' 8IT5
0 GENERATtS otE STIJ' BIl
1 GENERATES 00 STOP BITS

I)'

RECEIVEI'TRANSI'lIT INTERRlf'T SERIIICE ROUTINE

=============================================

=129

900711

= 121
= 122,1 ENTER INTERRUPT PIOOE
= 123 Tl ~
nF
LW.T

= 124

RETR

= 125 lIART: SEl
RB1
= 126 .i 1 SAVE ACCU1I.lAT~ CfllTENTS
= 127
my RTEIIf', it
909C 23FE
900E 62

= 128' 1 REU!fKl TIMER
= 129
MO~'
A, tTlf{:Nl
= 133
mil
1,/1
= 131;

900F
9811
9813
0015

7615
9A7F
8417
8A80

0017 FE
0018 1224

oo1fl 3664
801(: FE
8010 4301
00lF 53FB
8021 HE
0022 9464

8024

22~

= B1 ;

OUTPUT TXD BlFFER (F1) TO Tx[) I/O LINE (P27)

= 133 ,
= 134 ,
= 135

============================
JF1

= 136 OSPACE· ANI.
= 137
= BS
= 139
= 148
= 141
= 142

.JIIP
01'fIRI(

0Rl

0I1ARK
P2.I5PACE
RCY009
f>2,1MARK

)
)
,

START OF RECEIVE ROlITiNE

===============

.'

= 143 ; 1 IF RECEIVE FLAG=0 TI£N
= 144 RC\II!IJI!. IKJ\I
II, FLreYT
= 145
.7110
RCVII19
= 146 ; 2
= 147
= 148 ; 3

IF SERiAl INPUT=SPACE THEN
JTe
XI'IIT
RECEIVE FLAG:=l

= 149
= 1S!}
= 151 i 3
= 1S2

HOV
ORL

= 153 .2

ENDIF
HOY

= 154

A. FlreYT
it, 'RC~'FlG
BYTE FINISI£D FLitG:=8
ANl
It It«lT Il'1'FNFL

FLGBYT, it
Jt1P
XI'IIT
= 156, 1 ELSE
SIP{;f RECEIVE FLAG=1 TI£N

= 155

= 157 .' 2 IF S','NC FlAG=0 Tl£N
= 1SS Rf:v310. JB1
RCY033
= 159
IF SERIAl INPUT=5PACE

.i"

l~EN

Figura 4 (continued)
All mnemonics copyrighted © Intel Corporation 1979.

6

I

AP-49
SOIJRCE STATEMENT

LOt OBJ

8826

36~3

002'3 4302
002A AE
~1€t<'B B821
002D 8080

002F BN!4
tlfJ31 0464

0033 53FE

0035 f£
0036 lI464

= 160
= 161 . 4
= 162
= 163
= 164 .4
= 165

JTIl

RC\'820
5'ING FLffi=l

OI"L

1'10'1

A, J5VNFLG
FUlB'IT. A
DA1R:=80H

MQ~

RI!, mATA

= 166
= 167 ; 4

MO','

= 168

~(l\'

@R~. 188H
SRl'lPLE CNTR =4
SAl'lCTR, 44

= 169

JI'f'
XI'IIT
= 17~
ELSE
SINCE SERIf!:.. INf'lJT=I'IAFV THEN
= 171; 4
~(CEIVE FLA(, =0
= 172 ~GV820 ANt.
A,INOT RCVFLG
= 17:;.3
[N[)IF
= 174
OOV
FLI:iWT. A
Jt1F'
XI1lT
= 175
= 176; 2
EL Sf
51 NeE sw~: r LAG=l THEN
= 177 7
SRMI'LE C(ll.JjTE~ =SAI'II'LE COUNTER-l
= 178 RC'v'0J~ DJNZ
SMTR, :<~lT
IF Sp,r1PLE ~WN1ER=tl nOl
= 179 .3
= 180 ; 4
SAMPLE CDUUTER =4
I'IOV
5AI1CTR, t4
= 1st
= 182; 4
IF B'r'TE FItHSHf[l FLAG=8 THEN
= lB3
JK:
RCVB5B
= 184
C
of

003$ ED64

003A BOO4

003( 5259
003E 97

003F 2642
0041 Ii?
0042 P,s21
0i.l44 F£t
0045 67
0046 riO

cu.

= 185 .; 5
= 186
= 187
= 188 RCV040
= 189
= 139 ; 5
= 191

= 192
= 193

i~

CARR'{ =SERIHL INPlIl
JNTO
CPL

RCV049

I'lO\l
rtOV

Re. t!'IDATff

lIRe
rtOV

mc

C
fl,~e

SHIFT DATA t.'liJ:n WllH
A
~R0,A

IF CARRI'=1 THEN

:,:MIT

0047 E664

= 194
= 195 ;6

0049 BS2!l
0048 A!l

=196

1"0. tHlJl;(!RT

=19i'

@R9,A

004C FE
004[) "1254

= 198; 6
= 199
= 299

1!94F 4304
9951 fiE
0052 0464

CAR~I'

OI FLRG=l
A, .BVFhfL
FUlB\'T. A

=204

xlm

= 205; 6

ELSE

=206;7
= 287 . (

SIr'TE FINISHED FLfil3:=1
CIVERRI.lN FLAG =1

.~

298 RCV045.

0054 43<14
0056 AE

=
=
=
=

0057 8464

= 212 ;6
= 213 , .J
= 214

209

; ,,:w
~L

218
211

If.l\I

fl.. RGB\'T
A. t(B'r'FNFL OR OVRIJN)
RGBI'T. A
END IF

ENDIF

.~

JI1'

XMIT

Figure 4 (continued)
All mnemonics copyrighted 
801C

SIlRCE STllTEI£NT

SEQ

= 277
= 278

= 279
= 289
= 281
= 282
= 283

= 284
= 285
= 286
= 287
= 2SS
= 289
= 298
= 291
= 292

A,FlGBYT
/lOY
ft, tr«JT TRtU'L
IN.
FLGBYT,II
/lOY
JIf'
RET\J1N
EtI>lF
,3
ELSE
sua TICK COIJITEROTI£ fIlOYE ClUff TlEN
,4
SEll> I£XT BIT
00929: /lOY
119, III»UB'~
/lOY
II, ~
I!RC
A
HOI!
@Rg, II
; FLoo 1 WILL BE USEJ) TO BUFFER TXD
CLR
F1
Jt{:
RETlMl , 00 TO RETURN POINT If OO=SPllCE (8)
eft
F1
i ELSE Cl11PLEI'Errr FLAG 1 TO II PIARK
JI1P
RETI»I
,:$
Etl>IF
.; 2
ELSE
sIIa TRRNSfIITTlNG ~LAG=8 TI£N
;3
IF TRAlISMIT REIllEST FlAG=1 TlEN
XI'IT849: JSS
R E T I M l , FLAG BYTE 1l£RE
,4
XIITBYT :=NXTBYT
IllV
119, M«TBY

mY

A.@RiI

Pf.ly
/lOY

R8, t/lXlffijY
tiRe, ft
= 293
=294,4
TRfIIS"IT IIE!lI£ST FLAG: =8
I!OY
fI, FLGBYT
= 295
IN.
ft, INOT T~L
=296
= 297 ,4
TFRNSIIITTIrIG FLfI!;·=1
= 298 .
ORL
A.'TRlG\.
mY
FLGBYT, II
= 299
=3ee,4
T/ CK COOOER· =8
IIOY
TCKCTR, 10
= 381
= 382 ;4
SEND SYNC BIT (SPACE>
= 38:;'
CLR
F1
.; SET FLAG 1 TO CAUSE A SPin
= 384 i 3
ENOIF
= 385 ,2
EtI>lF
= 3\l6 .. 1 EtI>IF
= 397 RETURN:
= 398 i 1 RESTORE ACClIU.ftT~
= 389
mv A, ATEtIf'
= 319
RETR

:m

$EJECT

312
313
314
315
316
317
318
319

;
,
j

START IF TEST ROOmIE
============

;

WICHT
tFL!lB't'
IlSAllCT
320 "TCKCT

ORG

8189H

EQU

-2

EOO
EOO
EOO

1EH
1DH
1CH

EQU
EQU

R7

321 ;
9997
0006

322 ERRCNT

:m

PRTT

R6

324.;
Figure 4 (continued)
All mnemonics copyrighted

I

C> Inlel Corporation 1979.

9

AP-49
loe IB1

SEQ

SW!CE STfITEtIENT

325 ;
326 ;
327 ; 1 ERRIR ClUT: =8
II1IIIl 81'99

11182 BElli!

328
329
118
331
332

TEST: 'lIlY
EJIRCNT,18
; 1 REPEAT
TlOP:
;2
PATTERN :=8
..:J\I
PRTT, 199

m ;""

8194
811J6
8187
8198

23FE
62
55
25

81~ B81E
8198 B9II9

8180 AS
elSE B5

8111F BalE
8111 Fe
8112 8224
8114 B923
8116 FE
8117 R1

8118 35

8119 F8
911R4328
8He R9

9111>
911E
0120
9122

25
1622
2424
149A

8124 F9
8125 37
8126 7238

334
33S
336

m

338
339
349
341
342
343
344
34'5
346
347
348
349
358
351
3S2
353
3S4

.: 2

;2

;2
TlLOP:
;3

INITlfUZE TlItER
..:J\I
R,ITII'DIT
..:J\I
T,R
STRT

T

EN

TCNTI

CLERR FLAGBYTE
..:J\I
R9, IIflGBY
..:J\I
@R9,18
FUm=tlRRK
elI?
F1
CPt.
F1
P.EPERT

IF TRRNSPIIT REHST FLOO=8 T1£N
Re.II'IFLGBY
R.@R9

..:J\I
..:J\I
JB5

;4
..:J\I
..:J\I
..:J\I

;4

3S5
3S6
357

DIS

358
368

..:J\I
ORL
f!OII

361

EN

362
363

JIll

359

364
165
366
367

JTF
TESTR:
13
;3
TREC:

TREC
NXTBYTE :=PATTERN
Ri.1fIIXTBY
R.PflIT
@R1,R
TRfIISIIIT REHST FLoo=1
TCNTI; LOCK OUT TlI'ER INTERRlPT
; so TIflT ItITI.H. EXCLUSIIJI IS IftINTHII£D IflILE
; Uf ROO B\'TE IS BEING PIOO IFIED

@RIj,R
TCNTI
TESlft
TREe

CflL

lJIRT
i Cfll lJIRT BECflISE TIllER OI/Er(FLIl€D IU:H¥.i LOCKOUl
ENDIF
IF DRTR REfI)Y FlRG--t THEN

368

Itl\I

R.1!R8

369
379

CPt.

R

JB3

TRECE

8128 FIE

371 14
372
373
374

812C 35

376

PRITERN:=OOlfITA
tt)\I
Ri, IfIOI F8

3(9
Figure 4 (continued)

All mnemonics copyrighted Cllntel Corporation 1979.

10

I

AP-49
LOC OBJ

SOORCE S1ATEI'ENT

SEQ

A, IIWJT DRD'IFL

IN..

912E 53F7

388

9139 AI)
913125
9132 1636
(11342438
9136 148A

3B1
"'"
TeNTI
3B2
EN
TESTB
383
JTF
TR(CE
384
JI'f
38S TESTS: CALL
I.III1T
; CALL UART IF TIl'IER OYERFLIlEO Dl.JRING lOCKWT
3S6 TRECE:
3B7 ; 3
EN>IF
388; 2
UNTIL ER~ FLAG CCil MRRUH FLAil
3B9
I'KlV
A,@R!I
3913
ANI.
A. I(OYRlJl CCil ERRFLG)
:m
JZ
lILOP
:m ; 2 INCREI'fNT EJ1ROF! COUNT
m
11£
E~CNT
394 ; 1 I.tITIL FOREIlER
195
Jrf'
TLOP

~,A

ens F9
9139 53913
9138 C69F
913f) 1F
813E 2492

USER SYI1BCtS

flIDIP 9997
IFLGBY 991E

B't'FN'L iKI84
HNXTB't' 9923

DRl>YFL 9998

O'MJN !1(18(1
11CV95i.:l 9959
STPBTS 11989
TISR 8087
0091(1 Iti!6E

PAll l1li96
RCY960 00'5F

RCV800 6917
RC'r'970 Q061
TCKCTR 00i!4

SYhflG 9992
TlOP 9182
XIIT929 8978

flSSEMBlY COMPLETE,

IQ(llAT !1!129

TREe 9124
001140 9086

898(1

ERRCNT 0097
IISIlICT 8910

ERRFLG 9919
"TCKel 981(;

FlGBYT 0006
NXtITB't' Il822

I1AFJ(

0I1AR1( 9815

f10ATA !I!l21
OSPACE 9911

J
BO'2°

+

BOAO't>

11

AP-49

tions that the "shift and add" algorithm takes its common name.

The sum of all these terms represents the product of A
and B. The simplest multiply algorithm factors the
above terms as follows:

The "shift and add" algorithm shown above has two
areas where efficiency will be lost If Implemented in the
manner shown. The first problem is that the addition to
the partial product is double precision relative to the
two operands. The other problem, which Is also related
to double precision operations, is that the A operand is
double precision and that it must be left shifted and
then the 8 operand must be right shifted. An examination of the "longhand" polynomial multir ication will
reveal that, although the partial product is ondeed double precision, each addition performed is only single
precision. It would be deSirable to be able to shift the
partial product as It Is formed so that only single precl·
sion additions are performed. This would be especially
true If the partial product could be shifted into the "8"
operand since one bit of the partial product is formed
during each pass through the loop and (happily) one bit
of the "B" operand is vacated. To do this, however, it is
necessary to modify the algorithm so that both of the
shifts that occur are of the same type.

Since the coefficients of B (i.e., BO, 81, 82, and 83) can
only take on the binary values of 1 or 0, the sum of the
products can be formed by a series of simple adds and
multiplications by two. The simplest Implementation of
this would be:
MULTIPLY:
PRODUCT = 0
IF 80 = 1 THEN
IF 81 = 1 THEN
IF 82= 1 THEN
IF 83 = 1 THEN
END MULTIPLY

PRODUCT: =
PRODUCT: =
PRODUCT: =
PRODUCT: =

PRODUCT + A
PRODUCT + 2* A
PRODUCT+4*A
PRODUCT + 8* A

In order to conserve memory, the above straight line
code is normally converted to the following loop:

To see how this can be done one can take the basic
multiplication equation already presented:

MULTIPLY:
PRODUCT: =0
COUNT: = 4
REPEAT
IF 8(0)=1 THEN PRODUCT: = PRODUCT + A ENDIF
A:=2*A
8:= 812
COUNT: = COUNT - 1
UNTIL COUNT: = 0
END MULTIPLY

and factoring :t from the right side:
A*B=:t[BO*(A*2- 4)+ B1*(A*2-~
+ B2*(A*2- 2)+ B3*(A*2- 1»)

The repeated multiplication of A by two (which can be
performed by a simple left shift) forms the terms 2* A,
4*A, and 8*A. The variable 8 is divided by two (per·
formed by a simple right shift) 50 that the least signifi·
cant bit can always be used to determine whether the
addition should be executed during each pass through
the loop. It is from these shifting and addition opera·

This operation has resulted in a term (within the
brackets) which can be formed by right shifts and adds
and then multiplied by :t to get the final result. The
resulting algorithm, expanded to form an eight by eight
multiplication, is shown in figure 5. Note that although
the result is a full sixteen bits, the algorithm only performs eight bit additions and that only a single sixteen
bit shift operation is involved. This has the effect of
reducing both the code space and the execution time
for the routine.

1515-· II "::S-4ll1lf'1 -41 I'KRO RSSEItBLER, V2. 8
LOC OBJ

SEQ

sW1CE STRTEtalT

1 stKRCfILE

2 SIIUUDK H.WI'S. HEli)

3i *******-*-********************'"*****************-*******-*****-***
4.'*
•

•

•
7 i*==============--========--====--===S i*
9 i*
19 i*
11 i*
12 i*

13
All mnemonics copyrighted

12

.'*

THIS UTILlT'!' PROVIDES ff4 8 BY S UNSIGt£D IU.TIPL't'
RT ENTRY:
A = LOWER EIGHT BITS If liEST lNATJON (J>ERfH)
XA= LOn CARE
R1= POINTER TO SOORCE (J>ERfH) (1'Ill TJPum IN INl ERNAI.. 1'EI1E000'

to Intel Corporation

Figure 5

•
•*
•*
*

1979.

I

AP-49
LOC OBJ

SEQ

SOIJlCE STRTEMENT

14 ;*
15; *
16 ;*

*
'"

RT EXIT,

R = LOI6: EIGIH BITS OF RESULT
XA= UPPER EIGHT BITS OF RESUll
C = SET IF OI/E~lilol EL<;£ ClEff= DIVIDEND THEN
SET OVERFLOW ERROR FLAG
ELSE
IF S'DIVISOR>= DIVIDEND THEN
QUOTIENT(3]:= 1
DIVIDEND: = DIVIDEND- S'DIVISOR
ELSE
QUOTIENT(3]: = 0
ENDIF
IF 4'DIVISOR>= DIVIDEND THEN
QUOTIENT(2]: = 1
DIVIDEND: = DIVIDEND - 4'DIVISOR
ELSE
QUOTI ENT(2]: = 0
ENDIF
IF 2'DIVISOR>= DIVIDEND THEN
QUOTIENT(l]: = 1
DIVIDEND: = DIVIDEND - 2'DIVISOR
ELSE
QUOTIENT(l]: = 0
ENDIF
IF 1'DIVISOR> = DIVIDEND THEN
QUOTIENT(O]:= 1
DIVIDEND: = DIVIDEND - 1'DIVISOR
ELSE
OUOTlENT[O): = 0
ENDIF
ENDIF
END DIVIDE

14

The algorithm is easy to understand. The first test asks
if the division will fit into the dividend sixteen times. If it
will, the quotient cannot be expressed in only four bits
so an overflow error flag is set and the divide algorithm
ends. The algorithm then proceeds to determine if eight
times the divisor fits, four times, etc. After each test it
either sets or clears the appropriate quotient bit and
modifies the dividend. To see this algorithm in action,
consider the division of 15 by 5:
00001111
- 01010000

(15)
(16'5)

00001111
-00101000

(15)
(S'5)

00001111
- 00010100

'(15)
(4'5)

00001111
-00001010

(15)
(2'5)

Doesn't fit-no overflow

Doesn't flt-Q[3] = 0

Doesn't fit-O(2] = 0

00000101
00000101
-00000101
00000000

Fits-O[1] = 1
(15·2'5)
(1'5)
Fits-O(O] = 1

The result is 0 = 0011 which is the binary equivalent of
3-the correct answer. Clearly this algorithm can (and
has been) converted to a loop and used to perform divisions. An examination of the procedure, however, will
show that it has the same problems as the original mUltiply algorithm.

I

AP-49
The first problem is that double precision operations are
involved with both the comparison of the division with
the dividend and the conditional subtraction. The
second problem is that as the quotient bits are derived
they must be shifted into a register. In order to reduce
the register requirements, it would be desirable to shift
them into the divisor register as they are generated
since the divisor register gets shifted anyway. Unfor·
tunately the quotient bits are derived most significant
bits first so doing this will form a mirror image of the
quotient-not very useful.

When this algorithm is implemented on a computer
which does not have a direct compare instruction the
comparison is done by subtraction and the inner loop of
the algorithm is modified as follows:

REPEAT
DIVIDEND: = DIVIDEND'2
QUOTIENT: = QUOTIENT*2
DIVIDEND: = DIVIDEND - DIVISOR
IF BORROW = 0 THEN
QUOTIENT: = QUOTIENT + 1
ELSE
DIVIDEND: = DIVIDEND+ DIVISOR
ENDIF
COUNT: = COUNT - 1
UNTIL COUNT=O

Both of these problems can be solved by observing that
the algorithm presented for divide will still work if both
sides of all the "equations" involving the dividend are
divided by sixteen. The looping algorithm then would
proceed as follows:
DIVIDE:
QUOTIENT: = 0
COUNT: = 4
DIVIDEND: = DIVIDENDI16
IF DIVISOR>= DIVIDEND THEN
OVERFLOW FLAG: = 1
ELSE
REPEAT
DIVIDEND: = DIVIDEND'2
QUOTIENT: = QUOTIENT*2
IF DIVISOR> = DIVIDEND THEN
QUOTIENT: = QUOTIENT + 11'SET QUOTlENT[Ol'!
DIVIDEND: = DIVIDEND - DIVISOR
ENDIF
COUNT: = COUNT - 1
UNTIL COUNT=O
ENDIF
END DIVIDE

An implementation of this algorithm using the 8049 in·
struction set is shown in figure 6. This routine does an
unsigned divide of a 16 bit quantity by an eight bit quan·
tity. Since the multiply algorithm of figure 5 generates a
16 bit result from the multiplication of two eight bit
operands, these two routines complement each other
and can be used as part of more complex computations.

l5l5-]] W 5-48, 1JPH1 I'IfICI1O ASSEMBLER, 112. Ii

LOC OS.)

SOIJPCE

5EP
1

~:TATEMENT

$I'IAC~'OFILE

;: f1NClI.I[;£IF1DIV16 HE[;)

**********..*****************

! "t*.******~*·~*******.********",*",***************.* ...

4 . ,t

'"

'5 ;*
DIII1t.
..
6 ;*
7 . *=====================================================================*
8 ;..
..
THIS UTIUW ProvIDES ftj 16 B~' 8 I.lNSIGNE[! DIYID.
9 ;*
10 ; ..
AT ENTR',':
'"
A = Lrn.ER EIfjHT BllS OF rlfSTINATlON OPERAND
11 ;*
12 ; tXA= UPPEP UGHT BITS Of lilVIDEND
13 .•
1<1= POWlER TO [lIVlSOR HI INTERNAl. t1EM(lI.'Y
14 ; ..
*
15 ; '"
AT EXIT'
A = LOWER EIGHT BITS OF RESULl
*
XA= PEt1A INDER

.
.
.
.

Figure 6

AI! mnemonics copyrighted © Intel Corporation 1979.

I

15

AP-49

LOC OBJ

SOORCE STATEMENT

SEll

is ; t
C = SET IF OVHfLOW elSE CLEARED
*
19 .'.
*
213 .' **:+.*****~:.: t;**.f.::+.f:* ~.f:* «**·f;*:U:i·.f.***ic***fi*'~*******·fC***'i:,f.:*********,..***t**.**:01.******
21,
22 ;
2:' tlNfLIJDE( F1 L,IVI€. pr,ll
24 ,1 folV16
2"i ; 1 C(IIJIT =8
26 1 ['IVH'EN[>[1~,-9J=[IIVWfN[U5-8HHVISO~
'2? ; 1 II' 1l0RRow=e THEN i* IT FITS.',!
2S ;:<
SET OVERFl.O'J ~lfl(i
29 ; 1 ELSE
30 ;:;:
0E5TO~"E r,!'JrDENll
~i ,2
PEPERT
,,",;
[)1'./iDEND:=[lII/IDE~*2
13 : ~
ouormn =l~JOTIE~T*2
::4 ,]
[;I\iWEN[>[15-81=[HVWEN[l(1~-8J-i)IVISOF
35 ;,
IF 80""'01-1=1 THEN
;'6 ,4
>'E5TORE (iJ\!WEN!)
37 ':
ELSE
38 ,4
l)IJOTIENTUll =1
]0:; ':
EllL/IF
4,; ;,'
(:OU~-IT =COUNT-1
41 ; 2
IJtITlL (0I.lllT=9
42 ; 2
CLEAR OVERFLOW FLAG
43 ; 1 E~/Il;F
44 ,1
43
4~

E~/IlDI'/t:)E

, to'JfHES

47,

48
49 i~A
5tl cottn
51
':12 fEJECT

E9U
EQU

53 $INCLUDE( :Fl[;lV16i
54 ,.1 [11",116,
55 DIV16 :~CH
56 ; 1 C(lUNT' =13
'57
MC'"

58 ,1
009] 37
0094 61
BellS 37
0006 F600
lj~)(18 ~;'

~01J9

e424

ROIJTINE mRKS MOSTl',' WITH BJlS 15-8

H. :<:A
COUNT .• ~,

DIVlDEN[![i5-Bl=DIVlDEN['[1,)-3J-DIVISO~:

59

CF'L

A

6e

AN'

A, @Rl

61

Cf'L

A

62 .1 IF BOIiFOW=tl THEN /* [T F115'/
61
JC
~'IVI~
64 ;2
;ET OVERFLO~ FLf
*
6~
:: 7; *========:.=============================================*
8 ;.
9 ;,.
THIS UTILITY CONYERTS A 16 llli BlmR'r' IIfLUE 10 Bc.D
18 ,*
Al ENTIIV
•
11 .; *
A = lM~' EIGHT BlTS l., BlrtfI'r' \Ifl.IJE
*
12 ;
:~R= UPPER EIGHT BnS OF B!NAP'r' VIl.IJE
*
13 i *
R8= p:)mT~R TO i< rACKEe> BCD S1Rlt¥.l

*

*

14 i.
15 !*
16.;l
17 ;.
18

*
*

tiT EXli

~

A : IJNDEF INED
;<11= IJNDEFII£D
C : SET IF OVEFFLIlo: ElSE CLEARED

;t

19 ;.
29 ; *******~*****************.**.*.~**.***.*****

21 ;
22,

,.
,.

,..

*

••*****.**.****•.I<******************

2J SIN::lOOE(:F1CONOCl1. PDt)
24 •1 CON\'EI11-TO.SCI';
25 ! 1 EIl'W(:(. =0
26. 1 COUNT =16
27 1 REPEAT
2B.2
BIH:=BIN*2
29 ; 2
8CI) . =BC1>*2+CARRY
30 ; 2
IF CARIIV FROII BCDfa GOTO
11)2
1XlUNT:=rouNT-l
32 ) 1 UlITll (:OUNT=~
1J ; 1 00 CON\o'E!<'L To_sm

ER~

EXIT

34.,
1'5; EQL!ATES
36
'17 ;
}3 Y..A

J9 COUNT
40 ICNT
41 )

42 DIGPR

E!!U
E!!U

R2
R3

EQU

~4

EQU

3

43 .

44 fEJECT
4S $IHCUJt'F: F1 CON8CI))
46 .
47 TEI'IP1 SET
RS
48 ;
49 ,1 ;:ONI/E~LTO_BCD
~~ r~6ro

51 ; i BCDACC '=9
52
XCH

A,R8
Figu.. 7

All mnemonics copyrighted C Intel Corporalion 1979.

18

I

AP-49
LOt OSJ

I'I(W
5?
;-{CH
':.4
M(l'J
'55
'56 BroC(,f'l I'[iV

0001 A9

eoo2
OOlE
OOt1!5
0087
0098

SI)I.PCE 5HlW1ENT

SEQ

P~?

1:1100
19
E':05

'5,

IIIC
DJIl:
; 1 COVliT =1';
i'KlV

53
~9
~\3

~'1. fj

ft,110
ICNT,'DI~

i.f11,l0e
Pi
ICNT. Bet:{iJA
COUNT., 116

61 ·1 ~E?ERT
62 E:Wff.IB
~::

.;:

li:N: =SIN.;;

008C 97

~4

CLP

(:

~!'7

65

Pte
XCH

ft

OOIJE 2ft
9I.l9F F7
0018 ~A
0011

RLC
t:9 ; 2
79

~8

A.XfI
A

y.cH
fI.. :ifI
BCI) . =8CO*2tCflP.l1Y
litH
fl. R8

0012 A9

71

I'[iV

Rl,fj

0013 28
0014 Bce3

0016 Ali
0017 Fl

72
?3
74
7'5 8('[JOC

XCH
PlOY
p!oY
PlOY

A.. R9
ICNT.IDIGPR
TEMP1. R

!:l91S 71

76

ffiOC

~1019

001E: 19
001C Eet?

77
78
79
S0

Of;
PlOV
INC
I)

!JelE F[J

Sl

00lF F624

83
84 ; 2
crAllfT =COUNT-1
85 ; 1 UNTIL COIJHT=9

0021 EBOC

B6
S7

57

iJI.Ilf1 M1

ft. @Pj,
A. ~1
A

@Ri. A
R1
lOll .IlCCOC
1'1011
fl. TEI1I'1
IF CARRY FPOM BCDfICC G010 ERROR EXIT
Je
BrOCO!)

mz

~2;

2

r- .lNZ

CWIIT, BCOCOB
ClR
C ; CLEAR CARRY TO WDICATE ta:HAl
as ;1 END CIlN\I[RL TO_BCD
89 BCOCO~ RET
ge Elf'

0023 97

TERMINATI~j

USER SYI1EiOlS

E:COCOA iiOOS
TEMP1 0005
ffSSEM8L~'

BCDCoe 000C
~'A
0002

COtIl'LETE,

~

BroCOO 0024

Bt..'DOC 0017

Cllle[! 0008

COUNT 0093

0II»R

888~

100

M4

ERIIORS

Figure 7 (continued)
All mnemonics copyrighted C> Intel Corporation 1979.

I

19

AP-49
The conversion of a BCD value to binary is essentially
the same process as converting a binary value to BCD.

BIN = 10' BIN = (2) • (5) • (BIN)= 2' (2 • 2+ 1) • BIN

CONVERLTO.BINARY
BIN:=O
COUNT: = DIGNO
REPEAT
BCDACCUM: = BCDACCUM • 10
BIN: = 10 • BIN + CARRY DIGIT
COUNT: = COUNT - 1
UNTIL COUNT = 0
END CONVERT_TO_BINARY
The only complexity is the two multiplications by ten.
The BCDACCUM can be multiplied by ten by shifting It
left four places (one digit). The variable BIN could be
multiplied using the multiply algorithm already dis·
cussed, but It Is usually more efficient to do this by mak·

ISIS-I! HCS-4:;:/uPl-41 I'IftCRO ASSEI'IBlEP . V2.

lor OSJ

SEQ

ing the following substitution:

This implies that the value 10 • BIN can be generated by
saving the value of BIN and then shifting BIN two places
left. After this the original value of BIN can be added to
the new value of BIN (forming 5' BIN) and then BIN can
be multiplied by two. It is often possible to Implement
the multiplication of a value by a constant by using such
techniques. Figure 8 shows an 8049 routine which con·
verts BCD values to binary. This routine differs slightly
from the algorithm above in that the BCD digits are read,
and converted to binary, two digits at a time. Protection
has also been added to detect BCD operands which, If
converted, would yield binary values beyond the range
of the result.

(1

5(1J1!Cl STATEMENT

1 mH(ROFlLE
2 $INCUJDE( F1CCtlBIN.I£[»
3:
4 :l
'"
C!HlIN
5
6 .:'
7 ; *========================================--======*
8 ;*
9 :.
THIS umnv CO,.."ERTS A 6 DIGIT ero VAll.( TO fH~Y
18 ,.
AT ENTI"Y·
110= POINTER TO A PACKEt> BC{l STRHIi
11 : '"

********.*********.....***************.****.***___••**_......_***
.:*
'"

'"
'"
'"
'"

12 :.
13 ; *

14.:*
1~

i'
i'

16
17 .;

*

AT EXIT:
A = UJIER Wi/H BITS (J' THE BI~Y RESlll
Xfl= UPPER EIGHT BITS (J' THE BINff'Y RESLlT
C = SET IF OVERflOW ElSE CLEAREI>

'"
*

'•"

•
•*

18 : ************"'**.*****~~*'I<***----***-"'-****'''''**'''****.-**'I,*
19.:

21 $lr1:LIM:( ·F1:C0N3IN. PDl)
22.:
23
24
25
26
27
2B
29

.
.: 1 efMt'ERLTO_8INlF~'
.: 1 POINTERS :=PQINTER0+DIGITPRIR-l
:1 CWlT:=DIGITPRIR
; 1 BIN:=t'
: 1 REPEAT
:2
BIN·=BIN*lC
~ .: 2
BIN:=BIII+MEH(Rll)[7-4J
11 : 2
BIN· =BIN*l@
32 .: 2
BIN =BIN+I1EH(RIl)n-eJ

All mnemonics copyrighted © Intel Corporation 1979.

20

I

AP-49
Lot reJ

SEQ

SOORCE STATEI£NT

33 ·2
POI'lTERIJ =POINTER0-1
34.2
OOJIT=CWIT-1
35 • 1 ltlT!l COlINT =0
36 . 1 END CON'fERUO_BlNARV
38 . EQlJRTES
39 . ==--====
49'
41 XA
112
EIlIJ
42 GOIllT EPll
R3
43 ICNT
EQU
R4
44 :
45 DIGPR EQU
l
46 :
47 $EJECT
48 $INClUDE( "Fi:C(HlIN)
49.

59 TEII'1
51 TEll';;:
S2
53
54
55
56

57
58
59
9IJIi!4 88113

69
61

SET
SET

R5
R6

:
.: 1 CON~'ERUO_BINfIRY
COIeIN:
.: 1 POINTER9:=POINTER0+DIGITPAIR-l
1'10\1
A.1<0
roD
A.IOIGPI1-1
my
RlI . A
; 1 COliNT =DIGITPAIR
1'10'1
tllUNT. 10 IGPR
.: 1 BIN =0

0006 27

62

CL~

A

0007 flfI

E::

HQY

gAo A

64 : 1 REPEAT
65 CGNBLP:
E'£:2
BIN:=BI~18

67
68
69 : 2

ttIJOC

fit)

~F9

009E 47
009F 530F

0011 61)
0012 2tI
0013 1399
0015 2A

0916 F62A
9918 1428
OO1A F62A
a01e
0il1D
aB1E
9920
9921

AD
Fe
5~9F

6D
2A

CflL

CONBtIJ

.]C
CONBER
BIN.=BIN+I'EM(RlI)[7-4J

79
71
72
73
74

11f.N
'10\1

TEI'IP1, A

SW

('5
76

XCH

A
A. tllfH
~, TEl1I'l
A. XA
A.. tOO
A.. XA
C(H;£R

~

(,

78
79 ;2
80

81
82 :2
33

ANI..
A[oD

fU·C
XCH
JC

R.~

~IN.=81N*lEt

CALL

Je

CON810
COIlSER

SIN =BIN+MEI'1(RI})[3-9J
MOV
TEi'1P1.A

A.@R1l

84

I'1OY

35
Sf.
87

ANL

A.I0FH

ROO

A. TEtlPl

XCH

A,XA

All mnemonics copyrighted © Intel Corporation 1979.

I

21

AP-49
LOC OIl)

SOURCE STATEI'IENT

SEQ
SB
S9

0028 EB0S

Allot
11, 100
XCH
11,~
90
JC
COIflEP
91 ; 2
POltlTER9. =POINTER0-1
92
DEC
R9
93 ; 2
COIJIT .=COUNT-1
94 ,1 lJNllL COI.IIT=l:l
95
[\.J112
COUNT, C~BLP

00211 83

96; 1 00 CON\IE11T _TO_BINAR','
97 CI)1BER. liET

0022 l:l1Xl
0024 2A
00£"5 ~(.2A
0027 CB

0028
tfe2C
002[l
002E

AD
214

8I1~F

97

OO:l{t
0031
0032
0031
0014

F7
2A
F7
2f1
Ff46

9B $EJECT
99
=100
= 101
lITIllW TO I1lILTlPL¥ BIN BI' 10
= 192
CAP.P.\' WILL BE SET IF OI/ERFL()oI OCCURS
= 103 ;
= 104 C0Na1e. 1'1()\r'
TEm. A .• SAVE A
= 105
A,XA
; !iAYE ~
XCH
= 106
TEI'IP2,A
I'tOV
A, >:A
XCH
" 107
= 108 ,
= 109
CLR
c
RLC
A
BIN:=BIN*2
" 110
A.. XA
XCH
" 111
RLC
A
" 112
A,XA
=113
Xf'Ji
= 114
JC
CIltiE .' ERROR 011 OIIERFLOW

AE
2A

" 115
0016 F7

" 116
= 117
= 118
= 119

8€G7 2A
003S F7
0039 2P.
OO~

F646

003C
0830
003E
003:F
0040

6[-

= 129
= 121
= 122
= 123
= 124

2A

IE
2A
F646

0046 83

136

A

XCH

A,~

fI

XCI{
JC

fI,~

AOD
XCH

A, TEMPi; BIN.=8IN~5
A, \(fl
A, TEMP2
A, XA
COIlB1E
ERROR ON OVERFLOW

XCH
JC

COllllE ; ERRU<

RL(;

fI

XCH

R,XA

RLC

A
A,XA

~ C(1'IPLETE,

; 8111:=81,..4

RLC

fU('

" 125
= 126
" 127
" 128
= 129
" 130
" 1St
" 132
" 133 COliS1E
= 134
" 135 ;

8042 F7
0043 2A
0044 F7
9045 2A

PLe

COIlBIN B009

CONBLP 9008

COUNT 8083

DIGPR II1II33

ICNT

0004

0002

NO ERROIIS

All mnemonics copyrighted © Intel Corporation 1979.

22

I

AP-49

CONCLUSION
The design goals of the full duplex serial communications software were realized; if transmission and recep·
tion are occurring concurrently, only 42 percent of the
real time available to the 8049 will be consumed by the
serial link. This implies that an 8049 running full duplex
serial 1/0 will still outperform earlier members of the
family running without the serial 1/0 requirement. It is
also possible to run this program in an 8048 or 8748 at
1200 baud with the same 42 percent CPU utilization.
The execution times for the other routines that have
been discussed have been summarized in Table 1. All of
these routines were written to maintain maximum use·
ability rather than minimum code size or execution time.
The resulting execution times and code size are there·
fore what the user can expect to see in a real applica·
tion. The results that were obtained clearly show the ef·
ficiency and speed of the 8049. The equivalent times for
the 8048 are also shown. It is clear that the 8049 repre·
sents a substantial performance advantage over the
8048. Considering, in most applications, that the 8048 is

I

the highest performance microcomputer available to
date, the performance advantage of the 8049 should
allow the cost benefits of a single chip microcomputer
to be realized in many applications which up until now
have required too much "computer power" for a single
chip approach.

EXECUTION TIME
(MICROSECONDS)
BYTES

8049

8048

MPY8

21

109

200

DIV 16

37

183 MIN
204 MAX

335 MIN
375 MAX

CON BCD

36

733

1348

CONBIN

70

388

713

--

Table 1. Program Performance

23



---

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