ARM Architecture Reference Manual
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- Contents
- Preface
- CPU Architecture
- Introduction to the ARM Architecture
- Programmers’ Model
- A2.1 Data types
- A2.2 Processor modes
- A2.3 Registers
- A2.4 General-purpose registers
- A2.5 Program status registers
- A2.6 Exceptions
- A2.6.1 ARMv6 extensions to the exception model
- A2.6.2 Reset
- A2.6.3 Undefined Instruction exception
- A2.6.4 Software Interrupt exception
- A2.6.5 Prefetch Abort (instruction fetch memory abort)
- A2.6.6 Data Abort (data access memory abort)
- A2.6.7 Imprecise data aborts
- A2.6.8 Interrupt request (IRQ) exception
- A2.6.9 Fast interrupt request (FIQ) exception
- A2.6.10 Exception priorities
- A2.6.11 High vectors
- A2.6.12 Vectored interrupt support
- A2.6.13 Low interrupt latency configuration
- A2.6.14 New instructions to improve exception handling
- A2.7 Endian support
- A2.8 Unaligned access support
- A2.9 Synchronization primitives
- A2.10 The Jazelle Extension
- A2.11 Saturated integer arithmetic
- The ARM Instruction Set
- A3.1 Instruction set encoding
- A3.2 The condition field
- A3.3 Branch instructions
- A3.4 Data-processing instructions
- A3.5 Multiply instructions
- A3.6 Parallel addition and subtraction instructions
- A3.7 Extend instructions
- A3.8 Miscellaneous arithmetic instructions
- A3.9 Other miscellaneous instructions
- A3.10 Status register access instructions
- A3.11 Load and store instructions
- A3.12 Load and Store Multiple instructions
- A3.13 Semaphore instructions
- A3.14 Exception-generating instructions
- A3.15 Coprocessor instructions
- A3.16 Extending the instruction set
- A3.16.1 Media instruction space
- A3.16.2 Multiply instruction extension space
- A3.16.3 Control and DSP instruction extension space
- A3.16.4 Load/store instruction extension space
- A3.16.5 Architecturally Undefined Instruction space
- A3.16.6 Coprocessor instruction extension space
- A3.16.7 Unconditional instruction extension space
- ARM Instructions
- A4.1 Alphabetical list of ARM instructions
- A4.1.1 General notes
- A4.1.2 ADC
- A4.1.3 ADD
- A4.1.4 AND
- A4.1.5 B, BL
- A4.1.6 BIC
- A4.1.7 BKPT
- A4.1.8 BLX (1)
- A4.1.9 BLX (2)
- A4.1.10 BX
- A4.1.11 BXJ
- A4.1.12 CDP
- A4.1.13 CLZ
- A4.1.14 CMN
- A4.1.15 CMP
- A4.1.16 CPS
- A4.1.17 CPY
- A4.1.18 EOR
- A4.1.19 LDC
- A4.1.20 LDM (1)
- A4.1.21 LDM (2)
- A4.1.22 LDM (3)
- A4.1.23 LDR
- A4.1.24 LDRB
- A4.1.25 LDRBT
- A4.1.26 LDRD
- A4.1.27 LDREX
- A4.1.28 LDRH
- A4.1.29 LDRSB
- A4.1.30 LDRSH
- A4.1.31 LDRT
- A4.1.32 MCR
- A4.1.33 MCRR
- A4.1.34 MLA
- A4.1.35 MOV
- A4.1.36 MRC
- A4.1.37 MRRC
- A4.1.38 MRS
- A4.1.39 MSR
- A4.1.40 MUL
- A4.1.41 MVN
- A4.1.42 ORR
- A4.1.43 PKHBT
- A4.1.44 PKHTB
- A4.1.45 PLD
- A4.1.46 QADD
- A4.1.47 QADD16
- A4.1.48 QADD8
- A4.1.49 QADDSUBX
- A4.1.50 QDADD
- A4.1.51 QDSUB
- A4.1.52 QSUB
- A4.1.53 QSUB16
- A4.1.54 QSUB8
- A4.1.55 QSUBADDX
- A4.1.56 REV
- A4.1.57 REV16
- A4.1.58 REVSH
- A4.1.59 RFE
- A4.1.60 RSB
- A4.1.61 RSC
- A4.1.62 SADD16
- A4.1.63 SADD8
- A4.1.64 SADDSUBX
- A4.1.65 SBC
- A4.1.66 SEL
- A4.1.67 SETEND
- A4.1.68 SHADD16
- A4.1.69 SHADD8
- A4.1.70 SHADDSUBX
- A4.1.71 SHSUB16
- A4.1.72 SHSUB8
- A4.1.73 SHSUBADDX
- A4.1.74 SMLA<x><y>
- A4.1.75 SMLAD
- A4.1.76 SMLAL
- A4.1.77 SMLAL<x><y>
- A4.1.78 SMLALD
- A4.1.79 SMLAW<y>
- A4.1.80 SMLSD
- A4.1.81 SMLSLD
- A4.1.82 SMMLA
- A4.1.83 SMMLS
- A4.1.84 SMMUL
- A4.1.85 SMUAD
- A4.1.86 SMUL<x><y>
- A4.1.87 SMULL
- A4.1.88 SMULW<y>
- A4.1.89 SMUSD
- A4.1.90 SRS
- A4.1.91 SSAT
- A4.1.92 SSAT16
- A4.1.93 SSUB16
- A4.1.94 SSUB8
- A4.1.95 SSUBADDX
- A4.1.96 STC
- A4.1.97 STM (1)
- A4.1.98 STM (2)
- A4.1.99 STR
- A4.1.100 STRB
- A4.1.101 STRBT
- A4.1.102 STRD
- A4.1.103 STREX
- A4.1.104 STRH
- A4.1.105 STRT
- A4.1.106 SUB
- A4.1.107 SWI
- A4.1.108 SWP
- A4.1.109 SWPB
- A4.1.110 SXTAB
- A4.1.111 SXTAB16
- A4.1.112 SXTAH
- A4.1.113 SXTB
- A4.1.114 SXTB16
- A4.1.115 SXTH
- A4.1.116 TEQ
- A4.1.117 TST
- A4.1.118 UADD16
- A4.1.119 UADD8
- A4.1.120 UADDSUBX
- A4.1.121 UHADD16
- A4.1.122 UHADD8
- A4.1.123 UHADDSUBX
- A4.1.124 UHSUB16
- A4.1.125 UHSUB8
- A4.1.126 UHSUBADDX
- A4.1.127 UMAAL
- A4.1.128 UMLAL
- A4.1.129 UMULL
- A4.1.130 UQADD16
- A4.1.131 UQADD8
- A4.1.132 UQADDSUBX
- A4.1.133 UQSUB16
- A4.1.134 UQSUB8
- A4.1.135 UQSUBADDX
- A4.1.136 USAD8
- A4.1.137 USADA8
- A4.1.138 USAT
- A4.1.139 USAT16
- A4.1.140 USUB16
- A4.1.141 USUB8
- A4.1.142 USUBADDX
- A4.1.143 UXTAB
- A4.1.144 UXTAB16
- A4.1.145 UXTAH
- A4.1.146 UXTB
- A4.1.147 UXTB16
- A4.1.148 UXTH
- A4.2 ARM instructions and architecture versions
- A4.1 Alphabetical list of ARM instructions
- ARM Addressing Modes
- A5.1 Addressing Mode 1 - Data-processing operands
- A5.1.1 Encoding
- A5.1.2 The shifter operand
- A5.1.3 Data-processing operands - Immediate
- A5.1.4 Data-processing operands - Register
- A5.1.5 Data-processing operands - Logical shift left by immediate
- A5.1.6 Data-processing operands - Logical shift left by register
- A5.1.7 Data-processing operands - Logical shift right by immediate
- A5.1.8 Data-processing operands - Logical shift right by register
- A5.1.9 Data-processing operands - Arithmetic shift right by immediate
- A5.1.10 Data-processing operands - Arithmetic shift right by register
- A5.1.11 Data-processing operands - Rotate right by immediate
- A5.1.12 Data-processing operands - Rotate right by register
- A5.1.13 Data-processing operands - Rotate right with extend
- A5.2 Addressing Mode 2 - Load and Store Word or Unsigned Byte
- A5.2.1 Encoding
- A5.2.2 Load and Store Word or Unsigned Byte - Immediate offset
- A5.2.3 Load and Store Word or Unsigned Byte - Register offset
- A5.2.4 Load and Store Word or Unsigned Byte - Scaled register offset
- A5.2.5 Load and Store Word or Unsigned Byte - Immediate pre-indexed
- A5.2.6 Load and Store Word or Unsigned Byte - Register pre-indexed
- A5.2.7 Load and Store Word or Unsigned Byte - Scaled register pre-indexed
- A5.2.8 Load and Store Word or Unsigned Byte - Immediate post-indexed
- A5.2.9 Load and Store Word or Unsigned Byte - Register post-indexed
- A5.2.10 Load and Store Word or Unsigned Byte - Scaled register post-indexed
- A5.3 Addressing Mode 3 - Miscellaneous Loads and Stores
- A5.3.1 Encoding
- A5.3.2 Miscellaneous Loads and Stores - Immediate offset
- A5.3.3 Miscellaneous Loads and Stores - Register offset
- A5.3.4 Miscellaneous Loads and Stores - Immediate pre-indexed
- A5.3.5 Miscellaneous Loads and Stores - Register pre-indexed
- A5.3.6 Miscellaneous Loads and Stores - Immediate post-indexed
- A5.3.7 Miscellaneous Loads and Stores - Register post-indexed
- A5.4 Addressing Mode 4 - Load and Store Multiple
- A5.5 Addressing Mode 5 - Load and Store Coprocessor
- A5.1 Addressing Mode 1 - Data-processing operands
- The Thumb Instruction Set
- Thumb Instructions
- A7.1 Alphabetical list of Thumb instructions
- A7.1.1 General notes
- A7.1.2 ADC
- A7.1.3 ADD (1)
- A7.1.4 ADD (2)
- A7.1.5 ADD (3)
- A7.1.6 ADD (4)
- A7.1.7 ADD (5)
- A7.1.8 ADD (6)
- A7.1.9 ADD (7)
- A7.1.10 AND
- A7.1.11 ASR (1)
- A7.1.12 ASR (2)
- A7.1.13 B (1)
- A7.1.14 B (2)
- A7.1.15 BIC
- A7.1.16 BKPT
- A7.1.17 BL, BLX (1)
- A7.1.18 BLX (2)
- A7.1.19 BX
- A7.1.20 CMN
- A7.1.21 CMP (1)
- A7.1.22 CMP (2)
- A7.1.23 CMP (3)
- A7.1.24 CPS
- A7.1.25 CPY
- A7.1.26 EOR
- A7.1.27 LDMIA
- A7.1.28 LDR (1)
- A7.1.29 LDR (2)
- A7.1.30 LDR (3)
- A7.1.31 LDR (4)
- A7.1.32 LDRB (1)
- A7.1.33 LDRB (2)
- A7.1.34 LDRH (1)
- A7.1.35 LDRH (2)
- A7.1.36 LDRSB
- A7.1.37 LDRSH
- A7.1.38 LSL (1)
- A7.1.39 LSL (2)
- A7.1.40 LSR (1)
- A7.1.41 LSR (2)
- A7.1.42 MOV (1)
- A7.1.43 MOV (2)
- A7.1.44 MOV (3)
- A7.1.45 MUL
- A7.1.46 MVN
- A7.1.47 NEG
- A7.1.48 ORR
- A7.1.49 POP
- A7.1.50 PUSH
- A7.1.51 REV
- A7.1.52 REV16
- A7.1.53 REVSH
- A7.1.54 ROR
- A7.1.55 SBC
- A7.1.56 SETEND
- A7.1.57 STMIA
- A7.1.58 STR (1)
- A7.1.59 STR (2)
- A7.1.60 STR (3)
- A7.1.61 STRB (1)
- A7.1.62 STRB (2)
- A7.1.63 STRH (1)
- A7.1.64 STRH (2)
- A7.1.65 SUB (1)
- A7.1.66 SUB (2)
- A7.1.67 SUB (3)
- A7.1.68 SUB (4)
- A7.1.69 SWI
- A7.1.70 SXTB
- A7.1.71 SXTH
- A7.1.72 TST
- A7.1.73 UXTB
- A7.1.74 UXTH
- A7.2 Thumb instructions and architecture versions
- A7.1 Alphabetical list of Thumb instructions
- Memory and System Architectures
- Introduction to Memory and System Architectures
- Memory Order Model
- B2.1 About the memory order model
- B2.2 Read and write definitions
- B2.3 Memory attributes prior to ARMv6
- B2.4 ARMv6 memory attributes - introduction
- B2.5 Ordering requirements for memory accesses
- B2.6 Memory barriers
- B2.7 Memory coherency and access issues
- B2.7.1 Introduction to cache coherency
- B2.7.2 Ordering of cache maintenance operations in the memory order model
- B2.7.3 TLB maintenance operations and the memory order model
- B2.7.4 Synchronization primitives and the memory order model
- B2.7.5 Branch predictor maintenance operations and the memory order model
- B2.7.6 Changes to CP15 registers and the memory order model
- B2.7.7 Changes to CPSR and the memory order model
- The System Control Coprocessor
- Virtual Memory System Architecture
- B4.1 About the VMSA
- B4.2 Memory access sequence
- B4.3 Memory access control
- B4.4 Memory region attributes
- B4.5 Aborts
- B4.6 Fault Address and Fault Status registers
- B4.7 Hardware page table translation
- B4.7.1 Translation table base
- B4.7.2 First-level fetch
- B4.7.3 Page table translation in VMSAv6
- B4.7.4 First-level descriptors
- B4.7.5 Sections and supersections
- B4.7.6 Coarse page table descriptor
- B4.7.7 Second-level descriptor - Coarse page table format
- B4.7.8 Translating page references in coarse page tables
- B4.8 Fine page tables and support of tiny pages
- B4.9 CP15 registers
- B4.9.1 Register 0: TLB type register (VMSAv6)
- B4.9.2 Register 1: Control register
- B4.9.3 Register 2: Translation table base
- B4.9.4 Register 3: Domain access control
- B4.9.5 Register 4: Reserved
- B4.9.6 Register 5: Fault status
- B4.9.7 Register 6: Fault Address register
- B4.9.8 Register 8: TLB functions
- B4.9.9 Register 10: TLB lockdown
- B4.9.10 Register 13: Process ID
- Protected Memory System Architecture
- B5.1 About the PMSA
- B5.2 Memory access sequence
- B5.3 Memory access control
- B5.4 Memory access attributes
- B5.5 Memory aborts (PMSAv6)
- B5.6 Fault Status and Fault Address register support
- B5.7 CP15 registers
- B5.7.1 Register 0: MPU type register (PMSAv6)
- B5.7.2 Register 1: Control register
- B5.7.3 Register 2: Cacheability bits (prePMSAv6)
- B5.7.4 Register 3: Bufferability bits (prePMSAv6)
- B5.7.5 Registers 4, 8, 10, 11, 12 and 14: Reserved
- B5.7.6 Register 5: Access permission bits (prePMSAv6)
- B5.7.7 Register 5: Fault status (PMSAv6)
- B5.7.8 Register 6: Memory region programming (prePMSAv6)
- B5.7.9 Fault address (PMSAv6)
- B5.7.10 Register 6: Memory region programming (PMSAv6)
- B5.7.11 Registers 7 and 9: Cache and write buffer control
- B5.7.12 Register 13: Process ID (PMSAv6)
- Caches and Write Buffers
- B6.1 About caches and write buffers
- B6.2 Cache organization
- B6.3 Types of cache
- B6.4 L1 cache
- B6.5 Considerations for additional levels of cache
- B6.6 CP15 registers
- B6.6.1 Register 0: cache type
- B6.6.2 Cache Type register
- B6.6.3 Cache size fields
- B6.6.4 Register 1: cache and write buffer control bits
- B6.6.5 Register 7: cache management functions
- B6.6.6 Block transfer operations using CP15 Register 7
- B6.6.7 Cache cleaning and invalidating operations for TCM configured as SmartCache
- B6.6.8 Additional levels of cache
- B6.6.9 Register 9: cache lockdown functions
- Tightly Coupled Memory
- B7.1 About TCM
- B7.2 TCM configuration and control
- B7.3 Accesses to TCM and cache
- B7.4 Level 1 (L1) DMA model
- B7.5 L1 DMA control using CP15 Register 11
- B7.5.1 User Access to Cp15 Register 11 operations
- B7.5.2 Identification and Status Registers
- B7.5.3 User Accessibility Register
- B7.5.4 Channel Number Register
- B7.5.5 Enable Registers
- B7.5.6 Control Registers
- B7.5.7 Internal Start Address Registers
- B7.5.8 External Start Address Registers
- B7.5.9 Internal End Address Registers
- B7.5.10 Channel Status Registers
- B7.5.11 Context ID Registers
- Fast Context Switch Extension
- Vector Floating-point Architecture
- Introduction to the Vector Floating-point Architecture
- VFP Programmer’s Model
- VFP Instruction Set Overview
- C3.1 Data-processing instructions
- C3.2 Load and Store instructions
- C3.3 Single register transfer instructions
- C3.4 Two-register transfer instructions
- VFP Instructions
- C4.1 Alphabetical list of VFP instructions
- C4.1.1 FABSD
- C4.1.2 FABSS
- C4.1.3 FADDD
- C4.1.4 FADDS
- C4.1.5 FCMPD
- C4.1.6 FCMPED
- C4.1.7 FCMPES
- C4.1.8 FCMPEZD
- C4.1.9 FCMPEZS
- C4.1.10 FCMPS
- C4.1.11 FCMPZD
- C4.1.12 FCMPZS
- C4.1.13 FCPYD
- C4.1.14 FCPYS
- C4.1.15 FCVTDS
- C4.1.16 FCVTSD
- C4.1.17 FDIVD
- C4.1.18 FDIVS
- C4.1.19 FLDD
- C4.1.20 FLDMD
- C4.1.21 FLDMS
- C4.1.22 FLDMX
- C4.1.23 FLDS
- C4.1.24 FMACD
- C4.1.25 FMACS
- C4.1.26 FMDHR
- C4.1.27 FMDLR
- C4.1.28 FMDRR
- C4.1.29 FMRDH
- C4.1.30 FMRDL
- C4.1.31 FMRRD
- C4.1.32 FMRRS
- C4.1.33 FMRS
- C4.1.34 FMRX
- C4.1.35 FMSCD
- C4.1.36 FMSCS
- C4.1.37 FMSR
- C4.1.38 FMSRR
- C4.1.39 FMSTAT
- C4.1.40 FMULD
- C4.1.41 FMULS
- C4.1.42 FMXR
- C4.1.43 FNEGD
- C4.1.44 FNEGS
- C4.1.45 FNMACD
- C4.1.46 FNMACS
- C4.1.47 FNMSCD
- C4.1.48 FNMSCS
- C4.1.49 FNMULD
- C4.1.50 FNMULS
- C4.1.51 FSITOD
- C4.1.52 FSITOS
- C4.1.53 FSQRTD
- C4.1.54 FSQRTS
- C4.1.55 FSTD
- C4.1.56 FSTMD
- C4.1.57 FSTMS
- C4.1.58 FSTMX
- C4.1.59 FSTS
- C4.1.60 FSUBD
- C4.1.61 FSUBS
- C4.1.62 FTOSID
- C4.1.63 FTOSIS
- C4.1.64 FTOUID
- C4.1.65 FTOUIS
- C4.1.66 FUITOD
- C4.1.67 FUITOS
- C4.1 Alphabetical list of VFP instructions
- VFP Addressing Modes
- C5.1 Addressing Mode 1 - Single-precision vectors (non-monadic)
- C5.2 Addressing Mode 2 - Double-precision vectors (non-monadic)
- C5.3 Addressing Mode 3 - Single-precision vectors (monadic)
- C5.4 Addressing Mode 4 - Double-precision vectors (monadic)
- C5.5 Addressing Mode 5 - VFP load/store multiple
- Debug Architecture
- Introduction to the Debug Architecture
- Debug Events and Exceptions
- Coprocessor 14, the Debug Coprocessor
- D3.1 Coprocessor 14 debug registers
- D3.2 Coprocessor 14 debug instructions
- D3.3 Debug register reference
- D3.3.1 Register 0, Debug ID Register (DIDR)
- D3.3.2 Register 1, Debug Status and Control Register (DSCR)
- Core halted, bit[0]
- Core Restarted, bit[1]
- Method of Debug Entry, bits[5:2]
- Sticky Precise Abort, bit[6]
- Sticky Imprecise Abort, bit[7]
- DbgAck, bit[10]
- Interrupts Disable, bit[11]
- User mode access to Comms Channel disable, bit[12]
- Execute ARM Instruction enable, bit[13]
- Halting/Monitor debug-mode select, bit[14]
- Monitor debug-mode enable, bit[15]
- wDTRfull: wDTR register full, bit[29]
- rDTRfull: rDTR register full, bit[30]
- D3.3.3 Register 5, Data Transfer Register (DTR)
- D3.3.4 Register 6, Watchpoint Fault Address Register (WFAR)
- D3.3.5 Register 7, Vector Catch Register (VCR)
- D3.3.6 Registers 64-79, Breakpoint Value Registers (BVR)
- D3.3.7 Registers 80-95, Breakpoint Control Registers (BCR)
- D3.3.8 Registers 96-111, Watchpoint Value Registers (WVR)
- D3.3.9 Registers 112-127, Watchpoint Control Registers (WCR)
- D3.4 Reset values of the CP14 debug registers
- D3.5 Access to CP14 debug registers from the external debug interface
- Glossary