ARM Cortex M7 Processor Technical Reference Manual
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- ARM Cortex-M7 Processor Technical Reference Manual
- Contents
- Preface
- 1: Introduction
- 1.1 About the Cortex-M7 processor
- 1.2 Component blocks
- 1.2.1 Data Processing Unit
- 1.2.2 Prefetch Unit
- 1.2.3 Load Store Unit
- 1.2.4 Floating Point Unit
- 1.2.5 Nested Vectored Interrupt Controller
- 1.2.6 Wake-up Interrupt Controller
- 1.2.7 Memory System
- 1.2.8 Store Buffer
- 1.2.9 Memory Protection Unit
- 1.2.10 Cortex-M7 Processor and PPB ROM tables
- 1.2.11 Cross Trigger Interface Unit
- 1.2.12 ETM
- 1.2.13 Debug and trace components
- 1.3 Interfaces
- 1.4 Supported standards
- 1.5 Design process
- 1.6 Documentation
- 1.7 Product revisions
- 2: Programmers Model
- 3: System Control
- 3.1 About system control
- 3.2 Register summary
- 3.3 Register descriptions
- 3.3.1 Auxiliary Control Register
- 3.3.2 CPUID Base Register
- 3.3.3 Cache Level ID Register
- 3.3.4 Cache Size ID Register
- 3.3.5 Cache Size Selection Register
- 3.3.6 Instruction and Data Tightly-Coupled Memory Control Registers
- 3.3.7 AHBP Control Register
- 3.3.8 L1 Cache Control Register
- 3.3.9 Auxiliary Bus Fault Status Register
- 3.3.10 Instruction Error bank Register 0-1
- 3.3.11 Data Error bank Register 0-1
- 3.3.12 AHB Slave Control Register
- 4: Initialization
- 5: Memory System
- 6: Memory Protection Unit
- 7: Nested Vectored Interrupt Controller
- 8: Floating Point Unit
- 9: Debug
- 10: Cross Trigger Interface
- 11: Data Watchpoint and Trace Unit
- 12: Instrumentation Trace Macrocell Unit
- 13: Fault detection and handling
- A: Revisions