ARM Architecture Reference Manual ARMv7 A And R Edition ARM.arm

DDI0406C_C_arm_architecture_reference_manual

arm_architecture_reference_manual

DDI0406C_C_arm_architecture_reference_manual

01_armv7_architecture_reference_manual

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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
Contents
Preface
- About this manual
- Using this manual
- Conventions
- Additional reading
  - ARM publications
  - Other publications
- Feedback
  - Feedback on this manual
Part A: Application Level Architecture
A1: Introduction to the ARM Architecture
- A1.1 About the ARM architecture
- A1.2 The instruction sets
  - A1.2.1 Execution environment support
- A1.3 Architecture versions, profiles, and variants
  - A1.3.1 Debug architecture versions
- A1.4 Architecture extensions
  - A1.4.1 Instruction set architecture extensions
  - A1.4.2 Architecture extensions
- A1.5 The ARM memory model
A2: Application Level Programmers’ Model
- A2.1 About the Application level programmers’ model
  - A2.1.1 Instruction sets, arithmetic operations, and register files
- A2.2 ARM core data types and arithmetic
  - A2.2.1 Integer arithmetic
- A2.3 ARM core registers
  - A2.3.1 Writing to the PC
  - A2.3.2 Pseudocode details of operations on ARM core registers
- A2.4 The Application Program Status Register (APSR)
- A2.5 Execution state registers
- A2.6 Advanced SIMD and Floating-point Extensions
- A2.7 Floating-point data types and arithmetic
- A2.8 Polynomial arithmetic over {0, 1}
  - A2.8.1 Pseudocode details of polynomial multiplication
- A2.9 Coprocessor support
- A2.10 Thumb Execution Environment
  - A2.10.1 ThumbEE instructions
  - A2.10.2 ThumbEE configuration
    - Use of HandlerBase
- A2.11 Jazelle direct bytecode execution support
- A2.12 Exceptions, debug events and checks
A3: Application Level Memory Model
- A3.1 Address space
  - A3.1.1 Address space overflow or underflow
- A3.2 Alignment support
- A3.3 Endian support
- A3.4 Synchronization and semaphores
- A3.5 Memory types and attributes and the memory order model
- A3.6 Access rights
- A3.7 Virtual and physical addressing
- A3.8 Memory access order
- A3.9 Caches and memory hierarchy
A4: The Instruction Sets
- A4.1 About the instruction sets
- A4.2 Unified Assembler Language
  - A4.2.1 Conditional instructions
  - A4.2.2 Use of labels in UAL instruction syntax
- A4.3 Branch instructions
- A4.4 Data-processing instructions
- A4.5 Status register access instructions
  - A4.5.1 Banked register access instructions
- A4.6 Load/store instructions
- A4.7 Load/store multiple instructions
  - A4.7.1 Loads to the PC
- A4.8 Miscellaneous instructions
  - A4.8.1 The Yield instruction
- A4.9 Exception-generating and exception-handling instructions
- A4.10 Coprocessor instructions
- A4.11 Advanced SIMD and Floating-point load/store instructions
  - A4.11.1 Element and structure load/store instructions
- A4.12 Advanced SIMD and Floating-point register transfer instructions
- A4.13 Advanced SIMD data-processing instructions
- A4.14 Floating-point data-processing instructions
A5: ARM Instruction Set Encoding
- A5.1 ARM instruction set encoding
- A5.2 Data-processing and miscellaneous instructions
- A5.3 Load/store word and unsigned byte
- A5.4 Media instructions
- A5.5 Branch, branch with link, and block data transfer
- A5.6 Coprocessor instructions, and Supervisor Call
- A5.7 Unconditional instructions
  - A5.7.1 Memory hints, Advanced SIMD instructions, and miscellaneous instructions
A6: Thumb Instruction Set Encoding
- A6.1 Thumb instruction set encoding
- A6.2 16-bit Thumb instruction encoding
- A6.3 32-bit Thumb instruction encoding
A7: Advanced SIMD and Floating-point Instruction Encoding
- A7.1 Overview
  - A7.1.1 Advanced SIMD
  - A7.1.2 Floating-point
- A7.2 Advanced SIMD and Floating-point instruction syntax
- A7.3 Register encoding
  - A7.3.1 Advanced SIMD scalars
- A7.4 Advanced SIMD data-processing instructions
- A7.5 Floating-point data-processing instructions
  - A7.5.1 Operation of modified immediate constants, Floating-point
- A7.6 Extension register load/store instructions
- A7.7 Advanced SIMD element or structure load/store instructions
  - A7.7.1 Advanced SIMD addressing mode
- A7.8 8, 16, and 32-bit transfer between ARM core and extension registers
- A7.9 64-bit transfers between ARM core and extension registers
A8: Instruction Descriptions
- A8.1 Format of instruction descriptions
- A8.2 Standard assembler syntax fields
- A8.3 Conditional execution
  - A8.3.1 Pseudocode details of conditional execution
- A8.4 Shifts applied to a register
- A8.5 Memory accesses
- A8.6 Encoding of lists of ARM core registers
- A8.7 Additional pseudocode support for instruction descriptions
  - A8.7.1 Pseudocode details of coprocessor operations
  - A8.7.2 Calling the supervisor
- A8.8 Alphabetical list of instructions
A9: The ThumbEE Instruction Set
- A9.1 About the ThumbEE instruction set
- A9.2 ThumbEE instruction set encoding
  - A9.2.1 16-bit ThumbEE instructions
- A9.3 Additional instructions in Thumb and ThumbEE instruction sets
  - A9.3.1 ENTERX, LEAVEX
- A9.4 ThumbEE instructions with modified behavior
- A9.5 Additional ThumbEE instructions
Part B: System Level Architecture
B1: System Level Programmers’ Model
- B1.1 About the System level programmers’ model
- B1.2 System level concepts and terminology
  - B1.2.1 Mode, state, and privilege level
  - B1.2.2 Exceptions
    - Terminology for describing exceptions
    - Exceptions, privilege, and security state
- B1.3 ARM processor modes and ARM core registers
- B1.4 Instruction set states
  - B1.4.1 Exceptions and instruction set state
  - B1.4.2 Unimplemented instruction sets
- B1.5 The Security Extensions
- B1.6 The Large Physical Address Extension
- B1.7 The Virtualization Extensions
  - B1.7.1 Impact of the Virtualization Extensions on the modes and exception model
    - The virtual exceptions
- B1.8 Exception handling
- B1.9 Exception descriptions
- B1.10 Coprocessors and system control
  - B1.10.1 CP14 and CP15 system control registers
    - Access to CP14 and CP15 registers
  - B1.10.2 Access controls on CP0 to CP13
- B1.11 Advanced SIMD and floating-point support
- B1.12 Thumb Execution Environment
  - B1.12.1 ThumbEE and the Security Extensions and Virtualization Extensions
  - B1.12.2 Aborts, exceptions, and checks
- B1.13 Jazelle direct bytecode execution
- B1.14 Traps to the hypervisor
B2: Common Memory System Architecture Features
- B2.1 About the memory system architecture
- B2.2 Caches and branch predictors
- B2.3 IMPLEMENTATION DEFINED memory system features
  - B2.3.1 ARMv7 CP15 register support for IMPLEMENTATION DEFINED features
- B2.4 Pseudocode details of general memory system operations
B3: Virtual Memory System Architecture (VMSA)
- B3.1 About the VMSA
- B3.2 The effects of disabling MMUs on VMSA behavior
- B3.3 Translation tables
- B3.4 Secure and Non-secure address spaces
- B3.5 Short-descriptor translation table format
- B3.6 Long-descriptor translation table format
- B3.7 Memory access control
- B3.8 Memory region attributes
- B3.9 Translation Lookaside Buffers (TLBs)
- B3.10 TLB maintenance requirements
- B3.11 Caches in a VMSA implementation
- B3.12 VMSA memory aborts
- B3.13 Exception reporting in a VMSA implementation
- B3.14 Virtual Address to Physical Address translation operations
- B3.15 About the system control registers for VMSA
- B3.16 Organization of the CP14 registers in a VMSA implementation
- B3.17 Organization of the CP15 registers in a VMSA implementation
- B3.18 Functional grouping of VMSAv7 system control registers
- B3.19 Pseudocode details of VMSA memory system operations
B4: System Control Registers in a VMSA implementation
- B4.1 VMSA System control registers descriptions, in register order
- B4.2 VMSA system control operations described by function
B5: Protected Memory System Architecture (PMSA)
- B5.1 About the PMSA
- B5.2 Memory access control
  - B5.2.1 Access permissions
    - The XN (Execute-never) attribute and instruction fetching
- B5.3 Memory region attributes
- B5.4 PMSA memory aborts
- B5.5 Exception reporting in a PMSA implementation
- B5.6 About the system control registers for PMSA
- B5.7 Organization of the CP14 registers in a PMSA implementation
- B5.8 Organization of the CP15 registers in a PMSA implementation
- B5.9 Functional grouping of PMSAv7 system control registers
- B5.10 Pseudocode details of PMSA memory system operations
B6: System Control Registers in a PMSA implementation
- B6.1 PMSA System control registers descriptions, in register order
- B6.2 PMSA system control operations described by function
B7: The CPUID Identification Scheme
- B7.1 Introduction to the CPUID scheme
- B7.2 The CPUID registers
  - B7.2.1 Organization of the CPUID registers
    - General properties of the CPUID registers
  - B7.2.2 About the Instruction Set Attribute registers
    - Instruction set descriptions in the CPUID scheme
    - Summary of Instruction Set Attribute register attribute fields
- B7.3 Advanced SIMD and Floating-point Extension feature identification registers
  - B7.3.1 About the Media and VFP Feature registers
B8: The Generic Timer
- B8.1 About the Generic Timer
- B8.2 Generic Timer registers summary
  - B8.2.1 Status of the CNTVOFF register
B9: System Instructions
- B9.1 General restrictions on system instructions
  - B9.1.1 Restrictions on exception return instructions
  - B9.1.2 Restrictions on updates to the CPSR.M field
- B9.2 Encoding and use of Banked register transfer instructions
- B9.3 Alphabetical list of instructions
Part C: Debug Architecture
C1: Introduction to the ARM Debug Architecture
- C1.1 Scope of part C of this manual
  - C1.1.1 Support for Secure User halting debug
- C1.2 About the ARM Debug architecture
- C1.3 Security Extensions and debug
- C1.4 Register interfaces
C2: Invasive Debug Authentication
- C2.1 About invasive debug authentication
- C2.2 Invasive debug with no Security Extensions
- C2.3 Invasive debug with the Security Extensions
- C2.4 Invasive debug authentication security considerations
C3: Debug Events
- C3.1 About debug events
- C3.2 BKPT instruction debug events
- C3.3 Breakpoint debug events
- C3.4 Watchpoint debug events
- C3.5 Vector catch debug events
- C3.6 Halting debug events
- C3.7 Generation of debug events
- C3.8 Debug event prioritization
- C3.9 Pseudocode details of Software debug events
C4: Debug Exceptions
- C4.1 About debug exceptions
  - C4.1.1 Debug exception on BKPT instruction, Breakpoint, or Vector catch debug events
  - C4.1.2 Debug exception on Watchpoint debug event
- C4.2 Avoiding debug exceptions that might cause UNPREDICTABLE behavior
  - C4.2.1 Debug exceptions in exception handlers
  - C4.2.2 Debug exceptions in debug monitors
C5: Debug State
- C5.1 About Debug state
- C5.2 Entering Debug state
- C5.3 Executing instructions in Debug state
- C5.4 Behavior of non-invasive debug in Debug state
- C5.5 Exceptions in Debug state
  - C5.5.1 Handling of synchronous Data Aborts in Non-secure state, Virtualization Extensions
  - C5.5.2 Effect of asynchronous aborts when the processor is in Debug state
- C5.6 Memory system behavior in Debug state
- C5.7 Exiting Debug state
  - C5.7.1 CPSR and PC values on exit from Debug state
  - C5.7.2 Effect of asynchronous aborts on exiting Debug state
C6: Debug Register Interfaces
- C6.1 About the debug register interfaces
  - C6.1.1 Processor interfaces to the debug registers
  - C6.1.2 External debug interface to the debug registers
- C6.2 Synchronization of debug register updates
  - C6.2.1 Synchronization of accesses to the Debug Communications Channel
  - C6.2.2 Synchronization requirements for memory-mapped register interfaces
- C6.3 Access permissions
- C6.4 The CP14 debug register interface
- C6.5 The memory-mapped and recommended external debug interfaces
- C6.6 Summary of the v7 Debug register interfaces
- C6.7 Summary of the v7.1 Debug register interfaces
C7: Debug Reset and Powerdown Support
- C7.1 Debug guidelines for systems with energy management capability
- C7.2 Power domains and debug
- C7.3 The OS Save and Restore mechanism
- C7.4 Reset and debug
C8: The Debug Communications Channel and Instruction Transfer Register
- C8.1 About the DCC and DBGITR
- C8.2 Operation of the DCC and Instruction Transfer Register
  - C8.2.1 General operation of the DCC and Instruction Transfer Register
  - C8.2.2 Operation of the External DCC access modes
- C8.3 Behavior of accesses to the DCC registers and DBGITR
- C8.4 Synchronization of accesses to the DCC and the DBGITR
C9: Non-invasive Debug Authentication
- C9.1 About non-invasive debug authentication
- C9.2 Non-invasive debug authentication
- C9.3 Effects of non-invasive debug authentication
  - C9.3.1 Trace
C10: Sample-based Profiling
- C10.1 Sample-based profiling
  - C10.1.1 The implemented Sample-based profiling registers
  - C10.1.2 Reads of the Program Counter Sampling Register
C11: The Debug Registers
- C11.1 About the debug registers
- C11.2 Debug register summary
- C11.3 Debug identification registers
  - C11.3.1 About the Debug identification registers
- C11.4 Control and status registers
  - C11.4.1 About the Debug control and status registers
- C11.5 Instruction and data transfer registers
  - C11.5.1 About the Debug instruction transfer and data transfer registers
- C11.6 Software debug event registers
  - C11.6.1 About the Software debug event registers
- C11.7 Sample-based profiling registers
  - C11.7.1 About the sample-based profiling registers
- C11.8 OS Save and Restore registers
  - C11.8.1 About the OS Save and Restore registers
- C11.9 Memory system control registers
  - C11.9.1 About the Debug memory system control registers
- C11.10 Management registers
- C11.11 Register descriptions, in register order
C12: The Performance Monitors Extension
- C12.1 About the Performance Monitors
- C12.2 Accuracy of the Performance Monitors
- C12.3 Behavior on overflow
  - C12.3.1 Generating overflow interrupt requests
  - C12.3.2 Pseudocode details of overflow interrupt requests
- C12.4 Effect of the Security Extensions and Virtualization Extensions
  - C12.4.1 Interaction with Security Extensions
  - C12.4.2 Interaction with Virtualization Extensions
- C12.5 Event filtering, PMUv2
  - C12.5.1 Accuracy of event filtering
    - Exception-related events
    - Software increment events
  - C12.5.2 Pseudocode details of event filtering
- C12.6 Counter enables
- C12.7 Counter access
  - C12.7.1 PMNx event counters
  - C12.7.2 CCNT cycle counter
- C12.8 Event numbers and mnemonics
- C12.9 Performance Monitors registers
  - C12.9.1 CP15 c9 performance monitors registers
    - Power domains and Performance Monitors registers reset
    - Access permissions
Part D: Appendixes
D1: Recommended External Debug Interface
- D1.1 About the recommended external debug interface
- D1.2 Authentication signals
  - D1.2.1 Changing the authentication signals
- D1.3 Run-control and cross-triggering signals
- D1.4 Recommended debug slave port
  - D1.4.1 PADDRDBG
  - D1.4.2 PSLVERRDBG
- D1.5 Other debug signals
D2: Recommended Memory-mapped and External Debug Interfaces for the Performance Monitors
- D2.1 About the memory-mapped views of the Performance Monitors registers
- D2.2 PMU register descriptions for memory-mapped register views
D3: Recommendations for Performance Monitors Event Numbers for IMPLEMENTATION DEFINED Events
- D3.1 ARM recommendations for IMPLEMENTATION DEFINED event numbers
  - D3.1.1 Effect of selecting an unused or reserved event number
D4: Example OS Save and Restore Sequences for External Debug Over Powerdown
- D4.1 Example OS Save and Restore sequences for v7 Debug
  - D4.1.1 v7 Debug OS Save and Restore sequences using memory-mapped interface, v7 Debug
  - D4.1.2 v7 Debug OS Save and Restore sequences using the CP14 interface, v7 Debug
- D4.2 Example OS Save and Restore sequences for v7.1 Debug
D5: System Level Implementation of the Generic Timer
- D5.1 About the Generic Timer specification
  - D5.1.1 The memory-mapped view of the Generic Timer
- D5.2 Memory-mapped counter module
  - D5.2.1 Control of counter operating frequency and increment
    - The frequency modes table
    - Changing the system counter frequency and increment
- D5.3 Counter module control and status register summary
- D5.4 About the memory-mapped view of the counter and timer
- D5.5 The CNTBaseN and CNTPL0BaseN frames
- D5.6 The CNTCTLBase frame
- D5.7 System level Generic Timer register descriptions, in register order
- D5.8 Providing a complete set of counter and timer features
- D5.9 Gray-count scheme for timer distribution scheme
D6: Common VFP Subarchitecture Specification
- D6.1 Scope of this appendix
- D6.2 Introduction to the Common VFP subarchitecture
- D6.3 Exception processing
- D6.4 Support code requirements
- D6.5 Context switching
- D6.6 Subarchitecture additions to the Floating-point Extension system registers
- D6.7 Earlier versions of the Common VFP subarchitecture
  - D6.7.1 Differences between version 2 and version 3 of the Common VFP subarchitecture
  - D6.7.2 Differences between version 1 and version 2 of the Common VFP subarchitecture
    - Subarchitecture v1 exception handling when FPSCR.IXE is set to 1
D7: Barrier Litmus Tests
- D7.1 Introduction
- D7.2 Simple ordering and barrier cases
- D7.3 Exclusive accesses and barriers
- D7.4 Using a mailbox to send an interrupt
- D7.5 Cache and TLB maintenance operations and barriers
D8: Legacy Instruction Mnemonics
- D8.1 Thumb instruction mnemonics
- D8.2 Other UAL mnemonic changes
- D8.3 Pre-UAL pseudo-instruction NOP
D9: Deprecated and Obsolete Features
- D9.1 Deprecated features
- D9.2 Obsolete features
- D9.3 Use of the SP as a general-purpose register
- D9.4 Explicit use of the PC in ARM instructions
- D9.5 Deprecated Thumb instructions
D10: Fast Context Switch Extension (FCSE)
- D10.1 About the FCSE
- D10.2 Modified virtual addresses
- D10.3 Debug and trace
  - D10.3.1 Addresses used for the generation of debug events
D11: VFP Vector Operation Support
- D11.1 About VFP vector mode
  - D11.1.1 Affected instructions
- D11.2 Vector length and stride control
- D11.3 VFP register banks
- D11.4 VFP instruction type selection
D12: ARMv6 Differences
- D12.1 Introduction to ARMv6
- D12.2 Application level register support
  - D12.2.1 APSR support
  - D12.2.2 Instruction set state
    - Interworking
    - BL and BLX (immediate) instructions, before ARMv6T2
- D12.3 Application level memory support
- D12.4 Instruction set support
- D12.5 System level register support
- D12.6 System level memory model
- D12.7 System Control coprocessor, CP15, support
D13: v6 Debug and v6.1 Debug Differences
- D13.1 About v6 Debug and v6.1 Debug
  - D13.1.1 Major differences between the ARMv6 and ARMv7 Debug architectures
- D13.2 Invasive debug authentication, v6 Debug and v6.1 Debug
- D13.3 Debug events, v6 Debug and v6.1 Debug
  - D13.3.1 Software debug events
  - D13.3.2 Halting debug events
- D13.4 Debug exceptions, v6 Debug and v6.1 Debug
- D13.5 Debug state, v6 Debug and v6.1 Debug
- D13.6 Debug register interfaces, v6 Debug and v6.1 Debug
  - D13.6.1 v6 Debug and v6.1 Debug register visibility
    - ARMv6 debug features not defined by the Debug architecture
  - D13.6.2 v6 Debug and v6.1 Debug register accesses in the CP14 interface
    - Accesses to reserved registers
- D13.7 Reset and powerdown support
- D13.8 The Debug Communications Channel and Instruction Transfer Register
- D13.9 Non-invasive debug authentication, v6 Debug and v6.1 Debug
  - D13.9.1 ARMv6 non-invasive debug authentication
- D13.10 Sample-based profiling, v6 Debug and v6.1 Debug
- D13.11 The debug registers, v6 Debug and v6.1 Debug
- D13.12 Performance monitors, v6 Debug and v6.1 Debug
D14: Secure User Halting Debug
- D14.1 About Secure User halting debug
- D14.2 Invasive debug authentication in an implementation that supports SUHD
  - D14.2.1 Effect of SUHD support on invasive debug authentication
- D14.3 Effects of SUHD on Debug state
D15: ARMv4 and ARMv5 Differences
- D15.1 Introduction to ARMv4 and ARMv5
  - D15.1.1 Debug
  - D15.1.2 ARMv6 and ARMv7
- D15.2 Application level register support
  - D15.2.1 APSR support
  - D15.2.2 Instruction set state
    - Interworking
- D15.3 Application level memory support
- D15.4 Instruction set support
- D15.5 System level register support
- D15.6 System level memory model
- D15.7 System Control coprocessor, CP15 support
D16: Pseudocode Definition
- D16.1 About the ARMv7 pseudocode
  - D16.1.1 General limitations of ARMv7 pseudocode
- D16.2 Pseudocode for instruction descriptions
  - D16.2.1 Instruction encoding diagrams and instruction pseudocode
  - D16.2.2 Limitations of the instruction pseudocode
- D16.3 Data types
- D16.4 Expressions
- D16.5 Operators and built-in functions
- D16.6 Statements and program structure
- D16.7 Miscellaneous helper procedures and functions
D17: Pseudocode Index
- D17.1 Pseudocode operators and keywords
- D17.2 Pseudocode functions and procedures
D18: Registers Index
- D18.1 Alphabetic index of ARMv7 registers, by register name
- D18.2 Full registers index
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