ATmega164A; ATmega164PA; ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284, ATmega1284P ATmega324 Manual

User Manual:

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Features
1. Pin configurations
- 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
- 1.2 Pinout - DRQFN for Atmel ATmega164A/164PA/324A/324PA
- 1.3 Pinout - VFBGA for Atmel ATmega164A/164PA/324A/324PA
2. Overview
- 2.1 Block diagram
- 2.2 Comparison between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P
- 2.3 Pin Descriptions11
3. Resources
4. About code examples
5. Data retention
6. Capacitive touch sensing
7. AVR CPU Core
- 7.1 Overview
- 7.2 ALU – Arithmetic Logic Unit
- 7.3 Status Register
  - 7.3.1 SREG – Status Register
- 7.4 General Purpose Register File
  - 7.4.1 The X-register, Y-register, and Z-register
- 7.5 Stack Pointer
  - 7.5.1 SPH and SPL – Stack Pointer High and Stack pointer Low
  - 7.5.2 RAMPZ – Extended Z-pointer Register for ELPM/SPM(1)
- 7.6 Instruction Execution Timing
- 7.7 Reset and interrupt handling
  - 7.7.1 Interrupt response time
8. AVR memories
- 8.1 Overview
- 8.2 In-System Reprogrammable Flash Program Memory
- 8.3 SRAM data memory
  - 8.3.1 Data memory access times
- 8.4 EEPROM data memory
  - 8.4.1 EEPROM Read/Write Access
  - 8.4.2 Preventing EEPROM corruption
- 8.5 I/O memory
- 8.6 Register Description
9. System clock and clock options
- 9.1 Clock systems and their distribution
- 9.2 Clock Sources
- 9.3 Low Power Crystal Oscillator
- 9.4 Full swing Crystal Oscillator
- 9.5 Low Frequency Crystal Oscillator
- 9.6 Calibrated Internal RC Oscillator
- 9.7 128kHz internal oscillator
- 9.8 External clock
- 9.9 Timer/Counter Oscillator
- 9.10 Clock Output Buffer
- 9.11 System Clock Prescaler
- 9.12 Register description
  - 9.12.1 OSCCAL – Oscillator Calibration Register
  - 9.12.2 CLKPR – Clock Prescale Register
10. Power management and sleep modes
- 10.1 Overview
- 10.2 Sleep Modes
- 10.3 BOD disable(1)
- 10.4 Idle mode
- 10.5 ADC Noise Reduction mode
- 10.6 Power-down mode
- 10.7 Power-save mode
- 10.8 Standby mode
- 10.9 Extended Standby mode
- 10.10 Power Reduction Register
- 10.11 Minimizing Power Consumption
- 10.12 Register description
11. System Control and Reset
- 11.1 Resetting the AVR
- 11.2 Internal Voltage Reference
  - 11.2.1 Voltage Reference Enable Signals and Start-up Time
- 11.3 Watchdog Timer
  - 11.3.1 Features
  - 11.3.2 Overview
- 11.4 Register description
  - 11.4.1 MCUSR – MCU Status Register
  - 11.4.2 WDTCSR – Watchdog Timer Control Register
12. Interrupts
- 12.1 Overview
- 12.2 Interrupt Vectors in ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
  - 12.2.1 Moving Interrupts Between Application and Boot Space
- 12.3 Register description
  - 12.3.1 MCUCR – MCU Control Register
13. External Interrupts
- 13.1 Overview
- 13.2 Register description
14. I/O-Ports
- 14.1 Overview
- 14.2 Ports as General Digital I/O
- 14.3 Alternate Port Functions
- Register description
15. 8-bit Timer/Counter0 with PWM
- 15.1 Features
- 15.2 Overview
  - 15.2.1 Registers
  - 15.2.2 Definitions
- 15.3 Timer/Counter Clock Sources
- 15.4 Counter Unit
- 15.5 Output Compare unit
- 15.6 Compare Match Output unit
  - 15.6.1 Compare Output Mode and Waveform Generation
- 15.7 Modes of operation
- 15.8 Timer/Counter Timing diagrams
- 15.9 Register description
16. 16-bit Timer/Counter1 and Timer/Counter3(1) with PWM
- 16.1 Features
- 16.2 Overview
  - 16.2.1 Registers
  - 16.2.2 Definitions
- 16.3 Accessing 16-bit Registers
  - 16.3.1 Reusing the Temporary High Byte Register
- 16.4 Timer/Counter Clock Sources
- 16.5 Prescaler Reset
- 16.6 Counter Unit
- 16.7 Input Capture Unit
- 16.8 Output Compare units
- 16.9 Compare Match Output unit
  - 16.9.1 Compare Output Mode and Waveform Generation
- 16.10 Modes of Operation
- 16.11 Timer/Counter Timing diagrams
- 16.12 Register description
17. 8-bit Timer/Counter2 with PWM and asynchronous operation
- 17.1 Features
- 17.2 Overview
  - 17.2.1 Registers
  - 17.2.2 Definitions
- 17.3 Timer/Counter clock sources
- 17.4 Counter unit
- 17.5 Output Compare unit
- 17.6 Compare Match Output unit
  - 17.6.1 Compare Output Mode and Waveform Generation
- 17.7 Modes of operation
- 17.8 Timer/Counter Timing diagrams
- 17.9 Asynchronous Operation of Timer/Counter2
- 17.10 Timer/Counter Prescaler
- 17.11 Register description
18. SPI – Serial Peripheral Interface
- 18.1 Features
- 18.2 Overview
- 18.3 SS pin functionality
  - 18.3.1 Slave mode
  - 18.3.2 Master mode
- 18.4 Data modes
- 18.5 Register description
19. USART
- 19.1 Features
- 19.2 USART1 and USART0
- 19.3 Overview
- 19.4 Clock Generation
- 19.5 Frame formats
  - 19.5.1 Parity Bit Calculation
- 19.6 USART Initialization
- 19.7 Data Transmission – The USART Transmitter
- 19.8 Data Reception – The USART Receiver
- 19.9 Asynchronous Data Reception
- 19.10 Multi-processor Communication mode
  - 19.10.1 Using MPCMn
- 19.11 Register description
- 19.12 Examples of Baud Rate Setting
20. USART in SPI mode
- 20.1 Features
- 20.2 Overview
- 20.3 Clock Generation
- 20.4 SPI Data Modes and Timing
- 20.5 Frame Formats
  - 20.5.1 USART MSPIM Initialization
- 20.6 Data Transfer
  - 20.6.1 Transmitter and Receiver Flags and Interrupts
  - 20.6.2 Disabling the Transmitter or Receiver
- 20.7 AVR USART MSPIM vs. AVR SPI
- 20.8 Register description
21. Two-wire Serial Interface
- 21.1 Features
- 21.2 Two-wire Serial Interface bus definition
  - 21.2.1 TWI Terminology
  - 21.2.2 Electrical Interconnection
- 21.3 Data Transfer and Frame Format
- 21.4 Multi-master Bus Systems, Arbitration and Synchronization
- 21.5 Overview of the TWI Module
- 21.6 Using the TWI
- 21.7 Transmission modes
- 21.8 Multi-master Systems and Arbitration
- 21.9 Register description
22. AC - Analog Comparator
- 22.1 Overview
- 22.2 Analog Comparator Multiplexed Input
- 22.3 Register description
23. ADC - Analog-to-digital converter
- 23.1 Features
- 23.2 Overview
- 23.3 Operation
- 23.4 Starting a conversion
- 23.5 Prescaling and Conversion Timing
  - 23.5.1 Differential Gain Channels
- 23.6 Changing Channel or Reference Selection
  - 23.6.1 ADC Input Channels
  - 23.6.2 ADC Voltage Reference
- 23.7 ADC Noise Canceler
- 23.8 ADC Conversion Result
- 23.9 Register description
24. JTAG interface and on-chip debug system
- 24.1 Features
- 24.2 Overview
- 24.3 TAP – Test Access Port
- 24.4 TAP controller
- 24.5 Using the Boundary-scan Chain
- 24.6 Using the On-chip Debug System
- 24.7 On-chip Debug Specific JTAG Instructions
- 24.8 Using the JTAG Programming Capabilities
- 24.9 Bibliography
- 24.10 Register description
  - 24.10.1 OCDR – On-chip Debug Register
25. IEEE 1149.1 (JTAG) Boundary-scan
- 25.1 Features
- 25.2 Overview
- 25.3 Data Registers
- 25.4 Boundary-scan Specific JTAG Instructions
- 25.5 Boundary-scan Chain
  - 25.5.1 Scanning the Digital Port Pins
  - 25.5.2 Scanning the RESET Pin
- 25.6 Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Boundary-scan order
- 25.7 Boundary-scan Description Language Files
- 25.8 Register description
  - 25.8.1 MCUCR – MCU Control Register
  - 25.8.2 MCUSR – MCU Status Register
26. Boot loader support – read-while-write self-programming
- 26.1 Features
- 26.2 Overview
- 26.3 Application and Boot Loader Flash Sections
  - 26.3.1 Application Section
  - 26.3.2 BLS – Boot Loader Section
- 26.4 Read-While-Write and No Read-While-Write Flash Sections
  - 26.4.1 RWW – Read-While-Write Section
  - 26.4.2 NRWW – No Read-While-Write Section
- 26.5 Boot Loader Lock Bits
- 26.6 Entering the Boot Loader Program
- 26.7 Addressing the Flash During Self-Programming
- 26.8 Self-Programming the Flash
- 26.9 Register description
  - 26.9.1 SPMCSR – Store Program Memory Control and Status Register
27. Memory programming
- 27.1 Program And Data Memory Lock Bits
- 27.2 Fuse bits
  - 27.2.1 Latching of Fuses
- 27.3 Signature Bytes
- 27.4 Calibration byte
- 27.5 Page Size
- 27.6 Parallel Programming Parameters, Pin Mapping, and Commands
  - 27.6.1 Signal Names
- 27.7 Parallel programming
- 27.8 Serial downloading
  - 27.8.1 Serial Programming Pin Mapping
  - 27.8.2 Serial Programming Algorithm
- 27.9 Serial Programming Instruction set
  - 27.9.1 Serial Programming Characteristics
- 27.10 Programming via the JTAG Interface
28. Electrical characteristics (TA = -40°C to 85°C)
- 28.1 DC Characteristics
- 28.2 Speed grades
- 28.3 Clock characteristics
  - 28.3.1 External clock drive waveforms
  - 28.3.2 External clock drive
- 28.4 System and reset characteristics
- 28.5 External interrupts characteristics
- 28.6 SPI timing characteristics
- 28.7 Two-wire Serial Interface Characteristics
- 28.8 ADC characteristics
29. Electrical Characteristics - TA = -40°C to 105°C
- 29.1 DC Characteristics
30. Typical characteristics -TA = -40°C to 85°C
- 30.1 Atmel ATmega164A typical characteristics - TA = -40°C to 85°C
- 30.2 Atmel ATmega164PA typical characteristics - TA = -40°C to 85°C
- 30.3 Atmel ATmega324A typical characteristics - TA = -40°C to 85°C
- 30.4 Atmel ATmega324PA typical characteristics - TA = -40°C to 85°C
- 30.5 Atmel ATmega644A typical characteristics - TA = -40°C to 85°C
- 30.6 ATmega644PA typical characteristics - TA = -40°C to 85°C
- 30.7 ATmega1284 typical characteristics - TA = -40°C to 85°C
- 30.8 ATmega1284P typical characteristics - TA = -40°C to 85°C
31. Typical Characteristics - TA = -40°C to 105°C
- 31.1 ATmega164PA Typical Characteristics - TA = -40°C to 105°C
- 31.2 ATmega324PA Typical Characteristics - TA = -40°C to 105°C
- 31.3 ATmega644PA Typical Characteristics - TA = -40°C to 105°C
- 31.4 ATmega1284P typical characteristics - TA = -40°C to 105°C
32. Register summary
33. Instruction set summary
34. Ordering information
- 34.1 Atmel ATmega164A
- 34.2 Atmel ATmega164PA
- 34.3 Atmel ATmega324A
- 34.4 Atmel ATmega324PA
- 34.5 Atmel ATmega644A
- 34.6 Atmel ATmega644PA
- 34.7 Atmel ATmega1284
- 34.8 Atmel ATmega1284P
35. Packaging information
- 35.1 44A
- 35.2 40P6
- 35.3 44M1
- 35.4 44MC
- 35.5 49C2
36. Errata
- 36.1 Errata for ATmega164A
  - 36.1.1 Rev. E
- 36.2 Errata for ATmega164PA
  - 36.2.1 Rev. E
- 36.3 Errata for ATmega324A
  - 36.3.1 Rev. F
- 36.4 Errata for ATmega324PA
  - 36.4.1 Rev. F
- 36.5 Errata for ATmega644A
  - 36.5.1 Rev. F
- 36.6 Errata for ATmega644PA
  - 36.6.1 Rev. F
- 36.7 Errata for ATmega1284
  - 36.7.1 Rev. B
- 36.8 Errata for ATmega1284P
  - 36.8.1 Rev. B
37. Datasheet revision history
- 37.1 Rev. 8272G - 01/2015
- 37.2 Rev. 8272F - 08/2014
- 37.3 Rev. 8272E - 04/2013
- 37.4 Rev. 8272D - 05/12
- 37.5 Rev. 8272C - 06/11
- 37.6 Rev. 8272B - 05/11
- 37.7 Rev. 8272A - 01/10

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