Allwinner A64 User Manual V1.1
Allwinner_A64_User_Manual_V1.1
User Manual:
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- Declaration
- Revision History
- Table of Contents
- Chapter 1 About This Documentation
- Chapter 2 Overview
- Chapter 3 System
- 3.1. Memory Mapping
- 3.2. Boot System
- 3.3. CCU
- 3.3.1. Overview
- 3.3.2. Functionalities Description
- 3.3.3. Typical Applications
- 3.3.4. Register List
- 3.3.5. Register Description
- 3.3.5.1. PLL_CPUX Control Register (Default Value: 0x00001000)
- 3.3.5.2. PLL_Audio Control Register (Default Value: 0x00035514)
- 3.3.5.3. PLL_VIDEO0 Control Register (Default Value: 0x03006207)
- 3.3.5.4. PLL_VE Control Register (Default Value: 0x03006207)
- 3.3.5.5. PLL_DDR0 Control Register (Default Value: 0x00001000)
- 3.3.5.6. PLL_PERIPH0 Control Register (Default Value: 0x00041811)
- 3.3.5.7. PLL_PERIPH1 Control Register (Default Value: 0x00041811)
- 3.3.5.8. PLL_VIDEO1 Control Register (Default Value: 0x03006207)
- 3.3.5.9. PLL_GPU Control Register (Default Value: 0x03006207)
- 3.3.5.10. PLL_MIPI Control Register (Default Value: 0x00000515)
- 3.3.5.11. PLL_HSIC Control Register (Default Value: 0x03001300)
- 3.3.5.12. PLL_DE Control Register (Default Value: 0x03006207)
- 3.3.5.13. PLL_DDR1 Control Register (Default Value: 0x00001800)
- 3.3.5.14. CPUX/AXI Configuration Register (Default Value: 0x00010300)
- 3.3.5.15. AHB1/APB1 Configuration Register (Default Value: 0x00001010)
- 3.3.5.16. APB2 Configuration Register (Default Value: 0x01000000)
- 3.3.5.17. AHB2 Configuration Register (Default Value: 0x00000000)
- 3.3.5.18. Bus Clock Gating Register0 (Default Value: 0x00000000)
- 3.3.5.19. Bus Clock Gating Register1 (Default Value: 0x00000000)
- 3.3.5.20. Bus Clock Gating Register2 (Default Value: 0x00000000)
- 3.3.5.21. Bus Clock Gating Register3 (Default Value: 0x00000000)
- 3.3.5.22. Bus Clock Gating Register4 (Default Value: 0x00000000)
- 3.3.5.23. THS Clock Register (Default Value: 0x00000000)
- 3.3.5.24. NAND Clock Register (Default Value: 0x00000000)
- 3.3.5.25. SMHC0 Clock Register (Default Value: 0x00000000)
- 3.3.5.26. SMHC1 Clock Register (Default Value: 0x00000000)
- 3.3.5.27. SMHC2 Clock Register (Default Value: 0x00000000)
- 3.3.5.28. TS Clock Register (Default Value: 0x00000000)
- 3.3.5.29. CE Clock Register (Default Value: 0x00000000)
- 3.3.5.30. SPI0 Clock Register (Default Value: 0x00000000)
- 3.3.5.31. SPI1 Clock Register (Default Value: 0x00000000)
- 3.3.5.32. I2S/PCM 0 Clock Register (Default Value: 0x00000000)
- 3.3.5.33. I2S/PCM 1 Clock Register (Default Value: 0x00000000)
- 3.3.5.34. I2S/PCM 2 Clock Register (Default Value: 0x00000000)
- 3.3.5.35. OWA Clock Register (Default Value: 0x00000000)
- 3.3.5.36. USBPHY Configuration Register (Default Value: 0x00000000)
- 3.3.5.37. DRAM Configuration Register (Default Value: 0x00000000)
- 3.3.5.38. PLL_DDR Configuration Register (Default Value: 0xCCCA0000)
- 3.3.5.39. MBUS Reset Register (Default Value: 0x80000000)
- 3.3.5.40. DRAM Clock Gating Register (Default Value: 0x00000000)
- 3.3.5.41. DE Clock Gating Register (Default Value: 0x00000000)
- 3.3.5.42. TCON0 Clock Register (Default Value: 0x00000000)
- 3.3.5.43. TCON1 Clock Register (Default Value: 0x00000000)
- 3.3.5.44. DEINTERLACE Clock Register (Default Value: 0x00000000)
- 3.3.5.45. CSI_MISC Clock Register (Default Value: 0x00000000)
- 3.3.5.46. CSI Clock Register (Default Value: 0x00000000)
- 3.3.5.47. VE Clock Register (Default Value: 0x00000000)
- 3.3.5.48. AC Digital Clock Register (Default Value: 0x00000000)
- 3.3.5.49. AVS Clock Register (Default Value: 0x00000000)
- 3.3.5.50. HDMI Clock Register (Default Value: 0x00000000)
- 3.3.5.51. HDMI Slow Clock Register (Default Value: 0x00000000)
- 3.3.5.52. MBUS Clock Register (Default Value: 0x00000000)
- 3.3.5.53. MIPI_DSI Clock Register (Default Value: 0x00000000)
- 3.3.5.54. GPU Clock Register (Default Value: 0x00000000)
- 3.3.5.55. PLL Stable Time Register0 (Default Value: 0x000000FF)
- 3.3.5.56. PLL Stable Time Register1 (Default Value: 0x000000FF)
- 3.3.5.57. PLL_PERIPH1 Bias Register (Default Value: 0x10100010)
- 3.3.5.58. PLL_CPUX Bias Register (Default Value: 0x08100200)
- 3.3.5.59. PLL_AUDIO Bias Register (Default Value: 0x10100000)
- 3.3.5.60. PLL_VIDEO0 Bias Register (Default Value: 0x10100000)
- 3.3.5.61. PLL_VE Bias Register (Default Value: 0x10100000)
- 3.3.5.62. PLL_DDR0 Bias Register (Default Value: 0x81104000)
- 3.3.5.63. PLL_PERIPH0 Bias Register (Default Value: 0x10100010)
- 3.3.5.64. PLL_VIDEO1 Bias Register (Default Value: 0x10100000)
- 3.3.5.65. PLL_GPU Bias Register (Default Value: 0x10100000)
- 3.3.5.66. PLL_MIPI Bias Register (Default Value: 0XF8100400)
- 3.3.5.67. PLL_HSIC Bias Register (Default Value: 0x10100000)
- 3.3.5.68. PLL_DE Bias Register (Default Value: 0x10100000)
- 3.3.5.69. PLL_DDR1 Bias Register (Default Value: 0x10010000)
- 3.3.5.70. PLL_CPUX Tuning Register (Default Value: 0x0A101000)
- 3.3.5.71. PLL_DDR0 Tuning Register (Default Value: 0x14880000)
- 3.3.5.72. PLL_MIPI Tuning Register (Default Value: 0x8A002000)
- 3.3.5.73. PLL_PERIPH1 Pattern Control Register (Default Value: 0x00000000)
- 3.3.5.74. PLL_CPUX Pattern Control Register (Default Value: 0x00000000)
- 3.3.5.75. PLL_AUDIO Pattern Control Register(Default Value: 0x00000000)
- 3.3.5.76. PLL_VIDEO0 Pattern Control Register (Default Value: 0x00000000)
- 3.3.5.77. PLL_VE Pattern Control Register (Default Value: 0x00000000)
- 3.3.5.78. PLL_DDR0 Pattern Control Register (Default Value: 0x00000000)
- 3.3.5.79. PLL_VIDEO1 Pattern Control Register (Default Value: 0x00000000)
- 3.3.5.80. PLL_GPU Pattern Control Register (Default Value: 0x00000000)
- 3.3.5.81. PLL_MIPI Pattern Control Register (Default Value: 0x00000000)
- 3.3.5.82. PLL_HSIC Pattern Control Register (Default Value: 0x00000000)
- 3.3.5.83. PLL_DE Pattern Control Register (Default Value: 0x00000000)
- 3.3.5.84. PLL_DDR1 Pattern Control Register0 (Default Value: 0x00000000)
- 3.3.5.85. PLL_DDR1 Pattern Control Register1 (Default Value: 0x00000000)
- 3.3.5.86. Bus Software Reset Register 0 (Default Value: 0x00000000)
- 3.3.5.87. Bus Software Reset Register 1 (Default Value: 0x00000000)
- 3.3.5.88. Bus Software Reset Register 2 (Default Value: 0x00000000)
- 3.3.5.89. Bus Software Reset Register 3 (Default Value: 0x00000000)
- 3.3.5.90. Bus Software Reset Register 4 (Default Value: 0x00000000)
- 3.3.5.91. CCU Security Switch Register (Default Value: 0x00000000)
- 3.3.5.92. PS Control Register (Default Value: 0x00000000)
- 3.3.5.93. PS Counter Register (Default Value: 0x00000000)
- 3.3.5.94. PLL Lock Control Register (Default Value: 0x00000000)
- 3.3.6. Programming Guidelines
- 3.4. CPU Configuration
- 3.4.1. Overview
- 3.4.2. Block Diagram
- 3.4.3. Functionalities Description
- 3.4.4. Register List
- 3.4.5. Register Description
- 3.4.5.1. Cluster Control Register0 (Default Value: 0x80000000)
- 3.4.5.2. Cluster Control Register1 (Default Value: 0x00000000)
- 3.4.5.3. Cache Parameter Control Register0 (Default Value: 0x22222222)
- 3.4.5.4. Cache Parameter Control Register1 (Default Value: 0x02022020)
- 3.4.5.5. General Control Register0 (Default Value: 0x00000010)
- 3.4.5.6. Cluster CPU Status Register (Default Value: 0x000E0000)
- 3.4.5.7. L2 Status Register(Default Value: 0x00000000)
- 3.4.5.8. Cluster Reset Control Register (Default Value: 0x11101101)
- 3.4.5.9. Reset Vector Base Address Register0_L (Default Value: 0x00000000)
- 3.4.5.10. Reset Vector Base Address Register0_H (Default Value: 0x00000000)
- 3.4.5.11. Reset Vector Base Address Register1_L (Default Value: 0x00000000)
- 3.4.5.12. Reset Vector Base Address Register1_H (Default Value: 0x00000000)
- 3.4.5.13. Reset Vector Base Address Register2_L (Default Value: 0x00000000)
- 3.4.5.14. Reset Vector Base Address Register2_H (Default Value: 0x00000000)
- 3.4.5.15. Reset Vector Base Address Register3_L (Default Value: 0x00000000)
- 3.4.5.16. Reset Vector Base Address Register3_H (Default Value: 0x00000000)
- 3.5. System Control
- 3.6. Timer
- 3.6.1. Overview
- 3.6.2. Block Diagram
- 3.6.3. Operation Principle
- 3.6.4. Timer Register List
- 3.6.5. Timer Register Description
- 3.6.5.1. Timer IRQ Enable Register (Default Value: 0x00000000)
- 3.6.5.2. Timer IRQ Status Register (Default Value: 0x00000000)
- 3.6.5.3. Timer 0 Control Register (Default Value: 0x00000004)
- 3.6.5.4. Timer 0 Interval Value Register
- 3.6.5.5. Timer 0 Current Value Register
- 3.6.5.6. Timer 1 Control Register (Default Value: 0x00000004)
- 3.6.5.7. Timer 1 Interval Value Register
- 3.6.5.8. Timer 1 Current Value Register
- 3.6.5.9. AVS Counter Control Register (Default Value: 0x00000000)
- 3.6.5.10. AVS Counter 0 Register (Default Value: 0x00000000)
- 3.6.5.11. AVS Counter 1 Register (Default Value: 0x00000000)
- 3.6.5.12. AVS Counter Divisor Register (Default Value: 0x05DB05DB)
- 3.6.5.13. Watchdog IRQ Enable Register (Default Value: 0x00000000)
- 3.6.5.14. Watchdog Status Register (Default Value: 0x00000000)
- 3.6.5.15. Watchdog Control Register (Default Value: 0x00000000)
- 3.6.5.16. Watchdog Configuration Register (Default Value: 0x00000001)
- 3.6.5.17. Watchdog Mode Register (Default Value: 0x00000000)
- 3.6.6. Programming Guidelines
- 3.7. R_Trusted Watchdog Timer
- 3.7.1. Overview
- 3.7.2. Block Diagram
- 3.7.3. Functionalities Description
- 3.7.4. TWD Register List
- 3.7.5. R_TWD Register Description
- 3.7.5.1. R_TWD Status Register (Default Value: 0x00000000)
- 3.7.5.2. R_TWD Control Register (Default Value: 0x00000000)
- 3.7.5.3. R_TWD Restart Register (Default Value: 0x00000000)
- 3.7.5.4. R_TWD Low Counter Register (Default Value: 0x00000000)
- 3.7.5.5. R_TWD High Counter Register (Default Value: 0x00000000)
- 3.7.5.6. R_TWD Interval Value Register (Default Value: 0x00000000)
- 3.7.5.7. R_TWD Low Counter Compare Register (Default Value: 0x00000000)
- 3.7.5.8. R_TWD High Counter Compare Register (Default Value: 0x00000000)
- 3.7.5.9. Secure Storage NV-Counter Register (Default Value: 0x00000000)
- 3.7.5.10. Synchronize Data Counter Register 0 (Default Value: 0x00000000)
- 3.7.5.11. Synchronize Data Counter Register 1 (Default Value: 0x00000000)
- 3.7.5.12. Synchronize Data Counter Register 2 (Default Value: 0x00000000)
- 3.7.5.13. Synchronize Data Counter Register 3 (Default Value: 0x00000000)
- 3.8. RTC
- 3.8.1. Overview
- 3.8.2. RTC Register List
- 3.8.3. RTC Register Description
- 3.8.3.1. LOSC Control Register (Default Value: 0x00004000)
- 3.8.3.2. LOSC Auto Switch Status Register (Default Value: 0x00000000)
- 3.8.3.3. Internal OSC Clock Prescalar Register (Default Value: 0x0000000F)
- 3.8.3.4. RTC YY-MM-DD Register (Default Value: 0x00000000)
- 3.8.3.5. RTC HH-MM-SS Register (Default Value: 0x00000000)
- 3.8.3.6. Alarm 0 Counter Register (Default Value: 0x00000000)
- 3.8.3.7. Alarm 0 Current Value Register
- 3.8.3.8. Alarm 0 Enable Register (Default Value: 0x00000000)
- 3.8.3.9. Alarm 0 IRQ Enable Register (Default Value: 0x00000000)
- 3.8.3.10. Alarm 0 IRQ Status Register (Default Value: 0x00000000)
- 3.8.3.11. Alarm 1 Week HH-MM-SS Register (Default Value: 0x00000000)
- 3.8.3.12. Alarm 1 Enable Register (Default Value: 0x00000000)
- 3.8.3.13. Alarm 1 IRQ Enable Register (Default Value: 0x00000000)
- 3.8.3.14. Alarm 1 IRQ Status Register (Default Value: 0x00000000)
- 3.8.3.15. Alarm Config Register (Default Value: 0x00000000)
- 3.8.3.16. LOSC Output Gating Register (Default Value: 0x00000000)
- 3.8.3.17. General Purpose Register (Default Value: 0x00000000)
- 3.8.3.18. GPL Hold Output Register (Default Value: 0x00000000)
- 3.8.3.19. VDD RTC Regulation Register (Default Value: 0x00000004)
- 3.8.3.20. IC Characteristic Register (Default Value: 0x00000000)
- 3.8.3.21. Crypt Configuration Register (Default Value: 0x00000000)
- 3.8.3.22. Crypt Key Register (Default Value: 0x00000000)
- 3.8.3.23. Crypt Enable Register (Default Value: 0x00000000)
- 3.9. High-speed Timer
- 3.9.1. Overview
- 3.9.2. Operation Principle
- 3.9.3. HSTimer Block Diagram
- 3.9.4. HSTimer Register List
- 3.9.5. HSTimer Register Description
- 3.9.5.1. HS Timer IRQ Enable Register (Default Value: 0x00000000)
- 3.9.5.2. HS Timer IRQ Status Register (Default Value: 0x00000000)
- 3.9.5.3. HS Timer Control Register (Default Value: 0x00000000)
- 3.9.5.4. HS Timer Interval Value Lo Register
- 3.9.5.5. HS Timer Interval Value Hi Register
- 3.9.5.6. HS Timer Current Value Lo Register
- 3.9.5.7. HS Timer Current Value Hi Register
- 3.9.6. Programming Guidelines
- 3.10. PWM
- 3.11. DMA
- 3.11.1. Overview
- 3.11.2. Functionalities Description
- 3.11.3. DMA Register List
- 3.11.4. DMA Register Description
- 3.11.4.1. DMA IRQ Enable Register (Default Value: 0x00000000)
- 3.11.4.2. DMA IRQ Pending Status Register0 (Default Value: 0x00000000)
- 3.11.4.3. DMA Security Register (Default Value: 0x00000000)
- 3.11.4.4. DMA Auto Gating Register (Default Value: 0x00000000)
- 3.11.4.5. DMA Status Register (Default Value: 0x00000000)
- 3.11.4.6. DMA Channel Enable Register (Default Value: 0x00000000)
- 3.11.4.7. DMA Channel Pause Register (Default Value: 0x00000000)
- 3.11.4.8. DMA Channel Descriptor Address Register (Default Value: 0x00000000)
- 3.11.4.9. DMA Channel Configuration Register (Default Value: 0x00000000)
- 3.11.4.10. DMA Channel Current Source Address Register (Default Value: 0x00000000)
- 3.11.4.11. DMA Channel Current Destination Address Register (Default Value: 0x00000000)
- 3.11.4.12. DMA Channel Byte Counter Left Register (Default Value: 0x00000000)
- 3.11.4.13. DMA Channel Parameter Register (Default Value: 0x00000000)
- 3.11.4.14. DMA Mode Register (Default Value: 0x00000000)
- 3.11.4.15. DMA Former Descriptor Address Register (Default Value: 0x00000000)
- 3.11.4.16. DMA Package Number Register (Default Value: 0x00000000)
- 3.12. GIC
- 3.13. Message Box
- 3.13.1. Overview
- 3.13.2. Functionalities Description
- 3.13.3. Operation Principle
- 3.13.4. Message Box Register List
- 3.13.5. Message Box Register Description
- 3.13.5.1. MSGBox Control Register 0(Default Value: 0x10101010)
- 3.13.5.2. MSGBox Control Register 1(Default Value: 0x10101010)
- 3.13.5.3. MSGBox IRQ Enable Register u(Default Value: 0x00000000)
- 3.13.5.4. MSGBox IRQ Status Register u(Default Value: 0x0000AAAA)
- 3.13.5.5. MSGBox FIFO Status Register m(Default Value: 0x00000000)
- 3.13.5.6. MSGBox Message Status Register m(Default Value: 0x00000000)
- 3.13.5.7. MSGBox Message Queue Register (Default Value: 0x00000000)
- 3.14. Spinlock
- 3.15. Crypto Engine
- 3.15.1. Overview
- 3.15.2. Functionalities Description
- 3.15.3. Crypto Engine Register List
- 3.15.4. Crypto Engine Register Description
- 3.15.4.1. Crypto Engine Task Descriptor Queue Register(Default Value: 0x00000000)
- 3.15.4.2. Crypto Engine Control Register(Default Value: 0x00000000)
- 3.15.4.3. Crypto Engine Interrupt Control Register(Default Value: 0x00000000)
- 3.15.4.4. Crypto Engine Interrupt Status Register(Default Value: 0x00000000)
- 3.15.4.5. Crypto Engine Task Load Register(Default Value: 0x00000000)
- 3.15.4.6. Crypto Engine Task Status Register(Default Value: 0x00000000)
- 3.15.4.7. Crypto Engine Error Status Register(Default Value: 0x00000000)
- 3.15.4.8. Crypto Engine Current Source Address Register(Default Value: 0x00000000)
- 3.15.4.9. Crypto Engine Current Destination Address Register(Default Value: 0x00000000)
- 3.15.4.10. Crypto Engine Throughput Register(Default Value: 0x00000000)
- 3.15.5. Crypto Engine Clock Requirement
- 3.15.6. Programming Guidelines
- 3.16. Secure Memory Controller
- 3.16.1. Overview
- 3.16.2. Functionalities Description
- 3.16.3. SMC Register List
- 3.16.4. SMC Register Description
- 3.16.4.1. SMC Configuration Register(Default Value: 0x00001F0F)
- 3.16.4.2. SMC Action Register(Default Value: 0x00000001)
- 3.16.4.3. SMC Lockdown Range Register(Default Value: 0x00000000)
- 3.16.4.4. SMC Lockdown Select Register(Default Value: 0x00000000)
- 3.16.4.5. SMC Interrupt Status Register(Default Value: 0x00000000)
- 3.16.4.6. SMC Interrupt Clear Register(Default Value: 0x00000000)
- 3.16.4.7. SMC Master Bypass Register(Default Value: 0xFFFFFFFF)
- 3.16.4.8. SMC Master Secure Register(Default Value: 0x00000000)
- 3.16.4.9. SMC Fail Address Register(Default Value: 0x00000000)
- 3.16.4.10. SMC Fail Control Register(Default Value: 0x00000000)
- 3.16.4.11. SMC Fail ID Register(Default Value: 0x00001F00)
- 3.16.4.12. SMC Speculation Control Register(Default Value: 0x00000000)
- 3.16.4.13. SMC Security Inversion Enable Register(Default Value: 0x00000000)
- 3.16.4.14. SMC Master Attribute Register(Default Value: 0x00000000)
- 3.16.4.15. DRM Master Enable Register(Default Value: 0x00000000)
- 3.16.4.16. DRM Illegal Access Register(Default Value: 0x00000000)
- 3.16.4.17. DRM Start Address Register(Default Value: 0x00000000)
- 3.16.4.18. DRM End Address Register(Default Value: 0x00000000)
- 3.16.4.19. SMC Region Setup Low Register(Default Value: 0x00000000)
- 3.16.4.20. SMC Region Setup High Register(Default Value: 0x00000000)
- 3.16.4.21. SMC Region Attributes Register(Default Value: 0x00000000)
- 3.17. Secure Peripherals Controller
- 3.17.1. Overview
- 3.17.2. Functionalities Description
- 3.17.3. SPC Register List
- 3.17.4. SPC Register Description
- 3.17.4.1. SPC DECPORT0 Status Register(Default Value: 0x00000000)
- 3.17.4.2. SPC DECPORT0 Set Register(Default Value: 0x00000000)
- 3.17.4.3. SPC DECPORT0 Clear Register(Default Value: 0x00000000)
- 3.17.4.4. SPC DECPORT1 Status Register(Default Value: 0x00000000)
- 3.17.4.5. SPC DECPORT1 Set Register(Default Value: 0x00000000)
- 3.17.4.6. SPC DECPORT1 Clear Register(Default Value: 0x00000000)
- 3.17.4.7. SPC DECPORT2 Status Register(Default Value: 0x00000000)
- 3.17.4.8. SPC DECPORT2 Set Register(Default Value: 0x00000000)
- 3.17.4.9. SPC DECPORT2 Clear Register(Default Value: 0x00000000)
- 3.17.4.10. SPC DECPORT3 Status Register(Default Value: 0x00000000)
- 3.17.4.11. SPC DECPORT3 Set Register(Default Value: 0x00000000)
- 3.17.4.12. SPC DECPORT3 Clear Register(Default Value: 0x00000000)
- 3.17.4.13. SPC DECPORT4 Status Register(Default Value: 0x00000000)
- 3.17.4.14. SPC DECPORT4 Set Register(Default Value: 0x00000000)
- 3.17.4.15. SPC DECPORT4 Clear Register(Default Value: 0x00000000)
- 3.17.4.16. SPC DECPORT5 Status Register(Default Value: 0x00000000)
- 3.17.4.17. SPC DECPORT5 Set Register(Default Value: 0x00000000)
- 3.17.4.18. SPC DECPORT5 Clear Register(Default Value: 0x00000000)
- 3.18. Thermal Sensor Controller
- 3.18.1. Overview
- 3.18.2. Clock and Timing Requirements
- 3.18.3. Temperature Conversion Formula
- 3.18.4. Thermal Sensor Register List
- 3.18.5. Thermal Sensor Register Description
- 3.18.5.1. THS Control Register0 (Default Value: 0x00000000)
- 3.18.5.2. THS Control Register1 (Default Value: 0x00000000)
- 3.18.5.3. ADC calibration Data Register (Default Value: 0x00000000)
- 3.18.5.4. THS Control Register2 (Default Value: 0x00040000)
- 3.18.5.5. THS Interrupt Control Register (Default Value: 0x00000000)
- 3.18.5.6. THS status Register (Default Value: 0x00000000)
- 3.18.5.7. Alarm threshold Control Register0 (Default Value: 0x05a00684)
- 3.18.5.8. Alarm threshold Control Register1 (Default Value: 0x05a00684)
- 3.18.5.9. Alarm threshold Control Register2 (Default Value: 0x05a00684)
- 3.18.5.10. Shutdown threshold Control Register0 (Default Value: 0x04e90000)
- 3.18.5.11. Shutdown threshold Control Register1 (Default Value: 0x04e90000)
- 3.18.5.12. Shutdown threshold Control Register2 (Default Value: 0x04e90000)
- 3.18.5.13. Average filter Control Register (Default Value: 0x00000001)
- 3.18.5.14. Thermal Sensor 0&1 calibration Data Register (Default Value: 0x08000800)
- 3.18.5.15. Thermal Sensor 2 calibration Data Register (Default Value: 0x00000800)
- 3.18.5.16. THS0 Data Register (Default Value: 0x00000000)
- 3.18.5.17. THS1 Data Register (Default Value: 0x00000000)
- 3.18.5.18. THS2 Data Register (Default Value: 0x00000000)
- 3.19. KEYADC
- 3.20. Audio Codec
- 3.20.1. Overview
- 3.20.2. Power and Signal Description
- 3.20.3. Data Path Diagram
- 3.20.4. Audio Codec Register List
- 3.20.5. Audio Codec Register Description
- 3.20.5.1. 0x00 I2S_AP Control Register(Default Value: 0x00000000)
- 3.20.5.2. 0x04 I2S_AP Format Register0(Default Value: 0x0000000C)
- 3.20.5.3. 0x08 I2S_AP Format Register1(Default Value: 0x00004020)
- 3.20.5.4. 0x0C I2S_AP Interrupt Status Register(Default Value: 0x00000010)
- 3.20.5.5. 0x10 I2S_AP RX FIFO Register(Default Value: 0x00000000)
- 3.20.5.6. 0x14 I2S_AP FIFO Control Register(Default Value: 0x000400F0)
- 3.20.5.7. 0x18 I2S_AP FIFO Status Register(Default Value: 0x10800000)
- 3.20.5.8. 0x1C I2S_AP DMA&Interrupt Control Register(Default Value: 0x00000000)
- 3.20.5.9. 0x20 I2S_AP TX FIFO Register(Default Value: 0x00000000)
- 3.20.5.10. 0x24 I2S_AP Clock Divide Register(Default Value: 0x00000000)
- 3.20.5.11. 0x28 I2S_AP TX Counter Register(Default Value: 0x00000000)
- 3.20.5.12. 0x2C I2S_AP RX Counter Register(Default Value: 0x00000000)
- 3.20.5.13. 0x30 I2S_AP TX Channel Select Register(Default Value: 0x00000001)
- 3.20.5.14. 0x34 I2S_AP TX Channel Mapping Register(Default Value: 0x76543210)
- 3.20.5.15. 0x38 I2S_AP RX Channel Select Register(Default Value: 0x00000001)
- 3.20.5.16. 0x3C I2S_AP RX Channel Mapping Register(Default Value: 0x00003210)
- 3.20.5.17. 0x200 Codec Reset Register(Default Value: 0x00000101)
- 3.20.5.18. 0x20C System Clock Control Register(Default Value: 0x00000000)
- 3.20.5.19. 0x210 Module Clock Control Register(Default Value: 0x00000000)
- 3.20.5.20. 0x214 Module Reset Control Register(Default Value: 0x00000000)
- 3.20.5.21. 0x218 System Sample rate & SRC Configuration Register(Default Value: 0x00000000)
- 3.20.5.22. 0x21C System SRC Clock Source Select Register(Default Value: 0x00000000)
- 3.20.5.23. 0x220 System DVC Mode Select Register(Default Value: 0x00000000)
- 3.20.5.24. 0x240 AIF1 BCLK/LRCK Control Register(Default Value: 0x00000000)
- 3.20.5.25. 0x244 AIF1 ADCDAT Control Register(Default Value: 0x00000000)
- 3.20.5.26. 0x248 AIF1 DACDAT Control Register(Default Value: 0x00000000)
- 3.20.5.27. 0x24C AIF1 Digital Mixer Source Select Register(Default Value: 0x00000000)
- 3.20.5.28. 0x250 AIF1 Volume Control 1 Register(Default Value: 0x0000A0A0)
- 3.20.5.29. 0x254 AIF1 Volume Control 2 Register(Default Value: 0x0000A0A0)
- 3.20.5.30. 0x258 AIF1 Volume Control 3 Register(Default Value: 0x0000A0A0)
- 3.20.5.31. 0x25C AIF1 Volume Control 4 Register(Default Value: 0x0000A0A0)
- 3.20.5.32. 0x260 AIF1 Digital Mixer Gain Control Register(Default Value: 0x00000000)
- 3.20.5.33. 0x264 AIF1 Receiver Data Discarding Control Register(Default Value: 0x00000000)
- 3.20.5.34. 0x280 AIF2 BCLK/LRCK Control Register(Default Value: 0x00000000)
- 3.20.5.35. 0x284 AIF2 ADCDAT Control Register(Default Value: 0x00000000)
- 3.20.5.36. 0x288 AIF2 DACDAT Control Register(Default Value: 0x00000000)
- 3.20.5.37. 0x28C AIF2 Digital Mixer Source Select Register(Default Value: 0x00000000)
- 3.20.5.38. 0x290 AIF2 Volume Control 1 Register(Default Value: 0x0000A0A0)
- 3.20.5.39. 0x298 AIF2 Volume Control 2 Register(Default Value: 0x0000A0A0)
- 3.20.5.40. 0x2A0 AIF2 Digital Mixer Gain Control Register(Default Value: 0x00000000)
- 3.20.5.41. 0x2A4 AIF2 Receiver Data Discarding Control Register(Default Value: 0x00000000)
- 3.20.5.42. 0x2C0 AIF3 BCLK/LRCK Control Register(Default Value: 0x00000000)
- 3.20.5.43. 0x2C4 AIF3 ADCDAT Control Register(Default Value: 0x00000000)
- 3.20.5.44. 0x2C8 AIF3 DACDAT Control Register(Default Value: 0x00000000)
- 3.20.5.45. 0x2CC AIF3 Signal Path Control Register(Default Value: 0x00000000)
- 3.20.5.46. 0x2E4 AIF3 Receiver Data Discarding Control Register(Default Value: 0x00000000)
- 3.20.5.47. 0x300 ADC Digital Control Register(Default Value: 0x00000000)
- 3.20.5.48. 0x304 ADC Volume Control Register(Default Value: 0x0000A0A0)
- 3.20.5.49. 0x308 ADC Debug Control Register(Default Value: 0x00000000)
- 3.20.5.50. 0x310 HMIC Control 1 Register(Default Value: 0x00000020)
- 3.20.5.51. 0x314 HMIC Control 2 Register(Default Value: 0x00000000)
- 3.20.5.52. 0x318 HMIC Status Register(Default Value: 0x00000000)
- 3.20.5.53. 0x320 DAC Digital Control Register(Default Value: 0x00000000)
- 3.20.5.54. 0x324 DAC Volume Control Register(Default Value: 0x0000A0A0)
- 3.20.5.55. 0x328 DAC Debug Control Register(Default Value: 0x00000000)
- 3.20.5.56. 0x330 DAC Digital Mixer Source Select Register(Default Value: 0x00000000)
- 3.20.5.57. 0x334 DAC Digital Mixer Gain Control Register(Default Value: 0x00000000)
- 3.20.5.58. 0x400 ADC DAP Left Status Register(Default Value: 0x00000000)
- 3.20.5.59. 0x404 ADC DAP Right Status Register(Default Value: 0x00000000)
- 3.20.5.60. 0x408 ADC DAP Left Channel Control Register(Default Value: 0x00000000)
- 3.20.5.61. 0x40C ADC DAP Right Channel Control Register(Default Value: 0x00000000)
- 3.20.5.62. 0x410 ADC DAP Left Target Level Register(Default Value: 0x00002C28)
- 3.20.5.63. 0x414 ADC DAP Right Target Level Register(Default Value: 0x00002C28)
- 3.20.5.64. 0x418 ADC DAP Left High Average Coef Register(Default Value: 0x00000005)
- 3.20.5.65. 0x41C ADC DAP Left Low Average Coef Register(Default Value: 0x00001EB8)
- 3.20.5.66. 0x420 ADC DAP Right High Average Coef Register(Default Value: 0x00000005)
- 3.20.5.67. 0x424 ADC DAP Right Low Average Coef Register(Default Value: 0x00001EB8)
- 3.20.5.68. 0x428 ADC DAP Left Decay Time Register(Default Value: 0x0000001F)
- 3.20.5.69. 0x42C ADC DAP Left Attack Time Register(Default Value: 0x00000000)
- 3.20.5.70. 0x430 ADC DAP Right Decay Time Register(Default Value: 0x0000001F)
- 3.20.5.71. 0x434 ADC DAP Right Attack Time Register(Default Value: 0x00000000)
- 3.20.5.72. 0x438 ADC DAP Noise Threshold Register(Default Value: 0x00001E1E)
- 3.20.5.73. 0x43C ADC DAP Left Input Signal High Average Coef Register(Default Value: 0x00000005)
- 3.20.5.74. 0x440 ADC DAP Left Input Signal Low Average Coef Register(Default Value: 0x00001EB8)
- 3.20.5.75. 0x444 ADC DAP Right Input Signal High Average Coef Register(Default Value: 0x00000005)
- 3.20.5.76. 0x448 ADC DAP Right Input Signal Low Average Coef Register(Default Value: 0x00001EB8)
- 3.20.5.77. 0x44C ADC DAP High HPF Coef Register(Default Value: 0x000000FF)
- 3.20.5.78. 0x450 ADC DAP Low HPF Coef Register(Default Value: 0x0000FAC1)
- 3.20.5.79. 0x454 ADC DAP Optimum Register(Default Value: 0x00000000)
- 3.20.5.80. 0x480 DAC DAP Control Register(Default Value: 0x00000000)
- 3.20.5.81. 0x4D0 AGC Enable Register(Default Value: 0x00000000)
- 3.20.5.82. 0x4D4 DRC Enable Register(Default Value: 0x00000000)
- 3.20.5.83. 0x4D8 SRC Bist Control Register(Default Value: 0x00000000)
- 3.20.5.84. 0x4DC SRC Bist Status Register(Default Value: 0x00000202)
- 3.20.5.85. 0x4E0 SRC1 Control 1 Register(Default Value: 0x00000000)
- 3.20.5.86. 0x4E4 SRC1 Control 2 Register(Default Value: 0x00000000)
- 3.20.5.87. 0x4E8 SRC1 Control 3 Register(Default Value: 0x00000040)
- 3.20.5.88. 0x4EC SRC1 Control 4 Register(Default Value: 0x00000000)
- 3.20.5.89. 0x4F0 SRC2 Control 1 Register(Default Value: 0x00000000)
- 3.20.5.90. 0x4F4 SRC2 Control 2 Register(Default Value: 0x00000000)
- 3.20.5.91. 0x4F8 SRC2 Control 3 Register(Default Value: 0x00000040)
- 3.20.5.92. 0x4FC SRC2 Control 4 Register(Default Value: 0x00000000)
- 3.20.5.93. 0x600 DRC0 High HPF Coef Register(Default Value: 0x000000FF)
- 3.20.5.94. 0x604 DRC0 Low HPF Coef Register(Default Value: 0x0000FAC1)
- 3.20.5.95. 0x608 DRC0 Control Register(Default Value: 0x00000080)
- 3.20.5.96. 0x60C DRC0 Left Peak Filter High Attack Time Coef Register(Default Value: 0x0000000B)
- 3.20.5.97. 0x610 DRC0 Left Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)
- 3.20.5.98. 0x614 DRC0 Right Peak Filter High Attack Time Coef Register(Default Value: 0x0000000B)
- 3.20.5.99. 0x618 DRC0 Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)
- 3.20.5.100. 0x61C DRC0 Left Peak Filter High Release Time Coef Register(Default Value: 0x000000FF)
- 3.20.5.101. 0x620 DRC0 Left Peak Filter Low Release Time Coef Register(Default Value: 0x0000E1F8)
- 3.20.5.102. 0x624 DRC0 Right Peak filter High Release Time Coef Register(Default Value: 0x000000FF)
- 3.20.5.103. 0x628 DRC0 Right Peak filter Low Release Time Coef Register(Default Value: 0x0000E1F8)
- 3.20.5.104. 0x62C DRC0 Left RMS Filter High Coef Register(Default Value: 0x00000001)
- 3.20.5.105. 0x630 DRC0 Left RMS Filter Low Coef Register(Default Value: 0x00002BAF)
- 3.20.5.106. 0x634 DRC0 Right RMS Filter High Coef Register(Default Value: 0x00000001)
- 3.20.5.107. 0x638 DRC0 Right RMS Filter Low Coef Register(Default Value: 0x00002BAF)
- 3.20.5.108. 0x63C DRC0 Compressor Theshold High Setting Register(Default Value: 0x000006A4)
- 3.20.5.109. 0x640 DRC0 Compressor Theshold Low Setting Register(Default Value: 0x0000D3C0)
- 3.20.5.110. 0x644 DRC0 Compressor Slope High Setting Register(Default Value: 0x00000080)
- 3.20.5.111. 0x648 DRC0 Compressor Slope Low Setting Register(Default Value: 0x00000000)
- 3.20.5.112. 0x64C DRC0 Compressor High Output at Compressor Threshold Register(Default Value: 0x0000F95B)
- 3.20.5.113. 0x650 DRC0 Compressor Low Output at Compressor Threshold Register(Default Value: 0x00002C3F)
- 3.20.5.114. 0x654 DRC0 Limiter Theshold High Setting Register(Default Value: 0x000001A9)
- 3.20.5.115. 0x658 DRC0 Limiter Theshold Low Setting Register(Default Value: 0x000034F0)
- 3.20.5.116. 0x65C DRC0 Limiter Slope High Setting Register(Default Value: 0x00000005)
- 3.20.5.117. 0x660 DRC0 Limiter Slope Low Setting Register(Default Value: 0x00001EB8)
- 3.20.5.118. 0x664 DRC0 Limiter High Output at Limiter Threshold Register(Default Value: 0x0000FBD8)
- 3.20.5.119. 0x668 DRC0 Limiter Low Output at Limiter Threshold Register(Default Value: 0x0000FBA7)
- 3.20.5.120. 0x66C DRC0 Expander Theshold High Setting Register(Default Value: 0x00000BA0)
- 3.20.5.121. 0x670 DRC0 Expander Theshold Low Setting Register(Default Value: 0x00007291)
- 3.20.5.122. 0x674 DRC0 Expander Slope High Setting Register(Default Value: 0x00000500)
- 3.20.5.123. 0x678 DRC0 Expander Slope Low Setting Register(Default Value: 0x00000000)
- 3.20.5.124. 0x67C DRC0 Expander High Output at Expander Threshold Register(Default Value: 0x0000F45F)
- 3.20.5.125. 0x680 DRC0 Expander Low Output at Expander Threshold Register(Default Value: 0x00008D6E)
- 3.20.5.126. 0x684 DRC0 Linear Slope High Setting Register(Default Value: 0x00000100)
- 3.20.5.127. 0x688 DRC0 Linear Slope Low Setting Register(Default Value: 0x00000000)
- 3.20.5.128. 0x68C DRC0 Smooth filter Gain High Attack Time Coef Register(Default Value: 0x00000002)
- 3.20.5.129. 0x690 DRC0 Smooth filter Gain Low Attack Time Coef Register(Default Value: 0x00005600)
- 3.20.5.130. 0x694 DRC0 Smooth filter Gain High Release Time Coef Register(Default Value: 0x00000000)
- 3.20.5.131. 0x698 DRC0 Smooth filter Gain Low Release Time Coef Register(Default Value: 0x00000F04)
- 3.20.5.132. 0x69C DRC0 MAX Gain High Setting Register(Default Value: 0x0000FE56)
- 3.20.5.133. 0x6A0 DRC0 MAX Gain Low Setting Register(Default Value: 0x0000CB0F)
- 3.20.5.134. 0x6A4 DRC0 MIN Gain High Setting Register(Default Value: 0x0000F95B)
- 3.20.5.135. 0x6A8 DRC0 MIN Gain Low Setting Register(Default Value: 0x00002C3F)
- 3.20.5.136. 0x6AC DRC0 Expander Smooth Time High Coef Register(Default Value: 0x00000000)
- 3.20.5.137. 0x6B0 DRC0 Expander Smooth Time Low Coef Register(Default Value: 0x0000640C)
- 3.20.5.138. 0x6B4 DRC0 Optimum Register(Default Value: 0x00000000)
- 3.20.5.139. 0x6B8 DRC0 HPF Gain High Coef Register(Default Value: 0x00000100)
- 3.20.5.140. 0x6BC DRC0 HPF Gain Low Coef Register(Default Value: 0x00000000)
- 3.20.5.141. 0x700 DRC1 High HPF Coef Register(Default Value: 0x000000FF)
- 3.20.5.142. 0x704 DRC1 Low HPF Coef Register(Default Value: 0x0000FAC1)
- 3.20.5.143. 0x708 DRC1 Control Register(Default Value: 0x00000080)
- 3.20.5.144. 0x70C DRC1 Left Peak Filter High Attack Time Coef Register(Default Value: 0x0000000B)
- 3.20.5.145. 0x710 DRC1 Left Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)
- 3.20.5.146. 0x714 DRC1 Right Peak Filter High Attack Time Coef Register(Default Value: 0x0000000B)
- 3.20.5.147. 0x718 DRC1 Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)
- 3.20.5.148. 0x71C DRC1 Left Peak Filter High Release Time Coef Register(Default Value: 0x000000FF)
- 3.20.5.149. 0x720 DRC1 Left Peak Filter Low Release Time Coef Register(Default Value: 0x0000E1F8)
- 3.20.5.150. 0x724 DRC1 Right Peak filter High Release Time Coef Register(Default Value: 0x000000FF)
- 3.20.5.151. 0x728 DRC1 Right Peak filter Low Release Time Coef Register(Default Value: 0x0000E1F8)
- 3.20.5.152. 0x72C DRC Left RMS Filter High Coef Register(Default Value: 0x00000001)
- 3.20.5.153. 0x730 DRC1 Left RMS Filter Low Coef Register(Default Value: 0x00002BAF)
- 3.20.5.154. 0x734 DRC1 Right RMS Filter High Coef Register(Default Value: 0x00000001)
- 3.20.5.155. 0x738 DRC1 Right RMS Filter Low Coef Register(Default Value: 0x00002BAF)
- 3.20.5.156. 0x73C DRC1 Compressor Theshold High Setting Register(Default Value: 0x000006A4)
- 3.20.5.157. 0x740 DRC1 Compressor Slope High Setting Register(Default Value: 0x0000D3D0)
- 3.20.5.158. 0x744 DRC1 Compressor Slope High Setting Register(Default Value: 0x00000080)
- 3.20.5.159. 0x748 DRC1 Compressor Slope Low Setting Register(Default Value: 0x00000000)
- 3.20.5.160. 0x74C DRC1 Compressor High Output at Compressor Threshold Register(Default Value: 0x0000F95B)
- 3.20.5.161. 0x750 DRC1 Compressor Low Output at Compressor Threshold Register(Default Value: 0x00002C3F)
- 3.20.5.162. 0x754 DRC1 Limiter Theshold High Setting Register(Default Value: 0x000001A9)
- 3.20.5.163. 0x758 DRC1 Limiter Theshold Low Setting Register(Default Value: 0x000034F0)
- 3.20.5.164. 0x75C DRC1 Limiter Slope High Setting Register(Default Value: 0x00000005)
- 3.20.5.165. 0x760 DRC1 Limiter Slope Low Setting Register(Default Value: 0x00001EB8)
- 3.20.5.166. 0x764 DRC1 Limiter High Output at Limiter Threshold Register(Default Value: 0x0000FBD8)
- 3.20.5.167. 0x768 DRC1 Limiter Low Output at Limiter Threshold Register(Default Value: 0x0000FBA7)
- 3.20.5.168. 0x76C DRC1 Expander Theshold High Setting Register(Default Value: 0x00000BA0)
- 3.20.5.169. 0x770 DRC1 Expander Theshold Low Setting Register(Default Value: 0x00007291)
- 3.20.5.170. 0x774 DRC1 Expander Slope High Setting Register(Default Value: 0x00000500)
- 3.20.5.171. 0x778 DRC1 Expander Slope Low Setting Register(Default Value: 0x00000000)
- 3.20.5.172. 0x77C DRC1 Expander High Output at Expander Threshold Register(Default Value: 0x0000F45F)
- 3.20.5.173. 0x780 DRC1 Expander Low Output at Expander Threshold Register(Default Value: 0x00008D6E)
- 3.20.5.174. 0x784 DRC1 Linear Slope High Setting Register(Default Value: 0x00000100)
- 3.20.5.175. 0x788 DRC1 Linear Slope Low Setting Register(Default Value: 0x00000000)
- 3.20.5.176. 0x78C DRC1 Smooth filter Gain High Attack Time Coef Register(Default Value: 0x00000002)
- 3.20.5.177. 0x790 DRC1 Smooth filter Gain Low Attack Time Coef Register(Default Value: 0x00005600)
- 3.20.5.178. 0x794 DRC1 Smooth filter Gain High Release Time Coef Register(Default Value: 0x00000000)
- 3.20.5.179. 0x798 DRC1 Smooth filter Gain Low Release Time Coef Register(Default Value: 0x00000F04)
- 3.20.5.180. 0x79C DRC1 MAX Gain High Setting Register(Default Value: 0x0000FE56)
- 3.20.5.181. 0x7A0 DRC1 MAX Gain Low Setting Register(Default Value: 0x0000CB0F)
- 3.20.5.182. 0x7A4 DRC1 MIN Gain High Setting Register(Default Value: 0x0000F95B)
- 3.20.5.183. 0x7A8 DRC1 MIN Gain Low Setting Register(Default Value: 0x00002C3F)
- 3.20.5.184. 0x7AC DRC1 Expander Smooth Time High Coef Register(Default Value: 0x00000000)
- 3.20.5.185. 0x7B0 DRC1 Expander Smooth Time Low Coef Register(Default Value: 0x0000640C)
- 3.20.5.186. 0x7B8 DRC1 HPF Gain High Coef Register(Default Value: 0x00000100)
- 3.20.5.187. 0x7BC DRC1 HPF Gain Low Coef Register(Default Value: 0x00000000)
- 3.20.5.188. AC_PR Configuration Register
- 3.20.5.189. 0x00 Headphone Amplifier Control Register(Default Value: 0x00)
- 3.20.5.190. 0x01 Output Left Mixer Control Register(Default Value: 0x00)
- 3.20.5.191. 0x02 Output Right Mixer Control Register(Default Value: 0x00)
- 3.20.5.192. 0x03 Earpiece Control Register 0 (Default Value: 0x00)
- 3.20.5.193. 0x04 Earpiece Control Register 1 (Default Value: 0x00)
- 3.20.5.194. 0x05 LINEOUT Control Register 0 (Default Value: 0x00)
- 3.20.5.195. 0x06 LINEOUT Control Register 1 (Default Value: 0x00)
- 3.20.5.196. 0x07 MIC1 Control Register (Default Value: 0x34)
- 3.20.5.197. 0x08 MIC2 Control Register (Default Value: 0x11)
- 3.20.5.198. 0x09 Linein Control Register (Default Value: 0x03)
- 3.20.5.199. 0x0A Mixer and DAC Control Register (Default Value: 0x00)
- 3.20.5.200. 0x0B Left ADC Mixer Control Register (Default Value: 0x00)
- 3.20.5.201. 0x0C Right ADC Mixer Control Register (Default Value: 0x00)
- 3.20.5.202. 0x0D ADC Control Register (Default Value: 0x03)
- 3.20.5.203. 0x0E Headset Microphone Bias Control Register (Default Value: 0x21)
- 3.20.5.204. 0x0F Analog Performance Tuning Register (Default Value: 0xD6)
- 3.20.5.205. 0x10 OP BIAS Control Register0 (Default Value: 0x55)
- 3.20.5.206. 0x11 OP BIAS Control Register1 (Default Value: 0x55)
- 3.20.5.207. 0x12 USB Bias & Volume Change Control Register (Default Value: 0x02)
- 3.20.5.208. 0x13 Bias Calibration Data Register (Default Value: 0x00)
- 3.20.5.209. 0x14 Bias Calibration Set Data Register (Default Value: 0x20)
- 3.20.5.210. 0x15 Bias & DA16 Calibration Control Register (Default Value: 0x00)
- 3.20.5.211. 0x16 Headphone PA Control Register (Default Value: 0xF1)
- 3.20.5.212. 0x17 Headphone Calibration Control Register (Default Value: 0x04)
- 3.20.5.213. 0x18 Right Headphone Calibration DAT Register (Default Value: 0x00)
- 3.20.5.214. 0x19 Right Headphone Calibration Setting Register (Default Value: 0x80)
- 3.20.5.215. 0x1A Left Headphone Calibration DAT Register (Default Value: 0x00)
- 3.20.5.216. 0x1B Left Headphone Calibration Setting Register (Default Value: 0x80)
- 3.20.5.217. 0x1C Mic detect Control Register (Default Value: 0x40)
- 3.20.5.218. 0x1D Jack & Mic detect Control Register (Default Value: 0x00)
- 3.20.5.219. 0x1E Phone Output Register (Default Value: 0x60)
- 3.20.5.220. 0x1F Phone Input Register (Default Value: 0x34)
- 3.21. Port Controller(CPUx-PORT)
- 3.21.1. Port Controller Register List
- 3.21.2. Port Controller Register Description
- 3.21.2.1. PB Configure Register 0 (Default Value: 0x77777777)
- 3.21.2.2. PB Configure Register 1 (Default Value: 0x00000077)
- 3.21.2.3. PB Configure Register 2 (Default Value: 0x00000000)
- 3.21.2.4. PB Configure Register 3 (Default Value: 0x00000000)
- 3.21.2.5. PB Data Register (Default Value: 0x00000000)
- 3.21.2.6. PB Multi-Driving Register 0 (Default Value: 0x00055555)
- 3.21.2.7. PB Multi-Driving Register 1 (Default Value: 0x00000000)
- 3.21.2.8. PB PULL Register 0 (Default Value: 0x00000000)
- 3.21.2.9. PB PULL Register 1 (Default Value: 0x00000000)
- 3.21.2.10. PC Configure Register 0 (Default Value: 0x77777777)
- 3.21.2.11. PC Configure Register 1 (Default Value: 0x77777777)
- 3.21.2.12. PC Configure Register 2 (Default Value: 0x00000777)
- 3.21.2.13. PC Configure Register 3 (Default Value: 0x00000000)
- 3.21.2.14. PC Data Register (Default Value: 0x00000000)
- 3.21.2.15. PC Multi-Driving Register 0 (Default Value: 0x55555555)
- 3.21.2.16. PC Multi-Driving Register 1 (Default Value: 0x00000015)
- 3.21.2.17. PC PULL Register 0 (Default Value: 0x00005140)
- 3.21.2.18. PC PULL Register 1 (Default Value: 0x00000014)
- 3.21.2.19. PD Configure Register 0 (Default Value: 0x77777777)
- 3.21.2.20. PD Configure Register 1 (Default Value: 0x77777777)
- 3.21.2.21. PD Configure Register 2 (Default Value: 0x77777777)
- 3.21.2.22. PD Configure Register 3 (Default Value: 0x00000007)
- 3.21.2.23. PD Data Register (Default Value: 0x00000000)
- 3.21.2.24. PD Multi-Driving Register 0 (Default Value: 0x55555555)
- 3.21.2.25. PD Multi-Driving Register 1 (Default Value: 0x00015555)
- 3.21.2.26. PD PULL Register 0 (Default Value: 0x00000000)
- 3.21.2.27. PD PULL Register 1 (Default Value: 0x00000000)
- 3.21.2.28. PE Configure Register 0 (Default Value: 0x77777777)
- 3.21.2.29. PE Configure Register 1 (Default Value: 0x77777777)
- 3.21.2.30. PE Configure Register 2 (Default Value: 0x00000077)
- 3.21.2.31. PE Configure Register 3 (Default Value: 0x00000000)
- 3.21.2.32. PE Data Register (Default Value: 0x00000000)
- 3.21.2.33. PE Multi-Driving Register 0 (Default Value: 0x55555555)
- 3.21.2.34. PE Multi-Driving Register 1 (Default Value: 0x00000005)
- 3.21.2.35. PE PULL Register 0 (Default Value: 0x00000000)
- 3.21.2.36. PE PULL Register 1 (Default Value: 0x00000000)
- 3.21.2.37. PF Configure Register 0 (Default Value: 0x07777777)
- 3.21.2.38. PF Configure Register 1 (Default Value: 0x00000000)
- 3.21.2.39. PF Configure Register 2(Default Value: 0x00000000)
- 3.21.2.40. PF Configure Register 3(Default Value: 0x00000000)
- 3.21.2.41. PF Data Register (Default Value: 0x00000000)
- 3.21.2.42. PF Multi-Driving Register 0 (Default Value: 0x00001555)
- 3.21.2.43. PF Multi-Driving Register 1 (Default Value: 0x00000000)
- 3.21.2.44. PF PULL Register 0 (Default Value: 0x00000000)
- 3.21.2.45. PF PULL Register 1 (Default Value: 0x00000000)
- 3.21.2.46. PG Configure Register 0 (Default Value: 0x77777777)
- 3.21.2.47. PG Configure Register 1 (Default Value: 0x00777777)
- 3.21.2.48. PG Configure Register 2 (Default Value: 0x00000000)
- 3.21.2.49. PG Configure Register 3 (Default Value: 0x00000000)
- 3.21.2.50. PG Data Register (Default Value: 0x00000000)
- 3.21.2.51. PG Multi-Driving Register 0 (Default Value: 0x05555555)
- 3.21.2.52. PG Multi-Driving Register 1 (Default Value: 0x00000000)
- 3.21.2.53. PG PULL Register 0 (Default Value: 0x00000000)
- 3.21.2.54. PG PULL Register 1 (Default Value: 0x00000000)
- 3.21.2.55. PH Configure Register 0 (Default Value: 0x77777777)
- 3.21.2.56. PH Configure Register 1 (Default Value: 0x00007777)
- 3.21.2.57. PH Configure Register 2 (Default Value: 0x00000000)
- 3.21.2.58. PH Configure Register 3 (Default Value: 0x00000000)
- 3.21.2.59. PH Data Register (Default Value: 0x00000000)
- 3.21.2.60. PH Multi-Driving Register 0 (Default Value: 0x00555555)
- 3.21.2.61. PH Multi-Driving Register 1 (Default Value: 0x00000000)
- 3.21.2.62. PH PULL Register 0 (Default Value: 0x00000000)
- 3.21.2.63. PH PULL Register 1 (Default Value: 0x00000000)
- 3.21.2.64. PB External Interrupt Configure Register 0 (Default Value: 0x00000000)
- 3.21.2.65. PB External Interrupt Configure Register 1 (Default Value: 0x00000000)
- 3.21.2.66. PB External Interrupt Configure Register 2 (Default Value: 0x00000000)
- 3.21.2.67. PB External Interrupt Configure Register 3 (Default Value: 0x00000000)
- 3.21.2.68. PB External Interrupt Control Register (Default Value: 0x00000000)
- 3.21.2.69. PB External Interrupt Status Register (Default Value: 0x00000000)
- 3.21.2.70. PB External Interrupt Debounce Register (Default Value: 0x00000000)
- 3.21.2.71. PG External Interrupt Configure Register 0 (Default Value: 0x00000000)
- 3.21.2.72. PG External Interrupt Configure Register 1 (Default Value: 0x00000000)
- 3.21.2.73. PG External Interrupt Configure Register 2 (Default Value: 0x00000000)
- 3.21.2.74. PG External Interrupt Configure Register 3 (Default Value: 0x00000000)
- 3.21.2.75. PG External Interrupt Control Register (Default Value: 0x00000000)
- 3.21.2.76. PG External Interrupt Status Register (Default Value: 0x00000000)
- 3.21.2.77. PG External Interrupt Debounce Register (Default Value: 0x00000000)
- 3.21.2.78. PH External Interrupt Configure Register 0 (Default Value: 0x00000000)
- 3.21.2.79. PH External Interrupt Configure Register 1 (Default Value: 0x00000000)
- 3.21.2.80. PH External Interrupt Configure Register2 (Default Value: 0x00000000)
- 3.21.2.81. PH External Interrupt Configure Register3 (Default Value: 0x00000000)
- 3.21.2.82. PH External Interrupt Control Register (Default Value: 0x00000000)
- 3.21.2.83. PH External Interrupt Status Register (Default Value: 0x00000000)
- 3.21.2.84. PH External Interrupt Debounce Register (Default Value: 0x00000000)
- 3.22. Port Controller(CPUs-PORT)
- 3.22.1. Port Controller Register List
- 3.22.2. Port Controller Register Description
- 3.22.2.1. PL Configure Register 0 (Default Value: 0x77777777)
- 3.22.2.2. PL Configure Register 1 (Default Value: 0x00077777)
- 3.22.2.3. PL Configure Register 2 (Default Value: 0x00000000)
- 3.22.2.4. PL Configure Register 3 (Default Value: 0x00000000)
- 3.22.2.5. PL Data Register (Default Value: 0x00000000)
- 3.22.2.6. PL Multi-Driving Register 0 (Default Value: 0x01555555)
- 3.22.2.7. PL Multi-Driving Register 1 (Default Value: 0x00000000)
- 3.22.2.8. PL PULL Register 0 (Default Value: 0x00000005)
- 3.22.2.9. PL PULL Register 1 (Default Value: 0x00000000)
- 3.22.2.10. PL External Interrupt Configure Register 0 (Default Value: 0x00000000)
- 3.22.2.11. PL External Interrupt Configure Register 1 (Default Value: 0x00000000)
- 3.22.2.12. PL External Interrupt Configure Register 2 (Default Value: 0x00000000)
- 3.22.2.13. PL External Interrupt Configure Register 3 (Default Value: 0x00000000)
- 3.22.2.14. PL External Interrupt Control Register (Default Value: 0x00000000)
- 3.22.2.15. PL External Interrupt Status Register (Default Value: 0x00000000)
- 3.22.2.16. PL External Interrupt Debounce Register (Default Value: 0x00000000)
- Chapter 4 Memory
- 4.1. SDRAM
- 4.2. NAND Flash Controller(NDFC)
- 4.2.1. Overview
- 4.2.2. Block Diagram
- 4.2.3. NDFC Timing Diagram
- 4.2.4. NDFC Operation Guide
- 4.2.5. NDFC Register List
- 4.2.6. NDFC Register Description
- 4.2.6.1. NDFC Control Register(Default Value: 0x00000000)
- 4.2.6.2. NDFC Status Register(Default Value: 0x00000000)
- 4.2.6.3. NDFC Interrupt and DMA Enable Register(Default Value: 0x00000000)
- 4.2.6.4. NDFC Timing Control Register(Default Value: 0x00000000)
- 4.2.6.5. NDFC Timing Configure Register(Default Value: 0x00000095)
- 4.2.6.6. NDFC Address Low Word Register(Default Value: 0x00000000)
- 4.2.6.7. NDFC Address High Word Register(Default Value: 0x00000000)
- 4.2.6.8. NDFC Data Block Number Register(Default Value: 0x00000000)
- 4.2.6.9. NDFC Data Counter Register(Default Value: 0x00000000)
- 4.2.6.10. NDFC Command IO Register(Default Value: 0x00000000)
- 4.2.6.11. NDFC Command Set Register 0(Default Value: 0x00E00530)
- 4.2.6.12. NDFC Command Set Register 1(Default Value: 0x70008510)
- 4.2.6.13. NDFC IO Data Register(Default Value: 0x00000000)
- 4.2.6.14. NDFC ECC Control Register(Default Value: 0x4a800008)
- 4.2.6.15. NDFC ECC Status Register(Default Value: 0x00000000)
- 4.2.6.16. NDFC Enhanced Feature Register(Default Value: 0x00000000)
- 4.2.6.17. NDFC Error Counter Register 0(Default Value: 0x00000000)
- 4.2.6.18. NDFC Error Counter Register 1(Default Value: 0x00000000)
- 4.2.6.19. NDFC Error Counter Register 2(Default Value: 0x00000000)
- 4.2.6.20. NDFC Error Counter Register 3(Default Value: 0x00000000)
- 4.2.6.21. NDFC User Data Register [n]( Default Value: 0xffffffff)
- 4.2.6.22. NDFC EFNAND STATUS Register(Default Value: 0x00000000)
- 4.2.6.23. NDFC Spare Area Register(Default Value: 0x00000400)
- 4.2.6.24. NDFC Pattern ID Register(Default Value: 0x00000000)
- 4.2.6.25. NDFC Read Data Status Control Register(Default Value: 0x01000000)
- 4.2.6.26. NDFC Read Data Status Register 0(Default Value: 0x00000000)
- 4.2.6.27. NDFC Read Data Status Register 1(Default Value: 0x00000000)
- 4.2.6.28. NDFC MBUS DMA Address Register(Default Value: 0x00000000)
- 4.2.6.29. NDFC MBUS DMA Byte Counter Register(Default Value: 0x00000000)
- 4.2.6.30. NDFC Normal DMA Mode Control Register(Default Value: 0x000000A5)
- 4.3. SD-MMC Host Controller
- 4.3.1. Overview
- 4.3.2. Block Diagram
- 4.3.3. SMHC Controller Timing Diagram
- 4.3.4. SMHC Operation Description
- 4.3.5. SMHC DMA Controller Description
- 4.3.6. SMHC Register List
- 4.3.7. SMHC Register Description
- 4.3.7.1. SMHC Global Control Register(Default Value: 0x00000300)
- 4.3.7.2. SMHC Clock Control Register(Default Value: 0x00000000)
- 4.3.7.3. SMHC Timeout Register (Default Value: 0xFFFFFF40)
- 4.3.7.4. SMHC Bus Width Register (Default Value: 0x00000000)
- 4.3.7.5. SMHC Block Size Register (Default Value: 0x00000200)
- 4.3.7.6. SMHC Block Count Register (Default Value: 0x00000200)
- 4.3.7.7. SMHC Command Register (Default Value: 0x00000000)
- 4.3.7.8. SMHC Command Argument Register (Default Value: 0x00000000)
- 4.3.7.9. SMHC Response 0 Register (Default Value: 0x00000000)
- 4.3.7.10. SMHC Response 1 Register (Default Value: 0x00000000)
- 4.3.7.11. SMHC Response 2 Register (Default Value: 0x00000000)
- 4.3.7.12. SMHC Response 3 Register (Default Value: 0x00000000)
- 4.3.7.13. SMHC Interrupt Mask Register (Default Value: 0x00000000)
- 4.3.7.14. SMHC Masked Interrupt Status Register (Default Value: 0x00000000)
- 4.3.7.15. SMHC Raw Interrupt Status Register (Default Value: 0x00000000)
- 4.3.7.16. SMHC Status Register (Default Value: 0x00000006)
- 4.3.7.17. SMHC FIFO Water Level Register (Default Value: 0x000F0000)
- 4.3.7.18. SMHC Function Select Register (Default Value: 0x00000000)
- 4.3.7.19. SMHC Transferred Byte Count Register0 (Default Value: 0x00000000)
- 4.3.7.20. SMHC Transferred Byte Count Register1 (Default Value: 0x00000000)
- 4.3.7.21. SMHC CRC Status Detect Control Register (Default Value: 0x00000003)
- 4.3.7.22. SMHC Auto Command 12 Register (Default Value: 0x0000ffff)
- 4.3.7.23. SMHC NewTiming Set Register (Default Value: 0x00000000)
- 4.3.7.24. SMHC Hardware Reset Register (Default Value: 0x00000001)
- 4.3.7.25. SMHC DMAC Control Register (Default Value: 0x00000000)
- 4.3.7.26. SMHC Descriptor List Base Address Register (Default Value: 0x00000000)
- 4.3.7.27. SMHC DMAC Status Register (Default Value: 0x0000_0000)
- 4.3.7.28. SMHC DMAC Interrupt Enable Register (Default Value: 0x00000000)
- 4.3.7.29. SMHC Card Threshold Control Register (Default Value: 0x00000000)
- 4.3.7.30. SMHC eMMC4.5 DDR Start Bit Detection Control Register (Default Value: 0x00000000)
- 4.3.7.31. SMHC Response CRC Register (Default Value: 0x00000000)
- 4.3.7.32. SMHC Data7 CRC Register (Default Value: 0x00000000)
- 4.3.7.33. SMHC Data6 CRC Register (Default Value: 0x00000000)
- 4.3.7.34. SMHC Data5 CRC Register (Default Value: 0x00000000)
- 4.3.7.35. SMHC Data4 CRC Register (Default Value: 0x00000000)
- 4.3.7.36. SMHC Data3 CRC Register (Default Value: 0x00000000)
- 4.3.7.37. SMHC Data2 CRC Register (Default Value: 0x00000000)
- 4.3.7.38. SMHC Data1 CRC Register (Default Value: 0x00000000)
- 4.3.7.39. SMHC Data0 CRC Register (Default Value: 0x00000000)
- 4.3.7.40. SMHC CRC Status Register (Default Value: 0x00000000)
- 4.3.7.41. SMHC Drive Delay Control Register (Default Value: 0x00000000)
- 4.3.7.42. SMHC Sample Delay Control Register (Default Value: 0x00002000)
- 4.3.7.43. SMHC Data Strobe Delay Control Register (Default Value: 0x00002000)
- 4.3.7.44. SMHC FIFO Register (Default Value: 0x00000000)
- Chapter 5 Image
- 5.1. CSI
- 5.1.1. Overview
- 5.1.2. Functionalities Description
- 5.1.3. CSI Register list
- 5.1.4. CSI Register Description
- 5.1.4.1. CSI Enable Register (Default Value: 0x00000000)
- 5.1.4.2. CSI Interface Configuration Register (Default Value: 0x00000000)
- 5.1.4.3. CSI Capture Register (Default Value: 0x00000000)
- 5.1.4.4. CSI Synchronization Counter Register (Default Value: 0x00000000)
- 5.1.4.5. CSI FIFO Threshold Register (Default Value: 0x040f0400)
- 5.1.4.6. CSI Pattern Generation Length Register (Default Value: 0x00000000)
- 5.1.4.7. CSI Pattern Generation Address Register (Default Value: 0x00000000)
- 5.1.4.8. CSI Version Register (Default Value: 0x00000000)
- 5.1.4.9. CSI Channel_0 configuration Register (Default Value: 0x00300200)
- 5.1.4.10. CSI Channel_0 scale Register (Default Value: 0x00000000)
- 5.1.4.11. CSI Channel_0 FIFO 0 output buffer-A address Register (Default Value: 0x00000000)
- 5.1.4.12. CSI Channel_0 FIFO 1 output buffer-A address Register (Default Value: 0x00000000)
- 5.1.4.13. CSI Channel_0 FIFO 2 output buffer-A address Register (Default Value: 0x00000000)
- 5.1.4.14. CSI Channel_0 status Register (Default Value: 0x00000000)
- 5.1.4.15. CSI Channel_0 interrupt enable Register (Default Value: 0x00000000)
- 5.1.4.16. CSI Channel_0 interrupt status Register (Default Value: 0x00000000)
- 5.1.4.17. CSI Channel_0 horizontal size Register (Default Value: 0x05000000)
- 5.1.4.18. CSI Channel_0 vertical size Register (Default Value: 0x01E00000)
- 5.1.4.19. CSI Channel_0 buffer length Register (Default Value: 0x01400280)
- 5.1.4.20. CSI Channel_0 flip size Register (Default Value: 0x01E00280)
- 5.1.4.21. CSI Channel_0 frame clock counter Register (Default Value: 0x00000000)
- 5.1.4.22. CSI Channel_0 accumulated and internal clock counter Register (Default Value: 0x00000000)
- 5.1.4.23. CSI Channel_0 FIFO Statistic Register (Default Value: 0x00000000)
- 5.1.4.24. CSI Channel_0 PCLK Statistic Register (Default Value: 0x00007FFF)
- 5.1.4.25. CCI Control Register (Default Value: 0x00000000)
- 5.1.4.26. CCI Transmission Configuration Register (Default Value: 0x10000000)
- 5.1.4.27. CCI Packet Format Register (Default Value: 0x00110001)
- 5.1.4.28. CCI Bus Control Register (Default Value: 0x00002500)
- 5.1.4.29. CCI Interrupt Control Register (Default Value: 0x00000000)
- 5.1.4.30. CCI Line Counter Trigger Control Register (Default Value: 0x00000000)
- 5.1.4.31. CCI FIFO Acess Register (Default Value: 0x00000000)
- 5.1. CSI
- Chapter 6 Display
- 6.1. DE2.0
- 6.2. TCON
- 6.2.1. Overview
- 6.2.2. Block Diagram
- 6.2.3. Functionalities Description
- 6.2.4. TCON0 Module Register List
- 6.2.5. TCON0 Module Register Description
- 6.2.5.1. TCON Global Control Register (Default Value: 0x00000000)
- 6.2.5.2. TCON Global Interrupt Register0 (Default Value: 0x00000000)
- 6.2.5.3. TCON Global Interrupt Register1 (Default Value: 0x00000000)
- 6.2.5.4. TCON FRM Control Register0 (Default Value: 0x00000000)
- 6.2.5.5. TCON FRM Seed Register0 (Default Value: 0x00000000)
- 6.2.5.6. TCON FRM Table Register0 (Default Value: 0x00000000)
- 6.2.5.7. TCON 3D FIFO Register0 (Default Value: 0x00000000)
- 6.2.5.8. TCON0 Control Register (Default Value: 0x00000000)
- 6.2.5.9. TCON0 Data Clock Register (Default Value: 0x00000000)
- 6.2.5.10. TCON0 Basic0 Register (Default Value: 0x00000000)
- 6.2.5.11. TCON0 Basic1 Register (Default Value: 0x00000000)
- 6.2.5.12. TCON0 Basic2 Register (Default Value: 0x00000000)
- 6.2.5.13. TCON0 Basic3 Register (Default Value: 0x00000000)
- 6.2.5.14. TCON0 HV Panel Interface Register (Default Value: 0x00000000)
- 6.2.5.15. TCON0 CPU Panel Interface Register (Default Value: 0x00000000)
- 6.2.5.16. TCON0 CPU Panel Write Data Register (Default Value: 0x00000000)
- 6.2.5.17. TCON0 CPU Panel Read Data 0 Register (Default Value: 0x00000000)
- 6.2.5.18. TCON0 CPU Panel Read Data 1 Register (Default Value: 0x00000000)
- 6.2.5.19. TCON0 LVDS Panel Interface Register (Default Value: 0x00000000)
- 6.2.5.20. TCON0 IO Polarity Register (Default Value: 0x00000000)
- 6.2.5.21. TCON0 IO Trigger Register (Default Value: 0x00000000)
- 6.2.5.22. TCON CEU Control Register (Default Value: 0x00000000)
- 6.2.5.23. TCON CEU Coefficient Mul Register (Default Value: 0x00000000)
- 6.2.5.24. TCON CEU Coefficient Add Register (Default Value: 0x00000000)
- 6.2.5.25. TCON CEU Coefficient Range Register (Default Value: 0x00000000)
- 6.2.5.26. TCON0 CPU Panel Trigger0 Register (Default Value: 0x00000000)
- 6.2.5.27. TCON0 CPU Panel Trigger1 Register (Default Value: 0x00000000)
- 6.2.5.28. TCON0 CPU Panel Trigger2 Register (Default Value: 0x00000000)
- 6.2.5.29. TCON0 CPU Panel Trigger3 Register (Default Value: 0x00000000)
- 6.2.5.30. TCON0 CPU Panel Trigger4 Register (Default Value: 0x00000000)
- 6.2.5.31. TCON0 CPU Panel Trigger5 Register (Default Value: 0x00000000)
- 6.2.5.32. TCON Color Map Control Register (Default Value: 0x00000000)
- 6.2.5.33. TCON Color Map Odd Line0 Register (Default Value: 0x00000000)
- 6.2.5.34. TCON Color Map Odd Line1 Register (Default Value: 0x00000000)
- 6.2.5.35. TCON Color Map Even0 Register (Default Value: 0x00000000)
- 6.2.5.36. TCON Color Map Even1 Register (Default Value: 0x00000000)
- 6.2.5.37. TCON Safe Period Register (Default Value: 0x00000000)
- 6.2.5.38. TCON0 LVDS ANA0 Register (Default Value: 0x00000000)
- 6.2.6. TCON1 Module Register List
- 6.2.7. TCON1 Module Register Description
- 6.2.7.1. TCON Global Control Register (Default Value: 0x00000000)
- 6.2.7.2. TCON Global Interrupt Register0 (Default Value: 0x00000000)
- 6.2.7.3. TCON Global Interrupt Register1 (Default Value: 0x00000000)
- 6.2.7.4. TCON1 Control Register (Default Value: 0x00000000)
- 6.2.7.5. TCON1 Basic Timing 0 Register (Default Value: 0x00000000)
- 6.2.7.6. TCON1 Basic Timing 1 Register (Default Value: 0x00000000)
- 6.2.7.7. TCON1 Basic Timing 2 Register (Default Value: 0x00000000)
- 6.2.7.8. TCON1 Basic Timing 3 Register (Default Value: 0x00000000)
- 6.2.7.9. TCON1 Basic Timing Register (Default Value: 0x00000000)
- 6.2.7.10. TCON1 Basic Timing 5 Register (Default Value: 0x00000000)
- 6.2.7.11. TCON1 PS SYNC Register (Default Value: 0x00000000)
- 6.2.7.12. TCON1 IO Polarity Register (Default Value: 0x00000000)
- 6.2.7.13. TCON1 IO Polarity Register (Default Value: 0x0FFFFFFF)
- 6.2.7.14. TCON CEU Control Register (Default Value: 0x00000000)
- 6.2.7.15. TCON CEU Coefficient Mul Register (Default Value: 0x00000000)
- 6.2.7.16. TCON CEU Coefficient Add Register (Default Value: 0x00000000)
- 6.2.7.17. TCON CEU Coefficient Rang Register (Default Value: 0x00000000)
- 6.2.7.18. TCON Safe Period Register (Default Value: 0x00000000)
- 6.2.7.19. TCON1 Fill Control Register (Default Value: 0x00000000)
- 6.2.7.20. TCON1 Fill Begin Register (Default Value: 0x00000000)
- 6.2.7.21. TCON1 Fill End Register (Default Value: 0x00000000)
- 6.2.7.22. TCON1 Fill Data Register (Default Value: 0x00000000)
- Chapter 7 Interfaces
- 7.1. TWI
- 7.1.1. Overview
- 7.1.2. Timing Diagram
- 7.1.3. TWI Controller Special Requirement
- 7.1.4. TWI Controller Register List
- 7.1.5. TWI Controller Register Description
- 7.1.5.1. TWI Slave Address Register(Default Value: 0x00000000)
- 7.1.5.2. TWI Extend Address Register(Default Value: 0x00000000)
- 7.1.5.3. TWI Data Register(Default Value: 0x00000000)
- 7.1.5.4. TWI Control Register(Default Value: 0x00000000)
- 7.1.5.5. TWI Status Register(Default Value: 0x000000F8)
- 7.1.5.6. TWI Clock Register(Default Value: 0x00000000)
- 7.1.5.7. TWI Soft Reset Register(Default Value: 0x00000000)
- 7.1.5.8. TWI Enhance Feature Register(Default Value: 0x00000000)
- 7.1.5.9. TWI Line Control Register(Default Value: 0x0000003A)
- 7.1.5.10. TWI DVFS Register(Default Value: 0x00000000)
- 7.2. SPI
- 7.2.1. Overview
- 7.2.2. SPI Block Diagram
- 7.2.3. SPI Timing Diagram
- 7.2.4. SPI Pin Lists
- 7.2.5. SPI Register List
- 7.2.6. SPI Register Description
- 7.2.6.1. SPI Global Control Register(Default Value: 0x00000080)
- 7.2.6.2. SPI Transfer Control Register(Default Value: 0x00000087)
- 7.2.6.3. SPI Interrupt Control Register(Default Value: 0x00000000)
- 7.2.6.4. SPI Interrupt Status Register(Default Value: 0x00000022)
- 7.2.6.5. SPI FIFO Control Register(Default Value: 0x00400001)
- 7.2.6.6. SPI FIFO Status Register(Default Value: 0x00000000)
- 7.2.6.7. SPI Wait Clock Register(Default Value: 0x00000000)
- 7.2.6.8. SPI Clock Control Register(Default Value: 0x00000002)
- 7.2.6.9. SPI Master Burst Counter Register(Default Value: 0x00000000)
- 7.2.6.10. SPI Master Transmit Counter Register(Default Value: 0x00000000)
- 7.2.6.11. SPI Master Burst Control Counter Register(Default Value: 0x00000000)
- 7.2.6.12. SPI Normal DMA Mode Control Register(Default Value: 0x000000A5)
- 7.2.6.13. SPI TX Data Register(Default Value: 0x00000000)
- 7.2.6.14. SPI RX Data Register(Default Value: 0x00000000)
- 7.3. UART
- 7.3.1. Overview
- 7.3.2. UART Timing Diagram
- 7.3.3. UART Pin List
- 7.3.4. UART Controller Register List
- 7.3.5. UART Register Description
- 7.3.5.1. UART Receiver Buffer Register(Default Value: 0x00000000)
- 7.3.5.2. UART Transmit Holding Register(Default Value: 0x00000000)
- 7.3.5.3. UART Divisor Latch Low Register(Default Value: 0x00000000)
- 7.3.5.4. UART Divisor Latch High Register(Default Value: 0x00000000)
- 7.3.5.5. UART Interrupt Enable Register(Default Value: 0x00000000)
- 7.3.5.6. UART Interrupt Identity Register(Default Value: 0x00000000)
- 7.3.5.7. UART FIFO Control Register(Default Value: 0x00000000)
- 7.3.5.8. UART Line Control Register(Default Value: 0x00000000)
- 7.3.5.9. UART Modem Control Register(Default Value: 0x00000000)
- 7.3.5.10. UART Line Status Register(Default Value: 0x00000060)
- 7.3.5.11. UART Modem Status Register(Default Value: 0x00000000)
- 7.3.5.12. UART Scratch Register(Default Value: 0x00000000)
- 7.3.5.13. UART Status Register(Default Value: 0x00000006)
- 7.3.5.14. UART Transmit FIFO Level Register(Default Value: 0x00000000)
- 7.3.5.15. UART Receive FIFO Level Register(Default Value: 0x00000000)
- 7.3.5.16. UART Halt TX Register(Default Value: 0x00000000)
- 7.4. CIR Receiver
- 7.4.1. Overview
- 7.4.2. CIR Receiver Register List
- 7.4.3. CIR Receiver Register Description
- 7.4.3.1. CIR Receiver Control Register(Default Value: 0x00000000)
- 7.4.3.2. CIR Receiver Configure Register(Default Value: 0x00000004)
- 7.4.3.3. CIR Receiver FIFO Register(Default Value: 0x00000000)
- 7.4.3.4. CIR Receiver Interrupt Control Register(Default Value: 0x00000000)
- 7.4.3.5. CIR Receiver Status Register(Default Value: 0x00000000)
- 7.4.3.6. CIR Receiver Configure Register(Default Value: 0x00000000)
- 7.5. USB
- 7.5.1. USB Controller Block Diagram
- 7.5.2. USB OTG
- 7.5.3. USB Host
- 7.5.3.1. Overview
- 7.5.3.2. USB Host Timing Diagram
- 7.5.3.3. USB Host Register List
- 7.5.3.4. EHCI Register Description
- 7.5.3.4.1. EHCI Identification Register(Default Value: Implementation Dependent)
- 7.5.3.4.2. EHCI Host Interface Version Number Register(Default Value: 0x0100)
- 7.5.3.4.3. EHCI Host Control Structural Parameter Register(Default Value: Implementation Dependent)
- 7.5.3.4.4. EHCI Host Control Capability Parameter Register(Default Value: Implementation Dependent)
- 7.5.3.4.5. EHCI Companion Port Route Description (Default Value: UNDEFINED)
- 7.5.3.4.6. EHCI USB Command Register (Default Value: 0x00080000,0x00080B00 if Asynchronous Schedule Park Capability is a one)
- 7.5.3.4.7. EHCI USB Status Register (Default Value: 0x00001000)
- 7.5.3.4.8. EHCI USB Interrupt Enable Register (Default Value: 0x00000000)
- 7.5.3.4.9. EHCI Frame Index Register (Default Value: 0x00000000)
- 7.5.3.4.10. EHCI Periodic Frame List Base Address Register (Default Value: Undefined)
- 7.5.3.4.11. EHCI Current Asynchronous List Address Register (Default Value: Undefined)
- 7.5.3.4.12. EHCI Configure Flag Register (Default Value: 0x00000000)
- 7.5.3.4.13. EHCI Port Status and Control Register (Default Value: 0x00002000(w/PPC set to one);0x00003000(w/PPC set to a zero))
- 7.5.3.5. OHCI Register Description
- 7.5.3.5.1. HcRevision Register(Default Value: 0x00000010)
- 7.5.3.5.2. HcControl Register(Default Value: 0x00000000)
- 7.5.3.5.3. HcCommandStatus Register(Default Value: 0x00000000)
- 7.5.3.5.4. HcInterruptStatus Register(Default Value: 0x00000000)
- 7.5.3.5.5. HcInterruptEnable Register(Default Value: 0x00000000)
- 7.5.3.5.6. HcInterruptDisable Register(Default Value: 0x00000000)
- 7.5.3.5.7. HcHCCA Register(Default Value: 0x00000000)
- 7.5.3.5.8. HcPeriodCurrentED Register(Default Value: 0x00000000)
- 7.5.3.5.9. HcControlHeadED Register(Default Value: 0x00000000)
- 7.5.3.5.10. HcControlCurrentED Register(Default Value: 0x00000000)
- 7.5.3.5.11. HcBulkHeadED Register(Default Value: 0x00000000)
- 7.5.3.5.12. HcBulkCurrentED Register(Default Value: 0x00000000)
- 7.5.3.5.13. HcDoneHead Register(Default Value: 0x00000000)
- 7.5.3.5.14. HcFmInterval Register(Default Value: 0x00002EDF)
- 7.5.3.5.15. HcFmRemaining Register(Default Value: 0x00000000)
- 7.5.3.5.16. HcFmNumber Register(Default Value: 0x00000000)
- 7.5.3.5.17. HcPeriodicStart Register(Default Value: 0x00000000)
- 7.5.3.5.18. HcLSThreshold Register(Default Value: 0x00000628)
- 7.5.3.5.19. HcRhDescriptorA Register(Default Value: 0x02001201)
- 7.5.3.5.20. HcRhDescriptorB Register(Default Value: 0x00000000)
- 7.5.3.5.21. HcRhStatus Register(Default Value: 0x00000000)
- 7.5.3.5.22. HcRhPortStatus Register(Default Value: 0x00000100)
- 7.5.3.6. HCI Interface Control and Status Register Description
- 7.5.3.7. USB Host Clock Requirement
- 7.6. I2S/PCM
- 7.6.1. Overview
- 7.6.2. Signal Description
- 7.6.3. Functionalities Description
- 7.6.4. Timing Diagram
- 7.6.5. Operation Modes
- 7.6.6. I2S/PCM Register List
- 7.6.7. I2S/PCM Register Description
- 7.6.7.1. I2S/PCM Control Register(Default Value: 0x00060000)
- 7.6.7.2. I2S/PCM Format Register0 (Default Value: 0x00000033)
- 7.6.7.3. I2S/PCM Format Register1 (Default Value: 0x00000030)
- 7.6.7.4. I2S/PCM Interrupt Status Register(Default Value: 0x00000010)
- 7.6.7.5. I2S/PCM RX FIFO Register(Default Value: 0x00000000)
- 7.6.7.6. I2S/PCM FIFO Control Register (Default Value: 0x000400F0)
- 7.6.7.7. I2S/PCM FIFO Status Register (Default Value: 0x10800000)
- 7.6.7.8. I2S/PCM DMA & Interrupt Control Register(Default Value: 0x00000000)
- 7.6.7.9. I2S/PCM TX FIFO Register(Default Value: 0x00000000)
- 7.6.7.10. I2S/PCM Clock Divide Register(Default Value: 0x00000000)
- 7.6.7.11. I2S/PCM TX Counter Register(Default Value: 0x00000000)
- 7.6.7.12. I2S/PCM RX Counter Register(Default Value: 0x00000000)
- 7.6.7.13. I2S/PCM Channel Configuration Register(Default Value: 0x00000000)
- 7.6.7.14. I2S/PCM TXn Channel Select Register(Default Value: 0x00000000)
- 7.6.7.15. I2S/PCM TXn Channel Mapping Register(Default Value: 0x00000000)
- 7.6.7.16. I2S/PCM RX Channel Select Register(Default Value: 0x00000000)
- 7.6.7.17. I2S/PCM RX Channel Mapping Register(Default Value: 0x00000000)
- 7.7. OWA
- 7.7.1. Overview
- 7.7.2. Functional Description
- 7.7.3. OWA Register List
- 7.7.4. OWA Register Description
- 7.7.4.1. OWA General Control Register(Default Value : 0x00000080)
- 7.7.4.2. OWA TX Configure Register(Default Value: 0x000000F0)
- 7.7.4.3. OWA RX Configure Register(Default Value: 0x00000000)
- 7.7.4.4. OWA Interrupt Status Register(Default Value: 0x00000010)
- 7.7.4.5. OWA RX FIFO Register(Default Value: 0x00000000)
- 7.7.4.6. OWA FIFO Control Register(Default Value: 0x00001078)
- 7.7.4.7. OWA FIFO Status Register(Default Value: 0x00006000)
- 7.7.4.8. OWA Interrupt Control Register(Default Value: 0x00000000)
- 7.7.4.9. OWA TX FIFO Register(Default Value: 0x00000000)
- 7.7.4.10. OWA TX Counter Register(Default Value: 0x00000000)
- 7.7.4.11. OWA RX Counter Register(Default Value: 0x00000000)
- 7.7.4.12. OWA TX Channel Status Register0(Default Value: 0x00000000)
- 7.7.4.13. OWA TX Channel Status Register1(Default Value: 0x00000000)
- 7.7.4.14. OWA RX Channel Status Register0(Default Value: 0x00000000)
- 7.7.4.15. OWA RX Channel Status Register1(Default Value: 0x00000000)
- 7.8. SCR
- 7.8.1. Overview
- 7.8.2. Block Diagram
- 7.8.3. SCR Timing Diagram
- 7.8.4. SCR Special Requirement
- 7.8.5. SCR Register List
- 7.8.6. SCR Register Description
- 7.8.6.1. Smart Card Reader Control and Status Register(Default Value: 0x00000000)
- 7.8.6.2. Smart Card Reader Interrupt Enable Register(Default Value: 0x00000000)
- 7.8.6.3. Smart Card Reader Interrupt Status Register(Default Value: 0x00000000)
- 7.8.6.4. Smart Card Reader FIFO Control and Status Register(Default Value: 0x00000000)
- 7.8.6.5. Smart Card Reader FIFO Counter Register(Default Value: 0x00000000)
- 7.8.6.6. Smart Card Reader Repeat Control Register(Default Value: 0x00000000)
- 7.8.6.7. Smart Card Reader Clock Divisor Register(Default Value: 0x00000000)
- 7.8.6.8. Smart Card Reader Line Time Register(Default Value: 0x00000000)
- 7.8.6.9. Smart Card Reader Character Time Register(Default Value: 0x00000000)
- 7.8.6.10. Smart Card Reader Line Control Register(Default Value: 0x00000000)
- 7.8.6.11. Smart Card Reader FIFO Data Register(Default Value: 0x00000000)
- 7.9. EMAC
- 7.9.1. Overview
- 7.9.2. Block Diagram
- 7.9.3. EMAC Core Register List
- 7.9.4. EMAC Core Register Description
- 7.9.4.1. Basic Control 0 Register(Default Value: 0x00000000)
- 7.9.4.2. Basic Control 1 Register(Default Value: 0x08000000)
- 7.9.4.3. Interrupt Status Register(Default Value: 0x00000000)
- 7.9.4.4. Interrupt Enable Register(Default Value: 0x00000000)
- 7.9.4.5. Transmit Control 0 Register(Default Value: 0x00000000)
- 7.9.4.6. Transmit Control 1 Register(Default Value: 0x00000000)
- 7.9.4.7. Transmit Flow Control Register(Default Value: 0x00000000)
- 7.9.4.8. Transmit DMA Descriptor List Address Register(Default Value: 0x00000000)
- 7.9.4.9. Receive Control 0 Register(Default Value: 0x00000000)
- 7.9.4.10. Receive Control 1 Register(Default Value: 0x00000000)
- 7.9.4.11. Receive DMA Descriptor List Address Register(Default Value: 0x00000000)
- 7.9.4.12. Receive Frame Filter Register(Default Value: 0x00000000)
- 7.9.4.13. Receive Hash Table 0 Register(Default Value: 0x00000000)
- 7.9.4.14. Receive Hash Table 1 Register(Default Value: 0x00000000)
- 7.9.4.15. MII Command Register(Default Value: 0x00000000)
- 7.9.4.16. MII Data Register(Default Value: 0x00000000)
- 7.9.4.17. MAC Address 0 High Register(Default Value: 0x0000FFFF)
- 7.9.4.18. MAC Address 0 Low Register(Default Value: 0xFFFFFFFF)
- 7.9.4.19. MAC Address x High Register(Default Value: 0x0000FFFF)
- 7.9.4.20. MAC Address x Low Register(Default Value: 0xFFFFFFFF)
- 7.9.4.21. Transmit DMA Status Register(Default Value: 0x00000000)
- 7.9.4.22. Transmit DMA Current Descriptor Register(Default Value: 0x00000000)
- 7.9.4.23. Transmit DMA Current Buffer Address Register(Default Value: 0x00000000)
- 7.9.4.24. Receive DMA Status Register(Default Value: 0x00000000)
- 7.9.4.25. Receive DMA Current Descriptor Register(Default Value: 0x00000000)
- 7.9.4.26. Receive DMA Current Buffer Address Register(Default Value: 0x00000000)
- 7.9.4.27. RGMII Status Register(Default Value: 0x00000000)
- 7.9.5. EMAC RX/TX Descriptor
- 7.10. TSC
- 7.10.1. Overview
- 7.10.2. Transport Stream Input Timing Diagram
- 7.10.3. Transport Stream Controller Register List
- 7.10.4. Transport Stream Controller Register Description
- 7.10.4.1. TSC Control Register(Default Value: 0x00000000)
- 7.10.4.2. TSC Status Register(Default Value: 0x00000000)
- 7.10.4.3. TSC Port Control Register(Default Value: 0x00000000)
- 7.10.4.4. TSC Port Parameter Register(Default Value: 0x00000000)
- 7.10.4.5. TSC TSF Input Multiplex Control Register(Default Value: 0x00000000)
- 7.10.4.6. TSC Port Output Multiplex Control Register(Default Value: 0x00000000)
- 7.10.4.7. TSC Port Output Multiplex Control Register(Default Value: 0x00000000)
- 7.10.4.8. TSG Packet Parameter Register(Default Value: 0x00470000)
- 7.10.4.9. TSG Interrupt Enable and Status Register(Default Value: 0x00000000)
- 7.10.4.10. TSG Clock Control Register(Default Value: 0x00000000)
- 7.10.4.11. TSG Buffer Base Address Register(Default Value: 0x00000000)
- 7.10.4.12. TSG Buffer Size Register(Default Value: 0x00000000)
- 7.10.4.13. TSG Buffer Point Register(Default Value: 0x00000000)
- 7.10.4.14. TSF Control and Status Register(Default Value: 0x00000000)
- 7.10.4.15. TSF Packet Parameter Register(Default Value: 0x00470000)
- 7.10.4.16. TSF Interrupt Enable and Status Register(Default Value: 0x00000000)
- 7.10.4.17. TSF DMA Interrupt Enable Register(Default Value: 0x00000000)
- 7.10.4.18. TSF Overlap Interrupt Enable Register(Default Value: 0x00000000)
- 7.10.4.19. TSF DMA Interrupt Status Register(Default Value: 0x00000000)
- 7.10.4.20. TSF Overlap Interrupt Status Register(Default Value: 0x00000000)
- 7.10.4.21. TSF PCR Control Register(Default Value: 0x00000000)
- 7.10.4.22. TSF PCR Data Register(Default Value: 0x00000000)
- 7.10.4.23. TSF Channel Enable Register(Default Value: 0x00000000)
- 7.10.4.24. TSF PES Enable Register(Default Value: 0x00000000)
- 7.10.4.25. TSF Channel Descramble Enable Register(Default Value: 0x00000000)
- 7.10.4.26. TSF Channel Index Register(Default Value: 0x00000000)
- 7.10.4.27. TSF Channel Control Register(Default Value: 0x00000000)
- 7.10.4.28. TSF Channel Status Register(Default Value: 0x00000000)
- 7.10.4.29. TSF Channel CW Index Register(Default Value: 0x00000000)
- 7.10.4.30. TSF Channel PID Register(Default Value: 0x1FFF0000)
- 7.10.4.31. TSF Channel Buffer Base Address Register(Default Value: 0x00000000)
- 7.10.4.32. TSF Channel Buffer Size Register(Default Value: 0x00000000)
- 7.10.4.33. TSF Channel Write Pointer Register(Default Value: 0x00000000)
- 7.10.4.34. TSF Channel Read Pointer Register(Default Value: 0x00000000)
- 7.10.4.35. TSD Control Register(Default Value: 0x00000000)
- 7.10.4.36. TSD Status Register(Default Value: 0x00000000)
- 7.10.4.37. TSD Control Word Index Register(Default Value: 0x00000000)
- 7.10.4.38. TSD Control Word Register(Default Value: 0x00000000)
- 7.1. TWI
- Appendix