Allwinner H5 Manual V1.0

User Manual:

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Declaration
Revision History
Table of Contents
Figures
Tables
Chapter 1 About This Documentation
- 1.1. Purpose
- 1.2. Acronyms and Abbreviations
Chapter 2 Overview
- 2.1. Processor Overview
- 2.2. Processor Features
- 2.3. System Block Diagram
Chapter 3 Pin Description
- 3.1. Pin Characteristics
- 3.2. Signal Descriptions
Chapter 4 System
- 4.1. Memory Mapping
- 4.2. Boot System
  - 4.2.1. Overview
  - 4.2.2. Boot Diagram
- 4.3. CCU
  - 4.3.1. Overview
  - 4.3.2. Operations and Functional Descriptions
  - 4.3.3. Register List
  - 4.3.4. Register Description
- 4.4. CPU Configuration
  - 4.4.1. Overview
  - 4.4.2. Block Diagram
  - 4.4.3. Operations and Functional Descriptions
  - 4.4.4. Register List
  - 4.4.5. Register Description
- 4.5. System Control
  - 4.5.1. Overview
  - 4.5.2. Register List
  - 4.5.3. Register Description
    - 4.5.3.1. Version Register (Default Value: UDF)
    - 4.5.3.2. EMAC-EPHY Clock Register (Default Value: 0x0005_8000)
- 4.6. Timer
  - 4.6.1. Overview
  - 4.6.2. Block Diagram
  - 4.6.3. Operations and Functional Descriptions
  - 4.6.4. Register List
  - 4.6.5. Register Description
- 4.7. Trusted Watchdog
  - 4.7.1. Overview
  - 4.7.2. Block Diagram
  - 4.7.3. Operations and Functional Descriptions
    - 4.7.3.1. TWD Reset
    - 4.7.3.2. NV-Counter
  - 4.7.4. Register List
  - 4.7.5. Register Description
- 4.8. RTC
  - 4.8.1. Overview
  - 4.8.2. Register List
  - 4.8.3. Register Description
- 4.9. High Speed Timer
  - 4.9.1. Overview
  - 4.9.2. Operations and Functional Descriptions
  - 4.9.3. Programming Guidelines
  - 4.9.4. Register List
  - 4.9.5. Register Description
- 4.10. PWM
  - 4.10.1. Overview
  - 4.10.2. Block Diagram
  - 4.10.3. Register List
  - 4.10.4. Register Description
    - 4.10.4.1. PWM Control Register(Default Value: 0x0000_0000)
    - 4.10.4.2. PWM Channel Period Register (Default Value: UDF)
- 4.11. DMA
  - 4.11.1. Overview
  - 4.11.2. Block Diagram
  - 4.11.3. Functionalities Description
    - 4.11.3.1. DRQ Type and Corresponding Relation
    - 4.11.3.2. DMA Descriptor
  - 4.11.4. Register List
  - 4.11.5. Register Description
- 4.12. GIC
  - 4.12.1. Interrupt Source
- 4.13. Message Box
  - 4.13.1. Overview
  - 4.13.2. Block Diagram
  - 4.13.3. Operations and Functional Descriptions
  - 4.13.4. Register List
  - 4.13.5. Register Description
- 4.14. Spinlock
  - 4.14.1. Overview
  - 4.14.2. Operations and Functional Descriptions
  - 4.14.3. Programming Guidelines
  - 4.14.4. Register List
  - 4.14.5. Register Description
- 4.15. Crypto Engine
  - 4.15.1. Overview
  - 4.15.2. Block Diagram
  - 4.15.3. Operations and Functional Descriptions
  - 4.15.4. Register List
  - 4.15.5. Register Description
- 4.16. Security ID
  - 4.16.1. Overview
- 4.17. Secure Memory Controller
  - 4.17.1. Overview
  - 4.17.2. Operations and Functional Descriptions
  - 4.17.3. Register List
  - 4.17.4. Register Description
- 4.18. Secure Peripherals Controller
  - 4.18.1. Overview
  - 4.18.2. Operations and Functional Descriptions
    - 4.18.2.1. Typical Applications
    - 4.18.2.2. SPC Configuration Table
  - 4.18.3. Register List
  - 4.18.4. Register Description
- 4.19. Thermal Sensor Controller
  - 4.19.1. Overview
  - 4.19.2. Block Diagram
  - 4.19.3. Clock and Timing Requirements
  - 4.19.4. Programming Guidelines
  - 4.19.5. Register List
  - 4.19.6. Register Description
- 4.20. KEYADC
  - 4.20.1. Overview
  - 4.20.2. Block Diagram
  - 4.20.3. Operations and Functional Descriptions
  - 4.20.4. Programming Guidelines
  - 4.20.5. Register List
  - 4.20.6. Register Description
- 4.21. Port Controller(CPUx-PORT)
  - 4.21.1. Overview
  - 4.21.2. Register List
  - 4.21.3. Register Description
- 4.22. Port Controller (CPUs-PORT)
  - 4.22.1. Overview
  - 4.22.2. Register List
  - 4.22.3. Register Description
Chapter 5 Memory
- 5.1. SDRAM Controller(DRAMC)
  - 5.1.1. Overview
- 5.2. NAND Flash Controller(NDFC)
- 5.3. SD/MMC Host Controller(SMHC)
Chapter 6 Image
- 6.1. CSI
Chapter 7 Display
- 7.1. DE2.0
  - 7.1.1. Overview
- 7.2. TCON
Chapter 8 Audio
- 8.1. Audio Codec
- 8.2. I2S/PCM
- 8.3. OWA
Chapter 9 Interfaces
- 9.1. TWI
- 9.2. SPI
- 9.3. UART
- 9.4. CIR Receiver
- 9.5. USB
  - 9.5.1. USB OTG Controller
    - 9.5.1.1. Overview
    - 9.5.1.2. Block Diagram
  - 9.5.2. USB Host Controller
- 9.6. SCR
- 9.7. EMAC
- 9.8. TSC
Chapter 10 Electrical Characteristics
- 10.1. Absolute Maximum Ratings
- 10.2. Recommended Operating Conditions
- 10.3. DC Electrical Characteristics
- 10.4. ADC Electrical Characteristics
- 10.5. Oscillator Electrical Characteristics
- 10.6. Maximum Current Consumption
- 10.7. External Memory AC Electrical Characteristics
  - 10.7.1. Nand Flash AC Electrical Characteristics
  - 10.7.2. SMHC AC Electrical Characteristics
- 10.8. External Peripheral AC Electrical Characteristics
- 10.9. Power-up and Power-down Sequence
- 10.10. Package Thermal Characteristics
Appendix
- Pin Map
- Package Dimension
Declaration
Revision History
Table of Contents
Figures
Tables
Chapter 1 About This Documentation
- 1.1. Purpose
- 1.2. Acronyms and Abbreviations
Chapter 2 Overview
- 2.1. Processor Overview
- 2.2. Processor Features
- 2.3. System Block Diagram
Chapter 3 Pin Description
- 3.1. Pin Characteristics
- 3.2. Signal Descriptions
Chapter 4 System
- 4.1. Memory Mapping
- 4.2. Boot System
  - 4.2.1. Overview
  - 4.2.2. Boot Diagram
- 4.3. CCU
  - 4.3.1. Overview
  - 4.3.2. Operations and Functional Descriptions
  - 4.3.3. Register List
  - 4.3.4. Register Description
- 4.4. CPU Configuration
  - 4.4.1. Overview
  - 4.4.2. Block Diagram
  - 4.4.3. Operations and Functional Descriptions
  - 4.4.4. Register List
  - 4.4.5. Register Description
- 4.5. System Control
  - 4.5.1. Overview
  - 4.5.2. Register List
  - 4.5.3. Register Description
    - 4.5.3.1. Version Register (Default Value: UDF)
    - 4.5.3.2. EMAC-EPHY Clock Register (Default Value: 0x0005_8000)
- 4.6. Timer
  - 4.6.1. Overview
  - 4.6.2. Block Diagram
  - 4.6.3. Operations and Functional Descriptions
  - 4.6.4. Register List
  - 4.6.5. Register Description
- 4.7. Trusted Watchdog
  - 4.7.1. Overview
  - 4.7.2. Block Diagram
  - 4.7.3. Operations and Functional Descriptions
    - 4.7.3.1. TWD Reset
    - 4.7.3.2. NV-Counter
  - 4.7.4. Register List
  - 4.7.5. Register Description
- 4.8. RTC
  - 4.8.1. Overview
  - 4.8.2. Register List
  - 4.8.3. Register Description
- 4.9. High Speed Timer
  - 4.9.1. Overview
  - 4.9.2. Operations and Functional Descriptions
  - 4.9.3. Programming Guidelines
  - 4.9.4. Register List
  - 4.9.5. Register Description
- 4.10. PWM
  - 4.10.1. Overview
  - 4.10.2. Block Diagram
  - 4.10.3. Register List
  - 4.10.4. Register Description
    - 4.10.4.1. PWM Control Register(Default Value: 0x0000_0000)
    - 4.10.4.2. PWM Channel Period Register (Default Value: UDF)
- 4.11. DMA
  - 4.11.1. Overview
  - 4.11.2. Block Diagram
  - 4.11.3. Functionalities Description
    - 4.11.3.1. DRQ Type and Corresponding Relation
    - 4.11.3.2. DMA Descriptor
  - 4.11.4. Register List
  - 4.11.5. Register Description
- 4.12. GIC
  - 4.12.1. Interrupt Source
- 4.13. Message Box
  - 4.13.1. Overview
  - 4.13.2. Block Diagram
  - 4.13.3. Operations and Functional Descriptions
  - 4.13.4. Register List
  - 4.13.5. Register Description
- 4.14. Spinlock
  - 4.14.1. Overview
  - 4.14.2. Operations and Functional Descriptions
  - 4.14.3. Programming Guidelines
  - 4.14.4. Register List
  - 4.14.5. Register Description
- 4.15. Crypto Engine
  - 4.15.1. Overview
  - 4.15.2. Block Diagram
  - 4.15.3. Operations and Functional Descriptions
  - 4.15.4. Register List
  - 4.15.5. Register Description
- 4.16. Security ID
  - 4.16.1. Overview
- 4.17. Secure Memory Controller
  - 4.17.1. Overview
  - 4.17.2. Operations and Functional Descriptions
  - 4.17.3. Register List
  - 4.17.4. Register Description
- 4.18. Secure Peripherals Controller
  - 4.18.1. Overview
  - 4.18.2. Operations and Functional Descriptions
    - 4.18.2.1. Typical Applications
    - 4.18.2.2. SPC Configuration Table
  - 4.18.3. Register List
  - 4.18.4. Register Description
- 4.19. Thermal Sensor Controller
  - 4.19.1. Overview
  - 4.19.2. Block Diagram
  - 4.19.3. Clock and Timing Requirements
  - 4.19.4. Programming Guidelines
  - 4.19.5. Register List
  - 4.19.6. Register Description
- 4.20. KEYADC
  - 4.20.1. Overview
  - 4.20.2. Block Diagram
  - 4.20.3. Operations and Functional Descriptions
  - 4.20.4. Programming Guidelines
  - 4.20.5. Register List
  - 4.20.6. Register Description
- 4.21. Port Controller(CPUx-PORT)
  - 4.21.1. Overview
  - 4.21.2. Register List
  - 4.21.3. Register Description
- 4.22. Port Controller (CPUs-PORT)
  - 4.22.1. Overview
  - 4.22.2. Register List
  - 4.22.3. Register Description
Chapter 5 Memory
- 5.1. SDRAM Controller(DRAMC)
  - 5.1.1. Overview
- 5.2. NAND Flash Controller(NDFC)
- 5.3. SD/MMC Host Controller(SMHC)
Chapter 6 Image
- 6.1. CSI
Chapter 7 Display
- 7.1. DE2.0
  - 7.1.1. Overview
- 7.2. TCON
Chapter 8 Audio
- 8.1. Audio Codec
- 8.2. I2S/PCM
- 8.3. OWA
Chapter 9 Interfaces
- 9.1. TWI
- 9.2. SPI
- 9.3. UART
- 9.4. CIR Receiver
- 9.5. USB
  - 9.5.1. USB OTG Controller
    - 9.5.1.1. Overview
    - 9.5.1.2. Block Diagram
  - 9.5.2. USB Host Controller
- 9.6. SCR
- 9.7. EMAC
- 9.8. TSC
Chapter 10 Electrical Characteristics
- 10.1. Absolute Maximum Ratings
- 10.2. Recommended Operating Conditions
- 10.3. DC Electrical Characteristics
- 10.4. ADC Electrical Characteristics
- 10.5. Oscillator Electrical Characteristics
- 10.6. Maximum Current Consumption
- 10.7. External Memory AC Electrical Characteristics
  - 10.7.1. Nand Flash AC Electrical Characteristics
  - 10.7.2. SMHC AC Electrical Characteristics
- 10.8. External Peripheral AC Electrical Characteristics
- 10.9. Power-up and Power-down Sequence
- 10.10. Package Thermal Characteristics
Appendix
- Pin Map
- Package Dimension

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