Annexe2 Instructions MIPS
Annexe2-InstructionsMIPS
Annexe2-InstructionsMIPS
Annexe2-InstructionsMIPS
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rs 21 20 rt 16 15 rd 11 10 0 6 5 ADD 34 36 Operation: Programming Notes: ADDIU performs the same arithmetic operation but does not trap on overflow. Programming Notes: ADDU performs the same arithmetic operation but does not trap on overflow. Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 Integer Overflow Integer Overflow MIPS32® Architecture For Programmers Volume II, Revision 2.50 Exceptions: Exceptions: temp ← (GPR[rs]31||GPR[rs]31..0) + sign_extend(immediate) if temp32 ≠ temp31 then SignalException(IntegerOverflow) else GPR[rt] ← temp endif None Operation: temp ← (GPR[rs]31||GPR[rs]31..0) + (GPR[rt]31||GPR[rt]31..0) if temp32 ≠ temp31 then SignalException(IntegerOverflow) else GPR[rd] ← temp endif Restrictions: None • If the addition does not overflow, the 32-bit result is placed into GPR rt. • If the addition does not overflow, the 32-bit result is placed into GPR rd. Restrictions: • If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs. The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit result. MIPS32 0 ADDI • If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs. Description: GPR[rt] ¨ GPR[rs] + immediate 16 immediate The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a 32-bit result. 5 rt 16 15 Description: GPR[rd] ← GPR[rs] + GPR[rt] ADDI rt, rs, immediate 5 rs 21 20 To add a constant to a 32-bit integer. If overflow occurs, then trap. Format: 26 25 Purpose: MIPS32 6 001000 ADDI To add 32-bit integers. If an overflow occurs, then trap. ADD rd, rs, rt 6 31 Add Immediate Word ADDI Purpose: Format: 5 5 5 6 5 00000 000000 100000 0 26 25 31 SPECIAL ADD Add Word ADD 42 31 And AND 16 offset MIPS32 0 None Exceptions: MIPS32® Architecture For Programmers Volume II, Revision 2.50 Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. GPR[rd] ← GPR[rs] and GPR[rt] Operation: None target_offset ← sign_extend(offset || 02) condition ← (GPR[rs] = GPR[rt]) if condition then PC ← PC + target_offset endif Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 BEQ r0, r0 offset, expressed as B offset, is the assembly idiom used to denote an unconditional branch. With the 18-bit signed instruction offset, the conditional branch range is ± 128 Kbytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. Programming Notes: None Exceptions: I+1: I: Operation: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Restrictions: If the contents of GPR rs and GPR rt are equal, branch to the effective target address after the instruction in the delay slot is executed. 5 rt 16 15 Restrictions: 60 5 rs 21 20 BEQ rs, rt, offset 26 25 An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Format: 6 000100 BEQ Description: if GPR[rs] = GPR[rt] then branch 31 The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical AND operation. The result is placed into GPR rd. MIPS32 0 Description: GPR[rd] ← GPR[rs] AND GPR[rt] 6 100100 AND To compare GPRs then do a PC-relative conditional branch 5 Purpose: 6 BEQ To do a bitwise logical AND AND rd, rs, rt 5 0 Branch on Equal BEQ Purpose: Format: 5 rd 11 10 5 5 rt 16 15 6 rs 21 20 00000 26 25 000000 SPECIAL AND Programming Notes: With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 None Programming Notes: 69 Exceptions: None I+1: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] ≤ 0GPRLEN if condition then PC ← PC + target_offset endif Exceptions: I+1: I: Operation: Operation: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] > 0GPRLEN if condition then PC ← PC + target_offset endif Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. I: Restrictions: Restrictions: MIPS32 If the contents of GPR rs are less than or equal to zero (sign bit is 1 or value is zero), branch to the effective target address after the instruction in the delay slot is executed. 16 offset 0 If the contents of GPR rs are greater than zero (sign bit is 0 but value not zero), branch to the effective target address after the instruction in the delay slot is executed. 16 15 An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. 5 00000 0 Description: if GPR[rs] ≤ 0 then branch 21 20 An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. 72 5 rs BLEZ rs, offset 26 25 Description: if GPR[rs] > 0 then branch Format: 6 000110 BLEZ To test a GPR then do a PC-relative conditional branch MIPS32 31 BLEZ Purpose: 16 offset 0 Branch on Less Than or Equal to Zero BLEZ To test a GPR then do a PC-relative conditional branch BGTZ rs, offset 16 15 BGTZ Purpose: Format: 5 5 0 6 rs 21 20 00000 26 25 000111 BGTZ MIPS32® Architecture For Programmers Volume II, Revision 2.50 31 Branch on Greater Than Zero BGTZ MIPS32 122 SPECIAL target_offset ← sign_extend(offset || 02) condition ← (GPR[rs] ≠ GPR[rt]) if condition then PC ← PC + target_offset endif Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. 81 With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. Programming Notes: None Exceptions: I+1: I: Operation: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Restrictions: ← ← ← ← None Exceptions: q LO r HI Operation: MIPS32® Architecture For Programmers Volume II, Revision 2.50 Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. GPR[rs]31..0 div GPR[rt]31..0 q GPR[rs]31..0 mod GPR[rt]31..0 r If the divisor in GPR rt is zero, the arithmetic result value is UNPREDICTABLE. Restrictions: No arithmetic exception occurs under any circumstances. MIPS32 0 If the contents of GPR rs and GPR rt are not equal, branch to the effective target address after the instruction in the delay slot is executed. 6 011010 DIV The 32-bit word value in GPR rs is divided by the 32-bit value in GPR rt, treating both operands as signed values. The 32-bit quotient is placed into special register LO and the 32-bit remainder isplaced into special register HI. 5 Description: (HI, LO) ← GPR[rs] / GPR[rt] 6 An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. 10 00 0000 0000 0 Description: if GPR[rs] ≠ GPR[rt] then branch 5 rt 16 15 To divide a 32-bit signed integers DIV rs, rt 5 rs 21 20 Purpose: Format: 26 25 To compare GPRs then do a PC-relative conditional branch BNE rs, rt, offset 16 31 DIV Purpose: Format: 5 offset 0 6 5 rt 16 15 Divide Word 6 rs 21 20 DIV 000000 26 25 BNE 000101 BNE MIPS32® Architecture For Programmers Volume II, Revision 2.50 31 Branch on Not Equal BNE DIV Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 123 In MIPS 1 through MIPS III, if either of the two instructions preceding the divide is an MFHI or MFLO, the result of the MFHI or MFLO is UNPREDICTABLE. Reads of the HI or LO special register must be separated from subsequent instructions that write to them by two or more instructions. This restriction was removed in MIPS IV and MIPS32 and all subsequent levels of the architecture. Historical Perspective: In some processors the integer divide operation may proceed asynchronously and allow other CPU instructions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an opportunity for performance improvement by scheduling the divide so that other instructions can execute in parallel. As an example, the C programming language in a UNIX® environment expects division by zero to either terminate the program or execute a program-specified signal handler. C does not expect overflow to cause any exceptional condition. If the C compiler uses a divide instruction, it also emits code to test for a zero divisor and execute a BREAK instruction to inform the operating system if a zero is detected. No arithmetic exception occurs under any circumstances. If divide-by-zero or overflow conditions are detected and some action taken, then the divide instruction is typically followed by additional instructions to check for a zero divisor and/or for overflow. If the divide is asynchronous then the zero-divisor check can execute in parallel with the divide. The action taken on either divide-by-zero or overflow is either a convention within the program itself, or more typically within the system software; one possibility is to take a BREAK exception with a code field value to signal the problem to the system software. Programming Notes: Divide Word (cont.) 31 Jump 138 J J target 26 25 26 instr_index MIPS32 0 Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 This definition creates the following boundary case: When the jump instruction is in the last word of a 256 MB region, it can branch only to the following 256 MB region containing the branch delay slot. Forming the branch target address by catenating PC and index bits rather than adding a signed offset to the PC is an advantage if all program code addresses fit into a 256 MB region aligned on a 256 MB boundary. It allows a branch from anywhere in the region to anywhere in the region, an action not allowed by a signed relative offset. Programming Notes: None Exceptions: I: I+1:PC ← PCGPRLEN-1..28 || instr_index || 02 Operation: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Restrictions: Jump to the effective target address. Execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself. This is a PC-region branch (not PC-relative); the effective target address is in the “current” 256 MB-aligned region. The low 28 bits of the target address is the instr_index field shifted left 2 bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself). Description: To branch within the current 256 MB-aligned region Purpose: Format: 6 000010 J J 31 MIPS32 SPECIAL Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. 139 This definition creates the following boundary case: When the branch instruction is in the last word of a 256 MB region, it can branch only to the following 256 MB region containing the branch delay slot. Forming the branch target address by catenating PC and index bits rather than adding a signed offset to the PC is an advantage if all program code addresses fit into a 256 MB region aligned on a 256 MB boundary. It allows a branch from anywhere in the region to anywhere in the region, an action not allowed by a signed relative offset. Programming Notes: None Exceptions: I: GPR[31]← PC + 8 I+1:PC ← PCGPRLEN-1..28 || instr_index || 02 Operation: Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. Restrictions: Jump to the effective target address. Execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself. Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 None Exceptions: I: temp ← GPR[rs] I+1:if Config1CA = 0 then PC ← temp else PC ← tempGPRLEN-1..1 || 0 ISAMode ← temp0 endif Operation: 145 Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. In release 1 of the architecture, the only defined hint field value is 0, which sets default handling of JR. In Release 2 of the architecture, bit 10 of the hint field is used to encode an instruction hazard barrier. See the JR.HB instruction description for additional information. The effective target address in GPR rs must be naturally-aligned. For processors that do not implement the MIPS16e ASE, if either of the two least-significant bits are not zero, an Address Error exception occurs when the branch target is subsequently fetched as an instruction. For processors that do implement the MIPS16e ASE, if bit 0 is zero and bit 1 is one, an Address Error exception occurs when the jump target is subsequently fetched as an instruction. Restrictions: For processors that implement the MIPS16e ASE, set the ISA Mode bit to the value in GPR rs bit 0. Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one This is a PC-region branch (not PC-relative); the effective target address is in the “current” 256 MB-aligned region. The low 28 bits of the target address is the instr_index field shifted left 2 bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself). MIPS32 0 Jump to the effective target address in GPR rs. Execute the instruction following the jump, in the branch delay slot, before jumping. 6 001000 JR Description: PC ← GPR[rs] 5 Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, at which location execution continues after a procedure call. 5 hint 6 Description: 11 10 To execute a branch to an instruction address in a register 10 00 0000 0000 0 Purpose: JR rs 5 rs 21 20 To execute a procedure call within the current 256 MB-aligned region Format: 26 25 JR Purpose: Format: 6 26 31 Jump Register 6 instr_index 0 JR 000000 JAL target 26 25 JAL 000011 JAL Jump and Link MIPS32® Architecture For Programmers Volume II, Revision 2.50 JAL 146 JR Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 Software should use the value 31 for the rs field of the instruction word on return from a JAL, JALR, or BGEZAL, and should use a value other than 31 for remaining uses of JR. Programming Notes: Jump Register, cont. 31 5 6 5 rt 16 15 16 immediate MIPS32 0 LUI None Exceptions: GPR[rt] ← immediate || 016 Operation: None Restrictions: Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. 159 The 16-bit immediate is shifted left 16 bits and concatenated with 16 bits of low-order zeros. The 32-bit result is placed into GPR rt. Description: GPR[rt] ← immediate || 016 To load a constant into the upper half of a word Purpose: 21 20 LUI rt, immediate 00000 001111 Format: 0 LUI 26 25 Load Upper Immediate MIPS32® Architecture For Programmers Volume II, Revision 2.50 LUI 31 MIPS32 31 SPECIAL TLB Refill, TLB Invalid, Bus Error, Address Error, Watch Exceptions: vAddr ← sign_extend(offset) + GPR[base] if vAddr1..0 ≠ 02 then SignalException(AddressError) endif (pAddr, CCA)← AddressTranslation (vAddr, DATA, LOAD) memword← LoadMemory (CCA, WORD, pAddr, vAddr, DATA) GPR[rt]← memword Operation: Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. 161 The effective address must be naturally-aligned. If either of the 2 least-significant bits of the address is non-zero, an Address Error exception occurs. Restrictions: The contents of special register HI are loaded into GPR rd. The contents of the 32-bit word at the memory location specified by the aligned effective address are fetched, sign-extended to the GPR register length if necessary, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address. 5 rd 11 10 5 00000 0 6 5 6 0 MIPS32 010000 MFHI MFHI Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 181 In the MIPS I, II, and III architectures, the two instructions which follow the MFHI must not moodify the HI register. If this restriction is violated, the result of the MFHI is UNPREDICTABLE. This restriction was removed in MIPS IV and MIPS32, and all subsequent levels of the architecture. Historical Information: None Exceptions: GPR[rd] ← HI Operation: None Restrictions: Description: GPR[rd] ← HI Description: GPR[rt] ← memory[GPR[base] + offset] 16 15 To copy the special purpose HI register to a GPR MFHI rd 10 00 0000 0000 0 Purpose: Format: 26 25 To load a word from memory as a signed value LW rt, offset(base) 16 offset 0 Purpose: Format: 5 rt 16 15 6 5 base 21 20 6 26 25 Move From HI Register MFHI 000000 LW LW 100011 Load Word MIPS32® Architecture For Programmers Volume II, Revision 2.50 LW 182 31 rd 10 6 31 Format: 6 000000 SPECIAL 5 rs MULT rs, rt 26 25 21 20 5 rt 16 15 10 00 0000 0000 0 6 5 6 0 MIPS32 011000 MULT Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 In the MIPS I, II, and III architectures, the two instructions which follow the MFHI must not moodify the HI register. If this restriction is violated, the result of the MFHI is UNPREDICTABLE. This restriction was removed in MIPS IV and MIPS32, and all subsequent levels of the architecture. Historical Information: None Exceptions: GPR[rd] ← LO Operation: Restrictions: None ← GPR[rs]31..0 × GPR[rt]31..0 ← prod31..0 ← prod63..32 Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 209 Where the size of the operands are known, software should place the shorter operand in GPR rt. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies. Programs that require overflow detection must check for it explicitly. In some processors the integer multiply operation may proceed asynchronously and allow other CPU instructions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an opportunity for performance improvement by scheduling the multiply so that other instructions can execute in parallel. Programming Notes: None Exceptions: prod LO HI Operation: None Restrictions: No arithmetic exception occurs under any circumstances. The 32-bit word value in GPR rt is multiplied by the 32-bit value in GPR rs, treating both operands as signed values, to produce a 64-bit result. The low-order 32-bit word of the result is placed into special register LO, and the high-order 32-bit word is splaced into special register HI. MIPS32 0 Description: (HI, LO) ← GPR[rs] × GPR[rt] 6 010010 MFLO The contents of special register LO are loaded into GPR rd. 5 Description: GPR[rd] ← LO 6 To multiply 32-bit signed integers 5 00000 0 MULT Purpose: 5 rd 11 10 Multiply Word MULT To copy the special purpose LO register to a GPR 16 15 MFLO Purpose: MFLO 00 0000 0000 000000 Format: 0 SPECIAL 26 25 Move From LO Register MFLO 216 31 5 6 0 5 rt 16 15 5 rd 11 10 5 00000 0 6 5 6 0 MIPS32 100101 OR None Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 The zero instruction word, which represents SLL, r0, r0, 0, is the preferred NOP for software to use to fill branch and jump delay slots and to pad out alignment sequences. Programming Notes: Exceptions: None MIPS32® Architecture For Programmers Volume II, Revision 2.50 Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. GPR[rd] ← GPR[rs] or GPR[rt] Exceptions: None Operation: 21 20 None 218 5 rs OR rd, rs, rt 26 25 Operation: Format: 6 000000 SPECIAL Restrictions: 31 None Assembly Idiom 6 000000 SLL Restrictions: 5 The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical OR operation. The result is placed into GPR rd. 6 Description: GPR[rd] ← GPR[rs] or GPR[rt] 5 00000 0 NOP is the assembly idiom used to denote no operation. The actual instruction is interpreted by the hardware as SLL r0, r0, 0. 11 10 Description: 5 00000 0 OR To do a bitwise logical OR 16 15 Or Purpose: 5 00000 0 OR To perform no operation. 21 20 NOP Purpose: NOP 00000 000000 Format: 0 26 25 SPECIAL No Operation NOP 234 31 4 0000 5 6 000010 SRL 0 5 rd 11 10 5 sa 6 5 6 0 MIPS32 000000 SLL Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 Programming Notes: Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 SLL r0, r0, 1, expressed as SSNOP, is the assembly idiom used to denote no operation that causes an issue break on superscalar processors. SLL r0, r0, 0, expressed as NOP, is the assembly idiom used to denote no operation. None Reserved Instruction Exceptions: s ← sa temp ← GPR[rt](31-s)..0 || 0s GPR[rd]← temp Operation: None Exceptions: if ((ArchitectureRevision() < 2) and (Config3SM = 0)) then UNPREDICTABLE endif s ← sa temp ← GPR[rt]s-1..0 || GPR[rt]31..s GPR[rd]← temp Operation: Restrictions: 5 rt 16 15 Restrictions: 21 20 The contents of the low-order 32-bit word of GPR rt are shifted left, inserting zeros into the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by sa. 254 5 00000 0 SLL rd, rt, sa 26 25 Description: GPR[rd] ← GPR[rt] << sa Format: 6 000000 SPECIAL The contents of the low-order 32-bit word of GPR rt are rotated right; the word result is placed in GPR rd. The bit-rotate amount is specified by sa. 31 Description: GPR[rd] ← GPR[rt] ↔(right) sa SmartMIPS Crypto, MIPS32 Release 2 5 sa 6 SLL To left-shift a word by a fixed number of bits 5 rd 11 10 Shift Word Left Logical Purpose: 5 rt 16 15 SLL To execute a logical right-rotate of a word by a fixed number of bits 1 R 1 22 21 20 ROTR rd, rt, sa 26 25 ROTR Purpose: Format: 6 000000 SPECIAL Rotate Word Right ROTR 31 4 0000 1 R 0 22 21 20 SRL rd, rt, sa 26 25 5 rt 16 15 5 rd 11 10 5 sa 6 5 6 0 MIPS32 000010 SRL None Exceptions: MIPS32® Architecture For Programmers Volume II, Revision 2.50 Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. if GPR[rs] < GPR[rt] then GPR[rd] ← 0GPRLEN-1 || 1 else GPR[rd] ← 0GPRLEN endif Operation: None Restrictions: The arithmetic comparison does not cause an Integer Overflow exception. Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 None Exceptions: s ← sa temp ← 0s || GPR[rt]31..s GPR[rd]← temp Operation: None Restrictions: (logical) 263 The contents of the low-order 32-bit word of GPR rt are shifted right, inserting zeros into the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by sa. Format: 6 000000 SPECIAL Description: GPR[rd] ← GPR[rt] >> sa 31 Compare the contents of GPR rs and GPR rt as signed integers and record the Boolean result of the comparison in GPR rd. If GPR rs is less than GPR rt, the result is 1 (true); otherwise, it is 0 (false). MIPS32 0 Description: GPR[rd] ← (GPR[rs] < GPR[rt]) 6 101010 SLT To execute a logical right-shift of a word by a fixed number of bits 5 SRL Purpose: 6 Shift Word Right Logical SRL To record the result of a less-than comparison SLT rd, rs, rt 5 0 SLT Purpose: Format: 5 rd 11 10 5 5 rt 16 15 6 rs 21 20 00000 26 25 000000 SPECIAL Set on Less Than 256 SLT 266 31 270 5 base 21 20 SW rt, offset(base) 26 25 5 rt 16 15 16 offset MIPS32 0 Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 SUBU performs the same arithmetic operation but does not trap on overflow. Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. MIPS32® Architecture For Programmers Volume II, Revision 2.50 TLB Refill, TLB Invalid, TLB Modified, Address Error, Watch Programming Notes: Exceptions: Integer Overflow vAddr ← sign_extend(offset) + GPR[base] if vAddr1..0 ≠ 02 then SignalException(AddressError) endif (pAddr, CCA)← AddressTranslation (vAddr, DATA, STORE) dataword← GPR[rt] StoreMemory (CCA, WORD, dataword, pAddr, vAddr, DATA) Operation: The effective address must be naturally-aligned. If either of the 2 least-significant bits of the address is non-zero, an Address Error exception occurs. Restrictions: Exceptions: temp ← (GPR[rs]31||GPR[rs]31..0) − (GPR[rt]31||GPR[rt]31..0) if temp32 ≠ temp31 then SignalException(IntegerOverflow) else GPR[rd] ← temp31..0 endif Operation: None Restrictions: The least-significant 32-bit word of GPR rt is stored in memory at the location specified by the aligned effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address. Format: 6 101011 SW Description: memory[GPR[base] + offset] ← GPR[rt] 31 The 32-bit word value in GPR rt is subtracted from the 32-bit value in GPR rs to produce a 32-bit result. If the subtraction results in 32-bit 2’s complement arithmetic overflow, then the destination register is not modified and an Integer Overflow exception occurs. If it does not overflow, the 32-bit result is placed into GPR rd. MIPS32 0 Description: GPR[rd] ← GPR[rs] - GPR[rt] 6 100010 SUB SW To store a word to memory 5 Store Word Purpose: 6 SW To subtract 32-bit integers. If overflow occurs, then trap SUB rd, rs, rt 5 0 SUB Purpose: Format: 5 rd 11 10 5 5 rt 16 15 6 rs 21 20 00000 26 25 000000 SPECIAL Subtract Word SUB MIPS32 0 System Call Exceptions: SignalException(SystemCall) Operation: None Restrictions: Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. 285 The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. A system call exception occurs, immediately and unconditionally transferring control to the exception handler. Description: To cause a System Call exception Purpose: Format: SYSCALL 6 20 SYSCALL 6 5 001100 code 6 SYSCALL 000000 SPECIAL 26 25 MIPS32® Architecture For Programmers Volume II, Revision 2.50 31 System Call SYSCALL 5 rs XOR rd, rs, rt 26 25 21 20 5 rt 16 15 5 rd 11 10 5 00000 0 6 5 6 0 MIPS32 100110 XOR XOR None Exceptions: GPR[rd] ← GPR[rs] xor GPR[rt] Operation: None Restrictions: Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved. 313 Combine the contents of GPR rs and GPR rt in a bitwise logical Exclusive OR operation and place the result into GPR rd. Description: GPR[rd] ← GPR[rs] XOR GPR[rt] To do a bitwise logical Exclusive OR Purpose: Format: 6 000000 SPECIAL MIPS32® Architecture For Programmers Volume II, Revision 2.50 31 Exclusive OR XOR
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