CC2640x Reference Manual
User Manual:
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- Table of Contents
- Revision History: SWCU117G
- Preface
- 1 Architectural Overview
- 1.1 Target Applications
- 1.2 Overview
- 1.3 Functional Overview
- 1.3.1 ARM® Cortex®-M3
- 1.3.2 On-chip Memory
- 1.3.3 Radio
- 1.3.4 Advanced Encryption Standard (AES) Engine With 128-bit Key Support
- 1.3.5 General-Purpose Timers
- 1.3.6 Direct Memory Access
- 1.3.7 System Control and Clock
- 1.3.8 Serial Communication Peripherals
- 1.3.9 Programmable I/Os
- 1.3.10 Sensor Controller
- 1.3.11 Random Number Generator
- 1.3.12 cJTAG and JTAG
- 1.3.13 Power Supply System
- 2 The ARM® Cortex®-M3 Processor
- 2.1 The Cortex-M3 Processor Introduction
- 2.2 Block Diagram
- 2.3 Overview
- 2.4 Programming Model
- 2.5 Cortex-M3 Core Registers
- 2.5.1 Core Register Map
- 2.5.2 Core Register Descriptions
- 2.5.2.1 Cortex General-Purpose Register 0 (R0)
- 2.5.2.2 Cortex General-Purpose Register 1 (R1)
- 2.5.2.3 Cortex General-Purpose Register 2 (R2)
- 2.5.2.4 Cortex General-Purpose Register 3 (R3)
- 2.5.2.5 Cortex General-Purpose Register 4 (R4)
- 2.5.2.6 Cortex General-Purpose Register 5 (R5)
- 2.5.2.7 Cortex General-Purpose Register 6 (R6)
- 2.5.2.8 Cortex General-Purpose Register 7 (R7)
- 2.5.2.9 Cortex General-Purpose Register 8 (R8)
- 2.5.2.10 Cortex General-Purpose Register 9 (R9)
- 2.5.2.11 Cortex General-Purpose Register 10 (R10)
- 2.5.2.12 Cortex General-Purpose Register 11 (R11)
- 2.5.2.13 Cortex General-Purpose Register 12 (R12)
- 2.5.2.14 Stack Pointer (SP)
- 2.5.2.15 Link Register (LR)
- 2.5.2.16 Program Counter (PC)
- 2.5.2.17 Program Status Register (PSR)
- 2.5.2.18 Priority Mask Register (PRIMASK)
- 2.5.2.19 Fault Mask Register (FAULTMASK)
- 2.5.2.20 Base Priority Mask Register (BASEPRI)
- 2.5.2.21 Control Register (CONTROL)
- 2.6 Instruction Set Summary
- 2.7 Cortex-M3 Processor Registers
- 2.7.1 CPU_DWT Registers
- 2.7.1.1 CTRL Register (Offset = 0h) [reset = 40000000h]
- 2.7.1.2 CYCCNT Register (Offset = 4h) [reset = 0h]
- 2.7.1.3 CPICNT Register (Offset = 8h) [reset = X]
- 2.7.1.4 EXCCNT Register (Offset = Ch) [reset = X]
- 2.7.1.5 SLEEPCNT Register (Offset = 10h) [reset = X]
- 2.7.1.6 LSUCNT Register (Offset = 14h) [reset = X]
- 2.7.1.7 FOLDCNT Register (Offset = 18h) [reset = X]
- 2.7.1.8 PCSR Register (Offset = 1Ch) [reset = X]
- 2.7.1.9 COMP0 Register (Offset = 20h) [reset = X]
- 2.7.1.10 MASK0 Register (Offset = 24h) [reset = X]
- 2.7.1.11 FUNCTION0 Register (Offset = 28h) [reset = 0h]
- 2.7.1.12 COMP1 Register (Offset = 30h) [reset = X]
- 2.7.1.13 MASK1 Register (Offset = 34h) [reset = X]
- 2.7.1.14 FUNCTION1 Register (Offset = 38h) [reset = 200h]
- 2.7.1.15 COMP2 Register (Offset = 40h) [reset = X]
- 2.7.1.16 MASK2 Register (Offset = 44h) [reset = X]
- 2.7.1.17 FUNCTION2 Register (Offset = 48h) [reset = 0h]
- 2.7.1.18 COMP3 Register (Offset = 50h) [reset = X]
- 2.7.1.19 MASK3 Register (Offset = 54h) [reset = X]
- 2.7.1.20 FUNCTION3 Register (Offset = 58h) [reset = 0h]
- 2.7.2 CPU_FPB Registers
- 2.7.2.1 CTRL Register (Offset = 0h) [reset = 260h]
- 2.7.2.2 REMAP Register (Offset = 4h) [reset = X]
- 2.7.2.3 COMP0 Register (Offset = 8h) [reset = 0h]
- 2.7.2.4 COMP1 Register (Offset = Ch) [reset = 0h]
- 2.7.2.5 COMP2 Register (Offset = 10h) [reset = 0h]
- 2.7.2.6 COMP3 Register (Offset = 14h) [reset = 0h]
- 2.7.2.7 COMP4 Register (Offset = 18h) [reset = 0h]
- 2.7.2.8 COMP5 Register (Offset = 1Ch) [reset = 0h]
- 2.7.2.9 COMP6 Register (Offset = 20h) [reset = 0h]
- 2.7.2.10 COMP7 Register (Offset = 24h) [reset = 0h]
- 2.7.3 CPU_ITM Registers
- 2.7.3.1 STIM0 Register (Offset = 0h) [reset = X]
- 2.7.3.2 STIM1 Register (Offset = 4h) [reset = X]
- 2.7.3.3 STIM2 Register (Offset = 8h) [reset = X]
- 2.7.3.4 STIM3 Register (Offset = Ch) [reset = X]
- 2.7.3.5 STIM4 Register (Offset = 10h) [reset = X]
- 2.7.3.6 STIM5 Register (Offset = 14h) [reset = X]
- 2.7.3.7 STIM6 Register (Offset = 18h) [reset = X]
- 2.7.3.8 STIM7 Register (Offset = 1Ch) [reset = X]
- 2.7.3.9 STIM8 Register (Offset = 20h) [reset = X]
- 2.7.3.10 STIM9 Register (Offset = 24h) [reset = X]
- 2.7.3.11 STIM10 Register (Offset = 28h) [reset = X]
- 2.7.3.12 STIM11 Register (Offset = 2Ch) [reset = X]
- 2.7.3.13 STIM12 Register (Offset = 30h) [reset = X]
- 2.7.3.14 STIM13 Register (Offset = 34h) [reset = X]
- 2.7.3.15 STIM14 Register (Offset = 38h) [reset = X]
- 2.7.3.16 STIM15 Register (Offset = 3Ch) [reset = X]
- 2.7.3.17 STIM16 Register (Offset = 40h) [reset = X]
- 2.7.3.18 STIM17 Register (Offset = 44h) [reset = X]
- 2.7.3.19 STIM18 Register (Offset = 48h) [reset = X]
- 2.7.3.20 STIM19 Register (Offset = 4Ch) [reset = X]
- 2.7.3.21 STIM20 Register (Offset = 50h) [reset = X]
- 2.7.3.22 STIM21 Register (Offset = 54h) [reset = X]
- 2.7.3.23 STIM22 Register (Offset = 58h) [reset = X]
- 2.7.3.24 STIM23 Register (Offset = 5Ch) [reset = X]
- 2.7.3.25 STIM24 Register (Offset = 60h) [reset = X]
- 2.7.3.26 STIM25 Register (Offset = 64h) [reset = X]
- 2.7.3.27 STIM26 Register (Offset = 68h) [reset = X]
- 2.7.3.28 STIM27 Register (Offset = 6Ch) [reset = X]
- 2.7.3.29 STIM28 Register (Offset = 70h) [reset = X]
- 2.7.3.30 STIM29 Register (Offset = 74h) [reset = X]
- 2.7.3.31 STIM30 Register (Offset = 78h) [reset = X]
- 2.7.3.32 STIM31 Register (Offset = 7Ch) [reset = X]
- 2.7.3.33 TER Register (Offset = E00h) [reset = 0h]
- 2.7.3.34 TPR Register (Offset = E40h) [reset = 0h]
- 2.7.3.35 TCR Register (Offset = E80h) [reset = 0h]
- 2.7.3.36 LAR Register (Offset = FB0h) [reset = 0h]
- 2.7.3.37 LSR Register (Offset = FB4h) [reset = 3h]
- 2.7.4 CPU_SCS Registers
- 2.7.4.1 ICTR Register (Offset = 4h) [reset = 1h]
- 2.7.4.2 ACTLR Register (Offset = 8h) [reset = 0h]
- 2.7.4.3 STCSR Register (Offset = 10h) [reset = 4h]
- 2.7.4.4 STRVR Register (Offset = 14h) [reset = X]
- 2.7.4.5 STCVR Register (Offset = 18h) [reset = X]
- 2.7.4.6 STCR Register (Offset = 1Ch) [reset = C0075300h]
- 2.7.4.7 NVIC_ISER0 Register (Offset = 100h) [reset = 0h]
- 2.7.4.8 NVIC_ISER1 Register (Offset = 104h) [reset = 0h]
- 2.7.4.9 NVIC_ICER0 Register (Offset = 180h) [reset = 0h]
- 2.7.4.10 NVIC_ICER1 Register (Offset = 184h) [reset = 0h]
- 2.7.4.11 NVIC_ISPR0 Register (Offset = 200h) [reset = 0h]
- 2.7.4.12 NVIC_ISPR1 Register (Offset = 204h) [reset = 0h]
- 2.7.4.13 NVIC_ICPR0 Register (Offset = 280h) [reset = 0h]
- 2.7.4.14 NVIC_ICPR1 Register (Offset = 284h) [reset = 0h]
- 2.7.4.15 NVIC_IABR0 Register (Offset = 300h) [reset = 0h]
- 2.7.4.16 NVIC_IABR1 Register (Offset = 304h) [reset = 0h]
- 2.7.4.17 NVIC_IPR0 Register (Offset = 400h) [reset = 0h]
- 2.7.4.18 NVIC_IPR1 Register (Offset = 404h) [reset = 0h]
- 2.7.4.19 NVIC_IPR2 Register (Offset = 408h) [reset = 0h]
- 2.7.4.20 NVIC_IPR3 Register (Offset = 40Ch) [reset = 0h]
- 2.7.4.21 NVIC_IPR4 Register (Offset = 410h) [reset = 0h]
- 2.7.4.22 NVIC_IPR5 Register (Offset = 414h) [reset = 0h]
- 2.7.4.23 NVIC_IPR6 Register (Offset = 418h) [reset = 0h]
- 2.7.4.24 NVIC_IPR7 Register (Offset = 41Ch) [reset = 0h]
- 2.7.4.25 NVIC_IPR8 Register (Offset = 420h) [reset = 0h]
- 2.7.4.26 CPUID Register (Offset = D00h) [reset = 412FC231h]
- 2.7.4.27 ICSR Register (Offset = D04h) [reset = X]
- 2.7.4.28 VTOR Register (Offset = D08h) [reset = 0h]
- 2.7.4.29 AIRCR Register (Offset = D0Ch) [reset = FA050000h]
- 2.7.4.30 SCR Register (Offset = D10h) [reset = 0h]
- 2.7.4.31 CCR Register (Offset = D14h) [reset = 200h]
- 2.7.4.32 SHPR1 Register (Offset = D18h) [reset = 0h]
- 2.7.4.33 SHPR2 Register (Offset = D1Ch) [reset = 0h]
- 2.7.4.34 SHPR3 Register (Offset = D20h) [reset = 0h]
- 2.7.4.35 SHCSR Register (Offset = D24h) [reset = 0h]
- 2.7.4.36 CFSR Register (Offset = D28h) [reset = 0h]
- 2.7.4.37 HFSR Register (Offset = D2Ch) [reset = 0h]
- 2.7.4.38 DFSR Register (Offset = D30h) [reset = 0h]
- 2.7.4.39 MMFAR Register (Offset = D34h) [reset = X]
- 2.7.4.40 BFAR Register (Offset = D38h) [reset = X]
- 2.7.4.41 AFSR Register (Offset = D3Ch) [reset = 0h]
- 2.7.4.42 ID_PFR0 Register (Offset = D40h) [reset = 30h]
- 2.7.4.43 ID_PFR1 Register (Offset = D44h) [reset = 200h]
- 2.7.4.44 ID_DFR0 Register (Offset = D48h) [reset = 00100000h]
- 2.7.4.45 ID_AFR0 Register (Offset = D4Ch) [reset = 0h]
- 2.7.4.46 ID_MMFR0 Register (Offset = D50h) [reset = 00100030h]
- 2.7.4.47 ID_MMFR1 Register (Offset = D54h) [reset = 0h]
- 2.7.4.48 ID_MMFR2 Register (Offset = D58h) [reset = 01000000h]
- 2.7.4.49 ID_MMFR3 Register (Offset = D5Ch) [reset = 0h]
- 2.7.4.50 ID_ISAR0 Register (Offset = D60h) [reset = 01101110h]
- 2.7.4.51 ID_ISAR1 Register (Offset = D64h) [reset = 02111000h]
- 2.7.4.52 ID_ISAR2 Register (Offset = D68h) [reset = 21112231h]
- 2.7.4.53 ID_ISAR3 Register (Offset = D6Ch) [reset = 01111110h]
- 2.7.4.54 ID_ISAR4 Register (Offset = D70h) [reset = 01310132h]
- 2.7.4.55 CPACR Register (Offset = D88h) [reset = 0h]
- 2.7.4.56 DHCSR Register (Offset = DF0h) [reset = X]
- 2.7.4.57 DCRSR Register (Offset = DF4h) [reset = X]
- 2.7.4.58 DCRDR Register (Offset = DF8h) [reset = X]
- 2.7.4.59 DEMCR Register (Offset = DFCh) [reset = 0h]
- 2.7.4.60 STIR Register (Offset = F00h) [reset = X]
- 2.7.5 CPU_TPIU Registers
- 2.7.5.1 SSPSR Register (Offset = 0h) [reset = Bh]
- 2.7.5.2 CSPSR Register (Offset = 4h) [reset = 1h]
- 2.7.5.3 ACPR Register (Offset = 10h) [reset = 0h]
- 2.7.5.4 SPPR Register (Offset = F0h) [reset = 1h]
- 2.7.5.5 FFSR Register (Offset = 300h) [reset = 8h]
- 2.7.5.6 FFCR Register (Offset = 304h) [reset = 102h]
- 2.7.5.7 FSCR Register (Offset = 308h) [reset = 0h]
- 2.7.5.8 CLAIMMASK Register (Offset = FA0h) [reset = Fh]
- 2.7.5.9 CLAIMSET Register (Offset = FA0h) [reset = Fh]
- 2.7.5.10 CLAIMTAG Register (Offset = FA4h) [reset = 0h]
- 2.7.5.11 CLAIMCLR Register (Offset = FA4h) [reset = 0h]
- 2.7.5.12 DEVID Register (Offset = FC8h) [reset = CA0h]
- 2.7.1 CPU_DWT Registers
- 3 ARM® Cortex®-M3 Peripherals
- 4 Interrupts and Events
- 4.1 Exception Model
- 4.2 Fault Handling
- 4.3 Event Fabric
- 4.4 AON Event Fabric
- 4.5 MCU Event Fabric
- 4.6 AON Events
- 4.7 Interrupts and Events Registers
- 4.7.1 AON_EVENT Registers
- 4.7.2 EVENT Registers
- 4.7.2.1 CPUIRQSEL0 Register (Offset = 0h) [reset = 4h]
- 4.7.2.2 CPUIRQSEL1 Register (Offset = 4h) [reset = 9h]
- 4.7.2.3 CPUIRQSEL2 Register (Offset = 8h) [reset = 1Eh]
- 4.7.2.4 CPUIRQSEL3 Register (Offset = Ch) [reset = 38h]
- 4.7.2.5 CPUIRQSEL4 Register (Offset = 10h) [reset = 7h]
- 4.7.2.6 CPUIRQSEL5 Register (Offset = 14h) [reset = 24h]
- 4.7.2.7 CPUIRQSEL6 Register (Offset = 18h) [reset = 1Ch]
- 4.7.2.8 CPUIRQSEL7 Register (Offset = 1Ch) [reset = 22h]
- 4.7.2.9 CPUIRQSEL8 Register (Offset = 20h) [reset = 23h]
- 4.7.2.10 CPUIRQSEL9 Register (Offset = 24h) [reset = 1Bh]
- 4.7.2.11 CPUIRQSEL10 Register (Offset = 28h) [reset = 1Ah]
- 4.7.2.12 CPUIRQSEL11 Register (Offset = 2Ch) [reset = 19h]
- 4.7.2.13 CPUIRQSEL12 Register (Offset = 30h) [reset = 8h]
- 4.7.2.14 CPUIRQSEL13 Register (Offset = 34h) [reset = 1Dh]
- 4.7.2.15 CPUIRQSEL14 Register (Offset = 38h) [reset = 18h]
- 4.7.2.16 CPUIRQSEL15 Register (Offset = 3Ch) [reset = 10h]
- 4.7.2.17 CPUIRQSEL16 Register (Offset = 40h) [reset = 11h]
- 4.7.2.18 CPUIRQSEL17 Register (Offset = 44h) [reset = 12h]
- 4.7.2.19 CPUIRQSEL18 Register (Offset = 48h) [reset = 13h]
- 4.7.2.20 CPUIRQSEL19 Register (Offset = 4Ch) [reset = Ch]
- 4.7.2.21 CPUIRQSEL20 Register (Offset = 50h) [reset = Dh]
- 4.7.2.22 CPUIRQSEL21 Register (Offset = 54h) [reset = Eh]
- 4.7.2.23 CPUIRQSEL22 Register (Offset = 58h) [reset = Fh]
- 4.7.2.24 CPUIRQSEL23 Register (Offset = 5Ch) [reset = 5Dh]
- 4.7.2.25 CPUIRQSEL24 Register (Offset = 60h) [reset = 27h]
- 4.7.2.26 CPUIRQSEL25 Register (Offset = 64h) [reset = 26h]
- 4.7.2.27 CPUIRQSEL26 Register (Offset = 68h) [reset = 15h]
- 4.7.2.28 CPUIRQSEL27 Register (Offset = 6Ch) [reset = 64h]
- 4.7.2.29 CPUIRQSEL28 Register (Offset = 70h) [reset = Bh]
- 4.7.2.30 CPUIRQSEL29 Register (Offset = 74h) [reset = 1h]
- 4.7.2.31 CPUIRQSEL30 Register (Offset = 78h) [reset = 0h]
- 4.7.2.32 CPUIRQSEL31 Register (Offset = 7Ch) [reset = 6Ah]
- 4.7.2.33 CPUIRQSEL32 Register (Offset = 80h) [reset = 73h]
- 4.7.2.34 CPUIRQSEL33 Register (Offset = 84h) [reset = 68h]
- 4.7.2.35 RFCSEL0 Register (Offset = 100h) [reset = 3Dh]
- 4.7.2.36 RFCSEL1 Register (Offset = 104h) [reset = 3Eh]
- 4.7.2.37 RFCSEL2 Register (Offset = 108h) [reset = 3Fh]
- 4.7.2.38 RFCSEL3 Register (Offset = 10Ch) [reset = 40h]
- 4.7.2.39 RFCSEL4 Register (Offset = 110h) [reset = 41h]
- 4.7.2.40 RFCSEL5 Register (Offset = 114h) [reset = 42h]
- 4.7.2.41 RFCSEL6 Register (Offset = 118h) [reset = 43h]
- 4.7.2.42 RFCSEL7 Register (Offset = 11Ch) [reset = 44h]
- 4.7.2.43 RFCSEL8 Register (Offset = 120h) [reset = 77h]
- 4.7.2.44 RFCSEL9 Register (Offset = 124h) [reset = 2h]
- 4.7.2.45 GPT0ACAPTSEL Register (Offset = 200h) [reset = 55h]
- 4.7.2.46 GPT0BCAPTSEL Register (Offset = 204h) [reset = 56h]
- 4.7.2.47 GPT1ACAPTSEL Register (Offset = 300h) [reset = 57h]
- 4.7.2.48 GPT1BCAPTSEL Register (Offset = 304h) [reset = 58h]
- 4.7.2.49 GPT2ACAPTSEL Register (Offset = 400h) [reset = 59h]
- 4.7.2.50 GPT2BCAPTSEL Register (Offset = 404h) [reset = 5Ah]
- 4.7.2.51 UDMACH1SSEL Register (Offset = 508h) [reset = 31h]
- 4.7.2.52 UDMACH1BSEL Register (Offset = 50Ch) [reset = 30h]
- 4.7.2.53 UDMACH2SSEL Register (Offset = 510h) [reset = 33h]
- 4.7.2.54 UDMACH2BSEL Register (Offset = 514h) [reset = 32h]
- 4.7.2.55 UDMACH3SSEL Register (Offset = 518h) [reset = 29h]
- 4.7.2.56 UDMACH3BSEL Register (Offset = 51Ch) [reset = 28h]
- 4.7.2.57 UDMACH4SSEL Register (Offset = 520h) [reset = 2Bh]
- 4.7.2.58 UDMACH4BSEL Register (Offset = 524h) [reset = 2Ah]
- 4.7.2.59 UDMACH5SSEL Register (Offset = 528h) [reset = 3Ah]
- 4.7.2.60 UDMACH5BSEL Register (Offset = 52Ch) [reset = 39h]
- 4.7.2.61 UDMACH6SSEL Register (Offset = 530h) [reset = 3Ch]
- 4.7.2.62 UDMACH6BSEL Register (Offset = 534h) [reset = 3Bh]
- 4.7.2.63 UDMACH7SSEL Register (Offset = 538h) [reset = 75h]
- 4.7.2.64 UDMACH7BSEL Register (Offset = 53Ch) [reset = 76h]
- 4.7.2.65 UDMACH8SSEL Register (Offset = 540h) [reset = 74h]
- 4.7.2.66 UDMACH8BSEL Register (Offset = 544h) [reset = 74h]
- 4.7.2.67 UDMACH9SSEL Register (Offset = 548h) [reset = 45h]
- 4.7.2.68 UDMACH9BSEL Register (Offset = 54Ch) [reset = 4Dh]
- 4.7.2.69 UDMACH10SSEL Register (Offset = 550h) [reset = 46h]
- 4.7.2.70 UDMACH10BSEL Register (Offset = 554h) [reset = 4Eh]
- 4.7.2.71 UDMACH11SSEL Register (Offset = 558h) [reset = 47h]
- 4.7.2.72 UDMACH11BSEL Register (Offset = 55Ch) [reset = 4Fh]
- 4.7.2.73 UDMACH12SSEL Register (Offset = 560h) [reset = 48h]
- 4.7.2.74 UDMACH12BSEL Register (Offset = 564h) [reset = 50h]
- 4.7.2.75 UDMACH13BSEL Register (Offset = 56Ch) [reset = 3h]
- 4.7.2.76 UDMACH14BSEL Register (Offset = 574h) [reset = 1h]
- 4.7.2.77 UDMACH15BSEL Register (Offset = 57Ch) [reset = 7h]
- 4.7.2.78 UDMACH16SSEL Register (Offset = 580h) [reset = 2Dh]
- 4.7.2.79 UDMACH16BSEL Register (Offset = 584h) [reset = 2Ch]
- 4.7.2.80 UDMACH17SSEL Register (Offset = 588h) [reset = 2Fh]
- 4.7.2.81 UDMACH17BSEL Register (Offset = 58Ch) [reset = 2Eh]
- 4.7.2.82 UDMACH21SSEL Register (Offset = 5A8h) [reset = 64h]
- 4.7.2.83 UDMACH21BSEL Register (Offset = 5ACh) [reset = 64h]
- 4.7.2.84 UDMACH22SSEL Register (Offset = 5B0h) [reset = 65h]
- 4.7.2.85 UDMACH22BSEL Register (Offset = 5B4h) [reset = 65h]
- 4.7.2.86 UDMACH23SSEL Register (Offset = 5B8h) [reset = 66h]
- 4.7.2.87 UDMACH23BSEL Register (Offset = 5BCh) [reset = 66h]
- 4.7.2.88 UDMACH24SSEL Register (Offset = 5C0h) [reset = 67h]
- 4.7.2.89 UDMACH24BSEL Register (Offset = 5C4h) [reset = 67h]
- 4.7.2.90 GPT3ACAPTSEL Register (Offset = 600h) [reset = 5Bh]
- 4.7.2.91 GPT3BCAPTSEL Register (Offset = 604h) [reset = 5Ch]
- 4.7.2.92 AUXSEL0 Register (Offset = 700h) [reset = 10h]
- 4.7.2.93 CM3NMISEL0 Register (Offset = 800h) [reset = 63h]
- 4.7.2.94 I2SSTMPSEL0 Register (Offset = 900h) [reset = 5Fh]
- 4.7.2.95 FRZSEL0 Register (Offset = A00h) [reset = 78h]
- 4.7.2.96 SWEV Register (Offset = F00h) [reset = 0h]
- 5 JTAG Interface
- 6 Power, Reset, and Clock Management
- 6.1 Introduction
- 6.2 System CPU Mode
- 6.3 Supply System
- 6.4 Digital Power Partitioning
- 6.5 Clock Management
- 6.6 Power Modes
- 6.7 Reset
- 6.8 PRCM Registers
- 6.8.1 CC13x0 DDI_0_OSC Registers
- 6.8.1.1 DDI_0_OSC Registers
- 6.8.1.1.1 CTL0 Register (Offset = 0h) [reset = 0h]
- 6.8.1.1.2 CTL1 Register (Offset = 4h) [reset = 0h]
- 6.8.1.1.3 RADCEXTCFG Register (Offset = 8h) [reset = 0h]
- 6.8.1.1.4 AMPCOMPCTL Register (Offset = Ch) [reset = 0h]
- 6.8.1.1.5 AMPCOMPTH1 Register (Offset = 10h) [reset = 0h]
- 6.8.1.1.6 AMPCOMPTH2 Register (Offset = 14h) [reset = 0h]
- 6.8.1.1.7 ANABYPASSVAL1 Register (Offset = 18h) [reset = 0h]
- 6.8.1.1.8 ANABYPASSVAL2 Register (Offset = 1Ch) [reset = 0h]
- 6.8.1.1.9 ATESTCTL Register (Offset = 20h) [reset = 0h]
- 6.8.1.1.10 ADCDOUBLERNANOAMPCTL Register (Offset = 24h) [reset = 0h]
- 6.8.1.1.11 XOSCHFCTL Register (Offset = 28h) [reset = 0h]
- 6.8.1.1.12 LFOSCCTL Register (Offset = 2Ch) [reset = 0h]
- 6.8.1.1.13 RCOSCHFCTL Register (Offset = 30h) [reset = 0h]
- 6.8.1.1.14 STAT0 Register (Offset = 34h) [reset = 0h]
- 6.8.1.1.15 STAT1 Register (Offset = 38h) [reset = 0h]
- 6.8.1.1.16 STAT2 Register (Offset = 3Ch) [reset = 0h]
- 6.8.1.1 DDI_0_OSC Registers
- 6.8.2 CC26x0 PRCM Registers
- 6.8.2.1 DDI_0_OSC Registers
- 6.8.2.1.1 CTL0 Register (Offset = 0h) [reset = 0h]
- 6.8.2.1.2 CTL1 Register (Offset = 4h) [reset = 0h]
- 6.8.2.1.3 RADCEXTCFG Register (Offset = 8h) [reset = 0h]
- 6.8.2.1.4 AMPCOMPCTL Register (Offset = Ch) [reset = 0h]
- 6.8.2.1.5 AMPCOMPTH1 Register (Offset = 10h) [reset = 0h]
- 6.8.2.1.6 AMPCOMPTH2 Register (Offset = 14h) [reset = 0h]
- 6.8.2.1.7 ANABYPASSVAL1 Register (Offset = 18h) [reset = 0h]
- 6.8.2.1.8 ANABYPASSVAL2 Register (Offset = 1Ch) [reset = 0h]
- 6.8.2.1.9 ATESTCTL Register (Offset = 20h) [reset = 0h]
- 6.8.2.1.10 ADCDOUBLERNANOAMPCTL Register (Offset = 24h) [reset = 0h]
- 6.8.2.1.11 XOSCHFCTL Register (Offset = 28h) [reset = 0h]
- 6.8.2.1.12 LFOSCCTL Register (Offset = 2Ch) [reset = 0h]
- 6.8.2.1.13 RCOSCHFCTL Register (Offset = 30h) [reset = 0h]
- 6.8.2.1.14 STAT0 Register (Offset = 34h) [reset = 0h]
- 6.8.2.1.15 STAT1 Register (Offset = 38h) [reset = 0h]
- 6.8.2.1.16 STAT2 Register (Offset = 3Ch) [reset = 0h]
- 6.8.2.2 AON_SYSCTL Registers
- 6.8.2.3 AON_WUC Registers
- 6.8.2.3.1 MCUCLK Register (Offset = 0h) [reset = 0h]
- 6.8.2.3.2 AUXCLK Register (Offset = 4h) [reset = 1h]
- 6.8.2.3.3 MCUCFG Register (Offset = 8h) [reset = Fh]
- 6.8.2.3.4 AUXCFG Register (Offset = Ch) [reset = 1h]
- 6.8.2.3.5 AUXCTL Register (Offset = 10h) [reset = 0h]
- 6.8.2.3.6 PWRSTAT Register (Offset = 14h) [reset = 03800000h]
- 6.8.2.3.7 SHUTDOWN Register (Offset = 18h) [reset = 0h]
- 6.8.2.3.8 CTL0 Register (Offset = 20h) [reset = 0h]
- 6.8.2.3.9 CTL1 Register (Offset = 24h) [reset = 0h]
- 6.8.2.3.10 RECHARGECFG Register (Offset = 30h) [reset = 0h]
- 6.8.2.3.11 RECHARGESTAT Register (Offset = 34h) [reset = 0h]
- 6.8.2.3.12 OSCCFG Register (Offset = 38h) [reset = 0h]
- 6.8.2.3.13 JTAGCFG Register (Offset = 40h) [reset = 100h]
- 6.8.2.3.14 JTAGUSERCODE Register (Offset = 44h) [reset = 0B99A02Fh]
- 6.8.2.4 PRCM Registers
- 6.8.2.4.1 INFRCLKDIVR Register (Offset = 0h) [reset = 0h]
- 6.8.2.4.2 INFRCLKDIVS Register (Offset = 4h) [reset = 0h]
- 6.8.2.4.3 INFRCLKDIVDS Register (Offset = 8h) [reset = 0h]
- 6.8.2.4.4 VDCTL Register (Offset = Ch) [reset = 0h]
- 6.8.2.4.5 CLKLOADCTL Register (Offset = 28h) [reset = 2h]
- 6.8.2.4.6 RFCCLKG Register (Offset = 2Ch) [reset = 1h]
- 6.8.2.4.7 VIMSCLKG Register (Offset = 30h) [reset = 3h]
- 6.8.2.4.8 SECDMACLKGR Register (Offset = 3Ch) [reset = 0h]
- 6.8.2.4.9 SECDMACLKGS Register (Offset = 40h) [reset = 0h]
- 6.8.2.4.10 SECDMACLKGDS Register (Offset = 44h) [reset = 0h]
- 6.8.2.4.11 GPIOCLKGR Register (Offset = 48h) [reset = 0h]
- 6.8.2.4.12 GPIOCLKGS Register (Offset = 4Ch) [reset = 0h]
- 6.8.2.4.13 GPIOCLKGDS Register (Offset = 50h) [reset = 0h]
- 6.8.2.4.14 GPTCLKGR Register (Offset = 54h) [reset = 0h]
- 6.8.2.4.15 GPTCLKGS Register (Offset = 58h) [reset = 0h]
- 6.8.2.4.16 GPTCLKGDS Register (Offset = 5Ch) [reset = 0h]
- 6.8.2.4.17 I2CCLKGR Register (Offset = 60h) [reset = 0h]
- 6.8.2.4.18 I2CCLKGS Register (Offset = 64h) [reset = 0h]
- 6.8.2.4.19 I2CCLKGDS Register (Offset = 68h) [reset = 0h]
- 6.8.2.4.20 UARTCLKGR Register (Offset = 6Ch) [reset = 0h]
- 6.8.2.4.21 UARTCLKGS Register (Offset = 70h) [reset = 0h]
- 6.8.2.4.22 UARTCLKGDS Register (Offset = 74h) [reset = 0h]
- 6.8.2.4.23 SSICLKGR Register (Offset = 78h) [reset = 0h]
- 6.8.2.4.24 SSICLKGS Register (Offset = 7Ch) [reset = 0h]
- 6.8.2.4.25 SSICLKGDS Register (Offset = 80h) [reset = 0h]
- 6.8.2.4.26 I2SCLKGR Register (Offset = 84h) [reset = 0h]
- 6.8.2.4.27 I2SCLKGS Register (Offset = 88h) [reset = 0h]
- 6.8.2.4.28 I2SCLKGDS Register (Offset = 8Ch) [reset = 0h]
- 6.8.2.4.29 CPUCLKDIV Register (Offset = B8h) [reset = 0h]
- 6.8.2.4.30 I2SBCLKSEL Register (Offset = C8h) [reset = 0h]
- 6.8.2.4.31 GPTCLKDIV Register (Offset = CCh) [reset = 0h]
- 6.8.2.4.32 I2SCLKCTL Register (Offset = D0h) [reset = 0h]
- 6.8.2.4.33 I2SMCLKDIV Register (Offset = D4h) [reset = 0h]
- 6.8.2.4.34 I2SBCLKDIV Register (Offset = D8h) [reset = 0h]
- 6.8.2.4.35 I2SWCLKDIV Register (Offset = DCh) [reset = 0h]
- 6.8.2.4.36 SWRESET Register (Offset = 10Ch) [reset = 0h]
- 6.8.2.4.37 WARMRESET Register (Offset = 110h) [reset = 0h]
- 6.8.2.4.38 PDCTL0 Register (Offset = 12Ch) [reset = 0h]
- 6.8.2.4.39 PDCTL0RFC Register (Offset = 130h) [reset = 0h]
- 6.8.2.4.40 PDCTL0SERIAL Register (Offset = 134h) [reset = 0h]
- 6.8.2.4.41 PDCTL0PERIPH Register (Offset = 138h) [reset = 0h]
- 6.8.2.4.42 PDSTAT0 Register (Offset = 140h) [reset = 0h]
- 6.8.2.4.43 PDSTAT0RFC Register (Offset = 144h) [reset = 0h]
- 6.8.2.4.44 PDSTAT0SERIAL Register (Offset = 148h) [reset = 0h]
- 6.8.2.4.45 PDSTAT0PERIPH Register (Offset = 14Ch) [reset = 0h]
- 6.8.2.4.46 PDCTL1 Register (Offset = 17Ch) [reset = Ah]
- 6.8.2.4.47 PDCTL1CPU Register (Offset = 184h) [reset = 1h]
- 6.8.2.4.48 PDCTL1RFC Register (Offset = 188h) [reset = 0h]
- 6.8.2.4.49 PDCTL1VIMS Register (Offset = 18Ch) [reset = 1h]
- 6.8.2.4.50 PDSTAT1 Register (Offset = 194h) [reset = 1Ah]
- 6.8.2.4.51 PDSTAT1BUS Register (Offset = 198h) [reset = 1h]
- 6.8.2.4.52 PDSTAT1RFC Register (Offset = 19Ch) [reset = 0h]
- 6.8.2.4.53 PDSTAT1CPU Register (Offset = 1A0h) [reset = 1h]
- 6.8.2.4.54 PDSTAT1VIMS Register (Offset = 1A4h) [reset = 1h]
- 6.8.2.4.55 RFCBITS Register (Offset = 1CCh) [reset = 0h]
- 6.8.2.4.56 RFCMODESEL Register (Offset = 1D0h) [reset = 0h]
- 6.8.2.4.57 RFCMODEHWOPT Register (Offset = 1D4h) [reset = 0h]
- 6.8.2.4.58 PWRPROFSTAT Register (Offset = 1E0h) [reset = 1h]
- 6.8.2.4.59 RAMRETEN Register (Offset = 224h) [reset = 3h]
- 6.8.2.1 DDI_0_OSC Registers
- 6.8.1 CC13x0 DDI_0_OSC Registers
- 7 Versatile Instruction Memory System (VIMS)
- 7.1 VIMS Overview
- 7.2 VIMS Configurations
- 7.3 VIMS Software Remarks
- 7.4 ROM
- 7.5 FLASH
- 7.6 Power Management Requirements
- 7.7 ROM Functions
- 7.8 SRAM
- 7.9 VIMS Registers
- 7.9.1 FLASH Registers
- 7.9.1.1 STAT Register (Offset = 1Ch) [reset = 0h]
- 7.9.1.2 CFG Register (Offset = 24h) [reset = 0h]
- 7.9.1.3 SYSCODE_START Register (Offset = 28h) [reset = 0h]
- 7.9.1.4 FLASH_SIZE Register (Offset = 2Ch) [reset = 0h]
- 7.9.1.5 FWLOCK Register (Offset = 3Ch) [reset = 0h]
- 7.9.1.6 FWFLAG Register (Offset = 40h) [reset = 0h]
- 7.9.1.7 EFUSE Register (Offset = 1000h) [reset = 0h]
- 7.9.1.8 EFUSEADDR Register (Offset = 1004h) [reset = 0h]
- 7.9.1.9 DATAUPPER Register (Offset = 1008h) [reset = 0h]
- 7.9.1.10 DATALOWER Register (Offset = 100Ch) [reset = 0h]
- 7.9.1.11 EFUSECFG Register (Offset = 1010h) [reset = 1h]
- 7.9.1.12 EFUSESTAT Register (Offset = 1014h) [reset = 1h]
- 7.9.1.13 ACC Register (Offset = 1018h) [reset = 0h]
- 7.9.1.14 BOUNDARY Register (Offset = 101Ch) [reset = 0h]
- 7.9.1.15 EFUSEFLAG Register (Offset = 1020h) [reset = 0h]
- 7.9.1.16 EFUSEKEY Register (Offset = 1024h) [reset = 0h]
- 7.9.1.17 EFUSERELEASE Register (Offset = 1028h) [reset = X]
- 7.9.1.18 EFUSEPINS Register (Offset = 102Ch) [reset = X]
- 7.9.1.19 EFUSECRA Register (Offset = 1030h) [reset = 0h]
- 7.9.1.20 EFUSEREAD Register (Offset = 1034h) [reset = 0h]
- 7.9.1.21 EFUSEPROGRAM Register (Offset = 1038h) [reset = 0h]
- 7.9.1.22 EFUSEERROR Register (Offset = 103Ch) [reset = 0h]
- 7.9.1.23 SINGLEBIT Register (Offset = 1040h) [reset = 0h]
- 7.9.1.24 TWOBIT Register (Offset = 1044h) [reset = 0h]
- 7.9.1.25 SELFTESTCYC Register (Offset = 1048h) [reset = 0h]
- 7.9.1.26 SELFTESTSIGN Register (Offset = 104Ch) [reset = 0h]
- 7.9.1.27 FRDCTL Register (Offset = 2000h) [reset = 200h]
- 7.9.1.28 FSPRD Register (Offset = 2004h) [reset = 0h]
- 7.9.1.29 FEDACCTL1 Register (Offset = 2008h) [reset = 0h]
- 7.9.1.30 FEDACSTAT Register (Offset = 201Ch) [reset = 0h]
- 7.9.1.31 FBPROT Register (Offset = 2030h) [reset = 0h]
- 7.9.1.32 FBSE Register (Offset = 2034h) [reset = 0h]
- 7.9.1.33 FBBUSY Register (Offset = 2038h) [reset = FEh]
- 7.9.1.34 FBAC Register (Offset = 203Ch) [reset = Fh]
- 7.9.1.35 FBFALLBACK Register (Offset = 2040h) [reset = 0505FFFFh]
- 7.9.1.36 FBPRDY Register (Offset = 2044h) [reset = 00FF00FEh]
- 7.9.1.37 FPAC1 Register (Offset = 2048h) [reset = 02082081h]
- 7.9.1.38 FPAC2 Register (Offset = 204Ch) [reset = 0h]
- 7.9.1.39 FMAC Register (Offset = 2050h) [reset = 0h]
- 7.9.1.40 FMSTAT Register (Offset = 2054h) [reset = 0h]
- 7.9.1.41 FLOCK Register (Offset = 2064h) [reset = 55AAh]
- 7.9.1.42 FVREADCT Register (Offset = 2080h) [reset = 8h]
- 7.9.1.43 FVHVCT1 Register (Offset = 2084h) [reset = 00840088h]
- 7.9.1.44 FVHVCT2 Register (Offset = 2088h) [reset = 00A20000h]
- 7.9.1.45 FVHVCT3 Register (Offset = 208Ch) [reset = 000F0000h]
- 7.9.1.46 FVNVCT Register (Offset = 2090h) [reset = 800h]
- 7.9.1.47 FVSLP Register (Offset = 2094h) [reset = 8000h]
- 7.9.1.48 FVWLCT Register (Offset = 2098h) [reset = 8h]
- 7.9.1.49 FEFUSECTL Register (Offset = 209Ch) [reset = 0701010Ah]
- 7.9.1.50 FEFUSESTAT Register (Offset = 20A0h) [reset = 0h]
- 7.9.1.51 FEFUSEDATA Register (Offset = 20A4h) [reset = 0h]
- 7.9.1.52 FSEQPMP Register (Offset = 20A8h) [reset = 85080000h]
- 7.9.1.53 FBSTROBES Register (Offset = 2100h) [reset = 104h]
- 7.9.1.54 FPSTROBES Register (Offset = 2104h) [reset = 103h]
- 7.9.1.55 FBMODE Register (Offset = 2108h) [reset = 0h]
- 7.9.1.56 FTCR Register (Offset = 210Ch) [reset = 0h]
- 7.9.1.57 FADDR Register (Offset = 2110h) [reset = 0h]
- 7.9.1.58 FTCTL Register (Offset = 211Ch) [reset = 0h]
- 7.9.1.59 FWPWRITE0 Register (Offset = 2120h) [reset = FFFFFFFFh]
- 7.9.1.60 FWPWRITE1 Register (Offset = 2124h) [reset = FFFFFFFFh]
- 7.9.1.61 FWPWRITE2 Register (Offset = 2128h) [reset = FFFFFFFFh]
- 7.9.1.62 FWPWRITE3 Register (Offset = 212Ch) [reset = FFFFFFFFh]
- 7.9.1.63 FWPWRITE4 Register (Offset = 2130h) [reset = FFFFFFFFh]
- 7.9.1.64 FWPWRITE5 Register (Offset = 2134h) [reset = FFFFFFFFh]
- 7.9.1.65 FWPWRITE6 Register (Offset = 2138h) [reset = FFFFFFFFh]
- 7.9.1.66 FWPWRITE7 Register (Offset = 213Ch) [reset = FFFFFFFFh]
- 7.9.1.67 FWPWRITE_ECC Register (Offset = 2140h) [reset = FFFFFFFFh]
- 7.9.1.68 FSWSTAT Register (Offset = 2144h) [reset = 1h]
- 7.9.1.69 FSM_GLBCTL Register (Offset = 2200h) [reset = 1h]
- 7.9.1.70 FSM_STATE Register (Offset = 2204h) [reset = C00h]
- 7.9.1.71 FSM_STAT Register (Offset = 2208h) [reset = 4h]
- 7.9.1.72 FSM_CMD Register (Offset = 220Ch) [reset = 0h]
- 7.9.1.73 FSM_PE_OSU Register (Offset = 2210h) [reset = 0h]
- 7.9.1.74 FSM_VSTAT Register (Offset = 2214h) [reset = 3000h]
- 7.9.1.75 FSM_PE_VSU Register (Offset = 2218h) [reset = 0h]
- 7.9.1.76 FSM_CMP_VSU Register (Offset = 221Ch) [reset = 0h]
- 7.9.1.77 FSM_EX_VAL Register (Offset = 2220h) [reset = 301h]
- 7.9.1.78 FSM_RD_H Register (Offset = 2224h) [reset = 5Ah]
- 7.9.1.79 FSM_P_OH Register (Offset = 2228h) [reset = 100h]
- 7.9.1.80 FSM_ERA_OH Register (Offset = 222Ch) [reset = 1h]
- 7.9.1.81 FSM_SAV_PPUL Register (Offset = 2230h) [reset = 0h]
- 7.9.1.82 FSM_PE_VH Register (Offset = 2234h) [reset = 100h]
- 7.9.1.83 FSM_PRG_PW Register (Offset = 2240h) [reset = 0h]
- 7.9.1.84 FSM_ERA_PW Register (Offset = 2244h) [reset = 0h]
- 7.9.1.85 FSM_SAV_ERA_PUL Register (Offset = 2254h) [reset = 0h]
- 7.9.1.86 FSM_TIMER Register (Offset = 2258h) [reset = 0h]
- 7.9.1.87 FSM_MODE Register (Offset = 225Ch) [reset = 0h]
- 7.9.1.88 FSM_PGM Register (Offset = 2260h) [reset = 0h]
- 7.9.1.89 FSM_ERA Register (Offset = 2264h) [reset = 0h]
- 7.9.1.90 FSM_PRG_PUL Register (Offset = 2268h) [reset = 00040032h]
- 7.9.1.91 FSM_ERA_PUL Register (Offset = 226Ch) [reset = 00040BB8h]
- 7.9.1.92 FSM_STEP_SIZE Register (Offset = 2270h) [reset = 0h]
- 7.9.1.93 FSM_PUL_CNTR Register (Offset = 2274h) [reset = 0h]
- 7.9.1.94 FSM_EC_STEP_HEIGHT Register (Offset = 2278h) [reset = 0h]
- 7.9.1.95 FSM_ST_MACHINE Register (Offset = 227Ch) [reset = 00800500h]
- 7.9.1.96 FSM_FLES Register (Offset = 2280h) [reset = 0h]
- 7.9.1.97 FSM_WR_ENA Register (Offset = 2288h) [reset = 2h]
- 7.9.1.98 FSM_ACC_PP Register (Offset = 228Ch) [reset = 0h]
- 7.9.1.99 FSM_ACC_EP Register (Offset = 2290h) [reset = 0h]
- 7.9.1.100 FSM_ADDR Register (Offset = 22A0h) [reset = 0h]
- 7.9.1.101 FSM_SECTOR Register (Offset = 22A4h) [reset = FFFF0000h]
- 7.9.1.102 FMC_REV_ID Register (Offset = 22A8h) [reset = X]
- 7.9.1.103 FSM_ERR_ADDR Register (Offset = 22ACh) [reset = 0h]
- 7.9.1.104 FSM_PGM_MAXPUL Register (Offset = 22B0h) [reset = 0h]
- 7.9.1.105 FSM_EXECUTE Register (Offset = 22B4h) [reset = 000A000Ah]
- 7.9.1.106 FSM_SECTOR1 Register (Offset = 22C0h) [reset = FFFFFFFFh]
- 7.9.1.107 FSM_SECTOR2 Register (Offset = 22C4h) [reset = 0h]
- 7.9.1.108 FSM_BSLE0 Register (Offset = 22E0h) [reset = 0h]
- 7.9.1.109 FSM_BSLE1 Register (Offset = 22E4h) [reset = 0h]
- 7.9.1.110 FSM_BSLP0 Register (Offset = 22F0h) [reset = 0h]
- 7.9.1.111 FSM_BSLP1 Register (Offset = 22F4h) [reset = 0h]
- 7.9.1.112 FCFG_BANK Register (Offset = 2400h) [reset = 401h]
- 7.9.1.113 FCFG_WRAPPER Register (Offset = 2404h) [reset = 50009007h]
- 7.9.1.114 FCFG_BNK_TYPE Register (Offset = 2408h) [reset = 3h]
- 7.9.1.115 FCFG_B0_START Register (Offset = 2410h) [reset = 02000000h]
- 7.9.1.116 FCFG_B1_START Register (Offset = 2414h) [reset = 0h]
- 7.9.1.117 FCFG_B2_START Register (Offset = 2418h) [reset = 0h]
- 7.9.1.118 FCFG_B3_START Register (Offset = 241Ch) [reset = 0h]
- 7.9.1.119 FCFG_B4_START Register (Offset = 2420h) [reset = 0h]
- 7.9.1.120 FCFG_B5_START Register (Offset = 2424h) [reset = 0h]
- 7.9.1.121 FCFG_B6_START Register (Offset = 2428h) [reset = 0h]
- 7.9.1.122 FCFG_B7_START Register (Offset = 242Ch) [reset = 0h]
- 7.9.1.123 FCFG_B0_SSIZE0 Register (Offset = 2430h) [reset = 00200004h]
- 7.9.2 VIMS Registers
- 7.9.1 FLASH Registers
- 8 Bootloader
- 8.1 Bootloader Functionality
- 8.2 Bootloader Interfaces
- 8.2.1 Packet Handling
- 8.2.2 Transport Layer
- 8.2.3 Serial Bus Commands
- 8.2.3.1 COMMAND_PING
- 8.2.3.2 COMMAND_DOWNLOAD
- 8.2.3.3 COMMAND_SEND_DATA
- 8.2.3.4 COMMAND_SECTOR_ERASE
- 8.2.3.5 COMMAND_GET_STATUS
- 8.2.3.6 COMMAND_RESET
- 8.2.3.7 COMMAND_GET_CHIP_ID
- 8.2.3.8 COMMAND_CRC32
- 8.2.3.9 COMMAND_BANK_ERASE
- 8.2.3.10 COMMAND_MEMORY_READ
- 8.2.3.11 COMMAND_MEMORY_WRITE
- 8.2.3.12 COMMAND_SET_CCFG
- 9 Device Configuration
- 9.1 Customer Configuration (CCFG)
- 9.1.1 CCFG Registers
- 9.1.1.1 EXT_LF_CLK Register (Offset = FA8h) [reset = FFFFFFFFh]
- 9.1.1.2 MODE_CONF_1 Register (Offset = FACh) [reset = FFFBFFFFh]
- 9.1.1.3 SIZE_AND_DIS_FLAGS Register (Offset = FB0h) [reset = FFFFFFFFh]
- 9.1.1.4 MODE_CONF Register (Offset = FB4h) [reset = FFFFFFFFh]
- 9.1.1.5 VOLT_LOAD_0 Register (Offset = FB8h) [reset = FFFFFFFFh]
- 9.1.1.6 VOLT_LOAD_1 Register (Offset = FBCh) [reset = FFFFFFFFh]
- 9.1.1.7 RTC_OFFSET Register (Offset = FC0h) [reset = FFFFFFFFh]
- 9.1.1.8 FREQ_OFFSET Register (Offset = FC4h) [reset = FFFFFFFFh]
- 9.1.1.9 IEEE_MAC_0 Register (Offset = FC8h) [reset = FFFFFFFFh]
- 9.1.1.10 IEEE_MAC_1 Register (Offset = FCCh) [reset = FFFFFFFFh]
- 9.1.1.11 IEEE_BLE_0 Register (Offset = FD0h) [reset = FFFFFFFFh]
- 9.1.1.12 IEEE_BLE_1 Register (Offset = FD4h) [reset = FFFFFFFFh]
- 9.1.1.13 BL_CONFIG Register (Offset = FD8h) [reset = C5FFFFFFh]
- 9.1.1.14 ERASE_CONF Register (Offset = FDCh) [reset = FFFFFFFFh]
- 9.1.1.15 CCFG_TI_OPTIONS Register (Offset = FE0h) [reset = FFFFFFC5h]
- 9.1.1.16 CCFG_TAP_DAP_0 Register (Offset = FE4h) [reset = FFC5C5C5h]
- 9.1.1.17 CCFG_TAP_DAP_1 Register (Offset = FE8h) [reset = FFC5C5C5h]
- 9.1.1.18 IMAGE_VALID_CONF Register (Offset = FECh) [reset = FFFFFFFFh]
- 9.1.1.19 CCFG_PROT_31_0 Register (Offset = FF0h) [reset = FFFFFFFFh]
- 9.1.1.20 CCFG_PROT_63_32 Register (Offset = FF4h) [reset = FFFFFFFFh]
- 9.1.1.21 CCFG_PROT_95_64 Register (Offset = FF8h) [reset = FFFFFFFFh]
- 9.1.1.22 CCFG_PROT_127_96 Register (Offset = FFCh) [reset = FFFFFFFFh]
- 9.1.1 CCFG Registers
- 9.2 Factory Configuration (FCFG)
- 9.2.1 CC13x0 Factory Configuration (FCFG) Registers
- 9.2.1.1 FCFG1 Registers
- 9.2.1.1.1 MISC_CONF_1 Register (Offset = A0h) [reset = X]
- 9.2.1.1.2 MISC_CONF_2 Register (Offset = A4h) [reset = X]
- 9.2.1.1.3 CONFIG_RF_FRONTEND_DIV5 Register (Offset = C4h) [reset = X]
- 9.2.1.1.4 CONFIG_RF_FRONTEND_DIV6 Register (Offset = C8h) [reset = X]
- 9.2.1.1.5 CONFIG_RF_FRONTEND_DIV10 Register (Offset = CCh) [reset = X]
- 9.2.1.1.6 CONFIG_RF_FRONTEND_DIV12 Register (Offset = D0h) [reset = X]
- 9.2.1.1.7 CONFIG_RF_FRONTEND_DIV15 Register (Offset = D4h) [reset = X]
- 9.2.1.1.8 CONFIG_RF_FRONTEND_DIV30 Register (Offset = D8h) [reset = X]
- 9.2.1.1.9 CONFIG_SYNTH_DIV5 Register (Offset = DCh) [reset = X]
- 9.2.1.1.10 CONFIG_SYNTH_DIV6 Register (Offset = E0h) [reset = X]
- 9.2.1.1.11 CONFIG_SYNTH_DIV10 Register (Offset = E4h) [reset = X]
- 9.2.1.1.12 CONFIG_SYNTH_DIV12 Register (Offset = E8h) [reset = X]
- 9.2.1.1.13 CONFIG_SYNTH_DIV15 Register (Offset = ECh) [reset = X]
- 9.2.1.1.14 CONFIG_SYNTH_DIV30 Register (Offset = F0h) [reset = X]
- 9.2.1.1.15 CONFIG_MISC_ADC_DIV5 Register (Offset = F4h) [reset = X]
- 9.2.1.1.16 CONFIG_MISC_ADC_DIV6 Register (Offset = F8h) [reset = X]
- 9.2.1.1.17 CONFIG_MISC_ADC_DIV10 Register (Offset = FCh) [reset = X]
- 9.2.1.1.18 CONFIG_MISC_ADC_DIV12 Register (Offset = 100h) [reset = X]
- 9.2.1.1.19 CONFIG_MISC_ADC_DIV15 Register (Offset = 104h) [reset = X]
- 9.2.1.1.20 CONFIG_MISC_ADC_DIV30 Register (Offset = 108h) [reset = X]
- 9.2.1.1.21 SHDW_DIE_ID_0 Register (Offset = 118h) [reset = X]
- 9.2.1.1.22 SHDW_DIE_ID_1 Register (Offset = 11Ch) [reset = X]
- 9.2.1.1.23 SHDW_DIE_ID_2 Register (Offset = 120h) [reset = X]
- 9.2.1.1.24 SHDW_DIE_ID_3 Register (Offset = 124h) [reset = X]
- 9.2.1.1.25 SHDW_OSC_BIAS_LDO_TRIM Register (Offset = 138h) [reset = X]
- 9.2.1.1.26 SHDW_ANA_TRIM Register (Offset = 13Ch) [reset = X]
- 9.2.1.1.27 FLASH_NUMBER Register (Offset = 164h) [reset = X]
- 9.2.1.1.28 FLASH_COORDINATE Register (Offset = 16Ch) [reset = X]
- 9.2.1.1.29 FLASH_E_P Register (Offset = 170h) [reset = 17331A33h]
- 9.2.1.1.30 FLASH_C_E_P_R Register (Offset = 174h) [reset = 0A0A2000h]
- 9.2.1.1.31 FLASH_P_R_PV Register (Offset = 178h) [reset = 026E0200h]
- 9.2.1.1.32 FLASH_EH_SEQ Register (Offset = 17Ch) [reset = 0200F000h]
- 9.2.1.1.33 FLASH_VHV_E Register (Offset = 180h) [reset = 1h]
- 9.2.1.1.34 FLASH_PP Register (Offset = 184h) [reset = X]
- 9.2.1.1.35 FLASH_PROG_EP Register (Offset = 188h) [reset = 0FA00010h]
- 9.2.1.1.36 FLASH_ERA_PW Register (Offset = 18Ch) [reset = FA0h]
- 9.2.1.1.37 FLASH_VHV Register (Offset = 190h) [reset = X]
- 9.2.1.1.38 FLASH_VHV_PV Register (Offset = 194h) [reset = X]
- 9.2.1.1.39 FLASH_V Register (Offset = 198h) [reset = X]
- 9.2.1.1.40 USER_ID Register (Offset = 294h) [reset = X]
- 9.2.1.1.41 FLASH_OTP_DATA3 Register (Offset = 2B0h) [reset = X]
- 9.2.1.1.42 ANA2_TRIM Register (Offset = 2B4h) [reset = X]
- 9.2.1.1.43 LDO_TRIM Register (Offset = 2B8h) [reset = X]
- 9.2.1.1.44 BAT_RC_LDO_TRIM Register (Offset = 2BCh) [reset = X]
- 9.2.1.1.45 MAC_BLE_0 Register (Offset = 2E8h) [reset = X]
- 9.2.1.1.46 MAC_BLE_1 Register (Offset = 2ECh) [reset = X]
- 9.2.1.1.47 MAC_15_4_0 Register (Offset = 2F0h) [reset = X]
- 9.2.1.1.48 MAC_15_4_1 Register (Offset = 2F4h) [reset = X]
- 9.2.1.1.49 FLASH_OTP_DATA4 Register (Offset = 308h) [reset = 98989F9Fh]
- 9.2.1.1.50 MISC_TRIM Register (Offset = 30Ch) [reset = FFFFFF33h]
- 9.2.1.1.51 RCOSC_HF_TEMPCOMP Register (Offset = 310h) [reset = 3h]
- 9.2.1.1.52 TRIM_CAL_REVISION Register (Offset = 314h) [reset = X]
- 9.2.1.1.53 ICEPICK_DEVICE_ID Register (Offset = 318h) [reset = 2B9BE02Fh]
- 9.2.1.1.54 FCFG1_REVISION Register (Offset = 31Ch) [reset = 26h]
- 9.2.1.1.55 MISC_OTP_DATA Register (Offset = 320h) [reset = X]
- 9.2.1.1.56 IOCONF Register (Offset = 344h) [reset = X]
- 9.2.1.1.57 CONFIG_IF_ADC Register (Offset = 34Ch) [reset = X]
- 9.2.1.1.58 CONFIG_OSC_TOP Register (Offset = 350h) [reset = X]
- 9.2.1.1.59 CONFIG_RF_FRONTEND Register (Offset = 354h) [reset = X]
- 9.2.1.1.60 CONFIG_SYNTH Register (Offset = 358h) [reset = X]
- 9.2.1.1.61 SOC_ADC_ABS_GAIN Register (Offset = 35Ch) [reset = X]
- 9.2.1.1.62 SOC_ADC_REL_GAIN Register (Offset = 360h) [reset = X]
- 9.2.1.1.63 SOC_ADC_OFFSET_INT Register (Offset = 368h) [reset = X]
- 9.2.1.1.64 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register (Offset = 36Ch) [reset = X]
- 9.2.1.1.65 AMPCOMP_TH1 Register (Offset = 370h) [reset = FF7B828Eh]
- 9.2.1.1.66 AMPCOMP_TH2 Register (Offset = 374h) [reset = 6B8B0303h]
- 9.2.1.1.67 AMPCOMP_CTRL1 Register (Offset = 378h) [reset = FF183F47h]
- 9.2.1.1.68 ANABYPASS_VALUE2 Register (Offset = 37Ch) [reset = FFFFC3FFh]
- 9.2.1.1.69 CONFIG_MISC_ADC Register (Offset = 380h) [reset = X]
- 9.2.1.1.70 VOLT_TRIM Register (Offset = 388h) [reset = X]
- 9.2.1.1.71 OSC_CONF Register (Offset = 38Ch) [reset = X]
- 9.2.1.1.72 FREQ_OFFSET Register (Offset = 390h) [reset = X]
- 9.2.1.1.73 CAP_TRIM Register (Offset = 394h) [reset = FFFFFFFFh]
- 9.2.1.1.74 MISC_OTP_DATA_1 Register (Offset = 398h) [reset = E00403F8h]
- 9.2.1.1.75 PWD_CURR_20C Register (Offset = 39Ch) [reset = 080BA608h]
- 9.2.1.1.76 PWD_CURR_35C Register (Offset = 3A0h) [reset = 0C10A50Ah]
- 9.2.1.1.77 PWD_CURR_50C Register (Offset = 3A4h) [reset = 1218A20Dh]
- 9.2.1.1.78 PWD_CURR_65C Register (Offset = 3A8h) [reset = 1C259C14h]
- 9.2.1.1.79 PWD_CURR_80C Register (Offset = 3ACh) [reset = 2E3B9021h]
- 9.2.1.1.80 PWD_CURR_95C Register (Offset = 3B0h) [reset = 4C627A3Bh]
- 9.2.1.1.81 PWD_CURR_110C Register (Offset = 3B4h) [reset = 789E706Bh]
- 9.2.1.1.82 PWD_CURR_125C Register (Offset = 3B8h) [reset = ADE1809Ah]
- 9.2.1.1 FCFG1 Registers
- 9.2.2 CC26xx Factory Configuration (FCFG) Registers
- 9.2.2.1 FCFG1 Registers
- 9.2.2.1.1 MISC_CONF_1 Register (Offset = A0h) [reset = X]
- 9.2.2.1.2 MISC_CONF_2 Register (Offset = A4h) [reset = X]
- 9.2.2.1.3 CONFIG_RF_FRONTEND_DIV5 Register (Offset = C4h) [reset = FFFFFFFFh]
- 9.2.2.1.4 CONFIG_RF_FRONTEND_DIV6 Register (Offset = C8h) [reset = FFFFFFFFh]
- 9.2.2.1.5 CONFIG_RF_FRONTEND_DIV10 Register (Offset = CCh) [reset = FFFFFFFFh]
- 9.2.2.1.6 CONFIG_RF_FRONTEND_DIV12 Register (Offset = D0h) [reset = FFFFFFFFh]
- 9.2.2.1.7 CONFIG_RF_FRONTEND_DIV15 Register (Offset = D4h) [reset = FFFFFFFFh]
- 9.2.2.1.8 CONFIG_RF_FRONTEND_DIV30 Register (Offset = D8h) [reset = FFFFFFFFh]
- 9.2.2.1.9 CONFIG_SYNTH_DIV5 Register (Offset = DCh) [reset = FFFFFFFFh]
- 9.2.2.1.10 CONFIG_SYNTH_DIV6 Register (Offset = E0h) [reset = FFFFFFFFh]
- 9.2.2.1.11 CONFIG_SYNTH_DIV10 Register (Offset = E4h) [reset = FFFFFFFFh]
- 9.2.2.1.12 CONFIG_SYNTH_DIV12 Register (Offset = E8h) [reset = FFFFFFFFh]
- 9.2.2.1.13 CONFIG_SYNTH_DIV15 Register (Offset = ECh) [reset = FFFFFFFFh]
- 9.2.2.1.14 CONFIG_SYNTH_DIV30 Register (Offset = F0h) [reset = FFFFFFFFh]
- 9.2.2.1.15 CONFIG_MISC_ADC_DIV5 Register (Offset = F4h) [reset = FFFFFFFFh]
- 9.2.2.1.16 CONFIG_MISC_ADC_DIV6 Register (Offset = F8h) [reset = FFFFFFFFh]
- 9.2.2.1.17 CONFIG_MISC_ADC_DIV10 Register (Offset = FCh) [reset = FFFFFFFFh]
- 9.2.2.1.18 CONFIG_MISC_ADC_DIV12 Register (Offset = 100h) [reset = FFFFFFFFh]
- 9.2.2.1.19 CONFIG_MISC_ADC_DIV15 Register (Offset = 104h) [reset = FFFFFFFFh]
- 9.2.2.1.20 CONFIG_MISC_ADC_DIV30 Register (Offset = 108h) [reset = FFFFFFFFh]
- 9.2.2.1.21 SHDW_DIE_ID_0 Register (Offset = 118h) [reset = X]
- 9.2.2.1.22 SHDW_DIE_ID_1 Register (Offset = 11Ch) [reset = X]
- 9.2.2.1.23 SHDW_DIE_ID_2 Register (Offset = 120h) [reset = X]
- 9.2.2.1.24 SHDW_DIE_ID_3 Register (Offset = 124h) [reset = X]
- 9.2.2.1.25 SHDW_OSC_BIAS_LDO_TRIM Register (Offset = 138h) [reset = X]
- 9.2.2.1.26 SHDW_ANA_TRIM Register (Offset = 13Ch) [reset = X]
- 9.2.2.1.27 FLASH_NUMBER Register (Offset = 164h) [reset = X]
- 9.2.2.1.28 FLASH_COORDINATE Register (Offset = 16Ch) [reset = X]
- 9.2.2.1.29 FLASH_E_P Register (Offset = 170h) [reset = 17331A33h]
- 9.2.2.1.30 FLASH_C_E_P_R Register (Offset = 174h) [reset = 0A0A2000h]
- 9.2.2.1.31 FLASH_P_R_PV Register (Offset = 178h) [reset = 026E0200h]
- 9.2.2.1.32 FLASH_EH_SEQ Register (Offset = 17Ch) [reset = 0200F000h]
- 9.2.2.1.33 FLASH_VHV_E Register (Offset = 180h) [reset = 1h]
- 9.2.2.1.34 FLASH_PP Register (Offset = 184h) [reset = X]
- 9.2.2.1.35 FLASH_PROG_EP Register (Offset = 188h) [reset = 0FA00010h]
- 9.2.2.1.36 FLASH_ERA_PW Register (Offset = 18Ch) [reset = FA0h]
- 9.2.2.1.37 FLASH_VHV Register (Offset = 190h) [reset = X]
- 9.2.2.1.38 FLASH_VHV_PV Register (Offset = 194h) [reset = X]
- 9.2.2.1.39 FLASH_V Register (Offset = 198h) [reset = X]
- 9.2.2.1.40 USER_ID Register (Offset = 294h) [reset = X]
- 9.2.2.1.41 FLASH_OTP_DATA3 Register (Offset = 2B0h) [reset = X]
- 9.2.2.1.42 ANA2_TRIM Register (Offset = 2B4h) [reset = X]
- 9.2.2.1.43 LDO_TRIM Register (Offset = 2B8h) [reset = X]
- 9.2.2.1.44 BAT_RC_LDO_TRIM Register (Offset = 2BCh) [reset = X]
- 9.2.2.1.45 MAC_BLE_0 Register (Offset = 2E8h) [reset = X]
- 9.2.2.1.46 MAC_BLE_1 Register (Offset = 2ECh) [reset = X]
- 9.2.2.1.47 MAC_15_4_0 Register (Offset = 2F0h) [reset = X]
- 9.2.2.1.48 MAC_15_4_1 Register (Offset = 2F4h) [reset = X]
- 9.2.2.1.49 FLASH_OTP_DATA4 Register (Offset = 308h) [reset = 98989F9Fh]
- 9.2.2.1.50 MISC_TRIM Register (Offset = 30Ch) [reset = FFFFFF33h]
- 9.2.2.1.51 RCOSC_HF_TEMPCOMP Register (Offset = 310h) [reset = 3h]
- 9.2.2.1.52 TRIM_CAL_REVISION Register (Offset = 314h) [reset = X]
- 9.2.2.1.53 ICEPICK_DEVICE_ID Register (Offset = 318h) [reset = 8B99A02Fh]
- 9.2.2.1.54 FCFG1_REVISION Register (Offset = 31Ch) [reset = 25h]
- 9.2.2.1.55 MISC_OTP_DATA Register (Offset = 320h) [reset = X]
- 9.2.2.1.56 IOCONF Register (Offset = 344h) [reset = X]
- 9.2.2.1.57 CONFIG_IF_ADC Register (Offset = 34Ch) [reset = X]
- 9.2.2.1.58 CONFIG_OSC_TOP Register (Offset = 350h) [reset = X]
- 9.2.2.1.59 CONFIG_RF_FRONTEND Register (Offset = 354h) [reset = X]
- 9.2.2.1.60 CONFIG_SYNTH Register (Offset = 358h) [reset = X]
- 9.2.2.1.61 SOC_ADC_ABS_GAIN Register (Offset = 35Ch) [reset = X]
- 9.2.2.1.62 SOC_ADC_REL_GAIN Register (Offset = 360h) [reset = X]
- 9.2.2.1.63 SOC_ADC_OFFSET_INT Register (Offset = 368h) [reset = X]
- 9.2.2.1.64 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register (Offset = 36Ch) [reset = X]
- 9.2.2.1.65 AMPCOMP_TH1 Register (Offset = 370h) [reset = FF7B828Eh]
- 9.2.2.1.66 AMPCOMP_TH2 Register (Offset = 374h) [reset = 6B8B0303h]
- 9.2.2.1.67 AMPCOMP_CTRL1 Register (Offset = 378h) [reset = FF183F47h]
- 9.2.2.1.68 ANABYPASS_VALUE2 Register (Offset = 37Ch) [reset = FFFFC3FFh]
- 9.2.2.1.69 CONFIG_MISC_ADC Register (Offset = 380h) [reset = X]
- 9.2.2.1.70 VOLT_TRIM Register (Offset = 388h) [reset = X]
- 9.2.2.1.71 OSC_CONF Register (Offset = 38Ch) [reset = X]
- 9.2.2.1.72 FREQ_OFFSET Register (Offset = 390h) [reset = X]
- 9.2.2.1.73 CAP_TRIM Register (Offset = 394h) [reset = FFFFFFFFh]
- 9.2.2.1.74 MISC_OTP_DATA_1 Register (Offset = 398h) [reset = E00403F8h]
- 9.2.2.1.75 PWD_CURR_20C Register (Offset = 39Ch) [reset = 080BA608h]
- 9.2.2.1.76 PWD_CURR_35C Register (Offset = 3A0h) [reset = 0C10A50Ah]
- 9.2.2.1.77 PWD_CURR_50C Register (Offset = 3A4h) [reset = 1218A20Dh]
- 9.2.2.1.78 PWD_CURR_65C Register (Offset = 3A8h) [reset = 1C259C14h]
- 9.2.2.1.79 PWD_CURR_80C Register (Offset = 3ACh) [reset = 2E3B9021h]
- 9.2.2.1.80 PWD_CURR_95C Register (Offset = 3B0h) [reset = 4C627A3Bh]
- 9.2.2.1.81 PWD_CURR_110C Register (Offset = 3B4h) [reset = 789E706Bh]
- 9.2.2.1.82 PWD_CURR_125C Register (Offset = 3B8h) [reset = ADE1809Ah]
- 9.2.2.1 FCFG1 Registers
- 9.2.1 CC13x0 Factory Configuration (FCFG) Registers
- 9.1 Customer Configuration (CCFG)
- 10 Cryptography
- 10.1 AES Cryptoprocessor Overview
- 10.2 Functional Description
- 10.3 Power Management and Sleep Modes
- 10.4 Hardware Description
- 10.5 Module Description
- 10.6 Performance
- 10.7 Programming Guidelines
- 10.8 Conventions and Compliances
- 10.9 Cryptography Registers
- 10.9.1 CRYPTO Registers
- 10.9.1.1 DMACH0CTL Register (Offset = 0h) [reset = 0h]
- 10.9.1.2 DMACH0EXTADDR Register (Offset = 4h) [reset = 0h]
- 10.9.1.3 DMACH0LEN Register (Offset = Ch) [reset = 0h]
- 10.9.1.4 DMASTAT Register (Offset = 18h) [reset = 0h]
- 10.9.1.5 DMASWRESET Register (Offset = 1Ch) [reset = 0h]
- 10.9.1.6 DMACH1CTL Register (Offset = 20h) [reset = 0h]
- 10.9.1.7 DMACH1EXTADDR Register (Offset = 24h) [reset = 0h]
- 10.9.1.8 DMACH1LEN Register (Offset = 2Ch) [reset = 0h]
- 10.9.1.9 DMABUSCFG Register (Offset = 78h) [reset = 2400h]
- 10.9.1.10 DMAPORTERR Register (Offset = 7Ch) [reset = 0h]
- 10.9.1.11 DMAHWVER Register (Offset = FCh) [reset = 01012ED1h]
- 10.9.1.12 KEYWRITEAREA Register (Offset = 400h) [reset = 0h]
- 10.9.1.13 KEYWRITTENAREA Register (Offset = 404h) [reset = 0h]
- 10.9.1.14 KEYSIZE Register (Offset = 408h) [reset = 1h]
- 10.9.1.15 KEYREADAREA Register (Offset = 40Ch) [reset = 8h]
- 10.9.1.16 AESKEY2_0 to AESKEY2_3 Register (Offset = 500h to 50Ch) [reset = 0h]
- 10.9.1.17 AESKEY3_0 to AESKEY3_3 Register (Offset = 510h to 51Ch) [reset = 0h]
- 10.9.1.18 AESIV_0 to AESIV_3 Register (Offset = 540h to 54Ch) [reset = 0h]
- 10.9.1.19 AESCTL Register (Offset = 550h) [reset = 80000000h]
- 10.9.1.20 AESDATALEN0 Register (Offset = 554h) [reset = 0h]
- 10.9.1.21 AESDATALEN1 Register (Offset = 558h) [reset = 0h]
- 10.9.1.22 AESAUTHLEN Register (Offset = 55Ch) [reset = 0h]
- 10.9.1.23 AESDATAOUT0 Register (Offset = 560h) [reset = 0h]
- 10.9.1.24 AESDATAIN0 Register (Offset = 560h) [reset = 0h]
- 10.9.1.25 AESDATAOUT1 Register (Offset = 564h) [reset = 0h]
- 10.9.1.26 AESDATAIN1 Register (Offset = 564h) [reset = 0h]
- 10.9.1.27 AESDATAOUT2 Register (Offset = 568h) [reset = 0h]
- 10.9.1.28 AESDATAIN2 Register (Offset = 568h) [reset = 0h]
- 10.9.1.29 AESDATAOUT3 Register (Offset = 56Ch) [reset = 0h]
- 10.9.1.30 AESDATAIN3 Register (Offset = 56Ch) [reset = 0h]
- 10.9.1.31 AESTAGOUT_0 to AESTAGOUT_3 Register (Offset = 570h to 57Ch) [reset = 0h]
- 10.9.1.32 ALGSEL Register (Offset = 700h) [reset = 0h]
- 10.9.1.33 DMAPROTCTL Register (Offset = 704h) [reset = 0h]
- 10.9.1.34 SWRESET Register (Offset = 740h) [reset = 0h]
- 10.9.1.35 IRQTYPE Register (Offset = 780h) [reset = 0h]
- 10.9.1.36 IRQEN Register (Offset = 784h) [reset = 0h]
- 10.9.1.37 IRQCLR Register (Offset = 788h) [reset = 0h]
- 10.9.1.38 IRQSET Register (Offset = 78Ch) [reset = 0h]
- 10.9.1.39 IRQSTAT Register (Offset = 790h) [reset = 0h]
- 10.9.1.40 HWVER Register (Offset = 7FCh) [reset = 91118778h]
- 10.9.1 CRYPTO Registers
- 11 I/O Control
- 11.1 Introduction
- 11.2 IOC Overview
- 11.3 I/O Mapping and Configuration
- 11.4 Edge Detection on Pin (DIO)
- 11.5 AON IOC State Latching When Powering Off the MCU Domain
- 11.6 Unused I/O Pins
- 11.7 GPIO
- 11.8 I/O Pin Mapping
- 11.9 Peripheral PORTIDs
- 11.10 I/O Pins
- 11.11 I/O Control Registers
- 11.11.1 AON_IOC Registers
- 11.11.2 GPIO Registers
- 11.11.2.1 DOUT3_0 Register (Offset = 0h) [reset = 0h]
- 11.11.2.2 DOUT7_4 Register (Offset = 4h) [reset = 0h]
- 11.11.2.3 DOUT11_8 Register (Offset = 8h) [reset = 0h]
- 11.11.2.4 DOUT15_12 Register (Offset = Ch) [reset = 0h]
- 11.11.2.5 DOUT19_16 Register (Offset = 10h) [reset = 0h]
- 11.11.2.6 DOUT23_20 Register (Offset = 14h) [reset = 0h]
- 11.11.2.7 DOUT27_24 Register (Offset = 18h) [reset = 0h]
- 11.11.2.8 DOUT31_28 Register (Offset = 1Ch) [reset = 0h]
- 11.11.2.9 DOUT31_0 Register (Offset = 80h) [reset = 0h]
- 11.11.2.10 DOUTSET31_0 Register (Offset = 90h) [reset = 0h]
- 11.11.2.11 DOUTCLR31_0 Register (Offset = A0h) [reset = 0h]
- 11.11.2.12 DOUTTGL31_0 Register (Offset = B0h) [reset = 0h]
- 11.11.2.13 DIN31_0 Register (Offset = C0h) [reset = 0h]
- 11.11.2.14 DOE31_0 Register (Offset = D0h) [reset = 0h]
- 11.11.2.15 EVFLAGS31_0 Register (Offset = E0h) [reset = 0h]
- 11.11.3 IOC Registers
- 11.11.3.1 IOCFG0 Register (Offset = 0h) [reset = 6000h]
- 11.11.3.2 IOCFG1 Register (Offset = 4h) [reset = 6000h]
- 11.11.3.3 IOCFG2 Register (Offset = 8h) [reset = 6000h]
- 11.11.3.4 IOCFG3 Register (Offset = Ch) [reset = 6000h]
- 11.11.3.5 IOCFG4 Register (Offset = 10h) [reset = 6000h]
- 11.11.3.6 IOCFG5 Register (Offset = 14h) [reset = 6000h]
- 11.11.3.7 IOCFG6 Register (Offset = 18h) [reset = 6000h]
- 11.11.3.8 IOCFG7 Register (Offset = 1Ch) [reset = 6000h]
- 11.11.3.9 IOCFG8 Register (Offset = 20h) [reset = 6000h]
- 11.11.3.10 IOCFG9 Register (Offset = 24h) [reset = 6000h]
- 11.11.3.11 IOCFG10 Register (Offset = 28h) [reset = 6000h]
- 11.11.3.12 IOCFG11 Register (Offset = 2Ch) [reset = 6000h]
- 11.11.3.13 IOCFG12 Register (Offset = 30h) [reset = 6000h]
- 11.11.3.14 IOCFG13 Register (Offset = 34h) [reset = 6000h]
- 11.11.3.15 IOCFG14 Register (Offset = 38h) [reset = 6000h]
- 11.11.3.16 IOCFG15 Register (Offset = 3Ch) [reset = 6000h]
- 11.11.3.17 IOCFG16 Register (Offset = 40h) [reset = 00086000h]
- 11.11.3.18 IOCFG17 Register (Offset = 44h) [reset = 00106000h]
- 11.11.3.19 IOCFG18 Register (Offset = 48h) [reset = 6000h]
- 11.11.3.20 IOCFG19 Register (Offset = 4Ch) [reset = 6000h]
- 11.11.3.21 IOCFG20 Register (Offset = 50h) [reset = 6000h]
- 11.11.3.22 IOCFG21 Register (Offset = 54h) [reset = 6000h]
- 11.11.3.23 IOCFG22 Register (Offset = 58h) [reset = 6000h]
- 11.11.3.24 IOCFG23 Register (Offset = 5Ch) [reset = 6000h]
- 11.11.3.25 IOCFG24 Register (Offset = 60h) [reset = 6000h]
- 11.11.3.26 IOCFG25 Register (Offset = 64h) [reset = 6000h]
- 11.11.3.27 IOCFG26 Register (Offset = 68h) [reset = 6000h]
- 11.11.3.28 IOCFG27 Register (Offset = 6Ch) [reset = 6000h]
- 11.11.3.29 IOCFG28 Register (Offset = 70h) [reset = 6000h]
- 11.11.3.30 IOCFG29 Register (Offset = 74h) [reset = 6000h]
- 11.11.3.31 IOCFG30 Register (Offset = 78h) [reset = 6000h]
- 11.11.3.32 IOCFG31 Register (Offset = 7Ch) [reset = 6000h]
- 12 Micro Direct Memory Access (µDMA)
- 12.1 μDMA Introduction
- 12.2 Block Diagram
- 12.3 Functional Description
- 12.4 Initialization and Configuration
- 12.5 µDMA Registers
- 12.5.1 UDMA Registers
- 12.5.1.1 STATUS Register (Offset = 0h) [reset = 001F0000h]
- 12.5.1.2 CFG Register (Offset = 4h) [reset = 0h]
- 12.5.1.3 CTRL Register (Offset = 8h) [reset = 0h]
- 12.5.1.4 ALTCTRL Register (Offset = Ch) [reset = 200h]
- 12.5.1.5 WAITONREQ Register (Offset = 10h) [reset = FFFF1EFFh]
- 12.5.1.6 SOFTREQ Register (Offset = 14h) [reset = 0h]
- 12.5.1.7 SETBURST Register (Offset = 18h) [reset = 0h]
- 12.5.1.8 CLEARBURST Register (Offset = 1Ch) [reset = 0h]
- 12.5.1.9 SETREQMASK Register (Offset = 20h) [reset = 0h]
- 12.5.1.10 CLEARREQMASK Register (Offset = 24h) [reset = 0h]
- 12.5.1.11 SETCHANNELEN Register (Offset = 28h) [reset = 0h]
- 12.5.1.12 CLEARCHANNELEN Register (Offset = 2Ch) [reset = 0h]
- 12.5.1.13 SETCHNLPRIALT Register (Offset = 30h) [reset = 0h]
- 12.5.1.14 CLEARCHNLPRIALT Register (Offset = 34h) [reset = 0h]
- 12.5.1.15 SETCHNLPRIORITY Register (Offset = 38h) [reset = 0h]
- 12.5.1.16 CLEARCHNLPRIORITY Register (Offset = 3Ch) [reset = 0h]
- 12.5.1.17 ERROR Register (Offset = 4Ch) [reset = 0h]
- 12.5.1.18 REQDONE Register (Offset = 504h) [reset = 0h]
- 12.5.1.19 DONEMASK Register (Offset = 520h) [reset = 0h]
- 12.5.1 UDMA Registers
- 13 Timers
- 13.1 General-Purpose Timers
- 13.2 Block Diagram
- 13.3 Functional Description
- 13.4 Initialization and Configuration
- 13.5 General-Purpose Timer Registers
- 13.5.1 GPT Registers
- 13.5.1.1 CFG Register (Offset = 0h) [reset = 0h]
- 13.5.1.2 TAMR Register (Offset = 4h) [reset = 0h]
- 13.5.1.3 TBMR Register (Offset = 8h) [reset = 0h]
- 13.5.1.4 CTL Register (Offset = Ch) [reset = 0h]
- 13.5.1.5 SYNC Register (Offset = 10h) [reset = 0h]
- 13.5.1.6 IMR Register (Offset = 18h) [reset = 0h]
- 13.5.1.7 RIS Register (Offset = 1Ch) [reset = 0h]
- 13.5.1.8 MIS Register (Offset = 20h) [reset = 0h]
- 13.5.1.9 ICLR Register (Offset = 24h) [reset = 0h]
- 13.5.1.10 TAILR Register (Offset = 28h) [reset = FFFFFFFFh]
- 13.5.1.11 TBILR Register (Offset = 2Ch) [reset = FFFFh]
- 13.5.1.12 TAMATCHR Register (Offset = 30h) [reset = FFFFFFFFh]
- 13.5.1.13 TBMATCHR Register (Offset = 34h) [reset = FFFFh]
- 13.5.1.14 TAPR Register (Offset = 38h) [reset = 0h]
- 13.5.1.15 TBPR Register (Offset = 3Ch) [reset = 0h]
- 13.5.1.16 TAPMR Register (Offset = 40h) [reset = 0h]
- 13.5.1.17 TBPMR Register (Offset = 44h) [reset = 0h]
- 13.5.1.18 TAR Register (Offset = 48h) [reset = FFFFFFFFh]
- 13.5.1.19 TBR Register (Offset = 4Ch) [reset = FFFFh]
- 13.5.1.20 TAV Register (Offset = 50h) [reset = FFFFFFFFh]
- 13.5.1.21 TBV Register (Offset = 54h) [reset = FFFFh]
- 13.5.1.22 TAPS Register (Offset = 5Ch) [reset = 0h]
- 13.5.1.23 TBPS Register (Offset = 60h) [reset = 0h]
- 13.5.1.24 TAPV Register (Offset = 64h) [reset = 0h]
- 13.5.1.25 TBPV Register (Offset = 68h) [reset = 0h]
- 13.5.1.26 DMAEV Register (Offset = 6Ch) [reset = 0h]
- 13.5.1.27 VERSION Register (Offset = FB0h) [reset = 400h]
- 13.5.1.28 ANDCCP Register (Offset = FB4h) [reset = 0h]
- 13.5.1 GPT Registers
- 14 Real-Time Clock
- 14.1 Introduction
- 14.2 Functional Specifications
- 14.3 RTC Registers
- 14.4 Real-Time Clock Registers
- 14.4.1 AON_RTC Registers
- 14.4.1.1 CTL Register (Offset = 0h) [reset = 0h]
- 14.4.1.2 EVFLAGS Register (Offset = 4h) [reset = 0h]
- 14.4.1.3 SEC Register (Offset = 8h) [reset = 0h]
- 14.4.1.4 SUBSEC Register (Offset = Ch) [reset = 0h]
- 14.4.1.5 SUBSECINC Register (Offset = 10h) [reset = 00800000h]
- 14.4.1.6 CHCTL Register (Offset = 14h) [reset = 0h]
- 14.4.1.7 CH0CMP Register (Offset = 18h) [reset = 0h]
- 14.4.1.8 CH1CMP Register (Offset = 1Ch) [reset = 0h]
- 14.4.1.9 CH2CMP Register (Offset = 20h) [reset = 0h]
- 14.4.1.10 CH2CMPINC Register (Offset = 24h) [reset = 0h]
- 14.4.1.11 CH1CAPT Register (Offset = 28h) [reset = 0h]
- 14.4.1.12 SYNC Register (Offset = 2Ch) [reset = 0h]
- 14.4.1 AON_RTC Registers
- 15 Watchdog Timer
- 15.1 WDT Introduction
- 15.2 WDT Functional Description
- 15.3 WDT Initialization and Configuration
- 15.4 Watchdog Timer Registers
- 15.4.1 WDT Registers
- 15.4.1.1 LOAD Register (Offset = 0h) [reset = FFFFFFFFh]
- 15.4.1.2 VALUE Register (Offset = 4h) [reset = FFFFFFFFh]
- 15.4.1.3 CTL Register (Offset = 8h) [reset = 0h]
- 15.4.1.4 ICR Register (Offset = Ch) [reset = 0h]
- 15.4.1.5 RIS Register (Offset = 10h) [reset = 0h]
- 15.4.1.6 MIS Register (Offset = 14h) [reset = 0h]
- 15.4.1.7 TEST Register (Offset = 418h) [reset = 0h]
- 15.4.1.8 INT_CAUS Register (Offset = 41Ch) [reset = 0h]
- 15.4.1.9 LOCK Register (Offset = C00h) [reset = 0h]
- 15.4.1 WDT Registers
- 16 Random Number Generator
- 16.1 Overview
- 16.2 Block Diagram
- 16.3 TRNG Software Reset
- 16.4 Interrupt Requests
- 16.5 TRNG Operation Description
- 16.6 TRNG Low-Level Programing Guide
- 16.7 Random Number Generator Registers
- 16.7.1 TRNG Registers
- 16.7.1.1 OUT0 Register (Offset = 0h) [reset = 0h]
- 16.7.1.2 OUT1 Register (Offset = 4h) [reset = 0h]
- 16.7.1.3 IRQFLAGSTAT Register (Offset = 8h) [reset = 0h]
- 16.7.1.4 IRQFLAGMASK Register (Offset = Ch) [reset = 0h]
- 16.7.1.5 IRQFLAGCLR Register (Offset = 10h) [reset = 0h]
- 16.7.1.6 CTL Register (Offset = 14h) [reset = 0h]
- 16.7.1.7 CFG0 Register (Offset = 18h) [reset = 0h]
- 16.7.1.8 ALARMCNT Register (Offset = 1Ch) [reset = FFh]
- 16.7.1.9 FROEN Register (Offset = 20h) [reset = 00FFFFFFh]
- 16.7.1.10 FRODETUNE Register (Offset = 24h) [reset = 0h]
- 16.7.1.11 ALARMMASK Register (Offset = 28h) [reset = 0h]
- 16.7.1.12 ALARMSTOP Register (Offset = 2Ch) [reset = 0h]
- 16.7.1.13 LFSR0 Register (Offset = 30h) [reset = 0h]
- 16.7.1.14 LFSR1 Register (Offset = 34h) [reset = 0h]
- 16.7.1.15 LFSR2 Register (Offset = 38h) [reset = 0h]
- 16.7.1.16 HWOPT Register (Offset = 78h) [reset = 600h]
- 16.7.1.17 HWVER0 Register (Offset = 7Ch) [reset = 0200B44Bh]
- 16.7.1.18 IRQSTATMASK Register (Offset = 1FD8h) [reset = 0h]
- 16.7.1.19 HWVER1 Register (Offset = 1FE0h) [reset = 20h]
- 16.7.1.20 IRQSET Register (Offset = 1FECh) [reset = 0h]
- 16.7.1.21 SWRESET Register (Offset = 1FF0h) [reset = 0h]
- 16.7.1.22 IRQSTAT Register (Offset = 1FF8h) [reset = 0h]
- 16.7.1 TRNG Registers
- 17 AUX – Sensor Controller with Digital and Analog Peripherals
- 17.1 Introduction
- 17.2 Memory Mapping
- 17.3 I/O Mapping
- 17.4 Modules
- 17.4.1 Sensor Controller
- 17.4.2 GPIO Control
- 17.4.3 AUX Timers
- 17.4.4 Time-to-Digital Converter
- 17.4.5 Semaphores
- 17.4.6 Oscillator Configuration Interface (DDI)
- 17.4.7 Analog MUX
- 17.4.8 ADC
- 17.4.8.1 Introduction
- 17.4.8.2 ADC Reference
- 17.4.8.3 Sample Mode and Sample Duration
- 17.4.8.4 Input Signal Scaling
- 17.4.8.5 ADC Enable
- 17.4.8.6 Digital Core
- 17.4.8.7 ADC Core Clock
- 17.4.8.8 Sampling
- 17.4.8.9 FIFO
- 17.4.8.10 Interrupts and Events
- 17.4.8.11 DMA Usage
- 17.4.8.12 Usage Example—Single Shot ADC Measurement
- 17.5 Power Management
- 17.6 Clock Management
- 17.7 AUX – Sensor Controller Registers
- 17.7.1 ADI_4_AUX Registers
- 17.7.1.1 MUX0 Register (Offset = 0h) [reset = 0h]
- 17.7.1.2 MUX1 Register (Offset = 1h) [reset = 0h]
- 17.7.1.3 MUX2 Register (Offset = 2h) [reset = 0h]
- 17.7.1.4 MUX3 Register (Offset = 3h) [reset = 0h]
- 17.7.1.5 ISRC Register (Offset = 4h) [reset = 0h]
- 17.7.1.6 COMP Register (Offset = 5h) [reset = 0h]
- 17.7.1.7 MUX4 Register (Offset = 7h) [reset = 0h]
- 17.7.1.8 ADC0 Register (Offset = 8h) [reset = 0h]
- 17.7.1.9 ADC1 Register (Offset = 9h) [reset = 0h]
- 17.7.1.10 ADCREF0 Register (Offset = Ah) [reset = 0h]
- 17.7.1.11 ADCREF1 Register (Offset = Bh) [reset = 0h]
- 17.7.2 AUX_AIODIO Registers
- 17.7.2.1 GPIODOUT Register (Offset = 0h) [reset = 0h]
- 17.7.2.2 IOMODE Register (Offset = 4h) [reset = 0h]
- 17.7.2.3 GPIODIN Register (Offset = 8h) [reset = 0h]
- 17.7.2.4 GPIODOUTSET Register (Offset = Ch) [reset = 0h]
- 17.7.2.5 GPIODOUTCLR Register (Offset = 10h) [reset = 0h]
- 17.7.2.6 GPIODOUTTGL Register (Offset = 14h) [reset = 0h]
- 17.7.2.7 GPIODIE Register (Offset = 18h) [reset = 0h]
- 17.7.3 AUX_EVCTL Registers
- 17.7.3.1 VECCFG0 Register (Offset = 0h) [reset = 0h]
- 17.7.3.2 VECCFG1 Register (Offset = 4h) [reset = 0h]
- 17.7.3.3 SCEWEVSEL Register (Offset = 8h) [reset = 0h]
- 17.7.3.4 EVTOAONFLAGS Register (Offset = Ch) [reset = 0h]
- 17.7.3.5 EVTOAONPOL Register (Offset = 10h) [reset = 0h]
- 17.7.3.6 DMACTL Register (Offset = 14h) [reset = 0h]
- 17.7.3.7 SWEVSET Register (Offset = 18h) [reset = 0h]
- 17.7.3.8 EVSTAT0 Register (Offset = 1Ch) [reset = 0h]
- 17.7.3.9 EVSTAT1 Register (Offset = 20h) [reset = 0h]
- 17.7.3.10 EVTOMCUPOL Register (Offset = 24h) [reset = 0h]
- 17.7.3.11 EVTOMCUFLAGS Register (Offset = 28h) [reset = 0h]
- 17.7.3.12 COMBEVTOMCUMASK Register (Offset = 2Ch) [reset = 0h]
- 17.7.3.13 VECFLAGS Register (Offset = 34h) [reset = 0h]
- 17.7.3.14 EVTOMCUFLAGSCLR Register (Offset = 38h) [reset = 0h]
- 17.7.3.15 EVTOAONFLAGSCLR Register (Offset = 3Ch) [reset = 0h]
- 17.7.3.16 VECFLAGSCLR Register (Offset = 40h) [reset = 0h]
- 17.7.4 AUX_SMPH Registers
- 17.7.4.1 SMPH0 Register (Offset = 0h) [reset = 1h]
- 17.7.4.2 SMPH1 Register (Offset = 4h) [reset = 1h]
- 17.7.4.3 SMPH2 Register (Offset = 8h) [reset = 1h]
- 17.7.4.4 SMPH3 Register (Offset = Ch) [reset = 1h]
- 17.7.4.5 SMPH4 Register (Offset = 10h) [reset = 1h]
- 17.7.4.6 SMPH5 Register (Offset = 14h) [reset = 1h]
- 17.7.4.7 SMPH6 Register (Offset = 18h) [reset = 1h]
- 17.7.4.8 SMPH7 Register (Offset = 1Ch) [reset = 1h]
- 17.7.4.9 AUTOTAKE Register (Offset = 20h) [reset = 0h]
- 17.7.5 AUX_TDC Registers
- 17.7.5.1 CTL Register (Offset = 0h) [reset = 0h]
- 17.7.5.2 STAT Register (Offset = 4h) [reset = 6h]
- 17.7.5.3 RESULT Register (Offset = 8h) [reset = 2h]
- 17.7.5.4 SATCFG Register (Offset = Ch) [reset = Fh]
- 17.7.5.5 TRIGSRC Register (Offset = 10h) [reset = 0h]
- 17.7.5.6 TRIGCNT Register (Offset = 14h) [reset = 0h]
- 17.7.5.7 TRIGCNTLOAD Register (Offset = 18h) [reset = 0h]
- 17.7.5.8 TRIGCNTCFG Register (Offset = 1Ch) [reset = 0h]
- 17.7.5.9 PRECTL Register (Offset = 20h) [reset = 1Fh]
- 17.7.5.10 PRECNT Register (Offset = 24h) [reset = 0h]
- 17.7.6 AUX_TIMER Registers
- 17.7.6.1 T0CFG Register (Offset = 0h) [reset = 0h]
- 17.7.6.2 T1CFG Register (Offset = 4h) [reset = 0h]
- 17.7.6.3 T0CTL Register (Offset = 8h) [reset = 0h]
- 17.7.6.4 T0TARGET Register (Offset = Ch) [reset = 0h]
- 17.7.6.5 T1TARGET Register (Offset = 10h) [reset = 0h]
- 17.7.6.6 T1CTL Register (Offset = 14h) [reset = 0h]
- 17.7.7 AUX_WUC Registers
- 17.7.7.1 MODCLKEN0 Register (Offset = 0h) [reset = 0h]
- 17.7.7.2 PWROFFREQ Register (Offset = 4h) [reset = 0h]
- 17.7.7.3 PWRDWNREQ Register (Offset = 8h) [reset = 0h]
- 17.7.7.4 PWRDWNACK Register (Offset = Ch) [reset = 0h]
- 17.7.7.5 CLKLFREQ Register (Offset = 10h) [reset = 0h]
- 17.7.7.6 CLKLFACK Register (Offset = 14h) [reset = 0h]
- 17.7.7.7 WUEVFLAGS Register (Offset = 28h) [reset = 0h]
- 17.7.7.8 WUEVCLR Register (Offset = 2Ch) [reset = 0h]
- 17.7.7.9 ADCCLKCTL Register (Offset = 30h) [reset = 0h]
- 17.7.7.10 TDCCLKCTL Register (Offset = 34h) [reset = 0h]
- 17.7.7.11 REFCLKCTL Register (Offset = 38h) [reset = 0h]
- 17.7.7.12 RTCSUBSECINC0 Register (Offset = 3Ch) [reset = 0h]
- 17.7.7.13 RTCSUBSECINC1 Register (Offset = 40h) [reset = 0h]
- 17.7.7.14 RTCSUBSECINCCTL Register (Offset = 44h) [reset = 0h]
- 17.7.7.15 MCUBUSCTL Register (Offset = 48h) [reset = 0h]
- 17.7.7.16 MCUBUSSTAT Register (Offset = 4Ch) [reset = 0h]
- 17.7.7.17 AONCTLSTAT Register (Offset = 50h) [reset = 0h]
- 17.7.7.18 AUXIOLATCH Register (Offset = 54h) [reset = 0h]
- 17.7.7.19 MODCLKEN1 Register (Offset = 5Ch) [reset = 0h]
- 17.7.8 AUX_ANAIF Registers
- 17.7.1 ADI_4_AUX Registers
- 18 Battery Monitor and Temperature Sensor
- 18.1 Introduction
- 18.2 Functional Description
- 18.3 BATMON Registers
- 18.3.1 AON_BATMON Registers
- 18.3.1.1 CTL Register (Offset = 0h) [reset = 0h]
- 18.3.1.2 MEASCFG Register (Offset = 4h) [reset = 0h]
- 18.3.1.3 TEMPP0 Register (Offset = Ch) [reset = 0h]
- 18.3.1.4 TEMPP1 Register (Offset = 10h) [reset = 0h]
- 18.3.1.5 TEMPP2 Register (Offset = 14h) [reset = 0h]
- 18.3.1.6 BATMONP0 Register (Offset = 18h) [reset = 0h]
- 18.3.1.7 BATMONP1 Register (Offset = 1Ch) [reset = 0h]
- 18.3.1.8 IOSTRP0 Register (Offset = 20h) [reset = 28h]
- 18.3.1.9 FLASHPUMPP0 Register (Offset = 24h) [reset = 0h]
- 18.3.1.10 BAT Register (Offset = 28h) [reset = 0h]
- 18.3.1.11 BATUPD Register (Offset = 2Ch) [reset = 0h]
- 18.3.1.12 TEMP Register (Offset = 30h) [reset = 0h]
- 18.3.1.13 TEMPUPD Register (Offset = 34h) [reset = 0h]
- 18.3.1 AON_BATMON Registers
- 19 Universal Asynchronous Receiver/Transmitter (UART)
- 19.1 Universal Asynchronous Receiver/Transmitter
- 19.2 Block Diagram
- 19.3 Signal Description
- 19.4 Functional Description
- 19.5 Interface to DMA
- 19.6 Initialization and Configuration
- 19.7 UART Registers
- 19.7.1 UART Registers
- 19.7.1.1 DR Register (Offset = 0h) [reset = X]
- 19.7.1.2 RSR Register (Offset = 4h) [reset = 0h]
- 19.7.1.3 ECR Register (Offset = 4h) [reset = 0h]
- 19.7.1.4 FR Register (Offset = 18h) [reset = X]
- 19.7.1.5 IBRD Register (Offset = 24h) [reset = 0h]
- 19.7.1.6 FBRD Register (Offset = 28h) [reset = 0h]
- 19.7.1.7 LCRH Register (Offset = 2Ch) [reset = 0h]
- 19.7.1.8 CTL Register (Offset = 30h) [reset = 300h]
- 19.7.1.9 IFLS Register (Offset = 34h) [reset = 12h]
- 19.7.1.10 IMSC Register (Offset = 38h) [reset = 0h]
- 19.7.1.11 RIS Register (Offset = 3Ch) [reset = X]
- 19.7.1.12 MIS Register (Offset = 40h) [reset = 0h]
- 19.7.1.13 ICR Register (Offset = 44h) [reset = X]
- 19.7.1.14 DMACTL Register (Offset = 48h) [reset = 0h]
- 19.7.1 UART Registers
- 20 Synchronous Serial Interface (SSI)
- 20.1 Synchronous Serial Interface
- 20.2 Block Diagram
- 20.3 Signal Description
- 20.4 Functional Description
- 20.4.1 Bit Rate Generation
- 20.4.2 FIFO Operation
- 20.4.3 Interrupts
- 20.4.4 Frame Formats
- 20.4.4.1 Texas Instruments' Synchronous Serial Frame Format
- 20.4.4.2 Motorola SPI Frame Format
- 20.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
- 20.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
- 20.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
- 20.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
- 20.4.4.7 MICROWIRE Frame Format
- 20.5 DMA Operation
- 20.6 Initialization and Configuration
- 20.7 SSI Registers
- 20.7.1 SSI Registers
- 20.7.1.1 CR0 Register (Offset = 0h) [reset = 0h]
- 20.7.1.2 CR1 Register (Offset = 4h) [reset = 0h]
- 20.7.1.3 DR Register (Offset = 8h) [reset = X]
- 20.7.1.4 SR Register (Offset = Ch) [reset = 3h]
- 20.7.1.5 CPSR Register (Offset = 10h) [reset = 0h]
- 20.7.1.6 IMSC Register (Offset = 14h) [reset = 0h]
- 20.7.1.7 RIS Register (Offset = 18h) [reset = 8h]
- 20.7.1.8 MIS Register (Offset = 1Ch) [reset = 0h]
- 20.7.1.9 ICR Register (Offset = 20h) [reset = 0h]
- 20.7.1.10 DMACR Register (Offset = 24h) [reset = 0h]
- 20.7.1 SSI Registers
- 21 Inter-Integrated Circuit (I2C) Interface
- 21.1 Inter-Integrated Circuit (I2C) Interface
- 21.2 Block Diagram
- 21.3 Functional Description
- 21.4 Initialization and Configuration
- 21.5 I2C Interface Registers
- 21.5.1 I2C Registers
- 21.5.1.1 SOAR Register (Offset = 0h) [reset = 0h]
- 21.5.1.2 SSTAT Register (Offset = 4h) [reset = 0h]
- 21.5.1.3 SCTL Register (Offset = 4h) [reset = 0h]
- 21.5.1.4 SDR Register (Offset = 8h) [reset = 0h]
- 21.5.1.5 SIMR Register (Offset = Ch) [reset = 0h]
- 21.5.1.6 SRIS Register (Offset = 10h) [reset = 0h]
- 21.5.1.7 SMIS Register (Offset = 14h) [reset = 0h]
- 21.5.1.8 SICR Register (Offset = 18h) [reset = 0h]
- 21.5.1.9 MSA Register (Offset = 800h) [reset = 0h]
- 21.5.1.10 MSTAT Register (Offset = 804h) [reset = 20h]
- 21.5.1.11 MCTRL Register (Offset = 804h) [reset = 0h]
- 21.5.1.12 MDR Register (Offset = 808h) [reset = 0h]
- 21.5.1.13 MTPR Register (Offset = 80Ch) [reset = 1h]
- 21.5.1.14 MIMR Register (Offset = 810h) [reset = 0h]
- 21.5.1.15 MRIS Register (Offset = 814h) [reset = 0h]
- 21.5.1.16 MMIS Register (Offset = 818h) [reset = 0h]
- 21.5.1.17 MICR Register (Offset = 81Ch) [reset = 0h]
- 21.5.1.18 MCR Register (Offset = 820h) [reset = 0h]
- 21.5.1 I2C Registers
- 22 Inter-IC Sound (I2S) Module
- 22.1 Introduction
- 22.2 Digital Audio Interface
- 22.3 Frame Configuration
- 22.4 Pin Configuration
- 22.5 Clock Configuration
- 22.6 Serial Interface Formats
- 22.7 Memory Interface
- 22.8 Samplestamp Generator
- 22.9 Usage
- 22.10 I2S Registers
- 22.10.1 I2S Registers
- 22.10.1.1 AIFWCLKSRC Register (Offset = 0h) [reset = 0h]
- 22.10.1.2 AIFDMACFG Register (Offset = 4h) [reset = 0h]
- 22.10.1.3 AIFDIRCFG Register (Offset = 8h) [reset = 0h]
- 22.10.1.4 AIFFMTCFG Register (Offset = Ch) [reset = 170h]
- 22.10.1.5 AIFWMASK0 Register (Offset = 10h) [reset = 3h]
- 22.10.1.6 AIFWMASK1 Register (Offset = 14h) [reset = 3h]
- 22.10.1.7 AIFWMASK2 Register (Offset = 18h) [reset = 3h]
- 22.10.1.8 AIFPWMVALUE Register (Offset = 1Ch) [reset = 0h]
- 22.10.1.9 AIFINPTRNEXT Register (Offset = 20h) [reset = 0h]
- 22.10.1.10 AIFINPTR Register (Offset = 24h) [reset = 0h]
- 22.10.1.11 AIFOUTPTRNEXT Register (Offset = 28h) [reset = 0h]
- 22.10.1.12 AIFOUTPTR Register (Offset = 2Ch) [reset = 0h]
- 22.10.1.13 STMPCTL Register (Offset = 34h) [reset = 0h]
- 22.10.1.14 STMPXCNTCAPT0 Register (Offset = 38h) [reset = 0h]
- 22.10.1.15 STMPXPER Register (Offset = 3Ch) [reset = 0h]
- 22.10.1.16 STMPWCNTCAPT0 Register (Offset = 40h) [reset = 0h]
- 22.10.1.17 STMPWPER Register (Offset = 44h) [reset = 0h]
- 22.10.1.18 STMPINTRIG Register (Offset = 48h) [reset = 0h]
- 22.10.1.19 STMPOUTTRIG Register (Offset = 4Ch) [reset = 0h]
- 22.10.1.20 STMPWSET Register (Offset = 50h) [reset = 0h]
- 22.10.1.21 STMPWADD Register (Offset = 54h) [reset = 0h]
- 22.10.1.22 STMPXPERMIN Register (Offset = 58h) [reset = FFFFh]
- 22.10.1.23 STMPWCNT Register (Offset = 5Ch) [reset = 0h]
- 22.10.1.24 STMPXCNT Register (Offset = 60h) [reset = 0h]
- 22.10.1.25 STMPXCNTCAPT1 Register (Offset = 64h) [reset = 0h]
- 22.10.1.26 STMPWCNTCAPT1 Register (Offset = 68h) [reset = 0h]
- 22.10.1.27 IRQMASK Register (Offset = 70h) [reset = 0h]
- 22.10.1.28 IRQFLAGS Register (Offset = 74h) [reset = 0h]
- 22.10.1.29 IRQSET Register (Offset = 78h) [reset = 0h]
- 22.10.1.30 IRQCLR Register (Offset = 7Ch) [reset = 0h]
- 22.10.1 I2S Registers
- 23 Radio
- 23.1 RF Core
- 23.2 Radio Doorbell
- 23.3 RF Core HAL
- 23.3.1 Hardware Support
- 23.3.2 Firmware Support
- 23.3.3 Command Definitions
- 23.3.3.1 Protocol-Independent Radio Operation Commands
- 23.3.3.1.1 CMD_NOP: No Operation Command
- 23.3.3.1.2 CMD_RADIO_SETUP: Set Up Radio Settings Command
- 23.3.3.1.3 CMD_FS_POWERUP: Power Up Frequency Synthesizer
- 23.3.3.1.4 CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
- 23.3.3.1.5 CMD_FS: Frequency Synthesizer Controls Command
- 23.3.3.1.6 CMD_FS_OFF: Turn Off Frequency Synthesizer
- 23.3.3.1.7 CMD_RX_TEST: Receiver Test Command
- 23.3.3.1.8 CMD_TX_TEST: Transmitter Test Command
- 23.3.3.1.9 CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
- 23.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
- 23.3.3.1.11 CMD_COUNT: Counter Command
- 23.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
- 23.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
- 23.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
- 23.3.3.1 Protocol-Independent Radio Operation Commands
- 23.3.4 Protocol-Independent Direct and Immediate Commands
- 23.3.4.1 CMD_ABORT: Abort Command
- 23.3.4.2 CMD_STOP: Stop Command
- 23.3.4.3 CMD_GET_RSSI: Read RSSI Command
- 23.3.4.4 CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
- 23.3.4.5 CMD_TRIGGER: Generate Command Trigger
- 23.3.4.6 CMD_GET_FW_INFO: Request Information on the Firmware Being Run
- 23.3.4.7 CMD_START_RAT: Asynchronously Start Radio Timer Command
- 23.3.4.8 CMD_PING: Respond With Interrupt
- 23.3.4.9 CMD_READ_RFREG: Read RF Core Register
- 23.3.4.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
- 23.3.4.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
- 23.3.4.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
- 23.3.4.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
- 23.3.4.14 CMD_ARM_RAT_CH: Arm RAT Channel
- 23.3.4.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
- 23.3.4.16 CMD_SET_TX_POWER: Set Transmit Power
- 23.3.4.17 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration
- 23.3.4.18 CMD_BUS_REQUEST: Request System BUS Available for RF Core
- 23.3.5 Immediate Commands for Data Queue Manipulation
- 23.4 Data Queue Usage
- 23.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
- 23.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
- 23.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
- 23.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
- 23.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
- 23.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
- 23.4.2 Radio CPU Usage Model
- 23.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
- 23.5 IEEE 802.15.4
- 23.5.1 IEEE 802.15.4 Commands
- 23.5.2 Interrupts
- 23.5.3 Data Handling
- 23.5.4 Radio Operation Commands
- 23.5.5 Immediate Commands
- 23.6 Bluetooth low energy
- 23.6.1 Bluetooth low energy Commands
- 23.6.2 Interrupts
- 23.6.3 Data Handling
- 23.6.4 Radio Operation Command Descriptions
- 23.6.5 Immediate Commands
- 23.7 Proprietary Radio
- 23.7.1 Packet Formats
- 23.7.2 Commands
- 23.7.3 Interrupts
- 23.7.4 Data Handling
- 23.7.5 Radio Operation Command Descriptions
- 23.7.6 Immediate Commands
- 23.8 Radio Registers
- 23.8.1 RFC_RAT Registers
- 23.8.1.1 RATCNT Register (Offset = 4h) [reset = 0h]
- 23.8.1.2 RATCH0VAL Register (Offset = 80h) [reset = 0h]
- 23.8.1.3 RATCH1VAL Register (Offset = 84h) [reset = 0h]
- 23.8.1.4 RATCH2VAL Register (Offset = 88h) [reset = 0h]
- 23.8.1.5 RATCH3VAL Register (Offset = 8Ch) [reset = 0h]
- 23.8.1.6 RATCH4VAL Register (Offset = 90h) [reset = 0h]
- 23.8.1.7 RATCH5VAL Register (Offset = 94h) [reset = 0h]
- 23.8.1.8 RATCH6VAL Register (Offset = 98h) [reset = 0h]
- 23.8.1.9 RATCH7VAL Register (Offset = 9Ch) [reset = 0h]
- 23.8.2 RFC_DBELL Registers
- 23.8.2.1 CMDR Register (Offset = 0h) [reset = 0h]
- 23.8.2.2 CMDSTA Register (Offset = 4h) [reset = 0h]
- 23.8.2.3 RFHWIFG Register (Offset = 8h) [reset = 0h]
- 23.8.2.4 RFHWIEN Register (Offset = Ch) [reset = 0h]
- 23.8.2.5 RFCPEIFG Register (Offset = 10h) [reset = 0h]
- 23.8.2.6 RFCPEIEN Register (Offset = 14h) [reset = FFFFFFFFh]
- 23.8.2.7 RFCPEISL Register (Offset = 18h) [reset = FFFF0000h]
- 23.8.2.8 RFACKIFG Register (Offset = 1Ch) [reset = 0h]
- 23.8.2.9 SYSGPOCTL Register (Offset = 20h) [reset = 0h]
- 23.8.3 RFC_PWR Registers
- 23.8.1 RFC_RAT Registers
- Important Notice