CC2640x Reference Manual

User Manual:

Open the PDF directly: View PDF .
Page Count: 1733

Download
Open PDF In Browser	View PDF

CC13x0, CC26x0 SimpleLink™ Wireless MCU

Technical Reference Manual

Literature Number: SWCU117G
February 2015 – Revised February 2017

Contents
Revision History: SWCU117G ....................................................................................................... 11
Preface....................................................................................................................................... 12
1

Architectural Overview ........................................................................................................ 14
1.1
1.2
1.3

2.4

2.5

2.6
2.7

The Cortex-M3 Processor Introduction .................................................................................. 29
Block Diagram .............................................................................................................. 29
Overview..................................................................................................................... 30
2.3.1 System-level Interface ............................................................................................ 30
2.3.2 Integrated Configurable Debug .................................................................................. 30
2.3.3 Trace Port Interface Unit ......................................................................................... 31
2.3.4 Cortex-M3 System Component Details......................................................................... 31
Programming Model ....................................................................................................... 31
2.4.1 Processor Mode and Privilege Levels for Software Execution .............................................. 32
2.4.2 Stacks ............................................................................................................... 32
2.4.3 Exceptions and Interrupts ........................................................................................ 32
2.4.4 Data Types ......................................................................................................... 32
Cortex-M3 Core Registers ................................................................................................ 33
2.5.1 Core Register Map ................................................................................................ 34
2.5.2 Core Register Descriptions ...................................................................................... 34
Instruction Set Summary .................................................................................................. 47
Cortex-M3 Processor Registers .......................................................................................... 51
2.7.1 CPU_DWT Registers ............................................................................................. 51
2.7.2 CPU_FPB Registers .............................................................................................. 76
2.7.3 CPU_ITM Registers ............................................................................................... 86
2.7.4 CPU_SCS Registers ............................................................................................ 126
2.7.5 CPU_TPIU Registers ............................................................................................ 205

ARM® Cortex®-M3 Peripherals
3.1

15
15
17
17
18
19
19
20
20
21
21
24
24
25
25
26

The ARM® Cortex®-M3 Processor.......................................................................................... 28
2.1
2.2
2.3

Target Applications .........................................................................................................
Overview.....................................................................................................................
Functional Overview .......................................................................................................
1.3.1 ARM® Cortex®-M3 .................................................................................................
1.3.2 On-chip Memory ...................................................................................................
1.3.3 Radio ................................................................................................................
1.3.4 Advanced Encryption Standard (AES) Engine With 128-bit Key Support .................................
1.3.5 General-Purpose Timers .........................................................................................
1.3.6 Direct Memory Access ............................................................................................
1.3.7 System Control and Clock .......................................................................................
1.3.8 Serial Communication Peripherals ..............................................................................
1.3.9 Programmable I/Os ...............................................................................................
1.3.10 Sensor Controller ................................................................................................
1.3.11 Random Number Generator ....................................................................................
1.3.12 cJTAG and JTAG ................................................................................................
1.3.13 Power Supply System ...........................................................................................

............................................................................................ 218
.................................................................................... 219

Cortex-M3 Peripherals Introduction

Contents

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

www.ti.com

3.2

4.2

4.3

4.4

4.5

4.6
4.7

Exception Model ..........................................................................................................
4.1.1 Exception States .................................................................................................
4.1.2 Exception Types .................................................................................................
4.1.3 Exception Handlers ..............................................................................................
4.1.4 Vector Table ......................................................................................................
4.1.5 Exception Priorities ..............................................................................................
4.1.6 Interrupt Priority Grouping ......................................................................................
4.1.7 Exception Entry and Return ....................................................................................
Fault Handling .............................................................................................................
4.2.1 Fault Types .......................................................................................................
4.2.2 Fault Escalation and Hard Faults ..............................................................................
4.2.3 Fault Status Registers and Fault Address Registers ........................................................
4.2.4 Lockup.............................................................................................................
Event Fabric ...............................................................................................................
4.3.1 Introduction .......................................................................................................
4.3.2 Event Fabric Overview ..........................................................................................
AON Event Fabric ........................................................................................................
4.4.1 Common Input Event List .......................................................................................
4.4.2 Event Subscribers ...............................................................................................
MCU Event Fabric ........................................................................................................
4.5.1 Common Input Event List .......................................................................................
4.5.2 Event Subscribers ...............................................................................................
AON Events ...............................................................................................................
Interrupts and Events Registers ........................................................................................
4.7.1 AON_EVENT Registers .........................................................................................
4.7.2 EVENT Registers ................................................................................................

227
227
228
230
230
232
232
233
234
234
235
236
236
237
237
238
238
239
239
240
240
243
245
246
246
269

JTAG Interface ................................................................................................................. 388
5.1
5.2

5.3

5.4
5.5
5.6
5.7
5.8
5.9

219
220
220
221
222
222
222
223
224

Interrupts and Events ........................................................................................................ 226
4.1

Functional Description....................................................................................................
3.2.1 SysTick ............................................................................................................
3.2.2 NVIC ...............................................................................................................
3.2.3 SCB ................................................................................................................
3.2.4 ITM .................................................................................................................
3.2.5 FPB ................................................................................................................
3.2.6 TPIU ...............................................................................................................
3.2.7 DWT ...............................................................................................................
3.2.8 Cortex-M3 Memory Map ........................................................................................

Top-Level Debug System ................................................................................................
cJTAG ......................................................................................................................
5.2.1 JTAG Commands ................................................................................................
5.2.2 Programming Sequences .......................................................................................
ICEPick .....................................................................................................................
5.3.1 Secondary TAPs .................................................................................................
5.3.2 ICEPick Registers ...............................................................................................
5.3.3 ROUTER Scan Chain ...........................................................................................
5.3.4 TAP Routing Registers .........................................................................................
ICEMelter ..................................................................................................................
Serial Wire Viewer (SWV) ...............................................................................................
Halt In Boot (HIB) .........................................................................................................
Debug and Shutdown ....................................................................................................
Debug Features Supported Through WUC TAP .....................................................................
Profiler Register ...........................................................................................................

389
391
393
395
396
396
398
401
402
406
407
407
407
408
409

Power, Reset, and Clock Management................................................................................. 410

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Contents

www.ti.com

6.1
6.2
6.3

6.4

6.5

6.6

6.7

6.8

7.3

7.4
7.5

7.6
7.7
7.8
7.9

VIMS Overview ...........................................................................................................
VIMS Configurations .....................................................................................................
7.2.1 VIMS Modes ......................................................................................................
7.2.2 VIMS Flash Line Buffering ......................................................................................
7.2.3 VIMS Arbitration..................................................................................................
7.2.4 VIMS Cache TAG Prefetch .....................................................................................
VIMS Software Remarks .................................................................................................
7.3.1 Flash Program or Update .......................................................................................
7.3.2 VIMS Retention ..................................................................................................
ROM ........................................................................................................................
FLASH......................................................................................................................
7.5.1 FLASH Memory Protection .....................................................................................
7.5.2 Memory Programming ..........................................................................................
7.5.3 FLASH Memory Programming .................................................................................
Power Management Requirements ....................................................................................
ROM Functions ...........................................................................................................
SRAM ......................................................................................................................
VIMS Registers ...........................................................................................................
7.9.1 FLASH Registers ................................................................................................
7.9.2 VIMS Registers ..................................................................................................

553
554
554
557
557
557
558
558
558
559
559
559
560
560
560
562
563
564
564
690

Bootloader ....................................................................................................................... 693
8.1

411
412
413
414
414
415
416
416
416
416
419
421
422
423
423
424
424
426
426
426
428
428
428
428
428
429
429
449

Versatile Instruction Memory System (VIMS) ........................................................................ 552
7.1
7.2

Introduction ................................................................................................................
System CPU Mode .......................................................................................................
Supply System ............................................................................................................
6.3.1 Internal DC-DC Converter and Global LDO ..................................................................
6.3.2 External Regulator Mode .......................................................................................
Digital Power Partitioning ................................................................................................
6.4.1 MCU_VD ..........................................................................................................
6.4.2 AON_VD ..........................................................................................................
Clock Management .......................................................................................................
6.5.1 System Clocks ...................................................................................................
6.5.2 Clocks in MCU_VD ..............................................................................................
6.5.3 Clocks in AON_VD ..............................................................................................
Power Modes ..............................................................................................................
6.6.1 Start-Up State ....................................................................................................
6.6.2 Active Mode ......................................................................................................
6.6.3 Idle Mode .........................................................................................................
6.6.4 Standby Mode ....................................................................................................
6.6.5 Shutdown Mode ..................................................................................................
Reset .......................................................................................................................
6.7.1 System Resets ...................................................................................................
6.7.2 Warm Reset ......................................................................................................
6.7.3 Software-Initiated Reset of MCU_VD .........................................................................
6.7.4 Reset of the MCU_VD Power Domains and Modules ......................................................
6.7.5 Reset of AON_VD ...............................................................................................
6.7.6 Reset of AUX_PD................................................................................................
PRCM Registers ..........................................................................................................
6.8.1 CC13x0 DDI_0_OSC Registers................................................................................
6.8.2 CC26x0 PRCM Registers.......................................................................................

Bootloader Functionality ................................................................................................. 694
8.1.1 Bootloader Disabling ............................................................................................ 694
8.1.2 Bootloader Backdoor ............................................................................................ 694

Contents

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

www.ti.com

8.2

9.2

Customer Configuration (CCFG) .......................................................................................
9.1.1 CCFG Registers .................................................................................................
Factory Configuration (FCFG) ..........................................................................................
9.2.1 CC13x0 Factory Configuration (FCFG) Registers ...........................................................
9.2.2 CC26xx Factory Configuration (FCFG) Registers ...........................................................

709
710
738
739
825

Cryptography ................................................................................................................... 911
10.1
10.2

10.3
10.4

10.5

10.6

10.7

10.8

10.9

694
695
696
698

Device Configuration......................................................................................................... 708
9.1

Bootloader Interfaces.....................................................................................................
8.2.1 Packet Handling..................................................................................................
8.2.2 Transport Layer ..................................................................................................
8.2.3 Serial Bus Commands ..........................................................................................

AES Cryptoprocessor Overview ........................................................................................
Functional Description....................................................................................................
10.2.1 Debug Capabilities .............................................................................................
10.2.2 Exception Handling .............................................................................................
Power Management and Sleep Modes ................................................................................
Hardware Description ....................................................................................................
10.4.1 AHB Slave Bus ..................................................................................................
10.4.2 AHB Master Bus ................................................................................................
10.4.3 Interrupts .........................................................................................................
Module Description .......................................................................................................
10.5.1 Introduction ......................................................................................................
10.5.2 Module Memory Map ...........................................................................................
10.5.3 DMA Controller .................................................................................................
10.5.4 Master Control and Select .....................................................................................
10.5.5 AES Engine......................................................................................................
10.5.6 Key Area Registers .............................................................................................
Performance ...............................................................................................................
10.6.1 Introduction ......................................................................................................
10.6.2 Performance .....................................................................................................
Programming Guidelines.................................................................................................
10.7.1 One-time Initialization After a Reset..........................................................................
10.7.2 DMAC and Master Control ....................................................................................
10.7.3 Encryption and Decryption ....................................................................................
10.7.4 Exceptions Handling............................................................................................
Conventions and Compliances..........................................................................................
10.8.1 Conventions Used in This Manual ............................................................................
10.8.2 Compliance ......................................................................................................
Cryptography Registers ..................................................................................................
10.9.1 CRYPTO Registers .............................................................................................

912
912
913
913
913
913
913
913
914
914
914
914
916
919
920
924
925
925
926
926
926
927
928
936
937
937
938
939
939

I/O Control ....................................................................................................................... 983
11.1
11.2
11.3

11.4
11.5
11.6
11.7

Introduction ................................................................................................................
IOC Overview .............................................................................................................
I/O Mapping and Configuration .........................................................................................
11.3.1 Basic I/O Mapping ..............................................................................................
11.3.2 MAP AUXIO From the Sensor Controller to DIO Pin ......................................................
11.3.3 Map 32-kHz System Clock (LF Clock) to DIO/PIN .........................................................
Edge Detection on Pin (DIO) ............................................................................................
11.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT ...............................
AON IOC State Latching When Powering Off the MCU Domain ..................................................
Unused I/O Pins...........................................................................................................
GPIO........................................................................................................................

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Contents

984
984
985
985
985
986
986
986
987
987
987
5

www.ti.com

11.8 I/O Pin Mapping ........................................................................................................... 988
11.9 Peripheral PORTIDs ...................................................................................................... 989
11.10 I/O Pins .................................................................................................................... 989
11.10.1 Input/Output Modes ........................................................................................... 989
11.10.2 Digital Input/Output Power Domains ........................................................................ 991
11.11 I/O Control Registers ..................................................................................................... 992
11.11.1 AON_IOC Registers .......................................................................................... 992
11.11.2 GPIO Registers ................................................................................................ 998
11.11.3 IOC Registers ................................................................................................ 1020

Micro Direct Memory Access (µDMA)
12.1
12.2
12.3

12.4

12.5

13.4

13.5

General-Purpose Timers ...............................................................................................
Block Diagram ...........................................................................................................
Functional Description ..................................................................................................
13.3.1 GPTM Reset Conditions .....................................................................................
13.3.2 Timer Modes ...................................................................................................
13.3.3 Wait-for-Trigger Mode ........................................................................................
13.3.4 Synchronizing GPT Blocks ...................................................................................
13.3.5 Accessing Concatenated 16- and 32-Bit GPTM Register Values ......................................
Initialization and Configuration.........................................................................................
13.4.1 One-Shot and Periodic Timer Modes .......................................................................
13.4.2 Input Edge-Count Mode ......................................................................................
13.4.3 Input Edge-Timing Mode .....................................................................................
13.4.4 PWM Mode.....................................................................................................
13.4.5 Producing DMA Trigger Events .............................................................................
General-Purpose Timer Registers ....................................................................................
13.5.1 GPT Registers .................................................................................................

1189
1190
1190
1191
1191
1198
1199
1199
1200
1200
1201
1201
1202
1202
1203
1203

Real-Time Clock .............................................................................................................. 1237
14.1
14.2

14.3
6

1151
1152
1152
1153
1154
1154
1154
1155
1157
1164
1164
1164
1165
1165
1165
1166
1167
1167

Timers ........................................................................................................................... 1188
13.1
13.2
13.3

................................................................................ 1150

DMA Introduction ......................................................................................................
Block Diagram ...........................................................................................................
Functional Description ..................................................................................................
12.3.1 Channel Assignments ........................................................................................
12.3.2 Priority ..........................................................................................................
12.3.3 Arbitration Size ................................................................................................
12.3.4 Request Types ................................................................................................
12.3.5 Channel Configuration ........................................................................................
12.3.6 Transfer Modes ................................................................................................
12.3.7 Transfer Size and Increments ...............................................................................
12.3.8 Peripheral Interface ...........................................................................................
12.3.9 Software Request .............................................................................................
12.3.10 Interrupts and Errors ........................................................................................
Initialization and Configuration.........................................................................................
12.4.1 Module Initialization ...........................................................................................
12.4.2 Configuring a Memory-to-Memory Transfer ...............................................................
µDMA Registers .........................................................................................................
12.5.1 UDMA Registers...............................................................................................

Introduction ...............................................................................................................
Functional Specifications ...............................................................................................
14.2.1 Functional Overview ..........................................................................................
14.2.2 Free-Running Counter ........................................................................................
14.2.3 Channels .......................................................................................................
14.2.4 Events ..........................................................................................................
RTC Registers ...........................................................................................................

Contents

1238
1238
1238
1238
1239
1240
1240

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

www.ti.com

14.4

WDT Introduction ........................................................................................................
WDT Functional Description ...........................................................................................
WDT Initialization and Configuration..................................................................................
Watchdog Timer Registers .............................................................................................
15.4.1 WDT Registers ................................................................................................

1257
1257
1258
1259
1259

Random Number Generator .............................................................................................. 1269
16.1
16.2
16.3
16.4
16.5

16.6
16.7

1240
1240
1241
1242
1242

Watchdog Timer.............................................................................................................. 1256
15.1
15.2
15.3
15.4

14.3.1 Register Access ...............................................................................................
14.3.2 Entering Sleep and Wakeup From Sleep .................................................................
14.3.3 AON_RTC:SYNC Register ...................................................................................
Real-Time Clock Registers.............................................................................................
14.4.1 AON_RTC Registers ..........................................................................................

Overview..................................................................................................................
Block Diagram ...........................................................................................................
TRNG Software Reset ..................................................................................................
Interrupt Requests.......................................................................................................
TRNG Operation Description ..........................................................................................
16.5.1 TRNG Shutdown ..............................................................................................
16.5.2 TRNG Alarms ..................................................................................................
16.5.3 TRNG Entropy .................................................................................................
TRNG Low-Level Programing Guide .................................................................................
16.6.1 Initialization .....................................................................................................
Random Number Generator Registers ...............................................................................
16.7.1 TRNG Registers ...............................................................................................

AUX – Sensor Controller with Digital and Analog Peripherals
17.1
17.2
17.3
17.4

17.5

17.6

17.7

.............................................. 1300

Introduction ...............................................................................................................
17.1.1 AUX Hardware Overview .....................................................................................
Memory Mapping ........................................................................................................
17.2.1 Alias of Commonly Used Registers .........................................................................
I/O Mapping ..............................................................................................................
Modules...................................................................................................................
17.4.1 Sensor Controller ..............................................................................................
17.4.2 GPIO Control ..................................................................................................
17.4.3 AUX Timers ....................................................................................................
17.4.4 Time-to-Digital Converter.....................................................................................
17.4.5 Semaphores ...................................................................................................
17.4.6 Oscillator Configuration Interface (DDI) ....................................................................
17.4.7 Analog MUX ...................................................................................................
17.4.8 ADC .............................................................................................................
Power Management.....................................................................................................
17.5.1 Start-Up .........................................................................................................
17.5.2 Power Mode Management ...................................................................................
17.5.3 Wake-Up Events ..............................................................................................
17.5.4 MCU Bus Connection .........................................................................................
Clock Management .....................................................................................................
17.6.1 System Clocks .................................................................................................
17.6.2 Sensor Controller Clock ......................................................................................
17.6.3 Peripheral Clocks .............................................................................................
AUX – Sensor Controller Registers ...................................................................................
17.7.1 ADI_4_AUX Registers ........................................................................................
17.7.2 AUX_AIODIO Registers ......................................................................................
17.7.3 AUX_EVCTL Registers .......................................................................................

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

1270
1270
1271
1271
1272
1272
1273
1273
1274
1274
1277
1277

Contents

1301
1302
1303
1303
1305
1306
1306
1316
1318
1319
1321
1321
1321
1322
1325
1326
1326
1327
1328
1328
1328
1329
1329
1330
1330
1341
1349
7

www.ti.com

17.7.4
17.7.5
17.7.6
17.7.7
17.7.8

19.5
19.6
19.7

1429
1429
1430
1430

Universal Asynchronous Receiver/Transmitter ......................................................................
Block Diagram ...........................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
19.4.1 Transmit and Receive Logic .................................................................................
19.4.2 Baud-Rate Generation ........................................................................................
19.4.3 Data Transmission ............................................................................................
19.4.4 Modem Handshake Support .................................................................................
19.4.5 FIFO Operation ................................................................................................
19.4.6 Interrupts .......................................................................................................
19.4.7 Loopback Operation ..........................................................................................
Interface to DMA ........................................................................................................
Initialization and Configuration.........................................................................................
UART Registers .........................................................................................................
19.7.1 UART Registers ...............................................................................................

1445
1446
1446
1446
1447
1447
1447
1448
1449
1449
1450
1451
1452
1453
1453

Synchronous Serial Interface (SSI) .................................................................................... 1475
20.1
20.2
20.3
20.4

20.5
20.6
20.7

Introduction ...............................................................................................................
Functional Description ..................................................................................................
BATMON Registers .....................................................................................................
18.3.1 AON_BATMON Registers ....................................................................................

Universal Asynchronous Receiver/Transmitter (UART) ........................................................ 1444
19.1
19.2
19.3
19.4

1370
1379
1392
1400
1421

Battery Monitor and Temperature Sensor........................................................................... 1428
18.1
18.2
18.3

AUX_SMPH Registers ........................................................................................
AUX_TDC Registers ..........................................................................................
AUX_TIMER Registers .......................................................................................
AUX_WUC Registers .........................................................................................
AUX_ANAIF Registers .......................................................................................

Synchronous Serial Interface ..........................................................................................
Block Diagram ...........................................................................................................
Signal Description .......................................................................................................
Functional Description ..................................................................................................
20.4.1 Bit Rate Generation ...........................................................................................
20.4.2 FIFO Operation ................................................................................................
20.4.3 Interrupts .......................................................................................................
20.4.4 Frame Formats ................................................................................................
DMA Operation ..........................................................................................................
Initialization and Configuration.........................................................................................
SSI Registers ............................................................................................................
20.7.1 SSI Registers ..................................................................................................

1476
1477
1478
1478
1478
1478
1479
1480
1487
1487
1489
1489

Inter-Integrated Circuit (I2C) Interface ................................................................................ 1501
21.1
21.2
21.3

21.4
21.5

Inter-Integrated Circuit (I2C) Interface ................................................................................
Block Diagram ...........................................................................................................
Functional Description ..................................................................................................
21.3.1 I2C Bus Functional Overview ................................................................................
21.3.2 Available Speed Modes ......................................................................................
21.3.3 Interrupts .......................................................................................................
21.3.4 Loopback Operation ..........................................................................................
21.3.5 Command Sequence Flow Charts ..........................................................................
Initialization and Configuration.........................................................................................
I2C Interface Registers ..................................................................................................
21.5.1 I2C Registers ..................................................................................................

1502
1502
1503
1503
1505
1506
1506
1506
1514
1515
1515

Inter-IC Sound (I2S) Module.............................................................................................. 1535

Contents

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

www.ti.com

Introduction ..............................................................................................................
Digital Audio Interface ..................................................................................................
Frame Configuration ....................................................................................................
Pin Configuration ........................................................................................................
Clock Configuration .....................................................................................................
22.5.1 WCLK, BCLK, and MCLK Division Ratio...................................................................
22.6 Serial Interface Formats ................................................................................................
22.6.1 I2S ...............................................................................................................
22.6.2 Left Justified (LJF) ............................................................................................
22.6.3 Right Justified (RJF) ..........................................................................................
22.6.4 DSP .............................................................................................................
22.7 Memory Interface ........................................................................................................
22.7.1 Word Lengths ..................................................................................................
22.7.2 Audio Channels................................................................................................
22.7.3 Memory Buffers and Pointers................................................................................
22.8 Samplestamp Generator ...............................................................................................
22.8.1 Counters and Registers ......................................................................................
22.8.2 Starting Input and Output Pins ..............................................................................
22.8.3 Samplestamp Capturing ......................................................................................
22.9 Usage .....................................................................................................................
22.9.1 Start-up Sequence ............................................................................................
22.9.2 Termination Sequence .......................................................................................
22.10 I2S Registers ............................................................................................................
22.10.1 I2S Registers .................................................................................................
22.1
22.2
22.3
22.4
22.5

1536
1536
1537
1537
1537
1538
1538
1538
1539
1539
1540
1541
1541
1541
1542
1543
1543
1544
1544
1545
1545
1546
1547
1547

Radio ............................................................................................................................. 1578
23.1
23.2

23.3

23.4

23.5

23.6

23.7

RF Core...................................................................................................................
23.1.1 High-Level Description and Overview ......................................................................
Radio Doorbell ...........................................................................................................
23.2.1 Command and Status Register and Events ...............................................................
23.2.2 RF Core Interrupts ............................................................................................
23.2.3 Radio Timer ....................................................................................................
RF Core HAL ............................................................................................................
23.3.1 Hardware Support .............................................................................................
23.3.2 Firmware Support .............................................................................................
23.3.3 Command Definitions .........................................................................................
23.3.4 Protocol-Independent Direct and Immediate Commands ................................................
23.3.5 Immediate Commands for Data Queue Manipulation ....................................................
Data Queue Usage......................................................................................................
23.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations .....................
23.4.2 Radio CPU Usage Model ....................................................................................
IEEE 802.15.4 ...........................................................................................................
23.5.1 IEEE 802.15.4 Commands ...................................................................................
23.5.2 Interrupts .......................................................................................................
23.5.3 Data Handling..................................................................................................
23.5.4 Radio Operation Commands ................................................................................
23.5.5 Immediate Commands .......................................................................................
Bluetooth low energy ...................................................................................................
23.6.1 Bluetooth low energy Commands ..........................................................................
23.6.2 Interrupts .......................................................................................................
23.6.3 Data Handling..................................................................................................
23.6.4 Radio Operation Command Descriptions ..................................................................
23.6.5 Immediate Commands .......................................................................................
Proprietary Radio ........................................................................................................

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Contents

1579
1579
1580
1581
1581
1582
1584
1584
1584
1596
1610
1618
1621
1621
1624
1625
1625
1634
1634
1635
1647
1649
1649
1658
1659
1660
1682
1683
9

www.ti.com

23.8

23.7.1 Packet Formats ................................................................................................
23.7.2 Commands .....................................................................................................
23.7.3 Interrupts .......................................................................................................
23.7.4 Data Handling..................................................................................................
23.7.5 Radio Operation Command Descriptions ..................................................................
23.7.6 Immediate Commands .......................................................................................
Radio Registers..........................................................................................................
23.8.1 RFC_RAT Registers ..........................................................................................
23.8.2 RFC_DBELL Registers .......................................................................................
23.8.3 RFC_PWR Registers .........................................................................................

Contents

1683
1683
1692
1693
1694
1706
1707
1707
1716
1731

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Revision History: SWCU117G

www.ti.com

Revision History: SWCU117G
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from June 14, 2016 to February 20, 2017 ........................................................................................................ Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Reformatted Table 3-2 ................................................................................................................. 224
Changed Figure 4-4 .................................................................................................................... 238
Changed Figure 4-5 .................................................................................................................... 239
Changed Table 4-6..................................................................................................................... 240
Updated technical description in JTAG Interface chapter, section ICEMelter .................................................. 388
Changed Section 5.4 .................................................................................................................. 406
Changed Section 5.7 .................................................................................................................. 407
Added link to the reference design to Section 6.3.2 ............................................................................... 414
Changed Section 6.7.1.1 .............................................................................................................. 427
Added note to Section 8.1.2 .......................................................................................................... 694
Changed COMMAND_MEMORY_WRITE in Table 8-3 ........................................................................... 699
Changed Section 8.2.3.11 ............................................................................................................ 705
Changed Figure 11-2 .................................................................................................................. 989
Changed Table 12-1.................................................................................................................. 1153
Added Section 14.2.3.1 .............................................................................................................. 1239
Changed Table 16-2.................................................................................................................. 1274
Changed the title of Chapter 22 .................................................................................................... 1536
Added note to Section 22.7 ......................................................................................................... 1541
Changed Figure 23-2 ................................................................................................................. 1581
Changed Section 23.3.3.1.8 ......................................................................................................... 1605
Changed Section 23.3.4.16 ......................................................................................................... 1616
Changed Section 23.3.4.17 ......................................................................................................... 1617
Changed Table 23-69 ................................................................................................................ 1630
Added Table 23-103 .................................................................................................................. 1657
Changed Figure 23-9 and Figure 23-10 ........................................................................................... 1683
Added Table 23-143 .................................................................................................................. 1692

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Revision History

Preface
SWCU117G – February 2015 – Revised February 2017

Read This First
Trademarks
SimpleLink is a trademark of Texas Instruments.
ARM7, CoreSight are trademarks of ARM Limited.
ARM, Cortex, Thumb, AMBA, PrimeCell are registered trademarks of ARM Limited.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
Motorola is a trademark of Motorola Trademark Holdings, LLC.
All other trademarks are the property of their respective owners.

About This Document
This technical reference manual provides information on how to use the CC26x0 and the CC13x0
SimpleLink™ ultra-low power wireless microcontroller (MCU) devices. The CC26x0 and the CC13x0
families share the same MCU architecture and most of the peripherals. The radio in the CC26x0 device
operates in the 2.4-GHz ISM frequency band while the radio in the CC1310 device is designed for use in
the Sub-1 GHz frequency bands. The CC1350 device is a dual-band wireless MCU and can operate both
in the Sub-1 GHz and 2.4-GHz bands. This document covers the whole family of devices, so refer to the
individual device data sheets for supported modules and features.

Audience
This manual is intended for system software developers, hardware designers, and application developers.

About This Manual
This document is organized into sections that correspond to each major feature; it explains the features
and functionality of each module, and it also explains how to use them. For each feature, references are
given to the documentation for the driver of the corresponding operating systems. This document does not
contain performance characteristics of the device or modules, which are gathered in the corresponding
device data sheets.

Related Documentation
The following related documents are available on the CC26xx product pages at www.ti.com:
• CC2620 Data Sheet and Errata (CC2620 Technical Documents)
• CC2630 Data Sheet and Errata (CC2630 Technical Documents)
• CC2640 Data Sheet and Errata (CC2640 Technical Documents)
• CC2640R2F Data Sheet and Errata (CC2640R2F Technical Documents)
• CC2650 Data Sheet and Errata (CC2650 Technical Documents)
• CC1310 Data Sheet and Errata (CC1310 Technical Documents)
• CC1350 Data Sheet and Errata (CC1350 Technical Documents)
This list of documents was current as of publication date. Check the website for additional documentation,
application notes, and white papers.

Read This First

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Related Documentation

www.ti.com

Devices
The CC26x0 and the CC13x0 family of devices include both 2.4-GHz (CC26x0 and CC1350) and
Sub-1 GHz (CC13x0) radios and a variety of different memory sizes, peripherals and package options. All
devices are centered around an ARM® Cortex®-M series processor that handles the application layer and
protocol stack, as well as an autonomous radio core centered around an ARM Cortex-M0 processor that
handles all the low-level radio control and processing. Network processor options are available.
The availability of a wide range of different radio and MCU system combinations makes these device
families very well suited for almost any low-power RF node implementation.

Feedback
Help us meet your expectations:
We are always exploring ways to develop our service and improve our quality to fit your needs. Please
contact your TI representative and take a few minutes to provide general suggestions, give document
feedback, or submit an error.
Thank you.

Community Resources
All technical support is channeled through the TI Product Information Centers (PIC) - www.ti.com/support.
To send an E-mail request, please enter your contact information, along with your request at the following
link – PIC request form.
The following link connects to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI Embedded Processors Wiki – Texas Instruments Embedded Processors Wiki
TI Bluetooth low energy Wiki – Texas Instruments Bluetooth® low energy Wiki
Established to assist developers using the many Embedded Processors from TI to get started, help each
other innovate, and foster the growth of general knowledge about the hardware and software surrounding
these devices.

Register, Field, and Bit Calls
The naming convention applied for a call consists of:
• For a register call: .; for example: UART.UASR
• For a bit field call:
– .[End:Start] field; for example, UART.UASR[4:0]
SPEED bit field
– field .[End:Start]; for example, SPEED bit field
UART.UASR[4:0]
• For a bit call:
– .[pos] bit; for example, UART.UASR[5]
BIT_BY_CHAR bit
– bit .[pos]; for example, BIT_BY_CHAR bit
UART.UASR[5]

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Read This First

Chapter 1
SWCU117G – February 2015 – Revised February 2017

Architectural Overview
The CC26x0 and CC13x0 SimpleLink™ ultra-low power wireless MCU platforms provide solutions for a
wide range of applications. To help the user develop these applications, this user's guide focuses on the
use of the different building blocks of the devices. For detailed device descriptions, complete feature lists,
and performance numbers, see the data sheet for the specific device. The following subsections provide
easy access to relevant information and guide the reader to the different chapters in this document.
The CC26x0 and CC13x0 SimpleLink ultra-low power wireless MCU platform system-on-chips (SoCs) are
optimized for ultra-low power, while providing fast and capable MCU systems to enable short processing
times and high integration. The combination of an ARM® Cortex®-M3 processing core of up to 48 MHz,
flash memory, and a wide selection of peripherals makes the CC26x0 and CC13x0 device families ideal
for single-chip implementation or network processor implementations of lower power RF nodes.
Topic

1.1
1.2
1.3

...........................................................................................................................

Page

Target Applications ............................................................................................ 15
Overview ........................................................................................................... 15
Functional Overview ........................................................................................... 17

Architectural Overview

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Target Applications

www.ti.com

1.1

Target Applications
The CC26x0 and CC13x0 SimpleLink ultra-low power wireless MCU platforms are positioned for lowpower wireless applications such as:
•
•
•
•
•
•
•
•
•
•
•
•
•
•

1.2

Consumer electronics
Mobile phone accessories
Sports and fitness equipment
HID applications
Home and building automation
Lighting control
Alarm and security
Electronic shelf labeling
Proximity tags
Medical
Remote controls
Smart metering
Asset tracking
Wireless sensor networks

Overview
Figure 1-1 shows the building blocks of the CC26x0 and CC13x0 devices.
Figure 1-1. CC26x0 and CC13x0 Block Diagram

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Architectural Overview

Overview

www.ti.com

The CC26x0 and CC13x0 devices have the following features:
•

•

•
•

Cortex-M3 processor core
– 48-MHz RC oscillator and 24-MHz XTAL oscillator with an internal doubler
– 32-kHz XTAL oscillator, 32-kHz RC oscillator or low-power 24-MHz XTAL derivate clock for timing
maintenance while in low-power modes
– ARM Cortex SysTick timer
– Nested vectored interrupt controller (NVIC)
On-chip memory
– Flash with 8KB of 4-way set-associative cache RAM for speed and low power
– System RAM with configurable retention in 4-KB blocks
Power management
– Wide supply voltage range
– Efficient on-chip DC-DC converter for reduced power consumption
– High granularity clock gating and power gating of device parts
– Flexible frequency of operation
• Flexible low-power modes allowing low energy consumption in duty cycled applications
Sensor interface
– Autonomous, intelligent sensor interface that can wake up independently of the main CPU system
to perform sensor readings, collect data, and determine if the main CPU must be woken
– 12-bit analog-to-digital converter (ADC) with eight analog input channels
– Low-power analog comparator
– SPI or I2C master bit-banged
Advanced serial integration
– Universal asynchronous receiver/transmitter (UART)
– Inter-integrated circuit (I2C) module
– Synchronous serial interface modules (SSIs)
– Audio interface I2S module
System integration
– Direct memory access (DMA) controller
– Four 32-bit timers (up to eight 16-bit) with pulse width modulation (PWM) capability and
synchronization
– 32-kHz real-time clock (RTC)
– Watchdog timer
– On-chip temperature and supply voltage sensing
– GPIO with normal or high-drive capabilities
– GPIOs with analog capability for ADC and comparator
– Fully flexible digital pin muxing allows use as GPIO or any peripheral function
IEEE 1149.7 compliant 2-pin cJTAG with legacy 1149.1 JTAG support
4-mm × 4-mm, 5-mm × 5-mm, and 7-mm × 7-mm VQFN packages (5-mm × 5-mm not available for the
CC1350 device)

For applications requiring extreme conservation of power, the CC26x0 and CC13x0 devices feature a
power-management system to efficiently power down the CC26x0 or CC13x0 devices to a low-power state
during extended periods of inactivity. A power-up and power-down sequencer, a 32-bit sleep timer (an
RTC), with interrupt and 20KB of RAM with retention in all power modes positions the CC26x0 and
CC13x0 microcontroller perfectly for battery applications.

Architectural Overview

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Overview

www.ti.com

In addition, the CC26x0 and CC13x0 microcontroller offers the advantages of the widely available
development tools of ARM, SoC infrastructure IP applications, and a large user community. Additionally,
the microcontroller uses ARM Thumb®-compatible Thumb-2 instruction set to reduce memory
requirements and, thereby, cost.
TI offers a complete solution to get to market quickly, with evaluation and development boards, white
papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and
distributor network.

1.3

Functional Overview
The following subsections provide an overview of the features of the CC26x0 and CC13x0 microcontroller.

1.3.1 ARM® Cortex®-M3
The following subsections provide an overview of the Cortex-M3 processor core and instruction set, the
integrated system timer (SysTick), and the NVIC.
1.3.1.1

Processor Core

The CC26x0 and CC13x0 devices are designed around a Cortex-M3 processor core. The Cortex-M3
processor provides the core for a high-performance, low-cost platform that meets the needs of minimal
memory implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
Features of the processor core are as follows:
• 32-bit Cortex-M3 architecture optimized for small-footprint embedded applications
• Outstanding processing performance combined with fast interrupt handling
• Thumb-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM
core in a compact memory size, usually associated with 8- and 16-bit devices, typically in the range of
a few kilobytes of memory for microcontroller-class applications.
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
– Unaligned data access, enabling efficient packing of data into memory
• Fast code execution permits slower processor clock or increases sleep mode time
• Harvard architecture characterized by separate buses for instruction and data
• Efficient processor core, system, and memories
• Hardware division and fast multiplier
• Deterministic, high-performance interrupt handling for time-critical applications
• Enhanced system debug with extensive breakpoint capabilities and debugging through power modes
• Compact JTAG interface reduces the number of pins required for debugging
• Ultra-low power consumption with integrated sleep modes
• Up to 48-MHz operation

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Architectural Overview

Functional Overview

1.3.1.2

www.ti.com

System Timer (SysTick)

Cortex-M3 includes an integrated system timer (SysTick). SysTick provides a simple, 24-bit, clear-onwrite, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in
several different ways; for example:
• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
• A high-speed alarm timer using system clock 11
• A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and
the dynamic range of the counter
• A simple counter used to measure time to completion and time used
• An internal clock-source control based on missing or meeting durations
1.3.1.3

Nested Vector Interrupt Controller (NVIC)

The CC26x0 and CC13x0 device controller includes the ARM NVIC. The NVIC and Cortex-M3 prioritize
and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an
exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The
interrupt vector is fetched in parallel to state saving, thus enabling efficient interrupt entry. The processor
supports tail-chaining, that is, back-to-back interrupts can be performed without the overhead of state
saving and restoration. Software can set eight priority levels on seven exceptions (system handlers) and
can set CC26x0 and CC13x0 device interrupts.
Features of the NVIC are as follows:
• Deterministic, fast interrupt processing
– Always 12 cycles, or just 6 cycles with tail-chaining
• External nonmaskable interrupt (NMI) signal available for immediate execution of NMI handler for
safety-critical applications
• Dynamically reprioritizable interrupts
• Exceptional interrupt handling through hardware implementation of required register manipulations
1.3.1.4

System Control Block

The system control block (SCB) provides system implementation information and system control
(configuration, control, and reporting of system exceptions).

1.3.2 On-chip Memory
The following subsections describe the on-chip memory modules.
1.3.2.1

SRAM

The CC26x0 and CC13x0 devices provide low leakage on-chip SRAM with optional retention in all power
modes. Retention can be configured per block, and the device contains two blocks of 6KB and two blocks
of 4KB. Additionally, the flash cache RAM can be reconfigured to operate as normal system RAM.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding
technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory
map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic
operation.
Data can be transferred to and from the SRAM using the micro DMA (µDMA) controller.

Architectural Overview

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Overview

www.ti.com

1.3.2.2

Flash Memory

The flash block provides an in-circuit, programmable, nonvolatile program memory for the device. The
flash memory is organized as a set of 4-KB pages that can be individually erased. Erasing a block causes
the entire contents of the block to be reset to all 1s. These pages can be individually protected. Read-only
blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. In
addition to holding program code and constants, the nonvolatile memory allows the application to save
data that must be preserved so that it is available after restarting the device. Using this feature lets the
user use saved network-specific data to avoid the need for a full start-up and network find-and-join
process.
1.3.2.3

ROM

The ROM is preprogrammed with a boot sequence, device driver functions, low-level protocol stack
components, and a serial bootloader (SPI or UART).

1.3.3 Radio
The CC26x0 device family provides a highly integrated low-power 2.4-GHz radio transceiver with support
for multiple modulations and packet formats. The CC13x0 provides similar functionality optimized for the
Sub-1 GHz bands (CC1310) and also allows limited operation in the 2.4-GHz band (CC1350). The radio
subsystem provides an interface between the MCU and the radio, which makes it possible to issue
commands, read status, and automate and sequence radio events.

1.3.4 Advanced Encryption Standard (AES) Engine With 128-bit Key Support
The security core of the CC26x0 and CC13x0 devices features an AES module with 128-bit key support,
local key storage, and DMA capability.
Features of the AES engine are as follows:
• CCM, CTR, CBC-MAC, and ECB modes of operation
• 118-Mbps throughput
• Secure key storage memory
• Low latency

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Architectural Overview

Functional Overview

www.ti.com

1.3.5 General-Purpose Timers
General-purpose timers can be used to count or time external events that drive the timer-input pins. Each
16- or 32-bit GPTM block provides two 16-bit timers or counters that can be configured to operate
independently as timers or event counters, or configured to operate as one 32-bit timer.
The general-purpose timer module (GPTM) contains four 16- or 32-bit GPTM blocks with the following
functional options:
• 16- or 32-bit operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM
signal
• Count up or down
• Four 32-bit counters or up to eight 16-bit counters
• Up to eight capture/compare pins
• Up to four PWM pins (one PWM pin per 32-bit timer)
• Daisy-chaining of timer modules allows a single timer to initiate multiple timing events
• Timer synchronization allows selected timers to start counting on the same clock cycle
• User-enabled stalling when the microcontroller asserts CPU halt flag during debug
• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the ISR
• Efficient transfers using the µDMA controller
1.3.5.1

Watchdog Timer

The watchdog timer is used to regain control when the system fails because of a software error or an
external device fails to respond properly. The watchdog timer can generate an interrupt or a reset when a
predefined time-out value is reached.
1.3.5.2

Always-on Domain

The AON domain contains circuitry that is always enabled, except for the shutdown mode (where the
digital supply is off). This domain includes the following:
• The RTC can be used to wake the CC26x0 and CC13x0 devices from any state where it is active. The
RTC contains three match registers and one compare register. With software support, the RTC can be
used for clock and calendar operation. The RTC is clocked from the 32-kHz RC oscillator or the
32-kHz crystal oscillator.
• The battery monitor and temperature sensors are accessible by software. The battery monitor and
temperature sensors provide continuous monitoring of battery state as well as coarse temperature.

1.3.6 Direct Memory Access
The CC26x0 and CC13x0 microcontroller includes a DMA controller, known as DMA. The DMA
controller provides a way to offload data transfer tasks from the Cortex-M3 processor, allowing more
efficient use of the processor and the available bus bandwidth. The DMA controller can perform transfers
between memory and peripherals. Channels in the DMA are dedicated for each supported on-chip
module and can be programmed to automatically perform transfers between peripherals and memory,
because the peripheral is ready to transfer more data.

Architectural Overview

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Overview

www.ti.com

1.3.7 System Control and Clock
System control determines the overall operation of the CC26x0 and CC13x0 devices. System control
provides information about the CC26x0 and CC13x0 devices, controls power-saving features, controls the
clocking of the CC26x0 and CC13x0 devices and individual peripherals, and handles reset detection and
reporting.
• Power control:
– On-chip fixed DC-DC converter and low drop-out (LDO) voltage regulators
– Handles the power-up sequencing, power-down sequencing, and control for the core digital-logic
and analog circuits
– Low-power options for the CC26xx microcontroller
– Low-power options for on-chip modules:
• Software controls shutdown of individual peripherals and memory
• 20KB of RAM and configuration registers are retained in all power modes
– Control-pin option for control of external DC-DC regulator
– Configurable wake up from sleep timer or any GPIO interrupt
– Voltage supervision circuitry
• Multiple clock sources for microcontroller system clock:
– RC oscillator (HSRCOSC):
• On-chip resource providing a 48-MHz frequency
• The 24-MHz crystal oscillator (HSXOSC) is a frequency-accurate clock source from an external
crystal connected across the X24M_P input and X24M_N output pins.
• The internal 32-kHz RC oscillator is an on-chip resource providing a 32-kHz frequency, used
during power-saving modes and for RTC.
• The 32.768-kHz crystal oscillator is a frequency-accurate clock source from an external crystal
connected across the X32K_Q1 input and X32K_Q2 output pins
• Ideal for accurate RTC operation or synchronous network timing
• An external 32.768-kHz clock signal can be supplied by using one of the DIO pins as clock
input.
– CPU and periphery clock division options

1.3.8 Serial Communication Peripherals
The CC26x0 and CC13x0 devices support both asynchronous and synchronous serial communication
including:
• UART
• I2C
• I2S
• SSI (SPI)
The following subsections provide more detail on each of the communication functions.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Architectural Overview

Functional Overview

1.3.8.1

www.ti.com

UART

A UART is an integrated circuit used for RS-232C serial communications. A UART contains a transmitter
(parallel-to-serial converter) and a receiver (serial-to-parallel converter); each is clocked separately.
The CC26x0 and CC13x0 microcontroller includes one fully programmable UART. The UART can
generate individually masked interrupts from the receive (RX), transmit (TX), modem flow control, and
error conditions. The module generates one combined interrupt when any of the interrupts are asserted
and are unmasked.
The UART has the following features:
• Programmable baud-rate generator allows speeds up to 3 Mbps
• Separate 32 × 8 TX FIFOs and 32 × 16 RX FIFOs reduce CPU interrupt service loading
• Programmable FIFO length, including 1-byte deep operation that provides conventional doublebuffered interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
• Line-break generation and detection
• Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation and detection
– One or two stop-bit generation
• Full modem-handshake support
• Programmable hardware flow control
• Standard FIFO-level interrupts
• Efficient transfers using the µDMA controller:
– Separate channels for TX and RX
– Receive single request asserted when data is in the FIFO; burst request asserted at programmed
FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
1.3.8.2

I2C

The I2C bus provides bidirectional data transfer through a 2-wire design (a serial data line SDA and a
serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and
ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system
testing and diagnostic purposes in product development and manufacturing.
Each device on the I2C bus can be designated as a master or a slave. Each I2C module supports both
sending and receiving data (as either a master or a slave) and can operate simultaneously (as both a
master and a slave). Both the I2C master and slave can generate interrupts.
The CC26x0 and CC13x0 microcontrollers include an I2C module with the following features:
•

•

Architectural Overview

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Overview

www.ti.com

•

•
•

1.3.8.3

Two transmission speeds:
– Standard (100 kbps)
– Fast (400 kbps)
Clock low time-out interrupt
Master and slave interrupt generation:
– Master generates interrupts when a TX or RX operation completes (or aborts due to an error)
– Slave generates interrupts when data is transferred or requested by a master or when a START or
STOP condition is detected
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode
I2S

An I2S module enables the CC26x0 and CC13x0 devices to communicate with external devices like
codecs, DAC, ADCs, or DSPs. The CC26x0 and CC13x0 devices only support audio streaming formats
like I2S, RJF, LJF, and DSP; the CC26x0 and CC13x0 devices do not support configuration of external
devices. The CC26x0 and CC13x0 devices support both external and internally generated bit clock and
word clock (BCLK and WCLK).
1.3.8.4

SSI

An SSI module is a 4-wire bidirectional communications interface that converts data between parallel and
serial. The SSI performs serial-to-parallel conversion on data received from a peripheral device and
performs parallel-to-serial conversion on data transmitted to a peripheral device. The SSI can be
configured as either a master or slave device. As a slave device, the SSI can be configured to disable its
output, which allows coupling of a master device with multiple slave devices. The TX and RX paths are
buffered with separate internal FIFOs.
The SSI also includes a programmable bit rate clock divider and prescaler to generate the output serial
clock derived from the input clock of the SSI. Bit rates are generated based on the input clock, and the
maximum bit rate is determined by the connected peripheral.
The CC26x0 and CC13x0 devices include two SSI modules with the following features:
• Programmable interface operation for Freescale SPI, MICROWIRE, or TI synchronous serial interfaces
• Master or slave operation
• Programmable clock bit rate and prescaler
• Separate TX and RX FIFOs, each 16 bits wide and 8 locations deep
• Programmable data-frame size from 4 bits to 16 bits
• Internal loopback test mode for diagnostic and debug testing
• Standard FIFO-based interrupts and EoT interrupt
• Efficient transfers using the µDMA controller:
– Separate channels for TX and RX
– Receive single request asserted when data is in the FIFO; burst request is asserted when FIFO
contains four entries
– Transmit single request asserted when there is space in the FIFO; burst request is asserted when
FIFO contains four entries

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Architectural Overview

Functional Overview

www.ti.com

1.3.9 Programmable I/Os
I/O pins offer flexibility for a variety of connections. The CC26x0 and CC13x0 devices support highly
configurable I/O pins that can be muxed to any digital peripheral through the I/O Controller.
NOTE: Analog functionality, Sensor Controller connections, and high-drive strength is limited to
certain pins. Refer to Chapter 11 for details.

•
•
•
•

•
•
•
•
•

Up to 31 GPIOs, depending on configuration
Up to five 8-mA drive strength pins
Fully flexible digital pin muxing allows use as GPIO or any of several peripheral functions
Programmable control for GPIO interrupts:
– Interrupt generation masking per pin
– Edge-triggered on rising or falling
Bit masking in read and write operations through address lines
Can initiate a DMA transfer
Pin state can be retained during all sleep modes
Pins configured as digital inputs are Schmitt-triggered
Programmable control for GPIO pad configuration:
– Weak pullup or pulldown resistors
– Digital input enables

1.3.10 Sensor Controller
The sensor controller contains circuitry that can be selectively enabled in the power-down mode. The
peripherals in this domain may be controlled by the sensor controller, which is a proprietary poweroptimized CPU (sensor controller engine), or directly from the main CPU. The sensor controller engine
CPU can read and monitor sensors or perform other tasks autonomously, thereby reducing power
consumption and offloading the main CPU.
The sensor controller is set up using a PC-based configuration tool, and typical use cases may be (but not
limited to) the following:
• Analog sensors using integrated ADC
• Digital sensors using GPIO with bit-banged I2C and SPI
• Capacitive sensing
• Waveform generation
• Keyboard scan
• Quadrature decoder for polling rotation sensors
• Oscillator calibration
The peripherals in the sensor interface include the following:
• Analog comparator
The ultra-low power analog comparator can wake the CC26x0 and CC13x0 devices from any active
state. A configurable internal reference can be used with the comparator. The output of the
comparator can also trigger an interrupt or trigger the ADC.
• Capacitive sensing
Capacitive sensing is not a stand-alone module in the CC26x0 and CC13x0 devices; rather, the
functionality is achieved through the use of a constant current source, a time to digital converter,
and a comparator. The analog comparator in this block can also be used as a higher-accuracy
alternative to the ultra-low power comparator. The sensor controller takes care of baseline tracking,
hysteresis, filtering, and other related functions.

Architectural Overview

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Overview

www.ti.com

•

ADC
The ADC is a 12-bit, 200-ksamples/s ADC with 8 inputs and a built-in voltage reference. The ADC
can be triggered by many different sources including timers, I/O pins, software, the analog
comparator, and the RTC.
An ADC is a peripheral that converts a continuous analog voltage to a discrete digital number. The
ADC module features 12-bit conversion resolution and supports eight input channels plus an
internal division of the battery voltage and a temperature sensor.
Low-power SPI-I2C digital sensor interface
The sensor controller also includes a low-power SPI-I2C digital sensor interface by using bitbanging from the sensor controller engine, which can be used to periodically check digital sensors
and wake up the CC26x0 and CC13x0 devices when certain criteria are met.
The analog modules can be connected to up to eight different I/Os.

1.3.11 Random Number Generator
The random number generator generates true random numbers for backoff calculations or security keys.

1.3.12 cJTAG and JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits. The JTAG port also provides a standardized
serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data
Registers (DR) can be used to test the interconnections of assembled printed circuit boards (PCBs) and
obtain manufacturing information on the components. The JTAG port also provides a means of accessing
and controlling design-for-test features such as I/O pin observation and control, scan testing, and
debugging. The compact JTAG (cJTAG) interface has the following features:
• IEEE 1149.1-1990-compatible TAP controller
• IEEE 1149.7 cJTAG interface
• ICEPick JTAG router
• 4-bit IR chain for storing JTAG instructions
• IEEE standard instructions: BYPASS, IDCODE, SAMPLE and PRELOAD, EXTEST and INTEST
• ARM additional instructions: APACC, DPACC, and ABORT

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Architectural Overview

Functional Overview

www.ti.com

1.3.13 Power Supply System
1.3.13.1 Supply System
There are several voltage levels in use on the CC26x0 and CC13x0 device family. Figure 1-2 shows an
overview of the supply system.
Figure 1-2. CC26x0 and CC13x0 Supply System
VDDS
POR / BOD / Misc

Global LDO

IOs

Digital LDO
VDD

VDDS2
IOs

Micro LDO

VDDS3
IOs

VDDS_DCDC
AON_VD

DCDC_SW
DC/DC Converter

MCU_VD

VDDR

VDDR_RF
Oscillators

RF LDOs
DCOUPL

1.3.13.1.1 VDDS
The battery voltage on the CC26x0 and CC13x0 device family is called VDDS (supply). This supply has
the highest potential in the system and typically is the only one provided by the user.

Architectural Overview

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Overview

www.ti.com

1.3.13.1.2 VDDR
The two VDDR (regulated) pins are normally powered from one of the internal regualtors. For lowest
power, TI recommends using the internal DC-DC regulator (see the reference designs and
Section 1.3.13.2 for further details on this configuration).
Using the Global LDO is also an option. In this case the two VDDR pins must be tied together. In this
case, VDDR should have a 10-µF decoupling capacitor, whereas VDDR_RF should have the decoupling
recommended in the various reference designs. In this setup, VDDS_DCDC should be tied to VDDS and
DCDC_SW should be left floating.
1.3.13.1.3 Digital Core Supply
The digital core of the CC26x0 and CC13x0 devices is supplied by a 1.28-V regulator connected to VDDR.
The output of this regulator requires an external decoupling capacitor for proper operation; this capacitor
must be connected to the DCOUPL pin.
NOTE: The DCOUPL pin cannot be used to supply external circuitry.

When the system is in power down, a small low-power regulator (micro LDO) with limited current capacity
supplies the digital domain to ensure enabled modules still have power.
1.3.13.1.4 Other Internal Supplies
Several other modules in the device (such as the frequency synthesizer, RF power amplifier, and so forth)
have separate internal regulators running at either 1.4-V (analog modules) or 1.28-V (digital modules).
These regulators are powered up or down automatically by firmware when needed.
1.3.13.2 DC-DC Converter
The on-chip buck-mode DC-DC converter provides a simple way to reduce the power consumption of the
device. The DC-DC converter is integrated into the supply system and handles bias and clocks
automatically through the system controller.
The DC-DC converter is controlled through the AON_SYSCTL:PWRCTL register.
To enable the DC-DC converter when the system is active, the AON_SYSCTL:PWRCTL.DCDC_ACTIVE
bit must be set. The DC-DC converter is also used periodically when the device is in Standby mode to
maintain voltage on the VDDR domain.
The output voltage of the DC-DC regulator is typically trimmed to 1.68 V, but there are use cases where
other voltage levels are used. The voltage levels are controlled automatically by the device and cannot be
changed by the user.
NOTE: The DC-DC regulator output cannot be used to supply external circuitry.

1.3.13.3 External Regulator Mode (1.8-V Supply Voltage Mode)
The CC26x0 and CC13x0 devices can be used in 1.8-V systems in a special power supply setup called
External Regulator Mode. In this setup the VDDS and VDDR pins are tied together and the DC-DC
regulator is disabled. The VDDS_DCDC and DCDC_SW pins must be connected to ground. Additionally
appropriate registers in CCFG must be configured. It is possible to check that the device has booted
properly into external regulator mode by reading the AON_SYSCTL:PWRCTL.EXT_REG_MODE register
field.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Architectural Overview

Chapter 2
SWCU117G – February 2015 – Revised February 2017

The ARM® Cortex®-M3 Processor
The CC26x0 and CC13x0 family of microcontrollers builds on the ARM® Cortex®-M3 core to bring highperformance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory
automation and control, industrial control power devices, building and home automation, and stepper
motor control.
This chapter provides information on the CC26x0 and CC13x0 implementation of the Cortex-M3
processor.
For technical details on the instruction set, see Cortex-M3/M4F Instruction Set Technical User's Manual.
Topic

2.1
2.2
2.3
2.4
2.5
2.6
2.7

...........................................................................................................................
The Cortex-M3 Processor Introduction .................................................................
Block Diagram ...................................................................................................
Overview ...........................................................................................................
Programming Model ...........................................................................................
Cortex-M3 Core Registers ...................................................................................
Instruction Set Summary .....................................................................................
Cortex-M3 Processor Registers ...........................................................................

The ARM® Cortex®-M3 Processor

Page

29
29
30
31
33
47
51

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

The Cortex-M3 Processor Introduction

www.ti.com

2.1

The Cortex-M3 Processor Introduction
The Cortex-M3 processor provides a high-performance, low-cost platform that meets the system
requirements of minimal memory implementation, reduced pin count, and low-power consumption. The
following features are included:
•
•
•

•
•
•
•
•
•
•
•

•
•

•
•
•

2.2

32-bit Cortex-M3 architecture optimized for small-footprint, embedded applications
Outstanding processing performance combined with fast interrupt handling
ARM Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the
range of a few kilobytes of memory for microcontroller-class applications:
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
– Unaligned data access, enabling efficient packing of data into memory
Fast code execution permits slower processor clock or increases sleep mode time
Harvard architecture characterized by separate buses for instruction and data
Efficient processor core, system, and memories
Hardware division and fast digital signal processing oriented multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Enhanced system debug with extensive breakpoint and trace capabilities
Full debug with data matching for watchpoint generation
– DWT
– JTAG debug port
– FPB
Migration from the ARM7™ processor family for better performance and power efficiency
Standard trace support
– ITM
– TPIU with asynchronous serial wire output (SWO)
Optimized for single-cycle flash memory use
Ultra-low power consumption with integrated sleep modes
48-MHz operation

Block Diagram
Figure 2-1 shows the core processor unit (CPU) block diagram. The Cortex-M3 processor is built on a
high-performance processor core with a 3-stage pipeline Harvard architecture, thus it is ideal for
demanding embedded applications. The processor delivers exceptional power efficiency through an
efficient instruction set and extensively optimized design, which provides high-end processing hardware.
The instruction set includes a range of single-cycle and SIMD multiplication and multiply-with-accumulate
capabilities, saturating arithmetic, and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled
system components that reduce processor area while significantly improving interrupt handling and
system-debug capabilities. The Cortex-M3 processor implements a version of the Thumb instruction set
based on Thumb-2 technology; thus ensuring high code density and reduced program-memory
requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern
32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

The ARM® Cortex®-M3 Processor

Overview

www.ti.com

The Cortex-M3 processor closely integrates a nested vector interrupt controller (NVIC) to deliver fast
execution of interrupt service routines (ISRs) thereby dramatically reducing interrupt latency. The
hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations
further reduces interrupt latency. Interrupt handlers do not require any assembler stubs, thus removing
code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when
switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep
modes, including deep-sleep mode, which enables the entire device to be rapidly powered down.
Figure 2-1. CPU Block Diagram
Trace Data

CM3 Core

tInterruptst
NVIC

Trace Port
Interface
Unit

tSleept
Instructions

tDebugt

Trace Clock
To IOC

Data
Serial Wire
Viewer (SWV)

CPU_TIPROP_TRACECLKMUX
Register

Flash Patch
and
Breakpoint

Data
Watchpoint
and Trace

Instrumentation
Trace Macrocell

ROM
Table

Serial Wire JTAG
Debug Port

2.3

Bus Matrix

Advance
Peripheral Bus

Debug
Access Port

tI-code Bust
tD-code Bust
tSystem Bust

Overview

2.3.1 System-level Interface
The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide high-speed,
low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit
manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data
handling.

2.3.2 Integrated Configurable Debug
The Cortex-M3 processor implements a complete hardware-debug solution through a Serial Wire or JTAG
Debug Port (SWJ-DP) module. SWJ-DP provides a high system visibility of the processor and memory
through a traditional JTAG port. See Chapter 5 and the ARM® Debug Interface V5 Architecture
Specification for details on SWJ-DP.
For system trace, the processor integrates an instrumentation trace macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a
serial wire viewer (SWV) can export a stream of software-generated messages, data trace, and profiling
information through one pin.

The ARM® Cortex®-M3 Processor

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Overview

www.ti.com

The flash patch and breakpoint unit (FPB) provides up to eight hardware-breakpoint comparators that
debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the
program code in the CODE memory region. Remap functions enable patching of applications stored in a
read-only area of flash memory into another area of on-chip SRAM or flash memory. If a patch is required,
the application programs the FPB to remap a number of addresses. When those addresses are accessed,
the accesses are redirected to a remap table specified in the FPB configuration.
For more information on the Cortex-M3 debug capabilities, see the ARM® Debug Interface V5 Architecture
Specification.

2.3.3 Trace Port Interface Unit
Figure 2-2 shows the trace port interface unit (TPIU) block diagram. The TPIU acts as a bridge between
the Cortex-M3 trace data from the ITM, and an off-chip trace port analyzer.
Figure 2-2. TPIU Block Diagram
CPU_TIPROP_TRACECLKMUX
Register

Serial Wire
Viewer (SWV)
To IOC
Debug ATB
Slave Port

ATB
Interface

Asynchronous FIFO

Trace Out
(Serializer)

Trace Clock
Trace Data

APB Slave
Port

APB
Interface

See CM3_TIPROP for more information.

2.3.4 Cortex-M3 System Component Details
The Cortex-M3 includes the following system components:
• SysTick: A 24-bit count-down timer that can be used as a real-time operating system (RTOS) tick
timer or as a simple counter (see Section 3.2.1)
• Nested Vectored Interrupt Controller: An embedded interrupt controller (INTC) that supports lowlatency interrupt processing (see Section 3.2.2)
• System Control Block: The programming model interface to the processor, which provides system
implementation information and system control, including configuration, control, and reporting of
system exceptions (see Section 3.2.3). Key control and status features of the processor are managed
centrally in SCB within the system control space (SCS).

2.4

Programming Model
This section describes the Cortex-M3 programming model. For more information about the processor
modes and privilege levels for software execution and stacks and for descriptions of the individual core
registers, see Section 2.5.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

The ARM® Cortex®-M3 Processor

Programming Model

www.ti.com

2.4.1 Processor Mode and Privilege Levels for Software Execution
The Cortex-M3 processor has two modes of operation:
• Thread mode executes application software. The processor enters thread mode when it comes out of
reset.
• Handler mode handles exceptions. When the processor completes exception processing, it returns to
thread mode.
In addition, the Cortex-M3 processor has two privilege levels, unprivileged and privileged.
• In unprivileged mode, software has the following restrictions:
– Limited access to the MSR and MRS instructions and no use of the CPS instruction
– No access to the system timer, NVIC, or SCB
• In privileged mode, software can use all the instructions and has access to all resources in the
processor.
In thread mode, the CONTROL register (see Table 2-24) controls whether software execution is privileged
or unprivileged. In handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software
execution in thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to
transfer control to privileged software.

2.4.2 Stacks
The Cortex-M3 processor uses a full descending stack, meaning that the stack pointer indicates the last
stacked item on the memory. When the processor pushes a new item onto the stack, it decrements the
stack pointer and then writes the item to the new memory location. The processor implements two stacks,
the main stack and the process stack, with a pointer for each held in independent registers (see the SP
register in Table 2-16).
In thread mode, the CONTROL register (see Table 2-24) controls whether the processor uses the main
stack or the process stack. In handler mode, the processor always uses the main stack. Table 2-1 lists the
options for processor operations.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode

Use

Privilege Level

Thread

Applications

Privileged or unprivileged

Handler

Exception handlers

Always privileged

(1)

Stack Used
(1)

Main stack or process stack
Main stack

See the CONTROL register (Table 2-24).

2.4.3 Exceptions and Interrupts
An exception changes the normal flow of software control. The support for interrupts and system
exceptions is implemented by using the built-in NVIC, which supports up to 240 external interrupt inputs.
Besides the external interrupts, the Cortex-M3 also services 16 predefined exception sources including
Reset, NMI, and so on. The processor and the NVIC prioritize and handle all exceptions. The processor
uses handler mode to handle all exceptions, except for reset. Software configures the actual priorities
assigned to NVIC external interrupt inputs through registers.

2.4.4 Data Types
The Cortex-M3 processor supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also
supports 64-bit data transfer instructions. All instruction and data memory accesses are little endian. For
more information, see Cortex-M3/M4F Instruction Set Technical User's Manual.

The ARM® Cortex®-M3 Processor

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers

www.ti.com

2.5

Cortex-M3 Core Registers
Figure 2-3 shows the Cortex-M3 register set. Table 2-2 lists the core registers. The core registers are not
memory mapped and are accessed by register name, so the base address is N/A (not applicable) and
there is no offset.
Figure 2-3. Cortex-M3 Register Set
R0
R1
R2
Low registers

R3
R4
R5
R6

General-purpose registers

R7
R8
R9
High registers

R10
R11
R12

Stack pointer

SP (R13)

Link register

LR (R14)

Program counter

PC (R15)
PSR

PSP

MSP

See Note.

Program status register

PRIMASK
FAULTMASK

Exception mask registers

Special registers

BASEPRI
CONTROL

Control register

Note: Banked version of SP

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

The ARM® Cortex®-M3 Processor

Cortex-M3 Core Registers

www.ti.com

2.5.1 Core Register Map
Table 2-2. Processor Register Map
Name

Type

Reset

Description

Link

R/W

—

Cortex general-purpose register 0

See Section 2.5.2.1.

R/W

—

Cortex general-purpose register 1

See Section 2.5.2.2.

R/W

—

Cortex general-purpose register 2

See Section 2.5.2.3.

R/W

—

Cortex general-purpose register 3

See Section 2.5.2.4.

R/W

—

Cortex general-purpose register 4

See Section 2.5.2.5.

R/W

—

Cortex general-purpose register 5

See Section 2.5.2.6.

R/W

—

Cortex general-purpose register 6

See Section 2.5.2.7.

R/W

—

Cortex general-purpose register 7

See Section 2.5.2.8.

R/W

—

Cortex general-purpose register 8

See Section 2.5.2.9.

R/W

—

Cortex general-purpose register 9

See Section 2.5.2.10.

R10

R/W

—

Cortex general-purpose register 10

See Section 2.5.2.11.

R11

R/W

—

Cortex general-purpose register 11

See Section 2.5.2.12.

R12

R/W

—

Cortex general-purpose register 12

See Section 2.5.2.13.

R/W

–

Stack pointer

See Section 2.5.2.14.

R/W

0xFFFF FFFF

Link register

See Section 2.5.2.15.

R/W

—

Program counter

See Section 2.5.2.16.

PSR

R/W

0x0100 0000

Program status register

See Section 2.5.2.17.

PRIMASK

R/W

0x0000 0000

Priority mask register

See Section 2.5.2.18.

FAULTMASK

R/W

0x0000 0000

Fault mask register

See Section 2.5.2.19.

BASEPRI

R/W

0x0000 0000

Base priority mask register

See Section 2.5.2.20.

CONTROL

R/W

0x0000 0000

Control register

See Section 2.5.2.21.

2.5.2 Core Register Descriptions
This section lists and describes the Cortex-M3 registers, in the order listed in Figure 2-3. The core
registers are not memory mapped and are accessed by register name rather than offset.
See CM3_TIPROP for more information.
NOTE:

2.5.2.1

The register type shown in the register descriptions refers to type during program
execution in thread mode and handler mode. Debug access can differ.

Cortex General-Purpose Register 0 (R0)
Table 2-3. Cortex General-Purpose Register 0 (R0)

Address Offset

Reset

Physical Address

Instance

–

Description

The R0 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA

Bits

Field Name

Description

Type

Reset

31-0

DATA

R/W

—

The ARM® Cortex®-M3 Processor

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers

www.ti.com

2.5.2.2

Cortex General-Purpose Register 1 (R1)
Table 2-4. Cortex General-Purpose Register 1 (R1)

Address Offset

Reset

Physical Address

–

Instance

Description

The R1 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31–0

DATA

R/W

—

2.5.2.3

Cortex General-Purpose Register 2 (R2)
Table 2-5. Cortex General-Purpose Register 2 (R2)

Address Offset

Reset

Physical Address

–

Instance

Description

The R2 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31–0

DATA

R/W

—

2.5.2.4

Cortex General-Purpose Register 3 (R3)
Table 2-6. Cortex General-Purpose Register 3 (R3)

Address Offset

Reset

Physical Address

Instance

–

Description

The R3 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31–0

DATA

R/W

—

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers

2.5.2.5

www.ti.com

Cortex General-Purpose Register 4 (R4)
Table 2-7. Cortex General-Purpose Register 4 (R4)

Address Offset

Reset

Physical Address

–

Instance

Description

The R4 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31–0

DATA

R/W

—

2.5.2.6

Cortex General-Purpose Register 5 (R5)
Table 2-8. Cortex General-Purpose Register 5 (R5)

Address Offset

Reset

Physical Address

–

Instance

Description

The R5 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31–0

DATA

R/W

—

2.5.2.7

Cortex General-Purpose Register 6 (R6)
Table 2-9. Cortex General-Purpose Register 6 (R6)

Address Offset

Reset

Physical Address

Instance

–

Description

The R6 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA

Bits

Field Name

Description

Type

Reset

31–0

DATA

R/W

—

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers

www.ti.com

2.5.2.8

Cortex General-Purpose Register 7 (R7)
Table 2-10. Cortex General-Purpose Register 7 (R7)

Address Offset

Reset

Physical Address

–

Instance

Description

The R7 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31–0

DATA

R/W

—

2.5.2.9

Cortex General-Purpose Register 8 (R8)
Table 2-11. Cortex General-Purpose Register 8 (R8)

Address Offset

Reset

Physical Address

–

Instance

Description

The R8 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31–0

DATA

R/W

—

2.5.2.10 Cortex General-Purpose Register 9 (R9)
Table 2-12. Cortex General-Purpose Register 9 (R9)
Address Offset

Reset

Physical Address

Instance

–

Description

The R9 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31–0

DATA

R/W

—

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers

www.ti.com

2.5.2.11 Cortex General-Purpose Register 10 (R10)
Table 2-13. Cortex General-Purpose Register 10 (R10)
Address Offset

Reset

Physical Address

–

Instance

Description

The R10 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31–0

DATA

R/W

—

2.5.2.12 Cortex General-Purpose Register 11 (R11)
Table 2-14. Cortex General-Purpose Register 11 (R11)
Address Offset

Reset

Physical Address

–

Instance

Description

The R11 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31–0

DATA

R/W

—

2.5.2.13 Cortex General-Purpose Register 12 (R12)
Table 2-15. Cortex General-Purpose Register 12 (R12)
Address Offset

Reset

Physical Address

Instance

–

Description

The R12 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA

Bits

Field Name

Description

Type

Reset

31–0

DATA

R/W

—

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers

www.ti.com

2.5.2.14 Stack Pointer (SP)
Table 2-16. Stack Pointer (SP)
Address Offset

Reset

Physical Address

Instance

–

Description
The Stack Pointer (SP) is register R13. In thread mode, the function of this register changes depending on the ASP bit in the Control
Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this
register is the Process Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address
0x0000 0000. The MSP can only be accessed in privileged mode; the PSP can be accessed in either privileged or unprivileged mode.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

SP
Bits

Field Name

Description

Type

Reset

31–0

This field is the address of the stack pointer.

R/W

—

2.5.2.15 Link Register (LR)
Table 2-17. Link Register (LR)
Address Offset

Reset

Physical Address

Instance

0xFFFF FFFF

Description
The Link Register (LR) is register R14, and it stores the return information for subroutines, function calls, and exceptions. LR can be
accessed from either privileged or unprivileged mode.
EXC_RETURN is loaded into LR on exception entry. See Table 4-3 for the values and description.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

LINK
Bits

Field Name

Description

Type

Reset

31–0

LINK

This field is the return address.

R/W

0xFFFF FFFF

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers

www.ti.com

2.5.2.16 Program Counter (PC)
Table 2-18. Program Counter (PC)
Address Offset

Reset

Physical Address

Instance

–

Description
The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the
value of the reset vector, which is at address 0x0000 0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR register at
reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

PC
Bits

Field Name

Description

Type

Reset

31–0

This field is the current program address.

R/W

—

2.5.2.17 Program Status Register (PSR)
Table 2-19. PSR Combinations
Register

Type

PSR

R/W

IEPSR

EPSR and IPSR

IAPSR

R/W

APSR and IPSR

EAPSR

R/W

APSR and EPSR

(1)
(2)

Combination

(1) (2)

APSR, EPSR, and IPSR

Reads of the EPSR bits directly using the MSR instruction return 0, and the processor ignores writes to these bits.
The processor ignores writes to the IPSR bits.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers

www.ti.com

Table 2-20. Program Status Register (PSR) or (xPSR)
Address Offset

Reset

Physical Address

Instance

0x0100 0000

Description
Also referred to as xPSR
The
•
•
•

Program Status Register (PSR) has three functions, and the register bits are assigned to the different functions:
Application Program Status Register (APSR), bits 31–27
Execution Program Status Register (EPSR), bits 26–24, 15–10
Interrupt Program Status Register (IPSR), bits 6–0

The PSR, IPSR, and EPSR registers can be accessed only in privileged mode; the APSR register can be accessed in privileged or
unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the if-then (IT) instruction or the interruptible-continuable instruction (ICI)
field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the
MSR instruction always return 0. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault
handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see Section 4.1.7, Exception Entry and
Return).
IPSR contains the exception type number of the current ISR.
These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument
to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be
written to using APSR with the MSR instruction. Table 2-20 shows the possible register combinations for the PSR. See the MRS and MSR
instruction descriptions in Cortex-M3/M4F Instruction Set Technical User's Manual for more information about how to access the program
status registers.
R/W

Bits
31

ICI / IT

THUMB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RESERVED

Field Name

Description

APSR Negative or Less Flag

ICI / IT

RESERVED

Type

Value

Description

The previous operation result was negative or less
than.

The previous operation result was positive, zero,
greater than, or equal

ISRNUM

Type

Reset

R/W

The value of this bit is meaningful only when accessing PSR or
APSR.
30

APSR Zero Flag
Value

Description

The previous operation result was zero.

The previous operation result was nonzero.

The value of this bit is meaningful only when accessing PSR or
APSR.
29

APSR Carry or Borrow Flag
Value

Description

The previous add operation resulted in a carry bit or
the previous subtract operation did not result in a
borrow bit.

The previous add operation did not result in a carry
bit or the previous subtract operation resulted in a
borrow bit.

The value of this bit is meaningful only when accessing PSR or
APSR.
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers
Bits
28

www.ti.com

Field Name

Description

APSR Overflow Flag
Value

Description

The previous operation resulted in an overflow.

The previous operation did not result in an overflow.

Type

Reset

R/W

The value of this bit is meaningful only when accessing PSR or
APSR.
27

APSR Sticky Overflow and Saturation Flag
Value

Description

Overflow or saturation has occurred. (set by SSAT
or USAT instructions).

Overflow or saturation has not occurred since reset
or since the bit was last cleared.

The value of this bit is meaningful only when accessing PSR or
APSR.
This flag is sticky, in that, when set by an instruction it remains set
until explicitly cleared using an MSR instruction.
26–25

ICI / IT

EPSR ICI / IT status
These bits, along with bits 15:10, contain the ICI field for an
interrupted load multiple or store multiple instruction or the
execution state bits of the IT instruction. When EPSR holds the ICI
execution state, bits 26:25 are 0. The If-Then block contains up to
four instructions following an IT instruction. Each instruction in the
block is conditional. The conditions for the instructions are either all
the same, or some can be the inverse of others. See the Cortex™M3 Instruction Set Technical User's Manual for more information.
The value of this field is meaningful only when accessing PSR or
EPSR.

0x0

THUMB

EPSR Thumb state
This bit indicates the Thumb state and must always be set. The
following can clear the THUMB bit:

• The BLX, BX and POP{PC} instructions
• Restoration from the stacked xPSR value on an exception return
• Bit 0 of the vector value on an exception entry or reset
Attempting to execute instructions when this bit is clear results in a
fault or lockup. For more information, see Section 4.2.4. The value
of this bit is meaningful only when accessing PSR or EPSR.

23–16

RESERVED

Reserved

0x00

15–10

ICI / IT

EPSR ICI / IT status
These bits, along with bits 26:25, contain the ICI field for an
interrupted load multiple or store multiple instruction or the
execution state bits of the IT instruction. When an interrupt occurs
during the execution of an LDM, STM, PUSH, or POP instruction,
the processor stops the load multiple or store multiple instruction
operation temporarily and stores the next register operand in the
multiple operation to bits 15:12. After servicing the interrupt, the
processor returns to the register pointed to by bits 15:12 and
resumes execution of the multiple load or store instruction. When
EPSR holds the ICI execution state, bits 11:10 are 0. The If-Then
block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The
conditions for the instructions are either all the same, or some can
be the inverse of others. See Cortex-M3/M4F Instruction Set
Technical User's Manual for more information. The value of this field
is meaningful only when accessing PSR or EPSR.

0x0

9–7

RESERVED

Software must not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit must
be preserved across a read-modify-write operation.

0x0

6–0

ISRNUM

IPSR ISR Number
This field contains the exception type number of the current ISR.

0x00

Value

Description

0x00

Thread mode

0x01

Reserved
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers

www.ti.com
Bits

Field Name

Description

Type

0x02

NMI

0x03

Hard fault

0x04

Memory management fault

0x05

Bus fault

0x06

Usage fault

0x07–0x0A

Reserved

0x0B

SVCall

0x0C

Reserved for debug

0x0D

Reserved

0x0E

PendSV

0x0F

SysTick

0x10

Interrupt vector 0

0x11

Interrupt vector 1

...

0x31

Interrupt vector 33

0x32-0x7F

Reserved

Reset

For more information, see Section 4.1.2.
The value of this field is meaningful only when accessing PSR or
IPSR.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers

www.ti.com

2.5.2.18 Priority Mask Register (PRIMASK)
Table 2-21. Priority Mask Register (PRIMASK)
Address Offset

Reset

Physical Address

Instance

0x0000 0000

Description
The Priority Mask (PRIMASK) register prevents activation of all exceptions with programmable priority. Reset, nonmaskable interrupt (NMI),
and hard fault are the only exceptions with fixed priority. Exceptions must be disabled when they might impact the timing of critical tasks.
This register is accessible only in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS
instruction may be used to change the value of the PRIMASK register. For more information on these instructions, see Cortex-M3/M4F
Instruction Set Technical User's Manual . For more information on exception priority levels, see Section 4.1.2.
Type

R/W
9

RESERVED

Bits

Field Name

Description

Type

Reset

31–1

RESERVED

Software must not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit must
be preserved across a read-modify-write operation.

0x0000 000

PRIMASK

Priority Mask

R/W

0
PRIMASK

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Value

Description

Prevents the activation of all exceptions with configurable
priority

No effect

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers

www.ti.com

2.5.2.19 Fault Mask Register (FAULTMASK)
Table 2-22. Fault Mask Register (FAULTMASK)
Address Offset

Reset

Physical Address

Instance

0x0000 0000

Description
The Fault Mask FAULTMASK register prevents activation of all exceptions except for the NMI. Exceptions must be disabled when they
might impact the timing of critical tasks. This register is accessible only in privileged mode. The MSR and MRS instructions are used to
access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register. See CortexM3/M4F Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority
levels, see Section 4.1.2.
R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RESERVED

Bits

Field Name

Description

31–1

RESERVED

Reserved

FAULTMASK

Fault Mask
Value

Description

Prevents the activation of all exceptions except for NMI

No effect

0
FAULTMASK

Type

Reset

0x0000 000

R/W

The processor clears the FAULTMASK bit on exit from any
exception handler except the NMI handler.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Core Registers

www.ti.com

2.5.2.20 Base Priority Mask Register (BASEPRI)
Table 2-23. Base Priority Mask Register (BASEPRI)
Address Offset

Reset

Physical Address

Instance

0x0000 0000

Description
The Base Priority Mask BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value,
it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions must be disabled when
they might impact the timing of critical tasks. This register is accessible only in privileged mode. For more information on exception priority
levels, see Section 4.1.2.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RESERVED
Bits

Field Name

Description

31–8

RESERVED

7–5

BASEPRI

4–0

RESERVED

BASEPRI

RESERVED

Type

Reset

Reserved

0x0000 00

Base Priority
Any exception that has a programmable priority level with the same
or lower priority as the value of this field is masked. The PRIMASK
register can be used to mask all exceptions with programmable
priority levels. Higher priority exceptions have lower priority levels.

R/W

0x0

Value

Description

0x0

All exceptions are unmasked.

0x1

All exceptions with priority levels 1–7 are masked.

0x2

All exceptions with priority levels 2–7 are masked.

0x3

All exceptions with priority levels 3–7 are masked.

0x4

All exceptions with priority levels 4–7 are masked.

0x5

All exceptions with priority levels 5–7 are masked.

0x6

All exceptions with priority levels 6 and 7 are masked.

0x7

All exceptions with priority level 7 are masked.

Reserved

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Instruction Set Summary

www.ti.com

2.5.2.21 Control Register (CONTROL)
Table 2-24. Control Register (CONTROL)
Address Offset

Reset

Physical Address

Instance

0x0000 0000

Description
The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode. This
register is accessible only in privileged mode.
Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in handler mode.
The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value (see
Table 4-3). In an OS environment, threads running in thread mode must use the process stack and the kernel and exception handlers must
use the main stack. By default, thread mode uses MSP. To switch the stack pointer used in thread mode to PSP, either use the MSR
instruction to set the ASP bit, as detailed in the Cortex-M3/M4F Instruction Set Technical User's Manual, or perform an exception return to
thread mode with the appropriate EXC_RETURN value, as shown in Table 4-3.
When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction, ensuring that instructions
after the ISB instruction executes use the new stack pointer. See the Cortex-M3/M4F Instruction Set Technical User's Manual.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RESERVED

Bits

Field Name

Description

31–2

RESERVED
ASP

0
TMPL

R/W

ASP

Type

Reset

Reserved

0x0000 000

Active Stack Pointer

R/W

Value

Description

PSP is the current stack pointer.

MSP is the current stack pointer.

In handler mode, this bit reads as zero and ignores writes. The
Cortex-M3 updates this bit automatically on exception return.
0

2.6

TMPL

Thread Mode Privilege Level
Value

Description

Unprivileged software can be executed in thread mode.

Only privileged software can be executed in thread mode.

Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-25 lists the supported
instructions.
NOTE:

In Table 2-25:
• Angle brackets, <>, enclose alternative forms of the operand.
• Braces, {}, enclose optional operands.
• The Operands column is not exhaustive.
• Op2 is a flexible second operand that can be either a register or a constant.
• Most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction
descriptions in the Cortex-M3/M4F Instruction Set Technical User's Manual.

NOTE: Table 2-25 is copied from the Cortex™-M3 Instruction Set Technical User's Manual.
Changes made in the manual must be made in Table 2-25.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Instruction Set Summary

www.ti.com

Table 2-25. Cortex-M3 Instruction Summary
Mnemonic

Operands

Brief Description

Flags

ADC, ADCS

{Rd,} Rn, Op2

Add with carry

N, Z, C, V

ADD, ADDS

{Rd,} Rn, Op2

Add

N, Z, C, V

ADD, ADDW

{Rd,} Rn , #imm12

Add

N, Z, C, V

ADR

Rd, label

Load PC-relative address

–

AND, ANDS

{Rd,} Rn, Op2

Logical AND

N, Z, C

ASR, ASRS

Rd, Rm,

Arithmetic shift right

N, Z, C

label

Branch

–

BFC

Rd, #lsb, #width

Bit field clear

–

BFI

Rd, Rn, #lsb, #width

Bit field insert

–

BIC, BICS

{Rd,} Rn, Op2

Bit clear

N, Z, C

BKPT

#imm

Breakpoint

–

label

Branch with link

–

BLX

Branch indirect with link

–

Branch indirect

–

CBNZ

Rn, label

Compare and branch if nonzero

–

CBZ

Rn, label

Compare and branch if zero

–

CLREX

–

Clear exclusive

–

CLZ

Rd, Rm

Count leading zeros

–

CMN

Rn, Op2

Compare negative

N, Z, C, V

CMP

Rn, Op2

Compare

N, Z, C, V

CPSID

Change processor state, disable
interrupts

–

CPSIE

Change processor state, enable
interrupts

–

DMB

–

Data memory barrier

–

DSB

–

Data synchronization barrier

–

EOR, EORS

{Rd,} Rn, Op2

Exclusive OR

N, Z, C

ISB

–

Instruction synchronization barrier

–

If Then condition block

–

LDM

Rn{!}, reglist

Load multiple registers, increment after

–

LDMDB, LDMEA

Rn{!}, reglist

Load multiple registers, decrement
before

–

LDMFD, LDMIA

Rn{!}, reglist

Load multiple registers, increment after

–

LDR

Rt, [Rn, #offset]

Load register with word

–

LDRB, LDRBT

Rt, [Rn, #offset]

Load register with byte

–

LDRD

Rt, Rt2, [Rn, #offset]

Load register with 2 bytes

–

LDREX

Rt, [Rn, #offset]

Load register exclusive

–

LDREXB

Rt, [Rn]

Load register exclusive with byte

–

LDREXH

Rt, [Rn]

Load register exclusive with halfword

–

LDRH, LDRHT

Rt, [Rn, #offset]

Load register with halfword

–

LDRSB, LDRSBT

Rt, [Rn, #offset]

Load register with signed byte

–

LDRSH, LDRSHT

Rt, [Rn, #offset]

Load register with signed halfword

–

LDRT

Rt, [Rn, #offset]

Load register with word

–

LSL, LSLS

Rd, Rm,

Logical shift left

N, Z, C

LSR, LSRS

Rd, Rm,

Logical shift right

N, Z, C

MLA

Rd, Rn, Rm, Ra

Multiply with accumulate, 32-bit result

–

MLS

Rd, Rn, Rm, Ra

Multiply and subtract, 32-bit result

–

MOV, MOVS

Rd, Op2

Move

N, Z, C

MOV, MOVW

Rd, #imm16

Move 16-bit constant

N, Z, C

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Instruction Set Summary

www.ti.com

Table 2-25. Cortex-M3 Instruction Summary (continued)
Mnemonic

Operands

Brief Description

Flags

MOVT

Rd, #imm16

Move top

–

MRS

Rd, spec_reg

Move from special register to general
register

–

MSR

spec_reg, Rm

Move from general register to special
register

N, Z, C, V

MUL, MULS

{Rd,} Rn, Rm

Multiply, 32-bit result

N, Z

MVN, MVNS

Rd, Op2

Move NOT

N, Z, C

NOP

–

No operation

–

ORN, ORNS

{Rd,} Rn, Op2

Logical OR NOT

N, Z, C

ORR, ORRS

{Rd,} Rn, Op2

Logical OR

N, Z, C

POP

reglist

Pop registers from stack

–

PUSH

reglist

Push registers onto stack

–

RBIT

Rd, Rn

Reverse bits

–

REV

Rd, Rn

Reverse byte order in a word

–

REV16

Rd, Rn

Reverse byte order in each halfword

–

REVSH

Rd, Rn

Reverse byte order in bottom halfword
and sign extend

–

ROR, RORS

Rd, Rm,

Rotate right

N, Z, C

RRX, RRXS

Rd, Rm

Rotate right with extend

N, Z, C

RSB, RSBS

{Rd,} Rn, Op2

Reverse subtract

N, Z, C, V

SBC, SBCS

{Rd,} Rn, Op2

Subtract with carry

N, Z, C, V

SBFX

Rd, Rn, #lsb, #width

Signed bit field extract

–

SDIV

{Rd,} Rn, Rm

Signed divide

–

SEV

–

Send event

–

SMLAL

RdLo, RdHi, Rn, Rm

Signed multiply with accumulate (32 ×
32 + 64), 64-bit result

–

SMULL

RdLo, RdHi, Rn, Rm

Signed multiply (32 × 32), 64-bit result

–

SSAT

Rd, #n, Rm {,shift #s}

Signed saturate

STM

Rn{!}, reglist

Store multiple registers, increment after

–

STMDB, STMEA

Rn{!}, reglist

Store multiple registers, decrement
before

–

STMFD, STMIA

Rn{!}, reglist

Store multiple registers, increment after

–

STR

Rt, [Rn {, #offset}]

Store register word

–

STRB, STRBT

Rt, [Rn {, #offset}]

Store register byte

–

STRD

Rt, Rt2, [Rn {, #offset}]

Store register two words

–

STREX

Rt, Rt, [Rn {, #offset}]

Store register exclusive

–

STREXB

Rd, Rt, [Rn]

Store register exclusive byte

–

STREXH

Rd, Rt, [Rn]

Store register exclusive halfword

–

STRH, STRHT

Rt, [Rn {, #offset}]

Store register halfword

–

STRSB, STRSBT

Rt, [Rn {, #offset}]

Store register signed byte

–

STRSH, STRSHT

Rt, [Rn {, #offset}]

Store register signed halfword

–

STRT

Rt, [Rn {, #offset}]

Store register word

–

SUB, SUBS

{Rd,} Rn, Op2

Subtract

N, Z, C, V

SUB, SUBW

{Rd,} Rn, #imm12

Subtract 12-bit constant

N, Z, C, V

SVC

#imm

Supervisor call

–

SXTB

{Rd,} Rm {,ROR #n}

Sign extend a byte

–

SXTH

{Rd,} Rm {,ROR #n}

Sign extend a halfword

–

TBB

[Rn, Rm]

Table branch byte

–

TBH

[Rn, Rm, LSL #1]

Table branch halfword

–

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Instruction Set Summary

www.ti.com

Table 2-25. Cortex-M3 Instruction Summary (continued)
Mnemonic

Operands

Brief Description

Flags

TEQ

Rn, Op2

Test equivalence

N, Z, C

TST

Rn, Op2

Test

N, Z, C

UBFX

Rd, Rn, #lsb, #width

Unsigned bit field extract

–

UDIV

{Rd,} Rn, Rm

Unsigned divide

–

UMLAL

RdLo, RdHi, Rn, Rm

Unsigned multiply with accumulate (32 ×
–
32 + 32 + 32), 64-bit result

UMULL

RdLo, RdHi, Rn, Rm

Unsigned multiply (32 × 2), 64-bit result

–

USAT

Rd, #n, Rm {,shift #s}

Unsigned saturate

UXTB

{Rd,} Rm, {,ROR #n}

Zero extend a byte

–

UXTH

{Rd,} Rm, {,ROR #n}

Zero extend a halfword

–

USAT

Rd, #n, Rm {,shift #s}

Unsigned saturate

UXTB

{Rd,} Rm {,ROR #n}

Zero extend a byte

–

UXTH

{Rd,} Rm {,ROR #n}

Zero extend a halfword

–

WFE

–

Wait for event

–

WFI

–

Wait for interrupt

–

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7

Cortex-M3 Processor Registers

2.7.1 CPU_DWT Registers
Table 2-26 lists the memory-mapped registers for the CPU_DWT. All register offset addresses not listed in
Table 2-26 should be considered as reserved locations and the register contents should not be modified.
Table 2-26. CPU_DWT Registers
Offset

Acronym

CTRL

Control

Section 2.7.1.1

Section

CYCCNT

Current PC Sampler Cycle Count

Section 2.7.1.2

CPICNT

CPI Count

Section 2.7.1.3

EXCCNT

Exception Overhead Count

Section 2.7.1.4

10h

SLEEPCNT

Sleep Count

Section 2.7.1.5

14h

LSUCNT

LSU Count

Section 2.7.1.6

18h

FOLDCNT

Fold Count

Section 2.7.1.7

1Ch

PCSR

Program Counter Sample

Section 2.7.1.8

20h

COMP0

Comparator 0

Section 2.7.1.9

24h

MASK0

Mask 0

Section 2.7.1.10

28h

FUNCTION0

Function 0

Section 2.7.1.11

30h

COMP1

Comparator 1

Section 2.7.1.12

34h

MASK1

Mask 1

Section 2.7.1.13

38h

FUNCTION1

Function 1

Section 2.7.1.14

40h

COMP2

Comparator 2

Section 2.7.1.15

44h

MASK2

Mask 2

Section 2.7.1.16

48h

FUNCTION2

Function 2

Section 2.7.1.17

50h

COMP3

Comparator 3

Section 2.7.1.18

54h

MASK3

Mask 3

Section 2.7.1.19

58h

FUNCTION3

Function 3

Section 2.7.1.20

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.1.1

www.ti.com

CTRL Register (Offset = 0h) [reset = 40000000h]

CTRL is shown in Figure 2-4 and described in Table 2-27.
Return to Summary Table.
Control
Use the DWT Control Register to enable the DWT unit.
Figure 2-4. CTRL Register
31

25
NOCYCCNT
R/W-0h

24
NOPRFCNT
R/W-0h

19
SLEEPEVTEN
A
R/W-0h

18
EXCEVTENA

17
CPIEVTENA

16
EXCTRCENA

R/W-0h

9
CYCTAP

8
POSTCNT

R/W-0h

0
CYCCNTENA
R/W-0h

RESERVED
R/W-10h
23
RESERVED

22
CYCEVTENA

21
FOLDEVTENA

20
LSUEVTENA

R/W-0h

14
RESERVED

12
PCSAMPLEEN
A
R/W-0h

R/W-0h
7

6
POSTCNT
R/W-0h

SYNCTAP
R/W-0h
2
POSTPRESET
R/W-0h

Table 2-27. CTRL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-26

RESERVED

R/W

10h

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

NOCYCCNT

R/W

When set, CYCCNT is not supported.

NOPRFCNT

R/W

When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and
CPICNT are not supported.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CYCEVTENA

R/W

Enables Cycle count event. Emits an event when the POSTCNT
counter triggers it. See CYCTAP and POSTPRESET for details. This
event is only emitted if PCSAMPLEENA is disabled.
PCSAMPLEENA overrides the setting of this bit.
0: Cycle count events disabled
1: Cycle count events enabled

FOLDEVTENA

R/W

Enables Folded instruction count event. Emits an event when
FOLDCNT overflows (every 256 cycles of folded instructions). A
folded instruction is one that does not incur even one cycle to
execute. For example, an IT instruction is folded away and so does
not use up one cycle.
0: Folded instruction count events disabled.
1: Folded instruction count events enabled.

LSUEVTENA

R/W

Enables LSU count event. Emits an event when LSUCNT overflows
(every 256 cycles of LSU operation). LSU counts include all LSU
costs after the initial cycle for the instruction.
0: LSU count events disabled.
1: LSU count events enabled.

SLEEPEVTENA

R/W

Enables Sleep count event. Emits an event when SLEEPCNT
overflows (every 256 cycles that the processor is sleeping).
0: Sleep count events disabled.
1: Sleep count events enabled.

EXCEVTENA

R/W

Enables Interrupt overhead event. Emits an event when EXCCNT
overflows (every 256 cycles of interrupt overhead).
0x0: Interrupt overhead event disabled.
0x1: Interrupt overhead event enabled.
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-27. CTRL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

CPIEVTENA

R/W

Enables CPI count event. Emits an event when CPICNT overflows
(every 256 cycles of multi-cycle instructions).
0: CPI counter events disabled.
1: CPI counter events enabled.

EXCTRCENA

R/W

Enables Interrupt event tracing.
0: Interrupt event trace disabled.
1: Interrupt event trace enabled.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

PCSAMPLEENA

R/W

Enables PC Sampling event. A PC sample event is emitted when the
POSTCNT counter triggers it. See CYCTAP and POSTPRESET for
details. Enabling this bit overrides CYCEVTENA.
0: PC Sampling event disabled.
1: Sampling event enabled.

SYNCTAP

R/W

Selects a synchronization packet rate. CYCCNTENA and
CPU_ITM:TCR.SYNCENA must also be enabled for this feature.
Synchronization packets (if enabled) are generated on tap transitions
(0 to1 or 1 to 0).
0h = Disabled. No synchronization packets
1h = Tap at bit 24 of CYCCNT
2h = Tap at bit 26 of CYCCNT
3h = Tap at bit 28 of CYCCNT

CYCTAP

R/W

Selects a tap on CYCCNT. These are spaced at bits [6] and [10].
When the selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it
emits into the POSTCNT, post-scalar counter. That counter then
counts down. On a bit change when post-scalar is 0, it triggers an
event for PC sampling or cycle count event (see details in
CYCEVTENA).
0h = Selects bit [6] to tap
1h = Selects bit [10] to tap

8-5

POSTCNT

R/W

Post-scalar counter for CYCTAP. When the selected tapped bit
changes from 0 to 1 or 1 to 0, the post scalar counter is downcounted when not 0. If 0, it triggers an event for PCSAMPLEENA or
CYCEVTENA use. It also reloads with the value from
POSTPRESET.

4-1

POSTPRESET

R/W

Reload value for post-scalar counter POSTCNT. When 0, events are
triggered on each tap change (a power of 2). If this field has a non-0
value, it forms a count-down value, to be reloaded into POSTCNT
each time it reaches 0. For example, a value 1 in this register means
an event is formed every other tap change.

CYCCNTENA

R/W

Enable CYCCNT, allowing it to increment and generate
synchronization and count events. If NOCYCCNT = 1, this bit reads
zero and ignore writes.

15-13
12

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.1.2

www.ti.com

CYCCNT Register (Offset = 4h) [reset = 0h]

CYCCNT is shown in Figure 2-5 and described in Table 2-28.
Return to Summary Table.
Current PC Sampler Cycle Count
This register is used to count the number of core cycles. This counter can measure elapsed execution
time. This is a free-running counter (this counter will not advance in power modes where free-running
clock to CPU stops). The counter has three functions:
1: When CTRL.PCSAMPLEENA = 1, the PC is sampled and emitted when the selected tapped bit
changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0.
2: When CTRL.CYCEVTENA = 1 , (and CTRL.PCSAMPLEENA = 0), an event is emitted when the
selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0.
3: Applications and debuggers can use the counter to measure elapsed execution time. By subtracting a
start and an end time, an application can measure time between in-core clocks (other than when Halted in
debug). This is valid to 232 core clock cycles (for example, almost 89.5 seconds at 48MHz).
Figure 2-5. CYCCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CYCCNT
R/W-0h

Table 2-28. CYCCNT Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

CYCCNT

R/W

Current PC Sampler Cycle Counter count value. When enabled, this
counter counts the number of core cycles, except when the core is
halted. The cycle counter is a free running counter, counting
upwards (this counter will not advance in power modes where freerunning clock to CPU stops). It wraps around to 0 on overflow. The
debugger must initialize this to 0 when first enabling.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.3

CPICNT Register (Offset = 8h) [reset = X]

CPICNT is shown in Figure 2-6 and described in Table 2-29.
Return to Summary Table.
CPI Count
This register is used to count the total number of instruction cycles beyond the first cycle.
Figure 2-6. CPICNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

4 3 2
CPICNT
R/W-X

Table 2-29. CPICNT Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

CPICNT

R/W

Current CPI counter value. Increments on the additional cycles (the
first cycle is not counted) required to execute all instructions except
those recorded by LSUCNT. This counter also increments on all
instruction fetch stalls. If CTRL.CPIEVTENA is set, an event is
emitted when the counter overflows. This counter initializes to 0
when it is enabled using CTRL.CPIEVTENA.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.1.4

www.ti.com

EXCCNT Register (Offset = Ch) [reset = X]

EXCCNT is shown in Figure 2-7 and described in Table 2-30.
Return to Summary Table.
Exception Overhead Count
This register is used to count the total cycles spent in interrupt processing.
Figure 2-7. EXCCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

4 3 2
EXCCNT
R/W-X

Table 2-30. EXCCNT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-8

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

EXCCNT

R/W

Current interrupt overhead counter value. Counts the total cycles
spent in interrupt processing (for example entry stacking, return
unstacking, pre-emption). An event is emitted on counter overflow
(every 256 cycles). This counter initializes to 0 when it is enabled
using CTRL.EXCEVTENA.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.5

SLEEPCNT Register (Offset = 10h) [reset = X]

SLEEPCNT is shown in Figure 2-8 and described in Table 2-31.
Return to Summary Table.
Sleep Count
This register is used to count the total number of cycles during which the processor is sleeping.
Figure 2-8. SLEEPCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

4 3 2
SLEEPCNT
R/W-X

Table 2-31. SLEEPCNT Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

SLEEPCNT

R/W

Sleep counter. Counts the number of cycles during which the
processor is sleeping. An event is emitted on counter overflow (every
256 cycles). This counter initializes to 0 when it is enabled using
CTRL.SLEEPEVTENA. Note that the sleep counter is clocked using
CPU's free-running clock. In some power modes the free-running
clock to CPU is gated to minimize power consumption. This means
that the sleep counter will be invalid in these power modes.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.1.6

www.ti.com

LSUCNT Register (Offset = 14h) [reset = X]

LSUCNT is shown in Figure 2-9 and described in Table 2-32.
Return to Summary Table.
LSU Count
This register is used to count the total number of cycles during which the processor is processing an LSU
operation beyond the first cycle.
Figure 2-9. LSUCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

4 3 2
LSUCNT
R/W-X

Table 2-32. LSUCNT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-8

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

LSUCNT

R/W

LSU counter. This counts the total number of cycles that the
processor is processing an LSU operation. The initial execution cost
of the instruction is not counted. For example, an LDR that takes two
cycles to complete increments this counter one cycle. Equivalently,
an LDR that stalls for two cycles (i.e. takes four cycles to execute),
increments this counter three times. An event is emitted on counter
overflow (every 256 cycles). This counter initializes to 0 when it is
enabled using CTRL.LSUEVTENA.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.7

FOLDCNT Register (Offset = 18h) [reset = X]

FOLDCNT is shown in Figure 2-10 and described in Table 2-33.
Return to Summary Table.
Fold Count
This register is used to count the total number of folded instructions. The counter increments on each
instruction which takes 0 cycles.
Figure 2-10. FOLDCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

4 3 2
FOLDCNT
R/W-X

Table 2-33. FOLDCNT Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

FOLDCNT

R/W

This counts the total number folded instructions. This counter
initializes to 0 when it is enabled using CTRL.FOLDEVTENA.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.1.8

www.ti.com

PCSR Register (Offset = 1Ch) [reset = X]

PCSR is shown in Figure 2-11 and described in Table 2-34.
Return to Summary Table.
Program Counter Sample
This register is used to enable coarse-grained software profiling using a debug agent, without changing
the currently executing code. If the core is not in debug state, the value returned is the instruction address
of a recently executed instruction. If the core is in debug state, the value returned is 0xFFFFFFFF.
Figure 2-11. PCSR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
EIASAMPLE
R-X

Table 2-34. PCSR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

EIASAMPLE

Execution instruction address sample, or 0xFFFFFFFF if the core is
halted.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.9

COMP0 Register (Offset = 20h) [reset = X]

COMP0 is shown in Figure 2-12 and described in Table 2-35.
Return to Summary Table.
Comparator 0
This register is used to write the reference value for comparator 0.
Figure 2-12. COMP0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COMP
R/W-X

Table 2-35. COMP0 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

COMP

R/W

Reference value to compare against PC or the data address as
given by FUNCTION0. Comparator 0 can also compare against the
value of the PC Sampler Counter (CYCCNT).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.10 MASK0 Register (Offset = 24h) [reset = X]
MASK0 is shown in Figure 2-13 and described in Table 2-36.
Return to Summary Table.
Mask 0
Use the DWT Mask Registers 0 to apply a mask to data addresses when matching against COMP0.
Figure 2-13. MASK0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

2 1
MASK
R/W-X

Table 2-36. MASK0 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-4

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

MASK

R/W

Mask on data address when matching against COMP0. This is the
size of the ignore mask. That is, DWT matching is performed
as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) ==
COMP0. However, the actual comparison is slightly more complex to
enable matching an address wherever it appears on a bus. So, if
COMP0 is 3, this matches a word access of 0, because 3 would be
within the word.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.11 FUNCTION0 Register (Offset = 28h) [reset = 0h]
FUNCTION0 is shown in Figure 2-14 and described in Table 2-37.
Return to Summary Table.
Function 0
Use the DWT Function Registers 0 to control the operation of the comparator 0. This comparator can:
1. Match against either the PC or the data address. This is controlled by CYCMATCH. This function is
only available for comparator 0 (COMP0).
2. Emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined
by FUNCTION.
Figure 2-14. FUNCTION0 Register
31

28
RESERVED
R-0h

24
MATCHED
R/W-0h

RESERVED
R-0h
15

12
RESERVED
R-0h

7
CYCMATCH
R/W-0h

6
RESERVED
R-0h

5
EMITRANGE
R/W-0h

4
RESERVED
R-0h

FUNCTION
R/W-0h

Table 2-37. FUNCTION0 Register Field Descriptions
Field

Type

Reset

Description

31-25

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MATCHED

R/W

This bit is set when the comparator matches, and indicates that the
operation defined by FUNCTION has occurred since this bit was last
read. This bit is cleared on read.

23-8

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CYCMATCH

R/W

This bit is only available in comparator 0. When set, COMP0 will
compare against the cycle counter (CYCCNT).

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EMITRANGE

R/W

Emit range field. This bit permits emitting offset when range match
occurs. PC sampling is not supported when emit range is enabled.
This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-37. FUNCTION0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-0

FUNCTION

R/W

Function settings.
0x0: Disabled
0x1: EMITRANGE = 0, sample and emit PC through ITM.
EMITRANGE = 1, emit address offset through ITM
0x2: EMITRANGE = 0, emit data through ITM on read and write.
EMITRANGE = 1, emit data and address offset through ITM on read
or write.
0x3: EMITRANGE = 0, sample PC and data value through ITM on
read or write. EMITRANGE = 1, emit address offset and data value
through ITM on read or write.
0x4: Watchpoint on PC match.
0x5: Watchpoint on read.
0x6: Watchpoint on write.
0x7: Watchpoint on read or write.
0x8: ETM trigger on PC match
0x9: ETM trigger on read
0xA: ETM trigger on write
0xB: ETM trigger on read or write
0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE
= 1, sample Daddr (lower 16 bits) for read transfers
0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE
= 1, sample Daddr (lower 16 bits) for write transfers
0xE: EMITRANGE = 0, sample PC + data for read transfers.
EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read
transfers
0xF: EMITRANGE = 0, sample PC + data for write transfers.
EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write
transfers
Note 1: If the ETM is not fitted, then ETM trigger is not possible.
Note 2: Data value is only sampled for accesses that do not fault
(MPU or bus fault). The PC is sampled irrespective of any faults. The
PC is only sampled for the first address of a burst.
Note 3: PC match is not recommended for watchpoints because it
stops after the instruction. It mainly guards and triggers the ETM.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.12 COMP1 Register (Offset = 30h) [reset = X]
COMP1 is shown in Figure 2-15 and described in Table 2-38.
Return to Summary Table.
Comparator 1
This register is used to write the reference value for comparator 1.
Figure 2-15. COMP1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COMP
R/W-X

Table 2-38. COMP1 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

COMP

R/W

Reference value to compare against PC or the data address as
given by FUNCTION1.
Comparator 1 can also compare data values. So this register can
contain reference values for data matching.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.13 MASK1 Register (Offset = 34h) [reset = X]
MASK1 is shown in Figure 2-16 and described in Table 2-39.
Return to Summary Table.
Mask 1
Use the DWT Mask Registers 1 to apply a mask to data addresses when matching against COMP1.
Figure 2-16. MASK1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

2 1
MASK
R/W-X

Table 2-39. MASK1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-4

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

MASK

R/W

Mask on data address when matching against COMP1. This is the
size of the ignore mask. That is, DWT matching is performed
as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) ==
COMP1. However, the actual comparison is slightly more complex to
enable matching an address wherever it appears on a bus. So, if
COMP1 is 3, this matches a word access of 0, because 3 would be
within the word.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.14 FUNCTION1 Register (Offset = 38h) [reset = 200h]
FUNCTION1 is shown in Figure 2-17 and described in Table 2-40.
Return to Summary Table.
Function 1
Use the DWT Function Registers 1 to control the operation of the comparator 1. This comparator can:
1. Perform data value comparisons if associated address comparators have performed an address match.
This function is only available for comparator 1 (COMP1).
2. Emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined
by FUNCTION.
Figure 2-17. FUNCTION1 Register
31

28
RESERVED
R-0h

RESERVED
R-0h
15

6
RESERVED
R-0h

24
MATCHED
R/W-0h

9
LNK1ENA
R-1h

8
DATAVMATCH
R/W-0h

DATAVADDR1
R/W-0h
12

DATAVADDR0
R/W-0h
7

10
DATAVSIZE
R/W-0h

5
EMITRANGE
R/W-0h

4
RESERVED
R-0h

2
FUNCTION
R/W-0h

Table 2-40. FUNCTION1 Register Field Descriptions
Field

Type

Reset

Description

31-25

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MATCHED

R/W

This bit is set when the comparator matches, and indicates that the
operation defined by FUNCTION has occurred since this bit was last
read. This bit is cleared on read.

23-20

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

19-16

DATAVADDR1

R/W

Identity of a second linked address comparator for data value
matching when DATAVMATCH == 1 and LNK1ENA == 1.

15-12

DATAVADDR0

R/W

Identity of a linked address comparator for data value matching
when DATAVMATCH == 1.

11-10

DATAVSIZE

R/W

Defines the size of the data in the COMP1 register that is to be
matched:
0x0: Byte
0x1: Halfword
0x2: Word
0x3: Unpredictable.

LNK1ENA

Read only bit-field only supported in comparator 1.
0: DATAVADDR1 not supported
1: DATAVADDR1 supported (enabled)

DATAVMATCH

R/W

Data match feature:
0: Perform address comparison
1: Perform data value compare. The comparators given by
DATAVADDR0 and DATAVADDR1 provide the address for the data
comparison. The FUNCTION setting for the comparators given by
DATAVADDR0 and DATAVADDR1 are overridden and those
comparators only provide the address match for the data
comparison.
This bit is only available in comparator 1.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-40. FUNCTION1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EMITRANGE

R/W

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

FUNCTION

R/W

Function settings:
0x0: Disabled
0x1: EMITRANGE = 0, sample and emit PC through ITM.
EMITRANGE = 1, emit address offset through ITM
0x2: EMITRANGE = 0, emit data through ITM on read and write.
EMITRANGE = 1, emit data and address offset through ITM on read
or write.
0x3: EMITRANGE = 0, sample PC and data value through ITM on
read or write. EMITRANGE = 1, emit address offset and data value
through ITM on read or write.
0x4: Watchpoint on PC match.
0x5: Watchpoint on read.
0x6: Watchpoint on write.
0x7: Watchpoint on read or write.
0x8: ETM trigger on PC match
0x9: ETM trigger on read
0xA: ETM trigger on write
0xB: ETM trigger on read or write
0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE
= 1, sample Daddr (lower 16 bits) for read transfers
0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE
= 1, sample Daddr (lower 16 bits) for write transfers
0xE: EMITRANGE = 0, sample PC + data for read transfers.
EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read
transfers
0xF: EMITRANGE = 0, sample PC + data for write transfers.
EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write
transfers
Note 1: If the ETM is not fitted, then ETM trigger is not possible.
Note 2: Data value is only sampled for accesses that do not fault
(MPU or bus fault). The PC is sampled irrespective of any faults. The
PC is only sampled for the first address of a burst.
Note 3: FUNCTION is overridden for comparators given by
DATAVADDR0 and DATAVADDR1 if DATAVMATCH is also set.
The comparators given by DATAVADDR0 and DATAVADDR1 can
then only perform address comparator matches for comparator 1
data matches.
Note 4: If the data matching functionality is not included during
implementation it is not possible to set DATAVADDR0,
DATAVADDR1, or DATAVMATCH. This means that the data
matching functionality is not available in the implementation. Test the
availability of data matching by writing and reading DATAVMATCH.
If it is not settable then data matching is unavailable.
Note 5: PC match is not recommended for watchpoints because it
stops after the instruction. It mainly guards and triggers the ETM.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.15 COMP2 Register (Offset = 40h) [reset = X]
COMP2 is shown in Figure 2-18 and described in Table 2-41.
Return to Summary Table.
Comparator 2
This register is used to write the reference value for comparator 2.
Figure 2-18. COMP2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COMP
R/W-X

Table 2-41. COMP2 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

COMP

R/W

Reference value to compare against PC or the data address as
given by FUNCTION2.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.16 MASK2 Register (Offset = 44h) [reset = X]
MASK2 is shown in Figure 2-19 and described in Table 2-42.
Return to Summary Table.
Mask 2
Use the DWT Mask Registers 2 to apply a mask to data addresses when matching against COMP2.
Figure 2-19. MASK2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

2 1
MASK
R/W-X

Table 2-42. MASK2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-4

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

MASK

R/W

Mask on data address when matching against COMP2. This is the
size of the ignore mask. That is, DWT matching is performed
as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) ==
COMP2. However, the actual comparison is slightly more complex to
enable matching an address wherever it appears on a bus. So, if
COMP2 is 3, this matches a word access of 0, because 3 would be
within the word.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.17 FUNCTION2 Register (Offset = 48h) [reset = 0h]
FUNCTION2 is shown in Figure 2-20 and described in Table 2-43.
Return to Summary Table.
Function 2
Use the DWT Function Registers 2 to control the operation of the comparator 2. This comparator can emit
data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by
FUNCTION.
Figure 2-20. FUNCTION2 Register
31

28
RESERVED
R/W-0h

24
MATCHED
R/W-0h

RESERVED
R-0h
15

12
RESERVED
R-0h

6
RESERVED
R-0h

5
EMITRANGE
R/W-0h

4
RESERVED
R-0h

FUNCTION
R/W-0h

Table 2-43. FUNCTION2 Register Field Descriptions
Field

Type

Reset

Description

31-25

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MATCHED

R/W

This bit is set when the comparator matches, and indicates that the
operation defined by FUNCTION has occurred since this bit was last
read. This bit is cleared on read.

23-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EMITRANGE

R/W

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-43. FUNCTION2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-0

FUNCTION

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.18 COMP3 Register (Offset = 50h) [reset = X]
COMP3 is shown in Figure 2-21 and described in Table 2-44.
Return to Summary Table.
Comparator 3
This register is used to write the reference value for comparator 3.
Figure 2-21. COMP3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COMP
R/W-X

Table 2-44. COMP3 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

COMP

R/W

Reference value to compare against PC or the data address as
given by FUNCTION3.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.19 MASK3 Register (Offset = 54h) [reset = X]
MASK3 is shown in Figure 2-22 and described in Table 2-45.
Return to Summary Table.
Mask 3
Use the DWT Mask Registers 3 to apply a mask to data addresses when matching against COMP3.
Figure 2-22. MASK3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

2 1
MASK
R/W-X

Table 2-45. MASK3 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-4

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

MASK

R/W

Mask on data address when matching against COMP3. This is the
size of the ignore mask. That is, DWT matching is performed
as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) ==
COMP3. However, the actual comparison is slightly more complex to
enable matching an address wherever it appears on a bus. So, if
COMP3 is 3, this matches a word access of 0, because 3 would be
within the word.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.1.20 FUNCTION3 Register (Offset = 58h) [reset = 0h]
FUNCTION3 is shown in Figure 2-23 and described in Table 2-46.
Return to Summary Table.
Function 3
Use the DWT Function Registers 3 to control the operation of the comparator 3. This comparator can emit
data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by
FUNCTION.
Figure 2-23. FUNCTION3 Register
31

28
RESERVED
R/W-0h

24
MATCHED
R/W-0h

RESERVED
R/W-0h
15

12
RESERVED
R/W-0h

6
RESERVED
R/W-0h

5
EMITRANGE
R/W-0h

4
RESERVED
R/W-0h

FUNCTION
R/W-0h

Table 2-46. FUNCTION3 Register Field Descriptions
Field

Type

Reset

Description

31-25

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MATCHED

R/W

This bit is set when the comparator matches, and indicates that the
operation defined by FUNCTION has occurred since this bit was last
read. This bit is cleared on read.

23-6

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EMITRANGE

R/W

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-46. FUNCTION3 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-0

FUNCTION

R/W

2.7.2 CPU_FPB Registers
Table 2-47 lists the memory-mapped registers for the CPU_FPB. All register offset addresses not listed in
Table 2-47 should be considered as reserved locations and the register contents should not be modified.
Table 2-47. CPU_FPB Registers
Offset

Acronym

CTRL

Control

Section 2.7.2.1

Section

REMAP

Remap

Section 2.7.2.2

COMP0

Comparator 0

Section 2.7.2.3

COMP1

Comparator 1

Section 2.7.2.4

10h

COMP2

Comparator 2

Section 2.7.2.5

14h

COMP3

Comparator 3

Section 2.7.2.6

18h

COMP4

Comparator 4

Section 2.7.2.7

1Ch

COMP5

Comparator 5

Section 2.7.2.8

20h

COMP6

Comparator 6

Section 2.7.2.9

24h

COMP7

Comparator 7

Section 2.7.2.10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.2.1

CTRL Register (Offset = 0h) [reset = 260h]

CTRL is shown in Figure 2-24 and described in Table 2-48.
Return to Summary Table.
Control
This register is used to enable the flash patch block.
Figure 2-24. CTRL Register
31

1
KEY
W-0h

0
ENABLE
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

RESERVED
R-0h
7

12
NUM_CODE2
R-0h

NUM_LIT
R-2h
4

NUM_CODE1
R-6h

2
RESERVED
R-0h

Table 2-48. CTRL Register Field Descriptions
Field

Type

Reset

Description

31-14

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

13-12

NUM_CODE2

Number of full banks of code comparators, sixteen comparators per
bank. Where less than sixteen code comparators are provided, the
bank count is zero, and the number present indicated by
NUM_CODE1. This read only field contains 3'b000 to indicate 0
banks for Cortex-M processor.

11-8

NUM_LIT

Number of literal slots field.
0x0: No literal slots
0x2: Two literal slots

7-4

NUM_CODE1

Number of code slots field.
0x0: No code slots
0x2: Two code slots
0x6: Six code slots

3-2

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

KEY

Key field. In order to write to this register, this bit-field must be
written to '1'. This bit always reads 0.

ENABLE

R/W

Flash patch unit enable bit
0x0: Flash patch unit disabled
0x1: Flash patch unit enabled

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.2.2

www.ti.com

REMAP Register (Offset = 4h) [reset = X]

REMAP is shown in Figure 2-25 and described in Table 2-49.
Return to Summary Table.
Remap
This register provides the remap base address location where a matched addresses are remapped. The
three most significant bits and the five least significant bits of the remap base address are hard-coded to
3'b001 and 5'b00000 respectively. The remap base address must be in system space and is it required to
be 8-word aligned, with one word allocated to each of the eight FPB comparators.
Figure 2-25. REMAP Register
31

30
29
RESERVED
R-1h

22
REMAP
R/W-X

10
REMAP
R/W-X

2
1
RESERVED
R-0h

Table 2-49. REMAP Register Field Descriptions
Bit

Field

Type

Reset

Description

31-29

RESERVED

This field always reads 3'b001. Writing to this field is ignored.

28-5

REMAP

R/W

Remap base address field.

4-0

RESERVED

This field always reads 0. Writing to this field is ignored.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.2.3

COMP0 Register (Offset = 8h) [reset = 0h]

COMP0 is shown in Figure 2-26 and described in Table 2-50.
Return to Summary Table.
Comparator 0
Figure 2-26. COMP0 Register
31

29
RESERVED
R/W-0h

REPLACE
R/W-0h
23

26
COMP
R/W-0h

1
RESERVED
R/W-0h

0
ENABLE
R/W-0h

COMP
R/W-0h
15

12
COMP
R/W-0h

4
COMP
R/W-0h

Table 2-50. COMP0 Register Field Descriptions
Bit

Field

Type

Reset

Description

REPLACE

R/W

This selects what happens when the COMP address is matched.
Address remapping only takes place for the 0x0 setting.
0x0: Remap to remap address. See REMAP.REMAP
0x1: Set BKPT on lower halfword, upper is unaffected
0x2: Set BKPT on upper halfword, lower is unaffected
0x3: Set BKPT on both lower and upper halfwords.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

COMP

R/W

Comparison address.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ENABLE

R/W

Compare and remap enable comparator 0. CTRL.ENABLE must also
be set to enable comparisons.
0x0: Compare and remap for comparator 0 disabled
0x1: Compare and remap for comparator 0 enabled

31-30

29
28-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.2.4

www.ti.com

COMP1 Register (Offset = Ch) [reset = 0h]

COMP1 is shown in Figure 2-27 and described in Table 2-51.
Return to Summary Table.
Comparator 1
Figure 2-27. COMP1 Register
31

29
RESERVED
R/W-0h

REPLACE
R/W-0h
23

26
COMP
R/W-0h

1
RESERVED
R/W-0h

0
ENABLE
R/W-0h

COMP
R/W-0h
15

12
COMP
R/W-0h

4
COMP
R/W-0h

Table 2-51. COMP1 Register Field Descriptions
Bit

Field

Type

Reset

Description

REPLACE

R/W

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

COMP

R/W

Comparison address.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ENABLE

R/W

Compare and remap enable comparator 1. CTRL.ENABLE must also
be set to enable comparisons.
0x0: Compare and remap for comparator 1 disabled
0x1: Compare and remap for comparator 1 enabled

31-30

29
28-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.2.5

COMP2 Register (Offset = 10h) [reset = 0h]

COMP2 is shown in Figure 2-28 and described in Table 2-52.
Return to Summary Table.
Comparator 2
Figure 2-28. COMP2 Register
31

29
RESERVED
R/W-0h

REPLACE
R/W-0h
23

26
COMP
R/W-0h

1
RESERVED
R/W-0h

0
ENABLE
R/W-0h

COMP
R/W-0h
15

12
COMP
R/W-0h

4
COMP
R/W-0h

Table 2-52. COMP2 Register Field Descriptions
Bit

Field

Type

Reset

Description

REPLACE

R/W

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

COMP

R/W

Comparison address.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ENABLE

R/W

Compare and remap enable comparator 2. CTRL.ENABLE must also
be set to enable comparisons.
0x0: Compare and remap for comparator 2 disabled
0x1: Compare and remap for comparator 2 enabled

31-30

29
28-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.2.6

www.ti.com

COMP3 Register (Offset = 14h) [reset = 0h]

COMP3 is shown in Figure 2-29 and described in Table 2-53.
Return to Summary Table.
Comparator 3
Figure 2-29. COMP3 Register
31

29
RESERVED
R/W-0h

REPLACE
R/W-0h
23

26
COMP
R/W-0h

1
RESERVED
R/W-0h

0
ENABLE
R/W-0h

COMP
R/W-0h
15

12
COMP
R/W-0h

4
COMP
R/W-0h

Table 2-53. COMP3 Register Field Descriptions
Bit

Field

Type

Reset

Description

REPLACE

R/W

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

COMP

R/W

Comparison address.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ENABLE

R/W

Compare and remap enable comparator 3. CTRL.ENABLE must also
be set to enable comparisons.
0x0: Compare and remap for comparator 3 disabled
0x1: Compare and remap for comparator 3 enabled

31-30

29
28-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.2.7

COMP4 Register (Offset = 18h) [reset = 0h]

COMP4 is shown in Figure 2-30 and described in Table 2-54.
Return to Summary Table.
Comparator 4
Figure 2-30. COMP4 Register
31

29
RESERVED
R/W-0h

REPLACE
R/W-0h
23

26
COMP
R/W-0h

1
RESERVED
R/W-0h

0
ENABLE
R/W-0h

COMP
R/W-0h
15

12
COMP
R/W-0h

4
COMP
R/W-0h

Table 2-54. COMP4 Register Field Descriptions
Bit

Field

Type

Reset

Description

REPLACE

R/W

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

COMP

R/W

Comparison address.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ENABLE

R/W

Compare and remap enable comparator 4. CTRL.ENABLE must also
be set to enable comparisons.
0x0: Compare and remap for comparator 4 disabled
0x1: Compare and remap for comparator 4 enabled

31-30

29
28-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.2.8

www.ti.com

COMP5 Register (Offset = 1Ch) [reset = 0h]

COMP5 is shown in Figure 2-31 and described in Table 2-55.
Return to Summary Table.
Comparator 5
Figure 2-31. COMP5 Register
31

29
RESERVED
R/W-0h

REPLACE
R/W-0h
23

26
COMP
R/W-0h

1
RESERVED
R/W-0h

0
ENABLE
R/W-0h

COMP
R/W-0h
15

12
COMP
R/W-0h

4
COMP
R/W-0h

Table 2-55. COMP5 Register Field Descriptions
Bit

Field

Type

Reset

Description

REPLACE

R/W

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

COMP

R/W

Comparison address.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ENABLE

R/W

Compare and remap enable comparator 5. CTRL.ENABLE must also
be set to enable comparisons.
0x0: Compare and remap for comparator 5 disabled
0x1: Compare and remap for comparator 5 enabled

31-30

29
28-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.2.9

COMP6 Register (Offset = 20h) [reset = 0h]

COMP6 is shown in Figure 2-32 and described in Table 2-56.
Return to Summary Table.
Comparator 6
Figure 2-32. COMP6 Register
31

29
RESERVED
R/W-0h

REPLACE
R/W-0h
23

26
COMP
R/W-0h

1
RESERVED
R/W-0h

0
ENABLE
R/W-0h

COMP
R/W-0h
15

12
COMP
R/W-0h

4
COMP
R/W-0h

Table 2-56. COMP6 Register Field Descriptions
Bit

Field

Type

Reset

Description

REPLACE

R/W

This selects what happens when the COMP address is matched.
Comparator 6 is a literal comparator and the only supported setting
is 0x0. Other settings will be ignored.
0x0: Remap to remap address. See REMAP.REMAP
0x1: Set BKPT on lower halfword, upper is unaffected
0x2: Set BKPT on upper halfword, lower is unaffected
0x3: Set BKPT on both lower and upper halfwords.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

COMP

R/W

Comparison address.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ENABLE

R/W

Compare and remap enable comparator 6. CTRL.ENABLE must also
be set to enable comparisons.
0x0: Compare and remap for comparator 6 disabled
0x1: Compare and remap for comparator 6 enabled

31-30

29
28-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.2.10 COMP7 Register (Offset = 24h) [reset = 0h]
COMP7 is shown in Figure 2-33 and described in Table 2-57.
Return to Summary Table.
Comparator 7
Figure 2-33. COMP7 Register
31

29
RESERVED
R/W-0h

REPLACE
R/W-0h
23

26
COMP
R/W-0h

1
RESERVED
R/W-0h

0
ENABLE
R/W-0h

COMP
R/W-0h
15

12
COMP
R/W-0h

4
COMP
R/W-0h

Table 2-57. COMP7 Register Field Descriptions
Bit

Field

Type

Reset

Description

REPLACE

R/W

This selects what happens when the COMP address is matched.
Comparator 7 is a literal comparator and the only supported setting
is 0x0. Other settings will be ignored.
0x0: Remap to remap address. See REMAP.REMAP
0x1: Set BKPT on lower halfword, upper is unaffected
0x2: Set BKPT on upper halfword, lower is unaffected
0x3: Set BKPT on both lower and upper halfwords.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

COMP

R/W

Comparison address.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ENABLE

R/W

Compare and remap enable comparator 7. CTRL.ENABLE must also
be set to enable comparisons.
0x0: Compare and remap for comparator 7 disabled
0x1: Compare and remap for comparator 7 enabled

31-30

29
28-2

2.7.3 CPU_ITM Registers
Table 2-58 lists the memory-mapped registers for the CPU_ITM. All register offset addresses not listed in
Table 2-58 should be considered as reserved locations and the register contents should not be modified.
Table 2-58. CPU_ITM Registers
Offset

Acronym

Section

STIM0

Stimulus Port 0

Section 2.7.3.1

STIM1

Stimulus Port 1

Section 2.7.3.2

STIM2

Stimulus Port 2

Section 2.7.3.3

STIM3

Stimulus Port 3

Section 2.7.3.4

10h

STIM4

Stimulus Port 4

Section 2.7.3.5

14h

STIM5

Stimulus Port 5

Section 2.7.3.6

18h

STIM6

Stimulus Port 6

Section 2.7.3.7

1Ch

STIM7

Stimulus Port 7

Section 2.7.3.8
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-58. CPU_ITM Registers (continued)
Offset

Acronym

Section

20h

STIM8

Stimulus Port 8

Section 2.7.3.9

24h

STIM9

Stimulus Port 9

Section 2.7.3.10

28h

STIM10

Stimulus Port 10

Section 2.7.3.11

2Ch

STIM11

Stimulus Port 11

Section 2.7.3.12

30h

STIM12

Stimulus Port 12

Section 2.7.3.13

34h

STIM13

Stimulus Port 13

Section 2.7.3.14

38h

STIM14

Stimulus Port 14

Section 2.7.3.15

3Ch

STIM15

Stimulus Port 15

Section 2.7.3.16

40h

STIM16

Stimulus Port 16

Section 2.7.3.17

44h

STIM17

Stimulus Port 17

Section 2.7.3.18

48h

STIM18

Stimulus Port 18

Section 2.7.3.19

4Ch

STIM19

Stimulus Port 19

Section 2.7.3.20

50h

STIM20

Stimulus Port 20

Section 2.7.3.21

54h

STIM21

Stimulus Port 21

Section 2.7.3.22

58h

STIM22

Stimulus Port 22

Section 2.7.3.23

5Ch

STIM23

Stimulus Port 23

Section 2.7.3.24

60h

STIM24

Stimulus Port 24

Section 2.7.3.25

64h

STIM25

Stimulus Port 25

Section 2.7.3.26

68h

STIM26

Stimulus Port 26

Section 2.7.3.27

6Ch

STIM27

Stimulus Port 27

Section 2.7.3.28

70h

STIM28

Stimulus Port 28

Section 2.7.3.29

74h

STIM29

Stimulus Port 29

Section 2.7.3.30

78h

STIM30

Stimulus Port 30

Section 2.7.3.31

7Ch

STIM31

Stimulus Port 31

Section 2.7.3.32

E00h

TER

Trace Enable

Section 2.7.3.33

E40h

TPR

Trace Privilege

Section 2.7.3.34

E80h

TCR

Trace Control

Section 2.7.3.35

FB0h

LAR

Lock Access

Section 2.7.3.36

FB4h

LSR

Lock Status

Section 2.7.3.37

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.3.1

www.ti.com

STIM0 Register (Offset = 0h) [reset = X]

STIM0 is shown in Figure 2-34 and described in Table 2-59.
Return to Summary Table.
Stimulus Port 0
Figure 2-34. STIM0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM0
R/W-X

Table 2-59. STIM0 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM0

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA0 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.2

STIM1 Register (Offset = 4h) [reset = X]

STIM1 is shown in Figure 2-35 and described in Table 2-60.
Return to Summary Table.
Stimulus Port 1
Figure 2-35. STIM1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM1
R/W-X

Table 2-60. STIM1 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM1

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA1 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.3.3

www.ti.com

STIM2 Register (Offset = 8h) [reset = X]

STIM2 is shown in Figure 2-36 and described in Table 2-61.
Return to Summary Table.
Stimulus Port 2
Figure 2-36. STIM2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM2
R/W-X

Table 2-61. STIM2 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM2

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA2 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.4

STIM3 Register (Offset = Ch) [reset = X]

STIM3 is shown in Figure 2-37 and described in Table 2-62.
Return to Summary Table.
Stimulus Port 3
Figure 2-37. STIM3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM3
R/W-X

Table 2-62. STIM3 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM3

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA3 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.3.5

www.ti.com

STIM4 Register (Offset = 10h) [reset = X]

STIM4 is shown in Figure 2-38 and described in Table 2-63.
Return to Summary Table.
Stimulus Port 4
Figure 2-38. STIM4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM4
R/W-X

Table 2-63. STIM4 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM4

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA4 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.6

STIM5 Register (Offset = 14h) [reset = X]

STIM5 is shown in Figure 2-39 and described in Table 2-64.
Return to Summary Table.
Stimulus Port 5
Figure 2-39. STIM5 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM5
R/W-X

Table 2-64. STIM5 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM5

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA5 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.3.7

www.ti.com

STIM6 Register (Offset = 18h) [reset = X]

STIM6 is shown in Figure 2-40 and described in Table 2-65.
Return to Summary Table.
Stimulus Port 6
Figure 2-40. STIM6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM6
R/W-X

Table 2-65. STIM6 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM6

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA6 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.8

STIM7 Register (Offset = 1Ch) [reset = X]

STIM7 is shown in Figure 2-41 and described in Table 2-66.
Return to Summary Table.
Stimulus Port 7
Figure 2-41. STIM7 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM7
R/W-X

Table 2-66. STIM7 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM7

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA7 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

2.7.3.9

www.ti.com

STIM8 Register (Offset = 20h) [reset = X]

STIM8 is shown in Figure 2-42 and described in Table 2-67.
Return to Summary Table.
Stimulus Port 8
Figure 2-42. STIM8 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM8
R/W-X

Table 2-67. STIM8 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM8

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA8 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.10 STIM9 Register (Offset = 24h) [reset = X]
STIM9 is shown in Figure 2-43 and described in Table 2-68.
Return to Summary Table.
Stimulus Port 9
Figure 2-43. STIM9 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM9
R/W-X

Table 2-68. STIM9 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM9

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA9 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.11 STIM10 Register (Offset = 28h) [reset = X]
STIM10 is shown in Figure 2-44 and described in Table 2-69.
Return to Summary Table.
Stimulus Port 10
Figure 2-44. STIM10 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM10
R/W-X

Table 2-69. STIM10 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM10

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA10 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.12 STIM11 Register (Offset = 2Ch) [reset = X]
STIM11 is shown in Figure 2-45 and described in Table 2-70.
Return to Summary Table.
Stimulus Port 11
Figure 2-45. STIM11 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM11
R/W-X

Table 2-70. STIM11 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM11

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA11 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.13 STIM12 Register (Offset = 30h) [reset = X]
STIM12 is shown in Figure 2-46 and described in Table 2-71.
Return to Summary Table.
Stimulus Port 12
Figure 2-46. STIM12 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM12
R/W-X

Table 2-71. STIM12 Register Field Descriptions
Bit
31-0

100

Field

Type

Reset

Description

STIM12

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA12 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.14 STIM13 Register (Offset = 34h) [reset = X]
STIM13 is shown in Figure 2-47 and described in Table 2-72.
Return to Summary Table.
Stimulus Port 13
Figure 2-47. STIM13 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM13
R/W-X

Table 2-72. STIM13 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM13

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA13 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

101

Cortex-M3 Processor Registers

www.ti.com

2.7.3.15 STIM14 Register (Offset = 38h) [reset = X]
STIM14 is shown in Figure 2-48 and described in Table 2-73.
Return to Summary Table.
Stimulus Port 14
Figure 2-48. STIM14 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM14
R/W-X

Table 2-73. STIM14 Register Field Descriptions
Bit
31-0

102

Field

Type

Reset

Description

STIM14

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA14 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.16 STIM15 Register (Offset = 3Ch) [reset = X]
STIM15 is shown in Figure 2-49 and described in Table 2-74.
Return to Summary Table.
Stimulus Port 15
Figure 2-49. STIM15 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM15
R/W-X

Table 2-74. STIM15 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM15

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA15 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

103

Cortex-M3 Processor Registers

www.ti.com

2.7.3.17 STIM16 Register (Offset = 40h) [reset = X]
STIM16 is shown in Figure 2-50 and described in Table 2-75.
Return to Summary Table.
Stimulus Port 16
Figure 2-50. STIM16 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM16
R/W-X

Table 2-75. STIM16 Register Field Descriptions
Bit
31-0

104

Field

Type

Reset

Description

STIM16

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA16 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.18 STIM17 Register (Offset = 44h) [reset = X]
STIM17 is shown in Figure 2-51 and described in Table 2-76.
Return to Summary Table.
Stimulus Port 17
Figure 2-51. STIM17 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM17
R/W-X

Table 2-76. STIM17 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM17

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA17 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

105

Cortex-M3 Processor Registers

www.ti.com

2.7.3.19 STIM18 Register (Offset = 48h) [reset = X]
STIM18 is shown in Figure 2-52 and described in Table 2-77.
Return to Summary Table.
Stimulus Port 18
Figure 2-52. STIM18 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM18
R/W-X

Table 2-77. STIM18 Register Field Descriptions
Bit
31-0

106

Field

Type

Reset

Description

STIM18

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA18 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.20 STIM19 Register (Offset = 4Ch) [reset = X]
STIM19 is shown in Figure 2-53 and described in Table 2-78.
Return to Summary Table.
Stimulus Port 19
Figure 2-53. STIM19 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM19
R/W-X

Table 2-78. STIM19 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM19

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA19 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

107

Cortex-M3 Processor Registers

www.ti.com

2.7.3.21 STIM20 Register (Offset = 50h) [reset = X]
STIM20 is shown in Figure 2-54 and described in Table 2-79.
Return to Summary Table.
Stimulus Port 20
Figure 2-54. STIM20 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM20
R/W-X

Table 2-79. STIM20 Register Field Descriptions
Bit
31-0

108

Field

Type

Reset

Description

STIM20

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA20 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.22 STIM21 Register (Offset = 54h) [reset = X]
STIM21 is shown in Figure 2-55 and described in Table 2-80.
Return to Summary Table.
Stimulus Port 21
Figure 2-55. STIM21 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM21
R/W-X

Table 2-80. STIM21 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM21

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA21 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

109

Cortex-M3 Processor Registers

www.ti.com

2.7.3.23 STIM22 Register (Offset = 58h) [reset = X]
STIM22 is shown in Figure 2-56 and described in Table 2-81.
Return to Summary Table.
Stimulus Port 22
Figure 2-56. STIM22 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM22
R/W-X

Table 2-81. STIM22 Register Field Descriptions
Bit
31-0

110

Field

Type

Reset

Description

STIM22

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA22 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.24 STIM23 Register (Offset = 5Ch) [reset = X]
STIM23 is shown in Figure 2-57 and described in Table 2-82.
Return to Summary Table.
Stimulus Port 23
Figure 2-57. STIM23 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM23
R/W-X

Table 2-82. STIM23 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM23

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA23 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

111

Cortex-M3 Processor Registers

www.ti.com

2.7.3.25 STIM24 Register (Offset = 60h) [reset = X]
STIM24 is shown in Figure 2-58 and described in Table 2-83.
Return to Summary Table.
Stimulus Port 24
Figure 2-58. STIM24 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM24
R/W-X

Table 2-83. STIM24 Register Field Descriptions
Bit
31-0

112

Field

Type

Reset

Description

STIM24

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA24 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.26 STIM25 Register (Offset = 64h) [reset = X]
STIM25 is shown in Figure 2-59 and described in Table 2-84.
Return to Summary Table.
Stimulus Port 25
Figure 2-59. STIM25 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM25
R/W-X

Table 2-84. STIM25 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM25

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA25 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

113

Cortex-M3 Processor Registers

www.ti.com

2.7.3.27 STIM26 Register (Offset = 68h) [reset = X]
STIM26 is shown in Figure 2-60 and described in Table 2-85.
Return to Summary Table.
Stimulus Port 26
Figure 2-60. STIM26 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM26
R/W-X

Table 2-85. STIM26 Register Field Descriptions
Bit
31-0

114

Field

Type

Reset

Description

STIM26

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA26 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.28 STIM27 Register (Offset = 6Ch) [reset = X]
STIM27 is shown in Figure 2-61 and described in Table 2-86.
Return to Summary Table.
Stimulus Port 27
Figure 2-61. STIM27 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM27
R/W-X

Table 2-86. STIM27 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM27

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA27 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

115

Cortex-M3 Processor Registers

www.ti.com

2.7.3.29 STIM28 Register (Offset = 70h) [reset = X]
STIM28 is shown in Figure 2-62 and described in Table 2-87.
Return to Summary Table.
Stimulus Port 28
Figure 2-62. STIM28 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM28
R/W-X

Table 2-87. STIM28 Register Field Descriptions
Bit
31-0

116

Field

Type

Reset

Description

STIM28

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA28 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.30 STIM29 Register (Offset = 74h) [reset = X]
STIM29 is shown in Figure 2-63 and described in Table 2-88.
Return to Summary Table.
Stimulus Port 29
Figure 2-63. STIM29 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM29
R/W-X

Table 2-88. STIM29 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM29

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA29 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

117

Cortex-M3 Processor Registers

www.ti.com

2.7.3.31 STIM30 Register (Offset = 78h) [reset = X]
STIM30 is shown in Figure 2-64 and described in Table 2-89.
Return to Summary Table.
Stimulus Port 30
Figure 2-64. STIM30 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM30
R/W-X

Table 2-89. STIM30 Register Field Descriptions
Bit
31-0

118

Field

Type

Reset

Description

STIM30

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA30 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.32 STIM31 Register (Offset = 7Ch) [reset = X]
STIM31 is shown in Figure 2-65 and described in Table 2-90.
Return to Summary Table.
Stimulus Port 31
Figure 2-65. STIM31 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STIM31
R/W-X

Table 2-90. STIM31 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

STIM31

R/W

A write to this location causes data to be written into the FIFO if
TER.STIMENA31 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

119

Cortex-M3 Processor Registers

www.ti.com

2.7.3.33 TER Register (Offset = E00h) [reset = 0h]
TER is shown in Figure 2-66 and described in Table 2-91.
Return to Summary Table.
Trace Enable
Use the Trace Enable Register to generate trace data by writing to the corresponding stimulus port. Note:
Privileged writes are accepted to this register if TCR.ITMENA is set. User writes are accepted to this
register if TCR.ITMENA is set and the appropriate privilege mask is cleared. Privileged access to the
stimulus ports enables an RTOS kernel to guarantee instrumentation slots or bandwidth as required.
Figure 2-66. TER Register
31
STIMENA31
R/W-0h

30
STIMENA30
R/W-0h

29
STIMENA29
R/W-0h

28
STIMENA28
R/W-0h

27
STIMENA27
R/W-0h

26
STIMENA26
R/W-0h

25
STIMENA25
R/W-0h

24
STIMENA24
R/W-0h

23
STIMENA23
R/W-0h

22
STIMENA22
R/W-0h

21
STIMENA21
R/W-0h

20
STIMENA20
R/W-0h

19
STIMENA19
R/W-0h

18
STIMENA18
R/W-0h

17
STIMENA17
R/W-0h

16
STIMENA16
R/W-0h

15
STIMENA15
R/W-0h

14
STIMENA14
R/W-0h

13
STIMENA13
R/W-0h

12
STIMENA12
R/W-0h

11
STIMENA11
R/W-0h

10
STIMENA10
R/W-0h

9
STIMENA9
R/W-0h

8
STIMENA8
R/W-0h

7
STIMENA7
R/W-0h

6
STIMENA6
R/W-0h

5
STIMENA5
R/W-0h

4
STIMENA4
R/W-0h

3
STIMENA3
R/W-0h

2
STIMENA2
R/W-0h

1
STIMENA1
R/W-0h

0
STIMENA0
R/W-0h

Table 2-91. TER Register Field Descriptions

120

Bit

Field

Type

Reset

Description

STIMENA31

R/W

Bit mask to enable tracing on ITM stimulus port 31.

STIMENA30

R/W

Bit mask to enable tracing on ITM stimulus port 30.

STIMENA29

R/W

Bit mask to enable tracing on ITM stimulus port 29.

STIMENA28

R/W

Bit mask to enable tracing on ITM stimulus port 28.

STIMENA27

R/W

Bit mask to enable tracing on ITM stimulus port 27.

STIMENA26

R/W

Bit mask to enable tracing on ITM stimulus port 26.

STIMENA25

R/W

Bit mask to enable tracing on ITM stimulus port 25.

STIMENA24

R/W

Bit mask to enable tracing on ITM stimulus port 24.

STIMENA23

R/W

Bit mask to enable tracing on ITM stimulus port 23.

STIMENA22

R/W

Bit mask to enable tracing on ITM stimulus port 22.

STIMENA21

R/W

Bit mask to enable tracing on ITM stimulus port 21.

STIMENA20

R/W

Bit mask to enable tracing on ITM stimulus port 20.

STIMENA19

R/W

Bit mask to enable tracing on ITM stimulus port 19.

STIMENA18

R/W

Bit mask to enable tracing on ITM stimulus port 18.

STIMENA17

R/W

Bit mask to enable tracing on ITM stimulus port 17.

STIMENA16

R/W

Bit mask to enable tracing on ITM stimulus port 16.

STIMENA15

R/W

Bit mask to enable tracing on ITM stimulus port 15.

STIMENA14

R/W

Bit mask to enable tracing on ITM stimulus port 14.

STIMENA13

R/W

Bit mask to enable tracing on ITM stimulus port 13.

STIMENA12

R/W

Bit mask to enable tracing on ITM stimulus port 12.

STIMENA11

R/W

Bit mask to enable tracing on ITM stimulus port 11.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-91. TER Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

STIMENA10

R/W

Bit mask to enable tracing on ITM stimulus port 10.

STIMENA9

R/W

Bit mask to enable tracing on ITM stimulus port 9.

STIMENA8

R/W

Bit mask to enable tracing on ITM stimulus port 8.

STIMENA7

R/W

Bit mask to enable tracing on ITM stimulus port 7.

STIMENA6

R/W

Bit mask to enable tracing on ITM stimulus port 6.

STIMENA5

R/W

Bit mask to enable tracing on ITM stimulus port 5.

STIMENA4

R/W

Bit mask to enable tracing on ITM stimulus port 4.

STIMENA3

R/W

Bit mask to enable tracing on ITM stimulus port 3.

STIMENA2

R/W

Bit mask to enable tracing on ITM stimulus port 2.

STIMENA1

R/W

Bit mask to enable tracing on ITM stimulus port 1.

STIMENA0

R/W

Bit mask to enable tracing on ITM stimulus port 0.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

121

Cortex-M3 Processor Registers

www.ti.com

2.7.3.34 TPR Register (Offset = E40h) [reset = 0h]
TPR is shown in Figure 2-67 and described in Table 2-92.
Return to Summary Table.
Trace Privilege
This register is used to enable an operating system to control which stimulus ports are accessible by user
code. This register can only be used in privileged mode.
Figure 2-67. TPR Register
31

10
9
RESERVED
R/W-0h

24
23
RESERVED
R/W-0h
8

2
1
PRIVMASK
R/W-0h

Table 2-92. TPR Register Field Descriptions
Bit

122

Field

Type

Reset

Description

31-4

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

PRIVMASK

R/W

Bit mask to enable unprivileged (User) access to ITM stimulus ports:
Bit [0] enables stimulus ports 0, 1, ..., and 7.
Bit [1] enables stimulus ports 8, 9, ..., and 15.
Bit [2] enables stimulus ports 16, 17, ..., and 23.
Bit [3] enables stimulus ports 24, 25, ..., and 31.
0: User access allowed to stimulus ports
1: Privileged access only to stimulus ports

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.35 TCR Register (Offset = E80h) [reset = 0h]
TCR is shown in Figure 2-68 and described in Table 2-93.
Return to Summary Table.
Trace Control
Use this register to configure and control ITM transfers. This register can only be written in privilege mode.
DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is controlled by
DWTENA. If DWT requires timestamping, the TSENA bit must be set.
Figure 2-68. TCR Register
31

19
ATBID
R/W-0h

RESERVED
R/W-0h
23
BUSY
R/W-0h

13
RESERVED
R/W-0h

6
RESERVED
R/W-0h

4
SWOENA
R/W-0h

8
TSPRESCALE
R/W-0h

3
DWTENA
R/W-0h

2
SYNCENA
R/W-0h

1
TSENA
R/W-0h

0
ITMENA
R/W-0h

Table 2-93. TCR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BUSY

R/W

Set when ITM events present and being drained.

22-16

ATBID

R/W

Trace Bus ID for CoreSight system. Optional identifier for multisource trace stream formatting. If multi-source trace is in use, this
field must be written with a non-zero value.

15-10

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

9-8

TSPRESCALE

R/W

Timestamp prescaler
0h = No prescaling
1h = Divide by 4
2h = Divide by 16
3h = Divide by 64

7-5

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWOENA

R/W

Enables asynchronous clocking of the timestamp counter (when
TSENA = 1). If TSENA = 0, writing this bit to 1 does not enable
asynchronous clocking of the timestamp counter.
0x0: Mode disabled. Timestamp counter uses system clock from the
core and counts continuously.
0x1: Timestamp counter uses lineout (data related) clock from TPIU
interface. The timestamp counter is held in reset while the output line
is idle.

DWTENA

R/W

Enables the DWT stimulus (hardware event packet emission to the
TPIU from the DWT)

SYNCENA

R/W

Enables synchronization packet transmission for a synchronous
TPIU.
CPU_DWT:CTRL.SYNCTAP must be configured for the correct
synchronization speed.

31-24

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

123

Cortex-M3 Processor Registers

www.ti.com

Table 2-93. TCR Register Field Descriptions (continued)
Bit

124

Field

Type

Reset

Description

TSENA

R/W

Enables differential timestamps. Differential timestamps are emitted
when a packet is written to the FIFO with a non-zero timestamp
counter, and when the timestamp counter overflows. Timestamps
are emitted during idle times after a fixed number of two million
cycles. This provides a time reference for packets and inter-packet
gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity
on the internal trace bus only. In this case there is no regular
timestamp output when the ITM is idle.

ITMENA

R/W

Enables ITM. This is the master enable, and must be set before ITM
Stimulus and Trace Enable registers can be written.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.3.36 LAR Register (Offset = FB0h) [reset = 0h]
LAR is shown in Figure 2-69 and described in Table 2-94.
Return to Summary Table.
Lock Access
This register is used to prevent write accesses to the Control Registers: TER, TPR and TCR.
Figure 2-69. LAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LOCK_ACCESS
W-0h

Table 2-94. LAR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

LOCK_ACCESS

A privileged write of 0xC5ACCE55 enables more write access to
Control Registers TER, TPR and TCR. An invalid write removes
write access.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

125

Cortex-M3 Processor Registers

www.ti.com

2.7.3.37 LSR Register (Offset = FB4h) [reset = 3h]
LSR is shown in Figure 2-70 and described in Table 2-95.
Return to Summary Table.
Lock Status
Use this register to enable write accesses to the Control Register.
Figure 2-70. LSR Register
31

2
BYTEACC
R-0h

1
ACCESS
R-1h

0
PRESENT
R-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

Table 2-95. LSR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BYTEACC

Reads 0 which means 8-bit lock access is not be implemented.

ACCESS

Write access to component is blocked. All writes are ignored, reads
are permitted.

PRESENT

Indicates that a lock mechanism exists for this component.

31-3

2.7.4 CPU_SCS Registers
Table 2-96 lists the memory-mapped registers for the CPU_SCS. All register offset addresses not listed in
Table 2-96 should be considered as reserved locations and the register contents should not be modified.
Table 2-96. CPU_SCS Registers
Offset

126

Acronym

Section

ICTR

Interrupt Control Type

Section 2.7.4.1

ACTLR

Auxiliary Control

Section 2.7.4.2

10h

STCSR

SysTick Control and Status

Section 2.7.4.3

14h

STRVR

SysTick Reload Value

Section 2.7.4.4

18h

STCVR

SysTick Current Value

Section 2.7.4.5

1Ch

STCR

SysTick Calibration Value

Section 2.7.4.6

100h

NVIC_ISER0

Irq 0 to 31 Set Enable

Section 2.7.4.7

104h

NVIC_ISER1

Irq 32 to 63 Set Enable

Section 2.7.4.8

180h

NVIC_ICER0

Irq 0 to 31 Clear Enable

Section 2.7.4.9

184h

NVIC_ICER1

Irq 32 to 63 Clear Enable

Section 2.7.4.10

200h

NVIC_ISPR0

Irq 0 to 31 Set Pending

Section 2.7.4.11

204h

NVIC_ISPR1

Irq 32 to 63 Set Pending

Section 2.7.4.12

280h

NVIC_ICPR0

Irq 0 to 31 Clear Pending

Section 2.7.4.13

284h

NVIC_ICPR1

Irq 32 to 63 Clear Pending

Section 2.7.4.14

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-96. CPU_SCS Registers (continued)
Offset

Acronym

300h

NVIC_IABR0

Irq 0 to 31 Active Bit

Section 2.7.4.15

Section

304h

NVIC_IABR1

Irq 32 to 63 Active Bit

Section 2.7.4.16

400h

NVIC_IPR0

Irq 0 to 3 Priority

Section 2.7.4.17

404h

NVIC_IPR1

Irq 4 to 7 Priority

Section 2.7.4.18

408h

NVIC_IPR2

Irq 8 to 11 Priority

Section 2.7.4.19

40Ch

NVIC_IPR3

Irq 12 to 15 Priority

Section 2.7.4.20

410h

NVIC_IPR4

Irq 16 to 19 Priority

Section 2.7.4.21

414h

NVIC_IPR5

Irq 20 to 23 Priority

Section 2.7.4.22

418h

NVIC_IPR6

Irq 24 to 27 Priority

Section 2.7.4.23

41Ch

NVIC_IPR7

Irq 28 to 31 Priority

Section 2.7.4.24

420h

NVIC_IPR8

Irq 32 to 35 Priority

Section 2.7.4.25

D00h

CPUID

CPUID Base

Section 2.7.4.26

D04h

ICSR

Interrupt Control State

Section 2.7.4.27

D08h

VTOR

Vector Table Offset

Section 2.7.4.28

D0Ch

AIRCR

Application Interrupt/Reset Control

Section 2.7.4.29

D10h

SCR

System Control

Section 2.7.4.30

D14h

CCR

Configuration Control

Section 2.7.4.31

D18h

SHPR1

System Handlers 4-7 Priority

Section 2.7.4.32

D1Ch

SHPR2

System Handlers 8-11 Priority

Section 2.7.4.33

D20h

SHPR3

System Handlers 12-15 Priority

Section 2.7.4.34

D24h

SHCSR

System Handler Control and State

Section 2.7.4.35

D28h

CFSR

Configurable Fault Status

Section 2.7.4.36

D2Ch

HFSR

Hard Fault Status

Section 2.7.4.37

D30h

DFSR

Debug Fault Status

Section 2.7.4.38

D34h

MMFAR

Mem Manage Fault Address

Section 2.7.4.39

D38h

BFAR

Bus Fault Address

Section 2.7.4.40

D3Ch

AFSR

Auxiliary Fault Status

Section 2.7.4.41

D40h

ID_PFR0

Processor Feature 0

Section 2.7.4.42

D44h

ID_PFR1

Processor Feature 1

Section 2.7.4.43

D48h

ID_DFR0

Debug Feature 0

Section 2.7.4.44

D4Ch

ID_AFR0

Auxiliary Feature 0

Section 2.7.4.45

D50h

ID_MMFR0

Memory Model Feature 0

Section 2.7.4.46

D54h

ID_MMFR1

Memory Model Feature 1

Section 2.7.4.47

D58h

ID_MMFR2

Memory Model Feature 2

Section 2.7.4.48

D5Ch

ID_MMFR3

Memory Model Feature 3

Section 2.7.4.49

D60h

ID_ISAR0

ISA Feature 0

Section 2.7.4.50

D64h

ID_ISAR1

ISA Feature 1

Section 2.7.4.51

D68h

ID_ISAR2

ISA Feature 2

Section 2.7.4.52

D6Ch

ID_ISAR3

ISA Feature 3

Section 2.7.4.53

D70h

ID_ISAR4

ISA Feature 4

Section 2.7.4.54

D88h

CPACR

Coprocessor Access Control

Section 2.7.4.55

DF0h

DHCSR

Debug Halting Control and Status

Section 2.7.4.56

DF4h

DCRSR

Deubg Core Register Selector

Section 2.7.4.57

DF8h

DCRDR

Debug Core Register Data

Section 2.7.4.58

DFCh

DEMCR

Debug Exception and Monitor Control

Section 2.7.4.59

F00h

STIR

Software Trigger Interrupt

Section 2.7.4.60

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

127

Cortex-M3 Processor Registers

2.7.4.1

www.ti.com

ICTR Register (Offset = 4h) [reset = 1h]

ICTR is shown in Figure 2-71 and described in Table 2-97.
Return to Summary Table.
Interrupt Control Type
Read this register to see the number of interrupt lines that the NVIC supports.
Figure 2-71. ICTR Register
31

1
INTLINESNUM
R-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

Table 2-97. ICTR Register Field Descriptions
Bit

128

Field

Type

Reset

Description

31-3

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

2-0

INTLINESNUM

Total number of interrupt lines in groups of 32.
0: 0...32
1: 33...64
2: 65...96
3: 97...128
4: 129...160
5: 161...192
6: 193...224
7: 225...256

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.2

ACTLR Register (Offset = 8h) [reset = 0h]

ACTLR is shown in Figure 2-72 and described in Table 2-98.
Return to Summary Table.
Auxiliary Control
This register is used to disable certain aspects of functionality within the processor
Figure 2-72. ACTLR Register
31

2
DISFOLD
R/W-0h

1
DISDEFWBUF
R/W-0h

0
DISMCYCINT
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

5
RESERVED
R/W-0h

Table 2-98. ACTLR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DISFOLD

R/W

Disables folding of IT instruction.

DISDEFWBUF

R/W

Disables write buffer use during default memory map accesses. This
causes all bus faults to be precise bus faults but decreases the
performance of the processor because the stores to memory have to
complete before the next instruction can be executed.

DISMCYCINT

R/W

Disables interruption of multi-cycle instructions. This increases the
interrupt latency of the processor becuase LDM/STM completes
before interrupt stacking occurs.

31-3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

129

Cortex-M3 Processor Registers

2.7.4.3

www.ti.com

STCSR Register (Offset = 10h) [reset = 4h]

STCSR is shown in Figure 2-73 and described in Table 2-99.
Return to Summary Table.
SysTick Control and Status
This register enables the SysTick features and returns status flags related to SysTick.
Figure 2-73. STCSR Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

16
COUNTFLAG
R-0h

2
CLKSOURCE
R-1h

1
TICKINT
R/W-0h

0
ENABLE
R/W-0h

RESERVED
R-0h
7

5
RESERVED
R-0h

Table 2-99. STCSR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

COUNTFLAG

Returns 1 if timer counted to 0 since last time this was read. Clears
on read by application of any part of the SysTick Control and Status
Register. If read by the debugger using the DAP, this bit is cleared
on read-only if the MasterType bit in the **AHB-AP** Control
Register is set to 0. Otherwise, COUNTFLAG is not changed by the
debugger read.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLKSOURCE

Clock source:
0: External reference clock.
1: Core clock
External clock is not available in this device. Writes to this field will
be ignored.

TICKINT

R/W

0: Counting down to zero does not pend the SysTick handler.
Software can use COUNTFLAG to determine if the SysTick handler
has ever counted to zero.
1: Counting down to zero pends the SysTick handler.

ENABLE

R/W

Enable SysTick counter
0: Counter disabled
1: Counter operates in a multi-shot way. That is, counter loads with
the Reload value STRVR.RELOAD and then begins counting down.
On reaching 0, it sets COUNTFLAG to 1 and optionally pends the
SysTick handler, based on TICKINT. It then loads STRVR.RELOAD
again, and begins counting.

31-17
16

15-3

130

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.4

STRVR Register (Offset = 14h) [reset = X]

STRVR is shown in Figure 2-74 and described in Table 2-100.
Return to Summary Table.
SysTick Reload Value
This register is used to specify the start value to load into the current value register STCVR.CURRENT
when the counter reaches 0. It can be any value between 1 and 0x00FFFFFF. A start value of 0 is
possible, but has no effect because the SysTick interrupt and STCSR.COUNTFLAG are activated when
counting from 1 to 0.
Figure 2-74. STRVR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
RELOAD
R/W-0h
R/W-X

Table 2-100. STRVR Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-0

RELOAD

R/W

Value to load into the SysTick Current Value Register
STCVR.CURRENT when the counter reaches 0.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

131

Cortex-M3 Processor Registers

2.7.4.5

www.ti.com

STCVR Register (Offset = 18h) [reset = X]

STCVR is shown in Figure 2-75 and described in Table 2-101.
Return to Summary Table.
SysTick Current Value
Read from this register returns the current value of SysTick counter. Writing to this register resets the
SysTick counter (as well as STCSR.COUNTFLAG).
Figure 2-75. STCVR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
CURRENT
R/W-0h
R/W-X

Table 2-101. STCVR Register Field Descriptions
Bit

132

Field

Type

Reset

Description

31-24

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-0

CURRENT

R/W

Current value at the time the register is accessed. No read-modifywrite protection is provided, so change with care. Writing to it with
any value clears the register to 0. Clearing this register also clears
STCSR.COUNTFLAG.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.6

STCR Register (Offset = 1Ch) [reset = C0075300h]

STCR is shown in Figure 2-76 and described in Table 2-102.
Return to Summary Table.
SysTick Calibration Value
Used to enable software to scale to any required speed using divide and multiply.
Figure 2-76. STCR Register
31
NOREF
R-1h

30
SKEW
R-1h

RESERVED
R-0h
20
TENMS
R-00075300h

12
TENMS
R-00075300h

4
TENMS
R-00075300h

Table 2-102. STCR Register Field Descriptions
Bit

Field

Type

Reset

Description

NOREF

Reads as one. Indicates that no separate reference clock is
provided.

SKEW

Reads as one. The calibration value is not exactly 10ms because of
clock frequency. This could affect its suitability as a software real
time clock.

29-24

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-0

TENMS

00075300h

An optional Reload value to be used for 10ms (100Hz) timing,
subject to system clock skew errors. The value read is valid only
when core clock is at 48MHz.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

133

Cortex-M3 Processor Registers

2.7.4.7

www.ti.com

NVIC_ISER0 Register (Offset = 100h) [reset = 0h]

NVIC_ISER0 is shown in Figure 2-77 and described in Table 2-103.
Return to Summary Table.
Irq 0 to 31 Set Enable
This register is used to enable interrupts and determine which interrupts are currently enabled.
Figure 2-77. NVIC_ISER0 Register
31
SETENA31
R/W-0h

30
SETENA30
R/W-0h

29
SETENA29
R/W-0h

28
SETENA28
R/W-0h

27
SETENA27
R/W-0h

26
SETENA26
R/W-0h

25
SETENA25
R/W-0h

24
SETENA24
R/W-0h

23
SETENA23
R/W-0h

22
SETENA22
R/W-0h

21
SETENA21
R/W-0h

20
SETENA20
R/W-0h

19
SETENA19
R/W-0h

18
SETENA18
R/W-0h

17
SETENA17
R/W-0h

16
SETENA16
R/W-0h

15
SETENA15
R/W-0h

14
SETENA14
R/W-0h

13
SETENA13
R/W-0h

12
SETENA12
R/W-0h

11
SETENA11
R/W-0h

10
SETENA10
R/W-0h

9
SETENA9
R/W-0h

8
SETENA8
R/W-0h

7
SETENA7
R/W-0h

6
SETENA6
R/W-0h

5
SETENA5
R/W-0h

4
SETENA4
R/W-0h

3
SETENA3
R/W-0h

2
SETENA2
R/W-0h

1
SETENA1
R/W-0h

0
SETENA0
R/W-0h

Table 2-103. NVIC_ISER0 Register Field Descriptions

134

Bit

Field

Type

Reset

Description

SETENA31

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details).
Reading the bit returns its current enable state.

SETENA30

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details).
Reading the bit returns its current enable state.

SETENA29

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details).
Reading the bit returns its current enable state.

SETENA28

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details).
Reading the bit returns its current enable state.

SETENA27

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details).
Reading the bit returns its current enable state.

SETENA26

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details).
Reading the bit returns its current enable state.

SETENA25

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details).
Reading the bit returns its current enable state.

SETENA24

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details).
Reading the bit returns its current enable state.

SETENA23

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details).
Reading the bit returns its current enable state.

SETENA22

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details).
Reading the bit returns its current enable state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-103. NVIC_ISER0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

SETENA21

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details).
Reading the bit returns its current enable state.

SETENA20

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details).
Reading the bit returns its current enable state.

SETENA19

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details).
Reading the bit returns its current enable state.

SETENA18

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details).
Reading the bit returns its current enable state.

SETENA17

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details).
Reading the bit returns its current enable state.

SETENA16

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details).
Reading the bit returns its current enable state.

SETENA15

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details).
Reading the bit returns its current enable state.

SETENA14

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details).
Reading the bit returns its current enable state.

SETENA13

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details).
Reading the bit returns its current enable state.

SETENA12

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details).
Reading the bit returns its current enable state.

SETENA11

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details).
Reading the bit returns its current enable state.

SETENA10

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details).
Reading the bit returns its current enable state.

SETENA9

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details).
Reading the bit returns its current enable state.

SETENA8

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details).
Reading the bit returns its current enable state.

SETENA7

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details).
Reading the bit returns its current enable state.

SETENA6

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details).
Reading the bit returns its current enable state.

SETENA5

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details).
Reading the bit returns its current enable state.

SETENA4

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details).
Reading the bit returns its current enable state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

135

Cortex-M3 Processor Registers

www.ti.com

Table 2-103. NVIC_ISER0 Register Field Descriptions (continued)
Bit

136

Field

Type

Reset

Description

SETENA3

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details).
Reading the bit returns its current enable state.

SETENA2

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details).
Reading the bit returns its current enable state.

SETENA1

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details).
Reading the bit returns its current enable state.

SETENA0

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details).
Reading the bit returns its current enable state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.8

NVIC_ISER1 Register (Offset = 104h) [reset = 0h]

NVIC_ISER1 is shown in Figure 2-78 and described in Table 2-104.
Return to Summary Table.
Irq 32 to 63 Set Enable
This register is used to enable interrupts and determine which interrupts are currently enabled.
Figure 2-78. NVIC_ISER1 Register
31

1
SETENA33
R/W-0h

0
SETENA32
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 2-104. NVIC_ISER1 Register Field Descriptions
Field

Type

Reset

Description

31-2

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SETENA33

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details).
Reading the bit returns its current enable state.

SETENA32

R/W

Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details).
Reading the bit returns its current enable state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

137

Cortex-M3 Processor Registers

2.7.4.9

www.ti.com

NVIC_ICER0 Register (Offset = 180h) [reset = 0h]

NVIC_ICER0 is shown in Figure 2-79 and described in Table 2-105.
Return to Summary Table.
Irq 0 to 31 Clear Enable
This register is used to disable interrupts and determine which interrupts are currently enabled.
Figure 2-79. NVIC_ICER0 Register
31
CLRENA31
R/W-0h

30
CLRENA30
R/W-0h

29
CLRENA29
R/W-0h

28
CLRENA28
R/W-0h

27
CLRENA27
R/W-0h

26
CLRENA26
R/W-0h

25
CLRENA25
R/W-0h

24
CLRENA24
R/W-0h

23
CLRENA23
R/W-0h

22
CLRENA22
R/W-0h

21
CLRENA21
R/W-0h

20
CLRENA20
R/W-0h

19
CLRENA19
R/W-0h

18
CLRENA18
R/W-0h

17
CLRENA17
R/W-0h

16
CLRENA16
R/W-0h

15
CLRENA15
R/W-0h

14
CLRENA14
R/W-0h

13
CLRENA13
R/W-0h

12
CLRENA12
R/W-0h

11
CLRENA11
R/W-0h

10
CLRENA10
R/W-0h

9
CLRENA9
R/W-0h

8
CLRENA8
R/W-0h

7
CLRENA7
R/W-0h

6
CLRENA6
R/W-0h

5
CLRENA5
R/W-0h

4
CLRENA4
R/W-0h

3
CLRENA3
R/W-0h

2
CLRENA2
R/W-0h

1
CLRENA1
R/W-0h

0
CLRENA0
R/W-0h

Table 2-105. NVIC_ICER0 Register Field Descriptions

138

Bit

Field

Type

Reset

Description

CLRENA31

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details).
Reading the bit returns its current enable state.

CLRENA30

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details).
Reading the bit returns its current enable state.

CLRENA29

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details).
Reading the bit returns its current enable state.

CLRENA28

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details).
Reading the bit returns its current enable state.

CLRENA27

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details).
Reading the bit returns its current enable state.

CLRENA26

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details).
Reading the bit returns its current enable state.

CLRENA25

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details).
Reading the bit returns its current enable state.

CLRENA24

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details).
Reading the bit returns its current enable state.

CLRENA23

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details).
Reading the bit returns its current enable state.

CLRENA22

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details).
Reading the bit returns its current enable state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-105. NVIC_ICER0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

CLRENA21

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details).
Reading the bit returns its current enable state.

CLRENA20

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details).
Reading the bit returns its current enable state.

CLRENA19

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details).
Reading the bit returns its current enable state.

CLRENA18

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details).
Reading the bit returns its current enable state.

CLRENA17

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details).
Reading the bit returns its current enable state.

CLRENA16

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details).
Reading the bit returns its current enable state.

CLRENA15

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details).
Reading the bit returns its current enable state.

CLRENA14

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details).
Reading the bit returns its current enable state.

CLRENA13

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details).
Reading the bit returns its current enable state.

CLRENA12

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details).
Reading the bit returns its current enable state.

CLRENA11

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details).
Reading the bit returns its current enable state.

CLRENA10

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details).
Reading the bit returns its current enable state.

CLRENA9

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details).
Reading the bit returns its current enable state.

CLRENA8

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details).
Reading the bit returns its current enable state.

CLRENA7

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details).
Reading the bit returns its current enable state.

CLRENA6

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details).
Reading the bit returns its current enable state.

CLRENA5

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details).
Reading the bit returns its current enable state.

CLRENA4

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details).
Reading the bit returns its current enable state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

139

Cortex-M3 Processor Registers

www.ti.com

Table 2-105. NVIC_ICER0 Register Field Descriptions (continued)
Bit

140

Field

Type

Reset

Description

CLRENA3

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details).
Reading the bit returns its current enable state.

CLRENA2

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details).
Reading the bit returns its current enable state.

CLRENA1

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details).
Reading the bit returns its current enable state.

CLRENA0

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details).
Reading the bit returns its current enable state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.10 NVIC_ICER1 Register (Offset = 184h) [reset = 0h]
NVIC_ICER1 is shown in Figure 2-80 and described in Table 2-106.
Return to Summary Table.
Irq 32 to 63 Clear Enable
This register is used to disable interrupts and determine which interrupts are currently enabled.
Figure 2-80. NVIC_ICER1 Register
31

1
CLRENA33
R/W-0h

0
CLRENA32
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 2-106. NVIC_ICER1 Register Field Descriptions
Field

Type

Reset

Description

31-2

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLRENA33

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details).
Reading the bit returns its current enable state.

CLRENA32

R/W

Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details).
Reading the bit returns its current enable state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

141

Cortex-M3 Processor Registers

www.ti.com

2.7.4.11 NVIC_ISPR0 Register (Offset = 200h) [reset = 0h]
NVIC_ISPR0 is shown in Figure 2-81 and described in Table 2-107.
Return to Summary Table.
Irq 0 to 31 Set Pending
This register is used to force interrupts into the pending state and determine which interrupts are currently
pending.
Figure 2-81. NVIC_ISPR0 Register
31
SETPEND31
R/W-0h

30
SETPEND30
R/W-0h

29
SETPEND29
R/W-0h

28
SETPEND28
R/W-0h

27
SETPEND27
R/W-0h

26
SETPEND26
R/W-0h

25
SETPEND25
R/W-0h

24
SETPEND24
R/W-0h

23
SETPEND23
R/W-0h

22
SETPEND22
R/W-0h

21
SETPEND21
R/W-0h

20
SETPEND20
R/W-0h

19
SETPEND19
R/W-0h

18
SETPEND18
R/W-0h

17
SETPEND17
R/W-0h

16
SETPEND16
R/W-0h

15
SETPEND15
R/W-0h

14
SETPEND14
R/W-0h

13
SETPEND13
R/W-0h

12
SETPEND12
R/W-0h

11
SETPEND11
R/W-0h

10
SETPEND10
R/W-0h

9
SETPEND9
R/W-0h

8
SETPEND8
R/W-0h

7
SETPEND7
R/W-0h

6
SETPEND6
R/W-0h

5
SETPEND5
R/W-0h

4
SETPEND4
R/W-0h

3
SETPEND3
R/W-0h

2
SETPEND2
R/W-0h

1
SETPEND1
R/W-0h

0
SETPEND0
R/W-0h

Table 2-107. NVIC_ISPR0 Register Field Descriptions

142

Bit

Field

Type

Reset

Description

SETPEND31

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details).
Reading the bit returns its current state.

SETPEND30

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details).
Reading the bit returns its current state.

SETPEND29

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details).
Reading the bit returns its current state.

SETPEND28

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details).
Reading the bit returns its current state.

SETPEND27

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details).
Reading the bit returns its current state.

SETPEND26

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details).
Reading the bit returns its current state.

SETPEND25

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details).
Reading the bit returns its current state.

SETPEND24

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details).
Reading the bit returns its current state.

SETPEND23

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details).
Reading the bit returns its current state.

SETPEND22

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details).
Reading the bit returns its current state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-107. NVIC_ISPR0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

SETPEND21

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details).
Reading the bit returns its current state.

SETPEND20

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details).
Reading the bit returns its current state.

SETPEND19

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details).
Reading the bit returns its current state.

SETPEND18

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details).
Reading the bit returns its current state.

SETPEND17

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details).
Reading the bit returns its current state.

SETPEND16

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details).
Reading the bit returns its current state.

SETPEND15

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details).
Reading the bit returns its current state.

SETPEND14

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details).
Reading the bit returns its current state.

SETPEND13

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details).
Reading the bit returns its current state.

SETPEND12

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details).
Reading the bit returns its current state.

SETPEND11

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details).
Reading the bit returns its current state.

SETPEND10

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details).
Reading the bit returns its current state.

SETPEND9

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details).
Reading the bit returns its current state.

SETPEND8

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details).
Reading the bit returns its current state.

SETPEND7

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details).
Reading the bit returns its current state.

SETPEND6

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details).
Reading the bit returns its current state.

SETPEND5

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details).
Reading the bit returns its current state.

SETPEND4

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details).
Reading the bit returns its current state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

143

Cortex-M3 Processor Registers

www.ti.com

Table 2-107. NVIC_ISPR0 Register Field Descriptions (continued)
Bit

144

Field

Type

Reset

Description

SETPEND3

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details).
Reading the bit returns its current state.

SETPEND2

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details).
Reading the bit returns its current state.

SETPEND1

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details).
Reading the bit returns its current state.

SETPEND0

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details).
Reading the bit returns its current state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.12 NVIC_ISPR1 Register (Offset = 204h) [reset = 0h]
NVIC_ISPR1 is shown in Figure 2-82 and described in Table 2-108.
Return to Summary Table.
Irq 32 to 63 Set Pending
This register is used to force interrupts into the pending state and determine which interrupts are currently
pending.
Figure 2-82. NVIC_ISPR1 Register
31

1
SETPEND33
R/W-0h

0
SETPEND32
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 2-108. NVIC_ISPR1 Register Field Descriptions
Field

Type

Reset

Description

31-2

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SETPEND33

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details).
Reading the bit returns its current state.

SETPEND32

R/W

Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details).
Reading the bit returns its current state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

145

Cortex-M3 Processor Registers

www.ti.com

2.7.4.13 NVIC_ICPR0 Register (Offset = 280h) [reset = 0h]
NVIC_ICPR0 is shown in Figure 2-83 and described in Table 2-109.
Return to Summary Table.
Irq 0 to 31 Clear Pending
This register is used to clear pending interrupts and determine which interrupts are currently pending.
Figure 2-83. NVIC_ICPR0 Register
31
CLRPEND31
R/W-0h

30
CLRPEND30
R/W-0h

29
CLRPEND29
R/W-0h

28
CLRPEND28
R/W-0h

27
CLRPEND27
R/W-0h

26
CLRPEND26
R/W-0h

25
CLRPEND25
R/W-0h

24
CLRPEND24
R/W-0h

23
CLRPEND23
R/W-0h

22
CLRPEND22
R/W-0h

21
CLRPEND21
R/W-0h

20
CLRPEND20
R/W-0h

19
CLRPEND19
R/W-0h

18
CLRPEND18
R/W-0h

17
CLRPEND17
R/W-0h

16
CLRPEND16
R/W-0h

15
CLRPEND15
R/W-0h

14
CLRPEND14
R/W-0h

13
CLRPEND13
R/W-0h

12
CLRPEND12
R/W-0h

11
CLRPEND11
R/W-0h

10
CLRPEND10
R/W-0h

9
CLRPEND9
R/W-0h

8
CLRPEND8
R/W-0h

7
CLRPEND7
R/W-0h

6
CLRPEND6
R/W-0h

5
CLRPEND5
R/W-0h

4
CLRPEND4
R/W-0h

3
CLRPEND3
R/W-0h

2
CLRPEND2
R/W-0h

1
CLRPEND1
R/W-0h

0
CLRPEND0
R/W-0h

Table 2-109. NVIC_ICPR0 Register Field Descriptions

146

Bit

Field

Type

Reset

Description

CLRPEND31

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV
for details). Reading the bit returns its current state.

CLRPEND30

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV
for details). Reading the bit returns its current state.

CLRPEND29

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV
for details). Reading the bit returns its current state.

CLRPEND28

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV
for details). Reading the bit returns its current state.

CLRPEND27

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV
for details). Reading the bit returns its current state.

CLRPEND26

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV
for details). Reading the bit returns its current state.

CLRPEND25

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV
for details). Reading the bit returns its current state.

CLRPEND24

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV
for details). Reading the bit returns its current state.

CLRPEND23

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV
for details). Reading the bit returns its current state.

CLRPEND22

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV
for details). Reading the bit returns its current state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-109. NVIC_ICPR0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

CLRPEND21

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV
for details). Reading the bit returns its current state.

CLRPEND20

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV
for details). Reading the bit returns its current state.

CLRPEND19

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV
for details). Reading the bit returns its current state.

CLRPEND18

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV
for details). Reading the bit returns its current state.

CLRPEND17

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV
for details). Reading the bit returns its current state.

CLRPEND16

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV
for details). Reading the bit returns its current state.

CLRPEND15

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV
for details). Reading the bit returns its current state.

CLRPEND14

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV
for details). Reading the bit returns its current state.

CLRPEND13

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV
for details). Reading the bit returns its current state.

CLRPEND12

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV
for details). Reading the bit returns its current state.

CLRPEND11

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV
for details). Reading the bit returns its current state.

CLRPEND10

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV
for details). Reading the bit returns its current state.

CLRPEND9

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV
for details). Reading the bit returns its current state.

CLRPEND8

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV
for details). Reading the bit returns its current state.

CLRPEND7

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV
for details). Reading the bit returns its current state.

CLRPEND6

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV
for details). Reading the bit returns its current state.

CLRPEND5

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV
for details). Reading the bit returns its current state.

CLRPEND4

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV
for details). Reading the bit returns its current state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

147

Cortex-M3 Processor Registers

www.ti.com

Table 2-109. NVIC_ICPR0 Register Field Descriptions (continued)
Bit

148

Field

Type

Reset

Description

CLRPEND3

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV
for details). Reading the bit returns its current state.

CLRPEND2

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV
for details). Reading the bit returns its current state.

CLRPEND1

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV
for details). Reading the bit returns its current state.

CLRPEND0

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV
for details). Reading the bit returns its current state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.14 NVIC_ICPR1 Register (Offset = 284h) [reset = 0h]
NVIC_ICPR1 is shown in Figure 2-84 and described in Table 2-110.
Return to Summary Table.
Irq 32 to 63 Clear Pending
This register is used to clear pending interrupts and determine which interrupts are currently pending.
Figure 2-84. NVIC_ICPR1 Register
31

1
CLRPEND33
R/W-0h

0
CLRPEND32
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 2-110. NVIC_ICPR1 Register Field Descriptions
Field

Type

Reset

Description

31-2

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLRPEND33

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV
for details). Reading the bit returns its current state.

CLRPEND32

R/W

Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV
for details). Reading the bit returns its current state.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

149

Cortex-M3 Processor Registers

www.ti.com

2.7.4.15 NVIC_IABR0 Register (Offset = 300h) [reset = 0h]
NVIC_IABR0 is shown in Figure 2-85 and described in Table 2-111.
Return to Summary Table.
Irq 0 to 31 Active Bit
This register is used to determine which interrupts are active. Each flag in the register corresponds to one
interrupt.
Figure 2-85. NVIC_IABR0 Register
31
ACTIVE31
R-0h

30
ACTIVE30
R-0h

29
ACTIVE29
R-0h

28
ACTIVE28
R-0h

27
ACTIVE27
R-0h

26
ACTIVE26
R-0h

25
ACTIVE25
R-0h

24
ACTIVE24
R-0h

23
ACTIVE23
R-0h

22
ACTIVE22
R-0h

21
ACTIVE21
R-0h

20
ACTIVE20
R-0h

19
ACTIVE19
R-0h

18
ACTIVE18
R-0h

17
ACTIVE17
R-0h

16
ACTIVE16
R-0h

15
ACTIVE15
R-0h

14
ACTIVE14
R-0h

13
ACTIVE13
R-0h

12
ACTIVE12
R-0h

11
ACTIVE11
R-0h

10
ACTIVE10
R-0h

9
ACTIVE9
R-0h

8
ACTIVE8
R-0h

7
ACTIVE7
R-0h

6
ACTIVE6
R-0h

5
ACTIVE5
R-0h

4
ACTIVE4
R-0h

3
ACTIVE3
R-0h

2
ACTIVE2
R-0h

1
ACTIVE1
R-0h

0
ACTIVE0
R-0h

Table 2-111. NVIC_IABR0 Register Field Descriptions

150

Bit

Field

Type

Reset

Description

ACTIVE31

Reading 0 from this bit implies that interrupt line 31 is not active.
Reading 1 from this bit implies that the interrupt line 31 is active (See
EVENT:CPUIRQSEL31.EV for details).

ACTIVE30

Reading 0 from this bit implies that interrupt line 30 is not active.
Reading 1 from this bit implies that the interrupt line 30 is active (See
EVENT:CPUIRQSEL30.EV for details).

ACTIVE29

Reading 0 from this bit implies that interrupt line 29 is not active.
Reading 1 from this bit implies that the interrupt line 29 is active (See
EVENT:CPUIRQSEL29.EV for details).

ACTIVE28

Reading 0 from this bit implies that interrupt line 28 is not active.
Reading 1 from this bit implies that the interrupt line 28 is active (See
EVENT:CPUIRQSEL28.EV for details).

ACTIVE27

Reading 0 from this bit implies that interrupt line 27 is not active.
Reading 1 from this bit implies that the interrupt line 27 is active (See
EVENT:CPUIRQSEL27.EV for details).

ACTIVE26

Reading 0 from this bit implies that interrupt line 26 is not active.
Reading 1 from this bit implies that the interrupt line 26 is active (See
EVENT:CPUIRQSEL26.EV for details).

ACTIVE25

Reading 0 from this bit implies that interrupt line 25 is not active.
Reading 1 from this bit implies that the interrupt line 25 is active (See
EVENT:CPUIRQSEL25.EV for details).

ACTIVE24

Reading 0 from this bit implies that interrupt line 24 is not active.
Reading 1 from this bit implies that the interrupt line 24 is active (See
EVENT:CPUIRQSEL24.EV for details).

ACTIVE23

Reading 0 from this bit implies that interrupt line 23 is not active.
Reading 1 from this bit implies that the interrupt line 23 is active (See
EVENT:CPUIRQSEL23.EV for details).

ACTIVE22

Reading 0 from this bit implies that interrupt line 22 is not active.
Reading 1 from this bit implies that the interrupt line 22 is active (See
EVENT:CPUIRQSEL22.EV for details).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-111. NVIC_IABR0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

ACTIVE21

Reading 0 from this bit implies that interrupt line 21 is not active.
Reading 1 from this bit implies that the interrupt line 21 is active (See
EVENT:CPUIRQSEL21.EV for details).

ACTIVE20

Reading 0 from this bit implies that interrupt line 20 is not active.
Reading 1 from this bit implies that the interrupt line 20 is active (See
EVENT:CPUIRQSEL20.EV for details).

ACTIVE19

Reading 0 from this bit implies that interrupt line 19 is not active.
Reading 1 from this bit implies that the interrupt line 19 is active (See
EVENT:CPUIRQSEL19.EV for details).

ACTIVE18

Reading 0 from this bit implies that interrupt line 18 is not active.
Reading 1 from this bit implies that the interrupt line 18 is active (See
EVENT:CPUIRQSEL18.EV for details).

ACTIVE17

Reading 0 from this bit implies that interrupt line 17 is not active.
Reading 1 from this bit implies that the interrupt line 17 is active (See
EVENT:CPUIRQSEL17.EV for details).

ACTIVE16

Reading 0 from this bit implies that interrupt line 16 is not active.
Reading 1 from this bit implies that the interrupt line 16 is active (See
EVENT:CPUIRQSEL16.EV for details).

ACTIVE15

Reading 0 from this bit implies that interrupt line 15 is not active.
Reading 1 from this bit implies that the interrupt line 15 is active (See
EVENT:CPUIRQSEL15.EV for details).

ACTIVE14

Reading 0 from this bit implies that interrupt line 14 is not active.
Reading 1 from this bit implies that the interrupt line 14 is active (See
EVENT:CPUIRQSEL14.EV for details).

ACTIVE13

Reading 0 from this bit implies that interrupt line 13 is not active.
Reading 1 from this bit implies that the interrupt line 13 is active (See
EVENT:CPUIRQSEL13.EV for details).

ACTIVE12

Reading 0 from this bit implies that interrupt line 12 is not active.
Reading 1 from this bit implies that the interrupt line 12 is active (See
EVENT:CPUIRQSEL12.EV for details).

ACTIVE11

Reading 0 from this bit implies that interrupt line 11 is not active.
Reading 1 from this bit implies that the interrupt line 11 is active (See
EVENT:CPUIRQSEL11.EV for details).

ACTIVE10

Reading 0 from this bit implies that interrupt line 10 is not active.
Reading 1 from this bit implies that the interrupt line 10 is active (See
EVENT:CPUIRQSEL10.EV for details).

ACTIVE9

Reading 0 from this bit implies that interrupt line 9 is not active.
Reading 1 from this bit implies that the interrupt line 9 is active (See
EVENT:CPUIRQSEL9.EV for details).

ACTIVE8

Reading 0 from this bit implies that interrupt line 8 is not active.
Reading 1 from this bit implies that the interrupt line 8 is active (See
EVENT:CPUIRQSEL8.EV for details).

ACTIVE7

Reading 0 from this bit implies that interrupt line 7 is not active.
Reading 1 from this bit implies that the interrupt line 7 is active (See
EVENT:CPUIRQSEL7.EV for details).

ACTIVE6

Reading 0 from this bit implies that interrupt line 6 is not active.
Reading 1 from this bit implies that the interrupt line 6 is active (See
EVENT:CPUIRQSEL6.EV for details).

ACTIVE5

Reading 0 from this bit implies that interrupt line 5 is not active.
Reading 1 from this bit implies that the interrupt line 5 is active (See
EVENT:CPUIRQSEL5.EV for details).

ACTIVE4

Reading 0 from this bit implies that interrupt line 4 is not active.
Reading 1 from this bit implies that the interrupt line 4 is active (See
EVENT:CPUIRQSEL4.EV for details).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

151

Cortex-M3 Processor Registers

www.ti.com

Table 2-111. NVIC_IABR0 Register Field Descriptions (continued)
Bit

152

Field

Type

Reset

Description

ACTIVE3

Reading 0 from this bit implies that interrupt line 3 is not active.
Reading 1 from this bit implies that the interrupt line 3 is active (See
EVENT:CPUIRQSEL3.EV for details).

ACTIVE2

Reading 0 from this bit implies that interrupt line 2 is not active.
Reading 1 from this bit implies that the interrupt line 2 is active (See
EVENT:CPUIRQSEL2.EV for details).

ACTIVE1

Reading 0 from this bit implies that interrupt line 1 is not active.
Reading 1 from this bit implies that the interrupt line 1 is active (See
EVENT:CPUIRQSEL1.EV for details).

ACTIVE0

Reading 0 from this bit implies that interrupt line 0 is not active.
Reading 1 from this bit implies that the interrupt line 0 is active (See
EVENT:CPUIRQSEL0.EV for details).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.16 NVIC_IABR1 Register (Offset = 304h) [reset = 0h]
NVIC_IABR1 is shown in Figure 2-86 and described in Table 2-112.
Return to Summary Table.
Irq 32 to 63 Active Bit
This register is used to determine which interrupts are active. Each flag in the register corresponds to one
interrupt.
Figure 2-86. NVIC_IABR1 Register
31

1
ACTIVE33
R-0h

0
ACTIVE32
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 2-112. NVIC_IABR1 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ACTIVE33

Reading 0 from this bit implies that interrupt line 33 is not active.
Reading 1 from this bit implies that the interrupt line 33 is active (See
EVENT:CPUIRQSEL33.EV for details).

ACTIVE32

Reading 0 from this bit implies that interrupt line 32 is not active.
Reading 1 from this bit implies that the interrupt line 32 is active (See
EVENT:CPUIRQSEL32.EV for details).

31-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

153

Cortex-M3 Processor Registers

www.ti.com

2.7.4.17 NVIC_IPR0 Register (Offset = 400h) [reset = 0h]
NVIC_IPR0 is shown in Figure 2-87 and described in Table 2-113.
Return to Summary Table.
Irq 0 to 3 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
Figure 2-87. NVIC_IPR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_3
PRI_2
PRI_1
R/W-0h
R/W-0h
R/W-0h

4 3 2
PRI_0
R/W-0h

Table 2-113. NVIC_IPR0 Register Field Descriptions

154

Bit

Field

Type

Reset

Description

31-24

PRI_3

R/W

Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details).

23-16

PRI_2

R/W

Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details).

15-8

PRI_1

R/W

Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details).

7-0

PRI_0

R/W

Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.18 NVIC_IPR1 Register (Offset = 404h) [reset = 0h]
NVIC_IPR1 is shown in Figure 2-88 and described in Table 2-114.
Return to Summary Table.
Irq 4 to 7 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
Figure 2-88. NVIC_IPR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_7
PRI_6
PRI_5
R/W-0h
R/W-0h
R/W-0h

4 3 2
PRI_4
R/W-0h

Table 2-114. NVIC_IPR1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

PRI_7

R/W

Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details).

23-16

PRI_6

R/W

Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details).

15-8

PRI_5

R/W

Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details).

7-0

PRI_4

R/W

Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

155

Cortex-M3 Processor Registers

www.ti.com

2.7.4.19 NVIC_IPR2 Register (Offset = 408h) [reset = 0h]
NVIC_IPR2 is shown in Figure 2-89 and described in Table 2-115.
Return to Summary Table.
Irq 8 to 11 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
Figure 2-89. NVIC_IPR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_11
PRI_10
PRI_9
R/W-0h
R/W-0h
R/W-0h

4 3 2
PRI_8
R/W-0h

Table 2-115. NVIC_IPR2 Register Field Descriptions
Bit

156

Field

Type

Reset

Description

31-24

PRI_11

R/W

Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details).

23-16

PRI_10

R/W

Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details).

15-8

PRI_9

R/W

Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details).

7-0

PRI_8

R/W

Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.20 NVIC_IPR3 Register (Offset = 40Ch) [reset = 0h]
NVIC_IPR3 is shown in Figure 2-90 and described in Table 2-116.
Return to Summary Table.
Irq 12 to 15 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
Figure 2-90. NVIC_IPR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_15
PRI_14
PRI_13
R/W-0h
R/W-0h
R/W-0h

4 3 2
PRI_12
R/W-0h

Table 2-116. NVIC_IPR3 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

PRI_15

R/W

Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details).

23-16

PRI_14

R/W

Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details).

15-8

PRI_13

R/W

Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details).

7-0

PRI_12

R/W

Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

157

Cortex-M3 Processor Registers

www.ti.com

2.7.4.21 NVIC_IPR4 Register (Offset = 410h) [reset = 0h]
NVIC_IPR4 is shown in Figure 2-91 and described in Table 2-117.
Return to Summary Table.
Irq 16 to 19 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
Figure 2-91. NVIC_IPR4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_19
PRI_18
PRI_17
R/W-0h
R/W-0h
R/W-0h

4 3 2
PRI_16
R/W-0h

Table 2-117. NVIC_IPR4 Register Field Descriptions
Bit

158

Field

Type

Reset

Description

31-24

PRI_19

R/W

Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details).

23-16

PRI_18

R/W

Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details).

15-8

PRI_17

R/W

Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details).

7-0

PRI_16

R/W

Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.22 NVIC_IPR5 Register (Offset = 414h) [reset = 0h]
NVIC_IPR5 is shown in Figure 2-92 and described in Table 2-118.
Return to Summary Table.
Irq 20 to 23 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
Figure 2-92. NVIC_IPR5 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_23
PRI_22
PRI_21
R/W-0h
R/W-0h
R/W-0h

4 3 2
PRI_20
R/W-0h

Table 2-118. NVIC_IPR5 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

PRI_23

R/W

Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details).

23-16

PRI_22

R/W

Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details).

15-8

PRI_21

R/W

Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details).

7-0

PRI_20

R/W

Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

159

Cortex-M3 Processor Registers

www.ti.com

2.7.4.23 NVIC_IPR6 Register (Offset = 418h) [reset = 0h]
NVIC_IPR6 is shown in Figure 2-93 and described in Table 2-119.
Return to Summary Table.
Irq 24 to 27 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
Figure 2-93. NVIC_IPR6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_27
PRI_26
PRI_25
R/W-0h
R/W-0h
R/W-0h

4 3 2
PRI_24
R/W-0h

Table 2-119. NVIC_IPR6 Register Field Descriptions
Bit

160

Field

Type

Reset

Description

31-24

PRI_27

R/W

Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details).

23-16

PRI_26

R/W

Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details).

15-8

PRI_25

R/W

Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details).

7-0

PRI_24

R/W

Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.24 NVIC_IPR7 Register (Offset = 41Ch) [reset = 0h]
NVIC_IPR7 is shown in Figure 2-94 and described in Table 2-120.
Return to Summary Table.
Irq 28 to 31 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
Figure 2-94. NVIC_IPR7 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_31
PRI_30
PRI_29
R/W-0h
R/W-0h
R/W-0h

4 3 2
PRI_28
R/W-0h

Table 2-120. NVIC_IPR7 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

PRI_31

R/W

Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details).

23-16

PRI_30

R/W

Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details).

15-8

PRI_29

R/W

Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details).

7-0

PRI_28

R/W

Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

161

Cortex-M3 Processor Registers

www.ti.com

2.7.4.25 NVIC_IPR8 Register (Offset = 420h) [reset = 0h]
NVIC_IPR8 is shown in Figure 2-95 and described in Table 2-121.
Return to Summary Table.
Irq 32 to 35 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
Figure 2-95. NVIC_IPR8 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
PRI_33
R/W-0h
R/W-0h

4 3 2
PRI_32
R/W-0h

Table 2-121. NVIC_IPR8 Register Field Descriptions
Bit

162

Field

Type

Reset

Description

31-16

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-8

PRI_33

R/W

Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details).

7-0

PRI_32

R/W

Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.26 CPUID Register (Offset = D00h) [reset = 412FC231h]
CPUID is shown in Figure 2-96 and described in Table 2-122.
Return to Summary Table.
CPUID Base
This register determines the ID number of the processor core, the version number of the processor core
and the implementation details of the processor core.
Figure 2-96. CPUID Register
31

28
27
IMPLEMENTER
R-41h
12

22
21
VARIANT
R-2h

18
17
CONSTANT
R-Fh

10
9
PARTNO
R-C23h

2
1
REVISION
R-1h

Table 2-122. CPUID Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

IMPLEMENTER

41h

Implementor code.

23-20

VARIANT

Implementation defined variant number.

19-16

CONSTANT

Reads as 0xF

15-4

PARTNO

C23h

Number of processor within family.

3-0

REVISION

Implementation defined revision number.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

163

Cortex-M3 Processor Registers

www.ti.com

2.7.4.27 ICSR Register (Offset = D04h) [reset = X]
ICSR is shown in Figure 2-97 and described in Table 2-123.
Return to Summary Table.
Interrupt Control State
This register is used to set a pending Non-Maskable Interrupt (NMI), set or clear a pending SVC, set or
clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority
pended exception, and check the vector number of the active exception.
Figure 2-97. ICSR Register
31
NMIPENDSET
R/W-0h

23
ISRPREEMPT
R-0h

22
ISRPENDING
R-0h

28
PENDSVSET
R/W-0h

27
PENDSVCLR
W-X

26
PENDSTSET
R/W-0h

11
RETTOBASE
R-0h

RESERVED
R/W-0h

25
PENDSTCLR
W-X

17
16
VECTPENDING
R-0h

RESERVED
R-0h

14
13
VECTPENDING
R-0h

24
RESERVED
R-0h

8
VECTACTIVE
R-0h

RESERVED
R-0h

VECTACTIVE
R-0h

Table 2-123. ICSR Register Field Descriptions
Bit

Field

Type

Reset

Description

NMIPENDSET

R/W

Set pending NMI bit. Setting this bit pends and activates an NMI.
Because NMI is the highest-priority interrupt, it takes effect as soon
as it registers.
0: No action
1: Set pending NMI

30-29

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

PENDSVSET

R/W

Set pending pendSV bit.
0: No action
1: Set pending PendSV

PENDSVCLR

Clear pending pendSV bit
0: No action
1: Clear pending pendSV

PENDSTSET

R/W

Set a pending SysTick bit.
0: No action
1: Set pending SysTick

PENDSTCLR

Clear pending SysTick bit
0: No action
1: Clear pending SysTick

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ISRPREEMPT

This field can only be used at debug time. It indicates that a pending
interrupt is to be taken in the next running cycle. If
DHCSR.C_MASKINTS= 0, the interrupt is serviced.
0: A pending exception is not serviced.
1: A pending exception is serviced on exit from the debug halt state

ISRPENDING

Interrupt pending flag. Excludes NMI and faults.
0x0: Interrupt not pending
0x1: Interrupt pending

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

21-18

164

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-123. ICSR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

VECTPENDING

Pending ISR number field. This field contains the interrupt number of
the highest priority pending ISR.

RETTOBASE

Indicates whether there are preempted active exceptions:
0: There are preempted active exceptions to execute
1: There are no active exceptions, or the currently-executing
exception is the only active exception.

10-9

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

8-0

VECTACTIVE

Active ISR number field. Reset clears this field.

17-12

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

165

Cortex-M3 Processor Registers

www.ti.com

2.7.4.28 VTOR Register (Offset = D08h) [reset = 0h]
VTOR is shown in Figure 2-98 and described in Table 2-124.
Return to Summary Table.
Vector Table Offset
This register is used to relocated the vector table base address. The vector table base offset determines
the offset from the bottom of the memory map. The two most significant bits and the seven least
significant bits of the vector table base offset must be 0. The portion of vector table base offset that is
allowed to change is TBLOFF.
Figure 2-98. VTOR Register
31

3
RESERVED
R/W-0h

RESERVED
R/W-0h
23

TBLOFF
R/W-0h
22

20
TBLOFF
R/W-0h

12
TBLOFF
R/W-0h

7
TBLOFF
R/W-0h

Table 2-124. VTOR Register Field Descriptions
Bit

166

Field

Type

Reset

Description

31-30

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

29-7

TBLOFF

R/W

Bits 29 down to 7 of the vector table base offset.

6-0

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.29 AIRCR Register (Offset = D0Ch) [reset = FA050000h]
AIRCR is shown in Figure 2-99 and described in Table 2-125.
Return to Summary Table.
Application Interrupt/Reset Control
This register is used to determine data endianness, clear all active state information for debug or to
recover from a hard failure, execute a system reset, alter the priority grouping position (binary point).
Figure 2-99. AIRCR Register
31

9
PRIGROUP
R/W-0h

2
SYSRESETRE
Q
W-0h

1
VECTCLRACTI
VE
W-0h

0
VECTRESET

VECTKEY
R/W-FA05h
23

20
VECTKEY
R/W-FA05h

15
ENDIANESS
R-0h

13
RESERVED
R-0h
5
RESERVED
R/W-0h

W-0h

Table 2-125. AIRCR Register Field Descriptions
Bit

Field

Type

Reset

Description

VECTKEY

R/W

FA05h

Register key. Writing to this register (AIRCR) requires 0x05FA in
VECTKEY. Otherwise the write value is ignored. Read always
returns 0xFA05.

ENDIANESS

Data endianness bit
0h = Little endian
1h = Big endian

14-11

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

10-8

PRIGROUP

R/W

Interrupt priority grouping field. This field is a binary point position
indicator for creating subpriorities for exceptions that share the same
pre-emption level. It divides the PRI_n field in the Interrupt Priority
Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a preemption level and a subpriority level. The binary point is a left-of
value. This means that the PRIGROUP value represents a point
starting at the left of the Least Significant Bit (LSB). The lowest value
might not be 0 depending on the number of bits allocated for
priorities, and implementation choices.

7-3

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SYSRESETREQ

Requests a warm reset. Setting this bit does not prevent Halting
Debug from running.

VECTCLRACTIVE

Clears all active state information for active NMI, fault, and
interrupts. It is the responsibility of the application to reinitialize the
stack. This bit is for returning to a known state during debug. The bit
self-clears. IPSR is not cleared by this operation. So, if used by an
application, it must only be used at the base level of activation, or
within a system handler whose active bit can be set.

VECTRESET

System Reset bit. Resets the system, with the exception of debug
components. This bit is reserved for debug use and can be written to
1 only when the core is halted. The bit self-clears. Writing this bit to
1 while core is not halted may result in unpredictable behavior.

31-16

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

167

Cortex-M3 Processor Registers

www.ti.com

2.7.4.30 SCR Register (Offset = D10h) [reset = 0h]
SCR is shown in Figure 2-100 and described in Table 2-126.
Return to Summary Table.
System Control
This register is used for power-management functions, i.e., signaling to the system when the processor
can enter a low power state, controlling how the processor enters and exits low power states.
Figure 2-100. SCR Register
31

3
RESERVED
R/W-0h

2
SLEEPDEEP
R/W-0h

1
SLEEPONEXIT
R/W-0h

0
RESERVED
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

6
RESERVED
R/W-0h

4
SEVONPEND
R/W-0h

Table 2-126. SCR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SEVONPEND

R/W

Send Event on Pending bit:
0: Only enabled interrupts or events can wakeup the processor,
disabled interrupts are excluded
1: Enabled events and all interrupts, including disabled interrupts,
can wakeup the processor.
When an event or interrupt enters pending state, the event signal
wakes up the processor from WFE. If
the processor is not waiting for an event, the event is registered and
affects the next WFE.
The processor also wakes up on execution of an SEV instruction.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SLEEPDEEP

R/W

Controls whether the processor uses sleep or deep sleep as its low
power mode
0h = Sleep
1h = Deep sleep

SLEEPONEXIT

R/W

Sleep on exit when returning from Handler mode to Thread mode.
Enables interrupt driven applications to avoid returning to empty
main application.
0: Do not sleep when returning to thread mode
1: Sleep on ISR exit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-5

168

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.31 CCR Register (Offset = D14h) [reset = 200h]
CCR is shown in Figure 2-101 and described in Table 2-127.
Return to Summary Table.
Configuration Control
This register is used to enable NMI, HardFault and FAULTMASK to ignore bus fault, trap divide by zero
and unaligned accesses, enable user access to the Software Trigger Interrupt Register (STIR), control
entry to Thread Mode.
Figure 2-101. CCR Register
31

9
STKALIGN
R/W-1h

8
BFHFNMIGN
R/W-0h

4
DIV_0_TRP

3
UNALIGN_TRP

2
RESERVED

R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

13
RESERVED
R/W-0h

6
RESERVED

R/W-0h

1
0
USERSETMPE NONBASETHR
ND
EDENA
R/W-0h
R/W-0h

Table 2-127. CCR Register Field Descriptions
Field

Type

Reset

Description

31-10

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STKALIGN

R/W

Stack alignment bit.
0: Only 4-byte alignment is guaranteed for the SP used prior to the
exception on exception entry.
1: On exception entry, the SP used prior to the exception is adjusted
to be 8-byte aligned and the context to restore it is saved. The SP is
restored on the associated exception return.

BFHFNMIGN

R/W

Enables handlers with priority -1 or -2 to ignore data BusFaults
caused by load and store instructions. This applies to the HardFault,
NMI, and FAULTMASK escalated handlers:
0: Data BusFaults caused by load and store instructions cause a
lock-up
1: Data BusFaults caused by load and store instructions are ignored.
Set this bit to 1 only when the handler and its data are in absolutely
safe memory. The normal use
of this bit is to probe system devices and bridges to detect problems.

7-5

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIV_0_TRP

R/W

Enables faulting or halting when the processor executes an SDIV or
UDIV instruction with a divisor of 0:
0: Do not trap divide by 0. In this mode, a divide by zero returns a
quotient of 0.
1: Trap divide by 0. The relevant Usage Fault Status Register bit is
CFSR.DIVBYZERO.

UNALIGN_TRP

R/W

Enables unaligned access traps:
0: Do not trap unaligned halfword and word accesses
1: Trap unaligned halfword and word accesses. The relevant Usage
Fault Status Register bit is CFSR.UNALIGNED.
If this bit is set to 1, an unaligned access generates a UsageFault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of the value in UNALIGN_TRP.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

169

Cortex-M3 Processor Registers

www.ti.com

Table 2-127. CCR Register Field Descriptions (continued)
Bit

170

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

USERSETMPEND

R/W

Enables unprivileged software access to STIR:
0: User code is not allowed to write to the Software Trigger Interrupt
register (STIR).
1: User code can write the Software Trigger Interrupt register (STIR)
to trigger (pend) a Main exception, which is associated with the Main
stack pointer.

NONBASETHREDENA

R/W

Indicates how the processor enters Thread mode:
0: Processor can enter Thread mode only when no exception is
active.
1: Processor can enter Thread mode from any level using the
appropriate return value (EXC_RETURN).
Exception returns occur when one of the following instructions loads
a value of 0xFXXXXXXX into the PC while in Handler mode:
- POP/LDM which includes loading the PC.
- LDR with PC as a destination.
- BX with any register.
The value written to the PC is intercepted and is referred to as the
EXC_RETURN value.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.32 SHPR1 Register (Offset = D18h) [reset = 0h]
SHPR1 is shown in Figure 2-102 and described in Table 2-128.
Return to Summary Table.
System Handlers 4-7 Priority
This register is used to prioritize the following system handlers: Memory manage, Bus fault, and Usage
fault. System Handlers are a special class of exception handler that can have their priority set to any of
the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always
treated as a Hard Fault.
Figure 2-102. SHPR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
PRI_6
PRI_5
R/W-0h
R/W-0h
R/W-0h

4 3 2
PRI_4
R/W-0h

Table 2-128. SHPR1 Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-16

PRI_6

R/W

Priority of system handler 6. UsageFault

15-8

PRI_5

R/W

Priority of system handler 5: BusFault

7-0

PRI_4

R/W

Priority of system handler 4: MemManage

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

171

Cortex-M3 Processor Registers

www.ti.com

2.7.4.33 SHPR2 Register (Offset = D1Ch) [reset = 0h]
SHPR2 is shown in Figure 2-103 and described in Table 2-129.
Return to Summary Table.
System Handlers 8-11 Priority
This register is used to prioritize the SVC handler. System Handlers are a special class of exception
handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off
(disabled). When disabled, the fault is always treated as a Hard Fault.
Figure 2-103. SHPR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_11
RESERVED
R/W-0h
R/W-0h

Table 2-129. SHPR2 Register Field Descriptions
Bit

172

Field

Type

Reset

Description

31-24

PRI_11

R/W

Priority of system handler 11. SVCall

23-0

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.34 SHPR3 Register (Offset = D20h) [reset = 0h]
SHPR3 is shown in Figure 2-104 and described in Table 2-130.
Return to Summary Table.
System Handlers 12-15 Priority
This register is used to prioritize the following system handlers: SysTick, PendSV and Debug Monitor.
System Handlers are a special class of exception handler that can have their priority set to any of the
priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always
treated as a Hard Fault.
Figure 2-104. SHPR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_15
PRI_14
RESERVED
R/W-0h
R/W-0h
R/W-0h

4 3 2
PRI_12
R/W-0h

Table 2-130. SHPR3 Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

PRI_15

R/W

Priority of system handler 15. SysTick exception

23-16

PRI_14

R/W

Priority of system handler 14. Pend SV

15-8

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

PRI_12

R/W

Priority of system handler 12. Debug Monitor

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

173

Cortex-M3 Processor Registers

www.ti.com

2.7.4.35 SHCSR Register (Offset = D24h) [reset = 0h]
SHCSR is shown in Figure 2-105 and described in Table 2-131.
Return to Summary Table.
System Handler Control and State
This register is used to enable or disable the system handlers, determine the pending status of bus fault,
mem manage fault, and SVC, determine the active status of the system handlers. If a fault condition
occurs while its fault handler is disabled, the fault escalates to a Hard Fault.
Figure 2-105. SHCSR Register
31

18
USGFAULTEN
A
R/W-0h

17
BUSFAULTEN
A
R/W-0h

16
MEMFAULTEN
A
R/W-0h

RESERVED
R/W-0h
23

21
RESERVED
R/W-0h

15
SVCALLPEND
ED
R-0h

14
BUSFAULTPE
NDED
R-0h

13
MEMFAULTPE
NDED
R-0h

12
USGFAULTPE
NDED
R-0h

11
SYSTICKACT

10
PENDSVACT

9
RESERVED

8
MONITORACT

R-0h

7
SVCALLACT

5
RESERVED

3
USGFAULTAC
T
R-0h

2
RESERVED

1
BUSFAULTAC
T
R-0h

0
MEMFAULTAC
T
R-0h

R-0h

Table 2-131. SHCSR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

USGFAULTENA

R/W

Usage fault system handler enable
0h = Exception disabled
1h = Exception enabled

BUSFAULTENA

R/W

Bus fault system handler enable
0h = Exception disabled
1h = Exception enabled

MEMFAULTENA

R/W

MemManage fault system handler enable
0h = Exception disabled
1h = Exception enabled

SVCALLPENDED

SVCall pending
0h = Exception is not active
1h = Exception is pending.

BUSFAULTPENDED

BusFault pending
0h = Exception is not active
1h = Exception is pending.

MEMFAULTPENDED

MemManage exception pending
0h = Exception is not active
1h = Exception is pending.

USGFAULTPENDED

Usage fault pending
0h = Exception is not active
1h = Exception is pending.

31-19

174

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-131. SHCSR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

SYSTICKACT

SysTick active flag.
0x0: Not active
0x1: Active
0h = Exception is not active
1h = Exception is active

PENDSVACT

PendSV active
0x0: Not active
0x1: Active

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MONITORACT

Debug monitor active
0h = Exception is not active
1h = Exception is active

SVCALLACT

SVCall active
0h = Exception is not active
1h = Exception is active

6-4

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

USGFAULTACT

UsageFault exception active
0h = Exception is not active
1h = Exception is active

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BUSFAULTACT

BusFault exception active
0h = Exception is not active
1h = Exception is active

MEMFAULTACT

MemManage exception active
0h = Exception is not active
1h = Exception is active

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

175

Cortex-M3 Processor Registers

www.ti.com

2.7.4.36 CFSR Register (Offset = D28h) [reset = 0h]
CFSR is shown in Figure 2-106 and described in Table 2-132.
Return to Summary Table.
Configurable Fault Status
This register is used to obtain information about local faults. These registers include three subsections:
The first byte is Memory Manage Fault Status Register (MMFSR). The second byte is Bus Fault Status
Register (BFSR). The higher half-word is Usage Fault Status Register (UFSR). The flags in these registers
indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register
are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit.
The CFSR is byte accessible. CFSR or its subregisters can be accessed as follows:
The following accesses are possible to the CFSR register:
- access the complete register with a word access to 0xE000ED28.
- access the MMFSR with a byte access to 0xE000ED28
- access the MMFSR and BFSR with a halfword access to 0xE000ED28
- access the BFSR with a byte access to 0xE000ED29
- access the UFSR with a halfword access to 0xE000ED2A.
Figure 2-106. CFSR Register
31

25
DIVBYZERO
R/W-0h

24
UNALIGNED
R/W-0h

19
NOCP
R/W-0h

18
INVPC
R/W-0h

17
INVSTATE
R/W-0h

16
UNDEFINSTR
R/W-0h

12
STKERR
R/W-0h

11
UNSTKERR
R/W-0h

10
IMPRECISERR
R/W-0h

9
PRECISERR
R/W-0h

8
IBUSERR
R/W-0h

4
MSTKERR
R/W-0h

3
MUNSTKERR
R/W-0h

2
RESERVED
R/W-0h

1
DACCVIOL
R/W-0h

0
IACCVIOL
R/W-0h

RESERVED
R/W-0h
23

22
RESERVED
R/W-0h

15
BFARVALID
R/W-0h

7
MMARVALID
R/W-0h

RESERVED
R/W-0h
RESERVED
R/W-0h

Table 2-132. CFSR Register Field Descriptions
Bit

176

Field

Type

Reset

Description

31-26

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIVBYZERO

R/W

When CCR.DIV_0_TRP (see Configuration Control Register on page
8-26) is enabled and an SDIV or UDIV instruction is used with a
divisor of 0, this fault occurs The instruction is executed and the
return PC points to it. If CCR.DIV_0_TRP is not set, then the divide
returns a quotient of 0.

UNALIGNED

R/W

When CCR.UNALIGN_TRP is enabled, and there is an attempt to
make an unaligned memory access, then this fault occurs. Unaligned
LDM/STM/LDRD/STRD instructions always fault irrespective of the
setting of CCR.UNALIGN_TRP.

23-20

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

NOCP

R/W

Attempt to use a coprocessor instruction. The processor does not
support coprocessor instructions.

INVPC

R/W

Attempt to load EXC_RETURN into PC illegally. Invalid instruction,
invalid context, invalid value. The return PC points to the instruction
that tried to set the PC.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-132. CFSR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

INVSTATE

R/W

Indicates an attempt to execute in an invalid EPSR state (e.g. after a
BX type instruction has changed state). This includes state change
after entry to or return from exception, as well as from inter-working
instructions. Return PC points to faulting instruction, with the invalid
state.

UNDEFINSTR

R/W

This bit is set when the processor attempts to execute an undefined
instruction. This is an instruction that the processor cannot decode.
The return PC points to the undefined instruction.

BFARVALID

R/W

This bit is set if the Bus Fault Address Register (BFAR) contains a
valid address. This is true after a bus fault where the address is
known. Other faults can clear this bit, such as a Mem Manage fault
occurring later. If a Bus fault occurs that is escalated to a Hard Fault
because of priority, the Hard Fault handler must clear this bit. This
prevents problems if returning to a stacked active Bus fault handler
whose BFAR value has been overwritten.

14-13

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STKERR

R/W

Stacking from exception has caused one or more bus faults. The SP
is still adjusted and the values in the context area on the stack might
be incorrect. BFAR is not written.

UNSTKERR

R/W

Unstack from exception return has caused one or more bus faults.
This is chained to the handler, so that the original return stack is still
present. SP is not adjusted from failing return and new save is not
performed. BFAR is not written.

IMPRECISERR

R/W

Imprecise data bus error. It is a BusFault, but the Return PC is not
related to the causing instruction. This is not a synchronous fault.
So, if detected when the priority of the current activation is higher
than the Bus Fault, it only pends. Bus fault activates when returning
to a lower priority activation. If a precise fault occurs before returning
to a lower priority exception, the handler detects both
IMPRECISERR set and one of the precise fault status bits set at the
same time. BFAR is not written.

PRECISERR

R/W

Precise data bus error return.

IBUSERR

R/W

Instruction bus error flag. This flag is set by a prefetch error. The
fault stops on the instruction, so if the error occurs under a branch
shadow, no fault occurs. BFAR is not written.

MMARVALID

R/W

Memory Manage Address Register (MMFAR) address valid flag. A
later-arriving fault, such as a bus fault, can clear a memory manage
fault.. If a MemManage fault occurs that is escalated to a Hard Fault
because of priority, the Hard Fault handler must clear this bit. This
prevents problems on return to a stacked active MemManage
handler whose MMFAR value has been overwritten.

6-5

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MSTKERR

R/W

Stacking from exception has caused one or more access violations.
The SP is still adjusted and the values in the context area on the
stack might be incorrect. MMFAR is not written.

MUNSTKERR

R/W

Unstack from exception return has caused one or more access
violations. This is chained to the handler, so that the original return
stack is still present. SP is not adjusted from failing return and new
save is not performed. MMFAR is not written.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DACCVIOL

R/W

Data access violation flag. Attempting to load or store at a location
that does not permit the operation sets this flag. The return PC
points to the faulting instruction. This error loads MMFAR with the
address of the attempted access.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

177

Cortex-M3 Processor Registers

www.ti.com

Table 2-132. CFSR Register Field Descriptions (continued)
Bit
0

178

Field

Type

Reset

Description

IACCVIOL

R/W

Instruction access violation flag. Attempting to fetch an instruction
from a location that does not permit execution sets this flag. This
occurs on any access to an XN region, even when the MPU is
disabled or not present. The return PC points to the faulting
instruction. MMFAR is not written.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.37 HFSR Register (Offset = D2Ch) [reset = 0h]
HFSR is shown in Figure 2-107 and described in Table 2-133.
Return to Summary Table.
Hard Fault Status
This register is used to obtain information about events that activate the Hard Fault handler. This register
is a write-clear register. This means that writing a 1 to a bit clears that bit.
Figure 2-107. HFSR Register
31
DEBUGEVT
R/W1C-0h

30
FORCED
R/W1C-0h

1
VECTTBL
R/W1C-0h

0
RESERVED
R/W-0h

RESERVED
R/W-0h
20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 2-133. HFSR Register Field Descriptions
Bit

Field

Type

Reset

Description

DEBUGEVT

R/W1C

This bit is set if there is a fault related to debug. This is only possible
when halting debug is not enabled. For monitor enabled debug, it
only happens for BKPT when the current priority is higher than the
monitor. When both halting and monitor debug are disabled, it only
happens for debug events that are not ignored (minimally, BKPT).
The Debug Fault Status Register is updated.

FORCED

R/W1C

Hard Fault activated because a Configurable Fault was received and
cannot activate because of priority or because the Configurable Fault
is disabled. The Hard Fault handler then has to read the other fault
status registers to determine cause.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

VECTTBL

R/W1C

This bit is set if there is a fault because of vector table read on
exception processing (Bus Fault). This case is always a Hard Fault.
The return PC points to the pre-empted instruction.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

29-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

179

Cortex-M3 Processor Registers

www.ti.com

2.7.4.38 DFSR Register (Offset = D30h) [reset = 0h]
DFSR is shown in Figure 2-108 and described in Table 2-134.
Return to Summary Table.
Debug Fault Status
This register is used to monitor external debug requests, vector catches, data watchpoint match, BKPT
instruction execution, halt requests. Multiple flags in the Debug Fault Status Register can be set when
multiple fault conditions occur. The register is read/write clear. This means that it can be read normally.
Writing a 1 to a bit clears that bit. Note that these bits are not set unless the event is caught. This means
that it causes a stop of some sort. If halting debug is enabled, these events stop the processor into debug.
If debug is disabled and the debug monitor is enabled, then this becomes a debug monitor handler call, if
priority permits. If debug and the monitor are both disabled, some of these events are Hard Faults, and
some are ignored.
Figure 2-108. DFSR Register
31

3
VCATCH
R/W-0h

2
DWTTRAP
R/W-0h

1
BKPT
R/W-0h

0
HALTED
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

6
RESERVED
R/W-0h

4
EXTERNAL
R/W-0h

Table 2-134. DFSR Register Field Descriptions
Bit

180

Field

Type

Reset

Description

31-5

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EXTERNAL

R/W

External debug request flag. The processor stops on next instruction
boundary.
0x0: External debug request signal not asserted
0x1: External debug request signal asserted

VCATCH

R/W

Vector catch flag. When this flag is set, a flag in one of the local fault
status registers is also set to indicate the type of fault.
0x0: No vector catch occurred
0x1: Vector catch occurred

DWTTRAP

R/W

Data Watchpoint and Trace (DWT) flag. The processor stops at the
current instruction or at the next instruction.
0x0: No DWT match
0x1: DWT match

BKPT

R/W

BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch
code, and also by normal code. Return PC points to breakpoint
containing instruction.
0x0: No BKPT instruction execution
0x1: BKPT instruction execution

HALTED

R/W

Halt request flag. The processor is halted on the next instruction.
0x0: No halt request
0x1: Halt requested by NVIC, including step

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.39 MMFAR Register (Offset = D34h) [reset = X]
MMFAR is shown in Figure 2-109 and described in Table 2-135.
Return to Summary Table.
Mem Manage Fault Address
This register is used to read the address of the location that caused a Memory Manage Fault.
Figure 2-109. MMFAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDRESS
R/W-X

Table 2-135. MMFAR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ADDRESS

R/W

Mem Manage fault address field.
This field is the data address of a faulted load or store attempt.
When an unaligned access faults, the address is the actual address
that faulted. Because an access can be split into multiple parts, each
aligned, this address can be any offset in the range of the requested
size. Flags CFSR.IACCVIOL, CFSR.DACCVIOL
,CFSR.MUNSTKERR and CFSR.MSTKERR in combination with
CFSR.MMARVALIDindicate the cause of the fault.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

181

Cortex-M3 Processor Registers

www.ti.com

2.7.4.40 BFAR Register (Offset = D38h) [reset = X]
BFAR is shown in Figure 2-110 and described in Table 2-136.
Return to Summary Table.
Bus Fault Address
This register is used to read the address of the location that generated a Bus Fault.
Figure 2-110. BFAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDRESS
R/W-X

Table 2-136. BFAR Register Field Descriptions
Bit
31-0

182

Field

Type

Reset

Description

ADDRESS

R/W

Bus fault address field. This field is the data address of a faulted
load or store attempt. When an unaligned access faults, the address
is the address requested by the instruction, even if that is not the
address that faulted.
Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR,
CFSR.UNSTKERR and CFSR.STKERR in combination with
CFSR.BFARVALID indicate the cause of the fault.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.41 AFSR Register (Offset = D3Ch) [reset = 0h]
AFSR is shown in Figure 2-111 and described in Table 2-137.
Return to Summary Table.
Auxiliary Fault Status
This register is used to determine additional system fault information to software. Single-cycle high level
on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding
bit. Auxiliary fault inputs to the CPU are tied to 0.
Figure 2-111. AFSR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IMPDEF
R/W-0h

Table 2-137. AFSR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

IMPDEF

R/W

Implementation defined. The bits map directly onto the signal
assignment to the auxiliary fault inputs. Tied to 0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

183

Cortex-M3 Processor Registers

www.ti.com

2.7.4.42 ID_PFR0 Register (Offset = D40h) [reset = 30h]
ID_PFR0 is shown in Figure 2-112 and described in Table 2-138.
Return to Summary Table.
Processor Feature 0
Figure 2-112. ID_PFR0 Register
31

12
11
RESERVED
R-0h

24
23
RESERVED
R-0h
8

6
5
STATE1
R-3h

2
1
STATE0
R-0h

Table 2-138. ID_PFR0 Register Field Descriptions
Bit

184

Field

Type

Reset

Description

31-8

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-4

STATE1

State1 (T-bit == 1)
0x0: N/A
0x1: N/A
0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit
Buncond/BL but no other 32-bit basic instructions (Note non-basic
32-bit instructions can be added using the appropriate instruction
attribute, but other 32-bit basic instructions cannot.)
0x3: Thumb-2 encoding with all Thumb-2 basic instructions

3-0

STATE0

State0 (T-bit == 0)
0x0: No ARM encoding
0x1: N/A

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.43 ID_PFR1 Register (Offset = D44h) [reset = 200h]
ID_PFR1 is shown in Figure 2-113 and described in Table 2-139.
Return to Summary Table.
Processor Feature 1
Figure 2-113. ID_PFR1 Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

11
10
9
8
MICROCONTROLLER_PROGRAMMERS_MODEL
R-2h

RESERVED
R-0h
7

RESERVED
R-0h

Table 2-139. ID_PFR1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-12

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-8

MICROCONTROLLER_P
ROGRAMMERS_MODEL

Microcontroller programmer's model
0x0: Not supported
0x2: Two-stack support

7-0

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

185

Cortex-M3 Processor Registers

www.ti.com

2.7.4.44 ID_DFR0 Register (Offset = D48h) [reset = 00100000h]
ID_DFR0 is shown in Figure 2-114 and described in Table 2-140.
Return to Summary Table.
Debug Feature 0
This register provides a high level view of the debug system. Further details are provided in the debug
infrastructure itself.
Figure 2-114. ID_DFR0 Register
31

RESERVED
R-0h
23

22
21
MICROCONTROLLER_DEBUG_MODEL
R-1h

RESERVED
R-0h

RESERVED
R-0h
7

4
RESERVED
R-0h

Table 2-140. ID_DFR0 Register Field Descriptions
Bit

186

Field

Type

Reset

Description

31-24

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-20

MICROCONTROLLER_D
EBUG_MODEL

Microcontroller Debug Model - memory mapped
0x0: Not supported
0x1: Microcontroller debug v1 (ITMv1 and DWTv1)

19-0

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.45 ID_AFR0 Register (Offset = D4Ch) [reset = 0h]
ID_AFR0 is shown in Figure 2-115 and described in Table 2-141.
Return to Summary Table.
Auxiliary Feature 0
This register provides some freedom for implementation defined features to be registered. Not used in
Cortex-M.
Figure 2-115. ID_AFR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

Table 2-141. ID_AFR0 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

187

Cortex-M3 Processor Registers

www.ti.com

2.7.4.46 ID_MMFR0 Register (Offset = D50h) [reset = 00100030h]
ID_MMFR0 is shown in Figure 2-116 and described in Table 2-142.
Return to Summary Table.
Memory Model Feature 0
General information on the memory model and memory management support.
Figure 2-116. ID_MMFR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-00100030h

Table 2-142. ID_MMFR0 Register Field Descriptions
Bit
31-0

188

Field

Type

Reset

Description

RESERVED

00100030h

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.47 ID_MMFR1 Register (Offset = D54h) [reset = 0h]
ID_MMFR1 is shown in Figure 2-117 and described in Table 2-143.
Return to Summary Table.
Memory Model Feature 1
General information on the memory model and memory management support.
Figure 2-117. ID_MMFR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

Table 2-143. ID_MMFR1 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

189

Cortex-M3 Processor Registers

www.ti.com

2.7.4.48 ID_MMFR2 Register (Offset = D58h) [reset = 01000000h]
ID_MMFR2 is shown in Figure 2-118 and described in Table 2-144.
Return to Summary Table.
Memory Model Feature 2
General information on the memory model and memory management support.
Figure 2-118. ID_MMFR2 Register
31

28
RESERVED

24
WAIT_FOR_IN
TERRUPT_ST
ALLING
R-1h

R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 2-144. ID_MMFR2 Register Field Descriptions
Bit
31-25
24

23-0

190

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

WAIT_FOR_INTERRUPT
_STALLING

wait for interrupt stalling
0x0: Not supported
0x1: Wait for interrupt supported

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.49 ID_MMFR3 Register (Offset = D5Ch) [reset = 0h]
ID_MMFR3 is shown in Figure 2-119 and described in Table 2-145.
Return to Summary Table.
Memory Model Feature 3
General information on the memory model and memory management support.
Figure 2-119. ID_MMFR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

Table 2-145. ID_MMFR3 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

191

Cortex-M3 Processor Registers

www.ti.com

2.7.4.50 ID_ISAR0 Register (Offset = D60h) [reset = 01101110h]
ID_ISAR0 is shown in Figure 2-120 and described in Table 2-146.
Return to Summary Table.
ISA Feature 0
Information on the instruction set attributes register
Figure 2-120. ID_ISAR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-01101110h

Table 2-146. ID_ISAR0 Register Field Descriptions
Bit
31-0

192

Field

Type

Reset

Description

RESERVED

01101110h

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.51 ID_ISAR1 Register (Offset = D64h) [reset = 02111000h]
ID_ISAR1 is shown in Figure 2-121 and described in Table 2-147.
Return to Summary Table.
ISA Feature 1
Information on the instruction set attributes register
Figure 2-121. ID_ISAR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-02111000h

Table 2-147. ID_ISAR1 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RESERVED

02111000h

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

193

Cortex-M3 Processor Registers

www.ti.com

2.7.4.52 ID_ISAR2 Register (Offset = D68h) [reset = 21112231h]
ID_ISAR2 is shown in Figure 2-122 and described in Table 2-148.
Return to Summary Table.
ISA Feature 2
Information on the instruction set attributes register
Figure 2-122. ID_ISAR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-21112231h

Table 2-148. ID_ISAR2 Register Field Descriptions
Bit
31-0

194

Field

Type

Reset

Description

RESERVED

21112231h

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.53 ID_ISAR3 Register (Offset = D6Ch) [reset = 01111110h]
ID_ISAR3 is shown in Figure 2-123 and described in Table 2-149.
Return to Summary Table.
ISA Feature 3
Information on the instruction set attributes register
Figure 2-123. ID_ISAR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-01111110h

Table 2-149. ID_ISAR3 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RESERVED

01111110h

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

195

Cortex-M3 Processor Registers

www.ti.com

2.7.4.54 ID_ISAR4 Register (Offset = D70h) [reset = 01310132h]
ID_ISAR4 is shown in Figure 2-124 and described in Table 2-150.
Return to Summary Table.
ISA Feature 4
Information on the instruction set attributes register
Figure 2-124. ID_ISAR4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-01310132h

Table 2-150. ID_ISAR4 Register Field Descriptions
Bit
31-0

196

Field

Type

Reset

Description

RESERVED

01310132h

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.55 CPACR Register (Offset = D88h) [reset = 0h]
CPACR is shown in Figure 2-125 and described in Table 2-151.
Return to Summary Table.
Coprocessor Access Control
This register specifies the access privileges for coprocessors.
Figure 2-125. CPACR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

Table 2-151. CPACR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

197

Cortex-M3 Processor Registers

www.ti.com

2.7.4.56 DHCSR Register (Offset = DF0h) [reset = X]
DHCSR is shown in Figure 2-126 and described in Table 2-152.
Return to Summary Table.
Debug Halting Control and Status
The purpose of this register is to provide status information about the state of the processor, enable core
debug, halt and step the processor. For writes, 0xA05F must be written to higher half-word of this register,
otherwise the write operation is ignored and no bits are written into the register. If not enabled for Halting
mode, C_DEBUGEN = 1, all other fields are disabled. This register is not reset on a core reset. It is reset
by a power-on reset. However, C_HALT always clears on a core reset. To halt on a reset, the following
bits must be enabled: DEMCR.VC_CORERESET and C_DEBUGEN. Note that writes to this register in
any size other than word are unpredictable. It is acceptable to read in any size, and it can be used to
avoid or intentionally change a sticky bit.
Behavior of the system when writing to this register while CPU is halted (i.e. C_DEBUGEN = 1 and
S_HALT= 1):
C_HALT=0, C_STEP=0, C_MASKINTS=0 Exit Debug state and start instruction execution. Exceptions
activate according to the exception configuration rules.
C_HALT=0, C_STEP=0, C_MASKINTS=1 Exit Debug state and start instruction execution. PendSV,
SysTick and external configurable interrupts are disabled, otherwise exceptions activate according to
standard configuration rules.
C_HALT=0, C_STEP=1, C_MASKINTS=0 Exit Debug state, step an instruction and halt. Exceptions
activate according to the exception configuration rules.
C_HALT=0, C_STEP=1, C_MASKINTS=1 Exit Debug state, step an instruction and halt. PendSV, SysTick
and external configurable interrupts are disabled, otherwise exceptions activate according to standard
configuration rules.
C_HALT=1, C_STEP=x, C_MASKINTS=x Remain in Debug state
Figure 2-126. DHCSR Register
31

25
S_RESET_ST
R/W-0h

24
S_RETIRE_ST
R/W-0h

19
S_LOCKUP
R/W-0h

18
S_SLEEP
R/W-0h

17
S_HALT
R/W-0h

16
S_REGRDY
R/W-X

3
C_MASKINTS
R/W-0h

2
C_STEP
R/W-0h

1
C_HALT
R/W-0h

0
C_DEBUGEN
R/W-0h

RESERVED
R/W-0h
23

22
RESERVED
R/W-0h

RESERVED
R-0h
7

6
RESERVED
R-0h

5
C_SNAPSTALL
R/W-0h

4
RESERVED
R/W-0h

Table 2-152. DHCSR Register Field Descriptions
Bit
31-26

198

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved.
When writing to this register, 0x28 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.

S_RESET_ST

R/W

Indicates that the core has been reset, or is now being reset, since
the last time this bit was read. This a sticky bit that clears on read.
So, reading twice and getting 1 then 0 means it was reset in the
past. Reading twice and getting 1 both times means that it is being
reset now (held in reset still).
When writing to this register, 0 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

Table 2-152. DHCSR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

S_RETIRE_ST

R/W

Indicates that an instruction has completed since last read. This is a
sticky bit that clears on read. This determines if the core is stalled on
a load/store or fetch.
When writing to this register, 0 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.

23-20

RESERVED

R/W

Software should not rely on the value of a reserved.
When writing to this register, 0x5 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.

S_LOCKUP

R/W

Reads as one if the core is running (not halted) and a lockup
condition is present.
When writing to this register, 1 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.

S_SLEEP

R/W

Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ONEXIT**). Must use C_HALT to gain control or wait for interrupt to
wake-up.
When writing to this register, 1 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.

S_HALT

R/W

The core is in debug state when this bit is set.
When writing to this register, 1 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.

S_REGRDY

R/W

Register Read/Write on the Debug Core Register Selector register is
available. Last transfer is complete.
When writing to this register, 1 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.

15-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

C_SNAPSTALL

R/W

If the core is stalled on a load/store operation the stall ceases and
the instruction is forced to complete. This enables Halting debug to
gain control of the core. It can only be set if: C_DEBUGEN = 1 and
C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates
that no instruction has advanced. This prevents misuse. The bus
state is Unpredictable when this is used. S_RETIRE_ST can detect
core stalls on load/store operations.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

C_MASKINTS

R/W

Mask interrupts when stepping or running in halted debug. This
masking does not affect NMI, fault exceptions and SVC caused by
execution of the instructions. This bit must only be modified when
the processor is halted (S_HALT == 1). C_MASKINTS must be set
or cleared before halt is released (i.e., the writes to set or clear
C_MASKINTS and to set or clear C_HALT must be separate).
Modifying C_MASKINTS while the system is running with halting
debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause
unpredictable behavior.

C_STEP

R/W

Steps the core in halted debug. When C_DEBUGEN = 0, this bit has
no effect. Must only be modified when the processor is halted
(S_HALT == 1).
Modifying C_STEP while the system is running with halting debug
support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause
unpredictable behavior.

C_HALT

R/W

Halts the core. This bit is set automatically when the core Halts. For
example Breakpoint. This bit clears on core reset.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

199

Cortex-M3 Processor Registers

www.ti.com

Table 2-152. DHCSR Register Field Descriptions (continued)
Bit
0

200

Field

Type

Reset

Description

C_DEBUGEN

R/W

Enables debug. This can only be written by AHB-AP and not by the
core. It is ignored when written by the core, which cannot set or clear
it. The core must write a 1 to it when writing C_HALT to halt itself.
The values of C_HALT, C_STEP and C_MASKINTS are ignored by
hardware when C_DEBUGEN = 0. The read values for C_HALT,
C_STEP and C_MASKINTS fields will be unknown to software when
C_DEBUGEN = 0.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.57 DCRSR Register (Offset = DF4h) [reset = X]
DCRSR is shown in Figure 2-127 and described in Table 2-153.
Return to Summary Table.
Deubg Core Register Selector
The purpose of this register is to select the processor register to transfer data to or from. This write-only
register generates a handshake to the core to transfer data to or from Debug Core Register Data Register
and the selected register. Until this core transaction is complete, DHCSR.S_REGRDY is 0. Note that
writes to this register in any size but word are Unpredictable.
Note that PSR registers are fully accessible this way, whereas some read as 0 when using MRS
instructions. Note that all bits can be written, but some combinations cause a fault when execution is
resumed.
Figure 2-127. DCRSR Register
31

RESERVED
W-X
23

20
RESERVED
W-X

16
REGWNR
W-X

2
REGSEL
W-X

RESERVED
W-X
7

6
RESERVED
W-X

Table 2-153. DCRSR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Write 0.

REGWNR

1: Write
0: Read

15-5

RESERVED

Software should not rely on the value of a reserved. Write 0.

4-0

REGSEL

Register select
0x00: R0
0x01: R1
0x02: R2
0x03: R3
0x04: R4
0x05: R5
0x06: R6
0x07: R7
0x08: R8
0x09: R9
0x0A: R10
0x0B: R11
0x0C: R12
0x0D: Current SP
0x0E: LR
0x0F: DebugReturnAddress
0x10: XPSR/flags, execution state information, and exception
number
0x11: MSP (Main SP)
0x12: PSP (Process SP)
0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 |
PRIMASK

31-17
16

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

201

Cortex-M3 Processor Registers

www.ti.com

2.7.4.58 DCRDR Register (Offset = DF8h) [reset = X]
DCRDR is shown in Figure 2-128 and described in Table 2-154.
Return to Summary Table.
Debug Core Register Data
Figure 2-128. DCRDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DCRDR
R/W-X

Table 2-154. DCRDR Register Field Descriptions
Bit
31-0

202

Field

Type

Reset

Description

DCRDR

R/W

This register holds data for reading and writing registers to and from
the processor. This is the data value written to the register selected
by DCRSR. When the processor receives a request from DCRSR,
this register is read or written by the processor using a normal loadstore unit operation. If core register transfers are not being
performed, software-based debug monitors can use this register for
communication in non-halting debug. This enables flags and bits to
acknowledge state and indicate if commands have been accepted
to, replied to, or accepted and replied to.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.59 DEMCR Register (Offset = DFCh) [reset = 0h]
DEMCR is shown in Figure 2-129 and described in Table 2-155.
Return to Summary Table.
Debug Exception and Monitor Control
The purpose of this register is vector catching and debug monitor control. This register manages
exception behavior under debug. Vector catching is only available to halting debug. The upper halfword is
for monitor controls and the lower halfword is for halting exception support. This register is not reset on a
system reset. This register is reset by a power-on reset. The fields MON_EN, MON_PEND, MON_STEP
and MON_REQ are always cleared on a core reset. The debug monitor is enabled by software in the reset
handler or later, or by the **AHB-AP** port. Vector catching is semi-synchronous. When a matching event
is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait
until the next instruction boundary. As a result, it stops on the first instruction of the exception handler.
However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during a vector
read or stack push error the halt occurs on the corresponding fault handler for the vector error or stack
push. 2. If a late arriving interrupt detected during a vector read or stack push error it is not taken. That is,
an implementation that supports the late arrival optimization must suppress it in this case.
Figure 2-129. DEMCR Register
31

28
RESERVED
R/W-0h

24
TRCENA
R/W-0h

19
MON_REQ
R/W-0h

18
MON_STEP
R/W-0h

17
MON_PEND
R/W-0h

16
MON_EN
R/W-0h

RESERVED
R/W-0h
15

13
RESERVED
R/W-0h

10
VC_HARDERR
R/W-0h

9
VC_INTERR
R/W-0h

8
VC_BUSERR
R/W-0h

7
VC_STATERR

6
VC_CHKERR

5
VC_NOCPERR

4
VC_MMERR

2
RESERVED

R/W-0h

0
VC_CORERES
ET
R/W-0h

R/W-0h

Table 2-155. DEMCR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TRCENA

R/W

This bit must be set to 1 to enable use of the trace and debug
blocks: DWT, ITM, ETM and TPIU. This enables control of power
usage unless tracing is required. The application can enable this, for
ITM use, or use by a debugger.

23-20

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MON_REQ

R/W

This enables the monitor to identify how it wakes up. This bit clears
on a Core Reset.
0x0: Woken up by debug exception.
0x1: Woken up by MON_PEND

MON_STEP

R/W

When MON_EN = 1, this steps the core. When MON_EN = 0, this bit
is ignored.
This is the equivalent to DHCSR.C_STEP. Interrupts are only
stepped according to the priority of the monitor and settings of
PRIMASK, FAULTMASK, or BASEPRI.

MON_PEND

R/W

Pend the monitor to activate when priority permits. This can wake up
the monitor through the AHB-AP port. It is the equivalent to
DHCSR.C_HALT for Monitor debug. This register does not reset on
a system reset. It is only reset by a power-on reset. Software in the
reset handler or later, or by the DAP must enable the debug monitor.

31-25
24

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

203

Cortex-M3 Processor Registers

www.ti.com

Table 2-155. DEMCR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

MON_EN

R/W

Enable the debug monitor.
When enabled, the System handler priority register controls its
priority level. If disabled, then all debug events go to Hard fault.
DHCSR.C_DEBUGEN overrides this bit. Vector catching is semisynchronous. When a matching event is seen, a Halt is requested.
Because the processor can only halt on an instruction boundary, it
must wait until the next instruction boundary. As a result, it stops on
the first instruction of the exception handler. However, two special
cases exist when a vector catch has triggered: 1. If a fault is taken
during vectoring, vector read or stack push error, the halt occurs on
the corresponding fault handler, for the vector error or stack push. 2.
If a late arriving interrupt comes in during vectoring, it is not taken.
That is, an implementation that supports the late arrival optimization
must suppress it in this case.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

VC_HARDERR

R/W

Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is
cleared.

VC_INTERR

R/W

Debug trap on a fault occurring during an exception entry or return
sequence. Ignored when DHCSR.C_DEBUGEN is cleared.

VC_BUSERR

R/W

Debug Trap on normal Bus error. Ignored when
DHCSR.C_DEBUGEN is cleared.

VC_STATERR

R/W

Debug trap on Usage Fault state errors. Ignored when
DHCSR.C_DEBUGEN is cleared.

VC_CHKERR

R/W

Debug trap on Usage Fault enabled checking errors. Ignored when
DHCSR.C_DEBUGEN is cleared.

VC_NOCPERR

R/W

Debug trap on a UsageFault access to a Coprocessor. Ignored when
DHCSR.C_DEBUGEN is cleared.

VC_MMERR

R/W

Debug trap on Memory Management faults. Ignored when
DHCSR.C_DEBUGEN is cleared.

3-1

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

VC_CORERESET

R/W

Reset Vector Catch. Halt running system if Core reset occurs.
Ignored when DHCSR.C_DEBUGEN is cleared.

15-11

204

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.4.60 STIR Register (Offset = F00h) [reset = X]
STIR is shown in Figure 2-130 and described in Table 2-156.
Return to Summary Table.
Software Trigger Interrupt
Figure 2-130. STIR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
W-0h

4 3
INTID
W-X

Table 2-156. STIR Register Field Descriptions
Field

Type

Reset

Description

31-9

Bit

RESERVED

Software should not rely on the value of a reserved. Write 0.

8-0

INTID

Interrupt ID field. Writing a value to this bit-field is the same as
manually pending an interrupt by setting the corresponding interrupt
bit in an Interrupt Set Pending Register in NVIC_ISPR0 or
NVIC_ISPR1.

2.7.5 CPU_TPIU Registers
Table 2-157 lists the memory-mapped registers for the CPU_TPIU. All register offset addresses not listed
in Table 2-157 should be considered as reserved locations and the register contents should not be
modified.
Table 2-157. CPU_TPIU Registers
Offset

Acronym

SSPSR

Supported Sync Port Sizes

Section 2.7.5.1

Section

CSPSR

Current Sync Port Size

Section 2.7.5.2

10h

ACPR

Async Clock Prescaler

Section 2.7.5.3

F0h

SPPR

Selected Pin Protocol

Section 2.7.5.4

300h

FFSR

Formatter and Flush Status

Section 2.7.5.5

304h

FFCR

Formatter and Flush Control

Section 2.7.5.6

308h

FSCR

Formatter Synchronization Counter

Section 2.7.5.7

FA0h

CLAIMMASK

Claim Tag Mask

Section 2.7.5.8

FA0h

CLAIMSET

Claim Tag Set

Section 2.7.5.9

FA4h

CLAIMTAG

Current Claim Tag

Section 2.7.5.10

FA4h

CLAIMCLR

Claim Tag Clear

Section 2.7.5.11

FC8h

DEVID

Device ID

Section 2.7.5.12

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

205

Cortex-M3 Processor Registers

2.7.5.1

www.ti.com

SSPSR Register (Offset = 0h) [reset = Bh]

SSPSR is shown in Figure 2-131 and described in Table 2-158.
Return to Summary Table.
Supported Sync Port Sizes
This register represents a single port size that is supported on the device, that is, 4, 2 or 1. This is to
ensure that tools do not attempt to select a port width that an attached TPA cannot capture.
Figure 2-131. SSPSR Register
31

3
FOUR
R-1h

2
THREE
R-0h

1
TWO
R-1h

0
ONE
R-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

RESERVED
R-0h

Table 2-158. SSPSR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

FOUR

4-bit port size support
0x0: Not supported
0x1: Supported

THREE

3-bit port size support
0x0: Not supported
0x1: Supported

TWO

2-bit port size support
0x0: Not supported
0x1: Supported

ONE

1-bit port size support
0x0: Not supported
0x1: Supported

31-4

206

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.5.2

CSPSR Register (Offset = 4h) [reset = 1h]

CSPSR is shown in Figure 2-132 and described in Table 2-159.
Return to Summary Table.
Current Sync Port Size
This register has the same format as SSPSR but only one bit can be set, and all others must be zero.
Writing values with more than one bit set, or setting a bit that is not indicated as supported can cause
Unpredictable behavior. On reset this defaults to the smallest possible port size, 1 bit.
Figure 2-132. CSPSR Register
31

3
FOUR
R/W-0h

2
THREE
R/W-0h

1
TWO
R/W-0h

0
ONE
R/W-1h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

RESERVED
R/W-0h

Table 2-159. CSPSR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

FOUR

R/W

4-bit port enable
Writing values with more than one bit set in CSPSR, or setting a bit
that is not indicated as supported in SSPSR can cause
Unpredictable behavior.

THREE

R/W

3-bit port enable
Writing values with more than one bit set in CSPSR, or setting a bit
that is not indicated as supported in SSPSR can cause
Unpredictable behavior.

TWO

R/W

2-bit port enable
Writing values with more than one bit set in CSPSR, or setting a bit
that is not indicated as supported in SSPSR can cause
Unpredictable behavior.

ONE

R/W

1-bit port enable
Writing values with more than one bit set in CSPSR, or setting a bit
that is not indicated as supported in SSPSR can cause
Unpredictable behavior.

31-4

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

207

Cortex-M3 Processor Registers

2.7.5.3

www.ti.com

ACPR Register (Offset = 10h) [reset = 0h]

ACPR is shown in Figure 2-133 and described in Table 2-160.
Return to Summary Table.
Async Clock Prescaler
This register scales the baud rate of the asynchronous output.
Figure 2-133. ACPR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

7 6 5 4
PRESCALER
R/W-0h

Table 2-160. ACPR Register Field Descriptions
Bit

208

Field

Type

Reset

Description

31-13

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

12-0

PRESCALER

R/W

Divisor for input trace clock is (PRESCALER + 1).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.5.4

SPPR Register (Offset = F0h) [reset = 1h]

SPPR is shown in Figure 2-134 and described in Table 2-161.
Return to Summary Table.
Selected Pin Protocol
This register selects the protocol to be used for trace output.
Note: If this register is changed while trace data is being output, data corruption occurs.
Figure 2-134. SPPR Register
31

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

0
PROTOCOL
R/W-1h

Table 2-161. SPPR Register Field Descriptions
Field

Type

Reset

Description

31-2

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

PROTOCOL

R/W

Trace output protocol
0h = TracePort mode
1h = SerialWire Output (Manchester). This is the reset value.
2h = SerialWire Output (NRZ)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

209

Cortex-M3 Processor Registers

2.7.5.5

www.ti.com

FFSR Register (Offset = 300h) [reset = 8h]

FFSR is shown in Figure 2-135 and described in Table 2-162.
Return to Summary Table.
Formatter and Flush Status
Figure 2-135. FFSR Register
31

3
FTNONSTOP
R-1h

1
RESERVED
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

RESERVED
R-0h

Table 2-162. FFSR Register Field Descriptions
Bit
31-4
3
2-0

210

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

FTNONSTOP

0: Formatter can be stopped
1: Formatter cannot be stopped

RESERVED

This field always reads as zero

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.5.6

FFCR Register (Offset = 304h) [reset = 102h]

FFCR is shown in Figure 2-136 and described in Table 2-163.
Return to Summary Table.
Formatter and Flush Control
When one of the two single wire output (SWO) modes is selected, ENFCONT enables the formatter to be
bypassed. If the formatter is bypassed, only the ITM/DWT trace source (ATDATA2) passes through. The
TPIU accepts and discards data that is presented on the ETM port (ATDATA1). This function is intended
to be used when it is necessary to connect a device containing an ETM to a trace capture device that is
only able to capture Serial Wire Output (SWO) data. Enabling or disabling the formatter causes
momentary data corruption.
Note: If the selected pin protocol register (SPPR.PROTOCOL) is set to 0x00 (TracePort mode), this
register always reads 0x102, because the formatter is automatically enabled. If one of the serial wire
modes is then selected, the register reverts to its previously programmed value.
Figure 2-136. FFCR Register
31

12
RESERVED
R/W-0h

8
TRIGIN
R/W-1h

1
ENFCONT
R/W-1h

0
RESERVED
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

5
RESERVED
R/W-0h

Table 2-163. FFCR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TRIGIN

R/W

Indicates that triggers are inserted when a trigger pin is asserted.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ENFCONT

R/W

Enable continuous formatting:
0: Continuous formatting disabled
1: Continuous formatting enabled

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-9
8
7-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

211

Cortex-M3 Processor Registers

2.7.5.7

www.ti.com

FSCR Register (Offset = 308h) [reset = 0h]

FSCR is shown in Figure 2-137 and described in Table 2-164.
Return to Summary Table.
Formatter Synchronization Counter
Figure 2-137. FSCR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FSCR
R-0h

Table 2-164. FSCR Register Field Descriptions

212

Bit

Field

Type

Reset

Description

31-0

FSCR

The global synchronization trigger is generated by the Program
Counter (PC) Sampler block. This means that there is no
synchronization counter in the TPIU.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.5.8

CLAIMMASK Register (Offset = FA0h) [reset = Fh]

CLAIMMASK is shown in Figure 2-138 and described in Table 2-165.
Return to Summary Table.
Claim Tag Mask
Figure 2-138. CLAIMMASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CLAIMMASK
R-Fh

Table 2-165. CLAIMMASK Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

CLAIMMASK

This register forms one half of the Claim Tag value. When reading
this register returns the number of bits that can be set (each bit is
considered separately):
0: This claim tag bit is not implemented
1: This claim tag bit is not implemented
The behavior when writing to this register is described in CLAIMSET.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

213

Cortex-M3 Processor Registers

2.7.5.9

www.ti.com

CLAIMSET Register (Offset = FA0h) [reset = Fh]

CLAIMSET is shown in Figure 2-139 and described in Table 2-166.
Return to Summary Table.
Claim Tag Set
Figure 2-139. CLAIMSET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CLAIMSET
W-Fh

Table 2-166. CLAIMSET Register Field Descriptions
Bit
31-0

214

Field

Type

Reset

Description

CLAIMSET

This register forms one half of the Claim Tag value. Writing to this
location allows individual bits to be set (each bit is considered
separately):
0: No effect
1: Set this bit in the claim tag
The behavior when reading from this location is described in
CLAIMMASK.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.5.10 CLAIMTAG Register (Offset = FA4h) [reset = 0h]
CLAIMTAG is shown in Figure 2-140 and described in Table 2-167.
Return to Summary Table.
Current Claim Tag
Figure 2-140. CLAIMTAG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CLAIMTAG
R-0h

Table 2-167. CLAIMTAG Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

CLAIMTAG

This register forms one half of the Claim Tag value. Reading this
register returns the current Claim Tag value.
Reading CLAIMMASK determines how many bits from this register
must be used.
The behavior when writing to this register is described in CLAIMCLR.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

215

Cortex-M3 Processor Registers

www.ti.com

2.7.5.11 CLAIMCLR Register (Offset = FA4h) [reset = 0h]
CLAIMCLR is shown in Figure 2-141 and described in Table 2-168.
Return to Summary Table.
Claim Tag Clear
Figure 2-141. CLAIMCLR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CLAIMCLR
W-0h

Table 2-168. CLAIMCLR Register Field Descriptions
Bit
31-0

216

Field

Type

Reset

Description

CLAIMCLR

This register forms one half of the Claim Tag value. Writing to this
location enables individual bits to be cleared (each bit is considered
separately):
0: No effect
1: Clear this bit in the claim tag.
The behavior when reading from this location is described in
CLAIMTAG.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Processor Registers

www.ti.com

2.7.5.12 DEVID Register (Offset = FC8h) [reset = CA0h]
DEVID is shown in Figure 2-142 and described in Table 2-169.
Return to Summary Table.
Device ID
Figure 2-142. DEVID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DEVID
R-CA0h

Table 2-169. DEVID Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

DEVID

CA0h

This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there
is no ETM present.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

217

Chapter 3
SWCU117G – February 2015 – Revised February 2017

ARM® Cortex®-M3 Peripherals
This chapter describes the ARM Cortex-M3 peripherals.
Topic

3.1
3.2

218

...........................................................................................................................

Page

Cortex-M3 Peripherals Introduction .................................................................... 219
Functional Description ...................................................................................... 219

ARM® Cortex®-M3 Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cortex-M3 Peripherals Introduction

www.ti.com

3.1

Cortex-M3 Peripherals Introduction
This chapter provides information on the CC26x0x and CC13x0 implementation of the Cortex-M3
processor peripherals, including:
• System timer (SysTick) (see Section 3.2.1): Provides a simple, 24-bit clear-on-write, decrementing,
wrap-on-zero counter with a flexible control mechanism.
• Nested vectored interrupt controller (NVIC) (see Section 3.2.2):
– Facilitates low-latency exception and interrupt handling
– Works with system controller (see Chapter 6) to control power management
– Implements system control registers
• Cortex-M3 system control block (SCB) (see Section 3.2.3): Provides system implementation
information and system control, including configuration, control, and reporting of system exceptions.
Table 3-1 lists the address map of the private peripheral bus (PPB). Some peripheral register regions are
split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
ADDRESS

3.2

CORE PERIPHERAL

LINK

0xE000 E010 to 0xE000 E01C

System timer (SysTick)

See Section 3.2.1

0xE000 E100 to 0xE000 E420
0xE000 EF00 to 0xE000 EF00

Nested vectored interrupt controller
(NVIC)

See Section 3.2.2

0xE000 E008 to 0xE000 E00F
0xE000 ED00 to 0xE000 ED3F

System control block (SCB)

See Section 3.2.3

0xE000 1000 to 0xE000 1FFC

Data watchpoint and trace (DWT)

See Section 3.2.7

0xE000 2000 to 0xE000 2FFC

Flash patch and breakpoint (FPB)

See Section 3.2.5

0xE000 0000 to 0xE000 0FFC

Instrumentation trace macrocell (ITM)

See Section 3.2.4

0xE00F F000 to 0xE00F FFFC

ROM table

0xE004 0000 to 0xE004 0FFC

Trace port interface unit (TPIU)

0xE00F EFF8 to 0xE00F EFFC

TIPROP

See Section 3.2.6

Functional Description
This chapter provides information on the CC13x0 and CC26x0 implementation of the Cortex-M3 processor
peripherals:
• System timer (SysTick)
• Nested vectored interrupt controller (NVIC)
• System control block (SCB)
• Data watchpoint and trace (DWT)
• Flash patch and breakpoint (FPB)
• Instrumentation trace macrocell (ITM)
• Trace port interface unit (TPIU)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

ARM® Cortex®-M3 Peripherals

219

Functional Description

www.ti.com

3.2.1 SysTick
The Cortex-M3 processor includes an integrated system timer, SysTick, which provides a simple, 24-bit,
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be
used in several different ways. For example, the counter can be:
• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
• A high-speed alarm timer using the system clock
• A variable-rate alarm or signal timer—the duration is range-dependent on the reference clock used and
the dynamic range of the counter
• A simple counter used to measure the time to completion and the time used
• An internal clock-source control based on missing and/or meeting durations—the Control and Status
Register (STCSR) COUNTFLAG bit can be used to determine if an action completed within a set
duration as part of a dynamic clock-management control loop
The timer consists of three registers:
• SysTick Control and Status Register (STCSR): A control and status counter to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status (see Section 2.7.4.3)
• SysTick Reload Value Register (STRVR): The reload value for the counter, used to provide the wrap
value of the counter (see Section 2.7.4.4)
• SysTick Current Value Register (STCVR): The current value of the counter (see Section 2.7.4.5)
When enabled, the timer counts down on each clock from the reload value to 0, reloads (wraps) to the
value in the STRVR register on the next clock edge, then decrements on subsequent clocks. Clearing the
STRVR register disables the counter on the next wrap. When the counter reaches 0, the COUNTFLAG
status bit is set. The COUNTFLAG bit clears on reads.
Writing to the STCVR register clears the register and the COUNTFLAG status bit. The write does not
trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the
register is accessed.
The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the
SysTick counter stops. Ensure that software uses aligned word accesses to access the SysTick registers.
NOTE: When the processor is halted for debugging, the counter does not decrement.

3.2.2 NVIC
This section describes the NVIC and the registers it uses. The NVIC supports:
•
•
•
•
•
•
•
•

34 interrupt lines
A programmable priority level of 0 to 7 for each interrupt. A higher level corresponds to a lower priority,
so level 0 is the highest interrupt priority.
Low-latency exception and interrupt handling
Level and pulse detection of interrupt signals
Dynamic reprioritization of interrupts
Grouping of priority values into group priority and sub-priority fields
Interrupt tail chaining
An external nonmaskable interrupt (NMI)

The processor automatically stacks its state on exception entry and unstacks this state on exception exit,
with no instruction overhead, providing low-latency exception handling.

220

ARM® Cortex®-M3 Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

3.2.2.1

Level-sensitive and Pulse Interrupts

The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as
edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the
interrupt signal. The interrupt sources in CC26x0 and CC13x0 are normally level. That is, they stay active
until the interrupt source is cleared in the peripheral. Typically this happens because the interrupt service
routine (ISR) accesses the peripheral, causing it to clear the interrupt request. To ensure the NVIC detects
the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle.
When the processor enters the ISR, it automatically removes the pending state from the interrupt (see
Section 3.2.2.2). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns
from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. As a
result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
3.2.2.2

Hardware and Software Control of Interrupts

The Cortex-M3 processor latches all interrupts. A peripheral interrupt becomes pending for one of the
following reasons:
• The NVIC detects that the interrupt signal is asserted and the interrupt is not active.
• The NVIC detects a rising edge on the interrupt signal.
• Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt Register (STIR) to make a software-generated interrupt pending (see the NVIC_ISPR0
SETPENDn register bit in Section 2.7.4.10, or the STIR INTID register field in Section 2.7.4.60).
A pending interrupt remains pending until one of the following occurs:
• The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to
active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the
interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might
cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes
to inactive.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the
state of the interrupt changes to pending and active. In this case, when the processor returns from
the ISR the state of the interrupt changes to pending, which might cause the processor to
immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR,
when the processor returns from the ISR the state of the interrupt changes to inactive.
• Software writes to the corresponding interrupt clear-pending register bit:
– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does
not change. Otherwise, the state of the interrupt changes to inactive.
– For a pulse interrupt, the state of the interrupt changes to inactive if the state was pending, or to
active if the state was active and pending.

3.2.3 SCB
The SCB provides system implementation information and system control, including configuration, control,
and reporting of the system exceptions.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

ARM® Cortex®-M3 Peripherals

221

Functional Description

www.ti.com

3.2.4 ITM
The ITM is an application-driven trace source that supports printf() style debugging to trace operating
system and application events, and generates diagnostic system information. The ITM generates trace
information as packets. If multiple sources generate packets at the same time, the ITM arbitrates the order
in which packets are output. These sources in decreasing order of priority are the following:
• Software trace: Software can write directly to ITM stimulus registers to generate packets.
• Hardware trace: The DWT generates these packets, and the ITM outputs the packets.
• Time stamping: Timestamps are generated relative to packets. The ITM contains a 21-bit counter to
generate the timestamp. The Cortex-M3 clock or the bit-clock rate of the serial wire viewer (SWV)
output clocks the counter.
NOTE:

ITM registers are fully accessible in privileged mode. In user mode, all registers can be
read, but only the Stimulus Registers and Trace Enable Registers can be written, and only
when the corresponding Trace Privilege Register bit is set. Invalid user mode writes to the
ITM registers are discarded.

3.2.5 FPB
The FPB implements hardware breakpoints and patches code and data from the Code space to the
System space.
A full FPB unit contains:
• Two literal comparators match against literal loads from the Code space, and remap to a
corresponding area in the System space.
• Six instruction comparators for matching against instruction fetches from the Code space, and remaps
to a corresponding area in the System space. Alternatively, the comparators can be individually
configured to return a Breakpoint (BKPT) instruction to the processor core on a match for hardware
breakpoint capability.
A reduced FPB unit contains:
• Two instruction comparators that can be configured individually to return a BKPT instruction to the
processor on a match, and to provide hardware breakpoint capability
The FPB contains a global enable and individual enables for the eight comparators. If the comparison for
an entry matches, the address is either:
• Remapped to the address set in the remap register plus an offset corresponding to the matched
comparator
or
• Remapped to a BKPT instruction if that feature is enabled
The comparison happens dynamically, but the result of the comparison occurs too late to stop the original
instruction fetch or literal load taking place from the Code space. The processor ignores this transaction,
however, and only the remapped transaction is used.
If the FPB supports only two breakpoints, then only comparators 0 and 1 are used, and the FPB does not
support flash patching.

3.2.6 TPIU
The Cortex-M3 TPIU acts as a bridge between the on-chip trace data from the embedded trace macrocell
(ETM) and the instrumentation trace macrocell (ITM), with separate IDs, to a data stream. The TPIU
encapsulates IDs where required, and the data stream is then captured by a trace port analyzer (TPA).
There are two configurations of the TPIU:
• A configuration that supports ITM debug trace
• A configuration that supports both ITM and ETM debug trace

222

ARM® Cortex®-M3 Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

3.2.7 DWT
The DWT provides watchpoints, data tracing, and system profiling for the processor. A full DWT contains
four comparators that can be configured as any of the following:
• A hardware watchpoint
• An ETM trigger
• A PC sampler event trigger
• A data address sampler event trigger
The first comparator, DWT_COMP0, can also compare against the clock cycle counter, CYCCNT. The
second comparator, DWT_COMP1, can be used as a data comparator.
A reduced DWT contains one comparator that can be used as a watchpoint or as a trigger. A reduced
DWT does not support data matching.
The DWT contains counters for the following:
• Clock cycles (CYCCNT)
• Folded instructions
• Load store unit (LSU) operations
• Sleep cycles
• CPI (that is, all instruction cycles except for the first cycle)
• Interrupt overhead
The DWT generates PC samples at defined intervals and interrupt event information. The DWT can also
provide periodic requests for protocol synchronization to the ITM and the TPIU.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

ARM® Cortex®-M3 Peripherals

223

Functional Description

www.ti.com

3.2.8 Cortex-M3 Memory Map
Table 3-2. Memory Map
Base Address

Module

Module Name

0x0000 0000

FLASHMEM

On-Chip Flash

0x2000 0000

SRAM

Low-Leakage RAM

0x2100 0000

RFC_RAM

RF Core RAM

0x4000 0000

SSI0

Synchronous Serial Interface 0

0x4000 1000

UART0

Universal Asynchronous Receiver/Transmitter 0

0x4000 2000

I2C0

I2C Master/Slave Serial Controller 0

0x4000 8000

SSI1

Synchronous Serial Interface 1

0x4001 0000

GPT0

General Purpose Timer 0

0x4001 1000

GPT1

General Purpose Timer 1

0x4001 2000

GPT2

General Purpose Timer 2

0x4001 3000

GPT3

General Purpose Timer 3

0x4002 0000

UDMA0

Micro Direct Memory Access Controller 0

0x4002 1000

I2S0

I2S Audio DMA 0

0x4002 2000

GPIO

General Purpose Input/Output

0x4002 4000

CRYPTO

Cryptography Engine

0x4002 8000

TRNG

True Random Number Generator

0x4003 0000

FLASH

Flash Controller

0x4003 4000

VIMS

Versatile Instruction Memory System Control

0x4004 0000

RFC_PWR

RF Core Power

0x4004 1000

RFC_DBELL

RF Core Doorbell

0x4004 3000

RFC_RAT

RF Core Radio Timer

0x4008 0000

WDT

Watchdog Timer

0x4008 1000

IOC

Input/Output Controller

0x4008 2000

PRCM

Power, Clock, and Reset Management

0x4008 3000

EVENT

Event Fabric

0x4008 4000

SMPH

System CPU Semaphores

0x4009 0000

AON_SYSCTL

Always On System Control

0x4009 1000

AON_WUC

Always On Wake-up Controller

0x4009 2000

AON_RTC

Always On Real Time Clock

0x4009 3000

AON_EVENT

Always On Event

0x4009 4000

AON_IOC

Always On Input/Output Controller

0x4009 5000

AON_BATMON

Always On Battery and Temperature Monitor

0x400C 1000

AUX_AIODIO0

AUX Analog/Digital Input/Output Control 0

0x400C 2000

AUX_AIODIO1

AUX Analog/Digital Input/Output Control 1

0x400C 4000

AUX_TDCIF

AUX Time-to Digital Converter Interface

0x400C 5000

AUX_EVCTL

AUX Event Control

0x400C 6000

AUX_WUC

AUX Wake-up Controller

0x400C 7000

AUX_TIMER

AUX Timer

0x400C 8000

AUX_SMPH

AUX Semaphores

0x400C 9000

AUX_ANAIF

AUX Analog Interface

0x400C A000

AUX_DDI0_OSC

AUX Digital/Digital Interface, Oscillator control

0x400C B000

AUX_ADI4

AUX Analog/Digital Interface 4

0x400E 0000

AUX_RAM

AUX RAM

0x400E 1000

AUX_SCE

AUX Sensor Control Engine

0x5000 1000

FCFG1

Factory Configuration Area 1

0x5000 3000

CCFG

Customer Configuration Area

224 ARM® Cortex®-M3 Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Functional Description

www.ti.com

Table 3-2. Memory Map (continued)
Base Address

Module

Module Name

0xE000 0000

CPU_ITM

Cortex-M Instrumentation Trace Macrocell

0xE000 1000

CPU_DWT

Cortex-M Data Watchpoint and Trace

0xE000 2000

CPU_FPB

Cortex-M Flash Patch and Breakpoint

0xE000 E000

CPU_SCS

Cortex-M System Control Space

0xE004 0000

CPU_TPIU

Cortex-M Trace Port Interface Unit

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

ARM® Cortex®-M3 Peripherals

225

Chapter 4
SWCU117G – February 2015 – Revised February 2017

Interrupts and Events
This chapter describes CC26x0 and CC13x0 interrupts and events.

226

Topic

...........................................................................................................................

4.1
4.2
4.3
4.4
4.5
4.6
4.7

Exception Model ...............................................................................................
Fault Handling ..................................................................................................
Event Fabric.....................................................................................................
AON Event Fabric .............................................................................................
MCU Event Fabric .............................................................................................
AON Events .....................................................................................................
Interrupts and Events Registers .........................................................................

Interrupts and Events

Page

227
234
237
238
240
245
246

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Exception Model

www.ti.com

4.1

Exception Model
The ARM® Cortex®-M3 processor and the nested vectored interrupt controller (NVIC) prioritize and handle
all exceptions in handler mode. The state of the processor is automatically stored to the stack on an
exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The
vector is fetched in parallel to state saving, thus enabling efficient interrupt entry. The processor supports
tail-chaining, which enables performance of back-to-back interrupts without the overhead of state saving
and restoration.
Table 4-1 lists all exception types. Software can set eight priority levels on seven of these exceptions
(system handlers) as well as on CC26x0 and CC13x0 interrupts (listed in Table 4-8).
Priorities on the system handlers are set with the NVIC System Handler Priority n Registers
(CPU_SCS:SHPRn). Interrupts are enabled through the NVIC Interrupt Set Enable n Register
(CPU_SCS:NVIC_ISERn) and prioritized with the NVIC Interrupt Priority n Registers
(CPU_SCS:NVIC_IPRn). Priorities can be grouped by splitting priority levels into preemption priorities and
subpriorities. All the interrupt registers are described in Section 3.2.2.
Internally, the highest user programmable priority (0) is treated as third priority, after a reset, and a hard
fault, in that order.
NOTE: 0 is the default priority for all the programmable priorities.

CAUTION
After a write to clear an interrupt source, it may take several processor cycles
for the NVIC to detect the interrupt source deassertion due to the write buffer.
Thus, if the interrupt clear is done as the last action in an interrupt handler, it is
possible for the interrupt handler to complete while the NVIC detects the
interrupt as still asserted, causing the interrupt handler to be re-entered
errantly. This situation can be avoided by either clearing the interrupt source at
the beginning of the interrupt handler or by performing a read from the same
address after the write to clear the interrupt source (and flush the write buffer).
For more information on exceptions and interrupts, see Section 3.2.2.

4.1.1 Exception States
Each exception is in one of the following states:
• Inactive: The exception is not active and not pending.
• Pending: The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
• Active: An exception is being serviced by the processor but has not completed. An exception handler
can interrupt the execution of another exception handler. In this case, both exceptions are in the active
state.
• Active and Pending: The exception is being serviced by the processor, and there is a pending
exception from the same source.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

227

Exception Model

www.ti.com

4.1.2 Exception Types
The exception types are:
• Reset: Reset is invoked on power up or a warm reset. The exception model treats reset as a special
form of exception. When reset is asserted, the operation of the processor stops, potentially at any point
in an instruction. When reset is deasserted, execution restarts from the address provided by the reset
entry in the vector table. Execution restarts as privileged execution in thread mode.
• Hard Fault: A hard fault is an exception that occurs because of an error during exception processing,
or because an exception cannot be managed by any other exception mechanism. Hard faults have a
fixed priority of –1, meaning they have higher priority than any exception with configurable priority.
• Bus Fault: A bus fault is an exception that occurs because of a memory-related fault for an instruction
or data memory transaction such as a prefetch fault or a memory access fault. This fault can be
enabled or disabled.
• Usage Fault: A usage fault is an exception that occurs because of a fault related to instruction
execution, such as the following:
– An undefined instruction
– An illegal unaligned access
– Invalid state on instruction execution
– An error on exception return
An unaligned address on a word or halfword memory access or division by 0 can cause a usage fault
when the core is properly configured.
• SVCall: A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS
environment, applications can use SVC instructions to access OS kernel functions and device drivers.
• Debug Monitor: This exception is caused by the debug monitor (when not halting). This exception is
active only when enabled. This exception does not activate if it is a lower priority than the current
activation.
• PendSV: PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is triggered
using the Interrupt Control and State CPU_SCS:ICSR register.
• SysTick: A SysTick exception is generated by the system timer when it reaches 0 and is enabled to
generate an interrupt. Software can also generate a SysTick exception using the Interrupt Control and
State register, CPU_SCS:ICSR. In an OS environment, the processor can use this exception as
system tick.
• Interrupt (IRQ): An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a
software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction
execution. In the system, peripherals use interrupts to communicate with the processor. Table 4-8 lists
the interrupts on the CC26x0 and CC13x0 controller.
For an asynchronous exception, other than reset, the processor can execute another instruction between
when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 4-1 shows as having configurable priority(see
the CPU_SCS:SHCSR register in Section 2.7.4.35 and the CPU_SCS:NVIC_ICER0 register in
Section 2.7.4.9).
For more information about hard faults, bus faults, and usage faults, see Section 4.2.
Table 4-1. Exception Types
Vector Number

Priority (1)

Vector Address or
Offset (2)

Activation

–

0x0000 0000

Stack top is loaded from
the first entry of the
vector table on reset.

Reset

–3 (highest)

0x0000 0004

Asynchronous

–

Exception Type

(1)
(2)

–

0 is the default priority for all the programmable priorities.
See Section 4.1.4.

228 Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Exception Model

www.ti.com

Table 4-1. Exception Types (continued)
Vector Number

Priority (1)

Vector Address or
Offset (2)

Hard fault

–1

0x0000 000C

–

Bus fault

Programmable (3)

0x0000 0014

Synchronous when
precise and
asynchronous when
imprecise
Synchronous

Exception Type

Usage fault

Activation

Programmable

0x0000 0018

7 to 10

–

SVCall

Programmable

0x0000 002C

Synchronous

Debug monitor

Programmable

0x0000 0030

Synchronous

–

PendSV

Programmable

0x0000 0038

Asynchronous

0x0000 003C

Asynchronous

–

SysTick
Interrupts
(3)
(4)

Programmable

16 and above

Programmable (4)

Reserved

0x0000 0040 and above Asynchronous

See CPU_SCS:SHPR 1 in Figure 2-102.
See the PRIn registers in Section 2.7.4.

Table 4-2. Interrupts
Vector Number

Interrupt Number
(Bit in Interrupt Registers)

0 to 15

–

0x0000 0000 to 0x0000 003C

Processor exceptions

0x0000 0040

GPIO edge detect

0x0000 0044

I2C

0x0000 0048

RF Core and packet engine 1

0x0000 004C

Unassigned

0x0000 0050

AON RTC

0x0000 0054

UART0

0x0000 0058

UART1

0x0000 005C

SSI0

0x0000 0060

SSI1

0x0000 0064

RF Core and packet engine 2

0x0000 0068

RF Core hardware

0x0000 006C

RF command acknowledge

0x0000 0070

I2S

0x0000 0074

Unassigned

0x0000 0078

Watchdog timer

0x0000 007C

GPTimer 0A

0x0000 0080

GPTimer 0B

0x0000 0084

GPTimer 1A

0x0000 0088

GPTimer 1B

0x0000 008C

GPTimer 2A

0x0000 0090

GPTimer 2B

0x0000 0094

GPTimer 3A

0x0000 0098

GPTimer 3B

0x0000 009C

Crypto

0x0000 00A0

µDMA software defined

0x0000 00A4

µDMA error

0x0000 00A8

Flash

0x0000 00AC

Software event 0

Vector Address or Offset

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Description

Interrupts and Events 229

Exception Model

www.ti.com

Table 4-2. Interrupts (continued)
Vector Number

Interrupt Number
(Bit in Interrupt Registers)

0x0000 00B0

AUX combined event

0x0000 00B4

AON programmable event

0x0000 00B8

Dynamic programmable event

0x0000 00BC

AUX comparator A

0x0000 00C0

AUX ADC new sample available or ADC
DMA done, ADC underflow and overflow

0x0000 00C4

True random number generator

Vector Address or Offset

Description

4.1.3 Exception Handlers
The processor handles exceptions using:
• Interrupt Service Routines (ISRs): Interrupts (IRQx) are the exceptions handled by ISRs.
• Fault Handlers: Hard fault, usage fault, and bus fault are fault exceptions handled by the fault
handlers.
• System Handlers: PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions that
are handled by system handlers.

4.1.4 Vector Table
Figure 4-1 contains the reset value of the stack pointer and the start addresses, also called exception
vectors, for all exception handlers. The vector table is constructed using the vector address or offset listed
in Table 4-1. Figure 4-1 shows the order of the exception vectors in the vector table. The least significant
bit (LSB) of each vector must be 1, indicating that the exception handler is Thumb code.

230

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Exception Model

www.ti.com

Figure 4-1. Vector Table
Exception number

IRQ number

Offset

Vector
IRQ33

33
0x00C4
.
.
.

.
.
.

0x004C
IRQ2

0x0048
17

–1

IRQ1
0x0044
IRQ0
0x0040
Systick
0x003C
PendSV

–2

0x0038
13

Reserved

Reserved for debug
SVCall

–5

0x002C
10
9
Reserved
8
7
6

–10

–11

Usage fault
0x0018
Bus fault
0x0014

–12

–13

–14

Reserved
0x0010
Hard fault
0x000C
NMI
0x0008
Reset

1
0x0004

Initial SP value
0x 0000

On system reset, the vector table is fixed at address 0x0000 0000. Privileged software can write to the
Vector Table Offset Register (CPU_SCS:VTOR) to relocate the vector table start address to a different
memory location, in the range 0x0000 0200 to 0x3FFF FE00. When configuring the CPU_SCS:VTOR
register, the offset must be aligned on a 512-byte boundary.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

231

Exception Model

www.ti.com

4.1.5 Exception Priorities
As Table 4-1 shows, all exceptions have an associated priority, with a lower priority value indicating a
higher priority and configurable priorities for all exceptions except reset, and hard fault. If software does
not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For
information about configuring exception priorities, see the System Handlers Priority Registers
(CPU_SCS:SHPRn) listed in Table 2-96 and the Interrupt Priority Registers (CPU_SCS:NVIC_IPRn) listed
in Table 2-96.
NOTE: Configurable priority values for the CC26x0 and CC13x0 implementation are in the range
from 0 to 7. This means that the Reset and Hard fault exceptions, with fixed negative priority
values, always have a higher priority than any other exception.

Assigning a higher priority value to IRQ[0] and a lower-priority value to IRQ[1], for example, means that
IRQ[1] has higher priority than IRQ[0]. If IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before
IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if IRQ[0] and IRQ[1] are pending and have the same priority,
then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a higher
priority exception occurs. If an exception occurs with the same priority as the exception being handled, the
handler is not preempted, irrespective of the exception number. However, the status of the new interrupt
changes to pending.

4.1.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping
divides each interrupt priority register entry into two fields:
• An upper field that defines the group priority
• A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is executing an
interrupt exception handler, another interrupt with the same group priority as the interrupt being handled
does not preempt the handler.
If multiple pending interrupts have the same group priority, the sub-priority field determines the order in
which they are processed. If multiple pending interrupts have the same group priority and subpriority, the
interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see Application
Interrupt/Reset Control (CPU_SCS:AIRCR) in Section 2.7.4.29.

232

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Exception Model

www.ti.com

4.1.7 Exception Entry and Return
Descriptions of exception handling use the following terms:
• Preemption: When the processor is executing an exception handler, an exception can preempt the
exception handler if its priority is higher than the priority of the exception being handled. For more
information about preemption by an interrupt, see Section 4.1.6. When one exception preempts
another, the exceptions are called nested exceptions. For more information, see Section 4.1.7.1.
• Return: Return occurs when the exception handler is completed, and there is no pending exception
with sufficient priority to be serviced and the completed exception handler was not handling a latearriving exception. The processor pops the stack and restores the processor state to the state it had
before the interrupt occurred. For more information, see Section 4.1.7.2.
• Tail Chaining: This mechanism speeds up exception servicing. When an exception handler
completes, if a pending exception meets the requirements for exception entry, the stack pop is skipped
and control transfers to the new exception handler.
• Late Arriving: This mechanism speeds up preemption. If a higher-priority exception occurs during
state saving for a previous exception, the processor switches to handle the higher-priority exception
and initiates the vector fetch for that exception. State saving is not affected by late arrival because the
state saved is the same for both exceptions. Therefore, the state saving continues uninterrupted. The
processor can accept a late-arriving exception until the first instruction of the exception handler of the
original exception enters the execute stage of the processor. When the late-arriving exception returns
from the exception handler, the normal tail-chaining rules apply.
4.1.7.1

Exception Entry

Exception entry occurs when there is a pending exception with sufficient priority and either the processor
is in thread mode or the new exception is of a higher priority than the exception being handled, in which
case the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers (see
PRIMASK on Priority Mask Register, FAULTMASK on Fault Mask Register, and BASEPRI on Base
Priority Register). An exception with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception,
the processor pushes information onto the current stack (see Figure 4-2). This operation is referred to as
stacking and the structure of eight data words is referred to as stack frame.
Figure 4-2. Exception Stack Frame
...
{aligner}

Pre-IRQ top of stack

xPSR
PC
LR
R12
R3
R2
R1
R0

IRQ top of stack

Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
The stack frame includes the return address, which is the address of the next instruction in the interrupted
program. This value is restored to the PC at exception return so that the interrupted program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking completes, the processor starts executing the
exception handler. At the same time, the processor writes an EXC_RETURN value to the LR, indicating
which stack pointer corresponds to the stack frame and what operation mode the processor was in before
the entry occurred.
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

233

Fault Handling

www.ti.com

If no higher priority exception occurs during exception entry, the processor starts executing the exception
handler and automatically changes the status of the corresponding pending interrupt to active.
If another higher priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status of the
earlier exception.
4.1.7.2

Exception Return

Exception return occurs when the processor is in handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
• An LDM or POP instruction that loads the PC
• A BX instruction using any register
• An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on
this value to detect when the processor completes an exception handler. The lowest 4 bits of this value
provide information on the return stack and processor mode. Table 4-3 lists the EXC_RETURN values
with a description of the exception return behavior.
EXC_RETURN bits 31–4 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 4-3. Exception Return Behavior

4.2

EXC_RETURN[31:0]

Description

0xFFFF FFF0

Reserved

0xFFFF FFF1

Return to handler mode
Exception return uses state from MSP
Execution uses MSP after return.

0xFFFF FFF2 to 0xFFFF FFF8

Reserved

0xFFFF FFF9

Return to thread mode: VTOR
Exception return uses state from MSP
Execution uses MSP after return.

0xFFFF FFFA to 0xFFFF FFFC

Reserved

0xFFFF FFFD

Return to thread mode
Exception return uses state from PSP
Execution uses PSP after return

0xFFFF FFFE to 0xFFFF FFFF

Reserved

Fault Handling
Faults are a subset of the exceptions (see Section 4.1). The following conditions generate a fault:
• A bus error on an instruction fetch or vector table load or a data access
• An internally detected error such as an undefined instruction or an attempt to change state with a BX
instruction

4.2.1 Fault Types
Table 4-4 lists the types of fault, the handler used for the fault, the corresponding fault status register, and
the register bit that indicates the fault has occurred. For more information about the fault status registers,
see CPU_SCS:CFSR in Section 2.7.4.36.

234 Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Fault Handling

www.ti.com

Table 4-4. Faults
Fault

Handler

Fault Status Register

Bit Name

Bus error on a vector read

Hard fault

Hard Fault Status (HFSR)

VECTTBL

Fault escalated to a hard fault

Hard fault

Hard Fault Status (HFSR)

FORCED

Bus error during exception
stacking

Bus fault

Bus Fault Status (BFSR)

STKERR

Bus error during exception
unstacking

Bus fault

Bus Fault Status (BFSR)

UNSTEKRR

Bus error during instruction
prefetch

Bus fault

Bus Fault Status (BFSR)

IBUSERR

Precise data bus error

Bus fault

Bus Fault Status (BFSR)

PRECISERR

Imprecise data bus error

Bus fault

Bus Fault Status (BFSR)

IMPRECISERR

Attempt to access a coprocessor

Usage fault

Usage Fault Status (UFSR)

NOCP

Undefined instruction

Usage fault

Usage Fault Status (UFSR)

UNDEFINSTR

Attempt to enter an invalid
instruction set state (1)

Usage fault

Usage Fault Status (UFSR)

INVSTATE

Invalid EXC_RETURN value

Usage fault

Usage Fault Status (UFSR)

INVPC

Illegal unaligned load or store

Usage fault

Usage Fault Status (UFSR)

UNALIGNED

Divide by 0

Usage fault

Usage Fault Status (UFSR)

DIVBYZERO

(1)

Trying to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI
continuation.

4.2.2 Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see CPU_SCS:SHPR1 in
Section 2.7.4.32). Software can disable execution of the handlers for these faults (see CPU_SCS:SHCSR
in Section 2.7.4.35).
Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another fault
handler as described in Section 4.1.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority
escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when:
• A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault
occurs because a fault handler cannot preempt itself because it must have the same priority as the
current priority level.
• A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation
happens because the handler for the new fault cannot preempt the fault handler that is currently
executing.
• An exception handler causes a fault for which the priority is the same as or lower than the exception
that is currently executing.
• A fault occurs and the handler for that fault is not enabled.
NOTE: If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault
does not escalate to a hard fault. Thus, if a corrupted stack causes a fault, the fault handler
executes even though the stack push for the handler failed. The fault handler operates but
the stack contents are corrupted.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

235

Fault Handling

www.ti.com

4.2.3 Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults, the fault address register indicates
the address accessed by the operation that caused the fault, as shown in Table 4-5.
Table 4-5. Fault Status and Fault Address Registers
Handler

Status Register Name

Address Register Name

Hard fault

Hard Fault Status (HFSR)

–

See Section 2.7.4.37

Bus fault

Bus Fault Status (BFSR)

Bus Fault Address (BFAR)

See Section 2.7.4.40

Usage fault

Usage Fault Status (UFSR)

–

4.2.4 Lockup
The processor enters a lockup state if a hard fault occurs when executing the hard fault handlers. In a
CC26x0 and CC13x0 device, a lockup state resets the system.

236

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Event Fabric

www.ti.com

4.3

Event Fabric

4.3.1 Introduction
The event fabric is a combinational router between event sources and event subscribers. The event inputs
are routed to a central event-bus where a subscriber can select the appropriate events and output those
as inputs to peripherals. Figure 4-3 shows the general concept of the event fabric. The event fabric is
strictly combinational logic. Because this chapter provides only a general overview of the event fabric and
the system CPU, NMI, and Freeze subscriber, refer to the specific peripheral chapters in this user's guide
to understand how to use and configure the events for the different subscribers and peripherals.
Most of the events (signals) are statically routed, meaning that only a small number of configurable output
lines go to the event subscribers. A configurable output line from a subscriber can choose from a list of
several input events available to the specific subscriber in question. Subscribers output event signaling
identical to input signaling. That is, events are simply passed through the event fabric as presented to the
input ports. Possible event types include system hardware interrupts, software programmable interrupts,
and DMA triggers. All event inputs are considered level-triggered events active high. Events like DMA
triggers may or may not be level-type signals.
Figure 4-3. Event Fabric Concept
Event Fabric

Event bus

Subscriber X
Selection Register

Event Sources
(Peripherals)

Event Subscribers
(Peripherals)

Subscriber input

Subscriber output

Subscriber (X+1)

Figure 4-3 shows a simple illustration of the event fabric concept. Clearly the event fabric is not a
peripheral in itself, but rather a block of routing between the peripherals and more. The lines that have
configurable inputs are controlled by selection registers that are connected to a MUX, which forwards the
selected input in the subscriber to the peripherals.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

237

Event Fabric

www.ti.com

4.3.2 Event Fabric Overview
There are two main event fabric blocks in the CC26x0 and CC13x0 family. One in the MCU power domain
(MCU event fabric) and the other in the AON power domain (AON event fabric). Figure 4-4 shows a
simplified overview of the two modules together. The MCU event fabric is one of the subscribers to the
AON event fabric.
Figure 4-4. Event Fabric Overview (Simplified)
MCU Event Fabric
Legend
Event
Subscriber
Fabric

I2C
NMI

Subscriber

WIC

Peripheral

SSI0

System CPU

SEL

SSI1

Radio

Crypto

Radio

SEL

UART0
GPT[0-3]

AON Event Fabric

GPT[0-3]

WDT

IOC
WUC

WUC

IOC

RTC

Flash

MCU Event Bus

SEL

DMA

µDMA

SEL

RTC

AUX

AON Event Bus

AUX

MCU Event Fabric

AUX

SEL

AON
I2S

SEL

I2S
SEL

JTAG
JTAG

Freeze

RTC, WDT, AUX

SEL

EVENT_SW_EVENT

BATMON

4.3.2.1

Registers

The event fabric has two types of registers. The first type, a configuration register, is used to control and
report the selection settings for a subscriber output. For each subscriber output, an address is mapped for
a read register that contains a value representing the selection of the input event currently set for that
subscriber output. For nonconfigurable outputs, only a read-only register is implemented. A read to that
address returns the static, predefined value. The second type of register in the event fabric, of which there
is only one, is an operational register named SWEV. This register sets and clears any of the four software
events.
The AON event fabric is controlled through a series of registers residing in the MCU power domain. An
AON-MCU interface block in the AON domain shadows these registers, thereby providing them for the
AON block when the MCU is in power-down states.

4.4

AON Event Fabric
The AON event fabric resides in the AON power domain where the wake-up controller, the debug
subsystem, the AUX domain, and the real-time clock (RTC) reside.

238

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AON Event Fabric

www.ti.com

4.4.1 Common Input Event List
Section 4.5.1 lists the input events for the AON event fabric. The sources for these events are considered
level-triggered active high.

4.4.2 Event Subscribers
There are three subscribers in the AON event fabric as can be seen in Figure 4-4. The first subscriber is
the MCU event fabric, which resides in the MCU power domain. The other two subscribers, the WUC and
RTC, both reside in the AON power domain and are presented in the following subsections.
4.4.2.1

Wake-Up Controller (WUC)

The WUC receives output signals from the WUC subscriber in the AON event fabric where power-on
sequences can be triggered by configured input events from JTAG, AUX, or the MCU. JTAG has one
wake-up event going to the WUC, while the AUX domain has three programmable input events and the
MCU domain has four programmable input events. These specific input events are ORed together to form
a single input to the WUC, one from the MCU and one from the AUX. Figure 4-5 shows this configuration.
The inputs can be configured in the two selection registers AON_EVENT:AUXWUSEL and
AON_EVENT:MCUWUSEL. Any of the events listed in can be chosen as input by choosing the
appropriate event ID. By default, these IDs are set to 63 (NULL, no event), where the lines always stay
logic low.
Figure 4-5. WUC Subscriber in AON Event Fabric

WUC

JTAG

AUX

MCU

Event bus

Event Sources
(Peripherals)

4.4.2.2

Real-Time Clock

The RTC has a programmable event, which can be configured in the RTCSEL register, and a fixed event
with ID 46 (Channel 2 clear – from AUX).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

239

MCU Event Fabric

4.4.2.3

www.ti.com

MCU Event Fabric

Seven output events from the AON event fabric are routed as inputs to the MCU event fabric. These
events are:
1. AON programmable 0
2. AON programmable 1
3. AON programmable 2
4. AON edge detect
5. AON RTC
There are three programmable lines from which any of the input events from Table 4-6 can be chosen.
This can be set in the CTRL_EVENT:MCU register.

4.5

MCU Event Fabric
The MCU event fabric resides in the MCU power domain and routes signals between most of the
peripherals and different internal blocks. Only a few of the subscribers in the MCU event fabric are
described in this section. For more information on the remaining subscribers, refer to the specific
peripheral chapters for the appropriate consumer (peripheral) for that specific subscriber.

4.5.1 Common Input Event List
Table 4-6 lists the input events for the MCU event fabric. The sources for these events are considered
level-triggered active high.
Table 4-6. MCU Event Fabric Input Events
Event Number

Event Enumeration

Description

0x0

NONE

Always inactive (LOW)

0x1

AON_PROG0

Event selected by AON_EVENT MCU event selector,
AON_EVENT:EVTOMCUSEL.AON_PROG0_EV

0x2

AON_PROG1

Event selected by AON_EVENT MCU event selector,
AON_EVENT:EVTOMCUSEL.AON_PROG1_EV

0x3

AON_PROG2

Event selected by AON_EVENT MCU event selector,
AON_EVENT:EVTOMCUSEL.AON_PROG2_EV

0x4

AON_GPIO_EDGE

Edge detect event from IOC. Configured by the
IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings

0x5

RESERVED

0x6

RESERVED

0x7

AON_RTC_COMB

Event from AON_RTC controlled by the
AON_RTC:CTL.COMB_EV_MASK setting

0x8

I2S_IRQ

Interrupt event from I2S

0x9

I2C_IRQ

Interrupt event from I2C

0xA

AON_AUX_SWEV0

AUX software event 0, AUX_EVCTL:SWEVSET.SWEV0

0xB

AUX_COMB

AUX combined event, the corresponding flag register is here
AUX_EVCTL:EVTOMCUFLAGS.*

0xC

GPT2A

GPT2A interrupt event, controlled by GPT2:TAMR.*

0xD

GPT2B

GPT2B interrupt event, controlled by GPT2:TBMR.*

0xE

GPT3A

GPT3A interrupt event, controlled by GPT3:TAMR.*

0xF

GPT3B

GPT3B interrupt event, controlled by GPT3:TBMR.*

0x10

GPT0A

GPT0A interrupt event, controlled by GPT0:TAMR.*

0x11

GPT0B

GPT0B interrupt event, controlled by GPT0:TBMR.*

0x12

GPT1A

GPT1A interrupt event, controlled by GPT1:TAMR.*

0x13

GPT1B

GPT1B interrupt event, controlled by GPT1:TBMR.*

0x14

DMA_CH0_DONE

DMA done for software-triggered UDMA channel 0, see
UDMA0:SOFTREQ.*

240 Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

MCU Event Fabric

www.ti.com

Table 4-6. MCU Event Fabric Input Events (continued)
Event Number

Event Enumeration

Description

0x15

FLASH

FLASH controller error event, the status flags are
FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT

0x16

DMA_CH18_DONE

DMA done for software-triggered UDMA channel 18, see
UDMA0:SOFTREQ.*

0x17

RESERVED

0x18

WDT_IRQ

Watchdog interrupt event, controlled by WDT:CTL.INTEN

0x19

RFC_CMD_ACK

RFC Doorbell Command Acknowledgment interrupt, equivalent to
RFC_DBELL:RFACKIFG.ACKFLAG.

0x1A

RFC_HW_COMB

Combined RCF hardware interrupt, corresponding flag is here
RFC_DBELL:RFHWIFG.*

0x1B

RFC_CPE_0

Combined interrupt for CPE-generated events. Corresponding flags are
here RFC_DBELL:RFCPEIFG.*. Only interrupts selected with CPE0 in
RFC_DBELL:RFCPEIFG.* can trigger a RFC_CPE_0 event.

0x1C

AUX_SWEV0

AUX software event 0, triggered by AUX_EVCTL:SWEVSET.SWEV0,
also available as AUX_EVENT0 AON wake-up event.
MCU domain wake-up control AON_EVENT:MCUWUSEL.*
AUX domain wake-up control AON_EVENT:AUXWUSEL.*

0x1D

AUX_SWEV1

AUX software event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1,
also available as AUX_EVENT2 AON wake-up event.
MCU domain wake-up control AON_EVENT:MCUWUSEL.*
AUX domain wake-up control AON_EVENT:AUXWUSEL.*

0x1E

RFC_CPE_1

Combined interrupt for CPE-generated events. Corresponding flags are
here RFC_DBELL:RFCPEIFG.*. Only interrupts selected with CPE1 in
RFC_DBELL:RFCPEIFG.* can trigger a RFC_CPE_1 event.

0x1F to 0x21

RESERVED

0x22

SSI0_COMB

SSI0 combined interrupt, interrupt flags are found here SSI0:MIS.*.

0x23

SSI1_COMB

SSI0 combined interrupt, interrupt flags are found here SSI1:MIS.*.

0x24

UART0_COMB

UART0 combined interrupt, interrupt flags are found here UART0:MIS.*.

0x25

RESERVED

Always 0 (LOW)

0x26

DMA_ERR

DMA bus error, corresponds to UDMA0:ERROR.STATUS

0x27

DMA_DONE_COMB

Combined DMA done corresponding flags are here
UDMA0:REQDONE.*

0x28

SSI0_RX_DMABREQ

SSI0 RX DMA burst request, controlled by SSI0:DMACR.RXDMAE

0x29

SSI0_RX_DMASREQ

SSI0 RX DMA single request, controlled by SSI0:DMACR.RXDMAE

0x2A

SSI0_TX_DMABREQ

SSI0 TX DMA burst request, controlled by SSI0:DMACR.TXDMAE

0x2B

SSI0_TX_DMASREQ

SSI0 TX DMA single request, controlled by SSI0:DMACR.TXDMAE

0x2C

SSI1_RX_DMABREQ

SSI1 RX DMA burst request, controlled by SSI0:DMACR.RXDMAE

0x2D

SSI1_RX_DMASREQ

SSI1 RX DMA single request, controlled by SSI0:DMACR.RXDMAE

0x2E

SSI1_TX_DMABREQ

SSI1 TX DMA burst request, controlled by SSI0:DMACR.TXDMAE

0x2F

SSI1_TX_DMASREQ

SSI1 TX DMA single request, controlled by SSI0:DMACR.TXDMAE

0x30

UART0_RX_DMABREQ

UART0 RX DMA burst request, controlled by
UART0:DMACTL.RXDMAE

0x31

UART0_RX_DMASREQ

UART0 RX DMA single request, controlled by
UART0:DMACTL.RXDMAE

0x32

UART0_TX_DMABREQ

UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE

0x33

UART0_TX_DMASREQ

UART0 TX DMA single request, controlled by
UART0:DMACTL.TXDMAE

0x34 to 0x37

RESERVED

Always 0

0x38

RESERVED

0x39

RESERVED

0x3A

RESERVED

0x3B

RESERVED

0x3C

RESERVED

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Interrupts and Events 241

MCU Event Fabric

www.ti.com

Table 4-6. MCU Event Fabric Input Events (continued)
Event Number

Event Enumeration

Description

0x3D

GPT0A_CMP

GPT0A compare event. Configured by GPT0:TAMR.TCACT.

0x3E

GPT0B_CMP

GPT0B compare event. Configured by GPT0:TBMR.TCACT.

0x3F

GPT1A_CMP

GPT1A compare event. Configured by GPT1:TAMR.TCACT.

0x40

GPT1B_CMP

GPT1B compare event. Configured by GPT1:TBMR.TCACT.

0x41

GPT2A_CMP

GPT2A compare event. Configured by GPT2:TAMR.TCACT.

0x42

GPT2B_CMP

GPT2B compare event. Configured by GPT2:TBMR.TCACT.

0x43

GPT3A_CMP

GPT3A compare event. Configured by GPT3:TAMR.TCACT.

0x44

GPT3B_CMP

GPT3B compare event. Configured by GPT3:TBMR.TCACT.

0x45 to 0x4C

TIE_LOW

Not used; tied to 0 (LOW)

0x4D

GPT0A_DMABREQ

GPT 0A DMA trigger event. Configured by GPT0:DMAEV.*.

0x4E

GPT0B_DMABREQ

GPT 0B DMA trigger event. Configured by GPT0:DMAEV.*.

0x4F

GPT1A_DMABREQ

GPT 1A DMA trigger event. Configured by GPT1:DMAEV.*.

0x50

GPT1B_DMABREQ

GPT 1B DMA trigger event. Configured by GPT1:DMAEV.*.

0x51

GPT2A_DMABREQ

GPT 2A DMA trigger event. Configured by GPT2:DMAEV.*.

0x52

GPT2B_DMABREQ

GPT 2B DMA trigger event. Configured by GPT2:DMAEV.*.

0x53

GPT3A_DMABREQ

GPT 3A DMA trigger event. Configured by GPT3:DMAEV.*.

0x54

GPT3B_DMABREQ

GPT 3B DMA trigger event. Configured by GPT3:DMAEV.*.

0x55

PORT_EVENT0

Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID.
Events on ports configured with **ENUM** **PORT_EVENT0** are
routed here.

0x56

PORT_EVENT1

Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID.
Events on ports configured with PORT_EVENT1 are routed here.

0x57

PORT_EVENT2

Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID.
Events on ports configured with PORT_EVENT2 are routed here.

0x58

PORT_EVENT3

Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID.
Events on ports configured with PORT_EVENT3 are routed here.

0x59

PORT_EVENT4

Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID.
Events on ports configured with ENUM PORT_EVENT4 are routed here.

0x5A

PORT_EVENT5

Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID.
Events on ports configured with PORT_EVENT4 are routed here.

0x5B

PORT_EVENT6

Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID.
Events on ports configured with PORT_EVENT6 are routed here.

0x5C

PORT_EVENT7

Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID.
Events on ports configured with PORT_EVENT7 are routed here.

0x5D

CRYPTO_RESULT_AVAIL_IRQ

CRYPTO result available interrupt event, the corresponding flag is found
here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by
CRYPTO:IRQSTAT.RESULT_AVAIL

0x5E

CRYPTO_DMA_DONE_IRQ

CRYPTO DMA input done event, the corresponding flag is
CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by
CRYPTO:IRQEN.DMA_IN_DONE

0x5F

RFC_IN_EV4

RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4

0x60

RFC_IN_EV5

RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5

0x61

RFC_IN_EV6

RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6

0x62

RFC_IN_EV7

RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7

0x63

WDT_NMI

WATCHDOG nonmaskable interrupt event, controlled by
WDT:CTL.INTTYPE

0x64

SWEV0

Software event 0, triggered by SWEV.SWEV0

0x65

SWEV1

Software event 1, triggered by SWEV.SWEV1

0x66

SWEV2

Software event 2, triggered by SWEV.SWEV2

0x67

SWEV3

Software event 3, triggered by SWEV.SWEV3

0x68

TRNG_IRQ

TRNG Interrupt event, controlled by TRNG:IRQEN.EN

242 Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

MCU Event Fabric

www.ti.com

Table 4-6. MCU Event Fabric Input Events (continued)
Event Number

Event Enumeration

Description

0x69

AUX_AON_WU_EV

AON wake-up event, corresponds flags are here
AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV.

0x6A

AUX_COMPA

AUX COMP A event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA.

0x6B

AUX_COMPB

AUX COMP B event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB.

0x6C

AUX_TDC_DONE

AUX TDC measurement done event, corresponds to the flag
AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status
AUX_TDC:STAT.DONE.

0x6D

AUX_TIMER0_EV

AUX TIMER 0 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV.

0x6E

AUX_TIMER1_EV

AUX TIMER 1 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV.

0x6F

AUX_SMPH_AUTOTAKE_DONE

Auto-take event from AUX semaphore, configured by
AUX_SMPH:AUTOTAKE.*.

0x70

AUX_ADC_DONE

AUX ADC done, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE

0x71

AUX_ADC_FIFO_ALMOST_FULL

AUX ADC FIFO watermark event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL

0x72

AUX_OBSMUX0

Loopback of OBSMUX0 through AUX, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0

0x73

AUX_ADC_IRQ

AUX ADC interrupt event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here
AUX_EVCTL:EVTOMCUFLAGS.ADC*

0x74

AUX_SW_DMABREQ

AUX observation loopback

0x75

AUX_DMASREQ

DMA single request event from AUX, configured by
AUX_EVCTL:DMACTL.*

0x76

AUX_DMABREQ

DMA burst request event from AUX, configured by
AUX_EVCTL:DMACTL.*

0x77

AON_RTC_UPD

RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN

0x78

CPU_HALTED

CPU halted

0x79

ALWAYS_ACTIVE

Always asserted (HIGH)

4.5.2 Event Subscribers
There are eleven subscribers for the MCU event fabric. Most of these subscribers are different peripherals
that must be configured differently according to the purpose of those specific peripherals. The following
five subscribers are not described in this chapter, but rather in each of the corresponding peripheral
chapters:
• Radio (see Chapter 23)
• General-Purpose Timers (see Chapter 14)
• Micro Direct Memory Access (µDMA) (see Chapter 12)
• Sensor Controllers with Digital and Analog Peripherals (AUX) (see Chapter 17)
• Inter-IC Sound (I2S) (see Chapter 22)
The following three subscribers are described as they are related to the system CPU and CPU interrupts:
• System CPU
• Nonmaskable Interrupt (NMI) to System CPU
• Freeze

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

243

MCU Event Fabric

www.ti.com

4.5.2.1

System CPU Table 4.2
Table 4-8 shows that the interrupts with vector number from 16 to 49 are sourced by the events routed in
the MCU event fabric to the system CPU. The event fabric routes all level interrupt events to the system
Event
CPU. The event/interrupt called "AON programmable 0" can be configured in the AON event fabric.
EVENT:CPUIRQSEL29 is a read-only register for routing within the MCU event fabric and cannot be
configured, but the input event within the AON event fabric going to this line can be configured. One
dynamic event/interrupt called "Dynamic Programmable Event" has the valid selections as seen in
Table 4-8. The EVENT:CPUIRQSEL29 register is used to configure the input.
See the EVENT:CPUIRQSEL30 register (see Section 4.7.2.31).

Table 4.8 is the AON source configurable events

4.5.2.2

NMI

EVENT:CPUIRQSEL30 is used to configure the input

The NMI subscriber has one nonconfigurable input that comes from the WDT. The read-only register
(CM3NMISEL0) shows the only valid input event.
4.5.2.3

Freeze

The CC26x0 and CC13x0 freeze subscriber passes the halted debug signal to peripherals such as the
General Purpose Timer, Sensor Controller with Digital and Analog Peripherals (AUX), Radio, and RTC.
When the system CPU halts, the connected peripherals that have freeze enabled also halt. The
programmable output can be set to static values of 0 or 1, and can also be set to pass the halted signal.
The possible events listed in Table 4-7 can be selected in the FRZSEL0 register.
Table 4-7. Freeze Subscriber Event Selection
Event Number

Event Enumeration

0x0

NONE

0x78

CPU_HALTED

0x79

ALWAYS_ACTIVE

NOTE: When freeze is asserted, RTC stops incrementing the main counter, but the update event
from RTC (goes to RF core and AON event fabric) does not stop. The update event is a
down division of SCLK_LF and has no dependency on the main counter. So in practice,
when you are halting the CPU for debugging, there is no way to stop these update events to
RFC.

244

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AON Events

www.ti.com

4.6

AON Events
Table 4-8. AON Events
Event No.

Name

Description

0x0 to 0x1F

PAD0 to PAD31

Edge detect on PADn, n=0..31

0x20

PAD

Edge detect on any PAD

0x23 to 0x25

RTC_CH0 to RTC_CH2

RTC channel n event, n=0..2

0x26 to 0x28

RTC_CH0_DLY to RTC_CH2_DLY

RTC channel n - delayed event, n=0..2

0x29

RTC_COMB_DLY

RTC combined delayed event

0x2A

RTC_UPD

RTC Update Tick

0x2B

JTAG

JTAG generated event

0x2C to 0x2E

AUX_SWEV0 to AUX_SWEV2

AUX Software triggered event #n, n=0..2

0x2F

AUX_COMPA

Comparator A triggered

0x30

AUX_COMPB

Comparator B triggered

0x31

AUX_ADC_DONE

ADC conversion completed

0x32

AUX_TDC_DONE

TDC completed or timed out

0x33 to 0x34

AUX_TIMER0_EV to AUX_TIMER1_EV

AUX Timer n Event, n=0..1

0x35

BATMON_TEMP

BATMON temperature update event

0x36

BATMON_VOLT

BATMON voltage update event

0x37

AUX_COMPB_ASYNC

Comparator B triggered

0x38

AUX_COMPB_ASYNC_N

Comparator B not triggered

0x3F

NONE

No event

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

245

Interrupts and Events Registers

4.7

www.ti.com

Interrupts and Events Registers

4.7.1 AON_EVENT Registers
Table 4-9 lists the memory-mapped registers for the AON_EVENT. All register offset addresses not listed
in Table 4-9 should be considered as reserved locations and the register contents should not be modified.
Table 4-9. AON_EVENT Registers
Offset

246

Acronym

MCUWUSEL

Wake-up Selector For MCU

Section 4.7.1.1

AUXWUSEL

Wake-up Selector For AUX

Section 4.7.1.2

EVTOMCUSEL

Event Selector For MCU Event Fabric

Section 4.7.1.3

RTCSEL

RTC Capture Event Selector For AON_RTC

Section 4.7.1.4

Interrupts and Events

Section

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.1.1

MCUWUSEL Register (Offset = 0h) [reset = 3F3F3F3Fh]

MCUWUSEL is shown in Figure 4-6 and described in Table 4-10.
Return to Summary Table.
Wake-up Selector For MCU
This register contains pointers to 4 events which are routed to AON_WUC as wakeup sources for MCU.
AON_WUC will start a wakeup sequence for the MCU domain when either of the 4 selected events are
asserted. A wakeup sequence will guarantee that the MCU power switches are turned on, LDO resources
are available and SCLK_HF is available and selected as clock source for MCU.
Note: It is recommended ( or required when AON_WUC:MCUCLK.PWR_DWN_SRC=NONE) to also setup
a wakeup event here before MCU is requesting powerdown. ( PRCM requests uLDO, see conditions in
PRCM:VDCTL.ULDO ) as it will speed up the wakeup procedure.
Figure 4-6. MCUWUSEL Register
31

RESERVED
R-0h
23

RESERVED
R-0h
15

WU2_EV
R/W-3Fh
14

RESERVED
R-0h
7

26
WU3_EV
R/W-3Fh

WU1_EV
R/W-3Fh
6

RESERVED
R-0h

3
WU0_EV
R/W-3Fh

Table 4-10. MCUWUSEL Register Field Descriptions
Bit
31-30

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

247

Interrupts and Events Registers

www.ti.com

Table 4-10. MCUWUSEL Register Field Descriptions (continued)
Bit
29-24

248

Field

Type

Reset

Description

WU3_EV

R/W

3Fh

MCU Wakeup Source #3
AON Event Source selecting 1 of 4 events routed to AON_WUC for
waking up the MCU domain from Power Off or Power Down.
Note:
0h = Edge detect on PAD0
1h = Edge detect on PAD1
2h = Edge detect on PAD2
3h = Edge detect on PAD3
4h = Edge detect on PAD4
5h = Edge detect on PAD5
6h = Edge detect on PAD6
7h = Edge detect on PAD7
8h = Edge detect on PAD8
9h = Edge detect on PAD9
Ah = Edge detect on PAD10
Bh = Edge detect on PAD11
Ch = Edge detect on PAD12
Dh = Edge detect on PAD13
Eh = Edge detect on PAD14
Fh = Edge detect on PAD15
10h = Edge detect on PAD16
11h = Edge detect on PAD17
12h = Edge detect on PAD18
13h = Edge detect on PAD19
14h = Edge detect on PAD20
15h = Edge detect on PAD21
16h = Edge detect on PAD22
17h = Edge detect on PAD23
18h = Edge detect on PAD24
19h = Edge detect on PAD25
1Ah = Edge detect on PAD26
1Bh = Edge detect on PAD27
1Ch = Edge detect on PAD28
1Dh = Edge detect on PAD29
1Eh = Edge detect on PAD30
1Fh = Edge detect on PAD31
20h = Edge detect on any PAD
23h = RTC channel 0 event
24h = RTC channel 1 event
25h = RTC channel 2 event
26h = RTC channel 0 - delayed event
27h = RTC channel 1 - delayed event
28h = RTC channel 2 - delayed event
29h = RTC combined delayed event
2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value
every 32 kHz clock period)
2Bh = JTAG generated event
2Ch = AUX Software triggered event #0. Triggered by
AUX_EVCTL:SWEVSET.SWEV0
2Dh = AUX Software triggered event #1. Triggered by
AUX_EVCTL:SWEVSET.SWEV1
2Eh = AUX Software triggered event #2. Triggered by
AUX_EVCTL:SWEVSET.SWEV2
2Fh = Comparator A triggered
30h = Comparator B triggered
31h = ADC conversion completed
32h = TDC completed or timed out

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-10. MCUWUSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
33h = AUX Timer 0 Event
34h = AUX Timer 1 Event
35h = BATMON temperature update event
36h = BATMON voltage update event
37h = Comparator B triggered. Asynchronous signal directly from the
AUX Comparator B as opposed to AUX_COMPB which is
synchronized in AUX
38h = Comparator B not triggered. Asynchronous signal directly from
AUX Comparator B (inverted) as opposed to AUX_COMPB which is
synchronized in AUX
3Fh = No event, always low

23-22

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

21-16

WU2_EV

R/W

3Fh

MCU Wakeup Source #2
AON Event Source selecting 1 of 4 events routed to AON_WUC for
waking up the MCU domain from Power Off or Power Down.
Note:
0h = Edge detect on PAD0
1h = Edge detect on PAD1
2h = Edge detect on PAD2
3h = Edge detect on PAD3
4h = Edge detect on PAD4
5h = Edge detect on PAD5
6h = Edge detect on PAD6
7h = Edge detect on PAD7
8h = Edge detect on PAD8
9h = Edge detect on PAD9
Ah = Edge detect on PAD10
Bh = Edge detect on PAD11
Ch = Edge detect on PAD12
Dh = Edge detect on PAD13
Eh = Edge detect on PAD14
Fh = Edge detect on PAD15
10h = Edge detect on PAD16
11h = Edge detect on PAD17
12h = Edge detect on PAD18
13h = Edge detect on PAD19
14h = Edge detect on PAD20
15h = Edge detect on PAD21
16h = Edge detect on PAD22
17h = Edge detect on PAD23
18h = Edge detect on PAD24
19h = Edge detect on PAD25
1Ah = Edge detect on PAD26
1Bh = Edge detect on PAD27
1Ch = Edge detect on PAD28
1Dh = Edge detect on PAD29
1Eh = Edge detect on PAD30
1Fh = Edge detect on PAD31
20h = Edge detect on any PAD
23h = RTC channel 0 event
24h = RTC channel 1 event
25h = RTC channel 2 event
26h = RTC channel 0 - delayed event
27h = RTC channel 1 - delayed event
28h = RTC channel 2 - delayed event
29h = RTC combined delayed event

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

249

Interrupts and Events Registers

www.ti.com

Table 4-10. MCUWUSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value
every 32 kHz clock period)
2Bh = JTAG generated event
2Ch = AUX Software triggered event #0. Triggered by
AUX_EVCTL:SWEVSET.SWEV0
2Dh = AUX Software triggered event #1. Triggered by
AUX_EVCTL:SWEVSET.SWEV1
2Eh = AUX Software triggered event #2. Triggered by
AUX_EVCTL:SWEVSET.SWEV2
2Fh = Comparator A triggered
30h = Comparator B triggered
31h = ADC conversion completed
32h = TDC completed or timed out
33h = AUX Timer 0 Event
34h = AUX Timer 1 Event
35h = BATMON temperature update event
36h = BATMON voltage update event
37h = Comparator B triggered. Asynchronous signal directly from the
AUX Comparator B as opposed to AUX_COMPB which is
synchronized in AUX
38h = Comparator B not triggered. Asynchronous signal directly from
AUX Comparator B (inverted) as opposed to AUX_COMPB which is
synchronized in AUX
3Fh = No event, always low

15-14

250

RESERVED

Interrupts and Events

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-10. MCUWUSEL Register Field Descriptions (continued)
Bit
13-8

Field

Type

Reset

Description

WU1_EV

R/W

3Fh

MCU Wakeup Source #1
AON Event Source selecting 1 of 4 events routed to AON_WUC for
waking up the MCU domain from Power Off or Power Down.
Note:
0h = Edge detect on PAD0
1h = Edge detect on PAD1
2h = Edge detect on PAD2
3h = Edge detect on PAD3
4h = Edge detect on PAD4
5h = Edge detect on PAD5
6h = Edge detect on PAD6
7h = Edge detect on PAD7
8h = Edge detect on PAD8
9h = Edge detect on PAD9
Ah = Edge detect on PAD10
Bh = Edge detect on PAD11
Ch = Edge detect on PAD12
Dh = Edge detect on PAD13
Eh = Edge detect on PAD14
Fh = Edge detect on PAD15
10h = Edge detect on PAD16
11h = Edge detect on PAD17
12h = Edge detect on PAD18
13h = Edge detect on PAD19
14h = Edge detect on PAD20
15h = Edge detect on PAD21
16h = Edge detect on PAD22
17h = Edge detect on PAD23
18h = Edge detect on PAD24
19h = Edge detect on PAD25
1Ah = Edge detect on PAD26
1Bh = Edge detect on PAD27
1Ch = Edge detect on PAD28
1Dh = Edge detect on PAD29
1Eh = Edge detect on PAD30
1Fh = Edge detect on PAD31
20h = Edge detect on any PAD
23h = RTC channel 0 event
24h = RTC channel 1 event
25h = RTC channel 2 event
26h = RTC channel 0 - delayed event
27h = RTC channel 1 - delayed event
28h = RTC channel 2 - delayed event
29h = RTC combined delayed event
2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value
every 32 kHz clock period)
2Bh = JTAG generated event
2Ch = AUX Software triggered event #0. Triggered by
AUX_EVCTL:SWEVSET.SWEV0
2Dh = AUX Software triggered event #1. Triggered by
AUX_EVCTL:SWEVSET.SWEV1
2Eh = AUX Software triggered event #2. Triggered by
AUX_EVCTL:SWEVSET.SWEV2
2Fh = Comparator A triggered
30h = Comparator B triggered
31h = ADC conversion completed
32h = TDC completed or timed out

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

251

Interrupts and Events Registers

www.ti.com

Table 4-10. MCUWUSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

252

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

5-0

WU0_EV

R/W

3Fh

MCU Wakeup Source #0
AON Event Source selecting 1 of 4 events routed to AON_WUC for
waking up the MCU domain from Power Off or Power Down.
Note:
0h = Edge detect on PAD0
1h = Edge detect on PAD1
2h = Edge detect on PAD2
3h = Edge detect on PAD3
4h = Edge detect on PAD4
5h = Edge detect on PAD5
6h = Edge detect on PAD6
7h = Edge detect on PAD7
8h = Edge detect on PAD8
9h = Edge detect on PAD9
Ah = Edge detect on PAD10
Bh = Edge detect on PAD11
Ch = Edge detect on PAD12
Dh = Edge detect on PAD13
Eh = Edge detect on PAD14
Fh = Edge detect on PAD15
10h = Edge detect on PAD16
11h = Edge detect on PAD17
12h = Edge detect on PAD18
13h = Edge detect on PAD19
14h = Edge detect on PAD20
15h = Edge detect on PAD21
16h = Edge detect on PAD22
17h = Edge detect on PAD23
18h = Edge detect on PAD24
19h = Edge detect on PAD25
1Ah = Edge detect on PAD26
1Bh = Edge detect on PAD27
1Ch = Edge detect on PAD28
1Dh = Edge detect on PAD29
1Eh = Edge detect on PAD30
1Fh = Edge detect on PAD31
20h = Edge detect on any PAD
23h = RTC channel 0 event
24h = RTC channel 1 event
25h = RTC channel 2 event
26h = RTC channel 0 - delayed event
27h = RTC channel 1 - delayed event
28h = RTC channel 2 - delayed event
29h = RTC combined delayed event

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-10. MCUWUSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

253

Interrupts and Events Registers

4.7.1.2

www.ti.com

AUXWUSEL Register (Offset = 4h) [reset = 003F3F3Fh]

AUXWUSEL is shown in Figure 4-7 and described in Table 4-11.
Return to Summary Table.
Wake-up Selector For AUX
This register contains pointers to 3 events which are routed to AON_WUC as wakeup sources for AUX.
AON_WUC will start a wakeup sequence for the AUX domain when either of the 3 selected events are
asserted. A wakeup sequence will guarantee that the AUX power switches are turned on, LDO resources
are available and SCLK_HF is available and selected as clock source for AUX.
Note: It is recommended ( or required when AON_WUC:AUXCLK.PWR_DWN_SRC=NONE) to also setup
a wakeup event here before AUX is requesting powerdown. ( AUX_WUC:PWRDWNREQ.REQ is
asserted] ) as it will speed up the wakeup procedure.
Figure 4-7. AUXWUSEL Register
31

RESERVED
R-0h
23

RESERVED
R-0h
15

WU2_EV
R/W-3Fh
14

RESERVED
R-0h
7

WU1_EV
R/W-3Fh
6

RESERVED
R-0h

3
WU0_EV
R/W-3Fh

Table 4-11. AUXWUSEL Register Field Descriptions
Bit
31-22

254

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-11. AUXWUSEL Register Field Descriptions (continued)
Bit
21-16

Field

Type

Reset

Description

WU2_EV

R/W

3Fh

AUX Wakeup Source #2
AON Event Source selecting 1 of 3 events routed to AON_WUC for
waking up the AUX domain from Power Off or Power Down.
Note:
0h = Edge detect on PAD0
1h = Edge detect on PAD1
2h = Edge detect on PAD2
3h = Edge detect on PAD3
4h = Edge detect on PAD4
5h = Edge detect on PAD5
6h = Edge detect on PAD6
7h = Edge detect on PAD7
8h = Edge detect on PAD8
9h = Edge detect on PAD9
Ah = Edge detect on PAD10
Bh = Edge detect on PAD11
Ch = Edge detect on PAD12
Dh = Edge detect on PAD13
Eh = Edge detect on PAD14
Fh = Edge detect on PAD15
10h = Edge detect on PAD16
11h = Edge detect on PAD17
12h = Edge detect on PAD18
13h = Edge detect on PAD19
14h = Edge detect on PAD20
15h = Edge detect on PAD21
16h = Edge detect on PAD22
17h = Edge detect on PAD23
18h = Edge detect on PAD24
19h = Edge detect on PAD25
1Ah = Edge detect on PAD26
1Bh = Edge detect on PAD27
1Ch = Edge detect on PAD28
1Dh = Edge detect on PAD29
1Eh = Edge detect on PAD30
1Fh = Edge detect on PAD31
20h = Edge detect on any PAD
23h = RTC channel 0 event
24h = RTC channel 1 event
25h = RTC channel 2 event
26h = RTC channel 0 - delayed event
27h = RTC channel 1 - delayed event
28h = RTC channel 2 - delayed event
29h = RTC combined delayed event
2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value
every 32 kHz clock period)
2Bh = JTAG generated event
2Ch = AUX Software triggered event #0. Triggered by
AUX_EVCTL:SWEVSET.SWEV0
2Dh = AUX Software triggered event #1. Triggered by
AUX_EVCTL:SWEVSET.SWEV1
2Eh = AUX Software triggered event #2. Triggered by
AUX_EVCTL:SWEVSET.SWEV2
2Fh = Comparator A triggered
30h = Comparator B triggered
31h = ADC conversion completed
32h = TDC completed or timed out

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

255

Interrupts and Events Registers

www.ti.com

Table 4-11. AUXWUSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

256

15-14

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

13-8

WU1_EV

R/W

3Fh

AUX Wakeup Source #1
AON Event Source selecting 1 of 3 events routed to AON_WUC for
waking up the AUX domain from Power Off or Power Down.
Note:
0h = Edge detect on PAD0
1h = Edge detect on PAD1
2h = Edge detect on PAD2
3h = Edge detect on PAD3
4h = Edge detect on PAD4
5h = Edge detect on PAD5
6h = Edge detect on PAD6
7h = Edge detect on PAD7
8h = Edge detect on PAD8
9h = Edge detect on PAD9
Ah = Edge detect on PAD10
Bh = Edge detect on PAD11
Ch = Edge detect on PAD12
Dh = Edge detect on PAD13
Eh = Edge detect on PAD14
Fh = Edge detect on PAD15
10h = Edge detect on PAD16
11h = Edge detect on PAD17
12h = Edge detect on PAD18
13h = Edge detect on PAD19
14h = Edge detect on PAD20
15h = Edge detect on PAD21
16h = Edge detect on PAD22
17h = Edge detect on PAD23
18h = Edge detect on PAD24
19h = Edge detect on PAD25
1Ah = Edge detect on PAD26
1Bh = Edge detect on PAD27
1Ch = Edge detect on PAD28
1Dh = Edge detect on PAD29
1Eh = Edge detect on PAD30
1Fh = Edge detect on PAD31
20h = Edge detect on any PAD
23h = RTC channel 0 event
24h = RTC channel 1 event
25h = RTC channel 2 event
26h = RTC channel 0 - delayed event
27h = RTC channel 1 - delayed event
28h = RTC channel 2 - delayed event
29h = RTC combined delayed event

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-11. AUXWUSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

7-6

RESERVED

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupts and Events

257

Interrupts and Events Registers

www.ti.com

Table 4-11. AUXWUSEL Register Field Descriptions (continued)

258

Bit

Field

Type

Reset

Description

5-0

WU0_EV

R/W

3Fh

AUX Wakeup Source #0
AON Event Source selecting 1 of 3 events routed to AON_WUC for
waking up the AUX domain from Power Off or Power Down.
Note:
0h = Edge detect on PAD0
1h = Edge detect on PAD1
2h = Edge detect on PAD2
3h = Edge detect on PAD3
4h = Edge detect on PAD4
5h = Edge detect on PAD5
6h = Edge detect on PAD6
7h = Edge detect on PAD7
8h = Edge detect on PAD8
9h = Edge detect on PAD9
Ah = Edge detect on PAD10
Bh = Edge detect on PAD11
Ch = Edge detect on PAD12
Dh = Edge detect on PAD13
Eh = Edge detect on PAD14
Fh = Edge detect on PAD15
10h = Edge detect on PAD16
11h = Edge detect on PAD17
12h = Edge detect on PAD18
13h = Edge detect on PAD19
14h = Edge detect on PAD20
15h = Edge detect on PAD21
16h = Edge detect on PAD22
17h = Edge detect on PAD23
18h = Edge detect on PAD24
19h = Edge detect on PAD25
1Ah = Edge detect on PAD26
1Bh = Edge detect on PAD27
1Ch = Edge detect on PAD28
1Dh = Edge detect on PAD29
1Eh = Edge detect on PAD30
1Fh = Edge detect on PAD31
20h = Edge detect on any PAD
23h = RTC channel 0 event
24h = RTC channel 1 event
25h = RTC channel 2 event
26h = RTC channel 0 - delayed event
27h = RTC channel 1 - delayed event
28h = RTC channel 2 - delayed event
29h = RTC combined delayed event
2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value
every 32 kHz clock period)
2Bh = JTAG generated event
2Ch = AUX Software triggered event #0. Triggered by
AUX_EVCTL:SWEVSET.SWEV0
2Dh = AUX Software triggered event #1. Triggered by
AUX_EVCTL:SWEVSET.SWEV1
2Eh = AUX Software triggered event #2. Triggered by
AUX_EVCTL:SWEVSET.SWEV2
2Fh = Comparator A triggered
30h = Comparator B triggered
31h = ADC conversion completed
32h = TDC completed or timed out

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-11. AUXWUSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

259

Interrupts and Events Registers

4.7.1.3

www.ti.com

EVTOMCUSEL Register (Offset = 8h) [reset = 002B2B2Bh]

EVTOMCUSEL is shown in Figure 4-8 and described in Table 4-12.
Return to Summary Table.
Event Selector For MCU Event Fabric
This register contains pointers for 3 AON events that are routed to the MCU Event Fabric EVENT
Figure 4-8. EVTOMCUSEL Register
31

RESERVED
R-0h
23

19
18
AON_PROG2_EV
R/W-2Bh

11
10
AON_PROG1_EV
R/W-2Bh

3
2
AON_PROG0_EV
R/W-2Bh

RESERVED
R-0h
15
RESERVED
R-0h
7
RESERVED
R-0h

Table 4-12. EVTOMCUSEL Register Field Descriptions
Bit
31-22

260

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-12. EVTOMCUSEL Register Field Descriptions (continued)
Bit
21-16

Field

Type

Reset

Description

AON_PROG2_EV

R/W

2Bh

Event selector for AON_PROG2 event.
AON Event Source id# selecting event routed to EVENT as
AON_PROG2 event.
0h = Edge detect on PAD0
1h = Edge detect on PAD1
2h = Edge detect on PAD2
3h = Edge detect on PAD3
4h = Edge detect on PAD4
5h = Edge detect on PAD5
6h = Edge detect on PAD6
7h = Edge detect on PAD7
8h = Edge detect on PAD8
9h = Edge detect on PAD9
Ah = Edge detect on PAD10
Bh = Edge detect on PAD11
Ch = Edge detect on PAD12
Dh = Edge detect on PAD13
Eh = Edge detect on PAD14
Fh = Edge detect on PAD15
10h = Edge detect on PAD16
11h = Edge detect on PAD17
12h = Edge detect on PAD18
13h = Edge detect on PAD19
14h = Edge detect on PAD20
15h = Edge detect on PAD21
16h = Edge detect on PAD22
17h = Edge detect on PAD23
18h = Edge detect on PAD24
19h = Edge detect on PAD25
1Ah = Edge detect on PAD26
1Bh = Edge detect on PAD27
1Ch = Edge detect on PAD28
1Dh = Edge detect on PAD29
1Eh = Edge detect on PAD30
1Fh = Edge detect on PAD31
20h = Edge detect on any PAD
23h = RTC channel 0 event
24h = RTC channel 1 event
25h = RTC channel 2 event
26h = RTC channel 0 - delayed event
27h = RTC channel 1 - delayed event
28h = RTC channel 2 - delayed event
29h = RTC combined delayed event
2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value
every 32 kHz clock period)
2Bh = JTAG generated event
2Ch = AUX Software triggered event #0. Triggered by
AUX_EVCTL:SWEVSET.SWEV0
2Dh = AUX Software triggered event #1. Triggered by
AUX_EVCTL:SWEVSET.SWEV1
2Eh = AUX Software triggered event #2. Triggered by
AUX_EVCTL:SWEVSET.SWEV2
2Fh = Comparator A triggered
30h = Comparator B triggered
31h = ADC conversion completed
32h = TDC completed or timed out
33h = AUX Timer 0 Event

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

261

Interrupts and Events Registers

www.ti.com

Table 4-12. EVTOMCUSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
34h = AUX Timer 1 Event
35h = BATMON temperature update event
36h = BATMON voltage update event
37h = Comparator B triggered. Asynchronous signal directly from the
AUX Comparator B as opposed to AUX_COMPB which is
synchronized in AUX
38h = Comparator B not triggered. Asynchronous signal directly from
AUX Comparator B (inverted) as opposed to AUX_COMPB which is
synchronized in AUX
3Fh = No event, always low

262

15-14

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

13-8

AON_PROG1_EV

R/W

2Bh

Event selector for AON_PROG1 event.
AON Event Source id# selecting event routed to EVENT as
AON_PROG1 event.
0h = Edge detect on PAD0
1h = Edge detect on PAD1
2h = Edge detect on PAD2
3h = Edge detect on PAD3
4h = Edge detect on PAD4
5h = Edge detect on PAD5
6h = Edge detect on PAD6
7h = Edge detect on PAD7
8h = Edge detect on PAD8
9h = Edge detect on PAD9
Ah = Edge detect on PAD10
Bh = Edge detect on PAD11
Ch = Edge detect on PAD12
Dh = Edge detect on PAD13
Eh = Edge detect on PAD14
Fh = Edge detect on PAD15
10h = Edge detect on PAD16
11h = Edge detect on PAD17
12h = Edge detect on PAD18
13h = Edge detect on PAD19
14h = Edge detect on PAD20
15h = Edge detect on PAD21
16h = Edge detect on PAD22
17h = Edge detect on PAD23
18h = Edge detect on PAD24
19h = Edge detect on PAD25
1Ah = Edge detect on PAD26
1Bh = Edge detect on PAD27
1Ch = Edge detect on PAD28
1Dh = Edge detect on PAD29
1Eh = Edge detect on PAD30
1Fh = Edge detect on PAD31
20h = Edge detect on any PAD
23h = RTC channel 0 event
24h = RTC channel 1 event
25h = RTC channel 2 event
26h = RTC channel 0 - delayed event
27h = RTC channel 1 - delayed event
28h = RTC channel 2 - delayed event
29h = RTC combined delayed event
2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value
every 32 kHz clock period)

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-12. EVTOMCUSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
2Bh = JTAG generated event
2Ch = AUX Software triggered event #0. Triggered by
AUX_EVCTL:SWEVSET.SWEV0
2Dh = AUX Software triggered event #1. Triggered by
AUX_EVCTL:SWEVSET.SWEV1
2Eh = AUX Software triggered event #2. Triggered by
AUX_EVCTL:SWEVSET.SWEV2
2Fh = Comparator A triggered
30h = Comparator B triggered
31h = ADC conversion completed
32h = TDC completed or timed out
33h = AUX Timer 0 Event
34h = AUX Timer 1 Event
35h = BATMON temperature update event
36h = BATMON voltage update event
37h = Comparator B triggered. Asynchronous signal directly from the
AUX Comparator B as opposed to AUX_COMPB which is
synchronized in AUX
38h = Comparator B not triggered. Asynchronous signal directly from
AUX Comparator B (inverted) as opposed to AUX_COMPB which is
synchronized in AUX
3Fh = No event, always low

7-6

RESERVED

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupts and Events

263

Interrupts and Events Registers

www.ti.com

Table 4-12. EVTOMCUSEL Register Field Descriptions (continued)

264

Bit

Field

Type

Reset

Description

5-0

AON_PROG0_EV

R/W

2Bh

Event selector for AON_PROG0 event.
AON Event Source id# selecting event routed to EVENT as
AON_PROG0 event.
0h = Edge detect on PAD0
1h = Edge detect on PAD1
2h = Edge detect on PAD2
3h = Edge detect on PAD3
4h = Edge detect on PAD4
5h = Edge detect on PAD5
6h = Edge detect on PAD6
7h = Edge detect on PAD7
8h = Edge detect on PAD8
9h = Edge detect on PAD9
Ah = Edge detect on PAD10
Bh = Edge detect on PAD11
Ch = Edge detect on PAD12
Dh = Edge detect on PAD13
Eh = Edge detect on PAD14
Fh = Edge detect on PAD15
10h = Edge detect on PAD16
11h = Edge detect on PAD17
12h = Edge detect on PAD18
13h = Edge detect on PAD19
14h = Edge detect on PAD20
15h = Edge detect on PAD21
16h = Edge detect on PAD22
17h = Edge detect on PAD23
18h = Edge detect on PAD24
19h = Edge detect on PAD25
1Ah = Edge detect on PAD26
1Bh = Edge detect on PAD27
1Ch = Edge detect on PAD28
1Dh = Edge detect on PAD29
1Eh = Edge detect on PAD30
1Fh = Edge detect on PAD31
20h = Edge detect on any PAD
23h = RTC channel 0 event
24h = RTC channel 1 event
25h = RTC channel 2 event
26h = RTC channel 0 - delayed event
27h = RTC channel 1 - delayed event
28h = RTC channel 2 - delayed event
29h = RTC combined delayed event
2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value
every 32 kHz clock period)
2Bh = JTAG generated event
2Ch = AUX Software triggered event #0. Triggered by
AUX_EVCTL:SWEVSET.SWEV0
2Dh = AUX Software triggered event #1. Triggered by
AUX_EVCTL:SWEVSET.SWEV1
2Eh = AUX Software triggered event #2. Triggered by
AUX_EVCTL:SWEVSET.SWEV2
2Fh = Comparator A triggered
30h = Comparator B triggered
31h = ADC conversion completed
32h = TDC completed or timed out
33h = AUX Timer 0 Event

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-12. EVTOMCUSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

265

Interrupts and Events Registers

4.7.1.4

www.ti.com

RTCSEL Register (Offset = Ch) [reset = 3Fh]

RTCSEL is shown in Figure 4-9 and described in Table 4-13.
Return to Summary Table.
RTC Capture Event Selector For AON_RTC
This register contains a pointer to select an AON event for RTC capture. Please refer to
AON_RTC:CH1CAPT
Figure 4-9. RTCSEL Register
31

11
10
RESERVED
R-0h

24
23
RESERVED
R-0h
8

3
2
1
RTC_CH1_CAPT_EV
R/W-3Fh

Table 4-13. RTCSEL Register Field Descriptions
Bit
31-6

266

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-13. RTCSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

RTC_CH1_CAPT_EV

R/W

3Fh

AON Event Source id# for RTCSEL event which is fed to AON_RTC.
Please refer to AON_RTC:CH1CAPT
0h = Edge detect on PAD0
1h = Edge detect on PAD1
2h = Edge detect on PAD2
3h = Edge detect on PAD3
4h = Edge detect on PAD4
5h = Edge detect on PAD5
6h = Edge detect on PAD6
7h = Edge detect on PAD7
8h = Edge detect on PAD8
9h = Edge detect on PAD9
Ah = Edge detect on PAD10
Bh = Edge detect on PAD11
Ch = Edge detect on PAD12
Dh = Edge detect on PAD13
Eh = Edge detect on PAD14
Fh = Edge detect on PAD15
10h = Edge detect on PAD16
11h = Edge detect on PAD17
12h = Edge detect on PAD18
13h = Edge detect on PAD19
14h = Edge detect on PAD20
15h = Edge detect on PAD21
16h = Edge detect on PAD22
17h = Edge detect on PAD23
18h = Edge detect on PAD24
19h = Edge detect on PAD25
1Ah = Edge detect on PAD26
1Bh = Edge detect on PAD27
1Ch = Edge detect on PAD28
1Dh = Edge detect on PAD29
1Eh = Edge detect on PAD30
1Fh = Edge detect on PAD31
20h = Edge detect on any PAD
23h = RTC channel 0 event
24h = RTC channel 1 event
25h = RTC channel 2 event
26h = RTC channel 0 - delayed event
27h = RTC channel 1 - delayed event
28h = RTC channel 2 - delayed event
29h = RTC combined delayed event
2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value
every 32 kHz clock period)
2Bh = JTAG generated event
2Ch = AUX Software triggered event #0. Triggered by
AUX_EVCTL:SWEVSET.SWEV0
2Dh = AUX Software triggered event #1. Triggered by
AUX_EVCTL:SWEVSET.SWEV1
2Eh = AUX Software triggered event #2. Triggered by
AUX_EVCTL:SWEVSET.SWEV2
2Fh = Comparator A triggered
30h = Comparator B triggered
31h = ADC conversion completed
32h = TDC completed or timed out
33h = AUX Timer 0 Event
34h = AUX Timer 1 Event

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

267

Interrupts and Events Registers

www.ti.com

Table 4-13. RTCSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
35h = BATMON temperature update event
36h = BATMON voltage update event
37h = Comparator B triggered. Asynchronous signal directly from the
AUX Comparator B as opposed to AUX_COMPB which is
synchronized in AUX
38h = Comparator B not triggered. Asynchronous signal directly from
AUX Comparator B (inverted) as opposed to AUX_COMPB which is
synchronized in AUX
3Fh = No event, always low

268

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2 EVENT Registers
Table 4-14 lists the memory-mapped registers for the EVENT. All register offset addresses not listed in
Table 4-14 should be considered as reserved locations and the register contents should not be modified.
Table 4-14. EVENT Registers
Offset

Acronym

CPUIRQSEL0

Output Selection for CPU Interrupt 0

Section 4.7.2.1

Section

CPUIRQSEL1

Output Selection for CPU Interrupt 1

Section 4.7.2.2

CPUIRQSEL2

Output Selection for CPU Interrupt 2

Section 4.7.2.3

CPUIRQSEL3

Output Selection for CPU Interrupt 3

Section 4.7.2.4

10h

CPUIRQSEL4

Output Selection for CPU Interrupt 4

Section 4.7.2.5

14h

CPUIRQSEL5

Output Selection for CPU Interrupt 5

Section 4.7.2.6

18h

CPUIRQSEL6

Output Selection for CPU Interrupt 6

Section 4.7.2.7

1Ch

CPUIRQSEL7

Output Selection for CPU Interrupt 7

Section 4.7.2.8

20h

CPUIRQSEL8

Output Selection for CPU Interrupt 8

Section 4.7.2.9

24h

CPUIRQSEL9

Output Selection for CPU Interrupt 9

Section 4.7.2.10

28h

CPUIRQSEL10

Output Selection for CPU Interrupt 10

Section 4.7.2.11

2Ch

CPUIRQSEL11

Output Selection for CPU Interrupt 11

Section 4.7.2.12

30h

CPUIRQSEL12

Output Selection for CPU Interrupt 12

Section 4.7.2.13

34h

CPUIRQSEL13

Output Selection for CPU Interrupt 13

Section 4.7.2.14

38h

CPUIRQSEL14

Output Selection for CPU Interrupt 14

Section 4.7.2.15

3Ch

CPUIRQSEL15

Output Selection for CPU Interrupt 15

Section 4.7.2.16

40h

CPUIRQSEL16

Output Selection for CPU Interrupt 16

Section 4.7.2.17

44h

CPUIRQSEL17

Output Selection for CPU Interrupt 17

Section 4.7.2.18

48h

CPUIRQSEL18

Output Selection for CPU Interrupt 18

Section 4.7.2.19

4Ch

CPUIRQSEL19

Output Selection for CPU Interrupt 19

Section 4.7.2.20

50h

CPUIRQSEL20

Output Selection for CPU Interrupt 20

Section 4.7.2.21

54h

CPUIRQSEL21

Output Selection for CPU Interrupt 21

Section 4.7.2.22

58h

CPUIRQSEL22

Output Selection for CPU Interrupt 22

Section 4.7.2.23

5Ch

CPUIRQSEL23

Output Selection for CPU Interrupt 23

Section 4.7.2.24

60h

CPUIRQSEL24

Output Selection for CPU Interrupt 24

Section 4.7.2.25

64h

CPUIRQSEL25

Output Selection for CPU Interrupt 25

Section 4.7.2.26

68h

CPUIRQSEL26

Output Selection for CPU Interrupt 26

Section 4.7.2.27

6Ch

CPUIRQSEL27

Output Selection for CPU Interrupt 27

Section 4.7.2.28

70h

CPUIRQSEL28

Output Selection for CPU Interrupt 28

Section 4.7.2.29

74h

CPUIRQSEL29

Output Selection for CPU Interrupt 29

Section 4.7.2.30

78h

CPUIRQSEL30

Output Selection for CPU Interrupt 30

Section 4.7.2.31

7Ch

CPUIRQSEL31

Output Selection for CPU Interrupt 31

Section 4.7.2.32

80h

CPUIRQSEL32

Output Selection for CPU Interrupt 32

Section 4.7.2.33

84h

CPUIRQSEL33

Output Selection for CPU Interrupt 33

Section 4.7.2.34

100h

RFCSEL0

Output Selection for RFC Event 0

Section 4.7.2.35

104h

RFCSEL1

Output Selection for RFC Event 1

Section 4.7.2.36

108h

RFCSEL2

Output Selection for RFC Event 2

Section 4.7.2.37

10Ch

RFCSEL3

Output Selection for RFC Event 3

Section 4.7.2.38

110h

RFCSEL4

Output Selection for RFC Event 4

Section 4.7.2.39

114h

RFCSEL5

Output Selection for RFC Event 5

Section 4.7.2.40

118h

RFCSEL6

Output Selection for RFC Event 6

Section 4.7.2.41

11Ch

RFCSEL7

Output Selection for RFC Event 7

Section 4.7.2.42

120h

RFCSEL8

Output Selection for RFC Event 8

Section 4.7.2.43

124h

RFCSEL9

Output Selection for RFC Event 9

Section 4.7.2.44

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

269

Interrupts and Events Registers

www.ti.com

Table 4-14. EVENT Registers (continued)
Offset

270

Acronym

200h

GPT0ACAPTSEL

Output Selection for GPT0 0

Section 4.7.2.45

Section

204h

GPT0BCAPTSEL

Output Selection for GPT0 1

Section 4.7.2.46

300h

GPT1ACAPTSEL

Output Selection for GPT1 0

Section 4.7.2.47

304h

GPT1BCAPTSEL

Output Selection for GPT1 1

Section 4.7.2.48

400h

GPT2ACAPTSEL

Output Selection for GPT2 0

Section 4.7.2.49

404h

GPT2BCAPTSEL

Output Selection for GPT2 1

Section 4.7.2.50

508h

UDMACH1SSEL

Output Selection for DMA Channel 1 SREQ

Section 4.7.2.51

50Ch

UDMACH1BSEL

Output Selection for DMA Channel 1 REQ

Section 4.7.2.52

510h

UDMACH2SSEL

Output Selection for DMA Channel 2 SREQ

Section 4.7.2.53

514h

UDMACH2BSEL

Output Selection for DMA Channel 2 REQ

Section 4.7.2.54

518h

UDMACH3SSEL

Output Selection for DMA Channel 3 SREQ

Section 4.7.2.55

51Ch

UDMACH3BSEL

Output Selection for DMA Channel 3 REQ

Section 4.7.2.56

520h

UDMACH4SSEL

Output Selection for DMA Channel 4 SREQ

Section 4.7.2.57

524h

UDMACH4BSEL

Output Selection for DMA Channel 4 REQ

Section 4.7.2.58

528h

UDMACH5SSEL

Output Selection for DMA Channel 5 SREQ

Section 4.7.2.59

52Ch

UDMACH5BSEL

Output Selection for DMA Channel 5 REQ

Section 4.7.2.60

530h

UDMACH6SSEL

Output Selection for DMA Channel 6 SREQ

Section 4.7.2.61

534h

UDMACH6BSEL

Output Selection for DMA Channel 6 REQ

Section 4.7.2.62

538h

UDMACH7SSEL

Output Selection for DMA Channel 7 SREQ

Section 4.7.2.63

53Ch

UDMACH7BSEL

Output Selection for DMA Channel 7 REQ

Section 4.7.2.64

540h

UDMACH8SSEL

Output Selection for DMA Channel 8 SREQ

Section 4.7.2.65

544h

UDMACH8BSEL

Output Selection for DMA Channel 8 REQ

Section 4.7.2.66

548h

UDMACH9SSEL

Output Selection for DMA Channel 9 SREQ

Section 4.7.2.67

54Ch

UDMACH9BSEL

Output Selection for DMA Channel 9 REQ

Section 4.7.2.68

550h

UDMACH10SSEL

Output Selection for DMA Channel 10 SREQ

Section 4.7.2.69

554h

UDMACH10BSEL

Output Selection for DMA Channel 10 REQ

Section 4.7.2.70

558h

UDMACH11SSEL

Output Selection for DMA Channel 11 SREQ

Section 4.7.2.71

55Ch

UDMACH11BSEL

Output Selection for DMA Channel 11 REQ

Section 4.7.2.72

560h

UDMACH12SSEL

Output Selection for DMA Channel 12 SREQ

Section 4.7.2.73

564h

UDMACH12BSEL

Output Selection for DMA Channel 12 REQ

Section 4.7.2.74

56Ch

UDMACH13BSEL

Output Selection for DMA Channel 13 REQ

Section 4.7.2.75

574h

UDMACH14BSEL

Output Selection for DMA Channel 14 REQ

Section 4.7.2.76

57Ch

UDMACH15BSEL

Output Selection for DMA Channel 15 REQ

Section 4.7.2.77

580h

UDMACH16SSEL

Output Selection for DMA Channel 16 SREQ

Section 4.7.2.78

584h

UDMACH16BSEL

Output Selection for DMA Channel 16 REQ

Section 4.7.2.79

588h

UDMACH17SSEL

Output Selection for DMA Channel 17 SREQ

Section 4.7.2.80

58Ch

UDMACH17BSEL

Output Selection for DMA Channel 17 REQ

Section 4.7.2.81

5A8h

UDMACH21SSEL

Output Selection for DMA Channel 21 SREQ

Section 4.7.2.82

5ACh

UDMACH21BSEL

Output Selection for DMA Channel 21 REQ

Section 4.7.2.83

5B0h

UDMACH22SSEL

Output Selection for DMA Channel 22 SREQ

Section 4.7.2.84

5B4h

UDMACH22BSEL

Output Selection for DMA Channel 22 REQ

Section 4.7.2.85

5B8h

UDMACH23SSEL

Output Selection for DMA Channel 23 SREQ

Section 4.7.2.86

5BCh

UDMACH23BSEL

Output Selection for DMA Channel 23 REQ

Section 4.7.2.87

5C0h

UDMACH24SSEL

Output Selection for DMA Channel 24 SREQ

Section 4.7.2.88

5C4h

UDMACH24BSEL

Output Selection for DMA Channel 24 REQ

Section 4.7.2.89

600h

GPT3ACAPTSEL

Output Selection for GPT3 0

Section 4.7.2.90

604h

GPT3BCAPTSEL

Output Selection for GPT3 1

Section 4.7.2.91

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-14. EVENT Registers (continued)
Offset

Acronym

700h

AUXSEL0

Output Selection for AUX Subscriber 0

Section 4.7.2.92

800h

CM3NMISEL0

Output Selection for NMI Subscriber 0

Section 4.7.2.93

900h

I2SSTMPSEL0

Output Selection for I2S Subscriber 0

Section 4.7.2.94

A00h

FRZSEL0

Output Selection for FRZ Subscriber 0

Section 4.7.2.95

F00h

SWEV

Set or Clear Software Events

Section 4.7.2.96

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Section

Interrupts and Events

271

Interrupts and Events Registers

4.7.2.1

www.ti.com

CPUIRQSEL0 Register (Offset = 0h) [reset = 4h]

CPUIRQSEL0 is shown in Figure 4-10 and described in Table 4-15.
Return to Summary Table.
Output Selection for CPU Interrupt 0
Figure 4-10. CPUIRQSEL0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-4h

Table 4-15. CPUIRQSEL0 Register Field Descriptions
Bit

272

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

Read only selection value
4h = Edge detect event from IOC. Configureded by the
IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.2

CPUIRQSEL1 Register (Offset = 4h) [reset = 9h]

CPUIRQSEL1 is shown in Figure 4-11 and described in Table 4-16.
Return to Summary Table.
Output Selection for CPU Interrupt 1
Figure 4-11. CPUIRQSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-9h

Table 4-16. CPUIRQSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

Read only selection value
9h = Interrupt event from I2C

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

273

Interrupts and Events Registers

4.7.2.3

www.ti.com

CPUIRQSEL2 Register (Offset = 8h) [reset = 1Eh]

CPUIRQSEL2 is shown in Figure 4-12 and described in Table 4-17.
Return to Summary Table.
Output Selection for CPU Interrupt 2
Figure 4-12. CPUIRQSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-1Eh

Table 4-17. CPUIRQSEL2 Register Field Descriptions
Bit

274

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

1Eh

Read only selection value
1Eh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_1 event

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.4

CPUIRQSEL3 Register (Offset = Ch) [reset = 38h]

CPUIRQSEL3 is shown in Figure 4-13 and described in Table 4-18.
Return to Summary Table.
Output Selection for CPU Interrupt 3
Figure 4-13. CPUIRQSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-38h

Table 4-18. CPUIRQSEL3 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RESERVED

38h

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

275

Interrupts and Events Registers

4.7.2.5

www.ti.com

CPUIRQSEL4 Register (Offset = 10h) [reset = 7h]

CPUIRQSEL4 is shown in Figure 4-14 and described in Table 4-19.
Return to Summary Table.
Output Selection for CPU Interrupt 4
Figure 4-14. CPUIRQSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-7h

Table 4-19. CPUIRQSEL4 Register Field Descriptions
Bit

276

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

Read only selection value
7h = Event from AON_RTC, controlled by the
AON_RTC:CTL.COMB_EV_MASK setting

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.6

CPUIRQSEL5 Register (Offset = 14h) [reset = 24h]

CPUIRQSEL5 is shown in Figure 4-15 and described in Table 4-20.
Return to Summary Table.
Output Selection for CPU Interrupt 5
Figure 4-15. CPUIRQSEL5 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-24h

Table 4-20. CPUIRQSEL5 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

24h

Read only selection value
24h = UART0 combined interrupt, interrupt flags are found here
UART0:MIS

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

277

Interrupts and Events Registers

4.7.2.7

www.ti.com

CPUIRQSEL6 Register (Offset = 18h) [reset = 1Ch]

CPUIRQSEL6 is shown in Figure 4-16 and described in Table 4-21.
Return to Summary Table.
Output Selection for CPU Interrupt 6
Figure 4-16. CPUIRQSEL6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-1Ch

Table 4-21. CPUIRQSEL6 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

1Ch

Read only selection value
1Ch = AUX software event 0, triggered by
AUX_EVCTL:SWEVSET.SWEV0, also available as AUX_EVENT0
AON wake up event.
MCU domain wakeup control AON_EVENT:MCUWUSEL
AUX domain wakeup control AON_EVENT:AUXWUSEL

278

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.8

CPUIRQSEL7 Register (Offset = 1Ch) [reset = 22h]

CPUIRQSEL7 is shown in Figure 4-17 and described in Table 4-22.
Return to Summary Table.
Output Selection for CPU Interrupt 7
Figure 4-17. CPUIRQSEL7 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-22h

Table 4-22. CPUIRQSEL7 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

22h

Read only selection value
22h = SSI0 combined interrupt, interrupt flags are found here
SSI0:MIS

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

279

Interrupts and Events Registers

4.7.2.9

www.ti.com

CPUIRQSEL8 Register (Offset = 20h) [reset = 23h]

CPUIRQSEL8 is shown in Figure 4-18 and described in Table 4-23.
Return to Summary Table.
Output Selection for CPU Interrupt 8
Figure 4-18. CPUIRQSEL8 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-23h

Table 4-23. CPUIRQSEL8 Register Field Descriptions
Bit

280

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

23h

Read only selection value
23h = SSI1 combined interrupt, interrupt flags are found here
SSI1:MIS

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.10 CPUIRQSEL9 Register (Offset = 24h) [reset = 1Bh]
CPUIRQSEL9 is shown in Figure 4-19 and described in Table 4-24.
Return to Summary Table.
Output Selection for CPU Interrupt 9
Figure 4-19. CPUIRQSEL9 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-1Bh

Table 4-24. CPUIRQSEL9 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

1Bh

Read only selection value
1Bh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_0 event

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

281

Interrupts and Events Registers

www.ti.com

4.7.2.11 CPUIRQSEL10 Register (Offset = 28h) [reset = 1Ah]
CPUIRQSEL10 is shown in Figure 4-20 and described in Table 4-25.
Return to Summary Table.
Output Selection for CPU Interrupt 10
Figure 4-20. CPUIRQSEL10 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-1Ah

Table 4-25. CPUIRQSEL10 Register Field Descriptions
Bit

282

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

1Ah

Read only selection value
1Ah = Combined RCF hardware interrupt, corresponding flag is here
RFC_DBELL:RFHWIFG

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.12 CPUIRQSEL11 Register (Offset = 2Ch) [reset = 19h]
CPUIRQSEL11 is shown in Figure 4-21 and described in Table 4-26.
Return to Summary Table.
Output Selection for CPU Interrupt 11
Figure 4-21. CPUIRQSEL11 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-19h

Table 4-26. CPUIRQSEL11 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

19h

Read only selection value
19h = RFC Doorbell Command Acknowledgement Interrupt,
equvialent to RFC_DBELL:RFACKIFG.ACKFLAG

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

283

Interrupts and Events Registers

www.ti.com

4.7.2.13 CPUIRQSEL12 Register (Offset = 30h) [reset = 8h]
CPUIRQSEL12 is shown in Figure 4-22 and described in Table 4-27.
Return to Summary Table.
Output Selection for CPU Interrupt 12
Figure 4-22. CPUIRQSEL12 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-8h

Table 4-27. CPUIRQSEL12 Register Field Descriptions
Bit

284

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

Read only selection value
8h = Interrupt event from I2S

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.14 CPUIRQSEL13 Register (Offset = 34h) [reset = 1Dh]
CPUIRQSEL13 is shown in Figure 4-23 and described in Table 4-28.
Return to Summary Table.
Output Selection for CPU Interrupt 13
Figure 4-23. CPUIRQSEL13 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-1Dh

Table 4-28. CPUIRQSEL13 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

1Dh

Read only selection value
1Dh = AUX software event 1, triggered by
AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2
AON wake up event.
MCU domain wakeup control AON_EVENT:MCUWUSEL
AUX domain wakeup control AON_EVENT:AUXWUSEL

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

285

Interrupts and Events Registers

www.ti.com

4.7.2.15 CPUIRQSEL14 Register (Offset = 38h) [reset = 18h]
CPUIRQSEL14 is shown in Figure 4-24 and described in Table 4-29.
Return to Summary Table.
Output Selection for CPU Interrupt 14
Figure 4-24. CPUIRQSEL14 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-18h

Table 4-29. CPUIRQSEL14 Register Field Descriptions
Bit

286

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

18h

Read only selection value
18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.16 CPUIRQSEL15 Register (Offset = 3Ch) [reset = 10h]
CPUIRQSEL15 is shown in Figure 4-25 and described in Table 4-30.
Return to Summary Table.
Output Selection for CPU Interrupt 15
Figure 4-25. CPUIRQSEL15 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-10h

Table 4-30. CPUIRQSEL15 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

10h

Read only selection value
10h = GPT0A interrupt event, controlled by GPT0:TAMR

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

287

Interrupts and Events Registers

www.ti.com

4.7.2.17 CPUIRQSEL16 Register (Offset = 40h) [reset = 11h]
CPUIRQSEL16 is shown in Figure 4-26 and described in Table 4-31.
Return to Summary Table.
Output Selection for CPU Interrupt 16
Figure 4-26. CPUIRQSEL16 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-11h

Table 4-31. CPUIRQSEL16 Register Field Descriptions
Bit

288

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

11h

Read only selection value
11h = GPT0B interrupt event, controlled by GPT0:TBMR

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.18 CPUIRQSEL17 Register (Offset = 44h) [reset = 12h]
CPUIRQSEL17 is shown in Figure 4-27 and described in Table 4-32.
Return to Summary Table.
Output Selection for CPU Interrupt 17
Figure 4-27. CPUIRQSEL17 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-12h

Table 4-32. CPUIRQSEL17 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

12h

Read only selection value
12h = GPT1A interrupt event, controlled by GPT1:TAMR

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

289

Interrupts and Events Registers

www.ti.com

4.7.2.19 CPUIRQSEL18 Register (Offset = 48h) [reset = 13h]
CPUIRQSEL18 is shown in Figure 4-28 and described in Table 4-33.
Return to Summary Table.
Output Selection for CPU Interrupt 18
Figure 4-28. CPUIRQSEL18 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-13h

Table 4-33. CPUIRQSEL18 Register Field Descriptions
Bit

290

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

13h

Read only selection value
13h = GPT1B interrupt event, controlled by GPT1:TBMR

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.20 CPUIRQSEL19 Register (Offset = 4Ch) [reset = Ch]
CPUIRQSEL19 is shown in Figure 4-29 and described in Table 4-34.
Return to Summary Table.
Output Selection for CPU Interrupt 19
Figure 4-29. CPUIRQSEL19 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-Ch

Table 4-34. CPUIRQSEL19 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

Read only selection value
Ch = GPT2A interrupt event, controlled by GPT2:TAMR

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

291

Interrupts and Events Registers

www.ti.com

4.7.2.21 CPUIRQSEL20 Register (Offset = 50h) [reset = Dh]
CPUIRQSEL20 is shown in Figure 4-30 and described in Table 4-35.
Return to Summary Table.
Output Selection for CPU Interrupt 20
Figure 4-30. CPUIRQSEL20 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-Dh

Table 4-35. CPUIRQSEL20 Register Field Descriptions
Bit

292

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

Read only selection value
Dh = GPT2B interrupt event, controlled by GPT2:TBMR

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.22 CPUIRQSEL21 Register (Offset = 54h) [reset = Eh]
CPUIRQSEL21 is shown in Figure 4-31 and described in Table 4-36.
Return to Summary Table.
Output Selection for CPU Interrupt 21
Figure 4-31. CPUIRQSEL21 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-Eh

Table 4-36. CPUIRQSEL21 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

Read only selection value
Eh = GPT3A interrupt event, controlled by GPT3:TAMR

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

293

Interrupts and Events Registers

www.ti.com

4.7.2.23 CPUIRQSEL22 Register (Offset = 58h) [reset = Fh]
CPUIRQSEL22 is shown in Figure 4-32 and described in Table 4-37.
Return to Summary Table.
Output Selection for CPU Interrupt 22
Figure 4-32. CPUIRQSEL22 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-Fh

Table 4-37. CPUIRQSEL22 Register Field Descriptions
Bit

294

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

Read only selection value
Fh = GPT3B interrupt event, controlled by GPT3:TBMR

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.24 CPUIRQSEL23 Register (Offset = 5Ch) [reset = 5Dh]
CPUIRQSEL23 is shown in Figure 4-33 and described in Table 4-38.
Return to Summary Table.
Output Selection for CPU Interrupt 23
Figure 4-33. CPUIRQSEL23 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-5Dh

Table 4-38. CPUIRQSEL23 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

5Dh

Read only selection value
5Dh = CRYPTO result available interupt event, the corresponding
flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled
by CRYPTO:IRQSTAT.RESULT_AVAIL

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

295

Interrupts and Events Registers

www.ti.com

4.7.2.25 CPUIRQSEL24 Register (Offset = 60h) [reset = 27h]
CPUIRQSEL24 is shown in Figure 4-34 and described in Table 4-39.
Return to Summary Table.
Output Selection for CPU Interrupt 24
Figure 4-34. CPUIRQSEL24 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-27h

Table 4-39. CPUIRQSEL24 Register Field Descriptions
Bit

296

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

27h

Read only selection value
27h = Combined DMA done, corresponding flags are here
UDMA0:REQDONE

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.26 CPUIRQSEL25 Register (Offset = 64h) [reset = 26h]
CPUIRQSEL25 is shown in Figure 4-35 and described in Table 4-40.
Return to Summary Table.
Output Selection for CPU Interrupt 25
Figure 4-35. CPUIRQSEL25 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-26h

Table 4-40. CPUIRQSEL25 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

26h

Read only selection value
26h = DMA bus error, corresponds to UDMA0:ERROR.STATUS

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

297

Interrupts and Events Registers

www.ti.com

4.7.2.27 CPUIRQSEL26 Register (Offset = 68h) [reset = 15h]
CPUIRQSEL26 is shown in Figure 4-36 and described in Table 4-41.
Return to Summary Table.
Output Selection for CPU Interrupt 26
Figure 4-36. CPUIRQSEL26 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-15h

Table 4-41. CPUIRQSEL26 Register Field Descriptions
Bit

298

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

15h

Read only selection value
15h = FLASH controller error event, the status flags are
FLASH:FEDACSTAT.FSM_DONE and
FLASH:FEDACSTAT.RVF_INT

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.28 CPUIRQSEL27 Register (Offset = 6Ch) [reset = 64h]
CPUIRQSEL27 is shown in Figure 4-37 and described in Table 4-42.
Return to Summary Table.
Output Selection for CPU Interrupt 27
Figure 4-37. CPUIRQSEL27 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-64h

Table 4-42. CPUIRQSEL27 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

64h

Read only selection value
64h = Software event 0, triggered by SWEV.SWEV0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

299

Interrupts and Events Registers

www.ti.com

4.7.2.29 CPUIRQSEL28 Register (Offset = 70h) [reset = Bh]
CPUIRQSEL28 is shown in Figure 4-38 and described in Table 4-43.
Return to Summary Table.
Output Selection for CPU Interrupt 28
Figure 4-38. CPUIRQSEL28 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-Bh

Table 4-43. CPUIRQSEL28 Register Field Descriptions
Bit

300

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

Read only selection value
Bh = AUX combined event, the corresponding flag register is here
AUX_EVCTL:EVTOMCUFLAGS

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.30 CPUIRQSEL29 Register (Offset = 74h) [reset = 1h]
CPUIRQSEL29 is shown in Figure 4-39 and described in Table 4-44.
Return to Summary Table.
Output Selection for CPU Interrupt 29
Figure 4-39. CPUIRQSEL29 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-1h

Table 4-44. CPUIRQSEL29 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

Read only selection value
1h = AON programmable event 0. Event selected by AON_EVENT
MCU event selector,
AON_EVENT:EVTOMCUSEL.AON_PROG0_EV

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

301

Interrupts and Events Registers

www.ti.com

4.7.2.31 CPUIRQSEL30 Register (Offset = 78h) [reset = 0h]
CPUIRQSEL30 is shown in Figure 4-40 and described in Table 4-45.
Return to Summary Table.
Output Selection for CPU Interrupt 30
Figure 4-40. CPUIRQSEL30 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-0h

Table 4-45. CPUIRQSEL30 Register Field Descriptions
Bit

302

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

R/W

Read/write selection value
0h = Always inactive
2h = AON programmable event 1. Event selected by AON_EVENT
MCU event selector,
AON_EVENT:EVTOMCUSEL.AON_PROG1_EV
3h = AON programmable event 2. Event selected by AON_EVENT
MCU event selector,
AON_EVENT:EVTOMCUSEL.AON_PROG2_EV
8h = Interrupt event from I2S
Ah = AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0
14h = DMA done for software tiggered UDMA channel 0, see
UDMA0:SOFTREQ
16h = DMA done for software tiggered UDMA channel 18, see
UDMA0:SOFTREQ
5Eh = CRYPTO DMA input done event, the correspondingg flag is
CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by
CRYPTO:IRQEN.DMA_IN_DONE
5Fh = RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
60h = RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
69h = AON wakeup event, corresponds flags are here
AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
6Bh = AUX Compare B event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag
AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC
status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
6Eh = AUX timer 1 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by
AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
77h = RTC periodic event controlled by
AON_RTC:CTL.RTC_UPD_EN
79h = Always asserted

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.32 CPUIRQSEL31 Register (Offset = 7Ch) [reset = 6Ah]
CPUIRQSEL31 is shown in Figure 4-41 and described in Table 4-46.
Return to Summary Table.
Output Selection for CPU Interrupt 31
Figure 4-41. CPUIRQSEL31 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-6Ah

Table 4-46. CPUIRQSEL31 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

6Ah

Read only selection value
6Ah = AUX Compare A event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

303

Interrupts and Events Registers

www.ti.com

4.7.2.33 CPUIRQSEL32 Register (Offset = 80h) [reset = 73h]
CPUIRQSEL32 is shown in Figure 4-42 and described in Table 4-47.
Return to Summary Table.
Output Selection for CPU Interrupt 32
Figure 4-42. CPUIRQSEL32 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-73h

Table 4-47. CPUIRQSEL32 Register Field Descriptions
Bit

304

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

73h

Read only selection value
73h = AUX ADC interrupt event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found
here AUX_EVCTL:EVTOMCUFLAGS

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.34 CPUIRQSEL33 Register (Offset = 84h) [reset = 68h]
CPUIRQSEL33 is shown in Figure 4-43 and described in Table 4-48.
Return to Summary Table.
Output Selection for CPU Interrupt 33
Figure 4-43. CPUIRQSEL33 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-68h

Table 4-48. CPUIRQSEL33 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

68h

Read only selection value
68h = TRNG Interrupt event, controlled by TRNG:IRQEN.EN

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

305

Interrupts and Events Registers

www.ti.com

4.7.2.35 RFCSEL0 Register (Offset = 100h) [reset = 3Dh]
RFCSEL0 is shown in Figure 4-44 and described in Table 4-49.
Return to Summary Table.
Output Selection for RFC Event 0
Figure 4-44. RFCSEL0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-3Dh

Table 4-49. RFCSEL0 Register Field Descriptions
Bit

306

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

3Dh

Read only selection value
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.36 RFCSEL1 Register (Offset = 104h) [reset = 3Eh]
RFCSEL1 is shown in Figure 4-45 and described in Table 4-50.
Return to Summary Table.
Output Selection for RFC Event 1
Figure 4-45. RFCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-3Eh

Table 4-50. RFCSEL1 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

3Eh

Read only selection value
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

307

Interrupts and Events Registers

www.ti.com

4.7.2.37 RFCSEL2 Register (Offset = 108h) [reset = 3Fh]
RFCSEL2 is shown in Figure 4-46 and described in Table 4-51.
Return to Summary Table.
Output Selection for RFC Event 2
Figure 4-46. RFCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-3Fh

Table 4-51. RFCSEL2 Register Field Descriptions
Bit

308

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

3Fh

Read only selection value
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.38 RFCSEL3 Register (Offset = 10Ch) [reset = 40h]
RFCSEL3 is shown in Figure 4-47 and described in Table 4-52.
Return to Summary Table.
Output Selection for RFC Event 3
Figure 4-47. RFCSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-40h

Table 4-52. RFCSEL3 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

40h

Read only selection value
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

309

Interrupts and Events Registers

www.ti.com

4.7.2.39 RFCSEL4 Register (Offset = 110h) [reset = 41h]
RFCSEL4 is shown in Figure 4-48 and described in Table 4-53.
Return to Summary Table.
Output Selection for RFC Event 4
Figure 4-48. RFCSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-41h

Table 4-53. RFCSEL4 Register Field Descriptions
Bit

310

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

41h

Read only selection value
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.40 RFCSEL5 Register (Offset = 114h) [reset = 42h]
RFCSEL5 is shown in Figure 4-49 and described in Table 4-54.
Return to Summary Table.
Output Selection for RFC Event 5
Figure 4-49. RFCSEL5 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-42h

Table 4-54. RFCSEL5 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

42h

Read only selection value
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

311

Interrupts and Events Registers

www.ti.com

4.7.2.41 RFCSEL6 Register (Offset = 118h) [reset = 43h]
RFCSEL6 is shown in Figure 4-50 and described in Table 4-55.
Return to Summary Table.
Output Selection for RFC Event 6
Figure 4-50. RFCSEL6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-43h

Table 4-55. RFCSEL6 Register Field Descriptions
Bit

312

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

43h

Read only selection value
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.42 RFCSEL7 Register (Offset = 11Ch) [reset = 44h]
RFCSEL7 is shown in Figure 4-51 and described in Table 4-56.
Return to Summary Table.
Output Selection for RFC Event 7
Figure 4-51. RFCSEL7 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-44h

Table 4-56. RFCSEL7 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

44h

Read only selection value
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

313

Interrupts and Events Registers

www.ti.com

4.7.2.43 RFCSEL8 Register (Offset = 120h) [reset = 77h]
RFCSEL8 is shown in Figure 4-52 and described in Table 4-57.
Return to Summary Table.
Output Selection for RFC Event 8
Figure 4-52. RFCSEL8 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-77h

Table 4-57. RFCSEL8 Register Field Descriptions
Bit

314

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

77h

Read only selection value
77h = RTC periodic event controlled by
AON_RTC:CTL.RTC_UPD_EN

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.44 RFCSEL9 Register (Offset = 124h) [reset = 2h]
RFCSEL9 is shown in Figure 4-53 and described in Table 4-58.
Return to Summary Table.
Output Selection for RFC Event 9
Figure 4-53. RFCSEL9 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-2h

Table 4-58. RFCSEL9 Register Field Descriptions
Bit
31-7

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

315

Interrupts and Events Registers

www.ti.com

Table 4-58. RFCSEL9 Register Field Descriptions (continued)

316

Bit

Field

Type

Reset

Description

6-0

R/W

Read/write selection value
0h = Always inactive
1h = AON programmable event 0. Event selected by AON_EVENT
MCU event selector,
AON_EVENT:EVTOMCUSEL.AON_PROG0_EV
2h = AON programmable event 1. Event selected by AON_EVENT
MCU event selector,
AON_EVENT:EVTOMCUSEL.AON_PROG1_EV
8h = Interrupt event from I2S
Ah = AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0
18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN
22h = SSI0 combined interrupt, interrupt flags are found here
SSI0:MIS
23h = SSI0 combined interrupt, interrupt flags are found here
SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here
UART0:MIS
27h = Combined DMA done, corresponding flags are here
UDMA0:REQDONE
5Dh = CRYPTO result available interupt event, the corresponding
flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled
by CRYPTO:IRQSTAT.RESULT_AVAIL
64h = Software event 0, triggered by SWEV.SWEV0
65h = Software event 1, triggered by SWEV.SWEV1
69h = AON wakeup event, corresponds flags are here
AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
6Ah = AUX Compare A event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag
AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC
status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
6Eh = AUX timer 1 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by
AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
73h = AUX ADC interrupt event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found
here AUX_EVCTL:EVTOMCUFLAGS
79h = Always asserted

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.45 GPT0ACAPTSEL Register (Offset = 200h) [reset = 55h]
GPT0ACAPTSEL is shown in Figure 4-54 and described in Table 4-59.
Return to Summary Table.
Output Selection for GPT0 0
Figure 4-54. GPT0ACAPTSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-55h

Table 4-59. GPT0ACAPTSEL Register Field Descriptions
Bit
31-7

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

317

Interrupts and Events Registers

www.ti.com

Table 4-59. GPT0ACAPTSEL Register Field Descriptions (continued)

318

Bit

Field

Type

Reset

Description

6-0

R/W

55h

Read/write selection value
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the
IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
7h = Event from AON_RTC, controlled by the
AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here
AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are
FLASH:FEDACSTAT.FSM_DONE and
FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt,
equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RCF hardware interrupt, corresponding flag is here
RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here
SSI0:MIS
23h = SSI0 combined interrupt, interrupt flags are found here
SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here
UART0:MIS
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
55h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT0 wil be routed here.
56h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT1 wil be routed here.
5Fh = RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
60h = RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
69h = AON wakeup event, corresponds flags are here
AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
6Ah = AUX Compare A event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag
AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC
status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
6Eh = AUX timer 1 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by
AUX_SMPH:AUTOTAKE

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-59. GPT0ACAPTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
70h = AUX ADC done, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
73h = AUX ADC interrupt event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found
here AUX_EVCTL:EVTOMCUFLAGS
77h = RTC periodic event controlled by
AON_RTC:CTL.RTC_UPD_EN
79h = Always asserted

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

319

Interrupts and Events Registers

www.ti.com

4.7.2.46 GPT0BCAPTSEL Register (Offset = 204h) [reset = 56h]
GPT0BCAPTSEL is shown in Figure 4-55 and described in Table 4-60.
Return to Summary Table.
Output Selection for GPT0 1
Figure 4-55. GPT0BCAPTSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-56h

Table 4-60. GPT0BCAPTSEL Register Field Descriptions
Bit
31-7

320

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-60. GPT0BCAPTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6-0

R/W

56h

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

321

Interrupts and Events Registers

www.ti.com

Table 4-60. GPT0BCAPTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

322

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.47 GPT1ACAPTSEL Register (Offset = 300h) [reset = 57h]
GPT1ACAPTSEL is shown in Figure 4-56 and described in Table 4-61.
Return to Summary Table.
Output Selection for GPT1 0
Figure 4-56. GPT1ACAPTSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-57h

Table 4-61. GPT1ACAPTSEL Register Field Descriptions
Bit
31-7

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

323

Interrupts and Events Registers

www.ti.com

Table 4-61. GPT1ACAPTSEL Register Field Descriptions (continued)

324

Bit

Field

Type

Reset

Description

6-0

R/W

57h

Read/write selection value
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the
IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
7h = Event from AON_RTC, controlled by the
AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here
AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are
FLASH:FEDACSTAT.FSM_DONE and
FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt,
equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RCF hardware interrupt, corresponding flag is here
RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here
SSI0:MIS
23h = SSI0 combined interrupt, interrupt flags are found here
SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here
UART0:MIS
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
57h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT2 wil be routed here.
58h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT3 wil be routed here.
5Fh = RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
60h = RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
69h = AON wakeup event, corresponds flags are here
AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
6Ah = AUX Compare A event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag
AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC
status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
6Eh = AUX timer 1 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by
AUX_SMPH:AUTOTAKE

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-61. GPT1ACAPTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

325

Interrupts and Events Registers

www.ti.com

4.7.2.48 GPT1BCAPTSEL Register (Offset = 304h) [reset = 58h]
GPT1BCAPTSEL is shown in Figure 4-57 and described in Table 4-62.
Return to Summary Table.
Output Selection for GPT1 1
Figure 4-57. GPT1BCAPTSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-58h

Table 4-62. GPT1BCAPTSEL Register Field Descriptions
Bit
31-7

326

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-62. GPT1BCAPTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6-0

R/W

58h

Read/write selection value
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the
IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
7h = Event from AON_RTC, controlled by the
AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here
AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are
FLASH:FEDACSTAT.FSM_DONE and
FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt,
equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RCF hardware interrupt, corresponding flag is here
RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here
SSI0:MIS
23h = SSI0 combined interrupt, interrupt flags are found here
SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here
UART0:MIS
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
57h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT2 wil be routed here.
58h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT3 wil be routed here.
5Fh = RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
60h = RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
69h = AON wakeup event, corresponds flags are here
AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
6Ah = AUX Compare A event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag
AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC
status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
6Eh = AUX timer 1 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by
AUX_SMPH:AUTOTAKE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

327

Interrupts and Events Registers

www.ti.com

Table 4-62. GPT1BCAPTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

328

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.49 GPT2ACAPTSEL Register (Offset = 400h) [reset = 59h]
GPT2ACAPTSEL is shown in Figure 4-58 and described in Table 4-63.
Return to Summary Table.
Output Selection for GPT2 0
Figure 4-58. GPT2ACAPTSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-59h

Table 4-63. GPT2ACAPTSEL Register Field Descriptions
Bit
31-7

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

329

Interrupts and Events Registers

www.ti.com

Table 4-63. GPT2ACAPTSEL Register Field Descriptions (continued)

330

Bit

Field

Type

Reset

Description

6-0

R/W

59h

Read/write selection value
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the
IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
7h = Event from AON_RTC, controlled by the
AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here
AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are
FLASH:FEDACSTAT.FSM_DONE and
FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt,
equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RCF hardware interrupt, corresponding flag is here
RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here
SSI0:MIS
23h = SSI0 combined interrupt, interrupt flags are found here
SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here
UART0:MIS
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
59h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT4 wil be routed here.
5Ah = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT4 wil be routed here.
61h = RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6
62h = RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7
69h = AON wakeup event, corresponds flags are here
AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
6Ah = AUX Compare A event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag
AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC
status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
6Eh = AUX timer 1 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by
AUX_SMPH:AUTOTAKE

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-63. GPT2ACAPTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

331

Interrupts and Events Registers

www.ti.com

4.7.2.50 GPT2BCAPTSEL Register (Offset = 404h) [reset = 5Ah]
GPT2BCAPTSEL is shown in Figure 4-59 and described in Table 4-64.
Return to Summary Table.
Output Selection for GPT2 1
Figure 4-59. GPT2BCAPTSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-5Ah

Table 4-64. GPT2BCAPTSEL Register Field Descriptions
Bit
31-7

332

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-64. GPT2BCAPTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6-0

R/W

5Ah

Read/write selection value
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the
IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
7h = Event from AON_RTC, controlled by the
AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here
AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are
FLASH:FEDACSTAT.FSM_DONE and
FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt,
equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RCF hardware interrupt, corresponding flag is here
RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here
SSI0:MIS
23h = SSI0 combined interrupt, interrupt flags are found here
SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here
UART0:MIS
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
59h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT4 wil be routed here.
5Ah = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT4 wil be routed here.
61h = RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6
62h = RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7
69h = AON wakeup event, corresponds flags are here
AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
6Ah = AUX Compare A event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag
AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC
status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
6Eh = AUX timer 1 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by
AUX_SMPH:AUTOTAKE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

333

Interrupts and Events Registers

www.ti.com

Table 4-64. GPT2BCAPTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

334

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.51 UDMACH1SSEL Register (Offset = 508h) [reset = 31h]
UDMACH1SSEL is shown in Figure 4-60 and described in Table 4-65.
Return to Summary Table.
Output Selection for DMA Channel 1 SREQ
Figure 4-60. UDMACH1SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-31h

Table 4-65. UDMACH1SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

31h

Read only selection value
31h = UART0 RX DMA single request, controlled by
UART0:DMACTL.RXDMAE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

335

Interrupts and Events Registers

www.ti.com

4.7.2.52 UDMACH1BSEL Register (Offset = 50Ch) [reset = 30h]
UDMACH1BSEL is shown in Figure 4-61 and described in Table 4-66.
Return to Summary Table.
Output Selection for DMA Channel 1 REQ
Figure 4-61. UDMACH1BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-30h

Table 4-66. UDMACH1BSEL Register Field Descriptions
Bit

336

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

30h

Read only selection value
30h = UART0 RX DMA burst request, controlled by
UART0:DMACTL.RXDMAE

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.53 UDMACH2SSEL Register (Offset = 510h) [reset = 33h]
UDMACH2SSEL is shown in Figure 4-62 and described in Table 4-67.
Return to Summary Table.
Output Selection for DMA Channel 2 SREQ
Figure 4-62. UDMACH2SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-33h

Table 4-67. UDMACH2SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

33h

Read only selection value
33h = UART0 TX DMA single request, controlled by
UART0:DMACTL.TXDMAE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

337

Interrupts and Events Registers

www.ti.com

4.7.2.54 UDMACH2BSEL Register (Offset = 514h) [reset = 32h]
UDMACH2BSEL is shown in Figure 4-63 and described in Table 4-68.
Return to Summary Table.
Output Selection for DMA Channel 2 REQ
Figure 4-63. UDMACH2BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-32h

Table 4-68. UDMACH2BSEL Register Field Descriptions
Bit

338

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

32h

Read only selection value
32h = UART0 TX DMA burst request, controlled by
UART0:DMACTL.TXDMAE

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.55 UDMACH3SSEL Register (Offset = 518h) [reset = 29h]
UDMACH3SSEL is shown in Figure 4-64 and described in Table 4-69.
Return to Summary Table.
Output Selection for DMA Channel 3 SREQ
Figure 4-64. UDMACH3SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-29h

Table 4-69. UDMACH3SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

29h

Read only selection value
29h = SSI0 RX DMA single request, controlled by
SSI0:DMACR.RXDMAE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

339

Interrupts and Events Registers

www.ti.com

4.7.2.56 UDMACH3BSEL Register (Offset = 51Ch) [reset = 28h]
UDMACH3BSEL is shown in Figure 4-65 and described in Table 4-70.
Return to Summary Table.
Output Selection for DMA Channel 3 REQ
Figure 4-65. UDMACH3BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-28h

Table 4-70. UDMACH3BSEL Register Field Descriptions
Bit

340

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

28h

Read only selection value
28h = SSI0 RX DMA burst request , controlled by
SSI0:DMACR.RXDMAE

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.57 UDMACH4SSEL Register (Offset = 520h) [reset = 2Bh]
UDMACH4SSEL is shown in Figure 4-66 and described in Table 4-71.
Return to Summary Table.
Output Selection for DMA Channel 4 SREQ
Figure 4-66. UDMACH4SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-2Bh

Table 4-71. UDMACH4SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

2Bh

Read only selection value
2Bh = SSI0 TX DMA single request, controlled by
SSI0:DMACR.TXDMAE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

341

Interrupts and Events Registers

www.ti.com

4.7.2.58 UDMACH4BSEL Register (Offset = 524h) [reset = 2Ah]
UDMACH4BSEL is shown in Figure 4-67 and described in Table 4-72.
Return to Summary Table.
Output Selection for DMA Channel 4 REQ
Figure 4-67. UDMACH4BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-2Ah

Table 4-72. UDMACH4BSEL Register Field Descriptions
Bit

342

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

2Ah

Read only selection value
2Ah = SSI0 TX DMA burst request , controlled by
SSI0:DMACR.TXDMAE

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.59 UDMACH5SSEL Register (Offset = 528h) [reset = 3Ah]
UDMACH5SSEL is shown in Figure 4-68 and described in Table 4-73.
Return to Summary Table.
Output Selection for DMA Channel 5 SREQ
Figure 4-68. UDMACH5SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-3Ah

Table 4-73. UDMACH5SSEL Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RESERVED

3Ah

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

343

Interrupts and Events Registers

www.ti.com

4.7.2.60 UDMACH5BSEL Register (Offset = 52Ch) [reset = 39h]
UDMACH5BSEL is shown in Figure 4-69 and described in Table 4-74.
Return to Summary Table.
Output Selection for DMA Channel 5 REQ
Figure 4-69. UDMACH5BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-39h

Table 4-74. UDMACH5BSEL Register Field Descriptions
Bit
31-0

344

Field

Type

Reset

Description

RESERVED

39h

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.61 UDMACH6SSEL Register (Offset = 530h) [reset = 3Ch]
UDMACH6SSEL is shown in Figure 4-70 and described in Table 4-75.
Return to Summary Table.
Output Selection for DMA Channel 6 SREQ
Figure 4-70. UDMACH6SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-3Ch

Table 4-75. UDMACH6SSEL Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

RESERVED

3Ch

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

345

Interrupts and Events Registers

www.ti.com

4.7.2.62 UDMACH6BSEL Register (Offset = 534h) [reset = 3Bh]
UDMACH6BSEL is shown in Figure 4-71 and described in Table 4-76.
Return to Summary Table.
Output Selection for DMA Channel 6 REQ
Figure 4-71. UDMACH6BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-3Bh

Table 4-76. UDMACH6BSEL Register Field Descriptions
Bit
31-0

346

Field

Type

Reset

Description

RESERVED

3Bh

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.63 UDMACH7SSEL Register (Offset = 538h) [reset = 75h]
UDMACH7SSEL is shown in Figure 4-72 and described in Table 4-77.
Return to Summary Table.
Output Selection for DMA Channel 7 SREQ
Figure 4-72. UDMACH7SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-75h

Table 4-77. UDMACH7SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

75h

Read only selection value
75h = DMA single request event from AUX, configured by
AUX_EVCTL:DMACTL

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

347

Interrupts and Events Registers

www.ti.com

4.7.2.64 UDMACH7BSEL Register (Offset = 53Ch) [reset = 76h]
UDMACH7BSEL is shown in Figure 4-73 and described in Table 4-78.
Return to Summary Table.
Output Selection for DMA Channel 7 REQ
Figure 4-73. UDMACH7BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-76h

Table 4-78. UDMACH7BSEL Register Field Descriptions
Bit

348

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

76h

Read only selection value
76h = DMA burst request event from AUX, configured by
AUX_EVCTL:DMACTL

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.65 UDMACH8SSEL Register (Offset = 540h) [reset = 74h]
UDMACH8SSEL is shown in Figure 4-74 and described in Table 4-79.
Return to Summary Table.
Output Selection for DMA Channel 8 SREQ
Single request is ignored for this channel
Figure 4-74. UDMACH8SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-74h

Table 4-79. UDMACH8SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

74h

Read only selection value
74h = AUX observation loopback

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

349

Interrupts and Events Registers

www.ti.com

4.7.2.66 UDMACH8BSEL Register (Offset = 544h) [reset = 74h]
UDMACH8BSEL is shown in Figure 4-75 and described in Table 4-80.
Return to Summary Table.
Output Selection for DMA Channel 8 REQ
Figure 4-75. UDMACH8BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-74h

Table 4-80. UDMACH8BSEL Register Field Descriptions
Bit

350

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

74h

Read only selection value
74h = AUX observation loopback

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.67 UDMACH9SSEL Register (Offset = 548h) [reset = 45h]
UDMACH9SSEL is shown in Figure 4-76 and described in Table 4-81.
Return to Summary Table.
Output Selection for DMA Channel 9 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as
GPT0:RIS.DMAARIS
Figure 4-76. UDMACH9SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-45h

Table 4-81. UDMACH9SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

R/W

45h

Read/write selection value
0h = Always inactive
45h = Not used tied to 0
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

351

Interrupts and Events Registers

www.ti.com

4.7.2.68 UDMACH9BSEL Register (Offset = 54Ch) [reset = 4Dh]
UDMACH9BSEL is shown in Figure 4-77 and described in Table 4-82.
Return to Summary Table.
Output Selection for DMA Channel 9 REQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as
GPT0:RIS.DMAARIS
Figure 4-77. UDMACH9BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-4Dh

Table 4-82. UDMACH9BSEL Register Field Descriptions
Bit

352

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

R/W

4Dh

Read/write selection value
0h = Always inactive
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.69 UDMACH10SSEL Register (Offset = 550h) [reset = 46h]
UDMACH10SSEL is shown in Figure 4-78 and described in Table 4-83.
Return to Summary Table.
Output Selection for DMA Channel 10 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as
GPT0:RIS.DMABRIS
Figure 4-78. UDMACH10SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-46h

Table 4-83. UDMACH10SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

R/W

46h

Read/write selection value
0h = Always inactive
46h = Not used tied to 0
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

353

Interrupts and Events Registers

www.ti.com

4.7.2.70 UDMACH10BSEL Register (Offset = 554h) [reset = 4Eh]
UDMACH10BSEL is shown in Figure 4-79 and described in Table 4-84.
Return to Summary Table.
Output Selection for DMA Channel 10 REQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as
GPT0:RIS.DMABRIS
Figure 4-79. UDMACH10BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-4Eh

Table 4-84. UDMACH10BSEL Register Field Descriptions
Bit

354

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

R/W

4Eh

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.71 UDMACH11SSEL Register (Offset = 558h) [reset = 47h]
UDMACH11SSEL is shown in Figure 4-80 and described in Table 4-85.
Return to Summary Table.
Output Selection for DMA Channel 11 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as
GPT1:RIS.DMAARIS
Figure 4-80. UDMACH11SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-47h

Table 4-85. UDMACH11SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

R/W

47h

Read/write selection value
0h = Always inactive
47h = Not used tied to 0
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

355

Interrupts and Events Registers

www.ti.com

4.7.2.72 UDMACH11BSEL Register (Offset = 55Ch) [reset = 4Fh]
UDMACH11BSEL is shown in Figure 4-81 and described in Table 4-86.
Return to Summary Table.
Output Selection for DMA Channel 11 REQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as
GPT1:RIS.DMAARIS
Figure 4-81. UDMACH11BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-4Fh

Table 4-86. UDMACH11BSEL Register Field Descriptions
Bit

356

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

R/W

4Fh

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.73 UDMACH12SSEL Register (Offset = 560h) [reset = 48h]
UDMACH12SSEL is shown in Figure 4-82 and described in Table 4-87.
Return to Summary Table.
Output Selection for DMA Channel 12 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as
GPT1:RIS.DMABRIS
Figure 4-82. UDMACH12SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-48h

Table 4-87. UDMACH12SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

R/W

48h

Read/write selection value
0h = Always inactive
48h = Not used tied to 0
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

357

Interrupts and Events Registers

www.ti.com

4.7.2.74 UDMACH12BSEL Register (Offset = 564h) [reset = 50h]
UDMACH12BSEL is shown in Figure 4-83 and described in Table 4-88.
Return to Summary Table.
Output Selection for DMA Channel 12 REQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as
GPT1:RIS.DMABRIS
Figure 4-83. UDMACH12BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-50h

Table 4-88. UDMACH12BSEL Register Field Descriptions
Bit

358

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

R/W

50h

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.75 UDMACH13BSEL Register (Offset = 56Ch) [reset = 3h]
UDMACH13BSEL is shown in Figure 4-84 and described in Table 4-89.
Return to Summary Table.
Output Selection for DMA Channel 13 REQ
Figure 4-84. UDMACH13BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-3h

Table 4-89. UDMACH13BSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

Read only selection value
3h = AON programmable event 2. Event selected by AON_EVENT
MCU event selector,
AON_EVENT:EVTOMCUSEL.AON_PROG2_EV

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

359

Interrupts and Events Registers

www.ti.com

4.7.2.76 UDMACH14BSEL Register (Offset = 574h) [reset = 1h]
UDMACH14BSEL is shown in Figure 4-85 and described in Table 4-90.
Return to Summary Table.
Output Selection for DMA Channel 14 REQ
Figure 4-85. UDMACH14BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-1h

Table 4-90. UDMACH14BSEL Register Field Descriptions
Bit
31-7

360

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-90. UDMACH14BSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6-0

R/W

Read/write selection value
0h = Always inactive
1h = AON programmable event 0. Event selected by AON_EVENT
MCU event selector,
AON_EVENT:EVTOMCUSEL.AON_PROG0_EV
2h = AON programmable event 1. Event selected by AON_EVENT
MCU event selector,
AON_EVENT:EVTOMCUSEL.AON_PROG1_EV
3h = AON programmable event 2. Event selected by AON_EVENT
MCU event selector,
AON_EVENT:EVTOMCUSEL.AON_PROG2_EV
4h = Edge detect event from IOC. Configureded by the
IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
7h = Event from AON_RTC, controlled by the
AON_RTC:CTL.COMB_EV_MASK setting
8h = Interrupt event from I2S
9h = Interrupt event from I2C
Ah = AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0
Bh = AUX combined event, the corresponding flag register is here
AUX_EVCTL:EVTOMCUFLAGS
Ch = GPT2A interrupt event, controlled by GPT2:TAMR
Dh = GPT2B interrupt event, controlled by GPT2:TBMR
Eh = GPT3A interrupt event, controlled by GPT3:TAMR
Fh = GPT3B interrupt event, controlled by GPT3:TBMR
10h = GPT0A interrupt event, controlled by GPT0:TAMR
11h = GPT0B interrupt event, controlled by GPT0:TBMR
12h = GPT1A interrupt event, controlled by GPT1:TAMR
13h = GPT1B interrupt event, controlled by GPT1:TBMR
14h = DMA done for software tiggered UDMA channel 0, see
UDMA0:SOFTREQ
15h = FLASH controller error event, the status flags are
FLASH:FEDACSTAT.FSM_DONE and
FLASH:FEDACSTAT.RVF_INT
16h = DMA done for software tiggered UDMA channel 18, see
UDMA0:SOFTREQ
18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN
19h = RFC Doorbell Command Acknowledgement Interrupt,
equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RCF hardware interrupt, corresponding flag is here
RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_0 event
1Dh = AUX software event 1, triggered by
AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2
AON wake up event.
MCU domain wakeup control AON_EVENT:MCUWUSEL
AUX domain wakeup control AON_EVENT:AUXWUSEL
1Eh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here
SSI0:MIS
23h = SSI0 combined interrupt, interrupt flags are found here
SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here
UART0:MIS
26h = DMA bus error, corresponds to UDMA0:ERROR.STATUS
27h = Combined DMA done, corresponding flags are here

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

361

Interrupts and Events Registers

www.ti.com

Table 4-90. UDMACH14BSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
UDMA0:REQDONE
28h = SSI0 RX DMA burst request , controlled by
SSI0:DMACR.RXDMAE
29h = SSI0 RX DMA single request, controlled by
SSI0:DMACR.RXDMAE
2Ah = SSI0 TX DMA burst request , controlled by
SSI0:DMACR.TXDMAE
2Bh = SSI0 TX DMA single request, controlled by
SSI0:DMACR.TXDMAE
2Ch = SSI1 RX DMA burst request , controlled by
SSI0:DMACR.RXDMAE
2Dh = SSI1 RX DMA single request, controlled by
SSI0:DMACR.RXDMAE
2Eh = SSI1 TX DMA burst request , controlled by
SSI0:DMACR.TXDMAE
2Fh = SSI1 TX DMA single request, controlled by
SSI0:DMACR.TXDMAE
30h = UART0 RX DMA burst request, controlled by
UART0:DMACTL.RXDMAE
31h = UART0 RX DMA single request, controlled by
UART0:DMACTL.RXDMAE
32h = UART0 TX DMA burst request, controlled by
UART0:DMACTL.TXDMAE
33h = UART0 TX DMA single request, controlled by
UART0:DMACTL.TXDMAE
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
55h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT0 wil be routed here.
56h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT1 wil be routed here.
57h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT2 wil be routed here.
58h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT3 wil be routed here.
59h = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT4 wil be routed here.
5Ah = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT4 wil be routed here.
5Bh = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM

362

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-90. UDMACH14BSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
PORT_EVENT6 wil be routed here.
5Ch = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT7 wil be routed here.
5Dh = CRYPTO result available interupt event, the corresponding
flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled
by CRYPTO:IRQSTAT.RESULT_AVAIL
5Eh = CRYPTO DMA input done event, the correspondingg flag is
CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by
CRYPTO:IRQEN.DMA_IN_DONE
5Fh = RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
60h = RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
61h = RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6
62h = RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7
63h = Watchdog non maskable interrupt event, controlled by
WDT:CTL.INTTYPE
64h = Software event 0, triggered by SWEV.SWEV0
65h = Software event 1, triggered by SWEV.SWEV1
66h = Software event 2, triggered by SWEV.SWEV2
67h = Software event 3, triggered by SWEV.SWEV3
68h = TRNG Interrupt event, controlled by TRNG:IRQEN.EN
69h = AON wakeup event, corresponds flags are here
AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
6Ah = AUX Compare A event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag
AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC
status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
6Eh = AUX timer 1 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by
AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
73h = AUX ADC interrupt event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found
here AUX_EVCTL:EVTOMCUFLAGS
74h = AUX observation loopback
75h = DMA single request event from AUX, configured by
AUX_EVCTL:DMACTL
76h = DMA burst request event from AUX, configured by
AUX_EVCTL:DMACTL
77h = RTC periodic event controlled by
AON_RTC:CTL.RTC_UPD_EN
78h = CPU halted
79h = Always asserted

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

363

Interrupts and Events Registers

www.ti.com

4.7.2.77 UDMACH15BSEL Register (Offset = 57Ch) [reset = 7h]
UDMACH15BSEL is shown in Figure 4-86 and described in Table 4-91.
Return to Summary Table.
Output Selection for DMA Channel 15 REQ
Figure 4-86. UDMACH15BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-7h

Table 4-91. UDMACH15BSEL Register Field Descriptions
Bit

364

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

Read only selection value
7h = Event from AON_RTC, controlled by the
AON_RTC:CTL.COMB_EV_MASK setting

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.78 UDMACH16SSEL Register (Offset = 580h) [reset = 2Dh]
UDMACH16SSEL is shown in Figure 4-87 and described in Table 4-92.
Return to Summary Table.
Output Selection for DMA Channel 16 SREQ
Figure 4-87. UDMACH16SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-2Dh

Table 4-92. UDMACH16SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

2Dh

Read only selection value
2Dh = SSI1 RX DMA single request, controlled by
SSI0:DMACR.RXDMAE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

365

Interrupts and Events Registers

www.ti.com

4.7.2.79 UDMACH16BSEL Register (Offset = 584h) [reset = 2Ch]
UDMACH16BSEL is shown in Figure 4-88 and described in Table 4-93.
Return to Summary Table.
Output Selection for DMA Channel 16 REQ
Figure 4-88. UDMACH16BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-2Ch

Table 4-93. UDMACH16BSEL Register Field Descriptions
Bit

366

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

2Ch

Read only selection value
2Ch = SSI1 RX DMA burst request , controlled by
SSI0:DMACR.RXDMAE

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.80 UDMACH17SSEL Register (Offset = 588h) [reset = 2Fh]
UDMACH17SSEL is shown in Figure 4-89 and described in Table 4-94.
Return to Summary Table.
Output Selection for DMA Channel 17 SREQ
Figure 4-89. UDMACH17SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-2Fh

Table 4-94. UDMACH17SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

2Fh

Read only selection value
2Fh = SSI1 TX DMA single request, controlled by
SSI0:DMACR.TXDMAE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

367

Interrupts and Events Registers

www.ti.com

4.7.2.81 UDMACH17BSEL Register (Offset = 58Ch) [reset = 2Eh]
UDMACH17BSEL is shown in Figure 4-90 and described in Table 4-95.
Return to Summary Table.
Output Selection for DMA Channel 17 REQ
Figure 4-90. UDMACH17BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-2Eh

Table 4-95. UDMACH17BSEL Register Field Descriptions
Bit

368

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

2Eh

Read only selection value
2Eh = SSI1 TX DMA burst request , controlled by
SSI0:DMACR.TXDMAE

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.82 UDMACH21SSEL Register (Offset = 5A8h) [reset = 64h]
UDMACH21SSEL is shown in Figure 4-91 and described in Table 4-96.
Return to Summary Table.
Output Selection for DMA Channel 21 SREQ
Figure 4-91. UDMACH21SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-64h

Table 4-96. UDMACH21SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

64h

Read only selection value
64h = Software event 0, triggered by SWEV.SWEV0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

369

Interrupts and Events Registers

www.ti.com

4.7.2.83 UDMACH21BSEL Register (Offset = 5ACh) [reset = 64h]
UDMACH21BSEL is shown in Figure 4-92 and described in Table 4-97.
Return to Summary Table.
Output Selection for DMA Channel 21 REQ
Figure 4-92. UDMACH21BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-64h

Table 4-97. UDMACH21BSEL Register Field Descriptions
Bit

370

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

64h

Read only selection value
64h = Software event 0, triggered by SWEV.SWEV0

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.84 UDMACH22SSEL Register (Offset = 5B0h) [reset = 65h]
UDMACH22SSEL is shown in Figure 4-93 and described in Table 4-98.
Return to Summary Table.
Output Selection for DMA Channel 22 SREQ
Figure 4-93. UDMACH22SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-65h

Table 4-98. UDMACH22SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

65h

Read only selection value
65h = Software event 1, triggered by SWEV.SWEV1

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

371

Interrupts and Events Registers

www.ti.com

4.7.2.85 UDMACH22BSEL Register (Offset = 5B4h) [reset = 65h]
UDMACH22BSEL is shown in Figure 4-94 and described in Table 4-99.
Return to Summary Table.
Output Selection for DMA Channel 22 REQ
Figure 4-94. UDMACH22BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-65h

Table 4-99. UDMACH22BSEL Register Field Descriptions
Bit

372

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

65h

Read only selection value
65h = Software event 1, triggered by SWEV.SWEV1

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.86 UDMACH23SSEL Register (Offset = 5B8h) [reset = 66h]
UDMACH23SSEL is shown in Figure 4-95 and described in Table 4-100.
Return to Summary Table.
Output Selection for DMA Channel 23 SREQ
Figure 4-95. UDMACH23SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-66h

Table 4-100. UDMACH23SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

66h

Read only selection value
66h = Software event 2, triggered by SWEV.SWEV2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

373

Interrupts and Events Registers

www.ti.com

4.7.2.87 UDMACH23BSEL Register (Offset = 5BCh) [reset = 66h]
UDMACH23BSEL is shown in Figure 4-96 and described in Table 4-101.
Return to Summary Table.
Output Selection for DMA Channel 23 REQ
Figure 4-96. UDMACH23BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-66h

Table 4-101. UDMACH23BSEL Register Field Descriptions
Bit

374

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

66h

Read only selection value
66h = Software event 2, triggered by SWEV.SWEV2

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.88 UDMACH24SSEL Register (Offset = 5C0h) [reset = 67h]
UDMACH24SSEL is shown in Figure 4-97 and described in Table 4-102.
Return to Summary Table.
Output Selection for DMA Channel 24 SREQ
Figure 4-97. UDMACH24SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-67h

Table 4-102. UDMACH24SSEL Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

67h

Read only selection value
67h = Software event 3, triggered by SWEV.SWEV3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

375

Interrupts and Events Registers

www.ti.com

4.7.2.89 UDMACH24BSEL Register (Offset = 5C4h) [reset = 67h]
UDMACH24BSEL is shown in Figure 4-98 and described in Table 4-103.
Return to Summary Table.
Output Selection for DMA Channel 24 REQ
Figure 4-98. UDMACH24BSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-67h

Table 4-103. UDMACH24BSEL Register Field Descriptions
Bit

376

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

67h

Read only selection value
67h = Software event 3, triggered by SWEV.SWEV3

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.90 GPT3ACAPTSEL Register (Offset = 600h) [reset = 5Bh]
GPT3ACAPTSEL is shown in Figure 4-99 and described in Table 4-104.
Return to Summary Table.
Output Selection for GPT3 0
Figure 4-99. GPT3ACAPTSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-5Bh

Table 4-104. GPT3ACAPTSEL Register Field Descriptions
Bit
31-7

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

377

Interrupts and Events Registers

www.ti.com

Table 4-104. GPT3ACAPTSEL Register Field Descriptions (continued)

378

Bit

Field

Type

Reset

Description

6-0

R/W

5Bh

Read/write selection value
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the
IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
7h = Event from AON_RTC, controlled by the
AON_RTC:CTL.COMB_EV_MASK setting
Bh = AUX combined event, the corresponding flag register is here
AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are
FLASH:FEDACSTAT.FSM_DONE and
FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt,
equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RCF hardware interrupt, corresponding flag is here
RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here
SSI0:MIS
23h = SSI0 combined interrupt, interrupt flags are found here
SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here
UART0:MIS
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
5Bh = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT6 wil be routed here.
5Ch = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT7 wil be routed here.
61h = RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6
62h = RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7
69h = AON wakeup event, corresponds flags are here
AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
6Ah = AUX Compare A event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag
AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC
status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
6Eh = AUX timer 1 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by
AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-104. GPT3ACAPTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
73h = AUX ADC interrupt event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found
here AUX_EVCTL:EVTOMCUFLAGS
77h = RTC periodic event controlled by
AON_RTC:CTL.RTC_UPD_EN
79h = Always asserted

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

379

Interrupts and Events Registers

www.ti.com

4.7.2.91 GPT3BCAPTSEL Register (Offset = 604h) [reset = 5Ch]
GPT3BCAPTSEL is shown in Figure 4-100 and described in Table 4-105.
Return to Summary Table.
Output Selection for GPT3 1
Figure 4-100. GPT3BCAPTSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-5Ch

Table 4-105. GPT3BCAPTSEL Register Field Descriptions
Bit
31-7

380

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

Table 4-105. GPT3BCAPTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6-0

R/W

5Ch

Read/write selection value
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the
IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
7h = Event from AON_RTC, controlled by the
AON_RTC:CTL.COMB_EV_MASK setting
Bh = AUX combined event, the corresponding flag register is here
AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are
FLASH:FEDACSTAT.FSM_DONE and
FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt,
equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RCF hardware interrupt, corresponding flag is here
RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events.
Corresponding flags are here RFC_DBELL:RFCPEIFG. Only
interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger
a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here
SSI0:MIS
23h = SSI0 combined interrupt, interrupt flags are found here
SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here
UART0:MIS
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
5Bh = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT6 wil be routed here.
5Ch = Port capture event from IOC, configured by
IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM
PORT_EVENT7 wil be routed here.
61h = RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6
62h = RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7
69h = AON wakeup event, corresponds flags are here
AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
6Ah = AUX Compare A event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag
AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC
status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
6Eh = AUX timer 1 event, corresponds to
AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by
AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

381

Interrupts and Events Registers

www.ti.com

Table 4-105. GPT3BCAPTSEL Register Field Descriptions (continued)
Bit

Field

Type

Reset

382

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.92 AUXSEL0 Register (Offset = 700h) [reset = 10h]
AUXSEL0 is shown in Figure 4-101 and described in Table 4-106.
Return to Summary Table.
Output Selection for AUX Subscriber 0
Figure 4-101. AUXSEL0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-10h

Table 4-106. AUXSEL0 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

R/W

10h

Read/write selection value
0h = Always inactive
Ch = GPT2A interrupt event, controlled by GPT2:TAMR
Dh = GPT2B interrupt event, controlled by GPT2:TBMR
Eh = GPT3A interrupt event, controlled by GPT3:TAMR
Fh = GPT3B interrupt event, controlled by GPT3:TBMR
10h = GPT0A interrupt event, controlled by GPT0:TAMR
11h = GPT0B interrupt event, controlled by GPT0:TBMR
12h = GPT1A interrupt event, controlled by GPT1:TAMR
13h = GPT1B interrupt event, controlled by GPT1:TBMR
79h = Always asserted

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

383

Interrupts and Events Registers

www.ti.com

4.7.2.93 CM3NMISEL0 Register (Offset = 800h) [reset = 63h]
CM3NMISEL0 is shown in Figure 4-102 and described in Table 4-107.
Return to Summary Table.
Output Selection for NMI Subscriber 0
Figure 4-102. CM3NMISEL0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R-63h

Table 4-107. CM3NMISEL0 Register Field Descriptions
Bit

384

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

63h

Read only selection value
63h = Watchdog non maskable interrupt event, controlled by
WDT:CTL.INTTYPE

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.94 I2SSTMPSEL0 Register (Offset = 900h) [reset = 5Fh]
I2SSTMPSEL0 is shown in Figure 4-103 and described in Table 4-108.
Return to Summary Table.
Output Selection for I2S Subscriber 0
Figure 4-103. I2SSTMPSEL0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-5Fh

Table 4-108. I2SSTMPSEL0 Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

R/W

5Fh

Read/write selection value
0h = Always inactive
5Fh = RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
60h = RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
61h = RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6
62h = RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7
79h = Always asserted

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

385

Interrupts and Events Registers

www.ti.com

4.7.2.95 FRZSEL0 Register (Offset = A00h) [reset = 78h]
FRZSEL0 is shown in Figure 4-104 and described in Table 4-109.
Return to Summary Table.
Output Selection for FRZ Subscriber 0
Figure 4-104. FRZSEL0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
EV
R/W-78h

Table 4-109. FRZSEL0 Register Field Descriptions
Bit

386

Field

Type

Reset

Description

31-7

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

R/W

78h

Read/write selection value
0h = Always inactive
78h = CPU halted
79h = Always asserted

Interrupts and Events

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events Registers

www.ti.com

4.7.2.96 SWEV Register (Offset = F00h) [reset = 0h]
SWEV is shown in Figure 4-105 and described in Table 4-110.
Return to Summary Table.
Set or Clear Software Events
Figure 4-105. SWEV Register
31

28
RESERVED
R-0h

24
SWEV3
R/W-0h

20
RESERVED
R-0h

16
SWEV2
R/W-0h

12
RESERVED
R-0h

8
SWEV1
R/W-0h

4
RESERVED
R-0h

0
SWEV0
R/W-0h

Table 4-110. SWEV Register Field Descriptions
Bit
31-25
24
23-17
16
15-9
8
7-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWEV3

R/W

Writing "1" to this bit when the value is "0" triggers the Software 3
event.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWEV2

R/W

Writing "1" to this bit when the value is "0" triggers the Software 2
event.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWEV1

R/W

Writing "1" to this bit when the value is "0" triggers the Software 1
event.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWEV0

R/W

Writing "1" to this bit when the value is "0" triggers the Software 0
event.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interrupts and Events

387

Chapter 5
SWCU117G – February 2015 – Revised February 2017

JTAG Interface
This chapter describes the cJTAG and JTAG interface for on-chip debug support.

388

Topic

...........................................................................................................................

5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9

Top-Level Debug System ...................................................................................
cJTAG .............................................................................................................
ICEPick ...........................................................................................................
ICEMelter .........................................................................................................
Serial Wire Viewer (SWV) ...................................................................................
Halt In Boot (HIB)..............................................................................................
Debug and Shutdown ........................................................................................
Debug Features Supported Through WUC TAP ....................................................
Profiler Register ...............................................................................................

JTAG Interface

Page

389
391
396
406
407
407
407
408
409

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Top-Level Debug System

www.ti.com

Table 5-1. References

5.1

Description

[1]

IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Std 1149.1a
1993 and Supplement Std. 1149.1b 1994, The Institute of Electrical and Electronics
Engineers, Inc.

[2]

IEEE 1149.7 Standard for Reduced-Pin and Enhanced-Functionality Test Access Port
and Boundary-Scan Architecture

Top-Level Debug System
The debug subsystem in the CC26x0 and CC13x0 devices implements two IEEE standards for debug and
test purposes:
• IEEE standard 1149.1: Standard Test Access Port and Boundary Scan Architecture Test Access Port
(TAP) [1]. This standard is known by the acronym JTAG.
• Class 4 IEEE 1149.7: Standard for Reduced-pin and Enhanced-functionality Test Access Port and
Boundary-scan Architecture [2]. This is known by the acronym cJTAG (compact JTAG). This standard
serializes the IEEE 1149.1 transactions using a variety of compression formats to reduce the number
of pins needed to implement a JTAG debug port.
The debug subsystem also implements a firewall for unauthorized access to debug/test ports. Figure 5-1
shows a block diagram of debug subsystem.
Figure 5-1. Top-Level Debug System
AON voltage domain
1149.1

MCU voltage domain

TAP

CPU

eFuse TAP
TAP PRCM

CPU power reset clock control /status

PBIST1.0 TAP

1149.1

PBIST2.0 TAP

JTAG power domain

Test TAP

1149.1

Standby
ICEMelter

TDO

TDI

2/4pin

TDO/DIO

TDI/DIO

WUC

TMS

I/O MUX

TCK

TAP

cJTAG

Wakeup

Global power reset clock control
/
status

ICEPick

I/O

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

JTAG Interface

389

Top-Level Debug System

www.ti.com

The IEEE 1149.1 TAP uses the following signals to support the operation:
• TCK (Test Clock): This signal synchronizes the internal state machine operations.
• TMS (Test Mode Select): This signal is sampled at the rising edge of TCK to determine the next state.
• TDI (Test Data In): This signal represents the data shifted into the test or programming logic of the
device. TDI is sampled at the rising edge of TCK when the internal state machine is in the correct
state.
• TDO (Test Data Out): This signal represents the data shifted out of the test or programming logic of
the device and is valid on the falling edge of TCK when the internal state machine is in the correct
state.
There is no dedicated I/O pin for TRST. The debug subsystem is reset with system-wide resets and
power-on reset.
The TAP controller, a state machine whose transitions are controlled by the TMS signal, controls the
behavior of the JTAG system. Figure 5-2 shows the state-transition diagram for JTAG.
Figure 5-2. JTAG State Machine
TMS=1
Test Logic Reset
TMS=0

TMS=0

Run Test Idle
TMS=1
Select DR Scan

Select IR Scan
TMS=1

TMS=1
TMS=0
TMS=1

Capture DR
TMS=0

TMS=0

Shift DR

TMS=0
Shift IR

TMS=1
TMS=1

Exit 1 DR
TMS=0

TMS=1

Capture IR

Exit 1 IR

TMS=0

Pause DR

Pause IR

TMS=1
Exit 2 DR

TMS=1

TMS=0

TMS=1
Update DR
TMS=1

TMS=0

Exit 2 IR

TMS=0

TMS=1
Update IR

TMS=0

TMS=1

TMS=0

Every state has two exits, so all transitions can be controlled by the single TMS signal sampled on TCK.
The two main paths allow for setting or retrieving information from either a data register (DR) or the
instruction register (IR) of the device. The data register depends on the value loaded into the instruction
register.

390

JTAG Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

cJTAG

www.ti.com

5.2

cJTAG
This module implements IEEE 1149.7 compliant compact JTAG (cJTAG) adapter, which runs a 2-pin
communication protocol on top of a IEEE 1149.1 JTAG test access port (TAP). The 2-pin JTAG mode
using only TCK and TMS I/O pads is the default configuration after power up. The cJTAG configuration in
CC26x0 and CC13x0 devices implements a subset of class 4 feature scan modes. Class 4 inherits
features from classes 0, 1, 2, and 3 (except the features mentioned in Table 5-3.) Figure 5-3 shows
conceptual diagram of the cJTAG module.
Figure 5-3. cJTAG Conceptual Diagram
Class 2
Jscan 2

Class 4
JScan3
MultiDrop

Class 1

Mscan,
Oscan 0-7

Jscan 0,1

1149.1
Compliance
Class 0

ExtCmds

Delays

Pwr Ctl

SScan 0-3
Class 3

BDX

CDX
Class 5

•
•
•
•
•

Class 0: Strict compliance to IEEE 1149.1 specification with internal TAP selection
Class 1: Adds cJTAG command protocol, some optional discrete commands
Class 2: Adds serial select capability
Class 3: Adds JTAG star configuration, controller IDs and scan selection directives
Class 4: Adds advanced scan protocols

Table 5-2 lists the features in IEEE 1149.7 that are supported in CC26x0 and CC13x0 devices. The
cJTAG module in the CC26x0 and CC13x0 devices supports 12 scan formats. The scan formats use a
variety of compression protocols ranging from 1 to 4 clocks per bit to serialize each packet.
Table 5-2. IEEE 1149.7 Feature Subset

Configuration

Optional components

Power control

IEEE 1149.7 Feature

Device Support Through
cJTAG

Comment

Class 4 TAP

Yes

Supports 2-pin operation

Class 5 TAP

Data and custom channels for
background data transfer

FRST

Functional reset

TRST

Test reset

RDBK capability

Readback of register data

Aux pin functions

Yes

Reuse of TDI and TDO pins

TCKWID

Programmable TCK width

Power down logic

Power down logic capability for
cJTAG module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

JTAG Interface

391

cJTAG

www.ti.com

Table 5-2. IEEE 1149.7 Feature Subset (continued)

Scan formats

IEEE 1149.7 Feature

Device Support Through
cJTAG

Comment

JScan0

Yes

Parallel mode

JScan1

Yes

Parallel with firewall

JScan2

Yes

Parallel with super bypass select

JScan3

Yes

Parallel with register select

MScan

Multidevice mode, supports stalls

OScan0

Yes

Supports stalls

OScan1

Yes

Non-stall mode

OScan2

Yes

Bidirectional transfers, pipelined

OScan3

Yes

Host to target only, pipelined

OScan4

Yes

Supports stalls

OScan5

Yes

Pipelined

OScan6

Yes

Bidirectional transfers, pipelined

OScan7

Yes

Host to target only, pipelined

SScan0

Segmented scan

SScan1

Segmented scan, supports stalls

SScan2

Segmented scan

SScan3

Segmented scan, supports stalls

Table 5-3. OScan Scan Packet Contents
Scan
Format
OScan0

nTDI

TMS

OScan1

nTDI

TMS

RDY

Shift States
TDO

nTDI

TMS

TDO

RDY

TDO

nTDI

TMS

TDO

OScan2

TMS

nTDI

TMS

TDO

OScan3

TMS

nTDI

TMS

OScan4

nTDI

TMS

OScan5

nTDI

TMS

RDY

TDO

nTDI

TDO

nTDI

OScan6

TMS

nTDI

OScan7

TMS

nTDI

(1)

392

Nonshift States

RDY

TDO
TDO

TMS (1)

TDO

TMS is present for the first packet of the shift.

JTAG Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

cJTAG

www.ti.com

5.2.1 JTAG Commands
cJTAG commands are conveyed through benign JTAG scan activity.
The following are three basic steps:
1. Loading an inert opcode
2. Setting control level 2
3. Issue commands
Before cJTAG commands are issued, the controller must ensure the scan activity will not initiate any
unexpected actions in the device. To accomplish this, an inert opcode such as BYPASS or IDCODE must
be loaded into the instruction register. Normally bypass is used, because its value (all ones) is dictated by
the IEEE 1149.1 specification.
Command detection is enabled by performing two zero bit scans (ZBS), then a 1-bit shift. A ZBS is
defined as a scan sequence that traverses through the Capture DR state and eventually the Update DR
state without ever touching the Shift DR state. The scan sequence can enter Pause DR state for any
number of clocks, or skip the Pause DR state altogether. Each successive ZBS increments the control
level. The control level is locked when the first Shift DR state occurs.
When the control level is locked, commands are issued by pairs of DR scans, and sometimes a third DR
scan. The number of clocks spent in the Shift DR state is counted for each scan (from 0 to 31 clocks). The
first DR scan, command part 0 (CP0) forms the opcode of the command. The second DR scan, command
part 1 (CP1), provides additional information about the command. This may be more opcode bits or a data
field, depending upon the opcode.
There are three commands (SCNB, SCNS, and CIDA) that require a third DR scan, command part 2
(CP2), to transport data in or out of the device. Table 5-4 shows the commands.
Table 5-4. cJTAG Commands
OPCODE

Instruction
STMC Store Miscellaneous Control
Operand: bbbxy
bbb
State control
xy
0

NOP

ExitCmdLev (ECL)

Exit/suspend (SUSPEND = 1)

ZBS Inhibit (ZBSINH = 1)

Scan Control
x
1
00000

Scan Group Candidate (SGC)
SGC = y

Conditional Group Member (CGM)
CGM = y

Ready Control
RDYC = xy
With a scan format other than the MScan scan format, the number of logic 1
RDY bits preceding the last bit of the SP payload is xy + 1

Delay control (DLYC)
DLYC = xy
xy
3

4-7

No DTS delay is added

Add one TCKC signal period

Add two TCKC signal periods

Add a variable number of TCKC signal periods

Reserved

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

JTAG Interface 393

cJTAG

www.ti.com

Table 5-4. cJTAG Commands (continued)
OPCODE

Instruction
STC1 Store Conditional 1 bit
Operand: cbbbv
bbb

00001
0

1-7

Sampling Edge (SEDGE)
Defines the TCKC signal edge used to sample the TMSC signal input
SEDGE==0: Sample the TMSC signal with the TCKC signal falling edge
SEDGE==1: Sample the TMSC signal with the TCKC signal rising edge
C
0

SEDGE = v

SEDGE = v if CGM == 1

Reserved

STC2 Store Conditional 2 bit
Operand: cbbvv
bb
0-1
00010
2

Reserved
Auxiliary Pin Function Control (APFC)
APFC==00: No change in the default pin function.
APFC==01: The pin function becomes the standard pin function.
APFC==1x: The pin function becomes the auxiliary pin function.
C
0

APFC = vv

APFC = vv if CGM == 1

Reserved

STFMT Store Scan Format
Operand: nnnnn
nnnnn

00011

JSCAN0

JSCAN1

JSCAN2

JSCAN3

4-7

Reserved

OSCAN0

OSCAN1

OSCAN2

OSCAN3

OSCAN4

OSCAN5

OSCAN6

OSCAN7

16-31

Reserved

MSS Make Scan Selection
Operand: miiii
m
00100

00101–00110

394 JTAG Interface

SGC bit of the targeted controller is set
SGC bit of a nontargeted controller is cleared

SGC bit of the targeted controller is set
SGC bit of a nontargeted controller is not affected

Reserved

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

cJTAG

www.ti.com

Table 5-4. cJTAG Commands (continued)
OPCODE

Instruction
CCE Conditional Command Enable
Operand: miiii
m

00111

CGM bit of the targeted controller is set
CGM bit of a nontargeted controller is cleared

CGM bit of the targeted controller is set
CGM bit of a nontargeted controller is not affected

SCNB Scan Bit
Operand: yyyyy + CR Scan
yyyyy
01000

01001–11111

5.2.1.1

SGC, Scan Group Candidate, write

CGM, Conditional Group Member, write

02-05

CNFG0-3, TAP.7 Controller class, read

06-31

Reserved

Mandatory Commands

Three mandatory commands are used to manage command processing. These commands are
subcommands of STMC and are Exit Command Level, Suspend, and ZBSINH. The last two commands
can be used if the device uses ZBSs for its own purposes.
• Exit Command Level terminates command processing.
• Suspend inhibits command detection until a special sequence is detected.
• ZBSINH inhibits command detection until a reset occurs.

5.2.2 Programming Sequences
5.2.2.1

Opening Command Window

Before the cJTAG module accepts any commands, the control level must be set to 2 and locked.
1. Scan IR (bypass, end in Pause DR): Load benign opcode into the instruction register.
2. Goto Scan (through Update DR, end in Pause DR): This is the first ZBS.
3. Goto Scan (through Update DR, end in Pause DR): This is the second ZBS.
4. Scan DR (1 bit, end in Pause DR): This locks the control level at 2.
Opening the command window decouples the device TAP; the decoupling occurs when the second ZBS
occurs.
5.2.2.2

Changing to 4-Pin Mode

When the command window is open, commands can be issued. To change to 4-pin mode, APFC must be
written to 1 (using STC2 command), which assumes the TAP state is starting from Pause DR.
1. Scan DR (2 bits of 1, end in Pause DR): Load CP0 with 2.
2. Goto Scan (Through Update DR to Pause DR): Complete CP0 by going through update.
3. Scan DR (9 bits of 1, end in Pause DR): Load CP1 with 9.
4. Goto Scan (Through Update DR to Pause DR): Complete CP1 by going through update.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

JTAG Interface

395

ICEPick

5.2.2.3

www.ti.com

Close Command Window

The command window can be closed by doing an IR scan, going to test logic reset, or by an ECL
command. The ECL command is a subcommand of the STMC (opcode 0) command. The ECL command
assumes the TAP state is starting from Pause DR.
1. Goto Scan (Through Update DR to Pause DR): Does a Zero Bit scan to load CP0 with 0.
2. Scan DR (1 bit, end in Pause DR): Load CP1 with 1.
3. Goto Scan (Through Update DR to Pause DR): Complete CP1 by going through update.
NOTE: When the command window is closed, the device TAP couples so any subsequent scans (IR
or DR) are issued to the device TAP.

5.3

ICEPick
ICEPick is the primary TAP in the chip. It acts as the IEEE 1149.1 JTAG-compliant top-level router for the
chip. Conceptually, ICEPick can be viewed as a bank of switches that can connect or isolate a modulelevel TAPs to and from the higher level chip TAP. The module-level TAPs are called secondary TAPs,
while the primary TAP and external JTAG signals are called the master scan path. The ICEPick TAP
appears as the first TAP and only TAP in the scan path following a power on. None of the secondary
TAPs are selected or visible in the master scan path. From the perspective of the external JTAG interface,
secondary TAPs that are not selected appear to not exist. The ICEPick TAP has several scan paths of its
own to support secondary TAP selection, control, and status. ICEPick enables dynamic scan chain
management and can select one or several slave TAPs and link them in the scan chain.
A number of control bits are associated with each secondary TAP within ICEPick. Some of these bits
apply strictly to the TAP being managed by ICEPick, while others apply to the whole subsystem or power
domain in which the secondary TAP resides. These control bits deal with the TAP selection for inclusion in
the scan path, secondary TAP test reset management, and debug attention needed.
A number of status bits are associated with each secondary TAP within ICEPick. These status bits report
the accessibility, visibility, power, and clock states.
The communication protocol can be changed to 4-pin configuration after establishing connection between
debug application and on chip cJTAG TAP using 2-pin mode. When cJTAG switches to 4-pin mode, TDI
and TDO are mapped automatically to pins through IOC and this has precedence over any other function
that was mapped to corresponding pads before switching occurs. Switching from 4-pin to 2-pin mode is
also supported.

5.3.1 Secondary TAPs
Each secondary TAP has been assigned a number. The TAP numbering is linear and starts with 0. The
number assigned to a secondary TAP corresponds to its location within the secondary control and status
registers in ICEPick. The first selected TAP is the TAP with the lowest number, while the last selected
TAP is the TAP with the highest number. The ICEPick module has a firewall for unauthorized access of
slave TAPs. Table 5-5 lists the available TAPs, their corresponding order, and the availability of these
TAPs for end user. The open TAPs can be locked by writing to the corresponding field in the customer
configuration area.

396 JTAG Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

ICEPick

www.ti.com

Table 5-5. Slave TAP Order
Number

Test TAP Name

Description

Availability for End User

TEST

DFT functionalities and profiler

See

PBIST1.0

RAM BIST controller interface

Locked

PBIST2.0

ROM BIST controller interface

Locked

eFuse

eFuse interface for SRAM repair

Locked

PRCM

PD override control/status in MCU VD

Locked

AON WUC

VD override control/status

See

(2)

CM3

DAP for CM3 debug

See

(2) (3)

Test Banks
(1)

Debug Banks
0
(1)

(2)

(3)

The test TAP is locked for all devices except CC1350, CC2640R2 and CC2650. This TAP implements a profiler register that can be used
to extract runtime information about program execution and general chip status. The access to this TAP can be blocked by writing to the
corresponding field in the customer configuration area (see Section 9.1).
Some of the registers in AON WUC TAP are open for end user. This includes registers for requesting chip erase, system reset, and MCU
reset.
The access to debug port of the CPU can be blocked by writing to corresponding field in customer configuration area (see Section 9.1).

5.3.1.1

Slave DAP (CPU DAP)

The debug subsystem has only one slave DAP (CPU DAP). This debug port implements Serial Wire JTAG
Debug Port (SWJ-DP) interface, which allows external access to an Advanced High-performance Bus
Access Port (AHB-AP) interface for debug accesses in the CPU.
The SWJ-DP is a standard ARM CoreSight™ debug port that combines JTAG-DP and Serial Wire Debug
Port (SW-DP). Even though the SW-DP interface is supported by SWJ-DP, the CC26x0 and CC13x0
devices do not use this mode. The key reason is that SW-DP becomes redundant for the design in the
presence of the 2-pin JTAG (1149.7) mode.
5.3.1.2 Ordering Slave TAPs and DAPs
• When a single secondary TAP is selected, it is effectively connected to the TDO of the ICEPick TAP.
• When one or more secondary TAPs are selected, they are linked from the lowest numbered TAP to the
highest numbered TAP.
• The lowest-numbered TAP selected is connected closest to the device-level TDI (except for ICEPick),
while the highest numbered TAP is connected closest to the device TDO.
• Any selected TAPs within the test bank are linked before any TAPs within the debug bank (for
example, DAP).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

JTAG Interface

397

ICEPick

www.ti.com

5.3.2 ICEPick Registers
Table 5-6 lists the control and status registers in ICEPick.
Table 5-6. Register Summary

5.3.2.1

Abbreviation

Width

Number

Description

Data Shift Register

DSR

TAP Data Register

Instruction Register

TAP Instruction Register

Bypass Register

Bypass

Used by the BYPASS instruction

Device Identification Register

TAPID

Device ID used with IDCODE

User Code Register

User Code used with USERCODE

ICEPick Identification

IPID

Version of ICEPick

Connect

Connect code

Secondary Debug TAP Register
(SDTR)

SDTR

One register exists for each debug
TAP instantiated. It is used to control
selection, power, reset, and the clock
associated with each TAP.

Secondary Test TAP Register
(STTR)

STTR

One register exists for each test TAP
instantiated. It is used to control
selection of each TAP.

Reserved

SUTR

Reserved

Linking Mode

LMR

Specifies how ICEPick manages the
TAP selection.

ICEPick Control

IPCR

General ICEPick control

IR Instructions

The ICEPick TAP supports the instructions listed in Table 5-7. All unused TAP controller instructions
default to the bypass register. Several instructions are reserved for extensions to the ICEPick opcodes.
Refer to for device identification register descriptions.
Table 5-7. Instruction Register Opcodes

398

ICEPick Instruction

Access

000000, 111111

BYPASS

Always-open

ROUTER

Connected

100

IDCODE

Always-open

101

ICEPICKCODE

Always-open

111

CONNECT

Always-open

1000

USERCODE

Always-open

000001, 000011,
000110,
001001–111110

Reserved

JTAG Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

ICEPick

www.ti.com

5.3.2.2

Data Shift Register

Figure 5-4 is the register used to shift bits between the ICEPick TDI and TDO. This register is 32-bits
wide. The data shift register has multiple shift in points to facilitate shifts on the instruction path and
several of the data paths.
Figure 5-4. Data Shift Register
Bit

TDI
Access
Reset

1 0
Bypass
TDI
Instruction Shift
TDI
Connection Shift

TDI
Router or ID Shift
Broad side load and store, serial shift
0

TDO
TDO
TDO
TDO

When asked to shift, 1 bit is shifted from each bit into the next lower bit. A new value is shifted in from TDI
while the least significant bit is shifted out to TDO. The shift register has several insertion points based on
the current TAP state or value in the instruction register.
5.3.2.3

Instruction Register

This register contains the current TAP instruction. The ICEPick IR is 6-bits wide.
Figure 5-5. Instruction Register
Bit
TDI
Access
Reset

5
0
Instruction
W
IDCODE

TDO

See Table 5-7 for valid IR opcodes.
5.3.2.4

Bypass Register

This register is a 1-bit register. The value that is scanned in TDI is preserved and scanned out of TDO one
TCK cycle later.
Figure 5-6. Bypass Register
Bit
TDI
Access

5.3.2.5

0
Bypass
R/W

TDO

Device Identification Register

This register allows the manufacturer, part number, and version of the device to be determined through
the TAP. The device identification register is scanned in response to the IDCODE instruction.
IDCODE has three fields: version, part number, and manufacturer.
Figure 5-7. Device Identification Register
Bit
TDI
Access
Reset

31
28
Version
R
VERSION[3:0]

27
12
Part Number
R
PARTNUM[15:0]

11
1
Manufacturer
R
000 0001 0111b.

0
1
R
1

TDO

The contents of this register are replicated to a device configuration area which is memory mapped. Refer
to FCFG1:ICEPICK_DEVICE_ID in Section 9.2.2.1.53 for details of this register.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

JTAG Interface

399

ICEPick

www.ti.com

Table 5-8. Device Identification Register Description
Field

Width

Description

Version

Revision of the device

Part Number

Part number of the device

Manufacturer

TI’s JEDEC bank and company code: 00000010111b

This bit is always 1

5.3.2.6

User Code Register

The User Code Register helps to distinguish between the devices built from the same chip. The User
Code register value is set through eFuse. Each variant is uniquely identified by feature set or pinned out
interface.
The User Code Register is a 32-bit register that specifies the version and part number of the component.
The contents of this register is replicated to device configuration area that is memory mapped. Refer to
Figure 5-8 and Table 5-9 for details of this register.
Figure 5-8. User Code Register
Bit
TDI
Access
Reset

31
28
Version
R
VERSION[3:0]

27
12
Variant Number
R
VARIANT[15:0]

11
1
Reserved
R
0

0
1
R
1

TDO

Table 5-9. User Code Register Description

5.3.2.7

Field

Width

Description

Version

Revision of the device. This field must change each time
that the logic or mask set of the device is revised. The
initial value is 0.

Variant Number

Variant of chip. The decoding of this field is shown in
Section 9.2.2.1.40.

Reserved

Bit 0 is always 1

ICEPick Identification Register

This register indicates the features and version of the ICEPick module (do not confuse the ICEPick IR with
the device IR).
The ID register is a 32-bit register that specifies the version and features of the ICEPick module. See
Table 5-10 for a description of the ICEPick IR.
Figure 5-9. ICEPick Identification Register
Bit
TDI

31
24 23 20
Version
Test
TAPs
R
R
0x41
6

Access
Reset

19 16
EMU
TAPs
R
1

15
4 3
0
ICEPick Type Capabilities
R
0x1CC

TDO

R
*

Table 5-10. ICEPick Identification Register Description

400

Field

Width

Description

Version

Revision of ICEPick

Test TAPs

Number of Test TAPs

EMU TAPs

Number of EMU TAPs

ICEpick Type

An identifier of the ICEpick Type
This field is set to 0x1CC, which corresponds to Type C.

Capabilities

Reserved

JTAG Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

ICEPick

www.ti.com

5.3.2.8

Connect Register

This register guards the device from noise, hot connection of an emulator cable, or accidental scan by a
misconfigured scan controller. This register reduces the chances of accidentally engaging debug functions
due to noise or accidental scans. Refer to Figure 5-10 and Table 5-11 for more details.
Figure 5-10. Connect Register
Bit
TDI
Access
Reset

7
Write
W
0

6
4
Reserved
R
0

3
0
ConnectKey
R/W
b0110

TDO

Table 5-11. Connect Register
Bit

Field

Width

Type

Reset

Description

Write Enable

Must be 1 to write the Connect Key. A value of 0 is a read.
When read, a value of 0 is returned.

6–4

Reserved

3–0

ConnectKey

R/W

0110

When this field holds the key code of 1001, the scan controller
is considered to be connected. All other values are in the notconnected state. In this state, only a limited number of IR
instructions are valid.

5.3.3 ROUTER Scan Chain
This register accesses all TAP linking and control registers. The scan chain is 32-bits long. Refer to
Table 5-12 for more information.
Figure 5-11. ROUTER DR Scan Chain
Bit
TDI

31
Write Enable /
Write Failure
R/W

Access

30
28
Block Select

27
24
23
0
Register Number Register Value

TDO

R/W

Table 5-12. ROUTER DR Scan Chain Description
Bit

Field

Write Enable

Width

Type

Reset

Description
On scan-in:
0: Only a read is performed.
1: A write to the specified register is performed.
On scan-out:
If the previous scan resulted in a write to a ROUTER addressed
register, then when bit 31 is scanned out during the next trip
through the Shift DR state, it indicates whether the previous
write succeeded. If 1, the previous write failed. If 0, the previous
write was successful.
A write to a debug or test secondary TAP control and status
register may fail for a number of reasons including:
• ICEPick is in the disconnected state.
• The TapPresent bit is 0, which indicates that a TAP does
not exist at this location.
• The TapEnable bit is 0, which indicates that security or
other reasons are currently preventing access to this TAP.
• A previous programming of the ResetControl or
ReleaseFromWIR bits has not been processed yet.
Block select:
000: ICEPick Control (see Section 5.3.4.1)

30–28

Block Select

R/W

000

001: Test TAP Linking Control Block (see Section 5.3.4.2)
010: Debug TAP Linking Control Block (see Section 5.3.4.3)
011–111: Reserved

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

JTAG Interface 401

ICEPick

www.ti.com

Table 5-12. ROUTER DR Scan Chain Description (continued)
Bit

Field

Width

Type

Reset

Description

27–24

R/W

0000

This field specifies the register within the selected block (See
Table 5-13, Table 5-15, and Table 5-20)

23–0

Selected Register
Contents

–

Based on the values in Block Select and Register Number fields;
the corresponding register is mapped to this field.

During the Capture DR state, the Data Shift Register is inspected. The register specified by the Block and
Register fields is read and the value is placed in the lower 24 bits of the Data Shift Register.
NOTE: The current contents of the Data Shift register were those loaded by the previous scan.

The register specified in DR scan n 1 is read during scan n. Of course, if an intervening IR scan occurs,
the contents of the Data Shift Register are unpredictable, so a read of the register indicated in DR scan n
1 does not occur.
Sometimes an action on the destination register is still pending when the Update DR state is reached.
Some of the bits of the destination register may not be changed while the action is pending, such as the
reset controls signals have been written but not acted upon yet. Therefore, the new value indicated by this
write may not be applied to the register. If this happens, the write to the ICEPick register is suppressed
and the write-failure flag is set to 1. The write-failure bit is captured into the Data Shift Register at bit 31.
When the value has been captured, the WF flag is cleared.
If bit 31 indicates that a read must be performed, the ICEPick register specified is not touched at this
point. The ICEPick register contents remain undisturbed.
If the contents of the Data Shift Register remain constant until the next Capture DR state, then the
specified register is read at that point. An intervening IR scan disturbs the Data Shift Register contents
and as a consequence, it cannot be assured that the register specified will be read.
There is no address buffering within the ICEPick for the read block and register other than the Data Shift
Register. No extra storage is needed when the proper scan sequence is followed. Refer to Section 5.5 for
the sequence.

5.3.4 TAP Routing Registers
This section describes the TAP routing registers that can be accessed using router scan.
5.3.4.1

ICEPick Control Block

The ICEPick Control Block implements the Table 5-13. Reads of unused registers return all 0s.
Table 5-13. Control Block Registers

402

0x0

All0s

0x1

Control

0x2

Linking Mode

0x3–0xF

Reserved

JTAG Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

ICEPick

www.ti.com

5.3.4.1.1 All0s Register
This register is a dummy register that returns 0 when read. Writes are ignored. There are not any side
effects to writing or reading this register.
Table 5-14. All0s Register
Bit

Field

Width

Type

Reset

Description

23–0

Zero

Read zero

5.3.4.1.2 ICEPick Control Register
Table 5-15. ICEPick Control Register
Bit

Field

Width

Type

Reset

Description

23–7

Reserved

R/W

Reserved

BlockSysReset

R/W

When 1, the device system reset signal is blocked.

5–1

Reserved

R/W

Reserved

Emulator controlled System Reset
This signal provides the scan controller with the ability to
assert the system warm reset. When a 1 is written, this
behaves as if the external chip warm reset signal had
been momentarily asserted. This signal does not reset
any emulation logic. This is a self-clearing bit. This is
cleared by the assertion of the reset requested.
Writing a 0 has no effect.

SystemReset

R/W

5.3.4.1.3 Linking Mode Register
Table 5-16. ICEPick Linking Mode Register
Bit

Field

Width

Type

Reset

Description

23–4

Reserved

R/W

0x0

Reserved

3–1

TAPLinkMode

R/W

See Table 5-17

ActivateMode

R/W

When a 1 is written to this bit, the currently selected
TAPLinkMode is activated. ICEPick links the TAPs
according to these settings when the ICEPick TAP is
advanced to Run Test-Idle with any opcode in the IR.

Table 5-17. ICEPick TAP Link Mode
Value

Mode

Behavior

000

Always-first

ICEPick TAP always exists and is linked as the TAP closest to TDI.

011

Disappear-forever

When activated, the ICEPick TAP is no longer visible between the device
TDI and TDO. Only a power-on reset makes the TAP visible again.

001–010, 100–111

Reserved

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

JTAG Interface

403

ICEPick

www.ti.com

5.3.4.2

Test TAP Linking Block

The Test TAP Linking block contains the control and status registers shown in Table 5-18. These registers
are used in to select of secondary TAPs into the master scan path. Each TAP has its own Test TAP
Control and Status Register.
Table 5-18. Test TAP Linking Registers
Register

0x0

Secondary Test TAP 0 Register

0x1

Secondary Test TAP 1 Register

0x2

Secondary Test TAP 2 Register

0x3

Secondary Test TAP 3 Register

0x4

Secondary Test TAP 4 Register

0x5

Secondary Test TAP 5 Register

0x6–0xF

Reserved

5.3.4.2.1 Secondary Test TAP Register
Table 5-19. STTR – Secondary Test TAP Register

5.3.4.3

Bit

Field

Width

Type

Reset

Description

23–10

Reserved

R/W

Reserved

VisibleTAP

–

See Table 5-21.

SelectTAP

R/W

See Table 5-21.

7–2

Reserved

TapAccessible

–

See Table 5-21.

TapPresent

–

See Table 5-21.

Debug TAP Linking Block

The Debug TAP Linking block contains the control and status registers used in the selection of secondary
TAPs into the master scan path. The secondary debug tap has its own Debug TAP Control and Status
register. Refer to Table 5-20 for more details.
Table 5-20. Debug TAP Linking Registers

404

0x0

Secondary Debug TAP 0 Register

0x1–0xF

Reserved

JTAG Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

ICEPick

www.ti.com

5.3.4.3.1 Secondary Debug TAP Register
Table 5-21 shows the secondary debug TAP register (SDTR).
Table 5-21. Secondary Debug TAP Register (SDTR)
Bit

Field

Width

Type

Reset

Description

23–21

Reserved

R/W

Reserved

When 0, this bit does not influence the clock and the power
settings to the module.
While this bit is 1, power or clock for the module of the TAP is
not allowed to be turned off once it is turned on.
If the target does not have power or clock when setting this bit,
InhibitSleep does not change the power/clock state until the
target is powered and clocked again.

–

The value read does not reflect the value written until the
power and clock controller has acted upon a change in the
written value.

–

Reserved

–

The InReset status and the ReleaseFromWIR control share the
same bit.
When 1, the module or modules controlled by the secondary
TAP is in the reset state.
When 0, the module or modules is not in reset.

The InReset status and the ReleaseFromWIR control share the
same bit.
When a 1 is written to this bit and the module is held in reset
due to the WaitInReset bit, the module reset is released. This
only occurs if WaitInReset is 1 and it is the only cause for
holding the module in reset. This is a self-clearing bit.
Writing a 0 has no effect.

19–18

InhibitSleep

Reserved

InReset

17
ReleaseFromWIR

16–14

ResetControl

R/W

Override the application controls of the functional warm reset to
a module. See Table 5-22.

13–10

Reserved

R/W

Reserved

–

When 1, the TAP is currently selected and visible in the active
scan chain.
The VisibleTap bit indicates that the TAP, which was previously
selected with the SelectTap bit, is now part of the device
master scan path. The VisibleTap bit is set by ICEPick when
the Run Test Idle state has been reached.

VisibleTAP

SelectTAP

R/W

The SelectTap bit allows scan controller software to change
which secondary TAPs are included in the device level master
scan path. When this bit is set to 1, the TAP is selected for
inclusion in the master scan path when the TAP state
advances to the Run Test Idle state. When this bit is changed
to 0, the TAP is deselected from the master scan path when
the TAP state advances to the Run Test Idle state. Selection or
deselection occurs in the Run Test Idle state regardless of the
current IR instruction.
Writes to the SelectTap bit are blocked, and the bit is held at 0,
if TapPresent is 0.

7–4

Reserved

R/W

Reserved

–

When ForceActive is 0, the module’s clock and power settings
follow the normal application settings unless one of the other
emulation controls is affecting the state. Setting the
ForceActive bit causes the power and clock held on and to be
turned on if necessary. In this sense, the ForceActive bit could
be named ForcePowerAndClock.
Clearing the ForceActive bit returns control of the power and
clock settings to the application. If the application controls
indicate that the power and clock must be off, the power and
clock to the module is turned off.

–

The value read does not reflect the value written until the
power and clock controller has acted upon a change in the
written value.

–

Reserved

ForceActive
(ForcePowerAndClock)

Reserved

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

JTAG Interface 405

ICEMelter

www.ti.com

Table 5-21. Secondary Debug TAP Register (SDTR) (continued)
Bit

Field

Width

Type

Reset

Description

TapAccessible

–

When 0, the TAP cannot be accessed due to security.
When 1, the TAP can be accessed.

TapPresent

–

When 0, there is not a TAP assigned to this spot.
When 1, this TAP exists in the device.
If a TAP does not exist, the rest of the controls and status bits
in this register are considered to be nonoperational.

Table 5-22. Reset Control

5.4

Value

Command

Description

000

Normal Operation

Reset operates under the normal control of the application or device
controls.

001

Wait in reset
(Extend reset)

The module or modules controlled by this secondary TAP remain in the
reset state when the reset has been asserted. This bit alone does not
reset the processor.

010

Reserved

011

Reserved

1xx

Cancel

Cancels reset command lockout

ICEMelter
ICEMelter wakes up the JTAG power domain, that contains ICEPick and cJTAG modules and monitors
the activities on the TCK-pin. When ICEMelter detects traffic on the TCK-pin (8 rising edges and 8 falling
edges on TCK), it sends a power-up request to the AON WUC that powers up the JTAG power domain.
The emulator must allow power-up time of at least 200 µs for JTAG power domain before sending
remaining commands to JTAG interface.
TI recommends that care is taken to avoid unintentional traffic on the TCK-pin. This can for example
happen if the TCK-pin is made accessible through a connector which is frequently connected and
disconnected, or is located on a pin row that is touched during regular use. Unintentional traffic on the
TCK-pin can cause the ICEMelter to power up the JTAG domain, which will add approximately 400 µA to
any device mode (including Standby), and also set the Halt In Boot (HIB) flag. The HIB flag will halt the
device on the subsequent boot (such as after any system reset other than pin reset or POR, or when
entering Shutdown). Exiting Halt In Boot, clearing the HIB flag, and disabling the JTAG domain can only
be done by a pin reset, a POR, or by using the JTAG interface itself.
NOTE: On the CC2640R2F device, the HIB flag will not halt the device on the subsequent boot if the
following conditions are met:
•
The reason for system reset must be entering and wakeup from shutdown.
•
AON_SYSCTL:RESETCTL[13:12] = 0b10 prior to entering shutdown.
If JTAG_PD is on upon entering shutdown, the chip will immediately wake up from shutdown
as soon as system reaches the shutdown state; thus behaving like a cold reset. This action
will then disable the HIB flag and disable the JTAG_PD.

The TCK pin has an internal pullup designed to avoid unintentional traffic due to noise, but it will not be
sufficient if there is risk of external activity on the TCK-pin caused by unintentional touching or shorting of
the pin. If it is not possible to guarantee that such activity does not happen, it is recommended that a
strong external pullup is used, or even shorting the pin to the supply voltage through a zero-ohm resistor.
The size of the pullup or whether the pin is shorted to the supply voltage, will be a tradeoff between
robustness against unintentional external activity and the need for an accessible debug port. If the TCK
pin is disabled by shorting it to the supply voltage, flash programming must be done using the bootloader.

406

JTAG Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Serial Wire Viewer (SWV)

www.ti.com

5.5

Serial Wire Viewer (SWV)
The CPU uses the TPIU macro inside the processor to support the serial wire viewer (SWV) interface (a
single line interface).
The following sequence is needed to enable SWV output on the CPU.
1. Enable trace system by setting CPU_SCS:DEMCR.TRCENA (see Section 2.7.4.59).
2. Unlock ITM configuration by writing to the Lock Access Register CPU_ITM:LAR (see Section 2.7.3.36).
3. Enable ITM by setting CPU_ITM:TCR.ITMENA (see Section 2.7.3.35).
4. Enable the desired stimulus port (0 to 31) in CPU_ITM:TER (see Section 2.7.3.33).
5. Change formatter configuration if needed CPU_TPIU:FFCR (see Section 2.7.5.6).
6. Change the pin protocol if needed CPU_TPIU:SPPR (see Section 2.7.5.4).
7. Set the baudrate in CPU_TPIU:ACPR (see Section 2.7.5.3).
8. The SWV can be mapped to DIO n by writing the corresponding port ID in the IOC:IOCFGn register
(see ) For more details, refer to Chapter 11).
Writes to the CPU_ITM:STIMn registers (assuming that they are enabled) trigger a transmit on SWV
output if the FIFO is not full.

5.6

Halt In Boot (HIB)
The CC26x0 and CC13x0 devices implement a mechanism to ensure that the external emulator can take
control of the device before it executes any application code. This mechanism is called halt in boot (HIB).
When HIB detects debug activity, the boot code stops in a wait for interrupt instruction (WFI) at the end of
its execution before jumping to the application code in Flash.
Detection of activities on the TCK pin (which powers up the JTAG power domain) is the condition for HIB
when next boot occurs. If JTAG power domain is turned off by entering the test logic reset (TLR) state
before a system reset occurs, the HIB conditions can be cleared. The HIB conditions are not cleared if
AON_WUC:SHUTDOWN.EN (see Section 6.8.2.3.7) is written to 1.
To exit HIB, the external emulator must connect to the device and first HALT, then RESUME the CPU
through DAP. After resuming, the program execution continues from the application code.

5.7

Debug and Shutdown
The debugger cannot stay connected in shutdown mode because the power source for debug subsystem
turns off in this mode. This means that entering shutdown causes abrupt disconnection from the emulator.
To facilitate debugging of the shutdown scenarios, the CC26x0 and CC13x0 devices have the following
considerations:
• If a device is in shutdown mode, activity on TCK causes immediate wake up.
• If conditions for HIB are met while entering shutdown mode, the device wakes up as soon as it
reaches the shutdown state.
NOTE: For CC13x0 and CC26x0, except for CC2640R2F, if either of these considerations occur, the
boot code (before handing control to the application code) waits in a loop until an I/O wakeup event occurs.

NOTE: For CC2640R2F, before entering a loop waiting for the I/O wake-up event, HIB conditions
will be checked again and the loop is skipped if HIB conditions are not met.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

JTAG Interface

407

Debug Features Supported Through WUC TAP

5.8

www.ti.com

Debug Features Supported Through WUC TAP
Table 5-23. Debug Features Supported Through WUC TAP

408

Command

Control Bits

Function

CHIP_ERASE_REQ

IR 0x01,
Bit 1 in DR[7:0]

Setting this bit (if it is followed by MCU VD Reset request through
WUC TAP) initiates chip erase.

MCU_VD_RESET_REQ

IR 0x01,
Bit 5 in DR[7:0]

Setting this bit requests reset of the entire MCU VD.

SHUTDOWN_W_JTAG

IR 0x01,
Bit 6 in DR[7:0]

1: Entering shutdown is postponed until JTAG is disconnected.
0: Allows the device to enter shutdown without waiting for
disconnection from JTAG. Entering shutdown causes abrupt
disconnection from the emulator.

SYS_RESET_REQ

IR 0x01,
Bit 7 in DR[7:0]

Setting this bit requests reset of the entire chip. The DEBUGEN bit
remains asserted after this reset, which ensures HIB after next
boot.

TMS_PAD_CFG

IR 0x0C,
Bits [5:0] in DR[6:0]

Strength and slew control setting for TMS pad.

MCU_VD_FORCE_ACTIVE

IR 0x0C,
Bit 6 in DR[6:0]

1: If MCU VD is off, Force Active powers up the MCU VD.
0: The application controls the MCU VD.

JTAG_DO_NOT_PU

IR 0x04,
Bit 0 in DR[6:0]

1: Prevent JTAG power domain from being powered up from the
ICEMelter.
0: ICEMelter powers up the JTAG power domain when wake-up
conditions are met.

JTAG_DO_NOT_RESET

IR 0x04
Bit 4 in DR[6:0]

1: Do not reset WUC tap when the JTAG power domain is powered
down.
0: WUC is reset when the JTAG power domain is powered down.

JTAG Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Profiler Register

www.ti.com

5.9

Profiler Register
This register can be used to extract runtime information from the chip with no intrusion to the code
execution. This register resides in the TEST TAP (the profiler register IR number is 0x06). For more
details, refer to Table 5-24.
Figure 5-12. Profiler Register
Bit
TDI
Access
Reset

77
0
Chip Status
R
Unknown

TDO

Table 5-24. Profiler Register Fields
Bit

Width

Description

77–61

Reserved

60–59

Sleep state of the CPU:
00: Run mode
01: Sleep mode
1x: Deep sleep mode

1: Warm reset in progress
0: No warm reset active

Error in values of compressed program counter
1: The value returned in bits 56–36 cannot be trusted.
0: The value returned in bits 56–36 can be trusted.

56–36

Compressed current program counter in the CPU

35–30

Current interrupt number in the CPU

29–26

Reserved

25–24

Power domain state of the AUX:
00: Off
01:Power down
10: Reserved
11: Active

State of the sensor controller in the AUX power domain:
0: Suspend
1: Running

22–21

MCU_VD state:
00: Off
01: Power down
10: Reserved
11: Active

1: CPU power domain is on.
0: CPU power domain is off.

1: SERIAL power domain is on.
0: SERIAL power domain is off.

1: PERIPH power domain is on.
0: PERIPH power domain is off.

1: RFCORE power domain is on.
0: RFCORE power domain is off.

1: VIMS power domain is on.
0: VIMS power domain is off.

15–12

RF core state:
0x0 No information is yet available or RF core is powered off.
0x1 The RF core is powered but idle (no RF).
0x2 The RF synthesizer is active.
0x6 The RF synthesizer is active.
0xE The RF core is receiving a packet.
0xA The RF core is transmitting a packet.
Others: Reserved

11–0

Reserved

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

JTAG Interface

409

Chapter 6
SWCU117G – February 2015 – Revised February 2017

Power, Reset, and Clock Management
This chapter details the flexible power management and clock control (PRCM) of the CC26x0 and CC13x0
devices.

410

Topic

...........................................................................................................................

6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8

Introduction .....................................................................................................
System CPU Mode ............................................................................................
Supply System .................................................................................................
Digital Power Partitioning ..................................................................................
Clock Management ...........................................................................................
Power Modes ...................................................................................................
Reset ..............................................................................................................
PRCM Registers ...............................................................................................

Power, Reset, and Clock Management

Page

411
412
413
415
416
422
426
429

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Introduction

www.ti.com

6.1

Introduction
Power and clock management (PRCM) in the CC26x0 and CC13x0 devices is highly flexible to facilitate
low-power applications. The following sections describe details for clock and power control in addition to
covering reset features.
The features in this chapter are embedded and optimized in TI-RTOS. TI-RTOS users may regard this
chapter as informative only.
Figure 6-1. Hierarchy of Power Saving Features

Voltage
regulator
Voltage domain (VD)

Power domain (PD)
Clock

Clock enable

Power domain (PD)
Clock gate
Periphial
(PD)
ClockPower
gate domain Periphial
Clock gate

Periphial

Figure 6-1 shows the hierarchy of power-saving features in the CC26x0 and CC13x0 devices. Low-power
consumption and cycling time for a power-saving mode is inversely proportional. The power-saving mode
with the lowest power consumption requires the longest time from initiation to power-saving mode, as well
as wake-up time back to active mode. Table 6-1 summarizes the power-saving features.
Table 6-1. Power Saving Features
Power Saving Feature

Description

Clock gating

Immediate response—no latency
Offers the least amount of power saved

Power domain off
(overrides clock gating)

Power cycling down and up takes longer time than clock gating. Modules in power domains without
retention must be reinitialized before functionality can be resumed.

Voltage domain off

Power cycling down and up takes a longer time than PD power off. All modules in the voltage
domain must be reinitialized before functionality can be resumed.

Voltage regulator off

Power cycling down and up takes a longer time than VD power off. Chip loses all configurations and
boots at wakeup. Gives the least possible current consumption.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

411

System CPU Mode

www.ti.com

Table 6-2 lists the four defined power modes for the power-saving features in TI-RTOS, as shown in
Table 6-1. Section 6.6 discusses the power modes in detail.
Table 6-2. Power Modes in TI-RTOS

6.2

Power Mode

Description

Active mode

The system CPU is running.

Idle mode

The power domain in which CPU resides is off.

Standby mode

All power domains are powered off and voltage domains are supplied by the micro LDO.

Shutdown mode

Only I/Os maintain their operation. All voltage regulators, voltage, and power domains are off.

System CPU Mode
The following chapter refers to the system CPU mode so it is important to understand what this means.
The system CPU has three different operation modes: run, mode, and deep sleep (see Table 6-3). Each
mode is used to gate internal clocks in the system CPU, in addition to peripheral clocks that may be gated
in accordance to the current system CPU mode. Deep sleep mode is, in some cases, one of several
requirements for powering down voltage and power domains.
Table 6-3. System CPU Modes

412

System CPU Mode

Description

Run mode

WFI and WFE both inactive, CPU_SCS:SCR.SLEEPDEEP is don’t care

Sleep mode

WFI or WFE active and CPU_SCS:SCR.SLEEPDEEP = 0

Deep sleep mode

WFI or WFE active and CPU_SCS:SCR.SLEEPDEEP = 1

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Supply System

www.ti.com

6.3

Supply System
The supply system of the CC26x0 and CC13x0 devices is complex and controlled by hardware. Figure 6-2
shows a simplified scheme with focus on parts that can be controlled by software. Registers that affect the
different voltage domains and power domains are highlighted in the figure. For example, register
PRCM:PDCTL0.SERIAL_ON controls the SERIAL power domain.
See Figure 6-3 for more details about voltage and power domains.
Figure 6-2. CC26x0 and CC13x0 Supply System
VDDS
LDO selected by
PRCM:VDCTL.ULDO.

Legend
Voltage regulators

Digital LDO

Global LDO
VDDR
DC-DC converter

Voltage domain

VDD

Power domain

Micro LDO

MCU_VD is controlled by AON_WUC:MCUCFG and
AON_EVENT:MCUWUSEL.

AON_VD

MCU_VD
MCU_AON is powered whenever MCU_VD is powered.

Modules in AON is always powered when CC26xx is
not in shutdown mode.

AON

AUX_PD is powered on by
AON_WUC:AUXCTL.AUX_FORCE_ON = 1.
For power off see AUX section.

AUX_PD

MCU_AON

BUS_PD is HW controlled to be powered whenever
CPU_PD is powered. May be powered when CPU_PD
is off on demand from RFCORE FW.

BUS_PD

VIMS_PD is HW controlled to be powered whenever
CPU_PD is powered. Also powered when BUS_PD is
powered in combination with
PRCM:PDCTL1.VIMS_MODE = 1.

JTAG_PD is SW-controlled by
AON_WUC:JTAGCFG:JTAG_PD_FORCE_ON.

JTAG_PD

VIMS_PD

CPU_PD is powered on by an enabled system CPU
interrupt.
CPU_PD is powered down on completion of setting
system CPU in deep sleep mode in combination with
PRCM:PDCTL1.CPU_ON = 0.

CPU_PD

RFCORE_PD

RFCORE_PD is SW-controlled by
PRCM:PDCTL0.RFC_ON and
PRCM:PDCTL1.RFC_ON.
Both of these bits must be cleared to power down
RFCORE_PD.

SERIAL_PD is SW-controlled by
PRCM:PDCTL0.SERIAL_ON.

SERIAL_PD

PERIPH_PD is SW-controlled by
PRCM:PDCTL0.PERIPH_ON.

PERIPH_PD

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

413

Supply System

www.ti.com

6.3.1 Internal DC-DC Converter and Global LDO
Normally, the VDDS supply pins of the CC26x0 and CC13x0 devices are powered from a 1.8-V to 3.8-V
supply (for example, batteries), and the VDDR supply pins are powered from the internal DC-DC
regulator.
Alternatively, the internal global LDO can be used instead of the DC-DC regulator, but this increases the
current consumption of the device. In this mode, disconnect DCDC_SW and connect VDDS_DCDC to the
VDDS supply. The Global LDO is connected internally to the VDDR pin, which must be connected
externally to the VDDR_RF pin. The Global LDO must be decoupled by a µF-sized capacitor on the VDDR
net.

6.3.2 External Regulator Mode
The CC26x0 and CC13x0 devices have an option to be supplied by an external regulator with a voltage
range of 1.65 V to 1.95 V. In this mode, the VDDS and VDDR pins are tied together. To enable external
regulator mode, the VDDS_DCDC pin and the DCDC_SW pins must be connected to ground, which
effectively disables both the internal Global LDO and the internal DC-DC regulator. For a detailed
description of connections and decoupling in the external regulator mode, refer to the CC2650EM-4XSEXT-REG Reference Design.

414

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Digital Power Partitioning

www.ti.com

6.4

Digital Power Partitioning
The CC26x0 and CC13x0 devices have two voltage domains, MCU_VD and AON_VD. Both voltage
domains contain multiple power domains, *_PD. Each power domain contains digital modules. Figure 6-3
shows details of the power partitioning of the CC26x0 and CC13x0 devices.
Figure 6-3. Digital Power Partitioning in CC26x0 and CC13x0
Legend

MCU_VD

Voltage domain
MCU_AON

CPU_PD

PERIPH_PD
Always-on logic

System CPU

PRCM
Wakeup interrupt controller

JTAG DAP

DMA controller
Power domain

CRYPTO core

Event fabric

True random number gen.

I/O controller

GPT [3:0]

Module with retention

Watchdog timer

GPIO

Module no retention

SSI1

Memory

BUS_PD

AON interface
Interconnect

I2S

System SRAM
RFCORE_PD

SERIAL_PD

Radio doorbell

UART

Radio timer

VIMS_PD

Cortex-M0 CPU
FLASH
RFCORE SRAM

SSI0
I2C

ROM
FLASH cache

ROM

OTP/EFUSE
Radio register banks

AON_VD

AON

I/O Controller

AUX_PD

Power

Sensor processor
Oscillator interface

Edge detect

SYS CTL

AON IO mux

MCU Wakeup

I/O controller

I/O state holder

AUX Wakeup

Analog interface
TDC

Event

Peripherals

Event fabric

RTC

Timers
SC SRAM

JTAG_PD

ICEPick JTAG router
IEEE1149.7 (cJTAG)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

415

Digital Power Partitioning

www.ti.com

6.4.1 MCU_VD
Figure 6-3 shows that the MCU voltage domain contains the CPU system divided into multiple power
domains. MCU_VD also includes always-on logic not encapsulated in a power domain, which is powered
whenever MCU_VD is powered. Figure 6-3 shows this logic as MCU_AON.
MCU_VD is powered up by any enabled wake-up source.
Requirements to power off MCU_VD are found in the register description of PRCM:VDCTL.MCU_VD (see
Section 6.8.2.4.4).
6.4.1.1

MCU_VD Power Domains

Figure 6-2 shows control of MCU_VD power domains and provides descriptions of the registers.

6.4.2 AON_VD
AON_VD contains two power domains and always-on logic marked AON in Figure 6-3.
Logic in AON is always powered when the CC26x0 and CC13x0 devices are not in shutdown mode.
6.4.2.1

AON_VD Power Domains

Figure 6-2 shows control of AON_VD power domains and provides descriptions of the registers.

6.5

Clock Management

6.5.1 System Clocks
Figure 6-4 and Table 6-4 show that the CC26x0 and CC13x0 devices have a flexible clock mux where
system clocks can be derived from several sources.
Figure 6-4. Clock Sources
/ 768
24 MHz

HF XTAL
oscillator
x2

32.768 kHz

LF XTAL
oscillator

32.25 kHz

SCLK_LF

24 MHz
48 MHz

SCLK_HF

32.768 kHz
Clock mux

SCLK_LF_AUX

48 MHz
HF RC
oscillator

External
32 kHz

416

24 MHz

LF RC
oscillator

32 kHz

AON
I/O controller

32 kHz

Power, Reset, and Clock Management

ACLK_ADC

ACLK_REF

ACLK_TDC

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Clock Management

www.ti.com

6.5.1.1

Controlling the Oscillators

Figure 6-3 shows that the oscillator interface is located in AUX_PD.
For the system CPU to access the oscillator interface, perform the following steps:
• Power on AUX_PD by setting AON_WUC:AUXCTL.AUX_FORCE_ON = 1
• Ensure AUX_PD is powered up by checking the bit AON_WUC:PWRSTAT.AUX_PD_ON
• Turn on the oscillator interface clock in AUX_WUC:MODCLKEN0: AUX_DDI0_OSC = 1
Table 6-4. System Clocks
Clock

Description

Possible Sources

SCLK_LF

Low-frequency clock
Always used for AON
Available for MCU_VD and AUX_PD in
Standby

31.25 kHz derived from 24-MHz XTAL oscillator
32-kHz RC oscillator
32.768-kHz XTAL oscillator
31.25 kHz derived from 48-MHz RC oscillator
Selectable in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL

SCLK_HF

High-frequency clock
Used by MCU_VD in active and idle
modes
Used by AUX_PD in active mode

48 MHz derived from 48-MHz RC oscillator
48 MHz derived from 24-MHz XTAL oscillator (doubled
internally)
Selectable in DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL

SCLK_LF_AUX

Used for low-power comparator in
AUX_PD (COMP_B)

Same as SCLK_LF

ACLK_ADC

Used as clock source for ADC

Same as SCLK_HF

ACLK_REF

Used as a start or stop source for Timeto-Digital Converter (TDC)

Same sources as for SCLK_LF
Selectable in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL

ACLK_TDC

Used as clock for TDC

48 MHz from RC oscillator
24 MHz from RC oscillator
24 MHz from XTAL oscillator
Selectable in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL

NOTE: When the 24-MHz crystal oscillator is enabled (by selecting XOSCHF as source for
SCLK_HF), the XOSCHF must not be turned off, or SCLK_HF source must not be changed
to another source, before the XOSCHF is reported as stable and switched to. The XOSCHF
is stable when the DDI_0_OSC:STAT0.PENDINGSCLKHFSWITCHING is asserted after
starting the crystal. DriverLib API should be used to switch SCLK_HF source, and interrupts
must be disabled while doing so.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

417

Clock Management

www.ti.com

Figure 6-5. System Clock Muxing
DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL

RCOSC 48 MHz

/ 1536

XTAL 24 MHz

/ 768

1
SCLK_LF

RCOSC 32 kHz

2
3

XTAL 32.768 kHz

External 32 kHz

SCLK_LF_AUX

DDI_0_OSC:CTL0.XOSC_LF_DIG_BYPASS
DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL

RCOSC 48 MHz

0
SCLK_HF

XTAL 24 MHz

ACLK_ADC

DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL

RCOSC 48 MHz

0
1

ACLK_TDC
XTAL 24 MHz

Unused

DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL

RCOSC 48 MHz

/ 1536

XTAL 48 MHz

/ 768

1
ACLK_REF

418

RCOSC 32 kHz

XTAL 32.768 kHz

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Clock Management

www.ti.com

6.5.2 Clocks in MCU_VD
AON_WUC supports MCU_VD with a clock that is divided and gated by PRCM before being distributed to
all modules in MCU_VD. Figure 6-6 shows the registers in PRCM that define division and gate control for
all module clocks. When no BUS transactions can occur, hardware automatically gates the SYSBUS
clock.
The following conditions must be true to gate the SYSBUS:
•
•
•
•

System CPU in deep sleep mode
PRCM:SECDMACLKGDS.DMA_CLK_EN = 0
PRCM:SECDMACLKGDS.SEC_CLK_EN = 0
RFCORE FW does not require bus access

The SYSBUS clock may run even when the system CPU is in deep sleep mode when either DMA, SEC,
or RFCORE needs an active interconnect.
MCU_AON has two clocks, an INFRASTRUCTURE clock that always runs and a PERBUSULL clock that
is identical to the INFRASTRUCTURE clock whenever the SYSBUS clock is running. When the SYSBUS
clock is gated, the PERBUSULL clock is automatically gated. INFRASTRUCTURE and PERBUSULL
clocks are automatically controlled to run at a maximum of half the clock frequency of SCLK_HF,
regardless of the settings in PRCM:INFCLKDIVR/S/DS.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

419

Clock Management

www.ti.com

Figure 6-6. Clocks in MCU_VD
MCU clock
SCLK_HF in active and Idle modes. Selected by
AON_WUC:MCUCLK.PWR_DWN_SRC in standby mode.

SCLK_HF
SCLK_LF
RFCORE_PD

Divider
Divide by 2

Clock gate
PRCM:RFCCLKG.CLK_EN

VIMS_PD

Clock gate
PRCM:VIMSCLKG.CLK_EN

CPU_PD

Conditional clock gate
Clock disabled when system CPU is in SLEEP or
DEEPSLEEP. Else clock is running.

Conditional clock gate

BUS_PD

SYSBUS clock always running except when all below is true:
- System CPU is in DEEPSLEEP
- PRCM:SECDMACLKGDS.DMA_CLK_EN = 0
- PRCM:SECDMACLKGDS.CRYPTO_CLK_EN = 0
- RFCORE FW do not require bus access

SYSBUS clock

PERIPH_PD

Conditional clock gate
Controlled by system CPU mode and
PRCM:SECDMACLKGR/S/DS.DMA_CLK_EN

DMA controller

Conditional clock gate
Controlled by system CPU mode and
PRCM:SECDMACLKGR/S/DS.CRYPTO_CLK_EN

CRYPTO core

Conditional clock gate
Controlled by system CPU mode and
PRCM:SECDMACLKGR/S/DS.TRNG_CLK_EN

True random number gen.

Conditional clock gate
Controlled by system CPU mode and
PRCM:GPTCLKGR/S/DS.CLK_EN

GPT [3:0]

Conditional clock gate
Controlled by system CPU mode and
PRCM:GPIOCLKGR/S/DS.CLK_EN

GPIO

Conditional clock gate
Controlled by system CPU mode and
PRCM:I2SCLKGR/S/DS.CLK_EN

I2S

Conditional clock gate
Controlled by system CPU mode and
PRCM:SSICLKGR/S/DS.CLK_EN

SSI1

SERIAL_PD

SSI0

Conditional clock gate

UART

Controlled by system CPU mode and
PRCM:UARTCLKGR/S/DS.CLK_EN

Conditional clock gate

I 2C

Controlled by system CPU mode and
PRCM:I2CCLKGR/S/DS.CLK_EN
SYSBUS clock gated

MCU_AON

Conditional divider
Controlled by system CPU mode and
PRCM:INFCLKDIVR/S/DS
If SCLK_HF sources MCU clock division ratio
is overridden to 2 if
PRCM:INFCLKDIVR/S/ DS = 1

AON interface
0
0

PERBUSULL clock

Event fabric

I/O controller
INFRASTRUCTURE clock

Wakeup interrupt controller
Watchdog timer

420

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Clock Management

www.ti.com

6.5.2.1

Clock Gating

As seen in Figure 6-6, the peripheral modules have conditional clock gates that depend on the system
CPU mode. The clock of a module may be enabled or disabled when the system CPU mode changes.
Example:
• PRCM:I2CCLKGR.CLK_EN = 1
• PRCM:I2CCLKGS.CLK_EN = 0
• PRCM:I2CCLKGDS.CLK_EN = 1
These settings result in the I2C clock running when the system CPU is in run mode and deep sleep mode,
while the I2C clock is disabled when system CPU is in sleep mode.
NOTE: When set in deep sleep mode, the system CPU remains in sleep mode for a few clock
cycles during the transition. An application that requires a continuous module clock enables
all clock-gate registers for the module during the transition while the system CPU changes
modes.

Because power cycling of a power domain overrides clock gate registers, disabling the module clocks
before powering down a power domain is not required.
6.5.2.2

Scalar to GPTs

A scalar to GPTs is available to enable GPTs to count at a slower frequency than SYSBUS clock. The
setting in the PRCM:GPTCLKDIV register is valid for all GPTs in the system.
6.5.2.3

Scalar to WDT

There is a scalar with a fixed-division ratio of 32 of the MCU clock that is present. Regardless of the
settings in the PRCM:INFCLKDIVR, the PRCM:INFCLKDIVS, and the PRCM:INFCLKDIVDS registers, the
watchdog counts at a constant speed, as long as the MCU clock is not changing between the SCLK_HF
and SCLK_LF as a clock source.

6.5.3 Clocks in AON_VD
All modules in AON_VD run on SCLK_LF except AUX_PD. Clocks to AUX_PD are user configurable.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

421

Power Modes

6.6

www.ti.com

Power Modes
The flexibility of the CC26x0 and CC13x0 power management allows many different configurations to
achieve a low-power application. This section describes the power modes, as defined by TI-RTOS, which
covers a range of power-saving modes from low-power savings with fast-cycling time to high-power
savings with long-cycling time.
Table 6-5 provides an overview of the power modes defined in TI-RTOS.
Table 6-5. Power Modes as Defined in TI-RTOS
Software Configurable Power Modes

Mode

Idle

Standby

Shutdown

System CPU

Active

Off

System SRAM

Retained

Off

(1)

Full

Partial

VIMS_PD (flash)

Available

Off

RFCORE_PD
(radio)

Available

Off

SERIAL_PD

Available

Off

PERIPH_PD

Available

Off

Sensor controller

Available

Off

Supply system

Duty-cycled

Off

Current

Application
dependent

Application dependent

Wakeup time to
CPU active (2)

–

High-speed clock

1 µA

0.1 µA

25 µs

300 µs (3)

1.5 ms

XOSC_HF or
RCOSC_HF

Off

Low-speed clock

XOSC_LF or
RCOSC_LF

Off

Wakeup on RTC

Available

Off

Wakeup on pin
edge

Available

Off

Wakeup on reset
pin

Available

Brown Out Detect
(BOD)

Active

Partial (4)

Off

N/A

Power On Reset
(POR)

Active

N/A

(1)
(2)
(3)

(4)

422

Reset Pin Held

Active

See Figure 6-3 for modules with retention.
Numbers include TI-RTOS overhead.
When an emulator/debugger is attached to the device, the wake up time is approximately 200 µs shorter as the system does not
enter true standby.
Brown Out Detector is disabled between recharge periods in Standby.

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power Modes

www.ti.com

6.6.1 Start-Up State
The CC26x0 and CC13x0 device state after a system reset, power on, or wake up from shutdown is as
follows:
• Global LDO is active
• Digital LDO is active
• AON_VD is powered
– AUX_PD is powered
– JTAG_PD is powered off
• MCU_VD is powered
– MCU_AON is powered
– CPU_PD is powered
• System CPU is in run mode
– BUS_PD is powered
• SYSBUS is clock running
– VIMS_PD is powered
• VIMS is clock running
– All other power domains are off
– All digital module clocks are disabled

6.6.2 Active Mode
Active mode is defined as any possible chip state where CPU_PD is powered, including BUS_PD and
VIMS_PD (see Figure 6-2).
In active mode, all modules are available and power consumption is highly application dependent.
Power saving features are:
• Enable the DC-DC converter
• Power only the necessary power domains
• Enable only the necessary module clocks
NOTE: Wake-up time for a power domain in the CC26x0 and CC13x0 devices requires
approximately 15 µs. Because clock gating in the CC26x0 and CC13x0 devices is efficient, it
may be more power efficient to disable all the clocks in a power domain and leave the
domain powered may be more power efficient than to power cycle it frequently.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

423

Power Modes

www.ti.com

6.6.3 Idle Mode
Idle mode is defined as any possible chip state where CPU_PD is powered off while any other module can
be powered. In idle mode, all modules are available and power consumption is highly application
dependent.
The CC26x0 and CC13x0 devices are put in idle mode with the following requirements:
• PRCM:PDCTL1.CPU_ON = 0
• CPU_SCS:SCR.SLEEPDEEP = 1
• WFI or WFE active
The CC26x0 and CC13x0 devices may wake up from any wakeup source.

6.6.4 Standby Mode
Standby mode is defined as all power domains in the MCU_VD voltage domain being powered off and the
micro LDO supplying AON_VD and MCU_VD (see Figure 6-2). Standby is the lowest power mode where
the CC26x0 and CC13x0 devices still have functionality other than maintaining I/O output pins (see
Table 6-6)
All parts in MCU_VD with retention, as shown in Figure 6-3, are retained in standby mode. All other logic
in MCU_VD must be reconfigured after wake up from Standby mode.
Sensor controller is available in autonomous mode when the CC26x0 and CC13x0 devices are in standby
mode.
Possible wake-up sources are events from I/O, JTAG, RTC, and the sensor processor.
The following are prerequisites for the CC26x0 and CC13x0 devices to enter standby mode:
• AUX_PD is powered down or powered off and disconnected from the system bus
• Request micro LDO to supply digital parts (see Figure 6-2)
• JTAG_PD is powered off
• The SCLK_HF clock is derived from the 48-MHz RC oscillator
• The SCLK_LF clock is derived from one of the following clock sources:
– 32-kHz RC oscillator
– 32.768-kHz crystal oscillator

424 Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Power Modes

www.ti.com

Table 6-6. Example Sequence for Setting CC26x0 and CC13x0 in Standby Mode
Description

Required Step

Allow for power down

AON_WUC:CTL0.PWR_DWN_DIS

No
(Default: Enabled)

Enable the DC-DC converter for
lower power

AON_SYSCTL:PWRCTL.DCDC_ACTIVE

No
(Default: Global LDO)

Set the HF clocks to correct source

DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL

Yes

Set the LF clocks to correct source

DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL

Yes

Configure recharge interval

AON_WUC:RECHARGECFG

Yes

Configure one or more wake-up
sources for MCU

AON_EVENT:MCUWUSEL

Yes

Configure power-down clock for MCU AON_WUC:MCUCLK.PWR_DWN_SRC

No
(Default: No clock)

Configure power-down clock for AUX

AON_WUC:AUXCLK.PWR_DWN_SRC

No
(Default: No clock)

Configure system SRAM retention

AON_WUC:MCUCFG.SRAM_RET_EN

No
(Default: Retention
enabled)

Turn off JTAG

AON_WUC:JTAGCFG:JTAG_PD_FORCE_ON

Yes

Configure the wake-up source to
generate an event

IOC:IOCFG / AON_RTC / AUX

Yes

Request AUX_PD power down

AUX_WUC:PWRDWNREQ.REQ

Yes

Disconnect AUX from system bus

AUX_WUC:MCUBUSCTL.DISCONNECT_REQ

Yes

Latch I/O state

AON_IOC:IOCLATCH.EN

Yes

Turn off power domains and verify
they are turned off

PRCM.PDCTL0
PRCM.PDCTL1
PRCM.PDSTAT0
PRCM.PDSTAT1

Yes

Request digital supply to be Micro
LDO

PRCM:VDCTL.ULDO

Yes

Synchronize transactions to AON
domain

AON_RTC.SYNC.WBUSY

Yes
(Read register)

Set the system CPU SLEEPDEEP bit CPU_SCS:SCR.SLEEPDEEP

Yes

Stop the system CPU to start the
power-down sequence

Yes

WFI or WFE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

425

Power Modes

www.ti.com

6.6.5 Shutdown Mode
Shutdown mode is defined as having no active power regulator in the CC26x0 and CC13x0 devices.
Before putting the CC26x0 and CC13x0 devices in shutdown mode, I/O pins are latched to keep their
output values in shutdown. This is the only difference between holding the CC26x0 and CC13x0 devices
in reset with the reset pin and shutdown mode.
Only an enabled pin interrupt or reset pin can wake up the CC26x0 and CC13x0 devices from shutdown
mode.
Table 6-7. Example Sequence for Going to Shut Down

6.7

Description

Required Step

Enable shutdown and latch I/Os

AON_WUC:SHUTDOWN.EN

Yes

Turn off JTAG

AON_WUC:JTAGCFG.JTAG_PD_FORCE_ON

Yes

Configure the wake-up pin

IOC:IOCFGxx.WU_CFG

Yes

Request AUX power down

AUX_WUC:PWRDWNREQ.REQ

Yes

Disconnect AUX from system bus

AUX_WUC:MCUBUSCTL.DISCONNECT_REQ

Yes

Request MCU_VD power off

PRCM:VDCTL.MCU_VD

Yes

Synchronize transactions to AON
domain

AON_RTC.SYNC

Yes (Read register)

Set the system CPU SLEEPDEEP
bit

CPU_SCS:SCR.SLEEPDEEP

Yes

Stop the system CPU to start the
power-down sequence

WFI or WFE

Yes

Reset
The CC26x0 and CC13x0 devices have several sources of reset; some are triggered due to errors or
unexpected behavior, while others are user initiated.
Resets may result in reset of the following:
• The entire chip
• A power domain
• A voltage domain
• One digital module for debug purposes

6.7.1 System Resets
A reset resulting in a complete power-up sequence and system CPU boot sequence is defined as a
system reset. The AON_SYSCTL:RESETCTL.RESET_SRC register is readable and always shows the
last source of a reset resulting in a system reset.
The following resets cannot be disabled and, when triggered, always result in a system reset:
• Power-on reset
• Pin reset
• VDDS failure
• VDDR failure
• VDD failure

426

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Reset

www.ti.com

6.7.1.1

Clock Loss Detection

When the clock loss feature is enabled with the DDI_0_OSC:CTL0.CLK_LOSS_EN and the
AON_SYSCTL:RESETCTL.CLK_LOSS_EN registers, a detected loss of SCLK_LF results in a system
reset. After recovery, the AON_SYSCTL:RESETCTL.RESET_SRC register shows clock loss as the
source of reset.
The SCLK_LF (32 kHz), SCLK_MF (internal 500-kHz clock derived from SCLK_HF) and SCLK_HF (48
MHz) are used against each other to detect a clock loss event by using counters. The counter keeps
counting consecutive nontransition events and when the count of the clock is equal to the time-out value,
clock loss event is generated. When there is a transition that shows the presence of the clock under
detection, the counter is cleared instead. Because SCLK_LF generates a long period when its source is
changed, the Clock Loss Detect (CLD) circuit will generate a clock loss event when SCLK_LF source is
switched. To avoid this, do not enable Clock Loss Detect before switching SCLK_LF source or disable
clock loss detect for SCLK_LF while switching. Completion of source change is done by observing status
bits in DDI_0_OSC:STAT0:SCLK_LF_SRC.
Timeout details:
• Loss of SCLK_LF is flagged when no transitions on SCLK_LF are detected for 511 consecutive
SCLK_MF periods (approximately 1 ms).
• Loss of SCLK_HF is flagged when no transitions on SCLK_LF are detected for 7 consecutive
SCLK_LF periods (approximately 200 µs).
NOTE: The application must set both DDI_0_OSC:CTL0.CLK_LOSS_EN and the
AON_SYSCTL:RESETCTL.CLK_LOSS_EN to enable Clock Loss Detection, it is not enabled
after boot.

6.7.1.2

Software-Initiated System Reset

Writing to the AON_SYSCTL:RESETCTL.SYSRESET register results in a system reset. After recovery,
the AON_SYSCTL:RESETCTL.RESET_SRC register shows SYSRESET as the source of reset.
6.7.1.3

Warm Reset Converted to System Reset

Warm reset can be programmed with the PRCM:WARMRESET.WR_TO_PINRESET register to result in a
system reset when any warm reset source is triggered (see Section 6.7.2).
NOTE: TI strongly recommends enabling the Warm Reset Converted to System Reset feature.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

427

Reset

www.ti.com

6.7.2 Warm Reset
A reset that results in a reset of the MCU_VD and the system CPU bus part of AUX_PD, is defined as a
warm reset. A warm reset leaves all analog configurations unchanged, while the system CPU and all other
digital modules in MCU_VD are reset.
The following sources initiate a warm reset generation:
• The CPU_SCS:AIRCR.SYSRESETREQ register
• System CPU LOCKUP
• Watchdog time-out
When a warm reset source is triggered, MCU_VD is reset through a controlled sequence, returning
MCU_VD to the same state as when finishing a boot from system reset.
The PRCM:WARMRESET register has readable bits that indicate if the MCU_VD was reset due to a
system CPU LOCKUP event or a watchdog time-out.
NOTE: Because warm reset does not reset the analog parts of the device, such as the radio, doing
a warm reset will put the device in a partly unknown state. It is therefore strongly
recommended to enable Warm Reset Converted to System Reset feature as described in
the section above.
Triggering a warm reset run-time can lead to problems such as unexpected behaviour or
program freeze. The only situation where it is ok to not enable Warm Reset Converted to
System Reset is during development and debugging if a SW problem is triggering a warm
reset. In that situation, not enabling the warm to cold reset feature is typically required to
identify the reset source.

6.7.3 Software-Initiated Reset of MCU_VD
A feature to request a reset of MCU_VD is available. When writing the PRCM:SWRESET.MCU register,
AON_WUC does a controlled reset sequence of MCU_VD. This reset also clears the PRCM and other
logic in MCU_AON.

6.7.4 Reset of the MCU_VD Power Domains and Modules
Reset of logic in power domains are hardware controlled. A module without retention is reset when the
encapsulating power domain is power cycled. A module with retention resets when MCU_VD is power
cycled or reset.

6.7.5 Reset of AON_VD
AON_VD is reset by a system reset. For details, see Section 6.7.1.

6.7.6 Reset of AUX_PD
Reset of AUX_PD can be done by writing to the AON_WUC:AUXCTL.RESET_REQ register.

428

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8

PRCM Registers

6.8.1 CC13x0 DDI_0_OSC Registers
6.8.1.1

DDI_0_OSC Registers

Table 6-25 lists the memory-mapped registers for the DDI_0_OSC. All register offset addresses not listed
in Table 6-25 should be considered as reserved locations and the register contents should not be
modified.
Table 6-8. DDI_0_OSC Registers
Offset

Acronym

CTL0

Control 0

Section 6.8.2.1.1

CTL1

Control 1

Section 6.8.2.1.2

RADCEXTCFG

RADC External Configuration

Section 6.8.2.1.3

AMPCOMPCTL

Amplitude Compensation Control

Section 6.8.2.1.4

10h

AMPCOMPTH1

Amplitude Compensation Threshold 1

Section 6.8.2.1.5

14h

AMPCOMPTH2

Amplitude Compensation Threshold 2

Section 6.8.2.1.6

18h

ANABYPASSVAL1

Analog Bypass Values 1

Section 6.8.2.1.7

1Ch

ANABYPASSVAL2

Internal

Section 6.8.2.1.8

20h

ATESTCTL

Analog Test Control

Section 6.8.2.1.9

24h

ADCDOUBLERNANOAMPCTL

ADC Doubler Nanoamp Control

Section 6.8.2.1.10

28h

XOSCHFCTL

XOSCHF Control

Section 6.8.2.1.11

2Ch

LFOSCCTL

Low Frequency Oscillator Control

Section 6.8.2.1.12

30h

RCOSCHFCTL

RCOSCHF Control

Section 6.8.2.1.13

34h

STAT0

Status 0

Section 6.8.2.1.14

38h

STAT1

Status 1

Section 6.8.2.1.15

3Ch

STAT2

Status 2

Section 6.8.2.1.16

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Section

Power, Reset, and Clock Management

429

PRCM Registers

www.ti.com

6.8.1.1.1 CTL0 Register (Offset = 0h) [reset = 0h]
CTL0 is shown in Figure 6-23 and described in Table 6-26.
Return to Summary Table.
Control 0
Controls clock source selects
Figure 6-7. CTL0 Register
31
XTAL_IS_24M

30
RESERVED

R/W-0h

23
RESERVED

22
FORCE_KICKS
TART_EN

R/W-0h

15
RESERVED

14
HPOSC_MODE
_EN
R/W-0h

R/W-0h
7
ACLK_TDC_S
RC_SEL
R/W-0h

29
28
BYPASS_XOS BYPASS_RCO
C_LF_CLK_QU SC_LF_CLK_Q
AL
UAL
R/W-0h
R/W-0h
21

27
26
DOUBLER_START_DURATION

R/W-0h
19
RESERVED

25
DOUBLER_RE
SET_DURATIO
N
R/W-0h

24
RESERVED

16
ALLOW_SCLK
_HF_SWITCHI
NG
R/W-0h

R/W-0h
13
RESERVED
R/W-0h

12
RCOSC_LF_T
RIMMED
R/W-0h

11
XOSC_HF_PO
WER_MODE
R/W-0h

10
9
XOSC_LF_DIG CLK_LOSS_EN
_BYPASS
R/W-0h
R/W-0h

6
5
ACLK_REF_SRC_SEL

4
SPARE4

3
2
SCLK_LF_SRC_SEL

R/W-0h

1
SCLK_MF_SR
C_SEL
R/W-0h

R/W-0h

8
ACLK_TDC_S
RC_SEL
R/W-0h
0
SCLK_HF_SR
C_SEL
R/W-0h

Table 6-9. CTL0 Register Field Descriptions
Bit

Field

Type

Reset

Description

XTAL_IS_24M

R/W

Set based on the accurate high frequency XTAL.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BYPASS_XOSC_LF_CLK R/W
_QUAL

Internal. Only to be used through TI provided API.

BYPASS_RCOSC_LF_CL R/W
K_QUAL

Internal. Only to be used through TI provided API.

27-26

DOUBLER_START_DUR
ATION

R/W

Internal. Only to be used through TI provided API.

DOUBLER_RESET_DUR
ATION

R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

FORCE_KICKSTART_EN R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ALLOW_SCLK_HF_SWIT R/W
CHING

0: Default - Switching of HF clock source is disabled .
1: Allows switching of sclk_hf source.
Provided to prevent switching of the SCLK_HF source when running
from flash (a long period during switching could corrupt flash). When
sclk_hf switching is disabled, a new source can be started when
SCLK_HF_SRC_SEL is changed, but the switch will not occur until
this bit is set. This bit should be set to enable clock switching after
STAT0.PENDINGSCLKHFSWITCHING indicates the new HF clock
is ready. When switching completes (also indicated by
STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching should be
disabled to prevent flash corruption. Switching should not be enabled
when running from flash.

24-23
22
21-17
16

430

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

Table 6-9. CTL0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HPOSC_MODE_EN

R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RCOSC_LF_TRIMMED

R/W

Internal. Only to be used through TI provided API.

XOSC_HF_POWER_MO
DE

R/W

Internal. Only to be used through TI provided API.

XOSC_LF_DIG_BYPASS

R/W

Bypass XOSC_LF and use the digital input clock from AON for the
xosc_lf clock.
0: Use 32kHz XOSC as xosc_lf clock source
1: Use digital input (from AON) as xosc_lf clock source.
This bit will only have effect when SCLK_LF_SRC_SEL is selecting
the xosc_lf as the sclk_lf source. The muxing performed by this bit is
not glitch free. The following procedure must be followed when
changing this field to avoid glitches on sclk_lf.
1) Set SCLK_LF_SRC_SEL to select any source other than the
xosc_lf clock source.
2) Set or clear this bit to bypass or not bypass the xosc_lf.
3) Set SCLK_LF_SRC_SEL to use xosc_lf.
It is recommended that either the rcosc_hf or xosc_hf (whichever is
currently active) be selected as the source in step 1 above. This
provides a faster clock change.

CLK_LOSS_EN

R/W

Enable clock loss detection and hence the indicators to system
controller. Checks both SCLK_HF and SCLK_LF clock loss
indicators.
0: Disable
1: Enable
Clock loss detection must be disabled when changing the sclk_lf
source. STAT0.SCLK_LF_SRC can be polled to determine when a
change to a new sclk_lf source has completed.

8-7

ACLK_TDC_SRC_SEL

R/W

Source select for aclk_tdc.
00: RCOSC_HF (48MHz)
01: RCOSC_HF (24MHz)
10: XOSC_HF (24MHz)
11: Not used

6-5

ACLK_REF_SRC_SEL

R/W

Source select for aclk_ref
00: RCOSC_HF derived (31.25kHz)
01: XOSC_HF derived (31.25kHz)
10: RCOSC_LF (32kHz)
11: XOSC_LF (32.768kHz)

SPARE4

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-2

SCLK_LF_SRC_SEL

R/W

Source select for sclk_lf
0h = Low frequency clock derived from High Frequency RCOSC
1h = Low frequency clock derived from High Frequency XOSC
2h = Low frequency RCOSC
3h = Low frequency XOSC

SCLK_MF_SRC_SEL

R/W

Internal. Only to be used through TI provided API.

SCLK_HF_SRC_SEL

R/W

Source select for sclk_hf. XOSC option is supported for test and
debug only and should be used when the XOSC_HF is running.
0h = High frequency RCOSC clock
1h = High frequency XOSC clk

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

431

PRCM Registers

www.ti.com

6.8.1.1.2 CTL1 Register (Offset = 4h) [reset = 0h]
CTL1 is shown in Figure 6-24 and described in Table 6-27.
Return to Summary Table.
Control 1
This register contains OSC_DIG configuration
Figure 6-8. CTL1 Register
31

17
RCOSCHFCTR
IMFRACT_EN
R/W-0h

16
SPARE2

RESERVED
R/W-0h
23
RESERVED

20
RCOSCHFCTRIMFRACT

R/W-0h

SPARE2
R/W-0h
7

4
SPARE2
R/W-0h

1
0
XOSC_HF_FAST_START
R/W-0h

Table 6-10. CTL1 Register Field Descriptions
Bit

432

Field

Type

Reset

Description

31-23

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

22-18

RCOSCHFCTRIMFRACT

R/W

Internal. Only to be used through TI provided API.

RCOSCHFCTRIMFRACT
_EN

R/W

Internal. Only to be used through TI provided API.

16-2

SPARE2

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

XOSC_HF_FAST_START R/W

Internal. Only to be used through TI provided API.

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.1.1.3 RADCEXTCFG Register (Offset = 8h) [reset = 0h]
RADCEXTCFG is shown in Figure 6-25 and described in Table 6-28.
Return to Summary Table.
RADC External Configuration
Figure 6-9. RADCEXTCFG Register
31

23
22
HPM_IBIAS_WAIT_CNT
R/W-0h
15

28
27
HPM_IBIAS_WAIT_CNT
R/W-0h

5
RADC_MODE_
IS_SAR
R/W-0h

R/W-0h

10
9
RADC_DAC_TH
R/W-0h

19
18
LPM_IBIAS_WAIT_CNT
R/W-0h

IDAC_STEP
R/W-0h
7
6
RADC_DAC_TH

2
RESERVED

R/W-0h

Table 6-11. RADCEXTCFG Register Field Descriptions
Field

Type

Reset

Description

31-22

Bit

HPM_IBIAS_WAIT_CNT

R/W

Internal. Only to be used through TI provided API.

21-16

LPM_IBIAS_WAIT_CNT

R/W

Internal. Only to be used through TI provided API.

15-12

IDAC_STEP

R/W

Internal. Only to be used through TI provided API.

11-6

RADC_DAC_TH

R/W

Internal. Only to be used through TI provided API.

RADC_MODE_IS_SAR

R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

5
4-0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

433

PRCM Registers

www.ti.com

6.8.1.1.4 AMPCOMPCTL Register (Offset = Ch) [reset = 0h]
AMPCOMPCTL is shown in Figure 6-26 and described in Table 6-29.
Return to Summary Table.
Amplitude Compensation Control
Figure 6-10. AMPCOMPCTL Register
31
SPARE31
R/W-0h

30
AMPCOMP_RE
Q_MODE
R/W-0h

29
28
AMPCOMP_FSM_UPDATE_RA
TE
R/W-0h

22
21
IBIAS_OFFSET
R/W-0h

27
AMPCOMP_S
W_CTRL
R/W-0h

26
AMPCOMP_S
W_EN
R/W-0h

RESERVED
R/W-0h

IBIAS_INIT
R/W-0h

12
11
LPM_IBIAS_WAIT_CNT_FINAL
R/W-0h

CAP_STEP
R/W-0h

2
1
IBIASCAP_HPTOLP_OL_CNT
R/W-0h

Table 6-12. AMPCOMPCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

SPARE31

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AMPCOMP_REQ_MODE

R/W

Internal. Only to be used through TI provided API.

AMPCOMP_FSM_UPDAT R/W
E_RATE

Internal. Only to be used through TI provided API.

AMPCOMP_SW_CTRL

R/W

Internal. Only to be used through TI provided API.

AMPCOMP_SW_EN

R/W

Internal. Only to be used through TI provided API.

25-24

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-20

IBIAS_OFFSET

R/W

Internal. Only to be used through TI provided API.

19-16

IBIAS_INIT

R/W

Internal. Only to be used through TI provided API.

15-8

LPM_IBIAS_WAIT_CNT_
FINAL

R/W

Internal. Only to be used through TI provided API.

7-4

CAP_STEP

R/W

Internal. Only to be used through TI provided API.

3-0

IBIASCAP_HPTOLP_OL_ R/W
CNT

Internal. Only to be used through TI provided API.

29-28

434

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.1.1.5 AMPCOMPTH1 Register (Offset = 10h) [reset = 0h]
AMPCOMPTH1 is shown in Figure 6-27 and described in Table 6-30.
Return to Summary Table.
Amplitude Compensation Threshold 1
This register contains threshold values for amplitude compensation algorithm
Figure 6-11. AMPCOMPTH1 Register
31

21
20
HPMRAMP3_LTH
R/W-0h

13
12
HPMRAMP3_HTH
R/W-0h

3
2
HPMRAMP1_TH
R/W-0h

SPARE24
R/W-0h
23

7
6
IBIASCAP_LPTOHP_OL_CNT
R/W-0h

16
SPARE16
R/W-0h

9
8
IBIASCAP_LPTOHP_OL_CNT
R/W-0h
1

Table 6-13. AMPCOMPTH1 Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

SPARE24

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-18

HPMRAMP3_LTH

R/W

Internal. Only to be used through TI provided API.

17-16

SPARE16

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-10

HPMRAMP3_HTH

R/W

Internal. Only to be used through TI provided API.

9-6

IBIASCAP_LPTOHP_OL_ R/W
CNT

Internal. Only to be used through TI provided API.

5-0

HPMRAMP1_TH

Internal. Only to be used through TI provided API.

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

435

PRCM Registers

www.ti.com

6.8.1.1.6 AMPCOMPTH2 Register (Offset = 14h) [reset = 0h]
AMPCOMPTH2 is shown in Figure 6-28 and described in Table 6-31.
Return to Summary Table.
Amplitude Compensation Threshold 2
This register contains threshold values for amplitude compensation algorithm.
Figure 6-12. AMPCOMPTH2 Register
31

29
28
LPMUPDATE_LTH
R/W-0h

21
20
LPMUPDATE_HTH
R/W-0h

13
12
ADC_COMP_AMPTH_LPM
R/W-0h

5
4
ADC_COMP_AMPTH_HPM
R/W-0h

24
SPARE24
R/W-0h

16
SPARE16
R/W-0h

8
SPARE8
R/W-0h

0
SPARE0
R/W-0h

Table 6-14. AMPCOMPTH2 Register Field Descriptions
Bit

436

Field

Type

Reset

Description

31-26

LPMUPDATE_LTH

R/W

Internal. Only to be used through TI provided API.

25-24

SPARE24

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-18

LPMUPDATE_HTH

R/W

Internal. Only to be used through TI provided API.

17-16

SPARE16

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-10

ADC_COMP_AMPTH_LP
M

R/W

Internal. Only to be used through TI provided API.

9-8

SPARE8

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-2

ADC_COMP_AMPTH_HP R/W
M

Internal. Only to be used through TI provided API.

1-0

SPARE0

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.1.1.7 ANABYPASSVAL1 Register (Offset = 18h) [reset = 0h]
ANABYPASSVAL1 is shown in Figure 6-29 and described in Table 6-32.
Return to Summary Table.
Analog Bypass Values 1
Figure 6-13. ANABYPASSVAL1 Register
31

RESERVED
R/W-0h
23

RESERVED
R/W-0h

18
17
XOSC_HF_ROW_Q12
R/W-0h

12
11
XOSC_HF_COLUMN_Q12
R/W-0h

4
3
XOSC_HF_COLUMN_Q12
R/W-0h

Table 6-15. ANABYPASSVAL1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-20

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

19-16

XOSC_HF_ROW_Q12

R/W

Internal. Only to be used through TI provided API.

15-0

XOSC_HF_COLUMN_Q1
2

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

437

PRCM Registers

www.ti.com

6.8.1.1.8 ANABYPASSVAL2 Register (Offset = 1Ch) [reset = 0h]
ANABYPASSVAL2 is shown in Figure 6-30 and described in Table 6-33.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 6-14. ANABYPASSVAL2 Register
31

15
14
RESERVED
R/W-0h

24
23
RESERVED
R/W-0h

8
7
6
5
XOSC_HF_IBIASTHERM
R/W-0h

Table 6-16. ANABYPASSVAL2 Register Field Descriptions
Bit

438

Field

Type

Reset

Description

31-14

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

13-0

XOSC_HF_IBIASTHERM

R/W

Internal. Only to be used through TI provided API.

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.1.1.9 ATESTCTL Register (Offset = 20h) [reset = 0h]
ATESTCTL is shown in Figure 6-31 and described in Table 6-34.
Return to Summary Table.
Analog Test Control
Figure 6-15. ATESTCTL Register
31

30
SPARE30
R/W-0h

29
SCLK_LF_AUX
_EN
R/W-0h

26
RESERVED

R/W-0h
19

RESERVED
R/W-0h
15

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 6-17. ATESTCTL Register Field Descriptions
Bit
31-30
29
28-0

Field

Type

Reset

Description

SPARE30

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SCLK_LF_AUX_EN

R/W

Enable 32 kHz clock to AUX_COMPB.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

439

PRCM Registers

www.ti.com

6.8.1.1.10 ADCDOUBLERNANOAMPCTL Register (Offset = 24h) [reset = 0h]
ADCDOUBLERNANOAMPCTL is shown in Figure 6-32 and described in Table 6-35.
Return to Summary Table.
ADC Doubler Nanoamp Control
Figure 6-16. ADCDOUBLERNANOAMPCTL Register
31

28
RESERVED

24
NANOAMP_BI
AS_ENABLE
R/W-0h

19
RESERVED
R/W-0h

2
RESERVED

1
0
ADC_IREF_CTRL

R/W-0h

R/W-0h
23
SPARE23
R/W-0h

12
RESERVED
R/W-0h

5
ADC_SH_MOD
E_EN
R/W-0h

RESERVED
R/W-0h

4
ADC_SH_VBU
F_EN
R/W-0h

Table 6-18. ADCDOUBLERNANOAMPCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

NANOAMP_BIAS_ENABL R/W
E

Internal. Only to be used through TI provided API.

SPARE23

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ADC_SH_MODE_EN

R/W

Internal. Only to be used through TI provided API.

ADC_SH_VBUF_EN

R/W

Internal. Only to be used through TI provided API.

3-2

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

ADC_IREF_CTRL

R/W

Internal. Only to be used through TI provided API.

31-25

22-6

440

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.1.1.11 XOSCHFCTL Register (Offset = 28h) [reset = 0h]
XOSCHFCTL is shown in Figure 6-33 and described in Table 6-36.
Return to Summary Table.
XOSCHF Control
Figure 6-17. XOSCHFCTL Register
31

9
8
PEAK_DET_ITRIM
R/W-0h

3
HP_BUF_ITRIM
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

13
RESERVED
R/W-0h

7
RESERVED
R/W-0h

6
BYPASS
R/W-0h

5
RESERVED
R/W-0h

0
LP_BUF_ITRIM
R/W-0h

Table 6-19. XOSCHFCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

PEAK_DET_ITRIM

R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BYPASS

R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

4-2

HP_BUF_ITRIM

R/W

Internal. Only to be used through TI provided API.

1-0

LP_BUF_ITRIM

R/W

Internal. Only to be used through TI provided API.

31-10
9-8

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

441

PRCM Registers

www.ti.com

6.8.1.1.12 LFOSCCTL Register (Offset = 2Ch) [reset = 0h]
LFOSCCTL is shown in Figure 6-34 and described in Table 6-37.
Return to Summary Table.
Low Frequency Oscillator Control
Figure 6-18. LFOSCCTL Register
31

RESERVED
R/W-0h
23
22
XOSCLF_REGULATOR_TRIM
R/W-0h
15

20
19
XOSCLF_CMIRRWR_RATIO
R/W-0h

RESERVED
R/W-0h
7

16
RESERVED
R/W-0h

4
3
RCOSCLF_CTUNE_TRIM
R/W-0h

9
8
RCOSCLF_RTUNE_TRIM
R/W-0h
1

Table 6-20. LFOSCCTL Register Field Descriptions
Bit

442

Field

Type

Reset

Description

31-24

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-22

XOSCLF_REGULATOR_
TRIM

R/W

Internal. Only to be used through TI provided API.

21-18

XOSCLF_CMIRRWR_RA
TIO

R/W

Internal. Only to be used through TI provided API.

17-10

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

9-8

RCOSCLF_RTUNE_TRIM R/W

Internal. Only to be used through TI provided API.

7-0

RCOSCLF_CTUNE_TRIM R/W

Internal. Only to be used through TI provided API.

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.1.1.13 RCOSCHFCTL Register (Offset = 30h) [reset = 0h]
RCOSCHFCTL is shown in Figure 6-35 and described in Table 6-38.
Return to Summary Table.
RCOSCHF Control
Figure 6-19. RCOSCHFCTL Register
31

12
11
RCOSCHF_CTRIM
R/W-0h

24
23
RESERVED
R/W-0h
8

4
3
RESERVED
R/W-0h

Table 6-21. RCOSCHFCTL Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-8

RCOSCHF_CTRIM

R/W

Internal. Only to be used through TI provided API.

7-0

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

443

PRCM Registers

www.ti.com

6.8.1.1.14 STAT0 Register (Offset = 34h) [reset = 0h]
STAT0 is shown in Figure 6-36 and described in Table 6-39.
Return to Summary Table.
Status 0
This register contains status signals from OSC_DIG
Figure 6-20. STAT0 Register
31
SPARE31

30
29
SCLK_LF_SRC

R-0h

23
RESERVED

28
SCLK_HF_SR
C
R-0h

19
CLK_DCDC_R
DY
R-0h

18
CLK_DCDC_R
DY_ACK
R-0h

11
XOSC_HF_LP_
BUF_EN
R-0h

10
XOSC_HF_HP
_BUF_EN
R-0h

9
RESERVED

8
ADC_THMET

R-0h

0
PENDINGSCL
KHFSWITCHIN
G
R-0h

21
RCOSC_LF_E
N
R-0h

20
XOSC_LF_EN

R-0h

22
RCOSC_HF_E
N
R-0h

15
XOSC_HF_EN

14
RESERVED

12
RESERVED

R-0h

13
XB_48M_CLK_
EN
R-0h

7
ADC_DATA_R
EADY

R-0h

R-0h
17
16
SCLK_HF_LOS SCLK_LF_LOS
S
S
R-0h
R-0h

ADC_DATA

R-0h

RESERVED

R-0h

Table 6-22. STAT0 Register Field Descriptions
Bit

Field

Type

Reset

Description

SPARE31

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

30-29

SCLK_LF_SRC

Indicates source for the sclk_lf
0h = Low frequency clock derived from High Frequency RCOSC
1h = Low frequency clock derived from High Frequency XOSC
2h = Low frequency RCOSC
3h = Low frequency XOSC

SCLK_HF_SRC

Indicates source for the sclk_hf
0h = High frequency RCOSC clock
1h = High frequency XOSC

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RCOSC_HF_EN

RCOSC_LF_EN

XOSC_LF_EN

CLK_DCDC_RDY

CLK_DCDC_RDY_ACK

SCLK_HF_LOSS

Indicates sclk_hf is lost

SCLK_LF_LOSS

Indicates sclk_lf is lost

XOSC_HF_EN

Indicates that XOSC_HF is enabled.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

27-23

444

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

Table 6-22. STAT0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

XB_48M_CLK_EN

Indicates that the 48MHz clock from the DOUBLER is enabled.
It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler
bypass for the 48MHz crystal).

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

XOSC_HF_LP_BUF_EN

XOSC_HF_HP_BUF_EN

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ADC_THMET

ADC_DATA_READY

indicates when adc_data is ready.

ADC_DATA

adc_data

PENDINGSCLKHFSWITC R
HING

Indicates when sclk_hf is ready to be switched

6-1
0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

445

PRCM Registers

www.ti.com

6.8.1.1.15 STAT1 Register (Offset = 38h) [reset = 0h]
STAT1 is shown in Figure 6-37 and described in Table 6-40.
Return to Summary Table.
Status 1
This register contains status signals from OSC_DIG
Figure 6-21. STAT1 Register
31

19
18
LPM_UPDATE_AMP
R-0h
11
ACLK_TDC_E
N
R-0h
3
ACLK_TDC_G
OOD
R-0h

RAMPSTATE
R-0h
23
22
HPM_UPDATE_AMP
R-0h
15
FORCE_RCOS
C_HF
R-0h

14
SCLK_HF_EN

13
SCLK_MF_EN

R-0h

12
ACLK_ADC_E
N
R-0h

7
SCLK_HF_GO
OD
R-0h

6
SCLK_MF_GO
OD
R-0h

5
SCLK_LF_GO
OD
R-0h

4
ACLK_ADC_G
OOD
R-0h

26
25
HPM_UPDATE_AMP
R-0h

10
ACLK_REF_EN

9
CLK_CHP_EN

R-0h

8
CLK_DCDC_E
N
R-0h

2
ACLK_REF_G
OOD
R-0h

1
CLK_CHP_GO
OD
R-0h

0
CLK_DCDC_G
OOD
R-0h

Table 6-23. STAT1 Register Field Descriptions
Bit

446

Field

Type

Reset

Description

31-28

RAMPSTATE

AMPCOMP FSM State
0h = RESET
1h = INITIALIZATION
2h = HPM_RAMP1
3h = HPM_RAMP2
4h = HPM_RAMP3
5h = HPM_UPDATE
6h = IDAC_INCREMENT
7h = IBIAS_CAP_UPDATE
8h = IBIAS_DECREMENT_WITH_MEASURE
9h = LPM_UPDATE
Ah = IBIAS_INCREMENT
Bh = IDAC_DECREMENT_WITH_MEASURE
Ch = DUMMY_TO_INIT_1
Dh = FAST_START
Eh = FAST_START_SETTLE

27-22

HPM_UPDATE_AMP

OSC amplitude during HPM_UPDATE state.
When amplitude compensation of XOSC_HF is enabled in high
performance mode, this value is the amplitude of the crystal
oscillations measured by the on-chip oscillator ADC, divided by 15
mV. For example, a value of 0x20 would indicate that the amplitude
of the crystal is approximately 480 mV. To enable amplitude
compensation, AON_WUC OSCCFG must be set to a non-zero
value.

21-16

LPM_UPDATE_AMP

OSC amplitude during LPM_UPDATE state
When amplitude compensation of XOSC_HF is enabled in low power
mode, this value is the amplitude of the crystal oscillations measured
by the on-chip oscillator ADC, divided by 15 mV. For example, a
value of 0x20 would indicate that the amplitude of the crystal is
approximately 480 mV. To enable amplitude compensation,
AON_WUC OSCCFG must be set to a non-zero value.

FORCE_RCOSC_HF

force_rcosc_hf

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

Table 6-23. STAT1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

SCLK_HF_EN

SCLK_MF_EN

ACLK_ADC_EN

ACLK_TDC_EN

ACLK_REF_EN

CLK_CHP_EN

CLK_DCDC_EN

SCLK_HF_GOOD

SCLK_MF_GOOD

SCLK_LF_GOOD

ACLK_ADC_GOOD

ACLK_TDC_GOOD

ACLK_REF_GOOD

CLK_CHP_GOOD

CLK_DCDC_GOOD

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

447

PRCM Registers

www.ti.com

6.8.1.1.16 STAT2 Register (Offset = 3Ch) [reset = 0h]
STAT2 is shown in Figure 6-38 and described in Table 6-41.
Return to Summary Table.
Status 2
This register contains status signals from AMPCOMP FSM
Figure 6-22. STAT2 Register
31

25
HPM_RAMP1_
THMET
R-0h

24
HPM_RAMP2_
THMET
R-0h

19
RESERVED

1
XOSC_HF_FR
EQGOOD
R-0h

0
XOSC_HF_RF
_FREQGOOD
R-0h

ADC_DCBIAS
R-0h
23
HPM_RAMP3_
THMET
R-0h

R-0h
13

RAMPSTATE
R-0h
7

RESERVED
R-0h
5

RESERVED
R-0h

3
2
AMPCOMP_RE XOSC_HF_AM
Q
PGOOD
R-0h
R-0h

Table 6-24. STAT2 Register Field Descriptions
Bit

Field

Type

Reset

Description

ADC_DCBIAS

DC Bias read by RADC during SAR mode
The value is an unsigned integer. It is used for debug only.

HPM_RAMP1_THMET

Indication of threshold is met for hpm_ramp1

HPM_RAMP2_THMET

Indication of threshold is met for hpm_ramp2

HPM_RAMP3_THMET

Indication of threshold is met for hpm_ramp3

22-16

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-12

RAMPSTATE

xosc_hf amplitude compensation FSM
This is identical to STAT1.RAMPSTATE. See that description for
encoding.

11-4

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AMPCOMP_REQ

ampcomp_req

XOSC_HF_AMPGOOD

amplitude of xosc_hf is within the required threshold (set by DDI).
Not used for anything just for debug/status

XOSC_HF_FREQGOOD

frequency of xosc_hf is good to use for the digital clocks

XOSC_HF_RF_FREQGO
OD

frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for
radio operations. Used for SW to start synthesizer.

31-26

448

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2 CC26x0 PRCM Registers
6.8.2.1

DDI_0_OSC Registers

Acronym

Section

CTL0

Control 0

Section 6.8.2.1.1

CTL1

Control 1

Section 6.8.2.1.2

RADCEXTCFG

RADC External Configuration

Section 6.8.2.1.3

AMPCOMPCTL

Amplitude Compensation Control

Section 6.8.2.1.4

10h

AMPCOMPTH1

Amplitude Compensation Threshold 1

Section 6.8.2.1.5

14h

AMPCOMPTH2

Amplitude Compensation Threshold 2

Section 6.8.2.1.6

18h

ANABYPASSVAL1

Analog Bypass Values 1

Section 6.8.2.1.7

1Ch

ANABYPASSVAL2

Internal

Section 6.8.2.1.8

20h

ATESTCTL

Analog Test Control

Section 6.8.2.1.9

24h

ADCDOUBLERNANOAMPCTL

ADC Doubler Nanoamp Control

Section 6.8.2.1.10

28h

XOSCHFCTL

XOSCHF Control

Section 6.8.2.1.11

2Ch

LFOSCCTL

Low Frequency Oscillator Control

Section 6.8.2.1.12

30h

RCOSCHFCTL

RCOSCHF Control

Section 6.8.2.1.13

34h

STAT0

Status 0

Section 6.8.2.1.14

38h

STAT1

Status 1

Section 6.8.2.1.15

3Ch

STAT2

Status 2

Section 6.8.2.1.16

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

449

PRCM Registers

www.ti.com

6.8.2.1.1 CTL0 Register (Offset = 0h) [reset = 0h]
CTL0 is shown in Figure 6-23 and described in Table 6-26.
Return to Summary Table.
Control 0
Controls clock source selects
Figure 6-23. CTL0 Register
31
XTAL_IS_24M

30
RESERVED

R/W-0h

23
RESERVED

22
FORCE_KICKS
TART_EN

R/W-0h

15
RESERVED

14
HPOSC_MODE
_EN
R/W-0h

R/W-0h
7
ACLK_TDC_S
RC_SEL
R/W-0h

29
28
BYPASS_XOS BYPASS_RCO
C_LF_CLK_QU SC_LF_CLK_Q
AL
UAL
R/W-0h
R/W-0h
21

27
26
DOUBLER_START_DURATION

R/W-0h
19
RESERVED

25
DOUBLER_RE
SET_DURATIO
N
R/W-0h

24
RESERVED

16
ALLOW_SCLK
_HF_SWITCHI
NG
R/W-0h

R/W-0h
13
RESERVED
R/W-0h

12
RCOSC_LF_T
RIMMED
R/W-0h

11
XOSC_HF_PO
WER_MODE
R/W-0h

10
9
XOSC_LF_DIG CLK_LOSS_EN
_BYPASS
R/W-0h
R/W-0h

6
5
ACLK_REF_SRC_SEL

4
SPARE4

3
2
SCLK_LF_SRC_SEL

R/W-0h

1
SCLK_MF_SR
C_SEL
R/W-0h

R/W-0h

8
ACLK_TDC_S
RC_SEL
R/W-0h
0
SCLK_HF_SR
C_SEL
R/W-0h

Table 6-26. CTL0 Register Field Descriptions
Bit

Field

Type

Reset

Description

XTAL_IS_24M

R/W

Set based on the accurate high frequency XTAL.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BYPASS_XOSC_LF_CLK R/W
_QUAL

Internal. Only to be used through TI provided API.

BYPASS_RCOSC_LF_CL R/W
K_QUAL

Internal. Only to be used through TI provided API.

27-26

DOUBLER_START_DUR
ATION

R/W

Internal. Only to be used through TI provided API.

DOUBLER_RESET_DUR
ATION

R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

FORCE_KICKSTART_EN R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ALLOW_SCLK_HF_SWIT R/W
CHING

24-23
22
21-17
16

450

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

Table 6-26. CTL0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HPOSC_MODE_EN

R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RCOSC_LF_TRIMMED

R/W

Internal. Only to be used through TI provided API.

XOSC_HF_POWER_MO
DE

R/W

Internal. Only to be used through TI provided API.

XOSC_LF_DIG_BYPASS

R/W

CLK_LOSS_EN

R/W

8-7

ACLK_TDC_SRC_SEL

R/W

Source select for aclk_tdc.
00: RCOSC_HF (48MHz)
01: RCOSC_HF (24MHz)
10: XOSC_HF (24MHz)
11: Not used

6-5

ACLK_REF_SRC_SEL

R/W

Source select for aclk_ref
00: RCOSC_HF derived (31.25kHz)
01: XOSC_HF derived (31.25kHz)
10: RCOSC_LF (32kHz)
11: XOSC_LF (32.768kHz)

SPARE4

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-2

SCLK_LF_SRC_SEL

R/W

Source select for sclk_lf
0h = Low frequency clock derived from High Frequency RCOSC
1h = Low frequency clock derived from High Frequency XOSC
2h = Low frequency RCOSC
3h = Low frequency XOSC

SCLK_MF_SRC_SEL

R/W

Internal. Only to be used through TI provided API.

SCLK_HF_SRC_SEL

R/W

Source select for sclk_hf. XOSC option is supported for test and
debug only and should be used when the XOSC_HF is running.
0h = High frequency RCOSC clock
1h = High frequency XOSC clk

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

451

PRCM Registers

www.ti.com

6.8.2.1.2 CTL1 Register (Offset = 4h) [reset = 0h]
CTL1 is shown in Figure 6-24 and described in Table 6-27.
Return to Summary Table.
Control 1
This register contains OSC_DIG configuration
Figure 6-24. CTL1 Register
31

17
RCOSCHFCTR
IMFRACT_EN
R/W-0h

16
SPARE2

RESERVED
R/W-0h
23
RESERVED

20
RCOSCHFCTRIMFRACT

R/W-0h

SPARE2
R/W-0h
7

4
SPARE2
R/W-0h

1
0
XOSC_HF_FAST_START
R/W-0h

Table 6-27. CTL1 Register Field Descriptions
Bit

452

Field

Type

Reset

Description

31-23

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

22-18

RCOSCHFCTRIMFRACT

R/W

Internal. Only to be used through TI provided API.

RCOSCHFCTRIMFRACT
_EN

R/W

Internal. Only to be used through TI provided API.

16-2

SPARE2

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

XOSC_HF_FAST_START R/W

Internal. Only to be used through TI provided API.

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.1.3 RADCEXTCFG Register (Offset = 8h) [reset = 0h]
RADCEXTCFG is shown in Figure 6-25 and described in Table 6-28.
Return to Summary Table.
RADC External Configuration
Figure 6-25. RADCEXTCFG Register
31

23
22
HPM_IBIAS_WAIT_CNT
R/W-0h
15

28
27
HPM_IBIAS_WAIT_CNT
R/W-0h

5
RADC_MODE_
IS_SAR
R/W-0h

R/W-0h

10
9
RADC_DAC_TH
R/W-0h

19
18
LPM_IBIAS_WAIT_CNT
R/W-0h

IDAC_STEP
R/W-0h
7
6
RADC_DAC_TH

2
RESERVED

R/W-0h

Table 6-28. RADCEXTCFG Register Field Descriptions
Field

Type

Reset

Description

31-22

Bit

HPM_IBIAS_WAIT_CNT

R/W

Internal. Only to be used through TI provided API.

21-16

LPM_IBIAS_WAIT_CNT

R/W

Internal. Only to be used through TI provided API.

15-12

IDAC_STEP

R/W

Internal. Only to be used through TI provided API.

11-6

RADC_DAC_TH

R/W

Internal. Only to be used through TI provided API.

RADC_MODE_IS_SAR

R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

5
4-0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

453

PRCM Registers

www.ti.com

6.8.2.1.4 AMPCOMPCTL Register (Offset = Ch) [reset = 0h]
AMPCOMPCTL is shown in Figure 6-26 and described in Table 6-29.
Return to Summary Table.
Amplitude Compensation Control
Figure 6-26. AMPCOMPCTL Register
31
SPARE31
R/W-0h

30
AMPCOMP_RE
Q_MODE
R/W-0h

29
28
AMPCOMP_FSM_UPDATE_RA
TE
R/W-0h

22
21
IBIAS_OFFSET
R/W-0h

27
AMPCOMP_S
W_CTRL
R/W-0h

26
AMPCOMP_S
W_EN
R/W-0h

RESERVED
R/W-0h

IBIAS_INIT
R/W-0h

12
11
LPM_IBIAS_WAIT_CNT_FINAL
R/W-0h

CAP_STEP
R/W-0h

2
1
IBIASCAP_HPTOLP_OL_CNT
R/W-0h

Table 6-29. AMPCOMPCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

SPARE31

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AMPCOMP_REQ_MODE

R/W

Internal. Only to be used through TI provided API.

AMPCOMP_FSM_UPDAT R/W
E_RATE

Internal. Only to be used through TI provided API.

AMPCOMP_SW_CTRL

R/W

Internal. Only to be used through TI provided API.

AMPCOMP_SW_EN

R/W

Internal. Only to be used through TI provided API.

25-24

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-20

IBIAS_OFFSET

R/W

Internal. Only to be used through TI provided API.

19-16

IBIAS_INIT

R/W

Internal. Only to be used through TI provided API.

15-8

LPM_IBIAS_WAIT_CNT_
FINAL

R/W

Internal. Only to be used through TI provided API.

7-4

CAP_STEP

R/W

Internal. Only to be used through TI provided API.

3-0

IBIASCAP_HPTOLP_OL_ R/W
CNT

Internal. Only to be used through TI provided API.

29-28

454

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.1.5 AMPCOMPTH1 Register (Offset = 10h) [reset = 0h]
AMPCOMPTH1 is shown in Figure 6-27 and described in Table 6-30.
Return to Summary Table.
Amplitude Compensation Threshold 1
This register contains threshold values for amplitude compensation algorithm
Figure 6-27. AMPCOMPTH1 Register
31

21
20
HPMRAMP3_LTH
R/W-0h

13
12
HPMRAMP3_HTH
R/W-0h

3
2
HPMRAMP1_TH
R/W-0h

SPARE24
R/W-0h
23

7
6
IBIASCAP_LPTOHP_OL_CNT
R/W-0h

16
SPARE16
R/W-0h

9
8
IBIASCAP_LPTOHP_OL_CNT
R/W-0h
1

Table 6-30. AMPCOMPTH1 Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

SPARE24

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-18

HPMRAMP3_LTH

R/W

Internal. Only to be used through TI provided API.

17-16

SPARE16

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-10

HPMRAMP3_HTH

R/W

Internal. Only to be used through TI provided API.

9-6

IBIASCAP_LPTOHP_OL_ R/W
CNT

Internal. Only to be used through TI provided API.

5-0

HPMRAMP1_TH

Internal. Only to be used through TI provided API.

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

455

PRCM Registers

www.ti.com

6.8.2.1.6 AMPCOMPTH2 Register (Offset = 14h) [reset = 0h]
AMPCOMPTH2 is shown in Figure 6-28 and described in Table 6-31.
Return to Summary Table.
Amplitude Compensation Threshold 2
This register contains threshold values for amplitude compensation algorithm.
Figure 6-28. AMPCOMPTH2 Register
31

29
28
LPMUPDATE_LTH
R/W-0h

21
20
LPMUPDATE_HTH
R/W-0h

13
12
ADC_COMP_AMPTH_LPM
R/W-0h

5
4
ADC_COMP_AMPTH_HPM
R/W-0h

24
SPARE24
R/W-0h

16
SPARE16
R/W-0h

8
SPARE8
R/W-0h

0
SPARE0
R/W-0h

Table 6-31. AMPCOMPTH2 Register Field Descriptions
Bit

456

Field

Type

Reset

Description

31-26

LPMUPDATE_LTH

R/W

Internal. Only to be used through TI provided API.

25-24

SPARE24

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-18

LPMUPDATE_HTH

R/W

Internal. Only to be used through TI provided API.

17-16

SPARE16

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-10

ADC_COMP_AMPTH_LP
M

R/W

Internal. Only to be used through TI provided API.

9-8

SPARE8

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-2

ADC_COMP_AMPTH_HP R/W
M

Internal. Only to be used through TI provided API.

1-0

SPARE0

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.1.7 ANABYPASSVAL1 Register (Offset = 18h) [reset = 0h]
ANABYPASSVAL1 is shown in Figure 6-29 and described in Table 6-32.
Return to Summary Table.
Analog Bypass Values 1
Figure 6-29. ANABYPASSVAL1 Register
31

RESERVED
R/W-0h
23

RESERVED
R/W-0h

18
17
XOSC_HF_ROW_Q12
R/W-0h

12
11
XOSC_HF_COLUMN_Q12
R/W-0h

4
3
XOSC_HF_COLUMN_Q12
R/W-0h

Table 6-32. ANABYPASSVAL1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-20

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

19-16

XOSC_HF_ROW_Q12

R/W

Internal. Only to be used through TI provided API.

15-0

XOSC_HF_COLUMN_Q1
2

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

457

PRCM Registers

www.ti.com

6.8.2.1.8 ANABYPASSVAL2 Register (Offset = 1Ch) [reset = 0h]
ANABYPASSVAL2 is shown in Figure 6-30 and described in Table 6-33.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 6-30. ANABYPASSVAL2 Register
31

15
14
RESERVED
R/W-0h

24
23
RESERVED
R/W-0h

8
7
6
5
XOSC_HF_IBIASTHERM
R/W-0h

Table 6-33. ANABYPASSVAL2 Register Field Descriptions
Bit

458

Field

Type

Reset

Description

31-14

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

13-0

XOSC_HF_IBIASTHERM

R/W

Internal. Only to be used through TI provided API.

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.1.9 ATESTCTL Register (Offset = 20h) [reset = 0h]
ATESTCTL is shown in Figure 6-31 and described in Table 6-34.
Return to Summary Table.
Analog Test Control
Figure 6-31. ATESTCTL Register
31

30
SPARE30
R/W-0h

29
SCLK_LF_AUX
_EN
R/W-0h

26
RESERVED

R/W-0h
19

RESERVED
R/W-0h
15

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 6-34. ATESTCTL Register Field Descriptions
Bit
31-30
29
28-0

Field

Type

Reset

Description

SPARE30

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SCLK_LF_AUX_EN

R/W

Enable 32 kHz clock to AUX_COMPB.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

459

PRCM Registers

www.ti.com

6.8.2.1.10 ADCDOUBLERNANOAMPCTL Register (Offset = 24h) [reset = 0h]
ADCDOUBLERNANOAMPCTL is shown in Figure 6-32 and described in Table 6-35.
Return to Summary Table.
ADC Doubler Nanoamp Control
Figure 6-32. ADCDOUBLERNANOAMPCTL Register
31

28
RESERVED

24
NANOAMP_BI
AS_ENABLE
R/W-0h

19
RESERVED
R/W-0h

2
RESERVED

1
0
ADC_IREF_CTRL

R/W-0h

R/W-0h
23
SPARE23
R/W-0h

12
RESERVED
R/W-0h

5
ADC_SH_MOD
E_EN
R/W-0h

RESERVED
R/W-0h

4
ADC_SH_VBU
F_EN
R/W-0h

Table 6-35. ADCDOUBLERNANOAMPCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

NANOAMP_BIAS_ENABL R/W
E

Internal. Only to be used through TI provided API.

SPARE23

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ADC_SH_MODE_EN

R/W

Internal. Only to be used through TI provided API.

ADC_SH_VBUF_EN

R/W

Internal. Only to be used through TI provided API.

3-2

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

ADC_IREF_CTRL

R/W

Internal. Only to be used through TI provided API.

31-25

22-6

460

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.1.11 XOSCHFCTL Register (Offset = 28h) [reset = 0h]
XOSCHFCTL is shown in Figure 6-33 and described in Table 6-36.
Return to Summary Table.
XOSCHF Control
Figure 6-33. XOSCHFCTL Register
31

9
8
PEAK_DET_ITRIM
R/W-0h

3
HP_BUF_ITRIM
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

13
RESERVED
R/W-0h

7
RESERVED
R/W-0h

6
BYPASS
R/W-0h

5
RESERVED
R/W-0h

0
LP_BUF_ITRIM
R/W-0h

Table 6-36. XOSCHFCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

PEAK_DET_ITRIM

R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BYPASS

R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

4-2

HP_BUF_ITRIM

R/W

Internal. Only to be used through TI provided API.

1-0

LP_BUF_ITRIM

R/W

Internal. Only to be used through TI provided API.

31-10
9-8

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

461

PRCM Registers

www.ti.com

6.8.2.1.12 LFOSCCTL Register (Offset = 2Ch) [reset = 0h]
LFOSCCTL is shown in Figure 6-34 and described in Table 6-37.
Return to Summary Table.
Low Frequency Oscillator Control
Figure 6-34. LFOSCCTL Register
31

RESERVED
R/W-0h
23
22
XOSCLF_REGULATOR_TRIM
R/W-0h
15

20
19
XOSCLF_CMIRRWR_RATIO
R/W-0h

RESERVED
R/W-0h
7

16
RESERVED
R/W-0h

4
3
RCOSCLF_CTUNE_TRIM
R/W-0h

9
8
RCOSCLF_RTUNE_TRIM
R/W-0h
1

Table 6-37. LFOSCCTL Register Field Descriptions
Bit

462

Field

Type

Reset

Description

31-24

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-22

XOSCLF_REGULATOR_
TRIM

R/W

Internal. Only to be used through TI provided API.

21-18

XOSCLF_CMIRRWR_RA
TIO

R/W

Internal. Only to be used through TI provided API.

17-10

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

9-8

RCOSCLF_RTUNE_TRIM R/W

Internal. Only to be used through TI provided API.

7-0

RCOSCLF_CTUNE_TRIM R/W

Internal. Only to be used through TI provided API.

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.1.13 RCOSCHFCTL Register (Offset = 30h) [reset = 0h]
RCOSCHFCTL is shown in Figure 6-35 and described in Table 6-38.
Return to Summary Table.
RCOSCHF Control
Figure 6-35. RCOSCHFCTL Register
31

12
11
RCOSCHF_CTRIM
R/W-0h

24
23
RESERVED
R/W-0h
8

4
3
RESERVED
R/W-0h

Table 6-38. RCOSCHFCTL Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-8

RCOSCHF_CTRIM

R/W

Internal. Only to be used through TI provided API.

7-0

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

463

PRCM Registers

www.ti.com

6.8.2.1.14 STAT0 Register (Offset = 34h) [reset = 0h]
STAT0 is shown in Figure 6-36 and described in Table 6-39.
Return to Summary Table.
Status 0
This register contains status signals from OSC_DIG
Figure 6-36. STAT0 Register
31
SPARE31

30
29
SCLK_LF_SRC

R-0h

23
RESERVED

28
SCLK_HF_SR
C
R-0h

19
CLK_DCDC_R
DY
R-0h

18
CLK_DCDC_R
DY_ACK
R-0h

11
XOSC_HF_LP_
BUF_EN
R-0h

10
XOSC_HF_HP
_BUF_EN
R-0h

9
RESERVED

8
ADC_THMET

R-0h

0
PENDINGSCL
KHFSWITCHIN
G
R-0h

21
RCOSC_LF_E
N
R-0h

20
XOSC_LF_EN

R-0h

22
RCOSC_HF_E
N
R-0h

15
XOSC_HF_EN

14
RESERVED

12
RESERVED

R-0h

13
XB_48M_CLK_
EN
R-0h

7
ADC_DATA_R
EADY

R-0h

R-0h
17
16
SCLK_HF_LOS SCLK_LF_LOS
S
S
R-0h
R-0h

ADC_DATA

R-0h

RESERVED

R-0h

Table 6-39. STAT0 Register Field Descriptions
Bit

Field

Type

Reset

Description

SPARE31

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

30-29

SCLK_LF_SRC

Indicates source for the sclk_lf
0h = Low frequency clock derived from High Frequency RCOSC
1h = Low frequency clock derived from High Frequency XOSC
2h = Low frequency RCOSC
3h = Low frequency XOSC

SCLK_HF_SRC

Indicates source for the sclk_hf
0h = High frequency RCOSC clock
1h = High frequency XOSC

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RCOSC_HF_EN

RCOSC_LF_EN

XOSC_LF_EN

CLK_DCDC_RDY

CLK_DCDC_RDY_ACK

SCLK_HF_LOSS

Indicates sclk_hf is lost

SCLK_LF_LOSS

Indicates sclk_lf is lost

XOSC_HF_EN

Indicates that XOSC_HF is enabled.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

27-23

464

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

Table 6-39. STAT0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

XB_48M_CLK_EN

Indicates that the 48MHz clock from the DOUBLER is enabled.
It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler
bypass for the 48MHz crystal).

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

XOSC_HF_LP_BUF_EN

XOSC_HF_HP_BUF_EN

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ADC_THMET

ADC_DATA_READY

indicates when adc_data is ready.

ADC_DATA

adc_data

PENDINGSCLKHFSWITC R
HING

Indicates when sclk_hf is ready to be switched

6-1
0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

465

PRCM Registers

www.ti.com

6.8.2.1.15 STAT1 Register (Offset = 38h) [reset = 0h]
STAT1 is shown in Figure 6-37 and described in Table 6-40.
Return to Summary Table.
Status 1
This register contains status signals from OSC_DIG
Figure 6-37. STAT1 Register
31

19
18
LPM_UPDATE_AMP
R-0h
11
ACLK_TDC_E
N
R-0h
3
ACLK_TDC_G
OOD
R-0h

RAMPSTATE
R-0h
23
22
HPM_UPDATE_AMP
R-0h
15
FORCE_RCOS
C_HF
R-0h

14
SCLK_HF_EN

13
SCLK_MF_EN

R-0h

12
ACLK_ADC_E
N
R-0h

7
SCLK_HF_GO
OD
R-0h

6
SCLK_MF_GO
OD
R-0h

5
SCLK_LF_GO
OD
R-0h

4
ACLK_ADC_G
OOD
R-0h

26
25
HPM_UPDATE_AMP
R-0h

10
ACLK_REF_EN

9
CLK_CHP_EN

R-0h

8
CLK_DCDC_E
N
R-0h

2
ACLK_REF_G
OOD
R-0h

1
CLK_CHP_GO
OD
R-0h

0
CLK_DCDC_G
OOD
R-0h

Table 6-40. STAT1 Register Field Descriptions
Bit

466

Field

Type

Reset

Description

31-28

RAMPSTATE

27-22

HPM_UPDATE_AMP

21-16

LPM_UPDATE_AMP

FORCE_RCOSC_HF

force_rcosc_hf

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

Table 6-40. STAT1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

SCLK_HF_EN

SCLK_MF_EN

ACLK_ADC_EN

ACLK_TDC_EN

ACLK_REF_EN

CLK_CHP_EN

CLK_DCDC_EN

SCLK_HF_GOOD

SCLK_MF_GOOD

SCLK_LF_GOOD

ACLK_ADC_GOOD

ACLK_TDC_GOOD

ACLK_REF_GOOD

CLK_CHP_GOOD

CLK_DCDC_GOOD

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

467

PRCM Registers

www.ti.com

6.8.2.1.16 STAT2 Register (Offset = 3Ch) [reset = 0h]
STAT2 is shown in Figure 6-38 and described in Table 6-41.
Return to Summary Table.
Status 2
This register contains status signals from AMPCOMP FSM
Figure 6-38. STAT2 Register
31

25
HPM_RAMP1_
THMET
R-0h

24
HPM_RAMP2_
THMET
R-0h

19
RESERVED

1
XOSC_HF_FR
EQGOOD
R-0h

0
XOSC_HF_RF
_FREQGOOD
R-0h

ADC_DCBIAS
R-0h
23
HPM_RAMP3_
THMET
R-0h

R-0h
13

RAMPSTATE
R-0h
7

RESERVED
R-0h
5

RESERVED
R-0h

3
2
AMPCOMP_RE XOSC_HF_AM
Q
PGOOD
R-0h
R-0h

Table 6-41. STAT2 Register Field Descriptions
Bit

Field

Type

Reset

Description

ADC_DCBIAS

DC Bias read by RADC during SAR mode
The value is an unsigned integer. It is used for debug only.

HPM_RAMP1_THMET

Indication of threshold is met for hpm_ramp1

HPM_RAMP2_THMET

Indication of threshold is met for hpm_ramp2

HPM_RAMP3_THMET

Indication of threshold is met for hpm_ramp3

22-16

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-12

RAMPSTATE

xosc_hf amplitude compensation FSM
This is identical to STAT1.RAMPSTATE. See that description for
encoding.

11-4

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AMPCOMP_REQ

ampcomp_req

XOSC_HF_AMPGOOD

amplitude of xosc_hf is within the required threshold (set by DDI).
Not used for anything just for debug/status

XOSC_HF_FREQGOOD

frequency of xosc_hf is good to use for the digital clocks

XOSC_HF_RF_FREQGO
OD

frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for
radio operations. Used for SW to start synthesizer.

31-26

468

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.2

AON_SYSCTL Registers

Table 6-42 lists the memory-mapped registers for the AON_SYSCTL. All register offset addresses not
listed in Table 6-42 should be considered as reserved locations and the register contents should not be
modified.
Table 6-42. AON_SYSCTL Registers
Offset

Acronym

PWRCTL

Power Management

Section 6.8.2.2.1

RESETCTL

Reset Management

Section 6.8.2.2.2

SLEEPCTL

Sleep Mode

Section 6.8.2.2.3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Section

Power, Reset, and Clock Management

469

PRCM Registers

www.ti.com

6.8.2.2.1 PWRCTL Register (Offset = 0h) [reset = 0h]
PWRCTL is shown in Figure 6-39 and described in Table 6-43.
Return to Summary Table.
Power Management
This register controls bitfields for setting low level power management features such as selection of
regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled.
Figure 6-39. PWRCTL Register
31

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

5
RESERVED

R/W-0h

2
1
DCDC_ACTIVE EXT_REG_MO
DE
R/W-0h
R-0h

0
DCDC_EN
R/W-0h

Table 6-43. PWRCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DCDC_ACTIVE

R/W

Select to use DCDC regulator for VDDR in active mode
0: Use GLDO for regulation of VDDRin active mode.
1: Use DCDC for regulation of VDDRin active mode.

EXT_REG_MODE

Status of source for VDDRsupply:
0: DCDC/GLDO are generating VDDR
1: DCDC/GLDO are bypassed, external regulator supplies VDDR

DCDC_EN

R/W

Select to use DCDC regulator during recharge of VDDR
0: Use GLDO for recharge of VDDR
1: Use DCDC for recharge of VDDR
Note: This bitfield should be set to the same as DCDC_ACTIVE

31-3

470

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.2.2 RESETCTL Register (Offset = 4h) [reset = E0h]
RESETCTL is shown in Figure 6-40 and described in Table 6-44.
Return to Summary Table.
Reset Management
This register contains bitfields releated to system reset such as reset source and reset request and control
of brown out resets.
Figure 6-40. RESETCTL Register
31
SYSRESET

28
RESERVED

W-0h

25
24
BOOT_DET_1_ BOOT_DET_0_
CLR
CLR
R/W-0h
R/W-0h

17
16
BOOT_DET_1_ BOOT_DET_0_
SET
SET
R/W-0h
R/W-0h

11
VDDS_LOSS_
EN_OVR
R/W-0h

10
VDDR_LOSS_
EN_OVR
R/W-0h

9
VDD_LOSS_E
N_OVR
R/W-0h

8
RESERVED

2
RESET_SRC

0
RESERVED

R-0h

RESERVED
R-0h
15
WU_FROM_SD

13
BOOT_DET_1

12
BOOT_DET_0

R-0h

14
GPIO_WU_FR
OM_SD
R-0h

R-0h

7
VDDS_LOSS_
EN
R/W-1h

6
VDDR_LOSS_
EN
R/W-1h

5
VDD_LOSS_E
N
R/W-1h

4
CLK_LOSS_EN
R/W-0h

R-0h

Table 6-44. RESETCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

SYSRESET

Cold reset register. Writing 1 to this bitfield will reset the entire chip
and cause boot code to run again.
0: No effect
1: Generate system reset. Appears as SYSRESET in RESET_SRC.

30-26

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BOOT_DET_1_CLR

R/W

Internal. Only to be used through TI provided API.

BOOT_DET_0_CLR

R/W

Internal. Only to be used through TI provided API.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BOOT_DET_1_SET

R/W

Internal. Only to be used through TI provided API.

BOOT_DET_0_SET

R/W

Internal. Only to be used through TI provided API.

WU_FROM_SD

A Wakeup from SHUTDOWN on an IO event has occurred, or a
wakeup from SHUTDOWN has occurred as a result of the debugger
being attached.. (TCK pin being forced low)
Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as
wakeup sources.
0: Wakeup occurred from cold reset or brown out as seen in
RESET_SRC
1: A wakeup has occurred from SHUTDOWN
Note: This flag can not be cleared and will therefor remain valid untill
poweroff/reset

23-18

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

471

PRCM Registers

www.ti.com

Table 6-44. RESETCTL Register Field Descriptions (continued)

472

Bit

Field

Type

Reset

Description

GPIO_WU_FROM_SD

A wakeup from SHUTDOWN on an IO event has occurred
Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as
wakeup sources.
0: The wakeup did not occur from SHUTDOWN on an IO event
1: A wakeup from SHUTDOWN occurred from an IO event
The case where WU_FROM_SD is asserted but this bitfield is not
asserted will only occur in a debug session. The boot code will not
proceed with wakeup from SHUTDOWN procedure until this bitfield
is asserted as well.
Note: This flag can not be cleared and will therefor remain valid untill
poweroff/reset

BOOT_DET_1

Internal. Only to be used through TI provided API.

BOOT_DET_0

Internal. Only to be used through TI provided API.

VDDS_LOSS_EN_OVR

R/W

Override of VDDS_LOSS_EN
0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN=1
1: Brown out detect of VDDS generates system reset (regardless of
VDDS_LOSS_EN)
This bit can be locked

VDDR_LOSS_EN_OVR

R/W

Override of VDDR_LOSS_EN
0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN=1
1: Brown out detect of VDDR generates system reset (regardless of
VDDR_LOSS_EN)
This bit can be locked

VDD_LOSS_EN_OVR

R/W

Override of VDD_LOSS_EN
0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN=1
1: Brown out detect of VDD generates system reset (regardless of
VDD_LOSS_EN)
This bit can be locked

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

VDDS_LOSS_EN

R/W

Controls reset generation in case VDDS is lost
0: Brown out detect of VDDS is ignored, unless
VDDS_LOSS_EN_OVR=1
1: Brown out detect of VDDS generates system reset

VDDR_LOSS_EN

R/W

Controls reset generation in case VDDR is lost
0: Brown out detect of VDDR is ignored, unless
VDDR_LOSS_EN_OVR=1
1: Brown out detect of VDDR generates system reset

VDD_LOSS_EN

R/W

Controls reset generation in case VDD is lost
0: Brown out detect of VDD is ignored, unless
VDD_LOSS_EN_OVR=1
1: Brown out detect of VDD generates system reset

CLK_LOSS_EN

R/W

Controls reset generation in case SCLK_LF is lost. (provided that
clock loss detection is enabled by
DDI_0_OSC:CTL0.CLK_LOSS_EN)
Note: Clock loss reset generation must be disabled before SCLK_LF
clock source is changed in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL
and remain disabled untill the change is confirmed in
DDI_0_OSC:STAT0.SCLK_LF_SRC. Failure to do so may result in a
spurious system reset. Clock loss reset generation can be disabled
through this bitfield or by clearing
DDI_0_OSC:CTL0.CLK_LOSS_EN
0: Clock loss is ignored
1: Clock loss generates system reset

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

Table 6-44. RESETCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-1

RESET_SRC

Shows the source of the last system reset:
Occurrence of one of the reset sources may trigger several other
reset sources as essential parts of the system are undergoing reset.
This field will report the root cause of the reset (not the other resets
that are consequence of the system reset).
To support this feature the actual register is not captured before the
reset source being released. If a new reset source is triggered, in a
window of four 32 kHz periods after the previous has been released,
this register may indicate Power on reset as source.
0h = Power on reset
1h = Reset pin
2h = Brown out detect on VDDS
3h = Brown out detect on VDD
4h = Brown out detect on VDDR
5h = Clock loss detect
6h = Software reset via SYSRESET register
7h = Software reset via PRCM warm reset request

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

473

PRCM Registers

www.ti.com

6.8.2.2.3 SLEEPCTL Register (Offset = 8h) [reset = 0h]
SLEEPCTL is shown in Figure 6-41 and described in Table 6-45.
Return to Summary Table.
Sleep Mode
This register is used to unfreeze the IO pad ring after waking up from SHUTDOWN
Figure 6-41. SLEEPCTL Register
31

0
IO_PAD_SLEE
P_DIS
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 6-45. SLEEPCTL Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

IO_PAD_SLEEP_DIS

R/W

Controls the I/O pad sleep mode. The boot code will set this bitfield
automatically unless waking up from a SHUTDOWN (
RESETCTL.WU_FROM_SD is set ).
0: I/O pad sleep mode is enabled, ie all pads are latched and can
not toggle.
1: I/O pad sleep mode is disabled
Application software may want to reconfigure the state for all IO's
before setting this bitfield upon waking up from a SHUTDOWN.

6.8.2.3 AON_WUC Registers
Table 6-46 lists the memory-mapped registers for the AON_WUC. All register offset addresses not listed
in Table 6-46 should be considered as reserved locations and the register contents should not be
modified.
Table 6-46. AON_WUC Registers

474

Offset

Acronym

MCUCLK

MCU Clock Management

Section 6.8.2.3.1

Section

AUXCLK

AUX Clock Management

Section 6.8.2.3.2

MCUCFG

MCU Configuration

Section 6.8.2.3.3

AUXCFG

AUX Configuration

Section 6.8.2.3.4

10h

AUXCTL

AUX Control

Section 6.8.2.3.5

14h

PWRSTAT

Power Status

Section 6.8.2.3.6

18h

SHUTDOWN

Shutdown Control

Section 6.8.2.3.7

20h

CTL0

Control 0

Section 6.8.2.3.8

24h

CTL1

Control 1

Section 6.8.2.3.9

30h

RECHARGECFG

Recharge Controller Configuration

Section 6.8.2.3.10

34h

RECHARGESTAT

Recharge Controller Status

Section 6.8.2.3.11

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

Table 6-46. AON_WUC Registers (continued)
Offset

Acronym

38h

OSCCFG

Oscillator Configuration

Section 6.8.2.3.12

40h

JTAGCFG

JTAG Configuration

Section 6.8.2.3.13

44h

JTAGUSERCODE

JTAG USERCODE

Section 6.8.2.3.14

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Section

Power, Reset, and Clock Management

475

PRCM Registers

www.ti.com

6.8.2.3.1 MCUCLK Register (Offset = 0h) [reset = 0h]
MCUCLK is shown in Figure 6-42 and described in Table 6-47.
Return to Summary Table.
MCU Clock Management
This register contains bitfields related to the MCU clock.
Figure 6-42. MCUCLK Register
31

2
RCOSC_HF_C
AL_DONE
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED

R-0h

1
0
PWR_DWN_SRC
R/W-0h

Table 6-47. MCUCLK Register Field Descriptions
Bit
31-3
2

1-0

476

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RCOSC_HF_CAL_DONE

R/W

MCU bootcode will set this bit when RCOSC_HF is calibrated. The
FLASH can not be used until this bit is set.
1: RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power
up.
0: RCOSC_HF is not yet calibrated, ie FLASH must not assume that
the SCLK_HF is safe

PWR_DWN_SRC

R/W

Controls the clock source for the entire MCU domain while MCU is
requesting powerdown.
When MCU requests powerdown with SCLK_HF as source, then
WUC will switch over to this clock source during powerdown, and
automatically switch back to SCLK_HF when MCU is no longer
requesting powerdown and system is back in active mode.
0h = No clock in Powerdown
1h = Use SCLK_LF in Powerdown

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.3.2 AUXCLK Register (Offset = 4h) [reset = 1h]
AUXCLK is shown in Figure 6-43 and described in Table 6-48.
Return to Summary Table.
AUX Clock Management
This register contains bitfields that are relevant for setting up the clock to the AUX domain.
Figure 6-43. AUXCLK Register
31

12
11
PWR_DWN_SRC
R/W-0h

9
SCLK_HF_DIV
R/W-0h

1
SRC
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

14
RESERVED
R-0h

5
RESERVED
R-0h

Table 6-48. AUXCLK Register Field Descriptions
Field

Type

Reset

Description

31-13

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

12-11

PWR_DWN_SRC

R/W

When AUX requests powerdown with SCLK_HF as source, then
WUC will switch over to this clock source during powerdown, and
automatically switch back to SCLK_HF when AUX system is back in
active mode
0h = No clock in Powerdown
1h = Use SCLK_LF in Powerdown

10-8

SCLK_HF_DIV

R/W

Select the AUX clock divider for SCLK_HF
NB: It is not supported to change the AUX clock divider while
SCLK_HF is active source for AUX
0h = Divide by 2
1h = Divide by 4
2h = Divide by 8
3h = Divide by 16
4h = Divide by 32
5h = Divide by 64
6h = Divide by 128
7h = Divide by 256

7-3

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

2-0

SRC

R/W

Selects the clock source for AUX:
NB: Switching the clock source is guaranteed to be glitchless
1h = HF Clock (SCLK_HF)
4h = LF Clock (SCLK_LF)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

477

PRCM Registers

www.ti.com

6.8.2.3.3 MCUCFG Register (Offset = 8h) [reset = Fh]
MCUCFG is shown in Figure 6-44 and described in Table 6-49.
Return to Summary Table.
MCU Configuration
This register contains power management related bitfields for the MCU domain.
Figure 6-44. MCUCFG Register
31

17
VIRT_OFF
R/W-0h

16
FIXED_WU_EN
R/W-0h

2
1
SRAM_RET_EN
R/W-Fh

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

RESERVED
R-0h

Table 6-49. MCUCFG Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

VIRT_OFF

R/W

Internal. Only to be used through TI provided API.

FIXED_WU_EN

R/W

Internal. Only to be used through TI provided API.

15-4

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

SRAM_RET_EN

R/W

MCU SRAM is partitioned into 4 banks . This register controls which
of the banks that has retention during MCU power off
0h = Retention is disabled
1h = Retention on for SRAM:BANK0
3h = Retention on for SRAM:BANK0 and SRAM:BANK1
7h = Retention on for SRAM:BANK0, SRAM:BANK1 and
SRAM:BANK2
Fh = Retention on for all banks (SRAM:BANK0, SRAM:BANK1
,SRAM:BANK2 and SRAM:BANK3)

31-18

478

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.3.4 AUXCFG Register (Offset = Ch) [reset = 1h]
AUXCFG is shown in Figure 6-45 and described in Table 6-50.
Return to Summary Table.
AUX Configuration
This register contains power management related signals for the AUX domain.
Figure 6-45. AUXCFG Register
31

0
RAM_RET_EN
R/W-1h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 6-50. AUXCFG Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RAM_RET_EN

R/W

This bit controls retention mode for the AUX_RAM:BANK0:
0: Retention is disabled
1: Retention is enabled
NB: If retention is disabled, the AUX_RAM will be powered off when
it would otherwise be put in retention mode

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

479

PRCM Registers

www.ti.com

6.8.2.3.5 AUXCTL Register (Offset = 10h) [reset = 0h]
AUXCTL is shown in Figure 6-46 and described in Table 6-51.
Return to Summary Table.
AUX Control
This register contains events and control signals for the AUX domain.
Figure 6-46. AUXCTL Register
31
RESET_REQ
R/W-0h

27
RESERVED
R-0h

2
SCE_RUN_EN

1
SWEV

R/W-0h

0
AUX_FORCE_
ON
R/W-0h

RESERVED
R-0h
15

12
RESERVED
R-0h

5
RESERVED

R-0h

Table 6-51. AUXCTL Register Field Descriptions

480

Bit

Field

Type

Reset

Description

RESET_REQ

R/W

Reset request for AUX. Writing 1 to this register will assert reset to
AUX. The reset will be held until the bit is cleared again.
0: AUX reset pin will be deasserted
1: AUX reset pin will be asserted

30-3

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SCE_RUN_EN

R/W

Enables (1) or disables (0) AUX_SCE execution. AUX_SCE
execution will begin when AUX Domain is powered and either this or
AUX_SCE:CTL.CLK_EN is set.
Setting this bit will assure that AUX_SCE execution starts as soon
as AUX power domain is woken up. ( AUX_SCE:CTL.CLK_EN will
be reset to 0 if AUX power domain has been off)
0: AUX_SCE execution will be disabled if AUX_SCE:CTL.CLK_EN is
0
1: AUX_SCE execution is enabled.

SWEV

R/W

Writing 1 sets the software event to the AUX domain, which can be
read through AUX_WUC:WUEVFLAGS.AON_SW.
This event is normally cleared by AUX_SCE through the
AUX_WUC:WUEVCLR.AON_SW. It can also be cleared by writing 0
to this register.
Reading 0 means that there is no outstanding software event for
AUX.
Note that it can take up to 1,5 SCLK_LF clock cycles to clear the
event from AUX.

AUX_FORCE_ON

R/W

Forces the AUX domain into active mode, overriding the requests
from AUX_WUC:PWROFFREQ, AUX_WUC:PWRDWNREQ and
AUX_WUC:MCUBUSCTL.
Note that an ongoing AUX_WUC:PWROFFREQ will complete before
this bit will set the AUX domain into active mode.
MCU must set this bit in order to access the AUX peripherals.
The AUX domain status can be read from PWRSTAT.AUX_PD_ON
0: AUX is allowed to Power Off, Power Down or Disconnect.
1: AUX Power OFF, Power Down or Disconnect requests will be
overruled

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.3.6 PWRSTAT Register (Offset = 14h) [reset = 03800000h]
PWRSTAT is shown in Figure 6-47 and described in Table 6-52.
Return to Summary Table.
Power Status
This register is used to monitor various power management related signals in AON. Most signals are for
test, calibration and debug purpose only, and others can be used to detect that AUX or JTAG domains are
powered up.
Figure 6-47. PWRSTAT Register
31

9
AUX_PWR_D
WN
R-0h

8
RESERVED

1
AUX_RESET_
DONE
R-0h

0
RESERVED

RESERVED
R/W-E000h
23

20
RESERVED
R/W-E000h

12
RESERVED
R/W-E000h

7
RESERVED

6
JTAG_PD_ON

5
AUX_PD_ON

4
MCU_PD_ON

3
RESERVED

R-0h

2
AUX_BUS_CO
NNECTED
R-0h

R-0h

Table 6-52. PWRSTAT Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

E000h

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AUX_PWR_DWN

Indicates the AUX powerdown state when AUX domain is powered
up.
0: Active mode
1: AUX Powerdown request has been granted

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

JTAG_PD_ON

Indicates JTAG power state:
0: JTAG is powered off
1: JTAG is powered on

AUX_PD_ON

Indicates AUX power state:
0: AUX is not ready for use ( may be powered off or in power state
transition )
1: AUX is powered on, connected to bus and ready for use,

MCU_PD_ON

Indicates MCU power state:
0: MCU Power sequencing is not yet finalized and MCU_AONIF
registers may not be reliable
1: MCU Power sequencing is finalized and all MCU_AONIF registers
are reliable

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AUX_BUS_CONNECTED

Indicates that AUX Bus is connected:
0: AUX bus is not connected
1: AUX bus is connected ( idle_ack = 0 )

AUX_RESET_DONE

Indicates Reset Done from AUX:
0: AUX is being reset
1: AUX reset is released

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-10
9

8-7

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

481

PRCM Registers

www.ti.com

6.8.2.3.7 SHUTDOWN Register (Offset = 18h) [reset = 0h]
SHUTDOWN is shown in Figure 6-48 and described in Table 6-53.
Return to Summary Table.
Shutdown Control
This register contains bitfields required for entering shutdown mode
Figure 6-48. SHUTDOWN Register
31

24
23
RESERVED
R/W-0h
8
7
RESERVED
R/W-0h

0
EN
R/W0h

Table 6-53. SHUTDOWN Register Field Descriptions
Bit
31-1
0

482

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Writing a 1 to this bit forces a shutdown request to be registered and
all I/O values to be latched - in the PAD ring, possibly enabling I/O
wakeup. Writing 0 will cancel a registered shutdown request and
open th I/O latches residing in the PAD ring.
A registered shutdown request takes effect the next time power
down conditions exists. At this time, the will not enter Powerdown
mode, but instead it will turn off all internal powersupplies, effectively
putting the device into Shutdown mode.

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.3.8 CTL0 Register (Offset = 20h) [reset = 0h]
CTL0 is shown in Figure 6-49 and described in Table 6-54.
Return to Summary Table.
Control 0
This register contains various chip level control and debug bitfields.
Figure 6-49. CTL0 Register
31

8
PWR_DWN_DI
S
R/W-0h

3
AUX_SRAM_E
RASE
W-0h

2
MCU_SRAM_E
RASE
W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

RESERVED
R/W-0h

0
RESERVED
R-0h

Table 6-54. CTL0 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

PWR_DWN_DIS

R/W

Controls whether MCU and AUX requesting to be powered off will
enable a transition to powerdown:
0: Enabled
1: Disabled

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AUX_SRAM_ERASE

Internal. Only to be used through TI provided API.

MCU_SRAM_ERASE

Internal. Only to be used through TI provided API.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-9
8

7-4

1-0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

483

PRCM Registers

www.ti.com

6.8.2.3.9 CTL1 Register (Offset = 24h) [reset = 0h]
CTL1 is shown in Figure 6-50 and described in Table 6-55.
Return to Summary Table.
Control 1
This register contains various chip level control and debug bitfields.
Figure 6-50. CTL1 Register
31

1
MCU_RESET_
SRC
R/W1C-0h

0
MCU_WARM_
RESET
R/W1C-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 6-55. CTL1 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MCU_RESET_SRC

R/W1C

Indicates source of last MCU Voltage Domain warm reset request:
0: MCU SW reset
1: JTAG reset
This bit can only be cleared by writing a 1 to it

MCU_WARM_RESET

R/W1C

Indicates type of last MCU Voltage Domain reset:
0: Last MCU reset was not a warm reset
1: Last MCU reset was a warm reset (requested from MCU or JTAG
as indicated in MCU_RESET_SRC)
This bit can only be cleared by writing a 1 to it

31-2

484

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.3.10 RECHARGECFG Register (Offset = 30h) [reset = 0h]
RECHARGECFG is shown in Figure 6-51 and described in Table 6-56.
Return to Summary Table.
Recharge Controller Configuration
This register sets all relevant patameters for controlling the recharge algorithm.
Figure 6-51. RECHARGECFG Register
31
ADAPTIVE_EN
R/W-0h

27
RESERVED
R-0h

C2
R/W-0h

C1
R/W-0h

13
MAX_PER_M
R/W-0h

9
MAX_PER_E
R/W-0h

5
PER_M
R/W-0h

1
PER_E
R/W-0h

Table 6-56. RECHARGECFG Register Field Descriptions
Bit

Field

Type

Reset

Description

ADAPTIVE_EN

R/W

Enable adaptive recharge
Note: Recharge can be turned completely of by setting
MAX_PER_E=7 and MAX_PER_M=31 and this bitfield to 0

30-24

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-20

R/W

Gain factor for adaptive recharge algorithm
period_new=period * ( 1+/-(2-C1+2-C2) )
Valid values for C2 is 2 to 10
Note: Rounding may cause adaptive recharge not to start for very
small values of both Gain and Initial period. Criteria for algorithm to
start is MAX(PERIOD*2-C1,PERIOD*2-C2) >= 1

19-16

R/W

Gain factor for adaptive recharge algorithm
period_new=period * ( 1+/-(2-C1+2-C2) )
Valid values for C1 is 1 to 10
Note: Rounding may cause adaptive recharge not to start for very
small values of both Gain and Initial period. Criteria for algorithm to
start is MAX(PERIOD*2-C1,PERIOD*2-C2) >= 1

15-11

MAX_PER_M

R/W

This register defines the maximum period that the recharge
algorithm can take, i.e. it defines the maximum number of cycles
between 2 recharges.
The maximum number of cycles is specified with a 5 bit mantissa
and 3 bit exponent:
MAXCYCLES=(MAX_PER_M*16+15)*2MAX_PER_E
This field sets the mantissa of MAXCYCLES

10-8

MAX_PER_E

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

485

PRCM Registers

www.ti.com

Table 6-56. RECHARGECFG Register Field Descriptions (continued)

486

Bit

Field

Type

Reset

Description

7-3

PER_M

R/W

Number of 32 KHz clocks between activation of recharge controller
For recharge algorithm, PERIOD is the initial period when entering
powerdown mode. The adaptive recharge algorithm will not change
this register
PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa
and 3 bit exponent:
This field sets the Mantissa of the Period.
PERIOD=(PER_M*16+15)*2PER_E

2-0

PER_E

R/W

Number of 32 KHz clocks between activation of recharge controller
For recharge algorithm, PERIOD is the initial period when entering
powerdown mode. The adaptive recharge algorithm will not change
this register
PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa
and 3 bit exponent:
This field sets the Exponent of the Period.
PERIOD=(PER_M*16+15)*2PER_E

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.3.11 RECHARGESTAT Register (Offset = 34h) [reset = 0h]
RECHARGESTAT is shown in Figure 6-52 and described in Table 6-57.
Return to Summary Table.
Recharge Controller Status
This register controls various status registers which are updated during recharge. The register is mostly
intended for test and debug.
Figure 6-52. RECHARGESTAT Register
31

26
25
RESERVED
R-0h

8
7
MAX_USED_PER
R/W-0h

18
17
VDDR_SMPLS
R-0h
2

Table 6-57. RECHARGESTAT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-20

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

19-16

VDDR_SMPLS

The last 4 VDDR samples, bit 0 being the newest.
The register is being updated in every recharge period with a shift
left, and bit 0 is updated with the last VDDR sample, ie a 1 is shiftet
in in case VDDR > VDDR_threshold just before recharge starts.
Otherwise a 0 will be shifted in.

15-0

MAX_USED_PER

R/W

The maximum value of recharge period seen with VDDR>threshold.
The VDDR voltage is compared against the threshold voltage at just
before each recharge. If VDDR is above threshold,
MAX_USED_PER is updated with max ( current recharge peride
MAX_USED_PER ) This way MAX_USED_PER can track the
recharge period where VDDR is decharged to the threshold value.
We can therefore use the value as an indication of the leakage
current during recharge.
This bitfield is cleared to 0 when writing this register.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

487

PRCM Registers

www.ti.com

6.8.2.3.12 OSCCFG Register (Offset = 38h) [reset = 0h]
OSCCFG is shown in Figure 6-53 and described in Table 6-58.
Return to Summary Table.
Oscillator Configuration
This register sets the period for Amplitude compensation requests sent to the oscillator control system.
The amplitude compensations is only applicable when XOSC_HF is running in low power mode.
Figure 6-53. OSCCFG Register
31

12
11
RESERVED
R-0h

24
23
RESERVED
R-0h
8

5
PER_M
R/W-0h

1
PER_E
R/W-0h

Table 6-58. OSCCFG Register Field Descriptions
Bit

488

Field

Type

Reset

Description

31-8

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-3

PER_M

R/W

Number of 32 KHz clocks between oscillator amplitude calibrations.
When this counter expires, an oscillator amplitude compensation is
triggered immediately in Active mode. When this counter expires in
Powerdown mode an internal flag is set such that the amplitude
compensation is postponed until the next recharge occurs.
The Period will effectively be a 16 bit value coded in a 5 bit mantissa
and 3 bit exponent
PERIOD=(PER_M*16+15)*2PER_E
This field sets the mantissa
Note: Oscillator amplitude calibration is turned of when both this
bitfield and PER_E are set to 0

2-0

PER_E

R/W

Number of 32 KHz clocks between oscillator amplitude calibrations.
When this counter expires, an oscillator amplitude compensation is
triggered immediately in Active mode. When this counter expires in
Powerdown mode an internal flag is set such that the amplitude
compensation is postponed until the next recharge occurs.
The Period will effectively be a 16 bit value coded in a 5 bit mantissa
and 3 bit exponent
PERIOD=(PER_M*16+15)*2PER_E
This field sets the exponent
Note: Oscillator amplitude calibration is turned of when both PER_M
and this bitfield are set to 0

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.3.13 JTAGCFG Register (Offset = 40h) [reset = 100h]
JTAGCFG is shown in Figure 6-54 and described in Table 6-59.
Return to Summary Table.
JTAG Configuration
This register contains control for configuration of the JTAG domain,- hereunder access permissions for
each TAP.
Figure 6-54. JTAGCFG Register
31

8
JTAG_PD_FO
RCE_ON
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R/W-0h

Table 6-59. JTAGCFG Register Field Descriptions
Bit
31-9
8

7-0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

JTAG_PD_FORCE_ON

R/W

Controls JTAG PowerDomain power state:
0: Controlled exclusively by debug subsystem. (JTAG Powerdomain
will be powered off unless a debugger is attached)
1: JTAG Power Domain is forced on, independent of debug
subsystem.
NB: The reset value causes JTAG Power Domain to be powered on
by default. Software must clear this bit to turn off the JTAG Power
Domain

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

489

PRCM Registers

www.ti.com

6.8.2.3.14 JTAGUSERCODE Register (Offset = 44h) [reset = 0B99A02Fh]
JTAGUSERCODE is shown in Figure 6-55 and described in Table 6-60.
Return to Summary Table.
JTAG USERCODE
Boot code copies the JTAG USERCODE to this register from where it is forwarded to the debug
subsystem.
Figure 6-55. JTAGUSERCODE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
USER_CODE
R/W-0B99A02Fh

Table 6-60. JTAGUSERCODE Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

USER_CODE

R/W

0B99A02Fh

32-bit JTAG USERCODE register feeding main JTAG TAP
NB: This field can be locked

6.8.2.4 PRCM Registers
Table 6-61 lists the memory-mapped registers for the PRCM. All register offset addresses not listed in
Table 6-61 should be considered as reserved locations and the register contents should not be modified.
Table 6-61. PRCM Registers
Offset

490

Acronym

Section

INFRCLKDIVR

Infrastructure Clock Division Factor For Run Mode

Section 6.8.2.4.1

INFRCLKDIVS

Infrastructure Clock Division Factor For Sleep Mode

Section 6.8.2.4.2

INFRCLKDIVDS

Infrastructure Clock Division Factor For DeepSleep
Mode

Section 6.8.2.4.3

VDCTL

MCU Voltage Domain Control

Section 6.8.2.4.4

28h

CLKLOADCTL

Load PRCM Settings To CLKCTRL Power Domain

Section 6.8.2.4.5

2Ch

RFCCLKG

RFC Clock Gate

Section 6.8.2.4.6

30h

VIMSCLKG

VIMS Clock Gate

Section 6.8.2.4.7

3Ch

SECDMACLKGR

TRNG, CRYPTO And UDMA Clock Gate For Run Mode

Section 6.8.2.4.8

40h

SECDMACLKGS

TRNG, CRYPTO And UDMA Clock Gate For Sleep
Mode

Section 6.8.2.4.9

44h

SECDMACLKGDS

TRNG, CRYPTO And UDMA Clock Gate For Deep
Sleep Mode

Section 6.8.2.4.10

48h

GPIOCLKGR

GPIO Clock Gate For Run Mode

Section 6.8.2.4.11

4Ch

GPIOCLKGS

GPIO Clock Gate For Sleep Mode

Section 6.8.2.4.12

50h

GPIOCLKGDS

GPIO Clock Gate For Deep Sleep Mode

Section 6.8.2.4.13

54h

GPTCLKGR

GPT Clock Gate For Run Mode

Section 6.8.2.4.14

58h

GPTCLKGS

GPT Clock Gate For Sleep Mode

Section 6.8.2.4.15

5Ch

GPTCLKGDS

GPT Clock Gate For Deep Sleep Mode

Section 6.8.2.4.16

60h

I2CCLKGR

I2C Clock Gate For Run Mode

Section 6.8.2.4.17

64h

I2CCLKGS

I2C Clock Gate For Sleep Mode

Section 6.8.2.4.18

68h

I2CCLKGDS

I2C Clock Gate For Deep Sleep Mode

Section 6.8.2.4.19

6Ch

UARTCLKGR

UART Clock Gate For Run Mode

Section 6.8.2.4.20

70h

UARTCLKGS

UART Clock Gate For Sleep Mode

Section 6.8.2.4.21

74h

UARTCLKGDS

UART Clock Gate For Deep Sleep Mode

Section 6.8.2.4.22

78h

SSICLKGR

SSI Clock Gate For Run Mode

Section 6.8.2.4.23

7Ch

SSICLKGS

SSI Clock Gate For Sleep Mode

Section 6.8.2.4.24

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

Table 6-61. PRCM Registers (continued)
Offset

Acronym

80h

SSICLKGDS

SSI Clock Gate For Deep Sleep Mode

Section 6.8.2.4.25

Section

84h

I2SCLKGR

I2S Clock Gate For Run Mode

Section 6.8.2.4.26

88h

I2SCLKGS

I2S Clock Gate For Sleep Mode

Section 6.8.2.4.27

8Ch

I2SCLKGDS

I2S Clock Gate For Deep Sleep Mode

Section 6.8.2.4.28

B8h

CPUCLKDIV

Internal

Section 6.8.2.4.29

C8h

I2SBCLKSEL

I2S Clock Control

Section 6.8.2.4.30

CCh

GPTCLKDIV

GPT Scalar

Section 6.8.2.4.31

D0h

I2SCLKCTL

I2S Clock Control

Section 6.8.2.4.32

D4h

I2SMCLKDIV

MCLK Division Ratio

Section 6.8.2.4.33

D8h

I2SBCLKDIV

BCLK Division Ratio

Section 6.8.2.4.34

DCh

I2SWCLKDIV

WCLK Division Ratio

Section 6.8.2.4.35

10Ch

SWRESET

SW Initiated Resets

Section 6.8.2.4.36

110h

WARMRESET

WARM Reset Control And Status

Section 6.8.2.4.37

12Ch

PDCTL0

Power Domain Control

Section 6.8.2.4.38

130h

PDCTL0RFC

RFC Power Domain Control

Section 6.8.2.4.39

134h

PDCTL0SERIAL

SERIAL Power Domain Control

Section 6.8.2.4.40

138h

PDCTL0PERIPH

PERIPH Power Domain Control

Section 6.8.2.4.41

140h

PDSTAT0

Power Domain Status

Section 6.8.2.4.42

144h

PDSTAT0RFC

RFC Power Domain Status

Section 6.8.2.4.43

148h

PDSTAT0SERIAL

SERIAL Power Domain Status

Section 6.8.2.4.44

14Ch

PDSTAT0PERIPH

PERIPH Power Domain Status

Section 6.8.2.4.45

17Ch

PDCTL1

Power Domain Control

Section 6.8.2.4.46

184h

PDCTL1CPU

CPU Power Domain Direct Control

Section 6.8.2.4.47

188h

PDCTL1RFC

RFC Power Domain Direct Control

Section 6.8.2.4.48

18Ch

PDCTL1VIMS

VIMS Mode Direct Control

Section 6.8.2.4.49

194h

PDSTAT1

Power Manager Status

Section 6.8.2.4.50

198h

PDSTAT1BUS

BUS Power Domain Direct Read Status

Section 6.8.2.4.51

19Ch

PDSTAT1RFC

RFC Power Domain Direct Read Status

Section 6.8.2.4.52

1A0h

PDSTAT1CPU

CPU Power Domain Direct Read Status

Section 6.8.2.4.53

1A4h

PDSTAT1VIMS

VIMS Mode Direct Read Status

Section 6.8.2.4.54

1CCh

RFCBITS

Control To RFC

Section 6.8.2.4.55

1D0h

RFCMODESEL

Selected RFC Mode

Section 6.8.2.4.56

1D4h

RFCMODEHWOPT

Allowed RFC Modes

Section 6.8.2.4.57

1E0h

PWRPROFSTAT

Power Profiler Register

Section 6.8.2.4.58

224h

RAMRETEN

Memory Retention Control

Section 6.8.2.4.59

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

491

PRCM Registers

www.ti.com

6.8.2.4.1 INFRCLKDIVR Register (Offset = 0h) [reset = 0h]
INFRCLKDIVR is shown in Figure 6-56 and described in Table 6-62.
Return to Summary Table.
Infrastructure Clock Division Factor For Run Mode
Figure 6-56. INFRCLKDIVR Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

RATIO
R/W-0h

Table 6-62. INFRCLKDIVR Register Field Descriptions
Bit

492

Field

Type

Reset

Description

31-2

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

RATIO

R/W

Division rate for clocks driving modules in the MCU_AON domain
when system CPU is in run mode. Division ratio affects both
infrastructure clock and perbusull clock.
0h = Divide by 1
1h = Divide by 2
2h = Divide by 8
3h = Divide by 32

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.2 INFRCLKDIVS Register (Offset = 4h) [reset = 0h]
INFRCLKDIVS is shown in Figure 6-57 and described in Table 6-63.
Return to Summary Table.
Infrastructure Clock Division Factor For Sleep Mode
Figure 6-57. INFRCLKDIVS Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

RATIO
R/W-0h

Table 6-63. INFRCLKDIVS Register Field Descriptions
Field

Type

Reset

Description

31-2

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

RATIO

R/W

Division rate for clocks driving modules in the MCU_AON domain
when system CPU is in sleep mode. Division ratio affects both
infrastructure clock and perbusull clock.
0h = Divide by 1
1h = Divide by 2
2h = Divide by 8
3h = Divide by 32

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

493

PRCM Registers

www.ti.com

6.8.2.4.3 INFRCLKDIVDS Register (Offset = 8h) [reset = 0h]
INFRCLKDIVDS is shown in Figure 6-58 and described in Table 6-64.
Return to Summary Table.
Infrastructure Clock Division Factor For DeepSleep Mode
Figure 6-58. INFRCLKDIVDS Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

RATIO
R/W-0h

Table 6-64. INFRCLKDIVDS Register Field Descriptions
Bit

494

Field

Type

Reset

Description

31-2

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

RATIO

R/W

Division rate for clocks driving modules in the MCU_AON domain
when system CPU is in seepsleep mode. Division ratio affects both
infrastructure clock and perbusull clock.
0h = Divide by 1
1h = Divide by 2
2h = Divide by 8
3h = Divide by 32

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.4 VDCTL Register (Offset = Ch) [reset = 0h]
VDCTL is shown in Figure 6-59 and described in Table 6-65.
Return to Summary Table.
MCU Voltage Domain Control
Figure 6-59. VDCTL Register
31

2
MCU_VD
R/W-0h

1
RESERVED
R/W-0h

0
ULDO
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

5
RESERVED
R/W-0h

Table 6-65. VDCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MCU_VD

R/W

Request WUC to power down the MCU voltage domain
0: No request
1: Assert request when possible. An asserted power down request
will result in a boot of the MCU system when powered up again.
The bit will have no effect before the following requirements are met:
1. PDCTL1.CPU_ON = 0
2. PDCTL1.VIMS_MODE = 0
3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be
loaded with CLKLOADCTL.LOAD)
4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be
loaded with CLKLOADCTL.LOAD)
5. RFC do no request access to BUS
6. System CPU in deepsleep

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ULDO

R/W

Request WUC to switch to uLDO.
0: No request
1: Assert request when possible
The bit will have no effect before the following requirements are met:
1. PDCTL1.CPU_ON = 0
2. PDCTL1.VIMS_MODE = 0
3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be
loaded with CLKLOADCTL.LOAD)
4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be
loaded with CLKLOADCTL.LOAD)
5. RFC do no request access to BUS
6. System CPU in deepsleep

31-3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

495

PRCM Registers

www.ti.com

6.8.2.4.5 CLKLOADCTL Register (Offset = 28h) [reset = 2h]
CLKLOADCTL is shown in Figure 6-60 and described in Table 6-66.
Return to Summary Table.
Load PRCM Settings To CLKCTRL Power Domain
Figure 6-60. CLKLOADCTL Register
31

1
LOAD_DONE
R-1h

0
LOAD
W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 6-66. CLKLOADCTL Register Field Descriptions
Bit
31-2
1

496

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

LOAD_DONE

Status of LOAD.
Will be cleared to 0 when any of the registers requiring a LOAD is
written to, and be set to 1 when a LOAD is done.
Note that writing no change to a register will result in the
LOAD_DONE being cleared.
0 : One or more registers have been write accessed after last LOAD
1 : No registers are write accessed after last LOAD

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

Table 6-66. CLKLOADCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

LOAD

0: No action
1: Load settings to CLKCTRL. Bit is HW cleared.
Multiple changes to settings may be done before LOAD is written
once so all changes takes place at the same time. LOAD can also
be done after single setting updates.
Registers that needs to be followed by LOAD before settings being
applied are:
- RFCCLKG
- VIMSCLKG
- SECDMACLKGR
- SECDMACLKGS
- SECDMACLKGDS
- GPIOCLKGR
- GPIOCLKGS
- GPIOCLKGDS
- GPTCLKGR
- GPTCLKGS
- GPTCLKGDS
- GPTCLKDIV
- I2CCLKGR
- I2CCLKGS
- I2CCLKGDS
- SSICLKGR
- SSICLKGS
- SSICLKGDS
- UARTCLKGR
- UARTCLKGS
- UARTCLKGDS
- I2SCLKGR
- I2SCLKGS
- I2SCLKGDS
- I2SBCLKSEL
- I2SCLKCTL
- I2SMCLKDIV
- I2SBCLKDIV
- I2SWCLKDIV

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

497

PRCM Registers

www.ti.com

6.8.2.4.6 RFCCLKG Register (Offset = 2Ch) [reset = 1h]
RFCCLKG is shown in Figure 6-61 and described in Table 6-67.
Return to Summary Table.
RFC Clock Gate
Figure 6-61. RFCCLKG Register
31

0
CLK_EN
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 6-67. RFCCLKG Register Field Descriptions
Bit
31-1
0

498

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock if RFC power domain is on
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.7 VIMSCLKG Register (Offset = 30h) [reset = 3h]
VIMSCLKG is shown in Figure 6-62 and described in Table 6-68.
Return to Summary Table.
VIMS Clock Gate
Figure 6-62. VIMSCLKG Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
0
CLK_EN
R/W-3h

Table 6-68. VIMSCLKG Register Field Descriptions
Field

Type

Reset

Description

31-2

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

CLK_EN

R/W

00: Disable clock
01: Disable clock when SYSBUS clock is disabled
11: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

499

PRCM Registers

www.ti.com

6.8.2.4.8 SECDMACLKGR Register (Offset = 3Ch) [reset = 0h]
SECDMACLKGR is shown in Figure 6-63 and described in Table 6-69.
Return to Summary Table.
TRNG, CRYPTO And UDMA Clock Gate For Run Mode
Figure 6-63. SECDMACLKGR Register
31

12
RESERVED
R-0h

8
DMA_CLK_EN
R/W-0h

1
TRNG_CLK_E
N
R/W-0h

0
CRYPTO_CLK
_EN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

5
RESERVED
R-0h

Table 6-69. SECDMACLKGR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMA_CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TRNG_CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

CRYPTO_CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

31-9
8

7-2

500

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.9 SECDMACLKGS Register (Offset = 40h) [reset = 0h]
SECDMACLKGS is shown in Figure 6-64 and described in Table 6-70.
Return to Summary Table.
TRNG, CRYPTO And UDMA Clock Gate For Sleep Mode
Figure 6-64. SECDMACLKGS Register
31

12
RESERVED
R-0h

8
DMA_CLK_EN
R/W-0h

1
TRNG_CLK_E
N
R/W-0h

0
CRYPTO_CLK
_EN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

5
RESERVED
R-0h

Table 6-70. SECDMACLKGS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMA_CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TRNG_CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

CRYPTO_CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

31-9
8

7-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

501

PRCM Registers

www.ti.com

6.8.2.4.10 SECDMACLKGDS Register (Offset = 44h) [reset = 0h]
SECDMACLKGDS is shown in Figure 6-65 and described in Table 6-71.
Return to Summary Table.
TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode
Figure 6-65. SECDMACLKGDS Register
31

12
RESERVED
R-0h

8
DMA_CLK_EN
R/W-0h

1
TRNG_CLK_E
N
R/W-0h

0
CRYPTO_CLK
_EN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

5
RESERVED
R-0h

Table 6-71. SECDMACLKGDS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMA_CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TRNG_CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

CRYPTO_CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

31-9
8

7-2

502

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.11 GPIOCLKGR Register (Offset = 48h) [reset = 0h]
GPIOCLKGR is shown in Figure 6-66 and described in Table 6-72.
Return to Summary Table.
GPIO Clock Gate For Run Mode
Figure 6-66. GPIOCLKGR Register
31

0
CLK_EN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 6-72. GPIOCLKGR Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

503

PRCM Registers

www.ti.com

6.8.2.4.12 GPIOCLKGS Register (Offset = 4Ch) [reset = 0h]
GPIOCLKGS is shown in Figure 6-67 and described in Table 6-73.
Return to Summary Table.
GPIO Clock Gate For Sleep Mode
Figure 6-67. GPIOCLKGS Register
31

0
CLK_EN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 6-73. GPIOCLKGS Register Field Descriptions
Bit
31-1
0

504

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.13 GPIOCLKGDS Register (Offset = 50h) [reset = 0h]
GPIOCLKGDS is shown in Figure 6-68 and described in Table 6-74.
Return to Summary Table.
GPIO Clock Gate For Deep Sleep Mode
Figure 6-68. GPIOCLKGDS Register
31

0
CLK_EN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 6-74. GPIOCLKGDS Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

505

PRCM Registers

www.ti.com

6.8.2.4.14 GPTCLKGR Register (Offset = 54h) [reset = 0h]
GPTCLKGR is shown in Figure 6-69 and described in Table 6-75.
Return to Summary Table.
GPT Clock Gate For Run Mode
Figure 6-69. GPTCLKGR Register
31

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

2
1
CLK_EN
R/W-0h

Table 6-75. GPTCLKGR Register Field Descriptions
Bit

506

Field

Type

Reset

Description

31-4

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

CLK_EN

R/W

Each bit below has the following meaning:
0: Disable clock
1: Enable clock
ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for GPT0
2h = Enable clock for GPT1
4h = Enable clock for GPT2
8h = Enable clock for GPT3

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.15 GPTCLKGS Register (Offset = 58h) [reset = 0h]
GPTCLKGS is shown in Figure 6-70 and described in Table 6-76.
Return to Summary Table.
GPT Clock Gate For Sleep Mode
Figure 6-70. GPTCLKGS Register
31

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

2
1
CLK_EN
R/W-0h

Table 6-76. GPTCLKGS Register Field Descriptions
Field

Type

Reset

Description

31-4

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

CLK_EN

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

507

PRCM Registers

www.ti.com

6.8.2.4.16 GPTCLKGDS Register (Offset = 5Ch) [reset = 0h]
GPTCLKGDS is shown in Figure 6-71 and described in Table 6-77.
Return to Summary Table.
GPT Clock Gate For Deep Sleep Mode
Figure 6-71. GPTCLKGDS Register
31

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

2
1
CLK_EN
R/W-0h

Table 6-77. GPTCLKGDS Register Field Descriptions
Bit

508

Field

Type

Reset

Description

31-4

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

CLK_EN

R/W

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.17 I2CCLKGR Register (Offset = 60h) [reset = 0h]
I2CCLKGR is shown in Figure 6-72 and described in Table 6-78.
Return to Summary Table.
I2C Clock Gate For Run Mode
Figure 6-72. I2CCLKGR Register
31

0
CLK_EN
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 6-78. I2CCLKGR Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

509

PRCM Registers

www.ti.com

6.8.2.4.18 I2CCLKGS Register (Offset = 64h) [reset = 0h]
I2CCLKGS is shown in Figure 6-73 and described in Table 6-79.
Return to Summary Table.
I2C Clock Gate For Sleep Mode
Figure 6-73. I2CCLKGS Register
31

0
CLK_EN
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 6-79. I2CCLKGS Register Field Descriptions
Bit
31-1
0

510

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.19 I2CCLKGDS Register (Offset = 68h) [reset = 0h]
I2CCLKGDS is shown in Figure 6-74 and described in Table 6-80.
Return to Summary Table.
I2C Clock Gate For Deep Sleep Mode
Figure 6-74. I2CCLKGDS Register
31

0
CLK_EN
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 6-80. I2CCLKGDS Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

511

PRCM Registers

www.ti.com

6.8.2.4.20 UARTCLKGR Register (Offset = 6Ch) [reset = 0h]
UARTCLKGR is shown in Figure 6-75 and described in Table 6-81.
Return to Summary Table.
UART Clock Gate For Run Mode
Figure 6-75. UARTCLKGR Register
31

0
CLK_EN
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 6-81. UARTCLKGR Register Field Descriptions
Bit
31-1
0

512

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.21 UARTCLKGS Register (Offset = 70h) [reset = 0h]
UARTCLKGS is shown in Figure 6-76 and described in Table 6-82.
Return to Summary Table.
UART Clock Gate For Sleep Mode
Figure 6-76. UARTCLKGS Register
31

0
CLK_EN
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 6-82. UARTCLKGS Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

513

PRCM Registers

www.ti.com

6.8.2.4.22 UARTCLKGDS Register (Offset = 74h) [reset = 0h]
UARTCLKGDS is shown in Figure 6-77 and described in Table 6-83.
Return to Summary Table.
UART Clock Gate For Deep Sleep Mode
Figure 6-77. UARTCLKGDS Register
31

0
CLK_EN
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 6-83. UARTCLKGDS Register Field Descriptions
Bit
31-1
0

514

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.23 SSICLKGR Register (Offset = 78h) [reset = 0h]
SSICLKGR is shown in Figure 6-78 and described in Table 6-84.
Return to Summary Table.
SSI Clock Gate For Run Mode
Figure 6-78. SSICLKGR Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
0
CLK_EN
R/W-0h

Table 6-84. SSICLKGR Register Field Descriptions
Field

Type

Reset

Description

31-2

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for SSI0
2h = Enable clock for SSI1

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

515

PRCM Registers

www.ti.com

6.8.2.4.24 SSICLKGS Register (Offset = 7Ch) [reset = 0h]
SSICLKGS is shown in Figure 6-79 and described in Table 6-85.
Return to Summary Table.
SSI Clock Gate For Sleep Mode
Figure 6-79. SSICLKGS Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
0
CLK_EN
R/W-0h

Table 6-85. SSICLKGS Register Field Descriptions
Bit

516

Field

Type

Reset

Description

31-2

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for SSI0
2h = Enable clock for SSI1

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.25 SSICLKGDS Register (Offset = 80h) [reset = 0h]
SSICLKGDS is shown in Figure 6-80 and described in Table 6-86.
Return to Summary Table.
SSI Clock Gate For Deep Sleep Mode
Figure 6-80. SSICLKGDS Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
0
CLK_EN
R/W-0h

Table 6-86. SSICLKGDS Register Field Descriptions
Field

Type

Reset

Description

31-2

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for SSI0
2h = Enable clock for SSI1

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

517

PRCM Registers

www.ti.com

6.8.2.4.26 I2SCLKGR Register (Offset = 84h) [reset = 0h]
I2SCLKGR is shown in Figure 6-81 and described in Table 6-87.
Return to Summary Table.
I2S Clock Gate For Run Mode
Figure 6-81. I2SCLKGR Register
31

0
CLK_EN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 6-87. I2SCLKGR Register Field Descriptions
Bit
31-1
0

518

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.27 I2SCLKGS Register (Offset = 88h) [reset = 0h]
I2SCLKGS is shown in Figure 6-82 and described in Table 6-88.
Return to Summary Table.
I2S Clock Gate For Sleep Mode
Figure 6-82. I2SCLKGS Register
31

0
CLK_EN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 6-88. I2SCLKGS Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

519

PRCM Registers

www.ti.com

6.8.2.4.28 I2SCLKGDS Register (Offset = 8Ch) [reset = 0h]
I2SCLKGDS is shown in Figure 6-83 and described in Table 6-89.
Return to Summary Table.
I2S Clock Gate For Deep Sleep Mode
Figure 6-83. I2SCLKGDS Register
31

0
CLK_EN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 6-89. I2SCLKGDS Register Field Descriptions
Bit
31-1
0

520

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CLK_EN

R/W

0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.29 CPUCLKDIV Register (Offset = B8h) [reset = 0h]
CPUCLKDIV is shown in Figure 6-84 and described in Table 6-90.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 6-84. CPUCLKDIV Register
31

0
RATIO
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 6-90. CPUCLKDIV Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

RATIO

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

521

PRCM Registers

www.ti.com

6.8.2.4.30 I2SBCLKSEL Register (Offset = C8h) [reset = 0h]
I2SBCLKSEL is shown in Figure 6-85 and described in Table 6-91.
Return to Summary Table.
I2S Clock Control
Figure 6-85. I2SBCLKSEL Register
31

24
23
SPARE
R/W-0h
8
SPARE
R/W-0h

0
SRC
R/W0h

Table 6-91. I2SBCLKSEL Register Field Descriptions
Bit
31-1
0

522

Field

Type

Reset

Description

SPARE

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SRC

R/W

BCLK source selector
0: Use external BCLK
1: Use internally generated clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.31 GPTCLKDIV Register (Offset = CCh) [reset = 0h]
GPTCLKDIV is shown in Figure 6-86 and described in Table 6-92.
Return to Summary Table.
GPT Scalar
Figure 6-86. GPTCLKDIV Register
31

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

RATIO
R/W-0h

Table 6-92. GPTCLKDIV Register Field Descriptions
Field

Type

Reset

Description

31-4

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

RATIO

R/W

Scalar used for GPTs. The division rate will be constant and ungated
for Run / Sleep / DeepSleep mode.
For changes to take effect, CLKLOADCTL.LOAD needs to be written
Other values are not supported.
0h = Divide by 1
1h = Divide by 2
2h = Divide by 4
3h = Divide by 8
4h = Divide by 16
5h = Divide by 32
6h = Divide by 64
7h = Divide by 128
8h = Divide by 256

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

523

PRCM Registers

www.ti.com

6.8.2.4.32 I2SCLKCTL Register (Offset = D0h) [reset = 0h]
I2SCLKCTL is shown in Figure 6-87 and described in Table 6-93.
Return to Summary Table.
I2S Clock Control
Figure 6-87. I2SCLKCTL Register
31

3
SMPL_ON_PO
SEDGE
R/W-0h

1
WCLK_PHASE

0
EN

R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

RESERVED
R-0h

Table 6-93. I2SCLKCTL Register Field Descriptions
Bit
31-4
3

2-1

524

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SMPL_ON_POSEDGE

R/W

On the I2S serial interface, data and WCLK is sampled and clocked
out on opposite edges of BCLK.
0 - data and WCLK are sampled on the negative edge and clocked
out on the positive edge.
1 - data and WCLK are sampled on the positive edge and clocked
out on the negative edge.
For changes to take effect, CLKLOADCTL.LOAD needs to be written

WCLK_PHASE

R/W

Decides how the WCLK division ratio is calculated and used to
generate different duty cycles (See I2SWCLKDIV.WDIV).
0: Single phase
1: Dual phase
2: User Defined
3: Reserved/Undefined
For changes to take effect, CLKLOADCTL.LOAD needs to be written

R/W

0: MCLK, BCLK and **WCLK** will be static low
1: Enables the generation of MCLK, BCLK and WCLK
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.33 I2SMCLKDIV Register (Offset = D4h) [reset = 0h]
I2SMCLKDIV is shown in Figure 6-88 and described in Table 6-94.
Return to Summary Table.
MCLK Division Ratio
Figure 6-88. I2SMCLKDIV Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

5 4 3
MDIV
R/W-0h

Table 6-94. I2SMCLKDIV Register Field Descriptions
Bit
31-10
9-0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MDIV

R/W

An unsigned factor of the division ratio used to generate MCLK [21024]:
MCLK = MCUCLK/MDIV[Hz]
MCUCLK is 48MHz in normal mode. For powerdown mode the
frequency is defined by AON_WUC:MCUCLK.PWR_DWN_SRC
A value of 0 is interpreted as 1024.
A value of 1 is invalid.
If MDIV is odd the low phase of the clock is one MCUCLK period
longer than the high phase.
For changes to take effect, CLKLOADCTL.LOAD needs to be written

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

525

PRCM Registers

www.ti.com

6.8.2.4.34 I2SBCLKDIV Register (Offset = D8h) [reset = 0h]
I2SBCLKDIV is shown in Figure 6-89 and described in Table 6-95.
Return to Summary Table.
BCLK Division Ratio
Figure 6-89. I2SBCLKDIV Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

5 4 3
BDIV
R/W-0h

Table 6-95. I2SBCLKDIV Register Field Descriptions
Bit
31-10
9-0

526

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BDIV

R/W

An unsigned factor of the division ratio used to generate I2S BCLK
[2-1024]:
BCLK = MCUCLK/BDIV[Hz]
MCUCLK is 48MHz in normal mode. For powerdown mode the
frequency is defined by AON_WUC:MCUCLK.PWR_DWN_SRC
A value of 0 is interpreted as 1024.
A value of 1 is invalid.
If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low
phase of the clock is one MCUCLK period longer than the high
phase.
If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high
phase of the clock is one MCUCLK period longer than the low
phase.
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.35 I2SWCLKDIV Register (Offset = DCh) [reset = 0h]
I2SWCLKDIV is shown in Figure 6-90 and described in Table 6-96.
Return to Summary Table.
WCLK Division Ratio
Figure 6-90. I2SWCLKDIV Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
WDIV
R/W-0h

Table 6-96. I2SWCLKDIV Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

WDIV

R/W

If I2SCLKCTL.WCLK_PHASE = 0, Single phase.
WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [11023]) BCLK periods.
WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz]
MCUCLK is 48MHz in normal mode. For powerdown mode the
frequency is defined by AON_WUC:MCUCLK.PWR_DWN_SRC
If I2SCLKCTL.WCLK_PHASE = 1, Dual phase.
Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [11023]) BCLK periods.
WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz]
If I2SCLKCTL.WCLK_PHASE = 2, User defined.
WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low
WDIV[15:8] (unsigned, [1-255]) BCLK periods.
WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz]
For changes to take effect, CLKLOADCTL.LOAD needs to be written

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

527

PRCM Registers

www.ti.com

6.8.2.4.36 SWRESET Register (Offset = 10Ch) [reset = 0h]
SWRESET is shown in Figure 6-91 and described in Table 6-97.
Return to Summary Table.
SW Initiated Resets
Figure 6-91. SWRESET Register
31

2
MCU
W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

0
RESERVED
W-0h

Table 6-97. SWRESET Register Field Descriptions
Bit
31-3
2
1-0

528

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MCU

Internal. Only to be used through TI provided API.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.37 WARMRESET Register (Offset = 110h) [reset = 0h]
WARMRESET is shown in Figure 6-92 and described in Table 6-98.
Return to Summary Table.
WARM Reset Control And Status
Figure 6-92. WARMRESET Register
31

2
WR_TO_PINR
ESET
R/W-0h

1
LOCKUP_STA
T
R-0h

0
WDT_STAT

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED

R-0h

Table 6-98. WARMRESET Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

WR_TO_PINRESET

R/W

0: No action
1: A warm system reset event triggered by the below listed sources
will result in an emulated pin reset.
Warm reset sources included:
ICEPick sysreset
System CPU reset request, CPU_SCS:AIRCR.SYSRESETREQ
System CPU Lockup
WDT timeout
An active ICEPick block system reset will gate all sources except
ICEPick sysreset
SW can read AON_SYSCTL:RESETCTL.RESET_SRC to find the
source of the last reset resulting in a full power up sequence.
WARMRESET in this register is set in the scenario that
WR_TO_PINRESET=1 and one of the above listed sources is
triggered.

LOCKUP_STAT

0: No registred event
1: A system CPU LOCKUP event has occured since last SW clear of
the register.
A read of this register clears both WDT_STAT and LOCKUP_STAT.

WDT_STAT

0: No registered event
1: A WDT event has occured since last SW clear of the register.
A read of this register clears both WDT_STAT and LOCKUP_STAT.

31-3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

529

PRCM Registers

www.ti.com

6.8.2.4.38 PDCTL0 Register (Offset = 12Ch) [reset = 0h]
PDCTL0 is shown in Figure 6-93 and described in Table 6-99.
Return to Summary Table.
Power Domain Control
Figure 6-93. PDCTL0 Register
31

2
PERIPH_ON
R/W-0h

1
SERIAL_ON
R/W-0h

0
RFC_ON
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

Table 6-99. PDCTL0 Register Field Descriptions
Bit

530

Field

Type

Reset

Description

31-3

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

PERIPH_ON

R/W

PERIPH Power domain.
0: PERIPH power domain is powered down
1: PERIPH power domain is powered up

SERIAL_ON

R/W

SERIAL Power domain.
0: SERIAL power domain is powered down
1: SERIAL power domain is powered up

RFC_ON

R/W

0: RFC power domain powered off if also PDCTL1.RFC_ON = 0
1: RFC power domain powered on

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.39 PDCTL0RFC Register (Offset = 130h) [reset = 0h]
PDCTL0RFC is shown in Figure 6-94 and described in Table 6-100.
Return to Summary Table.
RFC Power Domain Control
Figure 6-94. PDCTL0RFC Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R/W0h

Table 6-100. PDCTL0RFC Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Alias for PDCTL0.RFC_ON

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

531

PRCM Registers

www.ti.com

6.8.2.4.40 PDCTL0SERIAL Register (Offset = 134h) [reset = 0h]
PDCTL0SERIAL is shown in Figure 6-95 and described in Table 6-101.
Return to Summary Table.
SERIAL Power Domain Control
Figure 6-95. PDCTL0SERIAL Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R/W0h

Table 6-101. PDCTL0SERIAL Register Field Descriptions
Bit
31-1
0

532

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Alias for PDCTL0.SERIAL_ON

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.41 PDCTL0PERIPH Register (Offset = 138h) [reset = 0h]
PDCTL0PERIPH is shown in Figure 6-96 and described in Table 6-102.
Return to Summary Table.
PERIPH Power Domain Control
Figure 6-96. PDCTL0PERIPH Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R/W0h

Table 6-102. PDCTL0PERIPH Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Alias for PDCTL0.PERIPH_ON

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

533

PRCM Registers

www.ti.com

6.8.2.4.42 PDSTAT0 Register (Offset = 140h) [reset = 0h]
PDSTAT0 is shown in Figure 6-97 and described in Table 6-103.
Return to Summary Table.
Power Domain Status
Figure 6-97. PDSTAT0 Register
31

2
PERIPH_ON
R-0h

1
SERIAL_ON
R-0h

0
RFC_ON
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

Table 6-103. PDSTAT0 Register Field Descriptions
Bit

534

Field

Type

Reset

Description

31-3

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

PERIPH_ON

PERIPH Power domain.
0: Domain may be powered down
1: Domain powered up (guaranteed)

SERIAL_ON

SERIAL Power domain.
0: Domain may be powered down
1: Domain powered up (guaranteed)

RFC_ON

RFC Power domain
0: Domain may be powered down
1: Domain powered up (guaranteed)

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.43 PDSTAT0RFC Register (Offset = 144h) [reset = 0h]
PDSTAT0RFC is shown in Figure 6-98 and described in Table 6-104.
Return to Summary Table.
RFC Power Domain Status
Figure 6-98. PDSTAT0RFC Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R-0h

Table 6-104. PDSTAT0RFC Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Alias for PDSTAT0.RFC_ON

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

535

PRCM Registers

www.ti.com

6.8.2.4.44 PDSTAT0SERIAL Register (Offset = 148h) [reset = 0h]
PDSTAT0SERIAL is shown in Figure 6-99 and described in Table 6-105.
Return to Summary Table.
SERIAL Power Domain Status
Figure 6-99. PDSTAT0SERIAL Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R-0h

Table 6-105. PDSTAT0SERIAL Register Field Descriptions
Bit
31-1
0

536

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Alias for PDSTAT0.SERIAL_ON

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.45 PDSTAT0PERIPH Register (Offset = 14Ch) [reset = 0h]
PDSTAT0PERIPH is shown in Figure 6-100 and described in Table 6-106.
Return to Summary Table.
PERIPH Power Domain Status
Figure 6-100. PDSTAT0PERIPH Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R-0h

Table 6-106. PDSTAT0PERIPH Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Alias for PDSTAT0.PERIPH_ON

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

537

PRCM Registers

www.ti.com

6.8.2.4.46 PDCTL1 Register (Offset = 17Ch) [reset = Ah]
PDCTL1 is shown in Figure 6-101 and described in Table 6-107.
Return to Summary Table.
Power Domain Control
Figure 6-101. PDCTL1 Register
31

3
VIMS_MODE
R/W-1h

2
RFC_ON
R/W-0h

1
CPU_ON
R/W-1h

0
RESERVED
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

6
RESERVED
R-0h

4
RESERVED
R/W-0h

Table 6-107. PDCTL1 Register Field Descriptions
Bit

538

Field

Type

Reset

Description

31-5

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

VIMS_MODE

R/W

0: VIMS power domain is only powered when CPU power domain is
powered.
1: VIMS power domain is powered whenever the BUS power domain
is powered.

RFC_ON

R/W

0: RFC power domain powered off if also PDCTL0.RFC_ON = 0
1: RFC power domain powered on
Bit shall be used by RFC in autonomus mode but there is no HW
restrictions fom system CPU to access the bit.

CPU_ON

R/W

0: Causes a power down of the CPU power domain when system
CPU indicates it is idle.
1: Initiates power-on of the CPU power domain.
This bit is automatically set by a WIC power-on event.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.47 PDCTL1CPU Register (Offset = 184h) [reset = 1h]
PDCTL1CPU is shown in Figure 6-102 and described in Table 6-108.
Return to Summary Table.
CPU Power Domain Direct Control
Figure 6-102. PDCTL1CPU Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R/W1h

Table 6-108. PDCTL1CPU Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

This is an alias for PDCTL1.CPU_ON

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

539

PRCM Registers

www.ti.com

6.8.2.4.48 PDCTL1RFC Register (Offset = 188h) [reset = 0h]
PDCTL1RFC is shown in Figure 6-103 and described in Table 6-109.
Return to Summary Table.
RFC Power Domain Direct Control
Figure 6-103. PDCTL1RFC Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R/W0h

Table 6-109. PDCTL1RFC Register Field Descriptions
Bit
31-1
0

540

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

This is an alias for PDCTL1.RFC_ON

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.49 PDCTL1VIMS Register (Offset = 18Ch) [reset = 1h]
PDCTL1VIMS is shown in Figure 6-104 and described in Table 6-110.
Return to Summary Table.
VIMS Mode Direct Control
Figure 6-104. PDCTL1VIMS Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R/W1h

Table 6-110. PDCTL1VIMS Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

This is an alias for PDCTL1.VIMS_MODE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

541

PRCM Registers

www.ti.com

6.8.2.4.50 PDSTAT1 Register (Offset = 194h) [reset = 1Ah]
PDSTAT1 is shown in Figure 6-105 and described in Table 6-111.
Return to Summary Table.
Power Manager Status
Figure 6-105. PDSTAT1 Register
31

3
VIMS_MODE
R-1h

2
RFC_ON
R-0h

1
CPU_ON
R-1h

0
RESERVED
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

6
RESERVED
R-0h

4
BUS_ON
R-1h

Table 6-111. PDSTAT1 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BUS_ON

0: BUS domain not accessible
1: BUS domain is currently accessible

VIMS_MODE

0: VIMS domain not accessible
1: VIMS domain is currently accessible

RFC_ON

0: RFC domain not accessible
1: RFC domain is currently accessible

CPU_ON

0: CPU and BUS domain not accessible
1: CPU and BUS domains are both currently accessible

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-5

542

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.51 PDSTAT1BUS Register (Offset = 198h) [reset = 1h]
PDSTAT1BUS is shown in Figure 6-106 and described in Table 6-112.
Return to Summary Table.
BUS Power Domain Direct Read Status
Figure 6-106. PDSTAT1BUS Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R-1h

Table 6-112. PDSTAT1BUS Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

This is an alias for PDSTAT1.BUS_ON

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

543

PRCM Registers

www.ti.com

6.8.2.4.52 PDSTAT1RFC Register (Offset = 19Ch) [reset = 0h]
PDSTAT1RFC is shown in Figure 6-107 and described in Table 6-113.
Return to Summary Table.
RFC Power Domain Direct Read Status
Figure 6-107. PDSTAT1RFC Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R-0h

Table 6-113. PDSTAT1RFC Register Field Descriptions
Bit
31-1
0

544

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

This is an alias for PDSTAT1.RFC_ON

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.53 PDSTAT1CPU Register (Offset = 1A0h) [reset = 1h]
PDSTAT1CPU is shown in Figure 6-108 and described in Table 6-114.
Return to Summary Table.
CPU Power Domain Direct Read Status
Figure 6-108. PDSTAT1CPU Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R-1h

Table 6-114. PDSTAT1CPU Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

This is an alias for PDSTAT1.CPU_ON

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

545

PRCM Registers

www.ti.com

6.8.2.4.54 PDSTAT1VIMS Register (Offset = 1A4h) [reset = 1h]
PDSTAT1VIMS is shown in Figure 6-109 and described in Table 6-115.
Return to Summary Table.
VIMS Mode Direct Read Status
Figure 6-109. PDSTAT1VIMS Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ON
R-1h

Table 6-115. PDSTAT1VIMS Register Field Descriptions
Bit
31-1
0

546

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

This is an alias for PDSTAT1.VIMS_MODE

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.55 RFCBITS Register (Offset = 1CCh) [reset = 0h]
RFCBITS is shown in Figure 6-110 and described in Table 6-116.
Return to Summary Table.
Control To RFC
Figure 6-110. RFCBITS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
READ
R/W-0h

Table 6-116. RFCBITS Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

READ

R/W

Control bits for RFC. The RF core CPE processor will automatically
check this register when it boots, and it can be used to immediately
instruct CPE to perform some tasks at its start-up. The supported
functionality is ROM-defined and may vary. See the technical
reference manual for more details.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

547

PRCM Registers

www.ti.com

6.8.2.4.56 RFCMODESEL Register (Offset = 1D0h) [reset = 0h]
RFCMODESEL is shown in Figure 6-111 and described in Table 6-117.
Return to Summary Table.
Selected RFC Mode
Figure 6-111. RFCMODESEL Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
CURR
R/W-0h

Table 6-117. RFCMODESEL Register Field Descriptions
Bit

548

Field

Type

Reset

Description

31-3

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

2-0

CURR

R/W

Selects the set of commands that the RFC will accept. Only modes
permitted by RFCMODEHWOPT.AVAIL are writeable. See the
technical reference manual for details.
0h = Select Mode 0
1h = Select Mode 1
2h = Select Mode 2
3h = Select Mode 3
4h = Select Mode 4
5h = Select Mode 5
6h = Select Mode 6
7h = Select Mode 7

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.57 RFCMODEHWOPT Register (Offset = 1D4h) [reset = 0h]
RFCMODEHWOPT is shown in Figure 6-112 and described in Table 6-118.
Return to Summary Table.
Allowed RFC Modes
Figure 6-112. RFCMODEHWOPT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3
AVAIL
R-0h

Table 6-118. RFCMODEHWOPT Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

AVAIL

Permitted RFC modes. More than one mode can be permitted.
1h = Mode 0 permitted
2h = Mode 1 permitted
4h = Mode 2 permitted
8h = Mode 3 permitted
10h = Mode 4 permitted
20h = Mode 5 permitted
40h = Mode 6 permitted
80h = Mode 7 permitted

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

549

PRCM Registers

www.ti.com

6.8.2.4.58 PWRPROFSTAT Register (Offset = 1E0h) [reset = 1h]
PWRPROFSTAT is shown in Figure 6-113 and described in Table 6-119.
Return to Summary Table.
Power Profiler Register
Figure 6-113. PWRPROFSTAT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
VALUE
R/W-1h

Table 6-119. PWRPROFSTAT Register Field Descriptions
Bit

550

Field

Type

Reset

Description

31-8

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

VALUE

R/W

SW can use these bits to timestamp the application. These bits are
also available through the testtap and can thus be used by the
emulator to profile in real time.

Power, Reset, and Clock Management

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

PRCM Registers

www.ti.com

6.8.2.4.59 RAMRETEN Register (Offset = 224h) [reset = 3h]
RAMRETEN is shown in Figure 6-114 and described in Table 6-120.
Return to Summary Table.
Memory Retention Control
Figure 6-114. RAMRETEN Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

2
RFC
R/W0h

VIMS
R/W-3h

Table 6-120. RAMRETEN Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RFC

R/W

0: Retention for RFC SRAM disabled
1: Retention for RFC SRAM enabled
Memories controlled: CPERAM MCERAM RFERAM

1-0

VIMS

R/W

0: Memory retention disabled
1: Memory retention enabled
Bit 0: VIMS_TRAM
Bit 1: VIMS_CRAM
Legal modes depend on settings in VIMS:CTL.MODE
00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted
- must be set to CACHE or SPLIT mode after waking up again
01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is
asserted. Must remain in GPRAM mode after wake up, alternatively
select OFF mode first and then CACHE or SPILT mode.
10: Illegal mode
11: No restrictions

31-3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power, Reset, and Clock Management

551

Chapter 7
SWCU117G – February 2015 – Revised February 2017

Versatile Instruction Memory System (VIMS)
This chapter discusses the Versatile Instruction Memory System (VIMS) of the CC26x0 and CC13x0
devices.

552

Topic

...........................................................................................................................

7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9

VIMS Overview ................................................................................................
VIMS Configurations .........................................................................................
VIMS Software Remarks ....................................................................................
ROM................................................................................................................
FLASH.............................................................................................................
Power Management Requirements .....................................................................
ROM Functions ................................................................................................
SRAM ..............................................................................................................
VIMS Registers .................................................................................................

Versatile Instruction Memory System (VIMS)

Page

553
554
558
559
559
560
562
563
564

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Overview

www.ti.com

7.1

VIMS Overview
The main instruction memories are encapsulated in a versatile instruction memory system (VIMS) module,
which includes the following memories:
• 128-KB Flash
• 8-KB RAM Cache or general-purpose RAM (GPRAM)
• 115-KB Boot ROM
Figure 7-1 shows an overview of the VIMS module.
Figure 7-1. VIMS Overview

icode
decoder

Cache

dcode
bus

bus

Flash

sysbys

ROM

The VIMS module forwards CPU accesses (icode/dcode) and system bus accesses to the addressed
memories; the VIMS module also arbitrates access between the CPU and the system bus.
The VIMS module runs on the 48-MHz system clock.
The flash memory is programmable from user software, from the debug interface, and from the ROM
bootloader. The RAM block can be used as a cache for the Flash block or as general purpose RAM.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

553

VIMS Configurations

7.2

www.ti.com

VIMS Configurations

7.2.1 VIMS Modes
The VIMS cache RAM block and the Cache block can operate in the following modes:
• GPRAM
• CACHE
• OFF
The current mode is shown in the VIMS:STAT.* register, and mode switching is controlled through the
VIMS:CTL.MODE register. The mode transitions are shown in Figure 7-2. Lines in black are software
initiated changes through the VIMS:CTL.MODE register. Lines in brown are hardware initiated changes.
The invalidating state is a transition state controlled by hardware. Invalidation clears the entire content of
the RAM block and takes 1029 clock periods to perform.
Figure 7-2. VIMS Mode Switching Flowchart
Reset
Invalidating

GPRAM

ENABLED

SPLIT

OFF

Invalidating

Once a mode change is initiated, shown in the VIMS:STATUS.MODE_CHANGING register, the mode
change must complete before another mode change can be initiated. The VIMS:CTL.MODE register is
blocked for updates during a mode change.

554

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Configurations

www.ti.com

7.2.1.1

GPRAM Mode

In GPRAM mode, the RAM block functions as a general-purpose RAM. The Flash block has no cache
support, and all accesses to the flash are routed directly to the Flash block.
Figure 7-3. VIMS Module in GPRAM Mode
GPRAM
address space

icode/dcode
GPRAM

icode/dcode

SYSCODE and
USERCODE
address space

FLASH

sysbus
sysbus

ROM

BROM
address space

7.2.1.2

Off Mode

In off mode, the RAM block is disabled and cannot be accessed by the CPU or by the system bus. The
Flash block has no cache support, and all accesses to the flash are routed directly to the Flash block.
Figure 7-4. VIMS Module in Off Mode
GPRAM

icode/dcode

SYSCODE and
USERCODE
address space

icode/dcode
FLASH

sysbus
sysbus

ROM

BROM
address space

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

555

VIMS Configurations

7.2.1.3

www.ti.com

Cache Mode

In cache mode, the RAM block functions as an 8K 4-way random replacement cache for the Flash block.
The GPRAM space is not available in cache mode. The cache support is only available for CPU accesses
to the flash SYSCODE address space. System bus accesses to the Flash block and CPU accesses to the
flash USERCODE address space are routed directly to the Flash block.
Figure 7-5. VIMS Module in Cache Mode
SYSCODE
address space

icode/dcode
GPRAM

USERCODE
address space

FLASH
USERCODE and

SYSCODE
address space

sysbus

ROM

BROM
address space

In cache mode, all CPU accesses to the flash SYSCODE address space are directed to the cache first.
The cache looks up the input address in the internal tag RAM to determine whether the access is a cache
hit or a cache miss.
In the case of a cache miss, the access is forwarded to the Flash block. The response from the Flash
block is routed back to the cache, then the cache is updated.
In the case of a cache hit, the data is fetched directly from the cache RAM.
The cache also contains a line buffer because the cache RAM word size is 64 bits. The objective of the
line buffer is to prevent refetching the 32-bit part of the data that has already been fetched (but not used)
in the previous access. The line buffer prevents both TAG and CACHE lookup if the data is already in the
line buffer.
The cache line buffer is cleared as a part of the invalidation scheme.

556

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Configurations

www.ti.com

7.2.2 VIMS Flash Line Buffering
The VIMS module contains two flash line buffers because the flash word size is 64 bits.
• A line buffer is placed in the flash CPU bus path that is controlled by the VIMS:CTL.IDCODE_LB_DIS
register.
• A line buffer is placed in the flash system bus path that is controlled by the
VIMS:CTL.SYSBUS_LB_DIS register.
The objectives of the buffers are to prevent refetching the 32-bit part of the data that has already been
fetched (but not used) in a previous cycle. The status of the line buffers can be found in the
VIMS:STATUS.IDCODE_LB_DIS register and the VIMS:STATUS.SYSBUS_LB_DIS register.

7.2.3 VIMS Arbitration
The VIMS provides arbitration between the CPU bus and the system bus. The arbitration is configurable
between round-robin and static, through the VIMS:CTL.ARB_CFG register. The static arbitration is
enabled by default and gives the CPU priority over system bus accesses.
The system arbiter allows accesses to occur simultaneously, provided that the CPU bus and the system
bus have different target memories. If, for example, a CPU access causes a cache hit, a system bus
access can access the flash simultaneously.

7.2.4 VIMS Cache TAG Prefetch
The cache contains a TAG prefetch system that automatically prefetches the TAG data for the next 64-bit
address. This feature is controlled through the VIMS:CTL.PREF_EN register, and is only enabled if the
VIMS mode is set to cache mode. Any access using a prefetched TAG saves one CLK cycle in the access
because tag lookup can be skipped. A prefetch hit is defined as an access using prefetched TAG data and
data that is available in the cache.
TAG prefetch is mainly intended for performance optimization when the CPU is running at full speed. If the
CPU is not running at full speed, there is no performance optimization; therefore the TAG prefetch system
must be disabled.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

557

VIMS Software Remarks

7.3

www.ti.com

VIMS Software Remarks
When the flash is programmed or updated, or when the VIMS domain is entering power down special care
must be taken from the software side.
The following remarks are automatically taken care of when using in-built ROM functions and the standard
API functions. However, custom code must take the following remarks into account.

7.3.1 Flash Program or Update
Before updating the flash, the VIMS cache and line buffers must be invalidated and flushed to prevent old
data or instructions from being fetched from the cache or line buffers after a flash program or update.
Hence, the VIMS mode must be set to GPRAM or OFF mode before programming, and both VIMS flash
line buffers must be set to disabled.

7.3.2 VIMS Retention
The VIMS domain can be kept in retention, if needed, when the domain is entering power down. The
retention control has the option to specify which memories (internal TAG RAM or cache RAM) are kept in
retention together with VIMS logic.
NOTE: If the whole MCU domain is powered off, the VIMS domain does not support retention.

Table 7-1 specifies the valid retention combination for VIMS memory.
Table 7-1. Valid Retention Combination for VIMS Memory
Mode

7.3.2.1

Retention Enabled

Comment

TAG-RAM

CACHE-RAM

VIMS Logic

Yes

Software must compensate for loss of data
in RAMs

Yes

Works in GPRAM mode without software
intervention

Yes

Mode 1

Mode 1 is intended for use when the system is in off mode, cache mode.
When the cache is enabled (in cache mode), software must manually change the VIMS mode to off mode
before entering retention. When the system is taken out of retention, software must put VIMS back into
either cache mode, which invalidates the cache memories (see Figure 7-6).
Figure 7-6. Software Precautions With No RAM Retention
Mode 1
ENABLED
or
SPLIT
OFF
pwr down

TAG and
cache
memory are
corrupted

OFF

INIT
SPLIT

INIT
ENABLED

Mode 1 can also be used when the system is in GPRAM mode, but software must take into account that
the data in the GPRAM is lost when the system is set in retention.
558

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

ROM

www.ti.com

7.3.2.2

Mode 2

Mode 2 is intended for systems where cache is in GPRAM mode. VIMS is retained with retention power to
the GPRAM.
NOTE: If software tries to put VIMS into enabled mode after retention, the system fails because the
TAG memory is corrupted.

The correct procedure is to put VIMS into off mode; then put VIMS into disabled mode (see Figure 7-7 for
more details).
Figure 7-7. GPRAM Retention
Mode 2
DISABLED
TAG
memory is
corrupted

pwr down
DISABLED
If switch to enabled is needed, the
following sequence is required:
OFF

INIT
SPLIT

7.4

INIT
ENABLED

ROM
The ROM contains a serial bootloader with SPI and UART support (see Chapter 8) as well as a Driver
Library and an RF stack support. See Table 3-2 for details.

7.5

FLASH
The flash memory is organized as a set of 4-KB blocks that can be individually erased. An individual 32-bit
word can be programmed to change bits from 1 to 0. In addition, a write buffer provides the ability to
program 32 continuous words in flash memory in half the time of programming the words individually.
Erasing a block causes the entire contents of the block to be reset to all 1s. The 4-KB blocks are paired
with sets of 8-KB blocks that can be individually protected. The protection allows blocks to be marked as
read-only or execute-only, thus providing different levels of code protection. Read-only blocks cannot be
erased or programmed, which protects the contents of those blocks from being modified. Execute-only
blocks cannot be erased or programmed and can only be read by the controller instruction fetch
mechanism, which protects the contents of those blocks from being read by either the controller or a
debugger.
The Flash block is mainly clocked by the 48-MHz system clock.

7.5.1 FLASH Memory Protection
The FLASH memory can be read/write protected in 4-KB sectors by configuring the CCFG.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

559

FLASH

www.ti.com

7.5.2 Memory Programming
Memory programming is done using TI provided API. When calling the API functions, all interrupts should
be disabled to prevent any attempts to read the FLASH during the execution of these functions.
Table 7-2. CC26x0 and CC13x0 Memory Write/Erase Protection (1) (2) (3)
Memory Area
CC26x0 and
CC13x0 State

FCFG0
(Efuse)

FCFG1
(ENGR)

CCFG

Ti locked
Sector

Customer
Locked

Customer Free

Write 1s
(no way back)

Free

None

All

Packed die

Locked

Free

None

All

Engineering sample

Locked

Free

None

All

Customer
development

Locked

Free

Fixed

None

Except TI locked
sectors

Customer delivery
case 1

Locked

Writable
(Not
erasable) (4)

Fixed

Can add locked
sectors (4)

May be reduced (4)

Customer delivery
case 2

Locked

Locked (4)

Fixed

Fixed (4)

Unpacked die

(1)
(2)
(3)
(4)

Locked: Not writable and not erasable
Free: Writable and erasable
Fixed: The number of this type is fixed
The Chip Erase function erases all sectors not locked by TI.

7.5.3 FLASH Memory Programming
During a flash memory write or erase operation, the Flash memory must not be read. If instruction
execution is required during a flash memory operation, the executing code must be placed in SRAM (and
executed from SRAM) while the flash operation is in progress.

7.6

Power Management Requirements
The module implements the following power-reducing functionalities:
• Voltage Off: The module logic VDD is turned off. Pump and bank is kept in deep sleep. This mode
requires a reset and software configuration to become active.
• Power Off: This is the same state as Voltage Off with the only difference that module logic has
retention on all registers. From Power Off mode, the module can become active without any software
configurations.
• Deep Standby: Internal circuits are partly powered down. No internal configuration is required to
become active, but there is some delay due to voltage ramping and so on.
• Idle Reading: Use advanced power reduction features in the Pump and Bank to save power when no
active reading is going on. In this mode, switching to Active Read is done without any reduced read
latency.
• Reading: Flash is actively reading without any power reduction.

560

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power Management Requirements

www.ti.com

Methods for changing power mode:
• Leaving Voltage Off or Power Off can only be done from the system power management. Voltage Off
is like initial power on. Power Off requires a restore of retention, and internal sequencers must power
up and configure the bank and charge pump.
• Leaving Deep Standby can start from the following:
– PRCM
– By writing a register in the MMR
– By starting a read access to the flash
• Switching between Idle Reading and Reading is done automatically when a read has ended. The
switching can be disabled by a register setting.
• Switching from Idle Reading to any other mode is done by setting up a register with the target power
mode. After some time without read accesses, the module enters or prepares the selected mode. The
last step to achieve Power Off or Voltage Off is done by the system power management.
Current Consumption
Flash Active

Read

Flash_off_req_1=1

No Read

Flash Active
Flash_off_req_1=0

Power Off:
logical mode,
ready for
retention

Warm Reset

MMR Block

Block Flash:
access during
oscillator
source change

Pump/ Bank Grace
Period

Read

Deep Standby:
this mode is entered after
a programmed idle mode timeout,
auto return to idle when reading

Retention mode by PRCM

µA

Power Off (retention mode)
RESETVDDSZ asserted
VDD off to bank/pump.

Voltage off by PRCM

Voltage Off,
Reset asserted
nA

Oscillator Requirements

None/uncalibrated

Holes allowed

Calibrated 48 MHz

Figure 7-8. Flash Power States

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

561

ROM Functions

7.7

www.ti.com

ROM Functions
Overview of memory contents:
• eFuse
– Contains mostly critical chip-trim items needed before bootloader starts
– Interfaced through the Flash module in the digital core
• Flash trim
• Ram repair
• Analog trim (band gap, brown-out, selected regulators, internal 48-MHz RC Oscillator)
• JTAG TAP/DAP lock
• CRC check (8 bits)
– The only critical item here is the JTAG TAP/DAP lock that is locked by default (if a fuse is blown).
• FCFG:
– Currently a separate Flash block
– All trims plus entire device configuration
• Flash trim to support erase/write
• Module trim (analog, RF+++)
• Chip configuration (ID, device type, package size, pinout++, production test data)
• Bootloader configuration
• Security
• TI FA Analysis option
• JTAG TAP/DAP lock override
• Bootloader enable
• Customer configuration (last page in flash):
– Bootloader disable
– JTAG DAP/TAP disable
– TI FA analysis disable
– Customer configuration area write or erase protection
– Other configuration not related to security
Configuration memory:
• RO
– OTP, 1-KB read interface (write through FMC)
• RO
– ENGR 1-KB read interface (write through FMC)
• CCFG
– FLASH sector 4-KB read interface (write through FMC)
• RO
– EFUSE, only accessible through MMR interface
The ROM is preprogrammed with a serial bootloader (SPI or UART). For applications that require in-field
programmability, the royalty-free bootloader acts as an application loader and supports in-field firmware
updates. The bootloader either executes automatically if no valid image has been written to the flash, or
the bootloader may be started through a configurable GPIO backdoor. The bootloader may not be called
from application code.

562

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

SRAM

www.ti.com

7.8

SRAM
The CC26x0 and CC13x0 devices provide a 20-KB single-cycle on-chip SRAM with full retention in all
power modes, except shutdown. Although retention can be configured in 4-KB blocks, this will not give
any noticeable reduction of current consumption. It is thus recommended to retain the whole SRAM at all
times.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding
technology in the Cortex-M3 processor. With a bit-band enabled processor, certain regions in the memory
map (SRAM and peripheral space) can use address aliases to access individual bits in one atomic
operation.
Data can also be transferred to and from the SRAM using the micro direct memory access controller
( DMA). The Cortex-M0 in the RF Core also has access to the system RAM.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

563

VIMS Registers

7.9

www.ti.com

VIMS Registers

7.9.1 FLASH Registers
Table 7-3 lists the memory-mapped registers for the FLASH. All register offset addresses not listed in
Table 7-3 should be considered as reserved locations and the register contents should not be modified.
Table 7-3. FLASH Registers
Offset

564

Acronym

Section

1Ch

STAT

FMC and Efuse Status

Section 7.9.1.1

24h

CFG

Internal

Section 7.9.1.2

28h

SYSCODE_START

Internal

Section 7.9.1.3

2Ch

FLASH_SIZE

Internal

Section 7.9.1.4

3Ch

FWLOCK

Internal

Section 7.9.1.5

40h

FWFLAG

Internal

Section 7.9.1.6

1000h

EFUSE

Internal

Section 7.9.1.7

1004h

EFUSEADDR

Internal

Section 7.9.1.8

1008h

DATAUPPER

Internal

Section 7.9.1.9

100Ch

DATALOWER

Internal

Section 7.9.1.10

1010h

EFUSECFG

Internal

Section 7.9.1.11

1014h

EFUSESTAT

Internal

Section 7.9.1.12

1018h

ACC

Internal

Section 7.9.1.13

101Ch

BOUNDARY

Internal

Section 7.9.1.14

1020h

EFUSEFLAG

Internal

Section 7.9.1.15

1024h

EFUSEKEY

Internal

Section 7.9.1.16

1028h

EFUSERELEASE

Internal

Section 7.9.1.17

102Ch

EFUSEPINS

Internal

Section 7.9.1.18

1030h

EFUSECRA

Internal

Section 7.9.1.19

1034h

EFUSEREAD

Internal

Section 7.9.1.20

1038h

EFUSEPROGRAM

Internal

Section 7.9.1.21

103Ch

EFUSEERROR

Internal

Section 7.9.1.22

1040h

SINGLEBIT

Internal

Section 7.9.1.23

1044h

TWOBIT

Internal

Section 7.9.1.24

1048h

SELFTESTCYC

Internal

Section 7.9.1.25

104Ch

SELFTESTSIGN

Internal

Section 7.9.1.26

2000h

FRDCTL

Internal

Section 7.9.1.27

2004h

FSPRD

Internal

Section 7.9.1.28

2008h

FEDACCTL1

Internal

Section 7.9.1.29

201Ch

FEDACSTAT

Internal

Section 7.9.1.30

2030h

FBPROT

Internal

Section 7.9.1.31

2034h

FBSE

Internal

Section 7.9.1.32

2038h

FBBUSY

Internal

Section 7.9.1.33

203Ch

FBAC

Internal

Section 7.9.1.34

2040h

FBFALLBACK

Internal

Section 7.9.1.35

2044h

FBPRDY

Internal

Section 7.9.1.36

2048h

FPAC1

Internal

Section 7.9.1.37

204Ch

FPAC2

Internal

Section 7.9.1.38

2050h

FMAC

Internal

Section 7.9.1.39

2054h

FMSTAT

Internal

Section 7.9.1.40

2064h

FLOCK

Internal

Section 7.9.1.41

2080h

FVREADCT

Internal

Section 7.9.1.42

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

Table 7-3. FLASH Registers (continued)
Offset

Acronym

2084h

FVHVCT1

Internal

Section 7.9.1.43

Section

2088h

FVHVCT2

Internal

Section 7.9.1.44

208Ch

FVHVCT3

Internal

Section 7.9.1.45

2090h

FVNVCT

Internal

Section 7.9.1.46

2094h

FVSLP

Internal

Section 7.9.1.47

2098h

FVWLCT

Internal

Section 7.9.1.48

209Ch

FEFUSECTL

Internal

Section 7.9.1.49

20A0h

FEFUSESTAT

Internal

Section 7.9.1.50

20A4h

FEFUSEDATA

Internal

Section 7.9.1.51

20A8h

FSEQPMP

Internal

Section 7.9.1.52

2100h

FBSTROBES

Internal

Section 7.9.1.53

2104h

FPSTROBES

Internal

Section 7.9.1.54

2108h

FBMODE

Internal

Section 7.9.1.55

210Ch

FTCR

Internal

Section 7.9.1.56

2110h

FADDR

Internal

Section 7.9.1.57

211Ch

FTCTL

Internal

Section 7.9.1.58

2120h

FWPWRITE0

Internal

Section 7.9.1.59

2124h

FWPWRITE1

Internal

Section 7.9.1.60

2128h

FWPWRITE2

Internal

Section 7.9.1.61

212Ch

FWPWRITE3

Internal

Section 7.9.1.62

2130h

FWPWRITE4

Internal

Section 7.9.1.63

2134h

FWPWRITE5

Internal

Section 7.9.1.64

2138h

FWPWRITE6

Internal

Section 7.9.1.65

213Ch

FWPWRITE7

Internal

Section 7.9.1.66

2140h

FWPWRITE_ECC

Internal

Section 7.9.1.67

2144h

FSWSTAT

Internal

Section 7.9.1.68

2200h

FSM_GLBCTL

Internal

Section 7.9.1.69

2204h

FSM_STATE

Internal

Section 7.9.1.70

2208h

FSM_STAT

Internal

Section 7.9.1.71

220Ch

FSM_CMD

Internal

Section 7.9.1.72

2210h

FSM_PE_OSU

Internal

Section 7.9.1.73

2214h

FSM_VSTAT

Internal

Section 7.9.1.74

2218h

FSM_PE_VSU

Internal

Section 7.9.1.75

221Ch

FSM_CMP_VSU

Internal

Section 7.9.1.76

2220h

FSM_EX_VAL

Internal

Section 7.9.1.77

2224h

FSM_RD_H

Internal

Section 7.9.1.78

2228h

FSM_P_OH

Internal

Section 7.9.1.79

222Ch

FSM_ERA_OH

Internal

Section 7.9.1.80

2230h

FSM_SAV_PPUL

Internal

Section 7.9.1.81

2234h

FSM_PE_VH

Internal

Section 7.9.1.82

2240h

FSM_PRG_PW

Internal

Section 7.9.1.83

2244h

FSM_ERA_PW

Internal

Section 7.9.1.84

2254h

FSM_SAV_ERA_PUL

Internal

Section 7.9.1.85

2258h

FSM_TIMER

Internal

Section 7.9.1.86

225Ch

FSM_MODE

Internal

Section 7.9.1.87

2260h

FSM_PGM

Internal

Section 7.9.1.88

2264h

FSM_ERA

Internal

Section 7.9.1.89

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

565

VIMS Registers

www.ti.com

Table 7-3. FLASH Registers (continued)

566

Offset

Acronym

2268h

FSM_PRG_PUL

Internal

Section 7.9.1.90

Section

226Ch

FSM_ERA_PUL

Internal

Section 7.9.1.91

2270h

FSM_STEP_SIZE

Internal

Section 7.9.1.92

2274h

FSM_PUL_CNTR

Internal

Section 7.9.1.93

2278h

FSM_EC_STEP_HEIGHT

Internal

Section 7.9.1.94

227Ch

FSM_ST_MACHINE

Internal

Section 7.9.1.95

2280h

FSM_FLES

Internal

Section 7.9.1.96

2288h

FSM_WR_ENA

Internal

Section 7.9.1.97

228Ch

FSM_ACC_PP

Internal

Section 7.9.1.98

2290h

FSM_ACC_EP

Internal

Section 7.9.1.99

22A0h

FSM_ADDR

Internal

Section 7.9.1.100

22A4h

FSM_SECTOR

Internal

Section 7.9.1.101

22A8h

FMC_REV_ID

Internal

Section 7.9.1.102

22ACh

FSM_ERR_ADDR

Internal

Section 7.9.1.103

22B0h

FSM_PGM_MAXPUL

Internal

Section 7.9.1.104

22B4h

FSM_EXECUTE

Internal

Section 7.9.1.105

22C0h

FSM_SECTOR1

Internal

Section 7.9.1.106

22C4h

FSM_SECTOR2

Internal

Section 7.9.1.107

22E0h

FSM_BSLE0

Internal

Section 7.9.1.108

22E4h

FSM_BSLE1

Internal

Section 7.9.1.109

22F0h

FSM_BSLP0

Internal

Section 7.9.1.110

22F4h

FSM_BSLP1

Internal

Section 7.9.1.111

2400h

FCFG_BANK

Internal

Section 7.9.1.112

2404h

FCFG_WRAPPER

Internal

Section 7.9.1.113

2408h

FCFG_BNK_TYPE

Internal

Section 7.9.1.114

2410h

FCFG_B0_START

Internal

Section 7.9.1.115

2414h

FCFG_B1_START

Internal

Section 7.9.1.116

2418h

FCFG_B2_START

Internal

Section 7.9.1.117

241Ch

FCFG_B3_START

Internal

Section 7.9.1.118

2420h

FCFG_B4_START

Internal

Section 7.9.1.119

2424h

FCFG_B5_START

Internal

Section 7.9.1.120

2428h

FCFG_B6_START

Internal

Section 7.9.1.121

242Ch

FCFG_B7_START

Internal

Section 7.9.1.122

2430h

FCFG_B0_SSIZE0

Internal

Section 7.9.1.123

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.1

STAT Register (Offset = 1Ch) [reset = 0h]

STAT is shown in Figure 7-9 and described in Table 7-4.
Return to Summary Table.
FMC and Efuse Status
Figure 7-9. STAT Register
31

10
EFUSE_ERRCODE

1
BUSY

0
POWER_MOD
E
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

15
EFUSE_BLAN
K
R-0h

14
EFUSE_TIMEO
UT
R-0h

13
EFUSE_CRC_
ERROR
R-0h

5
RESERVED

R-0h

2
SAMHOLD_DI
S
R-0h

R-0h

Table 7-4. STAT Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EFUSE_BLANK

Efuse scanning detected if fuse ROM is blank:
0 : Not blank
1 : Blank

EFUSE_TIMEOUT

Efuse scanning resulted in timeout error.
0 : No Timeout error
1 : Timeout Error

EFUSE_CRC_ERROR

Efuse scanning resulted in scan chain CRC error.
0 : No CRC error
1 : CRC Error

12-8

EFUSE_ERRCODE

Same as EFUSEERROR.CODE

7-3

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SAMHOLD_DIS

Status indicator of flash sample and hold sequencing logic. This bit
will go to 1 some delay after CFG.DIS_IDLE is set to 1.
0: Not disabled
1: Sample and hold disabled and stable

BUSY

Fast version of the FMC FMSTAT.BUSY bit.
This flag is valid immediately after the operation setting it
(FMSTAT.BUSY is delayed some cycles)
0 : Not busy
1 : Busy

POWER_MODE

Power state of the flash sub-system.
0 : Active
1 : Low power

31-16

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

567

VIMS Registers

7.9.1.2

www.ti.com

CFG Register (Offset = 24h) [reset = 0h]

CFG is shown in Figure 7-10 and described in Table 7-5.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-10. CFG Register
31

8
STANDBY_MO
DE_SEL
R/W-0h

2
RESERVED

1
DIS_STANDBY

0
DIS_IDLE

R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

7
6
STANDBY_PW_SEL
R/W-0h

5
4
3
DIS_EFUSECL DIS_READACC ENABLE_SWIN
K
ESS
TF
R/W-0h
R/W-0h
R/W-0h

Table 7-5. CFG Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Internal. Only to be used through TI provided API.

STANDBY_MODE_SEL

R/W

Internal. Only to be used through TI provided API.

STANDBY_PW_SEL

R/W

Internal. Only to be used through TI provided API.

DIS_EFUSECLK

R/W

Internal. Only to be used through TI provided API.

DIS_READACCESS

R/W

Internal. Only to be used through TI provided API.

ENABLE_SWINTF

R/W

Internal. Only to be used through TI provided API.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIS_STANDBY

R/W

Internal. Only to be used through TI provided API.

DIS_IDLE

R/W

Internal. Only to be used through TI provided API.

31-9
8
7-6

568

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.3

SYSCODE_START Register (Offset = 28h) [reset = 0h]

SYSCODE_START is shown in Figure 7-11 and described in Table 7-6.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-11. SYSCODE_START Register
31

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

3
2
1
SYSCODE_START
R/W-0h

Table 7-6. SYSCODE_START Register Field Descriptions
Field

Type

Reset

Description

31-5

Bit

RESERVED

Internal. Only to be used through TI provided API.

4-0

SYSCODE_START

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

569

VIMS Registers

7.9.1.4

www.ti.com

FLASH_SIZE Register (Offset = 2Ch) [reset = 0h]

FLASH_SIZE is shown in Figure 7-12 and described in Table 7-7.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-12. FLASH_SIZE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
SECTORS
R/W-0h

Table 7-7. FLASH_SIZE Register Field Descriptions
Bit

570

Field

Type

Reset

Description

31-8

RESERVED

Internal. Only to be used through TI provided API.

7-0

SECTORS

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.5

FWLOCK Register (Offset = 3Ch) [reset = 0h]

FWLOCK is shown in Figure 7-13 and described in Table 7-8.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-13. FWLOCK Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
FWLOCK
R/W-0h

Table 7-8. FWLOCK Register Field Descriptions
Field

Type

Reset

Description

31-3

Bit

RESERVED

Internal. Only to be used through TI provided API.

2-0

FWLOCK

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

571

VIMS Registers

7.9.1.6

www.ti.com

FWFLAG Register (Offset = 40h) [reset = 0h]

FWFLAG is shown in Figure 7-14 and described in Table 7-9.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-14. FWFLAG Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
FWFLAG
R/W-0h

Table 7-9. FWFLAG Register Field Descriptions
Bit

572

Field

Type

Reset

Description

31-3

RESERVED

Internal. Only to be used through TI provided API.

2-0

FWFLAG

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.7

EFUSE Register (Offset = 1000h) [reset = 0h]

EFUSE is shown in Figure 7-15 and described in Table 7-10.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-15. EFUSE Register
31

30
29
RESERVED
R-0h

27
26
25
INSTRUCTION
R/W-0h

8
7
DUMPWORD
R/W-0h

20
19
RESERVED
R-0h
4

Table 7-10. EFUSE Register Field Descriptions
Field

Type

Reset

Description

31-29

Bit

RESERVED

Internal. Only to be used through TI provided API.

28-24

INSTRUCTION

R/W

Internal. Only to be used through TI provided API.

23-16

RESERVED

Internal. Only to be used through TI provided API.

15-0

DUMPWORD

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

573

VIMS Registers

7.9.1.8

www.ti.com

EFUSEADDR Register (Offset = 1004h) [reset = 0h]

EFUSEADDR is shown in Figure 7-16 and described in Table 7-11.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-16. EFUSEADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
BLOCK
R-0h
R/W-0h

5 4
ROW
R/W-0h

Table 7-11. EFUSEADDR Register Field Descriptions
Bit

574

Field

Type

Reset

Description

31-16

RESERVED

Internal. Only to be used through TI provided API.

15-11

BLOCK

R/W

Internal. Only to be used through TI provided API.

10-0

ROW

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.9

DATAUPPER Register (Offset = 1008h) [reset = 0h]

DATAUPPER is shown in Figure 7-17 and described in Table 7-12.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-17. DATAUPPER Register
31

12
11
RESERVED
R-0h

24
23
RESERVED
R-0h
8

5
SPARE
R/W-0h

2
P
R/W0h

1
R
R/W0h

0
EEN
R/W0h

Table 7-12. DATAUPPER Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Internal. Only to be used through TI provided API.

7-3

SPARE

R/W

Internal. Only to be used through TI provided API.

R/W

Internal. Only to be used through TI provided API.

R/W

Internal. Only to be used through TI provided API.

EEN

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

575

VIMS Registers

www.ti.com

7.9.1.10 DATALOWER Register (Offset = 100Ch) [reset = 0h]
DATALOWER is shown in Figure 7-18 and described in Table 7-13.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-18. DATALOWER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA
R/W-0h

Table 7-13. DATALOWER Register Field Descriptions

576

Bit

Field

Type

Reset

Description

31-0

DATA

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.11 EFUSECFG Register (Offset = 1010h) [reset = 1h]
EFUSECFG is shown in Figure 7-19 and described in Table 7-14.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-19. EFUSECFG Register
31

8
IDLEGATING
R/W-0h

0
GATING
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

6
RESERVED
R-0h

SLAVEPOWER
R/W-0h

RESERVED
R-0h

Table 7-14. EFUSECFG Register Field Descriptions
Bit

Field

Type

Reset

Description

31-9

RESERVED

Internal. Only to be used through TI provided API.

IDLEGATING

R/W

Internal. Only to be used through TI provided API.

7-5

RESERVED

Internal. Only to be used through TI provided API.

4-3

SLAVEPOWER

R/W

Internal. Only to be used through TI provided API.

2-1

RESERVED

Internal. Only to be used through TI provided API.

GATING

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

577

VIMS Registers

www.ti.com

7.9.1.12 EFUSESTAT Register (Offset = 1014h) [reset = 1h]
EFUSESTAT is shown in Figure 7-20 and described in Table 7-15.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-20. EFUSESTAT Register
31

0
RESETDONE
R-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 7-15. EFUSESTAT Register Field Descriptions
Bit
31-1
0

578

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

RESETDONE

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.13 ACC Register (Offset = 1018h) [reset = 0h]
ACC is shown in Figure 7-21 and described in Table 7-16.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-21. ACC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
RESERVED
ACCUMULATOR
R-0h
R-0h

Table 7-16. ACC Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

Internal. Only to be used through TI provided API.

23-0

ACCUMULATOR

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

579

VIMS Registers

www.ti.com

7.9.1.14 BOUNDARY Register (Offset = 101Ch) [reset = 0h]
BOUNDARY is shown in Figure 7-22 and described in Table 7-17.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-22. BOUNDARY Register
31

RESERVED
R-0h
23
DISROW0

22
SPARE

R/W-0h

15
14
OUTPUTENABLE
R/W-0h
7

21
20
19
EFC_SELF_TE EFC_INSTRUC EFC_INSTRUC
ST_ERROR
TION_INFO
TION_ERROR
R/W-0h
R/W-0h
R/W-0h

18
EFC_AUTOLO
AD_ERROR
R/W-0h

17
16
OUTPUTENABLE

13
12
SYS_ECC_SEL SYS_ECC_OV
F_TEST_EN
ERRIDE_EN
R/W-0h
R/W-0h

9
8
SYS_REPAIR_EN

R/W-0h

10
SYS_DIEID_A
UTOLOAD_EN
R/W-0h

6
5
SYS_WS_READ_STATES
R/W-0h

11
EFC_FDI

R/W-0h

R/W-0h
1

INPUTENABLE
R/W-0h

Table 7-17. BOUNDARY Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

DISROW0

R/W

Internal. Only to be used through TI provided API.

SPARE

R/W

Internal. Only to be used through TI provided API.

EFC_SELF_TEST_ERRO R/W
R

Internal. Only to be used through TI provided API.

EFC_INSTRUCTION_INF
O

R/W

Internal. Only to be used through TI provided API.

EFC_INSTRUCTION_ER
ROR

R/W

Internal. Only to be used through TI provided API.

EFC_AUTOLOAD_ERRO
R

R/W

Internal. Only to be used through TI provided API.

OUTPUTENABLE

R/W

Internal. Only to be used through TI provided API.

SYS_ECC_SELF_TEST_
EN

R/W

Internal. Only to be used through TI provided API.

SYS_ECC_OVERRIDE_E R/W
N

Internal. Only to be used through TI provided API.

EFC_FDI

R/W

Internal. Only to be used through TI provided API.

SYS_DIEID_AUTOLOAD_ R/W
EN

Internal. Only to be used through TI provided API.

9-8

SYS_REPAIR_EN

R/W

Internal. Only to be used through TI provided API.

7-4

SYS_WS_READ_STATE
S

R/W

Internal. Only to be used through TI provided API.

3-0

INPUTENABLE

R/W

Internal. Only to be used through TI provided API.

31-24

17-14

580

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.15 EFUSEFLAG Register (Offset = 1020h) [reset = 0h]
EFUSEFLAG is shown in Figure 7-23 and described in Table 7-18.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-23. EFUSEFLAG Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
KEY
R-0h

Table 7-18. EFUSEFLAG Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

KEY

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

581

VIMS Registers

www.ti.com

7.9.1.16 EFUSEKEY Register (Offset = 1024h) [reset = 0h]
EFUSEKEY is shown in Figure 7-24 and described in Table 7-19.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-24. EFUSEKEY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CODE
R/W-0h

Table 7-19. EFUSEKEY Register Field Descriptions

582

Bit

Field

Type

Reset

Description

31-0

CODE

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.17 EFUSERELEASE Register (Offset = 1028h) [reset = X]
EFUSERELEASE is shown in Figure 7-25 and described in Table 7-20.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-25. EFUSERELEASE Register
31

28
27
ODPYEAR
R-X

23
22
ODPMONTH
R-X

12
11
EFUSEYEAR
R-X

7
6
EFUSEMONTH
R-X

18
ODPDAY
R-X

2
1
EFUSEDAY
R-X

Table 7-20. EFUSERELEASE Register Field Descriptions
Field

Type

Reset

Description

31-25

Bit

ODPYEAR

Internal. Only to be used through TI provided API.

24-21

ODPMONTH

Internal. Only to be used through TI provided API.

20-16

ODPDAY

Internal. Only to be used through TI provided API.

15-9

EFUSEYEAR

Internal. Only to be used through TI provided API.

8-5

EFUSEMONTH

Internal. Only to be used through TI provided API.

4-0

EFUSEDAY

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

583

VIMS Registers

www.ti.com

7.9.1.18 EFUSEPINS Register (Offset = 102Ch) [reset = X]
EFUSEPINS is shown in Figure 7-26 and described in Table 7-21.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-26. EFUSEPINS Register
31

10
EFC_AUTOLO
AD_ERROR
R-X

9
SYS_ECC_OV
ERRIDE_EN
R-X

8
EFC_READY

RESERVED
R-0h
23

20
RESERVED
R-0h

15
14
13
12
11
EFC_SELF_TE EFC_SELF_TE SYS_ECC_SEL EFC_INSTRUC EFC_INSTRUC
ST_DONE
ST_ERROR
F_TEST_EN
TION_INFO
TION_ERROR
R-X
R-X
R-X
R-X
R-X
7
EFC_FCLRZ
R-X

6
SYS_DIEID_A
UTOLOAD_EN
R-X

5
4
SYS_REPAIR_EN

2
1
SYS_WS_READ_STATES

R-X

R-X
0

R-X

Table 7-21. EFUSEPINS Register Field Descriptions
Bit
31-16

584

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

EFC_SELF_TEST_DONE R

Internal. Only to be used through TI provided API.

EFC_SELF_TEST_ERRO R
R

Internal. Only to be used through TI provided API.

SYS_ECC_SELF_TEST_
EN

Internal. Only to be used through TI provided API.

EFC_INSTRUCTION_INF
O

Internal. Only to be used through TI provided API.

EFC_INSTRUCTION_ER
ROR

Internal. Only to be used through TI provided API.

EFC_AUTOLOAD_ERRO
R

Internal. Only to be used through TI provided API.

SYS_ECC_OVERRIDE_E R
N

Internal. Only to be used through TI provided API.

EFC_READY

Internal. Only to be used through TI provided API.

EFC_FCLRZ

Internal. Only to be used through TI provided API.

SYS_DIEID_AUTOLOAD_ R
EN

Internal. Only to be used through TI provided API.

5-4

SYS_REPAIR_EN

Internal. Only to be used through TI provided API.

3-0

SYS_WS_READ_STATE
S

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.19 EFUSECRA Register (Offset = 1030h) [reset = 0h]
EFUSECRA is shown in Figure 7-27 and described in Table 7-22.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-27. EFUSECRA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2 1
DATA
R/W-0h

Table 7-22. EFUSECRA Register Field Descriptions
Field

Type

Reset

Description

31-6

Bit

RESERVED

Internal. Only to be used through TI provided API.

5-0

DATA

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

585

VIMS Registers

www.ti.com

7.9.1.20 EFUSEREAD Register (Offset = 1034h) [reset = 0h]
EFUSEREAD is shown in Figure 7-28 and described in Table 7-23.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-28. EFUSEREAD Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

8
DATABIT
R/W-0h

READCLOCK
R/W-0h

3
DEBUG
R/W-0h

2
SPARE
R/W-0h

0
MARGIN
R/W-0h

Table 7-23. EFUSEREAD Register Field Descriptions
Bit
31-10

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

9-8

DATABIT

R/W

Internal. Only to be used through TI provided API.

7-4

READCLOCK

R/W

Internal. Only to be used through TI provided API.

DEBUG

R/W

Internal. Only to be used through TI provided API.

SPARE

R/W

Internal. Only to be used through TI provided API.

MARGIN

R/W

Internal. Only to be used through TI provided API.

1-0

586

Field

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.21 EFUSEPROGRAM Register (Offset = 1038h) [reset = 0h]
EFUSEPROGRAM is shown in Figure 7-29 and described in Table 7-24.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-29. EFUSEPROGRAM Register
31
RESERVED

R-0h

30
COMPAREDIS
ABLE
R/W-0h

8
WRITECLOCK
R/W-0h

CLOCKSTALL
R/W-0h
20

19
CLOCKSTALL
R/W-0h

14
CLOCKSTALL
R/W-0h

13
VPPTOVDD
R/W-0h

11
ITERATIONS
R/W-0h
3
WRITECLOCK
R/W-0h

Table 7-24. EFUSEPROGRAM Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

COMPAREDISABLE

R/W

Internal. Only to be used through TI provided API.

29-14

CLOCKSTALL

R/W

Internal. Only to be used through TI provided API.

VPPTOVDD

R/W

Internal. Only to be used through TI provided API.

12-9

ITERATIONS

R/W

Internal. Only to be used through TI provided API.

8-0

WRITECLOCK

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

587

VIMS Registers

www.ti.com

7.9.1.22 EFUSEERROR Register (Offset = 103Ch) [reset = 0h]
EFUSEERROR is shown in Figure 7-30 and described in Table 7-25.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-30. EFUSEERROR Register
31

2
CODE
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

6
RESERVED
R-0h

5
DONE
R/W-0h

Table 7-25. EFUSEERROR Register Field Descriptions
Bit
31-6

588

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

DONE

R/W

Internal. Only to be used through TI provided API.

4-0

CODE

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.23 SINGLEBIT Register (Offset = 1040h) [reset = 0h]
SINGLEBIT is shown in Figure 7-31 and described in Table 7-26.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-31. SINGLEBIT Register
31

0
FROM0
R-0h

FROMN
R-0h
23

20
FROMN
R-0h

12
FROMN
R-0h

4
FROMN
R-0h

Table 7-26. SINGLEBIT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-1

FROMN

Internal. Only to be used through TI provided API.

FROM0

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

589

VIMS Registers

www.ti.com

7.9.1.24 TWOBIT Register (Offset = 1044h) [reset = 0h]
TWOBIT is shown in Figure 7-32 and described in Table 7-27.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-32. TWOBIT Register
31

0
FROM0
R-0h

FROMN
R-0h
23

20
FROMN
R-0h

12
FROMN
R-0h

4
FROMN
R-0h

Table 7-27. TWOBIT Register Field Descriptions
Bit

590

Field

Type

Reset

Description

31-1

FROMN

Internal. Only to be used through TI provided API.

FROM0

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.25 SELFTESTCYC Register (Offset = 1048h) [reset = 0h]
SELFTESTCYC is shown in Figure 7-33 and described in Table 7-28.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-33. SELFTESTCYC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CYCLES
R/W-0h

Table 7-28. SELFTESTCYC Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

CYCLES

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

591

VIMS Registers

www.ti.com

7.9.1.26 SELFTESTSIGN Register (Offset = 104Ch) [reset = 0h]
SELFTESTSIGN is shown in Figure 7-34 and described in Table 7-29.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-34. SELFTESTSIGN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SIGNATURE
R/W-0h

Table 7-29. SELFTESTSIGN Register Field Descriptions
Bit
31-0

592

Field

Type

Reset

Description

SIGNATURE

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.27 FRDCTL Register (Offset = 2000h) [reset = 200h]
FRDCTL is shown in Figure 7-35 and described in Table 7-30.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-35. FRDCTL Register
31

14
13
RESERVED
R-0h

10
9
RWAIT
R/W-2h

24
23
RESERVED
R-0h
8

RM
R-0h

Table 7-30. FRDCTL Register Field Descriptions
Field

Type

Reset

Description

31-12

Bit

RESERVED

Internal. Only to be used through TI provided API.

11-8

RWAIT

R/W

Internal. Only to be used through TI provided API.

7-0

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

593

VIMS Registers

www.ti.com

7.9.1.28 FSPRD Register (Offset = 2004h) [reset = 0h]
FSPRD is shown in Figure 7-36 and described in Table 7-31.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-36. FSPRD Register
31

12
11
RMBSEM
R/W-0h

24
23
DIS_PREEMPT
R-0h
8

5
4
RESERVED
R-0h

1
RM1
R/W0h

0
RM0
R/W0h

Table 7-31. FSPRD Register Field Descriptions
Bit

594

Field

Type

Reset

Description

31-16

DIS_PREEMPT

Internal. Only to be used through TI provided API.

15-8

RMBSEM

R/W

Internal. Only to be used through TI provided API.

7-2

RESERVED

Internal. Only to be used through TI provided API.

RM1

R/W

Internal. Only to be used through TI provided API.

RM0

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.29 FEDACCTL1 Register (Offset = 2008h) [reset = 0h]
FEDACCTL1 is shown in Figure 7-37 and described in Table 7-32.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-37. FEDACCTL1 Register
31

28
RESERVED
R-0h

24
SUSP_IGNR
R/W-0h

EDACEN
R-0h
15

12
EDACEN
R-0h

4
EDACEN
R-0h

Table 7-32. FEDACCTL1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-25

RESERVED

Internal. Only to be used through TI provided API.

SUSP_IGNR

R/W

Internal. Only to be used through TI provided API.

EDACEN

Internal. Only to be used through TI provided API.

23-0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

595

VIMS Registers

www.ti.com

7.9.1.30 FEDACSTAT Register (Offset = 201Ch) [reset = 0h]
FEDACSTAT is shown in Figure 7-38 and described in Table 7-33.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-38. FEDACSTAT Register
31

25
RVF_INT
R/W1C-0h

24
FSM_DONE
R/W1C-0h

RESERVED
R-0h
23

20
19
ERR_PRF_FLG
R-0h

12
11
ERR_PRF_FLG
R-0h

3
ERR_PRF_FLG
R-0h

Table 7-33. FEDACSTAT Register Field Descriptions
Bit
31-26

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

RVF_INT

R/W1C

Internal. Only to be used through TI provided API.

FSM_DONE

R/W1C

Internal. Only to be used through TI provided API.

ERR_PRF_FLG

Internal. Only to be used through TI provided API.

23-0

596

Field

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.31 FBPROT Register (Offset = 2030h) [reset = 0h]
FBPROT is shown in Figure 7-39 and described in Table 7-34.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-39. FBPROT Register
31

0
PROTL1DIS
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 7-34. FBPROT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-1

RESERVED

Internal. Only to be used through TI provided API.

PROTL1DIS

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

597

VIMS Registers

www.ti.com

7.9.1.32 FBSE Register (Offset = 2034h) [reset = 0h]
FBSE is shown in Figure 7-40 and described in Table 7-35.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-40. FBSE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
BSE
R/W-0h

Table 7-35. FBSE Register Field Descriptions
Bit

598

Field

Type

Reset

Description

31-16

RESERVED

Internal. Only to be used through TI provided API.

15-0

BSE

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.33 FBBUSY Register (Offset = 2038h) [reset = FEh]
FBBUSY is shown in Figure 7-41 and described in Table 7-36.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-41. FBBUSY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3
BUSY
R-FEh

Table 7-36. FBBUSY Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Internal. Only to be used through TI provided API.

7-0

BUSY

FEh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

599

VIMS Registers

www.ti.com

7.9.1.34 FBAC Register (Offset = 203Ch) [reset = Fh]
FBAC is shown in Figure 7-42 and described in Table 7-37.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-42. FBAC Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

16
OTPPROTDIS
R/W-0h

BAGP
R/W-0h
7

4
VREADS
R/W-Fh

Table 7-37. FBAC Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

OTPPROTDIS

R/W

Internal. Only to be used through TI provided API.

15-8

BAGP

R/W

Internal. Only to be used through TI provided API.

7-0

VREADS

R/W

Internal. Only to be used through TI provided API.

31-17
16

600

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.35 FBFALLBACK Register (Offset = 2040h) [reset = 0505FFFFh]
FBFALLBACK is shown in Figure 7-43 and described in Table 7-38.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-43. FBFALLBACK Register
31

26
25
FSM_PWRSAV
R/W-5h

18
17
REG_PWRSAV
R/W-5h

RESERVED
R-0h
23

22
RESERVED
R-0h

BANKPWR7
R/W-3h
7

BANKPWR6
R/W-3h
6

BANKPWR3
R/W-3h

BANKPWR5
R/W-3h
4

BANKPWR2
R/W-3h

8
BANKPWR4
R/W-3h

2
BANKPWR1
R/W-3h

0
BANKPWR0
R/W-3h

Table 7-38. FBFALLBACK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-28

RESERVED

Internal. Only to be used through TI provided API.

27-24

FSM_PWRSAV

R/W

Internal. Only to be used through TI provided API.

23-20

RESERVED

Internal. Only to be used through TI provided API.

19-16

REG_PWRSAV

R/W

Internal. Only to be used through TI provided API.

15-14

BANKPWR7

R/W

Internal. Only to be used through TI provided API.

13-12

BANKPWR6

R/W

Internal. Only to be used through TI provided API.

11-10

BANKPWR5

R/W

Internal. Only to be used through TI provided API.

9-8

BANKPWR4

R/W

Internal. Only to be used through TI provided API.

7-6

BANKPWR3

R/W

Internal. Only to be used through TI provided API.

5-4

BANKPWR2

R/W

Internal. Only to be used through TI provided API.

3-2

BANKPWR1

R/W

Internal. Only to be used through TI provided API.

1-0

BANKPWR0

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

601

VIMS Registers

www.ti.com

7.9.1.36 FBPRDY Register (Offset = 2044h) [reset = 00FF00FEh]
FBPRDY is shown in Figure 7-44 and described in Table 7-39.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-44. FBPRDY Register
31

RESERVED
R-7Fh
23

20
RESERVED
R-7Fh

16
BANKBUSY
R-1h

15
PUMPRDY
R-0h

11
RESERVED
R-7Fh

4
RESERVED
R-7Fh

0
BANKRDY
R-0h

Table 7-39. FBPRDY Register Field Descriptions
Bit

Field

Type

Reset

Description

31-17

RESERVED

7Fh

Internal. Only to be used through TI provided API.

BANKBUSY

Internal. Only to be used through TI provided API.

PUMPRDY

Internal. Only to be used through TI provided API.

14-1

RESERVED

7Fh

Internal. Only to be used through TI provided API.

BANKRDY

Internal. Only to be used through TI provided API.

602

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.37 FPAC1 Register (Offset = 2048h) [reset = 02082081h]
FPAC1 is shown in Figure 7-45 and described in Table 7-40.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-45. FPAC1 Register
31

RESERVED
R-0h
23

PSLEEPTDIS
R/W-208h
21

12
11
PUMPRESET_PW
R/W-208h

PSLEEPTDIS
R/W-208h
15

6
5
PUMPRESET_PW
R/W-208h

3
RESERVED
R-0h

0
PUMPPWR
R/W-1h

Table 7-40. FPAC1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-28

RESERVED

Internal. Only to be used through TI provided API.

27-16

PSLEEPTDIS

R/W

208h

Internal. Only to be used through TI provided API.

15-4

PUMPRESET_PW

R/W

208h

Internal. Only to be used through TI provided API.

3-2

RESERVED

Internal. Only to be used through TI provided API.

1-0

PUMPPWR

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

603

VIMS Registers

www.ti.com

7.9.1.38 FPAC2 Register (Offset = 204Ch) [reset = 0h]
FPAC2 is shown in Figure 7-46 and described in Table 7-41.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-46. FPAC2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
PAGP
R/W-0h

Table 7-41. FPAC2 Register Field Descriptions
Bit

604

Field

Type

Reset

Description

31-16

RESERVED

Internal. Only to be used through TI provided API.

15-0

PAGP

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.39 FMAC Register (Offset = 2050h) [reset = 0h]
FMAC is shown in Figure 7-47 and described in Table 7-42.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-47. FMAC Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
BANK
R/W-0h

Table 7-42. FMAC Register Field Descriptions
Field

Type

Reset

Description

31-3

Bit

RESERVED

Internal. Only to be used through TI provided API.

2-0

BANK

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

605

VIMS Registers

www.ti.com

7.9.1.40 FMSTAT Register (Offset = 2054h) [reset = 0h]
FMSTAT is shown in Figure 7-48 and described in Table 7-43.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-48. FMSTAT Register
31

17
RVSUSP
R-0h

16
RDVER
R-0h

RESERVED
R-0h
23

21
RESERVED
R-0h

15
RVF
R-0h

14
ILA
R-0h

13
DBF
R-0h

12
PGV
R-0h

11
PCV
R-0h

10
EV
R-0h

9
CV
R-0h

8
BUSY
R-0h

7
ERS
R-0h

6
PGM
R-0h

5
INVDAT
R-0h

4
CSTAT
R-0h

3
VOLSTAT
R-0h

2
ESUSP
R-0h

1
PSUSP
R-0h

0
SLOCK
R-0h

Table 7-43. FMSTAT Register Field Descriptions
Bit
31-18

606

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

RVSUSP

Internal. Only to be used through TI provided API.

RDVER

Internal. Only to be used through TI provided API.

RVF

Internal. Only to be used through TI provided API.

ILA

Internal. Only to be used through TI provided API.

DBF

Internal. Only to be used through TI provided API.

PGV

Internal. Only to be used through TI provided API.

PCV

Internal. Only to be used through TI provided API.

BUSY

Internal. Only to be used through TI provided API.

ERS

Internal. Only to be used through TI provided API.

PGM

Internal. Only to be used through TI provided API.

INVDAT

Internal. Only to be used through TI provided API.

CSTAT

Internal. Only to be used through TI provided API.

VOLSTAT

Internal. Only to be used through TI provided API.

ESUSP

Internal. Only to be used through TI provided API.

PSUSP

Internal. Only to be used through TI provided API.

SLOCK

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.41 FLOCK Register (Offset = 2064h) [reset = 55AAh]
FLOCK is shown in Figure 7-49 and described in Table 7-44.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-49. FLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
ENCOM
R/W-55AAh

Table 7-44. FLOCK Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Internal. Only to be used through TI provided API.

15-0

ENCOM

R/W

55AAh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

607

VIMS Registers

www.ti.com

7.9.1.42 FVREADCT Register (Offset = 2080h) [reset = 8h]
FVREADCT is shown in Figure 7-50 and described in Table 7-45.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-50. FVREADCT Register
31

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

2
1
VREADCT
R/W-8h

Table 7-45. FVREADCT Register Field Descriptions
Bit

608

Field

Type

Reset

Description

31-4

RESERVED

Internal. Only to be used through TI provided API.

3-0

VREADCT

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.43 FVHVCT1 Register (Offset = 2084h) [reset = 00840088h]
FVHVCT1 is shown in Figure 7-51 and described in Table 7-46.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-51. FVHVCT1 Register
31

28
27
RESERVED
R-0h

22
21
TRIM13_E
R/W-8h

18
17
VHVCT_E
R/W-4h

12
11
RESERVED
R-0h

6
5
TRIM13_PV
R/W-8h

2
1
VHVCT_PV
R/W-8h

Table 7-46. FVHVCT1 Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

Internal. Only to be used through TI provided API.

23-20

TRIM13_E

R/W

Internal. Only to be used through TI provided API.

19-16

VHVCT_E

R/W

Internal. Only to be used through TI provided API.

15-8

RESERVED

Internal. Only to be used through TI provided API.

7-4

TRIM13_PV

R/W

Internal. Only to be used through TI provided API.

3-0

VHVCT_PV

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

609

VIMS Registers

www.ti.com

7.9.1.44 FVHVCT2 Register (Offset = 2088h) [reset = 00A20000h]
FVHVCT2 is shown in Figure 7-52 and described in Table 7-47.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-52. FVHVCT2 Register
31

28
27
RESERVED
R-0h

8
7
RESERVED
R-0h

22
21
TRIM13_P
R/W-Ah

18
17
VHVCT_P
R/W-2h

Table 7-47. FVHVCT2 Register Field Descriptions
Bit

610

Field

Type

Reset

Description

31-24

RESERVED

Internal. Only to be used through TI provided API.

23-20

TRIM13_P

R/W

Internal. Only to be used through TI provided API.

19-16

VHVCT_P

R/W

Internal. Only to be used through TI provided API.

15-0

RESERVED

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.45 FVHVCT3 Register (Offset = 208Ch) [reset = 000F0000h]
FVHVCT3 is shown in Figure 7-53 and described in Table 7-48.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-53. FVHVCT3 Register
31

26
25
RESERVED
R-0h

10
9
RESERVED
R-0h

17
WCT
R/W-Fh

2
1
VHVCT_READ
R/W-0h

Table 7-48. FVHVCT3 Register Field Descriptions
Field

Type

Reset

Description

31-20

Bit

RESERVED

Internal. Only to be used through TI provided API.

19-16

WCT

R/W

Internal. Only to be used through TI provided API.

15-4

RESERVED

Internal. Only to be used through TI provided API.

3-0

VHVCT_READ

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

611

VIMS Registers

www.ti.com

7.9.1.46 FVNVCT Register (Offset = 2090h) [reset = 800h]
FVNVCT is shown in Figure 7-54 and described in Table 7-49.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-54. FVNVCT Register
31

14
13
RESERVED
R-0h

10
VCG2P5CT
R/W-8h

24
23
RESERVED
R-0h
8

6
5
RESERVED
R-0h

2
VIN_CT
R/W-0h

Table 7-49. FVNVCT Register Field Descriptions
Bit

612

Field

Type

Reset

Description

31-13

RESERVED

Internal. Only to be used through TI provided API.

12-8

VCG2P5CT

R/W

Internal. Only to be used through TI provided API.

7-5

RESERVED

Internal. Only to be used through TI provided API.

4-0

VIN_CT

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.47 FVSLP Register (Offset = 2094h) [reset = 8000h]
FVSLP is shown in Figure 7-55 and described in Table 7-50.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-55. FVSLP Register
31

14
13
VSL_P
R/W-8h

24
23
RESERVED
R-0h
8

6
5
RESERVED
R-0h

Table 7-50. FVSLP Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Internal. Only to be used through TI provided API.

15-12

VSL_P

R/W

Internal. Only to be used through TI provided API.

11-0

RESERVED

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

613

VIMS Registers

www.ti.com

7.9.1.48 FVWLCT Register (Offset = 2098h) [reset = 8h]
FVWLCT is shown in Figure 7-56 and described in Table 7-51.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-56. FVWLCT Register
31

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

2
VWLCT_P
R/W-8h

Table 7-51. FVWLCT Register Field Descriptions
Bit

614

Field

Type

Reset

Description

31-5

RESERVED

Internal. Only to be used through TI provided API.

4-0

VWLCT_P

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.49 FEFUSECTL Register (Offset = 209Ch) [reset = 0701010Ah]
FEFUSECTL is shown in Figure 7-57 and described in Table 7-52.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-57. FEFUSECTL Register
31

29
RESERVED
R-0h

25
CHAIN_SEL
R/W-7h

17
WRITE_EN
R/W-0h

16
BP_SEL
R/W-1h

8
EF_CLRZ
R/W-1h

RESERVED
R-0h
15

12
RESERVED
R-0h

6
RESERVED
R-0h

4
EF_TEST
R/W-0h

2
EFUSE_EN
R/W-Ah

Table 7-52. FEFUSECTL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-27

RESERVED

Internal. Only to be used through TI provided API.

26-24

CHAIN_SEL

R/W

Internal. Only to be used through TI provided API.

23-18

RESERVED

Internal. Only to be used through TI provided API.

WRITE_EN

R/W

Internal. Only to be used through TI provided API.

BP_SEL

R/W

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

EF_CLRZ

R/W

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

EF_TEST

R/W

Internal. Only to be used through TI provided API.

EFUSE_EN

R/W

Internal. Only to be used through TI provided API.

15-9
8
7-5
4
3-0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

615

VIMS Registers

www.ti.com

7.9.1.50 FEFUSESTAT Register (Offset = 20A0h) [reset = 0h]
FEFUSESTAT is shown in Figure 7-58 and described in Table 7-53.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-58. FEFUSESTAT Register
31

0
SHIFT_DONE
R/W1C-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 7-53. FEFUSESTAT Register Field Descriptions
Bit
31-1
0

616

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

SHIFT_DONE

R/W1C

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.51 FEFUSEDATA Register (Offset = 20A4h) [reset = 0h]
FEFUSEDATA is shown in Figure 7-59 and described in Table 7-54.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-59. FEFUSEDATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FEFUSEDATA
R/W-0h

Table 7-54. FEFUSEDATA Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

FEFUSEDATA

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

617

VIMS Registers

www.ti.com

7.9.1.52 FSEQPMP Register (Offset = 20A8h) [reset = 85080000h]
FSEQPMP is shown in Figure 7-60 and described in Table 7-55.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-60. FSEQPMP Register
31

RESERVED
R/W-8h
23

TRIM_3P4
R/W-5h
21

RESERVED
R-0h

TRIM_1P7
R/W-0h

TRIM_0P8
R/W-8h

15
RESERVED
R-0h

13
VIN_AT_X
R/W-0h

10
RESERVED
R-0h

8
VIN_BY_PASS
R/W-0h

SEQ_PUMP
R/W-0h

Table 7-55. FSEQPMP Register Field Descriptions
Bit

Field

Type

Reset

Description

31-28

RESERVED

R/W

Internal. Only to be used through TI provided API.

27-24

TRIM_3P4

R/W

Internal. Only to be used through TI provided API.

23-22

RESERVED

Internal. Only to be used through TI provided API.

21-20

TRIM_1P7

R/W

Internal. Only to be used through TI provided API.

19-16

TRIM_0P8

R/W

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

14-12

VIN_AT_X

R/W

Internal. Only to be used through TI provided API.

11-9

RESERVED

Internal. Only to be used through TI provided API.

VIN_BY_PASS

R/W

Internal. Only to be used through TI provided API.

SEQ_PUMP

R/W

Internal. Only to be used through TI provided API.

8
7-0

618

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.53 FBSTROBES Register (Offset = 2100h) [reset = 104h]
FBSTROBES is shown in Figure 7-61 and described in Table 7-56.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-61. FBSTROBES Register
31

28
RESERVED
R-0h

24
ECBIT
R/W-0h

21
RESERVED

18
RWAIT2_FLCL
K
R/W-0h

17
RWAIT_FLCLK

16
FLCLKEN

R/W-0h

R/W-0h
8
CTRLENZ
R/W-1h

R-0h
15

12
RESERVED
R-0h

7
RESERVED
R-0h

6
NOCOLRED
R/W-0h

5
PRECOL
R/W-0h

4
TI_OTP
R/W-0h

3
OTP
R/W-0h

2
TEZ
R/W-1h

0
RESERVED
R-0h

Table 7-56. FBSTROBES Register Field Descriptions
Bit
31-25
24
23-19

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

ECBIT

R/W

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

RWAIT2_FLCLK

R/W

Internal. Only to be used through TI provided API.

RWAIT_FLCLK

R/W

Internal. Only to be used through TI provided API.

FLCLKEN

R/W

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

CTRLENZ

R/W

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

NOCOLRED

R/W

Internal. Only to be used through TI provided API.

PRECOL

R/W

Internal. Only to be used through TI provided API.

TI_OTP

R/W

Internal. Only to be used through TI provided API.

OTP

R/W

Internal. Only to be used through TI provided API.

TEZ

R/W

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

15-9

1-0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

619

VIMS Registers

www.ti.com

7.9.1.54 FPSTROBES Register (Offset = 2104h) [reset = 103h]
FPSTROBES is shown in Figure 7-62 and described in Table 7-57.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-62. FPSTROBES Register
31

12
RESERVED
R-0h

8
EXECUTEZ
R/W-1h

1
V3PWRDNZ
R/W-1h

0
V5PWRDNZ
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

5
RESERVED
R-0h

Table 7-57. FPSTROBES Register Field Descriptions
Bit

620

Field

Type

Reset

Description

31-9

RESERVED

Internal. Only to be used through TI provided API.

EXECUTEZ

R/W

Internal. Only to be used through TI provided API.

7-2

RESERVED

Internal. Only to be used through TI provided API.

V3PWRDNZ

R/W

Internal. Only to be used through TI provided API.

V5PWRDNZ

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.55 FBMODE Register (Offset = 2108h) [reset = 0h]
FBMODE is shown in Figure 7-63 and described in Table 7-58.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-63. FBMODE Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
MODE
R/W-0h

Table 7-58. FBMODE Register Field Descriptions
Field

Type

Reset

Description

31-3

Bit

RESERVED

Internal. Only to be used through TI provided API.

2-0

MODE

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

621

VIMS Registers

www.ti.com

7.9.1.56 FTCR Register (Offset = 210Ch) [reset = 0h]
FTCR is shown in Figure 7-64 and described in Table 7-59.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-64. FTCR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
TCR
R/W-0h

Table 7-59. FTCR Register Field Descriptions
Bit

622

Field

Type

Reset

Description

31-7

RESERVED

Internal. Only to be used through TI provided API.

6-0

TCR

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.57 FADDR Register (Offset = 2110h) [reset = 0h]
FADDR is shown in Figure 7-65 and described in Table 7-60.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-65. FADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FADDR
R/W-0h

Table 7-60. FADDR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

FADDR

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

623

VIMS Registers

www.ti.com

7.9.1.58 FTCTL Register (Offset = 211Ch) [reset = 0h]
FTCTL is shown in Figure 7-66 and described in Table 7-61.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-66. FTCTL Register
31

16
WDATA_BLK_
CLR
R/W-0h

1
TEST_EN
R/W-0h

0
RESERVED
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 7-61. FTCTL Register Field Descriptions
Bit
31-17
16
15-2

624

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

WDATA_BLK_CLR

R/W

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

TEST_EN

R/W

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.59 FWPWRITE0 Register (Offset = 2120h) [reset = FFFFFFFFh]
FWPWRITE0 is shown in Figure 7-67 and described in Table 7-62.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-67. FWPWRITE0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FWPWRITE0
R/W-FFFFFFFFh

Table 7-62. FWPWRITE0 Register Field Descriptions
Bit
31-0

Field

Type

Reset

FWPWRITE0

R/W

FFFFFFFFh Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Versatile Instruction Memory System (VIMS)

625

VIMS Registers

www.ti.com

7.9.1.60 FWPWRITE1 Register (Offset = 2124h) [reset = FFFFFFFFh]
FWPWRITE1 is shown in Figure 7-68 and described in Table 7-63.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-68. FWPWRITE1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FWPWRITE1
R/W-FFFFFFFFh

Table 7-63. FWPWRITE1 Register Field Descriptions
Bit
31-0

626

Field

Type

Reset

FWPWRITE1

R/W

FFFFFFFFh Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

Description

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.61 FWPWRITE2 Register (Offset = 2128h) [reset = FFFFFFFFh]
FWPWRITE2 is shown in Figure 7-69 and described in Table 7-64.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-69. FWPWRITE2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FWPWRITE2
R/W-FFFFFFFFh

Table 7-64. FWPWRITE2 Register Field Descriptions
Bit
31-0

Field

Type

Reset

FWPWRITE2

R/W

FFFFFFFFh Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Versatile Instruction Memory System (VIMS)

627

VIMS Registers

www.ti.com

7.9.1.62 FWPWRITE3 Register (Offset = 212Ch) [reset = FFFFFFFFh]
FWPWRITE3 is shown in Figure 7-70 and described in Table 7-65.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-70. FWPWRITE3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FWPWRITE3
R/W-FFFFFFFFh

Table 7-65. FWPWRITE3 Register Field Descriptions
Bit
31-0

628

Field

Type

Reset

FWPWRITE3

R/W

FFFFFFFFh Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

Description

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.63 FWPWRITE4 Register (Offset = 2130h) [reset = FFFFFFFFh]
FWPWRITE4 is shown in Figure 7-71 and described in Table 7-66.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-71. FWPWRITE4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FWPWRITE4
R/W-FFFFFFFFh

Table 7-66. FWPWRITE4 Register Field Descriptions
Bit
31-0

Field

Type

Reset

FWPWRITE4

R/W

FFFFFFFFh Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Versatile Instruction Memory System (VIMS)

629

VIMS Registers

www.ti.com

7.9.1.64 FWPWRITE5 Register (Offset = 2134h) [reset = FFFFFFFFh]
FWPWRITE5 is shown in Figure 7-72 and described in Table 7-67.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-72. FWPWRITE5 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FWPWRITE5
R/W-FFFFFFFFh

Table 7-67. FWPWRITE5 Register Field Descriptions
Bit
31-0

630

Field

Type

Reset

FWPWRITE5

R/W

FFFFFFFFh Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

Description

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.65 FWPWRITE6 Register (Offset = 2138h) [reset = FFFFFFFFh]
FWPWRITE6 is shown in Figure 7-73 and described in Table 7-68.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-73. FWPWRITE6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FWPWRITE6
R/W-FFFFFFFFh

Table 7-68. FWPWRITE6 Register Field Descriptions
Bit
31-0

Field

Type

Reset

FWPWRITE6

R/W

FFFFFFFFh Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Versatile Instruction Memory System (VIMS)

631

VIMS Registers

www.ti.com

7.9.1.66 FWPWRITE7 Register (Offset = 213Ch) [reset = FFFFFFFFh]
FWPWRITE7 is shown in Figure 7-74 and described in Table 7-69.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-74. FWPWRITE7 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FWPWRITE7
R/W-FFFFFFFFh

Table 7-69. FWPWRITE7 Register Field Descriptions
Bit
31-0

632

Field

Type

Reset

FWPWRITE7

R/W

FFFFFFFFh Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

Description

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.67 FWPWRITE_ECC Register (Offset = 2140h) [reset = FFFFFFFFh]
FWPWRITE_ECC is shown in Figure 7-75 and described in Table 7-70.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-75. FWPWRITE_ECC Register
31

28
27
ECCBYTES07_00
R/W-FFh

20
19
ECCBYTES15_08
R/W-FFh

12
11
ECCBYTES23_16
R/W-FFh

4
3
ECCBYTES31_24
R/W-FFh

Table 7-70. FWPWRITE_ECC Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

ECCBYTES07_00

R/W

FFh

Internal. Only to be used through TI provided API.

23-16

ECCBYTES15_08

R/W

FFh

Internal. Only to be used through TI provided API.

15-8

ECCBYTES23_16

R/W

FFh

Internal. Only to be used through TI provided API.

7-0

ECCBYTES31_24

R/W

FFh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

633

VIMS Registers

www.ti.com

7.9.1.68 FSWSTAT Register (Offset = 2144h) [reset = 1h]
FSWSTAT is shown in Figure 7-76 and described in Table 7-71.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-76. FSWSTAT Register
31

0
SAFELV
R-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 7-71. FSWSTAT Register Field Descriptions
Bit
31-1
0

634

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

SAFELV

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.69 FSM_GLBCTL Register (Offset = 2200h) [reset = 1h]
FSM_GLBCTL is shown in Figure 7-77 and described in Table 7-72.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-77. FSM_GLBCTL Register
31

0
CLKSEL
R-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 7-72. FSM_GLBCTL Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

CLKSEL

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

635

VIMS Registers

www.ti.com

7.9.1.70 FSM_STATE Register (Offset = 2204h) [reset = C00h]
FSM_STATE is shown in Figure 7-78 and described in Table 7-73.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-78. FSM_STATE Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

11
CTRLENZ
R-1h

10
EXECUTEZ
R-1h

9
RESERVED
R-0h

8
FSM_ACT
R-0h

RESERVED
R-0h
7
TIOTP_ACT
R-0h

6
OTP_ACT
R-0h

RESERVED
R-0h

Table 7-73. FSM_STATE Register Field Descriptions
Bit
31-12

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

CTRLENZ

Internal. Only to be used through TI provided API.

EXECUTEZ

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

FSM_ACT

Internal. Only to be used through TI provided API.

TIOTP_ACT

Internal. Only to be used through TI provided API.

OTP_ACT

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

5-0

636

Field

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.71 FSM_STAT Register (Offset = 2208h) [reset = 4h]
FSM_STAT is shown in Figure 7-79 and described in Table 7-74.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-79. FSM_STAT Register
31

2
NON_OP

1
OVR_PUL_CN
T
R-0h

0
INV_DAT

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED

R-0h

R-1h

R-0h

Table 7-74. FSM_STAT Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

NON_OP

Internal. Only to be used through TI provided API.

OVR_PUL_CNT

Internal. Only to be used through TI provided API.

INV_DAT

Internal. Only to be used through TI provided API.

31-3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

637

VIMS Registers

www.ti.com

7.9.1.72 FSM_CMD Register (Offset = 220Ch) [reset = 0h]
FSM_CMD is shown in Figure 7-80 and described in Table 7-75.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-80. FSM_CMD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2 1
FSMCMD
R/W-0h

Table 7-75. FSM_CMD Register Field Descriptions
Bit

638

Field

Type

Reset

Description

31-6

RESERVED

Internal. Only to be used through TI provided API.

5-0

FSMCMD

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.73 FSM_PE_OSU Register (Offset = 2210h) [reset = 0h]
FSM_PE_OSU is shown in Figure 7-81 and described in Table 7-76.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-81. FSM_PE_OSU Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
PGM_OSU
R-0h
R/W-0h

4 3 2
ERA_OSU
R/W-0h

Table 7-76. FSM_PE_OSU Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Internal. Only to be used through TI provided API.

15-8

PGM_OSU

R/W

Internal. Only to be used through TI provided API.

7-0

ERA_OSU

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

639

VIMS Registers

www.ti.com

7.9.1.74 FSM_VSTAT Register (Offset = 2214h) [reset = 3000h]
FSM_VSTAT is shown in Figure 7-82 and described in Table 7-77.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-82. FSM_VSTAT Register
31

14
13
VSTAT_CNT
R/W-3h

24
23
RESERVED
R-0h
8

6
5
RESERVED
R-0h

Table 7-77. FSM_VSTAT Register Field Descriptions
Bit

640

Field

Type

Reset

Description

31-16

RESERVED

Internal. Only to be used through TI provided API.

15-12

VSTAT_CNT

R/W

Internal. Only to be used through TI provided API.

11-0

RESERVED

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.75 FSM_PE_VSU Register (Offset = 2218h) [reset = 0h]
FSM_PE_VSU is shown in Figure 7-83 and described in Table 7-78.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-83. FSM_PE_VSU Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
PGM_VSU
R-0h
R/W-0h

4 3 2
ERA_VSU
R/W-0h

Table 7-78. FSM_PE_VSU Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Internal. Only to be used through TI provided API.

15-8

PGM_VSU

R/W

Internal. Only to be used through TI provided API.

7-0

ERA_VSU

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

641

VIMS Registers

www.ti.com

7.9.1.76 FSM_CMP_VSU Register (Offset = 221Ch) [reset = 0h]
FSM_CMP_VSU is shown in Figure 7-84 and described in Table 7-79.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-84. FSM_CMP_VSU Register
31

14
13
ADD_EXZ
R/W-0h

24
23
RESERVED
R-0h
8

6
5
RESERVED
R-0h

Table 7-79. FSM_CMP_VSU Register Field Descriptions
Bit

642

Field

Type

Reset

Description

31-16

RESERVED

Internal. Only to be used through TI provided API.

15-12

ADD_EXZ

R/W

Internal. Only to be used through TI provided API.

11-0

RESERVED

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.77 FSM_EX_VAL Register (Offset = 2220h) [reset = 301h]
FSM_EX_VAL is shown in Figure 7-85 and described in Table 7-80.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-85. FSM_EX_VAL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
REP_VSU
R-0h
R/W-3h

4 3 2
EXE_VALD
R/W-1h

Table 7-80. FSM_EX_VAL Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Internal. Only to be used through TI provided API.

15-8

REP_VSU

R/W

Internal. Only to be used through TI provided API.

7-0

EXE_VALD

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

643

VIMS Registers

www.ti.com

7.9.1.78 FSM_RD_H Register (Offset = 2224h) [reset = 5Ah]
FSM_RD_H is shown in Figure 7-86 and described in Table 7-81.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-86. FSM_RD_H Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
RD_H
R/W-5Ah

Table 7-81. FSM_RD_H Register Field Descriptions
Bit

644

Field

Type

Reset

Description

31-8

RESERVED

Internal. Only to be used through TI provided API.

7-0

RD_H

R/W

5Ah

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.79 FSM_P_OH Register (Offset = 2228h) [reset = 100h]
FSM_P_OH is shown in Figure 7-87 and described in Table 7-82.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-87. FSM_P_OH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
PGM_OH
R-0h
R/W-1h

5 4 3 2
RESERVED
R-0h

Table 7-82. FSM_P_OH Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Internal. Only to be used through TI provided API.

15-8

PGM_OH

R/W

Internal. Only to be used through TI provided API.

7-0

RESERVED

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

645

VIMS Registers

www.ti.com

7.9.1.80 FSM_ERA_OH Register (Offset = 222Ch) [reset = 1h]
FSM_ERA_OH is shown in Figure 7-88 and described in Table 7-83.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-88. FSM_ERA_OH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
ERA_OH
R/W-1h

Table 7-83. FSM_ERA_OH Register Field Descriptions
Bit

646

Field

Type

Reset

Description

31-16

RESERVED

Internal. Only to be used through TI provided API.

15-0

ERA_OH

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.81 FSM_SAV_PPUL Register (Offset = 2230h) [reset = 0h]
FSM_SAV_PPUL is shown in Figure 7-89 and described in Table 7-84.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-89. FSM_SAV_PPUL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

7 6 5 4
SAV_P_PUL
R-0h

Table 7-84. FSM_SAV_PPUL Register Field Descriptions
Field

Type

Reset

Description

31-12

Bit

RESERVED

Internal. Only to be used through TI provided API.

11-0

SAV_P_PUL

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

647

VIMS Registers

www.ti.com

7.9.1.82 FSM_PE_VH Register (Offset = 2234h) [reset = 100h]
FSM_PE_VH is shown in Figure 7-90 and described in Table 7-85.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-90. FSM_PE_VH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
PGM_VH
R-0h
R/W-1h

4 3 2
ERA_VH
R-0h

Table 7-85. FSM_PE_VH Register Field Descriptions
Bit

648

Field

Type

Reset

Description

31-16

RESERVED

Internal. Only to be used through TI provided API.

15-8

PGM_VH

R/W

Internal. Only to be used through TI provided API.

7-0

ERA_VH

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.83 FSM_PRG_PW Register (Offset = 2240h) [reset = 0h]
FSM_PRG_PW is shown in Figure 7-91 and described in Table 7-86.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-91. FSM_PRG_PW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
RESERVED
PROG_PUL_WIDTH
R-0h
R/W-0h

Table 7-86. FSM_PRG_PW Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Internal. Only to be used through TI provided API.

15-0

PROG_PUL_WIDTH

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

649

VIMS Registers

www.ti.com

7.9.1.84 FSM_ERA_PW Register (Offset = 2244h) [reset = 0h]
FSM_ERA_PW is shown in Figure 7-92 and described in Table 7-87.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-92. FSM_ERA_PW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FSM_ERA_PW
R/W-0h

Table 7-87. FSM_ERA_PW Register Field Descriptions
Bit
31-0

650

Field

Type

Reset

Description

FSM_ERA_PW

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.85 FSM_SAV_ERA_PUL Register (Offset = 2254h) [reset = 0h]
FSM_SAV_ERA_PUL is shown in Figure 7-93 and described in Table 7-88.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-93. FSM_SAV_ERA_PUL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

7 6 5 4
SAV_ERA_PUL
R-0h

Table 7-88. FSM_SAV_ERA_PUL Register Field Descriptions
Field

Type

Reset

Description

31-12

Bit

RESERVED

Internal. Only to be used through TI provided API.

11-0

SAV_ERA_PUL

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

651

VIMS Registers

www.ti.com

7.9.1.86 FSM_TIMER Register (Offset = 2258h) [reset = 0h]
FSM_TIMER is shown in Figure 7-94 and described in Table 7-89.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-94. FSM_TIMER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FSM_TIMER
R-0h

Table 7-89. FSM_TIMER Register Field Descriptions
Bit
31-0

652

Field

Type

Reset

Description

FSM_TIMER

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.87 FSM_MODE Register (Offset = 225Ch) [reset = 0h]
FSM_MODE is shown in Figure 7-95 and described in Table 7-90.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-95. FSM_MODE Register
31

RESERVED
R-0h
23

19
18
RDV_SUBMODE
R-0h

17
16
PGM_SUBMODE
R-0h

8
SAV_ERA_MO
DE
R-0h

4
MODE
R-0h

1
CMD
R-0h

RESERVED
R-0h
15
14
ERA_SUBMODE

13
SUBMODE

R-0h
7
6
SAV_ERA_MODE
R-0h

R-0h
5

10
SAV_PGM_CMD
R-0h
2

Table 7-90. FSM_MODE Register Field Descriptions
Field

Type

Reset

Description

31-20

Bit

RESERVED

Internal. Only to be used through TI provided API.

19-18

RDV_SUBMODE

Internal. Only to be used through TI provided API.

17-16

PGM_SUBMODE

Internal. Only to be used through TI provided API.

15-14

ERA_SUBMODE

Internal. Only to be used through TI provided API.

13-12

SUBMODE

Internal. Only to be used through TI provided API.

11-9

SAV_PGM_CMD

Internal. Only to be used through TI provided API.

8-6

SAV_ERA_MODE

Internal. Only to be used through TI provided API.

5-3

MODE

Internal. Only to be used through TI provided API.

2-0

CMD

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

653

VIMS Registers

www.ti.com

7.9.1.88 FSM_PGM Register (Offset = 2260h) [reset = 0h]
FSM_PGM is shown in Figure 7-96 and described in Table 7-91.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-96. FSM_PGM Register
31

29
28
RESERVED
R-0h

24
23
PGM_BANK
R-0h
8
7
PGM_ADDR
R-0h

19
18
PGM_ADDR
R-0h
3

Table 7-91. FSM_PGM Register Field Descriptions
Bit

654

Field

Type

Reset

Description

31-26

RESERVED

Internal. Only to be used through TI provided API.

25-23

PGM_BANK

Internal. Only to be used through TI provided API.

22-0

PGM_ADDR

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.89 FSM_ERA Register (Offset = 2264h) [reset = 0h]
FSM_ERA is shown in Figure 7-97 and described in Table 7-92.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-97. FSM_ERA Register
31

29
28
RESERVED
R-0h

24
23
ERA_BANK
R-0h

8
7
ERA_ADDR
R-0h

19
18
ERA_ADDR
R-0h
3

Table 7-92. FSM_ERA Register Field Descriptions
Field

Type

Reset

Description

31-26

Bit

RESERVED

Internal. Only to be used through TI provided API.

25-23

ERA_BANK

Internal. Only to be used through TI provided API.

22-0

ERA_ADDR

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

655

VIMS Registers

www.ti.com

7.9.1.90 FSM_PRG_PUL Register (Offset = 2268h) [reset = 00040032h]
FSM_PRG_PUL is shown in Figure 7-98 and described in Table 7-93.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-98. FSM_PRG_PUL Register
31

26
25
RESERVED
R-0h

14
13
RESERVED
R-0h

6
5
MAX_PRG_PUL
R/W-32h

18
17
BEG_EC_LEVEL
R/W-4h
2

Table 7-93. FSM_PRG_PUL Register Field Descriptions
Bit

656

Field

Type

Reset

Description

31-20

RESERVED

Internal. Only to be used through TI provided API.

19-16

BEG_EC_LEVEL

R/W

Internal. Only to be used through TI provided API.

15-12

RESERVED

Internal. Only to be used through TI provided API.

11-0

MAX_PRG_PUL

R/W

32h

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.91 FSM_ERA_PUL Register (Offset = 226Ch) [reset = 00040BB8h]
FSM_ERA_PUL is shown in Figure 7-99 and described in Table 7-94.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-99. FSM_ERA_PUL Register
31

26
25
RESERVED
R-0h

14
13
RESERVED
R-0h

6
5
MAX_ERA_PUL
R/W-BB8h

18
17
MAX_EC_LEVEL
R/W-4h
2

Table 7-94. FSM_ERA_PUL Register Field Descriptions
Field

Type

Reset

Description

31-20

Bit

RESERVED

Internal. Only to be used through TI provided API.

19-16

MAX_EC_LEVEL

R/W

Internal. Only to be used through TI provided API.

15-12

RESERVED

Internal. Only to be used through TI provided API.

11-0

MAX_ERA_PUL

R/W

BB8h

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

657

VIMS Registers

www.ti.com

7.9.1.92 FSM_STEP_SIZE Register (Offset = 2270h) [reset = 0h]
FSM_STEP_SIZE is shown in Figure 7-100 and described in Table 7-95.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-100. FSM_STEP_SIZE Register
31

28
27
RESERVED
R-0h
12

21
20
19
EC_STEP_SIZE
R/W-0h

8
7
RESERVED
R-0h

Table 7-95. FSM_STEP_SIZE Register Field Descriptions
Bit

658

Field

Type

Reset

Description

31-25

RESERVED

Internal. Only to be used through TI provided API.

24-16

EC_STEP_SIZE

R/W

Internal. Only to be used through TI provided API.

15-0

RESERVED

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.93 FSM_PUL_CNTR Register (Offset = 2274h) [reset = 0h]
FSM_PUL_CNTR is shown in Figure 7-101 and described in Table 7-96.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-101. FSM_PUL_CNTR Register
31

14
13
RESERVED
R-0h

28
27
RESERVED
R-0h
12

21
20
19
CUR_EC_LEVEL
R-0h

6
5
PUL_CNTR
R-0h

Table 7-96. FSM_PUL_CNTR Register Field Descriptions
Field

Type

Reset

Description

31-25

Bit

RESERVED

Internal. Only to be used through TI provided API.

24-16

CUR_EC_LEVEL

Internal. Only to be used through TI provided API.

15-12

RESERVED

Internal. Only to be used through TI provided API.

11-0

PUL_CNTR

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

659

VIMS Registers

www.ti.com

7.9.1.94 FSM_EC_STEP_HEIGHT Register (Offset = 2278h) [reset = 0h]
FSM_EC_STEP_HEIGHT is shown in Figure 7-102 and described in Table 7-97.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-102. FSM_EC_STEP_HEIGHT Register
31

2
1
EC_STEP_HEIGHT
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

RESERVED
R-0h

Table 7-97. FSM_EC_STEP_HEIGHT Register Field Descriptions
Bit

660

Field

Type

Reset

Description

31-4

RESERVED

Internal. Only to be used through TI provided API.

3-0

EC_STEP_HEIGHT

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.95 FSM_ST_MACHINE Register (Offset = 227Ch) [reset = 00800500h]
FSM_ST_MACHINE is shown in Figure 7-103 and described in Table 7-98.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-103. FSM_ST_MACHINE Register
31

19
RANDOM

18
RV_SEC_EN

17
RV_RES

16
RV_INT_EN

R/W-0h

11
DO_REDU_CO
L
R/W-0h

9
DBG_SHORT_ROW

3
DIS_TST_EN

2
CMD_EN

1
INV_DATA

0
OVERRIDE

R/W-0h

RESERVED
R-0h
23
DO_PRECOND

22
FSM_INT_EN

21
ALL_BANKS

R/W-1h

R/W-0h

20
CMPV_ALLOW
ED
R/W-0h

15
RESERVED

14
ONE_TIME_G
OOD
R/W-0h

6
RESERVED

5
PGM_SEC_CO
F_EN
R/W-0h

R-0h
7
DBG_SHORT_
ROW
R/W-Ah

RESERVED
R-0h

R-0h

4
PREC_STOP_
EN
R/W-0h

R/W-Ah

Table 7-98. FSM_ST_MACHINE Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

DO_PRECOND

R/W

Internal. Only to be used through TI provided API.

FSM_INT_EN

R/W

Internal. Only to be used through TI provided API.

ALL_BANKS

R/W

Internal. Only to be used through TI provided API.

CMPV_ALLOWED

R/W

Internal. Only to be used through TI provided API.

RANDOM

R/W

Internal. Only to be used through TI provided API.

RV_SEC_EN

R/W

Internal. Only to be used through TI provided API.

RV_RES

R/W

Internal. Only to be used through TI provided API.

RV_INT_EN

R/W

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

ONE_TIME_GOOD

R/W

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

DO_REDU_COL

R/W

Internal. Only to be used through TI provided API.

DBG_SHORT_ROW

R/W

Internal. Only to be used through TI provided API.

RESERVED

Internal. Only to be used through TI provided API.

PGM_SEC_COF_EN

R/W

Internal. Only to be used through TI provided API.

PREC_STOP_EN

R/W

Internal. Only to be used through TI provided API.

DIS_TST_EN

R/W

Internal. Only to be used through TI provided API.

CMD_EN

R/W

Internal. Only to be used through TI provided API.

INV_DATA

R/W

Internal. Only to be used through TI provided API.

OVERRIDE

R/W

Internal. Only to be used through TI provided API.

31-24

13-12
11
10-7

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

661

VIMS Registers

www.ti.com

7.9.1.96 FSM_FLES Register (Offset = 2280h) [reset = 0h]
FSM_FLES is shown in Figure 7-104 and described in Table 7-99.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-104. FSM_FLES Register
31

14
13
RESERVED
R-0h

10
9
BLK_TIOTP
R/W-0h

24
23
RESERVED
R-0h
8

4
3
BLK_OTP
R/W-0h

Table 7-99. FSM_FLES Register Field Descriptions
Bit

662

Field

Type

Reset

Description

31-12

RESERVED

Internal. Only to be used through TI provided API.

11-8

BLK_TIOTP

R/W

Internal. Only to be used through TI provided API.

7-0

BLK_OTP

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.97 FSM_WR_ENA Register (Offset = 2288h) [reset = 2h]
FSM_WR_ENA is shown in Figure 7-105 and described in Table 7-100.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-105. FSM_WR_ENA Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
WR_ENA
R/W-2h

Table 7-100. FSM_WR_ENA Register Field Descriptions
Field

Type

Reset

Description

31-3

Bit

RESERVED

Internal. Only to be used through TI provided API.

2-0

WR_ENA

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

663

VIMS Registers

www.ti.com

7.9.1.98 FSM_ACC_PP Register (Offset = 228Ch) [reset = 0h]
FSM_ACC_PP is shown in Figure 7-106 and described in Table 7-101.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-106. FSM_ACC_PP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FSM_ACC_PP
R-0h

Table 7-101. FSM_ACC_PP Register Field Descriptions
Bit
31-0

664

Field

Type

Reset

Description

FSM_ACC_PP

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.99 FSM_ACC_EP Register (Offset = 2290h) [reset = 0h]
FSM_ACC_EP is shown in Figure 7-107 and described in Table 7-102.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-107. FSM_ACC_EP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
ACC_EP
R-0h

Table 7-102. FSM_ACC_EP Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Internal. Only to be used through TI provided API.

15-0

ACC_EP

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

665

VIMS Registers

www.ti.com

7.9.1.100 FSM_ADDR Register (Offset = 22A0h) [reset = 0h]
FSM_ADDR is shown in Figure 7-108 and described in Table 7-103.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-108. FSM_ADDR Register
31
RESERVED
R-0h

29
BANK
R-0h

CUR_ADDR
R-0h
19

CUR_ADDR
R-0h
15

12
CUR_ADDR
R-0h

4
CUR_ADDR
R-0h

Table 7-103. FSM_ADDR Register Field Descriptions

666

Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

30-28

BANK

Internal. Only to be used through TI provided API.

27-0

CUR_ADDR

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.101 FSM_SECTOR Register (Offset = 22A4h) [reset = FFFF0000h]
FSM_SECTOR is shown in Figure 7-109 and described in Table 7-104.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-109. FSM_SECTOR Register
31

13
12
11
10
FSM_SECTOR_EXTENSION
R-0h

24
23
SECT_ERASED
R/W-FFFFh
8

6
5
SECTOR
R-0h

2
1
SEC_OUT
R-0h

Table 7-104. FSM_SECTOR Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

SECT_ERASED

R/W

FFFFh

Internal. Only to be used through TI provided API.

15-8

FSM_SECTOR_EXTENSI R
ON

Internal. Only to be used through TI provided API.

7-4

SECTOR

Internal. Only to be used through TI provided API.

3-0

SEC_OUT

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

667

VIMS Registers

www.ti.com

7.9.1.102 FMC_REV_ID Register (Offset = 22A8h) [reset = X]
FMC_REV_ID is shown in Figure 7-110 and described in Table 7-105.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-110. FMC_REV_ID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MOD_VERSION
R-X

7 6 5 4
CONFIG_CRC
R-X

Table 7-105. FMC_REV_ID Register Field Descriptions
Bit

668

Field

Type

Reset

Description

31-12

MOD_VERSION

Internal. Only to be used through TI provided API.

11-0

CONFIG_CRC

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.103 FSM_ERR_ADDR Register (Offset = 22ACh) [reset = 0h]
FSM_ERR_ADDR is shown in Figure 7-111 and described in Table 7-106.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-111. FSM_ERR_ADDR Register
31

12
11
FSM_ERR_ADDR
R-0h

24
23
FSM_ERR_ADDR
R-0h
8

6
5
RESERVED
R-0h

2
1
FSM_ERR_BANK
R-0h

Table 7-106. FSM_ERR_ADDR Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

FSM_ERR_ADDR

Internal. Only to be used through TI provided API.

7-4

RESERVED

Internal. Only to be used through TI provided API.

3-0

FSM_ERR_BANK

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

669

VIMS Registers

www.ti.com

7.9.1.104 FSM_PGM_MAXPUL Register (Offset = 22B0h) [reset = 0h]
FSM_PGM_MAXPUL is shown in Figure 7-112 and described in Table 7-107.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-112. FSM_PGM_MAXPUL Register
31

14
13
RESERVED
R-0h

24
23
RESERVED
R-0h
8

6
5
4
FSM_PGM_MAXPUL
R-0h

Table 7-107. FSM_PGM_MAXPUL Register Field Descriptions
Bit

670

Field

Type

Reset

Description

31-12

RESERVED

Internal. Only to be used through TI provided API.

11-0

FSM_PGM_MAXPUL

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.105 FSM_EXECUTE Register (Offset = 22B4h) [reset = 000A000Ah]
FSM_EXECUTE is shown in Figure 7-113 and described in Table 7-108.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-113. FSM_EXECUTE Register
31

26
25
RESERVED
R-0h
10
9
RESERVED
R-0h

18
17
SUSPEND_NOW
R/W-Ah

2
1
FSMEXECUTE
R/W-Ah

Table 7-108. FSM_EXECUTE Register Field Descriptions
Field

Type

Reset

Description

31-20

Bit

RESERVED

Internal. Only to be used through TI provided API.

19-16

SUSPEND_NOW

R/W

Internal. Only to be used through TI provided API.

15-5

RESERVED

Internal. Only to be used through TI provided API.

4-0

FSMEXECUTE

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

671

VIMS Registers

www.ti.com

7.9.1.106 FSM_SECTOR1 Register (Offset = 22C0h) [reset = FFFFFFFFh]
FSM_SECTOR1 is shown in Figure 7-114 and described in Table 7-109.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-114. FSM_SECTOR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FSM_SECTOR1
R/W-FFFFFFFFh

Table 7-109. FSM_SECTOR1 Register Field Descriptions
Bit
31-0

672

Field

Type

Reset

FSM_SECTOR1

R/W

FFFFFFFFh Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

Description

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.107 FSM_SECTOR2 Register (Offset = 22C4h) [reset = 0h]
FSM_SECTOR2 is shown in Figure 7-115 and described in Table 7-110.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-115. FSM_SECTOR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FSM_SECTOR2
R/W-0h

Table 7-110. FSM_SECTOR2 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

FSM_SECTOR2

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

673

VIMS Registers

www.ti.com

7.9.1.108 FSM_BSLE0 Register (Offset = 22E0h) [reset = 0h]
FSM_BSLE0 is shown in Figure 7-116 and described in Table 7-111.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-116. FSM_BSLE0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FSM_BSLE0
R/W-0h

Table 7-111. FSM_BSLE0 Register Field Descriptions
Bit
31-0

674

Field

Type

Reset

Description

FSM_BSLE0

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.109 FSM_BSLE1 Register (Offset = 22E4h) [reset = 0h]
FSM_BSLE1 is shown in Figure 7-117 and described in Table 7-112.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-117. FSM_BSLE1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FSM_BSL1
R/W-0h

Table 7-112. FSM_BSLE1 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

FSM_BSL1

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

675

VIMS Registers

www.ti.com

7.9.1.110 FSM_BSLP0 Register (Offset = 22F0h) [reset = 0h]
FSM_BSLP0 is shown in Figure 7-118 and described in Table 7-113.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-118. FSM_BSLP0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FSM_BSLP0
R/W-0h

Table 7-113. FSM_BSLP0 Register Field Descriptions
Bit
31-0

676

Field

Type

Reset

Description

FSM_BSLP0

R/W

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.111 FSM_BSLP1 Register (Offset = 22F4h) [reset = 0h]
FSM_BSLP1 is shown in Figure 7-119 and described in Table 7-114.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-119. FSM_BSLP1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FSM_BSL1
R/W-0h

Table 7-114. FSM_BSLP1 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

FSM_BSL1

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

677

VIMS Registers

www.ti.com

7.9.1.112 FCFG_BANK Register (Offset = 2400h) [reset = 401h]
FCFG_BANK is shown in Figure 7-120 and described in Table 7-115.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-120. FCFG_BANK Register
31

22
21
EE_BANK_WIDTH
R-0h

28
27
EE_BANK_WIDTH
R-0h

18
17
EE_NUM_BANK
R-0h

2
1
MAIN_NUM_BANK
R-1h

12
11
MAIN_BANK_WIDTH
R-40h

6
5
MAIN_BANK_WIDTH
R-40h

Table 7-115. FCFG_BANK Register Field Descriptions
Bit

678

Field

Type

Reset

Description

31-20

EE_BANK_WIDTH

Internal. Only to be used through TI provided API.

19-16

EE_NUM_BANK

Internal. Only to be used through TI provided API.

15-4

MAIN_BANK_WIDTH

40h

Internal. Only to be used through TI provided API.

3-0

MAIN_NUM_BANK

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.113 FCFG_WRAPPER Register (Offset = 2404h) [reset = 50009007h]
FCFG_WRAPPER is shown in Figure 7-121 and described in Table 7-116.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-121. FCFG_WRAPPER Register
31

22
RESERVED
R-0h

28
27
FAMILY_TYPE
R-50h

11
ROM
R-0h

10
IFLUSH
R-0h

9
SIL3
R-0h

8
ECCA
R-0h

AUTO_SUSP
R-0h

20
MEM_MAP
R-0h

EE_IN_MAIN
R-9h
7

CPU2
R-0h

UERR
R-0h

CPU_TYPE1
R-7h

Table 7-116. FCFG_WRAPPER Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

FAMILY_TYPE

50h

Internal. Only to be used through TI provided API.

23-21

RESERVED

Internal. Only to be used through TI provided API.

MEM_MAP

Internal. Only to be used through TI provided API.

19-16

CPU2

Internal. Only to be used through TI provided API.

15-12

EE_IN_MAIN

Internal. Only to be used through TI provided API.

ROM

Internal. Only to be used through TI provided API.

IFLUSH

Internal. Only to be used through TI provided API.

SIL3

Internal. Only to be used through TI provided API.

ECCA

Internal. Only to be used through TI provided API.

7-6

AUTO_SUSP

Internal. Only to be used through TI provided API.

5-4

UERR

Internal. Only to be used through TI provided API.

3-0

CPU_TYPE1

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

679

VIMS Registers

www.ti.com

7.9.1.114 FCFG_BNK_TYPE Register (Offset = 2408h) [reset = 3h]
FCFG_BNK_TYPE is shown in Figure 7-122 and described in Table 7-117.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-122. FCFG_BNK_TYPE Register
31

30
29
B7_TYPE
R-0h

26
25
B6_TYPE
R-0h

22
21
B5_TYPE
R-0h

18
17
B4_TYPE
R-0h

14
13
B3_TYPE
R-0h

10
9
B2_TYPE
R-0h

6
5
B1_TYPE
R-0h

2
1
B0_TYPE
R-3h

Table 7-117. FCFG_BNK_TYPE Register Field Descriptions
Bit

680

Field

Type

Reset

Description

31-28

B7_TYPE

Internal. Only to be used through TI provided API.

27-24

B6_TYPE

Internal. Only to be used through TI provided API.

23-20

B5_TYPE

Internal. Only to be used through TI provided API.

19-16

B4_TYPE

Internal. Only to be used through TI provided API.

15-12

B3_TYPE

Internal. Only to be used through TI provided API.

11-8

B2_TYPE

Internal. Only to be used through TI provided API.

7-4

B1_TYPE

Internal. Only to be used through TI provided API.

3-0

B0_TYPE

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.115 FCFG_B0_START Register (Offset = 2410h) [reset = 02000000h]
FCFG_B0_START is shown in Figure 7-123 and described in Table 7-118.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-123. FCFG_B0_START Register
31

30
29
B0_MAX_SECTOR
R-0h

26
25
B0_MUX_FACTOR
R-2h

20
19
B0_START_ADDR
R-0h

12
11
B0_START_ADDR
R-0h

4
3
B0_START_ADDR
R-0h

Table 7-118. FCFG_B0_START Register Field Descriptions
Bit

Field

Type

Reset

Description

31-28

B0_MAX_SECTOR

Internal. Only to be used through TI provided API.

27-24

B0_MUX_FACTOR

Internal. Only to be used through TI provided API.

23-0

B0_START_ADDR

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

681

VIMS Registers

www.ti.com

7.9.1.116 FCFG_B1_START Register (Offset = 2414h) [reset = 0h]
FCFG_B1_START is shown in Figure 7-124 and described in Table 7-119.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-124. FCFG_B1_START Register
31

30
29
B1_MAX_SECTOR
R-0h

26
25
B1_MUX_FACTOR
R-0h

20
19
B1_START_ADDR
R-0h

12
11
B1_START_ADDR
R-0h

4
3
B1_START_ADDR
R-0h

Table 7-119. FCFG_B1_START Register Field Descriptions
Bit

682

Field

Type

Reset

Description

31-28

B1_MAX_SECTOR

Internal. Only to be used through TI provided API.

27-24

B1_MUX_FACTOR

Internal. Only to be used through TI provided API.

23-0

B1_START_ADDR

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.117 FCFG_B2_START Register (Offset = 2418h) [reset = 0h]
FCFG_B2_START is shown in Figure 7-125 and described in Table 7-120.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-125. FCFG_B2_START Register
31

30
29
B2_MAX_SECTOR
R-0h

26
25
B2_MUX_FACTOR
R-0h

20
19
B2_START_ADDR
R-0h

12
11
B2_START_ADDR
R-0h

4
3
B2_START_ADDR
R-0h

Table 7-120. FCFG_B2_START Register Field Descriptions
Bit

Field

Type

Reset

Description

31-28

B2_MAX_SECTOR

Internal. Only to be used through TI provided API.

27-24

B2_MUX_FACTOR

Internal. Only to be used through TI provided API.

23-0

B2_START_ADDR

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

683

VIMS Registers

www.ti.com

7.9.1.118 FCFG_B3_START Register (Offset = 241Ch) [reset = 0h]
FCFG_B3_START is shown in Figure 7-126 and described in Table 7-121.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-126. FCFG_B3_START Register
31

30
29
B3_MAX_SECTOR
R-0h

26
25
B3_MUX_FACTOR
R-0h

20
19
B3_START_ADDR
R-0h

12
11
B3_START_ADDR
R-0h

4
3
B3_START_ADDR
R-0h

Table 7-121. FCFG_B3_START Register Field Descriptions
Bit

684

Field

Type

Reset

Description

31-28

B3_MAX_SECTOR

Internal. Only to be used through TI provided API.

27-24

B3_MUX_FACTOR

Internal. Only to be used through TI provided API.

23-0

B3_START_ADDR

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.119 FCFG_B4_START Register (Offset = 2420h) [reset = 0h]
FCFG_B4_START is shown in Figure 7-127 and described in Table 7-122.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-127. FCFG_B4_START Register
31

30
29
B4_MAX_SECTOR
R-0h

26
25
B4_MUX_FACTOR
R-0h

20
19
B4_START_ADDR
R-0h

12
11
B4_START_ADDR
R-0h

4
3
B4_START_ADDR
R-0h

Table 7-122. FCFG_B4_START Register Field Descriptions
Bit

Field

Type

Reset

Description

31-28

B4_MAX_SECTOR

Internal. Only to be used through TI provided API.

27-24

B4_MUX_FACTOR

Internal. Only to be used through TI provided API.

23-0

B4_START_ADDR

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

685

VIMS Registers

www.ti.com

7.9.1.120 FCFG_B5_START Register (Offset = 2424h) [reset = 0h]
FCFG_B5_START is shown in Figure 7-128 and described in Table 7-123.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-128. FCFG_B5_START Register
31

30
29
B5_MAX_SECTOR
R-0h

26
25
B5_MUX_FACTOR
R-0h

20
19
B5_START_ADDR
R-0h

12
11
B5_START_ADDR
R-0h

4
3
B5_START_ADDR
R-0h

Table 7-123. FCFG_B5_START Register Field Descriptions
Bit

686

Field

Type

Reset

Description

31-28

B5_MAX_SECTOR

Internal. Only to be used through TI provided API.

27-24

B5_MUX_FACTOR

Internal. Only to be used through TI provided API.

23-0

B5_START_ADDR

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.121 FCFG_B6_START Register (Offset = 2428h) [reset = 0h]
FCFG_B6_START is shown in Figure 7-129 and described in Table 7-124.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-129. FCFG_B6_START Register
31

30
29
B6_MAX_SECTOR
R-0h

26
25
B6_MUX_FACTOR
R-0h

20
19
B6_START_ADDR
R-0h

12
11
B6_START_ADDR
R-0h

4
3
B6_START_ADDR
R-0h

Table 7-124. FCFG_B6_START Register Field Descriptions
Bit

Field

Type

Reset

Description

31-28

B6_MAX_SECTOR

Internal. Only to be used through TI provided API.

27-24

B6_MUX_FACTOR

Internal. Only to be used through TI provided API.

23-0

B6_START_ADDR

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

687

VIMS Registers

www.ti.com

7.9.1.122 FCFG_B7_START Register (Offset = 242Ch) [reset = 0h]
FCFG_B7_START is shown in Figure 7-130 and described in Table 7-125.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-130. FCFG_B7_START Register
31

30
29
B7_MAX_SECTOR
R-0h

26
25
B7_MUX_FACTOR
R-0h

20
19
B7_START_ADDR
R-0h

12
11
B7_START_ADDR
R-0h

4
3
B7_START_ADDR
R-0h

Table 7-125. FCFG_B7_START Register Field Descriptions
Bit

688

Field

Type

Reset

Description

31-28

B7_MAX_SECTOR

Internal. Only to be used through TI provided API.

27-24

B7_MUX_FACTOR

Internal. Only to be used through TI provided API.

23-0

B7_START_ADDR

Internal. Only to be used through TI provided API.

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.1.123 FCFG_B0_SSIZE0 Register (Offset = 2430h) [reset = 00200004h]
FCFG_B0_SSIZE0 is shown in Figure 7-131 and described in Table 7-126.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 7-131. FCFG_B0_SSIZE0 Register
31

30
29
RESERVED
R-0h

10
9
RESERVED
R-0h

22
21
20
B0_NUM_SECTORS
R-20h
6

2
1
B0_SECT_SIZE
R-4h

Table 7-126. FCFG_B0_SSIZE0 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

RESERVED

Internal. Only to be used through TI provided API.

27-16

B0_NUM_SECTORS

20h

Internal. Only to be used through TI provided API.

15-4

RESERVED

Internal. Only to be used through TI provided API.

3-0

B0_SECT_SIZE

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

689

VIMS Registers

www.ti.com

7.9.2 VIMS Registers
Table 7-127 lists the memory-mapped registers for the VIMS. All register offset addresses not listed in
Table 7-127 should be considered as reserved locations and the register contents should not be modified.
Table 7-127. VIMS Registers
Offset

690

Acronym

STAT

Status

Section 7.9.2.1

CTL

Control

Section 7.9.2.2

Versatile Instruction Memory System (VIMS)

Section

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

VIMS Registers

www.ti.com

7.9.2.1

STAT Register (Offset = 0h) [reset = 0h]

STAT is shown in Figure 7-132 and described in Table 7-128.
Return to Summary Table.
Status
Displays current VIMS mode and line buffer status
Figure 7-132. STAT Register
31

3
MODE_CHAN
GING
R-0h

2
INV

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

6
RESERVED
R-0h

5
4
IDCODE_LB_D SYSBUS_LB_D
IS
IS
R-0h
R-0h

R-0h

0
MODE
R-0h

Table 7-128. STAT Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

IDCODE_LB_DIS

Icode/Dcode flash line buffer status
0: Enabled or in transition to disabled
1: Disabled and flushed

SYSBUS_LB_DIS

Sysbus flash line buffer control
0: Enabled or in transition to disabled
1: Disabled and flushed

MODE_CHANGING

VIMS mode change status
0: VIMS is in the mode defined by MODE
1: VIMS is in the process of changing to the mode given in
CTL.MODE

INV

This bit is set when invalidation of the cache memory is active /
ongoing

MODE

Current VIMS mode
0h = GPRAM : VIMS GPRAM mode
1h = CACHE : VIMS Cache mode
3h = VIMS Off mode

31-6

1-0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Versatile Instruction Memory System (VIMS)

691

VIMS Registers

7.9.2.2

www.ti.com

CTL Register (Offset = 4h) [reset = 0h]

CTL is shown in Figure 7-133 and described in Table 7-129.
Return to Summary Table.
Control
Configure VIMS mode and line buffer settings
Figure 7-133. CTL Register
31
STATS_CLR
R/W-0h

30
STATS_EN
R/W-0h

29
DYN_CG_EN
R/W-0h

26
RESERVED
R-0h

3
ARB_CFG

2
PREF_EN

R/W-0h

RESERVED
R-0h
15

12
RESERVED
R-0h

6
RESERVED
R-0h

5
4
IDCODE_LB_D SYSBUS_LB_D
IS
IS
R/W-0h
R/W-0h

0
MODE
R/W-0h

Table 7-129. CTL Register Field Descriptions
Bit

Field

Type

Reset

Description

STATS_CLR

R/W

Set this bit to clear statistic counters.

STATS_EN

R/W

Set this bit to enable statistic counters.

DYN_CG_EN

R/W

0: The in-built clock gate functionality is bypassed.
1: The in-built clock gate functionality is enabled, automatically
gating the clock when not needed.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

IDCODE_LB_DIS

R/W

Icode/Dcode flash line buffer control
0: Enable
1: Disable

SYSBUS_LB_DIS

R/W

Sysbus flash line buffer control
0: Enable
1: Disable

ARB_CFG

R/W

Icode/Dcode and sysbus arbitation scheme
0: Static arbitration (icode/docde > sysbus)
1: Round-robin arbitration

PREF_EN

R/W

Tag prefetch control
0: Disabled
1: Enabled

MODE

R/W

VIMS mode request.
Write accesses to this field will be blocked while
STAT.MODE_CHANGING is set to 1.
Note: Transaction from CACHE mode to GPRAM mode should be
done through OFF mode to minimize flash block delay.
0h = GPRAM : VIMS GPRAM mode
1h = CACHE : VIMS Cache mode
3h = VIMS Off mode

28-6

1-0

692

Versatile Instruction Memory System (VIMS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Chapter 8
SWCU117G – February 2015 – Revised February 2017

Bootloader
This section describes the CC26x0 and CC13x0 bootloader.
Topic

8.1
8.2

...........................................................................................................................

Page

Bootloader Functionality ................................................................................... 694
Bootloader Interfaces ........................................................................................ 694

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bootloader

693

Bootloader Functionality

8.1

www.ti.com

Bootloader Functionality
The CC26x0 and CC13x0 devices include a simple, ROM-based bootloader that can communicate with an
external device over the serial interfaces on the UART0 and SSI0 peripherals. The same communication
protocol is used on both serial interfaces. These peripherals are IPs from ARM®.
The main purpose of the ROM bootloader is to support functionality for downloading a flash image.

8.1.1 Bootloader Disabling
The ROM bootloader supports commands that can read the flash image. Due to this read capability, a
secure measure for disabling the bootloader has been implemented. If the bootloader is disabled using the
CCFG BOOTLOADER_ENABLE parameter, the bootloader is unable to execute any commands, which
prevents attackers from using the bootloader if the Cortex®-M3 program counter (PC) is forced to execute
from the bootloader code.

8.1.2 Bootloader Backdoor
To enter the ROM bootloader even when a valid image is in the flash, a bootloader backdoor is
implemented. The CCFG parameter BL_ENABLE can enable this backdoor. The backdoor functionality
uses a configurable I/O pin (CCFG parameter BL_PIN_NO) and a configurable I/O pin level (CCFG
parameter BL_LEVEL).
If backdoor functionality is enabled, externally applying a configurable signal level on a configurable I/O
pin can force a ROM bootloader entry upon reset. If the backdoor is enabled and a valid flash image is
present, start-up code checks the level of the I/O pin. If the configured I/O-pin level matches the
configured signal level, the ROM bootloader does not transfer control to the flash image.
If the backdoor pin configuration matches one of the UART0 or SSI0 pins, the external user must deassert
the backdoor signal before transmitting on the UART0 or SSI0 interface.
Table 9-14 lists the BL_BACKDOOR_CONFIG parameter layout in CCFG.
NOTE: When using the bootloader backdoor functionality, the pin configured as backdoor
(BL_PIN_NO) will be configured to enable pullup while checking the backdoor level. This is
done regardless of the level configured with BL_LEVEL.

8.2

Bootloader Interfaces
The bootloader communicates with an external device over a 2-pin UART or a 4-pin SSI interface. The
communication protocol and transport layers are described in the following sections.

694

Bootloader

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bootloader Interfaces

www.ti.com

8.2.1 Packet Handling
The bootloader uses well-defined packets to ensure reliable communications with the external
communicating program. All communications, with the exception of the UART automatic baud (see
Section 8.2.2.1), use these well-defined packets. The packets are always acknowledged or not
acknowledged by the communicating devices with defined ACK or NACK bytes.
The packets use the same format for receiving and sending packets. This format includes the method to
acknowledge successful or unsuccessful reception of a packet.
While the actual signaling on the serial ports is different, the packet format remains the same for
supported UART and SSI interfaces.
Packet send and packet receive must adhere to the simple protocol shown in Figure 8-1.
Figure 8-1. Sequence Diagram for Send and Receive Protocol
:Receiver

:Sender

Send size of packet

Send packet checksum

Wait for nonzero data,
read size

Get checksum

Send byte 1
Get packet data

Send byte N

Await ACK

Send ACK

Calculate packet
checksum, signal
result

The following steps must be performed to successfully send a packet:
1. Send the size of the packet to be sent to the device. The size is always the size of the data + 2 with
truncation to 8 bits.
2. Send the checksum of the data buffer to ensure proper transmission of the command. The checksum
algorithm is a sum of the data bytes.
3. Send the actual data bytes.
4. Wait for a single-byte acknowledgment from the device that the data was properly received or that a
transmission error was detected.
To successfully receive a packet, the following steps must be performed:
1. Wait for nonzero data to be returned from the device. This is important as the device may send zero
bytes between a sent and a received data packet. The first nonzero byte received is the size of the
packet that is being received.
2. Read the next byte, which is the checksum for the packet.
3. Read the data bytes from the device. During the data phase, packet size minus 2 bytes is sent. For
example, if the packet size was 3, then there is only 1 byte of data to be received.
4. Calculate the checksum of the data bytes and verify it matches the checksum received in the packet.
5. Send an acknowledge or not-acknowledge to the device to indicate the successful or unsuccessful
reception of the packet.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bootloader

695

Bootloader Interfaces

www.ti.com

Acknowledge (ACK) bytes are sent out whenever a packet is successfully received and verified by the
receiver. A not-acknowledge (NAK) byte is sent out whenever a sent packet is detected to have an error,
usually as a result of a checksum error or just malformed data in the packet, which allows the sender to
retransmit the previous packet.
To illustrate packet handling, the basic packet format is shown in Figure 8-2.
In Figure 8-2, the top line shows the device that is transmitting data; the bottom line is the response from
the other device.
In this case, a 6-byte packet is sent with the data shown in Figure 8-2. This data results in a checksum of
0x48+0x6f+0x6c+0x61 which, when truncated to 8 bits, is 0x84. The first byte transmitted holds the size of
the packet in number of bytes. Then the checksum byte is transmitted. The next bytes to go out are the 4
data bytes in this packet. The transmitter is allowed to send zeros until a nonzero response is received,
that is necessary for SSI and is allowed by the UART. The receiver is allowed to return zeros until it is
ready to ACK or NAK the packet that is being sent. Neither device transfers a nonzero byte until it has
received a response after transmitting a packet.
Figure 8-2. Serial Bus Packet Format
size

checksum

0x06

0x84

data

0x48

0x6f

0x6c

0x61

0x03

0x00

ACK
0x00

8.2.1.1

0xcc

Packet Acknowledge and Not-Acknowledge Bytes

Table 8-1 shows the defined values for packet acknowledge (ACK) and not-acknowledge (NAK) bytes.
Table 8-1. Protocol Acknowledge and NotAcknowledge Bytes
Protocol Byte

Value

ACK

0xCC

NACK

0x33

8.2.2 Transport Layer
The bootloader supports updating through the UART0 and SSI0 ports, which are available on the CC26x0
and CC13x0 devices. The SSI0 port has the advantage of supporting higher and more flexible data rates,
but it also requires more connections to the CC26x0 and CC13x0 devices. The UART0 has the
disadvantage of having slightly lower and possibly less flexible rates. However, the UART0 requires fewer
pins and can be easily implemented with any standard UART connection.

696

Bootloader

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bootloader Interfaces

www.ti.com

Table 8-2 specifies which serial interface signals are configured to specific DIOs. These pins are fixed and
cannot be reconfigured.
Table 8-2. Configuration of Serial Interfaces
Signal

7×7 QFN (RGZ)

5×5 QFN (RHB)

4×4 QFN (RSM)

2.7 × 2.7 WCSP
(YFV)

UART0 RX

DIO2

DIO1

UART0 TX

DIO3

DIO0

DIO2

DIO0

SSI0 CLK

DIO10

DIO8

DIO10

SSI0 FSS

DIO11

DIO9

DIO7

DIO9

SSI0 RX

DIO9

DIO11

DIO9

DIO11

SSI0 TX

DIO8

DIO12

DIO0

DIO12

The bootloader initially configures only the input pins on the two serial interfaces. By default, all I/O pins
have their input buffers disabled, so the bootloader configures the required pins to be input pins so that
the bootloader interface is not accessible from a host before this point in time. For this initial configuration
of input pins, the firmware configures the IOC to route the input signals listed in Table 8-2 to their
corresponding peripheral signals.
The bootloader selects the interface that is the first to be accessed by the external device. Once selected,
the TX output pin for the selected interface is configured; the module on the inactive interface (UART0 or
SSI0) is disabled. To switch to the other interface, the CC26x0 and CC13x0 devices must be reset. The
delayed configuration of the TX pin imposes special consideration on an SSI0 master device regarding the
transfer of the first byte of the first packet. See Section 8.2.2.2.
8.2.2.1

UART Transport

The connections required to use the UART port are the following two pins: UART0 TX and UART0 RX.
The device communicating with the bootloader drives the UART0 RX pin on the CC26x0 and CC13x0,
while the CC26x0 and CC13x0 devices drive the UART0 TX pin.
While the baud rate is flexible, the UART serial format is fixed at 8 data bits, no parity, and 1 stop bit. The
bootloader automatically detects the baud rate for communication. The only requirement is that the baud
rate must be no more than 1/16 of the frequency of the UART module clock in CC26x0 and CC13x0
devices.
8.2.2.1.1 UART Baud Rate Automatic Detection
The bootloader provides a method to automatically detect the UART baud rate being used to
communicate with it.
To synchronize with the host, the bootloader must to receive 2 bytes with the value of 0x55. If
synchronization succeeds, the bootloader returns an acknowledge consisting of 2 bytes with the values of
0x00 and 0xCC.
If synchronization fails, the bootloader waits for synchronization attempts.
In the automatic-detection function, the UART0 RX pin is monitored for edges using GPIO interrupts.
When enough edges are detected, the bootloader determines the ratio of baud rate and frequency needed
to program the UART.
The UART module system clock must be at least 16 times the baud rate; thus, the maximum baud rate
can be no higher than 3 Mbaud (48 MHz divided by 16). The maximum baud rate is restricted to 1.6
Mbaud because of the firmware function that detects the transfer rate of the host.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bootloader

697

Bootloader Interfaces

8.2.2.2

www.ti.com

SSI Transport

The connections required to use the SSI port are the following four pins:
• SSI0 TX
• SSI0 RX
• SSI0 Clk
• SSI0 Fss
The device communicating with the bootloader drives the SSI0 RX, SSI0 Clk, and SSI0 Fss pins, while the
CC26x0 and CC13x0 devices drive the SSI0 TX pin.
The format used for SSI communications is the Motorola format with SPH set to 1 and SPO set to 1 (see
Figure 20-9 for more information on this format). The SSI interface has a hardware requirement that limits
the maximum rate of the SSI clock to be at most 1/12 the frequency of the SSI module clock
(48 MHz / 12 = 4 MHz).
The master must take special consideration (regarding the use of the SSI0 interface) due to the
functionality of not configuring any output pins before the external master device has selected a serial
interface.
NOTE: On the first packet transferred by the master, no data is received from the bootloader while
the bootloader clocks out the bits in the first byte of the packet.
When the bootloader detects that 1 byte has been received on SSI0 RX, the bootloader
configures the SSI0 TX output pin.
Before transmitting the next byte in the first packet, the master must include a small delay to
ensure that the bootloader has completed the configuration of the SSI0 TX output pin.

8.2.3 Serial Bus Commands
Table 8-3 lists the commands supported by the custom protocol on the UART0 and SSI0 bootloader
interfaces.
Each command is transferred within a protocol packet. The first 2 bytes within a packet are the size byte
followed by the checksum byte. The third byte holds the command value that identifies the command; the
values for all the supported commands are listed in the Command Value column of Table 8-3. The
remaining bytes within the packet are command parameters. See Section 8.2.3.1 through Section 8.2.3.12
for a complete description of the command byte and parameter bytes for each command.
Table 8-3. Supported Bootloader Commands
Command

Command Value

Bytes in Packet

Description

COMMAND_PING

0x20

Receives an acknowledge from the bootloader
indicating that communication has been
established.

COMMAND_DOWNLOAD

0x21

Prepares flash programming. Specifies from where
to program data in flash and how many bytes will
be sent by the COMMAND_SEND_DATA
commands that follow.

Returns the status of the last command that was
issued. Typically, this command must be received
by the bootloader after every command is sent to
ensure that the previous command was successful.
See Table 8-4 for defined status values. The status
is returned within a protocol packet of 3 bytes.

COMMAND_GET_STATUS

698 Bootloader

0x23

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Bootloader Interfaces

www.ti.com

Table 8-3. Supported Bootloader Commands (continued)
Command

Command Value

Bytes in Packet

Description

COMMAND_SEND_DATA

0x24

4 to 255

Transfers data and programs flash. Transferring
data which is programmed into flash following a
COMMAND_DOWNLOAD command or another
COMMAND_SEND_DATA command.
The number of data bytes to be programmed in
flash can be 1 to 252 (maximum data load in
packet).
If more data are downloaded by the
COMMAND_SEND_DATA commands than are
specified by the COMMAND_DOWNLOAD
command, an error status is generated.

COMMAND_RESET

0x25

Performs a system reset. See Section 6.7.1.2 for
details.

COMMAND_SECTOR_ERASE

0x26

Erases one sector within the flash main bank. The
sector to erase is specified by the sector start
address. Only flash sectors not protected by writeprotect bits in FCFG1 and CCFG are erased.
If the top sector is selected (containing CCFG), the
content of CCFG will be reset to the same values
as when the devices was delivered from TI.

COMMAND_CRC32

0x27

Calculates CRC32 over a specified memory area.
The number of reads per memory location is
specified.

COMMAND_GET_CHIP_ID

0x28

Returns the 32-bit UserID from the AON_WUC
JTAGUSERCODE register with MSB first. The ID is
returned within a protocol packet.

Reads a specified number of elements with a
specified access width (8 bits or 32 bits) from a
specified memory-mapped start address. The
requested amount of data must be less than the
maximum size of a communication packet.

COMMAND_MEMORY_READ

0x2A

COMMAND_MEMORY_WRITE

0x2B

COMMAND_BANK_ERASE

0x2C

COMMAND_SET_CCFG

0x2D

9 to 255

Writes the received data in accesses with a
specified width (8 or 32 bits) from a specified
memory-mapped start address. Data to be written
must be contained in same packet as the
command.

Performs an erase of all of the customer-accessible
flash sectors not protected by FCFG1 and CCFG
write-protect bits. No erase operation is performed
if the CCFG parameter BANK_ERASE_DIS is
cleared.
Because the top sector might be erased
(containing CCFG), the content of CCFG will be
reset to the same values as when the devices was
delivered from TI.

Writes the CC26x0- and CC13x0-defined CCFG
fields to the flash CCFG area with the values
received in the data bytes of this command.
This command abstracts the user from detailed
knowledge concerning which physical addresses
within the flash CCFG holding the defined CCFG
fields.

The following subsections specify the individual bytes within the protocol packets for each command.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bootloader

699

Bootloader Interfaces

8.2.3.1

www.ti.com

COMMAND_PING

The COMMAND_PING command receives an acknowledge from the bootloader, indicating that
communication has been established. This command is a single byte.
The format of the packet including the command is as follows:
unsigned char ucCommand[3];
ucCommand[0] = ;
ucCommand[1] = ;
ucCommand[2] = COMMAND_PING;
8.2.3.2

COMMAND_DOWNLOAD

The COMMAND_DOWNLOAD command is sent to the bootloader to indicate where to store data in flash
and how many bytes will be sent by the COMMAND_SEND_DATA commands that follow. The command
consists of two 32-bit values that are both transferred MSB first. The first 32-bit value is the address to
start programming data into, while the second is the 32-bit size of the data that will be sent. This
command must be followed by a COMMAND_GET_STATUS command to ensure that the program
address and program size are valid for the device. On the CC26x0 and CC13x0 devices, the flash starts
at address 0x0000 0000. The command does not perform any kind of erase operation; it only prepares for
the following flash programming performed by COMMAND_SEND_DATA commands. Required flash
erase can be done by the COMMAND_BANK_ERASE and COMMAND_SECTOR_ERASE commands.
The format of the packet including the command is as follows:
unsigned char ucCommand[11];
ucCommand[0] = ;
ucCommand[1] = ;
ucCommand[2] = COMMAND_DOWNLOAD;
ucCommand[3] = Program Address [31:24];
ucCommand[4] = Program Address [23:16];
ucCommand[5] = Program Address [15:8];
ucCommand[6] = Program Address [7:0];
ucCommand[7] = Program Size [31:24];
ucCommand[8] = Program Size [23:16];
ucCommand[9] = Program Size [15:8];
ucCommand[10] = Program Size [7:0];

700

Bootloader

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bootloader Interfaces

www.ti.com

8.2.3.3

COMMAND_SEND_DATA

The COMMAND_SEND_DATA command must only follow a COMMAND_DOWNLOAD command or
another COMMAND_SEND_DATA command, if more data is needed. Consecutive
COMMAND_SEND_DATA commands automatically increment the address and continue programming
from the previous location.
The command terminates programming when the number of bytes indicated by the
COMMAND_DOWNLOAD command is received.
The bootloader sends the ACK in response to the command after the actual programming is complete.
Each time this function is called, enter a COMMAND_GET_STATUS command to ensure that the data
was successfully programmed into the flash. If the bootloader sends a NAK signal to this command, the
bootloader does not increment the current address, which allows for retransmission of the previous data.
The format of the packet including the command is as follows:
unsigned char ucCommand[4-255];
ucCommand[0] = ;
ucCommand[1] = ;
ucCommand[2] = COMMAND_SEND_DATA;
ucCommand[3] = Data byte to be programmed[0];
ucCommand[4] = Data byte to be programmed[1];
ucCommand[5] = Data byte to be programmed[2];
ucCommand[6] = Data byte to be programmed[3];
ucCommand[7] = Data byte to be programmed[4];
ucCommand[] = Data byte to be programmed[];
8.2.3.4

COMMAND_SECTOR_ERASE

The COMMAND_SECTOR_ERASE command erases a specified flash sector. One flash sector has the
size of 4KB.
The command consists of one 32-bit value that is transferred MSB first. The 32-bit value is the start
address of the flash sector to be erased.
The bootloader responds with an ACK signal to the host device after the actual erase operation is
performed.
On the CC26x0 and CC13x0 devices, the flash starts at address 0x0000 0000 and it has sectors of 4KB
each.
NOTE: Sectors protected by write-protect bits in FCFG1 and CCFG are not erased.

If the sector address of the top sector (including the CCFG area) is specified, the actual erase is followed
by CCFG values being programmed to the same values as the device had when it was delivered from TI.
The format of the packet including the command is as follows:
unsigned char ucCommand[7];
ucCommand[0]=
ucCommand[1]=
ucCommand[2]=
ucCommand[3]=
ucCommand[4]=
ucCommand[5]=
ucCommand[6]=

;
;
COMMAND_ERASE;
Sector Address
Sector Address
Sector Address
Sector Address

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

[31:24];
[23:16];
[15: 8];
[ 7: 0];

Bootloader

701

Bootloader Interfaces

8.2.3.5

www.ti.com

COMMAND_GET_STATUS

The COMMAND_GET_STATUS command returns the status of the last command that was issued.
Typically, this command is received after every other command is sent to ensure that the previous
command was successful; or, if the command failed, to properly respond to a failure. The bootloader
responds by sending a 3-byte packet with the size byte, checksum byte, and 1 byte of the current-status
value.
The bootloader then waits for an ACK from the host as a confirmation that the packet was received.
The format of the packet including the command is as follows:
unsigned char ucCommand[3];
ucCommand[0] = ;
ucCommand[1] = ;
ucCommand[2] = COMMAND_GET_STATUS;
Table 8-4 lists the definitions for the possible status values that can be returned from the bootloader when
a COMMAND_GET_STATUS command is sent to the bootloader
Table 8-4. Defined Status Values
Status Definition

8.2.3.6

Value

Description

COMMAND_RET_SUCCESS

0x40

Status for successful command

COMMAND_RET_UNKNOWN_CMD

0x41

Status for unknown command

COMMAND_RET_INVALID_CMD

0x42

Status for invalid command (in other words,
incorrect packet size)

COMMAND_RET_INVALID_ADR

0x43

Status for invalid input address

COMMAND_RET_FLASH_FAIL

0x44

Status for failing flash erase or program operation

COMMAND_RESET

The COMMAND_RESET command tells the bootloader to perform a system reset. Use this command
after downloading a new flash image to the CC26x0 and CC13x0 devices to cause the new application to
start from a reset. The normal boot sequence occurs and the flash image runs as if from a hardware reset.
Also, use this command to reset the bootloader if a critical error occurs and the host device wants to
restart communication with the bootloader.
The bootloader responds with an ACK signal to the host device before actually executing the system
reset. This ACK signal informs the updating application that the command was received successfully and
the CC26x0 and CC13x0 devices are then reset.
The format of the packet including the command is as follows:
unsigned char ucCommand[3];
ucCommand[0] = ;
ucCommand[1] = ;
ucCommand[2] = COMMAND_RESET;

702

Bootloader

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bootloader Interfaces

www.ti.com

8.2.3.7

COMMAND_GET_CHIP_ID

The COMMAND_GET_CHIP_ID command makes the bootloader return the value of the 32-bit user ID
from the AON_WUW JTAGUSERCODE register. The bootloader first responds by sending the ACK signal
in response to the command; then the bootloader sends a packet of 6 bytes with the size byte, the
checksum byte, and the 4 bytes (MSB first) holding the user ID.
The bootloader then waits for an ACK signal from the host as a confirmation that the packet was received.
The format of the command is as follows:
unsigned char ucCommand[3];
ucCommand[0] = ;
ucCommand[1] = ;
ucCommand[2] = COMMAND_GET_CHIP_ID;
8.2.3.8

COMMAND_CRC32

The COMMAND_CRC32 command checks a flash area using CRC32. The command consists of three
32-bit values that are all transferred MSB first. The first 32-bit value is the address in memory from where
the CRC32 calculation starts, the second 32-bit value is the number of bytes comprised by the CRC32
calculation, and the third 32-bit value is the number of read repeats for each data location. A read repeat
count of 0x0000 0000 causes the checksum to be generated by a read of all data locations only once. The
command sends the ACK signal in response to the command after the actual CRC32 calculation. The
result is finally returned as 4 bytes (MSB first) in a 6-byte packet. The bootloader then waits for an ACK
signal from the host as a confirmation that the packet was received. The second parameter that holds the
number of bytes must be higher than eight. If not, the returned checksum is 0xFFFF FFFF.
The format of the packet including the command is as follows:
unsigned char ucCommand[15];
ucCommand[0] = ;
ucCommand[1] = ;
ucCommand[2]= COMMAND_CRC32;
ucCommand[3]= Data Address [31:24];
ucCommand[4]= Data Address [23:16];
ucCommand[5]= Data Address [15: 8];
ucCommand[6]= Data Address [ 7: 0];
ucCommand[7]= Data Size [31:24];
ucCommand[8]= Data Size [23:16];
ucCommand[9]= Data Size [15: 8];
ucCommand[10]= Data Size [7: 0];
ucCommand[11]= Read Repeat Count [31:24];
ucCommand[12]= Read Repeat Count [23:16];
ucCommand[13]= Read Repeat Count [15: 8];
ucCommand[14]= Read Repeat Count [7: 0];

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bootloader

703

Bootloader Interfaces

8.2.3.9

www.ti.com

COMMAND_BANK_ERASE

The COMMAND_BANK_ERASE command does not perform any erase operation if the CCFG parameter
BANK_ERASE_DIS is cleared. When COMMAND_BANK_ERASE is not cleared, this command erases all
main bank flash sectors including CCFG not protected by write-protect bits in FCFG1 and CCFG.
The command sends the ACK in response to the command after the actual erase operation is performed.
If the sector address of the top sector (including the CCFG area) is specified, the actual erase is followed
by CCFG values being programmed to the same values as the device had when it was delivered from TI.
The format of the packet including the command is as follows:
unsigned char ucCommand[3];
ucCommand[0] = ;
ucCommand[1] = ;
ucCommand[2] = COMMAND_BANK_ERASE;
NOTE: The bank erase operation locks the flash module FSM. A reset must be issued if additional
flash-bank operations are to be followed.

8.2.3.10 COMMAND_MEMORY_READ
This command reads a specified number of elements with a specified access type (8- or 32 bits) from a
specified memory mapped start address and returns the read data in a separate communication packet.
The requested amount of data must be less than the max size of a communication packet. The specified
Access Type must be either 0 or 1. The value of 0 forces 8-bits read accesses. The value of 1 forces 32bits read accesses. The specified Number of Accesses gives the number of 8- or 32-bits read accesses.
Max value of Number of Accesses is 253 for Access Type = 0. Max value for Number of Accesses is 63
for Access Type = 1. The format of the packet including the command is as follows:
unsigned char ucCommand[9];
ucCommand[0] = ;
ucCommand[1] = ;
ucCommand[2] = COMMAND_MEMORY_READ;
ucCommand[3] = Memory
ucCommand[4] = Memory
ucCommand[5] = Memory
ucCommand[6] = Memory
ucCommand[7] = Access
ucCommand[8] = Number

704

Bootloader

Map Address
Map Address
Map Address
Map Address
Type [7:0];
of Accesses

[31:24];
[23:16];
[15:8];
[7:0];
[7:0];

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bootloader Interfaces

www.ti.com

8.2.3.11 COMMAND_MEMORY_WRITE
This command writes the received data in accesses with specified width (8- or 32-bits) from a specified
memory mapped start address. Data to be written must be contained in same packet as the command.
The access width is given by the specified Access Type. The Access Type must be either 0 or 1. The
value of 0 forces 8-bits write accesses. The value of 1 forces 32-bits write accesses. The number of data
bytes received is given by the packet size byte. Maximum number of data bytes for access width 0 is 247
and 244 for access width 1.
Specific memory mapped areas must not be written to using the COMMAND_MEMORY_WRITE
command. Memory writes to the following memory mapped areas can cause the serial bootloader to end
up in a nonfunctional state as these areas are used by the bootloader. This is valid for the following
memory mapped areas:
• The lower 4KB of SRAM (0x2000 0000 to 0x2000 0FFF)
• Any hardware register controlling the functionality of the serial interface (UART or SSI) currently being
used by the serial bootloader.
NOTE:

The COMMAND_MEMORY_WRITE command cannot be used to write to Flash memory.

The format of the packet including the command is as follows:
unsigned char ucCommand[(from 9 to 255)];
ucCommand[0] = ;
ucCommand[1] = ;
ucCommand[2] = COMMAND_MEMORY_WRITE;
ucCommand[3] = Memory Map Address
ucCommand[4] = Memory Map Address
ucCommand[5] = Memory Map Address
ucCommand[6] = Memory Map Address
ucCommand[7] = Access Type [7:0];
ucCommand[8] = Data [7:0];
...
...
ucCommand[9 + (packet size - 9)] = Data

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

[31:24];
[23:16];
[15:8];
[7:0];

[7:0] or Data[31:24];

Bootloader

705

Bootloader Interfaces

www.ti.com

8.2.3.12 COMMAND_SET_CCFG
The COMMAND_SET_CCFG command is sent to the bootloader to configure the defined fields in the
flash CCFG area that are read by the ROM boot FW. The command sends the ACK signal in response to
the command after the actual flash program operation is performed. This command does not execute any
erase operation before the write operation.
The command consists of two 32-bit values that are all transferred MSB first. The first 32-bit value is the
CCFG Field ID, which identifies the CCFG parameter to be written, and the second 32-bit value is the
Field Value to be programmed. The command handler masks out Field Value bits not corresponding to the
CCFG parameter size.
NOTE: The COMMAND_SET_CCFG command can only change CCFG parameter value bits from 1
to 0.
Attempting to change any bit from 0 to 1 results in an error status that can be observed by a
following COMMAND_GET_STATUS command.
Only the CCFG fields controlling device configuration during ROM boot, can be written by
this command. (fields sequential from BL_CONFIG to until end).

The only way to change CCFG parameter value bits from 0 to 1 is by erasing the complete CCFG flash
sector. The command sends the ACK signal in response to the command after the actual flash
programming has terminated.
The programming operation fails if the CCFG area (flash top sector) is write-protected by the protect bit in
FCFG1 or in CCFG.
The format of the packet including the command is as follows:
unsigned char ucCommand[11];
ucCommand[0] = ;
ucCommand[1] = ;
ucCommand[2] = COMMAND_SET_CCFG;
ucCommand[3] = Field Id[31:24];
ucCommand[4] = Field Id[23:16];
ucCommand[5] = Field Id[15:8];
ucCommand[6] = Field Id[7:0];
ucCommand[7] = Field Value[31:24];
ucCommand[8] = Field Value[23:16];
ucCommand[9] = Field Value[15:8];
ucCommand[10] = Field Value[7:0];

706

Bootloader

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bootloader Interfaces

www.ti.com

Defined CCFG field IDs with corresponding field values are described in Table 8-5.
Table 8-5. Defined CCFG Field IDs and Field Values
Field ID

Field Value

Description

0: ID_SECTOR_PROT

Bit[31:0] – Flash sector number of sector to
protect from program and erase

The sector write-protect bit in CCFG
corresponding to the specified sector
number is set to 0. This protects the sector
from being programmed and erased. First
flash sector has sector number 0.
This command also sets the sticky sector
protect bit in the flash wrapper registers.
Be aware if protecting sector 31, which is
the CCFG sector. If sector 31 is protected,
none of the other CCFG parameters can
be set.

1: ID_IMAGE_VALID

Bit[31:0] - 0x0000 0000

For the boot sequence to transfer
execution control to a flash image, this
Field ID must be set to 0x0000 0000.

2: ID_TEST_TAP_LCK

Bit[31:8] – Don’t care
Bit[7:0] – 0xC5 = TAP unlocked

Any other value than 0xC5 forces a locked
TAP after a following boot sequence

3: ID_PRCM_TAP_LCK

Bit[31:8] – Don’t care
Bit[7:0] – 0xC5 = TAP unlocked

Any other value than 0xC5 forces a locked
TAP after a following boot sequence.

4: ID_CPU_DAP_LCK

Bit[31:8] – Don’t care
Bit[7:0] – 0xC5 = DAP unlocked

Any other value than 0xC5 forces a locked
DAP after a following boot sequence.

5: ID_WUC_TAP_LCK

Bit[31:8] – Don’t care
Bit[7:0] – 0xC5 = TAP unlocked

Any other value than 0xC5 forces a locked
TAP after a following boot sequence.

6: ID_PBIST1_TAP_LCK

Bit[31:8] – Don’t care
Bit[7:0] – 0xC5 = TAP unlocked

Any other value than 0xC5 forces a locked
TAP after a following boot sequence.

7: ID_PBIST2_TAP_LCK

Bit[31:8] – Don’t care
Bit[7:0] – 0xC5 = TAP unlocked

Any other value than 0xC5 forces a locked
TAP after a following boot sequence.

8: ID_BANK_ERASE_DIS

Bit[31:1] – Don’t care
Bit[0] – 0 = Bank erase disable

If set to 0, the COMMAND_BANK_ERASE
bootloader command does not force any
erase operation.

9: ID_CHIP_ERASE_DIS

Bit[31:1] – Don’t care
Bit[0] – 0 = Chip erase disable

If set to 0, the start-up sequence does not
perform any chip erase operation
regardless of the state of the
FLASHERASE bit in the AON WUC
STATUS register.

10: ID_TI_FA_ENABLE

Bit[31:8] – Don’t care
Bit[7:0] – 0xC5 = TI FA enable

Any value other than 0xC5 disables the TI
FA enable functionality in a following boot.

11: ID_BL_BACKDOOR_EN

Any other value than 0xC5 forces the
Bit[31:8] – Don’t care
bootloader backdoor to be disabled in a
Bit[7:0] – 0xC5 = Bootloader backdoor enable
following boot sequence.

12: ID_BL_BACKDOOR_PIN

If the pin number exceeds number of I/O
Bit[31:8] – Don’t care
pins on the device, the highest I/O pin
Bit[7:0] – Bootloader backdoor I/O pin number
number on the device is selected.

13: ID_BL_BACKDOOR_LEVEL

Bit[31:1] – Don’t care
Bit[0] – Bootloader backdoor pin active level

0 = Active low

14: ID_BL_ENABLE

Bit[31:8] – Don’t care
Bit[7:0] – Bootloader enable

Any value other than 0xC5 forces the
bootloader to ignore any received
command.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bootloader

707

Chapter 9
SWCU117G – February 2015 – Revised February 2017

Device Configuration
This chapter describes the device configuration areas. The factory configuration (FCFG) and customer
configuration (CCFG) areas are located in flash. The FCFG is set by Texas Instruments during device
production and contains device-specific trim values and configuration. The CCFG must be set by the
application and contains configuration parameters for the ROM boot code, device hardware, and device
firmware.
Topic

9.1
9.2

708

...........................................................................................................................

Page

Customer Configuration (CCFG) ........................................................................ 709
Factory Configuration (FCFG) ........................................................................... 738

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

9.1

Customer Configuration (CCFG)
•
•
•
•
•
•

Image valid bit (normally set by the programming tool)
Failure analysis access configuration
Custom MAC address
Bootloader configuration
TAP and DAP access configuration
CC13x0 only: Configure the output power to +14 dBm

In TI distributed software, the CCFG parameters are set at compile time in the ccfg.c file. The CCFG
settings are set by default to allow full debugging of the device. The CCFG settings are not recommended
for production.
CC13x0 only: To enable output power of +14 dBm, the CCFG_FORCE_VDDR_HH define must be set to
1 in ccfg.c distributed in cc13xxware by TI. If CCFG_FORCE_VDDR_HH is set to 0 the maximum possible
output power is +12.5 dBm.
The recommended way to configure a device for final production is as follows:
1. The BL_CONFIG:BOOTLOADER_ENABLE register and the BL_CONFIG:BL_ENABLE register must
be set to 0x00 to disallow access to Flash contents through the bootloader interface.
2. The CCFG_TI_OPTIONS:TI_FA_ENABLE register must be set to 0x00 to disallow failure analysis
access by TI.
3. The CCFG_TAP_DAP_0:PRCM_TAP_ENABLE register, the
CCFG_TAP_DAP_0:TEST_TAP_ENABLE register, and the CCFG_TAP_DAP_0:CPU_DAP_ENABLE
register must be set to set to 0x00 to disallow access to these module through JTAG.
4. The CCFG_TAP_DAP_1 register must be set to 0xFF00 0000 to disallow access to these modules
through JTAG.
5. The IMAGE_VALID_CONF:IMAGE_VALID register must be set to 0x0000 0000 to pass control to the
programmed image in Flash at boot.
6. Optionally, the ERASE_CONF:CHIP_ERASE_DIS_N register can be set to 0x0 to disallow erasing of
the Flash.
7. Use the CCFG_PROT_n registers to write and erase protect the sectors of Flash that are not designed
to be updated in-system by the final product.
NOTE: Enabling some of the functionality in the ENABLE fields in CCFG are contingent on the
corresponding ENABLE field in FCFG that has been set to enabled by the TI production test.
This is the case for the CCFG_TAP_DAP_0:TEST_TAP_ENABLE register for example,
which is enabled in FCFG in some products in the family while it is not enabled in others. In
the products where the CCFG_TAP_DAP_0:TEST_TAP_ENABLE register is not enabled in
FCFG, the value in the corresponding CCFG field is ignored and the functionality is disabled.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

709

Customer Configuration (CCFG)

www.ti.com

9.1.1 CCFG Registers
Table 9-1 lists the memory-mapped registers for the CCFG. All register offset addresses not listed in
Table 9-1 should be considered as reserved locations and the register contents should not be modified.
Table 9-1. CCFG Registers

710

Offset

Acronym

FA8h

EXT_LF_CLK

Extern LF clock configuration

Section 9.1.1.1

Section

FACh

MODE_CONF_1

Mode Configuration 1

Section 9.1.1.2

FB0h

SIZE_AND_DIS_FLAGS

CCFG Size and Disable Flags

Section 9.1.1.3

FB4h

MODE_CONF

Mode Configuration 0

Section 9.1.1.4

FB8h

VOLT_LOAD_0

Voltage Load 0

Section 9.1.1.5

FBCh

VOLT_LOAD_1

Voltage Load 1

Section 9.1.1.6

FC0h

RTC_OFFSET

Real Time Clock Offset

Section 9.1.1.7

FC4h

FREQ_OFFSET

Frequency Offset

Section 9.1.1.8

FC8h

IEEE_MAC_0

IEEE MAC Address 0

Section 9.1.1.9

FCCh

IEEE_MAC_1

IEEE MAC Address 1

Section 9.1.1.10

FD0h

IEEE_BLE_0

IEEE BLE Address 0

Section 9.1.1.11

FD4h

IEEE_BLE_1

IEEE BLE Address 1

Section 9.1.1.12

FD8h

BL_CONFIG

Bootloader Configuration

Section 9.1.1.13

FDCh

ERASE_CONF

Erase Configuration

Section 9.1.1.14

FE0h

CCFG_TI_OPTIONS

TI Options

Section 9.1.1.15

FE4h

CCFG_TAP_DAP_0

Test Access Points Enable 0

Section 9.1.1.16

FE8h

CCFG_TAP_DAP_1

Test Access Points Enable 1

Section 9.1.1.17

FECh

IMAGE_VALID_CONF

Image Valid

Section 9.1.1.18

FF0h

CCFG_PROT_31_0

Protect Sectors 0-31

Section 9.1.1.19

FF4h

CCFG_PROT_63_32

Protect Sectors 32-63

Section 9.1.1.20

FF8h

CCFG_PROT_95_64

Protect Sectors 64-95

Section 9.1.1.21

FFCh

CCFG_PROT_127_96

Protect Sectors 96-127

Section 9.1.1.22

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

9.1.1.1

EXT_LF_CLK Register (Offset = FA8h) [reset = FFFFFFFFh]

EXT_LF_CLK is shown in Figure 9-1 and described in Table 9-2.
Return to Summary Table.
Extern LF clock configuration
Figure 9-1. EXT_LF_CLK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
DIO
RTC_INCREMENT
R-FFh
R-00FFFFFFh

Table 9-2. EXT_LF_CLK Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

DIO

FFh

Unsigned integer, selecting the DIO to supply external 32kHz clock
as SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to
EXTERNAL. The selected DIO will be marked as reserved by the pin
driver (TI-RTOS environment) and hence not selectable for other
usage.

23-0

RTC_INCREMENT

00FFFFFFh Unsigned integer, defining the input frequency of the external clock
and is written to AON_RTC:SUBSECINC.VALUEINC. Defined as
follows: EXT_LF_CLK.RTC_INCREMENT =
238/InputClockFrequency in Hertz (e.g.:
RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

711

Customer Configuration (CCFG)

9.1.1.2

www.ti.com

MODE_CONF_1 Register (Offset = FACh) [reset = FFFBFFFFh]

MODE_CONF_1 is shown in Figure 9-2 and described in Table 9-3.
Return to Summary Table.
Mode Configuration 1
Figure 9-2. MODE_CONF_1 Register
31

19
ALT_DCDC_DI
THER_EN
R-1h

17
ALT_DCDC_IPEAK

RESERVED
R-FFh
23

22
21
ALT_DCDC_VMIN

R-Fh
15

14
13
DELTA_IBIAS_INIT
R-Fh

4
3
XOSC_MAX_START
R-FFh

R-3h
10
9
DELTA_IBIAS_OFFSET
R-Fh
2

Table 9-3. MODE_CONF_1 Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

FFh

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-20

ALT_DCDC_VMIN

Minimum voltage for when DC/DC should be used if alternate
DC/DC setting is enabled
(SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).
Voltage = (28 + ALT_DCDC_VMIN) / 16.
0: 1.75V
1: 1.8125V
...
14: 2.625V
15: 2.6875V
NOTE! The DriverLib function
SysCtrl_DCDC_VoltageConditionalControl() must be called regularly
to apply this field (handled automatically if using TI RTOS!).

ALT_DCDC_DITHER_EN

Enable DC/DC dithering if alternate DC/DC setting is enabled
(SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).
0: Dither disable
1: Dither enable

18-16

ALT_DCDC_IPEAK

Inductor peak current if alternate DC/DC setting is enabled
(SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming
10uH external inductor!
Peak current = 31 + ( 4 * ALT_DCDC_IPEAK ) :
0: 31mA (min)
...
4: 47mA
...
7: 59mA (max)

15-12

DELTA_IBIAS_INIT

Signed delta value for IBIAS_INIT. Delta value only applies if
SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0.
See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT

11-8

DELTA_IBIAS_OFFSET

Signed delta value for IBIAS_OFFSET. Delta value only applies if
SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0.
See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET

7-0

XOSC_MAX_START

FFh

Unsigned value of maximum XOSC startup time (worst case) in units
of 100us. Value only applies if
SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0.

712

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

9.1.1.3

SIZE_AND_DIS_FLAGS Register (Offset = FB0h) [reset = FFFFFFFFh]

SIZE_AND_DIS_FLAGS is shown in Figure 9-3 and described in Table 9-4.
Return to Summary Table.
CCFG Size and Disable Flags
Figure 9-3. SIZE_AND_DIS_FLAGS Register
31

28
27
SIZE_OF_CCFG
R-FFFFh

20
19
SIZE_OF_CCFG
R-FFFFh

12
11
DISABLE_FLAGS
R-FFFh

6
5
DISABLE_FLAGS

R-FFFh

3
DIS_TCXO

2
DIS_GPRAM

R-1h

1
0
DIS_ALT_DCD DIS_XOSC_OV
C_SETTING
R
R-1h
R-1h

Table 9-4. SIZE_AND_DIS_FLAGS Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

SIZE_OF_CCFG

FFFFh

Total size of CCFG in bytes.

15-4

DISABLE_FLAGS

FFFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

DIS_TCXO

Disable TCXO.
0: TCXO functionality enabled.
1: TCXO functionality disabled.
Note:
An external TCXO is required if DIS_TCXO = 0.

DIS_GPRAM

Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM).
0: GPRAM is enabled and hence CACHE disabled.
1: GPRAM is disabled and instead CACHE is enabled (default).
Notes:
- Disabling CACHE will reduce CPU execution speed (up to 60%).
- GPRAM is 8 K-bytes in size and located at 0x110000000x11001FFF if enabled.
See:
VIMS:CTL.MODE

DIS_ALT_DCDC_SETTIN R
G

Disable alternate DC/DC settings.
0: Enable alternate DC/DC settings.
1: Disable alternate DC/DC settings.
See:
MODE_CONF_1.ALT_DCDC_VMIN
MODE_CONF_1.ALT_DCDC_DITHER_EN
MODE_CONF_1.ALT_DCDC_IPEAK
NOTE! The DriverLib function
SysCtrl_DCDC_VoltageConditionalControl() must be called regularly
to apply this field (handled automatically if using TI RTOS!).

DIS_XOSC_OVR

Disable XOSC override functionality.
0: Enable XOSC override functionality.
1: Disable XOSC override functionality.
See:
MODE_CONF_1.DELTA_IBIAS_INIT
MODE_CONF_1.DELTA_IBIAS_OFFSET
MODE_CONF_1.XOSC_MAX_START

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

713

Customer Configuration (CCFG)

9.1.1.4

www.ti.com

MODE_CONF Register (Offset = FB4h) [reset = FFFFFFFFh]

MODE_CONF is shown in Figure 9-4 and described in Table 9-5.
Return to Summary Table.
Mode Configuration 0
Figure 9-4. MODE_CONF Register
31

30
29
VDDR_TRIM_SLEEP_DELTA

27
26
DCDC_RECHA DCDC_ACTIVE
RGE
R-1h
R-1h

R-Fh
23
22
SCLK_LF_OPTION
R-3h

21
VDDR_TRIM_S
LEEP_TC
R-1h

20
RTC_COMP

25
VDDR_EXT_L
OAD
R-1h

24
VDDS_BOD_L
EVEL
R-1h

17
XOSC_CAP_M
OD
R-1h

16
HF_COMP

18
XOSC_FREQ

R-1h

R-3h

12
11
XOSC_CAPARRAY_DELTA
R-FFh
4

R-1h

VDDR_CAP
R-FFh

Table 9-5. MODE_CONF Register Field Descriptions
Bit

Field

Type

Reset

Description

VDDR_TRIM_SLEEP_DE
LTA

Signed delta value to apply to the
VDDR_TRIM_SLEEP target, minus one. See
FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H.
0x8 (-8) : Delta = -7
...
0xF (-1) : Delta = 0
0x0 (0) : Delta = +1
...
0x7 (7) : Delta = +8

DCDC_RECHARGE

DC/DC during recharge in powerdown.
0: Use the DC/DC during recharge in powerdown.
1: Do not use the DC/DC during recharge in powerdown (default).
NOTE! The DriverLib function
SysCtrl_DCDC_VoltageConditionalControl() must be called regularly
to apply this field (handled automatically if using TI RTOS!).

DCDC_ACTIVE

DC/DC in active mode.
0: Use the DC/DC during active mode.
1: Do not use the DC/DC during active mode (default).
NOTE! The DriverLib function
SysCtrl_DCDC_VoltageConditionalControl() must be called regularly
to apply this field (handled automatically if using TI RTOS!).

VDDR_EXT_LOAD

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

VDDS_BOD_LEVEL

VDDS BOD level.
0: VDDS BOD level is 2.0 V (necessary for maximum PA output
power on CC13x0).
1: VDDS BOD level is 1.8 V (or 1.7 V for external regulator mode)
(default).

31-28

714

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

Table 9-5. MODE_CONF Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

SCLK_LF_OPTION

Select source for SCLK_LF.
0h = 31.25kHz clock derived from 24MHz XOSC (dividing by 768 in
HW). The RTC tick speed [AON_RTC.SUBSECINC.*] is updated to
0x8637BD, corresponding to a 31.25kHz clock (done in the
trimDevice() xxWare boot function). Standby power mode is not
supported when using this clock source.
1h = External low frequency clock on DIO defined by
EXT_LF_CLK.DIO. The RTC tick speed AON_RTC:SUBSECINC is
updated to EXT_LF_CLK.RTC_INCREMENT (done in the
trimDevice() xxWare boot function). External clock must always be
running when the chip is in standby for VDDR recharge timing.
2h = 32.768kHz low frequency XOSC
3h = Low frequency RCOSC (default)

VDDR_TRIM_SLEEP_TC

0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated
0x0: RTOS/driver temperature compensates
VDDR_TRIM_SLEEP_DELTA every time standby mode is entered.
This improves low-temperature RCOSC_LF frequency stability in
standby mode.
When temperature compensation is performed, the delta is
calculates this way:
Delta = max (delta, min(8, floor(62-temp)/8))
Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is
the current temperature in degrees C.

RTC_COMP

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

19-18

XOSC_FREQ

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.
1h = HPOSC
2h = 48M : 48 MHz XOSC_HF
3h = 24M : 24 MHz XOSC_HF

XOSC_CAP_MOD

Enable modification (delta) to XOSC cap-array. Value specified in
XOSC_CAPARRAY_DELTA.
0: Apply cap-array delta
1: Do not apply cap-array delta (default)

HF_COMP

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

15-8

XOSC_CAPARRAY_DEL
TA

FFh

Signed 8-bit value, directly modifying trimmed XOSC cap-array step
value. Enabled by XOSC_CAP_MOD.

7-0

VDDR_CAP

FFh

Unsigned 8-bit integer, representing the minimum decoupling
capacitance (worst case) on VDDR, in units of 100nF. This should
take into account capacitor tolerance and voltage dependent
capacitance variation. This bit affects the recharge period calculation
when going into powerdown or standby.
NOTE! If using the following functions this field must be configured
(used by TI RTOS):
SysCtrlSetRechargeBeforePowerDown()
SysCtrlAdjustRechargeAfterPowerDown()

23-22

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

715

Customer Configuration (CCFG)

9.1.1.5

www.ti.com

VOLT_LOAD_0 Register (Offset = FB8h) [reset = FFFFFFFFh]

VOLT_LOAD_0 is shown in Figure 9-5 and described in Table 9-6.
Return to Summary Table.
Voltage Load 0
Enabled by MODE_CONF.VDDR_EXT_LOAD.
Figure 9-5. VOLT_LOAD_0 Register
31

28
27
VDDR_EXT_TP45
R-FFh

20
19
VDDR_EXT_TP25
R-FFh

12
11
VDDR_EXT_TP5
R-FFh

4
3
VDDR_EXT_TM15
R-FFh

Table 9-6. VOLT_LOAD_0 Register Field Descriptions
Bit

716

Field

Type

Reset

Description

31-24

VDDR_EXT_TP45

FFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

23-16

VDDR_EXT_TP25

FFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

15-8

VDDR_EXT_TP5

FFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

7-0

VDDR_EXT_TM15

FFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

9.1.1.6

VOLT_LOAD_1 Register (Offset = FBCh) [reset = FFFFFFFFh]

VOLT_LOAD_1 is shown in Figure 9-6 and described in Table 9-7.
Return to Summary Table.
Voltage Load 1
Enabled by MODE_CONF.VDDR_EXT_LOAD.
Figure 9-6. VOLT_LOAD_1 Register
31

28
27
26
VDDR_EXT_TP125
R-FFh

20
19
18
VDDR_EXT_TP105
R-FFh

12
11
VDDR_EXT_TP85
R-FFh

4
3
VDDR_EXT_TP65
R-FFh

Table 9-7. VOLT_LOAD_1 Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

VDDR_EXT_TP125

FFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

23-16

VDDR_EXT_TP105

FFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

15-8

VDDR_EXT_TP85

FFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

7-0

VDDR_EXT_TP65

FFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

717

Customer Configuration (CCFG)

9.1.1.7

www.ti.com

RTC_OFFSET Register (Offset = FC0h) [reset = FFFFFFFFh]

RTC_OFFSET is shown in Figure 9-7 and described in Table 9-8.
Return to Summary Table.
Real Time Clock Offset
Enabled by MODE_CONF.RTC_COMP.
Figure 9-7. RTC_OFFSET Register
31

12
11
RTC_COMP_P1
R-FFh

24
23
RTC_COMP_P0
R-FFFFh
8

4
3
RTC_COMP_P2
R-FFh

Table 9-8. RTC_OFFSET Register Field Descriptions
Bit

718

Field

Type

Reset

Description

31-16

RTC_COMP_P0

FFFFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

15-8

RTC_COMP_P1

FFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

7-0

RTC_COMP_P2

FFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

9.1.1.8

FREQ_OFFSET Register (Offset = FC4h) [reset = FFFFFFFFh]

FREQ_OFFSET is shown in Figure 9-8 and described in Table 9-9.
Return to Summary Table.
Frequency Offset
Figure 9-8. FREQ_OFFSET Register
31

12
11
HF_COMP_P1
R-FFh

24
23
HF_COMP_P0
R-FFFFh
8

4
3
HF_COMP_P2
R-FFh

Table 9-9. FREQ_OFFSET Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

HF_COMP_P0

FFFFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

15-8

HF_COMP_P1

FFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

7-0

HF_COMP_P2

FFh

Reserved for future use. Software should not rely on the value of a
reserved. Writing any other value than the reset/default value may
result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

719

Customer Configuration (CCFG)

9.1.1.9

www.ti.com

IEEE_MAC_0 Register (Offset = FC8h) [reset = FFFFFFFFh]

IEEE_MAC_0 is shown in Figure 9-9 and described in Table 9-10.
Return to Summary Table.
IEEE MAC Address 0
Figure 9-9. IEEE_MAC_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R-FFFFFFFFh

Table 9-10. IEEE_MAC_0 Register Field Descriptions

720

Bit

Field

Type

Reset

31-0

ADDR

FFFFFFFFh Bits[31:0] of the 64-bits custom IEEE MAC address.
If different from 0xFFFFFFFF then the value of this field is applied
otherwise use value from FCFG.

Device Configuration

Description

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

9.1.1.10 IEEE_MAC_1 Register (Offset = FCCh) [reset = FFFFFFFFh]
IEEE_MAC_1 is shown in Figure 9-10 and described in Table 9-11.
Return to Summary Table.
IEEE MAC Address 1
Figure 9-10. IEEE_MAC_1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R-FFFFFFFFh

Table 9-11. IEEE_MAC_1 Register Field Descriptions
Bit

Field

Type

Reset

31-0

ADDR

FFFFFFFFh Bits[63:32] of the 64-bits custom IEEE MAC address.
If different from 0xFFFFFFFF then the value of this field is applied
otherwise use value from FCFG.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Device Configuration

721

Customer Configuration (CCFG)

www.ti.com

9.1.1.11 IEEE_BLE_0 Register (Offset = FD0h) [reset = FFFFFFFFh]
IEEE_BLE_0 is shown in Figure 9-11 and described in Table 9-12.
Return to Summary Table.
IEEE BLE Address 0
Figure 9-11. IEEE_BLE_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R-FFFFFFFFh

Table 9-12. IEEE_BLE_0 Register Field Descriptions

722

Bit

Field

Type

Reset

31-0

ADDR

FFFFFFFFh Bits[31:0] of the 64-bits custom IEEE BLE address.
If different from 0xFFFFFFFF then the value of this field is applied
otherwise use value from FCFG.

Device Configuration

Description

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

9.1.1.12 IEEE_BLE_1 Register (Offset = FD4h) [reset = FFFFFFFFh]
IEEE_BLE_1 is shown in Figure 9-12 and described in Table 9-13.
Return to Summary Table.
IEEE BLE Address 1
Figure 9-12. IEEE_BLE_1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R-FFFFFFFFh

Table 9-13. IEEE_BLE_1 Register Field Descriptions
Bit

Field

Type

Reset

31-0

ADDR

FFFFFFFFh Bits[63:32] of the 64-bits custom IEEE BLE address.
If different from 0xFFFFFFFF then the value of this field is applied
otherwise use value from FCFG.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Device Configuration

723

Customer Configuration (CCFG)

www.ti.com

9.1.1.13 BL_CONFIG Register (Offset = FD8h) [reset = C5FFFFFFh]
BL_CONFIG is shown in Figure 9-13 and described in Table 9-14.
Return to Summary Table.
Bootloader Configuration
Configures the functionality of the ROM boot loader.
If both the boot loader is enabled by the BOOTLOADER_ENABLE field and the boot loader backdoor is
enabled by the BL_ENABLE field it is possible to force entry of the ROM boot loader even if a valid image
is present in flash.
Figure 9-13. BL_CONFIG Register
31

28
27
BOOTLOADER_ENABLE
R-C5h

16
BL_LEVEL
R-1h

12
11
BL_PIN_NUMBER
R-FFh

20
RESERVED
R-7Fh

3
BL_ENABLE
R-FFh

Table 9-14. BL_CONFIG Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

BOOTLOADER_ENABLE

C5h

Bootloader enable. Boot loader can be accessed if
IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is
enabled (and conditions for boot loader backdoor are met).
0xC5: Boot loader is enabled.
Any other value: Boot loader is disabled.

23-17

RESERVED

7Fh

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BL_LEVEL

Sets the active level of the selected DIO number BL_PIN_NUMBER
if boot loader backdoor is enabled by the BL_ENABLE field.
0: Active low.
1: Active high.

15-8

BL_PIN_NUMBER

FFh

DIO number that is level checked if the boot loader backdoor is
enabled by the BL_ENABLE field.

7-0

BL_ENABLE

FFh

Enables the boot loader backdoor.
0xC5: Boot loader backdoor is enabled.
Any other value: Boot loader backdoor is disabled.
NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE)
if boot loader backdoor is enabled.

724

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

9.1.1.14 ERASE_CONF Register (Offset = FDCh) [reset = FFFFFFFFh]
ERASE_CONF is shown in Figure 9-14 and described in Table 9-15.
Return to Summary Table.
Erase Configuration
Figure 9-14. ERASE_CONF Register
31

8
CHIP_ERASE_
DIS_N
R-1h

0
BANK_ERASE
_DIS_N
R-1h

RESERVED
R-007FFFFFh
23

20
RESERVED
R-007FFFFFh

12
RESERVED
R-007FFFFFh
4
RESERVED
R-7Fh

Table 9-15. ERASE_CONF Register Field Descriptions
Bit
31-9
8

7-1
0

Field

Type

Reset

Description

RESERVED

007FFFFFh

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CHIP_ERASE_DIS_N

Chip erase.
This bit controls if a chip erase requested through the JTAG WUC
TAP will be ignored in a following boot caused by a reset of the MCU
VD.
A successful chip erase operation will force the content of the flash
main bank back to the state as it was when delivered by TI.
0: Disable. Any chip erase request detected during boot will be
ignored.
1: Enable. Any chip erase request detected during boot will be
performed by the boot FW.

RESERVED

7Fh

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BANK_ERASE_DIS_N

Bank erase.
This bit controls if the ROM serial boot loader will accept a received
Bank Erase command (COMMAND_BANK_ERASE).
A successful Bank Erase operation will erase all main bank sectors
not protected by write protect configuration bits in CCFG.
0: Disable the boot loader bank erase function.
1: Enable the boot loader bank erase function.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

725

Customer Configuration (CCFG)

www.ti.com

9.1.1.15 CCFG_TI_OPTIONS Register (Offset = FE0h) [reset = FFFFFFC5h]
CCFG_TI_OPTIONS is shown in Figure 9-15 and described in Table 9-16.
Return to Summary Table.
TI Options
Figure 9-15. CCFG_TI_OPTIONS Register
31

12
11
RESERVED
R-00FFFFFFh

24
23
RESERVED
R-00FFFFFFh
8

4
3
TI_FA_ENABLE
R-C5h

Table 9-16. CCFG_TI_OPTIONS Register Field Descriptions
Bit

726

Field

Type

Reset

31-8

RESERVED

00FFFFFFh Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

TI_FA_ENABLE

C5h

Device Configuration

Description

TI Failure Analysis.
0xC5: Enable the functionality of unlocking the TI FA (TI Failure
Analysis) option with the unlock code.
All other values: Disable the functionality of unlocking the TI FA
option with the unlock code.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

9.1.1.16 CCFG_TAP_DAP_0 Register (Offset = FE4h) [reset = FFC5C5C5h]
CCFG_TAP_DAP_0 is shown in Figure 9-16 and described in Table 9-17.
Return to Summary Table.
Test Access Points Enable 0
Figure 9-16. CCFG_TAP_DAP_0 Register
31

28
27
RESERVED
R-FFh

20
19
18
CPU_DAP_ENABLE
R-C5h

12
11
10
PRCM_TAP_ENABLE
R-C5h

4
3
2
TEST_TAP_ENABLE
R-C5h

Table 9-17. CCFG_TAP_DAP_0 Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

FFh

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-16

CPU_DAP_ENABLE

C5h

Enable CPU DAP.
0xC5: Main CPU DAP access is enabled during power-up/systemreset by ROM boot FW.
Any other value: Main CPU DAP access will remain disabled out of
power-up/system-reset.

15-8

PRCM_TAP_ENABLE

C5h

Enable PRCM TAP.
0xC5: PRCM TAP access is enabled during power-up/system-reset
by ROM boot FW if enabled by corresponding configuration value in
FCFG1 defined by TI.
Any other value: PRCM TAP access will remain disabled out of
power-up/system-reset.

7-0

TEST_TAP_ENABLE

C5h

Enable Test TAP.
0xC5: TEST TAP access is enabled during power-up/system-reset
by ROM boot FW if enabled by corresponding configuration value in
FCFG1 defined by TI.
Any other value: TEST TAP access will remain disabled out of
power-up/system-reset.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

727

Customer Configuration (CCFG)

www.ti.com

9.1.1.17 CCFG_TAP_DAP_1 Register (Offset = FE8h) [reset = FFC5C5C5h]
CCFG_TAP_DAP_1 is shown in Figure 9-17 and described in Table 9-18.
Return to Summary Table.
Test Access Points Enable 1
Figure 9-17. CCFG_TAP_DAP_1 Register
31

28
27
RESERVED
R-FFh

20
19
18
PBIST2_TAP_ENABLE
R-C5h

12
11
10
PBIST1_TAP_ENABLE
R-C5h

4
3
2
WUC_TAP_ENABLE
R-C5h

Table 9-18. CCFG_TAP_DAP_1 Register Field Descriptions
Bit

728

Field

Type

Reset

Description

31-24

RESERVED

FFh

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-16

PBIST2_TAP_ENABLE

C5h

Enable PBIST2 TAP.
0xC5: PBIST2 TAP access is enabled during power-up/system-reset
by ROM boot FW if enabled by corresponding configuration value in
FCFG1 defined by TI.
Any other value: PBIST2 TAP access will remain disabled out of
power-up/system-reset.

15-8

PBIST1_TAP_ENABLE

C5h

Enable PBIST1 TAP.
0xC5: PBIST1 TAP access is enabled during power-up/system-reset
by ROM boot FW if enabled by corresponding configuration value in
FCFG1 defined by TI.
Any other value: PBIST1 TAP access will remain disabled out of
power-up/system-reset.

7-0

WUC_TAP_ENABLE

C5h

Enable WUC TAP
0xC5: WUC TAP access is enabled during power-up/system-reset by
ROM boot FW if enabled by corresponding configuration value in
FCFG1 defined by TI.
Any other value: WUC TAP access will remain disabled out of
power-up/system-reset.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

9.1.1.18 IMAGE_VALID_CONF Register (Offset = FECh) [reset = FFFFFFFFh]
IMAGE_VALID_CONF is shown in Figure 9-18 and described in Table 9-19.
Return to Summary Table.
Image Valid
Figure 9-18. IMAGE_VALID_CONF Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IMAGE_VALID
R-FFFFFFFFh

Table 9-19. IMAGE_VALID_CONF Register Field Descriptions
Bit
31-0

Field

Type

Reset

IMAGE_VALID

FFFFFFFFh This field must have a value of 0x00000000 in order for enabling the
boot sequence to transfer control to a flash image.
A non-zero value forces the boot sequence to call the boot loader.
For CC2640R2:
This field must have the address value of the start of the flash vector
table in order for enabling the boot sequence to transfer control to a
flash image.
Any illegal vector table start address value forces the boot sequence
to call the boot loader.
Note that if any other legal vector table start address value than 0x0
is selected the PRCM:WARMRESET.WR_TO_PINRESET must be
set to 1.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Device Configuration

729

Customer Configuration (CCFG)

www.ti.com

9.1.1.19 CCFG_PROT_31_0 Register (Offset = FF0h) [reset = FFFFFFFFh]
CCFG_PROT_31_0 is shown in Figure 9-19 and described in Table 9-20.
Return to Summary Table.
Protect Sectors 0-31
Each bit write protects one 4KB flash sector from being both programmed and erased. Bit must be set to 0
in order to enable sector write protect.
Figure 9-19. CCFG_PROT_31_0 Register
31
WRT_PROT_S
EC_31
R-1h

30
WRT_PROT_S
EC_30
R-1h

29
WRT_PROT_S
EC_29
R-1h

28
WRT_PROT_S
EC_28
R-1h

27
WRT_PROT_S
EC_27
R-1h

26
WRT_PROT_S
EC_26
R-1h

25
WRT_PROT_S
EC_25
R-1h

24
WRT_PROT_S
EC_24
R-1h

23
WRT_PROT_S
EC_23
R-1h

22
WRT_PROT_S
EC_22
R-1h

21
WRT_PROT_S
EC_21
R-1h

20
WRT_PROT_S
EC_20
R-1h

19
WRT_PROT_S
EC_19
R-1h

18
WRT_PROT_S
EC_18
R-1h

17
WRT_PROT_S
EC_17
R-1h

16
WRT_PROT_S
EC_16
R-1h

15
WRT_PROT_S
EC_15
R-1h

14
WRT_PROT_S
EC_14
R-1h

13
WRT_PROT_S
EC_13
R-1h

12
WRT_PROT_S
EC_12
R-1h

11
WRT_PROT_S
EC_11
R-1h

10
WRT_PROT_S
EC_10
R-1h

9
WRT_PROT_S
EC_9
R-1h

8
WRT_PROT_S
EC_8
R-1h

7
WRT_PROT_S
EC_7
R-1h

6
WRT_PROT_S
EC_6
R-1h

5
WRT_PROT_S
EC_5
R-1h

4
WRT_PROT_S
EC_4
R-1h

3
WRT_PROT_S
EC_3
R-1h

2
WRT_PROT_S
EC_2
R-1h

1
WRT_PROT_S
EC_1
R-1h

0
WRT_PROT_S
EC_0
R-1h

Table 9-20. CCFG_PROT_31_0 Register Field Descriptions

730

Bit

Field

Type

Reset

Description

WRT_PROT_SEC_31

0: Sector protected

WRT_PROT_SEC_30

0: Sector protected

WRT_PROT_SEC_29

0: Sector protected

WRT_PROT_SEC_28

0: Sector protected

WRT_PROT_SEC_27

0: Sector protected

WRT_PROT_SEC_26

0: Sector protected

WRT_PROT_SEC_25

0: Sector protected

WRT_PROT_SEC_24

0: Sector protected

WRT_PROT_SEC_23

0: Sector protected

WRT_PROT_SEC_22

0: Sector protected

WRT_PROT_SEC_21

0: Sector protected

WRT_PROT_SEC_20

0: Sector protected

WRT_PROT_SEC_19

0: Sector protected

WRT_PROT_SEC_18

0: Sector protected

WRT_PROT_SEC_17

0: Sector protected

WRT_PROT_SEC_16

0: Sector protected

WRT_PROT_SEC_15

0: Sector protected

WRT_PROT_SEC_14

0: Sector protected

WRT_PROT_SEC_13

0: Sector protected

WRT_PROT_SEC_12

0: Sector protected

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

Table 9-20. CCFG_PROT_31_0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

WRT_PROT_SEC_11

0: Sector protected

WRT_PROT_SEC_10

0: Sector protected

WRT_PROT_SEC_9

0: Sector protected

WRT_PROT_SEC_8

0: Sector protected

WRT_PROT_SEC_7

0: Sector protected

WRT_PROT_SEC_6

0: Sector protected

WRT_PROT_SEC_5

0: Sector protected

WRT_PROT_SEC_4

0: Sector protected

WRT_PROT_SEC_3

0: Sector protected

WRT_PROT_SEC_2

0: Sector protected

WRT_PROT_SEC_1

0: Sector protected

WRT_PROT_SEC_0

0: Sector protected

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

731

Customer Configuration (CCFG)

www.ti.com

9.1.1.20 CCFG_PROT_63_32 Register (Offset = FF4h) [reset = FFFFFFFFh]
CCFG_PROT_63_32 is shown in Figure 9-20 and described in Table 9-21.
Return to Summary Table.
Protect Sectors 32-63
Each bit write protects one 4KB flash sector from being both programmed and erased. Bit must be set to 0
in order to enable sector write protect. Not in use by CC26x0 and CC13x0.
Figure 9-20. CCFG_PROT_63_32 Register
31
WRT_PROT_S
EC_63
R-1h

30
WRT_PROT_S
EC_62
R-1h

29
WRT_PROT_S
EC_61
R-1h

28
WRT_PROT_S
EC_60
R-1h

27
WRT_PROT_S
EC_59
R-1h

26
WRT_PROT_S
EC_58
R-1h

25
WRT_PROT_S
EC_57
R-1h

24
WRT_PROT_S
EC_56
R-1h

23
WRT_PROT_S
EC_55
R-1h

22
WRT_PROT_S
EC_54
R-1h

21
WRT_PROT_S
EC_53
R-1h

20
WRT_PROT_S
EC_52
R-1h

19
WRT_PROT_S
EC_51
R-1h

18
WRT_PROT_S
EC_50
R-1h

17
WRT_PROT_S
EC_49
R-1h

16
WRT_PROT_S
EC_48
R-1h

15
WRT_PROT_S
EC_47
R-1h

14
WRT_PROT_S
EC_46
R-1h

13
WRT_PROT_S
EC_45
R-1h

12
WRT_PROT_S
EC_44
R-1h

11
WRT_PROT_S
EC_43
R-1h

10
WRT_PROT_S
EC_42
R-1h

9
WRT_PROT_S
EC_41
R-1h

8
WRT_PROT_S
EC_40
R-1h

7
WRT_PROT_S
EC_39
R-1h

6
WRT_PROT_S
EC_38
R-1h

5
WRT_PROT_S
EC_37
R-1h

4
WRT_PROT_S
EC_36
R-1h

3
WRT_PROT_S
EC_35
R-1h

2
WRT_PROT_S
EC_34
R-1h

1
WRT_PROT_S
EC_33
R-1h

0
WRT_PROT_S
EC_32
R-1h

Table 9-21. CCFG_PROT_63_32 Register Field Descriptions

732

Bit

Field

Type

Reset

Description

WRT_PROT_SEC_63

0: Sector protected

WRT_PROT_SEC_62

0: Sector protected

WRT_PROT_SEC_61

0: Sector protected

WRT_PROT_SEC_60

0: Sector protected

WRT_PROT_SEC_59

0: Sector protected

WRT_PROT_SEC_58

0: Sector protected

WRT_PROT_SEC_57

0: Sector protected

WRT_PROT_SEC_56

0: Sector protected

WRT_PROT_SEC_55

0: Sector protected

WRT_PROT_SEC_54

0: Sector protected

WRT_PROT_SEC_53

0: Sector protected

WRT_PROT_SEC_52

0: Sector protected

WRT_PROT_SEC_51

0: Sector protected

WRT_PROT_SEC_50

0: Sector protected

WRT_PROT_SEC_49

0: Sector protected

WRT_PROT_SEC_48

0: Sector protected

WRT_PROT_SEC_47

0: Sector protected

WRT_PROT_SEC_46

0: Sector protected

WRT_PROT_SEC_45

0: Sector protected

WRT_PROT_SEC_44

0: Sector protected

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

Table 9-21. CCFG_PROT_63_32 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

WRT_PROT_SEC_43

0: Sector protected

WRT_PROT_SEC_42

0: Sector protected

WRT_PROT_SEC_41

0: Sector protected

WRT_PROT_SEC_40

0: Sector protected

WRT_PROT_SEC_39

0: Sector protected

WRT_PROT_SEC_38

0: Sector protected

WRT_PROT_SEC_37

0: Sector protected

WRT_PROT_SEC_36

0: Sector protected

WRT_PROT_SEC_35

0: Sector protected

WRT_PROT_SEC_34

0: Sector protected

WRT_PROT_SEC_33

0: Sector protected

WRT_PROT_SEC_32

0: Sector protected

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

733

Customer Configuration (CCFG)

www.ti.com

9.1.1.21 CCFG_PROT_95_64 Register (Offset = FF8h) [reset = FFFFFFFFh]
CCFG_PROT_95_64 is shown in Figure 9-21 and described in Table 9-22.
Return to Summary Table.
Protect Sectors 64-95
Each bit write protects one flash sector from being both programmed and erased. Bit must be set to 0 in
order to enable sector write protect. Not in use by CC26x0 and CC13x0.
Figure 9-21. CCFG_PROT_95_64 Register
31
WRT_PROT_S
EC_95
R-1h

30
WRT_PROT_S
EC_94
R-1h

29
WRT_PROT_S
EC_93
R-1h

28
WRT_PROT_S
EC_92
R-1h

27
WRT_PROT_S
EC_91
R-1h

26
WRT_PROT_S
EC_90
R-1h

25
WRT_PROT_S
EC_89
R-1h

24
WRT_PROT_S
EC_88
R-1h

23
WRT_PROT_S
EC_87
R-1h

22
WRT_PROT_S
EC_86
R-1h

21
WRT_PROT_S
EC_85
R-1h

20
WRT_PROT_S
EC_84
R-1h

19
WRT_PROT_S
EC_83
R-1h

18
WRT_PROT_S
EC_82
R-1h

17
WRT_PROT_S
EC_81
R-1h

16
WRT_PROT_S
EC_80
R-1h

15
WRT_PROT_S
EC_79
R-1h

14
WRT_PROT_S
EC_78
R-1h

13
WRT_PROT_S
EC_77
R-1h

12
WRT_PROT_S
EC_76
R-1h

11
WRT_PROT_S
EC_75
R-1h

10
WRT_PROT_S
EC_74
R-1h

9
WRT_PROT_S
EC_73
R-1h

8
WRT_PROT_S
EC_72
R-1h

7
WRT_PROT_S
EC_71
R-1h

6
WRT_PROT_S
EC_70
R-1h

5
WRT_PROT_S
EC_69
R-1h

4
WRT_PROT_S
EC_68
R-1h

3
WRT_PROT_S
EC_67
R-1h

2
WRT_PROT_S
EC_66
R-1h

1
WRT_PROT_S
EC_65
R-1h

0
WRT_PROT_S
EC_64
R-1h

Table 9-22. CCFG_PROT_95_64 Register Field Descriptions

734

Bit

Field

Type

Reset

Description

WRT_PROT_SEC_95

0: Sector protected

WRT_PROT_SEC_94

0: Sector protected

WRT_PROT_SEC_93

0: Sector protected

WRT_PROT_SEC_92

0: Sector protected

WRT_PROT_SEC_91

0: Sector protected

WRT_PROT_SEC_90

0: Sector protected

WRT_PROT_SEC_89

0: Sector protected

WRT_PROT_SEC_88

0: Sector protected

WRT_PROT_SEC_87

0: Sector protected

WRT_PROT_SEC_86

0: Sector protected

WRT_PROT_SEC_85

0: Sector protected

WRT_PROT_SEC_84

0: Sector protected

WRT_PROT_SEC_83

0: Sector protected

WRT_PROT_SEC_82

0: Sector protected

WRT_PROT_SEC_81

0: Sector protected

WRT_PROT_SEC_80

0: Sector protected

WRT_PROT_SEC_79

0: Sector protected

WRT_PROT_SEC_78

0: Sector protected

WRT_PROT_SEC_77

0: Sector protected

WRT_PROT_SEC_76

0: Sector protected

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

Table 9-22. CCFG_PROT_95_64 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

WRT_PROT_SEC_75

0: Sector protected

WRT_PROT_SEC_74

0: Sector protected

WRT_PROT_SEC_73

0: Sector protected

WRT_PROT_SEC_72

0: Sector protected

WRT_PROT_SEC_71

0: Sector protected

WRT_PROT_SEC_70

0: Sector protected

WRT_PROT_SEC_69

0: Sector protected

WRT_PROT_SEC_68

0: Sector protected

WRT_PROT_SEC_67

0: Sector protected

WRT_PROT_SEC_66

0: Sector protected

WRT_PROT_SEC_65

0: Sector protected

WRT_PROT_SEC_64

0: Sector protected

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

735

Customer Configuration (CCFG)

www.ti.com

9.1.1.22 CCFG_PROT_127_96 Register (Offset = FFCh) [reset = FFFFFFFFh]
CCFG_PROT_127_96 is shown in Figure 9-22 and described in Table 9-23.
Return to Summary Table.
Protect Sectors 96-127
Each bit write protects one flash sector from being both programmed and erased. Bit must be set to 0 in
order to enable sector write protect. Not in use by CC26x0 and CC13x0.
Figure 9-22. CCFG_PROT_127_96 Register
31
WRT_PROT_S
EC_127
R-1h

30
WRT_PROT_S
EC_126
R-1h

29
WRT_PROT_S
EC_125
R-1h

28
WRT_PROT_S
EC_124
R-1h

27
WRT_PROT_S
EC_123
R-1h

26
WRT_PROT_S
EC_122
R-1h

25
WRT_PROT_S
EC_121
R-1h

24
WRT_PROT_S
EC_120
R-1h

23
WRT_PROT_S
EC_119
R-1h

22
WRT_PROT_S
EC_118
R-1h

21
WRT_PROT_S
EC_117
R-1h

20
WRT_PROT_S
EC_116
R-1h

19
WRT_PROT_S
EC_115
R-1h

18
WRT_PROT_S
EC_114
R-1h

17
WRT_PROT_S
EC_113
R-1h

16
WRT_PROT_S
EC_112
R-1h

15
WRT_PROT_S
EC_111
R-1h

14
WRT_PROT_S
EC_110
R-1h

13
WRT_PROT_S
EC_109
R-1h

12
WRT_PROT_S
EC_108
R-1h

11
WRT_PROT_S
EC_107
R-1h

10
WRT_PROT_S
EC_106
R-1h

9
WRT_PROT_S
EC_105
R-1h

8
WRT_PROT_S
EC_104
R-1h

7
WRT_PROT_S
EC_103
R-1h

6
WRT_PROT_S
EC_102
R-1h

5
WRT_PROT_S
EC_101
R-1h

4
WRT_PROT_S
EC_100
R-1h

3
WRT_PROT_S
EC_99
R-1h

2
WRT_PROT_S
EC_98
R-1h

1
WRT_PROT_S
EC_97
R-1h

0
WRT_PROT_S
EC_96
R-1h

Table 9-23. CCFG_PROT_127_96 Register Field Descriptions

736

Bit

Field

Type

Reset

Description

WRT_PROT_SEC_127

0: Sector protected

WRT_PROT_SEC_126

0: Sector protected

WRT_PROT_SEC_125

0: Sector protected

WRT_PROT_SEC_124

0: Sector protected

WRT_PROT_SEC_123

0: Sector protected

WRT_PROT_SEC_122

0: Sector protected

WRT_PROT_SEC_121

0: Sector protected

WRT_PROT_SEC_120

0: Sector protected

WRT_PROT_SEC_119

0: Sector protected

WRT_PROT_SEC_118

0: Sector protected

WRT_PROT_SEC_117

0: Sector protected

WRT_PROT_SEC_116

0: Sector protected

WRT_PROT_SEC_115

0: Sector protected

WRT_PROT_SEC_114

0: Sector protected

WRT_PROT_SEC_113

0: Sector protected

WRT_PROT_SEC_112

0: Sector protected

WRT_PROT_SEC_111

0: Sector protected

WRT_PROT_SEC_110

0: Sector protected

WRT_PROT_SEC_109

0: Sector protected

WRT_PROT_SEC_108

0: Sector protected

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Customer Configuration (CCFG)

www.ti.com

Table 9-23. CCFG_PROT_127_96 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

WRT_PROT_SEC_107

0: Sector protected

WRT_PROT_SEC_106

0: Sector protected

WRT_PROT_SEC_105

0: Sector protected

WRT_PROT_SEC_104

0: Sector protected

WRT_PROT_SEC_103

0: Sector protected

WRT_PROT_SEC_102

0: Sector protected

WRT_PROT_SEC_101

0: Sector protected

WRT_PROT_SEC_100

0: Sector protected

WRT_PROT_SEC_99

0: Sector protected

WRT_PROT_SEC_98

0: Sector protected

WRT_PROT_SEC_97

0: Sector protected

WRT_PROT_SEC_96

0: Sector protected

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

737

Factory Configuration (FCFG)

9.2

www.ti.com

Factory Configuration (FCFG)
The FCFG are programmed by the TI production test for each device. The FCFG contains device-specific
trim values and configuration. Most of the trim values are used by TI boot code, RF core, ROM code, or
are provided by TI software automatically.
Some of the more useful fields in FCFG are MAC_15_4_n fields, which give the preprogrammed IEEE
address of the chipset, and the MAC_BLE_n fields that give the Bluetooth low energy address of the
chipset.

738

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1 CC13x0 Factory Configuration (FCFG) Registers
9.2.1.1

FCFG1 Registers

Table 9-107 lists the memory-mapped registers for the FCFG1. All register offset addresses not listed in
Table 9-107 should be considered as reserved locations and the register contents should not be modified.
Table 9-24. FCFG1 Registers
Offset

Acronym

A0h

MISC_CONF_1

Misc configurations

Section 9.2.2.1.1

Section

A4h

MISC_CONF_2

Internal

Section 9.2.2.1.2

C4h

CONFIG_RF_FRONTEND_DIV5

Internal

Section 9.2.2.1.3

C8h

CONFIG_RF_FRONTEND_DIV6

Internal

Section 9.2.2.1.4

CCh

CONFIG_RF_FRONTEND_DIV10

Internal

Section 9.2.2.1.5

D0h

CONFIG_RF_FRONTEND_DIV12

Internal

Section 9.2.2.1.6

D4h

CONFIG_RF_FRONTEND_DIV15

Internal

Section 9.2.2.1.7

D8h

CONFIG_RF_FRONTEND_DIV30

Internal

Section 9.2.2.1.8

DCh

CONFIG_SYNTH_DIV5

Internal

Section 9.2.2.1.9

E0h

CONFIG_SYNTH_DIV6

Internal

Section 9.2.2.1.10

E4h

CONFIG_SYNTH_DIV10

Internal

Section 9.2.2.1.11

E8h

CONFIG_SYNTH_DIV12

Internal

Section 9.2.2.1.12

ECh

CONFIG_SYNTH_DIV15

Internal

Section 9.2.2.1.13

F0h

CONFIG_SYNTH_DIV30

Internal

Section 9.2.2.1.14

F4h

CONFIG_MISC_ADC_DIV5

Internal

Section 9.2.2.1.15

F8h

CONFIG_MISC_ADC_DIV6

Internal

Section 9.2.2.1.16

FCh

CONFIG_MISC_ADC_DIV10

Internal

Section 9.2.2.1.17

100h

CONFIG_MISC_ADC_DIV12

Internal

Section 9.2.2.1.18

104h

CONFIG_MISC_ADC_DIV15

Internal

Section 9.2.2.1.19

108h

CONFIG_MISC_ADC_DIV30

Internal

Section 9.2.2.1.20

118h

SHDW_DIE_ID_0

Shadow of [JTAG_TAP::EFUSE:DIE_ID_0.*]

Section 9.2.2.1.21

11Ch

SHDW_DIE_ID_1

Shadow of [JTAG_TAP::EFUSE:DIE_ID_1.*]

Section 9.2.2.1.22

120h

SHDW_DIE_ID_2

Shadow of [JTAG_TAP::EFUSE:DIE_ID_2.*]

Section 9.2.2.1.23

124h

SHDW_DIE_ID_3

Shadow of [JTAG_TAP::EFUSE:DIE_ID_3.*]

Section 9.2.2.1.24

138h

SHDW_OSC_BIAS_LDO_TRIM

Internal

Section 9.2.2.1.25

13Ch

SHDW_ANA_TRIM

Internal

Section 9.2.2.1.26

164h

FLASH_NUMBER

16Ch

FLASH_COORDINATE

Section 9.2.2.1.27

170h

FLASH_E_P

Internal

Section 9.2.2.1.29

174h

FLASH_C_E_P_R

Internal

Section 9.2.2.1.30

178h

FLASH_P_R_PV

Internal

Section 9.2.2.1.31

17Ch

FLASH_EH_SEQ

Internal

Section 9.2.2.1.32

180h

FLASH_VHV_E

Internal

Section 9.2.2.1.33

184h

FLASH_PP

Internal

Section 9.2.2.1.34

188h

FLASH_PROG_EP

Internal

Section 9.2.2.1.35

18Ch

FLASH_ERA_PW

Internal

Section 9.2.2.1.36

190h

FLASH_VHV

Internal

Section 9.2.2.1.37

194h

FLASH_VHV_PV

Internal

Section 9.2.2.1.38

198h

FLASH_V

Internal

Section 9.2.2.1.39

294h

USER_ID

User Identification.

Section 9.2.2.1.40

2B0h

FLASH_OTP_DATA3

Internal

Section 9.2.2.1.41

Section 9.2.2.1.28

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

739

Factory Configuration (FCFG)

www.ti.com

Table 9-24. FCFG1 Registers (continued)

740

Offset

Acronym

2B4h

ANA2_TRIM

Internal

Section 9.2.2.1.42

Section

2B8h

LDO_TRIM

Internal

Section 9.2.2.1.43

2BCh

BAT_RC_LDO_TRIM

Internal

Section 9.2.2.1.44

2E8h

MAC_BLE_0

MAC BLE Address 0

Section 9.2.2.1.45

2ECh

MAC_BLE_1

MAC BLE Address 1

Section 9.2.2.1.46

2F0h

MAC_15_4_0

MAC IEEE 802.15.4 Address 0

Section 9.2.2.1.47

2F4h

MAC_15_4_1

MAC IEEE 802.15.4 Address 1

Section 9.2.2.1.48

308h

FLASH_OTP_DATA4

Internal

Section 9.2.2.1.49

30Ch

MISC_TRIM

Miscellaneous Trim Parameters

Section 9.2.2.1.50

310h

RCOSC_HF_TEMPCOMP

Internal

Section 9.2.2.1.51

314h

TRIM_CAL_REVISION

Internal

Section 9.2.2.1.52

318h

ICEPICK_DEVICE_ID

IcePick Device Identification

Section 9.2.2.1.53

31Ch

FCFG1_REVISION

Factory Configuration (FCFG1) Revision

Section 9.2.2.1.54

320h

MISC_OTP_DATA

Misc OTP Data

Section 9.2.2.1.55

344h

IOCONF

IO Configuration

Section 9.2.2.1.56

34Ch

CONFIG_IF_ADC

Internal

Section 9.2.2.1.57

350h

CONFIG_OSC_TOP

Internal

Section 9.2.2.1.58

354h

CONFIG_RF_FRONTEND

Internal

Section 9.2.2.1.59

358h

CONFIG_SYNTH

Internal

Section 9.2.2.1.60

35Ch

SOC_ADC_ABS_GAIN

AUX_ADC Gain in Absolute Reference Mode

Section 9.2.2.1.61

360h

SOC_ADC_REL_GAIN

AUX_ADC Gain in Relative Reference Mode

Section 9.2.2.1.62

368h

SOC_ADC_OFFSET_INT

AUX_ADC Temperature Offsets in Absolute Reference
Mode

Section 9.2.2.1.63

36Ch

SOC_ADC_REF_TRIM_AND_OFFSET_E
XT

Internal

Section 9.2.2.1.64

370h

AMPCOMP_TH1

Internal

Section 9.2.2.1.65

374h

AMPCOMP_TH2

Internal

Section 9.2.2.1.66

378h

AMPCOMP_CTRL1

Internal

Section 9.2.2.1.67

37Ch

ANABYPASS_VALUE2

Internal

Section 9.2.2.1.68

380h

CONFIG_MISC_ADC

Internal

Section 9.2.2.1.69

388h

VOLT_TRIM

Internal

Section 9.2.2.1.70

38Ch

OSC_CONF

OSC Configuration

Section 9.2.2.1.71

390h

FREQ_OFFSET

Internal

Section 9.2.2.1.72

394h

CAP_TRIM

Internal

Section 9.2.2.1.73

398h

MISC_OTP_DATA_1

Internal

Section 9.2.2.1.74

39Ch

PWD_CURR_20C

Power Down Current Control 20C

Section 9.2.2.1.75

3A0h

PWD_CURR_35C

Power Down Current Control 35C

Section 9.2.2.1.76

3A4h

PWD_CURR_50C

Power Down Current Control 50C

Section 9.2.2.1.77

3A8h

PWD_CURR_65C

Power Down Current Control 65C

Section 9.2.2.1.78

3ACh

PWD_CURR_80C

Power Down Current Control 80C

Section 9.2.2.1.79

3B0h

PWD_CURR_95C

Power Down Current Control 95C

Section 9.2.2.1.80

3B4h

PWD_CURR_110C

Power Down Current Control 110C

Section 9.2.2.1.81

3B8h

PWD_CURR_125C

Power Down Current Control 125C

Section 9.2.2.1.82

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.1 MISC_CONF_1 Register (Offset = A0h) [reset = X]
MISC_CONF_1 is shown in Figure 9-105 and described in Table 9-108.
Return to Summary Table.
Misc configurations
Figure 9-23. MISC_CONF_1 Register
31

12
11
RESERVED
R-00FFFFFFh

24
23
RESERVED
R-00FFFFFFh
8

4
3
2
DEVICE_MINOR_REV
R-X

Table 9-25. MISC_CONF_1 Register Field Descriptions
Field

Type

Reset

31-8

Bit

RESERVED

00FFFFFFh Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

DEVICE_MINOR_REV

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

HW minor revision number (a value of 0xFF shall be treated equally
to 0x00).
Any test of this field by SW should be implemented as a 'greater or
equal' comparison as signed integer.
Value may change without warning.

Device Configuration

741

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.2 MISC_CONF_2 Register (Offset = A4h) [reset = X]
MISC_CONF_2 is shown in Figure 9-106 and described in Table 9-109.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-24. MISC_CONF_2 Register
31

12
11
RESERVED
R-00FFFFFFh

24
23
RESERVED
R-00FFFFFFh
8

4
3
HPOSC_COMP_P3
R-X

Table 9-26. MISC_CONF_2 Register Field Descriptions
Bit

742

Field

Type

Reset

31-8

RESERVED

00FFFFFFh Internal. Only to be used through TI provided API.

7-0

HPOSC_COMP_P3

Device Configuration

Description

Internal. Only to be used through TI provided API.
Default value holds log information from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.3 CONFIG_RF_FRONTEND_DIV5 Register (Offset = C4h) [reset = X]
CONFIG_RF_FRONTEND_DIV5 is shown in Figure 9-107 and described in Table 9-110.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-25. CONFIG_RF_FRONTEND_DIV5 Register
31

30
29
IFAMP_IB
R-7h

15
14
CTL_PA0_TRI
M
R-X

26
25
LNA_IB
R-X

10
9
RESERVED

21
20
IFAMP_TRIM
R-0h
5

R-7Fh

18
17
16
CTL_PA0_TRIM
R-X

4
3
2
RFLDO_TRIM_OUTPUT

R-X

Table 9-27. CONFIG_RF_FRONTEND_DIV5 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-19

IFAMP_TRIM

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

13-7

RESERVED

7Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

743

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.4 CONFIG_RF_FRONTEND_DIV6 Register (Offset = C8h) [reset = X]
CONFIG_RF_FRONTEND_DIV6 is shown in Figure 9-108 and described in Table 9-111.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-26. CONFIG_RF_FRONTEND_DIV6 Register
31

30
29
IFAMP_IB
R-7h

15
14
CTL_PA0_TRI
M
R-X

26
25
LNA_IB
R-X

10
9
RESERVED

21
20
IFAMP_TRIM
R-0h
5

R-7Fh

18
17
16
CTL_PA0_TRIM
R-X

4
3
2
RFLDO_TRIM_OUTPUT

R-X

Table 9-28. CONFIG_RF_FRONTEND_DIV6 Register Field Descriptions
Bit

744

Field

Type

Reset

Description

31-28

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-19

IFAMP_TRIM

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

13-7

RESERVED

7Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.5 CONFIG_RF_FRONTEND_DIV10 Register (Offset = CCh) [reset = X]
CONFIG_RF_FRONTEND_DIV10 is shown in Figure 9-109 and described in Table 9-112.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-27. CONFIG_RF_FRONTEND_DIV10 Register
31

30
29
IFAMP_IB
R-7h

15
14
CTL_PA0_TRI
M
R-X

26
25
LNA_IB
R-X

10
9
RESERVED

21
20
IFAMP_TRIM
R-0h
5

R-7Fh

18
17
16
CTL_PA0_TRIM
R-X

4
3
2
RFLDO_TRIM_OUTPUT

R-X

Table 9-29. CONFIG_RF_FRONTEND_DIV10 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-19

IFAMP_TRIM

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

13-7

RESERVED

7Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

745

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.6 CONFIG_RF_FRONTEND_DIV12 Register (Offset = D0h) [reset = X]
CONFIG_RF_FRONTEND_DIV12 is shown in Figure 9-110 and described in Table 9-113.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-28. CONFIG_RF_FRONTEND_DIV12 Register
31

30
29
IFAMP_IB
R-7h

15
14
CTL_PA0_TRI
M
R-X

26
25
LNA_IB
R-X

10
9
RESERVED

21
20
IFAMP_TRIM
R-0h
5

R-7Fh

18
17
16
CTL_PA0_TRIM
R-X

4
3
2
RFLDO_TRIM_OUTPUT

R-X

Table 9-30. CONFIG_RF_FRONTEND_DIV12 Register Field Descriptions
Bit

746

Field

Type

Reset

Description

31-28

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-19

IFAMP_TRIM

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

13-7

RESERVED

7Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.7 CONFIG_RF_FRONTEND_DIV15 Register (Offset = D4h) [reset = X]
CONFIG_RF_FRONTEND_DIV15 is shown in Figure 9-111 and described in Table 9-114.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-29. CONFIG_RF_FRONTEND_DIV15 Register
31

30
29
IFAMP_IB
R-7h

15
14
CTL_PA0_TRI
M
R-X

26
25
LNA_IB
R-X

10
9
RESERVED

21
20
IFAMP_TRIM
R-0h
5

R-7Fh

18
17
16
CTL_PA0_TRIM
R-X

4
3
2
RFLDO_TRIM_OUTPUT

R-X

Table 9-31. CONFIG_RF_FRONTEND_DIV15 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-19

IFAMP_TRIM

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

13-7

RESERVED

7Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

747

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.8 CONFIG_RF_FRONTEND_DIV30 Register (Offset = D8h) [reset = X]
CONFIG_RF_FRONTEND_DIV30 is shown in Figure 9-112 and described in Table 9-115.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-30. CONFIG_RF_FRONTEND_DIV30 Register
31

30
29
IFAMP_IB
R-7h

15
14
CTL_PA0_TRI
M
R-X

26
25
LNA_IB
R-X

10
9
RESERVED

21
20
IFAMP_TRIM
R-0h
5

R-7Fh

18
17
16
CTL_PA0_TRIM
R-X

4
3
2
RFLDO_TRIM_OUTPUT

R-X

Table 9-32. CONFIG_RF_FRONTEND_DIV30 Register Field Descriptions
Bit

748

Field

Type

Reset

Description

31-28

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-19

IFAMP_TRIM

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

13-7

RESERVED

7Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.9 CONFIG_SYNTH_DIV5 Register (Offset = DCh) [reset = X]
CONFIG_SYNTH_DIV5 is shown in Figure 9-113 and described in Table 9-116.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-31. CONFIG_SYNTH_DIV5 Register
31

30
RESERVED

28
DISABLE_COR
NER_CAP
R-X

R-7h
23

26
25
RFC_MDM_DEMIQMC0

R-X

20
19
RFC_MDM_DEMIQMC0
R-X

14
13
RFC_MDM_DEMIQMC0
R-X

7
6
LDOVCO_TRIM_OUTPUT
R-X

10
9
LDOVCO_TRIM_OUTPUT
R-X

3
2
SLDO_TRIM_OUTPUT
R-X

Table 9-33. CONFIG_SYNTH_DIV5 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

DISABLE_CORNER_CAP R

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

27-12

RFC_MDM_DEMIQMC0

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization.
Default value holds trim value from production test.

11-6

LDOVCO_TRIM_OUTPU
T

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

5-0

SLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

31-29
28

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

749

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.10 CONFIG_SYNTH_DIV6 Register (Offset = E0h) [reset = X]
CONFIG_SYNTH_DIV6 is shown in Figure 9-114 and described in Table 9-117.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-32. CONFIG_SYNTH_DIV6 Register
31

30
RESERVED

28
DISABLE_COR
NER_CAP
R-X

R-7h
23

26
25
RFC_MDM_DEMIQMC0

R-X

20
19
RFC_MDM_DEMIQMC0
R-X

14
13
RFC_MDM_DEMIQMC0
R-X

7
6
LDOVCO_TRIM_OUTPUT
R-X

10
9
LDOVCO_TRIM_OUTPUT
R-X

3
2
SLDO_TRIM_OUTPUT
R-X

Table 9-34. CONFIG_SYNTH_DIV6 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

DISABLE_CORNER_CAP R

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

27-12

RFC_MDM_DEMIQMC0

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization.
Default value holds trim value from production test.

11-6

LDOVCO_TRIM_OUTPU
T

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

5-0

SLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

31-29
28

750

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.11 CONFIG_SYNTH_DIV10 Register (Offset = E4h) [reset = X]
CONFIG_SYNTH_DIV10 is shown in Figure 9-115 and described in Table 9-118.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-33. CONFIG_SYNTH_DIV10 Register
31

30
RESERVED

28
DISABLE_COR
NER_CAP
R-X

R-7h
23

26
25
RFC_MDM_DEMIQMC0

R-X

20
19
RFC_MDM_DEMIQMC0
R-X

14
13
RFC_MDM_DEMIQMC0
R-X

7
6
LDOVCO_TRIM_OUTPUT
R-X

10
9
LDOVCO_TRIM_OUTPUT
R-X

3
2
SLDO_TRIM_OUTPUT
R-X

Table 9-35. CONFIG_SYNTH_DIV10 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

DISABLE_CORNER_CAP R

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

27-12

RFC_MDM_DEMIQMC0

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization.
Default value holds trim value from production test.

11-6

LDOVCO_TRIM_OUTPU
T

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

5-0

SLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

31-29
28

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

751

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.12 CONFIG_SYNTH_DIV12 Register (Offset = E8h) [reset = X]
CONFIG_SYNTH_DIV12 is shown in Figure 9-116 and described in Table 9-119.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-34. CONFIG_SYNTH_DIV12 Register
31

30
RESERVED

28
DISABLE_COR
NER_CAP
R-X

R-7h
23

26
25
RFC_MDM_DEMIQMC0

R-X

20
19
RFC_MDM_DEMIQMC0
R-X

14
13
RFC_MDM_DEMIQMC0
R-X

7
6
LDOVCO_TRIM_OUTPUT
R-X

10
9
LDOVCO_TRIM_OUTPUT
R-X

3
2
SLDO_TRIM_OUTPUT
R-X

Table 9-36. CONFIG_SYNTH_DIV12 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

DISABLE_CORNER_CAP R

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

27-12

RFC_MDM_DEMIQMC0

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization.
Default value holds trim value from production test.

11-6

LDOVCO_TRIM_OUTPU
T

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

5-0

SLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

31-29
28

752

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.13 CONFIG_SYNTH_DIV15 Register (Offset = ECh) [reset = X]
CONFIG_SYNTH_DIV15 is shown in Figure 9-117 and described in Table 9-120.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-35. CONFIG_SYNTH_DIV15 Register
31

30
RESERVED

28
DISABLE_COR
NER_CAP
R-X

R-7h
23

26
25
RFC_MDM_DEMIQMC0

R-X

20
19
RFC_MDM_DEMIQMC0
R-X

14
13
RFC_MDM_DEMIQMC0
R-X

7
6
LDOVCO_TRIM_OUTPUT
R-X

10
9
LDOVCO_TRIM_OUTPUT
R-X

3
2
SLDO_TRIM_OUTPUT
R-X

Table 9-37. CONFIG_SYNTH_DIV15 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

DISABLE_CORNER_CAP R

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

27-12

RFC_MDM_DEMIQMC0

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization.
Default value holds trim value from production test.

11-6

LDOVCO_TRIM_OUTPU
T

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

5-0

SLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

31-29
28

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

753

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.14 CONFIG_SYNTH_DIV30 Register (Offset = F0h) [reset = X]
CONFIG_SYNTH_DIV30 is shown in Figure 9-118 and described in Table 9-121.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-36. CONFIG_SYNTH_DIV30 Register
31

30
RESERVED

28
DISABLE_COR
NER_CAP
R-X

R-7h
23

26
25
RFC_MDM_DEMIQMC0

R-X

20
19
RFC_MDM_DEMIQMC0
R-X

14
13
RFC_MDM_DEMIQMC0
R-X

7
6
LDOVCO_TRIM_OUTPUT
R-X

10
9
LDOVCO_TRIM_OUTPUT
R-X

3
2
SLDO_TRIM_OUTPUT
R-X

Table 9-38. CONFIG_SYNTH_DIV30 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

DISABLE_CORNER_CAP R

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

27-12

RFC_MDM_DEMIQMC0

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization.
Default value holds trim value from production test.

11-6

LDOVCO_TRIM_OUTPU
T

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

5-0

SLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

31-29
28

754

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.15 CONFIG_MISC_ADC_DIV5 Register (Offset = F4h) [reset = X]
CONFIG_MISC_ADC_DIV5 is shown in Figure 9-119 and described in Table 9-122.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-37. CONFIG_MISC_ADC_DIV5 Register
31

17
RESERVED
R-1h

16
RSSI_OFFSET
R-X

8
QUANTCTLTH
RES
R-5h

RESERVED
R-3FFh
23

7
6
QUANTCTLTHRES
R-5h

20
19
MIN_ALLOWED_RTRIM
R-X

RESERVED
R-3FFh
15

12
RSSI_OFFSET

R-X
4

3
DACTRIM
R-Dh

Table 9-39. CONFIG_MISC_ADC_DIV5 Register Field Descriptions
Field

Type

Reset

Description

31-22

Bit

RESERVED

3FFh

Internal. Only to be used through TI provided API.

21-18

MIN_ALLOWED_RTRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

RESERVED

Internal. Only to be used through TI provided API.

16-9

RSSI_OFFSET

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

755

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.16 CONFIG_MISC_ADC_DIV6 Register (Offset = F8h) [reset = X]
CONFIG_MISC_ADC_DIV6 is shown in Figure 9-120 and described in Table 9-123.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-38. CONFIG_MISC_ADC_DIV6 Register
31

17
RESERVED
R-1h

16
RSSI_OFFSET
R-X

8
QUANTCTLTH
RES
R-5h

RESERVED
R-3FFh
23

7
6
QUANTCTLTHRES
R-5h

20
19
MIN_ALLOWED_RTRIM
R-X

RESERVED
R-3FFh
15

12
RSSI_OFFSET

R-X
4

3
DACTRIM
R-Dh

Table 9-40. CONFIG_MISC_ADC_DIV6 Register Field Descriptions
Field

Type

Reset

Description

31-22

Bit

RESERVED

3FFh

Internal. Only to be used through TI provided API.

21-18

MIN_ALLOWED_RTRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

RESERVED

Internal. Only to be used through TI provided API.

16-9

RSSI_OFFSET

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

Internal. Only to be used through TI provided API.

756

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.17 CONFIG_MISC_ADC_DIV10 Register (Offset = FCh) [reset = X]
CONFIG_MISC_ADC_DIV10 is shown in Figure 9-121 and described in Table 9-124.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-39. CONFIG_MISC_ADC_DIV10 Register
31

17
RESERVED
R-1h

16
RSSI_OFFSET
R-X

8
QUANTCTLTH
RES
R-5h

RESERVED
R-3FFh
23

7
6
QUANTCTLTHRES
R-5h

20
19
MIN_ALLOWED_RTRIM
R-X

RESERVED
R-3FFh
15

12
RSSI_OFFSET

R-X
4

3
DACTRIM
R-Dh

Table 9-41. CONFIG_MISC_ADC_DIV10 Register Field Descriptions
Field

Type

Reset

Description

31-22

Bit

RESERVED

3FFh

Internal. Only to be used through TI provided API.

21-18

MIN_ALLOWED_RTRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

RESERVED

Internal. Only to be used through TI provided API.

16-9

RSSI_OFFSET

Internal. Only to be used through TI provided API.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

757

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.18 CONFIG_MISC_ADC_DIV12 Register (Offset = 100h) [reset = X]
CONFIG_MISC_ADC_DIV12 is shown in Figure 9-122 and described in Table 9-125.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-40. CONFIG_MISC_ADC_DIV12 Register
31

17
RESERVED
R-1h

16
RSSI_OFFSET
R-X

8
QUANTCTLTH
RES
R-5h

RESERVED
R-3FFh
23

7
6
QUANTCTLTHRES
R-5h

20
19
MIN_ALLOWED_RTRIM
R-X

RESERVED
R-3FFh
15

12
RSSI_OFFSET

R-X
4

3
DACTRIM
R-Dh

Table 9-42. CONFIG_MISC_ADC_DIV12 Register Field Descriptions
Field

Type

Reset

Description

31-22

Bit

RESERVED

3FFh

Internal. Only to be used through TI provided API.

21-18

MIN_ALLOWED_RTRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

RESERVED

Internal. Only to be used through TI provided API.

16-9

RSSI_OFFSET

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

Internal. Only to be used through TI provided API.

758

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.19 CONFIG_MISC_ADC_DIV15 Register (Offset = 104h) [reset = X]
CONFIG_MISC_ADC_DIV15 is shown in Figure 9-123 and described in Table 9-126.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-41. CONFIG_MISC_ADC_DIV15 Register
31

17
RESERVED
R-1h

16
RSSI_OFFSET
R-X

8
QUANTCTLTH
RES
R-5h

RESERVED
R-3FFh
23

7
6
QUANTCTLTHRES
R-5h

20
19
MIN_ALLOWED_RTRIM
R-X

RESERVED
R-3FFh
15

12
RSSI_OFFSET

R-X
4

3
DACTRIM
R-Dh

Table 9-43. CONFIG_MISC_ADC_DIV15 Register Field Descriptions
Field

Type

Reset

Description

31-22

Bit

RESERVED

3FFh

Internal. Only to be used through TI provided API.

21-18

MIN_ALLOWED_RTRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

RESERVED

Internal. Only to be used through TI provided API.

16-9

RSSI_OFFSET

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

759

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.20 CONFIG_MISC_ADC_DIV30 Register (Offset = 108h) [reset = X]
CONFIG_MISC_ADC_DIV30 is shown in Figure 9-124 and described in Table 9-127.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-42. CONFIG_MISC_ADC_DIV30 Register
31

17
RESERVED
R-1h

16
RSSI_OFFSET
R-X

8
QUANTCTLTH
RES
R-5h

RESERVED
R-3FFh
23

7
6
QUANTCTLTHRES
R-5h

20
19
MIN_ALLOWED_RTRIM
R-X

RESERVED
R-3FFh
15

12
RSSI_OFFSET

R-X
4

3
DACTRIM
R-Dh

Table 9-44. CONFIG_MISC_ADC_DIV30 Register Field Descriptions
Field

Type

Reset

Description

31-22

Bit

RESERVED

3FFh

Internal. Only to be used through TI provided API.

21-18

MIN_ALLOWED_RTRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

RESERVED

Internal. Only to be used through TI provided API.

16-9

RSSI_OFFSET

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

Internal. Only to be used through TI provided API.

760

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.21 SHDW_DIE_ID_0 Register (Offset = 118h) [reset = X]
SHDW_DIE_ID_0 is shown in Figure 9-125 and described in Table 9-128.
Return to Summary Table.
Shadow of the DIE_ID_0 register in eFuse
Figure 9-43. SHDW_DIE_ID_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ID_31_0
R-X

Table 9-45. SHDW_DIE_ID_0 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ID_31_0

Shadow of the DIE_ID_0 register in eFuse row number 3
Default value depends on eFuse value.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

761

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.22 SHDW_DIE_ID_1 Register (Offset = 11Ch) [reset = X]
SHDW_DIE_ID_1 is shown in Figure 9-126 and described in Table 9-129.
Return to Summary Table.
Shadow of the DIE_ID_1 register in eFuse
Figure 9-44. SHDW_DIE_ID_1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ID_63_32
R-X

Table 9-46. SHDW_DIE_ID_1 Register Field Descriptions
Bit
31-0

762

Field

Type

Reset

Description

ID_63_32

Shadow of the DIE_ID_1 register in eFuse row number 4
Default value depends on eFuse value.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.23 SHDW_DIE_ID_2 Register (Offset = 120h) [reset = X]
SHDW_DIE_ID_2 is shown in Figure 9-127 and described in Table 9-130.
Return to Summary Table.
Shadow of the DIE_ID_2 register in eFuse
Figure 9-45. SHDW_DIE_ID_2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ID_95_64
R-X

Table 9-47. SHDW_DIE_ID_2 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ID_95_64

Shadow of the DIE_ID_2 register in eFuse row number 5
Default value depends on eFuse value.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

763

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.24 SHDW_DIE_ID_3 Register (Offset = 124h) [reset = X]
SHDW_DIE_ID_3 is shown in Figure 9-128 and described in Table 9-131.
Return to Summary Table.
Shadow of the DIE_ID_3 register in eFuse
Figure 9-46. SHDW_DIE_ID_3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ID_127_96
R-X

Table 9-48. SHDW_DIE_ID_3 Register Field Descriptions
Bit
31-0

764

Field

Type

Reset

Description

ID_127_96

Shadow of the DIE_ID_3 register in eFuse row number 6
Default value depends on eFuse value.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.25 SHDW_OSC_BIAS_LDO_TRIM Register (Offset = 138h) [reset = X]
SHDW_OSC_BIAS_LDO_TRIM is shown in Figure 9-129 and described in Table 9-132.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-47. SHDW_OSC_BIAS_LDO_TRIM Register
31

30
RESERVED

28
27
SET_RCOSC_HF_COARSE_RE
SISTOR
R-X

R-X
23
TRIMMAG
R-X

25
TRIMMAG

R-X

20
TRIMIREF
R-X

10
9
VTRIM_COARSE
R-X

4
3
RCOSCHF_CTRIM
R-X

VTRIM_DIG
R-X
7

17
16
ITRIM_DIG_LDO
R-X

Table 9-49. SHDW_OSC_BIAS_LDO_TRIM Register Field Descriptions
Field

Type

Reset

Description

31-29

Bit

RESERVED

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

28-27

SET_RCOSC_HF_COAR
SE_RESISTOR

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

26-23

TRIMMAG

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

22-18

TRIMIREF

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

17-16

ITRIM_DIG_LDO

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

15-12

VTRIM_DIG

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

11-8

VTRIM_COARSE

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

7-0

RCOSCHF_CTRIM

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

765

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.26 SHDW_ANA_TRIM Register (Offset = 13Ch) [reset = X]
SHDW_ANA_TRIM is shown in Figure 9-130 and described in Table 9-133.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-48. SHDW_ANA_TRIM Register
31

29
RESERVED

26
25
BOD_BANDGAP_TRIM_CNF

R-X
23
VDDR_OK_HY
S
R-X

R-X

IPTAT_TRIM

18
VDDR_TRIM

R-X

13
TRIMBOD_INTMODE
R-X

7
6
TRIMBOD_EXTMODE
R-X

24
VDDR_ENABL
E_PG1
R-X

9
TRIMBOD_EXTMODE
R-X

TRIMTEMP
R-X

Table 9-50. SHDW_ANA_TRIM Register Field Descriptions
Bit

766

Field

Type

Reset

Description

31-27

RESERVED

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

26-25

BOD_BANDGAP_TRIM_
CNF

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

VDDR_ENABLE_PG1

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

VDDR_OK_HYS

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

22-21

IPTAT_TRIM

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

20-16

VDDR_TRIM

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

15-11

TRIMBOD_INTMODE

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

10-6

TRIMBOD_EXTMODE

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

5-0

TRIMTEMP

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.27 FLASH_NUMBER Register (Offset = 164h) [reset = X]
FLASH_NUMBER is shown in Figure 9-131 and described in Table 9-134.
Return to Summary Table.
Figure 9-49. FLASH_NUMBER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LOT_NUMBER
R-X

Table 9-51. FLASH_NUMBER Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

LOT_NUMBER

Number of the manufacturing lot that produced this unit.
Default value holds log information from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

767

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.28 FLASH_COORDINATE Register (Offset = 16Ch) [reset = X]
FLASH_COORDINATE is shown in Figure 9-132 and described in Table 9-135.
Return to Summary Table.
Figure 9-50. FLASH_COORDINATE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
XCOORDINATE
YCOORDINATE
R-X
R-X

Table 9-52. FLASH_COORDINATE Register Field Descriptions
Bit

768

Field

Type

Reset

Description

31-16

XCOORDINATE

X coordinate of this unit on the wafer.
Default value holds log information from production test.

15-0

YCOORDINATE

Y coordinate of this unit on the wafer.
Default value holds log information from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.29 FLASH_E_P Register (Offset = 170h) [reset = 17331A33h]
FLASH_E_P is shown in Figure 9-133 and described in Table 9-136.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-51. FLASH_E_P Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PSU
ESU
PVSU
R-17h
R-33h
R-1Ah

4 3
EVSU
R-33h

Table 9-53. FLASH_E_P Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

PSU

17h

Internal. Only to be used through TI provided API.

23-16

ESU

33h

Internal. Only to be used through TI provided API.

15-8

PVSU

1Ah

Internal. Only to be used through TI provided API.

7-0

EVSU

33h

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

769

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.30 FLASH_C_E_P_R Register (Offset = 174h) [reset = 0A0A2000h]
FLASH_C_E_P_R is shown in Figure 9-134 and described in Table 9-137.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-52. FLASH_C_E_P_R Register
31

RVSU
R-Ah
15

14
13
A_EXEZ_SETUP
R-2h

20
19
PV_ACCESS
R-Ah
4

CVSU
R-0h

Table 9-54. FLASH_C_E_P_R Register Field Descriptions

770

Bit

Field

Type

Reset

Description

31-24

RVSU

Internal. Only to be used through TI provided API.

23-16

PV_ACCESS

Internal. Only to be used through TI provided API.

15-12

A_EXEZ_SETUP

Internal. Only to be used through TI provided API.

11-0

CVSU

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.31 FLASH_P_R_PV Register (Offset = 178h) [reset = 026E0200h]
FLASH_P_R_PV is shown in Figure 9-135 and described in Table 9-138.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-53. FLASH_P_R_PV Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PH
RH
PVH
R-2h
R-6Eh
R-2h

4 3
PVH2
R-0h

Table 9-55. FLASH_P_R_PV Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

Internal. Only to be used through TI provided API.

23-16

6Eh

Internal. Only to be used through TI provided API.

15-8

PVH

Internal. Only to be used through TI provided API.

7-0

PVH2

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

771

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.32 FLASH_EH_SEQ Register (Offset = 17Ch) [reset = 0200F000h]
FLASH_EH_SEQ is shown in Figure 9-136 and described in Table 9-139.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-54. FLASH_EH_SEQ Register
31

EH
R-2h
15

14
13
VSTAT
R-Fh

SEQ
R-0h
11

6
5
SM_FREQUENCY
R-0h

Table 9-56. FLASH_EH_SEQ Register Field Descriptions
Bit

772

Field

Type

Reset

Description

31-24

Internal. Only to be used through TI provided API.

23-16

SEQ

Internal. Only to be used through TI provided API.

15-12

VSTAT

Internal. Only to be used through TI provided API.

11-0

SM_FREQUENCY

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.33 FLASH_VHV_E Register (Offset = 180h) [reset = 1h]
FLASH_VHV_E is shown in Figure 9-137 and described in Table 9-140.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-55. FLASH_VHV_E Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
VHV_E_START
VHV_E_STEP_HIGHT
R-0h
R-1h

Table 9-57. FLASH_VHV_E Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

VHV_E_START

Internal. Only to be used through TI provided API.

15-0

VHV_E_STEP_HIGHT

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

773

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.34 FLASH_PP Register (Offset = 184h) [reset = X]
FLASH_PP is shown in Figure 9-138 and described in Table 9-141.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-56. FLASH_PP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PUMP_SU
RESERVED
R-0h
R-X

8 7 6
MAX_PP
R-14h

Table 9-58. FLASH_PP Register Field Descriptions
Bit

774

Field

Type

Reset

Description

31-24

PUMP_SU

Internal. Only to be used through TI provided API.

23-16

RESERVED

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-0

MAX_PP

14h

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.35 FLASH_PROG_EP Register (Offset = 188h) [reset = 0FA00010h]
FLASH_PROG_EP is shown in Figure 9-139 and described in Table 9-142.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-57. FLASH_PROG_EP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
MAX_EP
PROGRAM_PW
R-FA0h
R-10h

Table 9-59. FLASH_PROG_EP Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

MAX_EP

FA0h

Internal. Only to be used through TI provided API.

15-0

PROGRAM_PW

10h

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

775

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.36 FLASH_ERA_PW Register (Offset = 18Ch) [reset = FA0h]
FLASH_ERA_PW is shown in Figure 9-140 and described in Table 9-143.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-58. FLASH_ERA_PW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ERASE_PW
R-FA0h

Table 9-60. FLASH_ERA_PW Register Field Descriptions
Bit
31-0

776

Field

Type

Reset

Description

ERASE_PW

FA0h

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.37 FLASH_VHV Register (Offset = 190h) [reset = X]
FLASH_VHV is shown in Figure 9-141 and described in Table 9-144.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-59. FLASH_VHV Register
31

30
29
RESERVED
R-0h

26
25
TRIM13_P
R-X

22
21
RESERVED
R-0h

18
17
VHV_P
R-X

14
13
RESERVED
R-0h

10
9
TRIM13_E
R-X

6
5
RESERVED
R-0h

1
VHV_E
R-4h

Table 9-61. FLASH_VHV Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

RESERVED

Internal. Only to be used through TI provided API.

27-24

TRIM13_P

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-20

RESERVED

Internal. Only to be used through TI provided API.

19-16

VHV_P

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-12

RESERVED

Internal. Only to be used through TI provided API.

11-8

TRIM13_E

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

7-4

RESERVED

Internal. Only to be used through TI provided API.

3-0

VHV_E

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

777

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.38 FLASH_VHV_PV Register (Offset = 194h) [reset = X]
FLASH_VHV_PV is shown in Figure 9-142 and described in Table 9-145.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-60. FLASH_VHV_PV Register
31

30
29
RESERVED
R-0h

12
11
VCG2P5
R-X

26
25
TRIM13_PV
R-X

22
21
RESERVED
R-0h
6

18
17
VHV_PV
R-8h

VINH
R-1h

Table 9-62. FLASH_VHV_PV Register Field Descriptions
Bit

778

Field

Type

Reset

Description

31-28

RESERVED

Internal. Only to be used through TI provided API.

27-24

TRIM13_PV

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-20

RESERVED

Internal. Only to be used through TI provided API.

19-16

VHV_PV

Internal. Only to be used through TI provided API.

15-8

VCG2P5

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

7-0

VINH

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.39 FLASH_V Register (Offset = 198h) [reset = X]
FLASH_V is shown in Figure 9-143 and described in Table 9-146.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-61. FLASH_V Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VSL_P
VWL_P
V_READ
R-X
R-X
R-X

5 4 3 2
RESERVED
R-X

Table 9-63. FLASH_V Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

VSL_P

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-16

VWL_P

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-8

V_READ

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

7-0

RESERVED

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

779

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.40 USER_ID Register (Offset = 294h) [reset = X]
USER_ID is shown in Figure 9-144 and described in Table 9-147.
Return to Summary Table.
User Identification.
Reading this register or the ICEPICK_DEVICE_ID register is the only support way of identifying a device.
The value of this register will be written to AON_WUC:JTAGUSERCODE by boot FW while in safezone.
Figure 9-62. USER_ID Register
31

30
29
PG_REV
R-X

14
13
PROTOCOL
R-X

VER
R-X
11

24
23
RESERVED
R-X
8

21
20
SEQUENCE
R-X

6
5
RESERVED
R-X

17
PKG
R-X

Table 9-64. USER_ID Register Field Descriptions
Bit

780

Field

Type

Reset

Description

31-28

PG_REV

Field used to distinguish revisions of the device.
Default value holds log information from production test.

27-26

VER

Version number.
0x0: Bits [25:12] of this register has the stated meaning.
Any other setting indicate a different encoding of these bits.
Default value differs depending on partnumber.

25-23

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Default value differs depending on partnumber.

22-19

SEQUENCE

Sequence.
Used to differentiate between marketing/orderable product where
other fields of USER_ID is the same (temp range, flash size, voltage
range etc)
Default value differs depending on partnumber.

18-16

PKG

Package type.
0x0: 4x4mm QFN (RHB) package
0x1: 5x5mm QFN (RSM) package
0x2: 7x7mm QFN (RGZ) package
0x3: Wafer sale package (naked die)
0x4: 2.7x2.7mm WCSP (YFV)
0x5: 7x7mm QFN package with Wettable Flanks
Other values are reserved for future use.
Packages available for a specific device are shown in the device
datasheet.
Default value differs depending on partnumber.

15-12

PROTOCOL

Protocols supported.
0x1: BLE
0x2: RF4CE
0x4: Zigbee/6lowpan
0x8: Proprietary
More than one protocol can be supported on same device - values
above are then combined.
Default value differs depending on partnumber.

11-0

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Default value differs depending on partnumber.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.41 FLASH_OTP_DATA3 Register (Offset = 2B0h) [reset = X]
FLASH_OTP_DATA3 is shown in Figure 9-145 and described in Table 9-148.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-63. FLASH_OTP_DATA3 Register
31

28
27
EC_STEP_SIZE
R-0h

23
EC_STEP_SIZ
E
R-0h

22
DO_PRECOND

20
19
MAX_EC_LEVEL

R-0h
12

16
TRIM_1P7

R-4h
13

R-1h
11

4
3
WAIT_SYSCODE
R-3h

FLASH_SIZE
R-X
7

Table 9-65. FLASH_OTP_DATA3 Register Field Descriptions
Field

Type

Reset

Description

31-23

Bit

EC_STEP_SIZE

Internal. Only to be used through TI provided API.

DO_PRECOND

Internal. Only to be used through TI provided API.

21-18

MAX_EC_LEVEL

Internal. Only to be used through TI provided API.

17-16

TRIM_1P7

Internal. Only to be used through TI provided API.

15-8

FLASH_SIZE

Internal. Only to be used through TI provided API.
Default value differs depending on partnumber.

7-0

WAIT_SYSCODE

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

781

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.42 ANA2_TRIM Register (Offset = 2B4h) [reset = X]
ANA2_TRIM is shown in Figure 9-146 and described in Table 9-149.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-64. ANA2_TRIM Register
31
RCOSCHFCTR
IMFRACT_EN

28
RCOSCHFCTRIMFRACT

R-1h

25
RESERVED

R-1h

24
SET_RCOSC_
HF_FINE_RESI
STOR
R-X

9
DCDC_IPEAK
R-0h

1
DCDC_HIGH_EN_SEL
R-7h

R-X

23
22
SET_RCOSC_ ATESTLF_UDI
HF_FINE_RESI GLDO_IBIAS_T
STOR
RIM
R-X
R-1h
15

19
18
NANOAMP_RES_TRIM

4
DCDC_LOW_EN_SEL
R-7h

R-X

14
RESERVED
R-Fh

7
6
DEAD_TIME_TRIM
R-1h

11
DITHER_EN
R-1h
3

Table 9-66. ANA2_TRIM Register Field Descriptions
Bit

Field

Type

Reset

Description

RCOSCHFCTRIMFRACT
_EN

Internal. Only to be used through TI provided API.

30-26

RCOSCHFCTRIMFRACT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

RESERVED

Internal. Only to be used through TI provided API.

24-23

SET_RCOSC_HF_FINE_
RESISTOR

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

ATESTLF_UDIGLDO_IBI
AS_TRIM

Internal. Only to be used through TI provided API.

21-16

NANOAMP_RES_TRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-12

RESERVED

Internal. Only to be used through TI provided API.

DITHER_EN

Internal. Only to be used through TI provided API.

10-8

DCDC_IPEAK

Internal. Only to be used through TI provided API.

7-6

DEAD_TIME_TRIM

Internal. Only to be used through TI provided API.

5-3

DCDC_LOW_EN_SEL

Internal. Only to be used through TI provided API.

2-0

DCDC_HIGH_EN_SEL

Internal. Only to be used through TI provided API.

782

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.43 LDO_TRIM Register (Offset = 2B8h) [reset = X]
LDO_TRIM is shown in Figure 9-147 and described in Table 9-150.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-65. LDO_TRIM Register
31

30
RESERVED
R-7h

26
VDDR_TRIM_SLEEP
R-X

21
RESERVED
R-1Fh

14
RESERVED
R-7h

5
RESERVED
R-1Fh

12
11
ITRIM_DIGLDO_LOAD
R-0h
4

17
GLDO_CURSRC
R-0h

9
ITRIM_UDIGLDO
R-0h

1
VTRIM_DELTA
R-3h

Table 9-67. LDO_TRIM Register Field Descriptions
Bit

Field

Type

Reset

Description

31-29

RESERVED

Internal. Only to be used through TI provided API.

28-24

VDDR_TRIM_SLEEP

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-19

RESERVED

1Fh

Internal. Only to be used through TI provided API.

18-16

GLDO_CURSRC

Internal. Only to be used through TI provided API.

15-13

RESERVED

Internal. Only to be used through TI provided API.

12-11

ITRIM_DIGLDO_LOAD

Internal. Only to be used through TI provided API.

10-8

ITRIM_UDIGLDO

Internal. Only to be used through TI provided API.

7-3

RESERVED

1Fh

Internal. Only to be used through TI provided API.

2-0

VTRIM_DELTA

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

783

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.44 BAT_RC_LDO_TRIM Register (Offset = 2BCh) [reset = X]
BAT_RC_LDO_TRIM is shown in Figure 9-148 and described in Table 9-151.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-66. BAT_RC_LDO_TRIM Register
31

RESERVED
R-Fh
23

RESERVED
R-Fh
15

VTRIM_UDIG
R-X
12

RESERVED
R-Fh
7

25
VTRIM_BOD
R-X

10
9
RCOSCHF_ITUNE_TRIM
R-0h
2

RESERVED
R-3Fh

0
MEASUREPER
R-0h

Table 9-68. BAT_RC_LDO_TRIM Register Field Descriptions
Bit

784

Field

Type

Reset

Description

31-28

RESERVED

Internal. Only to be used through TI provided API.

27-24

VTRIM_BOD

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-20

RESERVED

Internal. Only to be used through TI provided API.

19-16

VTRIM_UDIG

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-12

RESERVED

Internal. Only to be used through TI provided API.

11-8

RCOSCHF_ITUNE_TRIM

Internal. Only to be used through TI provided API.

7-2

RESERVED

3Fh

Internal. Only to be used through TI provided API.

1-0

MEASUREPER

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.45 MAC_BLE_0 Register (Offset = 2E8h) [reset = X]
MAC_BLE_0 is shown in Figure 9-149 and described in Table 9-152.
Return to Summary Table.
MAC BLE Address 0
Figure 9-67. MAC_BLE_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR_0_31
R-X

Table 9-69. MAC_BLE_0 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ADDR_0_31

The first 32-bits of the 64-bit MAC BLE address
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

785

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.46 MAC_BLE_1 Register (Offset = 2ECh) [reset = X]
MAC_BLE_1 is shown in Figure 9-150 and described in Table 9-153.
Return to Summary Table.
MAC BLE Address 1
Figure 9-68. MAC_BLE_1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR_32_63
R-X

Table 9-70. MAC_BLE_1 Register Field Descriptions
Bit
31-0

786

Field

Type

Reset

Description

ADDR_32_63

The last 32-bits of the 64-bit MAC BLE address
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.47 MAC_15_4_0 Register (Offset = 2F0h) [reset = X]
MAC_15_4_0 is shown in Figure 9-151 and described in Table 9-154.
Return to Summary Table.
MAC IEEE 802.15.4 Address 0
Figure 9-69. MAC_15_4_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR_0_31
R-X

Table 9-71. MAC_15_4_0 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ADDR_0_31

The first 32-bits of the 64-bit MAC 15.4 address
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

787

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.48 MAC_15_4_1 Register (Offset = 2F4h) [reset = X]
MAC_15_4_1 is shown in Figure 9-152 and described in Table 9-155.
Return to Summary Table.
MAC IEEE 802.15.4 Address 1
Figure 9-70. MAC_15_4_1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR_32_63
R-X

Table 9-72. MAC_15_4_1 Register Field Descriptions
Bit
31-0

788

Field

Type

Reset

Description

ADDR_32_63

The last 32-bits of the 64-bit MAC 15.4 address
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.49 FLASH_OTP_DATA4 Register (Offset = 308h) [reset = 98989F9Fh]
FLASH_OTP_DATA4 is shown in Figure 9-153 and described in Table 9-156.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-71. FLASH_OTP_DATA4 Register
31
STANDBY_MO
DE_SEL_INT_
WRT
R-1h

30
29
STANDBY_PW_SEL_INT_WRT

28
DIS_STANDBY
_INT_WRT

27
DIS_IDLE_INT
_WRT

R-0h

R-1h

23
STANDBY_MO
DE_SEL_EXT_
WRT
R-1h

22
21
STANDBY_PW_SEL_EXT_WRT

R-0h

R-1h

15
STANDBY_MO
DE_SEL_INT_
RD
R-1h

14
13
STANDBY_PW_SEL_INT_RD

12
DIS_STANDBY
_INT_RD

11
DIS_IDLE_INT
_RD

R-0h

R-1h

7
STANDBY_MO
DE_SEL_EXT_
RD
R-1h

6
5
STANDBY_PW_SEL_EXT_RD

R-0h

20
19
DIS_STANDBY DIS_IDLE_EXT
_EXT_WRT
_WRT

4
3
DIS_STANDBY DIS_IDLE_EXT
_EXT_RD
_RD
R-1h

R-1h

25
VIN_AT_X_INT_WRT

R-0h
18

17
VIN_AT_X_EXT_WRT

R-0h
10

9
VIN_AT_X_INT_RD

R-7h
2

1
VIN_AT_X_EXT_RD

R-7h

Table 9-73. FLASH_OTP_DATA4 Register Field Descriptions
Bit

Field

Type

Reset

Description

STANDBY_MODE_SEL_I
NT_WRT

Internal. Only to be used through TI provided API.

30-29

STANDBY_PW_SEL_INT
_WRT

Internal. Only to be used through TI provided API.

DIS_STANDBY_INT_WR
T

Internal. Only to be used through TI provided API.

DIS_IDLE_INT_WRT

Internal. Only to be used through TI provided API.

26-24

VIN_AT_X_INT_WRT

Internal. Only to be used through TI provided API.

STANDBY_MODE_SEL_
EXT_WRT

Internal. Only to be used through TI provided API.

22-21

STANDBY_PW_SEL_EXT R
_WRT

Internal. Only to be used through TI provided API.

DIS_STANDBY_EXT_WR R
T

Internal. Only to be used through TI provided API.

DIS_IDLE_EXT_WRT

Internal. Only to be used through TI provided API.

18-16

VIN_AT_X_EXT_WRT

Internal. Only to be used through TI provided API.

STANDBY_MODE_SEL_I
NT_RD

Internal. Only to be used through TI provided API.

14-13

STANDBY_PW_SEL_INT
_RD

Internal. Only to be used through TI provided API.

DIS_STANDBY_INT_RD

Internal. Only to be used through TI provided API.

DIS_IDLE_INT_RD

Internal. Only to be used through TI provided API.

10-8

VIN_AT_X_INT_RD

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

789

Factory Configuration (FCFG)

www.ti.com

Table 9-73. FLASH_OTP_DATA4 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

STANDBY_MODE_SEL_
EXT_RD

Internal. Only to be used through TI provided API.

STANDBY_PW_SEL_EXT R
_RD

Internal. Only to be used through TI provided API.

DIS_STANDBY_EXT_RD

Internal. Only to be used through TI provided API.

DIS_IDLE_EXT_RD

Internal. Only to be used through TI provided API.

2-0

VIN_AT_X_EXT_RD

Internal. Only to be used through TI provided API.

7
6-5

790

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.50 MISC_TRIM Register (Offset = 30Ch) [reset = FFFFFF33h]
MISC_TRIM is shown in Figure 9-154 and described in Table 9-157.
Return to Summary Table.
Miscellaneous Trim Parameters
Figure 9-72. MISC_TRIM Register
31

12
11
RESERVED
R-00FFFFFFh

24
23
RESERVED
R-00FFFFFFh
8

4
3
TEMPVSLOPE
R-33h

Table 9-74. MISC_TRIM Register Field Descriptions
Field

Type

Reset

31-8

Bit

RESERVED

00FFFFFFh Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

TEMPVSLOPE

33h

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Signed byte value representing the TEMP slope with battery voltage,
in degrees C / V, with four fractional bits.

Device Configuration

791

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.51 RCOSC_HF_TEMPCOMP Register (Offset = 310h) [reset = 3h]
RCOSC_HF_TEMPCOMP is shown in Figure 9-155 and described in Table 9-158.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-73. RCOSC_HF_TEMPCOMP Register
31

28
27
FINE_RESISTOR
R-0h

12
11
10
CTRIMFRACT_QUAD
R-0h

20
19
CTRIM
R-0h

4
3
2
CTRIMFRACT_SLOPE
R-3h

Table 9-75. RCOSC_HF_TEMPCOMP Register Field Descriptions
Bit

792

Field

Type

Reset

Description

31-24

FINE_RESISTOR

Internal. Only to be used through TI provided API.

23-16

CTRIM

Internal. Only to be used through TI provided API.

15-8

CTRIMFRACT_QUAD

Internal. Only to be used through TI provided API.

7-0

CTRIMFRACT_SLOPE

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.52 TRIM_CAL_REVISION Register (Offset = 314h) [reset = X]
TRIM_CAL_REVISION is shown in Figure 9-156 and described in Table 9-159.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-74. TRIM_CAL_REVISION Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FT1
R-X

8 7
MP1
R-X

Table 9-76. TRIM_CAL_REVISION Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

FT1

Internal. Only to be used through TI provided API.
Default value holds log information from production test.

15-0

MP1

Internal. Only to be used through TI provided API.
Default value holds log information from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

793

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.53 ICEPICK_DEVICE_ID Register (Offset = 318h) [reset = 2B9BE02Fh]
ICEPICK_DEVICE_ID is shown in Figure 9-157 and described in Table 9-160.
Return to Summary Table.
IcePick Device Identification
Reading this register or the USER_ID register is the only support way of identifying a device.
Figure 9-75. ICEPICK_DEVICE_ID Register
31

30
29
PG_REV
R-2h

14
13
WAFER_ID
R-B9BEh

22
21
WAFER_ID
R-B9BEh

6
5
4
MANUFACTURER_ID
R-2Fh

Table 9-77. ICEPICK_DEVICE_ID Register Field Descriptions
Bit

794

Field

Type

Reset

Description

31-28

PG_REV

Field used to distinguish revisions of the device.

27-12

WAFER_ID

B9BEh

Field used to identify silicon die.

11-0

MANUFACTURER_ID

2Fh

Manufacturer code.
0x02F: Texas Instruments

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.54 FCFG1_REVISION Register (Offset = 31Ch) [reset = 26h]
FCFG1_REVISION is shown in Figure 9-158 and described in Table 9-161.
Return to Summary Table.
Factory Configuration (FCFG1) Revision
Figure 9-76. FCFG1_REVISION Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
REV
R-26h

Table 9-78. FCFG1_REVISION Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

REV

26h

The revision number of the FCFG1 layout. This value will be read by
application SW in order to determine which FCFG1 parameters that
have valid values. This revision number must be incremented by 1
before any devices are to be produced if the FCFG1 layout has
changed since the previous production of devices.
Value migth change without warning.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

795

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.55 MISC_OTP_DATA Register (Offset = 320h) [reset = X]
MISC_OTP_DATA is shown in Figure 9-159 and described in Table 9-162.
Return to Summary Table.
Misc OTP Data
Figure 9-77. MISC_OTP_DATA Register
31

30
29
RCOSC_HF_ITUNE
R-0h

26
25
RCOSC_HF_CRIM
R-0h

22
21
RCOSC_HF_CRIM
R-0h

15
PER_M
R-1h

13
PER_E
R-4h

17
PER_M
R-1h

10
9
MIN_ALLOWED_RTRIM_DIV5
R-X

4
3
TEST_PROGRAM_REV
R-X

Table 9-79. MISC_OTP_DATA Register Field Descriptions
Bit

796

Field

Type

Reset

Description

31-28

RCOSC_HF_ITUNE

Internal. Only to be used through TI provided API.

27-20

RCOSC_HF_CRIM

Internal. Only to be used through TI provided API.

19-15

PER_M

Internal. Only to be used through TI provided API.

14-12

PER_E

Internal. Only to be used through TI provided API.

11-8

MIN_ALLOWED_RTRIM_
DIV5

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

7-0

TEST_PROGRAM_REV

The revision of the test program used in the production process
when FCFG1 was programmed.
Value migth change without warning.
Default value holds log information from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.56 IOCONF Register (Offset = 344h) [reset = X]
IOCONF is shown in Figure 9-160 and described in Table 9-163.
Return to Summary Table.
IO Configuration
Figure 9-78. IOCONF Register
31

11
10
RESERVED
R-01FFFFFEh

24
23
RESERVED
R-01FFFFFEh
8

3
GPIO_CNT
R-X

Table 9-80. IOCONF Register Field Descriptions
Field

Type

Reset

31-7

Bit

RESERVED

01FFFFFEh Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

GPIO_CNT

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Number of available DIOs.
Default value differs depending on partnumber.

Device Configuration

797

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.57 CONFIG_IF_ADC Register (Offset = 34Ch) [reset = X]
CONFIG_IF_ADC is shown in Figure 9-161 and described in Table 9-164.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-79. CONFIG_IF_ADC Register
31

FF2ADJ
R-3h
23

INT3ADJ
R-6h
15

2
IFANALDO_TRIM_OUTPUT
R-X

INT2ADJ
R-Dh

6
IFDIGLDO_TRIM_OUTPUT
R-X

FF1ADJ
R-0h

AAFCAP
R-3h
7

25
FF3ADJ
R-4h

9
8
IFDIGLDO_TRIM_OUTPUT
R-X
1

Table 9-81. CONFIG_IF_ADC Register Field Descriptions
Bit

798

Field

Type

Reset

Description

31-28

FF2ADJ

Internal. Only to be used through TI provided API.

27-24

FF3ADJ

Internal. Only to be used through TI provided API.

23-20

INT3ADJ

Internal. Only to be used through TI provided API.

19-16

FF1ADJ

Internal. Only to be used through TI provided API.

15-14

AAFCAP

Internal. Only to be used through TI provided API.

13-10

INT2ADJ

Internal. Only to be used through TI provided API.

9-5

IFDIGLDO_TRIM_OUTPU R
T

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

4-0

IFANALDO_TRIM_OUTP
UT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.58 CONFIG_OSC_TOP Register (Offset = 350h) [reset = X]
CONFIG_OSC_TOP is shown in Figure 9-162 and described in Table 9-165.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-80. CONFIG_OSC_TOP Register
31

28
27
XOSC_HF_ROW_Q12
R-Fh

20
19
XOSC_HF_COLUMN_Q12
R-Fh

13
12
XOSC_HF_COLUMN_Q12
R-Fh

9
8
RCOSCLF_CTUNE_TRIM
R-X

5
4
RCOSCLF_CTUNE_TRIM
R-X

1
0
RCOSCLF_RTUNE_TRIM
R-0h

RESERVED
R-3h

25
24
XOSC_HF_COLUMN_Q12
R-Fh
17

Table 9-82. CONFIG_OSC_TOP Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

RESERVED

Internal. Only to be used through TI provided API.

29-26

XOSC_HF_ROW_Q12

Internal. Only to be used through TI provided API.

25-10

XOSC_HF_COLUMN_Q1
2

Internal. Only to be used through TI provided API.

9-2

RCOSCLF_CTUNE_TRIM R

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

1-0

RCOSCLF_RTUNE_TRIM R

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

799

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.59 CONFIG_RF_FRONTEND Register (Offset = 354h) [reset = X]
CONFIG_RF_FRONTEND is shown in Figure 9-163 and described in Table 9-166.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-81. CONFIG_RF_FRONTEND Register
31

IFAMP_IB
R-7h
23

15
14
CTL_PA0_TRIM
R-X
7
RESERVED
R-3Fh

LNA_IB
R-X

21
IFAMP_TRIM
R-0h

17
CTL_PA0_TRIM
R-X

13
PATRIMCOMP
LETE_N
R-X

10
RESERVED

3
RFLDO_TRIM_OUTPUT
R-X

R-3Fh
2

Table 9-83. CONFIG_RF_FRONTEND Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-19

IFAMP_TRIM

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

PATRIMCOMPLETE_N

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

12-7

RESERVED

3Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

800

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.60 CONFIG_SYNTH Register (Offset = 358h) [reset = X]
CONFIG_SYNTH is shown in Figure 9-164 and described in Table 9-167.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-82. CONFIG_SYNTH Register
31

30
RESERVED

28
DISABLE_COR
NER_CAP
R-X

R-7h
23

26
25
RFC_MDM_DEMIQMC0

R-X

20
19
RFC_MDM_DEMIQMC0
R-X

14
13
RFC_MDM_DEMIQMC0
R-X

7
6
LDOVCO_TRIM_OUTPUT
R-X

10
9
LDOVCO_TRIM_OUTPUT
R-X

3
2
SLDO_TRIM_OUTPUT
R-X

Table 9-84. CONFIG_SYNTH Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

DISABLE_CORNER_CAP R

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

27-12

RFC_MDM_DEMIQMC0

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization only
on cc13x0.
Default value holds trim value from production test.

11-6

LDOVCO_TRIM_OUTPU
T

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

5-0

SLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

31-29
28

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

801

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.61 SOC_ADC_ABS_GAIN Register (Offset = 35Ch) [reset = X]
SOC_ADC_ABS_GAIN is shown in Figure 9-165 and described in Table 9-168.
Return to Summary Table.
AUX_ADC Gain in Absolute Reference Mode
Figure 9-83. SOC_ADC_ABS_GAIN Register
31

24
23
RESERVED
R-FFFFh

9
8
7
6
SOC_ADC_ABS_GAIN_TEMP1
R-X

Table 9-85. SOC_ADC_ABS_GAIN Register Field Descriptions
Bit

802

Field

Type

Reset

Description

31-16

RESERVED

FFFFh

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

SOC_ADC_ABS_GAIN_T
EMP1

SOC_ADC gain in absolute reference mode at temperature 1 (30C).
Calculated in production test..
Default value holds log information from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.62 SOC_ADC_REL_GAIN Register (Offset = 360h) [reset = X]
SOC_ADC_REL_GAIN is shown in Figure 9-166 and described in Table 9-169.
Return to Summary Table.
AUX_ADC Gain in Relative Reference Mode
Figure 9-84. SOC_ADC_REL_GAIN Register
31

24
23
RESERVED
R-FFFFh

9
8
7
6
SOC_ADC_REL_GAIN_TEMP1
R-X

Table 9-86. SOC_ADC_REL_GAIN Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

FFFFh

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

SOC_ADC_REL_GAIN_T
EMP1

SOC_ADC gain in relative reference mode at temperature 1 (30C).
Calculated in production test..
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

803

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.63 SOC_ADC_OFFSET_INT Register (Offset = 368h) [reset = X]
SOC_ADC_OFFSET_INT is shown in Figure 9-167 and described in Table 9-170.
Return to Summary Table.
AUX_ADC Temperature Offsets in Absolute Reference Mode
Figure 9-85. SOC_ADC_OFFSET_INT Register
31

28
27
RESERVED
R-FFh

21
20
19
18
SOC_ADC_REL_OFFSET_TEMP1
R-X

12
11
RESERVED
R-FFh

5
4
3
2
SOC_ADC_ABS_OFFSET_TEMP1
R-X

Table 9-87. SOC_ADC_OFFSET_INT Register Field Descriptions
Bit

804

Field

Type

Reset

Description

31-24

RESERVED

FFh

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-16

SOC_ADC_REL_OFFSET R
_TEMP1

SOC_ADC offset in relative reference mode at temperature 1 (30C).
Signed 8-bit number. Calculated in production test..
Default value holds trim value from production test.

15-8

RESERVED

FFh

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

SOC_ADC_ABS_OFFSE
T_TEMP1

SOC_ADC offset in absolute reference mode at temperature 1
(30C). Signed 8-bit number. Calculated in production test..
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.64 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register (Offset = 36Ch) [reset = X]
SOC_ADC_REF_TRIM_AND_OFFSET_EXT is shown in Figure 9-168 and described in Table 9-171.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-86. SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register
31

RESERVED
R-03FFFFFEh
23

20
RESERVED
R-03FFFFFEh

12
RESERVED
R-03FFFFFEh

RESERVED
R-03FFFFFEh

3
2
SOC_ADC_REF_VOLTAGE_TRIM_TEMP1
R-X

Table 9-88. SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register Field Descriptions
Bit

Field

Type

Reset

31-6

RESERVED

03FFFFFEh Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

5-0

SOC_ADC_REF_VOLTA
GE_TRIM_TEMP1

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

Device Configuration

805

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.65 AMPCOMP_TH1 Register (Offset = 370h) [reset = FF7B828Eh]
AMPCOMP_TH1 is shown in Figure 9-169 and described in Table 9-172.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-87. AMPCOMP_TH1 Register
31

21
20
HPMRAMP3_LTH
R-1Eh

13
12
HPMRAMP3_HTH
R-20h

3
2
HPMRAMP1_TH
R-Eh

RESERVED
R-FFh
23

7
6
IBIASCAP_LPTOHP_OL_CNT
R-Ah

16
RESERVED
R-3h

9
8
IBIASCAP_LPTOHP_OL_CNT
R-Ah
1

Table 9-89. AMPCOMP_TH1 Register Field Descriptions
Bit

806

Field

Type

Reset

Description

31-24

RESERVED

FFh

Internal. Only to be used through TI provided API.

23-18

HPMRAMP3_LTH

1Eh

Internal. Only to be used through TI provided API.

17-16

RESERVED

Internal. Only to be used through TI provided API.

15-10

HPMRAMP3_HTH

20h

Internal. Only to be used through TI provided API.

9-6

IBIASCAP_LPTOHP_OL_ R
CNT

Internal. Only to be used through TI provided API.

5-0

HPMRAMP1_TH

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.66 AMPCOMP_TH2 Register (Offset = 374h) [reset = 6B8B0303h]
AMPCOMP_TH2 is shown in Figure 9-170 and described in Table 9-173.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-88. AMPCOMP_TH2 Register
31

29
28
LPMUPDATE_LTH
R-1Ah

21
20
LPMUPDATE_HTM
R-22h

13
12
ADC_COMP_AMPTH_LPM
R-0h

5
4
ADC_COMP_AMPTH_HPM
R-0h

24
RESERVED
R-3h

16
RESERVED
R-3h

8
RESERVED
R-3h

0
RESERVED
R-3h

Table 9-90. AMPCOMP_TH2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-26

LPMUPDATE_LTH

1Ah

Internal. Only to be used through TI provided API.

25-24

RESERVED

Internal. Only to be used through TI provided API.

23-18

LPMUPDATE_HTM

22h

Internal. Only to be used through TI provided API.

17-16

RESERVED

Internal. Only to be used through TI provided API.

15-10

ADC_COMP_AMPTH_LP
M

Internal. Only to be used through TI provided API.

9-8

RESERVED

Internal. Only to be used through TI provided API.

7-2

ADC_COMP_AMPTH_HP R
M

Internal. Only to be used through TI provided API.

1-0

RESERVED

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

807

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.67 AMPCOMP_CTRL1 Register (Offset = 378h) [reset = FF183F47h]
AMPCOMP_CTRL1 is shown in Figure 9-171 and described in Table 9-174.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-89. AMPCOMP_CTRL1 Register
31
RESERVED
R-1h

30
AMPCOMP_RE
Q_MODE
R-1h

RESERVED
R-3Fh

22
21
IBIAS_OFFSET
R-1h

18
IBIAS_INIT
R-8h

12
11
LPM_IBIAS_WAIT_CNT_FINAL
R-3Fh

CAP_STEP
R-4h

2
1
IBIASCAP_HPTOLP_OL_CNT
R-7h

Table 9-91. AMPCOMP_CTRL1 Register Field Descriptions

808

Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

AMPCOMP_REQ_MODE

Internal. Only to be used through TI provided API.

29-24

RESERVED

3Fh

Internal. Only to be used through TI provided API.

23-20

IBIAS_OFFSET

Internal. Only to be used through TI provided API.

19-16

IBIAS_INIT

Internal. Only to be used through TI provided API.

15-8

LPM_IBIAS_WAIT_CNT_
FINAL

3Fh

Internal. Only to be used through TI provided API.

7-4

CAP_STEP

Internal. Only to be used through TI provided API.

3-0

IBIASCAP_HPTOLP_OL_ R
CNT

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.68 ANABYPASS_VALUE2 Register (Offset = 37Ch) [reset = FFFFC3FFh]
ANABYPASS_VALUE2 is shown in Figure 9-172 and described in Table 9-175.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-90. ANABYPASS_VALUE2 Register
31

15
14
RESERVED
R-0003FFFFh

24
23
RESERVED
R-0003FFFFh

8
7
6
5
XOSC_HF_IBIASTHERM
R-3FFh

Table 9-92. ANABYPASS_VALUE2 Register Field Descriptions
Field

Type

Reset

Description

31-14

Bit

RESERVED

0003FFFFh

Internal. Only to be used through TI provided API.

13-0

XOSC_HF_IBIASTHERM

3FFh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

809

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.69 CONFIG_MISC_ADC Register (Offset = 380h) [reset = X]
CONFIG_MISC_ADC is shown in Figure 9-173 and described in Table 9-176.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-91. CONFIG_MISC_ADC Register
31

RESERVED
R-3FFh
23
RESERVED

20
19
MIN_ALLOWED_RTRIM

R-3FFh

R-X

12
RSSI_OFFSET

17
16
RSSITRIMCOM RSSI_OFFSET
PLETE_N
R-X
R-X

8
QUANTCTLTH
RES
R-5h

R-X
7
6
QUANTCTLTHRES
R-5h

3
DACTRIM
R-Dh

Table 9-93. CONFIG_MISC_ADC Register Field Descriptions
Bit

810

Field

Type

Reset

Description

31-22

RESERVED

3FFh

Internal. Only to be used through TI provided API.

21-18

MIN_ALLOWED_RTRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

RSSITRIMCOMPLETE_N

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

16-9

RSSI_OFFSET

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.70 VOLT_TRIM Register (Offset = 388h) [reset = X]
VOLT_TRIM is shown in Figure 9-174 and described in Table 9-177.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-92. VOLT_TRIM Register
31

30
RESERVED
R-7h

26
VDDR_TRIM_HH
R-X

22
RESERVED
R-7h

18
VDDR_TRIM_H
R-X

14
RESERVED
R-7h

10
VDDR_TRIM_SLEEP_H
R-X

6
RESERVED
R-7h

2
TRIMBOD_H
R-X

Table 9-94. VOLT_TRIM Register Field Descriptions
Bit

Field

Type

Reset

Description

31-29

RESERVED

Internal. Only to be used through TI provided API.

28-24

VDDR_TRIM_HH

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-21

RESERVED

Internal. Only to be used through TI provided API.

20-16

VDDR_TRIM_H

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-13

RESERVED

Internal. Only to be used through TI provided API.

12-8

VDDR_TRIM_SLEEP_H

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

7-5

RESERVED

Internal. Only to be used through TI provided API.

4-0

TRIMBOD_H

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

811

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.71 OSC_CONF Register (Offset = 38Ch) [reset = X]
OSC_CONF is shown in Figure 9-175 and described in Table 9-178.
Return to Summary Table.
OSC Configuration
Figure 9-93. OSC_CONF Register
31

30
RESERVED

29
ADC_SH_VBU
F_EN

R-3h

R-1h

22
21
XOSCLF_CMIRRWR_RATIO

28
27
ADC_SH_MOD ATESTLF_RC
E_EN
OSCLF_IBIAS_
TRIM
R-1h
R-0h

26
25
XOSCLF_REGULATOR_TRIM

24
XOSCLF_CMIR
RWR_RATIO

R-0h

20
19
XOSC_HF_FAST_START

18
XOSC_OPTIO
N

17
HPOSC_OPTI
ON

R-1h

R-X

R-0h
15

14
13
HPOSC_CURRMIRR_RATIO
R-X

7
HPOSC_FILTE
R_EN
R-X

6
5
HPOSC_BIAS_RECHARGE_DE
LAY
R-X

16
HPOSC_BIAS_
HOLD_MODE_
EN
R-1h

10
9
HPOSC_BIAS_RES_SET
R-X

3
RESERVED

2
1
HPOSC_SERIES_CAP

R-X

0
HPOSC_DIV3_
BYPASS
R-X

Table 9-95. OSC_CONF Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ADC_SH_VBUF_EN

Trim value for
DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN.

ADC_SH_MODE_EN

Trim value for
DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN.

ATESTLF_RCOSCLF_IBI
AS_TRIM

Trim value for
DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM.

26-25

XOSCLF_REGULATOR_
TRIM

Trim value for
DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM.

24-21

XOSCLF_CMIRRWR_RA
TIO

Trim value for
DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO.

20-19

XOSC_HF_FAST_START R

Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START.

XOSC_OPTION

0: XOSC_HF unavailable (may not be bonded out)
1: XOSC_HF available (default)
Default value differs depending on partnumber.

HPOSC_OPTION

Internal. Only to be used through TI provided API.
Default value differs depending on partnumber.

HPOSC_BIAS_HOLD_M
ODE_EN

Internal. Only to be used through TI provided API.

15-12

HPOSC_CURRMIRR_RA
TIO

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

11-8

HPOSC_BIAS_RES_SET

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

HPOSC_FILTER_EN

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

31-30

812

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

Table 9-95. OSC_CONF Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6-5

HPOSC_BIAS_RECHAR
GE_DELAY

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

4-3

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Default value holds trim value from production test.

2-1

HPOSC_SERIES_CAP

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

HPOSC_DIV3_BYPASS

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

813

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.72 FREQ_OFFSET Register (Offset = 390h) [reset = X]
FREQ_OFFSET is shown in Figure 9-176 and described in Table 9-179.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-94. FREQ_OFFSET Register
31

12
11
10
HPOSC_COMP_P1
R-X

24
23
22
HPOSC_COMP_P0
R-X
8

4
3
HPOSC_COMP_P2
R-X

Table 9-96. FREQ_OFFSET Register Field Descriptions
Bit

814

Field

Type

Reset

Description

31-16

HPOSC_COMP_P0

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-8

HPOSC_COMP_P1

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

7-0

HPOSC_COMP_P2

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.73 CAP_TRIM Register (Offset = 394h) [reset = FFFFFFFFh]
CAP_TRIM is shown in Figure 9-177 and described in Table 9-180.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-95. CAP_TRIM Register
31

25
24
23
22
FLUX_CAP_0P28_TRIM
R-FFFFh

8
7
6
FLUX_CAP_0P4_TRIM
R-FFFFh

Table 9-97. CAP_TRIM Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

FLUX_CAP_0P28_TRIM

FFFFh

Internal. Only to be used through TI provided API.

15-0

FLUX_CAP_0P4_TRIM

FFFFh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

815

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.74 MISC_OTP_DATA_1 Register (Offset = 398h) [reset = E00403F8h]
MISC_OTP_DATA_1 is shown in Figure 9-178 and described in Table 9-181.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-96. MISC_OTP_DATA_1 Register
31

30
RESERVED
R-7h

23
22
LP_BUF_ITRIM
R-0h
15

21
20
DBLR_LOOP_FILTER_RESET_
VOLTAGE
R-0h

13
12
HPM_IBIAS_WAIT_CNT
R-100h

28
27
PEAK_DET_ITRIM
R-0h

6
5
LPM_IBIAS_WAIT_CNT
R-3Fh

25
HP_BUF_ITRIM
R-0h

18
17
HPM_IBIAS_WAIT_CNT

R-100h
9
8
LPM_IBIAS_WAIT_CNT
R-3Fh
1

IDAC_STEP
R-8h

Table 9-98. MISC_OTP_DATA_1 Register Field Descriptions
Bit

816

Field

Type

Reset

Description

31-29

RESERVED

Internal. Only to be used through TI provided API.

28-27

PEAK_DET_ITRIM

Internal. Only to be used through TI provided API.

26-24

HP_BUF_ITRIM

Internal. Only to be used through TI provided API.

23-22

LP_BUF_ITRIM

Internal. Only to be used through TI provided API.

21-20

DBLR_LOOP_FILTER_R
ESET_VOLTAGE

Internal. Only to be used through TI provided API.

19-10

HPM_IBIAS_WAIT_CNT

100h

Internal. Only to be used through TI provided API.

9-4

LPM_IBIAS_WAIT_CNT

3Fh

Internal. Only to be used through TI provided API.

3-0

IDAC_STEP

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.75 PWD_CURR_20C Register (Offset = 39Ch) [reset = 080BA608h]
PWD_CURR_20C is shown in Figure 9-179 and described in Table 9-182.
Return to Summary Table.
Power Down Current Control 20C
Figure 9-97. PWD_CURR_20C Register
31

28
27
26
DELTA_CACHE_REF
R-8h

12
11
10
DELTA_XOSC_LPM
R-A6h

20
19
18
DELTA_RFMEM_RET
R-Bh
4
3
BASELINE
R-8h

Table 9-99. PWD_CURR_20C Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

DELTA_CACHE_REF

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

A6h

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

817

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.76 PWD_CURR_35C Register (Offset = 3A0h) [reset = 0C10A50Ah]
PWD_CURR_35C is shown in Figure 9-180 and described in Table 9-183.
Return to Summary Table.
Power Down Current Control 35C
Figure 9-98. PWD_CURR_35C Register
31

28
27
26
DELTA_CACHE_REF
R-Ch

12
11
10
DELTA_XOSC_LPM
R-A5h

20
19
18
DELTA_RFMEM_RET
R-10h
4
3
BASELINE
R-Ah

Table 9-100. PWD_CURR_35C Register Field Descriptions
Bit

818

Field

Type

Reset

Description

31-24

DELTA_CACHE_REF

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

10h

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

A5h

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.77 PWD_CURR_50C Register (Offset = 3A4h) [reset = 1218A20Dh]
PWD_CURR_50C is shown in Figure 9-181 and described in Table 9-184.
Return to Summary Table.
Power Down Current Control 50C
Figure 9-99. PWD_CURR_50C Register
31

28
27
26
DELTA_CACHE_REF
R-12h

12
11
10
DELTA_XOSC_LPM
R-A2h

20
19
18
DELTA_RFMEM_RET
R-18h
4
3
BASELINE
R-Dh

Table 9-101. PWD_CURR_50C Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

DELTA_CACHE_REF

12h

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

18h

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

A2h

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

819

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.78 PWD_CURR_65C Register (Offset = 3A8h) [reset = 1C259C14h]
PWD_CURR_65C is shown in Figure 9-182 and described in Table 9-185.
Return to Summary Table.
Power Down Current Control 65C
Figure 9-100. PWD_CURR_65C Register
31

28
27
26
DELTA_CACHE_REF
R-1Ch

12
11
10
DELTA_XOSC_LPM
R-9Ch

20
19
18
DELTA_RFMEM_RET
R-25h
4
3
BASELINE
R-14h

Table 9-102. PWD_CURR_65C Register Field Descriptions
Bit

820

Field

Type

Reset

Description

31-24

DELTA_CACHE_REF

1Ch

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

25h

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

9Ch

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

14h

Worst-case baseline maximum powerdown current, in units of 0.5uA

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.79 PWD_CURR_80C Register (Offset = 3ACh) [reset = 2E3B9021h]
PWD_CURR_80C is shown in Figure 9-183 and described in Table 9-186.
Return to Summary Table.
Power Down Current Control 80C
Figure 9-101. PWD_CURR_80C Register
31

28
27
26
DELTA_CACHE_REF
R-2Eh

12
11
10
DELTA_XOSC_LPM
R-90h

20
19
18
DELTA_RFMEM_RET
R-3Bh
4
3
BASELINE
R-21h

Table 9-103. PWD_CURR_80C Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

DELTA_CACHE_REF

2Eh

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

3Bh

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

90h

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

21h

Worst-case baseline maximum powerdown current, in units of 0.5uA

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

821

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.80 PWD_CURR_95C Register (Offset = 3B0h) [reset = 4C627A3Bh]
PWD_CURR_95C is shown in Figure 9-184 and described in Table 9-187.
Return to Summary Table.
Power Down Current Control 95C
Figure 9-102. PWD_CURR_95C Register
31

28
27
26
DELTA_CACHE_REF
R-4Ch

12
11
10
DELTA_XOSC_LPM
R-7Ah

20
19
18
DELTA_RFMEM_RET
R-62h
4
3
BASELINE
R-3Bh

Table 9-104. PWD_CURR_95C Register Field Descriptions
Bit

822

Field

Type

Reset

Description

31-24

DELTA_CACHE_REF

4Ch

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

62h

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

7Ah

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

3Bh

Worst-case baseline maximum powerdown current, in units of 0.5uA

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.81 PWD_CURR_110C Register (Offset = 3B4h) [reset = 789E706Bh]
PWD_CURR_110C is shown in Figure 9-185 and described in Table 9-188.
Return to Summary Table.
Power Down Current Control 110C
Figure 9-103. PWD_CURR_110C Register
31

28
27
26
DELTA_CACHE_REF
R-78h

12
11
10
DELTA_XOSC_LPM
R-70h

20
19
18
DELTA_RFMEM_RET
R-9Eh
4
3
BASELINE
R-6Bh

Table 9-105. PWD_CURR_110C Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

DELTA_CACHE_REF

78h

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

9Eh

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

70h

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

6Bh

Worst-case baseline maximum powerdown current, in units of 0.5uA

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

823

Factory Configuration (FCFG)

www.ti.com

9.2.1.1.82 PWD_CURR_125C Register (Offset = 3B8h) [reset = ADE1809Ah]
PWD_CURR_125C is shown in Figure 9-186 and described in Table 9-189.
Return to Summary Table.
Power Down Current Control 125C
Figure 9-104. PWD_CURR_125C Register
31

28
27
26
DELTA_CACHE_REF
R-ADh

12
11
10
DELTA_XOSC_LPM
R-80h

20
19
18
DELTA_RFMEM_RET
R-E1h
4
3
BASELINE
R-9Ah

Table 9-106. PWD_CURR_125C Register Field Descriptions
Bit

824

Field

Type

Reset

Description

31-24

DELTA_CACHE_REF

ADh

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

E1h

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

80h

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

9Ah

Worst-case baseline maximum powerdown current, in units of 0.5uA

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2 CC26xx Factory Configuration (FCFG) Registers
9.2.2.1

FCFG1 Registers

Acronym

A0h

MISC_CONF_1

Misc configurations

Section 9.2.2.1.1

Section

A4h

MISC_CONF_2

Internal

Section 9.2.2.1.2

C4h

CONFIG_RF_FRONTEND_DIV5

Internal

Section 9.2.2.1.3

C8h

CONFIG_RF_FRONTEND_DIV6

Internal

Section 9.2.2.1.4

CCh

CONFIG_RF_FRONTEND_DIV10

Internal

Section 9.2.2.1.5

D0h

CONFIG_RF_FRONTEND_DIV12

Internal

Section 9.2.2.1.6

D4h

CONFIG_RF_FRONTEND_DIV15

Internal

Section 9.2.2.1.7

D8h

CONFIG_RF_FRONTEND_DIV30

Internal

Section 9.2.2.1.8

DCh

CONFIG_SYNTH_DIV5

Internal

Section 9.2.2.1.9

E0h

CONFIG_SYNTH_DIV6

Internal

Section 9.2.2.1.10

E4h

CONFIG_SYNTH_DIV10

Internal

Section 9.2.2.1.11

E8h

CONFIG_SYNTH_DIV12

Internal

Section 9.2.2.1.12

ECh

CONFIG_SYNTH_DIV15

Internal

Section 9.2.2.1.13

F0h

CONFIG_SYNTH_DIV30

Internal

Section 9.2.2.1.14

F4h

CONFIG_MISC_ADC_DIV5

Internal

Section 9.2.2.1.15

F8h

CONFIG_MISC_ADC_DIV6

Internal

Section 9.2.2.1.16

FCh

CONFIG_MISC_ADC_DIV10

Internal

Section 9.2.2.1.17

100h

CONFIG_MISC_ADC_DIV12

Internal

Section 9.2.2.1.18

104h

CONFIG_MISC_ADC_DIV15

Internal

Section 9.2.2.1.19

108h

CONFIG_MISC_ADC_DIV30

Internal

Section 9.2.2.1.20

118h

SHDW_DIE_ID_0

Shadow of [JTAG_TAP::EFUSE:DIE_ID_0.*]

Section 9.2.2.1.21

11Ch

SHDW_DIE_ID_1

Shadow of [JTAG_TAP::EFUSE:DIE_ID_1.*]

Section 9.2.2.1.22

120h

SHDW_DIE_ID_2

Shadow of [JTAG_TAP::EFUSE:DIE_ID_2.*]

Section 9.2.2.1.23

124h

SHDW_DIE_ID_3

Shadow of [JTAG_TAP::EFUSE:DIE_ID_3.*]

Section 9.2.2.1.24

138h

SHDW_OSC_BIAS_LDO_TRIM

Internal

Section 9.2.2.1.25

13Ch

SHDW_ANA_TRIM

Internal

Section 9.2.2.1.26

164h

FLASH_NUMBER

16Ch

FLASH_COORDINATE

Section 9.2.2.1.27

170h

FLASH_E_P

Internal

Section 9.2.2.1.29

174h

FLASH_C_E_P_R

Internal

Section 9.2.2.1.30

178h

FLASH_P_R_PV

Internal

Section 9.2.2.1.31

17Ch

FLASH_EH_SEQ

Internal

Section 9.2.2.1.32

180h

FLASH_VHV_E

Internal

Section 9.2.2.1.33

184h

FLASH_PP

Internal

Section 9.2.2.1.34

188h

FLASH_PROG_EP

Internal

Section 9.2.2.1.35

18Ch

FLASH_ERA_PW

Internal

Section 9.2.2.1.36

190h

FLASH_VHV

Internal

Section 9.2.2.1.37

194h

FLASH_VHV_PV

Internal

Section 9.2.2.1.38

198h

FLASH_V

Internal

Section 9.2.2.1.39

294h

USER_ID

User Identification.

Section 9.2.2.1.40

2B0h

FLASH_OTP_DATA3

Internal

Section 9.2.2.1.41

Section 9.2.2.1.28

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

825

Factory Configuration (FCFG)

www.ti.com

Table 9-107. FCFG1 Registers (continued)

826

Offset

Acronym

2B4h

ANA2_TRIM

Internal

Section 9.2.2.1.42

Section

2B8h

LDO_TRIM

Internal

Section 9.2.2.1.43

2BCh

BAT_RC_LDO_TRIM

Internal

Section 9.2.2.1.44

2E8h

MAC_BLE_0

MAC BLE Address 0

Section 9.2.2.1.45

2ECh

MAC_BLE_1

MAC BLE Address 1

Section 9.2.2.1.46

2F0h

MAC_15_4_0

MAC IEEE 802.15.4 Address 0

Section 9.2.2.1.47

2F4h

MAC_15_4_1

MAC IEEE 802.15.4 Address 1

Section 9.2.2.1.48

308h

FLASH_OTP_DATA4

Internal

Section 9.2.2.1.49

30Ch

MISC_TRIM

Miscellaneous Trim Parameters

Section 9.2.2.1.50

310h

RCOSC_HF_TEMPCOMP

Internal

Section 9.2.2.1.51

314h

TRIM_CAL_REVISION

Internal

Section 9.2.2.1.52

318h

ICEPICK_DEVICE_ID

IcePick Device Identification

Section 9.2.2.1.53

31Ch

FCFG1_REVISION

Factory Configuration (FCFG1) Revision

Section 9.2.2.1.54

320h

MISC_OTP_DATA

Misc OTP Data

Section 9.2.2.1.55

344h

IOCONF

IO Configuration

Section 9.2.2.1.56

34Ch

CONFIG_IF_ADC

Internal

Section 9.2.2.1.57

350h

CONFIG_OSC_TOP

Internal

Section 9.2.2.1.58

354h

CONFIG_RF_FRONTEND

Internal

Section 9.2.2.1.59

358h

CONFIG_SYNTH

Internal

Section 9.2.2.1.60

35Ch

SOC_ADC_ABS_GAIN

AUX_ADC Gain in Absolute Reference Mode

Section 9.2.2.1.61

360h

SOC_ADC_REL_GAIN

AUX_ADC Gain in Relative Reference Mode

Section 9.2.2.1.62

368h

SOC_ADC_OFFSET_INT

AUX_ADC Temperature Offsets in Absolute Reference
Mode

Section 9.2.2.1.63

36Ch

SOC_ADC_REF_TRIM_AND_OFFSET_E
XT

Internal

Section 9.2.2.1.64

370h

AMPCOMP_TH1

Internal

Section 9.2.2.1.65

374h

AMPCOMP_TH2

Internal

Section 9.2.2.1.66

378h

AMPCOMP_CTRL1

Internal

Section 9.2.2.1.67

37Ch

ANABYPASS_VALUE2

Internal

Section 9.2.2.1.68

380h

CONFIG_MISC_ADC

Internal

Section 9.2.2.1.69

388h

VOLT_TRIM

Internal

Section 9.2.2.1.70

38Ch

OSC_CONF

OSC Configuration

Section 9.2.2.1.71

390h

FREQ_OFFSET

Internal

Section 9.2.2.1.72

394h

CAP_TRIM

Internal

Section 9.2.2.1.73

398h

MISC_OTP_DATA_1

Internal

Section 9.2.2.1.74

39Ch

PWD_CURR_20C

Power Down Current Control 20C

Section 9.2.2.1.75

3A0h

PWD_CURR_35C

Power Down Current Control 35C

Section 9.2.2.1.76

3A4h

PWD_CURR_50C

Power Down Current Control 50C

Section 9.2.2.1.77

3A8h

PWD_CURR_65C

Power Down Current Control 65C

Section 9.2.2.1.78

3ACh

PWD_CURR_80C

Power Down Current Control 80C

Section 9.2.2.1.79

3B0h

PWD_CURR_95C

Power Down Current Control 95C

Section 9.2.2.1.80

3B4h

PWD_CURR_110C

Power Down Current Control 110C

Section 9.2.2.1.81

3B8h

PWD_CURR_125C

Power Down Current Control 125C

Section 9.2.2.1.82

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.1 MISC_CONF_1 Register (Offset = A0h) [reset = X]
MISC_CONF_1 is shown in Figure 9-105 and described in Table 9-108.
Return to Summary Table.
Misc configurations
Figure 9-105. MISC_CONF_1 Register
31

12
11
RESERVED
R-00FFFFFFh

24
23
RESERVED
R-00FFFFFFh
8

4
3
2
DEVICE_MINOR_REV
R-X

Table 9-108. MISC_CONF_1 Register Field Descriptions
Field

Type

Reset

31-8

Bit

RESERVED

00FFFFFFh Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

DEVICE_MINOR_REV

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Device Configuration

827

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.2 MISC_CONF_2 Register (Offset = A4h) [reset = X]
MISC_CONF_2 is shown in Figure 9-106 and described in Table 9-109.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-106. MISC_CONF_2 Register
31

12
11
RESERVED
R-00FFFFFFh

24
23
RESERVED
R-00FFFFFFh
8

4
3
HPOSC_COMP_P3
R-X

Table 9-109. MISC_CONF_2 Register Field Descriptions
Bit

828

Field

Type

Reset

31-8

RESERVED

00FFFFFFh Internal. Only to be used through TI provided API.

7-0

HPOSC_COMP_P3

Device Configuration

Description

Internal. Only to be used through TI provided API.
Default value holds log information from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.3 CONFIG_RF_FRONTEND_DIV5 Register (Offset = C4h) [reset = FFFFFFFFh]
CONFIG_RF_FRONTEND_DIV5 is shown in Figure 9-107 and described in Table 9-110.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-107. CONFIG_RF_FRONTEND_DIV5 Register
31

30
29
IFAMP_IB
R-Fh

15
14
CTL_PA0_TRI
M
R-1Fh

26
25
LNA_IB
R-Fh

10
9
RESERVED

21
20
IFAMP_TRIM
R-1Fh
5

R-7Fh

18
17
16
CTL_PA0_TRIM
R-1Fh

4
3
2
RFLDO_TRIM_OUTPUT

R-7Fh

Table 9-110. CONFIG_RF_FRONTEND_DIV5 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.

23-19

IFAMP_TRIM

1Fh

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

1Fh

Internal. Only to be used through TI provided API.

13-7

RESERVED

7Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

7Fh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

829

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.4 CONFIG_RF_FRONTEND_DIV6 Register (Offset = C8h) [reset = FFFFFFFFh]
CONFIG_RF_FRONTEND_DIV6 is shown in Figure 9-108 and described in Table 9-111.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-108. CONFIG_RF_FRONTEND_DIV6 Register
31

30
29
IFAMP_IB
R-Fh

15
14
CTL_PA0_TRI
M
R-1Fh

26
25
LNA_IB
R-Fh

10
9
RESERVED

21
20
IFAMP_TRIM
R-1Fh
5

R-7Fh

18
17
16
CTL_PA0_TRIM
R-1Fh

4
3
2
RFLDO_TRIM_OUTPUT

R-7Fh

Table 9-111. CONFIG_RF_FRONTEND_DIV6 Register Field Descriptions
Bit

830

Field

Type

Reset

Description

31-28

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.

23-19

IFAMP_TRIM

1Fh

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

1Fh

Internal. Only to be used through TI provided API.

13-7

RESERVED

7Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

7Fh

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.5 CONFIG_RF_FRONTEND_DIV10 Register (Offset = CCh) [reset = FFFFFFFFh]
CONFIG_RF_FRONTEND_DIV10 is shown in Figure 9-109 and described in Table 9-112.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-109. CONFIG_RF_FRONTEND_DIV10 Register
31

30
29
IFAMP_IB
R-Fh

15
14
CTL_PA0_TRI
M
R-1Fh

26
25
LNA_IB
R-Fh

10
9
RESERVED

21
20
IFAMP_TRIM
R-1Fh
5

R-7Fh

18
17
16
CTL_PA0_TRIM
R-1Fh

4
3
2
RFLDO_TRIM_OUTPUT

R-7Fh

Table 9-112. CONFIG_RF_FRONTEND_DIV10 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.

23-19

IFAMP_TRIM

1Fh

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

1Fh

Internal. Only to be used through TI provided API.

13-7

RESERVED

7Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

7Fh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

831

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.6 CONFIG_RF_FRONTEND_DIV12 Register (Offset = D0h) [reset = FFFFFFFFh]
CONFIG_RF_FRONTEND_DIV12 is shown in Figure 9-110 and described in Table 9-113.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-110. CONFIG_RF_FRONTEND_DIV12 Register
31

30
29
IFAMP_IB
R-Fh

15
14
CTL_PA0_TRI
M
R-1Fh

26
25
LNA_IB
R-Fh

10
9
RESERVED

21
20
IFAMP_TRIM
R-1Fh
5

R-7Fh

18
17
16
CTL_PA0_TRIM
R-1Fh

4
3
2
RFLDO_TRIM_OUTPUT

R-7Fh

Table 9-113. CONFIG_RF_FRONTEND_DIV12 Register Field Descriptions
Bit

832

Field

Type

Reset

Description

31-28

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.

23-19

IFAMP_TRIM

1Fh

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

1Fh

Internal. Only to be used through TI provided API.

13-7

RESERVED

7Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

7Fh

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.7 CONFIG_RF_FRONTEND_DIV15 Register (Offset = D4h) [reset = FFFFFFFFh]
CONFIG_RF_FRONTEND_DIV15 is shown in Figure 9-111 and described in Table 9-114.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-111. CONFIG_RF_FRONTEND_DIV15 Register
31

30
29
IFAMP_IB
R-Fh

15
14
CTL_PA0_TRI
M
R-1Fh

26
25
LNA_IB
R-Fh

10
9
RESERVED

21
20
IFAMP_TRIM
R-1Fh
5

R-7Fh

18
17
16
CTL_PA0_TRIM
R-1Fh

4
3
2
RFLDO_TRIM_OUTPUT

R-7Fh

Table 9-114. CONFIG_RF_FRONTEND_DIV15 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.

23-19

IFAMP_TRIM

1Fh

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

1Fh

Internal. Only to be used through TI provided API.

13-7

RESERVED

7Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

7Fh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

833

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.8 CONFIG_RF_FRONTEND_DIV30 Register (Offset = D8h) [reset = FFFFFFFFh]
CONFIG_RF_FRONTEND_DIV30 is shown in Figure 9-112 and described in Table 9-115.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-112. CONFIG_RF_FRONTEND_DIV30 Register
31

30
29
IFAMP_IB
R-Fh

15
14
CTL_PA0_TRI
M
R-1Fh

26
25
LNA_IB
R-Fh

10
9
RESERVED

21
20
IFAMP_TRIM
R-1Fh
5

R-7Fh

18
17
16
CTL_PA0_TRIM
R-1Fh

4
3
2
RFLDO_TRIM_OUTPUT

R-7Fh

Table 9-115. CONFIG_RF_FRONTEND_DIV30 Register Field Descriptions
Bit

834

Field

Type

Reset

Description

31-28

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.

23-19

IFAMP_TRIM

1Fh

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

1Fh

Internal. Only to be used through TI provided API.

13-7

RESERVED

7Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

7Fh

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.9 CONFIG_SYNTH_DIV5 Register (Offset = DCh) [reset = FFFFFFFFh]
CONFIG_SYNTH_DIV5 is shown in Figure 9-113 and described in Table 9-116.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-113. CONFIG_SYNTH_DIV5 Register
31

30
29
RESERVED
R-Fh

23
22
21
20
RFC_MDM_DEMIQMC0
R-FFFFh

15
14
13
12
RFC_MDM_DEMIQMC0
R-FFFFh

10
9
8
7
LDOVCO_TRIM_OUTPUT
R-3Fh

3
2
1
SLDO_TRIM_OUTPUT
R-3Fh

Table 9-116. CONFIG_SYNTH_DIV5 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

RESERVED

Internal. Only to be used through TI provided API.

27-12

RFC_MDM_DEMIQMC0

FFFFh

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization.

11-6

LDOVCO_TRIM_OUTPU
T

3Fh

Internal. Only to be used through TI provided API.

5-0

SLDO_TRIM_OUTPUT

3Fh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

835

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.10 CONFIG_SYNTH_DIV6 Register (Offset = E0h) [reset = FFFFFFFFh]
CONFIG_SYNTH_DIV6 is shown in Figure 9-114 and described in Table 9-117.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-114. CONFIG_SYNTH_DIV6 Register
31

30
29
RESERVED
R-Fh

23
22
21
20
RFC_MDM_DEMIQMC0
R-FFFFh

15
14
13
12
RFC_MDM_DEMIQMC0
R-FFFFh

10
9
8
7
LDOVCO_TRIM_OUTPUT
R-3Fh

3
2
1
SLDO_TRIM_OUTPUT
R-3Fh

Table 9-117. CONFIG_SYNTH_DIV6 Register Field Descriptions
Bit

836

Field

Type

Reset

Description

31-28

RESERVED

Internal. Only to be used through TI provided API.

27-12

RFC_MDM_DEMIQMC0

FFFFh

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization.

11-6

LDOVCO_TRIM_OUTPU
T

3Fh

Internal. Only to be used through TI provided API.

5-0

SLDO_TRIM_OUTPUT

3Fh

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.11 CONFIG_SYNTH_DIV10 Register (Offset = E4h) [reset = FFFFFFFFh]
CONFIG_SYNTH_DIV10 is shown in Figure 9-115 and described in Table 9-118.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-115. CONFIG_SYNTH_DIV10 Register
31

30
29
RESERVED
R-Fh

23
22
21
20
RFC_MDM_DEMIQMC0
R-FFFFh

15
14
13
12
RFC_MDM_DEMIQMC0
R-FFFFh

10
9
8
7
LDOVCO_TRIM_OUTPUT
R-3Fh

3
2
1
SLDO_TRIM_OUTPUT
R-3Fh

Table 9-118. CONFIG_SYNTH_DIV10 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

RESERVED

Internal. Only to be used through TI provided API.

27-12

RFC_MDM_DEMIQMC0

FFFFh

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization.

11-6

LDOVCO_TRIM_OUTPU
T

3Fh

Internal. Only to be used through TI provided API.

5-0

SLDO_TRIM_OUTPUT

3Fh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

837

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.12 CONFIG_SYNTH_DIV12 Register (Offset = E8h) [reset = FFFFFFFFh]
CONFIG_SYNTH_DIV12 is shown in Figure 9-116 and described in Table 9-119.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-116. CONFIG_SYNTH_DIV12 Register
31

30
29
RESERVED
R-Fh

23
22
21
20
RFC_MDM_DEMIQMC0
R-FFFFh

15
14
13
12
RFC_MDM_DEMIQMC0
R-FFFFh

10
9
8
7
LDOVCO_TRIM_OUTPUT
R-3Fh

3
2
1
SLDO_TRIM_OUTPUT
R-3Fh

Table 9-119. CONFIG_SYNTH_DIV12 Register Field Descriptions
Bit

838

Field

Type

Reset

Description

31-28

RESERVED

Internal. Only to be used through TI provided API.

27-12

RFC_MDM_DEMIQMC0

FFFFh

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization.

11-6

LDOVCO_TRIM_OUTPU
T

3Fh

Internal. Only to be used through TI provided API.

5-0

SLDO_TRIM_OUTPUT

3Fh

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.13 CONFIG_SYNTH_DIV15 Register (Offset = ECh) [reset = FFFFFFFFh]
CONFIG_SYNTH_DIV15 is shown in Figure 9-117 and described in Table 9-120.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-117. CONFIG_SYNTH_DIV15 Register
31

30
29
RESERVED
R-Fh

23
22
21
20
RFC_MDM_DEMIQMC0
R-FFFFh

15
14
13
12
RFC_MDM_DEMIQMC0
R-FFFFh

10
9
8
7
LDOVCO_TRIM_OUTPUT
R-3Fh

3
2
1
SLDO_TRIM_OUTPUT
R-3Fh

Table 9-120. CONFIG_SYNTH_DIV15 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

RESERVED

Internal. Only to be used through TI provided API.

27-12

RFC_MDM_DEMIQMC0

FFFFh

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization.

11-6

LDOVCO_TRIM_OUTPU
T

3Fh

Internal. Only to be used through TI provided API.

5-0

SLDO_TRIM_OUTPUT

3Fh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

839

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.14 CONFIG_SYNTH_DIV30 Register (Offset = F0h) [reset = FFFFFFFFh]
CONFIG_SYNTH_DIV30 is shown in Figure 9-118 and described in Table 9-121.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-118. CONFIG_SYNTH_DIV30 Register
31

30
29
RESERVED
R-Fh

23
22
21
20
RFC_MDM_DEMIQMC0
R-FFFFh

15
14
13
12
RFC_MDM_DEMIQMC0
R-FFFFh

10
9
8
7
LDOVCO_TRIM_OUTPUT
R-3Fh

3
2
1
SLDO_TRIM_OUTPUT
R-3Fh

Table 9-121. CONFIG_SYNTH_DIV30 Register Field Descriptions
Bit

840

Field

Type

Reset

Description

31-28

RESERVED

Internal. Only to be used through TI provided API.

27-12

RFC_MDM_DEMIQMC0

FFFFh

Trim value for RF Core.
Value is read by RF Core ROM FW during RF Core initialization.

11-6

LDOVCO_TRIM_OUTPU
T

3Fh

Internal. Only to be used through TI provided API.

5-0

SLDO_TRIM_OUTPUT

3Fh

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.15 CONFIG_MISC_ADC_DIV5 Register (Offset = F4h) [reset = FFFFFFFFh]
CONFIG_MISC_ADC_DIV5 is shown in Figure 9-119 and described in Table 9-122.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-119. CONFIG_MISC_ADC_DIV5 Register
31

RESERVED
R-7FFFh
23

20
RESERVED
R-7FFFh

16
RSSI_OFFSET
R-FFh

12
RSSI_OFFSET

8
QUANTCTLTH
RES
R-7h

7
6
QUANTCTLTHRES
R-7h

R-FFh
4

3
DACTRIM
R-3Fh

Table 9-122. CONFIG_MISC_ADC_DIV5 Register Field Descriptions
Field

Type

Reset

Description

31-17

Bit

RESERVED

7FFFh

Internal. Only to be used through TI provided API.

16-9

RSSI_OFFSET

FFh

Internal. Only to be used through TI provided API.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

3Fh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

841

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.16 CONFIG_MISC_ADC_DIV6 Register (Offset = F8h) [reset = FFFFFFFFh]
CONFIG_MISC_ADC_DIV6 is shown in Figure 9-120 and described in Table 9-123.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-120. CONFIG_MISC_ADC_DIV6 Register
31

RESERVED
R-7FFFh
23

20
RESERVED
R-7FFFh

16
RSSI_OFFSET
R-FFh

12
RSSI_OFFSET

8
QUANTCTLTH
RES
R-7h

7
6
QUANTCTLTHRES
R-7h

R-FFh
4

3
DACTRIM
R-3Fh

Table 9-123. CONFIG_MISC_ADC_DIV6 Register Field Descriptions
Bit

842

Field

Type

Reset

Description

31-17

RESERVED

7FFFh

Internal. Only to be used through TI provided API.

16-9

RSSI_OFFSET

FFh

Internal. Only to be used through TI provided API.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

3Fh

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.17 CONFIG_MISC_ADC_DIV10 Register (Offset = FCh) [reset = FFFFFFFFh]
CONFIG_MISC_ADC_DIV10 is shown in Figure 9-121 and described in Table 9-124.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-121. CONFIG_MISC_ADC_DIV10 Register
31

RESERVED
R-7FFFh
23

20
RESERVED
R-7FFFh

16
RSSI_OFFSET
R-FFh

12
RSSI_OFFSET

8
QUANTCTLTH
RES
R-7h

7
6
QUANTCTLTHRES
R-7h

R-FFh
4

3
DACTRIM
R-3Fh

Table 9-124. CONFIG_MISC_ADC_DIV10 Register Field Descriptions
Field

Type

Reset

Description

31-17

Bit

RESERVED

7FFFh

Internal. Only to be used through TI provided API.

16-9

RSSI_OFFSET

FFh

Internal. Only to be used through TI provided API.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

3Fh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

843

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.18 CONFIG_MISC_ADC_DIV12 Register (Offset = 100h) [reset = FFFFFFFFh]
CONFIG_MISC_ADC_DIV12 is shown in Figure 9-122 and described in Table 9-125.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-122. CONFIG_MISC_ADC_DIV12 Register
31

RESERVED
R-7FFFh
23

20
RESERVED
R-7FFFh

16
RSSI_OFFSET
R-FFh

12
RSSI_OFFSET

8
QUANTCTLTH
RES
R-7h

7
6
QUANTCTLTHRES
R-7h

R-FFh
4

3
DACTRIM
R-3Fh

Table 9-125. CONFIG_MISC_ADC_DIV12 Register Field Descriptions
Bit

844

Field

Type

Reset

Description

31-17

RESERVED

7FFFh

Internal. Only to be used through TI provided API.

16-9

RSSI_OFFSET

FFh

Internal. Only to be used through TI provided API.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

3Fh

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.19 CONFIG_MISC_ADC_DIV15 Register (Offset = 104h) [reset = FFFFFFFFh]
CONFIG_MISC_ADC_DIV15 is shown in Figure 9-123 and described in Table 9-126.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-123. CONFIG_MISC_ADC_DIV15 Register
31

RESERVED
R-7FFFh
23

20
RESERVED
R-7FFFh

16
RSSI_OFFSET
R-FFh

12
RSSI_OFFSET

8
QUANTCTLTH
RES
R-7h

7
6
QUANTCTLTHRES
R-7h

R-FFh
4

3
DACTRIM
R-3Fh

Table 9-126. CONFIG_MISC_ADC_DIV15 Register Field Descriptions
Field

Type

Reset

Description

31-17

Bit

RESERVED

7FFFh

Internal. Only to be used through TI provided API.

16-9

RSSI_OFFSET

FFh

Internal. Only to be used through TI provided API.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

3Fh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

845

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.20 CONFIG_MISC_ADC_DIV30 Register (Offset = 108h) [reset = FFFFFFFFh]
CONFIG_MISC_ADC_DIV30 is shown in Figure 9-124 and described in Table 9-127.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-124. CONFIG_MISC_ADC_DIV30 Register
31

RESERVED
R-7FFFh
23

20
RESERVED
R-7FFFh

16
RSSI_OFFSET
R-FFh

12
RSSI_OFFSET

8
QUANTCTLTH
RES
R-7h

7
6
QUANTCTLTHRES
R-7h

R-FFh
4

3
DACTRIM
R-3Fh

Table 9-127. CONFIG_MISC_ADC_DIV30 Register Field Descriptions
Bit

846

Field

Type

Reset

Description

31-17

RESERVED

7FFFh

Internal. Only to be used through TI provided API.

16-9

RSSI_OFFSET

FFh

Internal. Only to be used through TI provided API.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

3Fh

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.21 SHDW_DIE_ID_0 Register (Offset = 118h) [reset = X]
SHDW_DIE_ID_0 is shown in Figure 9-125 and described in Table 9-128.
Return to Summary Table.
Shadow of DIE_ID_0 register in eFuse
Figure 9-125. SHDW_DIE_ID_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ID_31_0
R-X

Table 9-128. SHDW_DIE_ID_0 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ID_31_0

Shadow of DIE_ID_0 register in eFuse row number 3
Default value depends on eFuse value.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

847

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.22 SHDW_DIE_ID_1 Register (Offset = 11Ch) [reset = X]
SHDW_DIE_ID_1 is shown in Figure 9-126 and described in Table 9-129.
Return to Summary Table.
Shadow of DIE_ID_1 register in eFuse
Figure 9-126. SHDW_DIE_ID_1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ID_63_32
R-X

Table 9-129. SHDW_DIE_ID_1 Register Field Descriptions
Bit
31-0

848

Field

Type

Reset

Description

ID_63_32

Shadow of DIE_ID_1 register in eFuse row number 4
Default value depends on eFuse value.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.23 SHDW_DIE_ID_2 Register (Offset = 120h) [reset = X]
SHDW_DIE_ID_2 is shown in Figure 9-127 and described in Table 9-130.
Return to Summary Table.
Shadow of DIE_ID_2 register in eFuse
Figure 9-127. SHDW_DIE_ID_2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ID_95_64
R-X

Table 9-130. SHDW_DIE_ID_2 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ID_95_64

Shadow of DIE_ID_2 register in eFuse row number 5
Default value depends on eFuse value.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

849

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.24 SHDW_DIE_ID_3 Register (Offset = 124h) [reset = X]
SHDW_DIE_ID_3 is shown in Figure 9-128 and described in Table 9-131.
Return to Summary Table.
Shadow of DIE_ID_3 register in eFuse
Figure 9-128. SHDW_DIE_ID_3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ID_127_96
R-X

Table 9-131. SHDW_DIE_ID_3 Register Field Descriptions
Bit
31-0

850

Field

Type

Reset

Description

ID_127_96

Shadow of DIE_ID_3 register in eFuse row number 6
Default value depends on eFuse value.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.25 SHDW_OSC_BIAS_LDO_TRIM Register (Offset = 138h) [reset = X]
SHDW_OSC_BIAS_LDO_TRIM is shown in Figure 9-129 and described in Table 9-132.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-129. SHDW_OSC_BIAS_LDO_TRIM Register
31

30
RESERVED

28
27
SET_RCOSC_HF_COARSE_RE
SISTOR
R-X

R-X
23
TRIMMAG
R-X

25
TRIMMAG

R-X

20
TRIMIREF
R-X

10
9
VTRIM_COARSE
R-X

4
3
RCOSCHF_CTRIM
R-X

VTRIM_DIG
R-X
7

17
16
ITRIM_DIG_LDO
R-X

Table 9-132. SHDW_OSC_BIAS_LDO_TRIM Register Field Descriptions
Field

Type

Reset

Description

31-29

Bit

RESERVED

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

28-27

SET_RCOSC_HF_COAR
SE_RESISTOR

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

26-23

TRIMMAG

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

22-18

TRIMIREF

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

17-16

ITRIM_DIG_LDO

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

15-12

VTRIM_DIG

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

11-8

VTRIM_COARSE

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

7-0

RCOSCHF_CTRIM

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

851

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.26 SHDW_ANA_TRIM Register (Offset = 13Ch) [reset = X]
SHDW_ANA_TRIM is shown in Figure 9-130 and described in Table 9-133.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-130. SHDW_ANA_TRIM Register
31

29
RESERVED

26
25
BOD_BANDGAP_TRIM_CNF

R-X
23
VDDR_OK_HY
S
R-X

R-X

IPTAT_TRIM

18
VDDR_TRIM

R-X

13
TRIMBOD_INTMODE
R-X

7
6
TRIMBOD_EXTMODE
R-X

24
VDDR_ENABL
E_PG1
R-X

9
TRIMBOD_EXTMODE
R-X

TRIMTEMP
R-X

Table 9-133. SHDW_ANA_TRIM Register Field Descriptions
Bit

852

Field

Type

Reset

Description

31-27

RESERVED

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

26-25

BOD_BANDGAP_TRIM_
CNF

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

VDDR_ENABLE_PG1

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

VDDR_OK_HYS

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

22-21

IPTAT_TRIM

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

20-16

VDDR_TRIM

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

15-11

TRIMBOD_INTMODE

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

10-6

TRIMBOD_EXTMODE

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

5-0

TRIMTEMP

Internal. Only to be used through TI provided API.
Default value depends on eFuse value.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.27 FLASH_NUMBER Register (Offset = 164h) [reset = X]
FLASH_NUMBER is shown in Figure 9-131 and described in Table 9-134.
Return to Summary Table.
Figure 9-131. FLASH_NUMBER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LOT_NUMBER
R-X

Table 9-134. FLASH_NUMBER Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

LOT_NUMBER

Number of the manufacturing lot that produced this unit.
Default value holds log information from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

853

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.28 FLASH_COORDINATE Register (Offset = 16Ch) [reset = X]
FLASH_COORDINATE is shown in Figure 9-132 and described in Table 9-135.
Return to Summary Table.
Figure 9-132. FLASH_COORDINATE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
XCOORDINATE
YCOORDINATE
R-X
R-X

Table 9-135. FLASH_COORDINATE Register Field Descriptions
Bit

854

Field

Type

Reset

Description

31-16

XCOORDINATE

X coordinate of this unit on the wafer.
Default value holds log information from production test.

15-0

YCOORDINATE

Y coordinate of this unit on the wafer.
Default value holds log information from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.29 FLASH_E_P Register (Offset = 170h) [reset = 17331A33h]
FLASH_E_P is shown in Figure 9-133 and described in Table 9-136.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-133. FLASH_E_P Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PSU
ESU
PVSU
R-17h
R-33h
R-1Ah

4 3
EVSU
R-33h

Table 9-136. FLASH_E_P Register Field Descriptions
Bit

Field

Type

Reset

Description

31-24

PSU

17h

Internal. Only to be used through TI provided API.

23-16

ESU

33h

Internal. Only to be used through TI provided API.

15-8

PVSU

1Ah

Internal. Only to be used through TI provided API.

7-0

EVSU

33h

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

855

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.30 FLASH_C_E_P_R Register (Offset = 174h) [reset = 0A0A2000h]
FLASH_C_E_P_R is shown in Figure 9-134 and described in Table 9-137.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-134. FLASH_C_E_P_R Register
31

RVSU
R-Ah
15

14
13
A_EXEZ_SETUP
R-2h

20
19
PV_ACCESS
R-Ah
4

CVSU
R-0h

Table 9-137. FLASH_C_E_P_R Register Field Descriptions

856

Bit

Field

Type

Reset

Description

31-24

RVSU

Internal. Only to be used through TI provided API.

23-16

PV_ACCESS

Internal. Only to be used through TI provided API.

15-12

A_EXEZ_SETUP

Internal. Only to be used through TI provided API.

11-0

CVSU

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.31 FLASH_P_R_PV Register (Offset = 178h) [reset = 026E0200h]
FLASH_P_R_PV is shown in Figure 9-135 and described in Table 9-138.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-135. FLASH_P_R_PV Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PH
RH
PVH
R-2h
R-6Eh
R-2h

4 3
PVH2
R-0h

Table 9-138. FLASH_P_R_PV Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

Internal. Only to be used through TI provided API.

23-16

6Eh

Internal. Only to be used through TI provided API.

15-8

PVH

Internal. Only to be used through TI provided API.

7-0

PVH2

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

857

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.32 FLASH_EH_SEQ Register (Offset = 17Ch) [reset = 0200F000h]
FLASH_EH_SEQ is shown in Figure 9-136 and described in Table 9-139.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-136. FLASH_EH_SEQ Register
31

EH
R-2h
15

14
13
VSTAT
R-Fh

SEQ
R-0h
11

6
5
SM_FREQUENCY
R-0h

Table 9-139. FLASH_EH_SEQ Register Field Descriptions
Bit

858

Field

Type

Reset

Description

31-24

Internal. Only to be used through TI provided API.

23-16

SEQ

Internal. Only to be used through TI provided API.

15-12

VSTAT

Internal. Only to be used through TI provided API.

11-0

SM_FREQUENCY

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.33 FLASH_VHV_E Register (Offset = 180h) [reset = 1h]
FLASH_VHV_E is shown in Figure 9-137 and described in Table 9-140.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-137. FLASH_VHV_E Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
VHV_E_START
VHV_E_STEP_HIGHT
R-0h
R-1h

Table 9-140. FLASH_VHV_E Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

VHV_E_START

Internal. Only to be used through TI provided API.

15-0

VHV_E_STEP_HIGHT

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

859

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.34 FLASH_PP Register (Offset = 184h) [reset = X]
FLASH_PP is shown in Figure 9-138 and described in Table 9-141.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-138. FLASH_PP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PUMP_SU
RESERVED
R-0h
R-X

8 7 6
MAX_PP
R-14h

Table 9-141. FLASH_PP Register Field Descriptions
Bit

860

Field

Type

Reset

Description

31-24

PUMP_SU

Internal. Only to be used through TI provided API.

23-16

RESERVED

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-0

MAX_PP

14h

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.35 FLASH_PROG_EP Register (Offset = 188h) [reset = 0FA00010h]
FLASH_PROG_EP is shown in Figure 9-139 and described in Table 9-142.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-139. FLASH_PROG_EP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
MAX_EP
PROGRAM_PW
R-FA0h
R-10h

Table 9-142. FLASH_PROG_EP Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

MAX_EP

FA0h

Internal. Only to be used through TI provided API.

15-0

PROGRAM_PW

10h

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

861

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.36 FLASH_ERA_PW Register (Offset = 18Ch) [reset = FA0h]
FLASH_ERA_PW is shown in Figure 9-140 and described in Table 9-143.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-140. FLASH_ERA_PW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ERASE_PW
R-FA0h

Table 9-143. FLASH_ERA_PW Register Field Descriptions
Bit
31-0

862

Field

Type

Reset

Description

ERASE_PW

FA0h

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.37 FLASH_VHV Register (Offset = 190h) [reset = X]
FLASH_VHV is shown in Figure 9-141 and described in Table 9-144.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-141. FLASH_VHV Register
31

30
29
RESERVED
R-0h

26
25
TRIM13_P
R-X

22
21
RESERVED
R-0h

18
17
VHV_P
R-X

14
13
RESERVED
R-0h

10
9
TRIM13_E
R-X

6
5
RESERVED
R-0h

1
VHV_E
R-4h

Table 9-144. FLASH_VHV Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

RESERVED

Internal. Only to be used through TI provided API.

27-24

TRIM13_P

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-20

RESERVED

Internal. Only to be used through TI provided API.

19-16

VHV_P

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-12

RESERVED

Internal. Only to be used through TI provided API.

11-8

TRIM13_E

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

7-4

RESERVED

Internal. Only to be used through TI provided API.

3-0

VHV_E

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

863

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.38 FLASH_VHV_PV Register (Offset = 194h) [reset = X]
FLASH_VHV_PV is shown in Figure 9-142 and described in Table 9-145.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-142. FLASH_VHV_PV Register
31

30
29
RESERVED
R-0h

12
11
VCG2P5
R-X

26
25
TRIM13_PV
R-X

22
21
RESERVED
R-0h
6

18
17
VHV_PV
R-8h

VINH
R-1h

Table 9-145. FLASH_VHV_PV Register Field Descriptions
Bit

864

Field

Type

Reset

Description

31-28

RESERVED

Internal. Only to be used through TI provided API.

27-24

TRIM13_PV

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-20

RESERVED

Internal. Only to be used through TI provided API.

19-16

VHV_PV

Internal. Only to be used through TI provided API.

15-8

VCG2P5

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

7-0

VINH

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.39 FLASH_V Register (Offset = 198h) [reset = X]
FLASH_V is shown in Figure 9-143 and described in Table 9-146.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-143. FLASH_V Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VSL_P
VWL_P
V_READ
R-X
R-X
R-X

5 4 3 2
RESERVED
R-X

Table 9-146. FLASH_V Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

VSL_P

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-16

VWL_P

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-8

V_READ

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

7-0

RESERVED

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

865

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.40 USER_ID Register (Offset = 294h) [reset = X]
USER_ID is shown in Figure 9-144 and described in Table 9-147.
Return to Summary Table.
User Identification.
Reading this register or the ICEPICK_DEVICE_ID register is the only support way of identifying a device.
The value of this register will be written to AON_WUC:JTAGUSERCODE by boot FW while in safezone.
Figure 9-144. USER_ID Register
31

30
29
PG_REV
R-X

14
13
PROTOCOL
R-X

VER
R-X
11

24
23
RESERVED
R-X
8

21
20
SEQUENCE
R-X

6
5
RESERVED
R-X

17
PKG
R-X

Table 9-147. USER_ID Register Field Descriptions
Bit

866

Field

Type

Reset

Description

31-28

PG_REV

Field used to distinguish revisions of the device.
Default value holds log information from production test.

27-26

VER

Version number.
0x0: Bits [25:12] of this register has the stated meaning.
Any other setting indicate a different encoding of these bits.
Default value differs depending on partnumber.

25-23

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Default value differs depending on partnumber.

22-19

SEQUENCE

18-16

PKG

15-12

PROTOCOL

11-0

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Default value differs depending on partnumber.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.41 FLASH_OTP_DATA3 Register (Offset = 2B0h) [reset = X]
FLASH_OTP_DATA3 is shown in Figure 9-145 and described in Table 9-148.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-145. FLASH_OTP_DATA3 Register
31

28
27
EC_STEP_SIZE
R-0h

23
EC_STEP_SIZ
E
R-0h

22
DO_PRECOND

20
19
MAX_EC_LEVEL

R-0h
12

16
TRIM_1P7

R-4h
13

R-1h
11

4
3
WAIT_SYSCODE
R-3h

FLASH_SIZE
R-X
7

Table 9-148. FLASH_OTP_DATA3 Register Field Descriptions
Field

Type

Reset

Description

31-23

Bit

EC_STEP_SIZE

Internal. Only to be used through TI provided API.

DO_PRECOND

Internal. Only to be used through TI provided API.

21-18

MAX_EC_LEVEL

Internal. Only to be used through TI provided API.

17-16

TRIM_1P7

Internal. Only to be used through TI provided API.

15-8

FLASH_SIZE

Internal. Only to be used through TI provided API.
Default value differs depending on partnumber.

7-0

WAIT_SYSCODE

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

867

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.42 ANA2_TRIM Register (Offset = 2B4h) [reset = X]
ANA2_TRIM is shown in Figure 9-146 and described in Table 9-149.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-146. ANA2_TRIM Register
31
RCOSCHFCTR
IMFRACT_EN

28
RCOSCHFCTRIMFRACT

R-1h

25
RESERVED

R-1h

24
SET_RCOSC_
HF_FINE_RESI
STOR
R-0h

9
DCDC_IPEAK
R-4h

1
DCDC_HIGH_EN_SEL
R-7h

R-X

23
22
SET_RCOSC_ ATESTLF_UDI
HF_FINE_RESI GLDO_IBIAS_T
STOR
RIM
R-0h
R-1h
15

19
18
NANOAMP_RES_TRIM

4
DCDC_LOW_EN_SEL
R-7h

R-X

14
RESERVED
R-Fh

7
6
DEAD_TIME_TRIM
R-1h

11
DITHER_EN
R-0h
3

Table 9-149. ANA2_TRIM Register Field Descriptions
Bit

Field

Type

Reset

Description

RCOSCHFCTRIMFRACT
_EN

Internal. Only to be used through TI provided API.

30-26

RCOSCHFCTRIMFRACT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

RESERVED

Internal. Only to be used through TI provided API.

24-23

SET_RCOSC_HF_FINE_
RESISTOR

Internal. Only to be used through TI provided API.

ATESTLF_UDIGLDO_IBI
AS_TRIM

Internal. Only to be used through TI provided API.

21-16

NANOAMP_RES_TRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-12

RESERVED

Internal. Only to be used through TI provided API.

DITHER_EN

Internal. Only to be used through TI provided API.

10-8

DCDC_IPEAK

Internal. Only to be used through TI provided API.

7-6

DEAD_TIME_TRIM

Internal. Only to be used through TI provided API.

5-3

DCDC_LOW_EN_SEL

Internal. Only to be used through TI provided API.

2-0

DCDC_HIGH_EN_SEL

Internal. Only to be used through TI provided API.

868

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.43 LDO_TRIM Register (Offset = 2B8h) [reset = X]
LDO_TRIM is shown in Figure 9-147 and described in Table 9-150.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-147. LDO_TRIM Register
31

30
RESERVED
R-7h

26
VDDR_TRIM_SLEEP
R-X

21
RESERVED
R-1Fh

14
RESERVED
R-7h

5
RESERVED
R-1Fh

12
11
ITRIM_DIGLDO_LOAD
R-0h
4

17
GLDO_CURSRC
R-0h

9
ITRIM_UDIGLDO
R-0h

1
VTRIM_DELTA
R-3h

Table 9-150. LDO_TRIM Register Field Descriptions
Bit

Field

Type

Reset

Description

31-29

RESERVED

Internal. Only to be used through TI provided API.

28-24

VDDR_TRIM_SLEEP

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-19

RESERVED

1Fh

Internal. Only to be used through TI provided API.

18-16

GLDO_CURSRC

Internal. Only to be used through TI provided API.

15-13

RESERVED

Internal. Only to be used through TI provided API.

12-11

ITRIM_DIGLDO_LOAD

Internal. Only to be used through TI provided API.

10-8

ITRIM_UDIGLDO

Internal. Only to be used through TI provided API.

7-3

RESERVED

1Fh

Internal. Only to be used through TI provided API.

2-0

VTRIM_DELTA

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

869

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.44 BAT_RC_LDO_TRIM Register (Offset = 2BCh) [reset = X]
BAT_RC_LDO_TRIM is shown in Figure 9-148 and described in Table 9-151.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-148. BAT_RC_LDO_TRIM Register
31

RESERVED
R-Fh
23

RESERVED
R-Fh
15

VTRIM_UDIG
R-X
12

RESERVED
R-Fh
7

25
VTRIM_BOD
R-X

10
9
RCOSCHF_ITUNE_TRIM
R-0h
2

RESERVED
R-3Fh

0
MEASUREPER
R-0h

Table 9-151. BAT_RC_LDO_TRIM Register Field Descriptions
Bit

870

Field

Type

Reset

Description

31-28

RESERVED

Internal. Only to be used through TI provided API.

27-24

VTRIM_BOD

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-20

RESERVED

Internal. Only to be used through TI provided API.

19-16

VTRIM_UDIG

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-12

RESERVED

Internal. Only to be used through TI provided API.

11-8

RCOSCHF_ITUNE_TRIM

Internal. Only to be used through TI provided API.

7-2

RESERVED

3Fh

Internal. Only to be used through TI provided API.

1-0

MEASUREPER

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.45 MAC_BLE_0 Register (Offset = 2E8h) [reset = X]
MAC_BLE_0 is shown in Figure 9-149 and described in Table 9-152.
Return to Summary Table.
MAC BLE Address 0
Figure 9-149. MAC_BLE_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR_0_31
R-X

Table 9-152. MAC_BLE_0 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ADDR_0_31

The first 32-bits of the 64-bit MAC BLE address
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

871

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.46 MAC_BLE_1 Register (Offset = 2ECh) [reset = X]
MAC_BLE_1 is shown in Figure 9-150 and described in Table 9-153.
Return to Summary Table.
MAC BLE Address 1
Figure 9-150. MAC_BLE_1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR_32_63
R-X

Table 9-153. MAC_BLE_1 Register Field Descriptions
Bit
31-0

872

Field

Type

Reset

Description

ADDR_32_63

The last 32-bits of the 64-bit MAC BLE address
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.47 MAC_15_4_0 Register (Offset = 2F0h) [reset = X]
MAC_15_4_0 is shown in Figure 9-151 and described in Table 9-154.
Return to Summary Table.
MAC IEEE 802.15.4 Address 0
Figure 9-151. MAC_15_4_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR_0_31
R-X

Table 9-154. MAC_15_4_0 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

ADDR_0_31

The first 32-bits of the 64-bit MAC 15.4 address
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

873

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.48 MAC_15_4_1 Register (Offset = 2F4h) [reset = X]
MAC_15_4_1 is shown in Figure 9-152 and described in Table 9-155.
Return to Summary Table.
MAC IEEE 802.15.4 Address 1
Figure 9-152. MAC_15_4_1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR_32_63
R-X

Table 9-155. MAC_15_4_1 Register Field Descriptions
Bit
31-0

874

Field

Type

Reset

Description

ADDR_32_63

The last 32-bits of the 64-bit MAC 15.4 address
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.49 FLASH_OTP_DATA4 Register (Offset = 308h) [reset = 98989F9Fh]
FLASH_OTP_DATA4 is shown in Figure 9-153 and described in Table 9-156.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-153. FLASH_OTP_DATA4 Register
31
STANDBY_MO
DE_SEL_INT_
WRT
R-1h

30
29
STANDBY_PW_SEL_INT_WRT

28
DIS_STANDBY
_INT_WRT

27
DIS_IDLE_INT
_WRT

R-0h

R-1h

23
STANDBY_MO
DE_SEL_EXT_
WRT
R-1h

22
21
STANDBY_PW_SEL_EXT_WRT

R-0h

R-1h

15
STANDBY_MO
DE_SEL_INT_
RD
R-1h

14
13
STANDBY_PW_SEL_INT_RD

12
DIS_STANDBY
_INT_RD

11
DIS_IDLE_INT
_RD

R-0h

R-1h

7
STANDBY_MO
DE_SEL_EXT_
RD
R-1h

6
5
STANDBY_PW_SEL_EXT_RD

R-0h

20
19
DIS_STANDBY DIS_IDLE_EXT
_EXT_WRT
_WRT

4
3
DIS_STANDBY DIS_IDLE_EXT
_EXT_RD
_RD
R-1h

R-1h

25
VIN_AT_X_INT_WRT

R-0h
18

17
VIN_AT_X_EXT_WRT

R-0h
10

9
VIN_AT_X_INT_RD

R-7h
2

1
VIN_AT_X_EXT_RD

R-7h

Table 9-156. FLASH_OTP_DATA4 Register Field Descriptions
Bit

Field

Type

Reset

Description

STANDBY_MODE_SEL_I
NT_WRT

Internal. Only to be used through TI provided API.

30-29

STANDBY_PW_SEL_INT
_WRT

Internal. Only to be used through TI provided API.

DIS_STANDBY_INT_WR
T

Internal. Only to be used through TI provided API.

DIS_IDLE_INT_WRT

Internal. Only to be used through TI provided API.

26-24

VIN_AT_X_INT_WRT

Internal. Only to be used through TI provided API.

STANDBY_MODE_SEL_
EXT_WRT

Internal. Only to be used through TI provided API.

22-21

STANDBY_PW_SEL_EXT R
_WRT

Internal. Only to be used through TI provided API.

DIS_STANDBY_EXT_WR R
T

Internal. Only to be used through TI provided API.

DIS_IDLE_EXT_WRT

Internal. Only to be used through TI provided API.

18-16

VIN_AT_X_EXT_WRT

Internal. Only to be used through TI provided API.

STANDBY_MODE_SEL_I
NT_RD

Internal. Only to be used through TI provided API.

14-13

STANDBY_PW_SEL_INT
_RD

Internal. Only to be used through TI provided API.

DIS_STANDBY_INT_RD

Internal. Only to be used through TI provided API.

DIS_IDLE_INT_RD

Internal. Only to be used through TI provided API.

10-8

VIN_AT_X_INT_RD

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

875

Factory Configuration (FCFG)

www.ti.com

Table 9-156. FLASH_OTP_DATA4 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

STANDBY_MODE_SEL_
EXT_RD

Internal. Only to be used through TI provided API.

STANDBY_PW_SEL_EXT R
_RD

Internal. Only to be used through TI provided API.

DIS_STANDBY_EXT_RD

Internal. Only to be used through TI provided API.

DIS_IDLE_EXT_RD

Internal. Only to be used through TI provided API.

2-0

VIN_AT_X_EXT_RD

Internal. Only to be used through TI provided API.

7
6-5

876

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.50 MISC_TRIM Register (Offset = 30Ch) [reset = FFFFFF33h]
MISC_TRIM is shown in Figure 9-154 and described in Table 9-157.
Return to Summary Table.
Miscellaneous Trim Parameters
Figure 9-154. MISC_TRIM Register
31

12
11
RESERVED
R-00FFFFFFh

24
23
RESERVED
R-00FFFFFFh
8

4
3
TEMPVSLOPE
R-33h

Table 9-157. MISC_TRIM Register Field Descriptions
Field

Type

Reset

31-8

Bit

RESERVED

00FFFFFFh Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

TEMPVSLOPE

33h

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Signed byte value representing the TEMP slope with battery voltage,
in degrees C / V, with four fractional bits.

Device Configuration

877

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.51 RCOSC_HF_TEMPCOMP Register (Offset = 310h) [reset = 3h]
RCOSC_HF_TEMPCOMP is shown in Figure 9-155 and described in Table 9-158.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-155. RCOSC_HF_TEMPCOMP Register
31

28
27
FINE_RESISTOR
R-0h

12
11
10
CTRIMFRACT_QUAD
R-0h

20
19
CTRIM
R-0h

4
3
2
CTRIMFRACT_SLOPE
R-3h

Table 9-158. RCOSC_HF_TEMPCOMP Register Field Descriptions
Bit

878

Field

Type

Reset

Description

31-24

FINE_RESISTOR

Internal. Only to be used through TI provided API.

23-16

CTRIM

Internal. Only to be used through TI provided API.

15-8

CTRIMFRACT_QUAD

Internal. Only to be used through TI provided API.

7-0

CTRIMFRACT_SLOPE

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.52 TRIM_CAL_REVISION Register (Offset = 314h) [reset = X]
TRIM_CAL_REVISION is shown in Figure 9-156 and described in Table 9-159.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-156. TRIM_CAL_REVISION Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FT1
R-X

8 7
MP1
R-X

Table 9-159. TRIM_CAL_REVISION Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

FT1

Internal. Only to be used through TI provided API.
Default value holds log information from production test.

15-0

MP1

Internal. Only to be used through TI provided API.
Default value holds log information from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

879

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.53 ICEPICK_DEVICE_ID Register (Offset = 318h) [reset = 8B99A02Fh]
ICEPICK_DEVICE_ID is shown in Figure 9-157 and described in Table 9-160.
Return to Summary Table.
IcePick Device Identification
Reading this register or the USER_ID register is the only support way of identifying a device.
Figure 9-157. ICEPICK_DEVICE_ID Register
31

30
29
PG_REV
R-8h

14
13
WAFER_ID
R-B99Ah

22
21
WAFER_ID
R-B99Ah

6
5
4
MANUFACTURER_ID
R-2Fh

Table 9-160. ICEPICK_DEVICE_ID Register Field Descriptions
Bit

880

Field

Type

Reset

Description

31-28

PG_REV

Field used to distinguish revisions of the device.

27-12

WAFER_ID

B99Ah

Field used to identify silicon die.

11-0

MANUFACTURER_ID

2Fh

Manufacturer code.
0x02F: Texas Instruments

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.54 FCFG1_REVISION Register (Offset = 31Ch) [reset = 25h]
FCFG1_REVISION is shown in Figure 9-158 and described in Table 9-161.
Return to Summary Table.
Factory Configuration (FCFG1) Revision
Figure 9-158. FCFG1_REVISION Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
REV
R-25h

Table 9-161. FCFG1_REVISION Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

REV

25h

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

881

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.55 MISC_OTP_DATA Register (Offset = 320h) [reset = X]
MISC_OTP_DATA is shown in Figure 9-159 and described in Table 9-162.
Return to Summary Table.
Misc OTP Data
Figure 9-159. MISC_OTP_DATA Register
31

30
29
RCOSC_HF_ITUNE
R-0h

26
25
RCOSC_HF_CRIM
R-0h

22
21
RCOSC_HF_CRIM
R-0h

15
PER_M
R-1h

13
PER_E
R-4h

17
PER_M
R-1h

10
9
PO_TAIL_RES_TRIM
R-6h

4
3
TEST_PROGRAM_REV
R-X

Table 9-162. MISC_OTP_DATA Register Field Descriptions
Bit

882

Field

Type

Reset

Description

31-28

RCOSC_HF_ITUNE

Internal. Only to be used through TI provided API.

27-20

RCOSC_HF_CRIM

Internal. Only to be used through TI provided API.

19-15

PER_M

Internal. Only to be used through TI provided API.

14-12

PER_E

Internal. Only to be used through TI provided API.

11-8

PO_TAIL_RES_TRIM

Internal. Only to be used through TI provided API.

7-0

TEST_PROGRAM_REV

The revision of the test program used in the production process
when FCFG1 was programmed.
Value migth change without warning.
Default value holds log information from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.56 IOCONF Register (Offset = 344h) [reset = X]
IOCONF is shown in Figure 9-160 and described in Table 9-163.
Return to Summary Table.
IO Configuration
Figure 9-160. IOCONF Register
31

11
10
RESERVED
R-01FFFFFEh

24
23
RESERVED
R-01FFFFFEh
8

3
GPIO_CNT
R-X

Table 9-163. IOCONF Register Field Descriptions
Field

Type

Reset

31-7

Bit

RESERVED

01FFFFFEh Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

GPIO_CNT

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Number of available DIOs.
Default value differs depending on partnumber.

Device Configuration

883

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.57 CONFIG_IF_ADC Register (Offset = 34Ch) [reset = X]
CONFIG_IF_ADC is shown in Figure 9-161 and described in Table 9-164.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-161. CONFIG_IF_ADC Register
31

FF2ADJ
R-3h
23

INT3ADJ
R-6h
15

2
IFANALDO_TRIM_OUTPUT
R-X

INT2ADJ
R-Dh

6
IFDIGLDO_TRIM_OUTPUT
R-X

FF1ADJ
R-0h

AAFCAP
R-3h
7

25
FF3ADJ
R-4h

9
8
IFDIGLDO_TRIM_OUTPUT
R-X
1

Table 9-164. CONFIG_IF_ADC Register Field Descriptions
Bit

884

Field

Type

Reset

Description

31-28

FF2ADJ

Internal. Only to be used through TI provided API.

27-24

FF3ADJ

Internal. Only to be used through TI provided API.

23-20

INT3ADJ

Internal. Only to be used through TI provided API.

19-16

FF1ADJ

Internal. Only to be used through TI provided API.

15-14

AAFCAP

Internal. Only to be used through TI provided API.

13-10

INT2ADJ

Internal. Only to be used through TI provided API.

9-5

IFDIGLDO_TRIM_OUTPU R
T

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

4-0

IFANALDO_TRIM_OUTP
UT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.58 CONFIG_OSC_TOP Register (Offset = 350h) [reset = X]
CONFIG_OSC_TOP is shown in Figure 9-162 and described in Table 9-165.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-162. CONFIG_OSC_TOP Register
31

28
27
XOSC_HF_ROW_Q12
R-Fh

20
19
XOSC_HF_COLUMN_Q12
R-3Fh

13
12
XOSC_HF_COLUMN_Q12
R-3Fh

9
8
RCOSCLF_CTUNE_TRIM
R-X

5
4
RCOSCLF_CTUNE_TRIM
R-X

1
0
RCOSCLF_RTUNE_TRIM
R-0h

RESERVED
R-3h

25
24
XOSC_HF_COLUMN_Q12
R-3Fh
17

Table 9-165. CONFIG_OSC_TOP Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

RESERVED

Internal. Only to be used through TI provided API.

29-26

XOSC_HF_ROW_Q12

Internal. Only to be used through TI provided API.

25-10

XOSC_HF_COLUMN_Q1
2

3Fh

Internal. Only to be used through TI provided API.

9-2

RCOSCLF_CTUNE_TRIM R

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

1-0

RCOSCLF_RTUNE_TRIM R

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

885

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.59 CONFIG_RF_FRONTEND Register (Offset = 354h) [reset = X]
CONFIG_RF_FRONTEND is shown in Figure 9-163 and described in Table 9-166.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-163. CONFIG_RF_FRONTEND Register
31

IFAMP_IB
R-7h
23

15
14
CTL_PA0_TRIM
R-X
7
RESERVED
R-3Fh

LNA_IB
R-X

21
IFAMP_TRIM
R-0h

17
CTL_PA0_TRIM
R-X

13
PATRIMCOMP
LETE_N
R-X

10
RESERVED

3
RFLDO_TRIM_OUTPUT
R-X

R-3Fh
2

Table 9-166. CONFIG_RF_FRONTEND Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

IFAMP_IB

Internal. Only to be used through TI provided API.

27-24

LNA_IB

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

23-19

IFAMP_TRIM

Internal. Only to be used through TI provided API.

18-14

CTL_PA0_TRIM

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

PATRIMCOMPLETE_N

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

12-7

RESERVED

3Fh

Internal. Only to be used through TI provided API.

6-0

RFLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

886

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.60 CONFIG_SYNTH Register (Offset = 358h) [reset = X]
CONFIG_SYNTH is shown in Figure 9-164 and described in Table 9-167.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-164. CONFIG_SYNTH Register
31

30
29
RESERVED
R-Fh

23
22
21
20
RFC_MDM_DEMIQMC0
R-FFFFh

15
14
13
12
RFC_MDM_DEMIQMC0
R-FFFFh

10
9
8
7
LDOVCO_TRIM_OUTPUT
R-X

3
2
1
SLDO_TRIM_OUTPUT
R-X

Table 9-167. CONFIG_SYNTH Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

RESERVED

Internal. Only to be used through TI provided API.

27-12

RFC_MDM_DEMIQMC0

FFFFh

Internal. Only to be used through TI provided API.

11-6

LDOVCO_TRIM_OUTPU
T

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

5-0

SLDO_TRIM_OUTPUT

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

887

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.61 SOC_ADC_ABS_GAIN Register (Offset = 35Ch) [reset = X]
SOC_ADC_ABS_GAIN is shown in Figure 9-165 and described in Table 9-168.
Return to Summary Table.
AUX_ADC Gain in Absolute Reference Mode
Figure 9-165. SOC_ADC_ABS_GAIN Register
31

24
23
RESERVED
R-X

9
8
7
6
SOC_ADC_ABS_GAIN_TEMP1
R-X

Table 9-168. SOC_ADC_ABS_GAIN Register Field Descriptions
Bit

888

Field

Type

Reset

Description

31-16

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Default value holds log information from production test.

15-0

SOC_ADC_ABS_GAIN_T
EMP1

SOC_ADC gain in absolute reference mode at temperature 1 (30C).
Calculated in production test..
Default value holds log information from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.62 SOC_ADC_REL_GAIN Register (Offset = 360h) [reset = X]
SOC_ADC_REL_GAIN is shown in Figure 9-166 and described in Table 9-169.
Return to Summary Table.
AUX_ADC Gain in Relative Reference Mode
Figure 9-166. SOC_ADC_REL_GAIN Register
31

24
23
RESERVED
R-X

9
8
7
6
SOC_ADC_REL_GAIN_TEMP1
R-X

Table 9-169. SOC_ADC_REL_GAIN Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Default value holds trim value from production test.

15-0

SOC_ADC_REL_GAIN_T
EMP1

SOC_ADC gain in relative reference mode at temperature 1 (30C).
Calculated in production test..
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

889

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.63 SOC_ADC_OFFSET_INT Register (Offset = 368h) [reset = X]
SOC_ADC_OFFSET_INT is shown in Figure 9-167 and described in Table 9-170.
Return to Summary Table.
AUX_ADC Temperature Offsets in Absolute Reference Mode
Figure 9-167. SOC_ADC_OFFSET_INT Register
31

28
27
RESERVED
R-X

21
20
19
18
SOC_ADC_REL_OFFSET_TEMP1
R-X

12
11
RESERVED
R-X

5
4
3
2
SOC_ADC_ABS_OFFSET_TEMP1
R-X

Table 9-170. SOC_ADC_OFFSET_INT Register Field Descriptions
Bit

890

Field

Type

Reset

Description

31-24

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Default value holds trim value from production test.

23-16

SOC_ADC_REL_OFFSET R
_TEMP1

SOC_ADC offset in relative reference mode at temperature 1 (30C).
Signed 8-bit number. Calculated in production test..
Default value holds trim value from production test.

15-8

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Default value holds trim value from production test.

7-0

SOC_ADC_ABS_OFFSE
T_TEMP1

SOC_ADC offset in absolute reference mode at temperature 1
(30C). Signed 8-bit number. Calculated in production test..
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.64 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register (Offset = 36Ch) [reset = X]
SOC_ADC_REF_TRIM_AND_OFFSET_EXT is shown in Figure 9-168 and described in Table 9-171.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-168. SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register
31

RESERVED
R-302h
23

20
RESERVED
R-302h

12
RESERVED
R-302h

RESERVED
R-302h

3
2
SOC_ADC_REF_VOLTAGE_TRIM_TEMP1
R-X

Table 9-171. SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-6

RESERVED

302h

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

5-0

SOC_ADC_REF_VOLTA
GE_TRIM_TEMP1

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

891

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.65 AMPCOMP_TH1 Register (Offset = 370h) [reset = FF7B828Eh]
AMPCOMP_TH1 is shown in Figure 9-169 and described in Table 9-172.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-169. AMPCOMP_TH1 Register
31

21
20
HPMRAMP3_LTH
R-1Eh

13
12
HPMRAMP3_HTH
R-20h

3
2
HPMRAMP1_TH
R-Eh

RESERVED
R-FFh
23

7
6
IBIASCAP_LPTOHP_OL_CNT
R-Ah

16
RESERVED
R-3h

9
8
IBIASCAP_LPTOHP_OL_CNT
R-Ah
1

Table 9-172. AMPCOMP_TH1 Register Field Descriptions
Bit

892

Field

Type

Reset

Description

31-24

RESERVED

FFh

Internal. Only to be used through TI provided API.

23-18

HPMRAMP3_LTH

1Eh

Internal. Only to be used through TI provided API.

17-16

RESERVED

Internal. Only to be used through TI provided API.

15-10

HPMRAMP3_HTH

20h

Internal. Only to be used through TI provided API.

9-6

IBIASCAP_LPTOHP_OL_ R
CNT

Internal. Only to be used through TI provided API.

5-0

HPMRAMP1_TH

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.66 AMPCOMP_TH2 Register (Offset = 374h) [reset = 6B8B0303h]
AMPCOMP_TH2 is shown in Figure 9-170 and described in Table 9-173.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-170. AMPCOMP_TH2 Register
31

29
28
LPMUPDATE_LTH
R-1Ah

21
20
LPMUPDATE_HTM
R-22h

13
12
ADC_COMP_AMPTH_LPM
R-0h

5
4
ADC_COMP_AMPTH_HPM
R-0h

24
RESERVED
R-3h

16
RESERVED
R-3h

8
RESERVED
R-3h

0
RESERVED
R-3h

Table 9-173. AMPCOMP_TH2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-26

LPMUPDATE_LTH

1Ah

Internal. Only to be used through TI provided API.

25-24

RESERVED

Internal. Only to be used through TI provided API.

23-18

LPMUPDATE_HTM

22h

Internal. Only to be used through TI provided API.

17-16

RESERVED

Internal. Only to be used through TI provided API.

15-10

ADC_COMP_AMPTH_LP
M

Internal. Only to be used through TI provided API.

9-8

RESERVED

Internal. Only to be used through TI provided API.

7-2

ADC_COMP_AMPTH_HP R
M

Internal. Only to be used through TI provided API.

1-0

RESERVED

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

893

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.67 AMPCOMP_CTRL1 Register (Offset = 378h) [reset = FF183F47h]
AMPCOMP_CTRL1 is shown in Figure 9-171 and described in Table 9-174.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-171. AMPCOMP_CTRL1 Register
31
RESERVED
R-1h

30
AMPCOMP_RE
Q_MODE
R-1h

RESERVED
R-3Fh

22
21
IBIAS_OFFSET
R-1h

18
IBIAS_INIT
R-8h

12
11
LPM_IBIAS_WAIT_CNT_FINAL
R-3Fh

CAP_STEP
R-4h

2
1
IBIASCAP_HPTOLP_OL_CNT
R-7h

Table 9-174. AMPCOMP_CTRL1 Register Field Descriptions

894

Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

AMPCOMP_REQ_MODE

Internal. Only to be used through TI provided API.

29-24

RESERVED

3Fh

Internal. Only to be used through TI provided API.

23-20

IBIAS_OFFSET

Internal. Only to be used through TI provided API.

19-16

IBIAS_INIT

Internal. Only to be used through TI provided API.

15-8

LPM_IBIAS_WAIT_CNT_
FINAL

3Fh

Internal. Only to be used through TI provided API.

7-4

CAP_STEP

Internal. Only to be used through TI provided API.

3-0

IBIASCAP_HPTOLP_OL_ R
CNT

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.68 ANABYPASS_VALUE2 Register (Offset = 37Ch) [reset = FFFFC3FFh]
ANABYPASS_VALUE2 is shown in Figure 9-172 and described in Table 9-175.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-172. ANABYPASS_VALUE2 Register
31

15
14
RESERVED
R-0003FFFFh

24
23
RESERVED
R-0003FFFFh

8
7
6
5
XOSC_HF_IBIASTHERM
R-3FFh

Table 9-175. ANABYPASS_VALUE2 Register Field Descriptions
Field

Type

Reset

Description

31-14

Bit

RESERVED

0003FFFFh

Internal. Only to be used through TI provided API.

13-0

XOSC_HF_IBIASTHERM

3FFh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

895

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.69 CONFIG_MISC_ADC Register (Offset = 380h) [reset = X]
CONFIG_MISC_ADC is shown in Figure 9-173 and described in Table 9-176.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-173. CONFIG_MISC_ADC Register
31

12
RSSI_OFFSET

8
QUANTCTLTH
RES
R-5h

RESERVED
R-3FFFh
23

21
RESERVED
R-3FFFh

17
16
RSSITRIMCOM RSSI_OFFSET
PLETE_N
R-X
R-X

R-X
7
6
QUANTCTLTHRES
R-5h

3
DACTRIM
R-Dh

Table 9-176. CONFIG_MISC_ADC Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

3FFFh

Internal. Only to be used through TI provided API.

RSSITRIMCOMPLETE_N

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

16-9

RSSI_OFFSET

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

8-6

QUANTCTLTHRES

Internal. Only to be used through TI provided API.

5-0

DACTRIM

Internal. Only to be used through TI provided API.

31-18
17

896

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.70 VOLT_TRIM Register (Offset = 388h) [reset = X]
VOLT_TRIM is shown in Figure 9-174 and described in Table 9-177.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-174. VOLT_TRIM Register
31

30
RESERVED
R-7h

26
VDDR_TRIM_HH
R-1Fh

22
RESERVED
R-7h

18
VDDR_TRIM_H
R-1Fh

14
RESERVED
R-7h

10
VDDR_TRIM_SLEEP_H
R-1Fh

6
RESERVED
R-7h

2
TRIMBOD_H
R-X

Table 9-177. VOLT_TRIM Register Field Descriptions
Bit

Field

Type

Reset

Description

31-29

RESERVED

Internal. Only to be used through TI provided API.

28-24

VDDR_TRIM_HH

1Fh

Internal. Only to be used through TI provided API.

23-21

RESERVED

Internal. Only to be used through TI provided API.

20-16

VDDR_TRIM_H

1Fh

Internal. Only to be used through TI provided API.

15-13

RESERVED

Internal. Only to be used through TI provided API.

12-8

VDDR_TRIM_SLEEP_H

1Fh

Internal. Only to be used through TI provided API.

7-5

RESERVED

Internal. Only to be used through TI provided API.

4-0

TRIMBOD_H

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

897

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.71 OSC_CONF Register (Offset = 38Ch) [reset = X]
OSC_CONF is shown in Figure 9-175 and described in Table 9-178.
Return to Summary Table.
OSC Configuration
Figure 9-175. OSC_CONF Register
31

30
RESERVED

29
ADC_SH_VBU
F_EN

R-3h

R-1h

22
21
XOSCLF_CMIRRWR_RATIO

28
27
ADC_SH_MOD ATESTLF_RC
E_EN
OSCLF_IBIAS_
TRIM
R-1h
R-0h

26
25
XOSCLF_REGULATOR_TRIM

24
XOSCLF_CMIR
RWR_RATIO

R-0h

20
19
XOSC_HF_FAST_START

18
XOSC_OPTIO
N

17
HPOSC_OPTI
ON

R-1h

R-X

R-0h
15

14
13
HPOSC_CURRMIRR_RATIO
R-X

7
HPOSC_FILTE
R_EN
R-X

6
5
HPOSC_BIAS_RECHARGE_DE
LAY
R-X

16
HPOSC_BIAS_
HOLD_MODE_
EN
R-0h

10
9
HPOSC_BIAS_RES_SET
R-X

3
RESERVED

2
1
HPOSC_SERIES_CAP

R-X

0
HPOSC_DIV3_
BYPASS
R-X

Table 9-178. OSC_CONF Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ADC_SH_VBUF_EN

Trim value for
DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN.

ADC_SH_MODE_EN

Trim value for
DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN.

ATESTLF_RCOSCLF_IBI
AS_TRIM

Trim value for
DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM.

26-25

XOSCLF_REGULATOR_
TRIM

Trim value for
DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM.

24-21

XOSCLF_CMIRRWR_RA
TIO

Trim value for
DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO.

20-19

XOSC_HF_FAST_START R

Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START.

XOSC_OPTION

0: XOSC_HF unavailable (may not be bonded out)
1: XOSC_HF available (default)
Default value differs depending on partnumber.

HPOSC_OPTION

Internal. Only to be used through TI provided API.
Default value differs depending on partnumber.

HPOSC_BIAS_HOLD_M
ODE_EN

Internal. Only to be used through TI provided API.

15-12

HPOSC_CURRMIRR_RA
TIO

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

11-8

HPOSC_BIAS_RES_SET

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

HPOSC_FILTER_EN

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

31-30

898

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

Table 9-178. OSC_CONF Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

6-5

HPOSC_BIAS_RECHAR
GE_DELAY

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

4-3

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Default value holds trim value from production test.

2-1

HPOSC_SERIES_CAP

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

HPOSC_DIV3_BYPASS

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

899

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.72 FREQ_OFFSET Register (Offset = 390h) [reset = X]
FREQ_OFFSET is shown in Figure 9-176 and described in Table 9-179.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-176. FREQ_OFFSET Register
31

12
11
10
HPOSC_COMP_P1
R-X

24
23
22
HPOSC_COMP_P0
R-X
8

4
3
HPOSC_COMP_P2
R-X

Table 9-179. FREQ_OFFSET Register Field Descriptions
Bit

900

Field

Type

Reset

Description

31-16

HPOSC_COMP_P0

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

15-8

HPOSC_COMP_P1

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

7-0

HPOSC_COMP_P2

Internal. Only to be used through TI provided API.
Default value holds trim value from production test.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.73 CAP_TRIM Register (Offset = 394h) [reset = FFFFFFFFh]
CAP_TRIM is shown in Figure 9-177 and described in Table 9-180.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-177. CAP_TRIM Register
31

25
24
23
22
FLUX_CAP_0P28_TRIM
R-FFFFh

8
7
6
FLUX_CAP_0P4_TRIM
R-FFFFh

Table 9-180. CAP_TRIM Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

FLUX_CAP_0P28_TRIM

FFFFh

Internal. Only to be used through TI provided API.

15-0

FLUX_CAP_0P4_TRIM

FFFFh

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

901

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.74 MISC_OTP_DATA_1 Register (Offset = 398h) [reset = E00403F8h]
MISC_OTP_DATA_1 is shown in Figure 9-178 and described in Table 9-181.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 9-178. MISC_OTP_DATA_1 Register
31

30
RESERVED
R-7h

23
22
LP_BUF_ITRIM
R-0h
15

21
20
DBLR_LOOP_FILTER_RESET_
VOLTAGE
R-0h

13
12
HPM_IBIAS_WAIT_CNT
R-100h

28
27
PEAK_DET_ITRIM
R-0h

6
5
LPM_IBIAS_WAIT_CNT
R-3Fh

25
HP_BUF_ITRIM
R-0h

18
17
HPM_IBIAS_WAIT_CNT

R-100h
9
8
LPM_IBIAS_WAIT_CNT
R-3Fh
1

IDAC_STEP
R-8h

Table 9-181. MISC_OTP_DATA_1 Register Field Descriptions
Bit

902

Field

Type

Reset

Description

31-29

RESERVED

Internal. Only to be used through TI provided API.

28-27

PEAK_DET_ITRIM

Internal. Only to be used through TI provided API.

26-24

HP_BUF_ITRIM

Internal. Only to be used through TI provided API.

23-22

LP_BUF_ITRIM

Internal. Only to be used through TI provided API.

21-20

DBLR_LOOP_FILTER_R
ESET_VOLTAGE

Internal. Only to be used through TI provided API.

19-10

HPM_IBIAS_WAIT_CNT

100h

Internal. Only to be used through TI provided API.

9-4

LPM_IBIAS_WAIT_CNT

3Fh

Internal. Only to be used through TI provided API.

3-0

IDAC_STEP

Internal. Only to be used through TI provided API.

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.75 PWD_CURR_20C Register (Offset = 39Ch) [reset = 080BA608h]
PWD_CURR_20C is shown in Figure 9-179 and described in Table 9-182.
Return to Summary Table.
Power Down Current Control 20C
Figure 9-179. PWD_CURR_20C Register
31

28
27
26
DELTA_CACHE_REF
R-8h

12
11
10
DELTA_XOSC_LPM
R-A6h

20
19
18
DELTA_RFMEM_RET
R-Bh
4
3
BASELINE
R-8h

Table 9-182. PWD_CURR_20C Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

DELTA_CACHE_REF

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

A6h

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

903

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.76 PWD_CURR_35C Register (Offset = 3A0h) [reset = 0C10A50Ah]
PWD_CURR_35C is shown in Figure 9-180 and described in Table 9-183.
Return to Summary Table.
Power Down Current Control 35C
Figure 9-180. PWD_CURR_35C Register
31

28
27
26
DELTA_CACHE_REF
R-Ch

12
11
10
DELTA_XOSC_LPM
R-A5h

20
19
18
DELTA_RFMEM_RET
R-10h
4
3
BASELINE
R-Ah

Table 9-183. PWD_CURR_35C Register Field Descriptions
Bit

904

Field

Type

Reset

Description

31-24

DELTA_CACHE_REF

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

10h

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

A5h

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.77 PWD_CURR_50C Register (Offset = 3A4h) [reset = 1218A20Dh]
PWD_CURR_50C is shown in Figure 9-181 and described in Table 9-184.
Return to Summary Table.
Power Down Current Control 50C
Figure 9-181. PWD_CURR_50C Register
31

28
27
26
DELTA_CACHE_REF
R-12h

12
11
10
DELTA_XOSC_LPM
R-A2h

20
19
18
DELTA_RFMEM_RET
R-18h
4
3
BASELINE
R-Dh

Table 9-184. PWD_CURR_50C Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

DELTA_CACHE_REF

12h

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

18h

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

A2h

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

905

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.78 PWD_CURR_65C Register (Offset = 3A8h) [reset = 1C259C14h]
PWD_CURR_65C is shown in Figure 9-182 and described in Table 9-185.
Return to Summary Table.
Power Down Current Control 65C
Figure 9-182. PWD_CURR_65C Register
31

28
27
26
DELTA_CACHE_REF
R-1Ch

12
11
10
DELTA_XOSC_LPM
R-9Ch

20
19
18
DELTA_RFMEM_RET
R-25h
4
3
BASELINE
R-14h

Table 9-185. PWD_CURR_65C Register Field Descriptions
Bit

906

Field

Type

Reset

Description

31-24

DELTA_CACHE_REF

1Ch

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

25h

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

9Ch

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

14h

Worst-case baseline maximum powerdown current, in units of 0.5uA

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.79 PWD_CURR_80C Register (Offset = 3ACh) [reset = 2E3B9021h]
PWD_CURR_80C is shown in Figure 9-183 and described in Table 9-186.
Return to Summary Table.
Power Down Current Control 80C
Figure 9-183. PWD_CURR_80C Register
31

28
27
26
DELTA_CACHE_REF
R-2Eh

12
11
10
DELTA_XOSC_LPM
R-90h

20
19
18
DELTA_RFMEM_RET
R-3Bh
4
3
BASELINE
R-21h

Table 9-186. PWD_CURR_80C Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

DELTA_CACHE_REF

2Eh

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

3Bh

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

90h

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

21h

Worst-case baseline maximum powerdown current, in units of 0.5uA

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

907

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.80 PWD_CURR_95C Register (Offset = 3B0h) [reset = 4C627A3Bh]
PWD_CURR_95C is shown in Figure 9-184 and described in Table 9-187.
Return to Summary Table.
Power Down Current Control 95C
Figure 9-184. PWD_CURR_95C Register
31

28
27
26
DELTA_CACHE_REF
R-4Ch

12
11
10
DELTA_XOSC_LPM
R-7Ah

20
19
18
DELTA_RFMEM_RET
R-62h
4
3
BASELINE
R-3Bh

Table 9-187. PWD_CURR_95C Register Field Descriptions
Bit

908

Field

Type

Reset

Description

31-24

DELTA_CACHE_REF

4Ch

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

62h

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

7Ah

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

3Bh

Worst-case baseline maximum powerdown current, in units of 0.5uA

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.81 PWD_CURR_110C Register (Offset = 3B4h) [reset = 789E706Bh]
PWD_CURR_110C is shown in Figure 9-185 and described in Table 9-188.
Return to Summary Table.
Power Down Current Control 110C
Figure 9-185. PWD_CURR_110C Register
31

28
27
26
DELTA_CACHE_REF
R-78h

12
11
10
DELTA_XOSC_LPM
R-70h

20
19
18
DELTA_RFMEM_RET
R-9Eh
4
3
BASELINE
R-6Bh

Table 9-188. PWD_CURR_110C Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

DELTA_CACHE_REF

78h

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

9Eh

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

70h

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

6Bh

Worst-case baseline maximum powerdown current, in units of 0.5uA

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Device Configuration

909

Factory Configuration (FCFG)

www.ti.com

9.2.2.1.82 PWD_CURR_125C Register (Offset = 3B8h) [reset = ADE1809Ah]
PWD_CURR_125C is shown in Figure 9-186 and described in Table 9-189.
Return to Summary Table.
Power Down Current Control 125C
Figure 9-186. PWD_CURR_125C Register
31

28
27
26
DELTA_CACHE_REF
R-ADh

12
11
10
DELTA_XOSC_LPM
R-80h

20
19
18
DELTA_RFMEM_RET
R-E1h
4
3
BASELINE
R-9Ah

Table 9-189. PWD_CURR_125C Register Field Descriptions
Bit

910

Field

Type

Reset

Description

31-24

DELTA_CACHE_REF

ADh

Additional maximum current, in units of 1uA, with cache retention

23-16

DELTA_RFMEM_RET

E1h

Additional maximum current, in 1uA units, with RF memory retention

15-8

DELTA_XOSC_LPM

80h

Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode

7-0

BASELINE

9Ah

Worst-case baseline maximum powerdown current, in units of 0.5uA

Device Configuration

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Chapter 10
SWCU117G – February 2015 – Revised February 2017

Cryptography
The security core of the CC26x0 and CC13x0 features an advanced encryption standard (AES) module
with 128-bit key support, local key storage, and DMA capability. This chapter provides the description and
information for configuring the AES engine.
Topic

10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9

...........................................................................................................................
AES Cryptoprocessor Overview .........................................................................
Functional Description ......................................................................................
Power Management and Sleep Modes .................................................................
Hardware Description........................................................................................
Module Description ...........................................................................................
Performance ....................................................................................................
Programming Guidelines ...................................................................................
Conventions and Compliances ...........................................................................
Cryptography Registers ....................................................................................

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography

Page

912
912
913
913
914
925
926
937
939

911

AES Cryptoprocessor Overview

www.ti.com

10.1 AES Cryptoprocessor Overview
The AES security module provides hardware-accelerated data encryption and decryption operations
based on a binary key. The module supports a 128-bit key in hardware for encryption and decryption and
uses symmetric algorithm, meaning that the encryption and decryption keys are identical. Encryption
converts plain text data to an unintelligible form called cipher text. Decrypting cipher text converts
previously encrypted data back into its original plain text form.
The main features of the AES module are:
• Support and availability of the following operating modes:
– Electronic code book mode (ECB)
– Cipher block chaining mode (CBC)
– Cipher block chaining message authentication code (CBC-MAC)
– Counter mode (CTR)
– Counter mode with CBC-MAC (CCM)
• Key size: 128 bits
• Support for CBC-MAC authentication modes
• Key scheduling in hardware
• Support for DMA transfers
• Fully synchronous design
ECB, CBC, CTR, and CCM modes require reading and writing of data. CBC-MAC requires only reading of
the data from an external source. The CCM modes of operation returns an authentication result. This
result can either be DMAed out with a separate DMA operation, or read through the slave interface. For all
modes, there is an option to provide the data through the slave interface instead of using DMA. The AES
engine is forced to use keys from the key store module for its operations. A key is provided to the AES
engine by triggering the key store module to read an AES key from the key store memory, and to write it
to the AES key registers. The AES engine automatically pads or masks misaligned last data blocks with
zeroes for AES CBC-MAC and CCM (including misaligned AAD data). For AES CTR mode, misaligned
last data blocks are internally masked to support nonblock size input data.

10.2 Functional Description
The AES engine is directly connected to the context and data registers so that it can immediately start
processing when all data is available. The AES engine also interfaces to the I/O-control FSM and DMA
request interface. AES comprises the following major functional blocks:
• Global control FSM and DMA interface
• Register interface module
• The AES engine
The AES engine, which is the major top-level component, comprises the following functional blocks:
• Mode-control FSM: manages the data flow to and from the AES engine and starts each encryption and
decryption operation.
• Feedback modes: the logic that implements the various feedback modes supported by AES.
• AES key scheduler: generates AES encryption and decryption (round) keys
• AES encryption core: the AES encryption algorithm
• AES decryption core: the AES decryption algorithm
• Substitution-boxes (S-boxes): contain AES S-Box GF(28) implementations.
The supported key length is 128-bit, which requires 10 rounds or 32 clock cycles, because {number of
clock cycles} = 2 + 3 × {number of rounds}. While one data block processes, the next block can be
preloaded immediately. When a block is preloaded, the previous block must finish before additional data
can be loaded. Therefore, once the pipeline is full, sequential data blocks can be passed every 32 clock
cycles.

912

Cryptography

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

10.2.1 Debug Capabilities
The AES module provides the following status registers to monitor operations of the engine:
• DMA status and port-error status registers
• Interrupt status registers in the master control module
• Key-store module status register

10.2.2 Exception Handling
The AES module can detect AHB master bus errors and abort the DMA operation. The AES key-store
module can detect key-load errors and does not store the bad key in that case. In both cases, the status
register in the master control module indicates the error.

10.3 Power Management and Sleep Modes
There is no retention logic for cryptography registers. The clocks can be enabled or gated by the following
PRCM registers:
• SECDMACLKGR.CRYPTO_CLK_EN bit while in run mode
• SECDMASCLKG.CRYPTO_CLK_EN bit while in sleep mode
• SECDMACLKGDS.CRYPTO_CLK_EN bit while in deepsleep mode
The cryptography module is enabled and disabled by the SECDMAHWOPT.CRYPTO_EN bit.
To save power, the application can disable the clock to the AES module when not in use. The AES is
clock-gated in sleep mode by setting the SECDMACLKGS register CRYPTO_CLK_EN bit. The AES can
also be clock-gated in run mode by setting the SECDMACLKGR register CRYPTO_CLK_EN bit.

10.4 Hardware Description
10.4.1 AHB Slave Bus
Internal registers of the AES module are accessed by the slave interface. The AHB slave interface
accepts 8-, 16-, and 32-bit transfers. However, the AES module accepts only 32-bit single access.
As each transfer is checked for multiple error conditions depending on the address, size, and type of the
transfer, these checks are performed on registered signals to improve timing on the input signals.
Therefore, one wait cycle must be inserted for each transfer. If an ERROR response occurs, h_ready_out
must be taken low one cycle after reception of the address. This results in the following timing:
• Write transfers take two clock cycles.
• Read transfers take three clock cycles.
The AHB slave handles only the little-endian transfers, and for register access only 32-bit single accesses
are allowed.

10.4.2 AHB Master Bus
The module is configured by the DMA configuration DMABUSCFG register (refer to Section 10.9.1.9) and
performs single 8-bit or 32-bit nonsequential single transfers by default. Transfer addresses and length
parameters of the DMA transfer are byte aligned.
When the AES module requests a DMA transfer, the AHB master asserts and signals to indicate to the
arbiter that it requires the bus. This signal stays asserted until the address phase of the last transfer of the
DMA and no new DMA transfers are requested.
When no DMA transfers are requested, the AHB master performs IDLE transfers. If the AHB master is
already granted and gets the DMA request, the first write transfer is an IDLE transfer. The last transfer is
always an IDLE transfer.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography

913

Hardware Description

www.ti.com

If the AHB_MST1_LOCK_EN bit is asserted, the AHB master asserts a lock signal to indicate the AHB is
performing a number of indivisible transfers. The arbiter does not grant any other AHB master access to
the bus when the first transfer of the sequence of locked transfers has commenced. The AHB master
inserts an IDLE transfer after each block sequence.
The AHB master can handle big- and little-endian transfers. The AES module is little-endian oriented
internally. However, when connected to a big-endian AHB system, a conversion from big to little endian
can be done in the AHB master interface. By default, a little-endian oriented AHB-host system is assumed.
When the AHB system is big-endian oriented, the AHB_MST1_BIGEND bit must be set to 1.
NOTE: The CC26x0 and CC13x0 devices do not support burst or nonsequential transfers through
internal interconnect. The DMABUSCFG register must not be changed for proper operation.

10.4.3 Interrupts
The AES module has two interrupt outputs; both are driven from the master control module and are
controlled by the respective registers (see Section 10.5.4.3).
To enable interrupts for the AES engine, the IRQTYPE.EN bit must be set and the interrupt source must
be configured in the IRQEN register.
The IRQCLR register is available to clear an interrupt output and error-status bit. The IRQSET register
provides the software a way to test the interrupt connections and must be used for debugging only.
The IRQSTAT register provides the status of the two interrupts along with error status messages. The
error status bits are asserted once they are detected, and typically the value of DMA_BUS_ERR and
KEY_ST_WR_ERR signals are valid after the RESULT_AVAIL bit is asserted. The KEY_ST_RD_ERR bit
is valid after triggering the key store module to read a key from memory and providing it to the AES
engine.
An interrupt RESULT_AVAIL is activated when an operation that uses DMA is finished. The signal asserts
when both the DMA and internal module are in the IDLE state.
Another interrupt DMA_IN_DONE is activated when only the input DMA is finished and is intended for
debugging.
NOTE: Interrupt outputs are not triggered for operations where the DMA is not used.

10.5 Module Description
10.5.1 Introduction
This section describes some accessible registers, internal interfaces, and module functionality. The
registers and functionality are discussed for each submodule. For complete information on the module
registers, see Section 10.9.1.

10.5.2 Module Memory Map
Table 10-1. Detailed Memory Map
Physical Address

Type

Reset Value

Remark

Link

DMA Controller Registers
0x4002 4000

DMACH0CTL

R/W

0x0000 0000

Channel 0 control
register

Section 10.9.1.1

0x4002 4004

DMACH0EXTADDR

R/W

0x0000 0000

Channel 0 external
address

Section 10.9.1.2

0x4002 400C

DMACH0LEN

R/W

0x0000 0000

Channel 0 DMA
length

Section 10.9.1.3

0x4002 4018

DMASTAT

0x0000 0000

DMAC status

Section 10.9.1.4

914 Cryptography

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Module Description

www.ti.com

Table 10-1. Detailed Memory Map (continued)
Physical Address

Type

Reset Value

Remark

Link
Section 10.9.1.5

0x4002 401C

DMASWRESET

0x0000 0000

DMAC software
reset

0x4002 4020

DMACH1CTL

R/W

0x0000 0000

Channel 1 control
register

Section 10.9.1.6

0x4002 4024

DMACH1EXTADDR

R/W

0x0000 0000

Channel 1 external
address

Section 10.9.1.7

0x4002 402C

DMACH1LEN

R/W

0x0000 0000

Channel 1 DMA
length

Section 10.9.1.8

0x4002 4078

DMABUSCFG

R/W

0x0000 6000

Master run-time
parameters

Section 10.9.1.9

0x4002 407C

DMAPORTERR

0x0000 0000

Port-error raw-status
Section 10.9.1.10
register

0x4002 40F8

DMAHWOPT

0x0000 0202

DMAC-options
register

0x4002 40FC

DMAHWVER

0x0101 2ED1

DMAC-version
register

Section 10.9.1.11

Key-Storage Registers
0x4002 4400

KEYWRITEAREA

R/W

0x0000 0000

Writer-area register

Section 10.9.1.12

0x4002 4404

KEYWRITTENAREA

R/W

0x0000 0000

Written-area register

Section 10.9.1.13

0x4002 4408

KEYSIZE

R/W

0x0000 0001

Key-size register

Section 10.9.1.14

0x4002 440C

KEYREADAREA

R/W

0x0000 0008

Read-area register

Section 10.9.1.15

Section 10.9.1.16

AES Engine Registers
0x4002 4500 to
0x4002 450C

AESKEY2_0 to AESKEY2_3

0x0000 0000

Clear/wipe
AESKEY2__0 to
AESKEY2__3
register

0x4002 4510 to
0x4002 451C

AESKEY3_0 to AESKEY3_3

0x0000 0000

Clear/wipe
AESKEY3__0 to
AESKEY3__3
register

Section 10.9.1.17

0x4002 4540 to
0x4002 454C

AESIV_0 to AESIV_3

R/W

0x0000 0000

AES IV (LSW)

Section 10.9.1.18

0x4002 4550

AESCTL

R/W

0x8000 0000

I/O and control mode Section 10.9.1.19

0x4002 4554

AESDATALEN0

0x0000 0000

Crypto data length
(LSW)

Section 10.9.1.20

0x4002 4558

AESDATALEN1

0x0000 0000

Crypto data length
(MSW)

Section 10.9.1.21

0x4002 455C

AESAUTHLEN

0x0000 0000

AAD data length

Section 10.9.1.22

0x4002 4560

AESDATAIN0

0x0000 0000

Data input (LSW)

Section 10.9.1.24

0x4002 4560

AESDATAOUT0

0x0000 0000

Data output (LSW)

Section 10.9.1.23

0x4002 4564

AESDATAIN1

0x0000 0000

Data input

Section 10.9.1.26

0x4002 4564

AESDATAOUT1

0x0000 0000

Data output

Section 10.9.1.25

0x4002 4568

AESDATAIN2

0x0000 0000

Data input

Section 10.9.1.28

0x4002 4568

AESDATAOUT2

0x0000 0000

Data output

Section 10.9.1.27

0x4002 456C

AESDATAIN3

0x0000 0000

Data input (MSW)

Section 10.9.1.30

0x4002 456C

AESDATAOUT3

0x0000 0000

Data output (MSW)

Section 10.9.1.29

0x4002 4570 to
0x4002 4057C

AESTAGOUT_0 to
AESTAGOUT_3

0x0000 0000

Tag output (LSW)

Section 10.9.1.31

R/W

0x0000 0000

Algorithm selection

Section 10.9.1.32
Section 10.9.1.33
Section 10.9.1.34

Master-Control Registers
0x4002 4700

ALGSEL

0x4002 4704

DMAPROTCTL

R/W

0x0000 0000

Enable privileged
access on master

0x4002 4740

SWRESET

0x0000 0000

Master-control
software reset

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Cryptography 915

Module Description

www.ti.com

Table 10-1. Detailed Memory Map (continued)
Physical Address

Type

Reset Value

Remark

Link

0x4002 4780

IRQTYPE

R/W

0x0000 0000

InterruptSection 10.9.1.35
configuration register

0x4002 4784

IRQEN

R/W

0x0000 0000

Interrupt-enabling
register

Section 10.9.1.36

0x4002 4788

IRQCLR

0x0000 0000

Interrupt-clear
register

Section 10.9.1.37

0x4002 478C

IRQSET

0x0000 0000

Interrupt-set register

Section 10.9.1.38
Section 10.9.1.39

0x4002 4790

IRQSTAT

0x0000 0000

Interrupt-status
register

0x4002 47F8

HWOPT

0x0201 0093

Type and options
register

0x4002 47FC

HWVER

0x9110 8778

Version register

Section 10.9.1.40

Unspecified addresses are reserved and must not be written and ignored on a read.

10.5.3 DMA Controller
Figure 10-1 shows the DMA controller (DMAC) and its integration in the AES module.
Figure 10-1. DMA Controller and Integration
Interrupts

ext DMA

DMA length

DMA dest addr

DMA src addr

Port error

external DMA port

conf./
status

Channel 0
(Inbound)

ext DMA
params

DMA active
transfer

Arbiter

req/
ack status
Control registers
conf./
status

Channel 1
(Outbound)

TCM

TCM slave

DMA req/ack

EIP-101m
Bus master adapter
(AHB)

Port control

EIP-101
Bus slave adapter
(AHB)

params

ack

Block/channel
done

Peripheral req/
ack/burst_size

Block/channel
done

Peripheral req/
ack/burst_size

EIP-209 DMA Controller

Master control

Crypto engine module
Crypto engine

916

Cryptography

Key store

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Module Description

www.ti.com

The DMAC of the AES module controls the data transfer requests to the AHB master adapter, which
transfers data to and from the AES engines and key store area.
The required parameters for proper functioning of the AHB master interface port are defined in the
DMABUSCFG register. The default configuration of this register configures fixed-length transfers and a
maximum burst size of 4 bytes. As a result, only nonsequential single transfers are performed on the AHB
bus.
The DMASTAT and DMAPORTERR registers provide the actual state of each DMA channel and individual
AHB port errors. A port error aborts operations on all serviced channels and prevents further transfers
using that port, until the error is cleared by writing to the DMASWRESET register.
If the address and lengths are 32-bit aligned, the master does only NONSEQ-type and SINGLE-type
transfers with a size of 4 bytes.
The DMAC splits channel DMA operation into small DMA transfers. The size of small DMA transfers is
determined by the target internal module, and equals the block size of the cryptographic operation.
The DMAC has the following features:
• Two channels (one inbound and one outbound) that can be enabled at the same time
• A maximum size of the DMA operation, controlled by a 16-bit long register
• An arbiter to schedule channel accesses to the external AHB port
• Functionality to capture external bus errors
The DMAC consists of two DMA channels with programmable priority: one is programmable to move input
data and keys from the external memory to the AES module, and another is programmable to move result
data from the AES module to the external memory. Access to the channels of the AHB master port is
handled by the arbiter module.
Channel control registers are used for channel enabling and priority selection. When a channel is
disabled, it becomes inactive only when all ongoing requests are finished.
NOTE: All the channel control registers (DMACHxCTL, DMACHxEXTADDR, and DMACHxLEN)
must be programmed by the host to start a new DMA operation.

The DMAC transfers data between a source address and destination address. Starting at a nonwordaligned boundary, byte transfers are generated until a word boundary is reached. From then onward, word
transfers are generated as long as data is available. If the transfer does not finish on word-aligned
address, the remaining transfers are again byte transfers.
NOTE: No halfword transfers are generated.

When the AHB_MST1_INCR_EN bit is set to 1, defined-length bursts and single transfers are generated
by default. The maximum size depends on the programmed burst size.
The DMAC registers are mapped to the external register map. To start the operation, the host must
program the mode of the DMAC and parameters of the operation. These parameters involve direction
(read, write, or read-and-write), length (1 to 65535 bytes), external source address (for reading), and
external destination address (for writing). For details of the registers, refer to Section 10.9.1.
NOTE: The internal destination is programmed using a dedicated algorithm selection register in
master control module. The burst size is provided to the DMAC based on the setting of that
register.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography

917

Module Description

www.ti.com

10.5.3.1 Internal Operation
The DMAC operates with the AHB master adapter that has two ports. One port is an external AHB port
used to perform read and write operations to the external AHB subsystem. This port can address the
complete 32-bit address range. The second port is an internal TCM port (master TCM) used to perform
read and write operations to the internal modules of the crypto core AES engine and key store.
Assignment of the internal modules for DMA operation must be selected in the master control module (see
to Section 10.5.4.1.1); therefore, an internal address is not needed in the DMAC.
The data path from the TCM port of the AHB master module to the internal modules is located outside of
the DMAC. The DMAC only observes the number of transferred words to determine when the requested
DMA operation is finished for the corresponding channel.
The key store is a 32-bit block of memory with a depth of 32 words, surrounded by control logic. When the
AES module is configured to write keys to this key-store module through DMA, the key store internally
manages access to the key store RAM based on its register settings (including generation of the key store
RAM addresses). The AES module supports only DMA write operations to the key store.
The AES engine has a 32-bit write interface for input data to be encrypted or decrypted, and a 32-bit read
interface for result data and tag. The write interface of the AES module collects 32-bit data into a 128-bit
input block (AES block size). When a full block is received, the AES calculation for the received block is
started. When receiving the last word of the last block, the DMAC and master controller generate a "data
done" signal to the crypto engine. The mode, message length, and optional parameters are programmed
using the target interface.
On the TCM side, the key store module immediately accepts all data without delay cycles, while the crypto
modules operate on a data block boundary. On the TCM side, the key-store module immediately accepts
all data without delay cycles, while the crypto module operates on a data block boundary (the processing
of which takes a number of clock cycles). Special handshake signals are used between the DMAC and
crypto modules:
• A data input request is sent to the DMA inbound channel (channel 0) when the crypto module can
accept the next data block.
• A data output request is sent to the DMA output channel (channel 1) when the crypto module has the
next block of data or tag available, after processing or hash module has a digest available.
• Both channels send an acknowledge when the DMA operation starts, channel transfer completes,
when a block has been transmitted and the channel transfer completes, or when all data is transmitted.
10.5.3.2 Supported DMA Operations
With each data request from the crypto engine, the DMAC requests a transfer from the AHB master. The
transfer size is at most the block size of the corresponding algorithm. This block size depends on the
selected algorithm in the master control module.
Table 10-2 provides a summary of the supported DMAC operations. The module refers to the selected
module in the master control module. TAG enable indicates whether the TAG bit is set in the master
control configuration register.
Table 10-2. Supported DMAC Operations
Module
Key store
Crypto

Incoming Data Stream (for Channel 0)
Source

Destination

(2)

918

Source

Destination

External memory location

Key store RAM

–

RAM (Authentication data only)

AES

See (1)

External memory location

AES

External memory location

AES (TAG enabled)

External memory location

See
(1)

Outcoming Data Stream (for Channel 1)

(2)

See

(2)

TAG is transferred through the slave interface or transferred with a separate DMA.
Data is transferred through another DMA, that has been executed before.

Cryptography

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Module Description

www.ti.com

10.5.4 Master Control and Select
The master control module synchronizes the DMA operations and the cryptographic module handshake
signals. In this module, the crypto algorithm is selected and the DMA burst sizes are defined. When the
complete encryption operation completes, an interrupt is asserted.
NOTE: For authentication operations, the interrupt is asserted only if the authentication result is
available.

The AES module also provides an interrupt to indicate that the input DMA transfer is complete. This
interrupt is primarily used to determine the end of an AAD data DMA transfer (AES-CCM), which is
typically set up as separate input data transfer.
10.5.4.1 Algorithm Select
This algorithm-selection register configures the internal destination of the DMAC.
10.5.4.1.1 Algorithm Select
Table 10-3 summarizes the allowed bit combinations of the ALGSEL register.
Table 10-3. Valid Combinations for ALGSEL Flags
Flags

Operation

KEY STORE

AES

TAG

Key store is loaded through the DMA.

AES data is loaded through the DMA and
encrypted and decrypted data are read through
the DMA (encryption and decryption) or AES
data is loaded through the DMA and result tag
is read through the slave interface
(authentication-only operations).

AES data is loaded through the DMA, result tag
is read through the DMA (authentication-only
operations).

10.5.4.2 Master PROT Enable
10.5.4.2.1 Master PROT-Privileged Access-Enable
The DMAPORTCTL register selects the AHB transfer protection control for DMA transfers, using the key
store as destination.
10.5.4.3 Software Reset
Refer to Section 10.7.4.1 for more details on the soft reset procedure.
To perform a software reset of the AES module, write 1 to the RESET bit in the SWRESET register. When
the software reset completes, the RESET bit in the SWRESET register is automatically reset. Software
must ensure that the software reset completes before starting any operations.
In the DMA control module, software reset is used to reset the DMAC to stop all transfers and clear the
DMAPORTERR register. After the software reset is performed, all channels are disabled and no new
requests are performed by the channels. The DMAC waits for the existing (active) requests to finish, then
sets the DMAC status registers.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography

919

Module Description

www.ti.com

10.5.5 AES Engine
The composition of the AES core is the following:
• The main data path operates on the input block, performing the required substitution, shift, and mix
operations.
• The key scheduler generates the round keys. A new subkey is generated and XORed with the data
each round.
The AES key scheduler generates the round keys. During each round, a new subkey is generated from
the input key to be XORed with the data. Round keys are generated on-the-fly and parallel to data
processing to minimize register requirements. For encryption operations, the key sequencer transfers the
initial key data to the AES core. For decryption operations, the key scheduler must provide the final
subkey to the AES core so it can generate the subkeys in reverse order.
The AES core operates on the input block and performs the required substitution, shift, and mix
operations. For each round, the encryption core receives the proper round key from the AES key
scheduler. A fundamental component of the AES algorithm is the S-box. The S-box provides a unique
8-bit output for each 8-bit input.
The architecture of the AES decryption core is generally the same as the architecture of the encryption
core. One difference is that the generation of round keys for decryption requires an initial conversion of the
input key (always supplied by the host in the form of an encryption key) to the corresponding decryption
key. This conversion is done by performing a dummy encryption operation and storing the final round key
as a decryption key. The key scheduler is then reversed to generate the round keys for the decryption
operation. Consequently, for each sequence of decryption operations under the same key, a single
throughput reduction equal to the time to encrypt a single block occurs. When a decryption key is
generated, subsequent decryption operations with the same key use this generated decryption key
directly.

920

Cryptography

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Module Description

www.ti.com

10.5.5.1 Second Key Registers (Internal, But Clearable)
The following registers shown in Table 10-4 and Table 10-5 are not accessible through the host for
reading and writing. These registers are used to store internally calculated key information and
intermediate results. However, when the host performs a write to any of the respective AESKEY2__0 to
AESKEY2__3 or AESKEY3__0 to AESKEY3__3 addresses, respectively, the whole 128-bit AESKEY2__0
to AESKEY2__3 or AESKEY3__0 to AESKEY3__3 register is cleared to zeroes.
The intermediate authentication result for CCM is stored in the AESKEY3__0 to AESKEY3__3 register.
Table 10-4. AES_KEY
AESKEY2__0 to AESKEY2__3 (Write Only), 32-bit Address Offset: 0x500 to 0x50C in 0x4-byte increments
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
AESKEY2__0 to AESKEY2__3[31:0]
AESKEY2__0 to AESKEY2__3[63:32]
AESKEY2__0 to AESKEY2__3[95:64]
AESKEY2__0 to AESKEY2__3[127:96]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 10-5. AES_KEY
AESKEY3__0 to AESKEY3__3 (Write Only), 32-bit Address Offset: 0x510 to 0x51C in 0x4-byte increments
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
AESKEY3__0 to AESKEY3__3[31:0] / AESKEY2__0 to AESKEY2__3[159:128]
AESKEY3__0 to AESKEY3__3[63:32] / AESKEY2__0 to AESKEY2__3[191:160]
AESKEY3__0 to AESKEY3__3[95:64] / AESKEY2__0 to AESKEY2__3[223:192]
AESKEY3__0 to AESKEY3__3[127:96] / AESKEY2__0 to AESKEY2__3[255:224]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

For CCM:
Bit

Field Name

Function

255-0

–

This register is used to store intermediate
values.

For CBC-MAC:
Bit

Field Name

Function

255-0

Zeroes

This register must remain zero.

Reusing the AES_KEYn registers is allowed for sequential operations; however for CBC-MAC,
intermediate values must be cleared when programming the respective mode and length parameters.
If a CBC-MAC operation is started without loading a new key (through the key store), and the previous
operation was not a CBC-MAC operation, both AESKEY2__0 to AESKEY2__3 and
AESKEY3__0 to AESKEY3__3 register locations must be written before starting the CBC-MAC operation,
which is required to clear these two key registers.
10.5.5.2 AES Initialization Vector (IV) Registers
Table 10-6 shows the AES Initialization Vector registers that are used to provide and read the IV from the
AES engine.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography

921

Module Description

www.ti.com

Table 10-6. AES Initialization Vector Registers
AES_IV_0, (Read/Write), 32-bit Address Offset: 0x540
AES_IV_1, (Read/Write), 32-bit Address Offset: 0x544
AES_IV_2, (Read/Write), 32-bit Address Offset: 0x548
AES_IV_3, (Read/Write), 32-bit Address Offset: 0x54C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

AES_IV[31:0] AES_IV[63:32] AES_IV[95:64] AES_IV[127:96]
0

Initialization Vector, used for regular non-ECB modes (CBC/CTR):
Bit

Name
AES_IV

127-0

Description
For regular AES operations (CBC and CTR), these registers must be written with a
new 128-bit IV.
After an operation, these registers contain the latest 128-bit result IV, generated by the
crypto core.
If CTR mode is selected, this value is incremented with 0x1 (after first use) when a
new data block is submitted to the engine.

Initialization Vector, used for CCM:
Bit

Name
A0

127-0

Description
For CCM, this field must be written with value A0. This value is the concatenation of:
A0-flags (5 bits of zero and 3 bits L), nonce and counter value.
L must be a copy from the L value of the AESCTL register. This L indicates the width
of the nonce and counter.
The loaded counter must be initialized to zero.
The total width of A0 is 128 bits.

Initialization Vector, used for CBC-MAC:
Bit

Name
Zeroes

127-0

Description
For CBC-MAC this register must be written with zeroes at the start of each operation.
After an operation, these registers contain the 128-bit TAG output, generated by the
crypto core.

10.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
The I/O buffer and mode-control register (AESCTL) specifies the mode of operation for the AES engine.
NOTE: Internal operation of the AES module can be interrupted by setting all mode bits to 0 and
writing zeroes to the length registers (AESDATALEN0, AESDATALEN1, and
AESAUTHLEN).

The length registers write the length values to the AES module. While processing, the length values
decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For
basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams must be
processed with the same key. Writing a 0 length results in continued data requests until a new context is
written. For the other modes (CBC-MAC and CCM), no new data requests are done if the length
decrements to or equals zero.
TI recommends writing a new length per packet. If the length registers decrement to 0, no new data is
processed until a new context or length value is written.
When writing a new mode without writing the length registers, the values of the length register from the
previous context are reused.

922

Cryptography

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Module Description

www.ti.com

10.5.5.4 Data Input and Output Registers
The AESDATAINn and AESDATAOUTn data registers are typically accessed through DMA and not with
host writes and reads. However, for debugging purposes, the Data Input and Output Registers can be
accessed through host write and read operations. The registers buffer the input and output data blocks to
and from the crypto core.
NOTE: The data input buffer AESDATAINn and data output buffer AESDATAOUTn are mapped to
the same address locations.

Writes (both DMA and host) to these addresses load the input buffer, while reads pull from the output
buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer
is read. The data input buffer must be written before starting an operation. The data output buffer contains
valid data when an operation completes. Therefore, any 128-bit data block can be split over multiple 32-bit
word transfers; these transfers can be mixed with other host transfers over the external interface.
For normal operations, this register is not used, because data input and output is transferred from and to
the AES core through DMA. For a host write operation, these registers must be written with the 128-bit
input block for the next AES operation. Writing at a word-aligned offset within this address range stores
the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block)
data-input buffer. This buffer is used for the next AES operation. If the last data block is not completely
filled with valid data, it can write only the words with valid data. Finally, the AES operation is triggered by
writing the AESCTL.INPUT_RDY register bit.
For a host read operation, this register contains the 128-bit output block from the latest AES operation.
Reading from a word-aligned offset within this address range reads one word (4 bytes) of data out of the
4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (four words, one full block)
must be read before the core moves the next block to the data output buffer. To empty the data output
buffer, the AESCTL.OUTPUT_RDY bit must be written.
For the modes with authentication (CBC-MAC and CCM), the invalid (message) bytes/words can be
written with any data.
NOTE: AES typically operates on a 128-bit block with multiple input data. The CTR and CCM modes
form an exception. The last block of a CTR-mode message may contain less than 128 bits
(refer to [NIST 800-38A]): 0 < n < = 128 bits. For CCM, the last block of both AAD and
message data may contain less than 128 bits (refer to [NIST 800-38D]). The AES module
automatically pads or masks misaligned ending data blocks with zeroes for CCM and
CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. The
AAD or authentication-only data is not copied to the output buffer but is only used for
authentication.

Table 10-7. Input/Output Block Format Per Operating Mode
Operation

Data Input Buffer

Data Output Buffer

ECB/CBC encrypt

128-bit plaintext block

128-bit ciphertext block

ECB/CBC decrypt

128-bit ciphertext block

128-bit plaintext block

CTR encrypt

n-bit plaintext block

n-bit ciphertext block

CTR decrypt

n-bit ciphertext block

n-bit plaintext block

CCM AAD data

n-bit plaintext block

no output data

CCM encrypt data

n-bit plaintext block

n-bit ciphertext block

CCM decrypt data

n-bit ciphertext block

n-bit plaintext block

CBC-MAC data

n-bit plaintext block

no output data

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

923

Module Description

www.ti.com

10.5.5.5 TAG Registers
Table 10-8 shows the TAG registers that buffer the TAG from the AES module and can be accessed
through DMA or directly with host reads. The TAG registers are shared with the intermediate
authentication result registers, but cannot be read until the processing is finished. While processing, a
read from these registers returns zeroes. If an operation does not return a TAG, reading from these
registers returns an initialization vector (IV). If an operation returns a TAG plus an IV and both must be
read by the host, the host must first read the TAG followed by the IV. Reading these in reverse order
returns the IV twice.
For a host-read operation, these registers contain the last 128-bit TAG output of the AES core. The TAG
is available until the next context is written. This register only contains valid data if the TAG is available,
and when the SAVED_CONTEXT_RDY bit in the AESCTL register is set. During processing or for
operations and modes that do not return a TAG, reads from this register return data from the IV register.
Table 10-8. AES Tag Output Register
AESTAGOUT__0 to AESTAGOUT__3, (Read Only), 32-bit Address Offset: 0x570 to 0x57C in 0x4 byte increments
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

AES_TAG[31:0] AES_TAG[63:32] AES_TAG[95:64] AES_TAG[127:96]
0

For CCM, CBC-MAC:
Bit

Field Name

31-0

TAG

Description
This register contains the authentication TAG for the
combined and authentication-only modes.

10.5.6 Key Area Registers
The local-key storage module is directly connected to 1KB memory. The module can store up to eight
AES keys and has eight 128-bit entries. The key size is programmed in the key store module. The key
material in the key store is not accessible through read operations through the AHB master and slave
interfaces.
Keys can only be written to the key store through DMA. Once a DMA operation for a key read is started,
all received data is written to the key store module. Keys that are stored in the key store memory can only
be transferred to the AES key registers and are not accessible for any other purpose.
10.5.6.1 Key Write Area Register
The Key Write Area register defines where the keys must be written in the key store RAM. After writing the
Key Write Area register, the key store module is ready to receive the keys using a DMA operation. If the
key data transfer triggered an error in the key store, the error is available in the interrupt status register,
IRQSTAT, after the DMA is finished. The key store write-error, KEY_ST_WR_ERR, is asserted when the
programmed or selected area is not completely written. This error is also asserted when the DMA
operation writes to RAM areas that are not selected.
10.5.6.2 Key Written Area Register
The Key Written Area register shows which areas of the key store RAM contain valid written keys.
When a new key must be written to the key store on a location that is already occupied by a valid key, this
key area must be cleared first. Clear the key area by writing this register before the new key is written to
the key store memory.
Trying to write to a key area that already contains a valid key is not allowed and results in an error.

924

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Performance

www.ti.com

10.5.6.3 Key Size Register
The Key Size register defines the size of the keys that are written with DMA. The Key Size register must
be configured before writing to the KEYWRITEAREA register.
10.5.6.4 Key Read Area Register
The Key Read Area register selects the key store RAM area from where the key must be read that is used
for an AES operation. The operation starts directly after writing this register. When the operation is
finished, the status of the key store read operation is available in the IRQSTAT interrupt status register.
Key store read error asserts when a RAM area is selected that does not contain a valid written key.

10.6 Performance
10.6.1 Introduction
The processing steps of the AES module are the basis for the performance calculations. The following
three major steps are identified for crypto operations using DMA:
1. Initialization (setup and initialization of the engines, DMA, and so forth)
2. Data processing for the complete message
3. Finalization (reading out the result, status checking)
The orange sections (full processing) of Figure 10-2, are covered by Step 1 and Step 3. Step 1 and Step 3
are under control of the host CPU, and therefore dependent on the performance of the host. Step 2 is
covered by the green section (data processing), and is fully handled by the hardware, which is not
dependent on the performance of the host CPU.

Set-up and initialization

Full processing

1st block

2nd block

...

last block

Result is available

All data processed

Start of the
operation

DMA- and key
material set up

First block processed

Figure 10-2. Symmetric Crypto Processing Steps

Finalization

Data processing

The full processing part is required once per processing command, and precedes the processing of the
first data block. The data processing blocks depend on the amount of data to be processed by the
command. The finalization is required when the operation produces a result digest or TAG.
The number of required blocks is determined by the block size requirements of the algorithms selected by
the command. The AES block size is 128 bits.
For longer data streams, the data processing time approaches the theoretical maximum throughput. For
operations that use the slave interface as alternative for the DMA, the performance depends on the
performance of the host CPU.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

925

Performance

www.ti.com

10.6.2 Performance
Table 10-9 shows the performance of the AES module running at 200 MHz for DMA-based cryptographic
operations.
Table 10-9. Performance Table for DMA-Based Operations
Performance in Mbps
Crypto Mode

Raw Engine
Performance

1-Block Packet
Performance (1)

20-Block
Performance (1)

100-Block
Performance (1)

AES-128 (1 block = 128 bits)

(1)

AES-128-ECB

492

111

420

476

AES-128-CBC

483

104

408

466

AES-128-CTR

492

104

415

474

The performance assumes full programming of the engine, loading keys, and setting up the DMA engine through the DMA slave.
If the context is reused (mode or keys), the performance is increased. The maximum number of cycles overhead per packet is
from 100 to 150 for the various modes and algorithms.

The engine performance depends heavily on the number of blocks processed per operation. Processing a
single block results in the minimum engine performance; in this case, the configuration overhead is the
most significant (assuming the engine is fully reconfigured for each operation). Therefore, processing
multiple blocks per operation results in a significantly higher performance.

10.7 Programming Guidelines
This section describes the low-level programming sequences for configuring and using the AES module
for the supported-use cases.

10.7.1 One-time Initialization After a Reset
The purpose of the initialization is to set the AES module into the initial mode common to all used
operations. Perform the following initialization steps after a hardware reset:
1. Read out and check that the AES module version and configuration matches the expected hardware
configuration.
2. Program the DMAC run-time parameters in the DMABUSCFG register with the desired values common
for all DMA operations.
3. Initialize the desired interrupt type (level), and enable the interrupt output signal RESULT_AVAIL in the
master control module.

926

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Programming Guidelines

www.ti.com

10.7.2 DMAC and Master Control
This section contains general guidelines on how to program the DMAC to perform a specific operation.
10.7.2.1 Regular Use
The following registers must be programmed to configure the DMA channels:
• Clear any outstanding interrupts and error flags if possible (see Section 10.9.1.37).
• The master control module algorithm-selection register must be programmed to allow a DMA operation
on the required internal module, which enables the DMA/AHB Master clock, and keeps it enabled until
the clock is disabled by the host (see Section 10.9.1.32).
• Channel control registers with channel bits enabled (see Section 10.9.1.1 and Section 10.9.1.6).
• Channel external address registers (see Section 10.9.1.2 and Section 10.9.1.7).
• Channel DMA length registers. Writing this register starts the DMA operation on the corresponding
channel (see Section 10.9.1.3 and Section 10.9.1.8).
• Completion of the operation is indicated by the result available interrupt output or the corresponding
status register. Clear the interrupt after handling the interrupt (see Section 10.9.1.39 and
Section 10.9.1.37).
• Master control module algorithm selection register must be cleared to zero to switch off the DMA/AHB
Master clock (see Section 10.9.1.32).
NOTE: The IRQSTAT register must be checked for possible errors if bus errors can occur in the
system, which is typically valid in a debugging phase, or in systems where bus errors can
occur during a DMA operation.

10.7.2.2 Interrupting DMA Transfers
If the host wants to stop a DMA transfer to abort the operation, the host can disable a channel using the
DMACHnCTL registers. Once the EN bit of this register is set to 0, no new DMA transfer is requested by
this channel and the current active transfer is finished. Alternatively, all active channels can be stopped by
activating the DMAC soft reset with the DMASWRESET register.
NOTE: When stopping the DMAC, the host must stop all active channels.

The state of the DMAC channel must be checked using the DMASTAT register. When the CHx_ACTIVE
bit of this register for the disabled channel is set to 0, the DMAC channel stops.
To stop the DMAC in combination with the AES engine, the AES engine must be set in idle mode first,
which is done by writing zeroes to the length registers, followed by disabling all modes in the AESCTL
register.
Stopping the DMAC channels might leave the master control module in an unfinished state, due to
pending events from the engines that will never occur. Therefore, to correctly recover the engine, the
master control soft reset must be issued by the SWRESET register after all active DMAC channels are
stopped.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

927

Programming Guidelines

www.ti.com

10.7.2.3 Interrupts, Hardware, and Software Synchronization
This section describes the important relation of the RESULT_AVAIL interrupt activation and the data
writing completion of the DMAC inside the crypto core.
The RESULT_AVAIL interrupt is activated when the AHB master finishes the data write transfer from the
crypto core and the internal operation is completed. However, that does not ensure that data has been
written to the external memory, due to latency from the AHB master to the destination (typically a
memory). This latency might occur in the AHB bus subsystem outside of the crypto core, as this system
possibly contains bridges.
NOTE: If this latency can occur, the host must ensure (using a time-out or other synchronization
mechanisms) that external memory reads are only performed after all memory write
operations are finished.

10.7.3 Encryption and Decryption
The crypto engine (AES) transfers data over the following interfaces:
• AES accepts input data from two sources: AHB slave interface and DMA. Within one operation, it is
possible to combine data from these two sources: write data from the slave interface, and write data
from the DMA to complete the operation.
• Input IV and length must be supplied using the AHB slave interface. The output IV can be read using
the slave interface only.
• Result data must be read using the same interface as the input data: either using the slave interface or
DMA.
• The result tag for operations with authentication can be read using the slave interface or DMA.

928

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Programming Guidelines

www.ti.com

10.7.3.1 Key Store
Before any encryption or decryption operation starts, the key store module must have at least one key
loaded and available for crypto operations. Keys can only be loaded from external memory using a DMA
operation. DMAC channel 0 (inbound) is used for this purpose.
10.7.3.1.1 Load Keys From External Memory
The following software example in pseudocode describes the actions that are typically executed by the
host software to load one or more keys into the key store module.
// configure master control module
write ALGSEL 0x0000_0001 // enable DMA path to the key store module
write IRQCLR 0x0000_0001 // clear any outstanding events
// configure key store module (area, size)
write KEYSIZE 0x0000_0001 // 128-bit key size
write KEYWRITEAREA 0x0000_0001 // enable keys to write (e.g. Key 0)
// configure DMAC
write DMACH0CTL 0x0000_00001 // enable DMA channel 0
write DMACH0EXTADDR // base address of the key in ext.
memory
write DMACH0LEN // total key length in bytes (e.g. 16 for 1 x 128-bit
// key)
// wait for completion
wait IRQSTAT[0]==’1’ // wait for operation completed
check IRQSTAT[31:30] == ‘00’ // check for absence of errors in DMA and key
store
write IRQCLR 0x0000_0001 // acknowledge the interrupt
write ALGSEL 0x0000_0000 // disable master control/DMA clock
// check status
check KEYWRITTENAREA 0x0000_00001 // check that Key 0 was written
// end of algorithm
10.7.3.2 Basic AES Modes
10.7.3.2.1 AES-ECB
For AES-ECB operations, the following configuration parameters are required:
• Key from the key store module
• Control register settings (mode, direction, key size)
• Length of the data
The length field can have any value. If a data stream is finished and the next data stream uses the same
key and control, only the length field has to be written with a new value. The length field may also be 0, for
continued processing.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

929

Programming Guidelines

www.ti.com

10.7.3.2.2 AES-CBC
For AES-CBC operations, the following configuration parameters are required:
• Key from the key store module
• IV from the slave interface
• Control register settings (mode, direction, key size)
• Length of the data
The length field can have any value. If a data stream is finished and the next data stream uses the same
key and control, it is allowed to write only the IV and length field with a new value. The length field may
also be 0, for continued processing.
If the result IV must be read by the host, the SAVE_CONTEXT bit must be set to 1 after processing the
programmed number of bytes.
10.7.3.2.3 AES-CTR
For AES-CTR operations, the following configuration parameters are required:
• Key from the key store module
• IV from the slave interface, including initial counter value (usually 0x0000 0001)
• Control register settings (mode, direction, key size)
• Length of the data (may be nonblock size aligned)
The length field can have any value. If a data stream is finished and the next data stream uses the same
key and control, only the IV and length field are allowed to written with a new value. The length field can
be 0, resulting in continued processing.
If the result IV must be read by the host, the save_context bit must be set to 1 after processing the
programmed number of bytes.

930

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Programming Guidelines

www.ti.com

10.7.3.2.4 Programming Sequence With DMA Data
The following software example in pseudocode describes the actions that are typically executed by the
host software to encrypt (using a basic AES mode) a message, stored in external memory, and place an
encrypted result into a preallocated area in the external memory.
// configure the master control module
write ALGSEL 0x0000_0002 // enable the DMA path to the AES engine
write IRQCLR 0x0000_0001 // clear any outstanding events
// configure the key store to provide pre-loaded AES key
write KEYREADAREA 0x0000_0000 // load the key from ram area 0 (NOTE: The key
// must be pre-loaded to this area)
wait KEYREADAREA[31]==’0’ // wait until the key is loaded to the AES module
check IRQSTAT[29] = ‘0’ // check that the key is loaded without errors
// Write the IV for non-ECB modes
// The IV must be written with the same conventions as the data (refer to
6.4.1 in IP docs)
if ((not ECB mode) and (not IV reuse)) then:
// write the initialization vector when a new IV is required
write AESIV_0
...
write AESIV_3
endif
// configure AES engine
write AESCTL = 0b0010_0000_0000_0000_
0000_0000_0010_1100 // program AES-CBC-128 encryption and save IV
write AESDATALEN0 // write length of the message (lo)
write AESDATALEN1 // write length of the message (hi)
write DMACH0CTL 0x0000_00001 // enable DMA channel 0// configure DMAC
write DMACH0EXTADDR // base address of the input data in ext. memory
write DMACH0LEN // input data length in bytes, equal to the message
// length (may be non-block size aligned)
write DMACH1CTL 0x0000_00001 // enable DMA channel 1
write DMACH1EXTADDR // base address of the output data buffer
write DMACH1LEN // output data length in bytes, equal to the result
// data length (may be non-block size aligned)
// wait for completion
wait IRQSTAT[0]==’1’ // wait for operation completed
check IRQSTAT[31] == ‘0’ // check for absence of errors
write AESALGSEL 0x0000_0000 // disable master control/DMA clock
if (not ECB mode) then: // only if the IV needs to be re-used/read
wait AESCTL[30]==’1’ // wait for SAVED_CONTEXT_RDY bit [30]
read AESIV_0
...
read AESIV_3 // this read clears the SAVED_CONTEXT_RDY flag
endif
// end of algorithm
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

931

Programming Guidelines

www.ti.com

10.7.3.3 CBC-MAC
For CBC-MAC operations, the following configuration parameters are required:
• Key from the key store module
• IV must be written with zeroes
• Control register settings (mode, direction, key size)
• Length of the authenticated data (may be nonblock size aligned)
The input data can end misaligned for CBC-MAC operations. If this is the case, the crypto core internally
pads the last input data block.
The length field can have any value. If a data stream is finished and the next data stream uses the same
key and control, writing only a part of the next context is not allowed. A new data stream must always
write the complete context. The length field must never be written with zeroes.

932

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Programming Guidelines

www.ti.com

10.7.3.3.1 Programming Sequence
The following software example in pseudocode describes the actions that are typically executed by the
host software to authenticate a message, stored in external memory, with AES-CBC-MAC mode. The
result TAG is read using the slave interface.
The following sequence processes a packet of at least 1 input data byte.
// configure the master control module
write ALGSEL 0x0000_0002 // enable the DMA path to the AES engine
write IRQCLR 0x0000_0001 // clear any outstanding events
// configure the key store to provide a pre-loaded AES key
write KEYREADAREA 0x0000_0000 // load the key from ram area 0 (NOTE: The key
// must be pre-loaded to this area)
wait KEYREADAREA[31]==’0’ // wait until the key is loaded to the AES module
check IRQSTAT[29] = ‘0’// check that the key is loaded without errors
// write the initialization vector
write AESIV_0
...
write AESIV_3
// configure the AES engine
write AESCTL = 0b0010_0000_0000_0000_
1000_0000_0100_1100 // program AES-CBC-MAC-128 authentication
write AESDATALEN0 // write length of the crypto block (lo)
write AESDATALEN1 // write the length of the crypto block (hi)
// (may be non-block size aligned)
/write DMACH0CTL 0x0000_00001 // enable DMA channel 0/ configure DMAC
write DMACH0EXTADDR // base address of the input data in ext. memory
write DMACH0LEN // input data length in bytes, equal to the message
// length len({aad data, pad, crypto_data, pad})
// (may be non-block size aligned)
// wait for completion
wait IRQSTAT[0]==’1’ // wait for operation completed
check IRQSTAT[31]==‘0’ // check for the absence of errors
write ALGSEL 0x0000_0000 // disable master control/DMA clock
// read tag
wait AESCTL[30]==’1’ // wait for the SAVED_CONTEXT_RDY bit [30]
read AESTAGOUT__0 AESTAGOUT__3 // this read clears the SAVED_CONTEXT_RDY flag
// end of algorithm

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

933

Programming Guidelines

www.ti.com

10.7.3.4 AES-CCM
For AES-CCM operations, the following configuration parameters are required:
• Key from the key store module
• The IV must be written with the flags for the cryptographic operation and the NONCE bytes, for both
authentication and encryption (see Section 10.5.5.2)
• Control register settings (mode, direction, key size)
• Length of the crypto data (may be nonblock size aligned)
• Length of the AAD data; must be less than 216 – 28 bytes (may be nonblock size-aligned)
CCM-L must be 001, 011, or 111, representing a crypto data length field of 2, 4, or 8 bytes, respectively.
CCM-M can be set to any value and has no effect on the processing. The host must select the valid TAG
bytes from the 128-bit TAG.
The AAD and cryptographic data may end misaligned. In this case, the crypto core pads both data types
to a 128-bit boundary with zeroes. Padding is done as follows: the AAD and crypto data padding satisfy
the bit string, 0n, with 0 n 127, such that the input data block length including padding is 128-bit
aligned. The AAD data must be transferred to the AES engine with a separate DMA operation (it may not
be combined with the payload data) or using slave transfers.
The context length field can have any value. If a data stream is done and the next data stream uses the
same key and control, only the IV and length fields can be written with a new value. The user cannot write
both length fields with zeroes.
The result TAG is typically read using the slave interface, but can also be written to an external memory
location using a separate DMA operation.
10.7.3.4.1 Programming Sequence
The following software example in pseudocode describes the actions that are typically executed by the
host software to encrypt and authenticate a message (AAD and payload data), stored in external memory,
with AES-CCM mode. The encrypted result is placed into a pre-allocated area in external memory. The
result TAG is read using the slave interface.
The following sequence processes a packet of at least one byte of AAD data and at least 1 crypto data
byte.
// configure the master control module
write ALGSEL 0x0000_0002 // enable the DMA path to the AES engine
write IRQCLR 0x0000_0001 // clear any outstanding events
// configure the key store to provide pre-loaded AES key
write KEYREADAREA 0x0000_0000 // load the key from ram area 0 (NOTE: The key
// must be pre-loaded to this area)
wait KEYREADAREA[31]==’0’ // wait until the key is loaded to the AES module
check IRQSTAT[29] = ‘0’// check that the key is loaded without errors
// write the initialization vector
write AESIV_0
...
write AESIV_3
// configure the AES engine
write AESCTL = 0b0010_0000_0101_1100_
0000_0000_0100_1100 // program AES-CCM-128 encryption (M=1, L=3)
write AESDATALEN0// write the length of the crypto block (lo)
write AESDATALEN1// write the length of the crypto block (hi)
// (may be non-block size aligned)
934

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Programming Guidelines

www.ti.com

write AESAUTHLEN // write the length of the AAD data block
// (may be non-block size aligned)
// configure DMAC to fetch the AAD data
write DMACH0CTL 0x0000_00001 // enable DMA channel 0
write DMACH0EXTADDR // base address of the AAD input data in ext.
memory
write DMACH0LEN // AAD data length in bytes, equal to the AAD
// length len({aad data})
// (may be non-block size aligned)
// wait for completion of the AAD data transfer
wait IRQSTAT[1]==’1’// wait for DMA_IN_DONE
check IRQSTAT[31]==‘0’// check for the absence of errors
// configure DMAC
write DMACH0CTL 0x0000_00001 // enable DMA channel 0
write DMACH0EXTADDR // base address of the payload data in ext.
memory
write DMACH0LEN // payload data length in bytes, equal to the message
// length len({crypto_data})
write DMACH1CTL 0x0000_00001 // enable DMA channel 1
write DMACH1EXTADDR // base address of the output data buffer
write DMACH1LEN // output data length in bytes, equal to the result
// data length len({crypto data})
// wait for completion
wait IRQSTAT[0]==’1’// wait for operation completed
check IRQSTAT[31]==‘0’// check for the absence of errors
write ALGSEL 0x0000_0000 // disable the master control/DMA clock
// read tag
wait AESCTL[30]==’1‘ // wait for the SAVED_CONTEXT_RDY bit [30]
read AESTAGOUT__0 AESTAGOUT__3 // this read clears the ‘saved_context_ready’ flag
// end of algorithm

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

935

Programming Guidelines

www.ti.com

10.7.4 Exceptions Handling
10.7.4.1 Soft Reset
If required, the AES module can be forced to abort its current active operation and go into the IDLE state
using the soft reset.
The IDLE state means the following:
• The DMAC is not actively performing DMA operations.
• The cryptographic modules are in the IDLE state.
• The key store module does not have any keys loaded.
• The master control module is in the IDLE state.
• A soft reset must be executed in the following order:
– If DMA is used and in operation, it must be stopped.
– The master control module must be reset through the SWRESET register.
• Write the mode and length registers for the crypto core with zeroes.
The mode and length registers are:
– AESCTL
– AESDATALEN0
– AESDATALEN1
– AESAUTHLEN
10.7.4.2 External Port Errors
The AHB master interface and the DMAC inside the crypto core can detect AHB port errors received
through the AHB_ERR signal.
In this situation, the DMAC disables all channels so that no new transfers are requested, while the error is
captured in the status registers. The DMAPORTERR register contains information about the active
channel when the AHB port error occurred. The DMAC indicates the channel completion to the master
control module. The recovery procedure is as follows:
• Issue a soft reset to the DMAC using the DMASWRESET register to clear the DMAPORTERR register
and initialize the channels to their default state
• Issue a soft reset to the master control module to clear its intermediate state.
10.7.4.3 Key Store Errors
Key store error generation is implemented for debugging purposes. In normal or specified operation, the
crypto core key store writes and reads must not trigger any errors. A bus error is the only exceptional case
that can result in a key store write error.
The key store module checks that the keys are properly written to the key store RAM. When a key write
error occurs, the KEY_ST_WR_ERR flag is asserted in the IRQSTAT register. In this case, the key is not
stored. The host must check the status of the KEY_ST_WR_ERR flag and ensure that the corresponding
RAM area is not used for AES operations.
If, due to software malfunction, the host tries to use a key from a nonwritten RAM area, the key store
module generates a read error. In this case, the KEY_ST_RD_ERR flag is asserted in the IRQSTAT
register. The host must check the status of this flag and ensure that all remaining steps for the AES
operation are not performed.
NOTE: In case of a read error, the key store writes a key with all bytes set to 0 to the AES engine.

936

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Conventions and Compliances

www.ti.com

10.8 Conventions and Compliances
10.8.1 Conventions Used in This Manual
10.8.1.1 Acronyms
AES

Advanced Encryption Standard

AES-CCM

AES Counter with CBC-MAC

AHB

Advanced High-speed Bus

AMBA

Advanced Microcontroller Bus Architecture

CBC

Cipher Block Chaining

CCM

Counter with CBC-MAC

Crypto Module

CTR

Counter Mode

DMAC

DMA Controller

DPRAM

Dual port Random Access Memory

ECB

Electronic Code Book

EIP

Embedded Intellectual Property

FIFO

First In First Out

FIPS

Federal Information Processing Standard

Gigabyte

Gbit

Gigabit

Gbps

Gigabits per second

HMAC

Hashed MAC

Hardware

ICM

Integer Counter Mode

IETF

Internet Engineering Task Force

Internet Protocol or Intellectual Property

Initialization Vector

Kilobyte

kbit

Kilobit

kbps

Kilobits per second

LSB

Least Significant Bit

LSW

Least Significant Word

MAC

Message Authentication Code

Megabyte

Mbit

Megabit

Mbps

Megabits per second

Mobile Equipment

MSB

Most Significant Bit

MSW

Most Significant Word

Operating System

RFC

Request for Comments

SPRAM

Single Port Random Access Memory

SRAM

Static Random Access Memory

TCM

Tightly Coupled Memory (memory interface protocol)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

937

Conventions and Compliances

www.ti.com

10.8.1.2 Terminology
This manual makes frequent use of certain terms. These terms refer to structures that the crypto core
uses for operations.
External memory: A memory that is externally attached to the crypto core AHB master port, and only
accessible using DMAC operations
Slave interface (host processor bus): Interface of the crypto core that is used by the host processor to
read or write registers of the engine
Tag or digest: Two interchangeable terms that indicate the result of an authentication operation. Term
digest is used for regular hash operations, while tag is used for authenticated encryption operations (AESCCM).
Crypto context: A collection of parameters that define the crypto operation: mode, key, IV, and so forth
10.8.1.3 Formulas and Nomenclature
This document contains formulas and nomenclature for different data types. The presentation of syntax is
given as follows:
0x00 or 0h

Hexadecimal value

Binary value

Decimal value

Digital logic 0 or LOW

Digital logic 1 or HIGH

bit

Binary digit

8 bits

1 byte

16 bits

Half word

32 bits

Word

64 bits

Dual-word

128 bits

Quad-word

MOD

Modulo

REM

Remainder

A&B

A Logical AND B

A OR B

A Logical OR B

NOR

Logical NOR

NOT A

Logical NOT

A NOR B

A logical NOR B

A logic exclusive OR B or XOR

XNOR

logic exclusive NOR

NAND

Logical NAND

DIV

Integer division

||
[n:m]
(1)

Concatenation
Size of a register or signal in bits where n > m2

(1)

31:0 indicates a size of 32 bits with most significant bit 31 and least significant bit 0. 11:3 indicates a size of 9 bits with most
significant bit 11 and least significant bit 3.

10.8.2 Compliance
AES encryption in ECB and CBC modes complies with FIPS-197.

938

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9 Cryptography Registers
10.9.1 CRYPTO Registers
Table 10-10 lists the memory-mapped registers for the CRYPTO. All register offset addresses not listed in
Table 10-10 should be considered as reserved locations and the register contents should not be modified.
Table 10-10. CRYPTO Registers
Offset

Acronym

Section

DMACH0CTL

DMA Channel 0 Control

Section 10.9.1.1

DMACH0EXTADDR

DMA Channel 0 External Address

Section 10.9.1.2

DMACH0LEN

DMA Channel 0 Length

Section 10.9.1.3

18h

DMASTAT

DMA Controller Status

Section 10.9.1.4

1Ch

DMASWRESET

DMA Controller Software Reset

Section 10.9.1.5

20h

DMACH1CTL

DMA Channel 1 Control

Section 10.9.1.6

24h

DMACH1EXTADDR

DMA Channel 1 External Address

Section 10.9.1.7

2Ch

DMACH1LEN

DMA Channel 1 Length

Section 10.9.1.8

78h

DMABUSCFG

DMA Controller Master Configuration

Section 10.9.1.9

7Ch

DMAPORTERR

DMA Controller Port Error

Section 10.9.1.10

FCh

DMAHWVER

DMA Controller Version

Section 10.9.1.11

400h

KEYWRITEAREA

Key Write Area

Section 10.9.1.12

404h

KEYWRITTENAREA

Key Written Area Status

Section 10.9.1.13

408h

KEYSIZE

Key Size

Section 10.9.1.14

40Ch

KEYREADAREA

Key Read Area

Section 10.9.1.15

500h to 50Ch AESKEY2_0 to AESKEY2_3

Clear AES_KEY2/GHASH Key

Section 10.9.1.16

510h to 51Ch AESKEY3_0 to AESKEY3_3

Clear AES_KEY3

Section 10.9.1.17

540h to 54Ch AESIV_0 to AESIV_3

AES Initialization Vector

Section 10.9.1.18

550h

AESCTL

AES Input/Output Buffer Control

Section 10.9.1.19

554h

AESDATALEN0

Crypto Data Length LSW

Section 10.9.1.20

558h

AESDATALEN1

Crypto Data Length MSW

Section 10.9.1.21

55Ch

AESAUTHLEN

AES Authentication Length

Section 10.9.1.22

560h

AESDATAOUT0

Data Input/Output

Section 10.9.1.23

560h

AESDATAIN0

AES Data Input/Output 0

Section 10.9.1.24

564h

AESDATAOUT1

AES Data Input/Output 3

Section 10.9.1.25

564h

AESDATAIN1

AES Data Input/Output 1

Section 10.9.1.26

568h

AESDATAOUT2

AES Data Input/Output 2

Section 10.9.1.27

568h

AESDATAIN2

AES Data Input/Output 2

Section 10.9.1.28

56Ch

AESDATAOUT3

AES Data Input/Output 3

Section 10.9.1.29

56Ch

AESDATAIN3

Data Input/Output

Section 10.9.1.30

570h to 57Ch AESTAGOUT_0 to AESTAGOUT_3

AES Tag Output

Section 10.9.1.31

700h

ALGSEL

Master Algorithm Select

Section 10.9.1.32

704h

DMAPROTCTL

Master Protection Control

Section 10.9.1.33

740h

SWRESET

Software Reset

Section 10.9.1.34

780h

IRQTYPE

Control Interrupt Configuration

Section 10.9.1.35

784h

IRQEN

Interrupt Enable

Section 10.9.1.36

788h

IRQCLR

Interrupt Clear

Section 10.9.1.37

78Ch

IRQSET

Interrupt Set

Section 10.9.1.38

790h

IRQSTAT

Interrupt Status

Section 10.9.1.39

7FCh

HWVER

CTRL Module Version

Section 10.9.1.40

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

939

Cryptography Registers

www.ti.com

10.9.1.1 DMACH0CTL Register (Offset = 0h) [reset = 0h]
DMACH0CTL is shown in Figure 10-3 and described in Table 10-11.
Return to Summary Table.
DMA Channel 0 Control
Figure 10-3. DMACH0CTL Register
31

1
PRIO
R/W-0h

0
EN
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 10-11. DMACH0CTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

PRIO

R/W

Channel priority:
A channel with high priority will be served before a channel with low
priority in cases with simultaneous access requests. If both channels
have the same priority access of the channels to the external port is
arbitrated using a Round Robin scheme.
0h = Priority low
1h = Priority high

R/W

DMA Channel 0 Control
0h = Channel disabled
1h = Channel enabled

31-2

940

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.2 DMACH0EXTADDR Register (Offset = 4h) [reset = 0h]
DMACH0EXTADDR is shown in Figure 10-4 and described in Table 10-12.
Return to Summary Table.
DMA Channel 0 External Address
Figure 10-4. DMACH0EXTADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R/W-0h

Table 10-12. DMACH0EXTADDR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

ADDR

R/W

Channel external address value.
Holds the last updated external address after being sent to the
master interface.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

941

Cryptography Registers

www.ti.com

10.9.1.3 DMACH0LEN Register (Offset = Ch) [reset = 0h]
DMACH0LEN is shown in Figure 10-5 and described in Table 10-13.
Return to Summary Table.
DMA Channel 0 Length
Figure 10-5. DMACH0LEN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

8 7 6
LEN
R/W-0h

Table 10-13. DMACH0LEN Register Field Descriptions
Bit

942

Field

Type

Reset

Description

31-16

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

LEN

R/W

DMA transfer length in bytes.
During configuration, this register contains the DMA transfer length
in bytes. During operation, it contains the last updated value of the
DMA transfer length after being sent to the master interface.
Note: Writing a non-zero value to this register field starts the transfer
if the channel is enabled by setting DMACH0CTL.EN.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.4 DMASTAT Register (Offset = 18h) [reset = 0h]
DMASTAT is shown in Figure 10-6 and described in Table 10-14.
Return to Summary Table.
DMA Controller Status
Figure 10-6. DMASTAT Register
31

17
PORT_ERR
R-0h

16
RESERVED
R-0h

1
CH1_ACTIVE
R-0h

0
CH0_ACTIVE
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 10-14. DMASTAT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-18

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

PORT_ERR

Reflects possible transfer errors on the AHB port.

16-2

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CH1_ACTIVE

This register field indicates if DMA channel 1 is active or not.
0: Not active
1: Active

CH0_ACTIVE

This register field indicates if DMA channel 0 is active or not.
0: Not active
1: Active

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

943

Cryptography Registers

www.ti.com

10.9.1.5 DMASWRESET Register (Offset = 1Ch) [reset = 0h]
DMASWRESET is shown in Figure 10-7 and described in Table 10-15.
Return to Summary Table.
DMA Controller Software Reset
Figure 10-7. DMASWRESET Register
31

0
RESET
W0C-0h

RESERVED
W-0h
23

20
RESERVED
W-0h

12
RESERVED
W-0h

4
RESERVED
W-0h

Table 10-15. DMASWRESET Register Field Descriptions
Bit
31-1
0

944

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RESET

W0C

Software reset enable
0: Disable
1: Enable (self-cleared to zero).
Note: Completion of the software reset must be checked in
DMASTAT.CH0_ACTIVE and DMASTAT.CH1_ACTIVE.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.6 DMACH1CTL Register (Offset = 20h) [reset = 0h]
DMACH1CTL is shown in Figure 10-8 and described in Table 10-16.
Return to Summary Table.
DMA Channel 1 Control
Figure 10-8. DMACH1CTL Register
31

1
PRIO
R/W-0h

0
EN
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 10-16. DMACH1CTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

PRIO

R/W

Channel enable:
Note: Disabling an active channel will interrupt the DMA operation.
The ongoing block transfer will be completed, but no new transfers
will be requested.
0h = Channel disabled
1h = Channel enabled

31-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

945

Cryptography Registers

www.ti.com

10.9.1.7 DMACH1EXTADDR Register (Offset = 24h) [reset = 0h]
DMACH1EXTADDR is shown in Figure 10-9 and described in Table 10-17.
Return to Summary Table.
DMA Channel 1 External Address
Figure 10-9. DMACH1EXTADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R/W-0h

Table 10-17. DMACH1EXTADDR Register Field Descriptions

946

Bit

Field

Type

Reset

Description

31-0

ADDR

R/W

Channel external address value.
Holds the last updated external address after being sent to the
master interface.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.8 DMACH1LEN Register (Offset = 2Ch) [reset = 0h]
DMACH1LEN is shown in Figure 10-10 and described in Table 10-18.
Return to Summary Table.
DMA Channel 1 Length
Figure 10-10. DMACH1LEN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

8 7 6
LEN
R/W-0h

Table 10-18. DMACH1LEN Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

LEN

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

947

Cryptography Registers

www.ti.com

10.9.1.9 DMABUSCFG Register (Offset = 78h) [reset = 2400h]
DMABUSCFG is shown in Figure 10-11 and described in Table 10-19.
Return to Summary Table.
DMA Controller Master Configuration
Figure 10-11. DMABUSCFG Register
31

11
AHB_MST1_ID
LE_EN
R/W-0h

10
AHB_MST1_IN
CR_EN
R/W-1h

9
AHB_MST1_L
OCK_EN
R/W-0h

8
AHB_MST1_BI
GEND
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

14
13
AHB_MST1_BURST_SIZE

R/W-2h
7

4
RESERVED
R/W-0h

Table 10-19. DMABUSCFG Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-12

AHB_MST1_BURST_SIZ
E

R/W

Maximum burst size that can be performed on the AHB bus
2h = 4_BYTE : 4 bytes
3h = 8_BYTE : 8 bytes
4h = 16_BYTE : 16 bytes
5h = 32_BYTE : 32 bytes
6h = 64_BYTE : 64 bytes

AHB_MST1_IDLE_EN

R/W

Idle transfer insertion between consecutive burst transfers on AHB
0h = Do not insert idle transfers.
1h = Idle transfer insertion enabled

AHB_MST1_INCR_EN

R/W

Burst length type of AHB transfer
0h = Unspecified length burst transfers
1h = Fixed length bursts or single transfers

AHB_MST1_LOCK_EN

R/W

Locked transform on AHB
0h = Transfers are not locked
1h = Transfers are locked

AHB_MST1_BIGEND

R/W

Endianess for the AHB master
0h = Little Endian
1h = Big Endian

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

948

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.10 DMAPORTERR Register (Offset = 7Ch) [reset = 0h]
DMAPORTERR is shown in Figure 10-12 and described in Table 10-20.
Return to Summary Table.
DMA Controller Port Error
Figure 10-12. DMAPORTERR Register
31

9
LAST_CH
R-0h

8
RESERVED
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

14
RESERVED
R-0h

12
AHB_ERR
R-0h

RESERVED
R-0h

Table 10-20. DMAPORTERR Register Field Descriptions
Bit
31-13
12
11-10
9
8-0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AHB_ERR

A 1 indicates that the Crypto peripheral has detected an AHB bus
error

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

LAST_CH

Indicates which channel was serviced last (channel 0 or channel 1)
by the AHB master port.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

949

Cryptography Registers

www.ti.com

10.9.1.11 DMAHWVER Register (Offset = FCh) [reset = 01012ED1h]
DMAHWVER is shown in Figure 10-13 and described in Table 10-21.
Return to Summary Table.
DMA Controller Version
Figure 10-13. DMAHWVER Register
31

30
29
RESERVED
R-0h

26
25
HW_MAJOR_VER
R-1h

12
11
10
VER_NUM_COMPL
R-2Eh

22
21
HW_MINOR_VER
R-0h
6

18
17
HW_PATCH_LVL
R-1h

4
3
VER_NUM
R-D1h

Table 10-21. DMAHWVER Register Field Descriptions
Bit

950

Field

Type

Reset

Description

31-28

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

27-24

HW_MAJOR_VER

Major version number

23-20

HW_MINOR_VER

Minor version number

19-16

HW_PATCH_LVL

Patch level.

15-8

VER_NUM_COMPL

2Eh

Bit-by-bit complement of the VER_NUM field bits.

7-0

VER_NUM

D1h

Version number of the DMA Controller (209)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.12 KEYWRITEAREA Register (Offset = 400h) [reset = 0h]
KEYWRITEAREA is shown in Figure 10-14 and described in Table 10-22.
Return to Summary Table.
Key Write Area
Figure 10-14. KEYWRITEAREA Register
31

3
RAM_AREA3
R/W-0h

2
RAM_AREA2
R/W-0h

1
RAM_AREA1
R/W-0h

0
RAM_AREA0
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

7
RAM_AREA7
R/W-0h

6
RAM_AREA6
R/W-0h

5
RAM_AREA5
R/W-0h

4
RAM_AREA4
R/W-0h

Table 10-22. KEYWRITEAREA Register Field Descriptions
Bit

Field

Type

Reset

Description

31-8

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RAM_AREA7

R/W

Represents an area of 128 bits.
Select the key store RAM area(s) where the key(s) needs to be
written.
Writing to multiple RAM locations is only possible when the selected
RAM areas are sequential.
0h = This RAM area is not selected to be written
1h = This RAM area is selected to be written

RAM_AREA6

R/W

RAM_AREA5

R/W

RAM_AREA4

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

951

Cryptography Registers

www.ti.com

Table 10-22. KEYWRITEAREA Register Field Descriptions (continued)
Bit

952

Field

Type

Reset

Description

RAM_AREA3

R/W

RAM_AREA2

R/W

RAM_AREA1

R/W

RAM_AREA0

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.13 KEYWRITTENAREA Register (Offset = 404h) [reset = 0h]
KEYWRITTENAREA is shown in Figure 10-15 and described in Table 10-23.
Return to Summary Table.
Key Written Area Status
This register shows which areas of the key store RAM contain valid written keys.
When a new key needs to be written to the key store, on a location that is already occupied by a valid key,
this key area must be cleared first. This can be done by writing this register before the new key is written
to the key store memory.
Attempting to write to a key area that already contains a valid key is not allowed and will result in an error.
Figure 10-15. KEYWRITTENAREA Register
31

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

7
6
5
4
3
2
1
0
RAM_AREA_W RAM_AREA_W RAM_AREA_W RAM_AREA_W RAM_AREA_W RAM_AREA_W RAM_AREA_W RAM_AREA_W
RITTEN7
RITTEN6
RITTEN5
RITTEN4
RITTEN3
RITTEN2
RITTEN1
RITTEN0
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h

Table 10-23. KEYWRITTENAREA Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RAM_AREA_WRITTEN7

R/W1C

On read this bit returns the key area written status.
This bit can be reset by writing a 1.
Note: This register will be reset on a soft reset initiated by writing to
DMASWRESET.RESET. After a soft reset, all keys must be rewritten
to the key store memory.
0h = This RAM area is not written with valid key information
1h = This RAM area is written with valid key information

RAM_AREA_WRITTEN6

R/W1C

RAM_AREA_WRITTEN5

R/W1C

RAM_AREA_WRITTEN4

R/W1C

31-8

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

953

Cryptography Registers

www.ti.com

Table 10-23. KEYWRITTENAREA Register Field Descriptions (continued)
Bit

954

Field

Type

Reset

Description

RAM_AREA_WRITTEN3

R/W1C

RAM_AREA_WRITTEN2

R/W1C

RAM_AREA_WRITTEN1

R/W1C

RAM_AREA_WRITTEN0

R/W1C

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.14 KEYSIZE Register (Offset = 408h) [reset = 1h]
KEYSIZE is shown in Figure 10-16 and described in Table 10-24.
Return to Summary Table.
Key Size
This register defines the size of the keys that are written with DMA.
Figure 10-16. KEYSIZE Register
31

24
23
RESERVED
R/W-0h

9
8
RESERVED
R/W-0h

SIZE
R/W-1h

Table 10-24. KEYSIZE Register Field Descriptions
Field

Type

Reset

Description

31-2

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

SIZE

R/W

Key size
When writing to this register, KEYWRITTENAREA will be reset.
Note: For the Crypto peripheral this field is fixed to 128 bits. For
software compatibility KEYWRITTENAREA will be reset when writing
to this register.
1h = 128_BIT : 128 bits
2h = 192_BIT : Not supported
3h = 256_BIT : Not supported

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

955

Cryptography Registers

www.ti.com

10.9.1.15 KEYREADAREA Register (Offset = 40Ch) [reset = 8h]
KEYREADAREA is shown in Figure 10-17 and described in Table 10-25.
Return to Summary Table.
Key Read Area
Figure 10-17. KEYREADAREA Register
31
BUSY
R-0h

27
RESERVED
R/W-0h

RESERVED
R/W-0h
15

12
RESERVED
R/W-0h

RESERVED
R/W-0h

RAM_AREA
R/W-8h

Table 10-25. KEYREADAREA Register Field Descriptions

956

Bit

Field

Type

Reset

Description

BUSY

Key store operation busy status flag (read only)
0: operation is completed.
1: operation is not completed and the key store is busy.

30-4

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

RAM_AREA

R/W

Selects the area of the key store RAM from where the key needs to
be read that will be written to the AES engine.
Only RAM areas that contain valid written keys can be selected.
0h = RAM Area 0
1h = RAM Area 1
2h = RAM Area 2
3h = RAM Area 3
4h = RAM Area 4
5h = RAM Area 5
6h = RAM Area 6
7h = RAM Area 7
8h = No RAM

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.16 AESKEY2_0 to AESKEY2_3 Register (Offset = 500h to 50Ch) [reset = 0h]
AESKEY2_0 to AESKEY2_3 is shown in Figure 10-18 and described in Table 10-26.
Return to Summary Table.
Clear AES_KEY2/GHASH Key
Figure 10-18. AESKEY2_0 to AESKEY2_3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
KEY2
W-0h

Table 10-26. AESKEY2_0 to AESKEY2_3 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

KEY2

AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where
x = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register
array.
The interpretation of this field depends on the crypto operation
mode.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

957

Cryptography Registers

www.ti.com

10.9.1.17 AESKEY3_0 to AESKEY3_3 Register (Offset = 510h to 51Ch) [reset = 0h]
AESKEY3_0 to AESKEY3_3 is shown in Figure 10-19 and described in Table 10-27.
Return to Summary Table.
Clear AES_KEY3
Figure 10-19. AESKEY3_0 to AESKEY3_3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
KEY3
W-0h

Table 10-27. AESKEY3_0 to AESKEY3_3 Register Field Descriptions

958

Bit

Field

Type

Reset

Description

31-0

KEY3

AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x
= 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register
arrary.
The interpretation of this field depends on the crypto operation
mode.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.18 AESIV_0 to AESIV_3 Register (Offset = 540h to 54Ch) [reset = 0h]
AESIV_0 to AESIV_3 is shown in Figure 10-20 and described in Table 10-28.
Return to Summary Table.
AES Initialization Vector
Figure 10-20. AESIV_0 to AESIV_3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IV
R/W-0h

Table 10-28. AESIV_0 to AESIV_3 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

R/W

The interpretation of this field depends on the crypto operation
mode.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

959

Cryptography Registers

www.ti.com

10.9.1.19 AESCTL Register (Offset = 550h) [reset = 80000000h]
AESCTL is shown in Figure 10-21 and described in Table 10-29.
Return to Summary Table.
AES Input/Output Buffer Control
Figure 10-21. AESCTL Register
31
CONTEXT_RD
Y
R-1h

30
SAVED_CONT
EXT_RDY
R/W-0h

29
SAVE_CONTE
XT
R/W-0h

20
CCM_L
R/W-0h

CCM_M
R/W-0h
15
CBC_MAC
R/W-0h

7
CTR_WIDTH
R/W-0h

6
CTR
R/W-0h

27
RESERVED

24
CCM_M

R/W-0h

R/W-0h
18
CCM
R/W-0h

8
CTR_WIDTH
R/W-0h

2
DIR
R/W-0h

1
INPUT_RDY
R/W-0h

0
OUTPUT_RDY
R/W-0h

RESERVED
R/W-0h

RESERVED
R/W-0h
5
CBC
R/W-0h

4
KEY_SIZE
R-0h

Table 10-29. AESCTL Register Field Descriptions

960

Bit

Field

Type

Reset

Description

CONTEXT_RDY

If 1, this status bit indicates that the context data registers can be
overwritten and the Host is permitted to write the next context.
Writing a context means writing either a mode, the crypto length or
AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length
registers

SAVED_CONTEXT_RDY

R/W

If read as 1, this status bit indicates that an AES authentication TAG
and/or IV block(s) is/are available for the Host to retrieve. This bit is
only asserted if SAVE_CONTEXT is set to 1. The bit is mutually
exclusive with CONTEXT_RDY.
Writing 1 clears the bit to zero, indicating the Crypto peripheral can
start its next operation. This bit is also cleared when the 4th word of
the output TAG and/or IV is read.
Note: All other mode bit writes will be ignored when this mode bit is
written with 1.
Note: This bit is controlled automatically by the Crypto peripheral for
TAG read DMA operations.
For typical use, this bit does NOT need to be written, but is used for
status reading only. In this case, this status bit is automatically
maintained by the Crypto peripheral.

SAVE_CONTEXT

R/W

IV must be read before the AES engine can start a new operation.

28-25

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

24-22

CCM_M

R/W

Defines M that indicates the length of the authentication field for
CCM operations
the authentication field length equals two times the value of CCM_M
plus one.
Note: The Crypto peripheral always returns a 128-bit authentication
field, of which the M least significant bytes are valid. All values are
supported.

21-19

CCM_L

R/W

Defines L that indicates the width of the length field for CCM
operations
the length field in bytes equals the value of CMM_L plus one. All
values are supported.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

Table 10-29. AESCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

CCM

R/W

AES-CCM mode enable.
AES-CCM is a combined mode, using AES for both authentication
and encryption.
Note: Selecting AES-CCM mode requires writing of
AESDATALEN1.LEN_MSW and AESDATALEN0.LEN_LSW after all
other registers.
Note: The CTR mode bit in this register must also be set to 1 to
enable AES-CTR
selecting other AES modes than CTR mode is invalid.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CBC_MAC

R/W

MAC mode enable.
The DIR bit must be set to 1 for this mode.
Selecting this mode requires writing the AESDATALEN1.LEN_MSW
and AESDATALEN0.LEN_LSW registers after all other registers.

14-9

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

8-7

CTR_WIDTH

R/W

Specifies the counter width for AES-CTR mode
0h = 32_BIT : 32 bits
1h = 64_BIT : 64 bits
2h = 96_BIT : 96 bits
3h = 128_BIT : 128 bits

CTR

R/W

AES-CTR mode enable
This bit must also be set for CCM, when encryption/decryption is
required.

CBC

R/W

CBC mode enable

KEY_SIZE

This field specifies the key size.
The key size is automatically configured when a new key is loaded
via the key store module.
00 = N/A - reserved
01 = 128 bits
10 = N/A - reserved
11 = N/A - reserved
For the Crypto peripheral this field is fixed to 128 bits.

DIR

R/W

Direction.
0 : Decrypt operation is performed.
1 : Encrypt operation is performed.
This bit must be written with a 1 when CBC-MAC is selected.

INPUT_RDY

R/W

If read as 1, this status bit indicates that the 16-byte AES input buffer
is empty. The Host is permitted to write the next block of data.
Writing a 0 clears the bit to zero and indicates that the AES engine
can use the provided input data block.
Writing a 1 to this bit will be ignored.
Note: For DMA operations, this bit is automatically controlled by the
Crypto peripheral.
After reset, this bit is 0. After writing a context (note 1), this bit will
become 1.
For typical use, this bit does NOT need to be written, but is used for
status reading only. In this case, this status bit is automatically
maintained by the Crypto peripheral.

OUTPUT_RDY

R/W

If read as 1, this status bit indicates that an AES output block is
available to be retrieved by the Host.
Writing a 0 clears the bit to zero and indicates that output data is
read by the Host. The AES engine can provide a next output data
block.
Writing a 1 to this bit will be ignored.
Note: For DMA operations, this bit is automatically controlled by the
Crypto peripheral.
For typical use, this bit does NOT need to be written, but is used for
status reading only. In this case, this status bit is automatically
maintained by the Crypto peripheral.

17-16
15

4-3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

961

Cryptography Registers

www.ti.com

10.9.1.20 AESDATALEN0 Register (Offset = 554h) [reset = 0h]
AESDATALEN0 is shown in Figure 10-22 and described in Table 10-30.
Return to Summary Table.
Crypto Data Length LSW
Figure 10-22. AESDATALEN0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LEN_LSW
W-0h

Table 10-30. AESDATALEN0 Register Field Descriptions
Bit
31-0

962

Field

Type

Reset

Description

LEN_LSW

Used to write the Length values to the Crypto peripheral.
This register contains bits [31:0] of the combined data length.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.21 AESDATALEN1 Register (Offset = 558h) [reset = 0h]
AESDATALEN1 is shown in Figure 10-23 and described in Table 10-31.
Return to Summary Table.
Crypto Data Length MSW
Figure 10-23. AESDATALEN1 Register
31

30
29
RESERVED
W-0h

8
7
LEN_MSW
W-0h

22
21
LEN_MSW
W-0h
6

Table 10-31. AESDATALEN1 Register Field Descriptions
Field

Type

Reset

Description

31-29

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

28-0

LEN_MSW

Bits [60:32] of the combined data length.
Bits [60:0] of the crypto length registers AESDATALEN1 and
AESDATALEN0 store the cryptographic data length in bytes for all
modes. Once processing with this context is started, this length
decrements to zero. Data lengths up to (261 - 1) bytes are allowed.
For GCM, any value up to 236 - 32 bytes can be used. This is
because a 32-bit counter mode is used
the maximum number of 128-bit blocks is 232 - 2, resulting in a
maximum number of bytes of 236 - 32.
Writing to this register triggers the engine to start using this context.
This is valid for all modes except GCM and CCM.
Note: For the combined modes (GCM and CCM), this length does
not include the authentication only data
the authentication length is specified in the AESAUTHLEN.LEN.
All modes must have a length > 0. For the combined modes, it is
allowed to have one of the lengths equal to zero.
For the basic encryption modes (ECB/CBC/CTR) it is allowed to
program zero to the length field
in that case the length is assumed infinite.
All data must be byte (8-bit) aligned for stream cipher modes
bit aligned data streams are not supported by the Crypto peripheral.
For block cipher modes, the data length must be programmed in
multiples of the block cipher size, 16 bytes.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

963

Cryptography Registers

www.ti.com

10.9.1.22 AESAUTHLEN Register (Offset = 55Ch) [reset = 0h]
AESAUTHLEN is shown in Figure 10-24 and described in Table 10-32.
Return to Summary Table.
AES Authentication Length
Figure 10-24. AESAUTHLEN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LEN
W-0h

Table 10-32. AESAUTHLEN Register Field Descriptions

964

Bit

Field

Type

Reset

Description

31-0

LEN

Authentication data length in bytes for combined mode, CCM only.
Supported AAD-lengths for CCM are from 0 to (216 - 28) bytes.
Once processing with this context is started, this length decrements
to zero.
Writing this register triggers the engine to start using this context for
CCM.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.23 AESDATAOUT0 Register (Offset = 560h) [reset = 0h]
AESDATAOUT0 is shown in Figure 10-25 and described in Table 10-33.
Return to Summary Table.
Data Input/Output
Figure 10-25. AESDATAOUT0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA
R-0h

Table 10-33. AESDATAOUT0 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

DATA

Data register 0 for output block data from the Crypto peripheral.
These bits = AES Output Data[31:0] of {127:0]
For normal operations, this register is not used, since data input and
output is transferred from and to the AES engine via DMA.
For a Host read operation, these registers contain the 128-bit output
block from the latest AES operation. Reading from a word-aligned
offset within this address range will read one word (4 bytes) of data
out the 4-word deep (16 bytes = 128-bits AES block) data output
buffer. The words (4 words, one full block) should be read before the
core will move the next block to the data output buffer. To empty the
data output buffer, AESCTL.OUTPUT_RDY must be written.
For the modes with authentication (CBC-MAC, GCM and CCM), the
invalid (message) bytes/words can be written with any data.
Note: The AAD / authentication only data is not copied to the output
buffer but only used for authentication.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

965

Cryptography Registers

www.ti.com

10.9.1.24 AESDATAIN0 Register (Offset = 560h) [reset = 0h]
AESDATAIN0 is shown in Figure 10-26 and described in Table 10-34.
Return to Summary Table.
AES Data Input/Output 0
Figure 10-26. AESDATAIN0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA
W-0h

Table 10-34. AESDATAIN0 Register Field Descriptions

966

Bit

Field

Type

Reset

Description

31-0

DATA

Data registers for input block data to the Crypto peripheral.
These bits = AES Input Data[31:0] of [127:0]
For normal operations, this register is not used, since data input and
output is transferred from and to the AES engine via DMA.
For a Host write operation, these registers must be written with the
128-bit input block for the next AES operation. Writing at a wordaligned offset within this address range will store the word (4 bytes)
of data into the corresponding position of 4-word deep (16 bytes =
128-bit AES block) data input buffer. This buffer is used for the next
AES operation. If the last data block is not completely filled with valid
data (see notes below), it is allowed to write only the words with valid
data. Next AES operation is triggered by writing to
AESCTL.INPUT_RDY.
Note: AES typically operates on 128 bits block multiple input data.
The CTR, GCM and CCM modes form an exception. The last block
of a CTR-mode message may contain less than 128 bits (refer to
[NIST 800-38A]): 0 < n <= 128 bits. For GCM/CCM, the last block of
both AAD and message data may contain less than 128 bits (refer to
[NIST 800-38D]). The Crypto peripheral automatically pads or masks
misaligned ending data blocks with zeroes for GCM, CCM and CBCMAC. For CTR mode, the remaining data in an unaligned data block
is ignored.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.25 AESDATAOUT1 Register (Offset = 564h) [reset = 0h]
AESDATAOUT1 is shown in Figure 10-27 and described in Table 10-35.
Return to Summary Table.
AES Data Input/Output 3
Figure 10-27. AESDATAOUT1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA
R-0h

Table 10-35. AESDATAOUT1 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

DATA

Data registers for output block data from the Crypto peripheral.
These bits = AES Output Data[63:32] of [127:0]
For normal operations, this register is not used, since data input and
output is transferred from and to the AES engine via DMA.
For a Host read operation, these registers contain the 128-bit output
block from the latest AES operation. Reading from a word-aligned
offset within this address range will read one word (4 bytes) of data
out the 4-word deep (16 bytes = 128-bits AES block) data output
buffer. The words (4 words, one full block) should be read before the
core will move the next block to the data output buffer. To empty the
data output buffer, AESCTL.OUTPUT_RDY must be written.
For the modes with authentication (CBC-MAC, GCM and CCM), the
invalid (message) bytes/words can be written with any data.
Note: The AAD / authentication only data is not copied to the output
buffer but only used for authentication.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

967

Cryptography Registers

www.ti.com

10.9.1.26 AESDATAIN1 Register (Offset = 564h) [reset = 0h]
AESDATAIN1 is shown in Figure 10-28 and described in Table 10-36.
Return to Summary Table.
AES Data Input/Output 1
Figure 10-28. AESDATAIN1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA
W-0h

Table 10-36. AESDATAIN1 Register Field Descriptions

968

Bit

Field

Type

Reset

Description

31-0

DATA

Data registers for input block data to the Crypto peripheral.
These bits = AES Input Data[63:32] of [127:0]
For normal operations, this register is not used, since data input and
output is transferred from and to the AES engine via DMA.
For a Host write operation, these registers must be written with the
128-bit input block for the next AES operation. Writing at a wordaligned offset within this address range will store the word (4 bytes)
of data into the corresponding position of 4-word deep (16 bytes =
128-bit AES block) data input buffer. This buffer is used for the next
AES operation. If the last data block is not completely filled with valid
data (see notes below), it is allowed to write only the words with valid
data. Next AES operation is triggered by writing to
AESCTL.INPUT_RDY.
Note: AES typically operates on 128 bits block multiple input data.
The CTR, GCM and CCM modes form an exception. The last block
of a CTR-mode message may contain less than 128 bits (refer to
[NIST 800-38A]): 0 < n <= 128 bits. For GCM/CCM, the last block of
both AAD and message data may contain less than 128 bits (refer to
[NIST 800-38D]). The Crypto peripheral automatically pads or masks
misaligned ending data blocks with zeroes for GCM, CCM and CBCMAC. For CTR mode, the remaining data in an unaligned data block
is ignored.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.27 AESDATAOUT2 Register (Offset = 568h) [reset = 0h]
AESDATAOUT2 is shown in Figure 10-29 and described in Table 10-37.
Return to Summary Table.
AES Data Input/Output 2
Figure 10-29. AESDATAOUT2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA
R-0h

Table 10-37. AESDATAOUT2 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

DATA

Data registers for output block data from the Crypto peripheral.
These bits = AES Output Data[95:64] of [127:0]
For normal operations, this register is not used, since data input and
output is transferred from and to the AES engine via DMA.
For a Host read operation, these registers contain the 128-bit output
block from the latest AES operation. Reading from a word-aligned
offset within this address range will read one word (4 bytes) of data
out the 4-word deep (16 bytes = 128-bits AES block) data output
buffer. The words (4 words, one full block) should be read before the
core will move the next block to the data output buffer. To empty the
data output buffer, AESCTL.OUTPUT_RDY must be written.
For the modes with authentication (CBC-MAC, GCM and CCM), the
invalid (message) bytes/words can be written with any data.
Note: The AAD / authentication only data is not copied to the output
buffer but only used for authentication.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

969

Cryptography Registers

www.ti.com

10.9.1.28 AESDATAIN2 Register (Offset = 568h) [reset = 0h]
AESDATAIN2 is shown in Figure 10-30 and described in Table 10-38.
Return to Summary Table.
AES Data Input/Output 2
Figure 10-30. AESDATAIN2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA
W-0h

Table 10-38. AESDATAIN2 Register Field Descriptions

970

Bit

Field

Type

Reset

Description

31-0

DATA

Data registers for input block data to the Crypto peripheral.
These bits = AES Input Data[95:64] of [127:0]
For normal operations, this register is not used, since data input and
output is transferred from and to the AES engine via DMA.
For a Host write operation, these registers must be written with the
128-bit input block for the next AES operation. Writing at a wordaligned offset within this address range will store the word (4 bytes)
of data into the corresponding position of 4-word deep (16 bytes =
128-bit AES block) data input buffer. This buffer is used for the next
AES operation. If the last data block is not completely filled with valid
data (see notes below), it is allowed to write only the words with valid
data. Next AES operation is triggered by writing to
AESCTL.INPUT_RDY.
Note: AES typically operates on 128 bits block multiple input data.
The CTR, GCM and CCM modes form an exception. The last block
of a CTR-mode message may contain less than 128 bits (refer to
[NIST 800-38A]): 0 < n <= 128 bits. For GCM/CCM, the last block of
both AAD and message data may contain less than 128 bits (refer to
[NIST 800-38D]). The Crypto peripheral automatically pads or masks
misaligned ending data blocks with zeroes for GCM, CCM and CBCMAC. For CTR mode, the remaining data in an unaligned data block
is ignored.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.29 AESDATAOUT3 Register (Offset = 56Ch) [reset = 0h]
AESDATAOUT3 is shown in Figure 10-31 and described in Table 10-39.
Return to Summary Table.
AES Data Input/Output 3
Figure 10-31. AESDATAOUT3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA
R-0h

Table 10-39. AESDATAOUT3 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

DATA

Data registers for output block data from the Crypto peripheral.
These bits = AES Output Data[127:96] of [127:0]
For normal operations, this register is not used, since data input and
output is transferred from and to the AES engine via DMA.
For a Host read operation, these registers contain the 128-bit output
block from the latest AES operation. Reading from a word-aligned
offset within this address range will read one word (4 bytes) of data
out the 4-word deep (16 bytes = 128-bits AES block) data output
buffer. The words (4 words, one full block) should be read before the
core will move the next block to the data output buffer. To empty the
data output buffer, AESCTL.OUTPUT_RDY must be written.
For the modes with authentication (CBC-MAC, GCM and CCM), the
invalid (message) bytes/words can be written with any data.
Note: The AAD / authentication only data is not copied to the output
buffer but only used for authentication.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

971

Cryptography Registers

www.ti.com

10.9.1.30 AESDATAIN3 Register (Offset = 56Ch) [reset = 0h]
AESDATAIN3 is shown in Figure 10-32 and described in Table 10-40.
Return to Summary Table.
Data Input/Output
Figure 10-32. AESDATAIN3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA
W-0h

Table 10-40. AESDATAIN3 Register Field Descriptions

972

Bit

Field

Type

Reset

Description

31-0

DATA

Data registers for input block data to the Crypto peripheral.
These bits = AES Input Data[127:96] of [127:0]
For normal operations, this register is not used, since data input and
output is transferred from and to the AES engine via DMA.
For a Host write operation, these registers must be written with the
128-bit input block for the next AES operation. Writing at a wordaligned offset within this address range will store the word (4 bytes)
of data into the corresponding position of 4-word deep (16 bytes =
128-bit AES block) data input buffer. This buffer is used for the next
AES operation. If the last data block is not completely filled with valid
data (see notes below), it is allowed to write only the words with valid
data. Next AES operation is triggered by writing to
AESCTL.INPUT_RDY.
Note: AES typically operates on 128 bits block multiple input data.
The CTR, GCM and CCM modes form an exception. The last block
of a CTR-mode message may contain less than 128 bits (refer to
[NIST 800-38A]): 0 < n <= 128 bits. For GCM/CCM, the last block of
both AAD and message data may contain less than 128 bits (refer to
[NIST 800-38D]). The Crypto peripheral automatically pads or masks
misaligned ending data blocks with zeroes for GCM, CCM and CBCMAC. For CTR mode, the remaining data in an unaligned data block
is ignored.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.31 AESTAGOUT_0 to AESTAGOUT_3 Register (Offset = 570h to 57Ch) [reset = 0h]
AESTAGOUT_0 to AESTAGOUT_3 is shown in Figure 10-33 and described in Table 10-41.
Return to Summary Table.
AES Tag Output
Figure 10-33. AESTAGOUT_0 to AESTAGOUT_3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TAG
R-0h

Table 10-41. AESTAGOUT_0 to AESTAGOUT_3 Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

TAG

This register contains the authentication TAG for the combined and
authentication-only modes.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

973

Cryptography Registers

www.ti.com

10.9.1.32 ALGSEL Register (Offset = 700h) [reset = 0h]
ALGSEL is shown in Figure 10-34 and described in Table 10-42.
Return to Summary Table.
Master Algorithm Select
This register configures the internal destination of the DMA controller.
Figure 10-34. ALGSEL Register
31
TAG
R/W-0h

27
RESERVED
R/W-0h

1
AES
R/W-0h

0
KEY_STORE
R/W-0h

RESERVED
R/W-0h
15

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 10-42. ALGSEL Register Field Descriptions
Bit

Field

Type

Reset

Description

TAG

R/W

If this bit is cleared to 0, the DMA operation involves only data.
If this bit is set, the DMA operation includes a TAG (Authentication
Result / Digest).

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AES

R/W

If set to 1, the AES data is loaded via DMA
Both Read and Write maximum transfer size to DMA engine is set to
16 bytes

KEY_STORE

R/W

If set to 1, selects the Key Store to be loaded via DMA.
The maximum transfer size to DMA engine is set to 32 bytes
(however transfers of 16, 24 and 32 bytes are allowed)

30-2

974

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.33 DMAPROTCTL Register (Offset = 704h) [reset = 0h]
DMAPROTCTL is shown in Figure 10-35 and described in Table 10-43.
Return to Summary Table.
Master Protection Control
Figure 10-35. DMAPROTCTL Register
31

24
23
RESERVED
R/W-0h
8
7
RESERVED
R/W-0h

0
EN
R/W0h

Table 10-43. DMAPROTCTL Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Select AHB transfer protection control for DMA transfers using the
key store area as destination.
0 : transfers use 'USER' type access.
1 : transfers use 'PRIVILEGED' type access.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

975

Cryptography Registers

www.ti.com

10.9.1.34 SWRESET Register (Offset = 740h) [reset = 0h]
SWRESET is shown in Figure 10-36 and described in Table 10-44.
Return to Summary Table.
Software Reset
Figure 10-36. SWRESET Register
31

0
RESET
R/W1C-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 10-44. SWRESET Register Field Descriptions
Bit
31-1
0

976

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RESET

R/W1C

If this bit is set to 1, the following modules are reset:
- Master control internal state is reset. That includes interrupt, error
status register and result available interrupt generation FSM.
- Key store module state is reset. That includes clearing the Written
Area flags
therefore the keys must be reloaded to the key store module.
Writing 0 has no effect.
The bit is self cleared after executing the reset.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.35 IRQTYPE Register (Offset = 780h) [reset = 0h]
IRQTYPE is shown in Figure 10-37 and described in Table 10-45.
Return to Summary Table.
Control Interrupt Configuration
Figure 10-37. IRQTYPE Register
31

0
LEVEL
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 10-45. IRQTYPE Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

LEVEL

R/W

If this bit is 0, the interrupt output is a pulse.
If this bit is set to 1, the interrupt is a level interrupt that must be
cleared by writing the interrupt clear register.
This bit is applicable for both interrupt output signals.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

977

Cryptography Registers

www.ti.com

10.9.1.36 IRQEN Register (Offset = 784h) [reset = 0h]
IRQEN is shown in Figure 10-38 and described in Table 10-46.
Return to Summary Table.
Interrupt Enable
Figure 10-38. IRQEN Register
31

1
DMA_IN_DON
E
R/W-0h

0
RESULT_AVAI
L
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

4
RESERVED
R/W-0h

Table 10-46. IRQEN Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMA_IN_DONE

R/W

This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ.

RESULT_AVAIL

R/W

This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ.

31-2

978

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.37 IRQCLR Register (Offset = 788h) [reset = 0h]
IRQCLR is shown in Figure 10-39 and described in Table 10-47.
Return to Summary Table.
Interrupt Clear
Figure 10-39. IRQCLR Register
31
DMA_BUS_ER
R
W-0h

30
KEY_ST_WR_
ERR
W-0h

29
KEY_ST_RD_E
RR
W-0h

26
RESERVED

W-0h
19

1
DMA_IN_DON
E
W-0h

0
RESULT_AVAI
L
W-0h

RESERVED
W-0h
15

12
RESERVED
W-0h

4
RESERVED
W-0h

Table 10-47. IRQCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

DMA_BUS_ERR

If 1 is written to this bit, IRQSTAT.DMA_BUS_ERR is cleared.

KEY_ST_WR_ERR

If 1 is written to this bit, IRQSTAT.KEY_ST_WR_ERR is cleared.

KEY_ST_RD_ERR

If 1 is written to this bit, IRQSTAT.KEY_ST_RD_ERR is cleared.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMA_IN_DONE

If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared.

RESULT_AVAIL

If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared.

28-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

979

Cryptography Registers

www.ti.com

10.9.1.38 IRQSET Register (Offset = 78Ch) [reset = 0h]
IRQSET is shown in Figure 10-40 and described in Table 10-48.
Return to Summary Table.
Interrupt Set
Figure 10-40. IRQSET Register
31

1
DMA_IN_DON
E
W-0h

0
RESULT_AVAI
L
W-0h

RESERVED
W-0h
23

20
RESERVED
W-0h

12
RESERVED
W-0h

4
RESERVED
W-0h

Table 10-48. IRQSET Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMA_IN_DONE

If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set.
Writing 0 has no effect.

RESULT_AVAIL

If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set.
Writing 0 has no effect.

31-2

980

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Cryptography Registers

www.ti.com

10.9.1.39 IRQSTAT Register (Offset = 790h) [reset = 0h]
IRQSTAT is shown in Figure 10-41 and described in Table 10-49.
Return to Summary Table.
Interrupt Status
Figure 10-41. IRQSTAT Register
31
DMA_BUS_ER
R
R-0h

30
KEY_ST_WR_
ERR
R-0h

29
KEY_ST_RD_E
RR
R-0h

26
RESERVED

R-0h
19

1
DMA_IN_DON
E
R-0h

0
RESULT_AVAI
L
R-0h

RESERVED
R-0h
15

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 10-49. IRQSTAT Register Field Descriptions
Bit

Field

Type

Reset

Description

DMA_BUS_ERR

This bit is set when a DMA bus error is detected during a DMA
operation. The value of this register is held until it is cleared via
IRQCLR.DMA_BUS_ERR
Note: This error is asserted if an error is detected on the AHB master
interface during a DMA operation.
Note: This is not an interrupt source.

KEY_ST_WR_ERR

This bit is set when a write error is detected during the DMA write
operation to the key store memory. The value of this register is held
until it is cleared via IRQCLR.KEY_ST_WR_ERR
Note: This error is asserted if a DMA operation does not cover a full
key area or more areas are written than expected.
Note: This is not an interrupt source.

KEY_ST_RD_ERR

This bit will be set when a read error is detected during the read of a
key from the key store, while copying it to the AES engine. The value
of this register is held until it is cleared via
IRQCLR.KEY_ST_RD_ERR.
Note: This error is asserted if a key location is selected in the key
store that is not available.
Note: This is not an interrupt source.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMA_IN_DONE

This bit returns the status of DMA data in done interrupt.

RESULT_AVAIL

This bit is set high when the Crypto peripheral has a result available.

28-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

981

Cryptography Registers

www.ti.com

10.9.1.40 HWVER Register (Offset = 7FCh) [reset = 91118778h]
HWVER is shown in Figure 10-42 and described in Table 10-50.
Return to Summary Table.
CTRL Module Version
Figure 10-42. HWVER Register
31

30
29
RESERVED
R-9h

26
25
HW_MAJOR_VER
R-1h

12
11
10
VER_NUM_COMPL
R-87h

22
21
HW_MINOR_VER
R-1h
6

4
3
VER_NUM
R-78h

18
17
HW_PATCH_LVL
R-1h
2

Table 10-50. HWVER Register Field Descriptions
Bit

982

Field

Type

Reset

Description

31-28

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

27-24

HW_MAJOR_VER

Major version number

23-20

HW_MINOR_VER

Minor version number

19-16

HW_PATCH_LVL

Patch level, starts at 0 at first delivery of this version.

15-8

VER_NUM_COMPL

87h

These bits simply contain the complement of VER_NUM (0x87),
used by a driver to ascertain that the Crypto peripheral register is
indeed read.

7-0

VER_NUM

78h

The version number for the Crypto peripheral, this field contains the
value 120 (decimal) or 0x78.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Chapter 11
SWCU117G – February 2015 – Revised February 2017

I/O Control
This chapter describes the input/output controller (IOC) and the general-purpose inputs and outputs
(GPIOs). The IOC design provides a flexible configuration, as most of the peripheral ports can be mapped
to any of the physical I/O pads (I/O at die boundary). The CC26x0 and CC13x0 device series has up to 31
I/O pins configurable as GPIO or to a peripheral function.
Topic

...........................................................................................................................

11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11

Introduction .....................................................................................................
IOC Overview ...................................................................................................
I/O Mapping and Configuration...........................................................................
Edge Detection on Pin (DIO) ..............................................................................
AON IOC State Latching When Powering Off the MCU Domain .............................
Unused I/O Pins ...............................................................................................
GPIO ...............................................................................................................
I/O Pin Mapping ................................................................................................
Peripheral PORTIDs ..........................................................................................
I/O Pins ..........................................................................................................
I/O Control Registers .......................................................................................

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

Page

984
984
985
986
987
987
987
988
989
989
992

983

Introduction

www.ti.com

11.1 Introduction
The I/O controller configures pins and map peripheral signals to physical pins (DIOx) on the CC26x0 and
CC13x0 packages. This chapter explains the IOC implementation and gives a few examples on how to
map peripheral functions to pins chosen by the user.
Several similar terms that can cause confusion follow:
• Pins are, in this context, defined as everything from the physical metals pads on the outside of the
package, to the last internal analog stage that drives and sense input signals on these lines (see
Figure 11-2.
• PORTID is the number for a peripheral function.
• GPIO is a peripheral function with the PORTID of 0x0.
• DIO (DIO0 to DIO31) are the logic names for the different I/O pins on the specific package.
Table 11-2 provides the mappings between DIO and pin for the different packages. Eight of these
DIOs also have analog capabilities.

11.2 IOC Overview
Figure 11-1 shows a general overview.
The IOC module consists of two main submodules:
• Microcontroller unit IOC (MCU IOC) configures the peripheral ports to the user-defined pins.
• Always-on IOC (AON IOC) module handles JTAG, 32-kHz clock, AON Peripheral, and AUX signals.
The always-on peripherals (RTC, Battery Monitor and internal temperature sensor) can operate even
when the MCU IOC is powered down, but they are clocked from the 32-kHz Low Frequency Clock
(SCLK_LF, see Section 6.5 for more details). This allows the device to operate at very low-power levels
while still maintaining active operation of these peripheral functions. When configured correctly, the AON
IOC ensures that output levels of all the I/Os remain unchanged when the MCU power domain, which
includes the MCU IOC, is powered down (for more details, see Section 11.5).
Figure 11-1. IOC Overview (Simplified)
AON
AON Event

MCU Event
AUX

IRQ

MCU
cfg

MCU AONIF

Latch
di
do

Edge
Detect

di
GPIO

oe_n

IOC

MCU Latch

pin_ctrl
AON

Pinconfig

Pins

CFG

oe_n

MCU

IOC

MUX

Peripherals

di
do
oe_n

AON
PERIPH
AON
Peripherals

AON/AUX MUX

TMS Pin

AUX
Latch

TMS CTRL

AUX

...

bmon_level
DEBUGSS

984

I/O Control

AON BATMON

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Mapping and Configuration

www.ti.com

11.3 I/O Mapping and Configuration
The MCU IOC can map a number of peripheral modules such as GPIO, SSI (SPI), UART, I2C, and I2S to
any of the available I/Os. The peripherals AUX and JTAG are limited to specific I/O pins. Each type of
peripheral signal has a unique PORTID that can be assigned to selected I/O pins (referenced as DIOs).
Table 11-3 lists the different PORTID signals.

11.3.1 Basic I/O Mapping
To map a peripheral function to DIOn, where n can range from 0 to a maximum of 31, the PORTID and
pin configuration must be set in the corresponding IOC:IOCFGn register. To select what kind of function
the pin must be routed, choose the PORTID number for the desired peripheral function and write the
PORTID number to the IOC:IOCFGn.PORTID bit field.
The function can be set by using the following driver library function:
IOCPortConfigureSet(DIOn, PORTID, PIN-CONFIG);
See Section 11.6 to see the kind of configurations that can be set in PIN-CONFIG.

11.3.2 MAP AUXIO From the Sensor Controller to DIO Pin
There are up to 16 signals (AUXIO0 to AUXIO15) in the sensor controller domain (AUX). These signals
can be routed to specific pins given in Table 11-2. AUXIO0 to AUXIO7 have analog capability, but can
also be used as digital I/Os, while AUXIO8 to AUXIO15 are digital only. The signals routed from the
sensor controller domain (AUX) are configured differently than GPIO and other peripheral functions. This
section does not cover the use of all the capabilities of the sensor controller (for more details, see
Chapter 17).
In this example, AUXIO1 is mapped to DIO29 on the 7 × 7 package type and set up as a digital input. The
pin number and DIO number differs for different package types. The module must be powered, and the
clock to the specific module within the AUX domain must be enabled (AIODIO1 for AUXIO0 to AUXIO7).
1. Set the IOC:IOCFG29 PORTID bit field to 0x08 (AUX_I/O) to route AUXIO1 to DIO29.
2. The I/O signals in the AUX domain have their own open-source or open-drain configuration, which
must be set in the AUX_AIODIO:IOMODE register in the AUX domain. Set AUX_AIODIO:IOMODE.IO1
to 0x01 to enable AUXIO1 as a digital input.
3. Enable the digital input buffer for AUXIO1 by setting the IO7_0 bit field to 0x02 in the
AUX_AIODIO0:GPIODIE register.
4. The AUX latch is set to static configuration by default (values from AUXIOs are latched). Release the
latch and set in transparent mode by writing 0x01 to the AUX_WUC:AUXIOLATCH register.
11.3.2.1 Control External LNA/PA (Range Extender) With I/Os
The RF Core has 4 internal logical output signals connected to the IO Controller, named RFC_GPO0 - 3.
These signals can be mapped to DIOs by the IOC and can be assigned various functionality by the RF
Core. Table 11-1 describes the default configuration for the signals which can be used for control of
external RF PA and LNA or RF swtiches. The signals can be mapped to any DIO by setting the relevant
PORTID in the designated IOCFGn register.
NOTE:

On the CC2640R2F the PA enable signal has a flaw in which it does not de-assert when the
internal PA is turned off. It will only go low when the RF Core is shut down. A work-around
for external PA control is to use the TX Start signal instead. This signal will also follow the
internal PA control signal, but will go high approximately 10 us earlier than PA enable.

Table 11-1. RF Core Data Signals for PA and LNA
Port Name

PORTID

RF Core Signal

Description

RFC_GPO0

0x2F

RF Core Data Out 0

LNA enable

RFC_GPO1

0x30

RF Core Data Out 1

PA enable

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

I/O Control 985

I/O Mapping and Configuration

www.ti.com

Table 11-1. RF Core Data Signals for PA and LNA (continued)
Port Name

PORTID

RF Core Signal

Description

RFC_GPO2

0x31

RF Core Data Out 2

Synthesizer calibration running

RFC_GPO3

0x32

RF Core Data Out 3

TX start

11.3.3 Map 32-kHz System Clock (LF Clock) to DIO/PIN
The AON IOC contains the output enable control for the 32-kHz LF system clock output, and the clock
signal has its own PORTID called AON_CLK32K (0x7). This makes it easy to output the clock signal to a
pin. Map the clock to a chosen DIO, and enable the clock output by setting the
AON_IOC:CLK32KCTL.OE_N to 0x0. The following two driverlib calls achieve the same result:

IOCPortConfigureSet(IOIDn, IOC_PORT_AON_CLK32K, IOC_STD_OUTPUT);
AONIOC32kHzOutputEnable();
This outputs the LF system clock signal in all power modes except for shutdown.

11.4 Edge Detection on Pin (DIO)
The AON IOC supports detection of positive and/or negative edges on the digital I/Os and provides the
resulting events to the AON event fabric. The edge-detect event can be cleared by both the MCU GPIO
and the AUX. The edge detect event can also be cleared from MCU IOC by doing a disable or enable
cycle of the edge configuration. The MCU GPIO has a separate clear line to each edge detection cell,
while the AUX uses a single line to clear all events on pins connected to the AUX. When clearing from
AUX, all events related to AUX I/Os are cleared.
The EDGE DETECT block uses an edge-detect cell for each I/O. Each detection cell can flag edgedetected and trigger an interrupt signal. The interrupt signals from all cells are ORed together to form a
single interrupt line toward the AON event fabric.
The AON IOC can also generate an interrupt event when any programmable subset of the input I/Os
generates an event. The registers controlling the edge-detect circuit reside in the MCU IOC, but the values
for the configuration are latched in the MCU latch in the AON IOC.

11.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
Interrupt and edge detect event generation from DIOs is configured through the IOC:IOCFGn
EDGE_IRQ_EN and EDGE_DET bit fields. The DIO must have input enable set in order to perform edge
detection. A GPIO edge-detect event is sent to the CPU interrupt IRQ0 (vector number 16). This interrupt
must be enabled to call the GPIO interrupt handler. In this interrupt handler, the event source must be
cleared by clearing the relevant GPIO:EVFLAGS31 event register DIOn bit. Reading this register returns 1
for triggered events and 0 for non-triggered events. The event is cleared from the MCU IOC by toggling
the enabled EDGE_DET configuration. The event is cleared when the active-edge configuration is
disabled and IOC:IOCFGn.EDGE_DET set to 0.

986

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AON IOC State Latching When Powering Off the MCU Domain

www.ti.com

11.5 AON IOC State Latching When Powering Off the MCU Domain
The I/O configurations and states can be retained when the MCU and/or AUX domain is powered off.
Before powering down the MCU domain, the pin configuration and output values from MCU peripherals
mapped to pins (DIOs) through the MCU IOC must be latched in AON IOC. This is done by disabling the
transparent mode in the AON_IOC:IOLATCH register. Before enabling the transparent mode after MCU is
powered up again, the MCU IOC configuration must be reconfigured to the state it was in before power
down.
If the sensor controller application is using I/Os and simultaneously power cycling the AUX power domain,
the I/O signals must be latched (static configuration). There are latches in AON that latch the signals
coming from AUX to the GPIO pins. The AUX_WUC:AUXIOLATCH register controls this latch. The reset
state of this register is that the latches are closed (in other words, not transparent). Before any IOs can be
used, this latch must be opened by writing 0x1 to the AUX_WUC:AUXIOLATCH register. The latches must
be closed again before powering off the AUX domain. There are more constraints and reliability issues to
consider before powering off a domain; (for more details, refer to Section 17.5).

11.6 Unused I/O Pins
By default, the I/O driver (output) and input buffer (input) are disabled (tri-state mode) at power on or
reset, and thus the I/O pin can safely be left unconnected (floating).
If the I/O pin is placed in the tri-state condition and connected to a node with a different voltage potential;
there might be a small leakage current going through the pin. The same applies to an I/O pin configured
as input, where the pin is connected to a voltage source (for example VDD / 2). The input is then an
undefined value of either
0 or 1.

11.7 GPIO
The MCU GPIO is a general-purpose input/output that drives a number of physical I/O pads. GPIO
supports up to 31 programmable I/O pins. These pins are configured by the IOC module. To modify a
single GPIO output value, use the GPIO:DOUTn registers (see Section 11.11.2). To set up DIO1 as a
GPIO output and toggle the bit, use the following procedure.
1. Map DIO1 as a GPIO output by setting the IOC:IOCFG1.PORT_ID register to 0 (GPIO PORDTID).
2. Ensure DIO1 is set as output by clearing the IOC:IOCFG1.IE bit. More port configurations can also be
set in the IOC:IOCFG1 register (for more details, see Section 11.10.1.2).
3. Set the data output enable bit for DIO1 in GPIO:DOE31_0.DIO1 by issuing a read-modify-write
operation.
4. Toggle the DIO1 output by issuing an XOR operation on the GPIO:DOUT3_0:DIO1 bit with 0x100.
5. Call the following driver library functions:
IOCPinTypeGpioOutput(0x1);
GPIOPinToggle(0x1);

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

987

I/O Pin Mapping

www.ti.com

11.8 I/O Pin Mapping
Table 11-2 shows the I/O pin mapping for different package types.
Table 11-2. CC26x0 and CC13x0 Family Pin Mapping
Package Type
7×7 QFN (RGZ)

988

Sensor Controller

WCSP (YFV)
Pin

DIO

4×4 QFN
(RSM)
Pin

DIO

Drive Strength

Analog
Capable

AUX IO

yes

2 mA / 4 mA

JTAG

DIO

yes

2 mA / 4 mA

yes

2 mA / 4 mA

yes

2 mA / 4 mA

yes

2 mA / 4 mA

yes

2 mA / 4 mA

yes

2 mA / 4 mA

yes

2 mA / 4 mA

2 mA / 4 mA / 8 mA

TDI

2 mA / 4 mA / 8 mA

TDO

2 mA / 4 mA

TCKC

TMSC

2 mA / 4 mA

2 mA / 4 mA / 8 mA

2 mA / 4 mA

5
(1)

5×5 QFN
(RHB)

(1)

WCSP is only
available for
CC2640R2F

CC13x0 does not have DIO0.

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Peripheral PORTIDs

www.ti.com

11.9 Peripheral PORTIDs
Table 11-3 lists the different PORTID signals.
Table 11-3. CC26x0 and CC13x0 Family PORTIDs
ID

Port Name

Port Description

GPIO

Default GPIO usage

1–6

Port Name

Port Description
Reserved

Reserved

MCU_CM3_SWV

CM3 SWV

AON_CLK32K

AON 32-kHz clock pin

MCU_SSI1_RX

SSI 1 Rx pin

AUX_IO

AUX I/O pin

MCU_SSI1_TX

SSI 1 Tx pin

MCU_SSI0_RX

SSI 0 Rx pin

MCU_SSI1_FSS

SSI 1 FSS pin

MCU_SSI0_TX

SSI 0 Tx pin

MCU_SSI1_CLK

SSI 1 CLK pin

MCU_SSI0_FSS

SSI 0 FSS pin

MCU_I2S_AD0

I2S Data 0 pin

MCU_SSI0_CLK

SSI 0 CLK pin

MCU_I2S_AD1

I2S Data 1 pin

MCU_I2C_MSSDA

I2C Data

MCU_I2S_WCLK

I2S WCLK pin

MCU_I2C_MSSCL

I2C Clock

MCU_I2S_BCLK

I2S BCLK pin

MCU_UART0_RX

UART 0 Rx pin

MCU_I2S_MCLK

I2S MCLK pin

MCU_UART0_TX

UART 0 Tx pin

42–45

MCU_UART0_CTS

UART 0 CTS pin

MCU_UART0_RTS

UART 0 RTS pin

RFC_GPO0

19–22

Reserved
RF Core internal signal

Reserved

RFC_GPO1

MCU_GPTM_GPTM0

GMTM timer pin GPTM0

RFC_GPO2

MCU_GPTM_GPTM1

GMTM timer pin GPTM1

RFC_GPO3

MCU_GPTM_GPTM2

GMTM timer pin GPTM2

51–56

MCU_GPTM_GPTM3

GMTM timer pin GPTM3

MCU_GPTM_GPTM4

GMTM timer pin GPTM4

MCU_GPTM_GPTM5

GMTM timer pin GPTM5

MCU_GPTM_GPTM6

GMTM timer pin GPTM6

MCU_GPTM_GPTM7

GMTM timer pin GPTM7

RF Core internal signals

11.10 I/O Pins
This section discusses specific physical details and configuration possibilities for the I/O pins on the
CC26x0 and CC13x0 devices.

11.10.1 Input/Output Modes
Each I/O pin has separate input and output buffers which can be configured independently. The main
configurations for input and output are
• Input mode (detached, hysteresis, pullup, pulldown)
• Output mode (tri-state condition, push-pull, open drain, open source)
Both the input and the output buffer can be enabled or disabled at the same time. By disabling the output
buffer the corresponding I/O pin will be in the tri-state condition (high impedance). If nothing is driving the
I/O to a valid logical level when the output buffer is disabled then disable the input buffer to avoid
excessive current draw through the I/O input buffer. Section 11.10.1.2 covers the I/O pin configuration in
more detail.
11.10.1.1 Physical Pin
The digital I/O driver and receiver is a wide-supply voltage range, bidirectional buffer combining an output
buffer, an input buffer with optional hysteresis, and optional pullup and pulldown circuitry. The I/O has
limited power-management features, including support for wakeup from sleep with core power gated. The
sink and source capability of the pins are symmetrical, as shown in Figure 11-2, which gives a rough
overview of the analog pin stage. Pullup and pulldown resistances are given in the data sheet.
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

989

I/O Pins

www.ti.com

Figure 11-2. Generic I/O Pin (Simplified)
VIO

Pullup Enable

Output Enable (OE)

Pin (DIOx)

Output

Pulldown Enable

Input Enable (IE)

Input

11.10.1.2 Pin Configuration
The IOC lets software configure the pins based on the application requirements. The software can
configure different characteristic settings for any or all of the I/O pins. All of the following features, except
for output driver (output enable set in the GPIO:DOE31_0 register), are controlled in the IOC:IOCFGn
registers:
• Drive Strength (IOC:IOCFGn.IOSTR)
Configures the drive strength and maximum current of an I/O pin. All I/O pins support 2 mA and 4 mA,
while five pins support up to 8 mA. By setting IOC:IOCFGn.IOSTR to 0x0, the drive strength is
automatically updated based upon inputs from the battery monitor, BATMON, to maintain the set drive
strength level at different battery voltages.
• Pull (IOC:IOCFGn.PULL_CTL)
Configures a weak pull on an I/O pin. The following can be set: pullup, pulldown, or no pull. See the
data sheet for specific pullup and pulldown resistance.
• Slew Control (IOC:IOCFGn.SLEW_RED)
Sets high or low slew rate on an I/O pin.
• Hysteresis (IOC:IOCFGn.HYST_EN)
Enables or disables input hysteresis on an I/O pin.
• Open-Source or Open-Drain Configuration (IOC:IOCFGn.IOMODE)
Configures the pin as normal, open source, or open drain; all of these can be set to either inverted or
normal (noninverted).
• Interrupt and Edge Detection (IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET)
Enables interrupt triggered by edge detection on I/O pin. Different edge detection modes are
supported, and the possible modes are rising edge, falling edge, trigger on both rising and falling, or no
edge detection.
• Input Driver (IOC:IOCFGn.IE)
Enables or disables the I/O input driver.
• Output Driver (Depends on specific peripheral mapped to pin)
Enables or disables the I/O output driver.

990

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Pins

www.ti.com

11.10.2 Digital Input/Output Power Domains
The DIO pins are separated into three different voltage domains (the RSM and RHB packages have only
two voltage domains). These power domains are powered by VDDS, VDDS2, and VDDS3 separately and
can have individual voltage levels (refer to the data sheet for details). VDDS is also the main power supply
to the device, in addition to powering a set of pins, which means that for example POR is based on the
voltage on this pin. Note that there is a limitation on VDDS2/3 when using JTAG as noted in the data
sheet. VDDS_DCDC must always be tied to VDDS.
Table 11-4. CC26x0 and CC13x0 DIO Power Domains
4 × 4 VQFN (RSM)
DIO

VDDS

VDDS2

WCSP (YFV)
VDDS

VDDS2

5 × 5 VQFN (RHB)
VDDS

VDDS2

7 × 7 VQFN (RGZ)
VDDS

VDDS2

VDDS3

TMSC

TCKC

Reset

DIO0

DIO1

DIO2

DIO3

DIO4

DIO5

DIO6

DIO7

DIO8

DIO9

DIO10

DIO11

DIO12

DIO13

DIO14
DIO15

DIO16

DIO17

DIO18

DIO19

DIO20

DIO21

DIO22

DIO23

DIO24

DIO25

DIO26

DIO27

DIO28

DIO29

DIO30

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

991

I/O Control Registers

www.ti.com

11.11 I/O Control Registers
11.11.1 AON_IOC Registers
Table 11-5 lists the memory-mapped registers for the AON_IOC. All register offset addresses not listed in
Table 11-5 should be considered as reserved locations and the register contents should not be modified.
Table 11-5. AON_IOC Registers

992

Offset

Acronym

IOSTRMIN

Internal

Section 11.11.1.1

IOSTRMED

Internal

Section 11.11.1.2

IOSTRMAX

Internal

Section 11.11.1.3

IOCLATCH

IO Latch Control

Section 11.11.1.4

10h

CLK32KCTL

SCLK_LF External Output Control

Section 11.11.1.5

I/O Control

Section

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.1.1 IOSTRMIN Register (Offset = 0h) [reset = 3h]
IOSTRMIN is shown in Figure 11-3 and described in Table 11-6.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 11-3. IOSTRMIN Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
0
GRAY_CODE
R/W-3h

Table 11-6. IOSTRMIN Register Field Descriptions
Field

Type

Reset

Description

31-3

Bit

RESERVED

Internal. Only to be used through TI provided API.

2-0

GRAY_CODE

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

993

I/O Control Registers

www.ti.com

11.11.1.2 IOSTRMED Register (Offset = 4h) [reset = 6h]
IOSTRMED is shown in Figure 11-4 and described in Table 11-7.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 11-4. IOSTRMED Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
0
GRAY_CODE
R/W-6h

Table 11-7. IOSTRMED Register Field Descriptions
Bit

994

Field

Type

Reset

Description

31-3

RESERVED

Internal. Only to be used through TI provided API.

2-0

GRAY_CODE

R/W

Internal. Only to be used through TI provided API.

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.1.3 IOSTRMAX Register (Offset = 8h) [reset = 5h]
IOSTRMAX is shown in Figure 11-5 and described in Table 11-8.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 11-5. IOSTRMAX Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
0
GRAY_CODE
R/W-5h

Table 11-8. IOSTRMAX Register Field Descriptions
Field

Type

Reset

Description

31-3

Bit

RESERVED

Internal. Only to be used through TI provided API.

2-0

GRAY_CODE

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

995

I/O Control Registers

www.ti.com

11.11.1.4 IOCLATCH Register (Offset = Ch) [reset = 1h]
IOCLATCH is shown in Figure 11-6 and described in Table 11-9.
Return to Summary Table.
IO Latch Control
Controls transparency of all latches holding I/O or configuration state from the MCU IOC
Figure 11-6. IOCLATCH Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
EN
R/W1h

Table 11-9. IOCLATCH Register Field Descriptions
Bit
31-1
0

996

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Controls latches between MCU IOC and AON_IOC.
The latches are transparent by default.
They must be closed prior to power off the domain(s) controlling the
IOs in order to preserve IO values on external pins.
0h = Latches are static, meaning the current value on the IO pin is
frozen by latches and kept even if GPIO module or a peripheral
module is turned off
1h = Latches are transparent, meaning the value of the IO is directly
controlled by the GPIO or peripheral value

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.1.5 CLK32KCTL Register (Offset = 10h) [reset = 1h]
CLK32KCTL is shown in Figure 11-7 and described in Table 11-10.
Return to Summary Table.
SCLK_LF External Output Control
Figure 11-7. CLK32KCTL Register
31

0
OE_N
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 11-10. CLK32KCTL Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

OE_N

R/W

0: Output enable active. SCLK_LF output on IO pin that has
PORT_ID (e.g. IOC:IOCFG0.PORT_ID) set to AON_CLK32K.
1: Output enable not active

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

997

I/O Control Registers

www.ti.com

11.11.2 GPIO Registers
Table 11-11 lists the memory-mapped registers for the GPIO. All register offset addresses not listed in
Table 11-11 should be considered as reserved locations and the register contents should not be modified.
Table 11-11. GPIO Registers

998

Offset

Acronym

Section

DOUT3_0

Data Out 0 to 3

Section 11.11.2.1

DOUT7_4

Data Out 4 to 7

Section 11.11.2.2

DOUT11_8

Data Out 8 to 11

Section 11.11.2.3

DOUT15_12

Data Out 12 to 15

Section 11.11.2.4

10h

DOUT19_16

Data Out 16 to 19

Section 11.11.2.5

14h

DOUT23_20

Data Out 20 to 23

Section 11.11.2.6

18h

DOUT27_24

Data Out 24 to 27

Section 11.11.2.7

1Ch

DOUT31_28

Data Out 28 to 31

Section 11.11.2.8

80h

DOUT31_0

Data Output for DIO 0 to 31

Section 11.11.2.9

90h

DOUTSET31_0

Data Out Set

Section 11.11.2.10

A0h

DOUTCLR31_0

Data Out Clear

Section 11.11.2.11

B0h

DOUTTGL31_0

Data Out Toggle

Section 11.11.2.12

C0h

DIN31_0

Data Input from DIO 0 to 31

Section 11.11.2.13

D0h

DOE31_0

Data Output Enable for DIO 0 to 31

Section 11.11.2.14

E0h

EVFLAGS31_0

Event Register for DIO 0 to 31

Section 11.11.2.15

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.2.1 DOUT3_0 Register (Offset = 0h) [reset = 0h]
DOUT3_0 is shown in Figure 11-8 and described in Table 11-12.
Return to Summary Table.
Data Out 0 to 3
Alias register for byte access to each bit in DOUT31_0
Figure 11-8. DOUT3_0 Register
31

28
RESERVED
R-0h

24
DIO3
W-0h

20
RESERVED
R-0h

16
DIO2
W-0h

12
RESERVED
R-0h

8
DIO1
W-0h

4
RESERVED
R-0h

0
DIO0
W-0h

Table 11-12. DOUT3_0 Register Field Descriptions
Bit
31-25
24
23-17
16
15-9
8
7-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO3

Sets the state of the pin that is configured as DIO#3, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO2

Sets the state of the pin that is configured as DIO#2, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO1

Sets the state of the pin that is configured as DIO#1, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO0

Sets the state of the pin that is configured as DIO#0, if the
corresponding DOE31_0 bitfield is set.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

999

I/O Control Registers

www.ti.com

11.11.2.2 DOUT7_4 Register (Offset = 4h) [reset = 0h]
DOUT7_4 is shown in Figure 11-9 and described in Table 11-13.
Return to Summary Table.
Data Out 4 to 7
Alias register for byte access to each bit in DOUT31_0
Figure 11-9. DOUT7_4 Register
31

28
RESERVED
R-0h

24
DIO7
W-0h

20
RESERVED
R-0h

16
DIO6
W-0h

12
RESERVED
R-0h

8
DIO5
W-0h

4
RESERVED
R-0h

0
DIO4
W-0h

Table 11-13. DOUT7_4 Register Field Descriptions
Bit
31-25
24
23-17
16
15-9
8
7-1
0

1000

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO7

Sets the state of the pin that is configured as DIO#7, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO6

Sets the state of the pin that is configured as DIO#6, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO5

Sets the state of the pin that is configured as DIO#5, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO4

Sets the state of the pin that is configured as DIO#4, if the
corresponding DOE31_0 bitfield is set.

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.2.3 DOUT11_8 Register (Offset = 8h) [reset = 0h]
DOUT11_8 is shown in Figure 11-10 and described in Table 11-14.
Return to Summary Table.
Data Out 8 to 11
Alias register for byte access to each bit in DOUT31_0
Figure 11-10. DOUT11_8 Register
31

28
RESERVED
R-0h

24
DIO11
W-0h

20
RESERVED
R-0h

16
DIO10
W-0h

12
RESERVED
R-0h

8
DIO9
W-0h

4
RESERVED
R-0h

0
DIO8
W-0h

Table 11-14. DOUT11_8 Register Field Descriptions
Bit
31-25
24
23-17
16
15-9
8
7-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO11

Sets the state of the pin that is configured as DIO#11, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO10

Sets the state of the pin that is configured as DIO#10, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO9

Sets the state of the pin that is configured as DIO#9, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO8

Sets the state of the pin that is configured as DIO#8, if the
corresponding DOE31_0 bitfield is set.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1001

I/O Control Registers

www.ti.com

11.11.2.4 DOUT15_12 Register (Offset = Ch) [reset = 0h]
DOUT15_12 is shown in Figure 11-11 and described in Table 11-15.
Return to Summary Table.
Data Out 12 to 15
Alias register for byte access to each bit in DOUT31_0
Figure 11-11. DOUT15_12 Register
31

28
RESERVED
R-0h

24
DIO15
W-0h

20
RESERVED
R-0h

16
DIO14
W-0h

12
RESERVED
R-0h

8
DIO13
W-0h

4
RESERVED
R-0h

0
DIO12
W-0h

Table 11-15. DOUT15_12 Register Field Descriptions
Bit
31-25
24
23-17
16
15-9
8
7-1
0

1002

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO15

Sets the state of the pin that is configured as DIO#15, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO14

Sets the state of the pin that is configured as DIO#14, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO13

Sets the state of the pin that is configured as DIO#13, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO12

Sets the state of the pin that is configured as DIO#12, if the
corresponding DOE31_0 bitfield is set.

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.2.5 DOUT19_16 Register (Offset = 10h) [reset = 0h]
DOUT19_16 is shown in Figure 11-12 and described in Table 11-16.
Return to Summary Table.
Data Out 16 to 19
Alias register for byte access to each bit in DOUT31_0
Figure 11-12. DOUT19_16 Register
31

28
RESERVED
R-0h

24
DIO19
W-0h

20
RESERVED
R-0h

16
DIO18
W-0h

12
RESERVED
R-0h

8
DIO17
W-0h

4
RESERVED
R-0h

0
DIO16
W-0h

Table 11-16. DOUT19_16 Register Field Descriptions
Bit
31-25
24
23-17
16
15-9
8
7-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO19

Sets the state of the pin that is configured as DIO#19, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO18

Sets the state of the pin that is configured as DIO#18, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO17

Sets the state of the pin that is configured as DIO#17, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO16

Sets the state of the pin that is configured as DIO#16, if the
corresponding DOE31_0 bitfield is set.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1003

I/O Control Registers

www.ti.com

11.11.2.6 DOUT23_20 Register (Offset = 14h) [reset = 0h]
DOUT23_20 is shown in Figure 11-13 and described in Table 11-17.
Return to Summary Table.
Data Out 20 to 23
Alias register for byte access to each bit in DOUT31_0
Figure 11-13. DOUT23_20 Register
31

28
RESERVED
R-0h

24
DIO23
W-0h

20
RESERVED
R-0h

16
DIO22
W-0h

12
RESERVED
R-0h

8
DIO21
W-0h

4
RESERVED
R-0h

0
DIO20
W-0h

Table 11-17. DOUT23_20 Register Field Descriptions
Bit
31-25
24
23-17
16
15-9
8
7-1
0

1004

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO23

Sets the state of the pin that is configured as DIO#23, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO22

Sets the state of the pin that is configured as DIO#22, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO21

Sets the state of the pin that is configured as DIO#21, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO20

Sets the state of the pin that is configured as DIO#20, if the
corresponding DOE31_0 bitfield is set.

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.2.7 DOUT27_24 Register (Offset = 18h) [reset = 0h]
DOUT27_24 is shown in Figure 11-14 and described in Table 11-18.
Return to Summary Table.
Data Out 24 to 27
Alias register for byte access to each bit in DOUT31_0
Figure 11-14. DOUT27_24 Register
31

28
RESERVED
R-0h

24
DIO27
W-0h

20
RESERVED
R-0h

16
DIO26
W-0h

12
RESERVED
R-0h

8
DIO25
W-0h

4
RESERVED
R-0h

0
DIO24
W-0h

Table 11-18. DOUT27_24 Register Field Descriptions
Bit
31-25
24
23-17
16
15-9
8
7-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO27

Sets the state of the pin that is configured as DIO#27, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO26

Sets the state of the pin that is configured as DIO#26, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO25

Sets the state of the pin that is configured as DIO#25, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO24

Sets the state of the pin that is configured as DIO#24, if the
corresponding DOE31_0 bitfield is set.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1005

I/O Control Registers

www.ti.com

11.11.2.8 DOUT31_28 Register (Offset = 1Ch) [reset = 0h]
DOUT31_28 is shown in Figure 11-15 and described in Table 11-19.
Return to Summary Table.
Data Out 28 to 31
Alias register for byte access to each bit in DOUT31_0
Figure 11-15. DOUT31_28 Register
31

28
RESERVED
R-0h

24
DIO31
W-0h

20
RESERVED
R-0h

16
DIO30
W-0h

12
RESERVED
R-0h

8
DIO29
W-0h

4
RESERVED
R-0h

0
DIO28
W-0h

Table 11-19. DOUT31_28 Register Field Descriptions
Bit
31-25
24
23-17
16
15-9
8
7-1
0

1006

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO31

Sets the state of the pin that is configured as DIO#31, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO30

Sets the state of the pin that is configured as DIO#30, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO29

Sets the state of the pin that is configured as DIO#29, if the
corresponding DOE31_0 bitfield is set.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DIO28

Sets the state of the pin that is configured as DIO#28, if the
corresponding DOE31_0 bitfield is set.

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.2.9 DOUT31_0 Register (Offset = 80h) [reset = 0h]
DOUT31_0 is shown in Figure 11-16 and described in Table 11-20.
Return to Summary Table.
Data Output for DIO 0 to 31
Figure 11-16. DOUT31_0 Register
31
DIO31
R/W-0h

30
DIO30
R/W-0h

29
DIO29
R/W-0h

28
DIO28
R/W-0h

27
DIO27
R/W-0h

26
DIO26
R/W-0h

25
DIO25
R/W-0h

24
DIO24
R/W-0h

23
DIO23
R/W-0h

22
DIO22
R/W-0h

21
DIO21
R/W-0h

20
DIO20
R/W-0h

19
DIO19
R/W-0h

18
DIO18
R/W-0h

17
DIO17
R/W-0h

16
DIO16
R/W-0h

15
DIO15
R/W-0h

14
DIO14
R/W-0h

13
DIO13
R/W-0h

12
DIO12
R/W-0h

11
DIO11
R/W-0h

10
DIO10
R/W-0h

9
DIO9
R/W-0h

8
DIO8
R/W-0h

7
DIO7
R/W-0h

6
DIO6
R/W-0h

5
DIO5
R/W-0h

4
DIO4
R/W-0h

3
DIO3
R/W-0h

2
DIO2
R/W-0h

1
DIO1
R/W-0h

0
DIO0
R/W-0h

Table 11-20. DOUT31_0 Register Field Descriptions
Bit

Field

Type

Reset

Description

DIO31

R/W

Data output for DIO 31

DIO30

R/W

Data output for DIO 30

DIO29

R/W

Data output for DIO 29

DIO28

R/W

Data output for DIO 28

DIO27

R/W

Data output for DIO 27

DIO26

R/W

Data output for DIO 26

DIO25

R/W

Data output for DIO 25

DIO24

R/W

Data output for DIO 24

DIO23

R/W

Data output for DIO 23

DIO22

R/W

Data output for DIO 22

DIO21

R/W

Data output for DIO 21

DIO20

R/W

Data output for DIO 20

DIO19

R/W

Data output for DIO 19

DIO18

R/W

Data output for DIO 18

DIO17

R/W

Data output for DIO 17

DIO16

R/W

Data output for DIO 16

DIO15

R/W

Data output for DIO 15

DIO14

R/W

Data output for DIO 14

DIO13

R/W

Data output for DIO 13

DIO12

R/W

Data output for DIO 12

DIO11

R/W

Data output for DIO 11

DIO10

R/W

Data output for DIO 10

DIO9

R/W

Data output for DIO 9

DIO8

R/W

Data output for DIO 8

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1007

I/O Control Registers

www.ti.com

Table 11-20. DOUT31_0 Register Field Descriptions (continued)

1008

Bit

Field

Type

Reset

Description

DIO7

R/W

Data output for DIO 7

DIO6

R/W

Data output for DIO 6

DIO5

R/W

Data output for DIO 5

DIO4

R/W

Data output for DIO 4

DIO3

R/W

Data output for DIO 3

DIO2

R/W

Data output for DIO 2

DIO1

R/W

Data output for DIO 1

DIO0

R/W

Data output for DIO 0

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.2.10 DOUTSET31_0 Register (Offset = 90h) [reset = 0h]
DOUTSET31_0 is shown in Figure 11-17 and described in Table 11-21.
Return to Summary Table.
Data Out Set
Writing 1 to a bit position sets the corresponding bit in the DOUT31_0 register
Figure 11-17. DOUTSET31_0 Register
31
DIO31
W1S-0h

30
DIO30
W1S-0h

29
DIO29
W1S-0h

28
DIO28
W1S-0h

27
DIO27
W1S-0h

26
DIO26
W1S-0h

25
DIO25
W1S-0h

24
DIO24
W1S-0h

23
DIO23
W1S-0h

22
DIO22
W1S-0h

21
DIO21
W1S-0h

20
DIO20
W1S-0h

19
DIO19
W1S-0h

18
DIO18
W1S-0h

17
DIO17
W1S-0h

16
DIO16
W1S-0h

15
DIO15
W1S-0h

14
DIO14
W1S-0h

13
DIO13
W1S-0h

12
DIO12
W1S-0h

11
DIO11
W1S-0h

10
DIO10
W1S-0h

9
DIO9
W1S-0h

8
DIO8
W1S-0h

7
DIO7
W1S-0h

6
DIO6
W1S-0h

5
DIO5
W1S-0h

4
DIO4
W1S-0h

3
DIO3
W1S-0h

2
DIO2
W1S-0h

1
DIO1
W1S-0h

0
DIO0
W1S-0h

Table 11-21. DOUTSET31_0 Register Field Descriptions
Bit

Field

Type

Reset

Description

DIO31

W1S

Set bit 31

DIO30

W1S

Set bit 30

DIO29

W1S

Set bit 29

DIO28

W1S

Set bit 28

DIO27

W1S

Set bit 27

DIO26

W1S

Set bit 26

DIO25

W1S

Set bit 25

DIO24

W1S

Set bit 24

DIO23

W1S

Set bit 23

DIO22

W1S

Set bit 22

DIO21

W1S

Set bit 21

DIO20

W1S

Set bit 20

DIO19

W1S

Set bit 19

DIO18

W1S

Set bit 18

DIO17

W1S

Set bit 17

DIO16

W1S

Set bit 16

DIO15

W1S

Set bit 15

DIO14

W1S

Set bit 14

DIO13

W1S

Set bit 13

DIO12

W1S

Set bit 12

DIO11

W1S

Set bit 11

DIO10

W1S

Set bit 10

DIO9

W1S

Set bit 9

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1009

I/O Control Registers

www.ti.com

Table 11-21. DOUTSET31_0 Register Field Descriptions (continued)

1010

Bit

Field

Type

Reset

Description

DIO8

W1S

Set bit 8

DIO7

W1S

Set bit 7

DIO6

W1S

Set bit 6

DIO5

W1S

Set bit 5

DIO4

W1S

Set bit 4

DIO3

W1S

Set bit 3

DIO2

W1S

Set bit 2

DIO1

W1S

Set bit 1

DIO0

W1S

Set bit 0

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.2.11 DOUTCLR31_0 Register (Offset = A0h) [reset = 0h]
DOUTCLR31_0 is shown in Figure 11-18 and described in Table 11-22.
Return to Summary Table.
Data Out Clear
Writing 1 to a bit position clears the corresponding bit in the DOUT31_0 register
Figure 11-18. DOUTCLR31_0 Register
31
DIO31
W1C-0h

30
DIO30
W1C-0h

29
DIO29
W1C-0h

28
DIO28
W1C-0h

27
DIO27
W1C-0h

26
DIO26
W1C-0h

25
DIO25
W1C-0h

24
DIO24
W1C-0h

23
DIO23
W1C-0h

22
DIO22
W1C-0h

21
DIO21
W1C-0h

20
DIO20
W1C-0h

19
DIO19
W1C-0h

18
DIO18
W1C-0h

17
DIO17
W1C-0h

16
DIO16
W1C-0h

15
DIO15
W1C-0h

14
DIO14
W1C-0h

13
DIO13
W1C-0h

12
DIO12
W1C-0h

11
DIO11
W1C-0h

10
DIO10
W1C-0h

9
DIO9
W1C-0h

8
DIO8
W1C-0h

7
DIO7
W1C-0h

6
DIO6
W1C-0h

5
DIO5
W1C-0h

4
DIO4
W1C-0h

3
DIO3
W1C-0h

2
DIO2
W1C-0h

1
DIO1
W1C-0h

0
DIO0
W1C-0h

Table 11-22. DOUTCLR31_0 Register Field Descriptions
Bit

Field

Type

Reset

Description

DIO31

W1C

Clears bit 31

DIO30

W1C

Clears bit 30

DIO29

W1C

Clears bit 29

DIO28

W1C

Clears bit 28

DIO27

W1C

Clears bit 27

DIO26

W1C

Clears bit 26

DIO25

W1C

Clears bit 25

DIO24

W1C

Clears bit 24

DIO23

W1C

Clears bit 23

DIO22

W1C

Clears bit 22

DIO21

W1C

Clears bit 21

DIO20

W1C

Clears bit 20

DIO19

W1C

Clears bit 19

DIO18

W1C

Clears bit 18

DIO17

W1C

Clears bit 17

DIO16

W1C

Clears bit 16

DIO15

W1C

Clears bit 15

DIO14

W1C

Clears bit 14

DIO13

W1C

Clears bit 13

DIO12

W1C

Clears bit 12

DIO11

W1C

Clears bit 11

DIO10

W1C

Clears bit 10

DIO9

W1C

Clears bit 9

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1011

I/O Control Registers

www.ti.com

Table 11-22. DOUTCLR31_0 Register Field Descriptions (continued)

1012

Bit

Field

Type

Reset

Description

DIO8

W1C

Clears bit 8

DIO7

W1C

Clears bit 7

DIO6

W1C

Clears bit 6

DIO5

W1C

Clears bit 5

DIO4

W1C

Clears bit 4

DIO3

W1C

Clears bit 3

DIO2

W1C

Clears bit 2

DIO1

W1C

Clears bit 1

DIO0

W1C

Clears bit 0

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.2.12 DOUTTGL31_0 Register (Offset = B0h) [reset = 0h]
DOUTTGL31_0 is shown in Figure 11-19 and described in Table 11-23.
Return to Summary Table.
Data Out Toggle
Writing 1 to a bit position will invert the corresponding DIO output.
Figure 11-19. DOUTTGL31_0 Register
31
DIO31
R/W-0h

30
DIO30
R/W-0h

29
DIO29
R/W-0h

28
DIO28
R/W-0h

27
DIO27
R/W-0h

26
DIO26
R/W-0h

25
DIO25
R/W-0h

24
DIO24
R/W-0h

23
DIO23
R/W-0h

22
DIO22
R/W-0h

21
DIO21
R/W-0h

20
DIO20
R/W-0h

19
DIO19
R/W-0h

18
DIO18
R/W-0h

17
DIO17
R/W-0h

16
DIO16
R/W-0h

15
DIO15
R/W-0h

14
DIO14
R/W-0h

13
DIO13
R/W-0h

12
DIO12
R/W-0h

11
DIO11
R/W-0h

10
DIO10
R/W-0h

9
DIO9
R/W-0h

8
DIO8
R/W-0h

7
DIO7
R/W-0h

6
DIO6
R/W-0h

5
DIO5
R/W-0h

4
DIO4
R/W-0h

3
DIO3
R/W-0h

2
DIO2
R/W-0h

1
DIO1
R/W-0h

0
DIO0
R/W-0h

Table 11-23. DOUTTGL31_0 Register Field Descriptions
Bit

Field

Type

Reset

Description

DIO31

R/W

Toggles bit 31

DIO30

R/W

Toggles bit 30

DIO29

R/W

Toggles bit 29

DIO28

R/W

Toggles bit 28

DIO27

R/W

Toggles bit 27

DIO26

R/W

Toggles bit 26

DIO25

R/W

Toggles bit 25

DIO24

R/W

Toggles bit 24

DIO23

R/W

Toggles bit 23

DIO22

R/W

Toggles bit 22

DIO21

R/W

Toggles bit 21

DIO20

R/W

Toggles bit 20

DIO19

R/W

Toggles bit 19

DIO18

R/W

Toggles bit 18

DIO17

R/W

Toggles bit 17

DIO16

R/W

Toggles bit 16

DIO15

R/W

Toggles bit 15

DIO14

R/W

Toggles bit 14

DIO13

R/W

Toggles bit 13

DIO12

R/W

Toggles bit 12

DIO11

R/W

Toggles bit 11

DIO10

R/W

Toggles bit 10

DIO9

R/W

Toggles bit 9

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1013

I/O Control Registers

www.ti.com

Table 11-23. DOUTTGL31_0 Register Field Descriptions (continued)

1014

Bit

Field

Type

Reset

Description

DIO8

R/W

Toggles bit 8

DIO7

R/W

Toggles bit 7

DIO6

R/W

Toggles bit 6

DIO5

R/W

Toggles bit 5

DIO4

R/W

Toggles bit 4

DIO3

R/W

Toggles bit 3

DIO2

R/W

Toggles bit 2

DIO1

R/W

Toggles bit 1

DIO0

R/W

Toggles bit 0

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.2.13 DIN31_0 Register (Offset = C0h) [reset = 0h]
DIN31_0 is shown in Figure 11-20 and described in Table 11-24.
Return to Summary Table.
Data Input from DIO 0 to 31
Figure 11-20. DIN31_0 Register
31
DIO31
R-0h

30
DIO30
R-0h

29
DIO29
R-0h

28
DIO28
R-0h

27
DIO27
R-0h

26
DIO26
R-0h

25
DIO25
R-0h

24
DIO24
R-0h

23
DIO23
R-0h

22
DIO22
R-0h

21
DIO21
R-0h

20
DIO20
R-0h

19
DIO19
R-0h

18
DIO18
R-0h

17
DIO17
R-0h

16
DIO16
R-0h

15
DIO15
R-0h

14
DIO14
R-0h

13
DIO13
R-0h

12
DIO12
R-0h

11
DIO11
R-0h

10
DIO10
R-0h

9
DIO9
R-0h

8
DIO8
R-0h

7
DIO7
R-0h

6
DIO6
R-0h

5
DIO5
R-0h

4
DIO4
R-0h

3
DIO3
R-0h

2
DIO2
R-0h

1
DIO1
R-0h

0
DIO0
R-0h

Table 11-24. DIN31_0 Register Field Descriptions
Bit

Field

Type

Reset

Description

DIO31

Data input from DIO 31

DIO30

Data input from DIO 30

DIO29

Data input from DIO 29

DIO28

Data input from DIO 28

DIO27

Data input from DIO 27

DIO26

Data input from DIO 26

DIO25

Data input from DIO 25

DIO24

Data input from DIO 24

DIO23

Data input from DIO 23

DIO22

Data input from DIO 22

DIO21

Data input from DIO 21

DIO20

Data input from DIO 20

DIO19

Data input from DIO 19

DIO18

Data input from DIO 18

DIO17

Data input from DIO 17

DIO16

Data input from DIO 16

DIO15

Data input from DIO 15

DIO14

Data input from DIO 14

DIO13

Data input from DIO 13

DIO12

Data input from DIO 12

DIO11

Data input from DIO 11

DIO10

Data input from DIO 10

DIO9

Data input from DIO 9

DIO8

Data input from DIO 8

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1015

I/O Control Registers

www.ti.com

Table 11-24. DIN31_0 Register Field Descriptions (continued)

1016

Bit

Field

Type

Reset

Description

DIO7

Data input from DIO 7

DIO6

Data input from DIO 6

DIO5

Data input from DIO 5

DIO4

Data input from DIO 4

DIO3

Data input from DIO 3

DIO2

Data input from DIO 2

DIO1

Data input from DIO 1

DIO0

Data input from DIO 0

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.2.14 DOE31_0 Register (Offset = D0h) [reset = 0h]
DOE31_0 is shown in Figure 11-21 and described in Table 11-25.
Return to Summary Table.
Data Output Enable for DIO 0 to 31
Figure 11-21. DOE31_0 Register
31
DIO31
R/W-0h

30
DIO30
R/W-0h

29
DIO29
R/W-0h

28
DIO28
R/W-0h

27
DIO27
R/W-0h

26
DIO26
R/W-0h

25
DIO25
R/W-0h

24
DIO24
R/W-0h

23
DIO23
R/W-0h

22
DIO22
R/W-0h

21
DIO21
R/W-0h

20
DIO20
R/W-0h

19
DIO19
R/W-0h

18
DIO18
R/W-0h

17
DIO17
R/W-0h

16
DIO16
R/W-0h

15
DIO15
R/W-0h

14
DIO14
R/W-0h

13
DIO13
R/W-0h

12
DIO12
R/W-0h

11
DIO11
R/W-0h

10
DIO10
R/W-0h

9
DIO9
R/W-0h

8
DIO8
R/W-0h

7
DIO7
R/W-0h

6
DIO6
R/W-0h

5
DIO5
R/W-0h

4
DIO4
R/W-0h

3
DIO3
R/W-0h

2
DIO2
R/W-0h

1
DIO1
R/W-0h

0
DIO0
R/W-0h

Table 11-25. DOE31_0 Register Field Descriptions
Bit

Field

Type

Reset

Description

DIO31

R/W

Data output enable for DIO 31

DIO30

R/W

Data output enable for DIO 30

DIO29

R/W

Data output enable for DIO 29

DIO28

R/W

Data output enable for DIO 28

DIO27

R/W

Data output enable for DIO 27

DIO26

R/W

Data output enable for DIO 26

DIO25

R/W

Data output enable for DIO 25

DIO24

R/W

Data output enable for DIO 24

DIO23

R/W

Data output enable for DIO 23

DIO22

R/W

Data output enable for DIO 22

DIO21

R/W

Data output enable for DIO 21

DIO20

R/W

Data output enable for DIO 20

DIO19

R/W

Data output enable for DIO 19

DIO18

R/W

Data output enable for DIO 18

DIO17

R/W

Data output enable for DIO 17

DIO16

R/W

Data output enable for DIO 16

DIO15

R/W

Data output enable for DIO 15

DIO14

R/W

Data output enable for DIO 14

DIO13

R/W

Data output enable for DIO 13

DIO12

R/W

Data output enable for DIO 12

DIO11

R/W

Data output enable for DIO 11

DIO10

R/W

Data output enable for DIO 10

DIO9

R/W

Data output enable for DIO 9

DIO8

R/W

Data output enable for DIO 8

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1017

I/O Control Registers

www.ti.com

Table 11-25. DOE31_0 Register Field Descriptions (continued)

1018

Bit

Field

Type

Reset

Description

DIO7

R/W

Data output enable for DIO 7

DIO6

R/W

Data output enable for DIO 6

DIO5

R/W

Data output enable for DIO 5

DIO4

R/W

Data output enable for DIO 4

DIO3

R/W

Data output enable for DIO 3

DIO2

R/W

Data output enable for DIO 2

DIO1

R/W

Data output enable for DIO 1

DIO0

R/W

Data output enable for DIO 0

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

11.11.2.15 EVFLAGS31_0 Register (Offset = E0h) [reset = 0h]
EVFLAGS31_0 is shown in Figure 11-22 and described in Table 11-26.
Return to Summary Table.
Event Register for DIO 0 to 31
Reading this registers will return 1 for triggered event and 0 for non-triggered events.
Writing a 1 to a bit field will clear the event.
The configuration of events is done inside MCU IOC, e.g. events for DIO #0 is configured in
IOC:IOCFG0.EDGE_DET and IOC:IOCFG0.EDGE_IRQ_EN.
Figure 11-22. EVFLAGS31_0 Register
31
DIO31
R/W1C-0h

30
DIO30
R/W1C-0h

29
DIO29
R/W1C-0h

28
DIO28
R/W1C-0h

27
DIO27
R/W1C-0h

26
DIO26
R/W1C-0h

25
DIO25
R/W1C-0h

24
DIO24
R/W1C-0h

23
DIO23
R/W1C-0h

22
DIO22
R/W1C-0h

21
DIO21
R/W1C-0h

20
DIO20
R/W1C-0h

19
DIO19
R/W1C-0h

18
DIO18
R/W1C-0h

17
DIO17
R/W1C-0h

16
DIO16
R/W1C-0h

15
DIO15
R/W1C-0h

14
DIO14
R/W1C-0h

13
DIO13
R/W1C-0h

12
DIO12
R/W1C-0h

11
DIO11
R/W1C-0h

10
DIO10
R/W1C-0h

9
DIO9
R/W1C-0h

8
DIO8
R/W1C-0h

7
DIO7
R/W1C-0h

6
DIO6
R/W1C-0h

5
DIO5
R/W1C-0h

4
DIO4
R/W1C-0h

3
DIO3
R/W1C-0h

2
DIO2
R/W1C-0h

1
DIO1
R/W1C-0h

0
DIO0
R/W1C-0h

Table 11-26. EVFLAGS31_0 Register Field Descriptions
Bit

Field

Type

Reset

Description

DIO31

R/W1C

Event for DIO 31

DIO30

R/W1C

Event for DIO 30

DIO29

R/W1C

Event for DIO 29

DIO28

R/W1C

Event for DIO 28

DIO27

R/W1C

Event for DIO 27

DIO26

R/W1C

Event for DIO 26

DIO25

R/W1C

Event for DIO 25

DIO24

R/W1C

Event for DIO 24

DIO23

R/W1C

Event for DIO 23

DIO22

R/W1C

Event for DIO 22

DIO21

R/W1C

Event for DIO 21

DIO20

R/W1C

Event for DIO 20

DIO19

R/W1C

Event for DIO 19

DIO18

R/W1C

Event for DIO 18

DIO17

R/W1C

Event for DIO 17

DIO16

R/W1C

Event for DIO 16

DIO15

R/W1C

Event for DIO 15

DIO14

R/W1C

Event for DIO 14

DIO13

R/W1C

Event for DIO 13

DIO12

R/W1C

Event for DIO 12

DIO11

R/W1C

Event for DIO 11

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1019

I/O Control Registers

www.ti.com

Table 11-26. EVFLAGS31_0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

DIO10

R/W1C

Event for DIO 10

DIO9

R/W1C

Event for DIO 9

DIO8

R/W1C

Event for DIO 8

DIO7

R/W1C

Event for DIO 7

DIO6

R/W1C

Event for DIO 6

DIO5

R/W1C

Event for DIO 5

DIO4

R/W1C

Event for DIO 4

DIO3

R/W1C

Event for DIO 3

DIO2

R/W1C

Event for DIO 2

DIO1

R/W1C

Event for DIO 1

DIO0

R/W1C

Event for DIO 0

11.11.3 IOC Registers
Table 11-27 lists the memory-mapped registers for the IOC. All register offset addresses not listed in
Table 11-27 should be considered as reserved locations and the register contents should not be modified.
Table 11-27. IOC Registers
Offset

1020

Acronym

IOCFG0

Configuration of DIO0

Section 11.11.3.1

Section

IOCFG1

Configuration of DIO1

Section 11.11.3.2

IOCFG2

Configuration of DIO2

Section 11.11.3.3

IOCFG3

Configuration of DIO3

Section 11.11.3.4

10h

IOCFG4

Configuration of DIO4

Section 11.11.3.5

14h

IOCFG5

Configuration of DIO5

Section 11.11.3.6

18h

IOCFG6

Configuration of DIO6

Section 11.11.3.7

1Ch

IOCFG7

Configuration of DIO7

Section 11.11.3.8

20h

IOCFG8

Configuration of DIO8

Section 11.11.3.9

24h

IOCFG9

Configuration of DIO9

Section 11.11.3.10

28h

IOCFG10

Configuration of DIO10

Section 11.11.3.11

2Ch

IOCFG11

Configuration of DIO11

Section 11.11.3.12

30h

IOCFG12

Configuration of DIO12

Section 11.11.3.13

34h

IOCFG13

Configuration of DIO13

Section 11.11.3.14

38h

IOCFG14

Configuration of DIO14

Section 11.11.3.15

3Ch

IOCFG15

Configuration of DIO15

Section 11.11.3.16

40h

IOCFG16

Configuration of DIO16

Section 11.11.3.17

44h

IOCFG17

Configuration of DIO17

Section 11.11.3.18

48h

IOCFG18

Configuration of DIO18

Section 11.11.3.19

4Ch

IOCFG19

Configuration of DIO19

Section 11.11.3.20

50h

IOCFG20

Configuration of DIO20

Section 11.11.3.21

54h

IOCFG21

Configuration of DIO21

Section 11.11.3.22

58h

IOCFG22

Configuration of DIO22

Section 11.11.3.23

5Ch

IOCFG23

Configuration of DIO23

Section 11.11.3.24

60h

IOCFG24

Configuration of DIO24

Section 11.11.3.25

64h

IOCFG25

Configuration of DIO25

Section 11.11.3.26

68h

IOCFG26

Configuration of DIO26

Section 11.11.3.27

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-27. IOC Registers (continued)
Offset

Acronym

6Ch

IOCFG27

Configuration of DIO27

Section 11.11.3.28

70h

IOCFG28

Configuration of DIO28

Section 11.11.3.29

74h

IOCFG29

Configuration of DIO29

Section 11.11.3.30

78h

IOCFG30

Configuration of DIO30

Section 11.11.3.31

7Ch

IOCFG31

Configuration of DIO31

Section 11.11.3.32

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Section

I/O Control

1021

I/O Control Registers

www.ti.com

11.11.3.1 IOCFG0 Register (Offset = 0h) [reset = 6000h]
IOCFG0 is shown in Figure 11-23 and described in Table 11-28.
Return to Summary Table.
Configuration of DIO0
Figure 11-23. IOCFG0 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-28. IOCFG0 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

If DIO is configured GPIO or non-AON peripheral signals, i.e.
PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX ie. PORT_ID
0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable
for the DIO.

28-27

1022

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-28. IOCFG0 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / outut
7h = OPENSRC_INV : Open Source
Inverted input/output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to
AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set
to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double
drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to
AUTO

9-8

IOSTR

R/W

Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC)
mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based
on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN
(min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by
AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX
(min 2 mA @1.8V with default values)

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1023

I/O Control Registers

www.ti.com

Table 11-28. IOCFG0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO0
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1024

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-28. IOCFG0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1025

I/O Control Registers

www.ti.com

11.11.3.2 IOCFG1 Register (Offset = 4h) [reset = 6000h]
IOCFG1 is shown in Figure 11-24 and described in Table 11-29.
Return to Summary Table.
Configuration of DIO1
Figure 11-24. IOCFG1 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-29. IOCFG1 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1026

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-29. IOCFG1 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1027

I/O Control Registers

www.ti.com

Table 11-29. IOCFG1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO1
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1028

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-29. IOCFG1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1029

I/O Control Registers

www.ti.com

11.11.3.3 IOCFG2 Register (Offset = 8h) [reset = 6000h]
IOCFG2 is shown in Figure 11-25 and described in Table 11-30.
Return to Summary Table.
Configuration of DIO2
Figure 11-25. IOCFG2 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-30. IOCFG2 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1030

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-30. IOCFG2 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1031

I/O Control Registers

www.ti.com

Table 11-30. IOCFG2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO2
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1032

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-30. IOCFG2 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1033

I/O Control Registers

www.ti.com

11.11.3.4 IOCFG3 Register (Offset = Ch) [reset = 6000h]
IOCFG3 is shown in Figure 11-26 and described in Table 11-31.
Return to Summary Table.
Configuration of DIO3
Figure 11-26. IOCFG3 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-31. IOCFG3 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1034

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-31. IOCFG3 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1035

I/O Control Registers

www.ti.com

Table 11-31. IOCFG3 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO3
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1036

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-31. IOCFG3 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1037

I/O Control Registers

www.ti.com

11.11.3.5 IOCFG4 Register (Offset = 10h) [reset = 6000h]
IOCFG4 is shown in Figure 11-27 and described in Table 11-32.
Return to Summary Table.
Configuration of DIO4
Figure 11-27. IOCFG4 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-32. IOCFG4 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1038

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-32. IOCFG4 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1039

I/O Control Registers

www.ti.com

Table 11-32. IOCFG4 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO4
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1040

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-32. IOCFG4 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1041

I/O Control Registers

www.ti.com

11.11.3.6 IOCFG5 Register (Offset = 14h) [reset = 6000h]
IOCFG5 is shown in Figure 11-28 and described in Table 11-33.
Return to Summary Table.
Configuration of DIO5
Figure 11-28. IOCFG5 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-33. IOCFG5 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1042

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-33. IOCFG5 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1043

I/O Control Registers

www.ti.com

Table 11-33. IOCFG5 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO5
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1044

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-33. IOCFG5 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1045

I/O Control Registers

www.ti.com

11.11.3.7 IOCFG6 Register (Offset = 18h) [reset = 6000h]
IOCFG6 is shown in Figure 11-29 and described in Table 11-34.
Return to Summary Table.
Configuration of DIO6
Figure 11-29. IOCFG6 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-34. IOCFG6 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1046

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-34. IOCFG6 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1047

I/O Control Registers

www.ti.com

Table 11-34. IOCFG6 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO6
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1048

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-34. IOCFG6 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1049

I/O Control Registers

www.ti.com

11.11.3.8 IOCFG7 Register (Offset = 1Ch) [reset = 6000h]
IOCFG7 is shown in Figure 11-30 and described in Table 11-35.
Return to Summary Table.
Configuration of DIO7
Figure 11-30. IOCFG7 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-35. IOCFG7 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1050

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-35. IOCFG7 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1051

I/O Control Registers

www.ti.com

Table 11-35. IOCFG7 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO7
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1052

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-35. IOCFG7 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1053

I/O Control Registers

www.ti.com

11.11.3.9 IOCFG8 Register (Offset = 20h) [reset = 6000h]
IOCFG8 is shown in Figure 11-31 and described in Table 11-36.
Return to Summary Table.
Configuration of DIO8
Figure 11-31. IOCFG8 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-36. IOCFG8 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1054

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-36. IOCFG8 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1055

I/O Control Registers

www.ti.com

Table 11-36. IOCFG8 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO8
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1056

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-36. IOCFG8 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1057

I/O Control Registers

www.ti.com

11.11.3.10 IOCFG9 Register (Offset = 24h) [reset = 6000h]
IOCFG9 is shown in Figure 11-32 and described in Table 11-37.
Return to Summary Table.
Configuration of DIO9
Figure 11-32. IOCFG9 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-37. IOCFG9 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1058

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-37. IOCFG9 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1059

I/O Control Registers

www.ti.com

Table 11-37. IOCFG9 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO9
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1060

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-37. IOCFG9 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1061

I/O Control Registers

www.ti.com

11.11.3.11 IOCFG10 Register (Offset = 28h) [reset = 6000h]
IOCFG10 is shown in Figure 11-33 and described in Table 11-38.
Return to Summary Table.
Configuration of DIO10
Figure 11-33. IOCFG10 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-38. IOCFG10 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1062

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-38. IOCFG10 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1063

I/O Control Registers

www.ti.com

Table 11-38. IOCFG10 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO10
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1064

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-38. IOCFG10 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1065

I/O Control Registers

www.ti.com

11.11.3.12 IOCFG11 Register (Offset = 2Ch) [reset = 6000h]
IOCFG11 is shown in Figure 11-34 and described in Table 11-39.
Return to Summary Table.
Configuration of DIO11
Figure 11-34. IOCFG11 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-39. IOCFG11 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1066

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-39. IOCFG11 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1067

I/O Control Registers

www.ti.com

Table 11-39. IOCFG11 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO11
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1068

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-39. IOCFG11 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1069

I/O Control Registers

www.ti.com

11.11.3.13 IOCFG12 Register (Offset = 30h) [reset = 6000h]
IOCFG12 is shown in Figure 11-35 and described in Table 11-40.
Return to Summary Table.
Configuration of DIO12
Figure 11-35. IOCFG12 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-40. IOCFG12 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1070

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-40. IOCFG12 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1071

I/O Control Registers

www.ti.com

Table 11-40. IOCFG12 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO12
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1072

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-40. IOCFG12 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1073

I/O Control Registers

www.ti.com

11.11.3.14 IOCFG13 Register (Offset = 34h) [reset = 6000h]
IOCFG13 is shown in Figure 11-36 and described in Table 11-41.
Return to Summary Table.
Configuration of DIO13
Figure 11-36. IOCFG13 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-41. IOCFG13 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1074

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-41. IOCFG13 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1075

I/O Control Registers

www.ti.com

Table 11-41. IOCFG13 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO13
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1076

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-41. IOCFG13 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1077

I/O Control Registers

www.ti.com

11.11.3.15 IOCFG14 Register (Offset = 38h) [reset = 6000h]
IOCFG14 is shown in Figure 11-37 and described in Table 11-42.
Return to Summary Table.
Configuration of DIO14
Figure 11-37. IOCFG14 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-42. IOCFG14 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1078

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-42. IOCFG14 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1079

I/O Control Registers

www.ti.com

Table 11-42. IOCFG14 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO14
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1080

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-42. IOCFG14 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1081

I/O Control Registers

www.ti.com

11.11.3.16 IOCFG15 Register (Offset = 3Ch) [reset = 6000h]
IOCFG15 is shown in Figure 11-38 and described in Table 11-43.
Return to Summary Table.
Configuration of DIO15
Figure 11-38. IOCFG15 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-43. IOCFG15 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1082

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-43. IOCFG15 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1083

I/O Control Registers

www.ti.com

Table 11-43. IOCFG15 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO15
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1084

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-43. IOCFG15 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1085

I/O Control Registers

www.ti.com

11.11.3.17 IOCFG16 Register (Offset = 40h) [reset = 00086000h]
IOCFG16 is shown in Figure 11-39 and described in Table 11-44.
Return to Summary Table.
Configuration of DIO16
Figure 11-39. IOCFG16 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-1h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-44. IOCFG16 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1086

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-44. IOCFG16 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1087

I/O Control Registers

www.ti.com

Table 11-44. IOCFG16 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO16
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1088

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-44. IOCFG16 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1089

I/O Control Registers

www.ti.com

11.11.3.18 IOCFG17 Register (Offset = 44h) [reset = 00106000h]
IOCFG17 is shown in Figure 11-40 and described in Table 11-45.
Return to Summary Table.
Configuration of DIO17
Figure 11-40. IOCFG17 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-2h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-45. IOCFG17 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1090

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-45. IOCFG17 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1091

I/O Control Registers

www.ti.com

Table 11-45. IOCFG17 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO17
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1092

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-45. IOCFG17 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1093

I/O Control Registers

www.ti.com

11.11.3.19 IOCFG18 Register (Offset = 48h) [reset = 6000h]
IOCFG18 is shown in Figure 11-41 and described in Table 11-46.
Return to Summary Table.
Configuration of DIO18
Figure 11-41. IOCFG18 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-46. IOCFG18 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1094

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-46. IOCFG18 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1095

I/O Control Registers

www.ti.com

Table 11-46. IOCFG18 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO18
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1096

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-46. IOCFG18 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1097

I/O Control Registers

www.ti.com

11.11.3.20 IOCFG19 Register (Offset = 4Ch) [reset = 6000h]
IOCFG19 is shown in Figure 11-42 and described in Table 11-47.
Return to Summary Table.
Configuration of DIO19
Figure 11-42. IOCFG19 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-47. IOCFG19 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1098

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-47. IOCFG19 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1099

I/O Control Registers

www.ti.com

Table 11-47. IOCFG19 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO19
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1100

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-47. IOCFG19 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1101

I/O Control Registers

www.ti.com

11.11.3.21 IOCFG20 Register (Offset = 50h) [reset = 6000h]
IOCFG20 is shown in Figure 11-43 and described in Table 11-48.
Return to Summary Table.
Configuration of DIO20
Figure 11-43. IOCFG20 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-48. IOCFG20 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1102

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-48. IOCFG20 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1103

I/O Control Registers

www.ti.com

Table 11-48. IOCFG20 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO20
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1104

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-48. IOCFG20 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1105

I/O Control Registers

www.ti.com

11.11.3.22 IOCFG21 Register (Offset = 54h) [reset = 6000h]
IOCFG21 is shown in Figure 11-44 and described in Table 11-49.
Return to Summary Table.
Configuration of DIO21
Figure 11-44. IOCFG21 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-49. IOCFG21 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1106

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-49. IOCFG21 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1107

I/O Control Registers

www.ti.com

Table 11-49. IOCFG21 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO21
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1108

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-49. IOCFG21 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1109

I/O Control Registers

www.ti.com

11.11.3.23 IOCFG22 Register (Offset = 58h) [reset = 6000h]
IOCFG22 is shown in Figure 11-45 and described in Table 11-50.
Return to Summary Table.
Configuration of DIO22
Figure 11-45. IOCFG22 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-50. IOCFG22 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1110

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-50. IOCFG22 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1111

I/O Control Registers

www.ti.com

Table 11-50. IOCFG22 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO22
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1112

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-50. IOCFG22 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1113

I/O Control Registers

www.ti.com

11.11.3.24 IOCFG23 Register (Offset = 5Ch) [reset = 6000h]
IOCFG23 is shown in Figure 11-46 and described in Table 11-51.
Return to Summary Table.
Configuration of DIO23
Figure 11-46. IOCFG23 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-51. IOCFG23 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1114

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-51. IOCFG23 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1115

I/O Control Registers

www.ti.com

Table 11-51. IOCFG23 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO23
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1116

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-51. IOCFG23 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1117

I/O Control Registers

www.ti.com

11.11.3.25 IOCFG24 Register (Offset = 60h) [reset = 6000h]
IOCFG24 is shown in Figure 11-47 and described in Table 11-52.
Return to Summary Table.
Configuration of DIO24
Figure 11-47. IOCFG24 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-52. IOCFG24 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1118

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-52. IOCFG24 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1119

I/O Control Registers

www.ti.com

Table 11-52. IOCFG24 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO24
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1120

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-52. IOCFG24 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1121

I/O Control Registers

www.ti.com

11.11.3.26 IOCFG25 Register (Offset = 64h) [reset = 6000h]
IOCFG25 is shown in Figure 11-48 and described in Table 11-53.
Return to Summary Table.
Configuration of DIO25
Figure 11-48. IOCFG25 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-53. IOCFG25 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1122

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-53. IOCFG25 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1123

I/O Control Registers

www.ti.com

Table 11-53. IOCFG25 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO25
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1124

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-53. IOCFG25 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1125

I/O Control Registers

www.ti.com

11.11.3.27 IOCFG26 Register (Offset = 68h) [reset = 6000h]
IOCFG26 is shown in Figure 11-49 and described in Table 11-54.
Return to Summary Table.
Configuration of DIO26
Figure 11-49. IOCFG26 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-54. IOCFG26 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1126

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-54. IOCFG26 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1127

I/O Control Registers

www.ti.com

Table 11-54. IOCFG26 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO26
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1128

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-54. IOCFG26 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1129

I/O Control Registers

www.ti.com

11.11.3.28 IOCFG27 Register (Offset = 6Ch) [reset = 6000h]
IOCFG27 is shown in Figure 11-50 and described in Table 11-55.
Return to Summary Table.
Configuration of DIO27
Figure 11-50. IOCFG27 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-55. IOCFG27 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1130

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-55. IOCFG27 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1131

I/O Control Registers

www.ti.com

Table 11-55. IOCFG27 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO27
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1132

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-55. IOCFG27 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1133

I/O Control Registers

www.ti.com

11.11.3.29 IOCFG28 Register (Offset = 70h) [reset = 6000h]
IOCFG28 is shown in Figure 11-51 and described in Table 11-56.
Return to Summary Table.
Configuration of DIO28
Figure 11-51. IOCFG28 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-56. IOCFG28 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1134

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-56. IOCFG28 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1135

I/O Control Registers

www.ti.com

Table 11-56. IOCFG28 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO28
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1136

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-56. IOCFG28 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1137

I/O Control Registers

www.ti.com

11.11.3.30 IOCFG29 Register (Offset = 74h) [reset = 6000h]
IOCFG29 is shown in Figure 11-52 and described in Table 11-57.
Return to Summary Table.
Configuration of DIO29
Figure 11-52. IOCFG29 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-57. IOCFG29 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1138

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-57. IOCFG29 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1139

I/O Control Registers

www.ti.com

Table 11-57. IOCFG29 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO29
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1140

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-57. IOCFG29 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1141

I/O Control Registers

www.ti.com

11.11.3.31 IOCFG30 Register (Offset = 78h) [reset = 6000h]
IOCFG30 is shown in Figure 11-53 and described in Table 11-58.
Return to Summary Table.
Configuration of DIO30
Figure 11-53. IOCFG30 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-58. IOCFG30 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1142

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-58. IOCFG30 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1143

I/O Control Registers

www.ti.com

Table 11-58. IOCFG30 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO30
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1144

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-58. IOCFG30 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1145

I/O Control Registers

www.ti.com

11.11.3.32 IOCFG31 Register (Offset = 7Ch) [reset = 6000h]
IOCFG31 is shown in Figure 11-54 and described in Table 11-59.
Return to Summary Table.
Configuration of DIO31
Figure 11-54. IOCFG31 Register
31
RESERVED
R-0h

30
HYST_EN
R/W-0h

29
IE
R/W-0h

21
RESERVED
R/W-0h

12
SLEW_RED
R/W-0h

15
RESERVED
R-0h

PULL_CTL
R/W-3h

25
IOMODE
R/W-0h

18
EDGE_IRQ_EN
R/W-0h

WU_CFG
R/W-0h

RESERVED
R-0h

EDGE_DET
R/W-0h

IOCURR
R/W-0h

8
IOSTR
R/W-0h

PORT_ID
R/W-0h

Table 11-59. IOCFG31 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

HYST_EN

R/W

0: Input hysteresis disable
1: Input hysteresis enable

R/W

0: Input disabled
1: Input enabled
Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will
be ignored.

WU_CFG

R/W

28-27

1146

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-59. IOCFG31 Register Field Descriptions (continued)
Bit
26-24

Field

Type

Reset

Description

IOMODE

R/W

IO Mode
N/A for IO configured for AON periph. signals and AUX ie. PORT_ID
0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output

23-19

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

EDGE_IRQ_EN

R/W

0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if
EDGE_DET is enabled)

17-16

EDGE_DET

R/W

Enable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

14-13

PULL_CTL

R/W

Pull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull

SLEW_RED

R/W

0: Normal slew rate
1: Enables reduced slew rate in output driver.

IOCURR

R/W

9-8

IOSTR

R/W

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control

1147

I/O Control Registers

www.ti.com

Table 11-59. IOCFG31 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

5-0

PORT_ID

R/W

Selects usage for DIO31
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SSI0_RX : SSI0 RX
Ah = SSI0_TX : SSI0 TX
Bh = SSI0_FSS : SSI0 FSS
Ch = SSI0_CLK : SSI0 CLK
Dh = I2C_MSSDA : I2C Data
Eh = I2C_MSSCL : I2C Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it via
registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV,
EVENT:UDMACH14BSEL.EV, etc
20h = CPU_SWV : CPU SWV
21h = SSI1_RX : SSI1 RX
22h = SSI1_TX : SSI1 TX
23h = SSI1_FSS : SSI1 FSS
24h = SSI1_CLK : SSI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0

1148

I/O Control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Control Registers

www.ti.com

Table 11-59. IOCFG31 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description
30h = RF Core
31h = RF Core
32h = RF Core
33h = RF Core
34h = RF Core
35h = RF Core
36h = RF Core
37h = RF Core
38h = RF Core

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Out 1
Data Out 2
Data Out 3
Data In 0
Data In 1
SMI Data Link Out
SMI Data Link In
SMI Command Link Out
SMI Command Link In

I/O Control

1149

Chapter 12
SWCU117G – February 2015 – Revised February 2017

Micro Direct Memory Access (µDMA)
This chapter describes the direct memory access (DMA) controller, known as DMA.
Topic

12.1
12.2
12.3
12.4
12.5

1150

...........................................................................................................................
DMA Introduction ..........................................................................................
Block Diagram ................................................................................................
Functional Description ....................................................................................
Initialization and Configuration .........................................................................
µDMA Registers ..............................................................................................

Micro Direct Memory Access (µDMA)

Page

1151
1152
1152
1165
1167

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

DMA Introduction

www.ti.com

12.1

DMA Introduction
The CC26x0 and CC13x0 microcontroller includes a direct memory access (DMA) controller, known as
DMA. The DMA controller provides a way to offload data transfer tasks from the Cortex®-M3 processor,
allowing for more efficient use of the processor and the available bus bandwidth. The DMA controller can
perform transfers between memory and peripherals. The controller has dedicated channels for each
supported on-chip module, and can be programmed to automatically perform transfers between
peripherals and memory as the peripheral is ready to transfer more data. The DMA controller provides
the following features:
• ARM PrimeCell® 32-channel configurable µDMA controller
• Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer
modes:
– Basic for simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
• Highly flexible and configurable channel operation:
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules
– Primary and secondary channel assignments
– Flexible channel assignments
– One channel each for receive and transmit paths for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable priority scheme
– Optional software-initiated requests for any channel
• Two levels of priority
• Data sizes of 8, 16, and 32 bits
• Transfer size is programmable in binary steps from 1 to 1024
• Source and destination address increment size of byte, halfword, word, or no increment
• Maskable peripheral requests
• Interrupt on transfer completion with a separate interrupt per channel

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1151

Block Diagram

www.ti.com

12.2 Block Diagram
Figure 12-1 shows the DMA block diagram.
Figure 12-1. DMA Block Diagram
Peripheral N
Done
Registers

µDMA controller

Active
Control / STATUS
Status
CFG

Interrupt

Request event

CTRL
ALTCTRL

System Memory

ControlWAITONREQ
/ Status
SOFTREQ
SETBURST
Transfer buffers used by µDMA
CLEARBURST

Event fabric

Control
/ Status
SETREQMASK
UDMACHx burst req
UDMACHx single req

CLEARREQMASK
STECHANNELEN
CLEARCHANNELEN

Nested vector
interrupt controller
NVIC

Control
/ Status
SETCHNLPRIALT
CPUIRQ
CLEARCHNLPRIALT
SETCHNLPRIORITY
CLEARCHNLPRIORITY

CPU

Control / ERROR
Status
REQDONE
DONEMASK

12.3 Functional Description
The DMA controller is a flexible and highly configurable DMA controller designed to work efficiently with
the microcontroller Cortex-M3 processor core. The controller supports multiple data sizes and address
increment schemes, multiple levels of priority among DMA channels, and several transfer modes to allow
for sophisticated programmed data transfers.
Each supported peripheral function has a dedicated channel on the DMA controller that can be
configured independently. The DMA controller implements a configuration method using channel control
structures maintained in system memory by the processor. While simple transfer modes are supported, it
is also possible to build up sophisticated task lists in memory that allow the DMA controller to perform
arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. The DMA
controller also supports the use of ping-pong buffering to accommodate constant streaming of data to or
from a peripheral.
Each channel also has a configurable arbitration size. The arbitration size is the number of items that are
transferred in a burst before the DMA controller requests channel priority. Using the arbitration size, it is
possible to control exactly how many items are transferred to or from a peripheral every time a DMA
service request is made.

1152

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

12.3.1 Channel Assignments
Table 12-1 lists DMA channel assignments to peripherals.
Table 12-1. Channel Assignments
dma
_done

dma
_active

DMA_CHANNEL
_WITH_2STAGE_SYNC

yes

DMA_PROG

AON_PROG2

GPT1_B

yes

GPT1_A

yes

GPT0_B

yes

GPT0_A

yes

AUX_SW

AUX_ADC

yes

Reserved

yes

Reserved

yes

SSP0_TX

yes

SSP0_RX

yes

UART0_TX

yes

UART0_RX

yes

0 (1)

Software 0

Channel

(1)

map
_wiatonreq

Peripheral

waitonreq

stall

21-31

Reserved

20 (1)

Software 3

19 (1)

Software 2

18 (1)

Software 1

yes

SSP1_TX

yes

SSP1_RX

yes

AON_RTC

DMA
_ACTIVE_FF

yes

DMA_CHANNEL
_ASYNC

DMA software trigger

Micro Direct Memory Access (µDMA) 1153

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Functional Description

www.ti.com

12.3.2 Priority
The DMA controller assigns priority to each channel based on the channel number and the priority-level
bit for the channel. Channel 0 has the highest priority, and as the channel number increases, the priority of
a channel decreases. Each channel has a priority-level bit to provide two levels of priority: default priority
and high priority. If the priority-level bit is set, then that channel has a higher priority than all other
channels at default priority. If multiple channels are set for high priority, then the channel number is used
to determine relative priority among all the high-priority channels.
The priority bit for a channel can be set using the UDMA:SETCHNLPRIORITY register and cleared with
the UDMA:CLEARCHNLPRIORITY register.

12.3.3 Arbitration Size
When a DMA channel requests a transfer, the DMA controller arbitrates among all the channels making
a request, and services the DMA channel with the highest priority. Once a transfer begins, it continues
for a selectable number of transfers before rearbitrating among the requesting channels. The arbitration
size can be configured for each channel, ranging from 1 to 1024 item transfers. After the DMA controller
transfers the number of items specified by the arbitration size, the controller then checks among all the
channels making a request, and services the channel with the highest priority.
If a lower-priority DMA channel uses a large arbitration size, the latency for higher-priority channels is
increased because the DMA controller completes the lower-priority burst before checking for higherpriority requests. Therefore, lower-priority channels must not use a large arbitration size for best response
on high-priority channels.
The arbitration size can also be thought of as burst size. Arbitration size is the maximum number of items
that are transferred at any one time in a burst. Here, the term arbitration refers to the determination of the
DMA channel priority, not arbitration for the bus. When the DMA controller arbitrates for the bus, the
processor always takes priority. Furthermore, the DMA controller is delayed whenever the processor
must perform a bus transaction on the same bus, even in the middle of a burst transfer.

12.3.4 Request Types
The DMA controller responds to two types of requests from a peripheral: single request or burst request.
Each peripheral may support either or both types of requests. A single request means that the peripheral
is ready to transfer one item, while a burst request means that the peripheral is ready to transfer multiple
items.
The DMA controller responds differently depending on whether the peripheral is making a single request
or a burst request. If both types of requests are asserted and the DMA channel has been set up for a
burst transfer, then the burst request takes precedence. Table 12-2 lists how each peripheral supports the
two request types.
Table 12-2. Request Type Support
Peripheral

1154

Single Request Signal

Burst Request Signal

ADC

None (FIFO is not empty)

Sequencer IE bit (FIFO is half full)

General-purpose timer

Raw interrupt pulse

None

GPIO

Raw interrupt pulse

None

SSI TX

TX FIFO not full

TX FIFO level (fixed at 4)

SSI RX

RX FIFO not empty

RX FIFO level (fixed at 4)

UART TX

TX FIFO not full

TX FIFO level (configurable)

UART RX

RX FIFO not empty

RX FIFO level (configurable)

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

12.3.4.1 Single Request
When a single request is detected (not a burst request), the DMA controller transfers one item and then
stops to wait for another request.
NOTE: Channels 8, 13, 14, and 15 do not respond to a single request because waitonreq is tied low.

12.3.4.2 Burst Request
When a burst request is detected, the DMA controller transfers the number of items that is the lesser of
the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration size must be
the same as the number of data items that the peripheral can accommodate when making a burst request.
For example, the UART and SPI, which use a mix of single or burst requests, could generate a burst
request based on the FIFO trigger level. In this case, the arbitration size must be set to the amount of data
that the FIFO can transfer when the trigger level is reached. A burst transfer runs to completion once it
starts and cannot be interrupted, even by a higher-priority channel. Burst transfers complete in a shorter
time than the same number of nonburst transfers.
It may be desirable to use only burst transfers and not allow single transfers (for example, when the
nature of the data is such that it only makes sense when transferred together as a single unit rather than
one piece at a time). The single request can be disabled in the UDMA:SETBURST register. By setting the
bit for a channel in this register, the DMA controller responds only to burst requests for that channel.

12.3.5 Channel Configuration
The DMA controller uses an area of system memory to store a set of channel control structures in a
table. The control table may have one or two entries for each DMA channel. Each entry in the table
structure contains source and destination pointers, transfer size, and transfer mode. The control table can
be located anywhere in system memory, but it must be contiguous and aligned on a 1024-byte boundary.
Table 12-3 describes the memory layout of the channel control table. Each channel may have one or two
control structures in the control table—a primary control structure and an optional, alternate control
structure. The table is organized with all of the primary entries in the first half of the table, and with all the
alternate structures in the second half of the table. The primary entry is used for simple transfer modes
where transfers can be reconfigured and restarted after each transfer completes. In this case, the
alternate control structures are not used and therefore, only the first half of the table must be allocated in
memory; the second half of the control table is not necessary, and that memory can be used for
something else. If a more complex transfer mode is used, such as ping-pong or scatter-gather, then the
alternate control structure is also used and memory space must be allocated for the entire table.
Any unused memory in the control table may be used by the application, which includes the control
structures for any channels that are unused by the application, as well as the unused control word for
each channel.
Table 12-3. Control Structure Memory Map
Offset

Channel

0x0

0, Primary

0x10

1, Primary

...

0x1F0

31, Primary

0x200

0, Alternate

0x210

1, Alternate

...

0x3F0

31, Alternate

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1155

Functional Description

www.ti.com

Table 12-4 describes an individual control-structure entry in the control table. Each entry is aligned on a
16-byte boundary. The entry contains four long words: the source end pointer, the destination end pointer,
the control word, and an unused entry. The inclusive end pointers point to the ending address of the
transfer. If the source or destination is nonincrementing (as for a peripheral register), then the pointer must
point to the transfer address.
Table 12-4. Channel Control Structure
Offset

Description

0x000

Source end pointer

0x004

Destination end pointer

0x008

Control word

0x00C

Unused entry

The control word contains the following fields:
• Source and destination data sizes
• Source and destination address increment size
• Number of transfers before bus arbitration
• Total number of items to transfer
• Useburst flag
• Transfer mode
The control parameters for a channel can be set using the driver library function void
uDMAChannelControlSet(); function. The DMA controller updates the transfer size and transfer mode
fields as the transfer is performed. At the end of a transfer, the transfer size indicates 0, and the transfer
mode indicates stopped. Because the control word is modified by the DMA controller, it must be
reconfigured before each new transfer. The source and destination end pointers are not modified, so they
can be left unchanged if the source or destination addresses remain the same.
Before starting a transfer, a DMA channel must be enabled by setting the appropriate bit in the
UDMA:SETCHANNELEN register. A channel can be disabled by setting the channel bit in the
UDMA:CLEARCHANNELEN register. At the end of a complete DMA transfer, the controller automatically
disables the channel.

1156

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

12.3.6 Transfer Modes
The DMA controller supports several transfer modes. Two of the modes support simple, one-time
transfers. Several complex modes support a continuous flow of data.
12.3.6.1 Stop Mode
While stop mode is not actually a transfer mode, stop is a valid value for the mode field of the control
word. When the mode field has the stop value, the DMA controller does not perform any transfers and
disables the channel if enabled. The DMA controller updates the control word to set the mode to stop at
the end of a transfer. This mode can be useful in scatter-gather operations.
12.3.6.2 Basic Mode
In basic mode, the DMA controller performs transfers as long as there are more items to transfer, and a
transfer request is present. This mode is used with peripherals that assert a DMA request signal
whenever the peripheral is ready for a data transfer. Basic mode must not be used in any situation where
the request is momentary, even though the entire transfer must be completed.
The DMA controller sets the mode for that channel to stop when all of the items have been transferred
using basic mode.
12.3.6.3 Auto Mode
Auto mode is similar to basic mode, except that when a transfer request is received, the transfer
completes, even if the DMA request is removed. This mode is suitable for software-triggered transfers.
Generally, auto mode is not used with a peripheral.
The DMA controller sets the mode for that channel to stop when all the items have been transferred
using auto mode.
12.3.6.4 Ping-Pong
Ping-pong mode is used to support a continuous data flow to or from a peripheral. Both the primary and
alternate data structures must be implemented to use ping-pong mode. Both structures are set up by the
processor for data transfer between memory and a peripheral. The transfer is started using the primary
control structure. When the transfer using the primary control structure completes, the DMA controller
reads the alternate control structure for that channel to continue the transfer. Each time this occurs, an
interrupt is generated, and the processor can reload the control structure for the just-completed transfer.
Data flow can continue indefinitely this way, using the primary and alternate control structures to switch
between buffers as the data flows to or from the peripheral.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1157

Functional Description

www.ti.com

Figure 12-2 shows an example operation in ping-pong mode.
Figure 12-2. Example of Ping-Pong DMA Transaction
Cortex-M3 processor

µDMA controller
SOURCE
DEST
CONTROL
Unused

Transfer continues using alternate

Primary structure

Time
Alternate structure

1158

µD

inte

rru

SOURCE
DEST
CONTROL
Unused

Transfers using BUFFER B

BUFFER B

rip

Transfers using BUFFER A

ral

µD

int

err

BUFFER A
x Process data in BUFFER B
x Reload alternate structure

SOURCE
DEST
CONTROL
Unused

x Process data in BUFFER A
x Reload primary structure

SOURCE
DEST
CONTROL
Unused

Micro Direct Memory Access (µDMA)

rip
h

l or

Transfer continues using alternate

Primary structure

BUFFER A

era

Transfer continues using primary

Alternate structure

Transfers using BUFFER A

rip
h

era

rµ
D

int

err

Transfers using BUFFER B
BUFFER B
x Process data in BUFFER A
x Reload alternate structure

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

12.3.6.5 Memory Scatter-Gather Mode
Memory scatter-gather mode is a complex mode used when data must be transferred to or from varied
locations in memory instead of a set of contiguous locations in a memory buffer. For example, a gather
DMA operation could be used to selectively read the payload of several stored packets of a
communication protocol, and store them together in sequence in a memory buffer.
In memory scatter-gather mode, the primary control structure is used to program the alternate control
structure from a table in memory. The table is set up by the processor software and contains a list of
control structures, each containing the source and destination end pointers, and the control word for a
specific transfer. The mode of each control word must be set to memory scatter-gather mode. Each entry
in the table is, in turn, copied to the alternate structure where it is then executed. The DMA controller
alternates between using the primary control structure to copy the next transfer instruction from the list,
and then executing the new transfer instruction. The end of the list is marked by programming the control
word for the last entry to use auto transfer mode. When the last transfer is performed using auto mode,
the DMA controller stops. A completion interrupt is generated only after the last transfer.
It is possible to loop the list by having the last entry copy the primary control structure to point back to the
beginning of the list (or to a new list). It is also possible to trigger a set of other channels to perform a
transfer, either directly, by programming a write to the software trigger for another channel, or indirectly, by
causing a peripheral action that results in a DMA request.
By programming the DMA controller using this method, a set of arbitrary transfers can be performed
based on a single DMA request.
Figure 12-3 shows an example of operation in memory scatter-gather mode. This example shows a gather
operation, where data in three separate buffers in memory is copied together into one buffer. Figure 12-3
shows how the application sets up a DMA task list in memory, that is then used by the controller to
perform three sets of copy operations from different locations in memory. The primary control structure for
the channel used for the operation is configured to copy from the task list to the alternate control structure.
Figure 12-4 shows the sequence as the DMA controller performs the three sets of copy operations. First,
using the primary control structure, the DMA controller loads the alternate control structure with Task A.
The DMA controller then performs the copy operation specified by Task A, copying the data from the
source buffer A to the destination buffer. Next, the DMA controller again uses the primary control
structure to load Task B into the alternate control structure, and then performs the B operation with the
alternate control structure. The process is repeated for Task C.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1159

Functional Description

www.ti.com

Figure 12-3. Memory Scatter-Gather, Setup, and Configuration
1

Source and destination
buffer in memory

Task list in memory

Channel control
table in memory

4 words (SRC A)

SRC

DST
ITEMS=4
Unused
SRC
DST
16 words (SRC B)

ITEMS=16

Task A

SRC
DST
ITEMS=12

Channel primary
control structure

Task B

Unused
SRC
DST
ITEMS=1
Unused

Task C

SRC
DST
ITEMS=n

1 words (SRC C)

Channel alterna te
control structure

4 (DEST A)

16 (DEST B)

1 (DEST C)

1160

(1)

The application has a need to copy data items from three separate locations in memory into one combined
buffer.

(2)

The application sets up µDMA "task list" in memory, which contains the pointers and control configuration for
three µDMA copy "tasks."

(3)

The application sets up the channel primary control structure to copy each task configuration, one at a time,
to the alternate control structure, where it is executed by the µDMA controller.

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

Figure 12-4. Memory Scatter-Gather, DMA Copy Sequence
Task list
in memory

µDMA control table
in memory

Buffers
in memory

SRC A

SRC

SRC B

PRI

Copied

DST
Task A
Task B

SRC C

SRC
ALT

Copied

DST

Task C

DEST A
DEST B
DEST C

Using the primary control structure of the channel, the µDMA
controller copies task A configuration to the alternate control
structure of the channel.

Task list
in memory

Then, using the alternate control structure of the channel, the
µDMA controller copies data from source buffer A to the destination
buffer.

µDMA control table
in memory

Buffers
in memory

SRC A

SRC

SRC B
PRI
DST

Task A
Task B
Task C

SRC C

SRC

Copied

ALT
Copied

DST

DEST A
DEST B
DEST C

Using the primary control structure of the channel, the µDMA
controller copies task B configuration to the alternate control
structure of the channel.

Task list
in memory

Then, using the alternate control structure of the channel, the
µDMA controller copies data from source buffer B to the destination
buffer.

µDMA control table
in memory

Buffers
in memory

SRC A

SRC

SRC B

PRI
DST
Task A

SRC C

SRC

Task B

ALT
DST

Task C

DEST A

Copied

DEST B
DEST C

Using the primary control structure of the channel, the µDMA
controller copies task C configuration to the alternate control
structure of the channel.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Then, using the alternate control structure of the channel, the
µDMA controller copies data from source buffer C to destination
buffer.

Micro Direct Memory Access (µDMA)

1161

Functional Description

www.ti.com

12.3.6.6 Peripheral Scatter-Gather Mode
Peripheral scatter-gather mode is similar to memory scatter-gather mode, except that the transfers are
controlled by a peripheral making a DMA request. When the DMA controller detects a request from the
peripheral, the DMA controller uses the primary control structure to copy one entry from the list to the
alternate control structure, and then performs the transfer. At the end of this transfer, the next transfer is
started only if the peripheral again asserts a DMA request. The DMA controller continues to perform
transfers from the list only when the peripheral makes a request, until the last transfer completes. A
completion interrupt is generated only after the last transfer.
By using this method, the DMA controller can transfer data to or from a peripheral from a set of arbitrary
locations whenever the peripheral is ready to transfer data.
Figure 12-5 shows an example of operation in peripheral scatter-gather mode. This example shows a
gather operation where data from three separate buffers in memory is copied to a single peripheral data
register. Figure 12-5 shows how the application sets up a µDMA task list in memory, that is then used by
the controller to perform three sets of copy operations from different locations in memory. The primary
control structure for the channel used for the operation is configured to copy from the task list to the
alternate control structure.
Figure 12-6 shows the sequence as the µDMA controller performs the three sets of copy operations. First,
using the primary control structure, the µDMA controller loads the alternate control structure with Task A.
The µDMA controller then performs the copy operation specified by Task A, copying the data from the
source buffer A to the peripheral data register. Next, the µDMA controller again uses the primary control
structure to load Task B into the alternate control structure, and then performs the B operation with the
alternate control structure. The process is repeated for Task C.
Figure 12-5. Peripheral Scatter-Gather, Setup, and Configuration
1
Source buffer
in memory

4 words (SRC A)
A

Task list in memory

Channel control
table in memory

SRC
DST
ITEMS=4
Unused

16 Words (SRC B)
B

Task A

SRC
DST
ITEMS=12

SRC
DST
ITEMS=16
Unused

Task B

SRC
DST
ITEMS=1
Unused

Task C

SRC
DST

Channel primary
control structure

Channel alternate
control structure

ITEMS=n

1 Word (SRC C)
C

Peripheral data
register
DEST

1162

(1)

The application has a need to copy data items from three separate locations in memory into a peripheral data
register.

(2)

The application sets up the µDMA "task list" in memory, which contains the pointers and control configuration
for three µDMA copy "tasks."

(3)

The application sets up the channel primary control structure to copy each task configuration, one at a time,
to the alternate control structure, where it is executed by the µDMA controller.

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

Figure 12-6. Peripheral Scatter-Gather, DMA Copy Sequence
Task list
in memory

µDMA control table
in memory

Buffers
in memory

SRC A

SRC

SRC B

PRI

Copied

DST
Task A
Task B

SRC C

SRC
ALT

Copied

DST

Task C

Using the primary control structure of the channel, the µDMA
controller copies task A configuration to the alternate control
structure of the channel.

Task list
in memory

Peripheral
data
register

Then, using the alternate control structure of the channel, the
µDMA controller copies data from source buffer A to the peripheral
data register.

µDMA control table
in memory

Buffers
in memory

SRC A

SRC

SRC B
PRI
DST

Task A
Task B
Task C

SRC C

SRC

Copied

ALT
Copied

DST

Using the primary control structure of the channel, the µDMA
controller copies task B configuration to the alternate control
structure of the channel.

Task list
in memory

Peripheral
data
register

Then, using the alternate control structure of the channel, the
µDMA controller copies data from source buffer B to the peripheral
data register.

µDMA control table
in memory

Buffers
in memory

SRC A

SRC

SRC B

PRI
DST
Task A

SRC C

SRC

Task B

ALT
DST

Task C

Copied

Peripheral
data
register

Using the primary control structure of the channel, the µDMA
controller copies task C configuration to the alternate control
structure of the channel.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Then, using the alternate control structure of the channel, the
µDMA controller copies data from source buffer C to the peripheral
data register.

Micro Direct Memory Access (µDMA)

1163

Functional Description

www.ti.com

12.3.7 Transfer Size and Increments
The DMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination data size
must be the same for any given transfer. The source and destination address can be automatically
incremented by bytes, half-words, words, or set to no increment. The source and destination address
increment values can be set independently; it is not necessary for the address increment to match the
data size, as long as the increment is the same or larger than the data size. For example, it is possible to
perform a transfer using 8-bit data size by using an address increment of full words (4 bytes). The data to
be transferred must be aligned in memory according to the data size (8, 16, or 32 bits).
Table 12-5 provides the configuration to read from a peripheral that supplies 8-bit data.
Table 12-5. DMA Read Example: 8-Bit Peripheral
Field

Configuration

Source data size

8 bits

Destination data size

8 bits

Source address increment

No increment

Destination address increment

Byte

Source end pointer

Peripheral read FIFO register

Destination end pointer

End of the data buffer in memory

12.3.8 Peripheral Interface
Each peripheral that supports DMA has a single request or burst request signal that is asserted when the
peripheral is ready to transfer data (see Table 12-2). The request signal can be disabled or enabled using
the UDMA:SETREQMASK and UDMA:CLEARREQMASK registers, respectively. The DMA request
signal is disabled, or masked, when the channel request mask bit is set. When the request is not masked,
the DMA channel is configured correctly and enabled, the peripheral asserts the request signal, and the
DMA controller begins the transfer.
NOTE: The peripheral must disable all interrupts to the event fabric when using DMA to transfer
data to and from a peripheral.

When a DMA transfer is complete, the DMA controller generates an interrupt; for more information, see
Section 12.3.10, Interrupts and Errors.
For more information on how a specific peripheral interacts with the DMA controller, refer to the DMA
Operation section in the chapter that discusses that peripheral.

12.3.9 Software Request
Channels may be set up to perform software transfers through the UDMA:SOFTREQ register. If the
channel used for software is also tied to a specific peripheral, the dma_done/interrupt signal is provided
directly to the Cortex-M3 CPU instead of sending it to the peripheral. The interrupt used is a combined
interrupt, number 46 – software µDMA interrupt, for all software transfers.
If software uses a DMA channel of the peripheral to initiate a request, then the completion interrupt
occurs on the interrupt vector for the peripheral instead of occurring on the software interrupt vector.
NOTE: DMA software requests are specified on channels 0, 18, 19, and 20. For channel 0 and
channel 18, dma_done is available as events DMA_CH0_DONE and DMA_CH18_DONE in
the EV field of the EVENT:UDMACH14BSEL or EVENT:CPUIRQSEL30 registers.

1164

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

12.3.10 Interrupts and Errors
The DMA controller generates a completion interrupt on the interrupt vector of the peripheral when a
DMA transfer completes. Therefore, if DMA is used to transfer data for a peripheral and interrupts are
used, then the interrupt handler for that peripheral must be designed to handle the DMA transfer
completion interrupt. If the transfer uses the software DMA channel, then the completion interrupt occurs
on the dedicated software DMA interrupt vector (see Table 12-6).
When DMA is enabled for a peripheral, the DMA controller stops the normal transfer interrupts for a
peripheral from reaching the interrupt controller (INTC). The interrupts are still reported in the interrupt
registers of the peripheral. Thus, when a large amount of data is transferred using DMA, instead of
receiving multiple interrupts from the peripheral as data flows, the INTC receives only one interrupt when
the transfer completes. Unmasked peripheral error interrupts continue to be sent to the INTC.
When a DMA channel generates a completion interrupt, the CHNLS bit corresponding to the peripheral
channel is set in the DMA Channel Request Done Register, UDMA:REQDONE. This register can be used
by the interrupt handler code of the peripheral to determine if the interrupt was caused by the DMA
channel or an error event reported by the interrupt registers of the peripheral. The completion interrupt
request from the DMA controller is automatically cleared when the interrupt handler is activated.
If the DMA controller encounters a bus or memory protection error as it tries to perform a data transfer,
the controller disables the DMA channel that caused the error and generates an interrupt on the DMA
error interrupt vector. The processor can read the DMA Clear Bus Error Register, UDMA:ERROR, to
determine if an error is pending. The STATUS bit is set if an error occurred. The error can be cleared by
setting the STATUS bit to 1.
NOTE:

The error interrupt or event goes to the event fabric as DMA_ERR, and is connected as
interrupt to CM3 through the EVENT:CPUIRQSEL25 register.

Table 12-6 lists the dedicated interrupt assignments for the DMA controller.
Table 12-6. DMA Interrupt Assignments
Interrupt

Assignment

DMA software channel transfer

DMA error

12.4 Initialization and Configuration
12.4.1 Module Initialization
The DMA controller resides in the peripheral domain, which must be powered up to enable the µDMA
controller. The following steps are necessary:
1. Enable the peripheral power domain by setting the PRCM:PDCTL0PERIPH.ON register bit or by using
the driver library function (PRCM_DOMAIN_PERIPH):
PRCMPowerDomainOn

2. Enable the µDMA controller by setting the PRCM:SECDMACLKGR.DMA_CLK_EN register bit and the
PRCM:SECDMACLKGS.DMA_CLK_EN register bit or by using the driver library functions:
PRCMPeripheralRunEnable(uint32_t)

and
PRCMPeripheralSleepEnable(uint32_t)

3. Load the setting to clock controller by setting the PRCM:CLKLOADCTL.LOAD register bit or by using
the function:
PRCMLoadSet()

4. Enable the µDMA controller by setting the DMA Configuration Register, UDMA:CFG,
MASTERENABLE bit.
5. Program the location of the channel control table by writing the base address of the table to the DMA
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1165

Initialization and Configuration

www.ti.com

Channel Control Base Pointer Register, UDMA:CTRL. The base address must be aligned on a 1024byte boundary.

12.4.2 Configuring a Memory-to-Memory Transfer
The DMA channels 0, 18, 19, and 20 are dedicated for software-initiated transfers. This specific example
uses channel 0. No attributes must be set for a software-based transfer. The attributes are cleared by
default, but are explicitly cleared as shown in the following sections.
12.4.2.1 Configure the Channel Attributes
Configure the channel attributes as follows, or use the following driver library function:
uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)

1. Program bit 0 of the DMA Set Channel Priority Register, UDMA:SETCHNLPRIORITY, or the DMA
Clear Channel Priority Register, UDMA:CLEARCHNLPRIORITY, to set the channel to high priority or
default priority.
2. Set bit 0 of the DMA Clear Channel Primary Alternate Register, UDMA:CLEARCHNLPRIALT, to select
the primary channel control structure for this transfer.
3. Set bit 0 of the DMA Channel Clear Useburst Register, UDMA:CLEARBURST, to allow the DMA
controller to respond to single requests and burst requests.
4. Set bit 0 of the DMA Clear Channel Request Mask Register, UDMA:CLEARREQMASK, to allow the
DMA controller to recognize requests for this channel.
12.4.2.2 Configure the Channel Control Structure
This example transfers 256 words from one memory buffer to another. Channel 0 is used for a software
transfer, and the control structure for channel 0 must be configured to transfer 8-bit data with source and
destination increments in bytes and byte-wise buffer copy. A bus arbitration size of eight can be used
here.
The transfer buffer and transfer size are now configured. The transfer uses auto mode, which means that
the transfer automatically runs to completion after the first request.
12.4.2.3 Start the Transfer
Finally, the channel must be enabled. A request must also be made because this is a software-initiated
transfer. The request starts the transfer.
1. Enable global interrupts (IntMasterEnable();) and enable interrupt for DMA (IntEnable(uint32_t
ui32Interrupt)).
2. Enable the channel by setting bit 0 of the DMA Set Channel Enable Register,
UDMA:SETCHANNELEN.
3. Issue a transfer request by setting bit 0 of the DMA Channel Software Request Register,
UDMA:SOFTREQ.
4. The DMA transfer begins. If the interrupt is enabled, then the processor is notified by interrupt when
the transfer completes.
If needed, the status can be checked by reading the UDMA:SETCHANNELEN register bit 0. This bit is
automatically cleared when the transfer completes.

1166

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

µDMA Registers

www.ti.com

12.5 µDMA Registers
12.5.1 UDMA Registers
Table 12-7 lists the memory-mapped registers for the UDMA. All register offset addresses not listed in
Table 12-7 should be considered as reserved locations and the register contents should not be modified.
Table 12-7. UDMA Registers
Offset

Acronym

Section

STATUS

Status

Section 12.5.1.1

CFG

Configuration

Section 12.5.1.2

CTRL

Channel Control Data Base Pointer

Section 12.5.1.3

ALTCTRL

Channel Alternate Control Data Base Pointer

Section 12.5.1.4

10h

WAITONREQ

Channel Wait On Request Status

Section 12.5.1.5

14h

SOFTREQ

Channel Software Request

Section 12.5.1.6

18h

SETBURST

Channel Set UseBurst

Section 12.5.1.7

1Ch

CLEARBURST

Channel Clear UseBurst

Section 12.5.1.8

20h

SETREQMASK

Channel Set Request Mask

Section 12.5.1.9

24h

CLEARREQMASK

Clear Channel Request Mask

Section 12.5.1.10

28h

SETCHANNELEN

Set Channel Enable

Section 12.5.1.11

2Ch

CLEARCHANNELEN

Clear Channel Enable

Section 12.5.1.12

30h

SETCHNLPRIALT

Channel Set Primary-Alternate

Section 12.5.1.13

34h

CLEARCHNLPRIALT

Channel Clear Primary-Alternate

Section 12.5.1.14

38h

SETCHNLPRIORITY

Set Channel Priority

Section 12.5.1.15

3Ch

CLEARCHNLPRIORITY

Clear Channel Priority

Section 12.5.1.16

4Ch

ERROR

Error Status and Clear

Section 12.5.1.17

504h

REQDONE

Channel Request Done

Section 12.5.1.18

520h

DONEMASK

Channel Request Done Mask

Section 12.5.1.19

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1167

µDMA Registers

www.ti.com

12.5.1.1 STATUS Register (Offset = 0h) [reset = 001F0000h]
STATUS is shown in Figure 12-7 and described in Table 12-8.
Return to Summary Table.
Status
Figure 12-7. STATUS Register
31

TEST
R-0h

RESERVED
R-0h

22
RESERVED
R-0h

18
TOTALCHANNELS
R-1Fh

2
RESERVED

STATE
R-0h

R-0h

0
MASTERENAB
LE
R-0h

RESERVED
R-0h
7

Table 12-8. STATUS Register Field Descriptions
Bit

Field

Type

Reset

Description

31-28

TEST

0x0: Controller does not include the integration test logic
0x1: Controller includes the integration test logic
0x2: Undefined
...
0xF: Undefined

27-21

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

20-16

TOTALCHANNELS

1Fh

Register value returns number of available uDMA channels minus
one. For example a read out value of:
0x00: Show that the controller is configured to use 1 uDMA channel
0x01: Shows that the controller is configured to use 2 uDMA
channels
...
0x1F: Shows that the controller is configured to use 32 uDMA
channels (32-1=31=0x1F)

15-8

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-4

STATE

Current state of the control state machine. State can be one of the
following:
0x0: Idle
0x1: Reading channel controller data
0x2: Reading source data end pointer
0x3: Reading destination data end pointer
0x4: Reading source data
0x5: Writing destination data
0x6: Waiting for uDMA request to clear
0x7: Writing channel controller data
0x8: Stalled
0x9: Done
0xA: Peripheral scatter-gather transition
0xB: Undefined
...
0xF: Undefined.

3-1

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1168

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

µDMA Registers

www.ti.com

Table 12-8. STATUS Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

MASTERENABLE

Shows the enable status of the controller as configured by
CFG.MASTERENABLE:
0: Controller is disabled
1: Controller is enabled

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1169

µDMA Registers

www.ti.com

12.5.1.2 CFG Register (Offset = 4h) [reset = 0h]
CFG is shown in Figure 12-8 and described in Table 12-9.
Return to Summary Table.
Configuration
Figure 12-8. CFG Register
31

0
MASTERENAB
LE
W-0h

RESERVED
W-0h
23

20
RESERVED
W-0h

12
RESERVED
W-0h

6
PRTOCTRL

3
RESERVED

W-0h

Table 12-9. CFG Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-5

PRTOCTRL

Sets the AHB-Lite bus protocol protection state by controlling the
AHB signal HProt[3:1] as follows:
Bit [7] Controls HProt[3] to indicate if a cacheable access is
occurring.
Bit [6] Controls HProt[2] to indicate if a bufferable access is
occurring.
Bit [5] Controls HProt[1] to indicate if a privileged access is
occurring.
When bit [n] = 1 then the corresponding HProt bit is high.
When bit [n] = 0 then the corresponding HProt bit is low.
This field controls HProt[3:1] signal for all transactions initiated by
uDMA except two transactions below:
- the read from the address indicated by source address pointer
- the write to the address indicated by destination address pointer
HProt[3:1] for these two exceptions can be controlled by dedicated
fields in the channel configutation descriptor.

4-1

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MASTERENABLE

Enables the controller:
0: Disables the controller
1: Enables the controller

1170

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

µDMA Registers

www.ti.com

12.5.1.3 CTRL Register (Offset = 8h) [reset = 0h]
CTRL is shown in Figure 12-9 and described in Table 12-10.
Return to Summary Table.
Channel Control Data Base Pointer
Figure 12-9. CTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BASEPTR
R/W-0h

6 5 4 3
RESERVED
R-0h

Table 12-10. CTRL Register Field Descriptions
Bit
31-10

9-0

Field

Type

Reset

Description

BASEPTR

R/W

This register point to the base address for the primary data
structures of each DMA channel. This is not stored in module, but in
system memory, thus space must be allocated for this usage when
DMA is in usage

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1171

µDMA Registers

www.ti.com

12.5.1.4 ALTCTRL Register (Offset = Ch) [reset = 200h]
ALTCTRL is shown in Figure 12-10 and described in Table 12-11.
Return to Summary Table.
Channel Alternate Control Data Base Pointer
Figure 12-10. ALTCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BASEPTR
R-200h

Table 12-11. ALTCTRL Register Field Descriptions
Bit
31-0

1172

Field

Type

Reset

Description

BASEPTR

200h

This register shows the base address for the alternate data
structures and is calculated by module, thus read only

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

µDMA Registers

www.ti.com

12.5.1.5 WAITONREQ Register (Offset = 10h) [reset = FFFF1EFFh]
WAITONREQ is shown in Figure 12-11 and described in Table 12-12.
Return to Summary Table.
Channel Wait On Request Status
Figure 12-11. WAITONREQ Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLSTATUS
R-FFFF1EFFh

Table 12-12. WAITONREQ Register Field Descriptions
Bit
31-0

Field

Type

Reset

CHNLSTATUS

FFFF1EFFh Channel wait on request status:
Bit [Ch] = 0: Once uDMA receives a single or burst request on
channel Ch, this channel may come out of active state even if
request is still present.
Bit [Ch] = 1: Once uDMA receives a single or burst request on
channel Ch, it keeps channel Ch in active state until the requests are
deasserted. This handshake is necessary for channels where the
requester is in an asynchronous domain or can run at slower clock
speed than uDMA

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Micro Direct Memory Access (µDMA)

1173

µDMA Registers

www.ti.com

12.5.1.6 SOFTREQ Register (Offset = 14h) [reset = 0h]
SOFTREQ is shown in Figure 12-12 and described in Table 12-13.
Return to Summary Table.
Channel Software Request
Figure 12-12. SOFTREQ Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
W-0h

Table 12-13. SOFTREQ Register Field Descriptions
Bit
31-0

1174

Field

Type

Reset

Description

CHNLS

Set the appropriate bit to generate a software uDMA request on the
corresponding uDMA channel
Bit [Ch] = 0: Does not create a uDMA request for channel Ch
Bit [Ch] = 1: Creates a uDMA request for channel Ch
Writing to a bit where a uDMA channel is not implemented does not
create a uDMA request for that channel

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

µDMA Registers

www.ti.com

12.5.1.7 SETBURST Register (Offset = 18h) [reset = 0h]
SETBURST is shown in Figure 12-13 and described in Table 12-14.
Return to Summary Table.
Channel Set UseBurst
Figure 12-13. SETBURST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
R/W-0h

Table 12-14. SETBURST Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

CHNLS

R/W

Returns the useburst status, or disables individual channels from
generating single uDMA requests. The value R is the arbitration rate
and stored in the controller data structure.
Read as:
Bit [Ch] = 0: uDMA channel Ch responds to both burst and single
requests on channel C. The controller performs 2R, or single, bus
transfers.
Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer
requests. The controller only responds to burst transfer requests and
performs 2R transfers.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch]
to 0.
Bit [Ch] = 1: Disables single transfer requests on channel Ch. The
controller performs 2R transfers for burst requests.
Writing to a bit where a uDMA channel is not implemented has no
effect

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1175

µDMA Registers

www.ti.com

12.5.1.8 CLEARBURST Register (Offset = 1Ch) [reset = 0h]
CLEARBURST is shown in Figure 12-14 and described in Table 12-15.
Return to Summary Table.
Channel Clear UseBurst
Figure 12-14. CLEARBURST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
W-0h

Table 12-15. CLEARBURST Register Field Descriptions
Bit
31-0

1176

Field

Type

Reset

Description

CHNLS

Set the appropriate bit to enable single transfer requests.
Write as:
Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single
transfer requests.
Bit [Ch] = 1: Enables single transfer requests on channel Ch.
Writing to a bit where a DMA channel is not implemented has no
effect.

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

µDMA Registers

www.ti.com

12.5.1.9 SETREQMASK Register (Offset = 20h) [reset = 0h]
SETREQMASK is shown in Figure 12-15 and described in Table 12-16.
Return to Summary Table.
Channel Set Request Mask
Figure 12-15. SETREQMASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
R/W-0h

Table 12-16. SETREQMASK Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

CHNLS

R/W

Returns the burst and single request mask status, or disables the
corresponding channel from generating uDMA requests.
Read as:
Bit [Ch] = 0: External requests are enabled for channel Ch.
Bit [Ch] = 1: External requests are disabled for channel Ch.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable
uDMA requests.
Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA
single request channel [C] input from generating uDMA requests.
Writing to a bit where a uDMA channel is not implemented has no
effect

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1177

µDMA Registers

www.ti.com

12.5.1.10 CLEARREQMASK Register (Offset = 24h) [reset = 0h]
CLEARREQMASK is shown in Figure 12-16 and described in Table 12-17.
Return to Summary Table.
Clear Channel Request Mask
Figure 12-16. CLEARREQMASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
W-0h

Table 12-17. CLEARREQMASK Register Field Descriptions
Bit
31-0

1178

Field

Type

Reset

Description

CHNLS

Set the appropriate bit to enable DMA request for the channel.
Write as:
Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable
channel C from generating requests.
Bit [Ch] = 1: Enables channel [C] to generate DMA requests.
Writing to a bit where a DMA channel is not implemented has no
effect.

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

µDMA Registers

www.ti.com

12.5.1.11 SETCHANNELEN Register (Offset = 28h) [reset = 0h]
SETCHANNELEN is shown in Figure 12-17 and described in Table 12-18.
Return to Summary Table.
Set Channel Enable
Figure 12-17. SETCHANNELEN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
R/W-0h

Table 12-18. SETCHANNELEN Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

CHNLS

R/W

Returns the enable status of the channels, or enables the
corresponding channels.
Read as:
Bit [Ch] = 0: Channel Ch is disabled.
Bit [Ch] = 1: Channel Ch is enabled.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to
disable a channel
Bit [Ch] = 1: Enables channel Ch
Writing to a bit where a DMA channel is not implemented has no
effect

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1179

µDMA Registers

www.ti.com

12.5.1.12 CLEARCHANNELEN Register (Offset = 2Ch) [reset = 0h]
CLEARCHANNELEN is shown in Figure 12-18 and described in Table 12-19.
Return to Summary Table.
Clear Channel Enable
Figure 12-18. CLEARCHANNELEN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
W-0h

Table 12-19. CLEARCHANNELEN Register Field Descriptions
Bit
31-0

1180

Field

Type

Reset

Description

CHNLS

Set the appropriate bit to disable the corresponding uDMA channel.
Write as:
Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable
uDMA channels.
Bit [Ch] = 1: Disables channel Ch
Writing to a bit where a uDMA channel is not implemented has no
effect

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

µDMA Registers

www.ti.com

12.5.1.13 SETCHNLPRIALT Register (Offset = 30h) [reset = 0h]
SETCHNLPRIALT is shown in Figure 12-19 and described in Table 12-20.
Return to Summary Table.
Channel Set Primary-Alternate
Figure 12-19. SETCHNLPRIALT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
R/W-0h

Table 12-20. SETCHNLPRIALT Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

CHNLS

R/W

Returns the channel control data structure status, or selects the
alternate data structure for the corresponding uDMA channel.
Read as:
Bit [Ch] = 0: uDMA channel Ch is using the primary data structure.
Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to
disable a channel
Bit [Ch] = 1: Selects the alternate data structure for channel Ch
Writing to a bit where a uDMA channel is not implemented has no
effect

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1181

µDMA Registers

www.ti.com

12.5.1.14 CLEARCHNLPRIALT Register (Offset = 34h) [reset = 0h]
CLEARCHNLPRIALT is shown in Figure 12-20 and described in Table 12-21.
Return to Summary Table.
Channel Clear Primary-Alternate
Figure 12-20. CLEARCHNLPRIALT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
W-0h

Table 12-21. CLEARCHNLPRIALT Register Field Descriptions
Bit
31-0

1182

Field

Type

Reset

Description

CHNLS

Clears the appropriate bit to select the primary data structure for the
corresponding uDMA channel.
Write as:
Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select
the alternate data structure.
Bit [Ch] = 1: Selects the primary data structure for channel Ch.
Writing to a bit where a uDMA channel is not implemented has no
effect

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

µDMA Registers

www.ti.com

12.5.1.15 SETCHNLPRIORITY Register (Offset = 38h) [reset = 0h]
SETCHNLPRIORITY is shown in Figure 12-21 and described in Table 12-22.
Return to Summary Table.
Set Channel Priority
Figure 12-21. SETCHNLPRIORITY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
R/W-0h

Table 12-22. SETCHNLPRIORITY Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

CHNLS

R/W

Returns the channel priority mask status, or sets the channel priority
to high.
Read as:
Bit [Ch] = 0: uDMA channel Ch is using the default priority level.
Bit [Ch] = 1: uDMA channel Ch is using a high priority level.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to
set channel Ch to the default priority level.
Bit [Ch] = 1: Channel Ch uses the high priority level.
Writing to a bit where a uDMA channel is not implemented has no
effect

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1183

µDMA Registers

www.ti.com

12.5.1.16 CLEARCHNLPRIORITY Register (Offset = 3Ch) [reset = 0h]
CLEARCHNLPRIORITY is shown in Figure 12-22 and described in Table 12-23.
Return to Summary Table.
Clear Channel Priority
Figure 12-22. CLEARCHNLPRIORITY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
W-0h

Table 12-23. CLEARCHNLPRIORITY Register Field Descriptions
Bit
31-0

1184

Field

Type

Reset

Description

CHNLS

Clear the appropriate bit to select the default priority level for the
specified uDMA channel.
Write as:
Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set
channel Ch to the high priority level.
Bit [Ch] = 1: Channel Ch uses the default priority level.
Writing to a bit where a uDMA channel is not implemented has no
effect

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

µDMA Registers

www.ti.com

12.5.1.17 ERROR Register (Offset = 4Ch) [reset = 0h]
ERROR is shown in Figure 12-23 and described in Table 12-24.
Return to Summary Table.
Error Status and Clear
Figure 12-23. ERROR Register
31

0
STATUS
R/W-0h

RESERVED
W-0h
23

20
RESERVED
W-0h

12
RESERVED
W-0h

4
RESERVED
W-0h

Table 12-24. ERROR Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STATUS

R/W

Returns the status of bus error flag in uDMA, or clears this bit
Read as:
0: No bus error detected
1: Bus error detected
Write as:
0: No effect, status of bus error flag is unchanged.
1: Clears the bus error flag.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1185

µDMA Registers

www.ti.com

12.5.1.18 REQDONE Register (Offset = 504h) [reset = 0h]
REQDONE is shown in Figure 12-24 and described in Table 12-25.
Return to Summary Table.
Channel Request Done
Figure 12-24. REQDONE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
R/W-0h

Table 12-25. REQDONE Register Field Descriptions
Bit
31-0

1186

Field

Type

Reset

Description

CHNLS

R/W

Reflects the uDMA done status for the given channel, channel [Ch].
It's a sticky done bit. Unless cleared by writing a 1, it holds the value
of 1.
Read as:
Bit [Ch] = 0: Request has not completed for channel Ch
Bit [Ch] = 1: Request has completed for the channel Ch
Writing a 1 to individual bits would clear the corresponding bit.
Write as:
Bit [Ch] = 0: No effect.
Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0

Micro Direct Memory Access (µDMA)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

µDMA Registers

www.ti.com

12.5.1.19 DONEMASK Register (Offset = 520h) [reset = 0h]
DONEMASK is shown in Figure 12-25 and described in Table 12-26.
Return to Summary Table.
Channel Request Done Mask
Figure 12-25. DONEMASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CHNLS
R/W-0h

Table 12-26. DONEMASK Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

CHNLS

R/W

Controls the propagation of the uDMA done and active state to the
assigned peripheral. Specifically used for software channels.
Read as:
Bit [Ch] = 0: uDMA done and active state for channel Ch is not
blocked from reaching to the peripherals.
Note that the uDMA done state for channel [Ch] is blocked from
contributing to generation of combined uDMA done signal
Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked
from reaching to the peripherals.
Note that the uDMA done state for channel [Ch] is not blocked from
contributing to generation of combined uDMA done signal
Write as:
Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the
peripherals.
Note that this disables uDMA done state for channel [Ch] from
contributing to generation of combined uDMA done signal
Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the
peripherals.
Note that this enables uDMA done for channel [Ch] to contribute to
generation of combined uDMA done signal.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Micro Direct Memory Access (µDMA)

1187

Chapter 13
SWCU117G – February 2015 – Revised February 2017

Timers
This chapter describes the general-purpose timers.
Topic

13.1
13.2
13.3
13.4
13.5

1188

Timers

...........................................................................................................................
General-Purpose Timers ..................................................................................
Block Diagram ................................................................................................
Functional Description ....................................................................................
Initialization and Configuration .........................................................................
General-Purpose Timer Registers .....................................................................

Page

1189
1190
1190
1200
1203

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timers

www.ti.com

13.1 General-Purpose Timers
Programmable timers can be used to count or time external events that drive the timer input pins. The
general-purpose timer module (GPTM) of the CC26x0 and CC13x0 devices provides two 16-bit timers
(Timer A and Timer B) that can be configured to operate independently as timers or concatenated to
operate as one 32-bit timer.
The GPTM is one timing resource available on the CC26x0 and CC13x0 MCU. Other timer resources
include the system timer (SysTick) and the watchdog timer (WDT). For reference, see Section 3.2.1 and
Chapter 15.
The GPTM contains four GPTM blocks with the following functional options:
• Operating modes:
– 16-bit with 8-bit prescaler or 32-bit programmable one-shot timer
– 16-bit with 8-bit prescaler or 32-bit programmable periodic timer
– Two capture compare PWM pins (CCP) for each 32-bit timer
– 24-bit input-edge count or 24-bit time-capture modes
– 24-bit PWM mode with software-programmable output inversion of the PWM signal
• Count up or down
• Daisy chaining of timer modules allows a single timer to initiate multiple timing events
• Timer synchronization allows selected timers to start counting on the same clock cycle
• User-enabled stalling when the microcontroller asserts a CPU Halt flag during debug
• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the
interrupt service routine

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1189

Block Diagram

www.ti.com

13.2 Block Diagram
Figure 13-1 shows the GPTM module block diagram.
Figure 13-1. GPTM Module Block Diagram
0x0000 (Down Counter Mode, 16/32-Bit)
0xFFFF (Up Counter Modes, 16/32-Bit)
0x0000 0000 (Down Counter Modes, 16/32-Bit)
0xFFFF FFFF (Up Counter Modes, 16/32-Bit)
32 kHz or
TIMER A
PWM

Timer A
Control

Timer A Free-Running Value

TAPS
TAPMR

TA Comparator

TAPR
Interrupt / Configure
Timer A
Interrupt

ANDCCP

TAMATCHR
TAILR

CFG

TAMR

TAR

Clock / Edge
Detect

CTL

TIMER A
CCP PIN

IMR
TAV

RIS
Timer B
Interrupt

MIS
ICLR

DMA
Request

TAPV

SYNC

Timer B
Control

DMAEV

TBMR
TBLIR

TBV
TBPV

TBR

TBMATCHR
Timer B Free-Running Value

TIMER B
CCP PIN

TBPR
TBPMR
TBPS

TB Comparator

TIMER B
PWM

0x0000 (Down Counter Mode, 16/32-Bit)
0xFFFF (Up Counter Modes, 16/32-Bit)
0x0000 0000 (Down Counter Modes, 16/32-Bit)
0xFFFF FFFF (Up Counter Modes, 16/32-Bit)
PERDMACLK

13.3 Functional Description
The main components of each GPTM block are: two free-running up and down counters (Timer A and
Timer B), two match registers, two prescaler match registers, two shadow registers, and two load and
initialization registers and their associated control functions. The exact function of each GPTM is
controlled by software and configured through the register interface. Timer A and Timer B can be used
individually, in which case they have a 16-bit counting range. In addition, Timer A and Timer B can be
concatenated to provide a 32-bit counting range. The prescaler can only be used when the timers are
used individually.
Table 13-1 lists the available modes for each GPTM block. When counting down in one-shot or periodic
modes, the prescaler acts as a true prescaler and contains the least-significant bits (LSBs) of the count.
When counting up in one-shot or periodic modes, the prescaler acts as a timer extension and holds the
most-significant bits (MSBs) of the count. In input edge count, input edge time, and PWM mode, the
prescaler always acts as a timer extension, regardless of the count direction.

1190Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Functional Description

www.ti.com

Table 13-1. General-Purpose Timer Capabilities
Mode
One-Shot

Periodic

Counter Size

Prescaler Size (1)

Up or Down

16-bit

8-bit

Concatenated

Up or Down

32-bit

–

Individual

Up or Down

16-bit

8-bit

Timer Use

Count Direction

Individual

Prescaler Behavior
(Count Direction)
Timer Extension (Up),
Prescaler (Down)
N/A
Timer Extension (Up),
Prescaler (Down)

Concatenated

Up or Down

32-bit

–

Edge Count

Individual

Up or Down

16-bit

8-bit

Timer Extension (Both)

Edge Time

Individual

Up or Down

16-bit

8-bit

Timer Extension (Both)

PWM

Individual

Down

16-bit

8-bit

Timer Extension

(1)

N/A

The prescaler is available only when the timers are used individually.

Software configures the GPTM using the GPTM Configuration Register (GPT:CFG), the GPTM Timer A
Mode Register (GPT:TAMR), and the GPTM Timer B Mode Register (GPT:TBMR). When in one of the
concatenated modes, Timer A and Timer B can operate in one mode only. However, when configured in
an individual mode, Timer A and Timer B can be independently configured in any combination of the
individual modes.

13.3.1 GPTM Reset Conditions
After reset is applied to the GPTM, the module is in an inactive state, and all control registers are cleared
and are in their default states. Counters (Timer A and Timer B) are initialized to all 1s, along with their
corresponding load registers: the GPTM Timer A Interval Load Register (GPT:TAILR) and the GPTM
Timer B Interval Load Register (GPT:TBILR). The prescale counters are initialized to 0x00:
• The GPTM Timer A Prescale Register (GPT:TAPR) and the GPTM Timer B Prescale Register
(GPT:TBPR)
• The GPTM Timer A Prescale Snapshot Register (GPT:TAPS) and the GPTM Timer B Prescale
Snapshot Register (GPT:TBPS)
• The GPTM Timer A Prescale Value Register (GPT:TAPV) and the GPTM Timer B Prescale Value
Register (GPT:TBPV)

13.3.2 Timer Modes
This section describes the operation of the various timer modes. When using Timer A and Timer B in
concatenated mode, only the Timer A control and status bits must be used; there is no need to use the
Timer B control and status bits. The GPTM is placed into individual or split mode by writing a value of 0x4
to the GPTM Configuration Register (GPT:CFG). In the following sections, the variable n is used in bit field
and register names to imply either a Timer A function or a Timer B function. Throughout this section, the
time-out event in down-count mode is 0x0; in up-count mode the time-out event is the value in the GPTM
Interval Load Register (GPT:TnILR) and the optional GPTM Timer n Prescale Register (GPT:TnPR).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1191

Functional Description

www.ti.com

13.3.2.1 One-Shot or Periodic Timer Mode
The selection of one-shot or periodic mode is determined by the value written to the GPTM Timer n Mode
Register (GPT:TnMR) TnMR field. The timer is configured to count up or down using the GPT:TnMR
TnCDIR bit.
When software sets the GPTM Control Register (GPTIMER:CTL) TnEN bit, the timer begins counting up
from 0x0, or down from its preloaded value. Alternatively, if the GPT:TnMR register TnWOT bit is set when
the TnEN bit is set, the timer waits for a trigger to begin counting (see Section 13.3.3).
When the timer is counting down and reaches the time-out event (0x0), the timer reloads its start value
from the GPT:TnILR and the GPT:TnPR registers on the next cycle. When the timer is counting up and
reaches the time-out event (the value in the GPT:TnILR and the optional GPT:TnPR registers), the timer
reloads with 0x0. If configured to be a one-shot timer, the timer stops counting and clears the GPT:CTL
TnEN register bit. If configured as a periodic timer, the timer starts counting again on the next cycle. In
periodic snap-shot mode (the TnMR field is 0x2 and the GPT:TnMR TnSNAPS register bit is set), the
actual free-running value of the timer at the time-out event is loaded into the GPT:TnR register. In this
manner, software can determine the time elapsed from the interrupt assertion to the ISR entry by
examining the snapshot values and the current value of the free-running timer, which is stored in the
GPT:TnV register. Snapshot mode is not available when the timer is configured in one-shot mode.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches the
time-out event. The GPTM sets the GPTM Raw Interrupt Status Register (GPT:RIS) TnTORIS bit, and
holds the bit until it is cleared by writing the GPTM Interrupt Clear Register (GPT:ICR). If the time-out
interrupt is enabled in the GPTM Interrupt Mask Register (GPT:IMR), the GPTM also sets the GPTM
Masked Interrupt Status Register (GPT:MIS) TnTOMIS bit. By setting the GPT:TnMR TnMIE register bit,
an interrupt condition can also be generated when the timer value equals the value loaded into the GPTM
Timer n Match Register (GPT:TnMATCHR) and the GPTM Timer n Prescale Match Register
(GPT:TnPMR). This interrupt has the same status, masking, and clearing functions as the time-out
interrupt but uses the match interrupt bits instead (for example, the raw interrupt status is monitored
through the GPTM Raw Interrupt Status Register (GPT:RIS) TnMRIS bit). The interrupt status bits are not
updated by the hardware unless the GPT:TnMR TnMIE register bit is set, which is different than the
behavior for the time-out interrupt.
If software updates the GPT:TnILR or the GPT:TnPR registers while the counter is counting down, the
counter loads the new value on the next clock cycle and continues counting from the new value if the
GPT:TnMR TnILD register bit is clear. If the TnILD bit is set, the counter loads the new value after the
next time out. If software updates the GPT:TnILR register or the GPT:TnPR register while the counter is
counting up, the time-out event is changed on the next cycle to the new value. If software updates the
GPTM Timer n Value Register (GPT:TnV) while the counter is counting up or down, the counter loads the
new value on the next clock cycle and continues counting from the new value. If software updates the
GPT:TnMATCHR register or the GPT:TnPMR register while the counter is counting, the match registers
reflect the new values on the next clock cycle if the GPT:TnMR TnMRSU register bit is clear. If the
TnMRSU bit is set, the new value does not take effect until the next time out.
If the GPT:CTL TnSTALL register bit is set, the timer freezes counting while the processor is halted by the
debugger. The timer resumes counting when the processor resumes execution.
Table 13-2 lists a variety of configurations for a 16-bit free-running timer while using the prescaler. All
values assume a 24-MHz clock with Tc = 41.67 ns (clock period). The prescaler can only be used when a
16- or 32-bit timer is configured in 16-bit mode.

1192Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated

Functional Description

www.ti.com

Table 13-2. 16-Bit Timer With Prescaler Configurations

(1)

Prescale (8-bit Value)

Number of Timer Clocks (Tc) (1)

Maximum Time

Unit

00000000

2.7

00000001

5.4

00000010

8.1

–

11111101

254

685.8

11111110

255

688.5

11111111

256

691.2

Tc is the clock period.

13.3.2.2 Input Edge-Count Mode
NOTE: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be low for
at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is ¼ of the system frequency.

In edge-count mode, the timer is configured as a 24-bit down counter, including the optional prescaler with
the upper count value stored in the GPTM Timer n Prescale Register (GPT:TnPR) and the lower bits in
the GPT:TnR register. In this mode, the timer is capable of capturing three types of events: rising edge,
falling edge, or both. To place the timer in edge-count mode, the GPT:TnMR register TnCMR bit must be
cleared. The type of edge that the timer counts is determined by the GPT:CTL register TnEVENT fields.
During initialization in down-count mode, the GPT:TnMATCHR and the GPT:TnPMR registers are
configured so that the difference between the value in the GPT:TnILR and the GPT:TnPR registers and
the GPT:TnMATCHR and the GPT:TnPMR registers equals the number of edge events that must be
counted. In up-count mode, the timer counts from 0x0 to the value in the GPT:TnMATCHR and the
GPT:TnPMR registers. Table 13-3 lists the values that are loaded into the timer registers when the timer is
enabled.
Table 13-3. Counter Values When the Timer is Enabled in Input Edge-Count Mode
Register

Count Down Mode

Count Up Mode

GPT:TnR

GPT:TnILR

0x0

GPT:TnV

GPT:TnILR

0x0

GPT:TnPV

GPT:TnPR

0x0

When software writes the GPTM Control Register (GPT:CTL) TnEN bit, the timer is enabled for event
capture. Each input event on the CCP pin decrements or increments the counter by 1 until the event count
matches the GPT:TnMATCHR and the GPT:TnPMR registers. When the counts match, the GPTM asserts
the GPTM Raw Interrupt Status Register (GPT:RIS) CnMRIS bit, and holds the bit until it is cleared by
writing the GPTM Interrupt Clear Register (GPT:ICR). If the capture mode match interrupt is enabled in
the GPTM Interrupt Mask Register (GPT:IMR), the GPTM also sets the GPTM Masked Interrupt Status
Register (GPT:MIS) CnMMIS bit. In this mode, the GPT:TnR register holds the count of the input events
while the GPT:TnV and the GPT:TnPV registers hold the free-running timer value and the free-running
prescaler value.
In addition to generating interrupts, a DMA trigger can be generated. The DMA trigger is enabled by
configuring and enabling the appropriate DMA channel.
After the match value is reached in down-count mode, the counter is then reloaded using the value in the
GPT:TnILR and the GPT:TnPR registers, and stopped because the GPTM automatically clears the
GPT:CTL TnEN register bit. Once the event count has been reached, all further events are ignored until
the TnEN bit is re-enabled by software. In up-count mode, the timer is reloaded with 0x0 and continues
counting.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1193

Functional Description

www.ti.com

Figure 13-2 shows how Input edge-count mode works. In this case, the timer start value is set to
GPT:TnILR = 0x000A, and the match value is set to GPT:TnMATCHR = 0x0006 so that four edge events
are counted. The counter is configured to detect both edges of the input signal.
NOTE:

The last two edges are not counted, because the timer automatically clears the TnEN bit
after the current count matches the value in the GPT:TnMATCHR register.

Figure 13-2. Input Edge-Count Mode Example, Counting Down
Timer stops,
flags
asserted

Count

Timer reload
on next cycle

Ignored

0x000A
0x0009
0x0008
0x0007
0x0006

Input Signal

13.3.2.3 Input Edge-Time Mode
NOTE: For rising-edge detection, the input signal must be high for at least two system-clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be low for
at least two system-clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is ¼ of the system frequency.

In edge-time mode, the timer is configured as a 24-bit down counter, including the optional prescaler with
the upper timer value stored in the GPT:TnPR register and the lower bits in the GPT:TnILR register. In this
mode, the timer is initialized to the value loaded in the GPT:TnILR and the GPT:TnPR registers when
counting down and 0x0 when counting up. The timer is capable of capturing three types of events: rising
edge, falling edge, or both. The timer is placed into edge-time mode by setting the GPT:TnMR TnCM
register bit, and the type of event that the timer captures is determined by the GPT:CTL TnEVENT register
fields. Table 13-4 lists the values that are loaded into the timer registers when the timer is enabled.
Table 13-4. Counter Values When the Timer is Enabled in Input Event-Count Mode
Register

Count Down Mode

Count Up Mode

GPT:TnR

GPT:TnILR

0x0

GPT:TnV

GPT:TnILR

0x0

GPT:TnPV

GPT:TnPR

0x0

When software writes to the GPT:CTL TnEN register bit, the timer is enabled for event capture. When the
selected input event is detected, the current timer counter value is captured in the GPT:TnR register and
is available to be read by the microcontroller. The GPTM then asserts the GPTM Raw Interrupt Status
Register (GPT:RIS) CnERIS bit, and holds the bit until it is cleared by writing the GPTM Interrupt Clear
Register (GPT:ICR). If the capture mode event interrupt is enabled in the GPTM Interrupt Mask Register
1194

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

(GPT:IMR), the GPTM also sets the GPTM Masked Interrupt Status Register (GPT:MIS) CnEMIS bit. In
this mode, the GPT:TnR register holds the time at which the selected input event occurred, while the
GPT:TnV and the GPT:TnPV registers hold the free-running timer value and the free-running prescaler
value. These registers can be read to determine the time that elapsed between the interrupt assertion and
the entry into the ISR.
In addition to generating interrupts a DMA trigger can be generated. This trigger is enabled by
configuring and enabling the appropriate DMA channel.
After an event has been captured, the timer does not stop counting. The timer continues to count until the
TnEN bit is cleared. When the timer reaches the timeout value, it is reloaded with 0x0 in up-count mode,
and the value from the GPT:TnILR and the GPT:TnPR registers in down-count mode.
Figure 13-3 shows how input edge timing mode works. In the diagram, it is assumed that the start value of
the timer is the default value of 0xFFFF, and the timer is configured to capture rising-edge events.
Each time a rising-edge event is detected, the current count value is loaded into the GPTIMER:TnR
register, and is held there until another rising edge is detected (at which point the new count value is
loaded into the GPT:TnR register).
Figure 13-3. Input Edge-Time Mode Example
Count
0xFFFF

GPTMTnR=X

GPTMTnR=Y

GPTMTnR=Z

Y
Time

Input Signal

NOTE: When operating in edge-time mode, the counter uses a modulo 224 count if prescaler is
enabled, or 216 if prescaler is not enabled. If there is a possibility the edge could take longer
than the count, another timer can be used to ensure detection of the missed edge.

13.3.2.4 PWM Mode
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a 16-bit
down counter with a start value (and thus, period) defined by the GPT:TnILR and the GPT:TnPR registers.
In this mode, the PWM frequency and period are synchronous events; therefore, they are ensured to be
glitch-free. PWM mode is enabled with the GPT:TnMR register by setting the TnAMS bit to 0x1, setting the
TnCM bit to 0x0, and setting the TnMR field to 0x2. Table 13-5 lists the values that are loaded into the
timer registers when the timer is enabled.
NOTE: Wait on trigger (daisy chaining) is not supported in PWM mode. The timer starts as soon as
it is enabled and does not wait for a trigger from the previous timer.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1195

Functional Description

www.ti.com

Table 13-5. Counter Values When the Timer is Enabled in PWM Mode
Register

Count Down Mode

Count Up Mode

GPT:TnR

GPT:TnILR

Not Available

GPT:TnV

GPT:TnILR

Not Available

GPT:TnPV

GPT:TnPR

Not Available

When software writes to the GPT:CTL TnEN register bit, the counter begins counting down until it reaches
the 0x0 state. Alternatively, if the GPT:TnMR TnWOT register bit is set when the TnEN bit is set, the timer
waits for a trigger to begin counting. On the next counter cycle in periodic mode, the counter reloads its
start value from the GPT:TnILR and the GPT:TnPR registers, and continues counting until disabled by
software clearing the GPT:CTL TnEN register bit. The timer is capable of generating interrupts based on
three types of events: rising edge, falling edge, or both. The event is configured by the GPT:CTL
TnEVENT register field, and the interrupt is enabled by setting the GPT:TnMR TnPWMIE register bit.
When the event occurs, the GPTM Raw Interrupt Status Register (GPT:RIS) CnERIS bit is set, and holds
the bit until it is cleared by writing the GPTM Interrupt Clear Register (GPT:ICLR). If the capture mode
event interrupt is enabled in the GPTM Interrupt Mask Register (GPT:IMR), the GPTM also sets the
GPTM Masked Interrupt Status Register (GPT:MIS) CnEMIS bit.
NOTE: The interrupt status bits are not updated unless the TnPWMIE bit is set.

In PWM mode, the GPT:TnR and the GPT:TnV registers always have the same value, as do the
GPT:PnPS and the GPT:TnPV registers.
The output PWM signal asserts when the counter is at the value of the GPT:TnILR and the GPT:TnPR
registers (its start state), and is deasserted when the counter value equals the value in the
GPT:TnMATCHR and the GPT:TnPMR registers. Software can invert the output PWM signal by setting
the GPT:CTL TnPWML register bit. Inverting the output PWM does not affect the edge detection interrupt.
Therefore, if a positive-edge interrupt trigger has been set, the event-trigger interrupt is asserted when the
PWM inversion generates a positive edge.
NOTE: Note that altering TnILR to a value smaller than the current counter value, may introduce
transients on the PWM output even when the “Time Out UPDATE” mode is enabled.

Figure 13-4 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a
50-MHz input clock and TnPWML = 0 (duty cycle would be 33% for the TnPWML = 1 configuration). For
this example, the start value is GPT:TnILR = 0xC350 and the match value is GPT:TnMATCHR = 0x411A.

1196

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

Figure 13-4. 16-Bit PWM Mode Example

Count GPTMTnR=GPTMnMRGPTMTnR=GPTMnMR
0xC350

0x411A

Time
TnEN set
Output
Signal

TnPWML = 0
TnPWML = 1

When synchronizing the timers using the GPT:SYNC register, the timer must be properly configured to
avoid glitches on the CCP outputs. Both the TnPLO and the TnMRSU bits must be set in the GPT:TnMR
register. Figure 13-5 shows how the CCP output operates when the TnPLO and TnMRSU bits are set and
the GPT:TnMATCHR register value is greater than the GPT:TnILR register value.
Figure 13-5. CCP Output, GPT:TnMATCHR > GPT:TnILR
GPTMnMATCHR

CounterValue

GPTMnILR

CCP
CCP set if GPTMnMATCHR ≠ GPTMnILR

Figure 13-6 shows how the CCP output operates when the PLO and MRSU bits are set and the
GPT:TnMATCHR register value is the same as the GPT:TnILR register value. In this situation, if the PLO
bit is 0, the CCP signal goes high when the GPT:TnILR register value is loaded, and the match would be
essentially ignored.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1197

Functional Description

www.ti.com

Figure 13-6. CCP Output, GPT:TnMATCHR = GPT:TnILR
GPTMnMATCHR

CounterValue

GPTMnILR

CCP
CCP not set if GPTMnMATCHR = GPTMnILR

Figure 13-7 shows how the CCP output operates when the PLO and MRSU bits are set and the
GPT:TnILR register value is greater than the GPT:TnMATCHR register value.
Figure 13-7. CCP Output, GPT:TnILR > GPT:TnMATCHR
GPTMnILR
GPTMnMATCHR = GPTMnILR-1
GPTMnMATCHR = GPTMnILR-2

GPTMnMATCHR == 0

CCP

Pulse width is 1 clock when GPTMnMATCHR = GPTMnILR - 1

CCP

Pulse width is 2 clocks when GPTMnMATCHR = GPTMnILR - 2

CCP

Pulse width is GPTMnMATCHR clocks when GPTMnMATCHR= 0

13.3.3 Wait-for-Trigger Mode
Wait-for-trigger mode allows daisy-chaining of the timer modules such that once configured, a single timer
can initiate multiple timing events using the timer triggers. Wait-for-trigger mode is enabled by setting the
GPT:TnMR TnWOT register bit. When the TnWOT bit is set, timer N+1 does not begin counting until the
timer in the previous position in the daisy-chain (timer N) reaches its time-out event. The daisy-chain is
configured such that GPTM1 always follows GPTM0, GPTM2 follows GPTM1, and so forth. If Timer A is
configured as a 32-bit (16 or 32-bit mode) timer (controlled by the CFG field in the GPT:CFG register), it
triggers Timer A in the next module. If Timer A is configured as a 16-bit (16- or 32-bit mode) timer, it
triggers Timer B in the same module and Timer B triggers Timer A in the next module. Ensure that the
TAWOT bit is never set in GPTM0. Figure 13-8 shows how the GPT:CFG CFG register bit affects the
daisy-chain. This function is valid for one-shot and periodic modes.

1198

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

Figure 13-8. Timer Daisy-Chain

GP Timer N+1
1

GPTMCFG

Timer B
Timer A

GP Timer N
1

GPTMCFG

Timer B
Timer A

13.3.4 Synchronizing GPT Blocks
The GPTM Synchronizer Control Register (GPT:SYNC) in the GPTM0 block can be used to synchronize
selected timers to begin counting at the same time. To do so, the timers must be started first. Setting a bit
in the GPT:SYNC register causes the associated timer to perform the actions of a time-out event. An
interrupt is not generated when the timers are synchronized. If a timer is being used in concatenated
mode, only the bit for Timer A must be set in the GPT:SYNC register. The register description shows
which timers can be synchronized.
Table 13-6 lists the actions for the time-out event performed when the timers are synchronized in the
various timer modes.
Table 13-6. Time-Out Actions for GPTM Modes
Mode

Count Direction

Time-out Action

Down

Count value = ILR

Count Value = 0

Down

Count value = ILR

Count value = 0

Down

Count value = ILR

16-bit and 32-bit one-shot (concatenated timers)
16- bit and 32-bit periodic (concatenated timers)

N/A

16-bit and 32- bit one-shot (individual and split timers)
16-bit and 32- bit periodic (individual and split timers)
16-bit and 32-bit edge-count (individual and split timers)
16-bit and 32-bit edge-time (individual and split timers)
16-bit PWM

N/A

Count Value = 0

Down

Count value = ILR

Count Value = 0

Down

Count value = ILR

13.3.5 Accessing Concatenated 16- and 32-Bit GPTM Register Values
The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTM Configuration
Register (GPT:CFG) GPTMCFG bit field. In both configurations, certain 16- and 32-bit GPTM registers are
concatenated to form pseudo 32-bit registers. These registers include the following:
• GPTM Timer A Interval Load Register (GPT:TAILR[15:0])
• GPTM Timer B Interval Load Register (GPT:TBILR[15:0])
• GPTM Timer A Register (GPT:TAR[15:0])
• GPTM Timer B Register (GPT:TBR[15:0])
• GPTM Timer A Value Register (GPT:TAV[15:0])
• GPTM Timer B Value Register (GPT:TBV[15:0])
• GPTM Timer A Match Register (GPT:TAMATCHR[15:0])
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1199

Initialization and Configuration

•

www.ti.com

GPTM Timer B Match Register (GPT:TBMATCHR[15:0])

In the 32-bit modes, the GPTM translates a 32-bit write access to the GPT:TAILR register into a write
access to both the GPT:TAILR and the GPT:TBILR registers. The resulting word ordering for such a write
operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]. Likewise, a 32-bit read access to GPT:TAR
register returns the value GPTMTBR[15:0]:GPTMTAR[15:0]. A 32-bit read access to GPT:TAV returns
the value
GPTMTBV[15:0]:GPTMTAV[15:0].

13.4 Initialization and Configuration
1. To use a GPT module, enable the peripheral domain and the appropriate GPT module in the PRCM by
writing to the PRCM:GPTCLKGR, the PRCM:GPTCLKGS, and the PRCM:GPTCLKGDS registers, or
by using the following driver library functions:
PRCMPeripheralRunEnable(uint32_t, ui32Peripheral)
PRCMPeripheralSleepEnable(uint32_t, ui32Peripheral)
PRCMPeripheralDeepSLeepEnable(uint32_t, ui32Peripheral)

2. Next, load the setting to the clock controller by writing to the PRCM:CLKLOADCTL register.
3. Configure the IOC module to route the output from the GPT module to the IOs.
4. The IOC module must then be configured to output the timer signal on the wanted I/O pin. For this,
IOCFGn.PORTID must be written to the correct PORTIDs (for more details, see Chapter 11).
The following sections show module initialization and configuration examples for each of the supported
timer modes.

13.4.1 One-Shot and Periodic Timer Modes
The GPTM is configured for one-shot and periodic modes by the following sequence:
1. Ensure the timer is disabled (clear the GPT:CTL TnEN register bit) before making any changes.
2. Write the GPTM Configuration Register (GPT:CFG) with a value of 0x0000 0000.
3. Configure the GPTM Timer n Mode Register (GPT:TnMR) TnMR field:
(a) Write a value of 0x1 for one-shot mode.
(b) Write a value of 0x2 for periodic mode.
4. Optionally, configure the GPT:TnMR TnSNAPS, TnWOT, TnMTE, and TnCDIR register bits to select
whether to capture the value of the free-running timer at time-out, use an external trigger to start
counting, configure an additional trigger or interrupt, and count up or down.
5. Load the start value into the GPTM Timer n Interval Load Register (GPT:TnILR).
6. If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask Register (GPT:IMR).
7. Set the GPT:CTL TnEN register bit to enable the timer and start counting.
8. Poll the GPT:MRIS register or wait for the interrupt to be generated (if enabled). In both cases, the
status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear Register
(GPT:ICR).
In one-shot mode, the timer stops counting after the time-out event. To re-enable the timer, repeat the
sequence. A timer configured in periodic mode reloads the timer and continues counting after the time-out
event.

1200

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Initialization and Configuration

www.ti.com

13.4.2 Input Edge-Count Mode
A timer is configured to input edge-count mode by the following sequence:
1. Ensure the timer is disabled (clear the TAEN bit) before making any changes.
2. Write the GPTM Configuration Register (GPT:CFG) with a value of 0x0000 0004.
3. In the GPTM Timer Mode Register (GPT:TnMR), write the TnCMR field to 0x0 and the TnMR field to
0x3.
4. Configure the type of events that the timer captures by writing the GPTM Control Register (GPT:CTL)
TnEVENT field.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
(GPT:TnPR).
6. Load the timer start value into the GPTM Timer n Interval Load Register (GPT:TnILR).
7. Load the event count into the GPTM Timer n Match Register (GPT:TnMATCHR).
8. If interrupts are required, set the GPTM Interrupt Mask Register (GPT:IMR) CnMIM bit.
9. Set the GPT:CTL TnEN register bit to enable the timer and begin waiting for edge events.
10. Poll the GPT:RIS CnMRIS register bit, or wait for the interrupt to be generated (if enabled). In both
cases, the status flags are cleared by writing a 1 to the GPTM Interrupt Clear Register (GPT:ICR)
CnMCINT bit.
When counting down in input edge-count mode, the timer stops after the programmed number of edge
events is detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat Step 4 through
Step 9.

13.4.3 Input Edge-Timing Mode
A timer is configured to input edge-timing mode by the following sequence:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPT:CFG) with a value of 0x0000 0004.
3. In the GPTM Timer Mode Register (GPT:TnMR), write the TnCM field to 0x1 and write the TnMR field
to 0x3.
4. Configure the type of events that the timer captures by writing the GPTM Control Register (GPT:CTL)
TnEVENT field.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
(GPT:TnPR).
6. Load the timer start value into the GPTM Timer n Interval Load Register (GPT:TnILR).
7. If interrupts are required, set the GPTM Interrupt Mask Register (GPT:IMR) CnMIM bit.
8. Set the GPT:CTL TnEN register bit to enable the timer and start counting.
9. Poll the GPT:RIS CnMRIS register bit, or wait for the interrupt to be generated (if enabled). In both
cases, the status flags are cleared by writing a 1 to the GPTM Interrupt Clear Register (GPT:ICR)
CnMCINT bit.
In input-edge timing mode, the timer continues to run after an edge event is detected, but the timer
interval can be changed at any time by writing the GPT:TnILR register. The change takes effect at the
next cycle after the write.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1201

Initialization and Configuration

www.ti.com

13.4.4 PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (clear the TnEN bit) before making any changes.
2. Write the GPTM Configuration Register (GPT:CFG) with a value of 0x0000 0004.
3. In the GPTM Timer Mode Register (GPT:TnMR), write the TnCMR field to 0x1 and write the TnMR
field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the GPTM Control
Register (GPT:CTL) TnPWML field.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
(GPT:TnPR).
6. If PWM interrupts are used, configure the interrupt condition in the GPT:CTL TnEVENT register field,
and enable the interrupts by setting the GPT:TnMR TnPWMIE register bit.
7. Load the timer start value into the GPTM Timer n Interval Load Register (GPT:TnILR).
8. Load the GPTM Timer n Match Register (GPT:TnMATCHR) with the match value.
9. Set the GPTM Control Register (GPT:CTL) TnEN bit to enable the timer and begin generation of the
output PWM signal.
In PWM timing mode, the timer continues to run after the PWM signal is generated. The PWM period can
be adjusted at any time by writing the GPT:TnILR register, and the change takes effect at the next cycle
after the write.

13.4.5 Producing DMA Trigger Events
The GPT can produce DMA trigger events through the event handler. Single or burst requests can be
passed to the µDMA controller by selecting the trigger source for µDMA channels through the event fabric.
Each timer only produces one signal per A and B, but this signal can be selected as either single or burst
in the event module. The DMA done interrupt is routed back to the timer module that originated the trigger.
The following is a procedure for configuring µDMA triggers by GPT events.
1. Configure the GPT operation.
2. Configure the GPT:DMAEV register to enable the appropriate timer event to DMA. The application can
select a match, capture, or time-out event for each timer.
3. Configure the event fabric (see Chapter 4) to select the appropriate timer. The event fabric supports
five channels for the GPT DMA event, out of which four are dedicated to the GPT block. These
dedicated channels are: 9, 10, 11, and 12. Single requests and burst requests are supported on
channels 9 through 12 for GPT DMA events. The fifth supported channel is 14, which is configurable
for GPT support and handles only burst requests. The configuration is done through the
EVENT:UDMACHcrSEL register where c is channel number and r is either S (single) or B (burst)
option. The configuration for channel 14 can be done using the EVENT:UDMACH14BSEL register.
Each timer produces only one signal per A and B, but this signal can be selected as either single or
burst in the event module.
4. Enable the GPT.
5. The DMA done interrupt is routed back to the timer module that originated the trigger. The GPT:RIS
DMAnRIS register bit gives the DMA transfer completed information.

1202

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5 General-Purpose Timer Registers
13.5.1 GPT Registers
Table 13-7 lists the memory-mapped registers for the GPT. All register offset addresses not listed in
Table 13-7 should be considered as reserved locations and the register contents should not be modified.
Table 13-7. GPT Registers
Offset

Acronym

Section

CFG

Configuration

Section 13.5.1.1

TAMR

Timer A Mode

Section 13.5.1.2

TBMR

Timer B Mode

Section 13.5.1.3

CTL

Control

Section 13.5.1.4

10h

SYNC

Synch Register

Section 13.5.1.5

18h

IMR

Interrupt Mask

Section 13.5.1.6

1Ch

RIS

Raw Interrupt Status

Section 13.5.1.7

20h

MIS

Masked Interrupt Status

Section 13.5.1.8

24h

ICLR

Interrupt Clear

Section 13.5.1.9

28h

TAILR

Timer A Interval Load Register

Section 13.5.1.10

2Ch

TBILR

Timer B Interval Load Register

Section 13.5.1.11

30h

TAMATCHR

Timer A Match Register

Section 13.5.1.12

34h

TBMATCHR

Timer B Match Register

Section 13.5.1.13

38h

TAPR

Timer A Pre-scale

Section 13.5.1.14

3Ch

TBPR

Timer B Pre-scale

Section 13.5.1.15

40h

TAPMR

Timer A Pre-scale Match

Section 13.5.1.16

44h

TBPMR

Timer B Pre-scale Match

Section 13.5.1.17

48h

TAR

Timer A Register

Section 13.5.1.18

4Ch

TBR

Timer B Register

Section 13.5.1.19

50h

TAV

Timer A Value

Section 13.5.1.20

54h

TBV

Timer B Value

Section 13.5.1.21

5Ch

TAPS

Timer A Pre-scale Snap-shot

Section 13.5.1.22

60h

TBPS

Timer B Pre-scale Snap-shot

Section 13.5.1.23

64h

TAPV

Timer A Pre-scale Value

Section 13.5.1.24

68h

TBPV

Timer B Pre-scale Value

Section 13.5.1.25

6Ch

DMAEV

DMA Event

Section 13.5.1.26

FB0h

VERSION

Peripheral Version

Section 13.5.1.27

FB4h

ANDCCP

Combined CCP Output

Section 13.5.1.28

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1203

General-Purpose Timer Registers

www.ti.com

13.5.1.1 CFG Register (Offset = 0h) [reset = 0h]
CFG is shown in Figure 13-9 and described in Table 13-8.
Return to Summary Table.
Configuration
Figure 13-9. CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

1 0
CFG
R/W-0h

Table 13-8. CFG Register Field Descriptions
Field

Type

Reset

Description

31-3

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

2-0

CFG

R/W

GPT Configuration
0x2- 0x3 - Reserved
0x5- 0x7 - Reserved
0h = 32BIT_TIMER : 32-bit timer configuration
4h = 16BIT_TIMER : 16-bit timer configuration.
Configure for two 16-bit timers.
Also see TAMR.TAMR and TBMR.TBMR.

1204

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.2 TAMR Register (Offset = 4h) [reset = 0h]
TAMR is shown in Figure 13-10 and described in Table 13-9.
Return to Summary Table.
Timer A Mode
Figure 13-10. TAMR Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

14
TCACT
R/W-0h

12
TACINTD
R/W-0h

11
TAPLO
R/W-0h

10
TAMRSU
R/W-0h

9
TAPWMIE
R/W-0h

8
TAILD
R/W-0h

7
TASNAPS
R/W-0h

6
TAWOT
R/W-0h

5
TAMIE
R/W-0h

4
TACDIR
R/W-0h

3
TAAMS
R/W-0h

2
TACM
R/W-0h

0
TAMR
R/W-0h

Table 13-9. TAMR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-13

TCACT

R/W

Timer Compare Action Select
0h = DIS_CMP : Disable compare operations
1h = Toggle State on Time-Out
2h = Clear CCP output pin on Time-Out
3h = Set CCP output pin on Time-Out
4h = Set CCP output pin immediately and toggle on Time-Out
5h = Clear CCP output pin immediately and toggle on Time-Out
6h = Set CCP output pin immediately and clear on Time-Out
7h = Clear CCP output pin immediately and set on Time-Out

TACINTD

R/W

One-Shot/Periodic Interrupt Disable
0h = Time-out interrupt function as normal
1h = Time-out interrupt are disabled

TAPLO

R/W

GPTM Timer A PWM Legacy Operation
0 Legacy operation with CCP pin driven Low when the TAILR
register is reloaded after the timer reaches 0.
1 CCP is driven High when the TAILR register is reloaded after the
timer reaches 0.
This bit is only valid in PWM mode.
0h = Legacy operation
1h = CCP output pin is set to 1 on time-out

TAMRSU

R/W

Timer A Match Register Update mode
This bit defines when the TAMATCHR and TAPR registers are
updated.
If the timer is disabled (CTL.TAEN = 0) when this bit is set,
TAMATCHR and TAPR are updated when the timer is enabled.
If the timer is stalled (CTL.TASTALL = 1) when this bit is set,
TAMATCHR and TAPR are updated according to the configuration
of this bit.
0h = Update TAMATCHR and TAPR, if used, on the next cycle.
1h = Update TAMATCHR and TAPR, if used, on the next time-out.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1205

General-Purpose Timer Registers

www.ti.com

Table 13-9. TAMR Register Field Descriptions (continued)
Bit

1206

Field

Type

Reset

Description

TAPWMIE

R/W

GPTM Timer A PWM Interrupt Enable
This bit enables interrupts in PWM mode on rising, falling, or both
edges of the CCP output, as defined by the CTL.TAEVENT
In addition, when this bit is set and a capture event occurs, Timer A
automatically generates triggers to the DMA if the trigger capability is
enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN
bit respectively.
0 Capture event interrupt is disabled.
1 Capture event interrupt is enabled.
This bit is only valid in PWM mode.
0h = Interrupt is disabled.
1h = Interrupt is enabled. This bit is only valid in PWM mode.

TAILD

R/W

GPT Timer A PWM Interval Load Write
0h = Update the TAR register with the value in the TAILR register on
the next clock cycle. If the pre-scaler is used, update the TAPS
register with the value in the TAPR register on the next clock cycle.
1h = Update the TAR register with the value in the TAILR register on
the next timeout. If the prescaler is used, update the TAPS register
with the value in the TAPR register on the next timeout.

TASNAPS

R/W

GPT Timer A Snap-Shot Mode
0h = Snap-shot mode is disabled.
1h = If Timer A is configured in the periodic mode, the actual freerunning value of Timer A is loaded at the time-out event into the GPT
Timer A (TAR) register.

TAWOT

R/W

GPT Timer A Wait-On-Trigger
0h = Timer A begins counting as soon as it is enabled.
1h = If Timer A is enabled (CTL.TAEN = 1), Timer A does not begin
counting until it receives a trigger from the timer in the previous
position in the daisy chain. This bit must be clear for GPT Module 0,
Timer A. This function is valid for one-shot, periodic, and PWM
modes

TAMIE

R/W

GPT Timer A Match Interrupt Enable
0h = The match interrupt is disabled for match events. Additionally,
output triggers on match events are prevented.
1h = An interrupt is generated when the match value in TAMATCHR
is reached in the one-shot and periodic modes.

TACDIR

R/W

GPT Timer A Count Direction
0h = DOWN : The timer counts down.
1h = UP : The timer counts up. When counting up, the timer starts
from a value of 0x0.

TAAMS

R/W

GPT Timer A Alternate Mode
Note: To enable PWM mode, you must also clear TACM and then
configure TAMR field to 0x2.
0h = Capture/Compare mode is enabled.
1h = PWM mode is enabled

TACM

R/W

GPT Timer A Capture Mode
0h = EDGCNT : Edge-Count mode
1h = EDGTIME : Edge-Time mode

1-0

TAMR

R/W

GPT Timer A Mode
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The Timer mode is based on the timer configuration defined by bits
2:0 in the CFG register
1h = One-Shot Timer mode
2h = Periodic Timer mode
3h = Capture mode

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.3 TBMR Register (Offset = 8h) [reset = 0h]
TBMR is shown in Figure 13-11 and described in Table 13-10.
Return to Summary Table.
Timer B Mode
Figure 13-11. TBMR Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

14
TCACT
R/W-0h

12
TBCINTD
R/W-0h

11
TBPLO
R/W-0h

10
TBMRSU
R/W-0h

9
TBPWMIE
R/W-0h

8
TBILD
R/W-0h

7
TBSNAPS
R/W-0h

6
TBWOT
R/W-0h

5
TBMIE
R/W-0h

4
TBCDIR
R/W-0h

3
TBAMS
R/W-0h

2
TBCM
R/W-0h

0
TBMR
R/W-0h

Table 13-10. TBMR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-13

TCACT

R/W

TBCINTD

R/W

One-Shot/Periodic Interrupt Mode
0h = Normal Time-Out Interrupt
1h = Mask Time-Out Interrupt

TBPLO

R/W

GPTM Timer B PWM Legacy Operation
0 Legacy operation with CCP pin driven Low when the TBILR
register is reloaded after the timer reaches 0.
1 CCP is driven High when the TBILR register is reloaded after the
timer reaches 0.
This bit is only valid in PWM mode.
0h = Legacy operation
1h = CCP output pin is set to 1 on time-out

TBMRSU

R/W

Timer B Match Register Update mode
This bit defines when the TBMATCHR and TBPR registers are
updated
If the timer is disabled (CTL.TBEN is clear) when this bit is set,
TBMATCHR and TBPR are updated when the timer is enabled.
If the timer is stalled (CTL.TBSTALL is set) when this bit is set,
TBMATCHR and TBPR are updated according to the configuration
of this bit.
0h = Update TBMATCHR and TBPR, if used, on the next cycle.
1h = Update TBMATCHR and TBPR, if used, on the next time-out.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1207

General-Purpose Timer Registers

www.ti.com

Table 13-10. TBMR Register Field Descriptions (continued)
Bit

1208

Field

Type

Reset

Description

TBPWMIE

R/W

GPTM Timer B PWM Interrupt Enable
This bit enables interrupts in PWM mode on rising, falling, or both
edges of the CCP output, as defined by the CTL.TBEVENT
In addition, when this bit is set and a capture event occurs, Timer A
automatically generates triggers to the DMA if the trigger capability is
enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN
bit respectively.
0 Capture event interrupt is disabled.
1 Capture event interrupt is enabled.
This bit is only valid in PWM mode.
0h = Interrupt is disabled.
1h = Interrupt is enabled. This bit is only valid in PWM mode.

TBILD

R/W

GPT Timer B PWM Interval Load Write
0h = Update the TBR register with the value in the TBILR register on
the next clock cycle. If the pre-scaler is used, update the TBPS
register with the value in the TBPR register on the next clock cycle.
1h = Update the TBR register with the value in the TBILR register on
the next timeout. If the prescaler is used, update the TBPS register
with the value in the TBPR register on the next timeout.

TBSNAPS

R/W

GPT Timer B Snap-Shot Mode
0h = Snap-shot mode is disabled.
1h = If Timer B is configured in the periodic mode

TBWOT

R/W

GPT Timer B Wait-On-Trigger
0h = Timer B begins counting as soon as it is enabled.
1h = If Timer B is enabled (CTL.TBEN is set), Timer B does not
begin counting until it receives a trigger from the timer in the
previous position in the daisy chain. This function is valid for oneshot, periodic, and PWM modes

TBMIE

R/W

GPT Timer B Match Interrupt Enable.
0h = The match interrupt is disabled for match events. Additionally,
output triggers on match events are prevented.
1h = An interrupt is generated when the match value in the
TBMATCHR register is reached in the one-shot and periodic modes.

TBCDIR

R/W

GPT Timer B Count Direction
0h = DOWN : The timer counts down.
1h = UP : The timer counts up. When counting up, the timer starts
from a value of 0x0.

TBAMS

R/W

GPT Timer B Alternate Mode
Note: To enable PWM mode, you must also clear TBCM bit and
configure TBMR field to 0x2.
0h = Capture/Compare mode is enabled.
1h = PWM mode is enabled

TBCM

R/W

GPT Timer B Capture Mode
0h = EDGCNT : Edge-Count mode
1h = EDGTIME : Edge-Time mode

1-0

TBMR

R/W

GPT Timer B Mode
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The Timer mode is based on the timer configuration defined by bits
2:0 in the CFG register
1h = One-Shot Timer mode
2h = Periodic Timer mode
3h = Capture mode

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.4 CTL Register (Offset = Ch) [reset = 0h]
CTL is shown in Figure 13-12 and described in Table 13-11.
Return to Summary Table.
Control
Figure 13-12. CTL Register
31

9
TBSTALL
R/W-0h

8
TBEN
R/W-0h

1
TASTALL
R/W-0h

0
TAEN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

15
RESERVED
R-0h

14
TBPWML
R/W-0h

7
RESERVED
R-0h

6
TAPWML
R/W-0h

RESERVED
R/W-0h

TBEVENT
R/W-0h
4

RESERVED
R/W-0h

3
TAEVENT
R/W-0h

Table 13-11. CTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TBPWML

R/W

GPT Timer B PWM Output Level
0: Output is unaffected.
1: Output is inverted.
0h = Not inverted
1h = Inverted

13-12

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-10

TBEVENT

R/W

GPT Timer B Event Mode
The values in this register are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
Note: If PWM output inversion is enabled, edge detection interrupt
behavior is reversed. Thus, if a positive-edge interrupt trigger
has been set and the PWM inversion generates a postive
edge, no event-trigger interrupt asserts. Instead, the interrupt
is generated on the negative edge of the PWM signal.
0h = Positive edge
1h = Negative edge
3h = Both edges

TBSTALL

R/W

GPT Timer B Stall Enable
0h = Timer B continues counting while the processor is halted by the
debugger.
1h = Timer B freezes counting while the processor is halted by the
debugger.

TBEN

R/W

GPT Timer B Enable
0h = Timer B is disabled.
1h = Timer B is enabled and begins counting or the capture logic is
enabled based on CFG register.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-15
14

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1209

General-Purpose Timer Registers

www.ti.com

Table 13-11. CTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

TAPWML

R/W

GPT Timer A PWM Output Level
0h = Not inverted
1h = Inverted

5-4

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-2

TAEVENT

R/W

GPT Timer A Event Mode
The values in this register are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
Note: If PWM output inversion is enabled, edge detection interrupt
behavior is reversed. Thus, if a positive-edge interrupt trigger
has been set and the PWM inversion generates a postive
edge, no event-trigger interrupt asserts. Instead, the interrupt
is generated on the negative edge of the PWM signal.
0h = Positive edge
1h = Negative edge
3h = Both edges

TASTALL

R/W

GPT Timer A Stall Enable
0h = Timer A continues counting while the processor is halted by the
debugger.
1h = Timer A freezes counting while the processor is halted by the
debugger.

TAEN

R/W

GPT Timer A Enable
0h = Timer A is disabled.
1h = Timer A is enabled and begins counting or the capture logic is
enabled based on the CFG register.

1210

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.5 SYNC Register (Offset = 10h) [reset = 0h]
SYNC is shown in Figure 13-13 and described in Table 13-12.
Return to Summary Table.
Synch Register
Figure 13-13. SYNC Register
31

12
11
RESERVED
R-0h

24
23
RESERVED
R-0h
8

7
SYNC3
W-0h

SYNC2
W-0h

SYNC1
W-0h

SYNC0
W-0h

Table 13-12. SYNC Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-6

SYNC3

Synchronize GPT Timer 3.
0h = No Sync. GPT3 is not affected.
1h = A timeout event for Timer A of GPT3 is triggered
2h = A timeout event for Timer B of GPT3 is triggered
3h = A timeout event for both Timer A and Timer B of GPT3 is
triggered

5-4

SYNC2

Synchronize GPT Timer 2.
0h = No Sync. GPT2 is not affected.
1h = A timeout event for Timer A of GPT2 is triggered
2h = A timeout event for Timer B of GPT2 is triggered
3h = A timeout event for both Timer A and Timer B of GPT2 is
triggered

3-2

SYNC1

Synchronize GPT Timer 1
0h = No Sync. GPT1 is not affected.
1h = A timeout event for Timer A of GPT1 is triggered
2h = A timeout event for Timer B of GPT1 is triggered
3h = A timeout event for both Timer A and Timer B of GPT1 is
triggered

1-0

SYNC0

Synchronize GPT Timer 0
0h = No Sync. GPT0 is not affected.
1h = A timeout event for Timer A of GPT0 is triggered
2h = A timeout event for Timer B of GPT0 is triggered
3h = A timeout event for both Timer A and Timer B of GPT0 is
triggered

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1211

General-Purpose Timer Registers

www.ti.com

13.5.1.6 IMR Register (Offset = 18h) [reset = 0h]
IMR is shown in Figure 13-14 and described in Table 13-13.
Return to Summary Table.
Interrupt Mask
This register is used to enable the interrupts.
Associated registers:
RIS, MIS, ICLR
Figure 13-14. IMR Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

13
DMABIM
R/W-0h

12
RESERVED
R-0h

11
TBMIM
R/W-0h

10
CBEIM
R/W-0h

9
CBMIM
R/W-0h

8
TBTOIM
R/W-0h

5
DMAAIM
R/W-0h

4
TAMIM
R/W-0h

3
RESERVED
R/W-0h

2
CAEIM
R/W-0h

1
CAMIM
R/W-0h

0
TATOIM
R/W-0h

RESERVED
R-0h
7
RESERVED
R-0h

Table 13-13. IMR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMABIM

R/W

Enabling this bit will make the RIS.DMABRIS interrupt propagate to
MIS.DMABMIS
0h = Disable Interrupt
1h = Enable Interrupt

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TBMIM

R/W

Enabling this bit will make the RIS.TBMRIS interrupt propagate to
MIS.TBMMIS
0h = Disable Interrupt
1h = Enable Interrupt

CBEIM

R/W

Enabling this bit will make the RIS.CBERIS interrupt propagate to
MIS.CBEMIS
0h = Disable Interrupt
1h = Enable Interrupt

CBMIM

R/W

Enabling this bit will make the RIS.CBMRIS interrupt propagate to
MIS.CBMMIS
0h = Disable Interrupt
1h = Enable Interrupt

TBTOIM

R/W

Enabling this bit will make the RIS.TBTORIS interrupt propagate to
MIS.TBTOMIS
0h = Disable Interrupt
1h = Enable Interrupt

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-14

7-6

1212

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

Table 13-13. IMR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

DMAAIM

R/W

Enabling this bit will make the RIS.DMAARIS interrupt propagate to
MIS.DMAAMIS
0h = Disable Interrupt
1h = Enable Interrupt

TAMIM

R/W

Enabling this bit will make the RIS.TAMRIS interrupt propagate to
MIS.TAMMIS
0h = Disable Interrupt
1h = Enable Interrupt

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CAEIM

R/W

Enabling this bit will make the RIS.CAERIS interrupt propagate to
MIS.CAEMIS
0h = Disable Interrupt
1h = Enable Interrupt

CAMIM

R/W

Enabling this bit will make the RIS.CAMRIS interrupt propagate to
MIS.CAMMIS
0h = Disable Interrupt
1h = Enable Interrupt

TATOIM

R/W

Enabling this bit will make the RIS.TATORIS interrupt propagate to
MIS.TATOMIS
0h = Disable Interrupt
1h = Enable Interrupt

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1213

General-Purpose Timer Registers

www.ti.com

13.5.1.7 RIS Register (Offset = 1Ch) [reset = 0h]
RIS is shown in Figure 13-15 and described in Table 13-14.
Return to Summary Table.
Raw Interrupt Status
Associated registers:
IMR, MIS, ICLR
Figure 13-15. RIS Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

13
DMABRIS
R-0h

12
RESERVED
R-0h

11
TBMRIS
R-0h

10
CBERIS
R-0h

9
CBMRIS
R-0h

8
TBTORIS
R-0h

5
DMAARIS
R-0h

4
TAMRIS
R-0h

3
RESERVED
R-0h

2
CAERIS
R-0h

1
CAMRIS
R-0h

0
TATORIS
R-0h

RESERVED
R-0h
7
RESERVED
R-0h

Table 13-14. RIS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMABRIS

GPT Timer B DMA Done Raw Interrupt Status
0: Transfer has not completed
1: Transfer has completed

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TBMRIS

GPT Timer B Match Raw Interrupt
0: The match value has not been reached
1: The match value is reached.
TBMR.TBMIE is set, and the match values in TBMATCHR and
optionally TBPMR have been reached when configured in one-shot
or periodic mode.

CBERIS

GPT Timer B Capture Mode Event Raw Interrupt
0: The event has not occured.
1: The event has occured.
This interrupt asserts when the subtimer is configured in Input EdgeTime mode

CBMRIS

GPT Timer B Capture Mode Match Raw Interrupt
0: The capture mode match for Timer B has not occurred.
1: A capture mode match has occurred for Timer B. This interrupt
asserts when the values in the TBR and TBPR
match the values in the TBMATCHR and TBPMR
when configured in Input Edge-Time mode.
This bit is cleared by writing a 1 to the ICLR.CBMCINT bit.

TBTORIS

GPT Timer B Time-out Raw Interrupt
0: Timer B has not timed out
1: Timer B has timed out.
This interrupt is asserted when a one-shot or periodic mode timer
reaches its count limit. The count limit is 0 or the value loaded into
TBILR, depending on the count direction.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-14

7-6

1214

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

Table 13-14. RIS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

DMAARIS

GPT Timer A DMA Done Raw Interrupt Status
0: Transfer has not completed
1: Transfer has completed

TAMRIS

GPT Timer A Match Raw Interrupt
0: The match value has not been reached
1: The match value is reached.
TAMR.TAMIE is set, and the match values in TAMATCHR and
optionally TAPMR have been reached when configured in one-shot
or periodic mode.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CAERIS

GPT Timer A Capture Mode Event Raw Interrupt
0: The event has not occured.
1: The event has occured.
This interrupt asserts when the subtimer is configured in Input EdgeTime mode

CAMRIS

GPT Timer A Capture Mode Match Raw Interrupt
0: The capture mode match for Timer A has not occurred.
1: A capture mode match has occurred for Timer A. This interrupt
asserts when the values in the TAR and TAPR
match the values in the TAMATCHR and TAPMR
when configured in Input Edge-Time mode.
This bit is cleared by writing a 1 to the ICLR.CAMCINT bit.

TATORIS

GPT Timer A Time-out Raw Interrupt
0: Timer A has not timed out
1: Timer A has timed out.
This interrupt is asserted when a one-shot or periodic mode timer
reaches its count limit. The count limit is 0 or the value loaded into
TAILR, depending on the count direction.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1215

General-Purpose Timer Registers

www.ti.com

13.5.1.8 MIS Register (Offset = 20h) [reset = 0h]
MIS is shown in Figure 13-16 and described in Table 13-15.
Return to Summary Table.
Masked Interrupt Status
Values are result of bitwise AND operation between RIS and IMR
Assosciated clear register: ICLR
Figure 13-16. MIS Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

13
DMABMIS
R-0h

12
RESERVED
R-0h

11
TBMMIS
R-0h

10
CBEMIS
R-0h

9
CBMMIS
R-0h

8
TBTOMIS
R-0h

5
DMAAMIS
R-0h

4
TAMMIS
R-0h

3
RESERVED
R-0h

2
CAEMIS
R-0h

1
CAMMIS
R-0h

0
TATOMIS
R-0h

RESERVED
R-0h
7
RESERVED
R-0h

Table 13-15. MIS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMABMIS

0: No interrupt or interrupt not enabled
1: RIS.DMABRIS = 1 && IMR.DMABIM = 1

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TBMMIS

0: No interrupt or interrupt not enabled
1: RIS.TBMRIS = 1 && IMR.TBMIM = 1

CBEMIS

0: No interrupt or interrupt not enabled
1: RIS.CBERIS = 1 && IMR.CBEIM = 1

CBMMIS

0: No interrupt or interrupt not enabled
1: RIS.CBMRIS = 1 && IMR.CBMIM = 1

TBTOMIS

0: No interrupt or interrupt not enabled
1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMAAMIS

0: No interrupt or interrupt not enabled
1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1

TAMMIS

0: No interrupt or interrupt not enabled
1: RIS.TAMRIS = 1 && IMR.TAMIM = 1

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CAEMIS

0: No interrupt or interrupt not enabled
1: RIS.CAERIS = 1 && IMR.CAEIM = 1

CAMMIS

0: No interrupt or interrupt not enabled
1: RIS.CAMRIS = 1 && IMR.CAMIM = 1

TATOMIS

0: No interrupt or interrupt not enabled
1: RIS.TATORIS = 1 && IMR.TATOIM = 1

31-14

7-6

1216

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.9 ICLR Register (Offset = 24h) [reset = 0h]
ICLR is shown in Figure 13-17 and described in Table 13-16.
Return to Summary Table.
Interrupt Clear
This register is used to clear status bits in the RIS and MIS registers
Figure 13-17. ICLR Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

13
DMABINT
R/W1C-0h

12
RESERVED
R/W-0h

11
TBMCINT
R/W1C-0h

10
CBECINT
R/W1C-0h

9
CBMCINT
R/W1C-0h

8
TBTOCINT
R/W1C-0h

5
DMAAINT
R/W1C-0h

4
TAMCINT
R/W1C-0h

3
RESERVED
R/W1C-0h

2
CAECINT
R/W1C-0h

1
CAMCINT
R/W1C-0h

0
TATOCINT
R/W1C-0h

RESERVED
R-0h
7
RESERVED
R-0h

Table 13-16. ICLR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMABINT

R/W1C

0: Do nothing.
1: Clear RIS.DMABRIS and MIS.DMABMIS

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TBMCINT

R/W1C

0: Do nothing.
1: Clear RIS.TBMRIS and MIS.TBMMIS

CBECINT

R/W1C

0: Do nothing.
1: Clear RIS.CBERIS and MIS.CBEMIS

CBMCINT

R/W1C

0: Do nothing.
1: Clear RIS.CBMRIS and MIS.CBMMIS

TBTOCINT

R/W1C

0: Do nothing.
1: Clear RIS.TBTORIS and MIS.TBTOMIS

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMAAINT

R/W1C

0: Do nothing.
1: Clear RIS.DMAARIS and MIS.DMAAMIS

TAMCINT

R/W1C

0: Do nothing.
1: Clear RIS.TAMRIS and MIS.TAMMIS

RESERVED

R/W1C

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CAECINT

R/W1C

0: Do nothing.
1: Clear RIS.CAERIS and MIS.CAEMIS

CAMCINT

R/W1C

0: Do nothing.
1: Clear RIS.CAMRIS and MIS.CAMMIS

TATOCINT

R/W1C

0: Do nothing.
1: Clear RIS.TATORIS and MIS.TATOMIS

31-14

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1217

General-Purpose Timer Registers

www.ti.com

13.5.1.10 TAILR Register (Offset = 28h) [reset = FFFFFFFFh]
TAILR is shown in Figure 13-18 and described in Table 13-17.
Return to Summary Table.
Timer A Interval Load Register
Figure 13-18. TAILR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TAILR
R/W-FFFFFFFFh

Table 13-17. TAILR Register Field Descriptions
Bit

Field

Type

Reset

31-0

TAILR

R/W

FFFFFFFFh GPT Timer A Interval Load Register
Writing this field loads the counter for Timer A. A read returns the
current value of TAILR.

1218

Timers

Description

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.11 TBILR Register (Offset = 2Ch) [reset = FFFFh]
TBILR is shown in Figure 13-19 and described in Table 13-18.
Return to Summary Table.
Timer B Interval Load Register
Figure 13-19. TBILR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TBILR
R/W-FFFFh

Table 13-18. TBILR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

TBILR

R/W

FFFFh

GPT Timer B Interval Load Register
Writing this field loads the counter for Timer B. A read returns the
current value of TBILR.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1219

General-Purpose Timer Registers

www.ti.com

13.5.1.12 TAMATCHR Register (Offset = 30h) [reset = FFFFFFFFh]
TAMATCHR is shown in Figure 13-20 and described in Table 13-19.
Return to Summary Table.
Timer A Match Register
Interrupts can be generated when the timer value is equal to the value in this register in one-shot or
periodic mode.
In Edge-Count mode, this register along with TAILR, determines how many edge events are counted.
The total number of edge events counted is equal to the value in TAILR minus this value.
Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be
greater than the value of TAPMR and this register.
In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal.
When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register.
(The upper 16-bits correspond to the contents TBMATCHR).
In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of
TBMATCHR.
Note : This register is updated internally (takes effect) based on TAMR.TAMRSU
Figure 13-20. TAMATCHR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TAMATCHR
R/W-FFFFFFFFh

Table 13-19. TAMATCHR Register Field Descriptions
Bit
31-0

1220

Field

Type

Reset

TAMATCHR

R/W

FFFFFFFFh GPT Timer A Match Register

Timers

Description

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.13 TBMATCHR Register (Offset = 34h) [reset = FFFFh]
TBMATCHR is shown in Figure 13-21 and described in Table 13-20.
Return to Summary Table.
Timer B Match Register
When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded
into the upper 16 bits of TAMATCHR.
Reads from this register return the current match value of Timer B and writes are ignored.
In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases.
Note : This register is updated internally (takes effect) based on TBMR.TBMRSU
Figure 13-21. TBMATCHR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

9 8 7 6
TBMATCHR
R/W-FFFFh

Table 13-20. TBMATCHR Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

TBMATCHR

R/W

FFFFh

GPT Timer B Match Register

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1221

General-Purpose Timer Registers

www.ti.com

13.5.1.14 TAPR Register (Offset = 38h) [reset = 0h]
TAPR is shown in Figure 13-22 and described in Table 13-21.
Return to Summary Table.
Timer A Pre-scale
This register allows software to extend the range of the timers when they are used individually.
When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer
counter.
When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV
registers are incremented.
In all other individual/split modes, this register is a linear extension of the upper range of the timer counter,
holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT.
Figure 13-22. TAPR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
TAPSR
R/W-0h

Table 13-21. TAPR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-8

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

TAPSR

R/W

Timer A Pre-scale.
Prescaler ratio in one-shot and periodic count mode is TAPSR + 1,
that is:
0: Prescaler ratio = 1
1: Prescaler ratio = 2
2: Prescaler ratio = 3
...
255: Prescaler ratio = 256

1222

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.15 TBPR Register (Offset = 3Ch) [reset = 0h]
TBPR is shown in Figure 13-23 and described in Table 13-22.
Return to Summary Table.
Timer B Pre-scale
This register allows software to extend the range of the timers when they are used individually.
When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer
counter.
When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV
registers are incremented.
In all other individual/split modes, this register is a linear extension of the upper range of the timer counter,
holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT.
Figure 13-23. TBPR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
TBPSR
R/W-0h

Table 13-22. TBPR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-8

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

TBPSR

R/W

Timer B Pre-scale.
Prescale ratio in one-shot and periodic count mode is TBPSR + 1,
that is:
0: Prescaler ratio = 1
1: Prescaler ratio = 2
2: Prescaler ratio = 3
...
255: Prescaler ratio = 256

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1223

General-Purpose Timer Registers

www.ti.com

13.5.1.16 TAPMR Register (Offset = 40h) [reset = 0h]
TAPMR is shown in Figure 13-24 and described in Table 13-23.
Return to Summary Table.
Timer A Pre-scale Match
This register allows software to extend the range of the TAMATCHR when used individually.
Figure 13-24. TAPMR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
TAPSMR
R/W-0h

Table 13-23. TAPMR Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

TAPSMR

R/W

GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23
to 16.

1224

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.17 TBPMR Register (Offset = 44h) [reset = 0h]
TBPMR is shown in Figure 13-25 and described in Table 13-24.
Return to Summary Table.
Timer B Pre-scale Match
This register allows software to extend the range of the TBMATCHR when used individually.
Figure 13-25. TBPMR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
TBPSMR
R/W-0h

Table 13-24. TBPMR Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

TBPSMR

R/W

GPT Timer B Pre-scale Match Register. In 16 bit mode this field
holds bits 23 to 16.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1225

General-Purpose Timer Registers

www.ti.com

13.5.1.18 TAR Register (Offset = 48h) [reset = FFFFFFFFh]
TAR is shown in Figure 13-26 and described in Table 13-25.
Return to Summary Table.
Timer A Register
This register shows the current value of the Timer A counter in all cases except for Input Edge Count and
Time modes. In the Input Edge Count mode, this register contains the number of edges that
have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event
took place.
When a GPT is configured to one of the 32-bit modes, this register appears as a 32-bit register (the upper
16-bits correspond to the contents of the Timer B (TBR) register). In
the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the counter
and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. Bits
31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read
bits [23:16] in the TAV register. To read the value of the prescalar in periodic snapshot
mode, read the Timer A Prescale Snapshot (TAPS) register.
Figure 13-26. TAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TAR
R-FFFFFFFFh

Table 13-25. TAR Register Field Descriptions
Bit

Field

Type

Reset

31-0

TAR

FFFFFFFFh GPT Timer A Register
Based on the value in the register field TAMR.TAILD, this register is
updated with the value from TAILR register either on the next cycle
or on the next timeout.
A read returns the current value of the Timer A Count Register, in all
cases except for Input Edge count and Timer modes.
In the Input Edge Count Mode, this register contains the number of
edges that have occurred. In the Input Edge Time mode, this register
contains the time at which the last edge event took place.

1226

Timers

Description

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.19 TBR Register (Offset = 4Ch) [reset = FFFFh]
TBR is shown in Figure 13-27 and described in Table 13-26.
Return to Summary Table.
Timer B Register
This register shows the current value of the Timer B counter in all cases except for Input Edge Count and
Time modes. In the Input Edge Count mode, this register contains the number of edges that
have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event
took place.
When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are
loaded into the upper 16 bits of the TAR register. Reads from this register return the current
value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the
value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes, which is the
upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit OneShot and Periodic modes, read bits [23:16] in the TBV register. To read the value of the
prescalar in periodic snapshot mode, read the Timer B Prescale Snapshot (TBPS) register.
Figure 13-27. TBR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TBR
R-FFFFh

Table 13-26. TBR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

TBR

FFFFh

GPT Timer B Register
Based on the value in the register field TBMR.TBILD, this register is
updated with the value from TBILR register either on the next cycle
or on the next timeout.
A read returns the current value of the Timer B Count Register, in all
cases except for Input Edge count and Timer modes.
In the Input Edge Count Mode, this register contains the number of
edges that have occurred. In the Input Edge Time mode, this register
contains the time at which the last edge event took place.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1227

General-Purpose Timer Registers

www.ti.com

13.5.1.20 TAV Register (Offset = 50h) [reset = FFFFFFFFh]
TAV is shown in Figure 13-28 and described in Table 13-27.
Return to Summary Table.
Timer A Value
When read, this register shows the current, free-running value of Timer A in all modes. Softwarecan use
this value to determine the time elapsed between an interrupt and the ISR entry when using
the snapshot feature with the periodic operating mode. When written, the value written into this register is
loaded into the TAR register on the next clock cycle.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, this register appears as a 32-bit register
(the upper 16-bits correspond to the contents of the GPTM Timer B Value (TBV) register). In a 16-bit
mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of
the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and oneshot or periodic up count modes. In one-shot or periodic
down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down
before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0.
Figure 13-28. TAV Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TAV
R/W-FFFFFFFFh

Table 13-27. TAV Register Field Descriptions
Bit

Field

Type

Reset

31-0

TAV

R/W

FFFFFFFFh GPT Timer A Register
A read returns the current, free-running value of Timer A in all
modes.
When written, the value written into this register is loaded into the
TAR register on the next clock cycle.
Note: In 16-bit mode, only the lower 16-bits of this
register can be written with a new value. Writes to the prescaler bits
have no effect

1228

Timers

Description

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.21 TBV Register (Offset = 54h) [reset = FFFFh]
TBV is shown in Figure 13-29 and described in Table 13-28.
Return to Summary Table.
Timer B Value
When read, this register shows the current, free-running value of Timer B in all modes. Software can use
this value to determine the time elapsed between an interrupt and the ISR entry. When
written, the value written into this register is loaded into the TBR register on the next clock cycle.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register
are loaded into the upper 16 bits of the TAV register. Reads from this register return
the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and
bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of
the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes.
In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits
23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as
0.
Figure 13-29. TBV Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TBV
R/W-FFFFh

Table 13-28. TBV Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

TBV

R/W

FFFFh

GPT Timer B Register
A read returns the current, free-running value of Timer B in all
modes.
When written, the value written into this register is loaded into the
TBR register on the next clock cycle.
Note: In 16-bit mode, only the lower 16-bits of this
register can be written with a new value. Writes to the prescaler bits
have no effect

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1229

General-Purpose Timer Registers

www.ti.com

13.5.1.22 TAPS Register (Offset = 5Ch) [reset = 0h]
TAPS is shown in Figure 13-30 and described in Table 13-29.
Return to Summary Table.
Timer A Pre-scale Snap-shot
Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAPR
register either on the next cycle or on the next timeout.
This register shows the current value of the Timer A pre-scaler in the 16-bit mode.
Figure 13-30. TAPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3
PSS
R-0h

Table 13-29. TAPS Register Field Descriptions
Bit

Field

Type

Reset

Description

31-8

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

PSS

GPT Timer A Pre-scaler

1230

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.23 TBPS Register (Offset = 60h) [reset = 0h]
TBPS is shown in Figure 13-31 and described in Table 13-30.
Return to Summary Table.
Timer B Pre-scale Snap-shot
Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBPR
register either on the next cycle or on the next timeout.
This register shows the current value of the Timer B pre-scaler in the 16-bit mode.
Figure 13-31. TBPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3
PSS
R-0h

Table 13-30. TBPS Register Field Descriptions
Bit

Field

Type

Reset

Description

31-8

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

PSS

GPT Timer B Pre-scaler

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1231

General-Purpose Timer Registers

www.ti.com

13.5.1.24 TAPV Register (Offset = 64h) [reset = 0h]
TAPV is shown in Figure 13-32 and described in Table 13-31.
Return to Summary Table.
Timer A Pre-scale Value
This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode.
Figure 13-32. TAPV Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3
PSV
R-0h

Table 13-31. TAPV Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

PSV

GPT Timer A Pre-scaler Value

1232

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.25 TBPV Register (Offset = 68h) [reset = 0h]
TBPV is shown in Figure 13-33 and described in Table 13-32.
Return to Summary Table.
Timer B Pre-scale Value
This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode.
Figure 13-33. TBPV Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3
PSV
R-0h

Table 13-32. TBPV Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

PSV

GPT Timer B Pre-scaler Value

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1233

General-Purpose Timer Registers

www.ti.com

13.5.1.26 DMAEV Register (Offset = 6Ch) [reset = 0h]
DMAEV is shown in Figure 13-34 and described in Table 13-33.
Return to Summary Table.
DMA Event
This register allows software to enable/disable GPT DMA trigger events.
Figure 13-34. DMAEV Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

11
TBMDMAEN
R/W-0h

10
CBEDMAEN
R/W-0h

9
CBMDMAEN
R/W-0h

8
TBTODMAEN
R/W-0h

4
TAMDMAEN
R/W-0h

3
RESERVED
R/W-0h

2
CAEDMAEN
R/W-0h

1
CAMDMAEN
R/W-0h

0
TATODMAEN
R/W-0h

RESERVED
R-0h
7

6
RESERVED
R/W-0h

Table 13-33. DMAEV Register Field Descriptions
Field

Type

Reset

Description

31-12

Bit

RESERVED

Software should not rely on the value of a reserved field. Writing any
other value may result in undefined behavior.

TBMDMAEN

R/W

GPT Timer B Match DMA Trigger Enable

CBEDMAEN

R/W

GPT Timer B Capture Event DMA Trigger Enable

CBMDMAEN

R/W

GPT Timer B Capture Match DMA Trigger Enable

TBTODMAEN

R/W

GPT Timer B Time-Out DMA Trigger Enable

7-5

RESERVED

R/W

Software should not rely on the value of a reserved field. Writing any
other value may result in undefined behavior.

TAMDMAEN

R/W

GPT Timer A Match DMA Trigger Enable

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CAEDMAEN

R/W

GPT Timer A Capture Event DMA Trigger Enable

CAMDMAEN

R/W

GPT Timer A Capture Match DMA Trigger Enable

TATODMAEN

R/W

GPT Timer A Time-Out DMA Trigger Enable

1234

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

General-Purpose Timer Registers

www.ti.com

13.5.1.27 VERSION Register (Offset = FB0h) [reset = 400h]
VERSION is shown in Figure 13-35 and described in Table 13-34.
Return to Summary Table.
Peripheral Version
This register provides information regarding the GPT version
Figure 13-35. VERSION Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VERSION
R-400h

Table 13-34. VERSION Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

VERSION

400h

Timer Revision.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timers

1235

General-Purpose Timer Registers

www.ti.com

13.5.1.28 ANDCCP Register (Offset = FB4h) [reset = 0h]
ANDCCP is shown in Figure 13-36 and described in Table 13-35.
Return to Summary Table.
Combined CCP Output
This register is used to logically AND CCP output pairs for each timer
Figure 13-36. ANDCCP Register
31

0
CCP_AND_EN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 13-35. ANDCCP Register Field Descriptions
Bit
31-1
0

1236

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CCP_AND_EN

R/W

Enables AND operation of the CCP outputs for timers A and B.
0 : PWM outputs of Timer A and Timer B are the internal generated
PWM signals of the respective timers.
1 : PWM output of Timer A is ANDed version of Timer A and Timer B
PWM signals and Timer B PWM ouput is Timer B PWM signal only.

Timers

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Chapter 14
SWCU117G – February 2015 – Revised February 2017

Real-Time Clock
This chapter describes the functionality and design of the always-on, real-time clock (AON_RTC) for the
CC26x0 and CC13x0 platform.
Topic

14.1
14.2
14.3
14.4

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Page

1238
1238
1240
1242

Real-Time Clock

1237

Introduction

www.ti.com

14.1 Introduction
This section describes the functionality and design of the always-on, real-time clock (AON_RTC) for the
CC26x0 and CC13x0 platform. The AON_RTC implements a second and subsecond counter with support
for software-compensation of ppm-offsets, with three match register and one compare register.
A special mechanism is in place to support power down of the MCU domain while the AON_RTC
continues to operate. The AON_RTC is powered in all power modes except for the deepest power-down
mode, known as shutdown.

14.2 Functional Specifications
This section gives a functional description of the AON_RTC.

14.2.1 Functional Overview
The functionality of the AON_RTC is described as follows:
• Runs on always-on, 32-kHz clock
• 70-bit incrementing counter with support for programmable increment to support ppm-adjustment
• Three general-purpose channels (0, 1, and 2) with comparators supporting the generation of events
• Software and hardware reset of events
• All events can be delayed by a programmable amount to generated corresponding delayed events.
• A programmable set of the delayed events can be combined to generate a delayed combined event.

14.2.2 Free-Running Counter
The AON_RTC implements a 70-bit, free-running counter incremented by a programmable value for each
32-kHz clock. The programmable value allows compensation of ppm-offsets in the 32-kHz clock, making it
possible for the counter to operate with a very high precision.
The counter starts from 0 when enabled following power up of the AON_RTC, but can also be reset to 0
or any other new value by the software. The counter measures seconds
(32 bit) and subseconds (32 bit).
By default, the AON_RTC increments its counter with 1/32768 seconds each 32-kHz clock tick. A
subsecond increment value of 0x80 000 corresponds to 1/32768 seconds. Increasing or decreasing the
subsecond increments value increases or decreases the speed of the AON_RTC by the same amount.
Change the increment by updating the AUX_WUC:RTCSUBSECINC0 and the
AUX_WUC:RTCSUBSECINC1 registers, and then load the new setting to the AON_RTC by a write to the
AUX_WUC:RTCSUBSECINCCTL.UPD_REQ register. The new subsecond increment value must not be
changed by AUX until it has received an acknowledgment from the AON_RTC. The acknowledgment can
be read from the AUX_WUC:RTCSUBSECINCCTL.UPD_ACK register. After the acknowledgment has
been received, the AUX_WUC:RTCSUBSECINCCTL.UPD_REQ register can be written back to 0 and a
new subsecond increment can be uploaded, if needed.
To perform an atomic read of the free-running counter, a read must first be done of the seconds part
AON_RTC:SEC. This will latch the subseconds part AON_RTC:SUBSEC until read.

1238

Real-Time Clock

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Specifications

www.ti.com

14.2.3 Channels
The AON_RTC contains three independent channels (0, 1, and 2) that have slightly different behaviors.
All channels can operate in a compare mode; each channel generates a compare event when a
programmable time limit has been reached or exceeded. This is the only mode of operation for channel 0.
Channel 1 can be operated in a capture mode, where an external event causes the current value of the
free-running timer to be latched, to remember the time of the event. A capture event is subsequently
generated. As the channel 1 timer is operating in either compare mode or capture mode, the same
physical event is generated in each mode.
Channel 2 can operate in a continuous compare mode, automatically incrementing its compare value
following a compare event. This enables the generation of completely equidistant events.
Figure 14-1 shows the three AON_RTC channels.
Figure 14-1. AON_RTC Channels
AON RTC Module
Registers
DELAY
counter

CLEAR
CH0_EVENT
CH0

32 kHz

I/O border

RTC_CNT

CH1_EVENT
CAPTURE

Programable event

CH1

I/O border

Event
fabric

DELAY
counter

CLEAR

32 kHz

RTC_CNT

DELAY
counter

CLEAR

CH2_CLEAR

CH2_EVENT

AUX
RTC_CNT

32 kHz

Main counter
RTC_CNT

CH2

32 kHz

subsecinc
RTC_UPD (16 kHz)

DIV 2

14.2.3.1 Capture and Compare
A RTC capture event can be set up on channel 1 by configuring a capture source in
AON_EVENT:RTCSEL and setting channel 1 to capture mode in AON_RTC:CHCTL. The captured RTC
value is available in the register AON_RTC:CH1CAPT after a capture event
Compare events are configured by writing to the corresponding channel compare register
AON_RTC:CHnCMP.
NOTE: When setting a compare event, the compare time must be set at least four SCLK_LF cycles
into the future to avoid being delayed until the RTC free-running value wraps around and
matches the compare value again.
If a compare value is set so that the compare value minus current value is larger than the
seconds wrap-around time minus one second (232 × SCLK_LFperiod – 1), an immediate
compare event is set to avoid losing the event.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock

1239

Functional Specifications

www.ti.com

14.2.4 Events
A programmable combination of the three delayed events can be combined into a seventh delayed event.
All events are fed to the AON event fabric, where they are available, for example, as wake-up events for
the MCU or AUX domains.
The three channels can individually generate an event. Each of these three events can generate a
corresponding event by delaying the channel event by a programmable amount of clocks, using a delay
counter. The delay counters use the uncompensated 32-kHz clock; thus, the delay time varies with this
clock. This process can generate precise events in the future, even when, for example, the MCU must be
woken up following an event—a process that takes an indeterministic, yet bounded, amount of time.
NOTE: Disabling a channel does not clear any pending events from that channel. The only way to
clear an event is by asserting the external clear signal, or by writing 1 to the corresponding
CHx bit in the AON_RTC:EVFLAGS register.

14.3 RTC Registers
The RTC registers are placed in the AON domain and are clocked using 32-kHz LF clock. All configuration
and status registers are preserved in all power modes except for SHUTDOWN. The MCU domain contains
an interface to the AON_RTC registers to ensure fast access with minimum latency on the system bus.
Due to synchronization between the MCU interface and the AON domain, there is a delay in the system
that software must take into account.

14.3.1 Register Access
A write access is delayed with one or two 32-kHz LF clock periods. The system bus is not affected by this
delay, so the MCU completes the bus transactions before the actual AON_RTC register is written in the
AON_RTC. This process enables the application to write several registers consecutively, without any extra
delay due to synchronization.
Due to synchronization, a read access always reads a value that is two to three system clocks (48 MHz)
delayed. In this case, the system bus is not halted.
The AON_RTC:EVFLAGS register has a fast-clear feature. When written to 1, the MCU intermediately
clears the EVFLAGS bit field. This process enables the MCU to clear the source quickly if the status is
used as an interrupt or event. Due to synchronization, the actual flag in the RTC is not cleared until 1 or 2
clock cycles later. For this reason, a new event is masked for up to two 32-kHz LF periods.

14.3.2 Entering Sleep and Wakeup From Sleep
Before entering sleep, the application must ensure that all write requests to the AON registers are
completed. The MCU domain register interface must be clocked to complete the synchronization towards
the AON domain. If the clock is stopped or halted before the synchronization has completed, the write
access might be lost.
Upon wakeup from sleep, the application must wait for one 32-kHz LF period. This wait ensures that the
MCU domain register interface is correctly synchronized. If registers are read before synchronization is
completed, the value might not be updated. For example, reading the AON_RTC:SEC register might show
the value from before entering sleep, and not the current value.

1240

Real-Time Clock

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RTC Registers

www.ti.com

14.3.3 AON_RTC:SYNC Register
The AON_RTC:SYNC register synchronizes between the MCU domain and AON domain.
A read request from the AON_RTC:SYNC register does not return if there are outstanding write requests
to the AON registers; in other words, the bus is halted until all outstanding requests are completed.
A write request triggers a dummy write to the AON domain. This write can ensure synchronization to the
LF clock. This dummy write takes 1 to 2 32-kHz LF clock cycles.
1. Write to the AON_RTC:SYNC register or any other register in the AON domain. The write triggers an
outstanding write request to be registered on the AON domain.
2. Read from the AON_RTC:SYNC register. This read does not return until all outstanding requests are
completed.
The AON_RTC:SYNC register operation is typically used when a specific order must be ensured. For
example, when disabling a channel, the AON_RTC:SYNC register can be polled to ensure that the
channel has been disabled and no further events can occur:
1. Set AON_RTC:CHCTL.CH2_EN = 0.
2. Read the AON_RTC:SYNC register.
3. The channel is now disabled. No further events can occur.
Another typical use case for the AON_RTC:SYNC register is to ensure that all outstanding accesses are
completed prior to powering down the MCU power domain. A problem can occur if the MCU sets up a new
wake-up event (RTC timer) but powers down before the new RTC compare values are transferred to the
AON_RTC.
1. Write a new compare value to the AON_RTC:CH1CMP.VALUE register.
2. Read the AON_RTC:SYNC register.
3. Put CM3 to sleep.
Another typical use is to ensure the correct values are updated in the MCU domain on wakeup. This MCU
domain is only updated on a positive edge of the 32-kHz LF clock.
1. Write to the AON_RTC:SYNC register.
2. Read the AON_RTC:SYNC register.
3. Other AON_RTC registers can now be read safely as their information is correctly updated.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock

1241

Real-Time Clock Registers

www.ti.com

14.4 Real-Time Clock Registers
14.4.1 AON_RTC Registers
Table 14-1 lists the memory-mapped registers for the AON_RTC. All register offset addresses not listed in
Table 14-1 should be considered as reserved locations and the register contents should not be modified.
Table 14-1. AON_RTC Registers
Offset

1242

Acronym

Section

CTL

Control

Section 14.4.1.1

EVFLAGS

Event Flags, RTC Status

Section 14.4.1.2

SEC

Second Counter Value, Integer Part

Section 14.4.1.3

SUBSEC

Second Counter Value, Fractional Part

Section 14.4.1.4

10h

SUBSECINC

Subseconds Increment

Section 14.4.1.5

14h

CHCTL

Channel Configuration

Section 14.4.1.6

18h

CH0CMP

Channel 0 Compare Value

Section 14.4.1.7

1Ch

CH1CMP

Channel 1 Compare Value

Section 14.4.1.8

20h

CH2CMP

Channel 2 Compare Value

Section 14.4.1.9

24h

CH2CMPINC

Channel 2 Compare Value Auto-increment

Section 14.4.1.10

28h

CH1CAPT

Channel 1 Capture Value

Section 14.4.1.11

2Ch

SYNC

AON Synchronization

Section 14.4.1.12

Real-Time Clock

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock Registers

www.ti.com

14.4.1.1 CTL Register (Offset = 0h) [reset = 0h]
CTL is shown in Figure 14-2 and described in Table 14-2.
Return to Summary Table.
Control
This register contains various bitfields for configuration of RTC
Figure 14-2. CTL Register
31

17
COMB_EV_MASK
R/W-0h

RESERVED
R-0h
23

21
RESERVED
R-0h

RESERVED
R-0h
7
RESET
W1C-0h

EV_DELAY
R/W-0h
5

RESERVED
R-0h

2
1
RTC_4KHZ_EN RTC_UPD_EN
R/W-0h
R/W-0h

0
EN
R/W-0h

Table 14-2. CTL Register Field Descriptions
Field

Type

Reset

Description

31-19

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

18-16

COMB_EV_MASK

R/W

Eventmask selecting which delayed events that form the combined
event.
0h = No event is selected for combined event.
1h = Use Channel 0 delayed event in combined event
2h = Use Channel 1 delayed event in combined event
4h = Use Channel 2 delayed event in combined event

15-12

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-8

EV_DELAY

R/W

Number of SCLK_LF clock cycles waited before generating delayed
events. (Common setting for all RTC cannels) the delayed event is
delayed
0h = No delay on delayed event
1h = Delay by 1 clock cycles
2h = Delay by 2 clock cycles
3h = Delay by 4 clock cycles
4h = Delay by 8 clock cycles
5h = Delay by 16 clock cycles
6h = Delay by 32 clock cycles
7h = Delay by 48 clock cycles
8h = Delay by 64 clock cycles
9h = Delay by 80 clock cycles
Ah = Delay by 96 clock cycles
Bh = Delay by 112 clock cycles
Ch = Delay by 128 clock cycles
Dh = Delay by 144 clock cycles

RESET

W1C

RTC Counter reset.
Writing 1 to this bit will reset the RTC counter.
This bit is cleared when reset takes effect

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock

1243

Real-Time Clock Registers

www.ti.com

Table 14-2. CTL Register Field Descriptions (continued)
Bit

1244

Field

Type

Reset

Description

RTC_4KHZ_EN

R/W

RTC_4KHZ is a 4 KHz reference output, tapped from
SUBSEC.VALUE bit 19 which is used by AUX timer.
0: RTC_4KHZ signal is forced to 0
1: RTC_4KHZ is enabled ( provied that RTC is enabled EN)

RTC_UPD_EN

R/W

RTC_UPD is a 16 KHz signal used to sync up the radio timer. The
16 Khz is SCLK_LF divided by 2
0: RTC_UPD signal is forced to 0
1: RTC_UPD signal is toggling @16 kHz

R/W

Enable RTC counter
0: Halted (frozen)
1: Running

Real-Time Clock

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock Registers

www.ti.com

14.4.1.2 EVFLAGS Register (Offset = 4h) [reset = 0h]
EVFLAGS is shown in Figure 14-3 and described in Table 14-3.
Return to Summary Table.
Event Flags, RTC Status
This register contains event flags from the 3 RTC channels. Each flag will be cleared when writing a '1' to
the corresponding bitfield.
Figure 14-3. EVFLAGS Register
31

12
11
RESERVED
R-0h

24
23
RESERVED
R-0h
8
CH1
R/W1
C-0h

16
CH2
R/W1
C-0h

4
3
RESERVED
R-0h

0
CH0
R/W1
C-0h

Table 14-3. EVFLAGS Register Field Descriptions
Bit
31-17
16

15-9
8

7-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CH2

R/W1C

Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC
value matches or passes the CH2CMP value.
An event will be scheduled to occur as soon as possible when
writing to CH2CMP provided that the channel is enabled and the
new value matches any time between next RTC value and 1 second
in the past
Writing 1 clears this flag. Note that a new event can not occur on this
channel in first 2 SCLK_LF cycles after a clearance.
AUX_SCE can read the flag through
AUX_WUC:WUEVFLAGS.AON_RTC_CH2 and clear it using
AUX_WUC:WUEVCLR.AON_RTC_CH2.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CH1

R/W1C

Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the
following:
- CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes
the CH1CMP value.
- CHCTL.CH1_CAPT_EN = 1 and capture occurs.
An event will be scheduled to occur as soon as possible when
writing to CH1CMP provided that the channel is enabled, in compare
mode and the new value matches any time between next RTC value
and 1 second in the past.
Writing 1 clears this flag. Note that a new event can not occur on this
channel in first 2 SCLK_LF cycles after a clearance.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CH0

R/W1C

Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC
value matches or passes the CH0CMP value.
An event will be scheduled to occur as soon as possible when
writing to CH0CMP provided that the channels is enabled and the
new value matches any time between next RTC value and 1 second
in the past.
Writing 1 clears this flag. Note that a new event can not occur on this
channel in first 2 SCLK_LF cycles after a clearance.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock

1245

Real-Time Clock Registers

www.ti.com

14.4.1.3 SEC Register (Offset = 8h) [reset = 0h]
SEC is shown in Figure 14-4 and described in Table 14-4.
Return to Summary Table.
Second Counter Value, Integer Part
Figure 14-4. SEC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VALUE
R/W-0h

Table 14-4. SEC Register Field Descriptions
Bit
31-0

1246

Field

Type

Reset

Description

VALUE

R/W

Unsigned integer representing Real Time Clock in seconds.
When reading this register the content of SUBSEC.VALUE is
simultaneously latched. A consistent reading of the combined Real
Time Clock can be obtained by first reading this register, then
reading SUBSEC register.

Real-Time Clock

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock Registers

www.ti.com

14.4.1.4 SUBSEC Register (Offset = Ch) [reset = 0h]
SUBSEC is shown in Figure 14-5 and described in Table 14-5.
Return to Summary Table.
Second Counter Value, Fractional Part
Figure 14-5. SUBSEC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VALUE
R/W-0h

Table 14-5. SUBSEC Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

VALUE

R/W

Unsigned integer representing Real Time Clock in fractions of a
second (VALUE/232 seconds) at the time when SEC register was
read.
Examples :
- 0x0000_0000 = 0.0 sec
- 0x4000_0000 = 0.25 sec
- 0x8000_0000 = 0.5 sec
- 0xC000_0000 = 0.75 sec

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock

1247

Real-Time Clock Registers

www.ti.com

14.4.1.5 SUBSECINC Register (Offset = 10h) [reset = 00800000h]
SUBSECINC is shown in Figure 14-6 and described in Table 14-6.
Return to Summary Table.
Subseconds Increment
Value added to SUBSEC.VALUE on every SCLK_LFclock cycle.
Figure 14-6. SUBSECINC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
VALUEINC
R-0h
R-00800000h

Table 14-6. SUBSECINC Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-0

VALUEINC

00800000h

This value compensates for a SCLK_LF clock which has an offset
from 32768 Hz.
The compensation value can be found as 238 / freq, where freq is
SCLK_LF clock frequency in Hertz
This value is added to SUBSEC.VALUE on every cycle, and carry of
this is added to SEC.VALUE. To perform the addition, bits [23:6] are
aligned with SUBSEC.VALUE bits [17:0]. The remaining bits [5:0]
are accumulated in a hidden 6-bit register that generates a carry into
the above mentioned addition on overflow.
The default value corresponds to incrementing by precisely 1/32768
of a second.
NOTE: This register is read only. Modification of the register value
must be done using registers AUX_WUC:RTCSUBSECINC1 ,
AUX_WUC:RTCSUBSECINC0 and
AUX_WUC:RTCSUBSECINCCTL

1248

Real-Time Clock

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock Registers

www.ti.com

14.4.1.6 CHCTL Register (Offset = 14h) [reset = 0h]
CHCTL is shown in Figure 14-7 and described in Table 14-7.
Return to Summary Table.
Channel Configuration
Figure 14-7. CHCTL Register
31

18
CH2_CONT_E
N
R/W-0h

17
RESERVED

16
CH2_EN

R-0h

R/W-0h

9
CH1_CAPT_E
N
R/W-0h

8
CH1_EN

0
CH0_EN
R/W-0h

RESERVED
R-0h
23

21
RESERVED

R-0h
15

RESERVED
R-0h
7

4
RESERVED
R-0h

R/W-0h

Table 14-7. CHCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CH2_CONT_EN

R/W

Set to enable continuous operation of Channel 2

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CH2_EN

R/W

RTC Channel 2 Enable
0: Disable RTC Channel 2
1: Enable RTC Channel 2

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CH1_CAPT_EN

R/W

Set Channel 1 mode
0: Compare mode (default)
1: Capture mode

CH1_EN

R/W

RTC Channel 1 Enable
0: Disable RTC Channel 1
1: Enable RTC Channel 1

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CH0_EN

R/W

RTC Channel 0 Enable
0: Disable RTC Channel 0
1: Enable RTC Channel 0

31-19

15-10

7-1
0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock

1249

Real-Time Clock Registers

www.ti.com

14.4.1.7 CH0CMP Register (Offset = 18h) [reset = 0h]
CH0CMP is shown in Figure 14-8 and described in Table 14-8.
Return to Summary Table.
Channel 0 Compare Value
Figure 14-8. CH0CMP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VALUE
R/W-0h

Table 14-8. CH0CMP Register Field Descriptions
Bit
31-0

1250

Field

Type

Reset

Description

VALUE

R/W

RTC Channel 0 compare value.
Bit 31 to 16 represents seconds and bits 15 to 0 represents
subseconds of the compare value.
The compare value is compared against SEC.VALUE (15:0) and
SUBSEC.VALUE (31:16) values of the Real Time Clock register. A
Cannel 0 event is generated when
{SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting
the compare value.
Writing to this register can trigger an immediate*) event in case the
new compare value matches a Real Time Clock value from 1 second
in the past up till current Real Time Clock value.
Example:
To generate a compare 5.5 seconds RTC start,- set this value =
0x0005_8000
*) It can take up to 2 SCLK_LF clock cycles before event occurs due
to synchronization.

Real-Time Clock

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock Registers

www.ti.com

14.4.1.8 CH1CMP Register (Offset = 1Ch) [reset = 0h]
CH1CMP is shown in Figure 14-9 and described in Table 14-9.
Return to Summary Table.
Channel 1 Compare Value
Figure 14-9. CH1CMP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VALUE
R/W-0h

Table 14-9. CH1CMP Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

VALUE

R/W

RTC Channel 1 compare value.
Bit 31 to 16 represents seconds and bits 15 to 0 represents
subseconds of the compare value.
The compare value is compared against SEC.VALUE (15:0) and
SUBSEC.VALUE (31:16) values of the Real Time Clock register. A
Cannel 0 event is generated when
{SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting
the compare value.
Writing to this register can trigger an immediate*) event in case the
new compare value matches a Real Time Clock value from 1 second
in the past up till current Real Time Clock value.
Example:
To generate a compare 5.5 seconds RTC start,- set this value =
0x0005_8000
*) It can take up to 2 SCLK_LF clock cycles before event occurs due
to synchronization.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock

1251

Real-Time Clock Registers

www.ti.com

14.4.1.9 CH2CMP Register (Offset = 20h) [reset = 0h]
CH2CMP is shown in Figure 14-10 and described in Table 14-10.
Return to Summary Table.
Channel 2 Compare Value
Figure 14-10. CH2CMP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VALUE
R/W-0h

Table 14-10. CH2CMP Register Field Descriptions
Bit
31-0

1252

Field

Type

Reset

Description

VALUE

R/W

RTC Channel 2 compare value.
Bit 31 to 16 represents seconds and bits 15 to 0 represents
subseconds of the compare value.
The compare value is compared against SEC.VALUE (15:0) and
SUBSEC.VALUE (31:16) values of the Real Time Clock register. A
Cannel 0 event is generated when
{SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting
the compare value.
Writing to this register can trigger an immediate*) event in case the
new compare value matches a Real Time Clock value from 1 second
in the past up till current Real Time Clock value.
Example:
To generate a compare 5.5 seconds RTC start,- set this value =
0x0005_8000
*) It can take up to 2 SCLK_LF clock cycles before event occurs due
to synchronization.

Real-Time Clock

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock Registers

www.ti.com

14.4.1.10 CH2CMPINC Register (Offset = 24h) [reset = 0h]
CH2CMPINC is shown in Figure 14-11 and described in Table 14-11.
Return to Summary Table.
Channel 2 Compare Value Auto-increment
This register is primarily used to generate periodical wake-up for the AUX_SCE module, through the
[AUX_EVCTL.EVSTAT0.AON_RTC] event.
Figure 14-11. CH2CMPINC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VALUE
R/W-0h

Table 14-11. CH2CMPINC Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

VALUE

R/W

If CHCTL.CH2_CONT_EN is set, this value is added to
CH2CMP.VALUE on every channel 2 compare event.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock

1253

Real-Time Clock Registers

www.ti.com

14.4.1.11 CH1CAPT Register (Offset = 28h) [reset = 0h]
CH1CAPT is shown in Figure 14-12 and described in Table 14-12.
Return to Summary Table.
Channel 1 Capture Value
If CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1, capture occurs on each rising edge of the event
selected in AON_EVENT:RTCSEL.
Figure 14-12. CH1CAPT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SEC
R-0h

8 7 6
SUBSEC
R-0h

Table 14-12. CH1CAPT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

SEC

Value of SEC.VALUE bits 15:0 at capture time.

15-0

SUBSEC

Value of SUBSEC.VALUE bits 31:16 at capture time.

1254

Real-Time Clock

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock Registers

www.ti.com

14.4.1.12 SYNC Register (Offset = 2Ch) [reset = 0h]
SYNC is shown in Figure 14-13 and described in Table 14-13.
Return to Summary Table.
AON Synchronization
This register is used for synchronizing between MCU and entire AON domain.
Figure 14-13. SYNC Register
31

0
WBUSY
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 14-13. SYNC Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

WBUSY

R/W

This register will always return 0,- however it will not return the value
until there are no outstanding write requests between MCU and AON
Note: Writing to this register prior to reading will force a wait until
next SCLK_LF edge. This is recommended for syncing read
registers from AON when waking up from sleep
Failure to do so may result in reading AON values from prior to going
to sleep

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Real-Time Clock

1255

Chapter 15
SWCU117G – February 2015 – Revised February 2017

Watchdog Timer
The watchdog timer (WDT) is used to regain control when the system has failed due to a software error or
to the failure of an external device to respond in the expected way. The WDT can generate a
nonmaskable interrupt (NMI), a regular interrupt, or a reset when a time-out value is reached. In addition,
the WDT can be configured to generate an interrupt to the microcontroller (MCU) on its first time-out and
to generate a reset signal on its second time-out.
Topic

15.1
15.2
15.3
15.4

1256

...........................................................................................................................
WDT Introduction ............................................................................................
WDT Functional Description .............................................................................
WDT Initialization and Configuration .................................................................
Watchdog Timer Registers ...............................................................................

Watchdog Timer

Page

1257
1257
1258
1259

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

WDT Introduction

www.ti.com

15.1 WDT Introduction
WDT has the following features:
• 32-bit down counter with a programmable load register
• Programmable interrupt generation logic with interrupt masking and optional NMI function
• Lock register protection from runaway software
• Reset generation logic with an enable or disable
• User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
The WDT can be configured to generate an interrupt to the controller on its first time-out, and to generate
a reset signal on its second time-out. Once the WDT has been configured, the lock register can be written
to prevent the timer configuration from being inadvertently altered.
There are two possible interrupts that can be driven out of the WDT. The interrupt choice is controlled
using the WDT:CTL.INTTYPE register.

15.2 WDT Functional Description
The WDT module generates the first time-out signal when the 32-bit counter reaches the zero state after
being enabled; enabling the counter also enables the WDT interrupt. Figure 15-1 shows the WDT block
diagram.
The watchdog interrupt can be programmed to be a nonmaskable interrupt (NMI) using the
WDT:CTL.INTTYPE register. After the first time-out event, the 32-bit counter is reloaded with the value of
the WDT Load Register (WDT:LOAD), and the timer resumes counting down from that value. To prevent
the WDT configuration from being inadvertently altered by software, the write access to the watchdog
registers can be locked by writing the WDT:LOCK register to any value. To unlock the WDT, write the
WDT:LOCK register to the value 0x1ACC E551.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset
signal has been enabled by setting the WDT:CTL.RESEN register to 1, the WDT asserts its reset signal to
the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit
counter is loaded with the value in the WDT:LOAD register, and counting resumes from that value.
If the WDT:LOAD register is written with a new value while the WDT counter is counting, then the counter
is loaded with the new value and continues counting.
Writing to the WDT:LOAD register does not clear an active interrupt. An interrupt must be cleared by
writing to the Watchdog Interrupt Clear Register (WDT:ICR). The watchdog module interrupt and reset
generation can be enabled or disabled as required. When the interrupt is enabled again, the 32-bit counter
is preloaded with the load register value (not its last state).
NOTE: The watchdog causes a warm reset in the system. This warm reset can be blocked by
ICEPick, which is useful for debugging. When ICEPick is asserted, the warm reset is blocked
from the rest of the system; however, watchdog itself is reset.
During normal operation the Warm Reset Converted to System Reset feature must be
enabled to ensure that the WDT performs a full system reset. For more details refer to the
Warm Reset section in the Power, Reset and Clock Management chapter.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Watchdog Timer

1257

WDT Initialization and Configuration

www.ti.com

Figure 15-1. WDT Block Diagram
WDT:LOAD

Control / Interrupt
generation

32± bit down counter

WDT:CTL
Interrupt / NMI
WDT:ICR
WDT:RIS
0x 0000 0000
WDT:MIS
INFRASTRUCTURE
clock

WDT:LOCK
Comparator

WDT:VALUE

15.3 WDT Initialization and Configuration
To use the WDT, its peripheral clock must be enabled. The WDT is running off the INFRASTRUCTURE
clock sourced by the MCU PRCM module. The WDT is then configured using the following sequence:
1. Load the WDT:LOAD register with the desired timer load value.
2. If the watchdog is configured to trigger system resets, set the WDT:CTL.RESEN bit.
3. Set the WDT:CTL.INTEN register bit to enable the WDT.
4. Lock the WDT module using the WDT:LOCK register.

1258

Watchdog Timer

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Watchdog Timer Registers

www.ti.com

15.4 Watchdog Timer Registers
15.4.1 WDT Registers
Table 15-1 lists the memory-mapped registers for the WDT. All register offset addresses not listed in
Table 15-1 should be considered as reserved locations and the register contents should not be modified.
Table 15-1. WDT Registers
Offset

Acronym

Section

LOAD

Configuration

Section 15.4.1.1

VALUE

Current Count Value

Section 15.4.1.2

CTL

Control

Section 15.4.1.3

ICR

Interrupt Clear

Section 15.4.1.4

10h

RIS

Raw Interrupt Status

Section 15.4.1.5

14h

MIS

Masked Interrupt Status

Section 15.4.1.6

418h

TEST

Test Mode

Section 15.4.1.7

41Ch

INT_CAUS

Interrupt Cause Test Mode

Section 15.4.1.8

C00h

LOCK

Lock

Section 15.4.1.9

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Watchdog Timer

1259

Watchdog Timer Registers

www.ti.com

15.4.1.1 LOAD Register (Offset = 0h) [reset = FFFFFFFFh]
LOAD is shown in Figure 15-2 and described in Table 15-2.
Return to Summary Table.
Configuration
Figure 15-2. LOAD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WDTLOAD
R/W-FFFFFFFFh

Table 15-2. LOAD Register Field Descriptions
Bit
31-0

1260

Field

Type

Reset

WDTLOAD

R/W

FFFFFFFFh This register is the 32-bit interval value used by the 32-bit counter.
When this register is written, the value is immediately loaded and the
counter is restarted to count down from the new value. If this register
is loaded with 0x0000.0000, an interrupt is immediately generated.

Watchdog Timer

Description

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Watchdog Timer Registers

www.ti.com

15.4.1.2 VALUE Register (Offset = 4h) [reset = FFFFFFFFh]
VALUE is shown in Figure 15-3 and described in Table 15-3.
Return to Summary Table.
Current Count Value
Figure 15-3. VALUE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WDTVALUE
R-FFFFFFFFh

Table 15-3. VALUE Register Field Descriptions
Bit
31-0

Field

Type

Reset

WDTVALUE

FFFFFFFFh This register contains the current count value of the timer.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Description

Watchdog Timer

1261

Watchdog Timer Registers

www.ti.com

15.4.1.3 CTL Register (Offset = 8h) [reset = 0h]
CTL is shown in Figure 15-4 and described in Table 15-4.
Return to Summary Table.
Control
Figure 15-4. CTL Register
31

2
INTTYPE
R/W-0h

1
RESEN
R/W-0h

0
INTEN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

Table 15-4. CTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

INTTYPE

R/W

WDT Interrupt Type
0: WDT interrupt is a standard interrupt.
1: WDT interrupt is a non-maskable interrupt.
0h = Maskable interrupt
1h = Non-maskable interrupt

RESEN

R/W

WDT Reset Enable. Defines the function of the WDT reset source
(see PRCM:WARMRESET.WDT_STAT if enabled)
0: Disabled.
1: Enable the Watchdog reset output.
0h = Reset output Disabled
1h = Reset output Enabled

INTEN

R/W

WDT Interrupt Enable
0: Interrupt event disabled.
1: Interrupt event enabled. Once set, this bit can only be cleared by
a hardware reset.
0h = Interrupt Disabled
1h = Interrupt Enabled

31-3

1262

Watchdog Timer

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Watchdog Timer Registers

www.ti.com

15.4.1.4 ICR Register (Offset = Ch) [reset = 0h]
ICR is shown in Figure 15-5 and described in Table 15-5.
Return to Summary Table.
Interrupt Clear
Figure 15-5. ICR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WDTICR
W-0h

Table 15-5. ICR Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

WDTICR

This register is the interrupt clear register. A write of any value to this
register clears the WDT interrupt and reloads the 32-bit counter from
the LOAD register.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Watchdog Timer

1263

Watchdog Timer Registers

www.ti.com

15.4.1.5 RIS Register (Offset = 10h) [reset = 0h]
RIS is shown in Figure 15-6 and described in Table 15-6.
Return to Summary Table.
Raw Interrupt Status
Figure 15-6. RIS Register
31

0
WDTRIS
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 15-6. RIS Register Field Descriptions
Bit
31-1
0

1264

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

WDTRIS

This register is the raw interrupt status register. WDT interrupt
events can be monitored via this register if the controller interrupt is
masked.
Value Description
0: The WDT has not timed out
1: A WDT time-out event has occurred

Watchdog Timer

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Watchdog Timer Registers

www.ti.com

15.4.1.6 MIS Register (Offset = 14h) [reset = 0h]
MIS is shown in Figure 15-7 and described in Table 15-7.
Return to Summary Table.
Masked Interrupt Status
Figure 15-7. MIS Register
31

0
WDTMIS
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 15-7. MIS Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

WDTMIS

This register is the masked interrupt status register. The value of this
register is the logical AND of the raw interrupt bit and the WDT
interrupt enable bit CTL.INTEN.
Value Description
0: The WDT has not timed out or is masked.
1: An unmasked WDT time-out event has occurred.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Watchdog Timer

1265

Watchdog Timer Registers

www.ti.com

15.4.1.7 TEST Register (Offset = 418h) [reset = 0h]
TEST is shown in Figure 15-8 and described in Table 15-8.
Return to Summary Table.
Test Mode
Figure 15-8. TEST Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

8
STALL
R/W-0h

4
RESERVED
R-0h

0
TEST_EN
R/W-0h

Table 15-8. TEST Register Field Descriptions
Bit
31-9
8

7-1
0

1266

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STALL

R/W

WDT Stall Enable
0: The WDT timer continues counting if the CPU is stopped with a
debugger.
1: If the CPU is stopped with a debugger, the WDT stops counting.
Once the CPU is restarted, the WDT resumes counting.
0h = Disable STALL
1h = Enable STALL

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TEST_EN

R/W

The test enable bit
0: Enable external reset
1: Disables the generation of an external reset. Instead bit 1 of the
INT_CAUS register is set and an interrupt is generated
0h = Test mode Disabled
1h = Test mode Enabled

Watchdog Timer

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Watchdog Timer Registers

www.ti.com

15.4.1.8 INT_CAUS Register (Offset = 41Ch) [reset = 0h]
INT_CAUS is shown in Figure 15-9 and described in Table 15-9.
Return to Summary Table.
Interrupt Cause Test Mode
Figure 15-9. INT_CAUS Register
31

1
CAUSE_RESE
T
R-0h

0
CAUSE_INTR

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

R-0h

Table 15-9. INT_CAUS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CAUSE_RESET

Indicates that the cause of an interrupt was a reset generated but
blocked due to TEST.TEST_EN (only possible when
TEST.TEST_EN is set).

CAUSE_INTR

Replica of RIS.WDTRIS

31-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Watchdog Timer

1267

Watchdog Timer Registers

www.ti.com

15.4.1.9 LOCK Register (Offset = C00h) [reset = 0h]
LOCK is shown in Figure 15-10 and described in Table 15-10.
Return to Summary Table.
Lock
Figure 15-10. LOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WDTLOCK
R/W-0h

Table 15-10. LOCK Register Field Descriptions
Bit
31-0

1268

Field

Type

Reset

Description

WDTLOCK

R/W

WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog
registers for write access. A write of any other value reapplies the
lock, preventing any register updates (NOTE: TEST.TEST_EN bit is
not lockable).
A read of this register returns the following values:
0x0000.0000: Unlocked
0x0000.0001: Locked

Watchdog Timer

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Chapter 16
SWCU117G – February 2015 – Revised February 2017

Random Number Generator
The true random number generator (TRNG) module provides a true, nondeterministic noise source for the
purpose of generating keys, initialization vectors (IVs), and other random number requirements. The
TRNG is built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear
combinatorial circuit. That post-processing of the output data is required to obtain cryptographically secure
random data. Typical applications might be (but are not limited to) the following:
• Generation of cryptographic key material
• Generation of initialization vectors
• Generation of cookies and nonces
• Statistical sampling
• Retry timers in communication protocols
• Noise generation
Topic

16.1
16.2
16.3
16.4
16.5
16.6
16.7

...........................................................................................................................
Overview........................................................................................................
Block Diagram ................................................................................................
TRNG Software Reset ......................................................................................
Interrupt Requests ..........................................................................................
TRNG Operation Description ............................................................................
TRNG Low-Level Programing Guide ..................................................................
Random Number Generator Registers ...............................................................

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Page

1270
1270
1271
1271
1272
1274
1277

Random Number Generator

1269

Overview

www.ti.com

16.1 Overview
The TRNG has the following features:
•

•

•
•

The TRNG is based on 24 ring oscillators (shot noise) to create entropy. To generate this entropy the
system needs a minimum of 28 system clock cycles (for reference) to produce the first random output.
Then the TRNG takes a minimum of 26 system clock cycles to produce each subsequent 64 bits
random number.
Startup time and entropy regeneration time can be controlled between 28 and 224 sampling clock
cycles, and entropy regeneration time can be controlled between 26 and 224 sampling clock cycles to
adapt entropy accumulation time to basic entropy generation rate. Entropy regeneration time can be
tailored in a trade-off between speed of random number generation and amount of entropy in each of
those random numbers.
The TRNG architecture is based on linear-feedback shift register (LFSR) in association with a
nonlinear entropic hasher.
The random numbers are accessible to the applications in a 64-bit read-only register. When the
register is read, the TRNG immediately generates a new value, which is then shifted into the output
register when ready.
If the ready value is not read within a maximum time-out window, the TRNG is set into idle mode
The TRNG provides a built-in self-test that checks the number of consecutive bits sampled to provide
the statistical robustness required by FIPS 140. System alarms are generated based on feedback from
this test.
The internal power-saving mode is built to carefully manage the entropy previously generated.
Interrupt channel allow the transfer of 32-bits data blocks.

16.2 Block Diagram
The TRNG core uses dual-shot noise generators that create unpredictable jittering output when
asynchronously sampled by the system clock provided to the TRNG. The outputs from the shot noise
generators feed a complex nonlinear combinatorial circuit (mixer) that produces the final TRNG output
(see Figure 16-1).
Figure 16-1. Random Number Generator Block Diagram
Clock and Reset

Interrupts

PRCM

FRO
FRO
FRO

1270

Random Number Generator

TRNG core control

FRO control and
error checking

Random number upper word
TRNG:OUT1
Main LSFR
Random number lower word
TRNG:OUT0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

TRNG Software Reset

www.ti.com

The TRNG core consists of two parts:
• The first part contains the FROs, whose output signals are sampled at regular intervals. The FROs are
asynchronous to one another and asynchronous to the sampling clock to make their behavior truly
nondeterministic. Each FRO has an error detection circuit that checks for repeating patterns coming
out of the FRO. If a repeating pattern is detected, the FRO is suspect of having locked onto the
sampling clock, which drastically reduces the amount of entropy generated by that FRO (this is
signaled as a FRO error event).
• The second part is the entropy accumulation circuit that uses an XOR tree to combine the sampled
FRO clock outputs and an 81-bit LFSR to accumulate entropy (TRNG:LFSR0, TRNG:LFSR1, and
TRNG:LFSR2 registers give the 81 bits main entropy accumulation LFSR).
The true entropy source is based upon a predetermined number of free-running oscillators (FROs). The
accumulation of timing jitter, caused (for the largest part) by shot noise, creates uncertainty intervals for
the output transitions of each FRO. Sampling within the uncertainly interval generates a small amount of
entropy, which is accumulated in an LFSR. Entropy generation with multiple FROs in parallel allows the
entropy accumulation to be done far more rapidly than is possible with one FRO.

16.3 TRNG Software Reset
A software reset of the module can be done by writing 1 to the TRNG:SWRESET.RESET register. When a
software reset completes the TRNG:SWRESET.RESET register is automatically reset to 0. By polling the
TRNG:SWRESET.RESET register for 0 the software can ensure that the reset is completed, the software
reset must be completed before doing any TRNG operations.

16.4 Interrupt Requests
An interrupt request, TRNG_IRQ, is generated when data is ready for transmission (or an alarm was
triggered). Table 16-1 lists the event flags, and their masks, that can cause module interrupts.
Table 16-1. Events
Event Flag

Event Mask

Description

TRNG:IRQSTAT.STAT

TRNG:IRQFLAGMASK.RDY
and
TRNG:IRQFLAGMASK.
SHUTDOWN_OVF

Not used, but can be read for combined status of the two
available interrupts

TRNG:IRQFLAGSTAT.RDY

TRNG:IRQFLAGMASK.RDY

When 1, data is available in the TRNG:OUT1 and the
TRNG:OUT0 registers. Use TRNG:IRQFLAGCLR.RDY to
clear it.

TRNG:IRQFLAGMASK.
SHUTDOWN_OFV

When 1, the number of FROs shut down after a second
error event (the number of 1 bits in the
TRNG:ALARMSTOP register) has exceeded the threshold
set by the TRNG:ALARMCNT.SHUTDOWN_THR register.
Use the TRNG:IRQFLAGCLR.SHUTDOWN_OVF register
to clear it.

TRNG:IRQFLAGSTAT.
SHUTDOWN_OVF

The TRNG:ALARMCNT register, together with the TRNG:ALARMMASK and TRNG:ALARMSTOP
registers, can be used by the host to determine if the FRO or sample cycle locking is a problem.
Lock detection in functional mode is performed using the sampled outputs of the individual FROs. A FRO
alarm event is declared when a repeating pattern (of up to four samples length) is detected continuously
for the number of samples defined by the TRNG:ALARMCNT:ALARM_THR register. The alarm event is
logged by setting a bit to pinpoint the FRO in the TRNG:ALARMMASK register. If that bit in the
TRNG:ALARMMASK register was already set, the corresponding bit in the TRNG:ALARMSTOP register is
set and the FRO is switched off to prevent further alarm events from that FRO. If the TRNG:ALARMMASK
register bit was not yet set, the FRO is restarted automatically in an attempt to break the locking. If a FRO
is locked again after detune and re-enable, software must leave the FRO deactivated.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1271

TRNG Operation Description

www.ti.com

The TRNG:ALARMCNT.SHUTDOWN_CNT register bit field keeps track of the number of FROs switched
off (actually, is a count of the number of 1 bits in the TRNG:ALARMSTOP register). The
TRNG:ALARMCNT.SHUTDOWN_THR register bit field allows a configurable threshold to be set to
generate the SHUTDOWN_OVF interrupt. When the TRNG:ALARMCNT.SHUTDOWN_CNT register
exceeds the TRNG:ALARMCNT.SHUTDOWN_THR register, the
TRNG:IRQFLAGSTAT.SHUTDOWN_OVF register bit is set to 1, which can be used to generate an
interrupt.

16.5 TRNG Operation Description
Before the first random number generation, the TRNG:CTL and the TRNG:CFG0 registers must be written
to start accumulating entropy. The entropy is a measure of the uncertainty associated with a random
value. The random numbers are accessible to the application in a 64-bit read-only register TRNG:OUT0
and TRNG:OUT1. When the register is read, the TRNG generates a new value, which is available after
the TRNG:CFG0.MIN_REFILL_CYCLES register system clock cycles and is then shifted into the output
register. Software can use two strategies for operating the TRNG:
•

•

Monitored mode: Software checks the TRNG:ALARMMASK register at regular intervals (on the order
of seconds). If a bit is set there, the TRNG:ALARMSTOP register must also be checked to see if a
FRO was shut down due to multiple alarm events—if none were shut down, the TRNG:ALARMMASK
register can be cleared to get rid of the spurious alarm events. If one or more FROs were shut down,
software can modify the delay selection of those FROs in the TRNG:FRODETUNE register in an
attempt to prevent further locking. For this type of operation, the
TRNG:ALARMCNT.SHUTDOWN_THR register would normally be set to a low value (for instance,
value 2) and the SHUTDOWN_OVF interrupt can then be used to signal abnormal operation conditions
and/or breakdowns of FROs.
Unmonitored mode: Software sets the TRNG:ALARMCNT.SHUTDOWN_THR register to the number
of FROs that are allowed to be shut down before corrective actions must be taken, and then uses the
SHUTDOWN_OVF interrupt to initiate those corrective actions (clearing the TRNG:ALARMMASK and
the TRNG:ALARMSTOP registers, toggling bits in the TRNG:FRODETUNE register). Software must
keep track of the time interval between these interrupts—if they happen too often, this indicates
abnormal operating conditions and/or breakdown of FROs.

16.5.1 TRNG Shutdown
The TRNG can be shutdown in many ways, but not all of them result in storing of entropy. The different
modes are discussed here.
The best way is to not read the last generated random number. After the MAX_REFILL time (maximum of
224 cycles) defined in the TRNG:CFG0 register, the TRNG enters idle mode where all FROs are turned off.
When the generated value is read, the TRNG starts up again and generates a new random seed, which is
ready after the time TRNG:CFG0.MIN_REFILL_CYCLES register. When the TRNG is in idle mode, the
module clock can be turned off. Entropy is kept in between random number creations, so no reset (SW) of
module is needed.
Another approach to shut down the TRNG is to just stop the module clock. By shutting down the TRNG by
stopping the module clock, the entropy is also kept (that is, does not affect randomness), but the FROs
might still be running. The clock can be enabled at any time, and the generation of a random seed is
continued. There is no need for a soft reset of the module.
If the clock is stopped, the TRNG can not be accessed and a bus fault is generated (within the
Interconnect).
If an application that no longer needs the TRNG must go into deep sleep mode without waiting, the
application can write 0 in the TRNG:CTL.TRNG_EN register bit, and the input system clock can be
switched off. After such a shutdown a soft reset of the TRNG module (see register description) should be
performed before generating a new random number because randomness cannot be guaranteed. The
penalty of this shutdown method is that entropy accumulation time is required before the next random
number is ready.

1272

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

TRNG Operation Description

www.ti.com

16.5.2 TRNG Alarms
TRNG alarms happen and are most likely caused by FRO clock to sampling clock frequency locking. The
sampling clock is the same as the system clock for the TRNG, and when the FRO oscillating frequency
gets too close to a multiple of this clock, frequency lock might result in sampling the FRO clock at the
same phase too many times so a repeated pattern is detected. When such a repeated pattern is detected
it is counted, and when this count exceeds the limit set by the TRNG:ALARMCNT.ALARM_THR register
and the alarm event is triggered. Keeping this value high limits the number of alarms, and default is 255
alarm indications before an alarm event is enabled.
When an alarm event is triggered, the associated FRO is automatically shut down and not allowed to
contribute to entropy accumulation. The user must then decide what to do with this event. Two options
exist:
•
•

Change the FRO oscillating frequency
Leave the FRO off
For the first option, a bit in the TRNG:FRODETUNE.FRO_MASK register set to 1 allows the
associated FRO run approximately 5 percent faster. The value of one of these bits may only be
changed while the corresponding FRO is turned off (by temporary writing 0 in the corresponding bits of
the TRNG:FROEN register—in case of an alarm this bit is already set to 0). When the value is
updated, the corresponding FRO must be enabled again.
For the second option, the detune probably had no effect, or the FRO is not oscillating. This state must
be stored so the corresponding bit in the TRNG:FROEN register is kept in off state to eliminate new
alarm triggers caused by the particular FRO.

16.5.3 TRNG Entropy
Entropy is defined as a result of:
• How many FROs are enabled—with more, entropy is achieved faster
• How many samples are accumulated—longer running times yield higher entropy
The more FROs are enabled and the longer they run (that is, how many samples have been stored in the
LSFR), the higher the entropy becomes.
The TRNG module must be running at maximum frequency when creating random values.
Creation time for a random value is defined by the values set in the TRNG:CTL.STARTUP_CYCLES
register, the TRNG:CFG0.MIN_REFILL_CYCLES or the TRNG:CFG0.MAX_REFILL_CYCLES register
and the TRNG:CFG0.SMPL_DIV register; modifications of all these registers can only be done when the
TRNG:CTL.TRNG_EN register is 0.
The TRNG:CFG0.SMPL_DIV register defines how often a sample is collected from the FRO, default value
0 indicates that samples are taken every clock cycle, maximum value 0xF takes one sample every 16
clock cycles. All values of SAMPLE_DIV can be used on this device and it must be set as small as
possible.
To have the same amount of entropy in each created seed, the startup and minimum refill times must be
identical. By using minimum startup and minimum refill time, the entropy per bit is very low. When all
FROs are enabled, a start-up time of 5 ms generates a word with 64-bit entropy.
Low values in the TRNG:CTL.STARTUP_CYCLES register and the TRNG:CFG0.MIN_REFILL_CYCLES
or TRNG:CFG0.MAX_REFILL_CYCLES registers must only be used to generate random values for
nonsecure use like synchronization words, CRC initialization, and so forth. For more secure usages the
minimum of 64-bit entropy and beyond must be defined.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1273

TRNG Low-Level Programing Guide

www.ti.com

16.6 TRNG Low-Level Programing Guide
This section covers the low-level hardware programming sequences for configuration and usage of the
module.

16.6.1 Initialization
16.6.1.1 Interfacing Modules
This section identifies the requirements of initializing the interfacing modules when the TRNG is to be
used for the first time after a device reset. Table 16-2 lists the Initialization of interfacing modules.
Table 16-2. Initialization of Surrounding Modules
Interfacing Module

Comment

PRCM

TRNG module interface clock must be enabled. See PRCM registers PRCM:PDCTL0.PERIPH_ON and
PRCM:SECDMACLKGR.TRNG_CLK_EN.

Cortex-M3

NVIC configuration must be done to enable the interrupt from the TRNG. Only needed for interrupt
based communication.

Interconnect

Interconnect must be enabled for communication with TRNG, which is handled in the PRCM as a
consequence of many settings like CPU in run, sleep, or deep sleep mode, usage of DMA, I2S,
RFCORE, and Crypto engine.

16.6.1.2 TRNG Main Sequence
This procedure initializes the TRNG after a power-on reset (POR). Table 16-3 lists the TRNG main
initialization sequence.
Table 16-3. TRNG Initialization Sequence
Step

Execute a SW reset

TRNG:SWRESET.RESET

Wait for SW completion by polling

TRNG:SWRESET.RESET

Select the number of FRO clock input cycles between two samples

TRNG:CFG0.SMPL_DIV

Select the number of samples taken to gather enough entropy in the FROs
of the module and to generate the first random value

TRNG:CTL.STARTUP_CYCLES

Select the minimum number of samples taken regenerate entropy in the
FROs of the module and to generate subsequent random values

TRNG:CFG0.MIN_REFILL_CYCLES

Select the maximum number of samples taken regenerate entropy in the
FROs of the module and to generate subsequent random values
Also defines timeout period for shutting down the FROs after inactivity

TRNG:CFG0.MAX_REFILL_CYCLES

Configure the desired FROs to run 5% faster

TRNG:FRODETUNE.FRO_MASK

Enable all FROs

TRNG:FROEN.FRO_MASK

Select the maximum number of samples after which a detected repeated
pattern an alarm event is generated

TRNG:ALARMCNT.ALARM_THR

Set the shutdown threshold to the number of FROs allowed to be shut
down (1)

TRNG:ALARMCNT.SHUTDOWN_THR

Enable and start

TRNG:CTL.TRNG_EN

(1)

1274

This step is only required if unmonitored mode is used.

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

TRNG Low-Level Programing Guide

www.ti.com

16.6.1.3 TRNG Operating Modes
This section presents the flow for different operating modes of the TRNG module.
16.6.1.3.1 Polling Mode
In polling mode, both monitored and unmonitored modes are covered. Figure 16-2 shows the TRNG
polling mode.
Figure 16-2. TRNG Polling Mode
Start

Enable the TRNG module
TRNG : CTL.TRNG_EN = 0x1

Yes

Is the result ready?
TRNG : IRQFLAGSTAT.RDY
=0x1

Read the resulted random number LSW
LSW_result = TRNG : OUT0

Monitored mode

Is the shutdown threshold set?
TRNG : ALARMCNT.SHUTDOWN_THR
!=0

Yes

Unmonitored mode

Read the resulted random number MSW
MSW_result = TRNG : OUT1
Yes

Has alarm event occurred?
TRNG:ALARMMASK:FRO_MASK
!=0x0

Clear the result ready event in the status register by
Writing to the acknowledge register
TRNG : IRQFLAGCLR.RDY = 0x1

Yes
Yes

Need more seeds?

Yes

Is (Are) the
FRO(s) shut down?
TRNG : ALARMSTOP.FRO_FLAGS
!= 0x0

Is the shutdown threshold reached?
TRNG : IRQFLAGSTAT.SHUTDOWN_OVF
= 0x1

Clear alarm events
TRNG : ALARMMASK.FRO_MASK = 0x0
TRNG : ALARMSTOP.FRO_FLAGS = 0x0

Modify the delay selection in an attempt to prevent
further locking
(detune the particular FROs that had the alarm)
TRNG : FRODETUNE.FRO_MASK = 0xModify the delay selection in an attempt to prevent
Further locking
(detune the particular FROs that had the alarm)
TRNG : FRODETUNE.FRO_MASK = 0x-

Re-enable the shutdown FROs
TRNG:FROEN.FRO_MASK = 0x-

Clear the shutdown overflow event in the status
Register by writing to the acknowledge register
TRNG : IRQFLAGCLR.SHUTDOWN_OVF = 0x1

Have too many
FROs been shutdown?
TRNG : ALARMCNT : SHUTDOWN_CNT
>min_number_of_FROs

Yes

Yes
Stop the TRNG module as required
number of FROs is not valid

Detuning already performed
On shutdown FROs

Start

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1275

TRNG Low-Level Programing Guide

www.ti.com

16.6.1.3.2 Interrupt Mode
This section covers the event servicing of the module. Only the unmonitored mode is covered. Table 16-4
lists the TRNG interrupt mode steps, while Figure 16-3 shows the interrupt service routine flow.
Table 16-4. TRNG Interrupt Mode
Step

Value

Enable interrupt generation when data is ready (available)
in the output registers.

TRNG:IRQFLAGMASK.RDY

0x1

Enable the shutdown overflow interrupt generation when
the maximum possible FRO shutdowns reach the selected
shutdown threshold

TRNG:IRQFLAGMASK.SHUTDOWN_OVF

0x1

Enable the TRNG

TRNG:CTL.TRNG_EN

0x1

Figure 16-3. Interrupt Service Routine
Enter ISR

Read the status register to determine the type of the
granted interrupt value = TRNG:IRQFLAGSTAT

Yes

Interrupt caused
By ready result in output registers?
TRNG : IRQFLAGSTAT.RDY = 0x1

Read the resulted random number LSW
LSW_result = TRNG : OUT0

Clear alarm events
TRNG : ALARMMASK.FRO_MASK = 0x0
TRNG : ALARMSTOP.FRO_FLAGS = 0x0

Read the resulted random number MSW
MSW_result = TRNG : OUT1

Modify the delay selection in an attempt to prevent
further locking
(detune the particular FROs that had the alarm)
TRNG : FRODETUNE.FRO_MASK = 0x-

Clear the result ready event in the status register by
Writing to the acknowledge register
TRNG : IRQFLAGCLR.RDY = 0x1

Re-enable the shutdown FROs
TRNG:FROEN.FRO_MASK = 0x-

Clear the shutdown overflow event in the status
Register by writing to the acknowledge register
TRNG : IRQFLAGCLR.SHUTDOWN_OVF = 0x1

Exit ISR

1276

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator Registers

www.ti.com

16.7 Random Number Generator Registers
16.7.1 TRNG Registers
Table 16-5 lists the memory-mapped registers for the TRNG. All register offset addresses not listed in
Table 16-5 should be considered as reserved locations and the register contents should not be modified.
Table 16-5. TRNG Registers
Offset

Acronym

Section

OUT0

Random Number Lower Word Readout Value

Section 16.7.1.1

OUT1

Random Number Upper Word Readout Value

Section 16.7.1.2

IRQFLAGSTAT

Interrupt Status

Section 16.7.1.3

IRQFLAGMASK

Interrupt Mask

Section 16.7.1.4

10h

IRQFLAGCLR

Interrupt Flag Clear

Section 16.7.1.5

14h

CTL

Control

Section 16.7.1.6

18h

CFG0

Configuration 0

Section 16.7.1.7

1Ch

ALARMCNT

Alarm Control

Section 16.7.1.8

20h

FROEN

FRO Enable

Section 16.7.1.9

24h

FRODETUNE

FRO De-tune Bit

Section 16.7.1.10

28h

ALARMMASK

Alarm Event

Section 16.7.1.11

2Ch

ALARMSTOP

Alarm Shutdown

Section 16.7.1.12

30h

LFSR0

LFSR Readout Value

Section 16.7.1.13

34h

LFSR1

LFSR Readout Value

Section 16.7.1.14

38h

LFSR2

LFSR Readout Value

Section 16.7.1.15

78h

HWOPT

TRNG Engine Options Information

Section 16.7.1.16

7Ch

HWVER0

HW Version 0

Section 16.7.1.17

1FD8h

IRQSTATMASK

Interrupt Status After Masking

Section 16.7.1.18

1FE0h

HWVER1

HW Version 1

Section 16.7.1.19

1FECh

IRQSET

Interrupt Set

Section 16.7.1.20

1FF0h

SWRESET

SW Reset Control

Section 16.7.1.21

1FF8h

IRQSTAT

Interrupt Status

Section 16.7.1.22

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1277

Random Number Generator Registers

www.ti.com

16.7.1.1 OUT0 Register (Offset = 0h) [reset = 0h]
OUT0 is shown in Figure 16-4 and described in Table 16-6.
Return to Summary Table.
Random Number Lower Word Readout Value
Figure 16-4. OUT0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VALUE_31_0
R-0h

Table 16-6. OUT0 Register Field Descriptions
Bit
31-0

1278

Field

Type

Reset

Description

VALUE_31_0

LSW of 64- bit random value. New value ready when
IRQFLAGSTAT.RDY = 1.

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator Registers

www.ti.com

16.7.1.2 OUT1 Register (Offset = 4h) [reset = 0h]
OUT1 is shown in Figure 16-5 and described in Table 16-7.
Return to Summary Table.
Random Number Upper Word Readout Value
Figure 16-5. OUT1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VALUE_63_32
R-0h

Table 16-7. OUT1 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

VALUE_63_32

MSW of 64-bit random value. New value ready when
IRQFLAGSTAT.RDY = 1.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1279

Random Number Generator Registers

www.ti.com

16.7.1.3 IRQFLAGSTAT Register (Offset = 8h) [reset = 0h]
IRQFLAGSTAT is shown in Figure 16-6 and described in Table 16-8.
Return to Summary Table.
Interrupt Status
Figure 16-6. IRQFLAGSTAT Register
31
NEED_CLOCK
R-0h

27
RESERVED
R-0h

1
SHUTDOWN_
OVF
R-0h

0
RDY

RESERVED
R-0h
15

12
RESERVED
R-0h

4
RESERVED
R-0h

R-0h

Table 16-8. IRQFLAGSTAT Register Field Descriptions
Bit

Field

Type

Reset

Description

NEED_CLOCK

1: Indicates that the TRNG is busy generating entropy or is in one of
its test modes - clocks may not be turned off and the power supply
voltage must be kept stable.
0: TRNG is idle and can be shut down

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SHUTDOWN_OVF

1: The number of FROs shut down (i.e. the number of '1' bits in the
ALARMSTOP register) has exceeded the threshold set by
ALARMCNT.SHUTDOWN_THR
Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0'
again.

RDY

1: Data are available in OUT0 and OUT1.
Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears
this bit to '0'.
If a new number is already available in the internal register of the
TRNG, the number is directly clocked into the result register. In this
case the status bit is asserted again, after one clock cycle.

30-2

1280

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator Registers

www.ti.com

16.7.1.4 IRQFLAGMASK Register (Offset = Ch) [reset = 0h]
IRQFLAGMASK is shown in Figure 16-7 and described in Table 16-9.
Return to Summary Table.
Interrupt Mask
Figure 16-7. IRQFLAGMASK Register
31

1
SHUTDOWN_
OVF
R/W-0h

0
RDY

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

R/W-0h

Table 16-9. IRQFLAGMASK Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SHUTDOWN_OVF

R/W

1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt
from this module.

RDY

R/W

1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this
module.

31-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1281

Random Number Generator Registers

www.ti.com

16.7.1.5 IRQFLAGCLR Register (Offset = 10h) [reset = 0h]
IRQFLAGCLR is shown in Figure 16-8 and described in Table 16-10.
Return to Summary Table.
Interrupt Flag Clear
Figure 16-8. IRQFLAGCLR Register
31

1
SHUTDOWN_
OVF
W-0h

0
RDY

RESERVED
W-0h
23

20
RESERVED
W-0h

12
RESERVED
W-0h

4
RESERVED
W-0h

W-0h

Table 16-10. IRQFLAGCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SHUTDOWN_OVF

1: Clear IRQFLAGSTAT.SHUTDOWN_OVF.

RDY

1: Clear IRQFLAGSTAT.RDY.

31-2

1282

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator Registers

www.ti.com

16.7.1.6 CTL Register (Offset = 14h) [reset = 0h]
CTL is shown in Figure 16-9 and described in Table 16-11.
Return to Summary Table.
Control
Figure 16-9. CTL Register
31

28
27
STARTUP_CYCLES
R/W-0h

20
19
STARTUP_CYCLES
R/W-0h

13
RESERVED
R-0h

10
TRNG_EN
R/W-0h

5
RESERVED
R-0h

2
NO_LFSR_FB
R/W-0h

1
TEST_MODE
R/W-0h

8
RESERVED
R-0h
0
RESERVED
R/W-0h

Table 16-11. CTL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

STARTUP_CYCLES

R/W

This field determines the number of samples (between 28 and 224)
taken to gather entropy from the FROs during startup. If the written
value of this field is zero, the number of samples is 224, otherwise the
number of samples equals the written value times 28.
0x0000: 224 samples
0x0001: 1*28 samples
0x0002: 2*28 samples
0x0003: 3*28 samples
...
0x8000: 32768*28 samples
0xC000: 49152*28 samples
...
0xFFFF: 65535*28 samples
This field can only be modified while TRNG_EN is 0. If 1 an update
will be ignored.

15-11

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TRNG_EN

R/W

0: Forces all TRNG logic back into the idle state immediately.
1: Starts TRNG, gathering entropy from the FROs for the number of
samples determined by STARTUP_CYCLES.

9-3

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

NO_LFSR_FB

R/W

1: Remove XNOR feedback from the main LFSR, converting it into a
normal shift register for the XOR-ed outputs of the FROs (shifting
data in on the LSB side). A '1' also forces the LFSR to sample
continuously.
This bit can only be set to '1' when TEST_MODE is also set to '1'
and should not be used for other than test purposes

TEST_MODE

R/W

1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2
registers (the latter are automatically cleared before enabling
access) and keeps IRQFLAGSTAT.NEED_CLOCK at '1'.
This bit shall not be used unless you need to change the LFSR seed
prior to creating a new random value. All other testing is done
external to register control.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1283

Random Number Generator Registers

www.ti.com

16.7.1.7 CFG0 Register (Offset = 18h) [reset = 0h]
CFG0 is shown in Figure 16-10 and described in Table 16-12.
Return to Summary Table.
Configuration 0
Figure 16-10. CFG0 Register
31

14
13
RESERVED
R-0h

10
9
SMPL_DIV
R/W-0h

24
23
22
MAX_REFILL_CYCLES
R/W-0h
8

4
3
2
MIN_REFILL_CYCLES
R/W-0h

Table 16-12. CFG0 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

MAX_REFILL_CYCLES

R/W

This field determines the maximum number of samples (between 28
and 224) taken to re-generate entropy from the FROs after reading
out a 64 bits random number. If the written value of this field is zero,
the number of samples is 224, otherwise the number of samples
equals the written value times 28.
0x0000: 224 samples
0x0001: 1*28 samples
0x0002: 2*28 samples
0x0003: 3*28 samples
...
0x8000: 32768*28 samples
0xC000: 49152*28 samples
...
0xFFFF: 65535*28 samples
This field can only be modified while CTL.TRNG_EN is 0.

15-12

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-8

SMPL_DIV

R/W

This field directly controls the number of clock cycles between
samples taken from the FROs. Default value 0 indicates that
samples are taken every clock cycle,
maximum value 0xF takes one sample every 16 clock cycles.
This field must be set to a value such that the slowest FRO (even
under worst-case
conditions) has a cycle time less than twice the sample period.
This field can only be modified while CTL.TRNG_EN is '0'.

7-0

MIN_REFILL_CYCLES

R/W

This field determines the minimum number of samples (between 26
and 214) taken to re-generate entropy from the FROs after reading
out a 64 bits random number. If the value of this field is zero, the
number of samples is fixed to the value determined by the
MAX_REFILL_CYCLES field, otherwise the minimum number of
samples equals the written value times 64 (which can be up to 214).
To ensure same entropy in all generated random numbers the value
0 should be used. Then MAX_REFILL_CYCLES controls the
minimum refill interval. The number of samples defined here cannot
be higher than the number defined by the 'max_refill_cycles' field
(i.e. that field takes precedence). No random value will be created if
min refill > max refill.
This field can only be modified while CTL.TRNG_EN = 0.
0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers
have same entropy)
0x01: 1*26 samples
0x02: 2*26 samples
...
0xFF: 255*26 samples

1284

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator Registers

www.ti.com

16.7.1.8 ALARMCNT Register (Offset = 1Ch) [reset = FFh]
ALARMCNT is shown in Figure 16-11 and described in Table 16-13.
Return to Summary Table.
Alarm Control
Figure 16-11. ALARMCNT Register
31

27
26
SHUTDOWN_CNT
R/W-0h

22
RESERVED
R-0h

18
SHUTDOWN_THR
R/W-0h

RESERVED
R-0h

RESERVED
R-0h
7

4
ALARM_THR
R/W-FFh

Table 16-13. ALARMCNT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-30

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

29-24

SHUTDOWN_CNT

R/W

Read-only, indicates the number of '1' bits in ALARMSTOP register.
The maximum value equals the number of FROs.

23-21

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

20-16

SHUTDOWN_THR

R/W

Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF
interrupt. The interrupt is triggered when SHUTDOWN_CNT value
exceeds this bit field.

15-8

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

ALARM_THR

R/W

FFh

Alarm detection threshold for the repeating pattern detectors on each
FRO. An FRO 'alarm event' is declared when a repeating pattern (of
up to four samples length) is detected continuously for the number of
samples defined by this field's value. Reset value 0xFF should keep
the number of 'alarm events' to a manageable level.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1285

Random Number Generator Registers

www.ti.com

16.7.1.9 FROEN Register (Offset = 20h) [reset = 00FFFFFFh]
FROEN is shown in Figure 16-12 and described in Table 16-14.
Return to Summary Table.
FRO Enable
Figure 16-12. FROEN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
RESERVED
FRO_MASK
R-0h
R/W-00FFFFFFh

Table 16-14. FROEN Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-0

FRO_MASK

R/W

00FFFFFFh Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'.
Default state is all '1's to enable all FROs after power-up. Note that
they are not actually started up before the CTL.TRNG_EN bit is set
to '1'.
Bits are automatically forced to '0' here (and cannot be written to '1')
while the corresponding bit in ALARMSTOP.FRO_FLAGS has value
'1'.

1286

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator Registers

www.ti.com

16.7.1.10 FRODETUNE Register (Offset = 24h) [reset = 0h]
FRODETUNE is shown in Figure 16-13 and described in Table 16-15.
Return to Summary Table.
FRO De-tune Bit
Figure 16-13. FRODETUNE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
FRO_MASK
R-0h
R/W-0h

Table 16-15. FRODETUNE Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-0

FRO_MASK

R/W

De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run
approximately 5% faster. The value of one of these bits may only be
changed while the corresponding FRO is turned off (by temporarily
writing a '0' in the corresponding
bit of the FROEN.FRO_MASK register).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1287

Random Number Generator Registers

www.ti.com

16.7.1.11 ALARMMASK Register (Offset = 28h) [reset = 0h]
ALARMMASK is shown in Figure 16-14 and described in Table 16-16.
Return to Summary Table.
Alarm Event
Figure 16-14. ALARMMASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
FRO_MASK
R/W-0h
R/W-0h

Table 16-16. ALARMMASK Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-0

FRO_MASK

R/W

Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n]
indicates FRO 'n' experienced an 'alarm event'.

1288

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator Registers

www.ti.com

16.7.1.12 ALARMSTOP Register (Offset = 2Ch) [reset = 0h]
ALARMSTOP is shown in Figure 16-15 and described in Table 16-17.
Return to Summary Table.
Alarm Shutdown
Figure 16-15. ALARMSTOP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
FRO_FLAGS
R-0h
R/W-0h

Table 16-17. ALARMSTOP Register Field Descriptions
Field

Type

Reset

Description

31-24

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

23-0

FRO_FLAGS

R/W

Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n]
indicates FRO 'n' experienced more than one 'alarm event' in quick
succession and has been turned off. A '1' in this field forces the
corresponding bit in FROEN.FRO_MASK to '0'.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1289

Random Number Generator Registers

www.ti.com

16.7.1.13 LFSR0 Register (Offset = 30h) [reset = 0h]
LFSR0 is shown in Figure 16-16 and described in Table 16-18.
Return to Summary Table.
LFSR Readout Value
Figure 16-16. LFSR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LFSR_31_0
R/W-0h

Table 16-18. LFSR0 Register Field Descriptions
Bit
31-0

1290

Field

Type

Reset

Description

LFSR_31_0

R/W

Bits [31:0] of the main entropy accumulation LFSR. Register can
only be accessed when CTL.TEST_MODE = 1.
Register contents will be cleared to zero before access is enabled.

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator Registers

www.ti.com

16.7.1.14 LFSR1 Register (Offset = 34h) [reset = 0h]
LFSR1 is shown in Figure 16-17 and described in Table 16-19.
Return to Summary Table.
LFSR Readout Value
Figure 16-17. LFSR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LFSR_63_32
R/W-0h

Table 16-19. LFSR1 Register Field Descriptions
Bit
31-0

Field

Type

Reset

Description

LFSR_63_32

R/W

Bits [63:32] of the main entropy accumulation LFSR. Register can
only be accessed when CTL.TEST_MODE = 1.
Register contents will be cleared to zero before access is enabled.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1291

Random Number Generator Registers

www.ti.com

16.7.1.15 LFSR2 Register (Offset = 38h) [reset = 0h]
LFSR2 is shown in Figure 16-18 and described in Table 16-20.
Return to Summary Table.
LFSR Readout Value
Figure 16-18. LFSR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
RESERVED
LFSR_80_64
R/W-0h
R/W-0h

Table 16-20. LFSR2 Register Field Descriptions
Field

Type

Reset

Description

31-17

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

16-0

LFSR_80_64

R/W

Bits [80:64] of the main entropy accumulation LFSR. Register can
only be accessed when CTL.TEST_MODE = 1.
Register contents will be cleared to zero before access is enabled.

1292

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator Registers

www.ti.com

16.7.1.16 HWOPT Register (Offset = 78h) [reset = 600h]
HWOPT is shown in Figure 16-19 and described in Table 16-21.
Return to Summary Table.
TRNG Engine Options Information
Figure 16-19. HWOPT Register
31

14
13
RESERVED
R-0h

24
23
RESERVED
R-0h

9
8
NR_OF_FROS
R-18h

3
2
RESERVED
R-0h

Table 16-21. HWOPT Register Field Descriptions
Field

Type

Reset

Description

31-12

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-6

NR_OF_FROS

18h

Number of FROs implemented in this TRNG, value 24 (decimal).

5-0

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1293

Random Number Generator Registers

www.ti.com

16.7.1.17 HWVER0 Register (Offset = 7Ch) [reset = 0200B44Bh]
HWVER0 is shown in Figure 16-20 and described in Table 16-22.
Return to Summary Table.
HW Version 0
EIP Number And Core Revision
Figure 16-20. HWVER0 Register
31

30
29
RESERVED
R-0h

26
25
HW_MAJOR_VER
R-2h

12
11
EIP_NUM_COMPL
R-B4h

22
21
HW_MINOR_VER
R-0h
6

4
3
EIP_NUM
R-4Bh

18
17
HW_PATCH_LVL
R-0h
2

Table 16-22. HWVER0 Register Field Descriptions
Field

Type

Reset

Description

31-28

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

27-24

HW_MAJOR_VER

4 bits binary encoding of the major hardware revision number.

23-20

HW_MINOR_VER

4 bits binary encoding of the minor hardware revision number.

19-16

HW_PATCH_LVL

4 bits binary encoding of the hardware patch level, initial release will
carry value zero.

15-8

EIP_NUM_COMPL

B4h

Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4.

7-0

EIP_NUM

4Bh

8 bits binary encoding of the module number. This TRNG gives
0x4B.

1294

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator Registers

www.ti.com

16.7.1.18 IRQSTATMASK Register (Offset = 1FD8h) [reset = 0h]
IRQSTATMASK is shown in Figure 16-21 and described in Table 16-23.
Return to Summary Table.
Interrupt Status After Masking
Figure 16-21. IRQSTATMASK Register
31

1
SHUTDOWN_
OVF
R-0h

0
RDY

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

R-0h

Table 16-23. IRQSTATMASK Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SHUTDOWN_OVF

Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF
AND'ed with IRQFLAGMASK.SHUTDOWN_OVF)

RDY

New random value available (result of IRQFLAGSTAT.RDY AND'ed
with IRQFLAGMASK.RDY)

31-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1295

Random Number Generator Registers

www.ti.com

16.7.1.19 HWVER1 Register (Offset = 1FE0h) [reset = 20h]
HWVER1 is shown in Figure 16-22 and described in Table 16-24.
Return to Summary Table.
HW Version 1
TRNG Revision Number
Figure 16-22. HWVER1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3
REV
R-20h

Table 16-24. HWVER1 Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

REV

20h

The revision number of this module is Rev 2.0.

1296

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator Registers

www.ti.com

16.7.1.20 IRQSET Register (Offset = 1FECh) [reset = 0h]
IRQSET is shown in Figure 16-23 and described in Table 16-25.
Return to Summary Table.
Interrupt Set
Figure 16-23. IRQSET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RDY
R/W-0h

Table 16-25. IRQSET Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

RDY

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1297

Random Number Generator Registers

www.ti.com

16.7.1.21 SWRESET Register (Offset = 1FF0h) [reset = 0h]
SWRESET is shown in Figure 16-24 and described in Table 16-26.
Return to Summary Table.
SW Reset Control
Figure 16-24. SWRESET Register
31

0
RESET
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 16-26. SWRESET Register Field Descriptions
Bit
31-1
0

1298

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RESET

R/W

Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0
for reset to be completed.

Random Number Generator

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator Registers

www.ti.com

16.7.1.22 IRQSTAT Register (Offset = 1FF8h) [reset = 0h]
IRQSTAT is shown in Figure 16-25 and described in Table 16-27.
Return to Summary Table.
Interrupt Status
Figure 16-25. IRQSTAT Register
31

0
STAT
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 16-27. IRQSTAT Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STAT

TRNG Interrupt status. OR'ed version of
IRQFLAGSTAT.SHUTDOWN_OVF and IRQFLAGSTAT.RDY

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Random Number Generator

1299

Chapter 17
SWCU117G – February 2015 – Revised February 2017

AUX – Sensor Controller with Digital and Analog
Peripherals
This chapter describes the functionality of the AUX subsystem on the CC26x0 and CC13x0 platform.
Topic

17.1
17.2
17.3
17.4
17.5
17.6
17.7

1300

...........................................................................................................................
Introduction ...................................................................................................
Memory Mapping ............................................................................................
I/O Mapping ....................................................................................................
Modules .........................................................................................................
Power Management .........................................................................................
Clock Management..........................................................................................
AUX – Sensor Controller Registers ...................................................................

AUX – Sensor Controller with Digital and Analog Peripherals

Page

1301
1303
1305
1306
1325
1328
1330

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Introduction

www.ti.com

17.1 Introduction
The AUX is a collective description of all the analog peripherals (ADC, comparators, and current source)
and the digital modules in the AUX power domain (AUX_PD) such as the sensor controller, timers, timeto-digital converter, and others.
The AUX_PD is located within the AON voltage domain of the device. The sensor controller can do its
own power and clock management of AUX_PD, independently of the MCU domain. The sensor controller
can also continue doing tasks while the MCU subsystem is powered down, but with limited resources
compared to the larger MCU domain.
All registers in the AUX_PD and the AUX SRAM are memory-mapped in the MCU domain, and can be
accessed by the system CPU. Peripherals can be used in the AUX directly from the system CPU.
The AUX modules are slaves to the system MCU and cannot access MCU peripherals. Instead, the
sensor controller can communicate with the MCU domain through event signaling routed to the system
CPU as interrupts through the MCU event fabric.
This process enables the sensor controller to collect and process data in SRAM, and interrupt the system
CPU as necessary.
Due to its small size and implementation in an ultra-low-leakage technology, the sensor controller can
perform certain tasks at significantly lower power consumption than the MCU subsystem.
Some typical use cases where the sensor controller can offload the MCU subsystem:
• ADC sampling and filtering of results
• Frequency measurements to support oscillator calibration
• Frequency measurements to compensate RTC frequency
• Control of GPIO pins, including bit-banged SPI, I2C, and UART
• Capacitive sensing and filtering of measurement results to reduce load on the system CPU
• Comparator monitoring
• Software-defined wake up of the MCU domain based on, for example, inputs from sensors
NOTE:

To ease development of program code running on the sensor controller, TI provides a tool
chain for writing software for the controller, Sensor Controller Studio, which is a fully
integrated tool consisting of an IDE, compiler, assembler, and linker.
This tool chain can be used to write C-like code for the controller, and has a power and
event management framework included behind the scenes which handles most of the
complexity described in the AUX chapters regarding the sensor controller, events and power
management, and the complexity that arises in a multi-CPU system.
The tool chain also has indirect JTAG support through the system CPU DAP, for testing and
debugging code running on the sensor controller.
The Sensor Controller Studio outputs drivers, used by the system CPU to configure and
interface the sensor controller, as well as machine code that is copied to AUX RAM from
flash by the system CPU before execution starts. There are also a number of examples
included with Sensor Controller Studio to get started with development.
Accessing the analog peripherals from the system CPU must be done by using TI-provided
drivers to ensure proper control of power management.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1301

Introduction

www.ti.com

17.1.1 AUX Hardware Overview
Figure 17-1. AUX_PD Block Diagram

System (MCU) Bus Interface
Time-to-Digital
Converter
HW
RAM

Arbitrator
AUX Control
- ADC
- Comparators
- Current Source

Event Control

Event BUS

Peripheral BUS (PBUS)

Sensor
Controller

Timer 0/1

I/O Control
Wakeup Controller

Oscillator Interface
Semaphore

AUX Analog Interface

The AUX power domain is connected to the MCU system through an asynchronous interface, ensuring
that all modules connected to the AUX bus are accessible from the system CPU.
The peripherals in AUX_PD are connected to a 32-bit wide bus called PBUS, and all registers are aligned
on 32-bit boundaries regardless of size to allow access from both the 32-bit system CPU and the 16-bit
sensor controller. All peripherals, other than the ADI and DDI modules, only implement 16-bit registers.
The sensor controller always wins arbitration when the system CPU accesses the same peripheral
simultaneously, ensuring minimum execution time for the sensor controller. The sensor controller uses two
or three clock cycles per instruction, dependent on operand size used. Accessing the oscillator or analog
interfaces requires more cycles, as the sensor controller is communicating with asynchronous peripherals
in the analog domain of the chip.
The arbiter prevents accesses to AUX peripherals which are not enabled (clock is stopped), or if the
address region is not assigned to a peripheral.

1302

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Memory Mapping

www.ti.com

If the source of the illegal operation is the MCU system, the arbiter returns a Bus Fault. If the source of the
illegal access is the sensor controller, the arbiter suspends the sensor controller by setting the
AUX_SCE:CTL.SUSPEND register, and the flag AUX_SCE:CPUSTAT.BUS_ERROR is set.
The event bus in AUX routes events between AUX peripherals, as well as to and from the MCU and AON
event fabric, which can be used, for example, to trigger actions in modules as well as interrupting the
sensor controller.

17.2 Memory Mapping
The arbitrator in AUX_PD maps the system CPU and sensor controller addresses into local PBUS
addresses. Each peripheral instance has a 4-KB memory space allocated in the system CPU address
space.
The addresses of the most frequently used registers in the different peripherals are aliased down to the
lower 256 words (512 bytes) in the AUX memory space, which can only be accessed by the sensor
controller. Accessing an alias address improves the execution time of an instruction by one clock cycle,
compared to using the direct peripheral 16-bit address.
Table 17-1 lists the memory map of the AUX peripherals.
Table 17-1. Memory Map of AUX Peripherals
AUX Peripheral Instance

Description

Start Address

AUX_ARBITER (alias of frequently used
registers)

Arbitrator (1)

0x 400C 0000

AUX_AIODIOCTRL0

IO Bank 0

0x 400C 1000

AUX_AIODIOCTRL1

IO Bank 1

0x 400C 2000

AUX_TDC

Time-to-digital converter

0x 400C 4000

AUX_EVCTRL

Event control

0x 400C 5000

AUX_WUC

Wake-up control

0x 400C 6000

AUX_TIMER

Timers

0x 400C 7000

AUX_SEMAPH

Semaphore

0x 400C 8000

AUX_ANAIF

Analog control

0x 400C 9000

DDI_0_OSC

Oscillator interface

0x 400C A000

AUX_ADI

Analog interface

0x 400C B000

AUX_RAM

AUX SRAM

0x 400E 0000

AUX_SCE

Sensor controller engine control and status (2)

0x 400E 1000

(1)
(2)

Only accessible for the sensor controller
Only accessible for the system CPU

17.2.1 Alias of Commonly Used Registers
Table 17-2 defines the mapping for the sensor controller to use direct I/O access to selected registers in
the peripherals.
Table 17-2. Register Mapping
Register Bank

Original Address

Alias Address

AUX_ANAIF

ADCCTL

0x400C 9000+0x10

AUX_ANAIF

ADCFIFOSTAT

0x400C 9000+0x14

AUX_ANAIF

ADCFIFO

0x400C 9000+0x18

AUX_ANAIF

ADCTRIG

0x400C 0000+0x1C

AUX_TDCIF

CTL

0x400C 4000+0x00

AUX_TDCIF

STAT

0x400C 4000+0x04

AUX_TDCIF

RESULT (lowest 16 bits)

0x400C 4000+0x08

AUX_TDCIF

RESULT (highest 8 bits)

0x400C 4000+0x0A

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals 1303

Memory Mapping

www.ti.com

Table 17-2. Register Mapping (continued)
Register Bank

Original Address

Alias Address

AUX_TDCIF

TRIGSRC

0x400C 4000+0x10

AUX_TIMER

CFG0

0x400C 7000+0x00

AUX_TIMER

CFG1

0x400C 7000+0x04

AUX_TIMER

T0CTL

0x400C 7000+0x08

AUX_TIMER

T0TARGET

0x400C 7000+0x0C

AUX_TIMER

T1TARGET

0x400C 7000+0x10

AUX_AIODIO0

GPIODOUT

0x400C 1000+0x00

AUX_AIODIO1

GPIODOUT

0x400C 2000+0x00

AUX_AIODIO0

IOMODE

0x400C 1000+0x04

AUX_AIODIO1

IOMODE

0x400C 2000+0x04

AUX_AIODIO0

GPIODIN

0x400C 1000+0x08

AUX_AIODIO1

GPIODIN

0x400C 2000+0x08

AUX_AIODIO0

GPIODOUTSET

0x400C 1000+0x0C

AUX_AIODIO1

GPIODOUTSET

0x400C 2000+0x0C

AUX_AIODIO0

GPIODOUTCLR

0x400C 1000+0x10

AUX_AIODIO1

GPIODOUTCLR

0x400C 2000+0x10

AUX_AIODIO0

GPIODOUTTGL

0x400C 1000+0x14

AUX_AIODIO1

GPIODOUTTGL

0x400C 2000+0x14

AUX_SMPH

SMPH0

0x400C 8000+0x00

AUX_SMPH

SMPH1

0x400C 8000+0x04

AUX_SMPH

SMPH2

0x400C 8000+0x08

AUX_SMPH

SMPH3

0x400C 8000+0x0C

AUX_SMPH

SMPH4

0x400C 8000+0x10

AUX_SMPH

SMPH5

0x400C 8000+0x14

AUX_SMPH

SMPH6

0x400C 8000+0x18

AUX_SMPH

SMPH7

0x400C 8000+0x1C

AUX_SMPH

AUTOTAKE

0x400C 8000+0x20

AUX_WUC

MODCLKEN0

0x400C 6000+0x00

AUX_WUC

PWROFFREQ

0x400C 6000+0x04

AUX_WUC

PWRDWNREQ

0x400C 6000+0x08

AUX_EVCTL

VECCFG0

0x400C 5000+0x00

AUX_EVCTL

VECCFG1

0x400C 5000+0x04

AUX_ANAIF

ISRCCTRL

0x400C 9000+0x20

AUX_AIODIO0

GPIODIE

0x400C 1000+0x18

AUX_AIODIO1

GPIODIE

0x400C 2000+0x18

AUX_EVCTL

VECFLAGS

0x400C 5000+0x34

AUX_EVCTL

SCEWEVSEL

0x400C 5000+0x08

AUX_EVCTL

SWEVSET

0x400C 5000+0x18

AUX_EVCTL

DMASWREQ

0x400C 5000+0x30

AUX_WUC

WUEVFLAGS

0x400C 6000+0x28

AUX_WUC

WUEVCLR

0x400C 6000+0x2C

AUX_WUC

ADCCLKCTL

0x400C 6000+0x30

AUX_WUC

TDCCLKCTL

0x400C 6000+0x34

AUX_WUC

REFCLKCTL

0x400C 6000+0x38

AUX_WUC

RTCSUBSECINCCTL

0x400C 6000+0x44

AUX_WUC

PWROFFREQ

0x400C 6000+0x04

AUX_WUC

PWRDWNREQ

0x400C 6000+0x08

1304AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I/O Mapping

www.ti.com

Table 17-2. Register Mapping (continued)
Register Bank

Original Address

Alias Address

AUX_WUC

PWRDWNACK

0x400C 6000+0x0C

AUX_WUC

CLKLFREQ

0x400C 6000+0x10

AUX_WUC

CLKLFACK

0x400C 6000+0x14

AUX_WUC

BGAPREQ

0x400C 6000+0x20

AUX_WUC

BGAPACK

0x400C 6000+0x24

AUX_WUC

MCUBUSCTL

0x400C 6000+0x48

AUX_WUC

MCUBUSSTAT

0x400C 6000+0x4C

AUX_EVCTL

EVTOMCUFLAGSCLR

0x400C 5000+0x38

AUX_EVCTL

EVTOAONFLAGSCLR

0x400C 5000+0x3C

AUX_EVCTL

VECFLAGSCLR

0x400C 5000+0x40

AUX_WUC

MODCLKEN1

0x400C 6000+0x5C

AUX_TIMER

T1CTL

0x400C 7000+0x14

AUX_ADI

SET03[1:0]

0x400C B000+0x10

AUX_ADI

SET03[3:2]

0x400C B000+0x12

AUX_ADI

SET47[1:0]

0x400C B000+0x14

AUX_ADI

SET47[3:2]

0x400C B000+0x16

AUX_ADI

SET811[1:0]

0x400C B000+0x18

AUX_ADI

SET811[3:2]

0x400C B000+0x1A

AUX_ADI

SET1215[1:0]

0x400C B000+0x1C

AUX_ADI

SET1215[3:2]

0x400C B000+0x1E

AUX_ADI

CLR03[1:0]

0x400C B000+0x20

AUX_ADI

CLR03[3:2]

0x400C B000+0x22

AUX_ADI

CLR47[1:0]

0x400C B000+0x24

AUX_ADI

CLR47[3:2]

0x400C B000+0x26

AUX_ADI

CLR811[1:0]

0x400C B000+0x28

AUX_ADI

CLR811[3:2]

0x400C B000+0x2A

AUX_ADI

CLR1215[1:0]

0x400C B000+0x2C

AUX_ADI

CLR1215[3:2]

0x400C B000+0x2E

17.3 I/O Mapping
Up to 16 package-dependent I/Os can be routed to the AUX_PD I/O controller by configuring the MCU I/O
controller, which allows the sensor controller to directly control I/Os independently of the MCU and the
MCU power modes used.
For more details on the mapping between AUX I/Os and digital I/Os, see Chapter 11.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1305

Modules

www.ti.com

17.4 Modules
17.4.1 Sensor Controller
17.4.1.1 Introduction
The sensor controller module is a proprietary, lightweight CPU optimized for low power. Some
architectural highlights include the following:
• Comprehensive 2-operand load and store RISC-style instruction set with high code density
• All instructions consist of one 16-bit opcode
• Eight general-purpose registers of configurable width (up to 16 bits)
• 8-bit immediate instructions embedded in opcode, extendable to 16 bits using a prefix instruction
• Powerful memory-addressing modes
• Efficient manipulation of single bits in I/O space
• Dedicated support for efficient handling of external events
• Vectorized reset and wake-up events allow direct branch to handler address in the vector table
• Multiple power-down features, including clock-stop when waiting for external events and wakeup
• Low-power implementation with explicit power gating
• 2-clock execution for all instructions (3-clock for prefixed instructions)
17.4.1.2 Registers
The sensor controller has eight 16-bit general-purpose registers, R0 to R7. The registers are used as
operands in all data operations, and also for memory and I/O addressing. All integer registers can be used
for any operation, except for a few instructions that require dedicated use of the integer registers R0 or R1
only. The size of a register is known as a word, and all operations operate on entire words; there are no
such concepts as byte, halfwords, and so forth.
Dedicated flag registers implement the traditional zero (Z), negative (N), carry (C), and overflow (V) status
indications. A dedicated loop-count and loop-address register support highly efficient looping instructions.
The program counter (PC) is used to address the instruction memory and the CPU has a built-in 3-level
stack to store the PC during subroutine calls.
Most of the sensor controller registers are memory-mapped and are available for the system CPU to read
or write. These are found in the AUX_SCE:FETCHSTAT and the AUX_SCE:CPUSTAT registers.
17.4.1.3 Interfaces
The sensor controller has the following interfaces:
• Instruction interface towards AUX_RAM
• Data interface towards AUX_RAM
• I/O interface towards the peripheral bus
• Event interface towards the event control module
• Power management interface towards the AUX wake-up controller
The data, I/O, and instruction interfaces are all 16-bit interfaces. The data and instruction interfaces are
time-interleaved, so both can access the AUX_RAM without affecting each other. The CPU automatically
selects the interface based on the instruction being used.
17.4.1.4 Events, Sleep, and Clock Management
The sensor controller has eight events connected to its event inputs, that are used with the wev0 and
wev1 instructions (wait for the event to be 0 or 1). In addition, before executing the sleep instruction, it is
possible to configure four additional events that can wake up the sensor controller again.
These events are used to control program flow upon wakeup and to save power.
1306

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Modules

www.ti.com

17.4.1.4.1 wev1, wev0, and sleep Instructions
The wev1, wev0, and sleep instructions take a parameter that is an event number (event 0 to 7). When
the instruction is executed, the clock stops until the selected event line reaches 0 for a wev0 instruction or
1 for a wev1 instruction. The events are described in Section 17.4.2.1 and Section 17.4.2.1.2.
The sleep instruction stops the clock and also triggers the AUX power domain to go into a low-power
mode if AUX is set up to do so. For more details, see Section 17.5.
The sensor controller continues execution from one of its four input wake-up vectors in the
AUX_EVCTL:VECCFG0 and the AUX_EVCTL:VECCFG1 registers, which are prioritized from 0 (highest)
to 3 (lowest).
17.4.1.5 Instruction Set
The sensor controller instruction set is compact, powerful, and highly regular. The sensor controller is
based on the traditional RISC concept of having all operands in the registers, or in an immediate field
embedded directly in the instruction opcode.
Data memory can only be accessed using load and store operations, while I/O ports can be accessed
using input and output instructions as well as special bit-manipulation instructions.
For dyadic operations, the destination register appears to the left in the mnemonic except for memory and
I/O operations, where the memory and port address is always the right operand.
The following sections describes all instructions. Each table shows the instruction, the mnemonic, an
informal and a formal description of the operation performed, and how the flags zero (Z), negative (N),
carry (C), and overflow (V) are updated. The operation description is described as right-associative.
17.4.1.5.1 Memory Access
The sensor controller load and store (ld and st) instructions allow reading and writing data from or to the
AUX_RAM.
Load and store instructions transfer data between an integer register and a location in the data memory,
the address of which is determined by the current addressing mode.
Table 17-3 lists the load and store instructions.
Table 17-3. Load and Store Instructions (1)
Syntax

Description

Operation

ld Rd,addr

Load direct

Rd = mem[addr]

–

ld Rd,(Rs)

Load indirect

Rd = mem[Rs]

–

ld Rd,(Rs)++

Load indirect, postincrement

Rd = mem[Rs], Rs++

–

ld Rd,(Rs+R0)

Load indexed

Rd = mem[Rs+R0]

–

st Rd,addr

Store direct

mem[addr] = Rd

–

st Rd,(Rs)

Store indirect

mem[Rs] = Rd

–

st Rd,(Rs)++

Store indirect, postincrement

mem[Rs] = Rd, Rs++

–

st Rd,(Rs+r0)

Store indexed

mem[Rs+r0] = Rd

–

(1)

Flags: Zero (Z), Negative (N), Carry (C), and Overflow (V)

For instructions using direct-memory addressing, a 10-bit address is embedded in the instruction word,
supporting direct access to 1K memory words in the range 0 to 1023. Using the prefix instruction, the
direct-memory address can be extended to 16-bit, allowing direct access to 64K memory words. 16-bit
addressing of memory is also possible using indirect or indexed addressing.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1307

Modules

www.ti.com

17.4.1.5.2 I/O Access
For the sensor controller to access the other peripherals in AUX_PD (address range 0x400C 0000 to
0x400C FFFF), it must use the input and output instructions (in and out), using only the 16 lowest bits of
the 32-bit address.
Input and output instructions transfer data between an integer register and a peripheral register, the
address of which is determined by the current addressing mode.
Table 17-4 lists the input and output instructions available.
Table 17-4. Input and Output Instructions (1)
Syntax

Description

Operation

in Rd,[#addr]

Input direct

Rd = reg[addr]

–

in Rd,(Rs)

Input indirect

Rd = reg[Rs]

–

out Rd,[#addr]

Output direct

reg[addr] = Rd

–

out Rd,(Rs)

Output indirect

reg[rs] = Rd

–

(1)

Flags: Zero (Z), Negative (N), Carry (C), and Overflow (V)

For instructions using direct peripheral register addressing, an 8-bit address is embedded in the instruction
supporting direct access to 256 I/O ports in the range 0 to 255. Using the prefix instruction, the direct I/O
address can be extended to 16. 16-bit addressing of I/O is also possible using indirect addressing.
17.4.1.5.3 I/O Bit Access
In addition to reading and writing I/O ports using the input and output instructions, individual bits in the I/O
ports can be directly set, cleared, and tested using single instructions. This allows very fast and codeefficient implementation of common bit-manipulation functions without requiring the use of internal
registers.
Table 17-5 lists the input and output instructions available.
Table 17-5. Input and Output Instructions (1)
Syntax

Description

Operation

iobclr #imm,[#addr]

I/O Bit Clear direct

reg[addr] &= ~2^imm

–

iobset #imm,[#addr]

I/O Bit Set direct

reg[addr] |= 2^imm

–

iobtst #imm,[#addr]

I/O Bit Test direct

reg[addr] & 2^imm

–

(1)

Flags: Zero (Z), Negative (N), Carry (C), and Overflow (V)

The clear and set instructions first perform an input operation from the addressed register, then modify the
selected bit only and output the resulting new value to the same register.
Note that it is only possible to select bits 0 to 7 in a register using the 3-bit immediate value encoded in
the instructions.
Because the instructions use only direct register addressing, an 8-bit address is embedded in the
instruction supporting direct access to 256 registers in the range 0 to 255. Using the prefix instruction, the
direct register address can be extended to 16-bit.

1308

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Modules

www.ti.com

17.4.1.5.4 Arithmetic and Logical Operations
The arithmetic and logical operations operate on a destination operand in an integer register, while the
source can be either another integer register, or an 8-bit immediate operand.
Table 17-6 lists the arithmetic and logical instructions.
Table 17-6. Arithmetic and Logical Instructions (1)
Syntax

Description

Operation

add Rd,#simm

Add immediate

Rd += simm

cmp Rd,#simm

Compare immediate

Rd – simm

and Rd,#imm

AND immediate

Rd &= imm

or Rd,#imm

OR immediate

Rd |= imm

xor Rd,#imm

XOR immediate

Rd ^= imm

tst Rd,#imm

Test immediate

Rd & imm

add Rd,Rs

Add register

Rd += Rs

sub Rd,Rs

Subtract register

Rd –= Rs

subr Rd,Rs

Subtract reverse register

Rd = Rs – Rd

cmp Rd,Rs

Compare register

Rd – Rs

and Rd,Rs

AND register

Rd &= Rs

or Rd,Rs

OR register

Rd |= Rs

xor Rd,Rs

XOR register

Rd ^= Rs

tst Rd,Rs

Test register

Rd & Rs

0
x

Dyadic instructions

Monadic instructions
abs Rd

Absolute register

Rd = Rd > 0 ? Rd : –Rd

neg Rd

Negate register

Rd = –Rd

not Rd

Invert register

Rd = ~Rd

(1)

Flags: Zero (Z), Negative (N), Carry (C), and Overflow (V)

For instructions using an immediate operand, an 8-bit immediate is embedded in the instruction word.
Using the prefix-instruction, the immediate can be extended to a full 16-bit.
The arithmetic add and cmp instructions treat the 8-bit immediate as a signed quantity, in other words in
the range of –128 to +127, sign-extending it to full register width as appropriate. This allows, for example,
immediate subtractions to be performed using the add instruction.
The logical and, or, xor, and tst instructions treat the 8-bit immediate as an unsigned quantity, in other
words in the range of 0 to 255, zero-extending it to full register width as appropriate.
For all operations, the zero (Z) flag is set if the result is 0. The negative (N) flag is set equal to the most
significant bit of the result.
For arithmetic operations, the carry (C) flag is set according to a carry or borrow out of the most significant
bit of the result. Similarly, the overflow (V) flag is asserted if a arithmetic signed overflow occurs.
For logical operations, the carry (C) and overflow (V) flags are always both cleared.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1309

Modules

www.ti.com

17.4.1.5.5 Shift Operations
The shift operations operate on a destination operand in an integer register, while the source can be either
another integer register or a 3-bit immediate operand.
Table 17-7 lists the shift instructions.
Table 17-7. Shift Instructions (1)
Syntax

Description

Operation

lsl Rd,Rs

Logical shift left
register

Rd <<= Rs

lsr Rd,Rs

Logical shift right
register

Rd >>= Rs

asr Rd,Rs

Arithmetic shift right
register

Rd >>= Rs, preserving sign

lsl Rd,#imm

Logical shift left
immediate

Rd <<= imm

lsr Rd,#imm

Logical shift right
immediate

Rd >>= imm

asr Rd,#imm

Arithmetic shift right
immediate

Rd >>= imm, preserving
sign

(1)

Flags: Zero (Z), Negative (N), Carry (C), and Overflow (V)

For instructions using an immediate operand, a 3-bit immediate is embedded in the instruction word,
allowing an immediate shift value in the range of 1–8 to be encoded.
NOTE: Due to restrictions in the built-in barrel shifter—to save area and power—shifts can only be in
the range 0 to 15 positions, even when using the register version of the instructions.

For all operations, the zero (Z) flag is set if the result is 0. The negative (N) flag is set equal to the most
significant bit of the result. The carry (C) flag is set according to the last bit shifted out, whether through
the most significant or the least significant bit. The overflow (V) flag is always cleared.
17.4.1.5.6 Flow Control
The sensor controller has support for several powerful flow-control instructions, leading to efficient
execution of control flows.
17.4.1.5.6.1 Nonloop Flow Control
Table 17-8 lists all the nonloop flow control instructions.
Table 17-8. Nonloop Flow Control Instructions (1)
Syntax

Description

Operation

jmp addr

Jump direct

pc = addr

–

jsr addr

Jump subroutine
direct

push(stack, pc+1),
pc = addr

–

jmp (rR)

Jump indirect

pc = R0

–

jsr (R0)

Jump subroutine
indirect

push(stack, pc+1),
pc = R0

–

rts

Return subroutine

pc = pop(stack)

–

b rel

Branch relative if
condition met

if (cc) pc+1+rel

–

bra rel

Branch relative

pc+1+rel

–

bev0 #ev, rel

Branch if event 0

if (!events[ev]) pc+1+rel

–

bev1 #ev, rel

Branch if event 1

if (events[ev]) pc+1+rel

–

(1)

1310

Flags: Zero (Z), Negative (N), Carry (C), and Overflow (V)

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Modules

www.ti.com

For instructions using direct memory addressing, a 10-bit address is embedded in the instruction word,
supporting direct access to 1K memory instructions in the range 0 to 1023. Using the prefix instruction, the
direct memory address can be extended to 16-bit, allowing direct access to 64K memory instructions.
16-bit addressing is also possible using one of the indirect or the indexed addressing modes.
The b disp instructions perform conditional branching depending on the condition code flags as listed
in Table 17-9.
Table 17-9. Conditional Branching
Syntax

Description

Condition

gtu

Greater than, unsigned

!C & !Z

geu / iob0

Greater or equal, unsigned / Tested
register bit = 0

eq / z

Equal / Zero

novf

Not overflow

pos

Positive

ges

Greater or equal, signed

(N & V) | (!N & !V)

gts

Greater than, signed

( (N & V) | (!N & !V) ) & !Z

leu

Less or Equal, unsigned

C|Z

ltu / iob1

Less than, unsigned / Tested I/O bit = 1

neq / nz

Not Equal / Not Zero

ovf

Overflow

neg

Negative

lts

Less than, signed

(N & !V) | (!N & V)

les

Less or equal, signed

(N & !V) | (!N & V) | Z

When the condition tested is true, the next instruction is fetched from instruction memory at a location
equal to the sum of address of the instruction following the branch instruction, and an 8-bit signed
displacement in the range –128 to +127 embedded in the instruction word itself. When the condition
tested is false, instruction fetching continues sequentially. In addition to the above mentioned conditional
branches, an unconditional relative branch bra rel also exists.
The branch-event instructions bev0 and bev1 perform conditional branching, depending on event inputs
provided directly to the sensor controller from its event input. These are the same events as for the wev0
and wev1 instructions, and are described in Section 17.4.2.1.2.
This branching allows efficient control processing based on external events. The instruction word embeds
a 3-bit event ID in the instruction word, directly supporting 8 external events, and more can be selected
using the prefix instruction.
Each event can be tested for being deasserted (0) or asserted (1). When the selected event input has the
expected value, the address of the next instruction to execute is determined using an 8-bit signed
displacement in the instruction word, as for the b disp instructions. When the selected event input
does not have the expected value, instruction fetching continues sequentially.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1311

Modules

www.ti.com

17.4.1.5.6.2 Loop Flow Control
The loop instructions constitute a special group of flow-control instructions that allow iterative loops to be
efficiently coded and executed. Table 17-10 lists the instructions.
Table 17-10. Loop Flow Instructions (1)
Mnemonic

Description

Operation

loop R1,rel

Loop register (2)

loopcount = R1,
loopstart = pc+1,
loopend = pc+rel

–

loop #n,rel

Loop
immediate (2)

loopcount = n,
loopstart = pc+1,
loopend = pc+rel

–

(1)
(2)

Flags: Zero (Z), Negative (N), Carry (C), and Overflow (V)
The Sensor Controller Studio assembler offsets the end-of-loop label, so it can be placed after the last instruction of the loop.

A loop instruction is executed just before the first instruction of a loop, and causes the following:
• The address of the following instruction—the first instruction of the loop itself—is stored in an internal
register loopstart.
• The address of the instruction following the last instruction of the actual loop is determined using an 8bit, signed displacement in the instruction word, as for the b disp instructions. The resulting
address is stored in the internal register loopend.
• The number of loop iterations, as determined by either the content of the R1 register or a 3-bit
immediate in the instruction word, is stored in an internal register loopcount.
• The loop-control logic is armed.
Instruction execution continues unaffected until the address of the next instruction to be executed matches
the address stored in loopend. When this happens, loopcount is decremented, and if nonzero, a branch to
the address in loopstart is executed. If loopcount is 0 after being decremented, the loop-control logic is
disarmed, and instruction fetching continues sequentially.
Because there is only one set of the loopstart, loopend, and loopcount registers, and these registers are
not readable or writable from other instructions, loops using the loop instructions cannot be nested. The
loop instructions are intended for use in the innermost loop only.
The loop immediate instructions provide direct support for seven commonly used iteration counts of 2, 4,
8, 16, 32, 64, and 128 through encoding of a 3-bit field embedded in the instruction word, thus not
requiring the use of register R1.

1312

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Modules

www.ti.com

17.4.1.5.7 Events, Sleep, and Power Management
To support low-power operation, the sensor controller supports a suspend mode where instruction
execution is halted, internal state is frozen, and the clock is stopped completely under control of external
events.
Table 17-11 lists the instructions that provide additional power management features.
Table 17-11. Power Management Instructions (1)
Syntax

Description

Operation

wev0 #ev

Wait event 0

Stop clock until events[ev] == 0

–

wev1 #ev

Wait event 1

Stop clock until events[ev] == 1

–

sleep

Stop clock until wakeup,
then pc = 2*vector

–

sleep
(1)

Flags: Zero (Z), Negative (N), Carry (C), and Overflow (V)

When a wev0 or wev1 instruction is executed, the sensor controller stops the clock until the selected event
is deasserted (0) or asserted (1), respectively. When the selected condition is satisfied, the clock is reenabled and instruction execution continues sequentially.
The wev0 and wev1 instructions use the same event inputs to the sensor controller as for the instructions
bev0 and bev1. They are described in Section 17.4.2.1.2, Sensor Controller Events.
The instructions embed a 3-bit event ID in the instruction word, directly supporting eight external events.
More can be selected using the prefix instruction.
The sleep instruction also stops the clock until a dedicated wake-up event is asserted. When the wake-up
event is asserted to the configured polarity (high or low), the clock starts again, and program execution
continues at an address corresponding to the value on a vector input to the sensor controller, as shown in
Table 17-12. The events have priority ordered from event vector 0 (highest) to event vector 3 (lowest).
Address 0 is also used as the reset vector.
Table 17-12. Vector Inputs
Vector

Address (Relative to AUX RAM)

0x0000

0x0002

0x0004

0x0006

The vector interrupts allow the sensor controller to stay in power down. When a wake-up event occurs, the
sensor controller will start executing code from the corresponding address given in Table 17-12.
If the sensor controller is running, it is not affected by new event vectors being asserted until the sleep
instruction is executed again. The events used with the sleep instruction are found in Section 17.4.2.1.2.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1313

Modules

www.ti.com

17.4.1.5.8 Miscellaneous Instructions
A few instructions fall outside of the previously described instruction groups. These instructions are shown
in Table 17-13 and described in this section.
Table 17-13. Miscellaneous Instructions (1)
Syntax

Description

Operation

ld Rd,#simm

Load immediate

Rd = simm

–

ld Rd,Rs

Load register

Rd = rs

–

pfix #imm

Prefix immediate

pfix = imm

–

(1)

Flags: Zero (Z), Negative (N), Carry (C), and Overflow (V)

The load immediate instruction embeds a 10-bit signed immediate in the instruction word, allowing an
immediate in the range –512 to +511 to be loaded directly into a register.
The load register instruction copies a source register to a destination register. The nop instruction is
encoded as ld R7,R7.
The prefix instruction embeds an 8-bit, unsigned immediate in the instruction word that is loaded into a
hidden prefix register. Upon execution of the next instruction with an immediate or direct address operand,
the prefix register is effectively providing bit 15–8 of the source operand. Once used, the prefix register is
disabled and not used again until following the execution of a new prefix instruction.
Using prefixed instructions have the following two implications:
• The two uppermost bits, 9 and 8, of a 10-bit immediate or direct address embedded in an instruction
are ignored, as they are replaced by bits from the prefix register.
• No sign extension of an embedded immediate is performed for instructions that would normally do so,
as the uppermost bits are provided by the prefix register.
17.4.1.5.9 Reset
Following reset, execution starts at an address corresponding to the value of the same vector input as
used for the sleep instruction. This execution enables a usage model where the sensor controller is
completely disabled (powered down), and once activated, execution starts directly at an address of a
dedicated handler corresponding to the source that caused the sensor controller to be activated as
described in Section 17.4.1.5.7.
Restart functionality is also provided by asserting AUX_SCE:CTL.RESTART, which immediately disrupts
the instruction flow, causing execution to resume at the handler address selected by the vector input.
The restart functionality does not clear internal registers and flags. Reset does disable an active loop or
prefix.
17.4.1.5.10 Limitations
Due to internal pipelining and minimized register bypass logic, the instructions using R0 as a dedicated
register require special caution.
R0 must not be loaded from memory or register by an instruction immediately preceding any instruction
using R0 as a dedicated register. The affected instructions are ld/st rd,(Rs+R0) and jmp/jsr (R0).
Not observing this rule causes the previous value of R0 to be used instead of the newly loaded one.
Loading an immediate or the result of any nonmemory I/O operation into R0 is perfectly valid and causes
the expected behavior.

1314

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Modules

www.ti.com

17.4.1.6 Sensor Controller Control and Status
Several sensor controller status and debug registers are found in the AUX_SCE registers. These registers
provide means for the MCU to control the sensor controller and observe its status:
• Hooks for development and debugging software on the sensor controller
• Observation of internal registers and flags in the sensor controller
• Support for starting, stopping, resetting, and single-stepping of the sensor controller
NOTE: The use of the AUX_SCE registers are only supported through drivers generated by the TIprovided Sensor Controller Studio.

17.4.1.6.1 Single-stepping and Debugging the Sensor Controller
To do single-stepping, first suspend the sensor controller by setting the AUX_SCE:CTL.SUSPEND
register. Single-stepping is done by writing 1 to the AUX_SCE:CTL.SINGLE_STEP register. One
instruction is executed per write. Normal program execution is done by clearing the
AUX_SCE:CTL.SUSPEND register.
Full system real-time operation can be debugged by setting the AUX_SCE:CTL.DBG_FREEZE_EN bit.
This ensures that the sensor controller and AUX timers are stopped when a debugger halts the system
CPU (configured by default to do so in the MCU event fabric).
Because the clocks in the MCU domain are asynchronous to the AUX domain, multiprocessor debugging
is not perfectly real-time, but can be useful in many cases.
17.4.1.7 Running a Program
To execute a program on the sensor controller, the program image must first be uploaded to the AUX
RAM by the system CPU or DMA. The sensor controller is halted from reset, and does not receive any
clock.
There are two ways to have the CPU receive a clock and start executing its code:
• Write to the AON_WUC:AUXCTL.SCE_RUN_EN register
• Write to the AUX_SCE:CTL.CLK_EN register
Using the AON_WUC:AUXCTL.SCE_RUN_EN register bit is necessary if AUX_PD is being powered
down or up by the sensor controller, and the user wants to have the sensor controller restart without
interaction from the system CPU. TI recommends this way of using the sensor controller.
The AON_WUC:AUXCTL.SCE_RUN_EN register bit survives until the device enters shutdown, or there is
a system-wide reset.
The AUX_SCE registers are reset whenever AUX is reset or power-cycled. Otherwise, it has the same
functionality as the AON_WUC:AUXCTL.SCE_RUN_EN register bit.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1315

Modules

www.ti.com

17.4.1.7.1 Use Case – Periodic Wakeup
A typical use case is to wake up both AUX _PD and the sensor controller periodically, to execute a task
such as SPI or ADC sampling.
This wake up can be achieved, for example, by enabling the RTC channel 2 in continuous-compare mode
and setting it as a wake-up event vector in the AON_EVENT:AUXWUSEL register. When an RTC
compare event occurs on channel 2, this causes AUX to be powered on in active mode.
However, the sensor controller does not start to execute code until one of the four wake-up event vectors
(described in Section 17.4.2.1.2) are triggered, so RTC channel 2 must also be setup as a wake-up vector
to the sensor controller in the AUX_EVCTL:VECCFG0 and the AUX_EVCTL:VECCFG1 registers.
During execution, the sensor controller event vector flag must be cleared to prevent it from restarting
again immediately at the same vector after a sleep instruction is issued.
When the task is finished executing and AUX_PD must power down, the sensor controller must make a
power-down request to the AON wake-up controller, and then the AUX_PD must be disconnected from
the MCU system bus. This process is described in Section 17.5.
The wake-up event must be cleared before powering down to stop AUX from immediately powering on
again. The RTC has a dedicated interface for clearing channel 2, by writing to the
AUX_WUC:WUEVCLR.AON_RTC_CH2 register.
The AUX_PD must not request to power down until a read of the corresponding wake-up event flag
AUX_WUC:WUEVFLAGS register reads 0.

17.4.2 GPIO Control
If the sensor controller is controlling GPIOs instead of the MCU domain, the I/O latches must be opened,
or the I/Os are in an unknown state. Opening the latches is done through the AUX_WUC:AUXIOLATCH
register.
17.4.2.1 Event Control
The AUX domain has an event bus where event outputs from many modules are distributed throughout
the module.
These AUX domain events can trigger a number of actions, both internally in the AUX domain and in the
AON and MCU domains, where events can be further routed through the event fabric (see Section 4.3).
Examples of these kinds of interactions are the following:
• Trigger a RTC capture when a timer has reached its target
• Wake up the MCU domain when an ADC conversion is done
• Trigger a DMA transfer when a comparator changes value
All events triggering actions internally in AUX are described in detail in the corresponding module chapter.
There are also events used to wake up AUX, which are described in Section 17.5.3 and Section 17.5.
17.4.2.1.1 Software-Defined Events
There are three software-defined events in AUX that can trigger actions in the AON or MCU domain.
These can, for example, be set by the sensor controller to wake up the MCU domain and trigger an
interrupt in the system CPU. The system CPU can also write these events, which allows for a
communication and synchronization protocol between the sensor controller and the system CPU.
The software-defined events are set by writing to the AUX_EVCTL:SWEVSET register and are cleared by
writing to AUX_EVCTL:EVTOAONFLAGSCLR register.
All events are connected to the AON and MCU event fabric, and software event 0 and event 1 are directly
routed to the system CPU.

1316

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Modules

www.ti.com

17.4.2.1.2 Sensor Controller Events
17.4.2.1.2.1 Sleep Instruction and Reset Events
The sensor controller has four edge-triggered event vector inputs that are used to wake from the sleep
instruction and trigger program execution from the corresponding reset vector.
These event vectors are defined in the AUX_EVCTL:VECCFG0 and the AUX_EVCTL:VECCFG1
registers.
Each event vector can have separate control of enable control, trigger source, and edge polarity.
During execution of a vector, the flag must be cleared by writing a 1 to the corresponding bit in the
AUX_EVCTL:VECFLAGSCLR register to avoid having the next sleep instruction wake up the sensor
controller again immediately.
17.4.2.1.2.2 wev0 and wev1 Events
Table 17-14 lists some events from the event bus that are connected directly to the sensor controller.
These events are to be used with the wev0 and wev1 instructions.
Table 17-14. Events Used With Sensor Controller WEV Instructions
Name

Number

Description

AON_RTC_CH2

RTC Channel 2 event

COMPA

Comparator A event

COMPB

Comparator B event

TDC_DONE

TDC conversion done or timed out

TIMER0

Timer 0 reached its target count

SMPH_AUTOTAKE_DONE

A given semaphore has been released

ADC_DONE

ADC conversion is done

PROG

Programmable event

Event 7 is programmable and is configured in the AUX_EVCTL:SCEWEVSEL register.
17.4.2.1.3 Events to AON Event Fabric
Several edge-triggered events in AUX are connected to the AON event fabric, where they can be routed to
modules to trigger an action.
Examples of such actions are waking up the MCU voltage domain or doing an RTC capture. In addition,
these events can be routed further from the AON event fabric to the MCU event fabric as AON
programmable events (for more information, see Section 4.3).
Table 17-15 lists the events routed to the AON event fabric.
Table 17-15. Events Routed to the AON Event Fabric
Name

Number

Description

SWEV0

Software defined event 0

SWEV1

Software defined event 1

SWEV2

Software defined event 2

COMPA

Comparator A event

COMPB

Comparator B event

ADC_DONE

ADC conversion is done

TDC_DONE

TDC conversion done or timed out

TIMER0

Timer 0 reached its target count

TIMER1

Timer 1 reached its target count

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1317

Modules

www.ti.com

Check the status and configure the events going to the AON event fabric with the following:
• Configure the polarity of events with the AUX_EVCTL:EVTOAONPOL register
• Read the status of events with the AUX_EVCTL:EVTOAONFLAGS register
• Clear the events with the AUX_EVCTL:EVTOAONFLAGSCLR register
17.4.2.1.4 Events to MCU
Several events are connected to the MCU event fabric and the system CPU, which can generate actions
such as DMA transfers or system CPU interrupts.
Table 17-16 lists the events connected directly to the MCU event fabric.
Table 17-16. MCU Event Fabric Events
Name

Number

Description

AON_WU_EV

AON wake-up event (1)

COMPA

Comparator A event

COMPB

Comparator B event

TDC_DONE

TDC conversion done or timed out

TIMER0

Timer 0 reached its target count

TIMER1

Timer 1 reached its target count

SMPH_AUTOTAKE_DONE

A given semaphore has been released

ADC_DONE

ADC conversion is done

ADC_FIFO_ALMOST_FULL

ADC FIFO almost full

ADC_IRQ

ADC IRQ (2)

(1)
(2)

Logical OR of the AUX wake-up events in the AUX_WUC:WUEVFLAGS register
ADC new sample available, FIFO underflow or overflow. If DMA is used: ADC DMA done, FIFO underflow or overflow.

Check the status and configure the events output to the MCU event fabric with the following:
• Configure the polarity of events with the AUX_EVCTL:EVTOMCUPOL register
• Read the event status and clear the events with the AUX_EVCTL:EVTOMCUFLAGS register
There is also a programmable, combined event to the MCU event fabric generated from a logical OR of all
events selected in an event mask, which is configured in the AUX_EVCTL:COMBEVTOMCUMASK
register.

17.4.3 AUX Timers
The AUX power domain has two compare timers available, one 16 bit and one 8 bit. The timers can use a
number of inputs as their tick source and can be clocked on either the AUX power domain system clock or
an external event.
To set up a timer, the tick source must first be configured in the AUX_TIMER:TnCFG.MODE register.
Setting the mode to CLK makes the timer tick at the AUX system clock. Configuring it in tick mode makes
the timer use the event input configured in the TICK_SRC field as its tick, which makes it possible to have
it tick on events such as AUX I/O events, MCU events, comparator events, and others.
Prescaling is also available by configuring the 4-bit register field AUX_TIMER:TXCFG.PRE, which divides
the selected tick source by 2PRE; thus, giving a prescaling range from 1 to 65536.
When a timer hits the compare value configured in the AUX_TIMER:TXTARGET.VALUE register, the
corresponding timer event is set. The timer either stops or restarts again, depending on the configuration
in the AUX_TIMER:TXCFG:RELOAD register. The timer starts running when asserting the
AUX_TIMER:TXCTL.EN register.

1318

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Modules

www.ti.com

17.4.4 Time-to-Digital Converter
The high-precision time-to-digital converter (TDC) peripheral measures time between two individually
selected start and stop events with high accuracy. The TDC counts on both clock edges, running
effectively up to a speed of 96 MHz. The TDC is controlled by a state machine running on the AUX_PD
system clock.
Typical use cases for TDC are as part of a system doing capacitive sensing, clock calibration, or pulse
counting.
17.4.4.1 Configuration
The TDC must be in idle mode to be configured; any register writes are ignored when not in idle mode.
The TDC starts up in idle and returns to idle when a measurement is done or a measurement is aborted.
17.4.4.2 Clocks
Before accessing the TDC module, the clock to the TDC interface must be enabled by writing to the
AUX_WUC:MODCLKEN0.TDC register.
The high-speed clock used to count must also be configured in the
DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL register. Table 17-17 lists the available clock sources.
Table 17-17. Available Clock Sources
Clock Source

Description

RCOSC_HF

48-MHz RCOSC

RCOSC_HF_D24M

24 MHz derived from RCOSC_HF

XOSC_HF_D24M

24 MHz derived from XOSC_HF

For information on writing to the oscillator interface, see Section 17.4.6.
If the TDC is used to measure the frequency of another on-chip frequency oscillator, the correct lowfrequency source must be configured in the DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL register.
Table 17-18 lists the available reference clock sources.
Table 17-18. Available Reference Clock Sources
Clock Source

Description

RCOSC_HF_DLF

Clock derived from 48-MHz RCOSC (31.25 kHz)

XOSC_HF_DLF

Clock derived from 24-MHz XOSC (31.25 kHz)

RCOSC_LF

Clock from RCOSC_LF (32 kHz)

XOSC_LF

Clock from XOSC_LF (32.768 kHz)

Before using the TDC, the above-configured clock sources must be enabled by writing to the
AUX_WUC:TDCCLKCTL.REQ and the AUX_WUC:REFCLKCTL.REQ register. The corresponding ACK
bit is set when the clock source has started and is ready to use.
NOTE: If there are any high-speed clocks enabled for the TDC, the system is not able to go to
standby mode because the oscillator is still requesting resources from the supply system.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1319

Modules

www.ti.com

17.4.4.2.1 Start and Stop Source
A start and stop source must be configured for the TDC before doing a measurement by configuring the
AUX_TDC:TRIGSRC register. It is also possible to configure the polarity of the start and stop sources,
which lets the TDC start or stop counting on the programmed edge.
If more than one period of a signal is to be measured, the number of stop events to ignore before stopping
the measurement must be configured in the AUX_TDC:TRIGCNTLOAD register, and the stop counter
must be enabled in the AUX_TDC:TRIGCNTCFG register.
17.4.4.2.2 Saturation
The TDC can be configured in the AUX_TDC:SATCFG register to saturate and stop the measurement if
the counter values are larger than a configurable saturation limit. This process can be useful when an
unknown signal is input as start or stop source to limit the maximum time the TDC is counting. If the TDC
saturates, both the SAT and DONE status bits are set in the AUX_TDC:STAT register.
17.4.4.2.3 Prescaler
If the input signal measured by the TDC has a high frequency (more than 1/10 of AUX clock frequency),
the TDC state machine may lose pulses. In this case, an optional prescaler can be used at the input of the
TDC.
The prescaler can be connected as a start or stop event (just like any other event) and then it divides the
input signal by 16 or 64, which is configurable in the AUX_TDC:PRECTL.RATIO register.
Any event in the AUX_TDC:PRECTL.SRC bit field can be used as input.
The following limitations apply to using the prescaler:
• The prescaler must be set as both start and stop source for the TDC
• The TDC must only be started in synchronous mode
• Prescaler input frequency must be lower than 24 MHz
• When configuring the prescaler, it must first be put in reset mode by clearing the
AUX_TDC:PRECTL.RESET_N register bit, and the TDC must be in idle mode.
The TDC result does not automatically compensate for the prescaler ratio. This must be done in software
by multiplying with the prescaler ratio.
17.4.4.3 Performing a Measurement
Starting and stopping a measurement is done by writing to the AUX_TDC:CTL.CMD register.
In asynchronous mode, the start event must not arrive until seven AUX clock periods after the start bit is
written to. This mode is recommended for measurements in which software has control of the arrival time
of the start event.
For synchronous mode, the TDC start automatically synchronizes to the edge of the start signal. If the
start event is too close to the time when the start command is given, it is missed and the TDC does not
start until the next edge of the start signal. This mode is recommended for measuring periodic signals
such as clock inputs.
Once a measurement is done, the counter value can be read out from the AUX_TDC:RESULT register.

1320

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Modules

www.ti.com

17.4.5 Semaphores
The AUX power domain has eight hardware semaphores that can be used for synchronization between
the sensor controller and system CPU. These are taken by reading the AUX_SMPH:SMPHn.STAT
semaphore registers. Reading a 1 means the semaphore was taken while reading; reading a 0 means the
semaphore is already taken by another owner. A semaphore is released by writing 1 to the same register.
The semaphore module also has an auto-take functionality where the semaphore number is written to the
AUX_SMPH:AUTOTAKE.SMPH_ID register. Once the semaphore becomes available, it automatically
takes again and the SMPH_AUTOTAKE_DONE event is asserted. Software must wait until this event is
triggered before writing to the AUTOTAKE register again. Failing to do so might lead to permanently lost
semaphores because the owners might be unknown.
NOTE: TI provided drivers and frameworks use semaphore 0 to ensure unique access to the analog
(ADI) and oscillator (DDI) interface. Using semaphore 0 for other purposes might create
system conflicts

17.4.6 Oscillator Configuration Interface (DDI)
The DDI is a 32-bit interface used to control the oscillators in the device. It is located within the AUX
power domain to allow both the system CPU and the sensor controller to configure the oscillators.
Section 6.5 provides details on what clocks can be configured through the oscillator interface.

17.4.7 Analog MUX
Between the analog I/Os and the modules connected to them, there are a set of muxes used to connect
various inputs to the module. These muxes are configured through the AUX ADI.
Section 11.8 shows that these I/Os are mapped to the analog-capable sensor controller pins (AUX IO 0 to
7).
The muxes can connect peripherals to both analog I/Os and some internal signals. Table 17-19 shows the
supported connections.
Table 17-19. Supported Connections
Peripheral

Connects To

ADC / Comparator B + (shared input)

AUX IO 0 to 7, GND,VDDS, VDD/DECOUPL

Comparator B –

VDDS, VDD/DECOUPL,GND

Comparator A +

AUX IO 0 to 7

Comparator A –

AUX IO 0 to 7, GND, VDDS, VDD/DECOUPL

To avoid shorting signals together internally, TI provides ROM-based driverLib functions that ensure a
break-before-make switching of the internal muxes when connecting them to the analog peripherals.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1321

Modules

www.ti.com

17.4.8 ADC
17.4.8.1 Introduction
The ADC is a 12-bit general-purpose successive-approximation type (SAR) ADC that can sample up to
200 kS/s using up to eight different input channels with a number of start triggers. Figure 17-2 shows the
ADC block diagram.
The input stage consists of a switched-capacitor stage, where the input voltage is sampled and held
before the conversion is done.
The ADC can operate in both synchronous and asynchronous mode.
In synchronous mode, the start trigger starts the sampling for a programmable amount of time before the
conversion is performed to allow for high-impedance sources to be properly sampled.
For asynchronous mode, the ADC samples continuously then stops sampling when the start signal
triggers to perform a conversion. This mode allows jitter-free sampling for applications that require it, such
as audio sampling.
The ADC is production-trimmed and it is possible to compensate for ADC gain and offset errors in
software by reading the factory configuration page (see Section 9.2).

Gnd

Vref

Vin

Gnd

Vref

Vin

Gnd

Vref

Vin

Gnd

Vref

Vin

Gnd

Vref

Vin

Gnd

Vref

Vin

Figure 17-2. ADC Block Diagram

Switch Control

32C

ADC
Digital
Vbias

Data[11:0]

17.4.8.2 ADC Reference
The ADC supports two different internal references, one constant and one relative to VDDS.
The ADC automatically scales down the input signal to be within the reference range. It is possible to
disable the scaling, but this requires great care by the user to ensure the maximum ratings in the data
sheet are followed. With scaling enabled, the internal fixed reference looks like 4.3 V compared to the
actual input level. With scaling disabled, the reference is 1.44 V.
NOTE: With scaling disabled it is possible to cause permanent damage to the ADC with voltage
levels lower than VDDS. See the data sheet for detailed limits.

To save power in synchronous mode, the ADC reference can also be powered off during idle periods (if
the sampling period is long enough to turn it on again during sampling) by setting the
ADI_4_AUX:ADCREF0.REF_ON_IDLE register.
The ADC reference source is selected in the ADI_4_AUX:ADCREF0.SRC register and enabled in the
ADI_4_AUX:ADCREF0.EN register.

1322

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Modules

www.ti.com

17.4.8.3 Sample Mode and Sample Duration
Sampling mode is configured in the ADI_4_AUX:ADC0.SMPL_MODE register.
Synchronous sampling is done by starting a sampling when a trigger is received. The input is then
sampled for a period defined in the ADI_4_AUX:ADC0.SMPL_CYCLE_EXP register before a conversion is
performed.
Asynchronous mode is always sampling; it only stops sampling when the start trigger occurs to perform a
conversion.
17.4.8.4

Input Signal Scaling

Disabling input scaling is configured through the ADI_4_AUX:ADC1.SCALE_DIS register, and can be
used to increase the ADC step resolution for lower input voltages.
Use this setting with caution because even input voltages within the VDDS operating voltage can damage
the ADC permanently. Refer to the device data sheet for voltage limits.
17.4.8.5 ADC Enable
Enabling the ADC analog core is done by setting the ADI_4_AUX:ADC0.EN register bit, which enables the
internal bias module and comparator.
17.4.8.6 Digital Core
The SAR ADC has a digital core that is used to configure the ADC, perform measurements, and interface
the AUX registers for control and data.
After configuring the ADC registers in ADI_4_AUX, the ADC digital core can be enabled. Any changes to
the ADC core or reference configuration (except for the enable signals) requires the ADC digital core to be
reset again to take effect. This reset is done by clearing and then setting the reset signal in the
ADI_4_AUX:ADC0.RESET_N register.
17.4.8.7 ADC Core Clock
The ADC core uses a 24-MHz clock source derived from SCLK_HF, which must be enabled by setting the
AUX_WUC:ADCCLKCTL.REQ register. When the corresponding ACK bit in the same register is read as
high, the clock is enabled to the ADC.
For accurate low-jitter sampling in asynchronous mode, the software must ensure that SCLK_HF is
sourced from the 24-MHz XTAL before using the ADC.
NOTE: When this clock is enabled, the system cannot go into standby or shutdown mode because
the system still has a dependency on the SCLK_HF setting.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1323

Modules

www.ti.com

17.4.8.8 Sampling
The ADC can start sampling on events from a number of different sources in AUX and AON, I/O events on
the AUX IOs, and the general purpose timers in MCU (through the event fabric).
The source and start polarity is configured in the AUX_ANAIF:ADCCTL register. For software triggered
sampling, set the start source to an unused value and write to AUX_ANAIF:ADCTRIG register.
17.4.8.9 FIFO
The ADC FIFO is a 4-element large FIFO for storing the results of ADC conversions.
ADC samples can be read from the FIFO register, AUX_ANAIF:ADCFIFO. When a sample is read, it is
popped from the FIFO and can be stored by the user.
Statuses and errors in the FIFO are found in the AUX_ANAIF:ADCFIFOSTAT register.
To recover from an FIFO overflow or underflow condition, the FIFO must be flushed by writing the flush
command to AUX_ANAIF:ADCCTL.CMD and then enabling the ADC interface again.
NOTE: When debugging the software, showing the ADCFIFO register causes JTAG to read the
FIFO, which pops the sample from the FIFO, and consequently the software cannot read it.

17.4.8.10 Interrupts and Events
The ADC events found in event control are output to allow other modules to trigger on ADC events or to
interrupt the system CPU. These are edge-triggered and must be cleared by software.
17.4.8.11 DMA Usage
The ADC can be used together with DMA to allow data transfer from the ADC FIFO to any other memorymapped location without CPU involvement.
To configure the ADC to trigger a DMA transfer, the corresponding DMA channel #7 must be set up in the
µDMA module.
After configuring the µDMA, configuration of a DMA trigger for the ADC is done in the
AUX_EVCTL:DMACTL register.
The trigger of a DMA transfer can be done by two different FIFO events: ADC_ FIFO_NOT_EMPTY (1 or
more samples available) or ADC_FIFO_ALMOST_FULL (3/4 full).
The type of DMA request must also be configured (burst or single transfer). If using single transfers, the
µDMA must be set up to copy 1 sample, while a burst transfer must copy no more than 3 samples to avoid
underflow.
When using µDMA, the AUX_ADC_IRQ event is set when the DMA transfer is done to allow the system
CPU to be interrupted, which occurs for ADC DMA transfer done, ADC FIFO underflow, and ADC FIFO
overflow.

1324

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power Management

www.ti.com

17.4.8.12 Usage Example—Single Shot ADC Measurement
17.4.8.12.1 Enable Interface Clocks and ADC Clocks
Use the following steps to enable the interface clocks and the ADC clocks: AUX_WUC:MODCLKEN0.ANAIF
1. Enable the clock for the AUX analog interface with the AUX_WUC:MODCLKEN0.SOC register and for
the ADI interface with the AUX_WUC:MODCLKEN0.ADI register. AUX_WUC:MODCLKEN0.ADI4
2. Request clock for the ADC core; wait until the request is acknowledged in the
AUX_WUC:ADCCLKCTL register.
17.4.8.12.2 Configure the ADC Registers
Use the following steps to configure the ADC registers:
1. Connect the correct MUX to the ADC and set the I/O in analog mode (disable the input and output
buffer).
2. Set the ADC sampling mode with the ADI_4_AUX:ADC0.SMPL_MODE register.
3. Configure the sampling time for continuous mode with the ADI_4_AUX:ADC0.SMPL_CYCLE_EXP
register.
• The minimum must be 0x3 (2.7 µs) for complete internal signal settling.
4. Chose the internal reference source with the ADI_4_AUX:ADCREF0.SRC register.
5. Configure the power-saving mode of internal reference with the ADI_4_AUX:ADCREF0.REF_ON_IDLE
register.
6. Enable the ADC analog core with the ADI_4_AUX:ADC0.EN register, and reference the
AUX_ADI:ADCREF0.EN register.
7. Release the ADC core from reset with the ADI_4_AUX:ADC0.RESET_N register.
17.4.8.12.3 Sampling
Use the following steps to initiate sampling:
1. Set the start polarity to rising and set the start source to manual (for example, 0x9) with the
AUX_ANAIF:ADCCTL register.
2. Write to the start trigger register, AUX_ANAIF:ADCTRIG.
3. Wait until the FIFO is no longer empty on the AUX_ANAIF:ADCFIFOSTAT register, and read the
measurement from the FIFO AUX_ANAIF:ADCFIFO register.

17.5 Power Management
NOTE: Before reading this Power Management section, read Chapter 6.

System resources and power modes can be requested with registers in the AUX_WUC, and these
requests are generally independent from similar requests in the MCU voltage domain. By configuring the
AUX_WUC, both the sensor controller and the system CPU can request the following:
• AUX_PD power modes
• AUX clock source and frequency
• AUX peripheral clocks
To access a peripheral in AUX (other than for AUX_WUC and AUX_EVCTL), the clock must be enabled in
the AUX_WUC:MODCLKEN0 register or the AUX_WUC:MODCLKEN1 register. Failure to do so results in
an error when accessing the peripheral (for details, refer to Section 17.1.1).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1325

Power Management

www.ti.com

17.5.1 Start-Up
From system reset, the AUX power domain powers on and requests active-system mode. The domain is
consequently clocked by the HF system clock at 24 MHz, though all AUX peripherals except for
AUX_WUC and AUX_EVCTL are clock gated.

17.5.2 Power Mode Management
To save power when AUX_PD is not being used, the entire power domain can be put in low-power mode.
As both the AUX and MCU are capable of requesting system resources such as active and standby
modes, it is important to be aware that neither must request active mode if the desired system-mode state
is standby or shutdown.
To enable low-power consumption, the user must request the minimal amount of system resources
required to achieve a task. Thus, when there is no task running on the sensor controller requiring active
mode in AUX, it must request to be powered down.
NOTE: TI-RTOS forces AUX into active whenever the MCU system is in active mode to ensure fast
access to the oscillator interface in the AUX domain.

There are three power modes available for the AUX domain: active, power down, and power off.
17.5.2.1 Active Mode
Active mode is requested when there is no request set for power down or power off. When active system
mode is entered, the AUX clock source is derived from the high-speed system clock, which can be divided
down by configuring the AON_WUC:AUXCLK.SCLK_HF_DIV register.
The maximum frequency is 24 MHz, and the configuration of clock division must be done by the system
CPU.
When the AUX_PD is in active mode, the device is prevented from entering standby or shutdown power
modes because the AUX_PD is requesting system resources from the supply system.
17.5.2.2 Power Down
Power down is requested when AUX has been disconnected from the system BUS.
In power down mode, the AUX_PD is on and the sensor controller can still execute programs. The AUX
domain receives a clock defined in the AON_WUC:AUXCLK.PWR_DWN_SRC register.
To have the AUX enter power-down mode, a 4-phase handshake with the AON_WUC is necessary, using
the AUX_WUC register bank by completing the following sequence:
1. Write AUX_WUC:PWRDWNREQ = 1
2. Wait for AUX_WUC:PWRDWNACK = 1
3. Write AUX_WUC:PWRDWNREQ = 0
4. Wait until AUX_WUC:PWRDWNACK = 0
When the PWRDWNACK register goes low, the AUX starts receiving the power-down clock instead of the
active-mode clock.
By default, the entire AUX domain has full retention in the power-down mode. TI recommends using this
low-power mode to save execution time by not having to reconfigure AUX every time it is used.
If the entire CC26x0 and CC13x0 device must be put in a low-power mode, the AUX must first disconnect
from the MCU system bus before completing the power-down sequence. For more details, refer to
Section 17.5.4.

1326

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Power Management

www.ti.com

17.5.2.3 Power Off
The AUX domain can be fully powered off (power disconnected) from the domain to reduce the leakage
current from the domain. To fully power off the AUX domain, the system must first disconnect from the
MCU system bus (For more details, refer to Section 17.5.4).
To request the domain to be powered off, write AON_WUC:PWROFFREQ = 1.
Even if the entire domain is powered off, the contents of AUX SRAM are retained by default, which is
configurable in the AON_WUC:AUXCFG.SRAM_RET_EN register field.
NOTE:

Powering off the entire AUX domain is usually not needed because the extra current being
drawn compared to power down is minimal (just a few nA).

17.5.3 Wake-Up Events
The AON domain can generate the following wake-up events that set the AUX domain into active mode
again:
• Up to four events configured in the AON_EVENT:AUXWUSEL register
• A software-triggered event from AON triggered by writing to the AON_WUC:AUXCTL.SWEV register
• Setting AON_WUC:AUXCTL.AUX_FORCE_ON = 1
If code running on the system CPU accesses the AUX, the AON_WUC:AUXCTL.AUX_FORCE_ON
register bit must always be set (For more details, see Chapter 6.
NOTE: Any power-down request remaining from before the AUX was powered down takes effect
again when the wake-up source bits are cleared, which is done by clearing the event flag at
the source of the event.

The current status of the wake-up events can be read from the AUX_WUC:WUEVFLAGS register. The
event flags that can be read out are the following:
• AON_RTC channel 2
• Software event from AON
• Wake-up source programmed in the AON_EVENT:AUXWUSEL register (including RTC channel 2)
To clear an AUX wake-up source, the sensor controller or system CPU must clear it through writing to the
AUX_WUC:WUEVCLR register. A power-down request must not be done before the flag is read as 0.
RTC channel 2 and software events from AON have dedicated clear bits. Any wake-up I/O events on pins
routed to the AUX are cleared by writing to the AUX_WUC:WUEVCLR.AON_PROG_WU register.
A use case that requires special handling is when both an I/O and RTC channel 2 are used as AUX wakeup sources and event vectors for the sensor controller.
If the RTC event occurs while the sensor controller is handling a task triggered by an I/O event, the
AUX_WUC:WUEVFLAGS:AON_PROG_WU register flag does not go low when clearing the RTC event in
the I/O wake-up handler because the flag includes the RTC event. This can be overcome in software by
checking if the flag AUX_WUC:WUEVFLAGS:AON_RTC_CH2 is set, and running a sleep instruction to
restart at the RTC vector instead of waiting for the AON_WU_PROG bit to be cleared.
Other wake-up events programmed in the AON_EVENT:AUXWUSEL register must be cleared at the
source module in the AUX or by the system CPU.
NOTE:

Waking up the AUX domain does not make the sensor controller start running its program
again because this is dependent on the state of the sensor controller. Refer to
Section 17.4.1.7 and Section 17.4.8.10.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1327

Power Management

www.ti.com

17.5.4 MCU Bus Connection
The AUX can request disconnection from the MCU bus interface, which connects the MCU domain to the
AUX. This request is done through the AUX_WUC:MCUBUSCTL register. The sensor controller can poll
the AUX_WUC:MCUBUSSTAT register to poll the status of the connection to the system bus.
Because the system CPU cannot read these registers after the bus is disconnected, the CPU must use
the AON_WUC:PWRSTAT.AUX_PD_ON register field to check if the AUX is connected to the MCU
system bus.

17.6 Clock Management
17.6.1 System Clocks
Because AUX is a slave to the system CPU, the system clock for AUX is controlled by the system CPU
through the AON wake-up controller, AON_WUC:AUXCLK.
The clock configuration is tied to the current power mode.
17.6.1.1 Active Mode
In active mode, AUX runs on the high-frequency system clock (SCLK_HF) divided down by a factor
between 2 and 256, which is configured by writing to the AON_WUC:AUXCLK.SCLK_HF_DIV register.
AUX can override this setting and run with the low-frequency system clock as source instead. This
override is done by requesting active mode by doing a four-phase handshake with the AON wake-up
controller with the following sequence:
1.
2.
3.
4.

Set the AUX_WUC:CLKLFREQ.REQ register high.
Wait for the AUX_WUC:CLKLFACK.ACK register to go high.
Set the AUX_WUC:CLKLFREQ.REQ register low.
Wait for the AUX_WUC:CLKLFACK.ACK register to go low.

After this handshake, AUX is ensured to always use the low-frequency clock in active mode.
LF clock source is not recommended for normal use because the system CPU experiences very long wait
times to access modules in AUX_PD, such as the oscillators.
17.6.1.2 Power Down
When AUX is in power-down mode, the domain receives a power-down clock instead, which is configured
in the AON_WUC:AUXCLK.PWR_DWN_SRC register.
Table 17-20 lists the power-down options.
Table 17-20. Options for Power Down
Clock Source

Description

NONE

The AUX system receives no system clock. The sensor controller does not run and any accesses
to AUX from the system CPU return a bus fault. Any peripherals that can run on an asynchronous
clock (such as timers and the TDC) continue to run.

SCLK_LF

AUX runs on the low-frequency system clock (SCLK_LF). The sensor controller can run on this
clock as well as all peripherals. Any accesses to AUX from the system CPU take several
SCLK_LF clock periods before returning.

Access to the AUX domain from the system CPU while AUX is using a low-frequency clock is slow
because the system CPU stalls while waiting for a response from AUX. Therefore, the system CPU must
force AUX into active mode by asserting the AON_WUC:AUXCTL:AUX_FORCE_ON register, which
causes AUX to run at full speed and be connected to the MCU system. The AUX must not be accessed
from the MCU domain before the AON_WUC:PWRSTAT:AUX_PD_ON status register field has been
asserted.

1328

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Clock Management

www.ti.com

17.6.2 Sensor Controller Clock
The sensor controller always runs at the same clock as the AUX system.
When switching between power modes, any code running on the device has a nondeterministic run time
because the clock source changes. The nondeterministic run time can be avoided by not running code on
the sensor controller while switching power modes, or by requesting to always run on the low-frequency
clock when switching between power modes.
For more details, see the clock section in Section 17.5.2.1.

17.6.3 Peripheral Clocks
The AUX can request a number of clocks for the peripherals in the AUX domain.
Enabling clocks for most peripherals is done through the AUX_WUC:MODCLKEN0 register. After enabling
the clock for a peripheral, it is ready to be accessed immediately.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1329

AUX – Sensor Controller Registers

www.ti.com

17.7 AUX – Sensor Controller Registers
17.7.1 ADI_4_AUX Registers
Table 17-21 lists the memory-mapped registers for the ADI_4_AUX. All register offset addresses not listed
in Table 17-21 should be considered as reserved locations and the register contents should not be
modified.
Table 17-21. ADI_4_AUX Registers
Offset

1330

Acronym

MUX0

Internal

Section 17.7.1.1

MUX1

Internal

Section 17.7.1.2

MUX2

Internal

Section 17.7.1.3

MUX3

Internal

Section 17.7.1.4

ISRC

Current Source

Section 17.7.1.5

COMP

Comparator

Section 17.7.1.6

MUX4

Internal

Section 17.7.1.7

ADC0

ADC Control 0

Section 17.7.1.8

ADC1

ADC Control 1

Section 17.7.1.9

ADCREF0

ADC Reference 0

Section 17.7.1.10

ADCREF1

ADC Reference 1

Section 17.7.1.11

AUX – Sensor Controller with Digital and Analog Peripherals

Section

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.1.1 MUX0 Register (Offset = 0h) [reset = 0h]
MUX0 is shown in Figure 17-3 and described in Table 17-22.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 17-3. MUX0 Register
7

COMPA_IN
R/W-0h

COMPA_REF
R/W-0h

Table 17-22. MUX0 Register Field Descriptions
Bit

Field

Type

Reset

Description

7-4

COMPA_IN

R/W

Internal. Only to be used through TI provided API.

3-0

COMPA_REF

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1331

AUX – Sensor Controller Registers

www.ti.com

17.7.1.2 MUX1 Register (Offset = 1h) [reset = 0h]
MUX1 is shown in Figure 17-4 and described in Table 17-23.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 17-4. MUX1 Register
7

COMPA_IN
R/W-0h

Table 17-23. MUX1 Register Field Descriptions

1332

Bit

Field

Type

Reset

Description

7-0

COMPA_IN

R/W

Internal. Only to be used through TI provided API.

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.1.3 MUX2 Register (Offset = 2h) [reset = 0h]
MUX2 is shown in Figure 17-5 and described in Table 17-24.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 17-5. MUX2 Register
7

5
ADCCOMPB_IN
R/W-0h

1
COMPB_REF
R/W-0h

Table 17-24. MUX2 Register Field Descriptions
Bit

Field

Type

Reset

Description

7-3

ADCCOMPB_IN

R/W

Internal. Only to be used through TI provided API.

2-0

COMPB_REF

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1333

AUX – Sensor Controller Registers

www.ti.com

17.7.1.4 MUX3 Register (Offset = 3h) [reset = 0h]
MUX3 is shown in Figure 17-6 and described in Table 17-25.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 17-6. MUX3 Register
7

4
3
ADCCOMPB_IN
R/W-0h

Table 17-25. MUX3 Register Field Descriptions

1334

Bit

Field

Type

Reset

Description

7-0

ADCCOMPB_IN

R/W

Internal. Only to be used through TI provided API.

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.1.5 ISRC Register (Offset = 4h) [reset = 0h]
ISRC is shown in Figure 17-7 and described in Table 17-26.
Return to Summary Table.
Current Source
Strength and trim control for current source
Figure 17-7. ISRC Register
7

TRIM
R/W-0h

1
RESERVED
R/W-0h

0
EN
R/W-0h

Table 17-26. ISRC Register Field Descriptions
Bit

Field

Type

Reset

Description

7-2

TRIM

R/W

Adjust current from current source.
Output currents may be combined to get desired total current.
0h = No current connected
1h = 0P25U : 0.25 uA
2h = 0P5U : 0.5 uA
4h = 1P0U : 1.0 uA
8h = 2P0U : 2.0 uA
10h = 4P5U : 4.5 uA
20h = 11P75U : 11.75 uA

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Current source enable

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1335

AUX – Sensor Controller Registers

www.ti.com

17.7.1.6 COMP Register (Offset = 5h) [reset = 0h]
COMP is shown in Figure 17-8 and described in Table 17-27.
Return to Summary Table.
Comparator
Control COMPA and COMPB comparators
Figure 17-8. COMP Register
7
COMPA_REF_
RES_EN
R/W-0h

6
COMPA_REF_
CURR_EN
R/W-0h

4
COMPB_TRIM

R/W-0h

2
COMPB_EN

1
RESERVED

0
COMPA_EN

R/W-0h

Table 17-27. COMP Register Field Descriptions
Bit

Field

Type

Reset

Description

COMPA_REF_RES_EN

R/W

Enables 400kohm resistance from COMPA reference node to
ground. Used with COMPA_REF_CURR_EN to generate voltage
reference for cap-sense.

COMPA_REF_CURR_EN R/W

Enables 2uA IPTAT current from ISRC to COMPA reference node.
Requires ISRC.EN = 1. Used with COMPA_REF_RES_EN to
generate voltage reference for cap-sense.

COMPB_TRIM

R/W

COMPB voltage reference trim temperature coded:
0h = No reference division
1h = Divide reference by 2
3h = Divide reference by 3
7h = Divide reference by 4

COMPB_EN

R/W

COMPB enable

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

COMPA_EN

R/W

COMPA enable

5-3

1336

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.1.7 MUX4 Register (Offset = 7h) [reset = 0h]
MUX4 is shown in Figure 17-9 and described in Table 17-28.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 17-9. MUX4 Register
7

COMPA_REF
R/W-0h

Table 17-28. MUX4 Register Field Descriptions
Bit

Field

Type

Reset

Description

7-0

COMPA_REF

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1337

AUX – Sensor Controller Registers

www.ti.com

17.7.1.8 ADC0 Register (Offset = 8h) [reset = 0h]
ADC0 is shown in Figure 17-10 and described in Table 17-29.
Return to Summary Table.
ADC Control 0
Figure 17-10. ADC0 Register
7
SMPL_MODE
R/W-0h

5
4
SMPL_CYCLE_EXP
R/W-0h

2
RESERVED
R/W-0h

1
RESET_N
R/W-0h

0
EN
R/W-0h

Table 17-29. ADC0 Register Field Descriptions
Bit

Field

Type

Reset

Description

SMPL_MODE

R/W

ADC Sampling mode:
0: Synchronous mode
1: Asynchronous mode
The ADC does a sample-and-hold before conversion. In
synchronous mode the sampling starts when the ADC clock detects
a rising edge on the trigger signal. Jitter/uncertainty will be inferred in
the detection if the trigger signal originates from a domain that is
asynchronous to the ADC clock. SMPL_CYCLE_EXP determines the
the duration of sampling.
Conversion starts immediately after sampling ends.
In asynchronous mode the sampling is continuous when enabled.
Sampling ends and conversion starts immediately with the rising
edge of the trigger signal. Sampling restarts when the conversion
has finished.
Asynchronous mode is useful when it is important to avoid jitter in
the sampling instant of an externally driven signal

SMPL_CYCLE_EXP

R/W

Controls the sampling duration before conversion when the ADC is
operated in synchronous mode (SMPL_MODE = 0). The setting has
no effect in asynchronous mode. The sampling duration is given as
2SMPL_CYCLE_EXP + 1 / 6 us.
3h = 2P7_US : 16x 6 MHz clock periods = 2.7us
4h = 5P3_US : 32x 6 MHz clock periods = 5.3us
5h = 10P6_US : 64x 6 MHz clock periods = 10.6us
6h = 21P3_US : 128x 6 MHz clock periods = 21.3us
7h = 42P6_US : 256x 6 MHz clock periods = 42.6us
8h = 85P3_US : 512x 6 MHz clock periods = 85.3us
9h = 170_US : 1024x 6 MHz clock periods = 170us
Ah = 341_US : 2048x 6 MHz clock periods = 341us
Bh = 682_US : 4096x 6 MHz clock periods = 682us
Ch = 1P37_MS : 8192x 6 MHz clock periods = 1.37ms
Dh = 2P73_MS : 16384x 6 MHz clock periods = 2.73ms
Eh = 5P46_MS : 32768x 6 MHz clock periods = 5.46ms
Fh = 10P9_MS : 65536x 6 MHz clock periods = 10.9ms

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RESET_N

R/W

Reset ADC digital subchip, active low. ADC must be reset every time
it is reconfigured.
0: Reset
1: Normal operation

R/W

ADC Enable
0: Disable
1: Enable

6-3

1338

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.1.9 ADC1 Register (Offset = 9h) [reset = 0h]
ADC1 is shown in Figure 17-11 and described in Table 17-30.
Return to Summary Table.
ADC Control 1
Figure 17-11. ADC1 Register
7

4
RESERVED
R/W-0h

0
SCALE_DIS
R/W-0h

Table 17-30. ADC1 Register Field Descriptions
Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SCALE_DIS

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1339

AUX – Sensor Controller Registers

www.ti.com

17.7.1.10 ADCREF0 Register (Offset = Ah) [reset = 0h]
ADCREF0 is shown in Figure 17-12 and described in Table 17-31.
Return to Summary Table.
ADC Reference 0
Control reference used by the ADC
Figure 17-12. ADCREF0 Register
7
RESERVED
R/W-0h

6
REF_ON_IDLE
R/W-0h

5
IOMUX
R/W-0h

4
EXT
R/W-0h

3
SRC
R/W-0h

1
RESERVED
R/W-0h

0
EN
R/W-0h

Table 17-31. ADCREF0 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

REF_ON_IDLE

R/W

Keep ADCREF powered up in IDLE state when ADC0.SMPL_MODE
= 0.
Set to 1 if ADC0.SMPL_CYCLE_EXP is less than 6 (21.3us
sampling time)

IOMUX

R/W

Internal. Only to be used through TI provided API.

EXT

R/W

Internal. Only to be used through TI provided API.

SRC

R/W

ADC reference source:
0: Fixed reference = 4.3V
1: Relative reference = VDDS

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

ADC reference module enable:
0: ADC reference module powered down
1: ADC reference module enabled

2-1
0

1340

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.1.11 ADCREF1 Register (Offset = Bh) [reset = 0h]
ADCREF1 is shown in Figure 17-13 and described in Table 17-32.
Return to Summary Table.
ADC Reference 1
Control reference used by the ADC
Figure 17-13. ADCREF1 Register
7

RESERVED
R/W-0h

VTRIM
R/W-0h

Table 17-32. ADCREF1 Register Field Descriptions
Bit

Field

Type

Reset

Description

7-6

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

5-0

VTRIM

R/W

Trim output voltage of ADC fixed reference (64 steps, 2's
complement). Applies only for ADCREF0.SRC = 0.
Examples:
0x00 - nominal voltage 1.43V
0x01 - nominal + 0.4% 1.435V
0x3F - nominal - 0.4% 1.425V
0x1F - maximum voltage 1.6V
0x20 - minimum voltage 1.3V

17.7.2 AUX_AIODIO Registers
Table 17-33 lists the memory-mapped registers for the AUX_AIODIO. All register offset addresses not
listed in Table 17-33 should be considered as reserved locations and the register contents should not be
modified.
Table 17-33. AUX_AIODIO Registers
Offset

Acronym

GPIODOUT

General Purpose Input/Output Data Out

Section 17.7.2.1

IOMODE

Input Output Mode

Section 17.7.2.2

GPIODIN

General Purpose Input Output Data In

Section 17.7.2.3

GPIODOUTSET

General Purpose Input Output Data Out Set

Section 17.7.2.4

10h

GPIODOUTCLR

General Purpose Input Output Data Out Clear

Section 17.7.2.5

14h

GPIODOUTTGL

General Purpose Input Output Data Out Toggle

Section 17.7.2.6

18h

GPIODIE

General Purpose Input Output Input Enable

Section 17.7.2.7

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Section

AUX – Sensor Controller with Digital and Analog Peripherals

1341

AUX – Sensor Controller Registers

www.ti.com

17.7.2.1 GPIODOUT Register (Offset = 0h) [reset = 0h]
GPIODOUT is shown in Figure 17-14 and described in Table 17-34.
Return to Summary Table.
General Purpose Input/Output Data Out
This register is used to set data on the pads assigned to AUX
Figure 17-14. GPIODOUT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
IO7_0
R/W-0h

Table 17-34. GPIODOUT Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

IO7_0

R/W

Output values for AUXIO0 through AUXIO7 (for AIODIO0) or
AUXIO8 through AUXIO15 (for AIODIO1).

1342

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.2.2 IOMODE Register (Offset = 4h) [reset = 0h]
IOMODE is shown in Figure 17-15 and described in Table 17-35.
Return to Summary Table.
Input Output Mode
Controls pull-up pull-down and output mode for the IO pins assigned to AUX
Figure 17-15. IOMODE Register
31

14
IO7
R/W-0h

12
IO6
R/W-0h

10
IO5
R/W-0h

24
23
RESERVED
R-0h

IO4
R/W-0h

7
IO3
R/W-0h

IO2
R/W-0h

IO1
R/W-0h

IO0
R/W-0h

Table 17-35. IOMODE Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-14

IO7

R/W

Selects mode for AUXIO7 (for AIODIO0) or AUXIO15 (for AIODIO1).
0h = Output
1h = Digital input with GPIODIE bit 7 = 1
Analog input/output with GPIODIE bit 7 = 0
2h = Open-drain: The pin is driven low when the corresponding
GPIODOUT bit is 0, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.
3h = Open-source: The pin is driven high when the corresponding
GPIODOUT bit is 1, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.

13-12

IO6

R/W

Selects mode for AUXIO6 (for AIODIO0) or AUXIO14 (for AIODIO1).
0h = Output
1h = Digital input with GPIODIE bit 6 = 1
Analog input/output with GPIODIE bit 6 = 0
2h = Open-drain: The pin is driven low when the corresponding
GPIODOUT bit is 0, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.
3h = Open-source: The pin is driven high when the corresponding
GPIODOUT bit is 1, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.

11-10

IO5

R/W

Selects mode for AUXIO5 (for AIODIO0) or AUXIO13 (for AIODIO1).
0h = Output
1h = Digital input with GPIODIE bit 5 = 1
Analog input/output with GPIODIE bit 5 = 0
2h = Open-drain: The pin is driven low when the corresponding
GPIODOUT bit is 0, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.
3h = Open-source: The pin is driven high when the corresponding
GPIODOUT bit is 1, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1343

AUX – Sensor Controller Registers

www.ti.com

Table 17-35. IOMODE Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

9-8

IO4

R/W

Selects mode for AUXIO4 (for AIODIO0) or AUXIO12 (for AIODIO1).
0h = Output
1h = Digital input with GPIODIE bit 4 = 1
Analog input/output with GPIODIE bit 4 = 0
2h = Open-drain: The pin is driven low when the corresponding
GPIODOUT bit is 0, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.
3h = Open-source: The pin is driven high when the corresponding
GPIODOUT bit is 1, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.

7-6

IO3

R/W

Selects mode for AUXIO3 (for AIODIO0) or AUXIO11 (for AIODIO1).
0h = Output
1h = Digital input with GPIODIE bit 3 = 1
Analog input/output with GPIODIE bit 3 = 0
2h = Open-drain: The pin is driven low when the corresponding
GPIODOUT bit is 0, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.
3h = Open-source: The pin is driven high when the corresponding
GPIODOUT bit is 1, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.

5-4

IO2

R/W

Selects mode for AUXIO2 (for AIODIO0) or AUXIO10 (for AIODIO1).
0h = Output
1h = Digital input with GPIODIE bit 2 = 1
Analog input/output with GPIODIE bit 2 = 0
2h = Open-drain: The pin is driven low when the corresponding
GPIODOUT bit is 0, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.
3h = Open-source: The pin is driven high when the corresponding
GPIODOUT bit is 1, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.

3-2

IO1

R/W

Selects mode for AUXIO1 (for AIODIO0) or AUXIO9 (for AIODIO1).
0h = Output
1h = Digital input with GPIODIE bit 1 = 1
Analog input/output with GPIODIE bit 1 = 0
2h = Open-drain: The pin is driven low when the corresponding
GPIODOUT bit is 0, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.
3h = Open-source: The pin is driven high when the corresponding
GPIODOUT bit is 1, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.

1-0

IO0

R/W

Selects mode for AUXIO0 (for AIODIO0) or AUXIO8 (for AIODIO1).
0h = Output
1h = Digital input with GPIODIE bit 0 = 1
Analog input/output with GPIODIE bit 0 = 0
2h = Open-drain: The pin is driven low when the corresponding
GPIODOUT bit is 0, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.
3h = Open-source: The pin is driven high when the corresponding
GPIODOUT bit is 1, and otherwise tri-stated or pulled depending on
the corresponding IOC configuration.

1344

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.2.3 GPIODIN Register (Offset = 8h) [reset = 0h]
GPIODIN is shown in Figure 17-16 and described in Table 17-36.
Return to Summary Table.
General Purpose Input Output Data In
Figure 17-16. GPIODIN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3
IO7_0
R-0h

Table 17-36. GPIODIN Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

IO7_0

Input values for AUXIO0 through AUXIO7 (for AIODIO0) or AUXIO8
through AUXIO15 (for AIODIO1).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1345

AUX – Sensor Controller Registers

www.ti.com

17.7.2.4 GPIODOUTSET Register (Offset = Ch) [reset = 0h]
GPIODOUTSET is shown in Figure 17-17 and described in Table 17-37.
Return to Summary Table.
General Purpose Input Output Data Out Set
Strobes for setting output data register bits
Figure 17-17. GPIODOUTSET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
IO7_0
R/W-0h

Table 17-37. GPIODOUTSET Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

IO7_0

R/W

Writing 1(s) to one or more bit positions sets the corresponding bit(s)
in GPIODOUT.
Read value is 0x00.

1346

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.2.5 GPIODOUTCLR Register (Offset = 10h) [reset = 0h]
GPIODOUTCLR is shown in Figure 17-18 and described in Table 17-38.
Return to Summary Table.
General Purpose Input Output Data Out Clear
Strobes for clearing output data register bits
Figure 17-18. GPIODOUTCLR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
IO7_0
R/W-0h

Table 17-38. GPIODOUTCLR Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

IO7_0

R/W

Writing 1(s) to one or more bit positions clears the corresponding
bit(s) in GPIODOUT.
Read value is 0x00.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1347

AUX – Sensor Controller Registers

www.ti.com

17.7.2.6 GPIODOUTTGL Register (Offset = 14h) [reset = 0h]
GPIODOUTTGL is shown in Figure 17-19 and described in Table 17-39.
Return to Summary Table.
General Purpose Input Output Data Out Toggle
Strobes for toggling output data register bits
Figure 17-19. GPIODOUTTGL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
IO7_0
R/W-0h

Table 17-39. GPIODOUTTGL Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

IO7_0

R/W

Writing 1(s) to one or more bit positions toggles the corresponding
bit(s) in GPIODOUT.
Read value is 0x00.

1348

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.2.7 GPIODIE Register (Offset = 18h) [reset = 0h]
GPIODIE is shown in Figure 17-20 and described in Table 17-40.
Return to Summary Table.
General Purpose Input Output Input Enable
Figure 17-20. GPIODIE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
IO7_0
R/W-0h

Table 17-40. GPIODIE Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

IO7_0

R/W

Enables (1) or disables (0) digital input buffers for each AUX I/O pin.
Input buffers must be enabled to allow reading pin values through
GPIODIN.
Input buffers must be disabled for analog input or floating pins to
avoid current leakage.

17.7.3 AUX_EVCTL Registers
Table 17-41 lists the memory-mapped registers for the AUX_EVCTL. All register offset addresses not
listed in Table 17-41 should be considered as reserved locations and the register contents should not be
modified.
Table 17-41. AUX_EVCTL Registers
Offset

Acronym

VECCFG0

Vector Configuration 0

Section 17.7.3.1

Section

VECCFG1

Vector Configuration 1

Section 17.7.3.2

SCEWEVSEL

Sensor Controller Engine Wait Event Selection

Section 17.7.3.3

EVTOAONFLAGS

Events To AON Domain Flags

Section 17.7.3.4

10h

EVTOAONPOL

Events To AON Domain Polarity

Section 17.7.3.5

14h

DMACTL

Direct Memory Access Control

Section 17.7.3.6

18h

SWEVSET

Software Event Set

Section 17.7.3.7

1Ch

EVSTAT0

Event Status 0

Section 17.7.3.8

20h

EVSTAT1

Event Status 1

Section 17.7.3.9

24h

EVTOMCUPOL

Event To MCU Domain Polarity

Section 17.7.3.10

28h

EVTOMCUFLAGS

Events to MCU Domain Flags

Section 17.7.3.11

2Ch

COMBEVTOMCUMASK

Combined Event To MCU Domain Mask

Section 17.7.3.12

34h

VECFLAGS

Vector Flags

Section 17.7.3.13

38h

EVTOMCUFLAGSCLR

Events To MCU Domain Flags Clear

Section 17.7.3.14

3Ch

EVTOAONFLAGSCLR

Events To AON Domain Clear

Section 17.7.3.15

40h

VECFLAGSCLR

Vector Flags Clear

Section 17.7.3.16

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1349

AUX – Sensor Controller Registers

www.ti.com

17.7.3.1 VECCFG0 Register (Offset = 0h) [reset = 0h]
VECCFG0 is shown in Figure 17-21 and described in Table 17-42.
Return to Summary Table.
Vector Configuration 0
AUX_SCE event vectors 0 and 1 configuration
Figure 17-21. VECCFG0 Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

15
RESERVED
R-0h

14
VEC1_POL
R/W-0h

13
VEC1_EN
R/W-0h

10
VEC1_EV
R/W-0h

7
RESERVED
R-0h

6
VEC0_POL
R/W-0h

5
VEC0_EN
R/W-0h

2
VEC0_EV
R/W-0h

Table 17-42. VECCFG0 Register Field Descriptions
Field

Type

Reset

Description

31-15

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

VEC1_POL

R/W

Selects vector 1 trigger event polarity.
To manually trigger vector 1 execution, set VEC1_EV to a known
static value, and toggle VEC1_POL twice.
0h = Rising edge triggers execution.
1h = Falling edge triggers execution.

VEC1_EN

R/W

Enables (1) or disables (0) triggering of vector 1 execution.
When enabled, the edge selected by VEC1_POL on the event
selected by VEC1_EV will set VECFLAGS.VEC1, which in turn
triggers vector 1 execution.
Note: Lower vectors (0) have priority.
0h = Event detection is disabled
1h = An event selected by VEC1_EV with polarity from VEC1_POL
triggers a jump to vector # 1 when AUX_SCE is in sleep

1350

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

Table 17-42. VECCFG0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

VEC1_EV

R/W

Selects vector 1 trigger source event.
0h = AON_RTC_CH2 event
1h = AUX_COMPA event
2h = AUX_COMPB event
3h = TDC_DONE event
4h = TIMER0_EV event
5h = TIMER1_EV event
6h = SMPH_AUTOTAKE_DONE event
7h = ADC_DONE event
8h = ADC_FIFO_ALMOST_FULL event
9h = OBSMUX0 event
Ah = OBSMUX1 event
Bh = AON_SW event
Ch = AON_PROG_WU event
Dh = AUXIO0 input data
Eh = AUXIO1 input data
Fh = AUXIO2 input data
10h = AUXIO3 input data
11h = AUXIO4 input data
12h = AUXIO5 input data
13h = AUXIO6 input data
14h = AUXIO7 input data
15h = AUXIO8 input data
16h = AUXIO9 input data
17h = AUXIO10 input data
18h = AUXIO11 input data
19h = AUXIO12 input data
1Ah = AUXIO13 input data
1Bh = AUXIO14 input data
1Ch = AUXIO15 input data
1Dh = ACLK_REF event
1Eh = MCU_EV event
1Fh = ADC_IRQ event

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

VEC0_POL

R/W

Selects vector 0 trigger event polarity.
To manually trigger vector 0 execution, set VEC0_EV to a known
static value, and toggle VEC0_POL twice.
0h = Rising edge triggers execution.
1h = Falling edge triggers execution.

VEC0_EN

R/W

Enables (1) or disables (0) triggering of vector 0 execution.
When enabled, the edge selected by VEC0_POL on the event
selected by VEC0_EV will set VECFLAGS.VEC0, which in turn
triggers vector 0 execution.
0h = Event detection is disabled
1h = An event selected by VEC0_EV with polarity from VEC0_POL
triggers a jump to vector #0 when AUX_SCE is in sleep

12-8

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1351

AUX – Sensor Controller Registers

www.ti.com

Table 17-42. VECCFG0 Register Field Descriptions (continued)

1352

Bit

Field

Type

Reset

Description

4-0

VEC0_EV

R/W

Selects vector 0 trigger source event.
0h = AON_RTC_CH2 event
1h = AUX_COMPA event
2h = AUX_COMPB event
3h = TDC_DONE event
4h = TIMER0_EV event
5h = TIMER1_EV event
6h = SMPH_AUTOTAKE_DONE event
7h = ADC_DONE event
8h = ADC_FIFO_ALMOST_FULL event
9h = OBSMUX0 event
Ah = OBSMUX1 event
Bh = AON_SW event
Ch = AON_PROG_WU event
Dh = AUXIO0 input data
Eh = AUXIO1 input data
Fh = AUXIO2 input data
10h = AUXIO3 input data
11h = AUXIO4 input data
12h = AUXIO5 input data
13h = AUXIO6 input data
14h = AUXIO7 input data
15h = AUXIO8 input data
16h = AUXIO9 input data
17h = AUXIO10 input data
18h = AUXIO11 input data
19h = AUXIO12 input data
1Ah = AUXIO13 input data
1Bh = AUXIO14 input data
1Ch = AUXIO15 input data
1Dh = ACLK_REF event
1Eh = MCU_EV event
1Fh = ADC_IRQ event

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.3.2 VECCFG1 Register (Offset = 4h) [reset = 0h]
VECCFG1 is shown in Figure 17-22 and described in Table 17-43.
Return to Summary Table.
Vector Configuration 1
AUX_SCE event vectors 2 and 3 configuration
Figure 17-22. VECCFG1 Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

15
RESERVED
R-0h

14
VEC3_POL
R/W-0h

13
VEC3_EN
R/W-0h

10
VEC3_EV
R/W-0h

7
RESERVED
R-0h

6
VEC2_POL
R/W-0h

5
VEC2_EN
R/W-0h

2
VEC2_EV
R/W-0h

Table 17-43. VECCFG1 Register Field Descriptions
Field

Type

Reset

Description

31-15

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

VEC3_POL

R/W

Selects vector 3 trigger event polarity.
To manually trigger vector 3 execution, set VEC3_EV to a known
static value, and toggle VEC3_POL twice.
0h = Rising edge triggers execution.
1h = Falling edge triggers execution.

VEC3_EN

R/W

Enables (1) or disables (0) triggering of vector 3 execution.
When enabled, the edge selected by VEC3_POL on the event
selected by VEC3_EV will set VECFLAGS.VEC3, which in turn
triggers vector 3 execution.
Note: Lower vectors (0, 1 and 2) have priority.
0h = Event detection is disabled
1h = An event selected by VEC3_EV with polarity from VEC3_POL
triggers a jump to vector # 3 when AUX_SCE is in sleep

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1353

AUX – Sensor Controller Registers

www.ti.com

Table 17-43. VECCFG1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

VEC3_EV

R/W

Selects vector 3 trigger source event.
0h = AON_RTC_CH2 event
1h = AUX_COMPA event
2h = AUX_COMPB event
3h = TDC_DONE event
4h = TIMER0_EV event
5h = TIMER1_EV event
6h = SMPH_AUTOTAKE_DONE event
7h = ADC_DONE event
8h = ADC_FIFO_ALMOST_FULL event
9h = OBSMUX0 event
Ah = OBSMUX1 event
Bh = AON_SW event
Ch = AON_PROG_WU event
Dh = AUXIO0 input data
Eh = AUXIO1 input data
Fh = AUXIO2 input data
10h = AUXIO3 input data
11h = AUXIO4 input data
12h = AUXIO5 input data
13h = AUXIO6 input data
14h = AUXIO7 input data
15h = AUXIO8 input data
16h = AUXIO9 input data
17h = AUXIO10 input data
18h = AUXIO11 input data
19h = AUXIO12 input data
1Ah = AUXIO13 input data
1Bh = AUXIO14 input data
1Ch = AUXIO15 input data
1Dh = ACLK_REF event
1Eh = MCU_EV event
1Fh = ADC_IRQ event

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

VEC2_POL

R/W

Selects vector 2 trigger event polarity.
To manually trigger vector 2 execution, set VEC2_EV to a known
static value, and toggle VEC2_POL twice.
0h = Rising edge triggers execution.
1h = Falling edge triggers execution.

VEC2_EN

R/W

Enables (1) or disables (0) triggering of vector 2 execution.
When enabled, the edge selected by VEC2_POL on the event
selected by VEC2_EV will set VECFLAGS.VEC2, which in turn
triggers vector 2 execution.
Note: Lower vectors (0 and 1) have priority.
0h = Event detection is disabled
1h = An event selected by VEC2_EV with polarity from VEC2_POL
triggers a jump to vector # 2 when AUX_SCE is in sleep

12-8

1354

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

Table 17-43. VECCFG1 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

4-0

VEC2_EV

R/W

Selects vector 2 trigger source event.
0h = AON_RTC_CH2 event
1h = AUX_COMPA event
2h = AUX_COMPB event
3h = TDC_DONE event
4h = TIMER0_EV event
5h = TIMER1_EV event
6h = SMPH_AUTOTAKE_DONE event
7h = ADC_DONE event
8h = ADC_FIFO_ALMOST_FULL event
9h = OBSMUX0 event
Ah = OBSMUX1 event
Bh = AON_SW event
Ch = AON_PROG_WU event
Dh = AUXIO0 input data
Eh = AUXIO1 input data
Fh = AUXIO2 input data
10h = AUXIO3 input data
11h = AUXIO4 input data
12h = AUXIO5 input data
13h = AUXIO6 input data
14h = AUXIO7 input data
15h = AUXIO8 input data
16h = AUXIO9 input data
17h = AUXIO10 input data
18h = AUXIO11 input data
19h = AUXIO12 input data
1Ah = AUXIO13 input data
1Bh = AUXIO14 input data
1Ch = AUXIO15 input data
1Dh = ACLK_REF event
1Eh = MCU_EV event
1Fh = ADC_IRQ event

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1355

AUX – Sensor Controller Registers

www.ti.com

17.7.3.3 SCEWEVSEL Register (Offset = 8h) [reset = 0h]
SCEWEVSEL is shown in Figure 17-23 and described in Table 17-44.
Return to Summary Table.
Sensor Controller Engine Wait Event Selection
Event selection for the AUX_SCE WEV0, WEV1, BEV0 and BEV1 instructions
Figure 17-23. SCEWEVSEL Register
31

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

2
WEV7_EV
R/W-0h

Table 17-44. SCEWEVSEL Register Field Descriptions
Field

Type

Reset

Description

31-5

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

4-0

WEV7_EV

R/W

Selects the event source to be mapped to
AUX_SCE:WUSTAT.EV_SIGNALS bit 7.
0h = AON_RTC_CH2 event
1h = AUX_COMPA event
2h = AUX_COMPB event
3h = TDC_DONE event
4h = TIMER0_EV event
5h = TIMER1_EV event
6h = SMPH_AUTOTAKE_DONE event
7h = ADC_DONE event
8h = ADC_FIFO_ALMOST_FULL event
9h = OBSMUX0 event
Ah = OBSMUX1 event
Bh = AON_SW event
Ch = AON_PROG_WU event
Dh = AUXIO0 input data
Eh = AUXIO1 input data
Fh = AUXIO2 input data
10h = AUXIO3 input data
11h = AUXIO4 input data
12h = AUXIO5 input data
13h = AUXIO6 input data
14h = AUXIO7 input data
15h = AUXIO8 input data
16h = AUXIO9 input data
17h = AUXIO10 input data
18h = AUXIO11 input data
19h = AUXIO12 input data
1Ah = AUXIO13 input data
1Bh = AUXIO14 input data
1Ch = AUXIO15 input data
1Dh = ACLK_REF event
1Eh = MCU_EV event
1Fh = ADC_IRQ event

1356

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.3.4 EVTOAONFLAGS Register (Offset = Ch) [reset = 0h]
EVTOAONFLAGS is shown in Figure 17-24 and described in Table 17-45.
Return to Summary Table.
Events To AON Domain Flags
AUX event flags going to/through the AON domain
These events may be used to wake up the MCU domain.
The flags may be cleared by writing 0 to these bits or writing 1 to the corresponding bits in
EVTOAONFLAGSCLR.
Figure 17-24. EVTOAONFLAGS Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

8
TIMER1_EV
R/W0C-0h

7
TIMER0_EV
R/W0C-0h

6
TDC_DONE
R/W0C-0h

5
ADC_DONE
R/W0C-0h

4
AUX_COMPB
R/W0C-0h

3
AUX_COMPA
R/W0C-0h

2
SWEV2
R/W0C-0h

1
SWEV1
R/W0C-0h

0
SWEV0
R/W0C-0h

Table 17-45. EVTOAONFLAGS Register Field Descriptions
Bit

Field

Type

Reset

Description

31-9

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TIMER1_EV

R/W0C

TIMER1_EV event flag.

TIMER0_EV

R/W0C

TIMER0_EV event flag.

TDC_DONE

R/W0C

TDC_DONE event flag.

ADC_DONE

R/W0C

ADC_DONE event flag.

AUX_COMPB

R/W0C

AUX_COMPB event flag.

AUX_COMPA

R/W0C

AUX_COMPA event flag.

SWEV2

R/W0C

SWEV2 event flag.

SWEV1

R/W0C

SWEV1 event flag.

SWEV0

R/W0C

SWEV0 event flag.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1357

AUX – Sensor Controller Registers

www.ti.com

17.7.3.5 EVTOAONPOL Register (Offset = 10h) [reset = 0h]
EVTOAONPOL is shown in Figure 17-25 and described in Table 17-46.
Return to Summary Table.
Events To AON Domain Polarity
AUX event source polarity for the event flags going to/through the AON domain
Note the inverse polarity (0 = high, 1 = low).
Figure 17-25. EVTOAONPOL Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

8
TIMER1_EV
R/W-0h

7
TIMER0_EV
R/W-0h

6
TDC_DONE
R/W-0h

5
ADC_DONE
R/W-0h

4
AUX_COMPB
R/W-0h

3
AUX_COMPA
R/W-0h

1
RESERVED
R-0h

Table 17-46. EVTOAONPOL Register Field Descriptions
Field

Type

Reset

Description

31-9

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TIMER1_EV

R/W

Selects the event source level that sets
EVTOAONFLAGS.TIMER1_EV.
0h = High level
1h = Low level

TIMER0_EV

R/W

Selects the event source level that sets
EVTOAONFLAGS.TIMER0_EV.
0h = High level
1h = Low level

TDC_DONE

R/W

Selects the event source level that sets
EVTOAONFLAGS.TDC_DONE.
0h = High level
1h = Low level

ADC_DONE

R/W

Selects the event source level that sets
EVTOAONFLAGS.ADC_DONE.
0h = High level
1h = Low level

AUX_COMPB

R/W

Selects the event source level that sets
EVTOAONFLAGS.AUX_COMPB.
0h = High level
1h = Low level

AUX_COMPA

R/W

Selects the event source level that sets
EVTOAONFLAGS.AUX_COMPA.
0h = High level
1h = Low level

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

2-0

1358

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.3.6 DMACTL Register (Offset = 14h) [reset = 0h]
DMACTL is shown in Figure 17-26 and described in Table 17-47.
Return to Summary Table.
Direct Memory Access Control
Figure 17-26. DMACTL Register
31

2
REQ_MODE
R/W-0h

1
EN
R/W-0h

0
SEL
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

Table 17-47. DMACTL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-3

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

REQ_MODE

R/W

DMA Request mode
0h = Burst requests are generated on DMA channel 7 when the
condition configured in SEL is met
1h = Single requests are generated on DMA channel 7 when the
condition configured in SEL is met

R/W

0: DMA interface is disabled
1: DMA interface is enabled

SEL

R/W

Selection of FIFO watermark level required to trigger an ADC_DMA
transfer
0h = ADC_DMA event will be generated when there are valid
samples in the ADC FIFO
1h = ADC_DMA event will be generated when the ADC FIFO is
almost full (3/4 full)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1359

AUX – Sensor Controller Registers

www.ti.com

17.7.3.7 SWEVSET Register (Offset = 18h) [reset = 0h]
SWEVSET is shown in Figure 17-27 and described in Table 17-48.
Return to Summary Table.
Software Event Set
Strobes for setting software events from the AUX domain to the AON/MCU Domains
The use of these events is software-defined.
Figure 17-27. SWEVSET Register
31

2
SWEV2
W-0h

1
SWEV1
W-0h

0
SWEV0
W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

Table 17-48. SWEVSET Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SWEV2

Writing 1 sets software event 2.
For the MCU domain, the event flag can be read from
EVTOAONFLAGS.SWEV2 and cleared using
EVTOAONFLAGSCLR.SWEV2.

SWEV1

Writing 1 sets software event 1.
For the MCU domain, the event flag can be read from
EVTOAONFLAGS.SWEV1 and cleared using
EVTOAONFLAGSCLR.SWEV1.

SWEV0

Writing 1 sets software event 0.
For the MCU domain, the event flag can be read from
EVTOAONFLAGS.SWEV0 and cleared using
EVTOAONFLAGSCLR.SWEV0.

31-3

1360

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.3.8 EVSTAT0 Register (Offset = 1Ch) [reset = 0h]
EVSTAT0 is shown in Figure 17-28 and described in Table 17-49.
Return to Summary Table.
Event Status 0
Current event source levels, 15:0
Figure 17-28. EVSTAT0 Register
31

11
AON_SW

10
OBSMUX1

9
OBSMUX0

R-0h

8
ADC_FIFO_AL
MOST_FULL
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

15
AUXIO2

14
AUXIO1

13
AUXIO0

R-0h

12
AON_PROG_
WU
R-0h

7
ADC_DONE

6
SMPH_AUTOT
AKE_DONE
R-0h

5
TIMER1_EV

4
TIMER0_EV

3
TDC_DONE

2
AUX_COMPB

1
AUX_COMPA

R-0h

0
AON_RTC_CH
2
R-0h

Table 17-49. EVSTAT0 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AUXIO2

Current value of AUXIO2 input data line

AUXIO1

Current value of AUXIO1 input data line

AUXIO0

Current value of AUXIO0 input data line

AON_PROG_WU

Current value of OBSMUX3 event line

AON_SW

Current value of OBSMUX2 event line

OBSMUX1

Current value of OBSMUX1 event line

OBSMUX0

Current value of OBSMUX0 event line

ADC_FIFO_ALMOST_FU
LL

Current value of ADC_FIFO_ALMOST_FULL event line

ADC_DONE

Current value of ADC_DONE event line

SMPH_AUTOTAKE_DON R
E

Current value of SMPH_AUTOTAKE_DONE event line

TIMER1_EV

Current value of TIMER1_EV event line

TIMER0_EV

Current value of TIMER0_EV event line

TDC_DONE

Current value of TDC_DONE event line

AUX_COMPB

Current value of AUX_COMPB event line

AUX_COMPA

Current value of AUX_COMPA event line

AON_RTC_CH2

Current value of AON_RTC_CH2 event line

31-16

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1361

AUX – Sensor Controller Registers

www.ti.com

17.7.3.9 EVSTAT1 Register (Offset = 20h) [reset = 0h]
EVSTAT1 is shown in Figure 17-29 and described in Table 17-50.
Return to Summary Table.
Event Status 1
Current event source levels, 31:16
Figure 17-29. EVSTAT1 Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

15
ADC_IRQ
R-0h

14
MCU_EV
R-0h

13
ACLK_REF
R-0h

12
AUXIO15
R-0h

11
AUXIO14
R-0h

10
AUXIO13
R-0h

9
AUXIO12
R-0h

8
AUXIO11
R-0h

7
AUXIO10
R-0h

6
AUXIO9
R-0h

5
AUXIO8
R-0h

4
AUXIO7
R-0h

3
AUXIO6
R-0h

2
AUXIO5
R-0h

1
AUXIO4
R-0h

0
AUXIO3
R-0h

Table 17-50. EVSTAT1 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ADC_IRQ

Current value of ADC_IRQ event line

MCU_EV

Current value of MCU_EV event line

ACLK_REF

Current value of ACLK_REF event line

AUXIO15

Current value of AUXIO15 input data line

AUXIO14

Current value of AUXIO14 input data line

AUXIO13

Current value of AUXIO13 input data line

AUXIO12

Current value of AUXIO12 input data line

AUXIO11

Current value of AUXIO11 input data line

AUXIO10

Current value of AUXIO10 input data line

AUXIO9

Current value of AUXIO9 input data line

AUXIO8

Current value of AUXIO8 input data line

AUXIO7

Current value of AUXIO7 input data line

AUXIO6

Current value of AUXIO6 input data line

AUXIO5

Current value of AUXIO5 input data line

AUXIO4

Current value of AUXIO4 input data line

AUXIO3

Current value of AUXIO3 input data line

31-16

1362

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.3.10 EVTOMCUPOL Register (Offset = 24h) [reset = 0h]
EVTOMCUPOL is shown in Figure 17-30 and described in Table 17-51.
Return to Summary Table.
Event To MCU Domain Polarity
AUX event source polarity for the event flags to the MCU domain
Note the inverse polarity (0 = high, 1 = low).
Figure 17-30. EVTOMCUPOL Register
31

10
ADC_IRQ

9
OBSMUX0

R/W-0h

8
ADC_FIFO_AL
MOST_FULL
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

13
RESERVED

R-0h
7
ADC_DONE
R/W-0h

6
SMPH_AUTOT
AKE_DONE
R/W-0h

5
TIMER1_EV

4
TIMER0_EV

3
TDC_DONE

2
AUX_COMPB

1
AUX_COMPA

0
AON_WU_EV

R/W-0h

Table 17-51. EVTOMCUPOL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ADC_IRQ

R/W

Selects the event source level that sets
EVTOMCUFLAGS.ADC_IRQ.
0h = High level
1h = Low level

OBSMUX0

R/W

Selects the event source level that sets
EVTOMCUFLAGS.OBSMUX0.
0h = High level
1h = Low level

ADC_FIFO_ALMOST_FU
LL

R/W

Selects the event source level that sets
EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL.
0h = High level
1h = Low level

ADC_DONE

R/W

Selects the event source level that sets
EVTOMCUFLAGS.ADC_DONE.
0h = High level
1h = Low level

SMPH_AUTOTAKE_DON R/W
E

Selects the event source level that sets
EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE.
0h = High level
1h = Low level

TIMER1_EV

Selects the event source level that sets
EVTOMCUFLAGS.TIMER1_EV.
0h = High level
1h = Low level

31-11

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1363

AUX – Sensor Controller Registers

www.ti.com

Table 17-51. EVTOMCUPOL Register Field Descriptions (continued)
Bit

1364

Field

Type

Reset

Description

TIMER0_EV

R/W

Selects the event source level that sets
EVTOMCUFLAGS.TIMER0_EV.
0h = High level
1h = Low level

TDC_DONE

R/W

Selects the event source level that sets
EVTOMCUFLAGS.TDC_DONE.
0h = High level
1h = Low level

AUX_COMPB

R/W

Selects the event source level that sets
EVTOMCUFLAGS.AUX_COMPB.
0h = High level
1h = Low level

AUX_COMPA

R/W

Selects the event source level that sets
EVTOMCUFLAGS.AUX_COMPA.
0h = High level
1h = Low level

AON_WU_EV

R/W

Selects the event source level that sets
EVTOMCUFLAGS.AON_WU_EV
0h = High level
1h = Low level

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.3.11 EVTOMCUFLAGS Register (Offset = 28h) [reset = 0h]
EVTOMCUFLAGS is shown in Figure 17-31 and described in Table 17-52.
Return to Summary Table.
Events to MCU Domain Flags
AUX event flags going to the MCU domain
The flags may be cleared by writing 0 to these bits or writing 1 to the corresponding bits in
EVTOMCUFLAGSCLR.
Figure 17-31. EVTOMCUFLAGS Register
31

10
ADC_IRQ

9
OBSMUX0

R/W0C-0h

8
ADC_FIFO_AL
MOST_FULL
R/W0C-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

13
RESERVED

R-0h
7
ADC_DONE
R/W0C-0h

6
SMPH_AUTOT
AKE_DONE
R/W0C-0h

5
TIMER1_EV

4
TIMER0_EV

3
TDC_DONE

2
AUX_COMPB

1
AUX_COMPA

0
AON_WU_EV

R/W0C-0h

Table 17-52. EVTOMCUFLAGS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ADC_IRQ

R/W0C

ADC_IRQ event flag.

OBSMUX0

R/W0C

OBSMUX0 event flag.

ADC_FIFO_ALMOST_FU
LL

R/W0C

ADC_FIFO_ALMOST_FULL event flag.

ADC_DONE

R/W0C

ADC_DONE event flag.

SMPH_AUTOTAKE_DON R/W0C
E

SMPH_AUTOTAKE_DONE event flag.

TIMER1_EV

R/W0C

TIMER1_EV event flag.

TIMER0_EV

R/W0C

TIMER0_EV event flag.

TDC_DONE

R/W0C

TDC_DONE event flag.

AUX_COMPB

R/W0C

AUX_COMPB event flag.

AUX_COMPA

R/W0C

AUX_COMPA event flag.

AON_WU_EV

R/W0C

AON_WU_EV event flag.
This is an OR of the AON_RTC_CH2, AON_PROG_WU and
AON_SW events. These event sources must be cleared before
clearing AON_WU_EV.

31-11

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1365

AUX – Sensor Controller Registers

www.ti.com

17.7.3.12 COMBEVTOMCUMASK Register (Offset = 2Ch) [reset = 0h]
COMBEVTOMCUMASK is shown in Figure 17-32 and described in Table 17-53.
Return to Summary Table.
Combined Event To MCU Domain Mask
Selects which of the flags In EVTOMCUFLAGS that contribute to the AUX_COMB event to the MCU
domain
The AUX_COMB event is asserted as long as one or more of the included event flags are set.
Figure 17-32. COMBEVTOMCUMASK Register
31

10
ADC_IRQ

9
OBSMUX0

R/W-0h

8
ADC_FIFO_AL
MOST_FULL
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

13
RESERVED

R-0h
7
ADC_DONE
R/W-0h

6
SMPH_AUTOT
AKE_DONE
R/W-0h

5
TIMER1_EV

4
TIMER0_EV

3
TDC_DONE

2
AUX_COMPB

1
AUX_COMPA

0
AON_WU_EV

R/W-0h

Table 17-53. COMBEVTOMCUMASK Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ADC_IRQ

R/W

Includes (1) or excludes (0) EVTOMCUFLAGS.ADC_IRQ
contribution to the AUX_COMB event.

OBSMUX0

R/W

Includes (1) or excludes (0) EVTOMCUFLAGS.OBSMUX0
contribution to the AUX_COMB event.

ADC_FIFO_ALMOST_FU
LL

R/W

Includes (1) or excludes (0)
EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL contribution to the
AUX_COMB event.

ADC_DONE

R/W

Includes (1) or excludes (0) EVTOMCUFLAGS.ADC_DONE
contribution to the AUX_COMB event.

SMPH_AUTOTAKE_DON R/W
E

Includes (1) or excludes (0)
EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE contribution to the
AUX_COMB event.

TIMER1_EV

R/W

Includes (1) or excludes (0) EVTOMCUFLAGS.TIMER1_EV
contribution to the AUX_COMB event.

TIMER0_EV

R/W

Includes (1) or excludes (0) EVTOMCUFLAGS.TIMER0_EV
contribution to the AUX_COMB event.

TDC_DONE

R/W

Includes (1) or excludes (0) EVTOMCUFLAGS.TDC_DONE
contribution to the AUX_COMB event.

AUX_COMPB

R/W

Includes (1) or excludes (0) EVTOMCUFLAGS.AUX_COMPB
contribution to the AUX_COMB event.

AUX_COMPA

R/W

Includes (1) or excludes (0) EVTOMCUFLAGS.AUX_COMPA
contribution to the AUX_COMB event.

AON_WU_EV

R/W

Includes (1) or excludes (0) EVTOMCUFLAGS.AON_WU_EV
contribution to the AUX_COMB event.

31-11

1366

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.3.13 VECFLAGS Register (Offset = 34h) [reset = 0h]
VECFLAGS is shown in Figure 17-33 and described in Table 17-54.
Return to Summary Table.
Vector Flags
If a vector flag has been set and AUX_SCE is sleeping, it will wake up and execute the vector. If multiple
vectors have been set, the one with the lowest index will execute first, and the next after returning to
sleep.
During execution of a vector, the flag must be cleared, by writing a 1 to the corresponding bit in
VECFLAGSCLR.
Figure 17-33. VECFLAGS Register
31

3
VEC3
R/W0C-0h

2
VEC2
R/W0C-0h

1
VEC1
R/W0C-0h

0
VEC0
R/W0C-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

RESERVED
R-0h

Table 17-54. VECFLAGS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

VEC3

R/W0C

The vector flag is set if the edge selected VECCFG1.VEC3_POL
occurs on the event selected in VECCFG1.VEC3_EV.
The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to
VECFLAGSCLR.VEC3.

VEC2

R/W0C

The vector flag is set if the edge selected VECCFG1.VEC2_POL
occurs on the event selected in VECCFG1.VEC2_EV.
The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to
VECFLAGSCLR.VEC2.

VEC1

R/W0C

The vector flag is set if the edge selected VECCFG0.VEC1_POL
occurs on the event selected in VECCFG0.VEC1_EV.
The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to
VECFLAGSCLR.VEC1.

VEC0

R/W0C

The vector flag is set if the edge selected VECCFG0.VEC0_POL
occurs on the event selected in VECCFG0.VEC0_EV.
The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to
VECFLAGSCLR.VEC0.

31-4

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1367

AUX – Sensor Controller Registers

www.ti.com

17.7.3.14 EVTOMCUFLAGSCLR Register (Offset = 38h) [reset = 0h]
EVTOMCUFLAGSCLR is shown in Figure 17-34 and described in Table 17-55.
Return to Summary Table.
Events To MCU Domain Flags Clear
Strobes for clearing flags in EVTOMCUFLAGS.
Figure 17-34. EVTOMCUFLAGSCLR Register
31

10
ADC_IRQ

9
OBSMUX0

W-0h

8
ADC_FIFO_AL
MOST_FULL
W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

13
RESERVED

R-0h
7
ADC_DONE
W-0h

6
SMPH_AUTOT
AKE_DONE
W-0h

5
TIMER1_EV

4
TIMER0_EV

3
TDC_DONE

2
AUX_COMPB

1
AUX_COMPA

0
AON_WU_EV

W-0h

Table 17-55. EVTOMCUFLAGSCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ADC_IRQ

Writing 1 clears EVTOMCUFLAGS.ADC_IRQ.
Read value is 0.

OBSMUX0

Writing 1 clears EVTOMCUFLAGS.OBSMUX0.
Read value is 0.

ADC_FIFO_ALMOST_FU
LL

Writing 1 clears EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL.
Read value is 0.

ADC_DONE

Writing 1 clears EVTOMCUFLAGS.ADC_DONE.
Read value is 0.

SMPH_AUTOTAKE_DON W
E

Writing 1 clears [EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE.
Read value is 0.

TIMER1_EV

Writing 1 clears EVTOMCUFLAGS.TIMER1_EV.
Read value is 0.

TIMER0_EV

Writing 1 clears EVTOMCUFLAGS.TIMER0_EV.
Read value is 0.

TDC_DONE

Writing 1 clears EVTOMCUFLAGS.TDC_DONE.
Read value is 0.

AUX_COMPB

Writing 1 clears EVTOMCUFLAGS.AUX_COMPB.
Read value is 0.

AUX_COMPA

Writing 1 clears EVTOMCUFLAGS.AUX_COMPA.
Read value is 0.

AON_WU_EV

Writing 1 clears EVTOMCUFLAGS.AON_WU_EV.
Read value is 0.

31-11

1368

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.3.15 EVTOAONFLAGSCLR Register (Offset = 3Ch) [reset = 0h]
EVTOAONFLAGSCLR is shown in Figure 17-35 and described in Table 17-56.
Return to Summary Table.
Events To AON Domain Clear
Strobes for clearing flags in EVTOAONFLAGS.
Figure 17-35. EVTOAONFLAGSCLR Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

8
TIMER1_EV
W-0h

7
TIMER0_EV
W-0h

6
TDC_DONE
W-0h

5
ADC_DONE
W-0h

4
AUX_COMPB
W-0h

3
AUX_COMPA
W-0h

2
SWEV2
W-0h

1
SWEV1
W-0h

0
SWEV0
W-0h

Table 17-56. EVTOAONFLAGSCLR Register Field Descriptions
Field

Type

Reset

Description

31-9

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TIMER1_EV

Writing 1 clears EVTOAONFLAGS.TIMER1_EV.
Read value is 0.

TIMER0_EV

Writing 1 clears EVTOAONFLAGS.TIMER0_EV.
Read value is 0.

TDC_DONE

Writing 1 clears EVTOAONFLAGS.TDC_DONE.
Read value is 0.

ADC_DONE

Writing 1 clears EVTOAONFLAGS.ADC_DONE.
Read value is 0.

AUX_COMPB

Writing 1 clears EVTOAONFLAGS.AUX_COMPB.
Read value is 0.

AUX_COMPA

Writing 1 clears EVTOAONFLAGS.AUX_COMPA.
Read value is 0.

SWEV2

Writing 1 clears EVTOAONFLAGS.SWEV2.
Read value is 0.

SWEV1

Writing 1 clears EVTOAONFLAGS.SWEV1.
Read value is 0.

SWEV0

Writing 1 clears EVTOAONFLAGS.SWEV0.
Read value is 0.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1369

AUX – Sensor Controller Registers

www.ti.com

17.7.3.16 VECFLAGSCLR Register (Offset = 40h) [reset = 0h]
VECFLAGSCLR is shown in Figure 17-36 and described in Table 17-57.
Return to Summary Table.
Vector Flags Clear
Strobes for clearing flags in VECFLAGS.
Figure 17-36. VECFLAGSCLR Register
31

3
VEC3
W-0h

2
VEC2
W-0h

1
VEC1
W-0h

0
VEC0
W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

RESERVED
R-0h

Table 17-57. VECFLAGSCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

VEC3

Writing 1 clears VECFLAGS.VEC3.
Read value is 0.

VEC2

Writing 1 clears VECFLAGS.VEC2.
Read value is 0.

VEC1

Writing 1 clears VECFLAGS.VEC1.
Read value is 0.

VEC0

Writing 1 clears VECFLAGS.VEC0.
Read value is 0.

31-4

17.7.4 AUX_SMPH Registers
Table 17-58 lists the memory-mapped registers for the AUX_SMPH. All register offset addresses not listed
in Table 17-58 should be considered as reserved locations and the register contents should not be
modified.
Table 17-58. AUX_SMPH Registers
Offset

1370

Acronym

Section

SMPH0

Semaphore 0

Section 17.7.4.1

SMPH1

Semaphore 1

Section 17.7.4.2

SMPH2

Semaphore 2

Section 17.7.4.3

SMPH3

Semaphore 3

Section 17.7.4.4

10h

SMPH4

Semaphore 4

Section 17.7.4.5

14h

SMPH5

Semaphore 5

Section 17.7.4.6

18h

SMPH6

Semaphore 6

Section 17.7.4.7

1Ch

SMPH7

Semaphore 7

Section 17.7.4.8

20h

AUTOTAKE

Sticky Request For Single Semaphore

Section 17.7.4.9

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.4.1 SMPH0 Register (Offset = 0h) [reset = 1h]
SMPH0 is shown in Figure 17-37 and described in Table 17-59.
Return to Summary Table.
Semaphore 0
Figure 17-37. SMPH0 Register
31

0
STAT
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-59. SMPH0 Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STAT

R/W

Status when reading:
0: Semaphore was already taken
1: Semaphore was available and hence taken by this read access
Reading the register causes it to change value to 0. Releasing the
semaphore is done by writing 1

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1371

AUX – Sensor Controller Registers

www.ti.com

17.7.4.2 SMPH1 Register (Offset = 4h) [reset = 1h]
SMPH1 is shown in Figure 17-38 and described in Table 17-60.
Return to Summary Table.
Semaphore 1
Figure 17-38. SMPH1 Register
31

0
STAT
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-60. SMPH1 Register Field Descriptions
Bit
31-1
0

1372

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STAT

R/W

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.4.3 SMPH2 Register (Offset = 8h) [reset = 1h]
SMPH2 is shown in Figure 17-39 and described in Table 17-61.
Return to Summary Table.
Semaphore 2
Figure 17-39. SMPH2 Register
31

0
STAT
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-61. SMPH2 Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STAT

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1373

AUX – Sensor Controller Registers

www.ti.com

17.7.4.4 SMPH3 Register (Offset = Ch) [reset = 1h]
SMPH3 is shown in Figure 17-40 and described in Table 17-62.
Return to Summary Table.
Semaphore 3
Figure 17-40. SMPH3 Register
31

0
STAT
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-62. SMPH3 Register Field Descriptions
Bit
31-1
0

1374

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STAT

R/W

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.4.5 SMPH4 Register (Offset = 10h) [reset = 1h]
SMPH4 is shown in Figure 17-41 and described in Table 17-63.
Return to Summary Table.
Semaphore 4
Figure 17-41. SMPH4 Register
31

0
STAT
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-63. SMPH4 Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STAT

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1375

AUX – Sensor Controller Registers

www.ti.com

17.7.4.6 SMPH5 Register (Offset = 14h) [reset = 1h]
SMPH5 is shown in Figure 17-42 and described in Table 17-64.
Return to Summary Table.
Semaphore 5
Figure 17-42. SMPH5 Register
31

0
STAT
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-64. SMPH5 Register Field Descriptions
Bit
31-1
0

1376

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STAT

R/W

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.4.7 SMPH6 Register (Offset = 18h) [reset = 1h]
SMPH6 is shown in Figure 17-43 and described in Table 17-65.
Return to Summary Table.
Semaphore 6
Figure 17-43. SMPH6 Register
31

0
STAT
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-65. SMPH6 Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STAT

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1377

AUX – Sensor Controller Registers

www.ti.com

17.7.4.8 SMPH7 Register (Offset = 1Ch) [reset = 1h]
SMPH7 is shown in Figure 17-44 and described in Table 17-66.
Return to Summary Table.
Semaphore 7
Figure 17-44. SMPH7 Register
31

0
STAT
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-66. SMPH7 Register Field Descriptions
Bit
31-1
0

1378

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STAT

R/W

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.4.9 AUTOTAKE Register (Offset = 20h) [reset = 0h]
AUTOTAKE is shown in Figure 17-45 and described in Table 17-67.
Return to Summary Table.
Sticky Request For Single Semaphore
Figure 17-45. AUTOTAKE Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
SMPH_ID
R/W-0h

Table 17-67. AUTOTAKE Register Field Descriptions
Field

Type

Reset

Description

31-3

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

2-0

SMPH_ID

R/W

Requesting a certain semaphore is done by writing the
corresponding semaphore ID, 0x0-0x7, to SMPH_ID. The request is
sticky and once the semaphore becomes available it will be taken. At
the same time, SMPH_AUTOTAKE_DONE event is asserted. This
event is deasserted when SW releases the semaphore or a new ID
is written to SMPH_ID.
Note: SW must wait until SMPH_AUTOTAKE_DONE event is
triggered before writing a new ID to SMPH_ID . Failing to do so
might lead to permanently lost semaphores as the owners may be
unknown

17.7.5 AUX_TDC Registers
Table 17-68 lists the memory-mapped registers for the AUX_TDC. All register offset addresses not listed
in Table 17-68 should be considered as reserved locations and the register contents should not be
modified.
Table 17-68. AUX_TDC Registers
Offset

Acronym

CTL

Control

Section 17.7.5.1

Section

STAT

Status

Section 17.7.5.2

RESULT

Result

Section 17.7.5.3

SATCFG

Saturation Configuration

Section 17.7.5.4

10h

TRIGSRC

Trigger Source

Section 17.7.5.5

14h

TRIGCNT

Trigger Counter

Section 17.7.5.6

18h

TRIGCNTLOAD

Trigger Counter Load

Section 17.7.5.7

1Ch

TRIGCNTCFG

Trigger Counter Configuration

Section 17.7.5.8

20h

PRECTL

Prescaler Control

Section 17.7.5.9

24h

PRECNT

Prescaler Counter

Section 17.7.5.10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1379

AUX – Sensor Controller Registers

www.ti.com

17.7.5.1 CTL Register (Offset = 0h) [reset = 0h]
CTL is shown in Figure 17-46 and described in Table 17-69.
Return to Summary Table.
Control
Figure 17-46. CTL Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

0
CMD
W-0h

Table 17-69. CTL Register Field Descriptions
Field

Type

Reset

Description

31-2

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

CMD

TDC command strobes
0h = This command clears STAT.SAT, STAT.DONE and results.
Note: This is not needed as prerequisite for a measurement. Reliable
clear is only guaranteed from IDLE state
1h = This command makes the TDC FSM start counting
synchronously to the first rising edge that follows a required falling
edge of the start event. This guarantees an edge triggered start and
is recommended for frequency measurements. A falling edge of the
start event may be missed if the command is issued close to it in
time, but the TDC will catch later falling edges and guarantee that a
measurement starts synchronously to the rising edge of the start
event
2h = This command makes the TDC FSM start and stop counting
asynchronously. TDC measurement may start immediately if start is
high and hence it may not give precise edge to edge measurements.
Only recommended when start pulse is guaranteed to arrive at least
7 clock periods after the command
3h = This command forces the TDC back to IDLE state

1380

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.5.2 STAT Register (Offset = 4h) [reset = 6h]
STAT is shown in Figure 17-47 and described in Table 17-70.
Return to Summary Table.
Status
Figure 17-47. STAT Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

7
SAT
R-0h

6
DONE
R-0h

3
STATE
R-6h

Table 17-70. STAT Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SAT

Saturation flag for TDC measurement
0: Conversion has not saturated
1: Conversion stopped due to saturation
This field is cleared when starting new measurement or setting
CTL.CMD to CLR_RESULT

DONE

Measurement complete flag
0: Measurement not yet complete
1: Measurement complete
This field is cleared when starting new measurement or setting
CTL.CMD to CLR_RESULT

5-0

STATE

TDC internal state machine status
0h = Current state is TDC_STATE_WAIT_START
4h = Current state is TDC_STATE_WAIT_STARTSTOPCNTEN
6h = Current state is TDC_STATE_IDLE
7h = Current state is TDC_STATE_CLRCNT
8h = Current state is TDC_STATE_WAIT_STOP
Ch = Current state is TDC_STATE_WAIT_STOPCNTDOWN
Eh = Current state is TDC_STATE_GETRESULTS
Fh = Current state is TDC_STATE_POR
16h = Current state is TDC_STATE_WAIT_CLRCNT_DONE
1Eh = Current state is TDC_WAIT_STARTFALL
2Eh = Current state is TDC_FORCESTOP

31-8

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1381

AUX – Sensor Controller Registers

www.ti.com

17.7.5.3 RESULT Register (Offset = 8h) [reset = 2h]
RESULT is shown in Figure 17-48 and described in Table 17-71.
Return to Summary Table.
Result
Result of last TDC conversion
Figure 17-48. RESULT Register
31

28
27
RESERVED
R-0h
12

20
VALUE
R-2h

VALUE
R-2h

Table 17-71. RESULT Register Field Descriptions
Field

Type

Reset

Description

31-25

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

24-0

VALUE

Result of the TDC conversion. The result is in clock edges of the
clock selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both
rising and falling edges are counted.
When saturating the result is slightly higher than the saturation limit,
since it takes a non-zero time to stop the measurement. The highest
saturation limit is 24 bits (see SATCFG.LIMIT) so maximum value of
VALUE is hence slightly above 224.

1382

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.5.4 SATCFG Register (Offset = Ch) [reset = Fh]
SATCFG is shown in Figure 17-49 and described in Table 17-72.
Return to Summary Table.
Saturation Configuration
Figure 17-49. SATCFG Register
31

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

1
LIMIT
R/W-Fh

Table 17-72. SATCFG Register Field Descriptions
Field

Type

Reset

Description

31-4

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-0

LIMIT

R/W

Select when the TDC times out. Values not enumerated are not
supported
3h = Result bit 12 : TDC saturates and stops when
RESULT.VALUE[12] is set. The flag STAT.SAT is set when the timer
saturates.
4h = Result bit 13 : TDC saturates and stops when
RESULT.VALUE[13] is set. The flag STAT.SAT is set when the timer
saturates.
5h = Result bit 14 : TDC saturates and stops when
RESULT.VALUE[14] is set. The flag STAT.SAT is set when the timer
saturates.
6h = Result bit 15 : TDC saturates and stops when
RESULT.VALUE[15] is set. The flag STAT.SAT is set when the timer
saturates.
7h = Result bit 16 : TDC saturates and stops when
RESULT.VALUE[16] is set. The flag STAT.SAT is set when the timer
saturates.
8h = Result bit 17 : TDC saturates and stops when
RESULT.VALUE[17] is set. The flag STAT.SAT is set when the timer
saturates.
9h = Result bit 18 : TDC saturates and stops when
RESULT.VALUE[18] is set. The flag STAT.SAT is set when the timer
saturates.
Ah = Result bit 19 : TDC saturates and stops when
RESULT.VALUE[19] is set. The flag STAT.SAT is set when the timer
saturates.
Bh = Result bit 20 : TDC saturates and stops when
RESULT.VALUE[20] is set. The flag STAT.SAT is set when the timer
saturates.
Ch = Result bit 21 : TDC saturates and stops when
RESULT.VALUE[21] is set. The flag STAT.SAT is set when the timer
saturates.
Dh = Result bit 22 : TDC saturates and stops when
RESULT.VALUE[22] is set. The flag STAT.SAT is set when the timer
saturates.
Eh = Result bit 23 : TDC saturates and stops when
RESULT.VALUE[23] is set. The flag STAT.SAT is set when the timer
saturates.
Fh = Result bit 24 : TDC saturates and stops when
RESULT.VALUE[24] is set. The flag STAT.SAT is set when the timer
saturates.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1383

AUX – Sensor Controller Registers

www.ti.com

17.7.5.5 TRIGSRC Register (Offset = 10h) [reset = 0h]
TRIGSRC is shown in Figure 17-50 and described in Table 17-73.
Return to Summary Table.
Trigger Source
TDC start/stop trigger source selection
Figure 17-50. TRIGSRC Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

13
STOP_POL
R/W-0h

10
STOP_SRC
R/W-0h

5
START_POL
R/W-0h

2
START_SRC
R/W-0h

RESERVED
R-0h
7
RESERVED
R-0h

Table 17-73. TRIGSRC Register Field Descriptions
Field

Type

Reset

Description

31-14

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STOP_POL

R/W

Polarity of stop signal. Note! Must not be changed if STAT.STATE is
not IDLE
0h = TDC stops when high level is detected
1h = TDC stops when low level is detected

1384

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

Table 17-73. TRIGSRC Register Field Descriptions (continued)
Field

Type

Reset

Description

12-8

Bit

STOP_SRC

R/W

Selects the asynchronous stop signal Note! Must not be changed if
STAT.STATE is not IDLE
0h = Selects AON_RTC_CH2
1h = Selects AUX_COMPA
2h = Selects AUX_COMPB
3h = Selects ISRC_RESET
4h = Selects TIMER0_EV
5h = Selects TIMER1_EV
6h = Selects SMPH_AUTOTAKE_DONE
7h = Selects ADC_DONE
8h = Selects ADC_FIFO_ALMOST_FULL
9h = Selects OBSMUX0
Ah = Selects OBSMUX1
Bh = Selects AON_SW
Ch = Selects AON_PROG_WU
Dh = Selects AUXIO0
Eh = Selects AUXIO1
Fh = Selects AUXIO2
10h = Selects AUXIO3
11h = Selects AUXIO4
12h = Selects AUXIO5
13h = Selects AUXIO6
14h = Selects AUXIO7
15h = Selects AUXIO8
16h = Selects AUXIO9
17h = Selects AUXIO10
18h = Selects AUXIO11
19h = Selects AUXIO12
1Ah = Selects AUXIO13
1Bh = Selects AUXIO14
1Ch = Selects AUXIO15
1Dh = Selects ACLK_REF
1Eh = Selects MCU_EV
1Fh = Selects TDC_PRE

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

START_POL

R/W

Polarity of start signal. Note! Must not be changed if STAT.STATE is
not IDLE
0h = TDC starts when high level is detected
1h = TDC starts when low level is detected

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1385

AUX – Sensor Controller Registers

www.ti.com

Table 17-73. TRIGSRC Register Field Descriptions (continued)

1386

Bit

Field

Type

Reset

Description

4-0

START_SRC

R/W

Selects the asynchronous start signal Note! Must not be changed if
STAT.STATE is not IDLE
0h = Selects AON_RTC_CH2
1h = Selects AUX_COMPA
2h = Selects AUX_COMPB
3h = Selects ISRC_RESET
4h = Selects TIMER0_EV
5h = Selects TIMER1_EV
6h = Selects SMPH_AUTOTAKE_DONE
7h = Selects ADC_DONE
8h = Selects ADC_FIFO_ALMOST_FULL
9h = Selects OBSMUX0
Ah = Selects OBSMUX1
Bh = Selects AON_SW
Ch = Selects AON_PROG_WU
Dh = Selects AUXIO0
Eh = Selects AUXIO1
Fh = Selects AUXIO2
10h = Selects AUXIO3
11h = Selects AUXIO4
12h = Selects AUXIO5
13h = Selects AUXIO6
14h = Selects AUXIO7
15h = Selects AUXIO8
16h = Selects AUXIO9
17h = Selects AUXIO10
18h = Selects AUXIO11
19h = Selects AUXIO12
1Ah = Selects AUXIO13
1Bh = Selects AUXIO14
1Ch = Selects AUXIO15
1Dh = Selects ACLK_REF
1Eh = Selects MCU_EV
1Fh = Selects TDC_PRE

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.5.6 TRIGCNT Register (Offset = 14h) [reset = 0h]
TRIGCNT is shown in Figure 17-51 and described in Table 17-74.
Return to Summary Table.
Trigger Counter
Stop counter status/control of TDC
Figure 17-51. TRIGCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
CNT
R/W-0h

Table 17-74. TRIGCNT Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

CNT

R/W

Remaining number of stop events that will be ignored. Writing to this
register updates the value. The CNT will be loaded with the value of
TRIGCNTLOAD.CNT at the start of every measurement.
When the stop counter is enabled the first CNT-1 stop events is
ignored after which the TDC will stop measurement on event number
CNT
Note! Must not be changed if STAT.STATE is not IDLE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1387

AUX – Sensor Controller Registers

www.ti.com

17.7.5.7 TRIGCNTLOAD Register (Offset = 18h) [reset = 0h]
TRIGCNTLOAD is shown in Figure 17-52 and described in Table 17-75.
Return to Summary Table.
Trigger Counter Load
Stop counter control of TDC
Figure 17-52. TRIGCNTLOAD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
CNT
R/W-0h

Table 17-75. TRIGCNTLOAD Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

CNT

R/W

Selects the number of stop events that will be ignored by the TDC.
This can be used to measure multiple periods of a clock signal. The
value written to this field is loaded into the stop counter at the start of
each measurement.
Note! Both values 0 and 1 will make the TDC stop on the first event
after the start event
Note! Must not be changed if STAT.STATE is not IDLE

1388

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.5.8 TRIGCNTCFG Register (Offset = 1Ch) [reset = 0h]
TRIGCNTCFG is shown in Figure 17-53 and described in Table 17-76.
Return to Summary Table.
Trigger Counter Configuration
Figure 17-53. TRIGCNTCFG Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
EN
R/W0h

Table 17-76. TRIGCNTCFG Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Stop counter enable
0: Stop counter is disabled
1: Stop counter is enabled

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1389

AUX – Sensor Controller Registers

www.ti.com

17.7.5.9 PRECTL Register (Offset = 20h) [reset = 1Fh]
PRECTL is shown in Figure 17-54 and described in Table 17-77.
Return to Summary Table.
Prescaler Control
The prescaler can be used to count events that are faster than the AUX clock speed. It can be used
standalone or as a start/stop source for the TDC by configuring TRIGSRC.START_SRC and
TRIGSRC.STOP_SRC to TDC_PRE. When counting fast signals with the TDC that are faster than 1/10th
of the clock frequency of AUX it is recommended to use the prescaler.
Figure 17-54. PRECTL Register
31

2
SRC
R/W-1Fh

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

7
RESET_N
R/W-0h

6
RATIO
R/W-0h

5
RESERVED
R-0h

Table 17-77. PRECTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RESET_N

R/W

Prescaler reset control
0: Prescaler is held in reset
1: Prescaler is not held in reset

RATIO

R/W

Prescaler ratio. This controls how often an event is generated on the
TDC_PRE line. After the prescaler is reset the event output
TDC_PRE is 0.
0h = Prescaler divides by 16. A rising edge on the output is
generated for every 16 rising edges of the input (the output toggles
on every 8th rising edge of the input).
1h = Prescaler divides by 64. A rising edge on the output is
generated for every 64 rising edges of the input (the output toggles
on every 32th rising edge of the input). .

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-8

1390

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

Table 17-77. PRECTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

4-0

SRC

R/W

1Fh

Selects event for prescaler to use as input
Note! Only change when prescaler is in reset
0h = 0
1h = 0
2h = 0
3h = 0
4h = 0
5h = 0
6h = 0
7h = 0
8h = 0
9h = 0
Ah = 0
Bh = 0
Ch = 0
Dh = 0
Eh = 0
Fh = 0
10h = 0
11h = 0
12h = 0
13h = 0
14h = 0
15h = 0
16h = 0
17h = 0
18h = 0
19h = 0
1Ah = 0
1Bh = 0
1Ch = 0
1Dh = 0
1Eh = 0
1Fh = 0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1391

AUX – Sensor Controller Registers

www.ti.com

17.7.5.10 PRECNT Register (Offset = 24h) [reset = 0h]
PRECNT is shown in Figure 17-55 and described in Table 17-78.
Return to Summary Table.
Prescaler Counter
Value of prescaler counter
Figure 17-55. PRECNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
CNT
R/W-0h

Table 17-78. PRECNT Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

CNT

R/W

Writing to this register will latch the contents of the 16 bit prescaler
counter (The value written is don't care).
Reading will return the latched value.

17.7.6 AUX_TIMER Registers
Table 17-79 lists the memory-mapped registers for the AUX_TIMER. All register offset addresses not
listed in Table 17-79 should be considered as reserved locations and the register contents should not be
modified.
Table 17-79. AUX_TIMER Registers
Offset

1392

Acronym

T0CFG

Timer 0 Configuration

Section 17.7.6.1

Section

T1CFG

Timer 1 Configuration

Section 17.7.6.2

T0CTL

Timer 0 Control

Section 17.7.6.3

T0TARGET

Timer 0 Target

Section 17.7.6.4

10h

T1TARGET

Timer 1 Target

Section 17.7.6.5

14h

T1CTL

Timer 1 Control

Section 17.7.6.6

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.6.1 T0CFG Register (Offset = 0h) [reset = 0h]
T0CFG is shown in Figure 17-56 and described in Table 17-80.
Return to Summary Table.
Timer 0 Configuration
Figure 17-56. T0CFG Register
31

10
TICK_SRC

1
MODE
R/W-0h

0
RELOAD
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

13
TICK_SRC_PO
L
R/W-0h

RESERVED
R-0h
7

R/W-0h

PRE
R/W-0h

2
RESERVED
R-0h

Table 17-80. T0CFG Register Field Descriptions
Bit
31-14
13

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TICK_SRC_POL

R/W

Source count polarity for timer 0
0h = Count on rising edges of TICK_SRC
1h = Count on falling edges of TICK_SRC

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1393

AUX – Sensor Controller Registers

www.ti.com

Table 17-80. T0CFG Register Field Descriptions (continued)
Field

Type

Reset

Description

12-8

Bit

TICK_SRC

R/W

Selected tick source for timer 0
0h = Selects RTC_CH2_EV
1h = Selects AUX_COMPA
2h = Selects AUX_COMPB
3h = Selects TDC_DONE
5h = Selects TIMER1_EV
6h = Selects SMPH_AUTOTAKE_DONE
7h = Selects ADC_DONE
8h = Selects RTC_4KHZ
9h = Selects OBSMUX0
Ah = Selects OBSMUX1
Bh = Selects AON_SW
Ch = Selects AON_PROG_WU
Dh = Selects AUXIO0
Eh = Selects AUXIO1
Fh = Selects AUXIO2
10h = Selects AUXIO3
11h = Selects AUXIO4
12h = Selects AUXIO5
13h = Selects AUXIO6
14h = Selects AUXIO7
15h = Selects AUXIO8
16h = Selects AUXIO9
17h = Selects AUXIO10
18h = Selects AUXIO11
19h = Selects AUXIO12
1Ah = Selects AUXIO13
1Bh = Selects AUXIO14
1Ch = Selects AUXIO15
1Dh = Selects ACLK_REF
1Eh = Selects MCU_EV
1Fh = Selects ADC_IRQ

7-4

PRE

R/W

Prescaler division ratio is 2PRE

3-2

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MODE

R/W

Timer 0 mode
0h = Timer 0 increments on every 2PRE edges of AUX clock
1h = Timer 0 counter increments only on edges of the event set by
TICK_SRC. The events are divided by the PRE setting.

RELOAD

R/W

Timer 0 reload setting
0h = Timer has to be restarted manually
1h = Timer is automatically restarted when target is reached

1394

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.6.2 T1CFG Register (Offset = 4h) [reset = 0h]
T1CFG is shown in Figure 17-57 and described in Table 17-81.
Return to Summary Table.
Timer 1 Configuration
Figure 17-57. T1CFG Register
31

10
TICK_SRC

1
MODE
R/W-0h

0
RELOAD
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

13
TICK_SRC_PO
L
R/W-0h

RESERVED
R-0h
7

R/W-0h

PRE
R/W-0h

2
RESERVED
R-0h

Table 17-81. T1CFG Register Field Descriptions
Bit
31-14
13

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TICK_SRC_POL

R/W

Source count polarity for timer 1
0h = Count on rising edges of TICK_SRC
1h = Count on falling edges of TICK_SRC

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1395

AUX – Sensor Controller Registers

www.ti.com

Table 17-81. T1CFG Register Field Descriptions (continued)
Field

Type

Reset

Description

12-8

Bit

TICK_SRC

R/W

Selected tick source for timer 1
0h = Selects RTC_CH2_EV
1h = Selects AUX_COMPA
2h = Selects AUX_COMPB
3h = Selects TDC_DONE
4h = Selects TIMER0_EV
6h = Selects SMPH_AUTOTAKE_DONE
7h = Selects ADC_DONE
8h = Selects RTC_4KHZ
9h = Selects OBSMUX0
Ah = Selects OBSMUX1
Bh = Selects AON_SW
Ch = Selects AON_PROG_WU
Dh = Selects AUXIO0
Eh = Selects AUXIO1
Fh = Selects AUXIO2
10h = Selects AUXIO3
11h = Selects AUXIO4
12h = Selects AUXIO5
13h = Selects AUXIO6
14h = Selects AUXIO7
15h = Selects AUXIO8
16h = Selects AUXIO9
17h = Selects AUXIO10
18h = Selects AUXIO11
19h = Selects AUXIO12
1Ah = Selects AUXIO13
1Bh = Selects AUXIO14
1Ch = Selects AUXIO15
1Dh = Selects ACLK_REF
1Eh = Selects MCU_EV
1Fh = Selects ADC_IRQ

7-4

PRE

R/W

Prescaler division ratio is 2PRE

3-2

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MODE

R/W

Timer 1 mode
0h = Timer 1 increments on every 2PRE edges of AUX clock
1h = Timer 1 counter increments only on edges of the event set by
TICK_SRC. The events are divided by the PRE setting.

RELOAD

R/W

Timer 1 reload setting
0h = Timer has to be restarted manually
1h = Timer is automatically restarted when target is reached

1396

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.6.3 T0CTL Register (Offset = 8h) [reset = 0h]
T0CTL is shown in Figure 17-58 and described in Table 17-82.
Return to Summary Table.
Timer 0 Control
Run control/status for timer 0
Figure 17-58. T0CTL Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
EN
R/W0h

Table 17-82. T0CTL Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Timer 0 run enable control. The counter restarts when enabling the
timer. If T0CFG.RELOAD = 0, the timer is automatically disabled
when reaching T0TARGET.VALUE
0: Disable timer 0
1: Enable timer 0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1397

AUX – Sensor Controller Registers

www.ti.com

17.7.6.4 T0TARGET Register (Offset = Ch) [reset = 0h]
T0TARGET is shown in Figure 17-59 and described in Table 17-83.
Return to Summary Table.
Timer 0 Target
Target counter value for timer 0
Figure 17-59. T0TARGET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
VALUE
R/W-0h

Table 17-83. T0TARGET Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

VALUE

R/W

Timer 0 counts from 0 to VALUE. Then gives an event and restarts if
configured to do to so in the T0CFG.RELOAD setting. If VALUE is
changed while timer 0 is running so that the count becomes higher
than VALUE timer 0 will also restart if configured to do so.
If T0CFG.MODE=0,no prescaler is used, and VALUE equals 1, the
TIMER0_EV event line will be always set

1398

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.6.5 T1TARGET Register (Offset = 10h) [reset = 0h]
T1TARGET is shown in Figure 17-60 and described in Table 17-84.
Return to Summary Table.
Timer 1 Target
Target Counter Value Timer 1
Figure 17-60. T1TARGET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
VALUE
R/W-0h

Table 17-84. T1TARGET Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

VALUE

R/W

Timer 1 counts from 0 to VALUE. Then gives an event and restarts if
configured to do to so in the T1CFG.RELOAD setting. If VALUE is
changed while timer 1 is running so that the count becomes higher
than VALUE timer 1 will also restart if configured to do so.
If T1CFG.MODE=0,no prescaler is used, and VALUE equals 1, the
TIMER1_EV event line will be always set

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1399

AUX – Sensor Controller Registers

www.ti.com

17.7.6.6 T1CTL Register (Offset = 14h) [reset = 0h]
T1CTL is shown in Figure 17-61 and described in Table 17-85.
Return to Summary Table.
Timer 1 Control
Run Control/Status For Timer 1
Figure 17-61. T1CTL Register
31

24
23
RESERVED
R-0h

0
EN
R/W0h

8
7
RESERVED
R-0h

Table 17-85. T1CTL Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Timer 1 run enable control. The counter restarts when enabling the
timer. If T1CFG.RELOAD = 0, the timer is automatically disabled
when reaching T1TARGET.VALUE
0: Disable timer 1
1: Enable timer 1

17.7.7 AUX_WUC Registers
Table 17-86 lists the memory-mapped registers for the AUX_WUC. All register offset addresses not listed
in Table 17-86 should be considered as reserved locations and the register contents should not be
modified.
Table 17-86. AUX_WUC Registers
Offset

1400

Acronym

Section

MODCLKEN0

Module Clock Enable

Section 17.7.7.1

PWROFFREQ

Power Off Request

Section 17.7.7.2

PWRDWNREQ

Power Down Request

Section 17.7.7.3

PWRDWNACK

Power Down Acknowledgment

Section 17.7.7.4

10h

CLKLFREQ

Low Frequency Clock Request

Section 17.7.7.5

14h

CLKLFACK

Low Frequency Clock Acknowledgment

Section 17.7.7.6

28h

WUEVFLAGS

Wake-up Event Flags

Section 17.7.7.7

2Ch

WUEVCLR

Wake-up Event Clear

Section 17.7.7.8

30h

ADCCLKCTL

ADC Clock Control

Section 17.7.7.9

34h

TDCCLKCTL

TDC Clock Control

Section 17.7.7.10

38h

REFCLKCTL

Reference Clock Control

Section 17.7.7.11

3Ch

RTCSUBSECINC0

Real Time Counter Sub Second Increment 0

Section 17.7.7.12

40h

RTCSUBSECINC1

Real Time Counter Sub Second Increment 1

Section 17.7.7.13

44h

RTCSUBSECINCCTL

Real Time Counter Sub Second Increment Control

Section 17.7.7.14

48h

MCUBUSCTL

MCU Bus Control

Section 17.7.7.15

4Ch

MCUBUSSTAT

MCU Bus Status

Section 17.7.7.16

50h

AONCTLSTAT

AON Domain Control Status

Section 17.7.7.17

54h

AUXIOLATCH

AUX Input Output Latch

Section 17.7.7.18

5Ch

MODCLKEN1

Module Clock Enable 1

Section 17.7.7.19

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.7.1 MODCLKEN0 Register (Offset = 0h) [reset = 0h]
MODCLKEN0 is shown in Figure 17-62 and described in Table 17-87.
Return to Summary Table.
Module Clock Enable
Clock enable for each module in the AUX domain
For use by the system CPU
The settings in this register are OR'ed with the corresponding settings in MODCLKEN1. This allows the
system CPU and AUX_SCE to request clocks independently. Settings take effect immediately.
Figure 17-62. MODCLKEN0 Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

7
AUX_ADI4
R/W-0h

6
AUX_DDI0_OS
C
R/W-0h

5
TDC

4
ANAIF

3
TIMER

2
AIODIO1

1
AIODIO0

0
SMPH

R/W-0h

Table 17-87. MODCLKEN0 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AUX_ADI4

R/W

Enables (1) or disables (0) clock for AUX_ADI4.
0h = System CPU has not requested clock for AUX_ADI4
1h = System CPU has requested clock for AUX_ADI4

AUX_DDI0_OSC

R/W

Enables (1) or disables (0) clock for AUX_DDI0_OSC.
0h = System CPU has not requested clock for AUX_DDI0_OSC
1h = System CPU has requested clock for AUX_DDI0_OSC

TDC

R/W

Enables (1) or disables (0) clock for AUX_TDCIF.
Note that the TDC counter and reference clock sources must be
requested separately using TDCCLKCTL and REFCLKCTL,
respectively.
0h = System CPU has not requested clock for TDC
1h = System CPU has requested clock for TDC

ANAIF

R/W

Enables (1) or disables (0) clock for AUX_ANAIF.
Note that the ADC internal clock must be requested separately using
ADCCLKCTL.
0h = System CPU has not requested clock for ANAIF
1h = System CPU has requested clock for ANAIF

TIMER

R/W

Enables (1) or disables (0) clock for AUX_TIMER.
0h = System CPU has not requested clock for TIMER
1h = System CPU has requested clock for TIMER

AIODIO1

R/W

Enables (1) or disables (0) clock for AUX_AIODIO1.
0h = System CPU has not requested clock for AIODIO1
1h = System CPU has requested clock for AIODIO1

31-8

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1401

AUX – Sensor Controller Registers

www.ti.com

Table 17-87. MODCLKEN0 Register Field Descriptions (continued)
Bit

1402

Field

Type

Reset

Description

AIODIO0

R/W

Enables (1) or disables (0) clock for AUX_AIODIO0.
0h = System CPU has not requested clock for AIODIO0
1h = System CPU has requested clock for AIODIO0

SMPH

R/W

Enables (1) or disables (0) clock for AUX_SMPH.
0h = System CPU has not requested clock for SMPH
1h = System CPU has requested clock for SMPH

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.7.2 PWROFFREQ Register (Offset = 4h) [reset = 0h]
PWROFFREQ is shown in Figure 17-63 and described in Table 17-88.
Return to Summary Table.
Power Off Request
Requests power off request for the AUX domain. When powered off, the power supply and clock is
disabled. This may only be used when taking the entire device into shutdown mode (i.e. with full device
reset when resuming operation).
Power off is prevented if AON_WUC:AUXCTL.AUX_FORCE_ON has been set, or if
MCUBUSCTL.DISCONNECT_REQ has been cleared.
Figure 17-63. PWROFFREQ Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
REQ
R/W0h

Table 17-88. PWROFFREQ Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

REQ

R/W

Power off request
0: No action
1: Request to power down AUX. Once set, this bit shall not be
cleared. The bit will be reset again when AUX is powered up again.
The request will only happen if AONCTLSTAT.AUX_FORCE_ON = 0
and MCUBUSSTAT.DISCONNECTED=1.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1403

AUX – Sensor Controller Registers

www.ti.com

17.7.7.3 PWRDWNREQ Register (Offset = 8h) [reset = 0h]
PWRDWNREQ is shown in Figure 17-64 and described in Table 17-89.
Return to Summary Table.
Power Down Request
Request from AUX for system to enter power down. When system is in power down there is limited
current supply available and the clock source is set by AON_WUC:AUXCLK.PWR_DWN_SRC
Figure 17-64. PWRDWNREQ Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
REQ
R/W0h

Table 17-89. PWRDWNREQ Register Field Descriptions
Bit
31-1
0

1404

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

REQ

R/W

Power down request
0: Request for system to be in active mode
1: Request for system to be in power down mode
When REQ is 1 one shall assume that the system is in power down,
and that current supply is limited. When setting REQ = 0, one shall
assume that the system is in power down until PWRDWNACK.ACK
=0

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.7.4 PWRDWNACK Register (Offset = Ch) [reset = 0h]
PWRDWNACK is shown in Figure 17-65 and described in Table 17-90.
Return to Summary Table.
Power Down Acknowledgment
Figure 17-65. PWRDWNACK Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ACK
R-0h

Table 17-90. PWRDWNACK Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ACK

Power down acknowledgment. Indicates whether the power down
request given by PWRDWNREQ.REQ is captured by the AON
domain or not
0: AUX can assume that the system is in active mode
1: The request for power down is acknowledged and the AUX must
act like the system is in power down mode and power supply is
limited
The system CPU cannot use this bit since the bus bridge between
MCU domain and AUX domain is always disconnected when this bit
is set. For AUX_SCE use only

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1405

AUX – Sensor Controller Registers

www.ti.com

17.7.7.5 CLKLFREQ Register (Offset = 10h) [reset = 0h]
CLKLFREQ is shown in Figure 17-66 and described in Table 17-91.
Return to Summary Table.
Low Frequency Clock Request
Figure 17-66. CLKLFREQ Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
REQ
R/W0h

Table 17-91. CLKLFREQ Register Field Descriptions
Bit
31-1
0

1406

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

REQ

R/W

Low frequency request
0: Request clock frequency to be controlled by AON_WUC:AUXCLK
and the system state
1: Request low frequency clock SCLK_LF as the clock source for
AUX
This bit must not be modified unless CLKLFACK.ACK matches the
current value

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.7.6 CLKLFACK Register (Offset = 14h) [reset = 0h]
CLKLFACK is shown in Figure 17-67 and described in Table 17-92.
Return to Summary Table.
Low Frequency Clock Acknowledgment
Figure 17-67. CLKLFACK Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
ACK
R-0h

Table 17-92. CLKLFACK Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ACK

Acknowledgment of CLKLFREQ.REQ
0: Acknowledgement that clock frequency is controlled by
AON_WUC:AUXCLK and the system state
1: Acknowledgement that the low frequency clock SCLK_LF is the
clock source for AUX

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1407

AUX – Sensor Controller Registers

www.ti.com

17.7.7.7 WUEVFLAGS Register (Offset = 28h) [reset = 0h]
WUEVFLAGS is shown in Figure 17-68 and described in Table 17-93.
Return to Summary Table.
Wake-up Event Flags
Status of wake-up events from the AON domain
The event flags are cleared by setting the corresponding bits in WUEVCLR
Figure 17-68. WUEVFLAGS Register
31

2
AON_RTC_CH
2
R-0h

1
AON_SW

0
AON_PROG_
WU
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED

R-0h

Table 17-93. WUEVFLAGS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AON_RTC_CH2

Indicates pending event from AON_RTC_CH2 compare. Note that
this flag will be set whenever the AON_RTC_CH2 event happens,
but that does not mean that this event is a wake-up event. To make
the AON_RTC_CH2 a wake-up event for the AUX domain configure
it as a wake-up event in AON_EVENT:AUXWUSEL.WU0_EV,
AON_EVENT:AUXWUSEL.WU1_EV or
AON_EVENT:AUXWUSEL.WU2_EV.

AON_SW

Indicates pending event triggered by system CPU writing a 1 to
AON_WUC:AUXCTL.SWEV.

AON_PROG_WU

Indicates pending event triggered by the sources selected in
AON_EVENT:AUXWUSEL.WU0_EV,
AON_EVENT:AUXWUSEL.WU1_EV and
AON_EVENT:AUXWUSEL.WU2_EV.

31-3

1408

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.7.8 WUEVCLR Register (Offset = 2Ch) [reset = 0h]
WUEVCLR is shown in Figure 17-69 and described in Table 17-94.
Return to Summary Table.
Wake-up Event Clear
Clears wake-up events from the AON domain
Figure 17-69. WUEVCLR Register
31

2
AON_RTC_CH
2
R/W-0h

1
AON_SW

0
AON_PROG_
WU
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED

R-0h

R/W-0h

Table 17-94. WUEVCLR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AON_RTC_CH2

R/W

Set to clear the WUEVFLAGS.AON_RTC_CH2 wake-up event. Note
that if RTC channel 2 is also set as source for AON_PROG_WU this
field can also clear WUEVFLAGS.AON_PROG_WU
This bit must remain set until WUEVFLAGS.AON_RTC_CH2 returns
to 0.

AON_SW

R/W

Set to clear the WUEVFLAGS.AON_SW wake-up event.
This bit must remain set until WUEVFLAGS.AON_SW returns to 0.

AON_PROG_WU

R/W

Set to clear the WUEVFLAGS.AON_PROG_WU wake-up event.
Note only if an IO event is selected as wake-up event, is it possible
to use this field to clear the source. Other sources cannot be cleared
using this field.
The IO pin needs to be assigned to AUX in the IOC and the input
enable for the pin needs to be set in AIODIO0 or AIODIO1 for this
clearing to take effect.
This bit must remain set until WUEVFLAGS.AON_PROG_WU
returns to 0.

31-3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1409

AUX – Sensor Controller Registers

www.ti.com

17.7.7.9 ADCCLKCTL Register (Offset = 30h) [reset = 0h]
ADCCLKCTL is shown in Figure 17-70 and described in Table 17-95.
Return to Summary Table.
ADC Clock Control
Controls the ADC internal clock
Note that the ADC command and data interface requires MODCLKEN0.ANAIF or MODCLKEN1.ANAIF
also to be set
Figure 17-70. ADCCLKCTL Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
ACK
R-0h

0
REQ
R/W0h

Table 17-95. ADCCLKCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ACK

Acknowledges the last value written to REQ.

REQ

R/W

Enables(1) or disables (0) the ADC internal clock.
This bit must not be modified unless ACK matches the current value.

31-2

1410

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.7.10 TDCCLKCTL Register (Offset = 34h) [reset = 0h]
TDCCLKCTL is shown in Figure 17-71 and described in Table 17-96.
Return to Summary Table.
TDC Clock Control
Controls the TDC counter clock source, which steps the TDC counter value
The source of this clock is controlled by OSC_DIG:CTL0.ACLK_TDC_SRC_SEL.
Figure 17-71. TDCCLKCTL Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
ACK
R-0h

0
REQ
R/W0h

Table 17-96. TDCCLKCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ACK

Acknowledges the last value written to REQ.

REQ

R/W

Enables(1) or disables (0) the TDC counter clock source.
This bit must not be modified unless ACK matches the current value.

31-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1411

AUX – Sensor Controller Registers

www.ti.com

17.7.7.11 REFCLKCTL Register (Offset = 38h) [reset = 0h]
REFCLKCTL is shown in Figure 17-72 and described in Table 17-97.
Return to Summary Table.
Reference Clock Control
Controls the TDC reference clock source, which is to be compared against the TDC counter clock.
The source of this clock is controlled by OSC_DIG:CTL0.ACLK_REF_SRC_SEL.
Figure 17-72. REFCLKCTL Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

1
ACK
R-0h

0
REQ
R/W0h

Table 17-97. REFCLKCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ACK

Acknowledges the last value written to REQ.

REQ

R/W

Enables(1) or disables (0) the TDC reference clock source.
This bit must not be modified unless ACK matches the current value.

31-2

1412

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.7.12 RTCSUBSECINC0 Register (Offset = 3Ch) [reset = 0h]
RTCSUBSECINC0 is shown in Figure 17-73 and described in Table 17-98.
Return to Summary Table.
Real Time Counter Sub Second Increment 0
New value for the real-time counter (AON_RTC) sub-second increment value, part corresponding to
AON_RTC:SUBSECINC bits 15:0.
After setting INC15_0 and RTCSUBSECINC1.INC23_16, the value is loaded into
AON_RTC:SUBSECINC.VALUEINC by setting RTCSUBSECINCCTL.UPD_REQ.
Figure 17-73. RTCSUBSECINC0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
INC15_0
R/W-0h

Table 17-98. RTCSUBSECINC0 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

INC15_0

R/W

Bits 15:0 of the RTC sub-second increment value.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1413

AUX – Sensor Controller Registers

www.ti.com

17.7.7.13 RTCSUBSECINC1 Register (Offset = 40h) [reset = 0h]
RTCSUBSECINC1 is shown in Figure 17-74 and described in Table 17-99.
Return to Summary Table.
Real Time Counter Sub Second Increment 1
New value for the real-time counter (AON_RTC) sub-second increment value, part corresponding to
AON_RTC:SUBSECINC bits 23:16.
After setting RTCSUBSECINC0.INC15_0 and INC23_16, the value is loaded into
AON_RTC:SUBSECINC.VALUEINC by setting RTCSUBSECINCCTL.UPD_REQ.
Figure 17-74. RTCSUBSECINC1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
INC23_16
R/W-0h

Table 17-99. RTCSUBSECINC1 Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

INC23_16

R/W

Bits 23:16 of the RTC sub-second increment value.

1414

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.7.14 RTCSUBSECINCCTL Register (Offset = 44h) [reset = 0h]
RTCSUBSECINCCTL is shown in Figure 17-75 and described in Table 17-100.
Return to Summary Table.
Real Time Counter Sub Second Increment Control
Figure 17-75. RTCSUBSECINCCTL Register
31

1
UPD_ACK
R-0h

0
UPD_REQ
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-100. RTCSUBSECINCCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

UPD_ACK

Acknowledgment of the UPD_REQ.

UPD_REQ

R/W

Signal that a new real time counter sub second increment value is
available
0: New sub second increment is not available
1: New sub second increment is available
This bit must not be modified unless UPD_ACK matches the current
value.

31-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1415

AUX – Sensor Controller Registers

www.ti.com

17.7.7.15 MCUBUSCTL Register (Offset = 48h) [reset = 0h]
MCUBUSCTL is shown in Figure 17-76 and described in Table 17-101.
Return to Summary Table.
MCU Bus Control
Controls the connection between the AUX domain bus and the MCU domain bus.
The buses must be disconnected to allow power-down or power-off of the AUX domain.
Figure 17-76. MCUBUSCTL Register
31

0
DISCONNECT
_REQ
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-101. MCUBUSCTL Register Field Descriptions
Bit
31-1
0

1416

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DISCONNECT_REQ

R/W

Requests the AUX domain bus to be disconnected from the MCU
domain bus. The request has no effect when
AON_WUC:AUX_CTL.AUX_FORCE_ON is set.
The disconnection status can be monitored through MCUBUSSTAT.
Note however that this register cannot be read by the system CPU
while disconnected.
It is recommended that this bit is set and remains set after initial
power-up, and that the system CPU uses
AON_WUC:AUX_CTL.AUX_FORCE_ON to connect/disconnect the
bus.

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.7.16 MCUBUSSTAT Register (Offset = 4Ch) [reset = 0h]
MCUBUSSTAT is shown in Figure 17-77 and described in Table 17-102.
Return to Summary Table.
MCU Bus Status
Indicates the connection state of the AUX domain and MCU domain buses.
Note that this register cannot be read from the MCU domain while disconnected, and is therefore only
useful for the AUX_SCE.
Figure 17-77. MCUBUSSTAT Register
31

1
DISCONNECT
ED
R-0h

0
DISCONNECT
_ACK
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-102. MCUBUSSTAT Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DISCONNECTED

Indicates whether the AUX domain and MCU domain buses are
currently disconnected (1) or connected (0).

DISCONNECT_ACK

Acknowledges reception of the bus disconnection request, by
matching the value of MCUBUSCTL.DISCONNECT_REQ.
Note that if AON_WUC:AUXCTL.AUX_FORCE_ON = 1 a reconnect
to the MCU domain bus will be made regardless of the state of
MCUBUSCTL.DISCONNECT_REQ

31-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1417

AUX – Sensor Controller Registers

www.ti.com

17.7.7.17 AONCTLSTAT Register (Offset = 50h) [reset = 0h]
AONCTLSTAT is shown in Figure 17-78 and described in Table 17-103.
Return to Summary Table.
AON Domain Control Status
Status of AUX domain control from AON_WUC.
Figure 17-78. AONCTLSTAT Register
31

1
AUX_FORCE_
ON
R-0h

0
SCE_RUN_EN

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

R-0h

Table 17-103. AONCTLSTAT Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AUX_FORCE_ON

Status of AON_WUC:AUX_CTL.AUX_FORCE_ON.

SCE_RUN_EN

Status of AON_WUC:AUX_CTL.SCE_RUN_EN.

31-2

1418

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.7.18 AUXIOLATCH Register (Offset = 54h) [reset = 0h]
AUXIOLATCH is shown in Figure 17-79 and described in Table 17-104.
Return to Summary Table.
AUX Input Output Latch
Controls latching of signals between AUX_AIODIO0/AUX_AIODIO1 and AON_IOC.
Figure 17-79. AUXIOLATCH Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
EN
R/W0h

Table 17-104. AUXIOLATCH Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Opens (1) or closes (0) the AUX_AIODIO0/AUX_AIODIO1 signal
latching.
At startup, set EN = TRANSP before configuring
AUX_AIODIO0/AUX_AIODIO1 and subsequently selecting AUX
mode in the AON_IOC.
When powering off the AUX domain (using PWROFFREQ.REQ), set
EN = STATIC in advance preserve the current state (mode and
output value) of the I/O pins.
0h = Latches are static ( closed )
1h = Latches are transparent ( open )

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1419

AUX – Sensor Controller Registers

www.ti.com

17.7.7.19 MODCLKEN1 Register (Offset = 5Ch) [reset = 0h]
MODCLKEN1 is shown in Figure 17-80 and described in Table 17-105.
Return to Summary Table.
Module Clock Enable 1
Clock enable for each module in the AUX domain, for use by the AUX_SCE. Settings take effect
immediately.
The settings in this register are OR'ed with the corresponding settings in MODCLKEN0. This allows
system CPU and AUX_SCE to request clocks independently.
Figure 17-80. MODCLKEN1 Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

7
AUX_ADI4
R/W-0h

6
AUX_DDI0_OS
C
R/W-0h

5
TDC

4
ANAIF

3
TIMER

2
AIODIO1

1
AIODIO0

0
SMPH

R/W-0h

Table 17-105. MODCLKEN1 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AUX_ADI4

R/W

Enables (1) or disables (0) clock for AUX_ADI4.
0h = AUX_SCE has not requested clock for AUX_ADI4
1h = AUX_SCE has requested clock for AUX_ADI4

AUX_DDI0_OSC

R/W

Enables (1) or disables (0) clock for AUX_DDI0_OSC.
0h = AUX_SCE has not requested clock for AUX_DDI0_OSC
1h = AUX_SCE has requested clock for AUX_DDI0_OSC

TDC

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ANAIF

R/W

Enables (1) or disables (0) clock for AUX_ANAIF.
0h = AUX_SCE has not requested clock for ANAIF
1h = AUX_SCE has requested clock for ANAIF

TIMER

R/W

Enables (1) or disables (0) clock for AUX_TIMER.
0h = AUX_SCE has not requested clock for TIMER
1h = AUX_SCE has requested clock for TIMER

AIODIO1

R/W

Enables (1) or disables (0) clock for AUX_AIODIO1.
0h = AUX_SCE has not requested clock for AIODIO1
1h = AUX_SCE has requested clock for AIODIO1

AIODIO0

R/W

Enables (1) or disables (0) clock for AUX_AIODIO0.
0h = AUX_SCE has not requested clock for AIODIO0
1h = AUX_SCE has requested clock for AIODIO0

SMPH

R/W

Enables (1) or disables (0) clock for AUX_SMPH.
0h = AUX_SCE has not requested clock for SMPH
1h = AUX_SCE has requested clock for SMPH

31-8

1420

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.8 AUX_ANAIF Registers
Table 17-106 lists the memory-mapped registers for the AUX_ANAIF. All register offset addresses not
listed in Table 17-106 should be considered as reserved locations and the register contents should not be
modified.
Table 17-106. AUX_ANAIF Registers
Offset

Acronym

10h

ADCCTL

ADC Control

Section 17.7.8.1

14h

ADCFIFOSTAT

ADC FIFO Status

Section 17.7.8.2

18h

ADCFIFO

ADC FIFO

Section 17.7.8.3

1Ch

ADCTRIG

ADC Trigger

Section 17.7.8.4

20h

ISRCCTL

Current Source Control

Section 17.7.8.5

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Section

AUX – Sensor Controller with Digital and Analog Peripherals

1421

AUX – Sensor Controller Registers

www.ti.com

17.7.8.1 ADCCTL Register (Offset = 10h) [reset = 0h]
ADCCTL is shown in Figure 17-81 and described in Table 17-107.
Return to Summary Table.
ADC Control
Figure 17-81. ADCCTL Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

13
START_POL
R/W-0h

10
START_SRC
R/W-0h

RESERVED
R-0h
7

RESERVED
R-0h

0
CMD
R/W-0h

Table 17-107. ADCCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-14

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

START_POL

R/W

Selected active edge for start event / Selected polarity for start event
0h = Start on rising edge of event
1h = Start on falling edge of event

1422

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

Table 17-107. ADCCTL Register Field Descriptions (continued)
Field

Type

Reset

Description

12-8

Bit

START_SRC

R/W

Selected source for ADC conversion start event. The start source
selected by this field is OR'ed with any trigger coming from writes to
ADCTRIG.START. If it is desired to only trigger ADC conversions by
writes to ADCTRIG.START one should select NO_EVENT here
0h = Selects RTC_CH2_EV as start signal
1h = Selects AUX_COMPA as start signal
2h = Selects AUX_COMPB as start signal
3h = Selects TDC_DONE as start signal
4h = Selects TIMER0_EV as start signal
5h = Selects TIMER1_EV as start signal
6h = Selects SMPH_AUTOTAKE_DONE as start signal
7h = Reserved do not use
8h = Reserved do not use
9h = No event selected
Ah = No event selected
Bh = Selects AON_SW as start signal
Ch = Selects AON_PROG_WU as start signal
Dh = Selects AUXIO0 as start signal
Eh = Selects AUXIO1 as start signal
Fh = Selects AUXIO2 as start signal
10h = Selects AUXIO3 as start signal
11h = Selects AUXIO4 as start signal
12h = Selects AUXIO5 as start signal
13h = Selects AUXIO6 as start signal
14h = Selects AUXIO7 as start signal
15h = Selects AUXIO8 as start signal
16h = Selects AUXIO9 as start signal
17h = Selects AUXIO10 as start signal
18h = Selects AUXIO11 as start signal
19h = Selects AUXIO12 as start signal
1Ah = Selects AUXIO13 as start signal
1Bh = Selects AUXIO14 as start signal
1Ch = Selects AUXIO15 as start signal
1Dh = Selects ACLK_REF as start signal
1Eh = Selects MCU_EV as start signal
1Fh = Selects ADC_IRQ as start signal

7-2

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

CMD

R/W

ADC interface control command
0h = ADC interface disabled
1h = ADC interface enabled
3h = ADC FIFO flush. Note that CMD needs to be set to 'EN' again
for FIFO to be functional after a flush. A flush takes two clock
periods on the AUX clock to finish.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1423

AUX – Sensor Controller Registers

www.ti.com

17.7.8.2 ADCFIFOSTAT Register (Offset = 14h) [reset = 1h]
ADCFIFOSTAT is shown in Figure 17-82 and described in Table 17-108.
Return to Summary Table.
ADC FIFO Status
FIFO can hold up to four ADC samples
Figure 17-82. ADCFIFOSTAT Register
31

3
UNDERFLOW
R-0h

2
FULL
R-0h

1
ALMOST_FULL
R-0h

0
EMPTY
R-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

6
RESERVED
R-0h

4
OVERFLOW
R-0h

Table 17-108. ADCFIFOSTAT Register Field Descriptions
Field

Type

Reset

Description

31-5

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

OVERFLOW

FIFO overflow flag.
0: FIFO has not overflowed.
1: FIFO has overflowed, this flag is sticky until FIFO is flushed.

UNDERFLOW

FIFO underflow flag.
0: FIFO has not underflowed
1: FIFO has underflowed, this flag is sticky until the FIFO is flushed

FULL

FIFO full flag.
0: FIFO is not full, i.e. there is less than 4 samples in the FIFO.
1: FIFO is full, i.e. there are 4 samples in the FIFO

ALMOST_FULL

FIFO almost full flag.
0: There is less than 3 samples in the FIFO, or the FIFO is full in
which case the FULL flag is asserted
1: There are 3 samples in the FIFO, i.e. there is room for one more
sample

EMPTY

FIFO empty flag.
0: FIFO contains one or more samples
1: FIFO is empty

1424

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.8.3 ADCFIFO Register (Offset = 18h) [reset = 0h]
ADCFIFO is shown in Figure 17-83 and described in Table 17-109.
Return to Summary Table.
ADC FIFO
Figure 17-83. ADCFIFO Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

6 5 4
DATA
R/W-0h

Table 17-109. ADCFIFO Register Field Descriptions
Field

Type

Reset

Description

31-12

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

11-0

DATA

R/W

FIFO is popped when read. Data is pushed into FIFO when written.
Writing is intended for debugging/code development purposes

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1425

AUX – Sensor Controller Registers

www.ti.com

17.7.8.4 ADCTRIG Register (Offset = 1Ch) [reset = 0h]
ADCTRIG is shown in Figure 17-84 and described in Table 17-110.
Return to Summary Table.
ADC Trigger
Figure 17-84. ADCTRIG Register
31

0
START
W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-110. ADCTRIG Register Field Descriptions
Bit
31-1
0

1426

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

START

Writing to this register will trigger an ADC conversion given that
ADCCTL.START_SRC is set to NO_EVENT0 or NO_EVENT1. If
other setting is used in ADCCTL.START_SRC behavior can be
unpredictable

AUX – Sensor Controller with Digital and Analog Peripherals

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller Registers

www.ti.com

17.7.8.5 ISRCCTL Register (Offset = 20h) [reset = 1h]
ISRCCTL is shown in Figure 17-85 and described in Table 17-111.
Return to Summary Table.
Current Source Control
Figure 17-85. ISRCCTL Register
31

0
RESET_N
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 17-111. ISRCCTL Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RESET_N

R/W

Current source control
0: Current source is clamped
1: Current source is active/charging

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

AUX – Sensor Controller with Digital and Analog Peripherals

1427

Chapter 18
SWCU117G – February 2015 – Revised February 2017

Battery Monitor and Temperature Sensor
This chapter describes the CC26x0 and CC13x0 battery monitor and temperature sensor.
Topic

18.1
18.2
18.3

1428

...........................................................................................................................

Page

Introduction ................................................................................................... 1429
Functional Description .................................................................................... 1429
BATMON Registers ......................................................................................... 1430

Battery Monitor and Temperature Sensor

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Introduction

www.ti.com

18.1 Introduction
The battery monitor is a small block automatically enabled at boot that monitors both the VDDS supply
voltage and the temperature through an on-chip temperature sensor.
The battery monitor provides voltage and temperature information to several modules, including the flash
and the radio, to ensure correct operation and lowest power consumption. Therefore, it is not
recommended to modify any settings in the battery monitor or turn it off.

18.2 Functional Description
The battery monitor is a 6-bit SAR-like ADC running at 32 kHz that performs alternate measurements of
the supply voltage and the temperature sensor. When the battery monitor has settled on its first
measurement, it stops working in SAR mode and starts linear tracking of voltage and temperature. A small
digital core transforms these measurements to voltage and temperature in °C, which are read directly from
the BAT and TEMP registers.
When a change in supply voltage or temperature is measured, the Battery Monitor will solely track the
parameter that has changed until it has settled on a new constant level. The 50-mV resolution of the ADC
and the 32-kHz clock speed will limit the Battery Monitors capability of measuring voltage spikes. Due to
the Battery Monitor not only alternating between temperature and battery voltage, but also between
checking if there has been a positive or negative change since last read, there can be a delay of 4 clock
cycles between a voltage dip and the time when the ADC notices that the temperature or voltage has
changed. This is important to keep in mind because the Battery Monitor is designed to measure the
battery voltage; it is not designed to measure voltage spurs due to short periods of higher current
consumption.
The module also includes two registers, BATUPD and TEMPUPD, that are used to monitor changes in
voltage and temperature, respectively. The registers are connected to the AON event fabric. For details,
see Chapter 4. The BATUPD and TEMPUPD registers must be cleared manually and assert only when
there is an updated value for either the supply voltage or temperature.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Battery Monitor and Temperature Sensor

1429

BATMON Registers

www.ti.com

18.3 BATMON Registers
18.3.1 AON_BATMON Registers
Table 18-1 lists the memory-mapped registers for the AON_BATMON. All register offset addresses not
listed in Table 18-1 should be considered as reserved locations and the register contents should not be
modified.
Table 18-1. AON_BATMON Registers
Offset

1430

Acronym

CTL

Internal

Section 18.3.1.1

Section

MEASCFG

Internal

Section 18.3.1.2

TEMPP0

Internal

Section 18.3.1.3

10h

TEMPP1

Internal

Section 18.3.1.4

14h

TEMPP2

Internal

Section 18.3.1.5

18h

BATMONP0

Internal

Section 18.3.1.6

1Ch

BATMONP1

Internal

Section 18.3.1.7

20h

IOSTRP0

Internal

Section 18.3.1.8

24h

FLASHPUMPP0

Internal

Section 18.3.1.9

28h

BAT

Last Measured Battery Voltage

Section 18.3.1.10

2Ch

BATUPD

Battery Update

Section 18.3.1.11

30h

TEMP

Temperature

Section 18.3.1.12

34h

TEMPUPD

Temperature Update

Section 18.3.1.13

Battery Monitor and Temperature Sensor

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

BATMON Registers

www.ti.com

18.3.1.1 CTL Register (Offset = 0h) [reset = 0h]
CTL is shown in Figure 18-1 and described in Table 18-2.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 18-1. CTL Register
31

1
CALC_EN
R/W-0h

0
MEAS_EN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 18-2. CTL Register Field Descriptions
Bit
31-2

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

CALC_EN

R/W

Internal. Only to be used through TI provided API.

MEAS_EN

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Battery Monitor and Temperature Sensor

1431

BATMON Registers

www.ti.com

18.3.1.2 MEASCFG Register (Offset = 4h) [reset = 0h]
MEASCFG is shown in Figure 18-2 and described in Table 18-3.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 18-2. MEASCFG Register
31

24
23
RESERVED
R-0h

9
8
RESERVED
R-0h

PER
R/W-0h

Table 18-3. MEASCFG Register Field Descriptions
Field

Type

Reset

Description

31-2

Bit

RESERVED

Internal. Only to be used through TI provided API.

1-0

PER

R/W

Internal. Only to be used through TI provided API.

1432

Battery Monitor and Temperature Sensor

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

BATMON Registers

www.ti.com

18.3.1.3 TEMPP0 Register (Offset = Ch) [reset = 0h]
TEMPP0 is shown in Figure 18-3 and described in Table 18-4.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 18-3. TEMPP0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
CFG
R/W-0h

Table 18-4. TEMPP0 Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Internal. Only to be used through TI provided API.

7-0

CFG

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Battery Monitor and Temperature Sensor

1433

BATMON Registers

www.ti.com

18.3.1.4 TEMPP1 Register (Offset = 10h) [reset = 0h]
TEMPP1 is shown in Figure 18-4 and described in Table 18-5.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 18-4. TEMPP1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2 1
CFG
R/W-0h

Table 18-5. TEMPP1 Register Field Descriptions
Field

Type

Reset

Description

31-6

Bit

RESERVED

Internal. Only to be used through TI provided API.

5-0

CFG

R/W

Internal. Only to be used through TI provided API.

1434

Battery Monitor and Temperature Sensor

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

BATMON Registers

www.ti.com

18.3.1.5 TEMPP2 Register (Offset = 14h) [reset = 0h]
TEMPP2 is shown in Figure 18-5 and described in Table 18-6.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 18-5. TEMPP2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

2 1
CFG
R/W-0h

Table 18-6. TEMPP2 Register Field Descriptions
Field

Type

Reset

Description

31-5

Bit

RESERVED

Internal. Only to be used through TI provided API.

4-0

CFG

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Battery Monitor and Temperature Sensor

1435

BATMON Registers

www.ti.com

18.3.1.6 BATMONP0 Register (Offset = 18h) [reset = 0h]
BATMONP0 is shown in Figure 18-6 and described in Table 18-7.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 18-6. BATMONP0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2 1
CFG
R/W-0h

Table 18-7. BATMONP0 Register Field Descriptions
Field

Type

Reset

Description

31-6

Bit

RESERVED

Internal. Only to be used through TI provided API.

5-0

CFG

R/W

Internal. Only to be used through TI provided API.

1436

Battery Monitor and Temperature Sensor

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

BATMON Registers

www.ti.com

18.3.1.7 BATMONP1 Register (Offset = 1Ch) [reset = 0h]
BATMONP1 is shown in Figure 18-7 and described in Table 18-8.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 18-7. BATMONP1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2 1
CFG
R/W-0h

Table 18-8. BATMONP1 Register Field Descriptions
Field

Type

Reset

Description

31-6

Bit

RESERVED

Internal. Only to be used through TI provided API.

5-0

CFG

R/W

Internal. Only to be used through TI provided API.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Battery Monitor and Temperature Sensor

1437

BATMON Registers

www.ti.com

18.3.1.8 IOSTRP0 Register (Offset = 20h) [reset = 28h]
IOSTRP0 is shown in Figure 18-8 and described in Table 18-9.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 18-8. IOSTRP0 Register
31

11
10
RESERVED
R-0h

24
23
RESERVED
R-0h
8

CFG2
R/W-2h

CFG1
R/W-8h

Table 18-9. IOSTRP0 Register Field Descriptions
Field

Type

Reset

Description

31-6

Bit

RESERVED

Internal. Only to be used through TI provided API.

5-4

CFG2

R/W

Internal. Only to be used through TI provided API.

3-0

CFG1

R/W

Internal. Only to be used through TI provided API.

1438

Battery Monitor and Temperature Sensor

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

BATMON Registers

www.ti.com

18.3.1.9 FLASHPUMPP0 Register (Offset = 24h) [reset = 0h]
FLASHPUMPP0 is shown in Figure 18-9 and described in Table 18-10.
Return to Summary Table.
Internal. Only to be used through TI provided API.
Figure 18-9. FLASHPUMPP0 Register
31

8
FALLB
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
LOWLIM
R/W-0h

4
OVR
R/W-0h

HIGHLIM
R/W-0h

CFG
R/W-0h

Table 18-10. FLASHPUMPP0 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Internal. Only to be used through TI provided API.

FALLB

R/W

Internal. Only to be used through TI provided API.

7-6

HIGHLIM

R/W

Internal. Only to be used through TI provided API.

LOWLIM

R/W

Internal. Only to be used through TI provided API.

OVR

R/W

Internal. Only to be used through TI provided API.

3-0

CFG

R/W

Internal. Only to be used through TI provided API.

31-9
8

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Battery Monitor and Temperature Sensor

1439

BATMON Registers

www.ti.com

18.3.1.10 BAT Register (Offset = 28h) [reset = 0h]
BAT is shown in Figure 18-10 and described in Table 18-11.
Return to Summary Table.
Last Measured Battery Voltage
This register may be read while BATUPD.STAT = 1
Figure 18-10. BAT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
RESERVED
INT
R-0h
R-0h

4 3
FRAC
R-0h

Table 18-11. BAT Register Field Descriptions
Field

Type

Reset

Description

31-11

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

10-8

INT

Integer part:
0x0: 0V + fractional part
...
0x3: 3V + fractional part
0x4: 4V + fractional part

7-0

FRAC

Fractional part, standard binary fractional encoding.
0x00: .0V
...
0x20: 1/8 = .125V
0x40: 1/4 = .25V
0x80: 1/2 = .5V
...
0xA0: 1/2 + 1/8 = .625V
...
0xFF: Max

1440

Battery Monitor and Temperature Sensor

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

BATMON Registers

www.ti.com

18.3.1.11 BATUPD Register (Offset = 2Ch) [reset = 0h]
BATUPD is shown in Figure 18-11 and described in Table 18-12.
Return to Summary Table.
Battery Update
Indicates BAT Updates
Figure 18-11. BATUPD Register
31

0
STAT
R/W1C-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 18-12. BATUPD Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STAT

R/W1C

0: No update since last clear
1: New battery voltage is present.
Write 1 to clear the status.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Battery Monitor and Temperature Sensor

1441

BATMON Registers

www.ti.com

18.3.1.12 TEMP Register (Offset = 30h) [reset = 0h]
TEMP is shown in Figure 18-12 and described in Table 18-13.
Return to Summary Table.
Temperature
Last Measured Temperature in Degrees Celsius
This register may be read while TEMPUPD.STAT = 1.
Figure 18-12. TEMP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
INT
R-0h
R-0h

5 4 3 2
RESERVED
R-0h

Table 18-13. TEMP Register Field Descriptions
Field

Type

Reset

Description

31-17

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

16-8

INT

Integer part (signed) of temperature value.
Total value = INTEGER + FRACTIONAL
2's complement encoding
0x100: Min value
0x1D8: -40C
0x1FF: -1C
0x00: 0C
0x1B: 27C
0x55: 85C
0xFF: Max value

7-0

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1442

Battery Monitor and Temperature Sensor

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

BATMON Registers

www.ti.com

18.3.1.13 TEMPUPD Register (Offset = 34h) [reset = 0h]
TEMPUPD is shown in Figure 18-13 and described in Table 18-14.
Return to Summary Table.
Temperature Update
Indicates TEMP Updates
Figure 18-13. TEMPUPD Register
31

0
STAT
R/W1C-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 18-14. TEMPUPD Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STAT

R/W1C

0: No update since last clear
1: New temperature is present.
Write 1 to clear the status.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Battery Monitor and Temperature Sensor

1443

Chapter 19
SWCU117G – February 2015 – Revised February 2017

Universal Asynchronous Receiver/Transmitter (UART)
This chapter discusses the Universal Asynchronous Receiver/Transmitter (UART).
Topic

19.1
19.2
19.3
19.4
19.5
19.6
19.7

1444

...........................................................................................................................
Universal Asynchronous Receiver/Transmitter ...................................................
Block Diagram ................................................................................................
Signal Description...........................................................................................
Functional Description ...................................................................................
Interface to DMA .............................................................................................
Initialization and Configuration .........................................................................
UART Registers ..............................................................................................

Universal Asynchronous Receiver/Transmitter (UART)

Page

1445
1446
1446
1446
1451
1452
1453

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter

www.ti.com

19.1 Universal Asynchronous Receiver/Transmitter
The controller of the CC26x0 and CC13x0 includes a UART with the following features:
• Programmable baud-rate generator allowing speeds up to 3 Mbps
• Separate 32 × 8 transmit (TX) and 32 × 12 receive (RX) first-in first-out (FIFO) buffers to reduce CPU
interrupt service loading
• Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered
interface
• FIFO trigger levels of , ¼, ½, ¾, and
• Standard asynchronous communication bits for start, stop, and parity
• Line-break generation and detection
• Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no parity bit generation and detection
– 1 or 2 stop-bit generation
• Support for modem control functions CTS and RTS
• Independent masking of the TX FIFO, RX FIFO RX time-out, modem status, and error conditions
• Standard FIFO-level and end-of-transmission interrupts
• Efficient transfers using micro direct memory access controller ( DMA):
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at programmed
FIFO level
– Transmit single request is asserted when there is space in the FIFO; burst request is asserted at
programmed FIFO level
• Programmable hardware flow control

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1445

Block Diagram

www.ti.com

19.2 Block Diagram
Figure 19-1 shows the UART module block diagram.
Figure 19-1. UART Module Block Diagram
Clock control

PERDMACLK
UART_CTL

DMA control

DMA Request

UART_DMACTL
TX FIFO
32 x 8
Interrupt control

Interrupt

UART_IFLS
Transmitter

UART_IMSC

UARTTXD

UART_MIS
UART_RIS
Identification regiters

UART_ICR

Baud rate
generator

Control / Status
UART_PERIPHID0

UART_IBRD
UART_DR

UART_PERIPHID1

UART_FBRD

UART_PERIPHID2

Receiver

UARTRXD

UART_PERIPHID3
Control / Status
UART_PCELLID0

Control / Status

UART_PCELLID1

Control / Status
UART_RSR/ECR

RX FIFO

UART_FR

32 x 12

UART_PCELLID2
UART_PCELLID3
UART_LCRH
UART_CTL

19.3 Signal Description
Table 19-1 lists the external signals of the UART module and describes the function of each. The UART
signals are set in the IOCFGn registers. For more information on configuring GPIOs, see Chapter 11.
Table 19-1. Signals for UART
Pin Name

Pin Number

Pin Type (1)

UARTRxD

Assigned through
GPIO
configuration

UART module 0 receive

UART module 0 transmit

UARTTxD
(1)

Description

I = Input; O = Output; I/O = Bidirectional

19.4 Functional Description
Each CC26x0 and CC13x0 UART performs the functions of parallel-to-serial and serial-to-parallel
conversions. The CC26x0 and CC13x0 UART is similar in functionality to a 16C550 UART, but is not
register compatible.
The UART is configured for transmit and receive through the UART Control Register (UART:CTL) TXE
and RXE bits. Transmit and receive are both enabled out of reset. Before any control registers are
programmed, the UART must be disabled by clearing the UART:CTL UARTEN register bit. If the UART is
disabled during a transmit or receive operation, the current transaction completes before the UART stops.

1446

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

19.4.1 Transmit and Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the TX FIFO. The control
logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first), parity
bit, and the stop bits, according to the programmed configuration in the control registers. For details, see
Figure 19-2.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse
is detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their
status accompanies the data written to the RX FIFO.
Figure 19-2. UART Character Frame
3456
,-.

!$0
-(12 )*(+

/-.
#$% &'(' )*(+

"
4
-('7(

:'7*(; )*(
*< 84')98&

19.4.2 Baud-Rate Generation
The baud-rate divisor (BRD) is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit period.
Having a fractional baud-rate divider allows the UART to generate all standard baud rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor Register (UART:IBRD), and the
6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor Register (UART:FBRD).
Equation 1 shows the relationship of the BRD to the system clock.
BRD = BRDI + BRDF = PERDMACLK / (ClkDiv × Baud Rate)

(1)

where:
BRDI is the integer part of the BRD
BRDF is the fractional part, separated by a decimal place
PERDMACLK is the system clock connected to the UART
ClkDiv is 16
The 6-bit fractional number that is loaded into the UART:FBRD DIVFRAC bit field can be calculated by
taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for
rounding errors, as shown by Equation 2.
UART:FBRD.DIVFRAC = integer (BRDF × 64 + 0.5)

(2)

Along with the UART Line Control, High Byte Register (UART:LCRH), the UART_IBRD and the
UART:FBRD registers form an internal 30-bit register. This internal register is updated only when a write
operation to the UART:LCRH register is performed, so a write to the UART:LCRH register must follow any
changes to the BRD for the changes to take effect.
The four possible sequences to update the baud-rate registers are as follows:
• UART:IBRD write, UART:FBRD write, and UART:LCRH write
• UART:FBRD write, UART;IBRD write, and UART:LCRH write
• UART:IBRD write and UART:LCRH write
• UART:FBRD write and UART:LCRH write

19.4.3 Data Transmission
Data received or transmitted is stored in two FIFOs, though the RX FIFO has an extra 4 bits per character
for status information. For transmission, data is written into the TX FIFO. If the UART is enabled, a data
frame starts transmitting with the parameters indicated in the UART:LCRH register. Data continues to
transmit until no data is left in the TX FIFO. The UART Flag Register (UART:FR) BUSY bit is asserted as
soon as data is written to the TX FIFO (that is, if the FIFO is not empty), and remains asserted while data
is transmitting. The BUSY bit is negated only when the TX FIFO is empty, and the last character has
transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even
though the UART may no longer be enabled.
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1447

Functional Description

www.ti.com

When the receiver is idle (the UARTRXD signal is continuously 1), and the data input goes low (a start bit
was received), the receive counter begins running and data is sampled.
The start bit is valid and recognized if the UARTRXD signal is still low on the eighth cycle of the baud rate
clock otherwise the start bit is ignored. After a valid start bit is detected, successive data bits are sampled
on every sixteenth cycle of the baud rate clock. The parity bit is then checked if parity mode is enabled.
Data length and parity are defined in the UART:LCRH register.
Lastly, a valid stop bit is confirmed if the UARTRXD signal is high; otherwise a framing error has occurred.
When a full word is received, the data is stored in the receive FIFO with any error bits associated with that
word.

19.4.4 Modem Handshake Support
This section describes how to configure and use the modem flow control signals for UART0 when
connected as a data terminal equipment (DTE), or as a data communications equipment (DCE). A modem
is a DCE, and a computing device that connects to a modem is the DTE.
19.4.4.1 Signaling
The status signals provided by UART0 differ based on whether the UART is used as a DTE or a DCE.
When used as a DTE, the modem flow control signals are defined as:
• UART0CTS is Clear To Send
• UART0RTS is Request To Send
When used as a DCE, the modem flow control signals are defined as:
• UART0CTS is Request To Send
• UART0RTS is Clear To Send
19.4.4.2 Flow Control
Either hardware or software can accomplish flow control. The following sections describe the different
methods.
19.4.4.2.1 Hardware Flow Control (RTS and CTS)
Hardware flow control between two devices is accomplished by connecting the UART0RTS output to the
Clear-To-Send input on the receiving device, and connecting the Request-To-Send output on the receiving
device to the UART0CTS input.
The UART0CTS input controls the transmitter. The transmitter can transmit data only when the
UART0CTS input is asserted. The UART0RTS output signal indicates the state of the receive FIFO.
UART0CTS remains asserted until the preprogrammed watermark level is reached, indicating that the RX
FIFO has no space to store additional characters.
The UART:CTL register bits CTSEN and RTSEN specify the flow control mode as shown in Table 19-2.
Table 19-2. Flow Control Mode

1448

CTSEN

RTSEN

Description

RTS and CTS flow control enabled

Only CTS flow control enabled

Only RTS flow control enabled

Both RTS and CTS flow control
disabled

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

19.4.4.2.2 Software Flow Control (Modem Status Interrupts)
Software flow control between two devices is accomplished by using interrupts to indicate the status of the
UART. Interrupts can be generated for the U1CTS signal using bit 3 of the UART:IMSC register. The raw
and masked interrupt status can be checked using the UART:RIS and UART:MIS registers. These
interrupts can be cleared using the UART:ICR register.

19.4.5 FIFO Operation
The UART has two 32-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
through the UART Data Register (UART:DR). Read operations of the UART:DR register return a 12-bit
value consisting of 8 data bits and 4 error flags, while write operations place 8-bit data in the TX FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by
setting the UART:LCRH FEN register bit.
FIFO status can be monitored through the UART Flag Register (UART:FR) and the UART Receive Status
Register (UART:RSR). Hardware monitors empty, full, and overrun conditions. The UART:FR register
contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the UART:RSR register shows
overrun status through the OE bit. If the FIFOs are disabled, the empty and full flags are set according to
the status of the 1-byte deep holding registers.
The trigger points at which the FIFOs generate interrupts are controlled through the UART Interrupt FIFO
Level Select Register (UART:IFLS). Both FIFOs can be individually configured to trigger interrupts at
different levels. Available configurations include , ¼, ½, ¾, and . For example, if the ¼ option is
selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out
of reset, both FIFOs are configured to trigger an interrupt at the ½ mark.

19.4.6 Interrupts
The UART can generate interrupts when the following conditions are observed:
• Overrun error
• Break error
• Parity error
• Framing error
• Receive time-out
• Transmit (when the condition defined in the UART:IFLS TXSEL register bit is met)
• Receive (when the condition defined in the UART:IFLS RXSEL register bit is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can
only generate a single interrupt request to the controller at any given time. Software can service multiple
interrupt events in a single interrupt service routine (ISR) by reading the UART Masked Interrupt Status
Register (UART:MIS).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask
Register (UART:IMSC) by setting the corresponding bits. If interrupts are not used, the raw interrupt status
is always visible through the UART Raw Interrupt Status Register (UART:RIS).
Interrupts can be cleared (for the UART:MIS and UART:RIS registers) by setting the corresponding bit in
the UART Interrupt Clear Register (UART:ICR).
The receive time-out interrupt is asserted when the RX FIFO is not empty, and no further data is received
over a 32-bit period. The receive time-out interrupt is cleared either when the FIFO becomes empty
through reading all the data (or by reading the holding register), or when the corresponding bit in the
UART:ICR register is set.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1449

Functional Description

www.ti.com

The UART module provides the possibility of setting and clearing masks for every individual interrupt
source using the UART Interrupt Mask Set/Clear Register (UART:IMSC). The five events that can cause
combined interrupts to CPU are:
• RX: The receive interrupt changes state when one of the following events occurs:
– If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level. When this
happens, the receive interrupt is asserted high. The receive interrupt is cleared by reading data
from the receive FIFO until it becomes less than the trigger level, or by clearing the interrupt.
– If the FIFOs are disabled (have a depth of one location) and data is received, thereby filling the
location, the receive interrupt is asserted high. The receive interrupt is cleared by performing a
single read of the receive FIFO, or by clearing the interrupt.
• TX: The transmit interrupt changes state when one of the following events occurs:
– If the FIFOs are enabled and the transmit FIFO is equal to or lower than the programmed trigger
level, then the transmit interrupt is asserted high. The transmit interrupt is cleared by writing data to
the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt.
– If the FIFOs are disabled (have a depth of one location) and there is no data present in the
transmitters single location, the transmit interrupt is asserted high. The interrupt is cleared by
performing a single write to the transmit FIFO, or by clearing the interrupt.
• RX time-out: The receive time-out interrupt is asserted when the receive FIFO is not empty, and no
more data is received during a 32-bit period. The receive time-out interrupt is cleared either when the
FIFO becomes empty through reading all the data (or by reading the holding register), or when 1 is
written to the corresponding bit of the Interrupt Clear Register (UART:ICR).
• Modem status: The modem status interrupt is asserted if the modem status signal uart_cts changes. It
can be cleared using the corresponding clear bit in the UART:ICR register.
• Error: The error interrupt is asserted when an error occurs in the reception of data by the UART. The
interrupt can be caused by a number of different error conditions:
– framing
– parity
– break
– overrun
The cause of the interrupt can be determined by reading the UART:RIS register or the UART:MIS
register. The interrupt can be cleared by writing to the relevant bits of the UART:ICR register.
In addition to the five events produced by the UART module, two additional events are ORed to the
interrupt line:
• RX DMA done: Indicates that the receiver DMA has completed its task. This is a level interrupt
provided by the DMA module, and is cleared using the dma_done clear register (UDMA:REQDONE) in
the DMA module.
• TX DMA done: Indicates that the transmit DMA has completed its task. This is a level interrupt
provided by the DMA module, and is cleared using the dma_done clear register (UDMA:REQDONE) in
the DMA module.

19.4.7 Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work by setting the
UART:CTL LBE register bit. In loopback mode, data transmitted on the UARTTXD output is received on
the UARTRXD input. The LBE bit must be set before the UART is enabled.

1450

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Interface to DMA

www.ti.com

19.5 Interface to DMA
The CC26x0 and CC13x0 devices provide an interface to connect to a DMA controller. Figure 19-3 shows
the interface between the DMA and UART. This interface contains four DMA requests as outputs (RX
Single, RX Burst, TX Single, and TX Burst). The DMA interface also has two DMA request clears as
inputs (for clearing TX and RX DMA requests). Each DMA request signal remains asserted until the
relevant DMA clear signal is asserted. After the DMA clear signal is deasserted, a request signal can
become active again, if conditions are setup correctly. The DMA clear signal must be connected to the
DMA active signal from the DMA module. This signal is asserted when DMA is granted access and is
active. The DMA active signal is deasserted when the DMA transfer completes. Connecting the DMA
active signal from DMA to the DMA request clear input of the UART module ensures that no requests are
generated by the UART module while the DMA is active.
The burst transfer and single transfer request signals are not mutually exclusive, and both can be asserted
at the same time. For example, when there is more data than the watermark level in the receive FIFO, the
burst transfer request and the single transfer request are asserted.
The single and burst requests cannot be masked separately by the UART module and if corresponding
DMA (RX or TX) is enabled, both of these requests are sent to the DMA. The DMA configuration selects
either single or burst request as the trigger. All request signals are deasserted if the UART is disabled or if
the relevant DMA enable bit (TXDMAE or RXDMAE) in the DMA Control Register (UART:DMACTL) is
cleared.
Figure 19-3. µDMA Example
UART
DMA active CH1

DMA RX Clear

DMA active CH2

DMA TX Clear

Event

DMA

DMA Channel 2 SREQ

UART0_TX_DMASREQ

DMA Channel 2 REQ

UART0_TX_DMABREQ

DMA Channel 1 SREQ

UART0_TX_DMASREQ

DMA Channel 1 REQ

UART0_TX_DMABREQ

UART DMA
Controller

DMA Channel 14 REQ

UART Interrupt

CPU
DMA done CH2
DMA done CH1
UART Interrupt
Controller

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1451

Initialization and Configuration

www.ti.com

19.6 Initialization and Configuration
The UART module provides four I/O signals to be routed to the pads. The following signals are selected
through the IOCFGn registers in the IOC module.
The UART module provides four I/O functions to be routed to the pads:
• Inputs: RXD, CTS
• Outputs: TXD, RTS
CTS and RTS lines are active low.
NOTE: IOC must be configured before enabling UART, or unwanted transitions on input signals may
confuse UART on incoming transactions. When IOC is configured as UART-specific I/Os
(RXD, CTS, TXD, or RTS), IOC sets static output driver enable to the pad (output driver
enable = 1 for output TXD and RTS and output driver enable = 0 for inputs RXD and CTS).

To enable and initialize the UART, use the following steps:
1. Enable the serial power domain and enable the UART module in the PRCM module by writing to the
PRCM:UARTCLKGR register, the PRCM:UARTCLKGS register, and the PRCM:UARTCLKGDS
register, or by using the driver library functions:
PRCMPeripheralRunEnable(uint32_t), PRCMPeripheralSleepEnable(uint32_t),
PRCMPeripheralDeepSleepEnable(unit32_t)

and loading the setting to the clock controller by writing to the PRCM:CLKLOADCTL register or by
using the function
PRCMLoadSet().

2. Configure the IOC module to map UART signals to the correct GPIO pins. For more information on pin
connections, see Chapter 11.
This section discusses the steps required to use a UART module. For this example, the UART clock is
assumed to be 24 MHz, and the desired UART configuration is the following:
• Baud rate: 115 200
• Data length of 8 bits
• One stop bit
• No parity
• FIFOs disabled
• No interrupts
The first thing to consider when programming the UART is the BRD because the UART:IBRD and
UART:FBRD registers must be written before the UART:LCRH register. The BRD can be calculated using
the equation described in Section 19.4.2.
BRD = 24 000 000 / (16 × 115 200) = 13.0208

(3)

The result of Equation 3 indicates that the UART:IBRD DIVINT field must be set to 13 decimal or 0xD.
Equation 4 calculates the value to be loaded into the UART:FBRD register.
UART:FBRD.DIVFRAC = integer (0.0208 × 64 + 0.5) = 1

(4)

With the BRD values available, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UART:CTL UARTEN bit.
2. Write the integer portion of the BRD to the UART:IBRD register.
3. Write the fractional portion of the BRD to the UART:FBRD register.
4. Write the desired serial parameters to the UART:LCRH register (in this case, a value of 0x0000 0060).
5. Enable the UART by setting the UART:CTL UARTEN bit.

1452

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

UART Registers

www.ti.com

19.7 UART Registers
19.7.1 UART Registers
Table 19-3 lists the memory-mapped registers for the UART. All register offset addresses not listed in
Table 19-3 should be considered as reserved locations and the register contents should not be modified.
Table 19-3. UART Registers
Offset

Acronym

Data

Section 19.7.1.1

RSR

Status

Section 19.7.1.2

ECR

Error Clear

Section 19.7.1.3

18h

Flag

Section 19.7.1.4

24h

IBRD

Integer Baud-Rate Divisor

Section 19.7.1.5

28h

FBRD

Fractional Baud-Rate Divisor

Section 19.7.1.6

2Ch

LCRH

Line Control

Section 19.7.1.7

30h

CTL

Control

Section 19.7.1.8

34h

IFLS

Interrupt FIFO Level Select

Section 19.7.1.9

38h

IMSC

Interrupt Mask Set/Clear

Section 19.7.1.10

3Ch

RIS

Raw Interrupt Status

Section 19.7.1.11

40h

MIS

Masked Interrupt Status

Section 19.7.1.12

44h

ICR

Interrupt Clear

Section 19.7.1.13

48h

DMACTL

DMA Control

Section 19.7.1.14

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Section

Universal Asynchronous Receiver/Transmitter (UART)

1453

UART Registers

www.ti.com

19.7.1.1 DR Register (Offset = 0h) [reset = X]
DR is shown in Figure 19-4 and described in Table 19-4.
Return to Summary Table.
Data
For words to be transmitted:
- if the FIFOs are enabled (LCRH.FEN = 1), data written to this location is pushed onto the transmit FIFO
- if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the transmitter holding register (the
bottom word of the transmit FIFO).
The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended
with the appropriate parity bit (if parity is enabled), and a stop bit.
The resultant word is then transmitted.
For received words:
- if the FIFOs are enabled (LCRH.FEN = 1), the data byte and the 4-bit status (break, frame, parity, and
overrun) is pushed onto the 12-bit wide receive FIFO
- if the FIFOs are not enabled (LCRH.FEN = 0), the data byte and status are stored in the receiving
holding register (the bottom word of the receive FIFO).
The received data byte is read by performing reads from this register along with the corresponding status
information. The status information can also be read by a read of the RSR register.
Figure 19-4. DR Register
31

14
13
RESERVED
R-0h

11
OE
R-X

10
BE
R-X

9
PE
R-X

24
23
RESERVED
R-0h

8
FE
R-X

DATA
R/W-X

Table 19-4. DR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

UART Overrun Error:
This bit is set to 1 if data is received and the receive FIFO is already
full. The FIFO contents remain valid because no more data is written
when the FIFO is full, , only the contents of the shift register are
overwritten.
This is cleared to 0 once there is an empty space in the FIFO and a
new character can be written to it.

UART Break Error:
This bit is set to 1 if a break condition was detected, indicating that
the received data input (UARTRXD input pin) was held LOW for
longer than a full-word transmission time (defined as start, data,
parity and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO (i.e., the oldest received data character since last read).
When a break occurs, a 0 character is loaded into the FIFO. The
next character is enabled after the receive data input (UARTRXD
input pin) goes to a 1 (marking state), and the next valid start bit is
received.

UART Parity Error:
When set to 1, it indicates that the parity of the received data
character does not match the parity that the LCRH.EPS and
LCRH.SPS select.
In FIFO mode, this error is associated with the character at the top of
the FIFO (i.e., the oldest received data character since last read).

31-12

1454

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

UART Registers

www.ti.com

Table 19-4. DR Register Field Descriptions (continued)
Bit
8

7-0

Field

Type

Reset

Description

UART Framing Error:
When set to 1, it indicates that the received character did not have a
valid stop bit (a valid stop bit is 1).
In FIFO mode, this error is associated with the character at the top of
the FIFO (i.e., the oldest received data character since last read).

DATA

R/W

Data transmitted or received:
On writes, the transmit data character is pushed into the FIFO.
On reads, the oldest received data character since the last read is
returned.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1455

UART Registers

www.ti.com

19.7.1.2 RSR Register (Offset = 4h) [reset = 0h]
RSR is shown in Figure 19-5 and described in Table 19-5.
Return to Summary Table.
Status
This register is mapped to the same address as ECR register. Reads from this address are associated
with RSR register and return the receive status. Writes to this address are associated with ECR register
and clear the receive status flags (framing, parity, break, and overrun errors).
If the status is read from this register, then the status information for break, framing and parity
corresponds to the data character read from the Data Register, DR prior to reading the RSR. The status
information for overrun is set immediately when an overrun condition occurs.
Figure 19-5. RSR Register
31

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

3
OE
R-0h

2
BE
R-0h

1
PE
R-0h

0
FE
R-0h

Table 19-5. RSR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

UART Break Error:
This bit is set to 1 if a break condition was detected, indicating that
the received data input (UARTRXD input pin) was held LOW for
longer than a full-word transmission time (defined as start, data,
parity and stop bits).
When a break occurs, a 0 character is loaded into the FIFO. The
next character is enabled after the receive data input (UARTRXD
input pin) goes to a 1 (marking state), and the next valid start bit is
received.

UART Parity Error:
When set to 1, it indicates that the parity of the received data
character does not match the parity that the LCRH.EPS and
LCRH.SPS select.

UART Framing Error:
When set to 1, it indicates that the received character did not have a
valid stop bit (a valid stop bit is 1).

31-4

1456

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

UART Registers

www.ti.com

19.7.1.3 ECR Register (Offset = 4h) [reset = 0h]
ECR is shown in Figure 19-6 and described in Table 19-6.
Return to Summary Table.
Error Clear
This register is mapped to the same address as RSR register. Reads from this address are associated
with RSR register and return the receive status. Writes to this address are associated with ECR register
and clear the receive status flags (framing, parity, break, and overrun errors).
Figure 19-6. ECR Register
31

10
9
RESERVED
W-0h

24
23
RESERVED
W-0h
8

3
OE
W-0h

2
BE
W-0h

1
PE
W-0h

0
FE
W-0h

Table 19-6. ECR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

The framing (FE), parity (PE), break (BE) and overrun (OE) errors
are cleared to 0 by any write to this register.

31-4

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1457

UART Registers

www.ti.com

19.7.1.4 FR Register (Offset = 18h) [reset = X]
FR is shown in Figure 19-7 and described in Table 19-7.
Return to Summary Table.
Flag
Reads from this register return the UART flags.
Figure 19-7. FR Register
31

3
BUSY
R-0h

0
CTS
R-X

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

7
TXFE
R-1h

6
RXFF
R-0h

5
TXFF
R-0h

4
RXFE
R-1h

RESERVED
R-0h

Table 19-7. FR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TXFE

UART Transmit FIFO Empty:
The meaning of this bit depends on the state of LCRH.FEN .
- If the FIFO is disabled, this bit is set when the transmit holding
register is empty.
- If the FIFO is enabled, this bit is set when the transmit FIFO is
empty.
This bit does not indicate if there is data in the transmit shift register.

RXFF

UART Receive FIFO Full:
The meaning of this bit depends on the state of LCRH.FEN.
- If the FIFO is disabled, this bit is set when the receive holding
register is full.
- If the FIFO is enabled, this bit is set when the receive FIFO is full.

TXFF

UART Transmit FIFO Full:
Transmit FIFO full. The meaning of this bit depends on the state of
LCRH.FEN.
- If the FIFO is disabled, this bit is set when the transmit holding
register is full.
- If the FIFO is enabled, this bit is set when the transmit FIFO is full.

RXFE

UART Receive FIFO Empty:
Receive FIFO empty. The meaning of this bit depends on the state
of LCRH.FEN.
- If the FIFO is disabled, this bit is set when the receive holding
register is empty.
- If the FIFO is enabled, this bit is set when the receive FIFO is
empty.

BUSY

UART Busy:
If this bit is set to 1, the UART is busy transmitting data. This bit
remains set until the complete byte, including all the stop bits, has
been sent from the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty,
regardless of whether the UART is enabled or not.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-8

2-1

1458

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

UART Registers

www.ti.com

Table 19-7. FR Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

CTS

Clear To Send:
This bit is the complement of the active-low UART CTS input pin.
That is, the bit is 1 when CTS input pin is LOW.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1459

UART Registers

www.ti.com

19.7.1.5 IBRD Register (Offset = 24h) [reset = 0h]
IBRD is shown in Figure 19-8 and described in Table 19-8.
Return to Summary Table.
Integer Baud-Rate Divisor
If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until
transmission or reception of the current character is complete.
Figure 19-8. IBRD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

8 7 6
DIVINT
R/W-0h

Table 19-8. IBRD Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

DIVINT

R/W

The integer baud rate divisor:
The baud rate divisor is calculated using the formula below:
Baud rate divisor = (UART reference clock frequency) / (16 * Baud
rate)
Baud rate divisor must be minimum 1 and maximum 65535.
That is, DIVINT=0 does not give a valid baud rate.
Similarly, if DIVINT=0xFFFF, any non-zero values in
FBRD.DIVFRAC will be illegal.
A valid value must be written to this field before the UART can be
used for RX or TX operations.

1460

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

UART Registers

www.ti.com

19.7.1.6 FBRD Register (Offset = 28h) [reset = 0h]
FBRD is shown in Figure 19-9 and described in Table 19-9.
Return to Summary Table.
Fractional Baud-Rate Divisor
If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until
transmission or reception of the current character is complete.
Figure 19-9. FBRD Register
31

11
10
RESERVED
R/W-0h

24
23
RESERVED
R/W-0h
8

3
2
DIVFRAC
R/W-0h

Table 19-9. FBRD Register Field Descriptions
Bit

Field

Type

Reset

Description

31-6

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

5-0

DIVFRAC

R/W

Fractional Baud-Rate Divisor:
The baud rate divisor is calculated using the formula below:
Baud rate divisor = (UART reference clock frequency) / (16 * Baud
rate)
Baud rate divisor must be minimum 1 and maximum 65535.
That is, IBRD.DIVINT=0 does not give a valid baud rate.
Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC
will be illegal.
A valid value must be written to this field before the UART can be
used for RX or TX operations.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1461

UART Registers

www.ti.com

19.7.1.7 LCRH Register (Offset = 2Ch) [reset = 0h]
LCRH is shown in Figure 19-10 and described in Table 19-10.
Return to Summary Table.
Line Control
Figure 19-10. LCRH Register
31

3
STP2
R/W-0h

2
EPS
R/W-0h

1
PEN
R/W-0h

0
BRK
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

7
SPS
R/W-0h

4
FEN
R/W-0h

WLEN
R/W-0h

Table 19-10. LCRH Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SPS

R/W

UART Stick Parity Select:
0: Stick parity is disabled
1: The parity bit is transmitted and checked as invert of EPS field
(i.e. the parity bit is transmitted and checked as 1 when EPS = 0).
This bit has no effect when PEN disables parity checking and
generation.

WLEN

R/W

UART Word Length:
These bits indicate the number of data bits transmitted or received in
a frame.
0h = 5 : Word Length 5 bits
1h = 6 : Word Length 6 bits
2h = 7 : Word Length 7 bits
3h = 8 : Word Length 8 bits

FEN

R/W

UART Enable FIFOs
0h = FIFOs are disabled (character mode) that is, the FIFOs become
1-byte-deep holding registers.
1h = Transmit and receive FIFO buffers are enabled (FIFO mode)

STP2

R/W

UART Two Stop Bits Select:
If this bit is set to 1, two stop bits are transmitted at the end of the
frame. The receive logic does not check for two stop bits being
received.

EPS

R/W

UART Even Parity Select
0h = Odd parity: The UART generates or checks for an odd number
of 1s in the data and parity bits.
1h = Even parity: The UART generates or checks for an even
number of 1s in the data and parity bits.

PEN

R/W

UART Parity Enable
This bit controls generation and checking of parity bit.
0h = Parity is disabled and no parity bit is added to the data frame
1h = Parity checking and generation is enabled.

31-8
7

6-5

1462

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

UART Registers

www.ti.com

Table 19-10. LCRH Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

BRK

R/W

UART Send Break
If this bit is set to 1, a low-level is continually output on the
UARTTXD output pin, after completing transmission of the current
character. For the proper execution of the break command, the
software must set this bit for at least two complete frames. For
normal use, this bit must be cleared to 0.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1463

UART Registers

www.ti.com

19.7.1.8 CTL Register (Offset = 30h) [reset = 300h]
CTL is shown in Figure 19-11 and described in Table 19-11.
Return to Summary Table.
Control
Figure 19-11. CTL Register
31

11
RTS
R/W-0h

10
RESERVED
R/W-0h

9
RXE
R/W-1h

8
TXE
R/W-1h

0
UARTEN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

15
CTSEN
R/W-0h

14
RTSEN
R/W-0h

7
LBE
R/W-0h

12
RESERVED
R/W-0h
4

RESERVED
R/W-0h

Table 19-11. CTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CTSEN

R/W

CTS hardware flow control enable
0h = CTS hardware flow control disabled
1h = CTS hardware flow control enabled

RTSEN

R/W

RTS hardware flow control enable
0h = RTS hardware flow control disabled
1h = RTS hardware flow control enabled

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RTS

R/W

Request to Send
This bit is the complement of the active-low UART RTS output. That
is, when the bit is programmed to a 1 then RTS output on the pins is
LOW.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RXE

R/W

UART Receive Enable
If the UART is disabled in the middle of reception, it completes the
current character before stopping.
0h = UART Receive disabled
1h = UART Receive enabled

TXE

R/W

UART Transmit Enable
If the UART is disabled in the middle of transmission, it completes
the current character before stopping.
0h = UART Transmit disabled
1h = UART Transmit enabled

LBE

R/W

UART Loop Back Enable:
Enabling the loop-back mode connects the UARTTXD output from
the UART to UARTRXD input of the UART.
0h = Loop Back disabled
1h = Loop Back enabled

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-16

13-12

6-1

1464

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

UART Registers

www.ti.com

Table 19-11. CTL Register Field Descriptions (continued)
Bit
0

Field

Type

Reset

Description

UARTEN

R/W

UART Enable
0h = UART disabled
1h = UART enabled

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1465

UART Registers

www.ti.com

19.7.1.9 IFLS Register (Offset = 34h) [reset = 12h]
IFLS is shown in Figure 19-12 and described in Table 19-12.
Return to Summary Table.
Interrupt FIFO Level Select
Figure 19-12. IFLS Register
31

11
10
RESERVED
R/W-0h

24
23
RESERVED
R/W-0h
8

4
RXSEL
R/W-2h

1
TXSEL
R/W-2h

Table 19-12. IFLS Register Field Descriptions
Field

Type

Reset

Description

31-6

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

5-3

RXSEL

R/W

Receive interrupt FIFO level select:
This field sets the trigger points for the receive interrupt. Values
0b101-0b111 are reserved.
0h = 1_8 : Receive FIFO becomes >= 1/8 full
1h = 2_8 : Receive FIFO becomes >= 1/4 full
2h = 4_8 : Receive FIFO becomes >= 1/2 full
3h = 6_8 : Receive FIFO becomes >= 3/4 full
4h = 7_8 : Receive FIFO becomes >= 7/8 full

2-0

TXSEL

R/W

Transmit interrupt FIFO level select:
This field sets the trigger points for the transmit interrupt. Values
0b101-0b111 are reserved.
0h = 1_8 : Transmit FIFO becomes <= 1/8 full
1h = 2_8 : Transmit FIFO becomes <= 1/4 full
2h = 4_8 : Transmit FIFO becomes <= 1/2 full
3h = 6_8 : Transmit FIFO becomes <= 3/4 full
4h = 7_8 : Transmit FIFO becomes <= 7/8 full

1466

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

UART Registers

www.ti.com

19.7.1.10 IMSC Register (Offset = 38h) [reset = 0h]
IMSC is shown in Figure 19-13 and described in Table 19-13.
Return to Summary Table.
Interrupt Mask Set/Clear
Figure 19-13. IMSC Register
31

10
OEIM
R/W-0h

9
BEIM
R/W-0h

8
PEIM
R/W-0h

1
CTSMIM
R/W-0h

0
RESERVED
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

13
RESERVED
R/W-0h

7
FEIM
R/W-0h

6
RTIM
R/W-0h

5
TXIM
R/W-0h

4
RXIM
R/W-0h

3
RESERVED
R/W-0h

Table 19-13. IMSC Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

OEIM

R/W

Overrun error interrupt mask. A read returns the current mask for
UART's overrun error interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.OEMIS. A write of 0 clears the mask which means
MIS.OEMIS will not reflect the interrupt.

BEIM

R/W

Break error interrupt mask. A read returns the current mask for
UART's break error interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.BEMIS. A write of 0 clears the mask which means
MIS.BEMIS will not reflect the interrupt.

PEIM

R/W

Parity error interrupt mask. A read returns the current mask for
UART's parity error interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.PEMIS. A write of 0 clears the mask which means
MIS.PEMIS will not reflect the interrupt.

FEIM

R/W

Framing error interrupt mask. A read returns the current mask for
UART's framing error interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.FEMIS. A write of 0 clears the mask which means
MIS.FEMIS will not reflect the interrupt.

RTIM

R/W

Receive timeout interrupt mask. A read returns the current mask for
UART's receive timeout interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.RTMIS. A write of 0 clears the mask which means
this bitfield will not reflect the interrupt.
The raw interrupt for receive timeout RIS.RTRIS cannot be set
unless the mask is set (RTIM = 1). This is because the mask acts as
an enable for power saving. That is, the same status can be read
from MIS.RTMIS and RIS.RTRIS.

TXIM

R/W

Transmit interrupt mask. A read returns the current mask for UART's
transmit interrupt. On a write of 1, the mask of the overrun error
interrupt is set which means the interrupt state will be reflected in
MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS
will not reflect the interrupt.

31-11

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1467

UART Registers

www.ti.com

Table 19-13. IMSC Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

RXIM

R/W

Receive interrupt mask. A read returns the current mask for UART's
receive interrupt. On a write of 1, the mask of the overrun error
interrupt is set which means the interrupt state will be reflected in
MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS
will not reflect the interrupt.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CTSMIM

R/W

Clear to Send (CTS) modem interrupt mask. A read returns the
current mask for UART's clear to send interrupt. On a write of 1, the
mask of the overrun error interrupt is set which means the interrupt
state will be reflected in MIS.CTSMMIS. A write of 0 clears the mask
which means MIS.CTSMMIS will not reflect the interrupt.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-2

1468

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

UART Registers

www.ti.com

19.7.1.11 RIS Register (Offset = 3Ch) [reset = X]
RIS is shown in Figure 19-14 and described in Table 19-14.
Return to Summary Table.
Raw Interrupt Status
Figure 19-14. RIS Register
31

10
OERIS
R-0h

9
BERIS
R-0h

8
PERIS
R-0h

1
CTSRMIS
R-X

0
RESERVED
R-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

13
RESERVED
R-0h

7
FERIS
R-0h

6
RTRIS
R-0h

5
TXRIS
R-0h

4
RXRIS
R-0h

3
RESERVED
R-3h

Table 19-14. RIS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

OERIS

Overrun error interrupt status:
This field returns the raw interrupt state of UART's overrun error
interrupt. Overrun error occurs if data is received and the receive
FIFO is full.

BERIS

Break error interrupt status:
This field returns the raw interrupt state of UART's break error
interrupt. Break error is set when a break condition is detected,
indicating that the received data input (UARTRXD input pin) was
held LOW for longer than a full-word transmission time (defined as
start, data, parity and stop bits).

PERIS

Parity error interrupt status:
This field returns the raw interrupt state of UART's parity error
interrupt. Parity error is set if the parity of the received data character
does not match the parity that the LCRH.EPS and LCRH.SPS select.

FERIS

Framing error interrupt status:
This field returns the raw interrupt state of UART's framing error
interrupt. Framing error is set if the received character does not have
a valid stop bit (a valid stop bit is 1).

RTRIS

Receive timeout interrupt status:
This field returns the raw interrupt state of UART's receive timeout
interrupt. The receive timeout interrupt is asserted when the receive
FIFO is not empty, and no more data is received during a 32-bit
period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data, or when a 1 is written
to ICR.RTIC.
The raw interrupt for receive timeout cannot be set unless the mask
is set (IMSC.RTIM = 1). This is because the mask acts as an enable
for power saving. That is, the same status can be read from
MIS.RTMIS and RTRIS.

31-11

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1469

UART Registers

www.ti.com

Table 19-14. RIS Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

TXRIS

Transmit interrupt status:
This field returns the raw interrupt state of UART's transmit interrupt.
When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is
asserted if the number of bytes in transmit FIFO is equal to or lower
than the programmed trigger level (IFLS.TXSEL). The transmit
interrupt is cleared by writing data to the transmit FIFO until it
becomes greater than the trigger level, or by clearing the interrupt
through ICR.TXIC.
When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth
of one location, the transmit interrupt is asserted if there is no data
present in the transmitters single location. It is cleared by performing
a single write to the transmit FIFO, or by clearing the interrupt
through ICR.TXIC.

RXRIS

Receive interrupt status:
This field returns the raw interrupt state of UART's receive interrupt.
When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is
asserted if the receive FIFO reaches the programmed trigger
level (IFLS.RXSEL). The receive interrupt is cleared by reading data
from the receive FIFO until it becomes less than the trigger level, or
by clearing the interrupt through ICR.RXIC.
When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth
of one location, the receive interrupt is asserted if data is received
thereby filling the location. The receive interrupt is cleared by
performing a single read of the receive FIFO, or by clearing the
interrupt through ICR.RXIC.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

CTSRMIS

Clear to Send (CTS) modem interrupt status:
This field returns the raw interrupt state of UART's clear to send
interrupt.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

3-2

1470

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

UART Registers

www.ti.com

19.7.1.12 MIS Register (Offset = 40h) [reset = 0h]
MIS is shown in Figure 19-15 and described in Table 19-15.
Return to Summary Table.
Masked Interrupt Status
Figure 19-15. MIS Register
31

10
OEMIS
R-0h

9
BEMIS
R-0h

8
PEMIS
R-0h

1
CTSMMIS
R-0h

0
RESERVED
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

13
RESERVED
R-0h

7
FEMIS
R-0h

6
RTMIS
R-0h

5
TXMIS
R-0h

4
RXMIS
R-0h

3
RESERVED
R-0h

Table 19-15. MIS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

OEMIS

Overrun error masked interrupt status:
This field returns the masked interrupt state of the overrun interrupt
which is the AND product of raw interrupt state RIS.OERIS and the
mask setting IMSC.OEIM.

BEMIS

Break error masked interrupt status:
This field returns the masked interrupt state of the break error
interrupt which is the AND product of raw interrupt state RIS.BERIS
and the mask setting IMSC.BEIM.

PEMIS

Parity error masked interrupt status:
This field returns the masked interrupt state of the parity error
interrupt which is the AND product of raw interrupt state RIS.PERIS
and the mask setting IMSC.PEIM.

FEMIS

Framing error masked interrupt status: Returns the masked interrupt
state of the framing error interrupt which is the AND product of raw
interrupt state RIS.FERIS and the mask setting IMSC.FEIM.

RTMIS

Receive timeout masked interrupt status:
Returns the masked interrupt state of the receive timeout interrupt.
The raw interrupt for receive timeout cannot be set unless the mask
is set (IMSC.RTIM = 1). This is because the mask acts as an enable
for power saving. That is, the same status can be read from RTMIS
and RIS.RTRIS.

TXMIS

Transmit masked interrupt status:
This field returns the masked interrupt state of the transmit interrupt
which is the AND product of raw interrupt state RIS.TXRIS and the
mask setting IMSC.TXIM.

RXMIS

Receive masked interrupt status:
This field returns the masked interrupt state of the receive interrupt
which is the AND product of raw interrupt state RIS.RXRIS and the
mask setting IMSC.RXIM.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-11

3-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1471

UART Registers

www.ti.com

Table 19-15. MIS Register Field Descriptions (continued)
Bit

1472

Field

Type

Reset

Description

CTSMMIS

Clear to Send (CTS) modem masked interrupt status:
This field returns the masked interrupt state of the clear to send
interrupt which is the AND product of raw interrupt state
RIS.CTSRMIS and the mask setting IMSC.CTSMIM.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

UART Registers

www.ti.com

19.7.1.13 ICR Register (Offset = 44h) [reset = X]
ICR is shown in Figure 19-16 and described in Table 19-16.
Return to Summary Table.
Interrupt Clear
On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
Figure 19-16. ICR Register
31

10
OEIC
W-X

9
BEIC
W-X

8
PEIC
W-X

1
CTSMIC
W-X

0
RESERVED
W-X

RESERVED
W-0h
23

20
RESERVED
W-0h

13
RESERVED
W-0h

7
FEIC
W-X

6
RTIC
W-X

5
TXIC
W-X

4
RXIC
W-X

3
RESERVED
W-X

Table 19-16. ICR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

OEIC

Overrun error interrupt clear:
Writing 1 to this field clears the overrun error interrupt (RIS.OERIS).
Writing 0 has no effect.

BEIC

Break error interrupt clear:
Writing 1 to this field clears the break error interrupt (RIS.BERIS).
Writing 0 has no effect.

PEIC

Parity error interrupt clear:
Writing 1 to this field clears the parity error interrupt (RIS.PERIS).
Writing 0 has no effect.

FEIC

Framing error interrupt clear:
Writing 1 to this field clears the framing error interrupt (RIS.FERIS).
Writing 0 has no effect.

RTIC

Receive timeout interrupt clear:
Writing 1 to this field clears the receive timeout interrupt
(RIS.RTRIS). Writing 0 has no effect.

TXIC

Transmit interrupt clear:
Writing 1 to this field clears the transmit interrupt (RIS.TXRIS).
Writing 0 has no effect.

RXIC

Receive interrupt clear:
Writing 1 to this field clears the receive interrupt (RIS.RXRIS).
Writing 0 has no effect.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Write 0

CTSMIC

Clear to Send (CTS) modem interrupt clear:
Writing 1 to this field clears the clear to send interrupt
(RIS.CTSRMIS). Writing 0 has no effect.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Write 0.

31-11

3-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Universal Asynchronous Receiver/Transmitter (UART)

1473

UART Registers

www.ti.com

19.7.1.14 DMACTL Register (Offset = 48h) [reset = 0h]
DMACTL is shown in Figure 19-17 and described in Table 19-17.
Return to Summary Table.
DMA Control
Figure 19-17. DMACTL Register
31

2
DMAONERR
R/W-0h

1
TXDMAE
R/W-0h

0
RXDMAE
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

5
RESERVED
R/W-0h

Table 19-17. DMACTL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-3

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

DMAONERR

R/W

DMA on error. If this bit is set to 1, the DMA receive request outputs
(for single and burst requests) are disabled when the UART error
interrupt is asserted (more specifically if any of the error interrupts
RIS.PERIS, RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted).

TXDMAE

R/W

Transmit DMA enable. If this bit is set to 1, DMA for the transmit
FIFO is enabled.

RXDMAE

R/W

Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO
is enabled.

1474

Universal Asynchronous Receiver/Transmitter (UART)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Chapter 20
SWCU117G – February 2015 – Revised February 2017

Synchronous Serial Interface (SSI)
This chapter describes the synchronous serial interface (SSI).
Topic

20.1
20.2
20.3
20.4
20.5
20.6
20.7

...........................................................................................................................
Synchronous Serial Interface ...........................................................................
Block Diagram ................................................................................................
Signal Description...........................................................................................
Functional Description ....................................................................................
DMA Operation ...............................................................................................
Initialization and Configuration .........................................................................
SSI Registers..................................................................................................

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Page

1476
1477
1478
1478
1487
1487
1489

Synchronous Serial Interface (SSI)

1475

Synchronous Serial Interface

www.ti.com

20.1 Synchronous Serial Interface
The two SSI modules of the CC26x0 and CC13x0 devices have the following features:
• Programmable interface operation for Motorola SPI, MICROWIRE, or TI SSIs
• Configurable as a master or a slave on the interface
• Programmable clock bit rate and prescaler
• Separate transmit (TX) and receive (RX) first-in first-out buffers (FIFOs), each 16-bits wide and
8-locations deep
• Programmable data frame size from 4 bits to 16 bits
• Internal loopback test mode for diagnostic and debug testing
• Interrupts for transmit and receive FIFOs, overrun and time-out interrupts, and DMA done interrupts
• Efficient transfers using micro direct memory access controller ( DMA):
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains four or more entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted when
FIFO contains four or fewer entries

1476

Synchronous Serial Interface (SSI)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Block Diagram

www.ti.com

20.2 Block Diagram
Figure 20-1 shows the SSI block diagram.
Figure 20-1. SSI Module Block Diagram
DMA control
DMA Request
SSI_DMACR

Interrupt

Interrupt Control

SSI_IMSC
SSI_MIS
SSI_RIS

TX FIFO
8 x 16

SSI_ICR
Control / Status

SSIn_TX
SSI_CR0
SSI n_RX

SSI_CR1
SSI_SR

Transmit /
receive logic

SSI_DR

SSIn_CLK

SSIn_FSS
RX FIFO
8 x 16

Clock Prescaler
PERDMACLK

SSI_CPSR

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Synchronous Serial Interface (SSI)

1477

Signal Description

www.ti.com

20.3 Signal Description
Table 20-1 lists the external signals of the SSI module and describes the function of each. The SSI signals
are selected in the IOC module through the IOCFGn registers. For more information on configuration of
GPIOs, see Chapter 4.
Table 20-1. SSI Signals
Signal Name

Pin Number

Pin Type (1)

Description

SSI0_CLK

I/O

SSI module 0 clock pin

SSI0_FSS

I/O

SSI module 0 frame pin

SSI0_RX

SSI module 0 RX pin

SSI0_TX

Assigned in the I/O
Controller

SSI1_CLK
SSI1_FSS

SSI module 0 TX pin

I/O

SSI module 1 clock pin

I/O

SSI module 1 frame pin

SSI1_RX

SSI module 1 RX pin

SSI1_TX

SSI module 1 TX pin

(1)

I = Input; O = Output; I/O = Bidrectional

20.4 Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. Internal FIFO memories buffer the transmit and receive
paths, allowing independent storage of up to eight 16-bit values in both transmit and receive modes. The
SSI also supports the DMA interface. The TX and RX FIFOs can be programmed as destination or
source addresses in the DMA module. The DMA operation is enabled by setting the appropriate bits in
the SSI:DMACR register.

20.4.1 Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock.
The bit rates are supported to 2 MHz and higher, with maximum bit rate is determined by peripheral
devices.
The serial bit rate is derived by dividing down the input clock (SysClk). First, the clock is divided by an
even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale Register
(SSI:CPSR) (see Section 20.7.1.5). The clock is further divided by a value from 1 to 256, which is 1 +
SCR, where SCR is the value programmed in the SSI Control 0 Register (SSI:CR0) (see
Section 20.7.1.1).
Equation 5 defines the frequency of the output clock SSIn_CLK.
SSIn_CLK = PERDMACLK / [CPSDVSR × (1 + SCR)]
NOTE:

(5)

For slave mode, the core clock (PERDMACLK) must be at least 12 times faster than
SSIn_CLK.
For master mode, the core clock (PERDMACLK) must be at least two times faster than
SSIn_CLK.

20.4.2 FIFO Operation
20.4.2.1 Transmit FIFO
The common TX FIFO is a 16-bit-wide, 8-location-deep, first-in first-out memory buffer. The CPU writes
data to the FIFO by writing the SSI Data Register, SSI:DR (see Section 20.7.1.3), and data is stored in the
FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the TX FIFO before serial conversion
and transmission to the attached slave or master, respectively, through the SSIn_TX pin.
1478

Synchronous Serial Interface (SSI)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

In slave mode, the SSI transmits data each time the master initiates a transaction. If the TX FIFO is empty
and the master initiates, the slave transmits the eighth most-recent value in the transmit FIFO. If less than
eight values are successfully written to the TX FIFO since the power domain for the SSI module is
powered up, then 0 is transmitted. User or software is responsible to make valid data available in the FIFO
as needed. The SSI can be configured to generate an interrupt or a µDMA request when the FIFO is
empty.
20.4.2.2 Receive FIFO
The common RX FIFO is a 16-bit-wide, 8-location-deep, first-in-first-out memory buffer. Received data
from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by
reading the SSI:DR register.
When configured as a master or slave, serial data received through the SSIn_RX pin is registered before
parallel loading into the attached slave or master RX FIFO, respectively.

20.4.3 Interrupts
The SSI can generate interrupts when the following conditions are observed:
• TX FIFO service (when the TX FIFO is half full or less)
• RX FIFO service (when the RX FIFO is half full or more)
• RX FIFO time-out
• RX FIFO overrun
All interrupt events are ORed together before sent to the event fabric, so the SSI generates a single
interrupt request to the controller regardless of the number of active interrupts. The TX FIFO, RX FIFO,
RX time-out, and RX overrun interrupts can be masked by clearing the appropriate bit in the SSI:IMSC
register. Setting the appropriate mask bit in the SSI:IMSC register enables the interrupt. RX DMA done
and TX DMA done interrupts can be masked by setting the appropriate bit in the UDMA Channel Request
Done Mask Register (UDMA:DONEMASK). Clearing the appropriate bit in the UDMA:DONEMASK register
enables the RX or TX DMA done interrupt.
The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status Register
(SSI:RIS) and the SSI Masked Interrupt Status Register (SSI:MIS) (see Section 20.7.1.7 and
Section 20.7.1.8, respectively).
The receive FIFO service interrupt request SSI:RIS.RXRIS is asserted when there are four or more valid
entries in the receive FIFO.
The transmit FIFO service interrupt request SSI:RIS.TXRIS is asserted when there are four or fewer valid
entries in the transmit FIFO. The transmitter interrupt is not qualified with the SSP enable signal, which
allows data to be written to the transmit FIFO before enabling the SSP and the interrupts and allows the
SSP and interrupts to be enabled so that data can be written to the transmit FIFO by an interrupt service
routine (ISR).
The receive overrun interrupt SSI:RIS.RORRIS request is asserted when the FIFO is already full and an
additional data frame is received, causing an overrun of the FIFO. Data is overwritten in the receive shift
register, but not in the FIFO.
The RX FIFO has a time-out period of 32 periods at the rate of SSIn_CLK (whether or not SSIn_CLK is
currently active), and is started when the RX FIFO goes from empty to not empty. If the RX FIFO is
emptied before 32 clocks pass, the time-out period is reset. As a result, the ISR clears the RX FIFO timeout interrupt just after reading out the RX FIFO by setting the RTIC bit in the SSI Interrupt Clear SSI:ICR
register to 1.
NOTE: The interrupt must not be cleared so late that the ISR returns before the interrupt is actually
cleared, or the ISR may be reactivated unnecessarily.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Synchronous Serial Interface (SSI)

1479

Functional Description

www.ti.com

20.4.4 Frame Formats
Each data frame is between 4- and 16-bits long, depending on the size of data programmed, and is
transmitted starting with the most significant bit (MSB). The following three basic frame types can be
selected:
• TI synchronous serial
• Motorola™ SPI
• National MICROWIRE
For all three formats, the serial clock (SSIn_CLK) is held inactive while the SSI is idle and SSIn_CLK
transitions at the programmed frequency only during active transmission or reception of data. The IDLE
state of SSIn_CLK provides a receive time-out indication that occurs when the RX FIFO still contains data
after a time-out period.
For Motorola SPI and MICROWIRE frame formats, the serial frame (SSIn_FSS) pin is active low and is
asserted (pulled down) during the entire transmission of the frame.
For TI synchronous serial frame format, the SSIn_FSS pin is pulsed for one serial clock period which
starts at its rising edge before the transmission of each frame. For this frame format, both the SSI and the
off-chip slave device drive their output data on the rising edge of SSIn_CLK and latch data from the other
device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a special
master-slave messaging technique that operates at half-duplex. When a frame begins, an 8-bit control
message is transmitted to the off-chip slave. No incoming data is received by the SSI during this
transmission. After the message is sent, the off-chip slave decodes it and responds with the requested
data after waiting one serial clock after the last bit of the 8-bit control message is sent. The returned data
can be 4- to 16-bits long, making the total frame length anywhere from 13 to 25 bits.
20.4.4.1 Texas Instruments' Synchronous Serial Frame Format
Figure 20-2 shows the TI synchronous serial frame format for a single transmitted frame.
Figure 20-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIn_Clk
SSIn_Fss
SSIn_Tx/SSIn_Rx

MSB

LSB
4 to 16 bits

SSIn_CLK and SSIn_FSS are forced low and the transmit data line SSIn_TX is placed in the tri-state
condition whenever the SSI is idle. When the bottom entry of the TX FIFO contains data, SSIn_FSS is
pulsed high for one SSIn_CLK period. The transmitted value is also transferred from the TX FIFO to the
serial shift register of the transmit logic. On the next rising edge of SSIn_CLK, the MSB of the 4- to 16-bit
data frame is shifted out on the SSIn_TX pin. Likewise, the MSB of the received data is shifted onto the
SSIn_RX pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on each
falling edge of SSIn_CLK. The received data is transferred from the serial shifter to the RX FIFO on the
first rising edge of SSIn_CLK after the least significant bit (LSB) is latched.

1480

Synchronous Serial Interface (SSI)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

Figure 20-3 shows the TI synchronous serial frame format when back-to-back frames are transmitted.
Figure 20-3. TI Synchronous Serial Frame Format (Continuous Transfer)
SSIn_Clk
SSIn_Fss
LSB

SSIn_Tx/SSIn_Rx
4 to 16 bits

20.4.4.2 Motorola SPI Frame Format
The Motorola SPI interface is a 4-wire interface where the SSIn_FSS signal behaves as a slave select.
The main feature of the Motorola SPI format is that the inactive state and phase of the SSIn_CLK signal
can be programmed through the SPO and SPH bits in the SSI:CR0 control register.
20.4.4.2.1 SPO Clock Polarity Bit
When the SPO clock polarity control bit is clear, the bit produces a steady-state low value on the
SSIn_CLK pin. If the SPO bit is set, the bit places a steady-state high value on the SSIn_CLK pin when
data is not being transferred.
20.4.4.2.2 SPH Phase-Control Bit
The SPH phase-control bit selects the clock edge that captures data, and allows it to change state. The
state of this bit has the most impact on the first bit transmitted, by either allowing or not allowing a clock
transition before the first data capture edge. When the SPH phase-control bit is clear, data is captured on
the first clock edge transition. If the SPH bit is set, data is captured on the second clock edge transition.
20.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
Figure 20-4 and Figure 20-5 show single and continuous transmission signal sequences for Motorola SPI
format with SPO = 0 and SPH = 0, respectively.
Figure 20-4. Motorola SPI Format (Single Transfer) With SPO = 0 and SPH = 0
SSIn_Clk
SSn_IFss

SSIn_Rx

LSB

MSB

4 to 16 bits
SSIn_Tx

MSB

LSB

Note: Q is undefined.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Synchronous Serial Interface (SSI)

1481

Functional Description

www.ti.com

Figure 20-5. Motorola SPI Format (Continuous Transfer) With SPO = 0 and SPH = 0
SSIn_Clk
SSIn_Fss
SSIn_Rx LSB

LSB

MSB

4 to16 bits
SSIn_Tx LSB

In
•
•
•
•
•

MSB

LSB

MSB

this configuration, the following occurs during idle periods:
SSIn_CLK is forced low
SSIn_FSS is forced high
The transmit data line SSIn_TX is arbitrarily forced low
When the SSI is configured as a master, the SSI enables the SSIn_CLK pad
When the SSI is configured as a slave, the SSI disables the SSIn_CLK pad

If the SSI is enabled and valid data is in the TX FIFO, the SSIn_FSS master signal is driven low at the
start of transmission which causes enabling of slave data onto the SSIn_RX input line of the master. The
master SSIn_TX output pad is enabled.
One-half SSIn_CLK period later, valid master data is transferred to the SSIn_TX pin. Once both the
master and slave data are set, the SSIn_CLK master clock pin goes high after an additional one-half
SSIn_CLK period.
The data is now captured on the rising edges and propagated on the falling edges of the SSIn_CLK
signal.
For a single-word transmission after all bits of the data word are transferred, the SSIn_FSS line is returned
to its IDLE high state one SSIn_CLK period after the last bit is captured.
For continuous back-to-back transmissions, the SSIn_FSS signal must pulse high between each data
word transfer because the slave-select pin freezes the data in its serial peripheral register and does not
allow altering of the data if the SPH bit is clear. The master device must raise the SSIn_FSS pin of the
slave device between each data transfer to enable the serial peripheral data write. When the continuous
transfer completes, the SSIn_FSS pin is returned to its IDLE state one SSIn_CLK period after the last bit
is captured.

1482

Synchronous Serial Interface (SSI)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

20.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
Figure 20-6 shows the transfer signal sequence for Motorola SPI format with SPO = 0 and SPH = 1, which
covers both single and continuous transfers.
Figure 20-6. Motorola SPI Frame Format With SPO = 0 and SPH = 1
SSIn_Clk
SSIn_Fss

SSIn_Rx

Q
MSB

LSB

4 to 16 bits
SSIn_Tx

MSB

LSB

Note: Q is undefined.

In
•
•
•
•
•

If the SSI is enabled and valid data is in the TX FIFO, the SSIn_FSS master signal goes low at the start of
transmission. The master SSIn_TX output is enabled. After an additional one-half SSIn_CLK period, both
master and slave valid data are enabled onto their respective transmission lines. At the same time,
SSIn_CLK is enabled with a rising-edge transition. Data is then captured on the falling edges and
propagated on the rising edges of the SSIn_CLK signal.
For a single-word transfer, after all bits are transferred, the SSIn_FSS line is returned to its IDLE high
state one SSIn_CLK period after the last bit is captured.
For continuous back-to-back transfers, the SSIn_FSS pin is held low between successive data words and
terminates like a single-word transfer.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Synchronous Serial Interface (SSI)

1483

Functional Description

www.ti.com

20.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
Figure 20-7 and Figure 20-8 show single and continuous transmission signal sequences, respectively, for
Motorola SPI format with SPO = 1 and SPH = 0.
Figure 20-7. Motorola SPI Frame Format (Single Transfer) With SPO = 1 and SPH = 0
SSIn_Clk
SSIn_Fss

SSIn_Rx

MSB

LSB

4 to 16 bits
LSB

MSB

SSIn_Tx

Note: Q is undefined.

Figure 20-8. Motorola SPI Frame Format (Continuous Transfer) With SPO = 1 and SPH = 0
SSIn_Clk

SSIn_Fss
SSIn_Tx/SSIn_Rx LSB

MSB

LSB

MSB

4 to 16 bits

In
•
•
•
•
•

this configuration, the following occurs during idle periods:
SSIn_CLK is forced high
SSIn_FSS is forced high
The transmit data line SSIn_TX is arbitrarily forced low
When the SSI is configured as a master, the SSI enables the SSIn_CLK pad
When the SSI is configured as a slave, the SSI disables the SSIn_CLK pad

If the SSI is enabled and valid data is in the TX FIFO, the SSIFss master signal goes low at the start of
transmission and transfers slave data onto the SSIn_RX line of the master immediately. The master
SSIn_TX output pad is enabled.
One-half SSIn_CLK period later, valid master data is transferred to the SSIn_TX line. When both the
master and slave data have been set, the SSIn_CLK master clock pin becomes low after one additional
half SSIn_CLK period. Data is captured on the falling edges and propagated on the rising edges of the
SSIn_CLK signal.
For a single-word transmission after all bits of the data word are transferred, the SSIn_FSS line is returned
to its IDLE high state one SSIn_CLK period after the last bit is captured.
For continuous back-to-back transmissions, the SSIn_FSS signal must pulse high between each data
word transfer as the slave-select pin freezes the data in its serial peripheral register and keeps it from
being altered if the SPH bit is clear. The master device must raise the SSIn_FSS pin of the slave device
between each data transfer to enable the serial peripheral data write. When the continuous transfer
completes, the SSIn_FSS pin returns to its IDLE state one SSIn_CLK period after the last bit is captured.

1484

Synchronous Serial Interface (SSI)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

20.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
Figure 20-9 shows the transfer signal sequence for Motorola SPI format with SPO = 1 and SPH = 1, which
covers both single and continuous transfers.
Figure 20-9. Motorola SPI Frame Format With SPO = 1 and SPH = 1
SSIn_Clk
SSIn_Fss

SSIn_Rx

MSB

LSB

4 to 16 bits
MSB

SSIn_Tx

LSB

Note: Q is undefined.

In
•
•
•
•
•

this configuration, the following occurs during idle periods:
SSIClk is forced high
SSIn_FSS is forced high
The transmit data line SSIn_TX is arbitrarily forced low
When the SSI is configured as a master, the SSI enables the SSIn_CLK pad
When the SSI is configured as a slave, the SSI disables the SSIn_CLK pad

If the SSI is enabled and valid data is in the TX FIFO, the start of transmission is signified by the
SSIn_FSS master signal going low. The master SSIn_TX output pad is enabled. After an additional onehalf SSIn_CLK period, both master and slave data are enabled onto their respective transmission lines. At
the same time, SSIn_CLK is enabled with a falling-edge transition. Data is then captured on the rising
edges and propagated on the falling edges of the SSIn_CLK signal.
For a single word transmission, after all bits are transferred, the SSIn_FSS line returns to its IDLE high
state one SSIn_CLK period after the last bit is captured.
For continuous back-to-back transmissions, the SSIn_FSS pin remains in its active low state until the final
bit of the last word is captured and then returns to its IDLE state.
For continuous back-to-back transfers, the SSIn_FSS pin is held low between successive data words and
terminates like a single-word transfer.
20.4.4.7 MICROWIRE Frame Format
Figure 20-10 shows the MICROWIRE frame format for a single frame. Figure 20-11 shows the same
format when back-to-back frames are transmitted.
Figure 20-10. MICROWIRE Frame Format (Single Frame)
SSIn_Clk
SSIn_Fss

SSIn_Tx

LSB

MSB
8-bit control

SSIn_Rx

MSB

LSB
4 to 16 bits
output data

MICROWIRE format is similar to SPI format, except that transmission is half-duplex and uses a masterslave message passing technique. Each serial transmission begins with an 8-bit control word that is
transmitted from the SSI to the off-chip slave device. During this transmission, the SSI does not receive
incoming data. After the message is sent, the off-chip slave decodes it and waits one serial clock after the
last bit of the 8-bit control message is sent. The off-chip slave then responds with the required data. The
returned data is 4- to 16-bits long, making the total frame length anywhere from 13 to 25 bits.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Synchronous Serial Interface (SSI)

1485

Functional Description

In
•
•
•

www.ti.com

this configuration, the following occurs during idle periods:
SSIn_CLK is forced low
SSIn_FSS is forced high
The transmit data line SSIn_TX is arbitrarily forced low

Writing a control byte to the TX FIFO triggers a transmission. The falling edge of SSIn_FSS transfers the
value in the bottom entry of the TX FIFO to the serial shift register of the transmit logic and shifts the MSB
of the 8-bit control frame out onto the SSIn_TX pin. SSIn_FSS remains low for the duration of the frame
transmission. The SSIn_RX pin remains in the tri-state condition during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on each rising edge of
SSIn_CLK. After the last bit is latched by the slave device, the control byte is decoded during a one clock
wait state and the slave responds by transmitting data back to the SSI. Each bit is driven onto the
SSIn_RX line on the falling edge of SSIn_CLK. The SSI latches each bit on the rising edge of SSIn_CLK.
At the end of the frame for single transfers, the SSIFss signal is pulled high one clock period after the last
bit is latched in the receive serial shifter transferring the data to the RX FIFO.
NOTE: The off-chip slave device can place the receive line in a tri-state condition either on the
falling edge of SSIn_CLK (after the LSB has been latched by the receive shifter), or when
the SSIn_FSS pin goes high.

For continuous transfers, data transmission begins and ends like a single transfer, but the SSIn_FSS line
is held low and data transmits back-to-back. The control byte of the next frame follows the LSB of the
received data from the current frame. After the LSB of the frame is latched into the SSI, each received
value is transferred from the receive shifter on the falling edge of SSIn_CLK.
Figure 20-11. MICROWIRE Frame Format (Continuous Transfer)
SSIn_Clk
SSIn_Fss
SSIn_Tx

LSB

MSB
8-bit control

SSIn_Rx

MSB

LSB
4 to 16 bits
output data

In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIn_CLK after SSIFss has gone low. Masters driving a free-running SSIn_CLK must ensure that the
SSIFss signal has sufficient setup and hold margins compared to the rising edge of SSIn_CLK.
Figure 20-12 shows these setup and hold time requirements. With respect to the SSIn_CLK rising edge on
which the first bit of receive data is to be sampled by the SSI slave, SSIn_FSS must have a setup of at
least two times the period of SSIn_CLK on which the SSI operates. With respect to the SSIn_CLK rising
edge previous to this edge, SSIn_FSS must have a hold of at least one SSIn_CLK period.
Figure 20-12. MICROWIRE Frame Format, SSIFss Input Setup, and Hold Requirements
tSetup = (2*t SSIn_Clk )
tHold = t SSIn_Clk
SSIn_Clk
SSIn_Fss

SSIn_Rx
First RX data to besampled by SSI slave

1486

Synchronous Serial Interface (SSI)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

DMA Operation

www.ti.com

20.5 DMA Operation
The SSI peripheral provides an interface to the DMA controller with separate channels for transmit and
receive. The SSI DMA Control Register (SSI:DMACR) allows the DMA to operate the SSI. When DMA
operation is enabled, the SSI asserts a DMA request on the receive or transmit channel when the
associated FIFO can transfer data. For the receive channel, a single transfer request is asserted
whenever any data is in the RX FIFO. Whenever data in the RX FIFO is four or more items, a burst
transfer request is asserted. For the transmit channel, a single transfer request is asserted whenever at
least one empty location is in the TX FIFO. Whenever the TX FIFO has four or more empty slots, the burst
request is asserted. The DMA controller handles the single and burst DMA transfer requests
automatically depending on how the DMA channel is configured. To enable DMA operation for the
receive channel, set the SSI:DMACR RXDMAE register bit. To enable DMA operation for the transmit
channel, set the SSI:MAC RTXDMAE register bit. If the DMA is enabled and appropriate bits are cleared
in the DMA Done Mask Register (UDMA:DONEMASK) the DMA controller triggers an interrupt when a
transfer completes. The interrupt occurs on the SSI interrupt vector. If interrupts are used for SSI
operation and the DMA is enabled, the SSI interrupt handler must be designed to handle the DMA
completion interrupt. The status of TX and RX DMA done interrupts can be read from the Channel
Request Done Register (UDMA:REQDONE). For clearing the TX and RX DMA done interrupts, the
corresponding bits in the UDMA:REQDONE register must be 1.
For more details about programming the DMA controller, see Chapter 12.

20.6 Initialization and Configuration
To enable and initialize the SSI, perform the following steps:
1. Ensure the corresponding power domain is powered up properly. For details, refer to .
2. Enable the appropriate SSI module in PRCM by writing to the PRCM:SSICLKGR register, the
PRCM:SSICLKGS register, and the PRCM:SSICLKGDS register, or by using the driverlib functions:
PRCMPeripheralRunEnable(uint32_t)
PRCMPeripheralSleepEnable(uint32_t)
PRCMPeripheralDeepSleepEnable(uint32_t)
and then loading the setting to clock controller by writing to PRCM:CLKLOADCTL

or by using the driverlib function.
PRCMLoadSet().

3. Configure the IOC module to route the SSIn_RX, SSIn_TX, SSIn_FSS, and SSIn_CLK functionalities
from I/Os to the SSI module. IOCFGn.PORTID must be written to the correct PORTIDs.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSI:CR1 register is clear before making any configuration changes.
2. Select whether the SSI is a master or slave:
(a) For master operations, set the SSI:CR1 register to 0x0000 0000.
(b) For slave mode (output enabled), set the SSI:CR1 register to 0x0000 0004.
(c) For slave mode (output disabled), set the SSI:CR1 register to 0x0000 000C.
3. Configure the clock prescale divisor by writing to the SSI:CPSR register.
4. Write the SSI:CR0 register with the following configuration:
• Serial clock rate (SCR)
• Desired clock phase and polarity, if using Motorola SPI mode (SPH and SPO)
• The protocol mode: Motorola SPI, TI SSF, MICROWIRE (FRF)
• The data size (DSS)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Synchronous Serial Interface (SSI)

1487

Initialization and Configuration

www.ti.com

5. Optionally, configure the DMA channel (see Chapter 12) and enable the DMA options in the
SSI:DMACR register.
6. Enable the SSI by setting the SSE bit in the SSI:CR1 register.
As
•
•
•
•

an example, assume that the SSI configuration is required to operate with the following parameters:
Master operation
Texas Instruments SSI mode
1-Mbps bit rate
8 data bits

Assuming the system clock is 48 MHz, the bit-rate calculation is shown in Equation 6.
SSIn_CLK = PERDMACLK / [CPSDVSR × (1 + SCR)] 1 × 106 = 20 × 106 / [CPSDVSR × (1 + SCR)] 1000000 bps =
48000000 Hz / [2 × (1 + 23)]
(6)

In this case, if CPSDVSR = 0x2, SCR must be 0x18.
The configuration sequence is:
1. Ensure that the SSE bit in the SSI:CR1 register is clear.
2. Write the SSI:CR1 register with a value of 0x0000 0000.
3. Write the SSI:CPSR register with a value of 0x0000 0002.
4. Write the SSI:CR0 register with a value of 0x0000 1817.
5. The SSI is then enabled by setting the SSE bit in the SSI:CR1 register.

1488

Synchronous Serial Interface (SSI)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

SSI Registers

www.ti.com

20.7 SSI Registers
20.7.1 SSI Registers
Table 20-2 lists the memory-mapped registers for the SSI. All register offset addresses not listed in
Table 20-2 should be considered as reserved locations and the register contents should not be modified.
Table 20-2. SSI Registers
Offset

Acronym

Section

CR0

Control 0

Section 20.7.1.1

CR1

Control 1

Section 20.7.1.2

Data

Section 20.7.1.3

Status

Section 20.7.1.4

10h

CPSR

Clock Prescale

Section 20.7.1.5

14h

IMSC

Interrupt Mask Set and Clear

Section 20.7.1.6

18h

RIS

Raw Interrupt Status

Section 20.7.1.7

1Ch

MIS

Masked Interrupt Status

Section 20.7.1.8

20h

ICR

Interrupt Clear

Section 20.7.1.9

24h

DMACR

DMA Control

Section 20.7.1.10

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Synchronous Serial Interface (SSI)

1489

SSI Registers

www.ti.com

20.7.1.1 CR0 Register (Offset = 0h) [reset = 0h]
CR0 is shown in Figure 20-13 and described in Table 20-3.
Return to Summary Table.
Control 0
Figure 20-13. CR0 Register
31

11
SCR
R/W-0h

24
23
RESERVED
R-0h
8

7
SPH
R/W0h

6
SPO
R/W0h

FRF
R/W-0h

DSS
R/W-0h

Table 20-3. CR0 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-8

SCR

R/W

Serial clock rate:
This is used to generate the transmit and receive bit rate of the SSI.
The bit rate is
(SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR).
SCR is a value from 0-255.

SPH

R/W

CLKOUT phase (Motorola SPI frame format only)
This bit selects the clock edge that captures data and enables it to
change state. It
has the most impact on the first bit transmitted by either permitting or
not permitting a clock transition before the first data capture edge.
0h = 1ST_CLK_EDGE : Data is captured on the first clock edge
transition.
1h = 2ND_CLK_EDGE : Data is captured on the second clock edge
transition.

SPO

R/W

CLKOUT polarity (Motorola SPI frame format only)
0h = SSI produces a steady state LOW value on the
CLKOUT pin when data is not being transferred.
1h = SSI produces a steady state HIGH value on the CLKOUT pin
when data is not being transferred.

5-4

1490

FRF

Synchronous Serial Interface (SSI)

R/W

Frame format.
The supported frame formats are Motorola SPI, TI synchronous
serial and National Microwire.
Value 0'b11 is reserved and shall not be used.
0h = Motorola SPI frame format
1h = TI synchronous serial frame format
2h = National Microwire frame format

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

SSI Registers

www.ti.com

Table 20-3. CR0 Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

3-0

DSS

R/W

Data Size Select.
Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used.
3h = 4_BIT : 4-bit data
4h = 5_BIT : 5-bit data
5h = 6_BIT : 6-bit data
6h = 7_BIT : 7-bit data
7h = 8_BIT : 8-bit data
8h = 9_BIT : 9-bit data
9h = 10_BIT : 10-bit data
Ah = 11_BIT : 11-bit data
Bh = 12_BIT : 12-bit data
Ch = 13_BIT : 13-bit data
Dh = 14_BIT : 14-bit data
Eh = 15_BIT : 15-bit data
Fh = 16_BIT : 16-bit data

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Synchronous Serial Interface (SSI)

1491

SSI Registers

www.ti.com

20.7.1.2 CR1 Register (Offset = 4h) [reset = 0h]
CR1 is shown in Figure 20-14 and described in Table 20-4.
Return to Summary Table.
Control 1
Figure 20-14. CR1 Register
31

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

3
SOD
R/W0h

2
MS
R/W0h

1
SSE
R/W0h

0
LBM
R/W0h

Table 20-4. CR1 Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SOD

R/W

Slave-mode output disabled
This bit is relevant only in the slave mode, MS=1. In multiple-slave
systems, it is possible for an SSI master to broadcast a message to
all slaves in the system while ensuring that only one slave drives
data onto its serial output line. In such systems the RXD lines from
multiple slaves could be tied together. To operate in such systems,
this bitfield can be set if the SSI slave is not supposed to drive the
TXD line:
0: SSI can drive the TXD output in slave mode.
1: SSI cannot drive the TXD output in slave mode.

R/W

Master or slave mode select. This bit can be modified only when SSI
is disabled, SSE=0.
0h = Device configured as master
1h = Device configured as slave

SSE

R/W

Synchronous serial interface enable.
0h = SSI_DISABLED : Operation disabled
1h = SSI_ENABLED : Operation enabled

LBM

R/W

Loop back mode:
0: Normal serial port operation enabled.
1: Output of transmit serial shifter is connected to input of receive
serial shifter internally.

31-4

1492

Synchronous Serial Interface (SSI)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

SSI Registers

www.ti.com

20.7.1.3 DR Register (Offset = 8h) [reset = X]
DR is shown in Figure 20-15 and described in Table 20-5.
Return to Summary Table.
Data
16-bits wide data register:
When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As
data values are removed by the receive logic from the incoming data frame, they are placed into the entry
in the receive FIFO, pointed to by the current FIFO write pointer.
When written, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are
removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit
serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit
FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically rightjustified in the receive buffer.
Figure 20-15. DR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7
DATA
R/W-X

Table 20-5. DR Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

DATA

R/W

Transmit/receive data
The values read from this field or written to this field must be rightjustified when SSI is programmed for a data size that is less than 16
bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by
transmit logic. The receive logic automatically right-justifies.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Synchronous Serial Interface (SSI)

1493

SSI Registers

www.ti.com

20.7.1.4 SR Register (Offset = Ch) [reset = 3h]
SR is shown in Figure 20-16 and described in Table 20-6.
Return to Summary Table.
Status
Figure 20-16. SR Register
31

10
9
RESERVED
R-0h

24
23
RESERVED
R-0h
8

4
BSY
R-0h

3
RFF
R-0h

2
RNE
R-0h

1
TNF
R-1h

0
TFE
R-1h

Table 20-6. SR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BSY

Serial interface busy:
0: SSI is idle
1: SSI is currently transmitting and/or receiving a frame or the
transmit FIFO is not empty.

RFF

Receive FIFO full:
0: Receive FIFO is not full.
1: Receive FIFO is full.

RNE

Receive FIFO not empty
0: Receive FIFO is empty.
1: Receive FIFO is not empty.

TNF

Transmit FIFO not full:
0: Transmit FIFO is full.
1: Transmit FIFO is not full.

TFE

Transmit FIFO empty:
0: Transmit FIFO is not empty.
1: Transmit FIFO is empty.

31-5

1494

Synchronous Serial Interface (SSI)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

SSI Registers

www.ti.com

20.7.1.5 CPSR Register (Offset = 10h) [reset = 0h]
CPSR is shown in Figure 20-17 and described in Table 20-7.
Return to Summary Table.
Clock Prescale
Figure 20-17. CPSR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
CPSDVSR
R/W-0h

Table 20-7. CPSR Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

CPSDVSR

R/W

Clock prescale divisor:
This field specifies the division factor by which the input system
clock to SSI must be internally divided before further use.
The value programmed into this field must be an even non-zero
number (2-254). The least significant bit of the programmed number
is hard-coded to zero. If an odd number is written to this register,
data read back from
this register has the least significant bit as zero.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Synchronous Serial Interface (SSI)

1495

SSI Registers

www.ti.com

20.7.1.6 IMSC Register (Offset = 14h) [reset = 0h]
IMSC is shown in Figure 20-18 and described in Table 20-8.
Return to Summary Table.
Interrupt Mask Set and Clear
Figure 20-18. IMSC Register
31

3
TXIM
R/W-0h

2
RXIM
R/W-0h

1
RTIM
R/W-0h

0
RORIM
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

RESERVED
R-0h

Table 20-8. IMSC Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TXIM

R/W

Transmit FIFO interrupt mask:
A read returns the current mask for transmit FIFO interrupt. On a
write of 1, the mask for transmit FIFO interrupt is set which means
the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears
the mask which means MIS.TXMIS will not reflect the interrupt.

RXIM

R/W

Receive FIFO interrupt mask:
A read returns the current mask for receive FIFO interrupt. On a
write of 1, the mask for receive FIFO interrupt is set which means
the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears
the mask which means MIS.RXMIS will not reflect the interrupt.

RTIM

R/W

Receive timeout interrupt mask:
A read returns the current mask for receive timeout interrupt. On a
write of 1, the mask for receive timeout interrupt is set which means
the interrupt state will be reflected in MIS.RTMIS. A write of 0 clears
the mask which means MIS.RTMIS will not reflect the interrupt.

RORIM

R/W

Receive overrun interrupt mask:
A read returns the current mask for receive overrun interrupt. On a
write of 1, the mask for receive overrun interrupt is set which means
the interrupt state will be reflected in MIS.RORMIS. A write of 0
clears the mask which means MIS.RORMIS will not reflect the
interrupt.

31-4

1496

Synchronous Serial Interface (SSI)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

SSI Registers

www.ti.com

20.7.1.7 RIS Register (Offset = 18h) [reset = 8h]
RIS is shown in Figure 20-19 and described in Table 20-9.
Return to Summary Table.
Raw Interrupt Status
Figure 20-19. RIS Register
31

3
TXRIS
R-1h

2
RXRIS
R-0h

1
RTRIS
R-0h

0
RORRIS
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

RESERVED
R-0h

Table 20-9. RIS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TXRIS

Raw transmit FIFO interrupt status:
The transmit interrupt is asserted when there are four or fewer valid
entries in the transmit FIFO. The transmit interrupt is not qualified
with the SSI enable signal. Therefore one of the following ways can
be used:
- data can be written to the transmit FIFO prior to enabling the SSI
and the
interrupts.
- SSI and interrupts can be enabled so that data can be written to
the transmit FIFO by an interrupt service routine.

RXRIS

Raw interrupt state of receive FIFO interrupt:
The receive interrupt is asserted when there are four or more valid
entries in the receive FIFO.

RTRIS

Raw interrupt state of receive timeout interrupt:
The receive timeout interrupt is asserted when the receive FIFO is
not empty and SSI has remained idle for a fixed 32 bit period. This
mechanism can be used to notify the user that data is still present in
the receive FIFO and requires servicing. This interrupt is deasserted
if the receive FIFO becomes empty by subsequent reads, or if new
data is received on RXD.
It can also be cleared by writing to ICR.RTIC.

RORRIS

Raw interrupt state of receive overrun interrupt:
The receive overrun interrupt is asserted when the FIFO is already
full and an additional data frame is received, causing an overrun of
the FIFO. Data is over-written in the
receive shift register, but not the FIFO so the FIFO contents stay
valid.
It can also be cleared by writing to ICR.RORIC.

31-4

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Synchronous Serial Interface (SSI)

1497

SSI Registers

www.ti.com

20.7.1.8 MIS Register (Offset = 1Ch) [reset = 0h]
MIS is shown in Figure 20-20 and described in Table 20-10.
Return to Summary Table.
Masked Interrupt Status
Figure 20-20. MIS Register
31

3
TXMIS
R-0h

2
RXMIS
R-0h

1
RTMIS
R-0h

0
RORMIS
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

RESERVED
R-0h

Table 20-10. MIS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TXMIS

Masked interrupt state of transmit FIFO interrupt:
This field returns the masked interrupt state of transmit FIFO
interrupt which is the AND product of raw interrupt state RIS.TXRIS
and the mask setting IMSC.TXIM.

RXMIS

Masked interrupt state of receive FIFO interrupt:
This field returns the masked interrupt state of receive FIFO interrupt
which is the AND product of raw interrupt state RIS.RXRIS and the
mask setting IMSC.RXIM.

RTMIS

Masked interrupt state of receive timeout interrupt:
This field returns the masked interrupt state of receive timeout
interrupt which is the AND product of raw interrupt state RIS.RTRIS
and the mask setting IMSC.RTIM.

RORMIS

Masked interrupt state of receive overrun interrupt:
This field returns the masked interrupt state of receive overrun
interrupt which is the AND product of raw interrupt state
RIS.RORRIS and the mask setting IMSC.RORIM.

31-4

1498

Synchronous Serial Interface (SSI)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

SSI Registers

www.ti.com

20.7.1.9 ICR Register (Offset = 20h) [reset = 0h]
ICR is shown in Figure 20-21 and described in Table 20-11.
Return to Summary Table.
Interrupt Clear
On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
Figure 20-21. ICR Register
31

1
RTIC
W-0h

0
RORIC
W-0h

RESERVED
W-0h
23

20
RESERVED
W-0h

12
RESERVED
W-0h

4
RESERVED
W-0h

Table 20-11. ICR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RTIC

Clear the receive timeout interrupt:
Writing 1 to this field clears the timeout interrupt (RIS.RTRIS).
Writing 0 has no effect.

RORIC

Clear the receive overrun interrupt:
Writing 1 to this field clears the overrun error interrupt
(RIS.RORRIS). Writing 0 has no effect.

31-2

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Synchronous Serial Interface (SSI)

1499

SSI Registers

www.ti.com

20.7.1.10 DMACR Register (Offset = 24h) [reset = 0h]
DMACR is shown in Figure 20-22 and described in Table 20-12.
Return to Summary Table.
DMA Control
Figure 20-22. DMACR Register
31

1
TXDMAE
R/W-0h

0
RXDMAE
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 20-12. DMACR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TXDMAE

R/W

Transmit DMA enable. If this bit is set to 1, DMA for the transmit
FIFO is enabled.

RXDMAE

R/W

Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO
is enabled.

31-2

1500

Synchronous Serial Interface (SSI)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Chapter 21
SWCU117G – February 2015 – Revised February 2017

Inter-Integrated Circuit (I2C) Interface
This chapter describes the inter-integrated circuit interface.
Topic

21.1
21.2
21.3
21.4
21.5

...........................................................................................................................
Inter-Integrated Circuit (I2C) Interface ................................................................
Block Diagram ................................................................................................
Functional Description ....................................................................................
Initialization and Configuration .........................................................................
I2C Interface Registers .....................................................................................

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Page

1502
1502
1503
1514
1515

Inter-Integrated Circuit (I2C) Interface

1501

Inter-Integrated Circuit (I2C) Interface

www.ti.com

21.1 Inter-Integrated Circuit (I2C) Interface
The I2C bus provides bidirectional data transfer through a 2-wire design, a serial data line (SDA) and a
serial clock line (SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs),
networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing
and diagnostic purposes in product development and manufacture. The CC26x0 and CC13x0 devices
include one I2C module, which provides the ability to interact (both transmit and receive) with other I2C
devices on the bus.
The CC26x0 and CC13x0 devices include one I2C module with the following features:
•

•

•
•

•

Devices on the I2C bus can be designated as either a master or a slave:
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
Four I2C modes:
– Master transmit
– Master receive
– Slave transmit
– Slave receive
Two transmission speeds: standard (100 Kbps) and fast (400 Kbps)
Master and slave interrupt generation:
– Master generates interrupts when a transmit or receive operation completes (or aborts due to an
error).
– Slave generates interrupts when data has been transferred or requested by a master or when a
Start or Stop condition is detected.
Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode

21.2 Block Diagram
Figure 21-1 shows the I2C block diagram.
Figure 21-1. I2C Block Diagram

I2C Control

I2CSCL

I2C_MSA

I2C_SOAR

I2C_MCTRL

I2C_SCTL

I2C_MDR

I2C_SDR

I2C_MTPR

I2C_SIMR

I2C_MIMR

I2C_SRIS

I2C_MRIS

I2C_SMIS

I2C_MMIS

I2C_SICR

I2C_MICR

I C Master Core

I2CSDA

I2CSCL
I2C I/O Select
I2CSDA
I2CSCL
2

I C Slave Core

I2CSDA

I2C_MCR

1502

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

21.3 Functional Description
The I2C module is comprised of both master and slave functions. For proper operation, the SDA pin must
be configured as an open-drain signal. Figure 21-2 shows a typical I2C bus configuration.
Figure 21-2. I2C Bus Configuration

RPUP

SCL
I2C Bus

SDA

I2CSCL

I2CSDA

CC26x0, CC13x0

SCL

SDA

Third-party device with I2C
interface

SCL

SDA

Third-party device with I2C
interface

21.3.1 I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on the CC26x0 and
CC13x0 controllers. SDA is the bidirectional serial data line and SCL line is the bidirectional serial clock
line. The bus is considered idle when both lines are high.
Every transaction on the I2C bus is 9-bits long, consisting of 8 data bits and 1 acknowledge bit. The
number of bytes per transfer (defined as the time between a valid Start and Stop condition, described in
Section 21.3.1.1) is unrestricted, an acknowledge bit must follow each byte, and data must be transferred
by the MSB first. When a receiver cannot receive another complete byte, the receiver can hold the clock
line SCL low and force the transmitter into a wait state. The data transfer continues when the receiver
releases the clock SCL.
21.3.1.1 Start and Stop Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: Start and Stop. A high-tolow transition on the SDA line while the SCL is high is defined as a Start condition, and a low-to-high
transition on the SDA line while the SCL line is high is defined as a Stop condition. The bus is considered
busy after a Start condition and free after a Stop condition (see Figure 21-3).
Figure 21-3. Start and Stop Conditions
SDA

SDA

SCL

SCL
Start
condition

Stop
condition

The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a Repeated
Start condition. To generate a single transmit cycle, the I2C Master Slave Address I2C:MSA register is
written with the desired address, the R/S bit is cleared, and the control register, I2C:MCTRL, is written with
ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the
operation is completed (or aborted due an error), the interrupt pin becomes active and the data is readable
from the I2C Master Data I2C:MDR register. When the I2C module operates in master receiver mode, the
ACK bit is normally set, causing the I2C bus controller to transmit an acknowledge automatically after each
byte. When the I2C bus controller requires no further data transmission from the slave transmitter, the ACK
bit must be cleared.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1503

Functional Description

www.ti.com

When operating in slave mode, 2 bits in the I2C Slave Raw Interrupt Status I2C:SRIS register indicate
detection of Start and Stop conditions on the bus, while 2 bits in the I2C Slave Masked Interrupt Status
I2C:SMIS register allow promotion of Start and Stop conditions to controller interrupts (when interrupts are
enabled).
21.3.1.2 Data Format With 7-bit Address
Data transfers follow the format shown in Figure 21-4. After the Start condition, a slave address is
transmitted. This address is 7 bits long followed by an eighth bit, which is a data direction bit (the R/S bit
in the I2C:MSA register). If the RS bit is clear, it indicates a transmit operation (send), and if it is set, it
indicates a request for data (receive). A data transfer is always terminated by a Stop condition generated
by the master; however, a master can initiate communications with another device on the bus, by
generating a Repeated Start condition and addressing another slave without first generating a Stop
condition. Various combinations of receive and transmit formats are then possible within a single transfer.
Figure 21-4. Complete Data Transfer With a 7-bit Address
SDA

MSB

SCL

1
Start

LSB

R/S

ACK

MSB

2
Slave Address

LSB

ACK

Data

Stop

The first 7 bits of the first byte comprise the slave address (see Figure 21-5). The eighth bit determines
the direction of the message. A 0 in the R/S position of the first byte means that the master transmits
(sends) data to the selected slave, and a 1 in this position means that the master receives data from the
slave.
Figure 21-5. R/S Bit in First Byte
MSB

LSB
R/S
Slave address

21.3.1.3 Data Validity
The SDA line must contain stable data during the high period of the clock, and the data line can change
only when SCL is low (see Figure 21-6).
Figure 21-6. Data Validity During Bit Transfer on the I2C Bus
SDA

SCL
Data line
stable

Change
of data
allow

21.3.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle generated by the master. During the
acknowledge cycle, the transmitter (master or slave) releases the SDA line. To acknowledge the
transaction, the receiver must pull down SDA during the acknowledge clock cycle. The data transmitted by
the receiver during the acknowledge cycle must comply with the data validity requirements described in
Section 21.3.1.3.

1504

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

When a slave receiver does not acknowledge the slave address, the slave must leave SDA high so that
the master can generate a Stop condition and abort the current transfer. If the master device is acting as a
receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. Because
the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter
by not generating an acknowledge on the last data byte. The slave transmitter must then release SDA to
let the master generate a Stop or a Repeated Start condition.
21.3.1.5 Arbitration
A master may start a transfer only if the bus is idle. Two or more masters can generate a Start condition
within minimum hold time of the Start condition. In these situations, an arbitration scheme occurs on the
SDA line, while SCL is high. During arbitration, the first of the competing master devices to place 1 (high)
on SDA while another master transmits 0 (low) switches off its data output stage, and retires until the bus
is idle again.
Arbitration can occur over several bits. The first stage of arbitration is a comparison of address bits; if both
masters are trying to address the same device, arbitration continues to the comparison of data bits.

21.3.2 Available Speed Modes
The I2C bus can run in either standard mode (100 kbps) or fast mode (400 kbps). The selected mode must
match the speed of the other I2C devices on the bus.
21.3.2.1 Standard and Fast Modes
Standard and fast modes are selected using a value in the I2C Master Timer Period I2C:MTPR register
that results in an SCL frequency of 100 kbps for standard mode, or 400 kbps for fast mode.
The I2C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP
where:
• CLK_PRD is the system clock period.
• TIMER_PRD is the programmed value in the I2C:MTPR register.
• SCL_LP is the low phase of SCL (fixed at 6).
• SCL_HP is the high phase of SCL (fixed at 4).
The I2C clock period is calculated as follows:
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD

(7)

For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP = 6
SCL_HP = 4
yields a SCL frequency of:
1/SCL_PERIOD = 333 kHz
Table 21-1 lists examples of the timer periods used to generate both standard and fast-mode SCL
frequencies, based on various system clock frequencies.
Table 21-1. Examples of I2C Master Timer Period versus Speed Mode
System Clock (MHz)

Timer Period

Standard Mode (kpbs)

Timer Period

Fast Mode (kbps)

0x01

100

–

0x03

100

0x01

–

0x07

100

0x01

400

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1505

Functional Description

www.ti.com

21.3.3 Interrupts
The I2C can generate interrupts when the following conditions are observed:
• Master transaction completed
• Master arbitration lost
• Master transaction error
• Master bus time-out
• Slave transaction received
• Slave transaction requested
• Stop condition on bus detected
• Start condition on bus detected
The I2C master and I2C slave modules have separate interrupt signals. While both modules can generate
interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller (INTC).
21.3.3.1 I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or receive),
when arbitration is lost, or when an error occurs during a transaction. To enable the I2C master interrupt,
software must set the IM bit in the I2C Master Interrupt Mask Register, I2C:MIMR. When an interrupt
condition is met, software must check the I2C Master Control and Status Register (I2C:MSTAT) ERR and
ARBLST bits to verify that an error did not occur during the last transaction, and to ensure that arbitration
has not been lost. An error condition is asserted if the last transaction was not acknowledged by the slave.
If an error is not detected and the master has not lost arbitration, the application can proceed with the
transfer. The interrupt is cleared by setting the IC bit in the I2C Master Interrupt Clear Register (I2C:MICR)
to 1.
If the application does not require the use of interrupts, the raw interrupt status is always visible through
the I2C Master Raw Interrupt Status Register (I2C:MRIS).
21.3.3.2 I2C Slave Interrupts
The slave module can generate an interrupt when data is received or requested. This interrupt is enabled
by setting the in the I2C Slave Interrupt Mask Register (I2C:SIMR). Software determines whether the
module must write (transmit) or read (receive) data from the I2C Slave Data Register (I2C:SDR) DATAIM
bit, by checking the RREQ and TREQ bits of the I2C Slave Control and Status Register (I2C:SSTAT). If
the slave module is in receive mode and the first byte of a transfer is received, the FBR and RREQ bits
are set. The interrupt is cleared by setting the I2C Slave Interrupt Clear Register (I2C:SICR) DATAIC bit.
In addition, the slave module generates an interrupt when a Start and a Stop condition is detected. These
interrupts are enabled by setting the I2C:SIMR register STARTIM and STOPIM bits; these interrupts are
cleared by setting the I2C:SICR register STOPIC and STARTIC bits to 1.
If the application does not require the use of interrupts, the raw interrupt status is always visible through
the I2C Slave Raw Interrupt Status Register (I2C:SRIS).

21.3.4 Loopback Operation
The I2C modules can be placed into an internal-loopback mode for diagnostic or debug work by setting
the I2C Master Configuration Register (I2C:MCR) LPBK bit. In loopback mode, the SDA and SCL signals
from the master and slave modules are tied together.

21.3.5 Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and slave
mode. To do this, the SDA and SCL signal configuration must be done in the IOC:IOCFG register.

1506

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

21.3.5.1 I2C Master Command Sequences
Figure 21-7, Figure 21-8, Figure 21-9, Figure 21-10, Figure 21-11, and Figure 21-12 show the command
sequences available for the I2C master.
Figure 21-7. Master Single TRANSMIT
Idle

Write slave address
to I2C_MSA

Sequence may be omitted in a
single master system.

Write data to
I2C_MDR

Read I2C_MSTAT

BUSY bit = 0?
No

Yes

Write 0 ± 111 to
I2C_MCTRL

Read I2C_MSTAT

Error service
No

BUSY bit = 0?
No

ERR bit = 0?
Yes

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Idle
Yes

Inter-Integrated Circuit (I2C) Interface

1507

Functional Description

www.ti.com

Figure 21-8. Master Single RECEIVE

Idle

Write slave address
to I2C_MSA
Sequence may be omitted in a
single master system.

Read I2C_MSTAT

BUSY bit = 0?
No

Yes

Write 0 ± 111 to
I2C_MCTRL

Error service

Read I2C_MSTAT

1508

BUSY bit = 0?

ERR bit = 0?
Yes

Inter-Integrated Circuit (I2C) Interface

Yes

Read data from
I2C_MDR

Idle

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

Figure 21-9. Master TRANSMIT With Repeated Start Condition

Idle
Read I2C_MSTAT
Write slave address
to I2C_MSA

Write data to
I2C_MDR

Sequence may be
omitted in a single
master system.

No
BUSY bit = 0?

Yes
Read I2C_MSTAT

ERR bit = 0?
No
BUSY bit = 0?

Yes

ARBLST bit = 1?
Yes

Write data to
I2C_MDR

Write 0 ± 011 to
I2C_MCTRL

Write 0 ± 100 to
I2C_MCTRL

Yes

Error serivce

Write 0 ± 001 to
I2C_MCTRL

Index = n?

Yes
Idle
Write 0 ± 101 to
I2C_MCTRL

Error service
Read I2C_MSTAT
No

Yes
Idle

ERR bit = 0?

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Yes

BUSY bit = 0?

Inter-Integrated Circuit (I2C) Interface

1509

Functional Description

www.ti.com

Figure 21-10. Master RECEIVE With Repeated Start Condition
Idle
Read I2C_MSTAT

Write slave address
to I2C_MSA

Sequence may be
omitted in a single
master system.

No
BUSY bit = 0?

Yes

Read I2C_MSTAT

ERR bit = 0?
No

No
BUSY bit = 0?
Yes
Yes

ARBLST bit = 1?
No

Read data from
I2C_MDR
Write 0 ±1011 to
I2C_MCTRL

Write 0 ± 100 to
I2C_MCTRL

Yes

Write 0 ± 1001 to
I2C_MCTRL

Error serivce

No
Index = m - 1?

Yes
Idle
Write 0 ± 101 to
I2C_MCTRL

Error service
Read I2C_MSTAT
No

Idle

1510

Read data from
I2C_MDR

Yes

Inter-Integrated Circuit (I2C) Interface

ERR bit = 0?

Yes

BUSY bit = 0?

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

Figure 21-11. Master RECEIVE With Repeated Start After TRANSMIT With Repeated Start Condition
Idle

Mater operates in master
transmit mode.

Stop condition is not
generated.

Write slave address
to I2C_MSA

Write 01011 to
I2C_MCTRL

Master operates in master
receive mode.

Repeated Start condition is
generated with changing data
direction.

Idle

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1511

Functional Description

www.ti.com

Figure 21-12. Master TRANSMIT With Repeated Start After RECEIVE With Repeated Start Condition
Idle

Mater operates in master
receive mode.

Stop condition is not
generated.

Write slave address
to I2C_MSA

Write 0-011 to
I2C_MCTRL

Master operates in master
transmit mode.

Repeated Start condition is
generated with changing data
direction.

Idle

1512

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Functional Description

www.ti.com

21.3.5.2 I2C Slave Command Sequences
Figure 21-13 shows the command sequence available for the I2C slave.
Figure 21-13. Slave Command Sequence
Idle

Write OWN slave
address to
I2C_SOAR

Write -----1 to
I2C_SCTL

Read
I2C_SSTAT

TREQ bit = 1?

Yes
Write data to
I2C_SDR

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

N
o

RREQ bit = 1?

FBR is
also
valid

Yes

Write data to
I2C_SDR

Inter-Integrated Circuit (I2C) Interface

1513

Initialization and Configuration

www.ti.com

21.4 Initialization and Configuration
The following example shows how to configure the I2C module to transmit a single byte as a master. This
assumes the system clock is 24 MHz.
1. Enable the serial power domain and enable the I2C module in PRCM by writing to the
PRCM:I2CCLKGR register, the PRCM:I2CCLKGS register, the PRCM:I2CCLKGDS register, or by
using the following driver library functions:
PRCMPeripheralRunEnabe(uint32_t)
PRCMPeripheralSleepEnable(uint32_t)
PRCMPeripheralDeepSLeepEnable(uint32_t)

and loading the setting to clock controller by writing to the PRCM:CLKLOADCTL register
or by using the driverlib function PRCMLoadSet().
2. Configure the IOC module to route the SDA and SCL signals from I/Os to the I2C module.
3. Initialize the I2C master by writing the I2C:MCR register with a value of 0x0000 0010.
4. Set the desired SCL clock speed of 100 kbps by writing the I2C:MTPR register with the correct value.
The value written to the I2C:MTPR register represents the number of system clock periods in one SCL
clock period. The TPR value is determined by Equation 8 through Equation 10.
TPR = {PERDMACLK / [2 × (SCL_LP + SCL_HP) × SCL_CLK]} – 1
TPR = {24 MHz / [2 × (6 + 4) × 100000]} – 1
TPR = 11

5.
6.
7.
8.
9.

1514

(8)
(9)
(10)

Write the I2C:MTPR register with the value of 0x0000 000B.
Specify the slave address of the master and that the next operation is a transmit by writing the
I2C:MSA register with a value of 0x0000 0076, which sets the slave address to 0x3B.
Place data (byte) to be transmitted in the data register by writing the I2C:MDR register with the desired
data.
Initiate a single-byte transmit of the data from master to slave by writing the I2C:MCTRL register with a
value of 0x0000 0007 (Stop, Start, Run).
Wait until the transmission completes by polling the I2C:MSTAT BUSBSY register bit until it is cleared.
Check the I2C:MSTAT ERR register bit to confirm the transmit was acknowledged.

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2C Interface Registers

www.ti.com

21.5 I2C Interface Registers
21.5.1 I2C Registers
Table 21-2 lists the memory-mapped registers for the I2C. All register offset addresses not listed in
Table 21-2 should be considered as reserved locations and the register contents should not be modified.
Table 21-2. I2C Registers
Offset

Acronym

Section

SOAR

Slave Own Address

Section 21.5.1.1

SSTAT

Slave Status

Section 21.5.1.2

SCTL

Slave Control

Section 21.5.1.3

SDR

Slave Data

Section 21.5.1.4

SIMR

Slave Interrupt Mask

Section 21.5.1.5

10h

SRIS

Slave Raw Interrupt Status

Section 21.5.1.6

14h

SMIS

Slave Masked Interrupt Status

Section 21.5.1.7
Section 21.5.1.8

18h

SICR

Slave Interrupt Clear

800h

MSA

Master Salve Address

Section 21.5.1.9

804h

MSTAT

Master Status

Section 21.5.1.10

804h

MCTRL

Master Control

Section 21.5.1.11

808h

MDR

Master Data

Section 21.5.1.12

80Ch

MTPR

I2C Master Timer Period

Section 21.5.1.13

810h

MIMR

Master Interrupt Mask

Section 21.5.1.14

814h

MRIS

Master Raw Interrupt Status

Section 21.5.1.15

818h

MMIS

Master Masked Interrupt Status

Section 21.5.1.16

81Ch

MICR

Master Interrupt Clear

Section 21.5.1.17

820h

MCR

Master Configuration

Section 21.5.1.18

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1515

I2C Interface Registers

www.ti.com

21.5.1.1 SOAR Register (Offset = 0h) [reset = 0h]
SOAR is shown in Figure 21-14 and described in Table 21-3.
Return to Summary Table.
Slave Own Address
This register consists of seven address bits that identify this I2C device on the I2C bus.
Figure 21-14. SOAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

3 2
OAR
R/W-0h

Table 21-3. SOAR Register Field Descriptions
Field

Type

Reset

Description

31-7

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

6-0

OAR

R/W

I2C slave own address
This field specifies bits a6 through a0 of the slave address.

1516

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2C Interface Registers

www.ti.com

21.5.1.2 SSTAT Register (Offset = 4h) [reset = 0h]
SSTAT is shown in Figure 21-15 and described in Table 21-4.
Return to Summary Table.
Slave Status
Note: This register shares address with SCTL, meaning that this register functions as a control register
when written, and a status register when read.
Figure 21-15. SSTAT Register
31

2
FBR
R-0h

1
TREQ
R-0h

0
RREQ
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

Table 21-4. SSTAT Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

FBR

First byte received
0: The first byte has not been received.
1: The first byte following the slave's own address has been
received.
This bit is only valid when the RREQ bit is set and is automatically
cleared when data has been read from the SDR register.
Note: This bit is not used for slave transmit operations.

TREQ

Transmit request
0: No outstanding transmit request.
1: The I2C controller has been addressed as a slave transmitter and
is using clock stretching to delay the master until data has been
written to the SDR register.

RREQ

Receive request
0: No outstanding receive data
1: The I2C controller has outstanding receive data from the I2C
master and is using clock stretching to delay the master until data
has been read from the SDR register.

31-3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1517

I2C Interface Registers

www.ti.com

21.5.1.3 SCTL Register (Offset = 4h) [reset = 0h]
SCTL is shown in Figure 21-16 and described in Table 21-5.
Return to Summary Table.
Slave Control
Note: This register shares address with SSTAT, meaning that this register functions as a control register
when written, and a status register when read.
Figure 21-16. SCTL Register
31

24
23
RESERVED
W-0h
8
7
RESERVED
W-0h

0
DA
W-0h

Table 21-5. SCTL Register Field Descriptions
Bit
31-1
0

1518

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved field. Writing any
other value may result in undefined behavior.

Device active
0: Disables the I2C slave operation
1: Enables the I2C slave operation

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2C Interface Registers

www.ti.com

21.5.1.4 SDR Register (Offset = 8h) [reset = 0h]
SDR is shown in Figure 21-17 and described in Table 21-6.
Return to Summary Table.
Slave Data
This register contains the data to be transmitted when in the Slave Transmit state, and the data received
when in the Slave Receive state.
Figure 21-17. SDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
DATA
R/W-0h

Table 21-6. SDR Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

DATA

R/W

Data for transfer
This field contains the data for transfer during a slave receive or
transmit operation. When written the register data is used as transmit
data. When read, this register returns the last data received.
Data is stored until next update, either by a system write for transmit
or by an external master for receive.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1519

I2C Interface Registers

www.ti.com

21.5.1.5 SIMR Register (Offset = Ch) [reset = 0h]
SIMR is shown in Figure 21-18 and described in Table 21-7.
Return to Summary Table.
Slave Interrupt Mask
This register controls whether a raw interrupt is promoted to a controller interrupt.
Figure 21-18. SIMR Register
31

2
STOPIM
R/W-0h

1
STARTIM
R/W-0h

0
DATAIM
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

Table 21-7. SIMR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STOPIM

R/W

Stop condition interrupt mask
0: The SRIS.STOPRIS interrupt is suppressed and not sent to the
interrupt controller.
1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt
controller.
0h = Disable Interrupt
1h = Enable Interrupt

STARTIM

R/W

Start condition interrupt mask
0: The SRIS.STARTRIS interrupt is suppressed and not sent to the
interrupt controller.
1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt
controller.
0h = Disable Interrupt
1h = Enable Interrupt

DATAIM

R/W

Data interrupt mask
0: The SRIS.DATARIS interrupt is suppressed and not sent to the
interrupt controller.
1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt
controller.

31-3

1520

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2C Interface Registers

www.ti.com

21.5.1.6 SRIS Register (Offset = 10h) [reset = 0h]
SRIS is shown in Figure 21-19 and described in Table 21-8.
Return to Summary Table.
Slave Raw Interrupt Status
This register shows the unmasked interrupt status.
Figure 21-19. SRIS Register
31

2
STOPRIS
R-0h

1
STARTRIS
R-0h

0
DATARIS
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

Table 21-8. SRIS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STOPRIS

Stop condition raw interrupt status
0: No interrupt
1: A Stop condition interrupt is pending.
This bit is cleared by writing a 1 to SICR.STOPIC.

STARTRIS

Start condition raw interrupt status
0: No interrupt
1: A Start condition interrupt is pending.
This bit is cleared by writing a 1 to SICR.STARTIC.

DATARIS

Data raw interrupt status
0: No interrupt
1: A data received or data requested interrupt is pending.
This bit is cleared by writing a 1 to the SICR.DATAIC.

31-3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1521

I2C Interface Registers

www.ti.com

21.5.1.7 SMIS Register (Offset = 14h) [reset = 0h]
SMIS is shown in Figure 21-20 and described in Table 21-9.
Return to Summary Table.
Slave Masked Interrupt Status
This register show which interrupt is active (based on result from SRIS and SIMR).
Figure 21-20. SMIS Register
31

2
STOPMIS
R-0h

1
STARTMIS
R-0h

0
DATAMIS
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

Table 21-9. SMIS Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STOPMIS

Stop condition masked interrupt status
0: An interrupt has not occurred or is masked/disabled.
1: An unmasked Stop condition interrupt is pending.
This bit is cleared by writing a 1 to the SICR.STOPIC.

STARTMIS

Start condition masked interrupt status
0: An interrupt has not occurred or is masked/disabled.
1: An unmasked Start condition interrupt is pending.
This bit is cleared by writing a 1 to the SICR.STARTIC.

DATAMIS

Data masked interrupt status
0: An interrupt has not occurred or is masked/disabled.
1: An unmasked data received or data requested interrupt is
pending.
This bit is cleared by writing a 1 to the SICR.DATAIC.

31-3

1522

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2C Interface Registers

www.ti.com

21.5.1.8 SICR Register (Offset = 18h) [reset = 0h]
SICR is shown in Figure 21-21 and described in Table 21-10.
Return to Summary Table.
Slave Interrupt Clear
This register clears the raw interrupt SRIS.
Figure 21-21. SICR Register
31

2
STOPIC
W-0h

1
STARTIC
W-0h

0
DATAIC
W-0h

RESERVED
W-0h
23

20
RESERVED
W-0h

12
RESERVED
W-0h

5
RESERVED
W-0h

Table 21-10. SICR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

STOPIC

Stop condition interrupt clear
Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS.

STARTIC

Start condition interrupt clear
Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS.

DATAIC

Data interrupt clear
Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS.

31-3

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1523

I2C Interface Registers

www.ti.com

21.5.1.9 MSA Register (Offset = 800h) [reset = 0h]
MSA is shown in Figure 21-22 and described in Table 21-11.
Return to Summary Table.
Master Salve Address
This register contains seven address bits of the slave to be accessed by the master (a6-a0), and an RS bit
determining if the next operation is a receive or transmit.
Figure 21-22. MSA Register
31

12
11
RESERVED
R-0h

24
23
RESERVED
R-0h
8

4
SA
R/W-0h

0
RS
R/W0h

Table 21-11. MSA Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-1

R/W

I2C master slave address
Defines which slave is addressed for the transaction in master mode

R/W

Receive or Send
This bit-field specifies if the next operation is a receive (high) or a
transmit/send (low) from the addressed slave SA.
0h = Transmit/send data to slave
1h = Receive data from slave

1524

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2C Interface Registers

www.ti.com

21.5.1.10 MSTAT Register (Offset = 804h) [reset = 20h]
MSTAT is shown in Figure 21-23 and described in Table 21-12.
Return to Summary Table.
Master Status
Figure 21-23. MSTAT Register
31

3
DATACK_N
R-0h

2
ADRACK_N
R-0h

1
ERR
R-0h

0
BUSY
R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

7
RESERVED
R-0h

6
BUSBSY
R-0h

5
IDLE
R-1h

4
ARBLST
R-0h

Table 21-12. MSTAT Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

BUSBSY

Bus busy
0: The I2C bus is idle.
1: The I2C bus is busy.
The bit changes based on the MCTRL.START and MCTRL.STOP
conditions.

IDLE

I2C idle
0: The I2C controller is not idle.
1: The I2C controller is idle.

ARBLST

Arbitration lost
0: The I2C controller won arbitration.
1: The I2C controller lost arbitration.

DATACK_N

Data Was Not Acknowledge
0: The transmitted data was acknowledged.
1: The transmitted data was not acknowledged.

ADRACK_N

Address Was Not Acknowledge
0: The transmitted address was acknowledged.
1: The transmitted address was not acknowledged.

ERR

Error
0: No error was detected on the last operation.
1: An error occurred on the last operation.

BUSY

I2C busy
0: The controller is idle.
1: The controller is busy.
When this bit-field is set, the other status bits are not valid.
Note: The I2C controller requires four SYSBUS clock cycles to
assert the BUSY status after I2C master operation has been initiated
through MCTRL register.
Hence after programming MCTRL register, application is requested
to wait for four SYSBUS clock cycles before issuing a controller
status inquiry through MSTAT register.
Any prior inquiry would result in wrong status being reported.

31-7

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1525

I2C Interface Registers

www.ti.com

21.5.1.11 MCTRL Register (Offset = 804h) [reset = 0h]
MCTRL is shown in Figure 21-24 and described in Table 21-13.
Return to Summary Table.
Master Control
This register accesses status bits when read and control bits when written. When read, the status register
indicates the state of the I2C bus controller as stated in MSTAT. When written, the control register
configures the I2C controller operation.
To generate a single transmit cycle, the I2C Master Slave Address (MSA) register is written with the
desired address, the MSA.RS bit is cleared, and this register is written with
* ACK=X (0 or 1),
* STOP=1,
* START=1,
* RUN=1
to perform the operation and stop.
When the operation is completed (or aborted due an error), an interrupt becomes active and the data may
be read from the MDR register.
Figure 21-24. MCTRL Register
31

3
ACK
W-0h

2
STOP
W-0h

1
START
W-0h

0
RUN
W-0h

RESERVED
W-0h
23

20
RESERVED
W-0h

12
RESERVED
W-0h

RESERVED
W-0h

Table 21-13. MCTRL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ACK

Data acknowledge enable
0: The received data byte is not acknowledged automatically by the
master.
1: The received data byte is acknowledged automatically by the
master.
This bit-field must be cleared when the I2C bus controller requires
no further data to be transmitted from the slave transmitter.
0h = Disable acknowledge
1h = Enable acknowledge

STOP

This bit-field determines if the cycle stops at the end of the data
cycle or continues on to a repeated START condition.
0: The controller does not generate the Stop condition.
1: The controller generates the Stop condition.
0h = Disable STOP
1h = Enable STOP

START

This bit-field generates the Start or Repeated Start condition.
0: The controller does not generate the Start condition.
1: The controller generates the Start condition.
0h = Disable START
1h = Enable START

31-4

1526

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2C Interface Registers

www.ti.com

Table 21-13. MCTRL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

RUN

I2C master enable
0: The master is disabled.
1: The master is enabled to transmit or receive data.
0h = Disable Master
1h = Enable Master

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1527

I2C Interface Registers

www.ti.com

21.5.1.12 MDR Register (Offset = 808h) [reset = 0h]
MDR is shown in Figure 21-25 and described in Table 21-14.
Return to Summary Table.
Master Data
This register contains the data to be transmitted when in the Master Transmit state and the data received
when in the Master Receive state.
Figure 21-25. MDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
DATA
R/W-0h

Table 21-14. MDR Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

DATA

R/W

When Read: Last RX Data is returned
When Written: Data is transferred during TX transaction

1528

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2C Interface Registers

www.ti.com

21.5.1.13 MTPR Register (Offset = 80Ch) [reset = 1h]
MTPR is shown in Figure 21-26 and described in Table 21-15.
Return to Summary Table.
I2C Master Timer Period
This register specifies the period of the SCL clock.
Figure 21-26. MTPR Register
31

3
TPR
R/W-1h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

7
TPR_7
R/W-0h

Table 21-15. MTPR Register Field Descriptions
Bit
31-8
7
6-0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TPR_7

R/W

Must be set to 0 to set TPR. If set to 1, a write to TPR will be
ignored.

TPR

R/W

SCL clock period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the timer period register value (range of 1 to 127)
SCL_LP is the SCL low period (fixed at 6).
SCL_HP is the SCL high period (fixed at 4).
CLK_PRD is the system clock period in ns.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1529

I2C Interface Registers

www.ti.com

21.5.1.14 MIMR Register (Offset = 810h) [reset = 0h]
MIMR is shown in Figure 21-27 and described in Table 21-16.
Return to Summary Table.
Master Interrupt Mask
This register controls whether a raw interrupt is promoted to a controller interrupt.
Figure 21-27. MIMR Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
IM
R/W0h

Table 21-16. MIMR Register Field Descriptions
Bit
31-1
0

1530

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

R/W

Interrupt mask
0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt
controller.
1: The master interrupt is sent to the interrupt controller when the
MRIS.RIS is set.
0h = Disable Interrupt
1h = Enable Interrupt

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2C Interface Registers

www.ti.com

21.5.1.15 MRIS Register (Offset = 814h) [reset = 0h]
MRIS is shown in Figure 21-28 and described in Table 21-17.
Return to Summary Table.
Master Raw Interrupt Status
This register show the unmasked interrupt status.
Figure 21-28. MRIS Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
RIS
R-0h

Table 21-17. MRIS Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RIS

Raw interrupt status
0: No interrupt
1: A master interrupt is pending.
This bit is cleared by writing 1 to the MICR.IC bit .

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1531

I2C Interface Registers

www.ti.com

21.5.1.16 MMIS Register (Offset = 818h) [reset = 0h]
MMIS is shown in Figure 21-29 and described in Table 21-18.
Return to Summary Table.
Master Masked Interrupt Status
This register show which interrupt is active (based on result from MRIS and MIMR).
Figure 21-29. MMIS Register
31

24
23
RESERVED
R-0h
8
7
RESERVED
R-0h

0
MIS
R-0h

Table 21-18. MMIS Register Field Descriptions
Bit
31-1
0

1532

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

MIS

Masked interrupt status
0: An interrupt has not occurred or is masked.
1: A master interrupt is pending.
This bit is cleared by writing 1 to the MICR.IC bit .

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2C Interface Registers

www.ti.com

21.5.1.17 MICR Register (Offset = 81Ch) [reset = 0h]
MICR is shown in Figure 21-30 and described in Table 21-19.
Return to Summary Table.
Master Interrupt Clear
This register clears the raw and masked interrupt.
Figure 21-30. MICR Register
31

24
23
RESERVED
W-0h
8
7
RESERVED
W-0h

0
IC
W-0h

Table 21-19. MICR Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Interrupt clear
Writing 1 to this bit clears MRIS.RIS and MMIS.MIS .
Reading this register returns no meaningful data.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-Integrated Circuit (I2C) Interface

1533

I2C Interface Registers

www.ti.com

21.5.1.18 MCR Register (Offset = 820h) [reset = 0h]
MCR is shown in Figure 21-31 and described in Table 21-20.
Return to Summary Table.
Master Configuration
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
Figure 21-31. MCR Register
31

2
RESERVED
R-0h

0
LPBK
R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

6
RESERVED
R/W-0h

5
SFE
R/W-0h

4
MFE
R/W-0h

Table 21-20. MCR Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

SFE

R/W

I2C slave function enable
0h = Slave mode is disabled.
1h = Slave mode is enabled.

MFE

R/W

I2C master function enable
0h = Master mode is disabled.
1h = Master mode is enabled.

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

LPBK

R/W

I2C loopback
0: Normal operation
1: Loopback operation (test mode)
0h = Disable Test Mode
1h = Enable Test Mode

31-6

3-1
0

1534

Inter-Integrated Circuit (I2C) Interface

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Chapter 22
SWCU117G – February 2015 – Revised February 2017

Inter-IC Sound (I2S) Module
This chapter describes the Inter-IC Sound (I2S) Module.
Topic

...........................................................................................................................

22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
22.9
22.10

Introduction ...................................................................................................
Digital Audio Interface .....................................................................................
Frame Configuration .......................................................................................
Pin Configuration ............................................................................................
Clock Configuration ........................................................................................
Serial Interface Formats ...................................................................................
Memory Interface ............................................................................................
Samplestamp Generator ..................................................................................
Usage ............................................................................................................
I2S Registers.................................................................................................

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Page

1536
1536
1537
1537
1537
1538
1541
1543
1545
1547

Inter-IC Sound (I2S) Module

1535

Introduction

www.ti.com

22.1 Introduction
The CC26x0 and CC13x0 devices feature an I2S module that supports the I2S, LJF, RJF, and DSP
interface formats. This interface can be used to transfer audio sample streams between CC26x0 or
CC13x0 and external audio devices, such as codecs, DACs, and ADCs. The CC26x0 and CC13x0
devices can act as either I2S master or I2S slave.

22.2 Digital Audio Interface
Figure 22-1 shows the signals in the I2S interface. The master provides the clock signals, Word Clock
(WCLK) and Bit Clock (BCLK), used for interface to the slave. Audio data is transferred serially on the two
data lines, AD0 and AD1. The direction for each ADx pin may be from master to slave or from slave to
master, and is fixed during active operation. An optional master clock (MCLK) signal can be provided from
the master. The MCLK signal can be used as the master clock for external audio codecs and so on.
Figure 22-1. Audio Interface Signals
BCLK
WCLK
Master

Slave
ADx
ADx

The supported interface formats are synchronous to the BCLK, and the words (samples) are aligned
according to the WCLK signal. WCLK is synchronous to BCLK signal, and for all supported interface
formats, the frequency of WCLK is the same as the sample frequency. The period from one positive
WCLK edge to the next positive WCLK edge is called a frame. Depending on the interface format, a frame
may consist of one or two phases.
Data is sampled on one edge of BCLK and updated on the opposite edge. The frequency of BCLK may be
any multiple of the frequency of WCLK, but the number of BCLK periods within a frame must at least be
equal to the number of bits produced or consumed within a sample period.
If a format has two phases per frame (as in I2S, RJF, and LJF), the format is said to be dual phased.
Figure 22-2 shows an example of the signals used for the I2S interface format. In this case, WCLK is low
during the first phase and high during the second phase; hence, both edges are relevant for phase timing.
NOTE: For the I2S interface format, the polarity of WCLK is inverted compared to RJF and LJF.

Figure 22-2. I2S Interface Format Example
WCLK and ADx are clocked out at this edge

BCLK

WCLK and ADx are sampled at this edge

WCLK

ADx (I2S)

MSB

LSB

MSB

Phase

The DSP interface format is a single-phased format. A single-phase format has one phase per frame, but
unlike the dual-phased formats, each frame can contain multiple data channels. Figure 22-3 presents an
example of the DSP interface format. WCLK goes high for one BCLK period at the start of the phase;
therefore only the positive edge is relevant for phase timing. The WCLK cycle is followed by all the data
channels back-to-back. The data is updated on the positive edge of BCLK and sampled on the negative
edge.

1536

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Frame Configuration

www.ti.com

Figure 22-3. DSP Interface Format Example
BCLK

WCLK

ADx (DSP)

LSB MSB

MSB
Channel 0

Channel 1

LSB
Channel 2

All samples produced or to be consumed in a sample period must be transferred within a frame, using one
or more data lines. Hence, samples transferred within a frame belong to different audio channels. The
different audio interface formats support a different number of channels per frame; I2S, RJF, and LJF
support one or two channels per frame (one per phase), while DSP supports one to eight channels per
frame. Section 22.6 presents a more detailed description of each supported interface format.

22.3 Frame Configuration
The I2S:AIFFMTCFG.DUAL_PHASE register determines the number of phases per frame (one or two). In
the following text, a WCLK edge includes only the positive edge for single-phased formats and both edges
for dual-phased formats. A phase is divided into three intervals:
1. DATA DELAY is the inactive period between the WCLK edge and the data period. The duration of this
interval is determined by the I2S:AIFFMTCFG.DATA_DELAY register (zero to 255 BCLK cycles). If a
new WCLK edge occurs before the DATA DELAY interval expires, the I2S:IRQFLAGS.WCLK_ERR
register is asserted.
2. WORD is the active period in which a sample word is clocked out or sampled on all ADx pins. The
duration of this interval is determined by the I2S:AIFFMTCFG.WORD_LEN register (8 to 24 BCLK
cycles). In dual-phase mode, the I2S:IRQFLAGS.WCLK_ERR register is asserted if two WCLK edges
are less than four BCLK cycles apart. Similarly in the single-phase mode, the
I2S:IRQFLAGS.WCLK_ERR register is asserted if a new WCLK edge occurs before the last channel is
started.
3. IDLE is the inactive period between the last word interval and the next WCLK edge.

22.4 Pin Configuration
The ADx pins can be individually configured to be input, output, or not in use by setting the
I2S:AIFDIRCFG:AD0, the I2S:AIFDIRCFG:AD1, and the I2S:AIFDIRCFG:AD2 registers with the following:
• 0x0: Not in use
• 0x1: Input
• 0x2: Output
When a direction is completely unused, there is no need to configure the corresponding memory access
and sample stamp registers. The ADx and the clock pins are configured in the I/O controller.

22.5 Clock Configuration
The I2S module includes one clock control register (I2S:AIFWCLKSRC); all other I2S clock configurations
are done in the PRCM module.
The I2S:AIFWCLKSRC.WCLK_SRC register selects an internal or external WCLK source for the I2S
module. The selected source must be the same as the BCLK source selected in the
PRCM:I2SBCLKSEL.SRC register. The WCLK source (internal or external) can be inverted using the
I2S:AIFWCLKSRC.WCLK_INV register. For example, the inverted WCLK source is used for the I2S serial
interface format.
On the I2S serial interface, data and WCLK are sampled and clocked out on opposite edges of BCLK. The
PRCM:I2SCLKCTL.SMPL_ON_POSEDGE register sets if the sampling or the clocking of WCLK and data
must be done on the positive or negative edge of BCLK. Sample edge and phase mode used by the I2S
module is set using the I2S:AIFFMTCFG register.
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1537

Clock Configuration

www.ti.com

The clock signals MCLK, BCLK, and WCLK must be enabled using the PRCM:I2SCLKCTL.EN register. If
these signals are not enabled, the output is static low.

22.5.1 WCLK, BCLK, and MCLK Division Ratio
The frequency of the three clock signals in the I2S module can be set individually to a ratio of the
MCUCLK by using the clock division registers PRCM:I2SMCLKDIV.MDIV, PRCM:I2SBCLKDIV.BDIV, and
PRCM:I2SWCLKDIV.WDIV.
To obtain the clock frequency for MCLK and BCLK, the PRCM:I2SBCLKDIV.BDIV and
PRCM:I2SWCLKDIV.WDIV bit fields are used directly as the denominators to divide the MCUCLK as in
the following:
• MCLK = MCUCLK / MDIV [Hz]
• BCLK = MCUCLK / BDIV [Hz]
The division ratio for WCLK is calculated differently depending on the PRCM:I2SWCLKDIV.WDIV register
and the phase mode selected in the PRCM:I2SCLKCTL.WCLK_PHASE register as in the following:
• Single phase: PRCM:I2SCLKCTL.WCLK_PHASE = 0 WCLK is high one BCLK period and low
WDIV[9:0] (unsigned, [1 to 1023]) BCLK periods.
WCLK = MCUCLK / {BDIV × (WDIV[9:0] + 1)} [Hz]

(11)

•

Dual phase: PRCM:I2SCLKCTL.WCLK_PHASE = 1. Each phase on WCLK (50% duty cycle) is
WDIV[9:0] (unsigned, [1 to 1023]) BCLK periods.

•

User defined: PRCM:I2SCLKCTL.WCLK_PHASE = 2. WCLK is high WDIV[7:0] (unsigned, [1 to 255])
BCLK periods and low WDIV[15:8] (unsigned, [1 to 255]) BCLK periods.

WCLK = MCUCLK / {BDIV × (2 × WDIV[9:0])}

(12)

WCLK = MCUCLK / {BDIV × (WDIV[7:0] + WDIV[15:8])}

(13)

22.6 Serial Interface Formats
The interface supports the dual-phase formats I2S, LJF, and RJF, which support one or two audio
channels per ADx pin. The I2S module also supports the single-phase format, DSP, which supports up to
eight audio channels per ADx pin.

22.6.1 I2S
Figure 22-4 shows the I2S interface format. I2S is a dual-phase format with a 50% WCLK duty cycle and
MSB of each sample word aligned with the edge of WCLK plus one BCLK period. This is configured by
setting I2S:AIFFMTCFG.DUAL_PHASE = 1 and I2S:AIFFMTCFG.DATA_DELAY = 1. For any given
sample, the LEFT channel is transferred first when WCLK is low, and the RIGHT channel is transferred
second when WCLK is high. Because the polarity of WCLK is reversed for the I2S format,
I2S:AIFWCLKSRC.WCLK_INV = 1.
Data is sampled on the rising edge of BCLK and updated on the falling edge of BCLK; hence,
I2S:AIFFMTCFG.SMPL_EDGE = 1. The I2S format is unique in the sense that the CC26x0 and CC13x0
devices are able to automatically detect the number of BCLK periods per WCLK period, and therefore
supports any BCLK rate after configuration along with variable sample resolutions as in the following:
• If the sample resolution is higher than the number of bits per WCLK period, the samples are truncated.
• If the sample resolution is lower than the number of bits per WCLK period, the samples are zeropadded.
When sample words are back-to-back, LSB of the previous sample is output in the DATA DELAY cycle.

1538

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Serial Interface Formats

www.ti.com

Figure 22-4. I2S Interface Format
WCLK

BCLK

ADx

n-1

n-2

n-3

MSB

n-1

n-2

n-3

LSB MSB

0
LSB

Right channel

Left channel
WCLK period = 1/Fs

22.6.2 Left Justified (LJF)
Figure 22-5 shows the LJF interface format. LJF is a dual-phase format, I2S:AIFFMTCFG.DUAL_PHASE
= 1, with a 50% WCLK duty cycle and MSB of each sample word aligned with the edge of WCLK; that is,
I2S:AIFFMTCFG.DATA_DELAY = 0. For any given sample, the left channel is transferred first when
WCLK is high, and the right channel is transferred second when WCLK is low. Data is sampled on the
rising edge of BCLK and updated on the falling edge of BCLK, I2S:AIFFMTCFG.SMPL_EDGE = 1.
The maximum number of bits per word is specified using the I2S:AIFFMTCFG.WORD_LEN register. The
number of BCLK cycles in a phase must be equal to or higher than this number. When there is an IDLE
period at the end of the clock phase, MSB of the next sample is output during this interval.
Figure 22-5. LJF Interface Format
WCLK
BCLK
ADx

n-1

n-2

n-3

n-1

LSB

MSB

n-2

n-3

n-1

LSB
Right channel

Left channel
WCLK period = 1/FS

22.6.3 Right Justified (RJF)
Figure 22-6 shows the RJF interface format. RJF is a dual-phase format, I2S:AIFFMTCFG.DUAL_PHASE
= 1, with a 50% WCLK duty cycle and LSB of each sample word aligned with the edge of WCLK. For any
given sample, the left channel is transferred first when WCLK is high, and the right channel is transferred
second when WCLK is low. Data is sampled on the rising edge of BCLK and updated on the falling edge
of BCLK,
I2S: AIFFMTCFG.SMPL_EDGE = 1.
There is an optional IDLE period at the start of the clock phase that is specified by the
I2S:AIFFMTCFG.DATA_DELAY register; logical 0 is output during this DATA DELAY interval.
The maximum number of bits per word is specified using the I2S:AIFFMTCFG.WORD_LEN register. The
number of BCLK cycles in each phase must be equal to I2S:AIFFMTCFG.WORD_LEN +
I2S:AIFFMTCFG.DATA_DELAY.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1539

Serial Interface Formats

www.ti.com

Figure 22-6. RJF Interface Format
WCLK

BCLK

ADx

n-1

n-2

n-3

MSB

n-1

n-3

n-2

MSB

LSB

1
LSB

Right channel

Left channel
WCLK period = 1/FS

22.6.4 DSP
Figure 22-7 shows the DSP interface format. DSP is a single-phase format,
I2S:AIFFMTCFG.DUAL_PHASE = 0, where WCLK is high for one BCLK period, followed by each audio
channel back-to-back. Data is sampled on the falling edge of BCLK and updated on the rising edge of
BCLK; this is configured by setting I2S:AIFFMTCFG.SMPL_EDGE = 0.
There is an optional IDLE period at the end of the clock phase between the last data channel and the next
WCLK period; logical 0 is output during this period. The number of BCLK cycles in the phase must be
equal to or higher than the word length, as specified in the I2S:AIFFMTCFG.WORD_LEN register, times
the number of specified channels (determined by the most significant 1 in all the I2S:AIFWMASKn
registers combined).
When sample words are back-to-back, LSB of the previous sample are output in the DATA DELAY cycle.
Figure 22-7. DSP Interface Format (Showing First Two of Eight Possible Channels)
WCLK

BCLK

ADx

n-1

n-2

n-3

MSB
Channel 0 (left)

n-1

LSB

MSB

n-2

n-3

n-1

LSB
Channel 1 (right)

WCLK period = 1/FS

1540

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Memory Interface

www.ti.com

22.7 Memory Interface
This section describes the register settings that affect the automated memory interface.
The following are the relevant registers:
• I2S:AIFDIRCFG
• I2S:AIFDMACFG
• I2S:AIFFMTCFG
• I2S:AIFWMASKn
• I2S:AIFINPTRNEXT
• I2S:AIFOUTPTRNEXT
The two observation registers are the following:
• I2S:AIFINPTR
• I2S:AIFOUTPTR
NOTE:

When using I2S (with DMA) and the CPU is in deepsleep mode, the system bus is turned
off; therefore, the I2S DMA has no access to flash or RAM.
Current behavior is to turn off the system bus when the following conditions are true:
•
PRCM.PDCTL1.CPU_ON = 0
•
PRCM.PDCTL1.VIMS_MODE = 0
•
PRCM.SECDMACLKGDS.DMA_CLK_EN = 0
•

– This setting must be loaded with CLKLOADCTL.LOAD.
PRCM.SECDMACLKGDS.CRYPTO_CLK_EN = 0

•
•

– This setting must be loaded with CLKLOADCTL.LOAD.
RFC does not request access to BUS.
System CPU is in deepsleep mode.

22.7.1 Word Lengths
The word length on the serial interface and the word length in memory are configured independently.
• The I2S:AIFFMTCFG.WORD_LEN register specifies the maximum number of bits (8 to 24) to transfer
on the serial interface. In single-phase format, this is the exact number of bits per word, while in dualphase format this is the maximum number of bits per word.
• The I2S:AIFFMTCFG.MEM_LEN_24 register determines whether words in memory are 16 or 24 bits.
Data written to memory is always aligned to 16 or 24 bits. The I2S:AIFFMTCFG.MEM_LEN_24 register
configuration determines the behavior of the memory interface as the following:
• I2S:AIFFMTCFG.MEM_LEN_24 = 0: A word is transferred in a single 16-bit transfer. The addresses
written to the I2S:AIFINPTRNEXT and the I2S:AIFOUTPTRNEXT registers must be word-aligned (that
is, even the addresses).
• I2S:AIFFMTCFG.MEM_LEN_24 = 1: A word is transferred in a double-locked transfer consisting of one
8-bit word and one 16-bit word in the appropriate order. The addresses written to the
I2S:AIFINPTRNEXT and the I2S:AIFOUTPTRNEXT registers do not have to be word aligned.
Samples on the serial interface and in memory are always aligned by MSB. If the source is longer than the
destination, the words are truncated. If the source is shorter than the destination, the words are zeropadded.

22.7.2 Audio Channels
The audio channel configuration is determined by the I2S:AIFDIRCFG and the I2S:AIFWMASKn registers.
For each ADx pin, the I2S:AIFWMASKn register determines whether the channels in a frame are present
in memory or not.
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1541

Memory Interface

•

www.ti.com

For each frame when I2S:AIFFMTCFG.DUAL_PHASE = 0:
– Input: the I2S:AIFWMASKn.MASK register determines whether or not channels are stored in
memory.
– Output: the I2S:AIFWMASKn.MASK register determines whether or not channels are fetched from
memory. Logical 0 is output on ADx when not fetched from memory.
For each frame when I2S:AIFFMTCFG.DUAL_PHASE = 1:
– Mono: I2S:AIFWMASKn.MASK = 0x01
• Input: channel 0 is stored to memory.
• Output: channel 0 is fetched from memory and repeated for channel 1.
– Stereo: I2S:AIFWMASKn.MASK = 0x03
• Input: both channels are stored to memory.
• Output: both channels are fetched from memory.

22.7.3 Memory Buffers and Pointers
The memory access functionality operates on blocks of frames. There are separate blocks for input
samples and output samples. The number of frames per block is configured in the
I2S:AIFDMACFG.END_FRAME_IDX register. This is the index of the last frame in the block (that is, the
block size minus 1).
Writing a nonzero value to the I2S:AIFDMACFG.END_FRAME_IDX register enables and initializes the
interface.
NOTE: Before writing a nonzero value to the I2S:AIFDMACFG.END_FRAME_IDX register, all other
configurations must be done, and the I2S:AIFINPTR register and/or the I2S:AIFOUTPTR
register must be loaded.

The block locations in memory are determined by the I2S:AIFINPTR and the I2S:AIFOUTPTR registers. A
double-buffering scheme is used to give software time to update the pointers.
• The input memory interface uses the I2S:AIFINPTR register, while output memory interface uses the
I2S:AIFOUTPTR register.
• Software must write the next block addresses to the I2S:AIFINPTRNEXT and the
I2S:AIFOUTPTRNEXT registers.
• When loading and storing samples, the I2S:AIFINPTR and the I2S:AIFOUTPTR registers increase for
each memory access.
• When a block is finished, the following occurs:
– Input memory interface block:
• I2S:AIFINPTR = I2S:AIFINPTRNEXT
• I2S:AIFINPTRNEXT = NULL
• I2S:IRQFLAGS.AIF_DMA_IN is set
– Output memory interface block:
• I2S:AIFOUTPTR = I2S:AIFOUTPTRNEXT
• I2S:AIFOUTPTRNEXT = NULL
• I2S:IRQFLAGS.AIF_DMA_OUT is set
The interrupt, or alternatively the I2S:AIFINPTRNEXT and the I2S:AIFOUTPTRNEXT registers returning to
NULL, signals software to write the next pointers. Failing to write the next pointers to the
I2S:AIFINPTRNEXT and (or) the I2S:AIFOUTPTRNEXT registers before the running block finishes asserts
the I2S:IRQFLAGS.PTR_ERR register.

1542

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Samplestamp Generator

www.ti.com

22.8 Samplestamp Generator
The samplestamp generator is mainly used to control the I/O streams of the I2S module. It also provides a
way to synchronize I2S modules over wireless networks to achieve correct and fixed audio latency.
The samplestamp generator is enabled and is running when I2S:STMPCTL.STMP_EN = 1. When the
I2S:STMPCTL.STMP_EN register goes from 1 to 0, all internal counters and capture values are reset. The
samplestamp generator must always be enabled because it controls I/O streaming.

22.8.1 Counters and Registers
The samplestamp generator contains the following parts that are based on two counters:
1. STMPXCNT counts XOSC (clock) cycles between positive WCLK edges. The counter value can be
read from the I2S:STMPXCNT register.
2. STMPWCNT counts positive WCLK edges and modulo the size of the sample ring buffer. The modulo
value is given by the I2S:STMPWPER register. The counter value can be read from the
I2S:STMPWCNT register.
The lower part of Figure 22-8 shows the part of the samplestamp generator that is used by the I2S module
to control the I/O pins on the serial audio interface.
The upper part of Figure 22-8, inside the dotted line, includes optional functionality in the form of capturing
registers which can be used, for example, in real-time streaming applications to achieve fixed latency and
I2S synchronization in a wireless network.
Figure 22-8. Samplestamp Generator Structure
samplestamp_req

I2S:STMPXCNTCAPT0
I2S:STMPXCNTCAPT1

STMPXCNT
I2S:STMPXPER

WCLK_pos_edge

samplestamp_req

I2S:STMPXCNTCAPT0
I2S:STMPXCNTCAPT1

WCLK_pos_edge

STMPWCNT

I2S:STMPWPER
I2S:STMPINTRIG

I2S:STMPCTL.IN_RDY

I2S:STMPOUTTRIG

I2S:STMPCTL.OUT_RDY

NOTE: During start-up, if WCLK is high during the first BCLK cycles, there can be one or two false
WCLK_pos_edge pulses:
•
One due to the level of the selected WCLK source
•
Another if the I2S:AIFFMTCFG.SMPL_EDGE register is not changed from 1 to 0 before
BCLK starts running

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1543

Samplestamp Generator

www.ti.com

22.8.2 Starting Input and Output Pins
The I2S:STMPINTRIG and the I2S:STMPOUTTRIG registers contain WCLK counter compare values that
are used to start the input and output audio streaming, respectively:
• When the WCLK counter value reaches the I2S:STMPINTRIG register and the I2S:STMPCTL.IN_RDY
register is set, the memory interface controller begins storing samples to memory in the next frame:
[(STMPINTRIG + 1) % STMPWPER].
• When the WCLK counter value reaches the I2S:STMPOUTTRIG register and the
I2S:STMPCTL.OUT_RDY register is set, the memory interface controller begins outputting samples
loaded from memory in the next frame: [(STMPINTRIG + 1) % STMPWPER].

22.8.3 Samplestamp Capturing
A pulse on samplestamp_req captures the XOSC and WCLK counter values for later retrieval:
• I2S:STMPXCNTCAPTn = the XOSC counter at time of capture
• I2S:STMPXPER = the number of XOSC cycles in the previous WCLK period
• I2S:STMPWCNTCAPTn = the WCLK counter at time of capture
The samplestamp value used is a fixed-point number, INT.FRAC, where:
• INT = I2S:STMPWCNTCAPTn
• FRAC = I2S:STMPXCNTCAPTn and I2S:STMPXPER
NOTE: Because the I2S:STMPXPER register is in the previous period value, saturation of the
I2S:STMPXCNTCAPTn registers must be handled in software (if required).

NOTE: The samplestamp_req pulse can be generated by different radio events that are configured
outside the I2S module, see the EVENT:I2SSTMPSEL0 register.

1544

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Usage

www.ti.com

22.9 Usage
This section describes the recommended start-up and termination sequences.

22.9.1 Start-up Sequence
The configuration of the I2S module must be carried out in the following order:
1. Set up and configure required ADx and clock pins (set externally in the IOC module).
2. Enable I2S peripheral and configure WCLK and MCLK audio clocks (set externally in the PRCM
module).
3. Configure the serial audio interface format and the memory interface controller:
• Set the following registers: I2S:AIFWCLKSRC, I2S:AIFDIRCFG, I2S:AIFFMTCFG,
I2S:AIFWMSK0, I2S:AIFWMSK1, and I2S:AIFWMSK2. BCLK must not be running when changing
the I2S:AIFWCLKSRC register.
4. Enable BCLK (set externally in the PRCM module).
5. Configure and prepare the samplestamp generator:
• Set the I2S:STMPWPER register. This number corresponds to the total size of the sample ring
buffer used by the system.
• Set the two registers I2S:STMPINTRIG and I2S:STMPOUTTRIG > I2S:STMPWPER to avoid false
triggers before the samplestamp generator is started.
6. Enable the samplestamp generator:
• Set I2S:STMPCTRL.STMP_EN = 1
• Optional steps:
– Poll the I2S:STMPWCNT register and wait until the counter value is 2 or higher:
• When the value is 2 or higher, there are no more false increments (as described in
Section 22.8.1).
• When the value is 4 or higher, the WCLK period is read out from the I2S:STMPXPER
register. This is used to determine the sample rate when using an external clock source.
• Reset the WCLK counter by writing I2S:STMPWSET = 0
7. Enable the serial audio interface:
• Set the I2S:AIFINPTRNEXT and the I2S:AIFOUTPTRNEXT registers for first memory interface
buffers.
• Set the I2S:AIFDMACFG register; This number corresponds to the length of each block in the
sample ring buffer used by the system.
• Set the I2S:AIFINPTRNEXT and the I2S:AIFOUTPTRNEXT registers for second memory interface
buffers.
8. Start input and output audio streaming:
• Set the I2S:STMPINTRIG and the I2S:STMPOUTTRIG registers so they correctly match the
I2S:AIFINPTR and the I2S:AIFOUTPTR registers.
NOTE: When using I2S with the CPU in deepsleep (idle power mode) the system bus is not kept on
automatically, causing the I2S DMA not to get access to flash or RAM. A workaround to keep
the system bus on is to assert either PRCM:SECDMACLKGDS.DMA_CLK_EN or
PRCM:SECDMACLKGDS.CRYPTO_CLK_EN by enabling either the DMA or the Crypto
module respectively.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1545

Usage

www.ti.com

22.9.2 Termination Sequence
The termination sequence consists of six steps that ensure the I2S module completes all buffers before
closing down I/O pins. If this is not important and the system allows read and write access to NULL, Step
1, Step 2, and Step 5 may be ignored.
1. Do not update (or write NULL to) the I2S:AIFINPTRNEXT or the I2S:AIFOUTPTRNEXT registers at
memory interface in/out interrupt.
2. Await next memory interface in/out interrupt:
• The I2S module closes down the input/output pins after this interrupt because NULL is loaded as
pointer.
• The I2S:IRQFLAGS.PTR_ERR register is set because NULL is loaded as pointer, and the I2S
module error interrupt is generated.
3. Set I2S:AIFDMACFG = 0.
4. Set I2S:STMPCTL.STMP_EN = 0.
5. Clear the I2S:IRQFLAGS.PTR_ERR register.
6. Disable the BCLK source (done externally in the PRCM module).

1546

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10 I2S Registers
22.10.1 I2S Registers
Table 22-1 lists the memory-mapped registers for the I2S. All register offset addresses not listed in
Table 22-1 should be considered as reserved locations and the register contents should not be modified.
Table 22-1. I2S Registers
Offset

Acronym

Section

AIFWCLKSRC

WCLK Source Selection

Section 22.10.1.1

AIFDMACFG

DMA Buffer Size Configuration

Section 22.10.1.2

AIFDIRCFG

Pin Direction

Section 22.10.1.3

AIFFMTCFG

Serial Interface Format Configuration

Section 22.10.1.4

10h

AIFWMASK0

Word Selection Bit Mask for Pin 0

Section 22.10.1.5

14h

AIFWMASK1

Word Selection Bit Mask for Pin 1

Section 22.10.1.6

18h

AIFWMASK2

Word Selection Bit Mask for Pin 2

Section 22.10.1.7

1Ch

AIFPWMVALUE

Audio Interface PWM Debug Value

Section 22.10.1.8

20h

AIFINPTRNEXT

DMA Input Buffer Next Pointer

Section 22.10.1.9

24h

AIFINPTR

DMA Input Buffer Current Pointer

Section 22.10.1.10

28h

AIFOUTPTRNEXT

DMA Output Buffer Next Pointer

Section 22.10.1.11

2Ch

AIFOUTPTR

DMA Output Buffer Current Pointer

Section 22.10.1.12

34h

STMPCTL

SampleStaMP Generator Control Register

Section 22.10.1.13

38h

STMPXCNTCAPT0

Captured XOSC Counter Value, Capture Channel 0

Section 22.10.1.14

3Ch

STMPXPER

XOSC Period Value

Section 22.10.1.15

40h

STMPWCNTCAPT0

Captured WCLK Counter Value, Capture Channel 0

Section 22.10.1.16

44h

STMPWPER

WCLK Counter Period Value

Section 22.10.1.17

48h

STMPINTRIG

WCLK Counter Trigger Value for Input Pins

Section 22.10.1.18

4Ch

STMPOUTTRIG

WCLK Counter Trigger Value for Output Pins

Section 22.10.1.19

50h

STMPWSET

WCLK Counter Set Operation

Section 22.10.1.20

54h

STMPWADD

WCLK Counter Add Operation

Section 22.10.1.21

58h

STMPXPERMIN

XOSC Minimum Period Value

Section 22.10.1.22

5Ch

STMPWCNT

Current Value of WCNT

Section 22.10.1.23

60h

STMPXCNT

Current Value of XCNT

Section 22.10.1.24

64h

STMPXCNTCAPT1

Captured XOSC Counter Value, Capture Channel 1

Section 22.10.1.25

68h

STMPWCNTCAPT1

Captured WCLK Counter Value, Capture Channel 1

Section 22.10.1.26

70h

IRQMASK

Masked Interrupt Status Register

Section 22.10.1.27

74h

IRQFLAGS

Raw Interrupt Status Register

Section 22.10.1.28

78h

IRQSET

Interrupt Set Register

Section 22.10.1.29

7Ch

IRQCLR

Interrupt Clear Register

Section 22.10.1.30

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1547

I2S Registers

www.ti.com

22.10.1.1 AIFWCLKSRC Register (Offset = 0h) [reset = 0h]
AIFWCLKSRC is shown in Figure 22-9 and described in Table 22-2.
Return to Summary Table.
WCLK Source Selection
Figure 22-9. AIFWCLKSRC Register
31

2
WCLK_INV
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

0
WCLK_SRC
R/W-0h

Table 22-2. AIFWCLKSRC Register Field Descriptions
Bit

Field

Type

Reset

Description

31-3

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

WCLK_INV

R/W

Inverts WCLK source (pad or internal) when set.
0: Not inverted
1: Inverted

1-0

WCLK_SRC

R/W

Selects WCLK source for AIF (should be the same as the BCLK
source). The BCLK source is defined in the
PRCM:I2SBCLKSEL.SRC
0h = None ('0')
1h = External WCLK generator, from pad
2h = Internal WCLK generator, from module PRCM/ClkCtrl
3h = Not supported. Will give same WCLK as 'NONE' ('00')

1548

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.2 AIFDMACFG Register (Offset = 4h) [reset = 0h]
AIFDMACFG is shown in Figure 22-10 and described in Table 22-3.
Return to Summary Table.
DMA Buffer Size Configuration
Figure 22-10. AIFDMACFG Register
31

12
11
RESERVED
R-0h

24
23
RESERVED
R-0h
8

4
3
END_FRAME_IDX
R/W-0h

Table 22-3. AIFDMACFG Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

END_FRAME_IDX

R/W

Defines the length of the Writing a non-zero value to this registerfield
enables and initializes AIF. Note that before doing so, all other
configuration must have been done, and AIFINPTR/AIFOUTPTR
must have been loaded.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1549

I2S Registers

www.ti.com

22.10.1.3 AIFDIRCFG Register (Offset = 8h) [reset = 0h]
AIFDIRCFG is shown in Figure 22-11 and described in Table 22-4.
Return to Summary Table.
Pin Direction
Figure 22-11. AIFDIRCFG Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

RESERVED
R-0h

8
AD2
R/W-0h

AD1
R/W-0h

2
RESERVED
R-0h

0
AD0
R/W-0h

Table 22-4. AIFDIRCFG Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

9-8

AD2

R/W

Configures the AD2 audio data pin usage
0x3: Reserved
0h = Not in use (disabled)
1h = Input mode
2h = Output mode

7-6

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

5-4

AD1

R/W

Configures the AD1 audio data pin usage:
0x3: Reserved
0h = Not in use (disabled)
1h = Input mode
2h = Output mode

3-2

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

1-0

AD0

R/W

Configures the AD0 audio data pin usage:
0x3: Reserved
0h = Not in use (disabled)
1h = Input mode
2h = Output mode

31-10

1550

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.4 AIFFMTCFG Register (Offset = Ch) [reset = 170h]
AIFFMTCFG is shown in Figure 22-12 and described in Table 22-5.
Return to Summary Table.
Serial Interface Format Configuration
Figure 22-12. AIFFMTCFG Register
31

2
WORD_LEN
R/W-10h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
DATA_DELAY
R/W-1h

7
MEM_LEN_24
R/W-0h

6
SMPL_EDGE
R/W-1h

5
DUAL_PHASE
R/W-1h

Table 22-5. AIFFMTCFG Register Field Descriptions
Bit

Field

Type

Reset

Description

31-16

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-8

DATA_DELAY

R/W

The number of BCLK periods between a WCLK edge and MSB of
the first word in a phase:
0x00: LJF format
0x01: I2S and DSP format
0x02: RJF format
...
0xFF: RJF format
Note: When 0, MSB of the next word will be output in the idle period
between LSB of the previous word and the start of the next word.
Otherwise logical 0 will be output until the data delay has expired.

MEM_LEN_24

R/W

The size of each word stored to or loaded from memory:
0h = 16BIT : 16-bit (one 16 bit access per sample)
1h = 24BIT : 24-bit (one 8 bit and one 16 bit locked access per
sample)

SMPL_EDGE

R/W

On the serial audio interface, data (and wclk) is sampled and
clocked out on opposite edges of BCLK.
0h = Data is sampled on the negative edge and clocked out on the
positive edge.
1h = Data is sampled on the positive edge and clocked out on the
negative edge.

DUAL_PHASE

R/W

Selects dual- or single-phase format.
0: Single-phase
1: Dual-phase

WORD_LEN

R/W

10h

Number of bits per word (8-24):
In single-phase format, this is the exact number of bits per word.
In dual-phase format, this is the maximum number of bits per word.
Values below 8 and above 24 give undefined behavior. Data written
to memory is always aligned to 16 or 24 bits as defined by
MEM_LEN_24. Bit widths that differ from this alignment will either be
truncated or zero padded.

4-0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1551

I2S Registers

www.ti.com

22.10.1.5 AIFWMASK0 Register (Offset = 10h) [reset = 3h]
AIFWMASK0 is shown in Figure 22-13 and described in Table 22-6.
Return to Summary Table.
Word Selection Bit Mask for Pin 0
Figure 22-13. AIFWMASK0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R/W-0h

4 3 2
MASK
R/W-3h

Table 22-6. AIFWMASK0 Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

MASK

R/W

Bit-mask indicating valid channels in a frame on AD0.
In single-phase mode, each bit represents one channel, starting with
LSB for the first word in the frame. A frame can contain up to 8
channels. Channels that are not included in the mask will not be
sampled and stored in memory, and clocked out as '0'.
In dual-phase mode, only the two LSBs are considered. For a stereo
configuration, set both bits. For a mono configuration, set bit 0 only.
In mono mode, only channel 0 will be sampled and stored to
memory, and channel 0 will be repeated when clocked out.
In mono mode, only channel 0 will be sampled and stored to
memory, and channel 0 will be repeated in the second phase when
clocked out.
If all bits are zero, no input words will be stored to memory, and the
output data lines will be constant '0'. This can be utilized when PWM
debug output is desired without any actively used output pins.

1552

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.6 AIFWMASK1 Register (Offset = 14h) [reset = 3h]
AIFWMASK1 is shown in Figure 22-14 and described in Table 22-7.
Return to Summary Table.
Word Selection Bit Mask for Pin 1
Figure 22-14. AIFWMASK1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
MASK
R/W-3h

Table 22-7. AIFWMASK1 Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

MASK

R/W

Bit-mask indicating valid channels in a frame on AD1.
In single-phase mode, each bit represents one channel, starting with
LSB for the first word in the frame. A frame can contain up to 8
channels. Channels that are not included in the mask will not be
sampled and stored in memory, and clocked out as '0'.
In dual-phase mode, only the two LSBs are considered. For a stereo
configuration, set both bits. For a mono configuration, set bit 0 only.
In mono mode, only channel 0 will be sampled and stored to
memory, and channel 0 will be repeated when clocked out.
In mono mode, only channel 0 will be sampled and stored to
memory, and channel 0 will be repeated in the second phase when
clocked out.
If all bits are zero, no input words will be stored to memory, and the
output data lines will be constant '0'. This can be utilized when PWM
debug output is desired without any actively used output pins.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1553

I2S Registers

www.ti.com

22.10.1.7 AIFWMASK2 Register (Offset = 18h) [reset = 3h]
AIFWMASK2 is shown in Figure 22-15 and described in Table 22-8.
Return to Summary Table.
Word Selection Bit Mask for Pin 2
Figure 22-15. AIFWMASK2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

4 3 2
MASK
R/W-3h

Table 22-8. AIFWMASK2 Register Field Descriptions
Field

Type

Reset

Description

31-8

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

7-0

MASK

R/W

Bit-mask indicating valid channels in a frame on AD2
In single-phase mode, each bit represents one channel, starting with
LSB for the first word in the frame. A frame can contain up to 8
channels. Channels that are not included in the mask will not be
sampled and stored in memory, and clocked out as '0'.
In dual-phase mode, only the two LSBs are considered. For a stereo
configuration, set both bits. For a mono configuration, set bit 0 only.
In mono mode, only channel 0 will be sampled and stored to
memory, and channel 0 will be repeated when clocked out.
In mono mode, only channel 0 will be sampled and stored to
memory, and channel 0 will be repeated in the second phase when
clocked out.
If all bits are zero, no input words will be stored to memory, and the
output data lines will be constant '0'. This can be utilized when PWM
debug output is desired without any actively used output pins.

1554

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.8 AIFPWMVALUE Register (Offset = 1Ch) [reset = 0h]
AIFPWMVALUE is shown in Figure 22-16 and described in Table 22-9.
Return to Summary Table.
Audio Interface PWM Debug Value
Figure 22-16. AIFPWMVALUE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
RESERVED
PULSE_WIDTH
R-0h
R/W-0h

Table 22-9. AIFPWMVALUE Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

PULSE_WIDTH

R/W

The value written to this register determines the width of the active
high PWM pulse (pwm_debug), which starts together with MSB of
the first output word in a DMA buffer:
0x0000: Constant low
0x0001: Width of the pulse (number of BCLK cycles, here 1).
...
0xFFFE: Width of the pulse (number of BCLK cycles, here 65534).
0xFFFF: Constant high

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1555

I2S Registers

www.ti.com

22.10.1.9 AIFINPTRNEXT Register (Offset = 20h) [reset = 0h]
AIFINPTRNEXT is shown in Figure 22-17 and described in Table 22-10.
Return to Summary Table.
DMA Input Buffer Next Pointer
Figure 22-17. AIFINPTRNEXT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PTR
R/W-0h

Table 22-10. AIFINPTRNEXT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

PTR

R/W

Pointer to the first byte in the next DMA input buffer.
The read value equals the last written value until the currently used
DMA input buffer is completed, and then becomes null when the last
written value is transferred to the DMA controller to start on the next
buffer. This event is signalized by aif_dma_in_irq.
At startup, the value must be written once before and once after
configuring the DMA buffer size in AIFDMACFG.
The next pointer must be written to this register while the DMA
function uses the previously written pointer. If not written in time,
IRQFLAGS.PTR_ERR will be raised and all input pins will be
disabled.
Note the following limitations:
- Address space wrapping is not supported. That means address(last
sample) must be higher than address(first sample.
- A DMA block cannot be aligned with the end of the address space,
that means a block cannot contain the address 0xFFFF.

1556

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.10 AIFINPTR Register (Offset = 24h) [reset = 0h]
AIFINPTR is shown in Figure 22-18 and described in Table 22-11.
Return to Summary Table.
DMA Input Buffer Current Pointer
Figure 22-18. AIFINPTR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PTR
R/W-0h

Table 22-11. AIFINPTR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

PTR

R/W

Value of the DMA input buffer pointer currently used by the DMA
controller. Incremented by 1 (byte) or 2 (word) for each AHB access.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1557

I2S Registers

www.ti.com

22.10.1.11 AIFOUTPTRNEXT Register (Offset = 28h) [reset = 0h]
AIFOUTPTRNEXT is shown in Figure 22-19 and described in Table 22-12.
Return to Summary Table.
DMA Output Buffer Next Pointer
Figure 22-19. AIFOUTPTRNEXT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PTR
R/W-0h

Table 22-12. AIFOUTPTRNEXT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

PTR

R/W

Pointer to the first byte in the next DMA output buffer.
The read value equals the last written value until the currently used
DMA output buffer is completed, and then becomes null when the
last written value is transferred to the DMA controller to start on the
next buffer. This event is signalized by aif_dma_out_irq.
At startup, the value must be written once before and once after
configuring the DMA buffer size in AIFDMACFG. At this time, the
first two samples will be fetched from memory.
The next pointer must be written to this register while the DMA
function uses the previously written pointer. If not written in time,
IRQFLAGS.PTR_ERR will be raised and all output pins will be
disabled.
Note the following limitations:
- Address space wrapping is not supported. That means address(last
sample) must be higher than address(first sample.
- A DMA block cannot be aligned with the end of the address space,
that means a block cannot contain the address 0xFFFF.

1558

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.12 AIFOUTPTR Register (Offset = 2Ch) [reset = 0h]
AIFOUTPTR is shown in Figure 22-20 and described in Table 22-13.
Return to Summary Table.
DMA Output Buffer Current Pointer
Figure 22-20. AIFOUTPTR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PTR
R/W-0h

Table 22-13. AIFOUTPTR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

PTR

R/W

Value of the DMA output buffer pointer currently used by the DMA
controller Incremented by 1 (byte) or 2 (word) for each AHB access.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1559

I2S Registers

www.ti.com

22.10.1.13 STMPCTL Register (Offset = 34h) [reset = 0h]
STMPCTL is shown in Figure 22-21 and described in Table 22-14.
Return to Summary Table.
SampleStaMP Generator Control Register
Figure 22-21. STMPCTL Register
31

2
OUT_RDY
R-0h

1
IN_RDY
R-0h

0
STMP_EN
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

5
RESERVED
R-0h

Table 22-14. STMPCTL Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

OUT_RDY

Low until the output pins are ready to be started by the samplestamp
generator. When started (that is STMPOUTTRIG equals the WCLK
counter) the bit goes back low.

IN_RDY

Low until the input pins are ready to be started by the samplestamp
generator. When started (that is STMPINTRIG equals the WCLK
counter) the bit goes back low.

STMP_EN

R/W

Enables the samplestamp generator. The samplestamp generator
must only be enabled after it has been properly configured.
When cleared, all samplestamp generator counters and capture
values are cleared.

31-3

1560

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.14 STMPXCNTCAPT0 Register (Offset = 38h) [reset = 0h]
STMPXCNTCAPT0 is shown in Figure 22-22 and described in Table 22-15.
Return to Summary Table.
Captured XOSC Counter Value, Capture Channel 0
Figure 22-22. STMPXCNTCAPT0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

9 8 7 6
CAPT_VALUE
R-0h

Table 22-15. STMPXCNTCAPT0 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

CAPT_VALUE

The value of the samplestamp XOSC counter
(STMPXCNT.CURR_VALUE) last time an event was pulsed (event
source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0). This
number corresponds to the number of 24 MHz clock cycles since the
last positive edge of the selected WCLK.
The value is cleared when STMPCTL.STMP_EN = 0.
Note: Due to buffering and synchronization, WCLK is delayed by a
small number of BCLK periods and clk periods.
Note: When calculating the fractional part of the sample stamp,
STMPXPER may be less than this bit field.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1561

I2S Registers

www.ti.com

22.10.1.15 STMPXPER Register (Offset = 3Ch) [reset = 0h]
STMPXPER is shown in Figure 22-23 and described in Table 22-16.
Return to Summary Table.
XOSC Period Value
Figure 22-23. STMPXPER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7
VALUE
R-0h

Table 22-16. STMPXPER Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

VALUE

The number of 24 MHz clock cycles in the previous WCLK period
(that is - the next value of the XOSC counter at the positive WCLK
edge, had it not been reset to 0).
The value is cleared when STMPCTL.STMP_EN = 0.

1562

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.16 STMPWCNTCAPT0 Register (Offset = 40h) [reset = 0h]
STMPWCNTCAPT0 is shown in Figure 22-24 and described in Table 22-17.
Return to Summary Table.
Captured WCLK Counter Value, Capture Channel 0
Figure 22-24. STMPWCNTCAPT0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

9 8 7 6
CAPT_VALUE
R-0h

Table 22-17. STMPWCNTCAPT0 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

CAPT_VALUE

The value of the samplestamp WCLK counter
(STMPWCNT.CURR_VALUE) last time an event was pulsed (event
source selected in EVENT:I2SSTMPSEL0.EV for channel 0). This
number corresponds to the number of positive WCLK edges since
the samplestamp generator was enabled (not taking modification
through STMPWADD/STMPWSET into account).
The value is cleared when STMPCTL.STMP_EN = 0.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1563

I2S Registers

www.ti.com

22.10.1.17 STMPWPER Register (Offset = 44h) [reset = 0h]
STMPWPER is shown in Figure 22-25 and described in Table 22-18.
Return to Summary Table.
WCLK Counter Period Value
Figure 22-25. STMPWPER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
VALUE
R/W-0h

Table 22-18. STMPWPER Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

VALUE

R/W

Used to define when STMPWCNT is to be reset so number of WCLK
edges are found for the size of the sample buffer. This is thus a
modulo value for the WCLK counter. This number must correspond
to the size of the sample buffer used by the system (that is the index
of the last sample plus 1).

1564

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.18 STMPINTRIG Register (Offset = 48h) [reset = 0h]
STMPINTRIG is shown in Figure 22-26 and described in Table 22-19.
Return to Summary Table.
WCLK Counter Trigger Value for Input Pins
Figure 22-26. STMPINTRIG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
RESERVED
IN_START_WCNT
R-0h
R/W-0h

Table 22-19. STMPINTRIG Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

IN_START_WCNT

R/W

Compare value used to start the incoming audio streams.
This bit field shall equal the WCLK counter value during the WCLK
period in which the first input word(s) are sampled and stored to
memory (that is the sample at the start of the very first DMA input
buffer).
The value of this register takes effect when the following conditions
are met:
- One or more pins are configured as inputs in AIFDIRCFG.
- AIFDMACFG has been configured for the correct buffer size, and
at least 32 BCLK cycle ticks have happened.
Note: To avoid false triggers, this bit field should be set higher than
STMPWPER.VALUE.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1565

I2S Registers

www.ti.com

22.10.1.19 STMPOUTTRIG Register (Offset = 4Ch) [reset = 0h]
STMPOUTTRIG is shown in Figure 22-27 and described in Table 22-20.
Return to Summary Table.
WCLK Counter Trigger Value for Output Pins
Figure 22-27. STMPOUTTRIG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
RESERVED
OUT_START_WCNT
R-0h
R/W-0h

Table 22-20. STMPOUTTRIG Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

OUT_START_WCNT

R/W

Compare value used to start the outgoing audio streams.
This bit field must equal the WCLK counter value during the WCLK
period in which the first output word(s) read from memory are
clocked out (that is the sample at the start of the very first DMA
output buffer).
The value of this register takes effect when the following conditions
are met:
- One or more pins are configured as outputs in AIFDIRCFG.
- AIFDMACFG has been configured for the correct buffer size, and
32 BCLK cycle ticks have happened.
- 2 samples have been preloaded from memory (examine the
AIFOUTPTR register if necessary).
Note: The memory read access is only performed when required,
that is channels 0/1 must be selected in AIFWMASK0/AIFWMASK1.
Note: To avoid false triggers, this bit field should be set higher than
STMPWPER.VALUE.

1566

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.20 STMPWSET Register (Offset = 50h) [reset = 0h]
STMPWSET is shown in Figure 22-28 and described in Table 22-21.
Return to Summary Table.
WCLK Counter Set Operation
Figure 22-28. STMPWSET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
VALUE
R/W-0h

Table 22-21. STMPWSET Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

VALUE

R/W

WCLK counter modification: Sets the running WCLK counter equal
to the written value.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1567

I2S Registers

www.ti.com

22.10.1.21 STMPWADD Register (Offset = 54h) [reset = 0h]
STMPWADD is shown in Figure 22-29 and described in Table 22-22.
Return to Summary Table.
WCLK Counter Add Operation
Figure 22-29. STMPWADD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

9 8 7 6
VALUE_INC
R/W-0h

Table 22-22. STMPWADD Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

VALUE_INC

R/W

WCLK counter modification: Adds the written value to the running
WCLK counter. If a positive edge of WCLK occurs at the same time
as the operation, this will be taken into account.
To add a negative value, write "STMPWPER.VALUE - value".

1568

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.22 STMPXPERMIN Register (Offset = 58h) [reset = FFFFh]
STMPXPERMIN is shown in Figure 22-30 and described in Table 22-23.
Return to Summary Table.
XOSC Minimum Period Value
Minimum Value of STMPXPER
Figure 22-30. STMPXPERMIN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

8 7 6
VALUE
R/W-FFFFh

Table 22-23. STMPXPERMIN Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

VALUE

R/W

FFFFh

Each time STMPXPER is updated, the value is also loaded into this
register, provided that the value is smaller than the current value in
this register.
When written, the register is reset to 0xFFFF (65535), regardless of
the value written.
The minimum value can be used to detect extra WCLK pulses (this
registers value will be significantly smaller than
STMPXPER.VALUE).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1569

I2S Registers

www.ti.com

22.10.1.23 STMPWCNT Register (Offset = 5Ch) [reset = 0h]
STMPWCNT is shown in Figure 22-31 and described in Table 22-24.
Return to Summary Table.
Current Value of WCNT
Figure 22-31. STMPWCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

9 8 7 6
CURR_VALUE
R-0h

Table 22-24. STMPWCNT Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

CURR_VALUE

Current value of the WCLK counter

1570

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.24 STMPXCNT Register (Offset = 60h) [reset = 0h]
STMPXCNT is shown in Figure 22-32 and described in Table 22-25.
Return to Summary Table.
Current Value of XCNT
Figure 22-32. STMPXCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

9 8 7 6
CURR_VALUE
R-0h

Table 22-25. STMPXCNT Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

CURR_VALUE

Current value of the XOSC counter, latched when reading
STMPWCNT.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1571

I2S Registers

www.ti.com

22.10.1.25 STMPXCNTCAPT1 Register (Offset = 64h) [reset = 0h]
STMPXCNTCAPT1 is shown in Figure 22-33 and described in Table 22-26.
Return to Summary Table.
Captured XOSC Counter Value, Capture Channel 1
Figure 22-33. STMPXCNTCAPT1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

9 8 7 6
CAPT_VALUE
R-0h

Table 22-26. STMPXCNTCAPT1 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

CAPT_VALUE

Channel 1 is idle and can not be sampled from an external pulse as
with Channel 0 STMPXCNTCAPT0

1572

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.26 STMPWCNTCAPT1 Register (Offset = 68h) [reset = 0h]
STMPWCNTCAPT1 is shown in Figure 22-34 and described in Table 22-27.
Return to Summary Table.
Captured WCLK Counter Value, Capture Channel 1
Figure 22-34. STMPWCNTCAPT1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h

9 8 7 6
CAPT_VALUE
R-0h

Table 22-27. STMPWCNTCAPT1 Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-0

CAPT_VALUE

Channel 1 is idle and can not be sampled from an external event as
with Channel 0 STMPWCNTCAPT0

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1573

I2S Registers

www.ti.com

22.10.1.27 IRQMASK Register (Offset = 70h) [reset = 0h]
IRQMASK is shown in Figure 22-35 and described in Table 22-28.
Return to Summary Table.
Masked Interrupt Status Register
Figure 22-35. IRQMASK Register
31

3
WCLK_TIMEO
UT
R/W-0h

2
BUS_ERR

1
WCLK_ERR

0
PTR_ERR

R/W-0h

RESERVED
R/W-0h
23

20
RESERVED
R/W-0h

12
RESERVED
R/W-0h

7
RESERVED

5
AIF_DMA_IN

4
AIF_DMA_OUT

R/W-0h

Table 22-28. IRQMASK Register Field Descriptions
Field

Type

Reset

Description

31-6

Bit

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AIF_DMA_IN

R/W

Defines the masks state for the interrupt of IRQFLAGS.AIF_DMA_IN
0: Disable
1: Enable

AIF_DMA_OUT

R/W

Defines the masks state for the interrupt of
IRQFLAGS.AIF_DMA_OUT
0: Disable
1: Enable

WCLK_TIMEOUT

R/W

Defines the masks state for the interrupt of
IRQFLAGS.WCLK_TIMEOUT
0: Disable
1: Enable

BUS_ERR

R/W

Defines the masks state for the interrupt of IRQFLAGS.BUS_ERR
0: Disable
1: Enable

WCLK_ERR

R/W

Defines the masks state for the interrupt of IRQFLAGS.WCLK_ERR
0: Disable
1: Enable

PTR_ERR

R/W

Defines the masks state for the interrupt of IRQFLAGS.PTR_ERR
0: Disable
1: Enable

1574

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.28 IRQFLAGS Register (Offset = 74h) [reset = 0h]
IRQFLAGS is shown in Figure 22-36 and described in Table 22-29.
Return to Summary Table.
Raw Interrupt Status Register
Figure 22-36. IRQFLAGS Register
31

3
WCLK_TIMEO
UT
R-0h

2
BUS_ERR

1
WCLK_ERR

0
PTR_ERR

R-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

7
RESERVED

5
AIF_DMA_IN

4
AIF_DMA_OUT

R-0h

Table 22-29. IRQFLAGS Register Field Descriptions
Field

Type

Reset

Description

31-6

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AIF_DMA_IN

Set when condition for this bit field event occurs (auto cleared when
input pointer is updated - AIFINPTR), see description of AIFINPTR
register

AIF_DMA_OUT

Set when condition for this bit field event occurs (auto cleared when
output pointer is updated - AIFOUTPTR), see description of
AIFOUTPTR register for details

WCLK_TIMEOUT

Set when the sample stamp generator does not detect a positive
WCLK edge for 65535 clk periods. This signalizes that the internal or
external BCLK and WCLK generator source has been disabled.
The bit is sticky and may only be cleared by software (by writing '1'
to IRQCLR.WCLK_TIMEOUT).

BUS_ERR

Set when a DMA operation is not completed in time (that is audio
output buffer underflow, or audio input buffer overflow).
This error requires a complete restart since word synchronization
has been lost. The bit is sticky and may only be cleared by software
(by writing '1' to IRQCLR.BUS_ERR).
Note that DMA initiated transactions to illegal addresses will not
trigger an interrupt. The response to such transactions is undefined.

WCLK_ERR

Set when:
- An unexpected WCLK edge occurs during the data delay period of
a phase. Note unexpected WCLK edges during the word and idle
periods of the phase are not detected.
- In dual-phase mode, when two WCLK edges are less than 4 BCLK
cycles apart.
- In single-phase mode, when a WCLK pulse occurs before the last
channel.
This error requires a complete restart since word synchronization
has been lost. The bit is sticky and may only be cleared by software
(by writing '1' to IRQCLR.WCLK_ERR).

PTR_ERR

Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been
loaded with the next block address in time.
This error requires a complete restart since word synchronization
has been lost. The bit is sticky and may only be cleared by software
(by writing '1' to IRQCLR.PTR_ERR).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1575

I2S Registers

www.ti.com

22.10.1.29 IRQSET Register (Offset = 78h) [reset = 0h]
IRQSET is shown in Figure 22-37 and described in Table 22-30.
Return to Summary Table.
Interrupt Set Register
Figure 22-37. IRQSET Register
31

3
WCLK_TIMEO
UT
W-0h

2
BUS_ERR

1
WCLK_ERR

0
PTR_ERR

W-0h

RESERVED
W-0h
23

20
RESERVED
W-0h

12
RESERVED
W-0h

7
RESERVED

5
AIF_DMA_IN

4
AIF_DMA_OUT

W-0h

Table 22-30. IRQSET Register Field Descriptions
Field

Type

Reset

Description

31-6

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AIF_DMA_IN

1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear
criteria was given at the same time, in which the set will be ignored)

AIF_DMA_OUT

1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto
clear criteria was given at the same time, in which the set will be
ignored)

WCLK_TIMEOUT

1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT

BUS_ERR

1: Sets the interrupt of IRQFLAGS.BUS_ERR

WCLK_ERR

1: Sets the interrupt of IRQFLAGS.WCLK_ERR

PTR_ERR

1: Sets the interrupt of IRQFLAGS.PTR_ERR

1576

Inter-IC Sound (I2S) Module

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

I2S Registers

www.ti.com

22.10.1.30 IRQCLR Register (Offset = 7Ch) [reset = 0h]
IRQCLR is shown in Figure 22-38 and described in Table 22-31.
Return to Summary Table.
Interrupt Clear Register
Figure 22-38. IRQCLR Register
31

3
WCLK_TIMEO
UT
W-0h

2
BUS_ERR

1
WCLK_ERR

0
PTR_ERR

W-0h

RESERVED
W-0h
23

20
RESERVED
W-0h

12
RESERVED
W-0h

7
RESERVED

5
AIF_DMA_IN

4
AIF_DMA_OUT

W-0h

Table 22-31. IRQCLR Register Field Descriptions
Field

Type

Reset

Description

31-6

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

AIF_DMA_IN

1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set
criteria was given at the same time in which the clear will be ignored)

AIF_DMA_OUT

1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set
criteria was given at the same time in which the clear will be ignored)

WCLK_TIMEOUT

1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set
criteria was given at the same time in which the clear will be ignored)

BUS_ERR

1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria
was given at the same time in which the clear will be ignored)

WCLK_ERR

1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set
criteria was given at the same time in which the clear will be ignored)

PTR_ERR

1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria
was given at the same time in which the clear will be ignored)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Inter-IC Sound (I2S) Module

1577

Chapter 23
SWCU117G – February 2015 – Revised February 2017

Radio
The radio in the CC26x0 and CC13x0 devices offers a wide variety of different operational modes,
covering many different packet formats. The radio firmware executes from the CC26x0 and CC13x0 radio
domain on an ARM® Cortex®-M0 processor, which can provide extensive baseband automation. The
application software interfaces and interoperates with the radio firmware using shared memory interface
(system RAM or radio RAM) and specific handshake hardware (radio doorbell).
Topic

23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8

1578

Radio

...........................................................................................................................
RF Core .........................................................................................................
Radio Doorbell................................................................................................
RF Core HAL ..................................................................................................
Data Queue Usage ..........................................................................................
IEEE 802.15.4..................................................................................................
Bluetooth low energy ......................................................................................
Proprietary Radio ............................................................................................
Radio Registers ..............................................................................................

Page

1579
1580
1584
1621
1625
1649
1683
1707

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core

www.ti.com

23.1 RF Core
The RF core contains an ARM Cortex-M0 processor that interfaces the analog RF and baseband
circuitries, handles data to and from the system side, and assembles the information bits in a given packet
structure. The RF core offers a high-level, command-based application program interface (API) to the
system CPU (ARM® Cortex®-M3). The RF core can autonomously handle the time-critical aspects of the
radio protocols (802.15.4 RF4CE and ZigBee®, Bluetooth® low energy, and so on), thus offloading the
system CPU and leaving more resources for the user’s application.
The RF core has a dedicated 4-KB SRAM block and runs almost entirely from separate ROM.

23.1.1 High-Level Description and Overview
The RF core receives high-level requests from the system CPU and performs all the necessary
transactions to fulfill them. These requests are primarily oriented to the transmission and reception of
information through the radio channel, but can also include additional maintenance tasks such as
calibration, test, or debug features.
As a general framework, the transactions between the system CPU and the RF core operate as follows:
• The RF core can access data and configuration parameters from the system RAM. This access
reduces the memory requirements of the RF core, avoids needless traffic between the different parts of
the system, and reduces the total energy consumption.
• In a similar fashion, the RF core can decode and write back the contents of the received radio packet,
together with status information, to the system RAM.
• For protocol confidentiality and authentication support purposes, the RF core can also access the
security subsystem.
• In general, the RF core recognizes complex commands from the system CPU (CCA transmissions, RX
with automatic acknowledge, and so forth) and divides them into subcommands without further
intervention of the system CPU.
Figure 23-1 shows the external interfaces and dependencies of the RF core.
Figure 23-1. Limited RF Core Overview With External Dependencies
RF Core
System
CPU
Cortex-M3

DMA

Radio
CPU
Cortex-M0

Bus bridge
L1 interconnect

Other
peripherals

M
L2 interconnect

Modem, frequency
synthesizer, and
RF interfaces

A
D
I

M
System flash
128KB

Security
subsystem

System RAM
20KB

Legend
Bus Fabric
Analog/Digital Signals
M

Bus Master

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1579

Radio Doorbell

www.ti.com

Each block in Figure 23-1 performs the following functions:
System Side
• System CPU: Main system processor that runs the user's application, together with the high-level
protocol stack (for a number of supported configurations) and eventually some higher-level MAC
features for some protocols. The system CPU runs code from the boot ROM and the system flash.
• System RAM: Contains packet information (TX and RX payloads) and the different parameters or
configuration options for a given transaction.
• Security Subsystem: Encompasses the different elements to provide protocol confidentiality and
authentication.
• DMA: Optionally charged with the task of moving information from the radio RAM to the system RAM
and vice versa, if direct CPU access is not used.
Radio Side
• Radio CPU: Main RF core processor. Receives high-level commands from the system CPU and
schedules them into the different parts of the RF core.
• Modem, Frequency Synthesizer, RF Interfaces: This is the core of the radio, converting the bits into
modulated signals and vice versa.

23.2 Radio Doorbell
The radio doorbell module (RFC_DBELL) is the primary means of communication between the system
CPU and the radio CPU, also known as command and packet engine (CPE). The radio doorbell contains
a set of dedicated registers, parameters in any of the RAMs of the device, and a set of interrupts to both
the radio CPU and the system CPU.
In addition, parameters and payload are transferred through the system RAM or the radio RAM. If any
parameters or payload are in the system RAM, the system CPU must remain powered, while if everything
is in the radio RAM, the system CPU may go into power-down mode to save current.
During operation, the radio CPU updates parameters and payload in RAM and raises interrupts. The
system CPU may mask out interrupts, so that it remains in idle or power-down mode until the entire radio
operation finishes.
Because the system CPU and the radio CPU share a common RAM area, ensure that no contention or
race conditions can occur. This is achieved in software by rules set up in the radio hardware abstraction
layer (HAL).

1580

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Doorbell

www.ti.com

Figure 23-2 shows the relevant modules for information exchange between the CPUs.
Figure 23-2. Hardware Support for the HAL
Radio Doorbell

Event Fabric

IRQs to
System CPU

Wake-up IRQ
Controller

CMDSTA

CMDR
System RAM

System
CPU

Radio RAM

Radio
CPU

IRQ to Radio
CPU

23.2.1 Command and Status Register and Events
Commands are sent to the radio through the CMDR register, while the CMDSTA read-only register
provides status back from the radio. The CMDR register can only be written while it reads 0; otherwise,
writes are ignored. When the CMDR register is 0 and a nonzero value is written to it, the radio CPU is
notified and the CMDSTA register becomes 0. After this, the value written is readable from the CMDR
register until the radio CPU has processed the command, at which point it goes back to 0.
When the command has been processed by the radio CPU, the CMDSTA register contains a nonzero
status, which is provided when the CMDR register goes back to 0. At the same time, an RFCMDACK
interrupt occurs. This interrupt is also mapped to the RFACKIFG register, which should be cleared when
the interrupt has been processed.
See Section 23.3.2 for the format of the command and status registers.

23.2.2 RF Core Interrupts
The RF core has four interrupt lines to the ARM Cortex-M3 (see Figure 23-2). The following interrupts are
controlled by the radio doorbell module:
• RF_CPE0 (interrupt number 9)
• RF_CPE1 (interrupt number 2)
• RF_HW (interrupt number 10)
• RF_CMD_ACK (interrupt number 11)
23.2.2.1 RF Command and Packet Engine Interrupts
The two system-level interrupts RF_CPE0 and RF_CPE1 can be produced from a number of low-level
interrupts produced by the CPE. Each of these low-level interrupts can be mapped to RF_CPE0 or
RF_CPE1 using the RFCPEISL register. In addition, interrupt generation at system level may be switched
on and off using the RFCPEIEN register.
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1581

Radio Doorbell

www.ti.com

In case of an event that triggers a low-level interrupt, the corresponding bit in the RFCPEIFG register is
set to 1. Whenever a bit in RFCPEIFG and the corresponding bit in RFCPEIEN are both 1, the systemlevel interrupt selected in RFCPEISL is raised. This means that the interrupt service routine (ISR) must
clear the bits in RFCPEIFG that correspond to low-level interrupts that have been processed.
A list of the available interrupts is found in the register description for RFCPEIFG in Section 23.8.2.5.
Clearing bits in RFCPEIFG is done by writing 0 to those bits, while any bits written to 1 remain
unchanged.
NOTE: When clearing bits in the RFCPEIFG register, interrupts may be lost if a read-modify-write
operation is done because interrupt flags that became active between the read and write
operation might be lost. Thus, clearing an interrupt flag should be done as follows:

HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = ~(1 << irq_no);
and not as:

HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) &= ~(1 <<
irq_no); // wrong
23.2.2.2 RF Core Hardware Interrupts
The system-level interrupt RF_HW can be produced from a number of low-level interrupts produced by RF
core hardware. Interrupt generation at the system level may be switched on and off for each source by
using the RFHWEN register.
In the case of an event that triggers a low-level interrupt, the corresponding bit in the RFHWIFG register is
set to 1. Whenever a bit in RFHWIFG and the corresponding bit in RFHWIEN are both 1, the RF_HW
interrupt is raised. This means that the ISR should clear the bits in RFHWIFG that correspond to low-level
interrupts that have been processed.
A list of the available interrupts is found in the register description for RFHWIFG in Section 23.8.2.3. In
general, TI does not recommend servicing these interrupts in the main CPU, but the available radio timer
channel interrupts may be served this way.
Clearing bits in RFHWIFG is done by writing 0 to those bits, while any bits written to 1 remain unchanged.
NOTE: When clearing bits in RFHWIFG, interrupts may be lost if a read-modify-write operation is
done. Therefore, the same rule applies for the RFHWIFG register as for RFCPEIFG (see
Section 23.2.2.1).

23.2.2.3 RF Core Command Acknowledge Interrupt
The system-level interrupt RF_CMD_ACK is produced when an RF core command is acknowledged (that
is, when the status becomes available in CMDSTA [see Section 23.8.2.2]). When the status becomes
available, the RFACKIFG.ACKFLAG register bit is set to 1. Whenever this bit is 1, the RF_CMD_ACK
interrupt is raised, which means that the ISR must clear RFACKIFG.ACKFLAG when processing the
RF_CMD_ACK interrupt.

23.2.3 Radio Timer
The radio has its own dedicated timer, the radio timer (RAT) module. The RAT is a 32-bit free-running
timer running on 4 MHz. The RAT has 8 channels with compare and capture functionality. Five of these
channels are reserved for the radio CPU, while the remaining three channels are available for use by the
ARM Cortex-M3. The available channels are numbered 5, 6, and 7.

1582

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Doorbell

www.ti.com

The RAT can only run while the RF core is powered up. The RAT must be started by the command
CMD_START_RAT or CMD_SYNC_START_RAT. The RAT must be running to execute a radio operation
command with delayed start or any radio operation command that runs the receiver or transmitter.
When the RAT is running, the current value of the timer can be read from the RATCNT register (see
Section 23.8.1.1).
23.2.3.1 Compare and Capture Events
The available channels may be set up in compare mode or capture mode.
Compare mode can be set up using the CMD_SET_RAT_CMP command (see Section 23.3.4.10). In this
case, the timer generates an interrupt when the counter reaches the value given by compareTime. The
interrupt is mapped to RFHWIFG (see Section 23.2.2.2 and Section 23.8.2.3). For the available RAT
channels, the interrupt flags in use are RATCH5, RATCH6, and RATCH7. Optionally, it is also possible to
control an I/O pin when the counter reaches the value given by compareTime (see Section 23.2.3.2).
When the CMD_SET_RAT_CMP command has been sent, the value of compareTime is stored in the
radio channel value register (RATCHnVAL) corresponding to the selected channel (see Table 23-154).
Capture mode can be used to capture a transition on an input pin and record the value of the RAT counter
at the time when the transition occurred. Compare mode can be set up using the CMD_SET_RAT_CPT
command (see Section 23.3.4.11). When the transition occurs, the current value of the RAT is stored in
the RATCHnVAL register corresponding to the selected channel (see Table 23-154), and the timer
generates an interrupt. As for compare mode, the interrupt is mapped to RFHWIFG. For the available RAT
channels, the interrupt flags in use are RATCH5, RATCH6, and RATCH7. If single-capture mode is
configured in CMD_SET_CPT, only the first transition is captured, unless the channel is armed again, as
explained in the following paragraph. If repeated mode is configured, every transition is captured.
NOTE: In this case, the captured value in the RATCHnVAL register may be overwritten at any time if
a new transition occurs.

A channel set up in compare mode or single capture mode may be armed or disarmed. When
CMD_SET_RAT_CMP or CMD_SET_RAT_CPT is sent, the channel is armed automatically, and when the
capture or compare event occurs, the channel is disarmed automatically. A disarmed channel does not
produce any interrupt or cause any timer value to be captured. In addition, a channel may be armed or
disarmed using CMD_ARM_RAT_CH or CMD_DISARM_RAT_CH (see Section 23.3.4.14 to
Section 23.3.4.15). While disarmed, the channel keeps its configuration. To disable a channel that is not
going to be re-armed with the same configuration, the CMD_DISABLE_RAT_CH command may be used
(see Section 23.3.4.12).
23.2.3.2 Radio Timer Outputs
The RAT module has four controllable outputs, RAT_GPO0 to RAT_GPO3. These signals may be
controlled by one of the RAT channels and mapped to signals available for the IOC using the
SYSGPOCTL register (see Section 23.8.2.9). RAT_GPO0 is reserved for starting the transmitter and is
controlled internally by the radio CPU (see Section 23.3.2.8). The other three signals may be configured
using the CMD_SET_RAT_OUTPUT command (see Section 23.3.4.11). The different output modes
decide the transition of the output when an interrupt occurs on the chosen RAT channel except for the
always-0 and always-1 configurations, which take effect immediately and may be used for initialization.
23.2.3.3 Synchronization With Real-Time Clock
When the radio is powered down, the RAT module is not counting. To keep a consistent time base over
time for synchronized protocols, it is possible to synchronize the RAT with the real-time clock (RTC) (see
Chapter 14).
To allow synchronization after power up, the CMD_SYNC_STOP_RAT command (see
Section 23.3.3.1.10) must be sent before the RF core is powered down. This command (until the next
RTC tick) stops the RAT and returns a parameter rat0, and should be stored and provided when the RAT
is restarted.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1583

RF Core HAL

www.ti.com

The next time the RF core is powered up and the RAT is started, this synchronization must be done using
CMD_SYNC_START_RAT (see Section 23.3.3.1.11), where the rat0 parameter obtained from
CMD_SYNC_STOP_RAT must be provided. This command starts the RAT, waits for an RTC tick, and
adjusts the RAT. Depending on the application, it may not be necessary to run the
CMD_SYNC_STOP_RAT command every time the radio is powered down; a previous value of rat0 may
be reused. In some cases, however, this may cause issues if the radio has been powered for a long time
and the low-frequency and high-frequency crystal oscillators have a significant error relative to each other.
To get accurate synchronization, it is important that the system is running on the high-frequency crystal
oscillator starting before the CMD_SYNC_START_RAT command is run and extending beyond
completion of the CMD_SYNC_STOP_RAT command.
For the CMD_SYNC_START_RAT and CMD_SYNC_STOP_RAT commands, the AON_RTC:CTL
RTC_UPD_EN register bit must be set to 1 (see Section 14.4.1.1). It is never necessary to reset this bit to
0; it may be set permanently to 1 when the RTC is started.

23.3 RF Core HAL
The RF core hides the complexity of the radio operations by providing a unified HAL to the system CPU.
NOTE: To ensure optimum radio performance always use the latest radio patches provided by TI.
See the product pages on www.ti.com for the latest patches.

23.3.1 Hardware Support
The radio HAL is supported by hardware, by means of the radio doorbell module in the RF core area and
command descriptors in the system RAM.

23.3.2 Firmware Support
The RF core accepts a set of high-level primitives. The following sections describe the desired
functionality at a high level.
23.3.2.1 Commands
The radio CPU lets the user run a set of high-level primitives or commands from the system CPU. After a
command has been issued through the CMDR register, the radio CPU examines it and decides a course
of action.
Three classes of commands are issued:
• Radio operation command
• Immediate command
• Direct command
For the first two classes of commands, CMDR contains a pointer to a command structure. This pointer
must be a valid pointer with 32-bit word alignment, so the 2 least significant bits (LSBs) must be 0 0, as
shown in Figure 23-3. A direct command is signaled by setting the 2 LSBs to 01 and placing the command
ID number in bits 16 to 31 of CMDR. Bits 8 through 15, or alternatively 2 through 15, may be used as an
optional byte parameter. Figure 23-4 shows the format for a direct command.
Figure 23-3. CMDR Register for Radio Operation Commands and Immediate Commands
Pointer to Command Structure (Bits 31-2)
31
MSB

1584

Radio

0
0
LSB

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

Figure 23-4. CMDR Register for Direct Commands

31
MSB

Optional Parameter
Extension

Optional Parameter

Command ID (16 Bits)
16

1
0
LSB

The data structure pointed to by the CMDR register for radio operation and immediate commands may be
in the system RAM, the radio RAM, or flash (the latter is possible only if the radio CPU does not write
anything to the command structure). The system CPU must ensure that the memory area in use is free for
access, in particular when using the radio RAM, where a part of the memory is reserved for use by the
radio CPU. This information may be obtained with the CMD_GET_FW_INFO command (see
Section 23.3.4.6). The format of the command follows the structure given in Section 23.3.2.6 and its
subsection, and are defined in more detail specifically for each command.
When deciding in which memory area to place data, consider which modules may be powered down:
• The radio RAM is accessible for the radio CPU at any time, but does not have retention when the radio
is powered down. Data that must be retained must therefore be copied into or out of the radio RAM
whenever the radio is powered up or down, respectively.
• The system RAM has retention in most low-power modes. If the system side is powered down, the
radio CPU requests that it is powered up again to access the RAM. The active current consumption
from the radio CPU accessing the system RAM is higher than the current consumption from accessing
the radio RAM, especially if the system side could otherwise have been powered down.
• The flash always has retention, and can only store parameters that are not written by the radio CPU.
As with accessing the system RAM, the radio CPU must ensure that the system side is powered up to
access the flash. The power consumption from the radio CPU accessing the flash is higher than the
current consumption from accessing the system RAM, but in most cases the difference is negligible
due to few accesses.
• The lowest peak-power consumption is obtained by putting all data structures in the radio RAM and
powering down the system side while the radio CPU is running. In some cases, the average power
consumption may be lower by putting data structures in the system RAM, because less copying is then
needed, and the system side can still be powered down for long periods (for instance, while the
receiver is in sync search).
A radio operation command causes the radio hardware to be accessed. Radio operation commands can
do operations such as transmitting or receiving a packet, setting up radio hardware registers, or doing
more complex, protocol-dependent operations. A radio operation command can normally be issued only
while the radio is idle.
An immediate command is a command to change or request status of the radio, or to manipulate TX or
RX data queues. An intermediate command can monitor status such as received signal strength. An
immediate command can be issued at any time, but the response is, in many cases, only of interest while
a radio operation is ongoing.
A direct command is an immediate command with no parameters, or in some cases, a direct command
has 1- or 2-byte parameters. A direct command is issued by sending a value to the CMDR register with
the format of Figure 23-4. The 16 most significant bits (MSBs) contain the command ID of the immediate
command to run. Bits 8 through 15 may contain an optional parameter if specified for the command.
23.3.2.2 Command Status
After a command is issued, the CMDSTA register is updated by the radio CPU, causing an RFCMDACK
interrupt to be sent back to the system CPU. This update occurs after the command finishes for immediate
and direct commands and after the command is scheduled for radio operation commands. No new
command may be issued until this interrupt is received. The CMDSTA register consists of 32 bits; the 8
LSBs give the result, while the upper 24 bits may be used for specific signaling in each command.
Figure 23-5 shows this format.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1585

RF Core HAL

www.ti.com

Figure 23-5. Format of CMDSTA Register
Return Byte 3
31
MSB

Return Byte 2
24

Return Byte 1
16

Result
8

0
LSB

In the result byte, bit 7 indicates whether an error occurred or not. The result byte of 0x00, meaning
pending, is produced automatically by the radio doorbell hardware when a command is issued, and the
other bits in the CMDSTA register also become 0, which is the value of CMDSTA before the
RF_CMD_ACK interrupt is raised.
Table 23-1 lists the values of the result byte in the CMDSTA register.
Table 23-1. Values of the Result Byte in the CMDSTA Register
Value

Name

Description

0x00

Pending

The command has not been parsed.

0x01

Done

Immediate command: The command finished successfully.
Radio operation command: The command was successfully submitted
for execution.

0x81

IllegalPointer

The pointer signaled in CMDR is not valid.

0x82

UnknownCommand

The command ID number in the command structure is unknown.

0x83

UnknownDirCommand

The command number for a direct command is unknown, or the
command is not a direct command.

0x85

ContextError

An immediate or direct command was issued in a context where it is
not supported.

SchedulingError

A radio operation command was attempted to be scheduled while
another operation was already running in the RF core. The new
command is rejected, while the command already running is not
impacted.

0x87

ParError

There were errors in the command parameters that are parsed on
submission. For radio operation commands, errors in parameters
parsed after start of the command are signaled by the command
ending, and an error is indicated in the status field of that command
structure.

0x88

QueueError

An operation on a data entry queue was attempted, but the operation
was not supported by the queue in its current state.

0x89

QueueBusy

An operation on a data entry was attempted while that entry was busy.

No Error

Error

0x86

In addition to the command status register, each radio operation command contains a status field (see
Table 23-8). This field may have values in the following categories.
• Idle: The command has not started.
• Pending: The command has been parsed, but the start trigger has not occurred.
• Active: The command is running.
• Suspended: The command has been active, and may become active again. The command is
supported only by certain IEEE 802.15.4 commands.
• Finished: The command is finished, and the system CPU is free to modify the command structure or
free memory.
• Skipped: The command was skipped and never executed.

1586

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

For common commands and when parsing any command before starting, refer to the status codes listed
in Table 23-2.
Table 23-2. Common Radio Operation Status Codes
Number

Name

Description

Operation Not Finished
0x0000

IDLE

Operation has not started.

0x0001

PENDING

Waiting for a start trigger.

0x0002

ACTIVE

Running an operation.

0x0003

SKIPPED

Operation skipped due to condition in another command.

Operation Finished Normally
0x0400

DONE_OK

Operation ended normally.

0x0401

DONE_COUNTDOWN

Counter reached zero.

0x0402

DONE_RXERR

Operation ended with CRC error.

0x0403

DONE_TIMEOUT

Operation ended with time-out.

0x0404

DONE_STOPPED

Operation stopped after CMD_STOP command.

0x0405

DONE_ABORT

Operation aborted by CMD_ABORT command.

Operation Finished With Error
0x0800

ERROR_PAST_START

The start trigger occurred in the past.

0x0801

ERROR_START_TRIG

Illegal start trigger parameter

0x0802

ERROR_CONDITION

Illegal condition for next operation

0x0803

ERROR_PAR

Error in a command specific parameter

0x0804

ERROR_POINTER

Invalid pointer to next operation

0x0805

ERROR_CMDID

The next operation has a command ID that is undefined or not a radio
operation command.

0x0807

ERROR_NO_SETUP

Operation using RX, TX or synthesizer attempted without
CMD_RADIO_SETUP.

0x0808

ERROR_NO_FS

Operation using RX or TX attempted without the synthesizer being
programmed or powered on.

0x0809

ERROR_SYNTH_PROG

Synthesizer programming failed.

0x080A

ERROR_TXUNF

Modem TX underflow observed.

0x080B

ERROR_RXOVF

Modem RX overflow observed.

0x080C

ERROR_NO_RX

Data requested from last RX when no such data exists.

When the system CPU prepares a command structure, the CPU must initialize the status field to Idle.
Commands may be set up in a loop. If so, the system CPU must not modify command structures until the
radio CPU becomes idle (the system CPU receives a LAST_COMMAND_DONE interrupt, even if the
status is finished or skipped [see Section 23.8.2.5]).
23.3.2.3 Interrupts
The radio CPU has 32 software interrupt sources that generate the RFCPE0 and RFCPE1 interrupts in
the system CPU. An interrupt flag register can indicate which software interrupt has been raised, and the
interrupts are enabled individually. In addition, the RFCMDACK interrupt is raised automatically when
CMDSTA is updated.
Some software-defined interrupts have a common meaning across all commands; the details of each of
the other interrupts are defined for each protocol that uses a particular interrupt. Some interrupts are used
in only one protocol, while others are used in several protocols. The interrupts are listed in the description
of the RFCPEIFG register (see Table 23-171).

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1587

RF Core HAL

www.ti.com

23.3.2.4 Passing Data
There are two basic ways to pass data transmitted or received over the air: directly or through a queue.
The most straight-forward way to pass data is to append it as part of the command parameters (directly or
through a pointer). The exact format depends on the command being run; normally there is a length field
and a data buffer for TX and a maximum length, received length (if variable length), and receive buffer for
RX.
For some operations, the number of packets received or transmitted (or which packet out of a few that will
actually be transmitted) cannot be known in advance. For such operations, use a concept of queues. An
operation can use one or more queues, for instance one RX and one TX queue for a combined RX/TX
operation, or several queues depending on information in the received packets. Any operation using
queues uses a common system for maintaining them, as explained in Section 23.3.2.7.
A radio operation command declares which data method is used.
23.3.2.5 Command Scheduling
The system CPU is responsible for scheduling the commands as required. When using low-power modes,
the system CPU must wake up a short time before the start of the next operation, using the RTC.
A radio operation command can be scheduled with a delayed start (see Section 23.3.2.5.1). If a command
is started with a delay, the radio CPU goes to idle mode until the command starts. The radio operation
command is considered to be running during this delay, and no other radio operation command can be
scheduled unless the pending command is first aborted or stopped.
The system CPU can schedule back-to-back radio operation commands by using the next operation
pointer in any radio operation command. This pointer can point to the next command to perform in the
chain, and by this method, complex operations can be made. Under some conditions (such as an error or
the expiration of a timer), the next command is not started. Instead, the operation ends or a number of
commands may be skipped (see Section 23.3.2.5.2). If a new command is scheduled while another
command is running, the system CPU must wait for the previous command or chain of commands to
finish. The IEEE 802.15.4 commands have exceptions for this rule.
When a radio operation command is finished, the radio CPU raises a COMMAND_DONE interrupt to the
system CPU. If a number of commands are chained as explained previously, the COMMAND_DONE
interrupt is raised after each command, while the LAST_COMMAND_DONE interrupt is raised after the
last command in the chain. For one, nonchained command, the LAST_COMMAND_DONE interrupt is also
raised after the command. When LAST_COMMAND_DONE is raised, COMMAND_DONE is always
raised at the same time. Before raising the COMMAND_DONE interrupt, the radio CPU updates the status
field of the command structure to a status that indicates that the command is finished. The radio CPU
does not access the command structure after raising the COMMAND_DONE interrupt.

1588

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

23.3.2.5.1 Triggers
Triggers can be used to set up a start time, or for other specific purposes in specific radio operation
commands. A common trigger byte definition exists, as defined in Table 23-3.
Table 23-3. Format of Trigger Definition Byte
Bit Index

Field

Description

0–3

triggerType

The type of trigger

bEnaCmd

0: No alternative trigger command.
1: CMD_TRIGGER can be used as an alternative trigger.

5–6

triggerNo

The trigger number of the CMD_TRIGGER command that triggers this action.

pastTrig

0: A trigger in the past is never triggered, or for start of commands, gives an error.
1: A trigger in the past is triggered as soon as possible.

Table 23-4 lists possible values for the triggerType field. Other values are reserved.
Table 23-4. Supported Trigger Types
Number

Name

Description

TRIG_NOW

Now (not applicable to end triggers)

TRIG_NEVER

Never (except possibly by CMD_TRIGGER if bEnaCmd = 1)

TRIG_ABSTIME

At absolute time, given by timer parameter

TRIG_REL_SUBMIT

At a time relative to the time the command was submitted

TRIG_REL_START

At a time relative to start of this command (not allowed for start triggers)

TRIG_REL_PREVSTART

At a time relative to the start of the previous command

TRIG_REL_FIRSTSTART

At a time relative to the start of the first command of the chain

TRIG_REL_PREVEND

At a time relative to the end of the previous command

TRIG_REL_EVT1

At a time relative to event 1 of the previous command

TRIG_REL_EVT2

At a time relative to event 2 of the previous command

TRIG_EXTERNAL

On an external trigger input to the RAT

A 32-bit time parameter is used together with all triggers except for TRIG_NOW and TRIG_NEVER.
Absolute timing uses the value of the 32-bit RAT. Relative timing uses the number of RAT ticks. The
external trigger uses an identifier of source and edge, as defined in Table 23-5.
Table 23-5. Fields of Time Parameter
for External Event Trigger
Bit Index

Field

Description

0–1

Reserved

2–3

Input mode:
00: Rising edge
01: Falling edge
10: Both edges
11: Reserved

inputMode

4–7
8–12

Reserved
source

13–31

22: RFC_GPI0
23: RFC_GPI1
Others: Reserved
Reserved

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1589

RF Core HAL

www.ti.com

Relative timing can be relative to the time of submitting the command chain, the start of the command, the
start of the previous or first command, or to certain observed events inside the command, to be defined for
each command. The following rules apply:
• For the first command in a chain, if the start trigger is any of the types 5 to 9, the start is immediate. If
another trigger referenced in the first command in a chain is any of the types 5 to 9, the trigger time is
relative to the time the command was submitted.
• If the start trigger of a command is TRIG_REL_START, an error is produced.
• If the start trigger of a command is TRIG_NEVER and bEnaCmd is 0, an error is produced.
• Some radio operation commands define events 1 and 2. These are context-dependent events that can
be observed by the radio CPU. See the description of each command for a definition in that context. If
undefined, these events are the time of the start of the command.
If bEnaCmd is 1, the action may also be triggered with a command (CMD_TRIGGER command, see
Section 23.3.4.5). The triggerNo parameter identifies the trigger number of this command.
If a trigger occurs in the past when evaluated, the behavior depends on the pastTrig bit. If this bit is 0, the
trigger does not occur, or for start triggers, an error is produced. If the pastTrig bit is 1, the trigger occurs
as soon as possible. If the pastTrig bit is 1 for start triggers, timing relative to the start of the command is
relative to the programmed start time, not the actual start time.
For an external trigger, the radio CPU sets the RAT to use the selected input event as a one-capture
trigger; the CPU then uses this capture interrupt to trigger the action. If the event occurs before the setup
occurs, the event is not captured, and the pastTrig bit is ignored.
23.3.2.5.2 Conditional Execution
The execution of a command may be conditional on the result of the previous command. For each
command, three results are possible:
• TRUE
• FALSE
• ABORT
The criteria are defined for each command. If not defined, the result is TRUE unless the command ended
with an error, in which case the result is ABORT.
Each command structure contains a condition for running the next command. The format of the condition
byte is given in Table 23-6. If the rule is COND_SKIP_ON_FALSE or COND_SKIP_ON_TRUE, the
number of commands to skip is signaled in the nSkip field. If the number of skips is zero, rerun the same
command. If the number of skips is one, run the next command in the chain. If the number of skips is two,
run the command after the next, and so forth. If the rule is COND_NEVER and no previous commands
use skipping, the next command pointer is ignored and may be NULL.
Table 23-6. Format of Condition Byte
Bit Index

Field Name

Description

0–3

rule

Rule for how to proceed, as defined in Table 23-7

4–7

nSkip

Number of skips + 1 if the rule involves skipping
0: Same, 1: next, 2: skip next, ...

1590Radio

RF Core HAL

www.ti.com

Table 23-7. Condition Rules
Number

Name

Description

COND_ALWAYS

Always run next command (except in case of ABORT).

COND_NEVER

Never run next command (next command pointer can still be used for
skip).

COND_STOP_ON_FALSE

Run next command if this command returned TRUE, stop if it returned
FALSE.

COND_STOP_ON_TRUE

Stop if this command returned TRUE, run next command if it returned
FALSE.

COND_SKIP_ON_FALSE

Run next command if this command returned TRUE, skip a number of
commands if it returned FALSE.

COND_SKIP_ON_TRUE

Skip a number of commands if this command returned TRUE, run next
command if it returned FALSE.

If execution is stopped, the radio CPU goes back to idle and no further commands are run until a new
command is entered through the CMDR register. The LAST_COMMAND_DONE interrupt is raised.
If a command ends with the ABORT result, the execution ends regardless of the condition. The
LAST_COMMAND_DONE interrupt is raised. An example of criterion for the ABORT result is that a
CMD_ABORT command is issued.
23.3.2.5.3 Handling Before Start of Command
For all radio operation commands, the start trigger and condition code are checked before parsing the rest
of the command. If the start trigger has an illegal trigger type (including TRIG_REL_START, which is not
allowed for start triggers, and TRIG_NEVER in combination with no command trigger), the radio CPU sets
the status field to ERROR_START_TRIG. If the condition field has an illegal value, the radio CPU sets the
status field to ERROR_CONDITION. If the start trigger occurs in the past and startTrigger.pastTrig is 0,
the radio CPU sets the status field to ERROR_PAST_START.
23.3.2.6 Command Data Structures
The data structures are listed in tables throughout this chapter. The Byte Index is the offset from the
pointer to that structure. Multibyte fields are little-endian, and 16-bit halfword or 32-bit word alignment as
given by the field size is required. For bit numbering, 0 is the LSB. The R/W column is used as follows:
R: The system CPU can read a result back; the radio CPU does not read the field.
W: The system CPU writes a value, the radio CPU reads it and does not modify it.
R/W: The system CPU writes an initial value, the radio CPU may modify it.
For data structures that are a specialization of another data structure, the fields from the parent structure
are not repeated, but the Byte Index column reflects their presence.
The only mandatory field for all commands is the command ID number, which is a 16-bit number sent as
the first 2 bytes of the command structure.
Some immediate commands have additional fields, which are defined for each command. The radio
operation commands have additional mandatory fields as defined in Table 23-8.
All command fields marked as “Reserved” should be written to 0.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1591

RF Core HAL

www.ti.com

23.3.2.6.1 Radio Operation Command Structure
Table 23-8 shows the command structure for radio operation commands. Some commands have
additional fields appended after this.
Table 23-8. Radio Operation Command Format
Byte Index

Field Name

0–1

commandNo

Bits

Bit Field
Name

Type

Description

The command ID number

2–3

status

R/W

An integer telling the status of the command. This
value is updated by the radio CPU during
operation and may be read by the system CPU at
any time.

4–7

pNextOp

Pointer to the next operation to run after this
operation is done

8–11

startTime

Absolute or relative start time (depending on the
value of the startTrigger field)

startTrigger

condition

Identification of the trigger that starts the
operation
W

Condition for running the next operation

23.3.2.7 Data Entry Structures
A data entry must belong to a queue. The queues are set up as part of the command structure of a radio
operation command.
Operations on queues available as commands are described in Section 23.3.5.
23.3.2.7.1 Data Entry Queue
Any command that uses a queue contains a pointer to a data entry queue structure, as given in
Table 23-9. The system CPU allocates and initializes this queue structure.
Table 23-9. Data Entry Queue Structure
Byte Index

1592

Field Name

Bits

Bit Field
Name

Type

Description

0–3

pCurrEntry

R/W

Pointer to the data entry currently in use by the
radio CPU (or next in line to be used if the radio is
not using the queue). NULL means that no buffer
is currently in the queue.

4–7

pLastEntry

R/W

Pointer to the last entry entered in this queue. If
pCurrEntry is nonNULL and pLastEntry is NULL,
additional entries may not be appended.

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

23.3.2.7.2 Data Entry
A data entry queue contains data entries of the type shown in Table 23-10. These entries are organized in
a linked list. The first entry of the queue is pointed to by the pCurrEntry field of the queue structure (see
Table 23-9). Each pNextEntry field points to the next entry. The pLastEntry field of the queue structure
points to the last entry in the queue.
Table 23-10. General Data Entry Structure
Byte Index

Field Name

0–3
4

Bits

Type

Description

pNextEntry

R/W

Pointer to the next entry in the queue, NULL if this
is the last entry

status

R/W

Indicates status of entry, including whether it is
free to receive a write from the system CPU

Type of data entry structure:
0: General data entry
1: Multielement RX entry
2: Pointer entry

0–1

Bit Field
Name

type

2–3

lenSz

Size of length word in start of each RX entry
element:
0: No length indicator
1: 1-byte length indicator
2: 2-byte length indicator
3: Reserved

4–7

irqIntv

RESERVED

config

6–7

length

Length of data field, or for pointer entries, of the
data buffer. For TX entries, this corresponds to
one entry element (packet). For RX entries, this
gives the total available storage space.

8–(7+n)

data

R/W

Array of data to be received or transmitted
(n = length)

The status field may take the following values:
• 0: Pending: The entry is not yet in use by the radio CPU. This is the status to write by the system CPU
before submitting the entry.
• 1: Active: The entry is the entry in the queue currently open for writing (RX) or reading (TX) by the
radio CPU.
• 2: Busy: An ongoing radio operation is writing or reading an unfinished packet. Certain operations are
not allowed while an entry is in this state (see Section 23.3.5).
• 3: Finished: The radio CPU is finished writing data into this entry, and is free for the system CPU to
reuse or free memory (if dynamically allocated).
For data entries, the system CPU sets up the required data structure, either in system RAM or in the
available part of the radio RAM. If the data structure is dynamically allocated, the system CPU frees the
memory after use.
In an entry is being used for received data, the radio CPU may start the entry element with a length
indicator. If config.lenSz is 00, no such indicator is written. This option must be used only if the length of
the received packet can be determined by other means. If config.lenSz is 01, 1 byte indicates the number
of bytes following the length byte. This option may be used only if no element of more than 255 bytes is
written to the entry. If config.lenSz is 10, a 16-bit word indicates the number of bytes following the length
word.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1593

RF Core HAL

www.ti.com

23.3.2.7.3 Pointer Entry
A pointer entry is an entry where the data are not contained in the entry itself, but the entry holds a pointer
to the buffer. Such an entry is indicated by setting config.type to 2. The pointer replaces the data field, as
shown in Table 23-11.
Table 23-11. Pointer Field in Pointer Entry Structure
Byte Index

Field Name

8–11

pData

Bits

Bit Field Name

Type

Description

Pointer to data buffer of size length
bytes

The data is read from or stored in the buffer given by pData. The size of this buffer is given by length, just
as is the size of the data field in a general data entry.
23.3.2.7.4 RX Multielement Entry
For an RX entry, a special variant of the structure in Table 23-10 may be used. With this type, several
entry elements can be contained in the same entry. Each entry element typically corresponds to one
packet received over the air, but may contain additional fields. This type is selected by setting config.type
to 1; if config.type is 0 or 2, the radio CPU writes only one entry element into each data entry. In the
multielement entry, the data field is composed as shown in Table 23-12 (the indexes are relative to the
entire entry structure).
Table 23-12. Fields in RX Multielement Structure
Byte Index

Field Name

8–9

Bits

Bit Field
Name

Type

Description

numElements

Number of entry elements
committed in the entry

10–11

nextIndex

Index to the byte after the last byte
of the last entry element committed
by the radio CPU

12–(7+n)

RXData

Data received. Exact format
depends on operation being run.
Each entry element may start with
a length byte or word.

An RX entry that is in the ACTIVE or BUSY state may be read by the system CPU, but cannot be freed or
written to, except for data already committed by the radio CPU (in other words, finished). The system CPU
may read and modify the data in the RXData buffer up to nextIndex-1, while these bytes are not modified
by the radio CPU.
When the radio CPU changes the status of the entry from Pending to Busy, it initializes numElements and
nextIndex to 0.
Each entry element may start with a length indicator as specified by config.lenSz. If this value is 2 so that
a 16-bit length word is used, the length word may not be halfword aligned, and must be read byte by byte.
Two (or more) RX queue entries may be set up in a ring buffer fashion. If so, pCurrEntry of the queue
must be initialized to one of the RX queue entries when setting up the radio operation command, and
pLastEntry must be NULL. pNextEntry of each RX queue entry must be set up to point to the other entry.
Whenever a packet is received, an RX interrupt is raised to the system CPU. The system CPU may then
read the corresponding entry element. If the status of the RX queue entry from which the system CPU is
reading has changed to Finished, the radio CPU writes its next entry element to the other entry. After
processing the received data in the first entry, the system CPU must reset the status field of that entry to
Pending. If this is not done before the radio CPU finishes with the other entry, the radio operation
assumes it is out of buffer space.

1594

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

23.3.2.7.5 Partial Read RX Entry
Proprietary mode supports an RX entry where the data can be read before the entire packet is received
over the air, which can be used for the following purposes:
• When data must be read before the entire packet is received
• When the length of the packet is not known in the beginning of the packet
• When the length of the packet is too long for the entire payload to be kept in memory simultaneously
To support this, a special variant of the structure in Table 23-10 is used. As for the multielement entry,
several entry elements may be contained in the same entry. Each entry element corresponds to one
packet received over the air, or part of it. The element may also contain additional fields. This type is
selected by setting config.type to 3. In the multielement entry, the data field is composed as shown in
Table 23-13 (the indexes are relative to the entire entry structure).
Table 23-13. Fields in a Partial Read RX Entry
Byte Index

8–9

10–11

12–(7+n)

Byte Field Name

Bits

Bit Field Name Type

Description

0–12

numElements

Number of entry elements
committed in the entry

bEntryOpen

The entry contains an element that
is still open for appending data.

bFirstCont

The first element is a continuation
of the last packet from the previous
entry.

bLastCont

The packet in the last element
continues in the next entry.

Index to the byte after the last byte
of the last entry element committed
by the radio CPU

Data received. Exact format
depends on operation being run.
Each entry element may start with
a length byte or word.

pktStatus

nextIndex

RXData

The entry is updated as follows:
• The nextIndex field is updated as new bytes are written to the buffer.
• While a packet is being received, the radio CPU sets pktStatus.bEntryOpen to 1.
When an entry element is finished, either because the packet ended or because the element reached the
end of the entry, pktStatus.bEntryOpen is set to 0 by the radio CPU, and pktStatus.numElements is
incremented. If the packet continues in the next entry, the radio CPU sets pktStatus.bLastCont to 1. In this
case, the pktStatus.bFirstCont bit of the next entry is also set to 1 by the radio CPU. If no next entry is
available, the status is set to Unfinished, otherwise it is set to Finished.
The length field specified in the beginning of an entry element (depending on config.lenSz) gives the
length of that entry element within the entry, not the entire packet. If the length is not known when the
entry is opened, the length field is written to the remaining length of the entry and updated by the radio
CPU before the entry is finished.
For a partial read RX entry, the radio CPU generates an Rx_Data_Written interrupt to the system CPU
whenever 1 or more bytes are written to the entry. In addition, the radio CPU generates an
Rx_N_Data_Written interrupt when k bytes have been written since the last interrupt or the start of the
entry element, where k is given by config.irqIntv.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1595

RF Core HAL

www.ti.com

23.3.2.8 External Signaling
The radio CPU controls the signals CPEGPO0 and CPEGPO1. For control of an external front end,
CPEGPO0 is high when the LNA must be enabled; otherwise, CPEGPO0 is low. CPEGPO1 is high when
the PA must be enabled; otherwise, CPEGPO1 is low. The radio CPU also controls the signal CPEGPO2
to go high when synthesizer calibration starts, and low when the calibration is done. This control can be
used for debugging.
Two of the output signals from the RAT have automatic configuration that may be used for observation.
The signal RATGPO0 goes high when transmission of a packet is initiated and low when transmission is
done. RATGPO0 may be observed for accurate timing of packet transmission, because the same signal is
used internally. RATGPO0 is very similar to CPEGPO1, but it goes high some microseconds earlier, and
the timing is more accurate compared to the first transmitted symbol out of the modem. However,
CPEGPO1 is recommended for control of external PA to avoid turning it on too early. The signal
RATGPO1 may be configured to go high when sync is found in the receiver, and low when the packet is
received or reception aborted (this does not work for the IEEE 802.15.4 receiver command). RATGPO1 is
configured with the radio firmware configuration parameter gpoContol. The other outputs from the RAT
may be configured to generate events as required, using CMD_SET_RAT_OUTPUT.
By default, the radio CPU maps CPEGPO0 to the signal RFC_GPO0, CPEGPO1 to the signal
RFC_GPO1, CPEGPO2 to the signal RFC_GPO2, and RATGPO0 to the signal RFC_GPO3 at boot time.
This mapping can be modified by writing to the RFC_DBELL:SYSGPOCTL register.
The RFC_GPOx signals can be mapped to output pins using the system I/O controller.

23.3.3 Command Definitions
There is a set of commands independent of the current RF protocol. These commands are related to the
low-level operations of the radio.
23.3.3.1 Protocol-Independent Radio Operation Commands
For radio operation commands listed here, the operation ends due to one of the causes listed in
Table 23-14, or by additional statuses listed for each command. After the operation has ended, the status
field of the command structure (2 status bytes listed in Table 23-8) indicates why the operation ended. In
each case, it is indicated if the result is TRUE, FALSE, or ABORT (see Section 23.3.2.5.2). This result
indicates whether to start the next command (if any) indicated in pNextOp, or to return to an IDLE state.
Table 23-14. End of Radio Operation Commands

1596

Condition

Status Code

Result

Finished operation

DONE_OK

TRUE

Received CMD_STOP while waiting for start trigger

DONE_STOPPED

FALSE

Received CMD_ABORT

DONE_ABORT

ABORT

The start trigger occurred in the past with startTrigger.pastTrig = 0

ERROR_PAST_START

ABORT

Illegal start trigger parameter

ERROR_START_TRIG

ABORT

Illegal condition for next operation

ERROR_CONDITION

ABORT

Observed illegal parameter

ERROR_PAR

ABORT

Invalid pointer to next operation

ERROR_POINTER

ABORT

Next operation has a command ID that is undefined or not a radio
operation command

ERROR_CMDID

ABORT

Operation using RX, TX, or synthesizer attempted without
CMD_RADIO_SETUP

ERROR_NO_SETUP

ABORT

Operation using RX or TX attempted without the synthesizer being
programmed

ERROR_NO_FS

ABORT

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

23.3.3.1.1 CMD_NOP: No Operation Command
Command ID number: 0x0801
CMD_NOP is a radio operation command that only takes the mandatory arguments listed in Table 23-8.
The command only waits for the start trigger, and then ends. The command can be used to test the
communication between the system CPU and the radio CPU or to insert a wait.
23.3.3.1.2 CMD_RADIO_SETUP: Set Up Radio Settings Command
Command ID number: 0x0802
CMD_RADIO_SETUP is a radio operation command. In addition to the parameters listed in Table 23-8,
the command structure contains the fields listed in Table 23-15.
Table 23-15. CMD_RADIO_SETUP Command Format
Byte Index Field

16–17

Bit Index

Bit Field name

mode

loDivider

0–2

frontEndMode

biasMode

Type

Description

This is the main mode to use.
0x00: Bluetooth low energy
0x01: IEEE 802.15.4
0x02: 2-Mbps GFSK
0x05: 5-Mbps coded 8-FSK
0xFF: Keep existing mode; update overrides
only.

CC13x0:
LO divider setting to use. Supported values: 0
(equivalent to 2), 2, 5, 6, 10, 12, 15, and 30.
Value of 0 or 2 only supported for CC1350.
CC26x0:
Reserved
0x00: Differential mode
0x01: Single-ended mode RFP
0x02: Single-ended mode RFN
0x05: Single-ended mode RFP with external
front-end control on RF pins (RFN and RXTX)
0x06: Single-ended mode RFN with external
front-end control on RF pins (RFP and RXTX)
Others: Reserved

0: Internal bias
1: External bias

config

4-9

analogCfgMode

0x00: Write analog configuration. Required first
time after boot and when changing frequency
band or front-end configuration
0x2D: Keep analog configuration. May be used
after standby or when changing mode with the
same frequency band and front-end
configuration.
Others: Reserved

bNoFsPowerup

0: Power up frequency synthesizer.
1: Do not power up frequency synthesizer.

11–15

Reserved

18–19

txPower

Output power setting; use value from SmartRF
Studio. For more details, see Section 23.3.4.16.

20–23

pRegOverride

Pointer to a list of hardware and configuration
registers to override. If NULL, no override is
used.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1597

RF Core HAL

www.ti.com

On start, the radio CPU sets up parameters for the operational mode given by mode.radioMode, with the
modifications given in pRegOverride, a pointer to a structure containing override values for certain
hardware registers, radio configuration controlled by the radio CPU, and protocol-related variables. If
pRegOverride is NULL, no registers are overridden. The override value structure is a string of 32-bit
entries provided by TI or produced by SmartRF Studio.
Running CMD_RADIO_SETUP or another radio setup command is mandatory before using any command
that uses the receiver, transmitter, or frequency synthesizer. If the RF core is reset, CMD_RADIO_SETUP
must be rerun.
When CMD_RADIO_SETUP is executing, trim values are read from FCFG1 unless they have been
provided elsewhere. If these values are read from FCFG1, the following limitations apply while
CMD_RADIO_SETUP is executing:
• The VIMS module must be powered, allowing flash reads.
• A SCLK_HF source switch must not occur, as Flash read access is momentarily disabled while the
switch is ongoing.
If either of the preceding limitations is violated, the internal system bus might end up in a nonresponsive
state. A system reset is required to exit this state. To avoid reading FCFG1 while running
CMD_RADIO_SETUP, the values may be read in advance using CMD_READ_TRIM and provided to the
radio using CMD_SET_TRIM. This is handled automatically by the TI provided RF driver.
The txPower parameter is stored and applied every time transmission of a packet starts to set an output
power with temperature compensation. This setting can be changed later with the command
CMD_SET_TX_POWER (see Section 23.3.4.16).
Table 23-16. Format of a Hardware Register Override Entry
Bit Index

Bit Field Name

Description

0–1

entryType

00: Hardware register
01: Array initiator; see Table 23-17
10: ADI register; see Table 23-18, or MCE/RFE override
11: Firmware-defined parameter; see Table 23-19

2–15

hwAddr

Bits 2–15 of the address to the hardware register. Bits 0–1 of the address are 0.

16–31

value

The value to write to the register

Table 23-17. Format of Array Initiator
Bit Index

Bit Field Name

Description

0–1

entryType

01: Array initiator

2–15

startAddr

First address or index to write to:
Hardware registers: Bits 2–15 of the address (bits 0 and 1 are 0)
ADI registers: ADI bus address, half-byte indicator in bit 6, ADI selector in bit 7
Firmware-defined parameters: Byte Index

16–29

length

Number of entries

arrayType

Type of array:
00: Hardware registers with 16-bit values
01: Hardware registers with 32-bit values
10: ADI registers
11: Firmware-defined parameters

30–31

1598Radio

RF Core HAL

www.ti.com

Table 23-18. Format of an ADI Register Override Entry
Bit Index

Bit Field Name

Description

0–1

entryType

10: ADI register

2–9

adiValue2

Optional second value to write

10–15

adiAddr2

Optional second ADI bus address

16–23

adiValue

Value to write to register

24–29

adiAddr

ADI bus address

bHalfSize

0: Use full-size writes
1: Use half-size writes, causing read-modify-write functionality

adiNo

0: Write to ADI 0 (RF)
1: Write to ADI 1 (synthesizer)

Table 23-19. Format of a Firmware-Defined Parameter Override Entry
Bit Index

Bit Field Name

Description

0–1

entryType

11: Firmware-defined parameter

2–3

entrySubType

00: Firmware-defined parameter
01: MCE/RFE override mode (must be in first entry); see Table 23-20
10: Reserved
11: End of override list

4–14

fwAddr

Byte index into parameter structure

bByte

0: 16-bit value
1: 8-bit value

16–31

value

The value to write to the parameter

Radio1599

RF Core HAL

www.ti.com

Table 23-20. Format of an MCE/RFE Override Mode Entry
Bit Index

Bit Field Name

Description

0–1

entryType

11: Firmware-defined parameter

2–3

entrySubType

01: MCE/RFE override mode

4–7

Reserved

bMceUseRam

0: Run MCE from ROM
1: Run MCE from RAM

9–11

mceRomBank

MCE ROM bank to run from

bRfeUseRam

0: Run RFE from ROM
1: Run RFE from RAM

13–15

rfeRomBank

RFE ROM bank to run from

16–23

mceMode

Mode to send to MCE

24–31

rfeMode

Mode to send to RFE

Table 23-21. Format of a Center Frequency Entry
Bit Index

Bit Field Name

Description

0–1

entryType

11: Firmware-defined parameter

2–3

entrySubType

10: Special configuration

4–7

specialType

0001: Center frequency entry

Reserved

bAutoTxIf

If 1, set TX IF to RX IF.

bApplyRx

If 1, use invRfFreq to recalculate RX IF.

bApplyTx

If 1, use invRfFreq to recalculate TX shape.

12–31

invRfFreq

Value where fRFMHz is center frequency in MHz:
(12 × 24 × 220) / (fRFMHz × loDivider)

Table 23-22. Format of an End of List Entry
Bit Index

Bit Field Name

Description

0–1

entryType

11: Firmware-defined parameter

2–3

entrySubType

11: End of list segment

4–7

nextEntryRegion

0x0: End of list
0x1: SRAM. Base = 0x2000 0000
0x2: RF core RAM. Base = 0x2100 0000
0x3: Flash. Base = 0xA000 0000
0x4: RF core ROM. Base = 0x0000 0000
0x5: BROM. Base = 0x10000 0002
0x6. GPRAM. Base = 0x11000 0002
0x7: Registers. Base = 0x40000 0002
0x8: FCFG. Base = 0x50000 0002
0xF: End of list
Others: Reserved

8–31

addrOffset

Address offset for next list part. Next address is:
Base + (addrOffset × 4)

(1)

1600

Radio

(1)

Not recommended. Included for completeness; works only if pointer range checks are disabled.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

For hardware registers, bits 2–15 give the address of the hardware register to access, see Table 23-16.
The register is written with a 32-bit write operation, but the 16 MSBs are always written as 0, while the 16
LSBs are as given by value. To write a full 32-bit hardware register, use an array operation of length 1.
An array initiator signals that the next words must be written to consecutive addresses (see Table 23-17).
The type of accesses is decided by array type:
• 00 gives 32-bit writes to 16-bit hardware registers. The first register address is 0x4004 0000 +
(startAddr << 2). Then length addresses are written. Each value is taken from the next 16-bit halfword
of the override entry, and the register address is incremented by 4 each time a write occurs. If length is
odd, padding is assumed so that the first entry after the array is 32-bit word-aligned.
• 01 gives 32-bit writes to hardware registers. The first register address is
0x4004 0000 + (startAddr << 2). Then length addresses are written. Each 32-bit value is taken from
the next 32-bit word of the override entry, and the register address is incremented by 4 each time a
write occurs.
• 10 gives byte writes to ADI registers. The first ADI bus address is given by bits 0–5 of startAddr. If bit 6
is set to 1, half-byte writes are used, otherwise full-byte writes (the LSB is ignored by the ADI in this
case). Bit 7 selects to which ADI to write. Each value written on the ADI bus is taken from the next byte
of the override entry, and the ADI register address is incremented by 1 in case of half-byte writes or by
2 in case of full-byte writes each time a write occurs. If length is not divisible by 4, padding is assumed
so that the first entry after the array is 32-bit word-aligned.
• 11 gives writes to firmware-defined parameters. The first index into the configuration values is given by
startAddr/4, and length bytes are copied from the override entry. If length is not divisible by 4, padding
is assumed so that the first entry after the array is 32-bit word-aligned.
For ADI registers, adiValue gives the value to write and adiAddr gives the address on the ADI bus (see
Table 23-18). The ADI to write is selected through adiNo. If bHalfSize is 1, the write size bit on the ADI
interface is set, causing the value to be masked half size; otherwise, it is a full-size write, and the LSB of
the address is ignored. If adiAddr2 is nonzero, the value given by adiValue2 is written to the ADI bus
address given by adiAddr2; otherwise, these two fields are ignored (if ADI address 0 is to be written, it
must be done through adiAddr/adiValue). In this case, bHalfSize and adiNo apply to both writes.
For radio firmware-defined parameters (see Table 23-19), fwAddr gives a Byte Index into an array of
configuration values held in the radio. If bByte = 1, only the least significant byte (LSByte) of value is
written to the addressed byte. If bByte = 0, all 16 bits are written to the 16-bit halfword at the given byte
address, which must be even in this case. The selected value is set to the value specified in the value part
of the override entry.
The first entry in the override list may contain an override of the MCE and RFE modes, as given by
Table 23-20. If so, the MCE is set to run from RAM if bMceUseRam is 1 and bMceCopyRam is 0;
otherwise the MCE runs from the ROM bank given by mceRomBank. The value of MDMCMDPAR0 that is
set when the CPE runs the MCE configuration command is given by mceMode. Similarly, the RFE is set
to run from RAM if bRfeUseRam is 1 and bRfeCopyRam is 0; otherwise the RFE runs from the ROM bank
given by rfeRomBank. The value of RFECMDPAR0 set when the CPE runs the RFE configuration
command is given by rfeMode.
If the pointer in pRegOverride is invalid, any override entry is invalid. If the length of an array is too large
or zero, the operation ends with the status ERROR_PAR. If config.bNoFsPowerup = 0 and powering up
the synthesizer fails, the command ends with ERROR_SYNTH_PROG as the status.
If CMD_ABORT or CMD_STOP is received while waiting for the start trigger, the operation ends without
any setup. If CMD_STOP is received after the start trigger, setup proceeds until finished. If CMD_ABORT
is received after the start trigger, the setup process is aborted. This leaves the registers in an incomplete
state, so another CMD_RADIO_SETUP command must be issued before using the radio.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1601

RF Core HAL

www.ti.com

23.3.3.1.3 CMD_FS_POWERUP: Power Up Frequency Synthesizer
Command ID number: 0x080C
CMD_FS_POWERUP is a radio operation command. In addition to the parameters listed in Table 23-8,
the command structure contains the fields listed in Table 23-23.
On start, the radio CPU powers up the frequency synthesizer and applies the register modifications given
in pRegOverride. If pRegOverride is NULL, no registers are overridden. The format of the override
structure is the same as the format for CMD_RADIO_SETUP (see Section 23.3.3.1.2). Only overrides
applicable to the synthesizer hardware are applied.
Running CMD_FS_POWERUP is mandatory before using any command that uses the frequency
synthesizer (and thus, the transmitter or receiver), unless the synthesizer has been powered up as part of
the radio setup. The radio must be set up using CMD_RADIO_SETUP or another setup command before
CMD_FS_POWERUP.
If the pointer in pRegOverride is invalid, the address or index is invalid, the length of an array is zero or is
too large. If another parameter in an entry is not permitted, the operation ends with the status
ERROR_PAR. If powering up the synthesizer fails, the command ends with ERROR_SYNTH_PROG as
the status. When otherwise finished, the command ends with DONE_OK as the status.
Table 23-23. CMD_FS_POWERUP Command Format
Byte Index Field Name

Bit Index

Bit Field
Name

Type

14–15
16–19

Description
Reserved

pRegOverride

Pointer to a list of hardware and
configuration registers to override. If NULL,
no override is used.

23.3.3.1.4 CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
Command ID number: 0x080D
CMD_FS_POWERDOWN is a radio operation command that only takes the mandatory arguments listed
in Table 23-8. The command waits for the start trigger and then powers down the synthesizer. The act of
powering down not only stops the synthesizer, as is done with CMD_FS_OFF (see Section 23.3.3.1.6) or
at the end of certain other radio operation commands, but it also switches off analog modules.
After running CMD_FS_POWERDOWN, the synthesizer must be powered up again using
CMD_FS_POWERUP, or another command that powers up the synthesizer before it is used.
CMD_FS_POWERDOWN must always be run before the radio is powered down (for instance, when the
device is going into low-power modes).
When finished, the CMD_FS_POWERDOWN command ends with a DONE_OK status.

1602

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

23.3.3.1.5 CMD_FS: Frequency Synthesizer Controls Command
Command ID number: 0x0803
CMD_FS is a radio operation command. In addition to the parameters listed in Table 23-8, the command
structure contains the fields listed in Table 23-24, and can program the synthesizer to a specific
frequency.
The frequency to use is given by frequency and fractFreq, and must be as close as possible to
(frequency + fractFreq / 65536) MHz.
The synthesizer is set up in RX mode or TX mode, depending on synthConf.bTxMode. This mode may be
changed by radio operation commands when setting up RX or TX. If synthConf.refFreq is nonzero, a
reference frequency of 24 MHz / synthConf.refFreq is used instead of the default frequency.
If the synthesizer is programmed and reports loss of lock after having been in lock, the radio CPU raises
the Synth_No_Lock interrupt. The synthesizer keeps running, but the system CPU may use this
information to stop and restart the radio. The Synth_No_Lock interrupt is not raised more than once for
each time the synthesizer is programmed. The interrupt may also occur for commands with implicitfrequency programming.
If the CMD_FS command is called with an illegal frequency or divider setting, the command ends with
ERROR_PAR as the status. If the command is called without the radio being configured, it ends with
ERROR_NO_SETUP as the status. If the command is called without the synthesizer being powered up, it
ends with ERROR_NO_FS as status.
Table 23-24. CMD_FS Command Format
Byte Index Field Name

Bit Index

Bit Field Name

Type

Description

14–15

frequency

The frequency in MHz to which the synthesizer
should be tuned

16–17

fractFreq

Fractional part of the frequency to which the
synthesizer should be tuned

0: Start synthesizer in RX mode.
1: Start synthesizer in TX mode.

synthConf

bTxMode

1–6

refFreq

CC13x0:
0: Use default reference frequency.
Others: Use reference frequency 24 MHz/refFreq.
CC26x0:
Reserved

Reserved

19–23

23.3.3.1.6 CMD_FS_OFF: Turn Off Frequency Synthesizer
Command ID number: 0x0804
CMD_FS_OFF is a radio operation command that only takes the mandatory arguments listed in
Table 23-8, and turns off the frequency synthesizer if it has been started by CMD_FS or left on by a radio
operation command that does not turn off the synthesizer.
When the command is started, the synthesizer outputs are disabled and the state machine is reset. The
analog parts are still powered; CMD_FS_POWERDOWN (see Section 23.3.3.1.4) can power down the
synthesizer to further reduce the current consumption.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1603

RF Core HAL

www.ti.com

23.3.3.1.7 CMD_RX_TEST: Receiver Test Command
Command ID number: 0x0807
CMD_RX_TEST is a radio operation command used to set the receiver in infinite RX mode for test
purposes.
The sync word programmed in the receiver is given in the LSBs of syncWord. If config.bNoSync is 1, the
correlation thresholds for sync search are set to the maximum value to avoid getting sync. The thresholds
are restored after the command ends. If config.bEnaFifo is 0, the modem FIFO is not enabled so that
received bits are not stored. If config.bEnaFifo is 1, the modem FIFO is enabled, but data is not read out;
this must then be done by the application. After sync and before the end trigger, the radio CPU does not
access the modem registers, so that accesses directly from the system CPU to the FIFO registers can be
safely done.
If pktConfig.bFsOn is 1, the synthesizer is turned off (corresponding to CMD_FS_OFF; see
Section 23.3.3.1.6) after the operation is done; otherwise the synthesizer is left on.
A trigger to end the operation is set up by endTrigger and endTime (see Section 23.3.2.5.1). If the trigger
that is defined by this parameter occurs, the radio operation ends.
The operation ends by one of the causes listed in Table 23-14.
The command structure for CMD_RX_TEST contains the fields listed in Table 23-25.
Table 23-25. CMD_RX_TEST Command Format
Byte
Index

1604

Byte Field
Name

Bits

Bit Field Name

Type

Description

Reserved

Set to 0

bFsOff

0: Keep frequency synthesizer on after command.
1: Turn frequency synthesizer off after command.

bNoSync

0: Run sync search as normal for the configured mode.
1: Write correlation thresholds to the maximum value to
avoid getting sync.

config

endTrigger

Trigger classifier for ending the operation

16–19

syncWord

Sync word to use for receiver

20–23

endTime

Time to end the operation

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

23.3.3.1.8 CMD_TX_TEST: Transmitter Test Command
Command ID number: 0x0808
CMD_TX_TEST is a radio operation command used to set the receiver in infinite TX mode and transmit
either a CW or modulated data for test purposes.
When the command starts, the radio CPU starts the transmitter. The radio must be configured with the
CMD_RADIO_SETUP command and the radio synthesizer must be started and in TX mode with the
CMD_FS radio command before CMD_TX_TEST is issued. The radio transmits a preamble and a sync
word of the size given by the current radio configuration, specified using CMD_RADIO_SETUP. The sync
word is given in the LSBs of syncWord. The payload after the sync word consists of the 16-bit word
TXWord, repeated indefinitely. This word may be run through whitening, with the options given in
config.whitenMode, which can take the following values:
• 0: No whitening is used. This is useful for testing with a repeated pattern, but gives spurs if used for
spectral measurements.
• 1: Default whitening. This means that the whitening is as configured for the mode in use (potentially
with overrides). If the mode does not use whitening, no whitening is applied.
• 2: PRBS-15: The polynomial x15 + x14 + 1 is used. This gives a pseudo-noise sequence with length
32767.
• 3: PRBS-31: The polynomial x32 + x22 + x2 + x + 1 is used. This gives a pseudo-noise sequence with
length 4294967295.
When config.whitenMode = 2 or 3, initialization is done by the radio CPU writing 0xAAAA 0000 to the
PRBS value register before transmission starts. When config.whitenMode is 1, the default initialization is
used.
The transmitter runs until the trigger set up by endTrigger and endTime (see Section 23.3.2.5.1) occurs, or
until an abort command is issued.
If pktConfig.bFsOn is 1, the synthesizer is turned off (corresponding to CMD_FS_OFF; see
Section 23.3.3.1.6) after the operation is done; otherwise it is left on.
The operation ends by one of the causes listed in Table 23-14.
The command structure for CMD_TX_TEST contains the fields listed in Table 23-26.
Table 23-26. CMD_TX_TEST Command Format
Byte Index

Field Name

Bits

Bit Field Name

Type

Description

bUseCw

0: Send modulated signal.
1: Send continuous wave.

bFsOff

0: Keep frequency synthesizer on after
command.
1: Turn frequency synthesizer off after
command.

0: No whitening
1: Default whitening
2: PRBS-15
3: PRBS-32

config

2–3

whitenMode

15
16–17

Reserved
Value to send to the modem before
whitening

txWord

endTrigger

Trigger classifier for ending the operation

20–23

syncWord

Sync word to use for transmitter

24–27

endTime

Time to end the operation

Reserved

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1605

RF Core HAL

www.ti.com

23.3.3.1.9 CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
Command ID number: 0x0809
CMD_SYNC_STOP_RAT is a radio operation command. In addition to the parameters listed in
Table 23-8, the command structure contains the fields listed in Table 23-27.
For more details, see Chapter 14.
AON_RTC:CTL.RTC_UPD_EN must be 1.
Table 23-27. CMD_SYNC_STOP_RAT Command Format
Byte Index Field Name

Bits

Bit Field Name

Type

14–15
16–19

Description
Unused

rat0

The returned RAT value corresponding
to the value the RAT would have had
when the RTC was zero.

When the command starts, the radio CPU sets up capture of an RTC tick and waits for this tick, then
stops the RAT and calculates the value rat0. This value must be stored for use when the RAT restarts.
23.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
Command ID number: 0x080A
CMD_SYNC_START_RAT is a radio operation command. In addition to the parameters listed in
Table 23-8, the command structure contains the fields listed in Table 23-28.
For more details, see Chapter 14. TOP:AON_RTC:CTL.RTC_UPD_EN must be 1.
Table 23-28. CMD_SYNC_START_RAT Command Format
Byte Index Field Name

Bits

Bit Field Name

Type

Description

14–15

Unused

16–19

The desired RAT value corresponding to
the value the RAT would have had when
the RTC was zero. This parameter is
returned by CMD_SYNC_STOP_RAT.

rat0

When the command starts, the radio CPU starts the RAT and sets up capture of an RTC tick and waits for
this tick, then calculates the necessary timer adjustment based on the input parameter rat0 and performs
this adjustment. The input parameter rat0 is the value previously returned by CMD_SYNC_STOP_RAT.
Because the RAT is normally not running when this command is issued, the start trigger must be
TRIG_NOW (see Section 23.3.2.5.1).
The first time the RAT is started after system boot, the command CMD_START_RAT must be used (see
Section 23.3.4.7). As an alternative, CMD_SYNC_START_RAT may be issued with a fixed parameter
such as 0; however, this gives an arbitrary start value for the RAT. Before powering down the radio, the
system CPU must run the CMD_SYNC_STOP_RAT command. After powering up the radio again, the
system CPU must run the CMD_SYNC_START_RAT command with the same parameter as the one
received when CMD_SYNC_STOP_RAT was issued.

1606

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

23.3.3.1.11 CMD_COUNT: Counter Command
Command ID number: 0x080B
CMD_COUNT is a radio operation command. In addition to the parameters listed in Table 23-8, the
command structure contains the fields listed in Table 23-29.
Table 23-29. CMD_COUNT Command Format
Byte Index Field Name
14–15

Bits

Bit Field Name

counter

Type

Description

R/W

Counter. When starting, the radio CPU
decrements the value, and the end
status of the operation differs if the
result is zero.

When the command starts, the radio CPU decrements the counter field by 1 and writes the result back to
this field. If the result of the decrement is 0, the operation ends with the status DONE_COUNTDOWN and
the result FALSE. Otherwise, the operation ends with the status DONE_OK and the result TRUE, which
can be used in conditional execution to create a loop.
If the operation is started with counter equal to 0, this is an illegal parameter, so the operation ends with
the status ERROR_PAR.
The operation ends by one of the causes listed in Table 23-2 or Table 23-30.
Table 23-30. Additional End Causes for CMD_COUNT
Condition

Status Code

Result

Finished operation with counter > 0

DONE_OK

TRUE

Finished operation with counter = 0

DONE_COUNTDOWN

FALSE

23.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
Command ID number: 0x0810
CMD_SCH_IMM is a radio operation command. In addition to the parameters listed in Table 23-8, the
command structure contains the fields listed in Table 23-31.
Table 23-31. CMD_SCH_IMM Command Format
Byte Index Field Name

Bits

Bit Field Name

Type

14–15

Description
Reserved

16–19

cmdrVal

Value as would be written to CMDR

20–23

cmdstaVal

Value as would be returned in CMDSTA

When the command starts, the radio CPU takes the value in cmdrVal and processes it as if it had been
written to the CMDR register. This command may be a pointer to an immediate command, or it may form
a direct command as shown in Figure 23-4. A pointer to a radio operation command causes a scheduling
error. The value that would normally have been returned in CMDSTA is written to cmdstaVal. This means
that no command RF_CMD_ACK interrupt is raised. Instead, a COMMAND_DONE interrupt is raised, as
for any other radio operation command.
Depending on the result of the immediate or direct command, the status and result of the radio operation
command is as shown in Table 23-32.
CMD_SCH_IMM may run immediate commands as part of a chain of radio operation commands, or to
schedule them in the future. If an immediate or direct command received in the CMDR register is being
processed at the same time that a scheduled CMD_SCH_IMM command starts, the processing of the
scheduled command starts after the other command has finished.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1607

RF Core HAL

www.ti.com

Table 23-32. End Statuses for CMD_SCH_IMM
Condition

Status Code

Result

Immediate command ended with the result DONE

DONE_OK

TRUE

There was an error in the execution of the command, giving a CMDSTA result not listed in
DONE_FAILED
the following table row.

FALSE

There was an error in the command, giving one of the following results:
• SchedulingError
• UnknownCommand
• UnknownDirCommand
• IllegalPointer
• ParError

ABORT

ERROR_PAR

23.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
Command ID number: 0x0812
CMD_COUNT_BRANCH is a radio operation command. In addition to the parameters listed in Table 23-8,
the command structure contains the fields listed in Table 23-33.
Table 23-33. CMD_COUNT_BRANCH Command Format
Byte Index Field Name

Bits

Bit Field Name

Type

Description

14–15

counter

R/W

Counter
When starting, the radio CPU decrements
the value, and the end status of the
operation differs if the result is zero.

16–19

pNextOpIfOk

Pointer to next operation if counter did not
expire

When the command starts, the radio CPU decrements the counter field by 1, unless it was already 0, and
writes the result back to this field. If the result of the decrement is 0, the operation ends with the status
DONE_COUNTDOWN and the result FALSE. Otherwise, the operation ends with the status DONE_OK
and the result TRUE. In this case, the next radio operation command to run is given by pNextOpIfOk
instead of pNextOp (see Table 23-8), which can be used in conditional execution to create a loop.
If the operation is started with the counter equal to 0, the operation ends with the status DONE_OK and
the next operation is taken from pNextOpIfOk. This operation can be used if the previous command is set
up to skip optionally, as skipping from a previous command in the chain follows pNextOp.
The operation ends by one of the causes listed in Table 23-14 or Table 23-34.
Table 23-34. Additional End Causes for CMD_COUNT_BRANCH

1608

Condition

Status Code

Result

Finished operation with counter = 0 when being started

DONE_OK

TRUE

Finished operation with counter > 0 after decrementing

DONE_OK

TRUE

Finished operation with counter = 0 after decrementing

DONE_COUNTDOWN

FALSE

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

23.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
Command ID number: 0x0813
CMD_PATTERN_CHECK is a radio operation command. In addition to the parameters listed in
Table 23-8, the command structure contains the fields listed in Table 23-35.
Table 23-35. CMD_PATTERN_CHECK Command Format
Byte
Index

14–15

Field Name

patternOpt

Bits

Bit Field Name

Type

Description

0–1

operation

Operation to perform:
0: TRUE if value == compareVal
1: TRUE if value < compareVal
2: TRUE if value > compareVal
3: Reserved

bByteRev

If 1, interchange the 4 bytes of the value, so that they
are read the MSB first.

bBitRev

If 1, perform bit reversal of the value.

4–8

signExtend

0: Treat value and compareVal as unsigned.
1–31: Treat value and compareVal as signed, where
the value gives the number of the MSB in the signed
number.

bRxVal

0: Use pValue as a pointer.
1: Use pValue as a signed offset to the start of the last
committed RX entry element.

16–19

pNextOpIfOk

Pointer to next operation if comparison result was true

20–23

pValue

Pointer from which to read, or offset from last RX entry
if patternOpt.bRxVal == 1

24–27

mask

Bit mask to apply before comparison

28–31

compareVal

Value to which to compare

When the command starts, the radio CPU reads a 4-byte value from the location pointed to by pValue if
patternOpt.bRxVal == 0. If patternOpt.bRxVal == 1, the location to read from is found by taking the pointer
to the start of the last committed RX entry element and adding the signed number found in pValue as a
byte offset. In either case, this pointer does not need to be 4-byte-aligned. If the pointer is not bytealigned, the value is read byte by byte.
The value is then subject to the following operations in this order:
1. If patternOpt.bByteRev == 1, interchange byte 3 with byte 0, and byte 1 with byte 2, as if the bytes had
been read MSB first.
2. If patternOpt.bBitRev == 1, reverse the bit order of the entire 32-bit word.
3. Perform a bitwise ‘AND’ operation between the value and mask.
4. If patternOpt.signExtend > 0, copy the value of bit number patternOpt.signExtend (where bit 0 is the
LSB) into all the more significant bits.
5. Perform a compare operation between the resulting value and compareVal, depending on
patternOpt.operation (see Table 23-35). The compare operation is unsigned if
patternOpt.signExtend == 0; otherwise it is signed.
If patternOpt.operation or pValue have illegal values, the operation ends with a status of ERROR_PAR.
Otherwise, the operation ends by one of the causes listed in Table 23-14 or Table 23-36, depending on
the result of the comparison in Step 5 in the previous list. If the comparison result was TRUE, the next
radio operation command to run is given by pNextOpIfOk instead of pNextOp.
Table 23-36. Additional End Causes for CMD_PATTERN_CHECK
Condition

Status Code

Result

Comparison result was TRUE.

DONE_OK

TRUE

Comparison result was FALSE.

DONE_FAILED

FALSE

Command run with patternOpt.bRxVal when no RX data is fully received

ERROR_NO_RX

ABORT

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1609

RF Core HAL

www.ti.com

23.3.4 Protocol-Independent Direct and Immediate Commands
This section contains immediate commands that can be used across protocols. Commands for
manipulating data queues are described in Section 23.3.5.
23.3.4.1 CMD_ABORT: Abort Command
Command ID number: 0x0401
CMD_ABORT is a direct command.
On reception, the radio CPU ends ongoing radio operation commands as soon as possible. Analog
circuitry for RX and TX is safely turned off, and data structures are updated so they are not left in an
unfinished state.
If a radio operation command is running when the CMD_ABORT command is issued, the radio CPU
produces a COMMAND_DONE and LAST_COMMAND_DONE interrupt when the radio operation
command finishes. The status of the command structure of that radio operation command reflects that the
command was aborted.
If no radio operation command is running, no action is taken. The result signaled in the CMDSTA register
is DONE in all cases. If a radio operation command is running, CMDSTA may be updated before the radio
operation ends.
23.3.4.2 CMD_STOP: Stop Command
Command ID number: 0x0402
CMD_STOP is a direct command.
On reception, the radio CPU informs the radio operation command currently running that it has been
requested to stop. The CMD_STOP command is more graceful than the CMD_ABORT command, but
might take more time to finish. Normally, a packet being received or transmitted is handled to completion.
The exact behavior on reception of CMD_STOP is described for each radio operation command. Some
commands always end in a known time and do not respond to CMD_STOP.
If no radio operation command is running, no action is taken. The result signaled in the CMDSTA register
is DONE in all cases. If a radio operation command is running, CMDSTA may be updated before the radio
operation ends.

1610

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

23.3.4.3 CMD_GET_RSSI: Read RSSI Command
Command ID number: 0x0403
CMD_GET_RSSI is an immediate command that takes no parameters, and therefore, can be used as a
direct command.
On reception, the radio CPU reads the RSSI from an underlying receiver. The RSSI is returned in result
byte 2 (bit 23–16) of CMDSTA (see Figure 23-5). The RSSI is given on signed form in dBm. If no RSSI is
available, this is signaled with a special value of the RSSI ( 128, or 0x80).
If no radio operation command is running, the radio CPU returns the result ContextError in CMDSTA.
Otherwise, the radio CPU returns a result of DONE along with the RSSI value.
23.3.4.4 CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
Command ID number: 0x0001
CMD_UPDATE_RADIO_SETUP is an immediate command that takes the parameters listed in
Table 23-37.
Table 23-37. CMD_UPDATE_RADIO_SETUP Command Format
Byte Index Field Name
0–1

Bits

Bit Field Name

commandNo

Type

Description

The command ID number

2–3
4–7

Reserved
pRegOverride

Pointer to a list of hardware and
configuration registers to override

On reception, the radio CPU updates the registers given in pRegOverride. This is a pointer to a structure
containing an override value for certain hardware registers, a radio configuration controlled by the radio
CPU, and protocol-related variables. The format is as for CMD_RADIO_SETUP (see Section 23.3.3.1). If
done while the radio is running, the update must primarily be done on the radio and protocol configuration,
as modifications to hardware registers may cause undesired behavior.
23.3.4.5 CMD_TRIGGER: Generate Command Trigger
Command ID number: 0x0404
CMD_TRIGGER is an immediate command that takes the parameters listed in Table 23-38.
Table 23-38. CMD_TRIGGER Command Format
Byte Index Field Name

Type

Description

0–1

commandNo

Bits

Bit Field Name

The command ID number

triggerNo

Command trigger number

On reception, the radio CPU generates the command trigger specified with triggerNo, so that running
radio operation commands respond accordingly (see Section 23.3.2.5.1).
If the trigger number is outside the valid range 0–3, the radio CPU returns the result ParError in CMDSTA.
If no radio operation command running is pending on the trigger number sent, the radio CPU returns the
result ContextError in CMDSTA. Otherwise, the radio CPU returns a result of DONE, which may be
returned before the running radio operation command responds to the trigger.
CMD_TRIGGER may be sent as a direct command. If so, the trigger number is given by the parameter in
bits 8–15 of CMDR.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1611

RF Core HAL

www.ti.com

23.3.4.6 CMD_GET_FW_INFO: Request Information on the Firmware Being Run
Command ID number: 0x0002
CMD_GET_FW_INFO is an immediate command that takes the parameters listed in Table 23-39.
Table 23-39. CMD_GET_FW_INFO Command Format
Byte Index

Field Name

Type

Description

0–1

commandNo

Bits

Bit Field Name

The command ID number

2–3

versionNo

Firmware version number

4–5

startOffset

The start of free RAM

6–7

freeRamSz

The size of free RAM

8–9

availRatCh

Bitmap of available RAT channels

On reception, the radio CPU reports information on the running radio firmware. A version number is
returned in versionNo. The startOffset and freeRamSz fields contain information on the area in the radio
RAM that is not used by the radio CPU for data (including stack and heap). This area is free to use by the
system CPU for data exchange, radio CPU patching, or other purposes. The start and end address of the
free RAM is given as offset from the start of the radio RAM.
NOTE: Some of this free RAM is used for patches provided by TI.

The availRatCh field is a bitmap where bit position n indicates whether RAT channel n may be used by the
system CPU. A bit value of 1 indicates that the corresponding channel may be used by the system CPU,
while a bit value of 0 means that the channel is reserved for the radio CPU or is nonexistent.
23.3.4.7 CMD_START_RAT: Asynchronously Start Radio Timer Command
Command ID number: 0x0405
CMD_ START_RAT is a direct command.
On reception, the radio CPU starts the RAT if it has not already started.
If the RAT is already running, the radio CPU returns the result ContextError in CMDSTA. Otherwise, the
radio CPU returns a result of DONE.
23.3.4.8 CMD_PING: Respond With Interrupt
Command ID number: 0x0406
CMD_PING is a direct command.
On reception, the radio CPU returns a result of DONE in CMDSTA. This command can test the
communication between the two CPUs, or check when the radio CPU is ready after boot.

1612

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

23.3.4.9 CMD_READ_RFREG: Read RF Core Register
Command ID number: 0x0601
CMD_READ_RFREG is an immediate command that takes the parameters listed in Table 23-40.
Table 23-40. CMD_READ_RFREG Command Format
Byte Index Field Name

Type

Description

0–1

commandNo

Bits

Bit Field Name

The command ID number

2–3

address

The offset from the start of the RF core hardware
register bank (0x4004 0000)

4–7

value

Returned value of the register

On reception, the radio CPU reads the RF core register with address 0x4004 0000 + address. The result
is written to value. If the address is not divisible by 4, the radio CPU returns ParError in CMDSTA.
CMD_READ_RFREG may be sent as a direct command. If so, the address is given by bits 2–15 of
CMDR, with the 2 LSBs of the address set to 00.
When reading has been performed, the result is returned in value. The 24 LSBs of the result are returned
in CMDSTA bits 8–31. The result returned in CMDSTA is DONE.
23.3.4.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
Command ID number: 0x000A
CMD_SET_RAT_CMP is an immediate command that takes the parameters listed in Table 23-41.
Table 23-41. CMD_SET_RAT_CMP Command Format
Byte
Index

Field Name

0–1
2

Bits

Bit Field Name

Type

Description

commandNo

The command ID number

ratCh

The radio timer channel number

compareTime

3
4–7

Reserved
The time at which the compare occurs

On reception, the radio CPU sets the RAT channel given by ratCh in compare mode, and sets the channel
compare time to compareTime, which also arms the channel. A channel event occurs at the given time,
and this can be enabled as an RF hardware interrupt to the system CPU through the RFC_DBELL
module.
The channel number must indicate a channel that is not reserved for use by the radio CPU. Otherwise, the
radio CPU returns ParError in CMDSTA. If the compare time is in the past when the command is
evaluated, the radio CPU returns ContextError in CMDSTA and disables the RAT channel. If the compare
event is successfully set up, the radio CPU returns a result of DONE in CMDSTA.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1613

RF Core HAL

www.ti.com

23.3.4.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
Command ID number: 0x0603
CMD_SET_RAT_CPT is an immediate command that takes the parameters listed in Table 23-42.
Table 23-42. CMD_SET_RAT_CPT Command Format
Byte Index

Field Name

0–1

commandNo

Bits

Bit Field Name

Type

Description

The command ID number

0–2

2–3

config

Reserved

3–7

inputSrc

Input source indicator:
22: RFC_GPI0
23: RFC_GPI1
Others: Reserved

8–11

ratCh

The radio timer channel number

bRepeated

0: Single capture mode
1: Repeated capture mode

Input mode:
00: Rising edge
01: Falling edge
10: Both edges
11: Reserved

13–14

inputMode

On reception, the radio CPU sets the RAT channel given by config.ratCh in capture mode. If
config.bRepeated is 0, the channel is set to single capture mode; otherwise, the channel is set to repeated
capture mode. The radio CPU sets the input source to config.inputSrc and the input mode to
config.inputMode. If the channel is set in single capture mode, it is also armed. This causes a channel
event to occur when capture occurs, and can be enabled as an RF hardware interrupt to the system CPU
through the RFC_DBELL module.
CMD_SET_RAT_CMP may be sent as a direct command. If so, bits 2–15 of the config word are given by
bits 2–15 of CMDR (bits 0–1 of config are not used).
The channel number must indicate a channel that is not reserved for use by the radio CPU. Otherwise, the
radio CPU returns ParError in CMDSTA. If the channel is successfully set up, the radio CPU returns a
result of DONE in CMDSTA.
23.3.4.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
Command ID number: 0x0408
CMD_DISABLE_RAT_CH is an immediate command that takes the parameters listed in Table 23-43.
Table 23-43. CMD_DISABLE_RAT_CH Command Format
Byte Index Field Name

Type

Description

0–1

commandNo

Bits

Bit Field Name

The command ID number

ratCh

The RAT channel number

On reception, the radio CPU disables the RAT channel given by ratCh. This disables previous
configurations of that channel done by the CMD_SET_RAT_CMP or CMD_SET_RAT_CPT command.
CMD_DISABLE_RAT_CH may be sent as a direct command. If so, ratCh is given by the parameter in bits
8–15 of CMDR.
The channel number must indicate a channel that is not reserved for use by the radio CPU. Otherwise, the
radio CPU returns ParError in CMDSTA. If the channel number is valid, the CPU returns a result of DONE
in CMDSTA after the channel has been disabled.

1614

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

23.3.4.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
Command ID number: 0x0604
CMD_SET_RAT_OUTPUT is an immediate command that takes the parameters listed in Table 23-44.
Table 23-44. CMD_SET_RAT_OUTPUT Command Format
Byte Index Field Name
0–1

2–3

Bits

Bit Field Name

commandNo

Type

Description

The command ID number

0–1

Reserved

2–4

Output event indicator:
1: RAT_GPO1
2: RAT_GPO2
3: RAT_GPO3
Others: Reserved

outputSel

5–7

outputMode

Output mode:
000: Pulse
001: Set
010: Clear
011: Toggle
100: Always 0
101: Always 1
Others: Reserved

8–11

ratCh

The RAT channel number

config

On reception, the radio CPU sets the RAT output event given by config.outputSel in the mode given by
config.outputMode, and to be controlled by the RAT channel given by config.ratCh. This command must
be combined with setting this channel in compare mode, using the CMD_SET_RAT_CMP command.
CMD_SET_RAT_OUTPUT may be sent as a direct command. If so, bits 2–15 of the config word are given
by bits 2–15 of CMDR (bits 0–1 of config are not used).
The channel number, config.ratCh, must indicate a channel that is not reserved for use by the radio CPU,
and the output number, config.outputSel, must not be an output used by the radio CPU. Otherwise, the
radio CPU returns ParError in CMDSTA. If the output event is successfully set up, the radio CPU returns a
result of DONE in CMDSTA.
23.3.4.14 CMD_ARM_RAT_CH: Arm RAT Channel
Command ID number: 0x0409
CMD_ARM_RAT_CH is an immediate command that takes the parameters listed in Table 23-45.
Table 23-45. CMD_ARM_RAT_CH Command Format
Byte Index Field Name

Type

Description

0–1

commandNo

Bits

Bit Field Name

The command ID number

ratCh

The RAT channel number

On reception, the radio CPU arms the RAT channel given by ratCh.
The CMD_DISABLE_RAT_CH command may be sent as a direct command. If so, ratCh is given by the
parameter in bits 8–15 of CMDR.
The channel number must indicate a channel not reserved for use by the radio CPU. Otherwise, the radio
CPU returns ParError in CMDSTA. If the channel number is valid, the CPU returns a result of DONE in
CMDSTA after the channel is armed.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1615

RF Core HAL

www.ti.com

23.3.4.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
Command ID number: 0x040A
CMD_DISARM_RAT_CH is an immediate command that takes the parameters listed in Table 23-46.
Table 23-46. CMD_DISARM_RAT_CH Command Format
Byte Index Field Name

Type

Description

0–1

commandNo

Bits

Bit Field Name

The command ID number

ratCh

The RAT channel number

On reception, the radio CPU disarms the RAT channel given by ratCh.
CMD_DISABLE_RAT_CH may be sent as a direct command. If so, ratCh is given by the parameter in bits
8–15 of CMDR.
The channel number must indicate a channel not reserved for use by the radio CPU. Otherwise, the radio
CPU returns ParError in CMDSTA. If the channel number is valid, the CPU returns a result of DONE in
CMDSTA after the channel is armed.
23.3.4.16 CMD_SET_TX_POWER: Set Transmit Power
Command ID number: 0x0010
CMD_SET_TX_POWER is an immediate command that takes the parameters listed in Table 23-47
(CC26x0) and Table 23-48 (CC13x0).
Table 23-47. CMD_SET_TX_POWER Command Format (CC26x0)
Byte Index

Field Name

0–1

commandNo

2–3

txPower

1616

Radio

IB25qC %

Bits

Bit Field Name

Type

Description

The command ID number

New TX power setting. It is
recommended to use values from
SmartRF Studio.
Bits 0-5: IB
Value to write to the PA power
control field at 25°C.
See Equation 14 for details.
Bits 6-7: GC
Value to write to the gain control of
the first stage of the PA.
Bits 8-15: tempCoeff
Temperature coefficient for IB.
0: No temperature compensation.

(Temperature[qC] " 25) u tempCoeff
512

(14)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

Table 23-48. CMD_SET_TX_POWER Command Format (CC13x0)
Byte Index

Field Name

0–1

commandNo

2–3

Bits

Bit Field Name

txPower

IB25qC %

Type

Description

The command ID number

New TX power setting. It is
recommended to use values from
SmartRF Studio.
Bits 0-5: IB
Value to write to the PA power
control field at 25°C.
See Equation 15 for details.
Bits 6-7: GC
Value to write to the gain control of
the first stage of the PA.
Bit 8: boost
Driver strength into the PA.
0: Low driver strength
1: High driver strength
Bits 9-15: tempCoeff
Temperature coefficient for IB.
0: No temperature compensation.

(Temperature[qC] " 25) u tempCoeff
256

(15)

On reception, the radio CPU sets the transmit power for use the next time transmission begins. If a packet
is being transmitted, the transmit power is not updated until transmission begins for the next packet.
Each time transmission of a packet begins, temperature compensation of the transmit power is done.
On completion, the radio CPU returns a result of DONE in CMDSTA.
23.3.4.17 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration
Command ID number: 0x0011
CMD_UPDATE_FS is an immediate command that takes the parameters listed in Table 23-49.
Table 23-49. CMD_UPDATE_FS Command Format
Byte Index

Field Name

0–1

Bits

Bit Field Name

Type

Description

commandNo

The command ID number

14–15

frequency

The frequency in MHz to tune to

16–17

fractFreq

Fractional part of the frequency to
tune to

2–13

Reserved

On reception, the radio CPU programs a new frequency in the synthesizer without restarting calibration.
This must be a small change compared to the frequency used under calibration, otherwise the synthesizer
is most likely unable to relock. Extra distortion may occur if the command is done during RX or TX.
This command is supported only in the 2.4-GHz frequency band.
NOTE: This command is not characterized. Limits for frequency changes are unknown.

The frequency to use is given by frequency and fractFreq, and the frequency must be as close as possible
to (frequency + fractFreq / 65536) MHz.
If the synthesizer is not running and the calibration is done, the radio CPU returns ContextError in
CMDSTA. If frequency is invalid, the radio CPU returns ParError in CMDSTA. Otherwise, the radio CPU
returns a result of DONE in CMDSTA when the update is finished.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1617

RF Core HAL

www.ti.com

23.3.4.18 CMD_BUS_REQUEST: Request System BUS Available for RF Core
Command ID number: 0x040E
CMD_BUS_REQUEST is an immediate command that takes the parameters listed in Table 23-50.
Table 23-50. CMD_BUS_REQUEST Command Format
Byte Index

Field Name

Type

Description

0–1

commandNo

Bits

Bit Field Name

The command ID number

bSysBusNeeded

0: System bus may sleep
1: System bus access needed

On reception, the radio CPU sets the bus request bit toward the PRCM to 1 if bSysBusNeeded is nonzero,
or to 0 if bSysBusNeeded is zero. If bSysBusNeeded is nonzero, this indicates that the system bus stays
awake even if the system goes to deep sleep, which must be done for the RF core to run and access the
system side for one of the following reasons:
• Any command structure, data structure, and so on, pointed to by a pointer sent to the RF core is
placed in system RAM or flash.
• The RF core must read the temperature because the TX power has a nonzero temperature coefficient.
• The RF core must read the RTC to synchronize with the RAT during CMD_SYNC_STOP_RAT or
CMD_SYNC_START_RAT.
CMD_BUS_REQUEST may be sent as a direct command. If so, bSysBusNeeded is given by the
parameter in bits 8–15 of CMDR.
The radio CPU returns a result of DONE in CMDSTA when the update finishes.

23.3.5 Immediate Commands for Data Queue Manipulation
The following commands are immediate commands used for data queue manipulation for all radio
operations that use data queues.
23.3.5.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
Command ID number: 0x0005
CMD_ADD_DATA_ENTRY is an immediate command that takes the parameters listed in Table 23-51.
Table 23-51. CMD_ADD_DATA_ENTRY Command Format
Byte Index Field Name
0–1

commandNo

Bits

Bit Field Name

Type

Description

The command ID number

2–3

Reserved

4–7

pQueue

Pointer to the queue structure to which the
entry is added

8–11

pEntry

Pointer to the entry

On reception, the radio CPU appends the provided data entry to the queue indicated. The radio CPU
performs the following operations:
Set pQueue-> pLastEntry-> pNextEntry = pEntry
Set pQueue-> pLastEntry = pEntry
If either of the pointers pQueue or pEntry are invalid (that is, in an address range that is not memory or
without 32-bit word alignment), the command fails, and the radio CPU sets the result byte of CMDSTA to
ParError. If the queue specified in pQueue is set up not to allow entries to be appended (see
Section 23.3.2.7.1), the command fails, and the radio CPU sets the result byte of CMDSTA to QueueError.

1618

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

RF Core HAL

www.ti.com

23.3.5.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
Command ID number: 0x0006
CMD_REMOVE_DATA_ENTRY is an immediate command that takes the parameters listed in
Table 23-52.
Table 23-52. CMD_REMOVE_DATA_ENTRY Command Format
Byte Index

Field Name

0–1

commandNo

Bits

Bit Field Name

Type

Description

The command ID number

2–3

Reserved

4–7

pQueue

Pointer to the queue structure from which the
entry is removed

8–11

pEntry

Pointer to the entry that was removed

On reception, the radio CPU removes the first data entry from the queue indicated. The command returns
a pointer to the entry that was removed. The radio CPU performs the following operations:
Set pEntry = pQueue->pCurrEntry
Set pQueue->pCurrEntry = pEntry->pNextEntry
Set pEntry->status = Finished
If the pointer pQueue is invalid, the command fails, and the radio CPU sets the result byte of CMDSTA to
ParError. If the queue specified in pQueue is empty, the command fails, and the radio CPU sets the result
byte of CMDSTA to QueueError. If the entry to be removed is in the BUSY state, the command fails, and
the radio CPU sets the result byte of CMDSTA to QueueBusy.
23.3.5.3 CMD_FLUSH_QUEUE: Flush Queue
Command ID number: 0x0007
CMD_FLUSH_QUEUE is an immediate command that takes the parameters listed in Table 23-53.
Table 23-53. CMD_FLUSH_QUEUE Command Format
Byte Index

Field Name

Type

Description

0–1

commandNo

Bits

Bit Field Name

The command ID number

4–7

pQueue

Pointer to the queue structure to be flushed

8–11

pFirstEntry

Pointer to the first entry that was removed

2–3

Reserved

On reception, the radio CPU flushes the queue indicated, and returns a pointer to the first entry that was
removed. The radio CPU performs the following operations:
Set pFirstEntry = pQueue->pCurrEntry
Set pQueue->pCurrEntry = NULL
Set pQueue->pLastEntry = NULL
If the pointer pQueue is invalid, the command fails, and the radio CPU sets the result byte of CMDSTA to
ParError. If the first entry to be removed is in the BUSY state, the command fails, and the radio CPU sets
the result byte of CMDSTA to QueueBusy. If the queue specified in pQueue is empty, the radio CPU does
not need to do any operation, but this is still viewed as a success. The returned pFirstEntry is NULL in this
case.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1619

RF Core HAL

www.ti.com

23.3.5.4 CMD_CLEAR_RX: Clear All RX Queue Entries
Command ID number: 0x0008
CMD_CLEAR_RX is an immediate command that takes the parameters listed in Table 23-54.
Table 23-54. CMD_CLEAR_RX Command Format
Byte Index

Field Name

Type

Description

0–1

commandNo

Bits

Bit Field Name

The command ID number

pQueue

2–:3
4–7

Reserved
Pointer to the queue structure to be cleared

On reception, the radio CPU makes all RX entries indicate that they are empty. The radio CPU performs
the following operations:
Set pTemp = pQueue->pCurrEntry
Loop: Set pTemp->status = Pending
If pTemp->type == 1 then:
Set pTemp->nextIndex = 0
Set pTemp->numElements = 0
Set pTemp = pTemp->nextIndex
If pTemp != NULL and pTemp != pQueue->pCurrEntry, repeat from Loop
If the pointer pQueue is invalid, the command fails, and the radio CPU sets the result byte of CMDSTA to
ParError. If the queue specified in pQueue is empty, the command fails, and the radio CPU sets the result
byte of CMDSTA to QueueError. If the first entry to be removed is in the BUSY state, the command fails,
and the radio CPU sets the result byte of CMDSTA to QueueBusy.
23.3.5.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
Command ID number: 0x0009
CMD_REMOVE_PENDING_ENTRIES is an immediate command that takes the parameters listed in
Table 23-55.
Table 23-55. CMD_REMOVE_PENDING_ENTRIES Command Format
Byte Index

Field Name

0–1

Bits

Bit Field Name

Type

Description

commandNo

The command ID number

4–7

pQueue

Pointer to the queue structure to be flushed

8–11

pFirstEntry

Pointer to the first entry that was removed

2–3

Reserved

On reception, the radio CPU removes all entries that are in the Pending state from the queue indicated,
and returns a pointer to the first entry that was removed. The radio CPU performs the following operations:
If pQueue->pCurrEntry->status = Pending, then
Set pFirstEntry = pQueue->pCurrEntry
Set pQueue->pCurrEntry = NULL
Set pQueue->pLastEntry = NULL
else
Set pFirstEntry = pQueue->pCurrEntry->pNextEntry
Set pQueue->pCurrEntry->pNextEntry = NULL
Set pQueue->pLastEntry = pQueue->pCurrEntry
If the pointer pQueue is invalid, the command fails, and the radio CPU sets the result byte of CMDSTA to
ParError. If the queue specified in pQueue is empty, the radio CPU does not need to do any operation, but
this is still viewed as a success. The returned pFirstEntry is NULL in this case.
1620

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Queue Usage

www.ti.com

23.4 Data Queue Usage
This section describes how the radio CPU uses data queues.

23.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
Section 23.3.5 lists commands used for data queue manipulation. For internal radio CPU operations
described, additional operations are available. These operations are described in the following sections.
23.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
The procedure takes the following input parameters:
• Pointer to queue, pQueue
The procedure returns the following:
• Pointer to allocated data entry, pEntry
The procedure returns with error if the specified queue is empty, or if the first entry of the queue is already
busy. Otherwise, the following is done:
Set pQueue->pCurrEntry->status = Busy
Set pEntry = pQueue->pCurrEntry
23.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
The procedure takes the following input parameters:
• Pointer to queue, pQueue
The procedure returns the following:
• Pointer to allocated data entry, pEntry
The procedure returns with error if the specified queue is empty. Otherwise, the following is done:
Set pQueue->pCurrEntry->status = Active
23.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
The procedure takes the following input parameters:
• Pointer to queue, pQueue
The procedure returns the following:
• Pointer to new entry, pEntry
The procedure returns with error if the specified queue is empty. Otherwise, the following is done:
Set pTemp = pQueue->pCurrEntry
Set pQueue->pCurrEntry = pTemp->pNextEntry
Set pTemp->status = Finished
Set pEntry = pQueue->pCurrEntry

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1621

Data Queue Usage

www.ti.com

23.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
The procedure takes the following input parameters:
• Pointer to queue, pQueue
• Size of entry element to store, size
The procedure returns the following:
• Pointer to data entry where data is stored, pEntry
• Pointer to a finished data entry, or NULL if not finished, pFinishedEntry
The procedure returns with error if the first entry of the queue is already busy. If there is not room for an
entry element of the specified size, including if the queue is empty, a “no space” error is returned. The
following procedure describes the operations:
Set pFinishedEntry == NULL
If pQueue->pCurrEntry == NULL then
Return with no space error
end if
If pQueue->pCurrEntry->type != 1 then
if pQueue->pCurrEntry->length < size then
Return with no space error
else
Set pQueue->pCurrEntry->status = Busy
Set pEntry = pQueue->pCurrEntry
end if
else
Set pTemp = pQueue->pCurrEntry
If pTemp->nextIndex + 2 + size > pTemp->length then
Set pQueue->pCurrEntry = pTemp->pNextEntry
Set pTemp->status = Finished
Set pFinishedEntry = pTemp
Set pTemp = pTemp->pNextEntry
If pTemp == NULL or pTemp->length < size + 2 then
Return with no space error
end if
end if
Set pTemp->status = Busy
Set pEntry = pTemp
end if

1622

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Data Queue Usage

www.ti.com

23.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
The procedure takes the following input parameters:
• Pointer to queue, pQueue
• Size of entry element that has been stored, size
The procedure returns the following:
• Pointer to data entry where data is stored, pEntry
• Pointer to a finished data entry, or NULL if not finished, pFinishedEntry
The procedure returns with error if the queue is empty or if there is not room for an entry element of the
specified size. Otherwise, the following is done:
If pQueue->pCurrEntry->type != 1 then
Set pTemp = pQueue->pCurrEntry
Set pQueue->pCurrEntry = pTemp->pNextEntry
Set pTemp->status = Finished
else
Increase pQueue->pCurrEntry->nextIndex by size
Increment pQueue->pCurrEntry->numElements by 1
If pQueue->pCurrEntry->nextIndex + 2 == pQueue->pCurrEntry>length then
Set pTemp = pQueue->pCurrEntry
Set pQueue->pCurrEntry = pTemp->pNextEntry
Set pTemp->status = Finished
Set pFinishedEntry == pTemp
else
Set pQueue->pCurrEntry->status = Active
Set pFinishedEntry == NULL
end if
end if
This operation is done after doing PROC_ALLOCATE_RX and writing to the correct locations in the buffer;
the size must be the same as with PROC_ALLOCATE_RX.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1623

Data Queue Usage

www.ti.com

23.4.2 Radio CPU Usage Model
23.4.2.1 Receive Queues
When the radio CPU receives a packet, it prepares a buffer for reading by calling PROC_ALLOCATE_RX.
If this is successful, the allocated buffer is used to store the incoming packet as defined for each protocol.
If a no space error occurs, the received data cannot be stored, and the handling is defined for each
protocol.
After a packet has been received, it may be kept or discarded depending on rules defined for each
protocol. To keep the packet, the radio CPU calls PROC_FINISH_RX. This makes the received data
available for the system CPU. To discard the packet, the radio CPU calls PROC_FREE_DATA_ENTRY,
meaning that the next packet may overwrite the data received in the last packet.
23.4.2.2 Transmit Queues
When the radio CPU is about to transmit a packet from a TX queue, it calls PROC_ALLOCATE_TX to get
a pointer to the data to transmit. When the packet transmits, the radio CPU calls
PROC_FINISH_DATA_ENTRY or PROC_FREE_DATA_ENTRY. If PROC_FINISH_DATA_ENTRY is
called, the system CPU is informed that the entry is finished and may be reused. This calling process
must be used if retransmission of the packet is not an option. If PROC_FREE_DATA_ENTRY is called,
the transmitted entry remains first in the queue so that it may be transmitted, which is used when an
acknowledgment is expected.
If an acknowledgment is received on a packet that was transmitted, followed by the radio CPU calling
PROC_FREE_DATA_ENTRY, the radio CPU calls PROC_ALLOCATE_TX followed by
PROC_FINISH_DATA_ENTRY (this is equivalent to CMD_REMOVE_DATA_ENTRY, see Section 23.3.4).
This calling process causes the next entry in the queue to be transmitted. If an acknowledgment is not
received, the last transmitted packet is retransmitted.

1624

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

IEEE 802.15.4

www.ti.com

23.5 IEEE 802.15.4
This section describes IEEE 802.15.4-specific command structure, interrupts, data handling, radio
operation commands, and immediate commands.

23.5.1 IEEE 802.15.4 Commands
Table 23-56 and Table 23-57 define the IEEE 802.15.4-specific radio operation commands.
Table 23-56. IEEE 802.15.4 Radio Operation Commands on Background Level
ID

Command Name

Description

0x2801

CMD_IEEE_RX

Run receiver

0x2802

CMD_IEEE_ED_SCAN

Run energy detect scan

Table 23-57. IEEE 802.15.4 Radio Operation Commands on Foreground Level
ID

Command Name

Description

0x2C01

CMD_IEEE_TX

Transmit packet

0x2C02

CMD_IEEE_CSMA

Perform CSMA-CA

0x2C03

CMD_IEEE_RX_ACK

Receive acknowledgment

0x2C04

CMD_IEEE_ABORT_BG

ABORT background level operation

In addition, Table 23-58 defines immediate commands.
Table 23-58. IEEE 802.15.4 Immediate Commands
ID

Command Name

Description

0x2001

CMD_IEEE_MOD_CCA

Modify CCA parameters for running
receiver

0x2002

CMD_IEEE_MOD_FILT

Modify frame filtering parameters for
running receiver

0x2003

CMD_IEEE_MOD_SRC_MATCH

Modify source matching parameters for
running receiver

0x2401

CMD_IEEE_ABORT_FG

ABORT foreground level operation

0x2402

CMD_IEEE_STOP_FG

Stop foreground level operation

0x2403

CMD_IEEE_CCA_REQ

Request CCA and RSSI information

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1625

IEEE 802.15.4

www.ti.com

23.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
Table 23-8 defines the first 14 bytes for all radio operation commands. The CMD_IEEE_ABORT_BG
command does not have any additional fields to those 14 bytes. Table 23-59 lists the IEEE 802.15.4 RX
command structure for bytes 14–59.
Table 23-59. IEEE 802.15.4 RX Command Structure
Byte Index

Field Name

Type

Description

channel

Channel to tune to in the start of the operation:
0: Use existing channel
11–26: Use as IEEE 802.15.4 channel; that is, frequency is
[2405 + 5 × (channel 11)] MHz
60–207: Frequency is (2300 + channel) MHz
Others: reserved

rxConfig

Configuration bits for the receive queue entries (see Table 23-69 for details)

16–19

pRxQ

Receive queue

20–23

pOutput

Pointer to result structure (see Table 23-68)
(NULL: Do not store results)

24–25

frameFiltOpt

R/W

Frame filtering options (see Table 23-71 for details)

frameTypes

R/W

Frame types to receive in frame filtering (see Table 23-72 for details)

ccaOpt

R/W

CCA options (see Table 23-70 for details)

ccaRssiThr

R/W

RSSI threshold for CCA

numExtEntries

Number of extended address entries

numShortEntries

Number of short address entries

32–35

pExtEntryList

Pointer to list of extended address entries

36–39

pShortEntryList

Pointer to list of short address entries

40–47

localExtAddr

The extended address of the local device

48–49

localShortAddr

The short address of the local device

50–51

localPanID

The PAN ID of the local device

endTrigger

Trigger that causes the device to end the RX operation

56–59

endTime

Time parameter for endTrigger

Reserved

52–54

Reserved

Table 23-60 lists the IEEE 802.15.4 energy detect scan command structure.
Table 23-60. IEEE 802.15.4 Energy Detect Scan Command Structure
Byte Index

Field Name

Type

Description

channel

Channel to tune to at the start of the operation:
0: Use existing channel
11–26: Use as IEEE 802.15.4 channel; that is,
frequency is [2405 + 5 × (channel – 11)] MHz
60–207: Frequency is (2300 + channel) MHz
Others: reserved

ccaOpt

R/W

CCA options (see Table 23-70 for details)

ccaRssiThr

R/W

RSSI threshold for CCA

maxRssi

The maximum RSSI recorded during the ED scan

endTrigger

Trigger that causes the device to end the RX
operation

20–23

endTime

Time parameter for endTrigger

Reserved

Table 23-61 lists the IEEE 802.15.4 CSMA-CA command structure.

1626Radio

IEEE 802.15.4

www.ti.com

Table 23-61. IEEE 802.15.4 CSMA-CA Command Structure
Byte Index

Field Name

Type

Description

14–15

randomState

R/W

The state of the pseudo-random generator

macMaxBE

The IEEE 802.15.4 MAC parameter macMaxBE

macMaxCSMABackoffs

The IEEE 802.15.4 MAC parameter
macMaxCSMABackoffs

Bits

Bit Field Name

0–4

initCW

The initialization value for the CW parameter

bSlotted

0 for nonslotted CSMA, 1 for slotted CSMA

0: RX stays on during CSMA backoffs.
1: The CSMA-CA algorithm suspends the
receiver if no frame is being received.
2: The CSMA-CA algorithm suspends the
receiver if no frame is being received, or after
finishing it (including auto ACK) otherwise.
3: The CSMA-CA algorithm suspends the
receiver immediately during backoffs.

csmaConfig
6–7

rxOffMode

R/W

The NB parameter from the IEEE 802.15.4
CSMA-CA algorithm

R/W

The BE parameter from the IEEE 802.15.4
CSMA-CA algorithm

remainingPeriods

R/W

The number of remaining periods from a
paused backoff countdown

lastRssi

RSSI measured at the last CCA operation

endTrigger

Trigger that causes the device to end the
CSMA-CA operation

24–27

lastTimeStamp

Time of the last CCA operation

28–31

endTime

Time parameter for endTrigger

Table 23-62 lists the IEEE 802.15.4 TX command structure.
Table 23-62. IEEE 802.15.4 TX Command Structure
Byte Index Field Name

txOpt

Bits

Bit Field Name

Type

Description

bIncludePhyHdr

0: Find PHY header automatically.
1: Insert PHY header from the buffer.

bIncludeCrc

0: Append automatically calculated CRC.
1: Insert FCS (CRC) from the buffer.

Reserved

3–7

payloadLenMsb

Most significant bits of payload length. Must only be
nonzero to create long nonstandard packets for test
purposes.

payloadLen

Number of bytes in the payload

16–19

pPayload

Pointer to payload buffer of size payloadLen

20–23

timeStamp

Timestamp of transmitted frame

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1627

IEEE 802.15.4

www.ti.com

Table 23-63 lists the IEEE 802.15.4 Receive ACK command structure.
Table 23-63. IEEE 802.15.4 Receive ACK Command Structure
Byte Index

Field Name

Type

Description

seqNo

Sequence number to expect

endTrigger

Trigger that causes the device to give up
acknowledgment reception

16–19

endTime

Time parameter for endTrigger

23.5.1.2 IEEE 802.15.4 Immediate Command Structures
Table 23-64 lists the IEEE 802.15.4 Modify CCA immediate command structure.
Table 23-64. IEEE 802.15.4 Modify CCA Immediate Command Structure
Byte Index

Field Name

Type

Description

0–1

commandNo

The command number

newCcaOpt

New value of ccaOpt for the running background
level operation (see Table 23-70 for details)

newCcaRssiThr

New value of ccaRssiThr for the running
background level operation

Table 23-65 lists the IEEE 802.15.4 modify frame filtering immediate command structure.
Table 23-65. IEEE 802.15.4 Modify Frame Filtering Immediate Command Structure
Byte Index

Field Name

Type

Description

0–1

commandNo

The command number

2–3

newFrameFiltOpt

New value of frameFiltOpt for the running
background level operation

newFrameTypes

New value of frameTypes for the running
background level operation

Table 23-66 lists the IEEE 802.15.4 enable or disable source matching entry immediate command
structure.
Table 23-66. IEEE 802.15.4 Enable or Disable Source Matching Entry
Immediate Command Structure
Byte Index

Field Name

0–1

commandNo

options

Bits

Bit Field Name

Type

Description

The command number

bEnable

0: Disable entry
1: Enable entry

srcPend

New value of the pending bit for
the entry

entryType

0: Extended address
1: Short address

3–7
3

1628

Radio

entryNo

Reserved
W

Index of entry to enable or
disable

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

IEEE 802.15.4

www.ti.com

Table 23-67 lists the IEEE 802.15.4 Request CCA state immediate command structure.
Table 23-67. IEEE 802.15.4 Request CCA State Immediate Command Structure
Byte Index

Field Name

Type

Description

0–1

commandNo

Bits

The command number

currentRssi

The RSSI currently observed on
the channel

maxRssi

The maximum RSSI observed
on the channel because RX was
started

Value of the current CCA state:
00: Idle
01: Busy
10: Invalid

Value of the current energy
detect CCA :state.
00: Idle
01: Busy
10: Invalid

Value of the current correlator
based carrier sense CCA state:
00: Idle
01: Busy
10: Invalid

Value of the current sync found
based carrier sense CCA state:
0: Idle
1: Busy

0–1

2–3

Bit Field Name

ccaState

ccaEnergy

ccaInfo
4–5

ccaCorr

ccaSync

Reserved

23.5.1.3 Output Structures
Table 23-68 lists the RX commands.
Table 23-68. RX Command
Byte Index

Field Name

Type

Description

nTxAck

R/W

Number of transmitted ACK frames

nRxBeacon

R/W

Number of received beacon frames

nRxData

R/W

Number of received data frames

nRxAck

R/W

Number of received acknowledgment frames

nRxMacCmd

R/W

Number of received MAC command frames

nRxReserved

R/W

Number of received frames with reserved frame type

nRxOk

R/W

Number of received frames with CRC error

nRxIgnored

R/W

Number of frames received that are to be ignored

nRxBufFull

R/W

Number of received frames discarded because the RX buffer was full

lastRssi

RSSI of last received frame

maxRssi

Highest RSSI observed in the operation

beaconTimeStamp

11
12–15

Reserved

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Timestamp of last received beacon frame

Radio

1629

IEEE 802.15.4

www.ti.com

23.5.1.4 Other Structures and Bit Fields
Table 23-69 lists the receive queue entry configuration bit fields.
Table 23-69. Receive Queue Entry Configuration Bit Field
Bits

Bit Field Name

Description

bAutoFlushCrc

If 1, automatically remove packets with CRC error from RX queue.

bAutoFlushIgn

If 1, automatically remove packets that can be ignored according to
frame filtering from RX queue.

bIncludePhyHdr

If 1, include the received PHY header field in the stored packet;
otherwise discard it.

bIncludeCrc

If 1, include the received CRC field in the stored packet; otherwise
discard it. This requires pktConf.bUseCrc to be 1.

bAppendRssi

If 1, append an RSSI byte to the packet in the RX queue.

bAppendCorrCrc

If 1, append a correlation value and CRC result byte to the packet in
the RX queue.

bAppendSrcInd

If 1, append an index from the source matching algorithm.

bAppendTimestamp

If 1, append a timestamp to the packet in the RX queue.

Table 23-70 lists the CCA configuration bit fields.
Table 23-70. CCA Configuration Bit Field
Bits

Bit Field Name

Description

ccaEnEnergy

Enable energy scan as CCA source.

ccaEnCorr

Enable correlator-based carrier sense as CCA source.

ccaEnSync

Enable sync found-based carrier sense as CCA source.

ccaCorrOp

Operator to use between energy-based and correlator-based CCA:
0: Report busy channel if either ccaEnergy or ccaCorr are busy.
1: Report busy channel if both ccaEnergy and ccaCorr are busy.

ccaSyncOp

Operator to use between sync found based CCA and the others:
0: Always report busy channel if ccaSync is busy.
1: Always report idle channel if ccaSync is idle.

5–6

ccaCorrThr

Threshold for number of correlation peaks in correlator-based carrier
sense.

1630

Radio

Reserved

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

IEEE 802.15.4

www.ti.com

Table 23-71 lists the frame filtering configuration bit fields
Table 23-71. Frame Filtering Configuration Bit Field
Bits

Bit Field Name

Description

frameFiltEn

0: Disable frame filtering
1: Enable frame filtering

frameFiltStop

0: Receive all packets to the end
1: Stop receiving frame once frame filtering has caused the frame to be
rejected

autoAckEn

0: Disable auto ACK
1: Enable auto ACK

slottedAckEn

0: Nonslotted ACK
1: Slotted ACK

autoPendEn

0: Auto-pend disabled
1: Auto-pend enabled

defaultPend

The value of the pending data bit in auto ACK packets that are not
subject to auto-pend.

bPendDataReqOnly

0: Use auto-pend for any packet
1: Use auto-pend for data request packets only

bPanCoord

0: Device is not PAN coordinator
1: Device is PAN coordinator

8–9

maxFrameVersion

Reject frames where the frame version field in the FCF is greater than
this value.

10–12

fcfReservedMask

Value to be ANDed with the reserved part of the FCF; frame rejected if
result is nonzero.

13–14

modifyFtFilter

Treatment of MSB of frame type field before frame-type filtering:
0: No modification
1: Invert MSB
2: Set MSB to 0
3: Set MSB to 1

bStrictLenFilter

0: Accept acknowledgment frames of any length 5
1: Accept only acknowledgment frames of length 5

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1631

IEEE 802.15.4

www.ti.com

Table 23-72 lists the frame type filtering bit fields.
Table 23-72. Frame Type Filtering Bit Field
Bits

Bit Field Name

Description

bAcceptFt0Beacon

Treatment of frames with frame type 000 (beacon):
0: Reject
1: Accept

bAcceptFt1Data

Treatment of frames with frame type 001 (data):
0: Reject
1: Accept

bAcceptFt2Ack

Treatment of frames with frame type 010 (ACK):
0: Reject, unless running ACK receive command
1: Always accept

bAcceptFt3MacCmd

Treatment of frames with frame type 011 (MAC command):
0: Reject
1: Accept

bAcceptFt4Reserved

Treatment of frames with frame type 100 (reserved):
0: Reject
1: Accept

bAcceptFt5Reserved

Treatment of frames with frame type 101 (reserved):
0: Reject
1: Accept

bAcceptFt6Reserved

Treatment of frames with frame type 110 (reserved):
0: Reject
1: Accept

bAcceptFt7Reserved

Treatment of frames with frame type 111 (reserved):
0: Reject
1: Accept

Table 23-73 lists the short address entry structures.
Table 23-73. Short Address Entry Structure

1632

Byte Index

Field Name

Description

0–1

shortAddr

Short address of the entry

2–3

panID

PAN ID of the entry

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

IEEE 802.15.4

www.ti.com

Table 23-74 lists the extended address list structure.
Table 23-74. Extended Address List Structure
Byte Index

0–(4K

Field Name

(4K)–(8K

(8K)–(8K + 7)

Type

Description

srcMatchEn

R/W

Words with enable bits for each extAddrEntry; LSB of first
word corresponds to entry 0. The array size K = ceil (N /
32), where N is the number of entries (given by
numExtEntries, see
Table 23-59) and ceil denotes rounding upward.

srcPendEn

R/W

Words with pending data bits for each extAddrEntry; LSB
of first word corresponds to entry 0.

extAddrEntry[0]

Extended address number 0

extAddrEntry[n]

Extended address number n

Extended address number N 1 (last entry)

...
(8K + 8n)–(8K + 8n + 7)
...
[8K + 8(N

1)]–(8K + 8N + 7) extAddrEntry[N-1]

Table 23-75 lists the short address list structure.
Table 23-75. Short Address List Structure
Byte Index

0–(4K

Field Name

(4K)–(8K

(8K)–(8K + 3)

Type

Description

srcMatchEn

R/W

Words with enable bits for each shortAddrEntry; LSB of
first word corresponds to entry 0. The array size K = ceil (N
/ 32), where N is the number of entries (given by
numShortEntries, see Table 23-59) and ceil denotes
rounding upward.

srcPendEn

R/W

Words with pending data bits for each shortAddrEntry; LSB
of first word corresponds to entry 0.

shortAddrEntry[0]

Short address number 0; the entry is an address/PAN ID
pair as defined in Table 23-73.

shortAddrEntry[n]

Short address number n; the entry is an address/PAN ID
pair as defined in Table 23-73.

Short address number N 1 (last entry); the entry is an
address/PAN ID pair as defined in Table 23-73.

...
(8K + 4n)–(8K + 4n + 3)
...
[8K + 4(N

1)]–(8K + 4N + 3) shortAddrEntry[N-1]

Table 23-76 lists the receive correlation/CRC result bit fields.
Table 23-76. Receive Correlation/CRC Result Bit Field
Bits

Bit Field Name

Description

0–5

corr

The correlation value

bIgnore

1 if the packet must be rejected by frame filtering; 0 otherwise

bCrcErr

1 if the packet was received with CRC error; 0 otherwise

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1633

IEEE 802.15.4

www.ti.com

23.5.2 Interrupts
The interrupts to be used by the IEEE 802.15.4 commands are listed in Table 23-77. Each interrupt may
be enabled individually in the system CPU. Details for when the interrupts are generated are given in
Section 23.5.4.
Table 23-77. Interrupt Definitions Applicable to IEEE 802.15.4
Interrupt Number

Interrupt Name

Description

COMMAND_DONE

A background level radio operation command has
finished.

LAST_COMMAND_DONE

The last background level radio operation command
in a chain of commands has finished.

FG_COMMAND_DONE

A foreground radio operation command has finished

LAST_FG_COMMAND_DONE

The last foreground radio operation command in a
chain of commands has finished.

TX_DONE

Transmitted frame

TX_ACK

Transmitted automatic ACK frame

RX_OK

Frame received with CRC OK

RX_NOK

Frame received with CRC error

RX_IGNORED

Frame received with ignore flag set

RX_BUF_FULL

Frame received that did not fit in the TX queue

RX_ENTRY_DONE

TX queue data entry changing state to Finished

MODULES_UNLOCKED

As part of the boot process, the CM0 has opened
access to RF core modules and memories.

BOOT_DONE

The RF core CPU boot is finished.

INTERNAL_ERROR

The radio CPU has observed an unexpected error.

23.5.3 Data Handling
For all the IEEE 802.15.4 commands, data received over the air is stored in a receive queue.
Data to be transmitted is fetched from a buffer given in the transmit command.
23.5.3.1 Receive Buffers
A frame being received is stored in the receive buffer. First, a length byte or word is stored, if configured in
the RX entry, by config.lenSz, and calculated from the length received over the air and the configuration of
appended status information.
The format of the entry elements in the receive queue pointed to by pRxQ is given by the configuration
rxConfig defined in Section 23.6.1.4.
Following the length field, the received PHY header byte is stored if rxConfig.bIncludePhyHdr is 1. If a
length field is present, this byte is redundant except for the reserved bit. The received MAC header and
MAC payload is stored as received over the air. The MAC footer containing the 16-bit frame check
sequence is stored if rxConfig.bIncludeCrc is 1.
If rxConfig.bAppendRssi is 1, a byte indicating the received RSSI value is appended. If
rxConfig.bAppendCorrCrc is 1, a status byte of the type defined in Table 23-76 is appended. If
rxConfig.bAppendSrcInd is 1, a byte giving the index of the first source matching entry that matches the
header of the received packet is appended, or 0xFF if no match. If rxConfig.bAppendTimeStamp is 1, a
timestamp indicating the start of the frame is appended. This timestamp is a 4-byte number from the radio
timer. Though the timestamp is multibyte, no word-address alignment is made, so the timestamp must be
written and read byte-wise. The timestamp is captured when SFD is found, but is adjusted to reflect the
start of the frame (assuming 8 preamble bytes as per the standard), defined so that it corresponds to the
time of the start trigger used on the transmit side. The adjustment is defined in the syncTimeAdjust
firmware-defined parameter, and may be overridden.

1634

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

IEEE 802.15.4

www.ti.com

Figure 23-6 shows the format of an entry element in the RX queues.
Figure 23-6. RX Queue Entry Element (Stapled Fields are Optional)

0±2 bytes
Element
length

0 or 1 byte
PHY
header

0±125 bytes
MAC header
and payload

0 or 2 bytes 0 or 1 byte
MAC footer
RSSI
(FCS)

0 or 1 byte
Status

0 or 1 byte
Source
index

0 or 4 bytes
Timestamp

23.5.3.2 Transmit Buffers
In the transmit operation, a pointer to a buffer containing the payload is given by pPayload. The length of
this buffer is given separately by payloadLen. The contents of the transmit buffer is given by the txOpt
parameter. The transmit buffer always contains the MAC header and MAC payload. If
txOpt.bIncludePhyHdr is 1, the buffer also includes the byte to be transmitted as a PHY header as the first
byte in the buffer. If txOpt.bIncludeCrc is 1, the last 2 bytes of the buffer are transmitted as a CRC instead
of the CRC being calculated automatically.

23.5.4 Radio Operation Commands
Before running any radio operation command described in this document, the radio must be set up in
IEEE 802.15.4 mode using the command CMD_RADIO_SETUP. Otherwise, the operation ends with an
error.
In IEEE 802.15.4 mode, the radio CPU accepts two levels of radio operation commands. Operations can
run in the background level or in the foreground level. Each operation can run in only one of these levels.
Operations in the foreground level normally require a background-level operation running at the same
time.
The background-level operations are the receive and energy detect scan operations. Only one of these
operations can run at a time. The foreground-level operations are the CSMA-CA operation, the receive
ACK operation, the transmit operation, the abort background level operation, and the modify radio setup
operation. These can be entered as one command or a command chain, even if a background-level
operation is running. The CSMA-CA and receive ACK operations run simultaneously with the backgroundlevel operation. The transmit operation causes suspension of the background level operation until the
transmission is done. Table 23-78 shows the allowed combinations of background and foreground-level
operations. Violation of these combinations causes an error when the foreground-level command is about
to start, signaled by the ERROR_WRONG_BG status in the status field of the foreground-level command
structure.
Table 23-78. Allowed Combinations of Foreground and Background Level Operations
Background Level Operation

Foreground Level Operation

None

CMD_IEEE_RX

CMD_IEEE_ED_SCAN

None

Allowed

CMD_IEEE_TX

Allowed1

Allowed

CMD_IEEE_CSMA

Forbidden

Allowed

CMD_IEEE_RX_ACK

Forbidden

Allowed

Forbidden

CMD_IEEE_ABORT_BG

Allowed2

Allowed

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1635

IEEE 802.15.4

www.ti.com

A non-15.4 radio operation may not be run simultaneously with a 15.4 radio operation; if a non-15.4 radio
operation is entered while a 15.4 operation is running on either level, a scheduling error occurs. Chains of
15.4 and non-15.4 operations can be created, however.
When a foreground-level operation finishes, an FG_COMMAND_DONE interrupt is raised. If the command
was the last one in a chain, a LAST_FG_COMMAND_DONE interrupt is raised as well (see
Table 23-77). Background-level operations use the common interrupts, COMMAND_DONE and
LAST_COMMAND_DONE (see Table 23-77).
The status field of the command structure is updated during the operation. When submitting the
command, the system CPU writes this field with a state of IDLE. During the operation, the radio CPU
updates the field to indicate the operation mode. When the operation is done, the radio CPU writes a
status indicating that the command has finished. Table 23-79 lists the status codes for IEEE 802.15.4
radio operation.
Table 23-79. IEEE 802.15.4 Radio Operation Status Codes
Number

Name

Description

0x0000

IDLE

Operation not started

0x0001

PENDING

Waiting for start trigger

0x0002

ACTIVE

Running operation

0x2001

IEEE_SUSPENDED

Operation suspended

0x2400

IEEE_DONE_OK

Operation ended normally

0x2401

IEEE_DONE_BUSY

CSMA-CA operation ended with failure

0x2402

IEEE_DONE_STOPPED

Operation stopped after stop command

0x2403

IEEE_DONE_ACK

ACK packet received with pending data bit cleared

0x2404

IEEE_DONE_ACKPEND

ACK packet received with pending data bit set

0x2405

IEEE_DONE_TIMEOUT

Operation ended due to time-out

0x2406

IEEE_DONE_BGEND

FG operation ended because necessary background level
operation ended

0x2407

IEEE_DONE_ABORT

Operation aborted by command

0x0806

ERROR_WRONG_BG

Foreground level operation is not compatible with running
background level operation

0x2800

IEEE_ERROR_PAR

Illegal parameter

0x2801

IEEE_ERROR_NO_SETUP

Radio was not set up in IEEE 802.15.4 mode

0x2802

IEEE_ERROR_NO_FS

Synthesizer was not programmed when running RX or TX

0x2803

IEEE_ERROR_SYNTH_PROG

Synthesizer programming failed

0x2804

IEEE_ERROR_RXOVF

RX overflow observed during operation

0x2805

IEEE_ERROR_TXUNF

TX underflow observed during operation

Operation Not Finished

Normal Operation Ending

Operation Ending With Error

The conditions for giving each status are listed for each operation. Some of the error causes listed in
Table 23-79 are not repeated in these lists. In some cases, general error causes described in Section 23.3
may occur. In all of these cases, the result of the operation as defined in Section 23.3 is ABORT.

1636

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

IEEE 802.15.4

www.ti.com

23.5.4.1 RX Operation
The receive radio operation is a background-level operation, started with the CMD_IEEE_RX command
and using the command structure given in Table 23-59.
At the start of an RX operation, the radio CPU waits for the start trigger, then programs the frequency
based on the channel parameter. If the channel is 0xFF, the operation keeps running on an alreadyconfigured channel. This requires that the operation follows another receive operation or a synthesizer
programming operation. If the frequency synthesizer is not running, the operation ends with an error. After
programming the frequency, the radio CPU configures the receiver to receive IEEE 802.15.4 packets.
When the demodulator obtains sync on a frame, the PHY header is read first. The 7 LSBs of this byte give
the frame length. The further treatment depends on the setting of frameFiltOpt. If frameFiltOpt.frameFiltEn
is 1, further frame filtering is done as explained in the following subsections. If frameFiltOpt.frameFiltEn is
0, no frame filtering is done.
The number of bytes given by the received PHY header are received and stored in the receive queue
given by pRxQ. As explained in Section 23.6.3.1, the format depends on rxConfig. The last 2 bytes of the
PHY payload are the FCS, or CRC, for the packet. These bytes are checked according to the FCS
specification, and the further treatment depends on the CRC result.
If there is a CRC error and rxConfig.bAutoFlushCrc is 1, the packet is discarded from the RX buffer. If
there is no available RX buffer with enough available space to hold the received packet, the received data
is discarded. If frameFiltOpt.frameFiltStop is 1, the reception stops, otherwise the packet is received so
that the CRC can be checked.
23.5.4.1.1 Frame Filtering and Source Matching
If frameFiltOpt.frameFiltEn is 1, frame filtering and source matching are performed as described in this
section. The frame filtering may have several purposes:
• Distinction between different packet types
• Rejection of packets with a nonmatching destination address
• Rejection of packets with unknown version or illegal fields
• Automatic identification of source address
• Automatic acknowledgment transmission
• Automatic insertion of pending data bit based on source address
23.5.4.1.1.1 Frame Filtering
When frame filtering is enabled, the MAC header of the packet is investigated by the radio CPU. The
frame control field (FCF) is checked first. The frame type subfield is the first subfield of the FCF to be
checked, and determines the further processing. The MSB of the frame type is processed according to
frameFiltOpt.modifyFtFilter before the check is made. The result of this modification is used only when
checking, not when storing the FCF in the RX queue entry. For each of the eight possible values of the
frame type field (including four reserved fields), the frame can be set up to be accepted or rejected. This is
controlled by the bits of frameTypes. If the frame type is Acknowledgment (010b) and a CMD_RX_ACK
operation is running in the foreground, the packet is processed further even if frameTypes.bAcceptFt2Ack
is 0. In that case, Section 23.5.4.5 gives more details on the processing.
Filtering is performed on the Frame Version and Reserved subfields. If the frame version is greater than
frameFiltOpt.maxFrameVersion, the frame is rejected.
If the Reserved subfield ANDed with frameFiltOpt.fcfReservedMask is nonzero, the frame is rejected. The
addressing fields are checked to see if the frame must be accepted or not. This filtering follows the rules
for third-level filtering (refer to the IEEE 802.15.4 standard). When checking against the local address, the
localExtAddr or localShortAddr field is used, and when checking against the local PAN ID, the localPanID
field is used.
If frameFiltOpt.bStrictLenFilter is 1 and the frame type indicates that the frame is an acknowledgment
frame, the frame is rejected if the length of the PHY payload is not 5, which is the length of a correctly
formulated ACK frame.
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1637

IEEE 802.15.4

www.ti.com

If frameFiltOpt.frameFiltStop is 1 and the frame filtering gives the conclusion that the frame is to be
rejected, reception stops and the radio returns to sync search. Otherwise, the frame is received to the end.
The radio CPU checks the header to see if an acknowledgment is to be transmitted. This gives a
preliminary result; the actual transmission of the ACK depends on the status at the end of the frame. The
condition for transmitting an acknowledgment frame is given in Section 23.5.4.1.3.
23.5.4.1.1.2 Source Matching
Source matching is performed on frames accepted by the frame filtering with a source address present. If
the source address was an extended address, the received address is compared against the entries in the
list pExtEntryList. If the source address was a short address, the received address and source pan ID are
compared against the entries in the list pShortEntryList.
The number of entries that the lists can hold is given by numExtEntries and numShortEntries. If either of
these values is 0, no source matching is performed on addresses of the corresponding type, and the
corresponding pointer is NULL. The lists start with source mapping enable bits, srcMatchEn, and continue
with pending enable bits, srcPendEn, followed by the list entries, see Table 23-73 and Table 23-74. The
enable bits consist of the number of 32-bit words needed to hold an enable bit for each entry in the list.
For each entry where the corresponding srcMatchEn bit is 1, the entry is compared against the received
source address for extended addresses, or against the received source address and PAN ID for short
addresses. If a match is found, the index is stored, and reported back in the message footer if configured
(see Section 23.6.3.1). If no match is found, the index reported back is 0xFF.
The source matching procedure may also be used to find the pending data bit to be transmitted in an
auto-acknowledgment frame (see Section 23.5.4.1.3). If frameFiltOpt.autoPendEn is 1 and a source match
was found, the pending data bit is set to the value of the bit in srcPendEn corresponding to the index of
the match. If no match was found or if frameFiltOpt.autoPendEn is 0, the pending data bit is set equal to
frameFiltOpt.defaultPend. If frameFiltOpt.bPendDataReqOnly is 1, the radio CPU investigates the frame to
determine if it is a MAC command frame with the command frame identifier set to a Data Request. If not,
the pending data bit of an auto ACK is set to 0, regardless of the source matching result and the value of
frameFiltOpt.defaultPend.
23.5.4.1.2 Frame Reception
After frame filtering is done, the rest of the packet is received and stored in the receive queue. The last 2
bytes of the PHY packet are the MAC footer, or FCS, which is a checked CRC. The CRC is stored in the
queue only if rxConfig.bIncludeCrc is 1.
The status of the received frame depends on the frame filtering result and the CRC result. Two status bits,
bCrcErr and bIgnore, must be maintained. If configured, these 2 bits are present in the Status byte of the
RX queue entry. The bCrcErr bit is 1 if the frame had a CRC error, and 0 otherwise. The bIgnore bit is 1 if
frame filtering is enabled and the frame was rejected by frame filtering, and 0 otherwise.
NOTE: If frameFiltOpt.frameFiltStop is 1, frames with bIgnore equal to 1 are never observed,
because the reception is stopped and the received bytes are not stored in the queue. If
rxConfig.bAutoFlushCrc is 1, packets with bCrcErr equal to 1 are removed from the queue
after reception; if rxConfig.bAutoFlushIgn is 1, packets with bIgnore equal to 1 are removed
from the queue after reception.

After a packet has been received, an interrupt is raised and one of the counters in pOutput is incremented.
Table 23-80 lists these conditions.
Table 23-80. Conditions for Incrementing Counters and Raising Interrupts for RX Operation
Condition

Counter Incremented

Interrupt Generated

Frame received with CRC OK and frame filtering disabled

nRXData

RX_OK

Frame received with CRC error

nRXNok

RX_NOK

Frame received that did not fit in the RX queue

nRXBufFull

RX_BUF_FULL

Beacon frame received with CRC OK and bIgnore = 0

nRXBeacon

RX_OK

1638Radio

IEEE 802.15.4

www.ti.com

Table 23-80. Conditions for Incrementing Counters and Raising Interrupts for RX
Operation (continued)
Condition

Counter Incremented

Interrupt Generated

ACK frame received with CRC OK and bIgnore = 0

nRXAck

RX_OK

Data frame received with CRC OK and bIgnore = 0

nRXData

RX_OK

MAC command frame received with CRC OK and bIgnore = 0

nRXMacCmd

RX_OK

Frame with reserved frame type received with CRC OK and
bIgnore = 0

nRXReserved

RX_OK

Frame received with CRC OK and bIgnore = 1

nRXIgnored

RX_IGNORED

The first RX data entry in the RX queue changed state to finished

—

RX_ENTRY_DONE

When a frame has been received, the RSSI observed while receiving the frame is written to
pOutput->lastRssi. If the frame was a beacon frame accepted by the frame filtering and with CRC OK, the
timestamp at the beginning of the frame is written to pOutput ->beaconTimeStamp. If the timestamp is
appended to the RX entry element (see Section 23.6.3.1), these two timestamps are the same for a
beacon frame.
After a packet has been received, the radio CPU either restarts sync search or sends an acknowledgment
frame. The conditions for the latter are as given in Section 23.5.4.1.3.
23.5.4.1.3 ACK Transmission
After a packet has been received, the radio CPU initiates transmission of an acknowledgment frame,
given that all of the following conditions are met:
• Auto ACK is enabled by frameFiltOpt.autoAckEn = 1.
• The frame is accepted by frame filtering (bIgnore = 0).
• The frame is a data frame or a MAC command frame.
• The destination address is not the broadcast address.
• The ACK request bit of the FCF is set.
• The CRC check is passed (bCrcErr = 0).
• The frame fits in the receive queue.
The transmit time of the ACK packet is timed by the radio CPU, depending on frameFiltOpt.slottedAckEn.
If this bit is 0, the ACK packet is transmitted 192 µs after the end of the received packet. Otherwise,
slotted ACK is used. Assume that the received packet started on a backoff-slot boundary. The ACK frame
then starts a whole number of backoff periods later than the start of the received frame, at the first backoff
boundary following at least one TurnaroundTime-symbol period after the end of the received frame.
The contents of the automatically transmitted ACK frame are as follows:
• The PHY header is 0x05.
• The PHY payload consists of a 3-byte MAC header and a 2-byte MAC footer.
• The MAC header starts with the 2-byte FCF with the following fields:
– The Frame Type subfield is 010b.
– The Frame Pending subfield is set as described in Section 23.5.4.1.1.2.
– The remaining subfields are set to all 0s.
• The next byte in the MAC header is the sequence number, which is set equal to the sequence number
of the received frame.
• The MAC footer is the FCS, which is calculated automatically.
After the ACK frame has been transmitted, a TX_ACK interrupt is raised. The radio CPU then enables the
receiver again.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1639

IEEE 802.15.4

www.ti.com

23.5.4.1.4 End of Receive Operation
The receive operation can end as a result of the end trigger given by endTrigger and endTime, or by a
command. The commands that can end the receive operation are the immediate commands
CMD_ABORT and CMD_STOP, and the foreground-level radio operation command
CMD_IEEE_ABORT_BG. The end-trigger and the CMD_STOP command cause the receiver to keep
running until the end of the frame, or until the reception would otherwise be stopped if observed while a
packet was being received. The CMD_ABORT and CMD_IEEE_ABORT_BG commands cause the
receiver to stop as quickly as the implementation allows.
A receive operation ends through one of the causes listed in Table 23-81. The status field of the command
structure after the command has ended indicates the reason why the operation ended. In all cases, a
COMMAND_DONE interrupt is raised. In each case, the result is indicated as TRUE, FALSE, or ABORT.
This decides whether to start the next command (if any) indicated in pNextOp, or to return to an IDLE
state. Before the receive operation ends, the radio CPU writes the maximum observed RSSI during the
receive operation to pOutput->maxRssi.
If a transmit operation is started in the foreground, the receive operation is suspended. The receiver stops
as when aborted, but the synthesizer is left on to the extent possible when switching to transmit mode.
When the receiver has stopped, the status field of the command structure is set to IEEE_SUSPENDED.
When the transmit command is done, the receiver restarts and the status field of the command structure is
reset to RUNNING.
Table 23-81. End of Receive Operation
Condition

Status Code

Result

Observed end trigger and finished any ongoing reception

IEEE_DONE_OK

TRUE

Received CMD_STOP

IEEE_DONE_STOPPED

FALSE

Received CMD_ABORT or CMD_IEEE_ABORT_BG

IEEE_DONE_ABORT

ABORT

Observed illegal parameter

IEEE_ERROR_PAR

ABORT

23.5.4.1.5 CCA Monitoring
While the receiver is running, the radio CPU monitors some signals for use in clear-channel assessment.
This monitoring is controlled by ccaOpt. There are three sources for CCA: RSSI above level (ccaEnergy),
carrier sense based on the correlation value (ccaCorr), and carrier sense based on sync found (ccaSync).
Each of these may have the state BUSY, IDLE, or INVALID.
The RSSI above-level is maintained by monitoring the RSSI. If the RSSI is greater than or equal to
ccaRssiThr, ccaEnergy is busy. If the RSSI is smaller than ccaRssiThr, ccaEnergy is IDLE. When an RSSI
calculation has not yet been completed because the receiver started, ccaEnergy is INVALID.
The carrier-sense monitoring based on correlation value uses correlation peaks as defined for use in the
SFD search algorithm in the receiver. If the number of correlation peaks observed in the last 8-symbol
periods (32 µs) is greater than ccaOpt.corrThr, ccaCorr is BUSY; otherwise, ccaCorr is IDLE. The value of
ccaOpt.corrThr can be from 0 to 3. While the receiver is receiving a frame, ccaCorr is BUSY regardless of
the observed correlation peaks. If the time since the receiver started is less than 8 symbol periods and the
number of correlation peaks observed since the receiver started is less than or equal to ccaOpt.corrThr,
ccaCorr is INVALID.
The carrier-sense monitoring based on sync found is maintained by the radio CPU as follows. If sync is
obtained on the receiver, the radio CPU checks the PHY header to find the frame length. The radio CPU
considers the channel to be busy for the duration of this frame. This check is done even if reception of the
frame is stopped due to the frame filtering and sync search is restarted. If sync is found again while the
channel is viewed as BUSY, the channel is viewed as BUSY until both these frames have ended
according to the observed frame lengths. The INVALID state is not used for ccaSync.
If the radio is transmitting an ACK or is suspended for running a TX operation, ccaEnergy, ccaCorr, and
ccaSync are all BUSY.

1640

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

IEEE 802.15.4

www.ti.com

The overall CCA state ccaState depends on the ccaEnEnergy, ccaEnCorr, and ccaEnSync bits of ccaOpt
together with the ccaCorrOp and ccaSyncOp bits. The following rules apply for finding the ccaState
(ccaTmp is a helper state in the description):
• If ccaEnEnergy = 0 and ccaEnCorr = 0 and ccaEnSync = 0, then ccaState = IDLE
• If ccaEnEnergy = 1 and ccaEnCorr = 0, then ccaTmp = ccaEnergy
• If ccaEnEnergy = 0 and ccaEnCorr = 1, then ccaTmp = ccaCorr
• If ccaEnEnergy = 1 and ccaEnCorr = 1 and ccaCorrOp = 0, then:
– If either ccaEnergy or ccaCorr is BUSY, then ccaTmp = BUSY
– Otherwise, if either ccaEnergy or ccaCorr is INVALID, then ccaTmp = INVALID
– Otherwise, ccaTmp = IDLE
• If ccaEnEnergy = 1 and ccaEnCorr = 1 and ccaCorrOp = 1, then:
– If either ccaEnergy or ccaCorr is IDLE, then ccaTmp = IDLE
– Otherwise, if either ccaEnergy or ccaCorr is Invalid, then ccaTmp = INVALID
– Otherwise, ccaTmp = BUSY
• If ccaEnEnergy = 0 and ccaEnCorr = 0 and ccaEnSync = 1, then ccaState = ccaSync
• Otherwise, if ccaEnSync = 1 and ccaSyncOp = 0, then:
– If either ccaTmp or ccaSync is BUSY, then ccaState = BUSY
– Otherwise, if ccaTmp is Invalid, then ccaState = INVALID
– Otherwise, ccaState = IDLE
• Otherwise, if ccaEnSync = 1 and ccaSyncOp = 1, then:
– If either ccaTmp or ccaSync is IDLE, then ccaState = IDLE
– Otherwise, if ccaTmp is INVALID, then ccaState = INVALID
– Otherwise, ccaState = BUSY
The ccaSync CCA state is required to be IDLE for the overall CCA state to be IDLE, according to the
IEEE 802.15.4 standard. Thus, to comply, ccaEnSync is 1 and cceSyncOp is 0.
CCA mode 1, as defined in the IEEE 802.15.4 standard, is implemented by setting ccaEnEnergy = 1 and
ccaEnCorr = 0. CCA mode 2 is implemented by setting ccaEnEnergy = 0 and ccaEnCorr = 1. CCA mode
3 is implemented by setting ccaEnEnergy = 1 and ccaEnCorr = 1. With CCA mode 3, ccaCorrOp is
allowed to be either 0 or 1; this distinguishes between the logical operator AND (1) and OR (0) as
described in the IEEE 802.15.4 standard.
The CCA states and the current RSSI can be read by the system CPU by issuing the immediate
command CMD_IEEE_CCA_REQ. If a CMD_IEEE_CSMA operation is running in the foreground, the
radio CPU also monitors the CCA autonomously.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1641

IEEE 802.15.4

www.ti.com

23.5.4.2 Energy Detect Scan Operation
The energy detect scan radio operation is a background-level operation that starts with the
CMD_IEEE_ED_SCAN command and uses a command structure as given in Table 23-60.
At the start of an RX operation, the radio CPU waits for the start trigger, then programs the frequency
based on the channel parameter. If the channel is 0xFF, the operation keeps running on an alreadyconfigured channel. This requires that the operation follows another receive operation or a synthesizer
programming operation. If the frequency synthesizer is not running, the operation ends with an error. After
programming the frequency, the radio CPU configures the receiver to receive IEEE 802.15.4 packets, but
it does not store any received data.
While the receiver is running, CCA is updated as described in Section 23.5.4.1.5. When the demodulator
obtains sync on a frame, the PHY header is read. This is used only to determine the carrier sense based
on sync found, and sync search restarts immediately afterwards.
The energy detect scan operation ends under the same conditions as the RX operation, as described in
Section 23.5.4.1.4. Before the operation ends, the radio CPU writes the maximum-observed RSSI during
the energy detect scan operation to maxRssi.
23.5.4.3 CSMA-CA Operation
The CSMA-CA operation is a foreground-level operation that runs on top of a receive or energy-detect
scan operation. If run on top of an energy-detect scan operation, this does not perform the energy-detect
scan procedure, but starts a receiver without having to receive packets. This operation starts with the
CMD_IEEE_CSMA command, and uses the command structure given in Table 23-61.
At the start of a CSMA-CA operation, the radio CPU waits for the start trigger.
The radio CPU maintains a variable CW, which initializes to csmaConfig.initCW.
If remainingPeriods is nonzero at the start of the command, the radio CPU delays for that number of
backoff periods (default 320 µs) measured from the start trigger before proceeding. Otherwise, the radio
CPU draws a pseudo-random number in the range 0 to 2(BE)–1, where BE is given by (Table 23-61). The
radio CPU then waits that number of backoff periods from the start trigger before proceeding.
After this wait time, the radio CPU checks the CCA state from the background-level operation, as
described in Section 23.5.4.1.5. If the CCA state was INVALID, the radio CPU waits before trying again. If
csmaConfig.bSlotted = 1, the wait is for one backoff period, otherwise it waits until an RSSI result is
available. If the CCA state was IDLE, the radio CPU decrements CW by 1, and if this results in a value of
0, the CSMA-CA operation is successful. If this results in a nonzero value, the radio CPU waits one
backoff period timed from the end of the wait time, and then checks the CCA state again as described
previously.

1642

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

IEEE 802.15.4

www.ti.com

If the channel was BUSY when the CCA state was checked, the radio CPU updates the variables as
follows:
CW = csmaConfig.initCW; NB + = 1; BE + = min (BE + 1, macMaxBE);
If NB after this update is greater than macMaxCSMABackoffs, the CSMA-CA operation ends with failure.
Otherwise, the radio CPU draws a random number of backoff periods to wait as described previously, and
proceeds as before. If csmaConfig.bSlotted = 1, the wait is from the next backoff period after the end of
the previous wait time; otherwise, the wait is from a configurable time after the end of the previous wait
time.
Figure 23-7 shows the flow chart for the CSMA-CA operation.
In addition to the CSMA-CA operation ending with success or failure as previously described, the
operation can end as a result of the end trigger given by endTrigger and endTime, or by a command. The
commands that can end the CSMA-CA operation are the immediate commands CMD_ABORT,
CMD_STOP, CMD_IEEE_ABORT_FG, and CMD_IEEE_STOP_FG. When the CSMA-CA operation ends,
the radio CPU writes lastTimeStamp with the timer value at the end of the most recent wait period before
a CCA check was done, and lastRssi with the RSSI value at that time. If the operation ended because of a
time-out or stop command, the radio CPU writes remainingPeriods with the number of backoff periods
remaining of the wait time. Otherwise, the radio CPU writes remainingPeriods to 0.
The pseudo-random algorithm is based on a maximum-length 16-bit linear-feedback shift register (LFSR).
The seed is as provided in randomState. When the operation ends, the radio CPU writes the current state
back to this field. If randomState is 0, the radio CPU self-seeds by initializing the LFSR to the 16 LSBs of
the RAT. There is some randomness to this value, but this is limited, especially for slotted CSMA-CA, and
seeding with a true-random number (or a pseudo-random number based on a true-random seed) by the
system CPU is therefore recommended. If the 16 LSBs of the RAT are all 0, another fixed value is
substituted.
Depending on csmaConfig.rxOffMode, the underlying RX operation may be suspended during the backoff
before another CCA check, if there is enough time for it. The different values have the following meaning:
• rxOffMode = 0: The radio stays on during CSMA backoffs.
• rxOffMode = 1: If a frame is being received, an ACK being transmitted, or in the transition between
those, the radio stays on. Otherwise, the radio switches off until the end of the backoff period.
• rxOffMode = 2: If a frame is being received, an ACK is being transmitted, or is in the transition between
those, the radio stays on until the packet has been fully received and the ACK has been transmitted if
applicable. After that, the radio switches off until the end of the backoff period.
• rxOffMode = 3: The radio switches off immediately at the beginning of a backoff period. This aborts a
frame being received or an ACK being transmitted. The radio remains switched off until the end of the
backoff period.
If the radio switches off this way, the receiver restarts sufficiently early for the next CCA operation to be
done, and the radio only switches off it there is sufficient time. This feature can be used for power saving
in systems that do not always need to be in RX. All modes except mode 0 may cause frames to be lost, at
increasing probability.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1643

IEEE 802.15.4

www.ti.com

Figure 23-7. Flow Chart for CSMA-CA Operation
CMD_IEEE_CSMA

CW = initCW

Wait for start event
N

Slotted?

remainingPeriods = 0?

Wait for next backoff
period boundary
Y

remainingPeriods =
random(2BEÌ1)

Wait remainingPeriods
backoff periods

Wait 1 backoff period

Check CCA state

Wait for RSSI update

CCA state INVALID?

Slotted?

Y
Y

CCA state IDLE?

CW = initCW,
NB = NB+1,
BE = min(BE+1,
macMaxBE)

NB >
macMaxCSMABackoffs?

Failure

1644

Radio

CW = CWÌ1

N
N

CW = 0?

Success

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

IEEE 802.15.4

www.ti.com

For operation according to IEEE 802.15.4, the parameters must be initialized as follows before starting a
new CSMA-CA operation:
• randomState must be set to a random value.
• csmaConfig.initCW must be set to 2 for slotted CSMA-CA and 1 for unslotted CSMA-CA.
• csmaConfig.bSlotted must be set to 1 for slotted CSMA-CA and 0 for unslotted CSMA-CA.
• NB must be set to 0.
• BE must be set to macMinBE, except for slotted CSMA-CA with battery-life extension, where BE must
be set to min (2, macMinBE).
• remainingPeriods must be set to 0.
• macMaxBE and macMaxCSMABackoffs must be set to their corresponding MAC PIB attribute.
For slotted CSMA-CS, startTrigger must be set up to occur on a backoff-slot boundary. For slotted CSMACA, the endTrigger must be set up to occur at the latest time that the transaction can be completed within
the superframe, as specified in the IEEE 802.15.4 standard. If the CSMA-CA ends due to time-out, the
CSMA can be restarted without modifying the parameters (except possibly the end time) at the next
superframe.
Table 23-82 lists the causes of a CSMA-CA operation end. After the command has ended, the status field
of the command structure (2 status bytes listed in Table 23-8) indicates why the operation ended. In all
cases, an FG_COMMAND_DONE interrupt is raised. In each case, it is indicated if the result is TRUE,
FALSE, or ABORT. This result indicates whether to start the next command (if any) in pNextOp, or to
return to an IDLE state.
Table 23-82. End of CSMA-CA Operation
Condition

Status Code

Result

CSMA-CA operation finished with success

IEEE_DONE_OK

TRUE

CSMA-CA operation finished with failure

IEEE_DONE_BUSY

FALSE

End trigger occurred

IEEE_DONE_TIMEOUT

FALSE

Received CMD_STOP or CMD_IEEE_STOP_FG

IEEE_DONE_STOPPED

FALSE

Received CMD_ABORT or CMD_IEEE_ABORT_FG

IEEE_DONE_ABORT

ABORT

Background operation ended

IEEE_DONE_BGEND

ABORT

Observed illegal parameter

IEEE_ERROR_PAR

ABORT

When the operation ends, the time of the last CCA check (that is, the time written into lastTimeStamp) is
defined as event 1, and may be used for timing subsequent chained operations.
23.5.4.4 Transmit Operation
The transmit operation is a foreground-level operation that transmits one packet. The operation is started
with the CMD_IEEE_TX command, and uses the command structure given in Table 23-62.
When the radio CPU receives the command, it waits for the start trigger. Any background-level operation
keeps running during this wait time. At the start trigger, the radio CPU suspends the receiver and
configures the transmitter. The synthesizer should be powered and calibrated. Therefore, if no
background-level operation is running, a calibrate synthesizer command must precede the TX operation. If
the frequency synthesizer is not running, the operation ends with an error.
The transmitter transmits the payload found in the buffer pointer to pPayload, which consists of
payloadLen bytes. If txOpt.payloadLenMsb is nonzero, this field is multiplied by 256 and added to
payloadLen to create (for test purposes) a long frame that is not compliant with IEEE 802.15.4. If
txOpt.bIncludePhyHdr is 0, the radio CPU inserts a PHY header automatically, calculated from the
payload length. Otherwise, no PHY header is inserted by the radio CPU, so for IEEE 802.15.4
compliance, the first byte in the payload buffer must be the PHY header. The payload is then transmitted
as found in the payload buffer. If txOpt.bIncludeCrc is 0, the radio CPU appends two CRC bytes,
calculated according to the IEEE 802.15.4 standard. Otherwise, no CRC is appended, so for IEEE
802.15.4 MAC compliance, the last 2 bytes in the payload buffer must be the MAC footer. The transmit
operation can be ended by one of the immediate commands CMD_ABORT, CMD_STOP,
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1645

IEEE 802.15.4

www.ti.com

CMD_IEEE_ABORT_FG, or CMD_IEEE_STOP_FG. If CMD_ABORT or CMD_IEEE_ABORT_FG is
received, the transmission ends as soon as possible in the middle of the packet. If CMD_STOP or
CMD_IEEE_STOP_BG is received while the radio CPU is waiting for the start trigger, the operation ends
without any transmission; otherwise, the transmission is finished, but the end status and result differ as
explained in the following.
When transmission of the packet starts, the trigger RAT time used for starting the modem is written to the
timeStamp field by the radio CPU. This timestamp is delayed by the firmware-defined parameter
startToTXRatOffset, compared to the configured start time of the CMD_IEEE_TX command. If the
transmitter and receiver have synchronized RAT timers, this timestamp is the same as the timestamp
appended to the RX entry element, as in Section 23.6.3.1, although with estimation uncertainty on the
receiver side.
When the operation ends, the end time of the transmitted frame is defined as event 1, and may be used
for timing subsequent chained operations.
Table 23-83 lists the causes of a transmit operation end. After the command has ended, the status field of
the command structure (2 status bytes listed in Table 23-8) indicates why the operation ended. In all
cases, an FG_COMMAND_DONE interrupt is raised. In each case, it is indicated if the result is TRUE,
FALSE, or ABORT. This indicates whether to start the next command (if any) in pNextOp, or to return to
an IDLE state.
Table 23-83. End of Transmit Operation
Condition

Status Code

Result

Packet transmitted

IEEE_DONE_OK

TRUE

Received CMD_STOP or CMD_IEEE_STOP_FG, then finished
transmitting if started

IEEE_DONE_STOPPED

FALSE

Received CMD_ABORT or CMD_IEEE_ABORT_FG

IEEE_DONE_ABORT

ABORT

Observed illegal parameter

IEEE_ERROR_PAR

ABORT

23.5.4.5 Receive Acknowledgment Operation
The receive-ACK operation is a foreground-level operation that runs on top of a receive operation. The
operation starts with the CMD_IEEE_RX_ACK command, and uses the command structure listed in
Table 23-63.
At the start of a receive-ACK operation, the radio CPU waits for the start trigger. If the receiver was
suspended due to a TX operation before the receive-ACK operation, the background-level RX operation is
not resumed until the start trigger occurs.
While the receive-ACK operation is running, the background-level RX operation runs normally. However,
in addition to looking for the packets, the operation looks for ACK packets with the sequence number
given in seqNo. The packet is stored in the receive queue only if configured in the background-level
receive operation (frameTypes.bAcceptFt2Ack = 1). If ACK packets are filtered out in the background RX
operation, for an ACK packet the sequence number is received, and if it matches, also the FCS.
If the ACK packet with the requested sequence number is received, the FCS is checked. If the CRC is
OK, the receive-ACK operation ends, otherwise it continues. If the ACK is received OK, the pending-data
bit of the header is checked.
In addition to the receive-ACK operation ending after receiving the ACK as described previously, the
operation can end as a result of the end trigger given by endTrigger and endTime, or by a command. The
commands that can end the receive-ACK operation are the immediate commands CMD_ABORT,
CMD_STOP, CMD_IEEE_ABORT_FG, and CMD_IEEE_STOP_FG.
A receive-ACK operation ends due to one of the causes listed in Table 23-84. After the command has
ended, the status field of the command structure (2 status bytes listed in Table 23-8) indicates why the
operation ended. In all cases, an FG_COMMAND_DONE interrupt is raised. In each case, it is indicated if
the result is TRUE, FALSE, or ABORT. This indicates whether to start the next command (if any) in
pNextOp, or to return to an IDLE state.

1646

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

IEEE 802.15.4

www.ti.com

Table 23-84. End of Receive ACK Operation
Condition

Status Code

Result

Requested ACK successfully received with pending data bit
cleared

IEEE_DONE_ACK

FALSE

Requested ACK successfully received with pending data bit set

IEEE_DONE_ACKPEND

TRUE

End trigger occurred

IEEE_DONE_TIMEOUT

FALSE

Received CMD_STOP or CMD_IEEE_STOP_FG

IEEE_DONE_STOPPED

FALSE

Received CMD_ABORT or CMD_IEEE_ABORT_FG

IEEE_DONE_ABORT

ABORT

Background operation ended

IEEE_DONE_BGEND

ABORT

Observed illegal parameter

IEEE_ERROR_PAR

ABORT

23.5.4.6 Abort Background-Level Operation Command
The abort background-level operation command is a foreground-level command that stops the command
running in the background. The abort background-level operation command is defined as a foregroundoperation command so that it has a start time, and so that it can be chained with other foregroundoperation commands. The command is executed with the CMD_IEEE_ABORT_BG command and uses a
command structure with only the minimum set of parameters.
At the start of an abort background-level operation, the radio CPU waits for the start trigger, then aborts
the ongoing background-level receive or energy-detect scan operation.
The operation may be stopped by a command while waiting for the start trigger. The commands that can
stop the operation are CMD_ABORT, CMD_STOP, CMD_IEEE_ABORT_FG, and CMD_IEEE_STOP_FG.
The first two commands cause the background-level operation to stop regardless.
An abort background-level operation ends due to one of the causes listed in Table 23-85. After the
command has ended, the status field of the command structure (2 status bytes listed in Table 23-8)
indicates why the operation ended. In all cases, an FG_COMMAND_DONE interrupt is raised. In each
case, it is indicated if the result is TRUE, FALSE, or ABORT. This indicates whether to start the next
command (if any) in pNextOp, or to return to an IDLE state.
Table 23-85. End of ABORT Background-Level Operation
Condition

Status Code

Result

Background level aborted

IEEE_DONE_OK

TRUE

Received CMD_STOP or CMD_IEEE_STOP_FG

IEEE_DONE_STOPPED

FALSE

Received CMD_ABORT or CMD_IEEEE_ABORT_FG

IEEE_DONE_ABORT

ABORT

23.5.5 Immediate Commands
23.5.5.1 Modify CCA Parameter Command
The CMD_IEEE_MOD_CCA command takes a command structure as defined in Table 23-64.
CMD_IEEE_MOD_CCA must only be sent while an RX or energy-detect scan operation is running. On
reception, the radio CPU modifies the values of ccaRssiThr and ccaOpt for the running process into the
values given by newCcaRssiThr and newCcaOpt, respectively. The radio CPU updates the command
structure. The new settings are used for future CCA requests.
If the command is issued without an active or suspended background-level operation, the radio CPU
returns the result ContextError in CMDSTA. If any of the parameters entered are illegal, the radio CPU
returns the result ParError in CMDSTA. Otherwise, the radio CPU returns DONE.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1647

IEEE 802.15.4

www.ti.com

23.5.5.2 Modify Frame-Filtering Parameter Command
The CMD_IEEE_MOD_FILT command takes a command structure as defined in Table 23-65.
CMD_IEEE_MOD_FILT must be sent only while an RX operation is running. On reception, the radio CPU
modifies the values of frameFiltOpt and frameTypes for the running process into the values given by
newFrameFiltOpt and newFrameTypes, respectively. The radio CPU updates the command structure.
The new values of the frame-filtering options are used from the next time frame filtering is started. If
autoAckEn or slottedAckEn are changed, the change applies from the next time reception of a packet
ends.
If the command is issued without an active or suspended background-level RX operation, the radio CPU
returns the result ContextError in CMDSTA. If any of the parameters entered are illegal, the radio CPU
returns the result ParError in CMDSTA. Otherwise, the radio CPU returns DONE.
23.5.5.3 Enable or Disable Source Matching Entry Command
The CMD_IEEE_MOD_SRC_MATCH command takes a command structure as defined in Table 23-65.
CMD_IEEE_MOD_SRC_MATCH must be sent only while an RX operation is running. On reception, the
radio CPU enables or disables the source-matching entry signaled in the command structure. If
options.entryType is 0, the entry is extended-address entry in the structure pointed to by pExtEntryList,
and if options.entryType is 1, the entry is short-address entry in the structure pointed to by
pShortEntryList. The index of the entry is signaled in entryNo. If options.bEnable is 0, the entry is disabled,
and if it is 1, the entry is enabled. The corresponding source pending bit is set to the value of
options.srcMatch.
The new values of the enable values are used from the next time source-matching is performed. The
system CPU may modify the address of a disabled entry, but not an enabled one.
If the command is issued without an active or suspended background-level RX operation, the radio CPU
returns the result ContextError in CMDSTA. If any of the parameters entered are illegal, for example,
pointing to a nonexistent entry, the radio CPU returns the result ParError in CMDSTA. Otherwise, the
radio CPU returns DONE.
23.5.5.4 Abort Foreground-Level Operation Command
CMD_IEEE_ABORT_FG is an immediate command that takes no parameters, and can thus be used as a
direct command.
The CMD_IEEE_ABORT_FG command aborts the foreground-level operation while the background-level
operation continues to run. For more detail, see the description of the foreground-level operations in
Table 23-57.
If no foreground-level radio operation command is running, no action is taken. The result signaled in
CMDSTA is DONE in all cases. If a foreground-level radio operation command was running, CMDSTA
may be updated before the radio operation has ended.
23.5.5.5 Stop Foreground-Level Operation Command
CMD_IEEE_STOP_FG is an immediate command that takes no parameters, and can thus be used as a
direct command.
The CMD_IEEE_STOP_FG command causes the foreground-level operation to stop gracefully, while the
background-level operation continues to run. For more detail, see the description of the foreground-level
operations in Table 23-57.
If no foreground-level radio operation command is running, no action is taken. The result signaled in
CMDSTA is DONE in all cases. If a foreground-level radio operation command was running, CMDSTA
may be updated before the radio operation has ended.

1648

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

23.5.5.6 Request CCA and RSSI Information Command
The CMD_IEEE_CCA_REQ command takes a command structure as defined in Table 23-67.
CMD_IEEE_CCA_REQ must be sent only while an RX or energy-detect scan operation is running. On
reception, the radio CPU writes the following figures back into the command structure:
• currentRssi is set to the RSSI number currently available from the demodulator.
• maxRssi is set to the maximum RSSI observed because the background-level operation was started.
• ccaState is set to the CCA state according to the current CCA options (see Section 23.5.4.1.5).
• ccaEnergy is set to the energy-detect CCA state, according to Section 23.5.4.1.5.
• ccaCorr is set to the correlator-based carrier-sense CCA state, according to Section 23.5.4.1.5.
• ccaSync is set to the sync found-based carrier-sense CCA state, according to Section 23.5.4.1.5.
If no valid RSSI is found when the request is sent, the currentRssi and maxRssi returned indicate this by
using a special value (0x80).
If the command is issued without an active or suspended background-level RX operation, the radio CPU
returns the result ContextError in CMDSTA. Otherwise, the radio CPU returns DONE.

23.6

Bluetooth low energy
This section describes Bluetooth low-energy-specific command structure, data handling, radio operation
commands, and immediate commands.

23.6.1

Bluetooth low energy Commands

Table 23-86 defines the Bluetooth low-energy-specific radio operation commands.
Table 23-86. Bluetooth low energy Radio Operation Commands
ID

Command Name

Description

0x1801

CMD_BLE_SLAVE

Start slave operation

0x1802

CMD_BLE_MASTER

Start master operation

0x1803

CMD_BLE_ADV

Start connectable undirected advertiser operation

0x1804

CMD_BLE_ADV_DIR

Start connectable directed advertiser operation

0x1805

CMD_BLE_ADV_NC

Start the not-connectable advertiser operation

0x1806

CMD_BLE_ADV_SCAN

Start scannable undirected advertiser operation

0x1807

CMD_BLE_SCANNER

Start scanner operation

0x1808

CMD_BLE_INITIATOR

Start initiator operation

0x1809

CMD_BLE_GENERIC_RX

Receive generic packets (used for PHY test or packet sniffing)

0x180A

CMD_BLE_TX_TEST

Transmit PHY test packets

Table 23-87 defines the Bluetooth low-energy-specific immediate command.
Table 23-87. Bluetooth low energy Immediate Command
ID

Command Name

Description

0x1001

CMD_BLE_ADV_PAYLOAD

Modify payload used in advertiser operations

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1649

Bluetooth low energy

www.ti.com

23.6.1.1 Command Data Definitions
This section defines data types that describe the data structures used to communicate between the
system CPU and the radio CPU. The data structures are listed with tables. The Byte Index is the offset
from the pointer to that structure. Multibyte fields are little-endian, and halfword or word alignment is
required. For bit numbering, 0 is the LSB. The R/W column is used as follows:
• R: The system CPU can read a result back; the radio CPU does not read the field.
• W: The system CPU writes a value; the radio CPU reads it and does not modify the value.
• R/W: The system CPU writes an initial value; the radio CPU may modify the initial value.
23.6.1.1.1 Bluetooth low energy Command Structures
Table 23-88. Bluetooth low energy Radio Operation Command Structure
Byte
Index

Field Name

Bits

Bit Field Name

channel

(1)

Type

Description

Channel to use:
0–39: Bluetooth low energy advertising/data channel
number
60–207: Custom frequency; (2300 + channel) MHz
255: Use existing frequency
Others: reserved

0–6

init

If bOverride = 1 or custom frequency is used:
0: Do not use whitening
Other value: Initialization for 7-bit LFSR whitener

bOverride

0: Use default whitening for Bluetooth low energy
advertising/data channels
1: Override whitening initialization with value of init

whitening

16–19

pParams

Pointer to command-specific parameter list

20–23

pOutput

Pointer to command-specific result (NULL: Do not store
results)

(1)

This command structure is used for all the radio operation commands for Bluetooth low energy support. Table 23-8 defines the
first 14 bytes.

Table 23-89. Update Advertising Payload Command

1650

Byte
Index

Field Name

Type

Description

0–1

commandNo

The command number

payloadType

0: Advertising data
1: Scan response data

newLen

Length of the new payload

4–7

pNewData

Pointer to the buffer containing the new data

8–11

pParams

Pointer to the parameter structure to update

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

23.6.1.2 Parameter Structures
Table 23-90. Slave Commands
Byte Index Field Name

Type

Description

0–3

pRxQ

Pointer to receive queue

4–7

pTxQ

Pointer to transmit queue

rxConfig

Configuration bits for the receive queue entries (see
Table 23-103 for details)

seqStat

R/W

Sequence number status (see Table 23-70 for details)

maxNack

Maximum number of NACKs received before operation
ends. 0: No limit

maxPkt

Maximum number of packets transmitted in the operation
before it ends. 0: No limit

12–15

accessAddress

Access address used on the connection

16–18

crcInit

CRC initialization value used on the connection

timeoutTrigger

Trigger that defines time-out of the first receive operation

20–23

timeoutTime

Time parameter for timeoutTrigger

24–26

Reserved

endTrigger

Trigger that causes the device to end the connection event
as soon as allowed

28–31

endTime

Time parameter for endTrigger

Table 23-91. Master Commands
Byte Index Field Name

Type

Description

0–3

pRxQ

Pointer to receive queue

4–7

pTxQ

Pointer to transmit queue

rxConfig

Configuration bits for the receive queue entries (see
Table 23-103 for details)

seqStat

R/W

Sequence number status (see Table 23-70 for details)

maxNack

Maximum number of NACKs received before operation
ends. 0: No limit

maxPkt

Maximum number of packets transmitted in the operation
before it ends. 0: No limit

12–15

accessAddress

Access address used on the connection

16–18

crcInit

CRC initialization value used on the connection

endTrigger

Trigger that causes the device to end the connection event
as soon as allowed

20–23

endTime

Time parameter for endTrigger

Table 23-92. Advertiser Commands
Byte Index Field Name

Type

Description

0–3

pRxQ

Pointer to receive queue

rxConfig

Configuration bits for the receive queue
entries (see Table 23-103 for details)

Bits

Bit Field Name

0–1

advFilterPolicy

The advertiser filter policy

deviceAddrType

The type of the device address: public (0) or
random (1)

peerAddrType

Directed advertiser: The type of the peer
address: public (0) or random (1)

bStrictLenFilter

advConfig
W

1: Discard messages with illegal length

advLen

Size of advertiser data

scanRspLen

Size of scan response data

Radio1651

Bluetooth low energy

www.ti.com

Table 23-92. Advertiser Commands (continued)
Byte Index Field Name

Type

Description

8–11

pAdvData

Bits

Bit Field Name

Pointer to buffer containing ADV*_IND data

12–15

pScanRspData

Pointer to buffer containing SCAN_RSP data

16–19

pDeviceAddress

Pointer to device address used for this
device

20–23

pWhiteList

Pointer to white list or peer address
(directed advertiser)

24–26

Reserved

endTrigger

Trigger that causes the device to end the
advertiser event as soon as allowed

28–31

endTime

Time parameter for endTrigger

Table 23-93. Scanner Command
Byte Index Field Name

Bits

Bit Field Name

Type

Description

0–3

pRxQ

Pointer to receive queue

rxConfig

Configuration bits for the receive queue
entries (see Table 23-103 for details)

scanConfig

scanFilterPolicy

The scanner filter policy

bActiveScan

0: Passive scan
1: Active scan

deviceAddrType

The type of the device address – public (0)
or random (1)

bStrictLenFilter

1: Discard messages with illegal length

bAutoWlIgnore

1: Automatically set ignore bit in white list

bEndOnRpt

1: End scanner operation after each reported
ADV*_IND and potentially SCAN_RSP

Reserved

6–7

randomState

R/W

State for pseudo-random number generation
used in backoff procedure

8–9

backoffCount

R/W

Parameter backoffCount used in backoff
procedure

backoffPar

0–3

logUpperLimit

R/W

Binary logarithm of parameter upperLimit
used in scanner backoff procedure

bLastSucceeded

R/W

1 if the last SCAN_RSP was successfully
received and upperLimit not changed

bLastFailed

R/W

1 if reception of the last SCAN_RSP failed
and upperLimit was not changed

scanReqLen

Size of scan request data

12–15

pScanReqData

Pointer to buffer containing SCAN_REQ data

16–19

pDeviceAddress

Pointer to device address used for this
device

20–23

pWhiteList

Pointer to white list

24–25

1652

Reserved

timeoutTrigger

Trigger that causes the device to stop
receiving as soon as allowed

endTrigger

Trigger that causes the device to stop
receiving as soon as allowed

28–31

timeoutTime

Time parameter for timeoutTrigger

32–35

endTime

Time parameter for endTrigger

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

Table 23-94. Initiator Command
Byte Index Field Name

Type

Description

0–3

pRxQ

Pointer to receive queue

rxConfig

Configuration bits for the receive queue
entries (see Table 23-103 for details)

initConfig

Bits

Bit Field Name

bUseWhiteList

Initiator filter policy:
0: Use specific peer address.
1: Use white list

bDynamicWinOffset

1: Use dynamic WinOffset insertion

deviceAddrType

The type of the device address – public (0)
or random (1)

peerAddrType

The type of the peer device address –
public (0) or random (1)

bStrictLenFilter

1: Discard messages with illegal length

Reserved

connectReqLen

Size of connect request data

8–11

pConnectReqData

Pointer to buffer containing LLData to go in
the CONNECT_REQ

12–15

pDeviceAddress

Pointer to device address used for this
device

16–19

pWhiteList

Pointer to white list or peer address

R/W

Indication of timer value of the first possible
start time of the first connection event. Set
to the calculated value if a connection is
made and to the next possible connection
time (see Table 23-100) if not.

20–23

connectTime

24–25

Reserved

timeoutTrigger

Trigger that causes the device to stop
receiving as soon as allowed

endTrigger

Trigger that causes the device to stop
receiving as soon as allowed

28–31

timeoutTime

Time parameter for timeoutTrigger

32–35

endTime

Time parameter for endTrigger

Radio1653

Bluetooth low energy

www.ti.com

Table 23-95. Generic RX Command
Byte Index

Field Name

Type

Description

0–3

pRxQ

Pointer to receive queue. May be NULL; if so,
received packets are not stored

rxConfig

Configuration bits for the receive queue entries (see
Table 23-103 for details).

bRepeat

0: End operation after receiving a packet.
1: Restart receiver after receiving a packet.

8–11

accessAddress

Access address used on the connection

12–14

crcInit

CRC initialization value used on the connection

endTrigger

Trigger that causes the device to end the RX
operation

16–19

endTime

Time parameter for endTrigger

6–7

Reserved

Table 23-96. TX Test Command
Byte Index

Field Name

0–1

Type

Description

numPackets

Number of packets to transmit
0: Transmit unlimited number of
packets

payloadLength

The number of payload bytes in each
packet

packetType

The packet type to be used

4–7

period

Number of radio timer cycles between
the start of each packet

config

byteVal

Bits

Bit Field Name

bOverride

0: Use default packet encoding
1: Override packet contents

bUsePrbs9

If bOverride is 1:
1: Use PRBS9 encoding of packet

bUsePrbs15

If bOverride is 1:
1: Use PRBS15 encoding of packet

If config.bOverride is 1, value of each
byte to be sent

1654

Reserved

endTrigger

Trigger that causes the device to end
the Test TX operation

12–15

endTime

Time parameter for endTrigger

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

23.6.1.3 Output Structures
Table 23-97. Master or Slave Commands
Byte Index

Field Name

Type

Description

nTx

R/W

Number of packets (including automatic empty and
retransmissions) transmitted

nTxAck

R/W

Number of transmitted packets (including automatic empty) ACKed

nTxCtrl

R/W

Number of unique LL control packets from the TX queue
transmitted

nTxCtrlAck

R/W

Number of LL control packets from the TX queue finished (ACKed)

nTxCtrlAckAck

R/W

Number of LL control packets ACKed and where an ACK has been
sent in response

nTxRetrans

R/W

Number of retransmissions done

nTxEntryDone

R/W

Number of packets from the TX queue finished (ACKed)

nRxOk

R/W

Number of packets received with payload, CRC OK and not
ignored

nRxCtrl

R/W

Number of LL control packets received with CRC OK and not
ignored

nRxCtrlAck

R/W

Number of LL control packets received with CRC OK and not
ignored, and then ACKed

nRxNok

R/W

Number of packets received with CRC error

nRxIgnored

R/W

Number of packets received with CRC OK and ignored due to
repeated sequence number

nRxEmpty

R/W

Number of packets received with CRC OK and no payload

nRxBufFull

R/W

Number of packets received and discarded due to lack of buffer
space

lastRssi

RSSI of last received packet

pktStatus

R/W

Status of received packets; see Table 23-107

16–19

timeStamp

Slave operation: Timestamp of first received packet

Table 23-98. Advertiser Commands
Byte Index

Field Name

Type

Description

0–1

nTxAdvInd

R/W

Number of ADV*_IND packets completely transmitted

nTxScanRsp

R/W

Number of SCAN_RSP packets transmitted

nRxScanReq

R/W

Number of SCAN_REQ packets received OK and not ignored

nRxConnectReq

R/W

Number of CONNECT_REQ packets received OK and not ignored

Reserved

6–7

nRxNok

R/W

Number of packets received with CRC error

8–9

nRxIgnored

R/W

Number of packets received with CRC OK, but ignored

nRxBufFull

R/W

Number of packets received that did not fit in RX queue

lastRssi

The RSSI of the last received packet

12–15

timeStamp

Timestamp of the last received packet

Radio1655

Bluetooth low energy

www.ti.com

Table 23-99. Scanner Command
Byte Index

Field Name

Type

Description

0–1

nTxScanReq

R/W

Number of transmitted SCAN_REQ packets

2–3

nBackedOffScanReq

R/W

Number of SCAN_REQ packets not sent due to backoff procedure

4–5

nRxAdvOk

R/W

Number of ADV*_IND packets received with CRC OK and not ignored

6–7

nRxAdvIgnored

R/W

Number of ADV*_IND packets received with CRC OK, but ignored

8–9

nRxAdvNok

R/W

Number of ADV*_IND packets received with CRC error

10–11

nRxScanRspOk

R/W

Number of SCAN_RSP packets received with CRC OK and not ignored

12–13

nRxScanRspIgnored

R/W

Number of SCAN_RSP packets received with CRC OK, but ignored

14–15

nRxScanRspNok

R/W

Number of SCAN_RSP packets received with CRC error

nRxAdvBufFull

R/W

Number of ADV*_IND packets received that did not fit in RX queue

nRxScanRspBufFull

R/W

Number of SCAN_RSP packets received that did not fit in RX queue

lastRssi

The RSSI of the last received packet

Reserved

20–23

timeStamp

Timestamp of the last successfully received ADV*_IND packet that was
not ignored

Table 23-100. Initiator Command
Byte Index

Field Name

Type

Description

nTxConnectReq

R/W

Number of transmitted CONNECT_REQ packets

nRxAdvOk

R/W

Number of ADV*_IND packets received with CRC OK and not
ignored

2–3

nRxAdvIgnored

R/W

Number of ADV*_IND packets received with CRC OK, but ignored

4–5

nRxAdvNok

R/W

Number of ADV*_IND packets received with CRC error

nRxAdvBufFull

R/W

Number of ADV*_IND packets received that did not fit in RX
queue

lastRssi

R/W

The RSSI of the last received packet

8–11

timeStamp

Timestamp of the received ADV*_IND packet that caused
transmission of CONNECT_REQ

Table 23-101. Generic RX Command
Byte
Index

Field Name

Type

Description

0–1

nRxOk

R/W

Number of packets received with CRC OK

2–3

nRxNok

R/W

Number of packets received with CRC error

4–5

nRxBufFull

R/W

Number of packets that have been received and
discarded due to lack of buffer space

lastRssi

The RSSI of the last received packet

timeStamp

Reserved

8–11

Timestamp of the last received packet

Table 23-102. Test TX Command

1656

Byte Index

Field Name

Type

Description

0–1

nTx

R/W

Number of packets transmitted

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

23.6.1.4 Other Structures and Bit Fields
Table 23-103. Receive Queue Entry Configuration Bit Field (1)
Bits

Bit Field Name

Description

bAutoFlushIgnored

If 1, automatically remove ignored packets from RX queue.

bAutoFlushCrcErr

If 1, automatically remove packets with CRC error from RX queue.

bAutoFlushEmpty

If 1, automatically remove empty packets from RX queue.

bIncludeLenByte

If 1, include the received length byte in the stored packet; otherwise discard
it.

bIncludeCrc

If 1, include the received CRC field in the stored packet; otherwise discard
it. This requires pktConf.bUseCrc to be 1.

bAppendRssi

If 1, append an RSSI byte to the packet in the RX queue.

bAppendStatus

If 1, append a status byte to the packet in the RX queue.

bAppendTimestamp

If 1, append a timestamp to the packet in the RX queue.

(1)

This bit field is used for the rxConfig byte of the parameter structures.

Table 23-104. Sequence Number Status Bit Field
Bits

Bit Field Name

Description

lastRxSn

The SN bit of the header of the last packet received with CRC OK

lastTxSn

The SN bit of the header of the last transmitted packet

nextTxSn

The SN bit of the header of the next packet to transmit

bFirstPkt

For slave: 0 if a packet has been transmitted on the connection, 1
otherwise

bAutoEmpty

1 if the last transmitted packet was an auto-empty packet

bLlCtrlTx

1 if the last transmitted packet was an LL control packet (LLID = 11)

bLlCtrlAckRx

1 if the last received packet was the ACK of an LL control packet

bLlCtrlAckPending

1 if the last successfully received packet was an LL control packet that has
not yet been ACKed

Table 23-105. White List Structure (1)
Byte Index

0–7

Field Name

entry[0]

Bits

Bit Field Name

Type

Description

0–7

Size

Number of white list entries

bEnable

1 if the entry is in use, 0 if the entry is not in use

addrType

The type address in the entry: public (0) or random (1)

bWlIgn

R/W

1 if the entry is to be ignored by a scanner, 0 otherwise.
Used to mask out entries that have already been
scanned and reported.

Address

bEnable

1 if the entry is in use, 0 if the entry is not in use

addrType

The type address in the entry: public (0) or random (1)

bWlIgn

R/W

1 if the entry is to be ignored by a scanner, 0 otherwise.
Used to mask out entries that have already been
scanned and reported.

11–15
16–63

Reserved
The address contained in the entry

...
0–7

8×n–8×n+7

entry[n]

Reserved

11–15
16–63
(1)

Reserved
address

The address contained in the entry

The white list structure has the form of an array. Each element consists of 8 bytes. The first byte of the first element tells the
number of entries, and is reserved in the remaining entries. The second byte contains some configuration bits, and the remaining
6 bytes contain the address.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1657

Bluetooth low energy

www.ti.com

Table 23-106. Receive Status Byte Bit Field

(1)

Bits

Bit Field Name

Description

0–5

channel

The channel on which the packet was received, provided channel is in
the range 0–39; otherwise 0x3F

bIgnore

1 if the packet is marked as ignored, 0 otherwise

bCrcErr

1 if the packet was received with CRC error, 0 otherwise

(1)

A byte of this bit field is appended to the received entries if configured.

The master and slave output structure field pktStatus follows the format described in Table 23-107. The
bTimeStampValid bit is set to 0 by the radio CPU at the start of the operation, and to 1 if a timestamp is
written to the output structure (this occurs for slave operation only). The bLastCrcErr bit is set according to
the CRC result when a packet is fully received; if no packet is received, this bit remains unaffected. The
remaining bits are set when a packet is received with CRC OK; if no packet is correctly received, these
bits remain unaffected.
Table 23-107. Master and Slave Packet Status Byte
Bits

Bit Field Name

Description

bTimeStampValid

1 if a valid timestamp has been written to timeStamp; 0 otherwise

bLastCrcErr

1 if the last received packet had CRC error; 0 otherwise

bLastIgnored

1 if the last received packet with CRC OK was ignored; 0 otherwise

bLastEmpty

1 if the last received packet with CRC OK was empty; 0 otherwise

bLastCtrl

1 if the last received packet with CRC OK was empty; 0 otherwise

bLastMd

1 if the last received packet with CRC OK had MD = 1; 0 otherwise

bLastAck

1 if the last received packet with CRC OK was an ACK of a transmitted
packet; 0 otherwise

Reserved

23.6.2 Interrupts
The radio CPU signals events back to the system CPU, using firmware-defined interrupts. Table 23-108
lists the interrupts used by the Bluetooth low energy commands. Each interrupt may be enabled
individually in the system CPU. Section 23.6.4 gives the details about when the interrupts are generated.
Table 23-108. Interrupt Definitions Applicable to Bluetooth low energy
Interrupt Number

Interrupt Name

Description

COMMAND_DONE

A radio operation command has finished.

LAST_COMMAND_DONE

The last radio operation command in a chain of
commands has finished.

TX_DONE

A packet has been transmitted.

TX_ACK

Acknowledgment received on a transmitted packet.

TX_CTRL

Transmitted LL control packet

TX_CTRL_ACK

Acknowledgment received on a transmitted LL control
packet.

TX_CTRL_ACK_ACK

Acknowledgment received on a transmitted LL control
packet, and acknowledgment transmitted for that packet.

TX_RETRANS

Packet has been retransmitted.

TX_ENTRY_DONE

TX queue data entry state changed to Finished.

TX_BUFFER_CHANGED

A buffer change is complete after
CMD_BLE_ADV_PAYLOAD.

RX_OK

The packet is received with CRC OK, payload, and not to
be ignored.

RX_NOK

The packet is received with CRC error.

RX_IGNORED

The packet is received with CRC OK, but to be ignored.

1658Radio

Bluetooth low energy

www.ti.com

Table 23-108. Interrupt Definitions Applicable to Bluetooth low energy (continued)
Interrupt Number

Interrupt Name

Description

RX_EMPTY

The packet is received with CRC OK, not to be ignored,
no payload.

RX_CTRL

LL control packet received with CRC OK, not to be
ignored.

RX_CTRL_ACK

LL control packet received with CRC OK, not to be
ignored, then acknowledgment sent.

RX_BUF_FULL

The packet is received that did not fit in the RX queue.

RX_ENTRY_DONE

RX queue data entry changing state to Finished.

MODULES_UNLOCKED

As part of the boot process, the CM0 has opened access
to RF core modules and memories.

BOOT_DONE

The RF core CPU boot is finished.

INTERNAL_ERROR

The radio CPU has observed an unexpected error.

23.6.3 Data Handling
For all the Bluetooth low energy commands, data received over the air is stored in a receive queue. Data
to be transmitted is fetched from a transmit queue for master and slave operation, while for the
nonconnected operations, the data is fetched from a specific buffer, or created entirely by the radio CPU
based on other available information.
23.6.3.1 Receive Buffers
A packet being received is stored in a receive buffer. First, a length byte or word is stored, if configured in
the RX entry, by config.lenSz. This word is calculated from the length received over the air and the
configuration of appended information.
Following the optional length field, the received header and payload is stored as received over the air. If
rxConfig.bIncludeLenByte is 1, the full 16-bit header, including the received length field, is stored, despite
the length field being redundant information if a length byte or word is present. If
rxConfig.bIncludeLenByte is 0, only the first byte of the header is stored, so that the second byte, which
only contains the redundant length field and some RFU bits, is discarded.
If rxConfig.bIncludeCrc is 1, the received CRC value is stored in the RX buffer. If rxConfig.bAppendRssi is
1, a byte indicating the received RSSI value is appended. If rxConfig.bAppendStatus is 1, a status byte of
the type RXStatus_t, as defined in Table 23-106, is appended. If rxConfig.bAppendTimeStamp is 1, a
timestamp indicating the start of the packet is appended. This timestamp corresponds to the ratmr_t data
type. Even though the timestamp is multibyte, no word-address alignment is made, so the timestamp must
be written and read byte-wise.
Figure 23-8 shows the format of an entry element in the RX queue.
Figure 23-8. Receive Buffer Entry Element

Optional
0±2 bytes
Element
length

Mandatory fields
1±2 bytes
0±37 bytes
BLE
BLE payload
header

Optional fields
0 or 3 bytes 0 or 1 byte 0 or 1 byte
Received
RSSI
Status
CRC

0 or x bytes
Timestamp

23.6.3.2 Transmit Buffers
For master and slave operations, transmit buffers are set up in a buffer queue. The length of the packet is
defined by the length field in the data entry. The first byte of the data entry gives the LLID that goes into
the data channel packet header. The NESN, SN, and MD bits are inserted automatically by the radio CPU,
the RFU bits are set to 0, and the length field is calculated from the length of the data entry.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1659

Bluetooth low energy

www.ti.com

For advertising channel packets, the radio CPU automatically generates the header and the address fields
of the payload. The data that comes after the address fields for each message type is given by a pointer
to a data buffer. The number of bytes in this buffer is given in a separate parameter. If no data bytes are
to be transmitted, this can be indicated by setting the length to 0. In this case, the pointer is ignored, and
may be set to NULL. For Bluetooth low energy compliance, the ADV_DIRECT_IND and SCAN_REQ
messages have no payload, but for the possibility of overriding this, data buffers are still present. For
CONNECT_REQ messages, the data are required to have length 22 for Bluetooth low energy compliance,
but the implementation allows any length.

23.6.4 Radio Operation Command Descriptions
Before running any radio operation command described in this document, the radio must be set up in
Bluetooth low energy mode using the command CMD_RADIO_SETUP. Otherwise, the operation ends
with an error.
The operations start with a radio operation command from the system CPU. The actual start of the
operation is set up by the radio CPU according to startTrigger and startTime in the command structure. At
this time, the radio CPU starts configuring the transmitter or receiver, depending on the type of operation.
The system CPU must consider the setup time of the transmitter or receiver when calculating the start
time of the operation.
The radio CPU sets up the channel based on the channel parameter. If the channel is in the range from 0
to 39, it indicates a data channel index or advertising channel index. In this case, only the values 0 to 36
are allowed in master and slave commands, and only the values 37 to 39 are allowed in advertiser,
scanner, and initiator commands. If the channel is in the range from 60 to 207, it indicates an RF with an
offset of 2300 MHz. If the channel is 255, the radio CPU does not program any frequency word, but keeps
the frequency already programmed with CMD_FS. If the channel is 255 and the frequency synthesizer is
not running, the operation ends with an error.
The whitening parameter indicates the initialization of the 7-bit LFSR used for data whitening in Bluetooth
low energy. If whitening.bOverride is 0 and the channel is in the range from 0 to 39, the LFSR initializes
with (0x40 | channel). Otherwise, the LFSR initializes with whitening.init. If whitening.init is 0 in this case,
no whitening is used.
All packets transmitted using Bluetooth low energy radio operation commands have a Bluetooth lowenergy-compliant CRC appended. On all packets received using Bluetooth low-energy radio-operation
commands, a Bluetooth low-energy-compliant CRC-check is performed. The initialization of the CRC
register is defined for each command.
The radio CPU times transmissions immediately following receptions, to fulfill the requirements for T_IFS.
For reception immediately following transmissions, the radio CPU times the start of RX and time-out so
that it always receives a packet transmitted at a time within the limits set by the Bluetooth low energy
standard, but without excessive margins, to avoid false syncing on advertising channels. For the first
receive operation in a slave command, the radio CPU sets up a time-out as defined in pParams>timeoutTrigger and pParams->timeoutTime. The time of this trigger depends on the sleep-clock
uncertainty, both in the slave and the peer master.
When the receiver is running, the message is received into an RX entry as described in Section 23.6.3.1
and Section 23.3.2.7. The radio CPU has flags bCrcErr and bIgnore, which are written to the
corresponding fields of the status byte of the RX entry if present. If there is a CRC error on the received
packet, the bCrcErr flag is set. If the CRC is OK, the bIgnore flag may be set based on principles defined
for each role. This flag indicates that the system CPU may ignore the packet. After receiving a packet, the
radio CPU raises an interrupt to the system CPU.
If a packet is received with a length that is too great, the reception is stopped and treated as if sync had
not been obtained on the packet. By default, the maximum allowed payload length of advertising channel
packets is 37, and the maximum allowed length of data channel packets is 31 (which can never be
violated because the length field in this case is 5 bits). If either the bCrcErr or bIgnore flag is set or if the
packet was empty (as defined under each operation), the packet may be removed from the RX entry
before raising the interrupt, depending on the bAutoFlushIgnored, bAutoFlushCrc, and bAutoFlushEmpty
bits of pParams->rxConfig.

1660

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

The status field of the command issued is updated during the operation. When submitting the command,
the system CPU writes this field with a state of IDLE (see Table 23-109). During the operation, the radio
CPU updates the field to indicate the operation mode. When the operation is done, the radio CPU writes a
status indicating that the operation is finished. Table 23-109 lists the status codes to be used by a
Bluetooth low energy radio operation.
Table 23-109. Bluetooth low energy Radio Operation Status Codes
Number

Name

Description

0x0000

IDLE

Operation not started

0x0001

PENDING

Waiting for start trigger

0x0002

ACTIVE

Running operation

0x1400

BLE_DONE_OK

Operation ended normally

0x1401

BLE_DONE_RXTIMEOUT

Time-out of first RX of slave operation or end
of scan window

0x1402

BLE_DONE_NOSYNC

Time-out of subsequent RX

0x1403

BLE_DONE_RXERR

Operation ended because of receive error
(CRC or other)

0x1404

BLE_DONE_CONNECT

CONNECT_REQ received or transmitted

0x1405

BLE_DONE_MAXNACK

Maximum number of retransmissions exceeded

0x1406

BLE_DONE_ENDED

Operation stopped after end trigger

0x1407

BLE_DONE_ABORT

Operation aborted by abort command

0x1408

BLE_DONE_STOPPED

Operation stopped after stop command

0x1800

BLE_ERROR_PAR

Illegal parameter

0x1801

BLE_ERROR_RXBUF

No available RX buffer (advertiser, scanner,
initiator)

0x1802

BLE_ERROR_NO_SETUP

Radio was not set up in Bluetooth low energy
mode

0x1803

BLE_ERROR_NO_FS

Synthesizer was not programmed when
running RX or TX

0x1804

BLE_ERROR_SYNTH_PROG

Synthesizer programming failed

0x1805

BLE_ERROR_RXOVF

RX overflow observed during operation

0x1806

BLE_ERROR_TXUNF

TX underflow observed during operation

Operation Not Finished

Operation Finished Normally

Operation Finished With Error

The conditions for giving each status are listed for each operation. Some of the error causes listed in
Table 23-109 are not repeated in these lists. In some cases, general error causes may occur. In all of
these cases, the result of the operation is ABORT.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1661

Bluetooth low energy

www.ti.com

23.6.4.1 Link Layer Connection
At the start of a slave or master operation, the radio CPU waits for the start trigger, then programs the
frequency based on the channel parameter of the command structure. The channel parameter is not
allowed to be 37, 38, or 39, because these are advertising channels. The radio CPU sets up the access
address defined in pParams ->accessAddress, and uses the CRC initialization value defined in pParams >crcInit. The whitener is set up as defined in the whitening parameter. The radio CPU then configures the
receiver or transmitter. The operation continues with reception and transmission, until it is ended by one of
the end-of-command criteria.
When the demodulator obtains sync on a message, the message is received into the first available RX
buffer that can fit the packet. The flags bCrcErr and bIgnore are set according to Table 23-110 depending
on the CRC result, and whether the SN field of the header was the same as the SN field of the last
successfully received packet. A received packet that has a payload length of 0 is viewed as an empty
packet. This means that if pParams ->rxConfig.bAutoflushEmpty is 1 and bCrcErr and bIgnore are both 0,
the packet is removed from the RX buffer.
Table 23-110. Actions on Received Packets
CRC Result

SN Different than Previous

bCrcErr

bIgnore

Yes

NOK

If there is no available RX buffer with enough available space to hold the received packet, the received
data are discarded. The packet is received, however, so that the CRC can be checked. When the packet
has been received, the radio CPU sets the sequence bits so that a retransmission of the lost packet is
requested (that is, NACK), unless the packet would have been discarded from the RX queue anyway due
to the setting of pParams->rxConfig.
If two subsequent packets are received with CRC error, the command ends, as required by the Bluetooth
low energy specification.
When a packet must be transmitted or retransmitted, it is read from the current data entry in the TX queue
unless the TX queue is empty or an automatic empty packet must be retransmitted. The radio CPU
creates the header as follows: the LLID bits are inserted from the first byte of the TX data entry. The SN
and NESN bits are set to values according to the Bluetooth low energy protocol. The MD bit is calculated
automatically. If the TX queue is empty, an empty packet (LLID = 0x1, Length = 0) is transmitted. This
empty packet is referred to as an automatic empty packet.

1662

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

Interrupts can be raised on different conditions. The pOutput structure contains counters corresponding to
the interrupts. Table 23-111 lists the conditions for incrementing each counter or raising an interrupt. More
than one condition may be fulfilled after a packet is transmitted or received. In the list of conditions, the
term acknowledgment is used, which is defined as a successfully received packet with an NESN value in
the header different from the SN value of the last transmitted packet.
Table 23-111. Conditions for Incrementing Counters and Raising Interrupts
for Master and Slave Commands
Condition

Counter Incremented

Interrupt Generated

Packet transmitted

nTx

TX_DONE

Packet transmitted and acknowledgment received

nTxAck

TX_ACK

Packet with LLID = 11b transmitted

nTxCtrl

TX_CTRL

Packet with LLID = 11b transmitted and acknowledgment received

nTxCtrlAck

TX_CTRL_ACK

Packet with LLID = 11b transmitted, acknowledgment received, and
acknowledgment sent

nTxCtrlAckAck

TX_CTRL_ACK_ACK

Packet transmitted with same SN as previous transmitted packet

nTxRetrans

TX_RETRANS

Packet with payload transmitted and acknowledgment received

nTxEntryDone

TX_ENTRY_DONE

Packet received with bCrcErr = 0, bIgnore = 0, and payload length > 0

nRxOk

RX_OK

Packet received with CRC error (bCrcErr = 1)

nRxNok

RX_NOK

Packet received with bCrcErr = 0 and bIgnore = 1

nRxIgnored

RX_IGNORED

Packet received with bCrcErr = 0, bIgnore = 0, and payload length = 0

nRxEmpty

RX_EMPTY

Packet received with LLID = 11b, bCrcErr = 0 and bIgnore = 0

nRxCtrl

RX_CTRL

Packet received with LLID = 11b, bCrcErr = 0 and bIgnore = 0, and
acknowledgment sent

nRxCtrlAck

RX_CTRL_ACK

Packet received which did not fit in RX buffer and was not to be flushed

nRxBufFull

RX_BUF_FULL

The first RX data entry in the RX queue changed state to finished

—

RX_ENTRY_DONE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1663

Bluetooth low energy

www.ti.com

The radio CPU maintains two counters: one packet counter nPkt, and one NACK counter nNack. These
two counters are both initialized to pParams->maxPkt and pParams->maxNack, respectively, at the start
of the master or slave radio operation. The packet counter nPkt is decremented each time a packet is
transmitted. The NACK counter nNack is decremented if a packet is received that does not contain an
acknowledgment of the last transmitted packet, and is reset to pParams->maxNack if an acknowledgment
is received. If either counter counts to 0, the operation ends. This occurs after a packet has been received
for master and a packet has been transmitted for slave. Setting pParams->maxPkt or pParams->maxNack
to 0 disables the corresponding counter functionality.
A trigger to end the operation is set up by pParams->endTrigger and pParams->endTime. If the trigger
defined by this parameter occurs, the radio operation ends as soon as possible. Any packet transmitted
after this has MD = 0, and the connection event ends after the next packet has been transmitted for a
slave or received for a master. If the immediate command CMD_STOP is received by the radio CPU, it
has the same meaning as the end trigger occurring, except that the status code after ending is
CMD_DONE_STOPPED.
The register pParams->seqStat contains bits that are updated by the radio CPU during operation, and are
used to get correct operation on SN and NESN and retransmissions. The rules for the radio CPU follow:
• Before the first operation on a connection, the bits in pParams->seqStat are set as follows by the
system CPU:
– lastRXSn = 1
– lastTXSn = 1
– nextTXSn = 0
– bFirstPkt = 1
– bAutoEmpty = 0
– bLlCtrlRX = 0
– bLlCtrlAckRX = 0
– bLlCtrlAckPending = 0
• When determining if the SN field of the header was the same as the SN field of the last successfully
received packet, the received SN bit is compared to pParams->seqStat.lastRXSn.
• If a packet is received with correct CRC and the packet fits in an RX buffer, the received SN is stored
in pParams ->seqStat.lastRXSn. If the packet was an LL control packet (LLID = 11b) and the packet
was not to be ignored, pParams->seqStat.bLlCtrlAckPending is set to 1 and an RX_CTRL interrupt is
raised.
• If a packet is received with correct CRC and the received NESN bit is different from pParams>seqStat.lastTXSn, pParams->seqStat.nextTXSn is set to the value of the received NESN bit
(regardless of whether the packet fits in an RX buffer).
• If pParams->seqStat.bFirstPkt = 0:
– If pParams ->seqStat.nextTXSn was updated and became different from pParams>seqStat.lastTXSn after reception of a packet, nNack is set to pParams->maxNack and a TX_ACK
interrupt is raised.
– Otherwise, nNack is decremented.
– If pParams ->seqStat.nextTXSn was updated and became different from pParams>seqStat.lastTXSn after reception of a packet, and pParams->seqStat.bAutoEmpty = 0, the current
TX queue entry is finished and the next one is set as active, and a TX_ENTRY_DONE interrupt is
raised. If pParams->seqStat.bLlCtrlTX = 1, an TX_CTRL_ACK interrupt is raised and pParams>seqStat.bLlCtrlAckRX is set to 1.
– If pParams->seqStat.nextTXSn was updated and became different from pParams>seqStat.lastTXSn after reception of a packet, pParams->seqStat.bAutoEmpty is set to 0.
• If no buffer is available in the TX queue, or if pParams->seqStat.nextTXSn is equal to pParams>seqStat.lastTXSn and pParams->seqStat.bAutoEmpty = 1 when transmission of a packet is to occur,
an automatically empty packet is transmitted. Nothing is read from the TX queue. Otherwise, the
transmitted packet is read from the first entry of the TX queue.
• In the header of a transmitted packet, the SN bit is set to the value of pParams->seqStat.nextTXSn,
and the NESN bit is set to the inverse of pParams->seqStat.lastRXSn.
1664

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

•

After a packet has been transmitted:
– If pParams->seqStat.nextTXSn is equal to pParams->seqStat.lastTXSn, a TX_RETRANS interrupt
is raised.
– If pParams->seqStat.nextTXSn is different from pParams->seqStat.lastTXSn after a transmission
and the transmitted packet had LLID = 11b, a TX_Ctrl interrupt is raised.
– If pParams->seqStat.nextTXSn is different from pParams->seqStat.lastTXSn after a transmission
and pParams->seqStat.bLlCtrlAckPending = 1, an RX_CTRL_ACK interrupt is raised.
– If pParams->seqStat.nextTXSn is different from pParams->seqStat.lastTXSn after a transmission
and pParams->seqStat.bLlCtrlAckRX = 1, a TX_CTRL_ACK_ACK interrupt is raised.
– pParams->seqStat.lastTXSn is set to the value of pParams->seqStat.nextTXSn.
– pParams->seqStat.bAutoEmpty is set to 1 if the packet was not read from the TX queue, otherwise
to 0.
– pParams->seqStat.bLlCtrlTX is set to 1 if the transmitted packet had LLID = 11, otherwise to 0.
– pParams->seqStat.firstPkt, pParams ->seqStat.bLlCtrlAckPending, and pParams>seqStat.bLlCtrlAckRX is set to 0.
– A TX_DONE interrupt is raised.
– nPkt is decremented.

When an interrupt is raised as described previously, the corresponding counter given in Table 23-90 is
incremented.
In the header of a transmitted packet, the MD bit is set according to the following rules:
• If the transmit queue is empty or the packet being transmitted is the last packet of the transmit queue,
MD is 0.
• If the trigger described in pParams->endTrigger has occurred, MD is 0.
• If the counter nPkt is 1, MD is 0.
• Otherwise, MD is 1.
The pOutput structure contains counters that are updated by the radio CPU as explained previously and in
Table 23-90. The radio CPU does not initialize the fields, so this must be done by the system CPU when a
reset of the counters is desired. In addition to the counters, the radio CPU sets the following fields:
• If a packet is received, lastRssi is set to the RSSI of that packet.
• For slave commands, timeStamp is set to the timestamp of the start of the first received packet, if any
packet is received. bValidTimeStamp is set to 0 at the beginning of the operation and to 1 if a packet is
received so that timeStamp is written.
For correct operation, the value of pParams->seqStat is the same at the beginning of a command as at
the end of the previous operation of the same connection. The TX queue must also be unmodified
between commands operating on the same connection, except that packets may be appended to the
queue.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1665

Bluetooth low energy

www.ti.com

23.6.4.2 Slave Command
A slave radio operation is started by a CMD_BLE_SLAVE command. In the command structure, it has a
pParams parameter of the type defined in Table 23-90, and a pOutput parameter of the type defined in
Table 23-97. The operation starts with reception. The parameters pParams->timeoutTrigger and
pParams->timeoutTime define the time to end the operation if no sync is found by the demodulator. The
startTrigger and pParams->timeoutTrigger together define the receive window for the slave.
The first received packet of a new LL connection on a slave is given special treatment, and is signaled by
the system CPU by setting pParams->seqStat.bFirstPkt to 1 when starting the first slave operation of a
new connection. When this flag is set, the received packet is not viewed as an ACK or NACK of a
previous transmitted packet. When a packet has been transmitted, the radio CPU clears pParams>seqStat.bFirstPkt.
The radio CPU writes a timestamp of the first received packet of the radio operation into pOutput>timeStamp. The captured time can be used by the system CPU as an anchor point to calculate the start
of future slave commands. This time is also defined as event 1, and may be used for timing subsequent
chained operations. If no anchor point is found, event 1 is the time of the start of the slave operation.
If a packet is received with CRC error, the radio CPU ends the radio operation if the previous packet in the
same radio operation was also received with CRC error (see Table 23-112). Otherwise, if a packet is
received, the radio CPU starts the transmitter and transmits from the TX queue, or transmits an
automatically empty packet if the TX queue is empty. The transmission may be a retransmission. Unless
the operation ends due to the criteria listed in Table 23-112, the receiver starts after the transmission is
done.
A slave operation ends due to one of the causes listed in Table 23-112. After the operation has ended, the
status field of the command structure (2 status bytes listed in Table 23-8) indicates why the operation
ended. In all cases, a COMMAND_DONE interrupt is raised. In each case, it is indicated if the result is
TRUE, FALSE, or ABORT, which decides the next action.
Table 23-112. End of Slave Operation

1666

Condition

Status Code

Result

Transmitted packet with MD=0 after having successfully received packet
where MD bit of header is 0.

BLE_DONE_OK

TRUE

Transmitted packet with MD=0 after having received packet which did not fit
in RX queue.

BLE_DONE_OK

TRUE

Finished transmitting packet and nPkt counted to 0.

BLE_DONE_OK

TRUE

Trigger indicated by pParams->timeoutTrigger occurred before demodulator
sync is ever obtained after starting the command.

BLE_DONE_RXTIMEOUT

FALSE

No sync obtained on receive operation after transmit.

BLE_DONE_NOSYNC

TRUE

Two subsequent packets in the same operation were received with CRC
error.

BLE_DONE_RXERR

TRUE

Finished transmitting packet after the internal counter nNack had counted
down to 0.

BLE_DONE_MAXNACK

TRUE

Finished transmitting packet after having observed trigger indicated by
pParams->endTrigger.

BLE_DONE_ENDED

FALSE

Finished transmitting packet after having observed CMD_STOP.

BLE_DONE_STOPPED

FALSE

Received CMD_ABORT.

BLE_DONE_ABORT

ABORT

Illegal value of channel

BLE_ERROR_PAR

ABORT

TX data entry length field has illegal value.

BLE_ERROR_PAR

ABORT

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

23.6.4.3 Master Command
A master radio operation is started by a CMD_BLE_MASTER command. In the command structure, it has
a pParams parameter of the type defined in Table 23-91 and a pOutput parameter of the type defined in
Table 23-97. The operation starts with transmission. After each transmission, the receiver is started.
A master operation ends due to one of the causes listed in Table 23-113. After the operation has ended,
the status field of the command structure (2 status bytes listed in Table 23-8) indicates why the operation
ended. In all cases, a COMMAND_DONE interrupt is raised. In each case, it is indicated if the result is
TRUE, FALSE, or ABORT, which decides the next action.
Table 23-113. End of Master Operation
Condition

Status Code

Result

Successfully received packet with MD = 0 after having transmitted a
packet with MD = 0.

BLE_DONE_OK

TRUE

Received packet which did not fit in RX queue after having transmitted
a packet with MD = 0.

BLE_DONE_OK

TRUE

Received a packet after nPkt had counted to 0.

BLE_DONE_OK

TRUE

No sync obtained on receive operation after transmit.

BLE_DONE_NOSYNC

TRUE

Two subsequent packets in the same operation were received with
CRC error.

BLE_DONE_RXERR

TRUE

The internal counter nNack counted down to 0 after a packet was
received.

BLE_DONE_MAXNACK

TRUE

Received a packet after having observed trigger indicated by pParams
>endTrigger.

BLE_DONE_ENDED

FALSE

Received a packet after having observed CMD_STOP.

BLE_DONE_STOPPED

FALSE

Received CMD_ABORT.

BLE_DONE_ABORT

ABORT

Illegal value of channel

BLE_ERROR_PAR

ABORT

TX data entry length field has illegal value.

BLE_ERROR_PAR

ABORT

23.6.4.4 Advertiser
At the start of any advertiser operation, the radio CPU waits for the start trigger, then programs the
frequency based on the channel parameter of the command structure. The channel parameter is not
allowed to be in the range from 0 to 36, as these are data channels. The radio CPU sets up the
advertising channel access address and uses the CRC initialization value 0x55 5555. The whitener is set
up as defined in the whitening parameter. The radio CPU then configures the transmitter. Except for an
advertiser that is not connectable, the operation goes on with reception after transmission, and if a
SCAN_REQ is received, another transmission of a SCAN_RSP may occur.
In Bluetooth low energy mode, advertising is usually done over all three advertising channels. To set this
up, three command structures can be chained using the pNextOp parameter. Typically, the parameter and
output structures can be the same for all channels.
The first packet transmitted is always an ADV*_IND packet. This packet consists of a header, an
advertiser address, and advertising data, except for the ADV_DIRECT_IND packet used in directed
advertising. The radio CPU constructs these packets as follows (the ADV_DIRECT_IND packet is
described in Section 23.6.4.4.2). In the header, the PDU Type bits are as shown in Table 23-114. The
TXAdd bit is as shown in pParams->advConfig.deviceAddrType. The length is calculated from the size of
the advertising data, meaning that it is pParams->advLen + 6. The RXAdd bit is not used and is 0, along
with the RFU bits. The payload starts with the 6-byte device address, which is read from pParams>pDeviceAddress. The rest of the payload is read from the pParams->pAdvData buffer (if pParams>advLen is nonzero).

Radio1667

Bluetooth low energy

www.ti.com

Table 23-114. PDU Types for Different Advertiser Commands
Command

Type of Advertising Packet

Value of PDU Type Bits in Header

CMD_BLE_ADV

ADV_IND

0000b

CMD_BLE_ADV_DIR

ADV_DIRECT_IND

0001b

CMD_BLE_ADV_NC

ADV_NONCONN_IND

0010b

CMD_BLE_ADV_SCAN

ADV_SCAN_IND

0110b

Except when an advertiser is not connectable, the receiver starts after the ADV*_IND packet has been
transmitted. Depending on the type of advertiser operation, the receiver listens for a SCAN_REQ or a
CONNECT_REQ message. If the demodulator obtains sync, the header is checked once it is received,
and if it is not a SCAN_REQ or CONNECT_REQ message, the demodulator is stopped immediately.
A SCAN_REQ or CONNECT_REQ message is received into the RX queue given by pParams ->pRxQ, as
described in Section 23.6.3.1. The bCrcErr and bIgnore bits are set according to the CRC result and the
received message. For connectable undirected or scannable advertising, the AdvA field in the message,
along with the TXAdd bit of the received header, is compared to the pParams->pDeviceAddress array and
the pParams->advConfig.deviceAddrType bit, respectively, to see if the message was addressed to this
advertiser. Then, depending on the advertising filter policy given by pParams->advConfig.advFilterPolicy,
the received ScanA or InitA field, along with the RXAdd bit of the received header, is checked against the
white list as described in Section 23.6.4.9, except for a directed advertiser, where the received header is
compared against the peer address as described in Section 23.6.4.4.2. Depending on this comparison, the
actions taken are as given in Table 23-115, where the definition of each action, including the value used
on the bCrcErr and bIgnore bits, is given in Table 23-116. If pParams->advConfig.bStrictLenFilter is 1,
only length fields that are compliant with the Bluetooth low energy specification are considered valid. For a
SCAN_REQ, that means a length field of 12, and for a CONNECT_REQ it means a length field of 34. If
pParams ->advConfig.bStrictLenFilter is 0, all received packets with a length field less than or equal to the
maximum length of an advertiser packet (37, but can be overridden) are considered valid. If the length is
not valid, the receiver is stopped.
Table 23-115. Actions to Take Based on Received Packets for Advertisers (1)
PDU Type

CRC Result

Advertiser
Type

Valid Length

AdvA
Matches Own
Address

Filter Policy

ScanA or
Action
InitA Present
Number
in White List

SCAN_REQ

C, S

Yes

SCAN_REQ

C, S

Yes

1 or 3

SCAN_REQ

C, S

Yes

1 or 3

Yes

SCAN_REQ

C, S

Yes

0 or 2

SCAN_REQ

NOK

C, S

Yes

SCAN_REQ

C, S

SCAN_REQ

CONNECT_REQ

C, D

Yes

CONNECT_REQ

C, D

Yes

2 or 3

CONNECT_REQ

C, D

Yes

2 or 3

Yes

CONNECT_REQ

C, D

Yes

0 or 1

CONNECT_REQ

NOK

C, D

Yes

CONNECT_REQ

C, D

CONNECT_REQ

Other

N/A

No packet received

N/A

(1)

1668

C – connectable undirected; D – connectable directed; S – scannable; X – don't care; N/A – not applicable

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

Table 23-116. Descriptions of the Actions to Take on Received Packets
Action Number

bCrcErr

bIgnore

Description

End operation with BLE_DONE_OK status.

Transmit SCAN_RSP message.

End operation with BLE_DONE_RXERR status.

End operation with BLE_DONE_CONNECT status.

—

Stop receiver immediately and end operation with
BLE_DONE_NOSYNC status.

If a SCAN_REQ packet is received with a length of 12 (or less), it is viewed as an empty packet. This
means that if pParams->rxConfig.bAutoflushEmpty is 1 and the bCrcErr and bIgnore bits are both 0, the
packet is removed from the RX buffer. If a packet is flagged by bIgnore or bCrcErr, it may also be
removed, based on the bits in pParams->rxConfig.
If the packet received did not fit in the RX queue, the packet is received to the end, but the received bytes
are not stored. If the packet would normally not have been discarded from the RX queue based on the bits
in pParams->rxConfig, the command ends.
If, according to Table 23-115 and Table 23-116, the next action is to transmit a SCAN_RSP, the radio
CPU starts the transmitter to transmit this packet. It consists of a header, an advertiser address, and
advertising data. The radio CPU constructs these packets as follows. In the header, the PDU Type bits are
0100b. The TXAdd bit is as shown in pParams->advConfig.devicAddrType. The length is calculated from
the size of the scan response data, pParams->scanRspLen + 6. The RXAdd bit is not used and is 0, along
with the RFU bits. The payload starts with the 6-byte device address, which is read from
pParams->pDeviceAddress. The rest of the payload is read from the pParams->pScanRspData buffer.
After the SCAN_RSP has been transmitted, the command ends.
A trigger to end the operation is set up by pParams->endTrigger. If the trigger defined by this parameter
occurs, the radio operation continues to completion, but the status code after ending is
BLE_DONE_ENDED and the result is FALSE. This can, for instance, be used to stop execution instead of
proceeding with the next chained operation by use of the condition in the command structure. If the
immediate command CMD_STOP is received by the radio CPU, CMD_STOP has the same meaning as
the end trigger occurring, except that the status code after ending is CMD_DONE_STOPPED.
The output structure pOutput contains fields which give information on the command being run. The radio
CPU does not initialize the fields, so this must be done by the system CPU when a reset of the counters is
desired. The fields are updated by the radio CPU as described in the following list. The list also indicates
when interrupts are raised in the system CPU.
• When the ADV*_IND packet has been transmitted, nTXAdvInd is incremented and a TX_DONE
interrupt is raised.
• If a SCAN_RSP packet has been transmitted, nTXScanRsp is incremented afterward, and a
TX_DONE interrupt is raised.
• If a SCAN_REQ is received with CRC OK and the bIgnore is flag cleared, nRXScanReq is
incremented. If the payload length is 12 or less, an RX_EMPTY interrupt is raised. If the payload length
is greater than 12, an RX_OK interrupt is raised.
• If a CONNECT_REQ is received with CRC OK and the bIgnore flag is cleared, nRXConnectReq is
incremented and an RX_OK interrupt is raised.
• If a packet is received with CRC error, nRXNok is incremented and an RX_NOK interrupt is raised.
• If a packet is received and the bIgnore flag is set, nRXIgnored is incremented and an RX_IGNORED
interrupt is raised.
• If a packet is received that did not fit in the RX queue, nRXBufFull is incremented and an
RX_BUF_FULL interrupt is raised.
• If a packet is received, lastRssi is set to the RSSI of that packet.
• If a packet is received, timeStamp is set to a timestamp of the start of that packet. For a
CONNECT_REQ, this can be used to calculate the anchor point of the first packet.
• If the first RX data entry in the RX queue changed state to Finished after a packet was received, an
RX_ENTRY_DONE interrupt is raised.
SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1669

Bluetooth low energy

www.ti.com

23.6.4.4.1 Connectable Undirected-Advertiser Command
A connectable undirected-advertiser operation is started by a CMD_BLE_ADV command. In the command
structure, it has a pParams parameter of the type defined in Table 23-92, and a pOutput parameter of the
type defined in Table 23-98. The operation starts with transmission and operates as described in
Section 23.6.4.4.
A connectable undirected-advertiser operation ends with one of the statuses listed in Table 23-117. After
the operation has ended, the status field of the command structure (2 status bytes listed in Table 23-8)
indicates why the operation ended. In all cases, a COMMAND_DONE interrupt is raised. In each case, it
is indicated if the result is TRUE, FALSE, or ABORT, which decides the next action.
Table 23-117. End of Connectable Undirected-Advertiser Operation
Condition

Status Code

Result

Performed Action Number1 after running receiver.

BLE_DONE_OK

TRUE

Performed Action Number2 and transmitted SCAN_RSP.

BLE_DONE_OK

TRUE

Performed Action Number3 after running receiver.

BLE_DONE_RXERR

TRUE

Performed Action Number4 after running receiver.

BLE_DONE_CONNECT

FALSE

Performed Action Number5 after running receiver.

BLE_DONE_NOSYNC

TRUE

Observed trigger indicated by pParams->endTrigger, then performed
Action Number1, 2, 3, or 5.

BLE_DONE_ENDED

FALSE

Observed CMD_STOP, then performed Action Number1, 2, 3, or 5.

BLE_DONE_STOPPED

FALSE

Received CMD_ABORT.

BLE_DONE_ABORT

ABORT

No space in RX buffer to store received packet.

BLE_ERROR_RXBUF

FALSE

Illegal value of channel

BLE_ERROR_PAR

ABORT

Advertising data or scan response data length field has illegal value.

BLE_ERROR_PAR

ABORT

23.6.4.4.2 Connectable Directed-Advertiser Command
A connectable directed-advertiser operation is started by a CMD_BLE_ADV_DIR command. In the
command structure, it has a pParams parameter of the type defined in Table 23-92, and a pOutput
parameter of the type defined in Table 23-98. The operation starts with transmission and operates as
described in Section 23.6.4.4, with some modifications as described in the following paragraphs.
For the directed advertiser, pParams->pWhiteList points to a buffer containing only the device address of
the device to which to connect. The address type of the peer is given in pParams>advConfig.peerAddrType. The first transmit operation sends an ADV_DIRECT_IND packet. The radio
CPU constructs this packet as follows. In the header, the PDU Type bits are 0001b as shown in Table 23114. The TXAdd bit is as shown in pParams->advConfig.deviceAddrType. The RXAdd bit is as shown in
pParams->advConfig.peerAddrType.
The length is calculated from the size of the advertising data, pParams->advLen + 12. The RFU bits are 0.
The payload starts with the 6-byte device address, which are read from pParams->pDeviceAddress,
followed by the 6-byte peer address read from pParams->pWhiteList. By the Bluetooth low energy
specification, there is no more payload, but a noncompliant message may be constructed by setting
pParams->advLen to a nonzero value. If so, the rest of the payload is read from the pParams->pAdvData
buffer.
The receiver is started after the ADV_DIRECT_IND packet has been transmitted as described in
Section 23.6.4.4, and received packets are processed as described there. When checking the address
against the white list, check the received RXAdd bit against pParams->advConfig.peerAddrType, and
check the received InitA field against pParams->pWhiteList.
A directed-advertiser operation ends with one of the statuses listed in Table 23-118. After the operation
has ended, the status field of the command structure (2 status bytes listed in Table 23-8) indicates why
the operation ended. In all cases, a COMMAND_DONE interrupt is raised. In each case, it is indicated if
the result is TRUE, FALSE, or ABORT, which decides the next action.

1670

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

Table 23-118. End of Directed-Advertiser Operation
Condition

Status Code

Result

Performed Action Number1 after running receiver.

BLE_DONE_OK

TRUE

Performed Action Number3 after running receiver.

BLE_DONE_RXERR

TRUE

Performed Action Number4 after running receiver.

BLE_DONE_CONNECT

FALSE

Performed Action Number5 after running receiver.

BLE_DONE_NOSYNC

TRUE

Observed trigger indicated by pParams->endTrigger, then performed
Action Number1, 3, or 5.

BLE_DONE_ENDED

FALSE

Observed CMD_STOP, then performed Action Number1, 3, or 5.

BLE_DONE_STOPPED

FALSE

Received CMD_ABORT.

BLE_DONE_ABORT

ABORT

No space in RX buffer to store received packet.

BLE_ERROR_RXBUF

FALSE

Illegal value of channel

BLE_ERROR_PAR

ABORT

Advertising data length field has illegal value.

BLE_ERROR_PAR

ABORT

23.6.4.4.3 Nonconnectable Advertiser Command
An advertiser operation that is not connectable is started by a CMD_BLE_ADV_NC command. In the
command structure, it has a pParams parameter of the type defined in Table 23-92, and a pOutput
parameter of the type defined in Table 23-98. The operation starts with transmission and operates as
described in Section 23.6.4.4. After transmission of an ADV_NONCONN_IND, the operation ends without
any receive operation.
An advertiser operation that is not connectable ends with one of the statuses listed in Table 23-119. After
the operation has ended, the status field of the command structure (2 status bytes listed in Table 23-8)
indicates why the operation ended. In all cases, a COMMAND_DONE interrupt is raised. In each case, it
is indicated if the result is TRUE, FALSE, or ABORT, which decides the next action.
Table 23-119. End of Nonconnectable Advertiser Operation
Condition

Status Code

Result

Transmitted ADV_NONCONN_IND.

BLE_DONE_OK

TRUE

Observed trigger indicated by pParams->endTrigger, then finished
transmitting ADV_NONCONN_IND.

BLE_DONE_ENDED

FALSE

Observed CMD_STOP, then finished transmitting
ADV_NONCONN_IND.

BLE_DONE_STOPPED

FALSE

Received CMD_ABORT.

BLE_DONE_ABORT

ABORT

Illegal value of channel

BLE_ERROR_PAR

ABORT

Advertising data length field has illegal value.

BLE_ERROR_PAR

ABORT

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1671

Bluetooth low energy

www.ti.com

23.6.4.4.4 Scannable Undirected-Advertiser Command
A scannable undirected-advertiser operation is started by a CMD_BLE_ADV_SCAN command. In the
command structure, it has a pParams parameter of the type defined in Table 23-92, and a pOutput
parameter of the type defined in Table 23-98. The operation starts with transmission and operates as
described in Section 23.6.4.4.
A scannable undirected-advertiser operation ends with one of the statuses listed in Table 23-120. After the
operation has ended, the status field of the command structure (2 status bytes listed in Table 23-8)
indicates why the operation ended. In all cases, a COMMAND_DONE interrupt is raised. In each case, it
is indicated if the result is TRUE, FALSE, or ABORT, which decides the next action.
Table 23-120. End of Scannable Undirected-Advertiser Operation
Condition

Status Code

Result

Performed Action Number1 after running receiver.

BLE_DONE_OK

TRUE

Performed Action Number2 and transmitted SCAN_RSP.

BLE_DONE_OK

TRUE

Performed Action Number3 after running receiver.

BLE_DONE_RXERR

TRUE

Performed Action Number5 after running receiver.

BLE_DONE_NOSYNC

TRUE

Observed trigger indicated by pParams->endTrigger, then performed
Action Number1, 2, 3, or 5.

BLE_DONE_ENDED

FALSE

Observed CMD_STOP, then performed Action Number1, 2, 3, or 5.

BLE_DONE_STOPPED

FALSE

Received CMD_ABORT.

BLE_DONE_ABORT

ABORT

No space in RX buffer to store received packet.

BLE_ERROR_RXBUF

FALSE

Illegal value of channel

BLE_ERROR_PAR

ABORT

Advertising data or scan response data length field has illegal value.

BLE_ERROR_PAR

ABORT

23.6.4.5 Scanner Command
A scanner operation is started by a CMD_BLE_SCANNER command. In the command structure, it has a
pParams parameter of the type defined in Table 23-93, and a pOutput parameter of the type defined in
Table 23-99. At the start of a scanner operation, the radio CPU waits for the start trigger, then programs
the frequency based on the channel parameter of the command structure. The channel parameter is not
allowed to be in the range from 0 to 36, because these are data channels. The radio CPU sets up the
advertising channel access address and uses the CRC initialization value 0x55 5555. The whitener is set
up as defined in the whitening parameter. The radio CPU then configures the receiver.
Tuned to the correct channel, the radio CPU starts listening for an advertising-channel packet. If sync is
obtained on the demodulator, the message is received into the RX queue. The header is checked, and if it
is not an advertising packet, reception stops and sync search restarted. The bCrcErr and bIgnore bits are
set according to the CRC result and the received message. Depending on the scanning filter policy, given
by pParams->scanConfig.scanFilterPolicy, the received AdvA field in the message, along with the TXAdd
bit of the received header is checked against white list as described in Section 23.6.4.9. For
ADV_DIRECT_IND messages, the received InitA field and RXAdd bit are checked against pParams>deviceAddr and pParams->scanConfig.deviceAddrType, respectively. Depending on this, and whether
the scan is active or passive as signaled in pParams->scanConfig.bActiveScan, the actions taken are as
shown in Table 23-121, where the definition of each action, including the value used on bCrcErr and
bIgnore, is given in Table 23-122. If pParams->scanConfig.bStrictLenFilter is 1, only length fields
compliant with the Bluetooth low energy specification are considered valid. For an ADV_DIRECT_IND,
valid means a length field of 12, and for other ADV*_IND messages valid means a length field in the range
from 6 to 37. If pParams->advConfig.bStrictLenFilter is 0, all received packets with a length field less than
or equal to the maximum length of an advertiser packet (37, but can be overridden) are considered valid.
If the length is not valid, the receiver stops.

1672Radio

Bluetooth low energy

www.ti.com

Table 23-121. Actions on Received Packets by Scanner

(1)

PDU Type

CRC Result

Filter
Policy

AdvA to be
Ignored

AdvA Present
in White List

InitA Match

Active
Scan

Action
Number

ADV_IND

N/A

ADV_IND

Yes

N/A

ADV_IND

Yes

N/A

Yes

ADV_IND

N/A

ADV_IND

N/A

Yes

ADV_IND

Yes

N/A

ADV_IND

NOK

N/A

ADV_SCAN_IND

N/A

ADV_SCAN_IND

Yes

N/A

ADV_SCAN_IND

Yes

N/A

Yes

ADV_SCAN_IND

N/A

ADV_SCAN_IND

N/A

Yes

ADV_SCAN_IND

Yes

N/A

ADV_SCAN_IND

NOK

N/A

ADV_NONCONN_IND

N/A

ADV_NONCONN_IND

Yes

N/A

ADV_NONCONN_IND

N/A

ADV_NONCONN_IND

Yes

N/A

ADV_NONCONN_IND

NOK

N/A

ADV_DIRECT_IND

Yes

ADV_DIRECT_IND

Yes

ADV_DIRECT_IND

Yes

ADV_DIRECT_IND

Yes

ADV_DIRECT_IND

NOK

ADV*_IND with invalid length

Other

N/A

(1)

X = don't care.

Table 23-122. Descriptions of the Actions to Take on Packets Received by Scanner
Action Number

bCrcErr

bIgnore

Description

Continue scanning.

Continue scanning or end operation with BLE_DONE_OK
status.

Perform backoff procedure and send SCAN_REQ and receive
SCAN_RSP if applicable. Then continue scanning or end
operation.

Continue scanning.

—

Stop receiving packet, then continue scanning.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1673

Bluetooth low energy

www.ti.com

If the packet being received did not fit in the RX queue, the packet is received to the end, but the received
bytes are not stored. If the packet would normally not have been discarded from the RX buffer, the
operation ends.
If the action from the received packet is number 3, a SCAN_REQ is transmitted if allowed after a backoff
procedure. This procedure starts with decrementing pParams ->backoffCount. If this variable is 0 after the
decrement, a SCAN_REQ is transmitted. If not, the operation ends. If the action from the received packet
is number 2 or number 3, the next action may be to continue scanning or end the operation. This is
configured with pParams ->scanConfig.bEndOnRpt; if 1, the operation ends, otherwise scanning
continues.
When transmitting a SCAN_REQ message, the radio CPU constructs this packet. In the header, the PDU
Type bits are 0011b. The TXAdd bit is as shown in pParams ->scanConfig.deviceAddrType. The RXAdd
bit is as shown in the TXAdd field of the header of the received ADV_IND or ADV_SCAN_IND message.
The length is calculated from the size of the scan request data, pParams->scanReqLen + 12. The RFU
bits are 0. The payload starts with the 6-byte device address, which is read from pParams >pDeviceAddress, followed by the 6-byte peer address read from the AdvA field of the received message.
By the Bluetooth low energy specification, there is no more payload, but a noncompliant message may be
constructed by setting pParams->scanReqLen to a nonzero value. If so, the rest of the payload is read
from the
pParams->pScanData buffer.
After a SCAN_REQ message is transmitted, the radio CPU configures the receiver and looks for a
SCAN_RSP message from the advertiser to which the SCAN_REQ was sent. If sync is obtained on the
demodulator, the header is checked when it is received, and if it is not a SCAN_RSP message, the
demodulator is stopped immediately. If the header is a SCAN_RSP message, then it is received into the
RX queue. Depending on the received SCAN_RSP, the values of bCrcErr and bIgnore are as given in
Table 23-123. If pParams->scanConfig.bStrictLenFilter is 1, only length fields that are compliant with the
Bluetooth low energy specification are considered valid. For a SCAN_RSP, valid means a length field in
the range from 6 to 37. If pParams->scanConfig.bStrictLenFilter is 0, all received packets with a length
field less than or equal to the maximum length of an advertiser packet (37, but can be overridden) are
considered valid. If the length is not valid, the receiver is stopped.
Table 23-123. Actions on Packets Received by Scanner After Transmission of SCAN_REQ (1)
PDU Type

CRC Result

AdvA Same as in
Request

bCrcErr

bIgnore

SCAN_RSP Result

SCAN_RSP

Failure

SCAN_RSP

Yes

Success

SCAN_RSP

NOK

Failure

SCAN_RSP with
invalid length

–

Failure

Other

N/A

–

Failure

No packet received

N/A

–

Failure

(1)

1674

X = don't care.

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

After receiving or trying to receive a SCAN_RSP message, the backoff parameters are updated by the
radio CPU. The update depends on the result as given in the SCAN_RSP Result column of Table 23-123
and the old values of the backoff parameters. The backoff parameters given in pParams->backoffPar are
updated as shown in Table 23-124. After this update, the radio CPU sets pParams->backoffCount to a
pseudo-random number between 1 and 2pParams->backoffPar.logUpperLimit.
Table 23-124. Update of Backoff Parameters (1)
SCAN_RSP
Result

Old pParams->backoffPar

New pParams >backoffPar

bLastSucceeded

bLastFailed

bLastSucceeded

bLastFailed

logUpperLimit

Failure

logUpperLimit

Failure

min(logUpperLimit+1, 8)

Success

logUpperLimit

Success

max(logUpperLimit-1, 0)

(1)

X = don't care.

If pParams->scanConfig.scanFilterPolicy and pParams->scanConfig.bAutoWlIgnore are both 1, the radio
CPU automatically sets the bWlIgn bit of the white-list entry corresponding to the address from which an
ADV*_IND message was received. This setting is done either after Action Number2 is performed, or after
Action Number3 is performed and a SCAN_RSP is received with the result Success. This prevents
reporting multiple advertising messages from the same device, and scanning the same device repeatedly.
The pseudo-random algorithm is based on a maximum-length 16-bit linear-feedback shift register (LFSR).
The seed is as provided in pParams->randomState. When the operation ends, the radio CPU writes the
current state back to this field. If pParams->randomState is 0, the radio CPU self-seeds by initializing the
LFSR to the 16 LSBs of the RAT. This is done only when the LFSR is first needed (that is, after receiving
an ADV*_IND), so there is some randomness to this value. If the 16 LSBs of the RAT are all 0, another
fixed value is substituted.
When the device enters the scanning state, the system CPU must initialize as follows:
• pParams->backoffCount to 1
• pParams->backoffPar.logUpperLimit to 0
• pParams ->backoffPar.bLastSucceeded to 0
• pParams->backoffPar.bLastFailed to 0
• pParams ->randomState to a true-random value (or a pseudo-random number based on a true-random
seed)
When starting new scanner operations while remaining in the scanning state, the system CPU must keep
pParams->randomState, pParams->backoffCount, and pParams->backoffPar at the values they had at the
end of the last scanner operation.
Two triggers to end the operation are set up by pParams->endTrigger/pParams->endTime and
pParams->timeoutTrigger/pParams->timeoutTime, respectively. If either of these triggers occurs, the radio
operation ends as soon as possible. If these triggers occur while waiting for sync on an ADV*_IND packet,
the operation ends immediately. If they occur at another time, the operation continues until the scan would
otherwise be resumed, and then ends. If the immediate command CMD_STOP is received by the radio
CPU, it has the same meaning as the end trigger occurring, except that the status code after ending is
CMD_DONE_STOPPED. The differences between the two triggers are the status and result at the end of
the operation. Typically, timeoutTrigger can be used at the end of a scan window, while endTrigger can be
used when scanning is to end entirely.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1675

Bluetooth low energy

www.ti.com

The output structure pOutput contains fields that give information on the command being run. The radio
CPU does not initialize the fields, so this must be done by the system CPU when resetting the counters is
desired. The fields are updated by the radio CPU as described in the following list. The list also indicates
when interrupts are raised in the system CPU.
• If a SCAN_REQ packet has been transmitted, nTXScanReq is incremented and a TX_DONE interrupt
is raised.
• If a SCAN_REQ is not transmitted due to the backoff procedure, nBackedOffScanReq is incremented.
• If an ADV*_IND packet is received with CRC OK and the bIgnore flag cleared, nRXAdvOk is
incremented, an RX_OK interrupt is raised, and timeStamp is set to a timestamp of the start of the
packet.
• If an ADV*_IND packet is received with CRC OK and the bIgnore flag set, nRXAdvIgnored is
incremented and an RX_IGNORED interrupt is raised.
• If an ADV*_IND packet is received with CRC error, nRXAdvNok is incremented and an RX_NOK
interrupt is raised.
• If an ADV*_IND packet is received and did not fit in the RX queue, nRXAdvBufFull is incremented and
an RX_BUF_FULL interrupt is raised.
• If a SCAN_RSP packet is received with CRC OK and the bIgnore flag cleared, nRXScanRspOk is
incremented and an RX_OK interrupt is raised.
• If a SCAN_RSP packet is received with CRC OK and the bIgnore flag set, nRXScanRspIgnored is
incremented and an RX_IGNORED interrupt is raised.
• If a SCAN_RSP packet is received with CRC error, nRXScanRspNok is incremented and an RX_NOK
interrupt is raised.
• If a SCAN_RSP packet is received and did not fit in the RX queue, nRXScanRspBufFull is incremented
and an RX_BUF_FULL interrupt is raised.
• If a packet is received, lastRssi is set to the RSSI of that packet.
• If the first RX data entry in the RX queue changed state to Finished after a packet was received, an
RX_ENTRY_DONE interrupt is raised.
A scanner operation ends with one of the statuses listed in Table 23-125. After the operation has ended,
the status field of the command structure (2 status bytes listed in Table 23-8) indicates why the operation
ended. In all cases, a COMMAND_DONE interrupt is raised. In each case, it is indicated if the result is
TRUE, FALSE, or ABORT, which decides the next action.
Table 23-125. End of Scanner Operation
Condition

Status Code

Result

Performed Action Number2 with pParams->scanConfig.bEndOnRpt = 1.

BLE_DONE_OK

TRUE

Performed Action Number3 with pParams->scanConfig.bEndOnRpt = 1 and did not
send SCAN_REQ due to backoff.

BLE_DONE_OK

TRUE

Performed Action Number3 with pParams->scanConfig.bEndOnRpt = 1, sent
SCAN_REQ and received SCAN_RSP with bCrcErr = 0 and bIgnore = 0.

BLE_DONE_OK

TRUE

Performed Action Number3 with pParams->scanConfig.bEndOnRpt = 1, sent
SCAN_REQ and received SCAN_RSP with bCrcErr = 1 or bIgnore = 1.

BLE_DONE_RXERR

TRUE

Performed Action Number3 with pParams->scanConfig.bEndOnRpt = 1, sent
SCAN_REQ, but did not get sync or found wrong packet type or invalid length.

BLE_DONE_NOSYNC

TRUE

Observed trigger indicated by pParams->timeoutTrigger while waiting for sync on
ADV*_IND.

BLE_DONE_RXTIMEOUT

TRUE

Observed trigger indicated by pParams->timeoutTrigger, then performed Action
Number1, 2, 3, 4, or 5.

BLE_DONE_RXTIMEOUT

TRUE

Observed trigger indicated by pParams->endTrigger while waiting for sync on
ADV*_IND.

BLE_DONE_ENDED

FALSE

Observed trigger indicated by pParams->endTrigger, then performed Action Number1,
BLE_DONE_ENDED
2, 3, 4, or 5.

FALSE

Observed CMD_STOP while waiting for sync on ADV*_IND.

BLE_DONE_STOPPED

FALSE

Observed CMD_STOP, then performed Action Number1, 2, 3, 4, or 5.

BLE_DONE_STOPPED

FALSE

Received CMD_ABORT.

BLE_DONE_ABORT

ABORT

1676Radio

Bluetooth low energy

www.ti.com

Table 23-125. End of Scanner Operation (continued)
Condition

Status Code

Result

No space in RX buffer to store received packet

BLE_ERROR_RXBUF

FALSE

Illegal value of channel

BLE_ERROR_PAR

ABORT

Scan request data length field has illegal value.

BLE_ERROR_PAR

ABORT

23.6.4.6 Initiator Command
An initiator operation is started by a CMD_BLE_INITIATOR command. In the command structure, it has a
pParams parameter of the type defined in Table 23-93 and a pOutput parameter of the type defined in
Table 23-99. At the start of an initiator operation, the radio CPU waits for the start trigger, then programs
the frequency based on the channel parameter of the command structure. The channel parameter is not
allowed to be in the range from 0 to 36, because these are data channels. The radio CPU sets up the
advertising channel access address and uses the CRC initialization value 0x55 5555. The whitener is set
up as defined in the whitening parameter. The radio CPU then configures the receiver.
After tuning to the correct channel, the radio CPU starts listening for an advertising channel packet. If sync
is obtained on the demodulator, the message is received into the RX queue. The header is checked, and
if it is not a connectable advertising packet, reception is stopped and sync search is restarted. The
bCrcErr and bIgnore bits are set according to the CRC result and the received message. The parameter
pParams->initConfig.bUseWhiteList determines if the initiator must try to connect to a specific device or
against the white list. If this parameter is 0, the white list is not used, and pParams->pWhiteList points to a
buffer containing only the device address of the device to which to connect. The address type of the peer
is given in pParams->advConfig.peerAddrType. Otherwise, pParams->pWhiteList points to a white list. If
the white list is not used, the received AdvA field in the message is checked against the address found in
pParams->pWhiteList, and the TXAdd bit of the received header is checked against
pParams->initConfig.peerAddrType. If the white list is used, the received AdvA field in the message (along
with the TXAdd bit of the received header) is checked against white list as described in Section 23.6.4.9.
For ADV_DIRECT_IND messages, the received InitA field and RXAdd bit are checked against pParams>deviceAddr and pParams->initConfig.deviceAddrType, respectively. Depending on this, the actions taken
are as listed in Table 23-126, where the definition of each action, including the value used on bCrcErr and
bIgnore, is listed in Table 23-127. If pParams->initConfig.bStrictLenFilter is 1, only length fields compliant
with the Bluetooth low energy specification are considered valid. For an ADV_DIRECT_IND, valid means
a length field of 12, and for ADV_IND messages it means a length field in the range from 6 to 37. If
pParams ->initConfig.bStrictLenFilter is 0, all received packets with a length field less than or equal to the
maximum length of an advertiser packet (37, if not overridden) are considered valid. If the length is not
valid, the receiver is stopped.
Table 23-126. Actions on Packets Received by Initiator (1)
PDU Type

CRC Result

AdvA Match

InitA Match

Action
Number

ADV_IND

N/A

ADV_IND

Yes

N/A

ADV_IND

NOK

N/A

ADV_DIRECT_IND

Yes

ADV_DIRECT_IND

Yes

ADV_DIRECT_IND

NOK

ADV*_IND with invalid length

Other

N/A

(1)

X = don't care.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1677

Bluetooth low energy

www.ti.com

Table 23-127. Descriptions of the Actions to Take on Packets Received by Initiator
Action Number

bCrcErr

bIgnore

Description

Continue scanning

Send CONNECT_REQ and end operation

Continue scanning

—

Stop receiving packet, then continue scanning

If the packet received did not fit in the RX queue, the packet is received to the end, but the received bytes
are not stored. If the packet would normally not have been discarded from the RX buffer, the operation
ends.
If the action from the received packet is 2, a CONNECT_REQ packet is transmitted. When transmitting a
CONNECT_REQ, the radio CPU constructs this packet. In the header, the PDU Type bits are 0101b. The
TXAdd bit is as shown in pParams ->initConfig.deviceAddrType. The RXAdd bit is as shown in the TXAdd
field of the header of the received ADV_IND or ADV_DIRECT_IND message. The length is calculated
from the length of the LLData, pParams->connectReqLen + 12. The RFU bits are 0. The payload starts
with the 6-byte device address, read from pParams ->pDeviceAddress, followed by the 6-byte peer
address read from the AdvA field of the received message. The rest of the payload is read from the
pParams->pConnectData buffer. If pParams ->initConfig.bDynamicWinOffset is 1, the radio CPU replaces
the bytes in the WinSize and WinOffset position with a calculated value as explained in the following
paragraphs. After a CONNECT_REQ message has been transmitted, the operation ends.
Two triggers to end the operation are set up by pParams->endTrigger/pParams->endTime and
pParams->timeoutTrigger/pParams->timeoutTime, respectively. If either of these triggers occurs, the radio
operation ends as soon as possible. If these triggers occur while waiting for sync on an ADV*_IND packet,
the operation ends immediately. If the triggers occur at another time, the operation continues until the
scan would otherwise be resumed, and then ends. If the immediate command CMD_STOP is received by
the radio CPU, it has the same meaning as the end trigger occurring, except that the status code after
ending is CMD_DONE_STOPPED. The differences between the two triggers are the status and result at
the end of the operation. Typically, timeoutTrigger is used at the end of a scan window, while endTrigger
is used when scanning is to end entirely.
If pParams->initConfig.bDynamicWinOffset is 1, the radio CPU performs automatic calculation of the
WinSize and WinOffset parameters in the transmitted message. WinSize is byte 7 of the payload, and
WinOffset is byte 8 and 9. The radio CPU finds the possible start times of the first connection event from
the pParams->connectTime parameter and the connection interval, which are given in 1.25-ms units by
the interval field (byte 10 and 11) from the payload to be transmitted. The possible times of the first
connection event are any whole multiple of connection intervals from pParams->connectTime, which may
be in the past or the future from the start of the initiator command. The radio CPU calculates a WinOffset
parameter to be inserted in the transmitted CONNECT_REQ. The calculated WinOffset ensures that the
transmit window covers the first applicable connection event with enough margin after the end of the
CONNECT_REQ packet. The radio CPU sets up the transmit window (WinOffset and WinSize) so that
there is margin both between the start of the transmit window and the start of the first master packet, and
between the start of the first master packet and the end of the transmit window. The inserted WinSize is
either 1 or 2; ensuring such a margin. The radio CPU writes the calculated values for WinSize and
WinOffset into the corresponding locations in the pParams->pConnectData buffer. The start time of the
first connection event used to transmit the first packet within the signaled transmit window is written back
by the radio CPU in pParams->connectTime. If no connection is made, the radio CPU adds a multiple of
connection intervals to pParams->connectTime, so that it is the first possible time of a connection event
after the operation ended.
The output structure pOutput contains fields that give information on running the command. The radio
CPU does not initialize the fields, so this must be done by the system CPU when a reset of the counters is
desired. The fields are updated by the radio CPU as described in the following list. The list also indicates
when interrupts are raised in the system CPU.
• If a CONNECT_REQ packet has been transmitted, nTXConnectReq is incremented and a TX_DONE
interrupt is raised.
• If an ADV*_IND packet is received with CRC OK and the bIgnore flag is cleared, nRXAdvOk is
incremented, an RX_OK interrupt is raised, and timeStamp is set to a timestamp of the start of the
packet.
1678

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

•
•
•
•
•

If an ADV*_IND packet is received with CRC OK and the bIgnore flag set, nRXAdvIgnored is
incremented and an RX_IGNORED interrupt is raised.
If an ADV*_IND packet is received with CRC error, nRXAdvNok is incremented and an RX_NOK
interrupt is raised.
If an ADV*_IND packet is received and did not fit in the RX queue, nRXAdvBufFull is incremented and
an RX_BUF_FULL interrupt is raised.
If a packet is received, lastRssi is set to the RSSI of that packet
If the first RX data entry in the RX queue changed state to Finished after a packet was received, an
RX_ENTRY_DONE interrupt is raised.

An initiator operation ends with one of the statuses listed in Table 23-128. After the operation has ended,
the status field of the command structure (2 status bytes listed in Table 23-8) indicates why the operation
ended. In all cases, a COMMAND_DONE interrupt is raised. In each case, it is indicated if the result is
TRUE, FALSE, or ABORT, which decides the next action.
Table 23-128. End of Initiator Operation
Condition

Status Code

Result

Performed Action Number2 (transmitted CONNECT_REQ).

BLE_DONE_CONNECT

FALSE

Observed trigger indicated by pParams->timeoutTrigger while waiting for
sync on ADV*_IND.

BLE_DONE_RXTIMEOUT

TRUE

Observed trigger indicated by pParams->timeoutTrigger, then performed
Action Number1, 2, 3, 4, or 5.

BLE_DONE_RXTIMEOUT

TRUE

Observed trigger indicated by pParams->endTrigger while waiting for sync
on ADV*_IND.

BLE_DONE_ENDED

FALSE

Observed trigger indicated by pParams->endTrigger, then performed Action
Number1, 2, 3, or 4.

BLE_DONE_ENDED

FALSE

Observed CMD_STOP while waiting for sync on ADV*_IND.

BLE_DONE_STOPPED

FALSE

Observed CMD_STOP, then performed Action Number1, 2, 3, or 4.

BLE_DONE_STOPPED

FALSE

Received CMD_ABORT.

BLE_DONE_ABORT

ABORT

No space in RX buffer to store received packet

BLE_ERROR_RXBUF

FALSE

Illegal value of channel

BLE_ERROR_PAR

ABORT

LLData length field has illegal value.

BLE_ERROR_PAR

ABORT

23.6.4.7 Generic Receiver Command
The generic receiver command is used to receive physical layer test packets or to receive any packet,
such as in a packet sniffer application.
A generic receiver operation is started by a CMD_BLE_GENERIC_RX command. In the command
structure, CMD_BLE_GENERIC_RX has a pParams parameter of the type defined in Table 23-95, and a
pOutput parameter of the type defined in Table 23-101. At the start of a generic receiver operation, the
radio CPU waits for the start trigger, then programs the frequency based on the channel parameter of the
command structure. The radio CPU sets up the access address defined in pParams->accessAddress and
uses the CRC initialization value defined in pParams->crcInit. The whitener is set up as defined in the
whitening parameter. The radio CPU then configures the receiver.
In a generic receiver operation, the only assumptions made on the packet format are that the 6 LSBs of
the second received byte is a length field which indicates the length of the payload following that byte, and
that a standard Bluetooth low-energy-type CRC is appended to the packet.
When tuned to the correct channel, the radio CPU starts listening for a packet. If sync is obtained on the
demodulator, the message is received into the RX queue (if any). If the length is greater than the
maximum allowed length for Bluetooth low energy advertising packets (37, but can be overridden),
reception is stopped and restarted.
If pParams->pRxQ is NULL, the received packets are be stored. The counters are still updated and
interrupts are generated.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1679

Bluetooth low energy

www.ti.com

If a packet is received with CRC error, the bCrcErr bit is set. The bIgnored flag is never set for the generic
RX command.
If the packet being received did not fit in the RX queue, the packet is received to the end, but the received
bytes are not stored. If the packet would normally not have been discarded from the RX buffer, the
operation ends.
A trigger to end the operation is set up by pParams->endTrigger and pParams->endTime. If the trigger
defined by this parameter occurs, the radio operation ends as soon as possible. If the trigger occurs while
waiting for sync, the operation ends immediately. If the trigger occurs at another time, the operation
continues until the current packet is fully received, and then ends. If the immediate command CMD_STOP
is received by the radio CPU, it has the same meaning as the end trigger occurring, except that the status
code after ending is CMD_DONE_STOPPED. The output structure pOutput contains fields that give
information on the command being run. The radio CPU does not initialize the fields, so this must be done
by the system CPU when a reset of the counters is desired. The fields are updated by the radio CPU, as
described in the following list. The list also indicates when interrupts are raised in the system CPU.
• If a packet is received with CRC OK, nRXOk is incremented and an RX_OK interrupt is raised.
• If a packet is received with CRC error, nRXNok is incremented and an RX_NOK interrupt is raised.
• If a packet is received and did not fit in the RX queue, nRXBufFull is incremented and an
RX_BUF_FULL interrupt is raised.
• If a packet is received, lastRssi is set to the RSSI of that packet
• If a packet is received, timeStamp is set to a timestamp of the start of that packet
• If the first RX data entry in the RX queue changed state to Finished after a packet was received, an
RX_ENTRY_DONE interrupt is raised.
When a packet is received, reception is restarted on the same channel if pParams->bRepeat = 1, the end
event has not been observed, and the packet fits in the receive queue. If pParams->bRepeat = 0, the
operation always ends when a packet is received.
A generic RX operation ends with one of the statuses listed in Table 23-129. After the operation has
ended, the status field of the command structure (2 status bytes listed in Table 23-8) indicates why the
operation ended. In all cases, a COMMAND_DONE interrupt is raised. In each case, it is indicated if the
result is TRUE, FALSE, or ABORT, which decides the next action. The pNextOp field of a generic RX
command structure may point to the same command structure. That way, RX may be performed until the
end trigger, or until the RX buffer becomes full.
Table 23-129. End of Generic RX Operation

1680

Condition

Status Code

Result

Received a packet with CRC OK and pParams->bRepeat = 0

BLE_DONE_OK

TRUE

Received a packet with CRC error and pParams->bRepeat = 0

BLE_DONE_RXERR

TRUE

Observed trigger indicated by pParams->endTrigger while waiting for
sync

BLE_DONE_ENDED

FALSE

Observed trigger indicated by pParams->endTrigger, then finished
receiving packet

BLE_DONE_ENDED

FALSE

Observed CMD_STOP while waiting for sync

BLE_DONE_STOPPED

FALSE

Observed CMD_STOP, then finished receiving packet

BLE_DONE_STOPPED

FALSE

Received CMD_ABORT

BLE_DONE_ABORT

ABORT

No space in RX buffer to store received packet

BLE_ERROR_RXBUF

FALSE

Illegal value of channel

BLE_ERROR_PAR

ABORT

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Bluetooth low energy

www.ti.com

23.6.4.8 PHY Test Transmit Command
The test packet transmitter command may be used to transmit physical layer test packets.
A test packet transmitter operation is started by a CMD_BLE_TX_TEST command. In the command
structure, CMD_BLE_TX_TEST has a pParams parameter of the type defined in Table 23-96, and a
pOutput parameter of the type defined in Table 23-102. At the start of a test TX operation, the radio CPU
waits for the start trigger, then programs the frequency based on the channel parameter of the command
structure. The radio CPU sets up the test mode packet access address and uses the CRC initialization
value 0x55 5555. The whitener is set up as defined in the whitening parameter. To produce PHY test
packets conforming to the Bluetooth low energy Test Specification, the whitener must be disabled.
The radio CPU transmits pParams->numPackets packets, then ends the operation. If pParams>numPackets is 0, transmission continues until the operation ends for another reason (time-out, stop, or
abort command). The time (number of RAT ticks) between the start of each packet is given by pParams>period. If this time is smaller than the duration of a packet, each packet is transmitted as soon as
possible. Each packet is assembled as follows by the radio CPU. The first byte is a header byte,
containing the value of pParams ->packetType, provided this is one of the values listed in Table 23-130.
The next byte is the length byte, which is the value of pParams->payloadLength, and is followed by a
number of payload bytes, which are as listed in Table 23-130. The number of payload bytes is equal to
pParams->payloadLength. If pParams->packetType is 0, the bytes are from the PRBS9 sequence.
Otherwise, all the bytes are the same, as listed in Table 23-130. A 3-byte CRC, according to the Bluetooth
low energy specification, is appended.
Table 23-130. Supported PHY Test Packet Types
Value of Packet Type

Transmitted Bytes

PRBS9 sequence

Repeated 0x0F

Repeated 0x55

PRBS15 sequence

Repeated 0xFF

Repeated 0x00

Repeated 0xF0

Repeated 0xAA

The PRBS15 payload type defined in the Bluetooth low energy standard, which corresponds to payload
type 3, is implemented using the polynomial x15 + x14 + 1. The initialization is taken from the RAT for the
first packet transmitted, and is not reinitialized for subsequent packets.
If pParams->config.overrideDefault is 1, the packet is nonstandard. The header contains the value given in
pParams->packetType, and each byte transmitted is as given in pParams->byteVal. If
pParams->config.bUsePrbs9 is 1, the sequence is generated by XORing each byte of the PRBS9
sequence used for packet type 0 with pParams ->byteVal. If pParams->config.bUsePrbs15 is 1, the
sequence is generated by XORing each byte of the PRBS15 sequence used for packet type 3 with
pParams->byteVal.
If either of the PRBS sequences is used, whitening is disabled regardless of the setting in the whitening
parameter.
A trigger to end the operation is set up by pParams->endTrigger and pParams->endTime. If the trigger
defined by this parameter occurs, the radio operation ends as soon as possible. If the trigger occurs while
waiting between packets, the operation ends immediately. If the trigger occurs at another time, the
operation continues until the current packet is fully transmitted, and then ends. If the immediate command
CMD_STOP is received by the radio CPU, it has the same meaning as the end trigger occurring, except
that the status code after ending is CMD_DONE_STOPPED.
The output structure pOutput contains only the field nTX, and is incremented each time a packet is
transmitted. The radio CPU does not initialize the field, so this must be done by the system CPU when a
reset of the counters is desired. A TX_DONE interrupt is raised each time a packet is transmitted.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1681

Bluetooth low energy

www.ti.com

A PHY test TX operation ends with one of the statuses listed in Table 23-131. After the operation has
ended, the status field of the command structure (2 status bytes listed in Table 23-8) indicates why the
operation ended.In all cases, a COMMAND_DONE interrupt is raised. In each case, it is indicated if the
result is TRUE, FALSE, or ABORT, which decides the next action.
Table 23-131. End of PHY Test TX Operation
Condition

Status Code

Result

Transmitted pParams->numPackets packets.

BLE_DONE_OK

TRUE

Observed trigger indicated by pParams->endTrigger while waiting between
packets.

BLE_DONE_ENDED

FALSE

Observed trigger indicated by pParams->endTrigger, then finished
transmitting packet.

BLE_DONE_ENDED

FALSE

Observed CMD_STOP while waiting between packets.

BLE_DONE_STOPPED

FALSE

Observed CMD_STOP, then finished transmitting packet.

BLE_DONE_STOPPED

FALSE

Received CMD_ABORT.

BLE_DONE_ABORT

ABORT

Illegal value of channel

BLE_ERROR_PAR

ABORT

Illegal value of pParams >packetType

BLE_ERROR_PAR

ABORT

23.6.4.9 White List Processing
A white list is used in advertiser, scanner, and initiator operation. The white list consists of a configurable
number of entries. The white list is an array of entries of the type defined in Table 23-71. The first entry of
the array contains the array size in the size field.
The minimum number of entries in a white list array is 1, but if no white list is to be used,
pParams->pWhiteList may be NULL. The maximum number is at least 8.
Each entry contains one address and three configuration bits. The bEnable bit is 1 if the entry is enabled,
otherwise the address is ignored when doing white-list filtering. The addrType bit indicates if the entry is a
public or random address. The bIgnore bit can be used by a scanner to avoid reporting and scanning the
same device multiple times.
When an address is checked against the white list, the address is compared against the address field of
each entry in the white list. The address is considered present in the white list only if there is an entry
where one or all of the following conditions are met:
• The bEnable bit is 1.
• addrType is equal to the address type of the address to check.
• All bytes of the address array are equal to the bytes of the address to check.
• For scanner only: the bWlIgn bit is 0.
For scanners, the bWlIgn bit may be set in the white list to indicate that a device is ignored even if the
white list entry would otherwise be a match. This feature can be used to check for advertisers that have
already been scanned, or where the advertising data has already been reported. Even if no white list
filtering is performed, this feature may be used. The white list is scanned for devices that match the
address and address type, and where bWlIgn is 1. Such devices are ignored. The bEnable bit is not
checked in this case. It is possible to configure the radio CPU to automatically set the bWlIgn bit, see
Section 23.6.4.5.

23.6.5 Immediate Commands
In addition to the immediate commands from Section 23.3.5, the following immediate command is also
supported.
23.6.5.1 Update Advertising Payload Command
The CMD_BLE_ADV_PAYLOAD command can change the payload buffer for an advertising command.
The command may be issued regardless of whether an advertising command is running or not.

1682

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Proprietary Radio

www.ti.com

The command structure has the format given in Table 23-89. When received, the radio CPU checks if an
advertiser radio operation command is running, using the parameter structure given in pParams of the
immediate command structure. If the advertiser radio operation command is not running, the radio CPU
updates the parameter structure immediately. If a radio operation command is running using the
parameter structure to be updated, the radio CPU only modifies the parameter structure if the payload to
be changed is not currently being transmitted. If the payload to be changed is being transmitted, the radio
CPU stores the request and updates as soon as transmission of the packet has finished.
When updating the parameter structure, the payload to change depends on the payloadType parameter of
the command structure. If payloadType is 0, the radio CPU sets pParams->advLen equal to newLen and
pParams->pAdvData equal to newData. If payloadType is 1, the radio CPU sets pParams->scanRspLen
equal to newLen and pParams->pScanRspData equal to newData. After the update occurs, the radio CPU
raises a TX_BUFFER_CHANGED interrupt (see Section 23.8.2.5). This interrupt is raised regardless of
whether the update was delayed or not.
If any of the parameters are illegal, the radio CPU responds with ParError in CMDSTAT and does not
perform any update. Otherwise, the radio CPU responds with Done in CMDSTAT, which may be done
before the update occurs.

23.7 Proprietary Radio
This section describes proprietary radio command structure, data handling, radio operations commands,
and immediate commands. The commands define a flexible packet handling compatible with the CC110x,
CC111x, CC112x, CC120x, CC2500, and CC251x devices, as well as supporting other legacy modes.

23.7.1 Packet Formats
For compatibility with existing TI parts, the packet format given in Figure 23-9 can be used in most cases.
This packet format is supported through the use of the commands CMD_PROP_TX and CMD_PROP_RX.
Figure 23-9. Standard Packet Format
1 bit to 32 bytes

8 to 32 bits

0 or 1 byte

0 to 255 bytes

0 or 16 bits
(0 to 32 bits)

Preamble

Sync word

Length field

Address

Payload

CRC

A more flexible packet format is also possible, as defined in Figure 23-10. This format is supported by the
commands CMD_PROP_RX_ADV and CMD_PROP_TX_ADV. The format in Figure 23-9 is an example of
this.
Figure 23-10. Advanced Packet Format
1 bit to 32 bytes or
repetition

8 to 32 bits

0 to 32 bits

0 to 8 bytes

Arbitrary

0 or 16 bits
(0 to 32 bits)

Preamble

Sync word

Header

Address

Payload

CRC

23.7.2 Commands
Table 23-132 defines the proprietary radio operation commands.
Table 23-132. Proprietary Radio Operation Commands
ID

Command Name

Supported Devices Description

0x3801

CMD_PROP_TX

CC26x0, CC13x0

Transmit packet

0x3802

CMD_PROP_RX

CC26x0, CC13x0

Receive packet or packets

0x3803

CMD_PROP_TX_ADV

CC26x0, CC13x0

Transmit packet with advanced modes

0x3804

CMD_PROP_RX_ADV

CC26x0, CC13x0

Receive packet or packets with advanced modes

Radio1683

Proprietary Radio

www.ti.com

Table 23-132. Proprietary Radio Operation Commands (continued)
ID

Command Name

Supported Devices Description

0x3805

CMD_PROP_CS

CC13x0

Run carrier sense command

0x3806

CMD_PROP_RADIO_SETUP

CC26x0/CC1350

Set up radio in proprietary mode (used only on CC1350
when operating at 2.4 GHz)

0x3807

CMD_PROP_RADIO_DIV_SETUP

CC13x0

Set up radio in proprietary mode

0x3808

CMD_PROP_RX_SNIFF

CC13x0

Receive packet or packets with sniff mode support

0x3809

CMD_PROP_RX_ADV_SNIFF

CC13x0

Receive packet or packets with advanced modes and
sniff mode support

Table 23-133 defines the proprietary immediate commands.
Table 23-133. Proprietary Immediate Commands
ID

Command Name

Description

0x3401

CMD_PROP_SET_LEN

Set length of packet being received

0x3402

CMD_PROP_RESTART_RX

Stop receiving a packet and go back to sync search

23.7.2.1 Command Data Definitions
This section defines data types used in describing the data structures used for communication between
the system CPU and the radio CPU. The data structures are listed with tables. The Byte Index is the offset
from the pointer to that structure. Multibyte fields are little-endian, and halfword or word alignment is
required. For bit numbering, 0 is the LSB. The R/W column is used as follows:
R: The system CPU can read a result back; the radio CPU does not read the field.
W: The system CPU writes a value, the radio CPU reads it and does not modify the value.
R/W: The system CPU writes an initial value, the radio CPU may modify the initial value.
23.7.2.1.1 Command Structures
For all the radio operation commands, the first 14 bytes are as defined in Table 23-8. Table 23-134
through Table 23-140 define the additional command structures.
Table 23-134. CMD_PROP_TX Command Structure
Byte
Index

Field Name

Bits

Bit Field name

Type

Description

bFsOff

0: Keep frequency synthesizer on after command.
1: Turn frequency synthesizer off after command.

1–2
14

pktConf

Reserved

bUseCrc

0: Do not append CRC.
1: Append CRC.

bVarLen

0: Fixed length
1: Transmit length as first byte

5–7

1684

Reserved

pktLen

Packet length

16–19

syncWord

Sync word to transmit

20–23

pPkt

Pointer to packet

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Proprietary Radio

www.ti.com

Table 23-135. CMD_PROP_TX_ADV Command Structure
Byte
Index

Field Name

Bits

Bit Field name

Type

Description

bFsOff

0: Keep frequency synthesizer on after command.
1: Turn frequency synthesizer off after command.

1–2
14

Reserved

bUseCrc

0: Do not append CRC.
1: Append CRC.

bCrcIncSw

0: Do not include sync word in CRC calculation.
1: Include sync word in CRC calculation.

bCrcIncHdr

0: Do not include header in CRC calculation.
1: Include header in CRC calculation.

pktConf

6–7

Reserved

numHdrBits

Number of bits in header (0 to 32)

16–17

pktLen

Packet length. 0: Unlimited

0: Start packet on a fixed time from the command
start trigger.
1: Start packet on an external trigger (Contact TI
to enable this feature).

bExtTxTrig

1–2

inputMode

Input mode if external trigger is used for TX start.
00: Rising edge
01: Falling edge
10: Both edges
11: Reserved

3–7

source

RAT input event number used for capture if
external trigger is used for TX start.

startConf

preTrigger

Trigger for transition from preamble to sync word.
If this is set to “now," one preamble as configured
in the setup is sent. Otherwise, the preamble is
repeated until this trigger is observed.

20–23

preTime

Time parameter for preTrigger

24–27

syncWord

Sync word to transmit

28–31

pPkt

Pointer to packet, or TX queue for unlimited length

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1685

Proprietary Radio

www.ti.com

Table 23-136. CMD_PROP_RX and CMD_PROP_RX_SNIFF Command Structure
Byte Index Field Name

1686

pktConf

Bits

Bit Field Name

Type

Description

bFsOff

0: Keep frequency synthesizer on after
command.
1: Turn frequency synthesizer off after command.

bRepeatOk

0: End operation after receiving a packet
correctly.
1: Go back to sync search after receiving a
packet correctly.

bRepeatNok

0: End operation after receiving a packet with
CRC error.
1: Go back to sync search after receiving a
packet with CRC error.

bUseCrc

0: Do not check CRC.
1: Check CRC.

bVarLen

0: Fixed length
1: Receive length as first byte.

bChkAddress

0: No address check
1: Check address.

endType

0: Packet is received to the end if end trigger
occurs after sync is obtained.
1: Packet reception is stopped if end trigger
occurs.

filterOp

0: Stop receiver and restart sync search on
address mismatch.
1: Receive packet and mark it as ignored on
address mismatch.

rxConf

RX configuration, see Table 23-143 for details.

16–19

syncWord

Sync word to listen for

maxPktLen

Packet length for fixed length, maximum packet
length for variable length
0: Unlimited or unknown length

address0

Address

address1

Address (Set equal to address0 to accept only
one address. If 0xFF, accept 0x00 as well.)

endTrigger

Trigger classifier for ending the operation

24–27

endTime

Time to end the operation

28–31

pQueue

Pointer to receive queue

32–35

pOutput

Pointer to output structure

36–47

CMD_PROP_RX_SNIFF only: carrier sense options as given in Table 23-142 (CC13x0 only)

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Proprietary Radio

www.ti.com

Table 23-137. CMD_PROP_RX_ADV and CMD_PROP_RX_ADV_SNIFF Command Structure
Byte Index Field Name

pktConf

Bits

Bit Field Name

Type

Description

bFsOff

0: Keep frequency synthesizer on after
command.
1: Turn frequency synthesizer off after command.

bRepeatOk

0: End operation after receiving a packet
correctly.
1: Go back to sync search after receiving a
packet correctly.

bRepeatNok

0: End operation after receiving a packet with
CRC error.
1: Go back to sync search after receiving a
packet with CRC error.

bUseCrc

0: Do not check CRC.
1: Check CRC.

bCrcIncSw

0: Do not include sync word in CRC calculation.
1: Include sync word in CRC calculation.

bCrcIncHdr

0: Do not include header in CRC calculation.
1: Include header in CRC calculation.

endType

0: Packet is received to the end if end trigger
occurs after sync is obtained.
1: Packet reception is stopped if end trigger
occurs.

filterOp

0: Stop receiver and restart sync search on
address mismatch.
1: Receive packet and mark it as ignored on
address mismatch.

rxConf

RX configuration, see Table 23-143 for details.

16–19

syncWord0

Sync word to listen for

20–23

syncWord1

Alternative sync word if nonzero

24–25

maxPktLen

Maximum length of received packets:
0: Unlimited or unknown length

26–27

28–29

hdrConf

0–5

numHdrBits

Number of bits in header (0–32)

6–10

lenPos

Position of length field in header (0–31)

11–15

numLenBits

Number of bits in length field (0–16)

addrType

0: Address after header
1: Address in header

1–5

addrSize

If addrType = 0: Address size in bytes.
If addrType = 1: Address size in bits.

6–10

addrPos

If addrType = 1: Bit position of address in header.
If addrType = 0: Nonzero to extend address with
sync word identifier.

11–15

numAddr

addrConf

Number of addresses in address list

lenOffset

Signed value to add to length field

endTrigger

Trigger classifier for ending the operation

32–35

endTime

Time to end the operation

36–39

pAddr

Pointer to address list

40–43

pQueue

Pointer to receive queue

44–47

pOutput

Pointer to output structure

48–59

CMD_PROP_RX_ADV_SNIFF only: carrier sense options as given in Table 23-142 (CC13x0 only)

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1687

Proprietary Radio

www.ti.com

Table 23-138. CMD_PROP_CS Command Structure (CC13x0 Only)
Byte Index Field Name

Bits
0

Bit Field Name
bFsOffIdle

Type

Description

0: Keep synthesizer running if command ends with
channel IDLE.
1: Turn off synthesizer if command ends with channel
IDLE.

0: Keep synthesizer running if command ends with
channel BUSY.
1: Turn off synthesizer if command ends with channel
BUSY.

csFsConf
1

bFsOffBusy

Reserved

16–27

Carrier sense options as given in Table 23-142.

Table 23-139. CMD_PROP_RADIO_SETUP and CMD_PROP_RADIO_DIV_SETUP Command
Structure
Byte
Index
14–15

16–19

Field Name

modulation

symbolRate

Bits

Bit Field Name

Type

Description

0–2

modType

0: FSK
1: GFSK
Others: Reserved

3–15

deviation

Deviation (250-Hz steps) for FSK modulations

0:3

preScale

Prescaler value (see Section 23.7.5.2)

4–7
8–28

Reserved, set to 0
rateWord

29–31

nPreamBytes

Receiver bandwidth, see Table 23-147
1–18: Legacy mode (bandwidth 88–4240 kHz)
(CC26x0 and CC13x0)
32–52: Normal mode (bandwidth 45–4240 kHz)
(CC13x0)

0: 1 preamble bit
1–16: Number of preamble bytes
18, 20, ..., 30: Number of preamble bytes
31: 4 preamble bits
32: 32 preamble bytes
Others: Reserved

00: Send 0 as the first preamble bit.
01: Send 1 as the first preamble bit.
10: Send same first bit in preamble and sync word.
11: Send different first bit in preamble and sync word.

preamConf

6–7

1688Radio

Reserved, set to 0

rxBw

0–5

Rate word (see Section 23.7.5.2)

preamMode

Proprietary Radio

www.ti.com

Table 23-139. CMD_PROP_RADIO_SETUP and CMD_PROP_RADIO_DIV_SETUP Command
Structure (continued)
Byte
Index

Field Name

Bits

Bit Field Name

Type

Description

0–5

nSwBits

Number of sync word bits. Valid values are from 8 to
32.

bBitReversal

0: Use positive deviation for 1.
1: Use positive deviation for 0.

bMsbFirst

0: LSB transmitted first
1: MSB transmitted first

Select Coding:
0000: Uncoded binary modulation
1000: Long Range Mode
1010: Manchester coded binary modulation (only
CC13x0 FSK/GFSK)
Others: Reserved

8–11

22–23

24–25

formatConf

fecMode

Reserved

13–15

000: No whitening
001: CC1101 and CC2500 compatible whitening
010: PN9 whitening without byte reversal
011: Reserved
100: No whitener, 32-bit IEEE 802.15.4g compatible
CRC (only CC13x0)
101: IEEE 802.15.4g compatible whitener and 32-bit
CRC (only CC13x0)
110: No whitener, dynamically IEEE 802.15.4g
compatible 16-bit or 32-bit CRC (only CC13x0)
111: Dynamically IEEE 802.15.4g compatible
whitener and 16-bit or 32-bit CRC (only CC13x0)

whitenMode

0–2

frontEndMode

0x00: Differential mode
0x01: Single-ended mode RFP
0x02: Single-ended mode RFN
0x05 Single-ended mode RFP with external front-end
control on RF pins (RFN and RXTX)
0x06 Single-ended mode RFN with external front-end
control on RF pins (RFP and RXTX)
Others: Reserved

biasMode

0: Internal bias
1: External bias

config

4-9

analogCfgMode

0x00: Write analog configuration. Required first time
after boot and when changing frequency band or
front-end configuration.
0x2D: Keep analog configuration. May be used after
standby or when changing mode with the same
frequency band and front-end configuration.
Others: Reserved

bNoFsPowerUp

0: Power up frequency synthesizer.
1: Do not power up frequency synthesizer.

11–15

Reserved

26–27

txPower

Output power setting, use value from SmartRF
Studio. See Section 23.3.4.16 for more details.

28–31

pRegOverride

Pointer to a list of hardware and configuration
registers to override. If NULL, no override is used.

32–33

centerFreq

CMD_PROP_RADIO_DIV_SETUP only: Center
frequency of the band. To be used in the initial
parameter computations.

34–35

intFreq

CMD_PROP_RADIO_DIV_SETUP only: Intermediate
frequency to use for RX, in MHz on 4.12 signed
format. TX will use same intermediate frequency if
supported, otherwise 0.
0x8000: Use default.

loDivider

CMD_PROP_RADIO_DIV_SETUP only: Divider
setting to use. See the Smart RF Studio for the
recommended settings per device and band.

Radio1689

Proprietary Radio

www.ti.com

Table 23-140. CMD_PROP_SET_LEN Command Structure
Byte Index

Field Name

0–1

RXLen

Bit Field
Name

Bits

Type

Description

Payload length to use

23.7.2.2 Output Structures
Table 23-141. Receive Commands

1690

Byte Index

Field Name

Type

Description

0–1

nRXOk

R/W

Number of packets that have been received with payload, CRC OK and
not ignored

2–3

nRXNok

R/W

Number of packets that have been received with CRC error

nRXIgnored

R/W

Number of packets that have been received with CRC OK and ignored
due to address mismatch

nRXStopped

R/W

Number of packets not received due to illegal length or address mismatch
with pktConf.filterOp = 1

nRXBufFull

R/W

Number of packets that have been received and discarded due to lack of
buffer space

lastRssi

RSSI of last received packet. RSSI is captured when sync word is found.

8–11

timeStamp

Timestamp of last received packet

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Proprietary Radio

www.ti.com

23.7.2.3 Other Structures and Bit Fields
Table 23-142. Carrier Sense Fields for CMD_PROP_RX_SNIFF, CMD_PROP_RX_ADV_SNIFF, and
CMD_PROP_CS (Only Applicable for CC13x0)
Byte
Index

Field Name

Bits

Bit Field Name

Type

Description

bEnaRssi

If 1, enable RSSI as a criterion.

bEnaCorr

If 1, enable correlation as a criterion.

0: Busy if either RSSI or correlation indicates
BUSY.
1: Busy if both RSSI and correlation indicates
BUSY.

csConf

operation

busyOp

0: Continue carrier sense on channel BUSY.
1: End carrier sense on channel BUSY.
For an RX command, the receiver continues
when carrier sense ends, then it does not end
if the channel goes IDLE.

idleOp

0: Continue on channel Idle.
1: End on channel Idle.

timeoutRes

0: Time-out with channel state Invalid treated
as BUSY.
1: Time-out with channel state Invalid treated
as IDLE.

rssiThr

RSSI threshold

numRssiIdle

Number of consecutive RSSI measurements
below the threshold needed before the channel
is declared IDLE.

numRssiBusy

Number of consecutive RSSI measurements
above the threshold needed before the channel
is declared BUSY.

4–5

corrPeriod

Number of RAT ticks for a correlation
observation periods.

0–3

numCorrInv

Number of subsequent correlation tops with
maximum corrPeriod RAT ticks between them
needed to go from IDLE to INVALID.

4–7

numCorrBusy

Number of subsequent correlation tops with
maximum corrPeriod RAT ticks between them
needed to go from INVALID to BUSY.

corrConfig

csEndTrigger

Trigger classifier for ending the carrier sense

8–11

csEndTime

Time to end carrier sense.

Radio1691

Proprietary Radio

www.ti.com

Table 23-143. Receive Queue Entry Configuration Bit Field

(1)

Bits

Bit Field Name

Description

bAutoFlushIgnored

If 1, automatically discard ignored packets from RX queue.

bAutoFlushCrcErr

If 1, automatically discard packets with CRC error from RX queue.

Reserved

bIncludeHdr

If 1, include the received header or length byte in the stored packet; otherwise
discard it.

bIncludeCrc

If 1, include the received CRC field in the stored packet; otherwise discard it. This
requires pktConf.bUseCrc to be 1.

bAppendRssi

If 1, append an RSSI byte to the packet in the RX queue.

bAppendTimestamp

If 1, append a timestamp to the packet in the RX queue.

bAppendStatus

If 1, append a status byte to the packet in the RX queue.

7
(1)

This bit field is used for the RXConf byte of the parameter structures.

Table 23-144. Receive Status Byte Bit Field (1)
Bits

Bit Field Name

Description

0–4

addressInd

Index of address found (0 if not applicable)

syncWordId

0 for primary sync word, 1 for alternate sync word

6–7

result

00: Packet received correctly, not ignored
01: Packet received with CRC error
10: Packet received correctly, but can be ignored
11: Packet reception was aborted

(1)

A byte of this bit field is appended to the received entries if configured.

23.7.3 Interrupts
The radio CPU signals events back to the system CPU using firmware-defined interrupts. Table 23-145
lists the interrupts to be used by the proprietary commands. Each interrupt may be enabled individually in
the system CPU. Details for when the interrupts are generated are given in Section 23.7.4 and
Section 23.7.5.
Table 23-145. Interrupt Definitions
Interrupt Number

Interrupt Name

Description

COMMAND_DONE

A radio operation command has finished.

LAST_COMMAND_DONE

The last radio operation command in a chain of commands has
finished.

TX_ENTRY_DONE

For transmission of packets with unlimited length: Reading from
a TX entry is finished.

RX_OK

Packet received with CRC OK, payload, and is not to be
ignored.

RX_NOK

Packet received with CRC error.

RX_IGNORED

Packet received with CRC OK, but is to be ignored.

RX_BUF_FULL

Packet received did not fit in RX buffer.

RX_ENTRY_DONE

RX queue data entry changing state to FINISHED.

RX_DATA_WRITTEN

Data written to partial read RX buffer.

RX_N_DATA_WRITTEN

Specified number of bytes written to partial read RX buffer.

RX_ABORTED

Packet reception stopped before packet was done.

SYNTH_NO_LOCK

The synthesizer has reported loss of lock (only valid for
CC13x0).

MODULES_UNLOCKED

As part of the boot process, the CM0 has opened access to RF
core modules and memories.

BOOT_DONE

The RF core CPU boot is finished.

INTERNAL_ERROR

The radio CPU has observed an unexpected error.

1692Radio

Proprietary Radio

www.ti.com

23.7.4 Data Handling
For the proprietary mode TX commands, data received over the air is stored in a receive queue. Partialread RX buffers are supported, and mandatory for unlimited length. Data transmitted is fetched from a
specific buffer.
23.7.4.1 Receive Buffers
A packet being received is stored in an RX buffer. First, a length byte or word is stored if configured in the
RX entry by config.lenSz, and calculated from the length received over the air and the configuration of
appended information, or for a partial-read RX buffer initialized to maximal possible size of that segment,
and set to the length of the segment in one buffer when finished.
Following the optional length field, the received header is stored as received over the air if
RXConf.bIncludeHdr is 1. This header is the length byte for CMD_PROP_RX and a field with up to 32 bits
for CMD_PROP_RX_ADV. In the case of the 32-bits header for the CMD_PROP_RX_ADV, the last byte
of the header is padded with zeros in the MSBs if the number of bits does not divide by 8, and is followed
by the received address (if configured) and the payload.
If RXConf.bIncludeCrc is 1, the received CRC value is stored in the RX buffer; otherwise, it is not stored,
but only used to check the CRC result. If RXConf.bAppendRssi is 1, a byte indicating the received RSSI
value is appended. If RXConf.bAppendStatus is 1, a status byte of the type defined in Table 23-144 is
appended. If RXConf.bAppendTimeStamp is 1, a timestamp indicating the start of the packet is appended.
This timestamp corresponds to the ratmr_t data type. Though the timestamp is multibyte, no word-address
alignment is made, so the timestamp must be written and read byte-wise.
If the reception of a packet is aborted, the packet is immediately removed from the receive queue, except
if a partial-read RX entry is used. In that case, the RSSI, Timestamp, and Status fields are appended if
configured (except if no more buffer space is available), and the Status byte indicates that the reception
was aborted.
Figure 23-11 shows the format of an entry element in the RX queue.
Figure 23-11. Receive Buffer Entry Element

0±2 bytes
Element
length

0±4 bytes
Header/length
byte

n bytes
Payload

0±4 bytes
Received
CRC

0 or 1 byte 0 or 4 bytes
RSSI

Timestamp

0 or 1 byte
Status

An RX_ENTRY_DONE interrupt is raised whenthe state of an RX entry changes to FINISHED. Depending
on the type of RX entry used, this means:
• For a general or pointer entry, an RX_ENTRY_DONE interrupt is raised after a packet is fully received,
unless the packet is automatically flushed.
• For a multielement entry, an RX_ENTRY_DONE interrupt is raised when a new buffer is allocated and
a new entry was taken into use, or when a buffer is finished and fills the entire entry.
• For a partial-read entry, an RX_ENTRY_DONE interrupt is raised when an RX entry is full, so writing
must continue in the next entry.
For partial-read entries, an RX_Data_Written interrupt is raised whenever data is written to the receive
buffer. An RX_N_Data_Written interrupt is raised whenever a multiple of config.irqIntv (as given in the
data entry) bytes have been written since the start of the packet.
23.7.4.2 Transmit Buffers
The transmit operations contain a buffer with the data to be transmitted. The number of bytes in this buffer
is given by pktLen. For the CMD_PROP_TX command, the length given in pktLen is transmitted as the
first byte if pktConf.bVarLen is 1, and then followed by the contents of the transmit buffer.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1693

Proprietary Radio

www.ti.com

For CMD_PROP_TX_ADV, the first bytes of the buffer contain the header if the header length is greater
than 0. The number of bytes is the number of bits in the header divided by 8, rounded up. The MSBs of
the last header byte are not sent if the number of bits does not divide by 8. If a length field is to be
transmitted using CMD_PROP_TX_ADV, it must be given explicitly from the system side as part of the
header.
If unlimited length is configured, a TX queue is used instead of one buffer. In this case, transmission of
payload continues until the queue is emptied. Every time transmission from one entry is finished, meaning
reading continues from the next entry or the entire payload is entered into the modem, a
TX_ENTRY_DONE interrupt is raised.

23.7.5 Radio Operation Command Descriptions
Before running any of the proprietary RX or TX radio operation commands, the radio must be set up in
proprietary mode using the command CMD_PROP_RADIO_SETUP or
CMD_PROP_RADIO_DIV_SETUP, or in another compatible mode with CMD_RADIO_SETUP. Otherwise,
the operation ends with an error. The RX and TX commands also require the CMD_FS command to
program the synthesizer, which can typically be done by a command chain where an RX or TX command
follows immediately after the CMD_FS.
23.7.5.1 End of Operation
The status field of the command issued is updated during the operation. When submitting the command,
the system CPU must write this field with a state of IDLE. During the operation, the radio CPU updates the
field to indicate the operation mode. When the operation is done, the radio CPU writes a status indicating
that the operation is finished. Table 23-146 lists the status codes used by a proprietary radio operation.
Table 23-146. Proprietary Radio Operation Status Codes
Number

Name

Description

Operation not finished
0x0000

IDLE

Operation not started

0x0001

PENDING

Waiting for start trigger

0x0002

ACTIVE

Running operation

Operation finished normally
0x3400

PROP_DONE_OK

Operation ended normally

0x3401

PROP_DONE_RXTIMEOUT

Operation stopped after end trigger while waiting for sync

0x3402

PROP_DONE_BREAK

RX stopped due to time-out in the middle of a packet

0x3403

PROP_DONE_ENDED

Operation stopped after end trigger during reception

0x3404

PROP_DONE_STOPPED

Operation stopped after stop command

0x3405

PROP_DONE_ABORT

Operation aborted by abort command

0x3406

PROP_DONE_RXERR

Operation ended after receiving packet with CRC error

0x3407

PROP_DONE_IDLE

Carrier sense operation ended because of idle channel (valid only for
CC13x0)

0x3408

PROP_DONE_BUSY

Carrier sense operation ended because of busy channel (valid only for
CC13x0)

0x3409

PROP_DONE_IDLETIMEOUT

Carrier sense operation ended because of time-out with
csConf.timeoutRes = 1 (valid only for CC13x0)

0x340A

PROP_DONE_BUSYTIMEOUT

Carrier sense operation ended because of time-out with
csConf.timeoutRes = 0 (valid only for CC13x0)

Operation finished with error
0x3800

PROP_ERROR_PAR

Illegal parameter

0x3801

PROP_ERROR_RXBUF

No RX buffer large enough for the received data available at the start of a
packet

0x3802

PROP_ERROR_RXFULL

Out of RX buffer during reception in a partial read buffer

0x3803

PROP_ERROR_NO_SETUP

Radio was not set up in proprietary mode

0x3804

PROP_ERROR_NO_FS

Synthesizer was not programmed when running RX or TX

1694Radio

Proprietary Radio

www.ti.com

Table 23-146. Proprietary Radio Operation Status Codes (continued)
Number

Name

Description

0x3805

PROP_ERROR_RXOVF

TX overflow observed during operation

0x3806

PROP_ERROR_TXUNF

TX underflow observed during operation

The conditions for giving each status are listed for each operation. Some of the error causes listed in
Table 23-146 are not repeated in these lists. If CMD_STOP or CMD_ABORT is received while waiting for
the start trigger, the end cause is DONE_STOPPED or DONE_ABORT, with an end result of FALSE and
ABORT, respectively. In some cases, general error causes may occur. For all these error cases, the result
of the operation is ABORT.
23.7.5.2 Proprietary Mode Setup Command
For proprietary mode radio, the CMD_PROP_RADIO_SETUP and CMD_PROP_RADIO_DIV_SETUP
commands are used instead of CMD_RADIO_SETUP. When CMD_PROP_RADIO_SETUP or
CMD_PROP_RADIO_DIV_SETUP is executing, trim values are read from FCFG1 unless they have been
provided elsewhere (for more details, see Section 23.3.3.1.2).
On start, the radio CPU sets up parameters for the proprietary mode with parameters given in
Table 23-139. The modulation.modType parameter selects between GFSK and unshaped FSK. For FSK
and GFSK, modulation.deviation gives the deviation in 250-Hz steps. The radio CPU uses this parameter
to calculate a proper shape for use in TX, or uses a precalculated shape for some typical deviations.
The symbol rate is programmed with symbolRate. The parameters are passed directly to the modem and
may be calculated using an external tool. The symbol rate is given by Equation 16.
fbaud = (R × fclk) / (p × 220)

where
•
•
•
•

f baud is the obtained baud rate.
f clk is the system clock frequency of 24 MHz.
R is the rate word given by symbolRate.rateWord.
p is the prescaler value, given by symbolRate.preScale, which can be from 4 to 15.

(16)

The rxBw parameter gives the receiver bandwidth. Values from 32 to 52 give the supported bandwidths
with the recommended settings. Values from 1 to 18 give the same bandwidths as settings from 35 to 52,
for the CC26x0 and CC13x0 devices. Table 23-147 summarizes the values supported and corresponding
settings are summarized in . These signals are also in calculation of other register settings.
Table 23-147. Receiver Bandwidth Settings
Setting CC26x0
and CC13x0

Setting Only
CC13x0

Receiver
Bandwidth
(868 MHz)

Receiver
Bandwidth
(915 MHz)

Receiver
Bandwidth
(2432 MHz)

Default Intermediate
Frequency

–

38.9 kHz

41.0 kHz

43.5 kHz (CC1350)

250 kHz

–

49.0 kHz

51.6 kHz

54.9 kHz (CC1350)

250 kHz

–

58.9 kHz

62.1 kHz

66.0 kHz (CC1350)

250 kHz

77.7 kHz

81.9 kHz

87.1 kHz

250 kHz

98.0 kHz

103.3 kHz

109.8 kHz

250 kHz

117.7 kHz

124.1 kHz

131.9 kHz

250 kHz

155.4 kHz

163.8 kHz

174.2 kHz

500 kHz

195.9 kHz

206.5 kHz

219.6 kHz

500 kHz

235.5 kHz

248.2 kHz

263.9 kHz

500 kHz

310.8 kHz

327.6 kHz

348.3 kHz

1 MHz

391.8 kHz

413.0 kHz

439.1 kHz

1 MHz

470.9 kHz

496.4 kHz

527.8 kHz

1 MHz

621.6 kHz

655.3 kHz

696.7 kHz

1 MHz

783.6 kHz

826.0 kHz

878.2 kHz

1 MHz

Radio1695

Proprietary Radio

www.ti.com

Table 23-147. Receiver Bandwidth Settings (continued)
Setting CC26x0
and CC13x0

Setting Only
CC13x0

Receiver
Bandwidth
(868 MHz)

Receiver
Bandwidth
(915 MHz)

Receiver
Bandwidth
(2432 MHz)

Default Intermediate
Frequency

941.8 kHz

992.8 kHz

1055.6 kHz

1 MHz

1243.2 kHz

1310.5 kHz

1393.3 kHz

1 MHz

1567.2 kHz

1652.1 kHz

1756.4 kHz

1 MHz

1883.7 kHz

1985.7 kHz

2111.1 kHz

1 MHz

2486.5 kHz

2621.1 kHz

2786.7 kHz

1 MHz

3134.4 kHz

3304.2 kHz

3512.9 kHz

1 MHz

3767.4 kHz

3971.4 kHz

4222.2 kHz

1 MHz

Others

Reserved

The CMD_PROP_RADIO_DIV_SETUP command contains settings for frequency band and intermediate
frequency. The center frequency of the band to use is given by centerFreq, and is used to calculate the
transmitter shaping filter and the TX IF. The divider to use in the synthesizer is given by loDivider. The
user must ensure that the setting is compatible with the given frequency. A value of 2 is allowed only for
devices supporting operation in the 2.4-GHz band. In the CMD_PROP_RADIO_SETUP command,
centerFreq defaults to 2432 MHz and loDivider defaults to 2.
For CMD_PROP_RADIO_DIV_SETUP, the intermediate frequency can be specified through the intFreq
parameter, which calculates the setting in the modem for RX and is written to the configuration parameter
area. If this parameter is 0x8000 and for CMD_PROP_RADIO_SETUP, a default intermediate frequency
as given in Table 23-147 is used.
The preamConf setting gives the preamble. The preamble is a sequence of 1010... or 0101..., where
preamConf.preamMode gives the first transmitted bit. For more than 16 bytes, only an even number of
bytes is supported. Setting preamConf.nPreamBytes = 31 gives a 4-bit preamble.
The formatConf setting is used for various setup of the packet format. The sync word length is given by
nSwBits, which can be up to 32 bits. The bit polarity for FSK type modulation is given by bBitReversal,
which must be 1 for compatibility with CC1101. The bit ordering is given by bMsbFirst, where 1 gives
compatibility with the CC1101 device, and so forth. The whitenMode setting can select a whitener
scheme. Other whiteners are obtained using override settings. Details of the IEEE 802.15.4g settings are
given in Section 23.7.5.2.1. The fecMode setting can be used to change the encoding of the transmitted or
received signal. For long-range mode (fecMode = 8), the nSwBits setting and the sync word programmed
in the RX and TX commands are ignored, and a hard-coded 64-bit sync word with good performance is
used. Setting fecMode to 10 enables Manchester coding. Only encoding and decoding of the payload and
CRC is supported. A 0 will be encoded as 01b and a 1 as 10b. More information about Manchester coding
can be found in the Proprietary RF user's guide in the CC13x0SDK.
The command sets up a 16-bit CRC with the polynomial x16 + x15 + x2 + 1 and initialization of all 1s. This is
compatible with the CC1101 device. Other polynomials, lengths, and initializations can be obtained by
parameter overrides.
The txPower parameter is used to set the output power. For CC13x0, in order to set maximum output
power (+14 dBm), changes must also be made to the CCFG area. In the ccfg.c distributed through
cc13xxware by TI, set CCFG_FORCE_VDDR_HH to 1. Essentially this will increase the VDDR level,
making it possible to use +14 dBm output power. However, setting CCFG_FORCE_VDDR_HH to 1 also
increases the overall power consumption. For all output power settings other than +14 dBm, TI
recommendssetting CCFG_FORCE_VDDR_HH to 0 (default in ccfg.c distributed by TI), to achieve the
lowest possible average power consumption.
The pRegOverride parameter gives a pointer to an override structure, just as the one given for
CMD_RADIO_SETUP. This parameter can be used to override parameters calculated from the other
settings in the commands, as well as from other parameters. If the value is NULL, no overrides are used.

1696

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Proprietary Radio

www.ti.com

23.7.5.2.1 IEEE 802.15.4g Packet Format (CC13x0 Only)
IEEE 802.15.4g PHY, including header, is supported by using the CMD_PROP_RX_ADV and
CMD_PROP_TX_ADV commands.
The radio is configured to IEEE 802.15.4g mode by setting the formatConf.whitenMode field to the values
4, 5, 6, or 7, and formatConf.bMsbFirst must be set to 1 using the CMD_PROP_RADIO_DIV_SETUP
command. For the CMD_PROP_TX_ADV and CMD_PROP_RX_ADV commands, pktConf.bCrcIncSw and
pktConf.bCrcIncHdr must both be set to 0. For CMD_PROP_RX_ADV, hdrConf.numHdrBits must be set
to 16, hdrConf.lenPos must be set to 0, hdrConf.numLenBits must be set to 11, and lenOffset must be 4.
When formatConf.whitenMode is 5 or 7, the radio is configured to produce the 32-bit CRC and whitening
defined in IEEE 802.15.4g. When formatConf.whitenMode is 6 or 7, the radio also processes the headers
in both receive and transmit as follows:
• If bit 15 of the header (counted from the LSB) is 1, the frame is assumed to consist of only a header,
with no payload or CRC.
• If bit 12 of the header (counted from the LSB) is 1, the 16-bit CRC defined in IEEE 802.15.4g is
assumed instead of the 32-bit CRC. For TX, 2 is added to the length offset to account for this,
assuming the CRC is included in the received frame length.
• For mode 7: If bit 11 of the header (counted from the LSB) is 1, whitening is enabled; otherwise it is
disabled.
NOTE: For modes 6 and 7, the transmitter adjusts CRC and whitening automatically based on
transmitted PHY header. However, for this feature to work properly, extended preamble must
be used (that is, CMD_PROP_TX_ADV.preTrigger.triggerType cannot be set to
TRIG_NOW). As a workaround, set preTrigger.triggerType to TRIG_REL_START,
preTrigger.pastTrig to 1 and preTime to 0. This will give normal preamble as configured.

NOTE: The IEEE 802.15.4g PHY header must be presented MSB first to the RF Core. In IEEE
802.15.4g specification, the payload part is LSB first, however the payload length info in
physical layer header (PHR) is MSB first. This means that the payload must be flipped in the
CM-3. This can be achieved with the CM3 assembly instruction RBIT.

The following example shows how to send a CRC-32 IEEE 802.15.4g frame with whitening enabled using
the automatic headers processing feature (formatConf.whitenMode = 7).
/*
* Prepare the .15.4g PHY header
* MS=0, Length MSBits=0, DW and CRC settings read from 15.4g header (PHDR) by
RF core.
* Total length = transmit_len (payload) + CRC length
*
* The Radio will flip the bits around, so tx_buf[0] must have the
* length LSBs (PHR[15:8] and tx_buf[1] will have PHR[7:0]
*/
/* Length in .15.4g PHY HDR includes the CRC but not the HDR itself */
uint16_t total_length;
total_length = transmit_len + CRC_LEN; /* CRC_LEN is 2 for CRC16 and 4 for CRC-32 */
tx_buf[0] = total_length & 0xFF;
tx_buf[1] = (total_length >> 8) + 0x08 + 0x0; /* Whitening and CRC-32 bits */
tx_buf[2] = data;

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1697

Proprietary Radio

www.ti.com

NOTE: When IEEE 802.15.4g mode is configured (CMD_PROP_RADIO_SETUP with
formatConf.whitenMode = 4, 5, 6, or 7), transmitting packets using unlimited length (pktLen =
0, pPkt pointing to a TX queue) and 32-bit CRC is not supported.

NOTE: To ensure correct crc-16 calculation when radio is configured for IEEE 802.15.4g, two
overrides are needed: (uint32_t)0x943, (uint32_t)0x963, these overrides must be added to
the override array.

An MCE patch is necessary to support FEC, mode switch, or other advanced features of IEEE 802.15.4g
PHY.
23.7.5.3 Transmitter Commands
There are two commands for sending packets, CMD_PROP_TX and CMD_PROP_TX_ADV. The latter
gives more flexibility in how the packet can be formed. Details of this are described in Section 23.7.5.3.1
and Section 23.7.5.3.2, respectively.
Both commands require the radio is set up in a compatible mode (such as proprietary mode), and that the
synthesizer is programmed using CMD_FS.
For both commands, after the packet has been transmitted, the frequency synthesizer is turned off when
the command ends if pktConf.bFsOff is 1. If pktConf.bFsOff is 0, the synthesizer keeps running, so that
the command must either be followed by one of the following:
• An RX or TX command (which operate on the same frequency)
• A CMD_FS_OFF command to turn off the synthesizer
or
Table 23-148 lists the end statuses for use with CMD_PROP_TX and CMD_PROP_TX_ADV. This status
decides the next operatio (see Section 23.7.5.1).
Table 23-148. End of Radio CMD_PROP_TX and CMD_PROP_TX_ADV Commands
Condition

Status Code

Result

Transmitted packet

PROP_DONE_OK

TRUE

Received CMD_STOP while transmitting packet and finished transmitting
packet.

PROP_DONE_STOPPED

FALSE

Received CMD_ABORT while transmitting packet.

PROP_DONE_ABORT

ABORT

Observed illegal parameter.

PROP_ERROR_PAR

ABORT

Command sent without setting up the radio in a supported mode using
CMD_PROP_RADIO_SETUP or CMD_RADIO_SETUP.

PROP_ERROR_NO_SETUP

ABORT

Command sent without the synthesizer being programmed.

PROP_ERROR_NO_FS

ABORT

TX underflow observed during operation.

PROP_ERROR_TXUNF

ABORT

23.7.5.3.1 Standard Transmit Command, CMD_PROP_TX
The CMD_PROP_TX command transmits a packet with the format from Table 23-136. The parameters
are as given in Table 23-132.
The packet transmission starts at the given start trigger, with a fixed delay. The modem first transmits the
preamble and sync word as configured. The sync word to transmit is given in the syncWord field, in the
LSBs if less than 32 bits are used. The word is transmitted in the bit order programmed in the radio.
If pktConf.bVarLen is 1, a length byte equal to the value of pktLen is sent next. After this, the content of
the buffer pointed to by pPkt is sent. This buffer consists of the number of bytes given in pktLen. If an
address byte as shown in Figure 23-9 is needed, it must be sent as the first payload byte.
If pktConf.bUseCrc is 1, a CRC is calculated and transmitted at the end. The number of CRC bits,
polynomial, and initialization are as configured in the radio. The CRC is calculated over the length byte (if
present) and over the entire contents of the buffer pointed to by pPkt.
1698

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Proprietary Radio

www.ti.com

If whitening is enabled, the optional length byte, the entire contents of the buffer pointed to by pPkt, and
the CRC are subject to whitening. The whitening is done after the data has been used for CRC
calculation.
23.7.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
The CMD_PROP_TX_ADV command transmits a packet with the format from Figure 23-10. As a special
case, the user can set up packets as outlined in Figure 23-9. The radio must be set up in a compatible
mode (such as proprietary mode) and the synthesizer programmed using CMD_FS. The parameters are
as given in Table 23-137.
The packet transmission starts at the given start trigger, with a fixed delay. Alternatively, if
startConf.bExtTXTrig is 1, the packet transmission starts on an external trigger to the RF core. The trigger
is identified as one of the inputs to the RAT, and can be configured as rising edge, falling edge, or both
edges through the startConf parameter. The system must ensure that this trigger comes after the start
trigger, otherwise it is lost. The minimum delay after the start trigger is implementation-dependent and
subject to characterization.
The modem first transmits the preamble and sync word as configured. If preTrigger is not TRIG_NOW, the
configured preamble is repeated until that trigger (seen in combination with preTime) has been observed.
After the trigger is observed, the configured preamble under transmission finishes before the sync word
transmission starts. If preTrigger is TRIG_NOW, the preamble is sent once, followed by the sync word.
The sync word to transmit is given in the syncWord field, in the LSBs if less than 32 bits are used, and is
transmitted in the bit order programmed in the radio.
If numHdrBits is greater than 0, a header of numHdrBits is sent next. The header may contain a length
field or an address. If so, these fields must be inserted correctly in the packet buffer. The header to be
transmitted is the first bytes of the buffer pointed to by pPkt. If numHdrBits does not divide by 8, the MSBs
of the last byte of the header are ignored.
The header is transmitted as one field in the bit ordering programmed in the radio. If the header has more
than 8 bits, it is always read from the transmit buffer in little-endian byte order. If the radio is configured to
transmit the MSB first, the last header byte from the TX buffer is transmitted first.
After the header, the remaining bytes in the buffer pointed to by pPkt are transmitted. The payload is
transmitted byte by byte, so after the header, no swapping of bytes occurs regardless of bit ordering over
the air. The total number of bytes (including the header) in this buffer is given by pktLen. If this length is
too small to fit the header, the operation ends with PROP_ERROR_PAR as status. If an address field after
the header as shown in Figure 23-10 is needed, it must be sent as the first payload byte.
If pktLen is 0, unlimited length is used. In this case, pPkt points to a transmit queue instead of a buffer
(see Section 23.5.3.2).
If pktConf.bUseCrc is 1, a CRC is calculated and transmitted at the end. The number of CRC bits,
polynomial, and initialization are as configured in the radio. If pktConf.bCrcIncSw is 1, the transmitted sync
word is included in the data set over which the CRC is calculated. If pktConf.bCrcIncHdr is 1, the
transmitted header is included in the data set over which the CRC is calculated. The payload is always
used to calculate the CRC.
If whitening is enabled, the optional header is subject to whitening if pktConf.bCrcIncHdr is 1. The entire
payload and the CRC are always subject to whitening when enabled. The whitening is done after the data
has been used for CRC calculation.
23.7.5.4 Receiver Commands
There are two commands for receiving packets, CMD_PROP_RX and CMD_PROP_RX_ADV. The latter
gives more flexibility in how the packet can be formed. Details are described in Section 23.7.5.4.1 and
Section 23.7.5.4.2, respectively.
For both commands, the radio must be set up in a compatible mode (such as proprietary mode), and the
synthesizer must be programmed using CMD_FS before the command is sent to the radio core.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1699

Proprietary Radio

www.ti.com

Both commands have an end trigger, given by endTrigger and endTime. If this trigger occurs while the
receiver is searching for sync, the operation ends with the status PROP_DONE_RXTIMEOUT. If the
trigger occurs while receiving a packet, the action depends on pktConf.endType.
If pktConf.endType = 0, the packet is received to the end and the operation then ends with
PROP_DONE_ENDED as the status. If pktConf.endType = 1, the packet reception is aborted and the
operation ends with PROP_DONE_BREAK as the status. The radio receives packets according to the
details given in Section 23.7.5.4.1 and Section 23.7.5.4.2. After receiving a packet, an interrupt is raised. If
pOutput is not NULL, an output structure as given in Table 23-137, pointed to by pOutput, is updated as
well. The interrupt to raise and field to update is given in Table 23-149. This table also gives the result to
write in the status field of the receive buffer, if enabled. The condition for packets being ignored is
described in Section 23.7.5.4.1 and Section 23.7.5.4.2.
Table 23-149. Interrupt, Counter, and Result Field for Received Packets (1)
Condition

Interrupt Raised

Counter
Incremented

Result Field of
Status Byte

Packet fully received with CRC OK and not to be ignored.

RX_OK

nRXOk

Packet fully received with CRC error.

RX_NOK

nRXNok

Packet fully received with CRC OK and address mismatch
(pktConf.filterOp = 1).

RX_IGNORED

nRXIgnored

Packet reception aborted due to timeout (pktConf.endType = 1),
CMD_ABORT, too short length in CMD_PROP_SET_LEN, or
CMD_PROP_RESTART_RX.

RX_ABORTED

nRXStopped

3 (1)

Packet reception aborted due to illegal length or address
mismatch (pktConf.filterOp = 0).

RX_ABORTED

nRXStopped

–

Packet could not be stored due to lack of buffer space.

RX_BUF_FULL

nRXBufFull

3 (1)

(1)

Provided partial-read entry is used and data has been written to the buffer.

For both types of commands, the packet length may be configured as unlimited or unknown at the start of
packet reception, by setting maxPktLen to 0. This mode can only be used with partial-read RX buffers. If
the length is later determined, it can be set by the immediate or direct command CMD_PROP_SET_LEN,
where the number of bytes between the header (if any) and the CRC is given. In addition to setting the
length this way, packet reception may be stopped in the following ways (CRC is not performed in the
following cases):
• If CMD_PROP_SET_LEN is called with a smaller number of bytes than already received
• If CMD_PROP_RESTART_RX is given
• If no more RX buffer is available
• If the end trigger occurs and pktConf.endType is 1
• If the command is aborted with CMD_ABORT
For ignored packets and packets with CRC error, automatic flush of the RX buffer can be configured. In
this case, packets are removed from the receive buffer after they have been received, so the next packet
overwrites it and the counters are not updated to reflect the packet received.
NOTE: Automatic flush is not supported for partial-read RX entries. Packets with CRC error (that is,
for which the RX_NOK interrupt is raised) are automatically flushed if
RXConf.bAutoFlushCrcErr is 1.

Ignored packets (that is, for which the RX_IGNORED interrupt is raised) are automatically flushed if
RXConf.bAutoFlushIgnored is 1. After a packet has been received, the next action depends on
pktConf.bRepeat. If this is 0, the command ends. Otherwise, it goes back into RX, unless another criterion
exists that leads to the command to end. When the command ends, the frequency synthesizer is turned
off if pktConf.bFsOff is 1. If pktConf.bFsOff is 0, the synthesizer keeps running, so that the command must
be followed by one of the following:
• An RX or TX command (which operate on the same frequency)
• A CMD_FS_OFF command to turn off the synthesizer

1700

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Proprietary Radio

www.ti.com

Table 23-150 lists the end statuses for CMD_PROP_RX and CMD_PROP_RX_ADV. This status decides
the next operation (see Section 23.7.5.1).
Table 23-150. End of Radio CMD_PROP_RX and CMD_PROP_RX_ADV Commands
Condition

Status Code

Result

Received packet with CRC OK and pktConf.bRepeatOk = 0.

PROP_DONE_OK

TRUE

Received packet with CRC error and pktConf.bRepeatNok = 0.

PROP_DONE_RXERR

FALSE

Observed end trigger while in sync search.

PROP_DONE_RXTIMEOUT

FALSE

Observed end trigger while receiving packet with pktConf.endType = 1.

PROP_DONE_BREAK

FALSE

Received packet after having observed end trigger while receiving packet with
pktConf.endType = 0.

PROP_DONE_ENDED

FALSE

Received CMD_STOP after command started and, if sync found, packet is
received.

PROP_DONE_STOPPED

FALSE

Received CMD_ABORT after command started.

PROP_DONE_ABORT

ABORT

No RX buffer large enough for the received data available at the start of a
packet.

PROP_ERROR_RXBUF

FALSE

Out of RX buffer during reception in a partial read buffer.

PROP_ERROR_RXFULL

FALSE

Observed illegal parameter.

PROP_ERROR_PAR

ABORT

Command sent without setting up the radio in a supported mode using
CMD_PROP_RADIO_SETUP or CMD_RADIO_SETUP.

PROP_ERROR_NO_SETUP

ABORT

Command sent without the synthesizer being programmed.

PROP_ERROR_NO_FS

ABORT

TX overflow observed during operation.

PROP_ERROR_RXOVF

ABORT

23.7.5.4.1 Standard Receive Command, CMD_PROP_RX
The CMD_PROP_RX receives packets with the format from Figure 23-9. The parameters are as given in
Table 23-138.
The modem configures the receiver and starts listening for sync. The sync word to listen for is given in the
LSBs of the syncWord field if less than 32 bits are used. The word is in the bit order programmed in the
radio.
If sync is found, the radio CPU starts receiving data. If pktConf.bVarLen is 1 and maxPktLen is nonzero, a
length byte is assumed as the next byte. This length byte is compared to maxPktLen, and if it is greater,
reception is stopped and synch search is restarted. Otherwise, this indicates the number of bytes after the
length byte and before the CRC. If pktConf.bVarLen is 0, the length is fixed, and the receiver assumes
maxPktLen bytes after the sync word and before the CRC. If maxPktLen is 0, the length is unlimited as
described in the beginning of Section 23.7.5.4.
If pktConf.bChkAddress is 1, an address byte is checked next. The address byte is checked against the
values of address0 and address1. If only one address is needed, these two fields must be set to the same
value. If address1 is 0xFF, it is also checked against the value 0x00. To check for 0xFF without checking
for 0x00, address0 must be set to 0xFF. If the address byte does not match the configured addresses, the
further treatment depends on pktConf.filterOp. If pktConf.filterOp = 0, reception is stopped and sync
search is restarted. If pktConf.filterOp = 1, the packet is received as if the address had matched, but it is
marked as ignored.
If the packet is being received, the data is placed in the RX buffer, as shown in Section 23.5.3.1. This RX
buffer is found from the receive queue pointed to by pQueue. If pQueue is NULL, the packet is never
stored.
If pktConf.bUseCrc is 1, a CRC is received and checked at the end. The number of CRC bits, polynomial,
and initialization are as configured in the radio. The CRC is calculated over the length byte (if present), the
optional address, and the payload. If pktConf.bUseCrc is 0, the treatment is the same as for CRC OK.
If whitening is enabled, the optional length byte, the payload (including the optional address), and the
received CRC are subject to dewhitening. The dewhitening is done before the CRC is evaluated.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1701

Proprietary Radio

www.ti.com

If a status byte is appended (RXConf.bAppendStatus is 1) to the packet, it is formatted as follows (see
Table 23-144). If pktConf.addressMode is nonzero, the addressInd field is 0 if the address matched
address0, 1 if it matched address1, 2 if it matched 0x00 and this address was enabled, and 3 if it matched
0xFF and this address was enabled. Otherwise, addressInd is 0. The syncWordId field is always 0 for
CMD_PROP_RX. The result field is written according to Table 23-150.
23.7.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
The command CMD_PROP_RX_ADV is used to receive packets with the format from Figure 23-10. As a
special case, the user can set up packets as in Figure 23-9. The parameters are as given in Table 23-139.
The modem configures the receiver and listens for sync. The sync word to listen for is given in the LSBs
of the syncWord0 field if less than 32 bits are used. The word is in the bit order programmed in the radio.
If syncWord1 is nonzero, the receiver also listens for the sync word given in the syncWord1 field
(formatted in the same way) if supported in the MCE.
If sync is found, the radio CPU starts receiving data. The packet may contain a header, which can consist
of any number of bits up to 32, given by hdrConf.numHdrBits. If the number of bits in the header does not
divide by 8, it is considered to consist of a sufficient number of bytes to contain all the stored bits, as
shown in Section 23.5.3.1. This header may contain a length field or an address.
The received packet may have fixed or variable length. If hdrConf.numLenBits is 0 and maxPktLen is
nonzero, the packet has a fixed length, consisting of maxPktLen bytes after the header and before the
CRC. If hdrConf.numLenBits is greater than 0, a field of hdrConf.numLenBits, read from bit number
hdrConf.lenPos from the LSB of the header, is taken as a length field. The signed number lenOffset is
added to the received length to give the number of bytes after the header and before the CRC. If this
number is less than or equal to maxPktLen, the packet is received. If maxPktLen is 0, the length is
unlimited as described in the beginning of Section 23.7.5.4. The definitions of packet length for
CMD_PROP_RX_ADV and CMD_PROP_TX_ADV differ; see Section 23.7.5.4.2 where the header is
included in the packet length.
Two kinds of addresses are supported. With the first option, the address is part of the header. In this case,
the address size can be from 1 to 31 bits. The other option is to have an address after the header. If so,
this address consists of from 1 to 8 bytes. To use an address as part of the header, addrConf.addrType
must be set to 1. The number of bits in the address is given by addrConf.addrSize. These bits are read
from bit number addrConf.addrPos from the first bit of the header. To use an address after the header,
addrConf.addrType must be set to 0. In this case, the number of bytes in the address is given by
addrConf.addrSize.
The received address is compared to an address list pointed to by pAddr. The address to compare against
this list is as received. In addition, 1 bit identifying the sync word is concatenated with the address as the
MSBs, if one of the following conditions is met:
• syncWord1 0 and addrConf.addrType = 1
• syncWord1 0, addrConf.addrType = 0, and addrConf.addrPos 0
This extra bit is 0 if the received sync word was syncWord0, and the extra bit is 1 if the received sync
word was syncWord1. The entries in the address list have a size of 8, 16, 32, or 64 bits; the size in use is
the smallest size that can fit the address size, including the sync word identification bit if applicable. The
number of entries in the address list is given by addrConf.numAddr. The radio CPU scans through the
addresses in the address list and compares it to the received address. If there is no match, the further
treatment depends on pktConf.filterOp. If pktConf.filterOp is 0, reception is stopped and synch search is
restarted. If pktConf.filterOp is 1, the packet is received as if the address had matched, but marked as
ignored.
If addrConf.addrSize is 0, no address is used. In this case, pAddr is ignored and must be NULL.
If the packet is being received, the data is placed in the RX buffer, as in Section 23.5.3.1. This RX buffer
is found from the receive queue pointed to by pQueue. If pQueue is NULL, the packet is never stored.
The header is received as one field in the bit ordering programmed in the radio. If the header has more
than 8 bits and rxConf.bIncludeHdr is 1, the header is always written in little-endian byte order to the RX
buffer. If the radio is configured to receive the MSB first, the last header byte stored in the RX buffer is
received first. The payload is stored byte by byte, so after the header, no swapping of bytes occurs
regardless of bit ordering over the air.
1702

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Proprietary Radio

www.ti.com

If pktConf.bUseCrc is 1, a CRC is received and checked at the end. The number of CRC bits, polynomial,
and initialization are as configured in the radio. If pktConf.bCrcIncSw is 1, the received sync word
(assuming it to be exactly equal to syncWord0 or syncWord1) is included in the data set over which the
CRC is calculated. If pktConf.bCrcIncHdr is 1, the received header is included in the data set over which
the CRC is calculated. The payload, including the optional address after the header, is always used for
calculating the CRC. If pktConf.bUseCrc is 0, the treatment is the same as for CRC OK.
If whitening is enabled, the optional header is subject to dewhitening only if pktConf.bCrcIncHdr is 1. The
payload (including the optional address after the header), and the received CRC are always subject to
dewhitening when enabled. The dewhitening is done before the CRC is evaluated.
If a status byte is appended (RXConf.bAppendStatus is 1) to the packet, it is formatted as detailed in
Table 23-144. If addrConf.addrSize is nonzero, the addressInd field is the first index into the address list
that matched the received address if an address match existed. Otherwise, addressInd is 0. The
syncWordId field is 0 if the received sync word was syncWord0, and 1 if syncWord1. The result field is
written according to Table 23-149.
23.7.5.5 Carrier-Sense Operation (CC13x0 Only)
The carrier-sense operation detects if a signal is present, which has the following main purposes:
• Turns off the radio instead of receiving when no signal is present
• Turns the radio to transmit only if no signal is present
The carrier-sense operation can be used with the command CMD_PROP_CS to chain with another
operation (for example, a transmit operation), or with the commands CMD_PROP_RX_SNIFF or
CMD_PROP_RX_ADV_SNIFF to combine with a normal receive operation to implement sniff mode. The
details of these commands are described in the following subsections.
23.7.5.5.1 Common Carrier-Sense Description
The parameters for the carrier-sense operation are common for all the commands, and are given in
Section 23.7.2.3. Table 23-142 gives the offset from the first byte used for carrier-sense parameters.
The channel can be in one of three states: BUSY, IDLE, or INVALID. BUSY indicates a signal on the
channel. IDLE indicates no signal is present on the channel. INVALID indicates that the state cannot be
determined. There are two sources of channel information, RSSI and correlation, and a separate state is
maintained for each source.
The operation starts when the radio is set up in receive mode. The RSSI or correlation is monitored,
according to the enable bits csConf.bEnaRssi and csConf.bEnaCorr. If csConf.bEnaRssi is 1, the RSSI is
monitored. If csConf.bEnaCorr is 1, the correlator is set up to correlate against the preamble. It is not
possible to set both enable bits to 0.
If csConf.bEnaRssi is 1, the RSSI is monitored every time a new value is available from the radio. At each
update, the RSSI is compared against the signed value rssiThr. If the RSSI is below rssiThr and if
numRssiIdle consecutive RSSI measurements below the threshold have been observed, the RSSI state is
IDLE. If the RSSI is above rssiThr and if numRssiBusy consecutive RSSI measurements above the
threshold have been observed, the RSSI state is BUSY. Otherwise, the RSSI state is INVALID.
If csConf.bEnaCorr is 1, the radio CPU monitors correlation peaks from the modem. When the radio
starts, the state is INVALID. If no correlation top is observed until corrPeriod RAT ticks after the carriersense command was started, the state becomes IDLE. If the state is IDLE and at least
corrConfig.numCorrInv correlation tops with a maximum of corrPeriod RAT ticks between them are
observed, the state becomes INVALID. If the state is INVALID and at least corrConfig.numCorrBusy
correlation tops with at most corrPeriod RAT ticks between them are observed, the state becomes BUSY.
If corrConfig.numCorrBusy is 0, the state goes directly to BUSY from IDLE. The value of
corrConfig.numCorrIdle must be greater than 0. If the state is not IDLE and corrTime RAT ticks pass after
the last correlation top, the state becomes IDLE again.
If only 1 of the enable bits is 1, the channel state is equal to the state of the corresponding source. If both
enable bits are 1, the channel state depends on the state of the two sources and the csConf.operation bit,
as shown in Table 23-151.

Radio1703

Proprietary Radio

www.ti.com

Table 23-151. Channel State When Both Sources are Enabled
csConf.operation = 0
RSSI state

Correlation state
INVALID

IDLE

BUSY

INVALID

BUSY

IDLE

INVALID

IDLE

BUSY

INVALID

IDLE

BUSY

INVALID

IDLE

INVALID

IDLE

BUSY

INVALID

IDLE

BUSY

csConf.operation = 1
RSSI state

Correlation state

If the state of the channel changes to BUSY, the action depends on csConf.busyOp and the command
being run. If csConf.busyOp is 0, the operation continues. If csConf.busyOp is 1 and the command is
CMD_PROP_CS, the operation ends with PROP_DONE_BUSY as the status. If csConf.busyOp is 1 and
the command is CMD_PROP_RX_SNIFF or CMD_PROP_RX_ADV_SNIFF, the receive operation
continues, but carrier sense is stopped, so the operation is not affected if the channel state later changes
to IDLE.
If the state of the channel changes to IDLE, the action depends on csConf.idleOp. If the value of this field
is 0, the receiver and carrier-sense operation continues. If the value of the bit field is 1, the operation ends
with PROP_DONE_IDLE as status.
If the trigger given by csEndTrigger and csEndTime is observed, the action depends on the command
being run and the channel state at that time. The details are described in Section 23.7.5.5.2 and
Section 23.7.5.5.3.
23.7.5.5.2 Carrier-Sense Command, CMD_PROP_CS
When the carrier-sense command starts, the radio is set up in receive mode, and the operations described
in Section 23.7.5.5.1 are performed. The radio must be set up in a compatible mode (such as proprietary
mode) and the synthesizer programmed using CMD_FS.
If the trigger given by csEndTrigger and csEndTime is observed, the operation ends, and the current
channel state is checked. If the state is BUSY or IDLE, the status is PROP_DONE_BUSY or
PROP_DONE_IDLE, respectively. If the state is INVALID, the status depends on csConf.timeoutRes. If 0,
the status is PROP_DONE_BUSYTIMEOUT; if 1, the status is PROP_DONE_IDLETIMEOUT.
When the command CMD_PROP_CS ends and the status is PROP_DONE_BUSY or
PROP_DONE_BUSYTIMEOUT, the synthesizer is turned off if csFsConf.bFsOffBusy is 1. If the command
ends and the status is PROP_DONE_IDLE or PROP_DONE_IDLETIMEOUT, the synthesizer is turned off
if csFsConf.bFsOffIdle is 1. If the command ends with another status, the synthesizer is turned off if either
of these bits is 1.
The end statuses for use with CMD_PROP_CS are summarized in Table 23-152. This status decides the
next operation, as shown in Section 23.7.5.1.
Table 23-152. End of CMD_PROP_CS Command
Condition

Status Code

Result

Observed channel state BUSY with csConf.busyOp = 1.

PROP_DONE_BUSY

TRUE

Observed channel state IDLE with csConf.idleOp = 1.

PROP_DONE_IDLE

FALSE

Time-out trigger observed with channel state BUSY.

PROP_DONE_BUSY

TRUE

Time-out trigger observed with channel state IDLE.

PROP_DONE_IDLE

FALSE

Time-out trigger observed with channel state INVALID and
csConf.timeoutRes = 0.

PROP_DONE_BUSYTIMEOUT

TRUE

1704Radio

Proprietary Radio

www.ti.com

Table 23-152. End of CMD_PROP_CS Command (continued)
Condition

Status Code

Result

Time-out trigger observed with channel state INVALID and
csConf.timeoutRes = 1.

PROP_DONE_IDLETIMEOUT

FALSE

Received CMD_STOP after command started.

PROP_DONE_STOPPED

FALSE

Received CMD_ABORT after command started.

PROP_DONE_ABORT

ABORT

Observed illegal parameter.

PROP_ERROR_PAR

ABORT

Command sent without setting up the radio in a supported mode using
CMD_PROP_RADIO_SETUP or CMD_RADIO_SETUP.

PROP_ERROR_NO_SETUP

ABORT

Command sent without the synthesizer being programmed.

PROP_ERROR_NO_FS

ABORT

23.7.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
The commands CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF behave like the commands
CMD_PROP_RX and CMD_PROP_RX_ADV, respectively, but they perform carrier-sense operations
during sync search.
When started, the commands perform the carrier-sense operations described in Section 23.7.5.5.1. As
described, the operation may end if the channel state becomes IDLE.
If the trigger given by csEndTrigger and csEndTime is observed, the current channel state is checked. If
the channel state is BUSY, the receiver continues, but may end later if the channel state becomes IDLE
and csConf.busyOp is 0. If the channel state is IDLE, the operation ends (even if csConf.idleOp is 0), and
the status is PROP_DONE_IDLE. If the channel state is INVALID, the action depends on
csConf.timeoutRes. If csConf.timeoutRes is 0, the receive operation continues, and if csConf.busyOp is 1,
carrier sense is no longer checked. If csConf.timeoutRes is 1, the operation ends and the status is
PROP_DONE_IDLETIMEOUT.
If sync is found, the receiver operates as described in Section 23.7.5.4. If sync search is restarted after a
packet is received or after reception is stopped due to an invalid length field or address mismatch, the
carrier-sense operation is resumed if it was running when sync was found.
The end statuses for use with CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF are listed in
Table 23-150 and Table 23-153. This status decides the next operation, as in Section 23.7.5.1.
Table 23-153. Additional End Statuses for CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
Condition

Status Code

Result

Observed channel state IDLE with csConf.idleOp = 1.

PROP_DONE_IDLE

FALSE

Time-out trigger observed with channel state IDLE.

PROP_DONE_IDLE

FALSE

Time-out trigger observed with channel state INVALID and
csConf.timeoutRes = 1.

PROP_DONE_IDLETIMEOUT

FALSE

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1705

Proprietary Radio

www.ti.com

23.7.6 Immediate Commands
23.7.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
The CMD_PROP_SET_LEN command takes a command structure as defined in Table 23-140.
CMD_PROP_SET_LEN must only be sent while a CMD_PROP_RX or CMD_PROP_RX_ADV command
is running configured with unlimited packet length. When the command is received, the radio CPU sets the
number of bytes to receive between the header and the CRC to RXLen. If at least this number of bytes
has already been received, reception is aborted, as in Section 23.7.5.4 and Section 23.7.5.4.2.
The command may be sent as a direct command if the payload length to set is 255 bytes or less. In this
case, the RXLen parameter is written in bits 8–16 of CMDR, and the 8 MSBs of this parameter is 0.
If the command is issued without a CMD_PROP_RX or CMD_PROP_RX_ADV command running, or if
such a command is not configured with unlimited length, the radio CPU returns the result ContextError in
CMDSTA. Otherwise, the radio CPU returns DONE.
23.7.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
The CMD_PROP_RESTART_RX command is a direct command that takes no parameters.
CMD_PROP_RESTART_RX must only be sent while a CMD_PROP_RX or CMD_PROP_RX_ADV
command is running. If a packet is being received, reception is aborted, as described in Section 23.7.5.4
and the packet returns to sync search.
If the command is issued without an RX command running, the radio CPU returns the result ContextError
in CMDSTA. Otherwise, the radio CPU returns DONE.

1706

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

23.8 Radio Registers
23.8.1 RFC_RAT Registers
Table 23-154 lists the memory-mapped registers for the RFC_RAT. All register offset addresses not listed
in Table 23-154 should be considered as reserved locations and the register contents should not be
modified.
Table 23-154. RFC_RAT Registers
Offset

Acronym

RATCNT

Radio Timer Counter Value

Section 23.8.1.1

80h

RATCH0VAL

Timer Channel 0 Capture/Compare Register

Section 23.8.1.2

84h

RATCH1VAL

Timer Channel 1 Capture/Compare Register

Section 23.8.1.3

88h

RATCH2VAL

Timer Channel 2 Capture/Compare Register

Section 23.8.1.4

8Ch

RATCH3VAL

Timer Channel 3 Capture/Compare Register

Section 23.8.1.5

90h

RATCH4VAL

Timer Channel 4 Capture/Compare Register

Section 23.8.1.6

94h

RATCH5VAL

Timer Channel 5 Capture/Compare Register

Section 23.8.1.7

98h

RATCH6VAL

Timer Channel 6 Capture/Compare Register

Section 23.8.1.8

9Ch

RATCH7VAL

Timer Channel 7 Capture/Compare Register

Section 23.8.1.9

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Section

Radio

1707

Radio Registers

www.ti.com

23.8.1.1 RATCNT Register (Offset = 4h) [reset = 0h]
RATCNT is shown in Figure 23-12 and described in Table 23-155.
Return to Summary Table.
Radio Timer Counter Value
Figure 23-12. RATCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CNT
R/W-0h

Table 23-155. RATCNT Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

CNT

R/W

Counter value. This is not writable while radio timer counter is
enabled.

1708

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

23.8.1.2 RATCH0VAL Register (Offset = 80h) [reset = 0h]
RATCH0VAL is shown in Figure 23-13 and described in Table 23-156.
Return to Summary Table.
Timer Channel 0 Capture/Compare Register
Figure 23-13. RATCH0VAL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VAL
R/W-0h

Table 23-156. RATCH0VAL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

VAL

R/W

Capture/compare value. The system CPU can safely read this
register, but it is recommended to use the CPE API commands to
configure it for compare mode.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1709

Radio Registers

www.ti.com

23.8.1.3 RATCH1VAL Register (Offset = 84h) [reset = 0h]
RATCH1VAL is shown in Figure 23-14 and described in Table 23-157.
Return to Summary Table.
Timer Channel 1 Capture/Compare Register
Figure 23-14. RATCH1VAL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VAL
R/W-0h

Table 23-157. RATCH1VAL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

VAL

R/W

Capture/compare value. The system CPU can safely read this
register, but it is recommended to use the CPE API commands to
configure it for compare mode.

1710

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

23.8.1.4 RATCH2VAL Register (Offset = 88h) [reset = 0h]
RATCH2VAL is shown in Figure 23-15 and described in Table 23-158.
Return to Summary Table.
Timer Channel 2 Capture/Compare Register
Figure 23-15. RATCH2VAL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VAL
R/W-0h

Table 23-158. RATCH2VAL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

VAL

R/W

Capture/compare value. The system CPU can safely read this
register, but it is recommended to use the CPE API commands to
configure it for compare mode.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1711

Radio Registers

www.ti.com

23.8.1.5 RATCH3VAL Register (Offset = 8Ch) [reset = 0h]
RATCH3VAL is shown in Figure 23-16 and described in Table 23-159.
Return to Summary Table.
Timer Channel 3 Capture/Compare Register
Figure 23-16. RATCH3VAL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VAL
R/W-0h

Table 23-159. RATCH3VAL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

VAL

R/W

Capture/compare value. The system CPU can safely read this
register, but it is recommended to use the CPE API commands to
configure it for compare mode.

1712

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

23.8.1.6 RATCH4VAL Register (Offset = 90h) [reset = 0h]
RATCH4VAL is shown in Figure 23-17 and described in Table 23-160.
Return to Summary Table.
Timer Channel 4 Capture/Compare Register
Figure 23-17. RATCH4VAL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VAL
R/W-0h

Table 23-160. RATCH4VAL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

VAL

R/W

Capture/compare value. The system CPU can safely read this
register, but it is recommended to use the CPE API commands to
configure it for compare mode.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1713

Radio Registers

www.ti.com

23.8.1.7 RATCH5VAL Register (Offset = 94h) [reset = 0h]
RATCH5VAL is shown in Figure 23-18 and described in Table 23-161.
Return to Summary Table.
Timer Channel 5 Capture/Compare Register
Figure 23-18. RATCH5VAL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VAL
R/W-0h

Table 23-161. RATCH5VAL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

VAL

R/W

Capture/compare value. The system CPU can safely read this
register, but it is recommended to use the CPE API commands to
configure it for compare mode.

1714

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

23.8.1.8 RATCH6VAL Register (Offset = 98h) [reset = 0h]
RATCH6VAL is shown in Figure 23-19 and described in Table 23-162.
Return to Summary Table.
Timer Channel 6 Capture/Compare Register
Figure 23-19. RATCH6VAL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VAL
R/W-0h

Table 23-162. RATCH6VAL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

VAL

R/W

Capture/compare value. The system CPU can safely read this
register, but it is recommended to use the CPE API commands to
configure it for compare mode.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1715

Radio Registers

www.ti.com

23.8.1.9 RATCH7VAL Register (Offset = 9Ch) [reset = 0h]
RATCH7VAL is shown in Figure 23-20 and described in Table 23-163.
Return to Summary Table.
Timer Channel 7 Capture/Compare Register
Figure 23-20. RATCH7VAL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VAL
R/W-0h

Table 23-163. RATCH7VAL Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

VAL

R/W

Capture/compare value. The system CPU can safely read this
register, but it is recommended to use the CPE API commands to
configure it for compare mode.

23.8.2 RFC_DBELL Registers
Table 23-164 lists the memory-mapped registers for the RFC_DBELL. All register offset addresses not
listed in Table 23-164 should be considered as reserved locations and the register contents should not be
modified.
Table 23-164. RFC_DBELL Registers
Offset

1716

Acronym

CMDR

Doorbell Command Register

Section 23.8.2.1

Section

CMDSTA

Doorbell Command Status Register

Section 23.8.2.2

RFHWIFG

Interrupt Flags From RF Hardware Modules

Section 23.8.2.3

RFHWIEN

Interrupt Enable For RF Hardware Modules

Section 23.8.2.4

10h

RFCPEIFG

Interrupt Flags For Command and Packet Engine
Generated Interrupts

Section 23.8.2.5

14h

RFCPEIEN

Interrupt Enable For Command and Packet Engine
Generated Interrupts

Section 23.8.2.6

18h

RFCPEISL

Interrupt Vector Selection For Command and Packet
Engine Generated Interrupts

Section 23.8.2.7

1Ch

RFACKIFG

Doorbell Command Acknowledgement Interrupt Flag

Section 23.8.2.8

20h

SYSGPOCTL

RF Core General Purpose Output Control

Section 23.8.2.9

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

23.8.2.1 CMDR Register (Offset = 0h) [reset = 0h]
CMDR is shown in Figure 23-21 and described in Table 23-165.
Return to Summary Table.
Doorbell Command Register
Figure 23-21. CMDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CMD
R/W-0h

Table 23-165. CMDR Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

CMD

R/W

Command register. Raises an interrupt to the Command and packet
engine (CPE) upon write.

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1717

Radio Registers

www.ti.com

23.8.2.2 CMDSTA Register (Offset = 4h) [reset = 0h]
CMDSTA is shown in Figure 23-22 and described in Table 23-166.
Return to Summary Table.
Doorbell Command Status Register
Figure 23-22. CMDSTA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STAT
R-0h

Table 23-166. CMDSTA Register Field Descriptions
Bit

Field

Type

Reset

Description

31-0

STAT

Status of the last command used

1718

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

23.8.2.3 RFHWIFG Register (Offset = 8h) [reset = 0h]
RFHWIFG is shown in Figure 23-23 and described in Table 23-167.
Return to Summary Table.
Interrupt Flags From RF Hardware Modules
Figure 23-23. RFHWIFG Register
31

RESERVED
R-0h
23

19
RATCH7
R/W-0h

18
RATCH6
R/W-0h

17
RATCH5
R/W-0h

16
RATCH4
R/W-0h

RESERVED
R-0h
15
RATCH3
R/W-0h

14
RATCH2
R/W-0h

13
RATCH1
R/W-0h

12
RATCH0
R/W-0h

11
RFESOFT2
R/W-0h

10
RFESOFT1
R/W-0h

9
RFESOFT0
R/W-0h

8
RFEDONE
R/W-0h

7
RESERVED
R/W-0h

6
TRCTK
R/W-0h

5
MDMSOFT
R/W-0h

4
MDMOUT
R/W-0h

3
MDMIN
R/W-0h

2
MDMDONE
R/W-0h

1
FSCA
R/W-0h

0
RESERVED
R/W-0h

Table 23-167. RFHWIFG Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RATCH7

R/W

Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to
one has no effect.

RATCH6

R/W

Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to
one has no effect.

RATCH5

R/W

Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to
one has no effect.

RATCH4

R/W

Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to
one has no effect.

RATCH3

R/W

Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to
one has no effect.

RATCH2

R/W

Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to
one has no effect.

RATCH1

R/W

Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to
one has no effect.

RATCH0

R/W

Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to
one has no effect.

RFESOFT2

R/W

RF engine software defined interrupt 2 flag. Write zero to clear flag.
Write to one has no effect.

RFESOFT1

R/W

RF engine software defined interrupt 1 flag. Write zero to clear flag.
Write to one has no effect.

RFESOFT0

R/W

RF engine software defined interrupt 0 flag. Write zero to clear flag.
Write to one has no effect.

RFEDONE

R/W

RF engine command done interrupt flag. Write zero to clear flag.
Write to one has no effect.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TRCTK

R/W

Debug tracer system tick interrupt flag. Write zero to clear flag. Write
to one has no effect.

31-20

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1719

Radio Registers

www.ti.com

Table 23-167. RFHWIFG Register Field Descriptions (continued)
Bit

1720

Field

Type

Reset

Description

MDMSOFT

R/W

Modem synchronization word detection interrupt flag. This interrupt
will be raised by modem when the synchronization word is received.
The CPE may decide to reject the packet based on its header
(protocol specific). Write zero to clear flag. Write to one has no
effect.

MDMOUT

R/W

Modem FIFO output interrupt flag. Write zero to clear flag. Write to
one has no effect.

MDMIN

R/W

Modem FIFO input interrupt flag. Write zero to clear flag. Write to
one has no effect.

MDMDONE

R/W

Modem command done interrupt flag. Write zero to clear flag. Write
to one has no effect.

FSCA

R/W

Frequency synthesizer calibration accelerator interrupt flag. Write
zero to clear flag. Write to one has no effect.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

23.8.2.4 RFHWIEN Register (Offset = Ch) [reset = 0h]
RFHWIEN is shown in Figure 23-24 and described in Table 23-168.
Return to Summary Table.
Interrupt Enable For RF Hardware Modules
Figure 23-24. RFHWIEN Register
31

RESERVED
R-0h
23

19
RATCH7
R/W-0h

18
RATCH6
R/W-0h

17
RATCH5
R/W-0h

16
RATCH4
R/W-0h

RESERVED
R-0h
15
RATCH3
R/W-0h

14
RATCH2
R/W-0h

13
RATCH1
R/W-0h

12
RATCH0
R/W-0h

11
RFESOFT2
R/W-0h

10
RFESOFT1
R/W-0h

9
RFESOFT0
R/W-0h

8
RFEDONE
R/W-0h

7
RESERVED
R/W-0h

6
TRCTK
R/W-0h

5
MDMSOFT
R/W-0h

4
MDMOUT
R/W-0h

3
MDMIN
R/W-0h

2
MDMDONE
R/W-0h

1
FSCA
R/W-0h

0
RESERVED
R/W-0h

Table 23-168. RFHWIEN Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RATCH7

R/W

Interrupt enable for RFHWIFG.RATCH7.

RATCH6

R/W

Interrupt enable for RFHWIFG.RATCH6.

RATCH5

R/W

Interrupt enable for RFHWIFG.RATCH5.

RATCH4

R/W

Interrupt enable for RFHWIFG.RATCH4.

RATCH3

R/W

Interrupt enable for RFHWIFG.RATCH3.

RATCH2

R/W

Interrupt enable for RFHWIFG.RATCH2.

RATCH1

R/W

Interrupt enable for RFHWIFG.RATCH1.

RATCH0

R/W

Interrupt enable for RFHWIFG.RATCH0.

RFESOFT2

R/W

Interrupt enable for RFHWIFG.RFESOFT2.

RFESOFT1

R/W

Interrupt enable for RFHWIFG.RFESOFT1.

RFESOFT0

R/W

Interrupt enable for RFHWIFG.RFESOFT0.

RFEDONE

R/W

Interrupt enable for RFHWIFG.RFEDONE.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

TRCTK

R/W

Interrupt enable for RFHWIFG.TRCTK.

MDMSOFT

R/W

Interrupt enable for RFHWIFG.MDMSOFT.

MDMOUT

R/W

Interrupt enable for RFHWIFG.MDMOUT.

MDMIN

R/W

Interrupt enable for RFHWIFG.MDMIN.

MDMDONE

R/W

Interrupt enable for RFHWIFG.MDMDONE.

FSCA

R/W

Interrupt enable for RFHWIFG.FSCA.

RESERVED

R/W

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

31-20

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1721

Radio Registers

www.ti.com

23.8.2.5 RFCPEIFG Register (Offset = 10h) [reset = 0h]
RFCPEIFG is shown in Figure 23-25 and described in Table 23-169.
Return to Summary Table.
Interrupt Flags For Command and Packet Engine Generated Interrupts
Figure 23-25. RFCPEIFG Register
31
INTERNAL_ER
ROR
R/W-0h

30
BOOT_DONE

29
MODULES_UN
LOCKED
R/W-0h

28
SYNTH_NO_L
OCK
R/W-0h

27
IRQ27

26
RX_ABORTED
R/W-0h

25
RX_N_DATA_
WRITTEN
R/W-0h

24
RX_DATA_WRI
TTEN
R/W-0h

R/W-0h

23
RX_ENTRY_D
ONE
R/W-0h

22
RX_BUF_FULL

20
RX_CTRL

R/W-0h

21
RX_CTRL_AC
K
R/W-0h

19
RX_EMPTY

18
RX_IGNORED

17
RX_NOK

16
RX_OK

R/W-0h

15
IRQ15

14
IRQ14

13
IRQ13

12
IRQ12

R/W-0h

10
TX_ENTRY_D
ONE
R/W-0h

9
TX_RETRANS

R/W-0h

11
TX_BUFFER_C
HANGED
R/W-0h

R/W-0h

8
TX_CTRL_ACK
_ACK
R/W-0h

R/W-0h
7
TX_CTRL_ACK

6
TX_CTRL

5
TX_ACK

4
TX_DONE

2
FG_COMMAN
D_DONE

1
LAST_COMMA
ND_DONE

0
COMMAND_D
ONE

R/W-0h

3
LAST_FG_CO
MMAND_DON
E
R/W-0h

R/W-0h

Table 23-169. RFCPEIFG Register Field Descriptions

1722

Bit

Field

Type

Reset

Description

INTERNAL_ERROR

R/W

Interrupt flag 31. The command and packet engine (CPE) has
observed an unexpected error. A reset of the CPE is needed. This
can be done by switching the RF Core power domain off and on in
PRCM:PDCTL1RFC. Write zero to clear flag. Write to one has no
effect.

BOOT_DONE

R/W

Interrupt flag 30. The command and packet engine (CPE) boot is
finished. Write zero to clear flag. Write to one has no effect.

MODULES_UNLOCKED

R/W

Interrupt flag 29. As part of command and packet engine (CPE) boot
process, it has opened access to RF Core modules and memories.
Write zero to clear flag. Write to one has no effect.

SYNTH_NO_LOCK

R/W

Interrupt flag 28. The phase-locked loop in frequency synthesizer
has reported loss of lock. Write zero to clear flag. Write to one has
no effect.

IRQ27

R/W

Interrupt flag 27. Write zero to clear flag. Write to one has no effect.

RX_ABORTED

R/W

Interrupt flag 26. Packet reception stopped before packet was done.
Write zero to clear flag. Write to one has no effect.

RX_N_DATA_WRITTEN

R/W

Interrupt flag 25. Specified number of bytes written to partial read Rx
buffer. Write zero to clear flag. Write to one has no effect.

RX_DATA_WRITTEN

R/W

Interrupt flag 24. Data written to partial read Rx buffer. Write zero to
clear flag. Write to one has no effect.

RX_ENTRY_DONE

R/W

Interrupt flag 23. Rx queue data entry changing state to finished.
Write zero to clear flag. Write to one has no effect.

RX_BUF_FULL

R/W

Interrupt flag 22. Packet received that did not fit in Rx queue. BLE
mode: Packet received that did not fit in the Rx queue. IEEE
802.15.4 mode: Frame received that did not fit in the Rx queue.
Write zero to clear flag. Write to one has no effect.

RX_CTRL_ACK

R/W

Interrupt flag 21. BLE mode only: LL control packet received with
CRC OK, not to be ignored, then acknowledgement sent. Write zero
to clear flag. Write to one has no effect.

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

Table 23-169. RFCPEIFG Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

RX_CTRL

R/W

Interrupt flag 20. BLE mode only: LL control packet received with
CRC OK, not to be ignored. Write zero to clear flag. Write to one has
no effect.

RX_EMPTY

R/W

Interrupt flag 19. BLE mode only: Packet received with CRC OK, not
to be ignored, no payload. Write zero to clear flag. Write to one has
no effect.

RX_IGNORED

R/W

Interrupt flag 18. Packet received, but can be ignored. BLE mode:
Packet received with CRC OK, but to be ignored. IEEE 802.15.4
mode: Frame received with ignore flag set. Write zero to clear flag.
Write to one has no effect.

RX_NOK

R/W

Interrupt flag 17. Packet received with CRC error. BLE mode: Packet
received with CRC error. IEEE 802.15.4 mode: Frame received with
CRC error. Write zero to clear flag. Write to one has no effect.

RX_OK

R/W

Interrupt flag 16. Packet received correctly. BLE mode: Packet
received with CRC OK, payload, and not to be ignored. IEEE
802.15.4 mode: Frame received with CRC OK. Write zero to clear
flag. Write to one has no effect.

IRQ15

R/W

Interrupt flag 15. Write zero to clear flag. Write to one has no effect.

IRQ14

R/W

Interrupt flag 14. Write zero to clear flag. Write to one has no effect.

IRQ13

R/W

Interrupt flag 13. Write zero to clear flag. Write to one has no effect.

IRQ12

R/W

Interrupt flag 12. Write zero to clear flag. Write to one has no effect.

TX_BUFFER_CHANGED

R/W

Interrupt flag 11. BLE mode only: A buffer change is complete after
CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one
has no effect.

TX_ENTRY_DONE

R/W

Interrupt flag 10. Tx queue data entry state changed to finished.
Write zero to clear flag. Write to one has no effect.

TX_RETRANS

R/W

Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to
clear flag. Write to one has no effect.

TX_CTRL_ACK_ACK

R/W

Interrupt flag 8. BLE mode only: Acknowledgement received on a
transmitted LL control packet, and acknowledgement transmitted for
that packet. Write zero to clear flag. Write to one has no effect.

TX_CTRL_ACK

R/W

Interrupt flag 7. BLE mode: Acknowledgement received on a
transmitted LL control packet. Write zero to clear flag. Write to one
has no effect.

TX_CTRL

R/W

Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero
to clear flag. Write to one has no effect.

TX_ACK

R/W

Interrupt flag 5. BLE mode: Acknowledgement received on a
transmitted packet. IEEE 802.15.4 mode: Transmitted automatic
ACK frame. Write zero to clear flag. Write to one has no effect.

TX_DONE

R/W

Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been
transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted).
Write zero to clear flag. Write to one has no effect.

LAST_FG_COMMAND_D
ONE

R/W

Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio
operation command in a chain of commands has finished. Write zero
to clear flag. Write to one has no effect.

FG_COMMAND_DONE

R/W

Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio
operation command has finished. Write zero to clear flag. Write to
one has no effect.

LAST_COMMAND_DONE R/W

Interrupt flag 1. The last radio operation command in a chain of
commands has finished. (IEEE 802.15.4 mode: The last background
level radio operation command in a chain of commands has
finished.) Write zero to clear flag. Write to one has no effect.

COMMAND_DONE

Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4
mode: A background level radio operation command has finished.)
Write zero to clear flag. Write to one has no effect.

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1723

Radio Registers

www.ti.com

23.8.2.6 RFCPEIEN Register (Offset = 14h) [reset = FFFFFFFFh]
RFCPEIEN is shown in Figure 23-26 and described in Table 23-170.
Return to Summary Table.
Interrupt Enable For Command and Packet Engine Generated Interrupts
Figure 23-26. RFCPEIEN Register
31
INTERNAL_ER
ROR
R/W-1h

30
BOOT_DONE

29
MODULES_UN
LOCKED
R/W-1h

28
SYNTH_NO_L
OCK
R/W-1h

27
IRQ27

26
RX_ABORTED
R/W-1h

25
RX_N_DATA_
WRITTEN
R/W-1h

24
RX_DATA_WRI
TTEN
R/W-1h

R/W-1h

23
RX_ENTRY_D
ONE
R/W-1h

22
RX_BUF_FULL

20
RX_CTRL

R/W-1h

21
RX_CTRL_AC
K
R/W-1h

19
RX_EMPTY

18
RX_IGNORED

17
RX_NOK

16
RX_OK

R/W-1h

15
IRQ15

14
IRQ14

13
IRQ13

12
IRQ12

R/W-1h

10
TX_ENTRY_D
ONE
R/W-1h

9
TX_RETRANS

R/W-1h

11
TX_BUFFER_C
HANGED
R/W-1h

R/W-1h

8
TX_CTRL_ACK
_ACK
R/W-1h

R/W-1h
7
TX_CTRL_ACK

6
TX_CTRL

5
TX_ACK

4
TX_DONE

2
FG_COMMAN
D_DONE

1
LAST_COMMA
ND_DONE

0
COMMAND_D
ONE

R/W-1h

3
LAST_FG_CO
MMAND_DON
E
R/W-1h

R/W-1h

Table 23-170. RFCPEIEN Register Field Descriptions

1724

Bit

Field

Type

Reset

Description

INTERNAL_ERROR

R/W

Interrupt enable for RFCPEIFG.INTERNAL_ERROR.

BOOT_DONE

R/W

Interrupt enable for RFCPEIFG.BOOT_DONE.

MODULES_UNLOCKED

R/W

Interrupt enable for RFCPEIFG.MODULES_UNLOCKED.

SYNTH_NO_LOCK

R/W

Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK.

IRQ27

R/W

Interrupt enable for RFCPEIFG.IRQ27.

RX_ABORTED

R/W

Interrupt enable for RFCPEIFG.RX_ABORTED.

RX_N_DATA_WRITTEN

R/W

Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN.

RX_DATA_WRITTEN

R/W

Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN.

RX_ENTRY_DONE

R/W

Interrupt enable for RFCPEIFG.RX_ENTRY_DONE.

RX_BUF_FULL

R/W

Interrupt enable for RFCPEIFG.RX_BUF_FULL.

RX_CTRL_ACK

R/W

Interrupt enable for RFCPEIFG.RX_CTRL_ACK.

RX_CTRL

R/W

Interrupt enable for RFCPEIFG.RX_CTRL.

RX_EMPTY

R/W

Interrupt enable for RFCPEIFG.RX_EMPTY.

RX_IGNORED

R/W

Interrupt enable for RFCPEIFG.RX_IGNORED.

RX_NOK

R/W

Interrupt enable for RFCPEIFG.RX_NOK.

RX_OK

R/W

Interrupt enable for RFCPEIFG.RX_OK.

IRQ15

R/W

Interrupt enable for RFCPEIFG.IRQ15.

IRQ14

R/W

Interrupt enable for RFCPEIFG.IRQ14.

IRQ13

R/W

Interrupt enable for RFCPEIFG.IRQ13.

IRQ12

R/W

Interrupt enable for RFCPEIFG.IRQ12.

TX_BUFFER_CHANGED

R/W

Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED.

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

Table 23-170. RFCPEIEN Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

TX_ENTRY_DONE

R/W

Interrupt enable for RFCPEIFG.TX_ENTRY_DONE.

TX_RETRANS

R/W

Interrupt enable for RFCPEIFG.TX_RETRANS.

TX_CTRL_ACK_ACK

R/W

Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK.

TX_CTRL_ACK

R/W

Interrupt enable for RFCPEIFG.TX_CTRL_ACK.

TX_CTRL

R/W

Interrupt enable for RFCPEIFG.TX_CTRL.

TX_ACK

R/W

Interrupt enable for RFCPEIFG.TX_ACK.

TX_DONE

R/W

Interrupt enable for RFCPEIFG.TX_DONE.

LAST_FG_COMMAND_D
ONE

R/W

Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE.

FG_COMMAND_DONE

R/W

Interrupt enable for RFCPEIFG.FG_COMMAND_DONE.

LAST_COMMAND_DONE R/W

Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE.

COMMAND_DONE

Interrupt enable for RFCPEIFG.COMMAND_DONE.

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1725

Radio Registers

www.ti.com

23.8.2.7 RFCPEISL Register (Offset = 18h) [reset = FFFF0000h]
RFCPEISL is shown in Figure 23-27 and described in Table 23-171.
Return to Summary Table.
Interrupt Vector Selection For Command and Packet Engine Generated Interrupts
Figure 23-27. RFCPEISL Register
31
INTERNAL_ER
ROR
R/W-1h

30
BOOT_DONE

29
MODULES_UN
LOCKED
R/W-1h

28
SYNTH_NO_L
OCK
R/W-1h

27
IRQ27

26
RX_ABORTED
R/W-1h

25
RX_N_DATA_
WRITTEN
R/W-1h

24
RX_DATA_WRI
TTEN
R/W-1h

R/W-1h

23
RX_ENTRY_D
ONE
R/W-1h

22
RX_BUF_FULL

20
RX_CTRL

R/W-1h

21
RX_CTRL_AC
K
R/W-1h

19
RX_EMPTY

18
RX_IGNORED

17
RX_NOK

16
RX_OK

R/W-1h

15
IRQ15

14
IRQ14

13
IRQ13

12
IRQ12

R/W-0h

10
TX_ENTRY_D
ONE
R/W-0h

9
TX_RETRANS

R/W-0h

11
TX_BUFFER_C
HANGED
R/W-0h

R/W-0h

8
TX_CTRL_ACK
_ACK
R/W-0h

R/W-0h
7
TX_CTRL_ACK

6
TX_CTRL

5
TX_ACK

4
TX_DONE

2
FG_COMMAN
D_DONE

1
LAST_COMMA
ND_DONE

0
COMMAND_D
ONE

R/W-0h

3
LAST_FG_CO
MMAND_DON
E
R/W-0h

R/W-0h

R/W-1h

Table 23-171. RFCPEISL Register Field Descriptions

1726

Bit

Field

Type

Reset

Description

INTERNAL_ERROR

R/W

Select which CPU interrupt vector the
RFCPEIFG.INTERNAL_ERROR interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

BOOT_DONE

R/W

Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE
interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

MODULES_UNLOCKED

R/W

Select which CPU interrupt vector the
RFCPEIFG.MODULES_UNLOCKED interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

SYNTH_NO_LOCK

R/W

Select which CPU interrupt vector the
RFCPEIFG.SYNTH_NO_LOCK interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

IRQ27

R/W

Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt
should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

RX_ABORTED

R/W

Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED
interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

RX_N_DATA_WRITTEN

R/W

Select which CPU interrupt vector the
RFCPEIFG.RX_N_DATA_WRITTEN interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

Table 23-171. RFCPEISL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

RX_DATA_WRITTEN

R/W

Select which CPU interrupt vector the
RFCPEIFG.RX_DATA_WRITTEN interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

RX_ENTRY_DONE

R/W

Select which CPU interrupt vector the
RFCPEIFG.RX_ENTRY_DONE interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

RX_BUF_FULL

R/W

Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL
interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

RX_CTRL_ACK

R/W

Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK
interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

RX_CTRL

R/W

Select which CPU interrupt vector the RFCPEIFG.RX_CTRL
interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

RX_EMPTY

R/W

Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY
interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

RX_IGNORED

R/W

Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED
interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

RX_NOK

R/W

Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt
should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

RX_OK

R/W

Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt
should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

IRQ15

R/W

Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt
should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

IRQ14

R/W

Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt
should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

IRQ13

R/W

Select which CPU interrupt vector the RFCPEIFG.IRQ13 interrupt
should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

IRQ12

R/W

Select which CPU interrupt vector the RFCPEIFG.IRQ12 interrupt
should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1727

Radio Registers

www.ti.com

Table 23-171. RFCPEISL Register Field Descriptions (continued)

1728

Bit

Field

Type

Reset

Description

TX_BUFFER_CHANGED

R/W

Select which CPU interrupt vector the
RFCPEIFG.TX_BUFFER_CHANGED interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

TX_ENTRY_DONE

R/W

Select which CPU interrupt vector the
RFCPEIFG.TX_ENTRY_DONE interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

TX_RETRANS

R/W

Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS
interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

TX_CTRL_ACK_ACK

R/W

Select which CPU interrupt vector the
RFCPEIFG.TX_CTRL_ACK_ACK interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

TX_CTRL_ACK

R/W

Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK
interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

TX_CTRL

R/W

Select which CPU interrupt vector the RFCPEIFG.TX_CTRL
interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

TX_ACK

R/W

Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt
should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

TX_DONE

R/W

Select which CPU interrupt vector the RFCPEIFG.TX_DONE
interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

LAST_FG_COMMAND_D
ONE

R/W

Select which CPU interrupt vector the
RFCPEIFG.LAST_FG_COMMAND_DONE interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

FG_COMMAND_DONE

R/W

Select which CPU interrupt vector the
RFCPEIFG.FG_COMMAND_DONE interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

LAST_COMMAND_DONE R/W

Select which CPU interrupt vector the
RFCPEIFG.LAST_COMMAND_DONE interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

COMMAND_DONE

Select which CPU interrupt vector the
RFCPEIFG.COMMAND_DONE interrupt should use.
0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector
1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector

Radio

R/W

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

23.8.2.8 RFACKIFG Register (Offset = 1Ch) [reset = 0h]
RFACKIFG is shown in Figure 23-28 and described in Table 23-172.
Return to Summary Table.
Doorbell Command Acknowledgement Interrupt Flag
Figure 23-28. RFACKIFG Register
31

0
ACKFLAG
R/W-0h

RESERVED
R-0h
23

20
RESERVED
R-0h

12
RESERVED
R-0h

4
RESERVED
R-0h

Table 23-172. RFACKIFG Register Field Descriptions
Bit
31-1
0

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

ACKFLAG

R/W

Interrupt flag for Command ACK

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio

1729

Radio Registers

www.ti.com

23.8.2.9 SYSGPOCTL Register (Offset = 20h) [reset = 0h]
SYSGPOCTL is shown in Figure 23-29 and described in Table 23-173.
Return to Summary Table.
RF Core General Purpose Output Control
Figure 23-29. SYSGPOCTL Register
31

14
13
GPOCTL3
R/W-0h

10
9
GPOCTL2
R/W-0h

24
23
RESERVED
R-0h
8

6
5
GPOCTL1
R/W-0h

2
1
GPOCTL0
R/W-0h

Table 23-173. SYSGPOCTL Register Field Descriptions
Field

Type

Reset

Description

31-16

Bit

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

15-12

GPOCTL3

R/W

RF Core GPO control bit 3. Selects which signal to output on the RF
Core GPO line 3.
0h = CPE GPO line 0
1h = CPE GPO line 1
2h = CPE GPO line 2
3h = CPE GPO line 3
4h = MCE GPO line 0
5h = MCE GPO line 1
6h = MCE GPO line 2
7h = MCE GPO line 3
8h = RFE GPO line 0
9h = RFE GPO line 1
Ah = RFE GPO line 2
Bh = RFE GPO line 3
Ch = RAT GPO line 0
Dh = RAT GPO line 1
Eh = RAT GPO line 2
Fh = RAT GPO line 3

11-8

GPOCTL2

R/W

RF Core GPO control bit 2. Selects which signal to output on the RF
Core GPO line 2.
0h = CPE GPO line 0
1h = CPE GPO line 1
2h = CPE GPO line 2
3h = CPE GPO line 3
4h = MCE GPO line 0
5h = MCE GPO line 1
6h = MCE GPO line 2
7h = MCE GPO line 3
8h = RFE GPO line 0
9h = RFE GPO line 1
Ah = RFE GPO line 2
Bh = RFE GPO line 3
Ch = RAT GPO line 0
Dh = RAT GPO line 1
Eh = RAT GPO line 2
Fh = RAT GPO line 3

1730

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Radio Registers

www.ti.com

Table 23-173. SYSGPOCTL Register Field Descriptions (continued)
Bit

Field

Type

Reset

Description

7-4

GPOCTL1

R/W

RF Core GPO control bit 1. Selects which signal to output on the RF
Core GPO line 1.
0h = CPE GPO line 0
1h = CPE GPO line 1
2h = CPE GPO line 2
3h = CPE GPO line 3
4h = MCE GPO line 0
5h = MCE GPO line 1
6h = MCE GPO line 2
7h = MCE GPO line 3
8h = RFE GPO line 0
9h = RFE GPO line 1
Ah = RFE GPO line 2
Bh = RFE GPO line 3
Ch = RAT GPO line 0
Dh = RAT GPO line 1
Eh = RAT GPO line 2
Fh = RAT GPO line 3

3-0

GPOCTL0

R/W

RF Core GPO control bit 0. Selects which signal to output on the RF
Core GPO line 0.
0h = CPE GPO line 0
1h = CPE GPO line 1
2h = CPE GPO line 2
3h = CPE GPO line 3
4h = MCE GPO line 0
5h = MCE GPO line 1
6h = MCE GPO line 2
7h = MCE GPO line 3
8h = RFE GPO line 0
9h = RFE GPO line 1
Ah = RFE GPO line 2
Bh = RFE GPO line 3
Ch = RAT GPO line 0
Dh = RAT GPO line 1
Eh = RAT GPO line 2
Fh = RAT GPO line 3

23.8.3 RFC_PWR Registers
Table 23-174 lists the memory-mapped registers for the RFC_PWR. All register offset addresses not listed
in Table 23-174 should be considered as reserved locations and the register contents should not be
modified.
Table 23-174. RFC_PWR Registers
Offset
0h

Acronym

PWMCLKEN

RF Core Power Management and Clock Enable

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

Section
Section 23.8.3.1

Radio

1731

Radio Registers

www.ti.com

23.8.3.1 PWMCLKEN Register (Offset = 0h) [reset = 1h]
PWMCLKEN is shown in Figure 23-30 and described in Table 23-175.
Return to Summary Table.
RF Core Power Management and Clock Enable
Figure 23-30. PWMCLKEN Register
31

RESERVED
R-0h
23

20
RESERVED
R-0h

13
RESERVED
R-0h

10
RFCTRC
R/W-0h

9
FSCA
R/W-0h

8
PHA
R/W-0h

7
RAT
R/W-0h

6
RFERAM
R/W-0h

5
RFE
R/W-0h

4
MDMRAM
R/W-0h

3
MDM
R/W-0h

2
CPERAM
R/W-0h

1
CPE
R/W-0h

0
RFC
R-1h

Table 23-175. PWMCLKEN Register Field Descriptions
Bit

Field

Type

Reset

Description

RESERVED

Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.

RFCTRC

R/W

Enable clock to the RF Core Tracer (RFCTRC) module.

FSCA

R/W

Enable clock to the Frequency Synthesizer Calibration Accelerator
(FSCA) module.

PHA

R/W

Enable clock to the Packet Handling Accelerator (PHA) module.

RAT

R/W

Enable clock to the Radio Timer (RAT) module.

RFERAM

R/W

Enable clock to the RF Engine RAM module.

RFE

R/W

Enable clock to the RF Engine (RFE) module.

MDMRAM

R/W

Enable clock to the Modem RAM module.

MDM

R/W

Enable clock to the Modem (MDM) module.

CPERAM

R/W

Enable clock to the Command and Packet Engine (CPE) RAM
module. As part of RF Core initialization, set this bit together with
CPE bit to enable CPE to boot.

CPE

R/W

Enable processor clock (hclk) to the Command and Packet Engine
(CPE). As part of RF Core initialization, set this bit together with
CPERAM bit to enable CPE to boot.

RFC

Enable essential clocks for the RF Core interface. This includes the
interconnect, the radio doorbell DBELL command interface, the
power management (PWR) clock control module, and bus clock
(sclk) for the CPE. To remove possibility of locking yourself out from
the RF Core, this bit can not be cleared. If you need to disable all
clocks to the RF Core, see the PRCM:RFCCLKG.CLK_EN register.

31-11

1732

Radio

SWCU117G – February 2015 – Revised February 2017
Submit Documentation Feedback

IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
Has XFA                         : No
XMP Toolkit                     : Adobe XMP Core 5.6-c015 84.159810, 2016/09/10-02:41:30
Format                          : application/pdf
Title                           : CC13x0, CC26x0 SimpleLink™ Wireless MCU (Rev. G)
Creator                         : Texas Instruments, Incorporated
Description                     : Technical Reference Manual
Metadata Date                   : 2018:08:23 11:18:32+09:00
Create Date                     : 2018:03:13 04:23:49Z
Modify Date                     : 2018:08:23 11:18:32+09:00
Creator Tool                    : TopLeaf 8.0.015
Instance ID                     : uuid:85ad9a7a-8a6f-794d-ac3d-130519ce039b
Document ID                     : uuid:474ef063-683c-7748-9dbe-4814f06bce62
Top Leaf-Version                : Version=tlapi 8.0 15 2016/09/12 support@turnkey.com.au Licence=X0514600
Top Leaf-Profile                : final
Producer                        : Mac OS X 10.12.6 Quartz PDFContext
Page Count                      : 1733
Apple Keywords                  : SWCU117,SWCU117G
Author                          : Texas Instruments, Incorporated
Keywords                        : SWCU117, SWCU117G
Subject                         : Technical Reference Manual

EXIF Metadata provided by EXIF.tools

CC2640x Reference Manual

Navigation menu

Versions of this User Manual:

Views

Navigation