CCS_2719_2P2S_Feb82 CCS 2719 2P2S Feb82
CCS_2719_2P2S_Feb82 CCS_2719_2P2S_Feb82
User Manual: CCS_2719_2P2S_Feb82
Open the PDF directly: View PDF 
.
Page Count: 67
| Download | |
| Open PDF In Browser | View PDF |
MODEL.2719
2 PARALLEL 1 2 SERIAL
1/0 INTERFACE
.Reference Manual
11-, CaHfoniia Computer Systems·
42000096-01
CCS MODEL 2719
2 PARALLEL /
2 SERIAL I/O INTERFACE
Reference Manual
Rev B
Manual #42000095-01
Copyright 1981
California Computer Systems
250 Caribbean Drive
Sunnyvale CA 94086
Copyright 1981 by California Computer Systems.
All rights reserved. No part of this publication may be
reproduced in any form or by any means without express
permission of California Computer Systems.
The information contained in this manual is believed
to be correct at the time of publication. However, CCS
assumes no liability resulting from the use of this
publication.
Publication History:
Revision A printed December 1981
Revision B printed February 1982
Z-80 is a trademark of Zilog, Inc.
CP/M is a trademark of Digital Research, Inc.
OASIS m is a trademark of Phase One, Inc.
M
M
TABLE OF CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
INTRODUCTION
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . •
USING THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2719 BLOCK DIAGRAM . . . . . . . . . . . . . • . . . . . . . . . . . . .
CHAPTER 2
1-1
1-2
1- 3
1-4
CONFIGURING THE 2719
BASE ADDRESS JUMPERS ....•...•............••.. 2-1
INTERRUPT MODE AND PRIORITY CONFIGURATION .•.• 2-4
2.2.1 Mode 0 Configuration ....••••••.•.••... 2-4
2 . 2 . 2 Mode 1 Configuration . . . . . . . . . . . . . . . . . . 2-4
2.2.3 Mode 2 Configuration .......•••..•.•... 2-5
2.3 SERIAL INTERFACES . . . . . . . . . . . . . . . . . . • . . • . . . . . . 2-7
2.3.1 Synchronous Conversion ...•.•..•.....•. 2-7
2.3.2 DCE/DTE Conversion ....••...•.....•..•. 2-7
2.3.3 Non-Standard Handshaking ...•....•..•.. 2-7
2.3.4 Baud Rate Source Jumpers .•.••..••..... 2-9
2 . 3 .5 Protective Ground ...........•••.•..•.. 2-9
2.4 PARALLEL INTERFACE CONFIGURATION ......••.... 2-10
2.4.1 Buffer Direction Jumpers •.........••• 2-10
2.4.2 Buffer Enable Jumpers ...•......•...•. 2-10
2.4.3 Reversing Interface Polarities •.•..•. 2-10
2.5 THE RESET JUMPER . . . . . . . . . . . . . . . . . . . . . . • . . . . • 2-11
2.6 INTERRUPT ACKNOWLEDGE WAITS . . . . . . . . . . . . . . . . . 2-11
2.7 CLOCK PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.8 DATA LATCH ENABLING AND DISABLING . . . . . . . . . . . 2-12
2.9 BAUD RATES IN 2 MHZ SYSTEMS . . . . . . . . . . . . . . . . . 2-12
2.10 OPERATION IN 6 MHZ SYSTEMS ...•.....••..•.•.. 2-12
2.1
2.2
CHAPTER 3
3.1
3.2
3.3
3.4
PROGRAMMING INFORMATION
PORT RELATIVE ADDRESSES ...........••......•..
DART 2719-UNIQUE PROGRAMMING .......•.•.......
CTC 2719-UNIQUE PROGRAMMING ......••.•..•.....
PROGRAMMING THE PIA . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 PIA Command Registers .......••........
3.4.2 PIA Data Direction Registers . . . . . . . . . .
PIA Initialization . . . . . . . . . . . . . • . . . . . .
~.4.3
3-1
3-2
3-3
3-4
3-5
3-7
3-7
CHAPTER 4
HARDWARE DESIGN
4.1
4 •2
4 •3
THE PlAIS . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . 4-1
THE DART . . . . . . • . . . . • • . . . • . . . • . . • . . • . . . . . . • • • . 4- 2
THE eTC . . . . . . . • . . . . . . . • . . . . • . • • . . . . . . . . . . . . . . 4- 3
4.4
4.5
4.6
ADDRESS AND CONTROL LOGIC ....•............... 4-6
INTERRUPT LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
DATA BUFFERING AND LATCHING . . . . . . . . . . . . . . . . . . 4-9
APPENDIX A
A.l
A.2
A.3
A.4
A.5
A.6
USER-REPLACEABLE PARTS . . . . . . . . . . . . . . . . . . . . . . .
SERIAL CONNECTOR PINOUTS . . . . . . . . . . . . . . . . . . . . .
PARALLEL CONNECTOR PINOUTS . . . . . . . . . . . . . . . . . . .
RS-232-C CONNECTOR PINOUTS . . . . . . . . . . . . . . . . . . .
BUS CONNECTOR PINOUTS ........•...............
SCHEMATIC/LOGIC DIAGRAM ....•.•..•....•..•....
APPENDIX B
B .1
B.2
TECHNICAL INFORMATION
A-2
A-4
A-4
A-5
A-6
A-7
SAMPLE DRIVERS
CP/M DRIVER ."................................. B-2
OASIS DRIVER ..•............•................. B-8
CHAPTER 1
INTRODUCTION
1.1
GENERAL DESCRIPTION
The CCS Model 2719 is capable of interfacing a wide
variety of peripheral equipment
to
Z-80-based
CPUs.
Software
and hardware options give a high degree of
flexibility to the 2719 1s two serial and two parallel I/O
ports. The serial ports are controlled by a Z-80 DART (Dual
Asynchronous
Receiver/Transmitter),
which
handles
asynchronous serial data transfers in all common formats.
Baud rates up to 11S.2K are available. The parallel ports,
each controlled by a 6821 PIA
(peripheral
Interface
Adapter), are designed to implement Centronics interfaces,
but each may also be used as two unidirectional 8-bit ports
with 2-line handshaking or as one unidirectional 16-bit
port.
The 2719 fully supports the three Z-80 interrupt modes
for all ports.
Separate headers allow the user to select
the Mode 0 or Mode 2 interrupt priority level and the
devices which will directly control the INT* line for Mode 1
and Mode 2 interrupts.
(In Mode 0 the INT* line is
controlled by the system1s Interrupt Controller.) The 2719
also supports CCSls fast Mode 2 Interrupt Daisy Chain
Look-Ahead Scheme as implemented in CCS Systems 300/400.
Though designed especially for use with CCS Systems
300/400, the 2719 is compatible with CCS System 2210 as well
as with a majority of the Z-80-based S-100 systems presently
available.
The
base address of the I/O ports is
jumper-selectable. Clock phase, Interrupt-Acknowledge wait,
and reset options allow the user to meet the special
conditions of specific systems.
1-2
1.2
INTRODUCTION
USING THIS MANUAL
This manual is intended to provide information required
by system integraters, troubleshooters,
and programmers.
Chapter 2 deals with
board
configuration,
including
hardware-configured serial and parallel interface options.
Chapter 3 discusses the 2719-unique programming requirements
of the DART and CTC and provides complete programming
instructions for the PIAs. Chapter 4 presents a detailed
discussion of the hardware design of the 2719, and is
intended to be read in conjunction with frequent references
to the Schematic/Logic Diagram included, along with various
technical illustrations and tables, in Appendix A. Sample
drivers for the serial and parallel port drivers for CP/M
and OASIS operating systems are provided in Appendix B.
INTRODUCTION
1.3
1-3
SPECIFICATIONS
I/O INTERFACES
SERIAL:
Two Asynchronous Ports Meet EIA RS-232-C
Standard, Full or Partial Primary Channel
Synchronous Capability (SIO/0 Plug-Compatible)
Easy DCE-to-DTE Reconfiguration
Non-Standard Handshaking Options
Programmable (Z-80 CTC) or External Baud Rates
PARALLEL:
Two Centronics-Type Ports
Hardware and Software Reconfiguration Options
Port Buffers Disabled When Cable Disconnected
SYSTEM INTERFACE
S-100: Complies with IEEE Task 696.l/D2
Supports All Three Z-80 Interrupt Modes
Supports CCS's Mode 2 Interrupt Extended
Daisy Chain Look-Ahead Scheme
Jumper-Selectable Board Base Address
Full Buffering of Bus-Driving Outputs,
Schmitt-Trigger Bus Receiver Inputs
POWER
+8 Volts Regul'ated On-Board to +5 Volts
+16 Volts Regulated On-Board to +12 Volts
-16 Volts Regulated On-Board to -12 Volts
Consumption:
.75 Amps at +8 Volts
.05 Amps at +16 Volts
.05 Amps at -16 Volts
Heat Burden:
110 gram-calories/minute
.45 BTU/minute
ENVIRONMENTAL REQUIREMENTS
Temperature:
Humidity:
o to 70 C. (32 to 155 F.)
Up to 90% Non-Condensing
1-4
1.4
INTRODUCTION
2719 BLOCK DIAGRAM
V10-7 -----
INT-
ROY -
INTERRUPT
MODE LOGIC
ru
Il
H
CTC
-'"=.J
XTAL
='-
I
r
ASYNC
SERIAL PORT
AO-7 ----+
ADDRESS &
SELECT LOGIC
CONTROL _
SIGNALS
I
~
~
~I--:I-l
DART
~
ASYNC
SERIAL PORT
CONTROL
LOGIC
PIA
....
~
CENTRONICS
PARALLEL PORT
010-7 ~ DATA IN J.,..~.--
BUFFER
DATA ~
OUT
000-7 ~ BUFFER
J----..
& LATCH
PIA
CENTRONICS
PARALLEL PORT
CHAPTER 2
CONFIGURING THE 2719
The 2719, while designed to be flexible, has also been
designed to require as little configuration as possible in
its primary environment, CCS Systems 300/400. When the 2719
is added to a System 300/400, only the 1M2 Header and
Protective Ground Jumper require configuration.
All other
headers and jumpers are shipped configured for a System
300/400. However, if the 2719 is used in a CCS System 2210
or a non-CCS system, additional configuration will be
required. This chapter includes configuration instructions
for all board options.
Jumper and header locations are
shown in Figure 2-1. Table 2-2 briefly defines each option.
2.1
BASE ADDRESS JUMPERS
Table 2-1.
BASE ADDRESSES
-----------------------------The CTC channels and
serial and parallel ports
occupy sixteen contiguous
port addresses (for relative locations see Table
3-1) .
The A7-A4 jumpers
allow the user to select
the base address of the
2719 at any multiple of 16
(10H) between 0 and 255
(00-FFH) . Table 2-1 shows
the jumper settings for
all possible base addressese
The 2719 is configured at the factory for a
base address of 50H.
JUMPER
SETTINGS
A7
A6
A5
A4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BASE
HEX. DEC.
------------------------------
1
1
1
00
10
20
30
40
50
60
70
80
90
AO
BO
CO
DO
EO
FO
00
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
------------------------------
Serial Port
Baud Rate
Source Jumpers
Protective
Ground
Jumper
Serial Port
DCE/DTE
Select Headers
Clock
Phase
Jumper
Parallel Port
Buffer Enable
Jumpers
Parallel Port
Buffer Direction
Jumpers
r
I':tj
1-'-
1O
C
t;
CD
N
POND
0
SER B CLK
SOND
(')(1)
oT
'"'"
0:11
I
C
::s:
I
,..r,
CJ
~
'" I .
'"
' I 0~
O I,
1BDIR
~
" INT
EXTc::::J
~
SER A CLK
Z
"DcTC
,..---,..------'
::r::
1 ADIR
~';
, -l C 1 ~
U
'.
trJ
VIO
VI1
:::0
~----I-:"---
0
C
i'lf
2BDIR
I
1
II
L
,
.,,;
r
c::::J
ADDR SEL
P2A
P2B
I~M1'2
1
~ M
{l
.J
1
j
VI7
~
IMO
8
INT;
1M 2 ~~------,
DAIBYDSBL
H
,1
,.
I'
VI2
VI3
VI4
VIS
vie
()
DLE
DSBL c::::J EN
A7001
lAS
A5
A4
'J
II
D
RDYCJ
IMODE RES
c::::JCJ
0,1 2
_____ ______________ ______________ ______________ ___________~r
0
Z
CJ)
Interrupt
Mode
Headers
Interrupt
Acknowledge
Wait Jumper
Interrupt
Mode
Jumpers
Reset
Signal
Jumper
Port
Address
Jumpers
o
2ADIR
-II "
'i ''
DART
:~:
i
,
trJ
L'1
2AEN
;;:Joo
::0
0
~:::
oT
0:11
"'0
~
D
;;:111
I:lj
0
1AEN
CJ
EXT c::::J INT
.....
Y
1BEN
Data Latch
Enable
Jumper
CONFIGURING THE 2719
2-3
Table 2-2.
: OPTION
: LABEL
: FACTORY
: CONFIGURATION
USER OPTIONS
: FUNCTION
,--------------------------------------------------------------------------ADDR SEL
Selects four most significant bits of
A7=0, A6=1,
A5=0, A4=1
2719's base I/O address.
RES
Open
If closed, 2719 is reset by RESET* as
well as by POC* and SLY CLR*.
DLE
EN
EN enables latching of all data written
to 2719; DSBL disables latching.
Selects uninverted (~) or inverted (-~)
system clock for CTC and DART clocks.
-¢/f/J
SER A CLK
SER B CLK
INT
INT
Selects CTC Ch. 0/1 (INT) or RS-232-C
line 15 (EXT) for Serial Port A/B
receiver and transmitter clocks.
SER A DCE/DTE
SER B DCE/DTE
DTE (standard)
DTE (standard)
Serial Port A/B interfaces to DTE device if header pin 1 at T, to DCE
device if pin 1 at C. May be modified for non-standard handshaking.
PGND/SGND
Configuration
required
Connects Serial Interface Protective
Ground to either Signal Ground or
Chassis Ground.
I
Conditions Parallel Port 1/2 Channel
AlB for input (I) or output (0)
1ADIR
1BDIR
2ADIR
2BDIR
o
1AEN
1BEN
2AEN
2BEN
Open
Open
Open
Open
If closed, permanently enables Parallel
Port 1/2 Channel A/B; if open, Channels A and B enabled by lows on interface pins 30 and 19 respectively.
IMO
Unconfigured
Selects VI* line controlled by 2719 for
Z-80 Mode 0 Interrupts.
IM1,2
CTC and DART
closed
If circuit closed straight across, corresponding device can pull INT* low.
1M2
Unconfigured
Selects daisy-chain priority level for
Z-80 Mode 2 Interrupts.
DAISYDSBL
Closed
If open, disables VIO* input, allowing
use of VIO* in Interrupt Mode O.
IMODE
2
Enables (2) or disables (0,1) output of
Interrupt Vector during appropriate
Interrupt Acknowledge cycles.
o
I
---------------------------------------------------------------------------
2-4
2.2
CONFIGURING THE 2719
INTERRUPT MODE AND PRIORITY CONFIGURATION
Three header areas and two jumpers allow you to tailor
2719 interrupts to a particular system. If the system uses an
interrupt controller, you will need to configure the 2719 for
Mode 0 interrupts. If the system does not implement vectored
interrupts, you will need to configure for Mode 1, in which an
interrupt causes an automatic restart at location 0038H. If
the system supports the powerful Mode 2 Interrupt Daisy Chain,
as CCS Systems 300/400 do, you should configure for Mode 2.
The three header areas are labelled IM0, 1M2, and IMl,2
in accordance with the interrupt modes to which they apply.
IMl,2 is a 2x6 pad matrix, hardwired for the standard
configuration, which may be altered by the installation of
jumper wires or header pins and shorting plugs. IM0 and 1M2
are socketed 2x8 headers.'
The Interrupt Mode (IMODE) and
Daisy Chain Disable (DAISYDSBL) Jumpers are hardwired for Mode
2 and must be reconfigured for Mode 0 or Mode 1.
2.2.1
Mode 0 Configuration
The first task in configuring for Mode 0
is
to
reconfigure the IMODE jumper, cutting the trace labelled 2 and
installing a jumper in the 0,1 position. Next, cut the CTC
and DART traces of the IMl,2 Jumpers and the DAISYDSBL trace.
Finally, install the 16 pin DIP header in the IM0 socket and
wire the header cover to select the VI* line by which each
device will assert its interrupt. Remember that the lower the
number of the VI* line, the higher the interrupt priority.
The pins corresponding to the VI* lines are labelled 0 through
7; the six interrupt signal pins are labelled C, D, lA, IB,
2A, and 2B.
Pins 9 and 16 are not used. More than one
interrupt line may be tied to one VI* line; it will then be up
to the interrupt service routine called when that VI* line is
asserted to determine which device generated the interrupt.
2.2.2
Mode 1 Configuration
Configuring for Mode 1 involves: 1) leaving the IM0 and
1M2 Headers unconfigured; 2) reconfiguring the IMODE Jumper by
cutting the trace labelled 2 and installing a
jumper in the
0/1 position; 3) cutting the DAISYDSBL trace; and 4) either
leaving the IMl,2 Jumpers as they are or installing jumpers,
CONFIGURING THE 2719
2-5
depending on whether or not parallel port interrupts are to
handled through the CTC.
If they are (see Chapter 3 for
explanation of how this is done), the IM1,2 Jumpers should
left as they are.
If parallel port interrupts are to
asserted directly by the parallel ports,
jumpers should
installed in positions PIA, PIB, P2A, and P2B.
2.2.3
be
an
be
be
be
Mode 2 Configuration
The Z-80 Mode 2 Interrupt Daisy Chain, when extended
beyond four peripheral devices, requires look-ahead logic to
ensure
that
all
devices
are
properly
informed
of
higher-priority interrupts within the allotted time.
CCS
Systems 200, 300, and 400 implement a unique look-ahead scheme
in which: 1) each board participating in the daisy chain
asserts its interrupt priority by forcing a given vectored
Interrupt bus line low; and 2) a board is prevented from
interrupting when a lower-numbered VI* line is low.
Thus
there are nine interrupt priority levels, 0-8; the priority 0
board controls VI0* and senses no VI* lines, while the
priority 8 board senses all VI* lines and controls none. The
1M2 Header allows the user to select the interrupt priority
level of the 2719 by selecting which VI* line(s) the board
will be sensitive to and which VI* line it will pull low.
System 300/400 interrupt priorities may be determined at
the system implementer's discretion, depending on system
components and application.
However,
the priority scheme
shown below should be appropriate for the majority of systems.
The System Processor is hardwired for Level 0; it is the only
board whose'priority is fixed.
---->
Level
Level
Level
Level
Level
Level
Level
Level
0:
1:
2:
3:
4:
5:
7:
8:
2820
2805
2830
2719
2831
2833
2822
2832
System Processor
Wallclock/Terminator
Six-Channel Serial I/O
2 Parallel/2 Serial I/O
Arithmetic Processor
GPIB Interface
Floppy Disk Controller
Hard Di~k Controller
Note that gaps are allowed in the priority structure; thus, it
is not necessary to reconfigure a level 3 board to level 2 if
there is no level 2 board in the system. However, no priority
level may be occupied by more than one board.
2-6
CONFIGURING THE 2719
Figure 2-2.
1M2 HEADER CONFIGURATION
LEVEL 1
LEVEL 2
LEVEL 3
1
2
1
1
0
2
2
0-
3
4
5
3
4
5
3
4
5
6
7
6
7
6
7
0
0
INT
0
INT
LEVEL 4
INT
LEVEL 6
LEVEL 5
1
0
0
1
0
0
1
0
0
2
0
0
2
0
0
2
0
0
3
4
5
0
0
3
4
5
0
0
0
0
N
3
4
5
0
0
0
0
0
0
6
0
~
6
7
N
o
o
0
6
0
7
0
INT
o
7
INT
0
LEVEL 7
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
~
LEVEL 8
1
2
3
4
5
6
7
INT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INT
INT
CONFIGURING THE 2719
2-7
To configure the 1M2 Header, determine the priority level,
then: 1) tie all lower-numbered left-column pins straight
across;
and 2) tie the pin corresponding to the 2719's
priority level to pin 9, labeled INT. Note that the lowest
level to which the 2719 may be assigned is 1: the board is
hardwired to sense the VI0* line, which is reserved as the
2820 System Processor's priority-assertion line. Figure 2-2
shows configuration of 1M2 for all priority levels.
2.3
SERIAL INTERFACES
2.3.1
Synchronous Conversion
To
convert
the
2719
serial
ports
for
synchronous
communications,
simply remove the Z-80 DART (U3) and replace
it with a Z-80 SIO/0 (neither the SIO/l nor the SIO/2 is
plug-compatible with the DART).
The SIO/0 is not supplied
with the board.
2.3.2
DCE/DTE Conversion
Each serial port interface includes a 16-pin DIP header with
cover for selecting whether the port-will interfac~ to a DTE
(Data Terminal Equipment)
or
DCE
(Data
Communication
Equipment) device.
Since most peripherals act as DTE, the
2719 is shipped configured to interface to DTE devices.
To
reconfigure a port to interface to a DCE device, simply turn
the port's DCE/DTE header so that instead of having pin 1 in
pin 1 of the socket (labeled T), pin 1 is in pin 9 of the
socket (labeled C).
2.3.3
Non-Standard Handshaking
Some devices using the
RS-232-C
interface,
especially
printers, use non-standard handshaking. To interface such a
device, you will need to reconfigure a DCE/DTE
Header
according to the requirements of the peripheral. Figure 2-3
shows the header pinouts and the standard DTE wiring.
Note
that, besides the RS-232-C lines normally used by the 2719's
2-8
CONFIGURING THE 2719
serial ports, two other lines, 19 (Secondary Request To Send)
and 11
(Unassigned),
are also made available for special
handshaking. Figure 2-4 shows a header modified for a device
such as an NEC Spinwriter printer which handshakes on RS-232-C
pin 19 (Sec RTS). -Assuming that the model driver in Appendix
B is used, the printer's handshake signal must toggle the DCD
bit in the DART channel's Status Register; thus RS-232-C pin
19 must be tied to the DART's DCD* input, rather than pin 20
(DTR) as in the standard DTE configuration. The procedure for
reconfiguring the header for a Spinwriter is as follows: 1)
remove the jumper wires connecting pin 1 to pin 16 and pin 8
to pin 10; 2) install a jumper wire connecting pin 1 to pin
10; 3) leave all other header wires as they are.
Figure 2-3.
Sit> t:w~
STANDARD DTE HEADER CONFIGURATION
SIO Side
DCD
DTR
CTS
RTS
'TxD
RxD
1
2
3
4
5
6
7
8
Figure 2-3.
DCD
DTR
CTS
RTS
TxD
RxD
0
0
RS-232-C Side
0
0
><
><
0
0
0
0
16
15
14
13
12
11
10
9
DTR (20)
DSR (6)
RTS (4 )
CTS (5 )"
RD (3)
TD (2)
Sec RTS (19)
NDEF (11)
SPINWRITER DTE HEADER CONFIGURATION
1
2
3
4
5
16
15
14
13
12
6
11
7
10
8
9
DTR (20)
DSR (6)
RTS (4)
CTS (5)
RD (3)
TD (2)
Sec RTS (19)
NDEF (11)
CONFIGURING THE 2719
2.3.4
2-9
Baud Rate Source Jumpers
If you plan to use a DART channel to interface a DCE device,
you may want that channel's baud rate clock to be supplied by
the DCE device. The Channel A and B Baud Rate Source Jumpers,
labeled SER A CLK and SER B CLK, allow each DART channel's
clocks to be controlled by either the CTC or RS-232-C li~e 15,
TSEC(DCE),
from the peripheral. The jumpers are hardwired in
the INT position,
selecting the internal (CTC) baud rate
sources.
To select the external (peripheral) baud rate
source, cut the INT trace and install a jumper wire in the EXT
position of the appropriate Baud Rate Source Jumper.
[Please note that because DART pins RxCA and TxCA are tied
together
on the PC Board, the Channel A Receiver and
transmitter Clocks cannot be separately controlled.]
2.3.5
Protective Ground
Protective Ground is defined as the supply current return
path, not a signal current return path. It is intended to
equalize the voltage potential of the terminal and the
mainframe, and should be implemented whenever the terminal and
the mainframe are connected to different power sources which
may have different ground potentials.
If
both
serial
terminals interfaced through the 2719 are to be connected to
the same outlet as the mainframe, the protective ground
feature need not be implemented.
At the upper left corner of the board are two jumper pads
labeled PGND and SGND. These allow the user to select one of
two implementations of the RS-232-C Protective Ground signals
for both ports. The recommended implementation is to run a
green wire from the PGND pad to the mainframe chassis, with an
alligator clip or other convenient method for connection.
This conforms to the RS-232 design specifications, ensuring
that terminal and mainframe have the same potentials. Use
this method with CCS-supplied terminals.
Some terminals,
however, tie Protective Ground and Signal Ground together or
use the Protective Ground as the Signal Ground.
If you are
using such a terminal with the 2719, you will need to install
a 100 ohm, 1/2 Watt resistor (as per EIA standard RS-422-A)
between the PGND and SGND pads.
2-10
2.4
CONFIGURING THE 2719
PARALLEL INTERFACE CONFIGURATION
2.4.1
Buffer Direction Jumpers
Bidirectional buffers are used on the four parallel port
data channels. The direction of data flow is determined by
the Parallel Port Buffer Direction Jumpers lADIR, lBDIR,
2ADIR, and 2BDIR, which are hardwired for the standard
Centronics-type interface configuration.
Channel B of each
port (Centronics data bus) is hardwired in the 0 position for
output; Channel A of each port (Centronics status bus) is
hardwired in the I position for input.
To change the
direction of a buffer, cut the existing trace and ~nstall a
jumper wire in the opposite position. [Please note that while
each channel may be used for either input· or output, the
characteristics of the PIA handshaking signals make Channel B
more suited for output and Channel A more suited for input.]
2.4.2
Buffer Enable Jumpers
The parallel interfaces are designed so that lows on
interface lines 30 and 19 enable the Channel A and Channel B
interface buffers respectively; otherwise the enable inputs to
the buffers are pulled high. Thus, the buffers will not be
enabled unless the interface cable is connected. On the
Centronics interface lines 30 and 19 are defined as ground
lines.
However, some Centronics-type peripherals may not
support the lines as defined. If this is the case, or if the
interface is used in a non-Centronics configuration and the
peripheral does not assert inter£ace lines 30 and 19 low,
jumper wires must be installed between the appropriate Buffer
Enable Jumper pads to permanently enable the buffers.
The
four Buffer Enable Jumpers are labeled lAEN, lBEN, 2AEN, and
2BEN.
2.4.3
Reversing Interface Polarities
The parallel port buffers were selected to support the
Centronics interface polarities: positive logic data and
negative logic handshaking. However, pin-compatible buffers
may be substituted for the buffers used on the parallel ports
CONFIGURING THE 2719
2-11
if positive-logic handshaking or negative-logic data are
required.
For negative-logic data, replace the appropriate
8104/8304 with an 8103/8303; for positive-logic handshaking,
replace the appropriate 74LS367A with a 74LS368A.
2.5
THE RESET JUMPER
If
the 2719 is used in a system which does not
automatically assert SLVCLR* when RESET* is asserted, a jumper
must be installed between the pads labelled RES.
This is
necessary primarily when the board is used in Cromemco
systems. It is not necessary with CCS systems.
If you are
uncertain about whether the Reset Jumper is required, consult
the system documentation; if you remain uncertain, call the
system manufacturer.
2.6
INTERRUPT ACKNOWLEDGE WAITS
If the 2719 is used with a CCS 2810 CPU, a wait state is
required in all Interrupt Acknowledge cycles to ensure that
the CTC has time to put its vector on the bus before the CPU
tries to read it.
To enable Interrupt Acknowledge wait
states,
install a
jumper wire between the pads labeled ROY.
This jumper is not required if the 2719 is used in a System
300/400. If the 2719 is used in a non-CCS system, this jumper
mayor may not be required; experiment, and install the jumper
if necessary.
2.7
CLOCK PHASE
In some systems,
including the CCS 2210 (with the 2810
CPU board), the system clock on bus pin 24 and the CPU clock
are of opposite phase. Z-80 devices in a system must all have
clocks of the same phase to work together. The Clock Phase
Jumper allows the user to invert the phase of the system clock
signal used on the 2719 as necessary. If the 2719 is used in
a CCS System 300/400 or any other system in which the bus
clock is in phase with the processor clock,
set the Clock
Phase Jumper to the rightmost (0) position. If the 2719 is
used in a system (including the CCS System 2210) featuring the
CCS 2810 CPU board or any other system in which the bus clock
and processor clock are of opposite phase, set the Clock Phase
Jumper to the leftmost (-0) position.
2-12
2.8
CONFIGURING THE 2719
DATA LATCH ENABLING AND DISABLING
The OLE jumper has been included on the 2719 to allow
disabling of the Data Out Latch. The jumper is hardwired in
the EN position, which is required if the 2719 is used with a
CCS 2810 CPU. When the 2719 is used in a System 300/400,
the
jumper may be in either the EN or DSBL position. However,
some CPU's may require that data corning onto the board not be
latched.
If you are using a non-CCS CPU, experiment, then
disable the latching by cutting the EN trace and installing a
jumper wire in the DSBL position if the 2719 cannot accept
latched data from your CPU.
2.9
BAUD RATES IN 2 MHZ SYSTEMS
The CTC cannot accept a CLK/TRG input whose frequency is
greater than half the system clock frequency. Thus, if you
use the 2719 in a 2 MHz system, you must replace the 1.8432
MHz crystal pack in the lower right corner of the board with a
74LS74 dual flip-flop. The crystal pack is not socketed; you
will need to unsolder its four pins and remove the solder from
the other pads before installing the 74LS74.
(If you install
the 74LS74, then at a later date install the 2719 in a 4 MHz
system, you need not replace the crystal pack unless you want
to be able to select baud rates greater than 9600.)
Note that installation of a 74LS74 will necessitate
changes to the serial port drivers if they have been written
for the 2719 with the crystal pack. See Section 3.3.
2.10
OPERATION IN 6MHZ SYSTEMS
To use "the 2719 in a 6 MHz system, you must replace four
chips: the Z-80A CTC with a Z-80B CTC; the Z-80A DART with a
Z-80B DART (or Z-80B SIO/0 for synchronous capability); and
both 6821 PIAs with 68B2l PIAs.
Some 2719 boards may be
shipped with 68B2l's, in which case replace ment of the PIAs
will not be necessary; check the chips (not the silkscreen
labels) before replacing the PIAs.
Baud rate programming will not change if the CTC is used
in the co~nter mode with the 1.8432 MHz crystal pack. In the
timer mode or with a 74LS74 installed instead of the crystal
pack, multiply the 4 MHz values in Table 3-3 by 1.5 (75 baud
will not be available).
CHAPTER 3
PROGRAMMING INFORMATION
This section is provided for those who wish to write
their own drivers for the 2719's serial and/or parallel ports.
Full instructions for programming"the PIAs are given, as they
may not be readily available. programming options for the
Z-80 SIO and CTC are quite elaborate, and are not given in
this manual.
Complete instructions are given in the Z-80
Family Programming Reference Manual included in CCS System
300/400 documentation packages or available separately from
CCS, as well as in a variety of other publications, a few of
which are listed below. Only the programming limitations and
requirements stemming from the implementation of the SIO and
CTC on the 2T19 are treated in this chapter.
AN
INTRODUCTION TO MICROCOMPUTERS, Osborne and
Associates, Inc. (Berkeley, CA: 1978).
ZILOG MICRCOMPUTER COMPONENTS DATA BOOK, Zilog, Inc.
(Cupertino, CA: 1980).
MOSTEK MICROCOMPUTER DATA BOOK, Mostek Corporation
(Carollton, TX: 1979).
3.1
PORT RELATIVE ADDRESSES
The base address of the 16 ports occupied by the 2719 is
selected by the user as described in Chapter 2, but within the
l6-port block the relative addresses of the ports are fixed.
Table 3-1 shows the relative addresses of the CTC channels,
the SIO data and command/status ports, and the PIA registers.
Addresses in parentheses are the hexadecimal port addresses if
the standard base address of 50H, required by CCS-supplied
software, is used.
3-2
PROGRAMMING INFORMATION
Table 3-1.
PORT RELATIVE ADDRESSES
----------------------------------------------------------1
1
CTC:
CHANNEL 0
Base (50)
CHANNEL 1
Base+l (51)
CHANNEL 2
Base+2 (52)
CHANNEL 3
Base+3 (53)
1
1-----------------------------------------------------------1
1
DART:
1
A DATA
Base+4 (54)
A COMMAND
Base+5 (55)
B DATA
Base+6 (56)
B COMr~D
Base+7 (57)
1
1
1-----------------------------------------------------------1
1
1
PIAl:
A DATA/DIR
Base+8 (58)
B DATA/DIR
Base+9 (59)
A CONTROL
Base+A (SA)
B CONTROL
Base+B (5B)
1
1
1-----------------------------------------------------------1
1
1
PIA2:
3.2
A DATA/DIR
Base+C (5C)
B DATA/DIR
Base+D (5D)
A CONTROL
Base+E (5E)
B CONTROL
Base+F (SF)
1
1
DART 2719-UNIQUE PROGRAMMING
Table 3-2 shows which DART pins are connected to which
RS-232-C lines. The RS-232-C signals are identified as DTE or
DCE according to whether the Serial Port DCE/DTE Header is in
the DTE or DCE position (see Section 2.3.2).
The programmer
should keep in mind that commmand and status bits in the
programming guide are named for the DART pin and not the
RS-232-C interface line--for example, the RTS command bit
actually controls the CTS interface line when the Serial Port
DCE/DTE Header is in the DTE position.
Table 3-2.
SIO
1
PIN
SIGNAL
1
I
15/26
12/28
17/24
18/23
16/25
19/22
TxD
RxD
RTS
CTS
DTR
DCD
1
1
1
1
1
1
DART/RS-232-C INTERFACING
RS-232-C (DTE)
PIN
SIGNAL
RS-232-C (DCE)
PIN
SIGNAL
1
1
3
2
5
4
6
20
2
3
4
5
20
6
1
1
1
1
1
1
1----------------1-----------------------------------1
1
1
1
1
-I
I
RD
TD
CTS
RTS
DSR
DTR
(BB)
(BA)
(CB)
{cAl
(CC)
(CD)
TD
RD
RTS
CTS
DTR
DSR
(BA)
(BB)
{cAl
(CB)
(CD)
(CC)
PROGRAMMING INFORMATION
3-3
Programming limitations of the DART are listed below.
They result from the fact that pins W/RDYA*, W/RDYB*,
RIA*,
and RIB* are not connected on the PC Board.
1.
Bit 7 of Command Register I (Wait/Ready Enable)
should be 0.
Bits 6 and 5 are don't-care bits.
2.
Bit 4 of Status Register 0 will always be low.
will not affect External Status Interrupts.
3.3
This
CTC 2719-UNIQUE PROGRAMMING
The CTC on the 2719 is used to provide programmable clock
signals for the DART and to generate Mode 2 interrupts for the
PIAs.
In the factory configuration, Channel 0 provides the
clocks for Serial Port A, Channel 1 provides the clocks for
Serial Port B, Channel 2 interrupts for PIAl,
and Channel 3
interrupts for PIA2.
Please note that, for each serial port,
both the Receiver Clock and the Transmitter Clock
are
controlled by the same CTC signal and therefore cannot be
independently programmed.
The specific programming requirements for the CTC on
2719 are listed below.
1.
Channels 0 and 1, which determine the serial port
baud rates, may be programmed in either the counter
mode or the timer mode.
Interrupts should be
disabled. Table 3-3 shows programming options for
common baud rates.
2.
If Mode 2 interrupts from the PIAs are desired,
Channels 2 and 3 must be progran~ed in the counter
mode with interrupts enabled, rising edges counted,
and a time constant of 1. Thus the two bytes sent
after the interrupt vector to initialize Channel 2
or 3 are D7H followed by 0lH.
the
3-4
PROGRAMMING INFORMATION
Table 3-3.
TIME CONSTANTS FOR COMMON BAUD RATES
TIME CONSTANTS
--------- ---------------------------------------CRYSTAL
BAUD
RATE
75
110
134.5
150
300
600
1200
2400
4800
7200
9600
19.2K
38.4K
57.6K
115.2K
4 MHZ
C
T
192
96
48
24
16
12
208
142
116
104
52
26
13
FLIP-FLOP
2 MHZ
C
T
104
52
26
13
104
71
58
52
26
13
4 MHZ
C
T
208
104
52
26
17
13
6
3
2
1
C = Counter Mode (Command Byte = 47H)
T = Timer Mode, Prescaler of 16 (Command
DART Clock Rate is assumed to be 16x
3.4
208
142
116
104
52
26
13
=
07H)
PROGRAMMING THE PIA
Each PIA has six accessible (read and write)
registers:
two Data Registers,
two Data Direction Registers, and two
Command Registers. Register selection is determined by two
Register Select inputs (RS0, RS1) controlled by A0 and Al and
by Bit 2 of the Command Register. Table 3-4 shows how each
register is selected.
PROGRAt'1MING INFORMATION
3-5
Table 3-4.
PIA REGISTER SELECTION
I
1
I
1 Al
A0 CRA2 CRB2 1 REGISTER
1
1---------------------1------------------------1
I 0
0
1
X 1 Data Register A
I
1 0
0
0
x l ' Data Direction Reg A 1
1 0
1
X I I Data Register B
1
1 0
1
X
0
I Data Direction Reg B I
1 1
0
X
X 1 Command Register A
1
1 1
1
X
X 1 Command Register B
1
--------------------- ------------------------
3.4.1
PIA Command Registers
The Command Registers may be both read and written to.
Written to, they determine
all
programmable
operating
parameters for the PIA channels except data direction. The
current command and interrupt status (Bit 7) can be obtained
by reading the Command Register. Command Register format is
as follows:
.'
r L R 61J t"At>
, ....... ' ......".. "'>~'-..• r.~'"'
.:5<::·'r
"~'i\J ~
'..'...'.--...~..•-
. " .. , ".
--2{~~-~p_______~ _____ ~ _____ ~_~ ___ ~___ ~::~ ____ ~J?
1
D7
1
1
1
D6
I
I
D5
I
D4
I
D3
I
I
D2
I
I
Dl
I
D0
1
I
CRA 1 IRQAll IRQA21
CA2 CONTROL
I DDRA 1 CAl CONTROL I
1------1------1--------------------1------1-------------I
CRB 1 IRQBll IRQB21
CB2 CONTROL
I DDRB I CBl CONTROL I
Bit 0
This bit disables interrupts by CAl/CBl
when 0, and enables interrupts by CAl/CBl
when 1. See Table 3-5.
Bit 1
This bit selects the edge of CAl/CBl (the
ACKA*/ACKB* interface line) which will set
Bit
7 of the Command Register, a 1 .
selecting the rising edge
and
a
0
selecting the falling edge.
See Table
3-5.
3-6
PROGRAMMING INFORMATION
Table 3-5.
CAl/CA2 INPUT CONTROL
-----------------------------------------------------------CRx-l I CRx-2 lINT FLAG CRx-7
lINT OUTPUT IRQx*
------------------------------------------------------------
o
0
Set high by high-tolow transition of Cxl
I
1
I
I
I
I
o
1
Set high by high-tolow transition of Cxl
1
0
Set high by low-to1
high transition of Cxl
1
1
Set high by low-to1
high transition of Cxl 1
1
Disabled: stays
high
Goes low when
CRx-7 goes high
Disabled: stays
high
I
Bit 2
If this bit is 1, a Data Register is
accessed
at
the
Data/Data Direction
address: if it is 0, a Data Direction
Register is addressed.
Bits 3-4
These
bits control output CA2/CB2 as
indicated in Table 3-6. Channel A timing
uses negative edges of E, while Channel B
uses positive edges.
Table 3-6.
1
Goes low when
CRx7 goes high
CR4
CR3 I
CA2/CB2 OUTPUT CONTROL
Cx2 FUNCTION
1
1----------1---------------------------------------------I
1 0
0
1 Set by exl going active: cleared by read
1
1
~I
I
0
1
.' 1
I
1
I
1
1
1
0
1
1
I
(Channel A) or write (Channel B)
I
Pulses low immediately after read (Channell
A) or write (Channel B)
I
Always low
1
Always high
I
Bit 5
This bit must be 1 to condition CA2/CB2 as
an output. On the 2719 CA2/CB2 may not be
used as an interrupt input.
Bit 6
This is the CA2/CB2
interrupt
flag.
Because on the 2719 CA2/CB2 cannot be used
as an interrupt input,
this bit will
always be 0. This bit is not affected by
a write to the Command Register.
PROGRAMMING INFORMATION
Bit 7
3.4.2
3-7
This is the CAllcBl interrupt flag. When
this bit is 1, IRQA*/IRQB* has
been
asserted by the appropriate transition of
CAl/cBl. This bit is cleared when the
channel1s Data Register is read and is not
affected
by
a write to the Command
Register.
PIA Data Direction Registers
Bits 0-7 of the Data Direction Register control the
direction of data lines 0-7 respectively. If a bit is 0, the
corresponding data line is an input; if a bit is 1, the
corresponding data line is an output.
A Data Direction
Register can be accessed only if Bit 2 of the Command Register
for the same channel is 0. Because of the way the PIA data
lines are buffered on the 2719, ALL BITS OF A CHANNEL MUST BE
PROGRAMMED FOR THE SAME DIRECTION and the data direction
programmed for a channel must agree with the setting of the
corresponding Parallel Port Data Direction Jumper as described
in Section 2.4.1.
3.4.3
PIA INITIALIZATION: CENTRONICS CONFIGURATION
The following sequence initializes a parallel port in the
standard Centronics configuration.
a. Output 00H to both Ch. A and Ch. B Control Ports to
select DDR.
b. Output to Data/Dir Ports (00H to Ch. A and 0FFH to
Ch. B) to select direction.
c. Output 2CH (or 2DH for interrupts) to both Ch. A and
Ch. B Control Ports to set the PIA mode.
d. Input from both Ch. A and Ch. B Data/Dir Ports to
clear the status bits.
CHAPTER 4
HARDWARE DESIGN
Two 6821 PIAs and a Z-80 DART provide the two parallel
and two serial ports of the 2719.
Most of the interface
functions are provided by these three chips. A Z-80 CTC is
employed to generate baud rate clocks for the two DART
channels and Mode 2 interrupts for the two PIAs. Additional
logic supports interrupt capability in all three Z-80 modes,
addresses and controls the CTC, DART, and PIAs, and controls
data buffering.
Thus the 2719 can be divided into six
functional elements: the PIAs, the DART, the CTC, the
interrupt
logic,
the address/control logic, and data
buffering. Each element is separately described below.
4.1
THE PIA'S
Each 6821 PIA provides two parallel data channels,
programmable for input or output on a bit-by-bit basis, with
programmable
two-line
handshaking
for
each channel.
programming options are discussed in Chapter 3. PIA inputs
and outputs are defined in Table 4-1.
For additional
information see a 6821 data sheet.
Each PIA data channel is buffered
by
an
8304
bi-directional driver/receiver, the direction of data flow
being jumper-selectable but pre-configured for Channel A as
input and Channel B as output. The A and B data buffers are
enabled by lows on interface lines 30 and 19 respectively,
or may be permanently enabled by the installation of a
jumper.
Handshaking is determined to consist of one input
(CA1/CB1) and one output (CA2/CB2) by the buffers on the
handshake lines. The on-board reset signal is buffered onto
the parallel interface to provide a reset signal for the
peripheral.
4-2
HARDWARE DESIGN
When used as hardwired, the parallel ports interface
with Centronics-type peripherals. Other types of parallel
interface devices may be interfaced, however. Hardware and
software options are discussed in Sections 2.4 and 3.5
respectively. Interface pinouts are shown in Section A.3.
TABLE 4-1.
SIGNAL
PIA SIGNALS
1
1
FUNCTION
--------- ------------------------------------------------1
1
E
Enable is the PIAls timing signal.
D0-7
The bi-directional data pins connect
to the 2719 1 s internal data bus.
R/W*
R/W* controls the direction of data transfer.
RESET*
This input low clears all registers.
CS0,CSl,
CS2*
The Chip Select inputs must all be active for
the PIA to be selected.
RS0
RSI
These inputs determine which PIA register will
be accessed.
IRQA*
IRQB*
These are the Interrupt
the two PIA channels.
PA0-7
PB0-7
These are the bi-directional data pins for the
the two PIA channels.
CAl
CBl
These handshaking
flags.
CA2
CB2
These pins are used on the 2719 as handshaking
outputs.
4.2
Request
inputs
set
directly
outputs
for
the interrupt
THE DART
A Z-80 DART provides two extensively programmable
asynchronous
serial
ports.
The port interface, as
implemented on the 2719, consists of Transmitter Data and
Receiver Data lines and four handshaking lines.
The
handshaking lines are connected to RS-232-C lines RTS, CTS,
HARDWARE DESIGN
4-3
DTR, and DSR, as indicated in Table 3-2, the Serial
Interface Headers allowing configuration of the interface as
either DCE or DTE, as well as allowing for non-standard
handshaking using lines 19 or 11. Table 4-2 defines the
DART inputs and outputs.
4.3
THE CTC
The Z-80 CTC consists of four separately programmable
counter/timer
circuits.
Each
circuit
includes
a
downcounter, a time constant register, and a prescaler.
In
the
timer
mode, the downcounter is loaded with the
programmed time constant, then decremented with every 16 or
256 pulses of the 4 MHz system clock (depending on the
prescaler selected). In the counter mode, the downcounter
is loaded with the time constant, then decremented with
every pulse of the channel's CLK/TRG input, the prescaler
having no effect. Channels 0-2 have ZC/TO (Zero Count/Time
Out) outputs that pulse high when the downcounters reach
zero; all four channels can be programmed to interrupt when
their downcounters reach zero.
In addition, downcounter
contents can be read from the channel address without
disturbing the counting. Table 4-3 defines the CTC inputs
and outputs.
On the 2719, CTC Channels 0 and 1 are used to supply
the DART Channel A and Channel B clocks respectively, while
Channels 2 and 3 are used to bring the PIA interrupts into
the Z-80 Mode 2 Interrupt Daisy Chain.
Channels 0 and 1
thus may be programmed in either the counter or timer mode,
as described in Section 3.3. The CLK/TRG inputs of Channels
o and 1 are controlled by a 1.8432 MHz crystal. (Note that
jumpers allow each DART channel's transmitter and receiver
clocks to be controlled by RS-232-C line 15 if the DART
channel functions as the DTE device and the user desires the
baud rate to be controlled by the DCE device.)
Whenever either of the PIAl interrupt request outputs
IRQA* and IRQB* goes low, the CLK/TRG input to CTC Channel 2
goes high. The CLK/TRG input to Channel 3 is similarly
controlled by the PIA2 interrupt request outputs. If these
channels are programmed in the counter mode as described in
Section 3.3, the CTC will generate the actual interrupt
request whenever a PIA signals that it wants one.
In
Interrupt Mode 2, this means that an Interrupt vector
pointing to the appropriate PIA service routine can be gated
4-4
HARDWARE DESIGN
TABLE 4-2.
I
I SIGNAL
DART SIGNALS
I FUNCTION
1-------------------------------------------------------I CE*
See Table 4-3 for definitions of these signals.
D0-7
IORQ*
MI*
RD*
B/A*
This input, controlled by A0, determines whether Channel A or Channel B is selected.
C/D*
This input, controlled by AI, determines whether a control or data transfer will occur.
TxDA
TxDB
Serial data at TTL levels is
face lines RxD.
RxDA
RxDB
Serial data at TTL levels is input at these
pins via the TxD interface lines.
CTSA*
CTSB*
The Clear To Send inputs, connected to the RTS
RS-232-C lines, may be programmed as transmitter auto-enable or general-purpose signals.
RTSA*
RTSB*
The Request to Send handshaking outputs are
connected to the CTS RS-232-C lines.
DCDA*
DCDB*
The Data Carrier Detect inputs,
connected to
the DTR RS-232-C lines, may be programmed as
receiver auto-enable or general purpose inputs.
DTRA*
DTRB*
The Data Terminal Ready handshaking outputs
are connected to the DSR RS-232-C lines.
RIA*
RIB*
These pins are not connected on the 2719.
RxCA
TxCA
RxTxCB
The Channel A and
Channel
controlled by CTC Channel IZJ
respectively.
RESET*
A low at this pin resets both DART channels.
CLK
This is the DART's system clock input.
INT*
lEI
lEO
See Section 4.5 for a discussion
interrupt daisy chain signals.
output to inter-
B clocks are
and Channel 1
of these
HARDWARE DESIGN
4-5
TABLE 4-3.
CTC SIGNALS
I
SIGNAL
1
FUNCTION
---------1-----------------------------------------------CE*
I Chip Enable
1
1
RD*
is controlled
decode circuitry.
I The Read input
I data transfer.
determines
by
the
the
address
direction
IORQ*
The I/O Request input enables data transfer.
Ml*
.Both Ml* and IORQ* low indicates an
Acknowledge cycle.
of
Interrupt
CS0,CSl
The Channel Select inputs select one of four
CTC channels. They are controlled by A0-Al.
CLK/TRG
0-3
The Clock/Trigger inputs control downcounter
decrementing in counter mode.
CLK/TRG0-l are
controlled by the crystal or the system clock
divided by two.
CLK/TRG2-3 are controlled by
the PIA IRQ* outputs.
ZC/TO
0-2
The Zero Count/Timeout pins pulse high when
the downcounters reach zero. ZC/T00-l control
: the DART receiver and transmitter clocks.
D0-7
The bi-directional data pins connect directly
to the 2719 internal data bus.
RESET*
Reset low terminates downcounting,
interrupts, and tri-states D0-D7.
CLK
This is the CTC's system clock input.
INT*
lEI
lEO
See Section 4.5 for a discussion
interrupt daisy chain signals.
disables
of
these
4-6
HARDWARE DESIGN
onto the bus during the Interrupt Acknowledge cycle.
IM0 and IMl,2 Headers allow direct assertion of
interrupt requests in Interrupt Modes 0 and 1, in which.
special interrupt capabilities of a Z-80 device are
required.
4.4
The
PIA
the,
not
ADDRESS AND CONTROL LOGIC
During I/O cycles, A7-A0 carry the I/O port address,
selecting one of 256 I/O ports.
Each of the four major
components of the 2719 (the DART, the CTC, and the t~o PIAs)
occupies four ports. The 2719 is designed so that the ports'
of the four devices occupy absolute locations relative to
each other in any l6-port block whose base is a multiple of
16. For an on-board device to be selected, A7-A4 must match
the settings of the Base Address Jumpers, either sINP or
sOUT must be active, and sINTA must be inactive. When these
conditions are met, the internal signal BDSEL (Board Select)
goes active.
BDSEL is the CS0 input to each PIA and is input to the
CTC and DART Select Gates (U10a and b), the outputs of which
control the CTC and DART Chip Enable inputs. When BDSEL is
active, A3 and A2 determine which device is enabled,
control'ling PIA inputs CSI and CS2* and being input to the
CTC and DART Select Gates. Table 4-4 shows the states of A3
and A2 required to enable the various chips.
Table 4-4.
I A3
CHIP SELECTION
A2 I CHIP SELECTED I
\--------1---------------1
I
I
I
1
0
0
1
1
0
1
0
1
1
1
I
I
CTC
DART
PIAl
PIA2
1
I
1
I
Except for the Enable inputs to the PIAs, the rest of
the control logic for the four devices is relatively
straightforward. The R/W* inputs to the PI As are controlled
directly by pWR*, while the RD* (essentially R*/W) inputs to
the DART and CTC are low when pDBIN is active during
non-Interrupt-Acknowledge cycles and high at all other
times. CTC and DART inputs MI* and eLK are controlled
HARDWARE DESIGN
4-7
directly by the sMl and 02 bus lines1 IORQ* is active when
'one of SINTA, sINP, or sOUT is active. The Enable inputs to
the PIAs are required to be active for 166 nanoseconds
during
read - and
write operations,
but need not be
synchronized to 'the system clock.
On the 2719 they are
a.ctive whenever either pWR* or pDBIN is active. With a 4
MHz or, slower system clock,
Enable pulses of adequate
duration are guaranteed.
The 2719 is wired so that the CTC, the DART, and the
PIAs are all reset when either of bus signals POC* or
SLVCLR* goes active. The IEEE standards for the 8-100 bus
specify that SLVCLR* should be asserted whenever RESET* is
asserted.
SLVCLR*, when asserted by RESET*, is removed
sli-ghtly before RESET* to ensure that bus slaves finish the
reset
before' the bus master comes up.
Thus it is
advantageous for a peripheral board to be reset by SLVCLR*
if possible.
However,
in some systems SLVCLR* is not
automatically asserted when RESET* is asserted.
When the
2719 is used in such systems it will be necessary to install
a
jumper between the pads labelled RES to cause the 2719 to
be reset directly by RESET* active.
4.5
INTERRUPT LOGIC
The Z-80 CPU is capable of three modes of maskable
interrupt response, the mode in which the CPU operates at a
given time being determined by software.
The three modes
are
defined
in the CPU section of the Z-80 Family
Programming Reference Manual.
Mode 0 is the 8080 interrupt
mode, which requires that an interrupt controller be part of
the system.
An interrupting device asserts one of the VI*
lines, which is sensed by the Interrupt Controller;
the
Interrupt Controller then asserts INT* and puts out the
programmed instruction (usually a restart or call).
In Mode
1 the interrupting device asserts INT* directly, causing the
CPU to execute a restart at location 0038H.
In Mode 2,
the
special Z-80 mode, the highest-priority interrupting device
puts the vector for its interrupt service routine onto the
bus during the Interrupt Acknowledge cycle.
In support of Mode 2 interrupts, the Z-80 peripherals
have lEI and lEO (Interrupt Enable In and Out) pins which
allow them to be linked in a hardware-prioritizing interrupt
daisy chain. The highest-priority device's lEO is connected
to the next-highest-priority device's lEI.
If a device's
lEI input is high, it may generate an interrupt request by
forcing INT* low.
A device's lEO output is forced low if
4-8
HARDWARE DESIGN
either its lEI pin or its INT* pin is low.
Thus a device
generating an interrupt request disables the interrupt
request logic of all lower-priority devices in the daisy
chain. Higher-priority devices are unaffected, however, and
may interrupt at any time, providing that CPU interrupts are
enabled.
If more than four devices are connected in a simple
daisy chain, a low-priority interrupt request may not be
disqualified by a higher-priority interrupt request soon
enough to prevent the low-priority device from thinking its
interrupt is being acknowledged and outputting its interrupt
vector. The 2719 supports an extended Z-80 Mode 2 Interrupt
Daisy Chain with a look-ahead scheme implemented on all CCS
System 300/400 peripheral boards. The VI* bus lines are
used to prioritize the boards participating in the chain.
Each board's look-ahead logic guarantees that an interrupt
request
by an on-board device or by a device on a
higher-priority board will be passed on to lower-priority
boards rapidly enough to be recognized before the interrupt
is acknowledged, preventing two devices from putting their
interrupt vectors on the bus at the same time.
On the 2719, if the DART requests an interrupt, the CTC
is prevented from interrupting by the normal chip-to-chip
lEI-lEO daisy chain.
An interrupt by a higher-priority
board does not ripple through the DART, however; the
interrupt request logic of both the DART and the CTC is
immediately disabled when the 2719 interrupt logic senses
any higher-priority VI* line going low.
Whenever
an
on-board device interrupts or the 2719 senses a higherpriority
VI*
line
low,
the
2719
forces
its
priority-assertion VI* line low to immediately disable
lower-priority boards. The particular VI* lines the 2719
senses and the VI* line it asserts are determined by the
configuration of the 1M2 Header (see Section 2.2.3).
In some environments it will be desirable for the 2719
to generate Mode 0 or Mode 1 interrupts. The Mode 0 Header
allows the user to select which VI* line each on-board
device will use to communicate its interrupt request to the
Interrupt Controller.
The Mode 1,2 Header allows each
device to directly assert INT*. Configuration instructions
for the interrupt headers are given in Section 2.2.
In some systems, including those using a CCS 2810 CPU,
a wait may be required during Interrupt Acknowledge cycles
to ensure that the eTC has time to get its interrupt vector
onto the bus. For this reason, jumper-enabled circuitry has
been provided to force bus line RDY low while pSYNC is
active during Interrupt Acknowledge cycles in which the 2719
has the highest-priority interrupt pending.
HARDWARE DESIGN
4.6
4-9
DATA BUFFERING AND LATCHING
All system bus inputs and outputs are fully buffered,
as are the serial and parallel port interface lines.
Hysteresis drivers and receivers are used for system bus
interfacing,
ensuring minimum noise on the bus. No load of
more than one Low-Power Schottky TTL level is placed on any
system
bus
input.
INT* and VI* line drivers are
open-collector. Serial port interface drivers and receivers
meet EIA RS-232-C specifications.
Except for the parallel port buffers, discussed in
Section 4.1, and the Data In Buffer, all buffers are
permanently enabled. The Data In Buffer and Data Out Latch
(described below) are alternately tri-stated except during
Interrupt Acknowledge cycles. The Data Out Latch is always
disabled during Interrupt Acknowledge cycles. The Data In .
Buffer is enabled during Interrupt Acknowledge cycles if the
board is configured for Mode 2 interrupts and the 2719 has
the highest-priority request pending: this is necessary to
allow the Interrupt Vector onto the bus.
However,
in
Interrupt Mode 0 or 1 it is necessary to keep the Interrupt
vector off the bus. If the IMS Jumper is wired for the 0/1
position,
the Data In Buffer is disabled during all
Interrupt Acknowledge cycles.
In
all
non-InterruptAcknowledge cycles,
the Data Out Latch is disabled and the
Data In Buffer enabled for the duration of pDBIN active when
the board is addressed during an I/O Read cycle: otherwise
the Data In Buffer is tri-stated and the Data Out Latch is
enabled.
The Data Out Latch has been included to defeat the
multiplexing of status and data on the DO lines by the CCS
2810 CPU, thus allowing the 2719 tol be used in the CCS
System 2210.
The CTC cannot handle the 2810's multiplexed
status and data. When bus signal sOUT goes inactive, the
data is latched (provided that the latching signal is not
jumper-disabled) until one of three things occurs: 1) sINTA
goes active: 2) an I/O Read cycle occurs, enabling the Data
In Buffer: or 3) another I/O Write cycle occurs, with sOUT
going active, gating new data onto the bus. Because the
CTC's RD* input is always low unless pDBIN is active and
sINTA is inactive, the CTC may read valid data for as long
as it is enabled during an I/O Write cycle.
When a device has interrupted, it monitors the data bus
during all instruction fetches,
looking for the
RETI
instruction which signals that servicing of the interrupt
has been completed and that lower-priority interrupts may
To ensure proper monitoring of the CPU
now be asserted.
instruction fetches by the 2719, the CPU must internally
4-10
HARDWARE DESIGN
connect the DI and DO buses. This is necessary because,
while the RETI instruction is input to the CPU on the Dr
lines,
the 2719 looks for RETI on the DO lines. The CCS
2820 System Processor Board meets this requirement as long
as no other board asserts DODSB during instruction fetch
cycles.
APPENDIX A
TECHNICAL INFORlvIATION
A-2
TECHNICAL INFORMATION
A.l
USER-REPLACEABLE PARTS
QTY
REF
DESCRIPTION
CCS
Z-80A DART
Z-80A CTC
6821 PIA
74LS136 quad EX-OR
74LS13 dual 4-in NAND
74LS240 oct buffers, inv
74LS08 quad 2-in AND
74LS244 octal buffers
74LS02 quad 2-in NOR
74LS00 quad 2-in NAND
8304B transceiver
7407 hex buffer, OC
74LS10 tri 3-in NAND
74LSl1 tri 3-in AND
75150 line driver
75154 line receiver
79L12 -12V regulator
78L12 +12V regulator
74LS367A hex drivers,
74LS373 octal D latches
LM323K +5 V regulator
Oscillator, 1.8432 MHz
48200119-01
48200084-01
48200076-01
48200021-01
48200120-01
48200034-01
48200006-01
48200035-01
48200002-01
48200001-01
48200068-01
48200051-01
48200008-01
48200125-01
48200055-01
48200056-01
48200115-01
48200127-01
48200039-01
48200041-01
48200107-01
48200118-01
.1uf Mono, 50VDC, 20%
4.7uf Tant, 35VDC, 20%
15900001-01
15500003-01
2.7K ohm, 1/4 Watt, 5%
SIP Network, 2.7K x 7
47000023-01
47400002-01
PART if:
Integrated Circuits
1
1
2
3
1
2
1
3
1
1
4
1
1
1
3
2
1
1
2
1
1
1
U3
U6
U16,17
U24,28,29
U23
U26,30
U22
U27,31,33
U21
U20
U7,9,10,12
U19
U28
U25
U5,14,15
U4,13
Ul
U2
U8,11
U32
U18
Yl
Capacitors
13
6
Cl,7-12,14-19
C2-6,13
Resistors
2
3
Rl,2
Zl-3
A-3
TECHNICAL INFORMATION
QTY
REF
DESCRIPTION
CCS
PART #
Socket, Ie, 16 pin
Socket, IC, 20 pin
Socket, IC, 28 pin
Socket, IC, 40 pin
Header, 2 x 13 rt angle
Header, 2 x 17 rt angle
Header, 1 x 4
Header, 1 x 3
Header, 2 x 4
Jumper Plug
Header, DIP, 16 pin
Header Cover, 16 pin
Heatsink, TO-3
Heatsink Insulator
Screw, 6-32 x 3/8
Nut, 6-32 KEP
Board extractor
Roll pin
Cable, 26 pin, 24" DB25
Cable, 34 pin, 2411
21400015-01
21400017-01
21400018-01
21400020-01
21000017-01
21000018-01
21000009-01
21000007-01
21000023-01
21300021-01
21600001-01
14100001-01
76000003-01
76000004-01
28000006-01
28100004-01
74000001-01
28300001-01
60900005-01
60900009-01
Miscellaneous
6
4
1
3
2
2
1
1
1
5
3
3
1
1
2
2
2
2
2
2
A-4
A.2
TECHNICAL INFORMATION
SERIAL CONNECTOR PINOUTS
PGND
TxD
RxD
CTS
RTS
DSR
SGND
AA
BA
BB
CB
CA
CC
AB
NDEF
A.3
1
3
5
7
9
11
13
15
17
19
21
23
25
0
0
0
0
0
0
0
0
0
0
0
0
0
2
4
6
0 8
0 10
0 12
0 14
0 16
o 18
o 20
o 22
0 24
0 26
0
0
0
CB
TSET (DCE)
SCA
CD
SRTS
DTR
PARALLEL CONNECTOR PINOUTS
BSTB
BD0
BDI
BD2
BD3
BD4
BD5
BD6
BD7
BACK
AD0
ADI
AD2
AD3
ASTB
AACK
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
BEN
SIG GND
SIG GND
SIG GND
SIG GND
SIG GND
SIG GND
SIG GND
SIG GND
SIG GND
SIG GND
AEN
RESET
AD4
ADS
AD6
AD7
TECHNICAL INFORMATION
A.4
A-5
RS-232-C CONNECTOR PINOUTS
FRONT VIEW
PROTECTIVE GROUND
TRANSMIT DATA
RECEIVE
DATA
REQUEST TO SEND
CLEAR TO SEND
DATA SET READY
SIGNAL GROUND
UNASSIGNED
@
AA
-BA
2
@
BB
3
@
CA
4
@
CB
5
@
CC
6
@
AB
7
@
8
@
9
@
10
@
11
@
12
@)
13
@)
@
14
@
15
@
16
@
17
@
18
@
19
@
20
@
21
@
22
@
23
@)
24
@)
25
DB-25S (FEMALE)
-
DB
--
TRANSMIT SIG ElE ClK (DCE)
SCA
SEC REQUEST TO SEND
CD
DATA TERMINAL READY
A-6
A.5
TECHNICAL INFORMATION
BUS CONNECTOR PINOUTS
+8V
+16V
ViO
Vi1
Vi2
VI3
Vi4
ViS
ViS
Vi7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
C
0
M
P
0
N
CP2
E
N
T
S
I
0
A5
A4
A3
E
001
000
004
005
006
sM1
sOUT
slNP
GNO
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
31
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TOP VIEW
+8V
-16V
SLAVE CLR
C
iiDv'.
iNT
RESET
pSYNC
pWR
pOBIN
AO
A1
A2
A6
A7
002
003
007
slNTA
~
GNO
I
R
C
U
I
T
S
I
0
E
TECHNICAL INFORMATION
A.6
SCHEMATIC/LOGIC DIAGRAM
A-7
ZBOA-CTC
000 36~~~~f'2~--------~________________________________________________________________~~2~5~
00' 35~
002 Be _~
003 B9~
~
L-6
c
iJ2.------Jz
c
!lI
'5
'6
'9
id
~
26 0 ,
27 02
2B03
~~: ~:~ ~ :t=::j ~ :
D06 40
007 90
~
t
'5
17
~
~ D
,
~:
5
Q 2
3 D6
4 07
II
19
L'--+H-f--I-I-+_+------"B'<;(ciU20r,;:;-
~:~ ::~
~~g~~
.---
' 11'01\5 C
6 -
Vi3
ViII
171!1
Vl1!
10
VT'1
"
? ?T~
3;'4 0
:--_
2
I
.-.-.--.-~;~7~..--L:~2~ ~
2
5 i
\ fd 1.1/
~~7
U20
45
""'~"-A-9;"3;j~7:~~:r~l~~2==t1=j=====1:t-l--_---I--+---_--=--_-+-+-4_H-f-+-1I_+-f___J
;
10 28
.--fo
~7
~
•
rrr.r-~5
DAISY 22
OSBL : fa r2 f3 ; 4 ,
I
.'6-
0.1 , MODE
r
2
U22
'21
~2
41u23
14
5
6
oJnL-_-.-~'2 74LS13
,2
3
~
~~ ~~
~~~~ 12.
CTSA
RTSA
TxDA
RxOA
RIA
~-++-l-----'3!!l.je D4
~+_+4-+---"I3 05
+-+_+_-H~+_-,,37'-lD6
3
5m
+--+-++_~+-~-H_t_+_+----4-++--""I34 B/A
+--+-++-+_+_+_------l-++_~+-I-- - . ~ C/O
,
10.~'
,~
6
CB (!!o)
CA (.)
BB (3)
BA (2)
SCA (19)
CLEAR TO SEND
REQUEST TO· SEND
RECEIvE OA1Jl.
TRANSMIT O,(lA
SECONDARy R'OUEST
D~I-- 13
AB (7)
SIGNAL GROUND
7~1-- 21 NOEF(~)
U3
PGNO
-
4~7_ _ _ _+_-
10
.'2
05
75
_~
:
pDBIN
~~4---~
~'3
1"'4'-------4'4;lU25
>'!'16'-------"-t;:;74LS;-;:"
4
18
3.
r
2'''.JCd'4--+-'
~-++_+---'=:'-"-l9 ~~
:~~
+-+-+-+_I-+---"~"'1~ ~:
::~
L--f--I-H_+~_+~3"51J;
H_+---+-r+-+-~-++--""-I36
~~-+---+_I-+~_t_+_I___'~"'I~~~
:
44
r
",39"--_+---,,,!'5k-,--,1'92r§B:'>"~''----+--_ _ 29
~:l f9:'.I---i---!'l'3(i~~ '4 4~ 5
31
3---B1 2
-'
~'3
z,
19
If":'---_~-__._-74t--LS--'3-6-l~-,
"
6
_~
U29
U29
U29
U29
2,
~ A7
-----.!Z f"-.....:L.J
~ 82_~
~ --f4'
A3
A2
'2'3
74LS'36
U30
<>'
<>'
A6
A5
A4
'4
~a40
:~ ~~
---'~=iS ~SO
c4f ..
CSo
4.7UL...---,-_ _
4._71i___
12
U1
----+--.
GNO 50 ....r - - -......- -.....
GNO 100
'--+----------------'2~3 CS2
U17
68B21
OUTI----C-13.--o----1~OSV
IN U'1:,UrI--o---t------- o'2V
52 4---_..__--\1
29 D4
28 OS
2' 13
L~~~~_t~t~i~;~~~~~~~~~~~~-=: =~~
ALTERNATE BAUD RATE CLOCK
[-----,
:
~'6VOC
U28
,
L-----'2"l1~:~,..~--------------+--+_-f-------------il'!.j24 CSI
19
7
9
o--f
.....-t-~o___f_____c~-- 2
~,
7
n
I
1
1
1
0-+0~4
:
YI
.;
1.6432MHz
I
I
I
I
L _ _ _ _ _ -I
U6- 22.23
-T~'---------
PA61"'6_~~"-17
PA5 f2-7_ _
::~
~:~
.'2
~ ~,
1"--_ _+__-4'4
3
PA21"---I----"I
li:
=:~ ~~===~~=~~
~.oS
,J..---'2c----,
2 4---
~ ~~
L -_ _ _ _ _ _
7BL12
016VOC
~
'----------'21':!-iR/W
LM323
U1B
+8VDC
j
~ 01
'-+-+-+-I_+------~3""leim:lA
1"-9,-_ _ _ _ _ _ _ _-'
CoN
~6
74LS'0 U28
5 3 4
lb
,
5:::r--
;
(0 9
S.
<>'
---ll DO
.....
74LS08
=
-6VOC
'~~..::UJ22/~6'----- -----l--..---+---+-f-j-++-+--+~
~~
3'4---"1
6
8' 4 - - _"l
PB6~
H+~f--+_+H_+4_H-f-+-lf--+------<'i'i,-,,34,,-----~--~- -
__ _+--_ _
3
..!.- <>'
A7 83
t::(f3:::,:.L-+---:
~
'J4LS11
'8
4------.!
IAOO
Z
r',,,,,AO,,,,'--o-.-4----f-2.,ili'\r-05
PBS 1~
6
•
14,
13
5
P84 I""L-_~~
11
P83 13
43
1-";6,+-+_-- 9
PB2 1-"'2'---~~_".f
PB( ~
2
1"'6,+-+_-1m' PBD
'.12---- 3
,,1
' ':L-_______---1_+-+_-l---------+---:;t.'~t=iU;;_;;2~-
U26
----!II!
51'011
1lJ,9iL+_ _ _ 21
66821
Do""!------------+----+---------'
s~~: :! !---=---';
lAD3
lA02
ffi7~17'--~~~8~"f--~·S
U16
~O
~~
I-"!-'-+-f--_--_-_-_-- ~~
fl':~4--- ~
'--::1';::IR
lBENQ
r-_+_~-++_+_+_+__~~_+_+4-+--+_+---'2~3~
96:
~
;
3
CBI ,..
5~~:
(7)
~'2-+-_ __
lA07
f ! " 3 4 - - - 32
~'4~_ _ _ 30 lADS
PAO fL---f----'-l'
::
RSO
74LS02
41:::.- '6
H-++_--~~_+_+_I-++_+---'3""j5 RSI
H-4_----+---+~t:7~I2I--4_I-I++-1_++------.--I--l-+f_j-+++-~~ :/W
19
1
-+_+------.!',2!..i1,~
.lJ,2~~,.J3
~69
~ ~ at:>'"
PA71"-9-~-6"l
PA6
7 \\3
PA5 7
6,
+--+-t-+_~_+_+_2""_16 07
~1!---------------+---+----------H-+-------+-+-~~-+-~1-+4
76_~
AB
lAEN I;) o---tl,9,--------
,----
~ DO
----R 0'
f--~f-----2! D2
~22 JL- f-- ~
)26'-----_+--+-----_++-l-~---'~~.!!L.---+-I--+_-I----f
1l"2,---<:,R,EcS>--4---25L..
t:l
01
~
SCA(9)
NOEF(11)
'2
=J_
....---;.-I"-8""Z11\r-!5
c
SA (2)
Z80A-OART
74LS08
8
'2 ~LRQ 9
>---11 U3'bLetR---+-'-I__+_----~~'3+'-2-+_ _- '
PSYN~ ~: 4 -_ _,' -!j~ [j fL~___,;=-+_----.:I7~-----+_-_+----..J
REm
SLY CLR 54
6
~ 99 _~
(3)
dL--21
12
a~
2.~~ ~~~4LS74PL..::~
r-
(4)
BB
~'2
11- U28 fll,'~'---+--I-~
I"
I
CA
012--oIL-- 3
9
r"
U22~
012---
012---- 14
20
~
~
~
DB CIS)
AA (I)
CD (20)
CC (6)
CB(5)
'---
Bm
~--~--~~~4-~+-~+4~+-I-tl ~~
+-+------t-_+_-H-++_+----4-++__t__+_~_+...+---+---+ ~~
74LS10
-0:::-.
SGNO
SER B CLK
+-----I-I1---I-+f---<4++-+-1---+--4++-1-+++-++--1-+++-1-+++--£l~ :~~ RXTXCB~ ~T
3
7
S
3
2BSTB
2BACK
2BEN
2B07
2B06
280S
2B03
2802
2801
2BOO
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ r34"----_ _---+_ _+~---.!!j6r,;(,z..f---=--- 26 2RESET
V
7 Z1 -S
2BOIR
F
MODEL 2719
©CCS 1981
2 PARALLEL / 2 SERIAL
REV B
TRANSMISSION SIGNAL ELEMENT TIMING
(1)
~~ 1L- ~
::...."
3
!Lx
<:il. ,~- 12
U21)o!-'
."
DB (15)
I. oI§... - - I AA
PROTECTIVE LROUNO
~'.'\ -,~ - ~~ ~~ :~) ~:~~ ~~~M:;O;EAD'f
'"
V" -,,- ~~ - 9
1L- ~ 7 3~ ~.y:L - -
+-+_+_-H-++_+--__+_+_~-+----H_+__"_'_12' rn
74LS02
t
1-++~_+++_-!!.j4 07 W/ROYA!lL~
U25
~'3
21--..
'5
~ 19
02
2 03
-.:.:: 819lJl!-19f-J>------I-+-I----I-++-+l----+++-HI-+--i
0
40
~-~
'5 '"
o-'!l.'
+/2-
~4
I T
2 1
4 ' 3 lA
4-'19'3 " l
j
5
'2 IB
-.:.:: lcuglf!1'''~_+-+---- __-+_+--I--6
,;r.2A'------_ _4-.+--I"!.6'9
I
9_
.---
SER ACLK
.-._ _ __t_--o 'NT
U20
TO
SEN~
APPENDIX B
SAMPLE DRIVERS
Drivers for the 2719 parallel and serial ports will be
included with future releases of CP/M with the CCS System 2210
and OASIS with the CCS Systems 300 and 400.
If your operating
system does not include drivers for the 2719, you will need to
add them.
The sample drivers that follow may be used as they
are or modified as desired. For instructions on adding the
drivers to your operating systems, see the relevant operating
system documentation. For CP/M on the System 300 or 400, see
the System 300 or System 400 CP/M Supplementary Manual;
for
OASIS,
see Phase One1s Macro Assembler Language Reference
Manual.
Please note that the ORG addresses used in the sample
driver listings were chosen for assembly purposes and are not
the addresses at which your drivers will reside.
SAMPLE DRIVERS
B-2
CP/M DRIVER
B.l
0100
ORG
100H
SAMPLE DRIVER CODE FOR THE CCS MODEL 2719
2 SERIAL/ 2 PARALLEL INPUT/OUTPUT INTERFACE BOARD
The input/output drivers shown below work in a pol led
environment. They conform to the CP/M interface
specifications as documented in the CP/M Alteration
guide, and are intended for CP/M or MP/M applications.
Port Address Assignments
0050
=
BASE19: EQU
50H
Base address of the 2719 board
0050 =
0051 =
0052 =
0053 =
CTCO:
CTC1:
CTC2:
CTC3:
EQU
EQU
EQU
EQU
BASE19
CTCO+l
CTCO+2
CTCO+3
CTC
CTC
CTC
CTC
0054
0055
0055
0056
0057
0057 =
SIOAD:
SIOAC:
SIOAS:
SlooD:
SIOBC:
SlOBS:
EQU
EQU
EQU
EQU
EQU
EQU
BASEl 9+4
SIOAD+l i
SIOAC
BASEl9+6
SIOBD+l
SIOBC
i SIO Channel A Data Register
SIO Channel A Command Register
SIO Channel A Status Register
i SIO Channel B Data Register
SIO Channel B Command Register
SIO Channel B Status Register
PIA1AD: EQU
PIA1ADD: EQU
PIA1BD: EQU
PIA1BDD: EQU
PIA1AC: EQU
PIA1AS: EQU
PIA1BC: EQU
PIA1BS: EQU
BASEl 9+8
PIA1AD ;
BASE 19+9
PIA1BD ;
PIA1AD+2
PIA1AC ;
PIA1BD+2
PIA1BC i
j PIAl Channel A Data Register
PIAl Channel A Data Direction Register
j PIAl Channel B Data Register
PIAl Channel B Data. Direction Register
j PIAl Channel A COMMAND Register
PIAl Channel A STATUS Register
i PIAl Channel B Command Register
PIAl Channel B Status Register
005C =
005C =
0050 =
0050
005E
005E
005F
005F
PIA2AD: EQU
PIA2ADD: EQU
PIA2BD: EQU
PIA2BDD: EQU
PIA2AC: EQU
PIA2AS: EQU
PIA2BC: EQU
PIA2BS: EQU
BASE19+12
PIA2AD j
BASE19+13
PIA2BD j
PIA2AD+2
PIA2AC ;
PIA2BD+2
PIA2BC i
; PIA2 Channel A Data Register
PIA2 Channel A Data Direction Register
i PIA2 Channel B Data Register
PIA2 Channel B Data Direction Register
; PIA2 Channel A Command Register
PIA2 Channel A Status Register
; PIA2 Channel B Command Register
PIA2 Channel B Status Register
002C
PIAMOD: EQU
001011008
0058
0058
0059
0059
005A
005A
005B
005B
=
=
=
=
=
=
=
=
j
base address
#1
#2
#3
PIA operating mode byte
8-3
SAMPLE DRIVERS
OOFF
DATOUT: EQU
11111111B
; PIA Data Direction byte for output
The fol lowing equates establ ish the baud rates for the serial
channels. Three sets of values are identified, and must
be set to match the specific board configuration.
The normal configuration is for 4 mhz operation with a
crystal oscillator. The other two are for deriving the
baud rate clock from the system clock divided by 2 by
U34 (74LS74). See the Manual text for further detail.
BAUD
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
0047
OOOC
CTCMOD: EQU
CTCDIV: EQU
CTCMOO
07H
07H
07H
07H
07H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
12
XTAL
208
142
116
104
52
192
96
64
58
48
32
24
16
12
6
3
2
1
CTCDIV
2mhz
104
71
58
52
26
104
52
35
31
26
17
13
9
4mhz
208
142
116
104
52
208
104
69
63
52
35
26
17
13
CTC mode for 9600 baud
CTC divisor for 9600 baud (XTAL)
; for the SIO command byte definitions, see the text.
;----------------------------------------------------------------------The fol lowing code segment initializes the 510 channels for
asynchronous operation with auto-enables.
It must be placed in the cold boot code path.
SAMPLE DRIVERS
8-4
0100
0103
0105
0106
0108
010A
010B
010C
OlOF
0111
0113
0115
0117
0119
211BOl
0606
7E
D355
D357
23
05
C20501
3E47
D350
D351
3EOC
D350
D351
SIOINIT:
SIOll :
LXI
MVI
MeV
OUT
OUT
INX
DCR
JNZ
MVI
OUT
OUT
MVI
OUT
OUT
H,SIOCMD
B,SIOLGTH
A,M
SIOAC
SIOBC
H
B
SIOll
A,CTCMOD
CTCO
CTCl
A,CTCDIV
CTCO
CTCl
; point to the SIO Init Data String
; get the String length
get the next init command
output to SIO Channel A
and to Channel B
advance string pointer
check the loop control
jump if more to do
; now, set the baud rate generator
Channel A
Channel B
i baud rate divisor
Channel A
Channel B
The SIO Initialization Data String should be put in
the data area of the BIOS or XIOS.
011B
011C
011D
011E
011F
0120
0006
04
46
05
EA
03
El
=
SIOCMD: I
DB
DB
DB
DB
DB
DB
SIOLGTH: EQU
4
;
01000110B
5
i
11101010B
3
11100001B
$-SIOCMD
Access Write Register 4
i x16 clock, 1 stop bit, no parity
Access Write Register 5
i DTR, Tx 8 bits, Tx Enable, RTS
Access Write Register 3
; Rx 8 bits, Auto enables, Rx enable
; Init Command string length
~,r
The fol lowing code segment initializes both PIAs for
Centronics-compatable printer operation
-j
It also must be put into the cold boot code.
PIAINIT:
0121
0122
0124
0126
0128
012A
012C
012E
AF
D35A
D35B
D35E
D35F
D358
D35C
3EFF
XRA
OUT
OUT
OUT
OUT
OUT
OUT
MVI
A
PIA lAC
PIA1BC
PIA2AC
PIA2BC
PIA1AD
PIA2AD
A,DATOUT
get a zero into (A)
al lows access to the data direction register
sets the A side for input
direction control byte for output
8-5
SAMPLE DRIVERS
0130
0132
0134
0136
0138
013A
013C
013E
013F
0141
0359
0350
3E2C
035A
035B
035E
035F
AF
0359
0350
OUT
OUT
MVI
OUT
OUT
OUT
OUT
XRA
I rJ
.@ijif
IN
9ijo'f
PIA1BO
PIA2BO
A,PIAMOO
PIA lAC
PIA1BC
PIA2AC
PIA2BC
A
PIA1BO
PIA2BO
sets the B side for output
PIA mode control byte
sets the PIA operating mode
get a nul I character
output it to prime the handshake lines
Serial Driver Routines
SIOAST:
0143
0145
0147
0148
014A
OB55
E601
C8
F6FF
C9
014B
014E
0151
0153
0155
C04301
C24BOl
OB54
E67F
C9
0156
0158
015A
015B
015D
015F
0160
0162
OB55
E608
C8
OB55
E604
C8
F6FF
C9
0163
0166
0169
016A
016C
C05601
CA6301
79
0354
C9
IN
ANI
RZ
ORI
RET
; SIO Channel A input status routine
SIOAC
; read the SIO status byte
00000001B ; see if Rx Character avai lable
done if not
OFFH
; else, flag the ready condition
SIOAIN:
CALL
JNZ
IN
ANI
RET
SIOAOST:
IN
ANI
RZ
IN
ANI
RZ
ORI
RET
SIOAST
SIOAIN
SIOAO
7FH
;
SIOAC
;
00001000B
;
SIOAC
;
000001008
OFFH
SIOAOUT:
CALL
JZ
MaV
OUT
RET
SIOBST:
SIOAOST
SIOAOUT
A,e
SIOAO
SIO Channel A Input Routine
check the port status
try again if not ready
get the data byte
strip off bit 7
SIO Channel A Output Status Routine
read the SIO status byte
; check the DCO bit (handshake)
return if not ready
reget the SIO status byte
; see if Tx Buffer is empty
no, stili busy
else, flag the ready condition
SIO Channel A output routine
see if port ready for output
try again if not
else, get the data for output
output it
SIO Channel B input status routine
8-6
SAMPLE DRIVERS
0160
016F
0171
0172
0174
0057
E601
C8
F6FF
C9
0175
0178
017B
0170
017F
C06001
C27501
OB56
E67F
C9
0180
0182
0184
0185
0187
0189
018A
018C
OB57
E608
C8
OB57
E604
C8
F6FF
C9
0180
0190
0193
0194
0196
C08001
CA8001
79
0356
C9
IN
ANI
RZ
ORI
SIOBC
read the SIO status byte
00000001B ; see if Rx Character avai lable
done if not
OFFH
else, flag the ready condition
RET
SIOBIN:
CALL
JNZ
IN
ANI
RET
SIOBOST:
IN
ANI
RZ
IN
ANI
RZ
ORI
RET
SI08ST
SIOBIN
SIOOO
7FH
SIO Channel B Output Status Routine
SIOBC
read the SIO status byte
00001000B ; check the OCO bit (handshake)
return if not ready
SIOBC
reget the SIO status byte
00000100B ; see if Tx Buffer is empty
no, still busy
OFFH
else, flag the ready condition
SIOBOUT:
CALL
JZ
MOV
OUT
RET
SIO Channel B Input Routine
check the port status
try again if not ready
get the data byte
str i p off bit 7
SIOBOST
SIOBOUT
A,C
SIOBO
SIO Channel B output routine
see if port ready for output
try again if not
else, get the data for output
output it
Centronics Printer Output Oriver.s
PIA1ST:
0197 OB58
0199 E617
IN
ANI
0198
0190
01AO
01Al
01A2
01A4
01A6
01A7
XRI
EE14
CAA201
AF
C9
OB5B
E680
C8
F6FF
JZ
XRA
RET
PIAl ST1: IN
ANI
RZ
ORI
PIAl Status Routine
check for Printer status
PIA1AO
00010111B
isolate the bits of interest
Fault (bit 4)
Select (bit 2)
Paper Empty (bit 1)
Busy (bit 0)
00010100B
invert the -Fault and Select signals
PIA1STl
al I must be zero for ready condition
else, show busy
A
read the B Side Status Register
PIA1BC
10000000B i check if last byte was accepted
busy if zero
OFFH
show the ready condition
B-7
SAMPLE DRIVERS
01A9 C9
RET
PIA10UT:
- 01M
01AD
01BO
01B2
01B3
0185
CD9701
CAAAOl
0859
79
0359
C9
CALL
JZ
IN
MOV
OUT
RET
PIA1ST
PIAl OUT
PIA1BD
A,C
PIA1BD
Printer Output entry point
See if ready for data out
try again if not
Reset the data accepted bit
get the data for output
output it
PIA2ST:
; PIA2 Status Routine
PIA2AD ; check for Printer status
00010111B
isolate the bits of interest
Fault (bit 4)
Select (bit 2)
Paper Empty (bit 1)
Busy (bit 0)
OlBA EE14
XRI
00010100B
invert the -Fault and Select signals
-o-lse-cAe10l---------~t----;tz---~:P.:>~$:IA2ST_t -i---a '-+--musToe -Zercfror--rEfaeW-'-condfTTOnOlBF AF
XRA
else, show busy
A
OlCO C9
RET
OlCl DB5F
PIA2STl : IN
PIA2BC
read the B Side Status Register
01C3 E680
ANI
10000000B i check if last byte was accepted
01C5 C8
RZ
busy if zero
01C6 F6FF
ORI
show the ready condition
OFFH
01C8 C9
RET
0186 DB5C
01B8 E617
IN
ANI
PIA20UT:
~01C9
OlCC
OlCF
OlDl
01D2
0104
CDB601
CAC901
OB5D
79
0350
C9
CALL
JZ
IN
MOV
OUT
RET
PIA2ST
PIA20UT
PIA2BO
A,C
PIA2BD
Printer Output entry point
See if ready for data out
try again if not
Reset the data accepted bit
get the data for output
output it
B-8
B.2
SAMPLE DRIVERS
OASIS DRIVER
DEV25: CCS 2719 SIO Port A Driver
Addr Obj-Code
0000
0050
0000 C30FOO
0003 C37000
0006 C39200
0009 C3B400
OOOC C35901
OOOF
OOOF
0010
0013
0014
0015
0017
0019
001B
001E
0020
0022
0024
0026
0028
002A
002C
002E
002E
002F
0030
0032
0033
F3
3A7A01
B7
F5
DB55
CB57
2852
FD7E1C
CB47
2031
CB5F
2039
CB4F
2021
CB57
283B
Fl
F5
2810
Fl
C07900
Line *** Source Statement ***
copy
2
110
CCSSIOA
112+LlNE:
EQU
113+PORTSI04AD:
114+
115+
116+
JP
117+
118+
JP
119+
120+
JP
121+
122+
JP
123+
124+
JP
125+
126+
127+ST:
128+;
129+; get SIO status
130+;
131+
01
132+
LD
133+
OR
134+
PUSH
135+
IN
136+
BIT
137+
JR
138+
LD
139+
BIT
140+
JR
141+
BIT
142+
JR
143+
BIT
144+
JR
145+
BIT
146+
JR
147+.ENAB3:
148+
POP
149+
PUSH
150+
JR
151+
POP
152+
CALL
CCS
PORT=SI04AO,CTC=CTC20,VECT=SI04AV*2
80
i line length
REL
; relocatable
ST
get status
IN
get byte
OUT
put byte
INIT
initial ize
UNIN
un-initialize
A,(BUFI)
A
AF
A, CDA+l )
2,A
Z, .NOTRDY
A,(IY+28)
O,A
NZ,.ENAB1
3,A
NZ,.ENAB4
l,A
NZ,.ENAB2
2,A
Z,.ROY
AF
AF
Z,.TEST3
AF
INl
no ints
get count
test if any
save
get port status
test txrdy
brif not ready
get enab type
dtr
cts
brif dc1/dc3
test
brif not etx/ack
get in flags
re-save
brif no char rdy
else, throwaway
get char
8-9
SAMPLE DRIVERS
DEV25: CCS 2719 510 Port A Driver
Addr Obj-Code
0036
0038
003A
003C
0040
0042
0042
0045
0047
0049
004B
0048
004E
004F
0051
0053
0053
0055
0057
0059
005B
0050
005F
005F
0061
0063
0065
0067
0069
0069
006A
006B
006C
0060
0060
006E
006F
0070
E67F
FE06
2003
F0361000
18CO
F07E10
FE80
2020
1822
F07E10
87
201C
1816
3E10
0355
OB55
CB5F
2810
180A
3E10
0355
0855
CB6F
2804
F1
37
FB
C9
F1
FB
C9
Line
***
Source Statement
***
153+
AND
7FH
154+
CP
ACK
155+
JR
NZ~ST
156+
LO
( IY+29) ~ 0
157+
JR
ST
158+.TEST3:
159+
LO
A~ (IY+29)
160+
CP
128
161+
JR
NZ~.ROY
162+
JR
• NOTROY
163+.ENAB2:
164+
LO
A~(IY+29)
165+
OR
A
166+
JR
NZ~.NOTROY
167+
JR
.ROY
168+.ENAB1 :
169+
LO
A~10H
170+
OUT
208+
LO
B,O
209+
INC
HL
210+
LO
A, (HL>
211+
JR
Z, .MT
212+
LO
O,H
213+
LO
E,L
214+
INC
HL
215+
LOIR
216+.MT:
217+
EI
218+
POP
HL
219+
POP
OE
220+
POP
BC
221+
RET
222+
223+
224+0UT:
225+;
226+; put byte to device
227+;
228+
CALL
ST
229+
JR
NC,OUT
230+
01
231+
2, (IY+28)
BIT
232+
JR
Z,OUT2
233+
( IY+29)
INC
234+
LO
A,(IY+29)
235+
CP
128
236+
JR
NZ,OUT2
237+
LO
A,ETX
238+
EI
get status
yes, ready
else, wait for int
loop
ints off
save regs
point buffer
decr length
get length
zero msb
point first char
load it
brif buffer now empty
copy register
compress the buffer
turn on ints
restore regs
return
get status
loop ti II ready
ints off
enab 3
no
bump count
load count
fu II now?
no
else, send etx
turn on ints
8-11
SAMPLE DRIVERS
DEV25: CCS 27i9 SIO Port A Driver
Addr Obj-Code
OOAB D354
OOAD 18E3
OOPF
OOPF 79
0080 FB
00B1 0354
0083 C9
00B4
00B4
00B8
OOBC
OOCO
00C3
OOC5
00C7
OOCA
OOCC
OOCF
0001
0001
0001
0002
0003
0004
0006
0009
OOOA
OODC
OODE
OOEO
00E2
00E5
OOE7
00£8
OOEA
FD22DE01
FDCB08A6
FDCB0886
FD7E05
E60F
200A
FD7E05
F608
FD7705
E60F
3D
87
5F
1600
21E001
19
0E50
0602
EOB3
3E3C
114102
CF67
3C
CF67
11FE01
Li ne *** Source Statement ***
239+
240+
241+OUT2:
242+
243+
244+
245+
246+
247+INIT:
248+
249+
250+
251+
252+
253+
254+
255+
256+
257+
258+.SOMEB:
259+;
260+;
261+;
262+;
263+;
264+;
265+;
266+.0KB:
267+
268+
269+
270+
271+
272+
273+
274+
275+
276+
277+
278+
279+
280+
281+
OUT
JR
COA) ,A
OUT
LD
EI
OUT
RET
A,C
LD
RES
RES
LD
AND
JR
LD
(UCB),IY
4, ( IY+8)
0,(IY+8)
A,(IY+5)
OFH
NZ,.SOMEB
A, (IY+5)
11
( IY+5) ,A
OFH
save ucb addr
no sync mode
or sdlc
get baud rate
any
brif some
get prev
default to 9600
store
mask
12
C, .OKB
A, (IY+5)
OFOH
11
( IY+5) ,A
OFH
too big?
brlf ok
else, get enab
mask
merge 9600
A
A
E,A
0,0
HL,BAUO
HL,OE
C,CTC
B,2
less one
times two
OR
LD
AND
CP
JR
LD
AND
OR
LD
AND
DEC
ADD
LD
LD
LD
ADD
LD
LD
OTIR
LD
LD
SC
INC
SC.
LD
COA) ,A
loop
get char
turn on ints
write
return
mask
zero high
point table
offset.
two bytes
program It
A,SI04AV*2/2 ; vector number
DE,RETI
; durrmy
103
A
103
DE, INTI
input interrupt
8-12
SAMPLE DRIVERS
DEV25: CCS 2719 SIO Port A Driver
Addr Obj-Code
OOED 3C
OOEE CF67
OOFO 3C
00F1 CF67
00F3 F3
OOF4 3E02
00F6 D357
OOF8 3E70
OOFA D357
OOFC 3E04
OOFE D355
0100 FDCB087E
0104 280C
0106 FOCB0876
010A 3E40
OlOG 2006
OlOE 3E4F
0110 1802
0112
01123E4C
0114
0114 0355
01163E03
0118 0355
011A FDCB087E
011E 3ECl
0120 2802
01223E41
0124
0124 D355
0126 3EOl
0128 0355,
012A 3E18
012C D355
012E 3EOl
0130 0357
0132 3EIC
0134 0357
0136 3E05
0138 0355
013A FOCB087E
013E 3EEA
0140 2802
Line *** Source Statement ***
282+
283+
284+
285+
286+
287+
288+
289+
290+
291+
292+
293+
294+
295+
296+
297+
298+
299+
300+. NOP AR :
301+
302+.0UT:
303+
304+
305+
306+
307+
308+
309+
310+.NP:
311+
312+
313+
314+
315+
316+
317+
318+
319+
320+
321+
322+
323+
324+
INC
SC
INC
SC
DI
LD
OUT
LD
OUT
LD
OUT
BIT
JR
BIT
LD
JR
LO
JR
A
103
A
103
LO
A,01001100B
OUT
LO
OUT
BIT
LO
JR
LD
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Producer : Adobe Acrobat 9.2 Paper Capture Plug-in
Modify Date : 2010:01:17 18:10:04-08:00
Create Date : 2010:01:17 18:10:04-08:00
Metadata Date : 2010:01:17 18:10:04-08:00
Format : application/pdf
Document ID : uuid:252613d3-6f3b-464f-9063-b7d07f6f9ce0
Instance ID : uuid:e18bcf75-98c4-4d95-b3a8-7392cc959c6c
Page Layout : SinglePage
Page Mode : UseOutlines
Page Count : 67
EXIF Metadata provided by EXIF.tools