CM Series/CM Radios Detailed Service Manual 6866545D30 O

User Manual: -CM Series/CM Radios Detailed service manual 6866545D30-O

Open the PDF directly: View PDF .
Page Count: 390

Download
Open PDF In Browser	View PDF

Commercial Series
CM Radios

Detailed Service Manual
6866545D30-O

Commercial Series
CM Radios
Detailed Service Manual
6866545D30-O
Contents

Section 1

Service Maintainability

Section 2

Controlhead Service Information

Section 3

UHF2 Service Information

Section 4

VHF2 Service Information

Section 5

Midband Service Information

Section 6

UHF2 High Power Service Information

Section 7

VHF2 High Power Service Information

WLS EMEA Publications Department, Jays Close, Viables Industrial Estate, Basingstoke, Hampshire, RG22 4PD, UK.
Issue : December 2003

iii

Commercial Series
CM Radios
Service Maintainability

Issue: December 2003

Computer Software Copyrights
The Motorola products described in this manual may include copyrighted Motorola computer programs stored
in semiconductor memories or other media. Laws in the United States and other countries preserve for
Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or
reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer
programs contained in the Motorola products described in this manual may not be copied or reproduced in
any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola
products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license
under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive
royalty-free license to use that arises by operation of law in the sale of a product.

iii

Table of Contents
Chapter 1

INTRODUCTION

1.0 Scope of Manual ..................................................................................................1-1
2.0 Warranty and Service Support.............................................................................1-1
2.1 Warranty Period and Return Instructions .......................................................1-1
2.2 After Warranty Period .....................................................................................1-1
2.3 European Radio Support Centre (ERSC).......................................................1-2
2.4 Parts Identification and Ordering ....................................................................1-2
2.5 EMEA Test Equipment Support......................................................................1-2
2.6 Technical Support...........................................................................................1-3
2.7 Related Documents ........................................................................................1-3
3.0 Radio Model Information......................................................................................1-4

Chapter 2

MAINTENANCE

1.0 Introduction ..........................................................................................................2-1
2.0 Preventive Maintenance ......................................................................................2-1
2.1 Inspection .......................................................................................................2-1
2.2 Cleaning .........................................................................................................2-1
3.0 Safe Handling of CMOS and LDMOS..................................................................2-2
4.0 General Repair Procedures and Techniques.......................................................2-2
5.0 Notes For All Schematics and Circuit Boards ......................................................2-5

Chapter 3

SERVICE AIDS

1.0 Recommended Test Tools...................................................................................3-1
2.0 Test Equipment....................................................................................................3-2

SAFETY INFORMATION
Read this information before using your radio.

PRODUCT SAFETY AND RF EXPOSURE FOR MOBILE TWO-WAY RADIOS
INSTALLED IN VEHICLES OR AS FIXED SITE CONTROL STATIONS.
This document provides information and instructions for the safe and efficient operation of Motorola
Mobile Two-Way Radios. The information provided in this document supersedes information
contained in user guides published prior to February 2002.

COMPLIANCE WITH RF ENERGY EXPOSURE STANDARDS
Note:This Radio is intended for use in occupational/controlled applications, where users have been
made aware of the potential for exposure and can exercise control over their exposure. This radio
device is NOT authorized for general population, consumer or similar use.
This user safety booklet includes useful information about RF exposure and helpful instructions on
how to control your RF exposures.
Your Motorola radio is designed and tested to comply with a number of national and international
standards and guidelines regarding human exposure to radio frequency electromagnetic energy. This
radio complies with IEEE and ICNIRP exposure limits for occupational/controlled RF exposure
environments at usage factors of up to 50% talk–50% listen. In terms of measuring RF energy for
compliance with the IEEE/ICNIRP exposure guidelines, your radio radiates measurable RF energy
only while it is transmitting (during talking), not when it is receiving (listening) or in standby mode.

Your Motorola two-way radio complies with the following RF energy exposure
standards and guidelines:
●

●

●
●
●

●

United States Federal Communications Commission, Code of Federal Regulations; 47 CFR part 2
sub-part J
American National Standards Institute (ANSI) / Institute of Electrical and Electronic Engineers
(IEEE) C95. 1-1992
Institute of Electrical and Electronic Engineers (IEEE) C95.1-1999 Edition
International Commission on Non-Ionizing Radiation Protection (ICNIRP) 1998
Ministry of Health (Canada) Safety Code 6. Limits of Human Exposure to Radiofrequency Electromagnetic Fields in the Frequency Range from 3 kHz to 300 GHz, 1999
Australian Communications Authority Radiocommunications (Electromagnetic Radiation - Human
Exposure) Standard 2001
ANATEL, Brasil Regulatory Authority, Resolution 256 (April 11, 2001) “additional requirements for
SMR, cellular and PCS product certification.”

COMPLIANCE AND CONTROL GUIDELINES AND OPERATING INSTRUCTIONS FOR
MOBILE TWO-WAY RADIOS INSTALLED IN VEHICLES
To control your exposure and ensure compliance with the occupational/controlled environment
exposure limits, always adhere to the following procedures:
●

To transmit (talk), push the Push-To-Talk (PTT) button; to receive, release the PTT button. Transmit
only when people outside the vehicle are at least the minimum lateral distance away from a properly
installed, externally-mounted antenna. Table 1 lists the minimum distance for bystanders in an
uncontrolled environment from the transmitting antenna at several different ranges of rated radio
power for mobile radios installed in a vehicle..
Table 1: Rated Power and Distance

●

Rated Power of Vehicle-Installed
Mobile Two-Way Radio

Minimum Distance from
Transmitting Antenna

Less than 7Watts

20 cm (8 Inches)

7 to 15 Watts

30.5 cm (1 Foot)

16 to 50 Watts

61 cm (2 Feet)

51 to 110 Watts

91.5 cm (3 Feet)

Install mobile antennas at the centre of the roof and centre of the trunk deck. These mobile installation guidelines are limited to metal body vehicles. The antenna installation must additionally be in
accordance with:
a. The requirements of the antenna manufacturer/supplier

●

b. Instructions in the Radio Installation Manual.
Use only Motorola-approved supplied or replacement antenna. Use of non–Motorola - approved
antennas, modifications, or attachments could damage the radio and may violate IEEE/ICNIRP regulations. For a list of Motorola-approved antennas please see your dealer. Your nearest dealer can
be found at the following web site :

http://www.motorola.com/cgiss/emea/dealerlocator.html
For additional information on exposure requirements or other training information, visit
http://www.motorola.com/rfhealth.

COMPLIANCE AND CONTROL GUIDELINES AND OPERATING INSTRUCTIONS FOR
MOBILE TWO-WAY RADIOS INSTALLED AS FIXED SITE CONTROL STATIONS
If mobile radio equipment is installed at a fixed location and operated as a control station or as a fixed
unit, the antenna installation must comply with the following requirements in order to ensure optimal
performance and compliance with the RF energy exposure in the standards and guidelines listed
above:
●
●

The antenna must be mounted outside the building on the roof or a tower if at all possible.
As with all fixed site antenna installations, it is the responsibility of the licensee to manage the site in
accordance with applicable regulatory requirements and may require additional compliance actions
such as site survey measurements, signage, and site access restrictions in order to insure that
exposure limits are not exceeded.

vii

ELECTROMAGNETIC INTERFERENCE/COMPATIBILITY
NOTE: Nearly every electronic device is susceptible to electromagnetic interference (EMI) if
inadequately shielded, designed or otherwise configured for electromagnetic compatibility. It may be
necessary to conduct compatibility testing to determine if any electronic equipment used in or around
vehicles or near fixed site antenna is sensitive to external RF energy or if any procedures need to be
followed to eliminate or mitigate the potential for interaction between the radio transmitter and the
equipment or device.

Facilities
To avoid electromagnetic interference and/or compatibility conflicts, turn off your radio in any
facility where posted notices instruct you to do so. Hospitals or health care facilities may be
using equipment that is sensitive to external RF energy.

Vehicles
To avoid possible interaction between the radio transmitter and any vehicle electronic control
modules, for example, ABS, engine, or transmission controls, the radio should be installed only by an
experienced installer and that the following precautions be used when installing the radio:
1. Refer to the manufacturer’s instructions or other technical bulletins or recommendations on radio installation.
2. Before installing the radio, determine the location of the electronic control modules and their harnesses in
the vehicle.

3. Route all radio wiring, including the antenna transmission line, as far away as possible from the electronic
control units and associated wiring.

Driver Safety
Check the laws and regulations on the use of radios in the area where you drive. Always obey them.
When using your radio while driving, please:
●
●

Give full attention to driving and to the road.
Pull off the road and park before making or answering a call if driving conditions so require.

OPERATIONAL WARNINGS
For Vehicles With An Air Bag
Do not mount or place a mobile radio in the area over an air bag or in the air bag deployment area. Air
bags inflate with great force. If a radio is placed in the air bag deployment area and the air bag
inflates, the radio may be propelled with great force and cause serious injury to occupants of the
vehicle.

Potentially Explosive Atmospheres
Turn off your radio prior to entering any area with a potentially explosive atmosphere. Sparks in a
potentially explosive atmosphere can cause an explosion or fire resulting in bodily injury or even
death.
The areas with potentially explosive atmospheres referred to above include fuelling areas such as
below decks on boats, fuel or chemical transfer or storage facilities, areas where the air contains
chemicals or particles, such as grain, dust or metal powders. Areas with potentially explosive
atmospheres are often but not always posted.

Blasting Caps And Areas
To avoid possible interference with blasting operations, turn off your radio when you are near
electrical blasting caps, in a blasting area, or in areas posted:
"Turn off two-way radio". Obey all signs and instructions.

viii

For radios installed in vehicles fueled by liquefied petroleum gas, refer to the (U.S.) National Fire
Protection Association standard, NFPA 58, for storage, handling, and/or container information. For a
copy of the LP-gas standard, NFPA 58, contact the National Fire Protection Association, One Battery
Park, Quincy, MA.

Chapter 1
INTRODUCTION
1.0

Scope of Manual
This manual is intended for use by service technicians familiar with similar types of equipment. It
contains service information required for the equipment described and is current as of the printing
date. Changes which occur after the printing date may be incorporated by a complete Manual
revision or alternatively as additions.
NOTE Before operating or testing these units, please read the Safety Information Section in the

front of this manual.

2.0

Warranty and Service Support
Motorola offers long term support for its products. This support includes full exchange and/or repair
of the product during the warranty period, and service/ repair or spare parts support out of warranty.
Any "return for exchange" or "return for repair" by an authorised Motorola Dealer must be
accompanied by a Warranty Claim Form. Warranty Claim Forms are obtained by contacting an
Authorised Motorola Dealer.

2.1

Warranty Period and Return Instructions
The terms and conditions of warranty are defined fully in the Motorola Dealer or Distributor or
Reseller contract. These conditions may change from time to time and the following notes are for
guidance purposes only.
In instances where the product is covered under a "return for replacement" or "return for repair"
warranty, a check of the product should be performed prior to shipping the unit back to Motorola.
This is to ensure that the product has been correctly programmed or has not been subjected to
damage outside the terms of the warranty.
Prior to shipping any radio back to the appropriate Motorola warranty depot, please contact
Customer Resources (Please see page 2 and page 3 in this Chapter). All returns must be
accompanied by a Warranty Claim Form, available from your Customer Services representative.
Products should be shipped back in the original packaging, or correctly packaged to ensure no
damage occurs in transit.

2.2

After Warranty Period
After the Warranty period, Motorola continues to support its products in two ways.
1.

Motorola's Radio Aftermarket and Accessory Division (AAD) offers a repair service to both
end users and dealers at competitive prices.

AAD supplies individual parts and modules that can be purchased by dealers who are
technically capable of performing fault analysis and repair.

1-2

2.3

INTRODUCTION

European Radio Support Centre (ERSC)
The ERSC Customer Information Desk is available through the following service numbers:
Austria:

08 00 29 75 41

Italy:

80 08 77 387

Belgium:

08 00 72 471

Luxemburg:

08 00 23 27

Denmark:

80 88 05 72

Netherlands:

08 00 22 45 13

Finland:

08 00 11 49 910

Norway:

80 01 11 15

France:

08 00 90 30 90

Portugal:

08 00 84 95 70

Germany:

08 00 18 75 240

Spain:

90 09 84 902

Greece:

00 80 04 91 29 020

Sweden:

02 07 94 307

UK :

08 00 96 90 95

Switzerland:

08 00 55 30 82

Ireland:

18 00 55 50 21

Iceland:

80 08 147

Or dial the European Repair and Service Centre:
Tel: +49 30 6686 1555
Please use these numbers for repair enquiries only.

2.4

Piece Parts
Some replacement parts, spare parts, and/or product information can be ordered directly. If a
complete Motorola part number is assigned to the part, it is available from Motorola Radio
Aftermarket and Accessory Division (AAD). If no part number is assigned, the part is not normally
available from Motorola. If the part number is appended with an asterisk, the part is serviceable by
Motorola Depot only. If a parts list is not included, this generally means that no user-serviceable
parts are available for that kit or assembly.
All part orders should be directed to :
Motorola GmbH
Customer Care
AM Borsigturm 130
13507 Berlin
Germany.

2.5

EMEA Test Equipment Support
Information related to support and service of Motorola Test Equipment is available via Motorola
Online (Extranet), through the Customer Care organisation of Motorola’s local area representation
or by calling the the European Repair and Service Centre: Tel: +49 30 6686 1555

Warranty and Service Support

2.6

1-3

Technical Support
Motorola Product Services is available to assist the dealer/distributors in resolving any malfunctions
which may be encountered.
UK/Ireland - Richard Russell
Telephone: +44 (0) 1256 488 082
Fax: +44 01256 488 080
Email: BRR001@email.mot.com
Central/East Europe - Siggy Punzenberger
Telephone: +49 (0) 6128 70 2342
Fax: +49 (0) 6128 95 1096
Email: TFG003@email.mot.com
Scandinavia
Telephone: +46 8 735 9282
Fax: +46 8 735 9280
Email: C14749@email.mot.com
Germany -Customer Connect Team
Telephone: +49 (0) 6128 70 2248
Fax: +49 (0) 6128 95 1082
Email: cgiss.emea@europe.mot.com
France - Lionel Lhermitte
Telephone: +33 1 6929 5722
Fax: +33 1 6929 5904
Email: TXE037@email.mot.com
Italy - Ugo Gentile
Telephone: +39 0 2822 0325
Fax: +39 0 2822 0334
Email: C13864@email.mot.com
Africa & Middle East - Armand Roy
Telephone: +33 1 6929 5715
Fax: +33 1 6929 5778
Email: armand.roy@Motorola.com

2.7

Related Documents
The following documents are directly related to the use and maintainability of this product.
Title
CM Series Product Manual

Language

Part Number

English

GMLN1062_

German

GMLN1063_

French

GMLN1064_

Italian

GMLN1065_

Spanish

GMLN1066_

Russian

GMLN1067_

1-4

3.0

INTRODUCTION

Radio Model Information
The model number and serial number are located on a label attached to the back of your radio. You
can determine the RF output power, frequency band, protocols, and physical packages. The
example below shows one mobile radio model number and its specific characteristics.
Table 1-1 Radio Model Number (Example: MDM50FNC9AN2_N)
Type of Model
Unit
Series
M

M = Mobile

MD = Motorola Internal Use

Freq.
Band

Power
Level

Physical
Packages

Channel
Spacing

F
Midband
(6688MHz)
J
VHF1
(136162MHz)
K
VHF2
(146174MHz)

N
1-25W

C
CM140
CM340

9
Programmable

Q
P
UHF1 25-40W
(403430MHz)

F
CM160
CM360

R
Q
UHF2 25-45W
(438470MHz)
S
UHF3
(465495MHz)

Protocol

Feature
Level

Model
Revision

Model
Package

AA
Conventional
MDC

1
RF
Connector :
Mini-UHF

AN
5 Tone

2
RF
Connector :
BNC

Chapter 2
MAINTENANCE
1.0

Introduction
This chapter of the manual describes:

2.0

■

preventive maintenance

■

safe handling of CMOS devices

■

repair procedures and techniques

Preventive Maintenance
The radios do not require a scheduled preventive maintenance program; however, periodic visual
inspection and cleaning is recommended.

2.1

Inspection
Check that the external surfaces of the radio are clean, and that all external controls and switches
are functional. It is not recommended to inspect the interior electronic circuitry.

2.2

Cleaning
The following procedures describe the recommended cleaning agents and the methods to be
used when cleaning the external and internal surfaces of the radio. External surfaces include the
front cover, housing assembly, and battery case. These surfaces should be cleaned whenever a
periodic visual inspection reveals the presence of smudges, grease, and/or grime.
NOTE

Internal surfaces should be cleaned only when the radio is disassembled for servicing or
repair.

The only recommended agent for cleaning the external radio surfaces is a 0.5% solution of a mild
dishwashing detergent in water. The only factory recommended liquid for cleaning the printed
circuit boards and their components is isopropyl alcohol (70% by volume).

CAUTION: The effects of certain chemicals and their vapors can have harmful results on
certain plastics. Aerosol sprays, tuner cleaners, and other chemicals should be avoided.
1.

Cleaning External Plastic Surfaces
The detergent-water solution should be applied sparingly with a stiff, non-metallic, shortbristled brush to work all loose dirt away from the radio. A soft, absorbent, lintless cloth or
tissue should be used to remove the solution and dry the radio. Make sure that no water
remains entrapped near the connectors, cracks, or crevices.

Cleaning Internal Circuit Boards and Components
Isopropyl alcohol may be applied with a stiff, non-metallic, short-bristled brush to dislodge
embedded or caked materials located in hard-to-reach areas. The brush stroke should
direct the dislodged material out and away from the inside of the radio. Make sure that
controls or tunable components are not soaked with alcohol. Do not use high-pressure
air to hasten the drying process since this could cause the liquid to collect in unwanted
places. Upon completion of the cleaning process, use a soft, absorbent, lintless cloth to
dry the area. Do not brush or apply any isopropyl alcohol to the frame, front cover, or
back cover.

2-2

MAINTENANCE

NOTE

3.0

Always use a fresh supply of alcohol and a clean container to prevent contamination by
dissolved material (from previous usage).

Safe Handling of CMOS and LDMOS
Complementary metal-oxide semiconductor (CMOS) devices are used in this family of radios.
CMOS characteristics make them susceptible to damage by electrostatic or high voltage
charges. Damage can be latent, resulting in failures occurring weeks or months later. Therefore,
special precautions must be taken to prevent device damage during disassembly,
troubleshooting, and repair.
Handling precautions are mandatory for CMOS circuits and are especially important in low
humidity conditions. DO NOT attempt to disassemble the radio without first referring to the CMOS
CAUTION paragraph in the Disassembly and Reassembly section of the manual.

4.0

General Repair Procedures and Techniques
IC Pre-Baking
No pre-baking of components is required in the repair of this product.
Parts Replacement and Substitution
When damaged parts are replaced, identical parts should be used. If the identical replacement
component is not locally available, check the parts list for the proper Motorola part number and
order the component from the nearest Motorola Communications parts center listed in the “Piece
Parts” section of this manual.
Rigid Circuit Boards
The family of radios uses bonded, multi-layer, printed circuit boards. Since the inner layers are
not accessible, some special considerations are required when soldering and unsoldering
components. The through-plated holes may interconnect multiple layers of the printed circuit.
Therefore, care should be exercised to avoid pulling the plated circuit out of the hole.
When soldering near the 18-pin and 40-pin connectors:
■

avoid accidentally getting solder in the connector.

■

be careful not to form solder bridges between the connector pins

■

closely examine your work for shorts due to solder bridges.

General Repair Procedures and Techniques

2-3

Chip Components
Use either the RLN4062 Hot-Air Repair Station or the Motorola 0180381B45 Repair Station for
chip component replacement. When using the 0180381B45 Repair Station, select the TJ-65 minithermojet hand piece. On either unit, adjust the temperature control to 370 °C (700 °F), and
adjust the airflow to a minimum setting. Airflow can vary due to component density.
■

■

To remove a chip component:
1.

Use a hot-air hand piece and position the nozzle of the hand piece approximately 0.3 cm
(1/8") above the component to be removed.

Begin applying the hot air. Once the solder reflows, remove the component using a pair
of tweezers.

Using a solder wick and a soldering iron or a power desoldering station, remove the
excess solder from the pads.

To replace a chip component using a soldering iron:
1.

Select the appropriate micro-tipped soldering iron and apply fresh solder to one of the
solder pads.

Using a pair of tweezers, position the new chip component in place while heating the
fresh solder.

Once solder wicks onto the new component, remove the heat from the solder.

Heat the remaining pad with the soldering iron and apply solder until it wicks to the
component. If necessary, touch up the first side. All solder joints should be smooth and
shiny.

To replace a chip component using hot air:
1.

Use the hot-air hand piece and reflow the solder on the solder pads to smooth it.

Apply a drop of solder paste flux to each pad.

Using a pair of tweezers, position the new component in place.

Position the hot-air hand piece approximately 0.3 cm (1/8” ) above the component and
begin applying heat.

Once the solder wicks to the component, remove the heat and inspect the repair. All
joints should be smooth and shiny.

2-4

MAINTENANCE

Shields
Removing and replacing shields will be done with the R1070 station with the temperature control
set to approximately 215°C (415°F) [230°C (445°F) maximum].
■

■

To remove the shield:
1.

Place the circuit board in the R1070 circuit board holder.

Select the proper heat focus head and attach it to the heater chimney.

Add solder paste flux around the base of the shield.

Position the shield under the heat-focus head.

Lower the vacuum tip and attach it to the shield by turning on the vacuum pump.

Lower the focus head until it is approximately 0.3 cm (1/8”) above the shield.

Turn on the heater and wait until the shield lifts off the circuit board.

Once the shield is off, turn off the heat, grab the part with a pair of tweezers, and turn off
the vacuum pump.

Remove the circuit board from the R1070 circuit board holder.

To replace the shield:
1.

Add solder to the shield if necessary, using a micro-tipped soldering iron.

Next, rub the soldering iron tip along the edge of the shield to smooth out any excess
solder. Use solder wick and a soldering iron to remove excess solder from the solder
pads on the circuit board.

Place the circuit board back in the R1070 circuit board holder.

Place the shield on the circuit board using a pair of tweezers.

Position the heat-focus head over the shield and lower it to approximately 0.3 cm (1/8”)
above the shield.

Turn on the heater and wait for the solder to reflow.

Once complete, turn off the heat, raise the heat-focus head and wait approximately one
minute for the part to cool.

Remove the circuit board and inspect the repair. No cleaning should be necessary.

Notes For All Schematics and Circuit Boards

5.0

2-5

Notes For All Schematics and Circuit Boards
* Component is frequency sensitive. Refer to the Electrical Parts List for value and usage.
1. Unless otherwise stated, resistances are in Ohms (k = 1000), and capacitances are in picofarads
(pF) or microfarads (µF).
2. DC voltages are measured from point indicated to chassis ground using a Motorola DC
multimeter or equivalent. Transmitter measurements should be made with a 1.2 µH choke in
series with the voltage probe to prevent circuit loading.
3. Interconnect Tie Point Legend:

Signal Name

Signal Description

16_8MHz

16.8MHz Reference Frequency from Synthesizer to ASFIC

3V RF regulator

5V RF regulator

5V_CH

Optional 5V for Control Head

Regulated 9.3V Supply Voltage

9V to enable RX_INJ when RX_EN is active

ASFIC_CS

ASFIC Chip Select

B+

13.8V Supply Voltage

BATT_SENSE

Battery Voltage Sense Line

BOOT_EN_IN_CH

Boot Mode Select

BW_SEL

Select BW (12.5 KHz, 25 KHz)

CH_ACT

Channel Activity Indicator Signal (Fast Squelch)

COMM_DATA_SEL_CH

Display Driver Command/ Data Select

D3_V3

Regulated 3.3V supply voltage for Voice Storage

DEMOD

Audio Output Signal from the Receiver IC

DETECTOR_AUDIO_SEND_BRD

Flat Audio to Option Board

DISPLAY_CS_CH

Control Head Chip Select

EMERGENCY_ACCES_CONN

Emergency line to switch on the radio voltage regulators

EMERGENCY_SENSE

Emergency sense to µP

EXTERNAL_MIC_AUDIO ACCES_CONN

External (from accessory connector) microphone input

F1200

Interrupt line from ASFIC CMP

FILT_SW_B+

Switched 13.8 V supply voltage

FLAT_TX_AUDIO_INPUT_ACCESS_CONN

Flat TX input from accessory connector

HANDSE RX_AUDIO_CH

Handset Audio Output

HOOK_CH

Hang-up switch input

HSIO

High Speed Clock In / Data Out

IGNITION

Ignition Line to switch on he radio’s voltage regulator

KEYPAD_COL_CH

Keypad Matrix Column

LOC_DIST

Enable Attenuator for RX line

LSIO

Low Speed Clock In / Data Out

MIC_AUDIO_CH

Microphone Input

2-6

MAINTENANCE

MIC_PTT_CH

Microphone PTT Input

MOD_IN

Modulation Signal from ASFIC

MOD_OUT

Modulation Signal to the Synthesizer

ONOFF_SENSE

On off sense switch

OPT_DATA_R_OPRD

DATA/Ready Request from Option Board

OPT_EN_OPBD

Option Board Chip Select

PA_BIAS

PA Control bias voltage

PA_CURRENT

Not used

POST_LIMITER_TX
AUDIO_RETURN_OPT_BRD

Flat TX Input from Option Board

PROG x IN ACC y

General Purpose Input x accessory connector Pin y

PROG x INOUT ACC y

General Purpose Input/Output x accessory connector Pin y

PROG x OUT ACC y

General Purpose Input x accessory connector Pin y

PWR_SET

PA Power Control Voltage

RESET

Reset Line

RSSI

Received Signal Strength Indicator

RX signal

RX AUD RTN

Option Board Input/Output of Receiver Audio Path

RX_AUDIO_OUTPUT_ACCESS_CONN

Flat or filtered audio to accessory connector

RX_EN

Enable Receiving

RX_INJ

RF signal from VCO into the Receiver

SCI_CH

Bi-directional serial communication line

SHIFT_R_CS

SPI Chip select for the Control Head

SPI_CLK

Serial peripheral interface bus CLOCK

SPI_MISO

Serial peripheral interface bus data IN

SPI_MOSI

Serial peripheral interface bus data OUT

SPKR-

Negative Audio PA Speaker Output

SPKR-

Negative Audio PA Speaker Output

SPKR+

Positive Audio PA Speaker Output

SQ_DET

Squelch Detect Signal

SYNTH_CS

Synth Chip Select

SYNTH_LOCK

µP Clock Lock Signal

TX AUDIO_RETURN_OPT_BRD

Option Board Output to Transmit Audio Path

TX AUDIO_SEND_OPT_BRD

Microphone Audio to Option Board

TX_INJ

RF signal from the VCO to transmitter PA

TX_EN

Enable transmitting

UNMUTED RX_AUDIO_SEND_OPT_BRD

Unmuted filtered audio to option board

uP_CLK

µP Clock signal

VoL_INDIRECT

Volume Pot Input

VOX

Voice operated transmit level

Notes For All Schematics and Circuit Boards

2-7

VS AUDIO_SEL

Switch signal to Enable option board audio output signal

VS GAIN_SEL

Voice Storage Gain Select line

VS_MIC

Voice Storage Audio Signal to microphone path

VS_INT

Voice Storage Interrupt line

VS_RAC

Voice storage Row Address Clock Signal

VSTBY

3.3 V supply for µP when the radio is switched off

2-8

MAINTENANCE

Chapter 3
SERVICE AIDS
1.0

Recommended Test Tools
Table 3.1 lists the service aids recommended for working on the radio. While all of these items are
available from Motorola, most are standard workshop equipment items, and any equivalent item
capable of the same performance may be substituted for the item listed.
Table 3-1 Service Aids

Motorola Part
No.

Description

Application

RLN4460_

Portable Test Set

Enables connection to audio/accessory jack.
Allows switching for radio testing.

GMVN5034_

Customer Programming
Software (CPS) and Tuner
CDROM (MDC)

Programs customer options and channel data.
Tunes hardware parameters, front end,
power, deviation etc.

GMVN5033_

Customer Programming
Software (CPS) and Tuner
CDROM (5-Tone)

Programs customer options and channel data.
Tunes hardware parameters, front end,
power, deviation etc.

RKN4081_

Programming Cable with
Internal RIB

Includes radio interface box (RIB) capability.

FKN8096_

Data/Flash Adapter Key

Used with RKN4081 (10 to 8 pin adapter for
front Telco connector with Data/Flash switch).

RKN4083_

Mobile Programming/Test Cable Connects radio to RIB (RLN4008_).via rear
accessory connector

FKN8113_

Adapter Cable

Used with RKN4083 (20 to 16 pin adapter for
rear accessory connector).

GTF374_

Program Cable

Connects RIB to Radio microphone input.

RLN4008_

Radio Interface Box

Enables communications between radio and
computer’s serial communications adapter.

HLN8027_

Mini UHF to BNC Adaptor

Adapts radio antenna port to BNC cabling of
test equipment.

GPN6133_

Power Supply

Provides the radio with power when bench
testing.

EPN4040_

Wall-Mounted Power Supply

Used to supply power to the RIB (UK).

EPN4041_

Wall-Mounted Power Supply

Used to supply power to the RIB (Euro).

8180384N64

Housing Eliminator (25W)

Test Fixture used to bench test the radio pcb.

3080369B71

Computer Interface Cable

Connects the RIB to the Computer (25-pin).

3-2

SERVICE AIDS

Table 3-1 Service Aids

Motorola Part
No.

Description

Application

3080369B72

Computer Interface Cable

Connects the RIB to the Computer (9-pin)
(Use for IBM PC AT - other IBM models use
the B71 cable above).

6686119B01

Removal Tool

Assists in the removal of radio control head.

6680334F39

Hex Tool

Assists in the removal of antenna connector.

WADN4055A

Portable Soldering Station

Digitally controlled soldering iron.

6604008K01

0.4mm Replacement Tip

For WADN4055A Soldering iron.

6604008K01

0.8mm Replacement Tip

For WADN4055A Soldering iron.

0180386A82

Anti-static Grounding Kit

Used for all radio assembly/disassembly
procedures.

6684253C72

Straight Prober

6680384A98

Brush

1010041A86

Solder (RMA type)

63/37, 0.5mm diameter, 1lb. spool.

Test Equipment

2.0

3-3

Test Equipment
Table 3-2 lists test equipment required to service the radio and other two-way radios.
Table 3-2 Recommended Test Equipment

Motorola Part
No.

Description

Characteristics

Application

R2600_NT

Comms System
This monitor will
Analyzer (non MPT) substitute for items with
an asterisk *

Frequency/deviation meter
and signal generator for widerange troubleshooting and
alignment

*R1072_

Digital Multimeter

AC/DC voltage and current
measurements

*R1377_

AC Voltmeter

100 µV to 300 V,
5Hz-1MHz,
10 Megohm input
impedance

Audio voltage
measurements

WADN4133

Delay
Oscilloscope

2 Channel 40 MHz
bandwidth,
5 mV/cm - 20 V/cm

Waveform measurements

R1440_

Wattmeter,

Transmitter power output
measurements

0180305F17
0180305F31
0180305F40
RLN4610_

Plug-in Elements
Plug-in Elements
Plug-in Elements
Carry case

Thruline 50-Ohm,
±5% accuracy
10W, 25 - 60 MHz
10W, 100 - 250 MHz
10W, 200 - 500 MHz
Wattmeter and
6 elements

T1013_

RF Dummy Load

S1339_

RF Millivolt Meter

100mV to 3 VRF,
10 kHz to 1.2 GHz

RF level measurements

R1011_/220V

220V Power
Supply

0-40V, 0-40A

Programmable

3-4

SERVICE AIDS

Commercial Series
CM Radios
Controlhead
Service Information

Issue: December 2003

Computer Software Copyrights
The Motorola products described in this manual may include copyrighted Motorola computer programs stored
in semiconductor memories or other media. Laws in the United States and other countries preserve for
Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or
reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer
programs contained in the Motorola products described in this manual may not be copied or reproduced in
any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola
products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license
under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive royaltyfree license to use that arises by operation of law in the sale of a product.

iii

Table of Contents
Chapter 1

MODEL OVERVIEW

1.0 CM140/CM340 Models ........................................................................................1-1
2.0 CM160/CM360 Models ........................................................................................1-1

Chapter 2

THEORY OF OPERATION

1.0 Introduction ..........................................................................................................2-1
2.0 Controlhead Model for CM140 and CM340 .........................................................2-1
2.1 Power Supplies...............................................................................................2-1
2.2 Power On / Off................................................................................................2-1
2.3 Microprocessor Circuit....................................................................................2-1
2.4 SBEP Serial Interface.....................................................................................2-1
2.5 Keypad Keys ..................................................................................................2-1
2.6 Status LED and Back Light Circuit..................................................................2-3
2.7 Microphone Connector Signals ......................................................................2-3
2.8 Speaker ..........................................................................................................2-4
2.9 Electrostatic Transient Protection ...................................................................2-4
3.0 Controlhead Model for CM160 andCM360 ..........................................................2-4
3.1 Power Supplies...............................................................................................2-4
3.2 Power On / Off................................................................................................2-4
3.3 Microprocessor Circuit....................................................................................2-5
3.4 SBEP Serial Interface.....................................................................................2-5
3.5 Keypad Keys ..................................................................................................2-6
3.6 Status LED and Back Light Circuit..................................................................2-6
3.7 Liquid Crystal Display (LCD) ..........................................................................2-6
3.8 Microphone Connector Signals ......................................................................2-6
3.9 Speaker ..........................................................................................................2-7
3.10 Electrostatic Transient Protection ...................................................................2-8

Chapter 3

TROUBLESHOOTING CHARTS

1.0 Troubleshooting Chart for Controlhead CM140/340 ...........................................3-1
1.1 On/Off ............................................................................................................3-1
1.2 Microprocessor ..............................................................................................3-2
2.0 Troubleshooting Chart for Controlhead CM160/360 ............................................3-3
2.1 On/Off ............................................................................................................3-3
2.2 Microprocessor ..............................................................................................3-4
2.3 Display ...........................................................................................................3-5
2.4 Backlight ........................................................................................................3-6

Chapter 4

CONTROLHEAD PCB/SCHEMATICS/PARTS LISTS

1.0 Allocation of Schematics and Circuit Boards ....................................................... 4-1
2.0 Controlhead CM140/340 - PCB 8488998U01 Schematics.................................. 4-3
2.1 Controlhead PCB 8488998U01 - Parts List.................................................... 4-5
3.0 Controlhead CM160/360 - PCB 8489714U01 Schematics ................................. 4-6
3.1 Controlhead PCB 8489714U01 - Parts List ................................................... 4-8

Chapter 1
OVERVIEW
1.0

CM140/CM340Models
The Controlhead contains the internal speaker, the on/off/volume knob, the microphone connector,
several buttons to operate the radio, three indicator Light Emitting Diodes (LED) to inform the user
about the radio status, and a single character 7-segment display for numeric information e.g.
channel number.

2.0

CM160/CM360Models
The Controlhead contains the internal speaker, the on/off/volume knob, the microphone connector,
several buttons to operate the radio, three indicator Light Emitting Diodes (LED) to inform the user
about the radio status, and an 8 character Liquid Crystal Display (LCD) for alpha - numerical
information e.g. channel number or call address name.

1-2

OVERVIEW

Chapter 2
THEORY OF OPERATION
1.0

Introduction
This Chapter provides a detailed theory of operation for the Controlhead circuits. For details of the
trouble shooting refer to the related chapter in this section.

2.0

Controlhead Model for CM140 and CM340
The controlhead contains the internal speaker, the on/off/volume knob, the microphone connector,
several buttons to operate the radio and three indicator Light Emitting Diodes (LED) to inform the
user about the radio status and a 7-segment display for numeric information.

7-segment
display

9.3V

BCD To
7-segment

Shift
Register

Control line
Boot_res / SCI

DTMF
Resistors

Mux.
Control

PTT
circuit

DTMF
Row/Column
Row/Column

9.3V

Keypads
Keypad
Backlight

Boot_res (DTMFColumn)/ SCI
(DTMF-Row)
2 pin speaker
connector

2.1

Power Supplies
The power supply to the control head is taken from the host radio’s 9.3V via connector J803-9, The
9.3V is used for the LEDs and back light, the 5V is used for the LCD driver and level shifter. The
stabilized 3V is used for the other parts.

2.2

SPI Interface
The host radio (master) communicates with the control head through its SPI bus. Three lines are
connected to the shift register (U801):SPI clock (J803-17), SPI MOSI (J803-16) and shift register
chip select (J803-15).

2-2

THEORY OF OPERATION

When the host radio needs to send date to the shift register, the radio asserts the shift register chip
select and the data is loaded to the shift register. For example, the host radio sends data to change
display channel or change LED status.

2.3

Keypad Keys
The control head keypad is a four-key design. All keys are configured as two analog lines read by
µP. The voltage on the analog lines varies between 0V and 3.3 V depending on which key is
pressed. If no key is pressed, the voltage at both lines is 3.3V. The key configuration can be thought
of as a matrix where the two lines represent one row and one column. Each line is connected to a
resistive divider powered by 3.3V. If a button is pressed, it will connect one specific resistor of each
divider line to ground level and thereby reduce the voltages on the analog lines. The voltages of the
lines are A/D converted inside the µP (ports PE 6 - 7) and specify the pressed button. To determine
which key is pressed, the voltage of both lines must be considered.
The same analog lines also support a keypad microphone. A microphone key press is processed in
the same manner like a control head key press.

2.4

2.5

Microphone Connector Signals
The MIC_PTT line (J802-3) is grounded when the PTT button on the microphone is pressed. When
released, this line is pulled to 9.3V by R805. Two transistor stages (Q802, Q801 and associated
parts) are used to level shift between 9.3V and 3.3V required for the uP while keeping the same
sense (active low for PTT pressed).
Two of the mic socket lines (J802-2,7) have dual functions depending on the type of microphone or
SCI lead connected. An electronic switch (U803) is used to switch these two lines between mic
keypad operation or SCI operation. The switch (mux) is controlled by the uP through J803-20 with
level shifting (and inversion) provided by transistor Q812. When MUX_CTRL (J803-20) is low the
electronic switch is in the mic keypad mode. The mic socket (J802) pin 2 is connected to the keypad
row line that goes to J803-13 and pin 7 is connected to the keypad column line that goes to J803-12.
When MUX_CTRL (J803-20) is high the electronic switch is in the SCI mode. The mic socket (J802
pin 2) is connected to the SCI line that goes to J803-4 and pin 7 is connected to the BOOT_RES line
that goes to J803-11.
The HOOK line (J802-6) is used to inform the uP which type of microphone or SCI lead is connected
to the microphone socket. The voltage of the HOOK line is monitored by the uP (port PE0,
MIC_SENSE) through a resistor divider on the main board. When the HOOK line is grounded (on
hook condition) or floating (2.8V nominal), the uP sets the mux (U803) for keypad operation to allow
the use of microphones with a keypad. When the HOOK line is connected to 9.3V, the uP sets the
mux for SCI operation. This mode is also used to select low cost mic operation where the gain of the
microphone path is increased (on the main board) to compensate for not having a pre-amp in the low
cost mic.

Controlhead Model for CM140 and CM340

2-3

If the BOOT_RES (J802-7) line is connected to >5V (e.g. 9.3V) at turn-on, the uP will start in boot
mode instead of normal operation. This mode is used to programme new firmware into the FLASH
memory (U404 mainboard).

2.6

Speaker
The controlhead contains a speaker for the receiver audio. The receiver audio signal from the
differential audio output of the audio amplifier located on the radio’s controller is fed via connector
J803-1, 2 to the speaker connector P801 pin 1 and pin 2. The speaker is connected to the speaker
connector P801. The controlhead speaker can be disconnected if an external speaker, connected on
the accessory connector, is used.

2.7

Electrostatic Transient Protection
Electrostatic transient protection is provided for the sensitive components in the controlhead by
diodes VR801, VR802, VR803 and VR804. The diodes limit any transient voltages to tolerable
levels. The associated capacitors provide Radio Frequency Interference (RFI) protection.

2-4

3.0

THEORY OF OPERATION

Controlhead Model for CM160 and CM360
The controlhead contains the internal speaker, the on/off/volume knob, the microphone connector,
several buttons to operate the radio, three indicator Light Emitting Diodes (LED) to inform the user
about the radio status, and an 8 character Liquid Crystal Display (LCD) for alpha - numerical
information e.g. channel number or call address name.

9.3V

LCD

LED
Backlight

LED
Indicators

LCD
Driver

Level
Shifter
9.3V

Backlight
Control

Shift
Register
Control line
Boot_Res / SCI

Keypad
Resistors

Mux.
Control

PTT
circuit

DTMF
Row/Column

8 pin JACK
connector

Row/Column
Keypads

Boot_Res (DTMFColumn)/ SCI
(DTMF-Row)
2-pin speaker
connector

3.1

Power Supplies
The power supply to the control head is taken from the host radio’s 9.3V via connector J103-9, The
9.3V is used for the LEDs and back light, the 5V is used for the LCD driver (U3) and level shifter
(U4). The stabilized 3V is used for the other parts.

3.2

SPI Interface
The host radio (master) communicates with the control head through its SPI bus. Three lines are
connected to the shift register (U8):SPI clock (J103-17), SPI MOSI (J103-16), shift register chip
select (J103-15) and LCD driver chip select (J103-18).
When the host radio needs to send date to the shift register, the radio asserts the shift register chip
select and the data is loaded to the shift register. For example, the host radio sends data to change
display channel or change LED status.

Controlhead Model for CM160 and CM360

3.3

2-5

3.4

LCD Driver
The LCD (36 x 4 segemnts) is controlled by U3. It has an on onboard clock controlled by R28
(typically 20kHz measured on pin 2). U3 is operated from the 5V supply and is controlled over the
SPI bus (SPI_CLK J103-17, SPI_MOSI J103-16, LCD chip select J103-18). Chip select is active low.
U2 is used to provide level shifting between the 3.3V logic from the uP and the 5V required by U3.

3.5

Status LED’s and Back Light Circuit
All indicator LEDs (red, yellow, and green) are driven by current sources. To change the LED status
the host radio sends a data message to the control head shift register via the SPI bus. The control
head shift register determines the LED status from the received data and switches the LEDs on or
off via Q8-Q10.
Backlighting for the LCD and keys is provided by a matrix of 21 LEDs arranged in 7 columns of 3
rows. The LEDs are driven from a constant current circuit (Q12, U1 and associated parts). There are
4 levels of baclight: off, low, medium and high, which are controlled by two outputs (pins 15, 1) from
the shift register (U8). The current is controlled by transistor Q12. The op amp U1 monitors the
current by measuring the voltage drop across R26, R27 and adjusting the bias of Q12 to achieve the
required level as set by the combined shift register o/ps. When in the off state, Q11 is also turned on
to clamp the base of Q12 so as to force it off. This ensures that the LEDs are fully off. Q11 is
controlled by pin 3 of the shift register U8.

3.6

Microphone Connector Signals
The MIC_PTT line (J102-3) is grounded when the PTT button on the microphone is pressed. When
released, this line is pulled to 9.3V by R33. Two transistor stages (Q14, Q13 and associated parts)
are used to level shift between 9.3V and 3.3V required for the uP while keeping the same sense
(active low for PTT pressed).
Two of the mic socket lines (J102-2, 7) have dual functions depending on which type of microphone
or SCI lead that is connected. An electronic switch (U41) is used to switch these two lines between
mic keypad operation or SCI operation. The switch (mux) is controlled by the uP through J103-20
with level shifting (and inversion) provided by transistor Q41. When MUX_CTRL (103-20) is low the
electronic switch is in the mic keypad mode. The mic socket (J102) pin 2 is connected to the keypad
row line that goes to J103-13 and pin 7 is connected to the keypad column line that goes to 103-12.
When MUX_CTRL (103-20) is high the electronic switch is in the SCI mode. The mic socket (J102
pin 2) is connected to the SCI line that goes to J103-4 and pin 7 is connected to the BOOT_RES line
that goes to J103-11.

2-6

THEORY OF OPERATION

The HOOK line (J102-6) is used to inform the uP which type of microphone or SCI lead is connected
to the microphone socket. The voltage of the HOOK line is monitored by the uP (port PE0,
MIC_SENSE) through a resistor divider on the main board. When the HOOK line is grounded (on
hook condition) or floating (2.8V nominal), the uP sets the mux (U8) for keypad operation to allow the
use of microphones with a keypad. When the HOOK line is connected to 9.3V, the uP sets the mux
for SCI operation. This mode is also used to select low cost mic operation where the gain of the
microphone path is increased (on the main board) to compensate for not having a pre-amp in the low
cost mic.
If the BOOT_RES (J102-7) line is connected to >5V (e.g. 9.3V) at turn-on then the uP will start in
boot mode instead of normal operation. This mode is used to programme new firmware into the
FLASH memory (U404 mainboard).

3.7

Speaker
The controlhead contains a speaker for the receiver audio. The receiver audio signal from the
differential audio output of the audio amplifier located on the radio’s controller is fed via connector
J103-1, 2 to the speaker connector P101 pin 1 and pin 2. The speaker is connected to the speaker
connector P101. The controlhead speaker can be disconnected if an external speaker, connected on
the accessory connector, is used.

3.8

Electrostatic Transient Protection
Electrostatic transient protection is provided for the sensitive components in the controlhead by
diodes VR1 - VR4. The diodes limit any transient voltages to tolerable levels. The associated
capacitors provide Radio Frequency Interference (RFI) protection.

Chapter 3
TROUBLESHOOTING CHARTS
1.0
1.1

Controlhead CM140/CM340 Troubleshooting Chart
Control Head Failure
Control Head Check

Back light
OK ?

Check 9.3V on
R808, R809

YES

Power-up
Alert Tone
OK ?

Check Speaker
Connection

Check
D801, Q806, U801

YES

Power-up
Red LED
Flash ?

YES

Channel
Display
OK?

Check
DS801, U801, U802

YES

Up/Down
P1 and P2
Alert Tone
Buttons OK?

Check R845, R846
R810, R811

YES

EXT
PTT
OK ?

YES
Communication Ok
Control Head is OK

Check Q801, Q802

Check Q803, Q812

3-2

1.2

TROUBLESHOOTING CHARTS

Button/Tones Select Error (Page 1 of 2)
Button/Tones Check

Check Voltage Levels on
TP401 (Keypad Col)
and TP402 (Keypad Row)
(see table on next page)

Right
Voltage
Up Key

Check R846, R811
on Control Head

YES
Right
Voltage
No
on Down Key
?

Check R845, R810
on Control Head

YES
Right
Voltage
on P1/P2
Keys ?

Check R813, R814
on Control Head

YES
Connect DTMF Mic
to TELCO Connector

Is there
0.75 Vdc on
MIC_SENSE
R429, on radio

Check Control Head
connectivity continuity
and R429, R430, D401
(main board)

Controlhead CM140/CM340 Troubleshooting Chart

Button/Tones Select Error (Page 2 of 2)
A

Right
Voltage
on DTMF keys
?

Does Q812
on Control Head
operates well
?

YES

Key_Col
Voltage
(TP401)

Replace
Q812

YES

Replace U803
on Control Head

Button/Tones Keys
Okay

Key_Row Voltage TP402

1.3

3-3

Key_Column Voltage TP401
0.008 V

0.675 V

1.346 V

1.997 V

2.650 V

0.008 V

0.675 V

1.346 V

1.997 V

2.650 V

Left Key
P1

Right Key
P2

3.300 V

Down

Idle

3-4

2.0
2.1

TROUBLESHOOTING CHARTS

Controlhead CM160/CM360 Troubleshooting Chart
Control Head Failure
Control Head Check

Back light
OK ?

Check 9.3V on
Q12, U1 and associated
parts and U8

YES

Power-up
Alert Tone
OK ?

Check Speaker
Connection

Check
Q8-Q10, U8 and 9.3V

YES

Indicator
LED’S
OK ?
YES

Display
OK?

Check LCD
connections, U3 for 5V,
Osc. pins 1 & 2 activity
SCI thru via U4

YES

Up/Down
P1 and P2
Alert Tone
Buttons
OK?

Check keypad resistors

YES

EXT
PTT
OK ?

YES
Communication Ok
Control Head is OK

Check Q13, Q802

Check Q803, Q14 and
associated parts

Controlhead CM160/CM360 Troubleshooting Chart

2.2

3-5

Button/Tones Select Error (Page 1 of 2)
Button/Tones Check

Check Voltage Levels on
TP401 (Keypad Col)
and TP402 (Keypad Row)
(see table on next page)

Right
Voltage
Up Key?

Check R13, R45
on Control Head

Check R12, R49
on Control Head

Check R31, R29
R51, R11
on Control Head

YES
Right
Voltage
on Down
Key?

YES
Right
Voltage
on P1-P4
Keys ?

YES
Connect DTMF Mic
to TELCO Connector

Is there
0.75 Vdc on
MIC_SENSE
R429, on radio

Check Control Head
connectivity continuity
and R429, R430, D401
(Main Board)

3-6

Button/Tones Select Error (Page 2 of 2)
A

Right
Voltage
on DTMF keys
?

Does Q41
on Control Head
operates well
?

YES

Key_Col
Voltage
(TP401)

Replace
Q41

YES

Replace U8
on Control Head

Button/Tones Keys
Okay

Key_Row Voltage TP402

2.3

TROUBLESHOOTING CHARTS

Key_Column Voltage TP401
0.008 V

0.675 V

1.346 V

1.997 V

2.650 V

0.008 V

0.675 V

1.346 V

1.997 V

2.650 V

Left Key
P1

Right Key
P2

3.300 V

Down

Idle

Chapter 4
CONTROLHEAD PCB / SCHEMATICS / PARTS LISTS
1.0

Allocation of Schematics and Circuit Boards
Table 4-1 Controlhead Diagrams and Parts Lists
PCB :

Controlhead CM140/CM340
8488998U01 Main Board Top Side
8488998U01 Main Board Bottom Side

Page 4-3
Page 4-3

SCHEMATICS
Sheet 1 of 1

Page 4-4

Parts List
8488998U01

Page 4-5

Table 4-2 Controlhead Diagrams and Parts Lists
PCB :

Controlhead CM160/CM360
8489714U01 Main Board Top Side
8489714U01 Main Board Bottom Side

Page 4-6
Page 4-6

SCHEMATICS
Sheet 1 of 1

Page 4-7

Parts List
8489714U01

Page 4-8

4-2

CONTROLHEAD PCB / SCHEMATICS / PARTS LISTS

THIS PAGE INTENTIONALLY LEFT BLANK

Controlhead CM140/CM340 - PCB 8488998U01 / Schematics

Controlhead CM140/CM340 - PCB 8488998U01 / Schematics
D802

D801

D803

J804
DS801

D806

SH1

J805
J802

S802
D805

D804

S801

Top Side

SHOWN FROM SIDE 1
8488998u01_p3

C814

C802

C801

C813

C803

C805

C804

C811

C806

C812

C809

C807

C810

C808

R808

R818

R809

R819

R820

Bottom Side

SHOWN FROM SIDE 2

Q802

R807

R806
Q801

C822

C821

C820

C819

VR802

VR804
R833

M804

C818

C816

C817

M802

C815
1

R840

R801
R804

R834

VR803

C823

R805

R802
C833

C836

R841

R810

R844

R811 R839

R848

R842

Q803

R829

R816

R847

R813

R842

C832

Q812

U801

R846

C834

R830

R850

P801
C825
C824
R826
R827
R821
R822
R823
R824
R825

J803

C826

R803

C827

R845

R843

R832

Q811

R849

1
Q806

R831

1
Q805

M801

1
1
Q804

M803

2.0

4-3

Controlhead CM140/CM340
PCB 8488998U01

4-4

Controlhead CM140/CM340 - PCB 8488998U01 / Schematics

D3_3V

C824

R842

R847

10.K

C825

220.p

M801

100n

THESE ARE THE
1
BI

M802
ESD PROTECTION

D3_3V
1
M803
DNP

CONTACTS (SPRINGS)
1
M804

9_3V

C826

DS801

C827

R829

R843

100n

10.K

DNP
9_3V

R821

33.

R822

33.

220.p

D3_3V

HDSP-513G

R820

3.9K

680.

ANODE_D

ANODE_G
ANODE_DP

33.

R826

33.

R827

33.

J803-17

1
2
3
4

J803-16

CLK_S

CLK_L

EN_OE

RESET

J803-15

J803-12

J803-13

J803-2

J803-1

U801
MC74HC595A

SEROUT

SERIN

R850

J803-3

J803-4

10K

J803-6
J803-11

R830
470.

J803-18

Q803

10K

100n

D3_3V

J803-10

C834

C832

SHIELD

R802
R844

C801

C803

3.3K

220.p

DNP
C805

220.p

C809

220.p

C811

220.p

C813

220.p

SPI_MOSI

KEY_COL

KEY_ROW

SPKR+
SPKR-

RX. AUDIO

SCI

MIC. PTT
MIC. AUDIO

HOOK

BOOT_RES

DISP_CS

COM/DATA_SEL

J803-21

C807

220.p

SH_R_CS

J803-22

220.p

10K

10.K

Place under the 7-segment

DNP

SPI_CLK

J803-7
DNP

22.n

47K
10K
Q805

J803-20

DISPL_CS

SH1

DIS_RES

J803-8

Q804

J803-5

CH_PTT

DNP

GND

9_3V

47K

14
9

J803-19

3
LT
U802
D2 MC14511BFEL
7
A1
E
1
15
B1
F
2
14
G
C1
6
D1
10

GREEN LED

YELLOW LED

RED LED

33.

R825

ANODE_C

D803

R824

ANODE_F

HSMG-C670

HSMY-C670

HSMH-C670

D802

33.

COMM_CATH_2
COMM_CATH_1

D801

R823

VSS

R819

J803-9

ANODE_A
R818

MAIN BOARD CONNECTOR
J803-14
5

VCC

VDD

ANODE_B
ANODE_E

Q811

47K
10K

47K

DISPL_CS

Q812
C802

C815 R801

47K

10u

9_3V

C804

220.p

C806

220.p

C808

220.p

C810

220.p

C812

220.p

C814

220.p

10K
Q806
47K
DNP
100n

9_3V

220.p

C836

2
1
5

VCC
Y0

Y
Y1

Z0
Z
Z1

R849

Change to 1%

GND

X
X1

R841

DNP

10.K
14

R833

11
0.
15

9_3V

D3_3V

9_3V

TELCO_PTT

D3_3V

10
DNP

DNP

VEE

R848

R846

R831

10.K

51.K

20.K

DNP
R832
20.K

J802-8
8

9.3 V

J802-7
7

BOOT_RES

J802-6
6

HOOK

J802-4
4

MIC. AUDIO

J802-3
3

MIC. PTT

J802-2
2

SCI

J802-1
1

RX. AUDIO

J802-5
5

R845
51.K
C816

U803
MC14053B

MICROPHONE CONNECTOR

R834
9_3V

C833

C820

C818

C822

13K
VR801

VR803

20.0

220.p

ROW
Change to 1%

Change to 1%

R813

R816

22K

13K

COL
DNP
KEYPAD BACKLIGHT
R811

R810

0.
9_3V

C819

C817

9_3V

VR802

VR804

20.0

20.

C821

220.p

SPEAKER CONNECTOR

DNP

3
5

4
6

CONTACT
1

PIN1

PIN2
DOWN

680.

R839

R840

22.K

D3_3V

9_3V

R803
R805

R804

47.K
Q801

47.K

10.K

CONTACT
2

PIN1

PIN2
UP

D805

D806

CH_PTT

10K

R806
Q802

47.K

47K

TELCO_PTT

R807
C823
1n

Controlhead CM140/CM340 Schematic

10.K

SPKRSPKR+
73B02964C39-O

D804

J804

J805
2

R809

300.

HSMG-C670

R808
DNP

HSMG-C670

S801
TOUCH_SW_MARLIN

P801-2
2

HSMG-C670

S802

P801-1
1

ROW

Change to 1%

TOUCH_SW_MARLIN

COL

Controlhead CM140/CM340 - PCB 8488998U01 / Schematics

2.1

Controlhead PCB 8488998U01 Parts
List

Circuit
Ref

Motorola
Part No

Description

4-5

Circuit
Ref

Motorola
Part No

Description

Circuit
Ref

Motorola
Part No

Description

J803

0989241U02

FLEX 20-PIN 1mmTOP NON

R830

0662057A41

CHIP RES 470 OHMS 5%

M801

7588823L03

PAD GROUNFD LCD

R841

0662057A73

CHIP RES 10K OHMS 5%

M802

7588823L03

PAD GROUNFD LCD

R842

0662057A73

CHIP RES 10K OHMS 5%

C802

2113740F59

CAP CHIP REEL CL13

M803

7588823L03

PAD GROUNFD LCD

R843

0662057A73

CHIP RES 10K OHMS 5%

C804

2113740F59

CAP CHIP REEL CL13

M804

7588823L03

PAD GROUNFD LCD

R844

0662057A73

CHIP RES 10K OHMS 5%

C805

2113740F39

CAP CHIP REEL CL1+/-30 33

P801

2809926G01

CONN 1.25MM 2PIN SURMT

R845

0662057A90

CHIP RES 51K OHMS 5%

C806

2113740F39

CAP CHIP REEL CL1+/-30 33

Q801

4809940E02

TSTR NPN DIG DTC114YE

R846

0662057A90

CHIP RES 51K OHMS 5%

C808

2113740F59

CAP CHIP REEL CL13

Q802

4813824A10

TSTR NPN 40V .2A GEN P

R849

0662057D03

CHIP RES 13K OHMS 5%

C809

2113740F39

CAP CHIP REEL CL1+/-30 33

Q803

4809940E02

TSTR NPN DIG DTC114YE

C810

2113740F39

CAP CHIP REEL CL1+/-30 33

Q804

4809940E02

TSTR NPN DIG DTC114YE

C811

2113740F59

CAP CHIP REEL CL13

Q805

4809940E02

TSTR NPN DIG DTC114YE

C812

2113740F39

CAP CHIP REEL CL1+/-30 33

Q806

4809940E02

TSTR NPN DIG DTC114YE

C813

2113740F59

CAP CHIP REEL CL13

Q811

4809940E02

TSTR NPN DIG DTC114YE

C814

2113740F59

CAP CHIP REEL CL13

Q812

4809940E02

TSTR NPN DIG DTC114YE

C816

2113740F39

CAP CHIP REEL CL1+/-30 33

R801

0662057A01

CHIP RES 10 OHMS 5%

C817

2113740F39

CAP CHIP REEL CL1+/-30 33

R802

0662057A61

CHIP RES 330 OHMS 5%

C818

2113740F39

CAP CHIP REEL CL1+/-30 33

R803

0662057A89

CHIP RES 47K OHMS 5%

C819

2113740F39

CAP CHIP REEL CL1+/-30 33

R804

0662057A89

CHIP RES 47K OHMS 5%

C820

2113740F39

CAP CHIP REEL CL1+/-30 33

R805

0662057A73

CHIP RES 10K OHMS 5%

C821

2113740F29

CAP CHIP REEL CL1+/-30 12

R806

0662057A89

CHIP RES 47K OHMS 5%

C822

2113740F39

CAP CHIP REEL CL1+/-30 33

R807

0662057A73

CHIP RES 10K OHMS 5%

C823

2113743K15

CER CHIP CAP .100uF

R808

0662057A36

CHIP RES 300 OHMS 5%

C824

2113740F59

CAP CHIP REEL CL13

R809

0662057A45

CHIP RES 680 OHMS 5%

C825

2113743K15

CER CHIP CAP .100uF

R810

0662057B47

CHIP RES 0 OHMS +0.5

C826

2113740F59

CAP CHIP REEL CL13

R811

0662057B47

CHIP RES 0 OHMS +0.5

C827

2113743K15

CER CHIP CAP .100uF

R813

0662057D08

CHIP RES 22K OHMS 5%

C832

2113743K15

CER CHIP CAP .100uF

R816

0662057D03

CHIP RES 13K OHMS 5%

C833

2113743K15

CER CHIP CAP .100uF

R818

0662057A63

CHIP RES 3900 OHMS 5%

C834

2113743E07

CER CHIP CAP .022uF

R819

0662057A45

CHIP RES 680 OHMS 5%

C836

2113740F59

CAP CHIP REEL CL13

R820

0662057A45

CHIP RES 680 OHMS 5%

D801

4805729G74

LED SMT RED HP

R821

0662057A13

CHIP RES 33 OHMS 5%

D802

4805729G73

LED SMT YEL HP

R822

0662057A13

CHIP RES 33 OHMS 5%

D803

4805729G75

LED SMT GREEN HP

R823

0662057A13

CHIP RES 33 OHMS 5%

D804

4805729G75

LED SMT GREEN HP

R824

0662057A13

CHIP RES 33 OHMS 5%

D805

4805729G75

LED SMT GREEN HP

R825

0662057A13

CHIP RES 33 OHMS 5%

D806

4805729G75

LED SMT GREEN HP

R826

0662057A13

CHIP RES 33 OHMS 5%

DS801

5180353L02

7-SEGMENT DISPLAY

R827

0662057A13

CHIP RES 33 OHMS 5%

J802

0908353Y02

MODULAR 8-PIN STR

R829

0662057A73

CHIP RES 10K OHMS 5%

C33
R22

C18
R21
R17

R16
R54

R31

Q14
VR2

Q41
1

VR1
VR3

C34

R38

R33

R43

D26

D20

S2
1

12
M1

R48

R12

C29

J103
R34

R50

R25

C24

R13

R46

R45

R44

R18

C17

R19

R27

R26

C42

C40
R36

R49
C41

C45

C44

C46

C48

C47

C50

C27

C49

C38

C51

C52

C53

C55

C54

R35

D12

D13

D23

D25

D22

D11

D16

D15

D14

D17

D21

D27

D24

DS1

R42

R40

R14

C15

Q13

R41 C56

C14

C58

R23

R30

R39

C32
Q10

C30

R28

C16

R15

C20

R20

R24

C11

C26

Q11

D18

R29

D19

R51

P101
C36

C25 R10

U18

4
Q12

6
7

3
4

C39

C21

C22

C35

R11

C23
8

C19

3.0

4-6
Controlhead CM160/CM360 - PCB 8489714U01 / Schematics

Controlhead CM160/CM360 - PCB 8489714U01 / Schematics

1
S6

1
D10

Top Side

J102

R37

C43
C6

Bottom Side

VR4

U41
9
8

Controlhead CM160/CM360 PCB
8489714U01

Controlhead CM160/CM360 - PCB 8489714U01 / Schematics

4-7

D3_3V
COM3
4
COM2
3
COM1
2
COM0
1

9_3V

R37
47K

SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0

DS1
LCD_36PIN
DNF

R36

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
5V_CH

Q14
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CK

C30
100pF
DNF

R30
10K
DNF

D3_3V

U2-1
MC74HCT04A
2
13

R23
680

9_3V

Q9
47K

R54

ROW

9_3V
Q8
R44
20K
DNF

HSMG-C670
D24

HSMG-C670
D22

R51
43K

VDD

C48
220pF
DNF

C46
220pF
DNF

C44
220pF
DNF

6
C52
470pF

R35
3.3K

R43
0
DNF

15
ZB
10
SB

C47
220pF
DNF

C45
220pF
DNF

9_3V

R42
0
DNF

4
ZC
9
SC

C49
470pF

MICROPHONE CONNECTOR

R13
51K

S6
TOUCH_SW
DNF
S1
TOUCH_SW
DNF

S2
TOUCH_SW
DNF
1
C1
3
C3
5
C5

R16

2
C2
4
C4
6
C6

1
C1
3
C3
5
C5

2
C2
4
C4
6
C6

R46
22K
DNF
9_3V

C2
470pF

C27
1000pF
DNF

J102-8

J102-7

BOOT_RES

J102-6

HOOK

J102-4

MIC. AUDIO

J102-3

MIC. PTT

J102-2

SCI

J102-1

RX. AUDIO

J102-5

P101-1

SPKR-

P101-2

SPKR+

9.3 V

C5
470pF

C3
470pF

C6
1000pF
DNF

D3_3V
VR4
20V

27K

C42
1000pF
DNF

VR2
20V

C29
1000pF
DNF

C34
1000pF
DNF

R29

R31

22K

13K

R48
20K
DNF

R12
51K

VR1
20V

VR3
20V

R49
0
C17
1000pF
DNF

S5
TOUCH_SW
DNF

R18
1K

S3
TOUCH_SW
DNF

R19
10K

1
C1
3
C3
5
C5

2
C2
4
C4
6
C6

1
C1
3
C3
5
C5

2
C2
4
C4
6
C6

DOWN
-

Controlhead CM160/CM360 Schematic

5V_CH
R50
22K
DNF

C4
1000pF
DNF
U1-2
LM2904
7

6
5

R20
10K
DNF

S4
TOUCH_SW
DNF
R27
10

Y1C

C51
220pF
DNF

DIS_RES
SPI_CLK
SH_R_CS
SPI_MOSI
KEY_COL
KEY_ROW
SPKR+
SPKRRX. AUDIO
SCI
MIC. PTT
MIC. AUDIO
HOOK
BOOT_RES
DISP_CS
COM/DATA_SEL

47K

R26
10

C53
220pF
DNF

J103-14
J103-9
J103-19
J103-17
J103-15
J103-16
J103-12
J103-13
J103-2
J103-1
J103-3
J103-4
J103-5
J103-6
J103-8
J103-11
J103-20
J103-18
J103-10
J103-7
J103-21
J103-22

0.1uF

C18
0.1uF

VCC
GND
7

Q11

CH_PTT
R3
10

R45
0

C39
1000pF
DNF

R11
130K

10K

DNF

14
9
19
17
15
16
12
13
2
1
3
4
5
6
8
11
20
18
10
7
G1
G2

TELCO_PTT

2.2K

Q12

C1
10uF

14
ZA
11
SA

1
Y1B
5
Y0C
3

D3_3V

10K

HSMG-C670
D25

HSMG-C670
D23

HSMG-C670
D21
HSMG-C670
D20

HSMG-C670
D9

HSMG-C670
D4

HSMG-C670
D8

HSMG-C670
D5

HSMG-C670
D27

R24

YOA

13
Y1A
2
Y0B

COL

13K
U1-1
LM2904
1

U41
HEF4053B

13K

R17

C11
0.1uF

R41
10K

C56

9_3V

47K

HSMG-C670
D13

HSMG-C670
D12

HSMG-C670
D11

HSMG-C670
D16

HSMG-C670
D15

HSMG-C670
D14

HSMG-C670
D17
HSMG-C670
D3
HSMG-C670
D2

HSMG-C670
D26

C40
1000pF
DNF
C26
1000pF

C14
0.1uF
DNF

MUX_CTL
CS

47K

C41
1000pF
DNF

9_3V

Q41

10K

9_3V

11
12
13
10

Q10

10K

MAIN BOARD CONNECTOR

10K

MUX_CTL

5
9_3V

9_3V

C38
1000pF
DNF

R40
10K

CK
9_3V

C54
470pF

Q7
14
SEROUT SERIN

VSS
8
VEE
7

C25
1000pF
DNF

U2-2
MC74HCT04A
4
11

GND

C20
2.2uF
DNF

R22
680

R21
3.9K

47K

9_3V

Q0
CLK_S
Q1
Q2
CLK_L
EN_OE
Q3
Q4
RESET
U8
Q5
MC74HC595A
Q6

C32
100pF
DNF

9_3V

R10
0
DNF

C55
220pF
DNF

C58
.022uF

GND

9_3V
D18
HSMY-C670

C33
100pF
DNF

D19
HSMH-C670

1
5
2
6

15
1
2
3
4
5
6
7
9

R39
10K

9_3V

U2-3
MC74HCT04A
9
6

8
INPUT
OUTPUT
7
FEEDBACK ERROR
3
SHUTDOWN SENSE
5V_TAP

680K

U2-6
MC74HCT04A
12

U18
LP2951C
DNF

R8
10K
DNF

U2-5
MC74HCT04A
10

R15
10K
DNF

U2-4
MC74HCT04A
8

C22
0.1uF

C50
470pF

R14
10K

5V_CH

R28
C21
4.7uF
DNF

C15
0.1uF

12
13
14
15
6

COM0
COM1
COM2
COM3
VSS

C7
1000pF

R34
10K

D10
HSMG-C670

SI
9

OSC1
1
OSC2
2

R7
10K
DNF

C_D

U3
S1D15100

C43
0.1uF

VCC

VDD

3
V1
4
V2
5
V3

VREG

R6
10K
DNF

C24
1000pF

C16
0.1uF

SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0

C23
1000pF

TELCO_PTT
47K

C8
1000pF

C19
2.2uF

D3_3V

R25

9_3V

5V_IN
10K

Q13
47K

5V_IN

R33
10K

R38
47K

CH_PTT

U2-7
PWR_GND

C35
1000pF
DNF

C36
1000pF
DNF

SPEAKER CONNECTOR
ESD CONTACTS
M1

Controlhead CM160/CM360 - PCB 8489714U01 / Schematics

3.1

Controlhead PCB 8489714U01 Parts
List

Circuit
Ref

Motorola
Part No

Description

4-8

Circuit
Ref

Motorola
Part No

Description

Circuit
Ref

Motorola
Part No

Description

Circuit
Ref

Motorola
Part No

Description

C44

NOTPLACED CAP, 220pF

J102

0908353Y02

CONN_J

R29

0662057A81

RES, 22K

C45

NOTPLACED CAP, 220pF

J103

0989241U02

CONN_J

R30

NOTPLACED RES, 10K

C46

NOTPLACED CAP, 220pF

7588823L03

CONTACT

R31

0662057A76

RES, 13K

NOTPLACED CAP, 220pF

7588823L03

CONTACT

R33

0662057A73

RES, 10K

NOTPLACED CAP, 10uF

C47

2113740F67

CAP, 470pF

C48

NOTPLACED CAP, 220pF

7588823L03

CONTACT

R34

0662057A73

RES, 10K

2113740F67

CAP, 470pF

7588823L03

CONTACT

R35

0662057A61

RES, 3.3K

2113740F67

CAP, 470pF

C49

2113740F12

CAP CHIP REEL CL1 +/-30 12

C50

2113740F67

CAP, 470pF

P101

2809926G01

CONN_P

R36

0662057A89

RES, 47K

2113740F67

CAP, 470pF

C51

2113740F12

CAP CHIP REEL CL1 +/-30 12

4809940E02

DTC114YE

R37

0662057A89

RES, 47K

2113740F12

CAP CHIP REEL CL1 +/-30 12

C52

2113740F67

CAP, 470pF

4809940E02

DTC114YE

R38

0662057A89

RES, 47K

2113741F25

CAP, 1000pF

C53

2113740F12

CAP CHIP REEL CL1 +/-30 12

Q10

4809940E02

DTC114YE

R39

0662057A73

RES, 10K

2113741F25

CAP, 1000pF

C54

2113740F67

CAP, 470pF

Q11

4809940E02

DTC114YE

R40

0662057A73

RES, 10K

C11

2113743K15

CAP, 0.1uF

C55

NOTPLACED CAP, 220pF

Q12

4813824B01

PZT2222A

R41

0662057A73

RES, 10K

C14

NOTPLACED CAP, 0.1uF

C56

2113743K15

CAP, 0.1uF

Q13

4809940E02

DTC114YE

R42

NOTPLACED RES, 0

C15

2113743K15

CAP, 0.1uF

C58

2113743E07

CAP, .022uF

Q14

4813824A10

MMBT3904

R43

NOTPLACED RES, 0

C16

2113743K15

CAP, 0.1uF

4805729G75

HSMG-C670

Q41

4809940E02

DTC114YE

R44

NOTPLACED RES, 20K

C17

NOTPLACED CAP, 1000pF

4805729G75

HSMG-C670

0662057A01

RES, 10

R45

0662057B47

C18

2113743K15

CAP, 0.1uF

4805729G75

HSMG-C670

NOTPLACED RES, 10K

R46

NOTPLACED RES, 22K

C19

2113743F18

CAP, 2.2uF

4805729G75

HSMG-C670

NOTPLACED RES, 10K

R48

NOTPLACED RES, 20K

C20

NOTPLACED CAP, 2.2uF

4805729G75

HSMG-C670

NOTPLACED RES, 10K

R49

0662057B47

C21

NOTPLACED CAPP, 4.7uF

4805729G75

HSMG-C670

0662057B47

RES, 0

R50

NOTPLACED RES, 22K

C22

2113743K15

CAP, 0.1uF

D10

4805729G75

HSMG-C670

R10

NOTPLACED RES, 0

R51

0662057A88

RES, 43K

4805729G75

HSMG-C670

R11

0662057B01

RES, 130K

R54

0662057A76

RES, 13K

RES, 0

C23

2113741F25

CAP, 1000pF

D11

C24

2113741F25

CAP, 1000pF

D12

4805729G75

HSMG-C670

R12

0662057A90

RES, 51K

NOTPLACED TOUCH_SW

C25

NOTPLACED CAP, 1000pF

D13

4805729G75

HSMG-C670

R13

0662057A90

RES, 51K

NOTPLACED TOUCH_SW

C26

2113741F25

CAP, 1000pF

D14

4805729G75

HSMG-C670

R14

0662057A73

RES, 10K

NOTPLACED TOUCH_SW

C27

2113740F12

CAP CHIP REEL CL1 +/-30 12

D15

4805729G75

HSMG-C670

R15

NOTPLACED RES, 10K

NOTPLACED TOUCH_SW

C29

2113740F12

CAP CHIP REEL CL1 +/-30 12

D16

4805729G75

HSMG-C670

R16

0662057A83

RES, 27K

NOTPLACED TOUCH_SW

C30

NOTPLACED CAP, 100pF

D17

4805729G75

HSMG-C670

R17

0662057A76

RES, 13K

NOTPLACED TOUCH_SW

C32

NOTPLACED CAP, 100pF

D18

4805729G73

HSMY-C670

R18

0662057A49

RES, 1K

5113818A01

LM2904

C33

NOTPLACED CAP, 100pF

D19

4805729G74

HSMH-C670

R19

0662057A73

RES, 10K

5113805A05

MC74HCT04A

C34

2113740F12

D20

4805729G75

HSMG-C670

R20

NOTPLACED RES, 10K

5102109U01

S1D15100

C35

NOTPLACED CAP, 1000pF

D21

4805729G75

HSMG-C670

R21

0662057A63

RES, 3.9K

5113805A75

MC74HC595A

C36

NOTPLACED CAP, 1000pF

D22

4805729G75

HSMG-C670

R22

0662057A45

RES, 680

U18

NOTPLACED LP2951C

C38

NOTPLACED CAP, 1000pF

D23

4805729G75

HSMG-C670

R23

0662057A45

RES, 680

U41

5184704M60

HEF4053B

C39

NOTPLACED CAP, 1000pF

D24

4805729G75

HSMG-C670

R24

0662057A57

RES, 2.2K

VR1

4813830A75

MMBZ20VAL

C40

NOTPLACED CAP, 1000pF

D25

4805729G75

HSMG-C670

R25

0662057B47

RES, 0

VR2

4813830A75

MMBZ20VAL

C41

NOTPLACED CAP, 1000pF

D26

4805729G75

HSMG-C670

R26

0662057A01

RES, 10

VR3

4813830A75

MMBZ20VAL

C42

2113740F12

CAP CHIP REEL CL1 +/-30 12

D27

4805729G75

HSMG-C670

R27

0662057A01

RES, 10

VR4

4813830A75

MMBZ20VAL

C43

2113743K15

CAP, 0.1uF

DS1

NOTPLACED LCD_36PIN

R28

0662057B18

RES, 680K

CAP CHIP REEL CL1 +/-30 12

Commercial Series
CM Radios
UHF2 (438-470MHz)
Service Information

Issue: December 2003

Computer Software Copyrights
The Motorola products described in this manual may include copyrighted Motorola computer programs stored
in semiconductor memories or other media. Laws in the United States and other countries preserve for
Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or
reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer
programs contained in the Motorola products described in this manual may not be copied or reproduced in
any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola
products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license
under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive royaltyfree license to use that arises by operation of law in the sale of a product.

iii

Table of Contents
Chapter 1

MODEL CHART AND TECHNICAL SPECIFICATIONS

1.0 CM140/CM340/CM160/CM360 Model Chart .......................................................1-1
2.0 Technical Specifications ......................................................................................1-2

Chapter 2

THEORY OF OPERATION

1.0 Introduction ..........................................................................................................2-1
2.0 UHF (438-470MHz) Receiver .............................................................................2-1
2.1 Receiver Front-End .......................................................................................2-1
2.2 Receiver Back-End.........................................................................................2-2
3.0 UHF (438-470MHz) Transmitter Power Amplifier ...............................................2-2
3.1 First Power Controller Stage...........................................................................2-2
3.2 Power Controlled Driver Stage .......................................................................2-3
3.3 Final Stage......................................................................................................2-3
3.4 Directional Coupler.........................................................................................2-3
3.5 Antenna Switch...............................................................................................2-3
3.6 Harmonic Filter ...............................................................................................2-4
3.7 Power Control.................................................................................................2-4
4.0 UHF (438-470MHz) Frequency Synthesis ..........................................................2-4
4.1 Reference Oscillator .......................................................................................2-4
4.2 Fractional-N Synthesizer ................................................................................2-5
4.3 Voltage Controlled Oscillator (VCO) ...............................................................2-6
4.4 Synthesizer Operation ....................................................................................2-7
5.0 Controller Theory of Operation ............................................................................2-8
5.1 Radio Power Distribution ................................................................................2-8
5.2 Protection Devices........................................................................................ 2-10
5.3 Automatic On/Off ..........................................................................................2-10
5.4 Microprocessor Clock Synthesiser ...............................................................2-11
5.5 Serial Peripheral Interface (SPI)...................................................................2-12
5.6 SBEP Serial Interface................................................................................... 2-12
5.7 General Purpose I/O.....................................................................................2-12
5.8 Normal Microprocessor Operation................................................................2-13
5.9 Static Random Access Memory....................................................................2-14
6.0 Control Board Audio and Signalling Circuits ......................................................2-14
6.1 Audio Signalling Filter IC and Compander (ASFIC CMP) ............................2-14
7.0 Transmit Audio Circuits......................................................................................2-15
7.1 Microphone Input Path .................................................................................2-15
7.2 PTT Sensing and TX Audio Processing ....................................................... 2-16

8.0 Transmit Signalling Circuits ............................................................................... 2-17
8.1 Sub-Audio Data (PL/DPL) ............................................................................ 2-17
8.2 High Speed Data .......................................................................................... 2-18
8.3 Dual Tone Multiple Frequency (DTMF) Data ............................................... 2-18
9.0 Receive Audio Circuits....................................................................................... 2-19
9.1 Squelch Detect ............................................................................................. 2-19
9.2 Audio Processing and Digital Volume Control.............................................. 2-20
9.3 Audio Amplification Speaker (+) Speaker (-) ................................................ 2-20
9.4 Handset Audio.............................................................................................. 2-21
9.5 Filtered Audio and Flat Audio ....................................................................... 2-21
10.0 Receive Audio Circuits ..................................................................................... 2-21
10.1 Sub-Audio Data (PL/DPL) and High Speed Data Decoder .......................... 2-21
10.2 Alert Tone Circuits........................................................................................ 2-22

Chapter 3

TROUBLESHOOTING CHARTS

1.0 Troubleshooting Flow Chart for Receiver RF (Sheet 1 of 2)................................ 3-2
1.1 Troubleshooting Flow Chart for Receiver (Sheet 2 of 2) ................................ 3-3
2.0 Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3) ....................... 3-4
2.1 Troubleshooting Flow Chart for 25W Transmitter (Sheet 2 of 3) ................... 3-5
2.2 Troubleshooting Flow Chart for 25W Transmitter (Sheet 3 of 3).................... 3-6
3.0 Troubleshooting Flow Chart for Synthesizer ....................................................... 3-7
4.0 Troubleshooting Flow Chart for VCO................................................................... 3-8
5.0 Troubleshooting Flow Chart for DC Supply (Sheet 1 of 2) .................................. 3-9
5.1 Troubleshooting Flow Chart for DC Supply (Sheet 2 of 2) ........................... 3-10

Chapter 4

UHF PCB/SCHEMATICS/PARTS LISTS

1.0 Allocation of Schematics and Circuit Boards ....................................................... 4-1
1.1 UHF2 and Controller Circuits ......................................................................... 4-1
2.0 UHF2 1-25W PCB 8488978U01 (Rev. D) / Schematics...................................... 4-3
2.1 UHF2 1-25W PCB 8488978U01 (Rev. D) Parts List .................................... 4-19

Chapter 1
MODEL CHART AND TECHNICAL SPECIFICATIONS
1.0

CM140/CM340/CM160/CM360 Model Chart

CM Series UHF2 438-470MHz
Model

Description

MDM50RNC9AA2_N

CM140 438-470 MHz 1-25W 8-Ch

MDM50RNC9AN2_N

CM340 438-470 MHz 1-25W 10-Ch

MDM50RNF9AA2_N
MDM50RNF9AN2_N

CM160 438-470 MHz 1-25W 64-Ch
CM360 438-470 MHz 1-25W 100-Ch

Item
X
X
X
X
X

Description

FUE1021_

S. Tanapa UHF2 25W 8 Ch BNC

PMUE2019_

S. Tanapa UHF2 25W 10 Ch BNC

PMUE1999_

S. Tanapa UHF2 25W 64 Ch BNC

PMUE2021_

S. Tanapa UHF2 25W 100 Ch BNC

FCN6288_

Control Head

FCN5523_

Control Head

HKN4137_

Battery Power Cable

RMN50188_
HMN3596_

Mag One Microphone
Compact Microphone

X
X

GLN7324_

Low Profile Trunnion

6866546D02_

RTTE Leaflet

6866537D37_

Safety Leaflet

FLE1621AS

Servicing Kit CM140

PMUE2041AS

Servicing Kit CM340

PMUE2027AS

Servicing Kit CM160

PMUE2043AS

Servicing Kit CM360

X
X
X
X

X = Indicates one of each is required

1-2

2.0

MODEL CHART AND TECHNICAL SPECIFICATIONS

Technical Specifications
Data is specified for +25°C unless otherwise stated.
General
Specification
Frequency Range:
Frequency Stability
(-30°C to +60°C, 25°C Ref.)
Channel Capacity:

Channel Spacing:

UHF2
438-470 MHz
±2 PPM

CM140 - 8
CM340 - 10
CM160 - 64
CM360 - 100
12.5/20/25 kHz

Power Output:

1-25W

Power Supply:

13.2Vdc (10.8 - 15.6 Vdc) negative vehicle ground

Dimensions (L X W X H)
Weight:
Low power (1-25W)

118mm X 169mm X 44mm

1.02 Kg

Operating Temperature

-30 to 60 o C

Storage temperature

-40 to 80o C

Shock and Vibration

Meets MIL-STD 810-C,D&E and TIA/EIA 603

Dust

Meets MIL-STD 810-C,D&E and TIA/EIA 603

Humidity

Meets MIL-STD 810-C,D&E and TIA/EIA 603

Technical Specifications

1-3

Transmitter
Specification

UHF2

Frequency Stability:

+/- 2.5ppm

Modulation Limiting:

±2.5 kHz @ 12.5 kHz
±4.0 kHz @ 20 kHz
±5.0 kHz @ 20/25 kHz

Current Drain Transmit:

8A (25W)

FM Hum and Noise:

-35 dB@12.5 kHz
-40 dB@ 20/25 kHz

Conducted/Radiated
Emissions:

-36 dBm < 1 GHz
-30 dBm > 1 GHz

Adjacent Channel Power

-60dB @12.5,
-70dB @ 20/25kHz

Audio Response:
( 300 to 3000Hz)

+1, -3dB

Audio Distortion:
@ 1000 Hz, 60%
Rated Maximum Deviation:

3% Typical

Receiver
Specification
Sensitivity (12dBSINAD): (ETS)
Intermodulation : (ETS)
Adjacent Channel
Selectivity: (ETS)
Spurious Rejection: (ETS)
Rated Audio: (ETS) (Extended audio with 4 Ohm
speaker)
Audio Distortion @ Rated Audio:

UHF2
0.35µV (12.5kHz) 0.30µV (25kHz) Typical
>65dB
70 dB @ 25 kHz
60 dB @ 12.5 kHz
70 dB
4W Internal , 13W External
3% Typical

Hum and Noise:

-35 dB @ 12.5 kHz
-40 dB @ 20/25 kHz

Audio Response:
( 300 to 3000Hz)

+1, -3dB

Conducted Spurious
Emission per FCC Part 15:

-57 dBm <1 GHz
-47 dBm >1 GHz

*Availability subject to the laws and regulations of individual countries.

1-4

MODEL CHART AND TECHNICAL SPECIFICATIONS

Chapter 2
THEORY OF OPERATION
1.0

Introduction
This Chapter provides a detailed theory of operation for the UHF circuits in the radio. Details of the
theory of operation and trouble shooting for the the associated Controller circuits are included in this
Section of the manual.

2.0

UHF (438-470MHz) Receiver

2.1

Receiver Front-End
The received signal is applied to the radio’s antenna input connector and routed through the
harmonic filter and antenna switch. The insertion loss of the harmonic filter/antenna switch is less
than 1 dB. The signal is routed to the first filter (4-pole), which has an insertion loss of 2 dB typically.
The output of the filter is matched to the base of the LNA (Q303) that provides a 16 dB gain and a
noise figure of better than 2 dB. Current source Q301 is used to maintain the collector current of
Q303. Diode CR301 protects Q303 by clamping excessive input signals. Q303 output is applied to
the second filter (3-pole) which has an insertion loss of 1.5 dB. In Distance mode, Q304 turns on and
causes D305 to conduct, thus bypassing C322 and R337. In Local mode, the signal is routed
through C322 and R337, thus inserting 7 dB attenuation. Since the attenuator is located after the RF
amplifier, the receiver sensitivity is reduced only by 6 dB, while the overall third order input intercept
is raised.
The first mixer is a passive, double-balanced type, consisting of T300, T301 and U302. This mixer
provides all of the necessary rejection of the half-IF spurious response. High-side injection at +15
dBm is delivered to the first mixer. The mixer output is then connected to a duplex network which
matches its output to the XTAL filter input (FL300) at the IF frequency of 44.85 MHz. The duplex
network terminates into a 50 ohm resistor (R340) at all other frequencies.

Antenna
Front Filter

12.5kHzFilter
LNA

Second Filter

Mixer

4- Pole
Xtal Filter

IF Amp

25kHzFilter

First LO

25kHzFilter

IFIC

2nd LO Xtal Osc

Phase Shift
Element
Controller

Figure 2-1 UHF Receiver Block Diagram

2-2

THEORY OF OPERATION

2.2

Receiver Back End
The IF signal from the crystal filter enters the IF amplifier which provides 20 dB of gain and feeds
the IF IC at pin 1. The first IF signal at 44.85 MHz mixes with the second local oscillator (LO) at
44.395 MHz to produce the second IF at 455 kHz. The second LO uses the external crystal Y301.
The second IF signal is amplified and filtered by two external ceramic filters (FL303/FL302 for
12.5KHz channel spacing and FL304/FL301 for 25KHz channel spacing). The IF IC demodulates
the signal by means of a quadrature detector and feeds the detected audio (via pin 7) to the audio
processing circuits. At IF IC pin 5, an RSSI signal is available with a dynamic range of 70 dB.

3.0

UHF Transmitter Power Amplifier (438-470 MHz)
The radio’s 25W PA is a three-stage amplifier used to amplify the output from the VCOBIC to the
radio transmit level. All three stages utilize LDMOS technology. The gain of the first stage (U101) is
adjustable and controlled by pin 7 of U103-2 via U103-3. It is followed by an LDMOS stage Q105
and LDMOS final stage Q100.

Pin Diode
Antenna
Switch

From VCO
Controlled
Stage

Driver

PA-Final
Stage

Antenna
Harmonic
Filter
RF Jack

Coupler

Bias

Forward

A S FI C _C M P
SPI BUS

PA
PWR
SET
L oo p
C ont r ol le r
U 103 - 2

Temperature
Sense

Figure 2-2 UHF Transmitter Block Diagram
Devices U101, Q105 and Q100 are surface mounted. A metal clip ensures good thermal contact
between both the driver and final stage, and the chassis.

3.1

First Power Controller Stage
The first stage (U101) is a 20dB gain integrated circuit containing two LDMOS FET amplifier stages.
It amplifies the RF signal from the VCO (TX_INJ). The output power of stage U101 is controlled by a
DC voltage applied to pin 1 from the op-amp U103-3, pin 8. The control voltage simultaneously
varies the bias of two FET stages within U101. This biasing point determines the overall gain of
U101 and therefore its output drive level to Q105, which in turn controls the output power of the

UHF Transmitter Power Amplifier (438-470 MHz)

2-3

PA.Op-amp U103-3 monitors the drain current of U101 via resistor R122 and adjusts the bias
voltage of U101.
In receive mode, the DC voltage from RX_EN line turns on Q101, which in turn switches off the
biasing voltage to U101.

3.2

Power Controlled Driver Stage
The next stage is an LDMOS device (Q105) which provides a gain of 12dB. This device requires a
positive gate bias and a quiescent current flow for proper operation. The bias is set during transmit
mode by the drain current control op-amp U102-1, and fed to the gate of Q105 via the resistive
network R175, R147.
Op-amp U102-1 monitors the drain current of Q105 via resistors R126-8 and adjusts the bias
voltage of Q105.
In receive mode the DC voltage from RX_EN line turns on Q102, which in turn switches off the
biasing voltage to Q105.

3.3

Final Stage
The final stage is an LDMOS device (Q100) providing a gain of 12dB. This device also requires a
positive gate bias and a quiescent current flow for proper operation. The voltage of the line PA_BIAS
is set in transmit mode by the ASFIC and fed to the gate of Q100 via the resistive network R134,
R131. This bias voltage is tuned in the factory. If the transistor is replaced, the bias voltage must be
tuned using the Tuner. Care must be taken not to damage the device by exceeding the maximum
allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC supply voltage
input, B+, via L117 and L115.
A matching network consisting of C1004-5, C1008, C1021: and two striplines, transforms the
impedance to 50 ohms and feeds the directional coupler.

3.4

Directional Coupler
The directional Coupler is a microstrip printed circuit, which couples a small amount of the forward
power of the RF power from Q100.The coupled signal is rectified to an output power which is
proportional to the DC voltage rectified by diode D105; and the resulting DC voltage is routed to the
power control section to ensure that the forward power out of the radio is held to a constant value.

3.5

Antenna Switch
The antenna switch utilizes the existing dc feed (B+) to the last stage device (Q100). The basic
operation is to have both PIN diodes (D103, D104) turned on during key-up by forward biasing
them. This is achieved by pulling down the voltage at the cathode end of D104 to around 12.4V
(0.7V drop across each diode). The current through the diodes needs to be set around 100 mA to
fully open the transmit path through resistor R108. Q106 is a current source controlled by Q103
which is turned on in Tx mode by TX_EN. VR102 ensures that the voltage at resistor R107 never
exceeds 5.6V.

2-4

3.6

THEORY OF OPERATION

Harmonic Filter
Inductors L111 and L113 along with capacitors C1011, C1023, C1020 and C1016 form a low-pass
filter to attenuate harmonic energy coming from the transmitter. Resistor R150 along with L126
drains any electrostatic charges that might otherwise build up on the antenna. The harmonic filter
also prevents high level RF signals above the receiver passband from reaching the receiver circuits
to improve spurious response rejection.

3.7

Power Control
The output power is regulated by using a forward power detection control loop. A directional coupler
samples a portion of the forward and reflected RF power. The forward sampled RF is rectified by
diode D105, and the resulting DC voltage is routed to the operational amplifier U100. The error
output current is then routed to an integrator, and converted into the control voltage. This voltage
controls the bias of the pre-driver (U101 and driver (Q105) stages. The output power level is set by
way of a DAC, PWR_SET, in the audio processing IC (U504) which acts at the forward power
control loop reference.
The sampled reflected power is rectified by diode D107,The resulting DC voltage is amplified by an
operational amplifier U100 and routed to the summing junction. This detector protects the final stage
Q100 from reflected power by increasing the error current. The temperature sensor protects the
final stage Q100 from overheating by increasing the error current. A thermistor RT100 measures the
final stage Q100 temperature. The voltage divider output is routed to an operational amplifier U103
and then goes to the summing junction. The Zener Diode VR101 keeps the loop control voltage
below 5.6V and eliminates the DC current from the 9.3 regulator U501.
Two local loops for the Pre Driver (U101) and for the Driver (Q105) are used in order to stabilize the
current for each stage.
In Rx mode, the two transistors Q101 and Q102 go to saturation and shut down the transmitter by
applying ground to the Pre Driver U101 and for the Driver Q105 control.

4.0

UHF (438-470MHz) Frequency Synthesis
The synthesizer consists of a reference oscillator (Y201), low voltage Fractional-N (LVFRAC-N)
synthesizer (U200), and a voltage controlled oscillator (VCO) (U201).

4.1

Reference Oscillator
The reference oscillator is a crystal (Y201) controlled Colpitts oscillator and has a frequency of
16.8MHz. The oscillator transistor and start-up circuit are located in the LVFRAC-N (U200) while the
oscillator feedback capacitors, crystal, and tuning varactors are external. An analog-to-digital (A/D)
converter internal to the LVFRAC-N (U200) and controlled by the microprocessor via SPI sets the
voltage at the warp output of U200 pin 25. This sets the frequency of the oscillator. Consequently,
the output of the crystal Y201 is applied to U200 pin 23.
The method of temperature compensation is to apply an inverse Bechmann voltage curve, which
matches the crystal’s Bechmann curve to a varactor that constantly shifts the oscillator back on
frequency. The crystal vendor characterizes the crystal over a specified temperature range and
codes this information into a bar code that is printed on the crystal package. In production, this
crystal code is read via a 2-dimensional bar code reader and the parameters are saved.

UHF (438-470MHz) Frequency Synthesis

2-5

This oscillator is temperature compensated to an accuracy of +/-2.5 PPM from -30 to 60 degrees C.
The temperature compensation scheme is implemented by an algorithm that uses five crystal
parameters (four characterize the inverse Bechmann voltage curve and one for frequency accuracy
of the reference oscillator at 25 degrees C). This algorithm is implemented by the LVFRAC-N (U200)
at the power up of the radio.
TCXO Y200, along with its corresponding circuitry R204, R205, R210, and C2053, are not placed as
the temperature compensated crystal proved to be reliable.

4.2

Fractional-N Synthesizer
The LVFRAC-N U200 consists of a pre-scaler, programmable loop divider, control divider logic,
phase detector, charge pump, A/D converter for low frequency digital modulation, balanced
attenuator used to balance the high and low frequency analog modulation, 13V positive voltage
multiplier, serial interface for control, and a super filter for the regulated 5 volts.

DATA (U403 PIN 100)
CLOCK (U403 PIN 1)
CSX (U403 PIN 2)
MOD IN (U501 PIN 40)
+5V (U503 PIN 1)
+5V (U503 PIN 1)

7
8
9
10
13, 30

5, 20, 34, 36

REFERENCE
OSCILLATOR

23
24

VOLTAGE
MULTIPLIER

FREFOUT

CLK

GND

CEX
MODIN
VCC, DC5V

IOUT
IADAPT

VDD, DC5V

MODOUT

XTAL1

U200

XTAL2

FRACTIONAL-N
SYNTHESIZER

WARP

PREIN

LOCK

DATA

LOW VOLTAGE

VCP
VMULT2
14

43
45

LOOP
FILTER

STEERING
LINE

AUX3

AUX1 BIAS2

FREF (U504 PIN 34)

6, 22, 33, 44

3
1 (NU)

BIAS1

LOCK (U403 PIN 56)

AUX4
AUX2

SFOUT

VMULT1

VCO Bias

LO RF INJECTION

TRB

VOLTAGE
28 FILTERED 5V CONTROLLED
OSCILLATOR
40
TX RF INJECTION
(1ST STAGE OF PA)

BWSELECT

To IF
Section

PRESCALER IN

Figure 2-3 UHF Synthesizer Block Diagram

A voltage of 5V applied to the super filter input (U200, pin 30) supplies an output voltage of 4.5Vdc
(VSF) at U200, pin 28. This supplies 4.5 V to the VCO Buffer IC U201.
To generate a high voltage to supply the phase detector (charge pump) output stage at pin VCP
(U200, pin 47) while using a low voltage 3.3Vdc supply, a 13V positive voltage multiplier is used
(D200, D201, and capacitors C2024, 2025, 2026, 2055, 2027, 2001).
Output lock (U200, pin 4) provides information about the lock status of the synthesizer loop. A high
level at this output indicates a stable loop. A 16.8 MHz reference frequency is provided at U200, pin
19.

2-6

THEORY OF OPERATION

4.3

Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) consists of the VCO/Buffer IC (VCOBIC, U201), the TX and
RX tank circuits, the external RX buffer stages, and the modulation circuitry.
AUX3 (U200 Pin 2)

Prescaler Out

TRB IN
Pin 20
Rx-SW

Pin7

Tx-SW

Pin13

(U200 Pin 28)

Pin 19

U200 Pin 32

Pin 12

TX/RX/BS
Switching Network

Vcc-Superfilter
Pin3

LO RF INJECTION

Presc

U201
VCOBIC

Q200
Buffers

Low Pass
Filter

Collector/RF in

Steer Line
Voltage
(VCTRL)

Pin4

RX Tank

RX VCO
Circuit

TX VCO
Circuit

Rx
Active Bias

Pin5
Pin6

TX Tank

Pin8

Pin14

Tx
Active Bias

Pin16
Pin15

Pin10

Vcc-Logic

TX RF Injection
Attenuator

Vsens
Circuit

Pin18

(U200 Pin28)
VCC Buffers

Pin2

Pin1

Rx-I adjust

Tx-I adjust

Pins 9,11,17

(U200 Pin 28)

Figure 2-4 UHF VCO Block Diagram

The VCOBIC together with the LVFRAC-N (U200) generate the required frequencies in both
transmit and receive modes. The TRB line (U201, pin 19) determines which VCO and buffer is
enabled (high being TX output at pin 10, low being RX output at pin 8). A sample of the signal from
the enabled output is routed from U201, pin 12 (PRESC_OUT), via a low pass filter to U200, pin 32
(PREIN).
A steering line voltage between 3.0V and 10.0V at varactor D204 tunes the TX VCO through the
frequency range of 438-470MHz, and at D203 tunes the RX VCO through the frequency range of
393.15-425.15MHz.
The external RX amplifier is used to increase the output from U201, pin 9 from 3-4 dBm to the
required 15dBm for proper mixer operation. In TX mode, the modulation signal from the LVFRAC-N
(U200, pin 41) is applied to the VCO by way of the modulation circuit D205, R212, R211, C2073.

UHF (438-470MHz) Frequency Synthesis

4.4

2-7

Synthesizer Operation
The synthesizer consists of a low voltage FRAC-N IC (LVFRAC-N), reference oscillator, charge
pump circuits, loop filter circuit, and DC supply. The output signal (PRESC_OUT) of the VCOBIC
(U201, pin 12) is fed to the PREIN, pin 32 of U200 via a low pass filter which attenuates harmonics
and provides a correct input level to the LVFRAC-N in order to close the synthesizer loop.
The pre-scaler in the synthesizer (U200) is a dual modulus pre-scaler with selectable divider ratios.
The divider ratio of the pre-scaler is controlled by the loop divider, which in turn receives its inputs
via the SPI. The output of the pre-scaler is applied to the loop divider. The output of the loop divider
is connected to the phase detector, which compares the loop divider’s output signal with the
reference signal. The reference signal is generated by dividing down the signal of the reference
oscillator (Y201).
The output signal of the phase detector is a pulsed dc signal that is routed to the charge pump. The
charge pump outputs a current from U200, pin 43 (IOUT). The loop filter (consisting of R224, R217,
R234, C2074, C2075, C2077, C2078, C2079, C2080, C2028, and L205) transforms this current into
a voltage that is applied the varactor diodes D203 and D204 for RX and TX respectively. The output
frequency is determined by this control voltage. The current can be set to a value fixed in the
LVFRAC-N or to a value determined by the currents flowing into BIAS 1 (U200, pin 40) or BIAS 2
(U200, pin 39). The currents are set by the value of R200 or R206 respectively. The selection of the
three different bias sources is done by software programming.
To modulate the synthesizer loop, a two-spot modulation method is utilized via the MODIN (U200,
pin 10) input of the LVFRAC-N. The audio signal is applied to both the A/D converter (low frequency
path) and the balance attenuator (high frequency path). The A/D converter converts the low
frequency analog modulating signal into a digital code which is applied to the loop divider, thereby
causing the carrier to deviate. The balance attenuator is used to adjust the VCO’s deviation
sensitivity to high frequency modulating signals. The output of the balance attenuator is presented
at the MODOUT port of the LVFRAC-N (U200,pin 41) and connected to the VCO modulation
varactor D205.

2-8

5.0

THEORY OF OPERATION

Controller Theory of Operation
This section provides a detailed theory of operation for the radio and its components. The main
radio is a single-board design, consisting of the transmitter, receiver, and controller circuits. A
control head is connected by an extension cable. The control head contains LED indicators, a
microphone connector, buttons, and speaker.
In addition to the power cable and antenna cable, an accessory cable can be attached to a
connector on the rear of the radio. The accessory cable enables you to connect accessories to the
radio, such as an external speaker, emergency switch, foot-operated PTT, and ignition sensing, etc.

External
Microphone

To Synthesizer
Mod
Out
16.8 MHz
Reference Clock
from Synthesizer

Audio/Signaling
Architecture

Disc Audio

ASFIC_CMP

Internal
Microphone
External
Speaker

Audio
PA
Internal
Speaker

µP Clock

SPI

To RF Section
Digital
Architecture

SCI to
Accessory &
Control Head
Connector

RAM
EEPROM

3.3V
Regulator

HC11FL0

FLASH

Figure 2-5 Controller Block Diagram

5.1

Radio Power Distribution
Voltage distribution is provided by five separate devices:
■

U514 P-cH FET - Batt + (Ext_SWB+)

■

U501 LM2941T - 9.3V

■

U503 LP2951CM - 5V

■

U508 MC 33269DTRK - 3.3V

■

U510 LP2986ILDX - 3.3V Digital

Handset

Controller Theory of Operation

2-9

The DC voltage applied to connector P2 supplies power directly to the following circuitry:
■

Electronic on/off control

■

RF power amplifier

■

12 volts P-cH FET -U514

■

9.3 volt regulator

■

Audio PA

Ignition

Auto
On/Off
Switch
Control

B+

Control Head
RF_PA
Audio_PA

Mic Connector

Ferrite Bit
Filt_B+

Antenna Switch
Power Control

500mA

FET
P-CH
On/Off
Control

SW_Filt_B+

11-16.6V
0.9A

Status LEDs

7_Seg

7_Seg
DOT

Bed
to
7-Seg

Back
light

Shift
Reg

Acces Conn
Audio PA_Soutdown
Power Loop Op_Amp
9.3V
65mA

U501
9.3V Regulator

Keypad

Mic Bias
9V, 5mA

0.85A

Reset

9.3V
45mA

On/Off
Control

U503
5V RF Regulator
500mA
Rx_Amp
PA_Pre-driver
PA Driver

3.2V
72mA

45mA
LVFRAC_N
IF_Amp

9.3V
75mA

9.3V
162mA

U508
3.3V RF Reg
50mA

25mA
ASFIC_CMP
IFIC
RX Cct

U510
3.3V D Reg
90mA
micro P
RAM
Flash
EEPROM

Figure 2-6 DC Power Distribution Block Diagram
Regulator U501 is used to generate the 9.3 volts required by some audio circuits, the RF circuitry
and power control circuitry. Input and output capacitors are used to reduce high frequency noise.
Resistors R5001 / R5081 set the output voltage of the regulator. This regulator output is
electronically enabled by a 0 volt signal on pin 2. Q502, Q505 and R5038 are used to disable the
regulator when the radio is turned off.
Voltage regulator U510 provides 3.3 volts for the digital circuitry. Operating voltage is from the
regulated 9.3V supply. Input and output capacitors are used to reduce high frequency noise and
provide proper operation during battery transients. U510 provides a reset output that goes to 0 volts
if the regulator output goes below 3.1 volts. This is used to reset the controller to prevent improper
operation.
Voltage regulator U508 provides 3.3V for the RF circuits and ASFIC_CMP. Input and output
capacitors are used to reduce the high frequency noise and provide proper operation during battery
transients.

2-10

THEORY OF OPERATION

Voltage regulator U503 provides 5V for the RF circuits. Input and output capacitors are used to
reduce the high frequency noise and provide proper operation during battery transients.
VSTBY is used only for CM360 5-tone radios.
The voltage VSTBY, which is derived directly from the supply voltage by components R5103 and
VR502, is used to buffer the internal RAM. Capacitor C5120 allows the battery voltage to be
disconnected for a couple of seconds without losing RAM parameters. Dual diode D501 prevents
radio circuitry from discharging this capacitor. When the supply voltage is applied to the radio,
C5120 is charged via R5103 and D501.

5.2

Protection Devices
Diode VR500 acts as protection against ESD, wrong polarity of the supply voltage, and load dump.
VR692 - VR699 are for ESD protection.

5.3

Automatic On/Off
The radio can be switched ON in any one of the following three ways:

5.3.1

■

On/Off switch. (No Ignition Mode)

■

Ignition and On/Off switch (Ignition Mode)

■

Emergency

No Ignition Mode
When the radio is connected to the car battery for the first time, Q500 will be in saturation, Q503 will
cut-off, Filt_B+ will pass through R5073, D500, and S5010-pin 6 (On/Off switch). When S5010 is
ON, Filt_B+ will pass through S5010-pin5, D511, R5069, R5037 and base of Q505 and move Q505
into saturation. This pulls U501-pin2 through R5038, D502 to 0.2V and turns On U514 and U501
9.3V regulator which supplies voltage to all other regulators and consequently turns the radio on,
When U504 (ASFIC_CMP) gets 3.3V, GCB2 goes to 3.3V and holds Q505 in saturation, for soft turn
off.

5.3.2

Ignition Mode
When ignition is connected for the first time, it will force high current through Q500 collector, This
will move Q500 out of saturation and consequently Q503 will cut-off. S5010 pin 6 will get ignition
voltage through R601 (for load dump), R610, (R610 & C678 are for ESD protection), VR501,
R5074, and D500. When S5010 is ON, Filt_B+ passes through S5010-pin 5, D511, R5069, R5037
and base of Q505 and inserts Q505 into saturation. This pulls U501-pin 2 through R5038, D502 to
0.2V and turns on U514 and U501 9.3V regulator which supply voltage to all other regulators and
turns the radio on, When U504 (ASFIC_CMP) get 3.3V supply, GCB2 goes to 3.3V and holds Q505
in saturation state to allow soft turn off,
When ignition is off Q500, Q503 will stay at the same state so S5010 pin 6 will get 0V from Ignition,
Q504 goes from Sat to Cut, ONOFF_SENSE goes to 3.3V and it indicates to the radio to soft turn
itself by changing GCB2 to ‘0’ after de registration if necessary.

Controller Theory of Operation

5.3.3

2-11

Emergency Mode
The emergency switch (P1 pin 9), when engaged, grounds the base of Q506 via EMERGENCY
_ACCES_CONN. This switches Q506 to off and consequently resistor R5020 pulls the collector of
Q506 and the base of Q506 to levels above 2 volts. Transistor Q502 switches on and pulls U501
pin2 to ground level, thus turning ON the radio. When the emergency switch is released R5030 pulls
the base of Q506 up to 0.6 volts. This causes the collector of transistor Q506 to go low (0.2V),
thereby switching Q502 to off.
While the radio is switched on, the µP monitors the voltage at the emergency input on the accessory
connector via U403-pin 62. Three different conditions are distinguished: no emergency kit is
connected, emergency kit connected (unpressed), and emergency press.
If no emergency switch is connected or the connection to the emergency switch is broken, the
resistive divider R5030 / R5049 will set the voltage to about 3.14 volts (indicates no emergency kit
found via EMERGENCY_SENSE line). If an emergency switch is connected, a resistor to ground
within the emergency switch will reduce the voltage on EMERGENCY _SENSE line, and indicate to
the µP that the emergency switch is operational. An engaged emergency switch pulls line
EMERGENCY _SENSE line to ground level. Diode VR503 limits the voltage to protect the µP input.
While EMERGENCY _ACCES_CONN is low, the µP starts execution, reads that the emergency
input is active through the voltage level of µP pin 64, and sets the DC POWER ON output of the
ASFIC CMP pin 13 to a logic high. This high will keep Q505 in saturation for soft turn off.

5.4

Microprocessor Clock Synthesiser
The clock source for the µP system is generated by the ASFIC CMP (U504). Upon power-up the
synthesizer IC (FRAC-N) generates a 16.8 MHz waveform that is routed from the RF section to the
ASFIC CMP pin 34. For the main board controller the ASFIC CMP uses 16.8 MHz as a reference
input clock signal for its internal synthesizer. The ASFIC CMP, in addition to audio circuitry, has a
programmable synthesizer which can generate a synthesized signal ranging from 1200Hz to
32.769MHz in 1200Hz steps.
When power is first applied, the ASFIC CMP will generate its default 3.6864MHz CMOS square
wave UP CLK (on U504 pin 28) and this is routed to the µP (U403 pin 90). After the µP starts
operation, it reprograms the ASFIC CMP clock synthesizer to a higher UP CLK frequency (usually
7.3728 or 14.7456 MHz) and continues operation.
The ASFIC CMP may be reprogrammed to change the clock synthesizer frequencies at various
times depending on the software features that are executing. In addition, the clock frequency of the
synthesizer is changed in small amounts if there is a possibility of harmonics of the clock source
interfering with the desired radio receive frequency.
The ASFIC CMP synthesizer loop uses C5025, C5024 and R5033 to set the switching time and jitter
of the clock output. If the synthesizer cannot generate the required clock frequency it will switch
back to its default 3.6864MHz output.
Because the ASFIC CMP synthesizer and the µP system will not operate without the 16.8 MHz
reference clock it (and the voltage regulators) should be checked first when debugging the system.

2-12

5.5

THEORY OF OPERATION

Serial Peripheral Interface (SPI)
The µP communicates to many of the IC’s through its SPI port. This port consists of SPI TRANSMIT
DATA (MOSI) (U403-pin100), SPI RECEIVE DATA (MISO) (U403-pin 99), SPI CLK (U0403-pin1)
and chip select lines going to the various IC’s, connected on the SPI PORT (BUS). This BUS is a
synchronous bus, in that the timing clock signal CLK is sent while SPI data (SPI TRANSMIT DATA
or SPI RECEIVE DATA) is sent. Therefore, whenever there is activity on either SPI TRANSMIT
DATA or SPI RECEIVE DATA there should be a uniform signal on CLK. The SPI TRANSMIT DATA
is used to send serial from a µP to a device, and SPI RECEIVE DATA is used to send data from a
device to a µP.
There are two IC’s on the SPI BUS, ASFIC CMP (U504 pin 22)), and EEPROM (U400). In the RF
sections there is one IC on the SPI BUS, the FRAC-N Synthesizer. The chip select line CSX from
U403 pin 2 is shared by the ASFIC CMP and FRAC-N Synthesizer. Each of these IC’s check the
SPI data and when the sent address information matches the IC’s address, the following data is
processed.
When the µP needs to program any of these Is it brings the chip select line CSX to a logic “0” and
then sends the proper data and clock signals. The amount of data sent to the various IC’s are
different; e.g., the ASFIC CMP can receive up to 19 bytes (152 bits). After the data has been sent
the chip select line is returned to logic “1”.

5.6

SBEP Serial Interface
The SBEP serial interface allows the radio to communicate with the Customer Programming
Software (CPS), or the Universal Tuner via the Radio Interface Box (RIB) or the cable with internal
RIB. This interface connects to the SCI pin via control head connector (J2-pin 17) and to the
accessory connector P1-6 and comprises BUS+. The line is bi-directional, meaning that either the
radio or the RIB can drive the line. The µP sends serial data and it reads serial data via pin 97.
Whenever the µP detects activity on the BUS+ line, it starts communication.

5.7

General Purpose Input/Output
The controller provides six general purpose lines (PROG I/O) available on the accessory connector
P1 to interface to external options. Lines PROG IN 3 and 6 are inputs, PROG OUT 4 is an output
and PROG IN OUT 8, 12 and 14 are bi-directional. The software and the hardware configuration of
the radio model define the function of each port.
■

PROG IN 3 can be used as external PTT input, or others, set by the CPS. The µP reads this
port via pin 72 and Q412.

■

PROG OUT 4 can be used as external alarm output, set by the CPS. Transistor Q401 is
controlled by the µP (U403 pin 55)

■

PROG IN 6 can be used as normal input, set by the CPS. The µP reads this port via pin 73
and Q411. This pin is also used to communicate with the RIB if resistor R421 is placed.

■

DIG IN OUT 8,12,14 are bi-directional and use the same circuit configuration. Each port uses
an output Q416, Q404, Q405 controlled by µP pins 52, 53, 54. The input ports are read
through µP pins 74, 76, 77; using Q409, Q410, Q411

Controller Theory of Operation

5.8

2-13

Normal Microprocessor Operation
For this radio, the µP is configured to operate in one of two modes, expanded and bootstrap. In
expanded mode the µP uses external memory devices to operate, whereas in bootstrap operation
the µP uses only its internal memory. In normal operation of the radio the µP is operating in
expanded mode as described below.
During normal operation, the µP (U403) is operating in expanded mode and has access to 3
external memory devices; U400 (EEPROM), U402 (SRAM), U404 (Flash). Also, within the µP there
are 3 Kilobytes of internal RAM, as well as logic to select external memory devices.
The external EEPROM (U400) space contains the information in the radio which is customer
specific, referred to as the codeplug. This information consists of items such as: 1) what band the
radio operates in, 2) what frequencies are assigned to what channel, and 3) tuning information.
The external SRAM (U402) as well as the µP’s own internal RAM space are used for temporary
calculations required by the software during execution. All of the data stored in both of these
locations is lost when the radio powers off.
The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of 8 data
lines (DATA 0 - DATA 7). There are also 3 control lines; CSPROG (U403-38) to chip select U404-pin
30 (FLASH), CSGP2 (U403-pin 41) to chip select U404-pin 20 (SRAM) and PG7_R_W (U403-pin 4)
to select whether to read or to write. The external EEPROM (U400-pin1).
When the µP is functioning normally, the address and data lines should be toggling at CMOS logic
levels. Specifically, the logic high levels should be between 3.1 and 3.3V, and the logic low levels
should be between 0 and 0.2V. No other intermediate levels should be observed, and the rise and
fall times should be <30ns.
The low-order address lines (ADDR 0 - ADDR 7) and the data lines (DATA 0-DATA 7) should be
toggling at a high rate, e.g., you should set your oscilloscope sweep to 1us/div. or faster to observe
individual pulses. High speed CMOS transitions should also be observed on the µP control lines.
On the µP the lines XIRQ (U403-pin 48), MODA LIR (U403-pin 58), MODB VSTPY (U403-pin 57)
and RESET (U403-pin 94) should be high at all times during normal operation. Whenever a data or
address line becomes open or shorted to an adjacent line, a common symptom is that the RESET
line goes low periodically, with the period being in the order of 20ms. In the case of shorted lines you
may also detect the line periodically at an intermediate level, i.e. around 2.5V when two shorted
lines attempt to drive to opposite rails.
The MODA LIR (U403-pin 58) and MODB VSTPY (U403-pin 57) inputs to the µP must be at a logic
“1” for it to start executing correctly. After the µP starts execution it will periodically pulse these lines
to determine the desired operating mode. While the Central Processing Unit (CPU) is running,
MODA LIR is an open-drain CMOS output which goes low whenever the µP begins a new
instruction. An instruction typically requires 2-4 external bus cycles, or memory fetches.
There are eight analog-to-digital coverter ports (A/D) on U403 labelled within the device block as
PEO-PE7. These lines sense the voltage level ranging from 0 to 3.3V of the input line and convert
that level to a number ranging from 0 to 255 which is read by the software to take appropriate action.

2-14

5.9

THEORY OF OPERATION

Static Random Access Memory (SRAM)
The SRAM (U402) contains temporary radio calculations or parameters that can change very
frequently, and which are generated and stored by the software during its normal operation. The
information is lost when the radio is turned off.
The device allows an unlimited number of write cycles. SRAM accesses are indicated by the CS
signal U402 (which comes from U403-CSGP2) going low. U402 is commonly referred to as the
external RAM as opposed to the internal RAM which is the 3 Kilobytes of RAM which is part of the
68HC11FL0. Both RAM spaces serve the purpose. However, the internal RAM is used for the
calculated values which are accessed most often.
Capacitor C402 and C411 serves to filter out any AC noise which may ride on +3.3 V at U402

6.0

Control Board Audio and Signalling Circuits

6.1

Audio Signalling Filter IC and Compander (ASFIC CMP)
The ASFIC CMP (U504) used in the controller has the following four functions:
1.

RX/TX audio shaping, i.e. filtering, amplification, attenuation

RX/TX signaling, PL/DPL/HST/MDC

Squelch detection

µP clock signal generation

The ASFIC CMP is programmable through the SPI BUS (U504 pins-20/21/22), normally receiving
19 bytes. This programming sets up various paths within the ASFIC CMP to route audio and/or
signaling signals through the appropriate filtering, gain and attenuator blocks. The ASFIC CMP also
has 6 General Control Bits GCB0-5 which are CMOS level outputs and used for the following:
■

GCBO - BW Select

■

GCBI - switches the audio PA On/Off

■

GCB2 - DC Power On switches the voltage regulator (and the radio) on and off

■

GCB3 - Control on MUX U509 pin 9 to select between Low Cost Mic path to STD Mic Path

■

GCB4 - Control on MUX U509 pin 11 to select between Flat RX path to filtered RX path on the
accessory connector.

■

GCB5 - Control on MUX U509 pin 10 to select between Flat TX path mute and Flat TX path

Transmit Audio Circuits

7.0

2-15

Transmit Audio Circuits

24kOhms

U509

MIC

46
35

FLAT TX
AUDIO

MIC
INT

GCB3
MIC
EXT

U509

36
TX RTN

MUX

CONTROL HEAD
CONNECTOR

EXT MIC

44
TX SND

MUX

AUX
TX
ACCESSORY
CONNECTOR

FILTERS AND
PREEMPHASIS
MIC
ASFIC_CMP
IN
U504 LIMITER
HS SUMMER
SPLATTER
FILTER
LS SUMMER

GCB5

FLAT TX
AUDIO MUTE

VCO
ATN
ATTENUATOR

MOD IN
40

TO
RF
SECTION
(SYNTHESIZER)

Figure 2-7 Transmit Audio Paths

7.1

Microphone Input Path
The radio supports 2 distinct microphone paths known as internal (from control head J2-15) and
external mic (from accessory connector P1-2) and an auxiliary path (FLAT TX AUDIO, from
accessory connector P1-5). The microphones used for the radio require a DC biasing voltage
provided by a resistive network.
The two microphone audio input paths enter the ASFIC CMP at U504-pin 48 (external mic) and
U504-pin 46 (internal mic). The microphone is plugged into the radio control head and connected to
the audio DC via J2-pin 15. The signal is then routed via C5045 to MUX U509 that select between
two paths with different gain to support Low Cost Mic (Mic with out amplifier in it) and Standard Mic.

7.1.1

Low Cost Microphone
Hook Pin is shorted to Pin 1(9.3V) inside the Low Cost Mic, This routes 9.3V to R429, and creates
2.6V on MIC_SENSE (u.P U403-67) by Voltage Divider R429/R430. U403 senses this voltage and
sends command to ASFIC_CMP U504 to get GCB3 = ‘0’. The audio signal is routed from C5045 via
U509-5 (Z0), R5072, U507, R5026, C5091, R5014 via C5046 to U504- 46 int. mic (C5046 100nF
creates a159Hz pole with U504- 46 int mic impedance of 16Kohm).

2-16

7.1.2

THEORY OF OPERATION

Standard Microphone
Hook Pin is shorted to the hook mic inside the standard Mic, If the mic is out off hook, 3.3V is routed
to R429 via R458, D401, and it create 0.7V on MIC_SENSE (u.P U403-67) by Voltage Divider
R429/R430. U403 senses this voltage and sends command to ASFIC_CMP U504 to get GCB3 =‘1’.
The audio signal is routed from C5045 via U509-3 (Z1), R5072, U507, R5026, C5091, R5014 via
C5046 to U504- 46 int mic (C5046 100nF create a159Hz pole with U504- 46 int mic impedance of
16Kohm). 9.3VDC is routed via R5077, R5075 to J2-15, It create 4.65V with Mic Impedance. C5010
supplies AC Ground to create AC impedance of 510 Ohms via R5075. and Filter 9.3V DC mic bias
supply.
Note: The audio signal at U504-pin 46 should be approximately 12mV for 1.5kHz or 3kHz of
deviation with 12.5kHz or 25kHz channel spacing.
The external microphone signal enters the radio on accessory connector P1 pin 2 and is routed via
line EXT MIC to R5054. R5078 and R5076 provide the 9.3Vdc bias. Resistive divider R5054/ R5070
divide the input signal by 5.5 and provide input protection for the CMOS amplifier input. R5076 and
C5009 provide a 510 ohm AC path to ground that sets the input impedance for the microphone and
determines the gain based on the emitter resistor in the microphone’s amplifier circuit.
C5047 serves as a DC blocking capacitor. The audio signal at U504-pin 48 should be approximately
14mV for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.
The FLAT TX AUDIO signal from accessory connector P1-pin 5 is fed to the ASFIC CMP (U504 pin
42 through U509 pin 2 to U509 pin 15 via U506 OP-AMP circuit and C5057.
The ASFIC has an internal AGC that can control the gain in the mic audio path. The AGC can be
disabled / enabled by the µP. Another feature that can be enabled or disabled in the ASFIC is the
VOX. This circuit, along with Capacitor C5023 at U504-pin 7, provides a DC voltage that can allow
the µP to detect microphone audio. The ASFIC can also be programmed to route the microphone
audio to the speaker for public address operation.

7.2

PTT Sensing and TX Audio Processing
Internal microphone PTT is sensed by µP U403 pin 71. Radio transmits when this pin is “0” and
selects inside the ASFIC_ CMP U504 internal Mic path. When the internal Mic PTT is “0” then
external Mic PTT is grounded via D402. External Mic PTT is sensed by U403 pin 72 via Q412
circuits. The radio transmits when this pin is “0” and selects inside the ASFIC _CMP U504 External
Mic path.
Inside the ASFIC CMP, the mic audio is filtered to eliminate frequency components outside the 3003000Hz voice band, and pre-emphasized if pre-emphasis is enabled. The signal is then limited to
prevent the transmitter from over deviating. The limited mic audio is then routed through a summer,
which is used to add in signaling data, and then to a splatter filter to eliminate high frequency
spectral components that could be generated by the limiter. The audio is then routed to an
attenuator, which is tuned in the factory or the field to set the proper amount of FM deviation. The
TX audio emerges from the ASFIC CMP at U504-pin 40 MOD IN, at which point it is routed to the
RF section.

Transmit Signalling Circuits

8.0

2-17

Transmit Signalling Circuits

HS
SUMMER

MICRO
CONTROLLER

U403

19 HIGH SPEED
CLOCK IN
(HSIO)

DTMF
ENCODER

SPI
BUS

SPLATTER
FILTER

ASFIC_CMP U504

5-3-2 STATE
ENCODER

LOW SPEED
CLOCK IN
(LSIO)

PL
ENCODER

LS
SUMMER
ATTENUATOR

40
MOD IN

TO RF
SECTION
(SYNTHESIZER)

Figure 2-8 Transmit Signalling Path
From a hardware point of view, there are 3 types of signaling:
■

Sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or
signaling,

■

DTMF data for telephone communication in trunked and conventional systems, and

■

Audible signaling including MDC and high-speed trunking.

Note: All three types are supported by the hardware while the radio software determines which
signaling type is available.

8.1

Sub-Audio Data (PL/DPL)
Sub-audible data implies signaling whose bandwidth is below 300Hz. PL and DPL waveforms are
used for conventional operation and connect tones for trunked voice channel operation. The
trunking connect tone is simply a PL tone at a higher deviation level than PL in a conventional
system. Although it is referred to as “sub-audible data”, the actual frequency spectrum of these
waveforms may be as high as 250 Hz, which is audible to the human ear. However, the radio
receiver filters out any audio below 300Hz, so these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U504 (ASFIC CMP) at any one time. The
process is as follows, using the SPI BUS, the µP programs the ASFIC CMP to set up the proper lowspeed data deviation and select the PL or DPL filters. The µP then generates a square wave which
strobes the ASFIC PL / DPL encode input LSIO U504-pin 18 at twelve times the desired data rate.
For example, for a PL frequency of 103Hz, the frequency of the square wave would be 1236Hz.
This drives a tone generator inside U504 which generates a staircase approximation to a PL sine
wave or DPL data pattern. This internal waveform is then low-pass filtered and summed with voice
or data. The resulting summed waveform then appears on U504-pin 40 (MOD IN), where it is sent to
the RF board as previously described for transmit audio. A trunking connect tone would be
generated in the same manner as a PL tone.

2-18

8.2

THEORY OF OPERATION

High Speed Data
High speed data refers to the 3600 baud data waveforms, known as Inbound Signaling Words
(ISWs) used in a trunking system for high speed communication between the central controller and
the radio. To generate an ISW, the µP first programs the ASFIC CMP (U504) to the proper filter and
gain settings. It then begins strobing U504-pin 19 (HSIO) with a pulse when the data is supposed to
change states. U504’s 5-3-2 State Encoder (which is in a 2-state mode) is then fed to the postlimiter summer block and then the splatter filter. From that point it is routed through the modulation
attenuator and then out of the ASFIC CMP to the RF board. MDC is generated in much the same
way as trunking ISW. However, in some cases these signals may also pass through a data preemphasis block in the ASFIC CMP. Also these signaling schemes are based on sending a
combination of 1200 Hz and 1800 Hz tones only. Microphone audio is muted during high speed data
signaling.

8.3

Dual Tone Multiple Frequency (DTMF) Data
DTMF data is a dual tone waveform used during phone interconnect operation. It is the same type
of tones which are heard when using a “Touch Tone” telephone.
There are seven frequencies, with four in the low group (697, 770, 852, 941Hz) and three in the high
group (1209, 1336, 1477Hz). The high-group tone is generated by the µP (U403-46) strobing U50419 at six times the tone frequency for tones less than 1440Hz or twice the frequency for tones
greater than 1440Hz. The low group tone is generated by the ASFIC CMP, controlled by the µP via
SPI bus. Inside U504 the low-group and high-group tones are summed (with the amplitude of the
high group tone being approximately 2 dB greater than that of the low group tone) and then preemphasized before being routed to the summer and splatter filter. The DTMF waveform then follows
the same path as was described for high-speed data.

Receive Audio Circuits

9.0

2-19

Receive Audio Circuits
ACCESSORY
CONNECTOR
11

1
AUDIO
PA
U502
9

SPKR +

SPKR -

EXTERNAL
SPEAKER

INT
SPKR+

INT
SPKRCONTROL HEAD
CONNECTOR
19

MUTE

U509

FLT RX AUDIO

INTERNAL
SPEAKER

20
J2

HANDSET
AUDIO

U505
37

10
GCB4 U IO

43 AUX RX

URX OUT AUDIO

GCB1

VOLUME
ATTEN.

ASFIC_CMP
U504

FILTER AND
DEEMPHASIS

DISC
FROM
AUDIO
RF
SECTION
(IF IC)

2 DISC

PL FILTER
LIMITER
LIMITER, RECTIFIER
FILTER, COMPARATOR

LS IO

SQUELCH
CIRCUIT
SQ DET

CH ACT

MICRO
CONTROLLER

U403

Figure 2-9 Receive Audio Paths

9.1

Squelch Detect
The radio’s RF circuits are constantly producing an output at the discriminator (IF IC). This signal
(DISC AUDIO) is routed to the ASFIC CMP’s squelch detect circuitry input DISC (U504-pin 2). All of
the squelch detect circuitry is contained within the ASFIC CMP. Therefore from a user’s point of
view, DISC AUDIO enters the ASFIC CMP, and the ASFIC CMP produces two CMOS logic outputs
based on the result. They are CH ACT (U504-16) and SQ DET (U504-17).
The squelch signal entering the ASFIC CMP is amplified, filtered, attenuated, and rectified. It is then
sent to a comparator to produce an active high signal on CH ACT. A squelch tail circuit is used to
produce SQ DET (U504-17) from CH ACT. The state of CH ACT and SQ DET is high (logic “1”)
when carrier is detected, otherwise low (logic “0”).
CH ACT is routed to the µP pin 84 while SQ DET is routed to the µP pin 83.
SQ DET is used to determine all audio mute / unmute decisions except for Conventional Scan. In
this case CH ACT is a pre-indicator as it occurs slightly faster than SQ DET.

2-20

9.2

THEORY OF OPERATION

Audio Processing and Digital Volume Control
The receiver audio signal (DISC AUDIO) enters the controller section from the IF IC where it is.DC
coupled to ASFIC CMP via the DISC input U504-pin 2. The signal is then applied to both the audio
and the PL/DPL paths
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth
being received, an LPF filter to remove any frequency components above 3000Hz, and a HPF to
strip off any sub-audible data below 300Hz. Next, the recovered audio passes through a deemphasis filter (if it is enabled to compensate for Pre-emphasis which is used to reduce the effects
of FM noise). The IC then passes the audio through the 8-bit programmable attenuator whose level
is set depending on the value of the volume control. Finally the filtered audio signal passes through
an output buffer within the ASFIC CMP. The audio signal exits the ASFIC CMP at AUDIO output
(U504 pin 41).
The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum /
maximum settings of the attenuator are set by codeplug parameters.
Since sub-audible signaling is summed with voice information on transmit, it must be separated
from the voice information before processing. Any sub-audible signaling enters the ASFIC CMP
from the IF IC at DISC U504-2. Once inside, it goes through the PL/DPL path. The signal first
passes through one of the two low-pass filters, either the PL low-pass filter or the DPL/LST low-pass
filter. Either signal is then filtered and goes through a limiter and exits the ASFIC CMP at LSIO
(U504-pin 18). At this point, the signal will appear as a square wave version of the sub-audible
signal which the radio received. The µP U403 pin 80 will decode the signal directly to determine if it
is the tone / code which is currently active on that mode.

9.3

Audio Amplification Speaker (+) Speaker (-)
The output of the ASFIC CMP’s digital volume pot, U504-pin 41 is routed through DC blocking
capacitor C5049 to the audio PA (U502 pin 1 and 9).
The audio power amplifier has one inverted and one non-inverted output that produces the
differential audio output SPK+/SPK- (U502 pins 4 and 6)
The audio PA is enabled via the ASFIC CMP (U504-GCB1). When the base of Q501 is low, the
transistor is off and U502-pin 8 is high, using pull up resistor R5041, and the audio PA is ON. The
voltage at U502-pin 8 must be above 8.5Vdc to properly enable the device.
If the voltage is between 3.3 and 6.4V, the device will be active but has its input (U502-pins 1/9) off.
This is a mute condition which is used to prevent an audio pop when the PA is enabled.
The SPK+ and SPK- outputs of the audio PA have a DC bias which varies proportionately with B+
(U502- pin 7). B+ of 11V yields a DC offset of 5V, and B+ of 17V yields a DC offset of 8.5V. If either
of these lines is shorted to ground, it is possible that the audio PA will be damaged. SPK+ and SPKare routed to the accessory connector (P1-pin 1 and 16) and to the control head (connector J2-pins
19 and 20).

Receive Signalling Circuits

9.4

2-21

Handset Audio
Certain handheld accessories have a speaker within them which require a different voltage level
than that provided by U502. For these devices HANDSET AUDIO is available at control head
connector J2 pin18.
The received audio from the output of the ASFIC CMP’s digital volume attenuator is routed to U505
pin 2 where it is amplified. This signal is routed from the output of the op-amp U505 to J2-pin 18.
From the control head, the signal is sent directly to the microphone jack.

9.5

Filtered Audio and Flat Audio
The ASFIC CMP output audio at U504-pin 39 is filtered and de-emphasized, but has not gone
through the digital volume attenuator. From ASFIC CMP U504-pin 39 the signal is routed via R5034
through gate U509-pin 12 and AC coupled to U505-pin 6. The gate controlled by ASFIC CMP port
GCB4 selects between the filtered audio signal from the ASFIC CMP pin 39 (URXOUT) or the
unfiltered (flat) audio signal from the ASFIC CMP pin 10 (UIO). Resistors R5034 and R5021
determine the gain of op-amp UU505-pin 6 for the filtered audio while R5032 and R5021 determine
the gain for the flat Audio. The output of U505-pin 7 is then routed to P1 pin 11 via DC blocking
capacitor C5003. Note that any volume adjustment of the signal on this path must be done by the
accessory.

10.0

Receive Signalling Circuits

DATA FILTER
AND DEEMPHASIS
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF IC)

LIMITER

HSIO 19

82
44

DISC

ASFIC_CMP
U504
FILTER

LIMITER

MICRO
CONTROLLER
U403

LSIO 18

80
85

PLEAP
8

PLCAP2
25

Figure 2-10 Receive Signalling Paths

10.1

Sub-Audio Data (PL/DPL) and High Speed Data Decoder
The ASFIC CMP (U504) is used to filter and limit all received data. The data enters the ASFIC CMP
at input DISC (U504 pin 2). Inside U504 the data is filtered according to data type (HS or LS), then it
is limited to a 0-3.3V digital level. The MDC and trunking high speed data appear at U504-pin 19,
where it connects to the µP U403 pin 80.

2-22

THEORY OF OPERATION

The low speed limited data output (PL, DPL, and trunking LS) appears at U504-pin18, where it
connects to the µP U403-pin 80.
The low speed data is read by the µP at twice the frequency of the sampling waveform; a latch
configuration in the ASFIC CMP stores one bit every clock cycle. The external capacitors C5028,
and C5026 set the low frequency pole for a zero crossings detector in the limiters for PL and HS
data. The hysteresis of these limiters is programmed based on the type of received data.

10.2

Alert Tone Circuits
When the software determines that it needs to give the operator an audible feedback (for a good
key press, or for a bad key press), or radio status (trunked system busy, phone call, circuit failures),
it sends an alert tone to the speaker. It does so by sending SPI BUS data to U504 which sets up the
audio path to the speaker for alert tones. The alert tone itself can be generated in one of two ways:
internally by the ASFIC CMP, or externally using the µP and the ASFIC CMP.
The allowable internal alert tones are 304, 608, 911, and 1823Hz. In this case a code contained
within the SPI BUS load to the ASFIC CMP sets up the path and determines the tone frequency,
and at what volume level to generate the tone. (It does not have to be related to the voice volume
setting.)
For external alert tones, the µP can generate any tone within the 100-3000Hz audio band. This is
accomplished by the µP generating a square wave which enters the ASFIC CMP at U504 pin 19.
Inside the ASFIC CMP this signal is routed to the alert tone generator.
The output of the generator is summed into the audio chain just after the RX audio de-emphasis
block. Inside U504, the tone is amplified and filtered, then passed through the 8-bit digital volume
attenuator, which is typically loaded with a special value for alert tone audio. The tone exits at U504pin 41 and is routed to the audio PA like receive audio.

Chapter 3
TROUBLESHOOTING CHARTS
This section contains detailed troubleshooting flowcharts. These charts should be used as a guide in
determining the problem areas. They are not a substitute for knowledge of circuit operation and
astute troubleshooting techniques. It is advisable to refer to the related detailed circuit descriptions
in the theory of operation sections prior to troubleshooting a radio.
Most troubleshooting charts end up by pointing to an IC to replace. It is not always noted, but it is
good practice to verify supplies and grounds to the affected IC and to trace continuity to the
malfunctioning signal and related circuitry before replacing any IC. For instance, if a clock signal is
not available at a destination, continuity from the source IC should be checked before replacing the
source IC.

3-2

1.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for Receiver RF (Sheet 1 of 2)
START

Yes
Problem in 12 KHz and
25 KHz channel spacing

Go to
DC Section

9V on Yes
R310 (LNA)
OK
?

Check
RX_EN

Go to
DC Section

3V
to U301
Okay ?

Yes

Check Q306, Q300
and U403

Check Q304, D305
and U403

Go to SYN
Section

Go to
DC Section

RX_EN
ON ?

Yes

LOC_DIST
ON?

Yes

Check
LOC_DIST

Check
TPI

LO
POWER
OK ?

Yes

Check 5V
on R337

5V
Yes
(IF AMP)
OK ?

Check 3V
on R339

Go
to A

Check D301-304
Replace IF Filters( FL304, FL301)
If problem in 25 KHz spacing

Troubleshooting Flow Chart for Receiver RF (Sheet 1 of 2)

1.1

3-3

Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
From
A

3V
(IFIC -Vcc)
OK ?

Go to
DC Section

Check
the component

Antenna to Mixer
circuitry problem

Check visually
all receiver
components
installation ?

Yes

Installation
OK ?

Yes

Inject - 40dBm (CW)
to RF connector
Check Power on
C335

RF
Yes
Power
> -28 dBM?

Check Power on
C337

Replace
Q305, Q300, U302
Check passive
components

Replace
Q303, Q301
Check passive
components

No
Replace Y301

No
Go to DC Section

3V to
U301
OK?

Yes

Y301
OK
?

Yes

RF
Yes
Power
> -28 dBM?

Replace Q302, Y300
Check D301 - 304

Replace U300

Check Y301
44.395 MHz

3-4

2.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3)
START

No or too low power when keyed

Check components between
Q100 and RF output,
Antenna Switch D104, D103,
VR102 and Q106
Before replacing Q100.

>1A

Current
increase when
keyed?

>800mA & <1A

<800mA
Check PA
Stages

Yes

Control
Voltage at
TP150
>1.6V?

No
Check 9.3V
Regulator
U501, R180 &
R181

Voltage U103
pin 5 =
4.7V?

Yes
Check power settings, tuning
& components between U103
Pin 3 and ASFIC Pin 6 before
replacing ASFIC

U103 Pin 3
<2.6Vdc

Yes
Check
U103

Yes

Short U100
Pin 3 to
ground

PA Bias
Voltage@R134
>2Vdc

No
Check Forward
Power Sense
Circuit

Check PA
Stages

Yes

Voltage at
TP150 rises?

No
Check Forward
Power Sense
Circuit

Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3)

2.1

3-5

Troubleshooting Flow Chart for 25W Transmitter (Sheet 2 of 3)
Check PA
Stages

No or too low power when keyed

DC
Voltage
at Q101 & Q102
base=0?

Check Q101, Q102,
R153, R136, R165,
R122, R168 & R137

<3.5V

Yes
Check U103 before replacing U101

DC
Voltage
at U103
Pin 8

>4.5V

Check resistive network at
Pin 9 and 10 of U103
before replacing U101

3.5 to 4.5V
Measure DC Voltage at U102 Pin 1

<2V

Pin 1
Voltage

>3V

Check Q102, R139,
R155, R166, R126R128, R169, R138,
R175, R147

No
DC
Voltage
U102 Pin 3 =
8.7V

Check U403

Yes

No
DC
Voltage at
U103 Pin
10=8.9V

2-3V

Yes
Check U102 before replacing Q105
Check Final PA Stages

Check resistive network at
Pin 2 & 3 of U102 before
replacing Q105

3-6

2.2

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for 25W Transmitter (Sheet 3 of 3)
Check Final PA Stage

<2V

Check Bias Tuning,
R134, R131 & R106
before replacing
ASFIC U504

PA_Bias
Voltage at
R134

Supply Voltage

Replace Q100

2-3V
RF Voltage
after C1044
>100mV?

Check FGU

Yes

Voltage
across R122
>50mV?

Check components
between C1044 &
C1117

Check components
between C1117 &
Q105

Check components
between Q105 &
Q100

Yes

RF Voltage
Q105 gate
>250mV?

Yes

RF Voltage
Q100 gate
>3V?

Yes
Check components
between Q100 &
antenna connector

Troubleshooting Flow Chart for Synthesizer

3.0

3-7

Troubleshooting Flow Chart for Synthesizer
Start

Correct
Problem

Check D200, D201,
C2026, C2025, &
C2027

5V
at U200
pins 5, 20, 34
& 36

Visual
check of the
Board
OK?

Check 5V
Regulator
U503

YES

YES
YES
5V
at pin 6 of
D200

Is
U200 Pin 47
at = 13VDC
?

+5V
at U200
Pin’s
13 & 30
?

YES

Check
R228

Check R201

Is
U201 Pin 19
<40 mVDC in RX &
>4.5 VDC in TX?
(at VCO section)
?

Are
Waveforms
at Pins 14 & 15
triangular
?

YES
NO

Is
there a short
between Pin 47 and
Pins 14 & 15 of
U200
?

Check programming
lines between
U403 and U200
Pins 7,8 & 9

NO
YES
Remove
Shorts
Is
RF level at
U200 Pin 32
-12 < x <-25
dBm
?
YES

Replace U200

Replace
U200

YES

NO
Replace U200

YES

Check
Y201 and associated
Parts
Are
signals
at Pin’s 14 &15
of U200
?
YES

Is
U200
Pin 2 >4.5 VDC in
Tx & <40 mVDC
in Rx
?

Is
16.8MHz
signal at
U200 Pin
23?

Check 5V
Regulator
U503

YES

Is
16.8MHz
Signal at U200
Pin 19
?

If C2052, R208,C2067,
C2068, L210 are OK, then
see VCO
troubleshooting chart

Check uP U403
Troubleshooting
Chart

Do
Pins 7,8 & 9
of U200 toggle
when channel is
changed?

YES

Is
information
from mP U403
correct
?
YES

Replace U200

3-8

TROUBLESHOOTING CHARTS

4.0

Troubleshooting Flow Chart for VCO

RX VCO

Low or no RF Signal
at input to PA

Low or no RF Signal
at TP1

Visual check
of board
OK?

Correct
Problem

Visual check
of board
OK?
YES

YES
Make sure Synthesizer is
working correctly and runner
between U200 Pin 28 and
U201 Pin 14 & and is OK

4.5V DC
at U201 Pin 14 & 18
OK ?

4.5V DC
at U201 Pin 14&18
OK ?

YES

YES
35mV DC at
U201 Pin 19
OK?

TX VCO

Check runner
between U200 Pin 2
and U201 Pin 19

4.8V DC at
U201 Pin 19
OK?

YES

Is RF available
at base of Q200

YES

Are U201 Pins
13 at 4.4V
15 at 1.1V
10 at 4.5V
16 at 1.9V

Replace U201

YES

Are Q200
Base at 2.4V
Collector at 4.5V
Emitter at 1.7V

If all parts
associated
with the pins
are OK,
replace U201

YES

If all parts associated
with the pins are OK,
replace Q200

Is RF available
at C2060

If parts between
R109 & U201 Pin10
are OK, replace U201

YES

YES
Check parts to pre-driver

If all parts from collector
of Q200 to TP1 are
OK, replace Q200

Power OK but
no modulation

Audio =180mVRMS
at “-” Side of

NO
Replace R212

D205

YES

4.5VDC
at D205

YES

If R211 and R12 are OK,
then replace D205

Replace R211

Troubleshooting Flow Chart for DC Supply (1 of 2)

5.0

3-9

Troubleshooting Flow Chart for DC Supply (1 of 2)
Since the failure of a critical voltage supply might cause the radio to automatically power down,
supply voltages should first be probed with a multimeter. If all the board voltages are absent, then
the voltage test point should be retested using a rising-edge-triggered oscilloscope. If the voltage is
still absent, then another voltage should be tested using the oscilloscope. If that voltage is present,
then the original voltage supply in question is defective and requires investigation of associated
circuitry.
5V
Check VDC on
C5006

Go to 3V

Replace U503

Yes

V=5V
?

9v 1 GHz

Adjacent Channel Power

-60dB @12.5,
-70dB @ 20/25kHz

Audio Response:
( 300 to 3000Hz)

+1, -3dB

Audio Distortion:
@ 1000 Hz, 60%
Rated Maximum Deviation:

3% Typical

VHF2
0.35µV (12.5kHz) 0.30µV (25kHz) Typical
>65dB
75 dB @ 25 kHz
65 dB @ 12.5 kHz
75 dB
4W Internal , 13W External
3% Typical

Hum and Noise:

-40 dB @ 12.5 kHz
-45 dB @ 20/25 kHz

Audio Response:
( 300 to 3000Hz)

+1, -3dB

Conducted Spurious
Emission per FCC Part 15:

-57 dBm <1 GHz
-47 dBm >1 GHz

*Availability subject to the laws and regulations of individual countries.

1-4

MODEL CHART AND TECHNICAL SPECIFICATIONS

Chapter 2
THEORY OF OPERATION
1.0

Introduction
This Chapter provides a detailed theory of operation for the VHF circuits in the radio. Details of the
theory of operation and trouble shooting for the the associated Controller circuits are included in this
Section of the manual.

2.0

VHF (146-174MHz) Receiver

2.1

Antenna
Front Filter

12.5kHzFilter
LNA

Second Filter

Mixer

4- Pole
Xtal Filter

IF Amp

25kHzFilter

First LO

25kHzFilter

IFIC

2nd LO Xtal Osc

Phase Shift
Element
Controller

Figure 2-1 VHF Receiver Block Diagram

2-2

THEORY OF OPERATION

2.2

3.0

VHF Transmitter Power Amplifier (146-174 MHz)
The radio’s 25W PA is a three-stage amplifier used to amplify the output from the TX_INJ to the
antenna port. All three stages utilize LDMOS technology. The gain of the first stage (U101)and the
second stage (Q105) is adjustable and is controlled by pin 7 of U103-2 via U103-3 and U102-1. It is
followed by an LDMOS final stage Q100.

Pin Diode
Antenna
Switch

From VCO (TX_INJ)
Controlled
Stage

Driver

PA-Final
Stage

Antenna
Harmonic
Filter
RF Jack

Coupler

Bias

Forward

A S FI C _C M P
SPI BUS

PA
PWR
SET
L oo p
C ont r ol le r
U 103 - 2

Temperature
Sense

Figure 2-2 VHF Transmitter Block Diagram
Devices U101, Q105 and Q100 are surface mounted. A metal clip ensures good thermal contact
between both the driver and final stage, and the chassis.

3.1

VHF Transmitter Power Amplifier (146-174 MHz)

2-3

Op-amp U103-3 monitors the drain current of U101 via resistor R122 and adjusts the bias voltage of
U101.
In receive mode, the DC voltage from RX_EN line turns on Q101, which in turn switches off the
biasing voltage to U101.

3.2

Power Controlled Driver Stage
The next stage is an LDMOS device (Q105) which provides a gain of 12dB. This device requires a
positive gate bias and a quiescent current flow for proper operation. The bias is set during transmit
mode by the drain current control op-amp U102-1, and fed to the gate of Q105 via the resistive
network.
Op-amp U102-1 monitors the drain current of Q105 via resistors R126-7 and adjusts the bias
voltage of Q105 so that the current remains constant.
In receive mode the DC voltage from RX_EN line turns on Q102, which in turn switches off the
biasing voltage to Q105.

3.3

Final Stage
The final stage is an LDMOS device (Q100) providing a gain of 12dB. This device also requires a
positive gate bias and a quiescent current flow for proper operation. The voltage of the line PA_BIAS
is set in transmit mode by the ASFIC and fed to the gate of Q100 via the resistive network R134,
R131. This bias voltage is tuned in the factory. If the transistor is replaced, the bias voltage must be
tuned using the Tuner. Care must be taken not to damage the device by exceeding the maximum
allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC supply voltage
input, B+, via L117 and L115.
A matching network consisting of C1004-5, C1008-9, C1021, C1013, C1019, L116: and two
striplines, transforms the impedance to 50 ohms and feeds the directional coupler.

3.4

Bi-Directional Coupler
The bi-directional Coupler is a microstrip printed circuit, which couples a small amount of the
forward and reverse power of the RF power from Q100.The coupled signal is rectified to an output
power which is proportional to the DC voltage rectified by diode D105; and the resulting DC voltage
is routed to the power control section to ensure that the forward power out of the radio is held to a
constant value.

3.5

2-4

3.6

THEORY OF OPERATION

Harmonic Filter
Inductors L111, L112 and L113 along with capacitors C1011, C1024, C1025, C1022, C1020, C1016,
C1017 and C1026 form a low-pass filter to attenuate harmonic energy coming from the transmitter.
Resistor R150 along with L126 drains any electrostatic charges that might otherwise build up on the
antenna. The harmonic filter also prevents high level RF signals above the receiver passband from
reaching the receiver circuits to improve spurious response rejection.

3.7

Power Control
The output power is regulated by using a forward power detection control loop. A directional coupler
samples a portion of the forward and reflected RF power. The forward sampled RF is rectified by
diode D105, and the resulting DC voltage is routed to the operational amplifier U100. The error
output current is then routed to an integrator, and converted into the control voltage. This voltage
controls the bias of the pre-driver (U101) and driver (Q105) stages. The output power level is set by
way of a DAC, PWR_SET, in the audio processing IC (U504), which acts at the forward power
control loop reference.
The sampled reflected power is rectified by diode D107,The resulting DC voltage is amplified by an
operational amplifier U100 and routed to the summing junction. This detector protects the final stage
Q100 from reflected power by increasing the error current. The temperature sensor protects the
final stage Q100 from overheating by increasing the error current. A thermistor RT100 measures the
final stage Q100 temperature. The voltage divider output is routed to an operational amplifier U103
and then goes to the summing junction. The Zener Diode VR101 keeps the loop control voltage
below 5.6V and eliminates the DC current from the 9.3 regulator U501.
Two local loops for the Pre Driver (U101) and for the Driver (Q105) are used in order to stabilize the
current for each stage.
In Rx mode, the two transistors Q101 and Q102 go to saturation and shut down the transmitter by
applying ground to the Pre Driver U101 and for the Driver Q105 control.

4.0

VHF (146-174MHz) Frequency Synthesis
The synthesizer consists of a reference oscillator (Y201), low voltage Fractional-N (LVFRAC-N)
synthesizer (U200), and a voltage controlled oscillator (VCO) (U201).

4.1

VHF (146-174MHz) Frequency Synthesis

2-5

4.2

DATA (U403 PIN 100)
CLOCK (U403 PIN 1)
CSX (U403 PIN 2)
MOD IN (U501 PIN 40)
+5V (U503 PIN 1)
+5V (U503 PIN 1)

7
8
9
10
13, 30

5, 20, 34, 36

REFERENCE
OSCILLATOR

23
24

VOLTAGE
MULTIPLIER

FREFOUT

CLK

GND

CEX
MODIN
VCC, DC5V

IOUT
IADAPT

VDD, DC5V

MODOUT

XTAL1

U200

XTAL2

FRACTIONAL-N
SYNTHESIZER

WARP

PREIN

LOCK

DATA

LOW VOLTAGE

VCP
VMULT2
14

43
45

LOOP
FILTER

STEERING
LINE

AUX3

AUX1 BIAS2

FREF (U504 PIN 34)

6, 22, 33, 44

3
1

BIAS1

LOCK (U403 PIN 56)

AUX4
AUX2

SFOUT

VMULT1

VCO Bias

LO RF INJECTION

TRB

VOLTAGE
28 FILTERED 5V CONTROLLED
OSCILLATOR
40
TX RF INJECTION
(1ST STAGE OF PA)

BWSELECT

To IF
Section

PRESCALER IN

Figure 2-3 VHF Synthesizer Block Diagram

2-6

THEORY OF OPERATION

4.3

Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) consists of the VCO/Buffer IC (VCOBIC, U201), the TX and
RX tank circuits, the external RX amplifier, and the modulation circuitry.
AUX3 (U200 Pin 2)

Prescaler Out

TRB IN
Pin 20
Rx-SW

Pin7

Tx-SW

Pin13

(U200 Pin 28)

Pin 19

U200 Pin 32

Pin 12

TX/RX/BS
Switching Network

Vcc-Superfilter
Pin3

LO RF INJECTION

Presc

U201
VCOBIC

Q200
Buffer

Low Pass
Filter

Collector/RF in

Steer Line
Voltage
(VCTRL)

Pin4

RX Tank

RX VCO
Circuit

TX VCO
Circuit

Rx
Active Bias

Pin5
Pin6

TX Tank

Pin8

Pin14

Tx
Active Bias

Pin16
Pin15

Pin10

Vcc-Logic

TX RF Injection
Attenuator

Vsens
Circuit

Pin18

(U200 Pin28)
VCC Buffers

Pin2

Pin1

Rx-I adjust

Tx-I adjust

Pins 9,11,17

(U200 Pin 28)

Figure 2-4 VHF VCO Block Diagram

The VCOBIC together with the LVFRAC-N (U200) generate the required frequencies in both
transmit and receive modes. The TRB line (U201, pin 19) determines which VCO and buffer is
enabled (high being TX output at pin 10, low being RX output at pin 8). A sample of the signal from
the enabled output is routed from U201, pin 12 (PRESC_OUT), via a low pass filter to U200, pin 32
(PREIN).
A steering line voltage between 3.0V and 10.0V at varactor D204 tunes the TX VCO through the
frequency range of 146-174MHz, and at D203 tunes the RX VCO through the frequency range of
190-219MHz.
The external RX amplifier is used to increase the output from U201, pin 9 from 3-4 dBm to the
required 15dBm for proper mixer operation. In TX mode, the modulation signal from the LVFRAC-N
(U200, pin 41) is applied to the VCO by way of the modulation circuit D205, R212, R211, C2073.

VHF (146-174MHz) Frequency Synthesis

4.4

2-7

2-8

5.0

THEORY OF OPERATION

External
Microphone

To Synthesizer
Mod
Out
16.8 MHz
Reference Clock
from Synthesizer

Audio/Signaling
Architecture

Disc Audio

ASFIC_CMP

Internal
Microphone
External
Speaker

Audio
PA
Internal
Speaker

µP Clock

SPI

To RF Section
Digital
Architecture

SCI to
Accessory &
Control Head
Connector

RAM
EEPROM

3.3V
Regulator

HC11FL0

FLASH

Figure 2-5 Controller Block Diagram

5.1

Radio Power Distribution
Voltage distribution is provided by five separate devices:
■

U514 P-cH FET - Batt + (Ext_SWB+)

■

U501 LM2941T - 9.3V

■

U503 LP2951CM - 5V

■

U508 MC 33269DTRK - 3.3V

■

U510 LP2986ILDX - 3.3V Digital

Handset

Controller Theory of Operation

2-9

The DC voltage applied to connector P2 supplies power directly to the following circuitry:
■

Electronic on/off control

■

RF power amplifier

■

12 volts P-cH FET -U514

■

9.3 volt regulator

■

Audio PA

Ignition

Auto
On/Off
Switch
Control

B+

Control Head
RF_PA
Audio_PA

Mic Connector

Ferrite Bit
Filt_B+

Antenna Switch
Power Control

500mA

FET
P-CH
On/Off
Control

SW_Filt_B+

11-16.6V
0.9A

Status LEDs

7_Seg

7_Seg
DOT

Bed
to
7-Seg

Back
light

Shift
Reg

Acces Conn
Audio PA_Soutdown
Power Loop Op_Amp
9.3V
65mA

U501
9.3V Regulator

Keypad

Mic Bias
9V, 5mA

0.85A

Reset

9.3V
45mA

On/Off
Control

U503
5V RF Regulator
500mA
Rx_Amp
PA_Pre-driver
PA Driver

3.2V
72mA

45mA
LVFRAC_N
IF_Amp

9.3V
75mA

9.3V
162mA

U508
3.3V RF Reg
50mA

25mA
ASFIC_CMP
IFIC
RX Cct

U510
3.3V D Reg
90mA
micro P
RAM
Flash
EEPROM

2-10

THEORY OF OPERATION

5.2

Protection Devices
Diode VR500 acts as protection against ESD, wrong polarity of the supply voltage, and load dump.
VR692 - VR699 are for ESD protection.

5.3

Automatic On/Off
The radio can be switched ON in any one of the following three ways:

5.3.1

■

On/Off switch. (No Ignition Mode)

■

Ignition and On/Off switch (Ignition Mode)

■

Emergency

5.3.2

Controller Theory of Operation

5.3.3

2-11

5.4

2-12

5.5

THEORY OF OPERATION

5.6

5.7

PROG IN 3 can be used as external PTT input, or others, set by the CPS. The µP reads this
port via pin 72 and Q412.

■

PROG OUT 4 can be used as external alarm output, set by the CPS. Transistor Q401 is
controlled by the µP (U403 pin 55)

■

PROG IN 6 can be used as normal input, set by the CPS. The µP reads this port via pin 73
and Q411. This pin is also used to communicate with the RIB if resistor R421 is placed.

■

Controller Theory of Operation

5.8

2-13

2-14

5.9

THEORY OF OPERATION

6.0

Control Board Audio and Signalling Circuits

6.1

Audio Signalling Filter IC and Compander (ASFIC CMP)
The ASFIC CMP (U504) used in the controller has the following four functions:
1.

RX/TX audio shaping, i.e. filtering, amplification, attenuation

RX/TX signaling, PL/DPL/HST/MDC

Squelch detection

µP clock signal generation

GCBO - BW Select

■

GCBI - switches the audio PA On/Off

■

GCB2 - DC Power On switches the voltage regulator (and the radio) on and off

■

GCB3 - Control on MUX U509 pin 9 to select between Low Cost Mic path to STD Mic Path

■

GCB4 - Control on MUX U509 pin 11 to select between Flat RX path to filtered RX path on the
accessory connector.

■

GCB5 - Control on MUX U509 pin 10 to select between Flat TX path mute and Flat TX path

Transmit Audio Circuits

7.0

2-15

Transmit Audio Circuits

24kOhms

U509

MIC

46
35

FLAT TX
AUDIO

MIC
INT

GCB3
MIC
EXT

U509

36
TX RTN

MUX

CONTROL HEAD
CONNECTOR

EXT MIC

44
TX SND

MUX

AUX
TX
ACCESSORY
CONNECTOR

FILTERS AND
PREEMPHASIS
MIC
ASFIC_CMP
IN
U504 LIMITER
HS SUMMER
SPLATTER
FILTER
LS SUMMER

GCB5

FLAT TX
AUDIO MUTE

VCO
ATN
ATTENUATOR

MOD IN
40

TO
RF
SECTION
(SYNTHESIZER)

Figure 2-7 Transmit Audio Paths

7.1

7.1.1

2-16

7.1.2

THEORY OF OPERATION

7.2

Transmit Signalling Circuits

8.0

2-17

Transmit Signalling Circuits

HS
SUMMER

MICRO
CONTROLLER

U403

19 HIGH SPEED
CLOCK IN
(HSIO)

DTMF
ENCODER

SPI
BUS

SPLATTER
FILTER

ASFIC_CMP U504

5-3-2 STATE
ENCODER

LOW SPEED
CLOCK IN
(LSIO)

PL
ENCODER

LS
SUMMER
ATTENUATOR

40
MOD IN

TO RF
SECTION
(SYNTHESIZER)

Figure 2-8 Transmit Signalling Path
From a hardware point of view, there are 3 types of signaling:
■

Sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or
signaling,

■

DTMF data for telephone communication in trunked and conventional systems, and

■

Audible signaling including MDC and high-speed trunking.

Note: All three types are supported by the hardware while the radio software determines which
signaling type is available.

8.1

2-18

8.2

THEORY OF OPERATION

8.3

Receive Audio Circuits

9.0

2-19

Receive Audio Circuits
ACCESSORY
CONNECTOR
11

1
AUDIO
PA
U502
9

SPKR +

SPKR -

EXTERNAL
SPEAKER

INT
SPKR+

INT
SPKRCONTROL HEAD
CONNECTOR
19

MUTE

U509

FLT RX AUDIO

INTERNAL
SPEAKER

20
J2

HANDSET
AUDIO

U505
37

10
GCB4 U IO

43 AUX RX

URX OUT AUDIO

GCB1

VOLUME
ATTEN.

ASFIC_CMP
U504

FILTER AND
DEEMPHASIS

DISC
FROM
AUDIO
RF
SECTION
(IF IC)

2 DISC

PL FILTER
LIMITER
LIMITER, RECTIFIER
FILTER, COMPARATOR

LS IO

SQUELCH
CIRCUIT
SQ DET

CH ACT

MICRO
CONTROLLER

U403

Figure 2-9 Receive Audio Paths

9.1

2-20

9.2

THEORY OF OPERATION

9.3

Receive Signalling Circuits

9.4

2-21

9.5

10.0

Receive Signalling Circuits

DATA FILTER
AND DEEMPHASIS
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF IC)

LIMITER

HSIO 19

82
44

DISC

ASFIC_CMP
U504
FILTER

LIMITER

MICRO
CONTROLLER
U403

LSIO 18

80
85

PLEAP
8

PLCAP2
25

Figure 2-10 Receive Signalling Paths

10.1

2-22

THEORY OF OPERATION

10.2

3-2

1.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for Receiver RF (Sheet 1 of 2)
START

Yes
Problem in 12 KHz and
25 KHz channel spacing

Go to
DC Section

9V on Yes
R310 (LNA)
OK?

Check
RX_EN

Go to
DC Section

3V
to U301
Okay ?

Yes

Check Q306, Q300
and U403

Check Q304, D305
and U403

Go to SYN
Section

Go to
DC Section

RX_EN
ON ?

Yes

LOC_DIST
ON?

Yes

Check
LOC_DIST

Check
TPI

LO
POWER
OK ?

Yes

Check 5V
on R336

5V
Yes
(IF AMP)
OK ?

Check 3V
on R339

Go
to A

Check D301-304
Replace IF Filters( FL304, FL301)
If problem in 25 KHz spacing

Troubleshooting Flow Chart for Receiver RF (Sheet 1 of 2)

1.1

3-3

Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
From
A

3V
(IFIC -Vcc)
OK ?

Go to
DC Section

Check
the component

Antenna to Mixer
circuitry problem

Check visually
all receiver
components
installation ?

Yes

Installation
OK ?

Yes

Inject - 40dBm (CW)
to RF connector
Check Power on
C332

RF
Yes
Power
> -28 dBM?

Check Power on
C336

Replace
Q305, Q300, U302
Check passive
components

Replace
Q303, Q301
Check passive
components

No
Replace Y301

No
Go to DC Section

3V to
U301
OK?

Yes

Y301
OK?

Yes

RF
Yes
Power
> -28 dBM?

Replace Q302, Y300
Check D301 - 304

Replace U300

Check Y301
44.395 MHz

3-4

2.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3)
START

No or too low power when keyed

Check components between
Q100 and RF output,
Antenna Switch D104,
D103, VR102 and Q106 before replacing Q100

>1.0A

Current
increase when
keyed?

>430mA & <1.0A

<500mA
Check PA
Stages

Yes
>1.5V

Control
Voltage at
TP150
=1.5V?

No
Check 9.3V
Regulator
U501

Voltage U103
pin 5 =
4.7V?

Yes
Check power settings, tuning
& components between U103
Pin 3 and ASFIC Pin 6 before
replacing ASFIC

U103 Pin 3
<2.6V

Yes
Check
U103

Yes

Short U100
Pin 3 to
ground

U100 Pin 3
>2Vdc

No
Check forward
Power Sense
Circuit

Check PA
Stages

Yes

Voltage at
TP150 rises?

No
Check Forward
Power Sense
Circuit

Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3)

2.1

3-5

Troubleshooting Flow Chart for 25W Transmitter (Sheet 2 of 3)
Check PA
Stages

No or too low power when keyed

DC
Voltage
at Q101 & Q102
base=0?

Check Q101,
R153,R136, R165,
R122, R168, R137

Check U403

Yes

No
DC
Voltage at
U103 Pin
10=8.8V

<2V

Yes

DC
Voltage
at U103
Pin 8

>5V

Check resistive network at
Pin 9 and 10 of U103
before replacing U101

2-5V

Check U103 and Resistive
Network at Pin 10 of U103
before replacing U101

Measure DC Voltage at U102 Pin 1 2.3V

Pin 1
Voltage
at U102

>3V

Check Q102, R139,
R155, R166, R126,
R127, R169, R138,
R175, R147

No
<2V

2-3V

U102 Pin 3 =
8.8V

Yes
Check U102 before replacing Q105
Check Final PA Stages

Check resistance network
at pin 1, 2, 3 of U102 before
replacing Q105

3-6

2.2

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for 25W Transmitter (Sheet 3 of 3)
Check Final PA Stage

<2V

Check Bias Tuning
R134, R131, R106
before replacing
ASFIC U504

PA_Bias
Voltage at
R134
2.1V

Supply Voltage

Replace Q100

2-3V
RF Voltage
after C1044 >100mV?

Check FGU

Yes

Voltage
across R122
>50mV?

Check components
between C1044 &
C1117

Check components
between C1117 &
Q105

Check components
between Q105 &
Q100

Yes

RF Voltage
Q105 gate
>100mV?

Yes

RF Voltage
Q100 gate
>1.5V?

Yes
Check components
between Q100 &
antenna connector

Troubleshooting Flow Chart for Synthesizer

3.0

3-7

Troubleshooting Flow Chart for Synthesizer

5V at
U200 pins 5,
20, 34 & 36

Start

Check 5V
Regulator
U503

Yes
No

Correct
Problem

Visual
check of the
Board OK?
Yes

Yes

5V
at pin 6 of
D200

Yes

Is U200
Pin 47
= 13VDC?

+5V at
U200 Pins
13 & 30?

Is 16.8MHz
Signal at
U200 Pin 19?

Is
16.8MHz
signal at
U200 pin
23?

Yes

Yes
Replace
U200

Yes
Check
Y201 and associated
parts

Check 5V
Regulator
U503

Check
R228

Is U201 Pin 19
<40 mVDC in RX &
>4.5 VDC in TX?
(at VCO section)

Are signals
at Pins 14 &
15 of U200?

Yes

Are Waveforms
at Pins 14 & 15
triangular?

Yes

Is U200 pin 2
>4.5 VDC in Tx &
<40 mVDC in Rx

Check D200, D201,
C2026, C2025,
C2024 & C2027

Yes

Check R201

Replace U200

Is there a short
between Pin 47 and
Pins 14 & 15 of
U200?
Yes

Is RF level at
U200 Pin 32
-12 < x <-25
dBm?

Yes

Replace
U200

If C2052, R208, C2067
C2068. C210, are OK, then
see VCO
troubleshooting chart

Check programming
lines between U403
and U200 Pins 7,8 & 9

Remove
Shorts

Check µP U403
Troubleshooting
Chart

Do Pins
7,8 & 9 of
U200 toggle
when channel is
changed?

Yes

Is information
from µP U403
correct?
Yes

Replace U200

3-8

TROUBLESHOOTING CHARTS

4.0

Troubleshooting Flow Chart for VCO

RX VCO

Low or no RF Signal
at input to PA

Low or no RF Signal
at TP1

Visual check
of board
OK?

Correct
Problem

Make sure U508 is working
correctly and runner
between U508 Pin 1 and
U201 Pin 14 & 18 is OK

Make sure Synthesizer is
working correctly and runner
between U200 Pin 28 and
U201 Pin 3 is OK

Check runner
between U200 Pin 2
and U201 Pin 19

YES

Are Q200
Base at 2.4V
Collector at 4.5V
Emitter at 1.7V

4.8V DC at
U201 Pin 19
OK?
YES

If all parts associated
with the pins are OK

Are U201 Pins
13 at 4.4V
15 at 1.1V
10 at 4.5V
16 at 1.9V

If all parts
associated
with the pins
are OK,
replace U201

YES

If L216, C2071, C2070,

Check 9V at R230

Is RF available
at C2060

YES

C2060 are okay
replace U201

YES

Is RF available
at base of Q200

Check Transmiiter
Pre Driver

YES

Check parts between
TP1 and Q200

4.5V DC at
U201 Pin 3 OK?
YES

YES
35mV DC at
U201 Pin 19
OK?

5V DC at U201
Pin 14 & 18 OK?

YES

YES
4.5V DC at
U201 Pin 3 OK?

Visual check
of board
OK?
YES

YES
3.3 DC at U201
Pin 14 & 18 OK?

TX VCO

If all parts from U200 Pin 8
to Base of Q200 are OK,
replace U200

Power OK but
no modulation

Audio =180mVrms
at “+” side of
D205

Replace R212

YES

2.5VDC
at D205

YES

If R211 is Ok,
replace D205

NO
Replace R211

Troubleshooting Flow Chart for DC Supply (1 of 2)

5.0

3-9

Go to 3V

Replace U503

Yes

V=5V
?

9v 1 GHz

Adjacent Channel Power

-60dB @12.5,
-70dB @ 20/25kHz

Audio Response:
( 300 to 3000Hz)

+1, -3dB

Audio Distortion:
@ 1000 Hz, 60%
Rated Maximum Deviation:

3% Typical

Midband
0.35µV (12.5kHz) 0.30µV (25kHz) Typical
>65dB
70 dB @ 25 kHz
60 dB @ 12.5 kHz
70 dB
4W Internal , 13W External
3% Typical

Hum and Noise:

-40 dB @ 12.5 kHz
-45 dB @ 20/25 kHz

Audio Response:
( 300 to 3000Hz)

+1, -3dB

Conducted Spurious
Emission per FCC Part 15:

-57 dBm <1 GHz
-47 dBm >1 GHz

*Availability subject to the laws and regulations of individual countries.

1-4

MODEL CHART AND TECHNICAL SPECIFICATIONS

Chapter 2
THEORY OF OPERATION
1.0

Introduction
This Chapter provides a detailed theory of operation for the Midband circuits in the radio. Details of
the theory of operation and trouble shooting for the the associated Controller circuits are included in
this Section of the manual.

2.0

Midband (66-88MHz) Receiver

2.1

Receiver Front-End
The received signal from the antenna connector is filtered by the harmonic filter (common to both
receive and transmit) and routed to the front end via the antenna switch. The signal is routed to 2pole pre-selector filter tuned by a dual varacter diode D2301, and on to the LNA, Q2301. This is
followed by a 3dB attenuator and a 2-pole post selector filter, tuned by varactor D2304. The varactor
control voltage is generated by a DAC in the ASFIC (U504-6). An inverting op-amp stage (U517)
amplifies the control signal to provide 0-8V. Signal RX_FE_TUNE voltage is increased under
software control for higher receive frequencies. Note that the same DAC is used to control the
transmitter power. The 9V supply to the LNA (Q2301) is turned on by Q4 when RX_EN is high.
Q2302 controls the biasing so that Q2301 is operated with a constant collector current (15mA).
In Local Mode, attenuator R38 improves the intermodulation performance prior to the first mixer. In
Distance Mode, normal operation, R38 is bypassed by diode D1, which is forward biassed by Q1
turning on when the LOC_DIST line from the microprocessor (U403-45) is high.
The first mixer is a passive, double-balanced type, consisting of T1, T2 and U1. This mixer provides
all of the necessary rejection of the half-IF spurious response. High-side injection at +15 dBm is
delivered to the first mixer. The mixer output is then connected to a duplex network which matches
its output to the XTAL filter input (FL2201) at the IF frequency of 21.4 MHz. The duplex network
terminates into a 50 ohm resistor (R41) at all other frequencies.

Antenna
Front Filter

RX_FE_TUNE

12.5kHzFilter 12.5kHzFilter
LNA

Second Filter

Mixer

Xtal Filter

IF Amp

25kHzFilter

First LO
Xtal Filter

2nd LO Xtal Osc

25kHzFilter

IFIC

Phase Shift
Element
Controller

Figure 2-1 Midband Receiver Block Diagram

2-2

THEORY OF OPERATION

2.2

Receiver Back End
The IF signal from the crystal filter enters the IF amplifier which provides 20 dB of gain and feeds
the IF IC (U2) at pin 1. The first IF signal at 21.4 MHz mixes with the second local oscillator (LO) at
20.945 MHz to produce the second IF at 455 kHz. The second LO uses the external crystal Y2. The
second IF signal is amplified and filtered by two external ceramic filters (FL4/FL3 for 12.5KHz
channel spacing and FL5/FL2 for 25KHz channel spacing). The IF IC demodulates the signal by
means of a quadrature detector and feeds the detected audio (via pin 7) to the audio processing
circuits. At IF IC pin 5, an RSSI signal is available with a dynamic range of 70 dB.

3.0

Midband Transmitter Power Amplifier (66-88 MHz)
The radio’s 25W PA is a three-stage amplifier used to amplify the output from the TX_INJ to the
antenna port. All three stages utilize LDMOS technology. The gain of the first stage (U101)and the
second stage (Q105) is adjustable and is controlled by pin 7 of U103-2 via U103-3 and U102-1. It is
followed by an LDMOS final stage Q100.

Pin Diode
Antenna
Switch

From VCO (TX_INJ)
Controlled
Stage

Driver

PA-Final
Stage

Antenna
Harmonic
Filter
RF Jack

Coupler

Bias

Forward

A S FI C _C M P
SPI BUS

PA
PWR
SET
L oo p
C ont r ol le r
U 103 - 2

Temperature
Sense

Figure 2-2 Midband Transmitter Block Diagram
Devices U101, Q105 and Q100 are surface mounted. When assembled, Q100 is in direct contact
with the chassis. Heat spreader M105 ensures good thermal contact for Q105.

3.1

First Power Controller Stage
The first stage (U101) is a variable gain integrated circuit containing two LDMOS FET amplifier
stages which can provide up to 20dB gain. It amplifies the RF signal from the VCO (TX_INJ). The
output power of stage U101 is controlled by a DC voltage applied to pin 1 from the op-amp U103-3,
pin 8. The control voltage simultaneously varies the bias of two FET stages within U101. This
biasing point determines the overall gain of U101 and therefore its output drive level to Q105, which
in turn controls the output power of the PA.

Midband Transmitter Power Amplifier (66-88 MHz)

2-3

For a given control voltage input on VCNTR1, Op-amp U103-3 monitors the drain current of U101
via resistor R122 and adjusts the bias voltage of U101 accordingly.
In receive mode, the DC voltage from RX_EN line turns on Q101, grounding VCNTR1, which in turn
switches off the biasing voltage to U101.

3.2

Power Controlled Driver Stage
The next stage is an LDMOS device (Q105) which provides a gain of up to 15dB. This device
requires a positive gate bias and a quiescent current flow for proper operation. The bias is set during
transmit mode by the drain current control op-amp U102-1, and fed to the gate of Q105 via the
resistive network (R175, R147, R178, R179).
For a given control voltage input on VCNTR2, Op-amp U102-1 monitors the drain current of Q105
via resistors R126-7 and adjusts the bias voltage of Q105 so that the current remains constant.
In receive mode the DC voltage from RX_EN line turns on Q102, grounding VCNTR1, which in turn
switches off the biasing voltage to Q105.

3.3

Final Stage
The final stage is an LDMOS device (Q100) providing a gain of 12dB. This device also requires a
positive gate bias and a quiescent current flow for proper operation. The voltage of the line PA_BIAS
is set in transmit mode by the ASFIC and fed to the gate of Q100 via the resistive network R134,
R131. This bias voltage is tuned in the factory. If the transistor is replaced, the bias voltage must be
tuned using the Tuner. Care must be taken not to damage the device by exceeding the maximum
allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC supply voltage
input, B+, via L117 and L115.
The output matching network transforms the impedance to 50 ohms and feeds the directional
coupler.

3.4

3.5

Antenna Switch
The antenna switch utilizes the existing dc feed (B+) to the last stage device (Q100). In transmit
mode, both PIN diodes (D103, D104) are forward biased. This is achieved by pulling down the
voltage at the cathode end of D104 to around 12.4V (0.7V drop across each diode). The current
through the diodes needs to be set at around 100 mA to fully open the transmit path through resistor
R108. Q106 is a current source controlled by Q103 which is turned on in Tx mode by TX_EN.
VR102 ensures that the voltage at resistor R107 never exceeds 5.6V, limiting the current to
approximately 100mA.

2-4

3.6

THEORY OF OPERATION

Harmonic Filter
Inductors L1511, L1512, L1513 and L1515 along with capacitors C1518 to C1523, C1528, C1532 to
C1535, C1537 to C1539 and C1542 form a 9-element elliptical low-pass filter to attenuate harmonic
energy coming from the transmitter. Resistor R152 drains any electrostatic charges that might
otherwise build up on the antenna. The harmonic filter also prevents high level RF signals above the
receiver passband from reaching the receiver circuits to improve spurious response rejection.

3.7

Power Control
The output power is regulated by using a forward power detection control loop. A directional coupler
samples a portion of the forward and reflected RF power. The forward sampled RF is rectified by
diode D105, and the resulting DC voltage is routed to the operational amplifier U100. The error
output current is then routed to an integrator, and converted into the control voltage. This voltage
controls the bias of the pre-driver (U101) and driver (Q105) stages. The output power level is set by
way of a DAC, PWR_SET, in the ASFIC (U504), which acts as the forward power control loop
reference.
The sampled reflected power is rectified by diode D107,The resulting DC voltage is amplified by an
operational amplifier U100 and routed to the summing junction. This detector protects the final stage
Q100 from reflected power by increasing the error current. The temperature sensor protects the
final stage Q100 from overheating by increasing the error current. A thermistor RT100 measures the
final stage Q100 temperature. The voltage divider output is routed to an operational amplifier U103
and then goes to the summing junction. The Zener Diode VR101 keeps the loop control voltage
below 5.6V and eliminates the DC current from the 9.3 regulator U501.
Two local loops for the Pre Driver (U101) and for the Driver (Q105) are used in order to stabilize the
current for each stage.
In Rx mode, the two transistors Q101 and Q102 go to saturation and shut down the transmitter by
applying ground to the Pre Driver U101 and for the Driver Q105 control.
VR103, VR104 and Q104, Q108, Q109 and associated circuitry provide protection during load
dump transients.

4.0

Midband (66-88MHz) Frequency Synthesis
The synthesizer consists of a reference oscillator (Y202), low voltage Fractional-N (LVFRAC-N)
synthesizer (U200), and a voltage controlled oscillator (VCO) (Q2741/Q2751).

4.1

Reference Oscillator
The reference oscillator is a crystal (Y202) controlled Colpitts oscillator and has a frequency of
16.8MHz. The oscillator transistor and start-up circuit are located in the LVFRAC-N (U200) while the
oscillator feedback capacitors, crystal, and tuning varactors are external. An analog-to-digital (A/D)
converter internal to the LVFRAC-N (U200) and controlled by the microprocessor via SPI sets the
voltage at the warp output of U200 pin 25. This sets the frequency of the oscillator. Consequently,
the output of the crystal Y202 is applied to U200 pin 23.

Midband (66-88MHz) Frequency Synthesis

2-5

The method of temperature compensation is to apply an inverse Bechmann voltage curve, which
matches the crystal’s Bechmann curve to a varactor that constantly shifts the oscillator back on
frequency. The crystal vendor characterizes the crystal over a specified temperature range and
codes this information into a bar code that is printed on the crystal package. In production, this
crystal code is read via a 2-dimensional bar code reader and the parameters are saved.
This oscillator is temperature compensated to an accuracy of +/-2.5 PPM from -30 to 60 degrees C.
The temperature compensation scheme is implemented by an algorithm that uses five crystal
parameters (four characterize the inverse Bechmann voltage curve and one for frequency accuracy
of the reference oscillator at 25 degrees C). This algorithm is implemented by the LVFRAC-N (U200)
at the power up of the radio.

4.2

DATA (U403 PIN 100)
CLOCK (U403 PIN 1)
+9V
CSX (U403 PIN 2)
MOD IN (U501 PIN 40)
+5V (U503 PIN 1)
+5V (U503 PIN 1)

7
8
30
9
10
13

5, 20, 34, 36

REFERENCE
OSCILLATOR

23
24

VOLTAGE
MULTIPLIER

FREFOUT

CLK

GND

CEX
MODIN
VCC, DC5V

IOUT
IADAPT

VDD, DC5V

MODOUT

XTAL1

U200

XTAL2

FRACTIONAL-N
SYNTHESIZER

WARP

PREIN

LOCK

DATA

LOW VOLTAGE

VCP
VMULT2
14

43
45

LOOP
FILTER

STEERING
LINE

AUX3

AUX1 BIAS2

FREF (U504 PIN 34)

6, 22, 33, 44

3
1

BIAS1

LOCK (U403 PIN 56)

AUX4
AUX2

SFOUT

VMULT1

NC
NC
TRB

VCO Bias

LO RF INJECTION

VOLTAGE
28 FILTERED 9V CONTROLLED
OSCILLATOR
40
TX RF INJECTION
(1ST STAGE OF PA)

BWSELECT

To IF
Section

PRESCALER IN

Figure 2-3 Midband Synthesizer Block Diagram
A voltage of 9.3V applied to the super filter input (U200, pin 30) supplies an output voltage of 8.6Vdc
(VSF) at U200, pin 28. This supplies 8.6 V to the two VCO circuits.
To generate a high voltage to supply the phase detector (charge pump) output stage at pin VCP
(U200, pin 47) while using a low voltage 5Vdc supply, a 13V positive voltage multiplier is used
(D200, D201, and capacitors C2024, 2025, 2026, 2055, 2027, 2001).
Output lock (U200, pin 4) provides information about the lock status of the synthesizer loop. A high
level at this output indicates a stable loop. A 16.8 MHz reference frequency is provided at U200, pin 19.

2-6

4.3

THEORY OF OPERATION

Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) uses 2 colpitts oscillators, FET Q2741 for transmit and FET
Q2751 for receive. The appropriate oscillator is switched on or off by LVFRAC-N IC output AUX3
(U200-2) using transistors Q2742 and Q2752. In RX mode AUX3 is nearly at ground level and
Q2742 enables a current flow from the source of FET Q2751 while Q2752 is switched off. In TX
mode AUX3 is about 3.3V DC and Q2742 is switched off. Q2752 is switched on and enables a
current flow from the source of FET Q2741 while Q2751 is switched off. When switched on the FETs
draw a drain current of 8 mA from the LVFRAC-N IC super filter output. The frequency of the receive
oscillator is mainly determined by L2752, L2753, C2752 - C2756 and varactor diodes D2751 /
D2752. Diode D2754 controls the amplitude of the oscillator. The frequency of the transmit oscillator
is mainly determined by L2734, C2736 - C2740 and varactor diodes D2732 / D2733. Diode D2739
controls the amplitude of the oscillator. With a steering voltage from 3V to 10V at the varactor diodes
the RX frequency range from 87.4 MHz to 109.4 MHz and the TX frequency range from 66 MHz to
88 MHz are covered. In TX mode the modulation signal coming from the LVFRAC-N synthesizer IC
(U200 pin 41) modulates the TX VCO via varactor diode D2731.

V-SF
STEERING
LINE

5V
Q2741

MOD OUT
U200-41

Q2760

Q2770

V-SF

TX_EN

Q2780

Q2751

TRB
U200-2

Q2790
9V

SWITCHING
CONTROL

PRE-SCALER
TO U200-32

TX_INJ

RX_INJ
(Ist LO)

Figure 2-4 Midband VCO Block Diagram

Both oscillator outputs are combined and buffered by the VCO Buffer Q2760. Q2760 draws a
collector current of 13 mA from the stabilized 5V and drives the Mixer Buffer Q2770. Q2770 draws a
collector current of 19 mA from the 9V3 voltage and drives the PA Buffer Q2780 (Pout = 13dBm)
and the Pre-scaler Buffer Q2790. Q2790 draws a collector current of 8 mA from the stabilized 5V
and drives the pre-scaler internal to the LVFRAC-N IC. In transmit mode, the 9.3V supply for the TX
PA Buffer Q2780 , is turned on by Q2791. PA Buffer Q2780 draws a collector current of 19mA. The
injection signal RX_INJ with a level of 10dBm feeds the mixer through R2774. The buffer stages
Q2760, Q2770, Q2780 and the feedback amplifier Q2790 provide the necessary gain and isolation
for the synthesizer loop.

Midband (66-88MHz) Frequency Synthesis

4.4

2-7

Synthesizer Operation
The synthesizer consists of a low voltage FRAC-N IC (LVFRAC-N), reference oscillator, charge
pump circuits, loop filter circuit, and DC supply. The output from the pre-scaler buffer (Q2790) is fed
to the PREIN, pin 32 of U200 via a low pass filter which attenuates harmonics and provides a correct
input level to the LVFRAC-N in order to close the synthesizer loop.
The pre-scaler in the synthesizer (U200) is a dual modulus pre-scaler with selectable divider ratios.
The divider ratio of the pre-scaler is controlled by the loop divider, which in turn receives its inputs
via the SPI. The output of the pre-scaler is applied to the loop divider. The output of the loop divider
is connected to the phase detector, which compares the loop divider’s output signal with the
reference signal. The reference signal is generated by dividing down the signal of the reference
oscillator (Y202).
The output signal of the phase detector is a pulsed dc signal that is routed to the charge pump. The
charge pump outputs a current from U200, pin 43 (IOUT). The loop filter (consisting of R224, R217,
R234, C2074, C2078, C2028, and L205) transforms this current into a voltage that is applied the
varactor diodes D2751, D2752 for Rx and D2732, D2733 for Tx. The output frequency is determined
by this control voltage. The current can be set to a value fixed in the LVFRAC-N or to a value
determined by the currents flowing into BIAS 1 (U200, pin 40) or BIAS 2 (U200, pin 39). The
currents are set by the value of R200 or R206 respectively. The selection of the three different bias
sources is done by software programming.
To modulate the synthesizer loop, a two-spot modulation method is utilized via the MODIN (U200,
pin 10) input of the LVFRAC-N. The audio signal is applied to both the A/D converter (low frequency
path) and the balance attenuator (high frequency path). The A/D converter converts the low
frequency analog modulating signal into a digital code which is applied to the loop divider, thereby
causing the carrier to deviate. The balance attenuator is used to adjust the VCO’s deviation
sensitivity to high frequency modulating signals. The output of the balance attenuator is presented
at the MODOUT port of the LVFRAC-N (U200 pin 41) and connected to the VCO modulation
varactor D2731.

2-8

5.0

THEORY OF OPERATION

External
Microphone

To Synthesizer
Mod
Out
16.8 MHz
Reference Clock
from Synthesizer

Audio/Signaling
Architecture

Disc Audio

ASFIC_CMP

Internal
Microphone
External
Speaker

Audio
PA
Internal
Speaker

µP Clock

SPI

To RF Section
Digital
Architecture

SCI to
Accessory &
Control Head
Connector

RAM
EEPROM

3.3V
Regulator

HC11FL0

FLASH

Figure 2-5 Controller Block Diagram

5.1

Radio Power Distribution
Voltage distribution is provided by five separate devices:
■

U514 P-cH FET - Batt + (Ext_SWB+)

■

U501 LM2941T - 9.3V

■

U503 LP2951CM - 5V

■

U508 MC 33269DTRK - 3.3V

■

U510 LP2986ILDX - 3.3V Digital

Handset

Controller Theory of Operation

2-9

The DC voltage applied to connector P2 supplies power directly to the following circuitry:
■

Electronic on/off control

■

RF power amplifier

■

12 volts P-cH FET -U514

■

9.3 volt regulator

■

Audio PA

Ignition

Auto
On/Off
Switch
Control

B+

Control Head
RF_PA
Audio_PA

Mic Connector

Ferrite Bit
Filt_B+

Antenna Switch
Power Control

500mA

FET
P-CH
On/Off
Control

SW_Filt_B+

11-16.6V
0.9A

Status LEDs

7_Seg

7_Seg
DOT

Bed
to
7-Seg

Back
light

Shift
Reg

Acces Conn
Audio PA_Soutdown
Power Loop Op_Amp
9.3V
65mA

U501
9.3V Regulator

Keypad

Mic Bias
9V, 5mA

0.85A

Reset

9.3V
45mA

On/Off
Control

U503
5V RF Regulator
500mA
Rx_Amp
PA_Pre-driver
PA Driver

3.2V
72mA

45mA
LVFRAC_N
IF_Amp

9.3V
75mA

9.3V
162mA

U508
3.3V RF Reg
50mA

25mA
ASFIC_CMP
IFIC
RX Cct

U510
3.3V D Reg
90mA
micro P
RAM
Flash
EEPROM

2-10

THEORY OF OPERATION

5.2

Protection Devices
Diode VR500 acts as protection against ESD, wrong polarity of the supply voltage, and load dump.
VR692 - VR699 are for ESD protection.

5.3

Automatic On/Off
The radio can be switched ON in any one of the following ways:

5.3.1

■

On/Off switch. (No Ignition Mode)

■

Ignition and On/Off switch (Ignition Mode)

■

Emergency

5.3.2

Controller Theory of Operation

5.3.3

2-11

5.4

2-12

5.5

THEORY OF OPERATION

5.6

5.7

PROG IN 3 can be used as external PTT input, or others, set by the CPS. The µP reads this
port via pin 72 and Q412.

■

PROG OUT 4 can be used as external alarm output, set by the CPS. Transistor Q401 is
controlled by the µP (U403 pin 55)

■

PROG IN 6 can be used as normal input, set by the CPS. The µP reads this port via pin 73
and Q411. This pin is also used to communicate with the RIB if resistor R421 is placed.

■

Controller Theory of Operation

5.8

2-13

2-14

5.9

THEORY OF OPERATION

6.0

Control Board Audio and Signalling Circuits

6.1

Audio Signalling Filter IC and Compander (ASFIC CMP)
The ASFIC CMP (U504) used in the controller has the following four functions:
1.

RX/TX audio shaping, i.e. filtering, amplification, attenuation

RX/TX signaling, PL/DPL/HST/MDC

Squelch detection

µP clock signal generation

GCBO - BW Select

■

GCBI - switches the audio PA On/Off

■

GCB2 - DC Power On switches the voltage regulator (and the radio) on and off

■

GCB3 - Control on MUX U509 pin 9 to select between Low Cost Mic path to STD Mic Path

■

GCB4 - Control on MUX U509 pin 11 to select between Flat RX path to filtered RX path on the
accessory connector.

■

GCB5 - Control on MUX U509 pin 10 to select between Flat TX path mute and Flat TX path

Transmit Audio Circuits

7.0

2-15

Transmit Audio Circuits

24kOhms

U509

MIC

46
35

FLAT TX
AUDIO

MIC
INT

GCB3
MIC
EXT

U509

36
TX RTN

MUX

CONTROL HEAD
CONNECTOR

EXT MIC

44
TX SND

MUX

AUX
TX
ACCESSORY
CONNECTOR

FILTERS AND
PREEMPHASIS
MIC
ASFIC_CMP
IN
U504 LIMITER
HS SUMMER
SPLATTER
FILTER
LS SUMMER

GCB5

FLAT TX
AUDIO MUTE

VCO
ATN
ATTENUATOR

MOD IN
40

TO
RF
SECTION
(SYNTHESIZER)

Figure 2-7 Transmit Audio Paths

7.1

7.1.1

2-16

7.1.2

THEORY OF OPERATION

7.2

Transmit Signalling Circuits

8.0

2-17

Transmit Signalling Circuits

HS
SUMMER

MICRO
CONTROLLER

U403

19 HIGH SPEED
CLOCK IN
(HSIO)

DTMF
ENCODER

SPI
BUS

SPLATTER
FILTER

ASFIC_CMP U504

5-3-2 STATE
ENCODER

LOW SPEED
CLOCK IN
(LSIO)

PL
ENCODER

LS
SUMMER
ATTENUATOR

40
MOD IN

TO RF
SECTION
(SYNTHESIZER)

Figure 2-8 Transmit Signalling Path
From a hardware point of view, there are 3 types of signaling:
■

Sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or
signaling,

■

DTMF data for telephone communication in trunked and conventional systems, and

■

Audible signaling including MDC and high-speed trunking.

Note: All three types are supported by the hardware while the radio software determines which
signaling type is available.

8.1

2-18

8.2

THEORY OF OPERATION

8.3

Receive Audio Circuits

9.0

2-19

Receive Audio Circuits
ACCESSORY
CONNECTOR
11

1
AUDIO
PA
U502
9

SPKR +

SPKR -

EXTERNAL
SPEAKER

INT
SPKR+

INT
SPKRCONTROL HEAD
CONNECTOR
19

MUTE

U509

FLT RX AUDIO

INTERNAL
SPEAKER

20
J2

HANDSET
AUDIO

U505
37

10
GCB4 U IO

43 AUX RX

URX OUT AUDIO

GCB1

VOLUME
ATTEN.

ASFIC_CMP
U504

FILTER AND
DEEMPHASIS

DISC
FROM
AUDIO
RF
SECTION
(IF IC)

2 DISC

PL FILTER
LIMITER
LIMITER, RECTIFIER
FILTER, COMPARATOR

LS IO

SQUELCH
CIRCUIT
SQ DET

CH ACT

MICRO
CONTROLLER

U403

Figure 2-9 Receive Audio Paths

9.1

2-20

9.2

THEORY OF OPERATION

9.3

Receive Signalling Circuits

9.4

2-21

9.5

10.0

Receive Signalling Circuits

DATA FILTER
AND DEEMPHASIS
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF IC)

LIMITER

HSIO 19

82
44

DISC

ASFIC_CMP
U504
FILTER

LIMITER

MICRO
CONTROLLER
U403

LSIO 18

80
85

PLEAP
8

PLCAP2
25

Figure 2-10 Receive Signalling Paths

10.1

2-22

THEORY OF OPERATION

10.2

3-2

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for Out-of-Lock Receiver (Sheet 1 of 2)
NOTE: HANDLE WITH CARE
C2078 (main loop filter capacitor) is
easily damaged by heat or soldering

START

Monitor TP200 at turn-on
See figure for typical trace

Yes

TP200
Is Voltage
correct for freq?
Typ. 4V for 66MHz
to 11v for 88MHz
(Rx freq.)

Voltage dependent
on power-on
channel:
typ. 3.8v for 66Mhz
10.7V for 88MHz
(Rx Freq.)

TP200
Is ramp-up
slope correct?
Typ.14V in 500ms

500ms
turn-on

Check C2078, R217,
R224, C2074, R200,
R234
Check U200-4
(lock detect line)
Check U200-45, 43 lines.
If all ok, replace U200

typ.14.7V

synth programmed
with power-up channel

1.0

Go to ‘A’
sheet 2 of 2

Yes

TP200
Does voltage
reach typ. 14.7V

Yes

Check voltage
on U200-47
typ. 14.7V

U200-19
No
Go to Ref.
should be
16.8MHz, 0.5Vpp
Osc.Section

Yes

Yes
Replace U200

Go to
Rx VCO Section

Check LO level
TP1 approx
-18dBm into
50 Ohms

Yes

Check D2751, D2752,
L2750-L2753,
C2751-C2756

Is freq approx
118MHz TP200
approx 14.7V ? or
<75MHz TP200
approx <1V

U200-14,15
should be
square wave
1.05MHz, 3.6Vpp

Yes

Check Q2790 and
associated cctry
check C2796, R2796

Check R228, R225
D200, D201,
C2024 -C2027, C2001

Troubleshooting Flow Chart for Out-of-Lock Receiver (Sheet 1 of 2)

1.1

3-3

Troubleshooting Flow Chart for Out-of-Lock Receiver (Sheet 2 of 2)
From ‘A’
sheet 1 of 2

TP200
Does Voltage
stay <1V ?

Yes
SPI
No
activity on
U200-7, 8, 9?

No
Yes
3.3V
on U200-5, 20
34, 36?

Check U508

Yes

5V
on U200-13?

Check U503

Yes

9.2V
on U200-30?

Check R2808,
Check U501

Check C2006,
U200-26, if ok
replace U200

Yes

V-SF
8.7V on
U200-28?

Yes
Check C2078, R234,
R217, C2074, R200
If all ok, replace U200

Check SPI Connections
Fault in digital area

3-4

2.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 4)
START

Ensure that the radio is set-up
via the CPS to have 25W channels

No or too low power when keyed

Rx
sensitivity
OK?

Check Harmonic Filter
components C1537 to
Antenna Connector

Yes
Check components between Q100 and
RF output, Antenna Switch D104,
D103, VR102 and Q106, Q103 and
associated bias circuitry.
Check DC volts present at anode of
D103.

>1A

Current
increase when
keyed?

>800mA & <1A
Short U100
Pin 3 to
ground

<800mA
Control
Voltage at
TP150
>1.6V?

No
Check 9.3V
Regulator
U501, R180 &
R181

Voltage U103
pin 5 =
4.7V?

Yes
Check power settings, tuning, R142,
R143, R156 & components between
U103 Pin 3 and ASFIC Pin 6 before
replacing ASFIC

U103 Pin 3
<2.7Vdc

Yes
Check
U103

Yes

PA Bias
Voltage@R134
>2Vdc

No
Check Forward
Power Sense
Circuit

Yes

Check PA
Stages

Yes

Voltage at
TP150 rises?

No
Check Forward
Power Sense
Circuit

Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 4)

2.1

3-5

Troubleshooting Flow Chart for 25W Transmitter (Sheet 2 of 4)
Check PA
Stages

Quick check of PA devices.

Check 13.8v present at drain Q100. Disconnect
power supply, measure R131 to Ground.

10kOhm?

Replace Q100.
Re-tune PA Bias
with Tuner.

Yes
Measure R147 to Ground.

22kOhm?

Yes
Connect power supply.
Key radio.

Go to ‘A’
sheet 3 of 4

Replace Q105.

3-6

2.2

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for 25W Transmitter (Sheet 3 of 4)
From ‘A’
sheet 2 of 4

DC
Voltage
at Q101 & Q102
base=0?

Check Q101, Q102,
R153, R136, R165,
R122, R168 & R137

<2.0V

Yes
Check U103 before replacing U101

DC
Voltage
at U103
Pin 8

>5.0V

Check resistive network at
Pin 9 and 10 of U103
before replacing U101

2.0 to 5.0V
Measure DC Voltage at U102 Pin 1

<2V

Pin 1
Voltage

>3V

Check Q102, R139,
R166, R126, R169,
R138, R175, R147

No
DC
Voltage at
U103 Pin 3 =
8.8V

Check U403

Yes

No
DC
Voltage at
U103 Pin
10=8.8V

2-3V

Yes
Check U102 before
replacing Q105
Check Final PA Stages

Check resistive network at
Pin 2 & 3 of U102 before
replacing Q105

Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 4)

2.3

3-7

Troubleshooting Flow Chart for 25W Transmitter (Sheet 4 of 4)

Check Final PA Stage

>100mV & <2V

Check voltage varies as bias
softpot is tuned (in small steps)
via the Global Tuner.
Check Bias Tuning, R134, R131,
R105 & R106 before replacing
ASFIC U504.

PA_Bias
Voltage at
R134

Supply Voltage

Replace Q100

or 0V

2-3V
RF Voltage
after C1044
>100mV?

Check FGU

Yes

Voltage
across R122
>50mV?

Check components
between C1044 &
C182

Check components
between C182 &
Q105

Check components
between Q105 &
Q100

Yes

RF Voltage
Q105 gate
>250mV?

Yes

RF Voltage
Q100 gate
>1.0V?

Yes
Check components
between Q100 &
antenna connector

3-8

3.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for Synthesizer (Reference Oscillator)

Incorrect or no µP
clock signal

TP403
Freq. = 14.7MHz
or 7.4MHz ?

YES

Reference Oscillator
working

NO
TP403

YES

Freq. = 3.68MHz

Power-up default freq.
Fault with ASFIC
or Controller section

Check U504-28
should be 16.8MHz
0.5Vpp
YES
Check U504 and
C504, C5025, R5033

Check U504-28
Check Y202-1
should be 16.8MHz
0.5Vpp
YES
Faulty U200,
or R229

Check Y201 and
associated
circuitry

Troubleshooting Flow Chart for VCO

4.0

3-9

Troubleshooting Flow Chart for VCO
No Receive VCO Signal
at TP1

NO
>7V at Q2751D ?

Power Ok but
No modulation

Check supply at Q2751

YES

NO
Audio from U200-11?

Check modulation
tuning softpots

YES
NO

<0.1V at Q2742-2?

Check Q2742, R2743
U200-2 should be 0V

Check audio on D2731
and Vdc approx 8.6V

YES

Use Hi - impedance
probe to check frequency
Is freq. approx 118 MHz?

YES

NO
Check Rx VCO parts

Check D27312, R2731,
C2734

YES
Fault in buffer section
Q2760, Q2770
- check supplies and parts

Out-of-Lock in TX
On detection of an out-of-lock in Tx,
the radio returns to the Rx mode.

Check Rx - Tx switching
Q2742, Q2752 (should be turned on)
Check Q2741 and associated circuitry.

NOTE:
The TX VCO can be force enabled by
grounding Q2742-3

Check R2714, C2722,
C2731, C2733, L2731

3-10

5.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for Receiver (Sheet 1 of 2)
START

Ensure that all Power Supplies are correct, as
detailed in paragraph 6.

Bad SINAD
Bad 20dB Quieting
No Recovered Audio

Audio at
pin 8 of
U2 ?

Yes

Check Controller
(in the case of no audio)
OR ELSE go to “B”

No
Spray or inject 21.4MHz
into XTAL Filter FL3101

Yes
B

Check Q6 bias
for faults
Audio heard ?

Biasing OK ?

Check 2nd LO
(20.945MHz) at C53

Replace Q6

Yes

Yes
LO present ?

Go to B

Check voltages on U2

Check circuitry
around U2.
Replace
U2 if defect

Voltages
OK?

Yes

Check circuitry around Y2
Replace Y2 if defect

Troubleshooting Flow Chart for Receiver (Sheet 1 of 2)

5.1

3-11

Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
B

Inject RF into J1

Yes

IF Signal at
C58?

Trace IF signal from
C58 to Q6. Check for
bad XTAL filters

IF signal at Q6
collector?

Before replacing
U2, check
U2 voltages

No
Yes

RF Signal at T1?

1st
LO level OK?
Locked?
Yes

Yes
RF Signal at
C2337?

Yes

No
Check FGU
Check T1, T2, U1 (diode),
R41, L2, L2792, C59 and
L6

Check filter between
C2337 & T1

No
Yes
RF Signal at
C2308?

Check RF amp
(Q2301) Stage

No or
weak RF
Yes
RF Signal at
C1108?

Check filter between C1108
& C2308. Check tuning
voltage at R2309

No
Check Harmonic Filter
J1 and
Antenna Switch
D103,D104,L1514

Is tuning
voltage OK?
No
Check U517

Yes

Check varactor filter
D2301, D2304

3-12

6.0

TROUBLESHOOTING CHARTS

Go to 3V

Replace U503

Yes

V=5V
?

9v 1 GHz

Audio Response: (from 6 dB/
oct. Pre-Emphasis, 300 to
3000Hz)

TIA603 and CEPT

Tx Audio Distortion

< 3%

Modulation Limiting:

±2.5 kHz @ 12.5 kHz
±4.0 kHz @ 20 kHz
±5.0 kHz @ 25 kHz

FM Hum and Noise:

-35 dB@12.5 kHz
-40 dB@25 kHz

Receiver
Specification
Sensitivity (12 dB SINAD):

UHF2
0.35 µV @ 12.5 kHz
0.3 µV @ 25 kHz

Intermodulation:

60 dB@12.5 kHz
70 dB@25 kHz

Adjacent Channel Selectivity:

60 dB @ 12.5 kHz
70 dB @ 25 kHz

Spurious Response

70 dB

Rated Audio Power

4 W (typ.) Internal
7.5 W @ 5 % External

Audio Distortion

<5%

Hum and Noise:

-35 dB @ 12.5 kHz
-40 dB @ 25 kHz

Audio Response

TIA603 and CEPT

Conducted Spurious Emission
per FCC Part 15:

-57 dBm <1 Ghz
-47 dBm >1 Ghz

Specifications subject to change without notice. All electrical specifications and methods
refer to EIA/TIA 603 standards.

1-4

MODEL CHART AND TECHNICAL SPECIFICATIONS

THIS PAGE INTENTIONALLY LEFT BLANK

Chapter 2
THEORY OF OPERATION
1.0

2.0

UHF (438-470MHz) Receiver

2.1

Receiver Front-End
The received signal is applied to the radio’s antenna input connector and routed through the
harmonic filter and antenna switch. The insertion loss of the harmonic filter/antenna switch is less
than 1 dB. The signal is routed to the first filter (3-pole), which has an insertion loss of 2 dB typically.
The output of the filter is matched to the base of the LNA (Q303) that provides a 16 dB gain and a
noise figure of better than 2 dB. Current source Q301 is used to maintain the collector current of
Q303. Diode CR301 protects Q303 by clamping excessive input signals. Q303 output is applied to
the second filter (4-pole) which has an insertion loss of 1.5 dB. In Distance mode, Q304 turns on and
causes D305 to conduct, thus bypassing C322 and R337. In Local mode, the signal is routed
through C322 and R337, thus inserting 7 dB attenuation. Since the attenuator is located after the RF
amplifier, the receiver sensitivity is reduced only by 6 dB, while the overall third order input intercept
is raised.
The first mixer is a passive, double-balanced type, consisting of T300, T301 and U302. This mixer
provides all of the necessary rejection of the half-IF spurious response. Low-side injection at +10
dBm is delivered to the first mixer. The mixer output is then connected to a duplex network which
matches its output to the XTAL filter input (FL300) at the IF frequency of 44.85 MHz. The duplex
network terminates into a 50 ohm resistor (R340) at all other frequencies.

Antenna
Front Filter

12.5kHzFilter 12.5kHzFilter
LNA

Second Filter

Mixer

4- Pole
Xtal Filter

IF Amp

First LO

25kHzFilter

IFIC

2nd LO Xtal Osc

Phase Shift
Element
Controller

Figure 2-1 UHF Receiver Block Diagram

2-2

THEORY OF OPERATION

2.2

3.0

UHF Transmitter Power Amplifier (438-470 MHz)
The radio’s 40W PA is a three-stage amplifier used to amplify the output from the VCOBIC to the
radio transmit level. All three stages utilize LDMOS technology. The gain of the first stage (U101) is
adjustable and controlled by pin 7 of U103-2 via U103-3. It is followed by an LDMOS stage Q105
and LDMOS final stage Q100.

Pin Diode
Antenna
Switch

From VCO
Controlled
Stage

Driver

PA-Final
Stage

Antenna
Harmonic
Filter
RF Jack

Coupler

Bias

Forward

A S FI C _C M P
SPI BUS

PA
PWR
SET
L oo p
C ont r ol le r
U 103 - 2

Temperature
Sense

Figure 2-2 UHF Transmitter Block Diagram
Devices U101, Q105 and Q100 are surface mounted. Q100 is screwed down to the chassis to
ensure good thermal contact. This scheme also ensures sufficient thermal contact between driver
and chassis.

3.1

First Power Controller Stage
The first stage (U101) is a 24dB gain integrated circuit containing two LDMOS FET amplifier stages.
It amplifies the RF signal from the VCO (TX_INJ). The output power of stage U101 is controlled by a
DC voltage applied to pin 1 from the op-amp U103-3, pin 8. The control voltage simultaneously
varies the bias of two FET stages within U101. This biasing point determines the overall gain of
U101 and therefore its output drive level to Q105, which in turn controls the output power of the

UHF Transmitter Power Amplifier (438-470 MHz)

2-3

3.2

Power Controlled Driver Stage
The next stage is an LDMOS device (Q105) which provides a gain of 12dB. This device requires a
positive gate bias and a quiescent current flow for proper operation.The voltage of the
PA_CURRENT is set in transmit mode by ASFIC (U504 pin 5) and fed to the gate of Q105 via
resistive network R186, R187. This bias voltage is tuned in the factory. If the transistor is replaced,
the bias voltage must be tuned using Global Tuner. Care must be taken so that the transistor is not
tuned exceeding the allowed bias voltage. This device directly drains current from B+ via L122.

3.3

Final Stage
The final stage is an LDMOS device (Q100) providing a gain of 12dB. This device also requires a
positive gate bias and a quiescent current flow for proper operation. The voltage of the line PA_BIAS
is set in transmit mode by ASFIC (U504 pin 4) and fed to the gate of Q100 via the resistive network
R134, R131. This bias voltage is tuned in the factory. If the transistor is replaced, the bias voltage
must be tuned using the Global Tuner. Care must be taken not to damage the device by exceeding
the maximum allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC
supply voltage input, B+, via L117, L115, L124 and L125.
A matching network consisting of C1005, C1017, C1004, C1009, C1008, C1007, C1274, C1279,
C1275, C1276, C1277, C1278, C1021, C1280, C1013, L126, L127 and two striplines, transforms
the impedance to 50 ohms and feeds the directional coupler.

3.4

Directional Coupler
The directional Coupler is a microstrip printed circuit, which couples a small amount of the forward
power of the RF power from Q100. Coupled power is rectified by diode D105 to produce a
proportional DC voltage; and the resulting DC voltage is routed to the power control section to
ensure that the forward power out of the radio is held to a constant value.

3.5

2-4

3.6

THEORY OF OPERATION

Harmonic Filter
Inductors L111, L113 and L128 along with capacitors C1011, C1023, C1020, C1016, C1025 and
C1026 form a low-pass filter to attenuate harmonic energy coming from the transmitter. Resistor
R150 along with L130 drains any electrostatic charges that might otherwise build up on the antenna.
The harmonic filter also prevents high level RF signals above the receiver passband from reaching
the receiver circuits to improve spurious response rejection.

3.7

Power Control
The output power is regulated by using a forward power detection control loop. A directional coupler
samples a portion of the forward and reflected RF power. The forward sampled RF is rectified by
diode D105, and the resulting DC voltage is routed to the operational amplifier U100. The error
output current is then routed to an integrator, and converted into the control voltage. This voltage
controls the bias of the pre-driver (U101) stage. The output power level is set by PWR_SET at
ASFIC (U504 pin 6) which acts as the reference for forward power control loop.
The reflected coupled power is rectified by diode D107,The resulting DC voltage is amplified by an
operational amplifier U100 and routed to the summing junction. This detector protects the final stage
Q100 from reflected power by increasing the error current. The temperature sensor protects the
final stage Q100 from overheating by increasing the error current. A thermistor RT100 measures the
final stage Q100 temperature. The voltage divider output is routed to an operational amplifier U103
and then goes to the summing junction. The Zener Diode VR101 keeps the loop control voltage
below 5.6V and eliminates the DC current from the 9.3 regulator U501.
One local loop for the Pre Driver (U101) is used in order to stabilize the current for each stage.
In Rx mode, the two transistors Q101 and Q102 go to saturation and shut down the transmitter by
applying ground to the Pre Driver U101.

4.0

UHF (438-470MHz) Frequency Synthesizer
The synthesizer consists of a reference oscillator (Y201), low voltage Fractional-N (LVFRAC-N)
synthesizer (U200), and a voltage controlled oscillator (VCO) (U201).

4.1

UHF (438-470MHz) Frequency Synthesizer

2-5

parameters (four characterize the inverse Bechmann voltage curve and one for frequency accuracy
of the reference oscillator at 25 degrees C). This algorithm is implemented by the LVFRAC-N (U200)
at the power up of the radio.
TCXO Y200, along with its corresponding circuitry R204, R205, R210, and C2053, are not placed as
the temperature compensated crystal proved to be reliable.

4.2

DATA (U403 PIN 100)
CLOCK (U403 PIN 1)
CSX (U403 PIN 2)
MOD IN (U501 PIN 40)
+5V (U503 PIN 1)
+5V (U503 PIN 1)

7
8
9
10
13, 30

5, 20, 34, 36

REFERENCE
OSCILLATOR

23
24

VOLTAGE
MULTIPLIER

FREFOUT

CLK

GND

CEX
MODIN
VCC, DC5V

IOUT
IADAPT

VDD, DC5V

MODOUT

XTAL1

U200

XTAL2

FRACTIONAL-N
SYNTHESIZER

WARP

PREIN

LOCK

DATA

LOW VOLTAGE

VCP
VMULT2
14

43
45

LOOP
FILTER

STEERING
LINE

AUX3

AUX1 BIAS2

FREF (U504 PIN 34)

6, 22, 33, 44

3
1 (NU)

BIAS1

LOCK (U403 PIN 56)

AUX4
AUX2

SFOUT

VMULT1

VCO Bias

LO RF INJECTION

TRB

VOLTAGE
28 FILTERED 5V CONTROLLED
OSCILLATOR
40
TX RF INJECTION
(1ST STAGE OF PA)

BWSELECT

To IF
Section

PRESCALER IN

Figure 2-3 UHF Synthesizer Block Diagram

2-6

THEORY OF OPERATION

4.3

Prescaler Out

TRB IN
Pin 20
Rx-SW

Pin7

Tx-SW

Pin13

(U200 Pin 28)

Pin 19

U200 Pin 32

Pin 12

TX/RX/BS
Switching Network

Vcc-Superfilter
Pin3

LO RF INJECTION

Presc

U201
VCOBIC

Q200
Buffers

Low Pass
Filter

Collector/RF in

Steer Line
Voltage
(VCTRL)

Pin4

RX Tank

RX VCO
Circuit

TX VCO
Circuit

Rx
Active Bias

Pin5
Pin6

TX Tank

Pin8

Pin14

Tx
Active Bias

Pin16
Pin15

Pin10

Vcc-Logic

TX RF Injection
Attenuator

Vsens
Circuit

Pin18

(U200 Pin28)
VCC Buffers

Pin2

Pin1

Rx-I adjust

Tx-I adjust

Pins 9,11,17

(U200 Pin 28)

Figure 2-4 UHF VCO Block Diagram

The VCOBIC together with the LVFRAC-N (U200) generate the required frequencies in both
transmit and receive modes. The TRB line (U201, pin 19) determines which VCO and buffer is
enabled (high being TX output at pin 10, low being RX output at pin 8). A sample of the signal from
the enabled output is routed from U201, pin 12 (PRESC_OUT), via a low pass filter to U200, pin 32
(PREIN).
A steering line voltage between 3.0V and 10.0V at varactor D204 tunes the TX VCO through the
frequency range of 438-470MHz, and at D203 tunes the RX VCO through the frequency range of
393.15-425.15MHz.
The external RX amplifier is used to increase the output from U201, pin 8 from 3-4 dBm to the
required 10dBm for proper mixer operation. In TX mode, the modulation signal from the LVFRAC-N
(U200, pin 41) is applied to the VCO by way of the modulation circuit D205, R212, R211, C2073.

UHF (438-470MHz) Frequency Synthesizer

4.4

2-7

Synthesizer Operation
The synthesizer consists of a low voltage FRAC-N IC (LVFRAC-N), reference oscillator, charge
pump circuits, loop filter circuit, and DC supply. The output signal (PRESC_OUT) of the VCOBIC
(U201, pin 12) is fed to the PREIN, pin 32 of U200 via a low pass filter which attenuates harmonics
and provides a correct input level to the LVFRAC-N in order to close the synthesizer loop.
The pre-scaler in the synthesizer (U200) is a dual modulus pre-scaler with selectable divider ratios.
The divider ratio of the pre-scaler is controlled by the loop divider, which in turn receives its inputs
via the SPI. The output of the pre-scaler is applied to the loop divider. The output of the loop divider
is connected to the phase detector, which compares the loop divider’s output signal with the
reference signal. The reference signal is generated by dividing down the signal of the reference
oscillator (Y201).
The output signal of the phase detector is a pulsed dc signal that is routed to the charge pump. The
charge pump outputs a current from U200, pin 43 (IOUT). The loop filter (consisting of R224, R217,
R234, C2074, C2078, C2028, and L205) transforms this current into a voltage that is applied the
varactor diodes D203 and D204 for RX and TX respectively. The output frequency is determined by
this control voltage. The current can be set to a value fixed in the LVFRAC-N or to a value
determined by the currents flowing into BIAS 1 (U200, pin 40) or BIAS 2 (U200, pin 39). The
currents are set by the value of R200 or R206 respectively. The selection of the three different bias
sources is done by software programming.
To modulate the synthesizer loop, a two-spot modulation method is utilized via the MODIN (U200,
pin 10) input of the LVFRAC-N. The audio signal is applied to both the A/D converter (low frequency
path) and the balance attenuator (high frequency path). The A/D converter converts the low
frequency analog modulating signal into a digital code which is applied to the loop divider, thereby
causing the carrier to deviate. The balance attenuator is used to adjust the VCO’s deviation
sensitivity to high frequency modulating signals. The output of the balance attenuator is presented
at the MODOUT port of the LVFRAC-N (U200,pin 41) and connected to the VCO modulation
varactor D205.

2-8

5.0

THEORY OF OPERATION

External
Microphone

To Synthesizer
Mod
Out
16.8 MHz
Reference Clock
from Synthesizer

Audio/Signaling
Architecture

Disc Audio

ASFIC_CMP

Internal
Microphone
External
Speaker

Audio
PA
Internal
Speaker

µP Clock

SPI

To RF Section
Digital
Architecture

SCI to
Accessory &
Control Head
Connector

RAM
EEPROM

3.3V
Regulator

HC11FL0

FLASH

Figure 2-5 Controller Block Diagram

5.1

Radio Power Distribution
Voltage distribution is provided by five separate devices:
•

U514 P-cH FET - Batt + (Ext_SWB+)

•

U501 LM2941T - 9.3V

•

U503 LP2951CM - 5V

•

U508 MC 33269DTRK - 3.3V

•

U510 LP2986ILDX - 3.3V Digital

Handset

Controller Theory of Operation

2-9

The DC voltage applied to connector P2 supplies power directly to the following circuitry:
•

Electronic on/off control

•

RF power amplifier

•

12 volts P-cH FET -U514

•

9.3 volt regulator

•

Audio PA

Ignition

Auto
On/Off
Switch
Control

B+

Control Head
RF_PA, 8.5A
Audio_PA

Mic Connector

Ferrite Bit
Filt_B+

Antenna Switch
Power Control

500mA

FET
P-CH
On/Off
Control

SW_Filt_B+

10.9-16.3V
0.9A

Status LEDs

7_Seg

7_Seg
DOT

Bed
to
7-Seg

Back
light

Shift
Reg

Acces Conn
Audio PA_Soutdown
Power Loop Op_Amp
9.3V
65mA

U501
9.3V Regulator

Keypad

Mic Bias
9V, 5mA

0.85A

Reset

9.3V
45mA

On/Off
Control

U503
5V RF Regulator
500mA
Rx_Amp
PA_Pre-driver
PA Driver

3.2V
72mA

45mA
LVFRAC_N
IF_Amp

9.3V
75mA

9.3V
162mA

U508
3.3V RF Reg
50mA

25mA
ASFIC_CMP
IFIC
RX Cct

U510
3.3V D Reg
90mA
micro P
RAM
Flash
EEPROM

2-10

THEORY OF OPERATION

Voltage regulator U503 provides 5V for the RF circuits. Input and output capacitors are used to
reduce the high frequency noise and provide proper operation during battery transients.
VSTBY is used only for GM3689 5-tone radios.
The voltage VSTBY, which is derived directly from the supply voltage by components R5103 and
VR502, is used to buffer the internal RAM. Capacitor C5120 allows the battery voltage to be
disconnected for a couple of seconds without losing RAM parameters. Dual diode D501 prevents
radio circuitry from discharging this capacitor. When the supply voltage is applied to the radio,
C5120 is charged via R5103 and D501.

5.2

Protection Devices
Diode VR500 acts as protection against ESD, wrong polarity of the supply voltage, and load dump.
VR692 - VR699 are for ESD protection.

5.3

Automatic On/Off
The radio can be switched ON in any one of the following three ways:

5.3.1

•

On/Off switch. (No Ignition Mode)

•

Ignition and On/Off switch (Ignition Mode)

•

Emergency

5.3.2

Controller Theory of Operation

5.3.3

2-11

5.4

2-12

5.5

THEORY OF OPERATION

5.6

5.7

PROG IN 3 can be used as external PTT input, or others, set by the CPS. The µP reads this
port via pin 72 and Q412.

•

PROG OUT 4 can be used as external alarm output, set by the CPS. Transistor Q401 is
controlled by the µP (U403 pin 55)

•

PROG IN 6 can be used as normal input, set by the CPS. The µP reads this port via pin 73
and Q411. This pin is also used to communicate with the RIB if resistor R421 is placed.

•

Controller Theory of Operation

5.8

2-13

2-14

5.9

THEORY OF OPERATION

6.0

Control Board Audio and Signalling Circuits

6.1

Audio Signalling Filter IC and Compander (ASFIC CMP)
The ASFIC CMP (U504) used in the controller has the following four functions:
1.

RX/TX audio shaping, i.e. filtering, amplification, attenuation

RX/TX signaling, PL/DPL/HST/MDC

Squelch detection

µP clock signal generation

GCBO - BW Select

•

GCBI - switches the audio PA On/Off

•

GCB2 - DC Power On switches the voltage regulator (and the radio) on and off

•

GCB3 - Control on MUX U509 pin 9 to select between Low Cost Mic path to STD Mic Path

•

GCB4 - Control on MUX U509 pin 11 to select between Flat RX path to filtered RX path on the
accessory connector.

•

GCB5 - Control on MUX U509 pin 10 to select between Flat TX path mute and Flat TX path

Transmit Audio Circuits

7.0

2-15

Transmit Audio Circuits

24kOhms

U509

MIC

46
35

FLAT TX
AUDIO

MIC
INT

GCB3
MIC
EXT

U509

36
TX RTN

MUX

CONTROL HEAD
CONNECTOR

EXT MIC

44
TX SND

MUX

AUX
TX
ACCESSORY
CONNECTOR

FILTERS AND
PREEMPHASIS
MIC
ASFIC_CMP
IN
U504 LIMITER
HS SUMMER
SPLATTER
FILTER
LS SUMMER

GCB5

FLAT TX
AUDIO MUTE

VCO
ATN
ATTENUATOR

MOD IN
40

TO
RF
SECTION
(SYNTHESIZER)

Figure 2-7 Transmit Audio Paths

7.1

7.1.1

2-16

7.1.2

THEORY OF OPERATION

7.2

Transmit Signalling Circuits

8.0

2-17

Transmit Signalling Circuits

HS
SUMMER

MICRO
CONTROLLER

U403

19 HIGH SPEED
CLOCK IN
(HSIO)

DTMF
ENCODER

SPI
BUS

SPLATTER
FILTER

ASFIC_CMP U504

5-3-2 STATE
ENCODER

LOW SPEED
CLOCK IN
(LSIO)

PL
ENCODER

LS
SUMMER
ATTENUATOR

40
MOD IN

TO RF
SECTION
(SYNTHESIZER)

Figure 2-8 Transmit Signalling Path
From a hardware point of view, there are 3 types of signaling:
•

Sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or
signaling,

•

DTMF data for telephone communication in trunked and conventional systems, and

•

Audible signaling including MDC and high-speed trunking.

Note: All three types are supported by the hardware while the radio software determines which
signaling type is available.

8.1

2-18

8.2

THEORY OF OPERATION

8.3

Receive Audio Circuits

9.0

2-19

Receive Audio Circuits
ACCESSORY
CONNECTOR
11

1
AUDIO
PA
U502
9

SPKR +

SPKR -

EXTERNAL
SPEAKER

INT
SPKR+

INT
SPKRCONTROL HEAD
CONNECTOR
19

MUTE

U509

FLT RX AUDIO

INTERNAL
SPEAKER

20
J2

HANDSET
AUDIO

U505
37

10
GCB4 U IO

43 AUX RX

URX OUT AUDIO

GCB1

VOLUME
ATTEN.

ASFIC_CMP
U504

FILTER AND
DEEMPHASIS

DISC
FROM
AUDIO
RF
SECTION
(IF IC)

2 DISC

PL FILTER
LIMITER
LIMITER, RECTIFIER
FILTER, COMPARATOR

LS IO

SQUELCH
CIRCUIT
SQ DET

CH ACT

MICRO
CONTROLLER

U403

Figure 2-9 Receive Audio Paths

9.1

2-20

9.2

THEORY OF OPERATION

9.3

Receive Signalling Circuits

9.4

2-21

9.5

10.0

Receive Signalling Circuits

DATA FILTER
AND DEEMPHASIS
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF IC)

LIMITER

HSIO 19

82
44

DISC

ASFIC_CMP
U504
FILTER

LIMITER

MICRO
CONTROLLER
U403

LSIO 18

80
85

PLEAP
8

PLCAP2
25

Figure 2-10 Receive Signalling Paths

10.1

2-22

THEORY OF OPERATION

10.2

3-2

1.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for Receiver RF (Sheet 1 of 2)
START

Problem in 12 KHz and
25 KHz channel spacing

Go to
DC Section

9V on Yes
R310 (LNA)
OK
?

Check
RX_EN

Go to
DC Section

3V
to U301
Okay ?

Yes

Check Q306, Q300
and U403

Check Q304, D305
and U403

Go to SYN
Section

Go to
DC Section

RX_EN
ON ?

Yes

LOC_DIST
ON?

Yes

Check
LOC_DIST

Check
TPI

LO
POWER
OK ?

Yes

Check 5V
on R337 )

5V
Yes
(IF AMP)
OK ?

Check 3V
on R339

Go
to A

Check D301-304
Replace IF Filters( FL304, FL301)
If problem in 25 KHz spacing

Troubleshooting Flow Chart for Receiver RF (Sheet 1 of 2)

1.1

3-3

Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
From
A

3V
(IFIC -Vcc)
OK ?

Go to
DC Section

Check
the component

Antenna to Mixer
circuitry problem

Check visually
all receiver
components
installation ?

Yes

Installation
OK ?

Yes

Inject - 40dBm (CW)
to RF connector
Check Power on
C335

RF
Yes
Power
> -28 dBM?

Check Power on
C337

Replace
Q305, Q300, U302
Check passive
components

Replace
Q303, Q301
Check passive
components

No
Replace Y301

No
Go to DC Section

3V to
U301
OK?

Yes

Y301
OK?

Yes

RF
Yes
Power
> -28 dBM?

Replace Q302, Y300
Check D301 - 304

Replace U300

Check Y301
44.395 MHz

3-4

2.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for 40W Transmitter (Sheet 1 of 3)
START

No or too low power when keyed

Check components between
Q100 and RF output,
Antenna Switch D104,
D103, VR102 and Q106

>4A

Current
increase when
keyed?

>500mA & <4A

<500mA
Check PA
Stages

Yes

Control
Voltage at
TP150
>4Vdc?

No
Check 9.3V
Regulator
U501

Voltage U103
pin 5 =
4.7V?

Yes
Check power settings, tuning
& components between U103
Pin 3 and ASFIC Pin 6 before
replacing ASFIC

U103 Pin 3
<1.6Vdc

Yes
Check
U103

Yes

Short U100
Pin 3 to
ground

U100 Pin 3
>1.8Vdc

No
Check forward
Power Sense
Circuit

Check PA
Stages

Yes

Voltage at
TP150 rises?

No
Check Forward
Power Sense
Circuit

Troubleshooting Flow Chart for 40W Transmitter (Sheet 1 of 3)

2.1

3-5

Troubleshooting Flow Chart for 40W Transmitter (Sheet 2 of 3)
Check PA
Stages

No or too low power when keyed

DC
Voltage
at Q101 & Q102
base=0?

Check Q102,
Q101, R122, R165

Check U510

Yes

No
DC
Voltage at
U103 Pin
10=8.9V

<2V

Yes

DC
Voltage
at U103
Pin 8

>5V

Check resistive network at
Pin 9 and 10 of U103
before replacing U101

2 to 5V

Check U103 and Resistive
Network at Pin 10 of U103
before replacing U101

Measure DC Voltage at Pin 2 & 3 of U5401

Pin 2
Voltage
0.62 x Voltage
at Pin 1

No
Replace U5410

Yes
Check bias tuning
before replacing
U504

Pin 3
Voltage
0.51 x Voltage
at Pin 1

No
ASFIC
U504
Pin 5 2-3V

Yes
Check components between ASFIC and Q105
before replacing Q105

No
Replace U5410

Yes
DC
Voltage at Supply Voltage
PA_CURRENT
line?
2-3V
Check Final PA Stages

Replace Q105

3-6

2.2

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for 40W Transmitter (Sheet 3 of 3)
Check Final PA Stage

Check components
between ASFIC &
Q100 before replacing Q100

Yes

PA_Bias
Voltage at
R134

Supply Voltage

Replace Q100

1-4V
RF Voltage
after C1044
>100mV?

RF Voltage
after C1044
>100mV?

Check FGU (U5301)

No
Check Bias Tuning
before replacing
ASFIC U504

Yes

Voltage
across R122
>2V?

Check components
between C1044 &
C1117

Check components
between C117 &
Q105

Check components
between Q105 &
Q100

Yes

RF Voltage
Q105 gate
>1V?

Yes

RF Voltage
Q100 gate
>7V?

Yes
Check components
between Q100 &
antenna connector

Troubleshooting Flow Chart for Synthesizer

3.0

3-7

Troubleshooting Flow Chart for Synthesizer
Start

Correct
Problem

Check D200, D201,
C2026, C2025, &
C2027

3.3V
at U200
pins 5, 20, 34
& 36

Visual
check of the
Board
OK?

Check 3V
Regulator
U503

YES

YES
YES
5V
at pin 6 of
D200

Is
U200 Pin 47
at = 14.6VDC
?

+5V
at U200
Pin’s
13 & 30
?

YES

Check
R228

Check R201

Is
U201 Pin 19
<40 mVDC in RX &
>4.5 VDC in TX?
(at VCO section)
?

Are
Waveforms
at Pins 14 & 15
triangular
?

YES
NO

Is
there a short
between Pin 47 and
Pins 14 & 15 of
U200
?

Check programming
lines between
U403 and U200
Pins 7,8 & 9

NO
YES
Remove
Shorts
Is
RF level at
U200 Pin 32
-12 < x <-25
dBm
?
YES

Replace U200

Replace
U200

YES

NO
Replace U200

YES

Check
Y201 and associated
Parts
Are
signals
at Pin’s 14 &15
of U200
?
YES

Is
U200
Pin 2 >4.5 VDC in
Tx & <40 mVDC
in Rx
?

Is
16.8MHz
signal at
U200 Pin
23?

Check 5V
Regulator
U503

YES

Is
16.8MHz
Signal at U200
Pin 19
?

If C2052, R208,C2067,
C2068, L210 are OK, then
see VCO
troubleshooting chart

Check uP U403
Troubleshooting
Chart

Do
Pins 7,8 & 9
of U200 toggle
when channel is
changed?

YES

Is
information
from uP U403
correct
?
YES

Replace U200

3-8

TROUBLESHOOTING CHARTS

4.0

Troubleshooting Flow Chart for VCO

RX VCO

Low or no RF Signal
at input to PA

Low or no RF Signal
at TP1

Visual check
of board
OK?

Correct
Problem

Visual check
of board
OK?
YES

YES
Make sure Synthesizer is
working correctly and runner
between U200 Pin 28 and
U201 Pin 14 & 18 is OK

4.5V DC
at U201 Pin 14 & 18
OK ?

YES

YES
370mV DC at
U201 Pin 19
OK?

TX VCO

Check runner
between U200 Pin 2
and U201 Pin 19

4.5V DC at
U201 Pin 19
OK?

YES

Is RF available
at base of Q200

YES

Are U201 Pins
15 at 1.0V
10 at 3.9V
16 at 1.8V

Replace U201

YES

Are Q200
Base at 2.9V
Collector at 6.6V
Emitter at 2.2V

If all parts
associated
with the pins
are OK,
replace U201

YES

If all parts associated
with the pins are OK,
replace Q200

Is RF available
at C2060

If parts between
R109 & U201 Pin10
are OK, replace U201

YES

YES
Check parts to pre-driver

If all parts from collector
of Q200 to TP1 are
OK, replace Q200

Power OK but
no modulation

Audio =180mVRMS
at “-” Side of

NO
Replace R212

D205

YES

4.5VDC
at D205

YES

If R211 and R12 are OK,
then replace D205

Replace R211

Troubleshooting Flow Chart for DC Supply (1 of 2)

5.0

3-9

Go to 3V

Replace U503

Yes

V=5V
?

9v 1 GHz

Adjacent Channel Power

-60dB @12.5,
-70dB @ 20/25kHz

Audio Response:
( 300 to 3000Hz)

+1, -3dB

Audio Distortion:
@ 1000 Hz, 60%
Rated Maximum Deviation:

3% Typical

VHF2
0.35µV (12.5kHz) 0.30µV (25kHz) Typical
>65dB
75 dB @ 25 kHz
65 dB @ 12.5 kHz
75 dB
4W Internal , 13W External
3% Typical

Hum and Noise:

-40 dB @ 12.5 kHz
-45 dB @ 20/25 kHz

Audio Response:
( 300 to 3000Hz)

+1, -3dB

Conducted Spurious
Emission per FCC Part 15:

-57 dBm <1 GHz
-47 dBm >1 GHz

*Availability subject to the laws and regulations of individual countries.

1-4

MODEL CHART AND TECHNICAL SPECIFICATIONS

Chapter 2
THEORY OF OPERATION
1.0

2.0

VHF (146-174MHz) Receiver

2.1

Antenna
Front Filter

12.5kHzFilter 12.5kHzFilter
LNA

Second Filter

Mixer

4- Pole
Xtal Filter

IF Amp

First LO

25kHzFilter

IFIC

2nd LO Xtal Osc

Phase Shift
Element
Controller

Figure 2-1 VHF Receiver Block Diagram

2-2

THEORY OF OPERATION

2.2

3.0

VHF Transmitter Power Amplifier (146-174 MHz)
The radio’s 45W PA is a three-stage amplifier used to amplify the output from the TX_INJ to the
antenna port. All three stages utilize LDMOS technology. The gain of the first stage (U101) is
adjustable and is controlled by pin 7 of U103-2 via U103-3 and U102-1. It is followed by an LDMOS
driver Q105 and final stage Q100.

Pin Diode
Antenna
Switch

From VCO (TX_INJ)
Controlled
Stage

PA-Final
Stage

Driver

Harmonic
Filter
RF Jack

Coupler

Bias

Antenna

Forward

A S FI C _C M P
SPI BUS

PA
PWR
SET
L oo p
C ont r ol le r
U 103 - 2

Temperature
Sense

Figure 2-2 VHF Transmitter Block Diagram
Devices U101, Q105 and Q100 are surface mounted.Two screws with Belleville washers provide
direct pressure ensuring good thermal contact between both the driver and final stage, and the
chassis.

3.1

VHF Transmitter Power Amplifier (146-174 MHz)

2-3

3.2

Power Controlled Driver Stage
The next stage is an LDMOS device (Q105) which provides a gain of 12dB. This device requires a
positive gate bias and a quiescent current flow for proper operation. The bias is set during transmit
mode by the V_cntrl_driver which is set to provide 100-150mA of quiescent current by the factory,
and fed to the gate of Q105 via the resistive network.
The V_cntrl_driver is directly controlled by the ASFIC CMP. In receive mode, the ASFIC CMP
(U504) sets V_cntrl_driver to 0V (DACR pin 5).

3.3

Final Stage
The final stage is an LDMOS device (Q100) providing a gain of 12dB. This device also requires a
positive gate bias and a quiescent current flow for proper operation. The voltage of the line PA_BIAS
is set in transmit mode by the ASFIC and fed to the gate of Q100 via the resistive network R134,
R131. This bias voltage is tuned in the factory. If the transistor is replaced, the bias voltage must be
tuned using the Tuner. Care must be taken not to damage the device by exceeding the maximum
allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC supply voltage
input, B+, via L117 and L115.
A matching network consisting of C1004-5, C1007-9, C1096, C1021, C1013, C1019, L116: and two
striplines, transforms the impedance to 50 ohms and feeds the directional coupler.

3.4

3.5

2-4

3.6

THEORY OF OPERATION

Harmonic Filter
Inductors L111, L112, L124 and L113 along with capacitors C11321, C1022, C1020, C1137, C1018
and C1017 form a low-pass filter to attenuate harmonic energy coming from the transmitter.
Resistor R150 drains any electrostatic charges that might otherwise build up on the antenna. The
harmonic filter also prevents high level RF signals above the receiver passband from reaching the
receiver circuits to improve spurious response rejection.

3.7

Power Control
The output power is regulated by using a forward power detection control loop. A directional coupler
samples a portion of the forward and reflected RF power. The forward sampled RF is rectified by
diode D105, and the resulting DC voltage is routed to the operational amplifier U100. The error
output current is then routed to an integrator, and converted into the control voltage. This voltage
controls the bias of the pre-driver (U101) stage. The output power level is set by way of a DAC,
PWR_SET, in the audio processing IC (U504), which acts at the forward power control loop
reference.
The sampled reflected power is rectified by diode D107. The resulting DC voltage is amplified by an
operational amplifier U100 and routed to the summing junction. This detector protects the final stage
Q100 from reflected power by increasing the error current. The temperature sensor protects the
final stage Q100 from overheating by increasing the error current. A thermistor RT100 measures the
final stage Q100 temperature. The voltage divider output is routed to an operational amplifier U103
and then goes to the summing junction. The Zener Diode VR101 keeps the loop control voltage
below 5.6V and eliminates the DC current from the 9.3 regulator U501.
A local loop for the Pre Driver (U101) is used in order to stabilize the current for each stage.
In Rx mode, the two transistors Q101 and Q102 go to saturation and shut down the transmitter by
applying ground to the Pre Driver U101.

4.0

4.1

VHF (146-174MHz) Frequency Synthesis

2-5

4.2

DATA (U403 PIN 100)
CLOCK (U403 PIN 1)
CSX (U403 PIN 2)
MOD IN (U501 PIN 40)
+5V (U503 PIN 1)
+5V (U503 PIN 1)

7
8
9
10
13, 30

5, 20, 34, 36

REFERENCE
OSCILLATOR

23
24

VOLTAGE
MULTIPLIER

FREFOUT

CLK

GND

CEX
MODIN
VCC, DC5V

IOUT
IADAPT

VDD, DC5V

MODOUT

XTAL1

U200

XTAL2

FRACTIONAL-N
SYNTHESIZER

WARP

PREIN

LOCK

DATA

LOW VOLTAGE

VCP
VMULT2
14

43
45

LOOP
FILTER

STEERING
LINE

AUX3

AUX1 BIAS2

FREF (U504 PIN 34)

6, 22, 33, 44

3
1

BIAS1

LOCK (U403 PIN 56)

AUX4
AUX2

SFOUT

VMULT1

VCO Bias

LO RF INJECTION

TRB

VOLTAGE
28 FILTERED 5V CONTROLLED
OSCILLATOR
40
TX RF INJECTION
(1ST STAGE OF PA)

BWSELECT

To IF
Section

PRESCALER IN

Figure 2-3 VHF Synthesizer Block Diagram

2-6

THEORY OF OPERATION

4.3

Prescaler Out

TRB IN
Pin 20
Rx-SW

Pin7

Tx-SW

Pin13

(U200 Pin 28)

Pin 19

U200 Pin 32

Pin 12

TX/RX/BS
Switching Network

Vcc-Superfilter
Pin3

LO RF INJECTION

Presc

U201
VCOBIC

Q200
Buffer

Low Pass
Filter

Collector/RF in

Steer Line
Voltage
(VCTRL)

Pin4

RX Tank

RX VCO
Circuit

TX VCO
Circuit

Rx
Active Bias

Pin5
Pin6

TX Tank

Pin8

Pin14

Tx
Active Bias

Pin16
Pin15

Pin10

Vcc-Logic

TX RF Injection
Attenuator

Vsens
Circuit

Pin18

(U200 Pin28)
VCC Buffers

Pin2

Pin1

Rx-I adjust

Tx-I adjust

Pins 9,11,17

(U200 Pin 28)

Figure 2-4 VHF VCO Block Diagram

The VCOBIC together with the LVFRAC-N (U200) generate the required frequencies in both
transmit and receive modes. The TRB line (U201, pin 19) determines which VCO and buffer is
enabled (high being TX output at pin 10, low being RX output at pin 8). A sample of the signal from
the enabled output is routed from U201, pin 12 (PRESC_OUT), via a low pass filter to U200, pin 32
(PREIN).
A steering line voltage between 3.0V and 10.0V at varactor D204 tunes the TX VCO through the
frequency range of 146-174MHz, and at D203 tunes the RX VCO through the frequency range of
190-219MHz.
The external RX amplifier is used to increase the output from U201, pin 9 from 3-4 dBm to the
required 15dBm for proper mixer operation. In TX mode, the modulation signal from the LVFRAC-N
(U200, pin 41) is applied to the VCO by way of the modulation circuit D205, R212, R211, C2073.

VHF (146-174MHz) Frequency Synthesis

4.4

2-7

2-8

5.0

THEORY OF OPERATION

External
Microphone

To Synthesizer
Mod
Out
16.8 MHz
Reference Clock
from Synthesizer

Audio/Signaling
Architecture

Disc Audio

ASFIC_CMP

Internal
Microphone
External
Speaker

Audio
PA
Internal
Speaker

µP Clock

SPI

To RF Section
Digital
Architecture

SCI to
Accessory &
Control Head
Connector

RAM
EEPROM

3.3V
Regulator

HC11FL0

FLASH

Figure 2-5 Controller Block Diagram

5.1

Radio Power Distribution
Voltage distribution is provided by five separate devices:
■

U514 P-cH FET - Batt + (Ext_SWB+)

■

U501 LM2941T - 9.3V

■

U503 LP2951CM - 5V

■

U508 MC 33269DTRK - 3.3V

■

U510 LP2986ILDX - 3.3V Digital

Handset

Controller Theory of Operation

2-9

The DC voltage applied to connector P2 supplies power directly to the following circuitry:
■

Electronic on/off control

■

RF power amplifier

■

12 volts P-cH FET -U514

■

9.3 volt regulator

■

Audio PA

Ignition

Auto
On/Off
Switch
Control

B+

Control Head
RF_PA
Audio_PA

Mic Connector

Ferrite Bit
Filt_B+

Antenna Switch
Power Control

500mA

FET
P-CH
On/Off
Control

SW_Filt_B+

11-16.6V
0.9A

Status LEDs

7_Seg

7_Seg
DOT

Bed
to
7-Seg

Back
light

Shift
Reg

Acces Conn
Audio PA_Soutdown
Power Loop Op_Amp
9.3V
65mA

U501
9.3V Regulator

Keypad

Mic Bias
9V, 5mA

0.85A

Reset

9.3V
45mA

On/Off
Control

U503
5V RF Regulator
500mA
Rx_Amp
PA_Pre-driver
PA Driver

3.2V
72mA

45mA
LVFRAC_N
IF_Amp

9.3V
75mA

9.3V
162mA

U508
3.3V RF Reg
50mA

25mA
ASFIC_CMP
IFIC
RX Cct

U510
3.3V D Reg
90mA
micro P
RAM
Flash
EEPROM

2-10

THEORY OF OPERATION

5.2

Protection Devices
Diode VR500 acts as protection against ESD, wrong polarity of the supply voltage, and load dump.
VR692 - VR699 are for ESD protection.

5.3

Automatic On/Off
The radio can be switched ON in any one of the following three ways:

5.3.1

■

On/Off switch. (No Ignition Mode)

■

Ignition and On/Off switch (Ignition Mode)

■

Emergency

5.3.2

Controller Theory of Operation

5.3.3

2-11

5.4

2-12

5.5

THEORY OF OPERATION

Serial Peripheral Interface (SPI)
The µP communicates to many of the IC’s through its SPI port. This port consists of SPI TRANSMIT
DATA (MOSI) (U403-pin100), SPI RECEIVE DATA (MISO) (U403-pin 99), SPI CLK (U0403-pin1)
and chip select lines going to the various IC’s, connected on the SPI PORT (BUS). This BUS is a
synchronous bus, in that the timing clock signal CLK is sent while SPI data (SPI TRANSMIT DATA
or SPI RECEIVE DATA) is sent. Therefore, whenever there is activity on either SPI TRANSMIT
DATA or SPI RECEIVE DATA there should be a uniform signal on CLK. The SPI TRANSMIT DATA
is used to send serial from a µP to a device, and SPI RECEIVE DATA is used to send data from a
device to a µP.
In the controller section, there are two IC’s on the SPI BUS, ASFIC CMP (U504 pin 22), and
EEPROM (U400). In the RF sections there is one IC on the SPI BUS, the FRAC-N Synthesizer. The
chip select line CSX from U403 pin 2 is shared by the ASFIC CMP and FRAC-N Synthesizer. Each
of these IC’s check the SPI data and when the sent address information matches the IC’s address,
the following data is processed.
When the µP needs to program any of these Is it brings the chip select line CSX to a logic “0” and
then sends the proper data and clock signals. The amount of data sent to the various IC’s are
different; e.g., the ASFIC CMP can receive up to 19 bytes (152 bits). After the data has been sent
the chip select line is returned to logic “1”.

5.6

5.7

PROG IN 3 can be used as external PTT input, or others, set by the CPS. The µP reads this
port via pin 72 and Q412.

■

PROG OUT 4 can be used as external alarm output, set by the CPS. Transistor Q401 is
controlled by the µP (U403 pin 55)

■

PROG IN 6 can be used as normal input, set by the CPS. The µP reads this port via pin 73
and Q411. This pin is also used to communicate with the RIB if resistor R421 is placed.

■

Controller Theory of Operation

5.8

2-13

Normal Microprocessor Operation
For this radio, the µP is configured to operate in one of two modes, expanded and bootstrap. In
expanded mode the µP uses external memory devices to operate, whereas in bootstrap operation
the µP uses only its internal memory. In normal operation of the radio the µP is operating in
expanded mode as described below.
During normal operation, the µP (U403) is operating in expanded mode and has access to 3
external memory devices; U400 (EEPROM), U402 (SRAM), U404 (Flash). Also, within the µP there
are 3 Kilobytes of internal RAM, as well as logic to select external memory devices.
The external EEPROM (U400) space contains the information in the radio which is customer
specific, referred to as the codeplug. This information consists of items such as: 1) what band the
radio operates in, 2) what frequencies are assigned to what channel, and 3) tuning information.
The external SRAM (U402) as well as the µP’s own internal RAM space are used for temporary
calculations required by the software during execution. All of the data stored in both of these
locations is lost when the radio powers off.
The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of 8 data
lines (DATA 0 - DATA 7). There are also 3 control lines; CSPROG (U403-38) to chip select U404-pin
30 (FLASH), CSGP2 (U403-pin 41) to chip select U404-pin 20 (SRAM) and PG7_R_W (U403-pin 4)
to select whether to read or to write.
When the µP is functioning normally, the address and data lines should be toggling at CMOS logic
levels. Specifically, the logic high levels should be between 3.1 and 3.3V, and the logic low levels
should be between 0 and 0.2V. No other intermediate levels should be observed, and the rise and
fall times should be <30ns.
The low-order address lines (ADDR 0 - ADDR 7) and the data lines (DATA 0-DATA 7) should be
toggling at a high rate, e.g., you should set your oscilloscope sweep to 1us/div. or faster to observe
individual pulses. High speed CMOS transitions should also be observed on the µP control lines.
On the µP the lines XIRQ (U403-pin 48), MODA LIR (U403-pin 58), MODB VSTPY (U403-pin 57)
and RESET (U403-pin 94) should be high at all times during normal operation. Whenever a data or
address line becomes open or shorted to an adjacent line, a common symptom is that the RESET
line goes low periodically, with the period being in the order of 20ms. In the case of shorted lines you
may also detect the line periodically at an intermediate level, i.e. around 2.5V when two shorted
lines attempt to drive to opposite rails.
The MODA LIR (U403-pin 58) and MODB VSTPY (U403-pin 57) inputs to the µP must be at a logic
“1” for it to start executing correctly. After the µP starts execution it will periodically pulse these lines
to determine the desired operating mode. While the Central Processing Unit (CPU) is running,
MODA LIR is an open-drain CMOS output which goes low whenever the µP begins a new
instruction. An instruction typically requires 2-4 external bus cycles, or memory fetches.
There are eight analog-to-digital coverter ports (A/D) on U403 labelled within the device block as
PEO-PE7. These lines sense the voltage level ranging from 0 to 3.3V of the input line and convert
that level to a number ranging from 0 to 255 which is read by the software to take appropriate action.

2-14

5.9

THEORY OF OPERATION

Static Random Access Memory (SRAM)
The SRAM (U402) contains temporary radio calculations or parameters that can change very
frequently, and which are generated and stored by the software during its normal operation. The
information is lost when the radio is turned off.
The device allows an unlimited number of write cycles. SRAM accesses are indicated by the CS
signal U402 (which comes from U403-CSGP2) going low. U402 is commonly referred to as the
external RAM as opposed to the internal RAM which is the 3 kilobytes of RAM which is part of the
68HC11FL0. Both RAM spaces serve the purpose. However, the internal RAM is used for the
calculated values which are accessed most often.
Capacitor C402 and C411 serves to filter out any AC noise which may ride on +3.3 V at U402

6.0

Control Board Audio and Signalling Circuits

6.1

Audio Signalling Filter IC and Compander (ASFIC CMP)
The ASFIC CMP (U504) used in the controller has the following four functions:
1.

RX/TX audio shaping, i.e. filtering, amplification, attenuation

RX/TX signaling, PL/DPL/HST/MDC

Squelch detection

µP clock signal generation

GCBO - BW Select

■

GCBI - switches the audio PA On/Off

■

GCB2 - DC Power On switches the voltage regulator (and the radio) on and off

■

GCB3 - Control on MUX U509 pin 9 to select between Low Cost Mic path to STD Mic Path

■

GCB4 - Control on MUX U509 pin 11 to select between Flat RX path to filtered RX path on the
accessory connector.

■

GCB5 - Control on MUX U509 pin 10 to select between Flat TX path mute and Flat TX path

Transmit Audio Circuits

7.0

2-15

Transmit Audio Circuits

24kOhms

U509

MIC

46
35

FLAT TX
AUDIO

MIC
INT

GCB3
MIC
EXT

U509

36
TX RTN

MUX

CONTROL HEAD
CONNECTOR

EXT MIC

44
TX SND

MUX

AUX
TX
ACCESSORY
CONNECTOR

FILTERS AND
PREEMPHASIS
MIC
ASFIC_CMP
IN
U504 LIMITER
HS SUMMER
SPLATTER
FILTER
LS SUMMER

GCB5

FLAT TX
AUDIO MUTE

VCO
ATN
ATTENUATOR

MOD IN
40

TO
RF
SECTION
(SYNTHESIZER)

Figure 2-7 Transmit Audio Paths

7.1

7.1.1

Low Cost Microphone
Hook Pin is shorted to Pin 1(9.3V) inside the Low Cost Mic, This routes 9.3V to R429, and creates
2.6V on MIC_SENSE (u.P U403-67) by Voltage Divider R429/R430. U403 senses this voltage and
sends command to ASFIC_CMP U504 to get GCB3 = ‘0’. The audio signal is routed from C5045 via
U509-5 (Z0), R5072, U507, R5026, C5091, R5014 via C5046 to U504- 46 int. mic (C5046 100nF
creates a 159Hz pole with U504- 46 int mic impedance of 16k ohm).

2-16

7.1.2

THEORY OF OPERATION

7.2

Transmit Signalling Circuits

8.0

2-17

Transmit Signalling Circuits

HS
SUMMER

MICRO
CONTROLLER

U403

19 HIGH SPEED
CLOCK IN
(HSIO)

DTMF
ENCODER

SPI
BUS

SPLATTER
FILTER

ASFIC_CMP U504

5-3-2 STATE
ENCODER

LOW SPEED
CLOCK IN
(LSIO)

PL
ENCODER

LS
SUMMER
ATTENUATOR

40
MOD IN

TO RF
SECTION
(SYNTHESIZER)

Figure 2-8 Transmit Signalling Path
From a hardware point of view, there are 3 types of signaling:
■

Sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or
signaling,

■

DTMF data for telephone communication in trunked and conventional systems, and

■

Audible signaling including MDC and high-speed trunking.

Note: All three types are supported by the hardware while the radio software determines which
signaling type is available.

8.1

2-18

8.2

THEORY OF OPERATION

8.3

Receive Audio Circuits

9.0

2-19

Receive Audio Circuits
ACCESSORY
CONNECTOR
11

1
AUDIO
PA
U502
9

SPKR +

SPKR -

EXTERNAL
SPEAKER

INT
SPKR+

INT
SPKRCONTROL HEAD
CONNECTOR
19

MUTE

U509

FLT RX AUDIO

INTERNAL
SPEAKER

20
J2

HANDSET
AUDIO

U505
37

10
GCB4 U IO

43 AUX RX

URX OUT AUDIO

GCB1

VOLUME
ATTEN.

ASFIC_CMP
U504

FILTER AND
DEEMPHASIS

DISC
FROM
AUDIO
RF
SECTION
(IF IC)

2 DISC

PL FILTER
LIMITER
LIMITER, RECTIFIER
FILTER, COMPARATOR

LS IO

SQUELCH
CIRCUIT
SQ DET

CH ACT

MICRO
CONTROLLER

U403

Figure 2-9 Receive Audio Paths

9.1

2-20

9.2

THEORY OF OPERATION

9.3

Receive Signalling Circuits

9.4

2-21

9.5

10.0

Receive Signalling Circuits

DATA FILTER
AND DEEMPHASIS
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF IC)

LIMITER

HSIO 19

82
44

DISC

ASFIC_CMP
U504
FILTER

LIMITER

MICRO
CONTROLLER
U403

LSIO 18

80
85

PLEAP
8

PLCAP2
25

Figure 2-10 Receive Signalling Paths

10.1

2-22

THEORY OF OPERATION

10.2

3-2

1.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for Receiver RF (Sheet 1 of 2)
START

Problem in 12 KHz and
25 KHz channel spacing

Yes

Go to
DC Section

9V on Yes
R310 (LNA)
OK?

Check
RX_EN

Go to
DC Section

3V
to U301
Okay ?

Yes

Check Q306, Q300
and U403

Check Q304, D305
and U403

Go to SYN
Section

Go to
DC Section

RX_EN
ON ?

Yes

LOC_DIST
ON?

Yes

Check
LOC_DIST

Check
TP1

LO
POWER
OK ?

Yes

Check 5V
on R336

5V
Yes
(IF AMP)
OK ?

Check 3V
on R338

Go
to A

Check D301-304
Replace IF Filters( FL304, FL301)
If problem in 25 KHz spacing

Troubleshooting Flow Chart for Receiver RF (Sheet 1 of 2)

1.1

3-3

Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
From
A

3V
(IFIC -Vcc)
OK ?

Go to
DC Section

Check
the component

Antenna to Mixer
circuitry problem

Check visually
all receiver
components
installation ?

Yes

Installation
OK ?

Yes

Inject - 40dBm (CW)
to RF connector
Check Power on
C332

RF
Yes
Power
> -28 dBM?

Check Power on
C336

Replace
Q305, Q300, U302
Check passive
components

Replace
Q303, Q301
Check passive
components

No
Replace Y301

No
Go to DC Section

3V to
U301
OK?

Yes

Y301
OK?

Yes

RF
Yes
Power
> -28 dBM?

Replace Q302, Y300
Check D301 - 304

Replace U300

Check Y301
44.395 MHz

3-4

2.0

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for 45W Transmitter (Sheet 1 of 3)
START

No or too low power when keyed

Check components between
Q100 and RF output,
Antenna Switch D104,
D103, VR102 and Q106

>4A

Current
increase when
keyed?

>500mA & <4A

<500mA
Check PA
Stages

Yes

Control
Voltage at
TP150
>4Vdc?

No
Check 9.3V
Regulator
U501

Voltage U103
pin 5 =
4.6V?

Yes
Check power settings, tuning
& components between U103
Pin 3 and ASFIC Pin 6 before
replacing ASFIC

U103 Pin 3
<1.6Vdc

Yes
Check
U103

Yes

Short U100
Pin 3 to
ground

U100 Pin 3
>1.8Vdc

No
Check forward
Power Sense
Circuit

Check PA
Stages

Yes

Voltage at
TP150 rises?

No
Check Forward
Power Sense
Circuit

Troubleshooting Flow Chart for 45W Transmitter (Sheet 1 of 3)

2.1

3-5

Troubleshooting Flow Chart for 45W Transmitter (Sheet 2 of 3)
Check PA
Stages

No or too low power when keyed

DC
Voltage
at Q101
base=0?

Check Q101, R122,
R197, R153, R136,
R165, R168,

Yes

No
DC
Voltage at
U103 Pin
10=8.9V

<2V

DC
Voltage
at U103
Pin 8

>5V

Yes
Check U103 before replacing U101

2 to 5V

DC
Voltage at
C1095

Check bias tuning
before replacing
U504

No
ASFIC
U504
Pin 5 2-3V

2-3V

Yes
Check components between ASFIC and Q105
before replacing Q105

Check U510

Check Final PA Stages

Check resistive network at
Pin 9 and 10 of U103
before replacing U101

3-6

2.2

TROUBLESHOOTING CHARTS

Troubleshooting Flow Chart for 45W Transmitter (Sheet 3 of 3)
Check Final PA Stage

Check components
between ASFIC &
Q100 before replacing Q100

Yes

PA_Bias
Voltage at
R134

Supply Voltage

Replace Q100

1-4Vdc
RF Voltage
after C1044
>100mV?

RF Voltage
after C1044
>100mV?

Check FGU

No
Check Bias Tuning
before replacing
ASFIC U504

Yes

Voltage
across R122
>2V?

Check components
between C1044 &
C1117

Check components
between C1117 &
Q105

Check components
between Q105 &
Q100

Yes

RF Voltage
Q105 gate
>1V?

Yes

RF Voltage
Q100 gate
>1.5V?

Yes
Check components
between Q100 &
antenna connector

Troubleshooting Flow Chart for Synthesizer

3.0

3-7

Troubleshooting Flow Chart for Synthesizer

3V at
U200 pins 5,
20, 34 & 36

Start

Check 3V
Regulator
U508

Yes
No

Correct
Problem

Visual
check of the
Board OK?
Yes

Yes

5V
at pin 6 of
D200

Yes

Is U200
Pin 47
= 13VDC?

+5V at
U200 Pins
13 & 30?

Is 16.8MHz
Signal at
U200 Pin 19?

Is
16.8MHz
signal at
U200 pin
23?

Yes

Yes
Replace
U200

Yes
Check
Y201 and associated
parts

Check 5V
Regulator
U503

Check
R228

Is U201 Pin 19
<40 mVDC in RX &
>4.5 VDC in TX?
(at VCO section)

Are signals
at Pins 14 &
15 of U200?

Yes

Yes
Is U200 pin 2
>4.5 VDC in Tx &
<40 mVDC in Rx

Check D200, D201,
C2026, C2025,
C2024 & C2027

Yes

Replace U200

Is there a short
between Pin 47 and
Pins 14 & 15 of
U200?
Yes

Yes

Replace
U200

Are Waveforms
at Pins 14 & 15
triangular?
No

Check R201

Is RF level at
U200 Pin 32
-12 < x <-25
dBm?

If C2052, R208, C2067
C2068. C210, are OK, then
see VCO
troubleshooting chart

Check programming
lines between U403
and U200 Pins 7,8 & 9

Remove
Shorts

Check µP U403
Troubleshooting
Chart

Do Pins
7,8 & 9 of
U200 toggle
when channel is
changed?

Yes

Is information
from µP U403
correct?
Yes

Replace U200

3-8

TROUBLESHOOTING CHARTS

4.0

Troubleshooting Flow Chart for VCO

RX VCO

Low or no RF Signal
at input to PA

Low or no RF Signal
at TP1

Visual check
of board
OK?

Correct
Problem

Make sure U508 is working
correctly and runner
between U508 Pin 1 and
U201 Pin 14 & 18 is OK

Make sure Synthesizer is
working correctly and runner
between U200 Pin 28 and
U201 Pin 3 is OK

Check runner
between U200 Pin 2
and U201 Pin 19

YES

Are Q200
Base at 2.4V
Collector at 4.5V
Emitter at 1.7V

4.8V DC at
U201 Pin 19
OK?
YES

If all parts associated
with the pins are OK
replace U201

Are U201 Pins
13 at 4.4V
15 at 1.1V
10 at 4.5V
16 at 1.9V

If all parts
associated
with the pins
are OK,
replace U201

YES

If L216, C2071, C2070,

Check 9V at R230

Is RF available
at C2060

YES

C2060 are okay
replace U201

YES

Is RF available
at base of Q200

Check Transmiter
Pre Driver

YES

Check parts between
TP1 and Q200

4.5V DC at
U201 Pin 3 OK?
YES

YES
35mV DC at
U201 Pin 19
OK?

3.3V DC at U201
Pin 14 & 18 OK?

YES

YES
4.5V DC at
U201 Pin 3 OK?

Visual check
of board
OK?
YES

YES
3.3 DC at U201
Pin 14 & 18 OK?

TX VCO

If all parts from U200 Pin 8
to Base of Q200 are OK,
replace U200

Power OK but
no modulation

Audio =180mVrms
at “+” side of
D205

Replace R212

YES

2.5VDC
at D205

YES

If R211 is Ok,
replace D205

NO
Replace R211

Troubleshooting Flow Chart for DC Supply (1 of 2)

5.0

3-9

Go to 3V

Replace U503

Yes

V=5V
?

9v
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.6
Linearized : Yes
Create Date : 2015:07:26 09:33:12-04:00
Creator : PScript5.dll Version 5.2
Modify Date : 2015:07:26 09:33:12-04:00
Title :
XMP Toolkit : Adobe XMP Core 5.4-c005 78.147326, 2012/08/23-13:03:03
Metadata Date : 2015:07:26 09:33:12-04:00
Creator Tool : PScript5.dll Version 5.2
Format : application/pdf
Document ID : uuid:b3856c71-6b0f-47e0-a836-43cefafdca8e
Instance ID : uuid:5e2f39bc-d4e9-45b0-91f9-9362f1ebaefc
Producer : Acrobat Distiller 4.0 for Windows
Page Count : 390

EXIF Metadata provided by EXIF.tools

CM Series/CM Radios Detailed Service Manual 6866545D30 O

Navigation menu

Versions of this User Manual:

Views

Navigation