NAVD0_LA6091P_R10_0303 COMPAL LA 6091P REV 1.0

User Manual:

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PJP1
ZZZ1

PCB

D0DAZ@

ZZZ3

ZZZ4

LA-6091P

D0DA@

LS-6094P

D0DA@

ZZZ5

45@ DCIN
DC301008S00

LS-6095P
D0DA@

1

1

ZZZ2

PCB

E0DAZ@

ZZZ6

ZZZ8

LA-6091P

E0DA@

LS-6096P

E0DA@

ZZZ7

LS-6097P
E0DA@

ZZZ9

ZZZ10

LS-6098P
E0DA@

LS-6099P
E0DA@

Compal Confidential
2

2

NAVD0 Schematics Document
Intel Pineview Processor with Tigerpoint + DDRII + NV OPTIMUS

2010-02-09
3

3

l.c
om

REV: 1.0

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D

Cover Page

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
B
Date:

xa

2010/10/09

Deciphered Date

Document Number

Rev
1.0

NAVD0 LA-6091P

he

2009/10/09

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

4

Wednesday, March 03, 2010

E

Sheet

1

of

46

4

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Clock Generator
CK505
page 13

Compal Confidential
Model Name : NAVD0
File Name : LA-6091P

CRT Conn.
page 15

1

1

RGB
LVDS

LCD Conn.

DDRII-SO-DIMM
page 7

1.8V DDRII 667

22x22mm

page 14

Thermal Sensor

Memory BUS(DDRII)

Pineview
FCBGA 559
page 4,5,6

EMC1402
page 5

DMI
X2 mode
GEN1

2

USB
HDA

Tigerpoint

PCI-Express

USB Port X2

PCBGA360

BlueTooth

17x17mm

page 24

SATA

page 17,18,19,20

VGA
N11M-OP2

MINI Card x1
3G

page 8,9,10,11,12

page 24

WLAN

CMOS CAM
page 14

10/100 Ethernet

HDD Conn.

AR8132L
page 25

2

page 23

3G

page 21

page 23

page 24

LPC BUS
HDMI Conn
3

Transfermer

page 16

3

Audio Codec
ALC272
Power ON/OFF

DC/DC Interface

Card Reader
ENE UB6250

page 28

RJ45

page 34

page 27

page 22

ENE KBC
KB926page

3VALW/5VALW
page 39

DC IN

page 36

SPI
29

0.89VP/0.9VSP

page 41

AMP & INT
Speaker
page 29

BATT IN

page 37

1.8V/VCCP

Int.KBD

page 40

CHARGER

SPI ROM

page 32

page 38

To Audio Board
INT MIC
page 28

To Audio Board
HeadPhone &
MIC Jack
page 29

page 31

Touch Pad

SD/MMC/MS
CONN page 27

page32

4

VGA
DC/DC Interface
page 35

page 42

VGA_CORE/
1.5VSP

2009/10/09

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

page 43

A

4

CPU_CORE

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

D

Title

Block Diagrams
Size
B
Date:

Document Number

Rev
1.0

NAVD0 LA-6091P
Wednesday, March 03, 2010

Sheet
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1

1

Voltage Rails

2

External PCI Devices

Power Plane

Description

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+0.9VS

0.9V switched power rail for DDR terminator

ON

OFF

OFF

+VCCP

VCCP switched power rail

ON

OFF

OFF

+1.5VS

1.5V switched power rail

ON

OFF

OFF

DEVICE

+1.8V

1.8V power rail for DDR

ON

ON

OFF

+0.89VS

Graphic core power rail

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

SIGNAL

SLP_S3# SLP_S4# SLP_S5#

PIRQ

2

EC SM Bus1 address

+VALW

+V

+VS

Clock

Full ON

HIGH

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

HIGH

HIGH

HIGH

ON

ON

ON

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S3 (Suspend to RAM)

REQ/GNT #

No PCI Device

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

STATE

IDSEL #

S4 (Suspend to Disk)

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

ON

OFF

OFF

OFF

EC SM Bus2 address

Device

Address

Device

Address

Smart Battery

0001 011X b

EMC1402

100_1100

ICH7M SM Bus address

3

BOARD ID Table(Page 31)
VCC
Ra

3.3V
100K

ID BRD ID

NAVE0

R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)

Vab-Min

Vab-Typ

Vab-Max

0
8.2K
18K
33K
56K
100K
200K
NC

0V
0.216V
0.436V
0.712V
1.036V
1.453V
1.935V
2.500V

0V
0.250V
0.503V
0.819V
1.185V
1.650V
2.200V
3.3V

0V
0.289V
0.538V
0.875V
1.264V
1.759V
2.341V
3.3V

Address
1101 001Xb

DDR DIMMA

1010 000Xb

l.c
om

NAVD0

0
1
2
3
4
5
6
7

Rb

Device
Clock Generator
(SLG8SP556VTR)

3

A

B

C

D

Notes List

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
B
Date:

xa

2010/10/09

Deciphered Date

Document Number

Rev
1.0

NAVD0 LA-6091P

he

2009/10/09

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

4

Wednesday, March 03, 2010

E

Sheet

3

of

46

4

5

4

3

2

1

<7> DDR_A_DQS#[0..7]
PINEVIEW_M
PINEVIEW_M

<7> DDR_A_D[0..63]

U71A

U71B

REV = 1.1

<7> DDR_A_DM[0..7]
REV = 1.1

F3
F2
H4
G3

DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1

N7
N6

EXP_CLKINN
EXP_CLKINP

DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

<7> DDR_A_DQS[0..7]

G2
G1
H3
J2

DMI_TX0 <19>
DMI_TX#0 <19>
DMI_TX1 <19>
DMI_TX#1 <19>

<7> DDR_A_MA[0..14]

DMI

DMI_RX0_R
DMI_RX#0_R
DMI_RX1_R
DMI_RX#1_R

D

<13> CLK_CPU_EXP#
<13> CLK_CPU_EXP

R10
R9
N10
N9

K2
J1
M4
L3

EXP_RCOMPO
EXP_ICOMPI
EXP_RBIAS

L10
L9
L8

RSVD_TP
RSVD_TP

N11
P11

EXP_TCLKINN
EXP_TCLKINP
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

R162
R203 49.9_0402_1%
750_0402_1%
T38
T39

C435
C436
<19>

DMI_RX#0
C437

C

<19>

DMI_RX1

<19>

DMI_RX#1

C438

DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#

AK22
AJ22
AK21

DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

AJ20
AH20
AK11

DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2

DDR_CS#0
DDR_CS#1

AH22
AK25
AJ21
AJ25

DDR_A_CS#_0
DDR_A_CS#_1
DDR_A_CS#_2
DDR_A_CS#_3

DDR_CKE0
DDR_CKE1

AH10
AH9
AK10
AJ8

DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3

M_ODT0
M_ODT1

AK24
AH26
AH24
AK27

DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3

Must be placed within 500 mils from Pineview-M pins
<7> DDR_A_WE#
<7> DDR_A_CAS#
<7> DDR_A_RAS#

K3
L2
M2
N2

<7> DDR_A_BS0
<7> DDR_A_BS1
<7> DDR_A_BS2

<7> DDR_CS#0
<7> DDR_CS#1

091105 change CPU Part Number to SA00003M870

DMI_RX0

DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14

DDR_A_DQS_0
DDR_A_DQS#_0
DDR_A_DM_0

AD3
AD2
AD4

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DM0

DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7

AC4
AC1
AF4
AG2
AB2
AB3
AE2
AE3

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7

AB8
AD7
AA9

DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DM1

AB6
AB7
AE5
AG5
AA5
AB5
AB9
AD6

DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

AD8
AD10
AE8

DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DM2

AG8
AG7
AF10
AG11
AF7
AF8
AD11
AE10

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

AK5
AK3
AJ3

DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DM3

AH1
AJ2
AK6
AJ7
AF3
AH2
AL5
AJ6

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

AG22
AG21
AD19

DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DM4

AE19
AG19
AF22
AD22
AG17
AF19
AE21
AD21

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39

DDR_A_DQS_5
DDR_A_DQS#_5
DDR_A_DM_5

AE26
AG27
AJ27

DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DM5

DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47

AE24
AG25
AD25
AD24
AC22
AG24
AD27
AE27

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

AE30
AF29
AF30

DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DM6

AG31
AG30
AD30
AD29
AJ30
AJ29
AE29
AD28

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55

AB27
AA27
AB26

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DM7

AA24
AB25
W24
W22
AB24
AB23
AA23
W27

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_DQS_1
DDR_A_DQS#_1
DDR_A_DM_1
DDR_A_DQ_8
DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15

1 OF 6

PINEVIEW-M_FCBGA8559

<19>

AH19
AJ18
AK18
AK16
AJ14
AH14
AK14
AJ12
AH13
AK12
AK20
AH12
AJ11
AJ24
AJ10

<7> DDR_CKE0
<7> DDR_CKE1

1

DMI_RX0_R
2
0.1U_0402_10V7K

1

DMI_RX#0_R
2
0.1U_0402_10V7K

1

DMI_RX1_R
2
0.1U_0402_10V7K

1

DMI_RX#1_R
2
0.1U_0402_10V7K

<7>
<7>

M_ODT0
M_ODT1

<7> M_CLK_DDR0
<7> M_CLK_DDR#0
<7> M_CLK_DDR1
<7> M_CLK_DDR#1

Close to CPU

M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1

AG15
AF15
AD13
AC13

DDR_A_CK_0
DDR_A_CK_0#
DDR_A_CK_1
DDR_A_CK_1#

AC15
AD15
AF13
AG13

DDR_A_CK_3
DDR_A_CK_3#
DDR_A_CK_4
DDR_A_CK_4#

AD17
AC17
AB15
AB17

RSVD
RSVD
RSVD
RSVD

AB4
AK8

RSVD
RSVD

+1.8V

DDR_A_DQS_2
DDR_A_DQS#_2
DDR_A_DM_2
DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23
DDR_A_DQS_3
DDR_A_DQS#_3
DDR_A_DM_3
DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
DDR_A_DQS_4
DDR_A_DQS#_4
DDR_A_DM_4
DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39

R369
10K_0402_5%
+1.8V

+1.8V

R370
10K_0402_5%
@ T40
AB11
AB13
T41

1

FAN1 Conn
R50

+3VS

1K_0402_1%
1

2

B

1

R256
10K_0402_5%

<31> FAN_SPEED1
<31> FAN_PWM

1

R142

JP12

+VCC_FAN1
FAN_PWM

C311
100P_0402_50V8J

1
2
3
4
5
6

R243
R242 80.6_0402_1%
80.6_0402_1%

AL28
AK28
AJ26
AK29

1K_0402_1%

1
2
3
4
G5
G6

DDR_VREF
DDR_RPD
DDR_RPU
RSVD

DDR_A_DQS_6
DDR_A_DQS#_6
DDR_A_DM_6

2

2

40mil

2

RSVD_TP
RSVD_TP

DDR_A

DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55

ACES_85205-04001
CONN@
091022 change JP12 to ACES_87213_0400G
2010 0105 change JP12 to ACES_85205-04001

DDR_A_DQS_7
DDR_A_DQS#_7
DDR_A_DM_7

0120 Change JP12 BOM structure from ME@ to CONN@
1 R817
2
0_0603_5%

+5VS

+VCC_FAN1

DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63

A

D

C

B

A

2 OF 6
PINEVIEW-M_FCBGA8559

091105 change CPU Part Number to SA00003M870

2009/10/09

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Pineview(1/3)
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

Wednesday, March 03, 2010

Sheet
1

4

of

46

5

4

3

2

1

Add 470PF on
H_SMI# for known issue 07/08
1
C1171

PINEVIEW_M

U71D

091202 move R247/R249 from CRT side to CPU side

2
470P_0402_50V7K

PINEVIEW_M
U71C

1

2
T8
1K_0402_5% T15
T9
T16
T17

L11

L31
L30

DAC_IREF

P28

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

GMCH_CRT_R <15>
GMCH_CRT_G <15>
GMCH_CRT_B <15>

R151
2.37K_0402_1%
GMCH_CRT_DATA <15>
GMCH_CRT_CLK <15>
R201
665_0402_1%
CPU_DREFCLK
CPU_DREFCLK#
CPU_SSCDREFCLK
CPU_SSCDREFCLK#

Y30
Y29
AA30
AA31

REFCLKINP
REFCLKINN
REFSSCLKINP
REFSSCLKINN

H_PW ROK

C

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

T22
T23
T24
T25

AA21
W21
T21
V21

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

R305 1

@

R306 1

2

0_0402_5%

2

0_0402_5%

VGATE

LIBG
LVBG
LVREFH
LVREFL
LBKLT_EN
LBKLT_CTL
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN

E7
H7
H6
F10
F11
E5
F8

DPRSTP#
DPSLP#
INIT#
PRDY#
PREQ#

G6
G10
G8
E11
F15

THERMTRIP#

E13

H_THERMTRIP#

PROCHOT#
CPUPWRGOOD

C18
W1

H_PROCHOT#
H_PW RGD

H_A20M#

C5

1

2

470P_0402_50V8J

H_INTR

C6

1

2

470P_0402_50V8J

H_NMI

C7

1

2

470P_0402_50V8J

H_IGNNE#

C9

1

2

470P_0402_50V8J

H_STPCLK# C11

1

2

470P_0402_50V8J

H_DPSLP#

C12

1

2

470P_0402_50V8J

H_INIT#

C13

1

2

470P_0402_50V8J

H_PW RGD

C14

1

2

470P_0402_50V8J

H_DPRSTP# C66

1

2

470P_0402_50V8J

G11
E15
G13
F13

BPM_1_0#
BPM_1_1#
BPM_1_2#
BPM_1_3#

T48
T49
T50
T51

B18
B20
C20
B21

BPM_2_0#/RSVD
BPM_2_1#/RSVD
BPM_2_2#/RSVD
BPM_2_3#/RSVD

XDP_TDI
XDP_TDO
XDP_TCK
XDP_TMS
XDP_TRST#

G5
D14
D13
B14
C14
C16

RSVD
TDI
TDO
TCK
TMS
TRST#

D30
E30

THRMDA_1
THRMDC_1

C30
D31

THRMDA_2/RSVD
THRMDC_2/RSVD

T74
T75
T76

T53
T52
T54
T57
T58

091216 change value
to 470P

H_THERMDA
H_THERMDC

D

H_DPRSTP# <19>
H_DPSLP# <19>
H_INIT# <18>
T78
T79

H_THERMTRIP# <18>

H_PW RGD <19>
T63

PCH_POK <19,31>

CLK_CPU_HPLCLK# <13>
CLK_CPU_HPLCLK <13>

H_SMI# <18>
H_A20M# <18>
H_FERR# <18>
H_INTR <18>
H_NMI
<18>
H_IGNNE# <18>
H_STPCLK# <18>

H_DPRSTP#
H_DPSLP#
H_INIT#
XDP_PRDY#
XDP_PREQ#

<13,19,31,42>

091214 Remove T77
T55 test point
for layout limitation

PLTRST# <8,19,24,25,26,31>

H_SMI#
H_A20M#
H_FERR#
H_INTR
H_NMI
H_IGNNE#
H_STPCLK#

SMI#
A20M#
FERR#
LINT0
LINT1
IGNNE#
STPCLK#

PM_DPRSLPVR <19>

Modify 08/04

MISC

AA7
AA6
R5
R6

<14> GMCH_LVDS_SCL
<14> GMCH_LVDS_SDA
<14> GMCH_ENVDD

PM_EXTTS#0 <7>

CLK_CPU_HPLCLK#
CLK_CPU_HPLCLK

W8
W9

HPL_CLKINN
HPL_CLKINP

0_0402_5%
R200

PM_EXTTS#1
PM_EXTTS#0
H_PW ROK
PLTRST#

K29
J30
L5
AA3

PM_EXTTS#_1/DPRSLPVR
PM_EXTTS#_0
PWROK
RSTIN#

LIBG R22
J28
N22
N23
GMCH_ENBKL
L27
@
L26
R213
0_0402_5% L23
K25
K23
K24
H26

<31> GMCH_ENBKL
<14,31> INVT_PW M

CPU_DREFCLK <13>
CPU_DREFCLK# <13>
CPU_SSCDREFCLK <13>
CPU_SSCDREFCLK# <13>

RSVD

T18
T19
T20
T21

GMCH_CRT_HSYNC
GMCH_CRT_VSYNC

LA_CLKN
LA_CLKP
LA_DATAN_0
LA_DATAP_0
LA_DATAN_1
LA_DATAP_1
LA_DATAN_2
LA_DATAP_2

ICH

N31
P30
P29
N30

CRT_DDC_DATA
CRT_DDC_CLK

091211 del T10/T11/T28
T37

CRT_RED
CRT_GREEN
CRT_BLUE
CRT_IRTN

U25
U26
R23
R24
N26
N27
R26
R27

<14> GMCH_LVDS_ACLK#
<14> GMCH_LVDS_ACLK
<15>
<14> GMCH_LVDS_A0#
<15>
<14> GMCH_LVDS_A0
<14> GMCH_LVDS_A1#
<14> GMCH_LVDS_A1
<14> GMCH_LVDS_A2#
<14> GMCH_LVDS_A2

GTLREF
VSS

A13
H27

RSVD
RSVD

L6
E17

BCLKN
BCLKP

H10
J10

H_GTLREF

CLK_CPU_BCLK#
CLK_CPU_BCLK

K5
H5
K6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6

H30
H29
H28
G30
G29
F29
E29

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

RSVD
RSVD
RSVD
RSVD

L7
D20
H13
D18

RSVD_TP
RSVD_TP
EXTBGREF

K9
D19
K7

BSEL_0
BSEL_1
BSEL_2

CPU

R1378

CRT_HSYNC
CRT_VSYNC

R249 OPT@ 15_0402_5%
M30 GMCH_CRT_HSYNC_R 1
2
M29 GMCH_CRT_VSYNC_R 1
2
R247 OPT@ 15_0402_5%

REV = 1.1

LVDS

D

REV = 1.1

XDP_RSVD_00
XDP_RSVD_01
XDP_RSVD_02
XDP_RSVD_03
XDP_RSVD_04
XDP_RSVD_05
XDP_RSVD_06
XDP_RSVD_07
XDP_RSVD_08
XDP_RSVD_09
XDP_RSVD_10
XDP_RSVD_11
XDP_RSVD_12
XDP_RSVD_13
XDP_RSVD_14
XDP_RSVD_15
XDP_RSVD_16
XDP_RSVD_17

VGA

D12
A7
D6
C5
C7
C6
D8
B7
A9
D9
C8
B8
C10
D10
B11
B10
B12
C11

T2
T12
T3
T4
T13
T5
T6
T7
T14

CLK_CPU_BCLK# <13> C
CLK_CPU_BCLK <13>
CPU_BSEL0 <13>
CPU_BSEL1 <13>
CPU_BSEL2 <13>
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

<42>
<42>
<42>
<42>
<42>
<42>
<42>

T26
T27
H_EXTBGREF

091212 Add C5, C6, C7, C9, C11, C12, C13, C14
to prevent switch noise

XDP Reserve

B

+VCCP

B
4 OF 6

2

51 +-1% 0402

R342 1

2

51 +-1% 0402

Place closed to chipset

XDP_TDO

R343 1

2

51 +-1% 0402

GMCH_CRT_R

XDP_PREQ#

R344 1

2

51 +-1% 0402

GMCH_CRT_G

XDP_TRST#

R345 1

2

51 +-1% 0402

GMCH_CRT_B

XDP_TCK

R346 1

2

51 +-1% 0402

GMCH_ENBKL

1

091105 change CPU Part Number to SA00003M870

R307

2
150_0402_1%
1 R308
2
150_0402_1%
1 R309
2
150_0402_1%
R34
100K_0402_5%

+VCCP
+VCCP
R244
976_0402_1%
R144
1K_0402_1%

+VCCP
+3VS

SMDATA

7

EC_SMB_DA2

DN

ALERT#

6

2

GND

5

2
3
4

THERM#

EC_SMB_DA2 <8,9,31>

R58 1
10K_0402_5%

2009/10/09

Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Address:100_1100
4

3

C940

1U_0402_6.3V6K

Compal Electronics, Inc.

Compal Secret Data

Security Classification

placed within 0.5"
of processor pin.

placed within 0.5"
of processor pin.

+3VS

Issued Date

EMC1402-1-ACZL-TR MSOP 8P SENSOR

5

Close to Processor
pin

2

2

R156
3.3K_0402_1%

l.c
om

DP

H_THERMDA
H_THERMDC
2200P_0402_50V7K

Close to Processor
pin

EC_SMB_CK2 <8,9,31>

1

@

ai

EC_SMB_CK2

R155
2K_0402_1%

tm

8

VDD

H_PROCHOT#

PM_EXTTS#0

SMCLK

1

@ C939

U2

1U_0603_10V6K

1

C80

2

1

ho

2

R202
68_0402_5%

R143
10K_0402_5%

1

C79

1

H_EXTBGREF
H_GTLREF

2

f@

A

CPU THERMAL SENSOR

2

0.1U_0402_16V4Z

+3VS

Title

Pineview(2/3)
Size
B
Date:

Document Number

in

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

R341 1

XDP_TMS

Rev
1.0

xa

091105 change CPU Part Number to SA00003M870

XDP_TDI

NAVD0 LA-6091P

he

3 OF 6
PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

W ednesday, March 03, 2010

Sheet
1

5

of

46

A

4

3

2

1

U71F

+CPU_CORE

U71E

GFX supply current: 1.38A
Sustained GFX supply current: 1.05A

PINEVIEW_M

+0.89VS

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX

CPU

T13
T14
T16
T18
T19
V13
V19
W14
W16
W18
W19

GFX/MCH

REV = 1.1

D

DDR supply current 2.27A
+1.8V
2.2U_0603_10V6K
2
2
C188

C187

1
+1.8V

1

C186

1

AK13
AK19
AK9
AL11
AL16
AL21
AL25

C85

1

1

2.2U_0603_10V6K

2.2U_0603_10V6K

AK7
AL7

+VCCP

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

VCCCK_DDR
VCCCK_DDR

1U_0402_6.3V6K

22U_0805_6.3V6M

1
C428

1
C429

1
C430

1
C431

1

2

2

2

2

2

C1154

1

C1152

2

1

PLACE IN CAVITY

+VCCP

C1160
0.1U_0402_10V6K

1
C243

1U_0402_6.3V6K

2

4.7U_0603_6.3V6K

2

1
C236
2

AA10
AA11

2

2

C1161
0.1U_0402_10V6K
Close U71.D4
+RING_EAST

R20

0_0402_5%

1

C242
1U_0402_6.3V6K

2

+RING_WEST
0_0402_5%

2
R28

VCCSENSE
VSSSENSE
VCCA

VCCACK_DDR
VCCACK_DDR

VCCP
VCCP
AA19

1

C64
1U_0402_6.3V6K

VCCP

Display PLL SFR and CRT DAC supply
current: 0.154A

1

1

1

2

2

1

1

2

2

C241
1U_0402_6.3V6K

POWER

1
C55

+
C275
C278
330U 2.5V Y
330U 2.5V Y
2
2

1U_0402_6.3V6K 22U_0805_6.3V6M

1U_0402_6.3V6K

R21
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR

1

+

2

DDR

U10
U5
U6
U7
U8
U9
V2
V3
V4
W10
W11

2

1

C1153
22U_0805_6.3V6M

DDR analog supply current: 1.32A

22U_0805_6.3V6M

C267
22U_0805_6.3V6M

C

2.2U_0603_10V6K
2
2

+CPU_CORE

1U_0402_6.3V6K

A23
A25
A27
B23
B24
B25
B26
B27
C24
C26
D23
D24
D26
D28
E22
E24
E27
F21
F22
F25
G19
G21
G24
H17
H19
H22
H24
J17
J19
J21
J22
K15
K17
K21
L14
L16
L19
L21
N14
N16
N19
N21

A11
A16
A19
A29
A3
A30
A4
AA13
AA14
AA16
AA18
AA2
AA22
AA25
AA26
AA29
AA8
AB19
AB21
AB28
AB29
AB30
AC10
AC11
AC19
AC2
AC21
AC28
AC30
AD26
AD5
AE1
AE11
AE13
AE15
AE17
AE22
AE31
AF11
AF17
AF21
AF24
AF28
AG10
AG3
AH18
AH23
AH28
AH4
AH6
AH8
AJ1
AJ16
AJ31
AK1
AK2
AK23
AK30
AK31
AL13
AL19
AL2
AL23
AL29
AL3
AL30
AL9
B13
B16
B19
B22
B30
B31
B5
B9
C1
C12
C21
C22
C25
C31
D22
E1
E10
E19
E21
E25
E8
F17
F19

C29
B29
Y2

VCCSENSE
VSSSENSE

C68
1U_0402_6.3V6K

VCCSENSE <42>
VSSSENSE <42>
+1.5VS

+VCCPProcessor

+VCC_DMI

1
0_0603_5%

C237
1U_0402_6.3V6K

1
Core
analog supply current: 0.08A
C391
2 0.01U_0402_16V7K

D4
B4
B3

VCCD_AB_DPL

B

2

+VCCSFR_AB_DPL AC31
1

2

+VCC_CRT_DAC T30

VCCACRTDAC

+3VS

GIO supply current: 0.006A T31
+RING_EAST
+RING_WEST

J31
C3
B2
C2
A21

+VCCP

+1.8VS

VCCSFR_AB_DPL

VCC_GIO
VCCRING_EAST
VCCRING_WEST
VCCRING_WEST
VCCRING_WEST
VCC_LGI

VCCALVDS
VCCDLVDS

V30
W31

VCCA_DMI
VCCA_DMI
VCCA_DMI

T1
T2
T3

R25
+VCC_CRT_DAC
1
2
MBK1608601YZF_2P 1
C239
1U_0402_6.3V6K

LVDS supply current: 0.06A

2

RSVD
VCCSFR_DMIHMPLL
VCCP

DAC, GIO, LVDS, & LGIO, DPLL, HMPLL
supply current: 0.33A
5 OF 6
PINEVIEW-M_FCBGA8559

+0.89VS

+VCC_ALVD
+VCC_DLVD

LVDS

1

VCCD_HMPLL

DMI

R321 0_0402_5%

C189
1U_0402_6.3V6K

C192
1U_0402_6.3V6K

V11

EXP\CRT\PLL

+1.8VS

P2
AA1

+VCC_DMI

R18

DMI analog supply current: 0.48A

+DMI_HMPLL

+DMI_HMPLL
0_0402_5% 1

T56
2

SFR & DMIHMPLL supply current: 0.104A

E2

R26

+VCCP
1

2

1

C1162

2

1
0.1UH +-10% MLF1608DR10KT
C56

0.1U_0402_10V6K

C77

C78

2

1

2

1U_0402_6.3V6K

2

1

1U_0402_6.3V6K

2

1

1U_0402_6.3V6K

2

1

1U_0402_6.3V6K
C75

2

1

1U_0402_6.3V6K
C76

1

1U_0402_6.3V6K
C70

2

1U_0402_6.3V6K
C71

C81

2.2U_0603_10V6K
C74

1

1

VSS

F24
F28
F4
G15
G17
G22
G27
G31
H11
H15
H2
H21
H25
H8
J11
J13
J15
J4
K11
K13
K19
K26
K27
K28
K30
K4
K8
L1
L13
L18
L22
L24
L25
L29
M28
M3
N1
N13
N18
N24
N25
N28
N4
N5
N8
P13
P14
P16
P18
P19
P21
P3
P4
R25
R7
R8
T11
U22
U23
U24
U27
V14
V16
V18
V28
V29
W13
W2
W23
W25
W26
W28
W30
W4
W5
W6
W7
Y28
Y3
Y4

D

C

B

T29

091105 change CPU Part Number to SA00003M870

Follow Intel check list change to 22uF 06/06
+VCC_DLVD
1

+CPU_CORE
VCCSENSE

1

R32

A

C235
1U_0402_6.3V6K

2
2

100_0402_1%
VSSSENSE

1

Close Chipset pin

Modify to 2.2U 05/11

R31
2
100_0402_1%

2009/10/09

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2
2
22U_0805_6.3V6M

0_0402_5%
2

REV = 1.1

VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS

6 OF 6
PINEVIEW-M_FCBGA8559

+VCC_ALVD
1
C1155
1U_0402_6.3V6K

091105 change CPU Part Number to SA00003M870
R27

A

C69
1U_0402_6.3V6K

PINEVIEW_M

GND

5

4

3

2

Title

Pineview(3/3)
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

Wednesday, March 03, 2010

Sheet
1

6

of

46

4

3

2

+1.8V

<4> DDR_A_D[0..63]

1

1

<4> DDR_A_DM[0..7]

Layout Note:
Place near JDIM1

<4> DDR_A_DQS[0..7]

C112

2.2U 6.3V M X5R 0402
2

+DIMM_VREF

Share +DIMM_VREF for
1.DDRII VREF
2.GMCH SM_VREF_0
SM_VREF_1

R62
1K_0402_1%

1

2

1

C130
2.2U_0603_6.3V4Z

1

2

C109
2.2U_0603_6.3V4Z

2

C110
2.2U_0603_6.3V4Z

C129
2.2U_0603_6.3V4Z

C128
2.2U_0603_6.3V4Z

2

+1.8V

2

1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D8
DDR_A_D9

1

D

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3

1K_0402_1%
2

<4> DDR_A_MA[0..14]

1

C111

0.1U_0402_16V4Z
2

R61

DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11

2
DDR_A_D16
DDR_A_D17

1

DDR_A_DQS#2
DDR_A_DQS2

2

1

2

1

2

C107
0.1U_0402_16V4Z

1

C108
0.1U_0402_16V4Z

2

C105
0.1U_0402_16V4Z

+

C106
0.1U_0402_16V4Z

@

C94
220U_B2_2.5VM_R35

DDR_A_D18
DDR_A_D19
1

DDR_A_D24
DDR_A_D25

1

DDR_A_DM3
2
DDR_A_D26
DDR_A_D27
<4>

C

DDR_CKE0

<4> DDR_A_BS2

DDR_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
<4> DDR_A_BS0
<4> DDR_A_WE#
<4> DDR_A_CAS#
<4> DDR_CS#1
<4>

M_ODT1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS#1
M_ODT1
DDR_A_D32
DDR_A_D33

+0.9VS

1

2

1

2

1

2

2

C446
0.1U_0402_16V4Z

2

C445
0.1U_0402_16V4Z

1

C444
0.1U_0402_16V4Z

2

C443
0.1U_0402_16V4Z

1

C442
0.1U_0402_16V4Z

2

C441
0.1U_0402_16V4Z

2

1

C440
0.1U_0402_16V4Z

2

1

C439
0.1U_0402_16V4Z

2

1

C89
0.1U_0402_16V4Z

2

1

C118
0.1U_0402_16V4Z

2

1

C120
0.1U_0402_16V4Z

2

1

C90
0.1U_0402_16V4Z

2

1

C91
0.1U_0402_16V4Z

2

1

C115
0.1U_0402_16V4Z

2

1

C122
0.1U_0402_16V4Z

2

1

C88
0.1U_0402_16V4Z

2

1

C87
0.1U_0402_16V4Z

2

1

C121
0.1U_0402_16V4Z

2

1

C86
0.1U_0402_16V4Z

1

C117
0.1U_0402_16V4Z

DDR_A_D34
DDR_A_D35

1

DDR_A_D40
DDR_A_D41
2

DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6
+0.9VS
8
7
6
5

1
2
3
4

DDR_A_BS1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA4

DDR_A_BS0
DDR_A_MA10
DDR_A_MA3
DDR_A_MA5

47_0804_8P4R_5%
RP4
DDR_A_MA6
8
1
DDR_A_MA7
7
2
DDR_A_MA11
6
3
DDR_A_MA14
5
4

47_0804_8P4R_5%
RP3
M_ODT1
1
8
DDR_CS#1
2
7
DDR_A_CAS# 3
6
DDR_A_WE# 4
5

47_0804_8P4R_5%
RP1
8
1 DDR_A_MA12
7
2 DDR_A_MA9
6
3 DDR_A_MA8
5
4 DDR_A_MA1

Layout Note:
Place these resistor
closely DIMMA,all
trace length<750 mil

DDR_A_DM7
DDR_A_D58
DDR_A_D59
<13,24> CLK_SMBDATA
<13,24> CLK_SMBCLK
+3VS

091204 swap nets for layout

C116

1

2

47_0804_8P4R_5%

C141

1

2

CLK_SMBDATA
CLK_SMBCLK

Follow Intel Layout checklist, add C141 05/12

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

091029 change JDIM1 to FOX_ASOA426-M2RN-7F
follow SJV03_MB_Conn_List_1029_Rev10(BTB)

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
D

DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR0 <4>
M_CLK_DDR#0 <4>

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21
R64
DDR_A_DM2

1

2
0_0402_5%

PM_EXTTS#0 <5>

DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1

DDR_CKE1 <4>
C

DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS#0

DDR_A_BS1 <4>
DDR_A_RAS# <4>
DDR_CS#0 <4>

M_ODT0
DDR_A_MA13

M_ODT0 <4>

DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
B

DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1 <4>
M_CLK_DDR#1 <4>

DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R66
R65

1
1

2 10K_0402_5%
2 10K_0402_5%

FOX_ASOA426-M2RN-7F
CONN@

DIMMA

5

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/10/09

Issued Date

ho

Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1.3"

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

f@

DDR_CKE0

1 R163
2
47_0402_5%
1 R60
2
47_0402_5%
1 R59
2
47_0402_5%

Title

DDRII-SODIMMA
Size
B
Date:

in

DDR_A_BS2

Document Number

Rev
1.0

xa

DDR_CKE1

tm

ai

47_0804_8P4R_5%

DDR_A_D56
DDR_A_D57

0.1U_0402_16V4Z

8
7
6
5

47_0804_8P4R_5%
RP2
1
8
2
7
3
6
4
5

A

DDR_A_D50
DDR_A_D51

RP5

1
2
3
4

0.1U_0402_16V4Z

RP6
DDR_A_MA13
M_ODT0
DDR_CS#0
DDR_A_RAS#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

NAVD0 LA-6091P

he

B

C119
0.1U_0402_16V4Z

DDR_A_DQS#4
DDR_A_DQS4

1

+1.8V
JDIM1

20mils
+DIMM_VREF

<4> DDR_A_DQS#[0..7]

1

+1.8V

09/03

l.c
om

5

Wednesday, March 03, 2010

1

Sheet

7

of

46

A

4

3

2

1

U30A

AB10
AC10
AF10
AE10

1
2
R694 200_0402_5% @
1
2
AG10
R695 2.49K_0402_1% VGA@
PLTRST_VGA#
AD9
AE9

B

I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CH_SCL
I2CH_SDA
I2CS_SCL
I2CS_SDA

2
10K_0402_5%
@
2
10K_0402_5%
@

1
R687

T68
PAD
VGA_DEEP_IDLE_R

1
R825 @

0_0402_5%

AD2
AD1

VGA_HSYNC <15>
VGA_VSYNC <15>

AE2
AD3
AE3

VGA_CRT_R
VGA_CRT_B
VGA_CRT_G

AF1
AE1

DACA_VREF
DACA_RSET

VGA_CRT_R <15>
VGA_CRT_B <15>
VGA_CRT_G <15>
DIS@ 2
C746
R682

U6
U4

CRT OUT

1
0.1U_0402_16V4Z

DIS@

R6
V6

AD25

R1
T3

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

PAD
PAD
PAD
PAD

R689 1 VGA@ 2
R688 1
2
VGA@
VGA_LVDS_SCL_C
VGA_LVDS_SDA_C

A2
B1

T73
T72
T71
T70

1
2
R693 VGA@
10K_0402_5%
TESTMODE
1
2
R674 VGA@
10K_0402_5%
1
2
+3VS
10K_0402_5% @ R675
VGA_DDCCLK_C
VGA_DDCDATA_C
I2CB_SCL
I2CB_SDA

R2
R3

A3
A4

HDCP_SMB_CK1
HDCP_SMB_DAI

T1
T2

SMB_EC_CK2_R
SMB_EC_DA2_R

2.2K_0402_5%
2.2K_0402_5%

XTAL_OUTBUFF
XTAL_OUT
XTAL_IN

Ball Name

GB1-N11x
Normal
Function

GPIO0
GPIO1

General Purpose
HPD-C

GPIO2

LCD0_BL_PWM

GPIO3

LCD0_VDD

GPIO4

LCD0_BL_EN

GPIO5
GPIO6
GPIO7

GPU_VID0
GPU_VID1
GPU_VID2

GPIO8

OVERT

GPU_VID0
GPU_VID1
GPU_VID2
Thermal Catastrophic
Overtemp

GPIO9

ALERT

Thermal Alert

R814 1

E9
E10

XTALOUT

D10

XTALIN

1

2

P0

PWR_CTRL1

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19

HPD-E
FAN_PWM
Reserved
Reserved
HPD-D

1

2 @ 100P_0402_50V8J

1

2 @ 100P_0402_50V8J

D

Function Description
Memory VREF switch
SLI raster sync
AC power detect input
MEM_VID or Power supply
Control
Power supply control
Hot plug detect for IFP link E
Programmable Fan control
Hot plug detect for IFP link D

091212 Add C26, C29 near PR241
, PR242 to prevent switch noise
C

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

+3VSDGPU

R691
R692
R690

1 DIS@
1 DIS@
1 DIS@

2
2
2

150_0402_1%
150_0402_1%
150_0402_1%

+3VSDGPU

R683
2.2K_0402_5%
VGA@

R681
2.2K_0402_5%
VGA@

+3VSDGPU

EC_SMB_CK2
2 0_0402_5%
EC_SMB_DA2
1
2
R815
0_0402_5%
DIS@

R677
10K_0402_5%
VGA@

VGA_DDCCLK_C

R678 2 VGA@ 1 2.2K_0402_5%

VGA_DDCDATA_C

R679 2 VGA@ 1 2.2K_0402_5%

VGA_LVDS_SCL_C

R699 2 VGA@ 1 2.2K_0402_5%

VGA_LVDS_SDA_C

R698 2 VGA@ 1 2.2K_0402_5%

VGA_DEEP_IDLE_R

R824 2 @

R676
10K_0402_5%
VGA@

1 10K_0402_5%

091026 add R824 10K PU to +3VSDGPU
B

DGPU_PWR_EN

091022 follow NV OPTIMUS D.G.
Q47A
1

SMB_EC_CK2_R

2

27MHZ_20P_7A27000010
VGA@

C739
27P_0402_50V8J
VGA@

DGPU_PWR_EN <13,31,35>

6

EC_SMB_CK2 <5,9,31>

2N7002DW-T/R7_SOT363-6
OPT@

OPT@

Q47B
4

SMB_EC_DA2_R

3

EC_SMB_DA2 <5,9,31>

5

L27

MBK1608121YZF_0603
2
2
MBK1608121YZF_0603
MBK1608121YZF_0603
VGA_LVDS_SCL_C L31 1
2
VGA_LVDS_SDA_C
1
2
L30
DIS@
MBK1608121YZF_0603
1
1
C737
C738
DIS@
DIS@
VGA_DDCCLK_C
VGA_DDCDATA_C

091124 change C740/C739 to 27PF

R1490
100K_0402_5%
VGA@

PLTRST_VGA#

DIS@

1
1

L28

VGA_DDCCLK <15>
VGA_DDCDATA <15>

DIS@
DIS@

100P_0402_50V8J

2

VGA_LVDS_SCL <14>
VGA_LVDS_SDA <14>
C748
DIS@

1

2

C747
DIS@

12P_0402_50V8J

1

091124 change crystal Y5 P/N to SJ127P0M800

12P_0402_50V8J

P
G

100112 change Q47 P/N from SB00000AR00 to SB00000DH00

PLTRST_VGA#

4

2

C35

P8

0.9V

GPIO14

C29

A

DGPU_HOLD_RST#

Deep P12

MEM_VREF
SLI_SYNC
PWR_LEVEL
MEM_VID

12P_0402_50V8J

2
0_0402_5%

0.8V
0.85V

GPIO10
GPIO11
GPIO12
GPIO13

C26

P0
P-State

0

Hot Plug detect for IFP link C
Panel Backlight Brightness
(PWM capable)
Panel power enable
Panel Backlight on/off
(PWM Capable)

P-State

1
1

GB1-N11x
Normal
Function

12P_0402_50V8J

1
R1526

VGA_CORE

Ball Name

GPU_VID1

DIS@
PLTRST#

1.0V

Function Description

GPU_VID0

2

NC7SZ08P5X_NL_SC70-5
OPT@

GPU_VID1

VGA_CORE

2N7002DW-T/R7_SOT363-6

Y
A

GPU_VID0

D11

C740
27P_0402_50V8J
VGA@

3

1

<31> DGPU_HOLD_RST#

P8

1

DIS@

1

<5,19,24,25,26,31> PLTRST#

0.85V

1

Y5

U87
2 B

Deep P12

1
1

0
0

PEG_CLKREQ#

+3VS

0.8V

0x0A7D

091216 change GPU P/N to SA00003UD00
<13> PEG_CLKREQ#

0

091217 change R678/R679 from 4.7K to 2.2K

I2CS is internal thermal sensor.
XTAL_SSIN

GPU_VID1

0
0

124_0402_1%

T5
R4
T4

AF3
AG4
AE4
AF4
AG3

Device ID

VGA_DEEP_IDLE <31>

GPIO6

GPU_VID0

0x0A74

N11M-GE1/LP1
(40nm)

091026 add GPIO18 usage
VGA_DEEP_IDLE output to EC

2

N11M-GE1-S-A2 _BGA533
VGA@

VGA@
2 10K_0402_5%
R696

1

+3VSDGPU

PEX_CLKREQ_N

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
TESTMODE

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

PEX_RST_N

DACB_RED
DACB_BLUE
DACB_GREEN
DACB_VREF
DACB_RSET

PEX_REFCLK
PEX_REFCLK_N

PEX_TERMP

DACB_HSYNC
DACB_VSYNC

VGA_GPIO14

1
R684

N10M-GS
(40nm)

GPIO5

2

CLK_PCIE_VGA
CLK_PCIE_VGA#

<13> CLK_PCIE_VGA
<13> CLK_PCIE_VGA#

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

DACA_VREF
DACA_RSET

VGA_GPIO11

Device ID

1

C

AD10
AD11
AD12
AC12
AB11
AB12
AD13
AD14
AD15
AC15
AB14
AB15
AC16
AD16
AD17
AD18
AC18
AB18
AB19
AB20
AD19
AD20
AD21
AC21
AB21
AB22
AC22
AD22
AD23
AD24
AE25
AE26

DACA_RED
DACA_BLUE
DACA_GREEN

HDMI_DETECT_VGA
HDMI_DETECT_VGA <16>
NV_INVTPWM
T33
VGA_ENVDD
VGA_ENVDD <14>
VGA_ENBKL
VGA_ENBKL <31>
GPU_VID0
1
2
GPU_VID0 <43>
GPU_VID1
R685 1 VGA@ 2 0_0402_5%
GPU_VID1 <43>
R686
VGA@
0_0402_5%
091105 add TestPad on GPIO8/GPIO9
T31
Follow
NV
review
T32

2

0.1U_0402_16V7K

DACA_HSYNC
DACA_VSYNC

N1
G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2

1

<19> PCIE_CRX_GTX_P0
<19> PCIE_CRX_GTX_N0

PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19

2

DIS@
0.1U_0402_16V7K
PCIE_CRX_GTX_P0 C736 1
2 VGA@
PCIE_CRX_GTX_N0 C735 1
2 VGA@

DACA

FBVDDQ
(+1.5VSDGPU)

DACB

IFPAB_IOVDD
(+1.8VSDGPU)

PCI EXPRESS

NVVDD
(VGA_CORE)

TEST

PEX_VDD can
ramp up any time

PEX_VDD
(+1.05VSDGPU)
D

I2C

VDD33
(+3VSDGPU)

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

CLK

DIS ONLY

AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
AF22
AE22
AE24
AF24
AG24
AF25
AG25
AG26
AF27
AE27

GPIO

Part 1 of 5
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

<19> PCIE_CTX_GRX_P0
<19> PCIE_CTX_GRX_N0

5

5

1

2

A

OPT@

091212 Add C35 near U87
to prevent switch noise

2009/10/09

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

N11M-OP2 PCIE,GPIO,CLK
Size
B
Date:

Document Number

Rev
1.0

NAVD0 LA-6091P
Wednesday, March 03, 2010

Sheet
1

8

of

46

5

4

3

2

1

FBAA[0..13]

<12> FBAA[0..13]

VGA_LVDS_ACLK
FBBA[2..5]

<12> FBBA[2..5]

VGA_LVDS_ACLK#
FBADQM[0..7]

<12> FBADQM[0..7]

FBADQS[0..7]

<12> FBADQS[0..7]

FBADQS#[0..7]

<12> FBADQS#[0..7]

C756
12P_0402_50V8J
@

FBA_D[0..63]

<12> FBA_D[0..63]

2

2

1

1

C757
12P_0402_50V8J
@

U30B
D

F26
J24
F25
M23
N27
M27
K26
J25
J27
G23
G26
J23
M25
K27
G25
L24
K23
K24
G22
K25
H22
M26
H24
F27
J26
G24
G27
M24
K22
J22
L22

FBAA4
FBARAS#
FBAA5
FBA_BA1
FBBA2
FBBA4
FBBA3

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

C26
B19
D19
D23
T24
AA23
AB27
T26

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

D25
A18
E18
B24
R22
Y24
AA27
R27

FBADQS#0
FBADQS#1
FBADQS#2
FBADQS#3
FBADQS#4
FBADQS#5
FBADQS#6
FBADQS#7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

C25
A19
E19
A24
T22
AA24
AA26
T27

FBADQS0
FBADQS1
FBADQS2
FBADQS3
FBADQS4
FBADQS5
FBADQS6
FBADQS7

FB_VREF

A16

FB_VREF1

FBA_CLK0
FBA_CLK0_N

F24
F23

FBACLK0 <12>
FBACLK0# <12>

1

N24
N23

FBACLK1 <12>
FBACLK1# <12>

2

IFPC_AUX
IFPC_AUX_N

FBA_BA2 <12>
FBBAODT0 <12>
1

FBAACS0# <12>
FBAAODT0 <12>

R609
10K_0402_5%
VGA@

HDMI

2

R607
10K_0402_5%
VGA@

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

VGA_HDMI_TX2+
VGA_HDMI_TX2VGA_HDMI_TX1+
VGA_HDMI_TX1VGA_HDMI_TX0+
VGA_HDMI_TX0VGA_HDMI_CLK+
VGA_HDMI_CLK-

G4
G5
P4
N4
M5
M4
L4
K4
H4
J4

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

+1.5VSDGPU
1

F7
G6
D6
C6
A6
A7
B6
B7
E6
E7

1.27V~0.9V

R615 2
M22
1
10K_0402_5%VGA@

2

R619
1.3K_0402_1%
@

BUFRST_N

C634
0.01U_0402_16V7K
@

THERMDN
THERMDP

CEC
SPDIF

ROM_CS_N

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

STRAP2

N5

PAD

T65

D8

PAD

T66

D9

PAD

T67

<11>

STRAP1

<11>

STRAP2

<11>

C

R634
10K_0402_5%
VGA@
+3VSDGPU

N2
SPDIF_IN
1 VGA@ 2
R620 36K_0402_5%

F9

R640
10K_0402_5%
VGA@

ROM_SCLK
ROM_SI
ROM_SO

IFPAB_RSET
IFPC_RSET

B10
C9

ROM_SCLK

A10

ROM_SI

C10

ROM_SO

AB6

M6

IFPE_RSET

F8

ROM_SI

<11>

ROM_SO <11>

1
2
R625
@
1K_0402_1%
1
2
R621 VGA@
1K_0402_1%
1
2
R622
@
1K_0402_1%
1
2
R649
@
1K_0402_1%

R5

IFPD_RSET

ROM_SCLK <11>

B

091216 change GPU P/N to SA00003UD00

+1.5VSDGPU

+3VSDGPU

2
+3VS

1

R821
100K_0402_5%
@

DGPU_PWRGD#

2

Q38B
4

ho

100112 change Q38 P/N from SB00000AR00 to SB00000DH00

2009/10/09

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification

tm

20100123 change R822 from OPT@ to VGA@

ai

5V PULL UP IN CONNECTER SIDE

Issued Date

4

VGA_HDMI_SDA <16>

Title

N11M-OP2 LVDS,Memory Bus

in

091022 add for OPTIMUS

3

2N7002DW-T/R7_SOT363-6

VGA_HDMI_SDA <16>

2N7002DW-T/R7_SOT363-6

VGA@

l.c
om

IFPC_AUX_N
2

3

DGPU_PWRGD

R654
4.7K_0402_5%
VGA@

5

1

Q74
SSM3K7002FU_SC70-3
@

Size
B
Date:

xa

5
EC_SMB_DA2

S

2
G

R822
22K_0402_5%
VGA@

@

Q73B
4

1
DGPU_PWRGD

<16,31> DGPU_PWRGD

D

3

VGA_HDMI_SCL <16>

DGPU_PWRGD#

A

VGA_HDMI_SCL <16>

+3VSDGPU

6

1

Q73A
1

2N7002DW-T/R7_SOT363-6
@

6

2N7002DW-T/R7_SOT363-6
VGA@

2
EC_SMB_CK2

Q38A
1

IFPC_AUX

1

DGPU_PWRGD#

DGPU_PWRGD

R652
4.7K_0402_5%
VGA@

2

change Q73,Q74,R821 from mount to @

5

A9

STRAP0

N11M-GE1-S-A2 _BGA533
VGA@

R618
1.3K_0402_1%
@

100112 change Q73 P/N from SB00000AR00 to SB00000DH00

<5,8,31> EC_SMB_DA2

STRAP1

+3VSDGPU

N11M-GE1-S-A2 _BGA533
VGA@

<5,8,31> EC_SMB_CK2

STRAP0

B9

2

IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

C7

1

10mil

STRAP2

SERIAL

D3
D4
F5
F4
E4
D5
C3
C4
B3
B4

STRAP1

1

2

2

R614
10K_0402_5%
VGA@

STRAP0

T6
W6
Y6
AA6
N3

1

1
FBAA_CKE <12>
1

FBAA0
FBAA9
FBAA6
FBAA2
FBAA8
FBAA3
FBAA1
FBAA13
FBA_BA2
FBBAODT0
FBAACS0#
FBAAODT0

R608
10K_0402_5%
VGA@

RFU_1
RFU_2
RFU_3
RFU_4
RFU_5

C15
D15
J5

2

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

FBA_RST <12>
FBAA_CKE

NC

AB3
AB2
W1
V1
W3
W2
AA2
AA3
AB1
AA1

<12>

NC
NC
NC

RFU

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

STRAP

LVDS

2

FBACAS# <12>
FBAWE# <12>
FBA_BA0 <12>

R613
10K_0402_5%
VGA@

VGA_LVDS_ACLK AC4
VGA_LVDS_ACLK# AD4
VGA_LVDS_A0
V5
VGA_LVDS_A0#
V4
VGA_LVDS_A1
AA5
VGA_LVDS_A1#
AA4
VGA_LVDS_A2
W4
VGA_LVDS_A2#
Y4
AB4
AB5

GENERAL

FBBACS0# <12>

FBAA12

FBBA_CKE <12>

1

FBBA_CKE
FBBACS0#
FBAA11
FBACAS#
FBAWE#
FBA_BA0
FBBA5
FBAA12
FBA_RST
FBAA7
FBAA10

<14> VGA_LVDS_ACLK
<14> VGA_LVDS_ACLK#
<14> VGA_LVDS_A0
<14> VGA_LVDS_A0#
<14> VGA_LVDS_A1
<14> VGA_LVDS_A1#
<14> VGA_LVDS_A2
<14> VGA_LVDS_A2#

LVDS / TMDS

Part 3 of 5

FBA_BA1 <12>

Document Number

Rev
1.0

NAVD0 LA-6091P

he

FBA_DEBUG

FBARAS# <12>

2

FBA_CLK1
FBA_CLK1_N

U30C

1

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

2

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

2

B

D22
E24
E22
D24
D26
D27
C27
B27
A21
B21
C21
C19
C18
D18
B18
C16
E21
F21
D20
F20
D17
F18
D16
E16
A22
C24
D21
B22
C22
A25
B25
A26
U24
V24
V23
R24
T23
R23
P24
P22
AC24
AB23
AB24
W24
AA22
W23
W22
V22
AA25
W27
W26
W25
AB25
AB26
AD26
AD27
V25
R25
V26
V27
R26
T25
N25
N26

MEMORY INTERFACE

C

D

Part 2 of 5
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

Wednesday, March 03, 2010

1

Sheet

9

of

46

A

5

4

3

2

0.01U_0402_16V7K

1

U30D
Part 4 of 5

0.047U_0402_25V7K

1
C619
VGA@

2

1
C641
VGA@

2

0.01U_0402_16V7K

1
C629
VGA@

2

J9
J10
J12
J13
L9
M9
M11
M17
N9
N11
N12
N13
N14
N15
N16
N17
N19
P11
P12
P13
P14
P15
P16
P17
R9
R11
R12
R13
R14
R15
R16
R17
T9
T11
T17
U9
U19
W9
W 10
W 12
W 13
W 18
W 19

1
C630
VGA@

2

C631
VGA@

2
0.1U_0402_10V7K
330U_D2_2.5VY_R9M
1

0.01U_0402_16V7K
0.047U_0402_25V7K

1

+

2

C804
VGA@

2

0.01U_0402_16V7K

1
C632
VGA@

2

1
C628
VGA@

2

C622
VGA@

0.01U_0402_16V7K
091022 add C804 330U for VGA_CORE

0.047U_0402_25V7K

1

2

0.01U_0402_16V7K

1
C627
VGA@

2

1
C643
VGA@

2

C642
VGA@

0.01U_0402_16V7K

NEAR BGA

+3VSDGPU

NEAR BALL

C

1U_0402_6.3V6K

120mA

1

2

0.1U_0402_10V7K

1
C665
VGA@

2

1
C679
VGA@

4.7U 6.3V K X5R 0603

2

1
C646
VGA@

0.1U_0402_10V7K

2

C645
VGA@

A12
B12
C12
D12
E12
F12

0.1U_0402_10V7K

NEAR BALL

L33
MBK1608121YZF_0603
2
VGA@
1

300mA

C635
VGA@

2

NEAR BGA
+1.8VSDGPU
1

1

AG9

+3VSDGPU

1

2
4.7U 6.3V K X5R 0603

2

1
C690
VGA@

2

+IFPA_IOVDD

0.1U_0402_10V7K
1
C692
VGA@

2

C693
VGA@

2
10K_0402_5%
VGA@

0.1U_0402_10V7K

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33

IFPA_IOVDD

+IFPA_IOVDD

V2

IFPB_IOVDD

+IFPC_IOVDD

J6

IFPC_IOVDD

H6

IFPDE_IOVDD

1 +IFPDE_IOVDD
R623

+IFPC_PLLVDD
1U_0402_6.3V6K
1

B

2

1

C689
VGA@

+IFPD_PLLVDD
1
2
R628
0_0402_5%
VGA@

0.1U_0402_10V7K
1
C688
VGA@

2

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_PLLVDD

AF9

NEAR BGA

K6

SP_PLLVDD

L6

PLLVDD

K5

1U_0402_6.3V6K

285mA

2

C658
VGA@

C657
VGA@
2

2

4.7U 6.3V K X5R 0603

1
C662
VGA@

2

0.1U_0402_10V7K

C656
VGA@

2

C712
VGA@

0.1U_0402_10V7K

+3VSDGPU
L24

1

2

MBK1608121YZF_0603
1

220mA

2

1
C661
VGA@

2

4.7U 6.3V K X5R 0603

0.1U_0402_10V7K

1
C660
VGA@

2

1
C652
VGA@

2

0.1U_0402_10V7K

1
C653
VGA@

1U_0402_6.3V6K

1
C637
VGA@

2

4.7U 6.3V K X5R 0603

1
C648
VGA@

1
C664
VGA@

2

1
C626
VGA@

2

2

2

1
C707
VGA@

2

1U_0402_6.3V6K

1
C638
VGA@

2

1
C650
VGA@

0.1U_0402_10V7K

C649
VGA@

2

2

1
C640
VGA@

0.1U_0402_10V7K

2

22U_0805_6.3V6M

1
C639
VGA@

2

1
C708
VGA@

1U_0402_6.3V6K

2

1
C710
VGA@

2

C813
@

091022 add C813 22U follow NV review

10U_0805_6.3V6M

NEAR BGA

+1.05VSDGPU

120mA
L21

1U_0402_6.3V6K

1

2

C636
VGA@

2

C

1
2
MBK1608121YZF_0603
VGA@

1
C647
VGA@

+PEX_PLLVDD

NEAR BALL
12~16mil

DACA_VDD

AG2

+DACA_VDD

DACB_VDD

W5

+DACB_VDD

NEAR BGA

0.1U_0402_10V7K 1U_0402_6.3V6K

1

2

1
C714
VGA@

2

1
C681
VGA@

2

1
C682
VGA@

2

C655
VGA@

W 15

D7

IFPE_PLLVDD

VDD_SENSE

E15

+1.05VSDGPU

MBK1608121YZF_0603
2
1
L29
1
VGA@
C683
VGA@
2

VID_PLLVDD=45mA
SP_PLLVDD=45mA
PLLVDD=60mA

+FB_PLLAVDD
4.7U 6.3V K X5R 0603

091212 Add C714 for +1.05VS_PLL
0104 Modify FB_CAL_PD_VDDQ connect from +1.5VS to +1.5VSDGPU
1
R626 VGA@

10K_0402_5%

B15
R637

+1.05VSDGPU

2
+SP_PLLVDD

VDD_SENSE

+1.5VSDGPU

VGA@ 40.2_0402_1%

1

The power is base on VRAM type.
+VGASENSE

L32
1
2
MBK1608121YZF_0603
VGA@

1U_0402_6.3V6K

+VGASENSE <43>

2

1
C716
VGA@

2

1
C654
VGA@

B

091212 Add C716 for +SP_PLLVDD

C685
VGA@

2
4.7U 6.3V K X5R 0603

0.1U_0402_10V7K

NEAR BALL
120mA

091216 change GPU P/N to
SA00003UD00

+3VSDGPU

+1.05VSDGPU

+FB_PLLAVDD

NEAR BGA
1U_0402_6.3V6K

1

C678
VGA@

2

C623
VGA@

2

L20

1
2
MBK1608121YZF_0603
VGA@

1

FB_PLLVDD=100mA
FB_DLLVDD=100mA

C617
VGA@

4.7U 6.3V K X5R 0603

0.1U_0402_10V7K
1U_0402_6.3V6K

L34
+IFPAB_PLLVDD

1

2

C709
VGA@

10U_0805_6.3V6M

4.7U 6.3V K X5R 0603

1

0.1U_0402_10V7K

FB_CAL_PD_VDDQ

2

2

NEAR BGA

0.1U_0402_10V7K

1

T19

IFPD_PLLVDD

C663
VGA@

2A

22U_0805_6.3V6M

+1.05VSDGPU

NEAR BALL

AC19

IFPC_PLLVDD

1

N10M-GS: 2.63A
N11M-GE1:2.55A

1

1
C706
VGA@

1U_0402_6.3V6K

NEAR BALL
+DACA_VDD

C659
VGA@

+3VSDGPU

NEAR BGAMBK1608121YZF_0603

4700P_0402_25V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

2

1
VGA@

1

2

+IFPC_PLLVDD

1
C702
VGA@

470P_0402_50V7K

2

1
C701
VGA@

2

1
C699
VGA@

2

0.1U_0402_10V7K

1
C695
VGA@

2

1
C700
VGA@

2

120mA

1
C698
VGA@

0.1U_0402_10V7K

2

C703
VGA@
A

4.7U 6.3V K X5R 0603

1
C651
VGA@

2
2
0.1U_0402_10V7K

C717
VGA@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

091212 Add C717 for +SP_PLLVDD

0.1U_0402_10V7K

2009/10/09

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C618
VGA@

0.047U_0402_25V7K

0.1U_0402_10V7K

NEAR BALL
1U_0402_6.3V6K

C624
VGA@

2

NEAR BGA

0.1U_0402_10V7K

4.7U 6.3V K X5R 0603
VGA@
2

0.01U_0402_16V7K

NEAR BALL

IFPAB_PLLVDD

VGA@
2

220mA

C625
VGA@

2

2

NEAR BGA
1

C633
VGA@

2

D

FB_PLLAVDD

NEAR BGA

+1.05VSDGPU
L23
1

C620
VGA@

2

1

+1.05VSDGPU

FB_DLLAVDD

091212 Add C712 for +IFPC_IOVDD

MBK1608121YZF_0603

A

0.01U_0402_16V7K

1

1

C621
VGA@

1

2

0.1U_0402_10V7K

1

2

1

+1.05VS_PLL

R19

VGA@

1

C644
VGA@

1

0.1U_0402_10V7K

P6

1 @
R627
1 VGA@ +IFPE_PLLVDD
R624

1

+SP_PLLVDD

FB_PLLAVDD

NEAR BALL

1

0.047U_0402_25V7K

4.7U 6.3V K X5R 0603

VID_PLLVDD

N11M-GE1-S-A2 _BGA533
VGA@

2
10K_0402_5%
2
10K_0402_5%

2

AG6
AF6
AE6
AD6
AC13
AC7
AB17
AB16
AB13
AB9
AB8
AB7

N6

C687
VGA@

2

0.1U_0402_10V7K

+1.05VSDGPU L22
MBK1608121YZF_0603

AD5

A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22

AG7
AF7
AE7
AD8
AD7
AC9

PEX_SVDD_3V3

V3

+IFPAB_PLLVDD

2

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

1U_0402_6.3V6K

C694
VGA@

1

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

POWER

4.7U 6.3V K X5R 0603

N10M-GS: 15.8A
N11M-GE1:16.7A

0.047U_0402_25V7K

4.7U 6.3V K X5R 0603

NEAR BALL

D

CLOSE
TO GPU
+1.5VSDGPU

PLACE UNDER GPU

NEAR
BGA
VGA_CORE

1

1

4

3

2

Title

N11M-OP2 PWR
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

Wednesday, March 03, 2010

Sheet
1

10

of

46

5

4

3

2

1

A total of 8 signals are required for GB1 strapping this includes
2 reference signals
6 physical strapping pins
4 logical strapping bits
A total of 24 logical strapping bits are available

U30E

GPU

FB_CAL_TERM_GND

B16

R616 1

GND_SENSE MULTI_STRAP_REF1_GND

F11

2 60.4_0402_1%

N11M-GE1
LP1
(0x0A7D)
40nm

VGA@

F10

R636
40.2K_0402_1%
VGA@

FB Memory (DDR3)
Samsung
800MHz
(defaul)

K4W1G1646E-HC12

Hynix
800MHz

H5TQ1G63BFR-12C

64Mx16

64Mx16

1
2
2

ROM_SO

ROM_SCLK

ROM_SI

STRAP2

STRAP1

STRAP0

PD 10K

PD 15K

PD 20K

PU 45K

PU 35K

PU 45K

PD 10K

PD 15K

PD 15K

PU 45K

PU 35K

PU 45K

2

R635
40.2K_0402_1%
VGA@

X76

2

Place Components Close to BGA
091216 change GPU P/N to SA00003UD00

B

Pull-up to VDD

Pull-down to GND

10K_0402_5%

R638
VGA@

C

N11M-GE1-S-A2 _BGA533
VGA@

Resistor
Values

15K_0402_1%

HY@

1

2
1
2

R642
SAM@
20K_0402_1%

2

15K_0402_1%

R629
VGA@

R639
@

2K_0402_5%

1
R641
@
2K_0402_5%

1
1

2

15K_0402_1%

1
2
1
2

R648
@
10K_0402_5%

1
2

45.3K_0402_1%

34.8K_0402_1%

1
2

R630
@

STRAP1 use for 3GIO_PADCFG to set 35K pull up.
(PUN-04335-001_V10 HW9 update)

R617 1 VGA@ 2 40.2_0402_1%

GND_SENSE MULTI_STRAP_REF0_GND

R645
VGA@

R643
@

34.8K_0402_1%

1
2

R647
@

A15

FB_CAL_PU_GND

STRAP2
STRAP1
STRAP0
ROM_SCLK
ROM_SI
ROM_SO

R644

VGA@

1

<9>
<9>
<9>
<9>
<9>
<9>

STRAP2
STRAP1
STRAP0
ROM_SCLK
ROM_SI
ROM_SO

45.3K_0402_1%

R646
VGA@

1

E14

D

R642

1

C

+3VSDGPU

2

W16

D

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

U2
U5
U11
U12
U13
U14
U15
U16
U17
U23
U26
V9
V19
W11
W14
W17
Y2
Y5
Y23
Y26
AC2
AC5
AC6
AC8
AC11
AC14
AC17
AC20
AC23
AC26
AF2
AF5
AF8
AF11
AF14
AF17
AF20
AF23
AF26
T16
T15
T14
F6

30K_0402_1%

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

Part 5 of 5

GND

B2
B5
B8
B11
B14
B17
B20
B23
B26
E2
E5
E8
E11
E17
E20
E23
E26
H2
H5
J11
J14
J17
K9
K19
L2
L5
L11
L12
L13
L14
L15
L16
L17
M12
M13
M14
M15
M16
P2
P5
P9
P19
P23
P26
T12
T13

SUB_VENDOR

XCLK_417

0*

No VBIOS ROM (Default)

0*

277MHz (Default)

1

BIOS ROM is present

1

Reserved

5Kohm

1000

0000

10Kohm

1001

0001

15Kohm

1010

0010

User[3:0]

20Kohm

1011

0011

EDID used *

25Kohm

1100

0100

30Kohm

1101

0101

0*

256MB (Default)

0

3D Device

35Kohm

1110

0110

1

Reserved

1*

VGA Device (Default)

45Kohm

1111

0111

Panel USER Straps

Customer defined

FB_0_BAR_SIZE

SMBUS_ALT_ADDR
0*

0x9E (Default)

1

0x9C (Multi-GPU usage)

VGA_DEVICE

PEX_PLL_EN_TERM

3GIO_PADCFG

0*

Disable (Default)

3GIO_PADCFG[3:0]

1

Enable

0110

*

Physical
Strapping
Pin

Power
Rail

Logical
Strapping
Bit 3

Logical
Strapping
Bit 2

Logical
Strapping
Bit 1

ROM_SO

VDD33

XCLK_417

FB_0_BAR_SIZE

SMB_ALT_ADDR

ROM_SCLK

VDD33

PCI_DEVID[4]

SUB_VENDOR

SLOT_CLK_CFG

ROM_SI

VDD33

RAMCFG[3]

RAMCFG[2]

STRAP2

VDD33

PCI_DEVID[3]

PCI_DEVID[2]

STRAP1

VDD33

3GIO_PADCFG[3] 3GIO_PADCFG[2]

STRAP0

VDD33
Memory/PKG

N11M-GE1
LP1

DDR3

USER[3]
FBVDDQ
+1.5VS

USER[2]

RAMCFG[1]

Must be used 1% resister for driver calibration

VGA_DEVICE
PEX_PLL_EN_TERM

B

RAMCFG[0]

PCI_DEVID[1]

PCI_DEVID[0]

3GIO_PADCFG[1] 3GIO_PADCFG[0]
USER[1]

FB_CAL_PU_GND FBCAL_PD_VDDQ
40.2 ohm

Logical
Strapping
Bit 0

40.2 ohm

USER[0]
FBCAL_TERM_GND
40.2/60.4 ohm

DG-04642-001-V01(May 22, 2009)

Notebook Default

GPU and MCH share a common reference clock (Default)

ai

GPU and MCH don't share a common reference clock

1

5

4

3

2

N11M-OP2 GND & STRAP

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
B
Date:

xa

2010/10/09

Deciphered Date

Document Number

Rev
1.0

NAVD0 LA-6091P

he

2009/10/09

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

0*

l.c
om

SLOT_CLOCK_CFG
A

Wednesday, March 03, 2010

1

Sheet

11

of

46

A

5

4

+VRAM_VREFB

<9> FBADQS[0..7]
<9> FBADQS#[0..7]
D

<9> FBA_D[0..63]

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13

FBADQM[0..7]
FBADQS[0..7]
FBADQS#[0..7]
FBA_D[0..63]

FBA_BA0
FBA_BA1
FBA_BA2

<9> FBA_BA0
<9> FBA_BA1
<9> FBA_BA2

<9> FBACLK0
<9> FBACLK0#
<9> FBAA_CKE
<9>
<9>
<9>
<9>
<9>

FBAA_CKE

FBAAODT0
FBAACS0#
FBARAS#
FBACAS#
FBAWE#

C

<9> FBA_RST

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8
M3
N9
M4

J8
K8
K10

FBAAODT0
FBAACS0#
FBARAS#
FBACAS#
FBAWE#

K2
L3
J4
K4
L4

FBADQS1
FBADQS3

F4
C8

FBADQM1
FBADQM3

E8
D4

FBADQS#1
FBADQS#3

G4
B8

FBA_RST

T3

BA0
BA1
BA2

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET

FBA_D9
FBA_D14
FBA_D8
FBA_D12
FBA_D10
FBA_D13
FBA_D11
FBA_D15

1

D8
C4
C9
C3
A8
A3
B9
A4

FBA_D24
FBA_D30
FBA_D26
FBA_D29
FBA_D28
FBA_D25
FBA_D27
FBA_D31

3

M9
H2
FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13

J2
L2
J10
L10

VGA@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

R605
240_0402_1%

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

+1.5VSDGPU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FBA_BA0
FBA_BA1
FBA_BA2

B3
D10
G8
K3
K9
N2
N10
R2
R10

FBAAODT0
FBAACS0#
FBARAS#
FBACAS#
FBAWE#

K2
L3
J4
K4
L4

FBADQS2
FBADQS0

F4
C8

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

FBADQM2
FBADQM0

E8
D4

FBADQS#2
FBADQS#0

G4
B8

FBA_RST

T3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

L9

E4
F8
F3
F9
H4
H9
G3
H8

FBA_D21
FBA_D18
FBA_D20
FBA_D16
FBA_D22
FBA_D19
FBA_D23
FBA_D17

D8
C4
C9
C3
A8
A3
B9
A4

FBA_D4
FBA_D1
FBA_D5
FBA_D2
FBA_D6
FBA_D0
FBA_D7
FBA_D3

M9
H2
FBAA0
FBAA1
FBBA2
FBBA3
FBBA4
FBBA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13

2

0

A1
A11
T1
T11

NC
NC
NC
NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
B10
D2
D9
E3
E9
F10
G2
G10

ZQ/ZQ0

J2
L2
J10
L10

R612
240_0402_1%
VGA@

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

091126 swap nets for layout

+1.5VSDGPU

BA0
BA1
BA2

J8
K8
K10

A2
A9
C2
C10
D3
E10
F2
H3
H10

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M3
N9
M4

FBACLK0
FBACLK0#
FBAA_CKE

+1.5VSDGPU

VREFCA
VREFDQ

FBA_BA0
FBA_BA1
FBA_BA2

B3
D10
G8
K3
K9
N2
N10
R2
R10

J8
K8
K10

FBBA_CKE

<9> FBBA_CKE

A2
A9
C2
C10
D3
E10
F2
H3
H10

M3
N9
M4

FBACLK1
FBACLK1#

<9> FBACLK1
<9> FBACLK1#
+1.5VSDGPU

<9> FBBAODT0
<9> FBBACS0#

FBBAODT0
FBBACS0#
FBARAS#
FBACAS#
FBAWE#

K2
L3
J4
K4
L4

FBADQS4
FBADQS7

F4
C8

FBADQM4
FBADQM7

E8
D4

FBADQS#4
FBADQS#7

G4
B8

FBA_RST

T3

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

L9

1

ZQ/ZQ0

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E4
F8
F3
F9
H4
H9
G3
H8

1

L9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

U34

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E4
F8
F3
F9
H4
H9
G3
H8

FBA_D37
FBA_D36
FBA_D35
FBA_D32
FBA_D39
FBA_D34
FBA_D38
FBA_D33

D8
C4
C9
C3
A8
A3
B9
A4

FBA_D61
FBA_D62
FBA_D56
FBA_D63
FBA_D58
FBA_D57
FBA_D59
FBA_D60

M9
H2
FBAA0
FBAA1
FBBA2
FBBA3
FBBA4
FBBA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13

4

7

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A1
A11
T1
T11

NC
NC
NC
NC

100-BALL
SDRAM DDR3

B2
B10
D2
D9
E3
E9
F10
G2
G10

J2
L2
J10
L10

R600
240_0402_1%
VGA@

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

A1
A11
T1
T11

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC

100-BALL
SDRAM DDR3

K4W1G1646E-HC12
SAM@

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

FBA_BA0
FBA_BA1
FBA_BA2

B3
D10
G8
K3
K9
N2
N10
R2
R10

M3
N9
M4

FBACLK1
FBACLK1#
FBBA_CKE

+1.5VSDGPU

J8
K8
K10

FBBAODT0
FBBACS0#
FBARAS#
FBACAS#
FBAWE#

A2
A9
C2
C10
D3
E10
F2
H3
H10
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

K2
L3
J4
K4
L4

FBADQS5
FBADQS6

F4
C8

FBADQM5
FBADQM6

E8
D4

FBADQS#5
FBADQS#6

G4
B8

FBA_RST

T3
L9

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E4
F8
F3
F9
H4
H9
G3
H8

FBA_D42
FBA_D46
FBA_D40
FBA_D45
FBA_D41
FBA_D47
FBA_D44
FBA_D43

D8
C4
C9
C3
A8
A3
B9
A4

FBA_D50
FBA_D53
FBA_D48
FBA_D52
FBA_D51
FBA_D54
FBA_D49
FBA_D55

5

D

6
091026 swap nets for layout

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B3
D10
G8
K3
K9
N2
N10
R2
R10

+1.5VSDGPU

A2
A9
C2
C10
D3
E10
F2
H3
H10
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

C

1

<9> FBADQM[0..7]

FBBA[2..5]

VREFCA
VREFDQ

U31

K4W1G1646E-HC12
SAM@
U32

B2
B10
D2
D9
E3
E9
F10
G2
G10

J2
L2
J10
L10

R651
240_0402_1%
VGA@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

FBBA[2..5]

M9
H2

U32

1

<9>

FBAA[0..13]

+VRAM_VREFC

+VRAM_VREFA

2

FBAA[0..13]

1

+VRAM_VREFD

+VRAM_VREFC
+VRAM_VREFA
U33

<9>

2

+VRAM_VREFD

2

N10x 40nm DDR3 MAPPING
NVIDIA COCUMENT FOR DA-3978-001

3

+VRAM_VREFB

A1
A11
T1
T11

NC
NC
NC
NC

100-BALL
SDRAM DDR3

100-BALL
SDRAM DDR3

K4W1G1646E-HC12
SAM@

K4W1G1646E-HC12
U31

B2
B10
D2
D9
E3
E9
F10
G2
G10

U34

SAM@

U33

H5TQ1G63BFR-12C

HY@

HY@

2

C604
VGA@
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M

C603
VGA@

C805

1
R611
1.33K_0402_1%
VGA@

@
2

15MIL

15MIL
1

R603
1.33K_0402_1%
VGA@

VGA@

2

2

1

+1.5VSDGPU

B

+VRAM_VREFB

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

1

0.1U_0402_10V6K

R610
1.33K_0402_1%
VGA@

0.1U_0402_10V6K

VGA@
243_0402_1%
R633
FBACLK0#

R604
1.33K_0402_1%
VGA@

+VRAM_VREFA

1

2

2

FBACLK0

10U_0603_6.3V6M
10P_0402_50V8J
1
1
1

2

2
10U_0603_6.3V6M

C600
VGA@

1

C675
VGA@

VGA@

2

2

2

10U_0603_6.3V6M
1
1

1

C697
VGA@

2

C615
VGA@

C616

10U_0603_6.3V6M
1
B

+1.5VSDGPU
1

+1.5VSDGPU

C601

+1.5VSDGPU

HY@

H5TQ1G63BFR-12C

HY@

H5TQ1G63BFR-12C

H5TQ1G63BFR-12C

FBACLK1
091020 reserve C805/C806/C807
10P for RF solution

@

2
10P_0402_50V8J

1

15MIL
1

2

R650
1.33K_0402_1%
VGA@

VGA@

2009/10/09

Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

2

VGA@
A

Title

N11M-OP2 VRAM DDR3
Size
C
Date:

5

1

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Issued Date

+VRAM_VREFD
2

2
R601
1.33K_0402_1%
VGA@
2

2

15MIL

0.1U_0402_10V6K

2
10P_0402_50V8J

R653
1.33K_0402_1%
VGA@

+VRAM_VREFC

2

+

@

R602
1.33K_0402_1%
VGA@

0.1U_0402_10V6K

A

1

C807

1

C613

1

C610

1

C608

1

C609

1

C611

1

C612

1

C606

1

C607

1

C674

C705

1

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2
2
2
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

C672
220U_B2_2.5VM_R35

VGA@

1

1

+1.5VSDGPU

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

C605

+1.5VSDGPU

1

+1.5VSDGPU

1

+1.5VSDGPU

C686

1
2

1

C806

1

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2
2
2
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

C704

1

C677

1

C676

1

C673

1

C680

1

C684

1

C614

1

C602

1

C691

FBACLK1#

C696

1
R606
243_0402_1%
VGA@

Document Number

Rev
1.0

NAVD0 LA-6091P
Wednesday, March 03, 2010

Sheet
1

12

of

46

5

4

3

Change C174 C175 to 10U_0603 05/14

FSA

CLKSEL1

CLKSEL0

0

0

0

CPU
MHz

0

0

SRC
MHz

266

1

100

133

100

PCI
MHz

REF
MHz

33.3

DOT_96 USB
MHz
MHz

14.318

33.3

96.0

14.318

1
2
R1370_0603_5%

+3VS

10U_0603_6.3V6M
1
C174

1

0.1U_0402_16V4Z
1
C138

C172

1

CLK_SMBDATA

C15

1

2 @ 100P_0402_50V8J

CLK_SMBCLK

C16

1

2 @ 100P_0402_50V8J

C148

R72

2
47P_0402_50V8J

48.0

2

2
0.1U_0402_16V4Z

2

2

Q10A
6

0.1U_0402_16V4Z

091212 Add C15 C16 near Q10
to prevent switch noise

<19> ICH_SMBDATA

96.0

R138
1
2
0_0603_5%

48.0
+VCCP

1

166

100

33.3

14.318

96.0

10U_0603_6.3V6M

1

48.0

1

D

1

0

0

333

100

33.3

14.318

96.0

48.0

1

0

1

100

100

33.3

14.318

96.0

48.0

1

1

0

400

100

33.3

14.318

96.0

48.0

1

1

1

1

C1146

2
47P_0402_50V8J

0.1U_0402_16V4Z
1
C167

1

C139

+3VS

0.1U_0402_16V4Z
1
C146

C137

2
0.1U_0402_16V4Z

2

2

2
0.1U_0402_16V4Z

2

Change co-lay net name to

C165

+1.5VS

1
R1349

2
0_0603_5%

+3VS

R1487
1 OPT@ 2
10K_0402_5%

2

10U_0603_6.3V6M
1
1
47P_0402_50V8J
C1119

PEG_CLKREQ#_R

1

2

2

2

2
2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

+1.05VM_CK505

3

R1350
1
R1351
1

+VCCP
+1.5VS

@

0_0402_5%
2
0_0402_5%
2

VDD_SRC_IO

1

+VCCP

1

@
091020 change value of
C386 from 10P to 22P

R68 @

CLK_48M_CR

<27> CLK_48M_CR

1
R376

1

2

1
C390

0111Change BOM Structure of C390 from @ to mount
091020 change value of C390 from 10P to 22P

2
R1528
2
R1529

1

70

CLK_CPU_BCLK#

CPU_1

68

CLK_CPU_HPLCLK

CPU_1#

67

CLK_CPU_HPLCLK#

VDD_48

27

VDD_PLL3

66

VDD_CPU_IO

SRC_0/DOT_96

24

CPU_DREFCLK

31

VDD_PLL3_IO

SRC_0#/DOT_96#

25

CPU_DREFCLK#

VDD_SRC_IO

23

20

R1289
10_0402_5%
@

2

FS_B/TEST_MODE
REF_0/FS_C/TEST_

1

1

CLK_XTAL_IN

5

CLK_XTAL_OUT

4

PCI2_TME
C388
22P_0402_50V8J
@

091210 add C392/C393 22P for RF team

1

<17> CLK_PCI_PCH

1

R86

2

For PCI4_SEL, 0 = Pin24/25
Pin28/29
1 = Pin24/25
Pin28/29

R87
0_0402_5%
@

:
:
:
:

R80

2
33_0402_5%
2
33_0402_5%

1

1
C393
22P_0402_50V8J
2 @

C389
22P_0402_50V8J 2
@

CLK_PCIE_WLAN#

SRC_6

57

CLK_PCIE_SATA

56

CLK_PCIE_SATA#

61

CLK_PCIE_PCH

60

CLK_PCIE_PCH#

NC

2
R95

R71

10K_0402_5%
@

10K_0402_5%
@

10K_0402_5%

CPU_STOP#
SRC_7
PCI_STOP#
XTAL_IN
SRC_8/CPU_ITP
XTAL_OUT

63

PCI4_SEL

CLK_PCIE_PCH

1 10K_0402_5%

R121 2

1 10K_0402_5%

WWAN_CLKREQ#

R107 2

1 10K_0402_5%

<19>
B

CLK_PCIE_LAN

51

CLK_PCIE_LAN#

48

CLK_PCIE_WWAN

SRC_10#

<19>

CLK_PCIE_PCH#

50

PCI_4/SEL_LCDCL

R1530 2

WLAN_CLKREQ#

64

SRC_8#/CPU_ITP#

PCI_3

LAN_CLKREQ#

CLK_CPU_EXP <4>
CLK_CPU_EXP# <4>
CLK_PCIE_LAN

<26>

CLK_PCIE_LAN#

<26>

PCIF_5/ITP_EN

18

VSS_PCI

3

VSS_REF

SRC_11#

VSS_48

CLKREQ_3#

47

37
41

CLK_PCIE_WWAN#
Add PEG_CLKREQ# 09/10/08
PU to +3VS
DIS@
PEG_CLKREQ#_R
1
2
R804
0_0402_5%
WLAN_CLKREQ#

VSS_IO

CLKREQ_4#

VSS_CPU

CLKREQ_6#

VSS_PLL3

CLKREQ_7#

VSS_SRC

CLKREQ_9#

59

VSS_SRC

SLKREQ_10#

49

LAN_CLKREQ#

42

VSS_SRC

CLKREQ_11#

46

WWAN_CLKREQ#

VSS

USB_1/CLKREQ_A#

CLK_PCIE_WWAN

REQ PORT LIST

<24>

CLK_PCIE_WWAN#

<24>

PORT
WLAN_CLKREQ#

REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#

<25>

Add WWAN_CLKREQ# 05/04

58
65
43

Add LAN_CLKREQ# 091116
LAN_CLKREQ#

<26>

WWAN_CLKREQ#

<24>

21

SLG8SP556VTR_QFN72_10X10

0303 change U4 P/N from SA00003H730 to SA00003H610
PCI2_TME

2

R89

R90

@
R77

10K_0402_5%

10K_0402_5%

10K_0402_5%

Issued Date

2009/10/09

Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Routing the trace at least 10mil
4

PCIE_VGA
PCIE_WLAN

PCIE_LAN
PCIE_WWAN

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1

27P_0402_50V8J

2

2
CLK_XTAL_OUT

1

2

14.318MHZ_16PF_7A14300083

DEVICE

PEG_CLKREQ#

1

ITP_EN

<25>

CLK_PCIE_SATA# <18>

SRC_10

73

1

1

1

R85

<25>

CLK_PCIE_WLAN#

CLK_PCIE_SATA <18>

CLK_CPU_EXP#

30

+3VS

C

<8>

CKPWRGD/PD#

CLK_CPU_EXP

69

2

2

2

06/05

Y1

5

SRC_4#

40

45

22

<5>

PCIE_VGA
PCIE_WLAN
PCIE_SATA
PCIE_PCH
CPU_ITP
CLK_CPU_EXP
PCIE_LAN
PCIE_WWAN

<8>

CLK_PCIE_WLAN

44

26

+3VS

CLK_XTAL_IN

C164

CLK_PCIE_WLAN

SRC_9

34
+3VS

27P_0402_50V8J

39

SRC_4

SRC_9#

17

<5>

CPU_SSCDREFCLK#

CLK_PCIE_VGA#

PCI_2

16

<5>

CPU_SSCDREFCLK

CLK_PCIE_VGA

PCI_1

ITP_EN

<5>

<5>

CPU_SSCDREFCLK

+3VS

REF_1

SRC_11

DOT96 / DOT96#
LCDCLK / LCDCLK#
SRC_0 / SRC_0#
27M/27M_SS

A

C161

CLK_PCIE_VGA#

14

PCI4_SEL

For PCI2_TME:0=Overclocking of CPU and SRC allowed
(ICS only)
1=Overclocking of CPU and SRC NOT allowed

Follow Intel check list change to 27P

36

SRC_3#

13

15

<31> CLK_PCI_LPC

1

1
2
R84
0_0402_5%

470_0402_5%

1

R98
10K_0402_5%
2
1

54

CLK_CPU_HPLCLK#

Add CLK to GPU 09/10/08
CLK_PCIE_VGA

SRC_6#
53

33
35

SRC_3

7

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
R92 @

32

0301 Change BOM Structure of R1289 and C388/C389/C393/C390 from NOR_CLK@ to @

2

2

1

SRC_2

SRC_7#

+VCCP

<5> CPU_BSEL2

@

CPU_SSCDREFCLK#

USB_0/FS_A

2

0_0402_5%
H_STP_CPU#_R
2
0_0402_5%
H_STP_PCI#_R
2

091015 add R801/R802 0ohm

R110
@
0_0402_5%

FSC

H_STP_PCI#

<19> H_STP_PCI#

CPU_SSCDREFCLK

29

DEVICE

SRC1
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11

<5>

CPU_DREFCLK#

28

PORT

<5>

CLK_CPU_HPLCLK

CPU_DREFCLK

LCDCLK/27M

VDD_SRC_IO

FSC

@
1
2
R371
0_0402_5%

<5>

CLK_CPU_BCLK#

VDD_IO

FSB

8

CLK_CPU_BCLK

LCDCLK#/27M_SS

SRC_2#
FSA

SRC PORT LIST

CLK_SMBCLK <7,24>

CPU_0

38

1

1
2
R119
0_0402_5%

<5> CPU_BSEL1

<19> H_STP_CPU#

CLK_CPU_BCLK

CPU_0#

CLK_PCI_LPC

2

R52 1K_0402_1%
FSB
1
2

1

B

R113
@
470_0402_5%

<8>

ho

Add 1K follow
Intel check list 05/11

R801
1
R802
1

71

CLK_SMBDATA <7,24>

VDD_CPU

11

H_STP_CPU#

CLK_SMBCLK

VDD_PCI

+3VS
@ 1 H_STP_CPU#_R
10K_0402_5%
1 H_STP_PCI#_R
10K_0402_5%

CLK_SMBDATA

10

19

0.1U_0402_16V4Z

CLK_EN

+VCCP

9

SCL

72

VDD_SRC_IO

<5,19,31,42> VGATE

PEG_CLKREQ#

VDD_REF

52

@

1K_0402_5%
@

SDA

12

62

1 R104
2
33_0402_5%
2
22P_0402_50V8J

<8,31,35>

OPT@

VDD_SRC

C173

1 R74
2
22_0402_5%
1 R75
2
22_0402_5%

FSA_R
2
0_0402_5%

<19> CLK_PCH_14M
R73

2

091029 add R376 0_0402_5%
for EMI solution

<19> CLK_PCH_48M

1

1
2
R69
0_0402_5%

<5> CPU_BSEL0

470_0402_5%

2 22P_0402_50V8J

1
C386

2

R76
2.2K_0402_5%
FSA 2
1

1

0301Change R1349,R1351 BOM structure from LOW_CLK@ to mount
0301Change R1348,R1350 BOM structure from NOR_CLK@ to @

DTC115EUA_SC70-3

C

Rename 06/06

6

C1147
Q31

DGPU_PWR_EN

SSM3K7002FU_SC70-3
3

f@

1

CLK_EN

55
0.1U_0402_16V4Z
1
1
C140
C160
C169

R1488
2 OPT@ 1
10K_0402_5%

Q63

U4

+1.5VM_CK505

2
0_0603_5%

10K_0402_5%

<42> CLK_ENABLE#

+3VM_CK505

@

R435

D

tm

1
R1348

CLK_SMBCLK

100112 change Q47 P/N from SB00000AR00 to SB00000DH00

+3VS
+3VS

2N7002DW-T/R7_SOT363-6
4

3

<19> ICH_SMBCLK

0.1U_0402_16V4Z

2

SA000020K00 (Silego : SLG8SP556VTR )
SA000020H10 (ICS : ICS9LPRS387AKLFT)
+1.5VM_CK505 07/03

Reserved

Q10B

1

C175

3

2

in

1

Title

Clock Generator CK505

Size
Date:

xa

0

2

14.318

5

33.3

Document Number

he

100

2
G

200

S

0

CLK_SMBDATA

2N7002DW-T/R7_SOT363-6

D

1

2.2K_0402_5%

1

+1.05VM_CK505

0

R91

2.2K_0402_5%

C1145

48.0

96.0

1

l.c
om

FSB

CLKSEL2

1

+3VS

ai

FSC

2

Add C1145 C1146 C1147 for EMI 06/12

+3VM_CK505

Rev
1.0

NAVD0 LA-6091P

Wednesday, March 03, 2010

Sheet
1

13

of

46

5

4

3

2

2
R1182

LCD POWER CIRCUIT
+LCDVDD

@

1

1
0_0402_5%
L3

091015 follow NTV00 Design

USB20_N3_1

+3VALW

2

2

1

D6
1

USB20_N3

4

USB20_P3

1

USB20_N3 <19>

GND

VCC

4

+CAM_VCC

3

Q4B
2N7002DW-T/R7_SOT363-6

G

Q3
AO3413_SOT23-3
1

2

4

1
47K_0402_5%

6
1

2

1
1

3

1

S

IO1

IO2

3

USB20_N3_1
D

091203 change P/N of D6 to SC300000100

1
0_0402_5%

+3VS

1

R807

2

1

C1113
0.1U_0402_16V4Z

1

@
C1106
4.7U_0805_10V4Z

+CAM_VCC

2

0_0603_5%

C1105
0.1U_0402_16V4Z

2

091020 change JUMP J1 to R807 0ohm

Q42

2
G
SSM3K7002FU_SC70-3
DIS@

2

R700
10K_0402_5%
DIS@
C

@

W=60mils

2
D

2
R1183

2

PRTR5V0U2X_SOT143
@

+LCDVDD

C1108
0.1U_0402_16V4Z

1

<8> VGA_ENVDD

USB20_P3 <19>

0111 Change BOM Structure of L3 from @ to mount and R1182/R1183 from mount to @

1

Q4A
2N7002DW-T/R7_SOT363-6
2
@
R174
100K_0402_5%

4

D

2
R579

2

<5> GMCH_ENVDD

091103 del C1167/C1168

W=60mils
5

3

WCM2012F2S-900T04_0805

R578
47K_0402_5%
2

3 2

R577
150_0603_5%

3

USB20_P3_1

S

D

USB20_P3_1

1

1

+3VS

OPTIMUS

2009/10/07 Add Q42 and R700 for DIS only

C

100112 change Q47 P/N from SB00000AR00 to SB00000DH00
<5> GMCH_LVDS_A0
<5> GMCH_LVDS_A0#
<5> GMCH_LVDS_A1
<5> GMCH_LVDS_A1#

CMOS & LCD/PANEL BD. Conn.

<5> GMCH_LVDS_A2
<5> GMCH_LVDS_A2#
+3VS

Modify JLVDS1 08/04

20100106 add R1186 connect pin1 of JLVDS1 to GND
0_0402_5%

2

1 R1186

0_0402_5%

2

1 R1185

LVDS_SCL

JLVDS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

B

USB20_P3_1
USB20_N3_1

<5> GMCH_LVDS_ACLK
<5> GMCH_LVDS_ACLK#

@

camera

DMIC_CLK_LVDS
DMIC_DATA_LVDS

LVDS_SDA

+3VS

1
R1180
1
R1181

C1306
56P_0402_50V8

+CAM_VCC

DMIC_CLK_LVDS <28>
DMIC_DATA_LVDS <28>

LVDS_ACLK
LVDS_ACLK#

C1307
56P_0402_50V8

2
2.2K_0402_5%
2
2.2K_0402_5%

1

<5> GMCH_LVDS_SCL
<5> GMCH_LVDS_SDA
<5,31> INVT_PWM

1

GMCH_LVDS_A0
GMCH_LVDS_A0#

LVDS_A0
3
LVDS_A0#
4
OPT@ 0_0404_4P2R_5%
GMCH_LVDS_A1
LVDS_A1
2
3
GMCH_LVDS_A1#
LVDS_A1#
1
4
RP8
OPT@ 0_0404_4P2R_5%
GMCH_LVDS_A2
LVDS_A2
2
3
GMCH_LVDS_A2#
LVDS_A2#
1
4
RP9
OPT@ 0_0404_4P2R_5%
GMCH_LVDS_ACLK
LVDS_ACLK
2
3
GMCH_LVDS_ACLK#
LVDS_ACLK#
1
4
RP10
OPT@ 0_0404_4P2R_5%
GMCH_LVDS_SCL R1498 1 OPT@ 2
LVDS_SCL
GMCH_LVDS_SDA R1499 1 OPT@ 2 0_0402_5%
LVDS_SDA
INVT_PWM
INVTPWM
R1500 1 VGA@ 2 0_0402_5%
0_0402_5%
091202 swap A0/A0#,A1/A1#,A2/A2#,ACLK/ACLK#
nets on RP7/RP8/RP9/RP10

2

091209 change BOM Structure of R1500 from OPT@ to VGA@

091020 change value of C1109 from 220P to 1200P

2

LVDS_A2
LVDS_A2#

INVTPWM
C1109
1
C1156

DISPOFF#
LVDS_A1
LVDS_A1#

2
1

RP7

DIS ONLY

1200P_0402_50V7K
2
220P_0402_50V7K

B

091130 combine Digital MIC into LVDS
follow NAV50 Pin definition

LVDS_A0
LVDS_A0#

0111 Change BOM Structure of C1306/C1307/C1308 from @ to mount
Change P/N from SE071100J80 to SE071560J80

LVDS_SDA
LVDS_SCL
DISPOFF#
INVTPWM

C1308
56P_0402_50V8

+3VS

+LCDVDD_L
L2
FBMA-L11-160808-221LMT 0603

+LCDVDD

+LEDVDD
2

1

CONN@

1

<9> VGA_LVDS_A1#
<9> VGA_LVDS_A1

2

<9> VGA_LVDS_A2#
<9> VGA_LVDS_A2

(20 MIL)

L1
FBMA-L11-160808-221LMT 0603

ACES_88341-3000B001

<9> VGA_LVDS_A0#
<9> VGA_LVDS_A0

+LCDVDD

<9> VGA_LVDS_ACLK#
<9> VGA_LVDS_ACLK

B+
1

C1111
330P_0402_50V7K

2

<8> VGA_LVDS_SCL
<8> VGA_LVDS_SDA

C1112
100P_0402_50V8J

VGA_LVDS_A0#
VGA_LVDS_A0
VGA_LVDS_A1#
VGA_LVDS_A1
VGA_LVDS_A2#
VGA_LVDS_A2
VGA_LVDS_ACLK#
VGA_LVDS_ACLK
VGA_LVDS_SCL
VGA_LVDS_SDA

2
1
RP11
2
1
RP12
2
1
RP13
2
1
RP14
R1514 1 DIS@
R1515 1 DIS@

LVDS_A0#
3
LVDS_A0
4
DIS@ 0_0404_4P2R_5%
LVDS_A1#
3
LVDS_A1
4
DIS@ 0_0404_4P2R_5%
LVDS_A2#
3
LVDS_A2
4
DIS@ 0_0404_4P2R_5%
LVDS_ACLK#
3
LVDS_ACLK
4
DIS@ 0_0404_4P2R_5%
LVDS_SCL
2
LVDS_SDA
2 0_0402_5%
0_0402_5%

091202 swap A0/A0#,A1/A1#,A2/A2#,ACLK/ACLK#
nets on RP11/RP12/RP13/RP14

LED PANEL Conn.
A

<31>

BKOFF#

R1464 1

2 0_0402_5%

R1465 1

2 10K_0402_5%

DISPOFF#
A

2009/10/09

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

LVDS /INVERTER
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

Wednesday, March 03, 2010

Sheet
1

14

of

46

A

B

C

D

E

1

L14
L12
CRT_B

1

2

C303

1

2

2

3

BK1608121YZF
2

1

RED

BK1608121YZF
2

GREEN

BK1608121YZF
2

BLUE

10P_0402_50V8J

2

C308

10P_0402_50V8J

1

C310

10P_0402_50V8J

1
2

2

R250

150_0402_1%

1

150_0402_1%

1

R253

2

R255

150_0402_1%

1

PJDLC05C_SOT23-3

1
CRT_G

D17

C307

1

2

1

C306

2

C304

1

2

10P_0402_50V8J

1

10P_0402_50V8J

L15
CRT_R

10P_0402_50V8J

1

1

0615

P/N from SM01000AL00 to SM010032020

D18
PJDLC05C_SOT23-3

Modify C31- C308 C303 C307 C306 C304 BOM Structure
0120 Change L12,L14,L15

3

CRT PORT

2

Close to CRT CONN for ESD.

+5VS

CRT_HSYNC_1

Y

3

1
R1512

CRT_HSYNC_2
2
39_0402_1%

1

JVGA_HS

L45
JVGA_VS

1
2
BK1608LL121-T_2P

SN74AHCT1G125DCKR_SC70-5

1

+5VS
2
0.1U_0402_16V4Z

1
OE#

1
C298

C1304
10P_0402_50V8J
5

Place closed to chipset

P

2

CRT_VSYNC

A
3

C1305
10P_0402_50V8J

2

2

R149
10K_0402_5%

U10
Y

CRT_VSYNC_1

4

G

2

2

+3VS

1

2

4

G

A

L44
1
2
BK1608LL121-T_2P

U11

1
R1513

High: CRT Plugged

CRT_VSYNC_2
2
39_0402_1%

091013 Add R/L/C folloew NTV00

<19>

CRT_DET

CRT_DET

SN74AHCT1G125DCKR_SC70-5
CRT_DET#

OPTIMUS

DIS ONLY
CRT_R

2
0_0402_5%

GMCH_CRT_G

<5> GMCH_CRT_G

R1502 1 OPT@

CRT_G

2
0_0402_5%

<5> GMCH_CRT_B
<5> GMCH_CRT_HSYNC

<8> VGA_CRT_G

R1503 1 OPT@

2

<8> VGA_CRT_B

GMCH_CRT_HSYNC

R1504 1 OPT@

2

<8> VGA_HSYNC

R1505 1 OPT@

CRT_B
0_0402_5%
CRT_HSYNC
0_0402_5%
CRT_VSYNC
2
0_0402_5%

<8> VGA_CRT_R

GMCH_CRT_B

GMCH_CRT_VSYNC

<5> GMCH_CRT_VSYNC

3

R1501 1 OPT@

<8> VGA_VSYNC

VGA_CRT_R

R1517 1 DIS@

+CRT_VCC_1

CRT_R

2
0_0402_5%

VGA_CRT_G

R1518 1 DIS@

D3
CRT_G

2

2

W=40mils
1

+CRT_VCC
F4

1

C142 0.1U_0402_16V4Z
1
2

2

VGA_CRT_B

R1519 1 DIS@

2

VGA_HSYNC

R1520 1 DIS@

2

VGA_VSYNC

R1521 1 DIS@

CRT_B
0_0402_5%
CRT_HSYNC
0_0402_5%
CRT_VSYNC
2
0_0402_5%

RB491D_SC59-3

1.1A_6V_SMD1812P110TF

CRT_DAT
GREEN

+3VSDGPU

3
Q67B

CRT_DAT

<8> VGA_DDCDATA

4

OPT@

2N7002DW-T/R7_SOT363-6
CRT_CLK
6

1

VGA_DDCDATA
2

2
GMCH_CRT_CLK

<5> GMCH_CRT_CLK

5

5

JVGA_VS

4

<8> VGA_DDCCLK

VGA_DDCCLK

1

OPT@
Q67A
2N7002DW-T/R7_SOT363-6

3
Q72B

CRT_DAT

1
R1103

+CRT_VCC

JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

RED

JVGA_HS
BLUE

GMCH_CRT_DATA

Q11
2N7002W-T/R7_SOT323-3

0_0402_5%

+3VS

<5> GMCH_CRT_DATA

S

20100129 add F4 for +CRT_VCC
+5VS

GMCH_CRT_R

D

2
G

091202 move R249/R247 to CPU side

<5> GMCH_CRT_R

1

2

1

CRT_HSYNC

3

P

5

2
0.1U_0402_16V4Z

OE#

1
C301

CRT_CLK
CRT_DET#
2
100K_0402_5%

3

G
G

16
17

SUYIN_070546FR015M21TZR
CONN@

DIS@

2N7002DW-T/R7_SOT363-6
CRT_CLK
6

091117 Change JCRT1 Symbol to
SUYIN_070546FR015M21TZR

DIS@
Q72A
2N7002DW-T/R7_SOT363-6

100112 change Q72 P/N from SB00000AR00 to SB00000DH00

+3VS

l.c
om
ai

CRT_CLK

2
2.2K_0402_5%
2
2.2K_0402_5%

tm

2
4.7K_0402_5%
2
4.7K_0402_5%

1
R251
1
R252

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/10/09

Issued Date

ho

1 @
R1469
1 @
R1470

VGA_DDCCLK

CRT_DAT

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

f@

VGA_DDCDATA

+CRT_VCC

Title

CRT PORT

in

GMCH_CRT_CLK

Size Document Number
Custom
Date:

xa

4

1 OPT@ 2
R248
2.2K_0402_5%
1 OPT@ 2
R245
2.2K_0402_5%

Rev
1.0

NAVD0 LA-6091P

he

GMCH_CRT_DATA

Wednesday, March 03, 2010

E

Sheet

15

of

46

4

<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>

D

C669
C668
C667
C666
C715
C713
C730
C711

VGA_HDMI_CLK+
VGA_HDMI_CLKVGA_HDMI_TX0+
VGA_HDMI_TX0VGA_HDMI_TX1+
VGA_HDMI_TX1VGA_HDMI_TX2+
VGA_HDMI_TX2-

1
1
1
1
1
1
1
1

3

2
2
2
2
2
2
2
2

VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K

HDMI_CLK+_CK
HDMI_CLK-_CK
HDMI_TX0+_CK
HDMI_TX0-_CK
HDMI_TX1+_CK
HDMI_TX1-_CK
HDMI_TX2+_CK
HDMI_TX2-_CK

R660
R658
R664
R662
R668
R666
R672
R670

1
1
1
1
1
1
1
1

@
@
@
@
@
@
@
@

2

2
2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

HDMI_CLK+_CONN
HDMI_CLK-_CONN
HDMI_TX0+_CONN
HDMI_TX0-_CONN
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI_TX2+_CONN
HDMI_TX2-_CONN

1

HDMI_CLK+_CONN

1

R661
HDMI_CLK-_CONN
R659
HDMI_TX0+_CONN

1

R665
HDMI_TX0-_CONN

1

R663
HDMI_TX1+_CONN

1

R669
HDMI_TX1-_CONN

1

R667
HDMI_TX2+_CONN
L36
HDMI_CLK-_CK

1

HDMI_CLK+_CK

4

VGA@

1
4

1

R673

2

2

HDMI_CLK-_CONN

3

3

HDMI_CLK+_CONN

2
VGA@ 499_0402_1%
2
VGA@ 499_0402_1%
2
VGA@ 499_0402_1%
2
VGA@ 499_0402_1%
2
VGA@ 499_0402_1%
2
VGA@ 499_0402_1%
2
VGA@ 499_0402_1%
2
VGA@ 499_0402_1%

1

HDMI_TX2-_CONN

1

R671

20mil

D

S

NEAR CONNECT

2
+3VSDGPU
G
VGA@
Q41
2N7002W -T/R7_SOT323-3

091022 change Q41.2 PU from
+3VS to +3VSDGPU

W CM-2012-900T_4P
L37

D

HDMI_CONN

1

4

3

5

VGA@

HDMI_TX0-_CK

1

1

2

2

HDMI_TX0-_CONN

HDMI_TX0+_CK

4

4

3

3

HDMI_TX0+_CONN

W CM-2012-900T_4P
C

C

L38

VGA@

HDMI_TX1-_CK

1

1

2

2

HDMI_TX1-_CONN

HDMI_TX1+_CK

4

4

3

3

HDMI_TX1+_CONN

L25
1
1
L26

<9> VGA_HDMI_SDA
<9> VGA_HDMI_SCL

VGA@
VGA@

MBK1608121YZF_0603
2
2
MBK1608121YZF_0603

W CM-2012-900T_4P
L39

C670

VGA@

HDMI_TX2-_CK

1

1

2

2

HDMI_TX2-_CONN

HDMI_TX2+_CK

4

4

3

3

HDMI_TX2+_CONN

1

12P_0402_50V8J
VGA@ 2

W CM-2012-900T_4P

HDMIDAT_R
HDMICLK_R

1
C671
12P_0402_50V8J
2 VGA@

+5VS

+3VSDGPU

1

+5VS

HDMI_DETECT_VGA <8>

+5VS_HDMI

1 C743
0.1U_0402_16V4Z
VGA@

2
1

2
HDMI_DETECT

1

<31> HDMI_DETECT

091012 change HDMI CONN Symbol to
SUYIN_100042GR019S268ZR

VGA@
L35

JHDMI1

2

VGA@
C718
330P_0402_50V7K

R655
100K_0402_5%
VGA@

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HDMIDAT_R
HDMICLK_R

1

2

@
D45
RB751V_SOD323

R656
10K_0402_1%
1
2
1
VGA@
MBK1608121YZF_0603

B

2

R632
2.2K_0402_5%
VGA@

HDMI_DETECT_VGA
1 DIS@
2
R816
0_0402_5%

2

HDMI_DETECT

@
D46
BAT54S-7-F_SOT23-3

R631
2.2K_0402_5%
VGA@

1

1

B

HDMI_DETECT_VGA

3

NC7SZ08P5X_NL_SC70-5
OPT@

4

VGA@
D49
RB491D_SC59-3

@

G

Y
A

R657
0_0805_5%

2

1

5

HDMI_DETECT

P

U15
2 B

3

<9,31> DGPU_PW RGD

DGPU_PW RGD

2

091027 swap L36/L37/L38/L39 nets for layout

HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_TX0-_CONN
HDMI_TX0+_CONN
HDMI_TX1-_CONN
HDMI_TX1+_CONN
HDMI_TX2-_CONN
HDMI_TX2+_CONN

A

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
D0D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21

A

SUYIN_100042GR019S268ZR
CONN@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/10/09

Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HDMI CONN
Size
Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

W ednesday, March 03, 2010

Sheet
1

16

of

46

5

4

3

2

1

D

D

+3VS

CLK_PCI_PCH

8.2K_0402_5%

R233

8.2K_0402_5%

R235

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

R236
R229
R207
R231
R230
R237

1

<13> CLK_PCI_PCH

2
1

C

PAR
DEVSEL#
PCICLK
PCIRST#
IRDY#
PME#
SERR#
STOP#
PLOCK#
TRDY#
PERR#
FRAME#

A18
E16

GNT1#
GNT2#

G16
A20

REQ1#
REQ2#

GPIO22

G14
A2
C15
C9

GPIO48/STRAP1#
GPIO17/STRAP2#
GPIO22
GPIO1

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

B2
D7
B3
H10
E8
D6
H8
F8

PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

D11
K9
M13

STRAP0#
RSVD01
RSVD02

PCI_DEVSEL#
CLK_PCI_PCH
PCI_IRDY#

R336
33_0402_5%
@

C432
22P_0402_50V8J
@

2

For EMI

PCI_SERR#
PCI_STOP#
PCI_PLOCK#
PCI_TRDY#
PCI_PERR#
PCI_FRAME#

0111 Change BOM Structure of R336 and C432 from @ to mount
0301 Change BOM Structure of R336 and C432 from NOR_CLK@ to @
8.2K_0402_5%
8.2K_0402_5%

GPIO22
2 DIS@
1
R823
10K_0402_5%

R362
10K_0402_5%
@

091023 add R823 DIS@ 10K PD
for SW OPTIMUS usage

B

TGP

U72A

A5
B15
J12
A23
B7
C22
B11
F14
A8
A10
D10
A16

R232
R209

OPT@
10K_0402_5%
10K_0402_5%

R291
R292

R363
10K_0402_5%
@
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

R238
R205
R206
R208
R210
R211
R212
R204

8.2K_0402_5%
8.2K_0402_5%

R364
R365

PCI

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

B22
D18
C17
C18
B17
C19
B18
B19
D16
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1

C/BE0#
C/BE1#
C/BE2#
C/BE3#

H16
M15
C13
L16

C

1

R366
10K_0402_5%
@

B

TIGERPOINT_ES1_BGA360

091105 change TigerPoint Part Number to SA000039N90

Boot BIOS

0

1

SPI

1

0

PCI

1

1

LPC

A

ho

tm

ai

A

STRAP1#
GPIO48

l.c
om

STRAP2#
GPIO17

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Tigerpoint(1/4)
Size

Document Number

in

2010/10/09

Rev
1.0

xa

Deciphered Date

NAVD0 LA-6091P

Date:

he

2009/10/09

Issued Date

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification

W ednesday, March 03, 2010

Sheet
1

17

of

46

5

4

3

2

1

D

D

TGP

U72C

AB16
AE24
AE23
+3VS

1

AD16
AB11
AB10
AD23

Del

C

SATA1 04/30

AD11
AC11
AD25

CLK_PCIE_SATA# <13>
CLK_PCIE_SATA <13>
SATARBIAS
SATA_LED#

+3VS
R45

R154 24.9_0402_1%
SATA_LED#
SATA_LED# <21>

10K_0402_5%

RSVD24
RSVD25
RSVD26

R293

GATEA20

10K_0402_5%

RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
GPIO36

2

GPIO36

AD4
AC4

SATARBIAS#
SATARBIAS
SATALED#

HOST

R294
10K_0402_5%
GAT@

B

SATA_CLKN
SATA_CLKP

SATA_DTX_C_IRX_N0 <21>
SATA_DTX_C_IRX_P0 <21>
SATA_ITX_C_DRX_N0 <21>
SATA_ITX_C_DRX_P0 <21>

SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0

Placed within 500 mils of Tiger point chipset pin.

RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

2

AA14
V14

AE6
AD6
AC7
AD7
AE8
AD8
AD9
AC9

U16
Y20
Y21
Y18
AD21
AC25
AB24
Y22
T17
AC21
AA16
AA21
V18
AA20

R312

GATEA20 <31>
H_A20M# <5>

H_IGNNE#
H_INIT#
H_INTR
H_FERR#
H_NMI
KB_RST#
SERIRQ
H_SMI#
H_STPCLK#

10K_0402_5%
+VCCP

H_IGNNE# <5>
H_INIT# <5>
H_INTR <5>
H_FERR# <5>
H_NMI <5>
KB_RST# <31>
SERIRQ <31>
H_SMI# <5>
H_STPCLK# <5>

R164
56_0402_5%

56 ohm±5% pull-up resistor has
to be within 1" from the Tiger
Point chipset.

B

H_THERMTRIP# <5>

1

R296
10K_0402_5%
PAC@

A20GATE
A20M#
CPUSLP#
IGNNE#
INIT3_3V#
INIT#
INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
STPCLK#
THRMTRIP#

SERIRQ

GATEA20
H_A20M#

1

AC17
AB13
AC13
AB15
Y14

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

2

C

RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
RSVD08
RSVD09
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18

SATA

R12
AE20
AD17
AC15
AD18
Y12
AA10
AA12
Y10
AD15
W10
V12
AE21
AE18
AD19
U12

ESD request
3

H_INTR

@
1
@
1
@
C451
1
@
C452
1
@
C453
1

H_FERR#

C454

H_THERMTRIP# C458

TIGERPOINT_ES1_BGA360

H_A20M#

091203 add R296 10K PD for customer recognize

091105 change TigerPoint Part Number to SA000039N90

H_IGNNE#
H_INIT#

+VCCP

R198
56_0402_5%

H_NMI
H_SMI#

H_FERR#

H_STPCLK#

Close to TigerPoint
pin

A

C450

1
@
C455
1
@
C456
1
@
C457
1

2 100P_0402_50V8J
2 100P_0402_50V8J
2 100P_0402_50V8J
2 100P_0402_50V8J
2 100P_0402_50V8J
2 470P_0402_50V8J
2 100P_0402_50V8J
2 100P_0402_50V8J
2 100P_0402_50V8J

091216 change value of C454 to 470P

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/10/09

Issued Date

A

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Tigerpoint(2/4)
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

Wednesday, March 03, 2010

Sheet
1

18

of

46

5

4

3

2

PCIE
@
SW2
EVQPLHA15_4P
1
3

091212 Add C30 near PCH
to prevent switch noise
2 @ 100P_0402_50V8J

1

USB Port List
0
1
2
3
4
5
6
7

LAN
WLAN
WWAN

4

3
4

6
5

HDA_SDIN0 C30

2

Port List

1
2

RTCRST#

1

R225
USB20_N1_R 2 @
USB20_P1_R 2 @
R226

0_0402_5%
1 USB20_N1
1 USB20_P1
0_0402_5%

USB20_N1 <24>
USB20_P1 <24>

D

20100120 change SW2 from mount to @

SPI_MISO
SPI_MOSI
SPI_CS#
SPI_CLK
SPI_ARB

AB17
V16
AC18
E21
H23
G22
D22
G18
G23
C25
T8
U10
AC3
AD3
J16

EC_THERM#
VGATE
MCH_SYNC#
PBTN_OUT#
ICH_RI#

SLP_S3#
SLP_S4#
SLP_S5#
BATLOW#
DPRSTP#
DPSLP#
RSVD31

+3VALW

R145

10K_0402_5% 2
8.2K_0402_5%

R39

2 ICH_PCIE_WAKE#
1 SYS_RST#

10K_0402_5% 2

R36

8.2K_0402_5%

R314

GPIO12

8.2K_0402_5%

R315

GPIO14

R316

GPIO15

R301

SMBALERT#

8.2K_0402_5%

EC_LID_OUT#

A

RTCRST#

2 R1184 @1 0_0402_5%

HDA_BITCLK_AUDIO

1
C1214

@

2

1

JUMP_43X39

5

1

Routing the trace at least 10mil

R1380
8.2K_0402_5%

R372
0_0402_5%
2

1

Q30
3

<31> EC_RSMRST#

+RTCVCC

NON3G_LCD@
GPIO39

RTCX1

3

NC

OSC

1

NC

OSC

4

C371
12P_0402_50V8J
1
2

1

1

R1379
8.2K_0402_5%

2

D28B
@
D28A
BAV99DW-7_SOT363

@

+CHGRTC

EC_RSMRST#R

@ MMBT3906_SOT23-3
1
2
+3VALW
R373
@ 4.7K_0402_5%

C1148

1

0.1U_0402_16V4Z

R375

2

@ 2.2K_0402_5%

Add +RTCVCC circuit 06/12
0112 Add R1379,R1380 10K_0402_5% for GPIO39

Issued Date

2009/10/09

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

RTCX2
4

R374
@ 2.2K_0402_5%

BAS40-04_SOT23-3

3G_LG@
2

10K_0402_5%

RSMRST circuit

+RTCBATT
2
1K_0402_5%

D37

0120 Change C368,C371 from 15p to 12p

1

Change J3 to R1184 4/29
20100129 Add J14 for RTCRST#

0118 Change C1158 from 220p to 100K ohm
0131 Change C1158 symbol
R1370

+3VS

2
22P_0402_50V8J

Del R203 (pull-up GPIO6 Resister) 06/08
C368
12P_0402_50V8J
1
2

R47

USB_OC#2
R49
10K_0402_5%
USB_OC#3_7
R48
10K_0402_5%
091020 change net name from
USB_OC#3/4/5/6/7 to USB_OC#3_7

BAV99DW-7_SOT363

32.768KHZ_12.5PF_Q13MC14610002

J14
2

<31,38>

For ESD

@ R222
0_0402_5%
100K_0402_5%

R1377
10K_0402_5%
E0@

091020 add R806 22ohm for 3G noise solution
0111 Change BOM Structure of R806 and C1214 from @ to mount
0111 Change R806 value from 22_0402_5% ohm to 0_0402_5%
2003 delete R806 for RF

Y3
C230
1U_0603_10V4Z~D
1
2

ACIN

1

B

1 R196
2
20K_0402_5%

GPIO38

2

+3VALW

E

1 R197
2 INTVRMEN
332K_0402_1%

MCH_SYNC#
GPIO7
EC_THERM#
GPIO0
PM_CLKRUN#

+3VALW

1

C

1M_0402_5%
1 R146 2 INTRUDER#

R42 1
R295
R368
R302
R241

2 R223

1

1

+RTCVCC

+RTCVCC

10K_0402_5% 2
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

ICH_RI#

R240

8.2K_0402_5%

+3VS

USB_OC#0

D25 RB751V_SOD323
2
1 ACIN

ACIN_C
R1376
10K_0402_5%
D0@

B

091113 change net name from
USB_OC#0_1 to USB_OC#0
add net name USB_OC#1

R1598
100K_0402_5%

ai

1K_0402_5% 1

PCH_POK <5,31>

tm

PM_BATT_LOW#

PLTRST#

ho

R239

For EMI, Close to TigerPoint

TIGERPOINT_ES1_BGA360

VGATE <5,13,31,42>

+3VS

EC_RSMRST#R

C434
@ 22P_0402_50V8J
2

DMI_CLKN
DMI_CLKP

2

f@

SMLINK1

W23
W24

Title

Tigerpoint(3/4)

in

SMLINK0

1

CLK_PCH_48M <13>

1

5

1

R43

T_PWROK

CLK_PCH_48M

F4

2

VGATE

USB_OC#2 <23>

USBRBIAS R152
22.6_0402_1%

DMI_ZCOMP
DMI_IRCOMP

2

R44

10K_0402_5% 2
8.2K_0402_5%

R37 1
R38 1

R153 24.9_0402_1%
DMI_COMP H24
1
2
J22

1 R311
2
0_0402_5%

TIGERPOINT_ES1_BGA360

10K_0402_5% 2
10K_0402_5% 2

0_0402_5%
R310 2
@

CLK48

1

LINKALERT#

1

1+RTCBATT_R

ICH_SMBDATA

1

T_PWROK

G2
G3

+1.5VS

<13> CLK_PCIE_PCH#
<13> CLK_PCIE_PCH

H_DPRSTP# <5>
H_DPSLP# <5>

USBRBIAS
USBRBIAS#

USB_OC#0 <23>

C

2 @ 100P_0402_50V8J

1

PM_SLP_S3# <31>
PM_SLP_S4# <31>
PM_SLP_S5# <31>
PM_BATT_LOW#
H_DPRSTP#
H_DPSLP#

USB_OC#0
USB_OC#3_7
USB_OC#2
USB_OC#3_7

<23>
<23>
<14>
<14>
<27>
<27>
<24>
<24>
<24>
<24>
<25>
<25>

R338
33_0402_5%
@

2

ICH_SMBCLK

2

R40

B25
AB23
AA18
F20

C50

3

2

R148

H20
E25
F21

D4
C5
D3
D2
E5
E6
C2
C3

09/10/08 Add PCIE to GPU

091212 Add C50 near PCH
to prevent switch noise

SB_SPKR <29>

2

R147

USB_OC#0

C1277
C1278

1

2.2K_0402_5% 1
2.2K_0402_5% 1
10K_0402_5% 2
10K_0402_5% 2

R288
10M_0402_5%
2
1

B

SYS_RST#
PLTRST#
ICH_PCIE_WAKE#
INTRUDER#
T_PWROK
EC_RSMRST#R
INTVRMEN
SB_SPKR

C52
C54

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31

USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

l.c
om

R2
T1
M8
P9
R4

AB22

THRM#
VRMPWRGD
MCH_SYNC#
PWRBTN#
RI#
SUS_STAT#/LPCPD#
SUSCLK
SYS_RESET#
PLTRST#
WAKE#
INTRUDER#
PWROK
RSMRST#
INTVRMEN
SPKR

SPI

Change EC_LID_OUT# From GPIO13 to GPIO11
06/08

SMBALERT#/GPIO11
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

CPUPWRGD/GPIO49

C53
C49

PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4

USB20_N0 <23>
USB20_P0 <23>

1

E20
H18
E23
H21
F25
F24

GPIO38
GPIO39

C565
C566

K21
K22
0.1U_0402_10V7K PCIE_ITX_C_DRX_N1_RJ23
0.1U_0402_10V7K PCIE_ITX_C_DRX_P1_RJ24
M18
M19
0.1U_0402_10V7KPCIE_ITX_C_DRX_N2_RK24
0.1U_0402_10V7K PCIE_ITX_C_DRX_P2_RK25
L23
L24
0.1U_0402_10V7K PCIE_ITX_C_DRX_N3_RL22
0.1U_0402_10V7K PCIE_ITX_C_DRX_P3_RM21
P17
VGA@
P18
0.1U_0402_10V7K PCIE_CTX_C_GRX_N0 N25
0.1U_0402_10V7K PCIE_CTX_C_GRX_P0 N24
VGA@

USB20_N0
USB20_P0
USB20_N1_R
USB20_P1_R
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

2

SMBALERT#
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
SMLINK0
SMLINK1

RTCX1
RTCX2
RTCRST#

<26> PCIE_DTX_C_IRX_N1
<26> PCIE_DTX_C_IRX_P1
<26> PCIE_ITX_C_DRX_N1
<26> PCIE_ITX_C_DRX_P1
<25> PCIE_DTX_C_IRX_N2
<25> PCIE_DTX_C_IRX_P2
H_PWRGD <5>
<25> PCIE_ITX_C_DRX_N2
<25> PCIE_ITX_C_DRX_P2
EC_THERM# <31> <24> PCIE_DTX_C_IRX_N3
<24> PCIE_DTX_C_IRX_P3
<24> PCIE_ITX_C_DRX_N3
PBTN_OUT# <31> <24> PCIE_ITX_C_DRX_P3
<8> PCIE_CRX_GTX_N0
<8> PCIE_CRX_GTX_P0
<8> PCIE_CTX_GRX_N0
<8> PCIE_CTX_GRX_P0
PLTRST# <5,8,24,25,26,31>
ICH_PCIE_WAKE# <24,25>

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

PCI-E

W4
V5
T5

SMB

<13> ICH_SMBCLK
<13> ICH_SMBDATA

RTCX1
RTCX2
RTCRST#

PM_CLKRUN#

H_PWRGD

MISC

C433
22P_0402_50V8J

@

2
For EMI, Close to TigerPoint

LAN_CLK
LANR_RSTSYNC
LAN_RST#
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2

RTC

1

LAN

T4
P7
B23
AA2
AD1
AC2
W3
T7
U4

1 R367
2
1K_0402_5%

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

Size Document Number
Custom
Date:

xa

EPROM

DMI_TX#0
DMI_TX0
DMI_RX#0
DMI_RX0
DMI_TX#1
DMI_TX1
DMI_RX#1
DMI_RX1

USB

EE_CS
EE_DIN
EE_DOUT
EE_SHCLK

2

C

U3
AE2
T6
V3

R337
33_0402_5%

@

HDA_BIT_CLK
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDOUT
HDA_SYNC
CLK14

<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>

GPIO0
CRT_DET
CRT_DET <15>
GPIO7
EC_SMI#
EC_SMI# <31>
EC_SCI#
EC_SCI#
<31>
ACIN_C
GPIO12
EC_LID_OUT#
EC_LID_OUT# <31>
GPIO14
GPIO15
2 R17
1 0_0402_5%
PM_DPRSLPVR <5>
H_STP_PCI# <13>
H_STP_CPU# <13>

1

1

HDA_BITCLK P6
HDA_RST# U2
W2
V2
P8
HDA_SDOUTAA1
HDA_SYNC Y1
AA3

AUDIO

R159 2
R157 2

33_0402_5% 1
33_0402_5% 1

<28,30> HDA_SDOUT_AUDIO
<28,30> HDA_SYNC_AUDIO
<13> CLK_PCH_14M

2
2

T15
W16
W14
K18
H19
M17
A24
C23
P5
E24
AB20
Y16
AB19
R3
C24
D19
D20
F22
AC19
U14
AC1
AC23
AC24

2

R160
R158

33_0402_5% 1
33_0402_5% 1

BMBUSY#/GPIO0
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
DPRSLPVR
STP_PCI#
STP_CPU#
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
CLKRUN#
GPIO33
GPIO34
GPIO38
GPIO39

H7
H6
H3
H2
J2
J3
K6
K5
K1
K2
L2
L3
M6
M5
N1
N2

2

<31> LPC_FRAME#
<28,30> HDA_BITCLK_AUDIO
<28,30> HDA_RST_AUDIO#
<28> HDA_SDIN0

LDRQ1#/GPIO23
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
LFRAME#/FWH4

R23
R24
P21
P20
T21
T20
T24
T25
T19
T18
U23
U24
V21
V20
V24
V23

DMI

AA5
V6
AA6
Y5
W8
Y8
Y4

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC

<31>
<31>
<31>
<31>

091204 add USB20_N1/P1 for
SIM CARD Conn.

TGP

U72B
TGP

U72D

091212 Add C17 C18 near U72
to prevent switch noise

D

091105 change TigerPoint Part Number to SA000039N90

091105 change TigerPoint Part Number to SA000039N90

Rev
1.0

NAVD0 LA-6091P

he

100P_0402_50V8J

1 2

100P_0402_50V8J

2

2

2

1

USB Right2
CMOS
CardReader
WWAN
BT
WIMAX

6

1

C18

4

C17

ICH_SMBDATA

3

ICH_SMBCLK

USB Left1

Wednesday, March 03, 2010

Sheet
1

19

of

46

5

4

3

2

1

091105 change TigerPoint Part Number to SA000039N90
TGP
U72E
D

D

VCC5REF

F12

+V5REF_RUN

6mA

F5

+V5REF_SUS

10mA

Y6

+SATAPLL

50mA

091105 change TigerPoint Part Number to SA000039N90
U72F

+5VS

VCC5REF_SUS

+3VS

AA8
M9
M20
N22

1.3A

VCC1_05_1
VCC1_05_2
VCC1_05_3
VCC1_05_4

J10
K17
P15
V10

0.98A

H25
AD13
F10
G10
R10
T9

0.29A

F18
N4
K7
F1

0.13A

5

2

C61
C460

1

C461

2

1

2

10U_0603_6.3V6M 1U_0402_6.3V6K

2

1U_0402_6.3V6K

2

0.1U_0402_16V4Z

C45
C63
C38

1

1U_0402_6.3V6K

0.1U_0402_16V4Z

2

1U_0402_6.3V6K

C60

1

1

2

1

2

+1.5VS

+VCCP

1

2

+3VS

+3VALW
1

2

C463

1

2

1U_0402_6.3V6K

C48
C39

VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4

2

1

2

1

1

2

1U_0402_6.3V6K

2

1

C37

C40
0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2
VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6

C43

1

1

C44

C46

+V5REF_SUS

1

0.1U_0402_16V4Z

2

1

10_0402_5%

2

0.1U_0402_16V4Z

2
1

D10
RB751V-40_SOD323-2

1

0.1U_0402_16V4Z

POWER

+3VALW
+5VALW

2

0.1U_0402_16V4Z
2

1U_0402_6.3V6K

C41

1U_0402_6.3V6K
2

R35

1

10U_0603_6.3V6M

VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4

V_CPU_IO

C47

14mA

2

1 C59

1

+RTCVCC

0.01U_0402_16V7K

W18

1

+VCCP

C459

10mA

1U_0402_6.3V6K

F6

+V5REF_RUN

1U_0402_6.3V6K

VCCUSBPLL

C42

+DMIPLL

Y25

0.1U_0402_16V4Z

1

2

AE3

VCCDMIPLL

C62

VCCRTC

D12
RB751V-40_SOD323-2

C462

R33
100_0402_5%

C

VSS01
VSS02
VSS03
VSS04
VSS05
VSS06
VSS07
VSS08
VSS09
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56

2

1

VCCSATAPLL

TGP

TIGERPOINT_ES1_BGA360
B

A1
A25
B6
B10
B16
B20
B24
E18
F16
G4
G8
H1
H4
H5
K4
K8
K11
K19
K20
L4
M7
M11
N3
N12
N13
N14
N23
P11
P13
P19
R14
R22
T2
T22
V1
V7
V8
V19
V22
V25
W12
W22
Y2
Y24
AB4
AB6
AB7
AB8
AC8
AD2
AD10
AD20
AD24
AE1
AE10
AE25

C

B

Place closely pin Y25 within 100mlis.
+1.5VS

R30
1
2
0_0603_5%
C58
10U_0603_6.3V6M

0.01U_0402_16V7K
1
1
C28

VSS57
VSS58
VSS59

+DMIPLL
1

C464

2

2

RSVD32

G24
AE13
F2
AE16

2
4.7U_0603_6.3V6K
TIGERPOINT_ES1_BGA360

Place closely pin Y6 within 100mlis.
+1.5VS
R29
1
2
0_0603_5%
C57
10U_0603_6.3V6M

A

+SATAPLL
1

1

2

2

C27
0.1U_0402_16V4Z
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/09

Issued Date

Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Tigerpoint(4/4)
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P
Sheet

Wednesday, March 03, 2010
1

20

of

46

A

B

C

D

E

F

G

H

LED PCB CONN
JP18
1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

+3VALW
<31> PWR_LED#
<31> PWR_SUSP_LED#
<31> BATT_GRN_LED#
<31> BATT_AMB_LED#

MEDIA_LED#
NUM_LED#
CAPS_LED#
BT_LED#

<31> NUM_LED#
<31> CAPS_LED#
<31> BT_LED#
+3VS

WWAN_LED#
WLAN_LED#

<24,25> WWAN_LED#
<24,25> WLAN_LED#

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

GND
GND

17
18

09/30 add ESD

ACES_85201-1605N
CONN@
JP21
+3VS

2

2

C1398
47P_0402_50V8J

1

B

6
7

2

Y
A

3

<18> SATA_LED#

G1
G2

ACES_85201-0505N
CONN@

4

MEDIA_LED#

D32
ROW PJSOT05C 3P C/A SOT-23
1

SATA_LED#

1
2
3
4
5

P

U29
2

<27> CARD_LED#

G

2

1
2
3
4
5

5

2

1

3

C247
1U_0402_6.3V6K

+3VS

1

WWAN_LED#
WLAN_LED#
BT_LED#

NC7SZ08P5X_NL_SC70-5
@

R805 1

0108 Add C247,C1398 on pin1 of JP21 (RF)

2 0_0402_5%

SATA HDD Conn.
JSATA1
SATA_ITX_C_DRX_P0

<18> SATA_ITX_C_DRX_P0
3

SATA_ITX_C_DRX_N0

<18> SATA_ITX_C_DRX_N0

SATA_DTX_C_IRX_N0

<18> SATA_DTX_C_IRX_N0

SATA_DTX_C_IRX_P0

<18> SATA_DTX_C_IRX_P0

SATA_ITX_DRX_P0
0.01U_0402_16V7K
SATA_ITX_DRX_N0
C31
0.01U_0402_16V7K
C380
SATA_DTX_IRX_N0
1
2
0.01U_0402_16V7K
SATA_DTX_IRX_P0
1
2
0.01U_0402_16V7K
C383
C32

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

+5VS
+5VS

0.1U_0402_16V4Z
1

C423

2

1

2

1

1

C422
1U_0402_6.3V6K
2

2

C426

1
2
3
4
5
6
7

C419
10U_0603_6.3V6M

1000P_0402_50V7K

GND
A+
AGND
BB+
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12 GND1
V12 GND2
V12

3

23
24

SUYIN_127043FR022G263ZR_NR
CONN@

l.c
om

091116 change symbol of JSATA1 to
SUYIN_127043FR022G263ZR_NR

Compal Electronics, Inc.

A

B

C

D

E

F

LED/HDD/Function Board CONN.

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
B

xa

2010/10/09

Deciphered Date

Document Number

Rev
1.0

NAVD0 LA-6091P

Date:

he

2009/10/09

f@

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

4

Wednesday, March 03, 2010
G

Sheet

21
H

of

46

4

SW1
SW1
EVQPLHA15_4P
1
3

+3VALW

(BLUE)
1

ON/OFFBTN#

4
6
5

2

D0@

51 +-5% 0402
R1388

TOP Side
+3VALW

@
R186 2
1
0_0805_5%

2

2

2

D0@

LED1
HT-191NB5-DT BLUE 0603

@
R194 2
1
0_0805_5%

1

D2
ON/OFFBTN#

3

PWR_PWM_LED#

2

PWR_PWM_LED#

R1347
100K_0402_5%
D14

Bottom Side
ON/OFFBTN#

1

D0@

2

ON/OFF#

3

51ON#

1

1

ON/OFF# <31>
51ON#

<36>

DAN202U_SC70
1

PJSOT24C_SOT23-3
D0@

1

2 @ 100P_0402_50V8J

ON/OFFBTN#

C3

1

2 @ 100P_0402_50V8J

2

100P_0402_50V8J

C4

2

D1 @

1000P_0402_50V7K
1

091212 Add C19 near D14
to prevent switch noise
EC_ON

D

S

RLZ20A_LL34

Q1
2N7002W-T/R7_SOT323-3

2
G

2

<31> EC_ON

1

C2

1

3

PWR_PWM_LED#

C19

2

ON/OFFBTN#

R3

1

10K_0402_5%

LID Switch

PWR/B Conn
091019 Change +3VS to +3VALW

Del R103 05/12
+3VALW

VDD

2

+3VALW

C246
1U_0402_6.3V6K

1

2

2

C1397
47P_0402_50V8J

C155
0.1U_0402_16V4Z

1

OUTPUT

2

ACES_85201-0405N
CONN@

3

LID_SW# <31>
1

GND

1

1
2
3
4
G1
G2

1

<31> PWR_PWM_LED#

1
2
3
4
5
6

C150
U5

APX9132ATI-TRL SOT-23 3P

2

10P_0402_50V8J

JP23
ON/OFFBTN#
PWR_PWM_LED#

0108 Add C246,C1397 on pin1 of JP23

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/10/09

Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
B
Date:

ON/OFF / PWR/B CONN./ LID SW
Document Number

Rev
1.0

NAVD0 LA-6091P
Wednesday, March 03, 2010

Sheet

22

of

46

A

B

C

D

E

5/5 Add U2 circuit
+5VALW

+USB_VCCC

+5VALW

W=80mils
+USB_VCCA
+USB_VCCA
U13
C1309
1U_0603_10V6K

1

2

1

2

C244
0.1U_0402_16V4Z
2
1

C1310
0.1U_0402_16V4Z

1
2
3
4

2

1

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

8
7
6
5

<31> USB_ON#
USB_OC#0 <19>

1

8
7
6
5

1

USB_OC#2 <19>

1
2

C819
@ 1000P_0402_50V7K

2

2

091014 add for RF Solution
USB_ON#

C51

1

2

100P_0402_50V8J

091212 Add C51 near U13
to prevent switch noise

USB CONN.1
+USB_VCCA

+USB_VCCC

W=40mils

+USB_VCCA
1
C315

1

+

W=40mils

2

USB CONN. 2

1

C316
C10

150U 6.3V M B LESR45M T520 H1.9
2

2

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

C245
@ 1000P_0402_50V7K

1

USB_ON#

<31> USB_ON#

C818
0.1U_0402_16V4Z

1
2
3
4

APL3510BKI-TRG SOP 8P PWR SWITCH

1

APL3510BKI-TRG SOP 8P PWR SWITCH

R224
100K_0402_5%

W=80mils

U8

+

1

C8

470P_0402_50V7K
150U 6.3V M B LESR45M T520 H1.9
2

2

470P_0402_50V7K

2

JUSB1

2

3

<19> USB20_N0
<19> USB20_P0

VCC
DD+
GND

5
6
7
8

GND1
GND2
GND3
GND4

JUSB2
USB20_N2_1
USB20_P2_1

SUYIN_020133GB004M25MZL
CONN@

D21

@
R1
0_0402_5%
1
2

<19> USB20_N2

1

<19> USB20_P2

4

VCC
DD+
GND

5
6
7
8

GND1
GND2
GND3
GND4
SUYIN_020133GB004M25MZL
CONN@

5/12 Revised net name

L5
3

1
2
3
4

091119 change JUSB1 to SUYIN_020133GB004M25MZL

1

PJDLC05C_SOT23-3

1
2
3
4

D4

1

2

4

3

2

USB20_N2_1

3

USB20_P2_1

USB20_N2_1

+USB_VCCC

WCM2012F2S-900T04_0805

6

5

4

1
2
R2
0_0402_5%
@

CH3

Vp

CH4

CH2

Vn

CH1

3

3

2

USB20_P2_1

1

CM1293-04SO_SOT23-6

l.c
om

@

A

B

C

D

USB PORT

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
B
Date:

xa

2010/10/09

Deciphered Date

Document Number

Rev
1.0

NAVD0 LA-6091P

he

2009/10/09

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

4

Wednesday, March 03, 2010

E

Sheet

23

of

46

4

A

B

C

D

E

Mini-Express Card for WWAN
091019 Remove C1163/C1164/C1165/C1166

Add C850 06/12

+3VS_WWAN

1
1

0.1U_0402_16V4Z
1
C507

1

C505

1

C506
2

0.1U_0402_16V4Z

2
10U_0805_10V4Z

091106 add R829 100K PD to GND
EC_TX_P80_DATA
EC_RX_P80_CLK

<31> EC_TX_P80_DATA
<31> EC_RX_P80_CLK

R402 0_0402_5%
1
2 EC_TX_P80_DATA_R
1
2 EC_TX_P80_CLK_R
R403
0_0402_5%

+3VALW

@

NON3G@
1
2
R504
0_1206_5%

2
0_1206_5%

150U_B_6.3VM_R40M

<19> PCIE_DTX_C_IRX_N3
<19> PCIE_DTX_C_IRX_P3
<19> PCIE_ITX_C_DRX_N3
<19> PCIE_ITX_C_DRX_P3

091212 Add C20, C21
near JMINI1
to prevent switch noise

GND1

C20

1

2 @ 100P_0402_50V8J

UIM_DATA

C21

1

2 @ 100P_0402_50V8J

+1.5VS

+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

+3VS
2

1

WXMIT_OFF#
R506 1

WXMIT_OFF# <31>
PLTRST# <5,8,19,25,26,31>

2 0_0402_5%
NON3G@

2

R507 0_0402_5%
1
2 NON3G@
1
2 NON3G@
R508 0_0402_5%
USB20_N5_1
USB20_P5_1

BT MODULE CONN

C411 BT@
0.1U_0402_16V4Z

+3VS_BT

R501
CLK_SMBCLK <7,13>
CLK_SMBDATA <7,13>

<31>

2

BT_ON#

+3VS

1

Q35
AO3413_SOT23-3

10K_0402_5%
BT@

3
1
R511

@

WWAN_LED# <21,25>
WLAN_LED# <21,25>

2
0_0402_5%

BT@

(9~16mA)

0.1U_0402_16V4Z

0104 Modify netname WWAN_LED_R# to WWAN_LED#, WLAN_LED_R# to WLAN_LED#

54

GND2

BT@
C502
2
1

1

+3VS_BT

53

UIM_VPP

G

EC_TX_P80_DATA_R
EC_TX_P80_CLK_R

091125 change 3G SKU power from +3VALW to +3VS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

D

10U_0805_10V4Z
1
2
C504
WWAN_WAKEUP_R#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2

<13> CLK_PCIE_WWAN#
<13> CLK_PCIE_WWAN

091106 change EC_TX_P80_DATA_R
from pin17 to pin49

C850
47P_0402_50V8J

Close to WWAN CONN

2

S

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

WWAN_CLKREQ#

+3VS_WWAN

2

+

C403

JMINI1

2

1

0.01U_0402_25V7K

1
+3VS_WWAN

+3VS

ICH_PCIE_WAKE#

<13> WWAN_CLKREQ#

2

1
C508

+3VS_WWAN

R829
100K_0402_5%
3G@
1
R405

<19,25> ICH_PCIE_WAKE#

2

JBT1
ACES_88910-5204
CONN@

091012 Change Mini PCIE CONN
Symbol to ACES 88910-5204 follow
ME CONN LISTRev08

2
0_0402_5%

1
R826
@

3

D15
@ CM1293-04SO_SOT23-6
1 CH1
CH4 4

UIM_VPP

USB20_N5_1

<19> USB20_P6
<19> USB20_N6

1
2
3
4

USB20_P6
USB20_N6

1
2
3 GND
4 GND

5
6

ACES 88266-04001
CONN@

L4

2

2

1

1

USB20_N5

3

3

4

4

USB20_P5

3

USB20_N5 <19>

UIM_DATA
USB20_P5_1

USB20_P5 <19>

WCM2012F2S-900T04_0805
2

Vn

Vp

5

+UIM_PWR

6

UIM_CLK

2
0_0402_5%
UIM_RST

3

CH2

CH3

1
R827

091102 add L4/R826/R827 on USB port5
follow RF team review

+UIM_PWR
TAITW_PMPAT2-08GLBS7N14N0

Reserve for SIM card does not meet rise time
and pull-up is needed.

CONN@

@

2

2

2

2

R509
10K_0402_5%

1

2

2

C1116

1
2

1

3G@
1
R510

<31> WWAN_WAKEUP#

WWAN_WAKEUP_R#
2
0_0402_5%
4

2009/10/09

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

091204 add USB20_P1/N1 for SIM Card Conn.

A

@

1
C512

Add C1114 C1116 C1117 C1118 05/11
Change C512 to 1U_0402 05/14

USB20_P1
USB20_N1

<19> USB20_P1
<19> USB20_N1

2

1

C1114
56P_0402_50V8

10
11

1

C513
0.1U_0402_16V4Z

GND
GND

@

1

22P_0402_50V8J

1

22P_0402_50V8J
C511

D+
D-

C510

8
9

56P_0402_50V8

Modifiy 05/11

R12
10K_0402_5%
2
1

C509

2

@

USB20_P1
USB20_N1

+UIM_PWR
UIM_RST
UIM_CLK

1U_0402_6.3V6K

4

2

1

22P_0402_50V8J

C1118
56P_0402_50V8

1

+3VALW
1
2
3

C1117
56P_0402_50V8

UIM_VPP
UIM_DATA

091204 change SIM Card Conn. to
TAITW_PMPAT2-08GLBS7N14N0
JP3
4 GND
VCC
5 VPP
RST
6 I/O
CLK
7 DET

B

C

D

Title

Mini-Card/BT CONN
Size

Document Number

Rev
1.0

NAVD0 LA-6091P
Date:

Wednesday, March 03, 2010

Sheet
E

24

of

46

5

4

3

2

1

D

D

Mini-Express Card for WLAN

+1.5VS
+3VS_WLAN

1
1

2

1
C1311
4.7U_0603_6.3V6K

2

1
C1312
0.1U_0402_16V4Z

2

1
C1313
47P_0402_50V8J

C240
1U_0402_6.3V6K

2

1
C1314
4.7U_0603_6.3V6K

2

1
C1315
0.1U_0402_16V4Z

2

1
C1316
47P_0402_50V8J

C238
1U_0402_6.3V6K

2

2

091127 reserve C240/C238 for RF team

C

C

0111 Change BOM Structure of C238/C240 from @ to mount

JMINI2
<19,24> ICH_PCIE_WAKE#
<13> WLAN_CLKREQ#
<13> CLK_PCIE_WLAN#
<13> CLK_PCIE_WLAN

<19> PCIE_DTX_C_IRX_N2
<19> PCIE_DTX_C_IRX_P2
<19> PCIE_ITX_C_DRX_N2
<19> PCIE_ITX_C_DRX_P2
+3VS_WLAN
B

1
C1317
10U_0603_6.3V6M

2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+3VS_WLAN

J12
JUMP_43X79
@
1 1
2 2

+3VS
+1.5VS

WL_OFF# <31>
PLTRST# <5,8,19,24,26,31>

USB20_N7 <19>
USB20_P7 <19>

@
1
R1536

2
0_0402_5%

WWAN_LED# <21,24>
WLAN_LED# <21,24>

B

(9~16mA)
0104 Modify netname WWAN_LED_R# to WWAN_LED#, WLAN_LED_R# to WLAN_LED#

54

ACES_88910-5204
CONN@

091116 Change JMINI2
Symbol to ACES 88910-5204 follow
ME CONN LIST 1116 Rev01

、 、 、 、

Update WLAN connector(the same as KAV60)
Revised 37 39 41 42 43 to NC
Update connector to DC040006S00
Update JMINI1 footprint
update pin 23,25,31,33

@
1
R723

WWAN_LED#
2
0_0402_5%

091125 reserve 0ohm for WIMAX

l.c
om

5/12
6/1
6/12
6/26
7/01

WLAN_LED#

5

4

3

2

WLAN
Size Document Number
Custom
Date:

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

xa

2010/10/09

Deciphered Date

Rev
1.0

NAVD0 LA-6091P

he

2009/10/09

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

A

Wednesday, March 03, 2010

1

Sheet

25

of

46

A

5

4

3

2

1

C1319 close to pin6
C1318 close to pin2
C1320 close to pin5
C1318 2

40mil

1013 pull up R1537 (Vendor)

C1319 1

R1537 2

CLK_PCIE_LAN

R1538 1

CLK_PCIE_LAN#

R1539 1

PCIE_DTX_C_IRX_P1

<19> PCIE_DTX_C_IRX_P1

2
C1324
2
C1325

PCIE_DTX_C_IRX_N1

<19> PCIE_DTX_C_IRX_N1

1

1

2

1

47
48

LAN_ACTIVITY
LAN_SK_LAN_LINK#
LAN_CLKREQ#

2
R1541

2

27

3
4

PERSTn
WAKEn

7

SEL_25 MHz

TRXP0
TRXN0
TRXP1
TRXN1

13
14
17
18

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-

AVDD_ REG
AVDDL

11
42

+AVDDVCO1
+AVDDVCO2

REFCLKN

43

RX_P

Atheros

RX_N

38

TX_P

PCIE_C_RXN1

37

TX_N

9
10

XTLO
XTLI

31
33

SMCLK
SMDATA

1

12
34

C1329
27P_0402_50V8J

49

091116 change P/N of Y7 to
SJ100003300

1
LAN_CLKREQ#

DVDDL
DVDDL
DVDD_REG
DVDD_REG

28
32
45
46

+1.2_DVDDL

VDD11_ REG
AVDDL
AVDDL
AVDDL
AVDDL

8
16
22
36
39

+1.2_AVDDL

VDDHO
AVDDH
AVDDH

15
19
25

+2.5V_VDDH

NC
NC
NC
NC
NC
NC

20
21
23
24
26
35

AR8132 10/100 LAN

44
PCIE_C_RXP1

C

10U_0603_6.3V6M

CLKREQn

REFCLKP

LANRBIAS_R
1
2.37K_0402_1%

+3V_LAN

VDD25V

R1541 keep away other singal (25mil)

25MHZ_20PF_7A25000012

C1327
27P_0402_50V8J

LED_ACTn
LED_10_100n

VDD17

40

LAN_X1
LAN_X2

29
30

5

0.1U_0402_16V7K

、C1325 close to U1

TWSI_CLK
TWSI_DATA

6

41

LAN_X2

2

VDD3V

CLK_PCIE_LAN#_R

Y7
LAN_X1

2

0.1U_0402_16V7K

1

C1324

+3V_LAN

LX

CLK_PCIE_LAN_R

PCIE_ITX_C_DRX_N1

<19> PCIE_ITX_C_DRX_N1

0_0805_5%

0_0402_5%
2
0_0402_5%
2

PCIE_ITX_C_DRX_P1

<19> PCIE_ITX_C_DRX_P1

1

1 0.1U_0402_16V4Z

1 4.7K_0402_5%

<13> CLK_PCIE_LAN#

R1540

C1320 2

PLTRST#
LAN_WAKE#

<13> CLK_PCIE_LAN

+3VALW

+AVDD_CEN
+2.5V_VDDH

<5,8,19,24,25,31> PLTRST#
<31> LAN_WAKE#
+3V_LAN

2 0.1U_0402_16V4Z

C1321,C1322,C1323 close to pin2 (<400mil)

U88

60mil
+1.8_VDD_LX

+3V_LAN

1013 Add R1538,R1539 for reserve 0.1u cap (Vendor)
D

1 1U_0402_6.3V4Z

RBIAS
TESTMODE
GND

<13>

C1321
0.1U_0402_16V4Z

20mil

1

1

2

2

C1322

2

C1326 close to pin11

D

+AVDDVCO1

C1326
0.1U_0402_16V4Z

20mil

C1323
10U_0603_6.3V6M

1

2

20mil
+1.2_AVDDL

1

+AVDDVCO2

2
1

R1542
0_0603_5%

2

C1328
0.1U_0402_16V4Z
C

AR8132-AL1E_QFN48_6X6

close to pin42
+1.8_VDD_LX
2
4.7UH_1008HC-472EJFS-A_5%_1008

1
L46

30mil

C1334,C1335 close to pin8

+AVDD_CEN

C1330
10U_0603_6.3V6M

1

1

2

2

C1331
0.1U_0402_16V4Z

RJ45 CONN

@
1
100P_0402_50V8J

+1.2_AVDDL

L46 close to pin1 (<200mil)
C1330 C1331 close to L1 (<200mil)

、

JRJ1
LAN_ACTIVITY

2
R1544

Place Close to Chip
B

2
2
2
2

2
R1543

1
511_0402_1%

1
5.1K_0402_5%

20mil

RJ45_MIDI1-

LAN_MDI1

1
C1339
0.1U_0402_16V4Z

For EMI.

1

2

2

C1340
0.1U_0402_16V4Z

2
1
C1341
470P_0402_50V7K
@

the GND directly connect to GND layer
+3V_LAN

Yellow LED+

12

Yellow LEDSHLD1

15

DETECT PIN1

13

1
C1335

2

2

1U_0402_6.3V4Z

PR4+

6

PR2-

5

PR3-

4

PR3+

C1343 close to pin28

3

PR2+

C1344 close to pin32

2

PR1-

C1345 close to pin45

RJ45_MIDI0+

1

PR1+

C1342 close to pin46

9

Green LED+

10

C1337

1
C1338

2

C1333

2

2

0.1U_0402_16V4Z

B

RJ45_MIDI0-

LAN_SK_LAN_LINK#

1

0.1U_0402_16V4Z

7

0.1U_0402_16V4Z

1
C1336

RJ45_MIDI1+

1 R1549
511_0402_1%

2

2

PR4-

0.1U_0402_16V4Z

1
C1334

11

8

LAN_MDI0

49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%

0.1U_0402_16V4Z

1

the GND directly connect to GND layer

R1545 1
R1546 1
R1547 1
R1548 1

Add C22 close to pin39 (Vendor)

C1337,C1338 close to pin22 .36

close to JRJ1
2
C1332

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-

1013

C1336 close to pin16

SHLD1

14

+1.2_DVDDL

C1342
1U_0402_6.3V4Z

0.1U_0402_16V4Z

1

1

2

2

0.1U_0402_16V4Z

1
C1343

1
C1344

C1345

2

2

0.1U_0402_16V4Z

Green LEDSANTA_130452-3

2
C1346

1
100P_0402_50V8J

+AVDD_CEN

C1350 close to pin15
RJ45_GND

C1347

2

1

2

C1351 close to pin19
C1352 close to pin25

1

2

C1349
0.1U_0402_16V4Z

+2.5V_VDDH

1

T80
LAN_MDI1+
LAN_MDI1+AVDD_CEN_R

A

1

1
C1354

2

RJ45_GNDA

2

C1348
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1000P_1206_2KV7K
R1550
0_0603_5%

C1353
1U_0402_6.3V4Z

40mil

CONN@

@

1013 Add R1550,C1353 for EMI (Vendor)

2

2

LAN_MDI0+
LAN_MDI0C1355

1
2
3
4
5
6
7
8

RD+
RDCT
NC
NC
CT
TD+
TD-

RX+
RXCT
NC
NC
CT
TX+
TX-

16
15
14
13
12
11
10
9

1

RJ45_MIDI1+
RJ45_MIDI1RJ45_CT0

1
R1551

2
75_0402_5%

1013 Add C1348,C1349 for ESD (Vendor)
2

1
C1350
1U_0402_6.3V4Z

2

1
C1351
0.1U_0402_16V4Z

2

C1352
0.1U_0402_16V4Z
A

RJ45_CT1
RJ45_MIDI0+
RJ45_MIDI0-

1
R1552

RJ45_GND
2
75_0402_5%

350uH_NS0013LF

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

0.1U_0402_16V4Z

2009/10/09

Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

LAN AR8132
Size
Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

Wednesday, March 03, 2010

Sheet

26

of

1

Compal Electronics, Inc.

46

5

4

1

+3VS

R808

3

2

1

2

0_0603_5%

U1 close to JREAD1

+VCC33

U78
1

+3VALW

R809

@
2

+3VS_READER

091020 change JUMP J2/J3 to R808/R809 0ohm

D

1

R1390
12K_0402_1%
1
2

1
C1179
10U 6.3V M X5R 0603 H0.8

2

28
29
30
31
33

+VCC_4IN1
+3VS_READER
+VCC33
+VCC18

0_0603_5%

C1180
0.1U_0402_25V4K
2 @

<19>
<19>

CrdVcc
SysVcc
Vcc33O
Vcc18O
Thermo Pad

14
13
REXT 12
8

USB20_P4
USB20_N4
XTLI

Clock from M/B
CARD_D0
CARD_D1
CARD_D2
CARD_D3
CARD_D4
CARD_D5
CARD_D6
CARD_D7

D+
DRref
EClkin

17
18
20
21
19
4
5
6

VddA
VccA

15
10

xDCeZ
xDCle
xDAle
xDBsyZ

7
23
24
22

SMCEZ_C
SMCLE
SMALE_CLK
SMBSYZ_SDCMD

3
25
32
26
27

PIN3
SMREZ_C
SMWPZ
SDCDZ
SMCDZ_MSINSZ

xDWeZ
xDReZ
xDWpZ
SdCdZ
xDCdZ

xDData0
xDData1
xDData2
xDData3
xDData4
xDData5
xDData6
xDData7

LedZ
ResetZ
VssA
GndA
NC

D

CARD_LED_R#

1
2

1

2

+VCC33

R1392
4.7K_0402_5%
@

16
11
9

XTLO

UB6250NF-A1-110_QFN32_5X5

If use external crystal(Y6),
U78 will change UB6252
+VCC_4IN1

1
C

1

2

1
C1182
10U 6.3V M X5R 0603 H0.8

2

20mils

1

@
C1183
0.1U_0402_25V4K

C

C1184
4.7U_0603_6.3V6K

2

+VCC33
+3VS

1

0_0402_5%
R1395
@

R1396
10K_0402_5%
@

G

2 2

1

2

@
C1181
10P 50V J NPO 0402

+VCC18

20mils

20mils

@
3

CARD_LED_R#

2

+VCC33

1
D

S

CARD_LED# <21>

Q53
2N7002W-T/R7_SOT323-3
2

1

1

@
C1185
0.01U_0402_16V7K

2

1
C1186
0.1U_0402_25V4K

2

C1187
4.7U_0603_6.3V6K

1

2

0_0402_5%
R1403
@
091203 change BOM structure of
Q53/R1395/R1396 from mount to @

ByPass Capacitors

Card Reader Connector
B

B

JREAD1
+VCC_4IN1

R1404 6250@
2
0_0402_5%

2
1
@
2

C1189
27P_0402_50V8J
6252@
Y6
12MHZ_16PF_7A12000026~D
6252@

C1191
22P_0402_50V8J
1

EMI

30
29
28
27
26
25
24
23

PIN3
SMWPZ
SMALE_CLK
SMCDZ_MSINSZ
SMBSYZ_SDCMD
SMREZ_C
SMCEZ_C
SMCLE

33
32
34
39
38
37
36
35

Only UB6252
need to use XTLI and XTLO

31
40

SD4-VDD
MS9-VCC

XD10-D0
XD11-D1
XD12-D2
XD13-D3
XD14-D4
XD15-D5
XD16-D6
XD17-D7

SD5-CLK
SD7-DAT0
SD8-DAT1
SD9-DAT2
SD1-DAT3
SD2-CMD
SD-CD
SD-WP

XD07-WE
XD08-WP
XD06-ALE
XD01-CD
XD02-R/B
XD03-RE
XD04-CE
XD05-CLE
XD GND
XD GND

091102 change Y6 to SJ100005900
41
42

XTLO

2

C1193
27P_0402_50V8J
6252@

SD CD/WP GND
SD CD/WP GND

11
18

+VCC_4IN1
SMALE_CLK
CARD_D0
CARD_D1
CARD_D2
CARD_D3
SMBSYZ_SDCMD
SDCDZ
PIN3

9
4
3
21
19
16
1
2

SD6-VSS
SD3-VSS

6
13

MS8-SCLK
MS4-DATA0
MS3-DATA1
MS5-DATA2
MS7-DATA3
MS6-INS
MS2-BS
MS1-VSS
MS10-VSS

17
10
8
12
15
14
7
5
20

SMALE_CLK
CARD_D0
CARD_D1
CARD_D2
CARD_D3
SMCDZ_MSINSZ
PIN3

C1188

@
C1190

4.7P_0402_50V8C

SMCDZ_MSINSZ
4.7P_0402_50V8C

1

2

C1192
0.1U_0402_25V4K

T-SOL_144-1300302600_NR
CONN@

5

4

3

2

CARD READER

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size Document Number
Custom
Date:

xa

2010/10/09

Deciphered Date

Rev
1.0

NAVD0 LA-6091P

he

2009/10/09

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

A

CARD_D0
CARD_D1
CARD_D2
CARD_D3
CARD_D4
CARD_D5
CARD_D6
CARD_D7

XD-VCC

l.c
om

R1405
33_0402_5%

@

2

2

1

1

XTLI

1

1

<13> CLK_48M_CR

22

Wednesday, March 03, 2010

1

Sheet

27

of

46

A

4

3

HDA_SDIN0_AUDIO

<30> MIC1_C_L
<30> MIC1_C_R
<30> AUDIO_GPIO0
<30> AUDIO_GPIO3
<30> SENSE_A
<30> SENSE_B
D

PVDD1_AUDIO

MIC1_C_L

SPKL-_R

MIC1_C_R

SPKR+_R

AUDIO_GPIO0
AUDIO_GPIO3

PVDD1_AUDIO <30>
SPKL-_R <30>

PVSS2
SENSE_A
SENSE_B

PVSS2

SPKR-_R

1
R1603 @
DMIC_DATA
1
R1604 @

SPKR-_R <30>

<30> EC_MUTE#_R

DMIC_CLK
DMIC_DATA

R1601 1
R1602 1

JP24
1
2
3
4

DMIC_CLK_R
DMIC_DATA_R

2 0_0402_5%
2 0_0402_5%

SPKL+_R <30>

DMIC_CLK

EAPD_R

<30> EAPD_R

+3VS

8mil

CODEC_VREF <30>

SPKL+_R

<30>

091130 add R1601/R1602 0ohm
Close to CODEC

271_VREFO <30>

CODEC_VREF

PVDD2_AUDIO <30>

<30>

271_AVSS2 <30>

271_VREFO

SPKR+_R <30>

PVDD2_AUDIO

HDA_SDIN0_AUDIO

271_AVSS2

1

2 DMIC_CLK_LVDS
0_0402_5%
2 DMIC_DATA_LVDS
0_0402_5%

1
2
3
4

G1
G2

5
6

ACES_88266-04001
CONN@

DMIC_CLK_LVDS <14>
DMIC_DATA_LVDS <14>

1

3

CD_GND

<30> CD_GND

2

2

5

D50
PJDLC05C_SOT23-3

EC_MUTE#_R
091130 reserve R1603/R1604 for LVDS Conn.
Close to CODEC

1

C1356

D

C1357
2

22P 50V J NPO 0402

22P 50V J NPO 0402

2

For ESD 12/22

J13
2

1

1

1

2

@ JUMP_43X39

+5VS

AUDIO_LDO_IN

L47 1
2
FBMA-L11-201209-221LMA30T_0805
1
C1358
0.1U_0402_16V4Z

2

40mil

2

1

2

U89
1

C1359
0.1U_0402_16V4Z

3

@
5

OUT

40mil

GND
SHDN

4

BYP

+VDDA
C1360
1

G9191-475T1U_SOT23-5

@

5/5 Add digital MIC
5/12 Revised circuit

PN:SCA00001100

(output = 300 mA)

IN

4.75V

+3VS_DVDD

2
+3VS_DVDD

2.2U_0603_6.3V6K
1

HD Audio Codec
2

1

1
C1361
0.1U_0402_16V4Z

2

L48
MBK1608121YZF_0603
2

+3VS

1
C1362
0.1U_0402_16V4Z

2

C1363
10U 6.3V M X5R 0603 H0.8

+AVDD_HDA

20mil

C33

1

2 @ 100P_0402_50V8J

HDA_SYNC_AUDIO

C34

1

2 @ 100P_0402_50V8J

36

16

MIC2_L

HP_OUT_L

39

PVDD1_AUDIO

MIC2_R

HP_OUT_R

41

SPKL-_R 1 271@

2 R1553

0_0402_5%

45

SPKR+_R 1 271@

2 R1554

0_0402_5%

46

PVDD2_AUDIO
2 R1556

1
R1555
0_0402_5%

CD_GND
1
19
20K_0402_1%
MIC1_L
MIC1_C_L 21
2
4.7U_0603_6.3V6K
MIC1_R
MIC1_C_R 22
2
4.7U_0603_6.3V6K
12
<29,30> MONO_IN
R1558
1
C1377
1
C1378

10P_0402_50V8J
2
1

11

<19,30> HDA_RST_AUDIO#

10

<19,30> HDA_SYNC_AUDIO

5

<19,30> HDA_SDOUT_AUDIO
R1564 2
R1566 2
R1567 2
2
1

1 39.2K +-1% 0402
1 20K_0402_1%
1 5.11K_0402_1%

C1383 271@
2.2U_0402_6.3VM

FBMA-11-100505-401T 0402
DMIC_DATA
AUDIO_GPIO0
R1563 1
2
DMIC_CLK
AUDIO_GPIO3
R1565 1
2
SENSE_A
271@ 0_0402_5%
SENSE_B

271@
272@
<31>

1
R1568
1
R1570
1
R1571

EAPD

<29,31> EC_MUTE#

EAPD_R
2
0_0402_5%
2 EC_MUTE#_R
0_0402_5% 271@
2
0_0402_5% 272@

9
35

18

7/04 Add C23 C1380 @

1

LINE_OUT_L
LINE_OUT_R

2

<29> HP_PLUG#
<29> MIC_PLUG#
<29> HP_PLUG#

+5VS

LINE1_L

NC

LINE1_R

DMIC_CLK

CD_L

NC

CD_R

NC

PVSS2

1 271@

SPKR-_R 1 271@

BIT_CLK

1

2

1
271@
C1370
10U 6.3V M X5R 0603 H0.8
2

271@
C1369
0.1U_0402_16V4Z

L51
271@
MBK1608121YZF_0603
1
2

PVDD2_AUDIO

20mil
44

2

271@
C1368
10U 6.3V M X5R 0603 H0.8

AMP_RIGHT <29,30>

R1559 1

CD_GND

C

SPKR+

<29>20mil

SPKR-

2 C1376

6

<29>20mil
1

DMIC_CLK
2 272@
FBMA-11-100505-401T 0402

R1557 0_0402_5%

2

2 22_0402_5% 1

SPKL-

2

1

271@
C1372
0.1U_0402_16V4Z

2

271@
C1373
10U 6.3V M X5R 0603 H0.8

1

2

+5VS

271@
C1374
0.1U_0402_16V4Z

1

2

271@
C1375
10U 6.3V M X5R 0603 H0.8

<29>

22P_0402_50V8J
HDA_BITCLK_AUDIO <19,30>

MIC1_L
MIC1_R

SDATA_IN

PCBEEP

MONO_OUT
LINE1_VREFO

RESET#
GPIO1
SYNC
MIC1_VREFO_L
SDATA_OUT
MIC1_VREFO_R

2
3
13
34

GPIO0
GPIO3
SENSE A
SENSE B

47

EAPD

48

SPDIFO

4
7

43

2

1

271@
C1366
0.1U_0402_16V4Z

AMP_LEFT <29,30>

NC

20

B

L49
271@
MBK1608121YZF_0603
2

271@
C1371
2.2U_0402_6.3VM

NC

271@

MIC1_R

1

15

24

MIC1_L

2

14

23

091212 Add C33, C34 near Codec
to prevent switch noise

DVDD

2

17

20mil <29>
20mil <29>

1

MIC2_VREFO

DVSS1
DVSS2

8

HDA_SDIN0_AUDIO

37

271_AVSS2

29

10mil

32
30

272@
271_VREFO

HP_RIGHT

1

C1381 1

10mil
20mil

2 10U 6.3V M X5R 0603 H0.8
271@
MIC1_VREFO

1
C1379

B

2 2.2U_0402_6.3VM

2
C1382
2.2U_0402_6.3VM
272@

HP_RIGHT <29,30>

10mil

MIC1_VREFO_R

VREF

27

CODEC_VREF

JDREF

40

SPKL+_R

NC

33

HP_LEFT

AVSS1
AVSS2

2
HDA_SDIN0 <19>
33_0402_5%
1
2
R1561
0_0402_5% 271@

MIC1_VREFO_L

31
28

1
R1560

20mil

1
HP_LEFT <29,30>

26
42

2
SPKL+
R1569
0_0402_5% 20mil
271@

<29>
1

1

HDA_RST_AUDIO#

2

U90

DVDD_IO

2

20mil

1
C1367
0.1U_0402_16V4Z

38

1
C1365
0.1U_0402_16V4Z

25

1
C1364
10U 6.3V M X5R 0603 H0.8

AVDD2

C

1

40mil

AVDD1

+VDDA

PVDD1_AUDIO

L50
MBK1608121YZF_0603
1
2

2

272@

1

@
C1385
10U 6.3V M X5R 0603 H0.8

2

C1384
0.1U_0402_16V4Z

ALC272-GR_LQFP48_9X9
20K_0402_1%

Impedance
39.2K

SENSE A

20K

DGND

Codec Signals

AGND

R1572

1
C447

2

Sense Pin

1
C448

PORT-A (PIN 39, 41)

Change to SA00002CI20

ALC272-VA2-GR

091127 reserve C447 0.1U for EMI request
20100125 change R1573 P/N from SD028000080 to SE102104K00 ,
value from 0_0402_5% to 0.1u_0402_10V7K
20100131 change R1573 symbol to C448

PORT-B (PIN 21, 22)

1
0_0402_5%
1
0_0402_5%
1
0_0603_5%


10K

PORT-C (PIN 23, 24)

5.1K

PORT-D (PIN 35, 36)

2
R1575

39.2K

PORT-E (PIN 14, 15)

20K

PORT-F (PIN 16, 17)

10K

PORT-G (PIN 43, 44)

GND

5

2009/10/09

Issued Date

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

A

GNDA

Compal Electronics, Inc.

Compal Secret Data

Security Classification

PORT-H (PIN 45, 46)

5.1K

2
0.1U_0402_10V7K

2
R1574
2
R1597

A

SENSE B

2
0.1U_0402_10V7K
@

2

Title

AUDIO CODEC ALC272
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

Wednesday, March 03, 2010

Sheet
1

28

of

46

5

4

3

2

1

091020 change JUMP J5 to R1576 0ohm

Int. Speaker Conn.

272@
2
+5VAMP_J
0_0603_5%

20mil
<28>
<28>
<28>
<28>

+5VAMP_J
272@
U81

2

GAIN1

3

VDD
NC
PVDD SHUTDOWN#
PVDD
LOUTGAIN0
ROUTGAIN1
LOUT+

272@
5
1
2
1 272@ 2 AMP_C_LEFT
C1388 0.47U_0603_10V7K R1581
0_0402_5%
272@ 1
2
1
2 AMP_C_RIGHT 17
C1389 0.47U_0603_10V7K R1582 272@ 0_0402_5%
272@ 1
2
9
C1390
0.47U_0603_10V7K
1
2
7
C1391
0.47U_0603_10V7K
272@

<28,30> AMP_LEFT
<28,30> AMP_RIGHT

LIN-

ROUT+

RIN-

GND
GND
GND
GND
GND
BYPASS

LIN+
RIN+

EC_MUTE#

8

SPKL-

14

SPKR-

4

SPKL+

18

SPKR+

1
11
13
20
21
10

2
C1392

1
2
3
4

G1
G2

D

5
6

ACES_88266-04001
CONN@

SPK_R+

SPK_L-

D51
PJDLC05C_SOT23-3

1
0.47U_0603_10V7K
272@

SPK_L+

D52
PJDLC05C_SOT23-3

Keep 10 mil width
1

091109 change U81 symbol to
APA2031RI-TRL_TSSOP20
P/N: SA00001RZ00

1
2
3
4

EC_MUTE# <28,31>

SPK_R-

APA2031RI-TRL_TSSOP20

JP25
SPK_L+
SPK_LSPK_R+
SPK_R-

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

3

272@

GAIN0

12
19

2
2
2
2

2

16
6
15

2

2
C1386
2
C1387

272@
1
10U 6.3V M X5R 0603 H0.8
1
0.1U_0402_16V4Z

R1577 1
R1578 1
R1579 1
R1580 1

SPKL+
SPKLSPKR+
SPKR-

1

D

3

1
R1576

+5VS

C

C

20081029 Update to 6dB

1

1

+5VAMP_J

<28,30> HP_RIGHT

@ R1587
100K_0402_5%
2

2

@ R1586
100K_0402_5%

HP_RIGHT

Headphone JACK

271@
1
2
R1583
56.2_0402_1%

HP_LEFT

<28,30> HP_LEFT

GAIN1

HP_RIGHT

<28,30> HP_RIGHT

272@
HPOUT_L_1 1
1
2
R1584 56.2_0402_1%
L52
HPOUT_R_1 1
1
2
R1585 56.2_0402_1%
L53

1

1

272@
R1590
100K_0402_5%
272@

<28,30> HP_LEFT

HP_LEFT

3

2
FBM-11-160808-700T_0603
2
FBM-11-160808-700T_0603

HPOUT_L_2

1

HPOUT_R_2

2
5

20mil

271@
1
2
R1588 56.2_0402_1%

1
C1393
330P_0402_50V7K

1

2

2

<28> HP_PLUG#

HP_PLUG#

6

C1394
330P_0402_50V7K

4 SHLD1

2

2

R1589
100K_0402_5%
272@

JHP1

20mil
GAIN0

SINGA_2SJ2285-112252

B

MIC1_VREFO

CONN@
091123 change symbol of JHP1 to
SINGA_2SJ2285-112252

2

2

MIC1_VREFO

B

1

272@
D54
RB751V-40TE17_SOD323-2
1

272@
D53
RB751V-40TE17_SOD323-2
271@

1
0_0402_5%
1

2
0_0402_5%

C812
MONO_IN_1

MONO_IN

R1593
4.7K_0402_5%

MONO_IN <28,30>

20mil
R1327

R1328
4.7K_0402_5%

MIC1_L

<28>

MIC1_R

C811
0.1U_0402_16V4Z

MIC2_L_1
2
1K_0603_1%
MIC2_R_1
2
1K_0603_1%

1
R1596
1
R1595

JMIC1
L55
FBM-11-160808-700T_0603
1
2

MIC2_L_2

1

MIC2_R_2

3

2
L54
FBM-11-160808-700T_0603

20mil

1

2

PCI Beep

<28>
1

1
2
47K_0402_5%

SB_SPKR

MIC JACK

R1594
4.7K_0402_5%
2

0.1U_0402_16V4Z

<19>

MIC1_VREFO_R

C1395
220P_0402_50V8J

091127 change value of R1328 from 10K to 4.7K

2

1

2

1
2
5
<28> MIC_PLUG#

MIC_PLUG#

6

C1396
220P_0402_50V8J

4 SHLD1

SINGA_2SJ2285-112252

091020 follow NTV00 Design

l.c
om

R1326
1
2
47K_0402_5%

BEEP#

271@
2
R1592

2

<31>

1
R1591

1

MIC1_VREFO_L

EC Beep

CONN@

A

5

4

3

2

AMP & Audio Jack

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size Document Number
Custom
Date:

xa

2010/10/09

Deciphered Date

Rev
1.0

NAVD0 LA-6091P

he

2009/10/09

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

091123 change symbol of JMIC1 to
SINGA_2SJ2285-112252

Wednesday, March 03, 2010

1

Sheet

29

of

46

A

5

4

3

2

1

D

D

HD Audio Codec
+3VS_DVDD

+AVDD_HDA
+3VS_DVDD

40mil

14
15
16

C

17
23
24
18
20
<28> CD_GND
<28> MIC1_C_L
<28> MIC1_C_R

CD_GND

19

MIC1_C_L

21

MIC1_C_R

22
12

<28,29> MONO_IN
<19,28> HDA_RST_AUDIO#

11

<19,28> HDA_SYNC_AUDIO

10
5

<19,28> HDA_SDOUT_AUDIO
<28> AUDIO_GPIO0
<28> AUDIO_GPIO3
<28>
<28>

SENSE_A
SENSE_B
<28> EAPD_R

B

AUDIO_GPIO0
AUDIO_GPIO3
SENSE_A
SENSE_B

2
3
13
34

EAPD_R

47
48

<28> EC_MUTE#_R

EC_MUTE#_R

4
7

DVDD

9

20mil

1

38

271@

AVDD2

AVDD1

U92

25

20mil

DVDD_IO

+AVDD_HDA

NC

LINE_OUT_L

NC

LINE_OUT_R

MIC2_L

HP_OUT_L

MIC2_R

HP_OUT_R

LINE1_L

NC

LINE1_R

DMIC_CLK

CD_L

NC

CD_R

NC

CD_GND
BIT_CLK

35

AMP_LEFT <28,29>

36

AMP_RIGHT <28,29>
PVDD1_AUDIO

39
41

SPKL-_R

45

SPKR+_R

46

PVDD2_AUDIO

PVDD1_AUDIO <28>

20mil

PVDD2_AUDIO <28>
PVSS2

SPKR-_R

44

20mil

SPKR+_R <28>

PVSS2

43

C

20mil

SPKL-_R <28>

<28>

SPKR-_R <28>

6

HDA_BITCLK_AUDIO <19,28>

MIC1_L
MIC1_R

SDATA_IN

PCBEEP

MONO_OUT
LINE1_VREFO

RESET#
GPIO1
SYNC
MIC1_VREFO_L
SDATA_OUT
MIC1_VREFO_R
GPIO0
GPIO3
SENSE A
SENSE B

MIC2_VREFO
VREF

EAPD

JDREF

SPDIFO
DVSS1
DVSS2

HDA_SDIN0_AUDIO

8
37

271_AVSS2

29

271_VREFO

HP_RIGHT

32

MIC1_VREFO_R

SPKL+_R

40

26
42

MIC1_VREFO
HP_RIGHT <28,29>

CODEC_VREF

27

AVSS1
AVSS2

20mil

10mil

30

33

MIC1_VREFO_L

10mil

28

<28>

271_VREFO <28>

10mil

31

NC

HDA_SDIN0_AUDIO
271_AVSS2 <28>

HP_LEFT

20mil

CODEC_VREF <28>
SPKL+_R <28>

B

HP_LEFT <28,29>

ALC271X-GR QFN 48P CODEC

DGND

Sense Pin

SENSE A

Impedance

AGND

Codec Signals

39.2K

PORT-A (PIN 39, 41)

20K

PORT-B (PIN 21, 22)

10K

PORT-C (PIN 23, 24)

5.1K

PORT-D (PIN 35, 36)

39.2K

PORT-E (PIN 14, 15)

20K

PORT-F (PIN 16, 17)

10K

PORT-G (PIN 43, 44)

5.1K

PORT-H (PIN 45, 46)

A

A

SENSE B

5

2009/10/09

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Title

AUDIO CODEC ALC271
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

Wednesday, March 03, 2010

Sheet
1

30

of

46

+3VALW

2

1

PLTRST#

<19>

2

EC_SCI#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

C1159
220P_0402_50V7K
KSO[0..15]

<32> KSO[0..15]

For ESD

<32>

KSI[0..7]

KSI[0..7]

<37>
<37>
<5,8,9>
<5,8,9>

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
77
78
79
80

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#

6
14
20100104 delete WLAN_LED_R# on pin 16
15
20100104 delete WWAN_LED_R# on pin 19
16
091015 add HDMI_DETECT on Pin16
VGA_DEEP_IDLE 17
091026 add VGA_DEEP_IDLE on Pin17
<8> VGA_DEEP_IDLE
DGPU_PWR_EN
18
<8,13,35> DGPU_PWR_EN
19
25
2
1
<5,14> INVT_PWM
FAN_SPEED1
R67
0_0402_5% 28
<4> FAN_SPEED1
HDMI_DETECT
29
<16> HDMI_DETECT
EC_TX_P80_DATA
30
<24> EC_TX_P80_DATA
EC_RX_P80_CLK
31
<24> EC_RX_P80_CLK
32
ON/OFF#
34
<22>
ON/OFF#
PWR_SUSP_LED#
36
<21> PWR_SUSP_LED#
NUM_LED#
<21> NUM_LED#
<19> PM_SLP_S3#
<19> PM_SLP_S5#
<19>
EC_SMI#

XCLKI
XCLKO

122
123

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

68
70
71
72

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

PS2 Interface

BATT_TEMP <37>
BATT_OVP
ADP_I
<38>

VCC
Ra

IREF
<38>
CALIBRATE# <38>
EC_MUTE# <28,29>
USB_ON# <23>

USB_ON#

BT_LED# <21>

TP_CLK
TP_DATA

97
98
99
109

TP_CLK <32>
TP_DATA <32>

DGPU_PWRGD

SPI Flash ROM

GPIO

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

2
R1293
FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#

119
120
126
128

C36

2

BATT_GRN_LED#
CAPS_LED#
BATT_AMB_LED#
PWR_LED#
SYSON

SUSP#

GPI

V18R

ENBKL

1 DIS@ 2
R1522
0_0402_5%
1 OPT@ 2
R1523
0_0402_5%

GMCH_ENBKL

C22

1

2

C23

R1472
10K_0402_5%

100P_0402_50V8J

1

2

091212 Add C22, C23, C24
to prevent switch noise

100P_0402_50V8J

C23 near PR199

C24 1
100P_0402_50V8J
2
Add 0 ohm R1309 06/08
0_0402_5% R1309
1
2
C24 near R800
EC_RSMRST# <19>
EC_LID_OUT#
EC_LID_OUT# <19>
EC_ON
RB751V-40TE17_SOD323-2
EC_ON
<22>
DGPU_HOLD_RST#
@
DGPU_HOLD_RST# <8>
ICH_POK_EC
PCH_POK
1
2
PCH_POK <5,19>
D29
BKOFF# <14>
R1295 2
1
1
2
+3VS
WL_OFF# <25>
R1296 10K_0402_5%
WXMIT_OFF# <24>
0_0402_5%
@
BT_ON# <24>

110
112
114
115
116
117
118
124

ENBKL

PM_SLP_S4# <19>

BT_LED# @ 1
C1177
TP_CLK
@
C816

2
470P_0402_50V7K
33P_0402_50V8K

EC_THERM#
SUSP#
PBTN_OUT#

EAPD
<28>
EC_THERM# <19>
SUSP#
<34,35,40,41,43>
PBTN_OUT# <19>
LAN_WAKE# <26>

EC_V18R

20mil 1

ECAGND

1 R320
1

C524
2

@
2

C1178

2

D30
PCH_POK

2

1

VGATE

<5,13,19,42>

RB751V-40TE17_SOD323-2
+3VALW
U75

+3VALW

100K_0402_5%

091102 reserve C816 33P on TP_CLK
follow RF team review

@

SPI_CS#

1
3
7
4

+3VALW

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

SPI_CLK_R
SPI_SI
SPI_SO

MX25L512AMC-12G_SO8
@
+3VALW

16M SPI ROM
C526

1

20mils

U76

2

+5VS
2
4.7K_0402_5%
2
4.7K_0402_5%

0V
0.289V
0.538V
0.875V
1.264V
1.759V
2.341V
3.3V

C22 near PR99

0.1U_0402_16V4Z

1
R1301
TP_DATA
X1
1
R1303
32.768KHZ_12.5PF_Q13MC14610002

Vab-Max

0V
0.250V
0.503V
0.819V
1.185V
1.650V
2.200V
3.3V

100P_0402_50V8J

WWAN_WAKEUP# <24>
VGAPWRGD <43>
FSTCHG <38>
BATT_GRN_LED# <21>
CAPS_LED# <21>
BATT_AMB_LED# <21>
PWR_LED# <21>
SYSON
<34,40>
VR_ON
<42>
ACIN
<19,38>

VGAPWRGD

C525
15P_0402_50V8J

TP_CLK

Vab-Typ

0V
0.216V
0.436V
0.712V
1.036V
1.453V
1.935V
2.500V

VGA_ENBKL

<8> VGA_ENBKL

1

Vab-Min

0
8.2K
18K
33K
56K
100K
200K
NC

<22>

<5> GMCH_ENBKL
VGAPWRGD

Rb

091212 Add C36
to prevent switch noise

73
74
89
90
91
92
93
95
121
127
100
101
102
103
104
105
106
107
108

LID_SW#

1
+3VALW
47K_0402_5%

R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)

Change BT_ON# from Pin98 to Pin108 06/24
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

XCLK1
XCLK0
GND
GND
GND
GND
GND

4

1
OSC

NAVE0

DGPU_PWRGD <9,16>

LID_SW#

SPI Device Interface

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

OSC
NC

NC
2

3

15P_0402_50V8J

0
1
2
3
4
5
6
7

NAVD0

20100115 change R1292 to 33K for Pre-MP phase

3.3V
100K

ID BRD ID
IREF

Rb

BOARD ID Table

0104 Delete WWAN_LED_R#, WLAN_LED_R#, WWAN_LED#, WLAN_LED#
C527

2

ACOFF <38>

091022 add DGPU_PWRGD on Pin98
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

R1292
33K +-5% 0402
D0@

PWR_PWM_LED# <22>
BEEP#
<29>
091022 add output pin FAN_PWM
FAN_PWM <4>

BRD_ID

83
84
85
86
87
88

2

0118 Change R1292 200K P/N from SD028200300 to SD028200380
Change R1292 18K P/N from SD028180200 to SD028180280

091022 add VGAPWRGD on Pin85, 20100104 delete WWAN_LED# on pin 85

SM Bus

KB926QFD3_LQFP128_14X14

1

67

9
22
33
96
111
125

AVCC
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

11
24
35
94
113

EC_SMB_CK1
2
2.2K_0402_5%
EC_SMB_DA1
2
2.2K_0402_5%
KSO1
2
47K_0402_5%
KSO2
2
47K_0402_5%

BATT_TEMP
BATT_OVP

AD Input

+3VALW
1
R1297
1
R1298
1
R1299
1
R1300

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

63
64
65
66
75
76

PWM Output

20100104 delete WLAN_LED# on pin 38
1

PWR_PWM_LED#
BEEP#
FAN_PWM
ACOFF

FSEL#SPICS# 2
R1302
SPI_CLK
2
R1304
FWR#SPI_SI 2
R1305

100112 delete JP26 for EC debug port

SPI_CS#
22_0402_5%
SPI_CLK_R
1
22_0402_5%
SPI_SI
1
22_0402_5%
1

8

VCC

3

W

7

HOLD

1

S

6
5

VSS

4

C
SPI_SO 2
2
D
Q
R1306
MX25L1605AM2C-12G_SO8-200mil

FRD#SPI_SO
22_0402_5%

1

l.c
om

C523
0.1U_0402_16V4Z

EC_RST#
EC_SCI#

BRD_ID

21
23
26
27

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

2 @ 100P_0402_50V8J

1

1

2
47K_0402_5%

12
13
37
20
38

C65

R1291
100K_0402_5%

2

1
R1290

+3VALW

<13> CLK_PCI_LPC
<5,8,19,24,25,26> PLTRST#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

VR_ON

U6

Ra

1

<18>
SERIRQ
<19> LPC_FRAME#
<19>
LPC_AD3
<19>
LPC_AD2
<19>
LPC_AD1
<19>
LPC_AD0

2

470P_0402_50V7K

GATEA20

KB_RST#

1
2
3
4
5
7
8
10

2

VCC
VCC
VCC
VCC
VCC
VCC

10K_0402_5%
R41 1
<18>

<18>

2

4.7U_0603_6.3V6K

2

+3VS

2

091212 Add C65
to prevent switch noise

AGND

05/14

2

+3VALW

1

69

Change to R_0402

2

2

1

C519
1000P_0402_50V7K

0.1U_0402_16V4Z
1 ECAGND
2
1
R1288
0_0402_5%

C518
1000P_0402_50V7K
@

1

C521
1000P_0402_50V7K

C520

+EC_AVCC

1

C517
0.1U_0402_16V4Z

1

C516
0.1U_0402_16V4Z

2

1

C515
0.1U_0402_16V4Z

1
2
MBK1608121YZF_0603

1

C514
0.1U_0402_16V4Z

+3VALW

Change R1292 to 0 ohm for BRD ID R01 (EVT) 091015

+EC_AVCC

L16

+3VS

ACIN

C531 1

2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J

091123 change SPI ROM to
SA00002TO00 (2MB)

C528
2

SPI_CLK_R
10P_0402_50V8J

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

1

2009/10/09

Deciphered Date

ai

C530 1

tm

C529 1

BATT_TEMP

ho

BATT_OVP

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

KB926/BIOS
Size Document Number
Custom
Date:

f@

EC_SMB_CK2
2.2K_0402_5%
EC_SMB_DA2
2.2K_0402_5%

in

2

Rev
1.0

xa

2

NAVD0 LA-6091P

Wednesday, March 03, 2010

he

1
R1307
1
R1308

Sheet

31

of

46

5

4

3

2

1

To TP/B Conn.
D

D

KSI[0..7]

KSI[0..7]

1
2
3
4
5
6

+5VS

KSI0

C136 1

2

100P_0402_50V8J

KSO4

C104 1

2

100P_0402_50V8J

KSI1

C135 1

2

100P_0402_50V8J

KSO5

C103 1

2

100P_0402_50V8J

KSI2

C134 1

2

100P_0402_50V8J

KSO6

C102 1

2

100P_0402_50V8J

KSI3

C133 1

2

100P_0402_50V8J

KSO7

C101 1

2

100P_0402_50V8J

KSI4

C132 1

2

100P_0402_50V8J

KSO8

C100 1

2

100P_0402_50V8J

KSI5

C131 1

2

100P_0402_50V8J

KSO9

C99

1

2

100P_0402_50V8J

KSI6

C127 1

2

100P_0402_50V8J

KSO10

C98

1

2

100P_0402_50V8J

KSI7

C126 1

2

100P_0402_50V8J

KSO11

C97

1

2

100P_0402_50V8J

KSO0

C125 1

2

100P_0402_50V8J

KSO12

C96

1

2

100P_0402_50V8J

KSO1

C124 1

2

100P_0402_50V8J

KSO13

C95

1

2

100P_0402_50V8J

KSO2

C114 1

2

100P_0402_50V8J

KSO14

C93

1

2

100P_0402_50V8J

KSO3

C113 1

2

100P_0402_50V8J

KSO15

C92

1

2

100P_0402_50V8J

KSI0
KSI1
KSI2
KSO0
KSO1
KSO2
KSI3
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSI4
KSO9
KSI5
KSI6
KSO10
KSO11
KSI7
KSO12
KSO13
KSO14
KSO15

1

G2
G1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

<31>
<31>

TP_CLK
TP_DATA

TP_CLK
TP_DATA

C522
2 0.1U_0402_16V4Z

3

JKB1

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2

KSO[0..15] <31>

1
2
3
4
5
6

GND
GND

8
7

ACES_85201-0605N
CONN@

D22
PJDLC05C_SOT23-3

1

KSO[0..15]

C

INT_KBD Conn.

<31>

JP11

Chage JP11 Pin define & Add D22

05/14

0111 Add C522 for JP11 pin1

Update TP/B Conn 05/04

C

ACES_85202-24051
CONN@

0108 Change 24 caps BOM structure from @ to mount (EMI)

B

B

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/10/09

Issued Date

Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

KB/SW/TP/LPC Debug CONN
Size
B
Date:

Document Number

Rev
1.0

NAVD0 LA-6091P
W ednesday, March 03, 2010

Sheet
1

32

of

46

091028 Modify Hole location by 1127_NAVD0_NEW_MB_ASSY_FOR_2865_v11

H_3P4X3P2N

H_8P7X5P8N

H2
H

H3
H

H17
H

H25
H

@

@
1

@
1

@
1

H5
H

H24
H

1

H16
H

H_3P2N

1

@

H_3P0N

H_2P8
H6
H

H7
H

H8
H

H9
H

@

1

@
1

@
1

1

1

@

1

@
@

20100201 change H4 from H_3P2N to H_3P2
H_3P2

@

H4
H
@
1

@
1

1

H22
H
@

@

FM4

H1
H

FM1
@

@

FIDUCIAL_C40M80

@

tm

ai

l.c
om

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ho

2010/10/09

Title

Screw
Size
B
Date:

Document Number

f@

Deciphered Date

in

2009/10/09

xa

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Rev
1.0

NAVD0 LA-6091P
Wednesday, March 03, 2010

Sheet

he

1

@

1

H14
H

FM3
@

1

@

1

FM2

H_3P8N

1

@

H23
H

1

H13
H

H21
H
@

1

1

@

1

@

H12
H

1

H11
H

1

H10
H

H20
H
@

1

H19
H
@

1

H18
H

H_2P6

33

of

46

A

B

C

D

+5VALW TO +5VS

+3VALW TO +3VS

091113 change Q19 P/N to SB564020020
+5VS
Q19
1
2
3
1
C219
1U_0603_10V4Z

1

+3VS

470_0402_5%
R190

1
2
3
C176
1U_0603_10V4Z

1

470_0402_5%
R114

2

1

2

Q15

2

2

SI4800BDY-T1-E3_SO8
8
7
6
5

091019 remove 10U*2
3

091019 remove 10U*2

3 1

4

SI4800BDY-T1-E3_SO8
8
7
6
5

+3VALW

4

+5VALW

1

E

Q17B
2N7002DW-T/R7_SOT363-6
C208
0.1U 25V K X5R 0402

SUSP

5

1

+VSB

Q12B
2N7002DW-T/R7_SOT363-6

R139
2
33K +-5% 0402
1

6

1

SUSP

5
4

5VS_GATE

2

4

1
R187
22K +-5% 0402

6

+VSB

C179

Q17A

2
2N7002DW-T/R7_SOT363-6

2

Q12A
SUSP

0.1U 25V K X5R 0402
2
2N7002DW-T/R7_SOT363-6

2
1

1

SUSP

2

100112 change Q47 P/N from SB00000AR00 to SB00000DH00

R141
100K_0402_5%

091113 change Q27 P/N to SB564020020
+1.8VS
Q27
S

D

SYSON#
4
6
ADD +5VS +VCCP +0.89VS Cap for EMI
R317

Q14A

+1.8V

0.1U 25V K X5R 0402

2
1

2N7002DW-T/R7_SOT363-6

C1173

@

1

C1174

@

1

C1175
@

2

2

2

1

C1176

2

+0.9VS

+3VLP
VL
2

2

1

2

2

C396

@
C1172

0.01U_0402_25V7K

Q28A
SUSP

1

@

0.01U_0402_25V7K

6

1

SUSP

0.01U_0402_25V7K

5
4

R318
200K +-1% 0402

0.01U_0402_25V7K

Q28B
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6
R830
10K_0402_5%

+1.8V

R172
100K_0402_5%
@

R173
100K_0402_5%

1

100112 change Q47 P/N from SB00000AR00 to SB00000DH00

3

SUSP

SUSP

3

<41>

1

+0.89VS

2
1

1

+VCCP
+5VS

1.8VS_GATE

SYSON

<31,40> SYSON

0.01U_0402_25V7K

091019 remove 10U*2

470_0402_5%

3

3

2

2

1

SI3456BDV-T1-E3 1N TSOP6

1U_0603_10V4Z

C395
G

6
5
2
1

+VSB

2

1

+1.8V to +1.8VS
+1.8V

3

2

100112 change Q47 P/N from SB00000AR00 to SB00000DH00

+5VALW

Q14B
5

<31,35,40,41,43> SUSP#

4

2N7002DW-T/R7_SOT363-6
R831
10K_0402_5%

2

SUSP

2N7002DW-T/R7_SOT363-6

2
1
6
Q8A
5 SUSP
@
2N7002DW-T/R7_SOT363-6

2

SYSON#

2N7002DW-T/R7_SOT363-6

2009/10/09

Compal Electronics, Inc.
2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

4

Compal Secret Data

Security Classification
Issued Date

4

1

4

4

@

R63

@

1
Q8B

SUSP

@
@

100112 change Q47 P/N from SB00000AR00 to SB00000DH00
470_0402_5%

3

1
Q6A
5

R70

@

6

1

470_0402_5%

R57

@

3
Q6B
2N7002DW-T/R7_SOT363-6

2
470_0402_5%

R51

+1.8V

1

470_0402_5%
@

+0.9VS

2

+VCCP

2

+1.5VS

D

Title

DC INTERFACE
Size
B
Date:

Document Number

Rev
1.0

NAVD0 LA-6091P
Wednesday, March 03, 2010

Sheet
E

34

of

46

5

4

3

2

1

+3VS to +3VSDGPU Transfer
0111 Change BOM Structure of C1302/C803/C1303/C801/C1294 from OPT@ to VGA@
+3VS

+VCCP to +1.05VSDGPU Transfer

J8

+VCCP

G

Q60
6
5
2
1

VGA_ON#

+1.5VSDGPU

1 OPT@ 2
2
R1485
0_0402_5%
1

2

1

2

VGA_ON#
OPT@2
0_0402_5%

C1296

2N7002DW-T/R7_SOT363-6
OPT@

C

S

D

100112 change Q55 P/N from SB00000AR00 to SB00000DH00

4
2
R716
VGA@

Q50B
2N7002DW-T/R7_SOT363-6
VGA@

1.5VSDGPU_GATE

<8,13,31> DGPU_PWR_EN

5
1
R722

<31,34,40,41,43> SUSP#

VGA_ON#
VGA@2
0_0402_5%

1
R1527

OPT@2
0_0402_5%

1
R800

DIS@ 2
0_0402_5%

VGA_ON

4

R715
200K +-1% 0402

470_0402_5%

1

2

3

G

3

VGA@

1
1U_0603_10V4Z

C768
SI3456BDV-T1-E3 1N TSOP6
VGA@

091113 change Q48 P/N to SB564020020

+VSB

5
1
R1481

1

JUMP_43X118
@
Q48
6
5
2
1

R1479
OPT@

0.1U 25V K X5R 0402
2 OPT@

Q55A

J10
2

1

OPT@

+1.5VS to +1.5VSDGPU Transfer

470_0402_5%

Q55B
2N7002DW-T/R7_SOT363-6
OPT@

1.05VSDGPU_GATE
R1483
200K +-1% 0402

2

1

G

Q69
SSM3K7002FU_SC70-3
OPT@

1

4

S

VGA@

091113 change Q60 P/N to SB564020020

+VSB

+1.5VS

C1294
3

D

2
G

C

4
SI3456BDV-T1-E3 1N TSOP6
OPT@

3

1

D

+3VSDGPU
R1508
470_0603_5%
OPT@

0301 change C802 P/N from SE070104Z80 to SE102104K00

1

6

2

2

2

1

1

2

C803
VGA@

3

1

C1302
VGA@

D

1

JUMP_43X118
DIS@

50mil(1140mA)
4.7U_0603_6.3V6K

0.1U_0402_16V4Z

1

Q68
AO3413_SOT23-3
OPT@

D

0.1U_0402_10V7K

+3VSDGPU_GATE 2
2
33K +-5% 0402
C802
OPT@

1
6

VGA@

1

1 VGA@ 2
2
R721
0_0402_5%

C769
VGA_ON

C25

2 @ 100P_0402_50V8J

1

091212 Add C25
to prevent switch noise

0.1U 25V K X5R 0402
2 VGA@

Q50A
VGA_ON#

+1.05VSDGPU
J9
2

1U_0603_10V4Z

OPT@
VGA_ON#
1
R1507

1

1

JUMP_43X79
DIS@

S

3

0223 change R1507 from 0ohm to 33k

2

S

2

D

100112 change Q50 P/N from SB00000AR00 to SB00000DH00

2N7002DW-T/R7_SOT363-6
VGA@

B

B

2

+5VALW

+1.8VS to +1.8VSDGPU Transfer

R1496
100K_0402_5%
VGA@
1

+1.8VS
VGA_ON#

J11

Q70
AO3413_SOT23-3
OPT@

1
1

R1497
22K_0402_5%
VGA@

R1511
470_0603_5%
OPT@

l.c
om

S

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/10/09

Issued Date

ho

Q71
SSM3K7002FU_SC70-3
OPT@

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

f@

2
G

tm

ai

D

Title

VGA DC INTERFACE

in

0301 change C800 P/N from SE070104Z80 to SE102104K00

Size Document Number
Custom
Date:

xa

2

Q66
SSM3K7002FU_SC70-3
VGA@

2

1

S

Rev
1.0

NAVD0 LA-6091P

he

2

C801
VGA@

D

2
G

VGA_ON

2

1

+1.8VSDGPU

1

C1303
VGA@

<43>

20mil(300mA)

1

1

3

1

1

4.7U_0603_6.3V6K

A

2

0.1U_0402_16V4Z

C800
OPT@

0.1U_0402_10V7K

+1.8VSDGPU_GATE
OPT@
200K +-1% 0402

G

R1510

D

VGA_ON#

2

JUMP_43X39
DIS@

S

3

2

3

091216 change value of R1510 to 200Kohm

Wednesday, March 03, 2010

1

Sheet

35

of

46

A

A

B

C

D

1

1

VIN
PL1
HCB2012KF-121T50_0805
1
2

DC_IN_S1

1

1
PC4
100P_0402_50V8J

PC5
100P_0402_50V8J

2

PC3
1000P_0402_50V7K

2

4
3
2
1

2

GND 4
GND 3
2
1

2

1

PJP1
6
5

1

SP02000GC00
PC6
1000P_0402_50V7K

ACES 88266-04001
CONN@

2

2

-

+

+RTCBATT

@ PBJ1

2

1

+RTCBATT

MAXEL_ML1220T10

VIN

PJ1

+3VALWP

2

2

PJ2
1

1

+3VALW

2

+5VALWP

2

JUMP_43X118

2

1

1

+5VALW

JUMP_43X118

PD2
RLS4148_LL34-2

1

1

2

1

BATT+

3

1

PD3
RLS4148_LL34-2

PR10
68_1206_5%

3

PR11
68_1206_5%
PJ4

+1.8VP

1

VS

2

2

+VCCPP

+1.8V

1

1

2

2

1

1

+VCCP

JUMP_43X118

JUMP_43X118

<22>

51ON#

1
PC14
0.1U_0402_25V6

2

TP0610K-T1-E3_SOT23-3

2

PR14
22K_0402_1%
1
2

PC13
0.22U_0603_25V7K

2

PR13
100K_0402_1%

2

1

1

3

PJ3

2

2

PQ1
N1

PJ5

+0.89VSP

2

2

1

1

PJ6

VGA_COREP

+0.89VS

2

JUMP_43X79

2

VGA_CORE

1

1

JUMP_43X118

+CHGRTC

PR16
560_0603_5%
1
2

PR17
560_0603_5%
1
2

+3VLP
PJ9

PJ7

+1.5VSP
4

2

2

1

1

+1.5VS

2

+0.9VSP

JUMP_43X118

Issued Date

2009/10/09

Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

1

1

+0.9VS

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2

JUMP_43X79

Title

DCIN/DECTOR
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

W ednesday, March 03, 2010
D

Sheet

36

of

46

A

B

C

VMB
PJP2

PL2
HCB2012KF-121T50_0805
1
2

VMB
TS
EC_SMCA
EC_SMDA

PH1 under CPU botten side :
CPU thermal protection at 92 degree C
Recovery at 70 degree C

BATT+

1

1

B/I

PC21
1000P_0402_50V7K

2

1
2
3
4
5
6
7
8
9
10

1

1
2
3
4
5
6
7
8
GND
GND

2

1

D

PC22
0.01U_0402_25V7K

VL
2

2

SUYIN_200275MR008G15QZR
VL

VCC TMSNS1

2

GND RHYST1

7

3

OT1 TMSNS2

6

OT2 RHYST2

5

PR31
13K_0402_1%

2

4

PR169
@ 47K_0402_1%
PH1

1

1

2

1
PR27
1K_0402_1%

2

1

8

2

1

2

+3VALW P

PR23 @
100K_0402_1%
1

PU3

2

1

PR29
10K_0402_1%

2

1

PC23
0.1U_0603_25V7K
PR25
6.49K_0402_1%
2
1

PR220
1K_0402_5%

PR28
21K_0402_1%

1

PR22
100_0402_1%

1

1

PR21
100_0402_1%

2

@

G718TM1U_SOT23-8
100K_0402_1%_NCP15W F104F03RC

2

2

2

1

BATT_TEMP <31>

MAINPW ON <39>
1

EC_SMB_CK1 <31>

PH2
@

EC_SMB_DA1 <31>

2

100K_0402_1%_NCP15W F104F03RC

@ PR236
0_0805_5%
1
2
PQ3
3

+VSB

1

PR30
100K_0402_1%

PR32
22K_0402_1%

2

1

D

S

1
SPOK

PQ4
2N7002W -T/R7_SOT323-3

2
G

l.c
om

<39>

3

1

PR34
100K_0402_1%

3

3

PC200
0.1U_0402_25V6

2

VL

2

2

TP0610K-T1-E3_SOT23-3

2

1

1

B+

4

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

in

Deciphered Date

BATTERY CONN / OTP
Size Document Number
Custom
Date:

xa

2009/10/09

Rev
1.0

he

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

f@

ho

tm

ai

4

NAVD0 LA-6091P

W ednesday, March 03, 2010
D

Sheet

37

of

46

A

B

C

D

B+

P2

PQ10
SI7121DN-T1-GE3_POW ERPAK8-5

PD9

VIN

2

1

1
2
3

1
5

CHG_B+

PR57 0.05_1206_1%
4

2

@ PJ8
2 2

1

1

5

CSIN

JUMP_43X118

3

1
2
3

3

20

6

VCOMP

CSIP

19

DH_CHG

PHASE

VREF

UGATE

17

2
AON7408L_DFN8-5

3
2
1

10UH_PCMB062D-100MS_2.5A_20%
PL5
CHG
1
2

BOOT

16

10

ACLIM

VDDP

15

11

VADJ

LGATE

14

GND

PGND

13

2

PR81
20K_0402_1%

12

26251VDD

1

PR74 0.05_1206_1%
4

2

3

AON7408L_DFN8-5

4

PD14
RB751V-40_SOD323-2

6251VDDP
DL_CHG

PQ21

BATT+
1

2

CHLIM

PC65
0.1U_0603_25V7K
BST_CHGA 2
1

1

9

1

.1U_0402_16V7K
PR79
38.3K_0402_1%
6251VREF 1
6251aclim
2

PR78
0_0603_5%
BST_CHG 1

2

4

5

ICM

PQ19

PR82
4.7_0603_5%
PC70
4.7U_0805_6.3V6K

1
2
PC71
4.7U_0805_25V6-K

CSIN

2 PACIN
G
2N7002W -T/R7_SOT323-3

PC68
10U_1206_25V6M
2
1

ICOMP

1

5

CSOP

3

21

S

PC67
10U_1206_25V6M
2
1

CSOP

8

PC54
2200P_0402_25V7K
2
1

3

CELLS

CSON

1

4

PR68
20_0402_5%
1
2
PC59
0.047U_0603_16V7K
1
2
PR69
20_0402_5%
2
1
PR70
PC62
20_0402_5%
0.1U_0603_25V7K
1
2
PR72
2_0402_5%
LX_CHG

PR76
4.7_1206_5%

22

PQ18D

5

CSON

VIN

PD13
1SS355TE-17_SOD323-2
2
1
2

PC58
0.1U_0603_25V7K
2
1

1
2

PR223
14.3K_0402_1%

EN

18

PR64
200K_0402_1%
1
2

1 1

2

PC214
1000P_0402_25V8J
2
1

3

7

PC53
4.7U_0805_25V6-K
2
1

1

PR221
191K_0402_1%

2
ACPRN

2

23

2

PR80
100K_0402_1%

2

ACSET ACPRN

VIN

PC66
680P_0402_50V7K

ACOFF

2

3
2
1

ACOFF

2

<31>

6251VREF

PC64
1
2

PR77
62K_0402_1%
2
1

IREF

PR73
100_0402_1%
1
2

1

DCIN

1

<31>

ADP_I

1

PQ22
DTC115EUA_SC70-3

<31>

6.81K_0402_1%
2

2
PC63
@ 100P_0402_50V8J

PC69
0.01U_0402_25V7K
2
1

PR75
22K_0402_5%
1
2

PR71
1

24

2

PC61
1
2
0.01U_0402_25V7K

DCIN

2

2N7002W -T/R7_SOT323-3

2

1

S

1

PACIN

D

3

PQ20
2
G

6800P_0402_25V7K
2

VDD

1

PC60
1

2

6251_EN

PC57
0.1U_0603_25V7K
2
1

1

1

PD10
1SS355TE-17_SOD323-2
ACOFF
1
2

PR62
10K_0402_1%

PQ16
DTC115EUA_SC70-3

1

2

@

PR58
47K_0402_1%
1
2

ACSETIN

2

PR66
150K_0402_1%
2

3

PQ17
2N7002W -T/R7_SOT323-3

1

1

2
PC56
.1U_0402_16V7K

2
G
S

PU5

1

PR67

DTC115EUA_SC70-3

D

FSTCHG

100K_0402_1%

<31>

2

PR65
10K_0402_5%
2
1

PQ15

3

1

2

@ PD12
1SS355TE-17_SOD323-2
1

PD4
RB751V-40_SOD323-2
PR222
10_1206_5%
2
1 1

1

ACSETIN

1

2

VIN
6251VDD

1

2

PR60
200K_0402_1%

PC55
2.2U_0603_6.3V6K
2
1

4
1

3

2

CSIP

PC52
5600P_0402_25V7K
1
2

PR59
47K_0402_1%

PC51
0.1U_0603_25V7K
2
1

1

DTA144EUA_SC70-3
PQ12

PC50
4.7U_0805_25V6-K
2
1

1

PC165
0.1U_0603_25V7K
2
1

4

B340A_SMA2

PQ11
SI7121DN-T1-GE3_POW ERPAK8-5

B+

P3

ISL6251AHAZ-T_QSOP24

3

3

CP = 85%*Iada ; CP = 1.343A

CP mode
Vaclim=2.39*(4.99K/(20K+4.99K))=1.876V

PR83
15.4K_0402_1%
1
2
2

<31> CALIBRATE#

6251VDD

PR85
31.6K_0402_1%
1

1

Iinput=(1/0.05)((0.05*Vaclm)/2.39+0.05)=1.343A

PR224
10K_0402_1%
1
2

1

Iada=0~1.58A(30W)

PR225
100K_0402_1%

<19,31>

PACIN
D

S

1

1 2

2N7002W -T/R7_SOT323-3
PR227
20K_0402_1%
2

ACPRN

PQ36
2
G

3

2

CC=0.3~1.76A
IREF=1.62*Icharge
IREF=0.486V~2.85V
3.24V==>2A

ACIN

PR226
10K_0402_1%

BATT Type

Charging Voltage
(0x15)

VADJ-->VREF-->4.41V

CV mode

VADJ--->Ground--->3.99V
Vcell=(0.175*VADJ+3.99)

4

4

Normal 3S LI-ON Cells

12600mV

12.60V

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/10/09

Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

CHARGER
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

W ednesday, March 03, 2010
D

Sheet

38

of

46

5

4

3

2

1

UG_3V

10

DRVH2

DRVH1

21

UG_5V

LX_3V

11

LL2

LL1

20

LX_5V

LG_3V

12

DRVL2

DRVL1

19

LG_5V

2

B++
1

5

2

PC43
680P_0402_50V7K

1

PC44
150U_B2_6.3VM_R45M

1
2

PR38
4.7_1206_5%

3
1

PQ8

IRFH3707TRPBF_PQFN8-3

VCLK

+5VALWP

1
+

2

B

2N7002W -T/R7_SOT323-3

+3.3VALWP Ipeak=6.42A=(5.82+0.6)A Imax=4.5A Vo=3.3V
Rds(on)=17.9m ohm(max) ; Rds(on)=14.5m ohm(typical)
Vtrip=(10E-06 * 143K)/9-24mV=156mV
Ilimit=156/(14.5~14.5*1.2)=10.76~7.26 A

1

+5VALWP
Ipeak=3.86A Imax=2.7A Vo=5.14v
Rds(on)=17.9m ohm(max) ; Rds(on)=14.5m ohm(typical)
Vtrip=(10E-06 * 158K)/9-24mV=151mV
Ilimit=151mV/17.9m ~151mV/14.5m x 1.2
=8.467A ~ 8.710A
Iocp=Ilimit+Delta I/2
=9.384A ~ 9.627A
Delta I=1.834A (Freq=245KHz)

1

Iocp=Ilimit+Delta I/2
=11.3~7.81A
Delta I=1.090A (Freq=305KHz)

l.c
om
ai
ho

tm
Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Title

3V/5V
Size
Document Number
Custom
Date:

in

2009/10/09

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

5

A

Rev
1.0

xa

3

PQ35
DTC115EUA_SC70-3

NAVD0 LA-6091P

he

2

2
1
PR235
40.2K_0402_1%

1

2

PR234
100K_0402_1%

@ PC213
0.01U_0402_16V7K

2

2

PC205
4.7U_0805_10V6K

PC204
1U_0603_10V6K
2
1

VL

PR231
@ 0_0402_5%

PQ34

<37> MAINPW ON

1

TPS51125RGER_QFN24_4X4

2
1

1
2

PR232
100K_0402_1%

1

C

PL4
8.2UH 20% FMJ-0630T-8R2A HF 4.5A
1
2

B+

PR233
100K_0402_1%

VS

18

VIN

VREG5
17

16

GND
15

13

PR230
499K_0402_1%
1
2

SKIPSEL

EN0

VFB=2.0V

PQ6
AON7408L_DFN8-5

4

3
2
1

PR40
PC41
0_0603_5% 0.1U_0402_16V7K
BST_5V 1
2 1
2

2
PC212
0.1U_0603_25V7K

1

3

2

S

2
G

S

VL

3

1
2
G

2N7002W -T/R7_SOT323-3

PC34
2200P_0402_50V7K
2
1

22

2VREF_51125
D

1

3

2
VFB1

23

VBST1

ENTRIP2

PQ33 D

A

VREF

4

6

5

PGOOD

VBST2

ENTRIP1
B

<37>

VREG3

2
IRFH3707TRPBF_PQFN8-3

SPOK

24

9

14

1
2
3
3

VO1

8

PQ7

1

2

PC42
680P_0402_50V7K
2
1

+

PC39
150U_B2_6.3VM_R45M

1

PC40
0.1U_0402_16V7K

PR37
4.7_1206_5%
2
1

PL3
8.2UH 20% FMJ-0630T-8R2A HF 4.5A
1
2

PR39
2 1
2
0_0603_5%

VO2

B++

BST_3V

C

1

7

PR229
158K_0402_1%
2

ENTRIP1

4

+3VALWP

P PAD

TONSEL

1

PU4

25

1

VFB2

PR228
162K_0402_1%
1
2

ENTRIP1

PR44
19.1K_0402_1%
1
2

2

PC203
4.7U_0805_10V6K

5

PC31
2200P_0402_50V7K
2
1

PQ5
AON7408L_DFN8-5

2

PR43
18.7K_0402_1%
1
2

ENTRIP2

PR42
30K_0402_1%
1
2

+3VLP
PC36
10U_1206_25V6M
2
1

B+

PL11
HCB2012KF-121T50_0805
1
2

PR41
12.7K_0402_1%
1
2

ENTRIP2

B++

D

PC32
10U_1206_25V6M
2
1

D

1

PC202
0.22U_0603_10V7K

2VREF_51125

W ednesday, March 03, 2010

Sheet
1

39

of

46

A

B

C

D

PL12
HCB2012KF-121T50_0805
1
2

PR90
1K_0402_1%
1
2

4

PR91
0_0603_5%
BST_1.8V 1
2

1

PQ23
AON7408L_DFN8-5

1

2

RT8209BGQW _W QFN14_3P5X3P5
2

PC82
4.7U_0805_10V6K

1
+
2

PC78
220U_B2_2.5VM

DL_1.8V

9

LGATE

1

NC
PGND

7

PC208
47P_0402_50V8J
1
2

8

2

@

 VFB=0.75V
Vo=VFB*(1+PR96/PR97)=1.8V
Fsw=262 KHz
1

PR96
5.9K_0402_1%
1
2

Cout ESR=15m ohm Rdson(max)=17.9m Rdson(typical)=14.5m
Ipeak=6.36 A, Imax=4.45 A, Iocp=7.63 A

PR97
4.12K_0402_1%

2

2

B+

PC167
0.1U_0603_25V7K
2
1

5
PR98
300K_0402_5%
1
2

4

PR100
0_0603_5%
BST_1.05V 1
2

PQ25
AON7408L_DFN8-5

LGATE

9

DL_1.05V
1

PGND

2

RT8209BGQW _W QFN14_3P5X3P5
2

7

PC209
47P_0402_50V8J
1
2

8

PGOOD

@

GND

1
2

PC89
4.7U_0603_6.3V6K

6

+5VALW

PC92
4.7U_0603_10V6K

1
+
2

PC88
330U_B2_2.5VM_R15M

10

3

LX_1.05V

PR102
4.7_1206_5%

VDDP

2
PR104
14K_0402_1%

1

PC90
680P_0603_50V7K

NC

14

11

1

FB

12

CS

+VCCPP

2

5

PHASE

1

VDD

13

2

VOUT

4

DH_1.05V

UGATE

PQ26
IRFH3707TRPBF_PQFN8-3

3

BOOT

TON

PL7
2.2UH_FMJ-0630T-2R2 HF_8A_20%
1
2

3

PR103
100_0603_1%
1
2

2

PC87
0.1U_0603_25V7K
BST_1.05V-1 1
2

1

+5VALW

15

1

PU7

EN/DEM

PC86
.1U_0402_16V7K

2

2

@ PR101
30K_0402_5%

1

1

3
2
1

PR99
1K_0402_1%
1
2

<31,34,35,41,43> SUSP#

PL13
HCB2012KF-121T50_0805
1
2

+VCCP_B+
PC30
10U_1206_25V6M
2
1

Delta I=((19-1.8)*(1.8/19))/(2.2u*262 K)=2.82 A
=>1/2DeltaI=1.41A
Vtrip=137mV
Iocp=Vtrip/(Rdson)+1.41
=95.3/(17.9~21.48)+ 1.41=9.07~7.79

PC83
2200P_0402_50V7K
2
1

2

PGOOD

GND

6

PC79
4.7U_0603_6.3V6K

+5VALW

2

10

2
PR95
13.7K_0402_1%

+1.8VP

PR93
4.7_1206_5%

VDDP

LX_1.8V
1

1

11

2

FB

12

CS

0.1U_0603_25V7K

PC80
680P_0603_50V7K

5

PHASE

DH_1.8V

PQ24
IRFH3707TRPBF_PQFN8-3

VDD

13

3

VOUT

4

BOOT

3

UGATE

1

PR94
100_0603_1%
1
2

TON

PL6
2.2UH_FMJ-0624T-2R2 HF_7A_20%
1
2

PC76
1
2

BST_1.8V-1

1

+5VALW

2

14

1

PU6

EN/DEM

PC77
1U_0402_6.3V6K

2

2

@ PR92
30K_0402_5%

15

1

1

<31,34> SYSON

B+

PC166
0.1U_0603_25V7K
2
1

PC73
2200P_0402_50V7K
2
1

5
PR89
300K_0402_5%
1
2

3
2
1

1

PC33
10U_1206_25V6M
2
1

1.8V_B+

3

1

PR105
3.48K_0402_1%
1
2

2

PR106
8.25K_0402_1%

 VFB=0.75V
Vo=VFB*(1+PR105/PR106)=1.052V
Fsw=262KHz
Cout ESR=15m ohm Rdson(max)=17.9m Rdson(typical)=14.5m
Ipeak=6.1A, Imax=4.27 A, Iocp=7.32 A
Delta I=((19-1.05)*(1.05/19))/(2.2u*262K)= 1.72A
=>1/2DeltaI=0.86A
Vtrip=14K*10uA=0.140 V
4

4

Iocp=Vtrip/(Rdson)+0.86
=113/(17.9~21.48)+0.86=8.68~7.37 A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/10/09

Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

VCCPP/1.8VP
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

W ednesday, March 03, 2010
D

Sheet

40

of

46

5

4

3

2

1

 VFB=0.6V
Vo=VFB*(1+PR117/PR116)=0.6*(1+30.1K/61.9K)=0.8917V

D

D

Ipeak=2.64A

1

1
2

1
PR116
61.9K_0402_1%

PC211
22U_0805_6.3VAM

1

NC

@

1
2
1

SY8033BDBC_DFN10_3X3

@

+0.89VSP

2

2
PR125
@ 47K_0402_5%

C

7

EN_SY8033B

30.9K_0402_1%
FB_SY8033B

2

2

6

PC103
680P_0603_50V7K

1

PR119 0_0402_5%

1

SUSP#

11

TP

FB

PR117

2

EN

3

PC101
22U_0805_6.3VAM

SVIN

5

LX

PC102
22P_0402_50V8J
2
1

8

PC104
0.1U_0402_10V7K

<31,34,35,40,43>

PL14
1UH_PCMB062D-1R0MS_9A_20%
1
2

LX_SY8033B

2

PVIN

2

1

9

LX

2

PC105
22U_0805_6.3VAM

PVIN

2

1

JUMP_43X79

10

PR118
4.7_1206_5%

1

NC

1

PG

2

4

PU9

PJ10

2

1

@

+5VALWP

C

+1.8V
B

PJ11
JUMP_43X79

2

1

1

B

6

NC

5

3

VREF

NC

7

4

VOUT

NC

8

TP

9

+3VALW
1

VCNTL

GND

PC111
1U_0603_6.3V6M

2

2

PR121
1K_0402_1%

1

PC110
4.7U_0805_6.3V6K

VIN

2
1

2

2

PU11
1

Ipeak=1A, Imax=0.7A

l.c
om

1
2

PC199
.1U_0402_16V7K

2

1

+0.9VSP
PC114
10U_0805_6.3V6M

1
2

3

PR123
1K_0402_1%
S
2N7002W -T/R7_SOT323-3

2

PC113
.1U_0402_16V7K

D

PC112
.1U_0402_16V7K
2
1

SUSP

1

<34>

PQ29
2
G

1

APL5336KAI-TRL SOP
PR122
0_0402_5%
1
2

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

in

2010/10/09

0.89VSP/0.9VSP
Size Document Number
Custom
Date:

xa

Deciphered Date

he

2009/10/09

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

A

Rev
1.0

NAVD0 LA-6091P

W ednesday, March 03, 2010

Sheet
1

41

of

46

A

B

C

D

E

F

G

H

<5>

<5>

<5>

CPU_VID2
<31>
CPU_VID3
<5>
CPU_VID4
<5>
CPU_VID5
<5>
CPU_VID6
<5>

VR_ON

CPU_VID1

1

CPU_VID0

1

1

+3VS

2
3211_SW

1
2

PC148
0.1U_0402_25V6

1
2

PC147
2200P_0402_50V7K

PC107
10U_1206_25V6M
2
1
AON7408L_DFN8-5

PL10
2.2UH_FMJ-0624T-2R2 HF_7A_20%
1
2

+CPU_CORE

+CPU_CORE

3

PR124
4.7_1206_5%

1

PC186
2.2U_0603_10V6K

18

PQ31

2

2

2

1

3211_DRVL

17

IRFH3707TRPBF_PQFN8-3

33

2

AGND

+5VS

LL=5.9m ohm
OCP=7.85A
VID:0.75V~1.1V
Io(max)=6.04A
DCR=23m

PC115
680P_0603_50V7K

PH4
100K_0402_1%_NCP15WF104F03RC

1

2
3

Place RTH1 close to inductor
on the same layer
1

1

1

PR217
75K_0402_1%

2

2

2

PC190
220P_0402_50V7K

PC189
1000P_0402_50V7K

2

1

1
2

PR218
422K_0402_1%

1

PC191
1000P_0402_50V7K

4

1

CSCOMP

AGND

20

3211_RAMP-1

Connect to input caps

2

1

21

PR206
PC183
0_0603_5%
0.22U_0603_25V7K
2CPU_BOOST-1
1
2

3
2
1

22

3211_DRVH

19

B+

16

CSREF

CSFB
15

2

25
VID6

27

26
VID5

VID4

29

28
VID3

VID2

5

1

1

1
VID6

3211_VCC

1
VID5

PR204

1
VID4

PR203

1
VID3

PR202

1
VID2

14

23 CPU_BOOST 1

PR213
35.7K_0402_1%
2
1

2

<6>

<6>

VCCSENSE

LLINE

RAMP
2

1

1
VSSSENSE

+CPU_B+

PR219
1K_0402_1%
2
1

13

12
3211_RAMP

IREF
9
PR211
200K_0402_1%
1
2 3211_RPM

PR210
80.6K_0402_1%
3211_IREF
1
2

2

2

PR158
0_0402_5%

2

PQ30

24

3211_CSCOMP

PR150
0_0402_5%

3211_CSFB

Avoid high dV/dt

3211_CSCOMP

3211_CSCOMP 1

PR209
2.61K_0402_1%

3

PR201

1
VID1

ILIM

PR207
28K_0402_1%

2

PC188
470P_0402_50V8J

30

PGND
GPU

3211_ILIM 8
PR208
1K_0402_1%

VID1

DRVL
COMP

2

PC182
1U_0805_25V6K

1

7

PVCC

FB

PR214
499K_0402_1%

3211_COMP 6

ADP3211AMNR2G_QFN32_5X5

RT

1

23211_COMP-1
1

2

PC187
47P_0402_50V8J

1

FBRTN

5

11

2

PR199

1

SW

3211_RT

1

31

32
EN

DRVH
CLKEN#

RPM

2

3211_FB

2

VID0

1
1
2

BST
IMON

3

PL9
HCB2012KF-121T50_0805

1
PR200
10_0603_1%

PWRGD

2

<13> CLK_ENABLE#

PC185
390P_0402_50V7K

+CPU_B+

VCC

1

4
1

+5VS

PU12

PR205
10K_0402_1%
PC184
1000P_0402_50V7K

PR198

1

VID0

PR196

+3VS

3211_EN

2

10

VGATE

PR212
274K_0402_1%
1
2

<5,13,19,31>

PR195
0_0402_5%
2
13211_PWRGD

PR197

2

2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%

PR194
4.7K_0402_1%

1000P_0402_50V7K
PC192

Shortest the
net trace

4

4

2009/10/09

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/10/09

Title

CPU_CORE

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
C
Date:

A

B

C

D

E

F

G

Document Number

Rev
1.0

NAVD0 LA-6091P
Wednesday, March 03, 2010

Sheet

42
H

of

46

5

4

3

2

1

Ipeak=11.6 A
Imax=8.15 A
delta I=3.27A 1/2 delta I=1.636 A
Iocp=RTEIP*ITRIP/RDS(ON)+1/2 I=14~11.98 A
Rds(on)=11~14m
PL20

D

PQ41
AON7408L_DFN8-5
PR253
300K_0402_5%
1
2

<31>
PR192
1.58K_0402_1%
1
2

8

7

@PC93
@
PC93
0.22U_0402_10V6K

1
1

4

RT8209BGQW _W QFN14_3P5X3P5

PC150
4.7U_0805_10V6K

VFB=0.75V

PQ32

+
2

C

AON7702L_DFN8-5

PR254
1

1

1
2

3

PR242
10K_0402_5%
1

PC181
0.22U_0402_10V4Z

PQ51
2N7002W -T/R7_SOT323-3

PR241
10K_0402_5%

1.5V_B+

5
B

PR112
300K_0402_5%
1
2

3
2
1

AON7408L_DFN8-5

LGATE

9

DL_1.5V

PQ27

1
+
2

4
1

PGND

RT8209BGQW _W QFN14_3P5X3P5
2

8

Ipeak=8.62 A
Imax=6.034 A
Iocp=10.35 A

GND

PC210
47P_0402_50V8J
1
2

7

@
2

PC99
4.7U_0603_6.3V6K

+5VALW

PC98
4.7U_0805_10V6K

AON7702L_DFN8-5

l.c
om

NC

14

10

LX_1.5V

PC91
330U_B2_2.5VM_R15M

PGOOD

VDDP

2
PR109
16.9K_0402_1%

1

PR113
4.7_1206_5%

6

11

PC95
680P_0603_50V7K

FB

12

CS

1

5

PHASE

+1.5VSP

2

VDD

13

1

VOUT

4

DH_1.5V

UGATE

2

3

BOOT

TON

PL8
2.2UH_FMJ-0630T-2R2 HF_8A_20%
1
2

5

PR111
100_0603_1%
1
2

2

PC94
0.1U_0603_25V7K
BST_1.5V-1
1
2

1

Vo=1.518V
Fsw=262 KHz

PQ28

3
2
1

+5VALW

15

PU8

1

@
PC97
.1U_0402_16V7K

2

2

PR110
30K_0402_5%

EN/DEM

@

B

4

PR114
0_0603_5%
BST_1.5V 1
2

1

<31,34,35,40,41> SUSP#

B+

1

PR115
0_0402_5%
1
2

PL15
HCB2012KF-121T50_0805
1
2

PC96
10U_1206_25V6M
2
1

PC180
0.22U_0402_10V4Z

GPU_VID1 <8>

2

2
1

1

3

1
2
10K_0402_5%

10_0402_1%

PC100
2200P_0402_50V7K
2
1

1

0.85V

S

GPU_VID0 <8>

+VGASENSE <10>

2

@
PR244
10K_0402_5%

1

1

1

2
G
S

2

0

PQ50
2N7002W -T/R7_SOT323-3

1.03 V

2
G

2

1

2

2

0

PR246

PR247
1
2
10K_0402_5%

D

PR243
10K_0402_5%
@

D

GPU_VID0 GPU_VID1

@ PR248
2.61K_0402_1%
1 2

1

1

+3VSDGPU
@ PR245
2K_0402_1%

PR184
10K_0402_1%

2

1

+3VSDGPU

0

PC149
330U_D2E_2.5VM_R9M

LG_VGA

1

LGATE

9

VGA_COREP

1

PR251
0_0402_5%
2

1

VGA_TRIP
+5VALW
1
2
PR215
15.8K_0402_1%

PR250
4.7_1206_5%

VDDP

10

2

BOOT

NC
PGND

PGOOD

PR216
0_0402_5%

VGAPW RGD

SW _VGA

11

FB
GND

2

6

12

CS

2

5

PHASE

PC201
680P_0603_50V7K

VGA_FB

UG_VGA
5

VDD

13

3
2
1

VOUT

4

D

PL18
1UH_PCMB062D-1R0MS_9A_20%
1
2

UGATE

11

1

PC207
47P_0402_50V8J
1
2

C

3
VGA_V5FILT

10K_0402_1%
1 PR255 2
+5VS

@
2

PC206
4.7U_0603_6.3V6K

TON

2

PR252
100_0603_1%
1
2

+5VALW

2

BST_VGA-1 1
2
PC155
0.1U_0603_25V7K

14

1
EN/DEM

PU13

2

2

PC81
0.1U_0402_16V7K

15

1

@
PR120
30K_0402_5%

B+

3
2
1

VGA_EN
1

<35> VGA_ON

4

PR193
0_0603_5%
BST_VGA
1
2

2

VGA_TON
PR249
47K_0402_1%
1
2

2

HCB2012KF-121T50_0805

PC106
10U_1206_25V6M
2
1

5

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

in

2010/10/09

VGA_CORE/1.5VSP
Size Document Number
Custom
Date:

xa

Deciphered Date

he

2009/10/09

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

PR108
4.12K_0402_1%
2

Ilimit=9.44A ~ 7.86A
Iocp=Ilimit+Delta I/2
=12~10.5A
Delta I=5.27A (Freq=262KHz)

A

tm

1

Rds(on)=17.9m ohm(max) ; Rds(on)=14.5m ohm(typical)

ai

PR107
4.22K_0402_1%
1
2

A

Rev
1.0

NAVD0 LA-6091P

W ednesday, March 03, 2010

Sheet
1

43

of

46

5

4

3

2

1

Version change list (P.I.R. List)
Item

Fixed Issue

D

B

Reason for change

Rev.

PG#

Modify List

Date

1

For save layout space and shortage

A

change PC50 PC53 to 0805 4.7u

2

For VGA_core 51117 power good delay

A

Reserve PR216 PC93

3

Save layout space

4

C

Page 1 of 1 for PWR

A

D

Delet PC35 PC36, change PC29 PC32 to 1206 10uF

For cost down

A

change 0.89V from MP2121 to SY8033

5

For cost down

A

delet Vin detector,battery OVP circuit

6

For cost down

A

change 3V/5v from ISL6237 to TPS51125

7

For Design change

A

change PR116 to 61.9K
PL14 to 1uH

8

For cost down

9

For cost down

A
A

PR117 to 30.1K

change 1.5V PL8 to 3mm
change VCCP

height

PL7 to 3mm

C

height

10

For Design change

11

For Design change

A

change PQ23 PQ25 PQ28 PQ30 TO AON7408

12

change 1.5V enable RC ,for HW request

A

change PR115 to 0 ohm ,unpop PR101

13

change VCCP enable RC ,for HW request

A

change PR99 to 1k ohm ,pc86 to 0.1u,unpop PR110

14

change VGACORE enable RC ,for HW request

A

change PR249 to 47k ohm ,pc81 to 0.1u,unpop PR120

15

For charger ripple

Add PC71 4.7u 0805 25V

16

For charger ripple

change PL5 to 10uF

17

Buyer suggest

change PQ36

18

Fix VGA_VID at 0.85V

delete PR248 PR245 ,change PR192 to 1.58K

19

OTP INPUT PULL HIGH resister

Add PR29

20

change OTP set

change PR31 to 13K

21

1.8V enable cap

Add PC77 1u 6.3v X5R

22

51125 VL cap size up to 1206

change PC205 to 1206 size

23

Buyer suggest

change PC96 PC106 PC107 from X6S to X5R

A

Phase

change PQ31 to IRFH3707

B

from 2N7002 TO SSM3K7002FU

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/10/09

Deciphered Date

2010/10/09

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PIR-PWR-1
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

W ednesday, March 03, 2010

Sheet
1

44

of

46

5

4

3

2

Version change list (P.I.R. List)
Item

1

Page 1 of 1 for PWR

Fixed Issue

Reason for change

Rev.

PG#

Modify List

Date

D

1

2009.6.30

EVT

2

2009.6.30

EVT

3

2009.7.2

EVT

2009.8.4

EVT

5

2009.8.12

EVT

6

2009.8.12

EVT

7

2009.8.12

EVT

8

2009.8.12

EVT

9

2009.8.24

EVT

10

2009.8.24

EVT

11

2009.8.24

EVT

12

2009.8.24

EVT

13

2009.8.24

EVT

14

2009.8.24

EVT

15

2009.8.27

EVT

16

2009.9.4

DVT

17

2009.9.10

DVT

18

2009.9.30

PVT

4

C

B

Phase
D

C

B

19
20
21

l.c
om

22
A

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PIR-PWR-2
Size Document Number
Custom
Date:

in

2010/10/09

Rev
1.0

xa

Deciphered Date

NAVD0 LA-6091P

W ednesday, March 03, 2010

he

2009/10/09

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

23

Sheet
1

45

of

46

5

4

<2009/4/28>
Update new power schematic,
release first version NAV50 schematic
<2009/04/29>
. Add R1182 R1183 L3 on page 9
. Change J3 to R1184 on page 13

<2009/06/12>
. Page4 Add C314 C313 C1150 D19 on +VCC_FAN1
. Page8 Add C1145 C1146 C1147
. Page10 Move CRT_DET# from Page13 to Page10
. Page13 Add +RTCVCC circuit

<2009/05/04>
. Add WWAN_CLKREQ# and R107 pull-high to +3VS on page 8
. Add CRT_DET# on page 10
. Add CRT_DET# circuit on page 13
. Add 3 LEDS on page 16
. Add BT/BTN Board CONN. on page 16
. Update TP/B CONN. to SP01000LB00 on page 19

<2009/06/17>
. Update New Power schematic 06/17
. Page9 modify LVDS Conn. Pin define
. Page9 Del C1110
. Page4 Add EMI solution D38 D39 D40

<2009/05/14>
. Update New Power schematic
. Del R376 R377 on page 8
. Del D5 D7 D8 on page 4
. Change JLVDS1 to SP010006810 on page 9
. Add D6 for EMI on page 9
. Change C1106 to C_0603 type on page 9
. Change USB_OC# on page 13
. Add USB Port2 on page 20
. Change JP11 Pin define & Add D22 on page 19
. Change C512 to 1u_0402 on page 15
. Add U29 (MEDIA_LED#)) on page 16

互互

<2009/09/10>
Update Power schematic 0910
. Page22 unmount Q6 Q8

<2009/06/23>
. Page15 Add C1163 C1164 C1165 C1166
. Page18 change PWR/B Conn. P/N to SP01000H300
. Page22 change JUSB1 JUSB2 P/N

B

<2009/06/24>
. Page8 Change C1350 C1351 to 0402 type
. Page10 Add R1385 R1386 on JVGA_HS JVGA_VS
<2009/06/25>
. Page22 move some parts to I/O Board , Add the MONO_IN_R on M/B
.
<2009/06/29>
. Page16 Change JP24 to ACES_88266_05001
. Page15 Change JMINI1 to FOX_AS0B246-S50U-7F_52P-T

<2009/06/05>
.Update new clock GEN co-lay schematic on page 8
.Follow Intel check list change C161 C165 to 27P on page 8
.Follow Intel check list change C56 to 22uF on page 6

<2009/06/30>
. Page18 Change PWR_LED# to PWR_PWM_LED#
. Page17 Add PWR LED DETECT PIN on Pin97

<2009/06/08>
.Update New Power schematic 06/06 version
Page 13- a.Del R203 (pull-up GPIO6 Resister)
b.Change R1184 NU
Page 17- a. Add VGATE
b. Del R1294
c. Change D30 NU
d. Change R1295 to 0 ohm
e. Add R1309 0 ohm on EC_RSMRST#
f. Pull-up LAN_WAKE# +3VALW
g. ICH_POK change to PCH_POK
h. Pull-up KB_RST# to +3VS
Page 10- a. Add R1283 R1284 ,Change R247 R249 to 10 ohm
b. Add @ on U10 U11 C301 C298
c. Del C302 C300 R1281 R1287

<2009/07/02>
. Update New Power schematic 07/02
. Page9 Add C1167 C1168 for RF request.
. Page13 Change R223 to 100K
. Page16 change JP24 to ACES_85201-0505N
. Page17 Del R1387 R1388 on EC Pin97
. Page17 Add New Board ID to separate NAV50 NAV60
IC to SA00003J400 (New)
. Page17 Change
. Page18 Add D41 for ESD

展展

A

2009/10/09

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/09

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C

<2009/06/22>
. Page22 change IO Conn. pin34 from 48M to USB_ON#
. Page10 change JCRT1 P/N to SP010906182

<2009/05/19>
.Update new clock GEN co-lay schematic on page 8

A

<2009/09/08>
Update Power schematic 0904
. Page18 Change R1388 to 100 ohm 0402
. Page18 Change LED1 to SC591NB5A00

<2009/06/19>
. Page4 Add new signal CPU_ITP , CPU_ITP#
. Page5 ADD R1378
. Page6 ADD C1152,C1153,C1154 C1160,C1161,C1162
. Page7 DDR_A_D8 DDR_A_D9
. Page8 ADD R1379,R1380,U77,R1381,C1157,R1382,R1383,R1384,C1157
, Page8 DEL C390
. Page9 ADD C1156
. Page11 DEL R1322, R1154
. Page13 DEL U77, ADD C1158
. Page17 ADD C1159

與

<2009/08/04>
. Page5 CLK_CPU_HPLCLK CLK_CPU_HPLCLK# exchange
. Page9 Change JLVDS1 to P/N ACES 88341-3001 30P
. Page17 del PM_1.8V(U6.82) ,Del R1310 R1311
. Page18 Del D41

<2009/09/03>
. Page7 Change C112 to 0402 type
. Page8 Add T6 on CLK_48M_CR
. Page16 Modify JP18 Pin define change +5VALW +5VS to +3VALW +3VS
. Page20 Change Pin 18, 23 to +1.5VS change Pin7 , 9 to USB20_P7 N7
. Page21 Del H12

<2009/06/18>
. Update New Power schematic 06/18
. Page8 modify U4 Pin define and Q31
. Page13 Add R1376, R1377
. Page15 Modify C403
. Page23 Modify H11

<2009/05/12>
. Follow Intel Layout Checklist, Add C141 on VDDSPD on page 7
. Modify SRC CLK PORT LIST on page 8
. Del CLKREQ_LAN# on page 8
. Change PCIE Port list on page 13
. Change USB Port list on page 13
. Add W/L 3G SW on page 16
. Del R103 on page 18

D



<2009/06/16>
. Page7 Modify DDR Command Control Pin pull-high Resister location
. Page9 Change R577 to 0402 type

<2009/05/13>
. Change JMINI1 to PCIE Port 3 on page 15
<2009/05/14>
. Page8 Change C174 C175 to 10U_0603

B

1

<2009/07/08>
. Page5 Add 470pf on H_SMI# for known issue.

<2009/06/15>
. Update New Power schematic (change PBJ1 to PJP3)
. Page 10 modify C310 C308 C303 C307 C306 C304 Bom Structure
. Page 22 Modify Hole location by (ME drawing 06/12)

<2009/05/11>
. Add INVT_PWM on Page 5
. Del R323 on page 5
. C74 change to 2.2U_0603 on page 6
. C267 change to 22U on page 6
. C391 change to 0.1U on page 6
. Del C67 C35 C33 C36 on page 6
. Del +LGI_VID and U71.A21 direct connect to +VCCP on page 6
. Follow Intel checklist, add R52 on FSB on page 8
. Add D5 D7 D8 on page 4
. Add R174 on page 9
. Add PCI_RST# on page 11
. Add C1115 C1114 C1116 C1117 C1118 on page 15

C

2

<2009/07/03>
. Page18 Add D41.2 to PWR_PWM_LED#
. Page8 Change co-lay net name to +1.5VM_CK505
. Page20 Change JP2 Pin42 to +5VS
<2009/07/06>
. Page18 Add pwr switch for NAV50

<2009/04/30>
. Change JDIM1 to SP07F001720 on page 7
. Del SATA1 Port on page 12
. Change R51 R57 R70 R63 R317 R314 R190 to 0402 Size on page 21
D

3

<2009/06/10>
. Page 7- Add C116 @
. Page 22- Modify USB_OC#1_2 to USB_OC#2
. Page 17- Modify PLTRST# to PCI_RST#
. Page 17- Add @ on R1311

4

3

2

Title

PIR -HW
Size Document Number
Custom
Date:

Rev
1.0

NAVD0 LA-6091P

Wednesday, March 03, 2010

Sheet
1

46

of

46



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