Compal LA 1432

User Manual:

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A

B

C

D

E

1

1

ATR60 LA-1432 REV1.A Schematics
Document
2

2

Intel Pentium 4 Processor it the 478-pin
Package

with 845D chipset

3

3

4

4

Title

Compal Electronics, Ltd.
Cover Sheet

Size
B
Date:
A

B

C

D

Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

1

of

45

COMPAL CONFIDENTIAL
MODEL

NAME : ATR60 LA-1432

REV:1.A

CRT & TV-OUT
& LVDS

VGA Controller

PIRQA#

Reset Circuit
PAGE 38

Brookdale-D MCH

nVIDIA NV17M

PAGE 18

PAGE 12

PSB

VGA DDR
CH-A

VGA DDR
CH-B

W320-04

PAGE 4,5

PAGE 19

PAGE 17

CLOCK

Northwood
uFCBGA/uFCPGA
CPU

Host-HUB Bridge

AGP BUS

IDSEL: AD11

DDR SODIMM X2
-BANK 0,1,2,3

MEMORY BUS

PAGE 13,14,15,16

POWER
INTERFACE
PAGE 37

PAGE 9,10,11
PAGE 6,7,8

Direct CD
Play

HUB Link

PAGE 28

PCI BUS
IDSEL: AD20
MASTER 2
PIRQA#,
PIRQB#
SIRQ

IDSEL: AD16
MASTER 0
PIRQA#

INTERNAL IDE

IDE/CD
/FDD
PAGE 29

ICH2

1394 Controller

FUNC 0: LAN, HUB-TO-PCI ,
PCI-TO-LPC BRIDGE
FUNC 1: IDE Controller
FUNC 2: USB Controller #1
FUNC 3: POWER MANAGEMENT
FUNC 4: USB Controller #2
FUNC 5: AC97 Audio Controller
FUNC 5: AC97 Modem Controller

TAB43AB22

CARDBUS
OZ6933

PAGE 25

IDSEL: AD17
MASTER 3
PIRQB#

IDSEL: AD18
MASTER 1
PIRQC#,
PIRQD#

Mini PCI
Connector

LAN Controller
RTL8100BL

PAGE 23

PAGE 26

PAGE 27

AC LINK

PAGE 20,21,22

LPC

LPC

MDC
Connector
PAGE 35

PCMCIA
SOCKET
PAGE 24

DC/DC POWER

USB X 3

+1.2VP POWER
PAGE 30

+1.25VS POWER

SIO
LPC 47N227
PAGE 31

LPT
PORT

EC/KBC

+1.5VS POWER

Audio Board

PC87591

+1.8VALW POWER

PAGE 35

PAGE 33

+2.5V POWER
+3VALW POWER

FIR/SIR Interface
PAGE 32

+5VALW POWER

KB/PS2 Interface

+12VALW POWER
CPU_CORE POWER
PAGE 39,40,41,42,43,44

Wireless
Keyboard/Mouse
LED Board Conn.

PAGE 36

BIOS
EC BUFFER
PAGE 34

LED Board Conn.
PAGE 35

Compal Electronics, Inc.
Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:

ATR60 COVER SHEET
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet

2

of

45

A

B

C

D

E

Voltage Rails

1

2

Power Plane

Description

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_VCC

Core voltage for CPU

ON

OFF

OFF

+1.2VP

1.2V switched power rail for CPU AGTL Bus

ON

OFF

OFF

+1.25VS

1.25V switched power rail

ON

OFF

OFF

+1.5VS

AGP 4X

ON

OFF

OFF

+1.8VALW

1.8V power rail

ON

ON

ON*

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+2.5V

2.5V power rail

ON

ON

OFF

+2.5VS

2.5V switched power rail

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V

3.3V power rail

ON

ON

OFF

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5V

5V power rail

ON

ON

OFF

+5VS

5V switched power rail

ON

OFF

OFF

+12VALW

12V always on power rail

ON

ON

ON*

RTCVCC

RTC power

ON

ON

ON

1

Board ID Table for AD channel
Vcc
Ra
Board ID0

0
1
2
3

3.3V +/- 5%
100K +/- 5%
Rb
0
47K +/- 5%
100K +/- 5%
NC

V AD_BID min
0V
0.921 V
1.453 V
2.5 V

V AD_BID typ
0V
1.055 V
1.650 V
3.3 V

V AD_BID max
0V
1.204 V
1.759 V
3.465 V

3.3V +/- 5%
100K +/- 5%
Rd
0
47K +/- 5%
100K +/- 5%
NC

V AD_BID min
0V
0.921 V
1.453 V
2.5 V

V AD_BID typ
0V
1.055 V
1.650 V
3.3 V

V AD_BID max
0V
1.204 V
1.759 V
3.465 V

2

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Vcc
Rc

External PCI Devices
Device

IDSEL#

Board ID1

REQ#/GNT#

Interrupts

VGA

0
1
2
3

PIRQA

C ardBus

AD20

2

PIRQA/PIRQB

LAN

A D17

3

PIRQB

Mini-PCI

AD18

1/4

PIRQC/PIRQD

1394

AD16

0

PIRQA

Real Board ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

3

EC SM Bus1 address

EC SM Bus2 address

Device

Address

Device

Address

Smart Battery

0001 011X b

MAX1617MEE

1001 110X b

EEPROM(24C16/02)

1010 000X b

OZ163

0011 0100 b

1011 000Xb

Smart Battery

0001 011X b

Docking

0011 011X b

DOT Board

XXXX XXXXb

(24C04)

ICH2 SM Bus address
4

Device

Address

Clock Generator ( ICS9238-50)

1101 0000

SDRAM Select ( 74HC4052 )

1010 0000

CPU Voltage VID select ( F3565 )

0110 111Xb

Board ID1
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3

Board ID0
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3

PCB Revision
0.1
1.0

3

4

Title

Compal Electronics, Ltd.
Notes & PIR

Size
B
Date:
A

B

C

D

Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

3

of

45

A

B

C

D

E

+5VS

3

+CPU_VCC

J1
K5
J4
J3
H3

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

6
6

ADSTB0#
ADSTB1#

L5
R5

ADSTB0#
ADSTB1#

6

ADS#

G1
AC1
V5
AA3
G2
AC3
J26
K25
K26
L25
BREQ0#
H6
D2
G4
F3
E3
E2
H2
V6
CPURST# AB25
J6
F1
G5
F4
AB2

ADS#
AP0#
AP1#
BINIT#
BNR#
IERR#
DP0#
DP1#
DP2#
DP3#
BREQ0#
BPRI#
LOCK#
HIT#
HITM#
DEFER#
DRDY#
MCERR#
RESET#
TRDY#
RS0#
RS1#
RS2#
RSP#

6

BNR#

6
6
6
6
6
6
6

BREQ0#
BPRI#
HLOCK#
HIT#
HITM#
DEFER#
DRDY#

6
6
6
6
6

2

CPURST#
HTRDY#
RS#0
RS#1
RS#2

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#

+CPU_VCC
12
12
6

H_BSEL0
H_BSEL1
DBSY#

20 CPU_PW RGD
20
CPUSLP#

AF26
D5
ITP_TDI
C1
ITP_TMS
F7
ITP_TRST#
E6
ITP_TCK
D4
1
2
C3
R82
@62_1%_0603
BSEL0
AD6
AD5
H5
AE25
CPU_PWRGD AB23
CPUSLP#
AB26
THERMDA
THERMDC
THERMTRIP#

1

AC6
AB5
AC4
Y6
AA5
AB4

B3
C4
A2

CONTROL GROUP

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
SKTOCC#
TDO
TDI
TMS
TRST#
TCK
PROCHOT#

MISC
HOST CLK

BSEL0
BSEL1
DBSY#
DBR#
PWRGOOD
SLP#

LEGACY CPU

THERMDA
THERMAL DIODE
THERMDC
THERMTRIP#

E21
G25
P26
V21

DBI0#
DBI1#
DBI2#
DBI3#

6
6
6
6

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

E22
K22
R22
W22
F21
J23
P23
W23

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

6
6
6
6
6
6
6
6

BCLK0
BCLK1

AF22
AF23

CLK_HCLK 12
CLK_HCLK# 12

ITPCLK0
ITPCLK1

AC26
AD26

A20M#
FERR#
IGNNE#
INTR/LINT0
NMI/LINT1

C6
B6
B2
D1
E5

INIT#
STPCLK#
SMI#

W5
Y4
B5

A20M#
FERR#
IGNNE#
INTR
NMI

2

DBI0#
DBI1#
DBI2#
DBI3#

2
1K

NC
VCC
DXP
DXN
NC
ADD1
GND
GND

NC
STBY
SMBCLK
NC
SMBDATA
ALERT
ADD0
NC

16
15
14
13
12
11
10
9

4

EC_SMC2 28,33
EC_SMD2 28,33

ATF#

1

1
R83

THERMDA
THERMDC

R87
1K

MAX1617/MAX6654

+5VS

+CPU_VCC

R392

R394

56

@470

3

THERMTRIP#

C

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

+5VS

2200PF

1
2
3
4
5
6
7
8

E

6
6
6
6
6

DATA GROUP

U4
C191

B

BPM0#
2
51_1%_0603
BPM1#
2
51_1%_0603
BPM2#
2
51_1%_0603
BPM3#
2
51_1%_0603
BPM4#
2
51_1%_0603
BPM5#
2
51_1%_0603

1
R305
1
R306
1
R318
1
R307
1
R319
1
R320

ADDR GROUP

200
1617VCC

2

8P4R-1K

R90
C192
.1UF_X5R

1

ITP_TMS
ITP_TRST#
ITP_TCK
ITP_TDI

B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24

2

8
7
6
5

Northwood

HD#[0..63] 6

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

2

RP75

1
2
3
4

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#

1

4

HD#[0..63]

U26A

K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1

2

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

1

HA#[3..31]

2

HA#[3..31]

1

6

2

CPURST#
2
51_1%_0603
FERR#
2
56
2 CPU_PWRGD
300_1%_0603
BREQ0#
2
51_1%_0603

1
R340
1
R387
1
R359
1
R363

1

+CPU_VCC

3

1

MAINPWON 39,41,43

Q46
@2SC2411K

PAD3

PAD2

PAD7

1

1

1

EMI PAD-4.5X3.2

EMI PAD-4.5X3.2

EMI PAD-4.5X3.2

EMI PAD-4.5X3.2

PAD8

A20M#
FERR#
IGNNE#
INTR
NMI

PAD4

1

PAD9

PAD6

PAD5

1

1

1

1

EMI PAD-4.5X3.2

EMI PAD-4.5X3.2

EMI PAD-4.5X3.2

EMI PAD-4.5X3.2

2

20
20
20
20
20

CPUINIT# 20
STPCLK# 20
SMI#
20

1

mPGA478
SELPSB[1:0]

STSEM BUS FREQUENCY

00

100MHZ

01

RESERVED

10

RESERVED

11

RESERVED

Compal Electronics, Inc.
Title
PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

D

Pentium 4/Northwood Processor in mPGA478
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

4

of

45

A

B

C

D

+CPU_VCC

PROPRIETARY NOTE
+VCCA

+CPU_VCC
C363

CPU_GTLREF
H_GTLREF

1
R360
1
R63

2 COMP0
51.1_1%_0603
2 COMP1
51.1_1%_0603

1

+1.2VP

2

1
R323
@0

L24
P1

A22
A7
AD2
AD3
AE21
AF3
AF24
AF25

COMP0
COMP1

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

1
2

1
2

2

.1UF_X5R

1

C400

2

1
2

1
2

1
2

1
2

1
2

1
2

.1UF_X5R

C401
.1UF_X5R

1UF_0603

1

C360

2

1UF_0603

1

C358

2

1UF_0603

1

C121

2

1
2

1

1UF_0603

2

1
2

1

C129

C359
1UF_0603

C97

1

1

C96

C98

2

2

10UF_1206 10UF_1206 10UF_1206

C64

1

C161

1

C160

1

C159

1

C158

1

C99

1

+CPU_VCC

C80

AF9
B11
B13
B15
B17
B19
B7
B9
C10
C12
C14
C16
C18
C20
C8
D11
D13
D15
D17
D19
D7
D9
E10
E12
E14
E16
E18
E20
E8
F11
F13
F15
F17
F19
F9

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AE5
AE4
AE3
AE2
AE1

VID0
VID1
VID2
VID3
VID4

AF4

VCCVID

Y5
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Northwood

POW ER, GROUND AND NC

2

2

2

2

2

2

10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4

C186

1

C166

1

C145

1

C374

1

C117

1

C105

1

+CPU_VCC

C65
+1.2VP

1

2

2

2

2

2

10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206

C155

C174

2

1

C135

1

C118

1

C106

1

C81

1

+CPU_VCC

C352
1UF_0603

C188

2

2

2

2

2

10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206

C447

C449

1

C434

1

C428

1

C413

1

C406

1

+CPU_VCC

C454

2

2

2

2

2

10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206

C380

C407

C414

C430

C435

C377

1

+CPU_VCC

3

2

+3VS
RP54

+CPU_VCC

+ C470
470U_E
2.5V

CPU_VID01
CPU_VID12
CPU_VID23
CPU_VID34
+ C484
470U_E
2.5V

+ C474
470U_E
2.5V

+ C473
470U_E
2.5V

+ C472
330U_E
2.5V

+ C495
470U_E
2.5V

+ C494
470U_E
2.5V

+ C471
470U_E
2.5V

+ C483
470U_E
2.5V

8
7
6
5

8P4R-1K
CPU_VID42
1
R317
1K

+ C475
330U_E
2.5V

+CPU_VCC
44

+ C345
470U_E
2.5V

+ C350
470U_E
2.5V

+ C348
470U_E
2.5V

+ C347
470U_E
2.5V

+ C346
470U_E
2.5V

CPU_VID[0..4]

VID[0..4]

+ C349
330U_E
2.5V

1

Compal Electronics, Inc.
Title

Pentium 4/Northwood Processor in mPGA478
Size
B
Date:

B

4

mPGA478

mPGA478

A

D6
D8
E1
E11
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5
F8
G21
G24
G3
G6
H1
H23
H26
H4
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C368

10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206 10UF_1206

2

GTLREF
GTLREF
GTLREF
GTLREF

C399

1

AA21
AA6
F20
F6

.1UF_X5R

2

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12

C398

1

220PF

AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25

.1UF_X5R

2

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12

C397

1

C405

+CPU_VCC

.1UF_X5R

2

220PF

1

C440

2

1

1UF_0603

2

C424

1

100_1%_0603

1

R358

2

2

H_GTLREF

2

1

R354
49.9_1%_0603

1UF_0603

1

2

+CPU_VCC

C126

2

220PF

.1UF_X5R

2

C404

U26C

C366

+CPU_VCC

1

220PF

1

C439

2

1

1UF_0603

2

1

C411

1

100_1%_0603

2

R361

C396

2

CPU_GTLREF

2

1

R366
49.9_1%_0603

1UF_0603

1

2

+CPU_VCC
3

.1UF_X5R

2

+CPU_VCC

POWER,
GROUND,
RESERVED
SIGNALS

C120

1

10P8R-4.7K

.1UF_X5R

2

TESTHI12

C365

+CPU_VCC

2

+CPU_VCC

1

+CPU_VCC

10
9
8
7
6

C367

2

1
2
3
4
5

Northwood

.1UF_X5R

+CPU_VCC

1

RP53
TESTHI8
TESTHI9
TESTHI10
TESTHI11

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

C364

2

10P8R-4.7K

A10
A12
A14
A16
A18
A20
A8
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7

D10
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD1
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE26
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
B4
B8
C11
C13
C15
C17
C19
C2
C22
C25
C5
C7
C9
D12
D14
D16
D18
D20
D21
D24
D3

1

+CPU_VCC

TESTHI7
TESTHI6
TESTHI5
TESTHI4

VCCIOPLL
VCCSENSE
VSSSENSE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2

+CPU_VCC

10
9
8
7
6

AE23
A5
A4

PLL ANALOG VOLTAGE

1

1
2
3
4
5

VCCA
VSSA

2

RP55
TESTHI0
TESTHI1
TESTHI2
TESTHI3

AD20
AD22

1

4

C341

150U_D
1UF_0603
VSSA
150U_D
VCCIOPLL

2

2

+

1
2
L32
4.7UH_0805

1

U26B

1

C351
+

2

1

1
2
L33
4.7UH_0805

E

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

5

of

45

A

B

C

D

E

MC-1/3(GTL+,AGP,HUB)

AD4
AE6
AE11
AC15
AD3
AE7
AD11
AC16
AD5
AG4
AH9
AD15

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
DBI0#
DBI1#
DBI2#
DBI3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
DBI0#
DBI1#
DBI2#
DBI3#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

U6
T7
R7
U5
U2

RS#0
RS#1
RS#2

W2
W7
W6

GAD[0..31]

HREQ#[0..4]
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
RS#0
RS#1
RS#2
RS#[0..2]

HREQ#[0..4] 4

ADSTB0#
ADSTB1#

R5
N6

RS#[0..2] 4
ADSTB0# 4
ADSTB1# 4

BCLK#
BCLK

K8
J8

CLK_GHT# 12
CLK_GHT 12

CPURST#
HLOCK#
DEFER#
ADS#
BNR#
BPRI#
DBSY#
DRDY#
HIT#
HITM#
HTRDY#
BR0#

AE17
W5
Y4
V3
W3
Y7
V5
V4
Y5
Y3
U7
V7

CPURST#
HLOCK#
DEFER#
ADS#
BNR#
BPRI#
DBSY#
DRDY#
HIT#
HITM#
HTRDY#
BREQ0#

RCOMP0
RCOMP1
SWNG0
SWNG1

AC2
AC13
AA7
AD13

HVREF
HVREF
HVREF
HVREF
HVREF

M7
R8
Y8
AB11
AB17

RCOMP0
RCOMP1

R44
R45
SWNG

4
4
4
4
4
4
4
4
4
4
4
4

13
13
13
13

GC/BE#0
GC/BE#1
GC/BE#2
GC/BE#3

13
13
13
13
13
13
13
13
13

GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GPAR
GREQ#
GGNT#
PIPE#

13
13
13
13

AD_STB0
AD_STB0#
AD_STB1
AD_STB1#

13
13

RBF#
WBF#

R27
R28
T25
R25
T26
T27
U27
U28
V26
V27
T23
U23
T24
U24
U25
V24
Y27
Y26
AA28
AB25
AB27
AA27
AB26
Y23
AB23
AA24
AA25
AB24
AC25
AC24
AC22
AD24

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31

V25
V23
Y25
AA23

G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3

GFRAME#
GDEVSEL#
GIRD Y#
GTRDY#
GSTOP#
GPAR
GREQ#
GGNT#
PIPE#

Y24
W28
W27
W24
W23
W25
AG24
AH25
AF22

G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
PIPE#

AD_STB0
AD_STB0#
AD_STB1
AD_STB1#
SBSTB
SBSTB#

R24
R23
AC27
AC28
AF27
AF26

AD_STB0
AD_STB#0
AD_STB1
AD_STB#1
SB_STB
SB_STB#

RBF#
W BF#

AE22
AE23

RBF#
WBF#

AGPREF
1
R48

2 22
2 22

1
1

U21C

GAD[0..31]
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

12 CLK_AGP_MCH

AA21
2 GRCOMP AD25
40.2_1%_0603 AD26
AD27

CLK_66M_MCH

P22

TESTIN#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

AGP

HOST

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

13

HA#[3..31] 4

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

H26
G9
G10
G16
G17
H6
H7
J23
H27
K23
K25
J25

1

AC18
AC20
AC21
AC23
AC26
AD6
AD8
AD10
AD12
AD14
AD16
AD19
AD22
AE1
AE4
AE18
AE20
AE29
HL[0..10]

HUB

AGPREF
GRCOMP
NC
NC
66IN

HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HIREF
HISTB
HISTB#
HLRCOMP

HL[0..10] 20

HL0
P25
HL1
P24
HL2
N27
HL3
P23
HL4
M26
HL5
M25
HL6
L28
HL7
L27
HL8
M27
HL9
N28
HL10
M24
H UBREF
P26
HL_STB
N25
HL_STB#
N24
+GMCH_HLCOMP
P27
1
R56

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

AH28
AH27
AG28
AG27
AE28
AE27
AE24
AE25

ST0
ST1
ST2
RSTIN#

AG25
AF24
AG26
J27

2

2
40.2_1%_0603

ST0
ST1
ST2

HUBREF 20
HL_STB
20
HL_STB# 20
+1.8VS

ST0
13
ST1
13
ST2
13
PCIRST# 13,20,23,24,25,26,27,31,33

BROOKDALE
R65
10

MCH_GTLREF

3

+1.5VS
C151
1

3

4
4
4
4
4
4
4
4
4
4
4
4

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HA#[3..31]
T4
T5
T3
U3
R3
P7
R2
P4
R6
P5
P3
N2
N7
N3
K4
M4
M3
L3
L5
K3
J2
M5
J3
L2
H4
N5
G2
M6
L7

10PF

+1.5VS
R350
1K_1%_0603

13

AGPREF

AGPREF

R351
1K_1%_0603
2

C90
0.1UF_X5R

C409
0.1UF_X5R

1

+CPU_VCC

+1.8VS
ST0
C71
0.01UF

2

1
2

R49

100_1%_0603

C104

C130

0.1UF_X5R

0.1UF_X5R

0.1UF_X5R

0.1UF_X5R

R206

C221

0.1UF_X5R

0.1UF_X5R

1

0.01UF

ST1

0.1UF_X5R
2

C88

C141

150_1%_0603

1
2K
1
@2K
1
100K
1
6.8K
1
6.8K
1
6.8K

2
R46
GDEVSEL#2
R54
GSTOP# 2
R51
GFRAME# 2
R50
GREQ#
2
R28
GGNT#
2
R29
SBSTB
2
R36
RBF#
2
R31
PIPE#
2
R22
W BF#
2
R32
AD_STB0
2
R58
AD_STB1
2
R47

4

150_1%_0603
1

C87

C140

2

0.1UF_X5R

1

0.1UF_X5R

2

MCH_GTLREF

H UBREF

1

C94

2

1
C70

1

2

49.9_1%_0603

R55

2

C222

SWNG
R69

4

2
R30
2
R38
GPAR
2
R53
AD_STB0# 2
R57
AD_STB1# 2
R40
SBSTB#
2
R26
ST1

R207

2

2
1

300_1%_0603

1

R33

+CPU_VCC

1
6.8K
1
6.8K
1
6.8K
1
6.8K
1
6.8K
1
6.8K
1
6.8K
1
@6.8K
1
6.8K
1
6.8K
1
6.8K
1
@6.8K
1
@6.8K

GIRD Y#

1

BROOKDALE

GTRDY# 2
R52

2

2

AA2
AB5
AA5
AB3
AB4
AC5
AA3
AA6
AE3
AB7
AD7
AC7
AC6
AC3
AC8
AE2
AG5
AG2
AE8
AF6
AH2
AF3
AG3
AE5
AH7
AH3
AF4
AG8
AG7
AG6
AF8
AH5
AC11
AC12
AE9
AC9
AE10
AD9
AG9
AC10
AE12
AF10
AG11
AG10
AH11
AG12
AE13
AF12
AG13
AH13
AC14
AF14
AG14
AE14
AG15
AG16
AG17
AH15
AC17
AF16
AE15
AH17
AD17
AE16

1

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

1

U21A

HD#[0..63]

1 2

HD#[0..63]

2

4

2
R37

150_1%_0603

1
@10K

Compal Electronics, Inc.
Title
PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

D

Brookdale-1/3(GTL+,AGP,HUB)
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

6

of

45

A

B

C

D

E

MCH-2/3(SDRAM)

2

2 SRCOMP
30.1_1%_0603

1
R75

0

2
1

1

SDREF

2

SRCOMP

J9
J21

SDREF
SDREF

DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12

SBS0
SBS1

G12
G13

DDR_SBS0
DDR_SBS1

SCK0
SCK#0
SCK1
SCK#1
SCK2
SCK#2
SCK3
SCK#3
SCK4
SCK#4
SCK5
SCK#5

E14
F15
J24
G25
G6
G7
G15
G14
E24
G24
H5
F5

SRAS#
SCAS#
SWE#

F11
G8
G11

DDR_SRAS#
DDR_SCAS#
DDR_SWE#

SCKE0
SCKE1
SCKE2
SCKE3

G23
E22
H23
F23

DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3

SCS#0
SCS#1
SCS#2
SCS#3

E9
F7
F9
E7

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8

F26
C26
C23
B19
D12
C8
C5
E3
E15

DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDQS8

SCB0
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7

C16
D16
B15
C14
B17
C17
C15
D14

DDR_CB0
DDR_CB1
DDR_CB2
DDR_CB3
DDR_CB4
DDR_CB5
DDR_CB6
DDR_CB7

RCVENIN#
RCVENOUT#

G3
H3

0.1UF_X5R

DDR_SMA[0..12] 9

1

DDR_SBS0 9
DDR_SBS1 9
DDR_CLK0 9
DDR_CLK#0 9
DDR_CLK1 9
DDR_CLK#1 9
DDR_CLK2 9
DDR_CLK#2 9
DDR_CLK3 10
DDR_CLK#3 10
DDR_CLK4 10
DDR_CLK#4 10
DDR_CLK5 10
DDR_CLK#5 10

R CVIN#
RCVOUT#

1
R81

C172
2

C173
3

J28

DDR_SMA[0..12]
E12
F17
E16
G18
G19
E18
F19
G21
G20
F21
F13
E20
G22

SMAA0
SMAA1
SMAA2
SMAA3
SMAA4
SMAA5
SMAA6
SMAA7
SMAA8
SMAA9
SMAA10
SMAA11
SMAA12

DDR_SRAS# 9
DDR_SCAS# 9
DDR_SWE# 9
DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3

9
9
10
10

DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDQS8

9
9
9
9
9
9
9
9
9

DDR_CB0
DDR_CB1
DDR_CB2
DDR_CB3
DDR_CB4
DDR_CB5
DDR_CB6
DDR_CB7

0

9
9
10
10

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

2

9
9
9
9
9
9
9
9

2

2

1
R80

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7
SMD8
SMD9
SMD10
SMD11
SMD12
SMD13
SMD14
SMD15
SMD16
SMD17
SMD18
SMD19
SMD20
SMD21
SMD22
SMD23
SMD24
SMD25
SMD26
SMD27
SMD28
SMD29
SMD30
SMD31
SMD32
SMD33
SMD34
SMD35
SMD36
SMD37
SMD38
SMD39
SMD40
SMD41
SMD42
SMD43
SMD44
SMD45
SMD46
SMD47
SMD48
SMD49
SMD50
SMD51
SMD52
SMD53
SMD54
SMD55
SMD56
SMD57
SMD58
SMD59
SMD60
SMD61
SMD62
SMD63

1

1

G28
F27
C28
E28
H25
G27
F25
B28
E27
C27
B25
C25
B27
D27
D26
E25
D24
E23
C22
E21
C24
B23
D22
B21
C21
D20
C19
D18
C20
E19
C18
E17
E13
C12
B11
C10
B13
C13
C11
D10
E10
C9
D8
E8
E11
B9
B7
C7
C6
D6
D4
B3
E6
B5
C4
E5
C3
D3
F4
F3
B2
C2
E2
G5

DDR-MEMORY

DDR_SDQ0
DDR_SDQ1
DDR_SDQ2
DDR_SDQ3
DDR_SDQ4
DDR_SDQ5
DDR_SDQ6
DDR_SDQ7
DDR_SDQ8
DDR_SDQ9
DDR_SDQ10
DDR_SDQ11
DDR_SDQ12
DDR_SDQ13
DDR_SDQ14
DDR_SDQ15
DDR_SDQ16
DDR_SDQ17
DDR_SDQ18
DDR_SDQ19
DDR_SDQ20
DDR_SDQ21
DDR_SDQ22
DDR_SDQ23
DDR_SDQ24
DDR_SDQ25
DDR_SDQ26
DDR_SDQ27
DDR_SDQ28
DDR_SDQ29
DDR_SDQ30
DDR_SDQ31
DDR_SDQ32
DDR_SDQ33
DDR_SDQ34
DDR_SDQ35
DDR_SDQ36
DDR_SDQ37
DDR_SDQ38
DDR_SDQ39
DDR_SDQ40
DDR_SDQ41
DDR_SDQ42
DDR_SDQ43
DDR_SDQ44
DDR_SDQ45
DDR_SDQ46
DDR_SDQ47
DDR_SDQ48
DDR_SDQ49
DDR_SDQ50
DDR_SDQ51
DDR_SDQ52
DDR_SDQ53
DDR_SDQ54
DDR_SDQ55
DDR_SDQ56
DDR_SDQ57
DDR_SDQ58
DDR_SDQ59
DDR_SDQ60
DDR_SDQ61
DDR_SDQ62
DDR_SDQ63

+1.25VS

U21B

DDR_SDQ[0..63]

9 DDR_SDQ[0..63]

C187
@47PF
3

0.1UF_X5R
BROOKDALE

4

4

Compal Electronics, Inc.
Title
PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

D

Brookdale-2/3(SDRAM)
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

7

of

45

A

B

C

D

E

MCH-3/3(Power)
L13
4.7UH_0805
2
2

U21D

3

+CPU_VCC

4

M8
U8
AA9
AB8
AB18
AB20
AC19
AD18
AD20
AE19
AE21
AF18
AF20
AG19
AG21
AG23
AJ19
AJ21
AJ23

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

AB19
AB22
AC1
AC4
AF21
AF25
AG1
AG18
AG20
AG22
AH19
AH21
AH23
AJ3
AJ5
AJ7
AJ27
AJ17

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

A3
A7
A11
A15
A19
A23
A27
D5
D9
D13
D17
D21
E1
E4
E26
E29
F8
F12
F16
F20
F24
G26
H9
H11
H13
H15
H17
H19
H21
J1
J4
J6
J22
J26
J29
K5
K7
K27
L1
L4
L6
L8
L22
L24
L26
M23
N1
N4
N8
N13
N15
N17
N22
N29
P6
P8
P14
P16
R1
R4
R13
R15
R17
R26
T6
T8
T14
T16
T22
U1
U4
U15
U29
V6
V8
V22
W1
W4
W8
W26
Y6
Y22
AA1
AA4
AA8
AA29
AB6
AB9
AB10
AB12
AB13
AB14
AB15
AB16
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AJ9
AJ11
AJ13
AJ15

C127

B

+1.5VS
+1.5VS

L14
4.7UH_0805

33U_D

1

C131

33U_D

+1.8VS

+

C144

C138

C152

C156

C139

C157

22UF_10V_1206

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

C57

C53

C76

C86

C75

C114

C150

C89

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

+CPU_VCC

C33
+
22UF_10V_1206

2

+2.5V

C185

+

150UF_E
6.3V

C189

C164

C169

C170

C163

C171

C168

C167

C193

C194

C195

C198

C197

C196

4.7UF_0805

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

C66

C115

C128

C143

C113

C69

C119

C77

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

+1.5VS

C49

C46
+

+
150UF_E
6.3V

22UF_10V_1206

3

4

Compal Electronics, Inc.
Title
PROPRIETARY NOTE

BROOKDALE

A

VSSA0
VSSA1

1

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

VSSHA2
VSSGA2

U13
U17

1
1

2

A5
A9
A13
A17
A21
A25
C1
C29
D7
D11
D15
D19
D23
D25
F6
F10
F14
F18
F22
G1
G4
G29
H8
H10
H12
H14
H16
H18
H20
H22
H24
J5
J7
K6
K22
K24
K26
L23

VCCA0
VCCA1

1

2

VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8

T13
T17

2

+2.5V

L25
L29
M22
N23
N26

VCCHA1
VCCGA1

+

+1.8VS

VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5

+

1

R22
R29
U22
U26
W22
W29
AA22
AA26
AB21
AC29
AD21
AD23
AE26
AF23
AG29
AJ25
N14
N16
P13
P15
P17
R14
R16
T15
U14
U16

POWER/GND

+1.5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

D

Brookdale-3/3(Power)
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

8

of

45

A

B

C

D

E

F

+2.5V

G

H

+2.5V

DDR_DQ[0..63]
DDR_F_CB[0..7]
DDR_DQS[0..8]

SDREF_DIMM

DDR_SDQ1
DDR_SDQ5
DDR_SDQS0
DDR_SDQ6
1

Layout note
DDR_SDQ8

Place these resistor
closely DIMM0,
all trace length<750mil

DDR_SDQ7
DDR_SDQ2
DDR_SDQ3
DDR_SDQ15
DDR_SDQS1
DDR_SDQ12
DDR_SDQ13
DDR_SDQ16
DDR_SDQ20
DDR_SDQ14
DDR_SDQ9

2

DDR_SDQ11
DDR_SDQ10
DDR_SDQ21
DDR_SDQ17
DDR_SDQ19
DDR_SDQ18
DDR_SDQ22
DDR_SDQS2
DDR_SDQ25
DDR_SDQ28
DDR_SDQ24
DDR_SDQ23
DDR_SDQS3

3

DDR_SDQ29

1
R434
1
R197

2
22
2
22

DDR_DQ0

DDR_SDQ30

DDR_DQ4

DDR_SDQ26

1
R433
1
R196

2
22
2
22

DDR_DQ1

DDR_SDQ31

DDR_DQ5

DDR_SDQ27

1
R195
1
R435

2
22
2
22

DDR_DQS0
DDR_DQ6

DDR_CB6

1
R437
1
R193

2
22
2
22

DDR_DQ8

DDR_CB5

DDR_DQ7

DDR_CB4

1
R436
1
R194

2
22
2
22

DDR_DQ2

DDR_CB0

DDR_DQ3

DDR_CB1

DDR_CB7

1
R440
1
R190

2
22
2
22

DDR_DQ15

1
R438
1
R192

2
22
2
22

DDR_DQ12

1
R187
1
R441

2
22
2
22

DDR_DQ16

DDR_SDQ36

DDR_DQ20

DDR_SDQ32

DDR_DQS1

DDR_DQ13

DDR_CB2

DDR_DQ30
JP17
DDR_DQ26

2
22
2
22

DDR_DQ31

1
R452
1
R174

2
22
2
22

DDR_F_CB7

1
R177
1
R449

2
22
2
22

DDR_F_CB5

1
R176
1
R450

2
22
2
22

DDR_F_CB0

2
22
2
22

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

DDR_DQ5
DDR_DQ4

DDR_DQ27

DDR_DQS0
DDR_DQ3
DDR_DQ7
DDR_DQ13

DDR_F_CB6
DDR_DQ9
DDR_DQS1
DDR_DQ10
DDR_DQ11

DDR_F_CB4
7
7

DDR_CLK1
DDR_CLK#1

DDR_F_CB1
DDR_DQ16
DDR_DQ21

DDR_F_CB2
DDR_DQS8

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_DQS2
DDR_DQ18
DDR_DQ23
DDR_DQ28

DDR_CB3

2
22
2
22

DDR_DQ14
DDR_DQ9

DDR_SDQ37

1
R188
1
R189

2
22
2
22

DDR_DQ11

DDR_SDQ34

DDR_DQ10

DDR_SDQ33

1
R186
1
R442

2
22
2
22

DDR_DQ21

DDR_SDQ39

1
R444
1
R184

2
22
2
22

DDR_DQ19

DDR_SDQ44

DDR_DQ18

DDR_SDQ35

1
R443
1
R185

2
22
2
22

DDR_DQ22

DDR_SDQS5

DDR_DQS2

DDR_SDQ40

1
R446
1
R182

2
22
2
22

DDR_DQ25

DDR_SDQ41

DDR_DQ28

DDR_SDQ45

1
R445
1
R183

2
22
2
22

DDR_DQ24

DDR_SDQ46

DDR_DQ23

DDR_SDQ42

1
R180
1
R181

2
22
2
22

DDR_DQS3
DDR_DQ29

2
22
2
22

1
R178
1
R448

1
R451
1
R175

DDR_SDQS8

1
R439
1
R191

DDR_DQ17

1
R179
1
R447

DDR_SDQS4

DDR_SDQ38

DDR_SDQ43
DDR_SDQ47

1
R173

2
22

DDR_F_CB3

1
R162
1
R163

2
22
2
22

DDR_DQ36

DDR_DQ29
DDR_DQS3
DDR_DQ32

DDR_DQ30
DDR_DQ31
DDR_F_CB5
DDR_F_CB0

1
R161
1
R462

2
22
2
22

DDR_DQS4
DDR_DQ37

DDR_DQS8
DDR_F_CB6

1
R160
1
R463

2
22
2
22

DDR_DQ34

DDR_F_CB3

1
R159
1
R464

2
22
2
22

DDR_DQ39

1
R158
1
R465

2
22
2
22

DDR_DQ44

1
R156
1
R467

2
22
2
22

DDR_DQS5

1
R157
1
R466

2
22
2
22

DDR_DQ41
DDR_DQ45

DDR_DQ32
DDR_DQ36

1
R468
1
R155

2
22
2
22

DDR_DQ46

DDR_DQS4
DDR_DQ34

1
R469
1
R154

2
22
2
22

DDR_DQ43

DDR_DQ33

DDR_DQ38

7
7

DDR_CLK0
DDR_CLK#0

7

DDR_CKE1

DDR_CKE1
DDR_F_SMA12
DDR_F_SMA9
DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1

DDR_DQ35

DDR_DQ40
7

DDR_SCS#0

DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE#
DDR_SCS#0

DDR_DQ42
DDR_DQ39
DDR_DQ44
DDR_DQ41
DDR_DQS5

DDR_DQ47

DDR_DQ42
DDR_DQ47
7 DDR_SDQ[0..63]
7 DDR_CB[0..7]
7 DDR_SDQS[0..8]

DDR_SDQ[0..63]
DDR_CB[0..7]
DDR_SDQS[0..8]

DDR_SDQ49

1
R470
1
R153

2
22
2
22

DDR_DQ49
DDR_DQ48

DDR_DQ48
DDR_DQ53

DDR_SDQS6 1
R151
1
R152

2
22
2
22

DDR_DQS6

DDR_DQS6
DDR_DQ55

DDR_DQ53

DDR_DQ50
DDR_DQ58

DDR_SDQ54

1
R472
1
R471

2
22
2
22

DDR_DQ54

DDR_DQ57
DDR_DQS7

1
R473
1
R150

2
22
2
22

DDR_DQ51

DDR_SDQ48

DDR_SDQ53
DDR_SDQ60
DDR_SDQ50
DDR_SDQ56
DDR_SDQ58

DDR_SDQ61
DDR_SDQ57

1
R474
1
R149

2
22
2
22

DDR_DQ60

1
R475
1
R148

2
22
2
22

DDR_DQ56

1
R476
1
R147

2
22
2
22

DDR_DQ61

DDR_DQ50
DDR_SDQ52
DDR_SDQ51
DDR_DQ58
DDR_SDQ55

DDR_DQ52
DDR_DQ62
DDR_DQ59
10,12,21 SMB_DATA
10,12,21 SMB_CLK

DDR_DQ55

+3VS

DDR_DQ57

DDR_SDQS7

DDR_SDQ59
DDR_SDQ63

1
R145
1
R146

1
R144
1
R477

2
22
2
22

DDR_DQ62

2
22
2
22

DDR_DQ59

DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DIMM0

DDR_DQS7

Bottom side

B

DDR_DQ1
DDR_DQ0

2
R497

C571

1
0

SDREF

.1UF_X5R

DDR_DQ6
DDR_SMA[0..12]

7 DDR_SMA[0..12]

DDR_DQ2
DDR_DQ8
DDR_DQ12
DDR_DQ14
DDR_DQ15

DDR_DQ20
DDR_DQ17
DDR_DQ22
DDR_DQ19
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_DQ27
DDR_F_CB4
DDR_F_CB1
DDR_F_CB2
DDR_F_CB7

DDR_SMA9 1
R171
DDR_SMA12 1
R172

2
10
2
10

DDR_F_SMA9

DDR_SMA6 1
R455
DDR_SMA8 1
R454

2
10
2
10

DDR_F_SMA6

DDR_SMA11 1
R453
DDR_SMA7 1
R170

2
10
2
10

DDR_F_SMA11

DDR_SMA5 1
R169
DDR_SMA4 1
R456

2
10
2
10

DDR_F_SMA5

DDR_SMA1 1
R167
DDR_SMA3 1
R168

2
10
2
10

DDR_F_SMA1

DDR_SMA10 1
R166
DDR_SMA2 1
R457

2
10
2
10

DDR_F_SMA10

R458
DDR_SMA0 1

10
2

1

DDR_F_SMA12

DDR_F_SMA8

DDR_F_SMA7

DDR_F_SMA4

DDR_F_SMA3

DDR_F_SMA2

DDR_F_SMA0
DDR_F_SMA[0..12]

10 DDR_F_SMA[0..12]

Place these resistor
closely DIMM0,
all trace length<=750mil

DDR_CKE0 7

DDR_F_SMA11
DDR_F_SMA8
DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0

Layout note

DDR_F_SBS1
DDR_F_SRAS#
DDR_F_SCAS#
DDR_SCS#1

Place these resistor
closely DIMM0,
all trace length Max=1.3"

DDR_SCS#1 7

+1.25VS

DDR_DQ37
DDR_DQ33
DDR_DQ38
DDR_DQ35
DDR_DQ45
DDR_DQ40

RP12
DDR_CKE1 1
DDR_CKE0 2

4P2R_56
4
3

RP11
DDR_SCS#0 1
DDR_SCS#1 2

4P2R_56
4
3

3

DDR_DQ46
DDR_DQ43
DDR_CLK#2 7
DDR_CLK2 7
DDR_DQ49
DDR_DQ52
DDR_DQ54
DDR_DQ51
DDR_DQ60

Layout note

DDR_DQ56

Place these resistor
closely DIMM0,
all trace length<=750mil

DDR_DQ61
DDR_DQ63

7

DDR_SWE#

DDR_SWE#

7

DDR_SBS0

DDR_SBS0

7

DDR_SCAS#

7

DDR_SRAS#

DDR_SBS1

1
R164
1
R165
DDR_SCAS# 1
R461
DDR_SRAS# 1
R460

2
10
2
10
2
10
2
10

R459
DDR_SBS1
1

10
2

DDR_F_SWE#
DDR_F_SBS0
DDR_F_SCAS#
DDR_F_SRAS#

DDR_F_SBS1

DDR_F_SWE# 10
DDR_F_SBS0 10
DDR_F_SCAS# 10
DDR_F_SRAS# 10

4

DDR_F_SBS1 10

Compal Electronics, Inc.
Title

C

D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
E

F

2

Layout note
DDR_CKE0

7

DDR_DQ63
PROPRIETARY NOTE

A

VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS

DDR-SODIMM_200_Normal

4

DDR_SDQ62

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

1

DDR_SDQ4

2

DDR_SDQ0

DDR_DQ[0..63] 10
DDR_F_CB[0..7] 10
DDR_DQS[0..8] 10

DDR-SODIMM SLOT1
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002
G

Sheet

9
H

of

45

A

B

C

D

E

+2.5V
+1.25VS

1

4P2R_56
4
3

RP40
1
2

4P2R_56
4
3

4
3

RP98
DDR_DQ13 1
DDR_DQ7 2

4P2R_56
4
3

4
3

RP99
DDR_DQS1 1
DDR_DQ9 2

4P2R_56
4
3

DDR_DQ1
DDR_DQ0

RP39
1
2

4P2R_56
4
3

RP37
DDR_DQ14 1
DDR_DQ15 2

4P2R_56
4
3

RP38
DDR_DQ8 1
DDR_DQ12 2

4P2R_56
4
3

RP36
DDR_DQ17 1
DDR_DQ20 2

4P2R_56
4
3

RP105
DDR_DQ31 1
DDR_DQ30 2

4
3
RP106

RP107

RP33
4
3
RP31

4P2R_56
4
3

RP100
DDR_DQ11 1
DDR_DQ10 2

RP101
DDR_DQ21 1
DDR_DQ16 2

3

RP32

RP97
DDR_DQ3 1
DDR_DQS0 2

DDR_DQ6
DDR_DQ2

2

4
3

4
3
RP108
4
3
RP28
4
3
RP30
4
3
RP27
4
3
RP111

4P2R_56
4
3

4
3
RP29

4P2R_56
4
3

4
3
RP112

RP35
DDR_DQ22 1
DDR_DQ19 2

4P2R_56
4
3

4
3

RP102
DDR_DQ18 1
DDR_DQS2 2

4P2R_56
4
3

4
3

RP104
DDR_DQS3 1
DDR_DQ29 2

4P2R_56
4
3

4
3

RP103
DDR_DQ28 1
DDR_DQ23 2

RP113

RP114

RP115

4P2R_56
4
3

4
3

Layout note
Place these resistor
closely DIMM1,
all trace
length<=800mil

4P2R_56
1
2

DDR_DQ24
DDR_DQ25

4P2R_56
1
2

DDR_DQ26
DDR_DQ27

4P2R_56
1
2

DDR_F_CB0
DDR_F_CB5

4P2R_56
1
2

DDR_F_CB6
DDR_DQS8

RP26
4
3

4P2R_56
1
2

RP116
4
3

4
3
RP25

DDR_F_SMA[0..12]

SDREF_DIMM

DDR_F_CB[0..7] 9

JP18

DDR_DQS[0..8] 9
DDR_DQ5
DDR_DQ4

DDR_DQ[0..63] 9
DDR_F_SMA[0..12] 9

DDR_DQS0
DDR_DQ3

DDR_DQ53
DDR_DQ48

DDR_DQ7
DDR_DQ13

4P2R_56
1
2

4
3

DDR_DQ[0..63]

4P2R_56
1
2

RP117

DDR_DQS[0..8]

DDR_DQ49
DDR_DQ52

DDR_DQ55
DDR_DQS6

DDR_DQ9
DDR_DQS1
DDR_DQ10
DDR_DQ11

4P2R_56
1
2

DDR_DQ54
DDR_DQ51

7
7

DDR_CLK4
DDR_CLK#4

4P2R_56
1
2

DDR_F_CB4
DDR_F_CB1

RP118
4
3

DDR_F_CB2
DDR_F_CB7

1
2

RP24
4
3

DDR_DQ16
DDR_DQ21
DDR_DQS2
DDR_DQ18

4P2R_56
1
2

RP119
DDR_F_CB3

4
3

DDR_DQ60
DDR_DQ56

DDR_DQ23
DDR_DQ28

4P2R_56
1
2

DDR_DQ29
DDR_DQS3

DDR_DQS7
DDR_DQ57

DDR_DQ30
DDR_DQ31

4P2R_56
1
2

DDR_DQ45
DDR_DQ40

RP120
4
3

4P2R_56
1
2

DDR_DQ59
DDR_DQ62

DDR_F_CB5
DDR_F_CB0

4P2R_56
1
2

DDR_DQ37
DDR_DQ33

RP23
4
3

DDR_DQS8
DDR_F_CB6

4P2R_56
1
2

DDR_DQ61
DDR_DQ63

DDR_F_CB3

4P2R_56
1
2

DDR_DQ46
DDR_DQ43

4P2R_56
1
2

7
7

DDR_CLK3
DDR_CLK#3

7

DDR_CKE3

DDR_DQ36
DDR_DQ32

DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1

DDR_DQ38
DDR_DQ35

4P2R_56
1
2

9 DDR_F_SBS0
9 DDR_F_SWE#
7
DDR_SCS#2

DDR_DQ34
DDR_DQS4

4P2R_56
1
2

1
2

DDR_DQS4
DDR_DQ34

For EC Tools

DDR_DQS5
DDR_DQ41

DDR_DQ39
DDR_DQ44

4P2R_56
1
2

DDR_DQ47
DDR_DQ42

DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE#
DDR_SCS#2
DDR_DQ32
DDR_DQ36

DDR_DQ44
DDR_DQ39

4P2R_56

DDR_CKE3
DDR_F_SMA12
DDR_F_SMA9

4P2R_56
1
2

DDR_DQ41
DDR_DQS5

+5VALW
JP20
1
2
3
4
5
6

VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_DQ1
DDR_DQ0

C616
.1UF_X5R

DDR_DQ6
DDR_DQ2
DDR_DQ8

+1.25VS
RP93

DDR_DQ12

4
3

DDR_DQ14
DDR_DQ15

RP19
4
3
RP94

DDR_DQ58
DDR_DQ50

4P2R_56
1
2

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS

4P2R_56

4P2R_56
1
2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

1

DDR_F_CB[0..7]

DDR_DQ4
DDR_DQ5

RP34

4P2R_56
4
3

2

+1.25VS

RP96
1
2

+2.5V

DDR_DQ42
DDR_DQ47
EC_URXD/KSO16
EC_UTXD/KSO17
EC_USCLK

EC_URXD/KSO16 33
EC_UTXD/KSO17 33,35
EN_USCLK 33

DDR_DQ48
DDR_DQ53
DDR_DQS6
DDR_DQ55

@ FCI SFW06R-2STE1

DDR_DQ50
DDR_DQ58
DDR_DQ57
DDR_DQS7
DDR_DQ62
DDR_DQ59
9,12,21 SMB_DATA
9,12,21 SMB_CLK
+3VS

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_DQ20
DDR_DQ17

4
3
RP18

DDR_DQ22

4
3

DDR_DQ19
DDR_DQ24

RP95

DDR_DQ25

4
3

DDR_DQ26
DDR_DQ27

RP17

DDR_F_CB4
DDR_F_CB1

4
3

DDR_F_CB2

R525
1

DDR_F_CB7

RP109
4
3
DDR_CKE2

DDR_CKE2 7

DDR_F_SMA11
DDR_F_SMA8

4
3

DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0

R224
1

DDR_F_SBS1
DDR_F_SRAS#
DDR_F_SCAS#
DDR_SCS#3

1
2

1

DDR_F_SMA9
DDR_F_SMA12

4P2R_56
1
2

DDR_F_SMA11
DDR_F_SMA8

4P2R_56
1
2

DDR_F_SMA5
DDR_F_SMA7

4P2R_56
1
2

DDR_F_SMA6
DDR_F_SMA4

4P2R_56
1
2

DDR_F_SMA1
DDR_F_SMA3

4P2R_56
1
2
56
2

DDR_F_SMA2
DDR_F_SMA0

DDR_F_SMA10
2

4P2R_56
1
2

DDR_F_SWE#
DDR_F_SBS0

4P2R_56
1
2
56
2

DDR_F_SRAS#
DDR_F_SCAS#

DDR_F_SBS1

DDR_F_SBS1 9
DDR_F_SRAS# 9
DDR_F_SCAS# 9
DDR_SCS#3 7

DDR_DQ37
DDR_DQ33
DDR_DQ38
DDR_DQ35
DDR_DQ45
DDR_DQ40
3

DDR_DQ46
DDR_DQ43
DDR_CLK#5 7
DDR_CLK5 7
DDR_DQ49
DDR_DQ52
+1.25VS

DDR_DQ54
DDR_DQ51
DDR_DQ60
DDR_DQ56
DDR_DQ61
DDR_DQ63
+3VS

RP22
DDR_CKE2 1
DDR_CKE3 2

4P2R_56
4
3

RP110
DDR_SCS#2 1
DDR_SCS#3 2

4P2R_56
4
3

Layout note
Place these resistor
closely DIMM0,
all trace length
Max=1.3"

DDR-SODIMM_200_Reverse
4

RP16

4P2R_56

DIMM1

4

Top side

Compal Electronics, Inc.
Title
PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

D

DDR-SODIMM SLOT1
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

10

of

45

A

B

C

D

E

Layout note :
Distribute as close as possible
to DDR-SODIMM.

1
2

1

1
C240
.1UF_X5R

1

C235
.1UF_X5R

C593
+
150UF_D2_6.3V

2

+

C606
150UF_D2_6.3V

2

C241
.1UF_X5R

1

1

1
C237
.1UF_X5R

2

1
C246
.1UF_X5R

2

1
C245
.1UF_X5R

2

1
C236
.1UF_X5R

2

1
C244
.1UF_X5R

C234
.1UF_X5R

+2.5V

2

2

1

+2.5V

C238
.1UF_X5R

2

C247
.1UF_X5R

2

1

1
C233
.1UF_X5R

2

C243
.1UF_X5R

2

1

1
C239
.1UF_X5R

2

C242
.1UF_X5R

2

1

1
C232
.1UF_X5R

2

2

1

2

1

+2.5V

Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V

2

2

1

1
C642
.1UF_X5R

2

C641
.1UF_X5R

2

1
C276
.1UF_X5R

2

1
C640
.1UF_X5R

2

1
C277
.1UF_X5R

2

1
C639
.1UF_X5R

2

1
C278
.1UF_X5R

2

1
C638
.1UF_X5R

2

1
C279
.1UF_X5R

2

2

1

+1.25VS

C629
.1UF_X5R

1

1
C646
.1UF_X5R

2

C274
.1UF_X5R

2

1
C645
.1UF_X5R

2

1
C644
.1UF_X5R

2

1
C275
.1UF_X5R

2

1
C643
.1UF_X5R

2

1
C631
.1UF_X5R

2

1
C263
.1UF_X5R

2

1
C630
.1UF_X5R

2

2

1

+1.25VS

C647
.1UF_X5R

1

1
C261
.1UF_X5R

2

C633
.1UF_X5R

2

1
C632
.1UF_X5R

2

1
C650
.1UF_X5R

2

1
C262
.1UF_X5R

2

1
C649
.1UF_X5R

2

1
C272
.1UF_X5R

2

1
C648
.1UF_X5R

2

1
C273
.1UF_X5R

2

3

2

1

+1.25VS

C657
.1UF_X5R
3

1

1
C653
.1UF_X5R

2

C271
.1UF_X5R

2

1
C652
.1UF_X5R

2

1
C651
.1UF_X5R

2

1
C637
.1UF_X5R

2

1
C636
.1UF_X5R

2

1
C635
.1UF_X5R

2

1
C628
.1UF_X5R

2

1
C627
.1UF_X5R

2

2

1

+1.25VS

C269
.1UF_X5R

1

1
C656
.1UF_X5R

2

C266
.1UF_X5R

2

1
C655
.1UF_X5R

2

1
C280
.1UF_X5R

2

1
C660
.1UF_X5R

2

1
C267
.1UF_X5R

2

1
C659
.1UF_X5R

2

1
C268
.1UF_X5R

2

1
C654
.1UF_X5R

2

2

1

+1.25VS

C265
.1UF_X5R

+1.25VS

1
C634
.1UF_X5R

2

1
C658
.1UF_X5R

2

C264
.1UF_X5R

2

2

1

4

1

4

C270
.1UF_X5R

Compal Electronics, Inc.
Title
PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

D

DDR SODIMM Decoupling
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

11

of

45

C

D

C201
.1UF_X5R

C202
.1UF_X5R

C204
.1UF_X5R

C206
.1UF_X5R

C211
.1UF_X5R

1
C212
.1UF_X5R

2

133Mhz Host CLK

1

1

C200
22UF_10V_1206

2

1

1

200Mhz Host CLK

2

0

1

1

+
2

100Mhz Host CLK

1

66Mhz Host CLK

1

2

0

0

H

Width=40 mils

L16
BLM21A601SPT
1
2

1

0

G

+3V_CLK

1

L17
BLM21A601SPT
1
2

Function

2

SEL0

F

2

+3VS

SEL1

E

2

B

1

A

C210
.1UF_X5R

+3VS_VDD48M

1

1

L15
1

10_0805
2

+3VS

1K
2

2

2
C214

R99

R100

1K

@1K

1K

2

R98

2

2

Host Swing Select

1

Rr =
Iref
Rr =
Iref

221 1%,
=5.00mA
475 1%,
=2.32mA

XTAL_OUT

40
55
54

SEL2
SEL1
SEL0

25
34
53

PWR_DWN#
PCI_STOP#
CPU_STOP#

1

1

45

CLK_BCLK

C213
10UF_10V_1206

1
R105

2
33
R96

1

CLK_HCLK 4

2
49.9_1%_0603

Place resistor near R184,R185 ;Trace
<=400mils

1
R101

2
1K

R89
R88

+3VS

Ioh = 4 * Iref

CPU_CLKC2

44

CLK_BCLK#

CPUCLKT1

49

CLK_HT

1
R106
1
R103

2
33
2
33

1
R97

2
49.9_1%_0603

1

2
49.9_1%_0603

R94

9,10,21 SMB_DATA
9,10,21 SMB_CLK

2 10K
2 @10K

1
1

SMB_DATA
SMB_CLK

28

VTT_PWRGD#

43

MULT0

CLK_HCLK# 4
CLK_GHT 6
2

Place resistor near R182,R183 ;Trace
<=400mils

29
30

SDATA
SCLK

33
35

3V66_0/DRCG
3V66_1/VCH_CLK

42

IREF

39

48MHZ_USB

38

48MHZ_DOT

CPUCLKC1

48

CPUCLKT0

52

CLK_HT#

1
R104

1
R95

2
33

2
49.9_1%_0603

CLK_GHT# 6

Ioh = 6 * Iref

Please closely pin42

21

R102 1

CLK_ICH48

R107 1
1
R108

21
CLK_ICH14
31 CLK_14M_SIO

2
475_1%_0603
2 22

2 33
2
33

CLK_ICH48M

CLK_ICH14M

56

CPUCLKC0

51

66MHZ_IN/3V66_5

24

66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2

23
22
21

PCICLK_F2
PCICLK_F1
PCICLK_F0

REF
GND_REF
GND_PCI
GND_PCI
GND_3V66
GND_3V66
GND_48MHZ
GND_IREF
GND_CPU

1
R409

3

CPUCLKT2

C209
.1UF_X5R

18
17
16
13
12
11
10

CLKPCI_F2

R118 1

CLKPCI_EC
CLKPCI_1394
CLKPCI_MINI
CLKPCI_SIO
CLKPCI_CB
CLKPCI_LAN

R113
R121
R120
R116
R119
R115

1
1
1
1
1
1

2 33
2 33
2 33

CLK_AGP_MCH 6
CLK_AGP 13
CLK_ICHHUB 21

2 33

CLK_ICHPCI 20

2
2
2
2
2
2

33
33
22
33
33
33

CLK_PCI_EC 33
CLK_PCI_1394 25
CLK_PCI_MINI 27
CLK_PCI_SIO 31
CLK_PCI_CB 23
CLK_PCI_LAN 26

4
9
15
20
31
36
41
47

ICS 9508-05

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

7
6
5

CLK66MCH R112 1
CLK66AGP R117 1
CLKICHHUB R114 1

3

1

0

+3VS

42 CK408_PWRGD#

Output
Current

Reference R,
Iref=
VDD/(3*Rr)

GND_CORE

27

2

MULT0

26

C199
10UF_10V_1206

1

2
@0

2

1
R91

1

H_BSEL0
H_BSEL1

3

1
@10P

H_BSEL2
H_BSEL0
BSEL0

1

4
4

VDD_CORE

2

R93
R92
@1K

XTAL_IN

Y1
14.318MHZ

C203
.1UF_X5R

+3VS

L18
BLM21A601SPT
1
2

2

caps are internal
to CK_TITAN

2

1

2

1
@10P

1

2
C208

+3VS
1

+3VS

+3VS_CLKVDD

1

VDD_REF
VDD_PCI
VDD_PCI
VDD_3V66
VDD_3V66
VDD_48MHZ
VDD_CPU
VDD_CPU

2

U7

Place Crystal within 500 mils of CK_Titan

2

1
8
14
19
32
37
46
50

1

*BLM21A601SPT

C531
10PF

or W320-04

Note:
CPU_CLK[2:0] needs to be running in C3, C4.

4

4

Compal Electronics, Inc.
Title
PROPRIETARY NOTE

A

B

C

D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
E

F

Clock Generator
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002
G

Sheet

12
H

of

45

5

4

3

2

PROPRIETARY NOTE

6
6

GAD[0..31]
GC/BE#[0..3]

6
6
6
6
6
6
6

ST0
ST1
ST2
AD_STB0
AD_STB0#
AD_STB1
AD_STB1#

6
6

PIPE#
RBF#

6
6

AGPREF
WBF#

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GAD[0..31]
GC/BE#[0..3]

2

C61
.1UF_X5R

+3VS

R42
R41

1

2

1

2

STP_AGP#
10K
AGP_BUSY#
10K

1

CLK_AGP
C

R21

1 2

10

2

C56
10PF

12
CLK_AGP
6
GDEVSEL#
6
GFRAME#
6
GGNT#
20,23,25 PIRQA#
6
GIRDY#
6
GPAR
6
GREQ#
6,20,23,24,25,26,27,31,33 PCIRST#
6
GSTOP#
6
GTRDY#

B

AGPST0
AGPST1
AGPST2
AGPADSTB0
AGPADSTB0#
AGPADSTB1
AGPADSTB1#
AGPBUSY#
AGPPIPE#
APGRBF#
AGPSTOP#
AGPVREF
AGPWBF#

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

AH29
AJ30
AH27
AJ29
AG25
AG26
AG24
AK30
AK28
AF22
AH26
AH25
AJ26
AF21
AK26
AH24
AH21
AK22
AG20
AF18
AJ21
AJ22
AH20
AK18
AF17
AJ20
AJ17
AJ18
AG16
AK16
AH16
AJ16

PCIAD0
PCIAD1
PCIAD2
PCIAD3
PCIAD4
PCIAD5
PCIAD6
PCIAD7
PCIAD8
PCIAD9
PCIAD10
PCIAD11
PCIAD12
PCIAD13
PCIAD14
PCIAD15
PCIAD16
PCIAD17
PCIAD18
PCIAD19
PCIAD20
PCIAD21
PCIAD22
PCIAD23
PCIAD24
PCIAD25
PCIAD26
PCIAD27
PCIAD28
PCIAD29
PCIAD30
PCIAD31

GC/BE#0
GC/BE#1
GC/BE#2
GC/BE#3

AF23
AJ25
AJ24
AG18

PCIC/BE#0
PCIC/BE#1
PCIC/BE#2
PCIC/BE#3

CLK_AGP
GDEVSEL#
GFRAME#
GGNT#
PIRQA
GIRD Y#
GPAR#
GREQ#
PCIRST#
GSTOP#
GTRDY#

AH18
AG22
AH22
AF13
AF16
AK24
AF20
AK12
AH17
AH23
AF19

PCICLK
PCIDEVSEL#
PCIFRAME#
PCIGNT#
PCIINTA#
PCIIRDY#
PCIPAR
PCIREQ#
PCIRST#
PCISTOP#
PCITRDY#

U15
U16
U17
U18
U19
V8
V11
V12
V13
V14
V15
V16
V17
V18
V19
V27
V30
W12
W13
W14
W15
W16
W17
W18
W19
W20
W23
Y13
Y15
Y19
Y27
AB27

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

A

HOST INTERFACE

D

1

AGPREF

AJ13
AH14
AJ14
AJ28
AF24
AK20
AH19
AF15
AG14
AK14
AH15
AF27
AF14

PCI/AGP INTERFACE

U20A
ST0
ST1
ST2
AD_STB0
AD_STB0#
AD_STB1
AD_STB1#
AGP_BUSY#
PIPE#
RBF#
STP_AGP#
AGPREF
WBF#

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

A1
A4
A6
A10
A14
A18
A22
A26
A30
B2
B29
C1
C3
C28
D4
D6
D8
D10
D12
D14
D16
D18
D20
D22
D24
D27
D30
E1
E5
E26
F27
F30
G4
H12
H18
H27
J1
K27
K30
L4
L12
L16
L18
M8
M11
M12
M13
M14
M15
M16
M17
M18
M19
M27
N1
N12
N13
N14
N15
N16
N17
N18
N19
N20
N23
P12
P13
P14
P15
P16
P17
P18
P19
P27
P30
R12
R13
R14
R15
R16
R17
R18
R19
R20
T11
T12
T13
T14
T15
T16
T17
T18
T19
T27
U12
U13
U14

D

C

B

A

Compal Electronics, Inc.
Title

NV17M

5

4

ATI M7-P AGP BUS

3

2

Size
B

Document Number
LA1432

Date:

星期五, 六月 07, 2002

Rev
1.A
Sheet
1

13

of

45

5

4

3

2

17,18 NMAA[0..13]

17,18 NMAB[4..7]

NMD[0..127]

17,18 NMD[0..127]

NMAB[4..7]

NDQM[0..15]

17,18 NDQM[0..15]

+3VS

AK13
AK17
AK21
AK25
AK29

NV17M

GND
GND
GND
GND
GND

Power Supply

1
2

2

1

C147
470PF

470PF

C153
470PF

1

C133

2

470PF

1

C112

2

470PF

1

C92

2

470PF

C183
470PF

+2.5VS

4700PF

4700PF

C176
4700PF

1

C180

2

4700PF

C184

2

4700PF

C122

1

B

C82

C162
4700PF

+2.5VS

2

1

NV17M

C62

0.047UF

C107

0.047UF

C142

0.047UF

C182

1

10K

470PF

0.047UF

2

R377

C16
G28
J4
AF2
AF12
AG27
AH12
AH13
AJ12

AB30
AC13
AC19
AD27
AF3
AF25
AF26
AF30
AG7
AG9
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AH28
AK6

C74

1

N_SUS_STAT#

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

C175

+2.5VS

2

19,33
19

470PF

1

ENVEE
ENVDD

C177

2

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

ENVEE
ENVDD

1

GPIOD0
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7

470PF

2

FBVREF

B5
E8
D7
C7
B6
A5
A3
J5

C179

1

D23

17,18

470PF

2

FBVREF

NMCS0#

C181

1

NMCKE#

17
17

C

+2.5VS

2

FBACKE

K28

NDQS5
NDQS6

+2.5VS

1

NMCS0#

18
18

A8
A12
A16
A20
A24
B8
B12
B16
B20
B24
G1
G2
H29
H30
M29
M30
T29
T30
Y29
Y30
AD29
AD30

2

N28
M26

NDQS5
NDQS6

NDQS1
NDQS2

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

1

FBACS0#
FBACS1#

NDQS1
NDQS2

FBD96
FBD97
FBD98
FBD99
FBD100
FBD101
FBD102
FBD103
FBD104
FBD105
FBD106
FBD107
FBD108
FBD109
FBD110
FBD111
FBD112
FBD113
FBD114
FBD115
FBD116
FBD117
FBD118
FBD119
FBD120
FBD121
FBD122
FBD123
FBD124
FBD125
FBD126
FBD127

AE26
V29
J27
C25
C20
C14
D5
M3

2

AC28
Y28
F28
D26
C22
C17
C10
H5

E20
D21
A21
B21
D19
E19
B19
A19
C15
D15
B14
E14
C13
D13
E13
C12
C6
C5
D3
E6
E4
A2
B3
F5
M5
L3
M2
M4
N5
M1
N4
N3

FBDQS8
FBDQS9
FBDQS10
FBDQS11
FBDQS12
FBDQS13
FBDQS14
FBDQS15

NDQM8
NDQM9
NDQM10
NDQM11
NDQM12
NDQM13
NDQM14
NDQM15

1

NC9
NC10

FBDQS0
FBDQS1
FBDQS2
FBDQS3
FBDQS4
FBDQS5
FBDQS6
FBDQS7

NMD96
NMD97
NMD98
NMD99
NMD100
NMD101
NMD102
NMD103
NMD104
NMD105
NMD106
NMD107
NMD108
NMD109
NMD110
NMD111
NMD112
NMD113
NMD114
NMD115
NMD116
NMD117
NMD118
NMD119
NMD120
NMD121
NMD122
NMD123
NMD124
NMD125
NMD126
NMD127

AE29
AA28
D28
E25
C19
E18
E7
L5

NMCLKB0 17
NMCLKB0# 17
NMCLKB1 17
NMCLKB1# 17

2

NC

NDQM0
NDQM1
NDQM2
NDQM3
NDQM4
NDQM5
NDQM6
NDQM7

FBDQM8
FBDQM9
FBDQM10
FBDQM11
FBDQM12
FBDQM13
FBDQM14
FBDQM15

D

1

GPIO

AB29
AE30
C27
F26
B18
E17
E10
K4

NMCLKB0
NMCLKB0#
NMCLKB1
NMCLKB1#

2

FBDQM0
FBDQM1
FBDQM2
FBDQM3
FBDQM4
FBDQM5
FBDQM6
FBDQM7

NMCLKA0 18
NMCLKA0# 18
NMCLKA1 18
NMCLKA1# 18

FBBCLK0
FBBCLK0#
FBBCLK1
FBBCLK1#

C11
D11
E9
D9

1

NMCLKA0
NMCLKA0#
NMCLKA1
NMCLKA1#

NMAB4
NMAB5
NMAB6
NMAB7

1

R28
R27
L27
L28

17,18
17,18
17,18

B13
A13
A11
B11

2

FBACLK0
FBACLK0#
FBACLK1
FBACLK1#

NMCAS#
NMRAS#
NMWE#

FBBA4
FBBA5
FBBA6
FBBA7

1

NMCAS#
NMRAS#
NMWE#

FBD64
FBD65
FBD66
FBD67
FBD68
FBD69
FBD70
FBD71
FBD72
FBD73
FBD74
FBD75
FBD76
FBD77
FBD78
FBD79
FBD80
FBD81
FBD82
FBD83
FBD84
FBD85
FBD86
FBD87
FBD88
FBD89
FBD90
FBD91
FBD92
FBD93
FBD94
FBD95

2

AK8
AK10

L30
L29
N29

AH30
AG29
AG28
AF28
AF29
AE28
AE27
AG30
W29
W30
V28
V26
U27
U29
U28
U26
J30
L26
G30
J28
K26
H28
J26
G29
E24
D25
A27
C26
E23
B26
C24
B25

2

FBD32
FBD33
FBD34
FBD35
FBD36
FBD37
FBD38
FBD39
FBD40
FBD41
FBD42
FBD43
FBD44
FBD45
FBD46
FBD47
FBD48
FBD49
FBD50
FBD51
FBD52
FBD53
FBD54
FBD55
FBD56
FBD57
FBD58
FBD59
FBD60
FBD61
FBD62
FBD63

FBACAS#
FBARAS#
FBAWE#

NMD64
NMD65
NMD66
NMD67
NMD68
NMD69
NMD70
NMD71
NMD72
NMD73
NMD74
NMD75
NMD76
NMD77
NMD78
NMD79
NMD80
NMD81
NMD82
NMD83
NMD84
NMD85
NMD86
NMD87
NMD88
NMD89
NMD90
NMD91
NMD92
NMD93
NMD94
NMD95

1

E22
A25
B23
C23
A23
E21
C21
B22
D17
C18
E16
B17
A17
A15
B15
E15
B10
E12
B9
A9
E11
B7
C9
C8
E3
F4
F3
D1
F2
E2
H4
G3

T28
U30
T26
P29
R29
R30
R26
P28
N27
P26
N26
M28
K29
J29
N30

SDRAM/SGRAM FRAMEBUFFER INTERFACE

NMD32
NMD33
NMD34
NMD35
NMD36
NMD37
NMD38
NMD39
NMD40
NMD41
NMD42
NMD43
NMD44
NMD45
NMD46
NMD47
NMD48
NMD49
NMD50
NMD51
NMD52
NMD53
NMD54
NMD55
NMD56
NMD57
NMD58
NMD59
NMD60
NMD61
NMD62
NMD63

NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13
FBAA14

1

FBD0
FBD1
FBD2
FBD3
FBD4
FBD5
FBD6
FBD7
FBD8
FBD9
FBD10
FBD11
FBD12
FBD13
FBD14
FBD15
FBD16
FBD17
FBD18
FBD19
FBD20
FBD21
FBD22
FBD23
FBD24
FBD25
FBD26
FBD27
FBD28
FBD29
FBD30
FBD31

2

B

AD28
AD26
AC27
AC26
AC29
AB26
AB28
AC30
AA27
AA26
AA29
Y26
W26
AA30
W28
W27
F29
G27
H26
E30
E29
D29
E28
G26
C30
E27
B30
C29
A29
B28
B27
A28

2

C

U20C

NMD0
NMD1
NMD2
NMD3
NMD4
NMD5
NMD6
NMD7
NMD8
NMD9
NMD10
NMD11
NMD12
NMD13
NMD14
NMD15
NMD16
NMD17
NMD18
NMD19
NMD20
NMD21
NMD22
NMD23
NMD24
NMD25
NMD26
NMD27
NMD28
NMD29
NMD30
NMD31

SDRAM/SGRAM FRAMEBUFFER INTERFACE

U20B

D

1

NMAA[0..13]

C178
0.047UF

2

+2.5VS

+2.5VS

2

1

2

C165
.1UF_X5R

10K

2

1
2

1

R64

A

R77
1K_1%_0603

17,18

C134

4.7UF_0805

C190
4.7UF_0805

1

1

C154

2

NMCKE#

2

NMCKE#

1

(10mil) FBVREF

1

Plece at T-Point

2

1

R76
1K_1%_0603

C110
4.7UF_0805
A

@.1UF_X5R

Compal Electronics, Inc.
Place clost to the NV17M
Title
ATI M7-P DDA CH-A
PROPRIETARY NOTE

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

2

Document Number
LA1432
星期五, 六月 07, 2002

Rev
1.A
Sheet
1

14

of

45

5

4

3

2

+2.8V
+IFP0PLLVDD

+3VS

PROPRIETARY NOTE

VOUT

VIN

6

SENSE

DELAY

2

1

CNOISE

ERROR

7

3

GND

ON/OFF#

8

SI91822AD

1

1

0.1UF_X5R

C438
1000PF

C436
4.7UF_0805

2

4.7UF_0805

C437

2

1

C422

R355
150K_1%_0603

2

2
200K_1%_0603

4

1

1
R356

2

0.1UF_X5R

1

C100

2

4700PF

1

C101

2

2

1

U24

5

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

D

1
R67

DVOD9
2
1
@10K
R316
VIPD7
2
@10K

1
R66

2
10K

2
10K

AGP4X
0: Enabled DEFAULT
1: disabled

1
R25

AGP_FW
0: Enabled DEFAULT
1: disabled

+3VS

1
R19

2
10K
2
1K

DVO HSYNC

AG2
AG5
AG3
AH1
AH2
AG1
AG6

DVOCLKOUT
DVOCLKOUT#
DVOCLKIN
DVOHSYNC
DVOVSYNC
DVOVREF
DVODE

DVOVREF
R27

PCI_DEVID[0:3]
0100: NV17M
0101: NV17SQUISH

1K

C50

1
2
1
2

1
2

1
2

1
2

1
2

4700PF

DACRSET

AJ10

DACVREF

AJ11

DACVDD

AK11

DACGND

AK9

DAC2RED
DAC2GREEN
DAC2BLUE

AD4
AE3
AD3

CRT2HSYNC
CRT2VSYNC

AE4
AD5

DAC2REST

AD2

DAC2VREF

AE2

DAC2VDD

AF1

DAC2GND

AD1

XTALIN
XTALOUT

AH9
AF10

XTALSSIN
XTALOUTBUFF

AH10
AG10

PLLVDD

AK7

DDCSCL
DDCSDA
I2C2SCL
I2C2SDA
I2CSCL
I2CSDA

AH7
AH6
AJ7
AH8
AF9
AG8

NV17M

DACRSET

1
R16
+DACVREF
1
C51

R
G
B

19
19
19

HSYNC
VSYNC

19
19

2
113_1%_0603

C34

470PF

L11
1
2
FBM-11-160808-121
C30

C35
4700PF

4.7UF_0805

+DACVDD

CRMA
LUMA
COMPS

CRMA
LUMA
COMPS

19
19
19
+3VS

+SVDD
DAC2RSET

1
R342
+DAC2VREF 1
C58

2
63.4_1%_0603
2
0.01UF_X7R

L9

C48

C47

C16

1
R15
1
R62

0.1UF_X5R

0.1UF_X5R

4.7UF_0805

2
10K
2
10K

XTALSSIN
27MOUT
2
22

1
R39

+SVDD

+PLLVDD
U3

1
R35
1
R43

DDC_CLK 19
DDC_DATA 19
LCD_CLK 19
LCD_DATA 19

2
10K
2
10K

27MOUT

+3VS
+3VS

1
R23
1
R24

2
1K
2
1K

5 1
R20

1

X1/CLK

7

FS1

X2

2

8

FS2

SS%

4

CLKOUT

2
22

XTALSSIN

R13
W180

1K

A

NXTALOUT

1

1

2

27MHZ_30PPM

18PF

ROMTYPE[1:0]
00: Parallel DEFAULT
01: serial AT25F
10: serial SST45V
11: serial future

C353

Compal Electronics, Inc.

18PF
Title

ATI M7-P POWER INTERFACE
Size
B
Date:

5

0.1UF_X5R

NXTALIN
NXTALOUT

2

DVOD10 1
2
@10K
R17
VIPD2
2
1
@10K
R61

1
2
FCM2012C80_0805
C22
B

+DAC2VDD

NXTALIN 1
C354

+3VS

2
0.01UF_X7R

0.047UF

BUS_TYPE
0: PCI
1: AGP DEFAULT

DVOD11
2
10K

+3VS

+PLLVDD

1

CRTHSYNC
CRTVSYNC

AJ9
AJ8

R
G
B

2

AH11
AG12
AF11

1

DACRED
DACGREEN
DACBLUE

Y3

1
R18

2

C

1

VIP 2.0 INTERFACE PORT

470PF

3

2
10K
2
10K
2
@10K
2
10K

1

VIPD4
2
1
@10K
R71
VIPD5
2
1
@10K
R70
VIPD3
2
1
10K
R59
2 DVO HSYNC 1
@10K
R336

19,31
19,31

C60

N2
F1
AH5

2

A

1
R72
1
R68
1
R60
1
R337

PID1
PID0

C54

1

TVD0
TVD1
TVD2
TVD3
TVD4
TVD5
TVD6
TVD7
TVD8
TVD9
TVD10
TVD11

4.7UF_0805

L37

2

2
@10K
2
10K

TVMODE[1:0]
00: SECAM
01: NTSC DEFAULT
10: PAL
11: VGA

AK5
AJ6
AK4
AJ5
AK2
AJ3
AJ1
AH3
AK1
AJ2
AK3
AJ4

ROMA14
ROMA15
ROMCS#

1
0_0603
C379

+DAC2VDD

2

1
R312

DVOD7
2
1
10K
R338
DVOD8
2
1
@10K
R321

2
10K
2
@10K

TXC2
TXC2#
TXD8
TXD8#
TXD9
TXD9#
TXD10
TXD10#

DVOD0
DVOD1
DVOD2
DVOD3
DVOD4
DVOD5
DVOD6
DVOD7
DVOD8
DVOD9
DVOD10
DVOD11

2

1
R339
1
R322

DVOD6
2
1
@10K
R330
VIPD6
2
1
10K
R73

TXC1
TXC1#
TXD4
TXD4#
TXD5
TXD5#
TXD6
TXD6#
TXD7
TXD7#

VIPD7
VIPD6
VIPD5
VIPD4
VIPD3
VIPD2
PID1
PID0

1

high drive strength
low drive strength
high drive strength
low drive strength
low drive strength

CRYSTAL[1:0]
00: 13.5MHz
01: 14.318MHz
10: 27MHz SQ17/NV17 DEFAULT, NV11 DEFAULT
11: unknown

Y5
Y4
AA4
AA3
AB3
AB2
AC3
AC2
AC4
AB4
R3
R2
R4
R5
T4
T3
U3
U2

B

1
R331
1
R78

IFP1VREF

H2
H3
J3
H1
K1
J2
K3
K2

19,31
19,31

1

word,
byte,
word,
word,
byte,

T2

VIPD7
VIPD6
VIPD5
VIPD4
VIPD3
VIPD2
VIPD1
VIPD0

PID3
PID2

4.7UF_0805

2

per
per
per
per
per

IFP1RSET

PID3
PID2

4700PF

+3VS

6

DDR, DQS
DDR ,DQS
DDR, DQS
DDR, DQS
DDR, DQS

R1

ROM/ IF

B1
D2

C36

VDD

RAM_CFG[3:0]
1111:4MX32
1101:4MX32
1001:2MX32
1000:2MX32
0111:2MX32

IFP1PLLVDD
IFP1PLLGND

VIPHAD1
VIPHAD0

0.01UF

L12
1
2
FBM-11-160808-121
C28

GND

2
@10K
2
10K
2
10K
2
@10K

1
R315
1
R314
1
R326
1
R328

T1
V4

2
10K

C2
C4
B4

2

DVOD2
2
10K
DVOD3
2
@10K
DVOD4
2
@10K
DVOD5
2
10K

2
10K

1
R372

VIPPCLK
VIPHCTL
VIPHCLK

C37

1

1
R311
1
R310
1
R327
1
R329

SUB_VENDOR
0: system BIOS
1: adapter BIOS DEFAULT

1
R352

A7

2

2
10K

IFP1IOVDD
IFP1IOGND

+DACVDD

2
10K

2

DVOD1
2
1
@10K
R313

U1
T5

1

1
R308

2
10K

1
R34

1

PCI_AD_SWAP
0: REVERSED
1: NORMAL DEFAULT

DVOD0
2
10K

TXC0
TXC0#
TXD0
TXD0#
TXD1
TXD1#
TXD2
TXD2#
TXD3
TXD3#

AF7

2

+3VS

U5
U4
V3
V2
W4
W3
Y3
Y2
AA2
AA1

1
R353

TZCLK+
TZCLKTZOUT0+
TZOUT0TZOUT1+
TZOUT1TZOUT2+
TZOUT2TZOUT3+
TZOUT3-

TZCLK+
TZCLKTZOUT0+
TZOUT0TZOUT1+
TZOUT1TZOUT2+
TZOUT2TZOUT3+
TZOUT3-

IFP0VREF

PLL & VIDEO DAC

19
19
19
19
19
19
19
19
19
19

IFP0RSET

DISPLAY I

C

V1
W2

LVDS

TXCLK+
TXCLKTXOUT0+
TXOUT0TXOUT1+
TXOUT1TXOUT2+
TXOUT2TXOUT3+
TXOUT3-

IFP0PLLVDD
IFP0PLLGND

LVDS

19
19
19
19
19
19
19
19
19
19

2
1K_1%_0603
1
0.1UF_X5R
TXCLK+
TXCLKTXOUT0+
TXOUT0TXOUT1+
TXOUT1TXOUT2+
TXOUT2TXOUT3+
TXOUT3-

TESTMODE

General BUF_RST#

CHANNEL 0

+IFP0PLLVDD

W1
AB5

TEST
MODE

CHANNEL 1

0.1UF_X5R

IFP0IOAVDD
IFP0IOBVDD
IFP0IOGND

D-TV ENCODER I

C79

1
R349
2
C93

1
R309

U20D

Y1
AC1
W5

2

4700PF

1

1

1

4.7UF_0805

C83

2

4.7UF_0805

C403

2

0.022UF

L38
1
2
FBM-11-160808-121
C392

2

1

C402

+IFP0IOVDD

+IFP0IOVDD

2

2

1

+3VS

4

3

2

Document Number
LA1432
星期五, 六月 07, 2002

Rev
1.A
Sheet
1

15

of

45

5

4

3

2

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PROPRIETARY NOTE

+VDD_CORE
U20E

470PF

C124
470PF

1

C73

2

470PF

1

C95

2

4700PF

1

C148

2

4700PF

1

C103

2

4700PF

1

C72

2

4700PF

1

C123

2

.1UF_X5R

1

C132

2

.1UF_X5R

1

C109

2

.1UF_X5R

1

C91

2

.1UF_X5R

1

C111

2

4.7UF_0805

1

C108

2

4.7UF_0805

1

1

C149

2

4.7UF_0805

2

1

C116

2

2

1

+5VS
C146
470PF
D

0.022UF

1

C41

C43
0.022UF

2

0.022UF

1

C39

2

.1UF_X5R

1

C44

2

.1UF_X5R

1

C42

2

.1UF_X5R

1

C40

2

.1UF_X5R

1

C38

2

4.7UF_0805

2

2

C29

1

+1.5VS

+3VS

1

AE5
AF4
AF5

2

VDDDVO
VDDDVO
VDDDVO

1

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

C45
0.022UF

.1UF_X5R

.1UF_X5R

C85
.1UF_X5R

1

C52

1

C63

2

.1UF_X5R

1

C78

2

.1UF_X5R

1

C59

2

.1UF_X5R

1

C67

2

.1UF_X5R

1

C84

2

.1UF_X5R

1

C102

2

.1UF_X5R

1

C125

2

.1UF_X5R

1

C136

2

+1.5VS

2

AK27
AK23
AK19
AK15
AJ27
AJ23
AJ19
AJ15

2

AGPVDDQ
AGPVDDQ
AGPVDDQ
AGPVDDQ
AGPVDDQ
AGPVDDQ
AGPVDDQ
AGPVDDQ

1

+3VS

C68
.1UF_X5R

C

+5VS

2

1

NV17M

1

C

G5
K5
AF8

C55
.1UF_X5R

2

H13
H19
L13
L15
L19
M20
M23
N8
N11
P1
P2
P3
P4
P5
R11
T20
V20
V23
W8
W11
Y12
Y16
Y18
AC12
AC18

+VDD_CORE

VD50CLAMP0
VD50CLAMP1
VD50CLAMP2

1

D

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33

2

L1
L2
V5
AA5
AB1
AC5
AE1
AF6
AG4
AH4

+3VS

C137
.1UF_X5R

As close as ppossible to related pin

B

B

2

1

1

1

S

6
5
2
1

4

2
2

PR142
10K

+5V

2

2
3

8

PU28A
LM393A

3

PC122
0.1UF_X5R

2

1

PC121
4700PF

2
PR143
1K

2

1

1

3

1
1

1

2

PQ33
HMBT2222A

+ PC119
150UF_D_4V_FP

PD28
RB051L-40

G

PD29
RB751V

+VDD_CORE

PL14
5uH-SPC-06704
1
2

D

+3VS

PC120
22UF_1210_6.3V

+1.2V +/-50mV, 3.5A

PQ32
SI3445DV

PQ34
2SA1036K

1

3

-

2

1

PU28B
LM393A

7

5

PR144
2

2.5VREF

105K_1%
A

PR145
97.6K_1%

1

PC123
0.01UF

2

A

1

4

2

1

2

+

+

5

Compal Electronics, Inc.

-

6

Title
ATI M7-P Power I/F

4

3

2

Size
B

Document Number
LA1432

Date:

星期五, 六月 07, 2002

Rev
1.A
Sheet
1

16

of

45

5

4

3

+2.5VS

2

+2.5VVDD_1

1

+2.5VS

+2.5VVDD_2
L42

NMCKE#

A0
A1
A2
A3
A4
A5
A6
A7
A8(AP)
A9
A10
A11
BA0
BA1

NDQM12
NDQM14
NDQM13
NDQM15

23
56
24
57

DM0
DM1
DM2
DM3

94

DQS

VREF_1

58
52
93

VREF
MCL
RFU

NMRAS#
NMCAS#
NMWE#
NMCS0#

27
26
25
28

RAS#
CAS#
WE#
CS#

NMCKE#

53

CKE

55
54

CK
CK#

87
88
89
90
91

NC
NC
NC
NC
NC

NMCLKB1
R414

NMD[0..127]

14,18 NMD[0..127]

NDQM[0..15]

14,18 NDQM[0..15]

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
NC
NC
NC
NC
NC
NC
NC

NMD102
NMD103
NMD98
NMD99
NMD97
NMD96
NMD101
NMD100
NMD115
NMD112
NMD119
NMD113
NMD116
NMD114
NMD118
NMD117
NMD105
NMD104
NMD107
NMD106
NMD110
NMD109
NMD108
NMD111
NMD125
NMD122
NMD121
NMD127
NMD123
NMD126
NMD120
NMD124

14

38
39
40
41
42
43
44

14

NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA13
NMAA11
NMAA12

31
32
33
34
47
48
49
50
51
45
36
37
29
30

A0
A1
A2
A3
A4
A5
A6
A7
A8(AP)
A9
A10
A11
BA0
BA1

NDQM4
NDQM6
NDQM5
NDQM7

23
56
24
57

DM0
DM1
DM2
DM3

NDQS5

NDQS5

94

DQS

VREF_2

58
52
93

VREF
MCL
RFU

NMRAS#
NMCAS#
NMWE#
NMCS0#

27
26
25
28

RAS#
CAS#
WE#
CS#

NMCKE#

53

CKE

55
54

CK
CK#

87
88
89
90
91

NC
NC
NC
NC
NC

NMCLKB0

NMCLKB0

R413
@68
14

NMCLKB0#

NMCLKB0#

1
2

1
2
1

1

.1UF_X5R

C486
.1UF_X5R

C509
.1UF_X5R

+2.5VVDD_2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
NC
NC
NC
NC
NC
NC
NC

NMD36
NMD34
NMD35
NMD33
NMD32
NMD39
NMD37
NMD38
NMD49
NMD52
NMD48
NMD54
NMD50
NMD51
NMD55
NMD53
NMD41
NMD40
NMD43
NMD44
NMD42
NMD47
NMD46
NMD45
NMD59
NMD61
NMD60
NMD56
NMD58
NMD63
NMD57
NMD62

97
98
100
1
3
4
6
7
60
61
63
64
68
69
71
72
9
10
12
13
17
18
20
21
74
75
77
78
80
81
83
84

C

B

38
39
40
41
42
43
44

K4D62323HA_1

K4D62323HA_1
+2.5VS

NMAB[4..7]

2

14,18 NMAB[4..7]

C502

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
97
98
100
1
3
4
6
7
60
61
63
64
68
69
71
72
9
10
12
13
17
18
20
21
74
75
77
78
80
81
83
84

5
11
19
62
70
76
82
92
99
16
46
66
85

NMAA[0..13]

14,18 NMAA[0..13]

C503
.1UF_X5R

2
8
14
22
59
67
73
79
86
95
15
35
65
96

U31

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS

NMCLKB1#

NMCLKB1#

1

@68
14

C520
.1UF_X5R

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS

14,18
NMCLKB1

2200PF

5
11
19
62
70
76
82
92
99
16
46
66
85

31
32
33
34
47
48
49
50
51
45
36
37
29
30

2

14

NMRAS#
NMCAS#
NMWE#
NMCS0#

C496

2

.1UF_X5R

+2.5VS

2

B

NMAA0
NMAA1
NMAA2
NMAA3
NMAB4
NMAB5
NMAB6
NMAB7
NMAA8
NMAA9
NMAA10
NMAA13
NMAA11
NMAA12

NDQS6

14,18
14,18
14,18
14,18

1

1
C510

+2.5VVDD_1

1

C

NDQS6

.1UF_X5R

2

.1UF_X5R

1

C465

2

.1UF_X5R

1

C479

2

.1UF_X5R

1

C512

2

.1UF_X5R

1

1

C498

2

.1UF_X5R

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD

U32

14

C464

D

2
8
14
22
59
67
73
79
86
95
15
35
65
96

+2.5VS

C489

2

.1UF_X5R

1

C488

2

.1UF_X5R

1

1

C499

2

.1UF_X5R

2

C513

2

1
2

22UF_16V_1206

+2.5VS

1

+2.5VS

D

C528

2

1

FCM2012C80_0805
C505
.1UF_X5R

2

2200PF

C521
.1UF_X5R

2

1

1

.1UF_X5R

C507

2

22UF_16V_1206

C467

2

C524

2

2

1

2
1

1

FCM2012C80_0805

2

2

1

1

L47

+2.5VS

R415
1K_1%_0603

2200PF

1

C482

C469

2

2200PF

C480
2200PF

1

1

1

C497

2

.1UF_X5R

2

2

C514
.1UF_X5R

C487

C466
2200PF

Compal Electronics, Inc.

2200PF
Title
ATI M7-P DDA CH-A
PROPRIETARY NOTE

5

10UF_1206

1
2200PF

1

C468

2

.1UF_X5R

1

C481

2

C515
.1UF_X5R

2

R419
1K_1%_0603

2

10UF_1206

2

1

C526

1

(10mil) VREF_1

2

1

R416
1K_1%_0603

2

C517

1
+2.5VS

R418
1K_1%_0603

1

A

1

(10mil) VREF_2

2

2

1

+2.5VS

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

2

Document Number
LA1432
星期五, 六月 07, 2002

Rev
1.A
Sheet
1

17

of

45

A

4

3

2

+2.5VS

As close as ppossible to related pin

23
56
24
57

DM0
DM1
DM2
DM3

14,17

NMCKE#

NMCLKA1

94

DQS

VREF_3

58
52
93

VREF
MCL
RFU

NMRAS#
NMCAS#
NMWE#
NMCS0#

27
26
25
28

RAS#
CAS#
WE#
CS#

NMCKEB#

53

CKE

55
54

CK
CK#

87
88
89
90
91

NC
NC
NC
NC
NC

NMCLKA1
R382

14,17 NMAB[4..7]
14,17 NMAA[0..13]
14,17 NMD[0..127]
14,17 NDQM[0..15]

NMCLKA1#
NMAB[4..7]

NMAA[0..13]
K4D62323HA_1

1

1
2

2

+2.5VVDD_4

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
NMD79
NMD76
NMD78
NMD77
NMD73
NMD72
NMD75
NMD74
NMD81
NMD84
NMD86
NMD83
NMD80
NMD85
NMD87
NMD82
NMD70
NMD69
NMD67
NMD68
NMD66
NMD65
NMD71
NMD64
NMD94
NMD93
NMD95
NMD90
NMD91
NMD89
NMD92
NMD88

14

NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA13
NMAA11
NMAA12

31
32
33
34
47
48
49
50
51
45
36
37
29
30

A0
A1
A2
A3
A4
A5
A6
A7
A8(AP)
A9
A10
A11
BA0
BA1

NDQM0
NDQM3
NDQM1
NDQM2

23
56
24
57

DM0
DM1
DM2
DM3

94

DQS

58
52
93

VREF
MCL
RFU

NMRAS#
NMCAS#
NMWE#
NMCS0#

27
26
25
28

RAS#
CAS#
WE#
CS#

NMCKE#

53

CKE

55
54

CK
CK#

87
88
89
90
91

NC
NC
NC
NC
NC

NDQS1

NDQS1

VREF_4

38
39
40
41
42
43
44

14

NMCLKA0

NMCLKA0

R345
@68
14

NMCLKA0#

NMCLKA0#

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
NC
NC
NC
NC
NC
NC
NC

NMD6
NMD5
NMD7
NMD4
NMD1
NMD0
NMD3
NMD2
NMD31
NMD28
NMD30
NMD29
NMD26
NMD24
NMD27
NMD25
NMD9
NMD8
NMD10
NMD13
NMD11
NMD12
NMD15
NMD14
NMD21
NMD19
NMD20
NMD22
NMD16
NMD17
NMD23
NMD18

97
98
100
1
3
4
6
7
60
61
63
64
68
69
71
72
9
10
12
13
17
18
20
21
74
75
77
78
80
81
83
84

C

B

38
39
40
41
42
43
44

K4D62323HA_1

+2.5VS

NMD[0..127]
NDQM[0..15]

2

NMCLKA1#

97
98
100
1
3
4
6
7
60
61
63
64
68
69
71
72
9
10
12
13
17
18
20
21
74
75
77
78
80
81
83
84

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS

14

1

@68

NC
NC
NC
NC
NC
NC
NC

C389

.1UF_X5R

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS

NMRAS#
NMCAS#
NMWE#
NMCS0#

C394
.1UF_X5R

5
11
19
62
70
76
82
92
99
16
46
66
85

14,17
14,17
14,17
14,17

C362
.1UF_X5R

2
8
14
22
59
67
73
79
86
95
15
35
65
96

U17

2

NDQM9
NDQM10
NDQM8
NDQM11

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

C339

.1UF_X5R

+2.5VS

1

A0
A1
A2
A3
A4
A5
A6
A7
A8(AP)
A9
A10
A11
BA0
BA1

2

14

31
32
33
34
47
48
49
50
51
45
36
37
29
30

1

C337

.1UF_X5R

+2.5VVDD_3

5
11
19
62
70
76
82
92
99
16
46
66
85

B

NMAA0
NMAA1
NMAA2
NMAA3
NMAB4
NMAB5
NMAB6
NMAB7
NMAA8
NMAA9
NMAA10
NMAA13
NMAA11
NMAA12

NDQS2

NDQS2

.1UF_X5R

2

C340

.1UF_X5R

1

C338

.1UF_X5R

2

1

C361

.1UF_X5R

2

.1UF_X5R

1

C418

2

.1UF_X5R

1

C461

2

.1UF_X5R

1

1

1

C459

2

.1UF_X5R

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
14

C336

2

2200PF

D

2
8
14
22
59
67
73
79
86
95
15
35
65
96

U22

C462

2

.1UF_X5R

1

C463

2

.1UF_X5R

2

1

C448

+2.5VS

C

1

C357

+2.5VS

2

1

+2.5VS

2

22UF_16V_1206

2

.1UF_X5R

2

.1UF_X5R

C408

C441

2

C442

2

2200PF

1

1

1

1

.1UF_X5R

C417

2

2

22UF_16V_1206

C460

2

1

C432

1

FCM2012C80_0805

2

FCM2012C80_0805

D

2
1

1

L41

1

+2.5VVDD_4
L40

+2.5VVDD_3

2

+2.5VS

1

1

5

R346
1K_1%_0603

1

+2.5VS
(10mil)

2200PF

C390
2200PF

1

1

C391

2

.1UF_X5R

2

C393

1

1

10UF_1206

2

2

C395

.1UF_X5R

C387
2200PF

1

C386

+2.5VS

A

(10mil) VREF_3

2200PF

1

1

C420

C419
2200PF

2

.1UF_X5R

2

C443

1

10UF_1206

2

C412

.1UF_X5R

1

C458

2

R385
1K_1%_0603

2

1

2

1

R384
1K_1%_0603

C416

Compal Electronics, Inc.

2200PF

Title
ATI DDR CH-B for M7P Only

1

A

R347
1K_1%_0603

2

2

1

2

+2.5VS

VREF_4

PROPRIETARY NOTE

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

2

Document Number
LA1432
星期五, 六月 07, 2002

Rev
1.A
Sheet
1

18

of

45

A

B

C

D

D13
DAN217

E

LVDS Connector

1

1

D15
DAN217

1

D14
DAN217

3

2

3

2

3

2

JP1
33
33

+3VS

330PF

C312

1

C315

15
15
15
15

+LCDVDD
TXOUT0+
TXOUT0TXOUT1+
TXOUT1-

15
15
15
15

TXOUT2+
TXOUT2TXOUT3+
TXOUT3-

15
TXCLK+
15
TXCLK15
LCD_DATA
15,31
PID0
15,31
PID2

S CONN._SUYIN

C313

330PF

@470PF

2

330PF

1

1

1

C314

2

270PF

1
2
3
4
5
6
7

2

270PF

JP11

2

270PF

1

C322

2

75

1

R270

75

2

R272

75

2

R271

2

COMPS

1

15

2

CRMA

1

15

1
2
C317
22PF
1
2
L24
FBM-11-160808-121
1
2
C319
22PF
1
2
L26
FBM-11-160808-121
1
2
C318
22PF
1
2
FBM-11-160808-121
L25
C324
C323

DAC_BRIG
INVT_PWM
DISPOFF#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

TXOUT0+
TXOUT0TXOUT1+
TXOUT1TXOUT2+
TXOUT2TXOUT3+
TXOUT3TXCLK+
TXCLKLCD_DATA
PID0
PID2

2

LUMA

1

15

1

1

DAC_BRIG
INVT_PWM

IB+

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

L2
CHB2012U170_0805
2
1
B+
2
1
L1
CHB2012U170_0805
TZOUT0+
TZOUT0TZOUT1+
TZOUT1TZOUT2+
TZOUT2TZOUT3+
TZOUT3TZCLK+
TZCLKLCD_CLK
PID1
PID3

+LCDVDD
TZOUT0+
TZOUT0TZOUT1+
TZOUT1-

15
15
15
15

TZOUT2+
TZOUT2TZOUT3+
TZOUT3-

15
15
15
15

TZCLK+
TZCLKLCD_CLK
PID1
PID3

15
15
15
15,31
15,31

1

Foxconn QTS1040A-2121

+3VS
+3VS

+12VALW

+LCDVDD

R269
100K

R277

2

1 2

2.2K

PID0
PID1
PID2
PID3

2

1
2
3
4

+LCDVDD

8
7
6
5

8P4R-10K

22K
+

C9
Q27
DTC124EK

3

3

47K
Q1
DTC124EK

C321
1000PF

2.2K

RP1

22K

2
1

2

22K

ENVDD 2

ENVDD

R268
200K

R264

Q28
2N7002

14

1

R274
10K

100

LCD_DATA
R304
LCD_CLK
R287

C3
4.7UF_1206
10V

Q3
SI2302DS

3

2

1

+

1

+5V

.1UF_X5R

C8
4.7UF_1206
10V

+3VS

22K
R12
1K

3

R74
@10K

D19
33

1

ENBKL

DISPOFF#

2
RB751V

14,33

15

G

6
11
1
7
12
2
8
13
3
CRT_VCC 9
14
4
10
15
5

1
2
FCM2012C80_0805
L30
1
2
FCM2012C80_0805

2

VSYNC

A

1

1

1

2
C310
100PF

R281
2.2K

R265
2.2K

3

Q4
2N7002

1
2

1
2

1
C305
68PF

2

1
C307
68PF

C309
220PF

+5VS

C303
220PF

DDC_DATA 15

1

4

3

DDC_CLK 15

Q2
2N7002

Compal Electronics, Inc.

1

.1UF_X5R

2

1K

5

C320

Title

4

3

15

4

3

U1
74HCT1G125GW

+CRT_VCC

2

2

HSYNC

C304
100PF

+5VS

R282
100K

1

1

1

5

L27
1
2
CHB1608U121

R280
15

15PF

+5VS

1
2
CHB1608U121

C10
.1UF_X5R

15PF

C306

L28

+CRT_VCC

4

15PF

C308

2

18PF

C302

2

1

C329

2

18PF

2

1

1
2

18PF

C328

1

2

R284
75

1

R283
75

1

R285
75

C327

1

1
2
FCM2012C80_0805

2

2

B

2

L29

15

3

2

R

1

JP10
CRT-15P

L31
15

8
U11C
74LVC125
+3VALW POWER

1

C316
.1UF

DAN217

3

2

DAN217

3

2

3

DAN217

2

2

10K

9

2

R260

FUSE_1A

2

1

RB491D

R79
10K

2

1

2

2

D3

2

D2

1

1

D1

1

D12

+5VS
3

ENVEE

ENVEE

+CRT_VCC

1

+R_CRT_VCC
F2
1
1

2

+5VS +5VS

10

CRT Connector

U16
74HCT1G125GW

PROPRIETARY NOTE

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

D

CRT&TV-OUT Connector
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

19

of

45

A

B

C

D

1

1

ICH-2
AD[0..31]

23,25,26,27 AD[0..31]

U9A
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

2

23,25,26,27
23,25,26,27
23,25,26,27
23,25,26,27

AA3
AB6
Y8
AA9

C/BE#0
C/BE#1
C/BE#2
C/BE#3
DEVSEL#
FRAME#
IRD Y#
TRDY#
STOP#

23,25,26,27 DEVSEL#
23,25,26,27 FRAME#
23,25,26,27 IRDY#
23,25,26,27 TRDY#
23,25,26,27 STOP#
23,25,26,27 PAR
6,13,23,24,25,26,27,31,33 PCIRST#
23
PLOCK#
23,25,26,27 SERR#
23,25,26,27 PERR#

PCI Pullups

PCIRST#
PLOCK#
SERR#
PERR#

PME# has internal PU
3

RP7
PIRQB#
PIRQG#
PIRQF#
REQA#
+3VS

1
2
3
4
5

10
9
8
7
6

PIRQE#
PIRQD#
PIRQH#

29

PIDERST#

12

CLK_ICHPCI

25
27
23
26

REQ#0
REQ#1
REQ#2
REQ#3

AA4
AB4
Y4
W5
W4
Y5
AB3
AA5
AB5
Y3
W6
W3
Y6
Y2
AA6
Y1
V2
AA8
V1
AB8
U4
W9
U3
Y9
U2
AB9
U1
W10
T4
Y10
T3
AA10

REQA#
GNTA#
CLK_ICHPCI

+3VS

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
GPI1

10P8R-8.2K

AB7
V3
W8
V4
W1
W2
AA15
AA7
W7
Y7
Y15
M3
L2
W11
R2
R3
T1
AB10
P4
L3

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

(FW82801BA)

CPU

HUB
PCI

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRQ

DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PCIRST#
PLOCK#
SERR#
PERR#
PME#
GPI0/REQA#
GPO16/GNTA#
PCICLK
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
GPI1/REQB#/REQ5#

A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
CPUPWRGD

D11
A12
R22
A11
C12
C11
B11
B12
C10
B13
C13
A13

1
R133

FERR#

0

A20M#
4
CPUSLP# 4
FERR#
4
IGNNE# 4
CPUINIT# 4
INTR
4
NMI
4
SMI#
4
STPCLK# 4
RC#
33
GATEA20 33
CPU_PWRGD 4

2

CPUINIT#
SMI#
STPCLK#
RC#
GATEA20
CPU_PWRGD
HL[0..10]

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HL11
HL_STB
HL_STB#
HLCOMP
HUBREF

A4
B5
A5
B6
B7
A8
B8
A9
C8
C6
C7
C5
A6
A7
A3
B4

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HL11
HL_STB
HL_STB#
+ICH_HLCOMP
H UBREF

PIRQA#
PIRQB#
PIRQC#
PIRQD#

P1
P2
P3
N4

PIRQA#
PIRQB#
PIRQC#
PIRQD#

IRQ14
IRQ15
APICCLK
APICD0
APICD1
SERIRQ

F21
C16
N20
P22
N19
N21

IRQ14
IRQ15
CLK_APIC_ICH
PICD0
PICD1
SIRQ

N3
N2
N1
M4

PIRQE#
PIRQF#
PIRQG#
PIRQH#

HL11

PIN N3, M4 can not use GPIO.

+ICH_HLCOMP

GPI2/PIRQE#
GPI3/PIRQF#
GPI4/PIRQG#
GPI5/PIRQH#

GNT0#
GNT1#
GNT2#
GNT3#
GNT4#
GPO17/GNTB#/GNT5#

M2
M1
R4
T2
R1
L4

HL[0..10] 6

2

HL_STB
HL_STB#
2
C542

6
6

1
.1UF_X5R
HUBREF
PIRQA#
PIRQB#
PIRQC#
PIRQD#

6
13,23,25
23,26
27
27

IRQ14
IRQ15

29
28

SIRQ

23,31,33
+1.8VS

GNT#0
GNT#1
GNT#2
GNT#3

GNT#0
GNT#1
GNT#2
GNT#3

SIDERST#

+3VS

PLOCK#
PERR#
SERR#
TRDY#

+3VS

REQ#0
REQ#1
REQ#2

10P8R-8.2K

IRQ15

1394

RP9

WLAN

REQ#0
REQ#4
PIRQC#
PIRQA#

PCMCIA CONTROLLER

REQ#3

LAN

REQ#4

NC

2
@8.2K
2
10K
2
10K

+3VS
SIDERST#
IRQ14

10
9
8
7
6

1
R200
1
R140
1
R134

3

SIDERST# 28

PCI REQ ASSIGMENT

1
2
3
4
5

2
@10K
2
40.2_1%

25
27
23
26

ICH-2
RP13
REQ#3
DEVSEL#
SIRQ
IRD Y#

1
R479
1
R132

1
2
3
4

8
7
6
5
8P4R-100K

1

CLK_ICHPCI
+3VS

R512
RP10

8P4R-8.2K
1
2
R142
8.2K
1
2
R198
@1K

PICD0

2
R202
2
R501
CLK_APIC_ICH 1
R504

@33

STOP#
FRAME#
REQ#1
REQ#2

PICD1

1 2

1
2
3
4

C581
2

4

8
7
6
5

GPI1

1
10K
1
10K
2
0

4

@22PF

GNTA#

Compal Electronics, Inc.

GNTA# Strapping for "A16 swap override" : "0" -> Enable

Title
PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

ICH2-A(PCI,HUB,CPU) & FWH
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
D

20

of

45

A

B

C

D

+3VALW
35,36,39

ACIN

CP6
8P4C-22PF

8
7
6
5
RP21
8P4R-15K

CP5
8P4C-22PF

8
7
6
5
8P4R-15

USB3_DUSB3_D+
USB1_DUSB1_D+

30
30
30
30

RP20
8P4R-15K
5
6
7
8

2
@RB751V
2
10K
2
RB751V

1
2
3
4

1
2
3
4

1
D7
1
R223
1
D8

ON/OFF

8P4R-15

USB0_D- 30
USB0_D+ 30

5
6
7
8

33,36
1

PBTN#

2
RB751V

USBP3USBP3+
USBP1USBP1+

4
3
2
1

8
7
6
5
1
D6

PBTN_OUT#

8
7
6
5

1
2
3
4

33

ICH2-B(IDE,LPC,GPIO)

RP14

1
2
3
4

4
3
2
1

RP15
USBP2USBP2+
USBP0USBP0+

1

IC H_ACIN

U9B

INTRUDER#

THRM#
GPO19
SLP_S3#
SLP_S5#
PWROK
PWRBTN#
RI#
RSMRST#
GPIO25
SUSCLK
GPI6
GPO18
GPO20
GPIO24
SUSSTAT#
INTRUDER#

2

ATF_INT#

AA13
D14
W16
AB18
R20
W21
AA17
R21
W15
AA18
Y11
A15
C14
V21
Y17
T19

SMB_DATA
SMB_CLK
IC H_ACIN
SMLINK0
SMLINK1

AA16
AB16
AB17
U19
V20

SMBDATA
SMBCLK
SMBALERT#/GPI11
SMLINK0
SMLINK1

+R_VBAIS 1

+RTCRST#
+VBIAS
RTCX1
RTCX2

T20
T21
U22
T22

33

ATF_INT#

SLP_S3#
SLP_S5#
SYS_PWROK
PBTN#
EC_RIOUT#
RSMRST#

33
SLP_S3#
33
SLP_S5#
38 SYS_PWROK
33
EC_RIOUT#
22,33,36 RSMRST#
34
FLASH#
23,24
RTCCLK

+RTCVCC
R204
1

2
15K
1

1

2 2
1K

C223
1UF_25V_0805

33
31

J2

R532

BATTLOW#

BATTLOW#
SUS_STAT#

1
9,10,12 SMB_DATA
9,10,12 SMB_CLK

@JOPEN

R205
2

C227
.047UF

1
R212
X2

R214
2
10M_0603
C231
R215
12PF
@2.4M_0603

1

R213
@22M_0603

1

32.768KHZ

2

1
2

2

2
10M_0603

1

2
1K

2

1

2

C230

35

IAC_RST#

35

IAC_BITCLK

35 IAC_SDATAI0
35 IAC_SDATAI1
35
SPKR

12PF

1

33

ECSMI#

33
ECSCI#
33 EC_LID_OUT#

1
R222

+RTCVCC

3

1
R513

2
10K

31,33
31,33
31,33
31,33
33
31
31,33

2
@10K

LAD0
LAD1
LAD2
LAD3
LDRQ#0
LDRQ#1
LFRAME#

INTRUDER#

+3VALW
1
R510
1
R515
1
R514

2
10K
2
10K
2
10K

SMLINK0
SMLINK1
OVCUR#2

30
30

OVCUR#0
OVCUR#1

30

OVCUR#3

V22
P19
R19
P21
Y22
W22
N22

IC H_AC_SYNC
IAC_BITCLK
ICH_AC_SDOUT
IAC_SDATAI0
IAC_SDATAI1
SPKR

P20
M19
D4

PDA0
PDA1
PDA2
PDCS1#
PDCS3#

F20
F19
E22
E21
E19

PDA0
PDA1
PDA2
PDCS1#
PDCS3#

PDREQ
PDDACK#
PDIOR#
PDIOW#
PIORDY

G22
F22
G19
G21
G20

PDDREQ
PDDACK#
PDIOR#
PDIOW#
PDIORDY

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

H19
H22
J19
J22
K21
L20
M21
M22
L22
L21
K22
K20
J21
J20
H21
H20

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

SDA0
SDA1
SDA2
SDCS1#
SDCS3#

A16
D16
B16
C15
D15

SDA0
SDA1
SDA2
SDCS1#
SDCS3#

LPC

SDDREQ
SDDACK#
SDIOR#
SDIOW#
SIORDY

B18
B17
D17
C17
A17

SDDREQ
SDDACK#
SDIOR#
SDIOW#
SDIORDY

USB

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

D18
B19
D19
A20
C20
C21
D22
E20
D21
C22
D20
B20
C19
A19
C18
A18

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

IDE
AC97

Y14
AA11
W14
AB15
L1
AB14
AA14

GPI8
GPI7
GPI12
GPI13
GPO21
GPIO27
GPIO28

LAD0
LAD1
LAD2
LAD3
LDRQ#0
LDRQ#1
LFRAME#

Y12
W12
AB13
AB12
Y13
W13
AB11
AA12

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
LDRQ1#
LFRAME#/FWH4
FSO

USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3-

W17
Y18
AB19
AA19
W18
Y19
AB20
AA20

USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3-

W19
Y20
Y21
W20

CLK48
CLK14
CLK66

RTCRST#
VBIAS
RTCX1
RTCX2

ECSMI#
DSCACHE#
ECSCI#
EC_LID_OUT#

OVCUR#2
OVCUR#3

U20
B14
A14
B15

SYSTEM

AC_RST#
AC_SYNC
AC_BIT_CLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
SPKR

R511 1K
2

TP0
GPO22
GPO23
VGATE/VRMPWRGD

GPIO

OC0#
OC1#
OC2#
OC3#

1

VGATE 1
R135
CLK_ICH48
CLK_ICH14
CLK_ICHHUB

+3VALW
2
0

V_GATE

44

CLK_ICH48 12
CLK_ICH14 12
CLK_ICHHUB 12
PDA0
PDA1
PDA2
PDCS1#
PDCS3#

29
29
29
29
29

PDDREQ
PDDACK#
PDIOR#
PDIOW#
PDIORDY

29
29
29
29
29

2

PDD[0..15]

PDD[0..15] 29

SDA0
SDA1
SDA2
SDCS1#
SDCS3#

28
28
28
28
28

SDDREQ
SDDACK#
SDIOR#
SDIOW#
SDIORDY

28
28
28
28
28

3

SDD[0..15]

SDD[0..15] 28

ICH-2

+5VS

SMB_CLK

35

IAC_SYNC

35

IAC_SDATAO
C574

C575

1

SMB_DATA

1
R505
1
R502

2
22
2
22

IC H_AC_SYNC
PDIORDY
ICH_AC_SDOUT
SDIORDY

2
4.7K
2
4.7K

VGATE
22PF
CLKRUN#

22PF

CLKRUN# 23,25,27,31,33

LDRQ#1

1
10K
1
10K
1
10K
1
1K

IAC_BITCLK

2

R506

C580
10PF

R484
10
1 2

2
R508
2
R219
2
R220
2
R201

IAC_BITCLK

2

RSMRST#

1 2

1
100K

R500
10
1 2

R507
10

1

2
R208

CLK_ICHHUB
1

CLK_ICH14

C567
10PF

2

ICH_AC_SDOUT

1

CLK_ICH48
1

DSCACHE#

AC_SDOUT Strapping: "1" -> Safe Mode Boot

4

C554
10PF

@33

IAC_SDATAI0
2

4

1
R486
1
R483

2

2
4.7K
2
4.7K
2
100K
2
10K
2
@10K
1
10K
2
@10K

2

1
R520
1
R519
1
R131
1
R526
1
R518
2
R517
1
R509

1

+3VS

IAC_SDATAI1

Compal Electronics, Inc.

SPKR

C576

Title

@33PF
PROPRIETARY NOTE

SPKR Strapping: "0" -> No Reboot
A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

ICH2-B(IDE,LPC,GPIO)
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
D

21

of

45

A

B

C

D

ICH2-C(LAN,Power)

+1.8VS

+3VS
U9C

2

.1UF_X5R

1

C588

C558
.1UF_X5R

2

.1UF_X5R

1

C589

2

.1UF_X5R

1

1

C584

2

.1UF_X5R

2

1

C578

2

2

1

+3VALW

C556
.1UF_X5R

.1UF_X5R

1000PF

1

1

1

1

1

C587

2

.1UF_X5R

C565

2

.1UF_X5R

C561

2

.1UF_X5R

C548

2

.1UF_X5R

C549

2

1

1

.1UF_X5R

C550

2

2

4.7UF_10V_0805

C579

2

1

C562
+

2

1

+3VS

C586
1000PF

+1.8VS

.1UF_X5R

.1UF_X5R

C545
1000PF

C551

1

C583

1

C582

1

C566

1

C564

1

C591

1

C590

1000PF

+CPU_VCC

1

1

+1.8VALW

C569

1

C577

1

1

C573

2

.1UF_X5R

1

C585

2

.1UF_X5R

1

C553

2

4.7UF_10V_0805

2

2

+

2

1

C555

2

1

3

E14
E15
E16
E17
E18
F18
G18
H18
J18
P18
R18
R5
T5
U5
V5
V6
V7
V8

V5REF1
V5REF2

K2
M20

VCCSUS1_8_1
VCCSUS1_8_2
VCCSUS1_8_3
VCCSUS1_8_4
VCCSUS1_8_5

V14
V15
V16
H5
J5

+1.8VALW

VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCCSUS3_3_6

T18
U18
F5
G5
V17
V18

+3VALW

V_CPU_IO_1
V_CPU_IO_2

D12
D13

VCCRTC

U21

V5REF_SUS

V19

EEPROM

K4
J3
J4
K3

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

1

+5VS

2

+3VS

R141
1K

+VCC5REF
C220
1UF_0805

2

1

D5
1SS355

1

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71

1

VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8
VCC3_3_9
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC3_3_18

2

A1
A2
A10
B1
B2
B3
B9
B10
C2
C3
C4
C9
D5
D6
D7
D8
D9
E6
E7
E8
E9
J10
J11
J12
J13
J14
J9
K10
K11
K12
K13
K14
K9
L10
L11
L12
L13
L14
L9
M10
M11
M12
M13
M14
M9
N10
N11
N12
P9
P14
P13
P12
P11
P10
N9
N14
N13
A21
A22
B21
B22
AA1
AA2
AA21
AA22
AB1
AB2
AB21
AB22
K1
D3

VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4
VCC1_8_5
VCC1_8_6
VCC1_8_7

1

D10
E5
K19
L19
P5
V9
D2

2

1

C219
.1UF_X5R

2

+CPU_VCC

VCCRTC

1
R210

+3VALW

1
R496

2
1K

1
C225

+RTCVCC

2
.1UF_X5R

2
@10K

LAN
G3
G2
G1
H1
F3
F2
F1
H2
Y16

LAN_CLK
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_RSTSYNC
RSM_PWROK

1
R516

2
0

3

RSMRST# 21,33,36

C552

.1UF_X5R

2

.1UF_X5R

2

.1UF_X5R

2

.1UF_X5R

2

.1UF_X5R

2

.1UF_X5R

2

2

2

ICH-2
.1UF_X5R

.1UF_X5R

4

4

Compal Electronics, Inc.
Title
PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

ICH2-C(LAN,Power) & Pull-Up
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
D

22

of

45

5

4

3

CardBus Controller
OZ6933T (uBGA)

+3V

+3VS

2

S1_IOWR#
S1_IORD#
S1_OE#
S1_CE2#
S1_A[0..25]
S1_D[0..15]

+3VS

1

CBRST# 24,25,27
S1_IOWR# 24
S1_IORD# 24
S1_OE#
24
S1_CE2# 24
S1_A[0..25] 24
S1_D[0..15] 24

C682
.1UF_X5R

C686
.1UF_X5R

C

20,25,26,27
20,25,26,27
20,25,26,27
20,25,26,27

C/BE#3
C/BE#2
C/BE#1
C/BE#0

12 CLK_PCI_CB
20,25,26,27 DEVSEL#
20,25,26,27 FRAME#
20,25,26,27 IRDY#
20,25,26,27 TRDY#
20,25,26,27 STOP#
20,25,26,27 PAR
20,25,26,27 PERR#
20,25,26,27 SERR#
20
REQ#2
20
GNT#2
13,20,25 PIRQA#
20,26
PIRQB#
20
PLOCK#
6,13,20,24,25,26,27,31,33 PCIRST#

B

25,26,27,33 PCM_PME#
21,25,27,31,33 CLKRUN#
33
RING#
35
PCM_SPK#
34
PCM1_LED
34
PCM2_LED
SIRQ

100
2

B14
A4
V9
K19
J19
E8
C5
E6

N18

R10
J18
B10

F2
J5
M6
P5

S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

S1_A9

S1_A11

Slot B

IRQ12/PME#
IRQ14/CLKRUN#
IRQ15/RING_OUT
SPKR_OUT#
LED_OUT/SKT_ACTIVITY
SKTB_ACTV
IRQ5/SERIRQ
IRQ7/SIN#/B_VPP_PGM

S2_D10
S2_D9
S2_D1
S2_D8
S2_D0
S2_A0
S2_A1
S2_A2
S2_A3
S2_A4
S2_A5
S2_A6
S2_A25
S2_A7
S2_A24
S2_A17

H3
K5

CardBus-OZ6933T-1

A_D10/CAD31
A_D9/CAD30
A_D1/CAD29
A_D8/CAD28
A_D0/CAD27
A_A0/CAD26
A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20
A_A25/CAD19
A_A7/CAD18
A_A24/CAD17
A_A17/CAD16
A_IOWR/CAD15
A_A9/CAD14
A_IORD#/CAD13
A_A11/CAD12
A_OE#/CAD11
A_CE2#/CAD10
A_A10/CAD9
A_D15/CAD8
A_D7/CAD7
A_D13/CAD6
A_D6/CAD5
A_D12/CAD4
A_D5/CAD3
A_D11/CAD2
A_D4/CAD1
A_D3/CAD0

IDSEL
PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
SERR#
PCI_REQ#
PCI_GNT#
IRQ9/INTA#
IRQ4/INTB#
LOCK#
RST#

GRST#

H5
E3
L3
K6
L1
L2
L5
M2
L6
M1
G6
F5
B5
F6
V5
D1

CORE_VCC
CORE_VCC
CORE_VCC

C/BE3#
C/BE2#
C/BE1#
C/BE0#

GND
GND

20,31,33

R533
AD20 1
CLK_PCI_CB

G1
K3
M3
R1

Slot
A

2

CLK_PCI_CB

D

A_SOCKET_VCC
A_SOCKET_VCC

R7
R13

A_REG#/CCBE3#
A_A12/CCBE2#
A_A8/CCBE1#
A_CE1#/CCBE0#

N15
V14
V11
W8

A_A16/CCLK
A_A23/CFRAME#
A_A15/CIRDY#
A_A22/CTRDY#
A_A21/CDEVSEL#
A_A20/CSTOP#
A_A13/CPAR
A_A14/CPERR
A_WAIT#/CSERR#
A_INPACK#/CREQ#
A_WE#/CGNT#
A_RDY_IRQ#/CINT#
A_A19/CBLOCK#
A_WP/CCLKRUN#
A_RST/CRESET#
A_D2/RFU
A_D14/RFU
A_A18/RFU
A_VS1/CVS1
A_VS2/CVS2
A_CD1#/CCD1#
A_CD2#/CCD2#
A_BVD2/CAUDIO
A_BVD1/CSTSCHG

V13
U14
P13
W14
U13
W13
R11
V12
R18
P17
R12
P12
U12
L17
P15
L19
V8
P11
W10
W16
V6
L14
M14
N19

B_BVD1/CSTSCHG
B_BVD2/CAUDIO
B_CD2#/CCD2#
B_CD1#/CCD1#
B_VS2/CVS2
B_VS1/CVS1
B_A18/RFU
B_D14/RFU
B_D2/RFU
B_RESET/CRESET#
B_WP/CCLKRUN#
B_A19/CBLOCK#
B_RDY_IRQ#/CINT#
B_WE#/CGNT#
B_INPACK#/CREQ#
B_WAIT#/CSERR#
B_A14/CPERR#
B_A13/CPAR
B_A20/CSTOP#
B_A21/CDEVSEL#
B_A22/CTRDY#
B_A15/CIRDY#
B_A23/CFRAME#
B_A16/CCLK

F8
C8
C6
J15
A10
E18
C14
G17
F7
C10
A5
A14
F12
E13
C9
A9
A15
C15
C13
B13
A13
C12
B12
E12

B_CE1#/CCBE0#
B_A8/CCBE1#
B_A12/CCBE2#
B_REG#/CCBE3#

G14
A16
A12
F9

B_SKT_VCC
B_SKT_VCC
B_SKT_VCC

G19
F13
E7

C676

C674

C681

.1UF_X5R

.1UF_X5R

.1UF_X5R

S1_REG# 24

S1_A12
S1_A8

S1_CE1#
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A13
S1_A14

S1_A19
S1_D2
S1_D14
S1_A18

S2_A18
S2_D14
S2_D2
S2_A19

S2_A14
S2_A13
S2_A20
S2_A21
S2_A22
S2_A15
S2_A23
1
R530
S2_A8
S2_A12

1
R531

24

2
33

S1_A16

S1_WAIT# 24
S1_INPACK# 24
S1_WE#
24
S1_RDY# 24
S1_WP
S1_RST

24
24

S1_VS1
S1_VS2
S1_CD1#
S1_CD2#
S1_BVD2
S1_BVD1

24
24
24
24
24
24

S2_BVD1
S2_BVD2
S2_CD2#
S2_CD1#
S2_VS2
S2_VS1

24
24
24
24
24
24

S2_RST
S2_WP

24
24

C

S2_RDY# 24
S2_WE#
24
S2_INPACK# 24
S2_WAIT# 24
B

2
33

S2_A16

S2_CE1#

24

S2_REG# 24
+S2_VCC

C673

C675

C670

.1UF_X5R

.1UF_X5R

.1UF_X5R

S2_A10
S2_D15
S2_D7
S2_D13
S2_D6
S2_D12
S2_D5
S2_D11
S2_D4
S2_D3

C677
.1UF_X5R

S2_A11

C668
.1UF_X5R

S2_A9

+3VS

O 2 MICRO
CARDBUS CONTROLLER
OZ6933 209PIN CSP

B_D10/CAD31
B_D9/CAD30
B_D1/CAD29
B_D8/CAD28
B_D0/CAD27
B_A0/CAD26
B_A1/CAD25
B_A2/CAD24
B_A3/CAD23
B_A4/CAD22
B_A5/CAD21
B_A6/CAD20
B_A25/CAD19
B_A7/CAD18
B_A24/CAD17
B_A17/CAD16
B_IOWR#/CAD15
B_A9/CAD14
B_IORD#/CAD13
B_A11/CAD12
B_OE#/CAD11
B_CE2#/CAD10
B_A10/CAD9
B_D15/CAD8
B_D7/CAD7
B_D13/CAD6
B_D6/CAD5
B_D12/CAD4
B_D5/CAD3
B_D11/CAD2
B_D4/CAD1
B_D3/CAD0

C679
.1UF_X5R

+S1_VCC

B6
A6
B7
C7
A7
B8
A8
E9
B9
F10
E10
F11
C11
B11
A11
E14
D19
F15
E17
F14
G15
E19
F18
F17
G18
H15
H14
H17
H18
H19
J14
J17

C684
.1UF_X5R

IRQ3/VCC3#
SCLK/A_VCC_5#
SDATA/B_VCC_3#
SLATCH/B_VCC_5#
IRQ9/A_VPP_VCC
IRQ10/B_VPP_VCC

C678
.1UF_X5R

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

W12
K14
K15
K17
P19
F19

C687
4.7UF_10V_0805

E1
E2
F3
F1
G5
H6
G3
G2
H2
H1
J1
J2
J3
J6
K1
K2
M5
N2
N1
N3
N6
P1
P3
N5
P6
R2
R3
T1
W4
R6
U5
P7

PCI

2

1

+3VS

GND
GND
GND
GND
GND
NC
NC

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

AUX_VCC

AD[0..31]

20,25,26,27 AD[0..31]

PCI_VCC
PCI_VCC
PCI_VCC
PCI_VCC

U46

P2
W5
V15
K18
E11
B15
E5

D

L15

.1UF_X5R

L18
M19
M18
M15
M17
N17
P18
R19
N14
R17
T19
R14
U15
P14
W15
U11
P10
W11
U10
V10
P9
R9
U9
W9
U8
R8
W7
V7
U7
W6
P8
U6

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17

C669

R534
@33

1

A

SLATCH
SLDATA
RTCCLK

C685
@10PF

S2_CE2#
S2_OE#
S2_IORD#
S2_IOWR#
S2_A[0..25]
S2_D[0..15]

24
24
21,24

A

S2_CE2# 24
S2_OE#
24
S2_IORD# 24
S2_IOWR# 24
S2_A[0..25] 24
S2_D[0..15] 24

Compal Electronics, Inc.
Title
CardBus Controller ( OZ6933T )

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
B

Document Number
LA1432

Date:

星期五, 六月 07, 2002

Rev
1.A
Sheet
1

23

of

45

PCMCIA POWER CTRL.

+3VALW

+5VALW

+S1_VPP

+S1_VPP

W=40mils

+S1_VCC

+12VALW

1

U42

CARDBUS
SOCKET

1
1
1
1
1

2 C600
.1UF_X5R
2 C602
.1UF_X5R
2 C599
.1UF_X5R
2 C610
.1UF_X5R
2 C611
.1UF_X5R
2 C613
.1UF_X5R

1
2
30

5V
5V
5V

15
16
17

3.3V
3.3V
3.3V

23
23
21,23

3
5
4

SLDATA
SLATCH
RTCCLK

13
19
18

AVPP
AVCC
AVCC
AVCC

8
9
10
11

BVPP
BVCC
BVCC
BVCC

23
20
21
22

RESET
RESET#

6
14

NC
NC
NC
NC

26
27
28
29

DATA
LATCH
CLOCK
APWR_GOOD#
BPWR_GOOD#
OC#

GND

JP22
C605

2

12V
12V

4.7UF_10V_0805

+S2_VPP

+S2_VPP

W=40mils

1

1

VCC_5V

7
24

2

1

25
C603
2 1UF_25V_0805

23
23

+S2_VCC

S1_WP
S1_CD2#

C604

S1_WP
S1_CD2#
S1_D2
S1_D10
S1_D1
S1_D9

4.7UF_10V_0805

CBRST#

23

S1_BVD1

23

S1_BVD2

12

TPS2206AI/TPS2216/TPS2226/G574

23

S1_REG#

23

S1_INPACK#

23

S1_WAIT#

23

S1_RST

23

S1_VS2

S1_D0
S1_D8
S1_A0
S1_BVD1
S1_A1
S1_BVD2
S1_A2
S1_REG#
S1_A3
S1_INPACK#
S1_A4
S1_WAIT#
S1_A5
S1_RST
S1_A6
S1_VS2
S1_A7
S1_A25
S1_A12
S1_A24
S1_A15
S1_A23
S1_A16
S1_A22

+S1_VPP
+S1_VCC
+3VALW

6,13,20,23,25,26,27,31,33 PCIRST#

23

S1_WE#

R221

23

S1_IOWR#

10K

23

S1_IORD#

23
23
23

S1_VS1
S1_OE#
S1_CE2#

23

S1_CE1#

2

1

PCMRST# 34

.1UF_X5R

U11A
74LVC125

3

CBRST#

.01UF

1UF_25V_0805

+3VALW POWER

CBRST#

23,25,27

2

2

C665

7

1

1
C664

2

S1_RDY#

1

W=30mils

+S2_VPP

23

C256

14

2

1

S1_A[0..25]
S1_D[0..15]
S2_A[0..25]
S2_D[0..15]

S1_A[0..25]
S1_D[0..15]
S2_A[0..25]
S2_D[0..15]

+3V

1

1

+S1_VPP

2

C663

.01UF

2
C689

C662

2

C594
S1_CD1# 1
@1000PF

W=30mils

S1_CD2# 1
@1000PF

1UF_25V_0805
S2_CD1# 1
@1000PF

2
C595
2
C680

56PF

1

C623

C622
.1UF_X5R

2

2

10U_1206

1

C615

2

1

+S1_VCC

S2_CD2# 1
@1000PF

2

23

S1_CD1#

S1_A21
S1_RDY#
S1_A20
S1_WE#
S1_A19
S1_A14
S1_A18
S1_A13
S1_A17
S1_A8
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_VS1
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_CE1#
S1_D14
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_CD1#
S1_D3

a68
b68
a34
b34
a67
b67
a33
b33
a66
b66
a32
b32
a65
b65
a31
b31
GND
GND
a64
b64
a30
b30
a63
b63
a29
b29
a62
b62
a28
b28
a61
b61
GND
GND
a27
b27
a60
b60
a26
b26
a59
b59
a25
b25
a58
b58
a24
b24
GND
GND
a57
b57
a23
b23
a56
b56
a22
b22
a55
b55
a21
b21
a54
b54
GND
GND
a20
b20
a53
b53
a19
b19
a52/a18 b52/b18
none
none
a51/a17 b51/b17
a16
b16
a50
b50
a15
b15
GND
GND
a49
b49
a14
b14
a48
b48
a13
b13
a47
b47
a12
b12
a46
b46
GND
GND
a11
b11
a45
b45
a10
b10
a44
b44
a9
b9
a43
b43
a8
b8
GND
GND
a42
b42
a7
b7
a41
b41
a6
b6
a40
b40
a5
b5
a39
b39
GND
GND
a4
b4
a38
b38
a3
b3
a37
b37
a2
b2
a36
b36
a1
b1
a35
b35

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75

S2_WP
S2_CD2#
S2_D2
S2_D10
S2_D1
S2_D9

S2_WP
23
S2_CD2# 23

S2_D0
S2_D8
S2_A0
S2_BVD1
S2_A1
S2_BVD2
S2_A2

S2_BVD1 23
S2_BVD2 23

S2_REG#
S2_A3
S2_INPACK#
S2_A4
S2_WAIT#
S2_A5
S2_RST
S2_A6
S2_VS2
S2_A7
S2_A25
S2_A12
S2_A24
S2_A15

S2_REG# 23
S2_INPACK# 23
S2_WAIT# 23
S2_RST

23

S2_VS2

23

S2_A23
S2_A16
S2_A22
+S2_VPP
+S2_VCC

S2_A21
S2_RDY#
S2_A20

S2_RDY# 23

S2_WE#
S2_A19
S2_A14
S2_A18
S2_A13
S2_A17
S2_A8

S2_WE#

S2_IOWR#
S2_A9
S2_IORD#
S2_A11
S2_VS1
S2_OE#
S2_CE2#

23

S2_IOWR# 23
S2_IORD# 23

S2_A10
S2_D15
S2_CE1#
S2_D14
S2_D7
S2_D13
S2_D6
S2_D12
S2_D5
S2_D11
S2_D4
S2_CD1#
S2_D3

S2_VS1
S2_OE#
S2_CE2#

23
23
23

S2_CE1#

23

S2_CD1# 23

C621
1000PF

PCMC150PIN

+S2_VCC

C625

1

C626

1

1

Compal Electronics, Inc
C618

C624

Title

.1UF_X5R

2

56PF

2

FCI PCMCIA SOCKET
10U_1206

2

23
23
23
23

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75

1000PF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
B

Document Number
LA1432

Date:

星期五, 六月 07, 2002

Rev
1.A
Sheet

24

of

45

A

B

C

D

E

C11

1

C371

1

C31

1

C26

1

C23

1

C20

1

C18

1

1

+3V

1

+3V

C13

C369

+3V

.1UF_X5R

.1UF_X5R

2

.1UF_X5R

2

.01UF

2

.01UF

2

.01UF

2

.01UF

2

.01UF

2

8
7
6
5

2

1
2
3
4

2

RP51
.1UF_X5R

+3V

8P4R_4.7K

3

20,23,26,27 FRAME#
20,23,26,27 IRDY#
20,23,26,27 TRDY#
20,23,26,27 DEVSEL#
20,23,26,27 STOP#
20,23,26,27 PERR#
13,20,23 PIRQA#
23,26,27,33 1394_PME#
20,23,26,27 SERR#
20,23,26,27 PAR
21,23,27,31,33 CLKRUN#
6,13,20,23,24,26,27,31,33 PCIRST#

PCIRST#

23,24,27 CBRST#

R9

R11

1
R290

TPBIAS1
TPA1+

125
124
123
122
121

1
2
C333 .1UF_X5R
R292
1K
1
2
1
2
R291
1K

R0

118

R1

119

X0

6

X1

5

FILTER0

3

FILTER1

4

.1UF_X5R

1
2

2

2

1
2
106

.1UF_X5R

.1UF_X5R

+3V

L10

1

+3V

1

1

0_0805

2

+3V

C17

2

C19

2

87

86
96
10
11
CYCLEOUT/CARDBUS
CNA
TEST17
TEST16

CPS

.1UF_X5R

C21

.01UF

4.7UF_0805

PCI BUS INTERFACE

PHY PORT 2

These pin are NC TPA1pin when u se
TPB1+
TPB1TSB43AB21
BIAS CURRENT

OSCILLATOR

2
1K

2

R295
6.34K_1%_0603
C355

1

2
15PF

Y2

FILTER

1

EEPROM 2 WIRE BUS SDA

92

SCL

91

PC0
PC1
PC2

99
98
97

POWER CLASS

PHY PORT 1

C15

1

2
15PF

2
.1UF_X5R

JP9

1
R8
1
R10

TPB0TPB0+
TPA0TPA0+

2
220
2
220
R4

56.2_1%_0603

1
2
3
4

1
2
3
4

C4
Foxconn UV31413-K5
0.33UF_0603

116
115
114
113
112

TPBIAS0

TEST9
TEST8

94
95

R7
R6

1
1

2 220
2 220

TEST3
TEST2
TEST1
TEST0

101
102
104
105

R288
R289
R303
R302

1
1
1
1

2
2
2
2

TPBIAS0
TPA0+
TPA0TPB0 +
TPB0 -

C356

24.576 MHz

R1
56.2_1%_0603

220
220
220
220

R2
56.2_1%_0603
R5
56.2_1%_0603

3

TPA0+
TPA0TPB0+
TPB0-

R3
5.11K_1%_0603
C5

220PF

220

2

1

220

1

GPIO3
GPIO2

15
27
39
51
59
72
88
100
7
1
2
107
108
120

C25

2

2

89
90

CYCLEIN

G_RST

VDDP
VDDP
VDDP
VDDP
VDDP

14

DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
PLLVDD
AVDD
AVDD
AVDD
AVDD
AVDD

1

1

CLK_PCI_1394
4

R14

2

20,23,26,27 C/BE#3
20,23,26,27 C/BE#2
20,23,26,27 C/BE#1
20,23,26,27 C/BE#0
12 CLK_PCI_1394
20
GNT#0
20
REQ#0

TSB43AB22
TSB43AB21

C32
@.1UF_X5R

1

2 1394_IDSEL
100

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_C/BE3
PCI_C/BE2
PCI_C/BE1
PCI_C/BE0
PCI_CLK
PCI_GNT
PCI_REQ
PCI_IDSEL
PCI_FRAME
PCI_IRDY
PCI_TRDY
PCI_DEVSEL
PCI_STOP
PCI_PERR
PCI_INTA/CINT
PCI_PME/CSTSCHG
PCI_SERR
PCI_PAR
PCI_CLKRUN
PCI_RST

C27

8
9
109
110
111
117
126
127
128
17
23
30
33
44
55
64
68
75
83
93
103

1
R324

22
24
25
26
28
29
31
32
37
38
40
41
42
43
45
46
61
63
65
66
67
69
70
71
74
76
77
79
80
81
82
84
34
47
60
73
16
18
19
36
49
50
52
53
54
56
13
21
57
58
12
85

PLLGND1
REG_EN
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DGND
DGND
REG18
DGND
DGND
DGND
DGND
DGND
DGND
DGND
REG18
DGND

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE#3
C/BE#2
C/BE#1
C/BE#0
CLK_PCI_1394
GNT#0
REQ#0
1394_IDSEL
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
PIRQA#
1394_PME#
SERR#
PAR

2

AD16

20
35
48
62
78

TSB43AB22
AD[0..31]

20,23,26,27 AD[0..31]

C370

1

1

U2

1

1

C12
@.1UF_X5R

2

@22

For TSB43AA22
C654,C655
change to 0
ohm to short
to GND

4

TSB43AB22 USE

Compal Electronics, Inc.

C24
Title

@10PF

1394 Interface
PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

D

Document Number
LA1432
星期五, 六月 07, 2002

Rev
1.A
Sheet
E

25

of

45

5

4

3

2

1

2
1

2

1

2

5
6
7
8

+3V
U18

LAN_X1

R335

R332

R333

50

50

50

50

ISOLATE#

74

RTSET

65

RTT3

63

VCTRL

55

NC
NC
NC
NC
NC
NC
NC
NC
NC

7
35
40
52
53
54
69
76
78

GND
GND
GND
GND
GND
GND
GND
GND
GND

2
16
31
43
56
62
66
73
88

D20

1

2

+3VS

C376
.1UF_X5R

C375
.1UF_X5R

C373
.1UF_X5R

Q32
DTA114YKA
+3V

3

JP14

1

1
R300

2
300_0603

12

Amber LED+

11

Amber LED-

8

PR4+

6

PR2-

5

PR3-

4

PR3+

RJ45_RX+

3

PR2+

RJ45_TX-

2

PR1-

RJ45_TX+

1

PR1+

ACTIVITY#
RJ45_RX-

Y4
25 MHz
LAN_X2

C410

C385

Q30
DTA114YKA

Green LED-

9

Green LED+

2
300_0603

2
LINK10_100#

1

1

R296

75

75

1 2

C445

13

1

LANGND

2
C343
.1UF_X5R

C342

1000PF_2KV_1206
4.7UF_10V_0805

C421

.1UF_X5R

2

.1UF_X5R

1

1

1

1

1

C446

2

.1UF_X5R

2

.1UF_X5R

2

.1UF_X5R

2

.1UF_X5R

2

1
2

A

C429

14

SHLD1

C334

RJ45_GND
@22

C433

SHLD2

2
R299

R357

C415

15

AMP RJ45/RJ11 with LED

1

C

1 1
R293

2

3

10K

+3V

47K

27PF_NPO

B

2

2

27PF_NPO

16

SHLD3

B

10
E

1

LAN_X1

SHLD4
PR4-

7

CLK_PCI_LAN

C425

C

RJ45_GND

RB751V

RTL8100BL

+3V

R297
75

2

Power

LAN_X2

1
2
R343
1K
1
2
R344
15K
1
2
R341
5.6K_1%_0603

C

60
64

R298
75

10K

X2
LWAKE

Pulse H0013

R334

1

61

RJ45_TX+
RJ45_TX-

1

X1

RJ45_RX+
RJ45_RX-

16
15
14
13
12
11
10
9

RX+
RXCT
NC
NC
CT
TX+
TX-

2

LAN_RD+
LAN_RD-

RD+
RDCT
NC
NC
CT
TD+
TD-

2

68
67

1

RXIN+
RXIN-

LAN_TD+
LAN_TD-

2

LAN_TD+
LAN_TD-

1

72
71

1

TXD+
TXD-

.1UF_X5R

1

80
79
77

C378

1
2
3
4
5
6
7
8

9346

1

LED0
LED1
LED2

+3V

2

1
2
R348
5.6K
ACTIVITY#
LINK10_100#

LAN_RD+
LAN_RD-

1

GND
NC
NC
VCC

1

VDD
VDD
VDD
VDD
VDD
VDD

DO
DI
SK
CS

2

CLK

6
22
34
39
90
97

1

50

RST#

CLK_PCI_LAN 83
+3V

AUX

4
3
2
1

2

PIRQB#

12 CLK_PCI_LAN

LAN_EEDO
LAN_EEDI
LAN_EECLK
LAN_EECS

2

REQ#
GNT#

B

46
47
48
49

E

85
84

6,13,20,23,24,25,27,31,33 PCIRST#

EEDO
EEDI
EESK
EECS

47K

REQ#3
GNT#3

82

+3V_LAN_VDD3

D

+3V

B

PERR#
SERR#

PME#

75

+2.5V

2

18
19

INTA#

AVDD

1
4.7UH
1
4.7UH
1
4.7UH
1
4.7UH

1

20,23,25,27 PERR#
20,23,25,27 SERR#

57

+3V_LAN_VDD2

2
L36
2
L34
2
L35
2
L39

2

PAR
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#

81

AVDD

70

C388
.1UF_X5R

2

20
12
13
14
15
17

20,23

+3V_LAN_VDD1

C384
.1UF_X5R

2

20,23,25,27 PAR
20,23,25,27 FRAME#
20,23,25,27 IRDY#
20,23,25,27 TRDY#
20,23,25,27 DEVSEL#
20,23,25,27 STOP#

23,25,27,33 LAN_PME#

59

C382
.1UF_X5R

1

IDSEL

20
20

AVDD

C383
.1UF_X5R

2

99

1
R371

+2.5V_LAN_VDD

1

2 LAN_IDSEL
100

AD17

AVDD25

1

C/BE#0
C/BE#1
C/BE#2
C/BE#3

C/BE#0
C/BE#1
C/BE#2
C/BE#3

51
96
58

C381
.1UF_X5R

2

2
32
21
11
98

20,23,25,27
20,23,25,27
20,23,25,27
20,23,25,27

C431
.1UF_X5R

U19

C/BE#0
C/BE#1
C/BE#2
C/BE#3

C

VDD25
VDD25

1

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Power

D

U25

45
44
42
41
38
37
36
33
30
29
28
27
26
25
24
23
10
9
8
5
4
3
1
100
95
94
93
92
91
89
87
86

PCI I/F
LAN I/F

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

+2.5V

1

AD[0..31]

20,23,25,27 AD[0..31]

1

2

+2.5V

Termination plane should be copled to chassis ground

@10PF

Compal Electronics, Inc.
Title
LAN REALTEK RTL8100BL
PROPRIETARY NOTE

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

2

Document Number
LA1432
星期五, 六月 07, 2002

Rev
1.A
Sheet
1

26

of

45

A

+3V

RF_OFF# 35
JP4

12 CLK_PCI_MINI
20

REQ#1
AD31
AD29
AD27
AD25

20,23,25,26 C/BE#3

AD23
AD21
AD19
AD17

20,23,25,26 C/BE#2
20,23,25,26 IRDY#
21,23,25,31,33 CLKRUN#
20,23,25,26 SERR#
20,23,25,26 PERR#
20,23,25,26 C/BE#1

AD14
AD12
AD10
AD8
AD7

CLK_PCI_MINI

1

AD5
AD3
W=30mils
AD1

+5VS_MINIPCI

C289
10PF

+5VS

2 W=30mils
0_0603

1
L21
0603

LAN RESERVED

W=30mils
PIRQC#
W=40mils
MINI_RST#

PCIRST#
2
0
2
@0

PCIRST#

6,13,20,23,24,25,26,31,33

CBRST#

23,24,25

+5VS_MINIPCI
PIRQC# 20
+3VS_MINIPCI
+3V

L23
W=40mils
GNT#1

20

WLANPME# 23,25,26,33

1

2

+3V

CHB1608U121
0603

AD30
AD28
AD26
R237
AD24
MINI_IDSEL1
AD22
AD20
AD18
AD16

2

AD18

100
PAR

20,23,25,26

FRAME#
TRDY#
STOP#

20,23,25,26
20,23,25,26
20,23,25,26

IDSEL : AD18

+5VS_MINIPCI

DEVSEL# 20,23,25,26
AD15
AD13
AD11

C248
@1000PF

C249
@.1UF_X5R

C290

C592

@.1UF_X5R

@10U_1210

AD9
C/BE#0

20,23,25,26

AD6
AD4
AD2
AD0

+3VS_MINIPCI
C254
.1UF_X5R

W=20mils

C281

C672

.1UF_X5R

.1UF_X5R

C257
.1UF_X5R

C255
.1UF_X5R

C617
10U_1210

+3V

C288

Mini-PCI SLOT

+5VS_MINIPCI

2

2

1 2

R240
33

1
R239
1
R238

MINI_RST#

1

CHB1608U121
0603

2

2

PIRQD#

PIRQD#

RING

2

1

+3V

W=40mils20

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

1

L22

2

2

+3VS_MINIPCI

2
KEY
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

1

D34
RB751V
1

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

1
KEY
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

2

LAN RESERVED

1

1

TIP

7SH08FU

2

3

4

1

2

2

1

KILL_SW#

1

WL_OFF#

34,35

2

34

.1UF_X5R

U47

1

5

C683

.1UF_X5R

Compal Electronics, Inc
Title
MINI_PCI
AD[0..31]

AD[0..31] 20,23,25,26

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
B

Document Number
LA1432

Date:

星期五, 六月 07, 2002

Rev
1.A
Sheet

27

of

45

C218

C215

C226

CHB1608U301
1
2
L19
1
2
L20
C217 CHB1608U301

.1UF_X5R

.1UF_X5R

.1UF_X5R

.1UF_X5R

+5VOZ

29

CDD[0..15]

21

SDD[0..15]

X1
OSC1

OSC2
8MHZ
R216

CDD[0..15]
SDD[0..15]

21
21
21

SDA0
SDA1
SDA2

21
21

SDCS1#
SDCS3#

21
21

SDIOR#
SDIOW#

21

SDIORDY

20
21
21

IRQ15
SDDREQ
SDDACK#

20

SIDERST#

10UF_1206_10V
10K

34

2

58

44

68
70
66

SDCS1#
SDCS3#

63
61

SDIOR#
SDIOW#

99
6
72
93

HDIOR#
HDIOW#
HIOCS16#
HIORDY

CDIOR#
CDIOW#
CIOCS16#
CIORDY

74
12
88

HINTRQ
HDMARQ
HDMACK#

24
59

HRESET#
HDASPN

48
53
55
50
46

HSYNC
HBIT_CLK
HDATA_OUT
HDATA_IN
HACRSTN

28
36
35
34
37

PAV_EN
PLAY/PAUSE
FFORWARD
REWIND
STOP/EJECT

DM_ON
INTN

CD_INTA#

VDD

SDA0
SDA1
SDA2

DM_ON
PLAYBTN#
FRDBTN#
REVBTN#
STOPBTN#

29
25
30

CDD0
CDD1
CDD2
CDD3
CDD4
CDD5
CDD6
CDD7
CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

77
79
82
84
87
91
96
98
1
3
7
10
14
17
19
21

CD D0
CD D1
CD D2
CD D3
CD D4
CD D5
CD D6
CD D7
CD D8
CD D9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

HDA0
HDA1
HDA2

CDA0
CDA1
CDA2

69
71
67

CD_SBA0
CD_SBA1
CD_SBA2

HCS0
HCS1

CCS0
CCS1

64
62

CD_SCS1#
CD_SCS3#

100
5
73
94

CD_SIOR#
CD_SIOW#
CIOCS16#
CD _SIORDY

CHINTRQ
CDMARQ
CHDMACK#

75
13
89

CD_IRQ
CD_DREQ
CD_DACK#

CRESET#
CDASPN

23
60

SSYNC
SBIT_CLK
SDATA_OUT
SDATA_IN
SACRSTN

47
52
54
49
45

PWR_CTL

51

ISCDROM

80

GPIO[1]/VOL_UP
GPIO[0]/VOL_DN

39
40

1
R136
GPIO_1
GPIO_0

56
57

R130
@1K
1
2
MODE1

HDD0
HDD1
HDD2
HDD3
HDD4
HDD5
HDD6
HDD7
HDD8
HDD9
HDD10
HDD11
HDD12
HDD13
HDD14
HDD15

PCSYSTEM_OFF
INTN
RESET#

MODE0
MODE1

D4
4,33

1
Q6
2N7002

EC_SMD2

3

2
1

EC_SMC2

OSC1
OSC2

R139

2

Q5
2N7002

2

2

100K
+5VALW

SDATA

27

SCLK

3
1

4,33

26

31
32

OSCI
OSCO

R203
100K

38

CSN
INCN
UDN

41
42
43

CD_RSTDRV#
CDASPN

ISCDROM

CD_SCS1# 29
CD_SCS3# 29

RP5
GPIO_0
GPIO_1
INTN

29

1
2
3
4

8
7
6
5

8P4R-10K

CD_IRQ 29
CD_DREQ 29
CD_DACK# 29

RP6
STOPBTN#
PLAYBTN#
FRDBTN#
REVBTN#

CD_RSTDRV# 29

1
2
3
4

8
7
6
5
8P4R-10K
+5VCD
RP4

1
R126
1
R127

1
R138

2
@10K
2
10K
2
@0

CD D7
CD D6
CD D5
CD D4
CD D3
CD D2
CD D1
CD D0

+5VCD

ISCDROM

1
R137

0

2

MEDIA_DETECT 34

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9
@16P8R_4.7K

** No stuff R427 when stuff OZ163
** No stuff R424 and R320 when stuff OZ168

RP8
CD D8
CD D9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

2
10K

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16
@16P8R_4.7K

+5VCD

CD _SIORDY
CD_IRQ

+5VCD

8
7
6
5

8P4R-10K

CD_SIOR# 29
CD_SIOW# 29
CD_SIORDY

1
2
3
4

CDASPN
MODE1

16
33
65
85
92

+5VCD

PAVMODE

+5VCD
RP3

CD_SBA0 29
CD_SBA1 29
CD_SBA2 29

GND
GND
GND
GND
GND

2
1N4148

1

1

1
R143
1
R128

2
1K
2
4.7K

1
R129

2
47K

R217
100K

+5VCD

+5VCD
U41

1
2
3
4

+5VALW

+5VALW

R432
1

240K
2

S
S
S
G

D
D
D
D

8
7
6
5

C216
10U_1206

R218
100K

C543
.1UF_X5R

SUSP#
DM_ON#

1

SI4425DY
C539
DM_ON

2

DM_ON

CIOCS16#

35

Q7
CD D7

2

2N7002
CD_DREQ

1
R199
1
R211

2
10K
2
5.6K

Q8
2N7002

3

10K

1

2

R478

1

1
1U_0805

DM_ON

1

C540
1UF_0805

3

C547
10U_1206

Compal Electronics, Inc
SUSP#

2

22K

22K

22K
Q48
DTC124EK

2

CDPLAY

22K

CD_PLAY 34

Title
OZ-168 CD_PLAY

3

33,36,37,42 SUSP#

3

+5VCD

C224
R209
1

C229
10PF

VDD

76
78
81
83
86
90
95
97
2
4
8
11
15
18
20
22

SDDREQ
SDDACK#

+5VCD

U10
OZ168

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

1M
C228
10PF

VDD

9

+5VOZ

Q49
DTC124EK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
B

Document Number
LA1432

Date:

星期五, 六月 07, 2002

Rev
1.A
Sheet

28

of

45

IDE,CD-ROM Module CONN.
28

CDD[0..15]

CDD[0..15]

JP16

1

35
INT_CD_L
35
CD_AGND
28 CD_RSTDRV#

2

SHDD_LED#
1
2
R495
100K

2
470

CDCSEL

1

1
R243

CD_SIOW#
CD_SIORDY
CD_IRQ
CD_SBA1
CD_SBA0
CD_SCS1#
SHDD_LED#
+5VCD
+5VCD

PDA2
PDCS3#

PDA2
PDCS3#

R485
470

21
21

+5VS

10U_1210

C291

R503

W=80mils

2

CD_DACK# 28
10K
+5VS
CD_SBA2 28
CD_SCS3# 28
+5VCD

1

2

+5VCD

C546 .1UF_X7R_0603

1UF_25V_0805

10U_1210

C292

1

C557

1000PF

C568

C560

1UF_25V_0805

.1UF_X5R

2

1

C570

2

1
2
C688

1

+5VCD

+5VS

1000PF

PDIAG#

CD-ROM CONN.

OCTEK AFH-22DC

C293

CD_DREQ 28
CD_SIOR# 28

Place component's closely IDE CONN.

.1UF_X5R
+5VS

C282

1000PF

10U_1210

1

C286

C283

1UF_25V_0805

2

1

1

Place component's closely IDE CONN.

2

2
100K

PCSEL

28
28
28
28
28
28
34

CD D8
CD D9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

2

+5VS

PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

INT_CD_R 35

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

2

1
R244

IRQ14
PDA1
PDA0
PDCS1#
PHDD_LED#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

1

+5VS

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

2

PDDREQ
PDIOW#
PDIOR#
PDIORDY
PDDACK#
IRQ14
PDA1
PDA0
PDCS1#
PHDD_LED#

JP23

1

21
21
21
21
21
20
21
21
21
34

PDD[0..15]
PIDERST#
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

2

PIDERST#

1

PDD[0..15]

20

2

21

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

CD_RSTDRV#
CD D7
CD D6
R538
CD D5
CD D4
@0
CD D3
CD D2
CD D1
CD D0

C287
.1UF_X5R

Place component's closely FDD CONN.

+5VS
JP5
31

INDEX#

31,34
31

+5VS
RP122

8
7
6
5

1
2
3
4

FDD IR#
MTR0#
DSKCHG#
INDEX#

8P4R_1K

1
R236

2
1K

RP121
TRACK0#
WGATE#
WDATA#
STEP#
+5VS

6
7
8
9
10

5
4
3
2
1

WP#
RDATA#
HDSEL#

DRV0#
DSKCHG#

31

MTR0#

31
31
31

FDDIR#
3MODE#
STEP#

31

WDATA#

31

WGATE#

31

TRACK0#

31

WP#

31

RDATA#

31

HDSEL#

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

INDEX#
DRV0#
DSKCHG#

MTR0#
FDD IR#
3MODE#
STEP#
WDATA#
WGATE#
TRACK0#
WP#
RDATA#
HDSEL#

+5VS

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
85201-2605

Compal Electronics, Inc

DRV0#
10P8R_1K

Title
IDE/ FDD MODULE CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
B

Document Number
LA1432

Date:

星期五, 六月 07, 2002

Rev
1.A
Sheet

29

of

45

+USB_VCCA

+USB_VCCC

F4

F3

1

POLYSWITCH_0.75A

C661
.1UF_X5R 150UF_E

R294

1

1
C335

R301

1000PF

560K

2

560K

2

R527

1000PF

2

C620

1
1

L49
0_0805
L48
0_0805

JP19

1
2
3
4

2
2

21
21

USB3_DUSB3_D+

USB3_DUSB3_D+

1
1

L6
0_0805
L5
0_0805

2
2

1

1

L8
CHB4516G750_1806
4516

.1UF_X5R

2

C7

2

C285

.1UF_X5R

+USB_VCCB
F1

R276

+

C2
C14
.1UF_X5R 150UF_E
USB_BGND

2

470K

2

POLYSWITCH_0.75A

1

1

+5V

1

OVCUR#1

1

21

C326

R278

1000PF

560K

JP12

2

2
21
21

USB1_DUSB1_D+

USB1_DUSB1_D+

1
1

L4
0_0805
L3
0_0805

1
2
3
4
5
6
7
8

2
2

C6

2

L7
CHB4516G750_1806
4516

1

1

SUYIN 2553A-08G1T-D

2

2

L50
CHB4516G750_1806
4516

1

SUYIN USB Connector 2551A-0411

1

USB0_DUSB0_D+

2

USB0_DUSB0_D+

USB_CGND

OVCUR#3

1

1

21

21
21

C331
.1UF_X5R 150UF_E

470K

OVCUR#0

2

21

+

C1

2

USB_AGND

2

470K

+

C284

2

R528

2

1

POLYSWITCH_0.75A

1

+5V

1

+5V

.1UF_X5R

Compal Electronics, Inc
Title
USB & FIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
B

Document Number
LA1432

Date:

星期五, 六月 07, 2002

Rev
1.A
Sheet

30

of

45

A

B

C

D

E

SUPER I/O SMsC FDC47N227
1

1

21,33 LAD[0..3]

LAD[0..3]
U14
LAD0
LAD1
LAD2
LAD3
21,33
21

24
25

LFRAME#
LDRQ#

26
27

PCIRST#
LPCPD#

CLK_PCI_SIO

50
17
30
28
29

GPIO12/IO_SMI#
IO_PME#
SIRQ
CLKRUN#
PCICLK

CLK_SIO14

19

CLK14

48
54
55
56
57
58
59
6
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

GPIO10
GPIO15
GPIO16
GPIO17
GPIO20
GPIO21
GPIO22
GPIO24
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47

51
52
64

GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23/FDC_PP

18

VTR

53
65
93

VCC
VCC
VCC

7
31
60
76

VSS
VSS
VSS
VSS

PCIRST#

+3VS
20,23,33
SIRQ
21,23,25,27,33 CLKRUN#
12 CLK_PCI_SIO
12 CLK_14M_SIO
15,19
15,19
15,19
15,19

1
R242
1
R241

LAD0
LAD1
LAD2
LAD3

LFRAME#
LDRQ#1

6,13,20,23,24,25,26,27,33 PCIRST#
21
SUS_STAT#

2

20
21
22
23

1
R247

2
10K

1
R258

2
10K

PID0
PID1
PID2
PID3

2
10K
2
10K

+3VS

.1UF_X5R

C294
.1UF_X5R

1

1

C295

2

4.7UF_10V_0805
10V

2

C300

2

1

3

C298
.1UF_X5R

PD0/INDEX#
PD1/TRK0
PD2/WRTPRT#
PD3/RDATA#
PD4/DSKCHG#
PD5
PD6/MTR0#
PD7

68
69
70
71
72
73
74
75

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

BUSY/MTR1#
PE/WDATA#
SLCT/WGATE#
ERROR#/HDSEL#
ACK#/DS1#
INIT#/DIR#
AUTOFD#/DRVDEN0#
STROBE#/DS0#
SLCTIN#/STEP#

79
78
77
81
80
66
82
83
67

LPTBUSY
LPTPE
LPTSLCT
LPTERR#
LPTACK#

100
99
98
97
96
95
94
92

DTR1#
CTS1#
RTS1#
DSR1#
TXD1
RXD1
DCD1#
RI1#

89
88
87
86
85
84
91
90

IRMODE/IRRX3
IRRX2
IRTX2

63
61
62

RDATA#
WDATA#
WGATE#
HDSEL#
DIR#
STEP#
DS0#
INDEX#
DSKCHG#
WRTPRT#
TRK0#
MTR0#
DRVDEN0

16
10
11
12
8
9
5
13
4
15
14
3
1

DRVDEN1
GPIO11/SYSOPT

2
49

LPTBUSY
LPTPE
LPTSLCT
LPTERR#
LPTACK#
INIT#
LPTAFD#
LPTSTB#
SLCTIN#

32
32
32
32
32
32
32
32
32

LPD[0..7] 32

RP41
DCD#1
RI#1
CTS#1
DSR#1

CTS#2

1
2
3
4

+3VS

8
7
6
5

RP42
CTS#2
DSR#2
DCD#2
RI#2

+3VS

1
2
3
4

8
7
6
5
2

DSR#2
DCD#2
RI#2
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1
DCD#1
RI#1

8P4R_4.7K

1
R255

2
1K

8P4R_4.7K
+5V
JP21

1
R251

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

2
1K

IRMODE 35
IRRX
35
IRTXOUT 35
RDATA#
WDATA#
WGATE#
HDSEL#
FDD IR#
STEP#
DRV0#
INDEX#
DSKCHG#
WP#
TRACK0#
MTR0#

2
R257
1
R248

RDATA#
WDATA#
WGATE#
HDSEL#
FDDIR#
STEP#
DRV0#
INDEX#
DSKCHG#
WP#
TRACK0#
MTR0#
3MODE#

29
29
29
29
29
29
29,34
29
29
29
29
29
29

1
10K
2
1K

+5VS

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
9
10
@96212-1011S

3

Base I/O Address
* 0 = 02Eh
1 = 04Eh

SMsC LPC47N227

2

CLK_PCI_SIO

2

CLK_14M_SIO

DTR2#
CTS2#
RTS2#
DSR2#
TXD2
RXD2
DCD2#
RI2#

LPD[0..7]

R259

R256
@33

2 1

2 1

10

1

15PF

C299

1

C301

4

4

@22PF

Compal Electronics, Inc.
Title
PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

D

LPC SUPER I/O SMSC FDC47N227
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

31

of

45

.1UF_X5R

FAN1

2
JP13

1

U15

1
3

1
2
3

D17
1N4148
Q31
2SA1036K

4
1
2
R273
13K_1%_0603

2

1N4148

10UF_1206

1SS355

53398-0310-FAN

2

EN_DFAN

EN_DFAN

2
.1UF_X5R

C344

D16

E

1

1
C332

.1UF_X5R
VCC

33

Q29
2SC2411K

D18

5

2

C330

2
B
C325

3

1

2

C

2

1

+5VALW

1

1

3.6K

FAN CONN.
1

+5VALW
R275

2

1

+12VALW

2

VEE LMV321_SOT23-5

1
2
R286
7.32K_1%_0603

33

FAN_SPEED

2
R279

1
10K

+3VS

+5V_PRN

PARALLEL PORT

AFD#/3M#
F D0
LPTERR#
F D1

10
9
8
7
6

+5V_PRN
CP4
RP44
10P8R-2.7K

D11
+5VS

2

1

1
2
3
4
5

RB420D

+5V_PRN
31

F D3
LPTSLCTIN#
F D2
LPTINIT#

LPTSTB#
AFD#/3M#

31

INIT#

1

2

31

SLCTIN#

1

R266
33
2

+5V_PRN

LPTINIT#

31

LPTAFD#

31

LPTERR#

LPTSLCTIN#

F D0
LPTERR#
F D1
LPTINIT#
F D2
LPTSLCTIN#
F D3
F D4

10
9
8
7
6

F D5
RP46
RP43
10P8R-2.7K

LPD0
LPD1
LPD2
LPD3

8
7
6
5

F D6
F D0
F D1
F D2
F D3

1
2
3
4
8P4R-68

1
2
3
4
5

LPD4
LPD5
LPD6
LPD7

+5V_PRN

RP45

8
7
6
5

F D7
F D6
F D5
F D4

1
2
3
4

F D4
F D5
F D6
F D7

F D7
31

LPTACK#

31

LPTBUSY

31

LPTPE

31

LPTSLCT

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

C311
220PF

R262

1
2
3
4

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

4
3
2
1

8P4C-220PF
CP1
5
6
7
8

LPTINIT#
F D2
LPTSLCTIN#
F D3

1
2
3
4

8P4C-220PF
CP3
8
7
6
5

F D4
F D5
F D6
F D7

1
2
3
4

8P4C-220PF
CP2
8
7
6
5

33
R261

R267
33

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

LPTSTB#

R263
2.2K

AFD#/3M#
F D0
LPTERR#
F D1

33

1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13

8
7
6
5

8P4C-220PF
JP8
LPTCN-25

8P4R-68

31

LPD[0..7]

LPD[0..7]

Compal Electronics, Inc.
Title
PARALLEL PORT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
B

Document Number
LA1432

Date:

星期五, 六月 07, 2002

Rev
1.A
Sheet

32

of

45

3

2

+3VALW

51AVCC

+RTCVCC

34
34

51AVCC

KBA[0..18]
ADB[0..7]

KBA[0..18]
ADB[0..7]

1

C559

21

PME#
ATF_INT#

ATF_INT#

MP3#

R431
10K

PACIN
R_RING#

PACIN

2

39,40,41
23,25,26,27 1394_PME#
23,25,26,27 PCM_PME#
23,25,26,27 WLANPME#
23,25,26,27 LAN_PME#

21

RING# 1
R494
1
R493

RING#
+3V

ECAGND

2
@0
2
10K

21

R_RING#

ECSMI#

ECSMI#

VGA_SUSP#
G_RST#
21

EC_RIOUT#

A/B#USE

BATT_TEMPA
2
.01UF

1
C519

SCR_LED#

35
NUM_LED#
35
CAPS_LED#
35 ARROW_LED#

PME#

C

23

SLP_S3#

43

BATT_TEMPA

40

BATT_OVP

BATT_TEMPA

BATT_TEMPB
VBATTB

2
C500

1
0.22UF_0603

40
21,36
21

43

ALI/MH#

1
R400

ADP_I
ON/OFF
SLP_S5#

BLI/MH#
BATT_CHGI

2
1M

AD_BID0
AD_BID1
19

DAC_BRIG

VOL_AMP
40
32

IREF
EN_DFAN

B

21,31

+5VALW

2 EC_SMC2
4.7K
2 EC_SMD2
4.7K

1
R429
1
R480

LAD[0..3]

LAD0
LAD1
LAD2
LAD3

1
R489

2 ECRST#
4.7K

1
R491

21,23,25,27,31 CLKRUN#

+3VALW

R395

R403

Rc

12

100K

1

R408

C508

81
82
83
84

AD0
AD1
AD2
AD3

87
88
89
90
2
44

IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
IOPE4/SWIN
IOPE5/EXWINT40

93
94

DP/AD8
DN/AD9

99
100
101
102

DA0
DA1
DA2
DA3

105
106
107
108
109

TINT#
TCK
TDO
TDI
TMS

15
14
13
10
9
8
7
19
22
23
24
25

CLK_PCI_EC

VBAT

AVCC

LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
SERIRQ
LREST#
SMI#
PWUREQ#
IOPE6/LPCPD#/EXWIN45
IOPE7/CLKRUN#/EXWINT46
IOPD3/ECSCI#
GA20/IOPB5
KBRST#/IOPB6
LCLK

1
C572
@22PF

2

1
R490
@33

2

113
112
104
103
48

KBA16
KBA17
KBA18

IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7

138
139
140
141
144
145
146
147

IOPJ0/RD#
IOPJ1/WR0#

150
151

SELIO#

152

SEL0#
SEL1#

173
174

IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15

148
149
155
156
3
4
27
28

PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7

110
111
114
115
116
117
118
119

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA
TP_CLK
TP_DATA
LID_SW#
MODE#

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

71
72
73
74
77
78
79
80

KSI0
KSI1
KSI2
KSI3

KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68

2

0

ECAGND

.1UF_X5R

C501
.1UF_X5R
ECAGND

FSTCHG

40

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

+5VS

TP_CLK
TP_DATA
FRD#
FWR#

SELIO#

SYSON
SUSP#
VR_ON

TRICKLE
RSMRST#

34
34

2
R402
2
R401

1
10K
1
10K

34

FSEL#

34

SYSON
SUSP#
VR_ON

37,42
28,36,37,42
44

ENVEE
ENBKL

C

RP84

SELIO#

PS2_DATA
PS2_CLK
KBD_DATA
KBD_CLK

1
2
3
4

8
7
6
5
8P4R-10K

**

RSMRST# 21,22,36

ENBKL

+3VALW

14,19
19

KBA1

KBD_CLK 36
KBD_DATA 36
PS2_CLK 36
PS2_DATA 36
TP_CLK
35
TP_DATA 35
LID_SW# 36
MODE#
35

1
R407

2
1K

R406
1
R396

@1K
2
1K

KBA2
KBA3
KBA5
R405
1
R399
MODE#
1
R398
RSMRST# 1
R487

1K
2
10K
2
10K
2
10K

LID_SW#

KSI0
KSI1
KSI2
KSI3

35,36
35
35
35

KSO0

36

B

J3
KSO0 2

1

KSI0

I/O Address
@JOPEN

BADDR1(KBA3) BADDR0(KBA2)

*

Index

Data

0

0

2E

2F

0

1

4E

4F

1

0

1

1

(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
Reserved

R422
C RY1

158

C RY1

32KX2

160

C RY2

CLK

.1UF_X5R

KBA19

32KX1/32KCLKOUT

1

2

C RY2

20M_0603

ENV0 (KBA0)
R424
510K

X3

47

PC97591VPC
L45

Rd
2

.1UF_X5R

IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS#
IOPJ6/PLI
IOPJ7/BRKL_RSTO#

18

AD_BID1

1
C506

2

47K

2

R397

Rb

1

1

AD_BID0

62
63
69
70
75
76

IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1#

1

2

100K

2

Ra

IOPD0/RI1#/EXWINT20
IOPD1/RI2#/EXWINT21
IOPD2/EXWINT24
IOPD4
IOPD5
IOPD6
IOPD7

ECSCI# 31
G20
5
RCL#
6

ECSCI#

1

1

21

A

2
@0
ECRST#

+3VALW

26
29
30
41
42
54
55

LAD[0..3]

21,31 LFRAME#
21
LDRQ#0
20,23,31
SIRQ

+3VALW

IOPC0
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT

KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15

2

1

**

168
169
170
171
172
175
176
1

143
142
135
134
130
129
121
120

1

+3VALW

EC_SMC2
EC_SMD2

IOPK0/A8
IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13/BE0
IOPK6/A14/BE1
IOPK7/A15/CBRD

32.768KHZ
C525
10PF

1

21
PBTN_OUT#
4,28
EC_SMC2
4,28
EC_SMD2
32 FAN_SPEED

RB751V

IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPB7/RING#/PFAIL#

C534

D

2

RCL#

D30

2

RC#

EC_URXD/KSO16153
EC_UTXD/SKO17 154
EC_USCLK
162
EC_SMC1
163
EC_SMD1
164
165

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10

1

RB751V

20

PCM_SUSP#

10 EC_URXD/KSO16
10,35 EC_UTXD/KSO17
10
EN_USCLK
34,43 EC_SMC1
34,43 EC_SMD1
6,13,20,23,24,25,26,27,31 PCIRST#

AGND

G20

124
125
126
127
128
131
132
133

11
12
20
21
85
86
91
92
97
98

GATEA20

1

96

1

D29

2

IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7

GND1
GND2
GND3
GND4
GND5
GND6
GND7

R498
10K

1

R499
10K

20

40
ACOFF
21
BATTLOW#
36
ECON
21 EC_LID_OUT#

2

2

D

32
33
36
37
38
39
40
43

IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6
IOPH7/A7

2

For PWM EN_DFAN

VDD

INVT_PWM

INVT_PWM
BEEP#

17
35
46
122
137
159
167

19
35

+3VS

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

2

U40

95

.1UF_X5R

+3VALW
L46
1
2
CHB1608U800

+RTCVCC

161

1000PF

34
45
123
136
157
166

C516

16

1000PF

1

C504

2

.1UF_X5R

1

C530

2

.1UF_X5R

1

C536

2

.1UF_X5R

1

1

C563

2

.1UF_X5R

2

1

C544

2

2

1

+3VS

1

1

4

+3VALW

2

5

C529
12PF

IRE
* OBD
DEV
PROG

0
0
1
1

ENV1 (KBA1)

TRIS (KBA4)
0
0
0
0

0
1
0
1

SHBM(KBA5)=1: Enable shared memory with host BIOS
TRIS(KBA4)=1: While in IRE and OBD, float all the
signals for clip-on ISE use

Compal Electronics, Inc.

1
2
CHB1608U800

Title
EC PC87591
PROPRIETARY NOTE

Analog Board ID definition, Please see page 2.
5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

2

Document Number
LA1432
星期五, 六月 07, 2002

Rev
1.A
Sheet
1

33

of

45

A

+3VALW
C518

1

+5VALW

2

2
R412

1
10K

+3VALW

KBA1

9
8

SELIO#

SELIO#

20
+3VALW
RP2
DD
AA
BB
CC

C205

1
2
3
4

8
7
6
5

1

+3VALW

2

.1UF_X5R

8P4R_100K

KBA2

4

SELIO#

5

U6B
74LVC32

6

74LVC244

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

3
4
7
8
13
14
17
18

D0
D1
D2
D3
D4
D5
D6
D7

AA
LARST#

11
1

CLK
CLR

CC

10

R411
+5VALW

U35
2
5
6
9
12
15
16
19

VCC

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

7

33

1G
2G

10

14

U6C
74LVC32

1
19

18
16
14
12
9
7
5
3

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

1

PWR_SUP_LED# 35
MDC_DN# 35
WLKB
36
WL_OFF# 27

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

10

29 SHDD_LED#
29 PHDD_LED#
29,31
DRV0#

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

14

PCM_LED

2
4
6
8
11
13
15
17

VCC

1
10K

7

CD_INTA#

2
R421

CD_PLAY 28
HDD_LED# 35
CD_FDD_LED# 35

GND

20
28

1
10K

2

.1UF_X5R
U36

GND

2
R420

C490

1

.1UF_X5R

74HCT273

C511

2

1

1UF_25V_0805

1

20K

2

R417

** No stuff R8 when stuff OZ168

+5VALW

2
KILL_SW#

1
10K

+3VALW

KBA3

12

SELIO#

13

1G
2G

VCC

1
19

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

10

14

U6D
74LVC32

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

+3VALW

KBA4

U6A
74LVC32

1
3

SELIO#

2

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

3
4
7
8
13
14
17
18

D0
D1
D2
D3
D4
D5
D6
D7

BB
LARST#

11
1

CLK
CLR

74LVC244

U5

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

2
5
6
9
12
15
16
19

PWR_LED# 35
CDON_LED# 35
MP3_LED# 35
BATT_LOW_LED# 35
PCMRST# 24
BATT_CHGI_LED# 35

74HCT273

DD

7

11

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

GND

27,35

2
R111

1
10K
1
10K

2
4
6
8
11
13
15
17

20

.1UF_X5R
U8
18
16
14
12
9
7
5
3

2
28 MEDIA_DETECT

1
10K 2
1 R123
10K 2
R125
1
10K 2
R110

VCC

@100K

2
R122
2
R124

2
.1UF_X5R

2

7

DAN202U

1

10

R109

C485

1

C207

14

+3VALW

20

23 PCM2_LED

2

PCM_LED

3

1

1

GND

100K

D28
23 PCM1_LED

+5VALW
+5VALW +5VALW

+5VALW

1

+3VALW +3VALW

D

1

1

2N7002

FLASH#
FWR#

21
33

33,43
33,43

1

R481

R482

4.7K

4.7K

EC_SMC1
EC_SMD1

2
.1UF_X5R
U38
8 VCC
7 WC
6 SCL
5 SDA

R423
100K

A0
A1
A2
GND

1
2
3
4

NM24C16

1

U33
7SH32FU

Q47
3

2

2
G

2

5
2
4

+3VS

3

FWE#

2
10K

2

1

1

1

R410
R404
100K

S

1
2
C493
.1UF_X5R

2

1

C533

2

R428
100K

C450
1
2

1
R374
1
R373
FLASH_VCC

2
@0
2
0

+5VALW

1
C453

+3VALW

U27

.1UF_X5R
KBA11
KBA9
KBA8
KBA13
KBA14
KBA17
FWE#
KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A11
A9
A8
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
A6
A5
A4

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

2
.1UF_X5R

U29

U28

FR D#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
KBA0
KBA1
KBA2
KBA3

FRD#

33

FSEL#

33

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
ADB0
ADB1
ADB2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS

VCC
WE*
A17
A14
A13
A8
A9
A11
OE*
A10
CE*
DQ7
DQ6
DQ5
DQ4
DQ3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

FWE#
KBA17
KBA14
KBA13
KBA8
KBA9
KBA11
FR D#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3

KBA11
KBA9
KBA8
KBA13
KBA14
KBA17
FWE#

FLASH_VCC

FLASH_VCC

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A11
A9
A8
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
A6
A5
A4

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

FR D#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
KBA0
KBA1
KBA2
KBA3

Compal Electronics, Inc

@29F040_TSOP
29F040/SST39VF040_PLCC

Title
BIOS & EXT. I/O PORT

33
33

KBA[0..18]
ADB[0..7]

@SST39VF040_TSOP
KBA[0..18]
ADB[0..7]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
B

Document Number
LA1432

Date:

星期五, 六月 07, 2002

Rev
1.A
Sheet

34

of

45

4

HDD_LED#

34
10K

1

C

R_HDD_LED#

2

34 BATT_CHGI_LED#
10K

B

34
10K

C

1

R_PWR_LED#

R_BATT_LOW_LED#

C

MP3_LED#

E

47K

MODE#
MP3_FRDBTN#
MP3_REVBTN#
R_CDON_LED#
R_MP3_LED#
ACIN_LED
R_PWR_LED#
R_PWR_SUP_LED#

+5VALW

R_BATT_CHGI_LED#
R_BATT_LOW_LED#
R_HDD_LED#
WIRELESS_LED#
R_CD_FDD_LED#

DTA114YKA

2
10K

C

R_BATT_CHGI_LED#

C

R_MP3_LED#

36,39
33
33,36

+5VALW

ECON#
MP3_STOPBTN#
MP3_PLAYBTN#

ECON#
KSI1
KSI0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

D

85201-2605

ACIN_LED

3

WIRELESS_LED#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

TP_CLK
TP_DATA

TP_CLK
TP_DATA

+5VS
10,33 EC_UTXD/KSO17
33
MODE#
33
KSI3
33
KSI2

R_PWR_SUP_LED#

Q18

DTA114YKA

2

1

34 BATT_LOW_LED#

E

47K

B

33
33

10K

C

Q10

DTA114YKA

DTA114YKA

2

3

3
E

47K

B

E

+5VALW

Q16
47K

B

DTA114YKA
34 PWR_SUP_LED#

10K

+5VALW

3

+5VALW

PWR_LED#

47K

2

C

R_CD_FDD_LED#

D

B

Q13

1

34
10K

DTA114YKA

1

34 CD_FDD_LED#

47K

B

2

1

DTA114YKA

2

JP6

Q17
E

1

47K

B

Q15
E

1

+5VALW

3

Q9
E

2

+5VALW

3

+5VALW

3

+5VALW

3

3

5

27
10K

Q14

C

1

C

D

2
G

RF_OFF#

21,36,39

D

S

Q12

2
G

ACIN

2N7002

S

1

1

DTA114YKA

2

CDON_LED#

3

34

E

3

Q11
47K

B

2N7002
JP3

R_CDON_LED#

+3VS

+3VS

+3VS

29
29
29

CD_AGND
INT_CD_L
INT_CD_R

28

DM_ON

B
33

3
B

2

CAPS_LED#

33 ARROW_LED#
10K

10K

C

1

1

MD_SPK
E

MD_MIC
IAC_RST#
I AC_SYNC
IAC_SDATAO

21
IAC_RST#
21
IAC_SYNC
21 IAC_SDATAO
21 IAC_SDATAI0
21
IAC_BITCLK
+5VS

C

31
31
31

R537
120_0603

2

R536
120_0603

2

R535
120_0603

47K

2

1

C

1

10K

E

1

2

NUM_LED#

47K

Q56
DTA114YKA

IAC_BITCLK

1

B
33

E

Q55
DTA114YKA

IRRX
IRTXOUT
IRMODE
+3VS

2

47K

3

3

MONO_IN_R
Q54
DTA114YKA

27,34
R_NUM_LED# 36

R_CAPS_LED# 36

R_ARROW_LED# 36

KILL_SW#
+3V
+5VCD

B

+3V

C

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

+3V

B

Aces 85201-3005

1

1

C258
2

.1UF_X5R

14

R226
100K

2

U12A

1

R228

2

560

JP15
MD_MIC

C253
1
2

PCM_SPK#

+3V
+3VS

L43
CHB1608U121
1
2 +3VS_MDC
IAC_SDATAO
IAC_RST#

U12B

560

MONO_IN_R

2
R230
10K

+3V
D9
RB751V

+3VS_MDC

+5VS_MDC

1

1

1UF_10V_0603

R229

C456

2

2

74LVC14
+3V POWER

C252
1
2

1UF_0805

C455
1UF_0805

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

MDC_DN# 34

MD_SPK
+5VS_MDC 1
L44

1
R84
R85

1
1
R86

2
CHB1608U121

+5VS

2
10K

+3VS

I AC_SYNC
2 @22
2
22
IAC_BITCLK

IAC_SDATAI1 21

AMP 108-5424

C457

2

4

7

2

1UF_10V_0603 560

1

3

A

1

R227

2

14
SPKR

1

1UF_10V_0603

+3V POWER

+3V

21

C251
2

1

.22UF_0603

2
74LVC14

1

C250

1

2

23

2
8.2K

7

+3VALW POWER
U11B
74LVC125

1
R225

1

6

2

5

1

BEEP#

4

33

A

Compal Electronics, Inc.

1UF_0805
Title
Switchs & Connectors

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Size
B

Document Number
LA1432

Date:

星期五, 六月 07, 2002

Rev
1.A
Sheet
1

35

of

45

5

4

3

2

1

J4

J8 Close to connector of SO-DIMM on bottom side.

1

@JOPEN
Q_KB_DOCK#

+5VALW_RX JP7

J1

J6 Close to connector of
Receiver board on top side.

2

2

2
R376

1
470K

100K

1

3

2

WL_ON/OFFBTN#

2
R254

ON/OFFBTN#
1
2N7002

3

Q40
1
10K

2
R378
1

1
100K
ON/OFF

2

ECON#

D21

D

KBD_ON/OFFBTN#

33
KBD_CLK
33
KBD_DATA
33
PS2_CLK
33
PS2_DATA
28,33,37,42 SUSP#

Power Button

3

+5VALW_RX

+3VALW
ON/OFF

21,33

ECON#

35,39

+5VS

2
4
6
8
10
12
14
16

RF_DATA

@JOPEN

2

SUSP#

1
3
5
7
9
11
13
15

R_NUM_LED# 35
R_CAPS_LED# 35
ACIN
21,35,39
R_ARROW_LED# 35
1
2
+5VALW
R253
100K

Q_KB_SYNC#/RF_OFF#
WL_ON/OFFBTN#

D

ACES 88018-1600
100K

100K

1
100K
1

1

1

2
R250

+3VALW

2
4.7K

1

33
33,35

RLZ20A

KSO0
KSI0

C476

@ACES 85205-0400

22K
B

22K
DTC124EK

1

U30
Q_KB_DOCK#
R_RF_DATA
RF_DATA

E

R375
33K

ECON

ECON

2 2

1000PF

KB_SYNC#/RF_OFF#

+5VALW

1
2
3
4

KB_SYNC#/RF_OFF#
R_KB_SYNC#/RF_OFF#

1
2
3
4
5
6
7

OE1#
1A
1B
OE2#
2A
2B
GND

14
13
12
11
10
9
8

VCC
OE4#
4A
4B
OE3#
3A
3B

2
.1UF_X5R

Q_KB_DOCK#
SUSP

KB_SUSP

37

1

33

1
R379

C477

Q44

C

2

1
2N7002

ON/OFFBTN#

D26

2

3

2

Q21

JP24

1

1
2

3

SUSP#

Q26
DTC115EK

100K

3

100K

+5VALW_RX

Q23
DTC115EK

2

DAN202U

3

RTCVREF

100K

Q41
DTC115EK

1

1

2

D

3

S

FST3125

2
G
2N7002
Q38

+5VALW

+5VALW

C

C

+5VALW_RX

2
R246

1
100K

B+

2
R245

1
100K

D

S Q22
2N7002

OUT
SNS
SHDN
GND

1

S Q19
2N7002

S Q57
2N7002

R_RF_DATA

5

2

D35
RSMRST#

3

3

ACIN

2

KB_SUSP

R540
DAN202U

2

6

1

100K

33

LID_SW#

2

3

.1UF_X5R

4

2

HCH MPU-101-6DB

1

A

Q43
SI2301DS
.1UF_X5R

+5V_KBD

C478

Compal Electronics, Inc.

2

C452

1

2

1

2
1

C

E

1

Q39
FMMT3904

1

DAN202U
C451

B

2

R381
100K

3

2

1

2
100K

SW1

1
3

+5VALW

2

+5VALW

Lid Switch

D27
RX_LDO_OFF#

Q_KB_DOCK# 3

2

B

2
G

R_KB_SYNC#/RF_OFF#

PACDN045

R391
10K

+

Title

5

1

Wireless K/B Interface
4.7UF_1206
10V

2

A

1UF_25V_1206

1

1

3

4

KBD_ON/OFFBTN#

1
R380

B+
C296

D22
D_KB_DOCK

21,35,39

+5VALW

8
7
6
5

MIC2951

2
G

D

IN
FB
TAP
ERR#

3
100K

1
2
3
4

3

1

D

2
G
3

D_KB_DOCK

D25
PSOT03C

2

B+

RX_LDO_OFF#

RTCVREF

1
Q20
DTC115EK

100K

2

0.78RbCa <= tL->H
<=1.43RbCa

Pull High for
D_KB_DOCK

SUYIN 250012MA009S100ZX

1
10K
U13

3
2
10K

2
R252

0.58(Ra+Rb)Ca <= tH->L
<=1.28(Ra+Rb)Ca

GND for R_KB_SYNC#/RF_OFF#

+5VALW

1

C297
1UF_10V_0603

2

NC7SZ14M5X

100K

1
R390

RSMRST#

1

3

U34

Q25
SI2301DS
3
1

2

Q45
DTC115EK

100K

Q_KB_DOCK#

1

2

5
2

100K

100K

DTC115EK

D_KB_DOCK
R_RF_DATA
KBD_ON/OFFBTN#
R_KB_SYNC#/RF_OFF#
KB_SUSP

1

2
1

2

4

Ca

1

1

JP2

B

KB_DOCK#

2

Rb

2

3

2

1K

2
.1UF_X5R
21,22,33 RSMRST#

2
1K

C492
1UF_X7R_0805

Q42

1
2
3
4
5
6
7
8
9

1

3

2

3

3

DAN217

100K
1
R393

RX_LDO_OFF#

1
D24

10K

D23
DAN202U

R539

+5V_KBD

R388

Ra
2

1

R389

C491

2N7002

1

+5VALW

1

1

G

Q58

2

WLKB

D

34

S

3

+5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Size
B

Document Number
LA1432

Date:

星期五, 六月 07, 2002

Rev
1.A
Sheet
1

36

of

45

A

B

C

D

E

+3V
5VS_GATE
C535
.01UF

SYSON_ALW

SI4800
+

C426

R364

.01UF

@1M

2N7002
Q33

R365

+12VALW

100K

S
S
S
G

+

C537

SI4800

2

+

SYSON#

Q35
2N7002
2 SYSON#

+1.8VS

1
2
3
4

2

4.7UF_1206

C532
4.7UF_1206
16V

SYSON#

Q50
2N7002

1

C541
1UF_0805

16V

2

C444
10UF_1206
6.3V

1

S
S
S
G

+1.8VALW
U39
8 D
7 D
6 D
5 D

3

D
D
D
D

1

1

1
2
3
4

R521
470_0805

3

U23

8
7
6
5

1

C423
10UF_1206
6.3V

+3VALW

R367
470_0805

C427
1UF_0805

3

+

1

+3V

+5V

+1.5VS

C597
10UF_1206
6.3V

1
R522

C612
.01UF

2N7002

@1M

Q51

+12VALW
100K
2 SUSP

D
D
D
D

S
S
S
G

C538
4.7UF_1206
16V

+

C527
4.7UF_1206

Q34
2N7002
2 SUSP

R524
470_0805

Q37
2N7002
2 SUSP

R529
470_0805

Q52
2N7002
2 SUSP

1

+2.5VS

1
2
3
4

SI4800
+

2

2

+5VS

2
3

R523
5VS_GATE

1

+

8
7
6
5

R370
470_0805

1

+2.5V
U37

SI4800

+3VS

3

1
2
3
4

3

S
S
S
G

3

D
D
D
D

1

C607
10UF_1206
6.3V

U44

8
7
6
5

R362
470_0805

C614
1UF_0805

1

C522
.01UF

+3VALW
+

+1.8VS

5VS_GATE

3

+3VS

SUSP

Q53
2N7002

C523
1UF_0805

16V

2

+5VALW
+5VALW

+5VS
U45

S
S
S
G

R368
10K
+
C667
4.7UF_1206
16V

SI4800
+

C609
4.7UF_1206
16V

C666
1UF_0805

SYSON#

1

D
D
D
D

1
2
3
4

33,42

SYSON

SYSON

2
Q36
2N7002

3

8
7
6
5

5VS_GATE

C619
.01UF

3

3

+5VALW

+5V
U43

8
7
6
5

D
D
D
D

S
S
S
G

1
2
3
4

+

SI4800
+

C596
4.7UF_1206

C598
4.7UF_1206
16V

C601
1UF_0805

16V

+5VALW

SYSON_ALW
R249
10K

C608
.01UF
SUSP

SUSP

1

36

SUSP#

2
Q24
2N7002

3

28,33,36,42 SUSP#

4

4

Compal Electronics, Inc.
Title
PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

D

POWER CONTROL CKT
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

37

of

45

A

B

C

D

E

+3V

74LVC14

47K

U12D

2

7

R233

2

9

330K

2

1

+3V

U12E

13

12

11

100K

D31

10

U11D
74LVC125

2

12

11

SYS_PWROK 21

+3VALW POWER

1N4148

7

C260

1

74LVC14

7

74LVC14

1

13

14

U12F

1

H11
Fan Fixed Position Hold

R235

2

H10
Fan Fixed Position Hold

+3VS

2

H18
Fixed Position Hold

2

H17
Fixed Position Hold

+3V

R234
470K

1N4148

1

t=0.51RC
14

D32

.1UF_X5R

1

1

1

+5VS

8
74LVC14

C259

7

1

1

H23
Fixed Position Hold

+3V
R232

6

14

5

1

14

+5V
U12C

R231

ST1
StandOff 6.5X4.2

ST2
StandOff 6.5X4.2

2

2
1

1
1

1

1

10K
1UF_X7R_0805

H2
StandOff 7.5X3.7

H5
StandOff 7.5X3.7

ST4
StandOff 8X0X4.2 NPTH

ST5
StandOff 8X0X4.2 NPTH

ST3
StandOff 8X0X4.7 NPTH

RTC BATT

1

1

1

1

1

1

2

1

2

-

H6
H7
H14
H15
CPU SCREW 8x4.5 CPU SCREW 8x4.5 CPU SCREW 8x4.5 CPU SCREW 8x4.5

+

BATT1

2

1

+RTCBATT

1

1

1

1

1

RTCBATT

D33
HSM1265

H9
SCREW 8x2.8

3

H16
SCREW 8x2.8

2

+RTCVCC
H8
SCREW 8x2.8

1

1

1

CHGRTC
C671
.1UF_X5R

3

3

H24
SCREW 8x2.9

H13
SCREW 8.5x3.0

H27
SCREW 8.5x3.0

H28
SCREW 8.5x3.0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

CF3
CF9
CF13
CF1
CF2
CF4
CF19
CF12
CF11
CF20
CF27
CF28
CF7
CF8
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80

H1
SCREW 8.5X3.0

H25
SCREW 8.5X3.0

H4
SCREW 8.5X3.0

H22
SCREW 8.5X3.0

H21
SCREW 8.5X3.0

FD3
FIDUCAL

FD4
FIDUCAL

1

1

1

1
FD6
FIDUCAL

FD1
FIDUCAL

1

1

1

1

1

1

1

1

1

H20
SCREW 8.5X3.0
PAD1

1

1

1
H26
SCREW 8.5X3.0

1

4

FD2
FIDUCAL

1

1

1

FD5
FIDUCAL

1

1

1

1

1

1

1

1

H12
SCREW 8.5X2.8

1

H19
SCREW 8.5X2.9

1

CF5
CF6
CF23
CF26
CF14
CF16
CF17
CF10
CF22
CF25
CF21
CF24
CF18
CF15
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80
H3
SCREW 8.5X2.9

PAD10

PAD11

4

PAD12

1

1

1

1

EMI PAD-4.5X3.2

EMI PAD-4.5X3.2

EMI PAD-4.5X3.2

EMI PAD-4.5X3.2

Compal Electronics, Inc.
Title

PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

D

RESET
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet
E

38

of

45

A

B

C

D

VS
VIN

PR1
1M_1%

2

1
1

2

PC6
0.1UF_50V

2

-

ACIN

21,35,36

PACIN

33,40,41

1

PACIN

1
1

PR6
20K_1%

+

1

PC5
PC4
1000PF_50V
100PF_50V

PC3
1000PF_50V

2

PZD1
RLZ4.3B

PR7
10K

Vin Detector

2

1
PR8
10K

2

2

2

PC2
100PF_50V

3

4

PC1
1000PF_50V

1

LM393M

2

PD1
EC10QS04

2
2DC-S107B200

1

2

3

2

3

2

1

1

1

PU1A

PR5
22K

2

1

4

PR4
1K

10K

2

2

1

PR2

PR3
84.5K_1%

8

PCN1

VS

1

VIN

PL1
CHC4532U800_1812

PF1
7A 24V UL/CSA FAST 1206

1

1

1

High 18.764 17.901 17.063
Low 17.745 16.903 16.038

RTCVREF

3.3V

2

VIN

PD2
1N4148

2

BATT+

PR9
1K_1206

1

PD3
RB751V

1
PR10

2

33_1206
PZD2
RLZ6.2C
2
1

VS

PD4
1N4148

PQ1
TP0610T
3
1

N1

2

VIN

PR11
1K_1206
N3

1

1

1

2

1

2

PC7
0.22UF_1206_25V

B+

1

PC8
0.1UF_0805_25V

2

2

2

PR12
100K

2

PR13
1K_1206

1

CHGRTCP

2

1

2

2

7

RB715F

3.3V
N2

PZD3
RLZ6.2C

PC12
1UF_0805_25V

PZD4
RLZ16B

2

3.3V
PR23
47K

2

PJP2

2

+2.5V

(6A,240mils ,Via NO.= 12)

+1.5VS

(2A,80mils ,Via NO.= 4)

1

+1.25VSP

PAD-OPEN 3x3m

2

+1.25VS

PAD-OPEN 3x3m

PJP3

1

(3A,120mils ,Via NO.= 6)

Precharge detector
15.34
15.90
16.48
13.13
13.71
14.20

2
G

2

100K

PAD-OPEN 3x3m
PQ3
DTC115EK

PJP4

1

+1.8VALW

(3A,120mils ,Via NO.= 6)

+12VALW

(120mA,20mils ,Via NO.= 1)

PACIN

2

+5VALWP

100K

3

+1.8VALWP

2

1

S

1

+1.5VSP

PQ2
2N7002

3

PJP1

1

3

RTCVREF

D

+2.5VP

PC9
1000PF_50V

2

2

PR19
499K_1%
PR21
215K_1%

1

PC13
10UF_1206_10V

1

1

PR22
200

2

PR20
10K

1

3

2

3

6

2

2

1

1

CHGRTC

5

-

PC10
1000PF_50V

2

3

+

1

3
2

1

200_0805

S-81233SG (SOT-89)

ACON

1

40

1

PR18

PU2

PR17
499K_1%

PU1B
LM393M

1

1

RTCVREF

1

2

PON
PD5

4,41,43 MAINPWON

1

PR16
1M_1%

6.0V

2

1

1

2

PR15
10K
VS

2

2
PR14
22K

PC11
0.1UF_16V

1

ECON#

2

35,36

PAD-OPEN 3x3m
PJP5
4

+12VALWP

2

PJP6

1

2

+1.2VPP

PAD-OPEN 2x2m
PJP7
+5VALWP

1

2

+5VALW

(5A,200mils ,Via NO.= 10)

1

+1.2VP

4

(300mA,40mils ,Via NO.= 2)
Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
Size
Document Number
B
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
Date: 星期五, 六月 07, 2002

PAD-OPEN 3x3m
PJP8
+3VALWP

1
PAD-OPEN 2x2m

2

+3VALW

DCIN & DETECTOR

(5A,200mils ,Via NO.= 10)

PAD-OPEN 3x3m
A

B

C

Rev

LA1432

1.A
Sheet

D

39

of

45

A

B

P3
PR24
0.02_2512_1%

1

PQ6
SI4835DY

4.7UF_1210_25V

1

ACOFF#

1
33

ADP_I

1

-INC2

+INC2

24

2

2

OUTC2 GND

23

PQ9
2N7002

3

+INE2

CS

22

2
G

4

-INE2 VCC(o)

21

5

FB2

OUT

20

6

VREF

VH

19

7

FB1

VCC

18

RT

17

VIN

2

4
PQ7
SI4835DY

100K

2

ACOFF

33

1

2

PC19
PR35
4700PF_50V 10K

PC17
0.1UF_0805_25V
PC20
0.1UF_50V
1
2

2

PC21
0.1UF_16V

1

2

1

PC22
2200PF_50V

2
PR36
10K

8

1

IREF

LXCHRG
PC23
0.1UF_0805_25V
1
2

+INE1

10

OUTC1

-INE3

16

FB3

15

11

OUTD

CTL

14

12

-INC1

+INC1

13

2
PR37
68K

1

PL3
22UH_SPC-1205P-220A
1
2
1

2
PR41
47K

1

2

PC24
1500PF_50V

BATT+

ACON

1

PR43
100K

2

2

PD7
RB051L-40

100K

1

2

2

PR39
0.02_2512_1%

PQ37
DTC115EK

2

PR151
47K

9

1

2

CS

1

PC25
0.1UF_16V

-INE1

2

CC=0.5~2.52A
CV=16.84V(12 CELLS LI-ION)

1

+3VALWP

PR40 10K
2
1

2

PR42
100K_1%

1

PR38
162K_1%
1
2

PQ8
DTC115EK

PC27
4.7UF_1210_25V
2
1

2

100K

PC26
4.7UF_1210_25V
2
1

1

1
33

1

N18

3

PR34
15.4K_1%

2

PC18
0.1UF_16V

2

ACON

IREF=1.31*Icharge
IREF=0.73~3.3V

2

2

5
6
7
8

PR33
21K_1%

1
ACON

1

1

S

2

39

PC16
0.022UF_25V
CS

2
PR28 47K

1

2

D

1
PR31
10K

1

PACIN

3

33,39,41

PACIN1

1

PR32
10K

1

1

PR30
150K_1%

2

2

PR27 10K

2

PU3
MB3878

2

ACOFF#

ACOFF#1

1

PR29
0

3
2
1

1
PD6
1SS355
42

8
7
6
5
4

4.7UF_1210_25V

PC15

2

PR26
200K_1%

2

PR25
10K

PC14

1
2
3

4

4

2

1

1

2

2

8
7
6
5

PL2
FBM-L11-453215-900LMAT_1812
1
2

1

1
2
3
1

1

1
2
3

B++

B+

PQ5
SI4835DY

8
7
6
5

D

Iadp=0~4.4A

P2
PQ4
SI4835DY
VIN

C

3

100K

1
PR46
47.5K_1%

2

1
PR47
143K_1%

4.2V

3

VMB

1

VS

PR48
340K_1%

OVP voltage : LI-MH

2

8 CELL : 18V--> BATT_OVP= 2.0V

1

PC29
0.1UF_50V

+2.5V

SDREF

1

100K
PQ38
DTC115EK

2

PR49
499K_1%

PR50
100K_0.5%

+

3

-

2

PU4B
LM358A

PR51
0

7

+

5

-

6

PR52
100K_0.5%

1

2.2K

2

PC33
0.01UF_50V

PR54
105K_0.5%

4

2

2

PC32
@0.1UF_16V

2

4

PC31
10UF_1206_10V

1

PR53

PC30
0.1UF_16V

2

1

4

1

1

33 BATT_OVP

8

PU4A
LM358A

2

(BAT_OVP=0.1111 *VMB)

2

2

1

3

FSTCHG

3

33

100K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
A

B

C

Compal Electronics, Inc.
Title

CHARGER
Size
B

Document Number

Date:

星期五, 六月 07, 2002

Rev

LA1432

1.A
Sheet

D

40

of

45

A

B

C

D

PC34
2.2UF_1206_25V
1
2

PD9

5
6
7
8

PC41
4.7UF_1210_25V

3
2
1

1
2
1

1
2

2

PR66
47K

1

1

2

2

680PF

+
PC54
100PF_50V

PR67

2

2

PR69

1

VL

1

POK

1

PD12
EP10QY03
3

PR68

44

0

10K_1%

1

2

2

+

2

1

PR64
10.5K_1%

1

+5VALWP

8

PC51

2

2

PON

1

3

PR65
10K_1%

PD11
EP10QY03

1

PC50
4.7UF_1206_16V
PC53
150UF_D_6.3V_KO

RUN/ON3

2

TIME/ON5

28

PR61
0.012_2512_1%

2.5VREF

1

7

PR60
2M

2

VL

V+
MAX1632

CSH5

3
2
1

CSH3
CSL3
FB3
SKIP#
SHDN#

PC46
47PF

4

1

PC49
100PF_50V

1
2
3
10
23

2

1

PR62
10K

LX3
DL3

PQ14
SI4810DY

PLX5

2

2

PU5

4

PDH51

PDL5

1

1

2

3.57K_1%

1

DH3

26
24

4
5
18
16
17
19
20
14
13
12
15
9
6
11

GND

PR63

PACIN

27

2
PR57
0

12OUT
VDD
BST5
DH5
LX5
DL5
PGND
CSH5
CSL5
FB5
SEQ
REF
SYNC
RST#

PT1
SDT-1205P-100

PQ12
SI4800DY

5
6
7
8

1

21

22
1

2

33,39,40

BST3

2

1
2
PDH5

2
2
1

2
1

CSH3

25

PC40
4.7UF_1210_25V

PC44

4.7UF_1206_16V
2
1

2

1

1

1

PDL3

1
2
3

4

2

8
7
6
5
1
1
2

47PF
PC45

+12VALWP
PC42
4.7UF_1206_16V

1
2
3

PD10
1SS355
PLX3

1
PR58
1M_1%

+

2

B+++

1

VL

PC52
150UF_D_6.3V_KO

2

PQ13
SI4810DY

2

PC48

150UF_D_6.3V_KO
2
1

PC47
150UF_D_6.3V_KO
2
1

+

2

3

2
PDH31 1

PDH3

PL5
SPC-1205P-100

+3VALWP

FLYBACK

PC39
0.1UF_0805_25V
1
2

DAP202U

VS
PR56
0

2

4

2

PR59
0.012_2512_1%

1

8
7
6
5
PQ11
SI4800DY

PC43
0.1UF_0805_25V

1
2

2

1

FBM-L11-322513-151LMAT

PC38
4.7UF_1210_25V

1
PC37
4.7UF_1210_25V

2

PD8
EC11FS2

3

PL4
B+

PR55
22_1206
SNB 2

2

BST51

4

BST31

2

1

1

B+++

1

PC35
470PF_0805_100V

PC36
0.1UF_0805_25V

1

1

N4

1

0.047UF_16V

+5V Ipeak = 6.66A ~ 10A

MAINPWON 4,39,43

2

1

2

+3.3V Ipeak = 6.66A ~ 10A

47K_1%

PC55

PC56
0.047UF_16V

4

4

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
Size
Document Number
B
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
Date: 星期五, 六月 07, 2002

5V/3.3V/12V

A

B

C

Rev

LA1432

1.A
Sheet

D

41

of

45

A

B

C

D

+2.5VP
D

4
1

PQ15
@SI3445DV

2

3

G

1
PC57
0.1UF_0805_25V

1
VCC1

2

PVDD1

VCC2

16

PVDD2

15

1

3

PL7
5UH_SPC_06704

PC62
4.7UF_1206_16V

3

2

PC63
0.1UF_50V

PU6

VL1

VL2

14

LX1.25

8
2

1
1

2.5VREF

PQ19
DTC115EK

2

VCCQ

10

SUSP#

SYSON

1

SYSON

2

100K

8

AGSEN

AGND

2

2

9

1
2

PC68
0.1UF_0805_25V

PR80
1K

PC67
1000PF_50V

100K

33,37

3

1
PC72

VIN/2

11

PQ20
DTC115EK

Layout : "Compensation network close to FB pin"

3

PR86
PR87
@100K_1% 160K_1%

7

VFB

1

3

PR84
100K

SD

+2.5VP

PQ21
DTC115EK

2

6

100K

100K

1

2.5VREF

2

PC71
1000PF_50V

1

2

1

PC70
1UF_1206_25V

1

2

6

PR77
100K

1UF_0805_25V

1

-

12

VL

2

100K

2

5

1

2

PR85
100K

1

PR79
100K

1

1

2
PR83
309K

+

2

2

3

1

1

1M_0.5%

PU7B
LM393M
7

1
2
G

S

2

100K

2

2
1

PQ22
2N7002
D

AGND2

2

PR82

36K

AGND1

+

1

VMB

2

PR81

5

PC64
4.7UF_1206_16V

PR78

1

VIN

13

2

PC66
1000PF_50V

+2.5VP
40

PGND2

2

4

1

2
PR76
200K_1%

100K
ACOFF#

PGND1

1

2
-

4

2

+1.25VSP

2

3

1

2

+

PC691000PF_50V
2
1

3
PQ18
2SA1036K

1

CM8500
PU7A
LM393M
1

2

PC58
0.1UF_0805_25V

1.25VIN

VS

2

1

1

PD14
RB051L-40

2

2

+

PC65
220UF_D_4V_FP

2

1

PR73
100

2

PQ16
SI3445DV

2

2
PR75
1K

1
1

SPC-1205P-4R7A

PR74
10K

1
1

3

1
1

PQ17
HMBT2222A

1

2

1

PD13
RB751V

PR72
10

1

G

PC60
10UF_1210_16V
2
1

2

4

2

1

2

D

S

2.5VIN

PC61
2200PF_50V

+2.5VP

PL6
LX2.5

6
5
2
1

PC59
220UF_D_4V_FP

PR71
0_1206

1

PR70
0_1206

+2.5V +-5%

2

+5VALWP

1

S

6
5
2
1

D

PQ23
SI3442DV
S

1

2
PR90
0

2
PR89
5.1K

5.1K

1

2

2

PR100
511K_1%

PC83
1000PF_50V

2
PR98

200K_1%

2.5VREF

7

+

5

-

6

PU9B
LM393M

+

5

-

6

1
PR148
1
PR149

PR150
100K_1%

A

PC124

2
150K_1%
2
56K_1%

100K

2

2

1

PR99

SUSP#

28,33,36,37

0

100K

2
7

1

12 CK408_PWRGD#

2
1

4

1

1

PQ27
DTC115EK

100K

4

3

2

PU8B
LM358A

2.5VREF

3

-

1

3

2
100K

2

1
PR147

1

+3VS

2

4

PQ26
DTC115EK

2

8
+

1

2

2.5VREF

PR96
100K

PR97

2

3
PQ28
2SA1036K

PR91
200K_1%
1

1

PC81
68PF

100K
PU9A
LM393M
1

3

+5VALWP

1

2

2
PR95
300K_0.5%

-

PC73
150UF_D_6.3V_KO

1
PC76
220PF_50V

1

1
2

+

8
3

2

PC82
0.1UF_50V

1

+

4

PR94
100

PU8A
LM358A

PC79
0.01UF_50V
1
2

1

2
VS

3

PR93
1K

2

3

1

2
2

2

+

PD16
RB051L-40

2

1

1

PC80
2200PF_50V

PR92
10K

1

PQ25
HMBT2222A

1

2
1
2

PD15
RB751V

G

PC78
4.7UF_1206_16V

PC77
150UF_D_6.3V_KO

S

6
5
2
1

4

1

D

1.8VIN

+1.8VALWP

PL8
5UH-SPC-06704
LX1.8 1
2

1

2

PQ24
SI3445DV

+1.5VSP
VS

PC75
0.1UF_16V

+1.8V+-5%

PR88
0_1206

3

+1.5V+-5%

4

3

1

PC74
4.7UF_1206_16V

+1.8VALWP

6
5
2
1
G

+3VALWP

+3VS
+CPU_VCC

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
Title
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
Size
Document Number
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
B
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
Date: 星期五, 六月 07, 2002
INC.

t = 0.51RC

DDR /2.5V / 1.8V/1.25V

0.33UF_0805

B

C

Rev

LA1432

1.A
Sheet

D

42

of

45

A

B

C

D

PH1 under CPU botten side :
CPU thermal protection at 87 degree C
Recovery at 48 degree C
1

1

VL

VS

VL

VMB

1

PR107
16.9K_1%

PD17
@BAS40-04

1

TM_REF1

2

+

2

-

33

+3VALWP

3K_1%

1

PQ39
DTC115EK

PD30

1

2

1

2

100K

1SS355
100K

PU10A
LM393M

PC87
1000PF_50V

ALI/MH#

PR110
25.5K_1%
2

PC88
0.22UF_0805_16V

PR102

1

VL
PR109
100K_1%
2

1

2

3

4

2

MAINPWON 4,39,41

3

PC86
0.01UF_50V

3
PR108
1K

47K_1%
PR103
47K_1%

2

PC85
1000PF_50V

PR153

PC84
0.1UF_50V

8

1

2

PR106
100

2

PR105
100

PJP9

2
2

1

BATT+

+3VALWP
PH1
10K_1%

PR104
47K

1

2

PL9
HCB4532K-800T90_9A
1
2

2

PR101
1K
1

1

BLI/NIMH#
BB/I
TS
EC_SMDA
EC_SMCA

1

1
2
3
4
5
6
7

1

PF2
12A 65V UL/CSA fast

BP0207

PR112
1K

PR111
100K_1%

2

3
PD18
@BAS40-04

1
2

BATT_TEMPA 33
EC_SMD1 33,34

1

1

EC_SMC1 33,34

PH2 near main Battery CONN :
BAT. thermal protection at 73 degree C
Recovery at 50(51) degree C

PD19
@BAS40-04

PD20
@BAS40-04
VL

PH2
10K_1%

3

2

2

3

VL

3

+5VALWP

PR154

3

47K_1%
PR114
47K_1%
PR115
10K_1%

PD31

5
TM_REF2

6

+

7

2

-

1
1SS355

PR113
3.24K_1%

PC89 1000PF_50V

PC90
0.22UF_0805_16V

PU10B
LM393M

VL
PR116

100K_1%

PR117
100K_1%

4

4

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
Size
Document Number
B
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
Date: 星期五, 六月 07, 2002

BATTERY CONN / OTP

A

B

C

Rev

LA1432

1.A
Sheet

D

43

of

45

F

5

2

1
2

1
2
3
4

N9
2

N10

PC93

8
7
6
5
S
S
S
G

D
D
D
D

8
7
6
5
D
D
D
D
S
S
S
G
1

100UF_EC_25V

PL11
0.6UH_HK_AE26A 0R6
1

2

DRVL

N8

+

ADP3414
PU13

PD22

PR122
2K_1%

S
S
S
G

PU15

S
S
S
G

PU14
SI4362

3

1
2
3
4

SI4362

1

7

B+

PC94

8
7
6
5

SW

D
D
D
D

DLY

@220PF

PC97

2
0.22UF_0805_16V

100K
PQ30
DTC115EK

1
8

PC98

2

POK

PR121
1

1
41

100K

BST
DRVH

IN

CPU-CORE

PL10
HCB4532K-800T90_9A
CPU_B+1
2

1

1
2
3
4

3

+5VALW
1K_1%

1

PR119
1K

PC96

4
2

PR120
2.4_1%

D
D
D
D

10K

VCC

2

PGND

2
2

1

N19

1
EP10QY03

6

PR118

1

2
PC95

+5VDRIVE

8
7
6
5

4.7UF_0805_10V

3

1
2
3
4

PD21

SI2301
1

+5VALW

0.1UF_0805_25V

+5VDRIVE
PQ29

H

CPU_B+

PU12
IRF7811A
PC92
4.7UF_1210_25V

PU11
IRF7811A

G

PC91

E

4.7UF_1210_25V

D

4.7UF_1210_25V

C

1

B

2
RB081L-20

A

CPU_B+

2

VID3

ISEN3

12

5

VID4

2 0 PR1301

1

VID4

VSEN

10

+3VS

1

PR131
10K 2

19

PGOOD

COMP

PC106
6 33PF_50V_NPO

1

2
8

FS/DIS

PC116
4.7UF_1206_16V

1
2

PC101

PC100
4.7UF_1210_25V

4.7UF_1210_25V

PC99

8
7
6
5
D
D
D
D

8
7
6
5
D
D
D
D

PC104

0.1UF_0805_25V

S
S
S
G

S
S
S
G
SI4362

S
S
S
G

PC112

PC111

4.7UF_1210_25V

PC110
4.7UF_1210_25V

4.7UF_1210_25V

S
S
S
G

PC109

4.7UF_1210_25V

8
7
6
5
D
D
D
D

8
7
6
5

N16

3

1
2
3
4

5

S
S
S
G

7

CPU_B+

2

1
2
3
4

SW
DRVL

PR133
2.4_1%
N14 1

D
D
D
D

PC108

4
VCC
DLY

PGND

IN

3

1
8

0.1UF_0805_25V

PC107
2

BST
DRVH

PU23
IRF7811A

N15

ADP3414
PU24

PL13
1

0.6UH_HK_AE26A 0R6
PD27

PR136
2K_1%
1

SI4362

1
2
3
4

SI4362

2
RB081L-20

S
S
S
G

PU26

S
S
S
G

PU25

1

D
D
D
D

2

8
7
6
5

8
7
6
5

2

1
2
3
4

3K_1% PR137
1
2
PR138
0

PU27
N17

4

VIN

2

DELAY

VOUT

5

SENSE

6

CNOISE

1

GND

3

+1.2VPP

1

+3VALWP

PR129
2K_1%

CPU_B+
PU22
IRF7811A

D
D
D
D

PQ40
DTC115EK
1

3

100K

N21

1
EP10QY03

6

100K

2

2

PR135
1

CPU_ON

1K_1%

1500PF_50V PC113
2

3

PQ31
DTC115EK

10K PR134

1
100K

2

@220PF

PR156
@0
PR132
137K_1%

100K

4

PD26
2

1

2

PC103

+5VDRIVE

2

1

1

10K

0.6UH_HK_AE26A 0R6

PU21

SI4362

PU16

2

2
10K
1

33

VR_ON

VR_ON

7
8

ERROR
ON/OFF#

1

4

PR139
0

PC117
4.7UF_1206_16V

2

1000PF_50V PC115
CPU_ON

2

4

1

3

ADP3414
PU19

1

7

1
PR152

PL12
2

PD25

PC114

+3VALWP

FB

+CPU_VCC

N12
N13

PU20

4.7UF_0805_10V

PC125 PR155
0
2200PF

9

V_GATE

5

PD24

VID3

7

EC10QS04
2
1

5

SW
DRVL

2

2

11

DLY

100UF_EC_25V

1

PWM3

IN

3

1

VID2

PR127
1

3

2 0 PR1281

GND

2 0 PR1261

21

PR157

N7

VID2

2

2
RB081L-20

13

PC102

+

1
2
3
4

ISEN2

8
7
6
5

VID1

2

D
D
D
D

4

1

S
S
S
G

2 0 PR1251

N11

CPU_B+

1
2
3
4

VID1

BST
DRVH

1
2
3
4

5

N6

8
7
6
5

14

PR124
2.4_1%

D
D
D
D

PWM2

PU18
IRF7811A

1
2
3
4

VID0

VCC

5

PGND

2 0 PR1231

1
8

6

VID0

N20

1
EP10QY03

@220PF

16

2

PC105

ISEN1

4.7UF_0805_10V

ISEN4

15

2

17

PWM1

5

5

+3VALWP

PWM4

1K_1%

2

18

VCC

20

PD23

N5

PU17
IRF7811A

4.7UF_1210_25V

+5VDRIVE

PC118

SI91822AD
2

PR140
0

0.1UF_50V

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
Size
Document Number
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
Date: 星期五, 六月 07, 2002

PR141
@10K_1%

+VCC_H_CORE

A

B

C

D

E

F

G

Rev

LA1432

1.A
Sheet

44
H

of

45

ATR60 PIR LIST
************* Rev0.2 PIR List **************
04/15/02 Written by Jerry
P26:Delete C372 and Remove +3V at pin6 of U18
P33: Remove @ at R492 and add @ at R488
Change value of R397 to 47K

04/26/02 Written by Sam
P14: Remove @ at C134
P17: Delete RP70, RP77, RP88, RP83, RP81, RP86, RP79, RP69, RP90, RP92
RP67, RP76, RP87, RP82, RP80, RP85, RP78, RP68, RP89, RP91
R386, R383
Remove @ at R413, R414
P18: Delete RP65, RP64, RP71, RP72, RP62, RP63, RP73, RP66, RP61, RP74
RP52, RP49, RP57, RP58, RP48, RP47, RP59, RP56, RP50, RP60
R325, R369
Remove @ at R345, R382
P33: Delete R425, R426, R427, R430, R488, R492
Add U40 Signal Pins for Keyboard Led NUM_LED# , CAPS_LED#, ARROW_LED#
P35: Add R535, R536 ,R537 ,Q54, Q55, Q56
P36: Add Q57
Change D25 to Be PSOT24C, Pin 1 : Floating,Pin 2 : Connect to JP2 Pin 8,
Pin 3 : Ground
Change R376 Pin 2 Connect with RTCVREF,Change R390 Pin 2 Connect with RTCVREF,
04/26/02 Written by Jerry
P17,P18: Modify net name R_NDQM* TO NDQM*
05/01/02 Written by Sam
P29: Add @ at R538
P34: Add U35 Pin 6 Signl for WLKB
P36: Add R539,R540,D35,Q58
Del D10
Change R250 Pin 1 from +12VALW to +5VALW_RX
05/06/02 Written by Sam
P35: Q12, Q14 Change Material to 2N7002
05/07/02 Written by Sam
P15: L37 Change Material to 0_0603
05/17/02 Written by Sam
P36: Change J3 footprinter to JUMP_2MM
P36: Add JP24 and Change J1,J4 footprinter to JUMP_2MM

Compal Electronics, Inc.
Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:

ATR60 PIR LIST
Document Number

Rev
1.A

LA1432
星期五, 六月 07, 2002

Sheet

45

of

45



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
Create Date                     : 2002:06:07 14:42:43+08:00
Modify Date                     : 2002:06:07 14:42:43+08:00
Page Count                      : 45
Creation Date                   : 2002:06:07 06:42:43Z
Mod Date                        : 2002:06:07 06:42:43Z
Producer                        : Acrobat Distiller 5.0 (Windows)
Metadata Date                   : 2002:06:07 06:42:43Z

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