Compal LA 2492
User Manual:
Open the PDF directly: View PDF .
Page Count: 51
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Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
151¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
LA-2492 Schematics Document
Intel Dothan / AlvisoPM / DDR-1 / ICH6-M / Select Bay
2004 / 12 / 22
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev:1.0
(nVIDIA NV43M & NV44M/ ATi M22 & M24)
EAT20 (Sakhir 10GC)
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Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
251¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
Power On/Off CKT.
File Name : LA-2492
LPC BUS
page 30
Compal confidential
PCBGA 1257
page 21
H_A#(3..31)
TI Controller
H_D#(0..63)
PCI7421
page 32
page 31
BANK 0, 1, 2, 3
USB conn x 3
400 / 533 Mhz
DMI
page 23,24
DC/DC Interface CKT.
page 40
FSB
Clock Generator
ICS954226
Power Circuit DC/DC
PATA HDD
PCI BUS
Intel Dothan CPU
page 34
DDR-SO-DIMM X2
page 40
Intel Alviso GM(PM)
page 4
page 4,5
RTC CKT.
page 14
DDR-1(DDR-2)
mBGA-609
page 39
AC-LINK
page 4
page 6,7,8,9,10
Intel ICH6-M
Thermal Sensor
ADM1032ARM
page 11,12,13
page 17,18,19,20
Docking CONN.
*RJ-11 / 45(LED*2)
*COMPOSITE Video Out
*TVOUT
*LINE IN / OUT
*PS/2
*Print port
*1394
*USB
*DC JACK
AMP & Audio Jack
Power OK CKT.
page 19
page 31
Slot 0
page 26
BT Conn
PATA
Fan Control
page 15
CRT/TV-OUT
5in1 CardReader
Slot
LCD CONN
page 16
page 25
page 44~51
page 29
Mini PCI
socket
page 27
page 28
MARVELL LAN
88E8036RJ45 CONN
page 32
MODULE
Connector
Touch Pad
CONN.
ENE KB910/910L
page 35
page 34
Int. KBD
page 36
BIOS
page 37
page 29
RJ11 CONN
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
USB 2.0
USB 2.0
SATA
88SA8040
NV44 / M24
VGA Board
SATA to PATA
Docking
Audio
page 31
conn
Slot 1
page 16
Two Channel DDR-2
Signal Channel DDR-1
page 21
page 22
SATA HDD
page 24
Conn.
1394
88E8053
ALC250-D
Audio CKT
PCI-E BUS
page 34
SMsC LPC47N217
Parellel
Port
page 34
Serial
Port
page 38
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Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
351¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
Voltage Rails
VIN
B+
+CPU_CORE
+1.05VS
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.05V switched power rail
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
CardBus
Mini-PCI
AD20
AD18
EC SM Bus1 address
Device
ADM1032
2'nd Battery
S1 S3 S5
ON OFF
ON OFF
N/A N/A N/A
N/AN/AN/A
Power Plane Description
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
ON
OFFON
ON
ON
ON
ON
OFF
ON*
OFF
OFF
ON
EC SM Bus2 address
Device
Smart Battery
2
1
PIRQA/PIRQB
PIRQG/PIRQH
ON
EEPROM(24C16/02)
1001 011X b
1001 110X b0001 011X b
1010 000X b
ON OFF OFF
(24C04)
1011 000Xb
ICH6M SM Bus address
Device
Clock Generator
( ICS 952623)
Address
Address Address
1101 001Xb
ON ON*
ON OFF OFF
1394
AD20 2
PIRQA/PIRQB
STATE SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOWLOWLOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGHHIGHHIGH
HIGH
HIGH
HIGH
Board ID / SKU ID Table for AD channel
ON OFF OFF
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 001Xb
Vcc 3.3V +/- 5%
100K +/- 5%Ra/Rc/Re
Board ID
Rb / Rd / Rf V min
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
AD_BID
Vtyp
AD_BID
V
AD_BID
max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V 0 V
4
5
6
7NC
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
1.185 V 1.264 V
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
ON
SD
AD20
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PIRQA/PIRQB
2
Docking
1010 000X b
+DDRVTT 1.25V switched power rail for DDR terminator
+RTCVCC RTC power
+1.5VS
+1.8VS 1.8V switched power rail
+2.5VS
+5VS
+3V
+3VS
+5VALW
+DDRVCC
2.5V switched power rail
+3VALW
2.5V power rail for DDR
3.3V always on power rail
3.3V power rail
5V always on power rail
3.3V switched power rail
5V switched power rail
+1.5VALW 1.5V always on power rail
+12VALW 12V always on power rail
+5VCD
+5VMOD
5V switched power rail for Direct CD
5V switched power rail for Module Bay
ONON ON*
ON ONON
OFF OFFON
OFF OFFON
ON*ON
1.5V switched power rail
BOARD ID Table
SKU ID Table
0.2
NC
0.2
1.0
SKU_ID_CHECK_1
SKU_ID_CHECK_0
11
0
12
13
7-Buttons
10
1
4
32
5
67
10GC
10G
10 3-Buttons1-Button
10C
10J
SKU_ID_CHECK_0
0
1
2
3
4
5
6
567
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_A#15
H_D#19
H_D#43
H_A#4
H_A#23
H_A#28
H_D#15
H_D#16
H_D#63
H_REQ#1
H_A#8
H_A#17
H_A#27
H_D#41
H_D#56
H_D#59
H_D#62
H_A#3
H_A#7
H_A#10
H_D#29
H_D#37
H_A#14
H_A#20
H_D#23
H_D#26
H_D#32
H_D#39
H_D#49
H_RS#0
H_D#2
H_D#4
H_D#8
H_D#28
H_D#45
H_D#51
H_A#18
H_A#19
H_D#30
H_D#60
H_REQ#2
H_CPURST#
H_D#27
H_D#55
H_A#6
H_D#1
H_D#7
H_D#10
H_D#17
H_D#18
H_REQ#0
H_A#24
H_D#3
H_D#44
H_D#52
H_A#12
H_D#0
H_D#12
H_D#14
H_D#38
H_D#40
H_D#46
H_D#50
H_D#61
H_REQ#4
H_A#29
H_A#30
H_D#21
H_D#48
H_D#58
H_IERR#
H_A#26
H_A#31
H_D#11
H_D#24
H_D#36
H_D#53
H_D#54
H_A#5
H_D#9
H_D#20
H_D#22
H_A#9
H_A#25
H_D#5
H_D#13
H_D#33
H_D#57
H_RS#2
H_A#11
H_A#16
H_A#22
H_D#31
H_D#34
H_D#35
H_RS#1
H_A#13
H_A#21
H_D#6
H_D#25
H_D#42
H_D#47
H_REQ#3
THERMDA
THERMDC
H_A#[3..31]
H_REQ#[0..4]
H_D#[0..63]
PRO_CHOT#
H_PWRGOOD
ITP_DBRRESET#
ITP_TMS
ITP_TDO
ITP_TCK
THERMDA
THERMDC
PRO_CHOT#
ITP_TCK
ITP_TRST#
TEST1
ITP_TDO
ITP_TDI
ITP_TMS
TEST2
H_CPUSLP#
H_PWRGOOD
H_IERR#
ITP_DBRRESET#
TEST1
TEST2
H_CPURST#
H_RS#[0..2]
ITP_TDI
ITP_TRST#
H_DINV#1 6
H_DINV#3 6
H_DSTBN#1 6
H_DSTBN#3 6
H_D#[0..63] 6
H_A#[3..31]6
H_REQ#[0..4]6
H_DSTBP#1 6
H_DSTBP#3 6
H_DINV#2 6
H_DINV#0 6
H_DSTBP#0 6
H_DSTBP#2 6
H_DSTBN#0 6
H_DSTBN#2 6
H_A20M# 18
H_INIT# 18
H_STPCLK# 18
H_SMI# 18
H_IGNNE# 18
H_THERMTRIP#6,18
H_CPURST#6
H_NMI 18
H_INTR 18
H_DPSLP#18
H_CPUSLP#6,18
H_PWRGOOD18
CLK_CPU_BCLK14CLK_CPU_BCLK#14
H_ADS#6
H_ADSTB#06 H_ADSTB#16
H_BNR#6
H_BPRI#6H_BR0#6
H_DBSY#6
H_DEFER#6
H_DPWR#6
H_DRDY#6
H_FERR# 18
H_HIT#6H_HITM#6
H_LOCK#6
H_TRDY#6
H_DPRSTP#18
EC_SMB_CK230,34,39
EC_SMB_DA230,34,39
H_RS#[0..2]6
+3VS
+1.05VS
+3VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
451¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THERMDA & THERMDC Trace / Space = 10 / 10 mil
U3
ADM1032ARM_RM8
VDD1 1
ALERT# 6
THERM# 4
GND 5
D+
2
D-
3
SCLK
8
SDATA
7
R508 150_0402_5%
12
R28 54.9_0402_1%@
12
C12
0.1U_0402_16V4Z
1
2
C17
2200P_0402_50V7K
1
2
R25 1K_0402_5%@
12
R26 150_0402_5%
12
R27 40.2_0402_1%
12
R46 1K_0402_5%@
12
R24 200_0402_5%
12
R29 54.9_0402_1%@
12
R30 27.4_0402_1%
12
R31 56_0402_5%
12
R23 56_0402_5%
12
R20
10K_0402_5%@
12
ADDR GROUP
CONTROL GROUP
HOST CLK
MISC
DATA GROUP
THERMAL
DIODE
LEGACY CPU
Dothan
JP7A
TYCO_1612365-1_Dothan
A3#
P4
A4#
U4
A5#
V3
A6#
R3
A7#
V2
A8#
W1
A9#
T4
A10#
W2
A11#
Y4
A12#
Y1
A13#
U1
A14#
AA3
A15#
Y3
A16#
AA2
A17#
AF4
A18#
AC4
A19#
AC7
A20#
AC3
A21#
AD3
A22#
AE4
A23#
AD2
A24#
AB4
A25#
AC6
A26#
AD5
A27#
AE2
A28#
AD6
A29#
AF3
A30#
AE1
A31#
AF1
REQ0#
R2
REQ1#
P3
REQ2#
T2
REQ3#
P1
REQ4#
T1
ADSTB0#
U3
ADSTB1#
AE5
BCLK0
B15
BCLK1
B14
ITP_CLK0
A16
ITP_CLK1
A15
ADS#
N2
BNR#
L1
BPRI#
J3
BR0#
N4
DEFER#
L4
DRDY#
H2
HIT#
K3
HITM#
K4
IERR#
A4
LOCK#
J2
RESET#
B11
RS0#
H1
RS1#
K1
RS2#
L2
TRDY#
M3
BPM0#
C8
BPM1#
B8
BPM2#
A9
BPM3#
C9
DBR#
A7
DBSY#
M2
DPSLP#
B7
DPWR#
C19
PRDY#
A10
PREQ#
B10
PROCHOT#
B17
PWRGOOD
E4
SLP#
A6
TCK
A13
TDI
C12
TDO
A12
TEST1
C5
TEST2
F23
TMS
C11
TRST#
B13
THERMDA
B18
THERMDC
A18
THERMTRIP#
C17
D0# A19
D1# A25
D2# A22
D3# B21
D4# A24
D5# B26
D6# A21
D7# B20
D8# C20
D9# B24
D10# D24
D11# E24
D12# C26
D13# B23
D14# E23
D15# C25
D16# H23
D17# G25
D18# L23
D19# M26
D20# H24
D21# F25
D22# G24
D23# J23
D24# M23
D25# J25
D26# L26
D27# N24
D28# M25
D29# H26
D30# N25
D31# K25
D32# Y26
D33# AA24
D34# T25
D35# U23
D36# V23
D37# R24
D38# R26
D39# R23
D40# AA23
D41# U26
D42# V24
D43# U25
D44# V26
D45# Y23
D46# AA26
D47# Y25
D48# AB25
D49# AC23
D50# AB24
D51# AC20
D52# AC22
D53# AC25
D54# AD23
D55# AE22
D56# AF23
D57# AD24
D58# AF20
D59# AE21
D60# AD21
D61# AF25
D62# AF22
D63# AF26
DINV0# D25
DINV1# J26
DINV2# T24
DINV3# AD20
DSTBN0# C23
DSTBN1# K24
DSTBN2# W25
DSTBN3# AE24
DSTBP0# C22
DSTBP1# L24
DSTBP2# W24
DSTBP3# AE25
A20M# C2
FERR# D3
IGNNE# A3
INIT# B5
LINT0 D1
LINT1 D4
STPCLK# C6
SMI# B4
DPRSTP#
G1
R509 680_0402_5%
12
![](asset-5.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
COMP3
GTL_REF0
COMP2
COMP1
VCCSENSE
VSSSENSE
COMP0
COMP3
COMP2
COMP1
COMP0
CPU_VID049 CPU_VID149 CPU_VID249 CPU_VID349 CPU_VID449 CPU_VID549
PSI#49
CPU_BSEL014 CPU_BSEL114
+CPU_CORE
+1.05VS
+1.05VS
+1.05VS
+CPU_CORE
+1.8VS
+VCCA
+1.5VS
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
551¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2X330uF 7m ohm/2 3.5nH/2
Vcc-core
Decoupling
35X10uF 5m ohm/35 0.6nH/35
C,uF ESR, mohm ESL,nH
SPCAP,Polymer
MLCC 0805 X5R
1.8V FOR DOTHAN-A
1.5V FOR DOTHAN-B
TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils
C42
10U_0805_6.3V6M
1
2
C64
10U_0805_6.3V6M
1
2
R84 54.9_0402_1%@
1 2
C430
10U_0805_6.3V6M
1
2
+
C460
330U_D_2VM
1
2
C30
10U_0805_6.3V6M
1
2
C453
0.1U_0402_16V4Z
1
2
C68
10U_0805_6.3V6M
1
2
C510
10U_0805_6.3V6M
1
2
C66
10U_0805_6.3V6M
1
2
R85 54.9_0402_1%@
1 2
C47
10U_0805_6.3V6M
1
2
C31
10U_0805_6.3V6M
1
2
R75
1K_0402_1%
12
Dothan
POWER, GROUND
JP7C
TYCO_1612365-1_Dothan
VCC
F20
VCC
F22
VCC
G5
VCC
G21
VCC
H6
VCC
H22
VCC
J5
VCC
J21
VCC
K22
VCC
U5
VCC
V6
VCC
V22
VCC
W5
VCC
W21
VCC
Y6
VCC
Y22
VCC
AA5
VCC
AA7
VCC
AA9
VCC
AA11
VCC
AA13
VCC
AA15
VCC
AA17
VCC
AA19
VCC
AA21
VCC
AB6
VCC
AB8
VCC
AB10
VCC
AB12
VCC
AB14
VCC
AB16
VCC
AB18
VCC
AB20
VCC
AB22
VCC
AC9
VCC
AC11
VCC
AC13
VCC
AC15
VCC
AC17
VCC
AC19
VCC
AD8
VCC
AD10
VCC
AD12
VCC
AD14
VCC
AD16
VCC
AD18
VCC
AE9
VCC
AE11
VCC
AE13
VCC
AE15
VCC
AE17
VCC
AE19
VCC
AF8
VCC
AF10
VCC
AF12
VCC
AF14
VCC
AF16
VCC
AF18
VSS
M4
VSS
M5
VSS
M21
VSS
M24
VSS
N3
VSS
N6
VSS
N22
VSS
N23
VSS
N26
VSS
P2
VSS
P5
VSS
P21
VSS
P24
VSS
R1
VSS
R4
VSS
R6
VSS
R22
VSS
R25
VSS
T3
VSS
T5
VSS
T21
VSS
T23
VSS T26
VSS U2
VSS U6
VSS U22
VSS U24
VSS V1
VSS V4
VSS V5
VSS V21
VSS V25
VSS W3
VSS W6
VSS W22
VSS W23
VSS W26
VSS Y2
VSS Y5
VSS Y21
VSS Y24
VSS AA1
VSS AA4
VSS AA6
VSS AA8
VSS AA10
VSS AA12
VSS AA14
VSS AA16
VSS AA18
VSS AA20
VSS AA22
VSS AA25
VSS AB3
VSS AB5
VSS AB7
VSS AB9
VSS AB11
VSS AB13
VSS AB15
VSS AB17
VSS AB19
VSS AB21
VSS AB23
VSS AB26
VSS AC2
VSS AC5
VSS AC8
VSS AC10
VSS AC12
VSS AC14
VSS AC16
VSS AC18
VSS AC21
VSS AC24
VSS AD1
VSS AD4
VSS AD7
VSS AD9
VSS AD11
VSS AD13
VSS AD15
VSS AD17
VSS AD19
VSS AD22
VSS AD25
VSS AE3
VSS AE6
VSS AE8
VSS AE10
VSS AE12
VSS AE14
VSS AE16
VSS AE18
VSS AE20
VSS AE23
VSS AE26
VSS AF2
VSS AF5
VSS AF9
VSS AF11
VSS AF13
VSS AF15
VSS AF17
VSS AF19
VSS AF21
VSS AF24
C514
10U_0805_6.3V6M
1
2
R82 54.9_0402_1%
1 2
C443
10U_0805_6.3V6M
1
2
R83 27.4_0402_1%
1 2
C512
10U_0805_6.3V6M
1
2
R78 2K_0402_1%
1 2
C32
10U_0805_6.3V6M
1
2
Dothan
POWER, GROUNG, RESERVED SIGNALS AND NC
JP7B
TYCO_1612365-1_Dothan
PSI#
E1
GTLREF
AD26
VCCQ0
P23
VCCQ1
W4
VCCSENSE
AE7
VSSSENSE
AF6
BSEL0
C16
BSEL1
C14
VCCA0
F26
VCCA1
B1
VCCA2
N1
VCCA3
AC26
VCCP
D10
VCCP
D12
VCCP
D14
VCCP
D16
VCCP
E11
VCCP
E13
VCCP
E15
VCCP
F10
VCCP
F12
VCCP
F14
VCCP
F16
VCCP
K6
VCCP
L5
VCCP
L21
VCCP
M6
VCCP
M22
VCCP
N5
VCCP
N21
VCCP
P6
VCCP
P22
VCCP
R5
VCCP
R21
VCCP
T6
VCCP
T22
VCCP
U21
VCC
D6
VCC
D8
VCC
D18
VCC
D20
VCC
D22
VCC
E5
VCC
E7
VCC
E9
VCC
E17
VCC
E19
VCC
E21
VCC
F6
VCC
F8
VCC
F18
VID0
E2
VID1
F2
VID2
F3
VID3
G3
VID4
G4
VID5
H4
COMP0
P25
COMP1
P26
COMP2
AB2
COMP3
AB1
RSVD
AF7
RSVD
B2
RSVD
C3
RSVD
E26
VSS A2
VSS A5
VSS A8
VSS A11
VSS A14
VSS A17
VSS A20
VSS A23
VSS A26
VSS B3
VSS B6
VSS B9
VSS B12
VSS B16
VSS B19
VSS B22
VSS B25
VSS C1
VSS C4
VSS C7
VSS C10
VSS C13
VSS C15
VSS C18
VSS C21
VSS C24
VSS D2
VSS D5
VSS D7
VSS D9
VSS D11
VSS D13
VSS D15
VSS D17
VSS D19
VSS D21
VSS D23
VSS D26
VSS E3
VSS E6
VSS E8
VSS E10
VSS E12
VSS E14
VSS E16
VSS E18
VSS E20
VSS E22
VSS E25
VSS F1
VSS F4
VSS F5
VSS F7
VSS F9
VSS F11
VSS F13
VSS F15
VSS F17
VSS F19
VSS F21
VSS F24
VSS G2
VSS G6
VSS G22
VSS G23
VSS G26
VSS H3
VSS H5
VSS H21
VSS H25
VSS J1
VSS J4
VSS J6
VSS J22
VSS J24
VSS K2
VSS K5
VSS K21
VSS K23
VSS K26
VSS L3
VSS L6
VSS L22
VSS L25
VSS M1
RSVD
AC1
C461
0.1U_0402_16V4Z
1
2
C40
10U_0805_6.3V6M
1
2
+
C435
150U_D2_6.3VM
1
2
C69
10U_0805_6.3V6M
1
2
C470
10U_0805_6.3V6M
1
2
C458
0.1U_0402_16V4Z
1
2
C471
10U_0805_6.3V6M
1
2
C70
10U_0805_6.3V6M
1
2
R56 0_1206_5%
1 2
C515
10U_0805_6.3V6M
1
2
C46
10U_0805_6.3V6M
1
2
C65
10U_0805_6.3V6M
1
2
C14
0.1U_0402_16V4Z
1
2
C15
0.1U_0402_16V4Z
1
2
C67
10U_0805_6.3V6M
1
2
C26
10U_0805_6.3V6M
1
2
R63 0_1206_5%@
1 2
C455
10U_0805_6.3V6M
1
2
C16
0.1U_0402_16V4Z
1
2
C454
10U_0805_6.3V6M
1
2
R70 54.9_0402_1%
1 2
C445
0.1U_0402_16V4Z
1
2
C33
10U_0805_6.3V6M
1
2
C25
0.01U_0402_16V7K
1
2
C509
10U_0805_6.3V6M
1
2
C13
0.1U_0402_16V4Z
1
2
+
C427
330U_D_2VM
1
2
C45
10U_0805_6.3V6M
1
2
C513
10U_0805_6.3V6M
1
2
C444
10U_0805_6.3V6M
1
2
C442
0.1U_0402_16V4Z
1
2
C48
10U_0805_6.3V6M
1
2
C516
10U_0805_6.3V6M
1
2
C429
10U_0805_6.3V6M
1
2
C511
10U_0805_6.3V6M
1
2
R69 27.4_0402_1%
1 2
C41
10U_0805_6.3V6M
1
2
C448
0.1U_0402_16V4Z
1
2
C39
10U_0805_6.3V6M
1
2
![](asset-6.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_D#[0..63]H_REQ#[0..4]
H_A#[3..31]
H_RS#0
H_RS#1
H_RS#2
H_REQ#1
H_REQ#0
H_REQ#2
H_REQ#4
H_REQ#3
H_A#28
H_A#6
H_A#14
H_A#4
H_A#22
H_A#31
H_A#19
H_A#18
H_A#8
H_A#24
H_A#27
H_A#16
H_A#9
H_A#21
H_A#25
H_A#7
H_A#15
H_A#17
H_A#10
H_A#30
H_A#26
H_A#5
H_A#3
H_A#23
H_A#20
H_A#11
H_A#29
H_A#13
H_A#12
H_D#21
H_D#23
H_D#46
H_D#11
H_D#2
H_D#31
H_D#50
H_D#37
H_D#58
H_D#35
H_D#8
H_D#5
H_D#39
H_D#30
H_D#27
H_D#52
H_D#10
H_D#51
H_D#44
H_D#60
H_D#18
H_D#59
H_D#4
H_D#56
H_D#14
H_D#43
H_D#3
H_D#62
H_D#48
H_D#28
H_D#63
H_D#34
H_D#24
H_D#55
H_D#13
H_D#36
H_D#57
H_D#29
H_D#20
H_D#16
H_D#22
H_D#9
H_D#17
H_D#45
H_D#0
H_D#53
H_D#26
H_D#1
H_D#41
H_D#47
H_D#7
H_D#33
H_D#40
H_D#15
H_D#61
H_D#38
H_D#25
H_D#54
H_D#42
H_D#6
H_D#49
H_D#19
H_D#12
H_D#32
CPU_SLP#
CPU_SLP#
H_VREF H_XSWING H_YSWING
H_VREF
H_XSWING
H_YSWING
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
DMI_ITX_MRX_N2
CFG13
M_OCDCOMP1
DMI_MTX_IRX_N2
DMI_ITX_MRX_N3
DMI_ITX_MRX_P0
M_YSELW
CFG18
DMI_MTX_IRX_P2 CFG18
CFG19
DMI_ITX_MRX_P2
CFG5
CFG16 CFG6
DDRA_SCS#0
SMVREF
CFG6
M_XSLEW
CFG7
DDRB_CKE0
DMI_ITX_MRX_P3
M_RCOMPP
DMI_MTX_IRX_N0
CFG12
DMI_MTX_IRX_N1
DDRA_CKE0
CFG0
CFG13
DDRB_SCS#1
DDRB_CKE1
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
CFG9
CFG12
CFG16
M_RCOMPN
SMVREF
DMI_MTX_IRX_N3
DDRB_SCS#0
DDRA_CKE1
DMI_ITX_MRX_P1
M_OCDCOMP0
DMI_MTX_IRX_P3
CFG9
CFG5
DDRA_SCS#1
CFG19
CFG7
EXT_TS#0
EXT_TS#1
H_THERMTRIP#
CLK_DREF_96M#
CLK_DREF_96M
CLK_DREF_SSC
CLK_DREF_SSC#
MCH_CLKSEL1
MCH_CLKSEL0
CFG0
H_RS#[0..2]
DMI_MTX_IRX_P1
DMI_MTX_IRX_P0
EXT_TS#0
EXT_TS#1
CLK_DREF_SSC
CLK_DREF_SSC#
H_D#[0..63] 4
H_BPRI#4
H_HIT#4
H_DEFER#4
H_TRDY#4
H_ADSTB#04 H_ADSTB#14
H_DSTBP#04
H_DSTBN#04
H_DSTBP#14
H_DSTBN#14
H_DSTBP#24
H_DSTBN#24
H_DSTBP#34
H_DSTBN#34
H_A#[3..31]4
H_REQ#[0..4]4
H_DINV#04H_DINV#14H_DINV#24H_DINV#34
H_HITM#4
H_ADS#4
H_CPURST#4
H_BNR#4
H_LOCK#4H_BR0#4
H_DRDY#4
H_DBSY#4
H_CPUSLP#4,18
DDRB_CLK2#12
DDRB_SCS#112
DDRB_CKE112
DMI_MTX_IRX_P319
DDRB_CLK112
DDRA_SCS#111
DDRA_CLK1#11
DMI_MTX_IRX_P219
DDRB_CLK1#12
DMI_MTX_IRX_P019
DMI_MTX_IRX_N219 DMI_MTX_IRX_N319
DMI_MTX_IRX_P119
DMI_MTX_IRX_N019 DMI_MTX_IRX_N119
DMI_ITX_MRX_P119 DMI_ITX_MRX_P219
DMI_ITX_MRX_P019
DDRA_CLK2#11
DDRA_SCS#011
DDRB_SCS#012
DDRA_CKE111
DMI_ITX_MRX_P319
DDRA_CLK211
DMI_ITX_MRX_N219 DMI_ITX_MRX_N319
DMI_ITX_MRX_N019 DMI_ITX_MRX_N119
DDRB_CLK212
DDRB_CKE012
DDRA_CKE011
DDRA_CLK111
PM_BMBUSY# 19
H_THERMTRIP# 4,18
CLK_DREF_96M# 14
CLK_DREF_96M 14
CLK_DREF_SSC# 14
CLK_DREF_SSC 14
PLT_RST# 16,17,19,21,22,24,27,33,34
MCH_CLKSEL1 14
MCH_CLKSEL0 14
VGATE 14,19,49
H_RS#[0..2] 4
H_DPWR#4
CLK_MCH_BCLK14 CLK_MCH_BCLK#14
+1.05VS +1.05VS+1.05VS
+1.05VS
+DDRVCC
+DDRVCC
+2.5VS
+2.5VS
+1.5VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
651¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
CFG[19:18]: internal pull-down
CFG[17:3]: internal pull-up
CFG[2:0] Refer to sheet 6 for FSB
frequency select
CFG19
(VTT Select)
*
*
CFG18
(VCC Select)
Low = DMI x 2
CFG7
High = DMI x 4
CFG5
Low = DT/Transportable CPU
High = Mobile CPU
CFG6 High = DDR-I
Low = DDR-II
CFG[13:12]
CFG16
(FSB Dynamic
ODT)
Low = 1.05V (Default)
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)
High = 1.2V
Low = 1.05V (Default)
High = 1.5V
High = Enabled
Low = Disabled
Low = Reverse Lane
CFG9 High = Normal Operation
*
*
*
*
*
*
(5mil:15mil) (12mil:10mil)
(12mil:10mil)
(10mil:20mil)
Un-pop for Dothan-A
H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil
HOST
Alviso
U5A
ALVISO_BGA1257
HD0# E4
HD1# E1
HD2# F4
HD3# H7
HD4# E2
HD5# F1
HD6# E3
HD7# D3
HD8# K7
HD9# F2
HD10# J7
HD11# J8
HD12# H6
HD13# F3
HD14# K8
HD15# H5
HD16# H1
HD17# H2
HD18# K5
HD19# K6
HD20# J4
HD21# G3
HD22# H3
HD23# J1
HD24# L5
HD25# K4
HD26# J5
HD27# P7
HD28# L7
HD29# J3
HD30# P5
HD31# L3
HD32# U7
HD33# V6
HD34# R6
HD35# R5
HD36# P3
HD37# T8
HD38# R7
HD39# R8
HD40# U8
HD41# R4
HD42# T4
HD43# T5
HD44# R1
HD45# T3
HD46# V8
HD47# U6
HD48# W6
HD49# U3
HD50# V5
HD51# W8
HD52# W7
HD53# U2
HD54# U1
HD55# Y5
HD56# Y2
HD57# V4
HD58# Y7
HD59# W1
HD60# W3
HD61# Y3
HD62# Y6
HD63# W2
HA3#
G9
HA4#
C9
HA5#
E9
HA6#
B7
HA7#
A10
HA8#
F9
HA9#
D8
HA10#
B10
HA11#
E10
HA12#
G10
HA13#
D9
HA14#
E11
HA15#
F10
HA16#
G11
HA17#
G13
HA18#
C10
HA19#
C11
HA20#
D11
HA21#
C12
HA22#
B13
HA23#
A12
HA24#
F12
HA25#
G12
HA26#
E12
HA27#
C13
HA28#
B11
HA29#
D13
HA30#
A13
HA31#
F13
HREQ#0
A7
HREQ#1
D7
HREQ#2
B8
HREQ#3
C7
HREQ#4
A8
HADSTB#0
B9
HADSTB#1
E13
HPCREQ#
A11
HCLKN
AB1
HCLKP
AB2
HVREF J11
HXRCOMP C1
HXSCOMP C2
HYRCOMP T1
HYSCOMP L1
HYSWING P1
HXSWING D1
HDSTBN#0
G4
HDSTBN#1
K1
HDSTBN#2
R3
HDSTBN#3
V3
HDSTBP#0
G5
HDSTBP#1
K2
HDSTBP#2
R2
HDSTBP#3
W4
HDINV#0
H8
HDINV#1
K3
HDINV#2
T7
HDINV#3
U5
HCPURST#
H10
HADS#
F8
HTRDY#
B5
HDPWR#
G6
HDRDY#
F7
HDEFER#
E6
HEDRDY#
F6
HHITM#
D6
HHIT#
D4
HLOCK#
B3
HBREQ0#
E7
HBNR#
A5
HBPRI#
D5
HDBSY#
C6
HCPUSLP#
G8
HRS0#
A4
HRS1#
C5
HRS2#
B4
R419
100_0603_1%
12
C489
0.1U_0402_16V4Z
1
2
C488
0.1U_0402_16V4Z
1
2
R426 40.2_0402_1%@
1 2
R40 10K_0402_5%
1 2
DMIDDR MUXING
CFG/RSVD
PM
CLK
NC
U5B
ALVISO_BGA1257
DMIRXN0
AA31
DMIRXN1
AB35
DMIRXP0
Y31
DMIRXP1
AA35
DMITXN0
AA33
DMITXN1
AB37
DMITXP0
Y33
DMITXP1
AA37
SM_CK0
AM33
SM_CK1
AL1
SM_CK2
AE11
SM_CK3
AJ34
SM_CK4
AF6
SM_CK5
AC10
SM_CK0#
AN33
SM_CK1#
AK1
SM_CK2#
AE10
SM_CK3#
AJ33
SM_CK4#
AF5
SM_CK5#
AD10
SM_CKE0
AP21
SM_CKE1
AM21
SM_CKE2
AH21
SM_CKE3
AK21
SM_CS0#
AN16
SM_CS1#
AM14
SM_CS2#
AH15
SM_CS3#
AG16
SM_OCDCOMP0
AF22
SM_OCDCOMP1
AF16
SM_ODT0
AP14
SM_ODT1
AL15
SM_ODT2
AM11
SM_ODT3
AN10
SMRCOMPN
AK10
SMRCOMPP
AK11
SMVREF0
AF37
SMVREF1
AD1
SMXSLEWIN
AE27
SMXSLEWOUT
AE28
SMYSLEWIN
AF9
SMYSLEWOUT
AF10
CFG0 G16
CFG1 H13
CFG2 G14
CFG3 F16
CFG4 F15
CFG5 G15
CFG6 E16
CFG7 D17
CFG8 J16
CFG9 D15
CFG10 E15
CFG11 D14
CFG12 E14
CFG13 H12
CFG14 C14
CFG15 H15
CFG16 J15
CFG17 H14
CFG18 G22
CFG19 G23
CFG20 D23
RSVD21 G25
RSVD22 G24
RSVD23 J17
RSVD24 A31
RSVD25 A30
RSVD26 D26
RSVD27 D25
BM_BUSY# J23
EXT_TS0# J21
EXT_TS1# H22
THRMTRIP# F5
PWROK AD30
RSTIN# AE29
DREF_CLKN A24
DREF_CLKP A23
DREF_SSCLKN C37
DREF_SSCLKP D37
NC1 AP37
NC2 AN37
NC3 AP36
NC4 AP2
NC5 AP1
NC6 AN1
NC7 B1
NC8 A2
NC9 B37
NC10 A36
NC11 A37
DMITXN2
AC33
DMITXN3
AD37
DMIRXN3
AD35 DMIRXN2
AC31
DMITXP2
AB33
DMITXP3
AC37
DMIRXP2
AB31
DMIRXP3
AC35
R430 80.6_0402_1%
1 2
R407 1K_0402_5%@
1 2
R429 80.6_0402_1%
1 2
R42 1K_0402_5%@
1 2
C436
0.1U_0402_16V4Z
1
2
R406
221_0603_1%
12
R412 1K_0402_5%@
1 2
R68 54.9_0402_1%
1 2
R421
1K_0402_1%
12
R417 1K_0402_5%@
1 2
R423
1K_0402_1%
12
R51 0_0402_5%PM@
1 2
R411 10K_0402_5%
1 2
C423
0.1U_0402_16V4Z
1
2
R388
100_0603_1%
12
R72 24.9_0402_1%
12
R408 1K_0402_5%@
1 2
R420
221_0603_1%
12
R413 1K_0402_5%@
1 2
R416 10K_0402_5%
1 2
R52 0_0402_5%PM@
1 2
R54 0_0402_5%
1 2
R427 40.2_0402_1%@
1 2
R41 1K_0402_5%@
1 2
R47 54.9_0402_1%
1 2
R405
100_0603_1%
12
R50 24.9_0402_1%
12
R409 1K_0402_5%@
1 2
C459
0.1U_0402_16V4Z
1
2
R387
200_0603_1%
12
R404 1K_0402_5%@
1 2
![](asset-7.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ7
DDRA_SDQ6
DDRA_SDQ5
DDRA_SDQ4
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQS5
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQS0 DDRA_SDQ12
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ13
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQS4
DDRA_SDM6
DDRA_SDM1
DDRA_SDM5
DDRA_SDM0
DDRA_SDM4
DDRA_SDM3
DDRA_SDM7
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ21
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ23
DDRA_SDQ16
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQS3
DDRA_SDQ27
DDRA_SDQ26
DDRA_SDQ29
DDRA_SDQ31
DDRA_SDQ30
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ28
DDRA_SDQS7
DDRA_SDQS2
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQS6
DDRA_SDQS1
DDRA_SMA3
DDRA_SMA7
DDRA_SMA2
DDRA_SMA0
DDRA_SMA6
DDRA_SMA1
DDRA_SMA10
DDRA_SMA12
DDRA_SMA5
DDRA_SMA9
DDRA_SMA8
DDRA_SMA4
DDRA_SMA11
DDRB_SMA3
DDRB_SMA7
DDRB_SMA2
DDRB_SMA0
DDRB_SMA6
DDRB_SMA1
DDRB_SMA10
DDRB_SMA12
DDRB_SMA5
DDRB_SMA9
DDRB_SMA8
DDRB_SMA4
DDRB_SMA11
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SDQS[0..7]
DDRA_SMA[0..13] DDRB_SMA[0..13]
DDRA_SMA13 DDRB_SMA13
DDRA_SCAS#11 DDRA_SRAS#11
DDRA_SBS011 DDRA_SBS111
DDRA_SWE#11 DDRB_SWE#12
DDRB_SBS012 DDRB_SBS112
DDRA_SDQ[0..63]11
DDRA_SDQS[0..7]11
DDRA_SDM[0..7]11
DDRA_SMA[0..13]11 DDRB_SMA[0..13]12
DDRB_SCAS#12 DDRB_SRAS#12
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
751¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DDR SYSTEM MEMORY B
U5D
ALVISO_BGA1257
SBDQ0 AE31
SBDQ1 AE32
SBDQ2 AG32
SBDQ3 AG36
SBDQ4 AE34
SBDQ5 AE33
SBDQ6 AF31
SBDQ7 AF30
SBDQ8 AH33
SBDQ9 AH32
SBDQ10 AK31
SBDQ11 AG30
SBDQ12 AG34
SBDQ13 AG33
SBDQ14 AH31
SBDQ15 AJ31
SBDQ16 AK30
SBDQ17 AJ30
SBDQ18 AH29
SBDQ19 AH28
SBDQ20 AK29
SBDQ21 AH30
SBDQ22 AH27
SBDQ23 AG28
SBDQ24 AF24
SBDQ25 AG23
SBDQ26 AJ22
SBDQ27 AK22
SBDQ28 AH24
SBDQ29 AH23
SBDQ30 AG22
SBDQ31 AJ21
SBDQ32 AG10
SBDQ33 AG9
SBDQ34 AG8
SBDQ35 AH8
SBDQ36 AH11
SBDQ37 AH10
SBDQ38 AJ9
SBDQ39 AK9
SBDQ40 AJ7
SBDQ41 AK6
SBDQ42 AJ4
SBDQ43 AH5
SBDQ44 AK8
SBDQ45 AJ8
SBDQ46 AJ5
SB_BS0#
AJ15
SB_BS1#
AG17
SB_BS2#
AG21
SBDQ47 AK4
SBDQ48 AG5
SBDQ49 AG4
SBDQ50 AD8
SBDQ51 AD9
SBDQ52 AH4
SBDQ53 AG6
SBDQ54 AE8
SBDQ55 AD7
SBDQ56 AC5
SBDQ57 AB8
SBDQ58 AB6
SBDQ59 AA8
SBDQ60 AC8
SBDQ61 AC7
SBDQ62 AA4
SBDQ63 AA5
SB_CAS#
AH14
SB_RAS#
AK14
SB_RCVENIN#
AF15
SB_RCVENOUT#
AF14
SB_WE#
AH16
SB_MA0
AH17
SB_MA1
AK17
SB_MA2
AH18
SB_MA3
AJ18
SB_MA4
AK18
SB_MA5
AJ19
SB_MA6
AK19
SB_MA7
AH19
SB_MA8
AJ20
SB_MA9
AH20
SB_MA10
AJ16
SB_MA11
AG18
SB_MA12
AG20
SB_MA13
AG15
SB_DQS0#
AF35
SB_DQS1#
AK33
SB_DQS2#
AK28
SB_DQS3#
AJ23
SB_DQS4#
AL10
SB_DQS5#
AH7
SB_DQS6#
AF7
SB_DQS7#
AB5
SB_DQS0
AF34
SB_DQS1
AK32
SB_DQS2
AJ28
SB_DQS3
AK23
SB_DQS4
AM10
SB_DQS5
AH6
SB_DQS6
AF8
SB_DQS7
AB4
SB_DM0
AF32
SB_DM1
AK34
SB_DM2
AK27
SB_DM3
AK24
SB_DM4
AJ10
SB_DM5
AK5
SB_DM6
AE7
SB_DM7
AB7
DDR MEMORY SYSTEM A
U5C
ALVISO_BGA1257
SADQ0 AG35
SADQ1 AH35
SADQ2 AL35
SADQ3 AL37
SADQ4 AH36
SADQ5 AJ35
SADQ6 AK37
SADQ7 AL34
SADQ8 AM36
SADQ9 AN35
SADQ10 AP32
SADQ11 AM31
SADQ12 AM34
SADQ13 AM35
SADQ14 AL32
SADQ15 AM32
SADQ16 AN31
SADQ17 AP31
SADQ18 AN28
SADQ19 AP28
SADQ20 AL30
SADQ21 AM30
SADQ22 AM28
SADQ23 AL28
SADQ24 AP27
SADQ25 AM27
SADQ26 AM23
SADQ27 AM22
SADQ28 AL23
SADQ29 AM24
SADQ30 AN22
SADQ31 AP22
SADQ32 AM9
SADQ33 AL9
SADQ34 AL6
SADQ35 AP7
SADQ36 AP11
SADQ37 AP10
SADQ38 AL7
SADQ39 AM7
SADQ40 AN5
SADQ41 AN6
SADQ42 AN3
SADQ43 AP3
SADQ44 AP6
SADQ45 AM6
SADQ46 AL4
SADQ47 AM3
SADQ48 AK2
SADQ49 AK3
SADQ50 AG2
SADQ51 AG1
SADQ52 AL3
SADQ53 AM2
SADQ54 AH3
SADQ55 AG3
SADQ56 AF3
SADQ57 AE3
SADQ58 AD6
SADQ59 AC4
SADQ60 AF2
SADQ61 AF1
SADQ62 AD4
SADQ63 AD5
SA_BS0#
AK15
SA_BS1#
AK16
SA_BS2#
AL21
SA_DM0
AJ37
SA_DM1
AP35
SA_DM2
AL29
SA_DM3
AP24
SA_DM4
AP9
SA_DM5
AP4
SA_DM6
AJ2
SA_DM7
AD3
SA_DQS0
AK36
SA_DQS1
AP33
SA_DQS2
AN29
SA_DQS3
AP23
SA_DQS4
AM8
SA_DQS5
AM4
SA_DQS6
AJ1
SA_DQS7
AE5
SA_DQS0#
AK35
SA_DQS1#
AP34
SA_DQS2#
AN30
SA_DQS3#
AN23
SA_DQS4#
AN8
SA_DQS5#
AM5
SA_DQS6#
AH1
SA_DQS7#
AE4
SA_MA0
AL17
SA_MA1
AP17
SA_MA2
AP18
SA_MA3
AM17
SA_MA4
AN18
SA_MA5
AM18
SA_MA6
AL19
SA_MA7
AP20
SA_MA8
AM19
SA_MA9
AL20
SA_MA10
AM16
SA_MA11
AN20
SA_MA12
AM20
SA_MA13
AM15
SA_CAS#
AN15
SA_RAS#
AP16
SA_RCVENIN#
AF29
SA_RCVENOUT#
AF28
SA_WE#
AP15
![](asset-8.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N15
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P12
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N0
GMCH_TZOUT1-
GMCH_TXOUT1-
GMCH_TXCLK-
GMCH_TZOUT2-
GMCH_TXCLK+
GMCH_TXOUT2-
GMCH_TZOUT1+
GMCH_TXOUT0+
GMCH_TZOUT2+
GMCH_TXOUT2+
GMCH_TXOUT0-
GMCH_TXOUT1+
GMCH_TZOUT0+
GMCH_TZOUT0-
GMCH_TZCLK-
GMCH_TZCLK+
LCTLB_DATA
LCTLA_CLK
GMCH_ENVDD
LIBG
LBKLT_EN
REFSET
GMCH_TV_LUMA
GMCH_TV_CRMA TV_REFSET
GMCH_CRT_DATA
PEG_COMP
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N5
PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_N5
PCEI_GTX_C_MRX_N11
PCEI_GTX_C_MRX_N14
PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_N2
PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_N12
PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_N8
PCEI_GTX_C_MRX_N10
PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_N4
PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_N13
PCEI_GTX_C_MRX_N9
PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_N15
PCEI_GTX_C_MRX_N1
PCEI_GTX_C_MRX_P15
PCEI_GTX_C_MRX_N6
PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_N3
PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_N7
PCEI_GTX_C_MRX_N0
GMCH_CRT_CLK
GMCH_TV_COMPS
LBKLT_EN
GMCH_CRT_CLK
GMCH_CRT_DATA
LDDC_CLK
LDDC_DATA
LIBG
LBKLT_EN
GMCH_LCD_CLK
LCTLB_DATA
LCTLA_CLK
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_GRX_N4 PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N3
GMCH_TV_COMPS
LDDC_CLK
GMCH_LCD_DATA
GMCH_TV_LUMA
GMCH_TV_CRMA
LDDC_DATA
PCEI_GTX_C_MRX_N[0..15]16
PCIE_MTX_C_GRX_P[0..15]16
PCIE_MTX_C_GRX_N[0..15]16
PCEI_GTX_C_MRX_P[0..15]16
GMCH_TXOUT1-16
GMCH_TXOUT1+16
GMCH_TXOUT2-16
GMCH_TXOUT2+16
GMCH_TXCLK+16 GMCH_TXCLK-16
GMCH_TZOUT1-16
GMCH_TZOUT1+16
GMCH_TZOUT2-16
GMCH_TZOUT2+16
GMCH_TXOUT0-16
GMCH_TXOUT0+16
GMCH_TZOUT0+16
GMCH_TZOUT0-16
GMCH_TZCLK+16 GMCH_TZCLK-16
GMCH_ENVDD16
GMCH_CRT_R15
GMCH_CRT_B15
GMCH_CRT_HSYNC15 GMCH_CRT_VSYNC15
GMCH_TV_CRMA15
CLK_MCH_3GPLL14 CLK_MCH_3GPLL#14
GMCH_CRT_G15
GMCH_TV_LUMA15
GMCH_ENBKL16,34
GMCH_CRT_DATA15 GMCH_CRT_CLK15
GMCH_LCD_CLK 16
GMCH_LCD_DATA 16
+2.5VS
+2.5VS
+1.5VS
+3VS +2.5VS
+2.5VS
+2.5VS
+3VS
+3VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
851¬P , 03, 2005
期一 一月
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Compal Electronics, Inc.
C71 0.1U_0402_16V4ZPM@
1 2
C83 0.1U_0402_16V4ZPM@
1 2
R39 2.2K_0402_5%
1 2
R44 75_0402_1%
1 2
R515 150_0402_5%
1 2
C115 0.1U_0402_16V4ZPM@
1 2
C101 0.1U_0402_16V4ZPM@
1 2
C110 0.1U_0402_16V4ZPM@
1 2
C73 0.1U_0402_16V4ZPM@
1 2
R399 0_0402_5%
12
C91 0.1U_0402_16V4ZPM@
1 2
C116 0.1U_0402_16V4ZPM@
1 2
C105 0.1U_0402_16V4ZPM@
1 2
R418 4.99K_0402_1%
12
R400 2.2K_0402_5%
1 2
C74 0.1U_0402_16V4ZPM@
1 2
C80 0.1U_0402_16V4ZPM@
1 2
R384 150_0402_5%
12
C100 0.1U_0402_16V4ZPM@
1 2
C63 0.1U_0402_16V4ZPM@
1 2
C114 0.1U_0402_16V4ZPM@
1 2
R386 150_0402_5%
12
R382 4.7K_0402_5%
1 2
C87 0.1U_0402_16V4ZPM@
1 2
R403 1.5K_0402_1%
1 2
R383 3K_0402_1%@
1 2
R381 4.7K_0402_5%
1 2
C79 0.1U_0402_16V4ZPM@
1 2
C60 0.1U_0402_16V4ZPM@
1 2
R516 150_0402_5%
1 2
R397
4.7K_0402_5%
GM@
1 2
C59 0.1U_0402_16V4ZPM@
1 2
C97 0.1U_0402_16V4ZPM@
1 2
R398 100K_0402_5%
1 2
R48 24.9_0402_1%
1 2
C109 0.1U_0402_16V4ZPM@
1 2
C76 0.1U_0402_16V4ZPM@
1 2
C98 0.1U_0402_16V4ZPM@
1 2
R385 150_0402_5%
12
C62 0.1U_0402_16V4ZPM@
1 2
R49 4.7K_0402_5%GM@
1 2
C104 0.1U_0402_16V4ZPM@
1 2
R402
2.2K_0402_5%GM@
12
C92 0.1U_0402_16V4ZPM@
1 2
R45
4.7K_0402_5%
GM@
1 2
C56 0.1U_0402_16V4ZPM@
1 2
C57 0.1U_0402_16V4ZPM@
1 2
R401 4.7K_0402_5%GM@
1 2
C75 0.1U_0402_16V4ZPM@
1 2
G
D
S
Q44 BSS138_SOT23GM@
2
1 3
R414 255_0402_1%
1 2
C58 0.1U_0402_16V4ZPM@
1 2
G
D
S
Q6 2N7002_SOT23GM@
2
13
C77 0.1U_0402_16V4ZPM@
1 2
C89 0.1U_0402_16V4ZPM@
1 2
R38 3K_0402_1%@
1 2
C78 0.1U_0402_16V4ZPM@
1 2
G
D
S
Q43 2N7002_SOT23GM@
2
13
MISCTVVGALVDS
PCI - EXPRESS GRAPHICS
U5G
ALVISO_BGA1257
SDVOCTRL_DATA
H24
SDVOCTRL_CLK
H25
GCLKN
AB29
GCLKP
AC29
TVDAC_A
A15
TVDAC_B
C16
TVDAC_C
A17
TV_REFSET
J18
TV_IRTNA
B15
TV_IRTNB
B16
TV_IRTNC
B17
GREEN#
B20
HSYNC
G21
DDCCLK
E24
DDCDATA
E23
BLUE
E21
BLUE#
D21
GREEN
C20
RED
A19
RED#
B19
VSYNC
H21
REFSET
J20
LDDC_CLK
F23
LBKLT_CTL
E25
LBKLT_EN
F25
LCTLA_CLK
C23
LCTLB_DATA
C22
LDDC_DATA
F22
LVDD_EN
F26
LIBG
C33
LVBG
C31
LVREFH
F28
LVREFL
F27
LACLKN
B30
LACLKP
B29
LBCLKN
C25
LBCLKP
C24
LADATAN0
B34
LADATAN1
B33
LADATAN2
B32
LADATAP0
A34
LADATAP1
A33
LADATAP2
B31
LBDATAN0
C29
LBDATAN1
D28
LBDATAN2
C27
LBDATAP2
C26
EXP_COMPI D36
EXP_ICOMPO D34
EXP_RXN0/SDVO_TVCLKIN# E30
EXP_RXN1/SDVO_INT# F34
EXP_RXN2/SDVO_FLDSTALL# G30
EXP_RXN3 H34
EXP_RXN4 J30
EXP_RXN5 K34
EXP_RXN6 L30
EXP_RXN7 M34
EXP_RXN8 N30
EXP_RXN9 P34
EXP_RXN10 R30
EXP_RXN11 T34
EXP_RXN12 U30
EXP_RXN13 V34
EXP_RXN14 W30
EXP_RXN15 Y34
EXP_RXP0/SDVO_TVCLKIN D30
EXP_RXP1/SDVO_INT E34
EXP_RXP2/SDVO_FLDSTALL F30
EXP_RXP3 G34
EXP_RXP4 H30
EXP_RXP5 J34
EXP_RXP6 K30
EXP_RXP7 L34
EXP_RXP8 M30
EXP_RXP9 N34
EXP_RXP10 P30
EXP_RXP11 R34
EXP_RXP12 T30
EXP_RXP13 U34
EXP_RXP14 V30
EXP_RXP15 W34
EXP_TXN0/SDVOB_RED# E32
EXP_TXN1/SDVOB_GREEN# F36
EXP_TXN2/SDVOB_BLUE# G32
EXP_TXN3/SDVOB_CLKN H36
EXP_TXN4/SDVOC_RED# J32
EXP_TXN5/SDVOC_GREEN# K36
EXP_TXN6/SDVOC_BLUE# L32
EXP_TXN7/SDVOC_CLKN M36
EXP_TXN8 N32
EXP_TXN9 P36
EXP_TXN10 R32
EXP_TXN11 T36
EXP_TXN12 U32
EXP_TXN13 V36
EXP_TXN14 W32
EXP_TXN15 Y36
EXP_TXP0/SDVOB_RED D32
EXP_TXP1/SDVOB_GREEN E36
EXP_TXP2/SDVOB_BLUE F32
EXP_TXP3/SDVOB_CLKP G36
EXP_TXP4/SDVOC_RED H32
EXP_TXP5/SDVOC_GREEN J36
EXP_TXP6/SDVOC_BLUE K32
EXP_TXP7/SDVOC_CLKP L36
EXP_TXP8 M32
EXP_TXP9 N36
EXP_TXP10 P32
EXP_TXP11 R36
EXP_TXP12 T32
EXP_TXP13 U36
EXP_TXP14 V32
EXP_TXP15 W36
LBDATAP0
C28
LBDATAP1
D27
![](asset-9.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3
+3GPLL
+1.05VS
+1.5VS
+1.05VS
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL
+3VS
+1.5VS
+2.5VS
+1.5VS_DDRDLL
+1.5VS_PEG
+1.5VS_3GPLL
+2.5VS_3GBG
+1.5VS
+1.5VS
+1.5VS_HPLL
+1.5VS_DPLLA
+DDRVCC
+1.5VS
+1.5VS_3GPLL
+1.5VS_PEG
+1.5VS
+1.5VS_DDRDLL
+1.5VS
+2.5VS_3GBG
+2.5VS
+2.5VS
+1.05VS
+1.5VS
+DDRVCC
+1.05VS
+2.5VS
+2.5VS
+1.5VS_MPLL
+1.5VS
+1.5VS
+1.5VS_DPLLB
+3VS_DAC
+3VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
951¬P , 03, 2005
期一 一月
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Compal Electronics, Inc.
VCCD_TVDAC (Ball D19)
VCCDQ_TVDAC (Ball H17)VCCD_LVDS(Ball A25,B25,B26)
VCCA_LVDS (Ball A35)
VCCHV(Ball A21,B21,B22)
VCCTX_LVDS(Ball A27,A28,B28)
VCC_SYNC(Ball H20)
VCCA_CRTDAC(Ball F19,E19)
60mA
60mA
0.15mA
950mA
4000mA
120mA
24mA
60mA
10mA
2mA
60mA
1000mA
2200mA
60mA
60mA
70mA
Change to 0 ohm
Change to 0 ohm Change to 0 ohm
Change to 0 ohm
Change to 0 ohm
VCCA_TVBG
(Ball H18)
120mA
VCCA_TVDAC
C451
0.1U_0402_16V4Z
1
2
C23
0.47U_0603_16V4Z
1
2
C439
4.7U_0805_10V4Z
1
2
C440
0.1U_0402_16V4Z
1
2
C433
0.1U_0402_16V4Z
1
2
C424
0.1U_0402_16V4Z
1
2
L7
CHB1608U301_0603
1 2
C447
0.1U_0402_16V4Z
1
2
C426
22U_1206_16V4Z_V1
1
2
C469
2.2U_0603_6.3V6K
1
2
C486
0.1U_0402_16V4Z
1
2
C412
22U_1206_16V4Z_V1
1
2
C417
0.1U_0402_16V4Z
1
2
C438
0.022U_0402_16V7K
1
2
C34
0.22U_0402_10V4Z
1
2
C483
0.1U_0402_16V4Z
1
2
C81
0.1U_0402_16V4Z
1
2
C413
4.7U_0805_10V4Z
1
2
C416
0.1U_0402_16V4Z
1
2
C520
0.1U_0402_16V4Z
12
C84
22U_1206_16V4Z_V1
1
2
C24
0.47U_0603_16V4Z
1
2
C21
4.7U_0805_10V4Z
1
2
C446
22U_1206_16V4Z_V1
1
2
+
C53
470U_D2_2.5VM
1
2
C422
0.022U_0402_16V7K
1
2
R79
0.5_0603_1%
1 2
C482
0.1U_0402_16V4Z
1
2
C20
4.7U_0805_10V4Z
1
2
C449
4.7U_0805_10V4Z
1
2
+
C88
330U_D2E_2.5VM
1
2
C505
0.1U_0402_16V4Z
12
C425
0.022U_0402_16V7K
1
2
L8
CHB1608U301_0603
1 2
R410 0_0603_5%
1 2
C82
0.1U_0402_16V4Z
12
C22
4.7U_0805_10V4Z
1
2
C474
2.2U_0603_6.3V6K
1
2
C456
2.2U_0603_6.3V6K
1
2
C55
10U_1206_16V4Z
1
2
C437
0.022U_0402_16V7K
1
2
C52
22U_1206_16V4Z_V1
1
2
POWER
U5E
ALVISO_BGA1257
VCC0
T29
VCC1
R29
VCC2
N29
VCC3
M29
VCC4
K29
VCC5
J29
VCC6
V28
VCC7
U28
VCC8
T28
VCC9
R28
VCC10
P28
VCC11
N28
VCC12
M28
VCC13
L28
VCC14
K28
VCC15
J28
VCC16
H28
VCC17
G28
VCC18
V27
VCC19
U27
VCC20
T27
VCC21
R27
VCC22
P27
VCC23
N27
VCC24
M27
VCC25
L27
VCC26
K27
VCC27
J27
VCC28
H27
VCC29
K26
VCC30
H26
VCC31
K25
VCC32
J25
VCC33
K24
VCC34
K23
VCC35
K22
VCC36
K21
VCC37
W20
VCC38
U20
VCC39
T20
VCC40
K20
VCC41
V19
VCC42
U19
VCC43
K19
VCC44
W18
VCC45
V18
VCC46
T18
VCC47
K18
VCC48
K17
VCCD_HMPLL1
AC1
VCCD_HMPLL2
AC2
VCCA_DPLLA
B23
VCCA_DPLLB
C35
VCCA_HPLL
AA1
VCCA_MPLL
AA2
VCCA_TVDACA0 F17
VCCA_TVDACA1 E17
VCCA_TVDACB0 D18
VCCA_TVDACB1 C18
VCCA_TVDACC0 F18
VCCA_TVDACC1 E18
VCCA_TVBG H18
VSSA_TVBG G18
VCCD_TVDAC D19
VCCDQ_TVDAC H17
VCCD_LVDS0 B26
VCCD_LVDS1 B25
VCCD_LVDS2 A25
VCCA_LVDS A35
VCCHV0 B22
VCCHV1 B21
VCCHV2 A21
VCCTX_LVDS0 B28
VCCTX_LVDS1 A28
VCCTX_LVDS2 A27
VCCA_SM0 AF20
VCCA_SM1 AP19
VCCA_SM2 AF19
VCCA_SM3 AF18
VCC3G0 AE37
VCC3G1 W37
VCC3G2 U37
VCC3G3 R37
VCC3G4 N37
VCC3G5 L37
VCC3G6 J37
VCCA_3GPLL0 Y29
VCCA_3GPLL1 Y28
VCCA_3GPLL2 Y27
VCCA_3GBG F37
VSSA_3GBG G37
VCC_SYNC H20
VCCA_CRTDAC0 F19
VCCA_CRTDAC1 E19
VSSA_CRTDAC G19
C517
0.1U_0402_16V4Z
12
C487
0.1U_0402_16V4Z
1
2
C86
0.1U_0402_16V4Z
1
2
C431
0.022U_0402_16V7K
1
2
C421
0.1U_0402_16V4Z
1
2
L25
CHB1608U301_0603
1 2
C452
0.1U_0402_16V4Z
1
2
C419
0.01U_0402_16V7K
1
2
C478
0.1U_0402_16V4Z
1
2
C494
0.1U_0402_16V4Z
1
2
C450
22U_1206_16V4Z_V1
1
2
C418
0.1U_0402_16V4Z
1
2
L9
CHB1608U301_0603
1 2
C415
0.1U_0402_16V4Z
1
2
L6
CHB1608U301_0603
1 2
C490
0.1U_0402_16V4Z
12
C49
0.22U_0402_10V4Z
1
2
C481
0.1U_0402_16V4Z
1
2
C498
0.1U_0402_16V4Z
1
2
C428
0.1U_0402_16V4Z
1
2
C496
0.1U_0402_16V4Z
1
2
C475
0.1U_0402_16V4Z
1
2
R415
0_0603_5%
1 2
C519
0.1U_0402_16V4Z
12
C420
0.1U_0402_16V4Z
1
2
C50
22U_1206_16V4Z_V1
1
2
C463
2.2U_0603_6.3V6K
1
2
C414
0.1U_0402_16V4Z
1
2
C432
0.1U_0402_16V4Z
1
2
R86
0_0603_5%
1 2
C457
2.2U_0603_6.3V6K
1
2
C434
0.1U_0402_16V4Z
1
2
POWER
U5F
ALVISO_BGA1257
VTT0
K13
VTT1
J13
VTT2
K12
VTT3
W11
VTT4
V11
VTT5
U11
VTT6
T11
VTT7
R11
VTT8
P11
VTT9
N11
VTT10
M11
VTT11
L11
VTT12
K11
VTT13
W10
VTT14
V10
VTT15
U10
VTT16
T10
VTT17
R10
VTT18
P10
VTT19
N10
VTT20
M10
VTT21
K10
VTT22
J10
VTT23
Y9
VTT24
W9
VTT25
U9
VTT26
R9
VTT27
P9
VTT28
N9
VTT29
M9
VTT30
L9
VTT31
J9
VTT32
N8
VTT33
M8
VTT34
N7
VTT35
M7
VTT36
N6
VTT37
M6
VTT38
A6
VTT39
N5
VTT40
M5
VTT41
N4
VTT42
M4
VTT43
N3
VTT44
M3
VTT45
N2
VTT46
M2
VTT47
B2
VTT48
V1
VTT49
N1
VTT50
M1
VTT51
G1
VCCSM0 AM37
VCCSM1 AH37
VCCSM2 AP29
VCCSM3 AD28
VCCSM4 AD27
VCCSM5 AC27
VCCSM6 AP26
VCCSM7 AN26
VCCSM8 AM26
VCCSM9 AL26
VCCSM10 AK26
VCCSM11 AJ26
VCCSM12 AH26
VCCSM13 AG26
VCCSM14 AF26
VCCSM15 AE26
VCCSM16 AP25
VCCSM17 AN25
VCCSM18 AM25
VCCSM19 AL25
VCCSM20 AK25
VCCSM21 AJ25
VCCSM22 AH25
VCCSM23 AG25
VCCSM24 AF25
VCCSM25 AE25
VCCSM26 AE24
VCCSM27 AE23
VCCSM28 AE22
VCCSM29 AE21
VCCSM30 AE20
VCCSM31 AE19
VCCSM32 AE18
VCCSM33 AE17
VCCSM34 AE16
VCCSM35 AE15
VCCSM36 AE14
VCCSM37 AP13
VCCSM38 AN13
VCCSM39 AM13
VCCSM40 AL13
VCCSM41 AK13
VCCSM42 AJ13
VCCSM43 AH13
VCCSM44 AG13
VCCSM45 AF13
VCCSM46 AE13
VCCSM47 AP12
VCCSM48 AN12
VCCSM49 AM12
VCCSM50 AL12
VCCSM51 AK12
VCCSM52 AJ12
VCCSM53 AH12
VCCSM54 AG12
VCCSM55 AF12
VCCSM56 AE12
VCCSM57 AD11
VCCSM58 AC11
VCCSM59 AB11
VCCSM60 AB10
VCCSM61 AB9
VCCSM62 AP8
VCCSM63 AM1
VCCSM64 AE1
C462
2.2U_0603_6.3V6K
1
2
![](asset-a.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.05VS
+1.05VS
+DDRVCC
+1.05VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
10 51¬P , 03, 2005
期一 一月
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Compal Electronics, Inc.
VSS
U5I
ALVISO_BGA1257
VSS271
Y1
VSS270
D2
VSS269
G2
VSS268
J2
VSS260
L2
VSS259
P2
VSS258
T2
VSS257
V2
VSS256
AD2
VSS255
AE2
VSS254
AH2
VSS253
AL2
VSS252
AN2
VSS251
A3
VSS250
C3
VSS249
AA3
VSS248
AB3
VSS247
AC3
VSS246
AJ3
VSS245
C4
VSS244
H4
VSS243
L4
VSS242
P4
VSS241
U4
VSS240
Y4
VSS239
AF4
VSS238
AN4
VSS237
E5
VSS236
W5
VSS235
AL5
VSS234
AP5
VSS233
B6
VSS232
J6
VSS231
L6
VSS230
P6
VSS229
T6
VSS228
AA6
VSS227
AC6
VSS226
AE6
VSS225
AJ6
VSS224
G7
VSS223
V7
VSS222
AA7
VSS221
AG7
VSS220
AK7
VSS219
AN7
VSS218
C8
VSS217
E8
VSS216
L8
VSS215
P8
VSS214
Y8
VSS213
AL8
VSS212
A9
VSS211
H9
VSS210
K9
VSS209
T9
VSS208
V9
VSS207
AA9
VSS206
AC9
VSS205
AE9
VSS204
AH9
VSS203
AN9
VSS202
D10
VSS201
L10
VSS200
Y10
VSSALVDS B36
VSS199
AA10
VSS198
F11
VSS197
H11
VSS196
Y11
VSS195 AA11
VSS194 AF11
VSS193 AG11
VSS192 AJ11
VSS191 AL11
VSS190 AN11
VSS189 B12
VSS188 D12
VSS187 J12
VSS186 A14
VSS185 B14
VSS184 F14
VSS183 J14
VSS182 K14
VSS181 AG14
VSS180 AJ14
VSS179 AL14
VSS178 AN14
VSS177 C15
VSS176 K15
VSS175 A16
VSS174 D16
VSS173 H16
VSS172 K16
VSS171 AL16
VSS170 C17
VSS169 G17
VSS168 AF17
VSS167 AJ17
VSS166 AN17
VSS165 A18
VSS164 B18
VSS163 U18
VSS162 AL18
VSS161 C19
VSS160 H19
VSS159 J19
VSS158 T19
VSS157 W19
VSS156 AG19
VSS155 AN19
VSS154 A20
VSS153 D20
VSS152 E20
VSS151 F20
VSS150 G20
VSS149 V20
VSS148 AK20
VSS147 C21
VSS146 F21
VSS145 AF21
VSS144 AN21
VSS143 A22
VSS142 D22
VSS141 E22
VSS140 J22
VSS139 AH22
VSS138 AL22
VSS137 H23
VSS136 AF23
VSS135 B24
VSS134 D24
VSS133 F24
VSS132 J24
VSS131 AG24
VSS130 AJ24
NCTF
U5H
ALVISO_BGA1257
VCCSM_NCTF31 AB12
VCCSM_NCTF30 AC12
VCCSM_NCTF29 AD12
VCCSM_NCTF28 AB13
VCCSM_NCTF27 AC13
VCCSM_NCTF26 AD13
VCCSM_NCTF25 AC14
VCCSM_NCTF24 AD14
VCCSM_NCTF23 AC15
VCCSM_NCTF22 AD15
VCCSM_NCTF21 AC16
VCCSM_NCTF20 AD16
VCCSM_NCTF19 AC17
VCCSM_NCTF18 AD17
VCCSM_NCTF17 AC18
VCCSM_NCTF16 AD18
VCCSM_NCTF15 AC19
VCCSM_NCTF14 AD19
VCCSM_NCTF13 AC20
VCCSM_NCTF12 AD20
VCCSM_NCTF11 AC21
VCCSM_NCTF10 AD21
VCCSM_NCTF9 AC22
VCCSM_NCTF8 AD22
VCCSM_NCTF7 AC23
VCCSM_NCTF6 AD23
VCCSM_NCTF5 AC24
VCCSM_NCTF4 AD24
VCCSM_NCTF3 AC25
VCCSM_NCTF2 AD25
VCCSM_NCTF1 AC26
VCC_NCTF78 L17
VCC_NCTF77 M17
VCC_NCTF76 N17
VCC_NCTF75 P17
VCC_NCTF74 T17
VCC_NCTF73 U17
VCC_NCTF72 V17
VCC_NCTF71 W17
VCC_NCTF70 L18
VCC_NCTF69 M18
VCC_NCTF68 N18
VCC_NCTF67 P18
VCC_NCTF66 R18
VCC_NCTF65 Y18
VCC_NCTF64 L19
VCC_NCTF63 M19
VCC_NCTF62 N19
VCC_NCTF61 P19
VCC_NCTF60 R19
VCC_NCTF59 Y19
VCC_NCTF58 L20
VCC_NCTF57 M20
VCC_NCTF56 N20
VCC_NCTF55 P20
VCC_NCTF54 R20
VCC_NCTF53 Y20
VCC_NCTF52 L21
VCC_NCTF51 M21
VCC_NCTF50 N21
VCC_NCTF49 P21
VCC_NCTF48 T21
VCC_NCTF47 U21
VCC_NCTF46 V21
VCC_NCTF45 W21
VCC_NCTF44 L22
VCC_NCTF43 M22
VCC_NCTF42 N22
VCC_NCTF41 P22
VCC_NCTF40 R22
VCC_NCTF39 T22
VCC_NCTF38 U22
VCC_NCTF37 V22
VCC_NCTF36 W22
VCC_NCTF35 L23
VCC_NCTF34 M23
VCC_NCTF33 N23
VCC_NCTF32 P23
VCC_NCTF31 R23
VCC_NCTF30 T23
VCC_NCTF29 U23
VCC_NCTF28 V23
VCC_NCTF27 W23
VCC_NCTF26 L24
VCC_NCTF25 M24
VCC_NCTF24 N24
VCC_NCTF23 P24
VCC_NCTF22 R24
VCC_NCTF21 T24
VCC_NCTF20 U24
VCC_NCTF19 V24
VCC_NCTF18 W24
VCC_NCTF17 L25
VCC_NCTF16 M25
VCC_NCTF15 N25
VCC_NCTF14 P25
VCC_NCTF13 R25
VCC_NCTF12 T25
VCC_NCTF11 U25
VCCSM_NCTF0 AD26
VTT_NCTF17
L12
VTT_NCTF16
M12
VTT_NCTF15
N12
VTT_NCTF14
P12
VTT_NCTF13
R12
VTT_NCTF12
T12
VTT_NCTF11
U12
VTT_NCTF10
V12
VTT_NCTF9
W12
VTT_NCTF8
L13
VTT_NCTF7
M13
VTT_NCTF6
N13
VTT_NCTF5
P13
VTT_NCTF4
R13
VTT_NCTF3
T13
VTT_NCTF2
U13
VTT_NCTF1
V13
VTT_NCTF0
W13
VSS_NCTF68
Y12
VSS_NCTF67
AA12
VSS_NCTF66
Y13
VSS_NCTF65
AA13
VSS_NCTF64
L14
VSS_NCTF63
M14
VSS_NCTF62
N14
VSS_NCTF61
P14
VSS_NCTF60
R14
VSS_NCTF59
T14
VSS_NCTF58
U14
VSS_NCTF57
V14
VSS_NCTF56
W14
VSS_NCTF55
Y14
VSS_NCTF54
AA14
VSS_NCTF53
AB14
VSS_NCTF52
L15
VSS_NCTF51
M15
VSS_NCTF50
N15
VSS_NCTF49
P15
VSS_NCTF48
R15
VSS_NCTF47
T15
VSS_NCTF46
U15
VSS_NCTF45
V15
VSS_NCTF44
W15
VSS_NCTF43
Y15
VSS_NCTF42
AA15
VSS_NCTF41
AB15
VSS_NCTF40
L16
VSS_NCTF39
M16
VSS_NCTF38
N16
VSS_NCTF37
P16
VSS_NCTF36
R16
VSS_NCTF35
T16
VSS_NCTF34
U16
VSS_NCTF33
V16
VSS_NCTF32
W16
VSS_NCTF31
Y16
VSS_NCTF30
AA16
VSS_NCTF29
AB16
VSS_NCTF28
R17
VSS_NCTF27
Y17
VSS_NCTF26
AA17
VSS_NCTF25
AB17
VSS_NCTF24
AA18
VSS_NCTF23
AB18
VSS_NCTF22
AA19
VSS_NCTF21
AB19
VSS_NCTF20
AA20
VSS_NCTF19
AB20
VSS_NCTF18
R21
VSS_NCTF17
Y21
VSS_NCTF16
AA21
VSS_NCTF15
AB21
VSS_NCTF14
Y22
VSS_NCTF13
AA22
VSS_NCTF12
AB22
VSS_NCTF11
Y23
VSS_NCTF10
AA23
VSS_NCTF9
AB23
VSS_NCTF8
Y24
VSS_NCTF7
AA24
VSS_NCTF6
AB24
VSS_NCTF5
Y25
VSS_NCTF4
AA25
VSS_NCTF3
AB25
VSS_NCTF2
Y26
VSS_NCTF1
AA26
VSS_NCTF0
AB26
VCC_NCTF10
V25
VCC_NCTF9
W25
VCC_NCTF8
L26
VCC_NCTF7
M26
VCC_NCTF6
N26
VCC_NCTF5
P26
VCC_NCTF4
R26
VCC_NCTF3
T26
VCC_NCTF2
U26
VCC_NCTF1
V26
VCC_NCTF0
W26
VSS
U5J
ALVISO_BGA1257
VSS267
AL24
VSS266
AN24
VSS265
A26
VSS264
E26
VSS263
G26
VSS262
J26
VSS261
B27
VSS129
E27
VSS128
G27
VSS127
W27
VSS126
AA27
VSS125
AB27
VSS124
AF27
VSS123
AG27
VSS122
AJ27
VSS121
AL27
VSS120
AN27
VSS119
E28
VSS118
W28
VSS117
AA28
VSS116
AB28
VSS115
AC28
VSS114
A29
VSS113
D29
VSS112
E29
VSS111
F29
VSS110
G29
VSS109
H29
VSS108
L29
VSS107
P29
VSS106
U29
VSS105
V29
VSS104
W29
VSS103
AA29
VSS102
AD29
VSS101
AG29
VSS100
AJ29
VSS99
AM29
VSS98
C30
VSS97
Y30
VSS96
AA30
VSS95
AB30
VSS94
AC30
VSS93
AE30
VSS92
AP30
VSS91
D31
VSS90
E31
VSS89
F31
VSS88
G31
VSS87
H31
VSS86
J31
VSS85
K31
VSS84
L31
VSS83
M31
VSS82
N31
VSS81
P31
VSS80
R31
VSS79
T31
VSS78
U31
VSS77
V31
VSS76
W31
VSS75
AD31
VSS74
AG31
VSS73
AL31
VSS72
A32
VSS71
C32
VSS70
Y32
VSS69
AA32
VSS68
AB32
VSS67 AC32
VSS66 AD32
VSS65 AJ32
VSS64 AN32
VSS63 D33
VSS62 E33
VSS61 F33
VSS60 G33
VSS59 H33
VSS58 J33
VSS57 K33
VSS56 L33
VSS55 M33
VSS54 N33
VSS53 P33
VSS52 R33
VSS51 T33
VSS50 U33
VSS49 V33
VSS48 W33
VSS47 AD33
VSS46 AF33
VSS45 AL33
VSS44 C34
VSS43 AA34
VSS42 AB34
VSS41 AC34
VSS40 AD34
VSS39 AH34
VSS38 AN34
VSS37 B35
VSS36 D35
VSS35 E35
VSS34 F35
VSS33 G35
VSS32 H35
VSS31 J35
VSS30 K35
VSS29 L35
VSS28 M35
VSS27 N35
VSS26 P35
VSS25 R35
VSS24 T35
VSS23 U35
VSS22 V35
VSS21 W35
VSS20 Y35
VSS19 AE35
VSS18 C36
VSS17 AA36
VSS16 AB36
VSS15 AC36
VSS14 AD36
VSS13 AE36
VSS12 AF36
VSS11 AJ36
VSS10 AL36
VSS9 AN36
VSS8 E37
VSS7 H37
VSS6 K37
VSS5 M37
VSS4 P37
VSS3 T37
VSS2 V37
VSS1 Y37
VSS0 AG37
![](asset-b.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRA_DQS2
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7
DDRA_DQ22
DDRA_DQ18
DDRA_DQ20
DDRA_DQ16
DDRA_DQ41
DDRA_DQ33
DDRA_DQ36
DDRA_DQ54
DDRA_DQ53
DDRA_DQ57
DDRA_DQ50
DDRA_DQ60
DDRA_DQ52
DDRA_DM6
DDRA_DM3
DDRA_DM7
DDRA_DM2
DDRA_DM4
DDRA_DM5
DDRA_DQ23
DDRA_DQ19
DDRA_DQ21
DDRA_DQ17
DDRA_DQ34
DDRA_DQ32
DDRA_DQ37
DDRA_DQ40
DDRA_DQ51
DDRA_DQ55
DDRA_DQ63
DDRA_DQ49
DDRA_DQ48
DDRA_DQ61
D_CK_SDATA
D_CK_SCLK
DDRA_SCAS#
DDRA_SRAS#
DDRA_SWE#
DDRA_SMA9
DDRA_SMA7
DDRA_SMA12
DDRA_SMA5
DDRA_SMA1
DDRA_SMA10
DDRA_SMA3
DDRA_SMA8
DDRA_SMA6
DDRA_SMA11
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_CKE1
DDRA_SCS#1DDRA_SCS#0
DDRA_CKE0
DDRA_SBS0 DDRA_SBS1
DDRA_CKE1
DDRA_SMA9
DDRA_SMA7
DDRA_SMA12
DDRA_SMA5
DDRA_CKE0
DDRA_SMA13
DDRA_DQ11
DDRA_DQ9
DDRA_DQ15
DDRA_DQ0
DDRA_DQ4
DDRA_DM0
DDRA_DQ6
DDRA_DQ2
DDRA_DQ8
DDRA_DQ12
DDRA_DM1
DDRA_DQ14
DDRA_DQ10
DDRA_DQ5
DDRA_DQ1
DDRA_DQS0
DDRA_DQ7
DDRA_DQ3
DDRA_DQ13
DDRA_DQS1
DDRA_DQ30
DDRA_DQ24
DDRA_DQ28
DDRA_DQ26
DDRA_DQ31
DDRA_DQ29
DDRA_DQ25
DDRA_DQ27
DDRA_DQ39
DDRA_DQ45
DDRA_DQ42
DDRA_DQ43
DDRA_DQ35
DDRA_DQ44
DDRA_DQ46
DDRA_DQ47
DDRA_DQ38
DDRA_DQ58
DDRA_DQ59
DDRA_DQ56
DDRA_DQ62
DDRA_DQ[0..63]
DDRA_DM[0..7]
DDRA_DQS[0..7]
DDRA_SDQ[0..63]
DDRA_SMA[0..13]
DDRA_SDM[0..7]
DDRA_SDQS[0..7]
DDRA_DQ10
DDRA_DQ0
DDRA_DQ4
DDRA_DM0
DDRA_DQ6
DDRA_DQ2
DDRA_DQ8
DDRA_DQ12
DDRA_DM1
DDRA_DQ14
DDRA_SDQ43
DDRA_SDQ21
DDRA_SDQ17
DDRA_SDQ45
DDRA_SDM2
DDRA_SDQ19
DDRA_SDQ40
DDRA_SDQ23
DDRA_SDM5
DDRA_SDQ24
DDRA_SDQ28
DDRA_SDQ26
DDRA_SDQ42
DDRA_SDM3
DDRA_SDQ31
DDRA_SDQ4
DDRA_SDQ0
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ2
DDRA_SDQ8
DDRA_SDQ12
DDRA_SDM1
DDRA_SDQ10
DDRA_SDQ14
DDRA_DQ43
DDRA_DQ39
DDRA_DQ45
DDRA_DM4
DDRA_DM5
DDRA_DQ34
DDRA_DQ32
DDRA_DQ37
DDRA_DQ40
DDRA_DQ42
DDRA_SDM4
DDRA_SDQ37
DDRA_SDQ32
DDRA_DQ31
DDRA_DQ24
DDRA_DM3
DDRA_DM2
DDRA_DQ23
DDRA_DQ19
DDRA_DQ21
DDRA_DQ17
DDRA_DQ28
DDRA_DQ26
DDRA_SDQ39
DDRA_SDQ34
DDRA_DQ58
DDRA_DM6
DDRA_DM7
DDRA_DQ51
DDRA_DQ55
DDRA_DQ63
DDRA_DQ48
DDRA_DQ49
DDRA_DQ61
DDRA_DQ59
DDRA_SDQ49
DDRA_SDQ48
DDRA_SDQ51
DDRA_SDQ55
DDRA_SDM6
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDM7
DDRA_SDQ63
DDRA_SDQ61
DDRA_SDQS6
DDRA_SDQS7
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQ35
DDRA_SDQ41
DDRA_SDQ33
DDRA_SDQ46
DDRA_SDQ57
DDRA_SDQ38
DDRA_SDQ11
DDRA_SDQ3
DDRA_SDQ9
DDRA_SDQ15
DDRA_SDQ27
DDRA_SDQ13
DDRA_SDQ29
DDRA_SDQ25
DDRA_SDQ5
DDRA_SDQ1
DDRA_SDQ7
DDRA_SDQS3
DDRA_SDQ22
DDRA_SDQ30
DDRA_DQ56
DDRA_DQ47
DDRA_DQ5
DDRA_DQ1
DDRA_DQ29
DDRA_DQ25
DDRA_DQ62
DDRA_DQ38
DDRA_DQ27
DDRA_DQS0
DDRA_DQ7
DDRA_DQ35
DDRA_DQ44
DDRA_DQ9
DDRA_DQ3
DDRA_DQ13
DDRA_DQS1
DDRA_DQ30
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7
DDRA_DQ22
DDRA_DQ33
DDRA_DQ36
DDRA_DQ41
DDRA_DQ46
DDRA_DQ54
DDRA_DQ53
DDRA_DQ57
DDRA_DQ50
DDRA_DQ60
DDRA_DQ52
DDRA_DQ11
DDRA_DQ15
DDRA_DQ20
DDRA_DQ16
DDRA_DQS2
DDRA_DQ18
DDRA_SDQ53
DDRA_SDQ52
DDRA_SDQ54
DDRA_SDQ50
DDRA_SDQ60
DDRA_SDQ62
DDRA_SDQ56
DDRA_SDQ36
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ20
DDRA_SDQ16
DDRA_SDQS1
DDRA_SDQS0
DDRA_SDQ47
DDRA_SDQ44
DDRA_SMA8
DDRA_SMA6
DDRA_SMA11
DDRA_SMA4
DDRA_SBS1
DDRA_SMA2
DDRA_SMA0
DDRA_SCAS#
DDRA_SCS#1
DDRA_SRAS#
DDRA_SCS#0
DDRA_SBS0
DDRA_SWE#
DDRA_SMA10
DDRA_SMA1
DDRA_SMA3
DDRA_SMA13
DDRA_SCAS# 7
DDRA_SRAS# 7
DDRA_SWE#7
DDRA_CKE0 6
DDRA_SCS#06DDRA_SCS#1 6
DDRA_CKE16
DDRA_CLK16DDRA_CLK1#6
DDRA_CLK2 6
DDRA_CLK2# 6
D_CK_SDATA12,14 D_CK_SCLK12,14
DDRA_SBS07DDRA_SBS1 7
DDRA_SMA[0..13]7
DDRA_SDQ[0..63]7
DDRA_SDQS[0..7]7
DDRA_SDM[0..7]7
DDRA_DM[0..7] 12
DDRA_DQ[0..63] 12
DDRA_DQS[0..7] 12
+DDRVCC
+3VS
+DIMM_VREF
+DDRVTT
+DDRVCC +DDRVCC
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
11 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DIMM0
R91
1K_0402_1%
12
RP35
56_0404_4P2R_5%
1 4
2 3
RP44
10_0404_4P2R_5%
1 4
2 3
RP40
10_0404_4P2R_5%
1 4
2 3
R89 56_0402_5%
1 2
RP8
10_0404_4P2R_5%
1 4
2 3
RP19
10_0404_4P2R_5%
1 4
2 3
RP34
56_0404_4P2R_5%
1 4
2 3
RP17
10_0404_4P2R_5%
1 4
2 3
RP18
10_0404_4P2R_5%
1 4
2 3
RP49
10_0404_4P2R_5%
1 4
2 3
RP41
10_0404_4P2R_5%
1 4
2 3
C121
0.1U_0402_16V4Z
1
2
RP45
10_0404_4P2R_5%
1 4
2 3
RP22
10_0404_4P2R_5%
1 4
2 3
RP37
10_0404_4P2R_5%
1 4
2 3
RP27
56_0404_4P2R_5%
1 4
2 3
RP9
10_0404_4P2R_5%
1 4
2 3
RP53
10_0404_4P2R_5%
1 4
2 3
RP46
10_0404_4P2R_5%
1 4
2 3
RP32
56_0404_4P2R_5%
1 4
2 3
RP33
56_0404_4P2R_5%
1 4
2 3
RP50
10_0404_4P2R_5%
1 4
2 3
RP24
10_0404_4P2R_5%
1 4
2 3
RP54
10_0404_4P2R_5%
1 4
2 3
R90 56_0402_5%
1 2
RP14
10_0404_4P2R_5%
1 4
2 3
R87 56_0402_5%
1 2
RP23
10_0404_4P2R_5%
1 4
2 3
RP10
10_0404_4P2R_5%
1 4
2 3
R92
1K_0402_1%
12
RP25
10_0404_4P2R_5%
1 4
2 3
RP26
56_0404_4P2R_5%
1 4
2 3
RP7
10_0404_4P2R_5%
1 4
2 3
RP38
10_0404_4P2R_5%
1 4
2 3
RP51
10_0404_4P2R_5%
1 4
2 3
RP47
10_0404_4P2R_5%
1 4
2 3
RP28
56_0404_4P2R_5%
1 4
2 3
RP20
10_0404_4P2R_5%
1 4
2 3
RP48
10_0404_4P2R_5%
1 4
2 3
RP15
10_0404_4P2R_5%
1 4
2 3
RP39
10_0404_4P2R_5%
1 4
2 3
RP55
10_0404_4P2R_5%
1 4
2 3
RP31
56_0404_4P2R_5%
1 4
2 3
RP42
10_0404_4P2R_5%
1 4
2 3
RP36
10_0404_4P2R_5%
1 4
2 3
RP21
10_0404_4P2R_5%
1 4
2 3
RP16
10_0404_4P2R_5%
1 4
2 3
RP6
10_0404_4P2R_5%
1 4
2 3
RP11
10_0404_4P2R_5%
1 4
2 3
RP30
56_0404_4P2R_5%
1 4
2 3
JP24
AMP_1565917-1
VREF
1
VSS
3
DQ0
5
DQ1
7
VDD
9
DQS0
11
DQ2
13
VSS
15
DQ3
17
DQ8
19
VDD
21
DQ9
23
DQS1
25
VSS
27
DQ10
29
DQ11
31
VDD
33
CK0
35
CK0#
37
VSS
39
DQ16
41
DQ17
43
VDD
45
DQS2
47
DQ18
49
VSS
51
DQ19
53
DQ24
55
VDD
57
DQ25
59
DQS3
61
VSS
63
DQ26
65
DQ27
67
VDD
69
CB0
71
CB1
73
VSS
75
DQS8
77
CB2
79
VDD
81
CB3
83
DU
85
VSS
87
CK2
89
CK2#
91
VDD
93
CKE1
95
DU/A13
97
A12
99
A9
101
VSS
103
A7
105
A5
107
A3
109
A1
111
VDD
113
A10/AP
115
BA0
117
WE#
119
S0#
121
DU
123
VSS
125
DQ32
127
DQ33
129
VDD
131
DQS4
133
DQ34
135
VSS
137
DQ35
139
DQ40
141
VDD
143
VREF 2
VSS 4
DQ4 6
DQ5 8
VDD 10
DM0 12
DQ6 14
VSS 16
DQ7 18
DQ12 20
VDD 22
DQ13 24
DM1 26
VSS 28
DQ14 30
DQ15 32
VDD 34
VDD 36
VSS 38
VSS 40
DQ20 42
DQ21 44
VDD 46
DM2 48
DQ22 50
VSS 52
DQ23 54
DQ28 56
VDD 58
DQ29 60
DM3 62
VSS 64
DQ30 66
DQ31 68
VDD 70
CB4 72
CB5 74
VSS 76
DM8 78
CB6 80
VDD 82
CB7 84
DU/RESET# 86
VSS 88
VSS 90
VDD 92
VDD 94
CKE0 96
DU/BA2 98
A11 100
A8 102
VSS 104
A6 106
A4 108
A2 110
A0 112
VDD 114
BA1 116
RAS# 118
CAS# 120
S1# 122
DU 124
VSS 126
DQ36 128
DQ37 130
VDD 132
DM4 134
DQ38 136
VSS 138
DQ39 140
DQ44 142
VDD 144
DQ41
145
DQS5
147
VSS
149
DQ42
151
DQ43
153
VDD
155
VDD
157
VSS
159
VSS
161
DQ48
163
DQ49
165
VDD
167
DQS6
169
DQ50
171
VSS
173
DQ51
175
DQ56
177
VDD
179
DQ57
181
DQS7
183
VSS
185
DQ58
187
DQ59
189
VDD
191
SDA
193
SCL
195
VDD_SPD
197
VDD_ID
199
DQ45 146
DM5 148
VSS 150
DQ46 152
DQ47 154
VDD 156
CK1# 158
CK1 160
VSS 162
DQ52 164
DQ53 166
VDD 168
DM6 170
DQ54 172
VSS 174
DQ55 176
DQ60 178
VDD 180
DQ61 182
DM7 184
VSS 186
DQ62 188
DQ63 190
VDD 192
SA0 194
SA1 196
SA2 198
DU 200
RP13
10_0404_4P2R_5%
1 4
2 3
RP43
10_0404_4P2R_5%
1 4
2 3
RP29
56_0404_4P2R_5%
1 4
2 3
RP52
10_0404_4P2R_5%
1 4
2 3
RP12
10_0404_4P2R_5%
1 4
2 3
![](asset-c.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRB_SMA9
DDRB_SMA7
DDRB_SMA12
DDRB_SMA5
DDRB_SMA8
DDRB_SMA6
DDRB_SMA11
DDRB_SMA4
DDRB_SMA1
DDRB_SMA10
DDRB_SMA3
DDRB_SCAS#
DDRB_SRAS#
DDRB_CKE1
DDRB_SCS#1DDRB_SCS#0
DDRB_CKE0
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1
D_CK_SDATA
D_CK_SCLK
DDRB_SWE#
DDRB_SBS0
DDRB_SMA13
DDRA_DQ5
DDRA_DQ1
DDRA_DQS0
DDRA_DQ7
DDRA_DQ11
DDRA_DQ9
DDRA_DQ15
DDRA_DQ3
DDRA_DQ13
DDRA_DQS1
DDRA_DQ10
DDRA_DQ0
DDRA_DQ4
DDRA_DM0
DDRA_DQ6
DDRA_DQ2
DDRA_DQ8
DDRA_DQ12
DDRA_DM1
DDRA_DQ14
DDRA_DQ29
DDRA_DQ25
DDRA_DQ27
DDRA_DQ30
DDRA_DQS2
DDRA_DQS3
DDRA_DQ22
DDRA_DQ18
DDRA_DQ20
DDRA_DQ16
DDRA_DQ31
DDRA_DQ24
DDRA_DM3
DDRA_DM2
DDRA_DQ23
DDRA_DQ19
DDRA_DQ21
DDRA_DQ17
DDRA_DQ28
DDRA_DQ26
DDRA_DQ56
DDRA_DQ47
DDRA_DQ62
DDRA_DQ38
DDRA_DQ35
DDRA_DQ44
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7
DDRA_DQ41
DDRA_DQ33
DDRA_DQ36
DDRA_DQ46
DDRA_DQ54
DDRA_DQ53
DDRA_DQ57
DDRA_DQ50
DDRA_DQ60
DDRA_DQ52
DDRA_DQ43
DDRA_DQ39
DDRA_DQ45
DDRA_DM4
DDRA_DM5
DDRA_DQ34
DDRA_DQ32
DDRA_DQ40
DDRA_DQ37
DDRA_DQ42
DDRA_DQ49
DDRA_DQ24
DDRA_DM2
DDRA_DQ23
DDRA_DQ19
DDRA_DQ21
DDRA_DQ17
DDRA_DQ10
DDRA_DQ0
DDRA_DQ4
DDRA_DM0
DDRA_DQ6
DDRA_DQ2
DDRA_DQ8
DDRA_DQ14
DDRA_DM1
DDRA_DQ12
DDRA_DQ31
DDRA_DQ26
DDRA_DM3
DDRA_DQ28
DDRB_SMA8
DDRB_SMA6
DDRB_SMA11
DDRB_SMA4
DDRB_SCAS#
DDRB_SRAS#
DDRB_SCS#1
DDRB_SBS1
DDRA_DQ43
DDRA_DQ39
DDRA_DQ45
DDRA_DM4
DDRA_DM5
DDRA_DQ34
DDRA_DQ32
DDRA_DQ40
DDRA_DQ37
DDRA_DQ42
DDRB_SMA2
DDRB_SMA0
DDRA_DQ5
DDRA_DQ1
DDRA_DQS0
DDRA_DQ7
DDRA_DQ11
DDRA_DQ9
DDRA_DQ15
DDRA_DQ3
DDRA_DQ13
DDRA_DQS1
DDRA_DQ29
DDRA_DQ25
DDRA_DQ27
DDRA_DQ30
DDRA_DQS2
DDRA_DQS3
DDRA_DQ22
DDRA_DQ18
DDRA_DQ20
DDRA_DQ16
DDRA_DQ[0..63]
DDRA_DM[0..7]
DDRA_DQS[0..7]
DDRB_SMA[0..13]
DDRB_CKE1
DDRB_SMA10
DDRA_DQ47
DDRA_DQ46
DDRB_SMA9
DDRB_SMA7
DDRB_SMA12
DDRB_SMA5
DDRB_SMA1
DDRB_SMA3
DDRA_DQ35
DDRA_DQ41
DDRB_SCS#0
DDRB_SMA13
DDRA_DQS5
DDRA_DQ44
DDRA_DQ38
DDRA_DQS4
DDRA_DQ33
DDRA_DQ36
DDRA_DQ56
DDRA_DQ62
DDRA_DQS6
DDRA_DQS7
DDRA_DQ54
DDRA_DQ53
DDRA_DQ57
DDRA_DQ50
DDRA_DQ60
DDRA_DQ52
DDRB_CKE0
DDRA_DQ58
DDRA_DM6
DDRA_DM7
DDRA_DQ51
DDRA_DQ55
DDRA_DQ63
DDRA_DQ59
DDRA_DQ61
DDRA_DM7
DDRA_DQ55
DDRA_DQ58
DDRA_DQ59
DDRA_DQ51
DDRA_DQ61
DDRA_DM6
DDRA_DQ48
DDRA_DQ63
DDRB_SBS0
DDRB_SWE#
DDRA_DQ48
DDRA_DQ49
DDRB_SCAS# 7
DDRB_SRAS# 7
DDRB_CKE0 6
DDRB_SCS#06DDRB_SCS#1 6
DDRB_CKE16
DDRB_CLK16DDRB_CLK1#6
DDRB_CLK2 6
DDRB_CLK2# 6
D_CK_SDATA11,14 D_CK_SCLK11,14
DDRB_SBS1 7
DDRB_SBS07DDRB_SWE#7
DDRA_DQ[0..63]11
DDRA_DQS[0..7]11
DDRA_DM[0..7]11
DDRB_SMA[0..13]7
+DDRVTT
+DDRVCC
+3VS
+DDRVCC +DIMM_VREF
+DDRVTT
+3VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
12 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
RP76
56_0404_4P2R_5%
1 4
2 3
RP77
56_0404_4P2R_5%
1 4
2 3
RP59
56_0404_4P2R_5%
14 23
RP70
56_0404_4P2R_5%
1 4
2 3
RP97
56_0404_4P2R_5%
14 23
RP105
56_0404_4P2R_5%
14 23
RP69
56_0404_4P2R_5%
1 4
2 3
C120
0.1U_0402_16V4Z
1
2
RP94
56_0404_4P2R_5%
14 23
R44456_0402_5%
12
RP109
56_0404_4P2R_5%
14 23
RP78
56_0404_4P2R_5%
1 4
2 3
RP68
56_0404_4P2R_5%
1 4
2 3
RP79
56_0404_4P2R_5%
1 4
2 3
RP66
56_0404_4P2R_5%
1 4
2 3
RP57
56_0404_4P2R_5%
14 23
RP98
56_0404_4P2R_5%
14 23
RP118
56_0404_4P2R_5%
14 23
RP96
56_0404_4P2R_5%
14 23
RP112
56_0404_4P2R_5%
14 23
RP75
56_0404_4P2R_5%
1 4
2 3
RP108
56_0404_4P2R_5%
14 23
RP61
56_0404_4P2R_5%
1 4
2 3
RP104
56_0404_4P2R_5%
14 23
RP80
56_0404_4P2R_5%
1 4
2 3
RP99
56_0404_4P2R_5%
14 23
JP25
AMP_1565918-1
VREF
1
VSS
3
DQ0
5
DQ1
7
VDD
9
DQS0
11
DQ2
13
VSS
15
DQ3
17
DQ8
19
VDD
21
DQ9
23
DQS1
25
VSS
27
DQ10
29
DQ11
31
VDD
33
CK0
35
CK0#
37
VSS
39
DQ16
41
DQ17
43
VDD
45
DQS2
47
DQ18
49
VSS
51
DQ19
53
DQ24
55
VDD
57
DQ25
59
DQS3
61
VSS
63
DQ26
65
DQ27
67
VDD
69
CB0
71
CB1
73
VSS
75
DQS8
77
CB2
79
VDD
81
CB3
83
DU
85
VSS
87
CK2
89
CK2#
91
VDD
93
CKE1
95
DU/A13
97
A12
99
A9
101
VSS
103
A7
105
A5
107
A3
109
A1
111
VDD
113
A10/AP
115
BA0
117
WE#
119
S0#
121
DU
123
VSS
125
DQ32
127
DQ33
129
VDD
131
DQS4
133
DQ34
135
VSS
137
DQ35
139
DQ40
141
VDD
143
VREF 2
VSS 4
DQ4 6
DQ5 8
VDD 10
DM0 12
DQ6 14
VSS 16
DQ7 18
DQ12 20
VDD 22
DQ13 24
DM1 26
VSS 28
DQ14 30
DQ15 32
VDD 34
VDD 36
VSS 38
VSS 40
DQ20 42
DQ21 44
VDD 46
DM2 48
DQ22 50
VSS 52
DQ23 54
DQ28 56
VDD 58
DQ29 60
DM3 62
VSS 64
DQ30 66
DQ31 68
VDD 70
CB4 72
CB5 74
VSS 76
DM8 78
CB6 80
VDD 82
CB7 84
DU/RESET# 86
VSS 88
VSS 90
VDD 92
VDD 94
CKE0 96
DU/BA2 98
A11 100
A8 102
VSS 104
A6 106
A4 108
A2 110
A0 112
VDD 114
BA1 116
RAS# 118
CAS# 120
S1# 122
DU 124
VSS 126
DQ36 128
DQ37 130
VDD 132
DM4 134
DQ38 136
VSS 138
DQ39 140
DQ44 142
VDD 144
DQ41
145
DQS5
147
VSS
149
DQ42
151
DQ43
153
VDD
155
VDD
157
VSS
159
VSS
161
DQ48
163
DQ49
165
VDD
167
DQS6
169
DQ50
171
VSS
173
DQ51
175
DQ56
177
VDD
179
DQ57
181
DQS7
183
VSS
185
DQ58
187
DQ59
189
VDD
191
SDA
193
SCL
195
VDD_SPD
197
VDD_ID
199
DQ45 146
DM5 148
VSS 150
DQ46 152
DQ47 154
VDD 156
CK1# 158
CK1 160
VSS 162
DQ52 164
DQ53 166
VDD 168
DM6 170
DQ54 172
VSS 174
DQ55 176
DQ60 178
VDD 180
DQ61 182
DM7 184
VSS 186
DQ62 188
DQ63 190
VDD 192
SA0 194
SA1 196
SA2 198
DU 200
RP117
56_0404_4P2R_5%
14 23
RP113
56_0404_4P2R_5%
14 23
RP106
56_0404_4P2R_5%
14 23
RP102
56_0404_4P2R_5%
14 23
RP65
56_0404_4P2R_5%
1 4
2 3
RP56
56_0404_4P2R_5%
14 23
RP71
56_0404_4P2R_5%
1 4
2 3
R9356_0402_5%
12
RP62
56_0404_4P2R_5%
1 4
2 3
RP73
56_0404_4P2R_5%
1 4
2 3
RP64
56_0404_4P2R_5%
1 4
2 3
RP107
56_0404_4P2R_5%
14 23
RP74
56_0404_4P2R_5%
1 4
2 3
RP67
56_0404_4P2R_5%
1 4
2 3
RP100
56_0404_4P2R_5%
14 23
RP63
56_0404_4P2R_5%
1 4
2 3
RP58
56_0404_4P2R_5%
14 23
RP101
56_0404_4P2R_5%
14 23
RP110
56_0404_4P2R_5%
14 23
RP60
56_0404_4P2R_5%
1 4
2 3
RP111
56_0404_4P2R_5%
14 23
RP95
56_0404_4P2R_5%
14 23
RP72
56_0404_4P2R_5%
1 4
2 3
RP114
56_0404_4P2R_5%
14 23
RP116
56_0404_4P2R_5%
14 23
R44556_0402_5%
12
RP115
56_0404_4P2R_5%
14 23
RP103
56_0404_4P2R_5%
14 23
![](asset-d.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+DDRVCC
+DDRVTT
+DDRVCC+DDRVCC
+DDRVTT
+DDRVTT
+DDRVTT
+DDRVTT
+DDRVTT
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
13 51
¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
Place one cap close to every 2 pull up resistors termination to
+1.25V
Layout note :
Layout note :
Distribute as close as possible
to DDR-SODIMM.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C130
0.1U_0402_16V4Z
1
2
C528
0.1U_0402_16V4Z
1
2
C531
0.1U_0402_16V4Z
1
2
C541
0.1U_0402_16V4Z
1
2
C113
0.1U_0402_16V4Z
1
2
C525
0.1U_0402_16V4Z
1
2
C524
0.1U_0402_16V4Z
1
2
C99
0.1U_0402_16V4Z
1
2
C123
0.1U_0402_16V4Z
1
2
C543
0.1U_0402_16V4Z
1
2
C112
0.1U_0402_16V4Z
1
2
C103
0.1U_0402_16V4Z
1
2
C93
0.1U_0402_16V4Z
1
2
C532
0.1U_0402_16V4Z
1
2
C138
0.1U_0402_16V4Z
1
2
C118
0.1U_0402_16V4Z
1
2
+
C85
150U_D2_6.3VM
1
2
C122
0.1U_0402_16V4Z
1
2
C119
0.1U_0402_16V4Z
1
2
C530
0.1U_0402_16V4Z
1
2
C96
0.1U_0402_16V4Z
1
2
C550
0.1U_0402_16V4Z
1
2
C111
0.1U_0402_16V4Z
1
2
C126
0.1U_0402_16V4Z
1
2
C529
0.1U_0402_16V4Z
1
2
C542
0.1U_0402_16V4Z
1
2
C548
0.1U_0402_16V4Z
1
2
C535
0.1U_0402_16V4Z
1
2
C136
0.1U_0402_16V4Z
1
2
C125
0.1U_0402_16V4Z
1
2
C124
0.1U_0402_16V4Z
1
2
C533
0.1U_0402_16V4Z
1
2
C547
0.1U_0402_16V4Z
1
2
C133
0.1U_0402_16V4Z
1
2
C134
0.1U_0402_16V4Z
1
2
C128
0.1U_0402_16V4Z
1
2
C526
0.1U_0402_16V4Z
1
2
C539
0.1U_0402_16V4Z
1
2
C102
0.1U_0402_16V4Z
1
2
C536
0.1U_0402_16V4Z
1
2
C95
0.1U_0402_16V4Z
1
2
C132
0.1U_0402_16V4Z
1
2
C135
0.1U_0402_16V4Z
1
2
C94
0.1U_0402_16V4Z
1
2
C127
0.1U_0402_16V4Z
1
2
C537
0.1U_0402_16V4Z
1
2
C131
0.1U_0402_16V4Z
1
2
C527
0.1U_0402_16V4Z
1
2
C538
0.1U_0402_16V4Z
1
2
C546
0.1U_0402_16V4Z
1
2
C129
0.1U_0402_16V4Z
1
2
C117
0.1U_0402_16V4Z
1
2
C545
0.1U_0402_16V4Z
1
2
C137
0.1U_0402_16V4Z
1
2
C540
0.1U_0402_16V4Z
1
2
C534
0.1U_0402_16V4Z
1
2
+
C139
150U_D2_6.3VM
1
2
C549
0.1U_0402_16V4Z
1
2
C544
0.1U_0402_16V4Z
1
2
![](asset-e.png)
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_DREF_96M
CLK_DREF_96M#
CLK_PCIE_SATA#
CLK_PCIE_SATA
CLK_MCH_3GPLL#
CLK_MCH_3GPLL
CLK_PCIE_ICH#
CLK_PCIE_ICH
CLK_CPU1
CLK_CPU1#
CLK_CPU0
CLK_CPU0#
CLK_CPU2
CLK_CPU2#
CLK_SRC5
CLK_SRC5#
CLK_SRC4
CLK_SRC4#
CLK_SRC3
CLK_SRC3#
CLK_SRC1
CLK_SRC1#
CLK_DOT
CLK_DOT#
CLK_SRC0
CLK_SRC0#
XTALOUT
XTALIN
+CLK_VDD48
+CLK_VDDREF
+CLK_VCCA
+CLK_VDD48 +CLK_VDDREF
CLK_PCIE_SATA#
CLK_PCIE_SATA
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_DREF_96M
CLK_DREF_96M#
CLK_PCIE_ICH#
CLK_PCIE_ICH
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_PCIE_LAN#
CLK_PCIE_LAN
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_3GPLL#
CLK_MCH_3GPLL
CLK_PCI3CLK_PCI_SIO
CLK_PCI_MINI CLK_PCI4
CLK_ICH_14M
CLK_REF CLK_14M_SIO
CLKSEL2CLK_SD_48M
CLK_ICH_48M
CLK_PCI0
CLK_PCI1CLK_PCI_LPC
CLKIREF
D_CK_SCLK
VTT_POWERGD#
D_CK_SDATA
CLK_PCI_ICH
STP_CPU#
STP_PCI#
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_PCIE_LAN#
CLK_PCIE_LAN
CLK_SRC2
CLK_SRC2#
D_CK_SDATA
D_CK_SCLK
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLKSEL2
CLKSEL0 CLKSEL1
CLK_14M_CODEC CLKSEL0
CLKSEL1
CLK_PCI2CLK_PCI_PCM
CLK_DREF_SSC# 6
CLK_DREF_SSC 6
CLK_CPU_BCLK# 4
CLK_CPU_BCLK 4
CLK_MCH_BCLK# 6
CLK_MCH_BCLK 6
CLK_DREF_96M# 6
CLK_DREF_96M 6
CLK_PCIE_SATA# 18
CLK_PCIE_SATA 18
CLK_MCH_3GPLL# 8
CLK_MCH_3GPLL 8
CLK_PCIE_ICH# 19
CLK_PCIE_ICH 19
CLK_PCI_MINI29
CLK_PCI_SIO33
CLK_ICH_14M 19
CLK_14M_SIO 33
CLK_SD_48M24
CLK_ICH_48M19
CLK_PCI_LPC34
CK_SDATA19
CK_SCLK19
CLK_PCI_ICH17
VGATE 6,19,49
PM_STP_PCI# 19
PM_STP_CPU# 19,49
CLK_PCIE_VGA# 16
CLK_PCIE_VGA 16
CLK_PCIE_LAN# 27
CLK_PCIE_LAN 27
MCH_CLKSEL1 6
CLK_PCI_PCM24
D_CK_SDATA11,12
D_CK_SCLK11,12
MCH_CLKSEL0 6
CPU_BSEL1 5CPU_BSEL0 5
CLK_14M_CODEC30
+CLK_VDD1 +CLK_VDD1
+CLK_VDD2 +3VS
+CLK_VDD2
+3VS
+3VS
+3VS
+CLK_VDD1
+1.05VS +1.05VS
+3VS
+3VS
+3VS
+3VS
+CLK_VDD1
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
14 51
¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
*
CLKSEL0 CLKSEL1 CLKSEL2
33.3
33.3
33.3
100
100
100
166
0
0
00
0
1
1
1
Table : ICS 954206B
FSC FSB FSA CPU
MHz SRC
MHz PCI
MHz
100
133
200
100 33.3
1
11
0
40mil
40mil
40mil
15mil
15mil
15mil
Change to 0 ohm
Change to 0 ohm
R106 33_0402_5%
1 2
R137 49.9_0402_1%
1 2
R148 12_0402_5%
1 2
C156
0.047U_0402_16V7K
1
2
R115 49.9_0402_1%
1 2
C147
0.047U_0402_16V7K
1
2
R147 12_0402_5%
1 2
R97 49.9_0402_1%
1 2
R454
1K_0402_5%@
1 2
R101 49.9_0402_1%
1 2
R124 33_0402_5%
1 2
R122 49.9_0402_1%
1 2
R118 49.9_0402_1%
1 2
R98 49.9_0402_1%
1 2
C553
2.2U_0603_6.3V6K
1
2
R96 33_0402_5%
1 2
R135 1_0402_5%
1 2
R448
0_0402_5%
12
R453
4.7K_0402_5%
1 2
R133 49.9_0402_1%
1 2
R119 49.9_0402_1%
1 2
R138 10K_0402_5%
1 2
R120 33_0402_5%
1 2
R145 10K_0402_5%
1 2
C150
0.047U_0402_16V7K
1
2
L10
KC FBM-L11-201209-221LMAT_0805
1 2
R459
0_0402_5%
12
R107 49.9_0402_1%
1 2
R113 33_0402_5%
1 2
G
D
S
Q14
2N7002_SOT23
2
1 3
R451
0_0402_5%@
1 2
R114 33_0402_5%
1 2
R123 49.9_0402_1%
1 2
R149 33_0402_5%
1 2
R151 12_0402_5%
12
R128 33_0402_5%
1 2
R132 49.9_0402_1%
1 2
R130 49.9_0402_1%
1 2
R127 49.9_0402_1%
1 2
Y1
14.318MHZ_20P_1BX14318CC1A
12
R103 49.9_0402_1%
1 2
R150 33_0402_5%
1 2
R125 33_0402_5%
1 2
G
D
S
Q17
2N7002_SOT23
2
1 3
R460
4.7K_0402_5%
1 2
R449
2.2_0402_5%
1 2
R139 10K_0402_5%
1 2
R450
0_0402_5%
1 2
C163
0.047U_0402_16V7K
1
2
R462
4.7K_0402_5%
1 2
C144
2.2U_0603_6.3V6K
1
2
G
D
S
Q16
2N7002_SOT23
2
1 3
R455 2.2_0402_5%
1 2
R112 49.9_0402_1%
1 2
R111 49.9_0402_1%
1 2
C555
2.2U_0603_6.3V6K
1
2
R146 33_0402_5%
1 2
R100 33_0402_5%
1 2
R143 12_0402_5%
1 2
R126 49.9_0402_1%
1 2
C165
2.2U_0603_6.3V6K
1
2
R136 33_0402_5%
1 2
R456
1K_0402_5%@
1 2
R461
4.7K_0402_5%
1 2
R457
0_0402_5%
1 2
R153 10K_0402_5%
1 2
R144 12_0402_5%
1 2
R102 33_0402_5%
1 2
C159
0.047U_0402_16V7K
1
2
R452 475_0402_1%
1 2
C145
0.047U_0402_16V7K
1
2
R134 33_0402_5%
1 2
R108 49.9_0402_1%
1 2
R99 33_0402_5%
1 2
R121 33_0402_5%
1 2
U8
ICS954226AGT_TSSOP56
VDDPCIEX_0
21
VDDPCIEX_1
28
VDDPCIEX_2
34
VDDPCI_0
1
VDDPCI_1
7
VDD48
11
VDDCPU
42
VDDREF
48
FS_A/USB_48MHz
12
GND_2
2
FSLB/TEST_MODE
16
X2
49
X1
50
GND_1
29
GND_0
13
GND_3
45
PCICLK2/REQ_SEL
56
REF1/FSLC/TEST_SEL
53
SDATA
47
SCLK
46
ITP_EN/PCICLK_F0
8
SELPCIEX_LCDCLK#/PCICLK_F1
9
IREF
39
PCIEXT4 31
CPU_STOP# 54
CPUCLKT1 41
CPUCLKC1 40
CPUCLKT2_ITP/PCIEXT6 36
PCIEXC4 30
PCICLK3
3
PCICLK4
4
PCICLK5
5
CPUCLKC0 43
CPUCLKT0 44
PEREQ1#/PCIEXT5 33
PEREQ2#/PCIEXC5 32
PCI/SRC_STOP# 55
GNDA 38
VDDA 37
REF0 52
GND_5
6
GND_4
51
CPUCLKC2_ITP/PCIEXC6 35
SATACLKT 26
SATACLKC 27
PCIEXT3 24
PCIEXC3 25
PCIEXT2 22
PCIEXC2 23
PCIEXT1 19
PCIEXC1 20
LCDCLK_SS/PCIEX0T 17
LCDCLK_SS/PCIEX0C 18
DOTT_96MHz 14
DOTC_96MHz 15
VTT_PWRGD#/PD 10
R131 33_0402_5%
1 2
C149
0.047U_0402_16V7K
1
2
C161
33P_0402_50V8J
1 2
R109 33_0402_5%
1 2
R110 33_0402_5%
1 2
C162
33P_0402_50V8J
1 2
R141 10K_0402_5%
1 2
C157
0.047U_0402_16V7K
1
2
R105 33_0402_5%
1 2
R117 33_0402_5%
1 2
C152
0.047U_0402_16V7K
1
2
R142 33_0402_5%
1 2
R104 49.9_0402_1%
1 2
R458
0_0402_5%@
1 2
R154 33_0402_5%
1 2
L11
KC FBM-L11-201209-221LMAT_0805
1 2
R129 33_0402_5%
1 2
![](asset-f.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
HSYNC_L
VSYNC_L
CRT_HSYNC D_CRT_HSYNC
CRT_G
CRT_VSYNC D_CRT_VSYNC
VGA_DDC_CLK
VGA_DDC_DATADSUB_12
DSUB_15
CRT_R CRT_R_L
CRT_B_L
CRT_G_L
VGA_DDC_CLK
VGA_DDC_DATAD_DDC_DATA
D_DDC_CLK
DSUB_12
DSUB_15
D_CRT_R
D_CRT_G
LUMA_1
D_CRT_B
CRT_R_F
CRT_B
DOCKIN#
CRMA_1
D_CRT_B
D_CRT_R
D_CRT_G
CRT_B_F
CRT_G_F
CRT_G
CRT_R
CRT_BCRT_B_F
CRT_G_F
CRT_R_F
VGA_TV_LUMA16
VGA_TV_CRMA16
GMCH_TV_LUMA8
GMCH_TV_CRMA8
VGA_CRT_R16
VGA_CRT_G16
VGA_CRT_B16
GMCH_CRT_R8
GMCH_CRT_G8
GMCH_CRT_B8
VGA_CRT_HSYNC16
VGA_CRT_VSYNC16
GMCH_CRT_HSYNC8
GMCH_CRT_VSYNC8
D_CRT_HSYNC 39
D_CRT_VSYNC 39
VGA_DDC_DATA 16
VGA_DDC_CLK 16
GMCH_CRT_DATA 8
GMCH_CRT_CLK 8
D_DDC_CLK39
D_DDC_DATA39
DOCKIN#34,39
D_CRT_B 39
D_CRT_R 39
D_CRT_G 39
+CRT_VCC+R_CRT_VCC
+5VS
+CRT_VCC
+CRT_VCC
+3VS
+2.5VS
+CRT_VCC
+3VS
+2.5VS
+5VS
+2.5VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
15 51
¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
W=40mils
CRT Connector
DDC_MD2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
W=40mils
3. Y (luminance+sync)
1. Y ground
2. C ground
4. C (crominance)
TV-OUT Conn.
Pop with No-Docking
R518 470_0402_5%
1 2
R572 0_0402_5%WO/D@
1 2
C506
22P_0402_50V8J
@
1 2
D23
DAN217_SC59@
2
31
D21
DAN217_SC59@
2
31
C485
22P_0402_50V8J
@
1 2
R19 0_0402_5%PM@
1 2
C10 0.1U_0402_16V4Z
1 2
R571 0_0402_5%WO/D@
1 2
C518
270P_0402_50V7K
12
C1
8P_0402_50V8K@
1
2
C408
100P_0402_50V8J
1
2
R380 0_0402_5%PM@
1 2
R424 0_0402_5%GM@
1 2
R519 470_0402_5%
1 2
L1 FCM1608C-121T_0603
1 2
D22
DAN217_SC59@
2
31
R4
4.7K_0402_5%
12
R18 0_0402_5%GM@
1 2
L3
FCM2012C-800_0805
1 2
C8
8P_0402_50V8K
1
2
C54
330P_0402_50V7K
12
C18 0.1U_0402_16V4Z
1 2
R379 0_0402_5%PM@
1 2
JP10
SUYIN_030244FS004TX01ZA
1
1
2
2
3
3
4
4
55
66
U35
SN74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
R434 0_0402_5%PM@
1 2
C407
68P_0402_50V8K
1
2
C9
8P_0402_50V8K
1
2
R11 0_0402_5%GM@
12
R9 0_0402_5%PM@
1 2
R34 0_0402_5%PM@
1 2
L4
FCM2012C-800_0805
1 2
R377 0_0402_5%PM@
1 2
C44
330P_0402_50V7K
12
C6
10P_0402_50V8J
1
2
R517 470_0402_5%
1 2
C5
10P_0402_50V8J
1
2
D1
RB411D_SOT23
2 1
R21 0_0402_5%GM@
1 2
L2 FCM1608C-121T_0603
1 2
L5
FCM2012C-800_0805
1 2
G
D
S
Q1
BSS138_SOT23
2
1 3
C410 0.1U_0402_16V4Z
1 2
JP1
SUYIN_070453FR015S208CU
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
16
17
L33
FBM-11-160808-121T_0603
1 2
G
D
S
Q42 BSS138_SOT23GM@
2
1 3
C495
270P_0402_50V7K
12
R8 0_0402_5%PM@
1 2
C409
68P_0402_50V8K
1
2
R10 0_0402_5%GM@
1 2
L28
FBM-11-160808-121T_0603
1 2
C3
8P_0402_50V8K@
1
2
R12 0_0402_5%GM@
12
U1
SN74AHCT1G125GW_SOT353-5
A
2Y4
OE# 1
G
3P5
R3
150_0402_5%
12
C4
0.1U_0402_16V4Z
1
2
R32 0_0402_5%PM@
1 2
R1
150_0402_5%
12
U4
FSAV330MTC_TSSOP16
W/D@
SEL
1
1A
4
2A
7
GND
8
3A
9
4A
12
OE#
15
VCC 16
1B1 2
2B1 5
3B1 11
4B1 14
1B2 3
2B2 6
3B2 10
4B2 13
R6 10K_0402_5%
12
R5
4.7K_0402_5%
12
R2
150_0402_5%
12
F1
POLYSWITCH_1A
G
D
S
Q41
BSS138_SOT23GM@
2
1 3
R428
150_0402_5%
12
R433 0_0402_5%GM@
1 2
R7 39_0402_5%GM@
1 2
R33 0_0402_5%GM@
1 2
R570 0_0402_5%WO/D@
1 2
R378 39_0402_5%GM@
1 2
L27
FBM-11-160808-121T_0603
1 2
R432
150_0402_5%
12
R422 0_0402_5%PM@
1 2
G
D
S
Q2
BSS138_SOT23
2
1 3
C7
8P_0402_50V8K
1
2
C2
8P_0402_50V8K@
1
2
![](asset-10.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BKOFF# DISPOFF#
PCEI_GTX_C_MRX_P[0..15]
PCEI_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
GMCH_LCD_CLK
GMCH_LCD_DATA
DAC_BRIG
INVT_PWM
DISPOFF#
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P14
PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_P15
PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_N11
PCEI_GTX_C_MRX_N8
PCEI_GTX_C_MRX_N10
PCEI_GTX_C_MRX_N9
PCEI_GTX_C_MRX_N5
PCEI_GTX_C_MRX_N14
PCEI_GTX_C_MRX_N12
PCEI_GTX_C_MRX_N13
PCEI_GTX_C_MRX_N15
PCEI_GTX_C_MRX_N1
PCEI_GTX_C_MRX_N3
PCEI_GTX_C_MRX_N7
PCEI_GTX_C_MRX_N2
PCEI_GTX_C_MRX_N4
PCEI_GTX_C_MRX_N6
PCEI_GTX_C_MRX_N0
PCEI_GTX_C_MRX_P4
DAC_BRIG
VGA_CRT_R
PCIE_MTX_C_GRX_N1
VGA_DDC_DATA
VGA_DDC_CLK
DISPOFF#
INVT_PWM
VGA_CRT_B VGA_CRT_VSYNC
VGA_CRT_HSYNC
VGA_CRT_G
VGA_TV_LUMA
VGA_TV_CRMA
SUSP#
GMCH_ENBKL
GMCH_TZCLK+
GMCH_TZCLK-
GMCH_TZOUT2+
GMCH_TZOUT2-
GMCH_TZOUT1+
GMCH_TZOUT1-
GMCH_TXCLK+
GMCH_TXCLK-
GMCH_TXOUT2+
GMCH_TXOUT2-
GMCH_TXOUT1-
GMCH_TXOUT1+
GMCH_TXOUT0-
GMCH_TXOUT0+GMCH_TZOUT0+
GMCH_TZOUT0-
LCD_ID
LCD_ID
GMCH_ENVDD
BKOFF#34
PCIE_MTX_C_GRX_N[0..15]8
PCEI_GTX_C_MRX_P[0..15]8
PCEI_GTX_C_MRX_N[0..15]8
PCIE_MTX_C_GRX_P[0..15]8
INVT_PWM 34
DAC_BRIG 34
GMCH_LCD_DATA8 GMCH_LCD_CLK8
CLK_PCIE_VGA 14
CLK_PCIE_VGA# 14
PLTRST_VGA#19
VGA_DDC_DATA 15
VGA_DDC_CLK 15
VGA_CRT_B15 VGA_CRT_HSYNC 15
VGA_CRT_VSYNC 15
VGA_CRT_G15
VGA_TV_LUMA 15
VGA_TV_CRMA 15
SUSP# 26,32,34,36,37,41,47,48
GMCH_ENBKL 8,34
DVI_TXD1+39 DVI_TXD1-39
DVI_TXD0+39 DVI_TXD0-39
DVI_TXC+39 DVI_TXC-39
DVI_TXD2+39 DVI_TXD2-39
VGA_CRT_R15
DVI_SCLK 39
DVI_SDATA 39
DVI_DET 39
GMCH_TZCLK-8 GMCH_TZCLK+8
GMCH_TZOUT2+8 GMCH_TZOUT2-8
GMCH_TZOUT1+8 GMCH_TZOUT1-8
GMCH_TXCLK+ 8
GMCH_TXCLK- 8
GMCH_TXOUT2+ 8
GMCH_TXOUT2- 8
GMCH_TXOUT1- 8
GMCH_TXOUT1+ 8
GMCH_TXOUT0+ 8
GMCH_TXOUT0- 8
GMCH_TZOUT0+8 GMCH_TZOUT0-8
PLT_RST#6,17,19,21,22,24,27,33,34
GMCH_ENVDD8
LCD_ID17,33
+3VS
+LCDVDD
+3VALW
+3VS
+3VS
B+
+LCDVDD
B+
B+
+LCDVDD
+3VS
+1.5VS
+3VALW
+2.5VS
+3VS
+5VALW
+5VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
16 51
¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD POWER CIRCUIT
LCD/PANEL BD. Conn.
VGA BOARD Conn.
R477
4.7K_0402_5%
12
R511 0_0402_5%@
1 2
R55
100K_0402_5%GM@
1 2
R510 0_0402_5%PM@
1 2
R62 100_0402_5%GM@
1 2
C663
0.01U_0402_25V7KGM@
1
2
C19
0.1U_0402_16V4Z@
1
2
C28
4.7U_0805_10V4ZGM@
1
2
U44 SN74AHCT1G125GW_SOT353-5GM@
A
2Y4
OE# 1
G
3P5
C29
0.1U_0402_16V4ZGM@
1
2
Q9 SI2301DS_SOT23GM@
2
1 3
C27
0.047U_0402_16V7KGM@
1
2
R53
300_0402_5%GM@
12
D32
RB751V_SOD323
21
G
D
S
Q8
2N7002_SOT23GM@
2
13
JP11
ACES_88081-1600PM@
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
97 98
99 100
101 102
103 104
105 106
107 108
109 110
111 112
113 114
115 116
117 118
119 120
121 122
123 124
125 126
127 128
129 130
131 132
133 134
135 136
137 138
139 140
141 142
143 144
145 146
147 148
149 150
151 152
153 154
155 156
157 158
159 160
JP6
ACES_87216-4012GM@
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
![](asset-11.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_PCI_ICH
PCI_SERR#
PCI_DEVSEL#
PCI_RST#
PCI_CBE#0
PCI_REQ#4
PCI_PERR#
PCI_PIRQG#
PCI_PIRQB#
PCI_STOP#
PCI_CBE#1
PCI_CBE#3
PCI_REQ#2
PCI_FRAME#
PCI_REQ#3
PCI_PLOCK#
PCI_IRDY#
PCI_CBE#2
PCI_REQ#1
PCI_PIRQA#
PCI_PAR
PCI_TRDY#
PCI_PIRQH#
CLK_ICH_PCI
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD7
PCI_AD6
PCI_AD8
PCI_AD9
PCI_AD11
PCI_AD10
PCI_AD14
PCI_AD15
PCI_AD13
PCI_AD12
PCI_AD16
PCI_AD17
PCI_AD19
PCI_AD18
PCI_AD22
PCI_AD23
PCI_AD21
PCI_AD20
PCI_AD25
PCI_AD24
PCI_AD28
PCI_AD29
PCI_AD31
PCI_AD30
PCI_AD26
PCI_AD27PCI_PIRQG#
PCI_REQ#4
PCI_GNT#2
PCI_PIRQD#
PCI_PIRQC#
PCI_GNT#0
PCI_REQ#0
PCI_PIRQF#
PCI_PIRQE#
PCI_REQ#5
PCI_GNT#1
PCI_GNT#3
PCI_REQ#5
PCI_REQ#6
PCI_REQ#2
PCI_PIRQH#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#3
PCI_PERR#
PCI_DEVSEL#
PCI_IRDY#
PCI_PLOCK#
PCI_GNT#5
PLT_RST#
PCI_GNT#5
PCI_GNT#6
PCI_GNT#4
PCI_STOP#
PCI_SERR#
PCI_FRAME#
PCI_TRDY#
PCI_PIRQD#
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQC#
PCI_REQ#6
PCI_AD[0..31]24,29
PCI_FRAME#24,29
PCI_REQ#2 24
PCI_GNT#2 24
PCI_IRDY# 24,29
PCI_PAR 24,29
PCI_PERR# 24,29
PCI_STOP# 24,29
PCI_SERR# 24,29
PCI_DEVSEL# 24,29
PCI_TRDY# 24,29
CLK_PCI_ICH 14
PCI_C/BE#0 24,29
PCI_C/BE#1 24,29
PCI_C/BE#2 24,29
PCI_C/BE#3 24,29
PCI_PIRQA#24 PCI_PIRQB#24
PLT_RST# 6,16,19,21,22,24,27,33,34
PCI_REQ#1 29
PCI_GNT#1 29
PCI_PIRQH# 29
PCI_PIRQG# 29PCI_PIRQC#24 PCI_PIRQD#24
PCI_RST# 22,24,29,33,34
LCD_ID 16,33
BT_DET# 33,35
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
17 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2492
Internal Pull-up.
Sample high destination is LPC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
RP91
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP92
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP88
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R576 0_0402_5%@
12
RP87
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP90
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R177
10_0402_5%@
1 2
RP89
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R575 0_0402_5% @
12
R231
0_0402_5%@
12
C192
10P_0402_50V8J@
1
2
Interrupt I/F
PCI
RESERVED
U17B
ICH6_BGA609
AD[0]
E2
AD[1]
E5
AD[2]
C2
AD[3]
F5
AD[4]
F3
AD[5]
E9
AD[6]
F2
AD[7]
D6
AD[8]
E6
AD[9]
D3
AD[10]
A2
AD[11]
D2
AD[12]
D5
AD[13]
H3
AD[14]
B4
AD[15]
J5
AD[16]
K2
AD[17]
K5
AD[18]
D4
AD[19]
L6
AD[20]
G3
AD[21]
H4
AD[22]
H2
AD[23]
H5
AD[24]
B3
AD[25]
M6
AD[26]
B2
AD[27]
K6
AD[28]
K3
AD[29]
A5
AD[30]
L1
AD[31]
K4
FRAME#
J3
REQ[0]# L5
GNT[0]# C1
REQ[1]# B5
GNT[1]# B6
REQ[2]# M5
GNT[2]# F1
REQ[3]# B8
GNT[3]# C8
REQ[4]#/GPI[40] F7
GNT[4]#/GPO[48] E7
REQ[5]#/GPI[1] E8
GNT[5]#/GPO[17] F6
REQ[6]#/GPI[0] B7
TRDY# J2
STOP# J1
PLTRST# R5
PCICLK G6
PME# P6
PIRQ[E]#/GPI[2] D9
PIRQ[F]#/GPI[3] C7
PIRQ[G]#GPI[4] C6
PIRQ[H]#/GPI[5] M3
GNT[6]#/GPO[16] D8
C/BE[0]# J6
C/BE[1]# H6
C/BE[2]# G4
C/BE[3]# G2
IRDY# A3
PAR E1
PCIRST# R2
DEVSEL# C3
PERR# E3
PLOCK# C5
SERR# G5
PIRQ[C]#
M1
SATA[1]TXP/RSVD[4]
AG4
PIRQ[A]#
N2
SATA[3]RXN/RSVD[5]
AC9
SATA[1]RXP/RSVD[2]
AD5
SATA[1]TXN/RSVD[3]
AF4
PIRQ[B]#
L2
PIRQ[D]#
L3
SATA[1]RXN/RSVD[1]
AC5
SATA[3]RXP/RSVD[6]
AD9
SATA[3]TXN/RSVD[7]
AF8
SATA[3]TXP/RSVD[8]
AG8
TP[3]/RSVD[9]
U3
![](asset-12.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LPC_FRAME#
AC_SDIN0
AC97_RST_R#
ICH_RTCX2 LPC_LAD2
LPC_LAD1
LPC_LAD0
LPC_LAD3
CLK_PCIE_SATA
H_A20M#
H_INIT#
H_IGNNE#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
H_PWRGOOD
THRMTRIP#
ICH_RTCX1
INTRUDER#
SATARBIAS
INTRUDER#
CLK_PCIE_SATA#
ICH_RTCRST#
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0 IDE_DCS1#
IDE_DA1
IDE_DD14
IDE_DA2
IDE_DD15
IDE_DD13
IDE_DD10
IDE_DD12
IDE_DD11
IDE_DD9
IDE_DD6
IDE_DD8
IDE_DD7
IDE_DD4
IDE_DD5
IDE_DDREQ
IDE_DD3
IDE_DD2
IDE_DD0
IDE_DD1
IDE_DCS3#
IDE_DA0
IDE_IRQ
IDE_DIOR#
IDE_DIOW#
IDE_DDACK#
IDE_DIORDY
IDE_IRQ
IDE_DIORDY
AC97_SYNC_R
AC97_SDOUT_R
AC97_BITCLK KB_RST#
EC_GA20
LPC_DRQ#1
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0 SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
PHDD_LED#
INTVRMEN H_DPRSTP#
H_FERR#
THRMTRIP#
H_THERMTRIP#
H_DPRSTP#
PHDD_LED#
H_CPUSLP#
H_FERR#FERR#
ICH_AC_BITCLK30,35
ICH_AC_RST#30,35
ICH_AC_SDIN030
CLK_PCIE_SATA#14 CLK_PCIE_SATA14
LPC_AD0 33,34
H_A20M# 4
H_PWRGOOD 4
H_INIT# 4
H_STPCLK# 4
H_INTR 4
H_IGNNE# 4
H_SMI# 4
H_NMI 4
EC_GA20 34
EC_KBRST# 34
LPC_FRAME# 33,34
LPC_AD1 33,34
LPC_AD2 33,34
LPC_AD3 33,34
IDE_DDREQ 22
IDE_DCS1# 22
IDE_DCS3# 22
IDE_DD[0..15] 22
IDE_DA[0..2] 22
IDE_DDACK#22
IDE_DIOR#22 IDE_DIOW#22
IDE_DIORDY22 IDE_IRQ22
ICH_AC_SYNC30,35
ICH_AC_SDOUT30,35
H_DPSLP# 4
ICH_AC_SDIN135
SATA_DTX_C_IRX_N021 SATA_DTX_C_IRX_P021
LPC_DRQ#1 33
SATA_ITX_C_DRX_N0 21
SATA_ITX_C_DRX_P0 21
PHDD_LED#34
H_DPRSTP# 4
H_THERMTRIP# 4,6
MAINPWON 43,44,46
H_CPUSLP# 4,6
H_FERR# 4
+RTCVCC
+RTCVCC
+3VS
+3VS
+3VS
+1.05VS
+1.05VS
+1.05VS
+3VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
18 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2492
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
close to RAM door
Place near ICH6 side.
C257 0.01U_0402_16V7K
12
R186 56_0402_5%
1 2
R176 56_0402_5%
1 2
R512
10K_0402_5%
12
J1 JOPEN
12
R215 33_0402_5%
12
C256 0.01U_0402_16V7K
12
R210 33_0402_5%
1 2
R181
330_0402_5%@
1 2
R190 10K_0402_5%
1 2
R573 56_0402_5%
1 2
R182 75_0402_1%
1 2
R439
20K_0402_5%
1 2
C269
12P_0402_50V8J
12
R206 33_0402_5%
12
R188
10K_0402_5%
1 2
C271
1U_0402_6.3V4Z
1 2
R201 4.7K_0402_5%
1 2
R187
56_0402_5%
12
C270
12P_0402_50V8J
12
Y3
32.768KHZ_12.5P_1TJS125DJ2A073
OUT 4
IN 1
NC
3
NC
2
C
B
E
Q22
2SC2411K_SC59@
1
2
3
R180 0_0402_5%
1 2
R203 8.2K_0402_5%
1 2
R209 24.9_0402_1%
1 2
R207
10_0402_5%@
12
R246
10M_0402_5%
12
C224
10P_0402_50V8J@
1 2
R244
1M_0402_1%
12
RTC
LAN SATAAC-97/AZALIA
LPC
CPU
PIDE
U17A
ICH6_BGA609
RTCX1
Y1
RTCX2
Y2
RTCRST#
AA2
INTRUDER#
AA3
INTVRMEN
AA5
EE_CS
D12
EE_SHCLK
B12
EE_DOUT
D11
EE_DIN
F13
LAN_CLK
F12
LAN_RSTSYNC
B11
LANRXD[0]
E12
LANRXD[1]
E11
LANRXD[2]
C13
LANTXD[0]
C12
LANTXD[1]
C11
LANTXD[2]
E13
ACZ_BIT_CLK
C10
ACZ_SYNC
B9
ACZ_RST#
A10
ACZ_SDIN[0]
F11
ACZ_SDIN[1]
F10
ACZ_SDIN[2]
B10
ACZ_SDO
C9
SATALED#
AC19
SATA[0]RXN
AE3
SATA[0]RXP
AD3
SATA[0]TXN
AG2
SATA[0]TXP
AF2
SATA[2]RXN
AD7
SATA[2]RXP
AC7
SATA[2]TXN
AF6
SATA[2]TXP
AG6
SATA_CLKN
AC2
SATA_CLKP
AC1
SATARBIAS#
AG11
SATARBIAS
AF11
IORDY
AF16
IDEIRQ
AB16
DDACK#
AB15
DIOW#
AC14
DIOR#
AE16
LAD[0]/FWH[0] P2
LAD[1]/FWH[1] N3
LAD[2]/FWH[2] N5
LAD[3]/FWH[3] N4
LDRQ[0]# N6
LDRQ[1]#/GPI[41] P4
LFRAME#/FWH[4] P3
A20GATE AF22
A20M# AF23
CPUSLP# AE27
DPRSLP#/TP[4] AE24
DPSLP#/TP[2] AD27
FERR# AF24
CPUPWRGD/GPO[49] AG25
IGNNE# AG26
INIT3_3V# AE22
INIT# AF27
INTR AG24
RCIN# AD23
NMI AF25
SMI# AG27
STPCLK# AE26
THRMTRIP# AE23
DA[0] AC16
DA[1] AB17
DA[2] AC17
DCS1# AD16
DCS3# AE17
DD[0] AD14
DD[1] AF15
DD[2] AF14
DD[3] AD12
DD[4] AE14
DD[5] AC11
DD[6] AD11
DD[7] AB11
DD[8] AE13
DD[9] AF13
DD[10] AB12
DD[11] AB13
DD[12] AC13
DD[13] AE15
DD[14] AG15
DD[15] AD13
DDREQ AB14
R520 0_0402_5%@
1 2
![](asset-13.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH_SMLINK1
PM_BATLOW#
ICH_PCIE_WAKE#
MCH_SYNC#
SERIRQ
USB_OC#7
DMI_MTX_IRX_N2
DMI_MTX_IRX_P0
RTC_CLK
CLK_48M_ICH
SYSRST#
ICH_SMLINK1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N1
ICH_SMLINK0
CK_SDATA
USB_OC#2
USB_OC#4
DMI_MTX_IRX_N3
DMI_ITX_MRX_P0
LINKALERT#
PM_CLKRUN#
CLK_14M_ICH
PBTN_OUT#
USB_OC#5
DMI_ITX_MRX_P3
SB_SPKR
DMI_ITX_MRX_N0
ICH_PCIE_WAKE#
CLK_PCIE_ICH#
DMI_MTX_IRX_P2
PM_STP_PCI#
CLK_PCIE_ICH
CK_SCLK
DMI_ITX_MRX_P2PM_STP_CPU#
MCH_SYNC#
DMI_MTX_IRX_N0
DMI_MTX_IRX_P3
EC_SWI#
USB_OC#1
DMI_ITX_MRX_N3
ACIN
SERIRQ
DMI_ITX_MRX_P1
EC_RSMRST#
EC_THERM#
SLP_S3#
PM_BATLOW#
CLK_48M_ICH
PM_CLKRUN#
ICH_SMLINK0
PCIE_ITX_PRX_P1 PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1
PCIE_ITX_PRX_N1
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
DMI_IRCOMP
USBRBIAS
ICH_GPI7
ICH_GPI7
CLK_14M_ICH
SLP_S5#
USB20_N0
USB20_P0
USB20_N2
USB20_P2
USB20_N4
USB20_P4
USB20_N5
USB20_P5
EC_FLASH#
EC_SMI#
USB20_N7
USB20_P7
USB_OC#0
PLT_RST#
SYS_PWROK
IDE_MPWR
SLP_S4#
EC_SWI#
ICH_VGATE
LINKALERT#
CK_SCLK
CK_SDATA
ICH_VGATE
SLP_S5#
SLP_S4#
EC_RSMRST#
SYS_PWROK
GPI26
GPI27
GPI28
GPI29
PM_DPRSLPVR
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
PLTRST_VGA#
IDE_HRESET#
IDE_MRESET#
SYSRST#
USB_OC#3
USB_OC#5
USB_OC#7
USB_OC#6
USB_OC#4
USB_OC#3
USB_OC#1
USB_OC#2
USB_OC#0
GPI26
GPI29
GPI27
GPI28
USB20_N6
USB20_P6
PM_BMBUSY#
EC_LID_OUT#
EC_SCI#
EC_LID_OUT#
USB_OC#6
PM_DPRSLPVR
DMI_MTX_IRX_N0 6
DMI_MTX_IRX_P0 6
DMI_ITX_MRX_N0 6
DMI_ITX_MRX_P0 6
DMI_MTX_IRX_N1 6
DMI_MTX_IRX_P1 6
DMI_ITX_MRX_N1 6
DMI_ITX_MRX_P1 6
DMI_MTX_IRX_N2 6
DMI_MTX_IRX_P2 6
DMI_ITX_MRX_N2 6
DMI_ITX_MRX_P2 6
DMI_MTX_IRX_N3 6
DMI_MTX_IRX_P3 6
DMI_ITX_MRX_N3 6
DMI_ITX_MRX_P3 6
CLK_PCIE_ICH# 14
CLK_PCIE_ICH 14
USB20_N2 38
USB20_P2 38
USB20_N4 38
USB20_P4 38
PM_SLP_S3#34
PM_STP_PCI#14
PM_STP_CPU#14,49
ICH_PCIE_WAKE#27
CK_SCLK14 CK_SDATA14
PM_CLKRUN#29,33
CLK_ICH_48M14 CLK_ICH_14M14
EC_RSMRST#34
PBTN_OUT#34
SYS_PWROK40
VGATE6,14,49
EC_THERM#34
SERIRQ24,33,34
SB_SPKR30
USB20_N5 35
USB20_P5 35
PCIE_PTX_C_IRX_N1 27
PCIE_PTX_C_IRX_P1 27
PCIE_ITX_C_PRX_P1 27
PCIE_ITX_C_PRX_N1 27
ACIN34,38,43
USB20_N0 38
USB20_P0 38
EC_FLASH#36
USB_OC#0 38
USB_OC#2 38
EC_SMI#34
USB20_N7 38
USB20_P7 38
EC_SWI#34
PLT_RST#6,16,17,21,22,24,27,33,34
IDE_MPWR22
USB_OC#4 38
RTC_CLK34
PM_SLP_S5#34
PM_DPRSLPVR49
PLTRST_VGA#16
IDE_HRESET#21
IDE_MRESET#34
USB20_P6 39
USB20_N6 39
SB_INT_FLASH_SEL#36
PM_BMBUSY#6
SUS_STAT#36
EC_LID_OUT#34 EC_SCI#34
USB_OC#7 38
+3VALW
+1.5VS
+3VALW
+3VS
+3VALW
Title
Size Document Number R ev
Date: Sheet of
401317
B
19 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2492
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R218
10_0402_5%@
12
R195 10K_0402_5%
1 2
C197 0.1U_0402_16V4Z
1 2
R196 8.2K_0402_5%
1 2
U21
TC7SH08FU_SSOP5
1
2
3
4
5
RP83
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5
C559
10P_0402_50V8J@
1
2
R258 1K_0402_5%
1 2
R249 8.2K_0402_5%
1 2
C198 0.1U_0402_16V4Z
1 2
R465 2.2K_0402_5%
1 2
R257 10K_0402_5%
1 2
R198 10K_0402_5%
1 2
R197 10K_0402_5%
1 2
R255 10K_0402_5%@
1 2
R189 22.6_0402_1%
1 2
R261 10K_0402_5%
1 2
R262 10K_0402_5%
1 2
R259 10K_0402_5%
1 2
R597 100K_0402_5%
1 2
R260 10K_0402_5%
1 2
R194 0_0402_5%
12
R464 2.2K_0402_5%
1 2
R193 10K_0402_5%
1 2
PCI-EXPRESSDIRECT MEDIA INTERFACE
USB
CLOCK
GPIO
POWER MGT
U17C
ICH6_BGA609
RI#
T2
SATA[0]GP/GPI[26]
AF17
SATA[1]GP/GPI[29]
AE18
SATA[2]GP/GPI[30]
AF18
SATA[3]GP/GPI[31]
AG18
SMBCLK
Y4
SMBDATA
W5
LINKALERT#
Y5
SMLINK[0]
W4
SMLINK[1]
U6
MCH_SYNC#
AG21
SPKR
F8
SUS_STAT#/LPCPD#
W3
SYS_RESET#
U2
BM_BUSY#/GPI[6]
AD19
GPI[7]
AE19
GPI[8]
R1
STP_PCI#/GPO[18]
AC21
GPO[19]
AB21
STP_CPU#/GPO[20]
AD22
GPO[21]
AD20
GPO[23]
AD21
GPIO[24]
V3
GPIO[25]
P5
GPIO[27]
R3
GPIO[28]
T3
CLKRUN#/GPIO[32]
AF19
GPIO[33]
AF20
GPIO[34]
AC18
WAKE#
U5
SERIRQ
AB20
THRM#
AC20
CLK14
E10
CLK48
A27
SUSCLK
V6
SLP_S3#
T4
SLP_S4#
T5
SLP_S5#
T6
PWROK
AA1
DPRSLPVR/TP[1]
AE20
LAN_RST#
V5
BATLOW#/TP[0]
V2
PWRBTN#
U1
VRMPWRGD
AF21
RSMRST#
Y3
PERn[1] H25
PERp[1] H24
PETn[1] G27
PETp[1] G26
PERn[2] K25
PERp[2] K24
PETn[2] J27
PETp[2] J26
SMBALERT#/GPI[11]
W6
GPI[12]
M2
GPI[13]
R6
PERn[3] M25
PERp[3] M24
PETn[3] L27
PETp[3] L26
PERn[4] P24
PERp[4] P23
PETn[4] N27
PETp[4] N26
DMI[0]RXN T25
DMI[0]RXP T24
DMI[0]TXN R27
DMI[0]TXP R26
DMI[1]RXN V25
DMI[1]RXP V24
DMI[1]TXN U27
DMI[1]TXP U26
DMI[2]RXN Y25
DMI[2]RXP Y24
DMI[2]TXN W27
DMI[2]TXP W26
DMI[3]RXN AB24
DMI[3]RXP AB23
DMI[3]TXN AA27
DMI[3]TXP AA26
DMI_CLKN AD25
DMI_CLKP AC25
DMI_ZCOMP F24
DMI_IRCOMP F23
OC[4]#/GPI[9] C23
OC[5]#/GPI[10] D23
OC[6]#/GPI[14] C25
OC[7]#/GPI[15] C24
OC[0]# C27
OC[1]# B27
OC[2]# B26
OC[3]# C26
USBP[0]N C21
USBP[0]P D21
USBP[1]N A20
USBP[1]P B20
USBP[2]N D19
USBP[3]N A18
USBP[3]P B18
USBP[4]N E17
USBP[4]P D17
USBP[5]P A16
USBP[5]N B16
USBP[6]N C15
USBP[6]P D15
USBP[7]N A14
USBP[7]P B14
USBP[2]P C19
USBRBIAS# A22
USBRBIAS B22
RP85
100_1206_8P4R_5%
1 8
2 7
3 6
4 5
R470
10_0402_5%@
12
RP82
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R256 10K_0402_5%
1 2
C235
10P_0402_50V8J@
1
2
R248 10K_0402_5%
1 2
C275
0.1U_0402_16V4Z
1 2
R472 24.9_0402_1%
1 2
![](asset-14.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH6_VCCPLL
ICH_V5REF_SUS
ICH_V5REF_RUN
ICH_V5REF_SUS
ICH_V5REF_RUN
ICH6_VCCDMIPLL ICH6_VCCPLL
+3VS
+3VALW
+1.5VS
+5VALW
+5VS
+1.05VS
+3VALW
+1.5VS
+1.5VS
+3VS
+1.5VS
+1.5VS
+1.5VS
+3VALW
+1.5VS
+3VS
+3VALW
+RTCVCC
+3VS
+RTCVCC
+1.5VS
+1.5VS
+2.5VS
+3VS
+3VS
+3VS
+3VALW
+1.5VS
+1.5VALW
+5VCD
Title
Size Document Number R ev
Date: Sheet of
401317
B
20 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2492
Near PIN AG5
Near PIN AG9
Near PIN
E26, E27
Near PIN
AC27
Near PIN AG10
Near PIN F27(C155),
P27(C154), AB27(C157)
Near PIN A25
Near PIN A24
Near PIN AA19
Near PIN AG23
Near PIN AB18
Near PIN
A2-A6, D1-H1
Near PIN
AG13, AG16
Near PIN A17
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Change to 0 ohm
R191
10_0402_5%
1 2
C199
0.1U_0402_16V4Z
1 2
GROUND
U17D
ICH6_BGA609
VSS[86] F4
VSS[85] F22
VSS[84] F19
VSS[83] F17
VSS[81] E19
VSS[82] E25
VSS[80] E18
VSS[79] E15
VSS[78] E14
VSS[76] D22
VSS[75] D20
VSS[74] D18
VSS[73] D14
VSS[72] D13
VSS[71] D10
VSS[70] D1
VSS[69] C4
VSS[68] C22
VSS[67] C20
VSS[66] C18
VSS[65] C14
VSS[64] B25
VSS[63] B24
VSS[62] B23
VSS[61] B21
VSS[60] B19
VSS[59] B15
VSS[58] B13
VSS[57] AG7
VSS[56] AG3
VSS[55] AG22
VSS[54] AG20
VSS[53] AG17
VSS[52] AG14
VSS[51] AG12
VSS[50] AG1
VSS[49] AF7
VSS[48] AF3
VSS[47] AF26
VSS[46] AF12
VSS[45] AF10
VSS[44] AF1
VSS[43] AE7
VSS[42] AE6
VSS[41] AE25
VSS[40] AE21
VSS[39] AE2
VSS[38] AE12
VSS[37] AE11
VSS[36] AE10
VSS[35] AD6
VSS[34] AD24
VSS[33] AD2
VSS[32] AD18
VSS[31] AD15
VSS[29] AD1
VSS[30] AD10
VSS[28] AC6
VSS[27] AC3
VSS[26] AC26
VSS[25] AC24
VSS[24] AC23
VSS[23] AC22
VSS[22] AC12
VSS[21] AC10
VSS[20] AB9
VSS[19] AB7
VSS[18] AB2
VSS[17] AB19
VSS[16] AB10
VSS[15] AB1
VSS[14] AA4
VSS[13] AA16
VSS[12] AA13
VSS[11] AA11
VSS[10] A9
VSS[9] A7
VSS[8] A4
VSS[7] A26
VSS[6] A23
VSS[5] A21
VSS[4] A19
VSS[3] A15
VSS[2] A12
VSS[1] A1
VSS[172]
E27
VSS[171]
Y6
VSS[170]
Y27
VSS[169]
Y26
VSS[168]
Y23
VSS[167]
W7
VSS[166]
W25
VSS[165]
W24
VSS[164]
W23
VSS[163]
W1
VSS[162]
V4
VSS[161]
V27
VSS[160]
V26
VSS[159]
V23
VSS[158]
U25
VSS[157]
U24
VSS[156]
U23
VSS[155]
U15
VSS[154]
U13
VSS[153]
T7
VSS[152]
T27
VSS[151]
T26
VSS[150]
T23
VSS[149]
T16
VSS[148]
T15
VSS[147]
T14
VSS[146]
T13
VSS[145]
T12
VSS[144]
T1
VSS[143]
R4
VSS[142]
R25
VSS[141]
R24
VSS[140]
R23
VSS[139]
R17
VSS[138]
R16
VSS[137]
R15
VSS[136]
R14
VSS[135]
R13
VSS[134]
R12
VSS[133]
R11
VSS[132]
P22
VSS[131]
P16
VSS[130]
P15
VSS[129]
P14
VSS[128]
P13
VSS[127]
P12
VSS[126]
N7
VSS[125]
N17
VSS[124]
N16
VSS[123]
N15
VSS[122]
N14
VSS[121]
N13
VSS[120]
N12
VSS[119]
N11
VSS[118]
N1
VSS[117]
M4
VSS[116]
M27
VSS[115]
M26
VSS[114]
M23
VSS[113]
M16
VSS[112]
M15
VSS[111]
M14
VSS[110]
M13
VSS[109]
M12
VSS[108]
L25
VSS[107]
L24
VSS[106]
L23
VSS[105]
L15
VSS[104]
L13
VSS[103]
K7
VSS[102]
K27
VSS[101]
K26
VSS[100]
K23
VSS[99]
K1
VSS[98]
J4
VSS[97]
J25
VSS[96]
J24
VSS[95]
J23
VSS[94]
H27
VSS[93]
H26
VSS[92]
H23
VSS[91]
G9
VSS[90]
G7
VSS[89]
G21
VSS[88]
G12
VSS[77] D7
VSS[87]
G1
D10
RB751V_SOD323
21
C568
0.1U_0402_16V4Z
1
2
C278
0.1U_0402_16V4Z
1
2
R240
1K_0402_5%@
1 2
L15
CHB1608U301_0603
1 2
C203
0.1U_0402_16V4Z
1 2
C205
0.01U_0402_16V7K
1
2
C193
0.1U_0402_16V4Z
1
2
C566
0.01U_0402_16V7K
1 2
C229
0.1U_0402_16V4Z
1
2
C571
0.1U_0402_16V4Z
1
2
C221
0.1U_0402_16V4Z
1
2
C562
0.1U_0402_16V4Z
1 2
+
C242
220U_D2_4VM_R12
1
2
R179
0.5_0603_1%
1 2
D9
RB751V_SOD323
21
C194
0.1U_0402_16V4Z
1
2
C226
0.1U_0402_16V4Z
1
2
C200
0.1U_0402_16V4Z
1 2
R214
10_0402_5%
1 2
C233
0.1U_0402_16V4Z
1
2
C234
0.1U_0402_16V4Z
1
2
C240
0.1U_0402_16V4Z
1
2
C213
1U_0603_10V4Z
1
2
PCIE
COREIDE
PCIUSB
SATA
USB CORE
PCI/IDE RBP
U17E
ICH6_BGA609
VCC1_5[1]
AA22
VCC1_5[2]
AA23
VCC1_5[3]
AA24
VCC1_5[4]
AA25
VCC1_5[5]
AB25
VCC1_5[6]
AB26
VCC1_5[7]
AB27
VCC1_5[8]
F25
VCC1_5[9]
F26
VCC1_5[10]
F27
VCC1_5[11]
G22
VCC1_5[12]
G23
VCC1_5[13]
G24
VCC1_5[14]
G25
VCC1_5[15]
H21
VCC1_5[16]
H22
VCC1_5[17]
J21
VCC1_5[18]
J22
VCC1_5[19]
K21
VCC1_5[20]
K22
VCC1_5[21]
L21
VCC1_5[22]
L22
VCC1_5[23]
M21
VCC1_5[24]
M22
VCC1_5[25]
N21
VCC1_5[26]
N22
VCC1_5[27]
N23
VCC1_5[28]
N24
VCC1_5[29]
N25
VCC1_5[30]
P21
VCC1_5[31]
P25
VCC1_5[32]
P26
VCC1_5[33]
P27
VCC1_5[34]
R21
VCC1_5[35]
R22
VCC1_5[36]
T21
VCC1_5[37]
T22
VCC1_5[38]
U21
VCC1_5[39]
U22
VCC1_5[40]
V21
VCC1_5[41]
V22
VCC1_5[42]
W21
VCC1_5[43]
W22
VCC1_5[44]
Y21
VCC1_5[45]
Y22
VCC1_5[46]
AA6
VCC1_5[47]
AB4
VCC1_5[48]
AB5
VCC1_5[49]
AB6
VCC1_5[50]
AC4
VCC1_5[51]
AD4
VCC1_5[52]
AE4
VCC1_5[53]
AE5
VCC1_5[54]
AF5
VCC1_5[55]
AG5
VCC1_5[56]
AA7
VCC1_5[57]
AA8
VCC1_5[58]
AA9
VCC1_5[59]
AB8
VCC1_5[60]
AC8
VCC1_5[61]
AD8
VCC1_5[62]
AE8
VCC1_5[63]
AE9
VCC1_5[64]
AF9
VCC1_5[65]
AG9
VCCDMIPLL
AC27
VCC3_3[1]
E26
VCCSATAPLL
AE1
VCC3_3[22]
AG10
VCCLAN3_3/VCCSUS3_3[1]
A13
VCCLAN3_3/VCCSUS3_3[2]
F14
VCCLAN3_3/VCCSUS3_3[3]
G13
VCCLAN3_3/VCCSUS3_3[4]
G14
VCCSUS3_3[1]
A11
VCCSUS3_3[2]
U4
VCCSUS3_3[3]
V1
VCCSUS3_3[4]
V7
VCCSUS3_3[5]
W2
VCCSUS3_3[6]
Y7
VCCSUS3_3[7]
A17
VCCSUS3_3[8]
B17
VCCSUS3_3[9]
C17
VCCSUS3_3[10]
F18
VCCSUS3_3[11]
G17
VCCSUS3_3[12]
G18
VCC1_5[98] F9
VCC1_5[97] U17
VCC1_5[96] U16
VCC1_5[95] U14
VCC1_5[93] U11
VCC1_5[94] U12
VCC1_5[92] T17
VCC1_5[91] T11
VCC1_5[90] P17
VCC1_5[89] P11
VCC1_5[88] M17
VCC1_5[87] M11
VCC1_5[86] L17
VCC1_5[85] L16
VCC1_5[84] L14
VCC1_5[83] L12
VCC1_5[82] L11
VCC1_5[81] AA21
VCC1_5[80] AA20
VCC1_5[79] AA19
VCC3_3[21] AA10
VCC3_3[20] AG19
VCC3_3[19] AG16
VCC3_3[18] AG13
VCC3_3[17] AD17
VCC3_3[16] AC15
VCC3_3[15] AA17
VCC3_3[14] AA15
VCC3_3[13] AA14
VCC3_3[12] AA12
VCC3_3[11] P1
VCC3_3[10] M7
VCC3_3[9] L7
VCC3_3[8] L4
VCC3_3[7] J7
VCC3_3[6] H7
VCC3_3[5] H1
VCC3_3[4] E4
VCC3_3[3] B1
VCC3_3[2] A6
VCCSUS1_5[3] U7
VCCSUS1_5[2] R7
VCCSUS1_5[1] G19
VCC1_5[78] G20
VCC1_5[77] F20
VCC1_5[76] E24
VCC1_5[75] E23
VCC1_5[74] E22
VCC1_5[73] E21
VCC1_5[72] E20
VCC1_5[71] D27
VCC1_5[70] D26
VCC1_5[69] D25
VCC1_5[68] D24
VCC1_5[67] G8
VCC2_5[2] P7
VCC2_5[4] AB18
V5REF[2] AA18
V5REF[1] A8
V5REF_SUS F21
VCCUSBPLL A25
VCCSUS3_3[20] A24
VCCRTC AB3
VCCLAN1_5/VCCSUS1_5[2] G11
VCCLAN1_5/VCCSUS1_5[1] G10
V_CPU_IO[3] AG23
V_CPU_IO[2] AD26
V_CPU_IO[1] AB22
VCCSUS3_3[19] G16
VCCSUS3_3[18] G15
VCCSUS3_3[17] F16
VCCSUS3_3[16] F15
VCCSUS3_3[15] E16
VCCSUS3_3[14] D16
VCCSUS3_3[13] C16
C237
0.1U_0402_16V4Z
1
2
C565
0.1U_0402_16V4Z
1 2
C561
0.1U_0402_16V4Z
1
2
C204
0.1U_0402_16V4Z
1 2
C277
0.1U_0402_16V4Z
1
2
C266
0.1U_0402_16V4Z
1
2
C243
1U_0603_10V4Z
1
2
C230
0.1U_0402_16V4Z
1 2
C212
0.1U_0402_16V4Z
1
2
C201
0.1U_0402_16V4Z
1 2
C265
0.1U_0402_16V4Z
1
2
C210
0.1U_0402_16V4Z
1 2
C228
0.1U_0402_16V4Z
1 2
C232
0.1U_0402_16V4Z
1
2
C267
0.1U_0402_16V4Z
1 2
C569
0.1U_0402_16V4Z
1
2
C572
0.1U_0402_16V4Z
1
2
C573
0.1U_0402_16V4Z
1 2
C567
0.1U_0402_16V4Z
1 2
C570
0.1U_0402_16V4Z
1
2
C223
0.1U_0402_16V4Z
1
2
C574
0.1U_0402_16V4Z
1 2
C563
0.01U_0402_16V7K
1 2
C195
0.1U_0402_16V4Z
1
2
C564
0.1U_0402_16V4Z
1 2
C560
0.1U_0402_16V4Z
1
2
C202
0.1U_0402_16V4Z
1 2
![](asset-15.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PIDE_HRESET#
PIDE_HDD11
IDE_XTLOUTIDE_XTLIN
PIDE_HDD12
T1
IDE_XTLIN
T2
IDE_XTLOUT
T5
T6
T0
T3
ATAIOSEL
SATA_DTX_IRX_N0
SATA_DTX_IRX_P0
SATA_DTX_C_IRX_N0
SATA_RST#
PIDE_HDD13
PIDE_HDD14 CNFG1PIDE_HDD15
T2
PIDE_HDA0
PIDE_HDD0
PIDE_HIORDY
ATAIOSEL
T6
PIDE_HDA1
PIDE_HDA2
PIDE_HCS0#
PIDE_HCS1#
PIDE_HINTRQ
PIDE_HDMACK#
PIDE_HIORDY
PIDE_HDIOR#
PIDE_HDIOW#
PIDE_HDREQ
PIDE_R_HRESET#
PIDE_HIOCS16#
T0
PIDE_HDD1
T3
PIDE_HINTRQ
PIDE_HDD2
SATA_DTX_IRX_P0
PIDE_HDD3
SATA_DTX_IRX_N0
SATA_ITX_C_DRX_P0
PIDE_HDD4 SATA_ITX_C_DRX_N0
PIDE_HDD5
PIDE_HDD6
PIDE_HDD7
T1
PIDE_HIOCS16#
PIDE_HDD8
PIDE_HDD9
PIDE_HDD10
PIDE_HDREQ
SATA_DTX_C_IRX_P0
SATA_RST#
IDE_HRESET#
PLT_RST#
IDE_XTLIN
PIDE_HDD7
PIDE_HDD14
PIDE_HDMACK#
PIDE_HDD6
PIDE_HIORDY
PIDE_HINTRQ
PIDE_HDD2
PIDE_HDA1
PIDE_HCS0#
PIDE_HDA0
PIDE_HDD10
PIDE_HDIOW#
PIDE_HRESET# PIDE_HDD8
PIDE_HDD5 PIDE_HDD11
PIDE_HDD1
PIDE_HDD4
PIDE_HDD3
PIDE_HDREQ
PIDE_HDD0
PIDE_HDIOR#
PIDE_HDD9
PIDE_HCS1#
SEC_CSEL
PIDE_HDD12
PIDE_HDD13
PIDE_HDD15
PIDE_HDA2
PLT_RST#
SATA_ITX_C_DRX_P0 18
SATA_ITX_C_DRX_N0 18
SATA_DTX_C_IRX_N0 18
SATA_DTX_C_IRX_P0 18
IDE_HRESET#19
PLT_RST#6,16,17,19,22,24,27,33,34
EC_IDERST30,34
+1.8VS
+5VS +3VS+1.8VS
+3VS
+3VS +3VS
+3VS
+3VS
+3VS
+5VS+5VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
21 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
SATA Module
CNFG0CNFG2 CNFG1
25MHz reference clock T[4:3] = 01
Sets maximum transfer rate and UDMA mode
Device Mode 100MB/s
Device Mode 133MB/s
Device Mode 150MB/s
Host Mode 100MB/s
Host Mode 133MB/s
Host Mode 150MB/s
0 1 1 Reserved
1 1 1 Reserved
Place near connector side.
NOTE
000
001
010
100
110
110
INT PDINT PD
*
Pleace near HD CONN Pleace near U178
P-ATA HDD Conn.
Change to 0 ohm
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R503 470_0402_5%
1 2
C287
0.1U_0402_16V4Z
1
2
R499 4.7K_0402_5%
1 2
R234 1M_0402_5% 10K_0402_5%R344 @
1 2
R604 0_0402_5%
1 2
C250
0.1U_0402_16V4Z
1 2
R491 10K_0402_5%
12
Y2
25MHZ_12PF_1BG25000CK1B
1 2
R504 10K_0402_5%
1 2
C294
0.1U_0402_16V4Z
1
2
C643
0.1U_0402_16V4Z
SWDJ@
12
R237 10K_0402_5%
1 2
U43
TC7SH08FU_SSOP5
SWDJ@
B
1
A
2Y4
P5
G
3
X3
OSC 25MHZ SG645PCG@
VDD
4
CONT
1
OUT 3
VSS 2
R245 10K_0402_5%@
1 2
C591
0.1U_0402_16V4Z
1
2
C595
2.2U_0603_6.3V6K
1
2
R275
10K_0402_5%
12
L31 CHB1608U800_0603
1 2
C293
4.7U_0805_10V4Z
1
2
C590
1000P_0402_50V7K
1
2
C251 0.01U_0402_16V7K
12
C252 0.01U_0402_16V7K
12
C375
0.1U_0402_16V4Z
1
2
C357
0.1U_0402_16V4Z
1
2
JP18 MOLEX_54782-4411
12 34 56 78 910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940 4142 4344
47
47 48
48
R322 10K_0402_5%
1 2
R268 10K_0402_5%
1 2
R266 10K_0402_5%
1 2
C255
0.1U_0402_16V4Z
1
2
C363
1U_0603_10V4Z
1
2
C249
12P_0402_50V8J
1
2
C258
0.01U_0402_16V7K
1
2
C384
1000P_0402_50V7K
1
2
R492 5.6K_0402_5%
12
C607
0.1U_0402_16V4Z@
1
2
R250 10K_0402_5%
1 2
C597
4.7U_0805_10V4Z
1
2
R243 33_0402_5%
1 2
R500 10K_0402_5%
1 2
R236
0_0402_5%
12
R263 10K_0402_5%
1 2
R230
0_0603_5%
12
R252 10K_0402_5%@
1 2
R235 10K_0402_5%
1 2
C282
0.1U_0402_16V4Z
1
2
C259
12P_0402_50V8J
1
2
R232 12.1K_0603_1%
12
U20
TC7SH08FU_SSOP5
B
1
A
2Y4
P5
G
3
R513
0_0402_5%@
12
Parallel ATA
UART
SATA
Config & Debug
Power
U22
88SA8040_TQFP64
HDD0
62
HDD1
64
HDD3
5HDD2
2
HDD4
7
HDD5
11
HDD6
13
HDD7
15
HDD8
14
HDD9
12
HDD10
10
HDD11
6
HDD12
3
TXP 32
TXM 31
RXP 27
HDD14
63
RXM 28
HDD15
61
RST# 17
T0 33
T1 34
T2 35
T3 36
T4 37
T5 38
T6 39
T7 40
CNFG2 20
CNFG1 19
CNFG0 18
ATAIOSEL 21
XTLIN/OSC 22
XTLOUT 23
ISET 26
VDDIO_0 44
VDDIO_1 4
VDD_0 9
VDD_1 41
VDD_2 56
VAA1 24
VAA2 29
VSS2 30
GND_0 8
GND_1 42
GND_2 57
HDA0
50
HDA1
51
HDA2
49
HCS0#
48
HCS1#
47
HIOCS16#
52
HINTRQ
53
HDMACK#
54
HIORDY
55
HDIOR#
58
HDIOW#
59
HDMARQ
60
HRESET#
16
HPDIAG#
46
UAO
45
UAI
43
VSS1 25
HDD13
1
![](asset-16.png)
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
MOD_DISCHARGE
IDE_MPWR
MID2
MID1
MID0
IDE_DCS1#
SHDD_LED#
IDE_DCS3#
SW_PCI_RST
MOD_DISCHARGE
SW_IDE_DCS3#
SW_IDE_DCS1#
CDROM_R
CDROM_L
CD_AGND
MODULE_RST#
IDE_DD7
IDE_DD8
IDE_DD15
MID2
IDE_DIOR#
IDE_DDREQ
IDE_DD13
IDE_DD12
IDE_DD11
IDE_DD9
IDE_DD10
MID1
IDE_DD14
IDE_DDACK#
SW_IDE_DCS3#
IDE_DA2
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD1
IDE_DD0
IDE_DA0
IDE_DA1
SW_IDE_DCS1#
IDE_DIOW#
IDE_DIORDY
IDE_IRQ
MID0
SEC_CSEL
IDE_DD[0..15]
IDE_DA[0..2]
SW_PCI_RST
SW_PCI_RST
CD_PLAY32,34 IDE_MPWR 19
IDE_DCS1#18
IDE_DCS3#18 MID2 34
MID1 34
MID0 34
IDE_DIOW#18
IDE_DIORDY18
IDE_IRQ18
INT_CD_R30,32 INT_CD_L30,32
CD_AGND30 MODULE_RST#34
IDE_DDREQ18
IDE_DIOR#18
IDE_DDACK#18
SHDD_LED#34
IDE_DA[0..2]18
IDE_DD[0..15]18
PCI_RST#17,24,29,33,34
PLT_RST#6,16,17,19,21,24,27,33,34
+5VMOD
+5VALW
+5VMOD
+5VALW
+3VALW
+3VALW
+5VMOD
+5VMOD
+5VMOD
+5VMOD
+5VMOD
+5VMOD
+3VALW
+5VMOD
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
22 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
Placea caps. near ODD CONN.
Module Conn.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
U10B
SN74LVC125APWLE_TSSOP14
SWDJ@
I
5O6
OE# 4
R152 10K_0402_5%
12
C155
1U_0603_10V4Z
1
2
R596
470_0402_5%
12
22K
22K
Q47
DTC124EK_SOT23
2
13
JP31
TYCO_1827293-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
R443 100K_0402_5%
12
C166 1U_0805_25V4Z
12
R590 0_0402_5%
1 2
C170
0.1U_0402_16V4Z
SWDJ@
1 2
C160
10U_1206_16V4Z
1
2
R591 0_0402_5%
1 2
G
D
S
Q21
2N7002_SOT23
SWDJ@
2
13
R158
10K_0402_5%
SWDJ@
12
22K
22K
Q48
DTC124EK_SOT23
2
13
R165
10K_0402_5%
SWDJ@
12
R514 10K_0402_5%
12
R535 0_0402_5%@
1 2
C552
10U_1206_16V4Z
1
2
Q15
AOS 3401_SOT23
2
13
G
D
S
Q62
2N7002_SOT23
2
13
C551
1000P_0402_50V7K
1
2
R155 240K_0402_5%
1 2
G
D
S
Q60
2N7002_SOT23
SWDJ@
2
13
R534 0_0402_5%
SWDJ@
1 2
C554
0.1U_0402_16V4Z
1
2
R442 100K_0402_5%
12
R507 475_0402_1%@
12
R166
10K_0402_5%
SWDJ@
12
C158
10U_1206_16V4Z
1
2
C164
0.1U_0402_16V4Z
1
2
R446 100K_0402_5%
12
U10A
SN74LVC125APWLE_TSSOP14
SWDJ@
I
2O3
OE# 1
P14
G
7
![](asset-17.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S1_D10
S1_D0
S1_D8
S1_D1
S1_D9
S1_A0
S1_A4
S1_A1
S1_A3
S1_A5
S1_A6
S1_A2
S1_A7
S1_A25
S1_D4
S1_D3
S1_D12
S1_D5
S1_D11
S1_D6
S1_D15
S1_A10
S1_IORD#
S1_D13
S1_D7
S1_IOWR#
S1_A11
S1_A9
S1_OE#
S1_D[0..15]
S1_A[0..25]
S1_CE2#
S1_A12
S1_CE1#
S1_A8
S1_REG#
S1_WAIT#
S1_A14
S1_A15
S1_A22
S1_INPACK#
S1_A23
S1_A13
A16_CLKS1_A16
S1_A20
S1_WE#
S1_RST
S1_WP
S1_BVD1
S1_A21
S1_A19
S1_RDY#
S1_BVD2
S1_VS2
S1_VS1
S1_CD1#
S1_D2
S1_A18
S1_D14
S1_CD2#
S1_CD1# S1_CD2#
S1_A17
S1_A24
S2_D10
S2_A[0..25]
S2_D[0..15]
S2_D9
S2_D1
S2_D8
S2_D0
S2_A0
S2_A1
S2_A2
S2_A3
S2_A4
S2_A5
S2_A6
S2_A25
S2_A7
S2_A24
S2_A17
S2_IOWR#
S2_A9
S2_IORD#
S2_A11
S2_OE#
S2_CE2#
S2_A10
S2_D15
S2_D7
S2_D13
S2_D6
S2_D12
S2_D5
S2_D11
S2_D4
S2_D3
S2_REG#
S2_A12
S2_A8
S2_CE1#
S2_A13
S2_A23
S2_A22
S2_A15
S2_A20
S2_A21
S2_A19
S2_A14
S2_WAIT#
S2_INPACK#
S2_WE#
S2_BVD1
S2_WP S2_A16
S2_RDY#
S2_RST
S2_BVD2
S2_CD1#
S2_CD2#
S2_VS1
S2_VS2
S2_D14
S2_D2
S2_A18
S2_CD2#S2_CD1#
S1_D[0..15]26
S1_A[0..25]26
S1_IOWR#26
S1_OE#26
S1_IORD#26
S1_CE2#26
S1_CE1#26
S1_REG#26
S1_INPACK#26
S1_RST26
S1_WE#26
S1_WAIT#26
S1_WP26 S1_BVD126
S1_RDY#26
S1_BVD226
S1_CD1#26
S1_VS226 S1_VS126 S1_CD2#26
CLOCK 26
LATCH 26
DATA 26
S2_A[0..25]26
S2_D[0..15]26
S2_IOWR# 26
S2_IORD# 26
S2_OE# 26
S2_CE2# 26
S2_REG# 26
S2_CE1# 26
S2_WAIT# 26
S2_INPACK# 26
S2_WE# 26
S2_BVD1 26
S2_WP 26
S2_RDY# 26
S2_RST 26
S2_BVD2 26
S2_CD1# 26
S2_CD2# 26
S2_VS1 26
S2_VS2 26
+3VS+S1_VCC +S2_VCC
+3VS
+3VS
+S1_VCC
+3VS
+S2_VCC
Title
Size Document Number R ev
Date: Sheet of
401317
B
23 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2492
Closed to Pin E5Closed to Pin C15
Closed to Pin N13 Closed to Pin B17
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C303
0.1U_0402_16V4Z
1
2
C298
0.1U_0402_16V4Z
1
2
C307
10P_0402_50V8J
1
2
C279
10P_0402_50V8J
1
2
PCI 7421
U41A
PCI7421GHK_PBGA288
A_CRST#/A_RESET
A6
A_CAUDIO/A_BVD2(SPKR#)
A2
A_USB_EN#
E2
B_USB_EN#
E1
A_CAD31/A_D10
D1
A_CAD30/A_D9
C1
A_CAD29/A_D1
D3
A_CAD28/A_D8
C2
A_CAD27/A_D0
B1
A_CAD26/A_A0
B4
A_CAD25/A_A1
A4
A_CAD24/A_A2
E6
A_CAD23/A_A3
B5
A_CAD22/A_A4
C6
A_CAD21/A_A5
B6
A_CAD20/A_A6
G9
A_CAD19/A_A25
C7
A_CAD18/A_A7
B7
A_CAD17/A_A24
A7
A_CAD16/A_A17
A10
A_CAD15/A_IOWR#
E11
A_CAD14/A_A9
G11
A_CAD13/A_IORD#
C11
A_CAD12/A_A11
B11
A_CAD11/A_OE#
C12
A_CAD10/A_CE2#
B12
A_CAD9/A_A10
A12
A_CAD8/A_D15
E12
A_CAD7/A_D7
C13
A_CAD6/A_D13
F12
A_CAD5/A_D6
A13
A_CAD4/A_D12
C14
A_CAD3/A_D5
E13
A_CAD2/A_D11
A14
A_CAD1/A_D4
B14
A_CAD0/A_D3
E14
A_CC/BE3#/A_REG#
C5
A_CC/BE2#/A_A12
F9
A_CC/BE1#/A_A8
B10
A_CC/BE0#/A_CE1#
G12
A_CPAR/A_A13
G10
A_CFRAME#/A_A23
C8
A_CTRDY#/A_A22
A8
A_CIRDY#/A_A15
B8
A_CSTOP#/A_A20
A9
A_CDEVSEL#/A_A21
C9
A_CBLOCK#/A_A19
E10
A_CPERR#/A_A14
F10
A_CSERR#/A_WAIT#
B3
A_CREQ#/A_INPACK#
E7
A_CGNT#/A_WE#
B9
A_CSTSCHG/A_BVD1(STSCHG/RI)
B2
A_CCLKRUN#/A_WP(IOIS16)
C3
A_CCLK/A_A16
E9
A_CINT#/A_READY(IREQ)
C4
A_CCD1#/A_CD1#
C15
A_CCD2#/A_CD2#
E5
A_CVS1/A_VS1#
A3
A_CVS2/A_VS2#
E8
A_CRSVD/A_D14
B13
A_CRSVD/A_D2
D2
A_CRSVD/A_A18
C10
GND
G7
GND
G8
GND
G13
GND
H13
GND
J9
GND
J10
GND
J11
GND
K9
GND
K10
GND
K11
GND
L8
GND
L9
GND
L10
GND
L11
GND
L12
GND
M8
VCCA A5
VCCA A11
VCC H8
VCC H9
VCC H10
VCC H11
VCC H12
VCC J8
VCC M7
VCC J12
VCC M9
VCC M10
VCC M12
VCC K8
VCC K12
VCC N7
VCCB D19
VCCB K19
DATA N1
CLOCK L6
LATCH N2
B_CAD31/B_D10 B15
B_CAD30/B_D9 A16
B_CAD29/B_D1 B16
B_CAD28/B_D8 A17
B_CAD27/B_D0 C16
B_CAD26/B_A0 D17
B_CAD25/B_A1 C19
B_CAD24/B_A2 D18
B_CAD23/B_A3 E17
B_CAD22/B_A4 E19
B_CAD21/B_A5 G15
B_CAD20/B_A6 F18
B_CAD19/B_A25 H14
B_CAD18/B_A7 H15
B_CAD17/B_A24 G17
B_CAD16/B_A17 K17
B_CAD15/B_IOWR# L13
B_CAD14/B_A9 K18
B_CAD13/B_IORD# L15
B_CAD12/B_A11 L17
B_CAD11/B_OE# L18
B_CAD10/B_CE2# L19
B_CAD9/B_A10 M17
B_CAD8/B_D15 M14
B_CAD7/B_D7 M15
B_CAD6/B_D13 N19
B_CAD5/B_D6 N18
B_CAD4/B_D12 N15
B_CAD3/B_D5 M13
B_CAD2/B_D11 P18
B_CAD1/B_D4 P17
B_CAD0/B_D3 P19
B_CC/BE3#/B_REG# F15
B_CC/BE2#/B_A12 G18
B_CC/BE1#/B_A8 K14
B_CC/BE0#/B_CE1# M18
B_CPAR/B_A13 K13
B_CFRAME#/B_A23 G19
B_CTRDY#/B_A22 H17
B_CIRDY#/B_A15 J13
B_CSTOP#/B_A20 J17
B_CDEVSEL#/B_A21 H19
B_CBLOCK#/B_A19 J19
B_CPERR#/B_A14 J18
B_CSERR#/B_WAIT# B18
B_CREQ#/B_INPACK# E18
B_CGNT#/B_WE# J15
B_CSTSCHG/B_BVD1(STSCHG/RI) F14
B_CCLKRUN#/B_WP(IOIS16) A18
B_CCLK/B_A16 H18
B_CINT#/B_READY(IREQ) B19
B_CRST#/B_RESET F17
B_CAUDIO/B_BVD2(SPKR#) C17
B_CCD1#/B_CD1# N13
B_CCD2#/B_CD2# B17
B_CVS1/B_VS1# C18
B_CVS2/B_VS2# F19
B_CRSVD/B_D14 N17
B_CRSVD/B_D2 A15
B_CRSVD/B_A18 K15
C292
0.1U_0402_16V4Z
1
2
C305
2.2U_0603_6.3V6K
1
2
C254
1U_0603_10V4Z
1
2
R239 33_0402_5%
12
C285
0.1U_0402_16V4Z
1
2
R304 10K_0402_5%
12
C262
0.1U_0402_16V4Z
1
2
C297
0.1U_0402_16V4Z
1
2
R305 10K_0402_5%
12
C284
10P_0402_50V8J
1
2
C261
0.1U_0402_16V4Z
1
2
C281
10P_0402_50V8J
1
2
C309
0.1U_0402_16V4Z
1
2
R273 33_0402_5%
12
C306
0.1U_0402_16V4Z
1
2
C326
0.1U_0402_16V4Z
1
2
C581
0.1U_0402_16V4Z
1
2
C268
0.1U_0402_16V4Z
1
2
![](asset-18.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCI_AD1
PCI_AD4
PCI_AD2
PCI_AD6
PCI_AD7
PCI_AD0
PCI_AD3
PCI_AD5
PCI_AD9
PCI_AD12
PCI_AD10
PCI_AD11
PCI_AD8
PCI_AD13
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD14
PCI_AD18
PCI_AD20
PCI_AD19
PCI_AD22
PCI_AD21
PCI_AD26
PCI_AD31
PCI_AD24
PCI_AD23
PCI_AD25
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD[0..31]
PCI_AD20PCM_ID
5IN1_LED#
SERIRQ
PCM_SPK#
MC_PW R_CTRL_0
PCI_PIRQC#
PCI_PIRQD#
AVDD_7421
TPB0+
TPBIAS0
TPA0+
TPA0-
TPBIAS0
TPA0+
TPA0-
TPB0+
TPB0-
TPB0-
TPB1-
TPB1+
TPA1-
TPA1+
TPBIAS1 TPBIAS1
TPA1+
TPA1-
TPB1+
TPB1-
AVDD_7421
SM_PHYS_WP#
SMRB#
SMCLE
MSBS_SDCMD_SMWE2
SMCD#
SDCD#
MSCD#
MSDATA3_SDDAT3_SMD3
MSDATA2_SDDAT2_SMD2
MSDATA1_SDDAT1_SMD1
MSDATA0_SDDAT0_SMD0
SMD4
SMALE
SMD7
SMD6
SMD5
SDW P_SMCE#
PCM_SPK#
PCI_PIRQB#
PCI_PIRQA#
PCI_AD[0..31] 17,29
PCI_GNT#2 17
PCI_RST# 17,22,29,33,34
PCI_DEVSEL# 17,29
PCI_SERR# 17,29
PCI_REQ#2 17
PCI_PERR# 17,29
PCI_STOP# 17,29
PCI_PAR 17,29
5IN1_LED 25,38
SERIRQ 19,33,34
PCI_C/BE#1 17,29
PCI_C/BE#2 17,29
PCI_C/BE#0 17,29
PCI_C/BE#3 17,29
PCM_SPK# 30
MC_PW R_CTRL_025
PCI_PIRQC# 17
PCI_PIRQD# 17
PCI_FRAME# 17,29
PCI_IRDY# 17,29
PCI_TRDY# 17,29
CLK_SD_48M14
TPA1+39 TPA1-39 TPB1+39 TPB1-39
MSDATA1_SDDATA1_SMD125 MSDATA2_SDDAT2_SMD225
MSCD#25 SDCD#25
MSDATA0_SDDAT0_SMD025
MSDATA3_SDDAT3_SMD325
SMD625 SMD725 SDW P_SMCE#25
SMD525 SMD425 SMALE25
SMELWP#25
MSBS_SDCMD_SMWE225
SM_PHYS_WP#25
SMRE#25
SMRB#25 SMCLE25
SMCD#25
MSCLK_SDCLK25
PLT_RST# 6,16,17,19,21,22,27,33,34
CLK_PCI_PCM 14
PCI_PIRQA# 17
PCI_PIRQB# 17
+3VS
+3VS
+VDPLL_33
+3VS
+3VS +VDPLL_33 +3VS
+3VS
+3VS
+AVDD_7421
+AVDD_7421
Title
Size Document Number R ev
Date: Sheet of
401317
B
24 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2492
LED R MAY CHANGE TO 150OHM
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Change to 0 ohm
C288
0.1U_0402_16V4Z
1
2
R346
5.11K_0402_1%
1 2
JP20
AMP_440168-2
1
2
3
4
C280
220P_0402_50V7K
1
2
C286
0.1U_0402_16V4Z
1
2
C387 1U_0603_25V4Z
1 2
X2
24.576MHz_16P_3XG-24576-43E1
1 2
R303 33_0402_5%
12
C325 1U_0603_25V4Z
1 2
C589
10U_1206_16V4Z
1
2
R265
56.2_0402_1%
1 2
R562 0_0402_5%
12
C274 1U_0603_25V4Z
1 2
C362
220P_0402_50V7K
1
2
C587 18P_0402_50V8J
R254 4.7K_0402_5%
12
R302 220_0402_5%
1 2
R242 6.34K_0402_1%
1 2
L30 CHB1608U800_0603
1 2
R251
56.2_0402_1%
1 2
C273
1U_0603_10V4Z
1
2
C322
0.1U_0402_16V4Z
1
2
R299 10K_0402_5%
1 2
R277 10K_0402_5%
1 2
R312
220_0402_5%
1 2
R350
56.2_0402_1%
1 2
R253
56.2_0402_1%
1 2
R586 10K_0402_5%
1 2
C310
10U_0805_10V4Z
1
2
R311 4.7K_0402_5%
12
C299
0.1U_0402_16V4Z
1
2
R313 0_0402_5%@
1 2
R283 100_0402_5%
12
R347
56.2_0402_1%
1 2
R301 220_0402_5%
1 2
R247
56.2_0402_1%
1 2
C260 1U_0603_25V4Z
1 2
R563 0_0402_5%@
12
C302
0.1U_0402_16V4Z
1
2
C588 18P_0402_50V8J
R552 33_0402_5%
12
R581
0_0402_5%@
12
C291
0.1U_0402_16V4Z
1
2
R280 33_0402_5%
1 2
R238 4.7K_0402_5%
1 2
PCI7421
U41B
PCI7421GHK_PBGA288
SPKROUT L7
SUSPEND# R2
VSSPLL
P14
VSSPLL
T17
VDPLL_15 T18
VR_PORT M19
VR_PORT H1
VCCP W10
VCCP W3
VDPLL_33 V19
AGND
N12
AGND
U14
AGND
U16
AVDD R13
AVDD R14
AVDD V17
AD31 U2
AD30 V1
AD29 V2
AD28 U3
AD27 W2
AD26 V3
AD25 U4
AD24 V4
AD23 V5
AD22 U5
AD21 R6
AD20 P6
AD19 W6
AD18 V6
AD17 U6
AD16 R7
AD15 V9
AD14 U9
AD13 R9
AD12 N9
AD11 V10
AD10 U10
AD9 R10
AD8 N10
AD7 V11
AD6 U11
AD5 R11
AD4 W12
AD3 V12
AD2 U12
AD1 N11
AD0 W13
C/BE3# W4
C/BE2# W7
C/BE1# W9
C/BE0# W11
PAR P9
FRAME# V7
TRDY# R8
IRDY# U7
STOP# W8
DEVSEL# N8
IDSEL W5
PERR# V8
SERR# U8
REQ# U1
GNT# T2
MFUNC0 N3
MFUNC1 M5
MFUNC2 P1
MFUNC3 P2
MFUNC4 P3
MFUNC5 N5
MFUNC6 R1
PCICLK P5
PCIRST# R3
GRST# T1
RI_OUT#/PME# T3
CLK_48
M1
PHY_TEST_MA
R17
MC_PWR_CTRL_0
F1
MC_PWR_CTRL_1
F2
SD_CD#
E3
MS_CD#
F5
SM_CD#
F6
MS_CLK/SD_CLK/SM_EL_WP#
G5
MS_BS/SD_CMD/SM_WE#
F3
MS_DATA3/SD_DAT3/SM_D3
H5
MS_DATA2/SD_DAT2/SM_D2
G3
MS_DATA1/SD_DAT1/SM_D1
G2
MS_SDIO(DATA0)/SD_DAT0/SM_D0
G1
SD_CLK/SM_RE#/SC_GPIO1
J5
SD_CMD/SM_ALE/SC_GPIO2
J3
SD_DAT0/SM_D4/SC_GPIO6
H3
SD_DAT1/SM_D5/SC_GPIO5
J6
SD_DAT2/SM_D6/SC_GPIO4
J1
SD_DAT3/SM_D7/SC_GPIO3
J2
SD_WP/SM_CE#
H7
SM_CLE/SC_GPIO0
J7
SM_R/B
K1
SM_PHYS_WP#/SC_FCB
K2
SC_CD#
L2
SC_CLK
K5
SC_RST
K3
SC_VCC_5V
K7
SC_DATA
L1
SC_OC#
L3
SC_PWR_CTRL
L5
TEST0
P12
NC
W17
RSVD
T19
R0
U18
R1
U19
TPBIAS0
U15
TPA0P
V15
TPA0N
W15
TPB0P
V14
TPB0N
W14
TPBIAS1
U17
TPA1P
V18
TPA1N
W18
TPB1P
V16
TPB1N
W16
CPS
M11
CNA
P15
XO
R19
XI
R18
PC0(TEST1)
R12
PC1(TEST2)
U13
PC2(TEST3)
V13
SCL M3
SDA M2
VR_EN# H2
R355
56.2_0402_1%
1 2
C300
0.1U_0402_16V4Z
1
2
R300 10K_0402_5%@
1 2
C283
0.1U_0402_16V4Z
1
2
C295
0.1U_0402_16V4Z
1
2
R264
5.11K_0402_1%
1 2
R359
56.2_0402_1%
1 2
R276 1K_0402_5%
1 2
C290
0.1U_0402_16V4Z
1
2
![](asset-19.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SDCD#
MSCD#
SMCD#
MSDATA1_SDDAT1_SMD1
SMCLE
MSCLK_SDCLK
SMRB#
SMD4 MSDATA0_SDDAT0_SMD0
MSDATA2_SDDAT2_SMD2
MSDATA0_SDDAT0_SMD0
SMD7
SMD6
MSDATA0_SDDAT0_SMD0
SMALE
MSCLK_SDCLK
MSDATA2_SDDAT2_SMD2
MSDATA1_SDDAT1_SMD1
SMD5 SDW P_SMCE#
MSCD#
SM_PHYS_WP#
MSBS_SDCMD_SMWE2
MSDATA3_SDDAT3_SMD3
MSDATA3_SDDAT3_SMD3
MSDATA1_SDDAT1_SMD1
SMCD#
SDW P_SMCE#
MSDATA3_SDDAT3_SMD3
MSBS_SDCMD_SMWE2
SMELWP#
SMRE#
MSDATA2_SDDAT2_SMD2
SMCD#
MSBS_SDCMD_SMWE2
SMRB#
SDW P_SMCE#
SMELWP# SM_PHYS_WP#
SMCD#
SDCD#
MC_PW R_CTRL_024
5IN1_LED24,38
MSDATA1_SDDATA1_SMD124
SMELWP#24
MSDATA0_SDDAT0_SMD024
MSBS_SDCMD_SMWE224
SMD724
MSDATA3_SDDAT3_SMD324
MSCD# 24
SMRE#24
SMD624
SMCD#24
SMD524
MSDATA2_SDDAT2_SMD224
SDW P_SMCE#24
SM_PHYS_WP#24
SMRB#24
SMD424
SMALE24
SMCLE24
MSCLK_SDCLK 24
SDCD# 24
+VCC_5IN1
+3VS +3VS
+3VS
+3VS
+3VS
+VCC_5IN1
+VCC_5IN1
+VCC_5IN1
+VCC_5IN1
+VCC_5IN1
+VCC_5IN1
Title
Size Document Number R ev
Date: Sheet of
401317
B
25 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2492
SD/XD/MS/SM PWR SWITCH
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5 in 1 CardReader Conn.
TI Workaround need check
R602 0_0402_5%
12
C381
0.1U_0402_16V4Z
R627 0_0402_5%
12
R353
10K_0402_5%
1 2
C382
0.1U_0402_16V4Z
R286
10K_0402_5%
1 2
5 IN 1 CONN
JP29
TAITWUN_R007-L30-15-S
SM_WP-IN / XD_WP-IN
35
SM-D4 / XD-D4
21
MS-DATA3 18
MS-DATA0 15
SD-DAT2 12
SD-DAT0 7
SD-CMD 10
MS-DATA1 14
SM-D6 / XD-D6
23
SD-DAT3 11
SD-DAT1 6
SD-WP-SW 5
#SM-ALE / XD-ALE
37
SM-D0
34
SD_CLK 8
SM-D2 / XD-D2
32
SM_-VCC / XD_-VCC
29
MS-INS 17
MS-DATA2 16
MS-SCLK 19
SM-LVD
25
#SM_-RE / XD_-RE
27 MS-BS 13
SM-D5 / XD-D5
22
#SM_-CD
30
SM-D7 / XD-D7
24
SM-D1 / XD-D1
33
#SM_-CE / XD_-CE
28
#SM_R/-B / XD_R/-B
26
SM_D3 / XD_D3
31
SD-VCC 9
#SM_-WE / XD_-WE
36
MS-VCC 20
SM-COM-SW
2
SM-CLE / XD-CLE
38
GND 1
SD-VCC-SW 42
SD-COM-SW 41
XD-VCC 40
XD-CD 39
SM-VCC-SW
3
SD-CD-SW 4
SM-WP-SW
43
GND 44
R267 10K_0402_5%
12
R584 43K_0402_5%@
12
R585 0_0402_5%
12
R233 10K_0402_5%
12
G
D
S
Q30
2N7002_SOT23@
2
13
U33
TPS2041ADR_SO8
GND
1
IN
2
IN
3
EN#
4OC# 5
OUT 6
OUT 7
OUT 8
R588
0_0402_5%
12
C393
1U_0603_10V4Z
1
2
R200 10K_0402_5%
12
R589
4.7K_0402_5%
1 2
R603 0_0402_5%
12
R354
10K_0402_5%
1 2
C685
0.1U_0402_16V4Z @ C394
1U_0603_10V4Z
1
2
R582 0_0402_5%
12
R626 0_0402_5%@
12
C397
4.7U_0805_10V4Z
1
2
R583 2.2K_0402_5%
12
C398
4.7U_0805_10V4Z
1
2
![](asset-1a.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S1_A[0..25]
S1_D[0..15]
S2_D[0..15]
S2_A[0..25]
S2_D1
S2_OE#
S2_CE2#
S1_D8
S1_WAIT#
S1_VS2
S1_D15
S1_D6
S2_WP
S2_A2
S2_A4
S2_A7
S2_CE1#
S1_A3
S1_A21
S1_A14
S1_A18
S1_IOWR#
S2_INPACK#
S2_VS2
S2_D12
S1_A8
S2_D2
S2_A17
S1_A25
S1_D4
S2_D9
S2_IORD#
S2_A10
S1_D1
S1_A5
S2_BVD1
S2_REG#
S2_WAIT#
S2_A25
S2_D5
S1_CD2#
S1_A2
S1_A20
S1_A13
S1_CE2#
S1_CE1#
S1_D5
S2_A5
S2_VS1
S2_D14
S2_D11
S1_A15
S2_BVD2
S2_A15
S2_A19
S1_D10
S1_OE#
S2_WE#
S2_A11
S1_D9
S1_A1
S2_D0
S2_A1
S2_RST
S2_D13
S2_CD1#
S1_D2
S1_BVD1
S1_REG#
S1_INPACK#
S1_RST
S1_A16
S1_A17
S1_A10
S1_D14
S1_D12
S2_CD2#
S2_D7
S2_D4
S1_A23 S2_A23
S2_A16
S2_A14
S1_IORD#
S2_A13
S2_IOWR#
S1_WP
S1_BVD2
S1_CD1#
S2_D8
S2_A0
S2_A8
S2_D6
S1_D0
S1_A4
S1_A6
S1_A24
S1_A22
S1_VS1
S1_D7
S1_D13
S1_D11
S2_D10
S2_A24
S2_D15
S1_A12
S1_A19
S2_A3
S2_A6
S2_A12
S2_A22
S2_A20
S2_RDY#
S2_A18
S1_A0
S1_A7
S1_A9
S1_RDY# S2_A21
S2_D3
S1_WE#
S1_A11
S1_D3
S2_A9
CLOCK23 LATCH23
S1_D[0..15]23
S1_A[0..25]23
DATA23
SUSP#16,32,34,36,37,41,47,48
S2_D[0..15]23
S2_A[0..25]23
S2_CD2# 23
S2_WP 23
S2_VS2 23
S1_CD2#23 S1_WP23
S1_OE#23 S1_VS123
S1_CE2#23 S1_CE1#23 S2_CE1# 23
S1_RDY#23
S1_IORD#23
S1_INPACK#23 S2_INPACK# 23
S2_IOWR# 23
S2_CE2# 23
S1_VS223
S1_IOWR#23
S1_REG#23 S2_REG# 23
S2_WE# 23
S2_VS1 23
S1_WE#23
S1_BVD223
S2_BVD1 23
S1_RST23 S2_RST 23
S2_RDY# 23
S2_OE# 23
S2_BVD2 23
S1_CD1#23
S1_BVD123
S2_CD1# 23
S1_WAIT#23 S2_WAIT# 23
S2_IORD# 23
+S1_VCC
+S1_VPP
+5VS
+3VS
+3VS
+S1_VPP
+S2_VCC+S1_VCC
+S2_VPP
+S2_VCC
+S2_VPP
Title
Size Document Number R ev
Date: Sheet of
401317
B
26 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2492
40mil
20mil
Power Switch for PCMCIA
CardBus Socket
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FOX_1CA84122-TC-4F_150P
JP19
a1
A74
a35
A75
a2
A72
a36
A73
a3
A70
a37
A71
a4
A68
a38
A69
GND
A67
a5
A65
a39
A66
a6
A63
a40
A64
a7
A61
a41
A62
GND
A59 a8
A58
a42
A60
a9
A56
a43
A57
a10
A54
GND
A51
a44
A55
a11
A52
a45
A53
a12
A49
a46
A50
GND
A43
a13
A47
a47
A48
a14
A45
a48
A46
a15
A42
a49
A44
a16
A40
a50
A41
a51/a17
A39 none
A38 a52/a18
A37 a19
A36
GND
A33
a53
A35 a20
A34
a54
A32 a21
A31 a55
A30 a22
A29
GND
A25
a56
A28 a23
A27 a57
A26
a24
A24 a58
A23 a25
A22 a59
A21
GND
A17
a26
A20 a60
A19 a27
A18
a61
A16 a28
A15 a62
A14 a29
A13 a63
A12 a30
A11 a64
A10
a31
A8 a65
A7 a32
A6 a66
A5
GND
A9
a33
A4 a67
A3 a34
A2 a68
A1
b1 B74
b35 B75
b2 B72
b36 B73
b3 B70
b37 B71
b4 B68
b38 B69
GND B67
b5 B65
b39 B66
b6 B63
b40 B64
b7 B61
b41 B62
GND B59
b8 B58
b42 B60
b9 B56
b43 B57
b10 B54
GND B51
b44 B55
b11 B52
b45 B53
b12 B49
b46 B50
GND B43
b13 B47
b47 B48
b14 B45
b48 B46
b15 B42
b49 B44
b16 B40
b50 B41
none B38
b51/b17 B39
b52/b18 B37
b19 B36
GND B33
b53 B35
b20 B34
b54 B32
b21 B31
b55 B30
b22 B29
GND B25
b56 B28
b23 B27
b57 B26
b24 B24
b58 B23
b25 B22
b59 B21
GND B17
b26 B20
b60 B19
b27 B18
b61 B16
b28 B15
b62 B14
b29 B13
b63 B12
b30 B11
b64 B10
b31 B8
b65 B7
b32 B6
b66 B5
b33 B4
b67 B3
b34 B2
b68 B1
GND B9
GND
3
GND
4
GND
5
GND
6
C2470.01U_0402_16V7K
12
U39
TPS2224ADBR_HTSSOP24
5V 1
5V 2
DATA
3
CLOCK
4
LATCH
5
NC 6
12V 7
AVPP
8
AVCC
9
AVCC
10 GND 11
RESET#
12
5V 24
NC 23
NC 22
SHDN#
21
12V 20
BVPP
19
BVCC
18 BVCC
17
NC 16
OC#
15 3.3V 14
3.3V 13
C276
0.1U_0402_16V4Z
C264
0.1U_0402_16V4Z
R483 10K_0402_5%
12
C263
0.1U_0402_16V4Z
C58410U_1206_16V4Z
12
C272
0.1U_0402_16V4Z
C586 4.7U_0805_10V4Z
C580 4.7U_0805_10V4Z
C57910U_1206_16V4Z
12
C5831U_0402_6.3V4Z
12
C585 0.1U_0402_16V4Z
C2461U_0402_6.3V4Z
12
C244 0.1U_0402_16V4Z
C5820.01U_0402_16V7K
12
![](asset-1b.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LAN_ACTIVITY#
LED_10/100
LED_1000
LAN_CTRL12
LAN_CTRL25
PCIE_PTX_IRX_P1
PCIE_PTX_IRX_N1
PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
PCIE_ITX_C_PRX_P1
LAN_X2LAN_X1
VPD_DATA
VPD_CLK
VPD_CLK
VPD_DATA
LAN_MDI0-
+LAN_AVDD25
LAN_MDI1+
LAN_LINK#
LAN_MDI1-
LAN_CTRL12
+LAN_AVDD
LAN_MDI2-
LAN_X1
LAN_X2
LAN_MDI3+
LAN_MDI2+
VPD_CLK
+LAN_AVDDL
LAN_MDI3-
PLT_RST#
LAN_CTRL25
PCIE_ITX_C_PRX_N1
LAN_MDI0+
VPD_DATA
LAN_ACTIVITY# 38,39
LAN_LINK# 38,39
LAN_MIDI3+28 LAN_MIDI3-28
LAN_MIDI2+28 LAN_MIDI2-28
LAN_MIDI1+28 LAN_MIDI0-28
PCIE_PTX_C_IRX_P119 PCIE_PTX_C_IRX_N119 PCIE_ITX_C_PRX_P119
ICH_PCIE_WAKE#19
LAN_MIDI0+28
LAN_MIDI1-28
PCIE_ITX_C_PRX_N119
CLK_PCIE_LAN#14 CLK_PCIE_LAN14
PLT_RST#6,16,17,19,21,22,24,33,34
+LAN_AVDD25
+3VALW
+3VALW
+LAN_VDD12
+3VALW
+LAN_AVDD25
+3VALW
+LAN_VDD12
+LAN_AVDDL
+LAN_VDD12
+3VALW
+LAN_AVDDL
+3VALW
+3VALW
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
27 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
40mil
40mil
4.7K for 88E8053
2K for 88E8036 R73 --
R77
4.7K_0402_5%
12
U38
AT24C16N10SC-2.7_SO8
A0 1
A1 2
SDA
5SCL
6
VCC
8
A2 3
GND 4
WP
7
R71
4.7K_0402_5%
12
C497
0.1U_0402_16V4Z
1
2
C51
4.7U_0805_10V4Z
1
2
C503
0.1U_0402_16V4Z
1
2
C467 0.1U_0402_16V4Z
1 2
C479
0.1U_0402_16V4Z
1
2
L26 0_0402_5%
1 2
Q10
BCP69_SOT223
1
2
43
R437 4.7K_0402_5%
12
R76 10K_0402_5%
12
C468
0.1U_0402_16V4Z
1
2
C504
0.1U_0402_16V4Z
1
2
C500
0.1U_0402_16V4Z
1
2
C477
0.1U_0402_16V4Z
1
2
R73 4.7K_0402_1%
12
C464
0.1U_0402_16V4Z
1
2
C502
0.1U_0402_16V4Z
1
2
C43
4.7U_0805_10V4Z
1
2
R438 4.7K_0402_5%
12
C476
27P_0402_50V8J
1
2
C501
0.1U_0402_16V4Z
1
2
C507 0.1U_0402_16V4Z
1 2
R74 10K_0402_5%
12
C493
0.1U_0402_16V4Z
1
2
C473
27P_0402_50V8J
1
2
C491
0.1U_0402_16V4Z
1
2
C508 0.1U_0402_16V4Z
1 2
R436
100K_0402_5%
12
C465
0.1U_0402_16V4Z
1
2
Q11
BCP69_SOT223
1
2
43
R425 10K_0402_5%
12
C499
0.1U_0402_16V4Z
1
2
C521 0.1U_0402_16V4Z
1 2
C466
0.1U_0402_16V4Z
1
2
C492
0.1U_0402_16V4Z
1
2
PCI-E LED
CLOCK
FLASH
MEMORY
EEPROM
TEST
Media
Analog
POWER
&
GROUND
U36
88E8053_QFN64
TX_P
49
TX_N
50
RX_P
54
RX_N
53
WAKEn
6
REFCLKP
55
REFCLKN
56
PERSTn
5
MDIP0
17
MDIN0
18
MDIP1
20
MDIN1
21
MDIP2
26
MDIN2
27
MDIP3
30
MDIN3
31
VPD_CLK
38
VPD_DATA
41
SPI_DO
34
SPI_DI
35
SPI_CLK
37
SPI_CS
36
XTALI
15
XTALO
14
LOM_DISABLEn
10
VAUX_AVLBL
12
SWITCH_VCC
11
VMAIN_AVLBL
47
SWITCH_VAUX
9
HSDACP
24
HSDACN
25
RSET
16
CTRL25
4
CTRL12
3
LED_ACTn 59
LED_LINK10/100n 60
LED_LINK1000n 62
LED_LINKn 63
TESTMODE 46
TSTPT 29
VDD25 64
AVDDL 19
AVDDL 22
AVDDL 28
AVDDL 32
AVDDL 51
AVDDL 52
AVDDL 57
AVDD 23
VDDO_TTL 1
VDDO_TTL 8
VDDO_TTL 40
VDDO_TTL 45
VDDO_TTL 61
VDD 2
VDD 7
VDD 13
VDD 33
VDD 39
VDD 44
VDD 48
VDD 58
SMCLK/NC 42
SMDATA/NC 43
EPAD 65
Y4
25MHZ_20P_1BX25000CK1A
C480
0.1U_0402_16V4Z
1
2
C484
0.1U_0402_16V4Z
1
2
![](asset-1c.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RJ45_MDI3-
RJ45_MDI3+
RJ45_MDI0-
RJ45_MDI0+
RJ45_MDI2-
RJ45_MDI2+
RJ45_MDI1-
RJ45_MDI1+
LAN_MDI0+
RJ45_MDI3-
RJ45_MDI3+
RJ45_MDI2+
LAN_MDI3+
LAN_MDI0-
LAN_MDI3-
LAN_MDI2-
LAN_MDI2+
RJ45_MDI2-
LAN_MDI1-
LAN_MDI1+
RJ45_GND RJ45_GND 38,39
LAN_MIDI3+27
LAN_MIDI3-27
LAN_MIDI2+27
LAN_MIDI2-27
LAN_MIDI1+27
LAN_MIDI1-27
LAN_MIDI0+27
LAN_MIDI0-27
RJ45_MDI3- 38,39
RJ45_MDI3+ 38,39
RJ45_MDI2+ 38,39
RJ45_MDI2- 38,39
RJ45_MDI1+ 38,39
RJ45_MDI1- 38,39
RJ45_MDI0+ 38,39
RJ45_MDI0- 38,39
+LAN_AVDD25
Title
Size Document Number R ev
Date: Sheet of
401317
B
28 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2492
reseved for 88E8036(10/100)
24ST0023-3(SP050004200) for 88E8036(10/100)
24HST1041A-3(SP050002110) for 88E8053(GbE)
unpop when use 88E8036(10/100)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R391 0_0402_5%@
1 2
R67
49.9_0402_1%
12
R65
49.9_0402_1%
12
R61
49.9_0402_1%
12
1:1
1:1
1:1
1:1
T1
24HST1041A-3_24P
TCT1
1
TD1+
2
TD1-
3
TCT2
4
TD21+
5
TD2-
6
TCT3
7
TD3+
8
TD3-
9
TCT4
10
TD4+
11
TD4-
12 MX4- 13
MX3- 16
MCT3 18
MX2- 19
MX2+ 20
MCT2 21
MX1- 22
MX1+ 23
MCT1 24
MX4+ 14
MCT4 15
MX3+ 17
C38
0.1U_0402_16V4Z
1
2
R66
49.9_0402_1%
12
R60
49.9_0402_1%
12
R389
75_0402_1%
12
R392
75_0402_1%
12
R394 0_0402_5%@
1 2
R59
49.9_0402_1%
12
R64
49.9_0402_1%
12
R395
75_0402_1%
12
R393 0_0402_5%@
1 2
R390 0_0402_5%@
1 2
R396
75_0402_1%
12
R58
49.9_0402_1%
12
C35
0.1U_0402_16V4Z
1
2
C36
0.1U_0402_16V4Z
1
2
C37
0.1U_0402_16V4Z
1
2
![](asset-1d.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCI_AD[0..31]
PCI_AD15
MINI_IDSEL
PCI_AD30
PCI_AD5
PCI_AD19
PCI_AD24
PCI_AD25
PCI_AD0
PCI_AD6
CLK_PCI_MINI
PCI_AD3
PCI_AD18
PCI_AD11
PCI_AD23
PCI_PIRQG#
PCI_AD18
PCI_AD12
PCI_AD27
PCI_AD4
PCI_PIRQH#
PCI_AD21
PCI_AD13
PCI_AD20
PCI_AD10
PCI_AD31
PCI_AD2
PCI_AD22
PCI_AD16
PCI_AD14
PCI_AD26
PCI_AD17
PCI_AD9
PCI_AD8
PCI_AD1
PCI_AD28
PCI_AD29
CLK_PCI_MINI
PCI_AD7
PCI_RST#
PCI_AD[0..31] 17,24
CLK_PCI_MINI14
PCI_C/BE#217,24
PCI_SERR#17,24
PCI_FRAME# 17,24
PCI_C/BE#317,24
PCI_PIRQH#17
PCI_DEVSEL# 17,24
PCI_PIRQG# 17
PCI_PERR#17,24
PM_CLKRUN#19,33 PCI_TRDY# 17,24
PCI_C/BE#0 17,24
PCI_IRDY#17,24
PCI_C/BE#117,24
PCI_PAR 17,24
WLANPME# 33,34
PCI_REQ#117
PCI_STOP# 17,24
KILL_SW#34,35,37
WL_OFF#34
PCI_GNT#1 17
PCI_RST# 17,22,24,33,34
+3V
+5VS_MINIPCI
+3V +3VS_MINIPCI
+3VS_MINIPCI
+3V
+3V
+5VS
+5VS_MINIPCI
+5VS_MINIPCI
+3VS_MINIPCI
+3V
+5VS_MINIPCI
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
29 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LAN RESERVED
LAN RESERVED
W=30mils
W=30mils W=20mils
W=40mils
W=40mils
W=40mils
W=30mils
0603
IDSEL : PCI_AD18
TIP
RING
MINI_PCI SOCKET
U9
TC7SH08FU_SSOP5
B
1
A
2Y4
P5
G
3
C177
0.1U_0402_16V4Z
1
2
C179 0.1U_0402_16V4Z
1 2
L14
0_0603_5%
1 2
L13
0_0603_5%
1 2
C182
0.1U_0402_16V4Z
1
2
C171
0.1U_0402_16V4Z
1
2
C183
0.1U_0402_16V4Z
1
2
JP28
QTC_C102A-040B31-4
1
122
3
344
5
566
7
788
9
910 10
11
11 12 12
13
13 14 14
15
15 16 16
17
17 18 18
19
19 20 20
21
21 22 22
23
23 24 24
25
25 26 26
27
27 28 28
29
29 30 30
31
31 32 32
33
33 34 34
35
35 36 36
37
37 38 38
39
39 40 40
41
41 42 42
43
43 44 44
45
45 46 46
47
47 48 48
49
49 50 50
51
51 52 52
53
53 54 54
55
55 56 56
57
57 58 58
59
59 60 60
61
61 62 62
63
63 64 64
65
65 66 66
67
67 68 68
69
69 70 70
71
71 72 72
73
73 74 74
75
75 76 76
77
77 78 78
79
79 80 80
81
81 82 82
83
83 84 84
85
85 86 86
87
87 88 88
89
89 90 90
91
91 92 92
93
93 94 94
95
95 96 96
97
97 98 98
99
99 100 100
101
101 102 102
103
103 104 104
105
105 106 106
107
107 108 108
109
109 110 110
111
111 112 112
113
113 114 114
115
115 116 116
117
117 118 118
119
119 120 120
121
121 122 122
123
123 124 124
L12 0_0603_5%
1 2
C175
10U_1206_16V4Z@
1
2
C178
1000P_0402_50V7K@
1
2
C181
0.1U_0402_16V4Z@
1
2
C174
10P_0402_50V8J@
1
2
C172
0.1U_0402_16V4Z
1
2
R162 100_0402_5%
1 2
R156
33_0402_5%@
12
C184
10U_1206_16V4Z
1
2
D6
RB751V_SOD323
21
C176
0.1U_0402_16V4Z
1
2
C173
0.1U_0402_16V4Z@
1
2
![](asset-1e.png)
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
CD_GNA
LINEL
LINER
MONO_IN
MONO_IN
CD_GNA
C_MIC
LINER
LINEL
+AC97_DVDD
SMB_DATA
SMB_CLK
SMB_CLK
SMB_DATA
LINE_IN_L31
LINE_IN_R31
BEEP#34
PCM_SPK#24
SB_SPKR19
ICH_AC_SDIN0 18
EAPD32,34
ICH_AC_SYNC18,35
ICH_AC_RST#18,35
ICH_AC_SDOUT18,35
MIC32
NBA_PLUG32,38
ICH_AC_BITCLK 18,35
EC_IDERST 21,34
CLK_14M_CODEC 14
INT_CD_L22,32
INT_CD_R22,32
HP_OUT_L 31
HP_OUT_R 31
AMP_LEFT 32
AMP_RIGHT 32
CD_AGND22
EC_SMB_CK24,34,39
EC_SMB_DA24,34,39
SYSON34,38,40,41,47
+VDDA
+5VALW
+VDDA
+3V
+3V
+3V
+AUD_VREF
+AVDD_AC97
+AVDD_AC97
+3VS
+3VS
+VDDA
+3V
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
30 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
GND GNDA
40mil
(output = 250 mA)
60mil
28.7K for Module Design (VDDA = 4.702)
4.85V
DGND AGND
AC97 Codec
With 14.318Mhz : R321 POP
With 24.576Mhz : R321 DEPOP
Change to 0 ohm
C603
1U_0402_6.3V4Z
12
R498
10K_0402_5%
12
C348
10U_0805_10V4Z
1
2
U27 ALC250-VD_LQFP48
AUX_L
14
AUX_R
15
JD1
17
JD2
16
LINE_IN_L
23
LINE_IN_R
24
CD_L
18
CD_R
20
CD_GND
19
MIC1
21
MIC2
22
PHONE
13
PC_BEEP
12
LINE_OUT_L 35
LINE_OUT_R 36
MONO_OUT/VREFOUT3 37
RESET#
11
SYNC
10
BIT_CLK 6
SDATA_OUT
5
SDATA_IN 8
XTL_IN 2
XTL_OUT 3
AFILT1 29
AFILT2 30
VREFOUT 28
VREF 27
DVDD1 1
DVDD2 9
AVDD1 25
AVDD2 38
DCVOL 32
XTLSEL
46
SPDIFI/EAPD
47
SPDIFO
48
DVSS1
4
DVSS2
7
NC 31
VREFOUT2 33
VAUX 34
DISABLE# 43
SCK 44
SDA
45
NC 40
AVSS1 26
AVSS2 42
HP_OUT_L 39
HP_OUT_R 41
G
D
S
Q58 2N7002_SOT23@
2
1 3
R309 6.8K_0402_5%
12
R501
10K_0402_5%
12
R287 22_0402_5%
1 2
C601
1U_0402_6.3V4Z
12
C368
1U_0402_6.3V4Z
1
2
L21
FBM-L10-160808-301-T_0603
1 2
L18 @FBM-L10-160808-301-T_0603
1 2
C318 0.1U_0402_16V4Z
1 2
R349 6.8K_0402_5%@
12
R540
4.7K_0402_5%@
12
C312
0.1U_0402_16V4Z
1
2
C612 1U_0603_10V4Z
1 2
R329 6.8K_0402_5%
12
R493
560_0402_5%
1 2
R495
560_0402_5%
1 2
R524 0_0603_5%@
1 2
C334 1U_0603_10V4Z
1 2
C366
0.1U_0402_16V4Z
1
2
R290 22_0402_5%
1 2
C359
1U_0402_6.3V4Z
1 2
R496
30K_0402_1%
1 2
C609 1U_0603_10V4Z
1 2
R324
6.8K_0402_5%
12
C604
1U_0402_6.3V4Z
1 2
C599
0.1U_0402_16V4Z
1
2
G
D
S
Q59 2N7002_SOT23@
2
1 3
R342 6.8K_0402_5%
12
C388 1000P_0402_50V7K
1 2
C373 1000P_0402_50V7K
1 2
R306 0_0603_5%
1 2
C640
1U_0402_6.3V4Z@
1
2
R315 20K_0402_5%
12
R288 22_0402_5%
1 2
R539
1K_0402_5%@
1 2
R521
1M_0402_5%@
1 2
U25A
SN74LVC14APWLE_TSSOP14
O2
I
1
P14
G
7
R336 6.8K_0402_5%@
12
C389 0.01U_0402_16V7K
1 2
C641 1U_0603_10V4Z
1 2
R523 0_0402_5%@
1 2
C339 1U_0402_6.3V4Z
1 2
R345 6.8K_0402_5%
12
D12
RB751V_SOD323
2 1
U24
SI9182DH-AD_MSOP8
VIN
4
SD
8
VOUT 5
GND 3
SENSE or ADJ 6
ERROR
7CNOISE 1
DELAY
2
R282
0_0402_5%
12
R538 0_0402_5%
1 2
C610
22P_0402_25V8K
1
2
C600
1U_0402_6.3V4Z
12
R321
0_0402_5%@
1 2
C313
10U_1206_16V4Z
1
2
C317
0.1U_0402_16V4Z
1
2
U25B
SN74LVC14APWLE_TSSOP14
O4
I
3
P14
G
7
C344 1U_0603_10V4Z
1 2
C332 1U_0402_6.3V4Z
1 2
R502
2.4K_0402_5%
1 2
R526 10K_0402_5%@
1 2
R291 0_0402_5%@
1 2
R497
10K_0402_1%
12
C639
1U_0402_6.3V4Z@
1
2
R307 0_0603_5%
1 2
R542 0_0402_5%
1 2
C611
22P_0402_25V8K
1
2
C602
1U_0402_6.3V4Z
12
C314
10U_1206_16V4Z
1
2
R494
560_0402_5%
1 2
R289 22_0402_5%
1 2
R279
10K_0402_5%
12
R323 20K_0402_5%
12
C349 1U_0603_10V4Z
1 2
R284 0_0603_5%
1 2
R536
1K_0402_5%@
1 2
X4
24.576MHz_16P_3XG-24576-43E1
1 2
C316
0.1U_0402_16V4Z
1
2
C296
0.1U_0402_16V4Z
1 2
U25C
SN74LVC14APWLE_TSSOP14
O6
I
5
P14
G
7
C
B
E
Q28
2SC2411K_SC59
1
2
3
C608 1U_0603_10V4Z
1 2
R522 22_0402_5%
1 2
C369
0.1U_0402_16V4Z
1
2
R328 20K_0402_5%
12
C367
0.1U_0402_16V4Z
1
2
R537
4.7K_0402_5%@
12
R525 0_0402_5%
1 2
C308
22U_1206_16V4Z_V1
1
2
L19 FBM-L10-160808-301-T_0603
1 2
C354
1U_0402_6.3V4Z
1 2
![](asset-1f.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+DOCK_AUD_VREF
LINEIL#39
LINEIL39
LINEIR#39
LINEIR39
HP_OUT_L30
HP_OUT_R30
LINEOL# 39
LINEOL 39
LINEOR 39
LINEOR# 39
LINE_IN_R 30
LINE_IN_L 30
+VDDA
+DOCK_AUD_VREF
+VDDA
+DOCK_AUD_VREF
+DOCK_AUD_VREF
+DOCK_AUD_VREF
+VDDA
+DOCK_AUD_VREF
+VDDA
+VDDA
+VDDA
+VDDA
+VDDA
+DOCK_AUD_VREF
+VDDA
+VDDA +DOCK_AUD_VREF
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
31 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
PROPRIETARY NOTE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R330 1K_0402_5%
1 2
U26B
LMV824MTX_TSSOP14
+
5O7
V+ 4
V-
11
-
6
R320 10K_0402_5%
1 2
R367 4.7K_0402_5%
12
R319 1K_0402_5%
1 2
R372 22K_0402_5%
1 2
U31B
LMV824MTX_TSSOP14
+
5O7
V+ 4
V-
11
-
6
U26C
LMV824MTX_TSSOP14
+
10 O8
V+ 4
V-
11
-
9
C400 1U_0402_6.3V4Z
1 2
U31C
LMV824MTX_TSSOP14
+
10 O8
V+ 4
V-
11
-
9
C337 1000P_0402_50V7K
1
2
C315
1U_0402_6.3V4Z
1 2
C360
0.1U_0402_16V4Z
1
2
R314 10K_0402_5%
1 2
U30A
LMV824MTX_TSSOP14
+
3
-
2
O1
V+ 4
V-
11
C355
1U_0402_6.3V4Z
1 2
U30B
LMV824MTX_TSSOP14
+
5O7
V+ 4
V-
11
-
6
C405 68P_0402_50V8K
1 2
R369
4.7K_0402_5%
1 2
R361
22K_0402_5%
1 2
C320 1U_0402_6.3V4Z
1 2
C343 1000P_0402_50V7K
1
2
C350 1U_0402_6.3V4Z
1 2
C331
0.1U_0402_16V4Z
1
2
R294
100K_0402_5%
1 2
U26A
LMV824MTX_TSSOP14
+
3
-
2
O1
V+ 4
V-
11
U30C
LMV824MTX_TSSOP14
+
10 O8
V+ 4
V-
11
-
9
C406
0.1U_0402_16V4Z
1
2
R360
4.7K_0402_5%
1 2
C321 1000P_0402_50V7K
1
2
R335 4.7K_0402_5%
1 2
R332 1K_0402_5%
1 2
C390 1U_0402_6.3V4Z
1 2
C386
0.1U_0402_16V4Z
1
2
C341
1U_0402_6.3V4Z
1
2
C379 1U_0402_6.3V4Z
1 2
R297 1K_0402_5%
1 2
C330 1000P_0402_50V7K
1
2
R357 4.7K_0402_5%
12
R333 10K_0402_5%
1 2
R358 22K_0402_5%
1 2
C345 1U_0402_6.3V4Z
1 2
R371
22K_0402_5%
1 2
C391 1U_0402_6.3V4Z
1 2
R292 10K_0402_5%
1 2
R326 4.7K_0402_5%
1 2
U31A
LMV824MTX_TSSOP14
+
3
-
2
O1
V+ 4
V-
11
R334 4.7K_0402_5%
1 2
C336 1U_0402_6.3V4Z
1 2
C378 68P_0402_50V8K
1 2
C392 1U_0402_6.3V4Z
1 2
R298 4.7K_0402_5%
1 2
C329 1U_0402_6.3V4Z
1 2
C358
0.1U_0402_16V4Z
1
2
R308
100K_0402_5%
1 2
C372 1U_0402_6.3V4Z
1 2
![](asset-20.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
NBA_PLUG
SPKR+
MIC
SPKL-
SHUTDOWN#
LINE_OUTR RIGHT_2
SPKL+
EAPD
VOL_AMP
LINE_OUTL
SPKR-
PATH_SEL_1
LEFT_2
SPKR+
BYPASS
NBA_PLUG
SUSP# CD_PLAY
PATH_SEL_1
SUSP#
HP_L
HP_R
SPKL+
SPKL+
SPKL-
SPKR+
SPKR-
MIC30
AMP_LEFT30
AMP_RIGHT30
EC_MUTE 34
EAPD 30,34
SUSP#16,26,34,36,37,41,47,48 CD_PLAY 22,34
INT_CD_L22,30
INT_CD_R22,30
NBA_PLUG30,38
VOL_AMP38
+5VCD
+AUD_VREF
+5VCD
+5VCD
+5VALW
+5VCD
+5VALW
+5VCD
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
B32 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MIC JACK
W=40mil Speaker Conn.
HeadPhone JACK
R566 0_0603_5%
1 2
C364 0.1U_0402_16V4Z
1 2
R352
4.7K_0402_5%
12
C365
0.1U_0402_16V4Z
1
2
C346
0.1U_0402_16V4Z
1
2
L23 FBM-11-160808-700T_0603
1 2
R337
100K_0402_5%@
1 2
C340
0.1U_0402_16V4Z
1
2
R567 0_0603_5%
1 2
R362 0_0402_5%
1 2
C353
0.047U_0402_16V7K
1
2
R343 10K_0402_5%
12
22K
22K
Q36
DTC124EK_SOT23
2
13
R568 0_0603_5%
1 2
+
C399 150U_4A_10VM
1 2
C351
1U_0402_6.3V4Z
1
2
C383 1U_0402_6.3V4Z
12
C370
330P_0402_50V7K
U29
TPA0232PWP_TSSOP24
HP/LINE#
2
VOLUME
3
LOUT+
4
ROUT+
21
LLINEIN
5
LHPIN
6
RHPIN
20
PVDD
7
PVDD
18
VDD
19
RLINEIN
23
GND 24
GND 13
GND 12
GND 1
RIN 8
LIN 10
ROUT- 16
LOUT- 9
BYPASS 11
PC-BEEP 14
SE/BTL# 15
CLK
17
SHUTDOWN# 22
R331 100K_0402_5%
1 2
C377
220P_0402_50V7K
1
2
R356 0_0402_5%
1 2
C371
10U_1206_16V4Z
1
2
R318
100K_0402_5%
12
C335 1U_0402_6.3V4Z@
1 2
C395
220P_0402_50V7K
1
2
+
C352 150U_4A_10VM
1 2
22K
22K
Q32
DTC124EK_SOT23
SWDJ@
2
13
C376
330P_0402_50V7K
C356
1U_0402_6.3V4Z
1
2
D37
PSOT24C_SOT23@
2
3
1
D36
PSOT24C_SOT23@
2
3
1
C333
0.1U_0402_16V4Z
1
2
Q39
AOS 3401_SOT23
2
13
G
D
S
Q31
2N7002_SOT23@
2
13
L24 FBM-11-160808-700T_0603
1 2
JP22
FOX_JA6033L-5S3-TR
1
2
3
4
5
6
C361
1U_0402_6.3V4Z
1
2
C342
0.1U_0402_16V4Z
1
2
R363 240K_0402_5%
1 2
C327 1U_0402_6.3V4Z
1 2
C347
4.7U_0805_10V4Z
1
2
L22 FBM-11-160808-700T_0603
1 2
R351
4.7K_0402_5%
12
R565 0_0603_5%
1 2
C328 1U_0402_6.3V4Z
1 2
G
D
S
Q33
2N7002_SOT23@
2
13
G
D
S
Q29
2N7002_SOT23
2
13
JP8
ACES_85204-0400
1
2
3
4
C338 1U_0402_6.3V4Z@
1 2
JP21
FOX_JA6033L-5S3-TR
1
2
3
4
5
6
MIC1
WM-64PCY_2P
1
2
R348 100K_0402_5%
1 2
![](asset-21.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CLK_PCI_SIOCLK_SIO_14M
SIO_PD#
LPD3 FD3
LPD2 FD2
FD1
FD0
LPD1
LPD0
FD7
FD6
LPD5
LPD7
LPD6 FD5
LPD4 FD4
FIR_DET#
LPC_AD[0..3]
IRRX
SIO_IRQ
IRRX
SIO_GPIO11
IRMODE
LPC_AD3
LPC_AD1
LPC_AD2
LPC_AD0
SIO_PME#
CLK_SIO_14M
LPC_FRAME#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
CTS#1
RTS#1
RI#1
TXD1
DCD#1
DTR#1
DSR#1
RXD1
SIO_PD#
SIO_IRQ
SIO_SMI#
SIO_GPIO11
CLK_PCI_SIO
SERIRQ
LPC_DRQ#1
PM_CLKRUN#
LPTBUSY
LPTSLCT
LPTACK#
LPTERR#
LPTPE
LPTSTB#
LPTAFD#
INIT#
SLCTIN#
IRTXOUT
AFD#/3M#
LPTERR#
FD1
FD0
LPTINIT#
FD3
FD6
LPTACK#
LPTPE
LPTBUSY
LPTSLCT
FD2 LPTSLCTIN#
FD7
FD5
FD4
R_LPTSTB#
SIO_SMI#
AFD#/3M#
LPTINIT#
LPTSLCTIN#
R_LPTSTB#
LPTAFD#
INIT#
SLCTIN#
LPTSTB#
BT_DET#
LPT_DET#
BT_DET#
SERIAL_DET#
FIR_DET#
LPT_DET#
SERIAL_DET#
LPT_DET#
LCD_ID
LCD_ID
LPTBUSY
LPTACK#
LPTPE
LPTSLCT
FD7
FD4
FD5
FD6
LPTBUSY_EMI
LPTACK#_EMI
LPTPE_EMI
LPTSLCT_EMI
FD7_EMI
FD4_EMI
FD5_EMI
FD6_EMI
LPTINIT#_EMI
AFD#/3M#_EMI
LPTSLCTIN#_EMI
LPTERR#_EMI
FD0_EMI
FD3_EMI
FD2_EMI
FD1_EMI
LPTINIT#
AFD#/3M#
LPTSLCTIN#
LPTERR#
FD0
FD3
FD2
FD1
LPTBUSY_EMI
LPTACK#_EMI
LPTPE_EMI
LPTSLCT_EMI
FD7_EMI
FD4_EMI
FD5_EMI
FD6_EMI
LPTINIT#_EMI
AFD#/3M#_EMI
LPTSLCTIN#_EMI
LPTERR#_EMI
FD0_EMI
FD3_EMI
FD2_EMI
FD1_EMI
CLK_14M_SIO14
CLK_PCI_SIO14 PM_CLKRUN#19,29
SERIRQ19,24,34
LPC_FRAME#18,34 LPC_DRQ#118
LPC_AD[0..3]18,34
PCI_RST#17,22,24,29,34
IRTXOUT 37
IRRX 37
IRMODE 37
FIR_DET#37
RXD1 37
TXD1 37
DSR#1 37
RTS#1 37
CTS#1 37
DTR#1 37
RI#1 37
DCD#1 37
FD039 LPTERR#39 FD139
FD239
FD339
FD439
FD539
FD639
FD739
LPTACK#39
LPTBUSY39
LPTPE39
LPTSLCT39
SIO_PME#29,34
AFD#/3M# 39
LPTINIT# 39
LPTSLCTIN# 39
R_LPTSTB# 39
BT_DET#17,35
SERIAL_DET#38
PLT_RST#6,16,17,19,21,22,24,27,34
LCD_ID16,17
+3V
+3VS
+3VS
+3VS
+5V_PRN
+5V_PRN
+5VS
+3VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
33 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SUPER I/O SMsC LPC47N217
Base I/O Address
0 = 02Eh
1 = 04Eh
*
Parallel Port
Close to Docking
L: R POP LPT Enable
H: R De-POP LPT Disable
LPT Module
LCD ID : High -- EDID
Low -- Panel ID
EMI Request for LPT ISSUE
R619 33_0402_5% LPT@
1 2
D24
RB420D_SOT23
2 1
R611 33_0402_5% LPT@
1 2
RP1
2.7K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R36 33_0402_5%
1 2
R621 33_0402_5% LPT@
1 2
POWER
CLOCK
GPIO
LPC I/F
SERIAL I/F
FIR
PARALLEL I/F
U18
LPC47N217_STQFP64
LAD0
10
LAD1
12
LAD2
13
LAD3
14
LFRAME#
15
LDRQ#
16
PCI_RESET#
17
LPCPD#
18
CLKRUN#
19
PCI_CLK
20
SER_IRQ
21
IO_PME#
6
RXD1 62
TXD1 63
DSR1# 64
RTS1# 1
CTS1# 2
DTR1# 3
RI1# 4
DCD1# 5
IRRX2 37
IRTX2 38
IRMODE/IRRX3 39
INIT# 41
SLCTIN# 42
PD0 44
PD1 46
PD2 47
PD3 48
PD4 49
PD5 50
PD6 51
PD7 53
SLCT 55
PE 56
BUSY 57
ACK# 58
ERROR# 59
ALF# 60
STROBE# 61
GPIO40
23
GPIO41
24
GPIO42
25
GPIO43
27
GPIO44
28
GPIO45
29
GPIO46
30
GPIO47
31
GPIO10
32
GPIO11/SYSOPT
33
GPIO12/IO_SMI#
34
GPIO13/IRQIN1
35
GPIO14/IRQIN2
36
GPIO23
40
CLK14
9
VTR 7
VCC 26
VCC 54
VSS
8
VSS
22
VSS
43
VSS
52 VCC 45
VCC 11
R617 33_0402_5% LPT@
1 2
C411
220P_0402_50V7K
1 2
C216
0.1U_0402_16V4Z
1
2
R35 33_0402_5%
1 2
R612 33_0402_5% LPT@
1 2
R224 10K_0402_5%
1 2
R545 0_0402_5%
1 2
RP5
2.7K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R544 100K_0402_5%
12
R622 33_0402_5% LPT@
1 2
R219
1K_0402_5%
1 2
R216
10K_0402_5%@
1 2
R613 33_0402_5% LPT@
1 2
R623 33_0402_5% LPT@
1 2
R620 33_0402_5% LPT@
1 2
R37
2.2K_0402_5%
12
L34
FBM-11-160808-121T_0603
1 2
RP93
2.7K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R43 33_0402_5%
1 2
R614 33_0402_5% LPT@
1 2
C239
15P_0402_50V8J@
1
2
C227
0.1U_0402_16V4Z
1
2
R222 100K_0402_5%
12
JP5
SUYIN_7313S-25G2T-AA
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
R624 33_0402_5% LPT@
1 2
RP3
68_1206_8P4R_5%
1 8
2 7
3 6
4 5
C222
0.1U_0402_16V4Z
1
2
R208 10K_0402_5%
12
R202
10K_0402_5%@
1 2
R546 0_0402_5%@
1 2
C236
0.1U_0402_16V4Z
1
2
R22 33_0402_5%
1 2
R223 100K_0402_5%
12
R615 33_0402_5% LPT@
1 2
R625 33_0402_5% LPT@
1 2
R543 100K_0402_5%
12
C220
4.7U_0805_10V4Z
1
2
RP2
68_1206_8P4R_5%
1 8
2 7
3 6
4 5
R551 1K_0402_5%
1 2
R616 33_0402_5% LPT@
1 2
R564 100K_0402_5%
12
R204 10K_0402_5%
1 2
R225
10_0402_5%@
1 2
R618 33_0402_5% LPT@
1 2
C225
15P_0402_50V8J@
1
2
RP4
2.7K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R211 10K_0402_5%
1 2
R610 33_0402_5% LPT@
1 2
![](asset-22.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FRD#
SELIO#
FSEL#
E51_RXD
MODE#
E51_TXD
LPC_AD0
ECAGND
KSI1
KSI6
KSI5
KSI7
KSO1
KSO0
KSO2
KSO4
KSO3
KSO5
KSO6
KSO7
KSO8
KSO12
KSO10
KSO13
KSO11
KSO9
KSO15
KSO14
TP_DATA
FSEL#
EC_LID_OUT#
PBTN_OUT#
FAN_SPEED1
ADB[0..7]
KBA[0..19]
CAPS_LED#
ECAGND
TEST_TP
TP_CLK
KBA5
KBA1
KBA4
ECAGND
KB_CLK
KB_DATA
PS_CLK
PS_DATA
KILL_SW#
BT_DETACH
E51_TXD
E51_RXD
TP_DATA RTC_CLK
CRY1
CRY2
ENBKL
KSI[0..7]
KSO[0..15]
EJCTSW#
EJCTSW#
ENBKL
DPCONF_S5P
TEST_TP
DPLL_TP
DPLL_TP
KSI2
HDD_LED#
WL_BT_LED#
KBA3
ADB5
FRD#
MID1
ADB7
ALI/MH#
ON/OFF
EC_SMB_DA2
EC_SMB_CK1
TP_CLK
LPC_AD1
PM_BATLOW#
ACOFF
PWR_LED#
EC_SCI# IREF
INVT_PWM
KBA12
ADB3
MODE#
KB_CLK
KBA13
AD_BID0
KSI0
BATT_LOW_LED#
KBA4
ADB6
FWR#
ENBKL
KBA14
ADB2
EC_MUTE
BEEP#
KBA9
KSO17
IDE_MRESET#
KBA17
EC_PME#
EC_THERM#
EC_SMI#
BKOFF#
DAC_BRIG
PS_DATA
LRST#
PM_SLP_S3#
KBA19
KBA0
FSTCHG
PWR_SUSP_LED
LID_SW#
BT_PWR
KBA7
LPC_AD3
EC_PME#
MID2
KBA16
ADB1
PS_CLK
KSI3
BT_WAKE_UP
KBA10
KBA5
BATT_TEMP
KBA18
KSI4
BATT_CHGI_LED#
KBA6
KBA2
SELIO#
EC_SMB_DA1
PM_SLP_S5#
EC_SMB_CK2
KBA1
LPC_AD2
AUD_SUDMUT_P3#
EN_DFAN1#
KBA11
KBA8
ADB0
BATT_AOVP
AD_BID0
BT_RST#
KB_DATA
ODD_LED#
CD_PLAY
EC_ON
ADB4
VR_ON
SYSON MID0
SUSP#
KBA15
DPCONF_S5P
DKN_B+_ON
NUM_LED#
PADS_LED#
SKU_ID_CHECK_0
SKU_ID_CHECK_0
CRY2CRY1
IE_BTN#
EC_SMB_DA1
EC_SMB_CK1
EC_SMB_DA2
EC_SMB_CK2
SHDD_LED#
LRST#
EC_IDERST
SKU_ID_CHECK_1
DOCKIN#
SKU_ID_CHECK_1
CD_PLAY
WLANPME#29,33
LAN_PME#29,33
SERIRQ19,24,33
LPC_FRAME#18,33
LPC_AD218,33
LPC_AD018,33
LPC_AD318,33
LPC_AD118,33
CLK_PCI_LPC14
EC_KBRST#18 EC_GA2018
TP_DATA35 TP_CLK35
EC_SWI#19 WL_OFF#29
S4_LATCH40
BKOFF#16
FSEL#36
BATT_TEMPA 44
EC_LID_OUT# 19
PHDD_LED#18
PBTN_OUT#19
EC_SMB_DA136,44 EC_SMB_CK136,44
EC_SMB_DA24,30,39 EC_SMB_CK24,30,39
FAN_SPEED1 37
KBA[0..19] 36
ADB[0..7] 36
FWR#36 FRD#36
EC_RSMRST# 19
EC_STOPBTN# 35,38
EC_SCI#19
S4_SATA40
MODULE_RST#22
LID_SW#38
KILL_SW# 29,35,37 ACIN 19,38,43
BT_DETACH35
BT_RST#35 BT_WAKE_UP35
RTC_CLK 19
GMCH_ENBKL8,16
KSO[0..15] 35
KSI[0..7] 35,38
ADP_I 45
MODE#38
CAPS_LED#35
SIO_PME#29,33
EJCTSW#39 1394_PHYRST_S3P 39
1394_DILSON_S3P 39
KB_DATA39
PS_DATA39
KB_CLK39
DAC_BRIG 16
BEEP# 30
SUSP#16,26,32,36,37,41,47,48
MID1 22
ALI/MH# 44
BATT_LOW_LED# 38
EN_DFAN1 37
EC_ON 40
FSTCHG45 AUD_SUDMUT_P3# 39
HDD_LED# 38
PS_CLK39
SYSON30,38,40,41,47
EC_PLAYBTN# 35,38
BT_PWR 35
IDE_MRESET# 19
PW R_LED# 38
ON/OFF 40
CD_PLAY 22,32
EC_SMI#19
PWR_SUSP_LED 38
WL_BT_LED# 38
KSO17 38
EC_REVBTN# 35,38
MID2 22
PM_SLP_S3# 19
INVT_PWM 16
ACOFF 45
MODE_LED# 38
EC_MUTE 32
EC_FRDBTN# 35,38
VR_ON49
MID0 22
BATT_AOVP 45
BATT_CHGI_LED# 38
IREF 45
EC_THERM# 19
PM_SLP_S5# 19
DPCONF_S5P 39
DKN_B+_ON45
NUM_LED#35
PADS_LED#35
IE_BTN#38
SHDD_LED# 22
PCI_RST#17,22,24,29,33
PLT_RST#
7
,19,21,22,24,27,33
EC_IDERST 21,30
EAPD 30,32
SKU_ID_CHECK_1 38
DOCKIN#15,39
+3VALW
+3VALW
+5VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+5VS
+3VALW
+RTCVCC
+5VS
+3VALW
+3VALW
+3VALW +3VALW
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
Compal Electronics, Inc.
34 51, 03,
星期一 一月
2005
For EC Tools
PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Analog Board ID definition,
Please see page 3.
Ra
Rb
Rc
Rd
SKU ID definition,
Please see page 3.
Re
Rf
SKU ID1 definition
Change to 0 ohm
In PWR Board
R1751K_0402_5%
12
X1
32.768KHZ_12.5P_1TJS125DJ2A073
OUT 4
IN 1
NC
3
NC
2
C217
1U_0603_10V4Z
1
2
RP81
4.7K_0804_8P4R_5%
1 8
2 7
3 6
4 5
C241
1000P_0402_50V7K
1
2
R480 47K_0402_5%
12
R473100K_0402_5%
12
R1714.7K_0402_5%
12
C209 0.01U_0402_16V7K
12
C238
0.1U_0402_16V4Z
1
2
R178 470_0402_5%
1 2
RP86
4.7K_0804_8P4R_5%
1 8
2 7
3 6
4 5
JP27
96212-1011S@
11
22
33
44
55
66
77
88
99
10 10
C185 0.22U_0402_10V4Z
1 2
R467 100K_0402_5%
12
L16
FBM-L11-160808-800LMT_0603
1 2
R547 0_0402_5%
1 2
R184
0_0402_5%
1 2
R1724.7K_0402_5%
12
C186
0.1U_0402_16V4Z
1
2
R168
33K_0402_5%
1 2
R549
100K_0402_5%
1 2
R229 1K_0402_5%
1 2
R587 0_0402_5%
1 2
C219
0.1U_0402_16V4Z
1
2
LPC Interface
X-BUS Interface
PS2 Interface
Internal Keyboard
SMBus
ENE-KB910-B4
Pulse Width
Wake Up Pin
Timer Pin
Analog To Digital
Digital To Analog
Expanded I/O
MISC
FAN
GPIO
*
*
**
*
*
*
*
*
*
*
*
*
*
U15
KB910Q B4_LQFP176
GPOK0/KSO0 49
GPOK1/KSO1 50
GPOK2/KSO2 51
GPOK3/KSO3 52
GPOK4/KSO4 53
GPOK5/KSO5 56
GPOK6/KSO6 57
GPOK7/KSO7 58
GPOK8/KSO8 59
GPOK9/KSO9 60
GPOK10/KSO10 61
GPOK11/KSO11 64
GPOK12/KSO12 65
GPOK13/KSO13 66
GPOK14/KSO14 67
GPOK15/KSO15 68
GPOK16/KSO16 153
GPOK17/KSO17 154
GPIK0/KSI0 71
GPIK1/KSI1 72
GPIK2/KSI2 73
GPIK3/KSI3 74
GPIK4/KSI4 77
GPIK5/KSI5 78
GPIK6/KSI6 79
GPIK7/KSI7 80
GPOW0/PWM0 32
GPOW1/PWM1 33
FAN2PWM/GPOW2/PWM2 36
GPOW3/PWM3 37
GPOW4/PWM4 38
GPOW5/PWM5 39
GPOW6/PWM6 40
FAN1PWM/GPOW7/PWM7 43
GPWU0 2
GPWU1 26
GPWU2 29
GPWU3 30
GPWU4 44
GPWU5 76
TIN1/GPWU6 172
TIN2/FANFB2/GPWU7 176
GPIAD0/AD0 81
GPIAD1/AD1 82
GPIAD2/AD2 83
GPIAD3/AD3 84
GPIAD4/AD4 87
GPIAD5/AD5 88
GPIAD6/AD6 89
GPIAD7/AD7 90
GPODA0/DA0 99
GPODA1/DA1 100
GPODA2/DA2 101
GPODA3/DA3 102
GPODA4/DA4 1
GPODA5/DA5 42
GPODA6/DA6 47
GPODA7/DA7 174
GPIO18/XIO8CS# 85
GPIO19/XIO9CS# 86
GPIO1A/XIOACS# 91
GPIO1B/XIOBCS# 92
GPIO1C/XIOCCS# 93
GPIO1D/XIODCS# 94
GPIO1E/XIOECS# 97
GPIO1F/XIOFCS# 98
GPIO2E/TOUT1/FANFB1 171
DPLL_TP/GPIO06/FANFB3 12
TEST_TP/GPIO05/FAN3PWM 11
TOUT2/GPIO2F 175
LAD0
15
LAD1
14
LAD2
13
LAD3
10
LFRAME#
9
LRST#/GPIO2C
165
LCLK
18
SERIRQ
7
CLKRUN#/GPIO0C
25
LPCPD#/GPIO0B
24
FnLock#/GPIO12
55
CapLock#/GPIO011
54
NumLock#/GPIO0A
23
ScrollLock#/GPIO0F
41
ECRST#
19
GA20/GPIO02
5
KBRST#/GPIO03
6
ECSCI#
31
GPIO04
8
GPIO07
20
GPIO08
21
GPIO09
22
GPIO0D
27
GPIO0E
28
GPIO10
48
GPIO13
62
GPIO14
63
GPIO15
69
GPIO16
70
GPIO17
75
GPIO24
109
GPIO25
118
GPIO26
119
GPIO27
148
GPIO28
149
GPIO29
155
GPIO2A
156
GPIO2B
162
GPIO2D
168
SCL1
163
SDA1
164
SCL2
169
SDA2
170
PSCLK1
110
PSDAT1
111
PSCLK2
114
PSDAT2
115
PSCLK3
116
PSDAT3
117
RD#
150
WR#
151
MEMCS#
173
IOCS#
152
D0
138
D1
139
D2
140
D3
141
D4
144
D5
145
D6
146
D7
147
A0
124
A1/XIOP_TP
125
A2
126
A3
127
A4/DMRP_TP
128
A5/EMWB_TP
131
A6
132
A7
133
A8
143
A9
142
A10
135
A11
134
A12
130
A13
129
A14
121
A15
120
A16
113
A17
112
A18
104
A19
103
A20/GPIO23
108
E51CS#/GPIO20/ISPEN
105
GND
17
GND
35
GND
46
GND
122
GND
137
GND
167
VCCBAT 161
BATGND 159
VCC 16
VCC 34
VCC 45
VCC 123
VCC 136
VCC 157
VCC 166
VCCA 95
AGND 96
E51IT0/GPIO00 3
E51IT1/GPIO01 4
E51RXD/GPIO21/ISPCLK 106
E51TXD/GPIO22/ISPDAT 107
XCLKI 158
XCLKO 160
D33
CH751H-40_SC76
2 1
R475
0_0402_5%
1 2
R478 0_0402_5%
1 2
R550
0_0402_5%@
1 2
R469
0_0402_5%@
1 2
C557
0.1U_0402_16V4Z
1
2
D38
PSOT24C_SOT23
2
31
C578 0.1U_0402_16V4Z
12
L29
FBM-L11-160808-800LMT_0603
1 2
R1741K_0402_5%
12
R169 100K_0402_5%
1 2
C575
10P_0402_50V8J
1
2
R183
100K_0402_5%
1 2
C218
0.1U_0402_16V4Z
1
2
C231
1000P_0402_50V7K
1
2
C207
0.1U_0402_16V4Z
1
2
RP84
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
C215
0.1U_0402_16V4Z
1
2
R476
20M_0603_5%@
1 2
R482 33_0402_5%@
12
R228 1K_0402_5%
1 2
R479
10K_0402_5%
1 2
R481 120K_0402_5%@
1 2
R548 0_0402_5%@
1 2
R1731K_0402_5%
12
C576
10P_0402_50V8J
1
2
C206
0.1U_0402_16V4Z
1
2
R474 0_0402_5%@
1 2
R170
100K_0402_5%
1 2
R199
0_0402_5%
1 2
C577
22P_0402_50V8J@
12
C688
0.1U_0402_16V4Z
1
2
R205
10K_0402_5%
1 2
![](asset-23.png)
+5VS_MDC
+3VS_MDC
KSO[0..15]
KSI6
KSO0
KSI[0..7]
KSO5
KSO7
KSO4
KSO6
KSO3
KSO2
KSO1
BT_RESET#
BT_WAKE_UP
USB20_P5
USB20_N5
BT_RESET#
Module_Detect
TP_CLK
SP_VCC
SP_GROND SP_Y
SP_X
TP_DATA
SP_Y
SP_GROND SP_X
SP_VCC
KSO4 KSO2
KSI2 KSI1
KSO1 KSO0
KSI0 KSI3
KSO5 KSO6
KSI5 KSI6
KSI4 KSO12
KSO7 KSO3
KSI7 KSO13
KSO9 KSO8
KSO11 KSO10
KSO14 KSO15
KSI4
KSI5
KSI7
KSI0
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSI1
KSI3
KSI2
KSO9
TP_CLK
TP_DATA TP_CLK
TP_DATA
KSO8
PADS_LED#
NUM_LED#
CAPS_LED#
ICH_AC_SDOUT18,30
ICH_AC_BITCLK 18,30
ICH_AC_SYNC 18,30
ICH_AC_SDIN1 18
ICH_AC_RST#18,30
KSO[0..15] 34
KSI[0..7] 34,38
BT_WAKE_UP34
BT_RST#34
BT_DETACH34
USB20_N519 USB20_P519
KILL_SW#29,34,37
BT_DET#17,33
BT_PWR34
TP_DATA 34
TP_CLK34
CAPS_LED# 34
PADS_LED#34 NUM_LED# 34
SUSP41,48
+5VS
+3VS
+3V
+3VS
+5VS_MDC+3V +3VS_MDC
+BT_VCC
+3VS
+BT_VCC
+3VS+5VS
+3VS
+3VS
+3VS
+5VS
+5VS_TP
+12VALW
+5VS
+5VS_TP
+5VS_TP
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
Compal Electronics, Inc.
35 51¬P , 03, 2005
期一 一月
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MDC CONN.
BlueTooth Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
INT_KBD CONN.
Module ID
Reset input High Active --> Low ,
Reset input Low Active --> Open
Indication for polarity of reset
Module ID
(MAX=200mA)
(Top Contact)
Bluetooth Connector
TP CONN.
Change to 0 ohm
Change to 0 ohm
PVT Reverse for FFC change
C629 100P_0402_25V8K
C636 100P_0402_25V8K
R605
100K_0402_5%
1 2
C623 100P_0402_25V8K
C671
0.1U_0402_16V4Z
JP30
ACES_88018-3010
MONO_OUT/PC_BEEP
1
GND
3
AUXA_RIGHT
5
AUXA_LEFT
7
CD_GND
9
CD_RIGHT
11
CD_LEFT
13
GND
15
+3.3Vaux/BT_VCC
17
GND
19
+3.3Vmain
21
AC97_SDATA_OUT
23
AC97_RESET#
25
GND
27
AC97_MSTRCLK
29
AUDIO_PWRDN/DETECH 2
MONO_PHONE 4
RESERVED/BT_ON# 6
GND 8
+5Vmain 10
RESERVED/USB+ 12
RESERVED/USB- 14
RESERVED/PRIMARY_DN 16
RESERVED/+5VD/WAKEUP 18
RESERVED/GND 20
AC97_SYNC 22
AC97_SDATA_IN1 24
AC97_SDATA_IN0 26
GND 28
AC97_BITCLK 30
C690
0.1U_0402_16V4Z
C633 100P_0402_25V8K
R140 300_0402_5%
12
R606
100K_0402_5%
1 2
L32 CHB1608B121_0603
1 2
C617 100P_0402_25V8K
C625 100P_0402_25V8K
22K
22K
Q13
DTC124EK_SOT23
2
13
C248
1U_0805_25V4Z
1
2
R241
0_0402_5%
1 2
C683 100P_0402_25V8K
C593
1U_0805_25V4Z
1
2
C624 100P_0402_25V8K
E
B
C
Q67
MMBT3904_SOT23
2
3 1
C618 100P_0402_25V8K
C682 100P_0402_25V8K
R487 0_0402_5%
1 2
R116
100K_0402_5%
1 2
C619 100P_0402_25V8K
C613 100P_0402_25V8K
C626 100P_0402_25V8K
JP14
ACES_88172-3400
35
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
36
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
37 38
E
B
C
Q68
MMBT3904_SOT23
2
3 1
G
D
S
Q63
2N7002_SOT23
2
13
R485 22_0402_5%
1 2
C142
0.1U_0402_16V4Z
C620 100P_0402_25V8K
C684 100P_0402_25V8K
JP13
ACES_87153-2008
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R560 300_0402_5%
12
C630 100P_0402_25V8K
R607
10_0402_5%
1 2
C614 100P_0402_25V8K
C151
0.1U_0402_16V4Z
C140
0.1U_0402_16V4Z
C253
1U_0805_25V4Z
1
2
C627 100P_0402_25V8K
C634 100P_0402_25V8K
L17 CHB1608B121_0603
1 2
R488 10K_0402_5%
1 2
JP15
ACES_87153-0801-01
1
3
5
7
2
4
6
8
C615 100P_0402_25V8K
R226 0_0402_5%
1 2
C245
0.1U_0402_16V4Z@
C631 100P_0402_25V8K
R608
0_0603_5%@
12
C628 100P_0402_25V8K
Q12
SI2301DS-T1_SOT23
2
1 3
C621 100P_0402_25V8K
C635 100P_0402_25V8K
C168 0.1U_0402_16V4Z
C616 100P_0402_25V8K
R559300_0402_5%
1 2
U19
TC7SH08FU_SSOP5@
B
1
A
2Y4
P5
G
3
C141
10U_1206_16V4Z
C622 100P_0402_25V8K
C632 100P_0402_25V8K
JP32
ACES_87153-0801-01
1
3
5
7
2
4
6
8
R486 22_0402_5%
1 2
![](asset-24.png)
FWE#
ADB[0..7]
KBA[0..19]
FRD#
INT_FSEL#
FWE#
KBA0
KBA3
KBA6
KBA2
KBA1
KBA9
KBA7
KBA5
KBA10
KBA4
KBA15
KBA14
KBA11
KBA13
KBA8
KBA12
KBA19
KBA18
KBA17
KBA16
RESET#
KBA1
KBA2
KBA3
KBA7
KBA4
KBA5
KBA11
KBA8
KBA10
KBA9
KBA14
KBA12
KBA15
KBA16 KBA17
KBA18
KBA19KBA13
KBA6
RESET#
FWE#
FRD#
FSEL#
ADB7
ADB6
ADB3
ADB5
ADB2
ADB0
ADB1
ADB4
ADB0
ADB3
ADB2
ADB1
ADB4
ADB7
ADB6
ADB5
KBA0
INT_FLASH_EN#
INT_FLASH_SEL
INT_FLASH_SEL
INT_FLASH_EN#
INT_FSEL#
FWR# 34
EC_SMB_CK134,44 EC_SMB_DA134,44
ADB[0..7]34
KBA[0..19]34
FRD#34
EC_FLASH# 19
SUSP# 16,26,32,34,37,41,47,48
SUS_STAT# 19
SB_INT_FLASH_SEL# 19
FSEL# 34
+3VALW
+3VALW
+5VALW +5VALW
+3VALW
+3VALW
+3VALW
+3VALW
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
Compal Electronics, Inc.
36 51¬P , 03, 2005
期一 一月
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1MB Flash ROM
1MB ROM Socket
U10C
SN74LVC125APWLE_TSSOP14@
I9
O
8
OE# 10
C188
0.1U_0402_16V4Z
1
2
R164
100K_0402_5%
12
R192
100K_0402_5%
12
U11
AT24C16N10SC-2.7_SO8
A0 1
A1 2
SDA
5SCL
6
VCC
8
A2 3
GND 4
WP
7
C644 0.1U_0402_16V4Z@
1 2
G
D
S
Q23
2N7002_SOT23
2
1 3
R167
100K_0402_5%
12
R529
10K_0402_5%
@
1 2
C187 0.1U_0402_16V4Z
1 2
R528 22_0402_5%@
1 2
C214
0.1U_0402_16V4Z
1 2
U14
TC7SH32FU_SSOP5
I0 2
I1 1
O
4
G
3P5
U10D
SN74LVC125APWLE_TSSOP14 @
I12
O
11
OE# 13
U16
SST39VF080-70_TSOP40
A0
21
A1
20
A2
19
A3
18
A4
17
A5
16
A6
15
A7
14
A8
8
A9
7
A10
36
A11
6
A12
5
A13
4
A14
3
A15
2
A16
1
A18
13
CE#
22
OE#
24
D0 25
D1 26
D2 27
D3 28
D4 32
D5 33
D6 34
D7 35
GND1 39
A17
40
WE#
9
VCC1 30
VCC0 31
GND0 23
A19
37
NC0 29
NC1 38
NC 11
RP# 10
READY/BUSY# 12
R527
100K_0402_5%@
1 2
R592 0_0402_5%
1 2
R212 100K_0402_5%
1 2
JP17
SUYIN_80065AR-040G2T@
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
![](asset-25.png)
EN_DFAN1
FAN1
EN_FAN1
FIR_DET#
IRTXOUT
IRRX IRMODE
+IR_3VS
DTR#
RTS#
TXD
CTS#
RI#
RXD
DCD#
DSR#
KILL_SW#
EN_DFAN134
FAN_SPEED134
IRTXOUT 33
IRMODE 33IRRX33
FIR_DET#33
RTS#133 TXD133
DTR#133
SUSP#16,26,32,34,36,41,47,48
CTS#133 RI#133 RXD133 DCD#133 DSR#133
CTS# 38,39
DTR# 38,39
RTS# 38,39
TXD 38,39
RI# 38,39
RXD 38,39
DCD# 38,39
DSR# 38,39
KILL_SW# 29,34,35
+12VALW +5VS
+3VS
+3VS
+3VS
+IR_ANODE
+3V
+3V
+3V
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
Compal Electronics, Inc.
37 51¬P , 03, 2005
期一 一月
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FAN Conn
L: R POP; FIR Enable
H: R De-POPFIR Disable
(30mil)
FIR Module
SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT
(60mil)
(60mil)
Close to Docking
Kill SWITCH
No Docking and Serial Port -----> Del
D3
1SS355_SOD323
12
D7
DAN217_SOT23
2
3
1
C523
0.1U_0402_16V4Z@
1
2
R365 4.7_1206_5%
1 2
C148
0.1U_0402_16V4Z
1
2
U7
MAX3243CAI_SSOP28
V- 3
VCC 26
FORCEOFF#
22
C1+
28
V+ 27
C1-
24
C2+
1
C2-
2
FORCEON
23
GND 25
TOUT1 9
TOUT2 10
TOUT3 11
RIN1 4
RIN2 5
RIN3 6
RIN4 7
RIN5 8
TIN1
14
TIN2
13
TIN3
12
ROUT1
19
ROUT2
18
ROUT3
17
ROUT4
16
ROUT5
15
ROUTB2
20
INVLD# 21
SW1 1BS003-1211L_3P
11
22
33
R440 8.2K_0402_5%
1 2
C396
10U_0805_10V4Z@
1
2
C106
1000P_0402_50V7K@
1
2
R160
100K_0402_5%
1 2
R88 10K_0402_5%
1 2
R368
0_1206_5%
1 2
C402
0.1U_0402_16V4Z
1
2
C522
0.1U_0402_16V4Z
1 2
C153
0.1U_0402_16V4Z
1
2
C154 0.1U_0402_16V4Z
12
R366 4.7_1206_5%@
1 2
IR1
HSDL-3603-007_9P
IRED_C
2
GND
8MODE 7
SD/MODE 5
IRED_A 1
RXD
4
VCC
6
TXD 3
GND 9
C107
1000P_0402_50V7K@
1
2
R435
10K_0402_5%
12
R220 1K_0402_5%
1 2
JP12
ACES_85205-0300
1
2
3
C108
10U_1206_16V4Z
12
C143
0.1U_0402_16V4Z
1
2
C
B
E
Q46
FMMT619_SOT23
1
2
3
C385
22U_1206_16V4Z_V1
1
2
D26
1N4148_SOT23
12
R441
100_0402_5%
1 2
C146 0.1U_0402_16V4Z
12
C401
10U_1206_16V4Z
1
2
U37A
LM358A_SO8
+IN
3
-IN
2OUT 1
P8
G
4
![](asset-26.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BATT_CHGI_LED# BATT_LOW_LED#
BATT_LOWLED#BATT_CHGILED#
RJ45_MDI3-
RJ45_GND
RJ45_MDI2+
RJ45_MDI3+
RJ45_MDI2-
RJ45_GND
RJ45_MDI1+
RJ45_MDI1-
RJ45_GND
RJ45_MDI0-
RJ45_MDI0+
LAN_LINK#
RJ45_GNDDTR#
RTS#
TXD
CTS#
RXD
RI#
DCD#
DSR#
LAN_ACTIVITY#
SYSON#
LID_SW#
LID
VOL_AMP
NBA_PLUG
PW R_LED_0#
BATT_LOWLED#
BATT_CHGILED#
51ON#
MODEBTN#
PW R_LED_1#
PWR_SUSPLED#
ON/OFFBTN# PW R_LED_1#
EC_STOPBTN#
EC_FRDBTN#EC_FRDBTN#
MODEBTN#
EC_PLAYBTN#
EC_REVBTN#
EC_STOPBTN#
IEBTN#
51ON#
IEBTN#
USB20_N7
USB20_P7
PWR_SUSPLED#
PW R_LED_0#
PW R_LED_1#
KSO17
ON/OFFBTN#
PWR_SUSPLED#
IEBTN#
MODEBTN#
EC_REVBTN#
EC_PLAYBTN#
SKU_ID_CHECK_1
PWR_SUSPLED_1#
PWR_SUSP_LED
SYSON
PWR_SUSPLED_1#
SYSON
PWR_LED#
SYSON#
MODE_LED# 34
HDD_LED# 34
WL_BT_LED# 34
BATT_CHGI_LED#34 BATT_LOW_LED# 34
CTS#37,39
DTR#37,39 RTS#37,39 TXD37,39
RI#37,39 RXD37,39 DCD#37,39 DSR#37,39
RJ45_GND 28,39
RJ45_MDI0- 28,39
RJ45_MDI0+ 28,39
RJ45_MDI1- 28,39
RJ45_MDI1+ 28,39
RJ45_MDI2- 28,39
RJ45_MDI2+ 28,39
RJ45_MDI3- 28,39
RJ45_MDI3+ 28,39
LAN_ACTIVITY# 27,39
USB_OC#019 USB_OC#219 USB_OC#419
SYSON#41
USB20_N0 19
USB20_P0 19
USB20_N2 19
USB20_P2 19
USB20_N4 19
USB20_P4 19
S4_LID_SW# 40
LID_SW# 34
NBA_PLUG30,32 VOL_AMP32
5IN1_LED24,25
ACIN19,34,43
MODE# 34
51ON# 40,43
ON/OFFBTN#40 KSO1734
EC_FRDBTN#34,35 EC_PLAYBTN#34,35
EC_REVBTN#34,35
EC_STOPBTN#34,35
IE_BTN# 34
USB20_N719 USB20_P719 LAN_LINK# 27,39
SERIAL_DET#33
SKU_ID_CHECK_134
PWR_SUSP_LED 34
PW R_LED# 34
SYSON 30,34,40,41,47
+5VS
+5VS
+3VALW
+5VS
+5VALW
+3VALW
+5VALW
+5VALW
+5VCD
+3VALW
+5VALW
+3VALW
+5VS
+3VALW
RTCVREF
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
Compal Electronics, Inc.
38 51¬P , 03, 2005
期一 一月
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WL LED
5IN1 LED
HDD LED
MODE LED
BATTERY CHGI/LOW LED
RJ45 / Serial Board Conn.
USB Board Conn.
Power / LED Board Conn.
POWER/ON LED
BATTERY CHG
AC IN LED
POWER/SUSP LED
D8
DAN202U_SC70
2
3
1
R374 120_0402_5%
1 2
C677 220P_0402_50V7K
1 2
10K
47K
Q52
DTA114YKA_SC59
2
1 3
C674 220P_0402_50V7K
1 2
G
D
S
Q55
2N7002_SOT23
2
13
D35
HT-191UD_AMBER_0603
2 1
JP16
ACES_87216-3002
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
23 23
24 24
25 25
26 26
27 27
28 28
29 29
30 30
D20
HT-191NB_BLUE_0603
2 1
D30
DAN202U_SC70
2
3
1
D15
HT-110UD_1204
12
R561 120_0402_5%
1 2
R531
100K_0402_5%
1 2
C679 220P_0402_50V7K
1 2
C676 220P_0402_50V7K
1 2
JP4
ACES_85203-1202
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
23 23
24 24
R533 300_0402_5%
1 2
R375 120_0402_5%
1 2
G
D
S
Q40
2N7002_SOT23
2
13
100K
100K
Q20
DTC115EKA_SOT23
2
13
C681 220P_0402_50V7K
1 2
10K
47K
Q57
DTA114YKA_SC59
2
1 3
C693
680P_0402_50V7K
1
2
C678 220P_0402_50V7K
1 2
JP3
ACES_87216-3002
11
22
33
44
55
66
77
88
99
10 10
11 11
12 12
13 13
14 14
15 15
16
16 17
17 18
18 19
19 20
20 21
21 22
22 23
23 24
24 25
25 26
26 27
27 28
28 29
29 30
30
R609 300_0402_5%
1 2
R532 300_0402_5%
1 2
R370 300_0402_5%
1 2
R471
200_0402_5%
12
R530 300_0402_5%
1 2
C680 220P_0402_50V7K
1 2
D31
DAN202U_SC70
2
3
1
C673 220P_0402_50V7K
1 2
R163
200_0402_5%
12
R185100K_0402_5%
1 2
C692
680P_0402_50V7K
1
2
D19
HT-191NB_BLUE_0603
2 1
G
D
S
Q65
2N7002_SOT23
2
1 3
D17
HT-191NB_BLUE_0603
2 1
G
D
S
Q66
2N7002_SOT23
2
1 3
D18
HT-191NB_BLUE_0603
2 1
100K
100K
Q51
DTC115EKA_SOT23
2
13
D34
HT-110UD_1204
12
R376 120_0402_5%
1 2
C675 220P_0402_50V7K
1 2
C672 220P_0402_50V7K
1 2
D16
HT-297UD/NB_BLUE/AMB_0603
2 1
3 4
R364 120_0402_5%
1 2
R293 120_0402_5%
1 2
![](asset-27.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
1394_PHYRST_S3P 1394_DILSON_S3P
TPA1+ TPA1-
TPB1+ TPB1-
D_EC_SMB_CK2 D_EC_SMB_DA2
CRT_CRTSC-P3P
CRT_CRED-PYP
CRT_CGREEN-PYP
CRT_CBLUE-PYP
CRT_CVSYNC-P5P
CRT_CRTSD-P3P
CRT_CHSYNC-P5P
RJ45_MDI3+
RJ45_MDI3- RJ45_MDI2-
RJ45_MDI2+
RJ45_MDI0+
RJ45_MDI0- RJ45_MDI1+
RJ45_MDI1-
RJ45_GND
LAN_ACTIVITY#
LAN_LINK#
LPTPE
FD7
FD6
FD4
FD1
FD2
FD0
R_LPTSTB#
LPTSLCT
LPTBUSY
LPTACK#
FD5
FD3
LPTSLCTIN#
LPTINIT#
LPTERR#
AFD#/3M#
LINEOR
LINEOR#
LINEOL#
LINEIL#
LINEIR
AUD_SUDMUT_P3#
EJCTSW#
TXD
DCOCT2#
LINEIR#
MDC1_RING
MDC2_TIP
LINEOL
LINEIL
DCOCT1#
RI#
DCD#
DSR# RTS#
DTR#
CTS#
RXD
DCOCT1#
DCOCT2#
DPCONF_S5P
D_EC_SMB_DA2
D_EC_SMB_CK2
1394_DILSON_S3P
PS_CLK PS_DATA
KB_CLK KB_DATA
DVI_SCLK DVI_SDATA
DVI_TXD2+
DVI_TXD2-
DVI_TXD1+
DVI_TXD1-
DVI_TXD0+
DVI_TXD0-
DVI_TXC+
DVI_TXC-
DVI_DET
DVI_TXD5+
DVI_TXD5-
DVI_TXD4+
DVI_TXD4-
DVI_TXD3+
DVI_TXD3-
MDC2_TIP
MDC1_RING
USBDP1-S3P
USBDP1-S3N
DOCKIN#
DOCK_ON/OFFBTN#
D_CRT_R15 D_CRT_G15 D_CRT_B15 D_CRT_HSYNC 15D_CRT_VSYNC15
D_DDC_CLK15 D_DDC_DATA 15
FD033 LPTINIT# 33
FD133 FD233
FD433
FD633 FD733 LPTPE33
FD3 33
LPTSLCTIN# 33
FD5 33
LPTACK# 33
LPTERR# 33
LPTBUSY 33
LPTSLCT 33
R_LPTSTB#33 AFD#/3M# 33
TXD37,38
LINEOL31 LINEOL# 31
LINEOR# 31
LINEOR 31
LINEIL31 LINEIR#31 LINEIL# 31
LINEIR 31
DOCK_ON/OFFBTN#40 RTS# 37,38
DTR# 37,38
RXD 37,38
CTS# 37,38
RI#37,38
DCD#37,38 DSR#37,38
DOCKIN# 15,34
TPA1+24
TPB1+24
TPA1- 24
TPB1- 24
EJCTSW# 34
1394_DILSON_S3P 34
1394_PHYRST_S3P34 DPCONF_S5P34
AUD_SUDMUT_P3#34
RJ45_MDI3+28,38 RJ45_MDI3-28,38 RJ45_MDI2- 28,38
RJ45_MDI2+ 28,38 RJ45_GND28,38 RJ45_MDI0+28,38 RJ45_MDI0-28,38 RJ45_MDI1+ 28,38
RJ45_MDI1- 28,38
LAN_ACTIVITY# 27,38
LAN_LINK# 27,38
EC_SMB_CK24,30,34
EC_SMB_DA24,30,34
PS_CLK34 PS_DATA 34
KB_CLK34 KB_DATA 34
DVI_TXD2+16 DVI_TXD2-16
DVI_TXD5+
DVI_TXD5-
DVI_TXD4+
DVI_TXD4-
DVI_TXD3+
DVI_TXD3-
DVI_TXD1+16 DVI_TXD1-16 DVI_TXD0+16 DVI_TXD0-16
DVI_TXC+16 DVI_TXC-16 DVI_DET16
DVI_SCLK16 DVI_SDATA 16
USB20_P6 19
USB20_N6 19
+5VS +5VS +5VS +5VS
+3VALW
DKN_B+ DKN_B+ DKN_B+ DNK_B+
+3VALW
+3VALW
+5VALW
+5VALW +3VALW
+5VALW
+5VALW
+DC_IN_S1 +DC_IN_S1
+3VALW
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
39 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MDC to Docking Conn.
Docking Conn.
Pin 73, 74 and 75 for VGA GND
R16 4.7K_0402_5%
1 2
C11 0.1U_0402_16V4Z
12
MODEM
JP23A
TYCO_1674036
GND
245
VCC
241
S1
1
S2
2
S3
3
S4
4
S5
5
S6
6
S7
7
S8
8
S9
9
S10
10
S11
11
S12
12
S13
13
S14
14
S15
15
S16
16
S17
17
S18
18
S19
19
S20
20
S21
21
S22
22
S23
23
S24
24
S25
25
S26
26
S27
27
S28
28
S29
29
S30
30
S31
31
S32
32
S33
33
S34
34
S35
35
S36
36
S37
37
S38
38
S39
39
S40
40
S41
41
S42
42
S43
43
S44
44
S45
45
S46
46
S47
47
S48
48
S49
49
S50
50
S51
51
S52
52
S55
55
S56
56
M59
59
M60
60
GND
253
GND 247
VCC 242
S61 61
S62 62
S63 63
S64 64
S65 65
S66 66
S67 67
S68 68
S69 69
S70 70
S71 71
S72 72
S73 73
S74 74
S75 75
S76 76
S77 77
S78 78
S79 79
S80 80
S81 81
S82 82
S83 83
S84 84
S85 85
S86 86
S87 87
S88 88
S89 89
S90 90
S91 91
S92 92
S93 93
S94 94
S95 95
S96 96
S97 97
S98 98
S99 99
S100 100
S101 101
S102 102
S103 103
S104 104
S105 105
S106 106
S107 107
S108 108
S109 109
S110 110
S111 111
S112 112
S115 115
S117 117
GND
246 GND 248
LAN
JP23B
TYCO_1674036
GND
249
VCC
243
S121
121
S122
122
S123
123
S124
124
S125
125
S126
126
S127
127
S128
128
S129
129
S130
130
S131
131
S132
132
S133
133
S134
134
S135
135
S136
136
S137
137
S138
138
S139
139
S140
140
S141
141
S142
142
S143
143
S144
144
S145
145
S146
146
S147
147
S148
148
S149
149
S150
150
S151
151
S152
152
S153
153
S154
154
S155
155
S156
156
S157
157
S158
158
S159
159
S160
160
S161
161
S162
162
S163
163
S164
164
S165
165
S166
166
S167
167
S168
168
S169
169
S170
170
S171
171
S172
172
S173
173
L178
178
L179
179
L180
180
GND 251
VCC 244
S181 181
S182 182
S183 183
S184 184
S185 185
S186 186
S187 187
S188 188
S189 189
S190 190
S191 191
S192 192
S193 193
S194 194
S195 195
S196 196
S197 197
S198 198
S199 199
S200 200
S201 201
S202 202
S203 203
S204 204
S205 205
S206 206
S207 207
S208 208
S209 209
S210 210
S211 211
S212 212
S213 213
S214 214
S215 215
S216 216
S217 217
S218 218
S219 219
S220 220
S221 221
S222 222
S223 223
S224 224
S225 225
S226 226
S227 227
S228 228
S229 229
S230 230
S231 231
S232 232
S233 233
S234 234
S235 235
S236 236
L239 239
L240 240
GND 254
S175
175
GND
250 GND 252
G
D
S
Q5
2N7002_SOT23
2
13
G
D
S
Q3
2N7002_SOT23
2
1 3
R13 10K_0402_5%
12
U2
TC7SH32FU_SSOP5
I0
2
I1
1O4
G
3P5
R574
100K_0402_5%D@
12
JP2
ACES_85205-0400
1
1
2
2
3
3
4
4
R15
100K_0402_5%
1 2
G
D
S
Q4
2N7002_SOT23
2
13
R14 4.7K_0402_5%
1 2
R17 10K_0402_5%
1 2
![](asset-28.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+RTCBATT
ON/OFFBTN#
D_SET_S4
51ON#
ON/OFFBTN#
EC_ON
SYS_PWROK 19 S4_SATA34
S4_LATCH34
SYSON30,34,38,41,47
S4_LID_SW#38
EC_ON34
ON/OFF 34
51ON# 38,43
ON/OFFBTN#38
DOCK_ON/OFFBTN#39
+3V +3V
+3VS
+RTCVCC
+CHGRTC
+RTCBATT
+3VALW
RTCVREF RTCVREF RTCVREF RTCVREF
RTCVREF
RTCVREF
RTCVREF
+3VALW
+3VALW
RTCVREF
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
40 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
RTC Battery
-+
+3V POWER +3V POWER
Power ON Circuit
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Power Button
TOP Side
Button Side
C323 0.1U_0402_16V4Z
1 2
U25D
SN74LVC14APWLE_TSSOP14
O8
I
9
P14
G
7
D29
DAN202U_SC70
2
3
1
U23
NC7SZ14M5X_SOT23-5
A
2
G
3
Y4
P5
C319
1U_0805_16V7K@
1
2
G
D
S
Q26
2N7002_SOT23
2
13
C304 1U_0805_16V7K
1 2
R468
100K_0402_5%
1 2
R569
10K_0402_5%
1 2
R594
100K_0402_5%D@
1 2
R269
180K_0402_5%
12
R325
10K_0402_5%
1 2
D27
RLZ20A_LL34
12
D14
RB751V_SOD323
2 1
R271
100K_0402_5%
R317
10K_0402_5%
1 2
R272
10K_0402_5%
1 2
G
D
S
Q24
2N7002_SOT23
2
13
R278
100K_0402_5%
12
C556
1000P_0402_50V7K
1
2
R270
100K_0402_5%
12
G
D
S
Q61
2N7002_SOT23D @
2
13
J2 JOPEN
12
R595 0_0402_5%
1 2
R285
10K_0402_5%
1 2
C289
1U_0805_25V4Z
1
2
C558
0.1U_0402_16V4Z
1
2
D28
BAS40-04_SOT23
1
2
3
R463
33K_0402_5%
1 2
C301 0.1U_0402_16V4Z
1 2
J3 JOPEN
12
G
D
S
Q25
2N7002_SOT23
2
13
U25E
SN74LVC14APWLE_TSSOP14
O10
I
11
P14
G
7
D13
1N4148_SOT23
12
BATT1
RTCBATT
12
R281
680K_0402_5%
12
G
D
S
Q50
2N7002_SOT23
2
13
Q49
DTC124EK_SC59
2
13
G
D
S
Q27
2N7002_SOT23
2
13
U28
74LCX74MTC_TSSOP14
CD1#
1
D1
2
CP1
3
SD1#
4
Q1
5
Q1#
6
GND
7
VCC 14
CD2# 13
D2 12
CP2 11
SD2# 10
Q2 09
Q2# 08
R593
100K_0402_5%D@
1 2
R466
4.7K_0402_5%
1 2
C324 1U_0805_16V7K
1 2
![](asset-29.png)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SUSP
SUSP
5VS_GATE
SUSPSUSP
SYSON#
SYSON#
SYSON
5VS_GATE
SUSP
SYSON#
SYSON_ALW
5VS_GATE
SUSP
5VS_GATE
SYSON30,34,38,40,47SUSP#16,26,32,34,36,37,47,48
SUSP35,48 SYSON#38
V_ON 47
VS_ON 47,48
+3VS
+12VALW
+5VALW
+5VALW +5VS
+5VS+3VS
+3V
+5VALW
+3VALW
+DDRVCC +25VS_18VS
+25VS_18VS
+12VALW
+3VALW
+3V
+2.5VS
+1.8VS
+1.5VALW +1.5VS
+1.5VS
+3V +3VALW
+3VS
+3VALW
+3VALW+3VALW
+5VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
Compal Electronics, Inc.
B
41 51¬P , 03, 2005
期一 一月
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PROPRIETARY NOTE
+3VALW TO +3V
+3VALW TO +3VS
+5VALW TO +5VS
+2.5V TO +2.5VS (DDR1)
+1.8V TO +1.8VS (DDR2)
+1.5VALW TO +1.5VS
+3VALW POWER
+3VALW POWER
+3VALW POWER+3VALW POWER
+3VALW POWER
In CUP side
U32
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
U42A
SN74LVC14APWLE_TSSOP14
O2
I
1
P14
G
7
C594
0.1U_0402_16V4Z
1
2
C208
1U_0805_25V4Z
1
2
C645
0.1U_0402_16V4Z@
1
2
G
D
S
Q38
2N7002_SOT23@
2
13
C596
10U_1206_16V4Z
1
2
R338
10K_0402_5%
1 2
R159
1M_0402_5%@
12
C211
4.7U_0805_10V4Z
1
2
G
D
S
Q54
2N7002_SOT23@
2
13
R341
470_0402_5%@
1 2
U42B
SN74LVC14APWLE_TSSOP14
O4
I
3
P14
G
7
G
D
S
Q37
2N7002_SOT23@
2
13
G
D
S
Q53
2N7002_SOT23
2
13
U6
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
R490
100K_0402_5%
1 2
C196
10U_1206_16V4Z
1
2
R489
470_0402_5%
@
1 2
R554
0_0402_5%
12
C404
4.7U_0805_10V4Z
1
2
U42D
SN74LVC14APWLE_TSSOP14
O8
I
9
P14
G
7
R80 0_0805_5%
1 2
G
D
S
Q19
2N7002_SOT23
2
13
C72
1U_0805_25V4Z
1
2
R161
470_0402_5%@
1 2
100K
100K
Q35
DTC115EKA_SOT23
2
13
C592
1U_0805_25V4Z
1
2
C380
4.7U_0805_10V4Z
1
2
C598
10U_1206_16V4Z
1
2
U42C
SN74LVC14APWLE_TSSOP14
O6
I
5
P14
G
7
C190
1U_0805_25V4Z
1
2
C90
4.7U_0805_10V4Z
1
2
C403
1U_0805_25V4Z
1
2
R553
0_0402_5%
12
R339
10K_0402_5%
1 2
100K
100K
Q34
DTC115EKA_SOT23
2
13
R484
1M_0402_5%@
12
C191
4.7U_0805_10V4Z
1
2
U40
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
C61
4.7U_0805_10V4Z
1
2
R81 0_0805_5%@
1 2
C686
10U_0805_6.3V6M
1
2
R157
100K_0402_5%
1 2
U12
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
C642
0.1U_0402_16V4Z
1
2
C687
10U_0805_6.3V6M
1
2
R431
470_0402_5%
@
1 2
C189
10U_1206_16V4Z
1
2
C646
0.1U_0402_16V4Z@
1
2
G
D
S
Q45
2N7002_SOT23@
2
13
U13
SI4800DY_SO8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
R340
470_0402_5%
@
1 2
G
D
S
Q18
2N7002_SOT23@
2
13
C180
0.1U_0402_16V4Z
1
2
![](asset-2a.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VDDA
+VDDA
+VDDA
+12VALW
+3V
+3VALW
+3VALW
Title
Size Document Number R ev
Date: Sheet of
401317
B
Compal Electronics, Inc.
42 51¬P , 03, 2005
期一 一月
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
M2
SCREW 8.5X2.8
1
U30D
LMV824MTX_TSSOP14
+
12
-
13
O14
V+ 4
V-
11
FD5
FIDUCAL
1
CF15
SMD40M80
1
H10
SCREW 8.5X2.8
1
H6
SCREW 8.5X2.8
1
M3
SCREW 8.5X2.8
1
FD4
FIDUCAL
1
CF9
SMD40M80
1
H18
SCREW 8.5X2.8
1
H16
SCREW 8.5X2.8
1
FD1
FIDUCAL
1
H4
SCREW 8.5X2.8
1
H5
SCREW 8.5X2.8
1
CF4
SMD40M80
1
U26D
LMV824MTX_TSSOP14
+
12
-
13
O14
V+ 4
V-
11
H20
SCREW 8.5X2.8
1
FD2
FIDUCAL
1
H3
SCREW 8.5X2.8
1
H15
SCREW 8.5X2.8
1
CF10
SMD40M80
1
M4
SCREW 8.5X2.8
1
H9
SCREW 8.5X2.8
1
CF7
SMD40M80
1
H14
SCREW 8.5X2.8
1
H2
SCREW 8.5X2.8
1
U42F
SN74LVC14APWLE_TSSOP14
O12
I
13
P14
G
7
CF2
SMD40M80
1
U31D
LMV824MTX_TSSOP14
+
12
-
13
O14
V+ 4
V-
11
H17
SCREW 8.5X2.8
1
U37B
LM358A_SO8
+IN
5
-IN
6OUT 7
H1
SCREW 8.5X2.8
1
H13
SCREW 8.5X2.8
1
H19
SCREW 8.5X2.8
1
CF11
SMD40M80
1
H12
SCREW 8.5X2.8
1
H21
SCREW 8.5X2.8
1
H8
SCREW 8.5X2.8
1
U25F
SN74LVC14APWLE_TSSOP14
O12
I
13
P14
G
7
H22
EMI2_7X2
1
FD6
FIDUCAL
1
CF1
SMD40M80
1
CF14
SMD40M80
1
M1
SCREW 8.5X2.8
1
H11
SCREW 8.5X2.8
1
FD3
FIDUCAL
1
H7
SCREW 8.5X2.8
1
CF16
SMD40M80
1
U42E
SN74LVC14APWLE_TSSOP14
O10
I
11
P14
G
7
H23
EMI2_7X2
1
![](asset-2b.png)
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
PACIN
CHGRTCP
DC_IN_S2 DC_IN_S1
PACIN
ACIN 19,34,38
PACIN 45,46
51ON#38,40
MAINPWON18,44,46
ACON45
VIN
VS
RTCVREF
+CHGRTC
RTCVREF
VIN
VS
VS
+1.5VALWP +1.5VALW
+3VALWP +3VALW
+5VALWP +5VALW
+12VALWP +12VALW
+DDRVCCP +DDRVCC
+DDRVTT+DDRVTTP
+1.8VSP +1.8VS
+1.05VS+1.05VSP
BATT_A
1538VCC
+2.5VS+2.5VSP
VIN
B+
VIN
VL
VL
+5VALWP
+DC_IN_S1
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
43 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
3.3V
3.3V
Vin Detector
High 14.57 14.01 13.46
Low 14.06 13.51 12.98
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
(1A,40mils ,Via NO.= 2)
(120mA,40mils ,Via NO.= 2)
(5A,200mils ,Via NO.= 10)
(8A,320mils ,Via NO.= 16)
(2A,80mils ,Via NO.= 4)
(5A,200mils ,Via NO.= 10)
(3.5A,140mils ,Via NO.= 7)
(3.5A,140mils ,Via NO.= 7)
(2A,80mils ,Via NO.= 4)
Precharge detector
14.3V/13.18V for adapter
PJ6
JUMP_43X118
11
2
2
PR9
10K_0402_5%
12
PD1
1N4148_SOD80
12
PD4
RLZ4.3B_LL34
12
PR32
1K_1206_5%
1 2
PJ2
JUMP_43X79
11
2
2
PR29
1K_1206_5%
1 2
PC8
0.1U_0603_25V7K
12
PJ9
JUMP_43X118
11
2
2
PR6
20K_0402_1%
12
PU1B
LM393M_SO8
+5
-6
O
7
P8
G
4
PR67
10K_0402_5%
1 2
PC17
1000P_0402_50V7K
12
PC7
0.22U_1206_25V7M
12
PR69
47K_0402_5%
1 2
PC37
1000P_0402_50V7K
12
PR68
237K_0402_1%
12
PD24
RB715F_SOT323
2
31
PR2
5.6K_0402_5%
12
PJ4
JUMP_43X118
11
2
2
PR7
10K_0402_5%
12
PJ3
JUMP_43X118
11
2
2
PU1A
LM393M_SO8
+
3
-
2O1
P8
G
4
PJ5
JUMP_43X39
11
2
2
PR64
66.5K_0402_1%
12
PC2
100P_0402_50V8J
12
PC5
1000P_0402_50V7K
12
PJ1
JUMP_43X118
11
2
2
PR63
34K_0402_1%
1 2
PJP1
JST_S4B-EH
11
33
44
22
PF1
12A_65VDC_451012
21
PR3
61.9K_0402_1%
12
PR4
1K_0402_5%
1 2
PD3
1N4148_SOD80
12
PC6
0.1U_0402_16V7K
12
PC3
1000P_0402_50V7K
12
PR11
100K_0402_5%
12
PC4
100P_0402_50V8J
12
PC9
1U_0805_25V4Z
12
PR28
1K_1206_5%
1 2
PR1 1M_0402_1%
1 2
PR60
2.2M_0402_5%
1 2
PR5 15.4K_0402_1%
1 2
PR8
33_1206_5%
12
PQ1
TP0610T_SOT23
13
2
G
D
S
PQ16
2N7002_SOT23
2
13
PU2
S-812C33AUA-C2N-T2_SOT89
IN 2
GND
1
OUT
3
PJ7
JUMP_43X118
11
2
2
PR14
200_0603_5%
1 2
PC10
10U_0805_10V4Z
12
PR10
200_0603_5%
1 2
PL1
FBM-L18-453215-900LMA90T_1812
1 2
PC39
1000P_0402_50V7K
12
PQ17
DTC115EUA_SC70
2
13
PR12 22K_0402_5%
1 2
PR13
200_0603_5%
1 2
PR34
499K_0402_1%
12
PJ10
JUMP_43X118
11
2
2
PJ8
JUMP_43X118
11
2
2
PC1
1000P_0402_50V7K
12
PD2
1N4148_SOD80
1 2
PR57
499K_0402_1%
12
![](asset-2c.png)
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
TM_REF1
TM_REF1
TS_A
AB/I
ALI/NIMH#
BATT_A_S1
EC_SMCA
EC_SMDA
MAINPWON 18,43,46
EC_SMB_CK1 34,36
BATT_TEMPA 34
EC_SMB_DA1 34,36
ALI/MH# 34
VL VS
VL
BATT_A
VL
VLVL
+3VALWP
VMB_A
+3VALWP
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
44 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
PH2 near main Battery CONN :
Recovery at 45 degree C
BAT. thermal protection at 79 degree C
Recovery at 45 degree C
CPU thermal protection at 84 degree C
PH1 under CPU botten side :
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
PL2
FBM-L18-453215-900LMA90T_1812
1 2
PQ2
DTC115EUA_SC70
2
13
PC11
0.1U_0603_25V7K
12
PC15
1000P_0402_50V7K
12
PR15
47K_0402_1%
1 2
PF2 12A_65VDC_451012
21
PR19
1K_0402_5%
12
PC12
1000P_0402_50V7K
12
PR22
100_0402_5%
1 2
PC13
0.01U_0402_25V7Z
12
PR16
1K_0402_5%
1 2
PR23
6.49K_0402_1%
12
PR18
47K_0402_1%
1 2
PC14
0.22U_0805_16V7K_V2
12
PJP2
TYCO_1747602-1_7P
BATT+ 1
B/I 3
TS 4
SMD 5
SMC 6
ID 2
GND 7
PR20
16.9K_0402_1%
1 2
PR26
1K_0402_5%
12
PR33
14.7K_0402_1%
1 2
PR35
3.48K_0402_1%
12
PD6
1SS355_SOD323
12
PU3B
LM393M_SO8
+
5
-
6O7
P8
G
4
PD5
1SS355_SOD323
12
PR17
47K_0402_5%
1 2
PU3A
LM393M_SO8
+
3
-
2O1
P8
G
4
PH1
10KB_0603_1%_TH11-3H103FT
12
PR21
100_0402_5%
1 2
PR27
100K_0402_1%
12
PR30
47K_0402_1%
1 2
PR31
47K_0402_1%
1 2
PC18
0.22U_0805_16V7K_V2
12
PR24
3.32K_0402_1%
12
PR25
100K_0402_1%
12
PH2
10KB_0603_1%_TH11-3H103FT
12
![](asset-2d.png)
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
CS
ACON
CS
N18
ACOFF#
PACIN
ACOFF#
LXCHRG
ACOFF 34
IREF34
FSTCHG34
ADP_I34
PACIN43,46
BATT_AOVP34
DKN_B+_ON34
ACON43
VIN
VIN
BATT_A
P2 P3 B+
B++
+3VALWP
VMB_A
+12VALWP
B+DKN_B+
B+
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
45 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
Iadp=0~4.7A
CC=0.5~3.3A
CV=12.6V(9 CELLS LI-ION)
IREF=0.6V~3.21V
IREF=1.31*Icharge
4.2V
OVP voltage : LI
(BAT_OVP=0.1111 *VMB)
3S3P : 13.5V--> BATT_OVP= 1.5V
PQ13
DTC115EUA_SC70
2
13
PQ5
AO4407_SO8
3 6
5
7
8
2
4
1
PR61
10K_0402_1%
1 2
PC34
4.7U_1206_25V6K
12
PR39
47K_0402_5%
1 2
PR47
68K_0402_5%
1 2
PR37
200K_0402_1%
12
PR54
150K_0603_0.1%
12
PU5A
LM358A_SO8
+3
-2
0
1
P8
G
4
PC29
1000P_0402_50V7K
1 2
PD8
1SS355_SOD323
1 2
PQ3
AO4407_SO8
3 6
5
7
8
2
4
1
PC25
0.1U_0402_16V7K
12
PQ15
DTC115EUA_SC70
2
13
PD9
1SS355_SOD323
1 2
PR43
10K_0402_1%
12
PR38
47K_0402_5%
12
PU4
MB3887_SSOP24
-INC2
1
OUTC2
2
+INE2
3
-INE2
4
+INC2 24
GND 23
CS 22
VCC(o) 21
FB2
5
VREF
6
FB1
7
-INE1
8
+INE1
9
OUTC1
10
OUTD
11
-INC1
12
OUT 20
VH 19
VCC 18
RT 17
-INE3 16
FB3 15
CTL 14
+INC1 13
PQ7
AO4407_SO8
36
5
7
82
4
1
PC19
4.7U_1206_25V6K
12
PD7
RLZ18B_LL34
12
PC33
4.7U_1206_25V6K
12
G
D
S
PQ11
SN7002N_SOT23
2
13
PC26
4700P_0402_25V7K
1 2
PQ4
AO4407_SO8
36
5
7
82
4
1
PR65
2.2K_0402_5%
12
PJ11
JUMP_43X118
11
2
2
PR50
0.02_2512_1%
1 2
PC22
0.1U_0603_25V7K
12
PQ12
DTC115EUA_SC70
2
13
PC24
0.1U_0603_25V7K
1 2
PC21
4.7U_1206_25V6K
12
PR40
1K_0402_5%
1 2
PQ14
AO4407_SO8
36
5
7
82
4
1
PR62
499K_0402_1%
12
PR49
3K_0402_1%
1 2
47K
47K
PQ6
DTA144EUA_SC70
2
1 3
PC36
1U_1206_25V7K
1 2
PC30
0.1U_0603_25V7K
1 2
PQ9
DTC115EUA_SC70
2
13
PC35
4.7U_1206_25V6K
12
PC28
0.1U_0402_16V7K
12
PR42
25.5K_0402_1%
12
PR56
47K_0402_5%
12
PR59
27K_0402_1%
1 2
PR55
300K_0603_0.1%
12
PQ8
DTC115EUA_SC70
2
13
PR52
47K_0402_5%
1 2
PC32
0.1U_0402_16V7K
12
PU5B
LM358A_SO8
+5
-6
0
7
EC31QS04
PD11
12
PC27
0.1U_0603_25V7K
1 2
PR66
105K_0402_1%
12
PR41 100K_0402_5%
12
PC20
4.7U_1206_25V6K
12
PL4
10UH_D104C-919AS-100M_4.5A_20%
1 2
PR46
1K_0402_5%
1 2
PR51 10K_0402_5%
12
PR44
10K_0402_5%
1 2
PR36
0.015_2512_1%
12
PR58
340K_0402_1%
12
G
D
S
PQ10
SN7002N_SOT23
2
13
PC31
1500P_0402_50V7K
1 2
PR53
100K_0402_1%
12
EC31QS04
PD12
12
PR48
143K_0402_1%
1 2
PR45
100K_0402_1%
12
PC23
0.022U_0402_16V7K
1 2
PC38
0.01U_0402_25V7Z
12
PD10
1SS355_SOD323
1 2
![](asset-2e.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FLYBACKSNB
BST51
PDH3
CSH3
PDL5
PLX5
BST31
N4
PDL3
PLX3
PDH5
CSL3 CSH5
MAINPWON 18,43,44
PACIN43,45
POK 47 +5VALWP
VS
B+++
B+++
VL
+12VALWP
B+
+3VALWP
VS
2.5VREF
VL
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
46 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
PQ19
SI4800DY-T1_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PU7
MAX1902EAI_SSOP28
LX3
26
DL3
24
BST3
25
DH3
27
CSH3
1
CSL3
2
FB3
3
SKIP#
10
GND
8
12OUT 4
VDD 5
BST5 18
DH5 16
LX5 17
DL5 19
PGND 20
CSH5 14
CSL5 13
FB5 12
SEQ 15
REF 9
SYNC 6
RST# 11
SHDN#
23
TIME/ON5
7
RUN/ON3
28
VL 21
V+ 22
PR76
1.27K_0402_1%
12
PC68
0.47U_0603_16V7K
12
PC45
470P_0805_100V7K
1 2
PC44
4.7U_1206_25V6K
1 2
PT1
10uH_SDT-1205P-100-118_5A_20%
1 4
3 2
PD16
SKUL30-02AT_SMA
2 1
PR81
620_0402_5%
12
PC51
4.7U_1206_25V6K
12
PC60
100P_0402_50V8J
12
PC46
0.1U_0603_25V7K
1 2
PJ12
JUMP_43X118
11
2
2
PD14
DAP202U_SOT323
2
3
1
PR78
2M_0402_1%
12
PR75
1.54K_0402_1%
12
PC62
1000P_0402_50V7K
12
PC61
4.7U_0805_6.3V6K
12
PR86
10.2K_0402_1%
12
PD17
SKUL30-02AT_SMA
2 1
PQ20
SI4810DY_SO8
S
1
S
2
S
3
G
4
D8
D7
D6
D5
PC55
47P_0402_50V8J
12
PC57
0.47U_0603_16V7K
12
PR83
698_0402_1%
12
PR74 22_1206_5%
12
PQ21
SI4810DY_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
+
PC59
220U_6.3V_M
1
2
PR85
47K_0402_5%
1 2
PR82
10K_0402_5%
1 2
PC63
100P_0402_50V8J
12
PC52
4.7U_0805_6.3V6K
12
PQ18
SI4800DY-T1_SO8
S
1
S
2
S
3
G
4
D8
D7
D6
D5
PC53
0.1U_0603_25V7K
12
PR89
220K_0402_5%
12
+
PC65
220U_6.3V_M
1
2
PC54
4.7U_1206_25V6K
12
PD15 1SS355_SOD323
1 2
PR77
1.27K_0402_1%
1 2
PC58
0.47U_0603_16V7K
12
PC56
47P_0402_50V8J
12
PC64
100P_0402_50V8J@
12
PL5
10UH_D104C-919AS-100M_4.5A_20%
12
PR84
3.32K_0402_1%
1 2
PC66
0.047U_0603_25V7M@
12
PC49
0.1U_0603_25V7K
1 2
PR88
10K_0402_1%
12
PR87
10K_0402_1%
1 2
PC67
100P_0402_50V8J@
12
PD13
EC11FS2_SOD106
12
PC48
4.7U_1206_25V6K
12
PR79
1M_0402_1%
1 2
PR80
0_0402_5%
12
PC47
4.7U_1206_25V6K
12
PC50
4.7U_1206_25V6K
12
![](asset-2f.png)
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
SYSON30,34,38,40,41
POK 46
SUSP#16,26,32,34,36,37,41,48
V_ON41
VS_ON41,48
B+
+5VALWP
+DDRVCCP
+1.5VALWP
+3VS
+2.5VSP
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
47 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
+1.5V
2.5V/1.8V
DDRI 18.2K_0402_1% (2.5V)
PR94
DDRII 10K_0402_1% (1.8V) PU12,PC95,PR114,PC96
UNPOP
PU9,PC84,PR105,PR104,PR106,PC85
PR101
10K_0402_1%
12
PC84
4.7U_0805_6.3V6K
@
1 2
PJ13
JUMP_43X118
11
2
2
PC76
0.1U_0402_16V7K
12
PC75
0.01U_0402_25V7K
12
PR102
200K_0402_1%
12
PC81
0.01U_0402_16V7Z
12
PR94
18.2K_0402_1%
12
PR99 0_0402_5%
1 2
+
PC80
220U_6.3V_M
1
2
PC69
4.7U_1206_25V6K
12
PR72
0_0402_5%
@
1 2
PC71
4.7U_1206_25V6K
12
PR106
20K_0402_1% @
12
PR105
0_0402_5%
@
1 2
PL8
4.7UH_D104C-919AS-100M_5.2A_20%
1 2
PR70 0_0402_5%
1 2
PQ24
SI4810DY_SO8
S
1
S
2
S
3
G
4
D8
D7
D6
D5
PR91
2.2_0603_5%
1 2
PC72
0.1U_0603_25V7K
12
PQ25
SI4810DY_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PC73
2.2U_0805_10V6K
12
PQ22
SI4800DY-T1_SO8
S
1
S
2
S
3
G
4
D8
D7
D6
D5
PR95
1.87K_0402_1%
1 2
PR98
0_0402_5%@
1 2
PR103
107K_0402_1%
12
+
PC78
220U_6.3V_M
1
2
PC70
4.7U_1206_25V6K
12
PU9
G965-18P1U_SO8
@
ADJ 4
GND
5
VIN
2VO 3
EN
1
GND 8
GND 7
GND
6
PC83
0.1U_0402_16V7K@
12
PC77
0.1U_0402_16V7K
12
PQ23
SI4800DY-T1_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PU8
ISL6225BCA-T_SSOP28
GND
1
LGATE1
2
PGND1
3
PHASE1
4
UGATE1
5
BOOT1
6
ISEN1
7
EN1
8
VOUT1
9
VSEN1
10
OCSET1
11
SOFT1
12
DDR
13
VIN 14
PG1
15 PG2/REF 16
SOFT2 17
OCSET2 18
VSEN2 19
VOUT2 20
EN2 21
ISEN2 22
BOOT2 23
UGATE2 24
PHASE2 25
PGND2 26
LGATE2 27
VCC 28
PR100
10K_0402_1%
12
PR90
0_1206_5%
12
PD18
DAP202U_SOT323
2
31
PC82
0.1U_0402_16V7K@
12
PR93
0_0603_5%
1 2
PL6
FBM-L18-453215-900LMA90T_1812
1 2
PR104
22K_0402_1% @
12
PR96
2.4K_0402_1%
1 2
PC86
0.1U_0402_16V7K@
12
PC79
0.01U_0402_16V7Z
12
PC16
4.7U_0805_6.3V6K
12
PR92
0_0603_5%
1 2
PR97
6.81K_0402_1%
12
PC85
10U_1206_6.3V6M
@
1 2
PL7
1.8UH_D104C-919AS-1R8N_9.5A_20%
1 2
PC74
0.01U_0402_25V7K
12
![](asset-30.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SUSP
SUSP# 1.8VS_ON
VS_ON
VS_ON
1.8VS_ON
SUSP#
6
,26,32,34,36,37,41,47
SUSP35,41
VS_ON41,47
+5VALW
+1.05VSP
VL
+3VALWP
+DDRVTTP
+DDRVCC
+DDRVCCP
+1.8VSP
+1.8VS
+3V
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
48 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
PJ14
JUMP_43X118
11
2
2
PC100
0.1U_0402_16V7K
12
PC90
470P_0603_50V7K
12
PR110
0_0402_5%@
1 2
PC93
0.1U_0402_16V7K@
1 2
PC99
0.1U_0402_16V7K@
12
PC98
1U_0603_6.3V6M
12
PU14
APL5301-18BC-TR_SOT23-5
@
VOUT
1
VIN
3
BP 5
GND
2
SHDN# 4
PC96
10U_1206_6.3V6M
1 2
PU11
APL5331KAC-TR_SO8
VOUT
4
NC 5
GND
2
VREF
3
VIN
1VCNTL 6
NC 7
NC 8
TP 9
PR115
0_0402_5%
1 2
PQ26
SI4800DY-T1_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PR108
5.1K_0402_1%
1 2
PC91
0.1U_0402_16V7K
12
G
D
S
PQ27
SN7002N_SOT23
2
13
+
PC92
220U_6.3V_M
1
2
PD19
1N4148_SOD80
1 2
G
D
S
PQ29
SN7002N_SOT23
2
13
PC122 1U_0603_10V4Z@
12
PC94
0.1U_0402_16V7K
1 2
PR107
10_0603_5%
1 2
PR710_0402_5%
1 2
PU12
G965-18P1U_SO8
ADJ 4
GND
5
VIN
2VO 3
EN
1
GND 8
GND 7
GND
6
PC97
10U_1206_6.3V7K
12
PR113
1K_0402_1%
12
PR111
2.26K_0402_1%
1 2
PU10
APW 7057KC-TR_SOP8
BOOT 1
LGATE 4
UGATE 2
FB
6
PHASE 8
GND
3
OCSET
7
VCC 5
PR109
100K_0402_5%
12
PC101
10U_1206_6.3V7K
12
PQ28
SI4800DY-T1_SO8
S
1S
2S
3G
4
D8
D7
D6
D5
PR116
1K_0402_1%
12
PC123
0.1U_0402_16V4Z
@
1 2
PR114
0_0402_5%@
1 2
PL9
3UH_SPC-07040-3R0_5A_30%
12
PC95
4.7U_0805_6.3V6K
1 2
PC102
0.1U_0402_16V7K@
12
PJ16
JUMP_43X118
11
2
2
PR112
7.5K_0402_1%
1 2
PC87
1U_0603_6.3V6M
12
PR143
0_0402_5%
1 2
PC89
22U_1206_6.3V
12
PC88
22U_1206_6.3V
12
G
D
S
PQ30
SN7002N_SOT23
2
13
PC1241U_0603_10V4Z@
1
2
PJ15
JUMP_43X118
11
2
2
![](asset-31.png)
REF
VCC
FB
FB
VCC
VCC
REF
CPU_VID05
CPU_VID45
CPU_VID35
CPU_VID15
CPU_VID55
CPU_VID25
VGATE6,14,19
VR_ON34
PM_DPRSLPVR19
PSI#5
PM_STP_CPU#14,19
+5VS CPU_B+ B+
CPU_B+
+5VS
+CPU_CORE
+5VS
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
49 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
CPU VCC SENSE
PC107
1U_0603_16V6K
1 2
PR135
20K_0402_1%
1 2
PC106
2.2U_0603_6.3V6K
1
2
PR134
0_0402_5%
1 2
PC113 470P_0402_50V8J
1 2
PR146
0_0603_5%
12
PC108
0.01U_0402_25V7Z
12
PC114 0.22U_0603_16V7K
1 2
PR120 909_0402_1%
12
PL10
0.56UH_ETQP4LR56WFC_21A_20%
1 2
PC109
0.22U_0603_16V7K
12
PR118
3.3_0603_5%
12
C
B
E
PQ38
HMBT2222A_SOT23
1
2
3
PR142 0_0402_5%@
1 2
PR133
3.3_0603_5%
1 2
PC104
4.7U_1206_25V6K
12
PR147
0_0603_5%
12
PR124 0_0402_5%
1 2
PR131
0_0402_5%
1 2
PC116
100P_0402_50V8J
12
PR128
3K_0402_1%
1 2
+
PC103
220U_25V_M
1
2
PC110
1000P_0402_50V7K
@
1 2
PR127 200K_0402_1%
1 2
PC120
0.22U_0603_16V7K
12
PR140 0_0402_5%
1 2
PC40
680P_0603_50V8J
12
PC112
270P_0402_50V7K
1 2
PC105
4.7U_1206_25V6K
12
PQ31
AO4408_SO8
S
1
S
3G
4
D8
D7
D6
D5
S
2
PR129
66.5K_0402_1%
1 2
G
D
S
PQ37
RHU002N06_SOT323
2
13
PR144
4.7_1206_5%
12
PR136
10K_0402_1%
1 2
PC41
680P_0603_50V8J
12
PU13
MAX1532
TIME
1
TON
2
SUS
3
S0
4
S1
5
SHDN#
6
OFS
7
REF
8
ILIM
9
VCC
10
GND
11
CCV
12
GNDS 13
CCI 14
FB 15
OAIN- 16
OAIN+ 17
SKIP
18
D5
19
D4
20
D3
21
D2
22
D1
23
D0
24
VROK
25
BSTM 26
LXM 27
DHM 28
DLM 29
VDD 30
PGND 31
DLS 32
DHS 33
LXS 34
BSTS 35
V+ 36
CMP 37
CMN 38
CSN 39
CSP 40
PR125 30.1K_0402_1%
12
PC121
0.47U_0603_16V7K
1 2
PR117
10_0402_5%
12
PL11
0.56UH_ETQP4LR56WFC_21A_20%
1 2
PR119
0.001_2512_5%
1 2
PC119
4.7U_1206_25V6K
12
PR139
909_0402_1%
1 2
PR132
10.7K_0402_1%
1 2
PR145
4.7_1206_5%
12
PC117
27P_0402_50V8J
1 2
PR122 499_0402_1%
12
PQ36
AO4410_SO8
S
1
S
3G
4
D8
D7
D6
D5
S
2
PC115
0.022U_0402_16V7K
1 2
PD20
EP10QY03
2 1
PR121 499_0402_1%
12
G
D
S
PQ34
RHU002N06_SOT323
2
13
PC118
4.7U_1206_25V6K
12
PR126 909_0402_1%
1 2
PL3
FBM-L18-453215-900LMA90T_1812
1 2
PD22
EP10QY03
21
G
D
S
PQ33
RHU002N06_SOT323
2
13
PQ35
AO4408_SO8
S
1
S
3G
4
D8
D7
D6
D5
S
2
PC111
0.47U_0603_16V7K
1 2
PR137
100K_0402_1%
1 2
PR130 100K_0402_1%
1 2
PR123
3K_0402_1%
1 2
PR138 909_0402_1%
12
PQ32
AO4410_SO8
S
1
S
3G
4
D8
D7
D6
D5
S
2
PR141 0_0402_5%@
1 2
![](asset-32.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number R ev
Date: Sheet of
401317
B
SCHEMATIC, M/B LA-2492
50 51¬P , 03, 2005
期一 一月
Compal Electronics, Inc.
EAT10 PIR List
Rev:0.2 PIR List 2004/10/26 Writer by Sam Tsai********** **********
P04:Add @ in R28
P06:Add @ in C441, C427
Del JP9
P12:+3VS change from JP25.196 to JP25.194
P15:New add R570, R571 & R572
P18:New add R573
P16:Change U44 from 7404 to 74125
P20:R214 Change Value from 1K to 10ohm
P24:New add R586
P33:New add R543, R544
P27:R73 Change Value from 4.99K to 4.7K
P32:Modify C399 Net to SPKL+
add@ in C647 ~ C662
P37:SW1 change to 1BS003-1211L_3P
P36:New add
New add C672 ~ C681
Intel Recommend
C472 & C460 Change Value from 220U to 330U Power Team testing OK
Intel Recommend
RGB without Docking
New add L33 EMI
Del D2 & D25 EMI
LCDVDD Soft-Start
Intel Recommend
Intel Recommend
C271 Change Value from 0.1U to 1U
R439 Change Value from 180K to 20K Intel Recommend
Intel Recommend
Intel Recommend
Intel Recommend
P22:New add @R , @R& Q
TI Recommend
SWDJ testing
New add @R581
P25:New add R582, R583, @R584, R585, R588, R589 & @C685 TI Recommend
Marvwll Recommend
P31:R361 & R371 Change Value from 47K to 22K Design Change
TI Recommend
Design Change
P33:New add L34 EMI
P34:New add R587 Design Change
P35:New add JP32 & C671 Design Change
New add C682 ~ C684 EMI
JP13 reverse Design Change
SWDJ testing
Design Change
P38:Q52.3 change from +3VALW to +3V
Q57.3 change from +5VALW to +5VS
Lid Switch IC Power change from JP16.26 +3VALW to JP16.27 RTCVREF
Design Change
EMI
P39:New add R574 Design Change
P40:Del D11 Design Change
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
![](asset-33.png)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
401317
B
51 51,
星期一 一月
03, 2005
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2492
Version Change List ( P. I. R. List ) for Power Circuit
Item DescriptionDate Request
Owner Rev.Page#
10.1
0.2
Title
45 07/06/2004 CompalDesign change Change PD7 from RLZ22B to RLZ18B for 15V adapter OVP
0.2
0.2
0.2
0.2
0.2
0.2
2 43 Design change 08/20/2004 Compal Add precharge function for MAX1902 UVP when adapter pull out /in right away
3 49 08/20/2004 Add PL3 fo speed step function,change PC103 from 100U_25V_M to 220U_25V_M
443
Design change
Design change 08/20/2004
Compal
Compal Change PF1 from 7A to 12A for customer review fuse current rating too margin
5 43 Design change 08/20/2004 Compal Change PQ1 from TP0610T to TP0610T for EOL
6 47 Design change 08/20/2004 Compal48
7 49 Design change 08/20/2004 Compal
Change control sign for HW request
Change PC115 from 0.022U to 2200P for improve transient
8 47 Design change 08/20/2004 Compal Change PL7 from 4.7UH_5.2A to 9.5A for design margin
9 48 Design change 10/04/2004 Change control sign for HW request Compal
10 48 Design change 12/20/2004 Compal Change PR118.PR133 from 0_0603_5% to 3.3_0603_5% and add 4.7_1206_5% on PR144,PR145,680p_0603_50V on PC40 PC41.
for EMI fail
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D