NIWBA_LA5371_ARRANDALE_0324B Compal LA 5371P
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A B C D E 1 1 Compal Confidential 2 Schematics Document Arrandale/Clarksfield with Intel IBEX PEAK-M core logic 2 NIWBA 3 3 REV:0.1 4 4 Issued Date Compal Electronics,Ltd. Compal Secret Data Security Classification 2008/03/25 Deciphered Date 2008/04/ Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Cover Sheet Size Document Number Custom Rev 0.1 NIWBA_LA5371P Date: Tuesday, March 24, 2009 Sheet E 1 of 52 A B C D ZZZ1 Compal confidential POWER BD Power on X1 LED X1 (G) :POWER NOVO X1 File Name : 15.6W_PCB_LA5371P VRAM 64*16 DDR3*8 1 page20 PCI-E X16 intel Arrandale/Clarksfield (UMA/DIS) (DIS) NVidia N10M-GS NVidia N10P-GS HDMI CONN page26 Clock Generator RIGHT BD VOLUME UP X1 VOLUME DOWN X1 MUTE X1 MUTE LED X1(G) 1 ICS9LRS3199AKLFT Socket-rPGA989 37.5mm*37.5mm DDR3-SO-DIMM X2 BANK 0, 1, 2, 3 page5~9 level shift IC 8110T 100MHz 2.7GT/s page27 page26 Dual Channel DDR3-800(1.5V) DDR3-1067(1.5V) DMI *4 FDI *8 page 10,11 UP TO 8G switchable graphic CRT cable page28 2 LVDS Connector Slide Bar LED X 10 (B) USER-DEFINED (W) DOLBY (W) LED X 3 WIRELESS LED (G) BLUETOOTH LED (G) 3G LED (G) HDD LED (G) page12 page19~25 switchable graphic E page29 PCI Express Mini card Slot 1 page28 SPK amplifier Intel Ibex Peak M switchable graphic page36 page29 6*PCI-E BUS Audio Codec AZALIA 25mm*25mm page35 6*SATA serial page 13~18 2Channel MIC_Int page36 CMOS Camera page40 page30 SPI ROM BIOS page38 BlueTooth CONN LPC BUS page40 USB CONN X1 page30 BCM57790/57780 10/100/1G LAN SIM Card page36 HP X 1+ MIC_Ext X1page36 Realtek ALC272 14*USB2.0 2 1Channel Speaker FCBGA 951 PCI Express Mini card Slot 2 3 page36 WOOFER amplifier page30 PCI Express Mini card Slot 3 2Channel Speaker page35 3 page40 EC ENE KB926D New Card X1 page37 page31 page29 page30 Realtek 5159E MS/MS pro/SD/SD pro/mmc/XD page33 M-PCIE CONN X 3 page29 Int.KBD RJ45 CONN page32 page38 Touch Pad SPI ROM page39 ESATA HDD AND USB CONN page39 page34 SATA HDD CONN page34 4 4 SATA ODD CONN page34 Compal Secret Data Security Classification 2008/03/24 Issued Date 2008/04/ Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title MB Block Diagram Size Document Number Custom Date: A B C D Compal Electronics, Inc. Rev 0.1 NIWBA_LA5371P Tuesday, March 24, 2009 Sheet E 2 of 52 A B C DDR3 Voltage Rails power plane 1 +5VALW +1.5V +B +3VALW State SOURCE RAM M2 +3VS SMB_EC_CK1 +1.5VS SMB_EC_DA1 +VCCP SMB_EC_CK2 +CPU_CORE SMB_EC_DA2 +VGA_CORE SMBCLK +1.8VS SMBDATA +0.75VS SML0CLK +1.05VS SML0DATA SML1CLK SML1DATA S0 O O O O S3 O O O X S5 S4/AC O O X X S5 S4/ Battery only O S5 S4/AC & Battery don't exist E SMBUS Control Table +5VS 2 D X X X X X X X KB926 +3VALW KB926 +3VALW PCH +3VALW PCH +3VALW PCH +3VALW N10x Thermal Sensor N10x Cap sensor board X X X X X X X X X X X WLAN CLK CHIP WWAN BATT KE926 SODIMM V X X X X X X X V X X X X X X X +3VALW +3VALW +3VS +3VS V X X X X X X X X X X V X X X V X +3VALW V +3VS NEW CARD PCH X V V X X X X V X X +3VS +3VS 1 +3VALW I2C / SMBUS ADDRESSING DEVICE HEX ADDRESS DDR SO-DIMM 0 A0 10100000 DDR SO-DIMM 1 A4 10100100 CLOCK GENERATOR (EXT.) D2 11010010 2 @ FUNCTION EVT 3 4 45@ GIGA@ NO_TVSW@ ARRAY@ S512@ H512@ S1024@ H1024@ X76@ M1@ 3G@ 10M@ 10P@ UMA@ DIS@ VGA@ (45 BOM) (GIGA LAN) (NON TV POWER SW) (ARRAY MIC) FOR X76 BOM FOR X76 BOM FOR X76 BOM FOR X76 BOM (X76 BOM) (DDR M1 MODE) (3G MODE) FOR 10M CHIP FOR 10P CHIP FOR Auberndale NON-USE 100@ TVSW@ MONO@ (100 LAN) (TV POWER SW) (MONO MIC) PCIE PORT LIST PORT 1 2 3 4 5 6 7 8 USB PORT LIST DEVICE PORT NEW CARD WLAN LAN 3G 0 1 2 3 4 5 6 7 8 9 10 11 12 13 TV TUNNER DEVICE 3 LEFT SIDE RIGHT SIDE CMOS RIGHT SIDE CARD READER WIRELESS TV TUNNER NEW CARD BT 3G 4 FOR Auberndale/Clarksfield FOR NVIDIA PART Compal Secret Data Security Classification 2008/03/24 Issued Date 2008/04/ Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title MB Notes List Size B Date: A B C D Compal Electronics, Inc. Document Number Rev 0.1 NIWBA_LA5371P Tuesday, March 24, 2009 Sheet E 3 of 52 A B VGA and DDR3 Voltage Rails C (N10x GPIO) GPIO I/O ACTIVE GPIO0 N/A N/A GPIO1 IN - Hot plug detect for IFP link C GPIO2 OUT H Panel Back-Light brightness(PWM capable) GPIO3 OUT H Panel Power Enable GPIO4 OUT H Panel Back-Light On/Off (PWM) GPIO5 OUT - GPU VID0 GPIO6 OUT - GPU VID1 GPIO7 OUT - GPU VID2 GPIO8 I/O L Thermal Catastrophic Overtemp GPIO9 OUT L Thermal Alert D E Performance Mode P0 TDP at Tj = 102 C* (DDR3) GPU (4) Mem (1,5) NVCLK /MCLK Products (W) (W) (MHz) (V) N10P-GS 128bit 1024MB DDR3 21.07 6.67 TBD TBD 18.25 17.34 Function Description FBVDD (1.5V) NVVDD (A) (W) PCI Express I/O and FBVDDQ (GPU+Mem) (1.05V) PLLVDD (1.5V) (6) (1.8V) I/O and PLLVDD (1.05V) Other (3.3V) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W) 2.06 3.09 4.09 6.14 850 75 63 55 0.89 0.14 0.07 0.18 1 2 1 OUT GPIO11 I/O L SLI raster sync GPIO12 IN - AC power detect pin GPIO13 OUT - MEM_VID orPower supply control GPIO14 OUT - Power supply control GPIO15 IN - Hot plug detect for IFP Link E GPIO16 OUT - Programmable Fan Control GPIO17 IN - GPIO18 IN - GPIO19 IN - GPIO20 IN - GPIO21 IN - Hot plug detect for IFP link F GPIO22 IN - SLI swap ready signal GPIO23 I/O 20.97 6.73 TBD TBD 19.17 17.25 2.03 3.05 4.09 6.14 840 0.88 75 0.14 63 0.07 55 0.18 N10P-LP 128bit 1024MB DDR3 15.48 6.44 TBD TBD 13.95 11.86 1.90 2.85 3.99 5.99 810 0.85 75 0.14 63 0.07 55 0.18 Performance Mode P0 TDP at Tj = 102 C* (DDR3) Memory VREF switch GPIO10 N10P-GE 128bit 1024MB DDR3 GPU (4) Mem (1,5) NVCLK /MCLK Products (W) (W) (MHz) (V) N10M-GE 64bit 512MB DDR3 13.36 2.93 TBD N10M-GS 64bit 512MB DDR3 14.29 3.10 N10M-LP 64bit 512MB DDR3 8.28 2.91 Power Sequence FBVDD (1.5V) NVVDD (A) (W) PCI Express I/O and FBVDDQ PLLVDD (GPU+Mem) (1.05V) (6) (1.8V) (1.5V) I/O and PLLVDD (1.05V) Other (3.3V) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W) TBD 11.89 10.70 0.66 0.99 2.16 3.24 792 0.83 75 0.14 63 0.07 100 0.33 TBD TBD 11.53 11.53 0.70 1.05 2.28 3.42 817 0.86 75 0.14 63 0.07 100 0.33 TBD TBD 0.62 0.93 2.20 3.3 782 0.82 75 0.14 63 0.07 100 0.33 6.60 5.61 2 The ramp time for any rail must be more than 40us Hot plug detect for IFP Link D (+3VS) VDD33 PEX_VDD can ramp up any time (1.1VS) PEX_VDD tNVVDD 3 3 (+VGA_CORE) NVVDD GPIO6 GPIO5 GPU_VID1 N10M-GS GPU_VID0 VGA_CORE N10P-GS P-State 0 0 0.8V 12 0 1 0.85V 12 1 1 0.9V 0, 10 tNV-IFPAB_IOVDD IFPAB_IOVDD tNV-FBVDDQ (1.8VS) FBVDDQ 4 4 Compal Secret Data Security Classification 2009/03/16 Issued Date 2010/03/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title VGA Notes List Size B Date: A B C D Compal Electronics, Inc. Document Number Rev 0.1 KIWB1/B2_LA4602P Tuesday, March 24, 2009 Sheet E 4 of 52 5 4 3 2 1 ： D D Layout rule 10mil width trace length < 0.5", spacing 20mil JCPU1B COMP3 20_0402_1% 1 R834 2COMP2 AT24 COMP2 49.9_0402_1% 1 R835 2COMP1 G16 COMP1 49.9_0402_1% 1 R837 2COMP0 AT26 COMP0 TP_SKTOCC# <16> 50_0402_1% H_PECI +VCCP 2 H_CATERR# 1 R840 R841 1 0_0402_5% 2 H_PECI_ISO 2 R842 SKTOCC# AK14 CATERR# AT15 PECI 1 68_0402_5% H_PROCHOT# <51> H_PROCHOT# H_THERMTRIP#_R <16> H_THERMTRIP# AN26 AK15 PROCHOT# THERMAL +VCCP AH24 THERMTRIP# BCLK BCLK# CLOCKS 2COMP3 AT23 AR30 AT30 PEG_CLK PEG_CLK# E16 D16 DPLL_REF_SSCLK DPLL_REF_SSCLK# A18 A17 AP26 2 H_PM_SYNC_R 0_0402_5% AL15 PM_SYNC AN14 VCCPWRGOOD_1 1 R852 2 VCCPWRGOOD_1 0_0402_5% R855 4.75K_0402_1% 1 <16> H_CPUPWRGD VDDPWRGOOD_R <15> PM_DRAM_PWRGD RESET_OBS# 1 R857 2 VCCPWRGOOD_0 0_0402_5% AN27 VCCPWRGOOD_0 1 R858 2 VDDPWRGOOD_R 0_0402_5% AK13 SM_DRAMPWROK AM15 VTTPWRGOOD AM26 TAPPWRGOOD AL14 RSTIN# 1 1.07V 1 R850 1 H_CPURST#_R R848 <49> VCCP_POK R860 12K_0402_1% FROM POWER VTT POWER GOOD SIGNAL 1 2 1.5K_0402_5% PLT_RST#_R DDR3 Compensation Signals CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16> SM_RCOMP0 1 R836 1 R838 1 R839 SM_RCOMP1 CLK_EXP CLK_EXP# CLK_EXP <14> CLK_EXP# <14> SM_RCOMP2 pins unused by Clarksfield on the rPGA989 Package 100_0402_1% 2 24.9_0402_1% 2 130_0402_1% Layout Note:Please these resistors near Processor DRAMRST# <10,11> SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 +VCCP PM_EXTTS#0 1 R843 1 R845 2 PM_EXT_TS#[0] PM_EXT_TS#[1] AN15 AP15 PM_EXTTS#0 PM_EXTTS#1 PRDY# PREQ# AT28 AP27 XDP_PREQ# XDP_PREQ# R846 1 @ 2 51_0402_1% TCK TMS TRST# AN28 AP28 AT27 XDP_TCK XDP_TMS XDP_TRST# XDP_TMS R847 1 @ 2 51_0402_1% XDP_TDI R849 1 @ 2 51_0402_1% TDI TDO TDI_M TDO_M AT29 AR27 AR29 AP29 XDP_TDI XDP_TDO XDP_TDO R851 1 R853 2 XDP_TCK R854 1 DBR# AN25 XDP_DBRESET# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 1 R844 2 0_0402_5% PM_EXTTS#1_R <10,11> 1 0_0402_5% PM_EXTTS#1 XDP_DBRESET# 10K_0402_5% 2 10K_0402_5% C 2 51_0402_5% @ XDP_TRST# R856 1 2 51_0402_1% 2 51_0402_5% R859 @ 1 2 1K_0402_5% +3VS CHECK INTEL DOCUMENT #385422 Debug Port Design Guide Rev1.3 IC,AUB_CFD_rPGA,R1P0 Address:100_1100 2 R862 750_0402_1% B 2 1 2 R861 <16,19,30,31> BUF_PLT_RST# JTAG & BPM 2 <15> H_PM_SYNC 2 PWR MANAGEMENT +1.5V 68_0402_5% CLK_CPU_BCLK CLK_CPU_BCLK# F6 AL1 AM1 AN1 SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] C +VCCP A16 B16 BCLK_ITP BCLK_ITP# SM_DRAMRST# DDR3 MISC 1 R833 MISC 20_0402_1% B +5VS FAN1 Conn C8641 2 10U_0805_10V4Z +5VS U41 EN_FAN1 GND GND GND GND 8 7 6 5 1 VEN VIN VO VSET @ D34 1SS355TE-17_SOD323-2 G990P11U_SO8 C865 2200P_0402_50V7K D35 1 2 @ BAS16_SOT23-3 +3VS 1 FAN +5VS DROOP 2 1 2 3 4 2 <37> +VCC_FAN1 +VCC_FAN1 EN_FAN1 R8631 2 100_0402_5% 1 2 R864 10K_0402_5% <37> FAN_SPEED1 C868 1000P_0402_50V7K C8661 2 1U_0603_10V4Z C8671 2 0.1U_0402_16V4Z 40mil +VCC_FAN1 +VCC_FAN1 JP1 1 2 A 1 2 3 1 2 3 4 5 GND GND A ME@E&T_3801-F03N-01R Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Clarksfiel(1/5)-Thermal/XDP Size Document Number Custom Rev 0.2 NIWBA_LA5371P Date: Sheet Tuesday, March 24, 2009 1 5 of 52 5 ： 4 3 2 1 Layout rule trace length < 0.5" JCPU1A <15> <15> <15> <15> DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 B24 D23 B23 A22 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] <15> <15> <15> <15> DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 D24 G24 F23 H23 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] <15> <15> <15> <15> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 D25 F24 E23 G23 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] <15> <15> <15> <15> <15> <15> <15> <15> FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 <15> <15> <15> <15> <15> <15> <15> <15> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 E22 D21 D19 D18 G21 E19 F21 G18 FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 D22 C21 D20 C18 G22 E20 F20 G19 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] <15> FDI_FSYNC0 <15> FDI_FSYNC1 FDI_FSYNC0 FDI_FSYNC1 F17 E17 FDI_FSYNC[0] FDI_FSYNC[1] <15> FDI_INT FDI_INT C17 FDI_INT <15> FDI_LSYNC0 <15> FDI_LSYNC1 FDI_LSYNC0 FDI_LSYNC1 F18 D17 FDI_LSYNC[0] FDI_LSYNC[1] B26 A26 B27 A25 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 EXP_ICOMPI 1 R865 2 49.9_0402_1% EXP_RBIAS 1 R866 2 750_0402_1% PCIE_CRX_GTX_N[0..15] PCIE_CRX_GTX_N15 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P15 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P0 PCIE_CTX_GRX_C_N15 PCIE_CTX_GRX_C_N14 PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_C_N12 PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_C_N10 PCIE_CTX_GRX_C_N9 PCIE_CTX_GRX_C_N8 PCIE_CTX_GRX_C_N7 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N0 PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_C_P14 PCIE_CTX_GRX_C_P13 PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_C_P11 PCIE_CTX_GRX_C_P10 PCIE_CTX_GRX_C_P9 PCIE_CTX_GRX_C_P8 PCIE_CTX_GRX_C_P7 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P0 <19> +V_DDR_CPU_REF0 +V_DDR_CPU_REF1 PCIE_CRX_GTX_P[0..15] CFG3 CFG4 PCIE Lane Numbers Reversed CFG3-PCI Express Static Lane Reversal @ R867 1 2 3.01K_0402_1% C885 C886 C887 C888 C889 C890 C891 C892 C893 C894 C895 C896 C897 C898 C899 C900 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K PCIE_CTX_GRX_N15 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N[0..15] <19> R871 0_0402_5% @ 1 2 @ 1 2 PCIE_CTX_GRX_P[0..15] R872 0_0402_5% <19> CFG Straps for PROCESSOR CFG0 1 2 R873@ 3.01K_0402_1% IC,AUB_CFD_rPGA,R1P0 PCI-Express Configuration Select 1: Single PEG 0: Bifurcation enabled CFG0 Not applicable for Clarksfield Processor CFG[1:0] R870 1 DIS@ 2 1K_0402_5% FDI_FSYNC1 R930 1 DIS@ 2 1K_0402_5% FDI_INT R943 1 DIS@ 2 1K_0402_5% FDI_LSYNC0 R990 1 DIS@ 2 1K_0402_5% FDI_LSYNC1 R991 1 DIS@ 2 1K_0402_5% H_RSVD17_R H_RSVD18_R AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 CFG3 RSVD15 RSVD16 A20 B20 RSVD17 RSVD18 U9 T9 RSVD19 RSVD20 AC9 AB9 RSVD21 RSVD22 RSVD32 RSVD33 AJ13 AJ12 RSVD34 RSVD35 AH25 AK26 RSVD36 RSVD_NCTF_37 AL26 AR2 RSVD38 RSVD39 AJ26 AJ27 RSVD_NCTF_40 RSVD_NCTF_41 AP1 AT2 RSVD_NCTF_42 RSVD_NCTF_43 AT3 AR1 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 E15 F15 A2 D15 C15 AJ15 AH15 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 RSVD_NCTF_23 RSVD_NCTF_24 J29 J28 RSVD26 RSVD27 A34 A33 RSVD_NCTF_28 RSVD_NCTF_29 C35 B35 RSVD_NCTF_30 RSVD_NCTF_31 VSS 11=1*16 PEG 10=2*8 PEG 1 R874 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 B19 A19 C1 A3 B FDI_FSYNC0 CFG7 FOR ES1 SAMPLE ONLY VGA@ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREF SB_DIMM_VREF RSVD11 RSVD12 RSVD13 RSVD14 <19> CFG0 C869 C870 C871 C872 C873 C874 C875 C876 C877 C878 C879 C880 C881 C882 C883 C884 AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 RESERVED DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] PCI EXPRESS -- GRAPHICS A24 C23 B22 A21 Intel(R) FDI C DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI D <15> <15> <15> <15> JCPU1E PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS D C R868 0_0402_5% @ RSVD64_R 2 RSVD65_R 2 @ R869 0_0402_5% 1 1 B AP34 IC,AUB_CFD_rPGA,R1P0 2 3.01K_0402_1% CFG3-PCI Express Static Lane Reversal 1: Normal Operation CFG3 0: Lane Numbers Reversed 15 -> 0, 14 ->1, ..... CFG4 R875 @ 1 2 3.01K_0402_1% CFG4-Display Port Presence 1: Disabled; No Physical Display Port attached to Embedded Display Port CFG4 0: Enabled; An external Display Port device is connected to the Embedded Display Port A A Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Clarksfiel(2/5)-DMI/PEG/FDI Size Document Number Custom Rev 0.2 NIWBA_LA5371P Date: Sheet Tuesday, March 24, 2009 1 6 of 52 5 4 3 2 1 JCPU1D JCPU1C <10> DDR_A_D[0..63] C B A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 <10> DDR_A_BS0 <10> DDR_A_BS1 <10> DDR_A_BS2 AC3 AB2 U7 <10> DDR_A_CAS# <10> DDR_A_RAS# <10> DDR_A_WE# AE1 AB3 AE9 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# AA6 AA7 P7 M_CLK_DDR0 <10> M_CLK_DDR#0 <10> DDR_CKE0_DIMMA <10> SA_CK[1] SA_CK#[1] SA_CKE[1] Y6 Y5 P6 M_CLK_DDR1 <10> M_CLK_DDR#1 <10> DDR_CKE1_DIMMA <10> SA_CS#[0] SA_CS#[1] AE2 AE8 DDR_CS0_DIMMA# <10> DDR_CS1_DIMMA# <10> SA_ODT[0] SA_ODT[1] AD8 AF9 M_ODT0 <10> M_ODT1 <10> B9 D7 H7 M7 AG6 AM7 AN10 AN13 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C9 F8 J9 N9 AH7 AK9 AP11 AT13 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] C8 F9 H9 M9 AH8 AK10 AN11 AR13 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] DDR SYSTEM MEMORY A DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 <11> DDR_B_D[0..63] SA_CK[0] SA_CK#[0] SA_CKE[0] DDR_A_DM[0..7] DDR_A_DQS#[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15] DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 <10> <10> <10> <10> B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] <11> DDR_B_BS0 <11> DDR_B_BS1 <11> DDR_B_BS2 AB1 W5 R7 SB_BS[0] SB_BS[1] SB_BS[2] <11> DDR_B_CAS# <11> DDR_B_RAS# <11> DDR_B_WE# AC5 Y7 AC6 SB_CAS# SB_RAS# SB_WE# SB_CK[0] SB_CK#[0] SB_CKE[0] W8 W9 M3 M_CLK_DDR2 <11> M_CLK_DDR#2 <11> DDR_CKE2_DIMMB <11> SB_CK[1] SB_CK#[1] SB_CKE[1] V7 V6 M2 M_CLK_DDR3 <11> M_CLK_DDR#3 <11> DDR_CKE3_DIMMB <11> SB_CS#[0] SB_CS#[1] AB8 AD6 DDR_CS2_DIMMB# <11> DDR_CS3_DIMMB# <11> SB_ODT[0] SB_ODT[1] AC7 AD1 M_ODT2 <11> M_ODT3 <11> SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] D4 E1 H3 K1 AH1 AL2 AR4 AT8 DDR_B_DM[0..7] DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 D <11> C DDR SYSTEM MEMORY - B D SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D5 F4 J4 L4 AH2 AL4 AR5 AR8 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C5 E3 H4 M5 AG2 AL5 AP5 AR7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_DQS#[0..7] <11> DDR_B_DQS[0..7] <11> DDR_B_MA[0..15] <11> B IC,AUB_CFD_rPGA,R1P0 IC,AUB_CFD_rPGA,R1P0 A A Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Clarksfiel(3/5)-DDR III Size Document Number Custom Rev 0.2 NIWBA_LA5371P Date: Sheet Tuesday, March 24, 2009 1 7 of 52 5 4 3 2 1 R876 1 1K_0402_5% GFX_IMON_R 2 VTT0(1.1V) = 7*0805 22uf edge caps AS NO CONNECT +GFX_CORE 3*330uf/6m ohm 1*330uf JCPU1G C275 UMA@ 2 2 1 C271 UMA@ 2 1 2 AR25 GFX_VR_EN 1 AT25 AM24 GFX_IMON_R 2 R314 2 1.1V <51> SENSE LINES IMVP_IMON <51> B15 A15 2 1 2 1 2 1 2 1 2 1 2 B 1 R878 1 R879 2 2 1*0805 1uf 1*0805 22uf CPU VTT_SENSE VSS_SENSE_VTT AN35 AJ34 VCC_SENSE AJ35 VSS_SENSE 1 VCCPLL(1.8V) = 1*0805 22uf H_VTTVID1 = High, 1.05V FOR Auburndale VCC_SENSE VSS_SENSE VDDQ(SO DIMM) = 14*0402 1uf (7*0402 PER CONNECTOR) VTT_SELECT <49> H_VTTVID1 = Low, 1.1V FOR Clarksfiel ISENSE C C938 4.7U_0603_6.3V6K G15 VTT_SELECT 2*0805 22uf TOTAL 3*330uf FOR 2 SO-DIMMs +1.8VS 2 IC,AUB_CFD_rPGA,R1P0 2 VDDQ(CPU) = 5*0402 1uf C937 10U_0805_10V4K 1.8V 1 1 PROC_DPRSLPVR 2 1 +VCCP C936 2.2U_0603_6.3V4Z CPU VIDS 0.6A <51> 2 0_0402_5% 2 1 +VCCP C935 1U_0603_10V4Z POWER H_VID[0..6] H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PM_DPRSLPVR_R 1 R877 GFXVR_EN <50> GFXVR_DPRSLPVR <50> GFXVR_IMON <50> C914 1U_0603_10V4Z L26 L27 M26 2 1 1 C934 1U_0603_10V4Z VTT_SELECT <51> 2 PEG & DMI VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 PSI# 2 1 C931 10U_0805_10V4K AN33 2 1 C930 10U_0805_10V4K PSI# 1 C929 10U_0805_10V4K 2 C928 10U_0805_10V4K 1 UMA@ C933 10U_0805_10V4K VCCPLL1 VCCPLL2 VCCPLL3 2 1 2 VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 2 4.7K_0402_5% 1 C927 10U_0805_10V4K J22 J20 J18 H21 H20 H19 + 2 C932 10U_0805_10V4K VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 1 2 1 C926 10U_0805_10V4K P10 N10 L10 K10 2 1 C921 10U_0805_10V4K VTT0_59 VTT0_60 VTT0_61 VTT0_62 1 +VCCP K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 0_0402_5% C913 1U_0603_10V4Z 3A VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 C920 10U_0805_10V4K VTT1_45 VTT1_46 VTT1_47 R91 GFX_VR_EN UMA@ GFX_VR_EN GFX_DPRSLPVR GFX_IMON C919 330U_B2_2.5VM_R15M 2 J24 J23 H25 FDI 2 1 C925 10U_0805_10V4K 2 1 C924 10U_0805_10V4K 2 1 C923 10U_0805_10V4K 1 C922 10U_0805_10V4K AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 <50> <50> <50> <50> <50> <50> <50> +1.5V +VCCP VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 DESIGN GUIDE REV1.1 D GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 C912 1U_0603_10V4Z 2 GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] AM22 AP22 AN22 AP23 AM23 AP24 AN24 (~15MW) MAYBE WASTED VCC_AXG_SENSE <50> VSS_AXG_SENSE <50> C911 1U_0603_10V4Z 2 1 AR22 AT22 C910 1U_0603_10V4Z 2 1 C918 10U_0805_10V4K 1 15A VAXG_SENSE VSSAXG_SENSE - 1.5V RAILS C279 UMA@ 1 DDR3 2 1 +VCCP C917 10U_0805_10V4K 1.1V RAIL POWER 2 C916 10U_0805_10V4K 2 1 C915 10U_0805_10V4K 1 2 C644 UMA@ 1 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 GRAPHICS 2 2 C270 @ 1 R313 0_0402_5% DIS@ C909 10U_0805_10V4K 2 1 2 C274 @ 1 AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 10U_0805_6.3V6M C908 10U_0805_10V4K @ 1 2 C278 @ 2 C904 10U_0805_10V4K 2 2 1 C907 10U_0805_10V4K 2 @ 1 C906 10U_0805_10V4K 1 2 1 C902 10U_0805_10V4K 2 1 C901 10U_0805_10V4K 1 C905 10U_0805_10V4K A VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 C600 @ 1 BUT A SMALL AMOUNT OF POWER 10U_0805_6.3V6M +VCCP CPU CORE SUPPLY B VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 C903 10U_0805_10V4K C AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 +VCCP 18A 48A D 1 22U_0805_6.3V6M 22U_0805_6.3V6M SENSE LINES 22U_0805_6.3V6M GRAPHICS VIDs 8*0805 10uf JCPU1F POWER +CPU_CORE DIS@ under cavity 0_0402_5% VCCSENSE VSSSENSE 0_0402_5% 1*0603 4.7uf VCCSENSE <51> VSSSENSE <51> VTT_SENSE <49> @ PAD T81 A Close to CPU VCCSENSE VSSSENSE 1 R880 1 R881 +CPU_CORE Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. IC,AUB_CFD_rPGA,R1P0 5 Compal Secret Data Security Classification 2 100_0402_1% 2 100_0402_1% 4 3 2 Title Compal Electronics, Inc. Clarksfiel(4/5)-PWR Size Document Number Custom Rev 0.2 NIWBA_LA5371P Date: Sheet Tuesday, March 24, 2009 1 8 of 52 5 4 3 2 CPU CORE +CPU_CORE 2 1 2 1 2 C950 22U_0805_6.3V6M 2 1 C949 22U_0805_6.3V6M 2 1 C948 22U_0805_6.3V6M 2 1 C947 22U_0805_6.3V6M 2 1 C946 22U_0805_6.3V6M 2 1 C945 22U_0805_6.3V6M 2 1 C944 22U_0805_6.3V6M 2 1 C943 22U_0805_6.3V6M 2 1 C942 22U_0805_6.3V6M 2 1 Inside cavity D 1 2 + 2 1 2 1 2 1 2 1 2 C974 22U_0805_6.3V6M 2 1 C973 22U_0805_6.3V6M + C972 22U_0805_6.3V6M 2 1 C971 22U_0805_6.3V6M + C970 470U_D2_2VM_R4.5M 1 C969 470U_D2_2VM_R4.5M 2 between Inductor and socket C968 470U_D2_2VM_R4.5M + C967 470U_D2_2VM_R4.5M 1 C959 10U_0805_6.3V6M 2 2 C958 10U_0805_6.3V6M 2 1 1 C966 10U_0805_6.3V6M 1 2 C957 10U_0805_6.3V6M 2 2 1 C965 10U_0805_6.3V6M 2 1 1 C956 10U_0805_6.3V6M 1 2 C964 10U_0805_6.3V6M 2 2 1 C955 10U_0805_6.3V6M 1 1 C963 10U_0805_6.3V6M 2 2 C962 10U_0805_6.3V6M 2 1 C961 10U_0805_6.3V6M 1 2 1 C954 10U_0805_6.3V6M 2 1 C953 10U_0805_6.3V6M 1 C952 10U_0805_6.3V6M IC,AUB_CFD_rPGA,R1P0 470uF 4.5mohm Under cavity VSS C +CPU_CORE = 12*0805 22uf NCTF VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 C941 22U_0805_6.3V6M 1 K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 C960 10U_0805_6.3V6M B VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 C951 10U_0805_6.3V6M C VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 C940 22U_0805_6.3V6M D JCPU1I AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 C939 22U_0805_6.3V6M JCPU1H AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 1 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 AT1 AR34 B34 B2 B1 A35 7*0805 10uf VSS_NCTF1_R VSS_NCTF2_R VSS_NCTF3_R VSS_NCTF4_R VSS_NCTF5_R VSS_NCTF6_R VSS_NCTF7_R INSIDE CAVITY UNDER CAVITY AND 9*0805 10uf BETWEEN INDUCTOR AND SOCKET ON TOP LAYER 4*470uf/4m ohm 2*470uf B IC,AUB_CFD_rPGA,R1P0 A A Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Clarksfiel(5/5)-GND/Bypass Size Document Number Custom Rev 0.2 NIWBA_LA5371P Date: Sheet Tuesday, March 24, 2009 1 9 of 52 5 4 +1.5V <7> DDR_A_D[0..63] JDDR1 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 C DDR_CKE0_DIMMA <7> DDR_CKE0_DIMMA DDR_A_BS2 <7> DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 <7> M_CLK_DDR0 <7> M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#0 <7> DDR_A_BS0 DDR_A_MA10 DDR_A_BS0 <7> DDR_A_WE# <7> DDR_A_CAS# DDR_A_WE# DDR_A_CAS# <7> DDR_CS1_DIMMA# DDR_A_MA13 DDR_CS1_DIMMA# B DDR_A_D34 DDR_A_D35 1 2 M2@ 1 1U_0603_10V4Z X5R DDR_A_D28 DDR_A_D29 1 VDD RH 6 2 GND RW 5 3 DDR_A_DQS#3 DDR_A_DQS3 SCL SDA <11,14> SMBCLK <11,14> SMBDATA SMBCLK 3 2 R888 M2@ 12.1k_0402_1% I2C address 5Ch SMBDATA + 1 O - C978 M2@ 1U_0603_10V4Z X5R 1 U43A M2@ LM393M_SO8 +V_DDR_M2_REF0 +VREF_OPAMP_POT0 DDR_CKE1_DIMMA 2 DDR_CKE1_DIMMA <7> C979 C DDR_A_MA15 DDR_A_MA14 1U_0603_10V4Z X5R 1 @ DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 M_ODT1 M_CLK_DDR1 <7> M_CLK_DDR#1 <7> DDR_A_BS1 <7> DDR_A_RAS# <7> DDR_CS0_DIMMA# <7> M_ODT0 <7> M_ODT1 <7> V_DDR_CPU_REF Layout Note: Place near DIMM DDR_A_D36 DDR_A_D37 1 DDR_A_DM4 2 DDR_A_D38 DDR_A_D39 1 2 B +1.5V 2 2 2 2 2 6*0603 10uf (PER CONNECTOR) DDR_A_DM6 1 2 1 2 1 2 1 2 C993 0.1U_0402_10V6K 2 1 C992 0.1U_0402_10V6K 2 1 C991 0.1U_0402_10V6K 2 1 C990 0.1U_0402_10V6K 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs) DDR_A_D52 DDR_A_D53 @ 1 C989 @ 1 10U_0603_6.3V6M DDR_A_D46 DDR_A_D47 1 C988 VDDQ(1.5V) = 1 10U_0603_6.3V6M 1 C987 DDR_A_DQS#5 DDR_A_DQS5 10U_0603_6.3V6M DDR_A_D44 DDR_A_D45 1 + C994 220U_B_2.5VM_R35M 2 VTT(0.75V) = DDR_A_D54 DDR_A_D55 3*0805 10uf 4*0402 1uf VREF = DDR_A_D60 DDR_A_D61 1*0402 0.1uf DDR_A_DQS#7 DDR_A_DQS7 VDDSPD (3.3V)= 2 2 2 1 2 C1000 PM_EXTTS#1_R <5,11> SMB_DATA_S3 <11,12,14,30> SMB_CLK_S3 <11,12,14,30> 1 +0.75VS 1 2 10U_0603_6.3V6M PM_EXTTS#1_R SMB_DATA_S3 SMB_CLK_S3 1 1U_0603_10V4Z 1 1U_0603_10V4Z 1*0402 2.2uf C999 1*0402 0.1uf DDR_A_D62 DDR_A_D63 +0.75VS 1*0402 2.2uf A 0.65A@0.75V 206 2 TYCO_2-2013289-1 Compal Secret Data Security Classification Issued Date TOP SLOT 5 4 ISL90727WIE627Z-TK_SC70-6 M2@ DDR_A_D30 DDR_A_D31 2 VREF_RW_POT0 10U_0603_6.3V6M 1 DDR_A_D22 DDR_A_D23 C998 G2 D +3VALW C986 G1 U42 C997 205 +V_DDR_CPU_REF R886 1K_0402_1% R887 M2@ 12.1k_0402_1% C977 1U_0603_10V4Z 2 2 DDR_A_DM2 C996 2 1 R890 10K_0402_5% 1 C1003 0.1U_0402_10V6K A C1002 2.2U_0603_6.3V4Z +3VS +V_DDR_CPU_REF0 +1.5V DDR_A_D20 DDR_A_D21 1U_0603_10V4Z DDR_A_D58 DDR_A_D59 1 R889 2 10K_0402_5% +1.5V 10U_0603_6.3V6M DDR_A_DM7 +3VALW C985 DDR_A_D56 DDR_A_D57 2 0_0402_5% M3@ R883 1K_0402_1% DRAMRST# <5,11> DDR_A_D14 DDR_A_D15 C984 DDR_A_D50 DDR_A_D51 1 R885 10U_0603_6.3V6M DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DM1 DRAMRST# C983 DDR_A_D48 DDR_A_D49 2 0_0402_5% M2@ +V_DDR_M2_REF0 DDR_A_D12 DDR_A_D13 10U_0603_6.3V6M DDR_A_D42 DDR_A_D43 DDR_A_D6 DDR_A_D7 C982 DDR_A_DM5 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_DQS#0 DDR_A_DQS0 10U_0603_6.3V6M DDR_A_D40 DDR_A_D41 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 <7> DDR_A_MA[0..15] C981 2.2U_0603_6.3V4Z DDR_A_DQS#4 DDR_A_DQS4 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 1 R884 <7> DDR_A_DQS#[0..7] C980 0.1U_0402_10V6K DDR_A_D32 DDR_A_D33 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 V_DDR_CPU_REF 2 0_0402_5% M1@ 8 DDR_A_D10 DDR_A_D11 1 R882 P DDR_A_DQS#1 DDR_A_DQS1 <7> DDR_A_DQS[0..7] DDR_A_D4 DDR_A_D5 G DDR_A_D8 DDR_A_D9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 4 DDR_A_D2 DDR_A_D3 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 +1.5V 2 2 DDR_A_DM0 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 1 1 C976 2.2U_0603_6.3V4Z 2 D C975 0.1U_0402_10V6K 1 DDR_A_D0 DDR_A_D1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 +V_DDR_CPU_REF +VREF_DQ_DIMMA <7> DDR_A_DM[0..7] 1 DDR3 SO-DIMM A 2 3A@1.5V +VREF_DQ_DIMMA 1 2 +1.5V 2 1 +VREF_DQ_DIMMA 3 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title Compal Electronics, Inc. DDRIII-SODIMM SLOT1 Size Document Number Custom Rev 0.2 NIWBA_LA5371P Date: Sheet Tuesday, March 24, 2009 1 10 of 52 5 4 +1.5V 3A@1.5V +VREF_DQ_DIMMB 3 +1.5V 2 1 <7> DDR_B_DQS#[0..7] <7> DDR_B_D[0..63] <7> DDR_B_DM[0..7] JDDR2 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_DM3 DDR_B_D26 DDR_B_D27 <7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB <7> DDR_B_BS2 DDR_B_BS2 C DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 <7> M_CLK_DDR2 <7> M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#2 <7> DDR_B_BS0 DDR_B_MA10 DDR_B_BS0 <7> DDR_B_WE# <7> DDR_B_CAS# DDR_B_WE# DDR_B_CAS# <7> DDR_CS3_DIMMB# DDR_B_MA13 DDR_CS3_DIMMB# 6 RW 5 3 SCL SDA 4 SMBCLK <10,14> SMBCLK R895 M2@ 12.1k_0402_1% DDR_B_D30 DDR_B_D31 I2C address 7Ch SMBDATA <10,14> SMBDATA CAP 1UF OVERPAGE VREF_RW_POT1 ISL90728WIE627Z-TK_SC70-6 M2@ DDR_B_DQS#3 DDR_B_DQS3 5 + 6 - O 7 U43B M2@ LM393M_SO8 +V_DDR_M2_REF1 +VREF_OPAMP_POT1 2 C1008 1U_0603_10V4Z X5R 1 M2@ DDR_B_MA15 DDR_B_MA14 C DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 M_ODT3 M_CLK_DDR3 <7> M_CLK_DDR#3 <7> DDR_B_BS1 <7> DDR_B_RAS# <7> Layout Note: Place near DIMM DDR_CS2_DIMMB# <7> M_ODT2 <7> M_ODT3 <7> V_DDR_CPU_REF +VREF_CA DDR_B_D36 DDR_B_D37 1 DDR_B_D46 DDR_B_D47 @ 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C1022 0.1U_0402_10V6K DDR_B_DQS#5 DDR_B_DQS5 2 1 C1021 0.1U_0402_10V6K @ DDR_B_D44 DDR_B_D45 1 C1020 0.1U_0402_10V6K 2 C1017 2 DDR_B_D38 DDR_B_D39 +1.5V C1019 0.1U_0402_10V6K DDR_B_DM4 1 10U_0603_6.3V6M 206 208 DDR_CKE3_DIMMB <7> C1016 BOSS1 BOSS2 DDR_CKE3_DIMMB 10U_0603_6.3V6M 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 C1015 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT B VDDQ(1.5V) = 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs) 6*0603 10uf (PER CONNECTOR) DDR_B_D52 DDR_B_D53 DDR_B_DM6 3*0805 10uf DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 Layout Note: Place near DIMM VTT(0.75V) = 4*0402 1uf 1*0402 0.1uf DDR_B_DQS#7 DDR_B_DQS7 +0.75VS 1*0402 2.2uf VDDSPD (3.3V)= 1*0402 0.1uf 1*0402 2.2uf DDR_B_D62 DDR_B_D63 1 PM_EXTTS#1_R SMB_DATA_S3 SMB_CLK_S3 0.65A@0.75V PM_EXTTS#1_R <5,10> SMB_DATA_S3 <10,12,14,30> SMB_CLK_S3 <10,12,14,30> +0.75VS 2 1 2 1 2 1 2 A TYCO_2-2013310-1_204P CONN@ Compal Secret Data Security Classification Issued Date BOT SLOT 5 RH GND 10U_0603_6.3V6M GND1 GND2 +3VALW C1026 1U_0603_10V4Z 2 205 207 VDD 2 C1025 1U_0603_10V4Z 2 1 1 R896 2 10K_0402_5% 1 2 R897 10K_0402_5% DDR_B_D28 DDR_B_D29 1 C1024 1U_0603_10V4Z 1 C1028 0.1U_0402_10V6K A C1027 2.2U_0603_6.3V4Z +3VS DDR_B_D22 DDR_B_D23 C1023 1U_0603_10V4Z DDR_B_D58 DDR_B_D59 M2@ 1 1U_0603_10V4Z X5R C1014 DDR_B_DM7 DDR_B_DM2 10U_0603_6.3V6M DDR_B_D56 DDR_B_D57 D R894 M2@ 12.1k_0402_1% 10U_0603_6.3V6M DDR_B_D50 DDR_B_D51 +V_DDR_CPU_REF1 +1.5V U44 C1013 DDR_B_DQS#6 DDR_B_DQS6 2 M3@ 0_0402_5% C1006 10U_0603_6.3V6M DDR_B_D48 DDR_B_D49 2 C1012 DDR_B_D42 DDR_B_D43 DDR_B_D20 DDR_B_D21 C1011 DDR_B_DM5 1 R893 DDR_B_D14 DDR_B_D15 10U_0603_6.3V6M DDR_B_D40 DDR_B_D41 2 M2@ 0_0402_5% +1.5V C1010 DDR_B_D34 DDR_B_D35 +3VALW DRAMRST# <5,10> 10U_0603_6.3V6M B DDR_B_DM1 DRAMRST# C1018 2.2U_0603_6.3V4Z DDR_B_DQS#4 DDR_B_DQS4 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT 1 R892 +V_DDR_M2_REF1 DDR_B_D12 DDR_B_D13 C1009 0.1U_0402_10V6K DDR_B_D32 DDR_B_D33 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_B_D6 DDR_B_D7 2 M1@ 0_0402_5% 8 DDR_B_D16 DDR_B_D17 <7> DDR_B_MA[0..15] DDR_B_DQS#0 DDR_B_DQS0 P DDR_B_D10 DDR_B_D11 +V_DDR_CPU_REF R891 1 G DDR_B_DQS#1 DDR_B_DQS1 +VREF_DQ_DIMMB <7> DDR_B_DQS[0..7] DDR_B_D4 DDR_B_D5 4 DDR_B_D8 DDR_B_D9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 2 DDR_B_D2 DDR_B_D3 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 1 2 DDR_B_DM0 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 2 DDR_B_D0 DDR_B_D1 1 C1005 C1004 2 0.1U_0402_10V6K 2.2U_0603_6.3V4Z D 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 1 +VREF_DQ_DIMMB 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title Compal Electronics, Inc. DDRIII-SODIMM SLOT2 Size Document Number Rev 0.2 NIWBA_LA5371P Date: Tuesday, March 24, 2009 Sheet 1 11 of 52 5 CLK GEN TO VGA 1. CLK_DMI 1. 27M_CLK 2. CLK_BUF_BCLK 1. 27M_CLK_SS +3VS_CK505 4. CLK_BUF_DOT96 R898 CLK_BUF_DOT96 1 CLK_BUF_DOT96# 1 R900 27M_CLK R901 1 27M_CLK_SS R902 1 <14> CLK_BUF_DOT96 <14> CLK_BUF_DOT96# <19> 27M_CLK <19> 27M_CLK_SS CLK_BUF_CKSSCD CLK_BUF_CKSSCD# <14> CLK_BUF_CKSSCD <14> CLK_BUF_CKSSCD# CLK_DMI CLK_DMI# <14> CLK_DMI <14> CLK_DMI# +3VS_CK505 +1.05VS_CK505 U45 0_0402_5% 2 2 L_CLK_BUF_DOT96 L_CLK_BUF_DOT96# 0_0402_5% 2 33_0402_1%27M_CLK_L 2 33_0402_1%27M_CLK_SS_L CLK_48M_CR_R CLOSE U5 R905 R906 1 1 R907 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 0_0402_5% L_CLK_DMI L_CLK_DMI# 2 0_0402_5% CPU_STOP# 2 10K_0402_5% +3VS_CK505 VDD_DOT VSS_DOT DOT_96 DOT_96# VDD_27 27MHZ 27MHZ_SS VSS_27 VSS_SATA SRC_1/SATA SRC_1#/SATA# VSS_SRC SRC_2 SRC_2# VDD_SRC_IO CPU_STOP# SLG8SP585VTR_QFN32_5X5 SMB_CLK_S3 SMB_DATA_S3 REF_0/CPU_SEL VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO VDD_SRC 24 23 22 21 20 19 18 17 R903 R_CLK_BUF_BCLK 1 R_CLK_BUF_BCLK# 1 R904 2 1 R899 CLK_14M_PCH 33_0402_1% SMB_CLK_S3 <10,11,14,30> SMB_DATA_S3 <10,11,14,30> CLK_14M_PCH <14> CLK_XTAL_IN CLK_XTAL_OUT CK_PWRGD 0_0402_5% 2 CLK_BUF_BCLK 2 CLK_BUF_BCLK# 0_0402_5% CK_PWRGD CLK_BUF_BCLK <14> CLK_BUF_BCLK# <14> R908 1 2 +3VS_CK505 C D S IC ICS9LRS3199AKLFT MLF 32P CLK GEN (SA000030P00) 2 G 2 R909 2 1 2 CLK_EN# <51> 3 Q60 S 2N7002_SOT23-3 C1033 0.1U_0402_10V6K 2 1 C1032 0.1U_0402_10V6K 2 1 C1031 0.1U_0402_10V6K 1 C1030 10U_0805_10V4K C1029 10U_0805_10V4K 2 <33> CLK_48M_CR CLK_48M_CR_R 2 2 R910 0_0402_5% 1 0_0402_5% 1 R911 @ PIN8 IS GND FOR ICS3197 PIN8 IS 48MHz FOR ICS3199 +3VS_CK505 C1034 2 1 PCS CAP(0.1u) BY 1 INPUT PIN 2 1 2 C1041 0.1U_0402_10V6K 2 1 C1040 0.1U_0402_10V6K 2 1 C1039 0.1U_0402_10V6K 2 1 C1038 0.1U_0402_10V6K 2 1 C1037 0.1U_0402_10V6K 2 1 C1036 10U_0805_10V4K 1 C1035 10U_0805_10V4K 2 R912 C1042 CLK_14M_PCH 1 @ 10P_0402_50V8J 2 @ 1 14.31818MHZ_16PF_DSX840GA +3VS B 32 31 30 29 28 27 26 25 +1.05VS_CK505 1 1 0_0603_5% SCL SDA REF_0/CPU_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF CKPWRGD/PD# 10K_0402_5% 1 PCS CAP(0.1u) BY 1 INPUT PIN 1 0_0603_5% +1.05VS_CK505 1 +1.05VS C 1 D 3. CLK_BUF_CKSSCD 5. CLK_14M_PCH 2 TGND CLK GEN TO PCH 3 33 D 4 REF_0/CPU_SEL 10P_0402_50V8J EMI Capacitor C1043 33P_0402_50V8J CLK_XTAL_OUT CLK_XTAL_IN Y6 2 B 1 2 2 1 1 C1044 33P_0402_50V8J +1.05VS PIN 30 CPU_0 CPU_1 0 (Default) 133MHz 133MHz 1 100MHz 100MHz 1 R913 2 @ 10K_0402_5% 1 R914 2 10K_0402_5% REF_0/CPU_SEL A A Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. CLOCK GENERATOR Size Document Number Rev 0.2 NIWBA_LA5371P Date: Tuesday, March 24, 2009 Sheet 1 12 of 52 5 4 3 2 1 PCH_RTCX1 D 2 U46A <35> HDA_BITCLK_CODEC PCH_SPKR 2 1K_0402_5% PCH_INTVRMEN A14 INTVRMEN 1 2 33_0402_5% BITCLK A30 HDA_BCLK R923 1 2 33_0402_5% HDA_SYNC D29 HDA_SYNC R925 1 2 33_0402_5% PCH_SPKR P1 HDA_RST# C30 HDA_SDIN0 G30 HDA_SDIN0 HDA_SDIN1 <35> HDA_SDIN1 R926 1 <35> HDA_SDOUT_CODEC 2 33_0402_5% GPIO33 = GPO , internal pull-up,should not be pulled low R927 1 R928 1 <37> ME_FLASH flash ME core of strap pin pull down R929 1 +3VALW HDA_SDIN1 HDA_SDIN2 F32 HDA_SDIN3 B29 HDA_SDO 2 100K_0402_5% 0_0402_5% 2 H32 HDA_DOCK_EN# / GPIO33 GPIO13 J30 HDA_DOCK_RST# / GPIO13 HDA_SDOUT GPIO13 = GPI,3.3V,SUS PCH_JTAG_TCK M3 JTAG_TCK PCH_JTAG_TMS K3 JTAG_TMS PCH_JTAG_TDI K1 JTAG_TDI PCH_JTAG_TDO J2 JTAG_TDO PCH_JTAG_RST# J4 TRST# AB9 SERIRQ 1 PAD SPI_CLK_PCH_R BA2 SPI_CLK SPI_SB_CS0# AV3 SPI_CS0# AY3 SPI_CS1# 1 SATA0RXN SATA0RXP SATA0TXN SATA0TXP AK7 AK6 AK11 AK9 SATA_ITX_C_DRX_N0 SATA_ITX_C_DRX_P0 0.01U_0402_16V7K 0.01U_0402_16V7K SATA1RXN SATA1RXP SATA1TXN SATA1TXP AH6 AH5 AH9 AH8 SATA_ITX_C_DRX_N1 SATA_ITX_C_DRX_P1 0.01U_0402_16V7K 0.01U_0402_16V7K SATA2RXN SATA2RXP SATA2TXN SATA2TXP AF11 AF9 AF7 AF6 SATA3RXN SATA3RXP SATA3TXN SATA3TXP AH3 AH1 AF3 AF1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP AD9 AD8 AD6 AD5 SATA5RXN SATA5RXP SATA5TXN SATA5TXP AD3 AD1 AB3 AB1 SATAICOMPO AF16 SATAICOMPI AF15 +3VS SERIRQ <37,38> R922 2 2 1 C1050 1 C1051 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 SATA_ITX_DRX_N0 SATA_ITX_DRX_P0 SATA_DTX_C_IRX_N0 <34> SATA_DTX_C_IRX_P0 <34> SATA_ITX_DRX_N0 <34> SATA_ITX_DRX_P0 <34> 2 2 1 C1052 1 C1053 SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 SATA_ITX_DRX_N1 SATA_ITX_DRX_P1 SATA_DTX_C_IRX_N1 <34> SATA_DTX_C_IRX_P1 <34> SATA_ITX_DRX_N1 <34> SATA_ITX_DRX_P1 <34> C SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4 SATA_ITX_C_DRX_N4 SATA_ITX_C_DRX_P4 0.01U_0402_16V7K 0.01U_0402_16V7K R931 SATAICOMP 1 2 37.4_0402_1% 2 2 SATA_DTX_C_IRX_N4 <34> SATA_DTX_C_IRX_P4 <34> SATA_ITX_DRX_N4_CONN <34> SATA_ITX_DRX_P4_CONN <34> SATA_ITX_DRX_N4_CONN SATA_ITX_DRX_P4_CONN 1 C1054 1 C1055 +3VS +1.05VS 2 0_0402_5% PCH_JTAG_RST# 1 R936 SATALED# 2 10K_0402_5% T3 R937 10K_0402_5% +3VS SPI_SI AY1 SPI_MOSI SPI_SO_R AV1 SPI_MISO R938 10K_0402_5% DRIVE_LED# <41> GPIO21 = GPI,3.3V,CORE R942 10K_0402_5% @ 2 1 2 R941 10K_0402_1% @ 2 SERIRQ LPC_DRQ0# <38> T82 GPIO23 = NATIVE,3.3V,CORE 1 2 PCH_JTAG_TDI GPIO23 R1076 SPI_CLK_PCH R935 20K_0402_5% @ 1 1 2 1 PCH_JTAG_TMS R940 100_0402_1% @ 2 R939 100_0402_1% @ 2 2 1 1 PCH_JTAG_TDO LPC_FRAME# <37,38> A34 F34 HDA_RST# F30 2 10K_0402_5% +3VALW R934 20K_0402_5% @ R933 200_0402_5% @ 1 2 R932 200_0402_5% @ B +3VALW @ SPKR E32 C +3VALW LPC INTRUDER# RTC A16 R919 1 <35> PCH_SPKR <35> HDA_RST_CODEC# +3VALW C34 LDRQ0# LDRQ1# / GPIO23 SATA0GP / GPIO21 Y9 GPIO21 SATA1GP / GPIO19 V1 GPIO19 1 @ SM_INTRUDER# CLRP2 SHORT PADS FWH4 / LFRAME# <37,38> <37,38> <37,38> <37,38> 2 1 R924 SRTCRST# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 2 10K_0402_5% <35> HDA_SYNC_CODEC +3VS RTCRST# D17 D33 B33 C32 A32 1 0.1U_0402_16V4Z ：：Integrated VRM enable Integrated VRM disable H L 2 C14 PCH_SRTCRST# SATA * PCH_INTVRMEN PCH_RTCRST# LAD0 LAD1 LAD2 LAD3 FWH0 / FWH1 / FWH2 / FWH3 / SPI 100_0603_1% C1049 C1048 1U_0603_10V4Z 1 RTCX1 RTCX2 CLRP1 SHORT PADS IHDA R918 1 2 SM_INTRUDER# 2 B13 D13 JTAG 2 1M_0402_5% 2 330K_0402_5% 1 C1047 1U_0603_10V4Z 1 2 R920 20K_0402_1% 1 2 R921 20K_0402_1% PCH_RTCX1 PCH_RTCX2 2 +RTCVCC 1 R916 1 +RTCBATT 1 1 C1046 18P_0402_50V8J +RTCVCC R917 2 1 2 +RTCVCC X7 32.768KHZ_12.5P_1TJS125BJ2A251 2 NC 2 4 1 IN C1045 OUT 1 NC 18P_0402_50V8J D PCH_RTCX2 2 10M_0402_5% 3 1 R915 B GPIO21 GPIO19 GPIO19 = GPI,3.3V,CORE SPI_CLK_PCH 1 IBEXPEAK-M_FCBGA1071 SPI ROM on ME PCH JTAG Enable PCH JTAG Disable ES1 ES1 +3VS RefDes R104 No Install ES2 200ohm ES2 +1.05VS R108 No Install 100ohm No Install No Install PCH_JTAG_TDO R806 1 @ 2 51_0402_5% R105 200ohm 200ohm No Install No Install PCH_JTAG_TMS R807 1 @ 2 51_0402_5% R109 100ohm 100ohm No Install No Install PCH_JTAG_TDI 1 @ 2 51_0402_5% PCH_JTAG_TMS 200ohm 200ohm 20Kohm No Install R808 PCH_JTAG_RST# R809 PCH_JTAG_TDI R110 PCH_JTAG_TCK A 100ohm 100ohm R97 51ohm 51ohm R107 20Kohm 20Kohm 10Kohm 51ohm No Install PCH_JTAG_TCK R90 1 1 @ 2 51_0402_5% 2 4.7K_0402_5% 10Kohm 10Kohm 2 SPI_WP# 3.3K_0402_5% R945 1 2SPI_HOLD# 3.3K_0402_5% CRB 1.0 Change to 4.7K C1056 +3VS 1 U37 1 SPI_SO_L SPI_WP# R947 15_0402_5%51ohm No Install No Install R944 1 R946 15_0402_5% SPI_SB_CS0# 1 2 SPI_SO_R 2 PCH_JTAG_RST# R110 C748 22P_0402_50V8J @ No Install No Install PCH_JTAG_TDO R106 2 PCH Pin R572 33_0402_5% @ 1 2 3 4 CS# SO WP# GND VCC HOLD# SCLK SI 2 0.1U_0402_16V4Z 8 7 6 5 SPI_HOLD# SPI_CLK_PCH SPI_SI A MX25L1605AM2C-12G_SO8 No Install No Install FOR EVT Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. IBEX-M(1/6)-HDA/JTAG/SATA Size Document Number Custom Rev 0.2 NIWBA_LA5371P Date: Sheet Tuesday, March 24, 2009 1 13 of 52 5 4 3 2 SMB_CLK_S3 PCIE PORT LIST PORT DEVICE 1 2 3 4 5 6 7 8 NEW CARD WLAN LAN 3G X TV TUNNER X X 1 1 R948 1 R950 SMB_DATA_S3 2 10K_0402_5% 2 10K_0402_5% SMBCLK +3VS 1 R949 1 R951 1 R952 1 R953 1 R954 1 R955 1 R956 1 R957 1 R958 SMBDATA SML0CLK SML0DATA C1065 1 C1066 1 MINI1 BF33 BH33 BG32 BJ32 PERN5 PERP5 PETN5 PETP5 CR R967 1 R968 1 <30> CLK_PCIE_EXP_PCH# <30> CLK_PCIE_EXP_PCH EXP +3VALW <30> CLK_PCIE_WLAN1# <30> CLK_PCIE_WLAN1 <30> WLAN_CLKREQ1# +3VS B LAN <31> CLK_PCIE_LAN# <31> CLK_PCIE_LAN <31> CLKREQ_LAN# +3VS 3G 2 0_0402_5% 2 0_0402_5% CLK_PCIE_EXP_PCH#_R CLK_PCIE_EXP_PCH_R <30> CLK_PCIE_CARD_PCH# <30> CLK_PCIE_CARD_PCH <30> PCIECLKREQ3# +3VALW BG34 BJ34 BG36 BJ36 PERN8 PERP8 PETN8 PETP8 AK48 AK47 P9 R969 1 2 10K_0402_5% R970 1 R971 1 2 0_0402_5% CLK_PCIE_MCARD_PCH#_R AM43 2 0_0402_5% CLK_PCIE_MCARD_PCH_R AM45 TV <30> CLK_PCIE_WLAN# <30> CLK_PCIE_WLAN R973 1 2 10K_0402_5% R974 1 R976 1 2 0_0402_5% 2 0_0402_5% +3VALW AM47 AM48 N4 R977 1 2 10K_0402_5% R978 1 R979 1 2 0_0402_5% CLK_PCIE_CARD_PCH#_R 2 0_0402_5% CLK_PCIE_CARD_PCH_R R980 1 2 10K_0402_5% 2 SML1ALERT# / GPIO74 M14 GPIO74 SML1CLK / GPIO58 E10 SML1CLK R962 0_0402_5% EC_SMB_CK2 EC_SMB_CK2 <37> SML1DATA / GPIO75 G12 SML1DATA R963 0_0402_5% EC_SMB_DA2 EC_SMB_DA2 <37> CL_CLK1 T13 SML0DATA PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1# / GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P SMB_DATA_S3 SMB_CLK_S3 SMB_DATA_S3 0_0402_5% R961 SMB_DATA_S3 <10,11,12,30> GPIO74 = NATIVE,3.3V,SUS EC_THERMAL DTS , read from EC CL_DATA1 T11 CL_RST1# T9 C PEG_CLKREQ# <19> 10K_0402_5% PEG_CLKREQ# 1 H1 +3VS R964 2 +3VS GPIO47 = 10Kohm PULL DOWN CLKOUT_PEG_A_N CLKOUT_PEG_A_P AD43 AD45 CLKOUT_DMI_N CLKOUT_DMI_P AN4 AN2 CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P AT1 AT3 CLK_PCIE_VGA# CLK_PCIE_VGA +3VS CLK_PCIE_VGA# <19> CLK_PCIE_VGA <19> R965 2.2K_0402_5% CLK_EXP# <5> CLK_EXP <5> CLKOUT_DP_N CLKOUT_DP_P Q62A 6 EC_SMB_DA2 EC_SMB_CK2 AW24 BA24 CLK_DMI# <12> CLK_DMI <12> CLKIN_BCLK_N CLKIN_BCLK_P AP3 AP1 CLK_BUF_BCLK# <12> CLK_BUF_BCLK <12> CLKIN_DOT_96N CLKIN_DOT_96P F18 E18 CLK_BUF_DOT96# <12> CLK_BUF_DOT96 <12> AH13 AH12 CLK_BUF_CKSSCD# <12> CLK_BUF_CKSSCD <12> CLKIN_DMI_N CLKIN_DMI_P CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P PCIECLKRQ2# / GPIO20 AH42 AH41 A8 CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3# / GPIO25 2 10K_0402_5% R981 1 R982 1 2 0_0402_5% 2 0_0402_5% R986 1 2 10K_0402_5% GPIO26 = NATIVE,3.3V,SUS M9 AJ50 AJ52 H6 CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4# / GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P PCIECLKRQ5# / GPIO44 GPIO44 = NATIVE,3.3V,SUS R966 2.2K_0402_5% Q62B 3 SMB_EC_DA2_R 1 SMB_EC_DA2_R <19,41> 2N7002DW-T/R7_SOT363-6 Nvidia thermall sensor SMB_EC_CK2_R 4 SMB_EC_CK2_R <19,41> 2N7002DW-T/R7_SOT363-6 EC_SMB_DA2 R9720_0402_5% @ 2 1 SMB_EC_DA2_R EC_SMB_CK2 R9750_0402_5% @ 2 1 SMB_EC_CK2_R B REFCLK14IN P41 CLK_14M_PCH CLKIN_PCILOOPBACK J42 CLK_PCI_FB XTAL25_IN XTAL25_OUT AH51 AH53 XTAL25_IN XTAL25_OUT XCLK_RCOMP AF38 R983 CLK_14M_PCH <12> CLK_PCI_FB <16> PEG_B_CLKRQ# / GPIO56 2 90.9_0402_1% +1.05VS CLKOUTFLEX1 / GPIO65 P43 R987 1 CLKOUTFLEX2 / GPIO66 T42 R988 1 CLKOUTFLEX3 / GPIO67 N50 2 22_0402_5% CLK_PCI_DB <38> 2 22_0402_5% CLK_14M_SIO <38> CLK_PCI_FB R666 33_0402_5% @ 1 R667 33_0402_5% @ C809 22P_0402_50V8J @ A 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 C810 22P_0402_50V8J @ Compal Secret Data Security Classification Issued Date XTAL25_OUT 1 @ R985 CLK_14M_PCH 2 1M_0402_5% @ Y8 1 IBEXPEAK-M_FCBGA1071 4 XTAL25_IN EMI REQUEST 0303 T45 2 2 Title 25MHZ_20P_1BG25000CK1A 18P_0402_50V8J P13 CLKOUTFLEX0 / GPIO64 1 18P_0402_50V8J 2 10K_0402_5% CLKOUT_PEG_B_N CLKOUT_PEG_B_P GPIO56 = NATIVE,3.3V,SUS 5 1 @ 2 GPIO25 = NATIVE,3.3V,SUS R984 1 R989 1 G8 SML0DATA Q61B 2N7002DW-T/R7_SOT363-6 3 4 SMBDATA R960 0_0402_5% @ 2 GPIO20 = NATIVE,3.3V,CORE AK53 AK51 +3VALW CLKOUT_PCIE0N CLKOUT_PCIE0P GPIO18 = NATIVE,3.3V,CORE PCIECLKREQ4# <30> PCIECLKREQ4# MINI2 GPIO73 = NATIVE,3.3V,SUS U4 SML0CLK PEG_A_CLKRQ# / GPIO47 PERN7 PERP7 PETN7 PETP7 AM51 AM53 +3VALW PERN6 PERP6 PETN6 PETP6 AT34 AU34 AU36 AV36 CLKREQ_EXP# <30> CLKREQ_EXP# WLAN 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K C6 DDR3*2 AND CLK GEN +3VS SMBDATA <10,11> 1 2 PERN4 PERP4 PETN4 PETP4 LAN SMBCLK D 5 BA32 BB32 BD32 BE32 SMBus 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 BA34 AW34 BC34 BD34 J14 GPIO60 SML0CLK SMB_CLK_S3 <10,11,12,30> SMBCLK <10,11> SMBDATA SML0ALERT# / GPIO60 SMB_CLK_S3 +3VALW 2 PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_C_DRX_N6 PCIE_PTX_C_DRX_P6 WLAN 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6 GPIO11 = NATIVE,3.3V,SUS GPIO60 = NATIVE,3.3V,SUS AU30 AT30 AU32 AV32 PERN3 PERP3 PETN3 PETP3 SMBCLK C8 SMBDATA PERN2 PERP2 PETN2 PETP2 H14 Q61A 2N7002DW-T/R7_SOT363-6 6 1 1 <30> <30> <30> <30> TV SMBCLK PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3 C SMBALERT# / GPIO11 NEW CARD LID_OUT# 5 C1062 1 C1063 1 AW30 BA30 BC30 BD30 PERN1 PERP1 PETN1 PETP1 B9 2 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P4 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2 BG30 BJ30 BF29 BH29 Link <30> <30> <30> <30> 3G C1061 1 C1064 1 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1 Controller LAN U46B C1059 1 C1060 1 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_C_DRX_N3 PCIE_PTX_C_DRX_P3 R959 0_0402_5% PEG <31> <31> <31> <31> GPIO60 C1058 1 C1057 1 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 LID_OUT# EC_LID_OUT# <37> From CLK BUFFER WLAN <30> <30> <30> <30> PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 GPIO74 Clock Flex <30> <30> <30> <30> EXP SML1DATA PCI-E* D SML1CLK 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 1 C1067 @ 2 1 C1068 @ 2 A Compal Electronics, Inc. IBEX-M(2/6)-PCI-E/SMBUS/CLK Size Document Number Custom Date: Rev 0.2 NIWBA_LA5371P Sheet Tuesday, March 24, 2009 1 14 of 52 5 4 3 2 1 D D DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 BE22 BF21 BD20 BE18 DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 BD22 BH21 BC20 BD18 DMI0TXP DMI1TXP DMI2TXP DMI3TXP BH25 DMI_ZCOMP <6> <6> <6> <6> DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 +1.05VS 1 R993 DMI_IRCOMP 2 49.9_0402_1% BF25 FDI DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI <6> <6> <6> <6> ： FDI_FSYNC0 BF13 FDI_FSYNC0 FDI_FSYNC1 BH13 FDI_FSYNC1 FDI_LSYNC0 BJ12 FDI_LSYNC0 FDI_LSYNC1 BG14 FDI_LSYNC1 FDI_FSYNC0 <6> FDI_FSYNC1 <6> FDI_LSYNC0 <6> FDI_LSYNC1 <6> ICH_POK R1001 1 @ M6 2 0_0402_5% B17 R1002 0_0402_5% 1 2 10K_0402_5%A10 LAN_RST# PM_RSMRST# R1006 2 1 10K_0402_5% 2 10K_0402_5% SUS_PWR_DN_ACK_R 1 2 R1024 @ 0_0402_5% C16 M1 PBTN_OUT#P5 <37> PBTN_OUT# AP39 AP41 LVD_IBG LVD_VBG AT43 AT42 LVD_VREFH LVD_VREFL <29> LVDS_ACLK# <29> LVDS_ACLK AV53 AV51 LVDSA_CLK# LVDSA_CLK <29> LVDS_A0# <29> LVDS_A1# <29> LVDS_A2# BB47 BA52 AY48 AV47 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 <29> LVDS_A0 <29> LVDS_A1 <29> LVDS_A2 BB48 BA50 AY49 AV48 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 <29> LVDS_BCLK# <29> LVDS_BCLK AP48 AP47 LVDSB_CLK# LVDSB_CLK <29> LVDS_B0# <29> LVDS_B1# <29> LVDS_B2# AY53 AT49 AU52 AT53 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 <29> LVDS_B0 <29> LVDS_B1 <29> LVDS_B2 AY51 AT48 AU50 AT51 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 AA52 AB53 AD53 CRT_BLUE CRT_GREEN CRT_RED T110 PAD DRAMPWROK RSMRST# PWRBTN# 2 AC_PRESENT_R 0_0402_5% P7 ACPRESENT / GPIO31 A6 BATLOW# / GPIO72 PCIE_WAKE# J12 PCIE_WAKE# <30,31> 1 R1000 Y1 2 10K_0402_5% +3VS GPIO32 = GPO,3.3V,CORE SUS_STAT# / GPIO61 P8 GPIO61 GPIO61 = NATIVE,3.3V,SUS SUSCLK / GPIO62 F3 GPIO62 GPIO62 = NATIVE,3.3V,SUS SLP_S5# / GPIO63 E4 SLP_S4# H7 SLP_S4# <37> SLP_S3# P12 SLP_S3# <37> SLP_M# K8 TP23 N2 SUS_PWR_DN_ACK / GPIO30 R1009 1 R1010 +3VALW <28> DAC_BLU <28> DAC_GRN <28> DAC_RED DAC_BLU DAC_GRN DAC_RED R1012 1 R1013 1 2 8.2K_0402_1% GPIO72 PMSYNCH GPIO30 = GPI,3.3V,SUS 2 10K_0402_5% F14 BJ48 BG48 SDVO_INTN SDVO_INTP BF45 BH45 CRT_DDC_CLK CRT_DDC_DATA <28> CRT_HSYNC <28> CRT_VSYNC Y53 Y51 CRT_HSYNC CRT_VSYNC Can be left NC when IAMT is not support on the platfrom BJ10 CRT_IREF AD48 AB51 H_PM_SYNC <5> DAC_IREF CRT_IRTN T51 T53 DDPB_AUXN DDPB_AUXP DDPB_HPD BG44 BJ44 AU38 DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 DDPC_CTRLCLK DDPC_CTRLDATA Y49 AB49 DDPC_AUXN DDPC_AUXP DDPC_HPD BE44 BD44 AV40 TMDS_B_HPD# <27> DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 TMDS_B_DATA2# <27> TMDS_B_DATA2 <27> TMDS_B_DATA1# <27> TMDS_B_DATA1 <27> TMDS_B_DATA0# <27> TMDS_B_DATA0 <27> TMDS_B_CLK# <27> TMDS_B_CLK <27> R1309 2 10K_0402_5% 1 +3VS UMA@ R1310 2.2K_0402_5% UMA@ R1311 2.2K_0402_5% HDMICLK_NB HDMIDAT_NB HDMICLK_NB <27> HDMIDAT_NB <27> C DDPD_CTRLCLK DDPD_CTRLDATA V51 V53 GPIO29 = GPO,3.3V,SUS If not using integrated SLP_LAN# / GPIO29 F6 LAN,signal may be left as NC. RI# SDVO_STALLN SDVO_STALLP HDMI U50 U52 DDPD_AUXN DDPD_AUXP DDPD_HPD BC46 BD46 AT38 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36 IBEXPEAK-M_FCBGA1071 B 2 +3VALW BJ46 BG46 SDVO_CTRLCLK SDVO_CTRLDATA <28> CRT_DDC_CLK <28> CRT_DDC_DATA GPIO31 = GPI,3.3V,SUS B SDVO_TVCLKINN SDVO_TVCLKINP SLP_S5# <37> R1011 1K_0402_0.5% 10K_0402_5% 1 2 <37> AC_PRESENT CLKRUN# / GPIO32 PWROK MEPWROK PM_DRAM_PWRGD D9 <5> PM_DRAM_PWRGD SYS_PWROK K5 1 R1003 WAKE# L_BKLTCTL L_CTRL_CLK L_CTRL_DATA 2 2 10K_0402_5% 10K_0402_5% 1 <37> 2 0_0402_5% SYS_RESET# Y48 AB46 V48 1 1R1306 R1307 R1308 2.37K_0402_1% R997 T6 System Power Management R999 1 SYS_RST# L_BKLTEN L_VDD_EN L_DDC_CLK L_DDC_DATA +3VS <6> <6> <6> <6> <6> <6> <6> <6> T48 T47 AB48 Y45 <29> EDID_CLK <29> EDID_DATA FDI_INT <6> 1K_0402_5% 1 2 2 VGATE +3VALW FDI_INT 2 100K_0402_1% 1 <51> <37> SUS_PWR_DN_ACK BJ14 R996 10K_0402_5% 1 R998 2 R1008 1 FDI_INT FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 INV_PWM +3VS Checklist0.8 MEPWROK can be connect to PWROK if iAMT disable +3VALW FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 DMI_IRCOMP 4mil width and place within 500mil of the PCH C BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 PCH_ENVDD <29> PCH_ENVDD_R 1 DMI0RXP DMI1RXP DMI2RXP DMI3RXP <6> <6> <6> <6> <6> <6> <6> <6> 1 BD24 BG22 BA20 BG20 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 2 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 <29> PCH_ENBKL_R FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 Digital Display Interface DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 LVDS <6> <6> <6> <6> DMI0RXN DMI1RXN DMI2RXN DMI3RXN CRT DMI_CTX_PRX_N0 BC24 DMI_CTX_PRX_N1 BJ22 DMI_CTX_PRX_N2 AW20 DMI_CTX_PRX_N3 BJ20 1 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 2 FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 <6> <6> <6> <6> U46D PCH_ENBKL 2 U46C IBEXPEAK-M_FCBGA1071 CRT OUT RSMRST circuit @ R1014 @R1014 0_0402_5% 2 1 E BAV99DW-7_SOT363 1 2 2 4 B 5 SLP_S4# SLP_S5# R1162 1 UMA@ 2 150_0402_1% DAC_GRN R1186 1 UMA@ 2 150_0402_1% DAC_RED R1184 1 UMA@ 2 150_0402_1% 1 2 R1004 @ 10K_0402_5% 1 2 R1005 @ 10K_0402_5% 1 2 R1007 @ 10K_0402_5% PM_RSMRST# 1 Q3 MMBT3906_SOT23-3 1 2 +3VALW R1015 4.7K_0402_5% C 3 <37> EC_RSMRST# SLP_S3# DAC_BLU D36B 1 3 A 6 D36A BAV99DW-7_SOT363 R1016 A 2 2.2K_0402_5% Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. IBEX-M(3/6)-DMI/GPIO/LVDS Size Document Number Custom Date: Rev 0.2 NIWBA_LA5371P Tuesday, March 24, 2009 Sheet 1 15 of 52 5 4 3 2 U46E = = = = GPI,5V,CORE GPI,5V,CORE GPI,5V,CORE GPI,5V,CORE G38 H51 B37 A44 PIRQA# PIRQB# PIRQC# PIRQD# PCI_REQ0# PCI_REQ1# DGPU_SELECT# PCI_REQ3# F51 A46 B45 M53 REQ0# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 PCI_GNT3# GNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# B41 K53 A36 A48 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 K6 PCIRST# PCI_SERR# PCI_PERR# E44 E50 SERR# PERR# PCI_IRDY# PCI_DEVSEL# PCI_FRAME# A42 H44 F46 C46 IRDY# PAR DEVSEL# FRAME# PCI_LOCK# D49 PCI_STOP# PCI_TRDY# D41 C48 STOP# TRDY# M7 PME# GNT2 Default-Internal pull up * Low=Configures DMI for ESI compatible operation(for servers only.Not for mobile/desktops) <37> PCI_PME# PLT_RST# B R1044 2 47_0402_1% 2 47_0402_1% 1 1 <37> CLK_PCI_LPC <14> CLK_PCI_FB AU2 NV_RB# AV7 NV_WR#0_RE# NV_WR#1_RE# AY8 AY5 D5 PLTRST# N52 P53 P46 P51 P48 CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 USBRBIAS# B25 USBRBIAS D25 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 N16 J16 F16 L16 E14 G16 F12 T15 TACH3 / GPIO7 EC_SMI# F10 GPIO8 CPUSB# K9 GPIO15 T7 GPIO15 DGPU_RST# AA2 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N DGPU_PWROK F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P <19> DGPU_RST# <47,49> DGPU_PWROK it have weak internal PU 20K 10K_0402_5% ： +3VALW 10K_0402_5% 10K_0402_5% 10K_0402_5% GPIO1 = GPI,3.3V,CORE GPIO6 = GPI,3.3V,CORE GPIO7 = GPI,3.3V,CORE GPIO8 = GPO,3.3V,SUS GPIO12 = GPI,3.3V,SUS R1032 32.4_0402_1% <42> DGPU_PWR_EN# 10K_0402_5% 10K_0402_5% 10K_0402_5% +3VALW USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 <40> <40> <34> <34> <40> <40> 10K_0402_5% RIGHT USB 10K_0402_5% LEFT USB 10K_0402_5% USB Camera <37> PCH_TEMP_ALERT# <40> <40> <33> <33> USB20_N13 <30> USB20_P13 <30> USBRBIAS 1 R1043 CARD READER DIS@ R992 0_0402_5% 1 2 SUSP# Y7 AB12 1 2 GPIO37 AB13 R1034 1 2 GPIO38 V3 R1035 P3 1 2 GPIO39 R1036 H3 1 2 GPIO45 R1037 1 2 GPIO46 F1 R1038 1 2 GPIO48 AB6 R1039 PCH_TEMP_ALERT# AA4 2 GPIO57 10K_0402_5% TV VGA_EN <48> R994 0_0402_5% 1 2 HYBRID@ WLAN <42> DGPU_PWR_EN# EXPRESS Bluetooth +3VALW 3G CARD 2 22.6_0402_1% RP1 USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 1 2 3 4 Within 500 mils minimum spacing to other signal is 15mil USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 LAN_PHY_PWR_CTRL / GPIO12 A20GATE USB_OC#2 <34,40> 8 7 6 5 8.2K_0804_8P4R_5% USB_OC#0 <34,40> RP2 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 1 2 3 4 2 R1025 10K_0402_5% 8 7 6 5 8.2K_0804_8P4R_5% F8 SCLOCK / GPIO22 GPIO24 PECI RCIN# GATEA20 <37> AM3 CLK_CPU_BCLK# GPIO27 GPIO28 A4 A49 A5 A50 A52 A53 B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53 AM1 H_PECI T1 KB_RST# PROCPWRGD THRMTRIP# BD10 H_PECI H_CPUPWRGD H_THERMTRIP#_L 1 54.9_0402_1% R1028 STP_PCI# / GPIO34 SATA2GP / GPIO36 TP1 BA22 SATA3GP / GPIO37 TP2 AW22 RP3 PCI_REQ0# PCI_PIRQB# PCI_PIRQF# PCI_REQ3# PCI_REQ1# PCI_FRAME# PCI_TRDY# PCI_PIRQH# 1 2 3 4 RP4 PCI_PIRQG# PCI_PIRQC# PCI_PIRQA# PCI_PIRQE# 8 7 6 5 1 2 3 4 8.2K_0804_8P4R_5% RP5 RP6 1 2 3 4 PCI_DEVSEL# PCI_LOCK# PCI_SERR# PCI_PERR# 8 7 6 5 8.2K_0804_8P4R_5% 1 2 3 4 PCI_GNT0# R1046 1 PCI_GNT1# R1047 1 2 1K_0402_5% @ 2 1K_0402_5% SLOAD / GPIO38 TP3 BB22 SDATAOUT0 / GPIO39 TP4 AY45 PCIECLKRQ6# / GPIO45 TP5 AY46 PCIECLKRQ7# / GPIO46 TP6 AV43 SDATAOUT1 / GPIO48 TP7 AV45 SATA5GP / GPIO49 TP8 AF13 GPIO57 TP9 M18 TP10 N18 TP11 AJ24 TP12 AK41 TP13 AK42 TP14 M32 TP15 N32 TP16 M30 TP17 N30 TP18 H12 TP19 AA23 NC_1 AB45 NC_2 AB38 NC_3 AB42 NC_4 AB41 NC_5 T39 INIT3_3V# P6 C B INT3_3V# USB PORT LIST C10 TP24 PORT PCI_GNT0# PCI_GNT1# Boot BIOS Location 0 LPC 0 8 7 6 5 8.2K_0804_8P4R_5% 0 1 Reserved(NAND) 1 0 PCI 1 1 SPI 8 7 6 5 1 R1049 * 2 0_0402_5% Low=A16 swap override/Top-Block PCI_GNT3# Swap Override enabled High=Default * 5 1 A16 swap overide Strap/Top-Block Swap Override jumper A 1 B 2 Y U49 1 R1022 DGPU_PWROK 2 10K_0402_5% DMI termination voltage. weak internal PU, don't PD 1 R1033 DGPU_PWR_EN 2 1K_0402_5% 1 R1182 PCH_TEMP_ALERT# 2 10K_0402_5% 2 R1021 @ 1 R1041 DGPU_RST# 1 10K_0402_5% EC_SCI# 2 10K_0402_5% @ 1 R1042 2 10K_0402_5% +3VS Set to Vcc when HIGH NV_CLE Set to Vss when LOW +3VS Weak internal PU,Do not pull low +3VALW @R1050 @ R1050 1 +3VS EC_SMI# 2 1K_0402_5% PLT_RST# Compal Secret Data Security Classification Issued Date R1052 100K_0402_5% 4 2 1K_0402_5% NV_CLE 3 G 4 <5,19,30,31> BUF_PLT_RST# P 2 1K_0402_5% @R1048 @ R1048 1 5 @R1051 @ R1051 1 NV_ALE NV_CLE 8.2K_0804_8P4R_5% PCI_GNT3# * DMI Termination Voltage +3VS NC7SZ08P5X_NL_SC70-5 @ ： ： Disable Intel Anti-Theft Technology floating(internal PD) +1.8VS 2008/08/12 Deciphered Date 2009/08/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 A DEVICE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 NV_ALE Enable Intel Anti-Theft Technology 8.2K PU to +3VS Intel Anti-Theft Techonlogy High=Enabled NV_ALE Low=Disable(floating) Boot BIOS Strap RP7 PCI_STOP# 1 PCI_IRDY# 2 PCI_PIRQD# 3 DGPU_SELECT#4 H_THERMTRIP# <5> @ 8 7 6 5 8.2K_0804_8P4R_5% <5> 2 +VCCP IBEXPEAK-M_FCBGA1071 +3VS KB_RST# R1030 56_0402_5% SATACLKREQ# / GPIO35 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 R1026 10K_0402_5% <5> KB_RST# <37> IBEXPEAK-M_FCBGA1071 +3VS +3VS <5> CLK_CPU_BCLK <5> BG10 BE10 TP24 R1045 U2 D RIGHT USB <30,37,42,47,49> USB20_N8 <30> USB20_P8 <30> USB20_N9 <30> USB20_P9 <30> USB20_N10 <30> USB20_P10 <30> USB20_N11 <40> USB20_P11 <40> GPIO22 1 2 GPIO28 V13 R1027 2 1 GPIO34 M11 R1029 2 1 GPIO35 V6 R1031 DGPU_PWR_EN# AB7 1 R1040 +3VALW USB20_N4 USB20_P4 USB20_N5 USB20_P5 2 GPIO27 if pull down to turn off 1.8V VR High Enables the internal VccVRM to have a clean supply for analog rails. no need to use on board filter circuit. NV_RCOMP 1 R1023 H10 ：Do not connect(floating) GPIO27 Default NV_ALE NV_CLE 2 AF48 AF47 1 1 R1020 CLKOUT_PCIE7N CLKOUT_PCIE7P 2 10K_0402_5% TACH2 / GPIO6 J32 +3VS 1 +3VALW D37 AH45 AH46 1 CPUSB# GPIO6 CLKOUT_PCIE6N CLKOUT_PCIE6P MISC EC_SMI# <30> TACH1 / GPIO1 BMBUSY# / GPIO0 CPU ： <37> C38 GPIO *： GPIO15 L Intel ME Crypto Transport Layer Security(TLS) chiper suite with no confidentiality H Intel ME Crypto Transport Layer Security(TLS) chiper suite with confidentiality EC_SCI# AV11 BF5 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P PLOCK# 10K_0402_5% <37> Y3 GPIO1 2 NV_RCOMP NV_WE#_CK0 NV_WE#_CK1 F48 K45 F36 H53 <37,38> PCI_RST# BD3 AY6 10K_0402_5% GPIO0 1 2 R1017 1 2 R1018 1 2 R1019 EC_SCI# RSVD GPIO2 GPIO3 GPIO4 GPIO5 NV_ALE NV_CLE 10K_0402_5% Check list Rev0.8 section1.23.2 If not implemented, the Braidwood interface signals can be left as No Connect (NC). 2 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_GNT0# PCI_GNT1# NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 +3VS NCTF C NVRAM C/BE0# C/BE1# C/BE2# C/BE3# AV9 BG8 GPIO0 = GPI,3.3V,CORE GPIO8 Weak internal PU, don't PD AY9 BD1 AP15 BD8 AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6 USB <26,28,29> DGPU_SELECT# NV_DQS0 NV_DQS1 J50 G42 H47 G34 PCI_CBE#3 GPIO18 = NATIVE,5V,CORE GPIO52 = NATIVE,5V,CORE GPIO54 = NATIVE,5V,CORE NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 PCI D AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 1 H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36 1 U46F 3 2 Title RIGHT SIDE LEFT SIDE CMOS RIGHT SIDE CARD READER WIRELESS TV TUNNER NEW CARD BT A 3G Compal Electronics, Inc. IBEX-M(4/6)-PCI/USB/RSVD Size Document Number Custom Date: Rev 0.1 NIWBA_LA5371P Sheet Tuesday, March 24, 2009 1 16 of 52 5 4 VCC3_3[5] V16 VCC3_3[6] Y16 VCC3_3[7] AD19 AF20 AF19 AH20 VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] AB19 AB20 AB22 AD22 VCCME[13] VCCME[14] VCCME[15] VCCME[16] AA34 Y34 Y35 AA35 1 2 A12 VCCRTC 2mA IBEXPEAK-M_FCBGA1071 6mA VCCSUSHDA 1 @ 2 10UH_LB2012T100MR_20% +1.05VS L507 @ +1.8VS AT22 VCCVRM[1] 0.035A BJ18 VCCFDIPLL 6mA +1.05VS_VCCFDIPLL 1 2 10UH_LB2012T100MR_20% AM23 +1.05VS C1107 @ 10U_0603_6.3V6M VCCIO[1] 1 VCCTX_LVDS[3] VCCTX_LVDS[4] +VCCTX_LVDS 0.01U_0402_16V7K C88 1 1 VCC3_3[2] 0.01U_0402_16V7K UMA@ AB34 VCC3_3[3] AB35 VCC3_3[4] AD35 VCCVRM[2] AT24 VCCDMI[1] AT16 VCCDMI[2] AU16 VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] 0.156A VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9] AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15 C1341 UMA@ 2 R154 0_0402_5% DIS@ 2 2 0.1U_0402_16V4Z 0.061A C +VCCP 1 C1092 1 2 2 1U_0402_6.3V6K R1058 1 2 0_0402_5% +1.8VS @ R1059 1 2 0_0402_5% +3VS +3VS 0.085A VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4] AM8 AM9 AP11 AP9 1 B +VCCADPLLA 10uH inductor, 120mA L40 1 2 10UH_LB2012T100MR_20% +1.05VS +PCH_VCC1_1_20 +PCH_VCC1_1_21 +PCH_VCC1_1_22 +PCH_VCC1_1_23 1 1 1 1 R1062 R1063 R1064 R1065 2 2 2 2 +5VALW +3VALW 1 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% C1094 220U_B_2.5VM_R35M + 1 C104 1U_0402_6.3V4Z 2 L30 1 2 R573 0_0402_5% @ R1060 100_0402_1% 2 D37 CH751H-40PT_SOD323-2 +VCCADPLLB +5VS +3VS R1061 100_0402_1% D38 CH751H-40PT_SOD323-2 PCH_V5REF_SUS +3VALW 10uH inductor, 120mA 1 1 C1007 220U_B_2.5VM_R35M PCH_V5REF_RUN 20 mils L42 1 2 10UH_LB2012T100MR_20% + 1 20 mils 1 C1116 0.1U_0402_10V6K 2 C109 1U_0402_6.3V4Z 2 2 C1117 1U_0402_6.3V6K A 2 Compal Secret Data Security Classification Issued Date 2008/08/12 Deciphered Date 2009/08/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 C1173 UMA@ 2 10U_0805_6.3V6M 1 C1082 IBEXPEAK-M_FCBGA1071 +1.05VS C87 UMA@ 2 L12 UMA@ 2 1 0.1UH_MLF1608DR10KT_10%_1608 10U_0805_6.3V6M 1 1 +3VS 2 2 0.1uH inductor, 200mA +1.8VS 1 AP43 AP45 AT46 AT45 2 VCCTX_LVDS[1] R136 0_0402_5% DIS@ 2 CRT VCC CORE VCC3_3[1] 2 2 CPU V_CPU_IO[2] AF22 VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] 2 1 +1.05VS C1118 2 >1mA VCCIO[12] 1 +1.8VS 1U_0402_6.3V6K 2 C1120 A 1 0.1U_0402_16V4Z C1119 1 0.1U_0402_16V4Z 2mA@3.3V V_CPU_IO[1] HDA 2 AU18 RTC 2 1 0.1U_0402_16V4Z 1 C1115 0.1U_0402_16V4Z C1113 2 +RTCVCC C1114 4.7U_0603_6.3V6K 1 AT18 @ C1112 V15 VCCIO[11] AD20 AH39 +1.8VS 2 1U_0402_6.3V6K VCCSUS3_3[32] AH19 +1.05VS L506 @ AT20 VCCIO[10] AN35 2 1 1 UMA@ 2 0.022_0805_1% 2 VCCSUS3_3[31] +3VS 1 1 2 C1103 0.1U_0402_16V4Z 1 0.042A VCCAPLLEXP VCCIO[54] VCCIO[55] 2 +3VS BJ24 AN30 AN31 1 +1.05VS_VCCAPLL R135 1 VCCSUS3_3[30] U20 VCCVRM[4] 2 AH22 VSSA_LVDS C1109 VCCSUS3_3[29] AK3 AK1 D +3VS 2 DCPSUS +VCCP 0.1A@1.1V AD13 VCCSATAPLL[1] U19 U22 0.4A@3.3V 2 0.1U_0402_16V4Z C1111 VCC3_3[14] 0.032A VCCSATAPLL[2] +3VS 1 U35 2 0.1U_0402_16V4Z 0.2A@3.3V 2 0.1U_0402_16V4Z C1110 VCC3_3[13] 3.208A VCCIO[9] P18 1 P36 C1093 0.1U_0402_16V4Z C1108 Y22 VCC3_3[12] 2 0_0603_5% 1 DCPSST VCC3_3[11] N36 VCCALVDS AH38 C1099 VCCIO[4] V12 M36 @ 0.1U_0402_16V4Z AF32 VCC3_3[10] 1 2 C1098 VCCIO[3] L38 1U_0402_6.3V6K +3VALW B AH34 VCC3_3[9] 2 +3VS 10U_0603_6.3V6M +V1.1A_INT_VCCSUS 1 2 0.1U_0402_16V4Z C1105 VCCIO[2] J38 C1106 2 0.1U_0402_16V4Z C1104 AF34 VCC3_3[8] PCH_V5REF_RUN 1 10U_0603_6.3V6M +VCCSST 1 VCCIO[21] VCCIO[22] VCCIO[23] K49 C1097 2 AH23 AJ35 AH35 0.357A V5REF 1 1U_0402_6.3V6K 2 1 VCCADPLLB[1] VCCADPLLB[2] >1mA +1.05VS C1096 1 1U_0402_6.3V6K C1102 1U_0402_6.3V6K C1100 2 C1101 1U_0402_6.3V6K 1 0.073A BD51 BD53 2 1U_0402_6.3V6K +1.05VS VCCADPLLA[1] VCCADPLLA[2] 1 +1.05VS PCH_V5REF_SUS 2 C1091 BB51 BB53 +VCCADPLLB 0.072A F24 @ 1U_0402_6.3V6K +VCCADPLLA 0.035A VCCVRM[3] V5REF_SUS >1mA VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO[50] VCCIO[51] VCCIO[52] VCCIO[53] +3VALW C1090 AU24 +1.8VS DCPRTC V23 AK24 AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 1U_0402_6.3V6K V9 VCCIO[56] 2 1 2 VCCME[12] U23 @ 1 2 1 Y42 VCCSUS3_3[28] AF51 2 VCCME[11] L505 @ 2 1 2 10UH_LB2012T100MR_20% R1056 1 C1088 VCCME[10] Y41 C1089 +VCCRTCEXT 1 2 0.1U_0402_16V4Z C VCCME[9] Y39 AF53 VSSA_DAC[2] 1 1 2 V42 VCCME[8] 1 @ 0_0603_5% C1081 V41 1.998A +1.05VS_APLL LVDS VCCME[7] VSSA_DAC[1] HVCMOS VCCME[6] V39 AE52 0.059A VCCTX_LVDS[2] DMI AF42 2 AE50 VCCADAC[2] 0.030A +1.05VS 10U_0805_6.3V6M 1 VCCME[5] VCCADAC[1] 1 +VCCA_LVDS NAND / SPI AF41 1 0.069A PCI E* VCCME[4] FDI AF43 0.1U_0402_16V4Z 2 VCCME[3] 1U_0402_6.3V6K 2 1 C1087 1 10U_0603_6.3V6M 2 C1086 10U_0603_6.3V6M 1 C1085 10U_0603_6.3V6M 2 C1084 10U_0603_6.3V6M C1083 1 AD41 2 +3VALW C1080 2 UPDATE 0210 VCCME[2] 2 0.1U_0402_16V4Z 1U_0402_6.3V6K C1076 1 USB AD39 +1.05VS VCCME[1] PCI/GPIO/LPC AD38 DCPSUSBYP SATA 2 2 Y20 0.1U_0402_16V4Z 2 1 1 1 C1075 2 T83 VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] 0.163AVCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27] VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4]1.524A VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] C1079 PAD 0.344A AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31 C1078 VCCLAN[2] 1 C1077 VCCLAN[1] AF24 1 C1073 @ C1074 @C1074 1U_0402_6.3V4Z V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26 C1072 AF23 1 +3VS R1053 POWER U46G 10U_0603_6.3V6M VCCACLK[2] +1.05VS V24 V26 Y24 Y26 1U_0402_6.3V6K AP53 +3VS_DAC VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] 0.052A 0.1U_0402_16V4Z 2 VCCACLK[1] 10U_0805_6.3V6M 2 AP51 0.01U_0402_16V7K @ 1U_0402_6.3V6K 1 R1054 0_0402_5% 1 +1.05VS POWER U46J C1071 @ 1 Clock and Miscellaneous 1 1U_0402_6.3V6K D C1069 DG1.1 no M3 support and not Intel LAN, VCCLAN Source=>GND @ R1055 @R1055 1 2 0_0603_5% C1070 10U_0603_6.3V6M +1.05VS 2 +VCCP_VCCA_CLK L504 @ 1 2 10UH_LB2012T100MR_20% PCI/GPIO/LPC +1.05VS 3 4 3 2 Title Compal Electronics, Inc. IBEX-M(5/6)-PWR Size Document Number Custom Rev 0.1 NIWBA_LA5371P Date: Sheet Tuesday, March 24, 2009 1 17 of 52 5 4 3 2 1 U46I AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48 E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF39 H16 H20 H30 H34 H38 H42 D C B A VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366] U46H H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14 AB16 VSS[0] AA19 AA20 AA22 AM19 AA24 AA26 AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47 AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28 VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47 D C B IBEXPEAK-M_FCBGA1071 A IBEXPEAK-M_FCBGA1071 Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. IBEX-M(6/6)-GND Size Document Number Custom Rev 0.2 NIWBA_LA5371P Date: Sheet Tuesday, March 24, 2009 1 18 of 52 5 4 3 2 1 U50A +3VS_D AR16 <14> CLK_PCIE_VGA AR17 <14> CLK_PCIE_VGA# AR13 2 1 R1079 1 2 10K_0402_5%VGA@ R1080 @ 0_0402_5% AJ17 AJ18 1 2 R1082 @ 200_0402_5% <14> PEG_CLKREQ# 0_0402_5% 2 VGA@ 1 NC7SZ08P5X_NL_SC70-5 B A HYBRID@ R1085 10K_0402_5% @ 4 Y AM16 1 AG21 2.49K_0402_1% 2 R1084 AE9 +PLLVDD +SP_PLLVDD CLOSE Y4 2 0_0402_5% @ 1 R1090 <12> 27M_CLK_SS PULL UP BY PCH SIDE 2 0_0402_5% <14,41> SMB_EC_CK2_R <14,41> SMB_EC_DA2_R <29> VGA_LVDS_SCL <29> VGA_LVDS_SDA +3VS_D 2.2K_0402_5% R1091 VGA@ VGA@ 2.2K_0402_5% PULL UP BY RGB <28> VGA_DDCCLK SIDE<28> VGA_DDCDATA XTALIN A XTALOUT 1 2 VGA@ C1167 20P_0402_50V8 60mA SP_PLLVDD 45mA VID_PLLVDD45mA PLLVDD B1 B2 XTAL_IN XTAL_OUT XTAL_OUTBUFF XTAL_SSIN D1 D2 XTAL_OUTBUFF XTAL_SSIN E2 E1 I2CS_SCL I2CS_SDA VGA_LVDS_SCL E3 VGA_LVDS_SDA E4 I2CC_SCL I2CC_SDA HDMI_SCL HDMI_SDA G3 G2 I2CB_SCL I2CB_SDA VGA_DDCCLK VGA_DDCDATA G1 G4 I2CA_SCL I2CA_SDA HDCP_I2CH_SCL F6 HDCP_I2CH_SDA G6 Y9 PEX_RST_N PEX_TERMP XTALIN XTALOUT SMB_EC_CK2_R SMB_EC_DA2_R PULL UP BY LVDS CONN SIDE R1092 AF9 AD9 @ 1 R1089 <12> 27M_CLK PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N VGA@ 2 2 DGPU_RST# G <16> DGPU_RST# BUF_PLT_RST# 3 <5,16,30,31> BUF_PLT_RST# +3VS U16 P 5 B 1 R1187 1 PEX_REFCLK PEX_REFCLK_N PEX_CLKREQ_N MIOA_HSYNC MIOA_VSYNC N3 L3 MIOB_HSYNC MIOB_VSYNC W1 W2 MIOA_DE MIOA_CTL3 MIOA_VREF N2 P5 N5 MIOB_DE MIOB_CTL3 MIOB_VREF Y5 W3 AF1 R1068 1 10K_0402_5% 0.9V 0,10 R1071 2.2K_0402_5% VGA@ @ R1072 10K_0402_5% VGA@ C1121 0.1U_0402_16V4Z 2 U51 VGA@ 8 7 6 5 OUT GND 4 2 GND IN 1 R1074 100K_0402_1% 2 VGA@ External Spread Spectrum OSC_OUT R1075 1 XTAL_OUTBUFF 2 @ 22_0402_5% C U52 OSC_OUT 1 REFOUT VSS 6 2 XOUT MODOUT 5 3 XIN/CLKIN VDD R1077 10K_0402_5% VGA@ OSC_SPREAD 4 +3VS_D 1 @ ASM3P2872AF-06OR_TSOT-23-6 2 @ C1147 0.1U_0402_16V4Z OSC_SPREAD R1179 1 XTAL_SSIN 2 @ 22_0402_5% R1178 10K_0402_5% VGA@ If External Spread Spectrum not stuff then stuff resistor +1.05VS_D 2 VGA@ 1 R1081 +PLLVDD L508 MBK1608121YZF_0603 1 2 VGA@ 2 VGA@ 1 R1083 1U_0603_10V4Z VGA@ C1155 VGA@ C1156 NEAR GPU VGA@ C1157 B 1U_0603_10V4Z 1U_0603_10V4Z CRT OUT VGA_CRT_R R1086 1 VGA@ 2 150_0402_1% VGA_CRT_G R1087 1 VGA@ 2 150_0402_1% R1088 1 VGA@ 2 150_0402_1% VGA_CRT_B VGA_HSYNC VGA_VSYNC VGA_HSYNC <28> VGA_VSYNC <28> DACA_VDD DACA_VREF DACA_RSET AJ12 AK12 AK13 +DACA_VDD DACA_VREF DACA_RSET 4700P_0402_16V7K VGA@ C1158 1 2 UNDER GPU VGA@ C1159 0.1U_0402_16V4Z +DACA_VDD +3VS_D 470P_0402_50V7K 1 2 L509MBK1608121YZF_0603 1 1 2 VGA@ VGA@ VGA@ VGA@ C1160 C1161 C1162 1 VGA@ VGA@ 4.7U_0603_6.3V6M 2 2 1 R1093 C1163 124_0402_1% 0.1U_0402_16V4Z 4700P_0402_16V7K 2 +1.05VS_D L510 VGA@ VGA@ 1U_0603_10V4Z 1 2 +DACB_VDD R1094 2 MBK1608121YZF_0603 1 10K_0402_5% C1164 VGA@ +SP_PLLVDD 4700P_0402_16V7K 1 A C1165 VGA@ C1166 VGA@ 2 0.1U_0402_16V4Z N10P-GS-A1_BGA969 10M@ 1 27MHZ_16PF_X7T027000BG1H-V 2 Compal Electronics,Ltd. Compal Secret Data Security Classification VGA@ C1168 20P_0402_50V8 2008/03/25 Issued Date Deciphered Date 2008/04/ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title N10x-GS PCIE,LVDS,GPIO,CLK Size Document Number Custom 4 3 2 Rev 0.1 NIWBA_LA5371P Date: Tuesday, March 24, 2009 5 1 2 3 4 A0 A1 A2 GND 1 VCC WP SCL SDA VGA@ 3 D AT24C16AN-10SU-2.7_SO8 AM13 AL13 AG7 AK6 AH7 0 @ R1073 2.2K_0402_5% DACA_HSYNC DACA_VSYNC DACB_VDD DACB_VREF DACB_RSET 1 HDCP_I2CH_SCL HDCP_I2CH_SDA VGA_CRT_R <28> VGA_CRT_G <28> VGA_CRT_B <28> AM1 AM2 12 10K_0402_5% R1070 2.2K_0402_5% VGA@ VGA_CRT_R VGA_CRT_G VGA_CRT_B DACB_HSYNC DACB_VSYNC 0.85V +3VS_D AM15 AM14 AL14 AK4 AL4 AJ4 1 12 T85 DACA_RED DACA_GREEN DACA_BLUE DACB_RED DACB_GREEN DACB_BLUE 0 P-State R1067 1 10K_0402_5% MIOBCAL_PD_VDDQ MIOBCAL_PU_GND 0.8V 2 10K_0402_5% PAD AE1 V4 AA7 AA6 0 VGA@ @ MIOB_CLKIN MIOB_CLKOUT MIOACAL_PD_VDDQ MIOACAL_PU_GND R1066 2 10K_0402_5% VGA@ R1069 10K_0402_5% U5 T5 I2CH_SCL I2CH_SDA VGA@ N4 R4 T4 W4 0 VGA@ 1 MIOA_CLKIN MIOA_CLKOUT MIOA_CLKOUT_N MIOB_CLKOUT_N VGA_CORE 1 Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6 GPU_VID0 2 MIOB_D0 MIOB_D1 MIOB_D2 MIOB_D3 MIOB_D4 MIOB_D5 MIOB_D6 MIOB_D7 MIOB_D8 MIOB_D9 MIOBD_10 MIOB_D11 MIOB_D12 MIOB_D13 MIOB_D14 GPU_VID1 1 PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N N10M-GS N10P-GS 2 AL17 AM17 AM18 AM19 AL19 AK19 AL20 AM20 AM21 AM22 AL22 AK22 AL23 AM23 AM24 AM25 AL25 AK25 AL26 AM26 AM27 AM28 AL28 AK28 AK29 AL29 AM29 AM30 AM31 AM32 AN32 AP32 GPIO5 GPU_VID0 <48> GPU_VID1 <48> 1 PCIE_CRX_GTX_C_P0 PCIE_CRX_GTX_C_N0 PCIE_CRX_GTX_C_P1 PCIE_CRX_GTX_C_N1 PCIE_CRX_GTX_C_P2 PCIE_CRX_GTX_C_N2 PCIE_CRX_GTX_C_P3 PCIE_CRX_GTX_C_N3 PCIE_CRX_GTX_C_P4 PCIE_CRX_GTX_C_N4 PCIE_CRX_GTX_C_P5 PCIE_CRX_GTX_C_N5 PCIE_CRX_GTX_C_P6 PCIE_CRX_GTX_C_N6 PCIE_CRX_GTX_C_P7 PCIE_CRX_GTX_C_N7 PCIE_CRX_GTX_C_P8 PCIE_CRX_GTX_C_N8 PCIE_CRX_GTX_C_P9 PCIE_CRX_GTX_C_N9 PCIE_CRX_GTX_C_P10 PCIE_CRX_GTX_C_N10 PCIE_CRX_GTX_C_P11 PCIE_CRX_GTX_C_N11 PCIE_CRX_GTX_C_P12 PCIE_CRX_GTX_C_N12 PCIE_CRX_GTX_C_P13 PCIE_CRX_GTX_C_N13 PCIE_CRX_GTX_C_P14 PCIE_CRX_GTX_C_N14 PCIE_CRX_GTX_C_P15 PCIE_CRX_GTX_C_N15 N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6 GPIO6 1 C 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K CLK VGA@ C1122 1 2 C1123 1 2 C1124 1 2 C1125 1 2 C1126 1 2 C1127 1 2 C1128 1 2 C1129 1 2 C1130 1 2 C1131 1 2 C1132 1 2 C1133 1 2 C1134 1 2 C1135 1 2 C1136 1 2 C1137 1 2 C1138 1 2 C1139 1 2 C1140 1 2 C1141 1 2 C1142 1 2 C1143 1 2 C1144 1 2 C1145 1 2 C1146 1 2 C1148 1 2 C1149 1 2 C1150 1 2 C1151 1 2 C1152 1 2 C1153 1 2 C1154 1 2 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_P15 PCIE_CRX_GTX_N15 MIOA_D0 MIOA_D1 MIOA_D2 MIOA_D3 MIOA_D4 MIOA_D5 MIOA_D6 MIOA_D7 MIOA_D8 MIOA_D9 MIOA_D10 MIOA_D11 MIOA_D12 MIOA_D13 MIOA_D14 HDMI_DETECT_VGA <26> PAD T84 @ VGA_ENVDD_R <29> VGA_ENBKL_R <29> NV_INVTPWM VGA_ENVDD_R VGA_ENBKL_R GPU_VID0 GPU_VID1 2 VGA@ K1 K2 K3 H3 H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 L1 L2 L4 M4 L7 L5 K6 L6 M6 2 D GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 DACs <6> PCIE_CRX_GTX_P[0..15] Part 1 of 7 1 PCIE_CRX_GTX_P[0..15] PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N 2 PCIE_CRX_GTX_N[0..15] <6> PCIE_CRX_GTX_N[0..15] AP17 AN17 AN19 AP19 AR19 AR20 AP20 AN20 AN22 AP22 AR22 AR23 AP23 AN23 AN25 AP25 AR25 AR26 AP26 AN26 AN28 AP28 AR28 AR29 AP29 AN29 AN31 AP31 AR31 AR32 AR34 AP34 I2C <6> PCIE_CTX_GRX_N[0..15] PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_P15 PCIE_CTX_GRX_N15 GPIO PCIE_CTX_GRX_N[0..15] PCI EXPRESS DVO PCIE_CTX_GRX_P[0..15] <6> PCIE_CTX_GRX_P[0..15] Sheet 1 19 of 52 5 4 3 FBA_CMD[0..30] FBC_CMD[0..30] FBA_DQM[0..7] <24> FBA_DQS[0..7] FBA_DQS[0..7] FBA_DQS#[0..7] FBC_CMD[0..30] FBC_DQM[0..7] <24> FBA_DQS#[0..7] FBA_D[0..63] 1 <24> FBA_CMD[0..30] FBA_DQM[0..7] 2 FBC_DQS[0..7] <24> FBC_DQS#[0..7] FBA_D[0..63] <24> UPDATE 0216 V32 W31 U31 Y32 AB35 AB34 W35 W33 W30 T34 T35 AB31 Y30 Y34 W32 AA30 AA32 Y33 U32 Y31 U34 Y35 W34 V30 U35 U30 U33 AB30 AB33 T33 W29 FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 +1.5VS_D B R1105 1K_0402_5% @ UNDER GPU +FB_PLLVDD AG27 AF27 FB_DLLAVDD FB_PLLAVDD 10MIL +FB_VREF R1109 1K_0402_5% @ +FB_PLLVDD FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 P32 H34 J30 P30 AF32 AL32 AL34 AF35 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 L35 G35 H31 N32 AD32 AJ31 AJ35 AC34 FBA_DQS#0 FBA_DQS#1 FBA_DQS#2 FBA_DQS#3 FBA_DQS#4 FBA_DQS#5 FBA_DQS#6 FBA_DQS#7 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 L34 H35 J32 N31 AE31 AJ32 AJ34 AC33 FBA_DQS0 FBA_DQS1 FBA_DQS2 FBA_DQS3 FBA_DQS4 FBA_DQS5 FBA_DQS6 FBA_DQS7 +FB_VREF 1 +1.5VS_D J27 MEMORY INTERFACE A C L32 N33 L33 N34 N35 P35 P33 P34 K35 K33 K34 H33 G34 G33 E34 E33 G31 F30 G30 G32 K30 K32 H30 K31 L31 L30 M32 N30 M30 P31 R32 R30 AG30 AG32 AH31 AF31 AF30 AE30 AC32 AD30 AN33 AL31 AM33 AL33 AK30 AK32 AJ30 AH30 AH33 AH35 AH34 AH32 AJ33 AL35 AM34 AM35 AF33 AE32 AF34 AE35 AE34 AE33 AB32 AC35 FBA_CLK0 FBA_CLK0_N T32 T31 FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1_N AC31 AC30 FBA_CLK1 FBA_CLK1# FB_VREF 1 VGA@ 2 T30 R1110 10K_0402_5% FBA_DEBUG R1095 FBA_CMD7 10K_0402_5% 1 2 VGA@ R1101 FBA_CMD15 10K_0402_5% 1 2 VGA@ R1096 FBA_CMD18 10K_0402_5% 1 2 VGA@ R1098 FBA_CMD28 10K_0402_5% 1 2 VGA@ R1099 FBA_CMD30 10K_0402_5% 1 2 VGA@ FBA_CLK0 <24> FBA_CLK0# <24> <25> UPDATE 0216 <25> U50C R1100 FBC_CMD7 10K_0402_5% 1 2 VGA@ R1102 FBC_CMD15 10K_0402_5% 1 2 VGA@ R1097 FBC_CMD18 10K_0402_5% 1 2 VGA@ R1103 FBC_CMD28 10K_0402_5% 1 2 VGA@ R1104 FBC_CMD30 10K_0402_5% 1 2 VGA@ Part 3 of 7 FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8 FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 +1.5VS_D FBA_CLK1 <24> FBA_CLK1# <24> B13 D13 A13 A14 C16 B16 A17 D16 C13 B11 C11 A11 C10 C8 B8 A8 E8 F8 F10 F9 F12 D8 D11 E11 D12 E13 F13 F14 F15 E16 F16 F17 D29 F27 F28 E28 D26 F25 D24 E25 E32 F32 D33 E31 C33 F29 D30 E29 B29 C31 C29 B31 C32 B32 B35 B34 A29 B28 A28 C28 C26 D25 B25 A25 VGA@ K27 R1106 60.4_0402_1% L27 2 VGA@ 1 R1107 40.2_0402_1% 2 VGA@ 1 M27 R1108 40.2_0402_1% FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8 FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 MEMORY INTERFACE C FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 Part 2 of 7 FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 <25> FBC_D[0..63] U50B D <25> FBC_DQS[0..7] FBC_DQS#[0..7] FBC_D[0..63] <25> FBC_DQM[0..7] FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8 FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30 C17 B19 D18 F21 A23 D21 B23 E20 G21 F20 F19 F23 A22 C22 B17 F24 C25 E22 C20 B22 A19 D22 D20 E19 D19 F18 C19 F22 C23 B20 A20 FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8 FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30 FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7 A16 D10 F11 D15 D27 D34 A34 D28 FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7 FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7 B14 B10 D9 E14 F26 D31 A31 A26 FBC_DQS#0 FBC_DQS#1 FBC_DQS#2 FBC_DQS#3 FBC_DQS#4 FBC_DQS#5 FBC_DQS#6 FBC_DQS#7 FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7 C14 A10 E10 D14 E26 D32 A32 B26 FBC_DQS0 FBC_DQS1 FBC_DQS2 FBC_DQS3 FBC_DQS4 FBC_DQS5 FBC_DQS6 FBC_DQS7 FBC_CLK0 FBC_CLK0_N E17 D17 FBC_CLK0 FBC_CLK0# FBC_CLK1 FBC_CLK1_N D23 E23 FBC_CLK1 FBC_CLK1# FBC_DEBUG G19 2 VGA@ 1 R1111 10K_0402_5% FBCAL_PD_VDDQ FBCAL_PU_GND FBCAL_TERM_GND C1169 0.01U_0402_16V7K 2 @ N10P-GS-A1_BGA969 10M@ D C B FBC_CLK0 <25> FBC_CLK0# <25> FBC_CLK1 <25> FBC_CLK1# <25> +1.5VS_D N10P-GS-A1_BGA969 10M@ Place Components Close to BGA Memory/PKG +1.05VS_D +FB_PLLVDD L511 1 MBK1608121YZF_0603 2 VGA@ 1 VGA@ VGA@ C1172 C1170 1U_0603_10V4Z 4.7U 6.3V K X5R 0603 2 1 2 VGA@ C1171 0.1U_0402_16V4Z FBVDDQ FBCAL_PU_GND FBCAL_PD_VDDQ FBCAL_TERM_GND DDR3 +1.5VS 40.2 ohm 60.4 ohm 40.2 ohm GDDR3 +1.8VS 40.2 ohm 60.4 ohm 40.2 ohm Must be used 1% resister for driver calibration A A NEAR GPU UNDER GPU Compal Secret Data Security Classification 2007/10/15 Issued Date Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title N10x-GS Memory Size Document Number Custom 4 3 2 Rev 0.1 NIWBA_LA5371P Date: 5 Compal Electronics, Inc. Tuesday, March 24, 2009 Sheet 1 20 of 52 5 4 3 2 1 U50D Part 4 of 7 <29> <29> <29> <29> <29> <29> <29> <29> VGA_LVDS_BCLK VGA_LVDS_BCLK# VGA_LVDS_B0 VGA_LVDS_B0# VGA_LVDS_B1 VGA_LVDS_B1# VGA_LVDS_B2 VGA_LVDS_B2# VGA_LVDS_ACLK VGA_LVDS_ACLK# VGA_LVDS_A0 VGA_LVDS_A0# VGA_LVDS_A1 VGA_LVDS_A1# VGA_LVDS_A2 VGA_LVDS_A2# AM11 AM12 AM8 AL8 AM10 AM9 AK10 AL10 AK11 AL11 IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N VGA_LVDS_BCLK VGA_LVDS_BCLK# VGA_LVDS_B0 VGA_LVDS_B0# VGA_LVDS_B1 VGA_LVDS_B1# VGA_LVDS_B2 VGA_LVDS_B2# AP13 AN13 AN8 AP8 AP10 AN10 AR11 AR10 AN11 AP11 IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N VGA_HDMI_TX2+ VGA_HDMI_TX2VGA_HDMI_TX1+ VGA_HDMI_TX1VGA_HDMI_TX0+ VGA_HDMI_TX0VGA_HDMI_CLK+ VGA_HDMI_CLK- <26> VGA_HDMI_TX2+ <26> VGA_HDMI_TX2<26> VGA_HDMI_TX1+ <26> VGA_HDMI_TX1<26> VGA_HDMI_TX0+ <26> VGA_HDMI_TX0<26> VGA_HDMI_CLK+ <26> VGA_HDMI_CLK- C IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N AR8 AR7 AP7 AN7 AN5 AP5 AR5 AR4 IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N AH6 AH5 AH4 AG4 AF4 AF5 AE6 AE5 IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N <26> VGA_HDMI_SCL 6 R1113 4.7K_0402_5% VGA@ VGA@ Q63A 1 2 2 1 +3VS_D AM7 AM6 AL5 AM5 AM3 AM4 AP1 AR2 A2 A7 B7 C5 C7 D5 D6 D7 E5 E7 F4 G5 G11 G12 G14 G15 G27 G28 G24 G25 H32 J18 J19 J25 J26 L29 M7 M29 P6 P29 R29 U7 V6 Y4 AA4 AB4 AB7 AC5 AD6 AD29 AE29 AF6 AG6 AG20 AG29 AH29 AJ5 AK15 AL7 VDD_SENSE_0 VDD_SENSE_1 VDD_SENSE_2 D35 P7 AD20 1 GND_SENSE_0 GND_SENSE_1 GND_SENSE_2 AD19 E35 R7 1 D C VGA@ AL2 AL3 AJ3 AJ2 AJ1 AH1 AH2 AH3 IFPF_L0 IFPF_L0_N IFPF_L1 IFPF_L1_N IFPF_L2 IFPF_L2_N IFPF_L3 IFPF_L3_N AP2 AN3 IFPC_AUX_I2CW_SCL IFPC_AUX_I2CW_SDA_N AP4 AN4 IFPD_AUX_I2CX_SCL IFPD_AUX_I2CX_SDA_N AE4 AD4 IFPE_AUX_I2CY_SCL IFPE_AUX_I2CY_SDA_N TESTMODE JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N AF3 AF2 IFPF_AUX_I2CZ_SCL IFPF_AUX_I2CZ_SDA_N SERIAL R1112 2 +VGASENSE <48> 0_0402_5% VGA@ R1114 2 0_0402_5% +3VS_D 1 2N7002DW-T/R7_SOT363-6 NC_0 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43 NC_44 NC_45 NC_46 NC_47 NC_48 NC VGA_LVDS_ACLK VGA_LVDS_ACLK# VGA_LVDS_A0 VGA_LVDS_A0# VGA_LVDS_A1 VGA_LVDS_A1# VGA_LVDS_A2 VGA_LVDS_A2# LVDS/TMDS D <29> <29> <29> <29> <29> <29> <29> <29> 2N7002DW-T/R7_SOT363-6 3 4 5 <26> VGA_HDMI_SDA Q63B VGA@ 1 B 2 5V PULL UP IN CONNECTER SIDE +3VS_D A4 PAD AB5 <23> <23> <23> STRAP0 STRAP1 STRAP2 B TESTMODE JTAG_TCK JTAG_TDO JTAG_TRST_N PAD T86 PAD T87 1K_0402_5% VGA@ R1116 C3 D3 C4 D4 NC/SPDIF A5 SPDIF_IN MULTI_STRAP_REF0_GND N9 MULTI_STRAP_REF1_GND M9 1 2 R1119 40.2K_0402_1% 1 VGA@ 2 R1121 40.2K_0402_1% THERMDP THERMDN B5 B4 GENERAL R1120 VGA@ 1 2 10K_0402_5% AP35 AP14 AN14 AN16 AR14 AP16 ROM_CS_N ROM_SI ROM_SO ROM_SCLK +3VS_D T89 2 TEST 2 R1118 4.7K_0402_5% VGA@ @ R1115 10K_0402_5% 1 IFPC_AUX IFPC_AUX_N STRAP0 STRAP1 STRAP2 W5 W7 V7 BUFRST_N CEC STRAP0 STRAP1 STRAP2 ROM_SI ROM_SO ROM_SCLK R1117 10K_0402_5% VGA@ ROM_SI <23> ROM_SO <23> ROM_SCLK <23> PAD T88 VGA@ N10P-GS-A1_BGA969 10M@ A A Compal Secret Data Security Classification 2007/10/15 Issued Date Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title N10P/N10M LVDS,HDMI Size Document Number Custom 4 3 2 Rev 0.1 NIWBA_LA5371P Date: 5 Compal Electronics, Inc. Tuesday, March 24, 2009 Sheet 1 21 of 52 5 4 3 +VGA_CORE U50G VGA@ C1174 .015U_0402_16V7K VGA@ C1184 0.01U_0402_16V7K VGA@ C1176 0.01U_0402_16V7K VGA@ C1182 .015U_0402_16V7K VGA@ C1177 0.01U_0402_16V7K VGA@ C1175 .022U_0402_16V7 VGA@ C1178 0.01U_0402_16V7K VGA@ C1179 0.01U_0402_16V7K VGA@ C1183 .022U_0402_16V7 VGA@ C1180 0.01U_0402_16V7K D VGA@ C1185 .022U_0402_16V7 VGA@ C1186 .022U_0402_16V7 VGA@ C1190 0.22U_0603_10V7K VGA@ C1191 0.22U_0603_10V7K VGA@ C1187 .022U_0402_16V7 1 VGA@ C1189 0.1U_0402_10V7K VGA@ C1188 .022U_0402_16V7 VGA@ C1192 0.1U_0402_16V4Z 2 UNDER GPU 220mA 1 MBK1608121YZF_0603 L512 +IFPAB_PLLVDD 2 VGA@ C1193 4.7U 6.3V K X5R 0603 1 VGA@ C1195 0.1U_0402_16V4Z VGA@ C1194 1U_0603_10V4Z VGA@ 2 1 VGA@ C1196 0.1U_0402_16V4Z 2 1 2 VGA@ C1197 4700P_0402_25V7K 1 2 C AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 AD24 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 M12 M14 M16 M18 M20 M22 M24 P11 P13 P15 P17 P19 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 1 +VGA_CORE Part 7 of 7 22.28A POWER VGA@ C1181 4700P_0402_16V7K +1.05VS_D 2 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 VDD_73 VDD_74 VDD_75 VDD_76 VDD_77 VDD_78 VDD_79 VDD_80 VDD_81 VDD_82 VDD_83 VDD_84 VDD_85 VDD_86 VDD_87 VDD_88 VDD_89 VDD_90 VDD_91 VDD_92 VDD_93 VDD_94 VDD_95 VDD_96 VDD_97 VDD_98 VDD_99 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110 P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24 D +1.05VS_D 1 2 VGA@ C1198 0.1U_0402_16V4Z 1 2 VGA@ C1199 0.1U_0402_16V4Z 1 2 1 VGA@ C1200 0.1U_0402_16V4Z 2 VGA@ C1201 0.1U_0402_16V4Z VGA@ C1202 1U_0402_6.3V6K VGA@ C1203 1U_0402_6.3V6K C UNDER GPU (0-150 Mil) 220mA +IFPD_PLLVDD VGA@ L513 1 2 MBK1608121YZF_0603 +IFPC_PLLVDD 1 C1210 4.7U 6.3V K X5R 0603 1 C1213 1U_0603_10V4Z 2 VGA@ C1214 1U_0603_10V4Z VGA@ C1211 0.1U_0402_16V4Z 2 1 C1215 0.1U_0402_16V4Z VGA@ VGA@ 2 VGA@ +1.5VS_D 220mA 2 VGA@ 150mA +IFPA_IOVDD 1 +1.8VS_D MBK1608121YZF_0603 VGA@ 2 L514 +IFPB_IOVDD VGA@ C1212 4.7U 6.3V K X5R 0603 1 2 VGA@ C1217 1U_0603_10V4Z VGA@ C1218 0.1U_0402_16V4Z 1 2 VGA@ C1219 4700P_0402_25V7K 1 150mA 2 285mA +IFPC_IOVDD B 1 +1.05VS_D MBK1608121YZF_0603 +1.5VS_D 2 +IFPD_IOVDD VGA@ C1226 4.7U 6.3V K X5R 0603 1 2 VGA@ C1227 1U_0603_10V4Z VGA@ C1228 0.1U_0402_16V4Z 1 2 VGA@ C1229 0.1U_0402_16V4Z UNDER GPU VGA@ C1241 0.1U_0402_16V4Z 1 285mA 2 1 R1122 VGA@ C1237 0.01U_0402_16V7K 1 VGA@ 2 L516 VGA@ C1238 0.01U_0402_16V7K 1 2 VGA@ C1242 0.1U_0402_16V4Z VGA@ C1239 0.01U_0402_16V7K 1 2 @ VGA@ C1240 0.01U_0402_16V7K +IFPAB_PLLVDD +IFPAB_RSET 2 1K_0402_5% +IFPA_IOVDD +IFPB_IOVDD +IFPC_PLLVDD VGA@ +IFPC_RSET 2 1 R1123 1K_0402_5% +IFPC_IOVDD VGA@ C1243 0.1U_0402_16V4Z +IFPD_PLLVDD +IFPD_RSET VGA@ 10K_0402_5% 2 1 R1180 +IFPD_IOVDD VGA@ 10K_0402_5% 2 1 R1124 +IFPEF_PLLVDD A VGA@ VGA@ 1 2A Part 5 of 7 1 C1216 0.1U_0402_16V4Z 10M@ N10P-GS-A1_BGA969 U50E 10K_0402_5% 2 1 R1125 +IFPE_IOVDD 2 1 R1126 +IFPF_IOVDD 10K_0402_5% J23 J24 J29 AA27 AA29 AA31 AB27 AB29 AC27 AD27 AE27 AJ28 B18 E21 G17 G18 G22 G8 G9 H29 J14 J15 J16 J17 J20 J21 J22 N27 P27 R27 T27 U27 U29 V27 V29 V34 W27 Y27 FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 AK9 AJ11 IFPAB_PLLVDD IFPAB_RSET AG9 AG10 IFPA_IOVDD IFPB_IOVDD AJ9 AK7 IFPC_PLLVDD IFPC_RSET AJ8 IFPC_IOVDD AC6 AB6 IFPD_PLLVDD IFPD_RSET AK8 IFPD_IOVDD AJ6 AL1 IFPEF_PLLVDD IFPEF_RSET AE7 AD7 IFPE_IOVDD IFPF_IOVDD POWER +3VS_D PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 PEX_IOVDDQ_15 PEX_IOVDDQ_16 PEX_IOVDDQ_17 PEX_IOVDDQ_18 PEX_IOVDDQ_19 PEX_IOVDDQ_20 PEX_IOVDDQ_21 PEX_IOVDDQ_22 PEX_IOVDDQ_23 PEX_IOVDDQ_24 AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16 2 VGA@ C1204 10U_0603_6.3V6M 1 2 VGA@ C1205 10U_0603_6.3V6M 1 2 1 VGA@ C1206 10U_0603_6.3V6M 2 1 VGA@ C1207 10U_0603_6.3V6M 2 VGA@ C1208 10U_0603_6.3V6M 1 2 VGA@ C1209 10U_0603_6.3V6M NEAR GPU (0-750 Mil) +1.05VS_D VGA@ 2 1 2 VGA@ C1220 0.1U_0402_16V4Z VGA@ C1221 1U_0402_6.3V6K VGA@ C1222 1U_0603_10V4Z VGA@ C1223 1U_0603_10V4Z VGA@ C1224 1U_0603_10V4Z UNDER GPU 1 2 1 L515 VGA@ MBK1608121YZF_0603 C1225 4.7U 6.3V K X5R 0603 NEAR GPU B +3VS_D PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 AK16 AK17 AK21 AK24 AK27 PEX_PLLVDD AG14 PEX_SVDD_3V3_0 PEX_SVDD_3V3_1 AG19 F7 VGA@ VGA@ C1230 C1231 0.01U_0402_16V7K 0.1U_0402_10V7K NEAR GPU UNDER GPU 150mA VGA@ C1232 1U_0603_10V4Z 120mA VDD33_0 VDD33_1 VDD33_2 VDD33_3 VDD33_4 J10 J11 J12 J13 J9 +3VS_D VGA@ C1233 0.1U_0402_10V7K VGA@ C1234 0.1U_0402_10V7K UNDER GPU MIOA_VDDQ_0 MIOA_VDDQ_1 MIOA_VDDQ_2 MIOA_VDDQ_3 P9 R9 T9 U9 MIOB_VDDQ_0 MIOB_VDDQ_1 MIOB_VDDQ_2 MIOB_VDDQ_3 AA9 AB9 W9 Y9 VGA@ C1235 1U_0603_10V4Z VGA@ C1236 1U_0603_10V4Z NEAR GPU +3VS_D VGA@ C1244 0.1U_0402_10V7K VGA@ C1245 0.1U_0402_10V7K A 10M@ N10P-GS-A1_BGA969 Compal Secret Data Security Classification Issued Date 2007/10/15 Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. N10x-GS POWER Size C Date: Document Number Rev 0.1 NIWBA_LA5371P Tuesday, March 24, 2009 Sheet 1 22 of 52 5 4 3 2 1 +3VS_D C B A R1138 10K_0402_1% VGA@ 2 X76@ R1137 20K_0402_1% 2 R1136 15K_0402_1% VGA@ 1 1 1 R1135 10K_0402_1% @ 2 R1134 10K_0402_1% VGA@ 2 R1133 10K_0402_1% @ 1 D GPU DEVID RAM_CFG X2 S1024@ GB1 Family GPU Strap Qptions X76_S1024 GPU FB Memory GPU DEVID ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0 X3 Samsung 64Mx16 PD 10K PD 15K PD 20K PU 10K PD 10K PU 45K Hynix 64Mx16 PD 10K PD 15K PD 15K PU 10K PD 10K PU 45K ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0 H1024@ X76_H1024 N10P-GS (0xA34) C X4 S512@ X76_S512 X5 GPU FB Memory H512@ X76_H512 U50 N10M-GS (0xA74) Samsung 64Mx16 PD 10K PD 15K PD 20K PU 10K PD 10K PU 45K Hynix 64Mx16 PD 10K PD 15K PD 15K PU 10K PD 10K PU 45K B N10P-GS 10P@ A N10P-GS-A1_BGA969 10M@ Compal Electronics,Ltd. Compal Secret Data Security Classification 2008/03/25 Issued Date Deciphered Date 2008/04/ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 @ R1132 4.99K_0402_1% 2 @ R1131 2K_0402_5% 2 @ R1130 15K_0402_1% 1 1 1 R1129 45.3K_0402_1% VGA@ 2 1 2 2 R1128 10K_0402_1% @ 1 STRAP2 STRAP1 STRAP0 ROM_SCLK ROM_SI ROM_SO <21> STRAP2 <21> STRAP1 <21> STRAP0 <21> ROM_SCLK <21> ROM_SI <21> ROM_SO R1127 10K_0402_1% VGA@ 2 V18 V20 V22 V24 V31 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 AA2 AA5 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA34 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD2 AD5 AD11 AD13 AD15 AD17 AD21 AD23 AD25 AD31 AD34 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG5 AG31 AG34 AK2 AK5 AK14 AK31 AK34 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AN2 AN34 AP3 AP6 AP9 AP12 AP15 AP18 AP21 AP24 AP27 AP30 AP33 1 GND_97 GND_98 GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 2 1 Part 6 of 7 2 GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND D B3 B6 B9 B12 B15 B21 B24 B27 B30 B33 C2 C34 E6 E9 E12 E15 E18 E24 E27 E30 F2 F31 F34 F5 J2 J5 J31 J34 K9 L9 M2 M5 M11 M13 M15 M17 M19 M21 M23 M25 M31 M34 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24 R2 R5 R31 R34 T11 T13 T15 T17 T19 T21 T23 T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 V2 V5 V9 V12 V14 V16 1 U50F 4 3 2 Title N10x-GS GND & STRAP Size Document Number Custom Rev 0.1 NIWBA_LA5371P Date: Tuesday, March 24, 2009 Sheet 1 23 of 52 5 4 3 2 1 N10x 40nm DDR3 MAPPING NVIDIA COCUMENT FOR DA-3978-001 VREFCA VREFDQ FBA_DQS[0..7] <20> FBA_DQS[0..7] FBA_CMD19 FBA_CMD25 FBA_CMD22 FBA_CMD24 FBA_CMD0 FBA_CMD2 FBA_CMD21 FBA_CMD16 FBA_CMD23 FBA_CMD20 FBA_CMD17 FBA_CMD9 FBA_CMD14 FBA_CMD26 N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 FBA_DQS#[0..7] <20> FBA_DQS#[0..7] FBA_D[0..63] <20> FBA_D[0..63] D FBA_CMD12 FBA_CMD3 FBA_CMD27 M3 N9 M4 <20> FBA_CLK0 <20> FBA_CLK0# FBA_CMD18 J8 K8 K10 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E4 F8 F3 F9 H4 H9 G3 H8 FBA_D5 FBA_D1 FBA_D7 FBA_D0 FBA_D6 FBA_D2 FBA_D3 FBA_D4 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D8 C4 C9 C3 A8 A3 B9 A4 FBA_D13 FBA_D9 FBA_D14 FBA_D11 FBA_D12 FBA_D8 FBA_D15 FBA_D10 U56 VREFC_A2 VREFD_Q2 M9 H2 VREFCA VREFDQ FBA_CMD19 FBA_CMD25 FBA_CMD22 FBA_CMD24 FBA_CMD0 FBA_CMD2 FBA_CMD21 FBA_CMD16 FBA_CMD23 FBA_CMD20 FBA_CMD17 FBA_CMD9 FBA_CMD14 FBA_CMD26 N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 FBA_CMD12 FBA_CMD3 FBA_CMD27 M3 N9 M4 FBA_CLK0 FBA_CLK0# FBA_CMD18 J8 K8 K10 +1.5VS_D VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A2 A9 C2 C10 D3 E10 F2 H3 H10 FBA_CMD30 FBA_CMD29 FBA_CMD1 FBA_CMD10 FBA_CMD11 K2 L3 J4 K4 L4 ODT/ODT0 CS RAS CAS WE FBA_DQS2 FBA_DQS3 F4 C8 DQSL DQSU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10 FBA_DQM2 FBA_DQM3 E8 D4 DML DMU FBA_DQS#2 FBA_DQS#3 G4 B8 DQSL DQSU FBA_CMD15 T3 RESET VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 B10 D2 D9 E3 E9 F10 G2 G10 CK CK CKE/CKE0 +1.5VS_D E4 F8 F3 F9 H4 H9 G3 H8 FBA_D19 FBA_D22 FBA_D18 FBA_D23 FBA_D17 FBA_D21 FBA_D16 FBA_D20 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D8 C4 C9 C3 A8 A3 B9 A4 FBA_D31 FBA_D28 FBA_D29 FBA_D25 FBA_D27 FBA_D24 FBA_D30 FBA_D26 FBA_DQS0 FBA_DQS1 F4 C8 DQSL DQSU FBA_DQM0 FBA_DQM1 E8 D4 DML DMU FBA_DQS#0 FBA_DQS#1 G4 B8 DQSL DQSU FBA_CMD15 T3 RESET NC/ODT1 NC/CS1 NC/CE1 NCZQ1 A1 A11 T1 T11 NC NC NC NC FBA_CMD12 FBA_CMD3 FBA_CMD27 M3 N9 M4 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ FBA_CMD28 FBA_CMD8 FBA_CMD1 FBA_CMD10 FBA_CMD11 K2 L3 J4 K4 L4 ODT/ODT0 CS RAS CAS WE FBA_DQS4 FBA_DQS5 F4 C8 DQSL DQSU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10 FBA_DQM4 FBA_DQM5 E8 D4 DML DMU FBA_DQS#4 FBA_DQS#5 G4 B8 DQSL DQSU FBA_CMD15 T3 RESET L9 ZQ/ZQ0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 B10 D2 D9 E3 E9 F10 G2 G10 ZQ/ZQ0 R1141 240_0402_1% VGA@ J2 L2 J10 L10 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 A1 A11 T1 T11 NC NC NC NC 2 J2 L2 J10 L10 2 R1140 240_0402_1% VGA@ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 A2 A9 C2 C10 D3 E10 F2 H3 H10 CK CK CKE/CKE0 <20> FBA_CLK1 <20> FBA_CLK1# FBA_CMD7 1 ZQ/ZQ0 N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8 VDD VDD VDD VDD VDD VDD VDD VDD VDD BA0 BA1 BA2 L9 1 L9 FBA_CMD19 FBA_CMD25 FBA_CMD4 FBA_CMD6 FBA_CMD5 FBA_CMD13 FBA_CMD21 FBA_CMD16 FBA_CMD23 FBA_CMD20 FBA_CMD17 FBA_CMD9 FBA_CMD14 FBA_CMD26 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E4 F8 F3 F9 H4 H9 G3 H8 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D8 C4 C9 C3 A8 A3 B9 A4 FBA_D40 FBA_D45 FBA_D41 FBA_D46 FBA_D43 FBA_D47 FBA_D42 FBA_D44 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A2 A9 C2 C10 D3 E10 F2 H3 H10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 B10 D2 D9 E3 E9 F10 G2 G10 BA0 BA1 BA2 J8 K8 K10 100-BALL SDRAM DDR3 R1142 240_0402_1% VGA@ CK CK CKE/CKE0 J2 L2 J10 L10 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 A1 A11 T1 T11 NC NC NC NC 100-BALL SDRAM DDR3 K4B1G1646D-HCF8_FBGA100 VREFC_A4 VREFD_Q4 M9 H2 VREFCA VREFDQ FBA_CMD19 FBA_CMD25 FBA_CMD4 FBA_CMD6 FBA_CMD5 FBA_CMD13 FBA_CMD21 FBA_CMD16 FBA_CMD23 FBA_CMD20 FBA_CMD17 FBA_CMD9 FBA_CMD14 FBA_CMD26 N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 FBA_CMD12 FBA_CMD3 FBA_CMD27 M3 N9 M4 +1.5VS_D B3 D10 G8 K3 K9 N2 N10 R2 R10 +1.5VS_D FBA_CLK1 FBA_CLK1# FBA_CMD7 FBA_CMD28 FBA_CMD8 FBA_CMD1 FBA_CMD10 FBA_CMD11 J8 K8 K10 E4 F8 F3 F9 H4 H9 G3 H8 FBA_D60 FBA_D59 FBA_D61 FBA_D63 FBA_D56 FBA_D58 FBA_D57 FBA_D62 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D8 C4 C9 C3 A8 A3 B9 A4 FBA_D48 FBA_D52 FBA_D51 FBA_D54 FBA_D49 FBA_D55 FBA_D50 FBA_D53 FBA_DQS7 FBA_DQS6 F4 C8 DQSL DQSU FBA_DQM7 FBA_DQM6 E8 D4 DML DMU FBA_DQS#7 FBA_DQS#6 G4 B8 DQSL DQSU T3 RESET L9 ZQ/ZQ0 D +1.5VS_D VDD VDD VDD VDD VDD VDD VDD VDD VDD B3 D10 G8 K3 K9 N2 N10 R2 R10 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A2 A9 C2 C10 D3 E10 F2 H3 H10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 B10 D2 D9 E3 E9 F10 G2 G10 CK CK CKE/CKE0 ODT/ODT0 CS RAS CAS WE R1143 240_0402_1% VGA@ J2 L2 J10 L10 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 A1 A11 T1 T11 NC NC NC NC 100-BALL SDRAM DDR3 K4B1G1646D-HCF8_FBGA100 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 BA0 BA1 BA2 K2 L3 J4 K4 L4 FBA_CMD15 1 ODT/ODT0 CS RAS CAS WE VREFCA VREFDQ 2 C K2 L3 J4 K4 L4 M9 H2 B3 D10 G8 K3 K9 N2 N10 R2 R10 +1.5VS_D FBA_CMD30 FBA_CMD29 FBA_CMD1 FBA_CMD10 FBA_CMD11 U57 VREFC_A3 VREFD_Q3 +1.5VS_D B3 D10 G8 K3 K9 N2 N10 R2 R10 BA0 BA1 BA2 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 2 M9 H2 FBA_DQM[0..7] <20> FBA_DQM[0..7] U55 VREFC_A1 VREFD_Q1 +1.5VS_D C 1 U54 FBA_CMD[0..30] <20> FBA_CMD[0..30] 100-BALL SDRAM DDR3 K4B1G1646D-HCF8_FBGA100 K4B1G1646D-HCF8_FBGA100 @ @ C1248 C1250 2 10U_0603_6.3V6M VGA@ 2 C1249 2 VGA@ VGA@ 2 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 2 R1148 1.33K_0402_1% VGA@ VGA@ VGA@ 2 VGA@ VGA@ +1.5VS_D +1.5VS_D 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 1 + C1274 1 C1273 1 C1272 1 C1271 1 C1270 1 C1269 1 C1268 1 C1267 1 C1266 C1265 1 1 1 1 2 1 2 1 C1263 1 C1262 1 C1261 1 C1260 1 C1259 1 C1258 1 C1257 1 C1256 1 C1255 FBA_CLK1# C1254 R1144 243_0402_1% VGA@ R1147 1.33K_0402_1% VGA@ VREFC_A2 1 0.1U_0402_10V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z VREFD_Q2 10MIL VREFD_Q1 1 0.1U_0402_10V6K FBA_CLK1 +1.5VS_D VREFC_A4 R1146 1.33K_0402_1% VGA@ VREFC_A1 10MIL 1 FBA_CLK0# B VREFD_Q4 +1.5VS_D VREFC_A3 R1145 1.33K_0402_1% VGA@ VGA@ 243_0402_1% R1139 VGA@ VREFD_Q3 +1.5VS_D 2 2 10U_0603_6.3V6M 10U_0603_6.3V6M VGA@ VGA@ C1251 2 C1252 FBA_CLK0 10U_0603_6.3V6M 1 1 C1253 C1247 2 10U_0603_6.3V6M 1 1 1 C1246 1 2 10U_0603_6.3V6M 1 2 +1.5VS_D B @ 1 @ 2 C1264 220U_B_2.5VM_R35M VGA@ 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z A VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ A VGA@ VGA@ Compal Secret Data Security Classification Issued Date 2007/10/15 Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. VRAM DDRA Size C Date: Document Number Rev 0.1 NIWBA_LA5371P Tuesday, March 24, 2009 Sheet 1 24 of 52 4 FBC_CMD12 FBC_CMD3 FBC_CMD27 M3 N9 M4 BA0 BA1 BA2 FBC_CLK0 FBC_CLK0# FBC_CMD18 J8 K8 K10 C FBC_D13 FBC_D11 FBC_D14 FBC_D8 FBC_D12 FBC_D10 FBC_D15 FBC_D9 K2 L3 J4 K4 L4 ODT/ODT0 CS RAS CAS WE FBC_DQS0 FBC_DQS1 F4 C8 DQSL DQSU FBC_DQM0 FBC_DQM1 E8 D4 DML DMU FBC_DQS#0 FBC_DQS#1 G4 B8 DQSL DQSU FBC_CMD15 T3 RESET VDD VDD VDD VDD VDD VDD VDD VDD VDD B3 D10 G8 K3 K9 N2 N10 R2 R10 +1.5VS_D FBC_DQS2 FBC_DQS3 F4 C8 DQSL DQSU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10 FBC_DQM2 FBC_DQM3 E8 D4 DML DMU FBC_DQS#2 FBC_DQS#3 G4 B8 DQSL DQSU FBC_CMD15 T3 RESET VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 B10 D2 D9 E3 E9 F10 G2 G10 A1 A11 T1 T11 NC NC NC NC 2 J2 L2 J10 L10 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 A1 A11 T1 T11 NC NC NC NC R1150 240_0402_1% VGA@ M3 N9 M4 BA0 BA1 BA2 <20> FBC_CLK1 <20> FBC_CLK1# +1.5VS_D FBC_CMD7 J8 K8 K10 CK CK CKE/CKE0 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D8 C4 C9 C3 A8 A3 B9 A4 FBC_D41 FBC_D46 FBC_D40 FBC_D47 FBC_D44 FBC_D45 FBC_D42 FBC_D43 A2 A9 C2 C10 D3 E10 F2 H3 H10 FBC_CMD28 FBC_CMD8 FBC_CMD1 FBC_CMD10 FBC_CMD11 K2 L3 J4 K4 L4 ODT/ODT0 CS RAS CAS WE FBC_DQS4 FBC_DQS5 F4 C8 DQSL DQSU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10 FBC_DQM4 FBC_DQM5 E8 D4 DML DMU FBC_DQS#4 FBC_DQS#5 G4 B8 DQSL DQSU FBC_CMD15 T3 RESET L9 ZQ/ZQ0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 B10 D2 D9 E3 E9 F10 G2 G10 R1151 240_0402_1% VGA@ VREFC_A8 VREFD_Q8 M9 H2 VREFCA VREFDQ FBC_CMD19 FBC_CMD25 FBC_CMD4 FBC_CMD6 FBC_CMD5 FBC_CMD13 FBC_CMD21 FBC_CMD16 FBC_CMD23 FBC_CMD20 FBC_CMD17 FBC_CMD9 FBC_CMD14 FBC_CMD26 N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 FBC_CMD12 FBC_CMD3 FBC_CMD27 M3 N9 M4 BA0 BA1 BA2 FBC_CLK1 FBC_CLK1# FBC_CMD7 J8 K8 K10 CK CK CKE/CKE0 +1.5VS_D VDD VDD VDD VDD VDD VDD VDD VDD VDD B3 D10 G8 K3 K9 N2 N10 R2 R10 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E4 F8 F3 F9 H4 H9 G3 H8 FBC_D52 FBC_D51 FBC_D55 FBC_D50 FBC_D53 FBC_D49 FBC_D54 FBC_D48 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D8 C4 C9 C3 A8 A3 B9 A4 FBC_D63 FBC_D57 FBC_D61 FBC_D59 FBC_D60 FBC_D56 FBC_D62 FBC_D58 +1.5VS_D VDD VDD VDD VDD VDD VDD VDD VDD VDD B3 D10 G8 K3 K9 N2 N10 R2 R10 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A2 A9 C2 C10 D3 E10 F2 H3 H10 FBC_CMD28 FBC_CMD8 FBC_CMD1 FBC_CMD10 FBC_CMD11 K2 L3 J4 K4 L4 ODT/ODT0 CS RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A2 A9 C2 C10 D3 E10 F2 H3 H10 FBC_DQS6 FBC_DQS7 F4 C8 DQSL DQSU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10 FBC_DQM6 FBC_DQM7 E8 D4 DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10 FBC_DQS#6 FBC_DQS#7 G4 B8 DQSL DQSU FBC_CMD15 T3 RESET L9 J2 L2 J10 L10 ZQ/ZQ0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 B10 D2 D9 E3 E9 F10 G2 G10 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 A1 A11 T1 T11 NC NC NC NC R1152 240_0402_1% VGA@ J2 L2 J10 L10 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 B10 D2 D9 E3 E9 F10 G2 G10 A1 A11 T1 T11 NC NC NC NC 100-BALL SDRAM DDR3 K4B1G1646D-HCF8_FBGA100 100-BALL SDRAM DDR3 K4B1G1646D-HCF8_FBGA100 100-BALL SDRAM DDR3 K4B1G1646D-HCF8_FBGA100 100-BALL SDRAM DDR3 K4B1G1646D-HCF8_FBGA100 @ @ @ @ C1278 1 10U_0603_6.3V6M 1 1 10U_0603_6.3V6M 1 1 C1279 C1281 2 10U_0603_6.3V6M VGA@ +1.5VS_D R1153 243_0402_1% VGA@ 1 VGA@ C1280 2 VGA@ VGA@ VGA@ 2 VREFC_A6 VREFD_Q6 10MIL 1 2 C1293 220U_B_2.5VM_R35M VGA@ VREFC_A7 VREFD_Q7 VREFC_A8 1 R1157 1.33K_0402_1% VGA@ 10MIL VREFD_Q5 2 +1.5VS_D R1158 1.33K_0402_1% VGA@ VGA@ VREFD_Q8 1 2 0.1U_0402_10V6K + +1.5VS_D R1156 1.33K_0402_1% VGA@ VREFC_A5 0.1U_0402_10V6K 1 +1.5VS_D C1292 C1291 C1290 C1289 C1288 C1287 C1286 C1285 C1284 C1283 2 +1.5VS_D R1155 1.33K_0402_1% VGA@ 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z VGA@ R1154 243_0402_1% VGA@ C C1282 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 1 1 1 1 1 1 1 1 1 1 VGA@ +1.5VS_D B 2 2 2 10U_0603_6.3V6M 10U_0603_6.3V6M VGA@ D +1.5VS_D VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ ZQ/ZQ0 2 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 FBC_CMD12 FBC_CMD3 FBC_CMD27 B3 D10 G8 K3 K9 N2 N10 R2 R10 1 1 L9 FBC_D31 FBC_D25 FBC_D29 FBC_D27 FBC_D28 FBC_D26 FBC_D30 FBC_D24 CK CK CKE/CKE0 ODT/ODT0 CS RAS CAS WE 2 FBC_CLK1# J8 K8 K10 K2 L3 J4 K4 L4 C1277 FBC_CLK1 FBC_CLK0 FBC_CLK0# FBC_CMD18 D8 C4 C9 C3 A8 A3 B9 A4 VDD VDD VDD VDD VDD VDD VDD VDD VDD FBC_CMD30 FBC_CMD29 FBC_CMD1 FBC_CMD10 FBC_CMD11 +1.5VS_D 10U_0603_6.3V6M 1 FBC_CLK0# BA0 BA1 BA2 A2 A9 C2 C10 D3 E10 F2 H3 H10 B FBC_CLK0 M3 N9 M4 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8 +1.5VS_D VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ ZQ/ZQ0 J2 L2 J10 L10 R1149 240_0402_1% VGA@ FBC_CMD12 FBC_CMD3 FBC_CMD27 +1.5VS_D CK CK CKE/CKE0 FBC_CMD30 FBC_CMD29 FBC_CMD1 FBC_CMD10 FBC_CMD11 L9 D8 C4 C9 C3 A8 A3 B9 A4 FBC_CMD19 FBC_CMD25 FBC_CMD4 FBC_CMD6 FBC_CMD5 FBC_CMD13 FBC_CMD21 FBC_CMD16 FBC_CMD23 FBC_CMD20 FBC_CMD17 FBC_CMD9 FBC_CMD14 FBC_CMD26 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 FBC_D37 FBC_D33 FBC_D39 FBC_D35 FBC_D36 FBC_D32 FBC_D38 FBC_D34 1 <20> FBC_CLK0 <20> FBC_CLK0# DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VREFCA VREFDQ U61 E4 F8 F3 F9 H4 H9 G3 H8 2 D A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 M9 H2 1 FBC_D[0..63] <20> FBC_D[0..63] N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8 VREFC_A7 VREFD_Q7 2 FBC_DQS#[0..7] FBC_CMD19 FBC_CMD25 FBC_CMD22 FBC_CMD24 FBC_CMD0 FBC_CMD2 FBC_CMD21 FBC_CMD16 FBC_CMD23 FBC_CMD20 FBC_CMD17 FBC_CMD9 FBC_CMD14 FBC_CMD26 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 FBC_D21 FBC_D23 FBC_D16 FBC_D18 FBC_D19 FBC_D22 FBC_D17 FBC_D20 C1276 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 VREFCA VREFDQ E4 F8 F3 F9 H4 H9 G3 H8 1 N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8 M9 H2 2 FBC_CMD19 FBC_CMD25 FBC_CMD22 FBC_CMD24 FBC_CMD0 FBC_CMD2 FBC_CMD21 FBC_CMD16 FBC_CMD23 FBC_CMD20 FBC_CMD17 FBC_CMD9 FBC_CMD14 FBC_CMD26 U60 VREFC_A6 VREFD_Q6 C1275 FBC_DQS[0..7] DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 FBC_D5 FBC_D3 FBC_D6 FBC_D0 FBC_D4 FBC_D1 FBC_D7 FBC_D2 1 <20> FBC_DQS#[0..7] VREFCA VREFDQ FBC_DQM[0..7] U59 E4 F8 F3 F9 H4 H9 G3 H8 1 <20> FBC_DQS[0..7] M9 H2 2 <20> FBC_DQM[0..7] VREFC_A5 VREFD_Q5 1 1 <20> FBC_CMD[0..30] U58 FBC_CMD[0..30] 2 2 N10x 40nm DDR3 MAPPING NVIDIA COCUMENT FOR DA-3978-001 3 2 5 VGA@ C1303 C1302 C1301 C1300 C1299 C1298 C1297 C1296 C1295 C1294 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z A A Compal Secret Data Security Classification Issued Date 2007/10/15 Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. VRAM DDRA Size Document Number Custom Date: Rev 0.1 NIWBA_LA5371P Tuesday, March 24, 2009 Sheet 1 25 of 52 5 4 3 2 1 HDMI switch1 +3VS HYBRID@ U68 <21> <21> <21> <21> <21> <21> <21> <21> D L15 1 1 L16 <21> VGA_HDMI_SDA <21> VGA_HDMI_SCL DIS@ DIS@ C462 C461 C464 C463 C466 C465 C468 C467 VGA_HDMI_CLK+ VGA_HDMI_CLKVGA_HDMI_TX0+ VGA_HDMI_TX0VGA_HDMI_TX1+ VGA_HDMI_TX1VGA_HDMI_TX2+ VGA_HDMI_TX2- 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ MBK1608121YZF_0603 VGA_HDMIDAT_SW 2 VGA_HDMICLK_SW 2 MBK1608121YZF_0603 C469 DIS@ 1 1 C470 2 DIS@ 2 12P_0402_50V8J 12P_0402_50V8J HDMI_CLK+_SW 48 0.1U_0402_16V7K HDMI_CLK-_SW 47 0.1U_0402_16V7K HDMI_TX0+_SW 43 0.1U_0402_16V7K HDMI_TX0-_SW 42 0.1U_0402_16V7K 0.1U_0402_16V7K HDMI_TX1+_SW 37 HDMI_TX1-_SW 36 0.1U_0402_16V7K HDMI_TX2+_SW 32 0.1U_0402_16V7K 0.1U_0402_16V7K HDMI_TX2-_SW 31 VGA_HDMIDAT_SW 22 VGA_HDMICLK_SW 23 HDMI_CLK+ HDMI_CLKHDMI_TX0+ HDMI_TX0HDMI_TX1+ HDMI_TX1HDMI_TX2+ HDMI_TX2HDMIDAT_SW HDMICLK_SW <27> HDMI_CLK+ <27> HDMI_CLK<27> HDMI_TX0+ <27> HDMI_TX0<27> HDMI_TX1+ <27> HDMI_TX1<27> HDMI_TX2+ <27> HDMI_TX2<27> HDMIDAT_SW <27> HDMICLK_SW 46 45 41 40 35 34 30 29 25 26 0B2 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 52 5 54 51 NC NC NC NC 57 Thermal_GND 4 10 18 27 38 50 56 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 2 3 7 8 11 12 14 15 19 20 SEL 17 GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1 6 9 13 16 21 24 28 33 39 44 49 53 55 HYBRID@ C1001 4.7U_0805_10V4Z 2 HDMI_CLK+_CK HDMI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK HDMIDAT_R HDMICLK_R DGPU_SELECT# 0_0402_5% 0_0402_5% HDMI_TX0-_SW HDMI_TX0+_SW 0_0402_5% 0_0402_5% HDMI_TX1-_SW HDMI_TX1+_SW 0_0402_5% 0_0402_5% HDMI_TX2-_SW HDMI_TX2+_SW 0_0402_5% 0_0402_5% VGA_HDMIDAT_SW VGA_HDMICLK_SW 0_0402_5% 0_0402_5% HDMI_CLKHDMI_CLK+ 0_0402_5% 0_0402_5% HDMI_TX0HDMI_TX0+ 0_0402_5% 0_0402_5% HDMI_TX1HDMI_TX1+ 0_0402_5% 0_0402_5% HDMI_TX2HDMI_TX2+ 0_0402_5% 0_0402_5% HDMICLK_SW HDMIDAT_SW 0_0402_5% 0_0402_5% DGPU_SELECT# <16,28,29> 2 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ DIS@ 1 R638 1 R640 HDMI_CLK-_CK HDMI_CLK+_CK 1 R642 1 R644 HDMI_TX0-_CK HDMI_TX0+_CK 1 R673 1 R674 HDMI_TX1-_CK HDMI_TX1+_CK 1 R648 1 R654 HDMI_TX2-_CK HDMI_TX2+_CK 1 R661 1 R646 1 R671 1 R650 2 2 UMA@ 2 UMA@ 1 2 1 UMA@ 2 UMA@ 1 2 1 UMA@ 2 UMA@ 1 2 1 UMA@ 2 UMA@ 1 2 1 UMA@ UMA@ D HDMIDAT_R HDMICLK_R HDMI_CLK-_CK HDMI_CLK+_CK R658 R652 HDMI_TX0-_CK HDMI_TX0+_CK R662 R656 HDMI_TX1-_CK HDMI_TX1+_CK R660 R672 HDMI_TX2-_CK HDMI_TX2+_CK R676 R675 HDMICLK_R HDMIDAT_R DGPU_SELECT DGPU_SELECT# 2 <28,29> DGPU_SELECT R242 HDMI_TX2-_CONN R243 1 1 Q77A 2N7002DW-T/R7_SOT363-6 R266 DIS@ 0_0402_5% 1 2 499_0402_1% 499_0402_1% 499_0402_1% 499_0402_1% S 499_0402_1% HDMI_DET_UMA +5VS R250 10K_0402_1% 1 2 2 HDMI_CLK+_CONN HDMI_DET_VGA 4 4 3 3 HDMI_CLK-_CONN @ D6 RB751V_SOD323 2 WCM-2012-900T_4P 1 HDMI_TX0-_CK 4 1 4 2 2 HDMI_TX0+_CONN 3 3 HDMI_TX0-_CONN R493 100K_0402_5% DIS@ 1 MBK1608121YZF_0603 1 HDMI_TX1-_CK 4 4 2 2 HDMI_TX1+_CONN L19 3 3 HDMI_TX1-_CONN HDMIDAT_R HDMICLK_R +5VS HDMI_TX2-_CK 4 1 2 2 4 3 3 B +5VS_HDMI 1 C471 0.1U_0402_16V4Z 2 R246 2.2K_0402_5% HDMIDAT_R HDMICLK_R 3 3 1 HDMI_TX2+_CONN 2 HDMI_TX2-_CONN HDMI_CLK-_CONN HDMI_CLK+_CONN HDMI_TX0-_CONN HDMI_TX0+_CONN HDMI_TX1-_CONN HDMI_TX1+_CONN HDMI_TX2-_CONN HDMI_TX2+_CONN +5VS L21 1 R245 2.2K_0402_5% DIS@ C472 330P_0402_50V7K WCM-2012-900T_4P HDMI_TX2+_CK @ D5 BAT54S-7-F_SOT23-3 2 L20 1 D4 RB491D_SC59-3 JHDMI WCM-2012-900T_4P HDMI_TX1+_CK @ 1 L18 HDMI_TX0+_CK R244 0_0805_5% DIS@ 1 HDMI_CLK-_CK 2 2 1 1 Q77B 2N7002DW-T/R7_SOT363-6 UMA@ R262 2 1 0_0402_5% +5VS 2 +3VS G DIS@ Q2 2N7002W-T/R7_SOT323-3 L17 1 HDMI_DET_UMA 3 D 499_0402_1% NEAR CONNECT HDMI_CLK+_CK 4 2 HDMI_TX2+_CONN 1 HDMI_DETECT <27> HDMI_DETECT 1 R241 1 HDMI_DET_VGA 6 2 R240 HDMI_TX1-_CONN 1 1 2 R239 HDMI_TX1+_CONN HDMI_DETECT_VGA 1 HDMI_TX0-_CONN 1 <19> HDMI_DETECT_VGA 499_0402_1% HYBRID@ 2 R238 499_0402_1% 1 HDMI_TX0+_CONN 1 3 R237 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ HYBRID@ 1 R236 HDMI_CLK-_CONN 1 3 HDMI_CLK+_CONN C 5 TMDS pull down (500ohm) resistors G9x only A 1 HYBRID@ C995 0.1U_0402_16V4Z HDMI_CLK-_SW HDMI_CLK+_SW TS3DV520ERHUR_QFN56_11X5~D C B 0B1 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 VCC VCC VCC VCC VCC VCC VCC HDMIDAT_R @ D7 BAT54S-7-F_SOT23-3 1 HDMICLK_R +5V SDA SCL HP_DET 12 10 9 7 6 4 3 1 CKCK+ D0D0+ D1D1+ D2D2+ CEC Reserved 13 14 GND GND GND GND GND GND GND GND DDC/CEC_GND 2 5 8 11 20 21 22 23 17 SUYIN_100042MR019S153ZL @ D8 BAT54S-7-F_SOT23-3 2 18 16 15 19 A WCM-2012-900T_4P HDMI_CLK+_CK HDMI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK R251 R252 R253 R254 R255 R256 R257 R258 5 1 1 1 1 1 1 1 1 @ @ @ @ @ @ @ @ 2 2 2 2 2 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% HDMI_CLK+_CONN HDMI_CLK-_CONN HDMI_TX0+_CONN HDMI_TX0-_CONN HDMI_TX1+_CONN HDMI_TX1-_CONN HDMI_TX2+_CONN HDMI_TX2-_CONN Compal Electronics,Ltd. Compal Secret Data Security Classification 2008/03/25 Issued Date Deciphered Date 2008/04/ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title Level Shiftter_PS8101T Size Document Number Custom Rev 0.1 KIWB1/B2_LA4601P Date: Tuesday, March 24, 2009 Sheet 1 26 of 52 5 4 3 2 1 D D +3VS FOR 7318C 1 P/N:SA00002D700 (8101T) P/N:SA00001U900 (CH7318A) @ R223 0_0402_5% 2 U17 +3VS 25 OE# SCL_SINK +3VS 28 <26> HDMIDAT_SW HDMIDAT_SW 29 HDMI_DETECT 30 HPD_SINK 32 DDC_EN 34 35 CFG0 CFG1 internal pull down VCC VCC VCC VCC VCC VCC VCC VCC output SDA_SINK 1 +3VS @ R226 0_0402_5% 4.7K_0402_5% 2 @ 2 @ 4.7K_0402_5% R228 1 PC1 4 R230 1 3 PC0 internal pull down R613 4.7K_0402_5% @ input 1 1 R612 4.7K_0402_5% @ 2 UMA@ C457 0.1U_0402_16V4Z 1 2 UMA@ C458 0.1U_0402_16V4Z 1 2 UMA@ C459 0.1U_0402_16V4Z 1 2 UMA@ C460 10U_0805_10V4Z R615 20K_0402_1% @ TMDS_B_HPD# R614 7.5K_0402_1% @ +3VS 2 2 2 R227 1 R229 1 1 R231 1 2 UMA@ 4.7K_0402_5% 4.7K_0402_5% 2 @ 2 UMA@ 499_0402_1% REXT 6 HPD# 7 SDA 8 HDMIDAT_NB <15> SCL 9 HDMICLK_NB RT_EN# 10 TMDS_B_HPD# C 2 <26> HDMI_DETECT 2 11 15 21 26 33 40 46 1 2 HDMICLK_SW 2 R225 4.7K_0402_5% UMA@ <26> HDMICLK_SW 2 1 @ R224 0_0402_5% 1 1 +3VS C PIN6 PULL DOWN 1.2Kohm PIN7 PULL DOWN 7.5Kohm PIN7 PULL UP 20Kohm TMDS_B_HPD# <15> <15> pull up by PCH side <15> TMDS_B_CLK <15> TMDS_B_CLK# 48 47 IN_D4+ IN_D4- OUT_D4+ OUT_D4- 13 14 HDMI_CLK+ HDMI_CLK- <15> TMDS_B_DATA0 <15> TMDS_B_DATA0# 45 44 IN_D3+ IN_D3- OUT_D3+ OUT_D3- 16 17 HDMI_TX0+ HDMI_TX0- <15> TMDS_B_DATA1 <15> TMDS_B_DATA1# 42 41 IN_D2+ IN_D2- OUT_D2+ OUT_D2- 19 20 HDMI_TX1+ HDMI_TX1- <15> TMDS_B_DATA2 <15> TMDS_B_DATA2# 39 38 IN_D1+ IN_D1- OUT_D1+ OUT_D1- 22 23 HDMI_TX2+ HDMI_TX2- GND GND GND GND GND GND GND GND GND GND PAD 1 5 12 18 24 27 31 36 37 43 49 HDMI_CLK+ <26> HDMI_CLK- <26> HDMI_TX0+ <26> HDMI_TX0- <26> HDMI_TX1+ <26> HDMI_TX1- <26> HDMI_TX2+ <26> HDMI_TX2- <26> B B UMA@ PS8101TQFN48G_QFN48_7X7 A A Compal Electronics,Ltd. Compal Secret Data Security Classification 2008/03/25 Issued Date Deciphered Date 2008/04/ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Level Shiftter_PS8101T Size Document Number Custom Rev 0.1 KIWB1/B2_LA4601P Date: Tuesday, March 24, 2009 Sheet 1 27 of 52 A B DAC_RED 1 1 2 R669 UMA@ 0_0402_5% DAC_GRN 1 2 R670 UMA@ 0_0402_5% DAC_BLU 1 2 R668 UMA@ 0_0402_5% CRT_R VGA_CRT_R 1 2 R1337 DIS@ 0_0402_5% VGA_CRT_G 1 2 R1338 DIS@ 0_0402_5% VGA_CRT_B 1 2 R1339 DIS@ 0_0402_5% CRT_R CRT_G C +5VS +5VS +5VS 3 3 3 3 3 BLUE 1 2 GREEN 1 2 @ D39 BAT54S-7-F_SOT23-3 DIS only <15> DAC_RED <15> DAC_GRN <15> DAC_BLU <15> CRT_HSYNC DAC_RED DAC_GRN DAC_BLU CRT_HSYNC 3 6 10 13 1B2 2B2 3B2 4B2 1A 2A 3A 4A DGPU_SELECT# 1 15 DGPU_SELECT# <16,26,29> L: B1 -> A(VGA) H: B2 -> A(PCH) CRT_R CRT_G CRT_B HSYNC_G_A 4 7 9 12 1 1 R1161 150_0402_1% 2 1B1 2B1 3B1 4B1 SEL OE# 2 2 5 11 14 R1160 150_0402_1% 1 C1304 C1305 2 2 2 C1306 10P_0402_50V8J D42 GREEN GND CRT Connector 1 1 2 1 RB491D_SC59-3 1.1A_6V_SMD1812P110TF W=40mils BLUE 1 2 2 JCRT1 C1309 10P_0402_50V8J RED GREEN 10P_0402_50V8J CLOSE TO CONN 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J BLUE JVGA_VS +3VS JVGA_HS CRT_DDC_DAT_CONN CRT_DDC_CLK_CONN R1322 10K_0402_5% 8 DGPU_SELECT 1 FSAV330MTC_TSSOP16 HYBRID@ DGPU_SELECT <26,29> 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND1 GND2 ACES_87213-1200G ME@ 1 2 G Q25 2N7002_SOT23 3 2 D S +CRT_VCC 1 HSYNC_G_A DGPU_SELECT# 1 0_0402_5% 2 HSYNC_G CRT_DDC_CLK 2 1 2 L: B1 -> A(VGA) H: B2 -> A(PCH) DIS@ R1375 1 P 0_0402_5% 2 2 A G 1 0_0402_5% 2 Y 4 CRT_VSYNC_1 1 @ C1312 10P_0402_50V8J JVGA_VS 2 MBK1608121YZF_0603 1 L521 U69 SN74AHCT1G125DCKR_SC70-5 CRT_DDC_DAT_CONN 3 JVGA_HS 2 MBK1608121YZF_0603 L520 1K_0402_5% 5 5 1 2 3 1 UMA@ R1376 2 4 R275 1 C1333 0.1U_0402_16V4Z <19> VGA_VSYNC CRT_DDC_DATA CRT_HSYNC_1 4 U62 SN74AHCT1G125DCKR_SC70-5 1 <15> CRT_VSYNC 2 <15> CRT_DDC_CLK 2 2 UMA@ R1185 2.2K_0402_5% 2 <15> CRT_DDC_DATA 1 1 1 UMA@ R1183 2.2K_0402_5% L: B1 -> A(VGA) B2 -> A(PCH) Y +CRT_VCC UMA@ R1340 H: 0_0402_5% HYBRID@ A OE# 2 1 R1377 +3VS HSYNC_G 0_0402_5% 2 OE# DIS@ R1374 1 P 0_0402_5% 2 G 1 1 2 3 <19> VGA_HSYNC 3 2 1K_0402_5% 5 C1311 0.1U_0402_16V4Z UMA@ R1373 R1342 0_0402_5% UMA@ 2 1 <15> CRT_HSYNC +3VS R276 HYBRID@ C1310 0.1U_0402_16V4Z 2 1 C1308 1 F1 2 C1307 2 @ D44 BAT54S-7-F_SOT23-3 +CRT_VCC +5VS RED JVGA_VS 1 2 @ D43 BAT54S-7-F_SOT23-3 2 VGA_CRT_R VGA_CRT_G VGA_CRT_B VGA_HSYNC VCC 1 R1159 150_0402_1% 2 16 <19> <19> <19> <19> 1 CRT_B U47 JVGA_HS 1 2 @ D41 MBK1608121YZF_0603 1 2 L517 MBK1608121YZF_0603 1 2 L518 MBK1608121YZF_0603 1 2 L519 1 1 CRT_R CRT_G +5VS RED 1 BAT54S-7-F_SOT23-3 2 @ D40 BAT54S-7-F_SOT23-3 CRT_G CRT_B E +5VS UMA only CRT_B D +5VS 2 3 @ C1313 10P_0402_50V8J Q71B UMA@ 2N7002DW-T/R7_SOT363-6 1 CRT_DDC_CLK_CONN 6 Q71A UMA@ 2N7002DW-T/R7_SOT363-6 +CRT_VCC Place closed to chipset <19> VGA_DDCCLK VGA_DDCCLK 1 DGPU_SELECT# 1 CRT_VSYNC_1 4 Y 5 A U65 SN74AHCT1G125DCKR_SC70-5 HYBRID@ 2 VGA_VSYNC <19> G 4 U63 SN74AHCT1G125DCKR_SC70-5 HYBRID@ P 1 Y HYBRID@ C1342 0.1U_0402_16V4Z 3 A OE# 2 1 2 5 2 P CRT_DDC_DAT_CONN DGPU_SELECT L: B1 -> A(VGA) H: B2 -> A(PCH) G 1 1 3 4 Q64B DIS@ 2N7002DW-T/R7_SOT363-6 6 Q64A DIS@ @ C1315 2N7002DW-T/R7_SOT363-6 100P_0402_50V8J A <15> CRT_VSYNC R1166 2.2K_0402_5% 2 5 4 DIS@ +CRT_VCC 1 3 1 DIS@ 2 VGA_DDCDATA 2 <19> VGA_DDCDATA HYBRID@ C1314 0.1U_0402_16V4Z 2.2K R1165 2.2K_0402_5% 2 4 R1341 0_0402_5% HYBRID@ R1164 2.2K_0402_5% DIS@ 2 R1163 2.2K_0402_5% DIS@ DGPU_SELECT <26,29> +CRT_VCC R1343 0_0402_5% DIS@ 1 1 1 +3VS 2 2 DGPU_SELECT OE# +3VS B 1 2 CRT_DDC_CLK_CONN 1 @ C1316 68P_0402_50V8K 2 Compal Secret Data Security Classification 2007/10/15 Issued Date Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C D Title Compal Electronics, Inc. CRT & TV-OUT Connector Size Document Number Custom Rev 0.1 NIWBA_LA5371P Date: Tuesday, March 24, 2009 Sheet E 28 of 52 5 4 3 2 1 B+ INVT_PWM LCD POWER CIRCUIT R1167 150_0603_1% 1 +3VS R1168 100K_0402_5% W=60mils 1 C1319 1 @ 2 IN 3 1 2 GND OUT 1 1 3 +LCDVDD_CONN 2 @ 680P_0402_50V7K C1326 W=60mils Q67 DTC124EKAT146_SC59-3 C1322 4.7U_0805_10V4Z 2 1 1 2 1 2 <37> LCD_COLOR <37> INVT_PWM 2 DISPOFF# <37> DAC_BRIG +3VS +LCDVDD_CONN +LCDVDD MBK1608121YZF_0603 1 2 L522 R1170 @ 100K_0402_5% (60 MIL) +3VS SI2301BDS-T1-E3_SOT23-3 C1318 Q66 0.1U_0402_16V4Z C1324 680P_0402_50V7K @ 1 1 2 2 C1325 4.7U_0805_25V6-K JLVDS1 2 2 1 2 1 3 LCD_ENVDD VGA LCD/PANEL BD. Conn. 4.7U_0805_10V4Z D DTC124EK 2 2 1 @ C1321 G 1 220K_0402_5% S 2 G Q65 2N7002_SOT23 S R1169 2 1 2 L523 MBK1608121YZF_0603 DISPOFF# For EMI C1317 D D 1 @ C1320 470P_0402_50V7K +5VALW 470P_0402_50V7K DAC_BRIG 470P_0402_50V7K +LCDVDD +LEDVDD R1172 2.2K_0402_5% R1173 2.2K_0402_5% CONN_LVDS_SCL CONN_LVDS_SDA C1323 0.1U_0402_16V4Z 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND 42 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 GND +LEDVDD +LCDVDD_CONN D +3VS CONN_LVDS_B2# CONN_LVDS_B2 CONN_LVDS_BCLK# CONN_LVDS_BCLK CONN_LVDS_B1# CONN_LVDS_B1 CONN_LVDS_A0# CONN_LVDS_A0 CONN_LVDS_B0 CONN_LVDS_B0# CONN_LVDS_A1 CONN_LVDS_A1# CONN_LVDS_A2# CONN_LVDS_A2 CONN_LVDS_ACLK# CONN_LVDS_ACLK ACES_87142-4041 LVDS switch1 +3VS HYBRID@ U67 LVDS_A0# LVDS_A0 LVDS_ACLK LVDS_ACLK# LVDS_A2 LVDS_A2# LVDS_A1# LVDS_A1 EDID_CLK EDID_DATA 46 45 41 40 35 34 30 29 25 26 B 0B2 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 52 5 54 51 NC NC NC NC 57 Thermal_GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 2 3 7 8 11 12 14 15 19 20 CONN_LVDS_A0# CONN_LVDS_A0 CONN_LVDS_ACLK CONN_LVDS_ACLK# CONN_LVDS_A2 CONN_LVDS_A2# CONN_LVDS_A1# CONN_LVDS_A1 CONN_LVDS_SCL CONN_LVDS_SDA SEL 17 DGPU_SELECT# GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1 6 9 13 16 21 24 28 33 39 44 49 53 55 +3VS C853 0.1U_0402_16V4Z 2 HYBRID@ C854 4.7U_0805_10V4Z DGPU_SELECT# <16,26,28> L: B1 -> A(VGA) H: B2 -> A(PCH) VGA_LVDS_SCL 0_0402_5% VGA_LVDS_SDA 0_0402_5% 2 DIS@ 2 DIS@ 1 R1360 CONN_LVDS_SCL 1 R1361 CONN_LVDS_SDA VGA_LVDS_A0 VGA_LVDS_A0# 2 DIS@ 2 DIS@ 1 R1344 CONN_LVDS_A0 1 R1345 CONN_LVDS_A0# 0_0402_5% 0_0402_5% VGA_LVDS_A1 VGA_LVDS_A1# 0_0402_5% 0_0402_5% 2 DIS@ 2 DIS@ 1 R1358 CONN_LVDS_A1 1 R1359 CONN_LVDS_A1# VGA_LVDS_A2 VGA_LVDS_A2# 0_0402_5% 0_0402_5% 2 DIS@ 2 DIS@ 1 R1346 CONN_LVDS_A2 1 R1348 CONN_LVDS_A2# VGA_LVDS_ACLK 0_0402_5% VGA_LVDS_ACLK#0_0402_5% 2 DIS@ 2 DIS@ 1 R1355 CONN_LVDS_ACLK 1 R1347 CONN_LVDS_ACLK# VGA_LVDS_B0 VGA_LVDS_B0# 0_0402_5% 0_0402_5% 2 DIS@ 2 DIS@ 1 R1356 CONN_LVDS_B0 1 R1349 CONN_LVDS_B0# VGA_LVDS_B1 VGA_LVDS_B1# 0_0402_5% 0_0402_5% 2 DIS@ 2 DIS@ 1 R1350 CONN_LVDS_B1 1 R1351 CONN_LVDS_B1# VGA_LVDS_B2 VGA_LVDS_B2# 0_0402_5% 0_0402_5% 2 DIS@ 2 DIS@ 1 R1352 CONN_LVDS_B2 1 R1353 CONN_LVDS_B2# VGA_LVDS_BCLK 0_0402_5% VGA_LVDS_BCLK#0_0402_5% 2 DIS@ 2 DIS@ 1 R1354 CONN_LVDS_BCLK 1 R1357 CONN_LVDS_BCLK# 1 C HYBRID@ 1 R1171 D45 <37> BKOFF# R265 A <15> LVDS_B0# <15> LVDS_B0 <15> LVDS_B1 <15> LVDS_B1# <15> LVDS_BCLK <15> LVDS_BCLK# <15> LVDS_B2 <15> LVDS_B2# LVDS_B0# LVDS_B0 LVDS_B1 LVDS_B1# LVDS_BCLK LVDS_BCLK# LVDS_B2 LVDS_B2# 46 45 41 40 35 34 30 29 25 26 0B2 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 52 5 54 51 NC NC NC NC 57 Thermal_GND 0_0402_5% DGPU_SELECT 1 <19> VGA_ENVDD_R 4 <19> VGA_ENBKL_R DGPU_SELECT <26,28> L: B1 -> A(PCH) H: B2 -> A(VGA) HYBRID@ 6 Q73A 2N7002DW-T/R7_SOT363-6 3 HYBRID@ Q73B 2N7002DW-T/R7_SOT363-6 B DIS@ R261 2 1 0_0402_5% L: B1 -> A(VGA) H: B2 -> A(PCH) +3VS <37> ENBKL ENBKL LCD_ENVDD 2 VCC VCC VCC VCC VCC VCC VCC 4 10 18 27 38 50 56 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 2 3 7 8 11 12 14 15 19 20 SEL 17 GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1 6 9 13 16 21 24 28 33 39 44 49 53 55 HYBRID@ 1 C855 0.1U_0402_16V4Z 2 HYBRID@ C856 4.7U_0805_10V4Z CONN_LVDS_B0# CONN_LVDS_B0 CONN_LVDS_B1 CONN_LVDS_B1# CONN_LVDS_BCLK CONN_LVDS_BCLK# CONN_LVDS_B2 CONN_LVDS_B2# DGPU_SELECT# L: B1 -> A(VGA) H: B2 -> A(PCH) EDID_CLK EDID_DATA 0_0402_5% 0_0402_5% 2 UMA@ 1 R630 2 UMA@ 1 R636 CONN_LVDS_SCL CONN_LVDS_SDA LVDS_A0 LVDS_A0# 0_0402_5% 0_0402_5% 2 UMA@ 1 R629 2 UMA@ 1 R633 CONN_LVDS_A0 CONN_LVDS_A0# LVDS_A1 LVDS_A1# 0_0402_5% 0_0402_5% 2 UMA@ 1 R634 2 UMA@ 1 R635 CONN_LVDS_A1 CONN_LVDS_A1# LVDS_A2 LVDS_A2# 0_0402_5% 0_0402_5% 2 UMA@ 1 R637 2 UMA@ 1 R639 CONN_LVDS_A2 CONN_LVDS_A2# LVDS_ACLK LVDS_ACLK# 0_0402_5% 0_0402_5% 2 UMA@ 1 R641 2 UMA@ 1 R643 CONN_LVDS_ACLK CONN_LVDS_ACLK# LVDS_B0 LVDS_B0# 0_0402_5% 0_0402_5% 2 UMA@ 1 R645 2 UMA@ 1 R647 CONN_LVDS_B0 CONN_LVDS_B0# LVDS_B1 LVDS_B1# 0_0402_5% 0_0402_5% 2 UMA@ 1 R649 2 UMA@ 1 R651 CONN_LVDS_B1 CONN_LVDS_B1# LVDS_B2 LVDS_B2# 0_0402_5% 0_0402_5% 2 UMA@ 1 R653 2 UMA@ 1 R655 CONN_LVDS_B2 CONN_LVDS_B2# LVDS_BCLK LVDS_BCLK# 0_0402_5% 0_0402_5% 2 UMA@ 1 R657 2 UMA@ 1 R659 CONN_LVDS_BCLK CONN_LVDS_BCLK# DGPU_SELECT# HYBRID@ 1 <15> PCH_ENBKL_R 4 <15> PCH_ENVDD_R 6 Q75A 2N7002DW-T/R7_SOT363-6 3 HYBRID@ Q75B 2N7002DW-T/R7_SOT363-6 R260 2 1 2008/10/15 Deciphered Date Title 2 Compal Electronics, Inc. LVDS & DVI Connector Size B Date: 3 0_0402_5% A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 R1174 100K_0402_1% 0_0402_5% 2 Compal Secret Data 2007/10/15 Issued Date UMA@ R263 1 UMA@ Security Classification TS3DV520ERHUR_QFN56_11X5~D 5 DISPOFF# 2 2 0B1 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 2 DIS@ 5 <21> VGA_LVDS_B0# <21> VGA_LVDS_B0 <21> VGA_LVDS_B1 <21> VGA_LVDS_B1# <21> VGA_LVDS_BCLK <21> VGA_LVDS_BCLK# <21> VGA_LVDS_B2 <21> VGA_LVDS_B2# 48 47 43 42 37 36 32 31 22 23 1 1 HYBRID@ U66 VGA_LVDS_B0# VGA_LVDS_B0 VGA_LVDS_B1 VGA_LVDS_B1# VGA_LVDS_BCLK VGA_LVDS_BCLK# VGA_LVDS_B2 VGA_LVDS_B2# BKOFF# CH751H-40PT_SOD323-2 TS3DV520ERHUR_QFN56_11X5~D LVDS switch2 4.7K_0402_5% 2 0B1 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 4 10 18 27 38 50 56 1 <15> LVDS_A0# <15> LVDS_A0 <15> LVDS_ACLK <15> LVDS_ACLK# <15> LVDS_A2 <15> LVDS_A2# <15> LVDS_A1# <15> LVDS_A1 <15> EDID_CLK <15> EDID_DATA 48 47 43 42 37 36 32 31 22 23 VCC VCC VCC VCC VCC VCC VCC 2 <21> VGA_LVDS_A0# <21> VGA_LVDS_A0 <21> VGA_LVDS_ACLK <21> VGA_LVDS_ACLK# <21> VGA_LVDS_A2 <21> VGA_LVDS_A2# <21> VGA_LVDS_A1# <21> VGA_LVDS_A1 <19> VGA_LVDS_SCL <19> VGA_LVDS_SDA VGA_LVDS_A0# VGA_LVDS_A0 VGA_LVDS_ACLK VGA_LVDS_ACLK# VGA_LVDS_A2 VGA_LVDS_A2# VGA_LVDS_A1# VGA_LVDS_A1 VGA_LVDS_SCL VGA_LVDS_SDA 5 C Document Number Rev 0.1 NIWBA_LA5371P Tuesday, March 24, 2009 Sheet 1 29 of 52 A B C +1.5VS_TV Mini-Express Card for 3G Or TV Tuner Mini-Express Card for WLAN C559 4.7U_0805_10V4Z TV@ Mini-Express Card(Slot 1-TV TUNNER) 4.0mm high D E +3VS_TV 1 1 2 4.7U_0805_10V4Z 2 TV@ Mini-Express Card(Slot 3-WWAN 3G) C557 5.6mm high +3VS +3VS_TV JP5 <14> PCIE_PRX_DTX_N6 <14> PCIE_PRX_DTX_P6 +3VS_TV <37,38> EC_TX_P80_DATA <37,38> EC_RX_P80_CLK TV@100_0402_1% R757 2 2 R756 TV@100_0402_1% EC_TX_P80_DATA1 EC_RX_P80_CLK 1 GND1 GND2 54 +1.5VS_TV +3VS R821 +3VS 1 U15 TV_RST# 4 1 2 B 2 A 1 Y 33K_0402_5% 100_0402_1% 2 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 WAKE# 3.3V NC GND NC 1.5V CLKREQ# NC GND NC REFCLKNC REFCLK+ NC GND NC NC GND NC NC GND PERST# PERn0 +3.3Vaux PERp0 GND GND +1.5V GND SMB_CLK PETn0 SMB_DATA PETp0 GND GND USB_DNC USB_D+ NC GND NC LED_WWAN# NC LED_WLAN# NC LED_WPAN# NC +1.5V NC GND NC +3.3V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 100_0402_1% 53 GND 54 R1175 1 R414 R419 1 2 @ 0_0402_5% 2 @ 0_0402_5% <14> CLK_PCIE_CARD_PCH# <14> CLK_PCIE_CARD_PCH BUF_PLT_RST# <5,16,19,31> TVSW@ NO_TVSW@ 0_0402_5% 1 2 <14> PCIE_PTX_C_DRX_N4 <14> PCIE_PTX_C_DRX_P4 TV SW R822 <14> PCIE_PRX_DTX_N4 <14> PCIE_PRX_DTX_P4 +3VS Vcc 3.3V +/- 8% Peak Icc 2750mA with max supply droop 50mA Average Icc 1000mA <37,38> EC_TX_P80_DATA <37,38> EC_RX_P80_CLK FOX_AS0B226-S40N-7F ME@ 2 JP6 PCIE_WAKE# BT_ACTIVE WLAN_ACTIVE PCIECLKREQ3# <15,31> PCIE_WAKE# <40> BT_ACTIVE <40> WLAN_ACTIVE <14> PCIECLKREQ3# NC7SZ08P5X_NL_SC70-5 USB20_N9 <16> USB20_P9 <16> 1 +3VS_TV TVSW@ C37 0.1U_0402_16V4Z 2 TVSW@ 5 53 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 P <14> PCIE_PTX_C_DRX_N6 <14> PCIE_PTX_C_DRX_P6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 G <14> CLK_PCIE_WLAN# <14> CLK_PCIE_WLAN 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 3 PCIECLKREQ4# <14> PCIECLKREQ4# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 EC_TX_P80_DATA R758 1 EC_RX_P80_CLK 1 R759 GND +1.5VS 3G@ C562 10U_0805_10V4Z 1 3G@ C558 10U_0805_10V4Z 2 2Watt +UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP R420 1 R422 1 1 3G@ 2 @ 2 0_0402_5% 0_0402_5% R424 1 R425 1 0_0402_5% +3VALW 2 @ 2 @ 0_0402_5% +3VS R426 1 R427 1 2 @ 0_0402_5% 2 @ 0_0402_5% USB20_N13 USB20_P13 SMB_CLK_S3 <10,11,12,14> SMB_DATA_S3 <10,11,12,14> USB20_N13 <16> USB20_P13 <16> 3G_LED# 3G_LED# <41> +1.5VS 1 2 ME@ 2 G R802 0_0402_5% NO_TVSW@ TAITW_PFPET0-AFGLBG1ZZ4N0 2 @ +1.5VS_TV 1 CH1 CH4 UIM_DATA 4 10K_0402_5% +3VS TV SW 2 Vn 3 CH2 Vp 5 CH3 6 JP8 4 5 6 7 UIM_VPP UIM_DATA 5.6mm high +3VS JP7 PCIE_WAKE# BT_ACTIVE R428 1 WLAN_ACTIVE R429 1 WLAN_CLKREQ1# 1 2 @ 0_0402_5% 3 2 @ 0_0402_5% 5 7 9 11 <14> CLK_PCIE_WLAN1# 13 <14> CLK_PCIE_WLAN1 15 17 19 21 23 <14> PCIE_PTX_C_DRX_N2 25 <14> PCIE_PTX_C_DRX_P2 27 29 31 <14> PCIE_PRX_DTX_N2 33 <14> PCIE_PRX_DTX_P2 35 +3VS 37 39 41 43 100_0402_1% 45 R436 47 EC_TX_P80_DATA1 @ 2 49 <37,38> EC_TX_P80_DATA EC_RX_P80_CLK 1 2 51 <37,38> EC_RX_P80_CLK R755 @ 100_0402_1% 53 2005/09/27 modified. Base on OPTION GTM351E Datasheet Rev0.1 Vcc 3.3V +/- 8% Peak Icc 2750mA with max supply droop 50mA Average Icc 1000mA WAKE# 3.3V NC GND NC 1.5V CLKREQ# NC GND NC REFCLKNC REFCLK+ NC GND NC NC GND NC NC GND PERST# PERn0 +3.3Vaux PERp0 GND GND +1.5V GND SMB_CLK PETn0 SMB_DATA PETp0 GND GND USB_DNC USB_D+ NC GND NC LED_WWAN# NC LED_WLAN# NC LED_WPAN# NC +1.5V NC GND NC +3.3V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND 54 GND +3VALW +1.5VS 2Watt 1 2 C1329 0.1U_0402_16V4Z 2 @ 0_0402_5% 0_0402_5% 2 R432 1 R433 1 2 @ 0_0402_5% 0_0402_5% 2 R434 1 R435 1 2 @ 0_0402_5% 2 @ 0_0402_5% 2 @ 2 1 R761 1 R760 WLAN_LED# 3 SMB_CLK_S3 <10,11,12,14> SMB_DATA_S3 <10,11,12,14> New Card 34mm Socket (Left/TOP) JEXP1 WLAN_LED# <41> 2 4 C1330 0.1U_0402_16V4Z <10,11,12,14> SMB_CLK_S3 <10,11,12,14> SMB_DATA_S3 +1.5VS_CARD1 <15,31> PCIE_WAKE# +3VALW_CARD1 2 C1331 0.1U_0402_16V4Z U22 +3VS 2 4 +3VALW 17 <5,16,19,31> BUF_PLT_RST# 1 <37,42,47> SYSON <16,37,42,47,49> SUSP# +3VALW R438 1 <16> +3VALW CPUSB# PLT_RST# 6 2 +1.5VS_CARD1 1.5Vout 1.5Vout 3.3Vin 3.3Vin AUX_IN SYSRST# 3.3Vout 3.3Vout 2 11 13 AUX_OUT OC# 19 20 SUSP# 1 STBY# NC 2 @ 100K_0402_5% 10 CPPE# GND CPUSB# 9 SHDN# 3 5 15 SYSON 18 1 <14> CLKREQ_EXP# 1 C565 10U_0805_10V4Z 2 C566 0.1U_0402_16V4Z PERST# 8 60mil <14> PCIE_PTX_C_DRX_N1 <14> PCIE_PTX_C_DRX_P1 +3VS_CARD1 PERST# 1 2 1 C568 10U_0805_10V4Z 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Imax = 1.35A +3VALW_CARD1 40mil CPUSB# <14> PCIE_PRX_DTX_N1 <14> PCIE_PRX_DTX_P1 40mil GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND GND GND SANTA_130832-1_RV +3VALW_CARD1 7 Imax = 0.275A CPUSB# 1 RCLKEN 2 @ C571 10U_0805_10V4Z 1 2 Compal Secret Data Security Classification C572 0.1U_0402_16V4Z Issued Date 2007/10/15 Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 4 C569 0.1U_0402_16V4Z 16 G577BSR91U_QFN20 C1332 0.1U_0402_16V4Z PERST# <14> CLK_PCIE_EXP_PCH# <14> CLK_PCIE_EXP_PCH +3VS_CARD1 +3VS USB20_N10 USB20_P10 CPUSB# <16> USB20_N10 <16> USB20_P10 <16> CPUSB# 1 1.5Vin 1.5Vin C564 0.1U_0402_16V4Z ME@ +3VS_CARD1 12 14 2 +3VALW +3VS +1.5VS_CARD1 +1.5VS 2 3G_OFF# <37> WL_OFF# <37> BUF_PLT_RST# <5,16,19,31> Imax = 0.75A Express Card Power Switch 8 9 GND GND USB20_N8 <16> USB20_P8 <16> 300_0402_5% 300_0402_5% @ D22 1 +UIM_PWR TAITW_PFPET0-AFGLBG1ZZ4N0 ME@ +1.5VS +UIM_PWR UIM_RST UIM_CLK 1 TAITW_PMPAT6-06GLBS7N14N0 R430 1 R431 1 1 2 3 VCC RST CLK R437 10K_0402_5% 2 1 Mini-Express Card(Slot 2-WIRELESS) GND VPP I/O DET +3VS DAN217T146_SC59-3 3 1 2 40mil C563 4.7U_0805_10V4Z 1 C36 0.1U_0402_16V4Z TVSW@ 2 1 1 +UIM_PWR R824 2 <37> TV_POWER_SW 3 2 3G@ C1328 0.1U_0402_16V4Z D21 @ CM1293-04SO_SOT23-6 1 1 +3VS_TV <15,31> PCIE_WAKE# <40> BT_ACTIVE <40> WLAN_ACTIVE <14> WLAN_CLKREQ1# 1 2 AO3414_SOT23-3 Q11 D TVSW@ R801 2 G 0_0805_5% S NO_TVSW@ 3 S 2 2 3 R820 33K_0402_5% 3G@ C1327 0.1U_0402_16V4Z +1.5VS 1 1 1 +5VS AO3414_SOT23-3 Q10 D TVSW@ 2 +3VS 3G_OFF# <37> WL_OFF# <37> BUF_PLT_RST# <5,16,19,31> B C D Title Compal Electronics, Inc. Mini-Card/3G/FeliCa/BT Size Document Number Rev 0.1 NIWBA_LA5371P Date: Tuesday, March 24, 2009 Sheet E 30 of 52 5 4 3 2 1 +3V_LAN L30 1 2 MBK1608121YZF_0603 LAN_BIASVDDH C1334 1 2 0.1U_0402_16V4Z L31 LAN_XTALVDDH 1 2 MBK1608121YZF_0603 C1335 2 1 0.1U_0402_16V4Z D D L32 LAN_AVDDH +3V_LAN 1 2 MBK1608121YZF_0603 U71 +1.2V_LAN +1.2V_LAN 42 6 15 41 1 L36 2 MBK1608121YZF_0603 1 2 1 L34 1 L35 1 C592 4.7U_0805_10V4Z 2 MBK1608121YZF_0603 1 2 2 2 24 C594 4.7U_0805_10V4Z 2 2 VDDC VDDC VDDC AVDDL AVDDL AVDDL 25 C1336 0.1U_0402_16V4Z XTALVDDH 14 AVDDH 30 AVDDH 36 TRD3_N 37 LAN_TX3- TRD3_P 38 LAN_TX3+ TRD2_N 35 LAN_TX2- TRD2_P 34 LAN_TX2+ TRD1_N 31 LAN_RX1- TRD1_P 32 LAN_RX1+ 1 1 2 2 C1340 0.1U_0402_16V4Z LAN_TX3- <32> LAN_TX3+ <32> LAN_TX2- <32> LAN_TX2+ <32> GPHY_PLLVDDL C595 0.1U_0402_16V4Z 18 PCIE_PLLVDDL 21 PCIE_PLLVDDL 1 C598 4.7U_0805_10V4Z BIASVDDH C593 0.1U_0402_16V4Z 1 2 MBK1608121YZF_0603 1 C 27 33 39 VDDC TRD0_P 28 LAN_TX0+ TRD0_N 29 LAN_TX0- LINKLED# 48 LAN_RX1- <32> LAN_RX1+ <32> LAN_TX0+ <32> LAN_TX0- <32> C599 0.1U_0402_16V4Z C 0.1U_0402_16V7K PCIE_IRX_C_PTX_P3 0.1U_0402_16V7K PCIE_IRX_C_PTX_N3 C596 C597 <14> PCIE_PRX_DTX_N3 <14> PCIE_PRX_DTX_P3 <14> PCIE_PTX_C_DRX_N3 <14> PCIE_PTX_C_DRX_P3 <15,30> PCIE_WAKE# <37> LAN_WAKE# <14> CLK_PCIE_LAN <14> CLK_PCIE_LAN# R462 1 WAKE# 2 @ 0_0402_5% 17 16 22 23 4 2 20 19 PCIE_TXD_P PCIE_TXD_N PCIE_RXD_P PCIE_RXD_N WAKE# REST# PCIE_REFCLK_P PCIE_REFCLK_N SPD100LED# 47 SPD1000LED# 46 TRAFFICLED# 45 LINKLED# <32> ACTIVITY# <32> +3V_LAN C588 1 <5,16,19,30> BUF_PLT_RST# 1 EEDATA LAN_DATA EECLK 44 LAN_CLK XTALO 2 200_0402_1% XTALI Y4 2 XTALO 12 XTALI 26 RDAC SR_VFB 11 1 2 4.7UH_PG031B-4R7MS_1.1A_20% 8 C602 0.1U_0402_16V4Z 1 1 2 2 A0 A1 NC GND 1 2 3 4 AT24C02_SO8 @ R446 4.7K_0402_5% R444 4.7K_0402_5% L33 1.2V OUTPUT VCC WP SCL SDA C603 10U_0805_10V4Z 2 25MHZ_20P C604 27P_0402_50V8J 1 2 B +3V_LAN C605 27P_0402_50V8J SR_VDDP 2 1 1 B 13 +1.2V_LAN 4.7uH LOW_PWR U23 @ 8 7 6 5 LAN_CLK LAN_DATA VMAIN_PRSINT SR_LX 2 2 @ 0_0402_5% 40 43 R445 4.7K_0402_5% 1 R469 1 VMAIN_PRSNT @ R443 4.7K_0402_5% 2 2 1K_0402_5% 1 1 R468 1 5 2 +3VS MODE WAKE# 1 10K_0402_5% 2 2 R552 1 +3V_LAN R477 1 2 0.1U_0402_16V4Z @ R474 1.24K_0402_1% SR_VDD 1 3 10 9 C622 0.1U_0402_16V4Z CLKREQ# 1 2 2 C574 4.7U_0805_10V4Z <14> CLKREQ_LAN# BCM57780A0KMLG_QFN48_7X7 49 PAD NC 7 1 +3VALW @ 1 +5VALW 2 MBK1608121YZF_0603 L29 S 3 D 1 +3V_LAN 1 2 2 1 1 A A 2 G Q68 AO3414_SOT23-3 EN_WOL EN_WOL 1 2 <37> D 3 R439 33K_0402_5% S 1 C582 0.1U_0402_16V4Z 2 C583 0.1U_0402_16V4Z 2 C584 1U_0603_10V4Z 1 Q34 2N7002_SOT23 2 G 1 C581 10U_0805_10V4Z 2 C585 0.1U_0603_25V7K Layout Notice : Place as close chip as possible. Issued Date Compal Electronics,Ltd. Compal Secret Data Security Classification 2008/03/25 Deciphered Date 2008/04/ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Broadcom LAN 57780/57790 Size C Document Number Rev 0.1 NIWBA_LA5371P Date: Tuesday, March 24, 2009 Sheet 1 31 of 52 5 4 3 2 1 T80 C607 1 D C608 1 C609 1 C611 1 TCT 2 0.1U_0402_16V4Z <31> <31> LAN_TX3+ LAN_TX3- <31> <31> LAN_TX2LAN_TX2+ <31> <31> LAN_RX1+ LAN_RX1- <31> <31> LAN_TX0LAN_TX0+ 1 2 3 TCT1 TD1+ TD1- MCT1 MX1+ MX1- 24 23 22 MCT3 MDO3+ MDO3- R479 TCT 4 5 6 TCT2 TD2+ TD2- MCT2 MX2+ MX2- 21 20 19 MCT2 MDO2MDO2+ TCT 7 8 9 TCT3 TD3+ TD3- MCT3 MX3+ MX3- 18 17 16 TCT 10 11 12 TCT4 TD4+ TD4- MCT4 MX4+ MX4- 15 14 13 LAN_TX3+ LAN_TX3- 2 0.1U_0402_16V4Z LAN_TX2LAN_TX2+ 2 0.1U_0402_16V4Z LAN_RX1+ LAN_RX1- 2 0.1U_0402_16V4Z LAN_TX0LAN_TX0+ 2 1 75_0402_5% R480 2 1 75_0402_5% MCT1 MDO1+ MDO1- R482 2 1 75_0402_5% MCT0 MDO0MDO0+ R483 2 1 75_0402_5% RJ45_PR D 350UH_IH-037-2 T80 350uH_NS0013LF 100@ C C RJ11+RJ45 CONN JLAN 12 1 330_0402_5% 11 2 R481 <31> ACTIVITY# 1 B C610 0.01U_0402_16V7K <31> LINKLED# 2 R485 2 SHLD4 16 8 PR4- SHLD3 15 7 PR4+ MDO1- 6 PR2- MDO2- 5 PR3- MDO2+ 4 PR3+ MDO1+ 3 PR2+ MDO0- 2 PR1- MDO0+ 1 PR1+ MDO3MDO3+ 1 330_0402_5% 10 9 +3V_LAN 1 C612 0.01U_0402_16V7K Amber LEDAmber LED+ +3V_LAN B Green LED- SHLD2 14 SHLD1 13 Green LED+ FOX_JM36113-P2221-7F 2 RJ45_PR 1 2 C614 1000P_1206_2KV7K C616 0.1U_0402_16V4Z 2 2 1 1 C617 0.1U_0402_16V4Z A A Compal Secret Data Security Classification 2007/10/15 Issued Date 2008/10/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title LAN CONTROLLER Size Document Number Custom Date: 5 4 3 2 Compal Electronics, Inc. Rev 0.1 KIWB1/B2_LA4601P Tuesday, March 24, 2009 Sheet 1 32 of 52 預預 2 100K change to 4.7u CAP==> 0513 : CARD_3V3 0521 : change C79 form 4.7u to 0.1u, add R47 100K ohm, change C526 form 1u to 4.7u JREAD1 D XDPWR_SDPWR_MSPWR 1 0_0402_5% 1 2 C618 0.1U_0402_16V4Z +3VS R491 1 R492 1 @ 3V3_IN RST# MODE SEL XTLO XTLI 2 0_0603_5% 2 0_0603_5% 1 +3VALW C1337 0.1U_0402_16V4Z 2 <16> <16> USB20_N5 USB20_P5 USB20_N5 USB20_P5 8 44 45 47 48 3V3_IN RST# MODE_SEL XTLO XTLI 4 5 14 DM DP GPIO0 R490 keep supply 3.3V to 3V3_IN when S3 Vender suggesttion 2 C 1 R495 100K_0402_5% RST# 1 2 2 2 C623 1U_0402_6.3V4Z RREF 12 32 DGND DGND 6 46 AGND AGND 10 22 30 XD_CLE_SP19 XD_CE#_SP18 XD_ALE_SP17 SD_DAT2/XD_RE#_SP16 SD_DAT3/XD_WE#_SP15 XD_RDY_SP14 SD_DAT4/XD_WP#/MS_D7_SP13 SD_DAT5/XD_D0/MS_D6_SP12 SD_CLK/XD_D1/MS_CLK_SP11 SD_DAT6/XD_D7/MS_D3_SP10 MS_INS#_SP9 SD_DAT7/XD_D2/MS_D2_SP8 SD_DAT0/XD_D6/MS_D0_SP7 SD_DAT1/XD_D3/MS_D1_SP6 XD_D5_SP5 XD_D4/SD_DAT1_SP4 SD_CD#_SP3 SD_WP_SP2 XD_CD#_SP1 EEDI 43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18 XTAL_CTR MS_D5 13 24 EEDO EECS EESK SD_CMD 15 16 17 36 C621 1 1U_0603_16V4Z 2 24 27 30 1 2 MS-DATA3 SD-DAT4 SD-DAT2 SD-CD SD-WP SDDAT5_XDD0_MSD6 XDD5_MSBS XDD4_SDDAT1 SDDAT0_XDD6_MSD0 SDDAT3_XDWE# 32 6 7 5 34 3 4 37 38 10 36 35 39 40 xD-D0 xD-D5 xD-D4 xD-D6 xD-WE xD-VCC xD-D7 xD-CE xD-RE xD-D1 xD-CLE xD-ALE xD-R/B xD-CD 23 14 25 29 12 SDDAT5_XDD0_MSD6 SDDAT0_XDD6_MSD0 SD_CMD SDDAT3_XDWE# XDD4_SDDAT1 MS-SCLK MS-BS MS-INS MS-VCC MS-DATA1 MS-DATA2 MS-DATA0 26 13 22 28 15 19 17 MS-SCLK XDD5_MSBS MS_INS# SD-CLK SD-DAT6 SD-DAT7 SD-VCC 20 18 16 21 7IN1-GND 7IN1-GND 31 11 GND GND 41 42 XDPWR_SDPWR_MSPWR 100K_0402_5% SDDAT1_XDD3_MSD1 SDDAT7_XDD2_MSD2 SDDAT0_XDD6_MSD0 D SD-CLK SDDAT6_XDD7_MSD3 SDDAT7_XDD2_MSD2 TAITW_R015-A10-LM_NR ME@ XDCLE XDCE# XDALE SDDAT2_XDRE# SDDAT3_XDWE# XD_RDY SDDAT4_XDWP#_MSD7 SDDAT5_XDD0_MSD6 SDCLK_XDD1_MSCLK SDDAT6_XDD7_MSD3 MS_INS# SDDAT7_XDD2_MSD2 SDDAT0_XDD6_MSD0 SDDAT1_XDD3_MSD1 XDD5_MSBS XDD4_SDDAT1 SDCD SDWP XDCD XTAL_CTR 2 1 R496 0_0603_5% R1176 2 1 0_0402_5% MS-SCLK R1177 SD-CLK 1 0_0402_5% 2 CLK_48M_CR MS-SCLK SD-CLK R663 33_0402_5% @ R665 33_0402_5% @ C805 22P_0402_50V8J @ 3V3_IN pin 13 (XTAL CTL) CLOCK SOURCE FLOATING 12MHz CRYSTAL INPUT PULL HIGH CLOCK GENERATOR'S 48MHZ INPUT C R664 33_0402_5% @ C807 22P_0402_50V8J @ C806 22P_0402_50V8J @ REMARK 使使 該該該該該該該該 但但但但RTS5158E側EMI). 將SD_DAT1 連連連RTS5158E的pin23 SD_CMD MSCLK and SDCLK solution , ( RTS5159-GR_LQFP48_7X7 INPUT TO PIN48 1 R498 0_0402_5% 1 R497 6.19K_0402_1% 2 VREG MS_D4 NC SDDAT6_XDD7_MSD3 SDDAT4_XDWP#_MSD7 SDDAT2_XDRE# SDCD SDWP SD-DAT5 SD-DAT0 SD-CMD SD-DAT3 SD-DAT1 2 XDPWR_SDPWR_MSPWR AV_PLL NC NC CARD_3V3 D3V3 D3V3 xD-WP xD-D3 xD-D2 1 2 2 U25 1 3 7 9 11 33 33 8 9 SDDAT6_XDD7_MSD3 XDCE# SDDAT2_XDRE# SDCLK_XDD1_MSCLK 1 XDCLE C620 0.1U_0402_16V4Z XDALE XD_RDY 2 XDCD 1 4.7U_0603_6.3V6K 1 C619 SDDAT4_XDWP#_MSD7 SDDAT1_XDD3_MSD1 SDDAT7_XDD2_MSD2 2 2 R489 1 1 旁旁旁旁 3 2 4 1 5 B B CLK_48M_CR R499 1 C624 MODE SEL 1 6P_0402_50V8D @ 1 2 @ R500 0_0402_5% Y5 12MHZ_16P_6X12000012 @ 2 47P_0402_50V8J 1 XTLI 2 2 C625 2 0_0603_5% 1 <12> CLK_48M_CR C626 1 2 XTLO 6P_0402_50V8D @ A A Compal Secret Data Security Classification Issued Date 2006/08/04 Deciphered Date 2006/10/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. 1394+3 in 1 Card Size Document Number Custom Rev 1.0 NIWBA_LA5371P Date: Tuesday, March 24, 2009 Sheet 1 33 of 52 A B C D E F G H SATA HDD Conn. JHDD SATA_ITX_DRX_P0 SATA_ITX_DRX_N0 <13> SATA_ITX_DRX_P0 <13> SATA_ITX_DRX_N0 1 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 <13> SATA_DTX_C_IRX_N0 <13> SATA_DTX_C_IRX_P0 C634 1 C633 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_DTX_IRX_N0 SATA_DTX_IRX_P0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +3VS +5VS +5VS 1 2 3 4 5 6 7 +3VS GND A+ AGND BB+ GND V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 GND V12 GND SATA ODD Conn. SATA_ITX_DRX_P1 SATA_ITX_DRX_N1 <13> SATA_ITX_DRX_P1 <13> SATA_ITX_DRX_N1 SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 <13> SATA_DTX_C_IRX_N1 <13> SATA_DTX_C_IRX_P1 C635 1 C636 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_DTX_IRX_N1 SATA_DTX_IRX_P1 +5VS 23 24 2 1 C627 1000P_0402_50V7K 2 1 C628 0.1U_0402_16V4Z 2 1 C629 1U_0603_10V4Z 2 1 C630 10U_0805_10V4Z 2 1 C631 10U_0805_10V4Z 2 @ C632 0.1U_0402_16V4Z 1 2 3 4 5 6 7 GND A+ AGND BB+ GND 8 9 10 11 12 13 DP +5V +5V MD GND GND OCTEK_SLS-13SB1G_RV ME@ CONN need change to new CONN FOX_LD2122H-S43_NR 1 1 JODD ME@ 2 2 +USB_VCCB W=80mils +USB_VCCB ESATA and USB Conn. 1 C733 150U_B_6.3VM_R40M 1 + 2 C734 470P_0402_50V7K 2 JESATA <16> USB20_N1 <16> USB20_P1 <13> SATA_ITX_DRX_P4_CONN <13> SATA_ITX_DRX_N4_CONN 3 <13> SATA_DTX_C_IRX_N4 <13> SATA_DTX_C_IRX_P4 SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4 USB20_N1 USB20_P1 SATA_ITX_DRX_P4_CONN SATA_ITX_DRX_N4_CONN 1 C1338 SATA_DTX_IRX_N4_CONN 1 C1339 SATA_DTX_IRX_P4_CONN 0.01U_0402_16V7K 2 0.01U_0402_16V7K 2 1 2 3 4 VBUS DD+ GND USB 5 6 7 8 9 10 11 GND A+ ESATA AGND BB+ GND 12 13 14 15 GND GND GND GND A+ = RXP A- = RXN 3 B- = TXN B+ = TXP TYCO_1759576-1 ME@ +5VALW +USB_VCCB U34 C732 0.1U_0402_16V4Z 2 1 <37,40> USB_ON 1 2 3 USB_ON 4 GND IN IN EN OUT OUT OUT OC# 8 7 6 5 USB_OC#0 <16,40> G545A1P1U_SO8 1 C735 @ 1000P_0402_50V7K 2 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/10/15 2008/10/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title HDD & ODD Connector Size B Document Number Date: A B C D E F Rev 0.1 NIWBA_LA5371P Tuesday, March 24, 2009 G Sheet 34 H of 52 5 4 1 EMI HDA_SYNC_CODEC Adjustable Output 2 +5VDDA_CODEC 2 @ @ @ 2 2 2 2 Place near Pin9 INT_MIC_L Internal MIC / Array MIC INT_MIC_R D32 RB751V_SOD323 1 1K_0402_5% 1 1K_0402_5% <36> EXT_MIC_L <36> EXT_MIC_R ARRAY@ 2 2 WM-64PCY_2P 45@ C660 47P_0402_50V8J 2 ARRAY@ GNDA R731 1 LOUT2_L 39 MIC2_R LOUT2_R 41 SPDIFO1 48 SPDIFO2 45 R732 1 R733 1 <37> B LINE1_R 1 C652 MIC_EXTL_C 21 MIC1_L HPOUT_L 33 2 1 C653 MIC_EXTR_C 22 MIC1_R HPOUT_R 32 PC_BEEP 12 BEEP_IN MONO_OUT 37 R706 1 HDA_BITCLK_CODEC 6 BITCLK DMIC_CLK1/2 46 HDA_SDOUT_CODEC 5 SDATA_OUT DMIC_CLK3/4 44 SDATA_IN 22_0402_5% HDA_RST_CODEC# 8 SDATA_IN LINE2_VREFO 20 11 RESET# LINE1_VREFO 18 HDA_SYNC_CODEC 10 SYNC MIC1_VREFO 28 MIC2_VREFO 19 CPVREF 31 2 2 GPO_AUD GPIO0/DMIC_DATA1/2 3 MIC Sense R516 place near pin13 Capless HP Sense R517 place near pin34 2 0_0402_5% 2 0_0402_5% 1 20K_0402_1% 2 5.1K_0402_1% 1 0_0402_5% <36> MIC_JD <36> PLUG_IN <37> EAPD 2 R516 1 R517 2 R762 GND Pin Assignment LINE1_L 24 2 <13> HDA_SYNC_CODEC 2 0_0402_5% SENSEA 13 SENSEB 34 GPIO1/DMIC_DATA3/4 Function LINE-OUT (Pin35/36) Internal Int Speaker Capless HP-OUT (Pin32/33) External Headphone out LINE1 (Pin23/24) External Line in MIC1(Pin21/22) External Mic in VREF 27 JDREF 40 CBN 30 CBP 29 AVSS1 AVSS2 26 42 SENSE A SENSE B 47 EAPD 43 NC 4 7 Location C842 10U_0805_10V4Z 9 MIC2_L 17 <13> HDA_RST_CODEC# 2 0_0402_5% DVDD 16 MIC_INR 2.2U_0603_16V6K <13> HDA_SDIN1 R829 1 1 MIC_INL <13> HDA_SDOUT_CODEC ARRAY@ LINE_OUTR DVSS DVSS NEED TO STUDY (FBMA-L10-160808-800LMT) COPMAL PN:SM01000DI00 1 2 R763 SPDIF_OUT <36> 2 63.4_0402_1% 2 63.4_0402_1% 1 R510 1 R512 HP_OUTL <36> 0_0402_5% +MIC1_VREFO_L +MIC2_VREFO 1 C658 2 2.2U_0603_10V6K R525 20K_0402_1% 1 C659 2 2.2U_0603_10V6K Close Pin27 bead? 2 0_0603_5% +3VALW W=40mil Internal Mic C811 0.1U_0402_16V4Z 1 1 2 2 U40 C812 4.7U_0805_10V4Z 16 6 15 +3VS GAIN0 R521 10K_0402_1% 2 2 GAIN1 3 1C662 C763 0.1U_0402_16V4Z VDD PVDD PVDD NC 12 SHUTDOWN 19 GAIN0 1 1 1 1U_0603_10V4Z @ AMP_OFF# R708 1 SPK_L1- <36> ROUT- 14 SPK_R1- SPK_R1- <36> LOUT+ 4 SPK_L2+ SPK_L2+ <36> ROUT+ 18 SPK_R2+ SPK_R2+ <36> 9 LIN+ 7 RIN+ 1 GND GND GND GND GND 1 11 13 20 21 2 C813 0.1U_0603_25V7K 1 BYPASS 10 R531 C815 0.1U_0603_25V7K TPA6017A2PWPR_TSSOP20 20mil GAIN1 0 1 0 1 +5VAMP 6dB 10dB 15.6dB 21.6dB +5VAMP @ R713 100K_0402_1% 1 2 C814 4.7U_0805_10V4Z R714 100K_0402_1% GAIN0 R715 100K_0402_1% GAIN1 A R716 100K_0402_1% @ 2 560_0402_5% D23 @ RB751V_SOD323 R532 10K_0402_5% Issued Date Compal Electronics,Ltd. Compal Secret Data Security Classification 2008/03/25 Deciphered Date 2008/04/ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 GAIN0 0 0 1 1 EC_MUTE# <36,37> 2 RIN- 2 EC_MUTE# 0_0402_5% 2 1 1 @ 17 2 1 2 @ R527 20K_0402_5% RIN C764 10U_0805_10V4Z 1 2 Q37 2SC2411KT146_SOT23-3 2 E 2 2 ICH Beep 2 B 1U_0603_10V4Z C668 <13> PCH_SPKR 2 560_0402_5% LIN- R623 1 C667 @ 0.1U_0402_16V4Z 1 2 1 1 1 C 3 BEEP# R524 R712 5 1 SPK_L1- LOUT- LIN 2 1 Title HD Audio Codec_ALC272 2 <37> C666 2 R711 10K_0402_5% A PC_BEEP R710 1 2 0_0402_5% 10K_0402_5% EC Beep 2PC_BEEP1 R523 20K_0402_5% LINE_OUTR 1 1 C665 1U_0603_10V4Z 2 1 R709 0_0402_5% 1 2 2 LINE_OUTL R522 10K_0402_1% 2 8 GAIN1 1U_0603_10V4Z 1 +5VS R707 10K_0402_5% @ 1 2 2 B 2 1 PC Beep 1 1 ALC272-GR_LQFP48 Internal Subwoofer Internal 2 1 MIC2(Pin16/17) C Headphone HP_OUTR <36> MONO_OUT <36> +5VAMP Internal SPDIF Add 64 ohm serial resistor to avoid ESD MONO_OUT +5VAMP MONO-OUT(Pin37) Internal Speaker 2 1 LOUT1_R 1 C650 <13> HDA_BITCLK_CODEC INT_MIC_R LINE_OUTL 2 3300P_0603_50V7K 2 1 2 1 0_0603_5% R520 GNDA 2 3300P_0603_50V7K 1 1 1 2 1 C646 2.2U_0603_16V6K R702 2 MIC4 C645 C_LINE_OUTR 1 C651 23 R701 R518 4.7K_0402_5% ARRAY@ C_LINE_OUTL 36 2 external MIC 1 1 C 35 2 2 +MIC2_VREFO LINE2-R +1.5VS 0.1U_0402_16V4Z 2.2U_0603_16V6K MIC_INTL 1 2 1K_0402_5% R703 MIC_INTR 1 2 1K_0402_5% R704 ARRAY@ 2.2U_0603_16V6K LOUT1_L 10U_0805_10V4Z C822 R513 LINE2-L 15 0_0402_5% C823 14 0_0402_5% INT_MIC_L 2 2 1 MIC_INTR 1 1 2 2 MONO@ DVDD_IO 2 1 R734 2 38 AVDD1 2 2 2 U64 MIC_INTL C655 47P_0402_50V8J 25 R533 4.7K_0402_5% AVDD2 R535 4.7K_0402_5% 1 0.1U_0402_16V4Z C639 1 1 1 2 1 1 R789 4.7K_0402_5% MONO@ MIC1 2 GNDA C649 +3VDD_CODEC R777 R509 4.7K_0402_5% ARRAY@ WM-64PCY_2P 45@ Place near Pin38 +IOVDD_CODEC D31 RB751V_SOD323 ARRAY@ GNDA 2 Place near Pin25 +MIC2_VREFO 1 2 1 D Place near Pin1 +5VDDA_CODEC 2 0_0603_5% 1 1 @ +MIC1_VREFO_L 1 2 1 C648 C816 C638 1 0.1U_0402_16V4Z 2 1 10U_0805_10V4Z 2 MBK1608121YZF_0603 1 0.1U_0402_16V4Z 2 2 10U_0805_10V4Z 1 @ L37 0.1U_0402_16V4Z 1 @ 1 22P_0402_50V8J C821 4 BYP 1 22P_0402_50V8J C820 SHDN G9191-475T1U_SOT23-5 @ 22P_0402_50V8J C819 2 1 C643 4.7U_0805_10V4Z 2 GND 3 +3VDD_CODEC 1 HDA_BITCLK_CODEC 1 2 R787 @ 33_0402_5% 5 OUT C642 0.01U_0402_16V7K 1 +5VDDA_CODEC IN 2 0.1U_0402_16V4Z C641 10U_0805_10V4Z C640 D 1 1 +3VS 1 HDA_SDOUT_CODEC U26 MBK1608121YZF_0603 2 L503 22P_0402_50V8J C808 +5VS 1 HDA_RST_CODEC# J4 2MM 2 C637 2 3 4 3 2 Size C Document Number Rev 0.1 NIWBA_LA5371P Date: Tuesday, March 24, 2009 Sheet 1 35 of 52 5 4 3 2 1 Audio Jack EMI 20080826 L49 D EXT_MIC_L <35> EXT_MIC_L 1 EXT_MIC_L-2 2 D FBMA-L10-160808-121LMT_2P C669 47P_0402_50V8J SubWoofer Conn. EMI 20080826 <35> <35> <35> <35> SPK_R1SPK_R2+ SPK_L1SPK_L2+ 1 1 1 1 1 1 2 2 2 2 2 2 2 2 @ C670 10P_0402_50V8J Audio Jack GNDA MIC IN L50 EXT_MIC_R <35> EXT_MIC_R L43 L44 L45 L46 L47 L48 1 GNDA Speaker Connector WOOFERWOOFER+ SPK_R1SPK_R2+ SPK_L1SPK_L2+ 1 EXT_MIC_R-2 2 FBMA-L10-160808-121LMT_2P 20mil JSPK1 WOWO+ SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_CONN SPK_L2+_CONN FBMA-L10-160808-121LMT_2P FBMA-L10-160808-121LMT_2P FBMA-L10-160808-121LMT_2P FBMA-L10-160808-121LMT_2P FBMA-L10-160808-121LMT_2P FBMA-L10-160808-121LMT_2P 1 1 2 3 4 5 6 1 2 3 4 5 G1 6 G2 C671 47P_0402_50V8J 7 8 ACES_87213-0600G 1 1 2 2 GNDA GNDA @ C672 10P_0402_50V8J JMIC1 1 2 3 MIC_JD <35> MIC_JD 4 GNDA 1 10P_0402_50V8J 5 C673 @ 2 GNDA C 6 2 1 1 Headphone C675 2 GNDA EMI 20080826 HP_OUTR <35> HP_OUTR L51 1 2 FBMA-L10-160808-121LMT_2P L52 1 2 FBMA-L10-160808-121LMT_2P HP_OUTL <35> HP_OUTL C @ R538 1K_0402_5% 2 @ R537 1K_0402_5% 220P_0402_50V7K C674 1 1 2 220P_0402_50V7K G SINGA_2SJ-0960-C02 ME@ JHP1 PR-OUT 6 1 PL-OUT 4 5 PLUG_IN +5VS <35> SPDIF_OUT 1 2 33K_0402_5% 1 2 R620 G1442 SubWoofer Amplifier 1nd = APA3011 (SA00001JM00) 2nd = TPA6211 (SA621110010 ) C676 220P_0402_50V7K 18K_0402_5% MONO_OUT <35> MONO_OUT 1 C759 2 6 R618 68K_0402_5% 1 2 R619 C761 2.2U_0603_6.3V4Z A VDD SHUTDOWN# WIN1 3 IN+ WIN2 4 IN- 2 BYPASS 2 2 ONLY FOR 15.6W 1 W=40mil U39 C760 1U_0603_10V4Z 1 AMP_OFF# Vo+ 5 WOOFER+ Vo- 8 WOOFER- GND 7 2 1 R622 0_0402_5% EC_MUTE# EC_MUTE# <35,37> APA3011XA-TRL_MSOP8 1 A Compal Electronics,Ltd. Compal Secret Data Security Classification 2008/03/25 Issued Date Deciphered Date 2008/04/ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 B R621 10K_0402_5% @ C762 +5VAMP SINGA_2SJ1533-000111 +3VALW 1500P_0402_50V7K 1 2 0.01U_0402_16V7K 1 2 2 1 C677 0.1U_0402_16V4Z B 7 3 8 SPDIF_OUT 2 <35> PLUG_IN 4 3 2 Title AMP,Audio speaker CONN Size Document Number Custom Rev 0.1 KIWB1/B2_LA4601P Date: Tuesday, March 24, 2009 Sheet 1 36 of 52 +3VALW +EC_AVCC <16> EC_SCI# <41> PWR_LED_SC# 2 C686 0.1U_0402_16V4Z 1 <38,41> <38> KSI3 KSI4 KSO[0..15] <38> KSO[0..15] KSI[0..7] <38,41> KSI[0..7] +3VALW @ 2 47K_0402_5% KSO1 R830 1 R831 1 2 47K_0402_5% KSO2 @ ENE UPDATE 08/10/21 <41> <41> KSO16 KSO17 LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 EC_RST# EC_SCI# KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 67 9 22 33 96 111 125 2 1 2 3 4 5 7 8 10 GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & 12 13 37 20 38 PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D 21 23 26 27 INVT_PWM BEEP# BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 63 64 65 66 75 76 BATT_TEMP BATT_OVP DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F 68 70 71 72 DAC_BRIG EN_FAN1 IREF PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F 83 84 85 86 87 88 INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 PWM Output MISC AD DA Output 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 77 78 79 80 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 PS2 Interface 2 SPI Flash ROM 2 @ Q38 2N7002_SOT23 XCLKI XCLKO 73 74 89 90 91 92 93 95 121 127 EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 100 101 102 103 104 105 106 107 108 PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 110 112 114 115 116 117 118 V18R 124 1 R558 FSEL#SPICS# 2 @ 100K_0402_1% 1 R559 KSO17 2 @ 10K_0402_5% +5VALW R810 EC_SMB_CK1 2 4.7K_0402_5% 1 R561 1 @ TP_LOCK# TP_CLK TP_DATA GPO_AUD <35> +5VS TP_CLK DAC_BRIG <29> EN_FAN1 <5> IREF <45> CHGVADJ <45> R544 1 +3VALW BATT_OVP EC_MUTE# R546 1 2 @ 10K_0402_5% EC_MUTE# <35,36> USB_ON R547 1 USB_ON <34,40> BATT_TEMP 2 10K_0402_5% ACIN TP_LOCK# <39> TP_CLK <38> TP_DATA <38> R548 1 2 @ 4.7K_0402_5% EN_WOL <31> BATT_SEL_EC <45> CMOS_OFF# <40> 2 4.7K_0402_5% TP_DATA R545 1 1 C688 1 C689 1 C690 2 4.7K_0402_5% 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J KB926 SPI STRAP PIN FRD#SPI_SO FWR#SPI_SI SPI_CLK FSEL#SPICS# RCIRRX I2C_INT CHARGE_LED0# CAPS_LED# CHARGE_LED1# SYSON ACIN FRD#SPI_SO FWR#SPI_SI SPI_CLK FSEL#SPICS# <39> <39> <39> <39> R549 10K_0402_5% RCIRRX <41> I2C_INT <41> FSTCHG <45> CHARGE_LED0# <39> CAPS_LED# <38> CHARGE_LED1# <39> PWR_LED# <39> SYSON <30,42,47> VR_ON <51> ACIN <43,45> I2C_INT EC_LID_OUT# EC_ON MUTE_LED ICH_POK_EC BKOFF# EC_RSMRST# <15> EC_LID_OUT# <14> EC_ON <41> D25 MUTE_LED# <41> 1 RB751V_SOD323 ICH_POK 2 ICH_POK <15> BKOFF# <29> 1 2 1 2 +3VS WL_OFF# <30> R555 0_0402_5% R556 10K_0402_5% TV_POWER_SW <30> @ WIRELESS_LED# <39> WIRELESS_LED# SLP_S4# <15> ENBKL <29> EAPD <35> SUSP# PBTN_OUT# SUSP# <16,30,42,47,49> PBTN_OUT# <15> BT_OFF# <40> 1 2 SUSP# C691 1U_0603_10V4Z 1 ENE ISSUE CHANGE FROM 4.7uF TO 1uF 20080606 2 @ C692 1000P_0402_50V7K needed to update to D3 version SA00001J580 +3VALW EC_SMB_CK1 2 4.7K_0402_5% XCLK1 XCLK0 KB926QFA1_LQFP128 R560 1 @ GPI ECAGND FRD#SPI_SO 2 @ 100K_0402_1% 122 123 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A GND GND GND GND GND +3VALW 1 R557 USB_ON BATT_TEMP <44> BATT_OVP <45> ADP_I <45> SUS_PWR_DN_ACK <15> LCD_COLOR <29> 1 2 R823 0_0402_5% +3VS AGND 1 G +3VALW EC_SMI# LID_SW# <38> KILL_SW# <5> FAN_SPEED1 <30> 3G_OFF# <30,38> EC_TX_P80_DATA <30,38> EC_RX_P80_CLK <41> ON/OFF# <16> PCH_TEMP_ALERT# <38> NUM_LED# D 3 PCI_PME# 6 14 15 16 17 18 19 25 FAN_SPEED1 28 29 EC_TX_P80_DATA 30 EC_RX_P80_CLK 31 32 PCH_TEMP_ALERT# 34 36 <15> SLP_S3# <15> SLP_S5# <16> EC_SMI# <38> LID_SW# <15> AC_PRESENT <13> ME_FLASH EC_PME# 2 @ 0_0402_5% S <16> 119 120 126 128 GPO_AUD_R INVT_PWM <29> BEEP# <35> NOVO# <41> ACOFF <45> @ 2 0_0402_5% 1 R554 SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 GPIO SM Bus 11 24 35 94 113 1 R551 <31> LAN_WAKE# EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 97 98 99 109 69 1 R550 10K_0402_5% EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 ACOFF SPI Device Interface +3VALW <44> <44> <14> <14> U29 AVCC VCC VCC VCC VCC VCC VCC 2 1 <16> CLK_PCI_LPC <16,38> PCI_RST# KB_RST#_EC 2 1 2 10_0402_5% 2 47K_0402_5% 2 1 C682 1000P_0402_50V7K +3VALW GATEA20 <13,38> SERIRQ @ <13,38> LPC_FRAME# RB751V_SOD323 <13,38> LPC_AD3 <13,38> LPC_AD2 <13,38> LPC_AD1 <13,38> LPC_AD0 2 1 2 1 @ C687 22P_0402_50V8J @ R541 1 R543 <16> 1 D24 2 1 C685 1000P_0402_50V7K 2 KB_RST# 2 1 C681 0.1U_0402_16V4Z <16> 1 C680 0.1U_0402_16V4Z +3VALW 1 C679 0.1U_0402_16V4Z C678 0.1U_0402_16V4Z L38 1 2 +EC_AVCC FBM-11-160808-601-T_0603 2 1 C683 C684 0.1U_0402_16V4Z 1000P_0402_50V7K 1 2 1 ECAGND 2 L39 FBM-11-160808-601-T_0603 0_0402_5% 1 2 R779 R811 EC_SMB_DA1 2 4.7K_0402_5% EC_SMB_DA1 2 4.7K_0402_5% 1 +3VS 1 C693 1 2 @ C694 100P_0402_50V8J 1 2 X1 2 NC IN 1 3 NC OUT 4 @ R564 20M_0603_5% 2 EC_SMB_CK2 EC_SMB_DA2 2 18P_0402_50V8J XCLKO R563 2.2K_0402_5% @ 1 R562 2.2K_0402_5% @ @ C695 100P_0402_50V8J 32.768KHZ_12.5P_1TJS125BJ2A251 1 C696 2 18P_0402_50V8J XCLKI Compal Secret Data Security Classification Issued Date 2007/10/15 Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Compal Electronics, Inc. BIOS & EC I/O Port Size Document Number Custom Date: Rev 0.1 NIWBA_LA5371P Tuesday, March 24, 2009 Sheet 37 of 52 5 4 3 2 INT_KBD Conn. D <37,41> KSO[0..15] <37> KSO2 C697 1 2 @ 100P_0402_50V8J KSO1 C698 1 2 @ 100P_0402_50V8J KSO15 C699 1 2 @ 100P_0402_50V8J KSO7 C700 1 2 @ 100P_0402_50V8J KSO6 C701 1 2 @ 100P_0402_50V8J KSI2 C702 1 2 @ 100P_0402_50V8J KSO8 C703 1 2 @ 100P_0402_50V8J KSO5 C704 1 2 @ 100P_0402_50V8J KSO13 C705 1 2 @ 100P_0402_50V8J KSI3 C706 1 2 @ 100P_0402_50V8J KSO12 C707 1 2 @ 100P_0402_50V8J KSO14 C708 1 2 @ 100P_0402_50V8J KSO11 C709 1 2 @ 100P_0402_50V8J KSI7 C710 1 2 @ 100P_0402_50V8J KSO10 C711 1 2 @ 100P_0402_50V8J KSI6 C712 1 2 @ 100P_0402_50V8J KSO3 C713 1 2 @ 100P_0402_50V8J KSI5 C714 1 2 @ 100P_0402_50V8J KSO4 C715 1 2 @ 100P_0402_50V8J KSI4 C716 1 2 @ 100P_0402_50V8J KSI0 C717 1 2 @ 100P_0402_50V8J KSO9 C718 1 2 @ 100P_0402_50V8J KSO0 C719 1 2 @ 100P_0402_50V8J KSI1 C720 1 2 @ 100P_0402_50V8J +5VS 470_0402_5% 470_0402_5% 2 2 <37> NUM_LED# <37> CAPS_LED# KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 1 R770 1 R771 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 D JP14 +3VALW <30,37> EC_TX_P80_DATA <30,37> EC_RX_P80_CLK 1 2 3 4 1 2 3 4 ACES_85205-0400 ME@ Lid Switch G1 G2 31 32 1 R565 +3VALW +VCC_LID 2 0_0402_5% ACES_85201-3005N CONN PIN define need double check EC_TX_P80_DATA EC_RX_P80_CLK R566 1 2 100K_0402_5% C A3212ELHLT-T_SOT23W-3 VDD C KSO[0..15] EC DEBUG PORT JP13 KSI[0..7] 2 KSI[0..7] 1 1 3 OUTPUT 2 1 +5VS LID_SW# <37> 2 GND To TP/B Conn. C721 0.1U_0402_16V4Z C723 U30 1 C722 10P_0402_50V8J 0.1U_0402_16V4Z JP15 <37> <37> 4 3 2 1 TP_CLK TP_DATA TP_CLK TP_DATA 1 2 @ C724 100P_0402_50V8J 1 2 @ C725 100P_0402_50V8J 4 3 2 1 E&T_6905-E04N-00R ME@ Kill Switch CONN PIN define need double check +3VALW R632 2 B <37> KILL_SW# LSSM12-P-V-T-R_3P 100K_0402_5% 1 KILL_SW# 3 3 2 2 1 1 B SW2 FOR LPC SIO DEBUG PORT JP16 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 +5VS +3VS LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ0# PCI_RST# CLK_PCI_DB SERIRQ CLK_14M_SIO <14> LPC_AD0 <13,37> LPC_AD1 <13,37> LPC_AD2 <13,37> LPC_AD3 <13,37> LPC_FRAME# <13,37> LPC_DRQ0# <13> PCI_RST# <16,37> CLK_PCI_DB <14> SERIRQ <13,37> 2 R567 1 10K_0402_5% @ A ACES_85201-2005 ME@ Compal Secret Data Security Classification 2007/10/15 Issued Date Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. KB /SW /LPC Debug Conn. Size B Date: Document Number Rev 0.1 KIWB1/B2_LA4601P Tuesday, March 24, 2009 Sheet 1 38 of 52 FOR EC 16M SPI ROM +3VALW 20mils U31 FSEL#SPICS# SPI_SO 2 15_0402_5% 1 2 3 4 CS# SO WP# GND VCC HOLD# SCLK SI 8 7 6 5 SPI_CLK_R SPI_SI R569 1 R570 1 2 15_0402_5% 2 15_0402_5% SPI_CLK FWR#SPI_SI SPI_CLK <37> FWR#SPI_SI <37> SPI_CLK_R 1 MX25L1605AM2C-12G_SO8 2 R832 0_0402_5% @ 2 R571 33_0402_5% @ 1 C727 22P_0402_50V8J @ C861 12P_0402_50V8J @ EMI FD1 1 2 3G FD2 1 FD3 1 FD4 1 LED 2 750_0402_5% H15 HOLEA 2 470_0402_5% 1 1 1 1 H12 HOLEA 1 H11 HOLEA H17 HOLEA H18 HOLEA H19 HOLEA H20 HOLEA H21 HOLEA 1 1 1 1 1 LED7 12-22-S2ST3D-C30-2C_WHI-ORG H22 HOLEA LED4 WHITE H6 HOLEA 2 BATT_LOW_LED# 2 750_0402_5% H23 HOLEA H24 HOLEA H25 HOLEA H26 HOLEA +5VS 19-213A-T1D-CP2Q2HY-3T_WHITE H27 HOLEA 1 R577 1 1 2 1 1 1 <37> TP_LOCK# H16 HOLEA 1 R626 1 1 CHARGE_LED1# H10 HOLEA 1 1 +5VALW 3 AMBER H5 HOLEA 2 470_0402_5% 1 R625 1 H9 HOLEA 1 BATT_CHG_LED# CHARGE_LED0# H8 HOLEA 1 H7 HOLEA 1 <37> CHARGE_LED1# H4 HOLEA +5VALW 1 R624 1 2 12-21SYGCS530-E1S155TR8_W <37> CHARGE_LED0# H3 HOLEA LED1 1 <37> PWR_LED# WHITE H2 HOLEA 1 WHITE H1 HOLEA 1 H13 HOLEA SC500005B00,If=5mA,Vf=2.7V~3.15V,R=460~390ohm 1 H28 HOLEA 1 2 R627 1 2 470_0402_5% +5VALW 1 LED5 <37> WIRELESS_LED# 1 <37> FRD#SPI_SO R568 1 R812 10K_0402_5% 1 <37> FSEL#SPICS# FRD#SPI_SO C726 0.1U_0402_16V4Z 2 2 1 1 12-21SYGCS530-E1S155TR8_W WHITE Compal Secret Data Security Classification Issued Date 2007/10/15 Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Compal Electronics, Inc. LED/EC SPI ROM Size B Date: Document Number Rev 0.1 NIWBA_LA5371P Tuesday, March 24, 2009 Sheet 39 of 52 A B C D USB Board Conn. 10 pin +5VALW +USB_VCCA +USB_VCCA W=80mils U33 C730 0.1U_0402_16V4Z 2 1 <34,37> USB_ON 1 E USB_ON 1 2 3 4 GND IN IN EN OUT OUT OUT OC# JP18 1 +USB_VCCA 8 7 6 5 C728 150U_B_6.3VM_R40M USB_OC#2 <16,34> G545A1P1U_SO8 + 2 USB_OC#0 <16,34> 1 1 2 C729 470P_0402_50V7K <16> <16> 1 2 3 4 5 6 7 8 USB20_P4 USB20_N4 USB20_P4 USB20_N4 USB20_N0 USB20_P0 <16> USB20_N0 <16> USB20_P0 C731 @ 1000P_0402_50V7K 1 GND 2 3 4 5 6 7 8 GND 9 1 10 ACES_87213-0800G 2 2 2 +5VS BT MODULE CONN 1 CMOS Camera Conn R578 10K_0402_1% <37> BT_OFF# +3VS Q40 DTC124EKAT146_SC59-3 +3VS_BT 30mils 3 1 2 1 IN D 2 2 GND 2 2 0.01U_0402_16V7K C736 0.1U_0402_16V4Z S 1 R580 0_0603_5% OUT 1 1 1 Q39 SI2301BDS-T1-E3_SOT23-3 C862 CMOS1 3 1 1 G R579 10K_0402_5% 0.01U_0402_16V7K 2 D S 1 3 2 C863 2 +5VS 3 3 Q41 2 JP20 Q42 DTC124EKAT146_SC59-3 1 C738 10U_0805_10V4Z SI2301BDS-T1-E3_SOT23-3 BT_LED# ACES_88266-05001 ME@ 0.1U_0402_16V4Z C737 MOLEX_53780-0870 2 10 9 8 7 6 5 4 3 2 1 Q43 DTC124EKAT146_SC59-3 IN 2 USB20_N11 USB20_P11 BT_ACTIVE WLAN_ACTIVE BTON_LED <16> USB20_N11 <16> USB20_P11 <30> BT_ACTIVE <30> WLAN_ACTIVE 3 2 <41> 1 2 3 4 5 GND1 GND2 1 USB20_N2 USB20_P2 USB20_N2 USB20_P2 OUT <16> <16> 1 2 3 4 5 6 7 GND IN 3 <37> CMOS_OFF# GND OUT G 2 1 GND2 GND1 8 7 6 5 4 3 2 1 ME@ JP21 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2006/08/18 Deciphered Date 2007/8/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Power OK, Reset and RTC Circuit, TP Size Document Number Custom Date: Rev 0.1 NIWBA_LA5371P Tuesday, March 24, 2009 Sheet E 40 of 52 Bottom Board Conn. 6 pin Power Bottom Board Conn. 6 pin +3VALW +5VS +5VALW 1 2 IF NON-CIR DEVICE , MUST TO PU JP23 R582 1 2 <37> PWR_LED_SC# 33_0402_5% 1 C739 22P_0402_50V8J 2 1 2 3 4 5 6 7 8 PWR_LED_SC# NOVO_BTN# ON/OFFBTN# IR1 +3VALW 1 2 R583 100_0603_5% 1 Vout 2 VCC 3 GND 1 NOVO_BTN# 4 4.7U_0805_10V4Z 2 EMI REQUEST 1ST = SCA00000G00 2ST = SCA00000T00 ON/OFFBTN# GND D29 PJSOT24C 3P C/A SOT-23 KSI2 KSO16 3 IRM-V538/TR1_3P KSI3 KSO17 1 D33 PACDN042Y3R_SOT23-3 3 2 4 EMI REQUEST 1ST = SCA00000E00 2ST = SCA00000R00 SMT1-05_4P 6 5 1 BTN FUNCTION MUTE BTN DOWN UP +3VALW 2 TOP Side Bottom Side KEY MATRIX IN OUT KSO17 KSI3 KSO17 KSI2 KSO16 KSI2 R584 100K_0402_5% 1 D26 ON/OFFBTN# 1 1 D30 PACDN042Y3R_SOT23-3 ON/OFF switchSW1 Power Button 1 2 3 4 5 6 GND GND ACES_85201-06051 ME@ ACES_85201-06051 ME@ 3 C740 MUTE_LED# KSO16 KSI2 KSO17 KSI3 <37> MUTE_LED# <37> KSO16 <37,38> KSI2 <37> KSO17 <37,38> KSI3 1 2 3 4 5 6 GND GND 3 RCIRRX RCIRRX 2 <37> JP25 1 2 3 4 5 6 7 8 2 1 R781 750_0402_5% R780 300_0402_5% 2 R581 100_0603_5% @ 2 2 1 CIR 3 ON/OFF# 2 51_ON# 1 ON/OFF# <37> IDEAPAD BOARD 2PIN 51_ON# <43> 1 DAN202UT106_SC70-3 1 C741 1000P_0402_50V7K 1 @ 2 G Q44 2N7002_SOT23-3 D ACES_87213-0200 3 EC_ON 2 4 3 2 1 R769 S 1 +5VS R587 10K_0402_5% 2 100_0603_5% G2 G1 2 1 JP26 Slide Board Conn. 10 pin 2 +3VALW JP24 R589 100K_0402_5% <37> <43> NOVO# 51_ON# NOVO# 51_ON# <13> DRIVE_LED# <40> BT_LED# <30> WLAN_LED# <30> 3G_LED# D28 1 EC_ON D27 RLZTE1120A LL34 @ 1 <37> 2 2 2 1 DRIVE_LED# BT_LED# WLAN_LED# 3G_LED# 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% +5VS NOVO_BTN# <37> 3 I2C_INT <14,19> SMB_EC_DA2_R <14,19> SMB_EC_CK2_R DAN202UT106_SC70-3 2 2 2 2 1 1 1 1 R773 R774 R775 R776 R631 1 2 0_0402_5% I2C_INT_R R586 1 R585 1 2 0_0402_5% R_SMB_DA2 2 0_0402_5% R_SMB_CK2 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 GND GND ACES_85201-1005N Issued Date Compal Electronics,Ltd. Compal Secret Data Security Classification 2008/03/25 Deciphered Date 2008/04/ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Audio Jack & SW connector Size Document Number Custom Rev 0.1 NIWBA_LA5371P Date: Tuesday, March 24, 2009 Sheet 41 of 52 A B C D +3VALW TO +3VS +5VALW TO +5VS E +1.5V to +1.5VS +1.5V C746 10U_0805_10V4Z 2 1 2 C747 1U_0603_10V4Z R591 470_0603_5% B+ 2 SUSP G Q47 2N7002_SOT23 1 S 2 @ 2 1 D R608 0_0402_5% SUSP C752 0.1U_0603_25V7K 2 G 2N7002_SOT23S +3VS 1 S Q57 1 3 R599 0_0402_5% Q50 2N7002_SOT23 @ C757 C758 @ 0.1U_0603_25V7K 2 2 0.1U_0603_25V7K +1.5VS +3VS_D +1.5VS_D PJ507 1 1 2 @ 2 PJ508 2 1 +1.05VS 1 +0.75VS 1 +VCCP 1 +1.5V 1 +1.8VS 8 7 6 5 JUMP_43X79 U53 HYBRID@ D S 1 D S 2 D S 3 D G 4 S S HYBRID@ HYBRID@ DGPU_PWR_EN# 2 G Q80 2N7002_SOT23 <16> DGPU_PWR_EN# 1 2 SUSP G Q69 2N7002_SOT23 HYBRID@ 1 D 2 47K_0402_5% 1 B+ C765 HYBRID@ 3 S 2 SUSP G Q56 2N7002_SOT23 R596 2 47K_0402_5% 1 B+ D 3 2 SUSP G Q55 2N7002_SOT23 2 SI4800BDY-T1-E3_SO8 R595 1 2 1 2 1 2 1 2 S 2 SYSON# G Q54 2N7002_SOT23 1 R1181 470_0603_5% D 3 2 SUSP G Q53 2N7002_SOT23 @ R605 470_0603_5% D 3 3 S R604 470_0603_5% D 3 1 2 D R603 470_0603_5% 1 JUMP_43X79 U48 HYBRID@ D S 1 D S 2 D S 3 D G 4 8 7 6 5 SI4800BDY-T1-E3_SO8 R602 470_0603_5% @ 2 @ 2 2 SUSP G Q52 2N7002_SOT23 1.5VS_GATE 1 1 HYBRID@ DGPU_PWR_EN# 2 G Q79 2N7002_SOT23 <16> DGPU_PWR_EN# 2 0.1U_0603_25V7K S 1 2 G 1 R606 150K_0402_5% 2 SUSP C751 0.1U_0603_25V7K D 1 @ 2 R601 470_0603_5% D 2 1 3 S 1 1 R598 0_0402_5% Q49 2N7002_SOT23 C756 1U_0603_10V4Z 2 B+ S R594 47K_0402_5% 2 D 2 G 2 SUSP G Q46 2N7002_SOT23 3 1 5VS_GATE SUSP 2 SI4800BDY-T1-E3_SO8 1 C755 10U_0805_10V4Z D 3 3 S R593 20K_0402_5% 1 3 D 1 2 3 4 S S S G 2 2 1 D D D D 3 B+ 1 8 7 6 C754 5 10U_0805_10V4Z 1 1 2 R590 470_0603_5% 1 1 2 +3VS U36 8 D 1 S 7 D 1 S 2 6 D S 3 C745 5 D G 4 10U_0805_10V4Z 2 SI4800BDY-T1-E3_SO8 1 +3VALW 1 +5VS U35 8 D 1 S 7 D 1 1 1 S 2 6 D S 3 C742 C743 C744 5 D G 4 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z 2 2 2 SI4800BDY-T1-E3_SO8 1 +1.5VS U38 +5VALW C766 HYBRID@ 2 0.1U_0603_25V7K S +1.8VS +1.05VS 3 1 D +1.8VS_D +1.05VS_D 3 PJ509 PJ510 1 JUMP_43X79 U72 HYBRID@ D S 1 D S 2 D S 3 D G 4 8 7 6 5 SI4800BDY-T1-E3_SO8 HYBRID@ <16> DGPU_PWR_EN# HYBRID@ DGPU_PWR_EN# 2 G Q82 2N7002_SOT23 2 47K_0402_5% HYBRID@ 1 D C768 HYBRID@ S <16> DGPU_PWR_EN# HYBRID@ 2 G Q81 2N7002_SOT23 1 2 47K_0402_5% 1 1 B+ 1 B+ 1 D DGPU_PWR_EN# 2 0.1U_0603_25V7K 3 IN 2 JUMP_43X79 U70 HYBRID@ D S 1 D S 2 D S 3 D G 4 R597 OUT <30,37,47> SYSON 2 1 R600 3 IN GND SUSP# SYSON 3 <16,30,37,47,49> 2 2 SYSON# Q59 DTC124EKAT146_SC59-3 OUT Q58 DTC124EKAT146_SC59-3 1 SI4800BDY-T1-E3_SO8 1 2 SUSP R611 100K_0402_5% GND SUSP 1 <47,48> 2 R609 10K_0402_5% 8 7 6 5 1 @ R610 100K_0402_5% 2 @ 1 1 +5VALW 1 @ 2 +5VALW 3 RTCVREF 2 C767 HYBRID@ 2 0.1U_0603_25V7K S 4 4 2006/08/18 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title DC Interface Size Document Number Custom Date: Rev 0.1 NIWBA_LA5371P Tuesday, March 24, 2009 Sheet E 42 of 52 B C VIN DC030006J00 VIN VS 2 RTCVREF <37,45> 1 PR108 10K_0402_5% PACIN 2 1 2 PR109 10K_0402_5% 2 1 ACIN PACIN 1 O PU102A LM393DG_SO8 PD102 RLZ4.3B_LL34 P - 1 PR104 10K_0805_5% 2 + 2 G 8 3 4 1 2 1 2 VINDE-3 PR107 24.9K_0402_1% VINDE-1 PC107 0.1U_0402_16V7K 2 PR106 215K_0402_1% 1 2 PR105 10K_0402_1% 1 2 2 1 1 PR103 82.5K_0402_1% PC106 1000P_0603_50V7K 2 1 1 2 PC104 1000P_0402_50V7K 1 2 1 PC103 100P_0402_50V8J 2 2 4 VINDE-2 VIN PC113 0.1U_0603_25V7K 4 1 3 2 3 PC102 100P_0402_50V8J 2 1 2 1 PR102 1M_0402_1% 1 2 PL101 SMB3025500YA_2P 1 2 2 1 PF101 7A_24VDC_429007.WRML 1 2 APDIN1 1 1 APDIN PC101 1000P_0402_50V7K JDCIN @ 4602-Q04C-09R 4P P2.5 PC112 0.1U_0603_25V7K 1 D PC105 0.01U_0402_25V7K A 3.3V 2 Vin Detector High 18.135 Low 14.866 17.566 14.355 17.011 14.063 2 VIN PD103 LL4148_LL34-2 1 51ON-1 1 BATT+ 1 PD101 LL4148_LL34-2 2 1 2 PR101 200_0603_5% 1 2 + PD104 @ MAXEL_ML1220T10 1 2 1 2 1 3.3V 3 2 SP093MX0000 PR114 200_0603_5% PU101 G920AT24U_SOT89-3 OUT 1 RB751V-40TE17_SOD323-2 PC109 0.1U_0603_25V7K 2 2 +CHGRTC PR115 PR116 560_0603_5% 560_0603_5% 1 2RTCVREF-1 1 2 3 2 +RTCBATT VS 51ON-3 RTCVREF 1 1 IN 2CHGRTCIN 1 JRTC 2 PR113 22K_0402_1% 1 2 3 GND PC110 10U_0603_6.3V6M 1 PC111 1U_0805_25V6K 2 - <41> 51_ON# 2 RTC Battery PR112 100K_0402_1% 1 1 51ON-2 PC108 0.22U_0603_25V7K CHGRTCP 3 PR111 68_1206_5% 2 PR110 PQ101 68_1206_5% TP0610K-T1-E3_SOT23-3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/06 Deciphered Date 2010/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title DCIN & DETECTOR Size Document Number Custom Date: Rev 0.1 Tuesday, March 24, 2009 D Sheet 43 of 52 A B C D 1 1 VMB2 VMB PF2 12A_65V_451012MRL 1 2 JBATT PL201 SMB3025500YA_2P 1 2 VL BATT+ VL EC_SMCA EC_SMDA 1 PR202 47K_0402_1% 1 PR203 47K_0402_1% TM-2 1 2 1 1 7 TM-3 D S PU102B LM393DG_SO8 1 PQ201 SSM3K7002FU_SC70-3 2 G VL PR208 100K_0402_5% PR210 100K_0402_5% 2 2 1 PC204 1000P_0402_50V7K +3VALW PR207 15.4K_0402_1% 1 2 PR209 6.49K_0402_1% 2 PC203 0.22U_0603_25V7K 2 1 EC_SMB_DA1 <37> 1 O - 4 6 + P 5 TM_REF1 EC_SMB_CK1 <37> 2 8 PR205 13.7K_0402_1% 1 2 TM-1 MAINPWON <46> 1 100K_0603_1%_TH11-4H104FT 3 PH201 G 2 PC202 0.01U_0402_25V7K 2 @ TYCO_1775768-1 PC201 1000P_0402_50V7K 2 1 2 2 2 1 PR206 100_0402_1% 1 2 3 4 5 6 7 8 9 2 1 PR204 100_0402_1% 2 1 2 3 4 5 6 7 GND GND PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C 1 2 PR211 10K_0402_5% A/D BATT_TEMP <37> 3 3 BATT_SEL_HW <45> 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/06 Deciphered Date 2010/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title BATTERY CONN / OTP Size Date: Document Number Rev 0.1 Tuesday, March 24, 2009 Sheet D 44 of 52 A B C D 24751_PVCC PQ302 FDS6675BZ_SO8 PR302 0.015_1206_1% 8 7 6 5 PJ301 24751_VREF PGND 22 24751_LODRV 8 ACOFF OVPSET CP Point Setting 1 9 2 13 ACGOOD SRSET 16 IADAPT 15 SRSET BATDRV IADAPT 1 1 2 3 2 1 2 IREF <37> PR322 180K_0402_1% 2 PR321 10_0402_5% PC325 @0.01U_0402_25V7K 1 1 24751_ACGOOD# ADP_I Current 2.842V 3.3A 1 ACIN D S 2 G <37,43> PQ311 @ SSM3K7002FU_SC70-3 VADJ CHGVADJ Pre Cell 3.3V 4.35V 0V 4V 24751_VREF 2 PC328 1000P_0402_50V7K 2 1 2 IREF <37> 3 @ PR325 100K_0402_5% 1 PQ309 SSM3K7002FU_SC70-3 2 G <37> FSTCHG 3 LI-3S :13.5V----BATT-OVP=1.5V BATT-OVP=0.1112*BATT+ D S 4 P 8 1 1 CHGEN# 2 2 2 1 PC331 10U_1206_25V6M 2 2 1 54.9K_0402_1% "CHGVADJ" connect to EC DA pin PC330 0.01U_0402_25V7K - PU302A LM358DR_SO8 PC314 @ 10U_1206_25V6M 24751_VREF RTCVREF PR319 PC327 100P_0402_50V8J PR328 499K_0402_1% 2 1 <37> CHGVADJ 1 2 1 PC305 4.7U_0805_25V6-K 1 2 ICHG setting 1 14 29 OVP-2 2 OVP-3 1 BATT_SEL_HW <44> PR332 @ 0_0402_5% 2 1 BATT_SEL_EC <37> PR333 @ 0_0402_5% 2 3 1 PR331 105K_0402_1% 4 4 5BAT_SEL2 2 1 6 1 2 1 PR329 PR327 499K_0402_1% 340K_0402_1% PC329 0.01U_0402_25V7K 1 2 8 P + 0 G 1 A/D + 5 - 6 0 4 G 7 PU302B LM358DR_SO8 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/06 Deciphered Date 2010/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. OVP-4 A TP PR324 @ 0_0402_5% PR326 210K_0402_1% 1 2 PC321 @0.1U_0603_25V7K PC323 0.1U_0603_25V7K REGN OVP-1 <37> BATT_OVP BAT BQ24751ARHDR_QFN28_5X5 VMB2 VS PR330 10K_0402_5% 2 1 24751_SRN 17 4 1 2 PC326 0.1U_0402_16V7K PR323 340K_0402_1% 18 0.1U_0603_25V7K PQ307B 2N7002KDW-2N_SOT363-6 5 SRN 2 24751_ACGOOD# 2 PC324 1 2 224751_OCP-1 24751_SRP PC320 0.1U_0603_25V7K PR335 100K_0402_5% 2 1 VADJ 3 1 19 2 1 12 PQ307A 2N7002KDW-2N_SOT363-6 2 SRP PQ310B @ 2N7002KDW-2N_SOT363-6 PQ310A @ 2N7002KDW-2N_SOT363-6 2 24751_OCP-2 1 /BATDRV 3 PR320 100K_0402_5% PR334 0_0402_5% VREF BATT_SEL-1 2 2 1 PR318 200K_0402_1% CELLS PC319 0.1U_0402_16V7K 1 2 PR338 @ 49.9K_0402_1% 2 24751_OCP-3 20 1 ACSET 1 24751_VREF CELLS 224751_VDAC 11 VDAC VADJ 24751_VREF ACOFF PC318 @ 820P_0603_50V7K 3 +EC_AVCC 1 PR336 0_0402_5% 21 3 PR317 100K_0402_5% 2 1 2 Fsw : 300KHz 10 PR337 @ 0_0402_5% 2 1 LEARN 2 BATT+ 1 ACIN detect : 17.26V 2 PR316 100K_0402_5% 1 2 Input OVP : 22.3V 1 3 PQ306 AO3413_SOT23-3 PC322 1U_0603_10V6K 24751_VREF 65W adapter Vacset=3.3*(115K/(150K+115K))=1.432V CP Point=(Vacset/Vvdac)*(0.1/PR302)=2.89A ACOFF AGND <37> 1 24751_OVPSET 1 PR314 54.9K_0402_1% 2 4 1 23 2 LODRV 2 224751_ACOP 7 ACOP PC317 0.47U_0603_16V7K 3 2 1 2 1 4 PC316 1U_0603_10V6K PR312 @ 4.7_1206_5% 1 1 PC312 LL4148_LL34-2 0.1U_0603_25V7K 24 1 CP setting 90W adapter Vacset=3.3*(127K/(75K+127K))=2.075V CP Point=(Vacset/Vvdac)*(0.1/PR302)=4.19A 2 PR308 0.02_1206_1% 2 2 ACSET REGN 2 1 PR313 127K_0402_1% 1 1 PC315 @ 0.01U_0402_25V7K 6 124751_BTST 1 PD301 2 PL302 10U_LF919AS-100M-P3_4.5A_20% 1 224751_SW-1 2 ACSET PQ303 SIS412DN-T1-GE3_PAK1212-8 PC313 10U_1206_25V6M 24751_PH 4 5 6 7 8 25 ACDRV ACDET 4 1 PH /BATDRV 2 26 1 PQ304 FDS6675BZ_SO8 1 HIDRV 2 PR303 100K_0402_5% 2 27 2 2 BTST 24751_BTST-1 1 PR307 2.2_0603_5% 24751_HIDRV PQ305 SI7716ADN-T1-GE3_PAK1212-8 PR311 75K_0402_1% 24751_VREF 1 2 1 5 PC310 1U_0805_25V6K REGN 2 2 ACN ACP PVCC 2 24751_SNB 1 PR309 340K_0402_1% CHGEN 1 28 PC302 0.01U_0402_25V7K 3 2 1 1 2 24751_ACDRV# 4 ACDET 5 1 2 PR339 150_0805_5% PR310 54.9K_0402_1% PU301 1 24751_ACN @ 2 24751_ACP 3 PR306 340K_0402_1% 1 1 1 1 PC308 0.1U_0603_25V7K 2 1 2 1 2 @ 2 @ PC307 0.1U_0402_16V7K 1 2 PC309 0.1U_0603_25V7K 4 PC306 0.01U_0402_25V7K 2 1 PR304 100K_0402_5% 4 1 2 1 PC301 0.01U_0402_25V7K PD302 RLZ24B_LL34 2 BK-2 PC311 2.2U_0805_25V6K 1 1 PR305 3.3_1210_5% BK-1 2 1 1 2 1 @ JUMP_43X118 PC304 4.7U_0805_25V6-K 3 PC303 4.7U_0805_25V6-K 2 CHGEN# PR301 3.3_1210_5% 2 CHG_B+ 4 5 B+_IN 1 3 1 2 3 2 1 2 3 4 8 7 6 5 VIN B+ 6 1 2 PR315 @ 49.9K_0402_1% PQ301 FDS6675BZ_SO8 B C Title CHARGER Size Date: Document Number Rev 0.1 Tuesday, March 24, 2009 Sheet D 45 of 52 5 4 3 ISL6237_B+ FB3 VL PHASE2 PHASE1 16 SW5 23 LGATE2 LGATE1 18 LG5 PGND 22 30 OUT2 OUT1 10 32 REFIN2 FB1 11 1 2 BYP 9 SKIP 29 NC POK2 28 EN_LDO POK1 13 ILIM1 12 ILM1 ILIM2 31 ILIM2 1 REF 8 LDOREFIN 2 PC417 0.22U_0603_25V7K EN_LDO 4 3/5V_EN1 14 EN1 3/5V_EN2 27 EN2 PC422 0.1U_0402_25V6 2 1 PC406 2200P_0402_50V7K 2 1 1 PC415 330P_0402_50V7K PQ404 SI7716ADN-T1-GE3_PAK1212-8 FB5 5V_SKIP 2 1 PR410 @ 0_0402_5% 1 2 PR411 0_0402_5% 2 1 PR421 @ 0_0402_5% PU401 ISL6237IRZ-T_QFN32_5X5 + PC413 2 220U_6.3VM_R15 C VL 2VREF_ISL6237 2 1 PR414 301K_0402_1% 2 1 PR415 301K_0402_1% B 13/5V_TON PR416 0_0402_5% 21 5 PC418 1U_0603_10V6K 2 13/5V_NC PR420 0_0402_5% PJ402 2 +3VALWP 2 2 1 1 +3VALW @ JUMP_43X118 2VREF_ISL6237 1 2 2 PC420 0.047U_0402_16V7K 2 1 1 0_0402_5% <44> 2VREF_ISL6237 1 PR419 @ 47K_0402_1% PC419 0.047U_0402_16V7K 1 806K_0603_1% 2 MAINPWON 2 1 PR418 VL PR417 PD403 @ RB751V-40TE17_SOD323-2 1 2 2 2 1 PR413 200K_0402_1% 1 2 EN_LDO-1 GND 20 PR412 100K_0402_1% 1 2 NC PD401 RB751V-40TE17_SOD323-2 1 2 TON PC416 0.22U_0603_25V7K PC412 0.1U_0603_25V7K 2 LG3 25 4 1 SW3 PR404 4.7_1206_5% 1BST5A-1 PR407 @ 61.9K_0402_1% 1 2 BST5A2 PR405 2.2_0603_5% +5VALWP 1 17 15V_SNB 2 BOOT1 2VREF_ISL6237 VS PC404 10U_1206_25V6M 2 1 5 HG5 PC411 0.1U_0603_25V7K @ PD402 RLZ5.1B_LL34 1 2 3 2 1 15 5 7 PVCC UGATE1 PQ402 SIS412DN-T1-GE3_PAK1212-8 PL402 4.7UH_PCMC063T-4R7MN_5.5A_20% 2 1 3 2 1 BOOT2 LDO VCC 24 PC410 1U_0603_10V6K 1 2 19 2 2 2 1 PR403 2.2_0603_5% VIN BST3A 4.7U_0805_6.3V6K PC409 2 1 PC408 3/5V_VCC 1 2 3 1U_0603_10V6K 3/5V_VIN 2 1 UGATE2 4 D PR409 0_0402_5% 1 2 2 26 PQ403 SI7716ADN-T1-GE3_PAK1212-8 PR408 10K_0402_1% 1 C TP UG3 1 2 3 1 4 2 PC414 330P_0402_50V7K 6 5 1 1 PC421 220U_6.3VM_R15 2 BST3A-1 13V_SNB 2 2 + PR402 4.7_1206_5% PR406 0_0402_5% 1 33 5 PL401 4.7UH_PCMC063T-4R7MN_5.5A_20% 1 2 +3VALWP PC407 0.1U_0603_25V7K PQ401 4 SIS412DN-T1-GE3_PAK1212-8 VL 1 2 3 PC401 10U_1206_25V6M 2 1 PC403 2200P_0402_50V7K 2 1 PR401 0_0402_5% 1 2 PC423 0.1U_0402_25V6 2 1 PC405 330P_0402_50V7K 2 1 PJ401 @ JUMP_43X118 2 2 1 1 B 1 ISL6237_B+ B+ D 2 @ PJ403 +5VALWP 2 2 1 1 +5VALW @ JUMP_43X118 A A 2009/01/06 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title 3VALW/5VALW Size Document Number Custom Date: Rev 0.1 Tuesday, March 24, 2009 Sheet 1 46 of 52 5 4 3 2 1 PJ501 6 PGOOD 2 1.5V_TRIP TRIP 11 V5DRV 10 SW_1.5V 1 2 PR117 10K_0402_1% 9 LG_1.5V DRVL +5VALW 4 1 PGND 7 PC543 @0.1U_0402_16V7K 8 2 PR533 100K_0402_1% 1 PC530 @ 47P_0402_50V8J 1 2 GND 1 2 PC529 1U_0603_10V6K 1 2 PC545 @ 470P_0402_50V7K 1 2 PC544 @ 330P_0402_50V7K 2 1 PC550 2200P_0402_50V7K 2 1 PC549 0.1U_0402_25V6 D 1 15 14 12 PR520 @ 4.7_1206_5% PU501 TPS51117RGYR_QFN14_3.5x3.5 PC531 4.7U_0805_6.3V6K 1 + 2 1 VFB LL 2 5 B+ PC528 10U_0603_6.3V6M 1.5V_FB 1 +1.5VP PC527 220U_6.3VM_R15 V5FILT UG_1.5V 1.5V_SNB 2 4 DRVH 13 1 1.5V_V5FILT 1 PC532 @ 470P_0402_50V7K 2 VOUT 2 @ JUMP_43X79 PQ501 SI4686DY-T1-E3_SO8 PL502 1.8UH_SIL104R-1R8PF_9.5A_30% 1 2 5 6 7 8 TON 3 VBST 2 1 +5VALW TP 1 PR521 422_0603_1% 1 2 EN_PSV 2 PC526 @0.1U_0402_16V7K 2BST_1.5V-1 1 2 PC525 0.1U_0603_25V7K PQ506 SI4634DY-T1-E3_SO8 BST_1.5V 1 PR519 2.2_0603_5% 3 2 1 1.5V_EN 1 <30,37,42> SYSON 4 3 2 1 PR518 0_0402_5% 1 2 2 D 2 1 PC502 10U_1206_25V6M PR501 240K_0402_1% 1 2 1.5V_TON 2 2 1 PC501 10U_1206_25V6M 5 6 7 8 1.5V_IN 1.5V_PGOOD 1 PR523 31.6K_0402_1% 1 2 C C PR524 30.1K_0402_1% VCCP_EN 1 1 2 PC548 @ 820P_0603_50V7K 1 2 PC546 @ 220P_0402_50V7K 1 2 2 1 PC551 0.1U_0402_25V6 2 1 PC552 2200P_0402_50V7K @ B+ PR535 100K_0402_1% LG_VCCP PU503 TPS51117RGYR_QFN14_3.5x3.5 4 PC541 4.7U_0805_6.3V6K 2 B PC542 680P_0402_50V7K PQ508 SI7716ADN-T1-GE3_PAK1212-8 DGPU_PWROK <16,49> 1 PR531 13.7K_0402_1% 1 2 + 1 9 DRVL 1 2 10 +5VS PC538 10U_0603_6.3V6M V5DRV PR528 4.7_1206_5% 5 11 1 14 VBST 15 1 TRIP VCCP_TRIP 1 2 PR530 23.7K_0402_1% PC537 220U_6.3VM_R15 PGOOD SW_VCCP 2 6 12 +1.05VSP 1 VFB LL 2 5 UG_VCCP 3 2 1 VCCP_FB DRVH 13 1 V5FILT PL501 2.2UH_PCMC063T-2R2MN_8A_20% 1 2 2 4 PGND VCCP_V5FILT 8 @ PC540 47P_0402_50V8J 1 2 TP 1 EN_PSV VOUT GND TON 3 2 1 2 PC539 1U_0603_10V6K B 1 PQ507 SIS412DN-T1-GE3_PAK1212-8 VCCP_SNB +3VS 2 7 2 PC536 0.22U_0402_6.3V6K PR529 422_0603_1% 1 2 +5VS 2 JUMP_43X79 0.1U_0603_25V7K 1 <16,30,37,42,49> SUSP# 4 PR527 PC535 2.2_0603_5% BST_VCCP1 2BST_VCCP-1 1 2 3 2 1 PR526 100K_0402_1% 1 2 2 1 PC534 10U_1206_25V6M 5 PR525 240K_0402_1% 1 2 VCCP_TON 2 PC547 @ 680P_0402_50V7K 2 PJ506 VCCP_IN PR532 31.6K_0402_1% PJ502 @ JUMP_43X79 2 1 1 2 +1.5V PJ504 VIN VCNTL 6 2 3 GND NC 5 VREF NC 7 4 VOUT NC 8 2 2 A TP 0.75V_REF 5 1 1 +1.5V PC520 1U_0402_6.3V6K PJ503 +1.05VSP 9 2 2 PJ505 1 1 +1.05VS 2 +0.75VSP @ JUMP_43X118 2 1 1 +0.75VS @ JUMP_43X79 1 +0.75VSP PC521 0.1U_0402_16V7K S PQ505 SSM3K7002FU_SC70-3 2 PC523 10U_0603_6.3V6M 2009/01/06 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 1 1 PR517 1K_0402_1% 2 1 D 2 PC522 @ 0.1U_0402_16V7K 3 1 SUSP 2 @ JUMP_43X118 G2992F1U_SO8 2 <42,48> PR534 0_0402_5% 1 20.75V_EN 2 G +3VALW 1 1 PR515 1K_0402_1% 2 PC519 4.7U_0805_6.3V6K 1 2 +1.5VP 1 2 PU502 0.75V_IN 2010/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title 1.5V/VCCP/0.75V Size Date: Document Number Rev 0.1 Tuesday, March 24, 2009 Sheet 1 47 of 52 A 5 4 3 1 2 PR637 @ 10K_0402_5% 2 1 +3VS PJ605 3 2 1 1 2 PR613 @ 2.2_0603_5% +5VS +VGA_COREP 7 8 2 1 PC637 0.01U_0402_25V7K 1 2 PR609 42.2K_0402_1% @ 1 2 PC634 10U_0603_6.3V6M 1 2 1 PC633 10U_0603_6.3V6M 2 2 + PC616 10U_0603_6.3V6M 1 PC619 330U_D2_2.5VY_R9M 1 2 PR615 0_0402_5% 2 PC615 330U_D2_2.5VY_R9M PR612 4.7_1206_5% VGA_SNB 2 1 + LG_VGA PJ602 +VGASENSE <21> 2 +VGA_COREP 2 1 1 +VGA_CORE @ JUMP_43X118 GPIO6 GPIO5 NB10M-GE 0 1 (Remove PR620) C PJ603 2 GPU_VID1 GPU_VID0 VGA_CORE 1 2 5 6 7 8 1 3 2 1 6 5 1 2 PR633 90.9K_0402_1% VGA_FB 1COMP_VGA 2 FSET_VGA 1 2 4 2 4 1 PC618 680P_0402_50V7K ISEN_VGA 2 1 PR614 6.81K_0402_1% PQ605 SI4634DY-T1-E3_SO8 9 3 2 1 ISEN 5 6 7 8 1 10 PC640 2.2U_0603_6.3V6K 2 1 1 @ JUMP_43X118 0 0 0.92V GPIO6 GPIO5 PR619 4.32K_0402_1% GPU_VID1 GPU_VID0 VGA_CORE NB10P-GE 0 1 GVID0-2 0 0 0.9V 1.1V PJ606 1 +1.8VSP 1 2 2 +1.8VS 3 @ JUMP_43X39 PQ606B 2N7002KDW-2N_SOT363-6 4 1 2 2 PR621 10K_0402_5% 1 PQ606A 2N7002KDW-2N_SOT363-6 PR618 127K_0402_1% 2 1GVID0-1 5 PR624 10K_0402_1% D PL602 0.88UH_PCMB103E-R88MS_20A_20% 1 2 SW_VGA PQ604 SI4634DY-T1-E3_SO8 1 PGND PC639 6800P_0402_25V7K 2 1 PR634 2.37K_0402_1% 2 6 PR620 8.2K_0402_1% 1 2 GVID1-2 PC625 0.022U_0402_16V7K 1 2 1 1 1 2 <19> GPU_VID0 COMP_VGA-1 PC638 22P_0402_50V8J PR629 10K_0402_5% PQ603 SI7686DP-T1-E3_SO8 B+ 2 LG 11 +VGA_PVCC 2 C 2 1GVID1-1 2 PR630 10K_0402_1% 1 2 1 PC617 @ 330P_0402_50V7K 2 BOOT EN COMP 4 PU601 ISL6269CRZ-T_QFN16 FCCM PC613 @ 0.1U_0402_16V7K <19> GPU_VID1 1 13 14 UG PHASE 12 VCC FB 2VGA_EN 1 PR610 0_0402_5% PVCC VO VGA_FCCM3 2 PR636 @ 0_0402_5% VGA_EN VIN FSET 2 1 <16> 1 PGOOD GND 1 PC636 2.2U_0603_6.3V6K PR616 0_0402_5% 1 2 +5VS 2 @ JUMP_43X79 4 +VGA_VCC 2 2 +VGA_PVCC 1 PR635 1_0402_5% 15 17 16 BST_VGA 1 2BST_VGA-1 1 2 PR611 PC614 2.2_0603_5% 0.1U_0603_25V7K 2 PC612 10U_1206_25V6M 1 5 UG_VGA D PC611 10U_1206_25V6M 2 1 VGA_IN PC632 0.022U_0402_16V7K +3VS B 2 PU603 1 VIN VCNTL 6 2 GND NC 5 3 VREF NC 7 NC 8 TP 9 2 VOUT 2 4 LDO_1.8V_REF 1 PC627 0.1U_0402_16V7K +1.8VSP 1 PR628 1.24K_0402_1% 1 D 2 1 S PQ609 SSM3K7002FU_SC70-3 2 3 2 PC631 0.1U_0402_16V7K PC624 1U_0402_6.3V6K G2992F1U_SO8 2 SUSP 1 <42,47> PR632 100K_0402_1% 1 2LDO_1.8V_EN 2 G +5VS 1 PR623 1K_0402_1% 2 PC623 4.7U_0805_6.3V6K 1 2 LDO_1.8V_IN 1 PJ607 @ JUMP_43X39 1 1 B PC629 10U_0603_6.3V6M A A 2009/01/06 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title VGA_CORE/1.8VS/1.1VS Size Date: Document Number Rev 0.1 Tuesday, March 24, 2009 Sheet 1 48 of 52 5 4 3 2 1 D D PJ701 VTT_B+ 1 +1.1V_VCCPP PR704 2 VTT_BOOT-1 0_0603_5% 13 PGND 12 2 3 2 1 UG BOOT LG PC704 2.2U_0603_6.3V6K LG_VTT PQ701 SI7686DP-T1-E3_SO8 PL701 0.88UH_PCMB103E-R88MS_20A_20% 1 2 1 2 PR427 35.7K_0402_1% 5 6 7 8 1 1 + VTT_SNB 2 PC707 @ 680P_0402_50V7K 1 + 2 2 3 2 1 10 Rds=4.0mΩ PQ703 SI4634DY-T1-E3_SO8 VO PR711 2.2K_0402_1% 4 3 2 1 4 PQ702 SI4634DY-T1-E3_SO8 5 6 7 8 2 1 PR724 10_0402_5% PC710 0.01U_0402_25V7K 1 2 9 FB VTT_ISEN 1 C 1 VTT_COMP-1 2 11 +1.1V_VCCPP PR709 @ 4.7_1206_5% 2 PC711 6800P_0402_25V7K 1 2 PC709 <8> VTT_SELECT 22P_0402_50V8J 1 VTT_COMP 7 PC706 @ 0.1U_0402_16V7K 6 2 ISEN FSET EN COMP 5 2 1 VTT_FSET PR714 57.6K_0402_1% VTT_EN-1 1 <16,47> DGPU_PWROK 1 VFB=0.6V 1 PR710 0_0402_5% 1 2 PC705 2.2U_0603_6.3V6K PR713 49.9K_0402_1% VTT_FB 2 C B PHASE PU701 ISL6268CAZ-T_SSOP16 VCC VTT_PVCC 1 PC714 330U_D2E_2.5VM 4 14 PVCC 4 PC708 330U_D2E_2.5VM VTT_VCC PR707 4.7_0603_5% 1 2 VTT_VCC 1 <16,30,37,42,47> SUSP# VIN 5 PR706 0_0603_5% 1 2 PR712 @ 0_0402_5% 1 2 PGOOD GND 3 2 PC703 0.1U_0603_25V7K +5VS @ 1 2 VTT_BOOT1 2 2 8 1.1VS_PGOOD <5> VCCP_POK UG_VTT 1 PR701 0_0402_5% 1 2 SW_VTT 15 1 1 2 PC702 10U_1206_25V6M PC701 10U_1206_25V6M 2 1 @ JUMP_43X118 16 1 1 2 PR702 115K_0402_1% 2 2 B+ 2 PR716 1.58K_0402_1% PR725 0_0402_5% 2 1 VTT_FB-1 B VTT_SENSE <8> PR719 1.96K_0402_1% 2 H_VTTVID1= Low, 1.1V H_VTTVID1= High, 1.05V PJ702 +1.1V_VCCPP 2 2 1 1 +VCCP @ JUMP_43X118 PJ703 2 2 1 1 @ JUMP_43X118 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/01/06 Issued Date Deciphered Date 2010/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title +1.1VS_VTT Size Document Number Custom Date: Rev 0.1 Sheet Tuesday, March 24, 2009 1 49 of 52 5 4 3 2 1 1 2 GFXVR_IMON <8> PR835 1 2 @ 0_0402_5% VSS_AXG_SENSE <8> 14 3 2 1 62881_VID0 PR810 2 0_0402_5% + 2 2 PH801 10KB_0603_5%_ERTJ1VR103J PC820 680P_0402_50V7K 1 2 PR818 11K_0402_1% 1 2 PC823 0.1U_0402_16V7K 1 2 PC824 0.033U_0402_16V7K PR825 3.01K_0402_1% PR829 82.5_0402_1% 1 2ISUM-3 1 2 2 2 1 PR821 2 1 PR822 2 1 PR824 2 1 PR826 2 1 PR827 2 1 PR828 2 1 PR830 2 1 PR831 2 1 PR834 @ 10K_0402_1% 0_0402_5% 2 1 PR832 2 1 PR833 10K_0402_1% GFXVR_VID_0 <8> GFXVR_VID_1 <8> GFXVR_VID_2 <8> GFXVR_VID_3 <8> GFXVR_VID_4 <8> GFXVR_VID_5 <8> GFXVR_VID_6 <8> GFXVR_EN <8> PR823 100_0402_1% 1 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% B 2 62881_VID1 2ISUM-2 1 PR815 2.61K_0402_1% 1 GFXVR_PWRGD GFXVR_CLKEN# PR812 3.65K_0402_1% 1 PC815 330U_D2E_2.5VM_R9 GFX_SN 1 PC819 2.2U_0603_6.3V6K PR809 2.2_1206_5% PC814 330U_D2E_2.5VM_R9 2 +5VALW 0_0603_5% 4 + 2ISUM-4 1 VID1 21 2 20 VID2 22 62881_VID2 VID3 23 62881_VID3 VID4 24 62881_VID4 VID5 25 VID6 VID0 1 1 19 62881_VCCP 1 PR808 1 13 IMON BOOT 11 VDD 10 ISUM+ 8 9 VR_ON DPRSLPVR CLK_EN# 26 B 18 LG_GFX PC825 0.01U_0402_25V7K PC826 180P_0402_50V8J 1 PGOOD +GFX_COREP 17 2 2 VCCP PL802 0.56UH_MMD-10CZ-R56M-M1_19A_20% 1 2 16 LX_GFX ISUM-1 RBIAS 15 UG_GFX 1 3 LGATE 62881_VID5 PR817 8.06K_0402_1% VW 62881_VID6 1 VSSP 27 2 1 PR820 @ 10K_0402_1% PR816 17.8K_0402_1% PC822 22P_0402_50V8J 1 2 2 1 +GFX_COREP 2 PC821 150P_0402_50V8J 1GFX_FB-2 2 162881_RBIAS 1 PC817 100P_0402_50V8J 2 2 COMP 62881_VR_ON PR811 47K_0402_1% PC818 1000P_0402_50V7K 2 1 PR819 @ 1.91K_0402_1% PR814 825K_0402_1% 1 2GFX_FB-1 1 2 1 PR813 8.66K_0402_1% 2 1 4 UGATE PU801 ISL62881HRZ-T_QFN28_4X4 PHASE 2 62881_VW PQ801 AO4474_SO8 1 62881_COMP 5 PC811 0.22U_0603_16V7K 4 2 FB PR805 2.2_0603_5% 2 2 VSEN 2BST_GFX1 1 PQ802 TPCA8028_PSO8 7 6 C BST_GFX 1 5 62881_FB RTN AGND PC813 330P_0402_50V7K ISUM PC812 330P_0402_50V7K 62881_DPRSLPVR 28 PR806 +GFX_COREP 10_0402_5% 1 2 2 29 1 2 <8> VCC_AXG_SENSE 1 1 2 PC810 1000P_0402_50V7K <8> VSS_AXG_SENSE VIN ISUM- C 12 62881_VIN 5 6 7 8 ISUM+ 3 2 1 PR804 10_0402_5% 1 2 2 2 PC807 1U_0603_10V6K 2 1 PR803 22.6K_0402_1% 1_0603_5% PC809 0.22U_0402_6.3V6K 2 62881_VDD 1 1 1 +5VALW 2 PC808 0.22U_0603_25V7K PR802 0_0603_5% PR801 1 2 1 2 1 2 PC806 0.1U_0402_25V6 GFX_B+ PC803 10U_1206_25V6M 2 1 PL801 SMB3025500YA_2P 1 2 PC802 10U_1206_25V6M B+ 1 D PC801 2200P_0402_50V7K D ISUM+ GFXVR_DPRSLPVR <8> ISUM- PJ801 +GFX_COREP 2 2 1 1 +GFX_CORE @ JUMP_43X118 PJ802 A 2 2 A 1 1 @ JUMP_43X118 (15A,600mils ,Via NO.= 30) Compal Secret Data Security Classification Issued Date 2009/01/06 Deciphered Date 2010/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. GFX_CORE Size Date: Document Number Rev 0.1 Tuesday, March 24, 2009 Sheet 1 50 of 52 8 7 6 5 4 3 2 1 H H 1 2 +3VS <15> VGATE <12> CLK_EN# 1 PR904 1 PR905 1 PR906 G <37> VR_ON 2 PR903 1K_0402_5% 1 PR902 1.91K_0402_1% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% G CPU_B+ VBST1 DRVH1 21 BOOT_CPU1 2 1 BOOT_CPU1-1 1 2 PR921 0_0603_5% PC919 UGATE_CPU1 0.22U_0603_10V7K 1 2 +5VS PD2 1SS355_SOD323-2 PC901 220U_25V_M PC926 @ 10U_1206_25V6M 2 1 PC906 10U_1206_25V6M 2 1 1 2 PC905 10U_1206_25V6M PC904 2200P_0402_50V7K 2 1 PR913 17.8K_0402_1% 2 1 1CPU_SNB2 2 E PC927 @ 10U_1206_25V6M 2 1 PC923 10U_1206_25V6M 2 1 PL903 0.36UH_PCMC104T-R36MN1R17_30A_20% 1 4 CPU_CSP1-1 2 PR940 17.8K_0402_1% 2 1 PC924 680P_0402_50V7K 1 3 PR941 69.8K_0402_1% 2 1 2CPU_SN-1 1 2 PR942 PH902 28.7K_0402_1% 100K_0603_1%_TH11-4H104FT 1 2 PC925 0.033U_0402_16V7K C CPU_CSN1 PQ908 TPCA8036_PSO8 PR938 2.2_1206_5% CPU_CSP1 PQ907 TPCA8036_PSO8 3 2 1 3 2 1 4 2 1CPU_SNB1 2 5 5 1 PQ905 SI7686DP-T1-E3_SO8 <8> <8> <8> PC922 10U_1206_25V6M 2 1 PC921 2200P_0402_50V7K 2 1 PC920 @0.1U_0402_25V6 2 1 5 5 3 2 1 PQ906 SI7686DP-T1-E3_SO8 4 <8> <8> H_VID0 <8> H_VID1 <8> H_VID2 H_VID4 <8> <8> H_VID3 <8> H_VID5 PSI# H_VID6 1 2CPU_SN-2 1 2 PR914 PH901 28.7K_0402_1% 100K_0603_1%_TH11-4H104FT 1 2 PC913 0.033U_0402_16V7K D 3 2 1 VID0 20 VID1 19 VID3 VID2 18 17 VID5 VID4 16 15 PSI# DPRSLPVR VID6 14 13 12 PR901 69.8K_0402_1% 2 UGATE_CPU1 4 4 <5> PROC_DPRSLPVR +CPU_CORE 3 CPU_B+ 1 PR929 PROC_DPRSLPVR 1 PR930 PSI# 1 PR931 H_VID6 1 PR932 H_VID5 1 PR933 H_VID4 1 PR934 H_VID3 1 PR935 H_VID2 1 PR936 H_VID1 1 PR937 H_VID0 1 PR939 IMVP_IMON 1 PC909 680P_0402_50V7K +5VS CPU_IMON 2 0_0402_5% 2CPU_DPRSLPVR 0_0402_5% CPU_PSI# 2 0_0402_5% VID6 2 0_0402_5% VID5 2 0_0402_5% VID4 2 0_0402_5% VID3 2 0_0402_5% VID2 2 0_0402_5% VID1 2 0_0402_5% VID0 2 0_0402_5% 11 IMON 2 68_0402_5% 2 CPU_CSN2 PHASE_CPU1 22 VSNS 1 PR926 CPU_CSP2-1 2 CPU_CSP2 LL1 2CPU_VR_TT# 0_0402_5% PC902 @0.1U_0402_25V6 2 1 1 LGATE_CPU1 23 PQ904 TPCA8036_PSO8 2 24 2 10U_0603_6.3V6M PQ903 TPCA8036_PSO8 3 2 1 DRVL1 VR_TT# + PL902 0.36UH_PCMC104T-R36MN1R17_30A_20% 1 4 5 5 25 GNDSNS 4 3 2 1 PGND 7 PQ901 SI7686DP-T1-E3_SO8 2 1 PC916 PU901 TPS51621RHAR_QFN40_6X6 4 1 26 CSP1 3 2 1 3 2 1 CPU_TRIPSEL 1 CPU_OSRSEL 1 32 OSRSEL TRIPSEL CPU_PGOOD 33 31 CPU_CLK_EN# 34 PGOOD CLK_EN# VR_ON CPU_VR_ON V5IN 6 5 5 +5VS 2 2 2 CPU_TONSEL 1 35 CPU_ISLEW 1 37 36 TONSEL V5FILT 38 39 DROOP DRVL2 CSN1 THERM +VCCP ISLEW CPU_VREF 40 41 GND VREF CSN2 LGATE_CPU2 10 1 PR925 UGATE_CPU2 29 28 9 2 20K_0402_1% 30 VBST2 27 CPU_THERM <8> <8> VCCSENSE DRVH2 LL2 8 1 PR924 PR923 0_0402_5% 1 2 PR922 0_0402_5% 2 1 PD1 1SS355_SOD323-2 CSP2 5 PQ902 SI7686DP-T1-E3_SO8 PR912 2.2_1206_5% BOOT_CPU2 1 2 BOOT_CPU2-1 1 2 PR917 0_0603_5% PC910 PHASE_CPU2 0.22U_0603_10V7K CPU_VSNS H_PROCHOT# 1 2 1 2 VSSSENSE C +5VS GND 4 1 UGATE_CPU2 4 4 PR911 D 3 PR910 PC918 100P_0402_50V8J 1 470_0402_1% 2 CPU_CSP2-2 33P_0402_50V8J 2 CPU_CSN2-1 33P_0402_50V8J 2 CPU_CSN1-1 33P_0402_50V8J 2 CPU_CSP1-2 33P_0402_50V8J CPU_GNDSNS 0_0402_5% CPU_CSP1 2 PR920 1 PC912 1 PC914 1 PC915 1 PC917 0_0402_5% CPU_CSN2 2 PR918 CPU_CSN1 2 PR919 PC911 100P_0402_50V8J 1 470_0402_1% 1 470_0402_1% MODE B+ F PR909 E 1 470_0402_1% PR908 2CPU_MODE 1 0_0402_5% 2 1 PR916 CPU_CSP2 2 PR915 0_0402_5% 1 2 PC908 0.22U_0603_10V7K 249K_0402_1% F 2 2 PC903 2.2U_0603_6.3V6K 1 2 PC907 68P_0402_50V8J CPU_DROOP 2 1 PR907 5.76K_0402_1% 1 +3VS 1 CPU_VREF 2 PR927 @ 1K_0402_5% +5VS PL901 HCB4532KF-800T90_1812 1 2 +VCCP B H_VID0 2 1PR943 1K_0402_5% H_VID0 2 1PR944 @ 1K_0402_5% H_VID1 2 1PR945 1K_0402_5% H_VID1 2 1PR946 @ 1K_0402_5% H_VID2 2 1PR947 1K_0402_5% H_VID2 2 1PR948 @ 1K_0402_5% H_VID3 2 1PR949 @ 1K_0402_5% H_VID3 2 1PR950 1K_0402_5% H_VID4 2 1PR951 @ 1K_0402_5% H_VID4 2 1PR952 1K_0402_5% H_VID5 2 1PR953 1K_0402_5% H_VID5 2 1PR954 @ 1K_0402_5% H_VID6 2 1PR955 @ 1K_0402_5% H_VID6 2 1PR956 1PR957 PROC_DPRSLPVR 2 PROC_DPRSLPVR 2 10K_0402_5% B 1K_0402_5% 1PR958 @ 1K_0402_5% A A Compal Secret Data Security Classification 2009/01/06 Issued Date Deciphered Date 2010/01/06 Title CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 8 7 6 5 4 3 Compal Electronics, Inc. Size Date: 2 Document Number Tuesday, March 24, 2009 Rev 0.1 51 Sheet 1 of 52 5 4 3 2 Version change list (P.I.R. List) Item D 1 Page 1 of 2 for PWR Reason for change PG# Modify List Date Phase 1 D 2 3 4 5 6 C C 7 8 9 10 B B 11 12 13 14 15 16 A 20081022 17 2009/01/06 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2009/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 A 2 Title PIR (PWR) Size Document Number Custom Rev 0.1 Date: Tuesday, March 24, 2009 Sheet 1 52 of 52
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