LA8001PR10_OPT_0116 Compal LA 8001P

User Manual:

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Compal Confidential
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2

QIWY3 M/B Schematics Document
Intel IVY Bridge Processor with DDRIII + Panther Point PCH
nVIDIA N13X

2011-12-23

3

3

REV:1.0

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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B

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Title

Cover Page
Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
E

1

of

64

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Compal confidential

D

Chief River

File Name : Y480

Intel
IVY Bridge
Processor

nVIDIA N13P-GT/GL1
PCI-E X16
Gen 1/2/3

1

VRAM 64*32
GDDR5*8

HDMI
CONN

1

DDR3-SO-DIMM X2
BANK 0, 1, 2, 3

Socket-rPGA989
37.5mm*37.5mm

Dual Channel
DDR3-1333(1.5V)
DDR3-1600(1.5V)

HDMI1.4a

UP TO 16G

SATA3.0 HDD CONN
FDI *8
100MHz
2.7GT/s

optimus 2012

CRT Connector

E

DMI2 *4
100MHz
5GT/s

SATA3.0 HDD (SSD)
SATA ODD CONN

6*SATA
(port0,1 Support SATA3)

2

Intel
Panther Point

optimus 2012

LVDS
Connector

PCI Express
Mini card Slot 1

USB(WiMAX)

CMOS Camera
BlueTooth CONN
USB PORT 3.0 x2(Left)

FCBGA 989 Balls
25mm*25mm

WLAN/WiMAX

PCI Express
Mini card Slot 2

14*USB2.0

PCH

6*PCI-E x1

PCI-E(WLAN)

2

4*USB3.0

SATA(SSD)

WLAN/WiMAX
USB PORT 2.0 x1(Right)

HD Audio

SSD

LPC BUS

SPI ROM
BIOS

USB PORT 3.0 x1 (Right)
Audio Board
with USB charger

3

3

EC
ENE KB9012

Card Reader
JBM389C
SD/MMC/MS/XD
Audio Board

Arthros
AR8161/AR8151

WLAN/WiMAX
RJ45 CONN
Sub-borad
4

2Channel Speaker

LAN(Gbe)
Int.KBD

Array Digital MIC

Audio Codec
RealTek
ALC269-VC

Touch Pad

Audio Jacks
Stereo
HeadPhone Output
Microphone Input

Thermal Sensor

Audio Board

EMC1403/2103

POWER BOARD

4

Function BOARD
Compal Secret Data

Security Classification

Audio Board
A

2011/07/21

Issued Date

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

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Title

Compal Electronics, Inc.
MB Block Diagram

Size Document Number
Custom
Date:

Rev
1.0

Monday, January 16, 2012

Sheet
E

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of

64

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E

Voltage Rails
SIGNAL

+5VS

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

STATE

+VALW

+V

+VS

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

Clock
ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

+3VS
Full ON

+1.5VS
power
plane

+VCCSA
+V1.5S_VCCP
+CPU_CORE

1

1

+1.5V

+5VALW

+VGA_CORE

+B

+GFX_CORE
+3VALW
+1.8VS
+1.05VS
State
+0.75VS

BOARD ID Table

Board ID / SKU ID Table for AD channel

+3.3VS_VGA
+1.5VS_VGA
+1.05VS_VGA

S0

O

S3
2

S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist

O

O

O

O

O

X

O

O

X

X

USB Port Table

O

X

X

X

USB 2.0 USB 3.0

X

X

X

X

3

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA

VGA

KB9012

+3VALW
KB9012

+3VALW
PCH

+3VALW
PCH

+3VALW
PCH

+3VALW

X
X
X
X
V
+3VS

BATT

KE9012

V
X
X
X
X

X
X
X
X
V
+3VS

+3VALW

SODIMM WLAN
WWAN

X
X
V
+3VS
X
X

Thermal
Sensor PCH

X
X
V
+3VS
X
X

X
X
X
X
V
+3VS

Address

EC SM Bus1 address
Device

EC SM Bus2 address
Device

Smart Battery

0001 011X b

Thermal Sensor EMC1403-2

Address
1001_101xb

PCH SM Bus address

4

Device

Address

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

XHCI

X
V
+3VS
X
X
X

EHCI1

Vcc
Ra/Rc/Re

PCB Revision
0.1

O

SMBUS Control Table

SOURCE

Board ID
0
1
2
3
4
5
6
7

1
2
3
4

EHCI2

Board ID

0
1
2
3
4
5
6
7

3.3V +/- 5%
10K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

4 External
USB Port

Port
0
1
2
3
4
5
6
7
8
9
10
11
12
13

USB Port (Right Side)
USB Port (Left Side)
USB Port (Left Side)
Camera

USB Port (Right Side)
Mini Card(WLAN)
Mini Card(TV)
Blue Tooth

PCIE PORT LIST
Port

1
2
3
4
5
6
7
8

Device
LAN
WLAN
TV
Card Reader

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

Project
QIWY3

EVT
DVT
PVT
MP
EVT
DVT
PVT
MP

QIWY3
QIWY3
QIWY3
QIWY4
QIWY4
QIWY4
QIWY4

2

BOM Structure Table
BOM Structure
OPTI@
HDMI@
TV@
CHG@
NOCHG@
BT@
CMOS@
8161@
8151@
8161S@
8151S@
SURGE@
61@
51@
X76@
S1G@
S2G@
H1G@
H2G@
GL@
GT@
GE@
GTGE@
GC6@
NOGC6@
1403@
2103@
KBL@
ME@
@

BTO Item
OPTIMUS part
HDMI part
TV module part
USB charger part
No USB charger part
Blue Tooth part
CMOS Camera part
AR8161 LAN part
AR8151 LAN part
AR8161 LAN surge part
AR8151 LAN surge part
AR8151&8161 LAN surge part
X76 P/N for AR8161

3

X76 P/N for AR8151
X76 Level part for VRAM
X76 P/N for Samsun VRAM 1G
X76 P/N for Samsun VRAM 2G
X76 P/N for Hynix VRAM 1G
X76 P/N for Hynix VRAM 2G
N13P-GL part
N13P-GT part
N13E-GE part
N13P-GT&N13E-GE common part
NV CG6 support part
NV no CG6 support part
EMC1403 thermal part
EMC2103 thermal part
K/B Light part
ME part

4

Unpop

ZZZ1

Issued Date
DA80000Q800

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/21

2012/12/31

Deciphered Date

Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

D

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
E

3

of

64

5

4

Hot plug detect for IFP link C

VGA and GDDR5 Voltage Rails

D

ACTIVE

3

GPIO

I/O

Function Description

GPIO0

OUT

-

GPU VID4

GPIO1

OUT

-

GPU VID3

GPIO2

OUT

N/A

GPIO3

OUT

N/A

GPIO4

OUT

N/A

GPIO5

OUT

-

GPU VID1

GPIO6

OUT

-

GPU VID2

GPIO7

OUT

N/A

GPIO8

I/O

-

Thermal Catastrophic Over Temperature

GPIO9

OUT

-

GC6 event

GPIO10

OUT

-

Memory VREF Control

GPIO11

OUT

-

GPU VID0

GPIO12

IN

GPIO13

OUT

-

GPIO14

OUT

N/A

GPIO15

IN

N/A

GPIO16

OUT

GPIO17
GPIO18
GPIO19

GPU
(4)

Mem
(1,5)

NVCLK
/MCLK

Products

(W)

(W)

(MHz)

(V)

(A)

(W)

(A)

N13X
128bit
1GB
GDDR5

TBD

TBD

TBD

TBD

TBD

TBD

TBD

FBVDDQ
(GPU+Mem)
(1.35V)

PCI Express I/O and
(1.05V)
PLLVDD
(6)
(1.8V)

I/O and
PLLVDD
(1.05V)

(W)

(A)

(W)

(mA)

(W)

(mA)

(W)

(mA)

(W)

(mA)

(W)

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

FBVDD
(1.35V)

NVVDD

Other
(3.3V)

D

Physical
Strapping pin
ROM_SCLK

Logical
Strapping Bit3

Power Rail

Logical
Strapping Bit2
SUB_VENDOR

Logical
Strapping Bit1

Logical
Strapping Bit0

SLOT_CLK_CFG

PEX_PLL_EN_TERM

RAM_CFG[2]

RAM_CFG[1]

RAM_CFG[0]

FB[0]

SMB_ALT_ADDR

VGA_DEVICE

+3VS_VGA

PCI_DEVID[4]

ROM_SI

+3VS_VGA

RAM_CFG[3]

ROM_SO

+3VS_VGA

FB[1]

STRAP0

+3VS_VGA

USER[3]

USER[2]

USER[1]

STRAP1

+3VS_VGA

STRAP2

+3VS_VGA

PCI_DEVID[3]

PCI_DEVID[2]

PCI_DEVID[1]

PCI_DEVID[0]

STRAP3

+3VS_VGA

SOR3_EXPOSED

SOR2_EXPOSED

SOR1_EXPOSED

SOR0_EXPOSED

STRAP4

+3VS_VGA

PCIE_SPEED_
CHANGE_GEN3

PCIE_MAX_SPEED

DP_PLL_VDD33V

USER[0]

3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]

RESERVED

3GIO_PAD_CFG_ADR[0]

Device ID

C

(10K pull High)

GPU VID5

(100K pull low)

N13P-GT
(28nm)

0x0FDB

N13E-GE
(28nm)

0x0FDB

N13P-GL1
(40nm)

0x0DE9

C

ROM_SO

ROM_SCLK

STRAP4

STRAP3

STRAP2

STRAP1

STRAP0

N/A

N13P-GT

PU 10K

PU 5K

PD 45K

PD 5K

PD 10K

PD 35K

PU 45K

IN

N/A

N13E-GE

PU 10K

PU 5K

PD 45K

PD 5K

PD 25K

PD 35K

PU 45K

IN

N/A

N13P-GL

PD 10K

PD 15K

NC

PU 10K

PD 45K

PU 45K

IN

N/A

GPU

GPU
FB Memory (GDDR5)

B

1

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)

(N13Px GPIO)

AC Power Detect Input

2

Samsung
2500MHz

+3VS_VGA

NC

N13P-GT

N13E-GE

N13P-GL

ROM_SI

ROM_SI

ROM_SI

PD 45K

PD 45K

PD 45K

PD 35K

PD 35K

PD 35K

PD 30K

PD 30K

PD 30K

PD 25K

PD 25K

PD 25K

K4G10325FG-HC04
B

32Mx32
+VGA_CORE
tNVVDD >0

Hynix
2500MHz

H5GQ1H24BFR-T2C

Samsung
2500MHz

K4G20325FD-FC04

Hynix
2500MHz

H5GQ2H24MFR-T2C

+1.5VS_VGA

32Mx32
tFBVDDQ >0

+1.05VS_VGA
tPEX_VDD >0

64Mx32

1. all power rail ramp up time should be larger than 40us

64Mx32

Other Power rail

+3VS_VGA
A

A

Tpower-off <10ms

Compal Secret Data

Security Classification
Issued Date

1.all GPU power rails should be turned off within 10ms
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

5

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Title

Compal Electronics, Inc.
VGA Notes List

Size

Document Number

Rev
1.0

QIWY3 LA-8001P
Date:

Sheet

Monday, January 16, 2012
1

4

of

64

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3

2

D

1
R1
24.9_0402_1%

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

<16>
<16>
<16>
<16>

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

B28
B26
A24
B23

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

<16>
<16>
<16>
<16>

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

G21
E22
F21
D21

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

<16>
<16>
<16>
<16>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

G22
D22
F20
C21

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

A21
H19
E19
F18
B21
C20
D18
E17

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

A22
G19
E20
G18
B20
C19
D19
F17

<16> FDI_FSYNC0
<16> FDI_FSYNC1
FDI_INT

1

<16>

<16> FDI_LSYNC0
<16> FDI_LSYNC1

R7
24.9_0402_1%

J18
J17

FDI_INT

H20

FDI_LSYNC0
FDI_LSYNC1

J19
H17

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC

2

B

FDI_FSYNC0
FDI_FSYNC1

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

DMI

B27
B25
A25
B24

A18
A17
B16

eDP_HPD
C15
D15
C17
F16
C16
G15
C18
E16
D16
F15

eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX
eDP_AUX#
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

eDP

EDP_COMP

eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

PCI EXPRESS* - GRAPHICS

+1.05VS

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

Intel(R) FDI

C

<16>
<16>
<16>
<16>

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

J22
J21
H22

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

D

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms

+1.05VS

2

JCPU1A

1

PEG_COMP

PCIE_CRX_GTX_N[0..15] <23>

PCIE_CRX_GTX_N15
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N0

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane #
socket pin map definition

CFG2

*

definition matches

0:Lane Reversed
C

PCIE_CRX_GTX_P[0..15] <23>

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

PCIE_CRX_GTX_P15
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P0

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

PCIE_CTX_GRX_C_N15
PCIE_CTX_GRX_C_N14
PCIE_CTX_GRX_C_N13
PCIE_CTX_GRX_C_N12
PCIE_CTX_GRX_C_N11
PCIE_CTX_GRX_C_N10
PCIE_CTX_GRX_C_N9
PCIE_CTX_GRX_C_N8
PCIE_CTX_GRX_C_N7
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N0

C1 1
C2 1
C3 1
C4 1
C5 1
C6 1
C7 1
C8 1
C9 1
C10 1
C11 1
C12 1
C13 1
C14 1
C15 1
C16 1

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PCIE_CTX_GRX_C_P15
PCIE_CTX_GRX_C_P14
PCIE_CTX_GRX_C_P13
PCIE_CTX_GRX_C_P12
PCIE_CTX_GRX_C_P11
PCIE_CTX_GRX_C_P10
PCIE_CTX_GRX_C_P9
PCIE_CTX_GRX_C_P8
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P0

C20 1
C23 1
C25 1
C30 1
C18 1
C22 1
C28 1
C32 1
C19 1
C24 1
C29 1
C17 1
C21 1
C27 1
C26 1
C31 1

OPT@
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
2 0.22U_0402_10V6K
OPT@
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
OPT@
2 0.22U_0402_10V6K
2 0.22U_0402_10V6K

PCIE_CTX_GRX_N15
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P0

PCIE_CTX_GRX_N[0..15] <23>

B

PCIE_CTX_GRX_P[0..15] <23>

TYCO_2013620-2_IVY BRIDGE
ME@

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

5

of

64

5

4

3

2

1

H : Sandy Bridge
PROC_SEL
L : IVY Bridge

JCPU1B

Place R10,R11 close to U4

D

D

AN34

PROC_SELECT#
SKTOCC#

+1.05VS
1

T14

R9
62_0402_5%

H_CATERR#

PAD

CATERR#

2

H_THEMTRIP#

<19> H_THRMTRIP#

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

H_PM_SYNC_R

AM34

PM_SYNC

R26
H_CPUPWRGD_R

2
2

100P_0402_50V8J

1

AP33

R29
1
2 PM_DRAM_PWRGD_R
130_0402_5%

R27

V8

UNCOREPWRGOOD

SM_DRAMPWROK

10K_0402_5%
1

2

R12
R13

2
2

1 1K_0402_5%
1 1K_0402_5%

A16
A15

SM_DRAMRST#

R8

H_DRAMRST#

AK1
A5
A4

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

AP29
AP27

XDP_PRDY#
XDP_PREQ#

AR26
AR27
AP30

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TMS
XDP_TDI
XDP_TDO

AR28
AP26

XDP_TDI
XDP_TDO

XDP_TCK
R24
XDP_TRST# R25

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

BUF_CPU_RST#

AR33

9/23 ESD Request

RESET#

TCK
TMS
TRST#

JTAG & BPM

<16> H_PM_SYNC

PWR MANAGEMENT

R22
0_0402_5%
1
2

C

C550

CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>

DPLL_REF_CLK
DPLL_REF_CLK#

PRDY#
PREQ#

0_0402_5%1

R11

0_0402_5%
1
2
1
2
0_0402_5%

DDR3
MISC

H_PROCHOT#_R

AN33

THERMAL

H_PECI
R15
56_0402_5%
1
2

H_PROCHOT#

<19> H_CPUPWRGD

CLK_CPU_DMI_R
CLK_CPU_DMII#_R

+1.05VS

Reserve 43 Ohm resistor closs to EC(250~750mils)
<19,42> H_PECI

<42,50> H_PROCHOT#

AL33

BCLK
BCLK#

CLOCKS

C26

<19> H_SNB_IVB#

MISC

R10
A28
A27

TDI
TDO

DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

AL35 XDP_DBRESET#

H_DRAMRST# <7>

R16
R17
R18

1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%

2
2
2

DDR3 Compensation Signals

+1.05VS

R28

R20
R21
R23

2
2
2
2
2

1 1K_0402_5%

2

1
1
1
@
1
1

51_0402_5%
51_0402_5%
51_0402_5%

C

PU/PD for JTAG signals

51_0402_5%
51_0402_5%

+3VS

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

TYCO_2013620-2_IVY BRIDGE
ME@
+3VS

+3VALW

Buffered reset to CPU
+3VS

C33
0.1U_0402_16V4Z

B

1

U1

4

PM_SYS_PWRGD_BUF

1.05V

3

74AHC1G09GW_TSSOP5

1

U2
BUFO_CPU_RST# 4

SN74LVC1G07DCKR_SC70-5

1
2

NC

Y
A

3V
PCH_PLTRST#

PCH_PLTRST# <18>

3

S

2
G

R34
43_0402_1%
1
2

BUF_CPU_RST#

R35 @
0_0402_5%

@
Q1
2N7002_SOT23

2

1 2
<10> RUN_ON_CPU1.5VS3#

D

3

@
R33
39_0402_5%

1

2

R32
75_0402_5%
2

O
A

C34
0.1U_0402_16V4Z

P

B

1

2

<16> PM_DRAM_PWRGD

1

2

5

+1.05VS

G

1

5

R30
200_0402_5%

P

2

G

R338
10K_0402_5%

+1.5V_CPU_VDDQ

1

1

R65
0_0402_5% @
2

B

2

1

<16> SYS_PWROK

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR(2/7) PM,XDP,CLK

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

6

of

64

5

4

3

2

JCPU1D

D

C

<12> DDR_A_BS0
<12> DDR_A_BS1
<12> DDR_A_BS2

B

<12> DDR_A_CAS#
<12> DDR_A_RAS#
<12> DDR_A_WE#

C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

AE10
AF10
V6

SA_BS[0]
SA_BS[1]
SA_BS[2]

AE8
AD9
AF9

SA_CAS#
SA_RAS#
SA_WE#

D

S

H_DRAMRST#

3

1

2

<6> H_DRAMRST#

M_CLK_DDR0 <12>
<13> DDR_B_D[0..63]
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>

SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]

AA5
AB5
V10

M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

AB4
AA4
W9

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

AB3
AA3
W10

SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

AK3
AL3
AG1
AH1

DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>

SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]

AH3
AG3
AG2
AH2

M_ODT0 <12>
M_ODT1 <12>

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

C4
G6
J3
M6
AL6
AM8
AR12
AM15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS#[0..7]

D4
F6
K3
N6
AL5
AM9
AR11
AM14

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS[0..7]

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

<12>

<12>

DDR_A_MA[0..15] <12>

<13> DDR_B_BS0
<13> DDR_B_BS1
<13> DDR_B_BS2

<13> DDR_B_CAS#
<13> DDR_B_RAS#
<13> DDR_B_WE#

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AA9
AA7
R6

SB_BS[0]
SB_BS[1]
SB_BS[2]

AA10
AB8
AB9

SB_CAS#
SB_RAS#
SB_WE#

AE2
AD2
R9

M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>

SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]

AE1
AD1
R10

M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

AB2
AA2
T9

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

AA1
AB1
T10

SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

AD3
AE3
AD6
AE6

DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>

SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

AE4
AD4
AD5
AE5

M_ODT2 <13>
M_ODT3 <13>

D7
F3
K6
N3
AN5
AP9
AK12
AP15

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS#[0..7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

C7
G3
J6
M3
AN6
AP8
AK11
AP14

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS[0..7]

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

ME@

ME@

+1.5V

SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]

D

<13>

C

<13>

DDR_B_MA[0..15] <13>

B

R37
1K_0402_5%

DDR3_DRAMRST#_R

R38
1K_0402_5%
2

1

DDR3_DRAMRST# <12,13>

Q2
BSS138_NL_SOT23-3

1

2

G

R39
4.99K_0402_1%

AB6
AA6
V9

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

2

@ R36
0_0402_5%
1
2

SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]

1

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR SYSTEM MEMORY A

<12> DDR_A_D[0..63]

DDR SYSTEM MEMORY B

JCPU1C

1

A

A

2 DRAMRST_CNTRL
0_0402_5%

1
R40

<15> DRAMRST_CNTRL_PCH
<10> DRAMRST_CNTRL

1
R64

<42> DRAMRST_CNTRL_EC

2
0_0402_5%

1

@

9/5 Reserve for Deep S3

2

Issued Date

Module design used 0.047u

5

Compal Secret Data

Security Classification
C35
0.047U_0402_16V4Z

4

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

7

of

64

5

4

3

2

1

CFG Straps for Processor

1

CFG2

2

R41
1K_0402_1%
D

D

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane #
socket pin map definition

CFG2

*

definition matches

0:Lane Reversed

1

CFG4

@

R42
1K_0402_1%

2

JCPU1E

R161
49.9_0402_1%

2
RSVD32

W8

RSVD33
RSVD34
RSVD35

AT26
AM33
AJ27

Display Port Presence Strap

*

CFG4

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG5
1

AJ31
AH31
AJ33
AH33
AJ26

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
RSVD5

2

VSS_VAL_SENSE

1

R196
49.9_0402_1%

INTEL 12/28 recommand
to add R187, R161, R291, R196
Please place as close as JCPU1

F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29

T8
J16
H16
G16

@ R43
1K_0402_1%

@ R44
1K_0402_1%

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

AR35
AT34
AT33
AP35
AR34

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10

RSVD51
RSVD52

CFG[6:5]

B34
A33
A34
B35
C35

*10: x8, x8 - Device 1 function 1 enabled ; function 2

B

disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

AJ32
AK32

CFG7

BCLK_ITP
BCLK_ITP#

RSVD24
RSVD25

@R45
@
R45
1K_0402_1%

AN35
AM35
2

J20
B18

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

C

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

2

VCC_AXG_VAL_SENSE
2 100_0402_1% VSS_AXG_VAL_SENSE
VCC_VAL_SENSE
2 100_0402_1% VSS_VAL_SENSE

VSS_AXG_VAL_SENSE

2

L7
AG7
AE7
AK2

1

@R72
@
R72 1

1

R2
0_0402_5%

RSVD28
RSVD29
RSVD30
RSVD31

RSVD37
RSVD38
RSVD39
RSVD40

RESERVED

1

@R71
@
R71 1

B

T13

CFG6

R187
49.9_0402_1%

R291
49.9_0402_1%

PAD

AH27
AH26

2

2

1

+VCC_CORE

VCC_DIE_SENSE
VSS_DIE_SENSE

1

2

+VCC_GFXCORE_AXG

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

1

CFG4
CFG5
CFG6
CFG7

C

AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

CFG

CFG2

J15

RSVD27

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

AT2
AT1
AR1

PEG DEFER TRAINING
KEY

B1

CFG7
A

1: (Default) PEG Train immediately following xxRESETB
de assertion
0: PEG Wait for BIOS for training

TYCO_2013620-2_IVY BRIDGE

A

ME@

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

8

of

64

5

4

3

JCPU1F

2

1

POWER

+VCC_CORE

PEG AND DDR

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

VCCIO40

J23

D

C

+1.05VS

Place the PU resistor close to CPU
R46
75_0402_5%

2
2

C36
0.1U_0402_10V7K

1

1

VIDALERT#
VIDSCLK
VIDSOUT

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

AJ29
AJ30
AJ28

R47
R48
R49

1
1
1

2 43_0402_5%
2 0_0402_5%
2 0_0402_5%

R50

2

1 130_0402_5%

VR_SVID_ALRT# <57>
VR_SVID_CLK <57>
VR_SVID_DAT <57>
+1.05VS
B

Place the PU resistor close to CPU

VCC_SENCE 100ohm +-1% pull-up to VCC near processor

1

+VCC_CORE

A

B10
A10

R52 1
R53 1
10_0402_1%
1

2
2

0_0402_5%
0_0402_5%

VCCSENSE <57>
VSSSENSE <57>
@ R73 1

+1.05VS

2 100_0402_1%

R54
100_0402_1%

VCCIO_SENSE <55>
VSSIO_SENSE <55>

VSSIO_SENSE

2

2

VCCIO_SENSE
VSS_SENSE_VCCIO

AJ35 VCCSENSE_R
AJ34 VSSSENSE_R
R1294
2

1

VCC_SENSE
VSS_SENSE

2

R51
100_0402_1%

R1297
10_0402_1%
1

B

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

SVID

C

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

SENSE LINES

D

+1.05VS

8.5A

CORE SUPPLY

QC=94A
DC=53A

A

VSS_SENCE 100ohm +-1% pull-down to GND near processor
TYCO_2013620-2_IVY BRIDGE

Compal Secret Data

Security Classification

ME@

Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR(5/7) PWR,BYPASS

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

9

of

64

4

3

+1.5V

2

+1.5V_CPU_VDDQ

@ J1
1

2

PAD-OPEN 4x4m
1
0_0402_5%

@
2

2

1
3

1

1
2

1

RUN_ON_CPU1.5VS3#

2
G
S

+1.5V_CPU_VDDQ

2

DMN3030LSS-13_SOP8L-8

1

2

1

2

1

2

C287
0.1U_0402_10V6K

Q3
2N7002_SOT23
@

1
2
3
4

S
S
S
G

C286
0.1U_0402_10V6K

R56
100K_0402_5%

D
D
D
D

C96
0.1U_0402_10V6K

R667
100K_0402_5%
@

D

U3
8
7
6
5

D

C92
0.1U_0402_10V6K
C95
0.1U_0402_10V6K

+VSB

+3VALW

+1.5V

1

R55
220_0402_5%
@

2
R668

2

<48,53,55> SUSP

1

1

5

D

R1349

S

2
1
470K_0402_5%
R57
330K_0402_5%
2
@

1

1
Q9
2N7002_SOT23
@

D
Q4
2N7002_SOT23

2
G
S

C97
0.01U_0603_50V7K

Place the PU/PD resistor close to CPU within 2 inch
(Reserve power side)

2
R59 @
VCC_AXG_SENSE <57>

+VCC_GFXCORE_AXG

VSS_AXG_SENSE <57>

2
R66
100_0402_1%

+1.5V_CPU_VDDQ

R132
1K_0402_1%
@

6/8 Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

2

11/07 Change type to 0603

1

2

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

1

2

1

2

1

2

+
2

@

+VCCSA
+VCCSA

M27
M26
L26
J26
J25
J24
H26
H25

1

2

1

2

1

1

2

2

1
@

+
2

@

VREF

11/07 Change type to 0603
VCCSA_SENSE

H23

+VCCSA_SENSE <54>
@
R68

VCCSA_VID[0]
VCCSA_VID[1]

VCCIO_SEL

C22
C24

A19

2 0_0402_5%

1

H_VCCSA_VID0 <54>
H_VCCSA_VID1 <54>6/3

modify for VCCSA 4-Level voltage

6/3 Add VCCIO_SEL for processor select
H_VCCP_SEL

TYCO_2013620-2_IVY BRIDGE

R69

1

R234 2
1
10K_0402_5%
R266 2
1
@ 10K_0402_5%

Issued Date

A

1.05V

+3VALW

0

1.0V

Compal Electronics, Inc.
2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Voltage

1
+3VS

Compal Secret Data
2011/07/21

VCCIO_SEL

2 0_0402_5%

ME@

Security Classification

4

C

R63
1K_0402_1%

B

6/9 change 330U to 22U X2

5

1

2
2

1

C128
330U_D2_2.5VY_R9M

2

2

1

6A

VCCPLL1
VCCPLL2
VCCPLL3

RUN_ON_CPU1.5VS3

1
1

C127
10U_0603_6.3V6M

2

1

C132
1U_0402_6.3V6K

@

1

C131
1U_0402_6.3V6K

2

1

C130
10U_0603_6.3V6M

@

1

C345
22U_0805_6.3V6M

2

A

C279
22U_0805_6.3V6M

1

B6
A6
A2

@

1

+1.5V_CPU_VDDQ

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

C126
10U_0603_6.3V6M

+1.8VS_VCCPLL

@Q5
@
Q5
AP2302GN-HF_SOT23-3

6/28 Follow module design

5A
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

+V_SM_VREF

3

R62
1K_0402_1%

All VREF traces should keep 20/20 mils(wide/spacing)

C125
10U_0603_6.3V6M

R67
0_0805_5%
1
2

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

+V_DDR_REFA_R
+V_DDR_REFB_R

C124
10U_0603_6.3V6M

+1.8VS

DDR3 -1.5V RAILS

DRAMRST_CNTRL

1

1
R139
1K_0402_1%
@

2

3

BSS138_SOT23
2
G

Q7

2

S

D

1

B

SA RAIL

S
@

2

C122
10U_0603_6.3V6M

+V_DDR_REFA_R
+V_DDR_REFB_R

2 0_0402_5%
2 0_0402_5%

1
1

2

AL1

B4
D1

@

R88
1K_0402_1%

C121
10U_0603_6.3V6M

R74
R75

+V_SM_VREF_CNT

SM_VREF

R61
0_0402_5%
2
1

R77
1K_0402_1%

C120
10U_0603_6.3V6M

@

100_0402_1%
1

C119
10U_0603_6.3V6M

+VREF_DQ_DIMMB

R89
2

+1.5V
@

0.1U_0402_16V4Z 1
C114

MISC

3

100_0402_1%
2

C123
330U_D2_2.5VY_R9M

1

@
1

C118
10U_0603_6.3V6M

+VREF_DQ_DIMMA

BSS138_SOT23

D

Q8

VAXG_SENSE
VSSAXG_SENSE

GRAPHICS

2
G

<7> DRAMRST_CNTRL

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

1.8V RAIL

C

SENSE
LINES

1

R76

AK35
AK34

C117
10U_0603_6.3V6M

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

2

46A

1

JCPU1G

1

POWER

+VCC_GFXCORE_AXG

2

<6> RUN_ON_CPU1.5VS3#

2

1
0_0402_5%

<42,48,53,55,56> SUSP#

D

2
G
3

<42,48,55> CPU1.5V_S3_GATE

2
R58 @

1

2

1
0_0402_5%

RUN_ON_CPU1.5VS3

3

1

RUN_ON_CPU1.5VS3#

2

Title

PROCESSOR(6/7) PWR
Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

10

of

64

5

4

3

2

JCPU1H
D

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25

C

B

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

1

JCPU1I

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

D

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

VSS

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

C

B

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

ME@

ME@

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR(7/7) VSS

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

11

of

64

5

4

3

2

<7> DDR_A_D[0..63]

+1.5V
+VREF_DQ_DIMMA
1

+1.5V

R78
1K_0402_1%

<7> DDR_A_DQS[0..7]

+1.5V

4BA2/6W

<7> DDR_A_DQS#[0..7]

DDR3 SO-DIMM A

DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
C

<7> DDR_CKE0_DIMMA

DDR_CKE0_DIMMA

<7> DDR_A_BS2

DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_CS0_DIMMA#
M_ODT0 <7>

<7>
R80
1K_0402_1%

M_ODT1 <7>

2

DDR_A_D38
DDR_A_D39

2

@
R81
1K_0402_1%

1

2

@

1

2

1

2

1

2

1

2

1

2

1

2

1

2

2

1

2

1

2

1
+

C148
220U_6.3V_M

B

2

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47

Layout Note:
Place near DIMM

DDR_A_D52
DDR_A_D53
DDR_A_DM6

+0.75VS

DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7

1

2

DDR_A_D62
DDR_A_D63
SMB_DATA_S3
SMB_CLK_S3

1

2

1

2

1

2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

Layout Note:
Place near DIMM

A

SMB_DATA_S3 <13,15,36>
SMB_CLK_S3 <13,15,36>

+0.75VS

1/76BA1/86W

Compal Secret Data

Security Classification

LCN_DAN06-K4806-0103

Issued Date

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

2

1

DDR_A_D44
DDR_A_D45

ME@

5

1

C156
0.1U_0402_10V6K

DDR_A_DM4

1

C147
0.1U_0402_10V6K

1

C155
0.1U_0402_10V6K

+VREF_CA
DDR_A_D36
DDR_A_D37

+1.5V

C154
0.1U_0402_10V6K

1

M_ODT1

+1.5V

C146

2

(0.1uF_402_10V)*4

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA#
M_ODT0

(10uF_0603_6.3V)*8

10U_0603_6.3V6M

206

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

C153

G2

DDR_A_BS1
DDR_A_RAS#

Layout Note:
Place near DIMM

10U_0603_6.3V6M

G1

M_CLK_DDR1
M_CLK_DDR#1

1U_0402_6.3V6K

205

OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)

DDR_A_MA2
DDR_A_MA0

C160
1U_0402_6.3V6K

2

R83
10K_0402_5%

2

1

C162
0.1U_0402_10V6K

1

C290
2.2U_0603_6.3V6K

+3VS

DDR_A_MA6
DDR_A_MA4

C159
1U_0402_6.3V6K

DDR_A_D58
DDR_A_D59
1 R82
2
10K_0402_5%

A

DDR_A_MA11
DDR_A_MA7

C158
1U_0402_6.3V6K

DDR_A_DM7

<7>

C288

DDR_A_D56
DDR_A_D57

DDR_CKE1_DIMMA

DDR_A_MA15
DDR_A_MA14

C145

DDR_A_D50
DDR_A_D51

DDR_CKE1_DIMMA

10U_0603_6.3V6M

DDR_A_DQS#6
DDR_A_DQS6

C

C144

DDR_A_D48
DDR_A_D49

DDR_A_D30
DDR_A_D31

C152

DDR_A_D42
DDR_A_D43

DDR_A_DQS#3
DDR_A_DQS3

C143

DDR_A_DM5

DDR_A_D28
DDR_A_D29

C142

DDR_A_D40
DDR_A_D41

DDR_A_D22
DDR_A_D23

C151

DDR_A_D34
DDR_A_D35

DDR_A_DM2

C150
2.2U_0603_6.3V6K

DDR_A_DQS#4
DDR_A_DQS4

<7,13>

DDR_A_D20
DDR_A_D21

C149
0.1U_0402_10V6K

DDR_A_D32
DDR_A_D33

B

DDR3_DRAMRST#

DDR_A_D14
DDR_A_D15

10U_0603_6.3V6M

<7> DDR_CS1_DIMMA#

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_DM1
DDR3_DRAMRST#

10U_0603_6.3V6M

DDR_A_WE#
DDR_A_CAS#

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_A_D12
DDR_A_D13

10U_0603_6.3V6M

<7> DDR_A_WE#
<7> DDR_A_CAS#

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDR_A_D6
DDR_A_D7

10U_0603_6.3V6M

<7> DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

D

DDR_A_DQS#0
DDR_A_DQS0

10U_0603_6.3V6M

<7> M_CLK_DDR0
<7> M_CLK_DDR#0

M_CLK_DDR0
M_CLK_DDR#0

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_A_D4
DDR_A_D5

1

DDR_A_D2
DDR_A_D3

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2

DDR_A_DM0

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1

2

DDR_A_D0
DDR_A_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2

2
1
2

1

C141
2.2U_0603_6.3V6K

2

C140
0.1U_0402_10V6K

R79
1K_0402_1%

<7> DDR_A_MA[0..15]

JDIMM1
+VREF_DQ_DIMMA

1

D

1

3

2

Title

Compal Electronics, Inc.
DDRIII-SODIMM SLOT1

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P
Sheet

Monday, January 16, 2012
1

12

of

64

5

4

3

2

1

<7> DDR_B_D[0..63]

+1.5V

<7> DDR_B_DQS[0..7]
1

4BA2/6W

+VREF_DQ_DIMMB

R84
1K_0402_1%
2
1
2

2

DDR_B_D0
DDR_B_D1

1

2

C157

C289

1

0.1U_0402_10V6K

R85
1K_0402_1%

+1.5V

<7> DDR_B_MA[0..15]

JDIMM2
+VREF_DQ_DIMMB
2.2U_0603_6.3V6K

D

<7> DDR_B_DQS#[0..7]

+1.5V

DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

205

G1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0

D

DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
DDR3_DRAMRST#

DDR3_DRAMRST#

<7,12>

DDR_CKE3_DIMMB

<7>

DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

C

C

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
<7> M_CLK_DDR2
<7> M_CLK_DDR#2

M_CLK_DDR2
M_CLK_DDR#2

<7> DDR_B_BS0

DDR_B_MA10
DDR_B_BS0

<7> DDR_B_WE#
<7> DDR_B_CAS#

DDR_B_WE#
DDR_B_CAS#

<7> DDR_CS3_DIMMB#

DDR_B_MA13
DDR_CS3_DIMMB#

2

2

B

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47

Layout Note:
Place near DIMM

DDR_B_D52
DDR_B_D53
DDR_B_DM6

+0.75VS

DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7

SMB_DATA_S3
SMB_CLK_S3

1/76BA1/86W

1

2

DDR_B_D62
DDR_B_D63

1

2

1

2

1

2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

A

Layout Note:
Place near DIMM

SMB_DATA_S3 <12,15,36>
SMB_CLK_S3 <12,15,36>
+0.75VS

TYCO_2-2013287-1

Compal Secret Data

Security Classification
Issued Date

ME@

4

2

1

DDR_B_D44
DDR_B_D45

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

1

C172
0.1U_0402_10V6K

2

1

C171
0.1U_0402_10V6K

2

1

C170
0.1U_0402_10V6K

2

1

C169
0.1U_0402_10V6K

2

1

C168

2

1

10U_0603_6.3V6M

2

1

C167

2

1

10U_0603_6.3V6M

2

1

C166

206

1

10U_0603_6.3V6M

G2

2

@

C165

2
10K_0402_5%

2

1

10U_0603_6.3V6M

2

1
R97

2

@

1U_0402_6.3V6K

2

1

C178
0.1U_0402_10V6K

1

C177
2.2U_0603_6.3V6K

+3VS

DDR_B_D38
DDR_B_D39

R87
1K_0402_1%

C176
1U_0402_6.3V6K

1 R95
2
10K_0402_5%

DDR_B_DM4

1

C175
1U_0402_6.3V6K

DDR_B_D58
DDR_B_D59
A

1

+1.5V

C174
1U_0402_6.3V6K

DDR_B_DM7

R86
1K_0402_1%

M_ODT3 <7>

+VREF_CB
DDR_B_D36
DDR_B_D37

(0.1uF_402_10V)*4

C173

DDR_B_D56
DDR_B_D57

<7>

C164

DDR_B_D50
DDR_B_D51

DDR_CS2_DIMMB#
M_ODT2 <7>

(10uF_0603_6.3V)*8

+1.5V

10U_0603_6.3V6M

DDR_B_DQS#6
DDR_B_DQS6

M_ODT3

DDR_B_BS1 <7>
DDR_B_RAS# <7>

10U_0603_6.3V6M

DDR_B_D48
DDR_B_D49

DDR_CS2_DIMMB#
M_ODT2

Layout Note:
Place near DIMM

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

C163

DDR_B_D42
DDR_B_D43

DDR_B_BS1
DDR_B_RAS#

10U_0603_6.3V6M

DDR_B_DM5

M_CLK_DDR3
M_CLK_DDR#3

C282

DDR_B_D40
DDR_B_D41

DDR_B_MA2
DDR_B_MA0

C161

DDR_B_D34
DDR_B_D35

DDR_B_MA6
DDR_B_MA4

10U_0603_6.3V6M

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_MA11
DDR_B_MA7

C281
2.2U_0603_6.3V6K

B

DDR_B_MA15
DDR_B_MA14

C280
0.1U_0402_10V6K

DDR_B_D32
DDR_B_D33

DDR_CKE3_DIMMB

1

DDR_B_BS2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

2

<7> DDR_B_BS2

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

1

DDR_CKE2_DIMMB

2

<7> DDR_CKE2_DIMMB

3

2

Title

Compal Electronics, Inc.
DDRIII-SODIMM SLOT2

Size

Document Number

Rev
1.0

QIWY3 LA-8001P
Date:

Sheet

Monday, January 16, 2012
1

13

of

64

5

4

3

2

1

PCH_RTCX1

W=20mils

W=20mils

+RTCVCC

+RTCBATT

1
R98

PCH_RTCX2

2
10M_0402_5%
Y1

R99
1K_0402_5%
1
2

1

1

15P_0402_50V8J

C179
1U_0603_10V4Z

CLRP1
SHORT PADS

2

1

2
D

2

32.768KHZ_12.5PF_CM31532768DZFT

1

1
C180

2

C181
18P_0402_50V8J

2

D

CMOS
+RTCVCC

U4A

+3VS

<41> HDA_SPKR

+3V_PCH

*

RTCRST#

PCH_SRTCRST#

G22

SRTCRST#

SM_INTRUDER#

K22

PCH_INTVRMEN

C17

HDA_BIT_CLK

N34

<41> HDA_SDIN0

L34

HDA_SPKR

T10

HDA_RST#

K34

HDA_SDIN0

E34

HDA_SDOUT

@ 1 1K_0402_5%

G34

Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]

INTRUDER#
INTVRMEN

R108

HDA_SYNC

1 1K_0402_5%

2

R107 1

This signal has a weak internal pull-down

*

ME_FLASH

<42> ME_FLASH

+3V_PCH

@

R317 2

SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

2 1K_0402_1%

PCH_GPIO33

C36

1 10K_0402_5%

PCH_GPIO13

N32

1

PCH_JTAG_TCK

J3

51_0402_5%
R110

PCH_JTAG_TMS

H7

PCH_JTAG_TDI

K5

PCH_JTAG_TDO

H1

11/08 Follow DG change to +5VS
R112
33_0402_5%
1
2
R114
33_0402_5%
1
2
R116
33_0402_5%
1
2
R118
33_0402_5%
1
2

R121
200_0402_5%

2

1

LPC_FRAME# <36,42>

1 10K_0402_5%

2

AM10
AM8
AP11
AP10

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AD7
AD5
AH5
AH4

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AB8
AB10
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

HDA_DOCK_RST# / GPIO13

JTAG_TCK

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

JTAG_TMS

SATAICOMPO

JTAG_TDI
JTAG_TDO

SATAICOMPI

SATA3COMPI
SPI_CLK_PCH

T3

SPI_SB_CS0#

Y14

SPI_SB_CS1#

T1

SPI_SI

V4

SPI_SO_R

U3

SPI_CLK

SATA3RBIAS

SERIRQ

<42>

SATA_ITX_C_DRX_N0 0.01U_0402_16V7K 2
SATA_ITX_C_DRX_P0 0.01U_0402_16V7K 2

SATA_ITX_C_DRX_N1 0.01U_0402_16V7K 2
SATA_ITX_C_DRX_P1 0.01U_0402_16V7K 2

SATA_ITX_C_DRX_N2 0.01U_0402_16V7K 2
SATA_ITX_C_DRX_P2 0.01U_0402_16V7K 2

1 C184
1 C185

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

1 C273
1 C272

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_DRX_N1
SATA_ITX_DRX_P1

1 C186
1 C187

SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
SATA_ITX_DRX_N2_CONN
SATA_ITX_DRX_P2_CONN

Y7
Y5
AD3
AD1

SATA_COMP

R111
37.4_0402_1% +1.05VS_VCC_SATA
1
2

SATA3_COMP

R113
49.9_0402_1%
1
2

Y11
Y10
AB12
AB13
AH1

SPI_MOSI
SPI_MISO

SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19

SATA_DTX_C_IRX_N1 <40>
SATA_DTX_C_IRX_P1 <40>
SATA_ITX_DRX_N1 <40>
SATA_ITX_DRX_P1 <40>

HDD

SATA_DTX_C_IRX_N2 <40>
SATA_DTX_C_IRX_P2 <40>
SATA_ITX_DRX_N2_CONN <40>
SATA_ITX_DRX_P2_CONN <40>

ODD

RBIAS_SATA3 R115 1

P3

SATALED#

V14

PCH_GPIO21

P1

BBS_BIT0_R

2 SPI_WP#_1
3.3K_0402_5%

R246 1

2 SPI_HOLD#_1
3.3K_0402_5%

C275
1
2

1 10K_0402_5%

+3VS
+3VS

R303
0_0402_5%
SPI_SB_CS1# 1
2 SPI_SB_CS1#_R
SPI_SO_R
1
2 SPI_SO_L1
SPI_WP#_1
33_0402_5%
R294

U9
1
2
3
4

CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)

0.1U_0402_16V4Z
R299
SPI_HOLD#_1
33_0402_5%
SPI_CLK_PCH_1 1
2 SPI_CLK_PCH
SPI_SI_R1
1
2 SPI_SI

8
7
6
5

+3VS

+3VS

4MB P/N : SA00003K800

SPI_CLK_PCH

PCH_JTAG_TDI
R127 1

2 SPI_WP#
3.3K_0402_5%

R129 1

2 SPI_HOLD#
3.3K_0402_5%

R124
33_0402_5%
@

+3VS
C191
1
2

R130
0_0402_5%
SPI_SB_CS0# 1
2SPI_SB_CS0#_R
SPI_SO_R
1
2 SPI_SO_L
SPI_WP#
33_0402_5%
R131
A

U5
1
2
3
4

CS#
DO
WP#
GND

VCC
HOLD#
CLK
DI

8
7
6
5

C190
22P_0402_50V8J
@
0.1U_0402_16V4Z
R298
SPI_HOLD#
33_0402_5%
SPI_CLK_PCH_0 1
2 SPI_CLK_PCH
SPI_SI_R
1
2 SPI_SI
33_0402_5%
R133

W25Q32BVSSIG_SO8

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

B

33_0402_5%
R199

W25Q16BVSSIG_SO8

SATA_DET# <36>

2

@

+3VS

2 750_0402_1%

R120 1
2
10K_0402_5%
R119 1
2
10K_0402_5%
2
1
R1418 @
0_0402_5%
R316 2

R292 1

R128
100_0402_1%

R126
100_0402_1%

C

1

2

SSD

+3VS

+1.05VS_SATA3

SPI_CS0#
SPI_CS1#

SATA_DTX_C_IRX_N0 <36>
SATA_DTX_C_IRX_P0 <36>
SATA_ITX_DRX_N0 <36>
SATA_ITX_DRX_P0 <36>

SPI ROM FOR ME
& Non-share ROM.
2MB P/N : SA00003FO10

Y3
Y1
AB3
AB1

1

2

PCH_JTAG_TMS

2

2

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

EC and Mini card debug port

+3VS
R104

V5
AM3
AM1
AP7
AP5

<36,42>
<36,42>
<36,42>
<36,42>

@

R125
100_0402_1%
@

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

R123
200_0402_5%

1

1

PCH_JTAG_TDO

HDA_DOCK_EN# / GPIO33

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

PANTHER-POINT_FCBGA989

1
R122
200_0402_5%

@
2

@

@

+3V_PCH

1

+3V_PCH

1

+3V_PCH

HDA_SDOUT

2

<41> HDA_SDOUT_AUDIO

HDA_RST#

Q10
BSS138_NL_SOT23-3
HDA_SYNC
1

R1353
1M_0402_5%

<41> HDA_RST_AUDIO#

3

LPC_FRAME#

E36
K36

SATA3RCOMPO

D

B

HDA_SYNC_R

S

<41> HDA_SYNC_AUDIO

+5VS
HDA_BIT_CLK

G

<41> HDA_BITCLK_AUDIO

HDA_SDOUT

1
2
0_0402_5%

2

D36

LDRQ0#
LDRQ1# / GPIO23

LPC

HDA_SYNC

@

On Die PLL VR Select is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Chief River platfrom

FWH4 / LFRAME#

SERIRQ

HDA_BCLK

R109
+3V_PCH

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

SERIRQ

HDA_SYNC

HIGH= Enable ( No Reboot )
LOW= Disable (Default)

R106 2

D20

RTCX2

2

C

HDA_SPKR

2 1K_0402_5%

PCH_RTCRST#

C38
A38
B37
C37

RTCX1

JTAG

*

@

C20

SPI

R105 1

PCH_RTCX2

SATA 6G

2

A20

SATA

C182
1U_0603_10V4Z

(INTVRMEN should always be pull high.)

PCH_RTCX1

RTC

1

1

INTVRMEN

Integrated VRM enable
烉Integrated
* LH烉
VRM disable

2

CLRP3
SHORT PADS

C183
1U_0603_10V4Z
1
2
R103 20K_0402_5%
1
2
R100 20K_0402_5%

2

PCH_INTVRMEN

2 330K_0402_5%

1

1

2

R102 1

+RTCVCC

IHDA

SM_INTRUDER#

2 1M_0402_5%

CLRP2
SHORT PADS

R101 1

4

3

2

Title

A

Compal Electronics, Inc.
PCH (1/8) SATA,HDA,SPI, LPC, XDP

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

14

of

64

5

4

3

2

1

U4B

BE34
BF34
BB32
AY32

D

Card Reader

<46> PCIE_PRX_DTX_N4
<46> PCIE_PRX_DTX_P4
<46> PCIE_PTX_C_DRX_N4
<46> PCIE_PTX_C_DRX_P4

C277
C276

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

1
1

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

BG36
BJ36
AV34
AU34

PERN3
PERP3
PETN3
PETP3

BF36
BE36
AY34
BB34

PERN4
PERP4
PETN4
PETP4

BG37
BH37
AY36
BB36

LAN
C

R153
R154

<37> CLK_PCIE_LAN#
<37> CLK_PCIE_LAN
<37> CLKREQ_LAN#
+3V_PCH

WLAN

<36> CLK_PCIE_WLAN1#
<36> CLK_PCIE_WLAN1
<36> WLAN_CLKREQ1#
+3VS

R151
R152

2 0_0402_5%
2 0_0402_5%

1
1

PERN6
PERP6
PETN6
PETP6

BG40
BJ40
AY40
BB40

PERN7
PERP7
PETN7
PETP7

BE38
BC38
AW38
AY38

PERN8
PERP8
PETN8
PETP8

CLKREQ_LAN#_R

2 0_0402_5%
1 10K_0402_5%

R149
R150

1
1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_WLAN1#_R
CLK_PCIE_WLAN1_R

R156
R158

1
2

2 0_0402_5%
1 10K_0402_5%

WLAN_CLKREQ1#_R

Y40
Y39
J2
AB49
AB47
M1
AA48
AA47

+3VS

Card Reader

<46> CLK_PCIE_CARD_PCH#
<46> CLK_PCIE_CARD_PCH
<46>

CPPE#
+3V_PCH

R301

2

R312
R311

1
1

R342

1

R168

2

1 10K_0402_5%

PCH_GPIO20

2 0_0402_5% CLK_PCIE_CARD_PCH#_R
2 0_0402_5% CLK_PCIE_CARD_PCH_R
@

2 0_0402_5%

CPPE#_R

PERN5
PERP5
PETN5
PETP5

BJ38
BG38
AU36
AV36

CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R

1
2

PERN2
PERP2
PETN2
PETP2

V10
Y37
Y36
A8

SMBDATA

SML0ALERT# / GPIO60
SML0CLK
SML0DATA

+3V_PCH

R165

2

1 10K_0402_5%

PCH_GPIO26

+3V_PCH

R147

2

1 10K_0402_5%

PCH_GPIO44

L12
V45
V46
L14

C9

PCH_SMBDATA

+3V_PCH

2.2K_0402_5%
R136 2
1
+3V_PCH

3

DRAMRST_CNTRL_PCH

A12
C8

1
R335
1
R336

G12

DRAMRST_CNTRL_PCH <7>

2
2.2K_0402_5%
2 R329
1
2
+3V_PCH 1K_0402_5%
2.2K_0402_5%
2
1
+3V_PCH
R140
10K_0402_5%

C13

PCH_HOT#
SML1CLK

SML1DATA / GPIO75

M16

SML1DATA

1
2
R135
2.2K_0402_5%

CL_CLK1
CL_DATA1
CL_RST1#

2.2K_0402_5%
1
2 R137
+3VS
1
2
R138
2.2K_0402_5%
4 SMB_DATA_S3

SMB_CLK_S3 <12,13,36>

DIMM1
DIMM2
MINI CARD
SMB_DATA_S3 <12,13,36>

DMN66D0LDW-7 2N_SOT363-6
Q60B

D

+3V_PCH
Q61A
DMN66D0LDW-7 2N_SOT363-6
EC_SMB_CK2
6
1

PCH_HOT# <42>

2.2K_0402_5%
R141 2
1

+3V_PCH

2
R142
2.2K_0402_5%

4

EC_SMB_CK2 <23,39,42>

VGA
EC
thermal sensor

+3VS

1

3

EC_SMB_DA2

EC_SMB_DA2 <23,39,42>

DMN66D0LDW-7 2N_SOT363-6
Q61B

M7
T11

+3V_PCH

P10

R143
10K_0402_5%

CLKOUT_PCIE0N
CLKOUT_PCIE0P
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P

PCIECLKRQ1# / GPIO18
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P

PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P

CLKIN_GND1_N
CLKIN_GND1_P

PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N
CLKIN_DOT_96P

1 10K_0402_5%
Y43
Y45

R134

E14

PEG_A_CLKRQ# / GPIO47

CLKOUT_PCIE1N
CLKOUT_PCIE1P

H14

SML1CLK / GPIO58

SML1ALERT# / PCHHOT# / GPIO74

PCIECLKRQ0# / GPIO73

10K_0402_5%
2
1

PCH_SMBCLK

2

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PCH_GPIO11

5

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

SMBCLK

E12

2

1
1

SMBALERT# / GPIO11

5

C194
C195

PERN1
PERP1
PETN1
PETP1

2

BG34
BJ34
AV32
AU32

R144
0_0402_5%
1
2

1

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

SMBUS

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

Link

1
1

Controller

<36> PCIE_PRX_DTX_N2
<36> PCIE_PRX_DTX_P2
<36> PCIE_PTX_C_DRX_N2
<36> PCIE_PTX_C_DRX_P2

C192
C193

CLOCKS

WLAN

<37> PCIE_PRX_DTX_N1
<37> PCIE_PRX_DTX_P1
<37> PCIE_PTX_C_DRX_N1
<37> PCIE_PTX_C_DRX_P1

PCI-E*

LAN

Q60A
DMN66D0LDW-7 2N_SOT363-6
6
1 SMB_CLK_S3

CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKIN_SATA_N
CLKIN_SATA_P

PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P

REFCLK14IN

PCIECLKRQ5# / GPIO44

CLKIN_PCILOOPBACK

M10 PEG_CLKREQ#_R
AB37
AB38

CLK_PCIE_VGA#_R
CLK_PCIE_VGA_R

AV22
AU22

CLK_CPU_DMI#
CLK_CPU_DMI

R146 1
R148 1

CLK_REQ_VGA# <23>
CLK_PCIE_VGA#
CLK_PCIE_VGA

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_VGA# <23>
CLK_PCIE_VGA <23>

CLK_CPU_DMI#
CLK_CPU_DMI

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

R349 1
R347 1

@

2
2

C

10K_0402_5%
10K_0402_5%

@

AM12
AM13
BF18
BE18

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

R155 1
R157 1

2
2

10K_0402_5%
10K_0402_5%

BJ30
BG30

CLKIN_DMI2#
CLKIN_DMI2

R159 1
R160 1

2
2

10K_0402_5%
10K_0402_5%

G24
E24

CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M

R162 1
R163 1

2
2

10K_0402_5%
10K_0402_5%

AK7
AK5

CLK_BUF_PCIE_SATA# R164 1
CLK_BUF_PCIE_SATA R166 1

2
2

10K_0402_5%
10K_0402_5%

K45

CLK_BUF_ICH_14M

2

10K_0402_5%

H45

CLK_PCI_LPBACK

V47
V49

XTAL25_IN
XTAL25_OUT

Y47

XCLK_RCOMP

R167 1

CLK_PCI_LPBACK <18>

B

B

XTAL25_IN

+3V_PCH

R170

2

1 10K_0402_5%

PCH_GPIO56

E6
V40
V42

+3V_PCH

R172

2

1 10K_0402_5%

PCH_GPIO45

T13
V38
V37

+3V_PCH

R174

2

1 10K_0402_5%

PCH_GPIO46

K12
AK14
AK13

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

XTAL25_IN
XTAL25_OUT

PEG_B_CLKRQ# / GPIO56
XCLK_RCOMP

XTAL25_OUT
R171
90.9_0402_1%
1
2

PCIECLKRQ7# / GPIO46

C196
27P_0402_50V8J

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67

1

1

PCIECLKRQ6# / GPIO45
CLKOUT_PCIE7N
CLKOUT_PCIE7P

1
R169
Y2
4 NC

+1.05VS_VCCDIFFCLKN

CLKOUT_PCIE6N
CLKOUT_PCIE6P

FLEX CLOCKS

AB42
AB40

2

OSC

2
1M_0402_5%
OSC
NC

3
2

1

25MHZ_12PF_X3G025000DC1H~D

2

C197
27P_0402_50V8J

K43
F47
H47

LAN_48M

K49

PCH_GPIO67

PANTHER-POINT_FCBGA989

1
R182

2
@

PCH_LAN_48M <37>

22_0402_5%
PCH_GPIO67 <19>

BIOS Request SKU ID

CLK_BUF_ICH_14M

@ R175
33_0402_5%
2
1

@ C198
22P_0402_50V8J
1
2

Reserve for EMI please close to PCH

CLK_PCI_LPBACK
A

@ R176
33_0402_5%
2
1

@ C199
22P_0402_50V8J
1
2

A

Reserve for EMI please close to PCH

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (2/8) PCIE, SMBUS, CLK

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

15

of

64

5

4

3

2

1

D

D

U4C

B

Y

4

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

<5>
<5>
<5>
<5>

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

SYS_PWROK <6>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW24
AW20
BB18
AV18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

BJ24

DMI_ZCOMP

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

+1.05VS_VCC_EXP

5

U6

R180
100K_0402_1%
@

C

BG25
BH21

4mil width and place
within 500mil of the PCH

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

AW16

FDI_INT

AV12

FDI_FSYNC0

BC10

FDI_FSYNC1

FDI_LSYNC0

AV14

FDI_LSYNC0

FDI_LSYNC1

BB10

FDI_LSYNC1

DSWVRMEN

A18

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

FDI_INT <5>
FDI_FSYNC0

<5>

FDI_FSYNC1

<5>

FDI_LSYNC0

<5>

FDI_LSYNC1

<5>

+RTCVCC

VGATE

R188 1

<42> PCH_PWROK

R190 1

2 0_0402_5%

R302 1

2 0_0402_5%

<57>

<42> PCH_APWROK

AEPWROK can be connect to
PWROK if iAMT disable

@

+3VS

SYS_PWROK

2
R191

1 300_0402_5%

PM_DRAM_PWRGD

R194

2

1 10K_0402_5%

SUSWARN#

For Deep S3

R197

1 10K_0402_5%

2

<42,51>

ACIN

PCH_RSMRST#_R

P12

PWROK

L22

APWROK

L10

PCH_RSMRST#_R
R193
0_0402_5%
R1455 0_0402_5%
SUSWARN#_R
2
1
DS3@
1

<42> SUSWARN#

2

K3

PM_DRAM_PWRGD B13

1
R198

<42> PBTN_OUT#
R192

1
0_0402_5%

@
<6> PM_DRAM_PWRGD

+3V_PCH

12/23 change to 300Ohm for S5 power saving

R184

2 0_0402_5%

<42> EC_RSMRST#

B

1 SYS_RST#
10K_0402_5%

2

D29

1

+3V_PCH

2

PBTN_OUT#_R
2
0_0402_5%

2 RB751V_SOD323 AC_PRESENT_R
R200 2 PCH_GPIO72
1
8.2K_0402_5%
R201
2
1 RI#
10K_0402_5%

C21
K16
E20
H20
E10
A10

SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#

DPWROK
WAKE#

N3

SUS_STAT# / GPIO61

G8

SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_A#

ACPRESENT / GPIO31
BATLOW# / GPIO72

SLP_SUS#
PMSYNCH

RI#

B9

CLKRUN# / GPIO32

SUSWARN#/SUSPWRDNACK/GPIO30
PWRBTN#

E22

SLP_LAN# / GPIO29

*
0_0402_5%
1
2 PCH_RSMRST#_R
R181

PCH_DPWROK_R
R185
0_0402_5%
WAKE#
1
2
PCIE_WAKE# <19,36,37>
1
2 10K_0402_5%
+3V_PCH
R186
PM_CLKRUN#
PAD
T73
1
2
+3VS
R189
@
8.2K_0402_5%
SUS_STAT#
1
2
R253
10K_0402_5%

N14

SUSCLK

D10

PM_SLP_S5#

H4

PM_SLP_S4#

F4

PM_SLP_S3#

烉
烉

DSWODVREN - On Die DSW VR Enable
H Enable
L Disable

R183
330K_0402_5%
@

SUSCLK <42>
PM_SLP_S5# <42>
PM_SLP_S4# <42>
PM_SLP_S3# <42>

G10
R1447
0_0402_5%
1
G16 PM_SLP_SUS#_R2
DS3@
AP14

H_PM_SYNC

K14

PCH_GPIO29

PANTHER-POINT_FCBGA989

1

DSWODVREN

2

SUSACK#

For Deep S3

C12

System Power Management

<42>

R1457 0_0402_5%
SUSACK#_R
2
1
DS3@

C

R179
330K_0402_5%
2

2

+3VS

DMI_IRCOMP
2
49.9_0402_1%
RBIAS_CPY
2
750_0402_1%

1
R177
1
R178

FDI

<5>
<5>
<5>
<5>

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

DMI

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BC24
BE20
BG18
BG20

1

A

2

<5>
<5>
<5>
<5>

1

1

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

P

VGATE
PCH_PWROK

G

3

MC74VHC1G08DFT2G SC70 5P

<5>
<5>
<5>
<5>

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

Can be left NC
when IAMT is not
support on the
platfrom

B

PM_SLP_SUS# <42>

For Deep S3
H_PM_SYNC <6>
PAD

Can be left NC if no use
integrated LAN.

T74

10/06 Test point request

1

+5VALW

100K_0402_5%
R1120
DS3@

2

1 200K_0402_5%

AC_PRESENT_R

R257

2

1 10K_0402_5%

SUSWARN#

<48> PM_SLP_SUS

PM_SLP_SUS#

S

Q118
2N7002_SOT23

DS3@
100K_0402_5%
R1121

@
2

11/08 Resreve for Deep S3

D

2
G

1

@

1

R195

PM_SLP_SUS

2

For Deep S3

3

+3V_DSW

+3VS
A

A

@
R1290

2

1 200_0402_5%

PM_DRAM_PWRGD

09/05 add for Deep S3

7/28 Modify follow Module Design.
Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (3/8) DMI,FDI,PM,

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

16

of

64

5

4

3

2

1

D

D

U4D

C

CTRL_CLK
CTRL_DATA

2 2.2K_0402_5%
2 2.2K_0402_5%
2.37K_0402_1%
R206
2
1

T40
K47
T45
P39
AF37
AF36

LVD_IBG
LVD_VBG

LVD_VREF

AE48
AE47

LVD_VREFH
LVD_VREFL

<33> LVDS_ACLK#
<33> LVDS_ACLK

AK39
AK40

LVDSA_CLK#
LVDSA_CLK

<33> LVDS_A0#
<33> LVDS_A1#
<33> LVDS_A2#

AN48
AM47
AK47
AJ48

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

<33> LVDS_A0
<33> LVDS_A1
<33> LVDS_A2

AN47
AM49
AK49
AJ47

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

AF40
AF39

LVDSB_CLK#
LVDSB_CLK

DAC_BLU

<34>

DAC_GRN

<34>

DAC_RED

R208 2

DAC_BLU
1 150_0402_1%

R209 2

DAC_GRN
1 150_0402_1%

R210 2

DAC_RED
1 150_0402_1%

AH43
AH49
AF47
AF43

N48
P49
T49

Pull up R for CONN SIDE

<34> CRT_DDC_CLK
<34> CRT_DDC_DATA

CRT_DDC_CLK
CRT_DDC_DATA

T39
M40

AP39
AP40

SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD

B

M47
M49

<34> CRT_HSYNC
<34> CRT_VSYNC

T43
T42

CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN

1

CRT_IREF

R202
2.2K_0402_5%
HDMI@

R203
2.2K_0402_5%
HDMI@

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

P38
M39

HDMICLK
HDMIDAT

AT49
AT47
AT40

HDMICLK <35>
HDMIDAT <35>

TMDS_B_HPD <35>

AV42 TMDS_B_DATA2#_PCH
AV40 TMDS_B_DATA2_PCH
AV45 TMDS_B_DATA1#_PCH
AV46 TMDS_B_DATA1_PCH
AU48 TMDS_B_DATA0#_PCH
AU47 TMDS_B_DATA0_PCH
AV47 TMDS_B_CLK#_PCH
AV49 TMDS_B_CLK_PCH

HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@

P46
P42

Colse connector

C200
C201
C202
C203
C204
C205
C206
C207

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K

HDMI_TX2-_CK <35>
HDMI_TX2+_CK <35>
HDMI_TX1-_CK <35>
HDMI_TX1+_CK <35>
HDMI_TX0-_CK <35>
HDMI_TX0+_CK <35>
HDMI_CLK-_CK <35>
HDMI_CLK+_CK <35>

HDMI

C

AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
B

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

PANTHER-POINT_FCBGA989

2

R211
1K_0402_1%

1

SDVO_INTN
SDVO_INTP

+3VS

1

AM42
AM40

L_CTRL_CLK
L_CTRL_DATA

LVDS_IBG

AH45
AH47
AF49
AF45

<34>

L_DDC_CLK
L_DDC_DATA

SDVO_STALLN
SDVO_STALLP

2

+3VS

EDID_CLK
EDID_DATA

<33> EDID_CLK
<33> EDID_DATA

L_BKLTCTL

AP43
AP45

2

R204 1
R205 1

SDVO_TVCLKINN
SDVO_TVCLKINP

Digital Display Interface

Pull up R for CONN SIDE

P45

PCH_PWM

L_BKLTEN
L_VDD_EN

LVDS

<33>

J47
M45

CRT

PCH_ENBKL
PCH_ENVDD

<33> PCH_ENBKL
<33> PCH_ENVDD

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (4/9) LVDS,CRT,DP,HDMI

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

17

of

64

5

4

3

2

1

+3VS
RP2
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#

1
2
3
4

U4E

8.2K_0804_8P4R_5%
RP1
8
7
6
5

D

PCH_GPIO2
DGPU_PWR_EN_R
PCH_GPIO4
ODD_DA#_R

1
2
3
4

8.2K_0804_8P4R_5%

PPT EDS DOC#474146

@

PCH_GPIO51

R305

1

R297

1

2 8.2K_0402_5%
2 8.2K_0402_5%

DGPU_GC6_EN

R213

1

2 8.2K_0402_5%

PCH_GPIO5

R225

1

2 8.2K_0402_5%

PCH_WL_OFF#

@

USB30
PORT1

RIGHT USB (SUB/B)

PORT2
R212

1

2 8.2K_0402_5%

DGPU_PWR_EN1

R252

1

2 8.2K_0402_5%

DGPU_HOLD_RST#_R

PORT3

LEFT USB

R306

1

2 8.2K_0402_5%

DGPU_GC6_EN

PORT4

LEFT USB

R214

1

2 8.2K_0402_5%

DGPU_HOLD_RST#_R

@

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

B21
M20
AY16
BG46

TP21
TP22
TP23
TP24

RSVD1
RSVD2
RSVD3
RSVD4

RSVD

8
7
6
5

C

R215

1

@

USB30_RX_P3
USB30_RX_P4
USB30_TX_N1

<45> USB30_RX_P3
<45> USB30_RX_P4
<46> USB30_TX_N1

A16 swap overide Strap/Top-Block
Swap Override jumper

USB30_TX_N3
USB30_TX_N4
USB30_TX_P1

<45> USB30_TX_N3
<45> USB30_TX_N4
<46> USB30_TX_P1

Low=A16 swap
override/Top-Block
PCI_GNT3# Swap Override enabled
High=Default *

DGPU_PWR_EN_R
1
R319

USB30_RX_N3
USB30_RX_N4
USB30_RX_P1

<45> USB30_RX_N3
<45> USB30_RX_N4
<46> USB30_RX_P1

2 1K_0402_5%

USB30_TX_P3
USB30_TX_P4

<45> USB30_TX_P3
<45> USB30_TX_P4

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

2 NVDD_PWR_EN
0_0402_5%
@

7/9 Reserve

<23> DGPU_HOLD_RST#
<56> NVDD_PWR_EN
<23,48> DGPU_PWR_EN
<27> DGPU_GC6_EN
<36> PCH_WL_OFF#

GPIO53=This Signal has a weak internal pull-up.
NOTE: The internal pull-up is disabled after
<40,42>
PLTRST# deasserts.

ODD_DA#

0_0402_5%
DGPU_HOLD_RST#_R C46
1
2
DGPU_PWR_EN1
C44
1
2
DGPU_PWR_EN_R E40
R318 0_0402_5%
R315
1
2
PCH_GPIO51
0_0402_5%
D47
DGPU_GC6_EN
E42
PCH_WL_OFF#
F46
R314

ODD_DA#
0_0402_5%

1
R715

2

@

<42>

B

PCH_GPIO51

R221

1

@

PCH_GPIO2
ODD_DA#_R
PCH_GPIO4
PCH_GPIO5

PCI_PME#

22_0402_5% 1
22_0402_5% 1
22_0402_5% 2

PCH_PLTRST#
2 R219
2 R220
1 R173

@

2 1K_0402_5%

G42
G40
C42
D44
K10

<6> PCH_PLTRST#
<15> CLK_PCI_LPBACK
<42> CLK_PCI_EC
<36> CLK_PCI_DB

K40
K38
H38
G38

C6

CLK_PCI_LPBACK_R H49
CLK_PCI_EC_R
H43
CLK_PCI_DB_R
J48
K42
H40

USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3Tp1
USB3Tp2
USB3Tp3
USB3Tp4

PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

AT10
BC8

RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

RSVD23
RSVD24

AV5
AV10

D

AT8

RSVD26
RSVD27

AY5
BA2

RSVD28
RSVD29

AT12
BF3

USB DEBUG=PORT1 AND PORT9
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USB

PCH_WL_OFF#

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

PCI

USB30_RX_N1

<46> USB30_RX_N1

RSVD5
RSVD6

RSVD25

@

AY7
AV7
AU3
BG4

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

USBRBIAS#
USBRBIAS

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33

USB20_N0
USB20_P0

USB20_N0 <46>
USB20_P0 <46>

RIGHT USB (SUB/B)
C

USB20_N2
USB20_P2
USB20_N3
USB20_P3

USB20_N2
USB20_P2
USB20_N3
USB20_P3

USB20_N5
USB20_P5

<45>
<45>
<45>
<45>

USB20_N5 <33>
USB20_P5 <33>

LEFT USB
LEFT USB
USB Camera

Some PCH config not support USB port 6 & 7.
USB20_N9
USB20_P9
USB20_N10
USB20_P10

USB20_N9 <46>
USB20_P9 <46>
USB20_N10 <36>
USB20_P10 <36>

USB20_N13
USB20_P13
USBRBIAS

USB20_N13 <44>
USB20_P13 <44>

+3V_PCH

RIGHT USB (Cable)
RP3

WLAN

USB_OC5#
USB_OC2#
USB_OC7#
USB_OC0#

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

10K_1206_8P4R_5%

Bluetooth

1
R218

2
22.6_0402_1%

RP4
USB_OC6#
USB_OC1#
USB_OC4#
USB_OC3#

B33

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

A14
K20
B17
C16
L16
A16
D14
C14

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

5
6
7
8

Within 500 mils

PME#
PLTRST#

4
3
2
1

4
3
2
1

USB_OC0# <46>
USB_OC1# <45>

5
6
7
8

B

10K_1206_8P4R_5%

USB_OC4# <46>

PANTHER-POINT_FCBGA989

Boot BIOS Strap bit1 BBS1
Boot BIOS
Bit11 Bit10 Destination

1

1

0

0

*

SPI

MC74VHC1G08DFT2G SC70 5P
@
3

Reserved
(Default)

4

<23,36,37,42,46> PLT_RST#

LPC

A

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

B

U7

PCH_PLTRST#

1
2

R223
100K_0402_5%

2

Compal Secret Data

Security Classification
Issued Date

1

A

Y

Title

A

+3VS

2

@
C208
1U_0402_6.3V6K

G

Reserved

0

P

1

1

2
0_0402_5%

5

0

1

GNT1#/
GPIO51

1
R222

Compal Electronics, Inc.
PCH (5/9) PCI, USB

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

18

of

64

2

X

Reserve

0

1

X

X

DIS

1

0

X

X

UMA

1

1

X

X

14"

X

X

0

0

R711

R708

1

@
PCH_GPIO38

R704

@

R703

@

2

X

@
1

0

10K_0402_5%

0

+3VS

2

PCH_GPIO69

1

PCH_GPIO70

10K_0402_5%

SG

PCH_GPIO67

2

PCH_GPIO38

2

Function

1

MB ID

1

3

10K_0402_5%

4

10K_0402_5%

5

PCH_GPIO67

<15> PCH_GPIO67

D

D

PCH_GPIO69

R235

1

EC_SMI#
BMBUSY# / GPIO0

TACH4 / GPIO68

C40

PCH_GPIO68

TACH1 / GPIO1

TACH5 / GPIO69

B41

PCH_GPIO69

TACH2 / GPIO6

TACH6 / GPIO70

C41

PCH_GPIO70

E38

TACH3 / GPIO7

TACH7 / GPIO71

C10

GPIO8

T7
R227

1

2 10K_0402_5%

PCH_GPIO1

A42

R228

1

2 10K_0402_5%

PCH_GPIO6

H36

EC_SCI#
EC_SMI#

<42> EC_SCI#

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

*

voltage regulator enable
烉烉On-Die
On-Die PLL Voltage Regulator disable
R240

1

R229

1

R230

1

@

R236
10K_0402_5%

2 10K_0402_5%

PCH_GPIO12

C4

LAN_PHY_PWR_CTRL / GPIO12

2 10K_0402_5%

EC_LID_OUT#

G2

GPIO15

A20GATE

<42> EC_LID_OUT#

2 1K_0402_5% PCH_GPIO28

@

<42> EC_SMI#
+3V_PCH

R231
R232

+3VS

2 10K_0402_5%
2 10K_0402_1%

1
1

PCH_GPIO16

U2

PECI
SATA4GP / GPIO16
RCIN#

+3VS

PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
Low: VCCVRM VR Disable

<36> BT_DISABLE
AOAC@
0_0402_5% 2

<16,36,37> PCIE_WAKE#

+3V_PCH

R241 1

+3VS

1

<36,44> PCH_BT_ON#
+3V_DSW

<40> ODD_EN

DGPU_PWROK_R
BT_DISABLE
ODD_EN

D40
T5

1

E8

GPIO24
GPIO27

AOAC_WAKE#

2 10K_0402_5%

PCH_GPIO28

P8

2 10K_0402_5%

PCH_BT_ON#

K1

2 10K_0402_5%

PCH_GPIO35

K4

PCH_GPIO36

V8

PCH_GPIO37

M5

AOAC@
R207

2

R245

1

1 10K_0402_5%
@

2 10K_0402_5%

+3VS

+3VS
+3V_PCH
+3VS

R250

1

2 200_0402_5%

R264

1

2 10K_0402_5%

B

PCH_GPIO38

N2

R247

1

2 10K_0402_5%

PCH_GPIO39

M3

R248

1

2 10K_0402_5%

PCH_GPIO48

V13

R249

1

2 10K_0402_5%

PCH_GPIO49

V3

2 10K_0402_5%

PCH_GPIO57

D6

AOAC_WAKE#

R251

1

A4
A44

A46

R259

1
1

@

2 10K_0402_5%

PROCPWRGD
THRMTRIP#

PCH_GPIO37

A5

2 10K_0402_5%

A6
B3
B47
BD1
BD49
BE1
BE49
BF1
BF49

P4

GATEA20 <42>

AU16

PCH_PECI_R

P5

KBRST#

@
1
2
0_0402_5% R237

AY11
AY10

H_PECI

<6,42>

KBRST#

<42>
C

H_CPUPWRGD <6>
PCH_THRMTRIP#_R 1
R239

H_THRMTRIP#
2
390_0402_5%

H_THRMTRIP# <6>

INIT3_3V#

T14

DF_TVS

AY1

TS_VSS1

AH8

INIT3_3V

AK11

This signal has weak internal
PU, can't pull low

STP_PCI# / GPIO34
TS_VSS2
GPIO35
TS_VSS3
SATA2GP / GPIO36
TS_VSS4

PCH_THRMTRIP#_R <23>

NV_CLE

AH10

+3VS
PCH_GPIO68 R255

1

2 10K_0402_5%

KBRST#

1

2 10K_0402_5%

R226

AK10

SATA3GP / GPIO37
SLOAD / GPIO38

NC_1

P37

Intel schematic reviwe recommand.

SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48

VSS_NCTF_15

SATA5GP / GPIO49 / TEMP_ALERT#

VSS_NCTF_16

GPIO57

VSS_NCTF_17
VSS_NCTF_18

A45

R244

GPIO28

PCH_GPIO36

@

+3VS

SCLOCK / GPIO22

E16

1 R224

R242
R243

TACH0 / GPIO17

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_4
VSS_NCTF_5

NCTF

*

2
R339
2 10K_0402_5%

CPU/MISC

1
0_0402_5%
R238
1

<27,53,56> DGPU_PWROK

GPIO

@
C

9/18 Reseve for SKU ID +3VS

A40

1

+3VS

H
L

2

1

1

X

2

X

U4F
2 1K_0402_5%

1

R705

10K_0402_5%

2 10K_0402_5%

1

@

1

R233

+3VS

2 10K_0402_5%

1

R706

2

R280

+3V_PCH

R709

1

Reserve

R712

10K_0402_5%

0

2

1

1

1

0

X

10K_0402_5%

X

X

2

X

GC6_EVENT#

<23> GC6_EVENT#

10K_0402_5%

14"L
15"

PCH_GPIO70

VSS_NCTF_22
VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

BG2
BG48
BH3
BH47
BJ4
B

H : Sandy Bridge

BJ44

PROC_SEL
L : INV Bridge

BJ45
BJ46

+1.8VS

BJ5
BJ6
R216
2.2K_0402_5%

C2
C48

NV_CLE

1
R217

D1

2
1K_0402_5%

H_SNB_IVB# <6>

CLOSE TO THE BRANCHING POINT

D49
E1
E49
F1
F49

PANTHER-POINT_FCBGA989

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (6/9) GPIO, CPU, MISC

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

19

of

64

5

4

3

+1.05VS

POWER

U4G
@ J2

2

1700mA

2

2

+1.05VS

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

63mA

VSSADAC

1mA

This pin can be left as no connect in
On-Die VR enabled mode (default).

VCCIO[15]
VCCIO[16]

AN27

+1.05VS_VCC_EXP
+1.05VS

AP21

C

+1.05VS_VCC_EXP

2

1

2

1

2

C225
1U_0402_6.3V6K

2

1

AP23
C224
1U_0402_6.3V6K

11/07 Change type to 0603

1

C223
1U_0402_6.3V6K

2

C221
10U_0603_6.3V6M

1

C222
1U_0402_6.3V6K

R296 2
1
0_0805_5%

+3VS_VCCA3GBG

1 R260
2
0_0603_5%

1

PAD

+1.05VS

+VCCAFDI_VRM
T48 @
R263 2
1
0_0603_5%

AP16

+1.05VS_VCCAPLL_FDI

BG6

+1.05VS_VCCDPLL_FDI

AP17
AU20

+VCCP_VCCDMI
B

VCC3_3[7]

+VCCTX_LVDS
1

1

0.001

D

AP37

2

C216
0.01U_0402_16V7K

2

C217
0.01U_0402_16V7K

2

V33

+3VS_VCC3_3_6

5

0.001

Vcc3_3

3.3

0.228

VccADAC

3.3

0.063

VccADPLLA

1.05

0.08

VccADPLLB

1.05

0.08

VccCore

1.05

1.7

VccDMI

1.05

0.047

VccIO

1.05

3.711

VccASW

1.05

0.903

VccSPI

3.3

0.01

VccDSW

3.3

0.001

VccDFTERM

1.8

0.002

VccRTC

3.3

6 uA

3.3

0.095

0.1uH inductor, 200mA

1

AP36

V34
2

3711mA

VCCVRM[3]

C218
22U_0805_6.3V6M

2 R256
1
0_0603_5%
C219
0.1U_0402_10V7K

AT16

+VCCAFDI_VRM
+VCCP_VCCDMI

VCCIO[21]

VCCDMI[1]

VCCIO[24]

AT20

+1.05VS

+VCCP_VCCDMI
1

+1.05VS

70mA

VCCCLKDMI

AB36 +1.05VS_VCC_DMI_CCI

2 R300
1
0_0603_5%

1
C226
1U_0402_6.3V6K

2

C

2 R258
1
0_0603_5%
C220
1U_0402_6.3V6K

2

VCCIO[25]
VCCIO[26]

VCCDFTERM[1]

190mA VCCDFTERM[2]

VCC3_3[3]

C227
0.1U_0402_10V7K

2

0.001

5

V5REF_Sus

+1.8VS
L2
0.1UH_MLF1608DR10KT_10%_1608
2
1

VCCIO[20]

VCCIO[23]

BH29

1.05

V5REF

1

VCCIO[19]

VCCIO[22]

AN34

+3VS

AM38

VCC3_3[6]

S0 Iccmax
Current (A)

VCCIO[18]

AP26

AN33

V_PROC_IO

Voltage

type to 0603

+3VS

VCCIO[17]

AP24

AT24

Voltage Rail

2 R295
1
0_0603_5%

VCCAPLLEXP

AN17

AN26

+VCCA_LVDS

PCH Power Rail Table
Refer to CPU EDS R1.5

AK37

VCCTX_LVDS[2]
VCCTX_LVDS[3]

C213
0.01U_0402_16V7K

+3VS
L1
BLM18PG181SN1_0603~D
2
1
1
1
1
C395 @
10U_0603_6.3V6M
C214
C215
0.1U_0402_10V7K
10U_0603_6.3V6M
2
2
2
+3VS
11/07 Change

VCCIO[28]

AN16

AN21

AK36

AM37

HVCMOS

BJ22

DMI

AN19

+VCCAPLLEXP

T47 @

DFT / SPI

+1.05VS_VCCDPLLEXP

0_0603_5%

PAD

1
U47

VCCTX_LVDS[1]

VCCTX_LVDS[4]

VCCIO

1

VCCALVDS
VSSALVDS

VCCVRM[2]
VccAFDIPLL

VCCDFTERM[3]

VccSus3_3

AG16
+VCCPNAND

AG17

2 R293
1
0_0603_5%

AJ16
1

VCCDFTERM[4]

+1.8VS

AJ17

C228
0.1U_0402_10V7K

2

+3VS

VccSusHDA

3.3 / 1.5

0.01

VccVRM

1.8 / 1.5

0.167

VccCLKDMI

1.05

0.07

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.055

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.04

R399

VCCIO[27]
VCCDMI[2]

FDI

2

+VCCADAC

U48

2

40mA
R254

VCCADAC

CRT

1

C212
1U_0402_6.3V6K

1

C211
1U_0402_6.3V6K

2

C210
1U_0402_6.3V6K

2

D

1

C209
10U_0603_6.3V6M

1

PAD-OPEN 4x4m

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

LVDS

+1.05VS_VCCCORE

1

VCC CORE

2

1

10mA

VCCSPI

V1

+3V_VCCPSPI

2
1
0_0603_5%

1

PANTHER-POINT_FCBGA989

2

C230
1U_0402_6.3V6K

B

+VCCAFDI_VRM
+1.5VS
R265

2

1

0_0603_5%

+VCCAFDI_VRM

Intel recommand
stuff R265 and unstuff R266

VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP

VCCVRM = 160mA detal waiting for newest spec

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (7/9) PWR

Size Document Number
Custom

Rev
1.0

QIWY3 LA-8001P

Date:

Monday, January 16, 2012

Sheet
1

20

of

64

5

4

3

2

1

Have internal VRM

R269
0_0603_5%
2
1

V12

+3VS_VCC_CLKF33

T38

T15

PAD

2 R271
1
0_0603_5%

+1.05VS

+VCCAPLL_CPY_PCH

BH23

+VCCDPLL_CPY

AL29

+VCCSUS1

AL24

1

2

@ C239
1U_0402_6.3V6K

AA19

+1.05VS

2

+1.05VS

1

2

1

+1.05VS_VCCA_B_DPL

2

2

R307
0_0603_5%

1

2

1

2

VCCASW[5]
VCCASW[6]

1

2

1
+
2

1

2

C253
1U_0402_6.3V6K

2

@

C252
220U_B2_2.5VM_R35

2

1

C237
22U_0805_6.3V6M

+

C251
1U_0402_6.3V6K

2

1

C250
220U_B2_2.5VM_R35

C229
22U_0805_6.3V6M

1

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

W23
W24
W26
W29
W31
W33

V24

VCCSUS3_3[6]

P24

VCCIO[34]

VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]

+VCCRTCEXT

N16

1
Y49

T26

2

2 R272
1
0_0603_5%

+3V_PCH
+5V_PCH

+3V_VCCAUBG
1

2

2 R273
1
0_0603_5%

C238
0.1U_0402_10V7K

+1.05VS_VCCAUPLL
+PCH_V5REF_SUS

DCPSUS[4]

AN23

+VCCA_USBSUS

VCCSUS3_3[1]

AN24

+3V_VCCPSUS

P34

+PCH_V5REF_RUN

N20

+3V_VCCPSUS

+3V_PCH

D1
CH751H-40PT_SOD323-2

R275
100_0402_5%

+1.05VS

2 R276
1
0_0603_5%

+PCH_V5REF_SUS

1
C240
0.1U_0402_25V6

2
C243 @1

2 1U_0402_6.3V6K

+5VS

1mA V5REF
VCCSUS3_3[2]
VCCSUS3_3[3]

N22

VCCSUS3_3[4]

P20

VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]

VCCASW[16]

VCC3_3[4]

+3V_PCH

2

1
AA16

+3VS_VCCPCORE

T34

2

VCCASW[20]
DCPRTC
VCCVRM[4]

VCCIO[13]

+VCC3_3_2
1

2 R283
1
0_0603_5%

2

2 R282
1
0_0603_5%

1

AH13
2

+1.05VS_SATA3

+1.05VS
2 R285
1
0_0603_5%

AF13

AH14

C248
1U_0603_10V6K

C254
0.1U_0402_10V7K

+1.05VS_SATA3

C255
2 0.1U_0402_10V7K

+PCH_V5REF_RUN

1

+3VS

+3VS_VCCPPCI

+3VS
VCC3_3[2]

+3VS

C249
0.1U_0402_10V7K

1

AJ2

C

D2
CH751H-40PT_SOD323-2

2 R281
1
0_0603_5%

2

W16

+3VS

R279
100_0402_5%

C247
1U_0402_6.3V

P22

VCCASW[18]
VCCASW[19]

2 R278
1
0_0603_5%

1

VCCASW[17]

VCCIO[12]
+VCCAFDI_VRM

1

M26

VCCIO[5]

C258
0.1U_0402_10V7K

+3V_PCH
+3V_VCCPUSB

V23

VCCSUS3_3[10]

1mA V5REF_SUS

VCCASW[7]

AC26

W21

T24

VCCSUS3_3[9]

903mA

VCCASW[4]

AA29

@

VCCSUS3_3[8]

VCCASW[1]

AA27

10UH_LB2012T100MR_20%
@

DCPSUS[3]

VCCASW[3]

AD29

D

T29
T23

VCCIO[14]

AA24

AA31

C233
1U_0402_6.3V6K

2

T27

228mA VCCSUS3_3[7]
VCCAPLLDMI2

VCCASW[2]

AD31
L6

VCCIO[33]

P28

VCC3_3[5]

AA21

AA26

C246
1U_0402_6.3V6K

1
+1.05VS_VCCA_A_DPL

2

2

C245
1U_0402_6.3V6K

10UH_LB2012T100MR_20%

C244
1U_0402_6.3V6K

L5
1

+1.05VM_VCCASW
1
C242
22U_0805_6.3V6M

1

C241
22U_0805_6.3V6M

1 R277
2
0_0805_5%

VCCIO[32]

P26

C236
0.1U_0402_10V7K

烉On-Die PLL voltage regulator enable

On-Die PLL Voltage Regulator

DCPSUSBYP

2 R270
1
0_0603_5%

1

+PCH_VCCDSW

USB

1

+1.05VS_VCCUSBCORE
1

2

VCCIO[31]

C235 @
0.1U_0402_10V7K

C

VCCIO[30]

1mA

VCCDSW3_3

N26

2

T16

VCCIO[29]

1

C234
0.1U_0402_10V7K

2
2

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

+1.05VS

VCCACLK

1

AD49

11/07 Change type to 0603

H

POWER

U4J
+VCCPDSW
1

2

For Deep S3

VCCDMI = 42mA detal waiting for newest spec

PCI/GPIO/LPC

10UH_LBR2012T100M_20%

2

+3V_DSW
C232
1U_0402_6.3V6K

2

@
D

+3VS_VCC_CLKF33
1

C231
10U_0603_6.3V6M

1

L3

VCC3_3 = 266mA detal waiting for newest spec
+VCCACLK

Clock and Miscellaneous

L3
0_0805_5%
1
2

R268 @
0_0603_5%
2
1

1

+1.05VS

2

+3VS

C257
1U_0402_6.3V6K

2
B

C256
1U_0402_6.3V6K

+1.05VS_VCCDIFFCLKN

2

+1.05VS_VCCDIFFCLKN
1

2

+1.05VS

2 R284
1
0_0603_5%

+1.05VS_SSCVCC

C259
1U_0402_6.3V6K

C263
0.1U_0402_10V7K
C262
1U_0402_6.3V6K

+1.05VM_VCCSUS

+VCCSST

V16

+1.05VM_VCCSUS

T17
V19

2

+V_CPU_IO

2

1

2

1

2

VCCSSC

VCCIO[2]

VCCIO[4]

95mA

+VCCSATAPLL

AK1

PAD

H
+VCCAFDI_VRM
+VCCAFDI_VRM
+1.05VS_VCC_SATA

AC16

+1.05VS_VCC_SATA

烉On-Die PLL voltage regulator enable

On-Die PLL Voltage Regulator

T16

AF11

+1.05VS

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

2 R288
1
0_0603_5%

AC17

1

AD17

C261
1U_0402_6.3V6K

+1.05VS

DCPSST
DCPSUS[1]
DCPSUS[2]

BJ8

V_PROC_IO 1mA

+RTCVCC
A22

2

1

2

1

2

C270
0.1U_0402_10V7K

1

C269
0.1U_0402_10V7K

@

C268
1U_0402_6.3V6K

C267
0.1U_0402_10V7K

1

C266
0.1U_0402_10V7K

C264 @
1U_0402_6.3V6K

AG33

1

2 R286
1
0_0603_5%

2

VCCVRM[1]

VCCIO[7]
VCCDIFFCLKN[1]
55mA
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

VCCASW[22]

+1.05VS

1

A

80mA

B

AF14

2

C265
4.7U_0603_6.3V6K

@ R290
0_0603_5%
2
1

VCCADPLLB

VCCIO[3]

1

2

+1.05VS

AF17
AF33
AF34
AG34

VCCAPLLSATA

VCCRTC

MISC

2 R304
1
0_0603_5%

BF47

+VCCDIFFCLK

80mA

VCCASW[23]
VCCASW[21]

T21
V21
T19
+3V_PCH

HDA

+1.05VS

+1.05VS_VCCA_B_DPL

VCCIO[6]
VCCADPLLA

CPU

1

BD47

SATA

+1.05VS_VCCA_A_DPL

2 R274
1
0_0603_5%

RTC

+1.05VS

10mA VCCSUSHDA

P32

+VCCSUSHDA
1

PANTHER-POINT_FCBGA989

@

2 R287
1
0_0603_5%

C271
0.1U_0402_16V4Z

A

2

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (8/9) PWR

Size Document Number
Custom

Rev
1.0

QIWY3 LA-8001P

Date:

Monday, January 16, 2012

Sheet
1

21

of

64

5

4

3

2

1

U4I

D

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

U4H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

C

B

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

PANTHER-POINT_FCBGA989

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

D

C

B

A

A

PANTHER-POINT_FCBGA989

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PCH (9/9) VSS

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

22

of

64

5

4

3

2

1

12/23 Change to +VDD33MISC for GTGE shutdown issue
UV1A

VGA_SMB_CK2

4

EC_SMB_CK2 <15,39,42>

2

2N7002DW-T/R7_SOT363-6
1
2
RV126
0_0402_5%
GTGE@
C

GL@
QV1A
1

VGA_SMB_DA2

6

EC_SMB_DA2 <15,39,42>

2N7002DW-T/R7_SOT363-6
1
2
RV137
0_0402_5%
GTGE@

PU AT EC SIDE, +3VS AND 4.7K

+3VS_VGA

OPT@

B

UV2

1

1

0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K

PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3
PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N4
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5
PCIE_CRX_C_GTX_P6
PCIE_CRX_C_GTX_N6
PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7
PCIE_CRX_C_GTX_P8
PCIE_CRX_C_GTX_N8
PCIE_CRX_C_GTX_P9
PCIE_CRX_C_GTX_N9
PCIE_CRX_C_GTX_P10
PCIE_CRX_C_GTX_N10
PCIE_CRX_C_GTX_P11
PCIE_CRX_C_GTX_N11
PCIE_CRX_C_GTX_P12
PCIE_CRX_C_GTX_N12
PCIE_CRX_C_GTX_P13
PCIE_CRX_C_GTX_N13
PCIE_CRX_C_GTX_P14
PCIE_CRX_C_GTX_N14
PCIE_CRX_C_GTX_P15
PCIE_CRX_C_GTX_N15

AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25

PLT_RST_VGA#

4

Y
A

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

AJ11

1

2

OPT@1
OPT@
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1
OPT@
OPT@1

3

<18> DGPU_HOLD_RST#

CV6
CV7
CV8
CV9
CV10
CV11
CV12
CV13
CV15
CV17
CV19
CV14
CV16
CV18
CV20
CV22
CV24
CV26
CV21
CV23
CV25
CV27
CV29
CV31
CV33
CV28
CV30
CV32
CV36
CV41
CV34
CV35

G

PLT_RST#
DGPU_HOLD_RST#

<18,36,37,42,46> PLT_RST#

@
RV105
10K_0402_5%

P

5

2

+3VS_VGA

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15

RV18
10K_0402_5%
2

NC7SZ08P5X_NL_SC70-5

<15> CLK_PCIE_VGA
<15> CLK_PCIE_VGA#

CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_REQ_GPU#

AL13
AK13
AK12

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#

AJ26
AK26

PLT_RST_VGA#

AJ12
AP29

OPT@

Differential signal

B

@
1
2
RV20
200_0402_1%

PEX_TERMP
1
2
RV22 OPT@ 2.49K_0402_1%

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

2

5
6

GC6_EVENT# <19>

QV7A
DMN66D0LDW-7 2N_SOT363-6
OPT@

VGA_AC_DET_R
1
RV223
10K_0402_5%
OPT@

GPU_VID5 <56>

2

2

DPRSLPVR_VGA <56>

OVERT#

1

GPU_VID5

D

4

MEM_VREF <28,29,30,31>
GPU_VID0 <56>

3

1

2
1
2
RV153 GC6@ 0_0402_5%

GPU_VID0

DACA_RED
DACA_GREEN
DACA_BLUE

+VDD33MISC

VGA_EDID_CLK

AK9
AL10
AL9

1
RV3

VGA_EDID_DATA

For N13P-GT/N13E-GE

AM9
AN9

VGA_CRT_CLK

12/23 Reserve for GTGE leakage issue

AG10
AP9
AP8

+3VS +VDD33MISC

+DACA_VDD 1 OPT@ 2
RV51
10K_0402_5%

I2CB_SDA
RV14
10K_0402_5%
@
VGA_AC_DET_R

I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA

R4
R5
R7
R6

SP_PLLVDD
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
PEX_RST_N
PEX_TERMP

VID_PLLVDD
XTAL_IN
XTAL_OUT
XTAL_OUTBUFF
XTAL_SSIN

OPT@
OPT@
OPT@

C

1
2
RV49
10K_0402_5%
NOGC6@

VGA_AC_DET <42,56>

OPT@

I2CB_SCL
I2CB_SDA

1
RV111

2
0_0402_5%
@

R2
R3
T4
T3

VGA_EDID_CLK
VGA_EDID_DATA
VGA_SMB_CK2
VGA_SMB_DA2

60mA
PLLVDD

PEX_WAKE_N

OPT@

2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%

1
2
RV1 OPT@ 10K_0402_5%

GC6_EVENT#_R

1VGA_AC_DET
DV3

2
RB751V_SOD323

VGA_CRT_CLK
VGA_CRT_DATA

OVERT#

RV2
10K_0402_5%
OPT@

OPT@

1
RV10
1
RV11
1
RV12
1
RV13

I2CB_SCL
DACA_VDD
DACA_VREF
DACA_RSET

OPT@
1

RV4
VGA_CRT_DATA

DACA_HSYNC
DACA_VSYNC

PCH_THRMTRIP#_R <19>

QV7B
DMN66D0LDW-7 2N_SOT363-6
OPT@

Vendor recommand reserve PU/PD resistor

AD8
AE8
AD7

45mA

+PLLVDD
1
RV112

@

2
0_0402_5%

45mA

+SP_PLLVDD

H3
H2

XTALIN
XTAL_OUT

J4
H1

XTALOUT
XTALSSIN 1
2
10K_0402_5% OPT@ RV26

B

RV27
10K_0402_5%
OPT@
2
N13P-PES-A1_FCBGA908

Internal Thermal Sensor

YV1
XTALIN1

RV65
10K_0402_5%

1

OVERT#
GC6_EVENT#_R

1
2
RV23 10M_0402_5%
OPT@

@

2

1

1

GL@
QV1B
3

GPU_VID1 <56>
GPU_VID2 <56>

PCH_THRMTRIP#_R
RV208
10K_0402_5%
OPT@

1

DIS@
5

GL@ RV24
2.2K_0402_5%

GL@
RV25
2.2K_0402_5%

GPU_VID1
GPU_VID2

2

2

2

+VDD33MISC

GPU_VID4 <56>
GPU_VID3 <56>

1

+VDD33MISC

GPU_VID4
GPU_VID3

P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1

1

OPT@

2

CV5

CV4

2

1

OPT@

1

0.1U_0402_10V7K

2

OPT@ CV113

2

1

0.1U_0402_10V7K

1

OPT@ CV112

180ohms (ESR=0.2) Bead

150mA
+SP_PLLVDD

4.7U_0402_6.3V6M

22U_0805_6.3V6M

+1.05VS_VGA

BLM18PG181SN1D_2P
2

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

GPIO

Under GPU(below 150mils)
LV1
1

+VDD33MISC

Part 1 of 7

DACs

PCIE_CRX_GTX_P[0..15]

<5> PCIE_CRX_GTX_P[0..15]

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

I2C

<5> PCIE_CRX_GTX_N[0..15]

AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27

PCI EXPRESS

PCIE_CRX_GTX_N[0..15]

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15

CLK

PCIE_CTX_GRX_P[0..15]

<5> PCIE_CTX_GRX_P[0..15]

D

+VDD33MISC

PCIE_CTX_GRX_N[0..15]

<5> PCIE_CTX_GRX_N[0..15]

2XTAL_OUT

UV1

GT@

27MHZ_16PF_X5H027000FG1H
CV37
CV38
OPT@
22P_0402_50V8J
22P_0402_50V8J
OPT@
OPT@

UV1

N13E-GE
GE@

9/20 For Crystal EA request

30 ohms @100MHz (ESR=0.05)
N13P-GL

OPT@
3

A

Under GPU

Near GPU

CLK_REQ_GPU#

Issued Date

1

2
0_0402_5%

Compal Secret Data

Security Classification

@ RV32
@RV32
10K_0402_5%
@

5

2

+1.05VS_VGA

2

2N7002H 1N_SOT23-3

1
RV110

2

2
0_0402_5%

S

QV2
1
D

<15> CLK_REQ_VGA#

1

1 2
G

RV30
10K_0402_5%
OPT@

1
LV7
1

OPT@CV40

2

2
RV29
10K_0402_5%
OPT@

A

1

22U_0805_6.3V6M

0.1U_0402_10V7K

+3VS_VGA

<18,48> DGPU_PWR_EN

OPT@ CV131

+PLLVDD

GL@

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Title

Compal Electronics, Inc.
N13P-PCIE/DAC/GPIO

Size

Document Number

Rev
1.0

QIWY3 LA-8001P
Date:

Monday, January 16, 2012
1

Sheet

23

of

64

5

4

3

2

1

UV1D
Part 4 of 7

B

AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5

IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5

IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1

IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N

P8
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32

D

VDD_SENSE

L4

VCCSENSE_VGA

VCCSENSE_VGA

GND_SENSE

L5

VSSSENSE_VGA

VSSSENSE_VGA <56>

<56>

trace width: 16mils
differential voltage sensing.
differential signal routing.

TEST
TESTMODE

AK11

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

AM10
AM11
AP12
AP11
AN11

TESTMODE

1
RV34

TV2
TV3
TV4
TV5

1

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

NC

AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

2
10K_0402_5%
OPT@

2

C

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

LVDS/TMDS

D

AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6

10K_0402_5%
RV33
OPT@

C

SERIAL
ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO

H6
H4
H5
H7

GENERAL

RV35

BUFRST_N

L2

CEC

L3

MULTI_STRAP_REF0_GND

J1

AG3
AG2

IFPC_AUX_I2CW _SCL
IFPC_AUX_I2CW _SDA_N

AK3
AK2

IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N

AB3
AB4

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N

AF3
AF2

IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N

ROM_CS
ROM_SCLK
ROM_SI
ROM_SO

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

J2
J7
J6
J5
J3

THERMDP
THERMDN

K3
K4

OPT@

2

ROM_SCLK <32>
ROM_SI
<32>
ROM_SO <32>

10K_0402_5%
1

1
2
RV56 GL@ 10K_0402_5%
1
2
RV38 OPT@ 40.2K_0402_1%
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

+3VS_VGA

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

<32>
<32>
<32>
<32>
<32>

B

Reserve 1MB SPI ROM FOR VBIOS ROM
+3VS_VGA

CV295

20mils

1
1

2
0.1U_0402_16V4Z
@

ROM_CS
ROM_SO

@
UV15

1
2
3
4

CS#
DO
W P#
GND

VCC
HOLD#
CLK
DIO

8
7
6
5

MX25L1005AMC-12G SOP
@

A

Compal Secret Data

Security Classification

2011/07/21

Issued Date

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

RV225
10K_0402_5%

2

RV229 @
10K_0402_5%
0_0402_5%
ROM_CS_R
2
ROM_SO_R
2
0_0402_5%

2

@ RV224
@RV224
1
1
@RV226
@
RV226

1

N13P-PES-A1_FCBGA908

ROM_HOLD#
@ RV228
ROM_SCLK_R 1
ROM_SI_R
1
@ RV227

0_0402_5%
ROM_SCLK
2
ROM_SI
2
0_0402_5%

A

Compal Electronics, Inc.
N13P-LVDS/HDMI/DP/THM

Size

Document Number

Rev
1.0

QIWY3 LA-8001P
Date:

Monday, January 16, 2012

Sheet
1

24

of

64

3

2

UV1E

1

CALIBRATION PIN

2
40.2_0402_1%

RV6

GDDR5

FB_GND_SENSE

J27

1

40.2Ohm

RV8

FB_CAL_x_PU_GND

40.2Ohm

RV9

2
40.2_0402_1%

H27

2
60.4_0402_1%

H25

+PEX_PLLVDD

IFPC_PLLVDD
IFPC_RSET
IFPC_IOVDD

FB_CAL_PD_VDDQ
IFPD_PLLVDD
IFPD_RSET

FB_CAL_PU_GND

IFPD_IOVDD
FB_CAL_TERM_GND

J8
K8
L8
M8

OPT@ CV52

OPT@ CV51

10U_0603_6.3V6M

OPT@ CV50

10U_0603_6.3V6M

OPT@ CV49

10U_0603_6.3V6M

10U_0603_6.3V6M

OPT@ CV48

2

1

2

1

2

2

2

1

CV105

CV72
0.1U_0402_10V7K

1

QV8

3
1

GTGE@
GL@

2
GTGE@

1
RV140

OPT@ CV73

1

OPT@ CV74

2
0_0402_5%

+PEX_SVDD3V3

AG12

2
0_0402_5%
+3VS

1
RV154

2
0_0402_5%

@

Under GPU(below 150mils)
Place near balls

10K_0402_5% RV52
1 OPT@
2
2
1
1K_0402_1%
RV40
@
AG8 +IFPAB_IOVDD
1 OPT@
2
10K_0402_5%
RV53
AG9

AH8 +IFPAB_PLLVDD
AJ8

1

2

+3VS_VGA

Place near GPU

0_0603_5%
2
1

+VDD33

1

2

1

2

1

2

OPT@ CV75

AG26

1
RV138

0.1U_0402_10V7K

OPT@ CV56

22U_0805_6.3V6M

OPT@ CV47

OPT@ CV46

OPT@ CV45

1U_0402_6.3V6K

1U_0402_6.3V6K

OPT@ CV43

1U_0402_6.3V6K

OPT@ CV44
OPT@ CV53

22U_0805_6.3V6M

OPT@ CV55

GTGE@

OPT@ CV293
4.7U_0603_6.3V6K

VDD33_0
VDD33_1
VDD33_2
VDD33_3

OPT@

1

+3VS_VGA

+VDD33MISC

OPT@

FB_CAL_x_PD_VDDQ

FB_CAL_xTERM_GND

FB_VDDQ_SENSE

AH12

D

+3VS_VGA
AO3413_SOT23
+VDD33MISC

4.7U_0603_6.3V6K

PEX_PLLVDD

IFPA_IOVDD
IFPB_IOVDD

F2

2

For N13P-GT/N13E-GE
+PEX_PLLHVDD

1

<48,53> DGPU_PWR_EN#

OPT@ CV70

PEX_SVDD_3V3

IFPAB_PLLVDD
IFPAB_RSET

F1

1

2

For N13P-GT/N13E-GE

OPT@ CV111

FB_VSS_SENSE
2
0_0402_5%

1

2

+1.05VS_VGA

1

4.7U_0603_6.3V6K

PEX_PLL_HVDD

FB_VDDQ_SENSE

+1.5VS_VGA

1

2

1U_0402_6.3V6K

OPT@ 1
RV142

2

2

OPT@ CV109
0.1U_0402_10V7K

2
0_0402_5%

2

1

2

0.1U_0402_10V7K

OPT@ 1
RV141

2

1

2

1

GTGE@

C

<53> VDDQ_SENSE

1

1

0.1U_0402_10V7K

2

2

Under GPU(below 150mils)
OPT@ CV54

1

OPT@ CV286

2

OPT@ CV285

1

0.1U_0402_10V7K

2

OPT@ CV284

1

0.1U_0402_10V7K

2

0.1U_0402_10V7K

1

OPT@ CV294

2

0.1U_0402_10V7K

1

OPT@ CV287

2

OPT@ CV292

1

0.1U_0402_10V7K

2

0.1U_0402_10V7K

1

OPT@ CV280

2

1U_0402_6.3V6K

1

OPT@ CV279

OPT@ CV278

2

1U_0402_6.3V6K

OPT@ CV282

1U_0402_6.3V6K

OPT@ CV281

OPT@ CV277

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

2

1

D

2

1

2

1

S

2

1

2

1

G

1

1U_0402_6.3V6K

Under GPU(below 150mils)

+1.5VS_VGA

AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28

1

22U_0805_6.3V6M

CV276

D

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13

+1.05VS_VGA

AG19
AG21
AG22
AG24
AH21
AH25

1U_0402_6.3V6K

2

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

22U_0805_6.3V6M

2

1

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43

POWER

2

1

OPT@

2

1

OPT@ CV275
22U_0805_6.3V6M

1

1

OPT@ CV274
22U_0805_6.3V6M

1

2

OPT@ CV273
22U_0805_6.3V6M

1

2

OPT@ CV272
22U_0805_6.3V6M

1

2

AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27

Near GPU

2000mA

Part 5 of 7

3.5A

OPT@ CV271
10U_0603_6.3V6M

2

2

OPT@ CV269
10U_0603_6.3V6M

2

1

OPT@ CV268
10U_0603_6.3V6M

2

1

Near GPU

OPT@ CV267
4.7U_0603_6.3V6K

2

1

OPT@ CV266
4.7U_0603_6.3V6K

2

1

OPT@ CV265
4.7U_0603_6.3V6K

2

1

OPT@ CV264
4.7U_0603_6.3V6K

1

OPT@ CV263
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

For GDDR5 setting.

OPT@ CV270
10U_0603_6.3V6M

+1.5VS_VGA

1

4.7U_0603_6.3V6K

4

4.7U_0603_6.3V6K

5

RV5 OPT@
C

AF7 +IFPC_PLLVDD
1 OPT@
2
10K_0402_5%
RV42 2
AF8
1
1K_0402_1%
RV43
@
AF6 +IFPC_IOVDD
1 OPT@
2
10K_0402_5%
RV44
AG7 +IFPD_PLLVDD
1 OPT@
2
10K_0402_5%
RV45 2
AN2
1
1K_0402_1%
RV46
@
AG6 +IFPD_IOVDD
1 OPT@
2
10K_0402_5%
RV47
LV2

OPT@

IFPEF_PLVDD
IFPEF_RSET

60.4Ohm

IFPE_IOVDD
IFPF_IOVDD

Place near balls

AB8 +IFPEF_PLLVDD
1 OPT@
2
10K_0402_5%
RV55 2
AD6
1K_0402_1%
AC7 +IFPE_IOVDD
1 OPT@
2
10K_0402_5%
RV54
AC8

1
RV50
@
GTGE@

0_0603_5%
+1.05VS_VGA
GL@
2

1

2

OPT@ CV66

CV3

2

OPT@

2

1

4.7U_0805_25V6-K

B

1

OPT@ CV65

0.1U_0402_10V7K

+PEX_PLLVDD
N13P-PES-A1_FCBGA908

1U_0603_10V6K

120mA

LV2

1

BLM18PG121SN1D_0603

120ohms @100MHz (ESR=0.18)
B

Place near balls

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
N13P-POWER

Size

Document Number

Rev
1.0

QIWY3 LA-8001P
Date:

Monday, January 16, 2012

Sheet
1

25

of

64

5

4

3

2

1

UV1F

+VGA_CORE

UV1G
+VGA_CORE

C

AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
U15
U17
U18
U20
U22
V13
V15

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55

POWER

Part 7 of 7
D

B

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38

V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22
U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8

N13P-PES-A1_FCBGA908

A

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99

GND

Part 6 of 7

A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7

N13P-PES-A1_FCBGA908
Title

D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32

GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT

D

C

B

A

Compal Electronics, Inc.
N13P-VGA CORE, GND

Size

Document Number

Rev
1.0

QIWY3 LA-8001P
Date:

Monday, January 16, 2012

Sheet
1

26

of

64

5

4

30ohms (ESR=0.01) Bead
P/N;SM010007W00

1

FBC_D[0..63]

PU for X16 mode

UV1B

PU for X16 mode
UV1C

FB_CLAMP

FB_DLL_AVDD

K31
L30
H34
J34
AG30
AG31
AJ34
AK34

FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#

FBA_WCK0
FBA_WCK0_N
FBA_WCK1
FBA_WCK1_N
FBA_WCK2
FBA_WCK2_N
FBA_WCK3
FBA_WCK3_N

FBA_WCK0 <28>
FBA_WCK0_N <28>
FBA_WCK1 <28>
FBA_WCK1_N <28>
FBA_WCK2 <29>
FBA_WCK2_N <29>
FBA_WCK3 <29>
FBA_WCK3_N <29>

J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33

<30>
<30>
<30>
<30>
<31>
<31>
<31>
<31>

FB_CLAMP

E1

K27

RV66 NOGC6@ 10K_0402_5%
2
1
+FB_PLLAVDD
CV106
1

FBC_DBI0#
FBC_DBI1#
FBC_DBI2#
FBC_DBI3#
FBC_DBI4#
FBC_DBI5#
FBC_DBI6#
FBC_DBI7#

0.1U_0402_10V7K
2
OPT@

Place close to ball
FBA_PLL_AVDD

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FB_VREF

U27

H26

1

2

Place close to ball

1

2

+FB_PLLAVDD
1

2

<30> FBC_EDC[3..0]
<31> FBC_EDC[7..4]

Place close to BGA

D10
D5
C3
B9
E23
E28
B30
A23
D9
E4
B2
A9
D22
D28
A30
B23

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7

FBC_CS#_L <30>
FBC_MA3_BA3_L <30>
FBC_MA2_BA0_L <30>
FBC_MA4_BA2_L <30>
FBC_MA5_BA1_L <30> +1.5VS_VGA
FBC_WE#_L <30>
FBC_MA7_MA8_L <30>
FBC_MA6_MA11_L <30>
FBC_ABI#_L <30>
RV210
FBC_MA12_RFU_L <30>
10K_0402_5%
FBC_MA0_MA10_L <30>
OPT@
FBC_MA1_MA9_L <30>
FBC_RAS#_L <30>
FBC_RST#_L <30>
FBC_CKE_L <30>
FBC_CAS#_L <30>
FBC_CS#_H <31>
FBC_MA3_BA3_H <31>
FBC_MA2_BA0_H <31>
FBC_MA4_BA2_H <31>
FBC_MA5_BA1_H <31>+1.5VS_VGA
FBC_WE#_H <31>
FBC_MA7_MA8_H <31>
FBC_MA6_MA11_H <31>
FBC_ABI#_H <31>
RV222
FBC_MA12_RFU_H <31>
10K_0402_5%
FBC_MA0_MA10_H <31>
OPT@
FBC_MA1_MA9_H <31>
FBC_RAS#_H <31>
FBC_RST#_H <31>
FBC_CKE_H <31>
FBC_CAS#_H <31>

GDDR5
Mode H - Mirror Mode Mapping

C12
C20
@

FBB_DEBUG0
FBB_DEBUG1

FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N

FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N

FBB_WCKB01
FBB_WCKB01_N
FBB_WCKB23
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N

FBB_PLL_AVDD

FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7

1
G14 60.4_0402_1%
1
G20 60.4_0402_1%

D12
E12
E20
F20

2RV60
2RV61
@

FBC_CLK0
FBC_CLK0#
FBC_CLK1
FBC_CLK1#

+1.5VS_VGA

FBC_CLK0 <30>
FBC_CLK0# <30>
FBC_CLK1 <31>
FBC_CLK1# <31>

FBC_WCK0
FBC_WCK0_N
FBC_WCK1
FBC_WCK1_N
FBC_WCK2
FBC_WCK2_N
FBC_WCK3
FBC_WCK3_N

F8
E8
A5
A6
D24
D25
B27
C27

FBC_WCK0 <30>
FBC_WCK0_N <30>
FBC_WCK1 <30>
FBC_WCK1_N <30>
FBC_WCK2 <31>
FBC_WCK2_N <31>
FBC_WCK3 <31>
FBC_WCK3_N <31>

DATA Bus
Address

0..31

FBx_CMD0

CS#

FBx_CMD1

A3_BA3

FBx_CMD2

A2_BA0

FBx_CMD3

A4_BA2

FBx_CMD4

A5_BA1

32..63

FBx_CMD5

WE#

FBx_CMD6

A7_A8

FBx_CMD7

A6_A11

FBx_CMD8

ABI#

FBx_CMD9

A12_RFU

FBx_CMD10

A0_A10

FBx_CMD11

A1_A9

FBx_CMD12

RAS#

FBx_CMD13

RST#

FBx_CMD14

CKE#

FBx_CMD15

CAS#

C

FBx_CMD16

CS#

FBx_CMD17

A3_BA3

FBx_CMD18

A2_BA0

FBx_CMD19

A4_BA2

FBx_CMD20

A5_BA1

FBx_CMD21

WE#

FBx_CMD22

D6
D7
C6
B6
F26
E26
A26
A27

H17

D

1

FBC_EDC0
FBC_EDC1
FBC_EDC2
FBC_EDC3
FBC_EDC4
FBC_EDC5
FBC_EDC6
FBC_EDC7

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7

FBB_CMD_RFU0
FBB_CMD_RFU1

FBC_CS#_L
FBC_MA3_BA3_L
FBC_MA2_BA0_L
FBC_MA4_BA2_L
FBC_MA5_BA1_L
FBC_WE#_L
FBC_MA7_MA8_L
FBC_MA6_MA11_L
FBC_ABI#_L
FBC_MA12_RFU_L
FBC_MA0_MA10_L
FBC_MA1_MA9_L
FBC_RAS#_L
FBC_RST#_L
FBC_CKE_L
FBC_CAS#_L
FBC_CS#_H
FBC_MA3_BA3_H
FBC_MA2_BA0_H
FBC_MA4_BA2_H
FBC_MA5_BA1_H
FBC_WE#_H
FBC_MA7_MA8_H
FBC_MA6_MA11_H
FBC_ABI#_H
FBC_MA12_RFU_H
FBC_MA0_MA10_H
FBC_MA1_MA9_H
FBC_RAS#_H
FBC_RST#_H
FBC_CKE_H
FBC_CAS#_H

D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17

2

E11
E3
A3
C9
F23
F27
C30
A24

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31

1

FBC_DBI0#
FBC_DBI1#
FBC_DBI2#
FBC_DBI3#
FBC_DBI4#
FBC_DBI5#
FBC_DBI6#
FBC_DBI7#

FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

2

1
2

FBA_CLK0 <28>
FBA_CLK0# <28>
FBA_CLK1 <29>
FBA_CLK1# <29>

G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26

MEMORY INTERFACE B

R30
R31
AB31
AC31

+1.5VS_VGA

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

A7_A8

FBx_CMD23

A6_A11

FBx_CMD24

ABI#

FBx_CMD25

A12_RFU

FBx_CMD26

A0_A10

FBx_CMD27

A1_A9

FBx_CMD28

RAS#

FBx_CMD29

RST#

FBx_CMD30

CKE#

FBx_CMD31

CAS#

B

+FB_PLLAVDD
1

2

OPT@ CV108

M30
H30
E34
M34
AF30
AK31
AM34
AF32

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

1

M31
G31
E33
M33
AE31
AK30
AN33
AF33

FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

2

FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7

FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N

1
R28 60.4_0402_1%
1
AC28 60.4_0402_1%

Part 3 of 7

0.1U_0402_10V7K

<29> FBA_EDC[7..4]

P30
F31
F34
M32
AD31
AL29
AM32
AF34

FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N

@
2RV58
2RV59
@

OPT@CV39

<28> FBA_EDC[3..0]

FBA_DBI0#
FBA_DBI1#
FBA_DBI2#
FBA_DBI3#
FBA_DBI4#
FBA_DBI5#
FBA_DBI6#
FBA_DBI7#

FBA_DEBUG0
FBA_DEBUG1

R32
AC32

OPT@ CV110

B

FBA_DBI0#
FBA_DBI1#
FBA_DBI2#
FBA_DBI3#
FBA_DBI4#
FBA_DBI5#
FBA_DBI6#
FBA_DBI7#

FBA_CMD_RFU0
FBA_CMD_RFU1

FBA_CS#_L <28>
FBA_MA3_BA3_L <28>
FBA_MA2_BA0_L <28>
FBA_MA4_BA2_L <28>
FBA_MA5_BA1_L <28> +1.5VS_VGA
FBA_WE#_L <28>
FBA_MA7_MA8_L <28>
FBA_MA6_MA11_L <28>
FBA_ABI#_L <28>
RV209
FBA_MA12_RFU_L <28>
10K_0402_5%
FBA_MA0_MA10_L <28>
OPT@
FBA_MA1_MA9_L <28>
FBA_RAS#_L <28>
FBA_RST#_L <28>
FBA_CKE_L <28>
FBA_CAS#_L <28>
FBA_CS#_H <29>
FBA_MA3_BA3_H <29>
FBA_MA2_BA0_H <29>
FBA_MA4_BA2_H <29>
FBA_MA5_BA1_H <29>+1.5VS_VGA
FBA_WE#_H <29>
FBA_MA7_MA8_H <29>
FBA_MA6_MA11_H <29>
FBA_ABI#_H <29>
RV221
FBA_MA12_RFU_H <29>
10K_0402_5%
FBA_MA0_MA10_H <29>
OPT@
FBA_MA1_MA9_H <29>
FBA_RAS#_H <29>
FBA_RST#_H <29>
FBA_CKE_H <29>
FBA_CAS#_H <29>

22U_0805_6.3V6M

<28>
<28>
<28>
<28>
<29>
<29>
<29>
<29>

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

FBA_CS#_L
FBA_MA3_BA3_L
FBA_MA2_BA0_L
FBA_MA4_BA2_L
FBA_MA5_BA1_L
FBA_WE#_L
FBA_MA7_MA8_L
FBA_MA6_MA11_L
FBA_ABI#_L
FBA_MA12_RFU_L
FBA_MA0_MA10_L
FBA_MA1_MA9_L
FBA_RAS#_L
FBA_RST#_L
FBA_CKE_L
FBA_CAS#_L
FBA_CS#_H
FBA_MA3_BA3_H
FBA_MA2_BA0_H
FBA_MA4_BA2_H
FBA_MA5_BA1_H
FBA_WE#_H
FBA_MA7_MA8_H
FBA_MA6_MA11_H
FBA_ABI#_H
FBA_MA12_RFU_H
FBA_MA0_MA10_H
FBA_MA1_MA9_H
FBA_RAS#_H
FBA_RST#_H
FBA_CKE_H
FBA_CAS#_H

OPT@ CV107

C

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31

1U_0402_6.3V6K

LV3 OPT@

Place close to BGA

L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33

0.1U_0402_10V7K

FBMA-L11-160808300LMA25T_2P
+FB_PLLAVDD
1
2

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

MEMORY INTERFACE
A

Part 2 of 7

+FB_PLLAVDD

200mA

D

2

<30,31> FBC_D[0..63]

FBA_D[0..63]

<28,29> FBA_D[0..63]

+1.05VS_VGA

3

Place close to ball
FBC_RST#_L
FBC_RST#_H

3

GC6@

2

GC6_EN

GC6@

FBVDDQ_PWR_EN <53>

2
0_0402_5%

2

1
RV156

Issued Date

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GC6@

NOGC6@
5

1

Compal Secret Data

Security Classification
RV19
200K_0402_5%

<19,53,56> DGPU_PWROK

A

RV71
RV72
10K_0402_5% 10K_0402_5%
OPT@
OPT@

DAN202UT106_SC70-3
2
1
3
1

2
RV7
1
RV67
GC6@

2

2
DV2

S

GC6@
FB_CLAMP
1
1K_0402_1%
2
10K_0402_5%

RV74
RV73
10K_0402_5% 10K_0402_5%
OPT@
OPT@

1

1

<18> DGPU_GC6_EN

N13P-PES-A1_FCBGA908
FBA_RST#_L
FBA_RST#_H

D
QV3
2N7002_SOT23

2 2
G
0_0402_5%

2

1

RV157
A

N13P-PES-A1_FCBGA908

+3VS

GC6@

1

1

For N13P-GT/N13E-GE GC6 support

4

3

2

Title

Compal Electronics, Inc.
N13P-MEM Interface

Size

Document Number

Rev
1.0

QIWY3 LA-8001P
Date:

Monday, January 16, 2012
1

Sheet

27

of

64

5

4

3

2

Memory Partition A - Lower 32 bits
UV3

MF=0

FBA_EDC0
FBA_EDC2

<27> FBA_D[0..31]

<27> FBA_EDC[3..0]
<27>

FBA_DBI0#

<27>

FBA_DBI2#

FBA_DBI0#
FBA_DBI2#

D

J12
J11
J3

FBA_MA2_BA0_L
FBA_MA5_BA1_L
FBA_MA4_BA2_L
FBA_MA3_BA3_L

H11
K10
K11
H10

FBA_MA7_MA8_L
FBA_MA1_MA9_L
FBA_MA0_MA10_L
FBA_MA6_MA11_L
FBA_MA12_RFU_L

K4
H5
H4
K5
J5

FBA_MA2_BA0_L
FBA_MA5_BA1_L
FBA_MA4_BA2_L
FBA_MA3_BA3_L

<27> FBA_MA7_MA8_L
<27> FBA_MA1_MA9_L
<27> FBA_MA0_MA10_L
<27> FBA_MA6_MA11_L
<27> FBA_MA12_RFU_L

D2
D13
P13
P2

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

<27> FBA_CLK0
<27> FBA_CLK0#
<27> FBA_CKE_L

<27>
<27>
<27>
<27>

C2
C13
R13
R2

A5
U5
2 RV115 1
OPT@ 1K_0402_1%
J1
J10
J13

2 RV117 1
OPT@ 1K_0402_1%

2 RV119 1
OPT@ 121_0402_1%

Follow DG
1
RV21

2
40.2_0402_1%
OPT@

2

FBA_CLK0

RV123
160_0402_1%
@
FBA_CLK0#

1
RV28

2
40.2_0402_1%

D5
D4

FBA_WCK1_N
FBA_WCK1

P5
P4

+FBA_VREFD_L

A10
U10
J14

<27> FBA_WCK1_N
<27> FBA_WCK1

1

2

OPT@ CV155

0.01U_0402_25V7K

OPT@

J4
G3
G12
L3
L12

FBA_WCK0_N
FBA_WCK0

<27> FBA_WCK0_N
<27> FBA_WCK0

1

C

FBA_ABI#_L
FBA_RAS#_L
FBA_CS#_L
FBA_CAS#_L
FBA_WE#_L

<27> FBA_ABI#_L
<27> FBA_RAS#_L
<27> FBA_CS#_L
<27> FBA_CAS#_L
<27> FBA_WE#_L

+FBA_VREFC0

FBA_RST#_L

<27> FBA_RST#_L

J2

UV4

MF=1

EDC0
EDC1
EDC2
EDC3

EDC3
EDC2
EDC1
EDC0

DBI0#
DBI1#
DBI2#
DBI3#

DBI3#
DBI2#
DBI1#
DBI0#

MF=1

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CK
CK#
CKE#
BA0/A2
BA1/A5
BA2/A4
BA3/A3

BA2/A4
BA3/A3
BA0/A2
BA1/A5

A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC

A10/A0
A11/A6
A8/A7
A9/A1

VPP/NC
VPP/NC

1
2

RV127
549_0402_1%
OPT@
RV212

2

1

820P_0402_25V7

B

OPT@ CV42

+FBA_VREFC0

1
2
931_0402_1%
OPT@
RV128
1.33K_0402_1%
OPT@

1

2

16 mil

+1.5VS_VGA

G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14

1

+1.5VS_VGA

RV129
549_0402_1%
OPT@

2

RV213

CAS#
WE#
RAS#
CS#

WCK01#
WCK01

WCK23#
WCK23

WCK23#
WCK23

WCK01#
WCK01

VREFD
VREFD
VREFC

RESET#

820P_0402_25V7

1

OPT@
S

2

1

D

2
G
3

<23,29,30,31> MEM_VREF

QV9
2N7002W-T/R7_SOT323-3

1

2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

OPT@ CV58

+FBA_VREFD_L

1
2
931_0402_1%
OPT@
RV130
1.33K_0402_1%
OPT@

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

+1.5VS_VGA

H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14

MF=0

MF=0

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7

FBA_EDC3
FBA_EDC1

BYTE0

<27>

FBA_DBI3#

<27>

FBA_DBI1#

FBA_DBI3#
FBA_DBI1#

FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23

<27>
<27>
<27>
<27>

BYTE2

FBA_MA4_BA2_L
FBA_MA3_BA3_L
FBA_MA2_BA0_L
FBA_MA5_BA1_L

<27> FBA_MA0_MA10_L
<27> FBA_MA6_MA11_L
<27> FBA_MA7_MA8_L
<27> FBA_MA1_MA9_L
<27> FBA_MA12_RFU_L

170-BALL
SGRAM GDDR5

C2
C13
R13
R2
D2
D13
P13
P2

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

J12
J11
J3

FBA_MA4_BA2_L
FBA_MA3_BA3_L
FBA_MA2_BA0_L
FBA_MA5_BA1_L

H11
K10
K11
H10

FBA_MA0_MA10_L
FBA_MA6_MA11_L
FBA_MA7_MA8_L
FBA_MA1_MA9_L
FBA_MA12_RFU_L

K4
H5
H4
K5
J5

<27> FBA_CLK0
<27> FBA_CLK0#
<27> FBA_CKE_L

A5
U5

+1.5VS_VGA

2 RV116 1
OPT@ 1K_0402_1%

+1.5VS_VGA

MF
SEN
ZQ
ABI#
RAS#
CS#
CAS#
WE#

2 RV118 1
OPT@ 1K_0402_1%

2 RV120 1
OPT@ 121_0402_1%

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

FBA_ABI#_L
FBA_CAS#_L
FBA_WE#_L
FBA_RAS#_L
FBA_CS#_L

<27> FBA_ABI#_L
<27> FBA_CAS#_L
<27> FBA_WE#_L
<27> FBA_RAS#_L
<27> FBA_CS#_L

<27> FBA_WCK1_N
<27> FBA_WCK1
<27> FBA_WCK0_N
<27> FBA_WCK0

J4
G3
G12
L3
L12

D5
D4

FBA_WCK0_N
FBA_WCK0

P5
P4

+FBA_VREFD_L
+FBA_VREFC0

FBA_RST#_L

<27> FBA_RST#_L

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

J1
J10
J13

FBA_WCK1_N
FBA_WCK1

+1.5VS_VGA

A10
U10
J14

J2

H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14

MF=1

EDC0
EDC1
EDC2
EDC3

EDC3
EDC2
EDC1
EDC0

DBI0#
DBI1#
DBI2#
DBI3#

DBI3#
DBI2#
DBI1#
DBI0#

CK
CK#
CKE#
BA0/A2
BA1/A5
BA2/A4
BA3/A3

BA2/A4
BA3/A3
BA0/A2
BA1/A5

A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC

A10/A0
A11/A6
A8/A7
A9/A1

VPP/NC
VPP/NC

ABI#
RAS#
CS#
CAS#
WE#

CAS#
WE#
RAS#
CS#

WCK01#
WCK01

WCK23#
WCK23

WCK23#
WCK23

WCK01#
WCK01

VREFD
VREFD
VREFC

RESET#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

170-BALL

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31

BYTE3

D

FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15

GDDR5
Mode H - Mirror Mode Mapping
BYTE1

DATA Bus

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

0..31

FBx_CMD0

CS#

FBx_CMD1

A3_BA3

FBx_CMD2

A2_BA0

FBx_CMD3

A4_BA2

FBx_CMD4

A5_BA1

FBx_CMD5

WE#

FBx_CMD6

A7_A8

FBx_CMD7

A6_A11

FBx_CMD8

ABI#

FBx_CMD9

A12_RFU

FBx_CMD10

A0_A10

FBx_CMD11

A1_A9

FBx_CMD12

RAS#

FBx_CMD13

RST#

FBx_CMD14

CKE#

FBx_CMD15

CAS#

32..63

C

FBx_CMD16

CS#

FBx_CMD17

A3_BA3

FBx_CMD18

A2_BA0

FBx_CMD19

A4_BA2

FBx_CMD20

A5_BA1

FBx_CMD21

WE#
A7_A8

FBx_CMD22

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

FBx_CMD23

A6_A11

FBx_CMD24

ABI#

FBx_CMD25

A12_RFU

FBx_CMD26

A0_A10

FBx_CMD27

A1_A9

FBx_CMD28

RAS#

FBx_CMD29

RST#

FBx_CMD30

CKE#

FBx_CMD31

CAS#

B

1

2

1

2

OPT@ CV136

2

OPT@ CV135

1

0.1U_0402_10V7K

2

OPT@ CV134

1

0.1U_0402_10V7K

2

0.1U_0402_10V7K

1

1U_0603_25V6

2

OPT@ CV80

1

OPT@ CV79

2

1U_0603_25V6

1

OPT@ CV76
1U_0603_25V6

1

1U_0603_25V6

2

A

Compal Secret Data

Security Classification
Issued Date

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Address

UV4 SIDE
OPT@ CV71

2

OPT@ CV174

1

10U_0603_6.3V6M

2

OPT@ CV133

1

OPT@ CV132

2

0.1U_0402_10V7K

1

OPT@ CV129

2

0.1U_0402_10V7K

1

0.1U_0402_10V7K

2

1U_0603_25V6

1

OPT@ CV78

2

OPT@ CV77

1

OPT@ CV69
1U_0603_25V6

2

1U_0603_25V6

1U_0603_25V6

1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

H5GQ1H24AFR-T2L_BGA170
+1.5VS_VGA

UV3 SIDE
OPT@ CV68

OPT@ CV166

10U_0603_6.3V6M

A

1

MF=0

X76@
H5GQ1H24AFR-T2L_BGA170

2

MF=1

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

+1.5VS_VGA

MF
SEN
ZQ

SGRAM GDDR5

X76@

+1.5VS_VGA

1

4

3

2

Title

Compal Electronics, Inc.
N13P-VRAM A Lower

Size

Document Number

Rev
1.0

QIWY3 LA-8001P
Date:

Monday, January 16, 2012
1

Sheet

28

of

64

5

4

3

2

Memory Partition A - Upper 32 bits

1

UV6

UV5
MF=0
MF=0

FBA_EDC4
FBA_EDC6

<27> FBA_D[63..32]

<27> FBA_EDC[7..4]
D

<27>

FBA_DBI4#

<27>

FBA_DBI6#

<27> FBA_CLK1
<27> FBA_CLK1#
<27> FBA_CKE_H

<27>
<27>
<27>
<27>

FBA_DBI4#
FBA_DBI6#

D2
D13
P13
P2

FBA_CLK1
FBA_CLK1#
FBA_CKE_H

J12
J11
J3

FBA_MA2_BA0_H
FBA_MA5_BA1_H
FBA_MA4_BA2_H
FBA_MA3_BA3_H

H11
K10
K11
H10

FBA_MA2_BA0_H
FBA_MA5_BA1_H
FBA_MA4_BA2_H
FBA_MA3_BA3_H

FBA_MA7_MA8_H
FBA_MA1_MA9_H
FBA_MA0_MA10_H
FBA_MA6_MA11_H
FBA_MA12_RFU_H

<27> FBA_MA7_MA8_H
<27> FBA_MA1_MA9_H
<27> FBA_MA0_MA10_H
<27> FBA_MA6_MA11_H
<27> FBA_MA12_RFU_H

C2
C13
R13
R2

K4
H5
H4
K5
J5
A5
U5

2 RV131 1
OPT@ 1K_0402_1%
2 RV133 1
OPT@ 1K_0402_1%
2 RV135 1
OPT@ 121_0402_1%

Follow DG
1
RV31

2
40.2_0402_1%
OPT@

2

FBA_CLK1

RV139
160_0402_1%
@
FBA_CLK1#

1
RV36

2
40.2_0402_1%

D5
D4

FBA_WCK3_N
FBA_WCK3

P5
P4

+FBA_VREFD_H

A10
U10
J14

<27> FBA_WCK3_N
<27> FBA_WCK3

1

2

OPT@ CV175

0.01U_0402_25V7K

OPT@

J4
G3
G12
L3
L12

FBA_WCK2_N
FBA_WCK2

<27> FBA_WCK2_N
<27> FBA_WCK2

1

C

FBA_ABI#_H
FBA_RAS#_H
FBA_CS#_H
FBA_CAS#_H
FBA_WE#_H

<27> FBA_ABI#_H
<27> FBA_RAS#_H
<27> FBA_CS#_H
<27> FBA_CAS#_H
<27> FBA_WE#_H

+FBA_VREFC1

FBA_RST#_H

<27> FBA_RST#_H

1
RV143
549_0402_1%
OPT@

2
1

820P_0402_25V7

+FBA_VREFC1

2

RV144
1.33K_0402_1%
OPT@

1

2

OPT@ CV59

RV214

16 mil
+1.5VS_VGA

G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14

B

1

+1.5VS_VGA

RV145
549_0402_1%
OPT@

2
S

1

820P_0402_25V7

OPT@

2
G
3

<23,28,30,31> MEM_VREF

QV11
2N7002W-T/R7_SOT323-3

EDC0
EDC1
EDC2
EDC3

EDC3
EDC2
EDC1
EDC0

DBI0#
DBI1#
DBI2#
DBI3#

DBI3#
DBI2#
DBI1#
DBI0#

CK
CK#
CKE#
BA0/A2
BA1/A5
BA2/A4
BA3/A3

BA2/A4
BA3/A3
BA0/A2
BA1/A5

A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC

A10/A0
A11/A6
A8/A7
A9/A1

VPP/NC
VPP/NC

1

2

MF=1

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

ABI#
RAS#
CS#
CAS#
WE#

WCK01#
WCK01
WCK23#
WCK23

CAS#
WE#
RAS#
CS#

WCK23#
WCK23
WCK01#
WCK01

VREFD
VREFD
VREFC

RESET#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

170-BALL
SGRAM GDDR5

MF=1

MF=1

MF=0

MF=0

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39

FBA_EDC7
FBA_EDC5

BYTE4
<27>

FBA_DBI7#

<27>

FBA_DBI5#

<27> FBA_CLK1
<27> FBA_CLK1#
<27> FBA_CKE_H
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55

<27>
<27>
<27>
<27>

BYTE6

FBA_MA4_BA2_H
FBA_MA3_BA3_H
FBA_MA2_BA0_H
FBA_MA5_BA1_H

<27> FBA_MA0_MA10_H
<27> FBA_MA6_MA11_H
<27> FBA_MA7_MA8_H
<27> FBA_MA1_MA9_H
<27> FBA_MA12_RFU_H

FBA_DBI7#
FBA_DBI5#

C2
C13
R13
R2
D2
D13
P13
P2

FBA_CLK1
FBA_CLK1#
FBA_CKE_H

J12
J11
J3

FBA_MA4_BA2_H
FBA_MA3_BA3_H
FBA_MA2_BA0_H
FBA_MA5_BA1_H

H11
K10
K11
H10

FBA_MA0_MA10_H
FBA_MA6_MA11_H
FBA_MA7_MA8_H
FBA_MA1_MA9_H
FBA_MA12_RFU_H

K4
H5
H4
K5
J5
A5
U5

+1.5VS_VGA

2 RV132 1
OPT@ 1K_0402_1%
+1.5VS_VGA

MF
SEN
ZQ

+FBA_VREFD_H

RV146
1.33K_0402_1%
OPT@

2

1

1
2
931_0402_1%
OPT@
D

OPT@ CV60

RV215

J2

H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14

+1.5VS_VGA

1
2
931_0402_1%
OPT@

J1
J10
J13

MF=1

2 RV134 1
OPT@ 1K_0402_1%
2 RV136 1
OPT@ 121_0402_1%

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

FBA_ABI#_H
FBA_CAS#_H
FBA_WE#_H
FBA_RAS#_H
FBA_CS#_H

<27> FBA_ABI#_H
<27> FBA_CAS#_H
<27> FBA_WE#_H
<27> FBA_RAS#_H
<27> FBA_CS#_H

<27> FBA_WCK3_N
<27> FBA_WCK3
<27> FBA_WCK2_N
<27> FBA_WCK2

J4
G3
G12
L3
L12

FBA_WCK3_N
FBA_WCK3

D5
D4

FBA_WCK2_N
FBA_WCK2

P5
P4

+FBA_VREFD_H

A10
U10
J14

+FBA_VREFC1

FBA_RST#_H

<27> FBA_RST#_H

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

J1
J10
J13

+1.5VS_VGA

J2

H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14

EDC0
EDC1
EDC2
EDC3

EDC3
EDC2
EDC1
EDC0

DBI0#
DBI1#
DBI2#
DBI3#

DBI3#
DBI2#
DBI1#
DBI0#

CK
CK#
CKE#
BA0/A2
BA1/A5
BA2/A4
BA3/A3

BA2/A4
BA3/A3
BA0/A2
BA1/A5

A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC

A10/A0
A11/A6
A8/A7
A9/A1

VPP/NC
VPP/NC

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

BYTE7

D

FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47

BYTE5

GDDR5
Mode H - Mirror Mode Mapping
DATA Bus

+1.5VS_VGA

MF
SEN
ZQ
ABI#
RAS#
CS#
CAS#
WE#

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CAS#
WE#
RAS#
CS#

WCK01#
WCK01

WCK23#
WCK23

WCK23#
WCK23

WCK01#
WCK01

VREFD
VREFD
VREFC

RESET#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

170-BALL
SGRAM GDDR5

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

Address

0..31

FBx_CMD0

CS#

FBx_CMD1

A3_BA3

FBx_CMD2

A2_BA0

FBx_CMD3

A4_BA2

FBx_CMD4

A5_BA1

FBx_CMD5

WE#

FBx_CMD6

A7_A8

FBx_CMD7

A6_A11

FBx_CMD8

ABI#

FBx_CMD9

A12_RFU

FBx_CMD10

A0_A10

FBx_CMD11

A1_A9

FBx_CMD12

RAS#

FBx_CMD13

RST#

FBx_CMD14

CKE#

FBx_CMD15

CAS#

32..63

C

FBx_CMD16

CS#

FBx_CMD17

A3_BA3

FBx_CMD18

A2_BA0

FBx_CMD19

A4_BA2

FBx_CMD20

A5_BA1

FBx_CMD21

WE#

FBx_CMD22

A7_A8
A6_A11

FBx_CMD23
FBx_CMD24

ABI#

FBx_CMD25

A12_RFU

FBx_CMD26

A0_A10

FBx_CMD27

A1_A9

FBx_CMD28

RAS#

FBx_CMD29

RST#

FBx_CMD30

CKE#

FBx_CMD31

CAS#

B

X76@

X76@
H5GQ1H24AFR-T2L_BGA170

UV5 SIDE

H5GQ1H24AFR-T2L_BGA170

1

2

1

2

OPT@ CV144

2

OPT@ CV143

1

0.1U_0402_10V7K

2

OPT@ CV145

1

0.1U_0402_10V7K

2

0.1U_0402_10V7K

1

1U_0603_25V6

2

OPT@ CV86

1

OPT@ CV85

2

1U_0603_25V6

1

OPT@ CV88
1U_0603_25V6

1

UV6 SIDE
1U_0603_25V6

2

OPT@ CV187

2

10U_0603_6.3V6M

1

OPT@ CV137

2

OPT@ CV142

1

0.1U_0402_10V7K

2

OPT@ CV138

1

0.1U_0402_10V7K

2

0.1U_0402_10V7K

1U_0603_25V6

2

1

OPT@ CV83

2

1

OPT@ CV82

1

OPT@ CV81
1U_0603_25V6

2

1U_0603_25V6

1

OPT@ CV84

1U_0603_25V6

1

OPT@ CV179

A

10U_0603_6.3V6M

+1.5VS_VGA

2

OPT@ CV87

+1.5VS_VGA

A

Compal Secret Data

Security Classification
Issued Date

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
N13P-VRAM A Upper

Size

Document Number

Rev
1.0

QIWY3 LA-8001P
Date:

Monday, January 16, 2012
1

Sheet

29

of

64

5

4

3

2

1

Memory Partition C - Lower 32 bits
UV7

UV8

FBC_CLK0

1
RV37
2

OPT@

C

RV155
160_0402_1%
@

<27> FBC_WCK0_N
<27> FBC_WCK0

1

FBC_CLK0#

FBC_ABI#_L
FBC_RAS#_L
FBC_CS#_L
FBC_CAS#_L
FBC_WE#_L

<27> FBC_ABI#_L
<27> FBC_RAS#_L
<27> FBC_CS#_L
<27> FBC_CAS#_L
<27> FBC_WE#_L

2
40.2_0402_1%

1
RV39

2
40.2_0402_1%

<27> FBC_WCK1_N
<27> FBC_WCK1
OPT@ CV195

0.01U_0402_25V7K

OPT@
1

2

J4
G3
G12
L3
L12

FBC_WCK0_N
FBC_WCK0

D5
D4

FBC_WCK1_N
FBC_WCK1

P5
P4

+FBC_VREFD_L
+FBC_VREFC0

FBC_RST#_L

<27> FBC_RST#_L

A10
U10
J14

J2

ABI#
RAS#
CS#
CAS#
WE#

CAS#
WE#
RAS#
CS#

WCK01#
WCK01

WCK23#
WCK23

WCK23#
WCK23

WCK01#
WCK01

VREFD
VREFD
VREFC

RESET#

1

+1.5VS_VGA

RV159
549_0402_1%
OPT@
2
1

820P_0402_25V7

+FBC_VREFC0

2

RV160
1.33K_0402_1%
OPT@

1

2

OPT@ CV61

RV216
1
2
931_0402_1%
OPT@

+1.5VS_VGA

G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14

B

1

+1.5VS_VGA

RV161
549_0402_1%
OPT@
2
1

820P_0402_25V7

S

+FBC_VREFD_L

RV162
1.33K_0402_1%
OPT@
2

1

D

3

1
2
931_0402_1%
OPT@

OPT@

2
G

<23,28,29,31> MEM_VREF

1

2

OPT@ CV62

RV217

H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

170-BALL
SGRAM GDDR5

QV13
2N7002W-T/R7_SOT323-3

X76@

1

2

OPT@ CV159

2

OPT@ CV157

1

0.1U_0402_10V7K

2

0.1U_0402_10V7K

1

OPT@ CV160

2

0.1U_0402_10V7K

1U_0603_25V6

2

1

OPT@ CV90

2

1

OPT@ CV89

2

1

H5GQ1H24AFR-T2L_BGA170
OPT@ CV92
1U_0603_25V6

1

1U_0603_25V6

1U_0603_25V6

1

UV7 SIDE
OPT@ CV91

2

OPT@ CV199

A

10U_0603_6.3V6M

+1.5VS_VGA

2 RV150 1
OPT@ 1K_0402_1%
2 RV152 1
OPT@ 121_0402_1%

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

FBC_ABI#_L
FBC_CAS#_L
FBC_WE#_L
FBC_RAS#_L
FBC_CS#_L

<27> FBC_ABI#_L
<27> FBC_CAS#_L
<27> FBC_WE#_L
<27> FBC_RAS#_L
<27> FBC_CS#_L

<27> FBC_WCK1_N
<27> FBC_WCK1
<27> FBC_WCK0_N
<27> FBC_WCK0

J1
J10
J13

D5
D4

FBC_WCK0_N
FBC_WCK0

P5
P4

+FBC_VREFD_L

A10
U10
J14

+FBC_VREFC0

FBC_RST#_L

<27> FBC_RST#_L

DBI3#
DBI2#
DBI1#
DBI0#

BA0/A2
BA1/A5
BA2/A4
BA3/A3

BA2/A4
BA3/A3
BA0/A2
BA1/A5

A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC

A10/A0
A11/A6
A8/A7
A9/A1

J2

ABI#
RAS#
CS#
CAS#
WE#

CAS#
WE#
RAS#
CS#

WCK01#
WCK01

WCK23#
WCK23

WCK23#
WCK23

WCK01#
WCK01

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

170-BALL
SGRAM GDDR5

+1.5VS_VGA

2

1

UV8 SIDE
1

2

1

2

1

2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

RESET#

G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14

MF=0
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31

FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15

BYTE3
D

GDDR5
Mode H - Mirror Mode Mapping

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

2

1

2

1

2

1

2

Issued Date

3

0..31

FBx_CMD0

CS#

FBx_CMD1

A3_BA3

FBx_CMD2

A2_BA0

FBx_CMD3

A4_BA2

FBx_CMD4

A5_BA1

FBx_CMD5

WE#

FBx_CMD6

A7_A8

FBx_CMD7

A6_A11

FBx_CMD8

ABI#

FBx_CMD9

A12_RFU

FBx_CMD10

A0_A10

FBx_CMD11

A1_A9

FBx_CMD12

RAS#

FBx_CMD13

RST#

FBx_CMD14

CKE#

FBx_CMD15

CAS#

32..63

C

FBx_CMD16

CS#

FBx_CMD17

A3_BA3

FBx_CMD18

A2_BA0

FBx_CMD19

A4_BA2

FBx_CMD20

A5_BA1

FBx_CMD21

WE#

FBx_CMD22

A7_A8

FBx_CMD23

A6_A11

FBx_CMD24

ABI#

FBx_CMD25

A12_RFU

FBx_CMD26

A0_A10
A1_A9

FBx_CMD27
FBx_CMD28

RAS#

FBx_CMD29

RST#

FBx_CMD30

CKE#

FBx_CMD31

CAS#

B

H5GQ1H24AFR-T2L_BGA170

A

Compal Secret Data
2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Address

X76@
1

Security Classification

5

DATA Bus

BYTE1

+1.5VS_VGA

VREFD
VREFD
VREFC

H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14

+1.5VS_VGA

DBI0#
DBI1#
DBI2#
DBI3#

MF
SEN
ZQ

J4
G3
G12
L3
L12

FBC_WCK1_N
FBC_WCK1

EDC3
EDC2
EDC1
EDC0

MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

VPP/NC
VPP/NC

2 RV148 1
OPT@ 1K_0402_1%

+1.5VS_VGA

MF
SEN
ZQ

EDC0
EDC1
EDC2
EDC3

OPT@ CV162

Follow DG

J1
J10
J13

K4
H5
H4
K5
J5

+1.5VS_VGA

MF=1

CK
CK#
CKE#

A5
U5

OPT@ CV161

2 RV149 1
OPT@ 1K_0402_1%
2 RV151 1
OPT@ 121_0402_1%

VPP/NC
VPP/NC

D2
D13
P13
P2

H11
K10
K11
H10

FBC_MA0_MA10_L
FBC_MA6_MA11_L
FBC_MA7_MA8_L
FBC_MA1_MA9_L
FBC_MA12_RFU_L

<27> FBC_MA0_MA10_L
<27> FBC_MA6_MA11_L
<27> FBC_MA7_MA8_L
<27> FBC_MA1_MA9_L
<27> FBC_MA12_RFU_L

0.1U_0402_10V7K

2 RV147 1
OPT@ 1K_0402_1%

A10/A0
A11/A6
A8/A7
A9/A1

FBC_MA4_BA2_L
FBC_MA3_BA3_L
FBC_MA2_BA0_L
FBC_MA5_BA1_L

OPT@ CV163

A5
U5

A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC

<27>
<27>
<27>
<27>

BYTE2

C2
C13
R13
R2

J12
J11
J3

FBC_MA4_BA2_L
FBC_MA3_BA3_L
FBC_MA2_BA0_L
FBC_MA5_BA1_L

0.1U_0402_10V7K

K4
H5
H4
K5
J5

BA2/A4
BA3/A3
BA0/A2
BA1/A5

FBC_CLK0
FBC_CLK0#
FBC_CKE_L

<27> FBC_CLK0
<27> FBC_CLK0#
<27> FBC_CKE_L
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23

0.1U_0402_10V7K

FBC_MA7_MA8_L
FBC_MA1_MA9_L
FBC_MA0_MA10_L
FBC_MA6_MA11_L
FBC_MA12_RFU_L

<27> FBC_MA7_MA8_L
<27> FBC_MA1_MA9_L
<27> FBC_MA0_MA10_L
<27> FBC_MA6_MA11_L
<27> FBC_MA12_RFU_L

BA0/A2
BA1/A5
BA2/A4
BA3/A3

FBC_DBI1#

<27> FBC_DBI1#

1U_0603_25V6

FBC_MA2_BA0_L
FBC_MA5_BA1_L
FBC_MA4_BA2_L
FBC_MA3_BA3_L

H11
K10
K11
H10

CK
CK#
CKE#

FBC_DBI3#

<27> FBC_DBI3#

OPT@ CV94

<27>
<27>
<27>
<27>

FBC_MA2_BA0_L
FBC_MA5_BA1_L
FBC_MA4_BA2_L
FBC_MA3_BA3_L

J12
J11
J3

DBI3#
DBI2#
DBI1#
DBI0#

FBC_EDC1

BYTE0

OPT@ CV93

FBC_CLK0
FBC_CLK0#
FBC_CKE_L

<27> FBC_CLK0
<27> FBC_CLK0#
<27> FBC_CKE_L

DBI0#
DBI1#
DBI2#
DBI3#

FBC_EDC3

1U_0603_25V6

FBC_DBI2#

<27> FBC_DBI2#

D2
D13
P13
P2

MF=0
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7

OPT@ CV96
1U_0603_25V6

FBC_DBI0#

<27> FBC_DBI0#

EDC3
EDC2
EDC1
EDC0

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

1U_0603_25V6

<27> FBC_EDC[3..0]
D

EDC0
EDC1
EDC2
EDC3

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

MF=0

OPT@ CV95

FBC_EDC2

<27> FBC_D[0..31]

C2
C13
R13
R2

MF=1

OPT@ CV207

FBC_EDC0

MF=1

10U_0603_6.3V6M

MF=0

2

Title

Compal Electronics, Inc.
N13P-VRAM C Lower

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012
1

Sheet

30

of

64

5

4

3

2

1

Memory Partition C - Upper 32 bits
UV9

Follow DG
FBC_CLK1

1
RV41

2
40.2_0402_1%

2

OPT@
RV171
160_0402_1%
@

FBC_CLK1#

1
RV48

2
40.2_0402_1%

D5
D4

FBC_WCK3_N
FBC_WCK3

P5
P4

+FBC_VREFD_H

A10
U10
J14

<27> FBC_WCK3_N
<27> FBC_WCK3
OPT@ CV215

0.01U_0402_25V7K

OPT@
1

2

J4
G3
G12
L3
L12

FBC_WCK2_N
FBC_WCK2

<27> FBC_WCK2_N
<27> FBC_WCK2

1

C

FBC_ABI#_H
FBC_RAS#_H
FBC_CS#_H
FBC_CAS#_H
FBC_WE#_H

<27> FBC_ABI#_H
<27> FBC_RAS#_H
<27> FBC_CS#_H
<27> FBC_CAS#_H
<27> FBC_WE#_H

J1
J10
J13

+FBC_VREFC1

FBC_RST#_H

<27> FBC_RST#_H

J2

VPP/NC
VPP/NC

ABI#
RAS#
CS#
CAS#
WE#

CAS#
WE#
RAS#
CS#

WCK01#
WCK01

WCK23#
WCK23

WCK23#
WCK23

WCK01#
WCK01

VREFD
VREFD
VREFC

RESET#

1
RV175
549_0402_1%
OPT@
2
1

820P_0402_25V7

+FBC_VREFC1

2

RV176
1.33K_0402_1%
OPT@

1

2

OPT@ CV63

RV218
1
2
931_0402_1%
OPT@

+1.5VS_VGA

G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14

B

1

+1.5VS_VGA

RV177
549_0402_1%
OPT@
2
1

820P_0402_25V7

S

+FBC_VREFD_H

RV178
1.33K_0402_1%
OPT@
2

1

D

3

1
2
931_0402_1%
OPT@

OPT@

2
G

<23,28,29,30> MEM_VREF

1

2

OPT@ CV64

RV219

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

170-BALL
SGRAM GDDR5

QV15
2N7002W-T/R7_SOT323-3

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

FBC_MA0_MA10_H
FBC_MA6_MA11_H
FBC_MA7_MA8_H
FBC_MA1_MA9_H
FBC_MA12_RFU_H

K4
H5
H4
K5
J5
A5
U5
J1
J10
J13

2 RV166 1
OPT@ 1K_0402_1%
2 RV168 1
OPT@ 121_0402_1%
FBC_ABI#_H
FBC_CAS#_H
FBC_WE#_H
FBC_RAS#_H
FBC_CS#_H

<27> FBC_ABI#_H
<27> FBC_CAS#_H
<27> FBC_WE#_H
<27> FBC_RAS#_H
<27> FBC_CS#_H

<27> FBC_WCK3_N
<27> FBC_WCK3
<27> FBC_WCK2_N
<27> FBC_WCK2

J4
G3
G12
L3
L12

FBC_WCK3_N
FBC_WCK3

D5
D4

FBC_WCK2_N
FBC_WCK2

P5
P4

+FBC_VREFD_H

A10
U10
J14

+FBC_VREFC1

FBC_RST#_H

<27> FBC_RST#_H

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

J2

H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14

+1.5VS_VGA

G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14

MF=1

EDC0
EDC1
EDC2
EDC3

EDC3
EDC2
EDC1
EDC0

DBI0#
DBI1#
DBI2#
DBI3#

DBI3#
DBI2#
DBI1#
DBI0#

CK
CK#
CKE#
BA0/A2
BA1/A5
BA2/A4
BA3/A3

BA2/A4
BA3/A3
BA0/A2
BA1/A5

A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC

A10/A0
A11/A6
A8/A7
A9/A1

VPP/NC
VPP/NC

MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

1

OPT@ CV227

2

ABI#
RAS#
CS#
CAS#
WE#

CAS#
WE#
RAS#
CS#

WCK01#
WCK01

WCK23#
WCK23

WCK23#
WCK23

WCK01#
WCK01

VREFD
VREFD
VREFC

RESET#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

UV10 SIDE
1

2

1

2

1

2

1

2

1

2

1

2

1

2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

170-BALL

+1.5VS_VGA

MF=0
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

BYTE7
D

GDDR5
Mode H - Mirror Mode Mapping
DATA Bus

FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47

BYTE5

+1.5VS_VGA

MF
SEN
ZQ

SGRAM GDDR5

10U_0603_6.3V6M

1

OPT@ CV165

2

0.1U_0402_10V7K

1

OPT@ CV164

2

OPT@ CV167

1

0.1U_0402_10V7K

2

0.1U_0402_10V7K

1U_0603_25V6

2

1

OPT@ CV98

2

1

OPT@ CV97

1

H5GQ1H24AFR-T2L_BGA170
OPT@ CV100
1U_0603_25V6

2

1U_0603_25V6

1

OPT@ CV99

1U_0603_25V6

1

OPT@ CV245

10U_0603_6.3V6M

A

2

UV9 SIDE

H11
K10
K11
H10

2 RV164 1
OPT@ 1K_0402_1%

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

X76@
+1.5VS_VGA

J12
J11
J3

+1.5VS_VGA
+1.5VS_VGA

MF
SEN
ZQ

+1.5VS_VGA
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14

<27> FBC_MA0_MA10_H
<27> FBC_MA6_MA11_H
<27> FBC_MA7_MA8_H
<27> FBC_MA1_MA9_H
<27> FBC_MA12_RFU_H

D2
D13
P13
P2

FBC_MA4_BA2_H
FBC_MA3_BA3_H
FBC_MA2_BA0_H
FBC_MA5_BA1_H

<27> FBC_MA4_BA2_H
<27> FBC_MA3_BA3_H
<27> FBC_MA2_BA0_H
<27> FBC_MA5_BA1_H

BYTE6

C2
C13
R13
R2

OPT@ CV169

2 RV165 1
OPT@ 1K_0402_1%
2 RV167 1
OPT@ 121_0402_1%

A10/A0
A11/A6
A8/A7
A9/A1

FBC_CLK1
FBC_CLK1#
FBC_CKE_H

<27> FBC_CLK1
<27> FBC_CLK1#
<27> FBC_CKE_H

FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55

OPT@ CV168

2 RV163 1
OPT@ 1K_0402_1%

A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC

FBC_DBI5#

<27> FBC_DBI5#

0.1U_0402_10V7K

A5
U5

BA2/A4
BA3/A3
BA0/A2
BA1/A5

FBC_DBI7#

<27> FBC_DBI7#

OPT@ CV170

K4
H5
H4
K5
J5

BA0/A2
BA1/A5
BA2/A4
BA3/A3

FBC_EDC5

0.1U_0402_10V7K

FBC_MA7_MA8_H
FBC_MA1_MA9_H
FBC_MA0_MA10_H
FBC_MA6_MA11_H
FBC_MA12_RFU_H

<27> FBC_MA7_MA8_H
<27> FBC_MA1_MA9_H
<27> FBC_MA0_MA10_H
<27> FBC_MA6_MA11_H
<27> FBC_MA12_RFU_H

H11
K10
K11
H10

CK
CK#
CKE#

MF=0
FBC_EDC7

BYTE4

1U_0603_25V6

FBC_MA2_BA0_H
FBC_MA5_BA1_H
FBC_MA4_BA2_H
FBC_MA3_BA3_H

DBI3#
DBI2#
DBI1#
DBI0#

FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39

OPT@ CV102

<27>
<27>
<27>
<27>

FBC_MA2_BA0_H
FBC_MA5_BA1_H
FBC_MA4_BA2_H
FBC_MA3_BA3_H

J12
J11
J3

DBI0#
DBI1#
DBI2#
DBI3#

UV10
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

OPT@ CV101

FBC_CLK1
FBC_CLK1#
FBC_CKE_H

<27> FBC_CLK1
<27> FBC_CLK1#
<27> FBC_CKE_H

D2
D13
P13
P2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

1U_0603_25V6

FBC_DBI6#

<27> FBC_DBI6#

EDC3
EDC2
EDC1
EDC0

MF=0

OPT@ CV104
1U_0603_25V6

FBC_DBI4#

<27> FBC_DBI4#

EDC0
EDC1
EDC2
EDC3

MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

1U_0603_25V6

<27> FBC_EDC[7..4]
D

MF=1

OPT@ CV103

FBC_EDC6

<27> FBC_D[63..32]

C2
C13
R13
R2

0.1U_0402_10V7K

MF=0
FBC_EDC4

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

FBx_CMD1

A3_BA3

FBx_CMD2

A2_BA0

FBx_CMD3

A4_BA2

FBx_CMD4

A5_BA1

FBx_CMD5

WE#

FBx_CMD6

A7_A8

FBx_CMD7

A6_A11

FBx_CMD8

ABI#

FBx_CMD9

A12_RFU

FBx_CMD10

A0_A10

FBx_CMD11

A1_A9

FBx_CMD12

RAS#

FBx_CMD13

RST#

FBx_CMD14

CKE#

FBx_CMD15

CAS#

32..63

C

FBx_CMD16

CS#

FBx_CMD17

A3_BA3

FBx_CMD18

A2_BA0

FBx_CMD19

A4_BA2

FBx_CMD20

A5_BA1

FBx_CMD21

WE#

FBx_CMD22

A7_A8
A6_A11

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

FBx_CMD24

ABI#

FBx_CMD25

A12_RFU

FBx_CMD26

A0_A10

FBx_CMD27

A1_A9

FBx_CMD28

RAS#

FBx_CMD29

RST#

FBx_CMD30

CKE#

FBx_CMD31

CAS#
B

H5GQ1H24AFR-T2L_BGA170

A

Issued Date

3

CS#

FBx_CMD23

Compal Secret Data
2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

0..31

X76@

Security Classification

5

Address

FBx_CMD0

2

Title

Compal Electronics, Inc.
N13P-VRAM C Upper

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012
1

Sheet

31

of

64

5

4

3

2

2

GL@
RV94
10K_0402_1%

RV122
20K_0402_1%
@
1

1

1

RV121
20K_0402_1%
@

RV96

RV97

45.3K_0402_1%

GL@

1

Logical
Strapping Bit3

ROM_SI

+3VS_VGA

RAM_CFG[3]

RAM_CFG[2]

RAM_CFG[1]

RAM_CFG[0]

ROM_SO

+3VS_VGA

FB[1]

FB[0]

SMB_ALT_ADDR

VGA_DEVICE

STRAP0

+3VS_VGA

USER[3]

USER[2]

USER[1]

STRAP1

+3VS_VGA

STRAP2

+3VS_VGA

PCI_DEVID[3]

STRAP3

+3VS_VGA

SOR3_EXPOSED

STRAP4

+3VS_VGA

PCI_DEVID[1]

PCI_DEVID[0]

SOR2_EXPOSED

SOR1_EXPOSED

SOR0_EXPOSED

PCIE_SPEED_
CHANGE_GEN3

PCIE_MAX_SPEED

DP_PLL_VDD33V

2

RESERVED

5K

24.9K_0402_1%

2

2
1

Pull-down to Gnd
0000

10K

1001

0001

15K

1010

0010

20K

1011

0011

25K

1100

0100

30K

1101

0101

35K

1110

0110

45K

1111

0111
C

GTGE@
RV100
4.99K_0402_1%

3GIO_PADCFG

XCLK_417

3GIO_PADCFG[3:0]

0

277MHz (Default)

1

Reserved

0110

1

2
1

Pull-up to
+3VS_VGA
1000

Resistor Values

RV125
45.3K_0402_1%
GTGE@

D

Notebook Default

SLOT_CLK_CFG

2

GL@
RV102
10K_0402_1%

RV103
15K_0402_1%
GL@
1

1

1

2

2
RV101
20K_0402_1%
X76@

X76

B

0

GPU and MCH don't share a common reference clock

1

GPU and MCH share a common reference clock (Default)

SMBUS_ALT_ADDR

VGA_DEVICE

0

0x9E (Default)

0

3D Device (Class Code 302h)

1

0x9C (Multi-GPU usage)

1

VGA Device (Default)

User[3:0]

0

No VBIOS ROM

1

1000-1100

BIOS ROM is present (Default)

0

Reserved

1

Reserved

2

256MB (Default)

3

Reserved

Compal Secret Data
2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

0

Disable (Default)

1

Enable

PCIE_MAX_SPEED

A

Issued Date

Customer defined

PEX_PLL_EN_TERM

FB_0_BAR_SIZE

Security Classification

B

USER Straps

SUB_VENDOR

5

3GIO_PAD_CFG_ADR[0]

PCI_DEVID[2]

11/07 Follow NV request change to 45K for GTGE

RV99
10K_0402_1%
GTGE@

USER[0]

3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]

ROM_SI
ROM_SO
ROM_SCLK

<24>
ROM_SI
<24>
ROM_SO
<24> ROM_SCLK

PEX_PLL_EN_TERM

PCI_DEVID[4]

+3VS_VGA

RV98
4.99K_0402_1%
@

Logical
Strapping Bit0

SLOT_CLK_CFG

+3VS_VGA

Power Rail

GE@

C

Logical
Strapping Bit1

Logical
Strapping Bit2
SUB_VENDOR

1

2

GTGE@
RV124
4.99K_0402_1%

1

GT@
RV97
10K_0402_1%

1

GTGE@
RV96
34.8K_0402_1%

1

1

@ RV95
45.3K_0402_1%

2

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

2

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

2

<24>
<24>
<24>
<24>
<24>

RV93
34.8K_0402_1%
@
1

1

D

2

2

2
RV92
45.3K_0402_1%
OPT@

2

Physical
Strapping pin
ROM_SCLK

+3VS_VGA

Title

0

Limit to PCIE Gen1

1

PCIE Gen 2/3 Capable

A

Compal Electronics, Inc.
N13P_MISC

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

32

of

64

5

4

3

2

1

+LEDVDD
+LEDVDD

(60 MIL)

CPU_B+

+LCDVDD_CONN

W=40mils
<17>
<17>
<17>
<17>
<17>
<17>

D

C523
470P_0603_50V8J

JLVDS1

CMOS
+CMOS_PW

1 R813

<18>
<18>

USB20_N5
USB20_P5

LVDS_A0#
LVDS_A0
LVDS_A1#
LVDS_A1
LVDS_A2#
LVDS_A2

<17> LVDS_ACLK#
<17> LVDS_ACLK
<42>

USB20_N5
USB20_P5
LVDS_A0#
LVDS_A0
LVDS_A1#
LVDS_A1
LVDS_A2#
LVDS_A2
LVDS_ACLK#
LVDS_ACLK

ECR_EN

9/18 Remove CE_EN

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

31

GND GND

32

9/23 EMI Request

W=60mils

1

1

2

2

2 0_0805_5%

C524
4.7U_0805_25V6-K

+3VS
+3VS
DMIC_DATA <41>
DMIC_CLK <41>

1

D

@
680P_0402_50V7K
C528

2
DISPOFF#
INVPWM
EDID_DATA_CONN
EDID_CLK_CONN

USB20_P5

DMIC_DATA

USB20_N5

DMIC_CLK

1

R828
0_0402_5%
R824
0_0402_5%

EC_INVT_PWM
PCH_PWM

<42>

<17>

+3VS

R823
2.2K_0402_5%

2

3
D52
@

D55
@

1

1

2

1

2

PJDLC05_SOT23-3

@
INVPWM

2

PJDLC05_SOT23-3

3

ACES_87142-3041-BS

R826
2.2K_0402_5%

ESD request

<17> EDID_CLK

EDID_CLK

R1199 1

2

0_0402_5%

EDID_CLK_CONN

<17> EDID_DATA

EDID_DATA

R1200 1

2

0_0402_5%

EDID_DATA_CONN

C

C

1

2

DISPOFF#

DMIC_CLK

1

RB751V-40 SOD-323
@

1

R890
10K_0402_5%

2

2
+LCDVDD

2

IN

2

3

2
1

B

2

1

2

C530

AO3413_SOT23-3
Q68

W=60mils

0.1U_0402_16V4Z
+LCDVDD
1

Q69
DTC124EKAT146_SC59-3

CMOS Camera

+LCDVDD_CONN

L15

(40 MIL)

2
Q94

FBMA-L11-201209-221LMA30T_0805
C531

1

2

2

(40 MIL)

C532
0.1U_0402_16V4Z

+3VALW

2

4.7U_0805_10V4Z

3

+3VS

@

1

<42> CMOS_ON#
R435
150K_0402_5%
CMOS@

A

+CMOS_PW_R

1

CMOS@

R432
+CMOS_PW
0_0603_5%
1
2
CMOS@
1
1
CMOS@
CMOS@
C518
C519
0.1U_0402_16V4Z
10U_0603_6.3V6M
2
2

@

11/07 Change type to 0603

2
1

2

CMOS@
C520
0.1U_0402_16V4Z
A

Compal Secret Data

Security Classification
Issued Date

AO3413_SOT23-3

G

1

C521
0.1U_0402_16V4Z

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

<42>

2

D

R821
100K_0402_5%

220K_0402_5%

ENBKL

R827
100K_0402_1%

S

3

1

<17> PCH_ENVDD

GND

OUT

1

3

DTC124EK

R820
1

0_0402_5%

C529
4.7U_0805_10V4Z

2

LCD_ENVDD#

2

W=60mils
1

1

2

1
2
G

S

For EMI

@

G

D
Q67
2N7002_SOT23

R817
100K_0402_5%

D

R816
150_0603_1%

S

1

+3VS

B

R1201 1

<17> PCH_ENBKL

+5VALW

2

For EMI

100P_0402_50V8J

2

BKOFF#

BKOFF#

2

DISPOFF#
1 @
C527

@
R822
4.7K_0402_5%

D30
<42>

C525
1 @

C934

1

+3VS

R891 1
2
0_0402_5%

470P_0402_50V7K

470P_0402_50V7K

INVPWM

4

3

2

Title

Compal Electronics, Inc.
LVDS/CAMERA

Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P
Sheet

Monday, January 16, 2012
1

33

of

64

A

B

C

+5VS

+5VS

3

3

D

+5VS

3

BLUE

1

GREEN

1

2

E

BAT54S-7-F_SOT23-3

2

@
D31
BAT54S-7-F_SOT23-3

RED

1

2
@
D32
BAT54S-7-F_SOT23-3

@
D33

1

CRT Connector

+CRT_VCC

+5VS
D36

2

1

+CRT_VCC_CONN

2
1

RB491D_SC59-3
1.1A_6V_SMD1812P110TF
DAC_RED

<17> DAC_RED

DAC_GRN

<17> DAC_GRN

1

1

1

DAC_BLU

<17> DAC_BLU

1
R832
150_0402_1%

1
C537

C538

2

2

R831
150_0402_1%

2

2

R830
150_0402_1%

2

2

C539
10P_0402_50V8J

10P_0402_50V8J 10P_0402_50V8J

CLOSE TO CONN

W=40mils

FCM1608CF-121T03 0603
1
2
L16
FCM1608CF-121T03 0603
1
2
L17
FCM1608CF-121T03 0603
1
2
L18
1
1

2

GREEN
JCRT1
BLUE

1

C540

2

T75
PAD
RED

1
C542

2

2

C541
10P_0402_50V8J

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

CRT_TEST

CRT_DDC_DAT_CONN
GREEN
JVGA_HS
BLUE

10P_0402_50V8J10P_0402_50V8J

CRT_DDC_CLK_CONN
2

1

R833

1

2

Y

CRT_HSYNC_1

4

1

3

JVGA_HS

2
L19

U24
SN74AHCT1G125DCKR_SC70-5

+CRT_VCC

1

2

R834

1

@
C545
10P_0402_50V8J

D8
JVGA_VS

P

CRT_DDC_CLK_CONN

1

G

2
FCM1608CF-121T03 0603 A

OE#

5

2

Y

CRT_VSYNC_1

4

1

JVGA_HS

2

GND

VDD

5

+5VS

1

I/O1

I/O3

4

CRT_DDC_DAT_CONN

2

3

3

1

1

@ C547
10P_0402_50V8J

2

R838
2.2K_0402_5%

2

2

5

R837
2.2K_0402_5%

4

AZC099-04S.R7G_SOT23-6

1

+CRT_VCC

1

1
2

6

JVGA_VS

2

+3VS

CRT_DDC_DATA

I/O4

L20

U25
SN74AHCT1G125DCKR_SC70-5

+3VS

<17> CRT_DDC_DATA

I/O2

1K_0402_5%

C546
0.1U_0402_16V4Z

R836
2.2K_0402_5%

@

3

2

1

R835
2.2K_0402_5%

2

TYCO_1775763-1
ME@

1

5
P
A

OE#

2

G

CRT_HSYNC

CRT_VSYNC

16
17

2

FCM1608CF-121T03 0603

<17> CRT_VSYNC

100P_0402_50V8J

G
G

1K_0402_5%

C544
0.1U_0402_16V4Z

3

C543

2

1

<17> CRT_HSYNC

C536
0.1U_0402_16V4Z

RED

JVGA_VS

+CRT_VCC

1

F1

1

CRT_DDC_DAT_CONN

3

2

DMN66D0LDW -7 2N_SOT363-6
Q73B
<17> CRT_DDC_CLK

CRT_DDC_CLK

1

CRT_DDC_CLK_CONN
1
@
C549
68P_0402_50V8K
2

6

DMN66D0LDW -7 2N_SOT363-6
Q73A

@
C548
100P_0402_50V8J

1

2

4

4

Compal Secret Data

Security Classification
2011/07/21

Issued Date

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Compal Electronics, Inc.
CRT Connector

Size
Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
E

34

of

64

5

4

3

2

1

L23
HDMI_CLK+_CK
HDMI_CLK-_CK

1
4

1

2

4

3

2
3

HDMI_CLK+_CONN

1
C1016

HDMI_CLK-_CONN

1
C1015

HDMI@
W CM-2012-900T_4P

2
3.3P_0402_50V8C
@

2
3.3P_0402_50V8C

@

L24
HDMI_TX0+_CK

1

HDMI_TX0-_CK

4

HDMI_TX1+_CK

1

D

1

2

2

4
3 3
HDMI@
W CM-2012-900T_4P

HDMI_TX0+_CONN

1
C1018

HDMI_TX0-_CONN

1
C1017

HDMI_TX1+_CONN

1
C1020

<17>
<17>
<17>
<17>
<17>
<17>
<17>
<17>

2
3.3P_0402_50V8C
@

2
3.3P_0402_50V8C

@

L26

HDMI_TX1-_CK

4

1

2

2

4
3 3
HDMI@
W CM-2012-900T_4P

HDMI_TX1-_CONN

1
C1019

HDMI_CLK+_CK
HDMI_CLK-_CK
HDMI_TX0+_CK
HDMI_TX0-_CK
HDMI_TX1+_CK
HDMI_TX1-_CK
HDMI_TX2+_CK
HDMI_TX2-_CK

HDMI_CLK+_CK
HDMI_CLK-_CK
HDMI_TX0+_CK
HDMI_TX0-_CK
HDMI_TX1+_CK
HDMI_TX1-_CK
HDMI_TX2+_CK
HDMI_TX2-_CK

R865
R866
R867
R868
R869
R870
R871
R872

@
@
@
@
@
@
@
@

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

HDMI_CLK+_CONN
HDMI_CLK-_CONN
HDMI_TX0+_CONN
HDMI_TX0-_CONN
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI_TX2+_CONN
HDMI_TX2-_CONN

D

2
3.3P_0402_50V8C
@

2
3.3P_0402_50V8C

@

L27

1

HDMI_TX2-_CK

4

1

2

2

HDMI_TX2+_CONN

1
C1022

3

HDMI_TX2-_CONN

1
C1021

4
3
HDMI@
W CM-2012-900T_4P

2
3.3P_0402_50V8C
@

2
3.3P_0402_50V8C

+3VS

@

2

HDMI_TX2+_CK

HDMICLK

HDMI@
6

1

C

RP5
HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_TX1-_CONN
HDMI_TX1+_CONN

1
2
3
4

HDMIDAT

<17> HDMIDAT

HDMICLK_R

DMN66D0LDW -7 2N_SOT363-6
Q80A
HDMI@
3

5

<17> HDMICLK

4

C

HDMIDAT_R

DMN66D0LDW -7 2N_SOT363-6

8
7
6
5

Q80B
+5VS

2

680_8P4R_5%
HDMI@
RP6

1
3

R857
0_0805_5%

D

2
G
S

Q114
2N7002H 1N_SOT23-3
HDMI@

@

2

1

HDMI@
D37
RB491D_SC59-3

680_8P4R_5%
HDMI@
+3VS

+5VS_HDMI_F

8
7
6
5

F2
1.1A_6V_SMD1812P110TF

+5VS
+3VS

3

1 @
2
R1142 100K_0402_5%

1 C561
0.1U_0402_16V4Z
HDMI@

2

2
1

D

S

2N7002_SOT23

R860
2.2K_0402_5%
HDMI@

1

@
D38
BAT54S-7-F_SOT23-3

B

2

R861
2.2K_0402_5%
HDMI@

2

2

1

G

3

<17> TMDS_B_HPD

Q85
HDMI@
1 HDMI_DET_UMA

1

2

+5VS_HDMI

R859
1M_0402_5%
HDMI@

B

HDMI@

1

1
2
3
4

2

HDMI_TX0-_CONN
HDMI_TX0+_CONN
HDMI_TX2-_CONN
HDMI_TX2+_CONN

R864
20K_0402_5%
HDMI@

JHDMI1

1

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HDMIDAT_R
HDMICLK_R

HDMI_CLK+_CONN
HDMI_TX0-_CONN

2

3

HDMI_CLK-_CONN
HDMIDAT_R
HDMICLK_R

D57
PJSOT24C 3P C/A SOT-23
@

HDMI_TX0+_CONN
HDMI_TX1-_CONN

1

HDMI_TX1+_CONN
HDMI_TX2-_CONN
HDMI_TX2+_CONN

A

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKG1
CK_shield
G2
CK+
G3
D0G4
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

A

SUYIN_100042GR019M23DZL
ME@

Compal Electronics,Ltd.

Compal Secret Data

Security Classification
2011/07/21

Issued Date

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HDMI CONN
Size
Document Number
Custom

Rev
1.0

QIWY3 LA-8001P

Date: Monday, January 16, 2012

Sheet
1

35

of

64

A

B

C

+3VS

Mini-Express Card for WLAN/WiMAX(Half)
Mini-Express Card for SSD(Full)

J3
1

1

D

E

+3VS_WLAN
2

2
1

@

JUMP_43X79
2

1
C563
0.1U_0402_16V4Z

Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.

@
C570
10U_0603_6.3V6M

2

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB

11/08 Reserve
+1.5VS

contact to +3VS_WLAN for AOAC function

+1.5VS

+3VS_WLAN_AOAC

Mini-Express Card(WLAN/WiMAX)

1

R897 1

<19> BT_DISABLE

2
2

0_0402_5%

<15> WLAN_CLKREQ1#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2 @ 0_0402_5%

<15> CLK_PCIE_WLAN1#
<15> CLK_PCIE_WLAN1
PCI_RST#_R
CLK_PCI_DB
<15> PCIE_PRX_DTX_N2
<15> PCIE_PRX_DTX_P2
<15> PCIE_PTX_C_DRX_N2
<15> PCIE_PTX_C_DRX_P2
+3VS_WLAN

EC_TX
EC_RX

EC_TX
EC_RX

1
1

100_0402_1%
R887
2
2
R888
100_0402_1%

For EC to detect
debug card insert.

2

53

WAKE#
3.3V
NC
GND
NC
1.5V
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
NC
NC
GND
NC
NC
GND
PERST#
PERn0
+3.3Vaux
PERp0
GND
GND
+1.5V
GND
SMB_CLK
PETn0
SMB_DATA
PETp0
GND
GND
USB_DNC
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V
GND

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

R880 1
R881 1
R882 1

0_0402_5%
WL_RST#
2 @ 0_0402_5%
0_0402_5%
2

R883 1
R884 1

2 @ 0_0402_5%
2 @ 0_0402_5%

2

USB20_N10
USB20_P10

PCH_WL_OFF#
+3VALW
+3VS_WLAN_AOAC

R889
100K_0402_5%

C564
0.1U_0402_16V4Z

2

PLT_RST# <18,23,37,42,46>

SMB_CLK_S3 <12,13,15>
SMB_DATA_S3 <12,13,15>

+3VS_WLAN

+3VS_WLAN_AOAC

54
R267

1 0_0603_5%

2

+3VALW

ME@

Q104

AO3413_SOT23-3
D

S

1

1

2

1

2

G

2

2

2

@
C569

100_0402_1%
2 @
2 @
100_0402_1%

53

3

0.01U_0402_16V7K
SATA_DTX_C_IRX_P0 2
1 C572 SATA_DTX_IRX_P0
SATA_DTX_C_IRX_N0 2
1 C573 SATA_DTX_IRX_N0

<14> SATA_DTX_C_IRX_P0
<14> SATA_DTX_C_IRX_N0
<14> SATA_ITX_DRX_N0
<14> SATA_ITX_DRX_P0

0.01U_0402_16V7K
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
+3VS_SSD

<42,43>
<42,43>

EC_TX
EC_RX

EC_TX
EC_RX

R893 1
1
R894

2

JP3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

11/07 Change type to 0603

1

2

JUMP_43X79
@

2

10U_0603_6.3V6M

2

2

AOAC@
C526
0.1U_0402_16V4Z

J5
1

0.01U_0402_25V7K

1

AOAC@
C533
0.1U_0402_16V4Z

+3VS_SSD

+3VS

1

1

C565
0.1U_0402_16V4Z

<18>
2
1 PLT_RST#
0_0402_5% R1343

3

10U_0603_6.3V6M

C568

<18>

SSD Active:4.5W(1.5A)

+3VS_SSD

1

CLK_PCI_DB

9/18 Increase for Intel AOAC function

Mini-Express Card(SSD)

C567

LPC_FRAME# <14,42>
LPC_AD3 <14,42>
LPC_AD2 <14,42>
LPC_AD1 <14,42>
LPC_AD0 <14,42>

<18>
<18>

AOAC@

1

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R

R436
150K_0402_5%

C566

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

1

AOAC@

1

2
2
2
2
2
2

+1.5VS_WLAN

<42> AOAC_ON#

0.1U_0402_16V4Z

@
@
@
@
@
@

TAITW_PFPET0-AFGLBG1ZZ4N0

2

<42,43>
<42,43>

2

2

PCIE_WAKE#
BT_ACTIVE
R877 1
BT_DISABLE_R
WLAN_CLKREQ1#

PCIE_WAKE#
<44> BT_ACTIVE

0_0402_5%

1

R289
0_0603_5%
JP1

<16,19,37>

@
R892 1

<19,44> PCH_BT_ON#

1
1
1
1
1
1

1

9/18 JP1 Pin2,24,52

R873
R874
R875
R876
R878
R879

WAKE#
3.3V
NC
GND
NC
1.5V
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
NC
NC
GND
NC
NC
GND
PERST#
PERn0
+3.3Vaux
PERp0
GND
GND
+1.5V
GND
SMB_CLK
PETn0
SMB_DATA
PETp0
GND
GND
USB_DNC
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V
GND

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

3

54

TAITW_PFPET0-AFGLBG1ZZ4N0
<14> SATA_DET#

SATA_DET#
ME@

For SSD use:

4

4

Compal Secret Data

Security Classification

Issued Date

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Mini-Card
Size

B

C

D

Document Number

Rev
1.0

QIWY3 LA-8001P
Date:

A

Compal Electronics, Inc.

Sheet

Monday, January 16, 2012
E

36

of

64

R145

2

G

2

Note: Place Close to LAN chip
L39 DCR< 0.15 ohm
Rate current > 1A

+1.1_AVDDL_L

1

11/07 Change type to 0603

2
10K_0402_5%

1

C976
0.1U_0402_16V7K

1

2

Close to
Pin40

Layout Notice : Place as close
chip as possible.

11/08 Increase for LAN S5 power saving

R1357,R1372,L76
L76

FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
+1.1_AVDDL
+1.1_DVDDL
1
2
1
2

C967

<42> LAN_PWR_ON#

Q150

2

2

R1356,C955

L75

1

2

C278

1

1

AR8161

Configure

1

2

4.7U_0603_6.3V6K

D

S

3
D

1

10U_0603_6.3V6M

R1357 8161@ 0_0402_5%
+1.1_DVDDL 1
2

C936

JUMP_43X79

AR8151

L74
1
2 +LX
4.7UH_SIA4012-4R7M_20%

+LX_R

C980

+1.7_VDDCT
R1356 8151@ 0_0402_5%
1
2

2

2

0.1U_0402_16V4Z
C937

1

AO3413_SOT23

LAN_PWR_ON#

LX Voltage

+1.7V

+1.1V


Close together

J18

1

1

+LX

+3V_LAN

@

+3VALW

2

1U_0402_6.3V4Z

3

0.1U_0402_16V4Z

4

@ C935
1000P_0402_50V7K

5

D

8161@

Place close to Pin34

Vendor recommand reseve the
PU resistor close LAN chip
R345 1

+3V_LAN

2 4.7K_0402_5%
@
PLT_RST#

36

RX_N

<15> PCIE_PTX_C_DRX_P1

35

RX_P

<15> CLK_PCIE_LAN#
<15> CLK_PCIE_LAN

32
33

REFCLK_N
REFCLK_P

VDD33

1

+3V_LAN

Near
Pin19

Near
Pin31

<15> PCH_LAN_48M

C959

2

1

2

0.1U_0402_16V4Z

2

1

1U_0402_6.3V4Z
C960

C958

1

0.1U_0402_16V4Z

C957

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Near
Pin13

1

DVDDL/PPS
DVDDL_REG/DVDDL

24
37

+1.1_DVDDL_R R1366 1

AVDDH/AVDD33
AVDDH
AVDDH_REG

16
22
9

CLKREQ#
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG/AVDDL

41

GND

+1.1_DVDDL

Near
Pin6

1

2

Near
Pin9

SA00003LE20
8151@
3.3P_0402_50V8
2

2 0_0402_5% +1.1_DVDDL

1

2

2

1

2

1

2

1

2

MDI2MDI3+
MDI3-

Note

4

NC

1

OSC

OSC

3

NC

2

2

C968

9/20 For Crystal EA request

11/07 Change type to 0603

1

2

1

2

1

2

2

1

1@

2 C942 1000P_0402_50V7K
8151@
2 C943 0.1U_0402_16V4Z

1
1@

2 C944 1000P_0402_50V7K
8151@
2 C945 0.1U_0402_16V4Z

1

: C938, C940, C942, 944, reserved for EMI.

Near
Pin22

Near
Pin37

B

+3V_LAN
8151@

+2.7_AVDDH

8161@
R1367 1

2 0_0402_5%
8151@

+AVDDH_AVDD3.3

Near
Pin24

R1368 1

1

2

1

2

2 0_0402_5%

+2.7_AVDDH

8161@

For AR8151: Stuff R1368 for +AVDD3.3
For AR8161: Stuff R1367,C949 for +AVDDH

2011/07/21

3

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

2 C940 1000P_0402_50V7K
8151@
2 C941 0.1U_0402_16V4Z

1

For AR8151: Stuff 49.9K and 0.1u
For AR8161: NC

For AR8151: Stuff C966,R1366
For AR8161: NC

Issued Date

5

1@

Place close to Pin16

1 25MHZ_12PF_X3G025000DC1H~D 1

2

2 C938 1000P_0402_50V7K
8151@
2 C939 0.1U_0402_16V4Z

1

LAN_XTALO

Y6

@

1@

8151@

LAN_XTALI

Place Close to C968
33P_0402_50V8J

+3VS

+AVDDH_AVDD3.3
+2.7_AVDDH
+2.7_AVDDH

U63

8161@

R1372 8161@ 30K_0402_5%
1
2
8151@
1
2
C955 0.1U_0402_16V4Z

+LX

1

@

+1.7_VDDCT

@

C954

40
5

LX

13
19
31
34
6

MDI2+

+LX

XTLO
XTLI

A

MDI1-

Place Close to PIN1

AR8161-AL3A-R_QFN40_5X5

C981
1

+3V_LAN

1
2
R1371 2.37K_0402_1%

8151@ 49.9_0402_1%
R1358 1
2
8151@ 49.9_0402_1%
R1359 1
2
8151@ 49.9_0402_1%
R1360 1
2
8151@ 49.9_0402_1%
R1361 1
2
8151@ 49.9_0402_1%
R1362 1
2
8151@ 49.9_0402_1%
R1363 1
2
8151@ 49.9_0402_1%
R1364 1
2
8151@ 49.9_0402_1%
R1365 1
2

C948

4
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL_L
+1.1_AVDDL

C956

NC
TESTMODE

MDI1+

VDDCT/ISOLAN

B

2

28
27
7
8

<15> CLKREQ_LAN#

1

10

C953
10U_0603_6.3V6M

LAN_XTALO
LAN_XTALI

@
2 4.7K_0402_5%

RBIAS

MDI0-

Place Close to PIN1

C952
10U_0603_6.3V6M

R344 1

SMCLK
SMDATA

MDI0+

C951
1U_0402_6.3V4Z

+3V_LAN

W AKE#

25
26

Place Close to LAN chip

C950
0.1U_0402_16V4Z

@

Vendor recommand reseve the
PU resistor close LAN chip

LAN_RBIAS

3

<38>
<38>
<38>
<38>
<38>
<38>
<38>
<38>

1000P_0402_50V7K
1
2

R343 1 BOM Structure
2 4.7K_0402_5%
= CD4@

MDI0MDI0+
MDI1MDI1+
MDI2MDI2+
MDI3MDI3+

C966

+3V_LAN

MDI0MDI0+
MDI1MDI1+
MDI2MDI2+
MDI3MDI3+

0.1U_0402_16V4Z

<16,19,36> PCIE_WAKE#
<42> LAN_WAKE#

PCIE_WAKE#_R

2 0_0402_5%
2 0_0402_5%

12
11
15
14
18
17
21
20

C961

R1369 1
R1370 1

PERST#

TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3

C

ACTIVITY <38>
LAN_LINK# <38>

1U_0402_6.3V4Z

2

ACTIVITY
LAN_LINK#

0.1U_0402_16V4Z
C962

PLT_RST#
@

38
39
23

C949

AR8151/AR8161

<15> PCIE_PTX_C_DRX_N1

LED_0
LED_1
LED_2

1U_0402_6.3V4Z

Atheros

TX_P

0.1U_0402_16V4Z

TX_N

C964

PCIE_PRX_C_DTX_P1 30

0.1U_0402_16V4Z
C965

PCIE_PRX_C_DTX_N1 29

2 0.1U_0402_16V7K

C963

2 0.1U_0402_16V7K

C947 1

H --> Overclocking mode
L --> Not overclocking mode

1
10K_0402_5%

0.1U_0402_16V4Z

C946 1

<15> PCIE_PRX_DTX_P1

1U_0402_6.3V4Z

<15> PCIE_PRX_DTX_N1

C969

C

@

2
R31

U63

Place Close to Chip

33P_0402_50V8J

<18,23,36,42,46> PLT_RST#

2

Title

LAN-AR8151/8161
Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
1

37

of

64

5

4

C970

3

C972

0.1U_0402_16V4Z
8161S@

C974

0.1U_0402_16V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z

8161S@

2

8161S@

11/25 Change

8161S@

T1,T2 P/N to SP050007K00

+1.7_VDDCT

T76

D

8151@

2

R1373
2

1

C975

C970
0.1U_0402_16V4Z

8151@

1
0_0603_5%
C971
8151@

1U_0402_6.3V4Z

<37>
<37>

MDI3+
MDI3-

<37>
<37>

MDI2+
MDI2-

MDI3+
MDI3-

1
1
1
8151@

2

C972
0.1U_0402_16V4Z

2

MDI2+
MDI2-

1
2
3
4
5
6
7
8

TD+
TDCT
NC
NC
CT
RD+
RD-

D

TX+
TXCT
NC
NC
CT
RX+
RX-

16
15
14
13
12
11
10
9

MDO3+
MDO3MCT3
MCT2
MDO2+
MDO2-

R1374
2
1
0_0402_5%
R1375
2
1
0_0402_5%

11/20 For LAN SURGE CO-LAY

BOTHHAND_NS0013LF
1 R90

6/23 update

2

75_0603_5%
T77
2
8151@

Place Close to T76

<37>
<37>

MDI0+
MDI0-

<37>
<37>

MDI1+
MDI1-

MDI0+
MDI0-

1

MDI3C

C974
0.1U_0402_16V4Z

1

MDI3+
D68

8151@

C975
0.1U_0402_16V4Z

2

TCLAMP3302N.TCT_SLP2626P10-10

MDI1+
MDI1-

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9

MDO0+
MDO0-

R1376
2
1
0_0402_5%
R1377
2
1
0_0402_5%

MCT0
MCT1
MDO1+
MDO1-

C

6
7
8
9
10
6
7
8
9
10

R02

GND

MCT0

MDO2+

4

PR3+

MDO2-

5

PR3-

MDO1-

6

PR2-

MDO3+

7

PR4+

G2

14

MDO3-

8

PR4-

G1

13

2

D67

2

R02
ACTIVITY

<37> ACTIVITY

2

1 220_0402_5%

12

1

R1442
+3V_LAN 2

2

2

5
4
3
2
1

@
@
C979
470P_0402_50V7K

5
4
3
2
1

R1379

11

1

0_0402_5%

MDI0-

R1446

GND

220_0402_5%
1

SURGE@

Yellow LEDYellow LED+

@

@

@

B

SANTA_130452-D

@

1

6
7
8
9
10

R1448

0_0402_5%

6
7
8
9
10

TCLAMP3302N.TCT_SLP2626P10-10

2

PR2+

1

3

LSE-200NX3216TRLF_1206-2

MCT1

MDO1+

LSE-200NX3216TRLF_1206-2
F5

MCT2

PR1-

2

PR1+

2

1

1

MDO0-

MDI1MDI1+

Place Close to T76,T77

LSE-200NX3216TRLF_1206-2
F4

B

MCT3

2

Place Close to T77

Green LED+

MDO0+

F3

2

8151S@

Green LED-

10
1 0_0402_5%

1

MDI2+

JRJ1
9

LSE-200NX3216TRLF_1206-2

@
C978
470P_0402_50V7K

1

F6

MDI2-

220_0402_5%
2
1
R1380
+3V_LAN R1378 2

LAN_LINK#

1

5
4
3
2
1

11/20 Atheros request
<37> LAN_LINK#

11

TX+
TXCT
NC
NC
CT
RX+
RX-

2

C973
10P_0603_50V8-J

BOTHHAND_NS0013LF

5
4
3
2
1

11

TD+
TDCT
NC
NC
CT
RD+
RD-

1

Reserve for EMI go rural solution

ME@

MDI0+
8151S@

A

A

Reserve D67,D68 for EMI go rural solution
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/07/21

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

LAN_Transformer
Size
B
Date:

Document Number

Rev
1.0

QIWY3 LA-8001P
Monday, January 16, 2012

Sheet
1

38

of

64

5

4

2

1

1403@

1403:
@C982/@C984=100p

EC_SMB_CK2

<15,23,42> EC_SMB_CK2

FAN_PW M
SHDN_SEL

C443
0.1U_0402_16V4Z

@
C982
100P_0402_50V8J

Close U20
REMOTE1+
1403@
C449
2200P_0402_50V7K

2103@
1
2
R622
0_0402_5%
2103@
1
2
R623
0_0402_5%

REMOTE2+

1
REMOTE2-

2

TACH

EC_SMB_DA2 <15,23,42>

TRIP_SET

Close to SSD side

REMOTE2+
REMOTE2+
@
C984
100P_0402_50V8J

R439
1.5K_0402_1%
@

1

C
Q138
MMST3904-7-F_SOT323-3

2
B
2

E

REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"

C

REMOTE1+

B

+3VS

FAN1 Conn

1
REMOTE2-

R624
10K_0402_5%
@
U29
+VDD

Shutdown
Temp
93
94
95
96
97
98
99
100
101
102
103
104
105

1

REMOTE2-

TRIP_SET
R1387(1%)
953ohm
1020ohm
1100ohm
1150ohm
1240ohm
1330ohm
1400ohm
1500ohm
1580ohm
1690ohm
1820ohm
1960ohm
2050ohm
5

1

1403@

2

2

E

REMOTE1-

1
C658
2200P_0402_50V7K

Q137
MMST3904-7-F_SOT323-3

2
B
2

REMOTE1-

REMOTE2+

B

C

REMOTE1EC_SMB_DA2

internal pull up 1.2K to 1.5V
R for initial thermal
shutdown temp

C

1

ALERT#

EMC2103-2-AP-TR_QFN16_4X4

FAN_PWM & TACH
Address 0101_110xb
for PWM FAN

Under VRAM

REMOTE1+

1

1

2103@
R441
10K_0402_5%

3

DN1
DP1
VDD
GPIO1
GPIO2
ALERT#
SYS_SHDN# SMDATA
SMCLK
TACH
PWM
GND
SHDN_SEL TRIP_SET
DN2 / DP3
DP2 / DN3
GPAD

2
4
6
8
10
12
14
16
17

REMOTE2-

A

2103@
R461
10K_0402_5%

D

1

+VDD

2103@

+3VS

2

U20

1
3
5
7
9
11
13
15

+3VS

2

1

R440
10K_0402_5%
@

SMSC thermal sensor
placed near by VRAM

2

2103@
R462
10K_0402_5%

2

2
2

+3VS

1

2103@
2103@
R460
10K_0402_5%
R459
6.8K_0402_5%

2

1

1

2103@
R431
68_0402_5%

+3VS

2

+3VS

1

+3VS

1

+3VS

2

D

1

0_0402_5%

3

R431

3

+5VS

VDD

SMCLK

DP1

SMDATA

9

R309

EC_SMB_CK2

10

1

REMOTE1+

2

REMOTE1-

3

DN1

ALERT#

8

REMOTE2+

4

DP2

THERM#

7

REMOTE2-

5

DN2

GND

6

EC_SMB_DA2

2

2

ALERT#

11/07 Change type to 0603

JP22

0_0603_5%
C986
10U_0603_6.3V6M
1
<42> EC_TACH
<42> EC_FAN_PW M

EMC1403-2-AIZL-TR_MSOP10

1
2
3
4
5
6

1
2
3
4
G5
G6

ACES_85205-04001
ME@

Address 1001_101xb
A

Compal Electronics,Ltd.

Compal Secret Data

Security Classification
2011/07/21

Issued Date

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Title

EMC1403/2103_Thermal sensor/FAN
Size
Document Number
Custom
Date: Monday, January 16, 2012

Rev
1.0

QIWY3 LA-8001P
Sheet
1

39

of

64

A

B

C

D

E

F

G

H

1

1

SATA HDD Conn.
JHDD1
2

SATA_ITX_DRX_P1
SATA_ITX_DRX_N1

<14> SATA_ITX_DRX_P1
<14> SATA_ITX_DRX_N1
<14> SATA_DTX_C_IRX_N1
<14> SATA_DTX_C_IRX_P1

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1

C627 1
C628 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_IRX_N1
SATA_DTX_IRX_P1

1
2
3
4
5
6
7

2

GND
A+
AGND
BB+
GND

SATA ODD Conn.
JODD1

@
+3VS

1

J13

1

2

2

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS_HDD

JUMP_43X79

+5VS

1

@

J12

1

2

2

+5VS_HDD

JUMP_43X79

+5VS

+3VS

1

2

1
C631
1000P_0402_50V7K

2

1
C632
0.1U_0402_16V4Z

2

1
C633
1U_0603_10V4Z

2

1
C634
10U_0603_6.3V6M

2

1
C635
10U_0603_6.3V6M

2

@
C636
0.1U_0402_16V4Z

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
G1
VCC12
G2
VCC12

SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2

<14> SATA_DTX_C_IRX_N2
<14> SATA_DTX_C_IRX_P2

C629 1
C630 1

1
2
3
4
5
6
7

GND
RX+
RXGND
TXTX+
GND

8
9
10
11
12
13

DP
+5V
+5V
MD
GND
GND

SATA_ITX_DRX_P2_CONN
SATA_ITX_DRX_N2_CONN

<14> SATA_ITX_DRX_P2_CONN
<14> SATA_ITX_DRX_N2_CONN
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_IRX_N2
SATA_DTX_IRX_P2
@

+3VS

R921
1

R710 1
2
10K_0402_5%

ODD_DA#

<18,42> ODD_DA#

2 0_0402_5%

+5V_ODD
1
R922

2
0_0402_5%

23
24

GND1
GND2

14
15

TYCO_2-1759838-8~D
ME@

FOX_LD2822F-SAQL6
ME@

ODD Power Control

3

11/07 Change type to 0603

@
1
+5VS

1

J6
2

2

JUMP_43X79

+5VALW

3

+5V_ODD

Q88
D

S

1

1

3

1

AO3413_SOT23-3
2

G

R923
10K_0402_5%

2
1

2
2

ODD_EN

IN

3

<19>

GND

OUT

1

R1110
1

C638 0.1U_0402_10V7K
1
2

2

C637
0.1U_0402_16V4Z

2

200K_0402_5%

C639
10U_0603_6.3V6M

11/07 Change type to 0603
11/07 Change for soft star

Q89
DTC124EKAT146_SC59-3

4

4

Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Compal Electronics, Inc.

Compal Secret Data

Security Classification

E

F

Title

HDD/ODD Connector
Size
B

Document Number

Rev
1.0

QIWY3 LA-8001P
Monday, January 16, 2012

Date:
G

Sheet

40
H

of

64

3

2

R1355

R70
0_0805_5%
2

<14> HDA_SDOUT_AUDIO

+3VS
2

<14> HDA_SDIN0

R341
4.7K_0402_5%
@
1

1 SDATA_IN
R938

8

1

12
2

JDREF

1
R942

19

2

20
2

<46>

MIC_JD

<46>

PLUG_IN

20K_0402_1%
2

2
2.2U_0603_6.3V6K

Capless HP Sense
R940 place near pin34

2
2.2U_0603_6.3V6K
2
4.7U_0603_6.3V6K
EAPD

1
R9451
R481

11/11 Reserve for MUTE_LED issue

SENSEA

1
R939
1
R940

39.2K_0402_1%

MIC Sense
R939 place near pin13

C654

0.1U_0402_16V4Z
C655

C293

C648

4.7U_0603_6.3V6K

13
18

1
C666
1
C673
1
C291

CBN

35

CBP

36
34
28

LINE1-L(PORT-C-L)

SDATA-OUT

MIC1-R(PORT-B-R)

BIT-CLK

MIC1-L(PORT-B-L)

SDATA-IN

MIC2-R(PORT-F-R)

SYNC

LINE2-R(PORT-E-R)

RESET#

LINE2-L(PORT-E-L)

29
30
31

+MIC1_VREFO_L

42
43
7

Vendor recommend. 2.2u

24

1

1
2

Vendor recommend. 2.2K

R930
2.2K_0402_5%
1

LINE1-R(PORT-C-R)

PD#

2

9
DVDD-IO

DVDD1

1

38
AVDD2

25

DAPD/COMB_JACK

12/26 modify for MIC R/L reverse issue
23
22

MIC_EXTR_C

21

MIC_EXTL_C

C675
2

2.2U_0603_6.3V6K
1

2

1
1K_0402_5%
1
1K_0402_5%

R933
2

1

2
R935

C689

17

EXT_MIC_R <46>

external MIC

EXT_MIC_L <46>

2.2U_0603_6.3V6K

16
15
14

PCBEEP
SPK-OUT-L+
JDREF
SPK-OUT-LMONO-OUT(PORT-H)
SPK-OUT-RSense A
SPK-OUT-R+

40

SPK_L2+

41

SPK_L1-

44

SPK_R1-

12/26 modify for MIC R/L reverse issue
C

Internal Speaker

SPK_R2+

45

12/26 modify for HP R/L reverse issue

Sense-B
CBN

HPOUT-R(PORT-A-R)

CBP

HPOUT-L(PORT-A-L)

CPVEE

SPDIF-OUT

LDO-CAP
GPIO1/DMIC-CLK

2
2 0_0402_5%
10K_0402_5%

2

2
4

11

PC_BEEP

D22

R931
2.2K_0402_5%

MIC2-L(PORT-F-L)

20K_0402_1%

D

D23

1

47

10

R331
4.7K_0402_5%
@

11/07 Change type to 0603

RB751V_SOD323

5

HDA_RST_AUDIO#

C

@

2

+MIC1_VREFO_L

RB751V_SOD323

PVDD1
EAPD_R
0_0402_5%
EC_MUTE#_R
2
0_0402_5%
2

<14> HDA_SYNC_AUDIO

<14> HDA_RST_AUDIO#

P/N: SM01000DI00

Place near Pin9

+IOVDD_CODEC

6

HDA_SDIN0
2
22_0402_5%

2

1

+3VDD_CODEC

AVDD1

2

46

1

39

2

PVDD2

1

HDA_BITCLK_AUDIO

<14> HDA_BITCLK_AUDIO

@

1

MIC2-VREFO

GPIO0/DMIC-DATA

33

HPOUT_R

32

HPOUT_L

48

75_0402_5%
SPDIF
1
FBMA-10-100505-301T_2P

2

1

2

1

75_0402_5%

3
2

R936

DMIC_CLK_R
1
FBMA-10-100505-301T_2P
DMIC_DATA_R
2
0_0402_5%

R934
2

HP_OUTR

<46>

HP_OUTL

<46>

SPDIF_OUT

R932

<46>

Headphone
SPDIF

9/23 EMI Request
2

DMIC_CLK

R937
1
R944

<33>

DMIC_DATA

<33>

MIC1-VREFO-R
MIC1-VREFO-L
PVSS1

VREF

PVSS2

AVSS1

DVSS

AVSS2
Thermal PAD

Place next to pin 27

27
26
37
49

1

2

1

C659

EAPD
EC_MUTE#

2

Place near Pin1

1U_0603_10V4Z

<42>

1

2

0.1U_0402_16V4Z

C294

1

@

<42>

2

1

Place near Pin38

U8

1
R941
EC_MUTE#
1
R943
HDA_SDOUT_AUDIO

2

R927
2

1
1

+5VS_PVDD
2

Power down (PD#) power stage for save power
0V: Power down power stage
3.3V: Power up power stage

0.1U_0402_16V4Z

C646

0.1U_0402_16V4Z

2

1

Place near Pin25
0.1U_0402_16V4Z
C656

1

+5VS

4.7U_0603_6.3V6K
C657

D

2

C295

4.7U_0805_10V4Z

600ohms @100MHz 2A
P/N: SM01000EE00

2
0_0603_5%

1

+3VDD_CODEC

0_0402_5%

1

C693

+5VDDA_CODEC

L10
1
2
FBMA-L11160808601LMA10T_2P
1

+IOVDD_CODEC

1U_0603_10V4Z

+5VDDA_CODEC

+3VDD_CODEC

C644

+5VS

1

+3VS

10U_0603_6.3V6M

600ohms @100MHz 1A
P/N: SM01000BU00

0.1U_0402_16V4Z

4

C674
0.1U_0402_16V4Z

5

2

ALC269Q-VC2-GR_QFN48_6X6
R946
1

Function

R947
1

SPK-OUT (Pin40/41/44/45)

Internal

Int Speaker

R948
1

Headphone out

R949
1

Mic in

R950
1

Capless HP-OUT (Pin32/33)

External

MIC1(Pin21/22)

JSPK1
SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN

2

@

2

1

2

@

@

2
0_0402_5%

@

2
0_0402_5%

@

2
0_0402_5%

@

2
0_0402_5%

SPK_L1-_CONN

SPK_R2+_CONN

SPK_L2+_CONN

@

1

2

5
6

1
2
3
4
GND1
GND2

HDA_SYNC_AUDIO
HDA_SDOUT_AUDIO
1
R928
1

GND

GNDA

EMI

@

2

1

@

2

1

2

2
@

HDA_BITCLK_AUDIO
27_0402_5%

1
@

2

C1014
33P_0402_50V8J

@

PC Beep

ACES_88231-04001
ME@

EC Beep

<42>

PCH Beep

<14>

BEEP#

HDA_SPKR

1
C619

2
0.1U_0402_16V4Z

1
C612

2PC_BEEP1
0.1U_0402_16V4Z

R492
1
2
33_0402_5%

PC_BEEP

@
R480
10K_0402_5%
2

@

1

1

@
D59
PACDN042Y3R_SOT23-3

A

2

3

3

A

2

1

SPK_R1-_CONN

C681

C680

1

1000P_0402_50V7K

@

1

1000P_0402_50V7K

11/15 For EMI request change to SM010024230

1
2
3
4
C679

0_0805_5%
0_0805_5%
0_0805_5%
0_0805_5%

1000P_0402_50V7K

2
2
2
2

C678

R1280
R1281
R1282
R1283

1000P_0402_50V7K

1
1
1
1

B

HDA_RST_AUDIO#
2
0_0402_5%

R951
1

wide 25MIL
SPK_R1SPK_R2+
SPK_L1SPK_L2+

External

2
0_0402_5%

22P_0402_50V8J
C652

Location

22P_0402_50V8J
C651

Pin Assignment

22P_0402_50V8J
C650

B

D60
PACDN042Y3R_SOT23-3

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification

Reserve for ESD request.

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

HD Audio Codec_ALC269Q-VC
Size
C

Document Number

5

4

3

2

Rev
1.0

QIWY3 LA-8001P

Date: Monday, January 16, 2012

Sheet
1

41

of

64

+3VALW
+EC_VCCA

+3VLP

KSI[0..7]
<43>

KSI[0..7]

+3VALW

@
R1411 1

2 47K_0402_5% KSO1

R1413 1

2 47K_0402_5% KSO2
@
+3VALW

+3VS

R1417
EC_SMB_CK1
2
2.2K_0402_5%

1
R1424
R1422
2.2K_0402_5%

R1423
2.2K_0402_5%

EC_SMB_DA1
2
2.2K_0402_5%

1

EC_SMB_CK2
EC_SMB_DA2
1

2

@
C1003
100P_0402_50V8J

<50,51>
<50,51>
<15,23,39>
<15,23,39>

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

67

2
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00

83
84
85
86
87
88
97
98
99
109

Bus

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

TP_CLK
TP_DATA
CPU1.5V_S3_GATE
NTC_V_R

1 R1407

2

10K_0402_5%

EC_MUTE# <41>
USB_ON# <45,46>
MUTE_LED# <47>
EAPD <41>
TP_CLK
<43>
TP_DATA <43>

USB_ON#

119
120
126
128
73
74
89
90
91
92
93
95
121
127

2
R1432

ONEKEY_BTN#_R

R1444
2

BATT_CHG_LED#
CAPS_LED#
BATT_LOW_LED#
SYSON

PCH_PWR_EN
@ 1
BM#
0_0402_5%

USB_ON# 1

2

1
@ R1433
10K_0402_5%
SUSCLK

R1436
2
1
0_0402_5%

EC_RTCX1
SUSCLK_R

122
123

XCLKI/GPIO5D
XCLKO/GPIO5E

1

1

<16>

C1006
20P_0402_50V8

EC_RTCX1

ECAGND

2

2

R1438
100K_0402_5%

GPI

AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R

110
112
114
115
116
117
118
124

EC_LID_OUT#
Turbo_V_R
H_PROCHOT#_EC
MAINPWON_R
BKOFF#
PBTN_OUT#

BKOFF# <33>
PBTN_OUT# <16>
PCH_APWROK <16>
SA_PGOOD <54>

1 0_0402_5%
@ 1 0_0402_5%
@ 1 0_0402_5%
@

H_PECI

H_PECI

1

2
G
Q141
2N7002H_SOT23-3

<6,50>

1
S
2

C1004
47P_0402_50V8J

R1434
10K_0402_5%

<6,19>

2 R1439 1
0_0402_5%

KB9012QF-A2_LQFP128_14X14

H_PROCHOT#
D

+3VALW

LAN_WAKE#

<37>

2 R1440 1
0_0402_5% @

EMC Request
SYSON

EC_PME#

1

Q142 @
2N7002_SOT23

0.1U_0402_10V6K
C1007

3

1

PCI_PME#

<18>

+3VALW

2

1

+5VALW
C1009 @
18P_0402_50V8J
1

18P_0402_50V8J

2

1 R1427 2
0_0402_5%

H_PROCHOT#_EC

C1005
4.7U_0805_10V4Z

2

@

VR_HOT#

VR_HOT#

to EC with in 750mil

32.768KHZ_12.5PF_CM31532768DZFT
C1008
@

<57>

Turbo_V
<50>
PROCHOT <50>
MAINPWON <50,52>

@

1

1
2
C1000
100P_0402_50V8J
1
2
C1001
100P_0402_50V8J
1
2
R1416 @ 4.7K_0402_5%

11/08 Increase for LAN S5 power saving

ACIN
<16,51>
EC_ON
<47,52>
ON/OFF
<47>
LID_SW# <43>
SUSP#
<10,48,53,55,56>
PCH_HOT# <15>

Y3
1

2 2.2K_0402_5%

ACIN

R1426
47K_0402_5%

SUSCLK_R

1
2
R1441
@
10M_0402_5%

TP_DATA R1419 1

+3VLP

EC_RSMRST# <16>
EC_LID_OUT# <19>
R1428 2
R1429 2
R1430 2

LID_SW#
SUSP#
PCH_HOT#_R R1445 2 @
1 0_0402_5%
PECI_KB9012
R1435 1
2 43_0402_1%
+V18R
Please place R1435 close
1

2 2.2K_0402_5%

12/23 Follow T/P power to PU +3VS

ONEKEY_BTN# <47>
LAN_PWR_ON# <37>
BATT_CHG_LED# <44>

ACIN
EC_ON

2

+3VS
TP_CLK R1415 1

BATT_TEMP

1 0_0402_5%

2 4.7K_0402_5%
@

2

100
101
102
103
104
105
106
107
108

TP_DATA R1412 1

2

10K_0402_5%

BM#
<51>
AOAC_ON# <36>
SUSACK# <16>
ENBKL
<33>

CAPS_LED# <44>
PWR_LED# <44,47>
BATT_LOW_LED# <44>
SYSON
<48,53>
VR_ON
<57>
PM_SLP_S4# <16>

2 4.7K_0402_5%

1

EC_TX
EC_RX

AGND/AGND

<36,43>
<36,43>

<39> EC_FAN_PWM
<44> NUM_LED#

GPIO

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11

69

EC_TACH

<16> PCH_PWROK

ODD_DA#
EC_INVT_PWM
EC_TACH
EC_PME#
EC_TX
EC_RX
PCH_PWROK
EC_FAN_PWM

GND/GND
GND/GND
GND/GND
GND/GND
GND0

2

<18,40> ODD_DA#
<33> EC_INVT_PWM
<39> EC_TACH

EC_SMI#

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

11
24
35
94
113

1

<33> CMOS_ON#
<44> TP_LED#
<7> DRAMRST_CNTRL_EC

R1431
10K_0402_5%

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

+5VS
@
TP_CLK R1410 1

CPU1.5V_S3_GATE <10,48,55>
VGA_AC_DET <23,56>
ME_FLASH <14>
NTC_V
<50>

2
1
R1414 0_0402_5%
@

BM#_R

+5VALW
+3VALW
R1409

@
<16> PM_SLP_S3#
<16> PM_SLP_S5#
<19> EC_SMI#

+3VS

R1406
33K_0402_5%

ECR_EN
<33>
CHG_ON# <46>
PM_SLP_SUS# <16>
SUSWARN# <16>

SPI Device Interface
SPI Flash ROM

EC_FAN_PWM

<57>

BRDID

1

IMVP_IMON

68
70
71
72

R1.0
R1405
100K_0402_1%

R1402
10K_0402_5%
@

2

BRDID

EC_MUTE#

GPIO

+3VALW

1

9
22
33
96
111
125

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

+3VS

BATT_TEMP <50>
VGA_IMVP_IMON <56>
ADP_I
<50,51>
MUTE_BTN# <47>

2

100K_0402_5%
R1111

PCH_PWR_EN#

<50> PCH_PWR_EN
1

8/23 change to reserved

2

@
<48> PCH_PWR_EN#

1

2

@
C1002
100P_0402_50V8J

BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

PS2 Interface

<47>

D

3

1

BATT_TEMP

LED_KB_PWM_R

BEEP#
<41>
NOVO#
<47>
ACOFF
<51>

1

KSO[0..15]

AD Input

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

63
64
65
66
75
76

KBL@
R1443
0_0402_5%
2
1

3

<43>

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

LED_KB_PWM
BEEP#
NOVO#
ACOFF

PWM Output

DA Output

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

21
23
26
27

S

1

KSO[0..15]

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

D

EC_SCI#
BATT_LEN#

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

U70

2
G

<19>
<50>

2

1
0_0402_5%

2

2

<18> CLK_PCI_EC
<18,23,36,37,46> PLT_RST#

2
47K_0402_5%
C999
0.1U_0402_16V4Z

EC_RST#
EC_SCI#
BATT_LEN#

12
13
37
20
38

10_0402_5%

2

+3VLP_R 2

EC_VDD/AVCC

<14>
SERIRQ
<14,36> LPC_FRAME#
<14,36> LPC_AD3
<14,36> LPC_AD2
<14,36> LPC_AD1
<14,36> LPC_AD0

1
2
1
22P_0402_50V8J
@ R1403

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

1
2
3
4
5
7
8
10

KBRST#

KBRST#

2

R1401

1

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

GATEA20

2

1

2

1
R1404

+3VALW

2

1

1

2
@ C998

1

C994
1000P_0402_50V7K

<19>
<19>

2

1

C997
1000P_0402_50V7K

1000P_0402_50V7K

2

1

C993
0.1U_0402_16V4Z

C995
0.1U_0402_16V4Z
2 ECAGND
1
2
L78
FBM-11-160808-601-T_0603

C996

C992
0.1U_0402_16V4Z

+EC_VCCA

1

C991
0.1U_0402_16V4Z

+3VALW

C990
0.1U_0402_16V4Z

L77
FBM-11-160808-601-T_0603
1
2
1

S

Q117
2N7002_SOT23

2
G
100K_0402_5%
R1114

@

2

@

Compal Secret Data

Security Classification

Issued Date

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.
BIOS & EC I/O Port

Size
C
Date:

Document Number

Rev
1.0

QIWY3 LA-8001P
Monday, January 16, 2012

Sheet

42

of

64

5

4

3

2

1

INT_KBD Conn.
KSI[0..7]
KSO[0..15]

D

EC DEBUG PORT

KSI[0..7]

<42>
D

KSO[0..15] <42>
JP5

2 @ 100P_0402_50V8J

KSO1

C735 1

2 @ 100P_0402_50V8J

C736 1

2 @ 100P_0402_50V8J

KSO7

C737 1

2 @ 100P_0402_50V8J

KSO6

C738 1

2 @ 100P_0402_50V8J

KSI2

C739 1

2 @ 100P_0402_50V8J

KSO8

C740 1

2 @ 100P_0402_50V8J

KSO5

C741 1

2 @ 100P_0402_50V8J

KSO13

C742 1

2 @ 100P_0402_50V8J

KSI3

C743 1

2 @ 100P_0402_50V8J

KSO12

C744 1

2 @ 100P_0402_50V8J

KSO14

C745 1

2 @ 100P_0402_50V8J

KSO11

C746 1

2 @ 100P_0402_50V8J

KSI7

C747 1

2 @ 100P_0402_50V8J

KSO10

C748 1

2 @ 100P_0402_50V8J

KSI6

C749 1

2 @ 100P_0402_50V8J

KSO3

C750 1

2 @ 100P_0402_50V8J

KSI5

C751 1

2 @ 100P_0402_50V8J

KSO4

C752 1

2 @ 100P_0402_50V8J

KSI4

C753 1

2 @ 100P_0402_50V8J

KSI0

C754 1

2 @ 100P_0402_50V8J

KSO9

C755 1

2 @ 100P_0402_50V8J

KSO0

C756 1

2 @ 100P_0402_50V8J

KSI1

C757 1

2 @ 100P_0402_50V8J

CONN PIN define need double check

JP6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2

1
R1002

+3VALW

+VCC_LID

2
0_0402_5%

1

To TP/B Conn.

TP_DATA
TP_CLK

1

1

2

@
C762
100P_0402_50V8J

3

2

@
C761
100P_0402_50V8J

+3VS
C760

6
5
4
3
2
1

2 100K_0402_5%
C

3

2

LID_SW # <42>

2

1

U37

1

C759
10P_0402_50V8J

ACES_88514-00601-071

0.1U_0402_16V4Z

2

TP_DATA
TP_CLK

1
2
3
4

5711ACDL-M3T1S SOT-23

OUTPUT

JP24

<42>
<42>

R1003 1

GND

C758
0.1U_0402_16V4Z

GND
GND

EC_TX
EC_RX

Lid Switch

ME@

6
5
4
3
2
1

1
2
3
4

ACES_85205-0400
ME@

ACES_85202-24051

8
7

+3VALW
EC_TX
EC_RX

<36,42>
<36,42>

2

C734 1

KSO15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

VDD

C

KSO2

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

ME@
@

1

B

B

D58
PACDN042Y3R_SOT23-3

A

A

Compal Secret Data

Security Classification
2011/07/21

Issued Date

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
KB /SW /LPC Debug Conn.

Size
B
Date:

Document Number

Rev
1.0

QIWY3 LA-8001P
Monday, January 16, 2012

Sheet
1

43

of

64

LED
LED1
<42>

1

TP_LED#

2

2
300_0402_5%

1
R1010

+5VS

1
R1012

+5VALW

12-21SYGCS530-E1S155TR8_W

White
LED2

Amber

BATT_LOW_LED#

<42> BATT_LOW_LED#

FD1

3

FD2

1
1

2
470_0402_5%

BATT_CHG_LED#

White

FD3

FD4

1

1

H4
HOLEA

H5
HOLEA

D:H_2P8 X 10

2

<42> BATT_CHG_LED#

1

H1
HOLEA

12-22-S2ST3D-C30-2C_WHI-ORG

H2
HOLEA

H3
HOLEA

H6
HOLEA

H7
HOLEA

H8
HOLEA

H9
HOLEA

H19
HOLEA

1
R1026

+5VS

1

2
300_0402_5%

1

+5VS

1

1
R1014

1

2
300_0402_5%

1

2

1

+5VALW
1

1
R1013

1

2
300_0402_5%

1

<42,47> PWR_LED#

2

1

LED3
1
12-21SYGCS530-E1S155TR8_W

White
LED4
1

<42> CAPS_LED#

12-21SYGCS530-E1S155TR8_W

A:H_3P9 X 3

B:H_3P8 X 2

H10
HOLEA

H13
HOLEA

H11
HOLEA

H12
HOLEA

H15
HOLEA

1

1

1

1

1

White
LED5
<42>

1

NUM_LED#

2

12-21SYGCS530-E1S155TR8_W

H_3P2

H16
HOLEA

H18
HOLEA

H_6P0X3P0N

H_4P5X3P0N
H21
HOLEA

1

H20
HOLEA

1

1

H_3P3

1

White

BT MODULE CONN

+3VS

+3VS_BT

+3VALW
Q93

2

30mils

1
1

BT@
2

2

AO3413_SOT23-3

3

G

R1025
<19,36> PCH_BT_ON#

@

D

1

C522
0.1U_0402_16V4Z

S

11/30 change to 200K for soft star

1

2

0.1U_0402_16V4Z
C776
BT@

200K_0402_5% BT@

JP8
1

C775
0.1U_0402_16V4Z
BT@

2

<18> USB20_P13
<18> USB20_N13

USB20_P13
USB20_N13

<36> BT_ACTIVE

BT_ACTIVE

1
2
3
4
5
6

1
2
3
4
5 G1
6 G2

7
8

ACES_87213-0600G
ME@

Compal Secret Data

Security Classification
Issued Date

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.
LED/EC SPI ROM/BT

Size
B
Date:

Document Number

Rev
1.0

QIWY3 LA-8001P
Monday, January 16, 2012

Sheet

44

of

64

A

B

C

D

E

LEFT SIDE USB3.0 PORT X2
11/07 Change source to SA00004KB00
+5VALW

+USB_VCCA
U39

C767 0.1U_0402_16V4Z
2
1
<42,46> USB_ON#

1

USB_ON#

1
2
3
4

8
7
6
5

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

1

USB_OC1#

SY6288DCAC_MSOP8

1

Low Active 2A

USB_OC1# <18>

C904
@ 1000P_0402_50V7K

2

+

+USB_VCCA
C814 220U_6.3V_M
1
2

For EMI request

1
2
C816 470P_0402_50V7K

USB2.0 choke --> SM070000I00
USB3.0 Choke --> SM070001U00
JUSB1
<18> USB30_TX_P3
L68
USB30_RX_N3

2

2

1

1

USB30_RX_R_N3

<18> USB30_TX_N3
<18> USB20_N2

USB30_RX_P3

3

3

4

4

USB30_RX_R_P3

<18> USB20_P2
<18> USB30_RX_P3

2

WCM-2012-900T_4P

USB30_TX_P3 C299 1

2 0.1U_0402_10V6K

USB30_TX_C_P3

R1157 1

2 0_0402_5% USB30_TX_R_P3

USB30_TX_N3 C300 1
USB20_N2

2 0.1U_0402_10V6K

USB30_TX_C_N3

R1156 1 @
R1162 1
@
R1163 1 @
R1155 1
@
R1154 1 @

2 0_0402_5% USB30_TX_R_N3
2 0_0402_5% USB20_N2_R

USB20_P2
USB30_RX_P3
USB30_RX_N3

<18> USB30_RX_N3

L70
USB30_TX_C_N3 2
USB30_TX_C_P3 3

2

1

1

3

4

4

USB30_TX_R_P3
@

USB20_N2

2

2

1

1

USB20_N2_R

USB20_P2

3

3

4

4

USB20_P2_R



1USB30_RX_R_N3

USB30_RX_R_P3 8 



2 USB30_RX_R_P3

USB30_TX_R_N3 7 



4 USB30_TX_R_N3

USB30_TX_R_P3 6 



5 USB30_TX_R_P3



3

USB20_N2_R

2

1

1

USB30_RX_R_N4

3

4

4

USB30_RX_R_P4

L71

USB30_TX_C_P4 3

2
3

@

I/O2

I/O4

6

2

GND

VDD

5

+5VALW

I/O1

I/O3

4

USB20_P2_R

1

1

1

USB30_TX_R_N4

4

4

USB30_TX_R_P4

<18> USB30_TX_N4
<18> USB20_N3

1
C825

USB30_TX_P4 C292 1

2 0.1U_0402_10V6K USB30_TX_C_P4

R1161 1

2 0_0402_5% USB30_TX_R_P4

USB30_TX_N4 C296 1
USB20_N3

2 0.1U_0402_10V6K USB30_TX_C_N4

R1160 1 @
R1164 1
@
R1165 1 @
R1159 1
@
R1158 1 @

2 0_0402_5% USB30_TX_R_N4
2 0_0402_5% USB20_N3_R

USB20_P3
USB30_RX_P4

<18> USB20_P3
<18> USB30_RX_P4

USB30_RX_N4

<18> USB30_RX_N4

WCM-2012-900T_4P

USB20_P3

2
3

2
3

9
1
8
2
7
3
6
4
5

2 0_0402_5% USB20_P3_R
2 0_0402_5% USB30_RX_R_P4
2 0_0402_5% USB30_RX_R_N4

2
470P_0402_50V7K

1
4

1
4

USB20_N3_R
USB20_P3_R

GND
GND
GND
GND

10
11
12
13

ME@

For ESD request
@

WCM-2012-900T_4P

3

SSTX+
VBUS
SSTXDGND
D+
SSRX+
GND
SSRX-

OCTEK_USB-09EAEB

@

L73
USB20_N3

+USB_VCCA

AZC099-04S.R7G_SOT23-6

JUSB2
<18> USB30_TX_P4

WCM-2012-900T_4P
USB30_TX_C_N4 2

2

YSCLAMP0524P_SLP2510P8-10-9

L69

3

10
11
12
13

GND
GND
GND
GND

OCTEK_USB-09EAEB

3

8

USB30_RX_P4

SSTX+
VBUS
SSTXDGND
D+
SSRX+
GND
SSRX-

ME@
D24

D27

USB30_RX_R_N3 9 

WCM-2012-900T_4P

3

2 0_0402_5% USB30_RX_R_N3

For ESD request

L72

2

2 0_0402_5% USB20_P2_R
2 0_0402_5% USB30_RX_R_P3

@

USB30_TX_R_N3

WCM-2012-900T_4P

USB30_RX_N4

9
1
8
2
7
3
6
4
5

D40

D39

USB30_RX_R_N4 9 



1 USB30_RX_R_N4

USB30_RX_R_P4 8 



2 USB30_RX_R_P4

USB30_TX_R_N4 7 



4 USB30_TX_R_N4

USB30_TX_R_P4 6 



5 USB30_TX_R_P4



3

USB20_P3_R

8

4

@

3

I/O2

I/O4

6

2

GND

VDD

5

+5VALW

1

I/O1

I/O3

4

USB20_N3_R
4

AZC099-04S.R7G_SOT23-6

YSCLAMP0524P_SLP2510P8-10-9

Compal Secret Data

Security Classification
Issued Date

2011/07/21

Deciphered Date

For EMI request
2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Compal Electronics, Inc.
Title

D

USB3.0 ports
Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
E

45

of

64

5

4

3

2

+5VS

Right side USB Charger

1

+5V_CHGUSB

+3VS
ACES_88514-3001

U68
1

CEN#

USB20_N0_C

2

DM

USB20_P0_C

3

DP

4

GND

CB

8

TDM

7

TDP

6

VDD

5

CHG_ON#

9

USB20_N0 <18>

R1394
100K_0402_5%
USB20_P0 <18>
+5VALW

PLT_RST#
<18,23,36,37,42>

1

SLG55566VTR_TDFN8_2X2
CHG@

C987
0.1U_0402_16V4Z
CHG@

CLK_PCIE_CARD_PCH#
CLK_PCIE_CARD_PCH
PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4

<15> PCIE_PTX_C_DRX_N4
<15> PCIE_PTX_C_DRX_P4

11/07 Change source to SA00004KB00
+5VALW

PLT_RST#

<15> CLK_PCIE_CARD_PCH#
<15> CLK_PCIE_CARD_PCH

2

Thermal Pad

CHG@

2

SLG55566

D

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

<15> PCIE_PRX_DTX_N4
<15> PCIE_PRX_DTX_P4

+5V_CHGUSB
U69

C988 0.1U_0402_16V4Z
2
1
<42,45> USB_ON#

USB_ON#

1
2
3
4

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

USB20_P0_C
USB20_N0_C

8
7
6
5

Low Active 2A

+5VALW

1

C989
@ 1000P_0402_50V7K

+5V_CHGUSB
1

1

USB20_N0

1 2

2

USB20_P0
R1396
470_0603_5%
@

1

3

S

R1397
10K_0402_5%

CPPE#
EXT_MIC_L
EXT_MIC_R
MIC_JD
HP_OUTR
HP_OUTL
SPDIF_OUT
PLUG_IN

EXT_MIC_L
EXT_MIC_R
MIC_JD
HP_OUTR
HP_OUTL
SPDIF_OUT
PLUG_IN

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

32
31

GND
GND

D

JP21

NOCHG@
R1167 1

2 0_0402_5% USB20_N0_C

C

ME@

2 0_0402_5% USB20_P0_C

R1166 1
NOCHG@

12/23 Change to SP010011A00 for ASSY issue
CB

D
PWRSHARE_EN#

<41>
<41>
<41>
<41>
<41>
<41>
<41>

2

C

R1395
10K_0402_5%
@

<15>

USB_OC0#

SY6288DCAC_MSOP8

2 PWRSHARE_EN#
G
Q140
2N7002_SOT23
@

Function

L

auto detection charger identification active

H

DP/DM=TDP/TDM

USB2.0/3.0 choke and ESD diode at sub-B.

Right USB Conn.(Cable)

Right side USB3.0 port (Option)
AC CAP reserve on SUB/B
<18> USB30_TX_P1
<18> USB30_TX_N1
<18> USB30_RX_P1
<18> USB30_RX_N1

JP23
1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
GND
GND

W=80mils

2

<18> USB20_N9
<18> USB20_P9

1

2

C766
470P_0402_50V7K

1
1

2
2

WCM-2012-900T_4P
USB20_N9

4

USB20_P9

1

4

3

3

1
L64

2

2

1
2
3
4
5
6

USB20_N9_R
USB20_P9_R

USB20_N9_R
USB20_P9_R

2

+

JUSB3
0_0402_5%
0_0402_5%

3

1

R1109
R1108

D49
@

@

1
2
3
4
G5
G6

B

ACES_85205-04001
ME@

1

B

150U_B2_6.3VM_R35M
C911

+USB_VCCB

PJDLC05_SOT23-3

2

CHG@

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

CHG_ON# <42>
1

PWRSHARE_EN#

11/07 Change source to SA00004KB00
+5VALW

+USB_VCCB
U40

C768 0.1U_0402_16V4Z
2
1
<42,45> USB_ON#

USB_ON#

1
2
3
4

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

8
7
6
5

USB_OC4#

SY6288DCAC_MSOP8

1

ACES_50463-0104A-001

Low Active 2A

ME@

USB_OC4# <18>

C909
@ 1000P_0402_50V7K

2

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/21

Deciphered Date

2012/12/31

Title

Audio B Conn/USB charger

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

Size Document Number
Custom
Date:
2

Monday, January 16, 2012

Rev
1.0

QIWY3 LA-8001P
Sheet

46
1

of

64

0_0402_5%
1
2

2

51_ON#

51_ON# <49>
<42> MUTE_BTN#
<42> MUTE_LED#
<42> ONEKEY_BTN#

@

9/23 ESD Request
C551

1

100P_0402_50V8J

<49>

51_ON#

2
NOVO_BTN#
1
51_ON# 1
@ 2
3
R14
0_0402_5%
R19
0_0402_5%
DAN202UT106_SC70-3
ON/OFF 1
2

R1229
10K_0402_5%
KBL@

1 R1232 2
100K_0402_5%
KBL@

E-T_6712K-F12N-02L
ME@

1

1

2
2

<42> LED_KB_PW M_R

2

IN

1

1

1

NOVO#

3

3

NOVO#

13
14

2

2

2
<42>

D56

GND
GND

D54
PJSOT24C 3P C/A SOT-23
@

R1118
100K_0402_5%

100K_0402_5%
R1117
@

11/07 change to +5VALW

ON/OFFBTN#

3

NOVO_BTN#

+VCC_KB_LED
Q121

AO3413_SOT23-3
KBL@

1

2

KBL@
C907
0.01U_0402_16V7K

2

1

KBL@
C908
0.1U_0402_16V4Z

1

+3VLP +3VALW

1

+5VS
+5VALW

OUT

1
3

S

ON/OFFBTN#

1
2
3
4
5
6
7
8
9
10
11
12

G

2

NOVO_BTN#
<42,44> PW R_LED#

JP10

1
2
3
4
5
6
7
8
9
10
11
12

GND
GND

D

2
G
Q95
2N7002_SOT23-3

D

R1112
10K_0402_5%

@

R1399
100K_0402_5%

5
6

JOINT_F1017W R-S-04P
ME@

S

EC_ON

R1398
100K_0402_5%

ON/OFF <42>

1
2
3
4

1

ON/OFF

1

3

@

2

D53

1
@

2

2

1

DAN202UT106_SC70-3

EC_ON

2

1

R60

2

SHORT PADS
@
ON/OFFBTN#

<42,52>

+5VALW +5VS

1
2
3
4

KBL@
C906
10U_0603_6.3V6M

+3VALW

1

1

Bottom Side

JP12
+VCC_KB_LED

@
100K_0402_5%
R1115

J7

@

1

TOP Side

KB Lighting CONN.4pin

2

SMT1-05_4P
100K_0402_5%
R1116

Power Button/B link to Function/B Conn. 10pin

GND

4

+3VALW

0.1U_0402_10V6K
C905

2

+3VLP

2

3

6
5

Power Button

1

2

ON/OFF switchSW 2

EMI REQUEST 1ST = SCA00000E00
2ST = SCA00000R00

Q122
DTC124EKAT146_SC59-3
KBL@

Compal Electronics,Ltd.

Compal Secret Data

Security Classification
Issued Date

11/07 Change type to 0603

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

other IO connector
Size
Document Number
Custom
Date: Monday, January 16, 2012

Rev
1.0

QIWY3 LA-8001P
Sheet

47

of

64

+3VALW TO +3VS

+1.5V
3

U47

3

+5VALW

2

1

1
C39
10U_0603_6.3V6M
DS3@

C851
0.1U_0402_25V6
@

<42> PCH_PWR_EN#

+3VS to +3VS_VGA

<16> PM_SLP_SUS

@
+5VALW
+1.05VS

3

AO3413_SOT23

S

2
@ R91
2
2
G
R92
Q105
2N7002_SOT23

1
0_0402_5%
1 SUSP
0_0402_5%

6
2
Q144A

1 2

D
2 SUSP
G
Q102
2N7002_SOT23
@

3

1 2

D

R1094
22_0603_5%
CPU1.5V_S3_GATE <10,42,55>

1

1

@
SUSP

R1091
470_0603_5%
@

1
R1454
100K_0402_5%
OPT@

Deciphered Date

1
2

1
10U_0603_6.3V6M

S

R1450
470_0603_5%
@
@
R1453
2
2
1
10K_0402_5%
G
Q147
2N7002_SOT23
@
1

2

DGPU_PWR_EN#

Compal Electronics, Inc.
2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

D

Compal Secret Data
2011/07/21

Issued Date

For Intel S3 Power Reduction.

1

C1011

Q146
2N7002_SOT23
S OPT@

2
G

OPT@

2
1

D

3

R1452
0_0402_5%
1

2
C37

OPT@

4

Security Classification

A

2

1

Q145

0.1U_0402_10V7K

@

@

<18,23> DGPU_PWR_EN

2

R8
100K_0402_5%

+0.75VS

1

10.75VR_EN 5

2

DMN66D0LDW-7 2N_SOT363-6

2
<54,55> +V1.05S_VCCP_PWRGOOD

3

Q143B

<55> 0.75VR_EN#

DMN66D0LDW-7 2N_SOT363-6

3

3

S

2 SUSP
G
Q106
2N7002_SOT23
@

4

1 2

<25,53> DGPU_PWR_EN#

R1449
47K_0402_5%
OPT@
OPT@
R1451
1
2
10K_0402_5%

G

1 2

1

1

1

3
R6
100K_0402_5%

@

D
2 SYSON#
G
Q103
2N7002_SOT23
@

S

+1.8VS

R1095
470_0603_5%
@

OPT@

D

D

2

JUMP_43X79

S

R1092
470_0603_5%
@

1

2

+3VALW
1

+1.5V

+3VS_VGA

J10
1

@ C1012

2

0.1U_0402_10V7K

@

1 2

1

3

S 2N7002_SOT23

1

3

R1107
0_0402_5%

Q116

09/05 add for Deep S3

3

1

R1101
100K_0402_5%

@

2

1

D

3

S

IN

2

2

2

3

DS3@

SYSON

SYSON

3

Q149

+3VS

4

<42,53>

IN

2

C38
10U_0603_6.3V6M
DS3@

2

2

2

<10,42,53,55,56> SUSP#

1
1

DS3@

Q108
DTC124EKAT146_SC59-3
@

1

Q107
DTC124EKAT146_SC59-3

2

2

2

1

SYSON#

1

<10,53,55> SUSP

@
R1098
100K_0402_5%

OUT

@

3

G

G

Q148

SUSP

JUMP_43X79

1

0.1U_0402_25V6

@
R1097
100K_0402_5%

R1096
220K_0402_5%

D

1

C845

+5VALW

2

2

S

3

1

2

+RTCVCC

AO3413_SOT23

D

2 PCH_PWR_EN#
G
Q110
2N7002_SOT23
@

2

3

1

0.1U_0402_25V6

+5V_PCH

J14
1

JUMP_43X79

S

3

2

2

AO3413_SOT23

D

R1106
47K_0402_5%
@

+5VALW

2

@

R1100
470_0603_5%
@

1

2

2

1

S

PCH_PWR_EN# 2
G
@

C844

+5VALW to +5V_PCH

+3V_PCH

J11

1.5VS_GATE
1
1

2 R1090 1
0_0402_5%

D

SUSP# 2
G
2N7002_SOT23S

@
1

@

1

+3V_DSW

@

+3V_DSW to +3V_PCH
+3V_DSW

C846
1U_0603_10V4Z

@

2

2

C843
0.01U_0603_50V7K

JUMP_43X79

+3VALW

C848
10U_0603_6.3V6M

+3V_DSW
U48
8
1
D
S
7 D
1
1
S 2
6
3
D
S
C847
5
4
G
10U_0603_6.3V6M D
2
DMN3030LSS-13_SOP8L-8 2

1

S

Q101

1

1

2 SUSP
G
Q98
2N7002_SOT23
@

GND

+3VALW

2

R1089
0_0402_5%

Q100
2N7002_SOT23

2

1

D

2
G

@

11/07 Change type to 0603

100K_0402_5%
R1087

2
J20

+3VALW TO +3V_DSW

@+VSB

1
SUSP

R1119
470_0603_5%
@

D

S

2
1
C842
0.01U_0603_50V7K

3

2

C835
1U_0603_10V4Z

+3VALW

2 SUSP
G
Q97
2N7002_SOT23
@

1

3

1

S

2

S
R1086
470K_0402_5%

15VS_GATE_R

82K_0402_5%
Q99
2N7002_SOT23

1 2

1

5VS_GATE2 R1088
D

2

SI2301BDS-T1-E3_SOT23-3

D
2 SUSP
G
Q96
2N7002_SOT23
@

3

3

S

2

1
C857
10U_0603_6.3V6M

OUT

+VSB

D

R1085
150K_0402_5%

2
R1084
470_0603_5%
@

C856
10U_0603_6.3V6M

1

R1113
470_0603_5%
@

1

Q120

1

1 2

C837
C838
10U_0603_6.3V6M 1U_0603_10V4Z
2
2
DMN3030LSS-13_SOP8L-8

1

1

1

1

1

1

8
1
D
S
7
2
1
1
1
D
S
6 D
S 3
C839
C840
C841
5
4
G
10U_0603_6.3V6M D
10U_0603_6.3V6M 1U_0603_10V4Z
2
2
DMN3030LSS-13_SOP8L-8 2

1 2

1
2
3
4

1

S
S
S
G

G

D
D
D
D

+3VS

D

+3VALW

+VSB

2
G

+1.5VS
S

+5VS
U46

SUSP

7/26 change SI4800 to SI2301

+1.5V to +1.5VS

11/07 Change type to 0603

11/07 Change type to 0603

+5VALW
8
7
1
6
C836
5
10U_0603_6.3V6M
2

E

GND

11/07 Change type to 0603

1

D

1

+5VALW TO +5VS

C

2

B

2

A

C

D

Title

DC Interface
Size Document Number
Custom
Date:

Rev
1.0

QIWY3 LA-8001P

Monday, January 16, 2012

Sheet
E

48

of

64

5

4

3

1

1
2

@ 4602-Q04C-09R 4P P2.5
JDCIN1

2

1

1

2
1

1

2

D

PC104
1000P_0402_50V7K

PL101
SMB3025500YA_2P
1
2

PC103
100P_0402_50V8J

PF101
12A_65V_451012MRL
2 APDIN1

2

3

2

1

PC102
100P_0402_50V8J

3

APDIN

PC101
1000P_0402_50V7K

4

1

VIN

DC030006J00

4

2

D

+3VLP

<47>

51_ON#

LL4148_LL34-2

2

PR119 @
68_1206_5%

1
1

VS
1

3

2

2
1

100K_0402_1%

PR124 @
22K_0402_1%
1
2

2

PR123 @
1

51ON-2

2

PQ104 @
TP0610K-T1-E3_SOT23-3

PR125 @
200_0402_1%
1
2

C

51ON-1

1

PJ101
@ JUMP_43X39
1
2
1
2

51ON-3

PC113
@ 0.1U_0603_25V7K

PD104 @
LL4148_LL34-2
2
1

2

BATT+

PC112 @
0.22U_0603_25V7K

C

PR118 @
68_1206_5%
2
1

PD103 @

VIN

-

JRTC1

+

2

1

PR129
560_0603_5%
1
2

PR130
560_0603_5%
1
2

PD107
2

1

+RTCBATT

@ MAXEL_ML1220T10
@ PU101
@

VOUT

1
2

+CHGRTC

PR128
200_0603_5%

RTC Battery

2

3

B

2

PD108
RB751V-40_SOD323-2

APL5156-33DI-TRL_SOT89-3
VIN

2 CHGRTCIN
1

3.3V

1

1

+CHGRTC

GND
PC114
10U_0603_6.3V6M
@

1

2

1

PR126

0_0402_5%

2

RB751V-40_SOD323-2

B

PC115
1U_0805_25V6K
@

A

A

Compal Secret Data

Security Classification
Issued Date

2011/06/30

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
Vin Detector

Size Document Number
Custom
Date:

Rev
1.0

QIWY3

Monday, January 16, 2012

Sheet
1

49

of

64

5

4

VMB2

1

PL201
SMB3025500YA_2P
1
2

BATT+

1
2

D

PC202
0.01U_0402_25V7K

PH201 under CPU botten side :
CPU thermal protection at 92+-3 degree C
Recovery at 56 +-3 degree C

EC_SMB_CK1 <42,51>
EC_SMB_DA1 <42,51>

VL
2
1
PR207
21.5K_0402_1%
1
2

+3VLP
PR236 @
47K_0402_1%
2
1

PR235 @
47K_0402_1%
2
1

Turbo_V

+3VLP

1

47K_0402_1%

B

PH201
100K_0402_1%_NCP15WF104F03RC

0_0402_5%

0_0402_5%

PR231 @
2
1

PR232
2

PR234
0_0402_5%
2
1

MAINPWON <42,52>

+3VALW

<42>

1

2
1
PR206 @
13.7K_0402_1%

2

PR210
+3VALW PR233 @
27.4K:90W
47K_0402_1%
2
1
82.5K:120W

PR213
2

2

PR210
82.5K_0402_1%

2

ADP_OCP_2 1

5

NTC_V

PR212 @
0_0402_5%
2

1
PR208
10K_0402_1%

PR211

OT2 RHYST2

C

2
Turbo_V-1

6

G718TM1U_SOT23-8

3

1

OT1 TMSNS2

NTC_V-1

OTP_N_002

1

4

2 ADP_OCP_1
G

PROCHOT

7

3

S

<42>

8

GND RHYST1

10K_0402_1%

D
PQ201
2N7002KW_SOT323-3

VCC TMSNS1

2

<42>

1

<6,42> H_PROCHOT#

PU201
1

0_0402_5%

PR209
1

C

1

+3VS

PR205
4.42K:90W
9.1K:120W

PR230 @
2

A/D

2

BATT_TEMP <42>

<42,51> ADP_I

1

1
2
PR204
10K_0402_5%

+3VLP

PC203
0.1U_0603_25V7K
2
1

+3VALW

PR205
9.1K_0402_1%

1
2
PR203
6.49K_0402_1%

OTP_N_003

2

PC201
1000P_0402_50V7K

100K_0402_1%

@ SUYIN_200082GR007M229ZR

2
1
PR202
100_0402_1%

1

EC_SMCA
EC_SMDA
2
1
PR201
100_0402_1%

D

1
2
3
4
5
6
7
8
9

2

VMB
PF201
12A_65V_451012MRL
1
2

JBATT1
1
2
3
4
5
6
7
GND
GND

3

B

S

VL

2VREF_8205

PR225
10K_0402_1%
<42> BATT_LEN#

PR227
2

1

10K_0402_1%

PR229
0_0402_5%
1
2

PQ204
D 2N7002KW_SOT323-3

S

1

PR224
1K_0402_1%
2

2

<42> PCH_PWR_EN

1

D

1
2

1
2

PQ205
2N7002KW_SOT323-3

2
G
3

SPOK

PR228 @
0_0402_5%
1
2

PC207
1U_0402_6.3V6K

1

1

2

A

1

PR223 @
10K_0402_1%

3

PR226

2

+CHGRTC

<52>

100K_0402_1%

1

PC206
0.1U_0603_25V7K

2

1

2

+VSBP

PR222 @
100K_0402_1%

+3VLP

1

PU202A
AS393MTR-E1 SO 8P OP

PC205
0.22U_0603_25V7K

D

2
G

1

1

PR220
22K_0402_1%
1
2

2
1
PR216
100K_0402_1%

BATT_OUT <51>

1

2

100K_0402_1%

2
PR215
1

-

1

PR214
1

100K_0402_1%

2
O
4

2

+

3

B+

PQ203
2N7002KW_SOT323-3

3

PR221
221K_0402_1%

2

8
3

2

PR218
10M_0402_5%
1

PR219
10K_0402_1%
1
2

PQ202
TP0610K-T1-E3_SOT23-3

+3VALW

P

PR217
768K_0402_1%

G

1

2

2

VMB2

+3VLP

PC204
0.01U_0402_25V7K

1

P2

+VSBP

S

+VSB

A

2
G

Compal Secret Data

Security Classification
Issued Date

2010/06/30

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

PJ201
@ JUMP_43X39
1
2
1
2

4

3

2

Title

Compal Electronics, Inc.
BATTERY CONN/OTP

Size Document Number
Custom
Date:

Rev
1.0

QIWY3

Monday, January 16, 2012

Sheet
1

50

of

64

5

4

3

2

1

B+

P3
P2
PQ302
SI4459_SO8

PR304
47K_0402_1%
1
2

5
6
7
8
20

PHASE

19

HIDRV

18

BTST

17

REGN

16

1

4

2
3
2
1

1U_0603_25V6

1

4

3
2
1

1

15

14

BQ24737_VDD

2

PR325
10_0603_5%

2
1
3

BATT+

CHG
1

4

2

3

1

DL_CHG

PR320
4.7_1206_5%

PQ312

PC317
1U_0603_25V6

PC319
0.1U_0603_25V7K
2
1

2

5
6
7
8

PR322
PC314
2.2_0603_5%
0.047U_0603_50V7
BST_CHG
1
2
2
1
PD301
RB751V-40_SOD323-2
2
1

16251_SN
2

LODRV

ILIM

C

PL302
PR318
4.7UH_PCMB104E-4R7MS_10A_20% 0.01_1206_1%

LX_CHG
DH_CHG

PACIN

PC316
10U_0805_25V6K
2
1

ACN
VCC

2
G
S

PC315
10U_0805_25V6K
2
1

1

3

2
ACP

21

2

1

CMPIN

CMPOUT

TP

SCL

1 13

PQ310

PR328
10_1206_5%
1
2
PC313

PU301
SDA
BQ24737RGRR_VQFN20_3P5X3P5

11

1

P2

IOUT

BM#

2ACOFF-1

1

2
<42>

PD302

1DISCHG_G-1
1

PQ309
2N7002KW _SOT323-3
D

PC311
0.1U_0603_25V7K
2
1

2

GND

PR324
100K_0402_1%

PD303
1SS355_SOD323-2
2

PC310
0.1U_0603_25V7K

SRP

9
10

1

PC318
680P_0603_50V7K

PR310
2
1
@ 10K_0603_1%

PR309 @
2

100K_0402_1%

2

B

1

S

7

100P_0603_50V8
8

ACDET

SRN

+3VALW P

PC312
1
2

PR321
1
2
147K_0402_1%

4

5
6

PC321 @ .1U_0603_25V7K
2
1
PR329
0_0402_5%
<42,50> EC_SMB_DA1
1
2
PR330
0_0402_5%
<42,50> EC_SMB_CK1
1
2

2

3
B

ADP_I

PR327 @
10K_0402_5%
1
2

D

1
0.1U_0603_25V7K

PR312 @
1
2
4.7M_0603_1%

1

ACOK

<42,50>

PR317
64.9K_0603_1%
1
2

2N7002KW_SOT323-3

2
1

PQ313
2
G

<50> BATT_OUT

PC309
2

39.2K_0402_1%

3

PR323
0_0402_5%

2

PR306
200K_0402_1%

TPC8037-H 1N SO8

2
1
390K_0603_1%

PR313

PR311 @
2

BM

1
2ACOFF-12
10K_0402_5%

VIN

6.8_0603_5%
1 12
PR326

ACOFF

S

1

<42>

1

2

PR319

PQ308
2N7002KW _SOT323-3
2
BATT_OUT <50>
G

1

PQ311
DTC115EUA_SC70-3

1

ACON

D

PC308
+3VALW P

ACPRN

3

1
5

PR308
150K_0402_1%

2
P2-2
3

PQ307B

PACIN

4

PACIN

PR316
47K_0402_1%
1
2

2N7002KDW-2N_SOT363-6

1
C

1 2

3
6
PQ307A
2N7002KDW -2N_SOT363-6

2

<52>

PR307
20K_0402_1%

PQ306
DTC115EUA_SC70-3

3

1

DTC115EUA_SC70-3

0.1U_0603_25V7K

1
PQ305

1SS355_SOD323-2

2

VIN

PR305
10K_0402_1%

TPC8A03-H 1N SO8

1

ACP

2

D

4

DISCHG_G

ACN

P2-1

8
7
6
5

1

PC322 @
0.1U_0603_25V7K

1
2
3

PC307
2200P_0402_50V7K

2

PC306
4.7U_0805_25V6-K
1
2

1

PQ303
SI4459_SO8

PC305
4.7U_0805_25V6-K
1
2

3

2

2

CHG_B+

PL301
FBMA-L11-201209-121LMA50T_0805
1
2

1

1
2

2

PC303
0.1U_0603_25V7K
2
1
PR303
200K_0402_1%

3

2

1
PR302
47K_0402_5%

4

PC301
5600P_0402_25V7K
1
2

PQ304
DTA144EUA_SC70-3

1

PC304
4.7U_0805_25V6-K
1
2

D

PR301
0.01_1206_1%

8
7
6
5

PC302
1000P_0603_50V7K
1
2

1
2
3

4

1
2
3

4

8
7
6
5

PC323
1000P_0603_50V7K
1
2

PQ301
SI4459_SO8

VIN

2

+3VS

PC320
0.1U_0603_25V7K

PR337
10K_0402_1%
1
2

1

1

BQ24737_VDD

3

S

1
PR339
2

D

2
G

2N7002KW_SOT323-3

PQ316

1

<52>

<16,42>

PACIN

2

2
ACPRN

ACIN

PR336
10K_0402_1%

PR335
47K_0402_1%

12K_0402_1%

A

A

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title
Size
Date:

Document Number

Rev
1.0
Sheet

Monday, January 16, 2012
1

51

of

64

5

4

3

2

1

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205

PJ402

2

+3VALW P

2

1

1

+3VALW

PC401
1U_0603_10V6K

@ JUMP_43X118

1

D

PJ403

2

+5VALW P

2

D

@

RT8205_B+
PJ401

PR403
20K_0402_1%
1
2

PR404
20K_0402_1%
1
2

1
2

5

UG_5V

20

LX_5V

LGATE2

LGATE1

19

LG_5V

<50>
3
2
1

SPOK

1
+

2

+5VALWP

PC418
150U_B2_6.3VM_R45M

3
2
1
1
2

PR420 @
0_0402_5%
2
1

PC422
0.1U_0603_25V7K

RT8205_B+

PR419
0_0402_5%
2
1

PC421
4.7U_0805_10V6K

2

1

VL

Typ: 175mA

PC415
150U_B2_6.3VM_R45M

2
1
2

TPC8A03-H 1N SO8

PC417
@ 1U_0603_10V6K
2
1

1
5
6
7
8
4

PC419
680P_0603_50V7K

NC

PQ404
RT8205LZQW _W QFN24_4X4

PR410
4.7_1206_5%

PL402
4.7UH_VMPI1004AR-4R7M-Z01_10A_20%
1
2

18

VIN

VREG5
17

13

5
6
7
8

PC410
0.1U_0603_25V7K
2
1

PC409
2200P_0402_50V7K
2
1

PC408
4.7U_0805_25V6-K
2
1

1

3

4

2
FB1

REF

FB2

PC407
4.7U_0805_25V6-K
2
1

ENTRIP1

ENTRIP2

6

5

21

PHASE1

1
+

2

B

RT8205
TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)
TPS51125A
TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
(2)SMPS2=305KHZ(+3VALWP)

+5VALWP Imax=11.1A ; Ipeak=13.32A
1/2 Delta I=1.33A (F=300K Hz)
Vtrip=0.098V
Rds(on)=7.0m ohm(max) ; Rds(on)=5.1m ohm(typical)
Ilimit_min=0.098/7m=14.03A
Ilimit_max=0.098/5.1m=19.21A
Iocp=Ilimit+1/2Delta I=15.36A ~ 20.54A

A

3

+3.3VALWP Imax=7.5A ; Ipeak=9A
1/2 Delta I=1.113A (F=375K Hz)
Vtrip=0.169V
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Ilimit_min=0.169/18m=9.388A
Ilimit_max=0.169/15=11.26A
Iocp=Ilimit+1/2Delta I=10.5A~12.373A

Compal Secret Data

Security Classification
2010/06/30

Issued Date

3

PQ408
@ DTC115EUA_SC70-3

PC423
4.7U_0603_10V6K

EC_ON

PQ406
DTC115EUA_SC70-3

2

1

2

PR416 @
100K_0402_1%

2

1

1

VS

UGATE1

PHASE2

PR421 @
0_0402_5%
2
1

PQ407 @
2N7002KW _SOT323-3

2
1
PR417 @
402K_0402_1%

1

S

2
G

A

2,47>

D

3

PR415 @
200K_0402_1%
2
1

UGATE2

EN
4

2VREF_8205

PR414
100K_0402_1%
2
1

VL

PR408 PC413
2.2_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2

PC420
1U_0603_10V6K
2
1

3
5

PQ405B
2N7002KDW -2N_SOT363-6

VL

PR418
2.2K_0402_5%
2
1

EC_ON

2
1

PR413
0_0402_5%
2
1

22

16

8
7
6
5

ENTRIP2

6

ENTRIP1

<42,50> MAINPW ON

C

B+

B

PQ405A
2N7002KDW -2N_SOT363-6

23

BOOT1

VFB=2.0V

PQ402
TPC8037-H 1N SO8

1

2

PGOOD

BOOT2

PR411
499K_0402_1%
1
2

2

+

12

VREG3

4

PR412
100K_0402_1%

PC416
680P_0603_50V7K
2
1

1

LG_3V
PQ403
AO4712_SO8

1
2
3

PC414
150U_B2_6.3VM_R45M

PR409
4.7_1206_5%
2
1

PL401
3.3UH +-20% PCMC063T-3R3MN 6A
1
2

+3VALWP

ACPRN

+5VALW

4
24

GND

1
2
3

8
PR407
2 1
2 BST_3V 9
2.2_0603_5%
PC412
UG_3V 10
0.1U_0603_25V7K
LX_3V
11
1

PR406
88.7K_0402_1%
2

VO1

VO2

SKIPSEL

7

<42,47>

1

RT8205_B+

ENTRIP1

4

TONSEL

P PAD

15

25

1

14

AO4466L_SO8

PU401

1

PQ401

2

PC411
4.7U_0805_10V6K

8
7
6
5

PC406
2200P_0402_50V7K
2
1

C

PR405
154K_0402_1%
1
2

ENTRIP2

+3VLP

1

1

PC405
4.7U_0805_25V6-K
2
1

2

@ JUMP_43X118

PC404
4.7U_0805_25V6-K
2
1

2

PR402
30K_0402_1%
1
2

1

Typ: 175mA
PC403
0.1U_0603_25V7K
2
1

PC402
0.1U_0603_25V7K
2
1

B+

PR401
13K_0402_1%
1
2

2

JUMP_43X118

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Title

Compal Electronics, Inc.
3VALWP/5VALWP

Size
Document Number
Custom
Date:

Rev
1.0

QIWY3

Monday, January 16, 2012

Sheet
1

52

of

64

A

B

C

D

PJ501
1.5V_B+
470P_0603_50V7K

PC505
2
1

PC504
2
1

@

2

B+

1

1

JUMP_43X118
PL503
1
2

FBMA-L11-160808-121LMA30T_0603

BST_1.5V

2

TRIP

DRVH

9

DH_1.5V

3

EN

SW

8

LX_1.5V

4

VFB

V5IN

7
1

11

TP

5
6
7
8

TPC8A03-H 1N SO8
PC507
1U_0603_10V6K

2

6

DRVL

PQ502

+5VALW
DL_1.5V

PC510 @
1000P_0603_50V7K

RF

PL501
1UH +-20% PCMB104T-1R0MH 18A
1
2

4
1

TPS51212DSCR_SON10_3X3

2

VFB=0.7V
3
2
1

470K_0402_1%

2
PR506
1

2

PR505

1

84.5K_0402_1%

5

PR503
PC506
2.2_0603_5%
0.22U_0603_16V7K
1
2BST_1.5V-1 1
2

PC508

10

1

+1.5VP

1

220U_6.3V_M

VBST

1

PGOOD

PR504 @
4.7_1206_5%

PU501
1

2

1
2

1

1

PC501 @
.1U_0402_16V7K

PR502
47K_0402_5%

2

3
2
1

<42,48> SYSON

2200P_0402_50V7K
PC526
2
1

4
PR501
0_0402_5%
1
2

0.1U_0402_25V6

PQ501
TPC8037-H 1N SO8

PC503
10U_0805_25V6K
2
1

Iocp=13.58A~23.10A

2
PC502
10U_0805_25V6K
2
1

5
6
7
8

Freq= 266~314KHz , 290KHz(typ)

+
2
PJ502
+1.5VP

2
@

2

+1.5V
1

1

JUMP_43X118

PR507

3
2
1
10

PR511
PC516
2.2_0603_5%
0.22U_0603_16V7K
BST_1.5VSP_VGA
1
2BST_1.5VSP_VGA-1
1
2

2

TRIP

DRVH

9

DH_1.5VSP_VGA

3
2
1
PR516

1
2

PC527
470P_0603_50V7K

2200P_0402_50V7K

PC514
2
1

PC513
2
1

+

2

2

1

1

PJ504
+1.5VSP_VGA

2

2

@
PR517
0_0402_5%
2
1

2

+1.5VS_VGA
1

1

JUMP_43X118

VDDQ_SENSE <25>

1

1

+1.5VSP_VGA

PC519
0.1U_0402_10V7K

4

VFB=0.7V

PC518
220U_D2_4VY_R15M

TPS51212DSCR_SON10_3X3

PR513 @
4.7_1206_5%

1

11

PC517
1U_0603_10V6K

2

+5VALW
DL_1.5VSP_VGA

1

DRVL

6

LX_1.5VSP_VGA

PC520 @
1000P_0603_50V7K

7

2

8

TP

2

PL502
1UH_PCMC063T-1R0MN_11A_20%
1
2

TPCA8057-H 1N PPAK56-8

2

470K_0402_1%

PR515
1

RF

SW
V5IN

5

VFB

1

EN

4

B+

PQ504

2

3

0.1U_0402_25V6

100K_0402_1%

1.5V_VGA_PWROK
PR523
2
1
1
PR514

VBST

PU502

5

75K_0402_1%

2

PGOOD

PC512
10U_0805_25V6K
2
1

TPCA8065-H_PPAK56-8-5

1
2
1
2

PC515 @
.1U_0402_16V7K

2
1

4

1

PC511
10U_0805_25V6K
2
1

1.5VSP_VGA_B+
PQ503

+5VS

PR510
@ 0_0402_5%
1
2
PR512 @
47K_0402_5%

10,42,48,55,56> SUSP#

PR509
10K_0402_1%

PR522
0_0402_5%
1
2

2

7> FBVDDQ_PWR_EN

PL504
FBMA-L11-201209-121LMA50T_0805
1
2

2
11.5K_0402_1%

5

1

3

3

11.5K_0402_1%
PR518
10K_0402_1%

PJ505
+1.05VS

2

2
3

PQ506B

<10,48,55> SUSP

2
1

2N7002KDW-2N_SOT363-6

@ 1U_0603_10V6K

1

PC525

2

4

5

4

6

2

2N7002KDW-2N_SOT363-6

PR525
@ 0_0402_5%
1
2

PR520

100K_0402_1%
2

2

1

PQ507 @

S

4

Issued Date

Compal Secret Data
2010/06/30

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

+1.05VS_VGA

<25,48> DGPU_PWR_EN#

Security Classification

A

1

JUMP_43X118

2N7002KW _SOT323-3

2
G

PR528
@ 0_0402_5%
1
2

PC524
0.01u_0603_10V6K

D

@ 470K_0603_5%

1

PR521

2

PC523
1U_0603_10V6K

1

PR527
@ 0_0402_5%
1
2

1

2

PR519
100K_0402_1%

1

1

<10,42,48,55,56> SUSP#

PQ506A

<19,27,56> DGPU_PWROK

PR524
0_0402_5%
1
2

1
2
3

4

1

1

+5VALW

PR526
10K_0402_1%

8
7
6
5

PC521
10U_0805_25V6K
2
1

+5VALW

PQ505
TPC8A03-H 1N SO8

2
@

+1.05VS_VGA

2

+1.05VS

PC522
10U_0805_25V6K
2
1

Iocp=12.25A~20.77A

3

Freq= 266~314KHz , 290KHz(typ)

C

Title

Compal Electronics, Inc.
1.5VP/1.5VSP_VGA/1.05VSP_VGA

Size Document Number
Custom
Date:

Rev
1.0

QIWY3

Monday, January 16, 2012
D

Sheet

53

of

64

4

3

+3VS
PR602
100K_0402_5%
1

H_VCCSA_VID1

<10>

PR605
0_0402_5%
1
2

+V1.05S_VCCP_PWRGOOD <48,55>

+VCCSA_PHASE

PL601
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

PGND
1
SW

21

TPS51461RGER_QFN24_4X4

24

7

@

PC604
1000P_0603_50V7K

@

@

@

MODE
6

VREF

3

1

COMP

JUMP_43X118

VOUT

VIN
SLEW

+VCCSA_PWR_SRC

5

1 +VCCSA_PWR_SRC

4

1

SW

GND

@

2

8

1

SW
VIN

PJ601
2

9
2

SW

VIN

23

1

PR607
4.7_1206_5%

PGND

22

2

+VCCSAP

2

1

10U_0805_6.3V6M
PC616

10U_0805_6.3V6M
PC615

2

10

PC612
22U_0805_6.3V6M
1
2

11

PR606
PC603
2.2_0603_5%
0.22U_0603_16V7K
2+VCCSA_BT_1 1
2

PC611
22U_0805_6.3V6M
1
2

+VCCSA_BT 1

PC610
2200P_0402_50V7K
2
1

12

PC609
22U_0805_6.3V6M
1
2

BST
SW

2

C

2

0.1U_0603_25V7K
PC614
1
2

2200P_0402_50V7K
PC613

+3VALW

1

D

13
EN

14

+VCCSA_EN

PC608
22U_0805_6.3V6M
1
2

PGND

20

+VCCSA

2

PAD-OPEN 4x4m

PC607
0.1U_0402_10V7K
2
1

19

V5FILT

V5DRV

PU601

PGOOD

PC602
2.2U_0603_10V7K
1
2

1

+VCCSAP

The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.

+VCCSA_VID0

+VCCSA_VID1
15

2
1

18

17

PC601
1U_0603_10V6K

PR604
10_0402_1%
2
1

16

+VCCSA_PWRGD

+5VALW

VID1

output voltage adjustable network
D

H_VCCSA_VID0

PJ602

+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A

<10>

PR603
1K_0402_1%
2
1

VID0

<42> SA_PGOOD

1

PC606
22U_0805_6.3V6M
1
2

VCCSA Vout
0.9V
0.8V
0.725V
0.675V

2

VID[1]
0
1
0
1

+VCCSA_PWRGD

VID [0]
0
0
1
1

2

PR601
1K_0402_1%
2
1

PC605
22U_0805_6.3V6M
1
2

5

TP

25

C

@

PR608
2

1

33K_0402_5%
PR609
100_0402_5%
2
1

0.22U_0402_10V6K
2
PC618
3300P_0402_50V7K

1

2

1

PR610
4.99K_0402_1%

PC619
0.01U_0402_25V7K
1
2

PC617
2
1

PR611
0_0402_5%
2
1

+VCCSA_SENSE <10>

B

B

A

A

Compal Secret Data

Security Classification

Issued Date

2011/06/30

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
C
Date:

5

4

3

2

Compal Electronics, Inc.
VCCSAP/1.05S_VCCPP
Document Number

Rev
1.0

QIWY3
Monday, January 16, 2012

Sheet
1

54

of

64

5

4

3

2

1

PJ707

2

2

1

1

@

1

PC702
68P_0402_50V8J
2
1

2

1

PC705
22U_0805_6.3VAM

+1.8VSP

2

2

@

+1.8VS

1

1

JUMP_43X118
PJ702

2

+0.75VSP

2

1

1

+0.75VS

JUMP_43X118

PR705
10K_0402_1%

2

PJ704

2
PU702

NC

7

VREF VCNTL

6

GND

3
4

VOUT

NC

5

TP

9

2

1

@

+1.05VS

JUMP_43X118

PC708

2

PR706
1K_0402_1%

1

JUMP_43X118
PJ705
2 2
1 1

+1.05VS_VCCPP

1

8

1

2

NC

VIN

2

2

@

+3VALW

1U_0603_10V6K

B+

APL5336KAI-TRL_SOP8P8

1

PC711
10U_0603_6.3V6M

2

PC710
10U_0603_6.3V6M
2
1

PC712
0.1U_0402_16V7K
2
1

BST

LX_1.05VS_VCCP

DH

11

DH_1.05VS_VCCP

DL

10

1

+5VALW
3
2
1
1
2

54.9K_0402_1%

2 PR719 1

2
1

9

8

7

GND

TRIP
6

5

2

PC717
4.7U_0805_25V6-K
2
1

1

B+

B

+1.05VS_VCCPP

1
+

2 3

PC725
1U_0603_10V6K
A

PR721

1

1

1

1

PC723
PR717
1000P_0603_50V7K 4.7_1206_5%

V5

2

DL_1.05VS_VCCP

PGND

VSNS
COMP

0_0402_5%

2

JUMP_43X118

PL703
1UH +-20% PCMB104T-1R0MH 18A

TPCA8057-H 1N PPAK56-8

PQ703

TPS51219RTER_QFN16_3X3

GSNS

0.01U_0402_25V7K

2

PR720 @
2

1

2
1

1000P_0402_50V7K

PC716
4.7U_0805_25V6-K
2
1

PC715
2200P_0402_50V7K
2
1

PC719
0.1U_0402_25V6
2
1

PC722
220P_0402_50V7K
2
1

5

13

14
EN

MODE

12

4

2

@

TPCA8065-H_PPAK56-8-5

SW

5

PC721
0.01U_0402_25V7K

1

PC726

PC718
0.1U_0603_25V7K
1
2

3
2
1

REFIN

PGOOD

2

3

10_0402_1%

5

15

16

17
PAD

2
1

2
PR715

1
PR716
2

1

VREF

PC724

1

1

PR714
2.2_0603_5%
BST_1.05VS_VCCP
1
2

PQ702

2

PR718

A

1K_0402_1%

PR709
2

1
2
100K_0402_1%

PR713

PJ706

2

4

1

4

<9> VCCIO_SENSE

2

C

2
10_0402_1%

PC727
1000P_0402_50V7K

4

PC66
330U_D2_2VM_R6M

12K_0402_1%

PC720
0.1U_0402_25V6
2
1

10.7K_0402_1%

PU703

<9> VSSIO_SENSE

+0.75VSP

1.05VS_B+

B

PR723
0_0402_5%
1
2

+

+1.05VS_VCCPP OCP(min)=22.38A

PR712
100K_0402_1%
1
2

1
2

PR722
0_0402_5%
1
2

<48,54> +V1.05S_VCCP_PWRGOOD

S

PQ701
2N7002KW _SOT323-3

1

+3VS

PC714
@.1U_0402_16V7K

1

PR711

2

@ 10K_0402_1%

PR710
0_0402_5%
1
2

<10,42,48,53,56> SUSP#

D

2
G

PC713
0.1U_0402_10V7K
2
1

<10,48,53> SUSP

1

PR708
33K_0402_1%
1
2

3

C

PC709 @
68U_25V_M_R0.36

2

2

PJ703
JUMP_43X118
@

PC707
4.7U_0805_6.3V6K

PR707
@ 0_0402_5%
1
2

<48> 0.75VR_EN#

PJ701

@

1

<10,42,48> CPU1.5V_S3_GATE

1
2

1.8VSP_FB

1
PR724 @
0_0402_5%
1
2

D

PC704
22U_0805_6.3VAM

1
PR703
20K_0402_1%

2

NC

+1.5V

1

1
1

2

PR704
1M_0402_5%

FB=0.6Volt

PC706 @
0.1U_0402_10V7K

2

0_0402_5%

6

+1.8VSP

1

EN_1.8VSP

2

TP

11

PR701

1

7

<10,42,48,53,56> SUSP#

EN

FB

1

SVIN

5

3

1 2

8

PC701
22U_0805_6.3VAM

LX

PL702
1UH_PH041H-1R0MS_3.8A_20%
1
2

1.8VSP_LX

2

PVIN

2

PC703
PR702
680P_0603_50V7K 4.7_1206_5%

9

LX

NC

PVIN

1

10

2

D

SY8033BDBC_DFN10_3X3

4

PU701
1.8VSP_VIN

1

+5VALW

PG

JUMP_43X118
PL701 @
HCB1608KF-121T30_0603
1
2

Compal Secret Data

Security Classification
2010/06/30

Issued Date

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

Compal Electronics, Inc.
1.8VSP/0.75VSP/1.05VS_VCCPP

Size
Document Number
Custom
Date:

Rev
1.0

QIWY3

Monday, January 16, 2012

Sheet
1

55

of

64

A

B

C

D

+VGA_CORE

1
2

1

2

+

PC809 @
680P_0402_50V7K
SNUB2_VGA
2
1

VSUM-_VGA

1
+
2

PC808
470U_D2_2VY_R9M

PR810
1_0402_1%

PC807
470U_D2_2VM_R9M

PR809
10K_0402_1%

1

V2N_VGA

1
2

PR807 @
4.7_1206_5%
2
1

TPCA8057-H 1N PPAK56-8

PR808
3.65K_0402_1%
2
1

5
3
2
1

TPCA8057-H 1N PPAK56-8

3

1
+
2

PC867
470U_D2_2VY_R9M

3
2
1

3
2
1
5

3
2
1

VSUM+_VGA ISEN2_VGA

2

+VGA_CORE

Near VGA Core

PC829
4.7U_0603_6.3V6M
2
1

PC830
4.7U_0603_6.3V6M
2
1

PC831
4.7U_0603_6.3V6M

PC843
0.1U_0402_10V7K
2
1

PC844
0.1U_0402_10V7K
2
1

PC845
0.1U_0402_10V7K
2
1

2
PC846
0.1U_0402_10V7K

PC822
4.7U_0805_6.3V6K

2

PC821
22U_0805_6.3V6M
2
1

1

PC835
4.7U_0805_6.3V6K

PC828
4.7U_0603_6.3V6M
2
1
PC842
0.1U_0402_10V7K
2
1

PC820
47U_0805_6.3V6M

PC827
4.7U_0603_6.3V6M
2
1
PC841
0.1U_0402_10V7K
2
1

1

PC826
4.7U_0603_6.3V6M
2
1
PC840
0.1U_0402_10V7K
2
1

PC833
4.7U_0805_6.3V6K
2
1

2

PC819
22U_0805_6.3V6M
2
1

1

PC832
4.7U_0805_6.3V6K
2
1

PC818
4.7U_0603_6.3V6M

PC817
4.7U_0603_6.3V6M
2
1

PC816
4.7U_0603_6.3V6M
2
1

PC815
4.7U_0603_6.3V6M
2
1

PC814
4.7U_0603_6.3V6M
2
1

PC813
4.7U_0603_6.3V6M
2
1

PC812
4.7U_0603_6.3V6M
2
1

2
1
2

PC825
4.7U_0603_6.3V6M
2
1

1
<42>

PC818
PC825,PC827,PC828,PC829
PC839,PC841,PC844,PC845
3

3
2
1

BOOT1_1_VGA

2

1

PC855
10U_0805_25V6K
2
1

PC854
10U_0805_25V6K

PC853
2200P_0402_50V7K
2
1

PC852
0.1U_0402_25V6
2
1

4

PC856
0.22U_0603_10V7K
1
2

3
2
1

PR827
2.2_0603_5%
2
1

PQ808

TPCA8065-H_PPAK56-8-5
4

UGATE1_VGA

PQ804

5

PQ806@GL1
PQ808@GL1

5

<24>

PR828
2.61K_0402_1%
NTC_VGA
2
1

TPCA8065-H_PPAK56-8-5
PL804
0.36UH_VMPI1004AR-R36M-Z03_30A_20%

Layout Note:
Place near Phase1 Choke

3

+VGA_CORE
V1N_VGA

VSUM-_VGA

1
+
2

1
+
2

PC861
470U_D2_2VM_R9M

1_0402_1%

1
PR833
2

2

1

4

2

PR832
10K_0402_1%

PR830 @
4.7_1206_5%
2
1

PR831
3.65K_0402_1%
2
1

5

VSUM-_VGA

1

PC860
470U_D2_2VM_R9M

3
2
1

PH801
10K_0402_1%_TSM0A103F34D1RZ

4

TPCA8057-H 1N PPAK56-8

4

LF1_VGA
PQ806

3
2
1

1

LGATE1_VGA

PQ805
TPCA8057-H 1N PPAK56-8

5

PHASE1_VGA

2

PR834
11K_0402_1%
2
1

PC859
0.033U_0603_25V7K
2
1

PC858
0.22U_0603_10V7K
2
1

1
1

2

+VGA_B+
VSSSENSE_VGA

PR837
1.43K_0402_1%
1
2

VSUM+_VGA
ISEN1_VGA
4

PC866
0.1U_0402_16V7K

2

1

4

PR826 @
82.5_0402_5%

2

PR836
10_0402_1%
1
2

2

1

PR835
0_0402_5%
1
2

<24> VSSSENSE_VGA

1

PC862
1000P_0402_50V7K

2

PC857
330P_0402_50V7K

2

2

PC864 @
0.01U_0402_25V7K

1

VSUM_VGA_N001

PR825
10_0402_1%

PR829
0_0402_5%

+5VS

VSUM+_VGA

PC863 @
330P_0402_50V7K
2
1

<24> VCCSENSE_VGA

@ 0_0402_5%
2

VGA_IMVP_IMON

VSUM-_VGA
2

PC811
4.7U_0603_6.3V6M
2
1

1
PC851
0.22U_0603_25V7K

PC850
1U_0603_10V6K
2
1

1
2

+5VS

0.047U_0402_16V7-K
1
2
PR850
11K_0402_1%

PR823
1_0402_5%
1
2

PC849
0.22U_0402_10V6K

1
2

1
2

0_0402_5%
2
+VGA_B+

BOOT1_VGA

2

PR824
30K_0402_1%

1

<23>

PR847
0_0402_5%
1
2
1

ISEN1_VGA

+VGA_CORE

<23>

<23>
GPU_VID0

<23>
GPU_VID1

<23>
GPU_VID2

PR846
0_0402_5%
1
2

PR845
0_0402_5%
1
2

PR819

ISEN2_VGA

2

PR822
267K_0402_1%

PC848
0.22U_0402_10V6K

2FB2_VGA1

<23>
GPU_VID3

ISL62883CHRTZ-T_TQFN40_5X5

VSEN_VGA

1

1

PC847
150P_0402_50V8J

PC824
1U_0603_10V6K

2

PR820
1.69K_0402_1%
1
2

4

2

Under VGA Core

PC839
0.1U_0402_10V7K
2
1

PR818
499_0402_1%
PC837
2FB1_VGA1
2

PR821
VIN_VGA 1

3

PR844
0_0402_5%
1
2

PR843
0_0402_5%
1
2

40
39
38
37
36
35
34
33
32
31
11
12
13
14
15
16
17
18
19
20

AGND

390P_0402_50V7K

PC838
33P_0402_50V8J
1
2

4

+5VS

PC874
2
1

1

41

RTN_VGA
ISUM-_VGA

1
2

PC836
1000P_0402_50V7K

PR817
8.06K_0402_1%
2
1

PR816 @
249K_0402_1%
1
2

PC823
22P_0402_50V8J

30
29
28
27
26
25
24
23
22
21
1

COMP_VGA
FB_VGA
2ISEN3_VGA

1

BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1

PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

2

VW_VGA

PH802

1
2
3
4
5
6
7
8
9
10

VDD_VGA

2

470K_0402_5%_TSM0B474J4702RE
2
1
2

PR863
1

4

LF2_VGA
PQ803

1

PC810
1U_0603_10V6K
1
2

CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0

PU801

PR864 @
0_0402_5%

4.02K_0402_1%

PR842
0_0402_5%
1
2

PSI#_VGA

+VGA_CORE

ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1

1

<23,42> VGA_AC_DET

LGATE2_VGA

PQ802

2

PR865
@ 100K_0402_5%
1
2

+3VS

PL803
0.36UH_VMPI1004AR-R36M-Z03_30A_20%

PD801 @
RB751V-40_SOD323-2
2
1

PR813
147K_0402_1%
2
1

2

TPCA8065-H_PPAK56-8-5

UGATE2_VGA

PC865 @
680P_0402_50V7K
2
1 SNUB1_VGA

1 PR838
0_0402_5%

<23> DPRSLPVR_VGA

GPU_VID6

CLK_ENABLE#_VGA

PR812
2.2K_0402_1%
1
2

+3VS

DGPU_PWROK

BOOT2_2_VGA

@ .1U_0402_16V7K

RBIAS_VGA

>

PR811
2
1
1.91K_0402_1%

PR814
0_0402_5%
1
2

BOOT2_VGA

4

PC805
0.22U_0603_10V7K
1
2

DPRSLPVR_VGA-1

2.2K_0402_1%
PR806 @
1.91K_0402_1%
1
2

+3VS

4
PR804
2.2_0603_5%
2
1

PHASE2_VGA

0_0402_5%
PR805
1
2

1

PC834
4.7U_0805_6.3V6K
2
1

PC806

2

GPU_VID4

1

GPU_VID5

<10,42,48,53,55> SUSP#
PR815 @
1
2

<23> DPRSLPVR_VGA

1

PR803 @
0_0402_5%
1
2

PQ801

B+

TPCA8065-H_PPAK56-8-5

PR802
PR801
0_0402_5%
0_0402_5%
1
2VRON_VGA

<18> NVDD_PWR_EN

2

2

PC804
10U_0805_25V6K
2
1

5
2

PQ807

PC803
10U_0805_25V6K

PQ801@GL1
PQ802@GL1

1

1

PL801
HCB4532KF-800T90_1812
1
2

PC802
2200P_0402_50V7K
2
1

10K_0402_1%
2

+VGA_B+

PC801
0.1U_0402_25V6
2
1

10K_0402_1%
2

PR862
GPU_VID0
1

PJ801 @
JUMP_43X118
1

5

10K_0402_1%
2

10K_0402_1%
2
PR858
GPU_VID4
1

PR861
1

10K_0402_1%
2
PR857
1

GPU_VID1

10K_0402_1%
2

10K_0402_1%
2

10K_0402_1%
2

PR856
GPU_VID0
1

PR860
1

10K_0402_1%
2

PR855
GPU_VID1
1

GPU_VID2

10K_0402_1%
2

PR854
GPU_VID2
1

PR859
GPU_VID3
1

10K_0402_1%
2

PR853
GPU_VID3
1

GPU_VID5

10K_0402_1%
2

PR852
GPU_VID4
1

GPU_VID5

GL1:0.9V(110000)
GT:0.975V(101010)

PR851
1

+VDD33MISC

Compal Secret Data

Security Classification

Issued Date

2011/06/30

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

VGA_COREP
Size

B

C

Document Number

Rev
1.0

QIWY3 LA-8001P
Date:

A

Compal Electronics, Inc.

Monday, January 16, 2012
D

Sheet

56

of

64

1

2P: 36K
1P: 26.1K

BSTA1

HG2
LG2

6132P_VCCP

BST1

<58>
PR930 2
1
0_0402_5%

HG1

<58>
PR931 2 BST1_1 2
1
1
4.7_0603_5%
PC922
0.22U_0603_10V7K

CSP3

<58>

CSCOMP

1

2

806_0402_1%

DROOP

A

<42>

IMVP_IMON

PUT COLSE
TO VCORE
Phase 1
Inductor

CSP2A

2
1

2Phase: @
1Phase: install

+5VS

PR9372
6.98K_0402_1%

Option for
2 phase CPU
SWN3

<58>
CSP3

3Phase: @
2Phase: install

B

<58>

SWN1

<58>

1

SWN2

1

PC931
0.047U_0402_16V7K

2

PR9452
6.98K_0402_1%

PH903
100K_0402_1%_TSM0B104F4251RZ

1

2

PC927
0.047U_0402_16V7K
PR946 1

3P: 1500p
2P: 1200p

PR9412
6.98K_0402_1%

2

<58>

CSREF

PC934
2
1500P_0402_50V7K

1

PR949 2
130K_0603_1%

SWN1

1

PR951 2
130K_0603_1%

SWN2

1

PR954 2
130K_0603_1%

SWN3

PC969@QC
1

2 PC969
330P_0402_50V7K

1

2 PC936
330P_0402_50V7K

PR952
NTC_PH201
1
2
75K_0402_1%

1

1

PC932
1000P_0402_50V7K

PR976 @
20K_0402_1%
2
1

CSREF

2
1

CSCOMP
PC935
1
2

23.7K_0402_1%

CSREF

1000P_0402_50V7K

3P: 806
2P: 1K

<58>

+5VS

3P: install
@

CSREF
CSP1

CSSUM

PC937
1
2

SW1

Option for
1 phase GFX

TSENSE

3P: 21K
2P: 12.4K

1
.1U_0402_16V7K

PR955

<58>

PC925
0.047U_0402_16V7K2P:

CSP2

806_0402_1%

3P: 23.7K
2P: 24.9K

SW2

CSREF

PR939

2

2

2

PC933

1

PR950
1

1

8.06K_0402_1%

0.033u_0402_16V7K

TRBST#

1

1

DRVEN
PC924
2
.1U_0402_16V7K

CSP1
CSP2
CSP3

PR943
PC929
2
1COMP_CPU1 2
1
6.04K_0402_1%
2200P_0402_50V7K

PR948

<58>

3P: 73.2K
2P: 41.2K

PR934 2
73.2K_0402_1%

22P_0402_50V8J

PR944
PC930
1
2FB_CPU3 1
2
10_0402_1%
0.033u_0402_16V7K
PR947
FB_CPU2
1
2

SW1A

1

<58>

6132_PWM <58>

1

2

+5VS

PC920
2.2U_0603_10V7K

LG1

2

PC926
2
1

1 PR940 2
1K_0402_1%

PR921
PC918
2 BSTA1_12
1
2.2_0603_5%
<58>
0.22U_0603_10V7K
PC919
<58>
PR924 2 BST2_1 2
1
1
4.7_0603_5%
<58>
0.22U_0603_10V7K

C

1
PR928 @
0_0402_5%

LG1A

BST2

100K_0402_1%_TSM0B104F4251RZ

PUT COLSE
TO V_GT
HOT SPOT

1
HG1A

2

45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

PR975 @
20K_0402_1%
2
1

B

PR942
PC928
1
2FB_CPU1 1
2
49.9_0402_1%
470P_0402_50V7K

<58>

PH902

1
PR935 @
0_0402_5%

PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA

3P: 22p
2P: 10p

PC923
1000P_0402_50V7K
VSP

SWN2A

6132_PWMA <58>

TSENSE

VSN

<58>

2

PR918
1
2
36K_0402_1%

1

1
2
21K_0402_1%

2

PR938
1
2
0_0402_5%

<9> VCCSENSE

CSP2A

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

PR936
1
2
0_0402_5%

TRBST#
FB_CPU
COMP_CPU

2

VGATE

1

<16>
<9> VSSSENSE

CSSUMA

DIFFA
TRBSTA#
FBA
COMPA
IMONA
ILIMA
DROOPA

1
2

1
PR933
10K_0402_5%

PC972 @
43P_0402_50V7K
1
2

SWN1A

2P: install
1P: @

PC913
0.047U_0402_16V7K
1
2
PR916
5.49K_0402_1%

.1U_0402_16V7K

VCC
PWMA
VDDBP
BSTA
VRDYA
HGA
EN
SWA
SDIO
LGA
ALERT#
BST2
SCLK
HG2
VBOOT
SW2
NCP6132AMNR2G_QFN60_7X7
ROSC
LG2
VRMP
PVCC
VRHOT#
PGND
VRDY
LG1
VSN
SW1
VSP
HG1
DIFF
BST1

ILIM_CPU
DROOP

1
2

PR932
75_0402_1%
2
1
<42> VR_HOT#

6132_VCC

0.01U_0402_25V7K

+1.05VS

PC914
1
2

TRBST#
FB
COMP
IOUT
ILIM
DROOP
CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1
TSNS
DRVEN
PWM

.1U_0402_16V7K

PR923
1
2
54.9_0402_1%

PR922 2

1
<9> VR_SVID_DAT
<9> VR_SVID_ALRT#
<9> VR_SVID_CLK

5.49K_0402_1%
2

PU901

1
2.2U_0603_10V7K
2
PR920
VR_RDYA
3
VR_ON_CPU
4
1
2
<42>
VR_ON
0_0402_5%
PC917
VR_SVID_DAT1 5
VR_SVID_ALRT# 6
PR927
PR925
VR_SVID_CLK
7
95.3K_0402_1%
0_0402_5%
8
1
2 VBOOT
10K_0402_1%
ROSC_CPU
9
1 PR926 2VR_SVID_DAT1
1
2
VRMP
10
1
2
CPU_B+
VR_HOT#
11
PR929 1K_0402_1%
VGATE
12
13
PC921
14
+3VS
DIFF_CPU
15

130_0402_1%

1
2

PC916

.1U_0402_16V7K

+1.05VS

PR919 2
1
2_0603_5%
PC915
1
2

PR913
1

TSENSEA

CSREFA

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46

+5VS

CSP1A
PC911
1000P_0402_50V7K

PC910
0.047U_0402_16V7K

2

1PR914
2
21.5K_0402_1%
CSCOMPA

2
1
2

PR917
10K_0402_1%

VR_RDYA

CSREFA

SWN1A

CSREFA <58>

+3VS

CSREFA

1000P_0402_50V7K

2P: 1.65K
1P: 1K

2P: install
1P: @

91K_0603_1%

<10> VSS_AXG_SENSE

C

PR912 2

SWN2A

91K_0603_1%

1

PC912
1000P_0402_50V7K

1

2200P_0402_50V7K

2P: 21.5K
1P: 15.8K
<10> VCC_AXG_SENSE

PR911 2

PC906
1
2

DROOPA

2

1

5.11K_0402_1%

1

1

1.65K_0402_1%

PR915
2

1K_0402_1%

PR910 10P_0402_50V8J PC909
2 COMPA1 1
2

CSCOMPA

8.25K_0402_1%

1

PR906

220K_0402_5%_ERTJ0EV224J

NTC_PH203

8.25K_0402_1%

560P_0402_50V7K
PR909 2

1

PR907 1
2
165K_0402_1%

2

FBA2

1
2
10_0402_1%

PC908
1
2

1

PC907
1
2

PR974 @
20K_0402_1%
2
1

PR908

D

2

24K_0402_1%

2P: 24K
1P: 24.9K

806_0402_1%

PUT COLSE
TO GT
Inductor

PH901

1

2

2

8.06K_0402_1%

1

1

FBA1

PC903
1
2

.1U_0402_16V7K
1 PR904 2

PR903

2

PC905
0.033u_0402_16V7K
2
1

1

CSP2A
CSP1A
TSENSEA

PR902
TRBSTA#

1

2

PC902
2

1

D

PR905
1
2
75K_0402_1%

PC901
0.033u_0402_16V7K
FBA3
1
2

2

PC904
1
2

PR901
10_0402_1%
1
2

3

330P_0402_50V8J

4

1200P_0402_50V7K

5

PR953

1

PUT COLSE
TO VCORE
HOT SPOT

3P: install
2P: @

2

165K_0402_1%

A

PH904

2

1
220K_0402_5%_ERTJ0EV224J

Compal Secret Data

Security Classification
Issued Date

2011/06/30

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
CPU_CORE

Size Document Number
Custom
Date:

Rev
1.0

QIWY3

Monday, January 16, 2012

Sheet
1

57

of

64

5

4

3

2

1

3
2
1
<57>

4

LG2

2

10_0402_1%
<57>

3
2
1

SWN1

PC946
2200P_0402_25V7K
2
1

PC944
0.1U_0402_25V6
2
1

1
2

CSREF <57>

PC943
10U_0805_25V6K
2
1

2

PR958
1

D

1

SW2
PQ904

V1N_CPU2

PC942
10U_0805_25V6K
2
1

5

TPCA8065-H_PPAK56-8-5

PC971
470P_0603_50V7K

PC947

220U_25V_M

PC973
1000P_0603_50V7K
2
1

<57>

+VCC_CORE

PL903
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
4

1

PC948

3

PR957
4.7_1206_5%
2

3

2

4

HG2

V2N_CPU 2 PR959 1
10_0402_1%

SNUB_CPU2

2

+

<57>

TPCA8057-H 1N PPAK56-8

4

2

CPU_B+
1

1

1

+

PC945
100U_25V_M_R0.36

1
2

+VCC_CORE

1

5

PC941
2200P_0402_25V7K
2
1

PC940
0.1U_0402_25V6
2
1

PL901
HCB4532KF-800T90_1812
1
2

PR956
4.7_1206_5%

1SNUB_CPU1

4

LG1

3
2
1

<57>

TPCA8057-H 1N PPAK56-8

PQ903

PQ902

PL902
0.36UH_VMPI1004AR-R36M-Z03_30A_20%

SW1
5

<57>

CPU_B+
B+

PC970
470P_0603_50V7K

D

PC939
10U_0805_25V6K
2
1

TPCA8065-H_PPAK56-8-5

5

4

HG1

3
2
1

<57>

PC938
10U_0805_25V6K
2
1

CPU_B+
PQ901

2

680P_0402_50V7K

CSREF

SWN2

<57>

PC949

2

680P_0402_50V7K

EN

SW

C

SW3

7

+VCC_CORE

PL904
1

4

2

3

QC 45W CPU
VID1=0.9V
IccMax=94A
Icc_Dyn=66A
Icc_TDC=52A
R_LL=1.9m ohm
OCP~110A

1

3

HG3

8

VCC

GND
DRVL

6
PQ906
LG3

5

NCP5911MNTBG_DFN8_2X2

V3N_CPU 2 PR964

1

3
2
1

4

0.36UH_VMPI1004AR-R36M-Z03_30A_20%
PR963
4.7_1206_5%
2

4

PC955
2.2U_0603_10V7K

SNUB_CPU3

2

1

+5VS

2 PR961 1EN_CPU3
2K_0402_1%
2
1VCC_CPU3
PR962
0_0402_5%

DRVH

TPCA8057-H 1N PPAK56-8

DRVEN

PWM

9

5

<57>

FLAG

3
2
1

2

<57> 6132_PWM

BST

PC954
2200P_0402_25V7K
2
1

4
PU902
1
C

PC951
10U_0805_25V6K
2
1

1

PC950
0.22U_0603_10V7K

TPCA8065-H_PPAK56-8-5

PQ905

2

5

BST3_1

PC953
0.1U_0402_25V6
2
1

PR960
1
2
4.7_0603_5%

PC952
10U_0805_25V6K
2
1

CPU_B+
BST3

1

CSREF

DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=36A
R_LL=1.9m ohm
OCP~65A

10_0402_1%
SWN3

<57>

PC956
680P_0402_50V7K

2

3Phase: install
2Phase:: @

HG2A

7

SW2A

3
2
1

8

6

CSREFA <57>

4

1

10_0402_1%

SWN1A <57>

PC964
2200P_0402_25V7K
2
1

PC963
0.1U_0402_25V6
2
1

PC962
10U_0805_25V6K
2
1
1

PR970
2
1
10_0402_1%

CSREFA

SWN2A <57>

PC967 @

2

680P_0402_50V7K
A

QC 45W GT2
VID1=1.23V
IccMax=46A
Icc_Dyn=37A
Icc_TDC=38A
R_LL=3.9m ohm
OCP~55A

DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A

Compal Secret Data

Security Classification

Issued Date

2011/06/30

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

4

3

2

Compal Electronics, Inc.
CPU_CORE

Size
C
Date:

5

PR969 @
4.7_1206_5%

0_0402_5%

LG2A

PR973

PQ910

5

NCP5911MNTBG_DFN8_2X2
PC966
2.2U_0603_10V7K

2

GND
DRVL

PC961
10U_0805_25V6K
2
1

PL907
0.36UH 20% PDME064T-R36MS1R405 24A
+VCC_GFXCORE_AXG
1
2

1

VCC

SW

3
2
1

PR971 1

DRVH

EN

2

2

@ 680P_0402_50V7K

2

PWM

9

TPCA8057-H 1N PPAK56-8

1
1
PR972

0_0402_5%

2

@ 4.7_1206_5%

+5VS

2 PR966 1EN_GFX2 3
2K_0402_1%
4
2
1VCC_GFX2
PR968
0_0402_5%

FLAG

B

SNUB_GFX2

DRVEN

1
PR967
2
SNUB_GFX1
2

PC968

2

<57> 6132_PWMA

BST

TPCA8065-H_PPAK56-8-5

2

5

PC960
2200P_0402_25V7K
2
1

PC959
0.1U_0402_25V6
2
1

PC958
10U_0805_25V6K
2
1

1

PC965
0.22U_0603_10V7K
4

1

3
2
1
A

BSTA2_1

2

PU903
1

+VCC_GFXCORE_AXG

TPCA8057-H 1N PPAK56-8

4

LG1A

1 PR965

2.2_0603_5%

PL905
0.36UH 20% PDME064T-R36MS1R405 24A
1
2
PQ909

<57>

PQ908
BSTA2

SW1A
5

<57>

CPU_B+

2Phase: install
1Phase:: @

5

4

HG1A

3
2
1

<57>

TPCA8065-H_PPAK56-8-5

5

PQ907

PC957
10U_0805_25V6K
2
1

CPU_B+

B

Document Number

Rev
1.0

QIWY3
Monday, January 16, 2012

Sheet
1

58

of

64

5

4

+VCC_CORE
1

2

3

2

+CPU_CORE
1

PC1
10U_0805_6.3VAM

2

1
PC2
10U_0805_6.3VAM

2

1
PC3
10U_0805_6.3VAM

2

1

Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_GFXCORE_AXG

Socket Bottom

5 x 22 ȝF (0805)
5 x (0805) no-stuff
sites

Socket Top

7 x 22 ȝF (0805)
2 x (0805) no-stuff
sites

1
PC4
10U_0805_6.3VAM

2

PC5
10U_0805_6.3VAM

+VCC_GFXCORE_AXG

D

2

1

2

1

2

1

2

1

2

1

2

1

2

PC19
22U_0805_6.3V6M

2

+VCC_CORE

1

PC18
22U_0805_6.3V6M

2

1
PC11
10U_0805_6.3VAM

PC17
22U_0805_6.3V6M

2

1
PC10
10U_0805_6.3VAM

PC16
22U_0805_6.3V6M

2

1
PC9
10U_0805_6.3VAM

PC15
22U_0805_6.3V6M

2

1
PC8
10U_0805_6.3VAM

PC14
22U_0805_6.3V6M

2

1
PC7
10U_0805_6.3VAM

PC13
22U_0805_6.3V6M

2

1
PC6
10U_0805_6.3VAM

PC12
22U_0805_6.3V6M

1

+1.05VS

2 3

C

1
+

1
+

2 3

2

PC72
22U_0805_6.3V6M

PC32,PC49,PC54,PC55,PC56

1
+

2

PC38,PC39,PC40,PC41

PC78
470U_D2_2VM_R9M

+

330U_D2_2VM_R9M

PC77 @

330U_D2_2VM_R9M

PC76

330U_D2_2VM_R9M

PC75@DC

330U_D2_2VM_R9M

PC74

PC73

330U_D2_2VM_R9M

2 3

1

2

PC68
330U_D2_2VM_R6M

+

1

PC56
22U_0805_6.3V6M

2 3

1

2

PC35
22U_0805_6.3V6M

2 3

+

1

PC59@DC

2 3

PC8,PC21,PC22,PC63
1

2

PC55
22U_0805_6.3V6M

+

2

1

PC34
22U_0805_6.3V6M

2 3

1

2

2

PC67
330U_D2_2VM_R6M

B

+

2

1

1

1
PC71
22U_0805_6.3V6M

+VCC_CORE
1

2

2

PC54
22U_0805_6.3V6M

2

PC65
22U_0805_6.3V6M

2 3

2

1

1

PC33
22U_0805_6.3V6M

2

1
PC70
22U_0805_6.3V6M

2

+

2

PC53
22U_0805_6.3V6M

2

1
PC69
22U_0805_6.3V6M

2

2 3

1

PC59
330U_D2_2VM_R9M

1

2

1
PC64
22U_0805_6.3V6M

+

PC58
330U_D2_2VM_R9M

2

1
PC63
22U_0805_6.3V6M

PC57
330U_D2_2VM_R9M

2

1
PC62
22U_0805_6.3V6M

1

1

1

PC32
22U_0805_6.3V6M

2
1

1

2

PC52
22U_0805_6.3V6M

PC48
22U_0805_6.3V6M

1

2

1

PC31
22U_0805_6.3V6M

2

2 3
1

1

2

PC51
22U_0805_6.3V6M

PC47
22U_0805_6.3V6M

C

PC61
22U_0805_6.3V6M

2

1

+

1

2

PC30
22U_0805_6.3V6M

2

2

PC50
22U_0805_6.3V6M

PC46
22U_0805_6.3V6M

2

2

+1.05VS
1
1
PC29
22U_0805_6.3V6M

2

2

1

PC49
22U_0805_6.3V6M

PC45
22U_0805_6.3V6M

2

1

1

PC28
22U_0805_6.3V6M

2

1

2

1

1

PC27
22U_0805_6.3V6M

PC44
22U_0805_6.3V6M

1

2

1

1

PC26
22U_0805_6.3V6M

2

1

2

1

PC43
22U_0805_6.3V6M

1

2

1

PC42
22U_0805_6.3V6M

2

1

PC41
22U_0805_6.3V6M

1

PC40
22U_0805_6.3V6M

2

PC24
22U_0805_6.3V6M

PC39
22U_0805_6.3V6M

2

1
PC23
22U_0805_6.3V6M

PC38
22U_0805_6.3V6M

2

1
PC22
22U_0805_6.3V6M

PC37
22U_0805_6.3V6M

2

1
PC21
22U_0805_6.3V6M

PC36
22U_0805_6.3V6M

2

1
PC20
22U_0805_6.3V6M

PC25
22U_0805_6.3V6M

1
1

D

B

DC:PC73,PC74,PC76(330uF/9m)+PC78(330uF/6m)
QC:PC73,PC74,PC75,PC76(330uF/9m)+PC78(470uF/9m)

A

A

Compal Secret Data

Security Classification
2011/06/30

Issued Date

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR DECOUPLING

Size

Document Number

Rev
1.0

QIWY3 LA-8001P
Date:

Monday, January 16, 2012

Sheet
1

59

of

64

5

4

3

2

9HUVLRQFKDQJHOLVW 3,5/LVW
,WHP

D

5HVHUYHX)IRU&KDUJHU,&



0RGLI\/LVW

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5HVHUYH3&
FKDQJH3535353535353535WRRKP
DGG3&3&3&3& S)



%WHVW
D

(0,5HTXHVW



&RPELQH9



5HPRYHRQHSRZHUUDLO96B9&&33
3RS353535



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'LVFKDUJHIRU96B9*$E\195HTXHVW



5HVHUYH35



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6HW9*$B&25(9%227YROWDJH



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IRU&38B&25(ORDGOLQHDGMXVW



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DGG353&



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SRS3&34353835
XQSRS35



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FKDQJH3535WR.



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DGG3/3&3/3/
DGG3&3&3&3&3&3&3&



&WHVW




B

3*

3DJHRI
IRU3:5





C

5HDVRQIRUFKDQJH

1



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IRU&38WUDQVLHQW

%WHVW

%WHVW



IRU(0,5HTXHVW



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UHVHUYHFRQQHFW3&+B3:5B(1IRUSRZHUVHTXHQFH
UHVHUYHFRQQHFW&389B6B*$7(IRUSRZHUVHTXHQFH



&WHVW



IRUWKHUPDOUHTXHVWWRUHGXFHWHPSHUDWXUH



FKDQJH3434



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DGMXVW963B9*$2&3



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FKDQJH3535WR1$
FKDQJH35WRRKP



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7RDGMXVW9$/:E\+:UHTXHVW



FKDQJH35WR.



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8VLQJ*WRUHSODFH.%IXQFWLRQQHHGWRDGG
RUUHVHUYHUHVLVWRU



$GG35DQGUHVHUYH35SXOOKLJKWR9$/:
$GG35SXOOGRZQ



3UH03

C

B

A

A

2011/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PIR (PWR)
Size Document Number
Custom
Date:

Rev
1.0

QIWY3
Sheet

Monday, January 16, 2012
1

60

of

64

5

4

3

2

9HUVLRQFKDQJHOLVW 3,5/LVW
,WHP

D

5HDVRQIRUFKDQJH

3*

1

3DJHRI
IRU3:5

0RGLI\/LVW

'DWH

3KDVH



3UH03

5HVHUYH353535



3UH03

FKDQJH3&WRX)



3UH03



7, VVXJJHVWLRQWKDWVQXEEHUVKRXOGEHILUVWDW5WKDQ&



FKDQJH35DQG3&RUGHU



5HVHUYHUHVLVWRUIRUDGMXVWFXUUHQWEDODQFH





7RUHGXFHQRLVH



D

C

C

B

B

A

A

2011/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PIR (PWR)
Size Document Number
Custom
Date:

Rev
1.0

QIWY3
Sheet

Monday, January 16, 2012
1

61

of

64

5

4

3

2

1

QIWY3 HW PIR List
OP!EBUF!!!QBHF!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF

D

C

B

2
3
4
5
6
7
8
9
:
21
22
23
24
25
25
26
27

Q8
Q27
Q27
Q27
Q32
Q47
Q47
Q53
Q59
Q56
Q57
Q58
Q2:
Q52
Q2:
Q34
Q48

Sftfswf!S75
Sftfswf!S2568-S2566-S2558
Sftfswf!R229-S2231-S2232
Dibohf!BD`QSFTFOU!Qvmm!ijhi!tpvsdf!up!,4W`ETX
Sfnpwf!S39:
Sftfswf!K9-R215-D644-D637-S547
Dibohf!KQ2!qjo3-35-63!qpxfs!tpvsdf!up!,4WT`XMBO`BPBD
Dibohf!FD!HQJP!qjo!tfuujoh!)Jnqbdu!qjo!29-82-83-237-239*
Sftfswf!K22-K25-R259-R25:-D49-D4:
dibohf!V5:!tzncpm!!)xjuipvu!HOE!qbe*
dibohf!V51-V7:!tzncpm!!)xjuipvu!HOE!qbe*
dibohf!KQ21!uzqf!up!TQ12112C911
Sftfswf!S318-S335!up!dpoubdu!XMBO!xblf!fwfo
Dibohf!KTQL2!uzqf!up!TQ13111I811
Sftfswf!S815!boe!S817!!gps!HQJP7:!QV'QE
Dibohf!DW48-DW49!up!33Q
Dibohf!D:79-D:7:!up!44Q

2
3
4
5
6
7
8
9
:
21
22
23
24

Q25
Q27
Q51
Q21
Q31
Q32
Q44
Q47
Q48
Q4:
Q51
Q52
Q59

25
26
27
28
29
2:
31
32
33

Q58
Q58
Q56
Q57
Q48
Q53
Q52
Q49
Q49

Dibohf!qpxfs!tpvsdf!up!,6WT!)R21!qjo!3*
Sftfswf!S368!QV!21L!up!,4W`ETX
Dibohf!S2221!up!311L-D749!up!1/2v
Dibohf!D235-D236-D237-D238-D241!up!1714!uzqf
Dibohf!D326-D332-D4:6!up!1714!uzqf
Dibohf!D342!up!1714!uzqf
Dibohf!D62:!up!1714!uzqf
Dibohf!D679-D67:!up!1714!uzqf
Dibohf!D:48-D:65-D:64!up!1714!uzqf
Dibohf!D:97!up!1714!uzqf
Dibohf!D745-D746-D74:!up!1714!uzqf
Dibohf!D766!up!1714!uzqf
Dibohf!D947-D948-D94:-D951-D958
D959-D967-D968!up!1714!uzqf
Dibohf!D:17!up!1714!uzqf
Npejgz!hbuf!qpxs!sbjm!pg!NPT!up!,6WBMX!!
Dibohf!V4:!tpvsdf!up!TB11115LC11
Dibohf!V51-V7:!tpvsdf!up!TB11115LC11
Bee!R261-S256-D:87
Sftfswf!MBO`QXS`PO$!ofu!po!FD!qjo!9:
Tuvgg!S:56-S592!gps!FBQE!dpoubdu!V9!qjo3:
Bee!S:1
Bee!S2491

FWU!UP!EWU
Sftfswf!FD!ESBNSTU!dpouspm!qjo!gps!Effq!T4
Sftfswf!TVTBDL$-TVTXBSO$-TMQ`TVT$!dpouspm!tjhobm!gps!Effq!T4
Sfwfstf!TMQ`TVT$!up!dpouspm!,4W`QDI',6W`QDI
Gps!Effq!T4!gvodujpo
,6W`QDI!dpouspm!djsdvju!dibohf!gps!Effq!T4
Sftfswf!gps!BPBD!gvodujpo
Sftfswf!gps!BPBD!gvodujpo
Gps!EffqT40BPBD!gvodujpo
,4W`QDI',6W`QDI!dpouspm!djsdvju!gps!Effq!T4
Gps!EGy!jttvf
Gps!EGy!jttvf
Gps!EGy!jttvf
Sftfswf!gps!BPBD!gvodujpo
Gps!EGy!jttvf
Gps!TLV!JE
Gps!Dsztubm!FB!sfrvftu
Gps!Dsztubm!FB!sfrvftu
EWU!UP!QWU
Gpmmpx!joufm!Eftjho!Hvjef
Gps!Effq!T4!gvodujpo
Gps!PEE!tpgu!tubs
Gps!dpnnpoe!eftjho
Gps!dpnnpoe!eftjho
Gps!dpnnpoe!eftjho
Gps!dpnnpoe!eftjho
Gps!dpnnpoe!eftjho
Gps!dpnnpoe!eftjho
Gps!dpnnpoe!eftjho
Gps!dpnnpoe!eftjho
Gps!dpnnpoe!eftjho
Gps!dpnnpoe!eftjho

D

C

Gps!dpnnpoe!eftjho
Bwpje!mfblbhf!jttvf/!
Gps!nbjo!tpvsdf!jttvf
Gps!nbjo!tpvsdf!jttvf
Gps!MBO!qpxfs!dpouspm
Gps!MBO!qpxfs!dpouspm
Gps!NVUF`MFE!jttvf
Gps!MBO!TVSHF!DP.MBZ
Buifspt!sfrvftu

B

A

A

2011/07/21

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PIR (HW)
Size Document Number
Custom
Date:

Rev
1.0

LA-6882P
Sheet

Monday, January 16, 2012
1

62

of

64

5

4

3

2

1

QIWY3 HW PIR List
OP!EBUF!!!QBHF!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF

D

2
3
4
5
6

Q57
Q34
Q34
Q52
Q53

dibohf!KQ32!uzqf!)TQ121122B11*
SW319!dibohf!up!dpoubdu!,WEE44NJTD
Sftfswf!SW25
Txbq!IQ!S0M
Bee!S2526-S252:

Gps!BTTZ!jttvf
Gps!O24Q.HU0O24F.HF!tivuepxo!jttvf
Gps!O24Q.HU0O24F.HF!,WEE44NJTD!!mfblbhf!jttvf
Gps!IQ!S0M!sfwfstf!jttvf
U0Q!TN!CVT!qvmm!ijhi!wpmubhf!!dibohf

QWU!UP!TWU

D

C

C

B

B

A

A

2011/07/21

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PIR (HW)
Size Document Number
Custom
Date:

Rev
1.0

LA-6881P
Sheet

Monday, January 16, 2012
1

63

of

64

5

4

3

2

1

D

D

2

A3

PU3

B5

+3VALW

A5
B7

V

B4

V

4

EC

SYSON#

V
V V

+1.5V
PU5

8a (DIS) VGA_ON
8

V

V

SUSP#,SUSP

V

V

B

U49
+5VS

+1.5VSDGPU
U40

U20
+3VS

+1.8VSDGPU
U37

U13
+1.5VS
PU8
+0.75V

V

V

VCCPPWRGOOD

+3VSDGPU
Q6

PU9
+1.05VS_VCCP

PU7
+VCCSA

11
VGATE

V

DGPU_PWR_EN

7

C

6

V

SYSON

CPU

V

V

V

ON/OFF

15

VGA
B

+1.0VSDGPU
PU28

V

B6

V

A4

PLT_RST#

14

V

C

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_A#
PM_SLP_SUS#

H_CPUPWRGD

+VGA_CORE
PU998

V

PBTN_OUT#

EC_ON

PCH

5

V

B7

PM_DRAM_PWRGD

V

A5

V

51ON#

PCH_RSMRST#

V V

B3

SYS_PWROK
13

PQ2

V

B+

V

B2

+3VALW_PCH
+5VALW_PCH

3

2

V

B1

2

V

BATT

U14,+3VALW_PCH
QH4,+5VALW_PCH

V

B+

V

V

A2

PU2

VV

VIN

V V

BATT
MODE

A1

V

AC
MODE

V

PCH_PWR_EN#

VGA_PWROK

8b (DIS)

U47
CK505

V

9

V

VR_ON

PU1000
+CPU_CORE

10

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/21

2012/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
Power sequence

Size Document Number
Custom

Rev
1.0

QIWY3 LA-8001P

Date:

Monday, January 16, 2012

Sheet
1

64

of

64



---

Source Exif Data:

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Author                          : Jimmy_Lee
Create Date                     : 2012:02:15 11:34:43+07:00
Modify Date                     : 2012:02:15 11:35:25+07:00
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Title                           : LA8001PR10_OPT_0116
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