LA8001PR10_OPT_0116 Compal LA 8001P

User Manual:

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Page Count: 64

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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
Cover Page
Custom
164Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
Cover Page
Custom
164Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
Cover Page
Custom
164Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
Intel IVY Bridge Processor with DDRIII + Panther Point PCH
QIWY3 M/B Schematics Document
REV:1.0
Compal Confidential
2011-12-23
nVIDIA N13X
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B
B
C
C
D
D
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E
1 1
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
MB Block Diagram
Custom
264Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
MB Block Diagram
Custom
264Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
MB Block Diagram
Custom
264Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
File Name : Y480
Compal confidential
SPI ROM
BIOS
HDMI
USB PORT 3.0 x2(Left)
37.5mm*37.5mm
25mm*25mm
SATA3.0 HDD CONN
SATA ODD CONN
DDR3-1600(1.5V)
6*PCI-E x1
PCI Express
Mini card Slot 1
FDI *8
100MHz
2.7GT/s
Intel
6*SATA
UP TO 16G
Array Digital MIC
PCI-E X16
Function BOARD
BlueTooth CONN
CMOS Camera
RealTek
ALC269-VC
Audio Codec
2Channel Speaker
LPC BUS
CRT Connector
HD Audio
Int.KBD
ENE KB9012
Touch Pad
BANK 0, 1, 2, 3
DDR3-SO-DIMM X2
DDR3-1333(1.5V)
Dual Channel
14*USB2.0
LVDS
Connector
EC
IVY Bridge
Socket-rPGA989
DMI2 *4
FCBGA 989 Balls
Intel
Panther Point
CONN
GDDR5*8
nVIDIA N13P-GT/GL1
VRAM 64*32
Audio Jacks
Stereo
HeadPhone Output
Microphone Input
optimus 2012
optimus 2012
(port0,1 Support SATA3)
Card Reader
JBM389C
SD/MMC/MS/XD
SATA3.0 HDD (SSD)
LAN(Gbe)
RJ45 CONN
EMC1403/2103
WLAN/WiMAX
Thermal Sensor
WLAN/WiMAX
PCI-E(WLAN)
USB(WiMAX)
PCI Express
Mini card Slot 2
SATA(SSD)
SSD
100MHz
5GT/s
Gen 1/2/3
HDMI1.4a
Processor
PCH
Sub-borad
Audio Board
Chief River
Audio Board
Audio Board
Audio Board
4*USB3.0
WLAN/WiMAX
USB PORT 3.0 x1 (Right)
with USB charger
USB PORT 2.0 x1(Right)
Arthros
AR8161/AR8151
POWER BOARD
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
Notes List
Custom
364Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
Notes List
Custom
364Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
Notes List
Custom
364Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
CHG@
HDMI@
EVT
DVT
PVT
MP
USB 3.0USB 2.0 Port 4 External
USB Port
USB Port (Right Side)
Camera
Blue Tooth
0
1
2
3
4
5
6
7
8
9
10
11
12
13
EHCI1
EHCI2
USB Port Table
Board ID / SKU ID Table for AD channelBOARD ID Table
STATE SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Vcc 3.3V +/- 5%
10K +/- 5%Ra/Rc/Re
Board ID
Rb / Rd / Rf V min
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
AD_BID
V typ
AD_BID
V
AD_BID
max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V 0 V
4
5
6
7NC
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
1.185 V 1.264 V
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
Voltage Rails
BTO ItemBOM Structure
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOWLOWLOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGHHIGHHIGH
HIGH
HIGH
HIGH
OPTI@
TV@
Mini Card(WLAN)
BOM Structure Table
O
X
S3
+3VS
X
X
+3VALW
+5VS
O
+CPU_CORE
OO
X
XX
+VCCSApower
plane
O
O
O
O
X
S5 S4/ Battery only
XX X
+B
State
+1.5VS
+1.5V
S5 S4/AC & Battery
don't exist
S5 S4/AC
+5VALW
S0
O
O
+GFX_CORE
+1.8VS
+1.5VS_VGA
+1.05VS
+VGA_CORE
USB Port (Right Side)
LAN
6
4
5
3
2
1
7
8
Thermal Sensor EMC1403-2
1001_101xb
EC SM Bus1 address
Device
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
PCH SM Bus address
Device Address
Address
Address
EC SM Bus2 address
Device
Smart Battery
0001 011X b
PCIE PORT LIST
USB Port (Left Side)
USB Port (Left Side)
Mini Card(TV)
WLAN
Card Reader
TV
OPTIMUS part
HDMI part
TV module part
USB charger part
NOCHG@
No USB charger part
CMOS@
BT@
AR8161 LAN part
Blue Tooth part
CMOS Camera part
Port Device
+0.75VS
+1.05VS_VGA
+V1.5S_VCCP
+3.3VS_VGA
XHCI
1
2
3
4
Project
QIWY3
DVT
EVT
MP
PVT
AR8151 LAN part
8161@
8151@
QIWY3
QIWY3
QIWY3
QIWY4
QIWY4
QIWY4
QIWY4
ME@
Unpop
ME part
@
1403@
EMC1403 thermal part
2103@
EMC2103 thermal part
X76@
S1G@
S2G@
H1G@
X76 Level part for VRAM
X76 P/N for Samsun VRAM 1G
X76 P/N for Samsun VRAM 2G
X76 P/N for Hynix VRAM 1G
KBL@
K/B Light part
H2G@
X76 P/N for Hynix VRAM 2G
GL@
N13P-GL part
GT@
GE@
GTGE@
N13P-GT part
N13E-GE part
N13P-GT&N13E-GE common part
GC6@
NV CG6 support part
NOGC6@
NV no CG6 support part
61@
51@
X76 P/N for AR8161
X76 P/N for AR8151
8161S@
8151S@
SURGE@
AR8161 LAN surge part
AR8151 LAN surge part
AR8151&8161 LAN surge part
ZZZ1
DA80000Q800
ZZZ1
DA80000Q800
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
VGA Notes List
464Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
QIWY3 LA-8001P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
VGA Notes List
464Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
QIWY3 LA-8001P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
VGA Notes List
464Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
QIWY3 LA-8001P
+1.5VS_VGA
1. all power rail ramp up time should be larger than 40us
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
+3VS_VGA
+1.05VS_VGA
+VGA_CORE
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
OUT
OUT
OUT
OUT
OUT
OUT
I/O
OUT
OUT
IN
OUT
OUT
GPU VID1
GPU VID2
-
GPIO I/O ACTIVE Function Description
-
-
IN
OUT
IN
IN
IN
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
VGA and GDDR5 Voltage Rails (N13Px GPIO)
N/A
(10K pull High)
N/A
N/A
Thermal Catastrophic Over Temperature
GC6 event
Memory VREF Control
AC Power Detect Input
N/A
N/A
-
-
-
Products
GPU Mem NVCLK
/MCLK NVVDD FBVDD FBVDDQ PCI Express I/O and
PLLVDD I/O and
PLLVDD Other
(3.3V)(1.05V)(1.8V)
(1.05V)
(1.35V)(1.35V) (GPU+Mem)
(4) (1,5) (6)
(V) (A) (W) (A) (W)
Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)
N13X
128bit
1GB
GDDR5
(W) (W) (MHz)
TBD TBDTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
tFBVDDQ >0
tNVVDD >0
tPEX_VDD >0
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
FB[1]
3GIO_PAD_CFG_ADR[0]
USER[2] USER[1] USER[0]USER[3]
3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]
PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
STRAP3
STRAP4
+3VS_VGA
+3VS_VGA
SOR3_EXPOSED
RESERVED PCIE_SPEED_
CHANGE_GEN3
PCIE_MAX_SPEED DP_PLL_VDD33V
SOR2_EXPOSED SOR1_EXPOSED
Power Rail
+3VS_VGA
ROM_SCLK
SOR0_EXPOSED
Logical
Strapping Bit3
Logical
Strapping Bit2
SLOT_CLK_CFG
Logical
Strapping Bit0
SUB_VENDOR
PEX_PLL_EN_TERM
RAM_CFG[0]
STRAP0
STRAP1
STRAP2
ROM_SI
RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]
VGA_DEVICESMB_ALT_ADDR
PCI_DEVID[4]
ROM_SO FB[0]
Logical
Strapping Bit1
Physical
Strapping pin
N13P-GT
(28nm) 0x0FDB
Device ID
N13E-GE
(28nm) 0x0FDB
Hot plug detect for IFP link C
GPU VID3OUT
OUT GPU VID4-
GPU VID0-OUT
1.all GPU power rails should be turned off within 10ms
Tpower-off <10ms
GPU VID5-
+3VS_VGA
Other Power rail
N/A
N/A
0x0DE9
N13P-GL1
(40nm)
(100K pull low)
N/A
N/A
N/A
ROM_SO
PU 10K
N13P-GT
PD 10K PD 15K
ROM_SCLK
PU 5K
PU 5K
PU 10K
GPU
PD 35K
STRAP2
PD 35K
PU 45KPD 45K
PU 45K
PU 45K
STRAP0STRAP1STRAP4
NC
PD 5K
N13P-GL
N13E-GE PD 5K
STRAP3
PU 10K
PD 25K
PD 10K
NC
PD 45K
PD 45K
32Mx32 PD 35K
64Mx32
64Mx32
K4G20325FD-FC04
H5GQ2H24MFR-T2CHynix
2500MHz
Samsung
2500MHz
H5GQ1H24BFR-T2C
K4G10325FG-HC04
ROM_SI
Samsung
2500MHz
GPU
PD 45K
FB Memory (GDDR5)
Hynix
2500MHz
32Mx32
PD 30K
PD 25K
N13P-GT N13E-GE N13P-GL
PD 30K
PD 25K
ROM_SI ROM_SI
PD 35K
PD 45K
PD 25K
PD 30K
PD 35K
PD 45K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FDI_FSYNC0
FDI_LSYNC0
FDI_LSYNC1
FDI_FSYNC1
FDI_INT
EDP_COMP
PEG_COMP
PCIE_CRX_GTX_N15
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P2
PCIE_CTX_GRX_C_P0
PCIE_CTX_GRX_C_P10
PCIE_CTX_GRX_C_P15
PCIE_CTX_GRX_C_P14
PCIE_CTX_GRX_C_P8
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P13
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P9
PCIE_CTX_GRX_C_P12
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_P11
PCIE_CTX_GRX_C_N14
PCIE_CTX_GRX_C_N15
PCIE_CTX_GRX_C_N0
PCIE_CTX_GRX_C_N10
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_C_N8
PCIE_CTX_GRX_C_N13
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_C_N9
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N12
PCIE_CTX_GRX_C_N7
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N11
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_N15
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P12
DMI_CTX_PRX_P0<16>
DMI_CRX_PTX_P0<16>
DMI_CTX_PRX_N1<16>
DMI_CRX_PTX_N1<16>
DMI_CTX_PRX_P3<16>
DMI_CRX_PTX_P3<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_N0<16>
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P1<16>
DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_P1<16>
DMI_CTX_PRX_N2<16>
FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>
FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>
FDI_FSYNC0<16>
FDI_FSYNC1<16>
FDI_INT<16>
FDI_LSYNC0<16>
FDI_LSYNC1<16>
PCIE_CRX_GTX_N[0..15] <23>
PCIE_CTX_GRX_P[0..15] <23>
PCIE_CTX_GRX_N[0..15] <23>
PCIE_CRX_GTX_P[0..15] <23>
+1.05VS
+1.05VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(1/7) DMI,FDI,PEG
Custom
564Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(1/7) DMI,FDI,PEG
Custom
564Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(1/7) DMI,FDI,PEG
Custom
564Monday, January 16, 2012
2011/07/21 2012/12/31
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
max length = 500 mils
- typical impedance = 14.5 mohms
eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms
Compal Electronics, Inc.
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
0:Lane Reversed
1: Normal Operation; Lane # definition matches
socket pin map definition
*
eDP_HPD
C31 0.22U_0402_10V6K
OPT@
C31 0.22U_0402_10V6K
OPT@
1 2
C9 0.22U_0402_10V6K
OPT@
C9 0.22U_0402_10V6K
OPT@
1 2
C20 0.22U_0402_10V6K
OPT@
C20 0.22U_0402_10V6K
OPT@
1 2
C32 0.22U_0402_10V6K
OPT@
C32 0.22U_0402_10V6K
OPT@
1 2
C21 0.22U_0402_10V6K
OPT@
C21 0.22U_0402_10V6K
OPT@
1 2
C4 0.22U_0402_10V6K
OPT@
C4 0.22U_0402_10V6K
OPT@
1 2
C11 0.22U_0402_10V6K
OPT@
C11 0.22U_0402_10V6K
OPT@
1 2
C1 0.22U_0402_10V6K
OPT@
C1 0.22U_0402_10V6K
OPT@
1 2
C22 0.22U_0402_10V6K
OPT@
C22 0.22U_0402_10V6K
OPT@
1 2
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
JCPU1A
TYCO_2013620-2_IVY BRIDGE
ME@
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
JCPU1A
TYCO_2013620-2_IVY BRIDGE
ME@
DMI_RX#[0]
B27
DMI_RX#[1]
B25
DMI_RX#[2]
A25
DMI_RX#[3]
B24
DMI_RX[0]
B28
DMI_RX[1]
B26
DMI_RX[2]
A24
DMI_RX[3]
B23
DMI_TX#[0]
G21
DMI_TX#[1]
E22
DMI_TX#[2]
F21
DMI_TX#[3]
D21
DMI_TX[0]
G22
DMI_TX[1]
D22
DMI_TX[3]
C21 DMI_TX[2]
F20
FDI0_TX#[0]
A21
FDI0_TX#[1]
H19
FDI0_TX#[2]
E19
FDI0_TX#[3]
F18
FDI1_TX#[0]
B21
FDI1_TX#[1]
C20
FDI1_TX#[2]
D18
FDI1_TX#[3]
E17
FDI0_TX[0]
A22
FDI0_TX[1]
G19
FDI0_TX[2]
E20
FDI0_TX[3]
G18
FDI1_TX[0]
B20
FDI1_TX[1]
C19
FDI1_TX[2]
D19
FDI1_TX[3]
F17
FDI0_FSYNC
J18
FDI1_FSYNC
J17
FDI_INT
H20
FDI0_LSYNC
J19
FDI1_LSYNC
H17
PEG_ICOMPI J22
PEG_ICOMPO J21
PEG_RCOMPO H22
PEG_RX#[0] K33
PEG_RX#[1] M35
PEG_RX#[2] L34
PEG_RX#[3] J35
PEG_RX#[4] J32
PEG_RX#[5] H34
PEG_RX#[6] H31
PEG_RX#[7] G33
PEG_RX#[8] G30
PEG_RX#[9] F35
PEG_RX#[10] E34
PEG_RX#[11] E32
PEG_RX#[12] D33
PEG_RX#[13] D31
PEG_RX#[14] B33
PEG_RX#[15] C32
PEG_RX[0] J33
PEG_RX[1] L35
PEG_RX[2] K34
PEG_RX[3] H35
PEG_RX[4] H32
PEG_RX[5] G34
PEG_RX[6] G31
PEG_RX[7] F33
PEG_RX[8] F30
PEG_RX[9] E35
PEG_RX[10] E33
PEG_RX[11] F32
PEG_RX[12] D34
PEG_RX[13] E31
PEG_RX[14] C33
PEG_RX[15] B32
PEG_TX#[0] M29
PEG_TX#[1] M32
PEG_TX#[2] M31
PEG_TX#[3] L32
PEG_TX#[4] L29
PEG_TX#[5] K31
PEG_TX#[6] K28
PEG_TX#[7] J30
PEG_TX#[8] J28
PEG_TX#[9] H29
PEG_TX#[10] G27
PEG_TX#[11] E29
PEG_TX#[12] F27
PEG_TX#[13] D28
PEG_TX#[14] F26
PEG_TX#[15] E25
PEG_TX[0] M28
PEG_TX[1] M33
PEG_TX[2] M30
PEG_TX[3] L31
PEG_TX[4] L28
PEG_TX[5] K30
PEG_TX[6] K27
PEG_TX[7] J29
PEG_TX[8] J27
PEG_TX[9] H28
PEG_TX[10] G28
PEG_TX[11] E28
PEG_TX[12] F28
PEG_TX[13] D27
PEG_TX[14] E26
PEG_TX[15] D25
eDP_AUX
C15
eDP_AUX#
D15
eDP_TX[0]
C17
eDP_TX[1]
F16
eDP_TX[2]
C16
eDP_TX[3]
G15
eDP_TX#[0]
C18
eDP_TX#[1]
E16
eDP_TX#[2]
D16
eDP_TX#[3]
F15
eDP_COMPIO
A18
eDP_HPD#
B16 eDP_ICOMPO
A17
C16 0.22U_0402_10V6K
OPT@
C16 0.22U_0402_10V6K
OPT@
1 2
C23 0.22U_0402_10V6K
OPT@
C23 0.22U_0402_10V6K
OPT@
1 2
C6 0.22U_0402_10V6K
OPT@
C6 0.22U_0402_10V6K
OPT@
1 2
C13 0.22U_0402_10V6K
OPT@
C13 0.22U_0402_10V6K
OPT@
1 2
C24 0.22U_0402_10V6K
OPT@
C24 0.22U_0402_10V6K
OPT@
1 2
C8 0.22U_0402_10V6K
OPT@
C8 0.22U_0402_10V6K
OPT@
1 2
C25 0.22U_0402_10V6K
OPT@
C25 0.22U_0402_10V6K
OPT@
1 2
C26 0.22U_0402_10V6K
OPT@
C26 0.22U_0402_10V6K
OPT@
1 2
C3 0.22U_0402_10V6K
OPT@
C3 0.22U_0402_10V6K
OPT@
1 2
C10 0.22U_0402_10V6K
OPT@
C10 0.22U_0402_10V6K
OPT@
1 2
C27 0.22U_0402_10V6K
OPT@
C27 0.22U_0402_10V6K
OPT@
1 2
C15 0.22U_0402_10V6K
OPT@
C15 0.22U_0402_10V6K
OPT@
1 2
C5 0.22U_0402_10V6K
OPT@
C5 0.22U_0402_10V6K
OPT@
1 2
C12 0.22U_0402_10V6K
OPT@
C12 0.22U_0402_10V6K
OPT@
1 2
C28 0.22U_0402_10V6K
OPT@
C28 0.22U_0402_10V6K
OPT@
1 2
R7
24.9_0402_1%
R7
24.9_0402_1%
12
C17 0.22U_0402_10V6K
OPT@
C17 0.22U_0402_10V6K
OPT@
1 2
R1
24.9_0402_1%
R1
24.9_0402_1%
12
C29 0.22U_0402_10V6K
OPT@
C29 0.22U_0402_10V6K
OPT@
1 2
C18 0.22U_0402_10V6K
OPT@
C18 0.22U_0402_10V6K
OPT@
1 2
C7 0.22U_0402_10V6K
OPT@
C7 0.22U_0402_10V6K
OPT@
1 2
C14 0.22U_0402_10V6K
OPT@
C14 0.22U_0402_10V6K
OPT@
1 2
C2 0.22U_0402_10V6K
OPT@
C2 0.22U_0402_10V6K
OPT@
1 2
C30 0.22U_0402_10V6K
OPT@
C30 0.22U_0402_10V6K
OPT@
1 2
C19 0.22U_0402_10V6K
OPT@
C19 0.22U_0402_10V6K
OPT@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XDP_TCK
XDP_TRST#
XDP_TMS
XDP_TDI
XDP_TDO
H_CATERR#
XDP_BPM#4
XDP_TRST#
XDP_PREQ#
SM_RCOMP0
H_PECI
XDP_BPM#7
PM_DRAM_PWRGD_R
XDP_TDO
SM_RCOMP2
XDP_BPM#1
XDP_BPM#6
CLK_CPU_DMI_R
H_THEMTRIP#
CLK_CPU_DMII#_R
XDP_BPM#3
H_CPUPWRGD_R
XDP_TDI
XDP_BPM#0
BUF_CPU_RST#
XDP_DBRESET#
H_PROCHOT#_R
XDP_TCK
H_DRAMRST#
XDP_BPM#2
H_PM_SYNC_R
XDP_PRDY#
SM_RCOMP1
XDP_BPM#5
PCH_PLTRST#
BUFO_CPU_RST#
H_PROCHOT#
PM_SYS_PWRGD_BUF
BUF_CPU_RST#
XDP_TMS
PM_DRAM_PWRGD<16>
RUN_ON_CPU1.5VS3#<10>
H_DRAMRST# <7>
H_PM_SYNC<16>
CLK_CPU_DMI# <15>
H_THRMTRIP#<19>
CLK_CPU_DMI <15>
H_CPUPWRGD<19>
H_SNB_IVB#<19>
H_PECI<19,42>
H_PROCHOT#<42,50>
PCH_PLTRST# <18>
SYS_PWROK<16>
+1.05VS
+1.5V_CPU_VDDQ
+3VALW
+1.05VS
+3VS
+1.05VS
+1.05VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(2/7) PM,XDP,CLK
Custom
664Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(2/7) PM,XDP,CLK
Custom
664Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(2/7) PM,XDP,CLK
Custom
664Monday, January 16, 2012
2011/07/21 2012/12/31
PU/PD for JTAG signals
DDR3 Compensation Signals
Compal Electronics, Inc.
Buffered reset to CPU
Place R10,R11 close to U4
Reserve 43 Ohm resistor closs to EC(250~750mils)
3V
1.05V
H : Sandy Bridge
PROC_SEL L : IVY Bridge
9/23 ESD Request
R24 51_0402_5%R24 51_0402_5%
12
R32
75_0402_5%
R32
75_0402_5%
12
R12 1K_0402_5%R12 1K_0402_5%
12
R10 0_0402_5%R10 0_0402_5%
1 2
R26
0_0402_5%
R26
0_0402_5%1 2
R16 140_0402_1%R16 140_0402_1%
12
R17 25.5_0402_1%R17 25.5_0402_1%
12
R29
130_0402_5%
R29
130_0402_5%
1 2
R15
56_0402_5%
R15
56_0402_5%
1 2
R20 51_0402_5%R20 51_0402_5%
12
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
TYCO_2013620-2_IVY BRIDGE
ME@
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
TYCO_2013620-2_IVY BRIDGE
ME@
SM_RCOMP[1] A5
SM_RCOMP[2] A4
SM_DRAMRST# R8
SM_RCOMP[0] AK1
BCLK# A27
BCLK A28
DPLL_REF_CLK# A15
DPLL_REF_CLK A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
THERMTRIP#
AN32
SM_DRAMPWROK
V8
RESET#
AR33
PRDY# AP29
PREQ# AP27
TCK AR26
TMS AR27
TRST# AP30
TDI AR28
TDO AP26
DBR# AL35
BPM#[0] AT28
BPM#[1] AR29
BPM#[2] AR30
BPM#[3] AT30
BPM#[4] AP32
BPM#[5] AR31
BPM#[6] AT31
BPM#[7] AR32
PM_SYNC
AM34
SKTOCC#
AN34
PROC_SELECT#
C26
UNCOREPWRGOOD
AP33
R28 1K_0402_5%R28 1K_0402_5%
12
R27
10K_0402_5%
R27
10K_0402_5%
1 2
R25 51_0402_5%R25 51_0402_5%
12
R34
43_0402_1%
R34
43_0402_1%
1 2
R22
0_0402_5%
R22
0_0402_5%
1 2
C550
100P_0402_50V8J
C550
100P_0402_50V8J
1
2
R9
62_0402_5%
R9
62_0402_5%
12
R13 1K_0402_5%R13 1K_0402_5%
12
C33
0.1U_0402_16V4Z
C33
0.1U_0402_16V4Z
1
2
G
D
S
Q1
2N7002_SOT23
@
G
D
S
Q1
2N7002_SOT23
@
2
13
C34
0.1U_0402_16V4Z
C34
0.1U_0402_16V4Z
1
2
R33
39_0402_5%
@
R33
39_0402_5%
@
12
U1
74AHC1G09GW_TSSOP5
U1
74AHC1G09GW_TSSOP5
B
1
A
2
G
3
O4
P5
R11
0_0402_5%
R11
0_0402_5%
1 2
R65
0_0402_5% @
R65
0_0402_5% @
12
R18 200_0402_1%R18 200_0402_1%
12
T14 PADT14 PAD
R30
200_0402_5%
R30
200_0402_5%
12
U2
SN74LVC1G07DCKR_SC70-5
U2
SN74LVC1G07DCKR_SC70-5
NC 1
A2
G
3
Y
4
P5
R338
10K_0402_5%
R338
10K_0402_5%
1 2
R21 51_0402_5%R21 51_0402_5%
12
R23 51_0402_5%
@
R23 51_0402_5%
@
12
R35
0_0402_5%
@R35
0_0402_5%
@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D63
DDR_A_D62
DDR_A_D8
DDR_A_D3
DDR_A_D4
DDR_A_D7
DDR_A_D5
DDR_A_D6
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D47
DDR_A_D46
DDR_A_D42
DDR_A_D43
DDR_A_D34
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_D35
DDR_A_D41
DDR_A_D40
DDR_A_D38
DDR_A_D36
DDR_A_D37
DDR_A_D32
DDR_A_D33
DDR_A_D61
DDR_A_D60
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_D55
DDR_A_D54
DDR_A_D51
DDR_A_D48
DDR_A_D50
DDR_A_D49
DDR_A_D52
DDR_A_D53
DDR_A_D31
DDR_A_D14
DDR_A_D15
DDR_A_D25
DDR_A_D24
DDR_A_D26
DDR_A_D27
DDR_A_D30
DDR_A_D9
DDR_A_D13
DDR_A_D12
DDR_A_D10
DDR_A_D11
DDR_A_D29
DDR_A_D28
DDR_A_D19
DDR_A_D20
DDR_A_D16
DDR_A_D21
DDR_A_D17
DDR_A_D22
DDR_A_D18
DDR_A_D23
DDR_A_MA15
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DQS1
DDR_A_DQS6
DDR_A_DQS5
DDR_A_DQS4
DDR_A_DQS3
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS#0
DDR_A_DQS#2
DDR_A_DQS#5
DDR_A_DQS#3
DDR_A_DQS#1
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_MA0
DDR_A_MA14
DDR_A_MA5
DDR_A_MA4
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA9
DDR_A_MA7
DDR_A_MA6
DDR_A_MA12
DDR_A_MA13
DDR_A_MA8
DDR_A_MA11
DDR_A_MA10
DDR_B_D33
DDR_B_D14
DDR_B_D42
DDR_B_D59
DDR_B_D63
DDR_B_D43
DDR_B_D55
DDR_B_D53
DDR_B_D29
DDR_B_D24
DDR_B_D34
DDR_B_D4
DDR_B_D26
DDR_B_D13
DDR_B_D10
DDR_B_D21
DDR_B_D11
DDR_B_D57
DDR_B_D44
DDR_B_D0
DDR_B_D7
DDR_B_D46
DDR_B_D3
DDR_B_D15
DDR_B_D27
DDR_B_D30
DDR_B_D35
DDR_B_D40
DDR_B_D49
DDR_B_D23
DDR_B_D25
DDR_B_D19
DDR_B_D37
DDR_B_D48
DDR_B_D36
DDR_B_D18
DDR_B_D8
DDR_B_D47
DDR_B_D9
DDR_B_D60
DDR_B_D50
DDR_B_D62
DDR_B_D52
DDR_B_D2
DDR_B_D51
DDR_B_D56
DDR_B_D39
DDR_B_D22
DDR_B_D28
DDR_B_D6
DDR_B_D45
DDR_B_D17
DDR_B_D58
DDR_B_D61
DDR_B_D31
DDR_B_D54
DDR_B_D1
DDR_B_D41
DDR_B_D5
DDR_B_D12
DDR_B_D20
DDR_B_D38
DDR_B_D32
DDR_B_D16
DDR_B_MA15
DDR_B_DQS#1
DDR_B_DQS#7
DDR_B_DQS#5
DDR_B_DQS#4
DDR_B_DQS#0
DDR_B_DQS#3
DDR_B_DQS#6
DDR_B_DQS#2
DDR_B_DQS7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS5
DDR_B_DQS4
DDR_B_DQS3
DDR_B_DQS2
DDR_B_DQS6
DDR_B_MA0
DDR_B_MA9
DDR_B_MA7
DDR_B_MA13
DDR_B_MA2
DDR_B_MA4
DDR_B_MA11
DDR_B_MA3
DDR_B_MA5
DDR_B_MA6
DDR_B_MA10
DDR_B_MA8
DDR_B_MA1
DDR_B_MA12
DDR_B_MA14
DDR3_DRAMRST#_RH_DRAMRST#
DRAMRST_CNTRL
DDR_A_D[0..63]<12>
DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>
DDR_A_WE#<12>
DDR_A_RAS#<12>
DDR_A_CAS#<12>
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>
M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>
DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>
M_ODT0 <12>
M_ODT1 <12>
DDR_A_DQS#[0..7] <12>
DDR_A_DQS[0..7] <12>
DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>
DDR_B_D[0..63]<13>
DDR_B_WE#<13>
DDR_B_RAS#<13>
DDR_B_CAS#<13>
DDR_CS3_DIMMB# <13>
DDR_B_DQS[0..7] <13>
DDR_B_DQS#[0..7] <13>
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
M_CLK_DDR3 <13>
DDR_CS2_DIMMB# <13>
M_ODT3 <13>
M_ODT2 <13>
DDR_CKE3_DIMMB <13>
M_CLK_DDR#3 <13>
DDR3_DRAMRST# <12,13>
H_DRAMRST#<6>
DRAMRST_CNTRL_PCH<15>
DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>
DRAMRST_CNTRL<10>
DRAMRST_CNTRL_EC<42>
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(3/7) DDRIII
Custom
764Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(3/7) DDRIII
Custom
764Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(3/7) DDRIII
Custom
764Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
Module design used 0.047u
9/5 Reserve for Deep S3
R39
4.99K_0402_1%
R39
4.99K_0402_1%
1 2
R36
0_0402_5%
@R36
0_0402_5%
@
1 2
DDR SYSTEM MEMORY B
JCPU1D
TYCO_2013620-2_IVY BRIDGE
ME@
DDR SYSTEM MEMORY B
JCPU1D
TYCO_2013620-2_IVY BRIDGE
ME@
SB_BS[0]
AA9
SB_BS[1]
AA7
SB_BS[2]
R6
SB_CAS#
AA10
SB_RAS#
AB8
SB_WE#
AB9
SB_CLK[0] AE2
SB_CLK[1] AE1
SB_CLK#[0] AD2
SB_CLK#[1] AD1
SB_CKE[0] R9
SB_CKE[1] R10
SB_ODT[0] AE4
SB_ODT[1] AD4
SB_DQS[4] AN6
SB_DQS#[4] AN5
SB_DQS[5] AP8
SB_DQS#[5] AP9
SB_DQS[6] AK11
SB_DQS#[6] AK12
SB_DQS[7] AP14
SB_DQS#[7] AP15
SB_DQS[0] C7
SB_DQS#[0] D7
SB_DQS[1] G3
SB_DQS#[1] F3
SB_DQS[2] J6
SB_DQS#[2] K6
SB_DQS[3] M3
SB_DQS#[3] N3
SB_MA[0] AA8
SB_MA[1] T7
SB_MA[2] R7
SB_MA[3] T6
SB_MA[4] T2
SB_MA[5] T4
SB_MA[6] T3
SB_MA[7] R2
SB_MA[8] T5
SB_MA[9] R3
SB_MA[10] AB7
SB_MA[11] R1
SB_MA[12] T1
SB_MA[13] AB10
SB_MA[14] R5
SB_MA[15] R4
SB_DQ[0]
C9
SB_DQ[1]
A7
SB_DQ[2]
D10
SB_DQ[3]
C8
SB_DQ[4]
A9
SB_DQ[5]
A8
SB_DQ[6]
D9
SB_DQ[7]
D8
SB_DQ[8]
G4
SB_DQ[9]
F4
SB_DQ[10]
F1
SB_DQ[11]
G1
SB_DQ[12]
G5
SB_DQ[13]
F5
SB_DQ[14]
F2
SB_DQ[15]
G2
SB_DQ[16]
J7
SB_DQ[17]
J8
SB_DQ[18]
K10
SB_DQ[19]
K9
SB_DQ[20]
J9
SB_DQ[21]
J10
SB_DQ[22]
K8
SB_DQ[23]
K7
SB_DQ[24]
M5
SB_DQ[25]
N4
SB_DQ[26]
N2
SB_DQ[27]
N1
SB_DQ[28]
M4
SB_DQ[29]
N5
SB_DQ[30]
M2
SB_DQ[31]
M1
SB_DQ[32]
AM5
SB_DQ[33]
AM6
SB_DQ[34]
AR3
SB_DQ[35]
AP3
SB_DQ[36]
AN3
SB_DQ[37]
AN2
SB_DQ[38]
AN1
SB_DQ[39]
AP2
SB_DQ[40]
AP5
SB_DQ[41]
AN9
SB_DQ[42]
AT5
SB_DQ[43]
AT6
SB_DQ[44]
AP6
SB_DQ[45]
AN8
SB_DQ[46]
AR6
SB_DQ[47]
AR5
SB_DQ[48]
AR9
SB_DQ[49]
AJ11
SB_DQ[50]
AT8
SB_DQ[51]
AT9
SB_DQ[52]
AH11
SB_DQ[53]
AR8
SB_DQ[54]
AJ12
SB_DQ[55]
AH12
SB_DQ[56]
AT11
SB_DQ[57]
AN14
SB_DQ[58]
AR14
SB_DQ[59]
AT14
SB_DQ[60]
AT12
SB_DQ[61]
AN15
SB_DQ[62]
AR15
SB_DQ[63]
AT15
RSVD_TP[11] AB2
RSVD_TP[12] AA2
RSVD_TP[13] T9
RSVD_TP[14] AA1
RSVD_TP[15] AB1
RSVD_TP[16] T10
SB_CS#[0] AD3
SB_CS#[1] AE3
RSVD_TP[17] AD6
RSVD_TP[18] AE6
RSVD_TP[19] AD5
RSVD_TP[20] AE5
R40 0_0402_5%R40 0_0402_5%
1 2
C35
0.047U_0402_16V4Z
C35
0.047U_0402_16V4Z
1
2
DDR SYSTEM MEMORY A
JCPU1C
TYCO_2013620-2_IVY BRIDGE
ME@
DDR SYSTEM MEMORY A
JCPU1C
TYCO_2013620-2_IVY BRIDGE
ME@
SA_BS[0]
AE10
SA_BS[1]
AF10
SA_BS[2]
V6
SA_CAS#
AE8
SA_RAS#
AD9
SA_WE#
AF9
SA_CLK[0] AB6
SA_CLK[1] AA5
SA_CLK#[0] AA6
SA_CLK#[1] AB5
SA_CKE[0] V9
SA_CKE[1] V10
SA_CS#[0] AK3
SA_CS#[1] AL3
SA_ODT[0] AH3
SA_ODT[1] AG3
SA_DQS[0] D4
SA_DQS#[0] C4
SA_DQS[1] F6
SA_DQS#[1] G6
SA_DQS[2] K3
SA_DQS#[2] J3
SA_DQS[3] N6
SA_DQS#[3] M6
SA_DQS[4] AL5
SA_DQS#[4] AL6
SA_DQS[5] AM9
SA_DQS#[5] AM8
SA_DQS[6] AR11
SA_DQS#[6] AR12
SA_DQS[7] AM14
SA_DQS#[7] AM15
SA_MA[0] AD10
SA_MA[1] W1
SA_MA[2] W2
SA_MA[3] W7
SA_MA[4] V3
SA_MA[5] V2
SA_MA[6] W3
SA_MA[7] W6
SA_MA[8] V1
SA_MA[9] W5
SA_MA[10] AD8
SA_MA[11] V4
SA_MA[12] W4
SA_MA[13] AF8
SA_MA[14] V5
SA_MA[15] V7
SA_DQ[0]
C5
SA_DQ[1]
D5
SA_DQ[2]
D3
SA_DQ[3]
D2
SA_DQ[4]
D6
SA_DQ[5]
C6
SA_DQ[6]
C2
SA_DQ[7]
C3
SA_DQ[8]
F10
SA_DQ[9]
F8
SA_DQ[10]
G10
SA_DQ[11]
G9
SA_DQ[12]
F9
SA_DQ[13]
F7
SA_DQ[14]
G8
SA_DQ[15]
G7
SA_DQ[16]
K4
SA_DQ[17]
K5
SA_DQ[18]
K1
SA_DQ[19]
J1
SA_DQ[20]
J5
SA_DQ[21]
J4
SA_DQ[22]
J2
SA_DQ[23]
K2
SA_DQ[24]
M8
SA_DQ[25]
N10
SA_DQ[26]
N8
SA_DQ[27]
N7
SA_DQ[28]
M10
SA_DQ[29]
M9
SA_DQ[30]
N9
SA_DQ[31]
M7
SA_DQ[32]
AG6
SA_DQ[33]
AG5
SA_DQ[34]
AK6
SA_DQ[35]
AK5
SA_DQ[36]
AH5
SA_DQ[37]
AH6
SA_DQ[38]
AJ5
SA_DQ[39]
AJ6
SA_DQ[40]
AJ8
SA_DQ[41]
AK8
SA_DQ[42]
AJ9
SA_DQ[43]
AK9
SA_DQ[44]
AH8
SA_DQ[45]
AH9
SA_DQ[46]
AL9
SA_DQ[47]
AL8
SA_DQ[48]
AP11
SA_DQ[49]
AN11
SA_DQ[50]
AL12
SA_DQ[51]
AM12
SA_DQ[52]
AM11
SA_DQ[53]
AL11
SA_DQ[54]
AP12
SA_DQ[55]
AN12
SA_DQ[56]
AJ14
SA_DQ[57]
AH14
SA_DQ[58]
AL15
SA_DQ[59]
AK15
SA_DQ[60]
AL14
SA_DQ[61]
AK14
SA_DQ[62]
AJ15
SA_DQ[63]
AH15
RSVD_TP[1] AB4
RSVD_TP[2] AA4
RSVD_TP[4] AB3
RSVD_TP[5] AA3
RSVD_TP[3] W9
RSVD_TP[6] W10
RSVD_TP[7] AG1
RSVD_TP[8] AH1
RSVD_TP[9] AG2
RSVD_TP[10] AH2
G
D
S
Q2
BSS138_NL_SOT23-3
G
D
S
Q2
BSS138_NL_SOT23-3
2
13
R64 0_0402_5%
@
R64 0_0402_5%
@
1 2
R37
1K_0402_5%
R37
1K_0402_5%
12
R38
1K_0402_5%
R38
1K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG4
CFG6
CFG2
CFG7
CFG5
VCC_VAL_SENSE
CFG2
CFG4
CFG6
CFG7
CFG5
VCC_AXG_VAL_SENSE
VSS_VAL_SENSE
VSS_AXG_VAL_SENSE
VSS_VAL_SENSE
VSS_AXG_VAL_SENSE
+VCC_GFXCORE_AXG
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(4/7) RSVD,CFG
Custom
864Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(4/7) RSVD,CFG
Custom
864Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(4/7) RSVD,CFG
Custom
864Monday, January 16, 2012
2011/07/21 2012/12/31
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
PCIE Port Bifurcation Straps
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG7
PEG DEFER TRAINING
0: PEG Wait for BIOS for training
1: (Default) PEG Train immediately following xxRESETB
de assertion
CFG4
Display Port Presence Strap
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
CFG Straps for Processor
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
0:Lane Reversed
1: Normal Operation; Lane # definition matches
socket pin map definition
Compal Electronics, Inc.
*
*
*
INTEL 12/28 recommand
to add R187, R161, R291, R196
Please place as close as JCPU1
R44
1K_0402_1%
@R44
1K_0402_1%
@
12
R2
0_0402_5%
R2
0_0402_5%
1 2
R196
49.9_0402_1%
R196
49.9_0402_1%
1 2
R43
1K_0402_1%
@R43
1K_0402_1%
@
12
R291
49.9_0402_1%
R291
49.9_0402_1%
1 2
R45
1K_0402_1%
@R45
1K_0402_1%
@
12
R71 100_0402_1%@R71 100_0402_1%@1 2
R161
49.9_0402_1%
R161
49.9_0402_1%
1 2
R42
1K_0402_1%
@R42
1K_0402_1%
@
12
R41
1K_0402_1%
R41
1K_0402_1%
12
RESERVED
CFG
JCPU1E
TYCO_2013620-2_IVY BRIDGE
ME@
RESERVED
CFG
JCPU1E
TYCO_2013620-2_IVY BRIDGE
ME@
CFG[0]
AK28
CFG[1]
AK29
CFG[2]
AL26
CFG[3]
AL27
CFG[4]
AK26
CFG[5]
AL29
CFG[6]
AL30
CFG[7]
AM31
CFG[8]
AM32
CFG[9]
AM30
CFG[10]
AM28
CFG[11]
AM26
CFG[12]
AN28
CFG[13]
AN31
CFG[14]
AN26
CFG[15]
AM27
CFG[16]
AK31
CFG[17]
AN29
RSVD34 AM33
RSVD35 AJ27
RSVD38 J16
RSVD_NCTF2 AT34
RSVD39 H16
RSVD40 G16
RSVD_NCTF1 AR35
RSVD_NCTF3 AT33
RSVD_NCTF5 AR34
RSVD_NCTF11 AT2
RSVD_NCTF12 AT1
RSVD_NCTF13 AR1
RSVD_NCTF6 B34
RSVD_NCTF7 A33
RSVD_NCTF8 A34
RSVD_NCTF9 B35
RSVD_NCTF10 C35
RSVD51 AJ32
RSVD52 AK32
RSVD27
J15
RSVD16
C30 RSVD15
D23
RSVD17
A31
RSVD18
B30
RSVD20
D30 RSVD19
B29
RSVD22
A30 RSVD21
B31
RSVD23
C29
RSVD37 T8
RSVD8
F25
RSVD9
F24
RSVD11
D24
RSVD12
G25
RSVD13
G24
RSVD14
E23
RSVD32 W8
RSVD33 AT26
RSVD_NCTF4 AP35
RSVD10
F23
RSVD5
AJ26
VAXG_VAL_SENSE
AJ31
VSSAXG_VAL_SENSE
AH31
VCC_VAL_SENSE
AJ33
VSS_VAL_SENSE
AH33
KEY B1
VCC_DIE_SENSE AH27
BCLK_ITP AN35
BCLK_ITP# AM35
VSS_DIE_SENSE AH26
RSVD31 AK2
RSVD30 AE7
RSVD29 AG7
RSVD28 L7
RSVD24
J20
RSVD25
B18
T13PAD T13PAD
R187
49.9_0402_1%
R187
49.9_0402_1%
1 2
R72 100_0402_1%@R72 100_0402_1%@1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VSSSENSE_R
VCCSENSE_R
VSSIO_SENSE
H_CPU_SVIDCLK
H_CPU_SVIDDAT
H_CPU_SVIDALRT#
VCCIO_SENSE <55>
VCCSENSE <57>
VSSSENSE <57>
VR_SVID_ALRT# <57>
VR_SVID_CLK <57>
VR_SVID_DAT <57>
VSSIO_SENSE <55>
+VCC_CORE
+VCC_CORE
+1.05VS
+1.05VS
+1.05VS
+1.05VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(5/7) PWR,BYPASS
Custom
964Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(5/7) PWR,BYPASS
Custom
964Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(5/7) PWR,BYPASS
Custom
964Monday, January 16, 2012
2011/07/21 2012/12/31
DC=53A
Compal Electronics, Inc.
QC=94A
Place the PU resistor close to CPU
VCC_SENCE 100ohm +-1% pull-up to VCC near processor
VSS_SENCE 100ohm +-1% pull-down to GND near processor
8.5A
Place the PU resistor close to CPU
R53 0_0402_5%R53 0_0402_5%
1 2
R1297
10_0402_1%
R1297
10_0402_1%
1 2
R1294 10_0402_1%R1294 10_0402_1%
12
R54
100_0402_1%
R54
100_0402_1%
12
R50 130_0402_5%R50 130_0402_5%
12
R47 43_0402_5%R47 43_0402_5%
1 2
C36
0.1U_0402_10V7K
C36
0.1U_0402_10V7K
1
2
R51
100_0402_1%
R51
100_0402_1%
12
R49 0_0402_5%R49 0_0402_5%
1 2
POWER
CORE SUPPLY
PEG AND DDR
SENSE LINES SVID
JCPU1F
TYCO_2013620-2_IVY BRIDGE
ME@
POWER
CORE SUPPLY
PEG AND DDR
SENSE LINES SVID
JCPU1F
TYCO_2013620-2_IVY BRIDGE
ME@
VCC_SENSE AJ35
VSS_SENSE AJ34
VIDALERT# AJ29
VIDSCLK AJ30
VIDSOUT AJ28
VSS_SENSE_VCCIO A10
VCC1
AG35
VCC2
AG34
VCC3
AG33
VCC4
AG32
VCC5
AG31
VCC6
AG30
VCC7
AG29
VCC8
AG28
VCC9
AG27
VCC10
AG26
VCC11
AF35
VCC12
AF34
VCC13
AF33
VCC14
AF32
VCC15
AF31
VCC16
AF30
VCC17
AF29
VCC18
AF28
VCC19
AF27
VCC20
AF26
VCC21
AD35
VCC22
AD34
VCC23
AD33
VCC24
AD32
VCC25
AD31
VCC26
AD30
VCC27
AD29
VCC28
AD28
VCC29
AD27
VCC30
AD26
VCC31
AC35
VCC32
AC34
VCC33
AC33
VCC34
AC32
VCC35
AC31
VCC36
AC30
VCC37
AC29
VCC38
AC28
VCC39
AC27
VCC40
AC26
VCC41
AA35
VCC42
AA34
VCC43
AA33
VCC44
AA32
VCC45
AA31
VCC46
AA30
VCC47
AA29
VCC48
AA28
VCC49
AA27
VCC50
AA26
VCC51
Y35
VCC52
Y34
VCC53
Y33
VCC54
Y32
VCC55
Y31
VCC56
Y30
VCC57
Y29
VCC58
Y28
VCC59
Y27
VCC60
Y26
VCC61
V35
VCC62
V34
VCC63
V33
VCC64
V32
VCC65
V31
VCC66
V30
VCC67
V29
VCC68
V28
VCC69
V27
VCC70
V26
VCC71
U35
VCC72
U34
VCC73
U33
VCC74
U32
VCC75
U31
VCC76
U30
VCC77
U29
VCC78
U28
VCC79
U27
VCC80
U26
VCC81
R35
VCC82
R34
VCC83
R33
VCC84
R32
VCC85
R31
VCC86
R30
VCC87
R29
VCC88
R28
VCC89
R27
VCC90
R26
VCC91
P35
VCC92
P34
VCC93
P33
VCC94
P32
VCC95
P31
VCC96
P30
VCC97
P29
VCC98
P28
VCC99
P27
VCC100
P26
VCCIO1 AH13
VCCIO12 J11
VCCIO18 G12
VCCIO19 F14
VCCIO20 F13
VCCIO21 F12
VCCIO22 F11
VCCIO23 E14
VCCIO24 E12
VCCIO2 AH10
VCCIO3 AG10
VCCIO4 AC10
VCCIO5 Y10
VCCIO6 U10
VCCIO7 P10
VCCIO8 L10
VCCIO9 J14
VCCIO10 J13
VCCIO11 J12
VCCIO13 H14
VCCIO14 H12
VCCIO15 H11
VCCIO16 G14
VCCIO17 G13
VCCIO25 E11
VCCIO32 C12
VCCIO33 C11
VCCIO34 B14
VCCIO35 B12
VCCIO36 A14
VCCIO37 A13
VCCIO38 A12
VCCIO39 A11
VCCIO26 D14
VCCIO27 D13
VCCIO28 D12
VCCIO29 D11
VCCIO30 C14
VCCIO31 C13
VCCIO_SENSE B10
VCCIO40 J23
R52 0_0402_5%R52 0_0402_5%
1 2
R46
75_0402_5%
R46
75_0402_5%
12
R48 0_0402_5%R48 0_0402_5%
1 2
R73 100_0402_1%@R73 100_0402_1%@1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.8VS_VCCPLL
RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3
RUN_ON_CPU1.5VS3#
+VCCSA
RUN_ON_CPU1.5VS3
+V_SM_VREF_CNT +V_SM_VREF
H_VCCP_SEL
+V_DDR_REFA_R
DRAMRST_CNTRL
+V_DDR_REFB_R
+V_DDR_REFA_R
+V_DDR_REFB_R
VCC_AXG_SENSE <57>
VSS_AXG_SENSE <57>
SUSP#<42,48,53,55,56>
CPU1.5V_S3_GATE<42,48,55>
SUSP<48,53,55>
H_VCCSA_VID1 <54>
H_VCCSA_VID0 <54>
DRAMRST_CNTRL<7>
RUN_ON_CPU1.5VS3#<6>
+VCCSA_SENSE <54>
+1.5V_CPU_VDDQ
+1.8VS
+VCC_GFXCORE_AXG
+1.5V
+1.5V_CPU_VDDQ
+1.5V +1.5V_CPU_VDDQ
+VSB
+3VALW
+VCCSA
+1.5V
+3VALW
+3VS
+VREF_DQ_DIMMA
+VREF_DQ_DIMMB
+VCC_GFXCORE_AXG
+1.5V_CPU_VDDQ
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(6/7) PWR
Custom
10 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(6/7) PWR
Custom
10 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(6/7) PWR
Custom
10 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
6/9 change 330U to 22U X2
Place the PU/PD resistor close to CPU within 2 inch
(Reserve power side)
All VREF traces should keep 20/20 mils(wide/spacing)
46A
5A
6A
6/3 modify for VCCSA 4-Level voltage
VCCIO_SEL Voltage
1
0
1.05V
1.0V
6/3 Add VCCIO_SEL for processor select
6/8 Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
6/28 Follow module design
11/07 Change type to 0603
11/07 Change type to 0603
R57
330K_0402_5%
@
R57
330K_0402_5%
@
12
C118
10U_0603_6.3V6M
C118
10U_0603_6.3V6M
1
2
C126
10U_0603_6.3V6M
C126
10U_0603_6.3V6M
1
2
R68 0_0402_5%
@
R68 0_0402_5%
@
1 2
R266
10K_0402_5%@
R266
10K_0402_5%@
12
R66
100_0402_1%
R66
100_0402_1%
1 2
G
D
S
Q9
2N7002_SOT23
@
G
D
S
Q9
2N7002_SOT23
@
2
13
R63
1K_0402_1%
@R63
1K_0402_1%
@
12
C120
10U_0603_6.3V6M
C120
10U_0603_6.3V6M
1
2
C122
10U_0603_6.3V6M
C122
10U_0603_6.3V6M
1
2
C345
22U_0805_6.3V6M
@
C345
22U_0805_6.3V6M
@
1
2
G
D
S
Q8 BSS138_SOT23
G
D
S
Q8 BSS138_SOT23
2
1 3
C286
0.1U_0402_10V6K
C286
0.1U_0402_10V6K
1
2
C119
10U_0603_6.3V6M
C119
10U_0603_6.3V6M
1
2
C96
0.1U_0402_10V6K
C96
0.1U_0402_10V6K
1
2
R75 0_0402_5%
@
R75 0_0402_5%
@
1 2
R74 0_0402_5%
@
R74 0_0402_5%
@
1 2
U3
DMN3030LSS-13_SOP8L-8
U3
DMN3030LSS-13_SOP8L-8
S1
S2
S3
G4
D
8
D
7
D
6
D
5
J1
PAD-OPEN 4x4m
@J1
PAD-OPEN 4x4m
@
1 2
R667
100K_0402_5%
@
R667
100K_0402_5%
@
12
C279
22U_0805_6.3V6M
@
C279
22U_0805_6.3V6M
@
1
2
C130
10U_0603_6.3V6M
C130
10U_0603_6.3V6M
1
2
C131
1U_0402_6.3V6K
C131
1U_0402_6.3V6K
1
2
R590_0402_5% @R590_0402_5% @
1 2
R61
0_0402_5%
@R61
0_0402_5%
@
12
R89 100_0402_1%R89 100_0402_1%
12
G
D
S
Q7 BSS138_SOT23
G
D
S
Q7 BSS138_SOT23
2
1 3
C287
0.1U_0402_10V6K
C287
0.1U_0402_10V6K
1
2
+
C128
330U_D2_2.5VY_R9M
@
+
C128
330U_D2_2.5VY_R9M
@
1
2
R234
10K_0402_5%
R234
10K_0402_5%
12
R56
100K_0402_5%
R56
100K_0402_5%
12
Q5
AP2302GN-HF_SOT23-3
@Q5
AP2302GN-HF_SOT23-3
@
3
1
2
R76 100_0402_1%@R76 100_0402_1%@
1 2
C95
0.1U_0402_10V6K
C95
0.1U_0402_10V6K
1
2
C117
10U_0603_6.3V6M
C117
10U_0603_6.3V6M
1
2
R88
1K_0402_1%
R88
1K_0402_1%
12
POWER
GRAPHICS
DDR3 -1.5V RAILS SENSE
LINES
1.8V RAIL
SA RAIL
VREFMISC
JCPU1G
TYCO_2013620-2_IVY BRIDGE
ME@
POWER
GRAPHICS
DDR3 -1.5V RAILS SENSE
LINES
1.8V RAIL
SA RAIL
VREFMISC
JCPU1G
TYCO_2013620-2_IVY BRIDGE
ME@
SM_VREF AL1
VSSAXG_SENSE AK34
VAXG_SENSE AK35
VAXG1
AT24
VAXG2
AT23
VAXG3
AT21
VAXG4
AT20
VAXG5
AT18
VAXG6
AT17
VAXG7
AR24
VAXG8
AR23
VAXG9
AR21
VAXG10
AR20
VAXG11
AR18
VAXG12
AR17
VAXG13
AP24
VAXG14
AP23
VAXG15
AP21
VAXG16
AP20
VAXG17
AP18
VAXG18
AP17
VAXG19
AN24
VAXG20
AN23
VAXG21
AN21
VAXG22
AN20
VAXG23
AN18
VAXG24
AN17
VAXG25
AM24
VAXG26
AM23
VAXG27
AM21
VAXG28
AM20
VAXG29
AM18
VAXG30
AM17
VAXG31
AL24
VAXG32
AL23
VAXG33
AL21
VAXG34
AL20
VAXG35
AL18
VAXG36
AL17
VAXG37
AK24
VAXG38
AK23
VAXG39
AK21
VAXG40
AK20
VAXG41
AK18
VAXG42
AK17
VAXG43
AJ24
VAXG44
AJ23
VAXG45
AJ21
VAXG46
AJ20
VAXG47
AJ18
VAXG48
AJ17
VAXG49
AH24
VAXG50
AH23
VAXG51
AH21
VAXG52
AH20
VAXG53
AH18
VAXG54
AH17
VDDQ11 U4
VDDQ12 U1
VDDQ13 P7
VDDQ14 P4
VDDQ15 P1
VDDQ1 AF7
VDDQ2 AF4
VDDQ3 AF1
VDDQ4 AC7
VDDQ5 AC4
VDDQ6 AC1
VDDQ7 Y7
VDDQ8 Y4
VDDQ9 Y1
VDDQ10 U7
VCCPLL1
B6
VCCPLL2
A6
VCCSA1 M27
VCCSA2 M26
VCCSA3 L26
VCCSA4 J26
VCCSA5 J25
VCCSA6 J24
VCCSA7 H26
VCCSA8 H25
VCCSA_SENSE H23
VCCSA_VID[1] C24
VCCPLL3
A2 VCCSA_VID[0] C22
SA_DIMM_VREFDQ B4
SB_DIMM_VREFDQ D1
VCCIO_SEL A19
C92
0.1U_0402_10V6K
@C92
0.1U_0402_10V6K
@
1
2
C114
0.1U_0402_16V4Z
C114
0.1U_0402_16V4Z 1
2
C124
10U_0603_6.3V6M
C124
10U_0603_6.3V6M
1
2
R580_0402_5% @R580_0402_5% @
1 2
R1349
470K_0402_5%
R1349
470K_0402_5%
1 2
R132
1K_0402_1%
@
R132
1K_0402_1%
@
12
R6680_0402_5% R6680_0402_5%
1 2
R77
1K_0402_1%
R77
1K_0402_1%
12
C125
10U_0603_6.3V6M
C125
10U_0603_6.3V6M
1
2
R67
0_0805_5%
R67
0_0805_5%
1 2
R139
1K_0402_1%
@
R139
1K_0402_1%
@
12
R69 0_0402_5%R69 0_0402_5%
1 2
C127
10U_0603_6.3V6M
@
C127
10U_0603_6.3V6M
@
1
2
G
D
S
Q3
2N7002_SOT23
@
G
D
S
Q3
2N7002_SOT23
@
2
13
G
D
S
Q4
2N7002_SOT23
G
D
S
Q4
2N7002_SOT23
2
13
C97
0.01U_0603_50V7K
C97
0.01U_0603_50V7K
1
2
R62
1K_0402_1%
@R62
1K_0402_1%
@
12
+
C123
330U_D2_2.5VY_R9M
@
+
C123
330U_D2_2.5VY_R9M
@
1
2
C121
10U_0603_6.3V6M
C121
10U_0603_6.3V6M
1
2
C132
1U_0402_6.3V6K
C132
1U_0402_6.3V6K
1
2
R55
220_0402_5%
@
R55
220_0402_5%
@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(7/7) VSS
Custom
11 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(7/7) VSS
Custom
11 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PROCESSOR(7/7) VSS
Custom
11 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
VSS
JCPU1H
TYCO_2013620-2_IVY BRIDGE
ME@
VSS
JCPU1H
TYCO_2013620-2_IVY BRIDGE
ME@
VSS1
AT35
VSS2
AT32
VSS3
AT29
VSS4
AT27
VSS5
AT25
VSS6
AT22
VSS7
AT19
VSS8
AT16
VSS9
AT13
VSS10
AT10
VSS11
AT7
VSS12
AT4
VSS13
AT3
VSS14
AR25
VSS15
AR22
VSS16
AR19
VSS17
AR16
VSS18
AR13
VSS19
AR10
VSS20
AR7
VSS21
AR4
VSS22
AR2
VSS23
AP34
VSS24
AP31
VSS25
AP28
VSS26
AP25
VSS27
AP22
VSS28
AP19
VSS29
AP16
VSS30
AP13
VSS31
AP10
VSS32
AP7
VSS33
AP4
VSS34
AP1
VSS35
AN30
VSS36
AN27
VSS37
AN25
VSS38
AN22
VSS39
AN19
VSS40
AN16
VSS41
AN13
VSS42
AN10
VSS43
AN7
VSS44
AN4
VSS45
AM29
VSS46
AM25
VSS47
AM22
VSS48
AM19
VSS49
AM16
VSS50
AM13
VSS51
AM10
VSS52
AM7
VSS53
AM4
VSS54
AM3
VSS55
AM2
VSS56
AM1
VSS57
AL34
VSS58
AL31
VSS59
AL28
VSS60
AL25
VSS61
AL22
VSS62
AL19
VSS63
AL16
VSS64
AL13
VSS65
AL10
VSS66
AL7
VSS67
AL4
VSS68
AL2
VSS69
AK33
VSS70
AK30
VSS71
AK27
VSS72
AK25
VSS73
AK22
VSS74
AK19
VSS75
AK16
VSS76
AK13
VSS77
AK10
VSS78
AK7
VSS79
AK4
VSS80
AJ25
VSS81 AJ22
VSS82 AJ19
VSS83 AJ16
VSS84 AJ13
VSS85 AJ10
VSS86 AJ7
VSS87 AJ4
VSS88 AJ3
VSS89 AJ2
VSS90 AJ1
VSS91 AH35
VSS92 AH34
VSS93 AH32
VSS94 AH30
VSS95 AH29
VSS96 AH28
VSS98 AH25
VSS99 AH22
VSS100 AH19
VSS101 AH16
VSS102 AH7
VSS103 AH4
VSS104 AG9
VSS105 AG8
VSS106 AG4
VSS107 AF6
VSS108 AF5
VSS109 AF3
VSS110 AF2
VSS111 AE35
VSS112 AE34
VSS113 AE33
VSS114 AE32
VSS115 AE31
VSS116 AE30
VSS117 AE29
VSS118 AE28
VSS119 AE27
VSS120 AE26
VSS121 AE9
VSS122 AD7
VSS123 AC9
VSS124 AC8
VSS125 AC6
VSS126 AC5
VSS127 AC3
VSS128 AC2
VSS129 AB35
VSS130 AB34
VSS131 AB33
VSS132 AB32
VSS133 AB31
VSS134 AB30
VSS135 AB29
VSS136 AB28
VSS137 AB27
VSS138 AB26
VSS139 Y9
VSS140 Y8
VSS141 Y6
VSS142 Y5
VSS143 Y3
VSS144 Y2
VSS145 W35
VSS146 W34
VSS147 W33
VSS148 W32
VSS149 W31
VSS150 W30
VSS151 W29
VSS152 W28
VSS153 W27
VSS154 W26
VSS155 U9
VSS156 U8
VSS157 U6
VSS158 U5
VSS159 U3
VSS160 U2
VSS
JCPU1I
TYCO_2013620-2_IVY BRIDGE
ME@
VSS
JCPU1I
TYCO_2013620-2_IVY BRIDGE
ME@
VSS161
T35
VSS162
T34
VSS163
T33
VSS164
T32
VSS165
T31
VSS166
T30
VSS167
T29
VSS168
T28
VSS169
T27
VSS170
T26
VSS171
P9
VSS172
P8
VSS173
P6
VSS174
P5
VSS175
P3
VSS176
P2
VSS177
N35
VSS178
N34
VSS179
N33
VSS180
N32
VSS181
N31
VSS182
N30
VSS183
N29
VSS184
N28
VSS185
N27
VSS186
N26
VSS187
M34
VSS188
L33
VSS189
L30
VSS190
L27
VSS191
L9
VSS192
L8
VSS193
L6
VSS194
L5
VSS195
L4
VSS196
L3
VSS197
L2
VSS198
L1
VSS199
K35
VSS200
K32
VSS201
K29
VSS202
K26
VSS203
J34
VSS204
J31
VSS205
H33
VSS206
H30
VSS207
H27
VSS208
H24
VSS209
H21
VSS210
H18
VSS211
H15
VSS212
H13
VSS213
H10
VSS214
H9
VSS215
H8
VSS216
H7
VSS217
H6
VSS218
H5
VSS219
H4
VSS220
H3
VSS221
H2
VSS222
H1
VSS223
G35
VSS224
G32
VSS225
G29
VSS226
G26
VSS227
G23
VSS228
G20
VSS229
G17
VSS230
G11
VSS231
F34
VSS232
F31
VSS233
F29
VSS234 F22
VSS235 F19
VSS236 E30
VSS237 E27
VSS238 E24
VSS239 E21
VSS240 E18
VSS241 E15
VSS242 E13
VSS243 E10
VSS244 E9
VSS245 E8
VSS246 E7
VSS247 E6
VSS248 E5
VSS249 E4
VSS250 E3
VSS251 E2
VSS252 E1
VSS253 D35
VSS254 D32
VSS255 D29
VSS256 D26
VSS257 D20
VSS258 D17
VSS259 C34
VSS260 C31
VSS261 C28
VSS262 C27
VSS263 C25
VSS264 C23
VSS265 C10
VSS266 C1
VSS267 B22
VSS268 B19
VSS269 B17
VSS270 B15
VSS271 B13
VSS272 B11
VSS273 B9
VSS274 B8
VSS275 B7
VSS276 B5
VSS277 B3
VSS278 B2
VSS279 A35
VSS280 A32
VSS281 A29
VSS282 A26
VSS283 A23
VSS284 A20
VSS285 A3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D31
DDR_A_D12
DDR_CKE0_DIMMA
DDR_A_D59
DDR_A_D6
DDR_A_MA3
DDR_CS1_DIMMA#
DDR_A_D39
DDR_A_BS1
DDR_A_DQS0
DDR_A_WE#
DDR_A_MA7
DDR_A_MA0
DDR_A_DM2
DDR_A_DM1
DDR_A_DQS7
DDR_A_D0
DDR_A_D57
DDR_A_D46
DDR_A_D28
DDR_A_DM0
DDR_A_D19
DDR_A_DQS#5
DDR_A_D51
DDR_A_D4
DDR_A_DM4
DDR_A_D30
DDR_A_DQS2
DDR_A_D44
DDR_A_RAS#
DDR_A_D33
DDR_A_D58
DDR_A_DM5
DDR_A_DQS3
DDR_A_MA8
DDR_CS0_DIMMA#
DDR_A_D10
DDR_A_MA6
DDR_A_D27
DDR_A_D3
DDR3_DRAMRST#
DDR_A_MA10
DDR_A_DQS#7
DDR_A_D1
DDR_A_DQS#6
DDR_A_D40
DDR_A_MA9
DDR_A_D16
DDR_A_D29
DDR_A_DQS#4
DDR_A_D52
DDR_A_DM3
DDR_A_DQS5
DDR_A_D54
DDR_A_D49
DDR_A_BS2
DDR_A_D45
DDR_A_D9
DDR_A_DM7
DDR_A_D7
DDR_A_MA1
DDR_A_D13
DDR_A_D20
DDR_A_D60
DDR_A_BS0
DDR_A_CAS# M_ODT0
DDR_A_D37
DDR_A_MA5
DDR_A_DQS#1
DDR_A_MA14
DDR_A_D55
DDR_A_MA4
DDR_A_D21
DDR_A_D62
DDR_A_D24
DDR_A_D15
DDR_A_D23
DDR_A_D56
DDR_A_D53
DDR_A_D47
DDR_A_D18
M_ODT1
DDR_A_D43
DDR_A_D34
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_D48
DDR_A_DQS#2
DDR_A_D11
DDR_A_D38
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_DQS#3
DDR_A_D32
DDR_A_D8
DDR_A_DQS1
DDR_A_MA13
DDR_A_MA11
DDR_A_D50
DDR_A_D61
DDR_A_MA2
DDR_A_D41
DDR_A_D17
DDR_A_D36
DDR_A_D26
DDR_A_D63
DDR_A_D2
DDR_A_D5
DDR_A_D22
DDR_A_D25
DDR_A_DQS6
DDR_A_D35
DDR_A_D14
DDR_A_MA12
DDR_A_DQS#0
DDR_A_DQS4
DDR_A_DM6
DDR_A_D42
DDR_CKE1_DIMMA
+VREF_CA
+VREF_DQ_DIMMA
DDR_A_MA15
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
SMB_CLK_S3
SMB_DATA_S3
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..15]<7>
DDR_CKE0_DIMMA<7>
DDR_A_BS2<7>
M_CLK_DDR0<7>
M_CLK_DDR#0<7>
DDR_A_BS0<7>
DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_CS1_DIMMA#<7>
DDR_CKE1_DIMMA <7>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA# <7>
M_ODT0 <7>
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
M_ODT1 <7>
DDR3_DRAMRST# <7,13>
SMB_CLK_S3 <13,15,36>
SMB_DATA_S3 <13,15,36>
+0.75VS
+3VS
+VREF_DQ_DIMMA
+0.75VS
+1.5V+1.5V
+1.5V
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
DDRIII-SODIMM SLOT1
Custom
12 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
QIWY3 LA-8001P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
DDRIII-SODIMM SLOT1
Custom
12 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
QIWY3 LA-8001P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
DDRIII-SODIMM SLOT1
Custom
12 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
QIWY3 LA-8001P
DDR3 SO-DIMM A
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
C156
0.1U_0402_10V6K
C156
0.1U_0402_10V6K
1
2
C151
10U_0603_6.3V6M
@
C151
10U_0603_6.3V6M
@
1
2
+
C148
220U_6.3V_M
+
C148
220U_6.3V_M
1
2
R82
10K_0402_5%
R82
10K_0402_5%
1 2
C154
0.1U_0402_10V6K
C154
0.1U_0402_10V6K
1
2
C159
1U_0402_6.3V6K
C159
1U_0402_6.3V6K
1
2
R78
1K_0402_1%
R78
1K_0402_1%
12
C145
10U_0603_6.3V6M
C145
10U_0603_6.3V6M
1
2
R81
1K_0402_1%
R81
1K_0402_1%
12
C160
1U_0402_6.3V6K
C160
1U_0402_6.3V6K
1
2
C140
0.1U_0402_10V6K
C140
0.1U_0402_10V6K
1
2
R79
1K_0402_1%
R79
1K_0402_1%
12
C288
1U_0402_6.3V6K
C288
1U_0402_6.3V6K
1
2
R80
1K_0402_1%
R80
1K_0402_1%
12
C146
10U_0603_6.3V6M
C146
10U_0603_6.3V6M
1
2
C153
10U_0603_6.3V6M
C153
10U_0603_6.3V6M
1
2
C143
10U_0603_6.3V6M
C143
10U_0603_6.3V6M
1
2
C149
0.1U_0402_10V6K
C149
0.1U_0402_10V6K
1
2
C144
10U_0603_6.3V6M
C144
10U_0603_6.3V6M
1
2
JDIMM1
LCN_DAN06-K4806-0103
ME@
JDIMM1
LCN_DAN06-K4806-0103
ME@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
C150
2.2U_0603_6.3V6K
C150
2.2U_0603_6.3V6K
1
2
C155
0.1U_0402_10V6K
C155
0.1U_0402_10V6K
1
2
C162
0.1U_0402_10V6K
C162
0.1U_0402_10V6K
1
2
C290
2.2U_0603_6.3V6K
C290
2.2U_0603_6.3V6K
1
2
C141
2.2U_0603_6.3V6K
C141
2.2U_0603_6.3V6K
1
2
C142
10U_0603_6.3V6M
@
C142
10U_0603_6.3V6M
@
1
2
R83
10K_0402_5%
R83
10K_0402_5%
12
C147
0.1U_0402_10V6K
C147
0.1U_0402_10V6K
1
2
C158
1U_0402_6.3V6K
C158
1U_0402_6.3V6K
1
2
C152
10U_0603_6.3V6M
C152
10U_0603_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_D36
DDR_B_D63
DDR_B_MA15
DDR_B_DM6
DDR_B_D39
DDR_B_BS1
DDR_B_MA7
DDR_B_MA0
DDR_B_DQS7
DDR_B_D46
DDR_B_DQS#5
DDR_B_DM4
DDR_B_D44
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_MA6
DDR_B_DQS#7
DDR_B_D52
DDR_B_DQS5
DDR_B_D54
DDR_B_D45
DDR_B_D60
M_ODT2
DDR_B_D37
DDR_B_MA14
DDR_B_D55
DDR_B_MA4
DDR_B_D62
DDR_B_D53
DDR_B_D47
M_ODT3
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_D38
DDR_B_MA11
DDR_B_D61
DDR_B_MA2
SMB_CLK_S3
SMB_DATA_S3
DDR_B_DQS6
DDR_B_D35
DDR_B_MA12
DDR_B_DQS4
DDR_B_D42
DDR_CKE2_DIMMB
DDR_B_D59
DDR_B_MA3
DDR_CS3_DIMMB#
DDR_B_WE#
DDR_B_D57
DDR_B_D51
DDR_B_D33
DDR_B_D58
DDR_B_DM5
DDR_B_MA8
DDR_B_MA10
DDR_B_DQS#6
DDR_B_D40
DDR_B_MA9
DDR_B_DQS#4
DDR_B_D49
DDR_B_BS2
DDR_B_DM7
DDR_B_MA1
DDR_B_BS0
DDR_B_CAS#
DDR_B_MA5
DDR_B_D56
DDR_B_D43
DDR_B_D34
DDR_B_D48
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_D32
DDR_B_MA13
DDR_B_D50
DDR_B_D41
DDR_B_DM6
DDR_B_DM7
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
+VREF_CB
DDR_B_D5
DDR_B_D22
DDR_B_D14
DDR_B_DQS#0
DDR_B_D31
DDR_B_D12
DDR_B_D6
DDR_B_DQS0
DDR_B_DM2
DDR_B_DM1
DDR_B_D28
DDR_B_D4
DDR_B_D30
DDR_B_DQS3
DDR3_DRAMRST#
DDR_B_D29
DDR_B_D7
DDR_B_D13
DDR_B_D20
DDR_B_D21
DDR_B_D15
DDR_B_D23
DDR_B_DQS#3
DDR_CKE3_DIMMB
DDR_B_D26
DDR_B_D2
DDR_B_D25
+VREF_DQ_DIMMB
DDR_B_D0
DDR_B_DM0
DDR_B_D19
DDR_B_DQS2
DDR_B_D10
DDR_B_D27
DDR_B_D3
DDR_B_D1
DDR_B_D16
DDR_B_DM3
DDR_B_D9
DDR_B_DQS#1
DDR_B_D24
DDR_B_D18
DDR_B_DQS#2
DDR_B_D11
DDR_B_D8
DDR_B_DQS1
DDR_B_D17
DDR3_DRAMRST# <7,12>
DDR_B_DQS#[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>
DDR_B_MA[0..15]<7>
DDR_CKE3_DIMMB <7>
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDR_CS2_DIMMB# <7>
M_ODT2 <7>
M_ODT3 <7>
SMB_DATA_S3 <12,15,36>
SMB_CLK_S3 <12,15,36>
DDR_B_BS2<7>
DDR_CKE2_DIMMB<7>
M_CLK_DDR2<7>
M_CLK_DDR#2<7>
DDR_B_BS0<7>
DDR_B_WE#<7>
DDR_B_CAS#<7>
DDR_CS3_DIMMB#<7>
+0.75VS
+3VS
+0.75VS
+1.5V+1.5V
+1.5V
+1.5V
+VREF_DQ_DIMMB
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
DDRIII-SODIMM SLOT2
13 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
QIWY3 LA-8001P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
DDRIII-SODIMM SLOT2
13 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
QIWY3 LA-8001P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
DDRIII-SODIMM SLOT2
13 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
QIWY3 LA-8001P
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
C178
0.1U_0402_10V6K
C178
0.1U_0402_10V6K
1
2
C161
10U_0603_6.3V6M
@
C161
10U_0603_6.3V6M
@
1
2
C281
2.2U_0603_6.3V6K
C281
2.2U_0603_6.3V6K
1
2
C174
1U_0402_6.3V6K
C174
1U_0402_6.3V6K
1
2
JDIMM2
TYCO_2-2013287-1
ME@
JDIMM2
TYCO_2-2013287-1
ME@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
C173
1U_0402_6.3V6K
C173
1U_0402_6.3V6K
1
2
C280
0.1U_0402_10V6K
C280
0.1U_0402_10V6K
1
2
C167
10U_0603_6.3V6M
C167
10U_0603_6.3V6M
1
2
C176
1U_0402_6.3V6K
C176
1U_0402_6.3V6K
1
2
C168
10U_0603_6.3V6M
C168
10U_0603_6.3V6M
1
2
R97 10K_0402_5%R97 10K_0402_5%
1 2
C175
1U_0402_6.3V6K
C175
1U_0402_6.3V6K
1
2
C169
0.1U_0402_10V6K
C169
0.1U_0402_10V6K
1
2
C289
2.2U_0603_6.3V6K
C289
2.2U_0603_6.3V6K
1
2
C177
2.2U_0603_6.3V6K
C177
2.2U_0603_6.3V6K
1
2
C282
10U_0603_6.3V6M
@
C282
10U_0603_6.3V6M
@
1
2
C172
0.1U_0402_10V6K
C172
0.1U_0402_10V6K
1
2
R95
10K_0402_5%
R95
10K_0402_5%
1 2
C166
10U_0603_6.3V6M
C166
10U_0603_6.3V6M
1
2
R86
1K_0402_1%
R86
1K_0402_1%
12
C165
10U_0603_6.3V6M
C165
10U_0603_6.3V6M
1
2
R85
1K_0402_1%
R85
1K_0402_1%
12
C164
10U_0603_6.3V6M
C164
10U_0603_6.3V6M
1
2
C157
0.1U_0402_10V6K
C157
0.1U_0402_10V6K
1
2
R84
1K_0402_1%
R84
1K_0402_1%
12
C170
0.1U_0402_10V6K
C170
0.1U_0402_10V6K
1
2
C163
10U_0603_6.3V6M
C163
10U_0603_6.3V6M
1
2
R87
1K_0402_1%
R87
1K_0402_1%
12
C171
0.1U_0402_10V6K
C171
0.1U_0402_10V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_RTCX1
PCH_RTCX2
PCH_RTCX1
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
SM_INTRUDER#
HDA_SPKR
SPI_CLK_PCH
SPI_SI
SPI_SO_R
SPI_SB_CS0#
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
HDA_SYNC
HDA_RST#
HDA_SDIN0
HDA_SDOUT
PCH_GPIO21
PCH_RTCX2
HDA_BIT_CLK
PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS
LPC_AD2
LPC_FRAME#
LPC_AD0
LPC_AD3
LPC_AD1
SATA_COMP
RBIAS_SATA3
SATA3_COMP
HDA_BIT_CLK
HDA_RST#
HDA_SDOUT
HDA_SPKR
HDA_SDOUT
HDA_SYNC
SPI_WP#
SPI_HOLD#
SPI_WP#
SPI_HOLD#
SPI_SB_CS0#_R
SPI_SO_R SPI_SO_L
SPI_SI_R
SPI_CLK_PCH_0
SPI_CLK_PCH
SPI_SB_CS0#
PCH_GPIO33
SATA_ITX_DRX_P0
SATA_ITX_DRX_N0
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
SPI_SI
SATA_ITX_DRX_N2_CONN
SATA_DTX_C_IRX_N2
SATA_ITX_DRX_P2_CONN
SATA_DTX_C_IRX_P2
SATA_ITX_C_DRX_N2
SATA_ITX_C_DRX_P2
ME_FLASH
HDA_SYNC
SATA_ITX_DRX_P1
SATA_ITX_DRX_N1
SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1
PCH_INTVRMENPCH_INTVRMEN
SPI_CLK_PCH
HDA_SYNC_R
PCH_GPIO13
SPI_CLK_PCHSPI_WP#_1
SPI_HOLD#_1
SPI_SB_CS1#_R
SPI_SO_R SPI_SO_L1
SPI_SB_CS1#
SPI_SI_R1
SPI_CLK_PCH_1
SPI_SI
SPI_SB_CS1#
SPI_WP#_1
SPI_HOLD#_1
BBS_BIT0_R
SERIRQ
SATALED#
HDA_SPKR<41>
LPC_AD0 <36,42>
LPC_AD1 <36,42>
LPC_AD2 <36,42>
LPC_AD3 <36,42>
LPC_FRAME# <36,42>
HDA_SYNC_AUDIO<41>
HDA_SDOUT_AUDIO<41>
HDA_RST_AUDIO#<41>
HDA_BITCLK_AUDIO<41>
SATA_DTX_C_IRX_N0 <36>
SATA_DTX_C_IRX_P0 <36>
SATA_ITX_DRX_N0 <36>
SATA_ITX_DRX_P0 <36>
SATA_DTX_C_IRX_P2 <40>
SATA_ITX_DRX_N2_CONN <40>
SATA_DTX_C_IRX_N2 <40>
SATA_ITX_DRX_P2_CONN <40>
ME_FLASH<42>
SATA_ITX_DRX_N1 <40>
SATA_ITX_DRX_P1 <40>
SATA_DTX_C_IRX_N1 <40>
SATA_DTX_C_IRX_P1 <40>
HDA_SDIN0<41>
SATA_DET# <36>
SERIRQ <42>
+RTCVCC
+RTCVCC
+1.05VS_VCC_SATA
+1.05VS_SATA3
+3VS
+3V_PCH
+3VS
+3VS
+RTCBATT+RTCVCC
+3VS
+5VS
+3VS
+3V_PCH
+3V_PCH +3V_PCH +3V_PCH
+3V_PCH
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (1/8) SATA,HDA,SPI, LPC, XDP
Custom
14 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (1/8) SATA,HDA,SPI, LPC, XDP
Custom
14 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (1/8) SATA,HDA,SPI, LPC, XDP
Custom
14 64Monday, January 16, 2012
2011/07/21 2012/12/31
CMOS
HDD
Compal Electronics, Inc.
HIntegrated VRM enable
LIntegrated VRM disable
INTVRMEN
*
LOW= Disable (Default)
HIGH= Enable ( No Reboot )
*
*
Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Chief River platfrom
*
(INTVRMEN should always be pull high.)
W=20milsW=20mils
EC and Mini card debug port
ODD
SSD
11/08 Follow DG change to +5VS
U5
W25Q32BVSSIG_SO8
U5
W25Q32BVSSIG_SO8
CS#
1
DO
2
WP#
3
GND
4
VCC 8
HOLD# 7
CLK 6
DI 5
R108 1K_0402_5%R108 1K_0402_5%
12
R199
33_0402_5%
R199
33_0402_5%
1 2
R103 20K_0402_5%R103 20K_0402_5%
1 2
R118
33_0402_5%
R118
33_0402_5%
1 2
R128
100_0402_1%
@
R128
100_0402_1%
@
12
C180
15P_0402_50V8J
C180
15P_0402_50V8J
1
2
U9
W25Q16BVSSIG_SO8
U9
W25Q16BVSSIG_SO8
CS#
1
DO(IO1)
2
WP#(IO2)
3
GND
4
VCC 8
HOLD#(IO3) 7
CLK 6
DI(IO0) 5
R116
33_0402_5%
R116
33_0402_5%
1 2
RTCIHDA
SATA
LPC
SPI JTAG
SATA 6G
U4A
PANTHER-POINT_FCBGA989
RTCIHDA
SATA
LPC
SPI JTAG
SATA 6G
U4A
PANTHER-POINT_FCBGA989
RTCX1
A20
RTCX2
C20
INTVRMEN
C17
INTRUDER#
K22
HDA_BCLK
N34
HDA_SYNC
L34
HDA_RST#
K34
HDA_SDIN0
E34
HDA_SDIN1
G34
HDA_SDIN2
C34
HDA_SDO
A36
SATALED# P3
FWH0 / LAD0 C38
FWH1 / LAD1 A38
FWH2 / LAD2 B37
FWH3 / LAD3 C37
LDRQ1# / GPIO23 K36
FWH4 / LFRAME# D36
LDRQ0# E36
RTCRST#
D20
HDA_SDIN3
A34
HDA_DOCK_EN# / GPIO33
C36
HDA_DOCK_RST# / GPIO13
N32
SRTCRST#
G22
SATA0RXN AM3
SATA0RXP AM1
SATA0TXN AP7
SATA0TXP AP5
SATA1RXN AM10
SATA1RXP AM8
SATA1TXN AP11
SATA1TXP AP10
SATA2RXN AD7
SATA2RXP AD5
SATA2TXN AH5
SATA2TXP AH4
SATA3RXN AB8
SATA3RXP AB10
SATA3TXN AF3
SATA3TXP AF1
SATA4RXN Y7
SATA4RXP Y5
SATA4TXN AD3
SATA4TXP AD1
SATA5RXN Y3
SATA5RXP Y1
SATA5TXN AB3
SATA5TXP AB1
SATAICOMPI Y10
SPI_CLK
T3
SPI_CS0#
Y14
SPI_CS1#
T1
SPI_MOSI
V4
SPI_MISO
U3
SATA0GP / GPIO21 V14
SATA1GP / GPIO19 P1
JTAG_TCK
J3
JTAG_TMS
H7
JTAG_TDI
K5
JTAG_TDO
H1
SERIRQ V5
SPKR
T10
SATAICOMPO Y11
SATA3COMPI AB13
SATA3RCOMPO AB12
SATA3RBIAS AH1
C1850.01U_0402_16V7K C1850.01U_0402_16V7K 12
R123
200_0402_5%
@
R123
200_0402_5%
@
12
R109
0_0402_5%
R109
0_0402_5%
1 2
R299
33_0402_5%
R299
33_0402_5%
1 2
R120
10K_0402_5%
R120
10K_0402_5%
12
R131
33_0402_5%
R131
33_0402_5%
1 2
C1840.01U_0402_16V7K C1840.01U_0402_16V7K 12
CLRP1
SHORT PADS
CLRP1
SHORT PADS
12
C1860.01U_0402_16V7K C1860.01U_0402_16V7K 12
R106 1K_0402_5%@R106 1K_0402_5%@12
G
D
S
Q10
BSS138_NL_SOT23-3
G
D
S
Q10
BSS138_NL_SOT23-3
2
13
R122
200_0402_5%
@
R122
200_0402_5%
@
12
R100 20K_0402_5%R100 20K_0402_5%
1 2
C190
22P_0402_50V8J
@
C190
22P_0402_50V8J
@
R294
33_0402_5%
R294
33_0402_5%
1 2
Y1
32.768KHZ_12.5PF_CM31532768DZFT
Y1
32.768KHZ_12.5PF_CM31532768DZFT
1 2
C2730.01U_0402_16V7K C2730.01U_0402_16V7K 12
CLRP3
SHORT PADS
CLRP3
SHORT PADS
12
R110
51_0402_5%
R110
51_0402_5%
12
R129
3.3K_0402_5%
R129
3.3K_0402_5%
1 2
R125
100_0402_1%
@
R125
100_0402_1%
@
12
C179
1U_0603_10V4Z
C179
1U_0603_10V4Z
1
2
R1353
1M_0402_5%
R1353
1M_0402_5%
12
R317 10K_0402_5%
@
R317 10K_0402_5%
@
12
R113
49.9_0402_1%
R113
49.9_0402_1%
1 2
R102 330K_0402_5%R102 330K_0402_5%
1 2
C191
0.1U_0402_16V4Z
C191
0.1U_0402_16V4Z
1 2
R101 1M_0402_5%R101 1M_0402_5%
1 2
R111
37.4_0402_1%
R111
37.4_0402_1%
1 2
C2720.01U_0402_16V7K C2720.01U_0402_16V7K 12
C182
1U_0603_10V4Z
C182
1U_0603_10V4Z
1
2
R119
10K_0402_5%
R119
10K_0402_5%
12
R115 750_0402_1%R115 750_0402_1%
1 2
R316 10K_0402_5%R316 10K_0402_5%
12
R104 10K_0402_5%R104 10K_0402_5%
12
R126
100_0402_1%
@
R126
100_0402_1%
@
12
R130
0_0402_5%
R130
0_0402_5%
1 2
C1870.01U_0402_16V7K C1870.01U_0402_16V7K 12
R246
3.3K_0402_5%
R246
3.3K_0402_5%
1 2
R121
200_0402_5%
@
R121
200_0402_5%
@
12
R98 10M_0402_5%R98 10M_0402_5%
1 2
R124
33_0402_5%
@
R124
33_0402_5%
@
12
R303
0_0402_5%
R303
0_0402_5%
1 2
R112
33_0402_5%
R112
33_0402_5%
1 2
R292
3.3K_0402_5%
R292
3.3K_0402_5%
1 2
R298
33_0402_5%
R298
33_0402_5%
1 2
R1418 0_0402_5%@R1418 0_0402_5%@
12
R127
3.3K_0402_5%
R127
3.3K_0402_5%
1 2
R107 1K_0402_1%@R107 1K_0402_1%@
1 2
R105 1K_0402_5%@R105 1K_0402_5%@
1 2
R99
1K_0402_5%
R99
1K_0402_5%
1 2
CLRP2
SHORT PADS
CLRP2
SHORT PADS
12
C183
1U_0603_10V4Z
C183
1U_0603_10V4Z
1
2
C181
18P_0402_50V8J
C181
18P_0402_50V8J
1
2
R133
33_0402_5%
R133
33_0402_5%
1 2
R114
33_0402_5%
R114
33_0402_5%
1 2 C275
0.1U_0402_16V4Z
C275
0.1U_0402_16V4Z
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XTAL25_IN
XTAL25_OUT
SML1DATA
XCLK_RCOMP
CLK_PCI_LPBACK
CLK_CPU_DMI#
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P1
PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2
PCIE_PTX_DRX_P2
PCIE_PTX_DRX_N1
PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1
CLK_BUF_ICH_14M
CLK_PCI_LPBACK
CLK_BUF_DREF_96M
CLK_BUF_DREF_96M#
CLK_BUF_CPU_DMI
CLK_BUF_CPU_DMI#
CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA#
PCH_GPIO26
XTAL25_OUT
XTAL25_IN
EC_SMB_CK2
EC_SMB_DA2
CLKIN_DMI2#
CLKIN_DMI2
PCH_GPIO56
PCH_HOT#
CLK_PCIE_VGA#_R CLK_PCIE_VGA#
CLK_PCIE_VGACLK_PCIE_VGA_R
PEG_CLKREQ#_R
CLK_CPU_DMI
CLK_BUF_ICH_14M
PCH_SMBCLK
PCH_SMBDATA
DRAMRST_CNTRL_PCH
SML1CLK
PCH_GPIO46
SMB_CLK_S3
SMB_DATA_S3
CLK_CPU_DMI
CLK_CPU_DMI#
WLAN_CLKREQ1#_R
CLK_PCIE_WLAN1_R
CLK_PCIE_WLAN1#_R
PCH_GPIO45
LAN_48M
PCIE_PTX_DRX_N4
PCIE_PRX_DTX_P4
PCIE_PRX_DTX_N4
PCIE_PTX_DRX_P4
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
CLKREQ_LAN#_R
PCH_GPIO20
CLK_PCIE_CARD_PCH#_R
CLK_PCIE_CARD_PCH_R
PCH_GPIO44
CPPE#_R
PCH_GPIO67
PCH_GPIO11
CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>
PCIE_PRX_DTX_N1<37>
PCIE_PTX_C_DRX_N1<37>
PCIE_PRX_DTX_P1<37>
PCIE_PTX_C_DRX_P1<37>
PCIE_PRX_DTX_N2<36>
PCIE_PRX_DTX_P2<36>
PCIE_PTX_C_DRX_N2<36>
PCIE_PTX_C_DRX_P2<36>
CLK_PCI_LPBACK <18>
DRAMRST_CNTRL_PCH <7>
EC_SMB_CK2 <23,39,42>
EC_SMB_DA2 <23,39,42>
CLK_REQ_VGA# <23>
CLK_PCIE_VGA# <23>
CLK_PCIE_VGA <23>
SMB_DATA_S3 <12,13,36>
SMB_CLK_S3 <12,13,36>
CLK_PCIE_WLAN1<36>
CLK_PCIE_WLAN1#<36>
WLAN_CLKREQ1#<36>
PCH_LAN_48M <37>
PCIE_PRX_DTX_N4<46>
PCIE_PRX_DTX_P4<46>
PCIE_PTX_C_DRX_N4<46>
PCIE_PTX_C_DRX_P4<46>
CLK_PCIE_LAN<37>
CLK_PCIE_LAN#<37>
CLKREQ_LAN#<37>
CLK_PCIE_CARD_PCH#<46>
CLK_PCIE_CARD_PCH<46>
CPPE#<46>
PCH_GPIO67 <19>
PCH_HOT# <42>
+1.05VS_VCCDIFFCLKN
+3VS
+3VS
+3VS
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3VS
+3V_PCH
+3V_PCH
+3V_PCH
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (2/8) PCIE, SMBUS, CLK
Custom
15 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (2/8) PCIE, SMBUS, CLK
Custom
15 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (2/8) PCIE, SMBUS, CLK
Custom
15 64Monday, January 16, 2012
2011/07/21 2012/12/31
WLAN
LAN
Compal Electronics, Inc.
Reserve for EMI please close to PCH
Reserve for EMI please close to PCH
DIMM1
DIMM2
MINI CARD
EC
thermal sensor
VGA
WLAN
Card Reader
LAN
Card Reader
BIOS Request SKU ID
C277 0.1U_0402_10V7KC277 0.1U_0402_10V7K
1 2
R167 10K_0402_5%R167 10K_0402_5%
1 2
C199
22P_0402_50V8J
@C199
22P_0402_50V8J
@
1 2
R335 2.2K_0402_5%R335 2.2K_0402_5%
1 2
C276 0.1U_0402_10V7KC276 0.1U_0402_10V7K
1 2
R153 0_0402_5%R153 0_0402_5%
1 2
PCI-E*
CLOCKS
FLEX CLOCKS
SMBUSController
Link
U4B
PANTHER-POINT_FCBGA989
PCI-E*
CLOCKS
FLEX CLOCKS
SMBUSController
Link
U4B
PANTHER-POINT_FCBGA989
PERN1
BG34
PERP1
BJ34
PERN2
BE34
PERP2
BF34
PERN3
BG36
PERP3
BJ36
PERN4
BF36
PERP4
BE36
PERN5
BG37
PERP5
BH37
PERN6
BJ38
PERP6
BG38
PERN7
BG40
PERP7
BJ40
PERN8
BE38
PERP8
BC38
PETN1
AV32
PETP1
AU32
PETN2
BB32
PETP2
AY32
PETN3
AV34
PETP3
AU34
PETN4
AY34
PETP4
BB34
PETN5
AY36
PETP5
BB36
PETN6
AU36
PETP6
AV36
PETN7
AY40
PETP7
BB40
PETN8
AW38
PETP8
AY38
CLKOUT_PCIE0N
Y40
CLKOUT_PCIE0P
Y39
CLKOUT_PCIE1N
AB49
CLKOUT_PCIE1P
AB47
CLKOUT_PCIE2N
AA48
CLKOUT_PCIE2P
AA47
CLKOUT_PCIE3N
Y37
CLKOUT_PCIE3P
Y36
CLKOUT_PCIE4N
Y43
CLKOUT_PCIE4P
Y45
CLKOUT_PCIE5N
V45
CLKOUT_PCIE5P
V46
CLKIN_GND1_N BJ30
CLKIN_GND1_P BG30
CLKIN_DMI_N BF18
CLKIN_DMI_P BE18
CLKIN_DOT_96N G24
CLKIN_DOT_96P E24
CLKIN_SATA_N AK7
CLKIN_SATA_P AK5
XTAL25_IN V47
XTAL25_OUT V49
REFCLK14IN K45
CLKIN_PCILOOPBACK H45
CLKOUT_PEG_A_N AB37
CLKOUT_PEG_A_P AB38
PEG_A_CLKRQ# / GPIO47 M10
PCIECLKRQ0# / GPIO73
J2
PCIECLKRQ1# / GPIO18
M1
PCIECLKRQ2# / GPIO20
V10
PCIECLKRQ3# / GPIO25
A8
PCIECLKRQ4# / GPIO26
L12
PCIECLKRQ5# / GPIO44
L14
CLKOUTFLEX0 / GPIO64 K43
CLKOUTFLEX1 / GPIO65 F47
CLKOUTFLEX2 / GPIO66 H47
CLKOUTFLEX3 / GPIO67 K49
CLKOUT_DMI_N AV22
CLKOUT_DMI_P AU22
PEG_B_CLKRQ# / GPIO56
E6
CLKOUT_PEG_B_P
AB40 CLKOUT_PEG_B_N
AB42
XCLK_RCOMP Y47
CLKOUT_DP_P AM13
CLKOUT_DP_N AM12
CLKOUT_PCIE6N
V40
CLKOUT_PCIE6P
V42
PCIECLKRQ7# / GPIO46
K12
CLKOUT_PCIE7N
V38
CLKOUT_PCIE7P
V37
CLKOUT_ITPXDP_N
AK14
CLKOUT_ITPXDP_P
AK13
SMBALERT# / GPIO11 E12
SMBCLK H14
SMBDATA C9
SML0ALERT# / GPIO60 A12
SML0CLK C8
SML0DATA G12
SML1ALERT# / PCHHOT# / GPIO74 C13
SML1CLK / GPIO58 E14
SML1DATA / GPIO75 M16
CL_CLK1 M7
CL_DATA1 T11
CL_RST1# P10
PCIECLKRQ6# / GPIO45
T13
R157 10K_0402_5%R157 10K_0402_5%
1 2
C192 0.1U_0402_10V7KC192 0.1U_0402_10V7K
1 2
C198
22P_0402_50V8J
@C198
22P_0402_50V8J
@
1 2
R176
33_0402_5%
@R176
33_0402_5%
@
12
R154 0_0402_5%R154 0_0402_5%
1 2
R158 10K_0402_5%R158 10K_0402_5%
12
R155 10K_0402_5%R155 10K_0402_5%
1 2
R137
2.2K_0402_5%
R137
2.2K_0402_5%
1 2
R165 10K_0402_5%R165 10K_0402_5%
12
R151 0_0402_5%R151 0_0402_5%
1 2
R136
2.2K_0402_5%
R136
2.2K_0402_5%
1 2
R156 0_0402_5%R156 0_0402_5%
1 2
R171
90.9_0402_1%
R171
90.9_0402_1%
1 2
C197
27P_0402_50V8J
C197
27P_0402_50V8J
1
2
R312 0_0402_5%R312 0_0402_5%
1 2
R152 10K_0402_5%R152 10K_0402_5%
12
R329
1K_0402_5%
R329
1K_0402_5%
12
R148 0_0402_5%R148 0_0402_5%
1 2
Q61B
DMN66D0LDW-7 2N_SOT363-6
Q61B
DMN66D0LDW-7 2N_SOT363-6
3
5
4
R349 10K_0402_5%@R349 10K_0402_5%@
1 2
R311 0_0402_5%R311 0_0402_5%
1 2
R144
0_0402_5%
R144
0_0402_5%
1 2
R160 10K_0402_5%R160 10K_0402_5%
1 2
R347 10K_0402_5%
@
R347 10K_0402_5%
@
1 2
R138
2.2K_0402_5%R138
2.2K_0402_5%
1 2
R142
2.2K_0402_5%
R142
2.2K_0402_5%
1 2
R172 10K_0402_5%R172 10K_0402_5%
12
R147 10K_0402_5%R147 10K_0402_5%
12
R342 0_0402_5%@R342 0_0402_5%@
1 2
R162 10K_0402_5%R162 10K_0402_5%
1 2
Q61A
DMN66D0LDW-7 2N_SOT363-6
Q61A
DMN66D0LDW-7 2N_SOT363-6
6 1
2
R134
10K_0402_5%
R134
10K_0402_5%
12
C196
27P_0402_50V8J
C196
27P_0402_50V8J
1
2
R149 0_0402_5%R149 0_0402_5%
1 2
R170 10K_0402_5%R170 10K_0402_5%
12
R175
33_0402_5%
@R175
33_0402_5%
@
12
R168 10K_0402_5%R168 10K_0402_5%
12
R140 10K_0402_5%R140 10K_0402_5%
12
Y2
25MHZ_12PF_X3G025000DC1H~D
Y2
25MHZ_12PF_X3G025000DC1H~D
NC
4
OSC
1
OSC 3
NC 2
R159 10K_0402_5%R159 10K_0402_5%
1 2
R301 10K_0402_5%R301 10K_0402_5%
12
R143
10K_0402_5%
R143
10K_0402_5%
1 2
R141
2.2K_0402_5%
R141
2.2K_0402_5%
1 2
C195 0.1U_0402_10V7KC195 0.1U_0402_10V7K
1 2
C194 0.1U_0402_10V7KC194 0.1U_0402_10V7K
1 2
R135
2.2K_0402_5%
R135
2.2K_0402_5%
1 2
Q60A
DMN66D0LDW-7 2N_SOT363-6
Q60A
DMN66D0LDW-7 2N_SOT363-6
6 1
2
R169 1M_0402_5%R169 1M_0402_5%
1 2
C193 0.1U_0402_10V7KC193 0.1U_0402_10V7K
1 2
R182 22_0402_5%@R182 22_0402_5%@
1 2
R163 10K_0402_5%R163 10K_0402_5%
1 2
R174 10K_0402_5%R174 10K_0402_5%
12
R166 10K_0402_5%R166 10K_0402_5%
1 2
R150 0_0402_5%R150 0_0402_5%
1 2
R164 10K_0402_5%R164 10K_0402_5%
1 2
R146 0_0402_5%R146 0_0402_5%
1 2
R336 2.2K_0402_5%R336 2.2K_0402_5%
1 2
Q60B
DMN66D0LDW-7 2N_SOT363-6
Q60B
DMN66D0LDW-7 2N_SOT363-6
3
5
4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DMI_IRCOMP
DMI_CRX_PTX_N1
DMI_CRX_PTX_P0
DMI_CRX_PTX_P3
DMI_CTX_PRX_P0
DMI_CRX_PTX_N2
DMI_CRX_PTX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_P2
DMI_CTX_PRX_N1
DMI_CRX_PTX_N0
DMI_CTX_PRX_N0
DMI_CTX_PRX_P1
DMI_CRX_PTX_N3
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC1
FDI_LSYNC0
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_CTX_PRX_P5
PCH_GPIO72
RI#
RBIAS_CPY
APWROK
PM_DRAM_PWRGD
PCH_RSMRST#_R
PBTN_OUT#_R
DSWODVREN
WAKE#
PCH_RSMRST#_RPCH_DPWROK_R
PM_SLP_S5#
PM_SLP_S4#
SUS_STAT#
H_PM_SYNC
SUSCLK
PWROK
SYS_RST#
SUSWARN#
PCH_RSMRST#_R
PM_DRAM_PWRGD
SYS_PWROK
VGATE
PCH_PWROK
PM_SLP_S3#
PM_CLKRUN#
AC_PRESENT_R
PM_DRAM_PWRGD
PCH_GPIO29
PM_SLP_SUS
PM_SLP_SUS#
PM_SLP_SUS#_R
SUSWARN#_R
SUSACK#_R
AC_PRESENT_R
SUSWARN#
DMI_CTX_PRX_N0<5>
DMI_CRX_PTX_N2<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N3<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P3<5>
DMI_CTX_PRX_P2<5>
DMI_CRX_PTX_N3<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P0<5>
FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>
FDI_CTX_PRX_P0 <5>
FDI_CTX_PRX_P1 <5>
FDI_CTX_PRX_P2 <5>
FDI_CTX_PRX_P3 <5>
FDI_CTX_PRX_P4 <5>
FDI_CTX_PRX_P5 <5>
FDI_CTX_PRX_P6 <5>
FDI_CTX_PRX_P7 <5>
FDI_FSYNC1 <5>
FDI_LSYNC0 <5>
FDI_FSYNC0 <5>
FDI_INT <5>
FDI_LSYNC1 <5>
PM_DRAM_PWRGD<6>
PBTN_OUT#<42>
PCIE_WAKE# <19,36,37>
H_PM_SYNC <6>
PM_SLP_S3# <42>
PM_SLP_S4# <42>
PM_SLP_S5# <42>
VGATE<57>
EC_RSMRST#<42>
SUSCLK <42>
ACIN<42,51>
PCH_APWROK<42>
PCH_PWROK<42>
SYS_PWROK <6>
PM_SLP_SUS# <42>
PM_SLP_SUS<48>
SUSWARN#<42>
SUSACK#<42>
+1.05VS_VCC_EXP
+3VS
+3VS
+3VS
+RTCVCC
+3VS
+3V_PCH
+3V_PCH
+3V_PCH
+5VALW
+3V_DSW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (3/8) DMI,FDI,PM,
Custom
16 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (3/8) DMI,FDI,PM,
Custom
16 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (3/8) DMI,FDI,PM,
Custom
16 64Monday, January 16, 2012
2011/07/21 2012/12/31
4mil width and place
within 500mil of the PCH
Can be left NC
when IAMT is not
support on the
platfrom
Compal Electronics, Inc.
AEPWROK can be connect to
PWROK if iAMT disable
Can be left NC if no use
integrated LAN.
*
DSWODVREN - On Die DSW VR Enable
HEnable
LDisable
7/28 Modify follow Module Design.
10/06 Test point request
09/05 add for Deep S3
For Deep S3
For Deep S3
For Deep S3
For Deep S3
11/08 Resreve for Deep S3
12/23 change to 300Ohm for S5 power saving
R197 10K_0402_5%R197 10K_0402_5%
12
G
D
S
Q118
2N7002_SOT23
DS3@
G
D
S
Q118
2N7002_SOT23
DS3@
2
13
R184 10K_0402_5%R184 10K_0402_5%
12
R180
100K_0402_1%
@
R180
100K_0402_1%
@
12
R1120
100K_0402_5%
DS3@
R1120
100K_0402_5%
DS3@
12
R183
330K_0402_5%
@
R183
330K_0402_5%
@
12
D29 RB751V_SOD323D29 RB751V_SOD323
21
R253 10K_0402_5%R253 10K_0402_5%
1 2
R192 300_0402_5%R192 300_0402_5%
12
T74PAD T74PAD
T73PAD T73PAD
R178 750_0402_1%R178 750_0402_1%
1 2
R181
0_0402_5%
R181
0_0402_5%
1 2
R1121
100K_0402_5%
@R1121
100K_0402_5%
@
12
R302 0_0402_5%
@
R302 0_0402_5%
@
1 2
R186
10K_0402_5%
R186
10K_0402_5%
1 2
R177 49.9_0402_1%R177 49.9_0402_1%
1 2
R201
10K_0402_5%
R201
10K_0402_5%
12
R1455 0_0402_5%
DS3@
R1455 0_0402_5%
DS3@
12
U6
MC74VHC1G08DFT2G SC70 5P
U6
MC74VHC1G08DFT2G SC70 5P
B
2
A
1
Y4
P
5G3
R194 10K_0402_5%R194 10K_0402_5%
12
R193 0_0402_5%R193 0_0402_5%
1 2
R190 0_0402_5%R190 0_0402_5%
1 2
R185
0_0402_5%
R185
0_0402_5%
1 2
R189 8.2K_0402_5%@R189 8.2K_0402_5%@
1 2
R191 0_0402_5%R191 0_0402_5%
12
R198 0_0402_5%R198 0_0402_5%
1 2
R1290 200_0402_5%
@
R1290 200_0402_5%
@
12
R188 0_0402_5%@R188 0_0402_5%@
1 2
R1457 0_0402_5%
DS3@
R1457 0_0402_5%
DS3@
12
DMI
FDI
System Power Management
U4C
PANTHER-POINT_FCBGA989
DMI
FDI
System Power Management
U4C
PANTHER-POINT_FCBGA989
DMI0RXN
BC24
DMI1RXN
BE20
DMI2RXN
BG18
DMI3RXN
BG20
DMI0RXP
BE24
DMI1RXP
BC20
DMI2RXP
BJ18
DMI3RXP
BJ20
DMI0TXN
AW24
DMI1TXN
AW20
DMI2TXN
BB18
DMI3TXN
AV18
DMI0TXP
AY24
DMI1TXP
AY20
DMI2TXP
AY18
DMI3TXP
AU18
DMI_ZCOMP
BJ24
DMI_IRCOMP
BG25
FDI_RXN0 BJ14
FDI_RXN1 AY14
FDI_RXN2 BE14
FDI_RXN3 BH13
FDI_RXN4 BC12
FDI_RXN5 BJ12
FDI_RXN6 BG10
FDI_RXN7 BG9
FDI_RXP0 BG14
FDI_RXP1 BB14
FDI_RXP2 BF14
FDI_RXP3 BG13
FDI_RXP4 BE12
FDI_RXP5 BG12
FDI_RXP6 BJ10
FDI_RXP7 BH9
FDI_FSYNC0 AV12
FDI_FSYNC1 BC10
FDI_LSYNC0 AV14
FDI_LSYNC1 BB10
FDI_INT AW16
PMSYNCH AP14
SLP_SUS# G16
SLP_S3# F4
SLP_S4# H4
SLP_S5# / GPIO63 D10
SYS_RESET#
K3
SYS_PWROK
P12
PWRBTN#
E20
RI#
A10
WAKE# B9
SUS_STAT# / GPIO61 G8
SUSCLK / GPIO62 N14
ACPRESENT / GPIO31
H20
BATLOW# / GPIO72
E10
PWROK
L22
CLKRUN# / GPIO32 N3
SUSWARN#/SUSPWRDNACK/GPIO30
K16
RSMRST#
C21
DRAMPWROK
B13
SLP_LAN# / GPIO29 K14
APWROK
L10
DPWROK E22
DMI2RBIAS
BH21
SLP_A# G10
DSWVRMEN A18
SUSACK#
C12
R257 10K_0402_5%
@
R257 10K_0402_5%
@
12
R179
330K_0402_5%
R179
330K_0402_5%
12
R195 200K_0402_5%R195 200K_0402_5%
12
R200
8.2K_0402_5%
R200
8.2K_0402_5%
1 2
R1447 0_0402_5%
DS3@
R1447 0_0402_5%
DS3@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CRT_IREF
CTRL_CLK
CTRL_DATA
LVDS_IBG
LVD_VREF
PCH_ENBKL
PCH_ENVDD
EDID_DATA
EDID_CLK
DAC_BLU
DAC_GRN
DAC_RED
CRT_DDC_DATA
CRT_DDC_CLK
HDMIDAT
HDMICLK
TMDS_B_CLK#_PCH
TMDS_B_DATA2_PCH
TMDS_B_DATA1#_PCH
TMDS_B_DATA0#_PCH
TMDS_B_DATA2#_PCH
TMDS_B_DATA1_PCH
TMDS_B_DATA0_PCH
TMDS_B_CLK_PCH
PCH_ENBKL<33>
PCH_ENVDD<33>
PCH_PWM<33>
EDID_DATA<33>
EDID_CLK<33>
LVDS_ACLK#<33>
LVDS_ACLK<33>
LVDS_A0#<33>
LVDS_A1#<33>
LVDS_A2#<33>
LVDS_A0<33>
LVDS_A1<33>
LVDS_A2<33>
CRT_HSYNC<34>
CRT_VSYNC<34>
CRT_DDC_CLK<34>
CRT_DDC_DATA<34>
DAC_BLU<34>
DAC_GRN<34>
DAC_RED<34>
HDMIDAT <35>
HDMICLK <35>
HDMI_TX2-_CK <35>
HDMI_TX2+_CK <35>
HDMI_TX1-_CK <35>
HDMI_TX1+_CK <35>
HDMI_TX0-_CK <35>
HDMI_TX0+_CK <35>
HDMI_CLK-_CK <35>
HDMI_CLK+_CK <35>
TMDS_B_HPD <35>
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (4/9) LVDS,CRT,DP,HDMI
Custom
17 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (4/9) LVDS,CRT,DP,HDMI
Custom
17 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (4/9) LVDS,CRT,DP,HDMI
Custom
17 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
HDMI
Colse connector
Pull up R for CONN SIDE
Pull up R for CONN SIDE
C207 0.1U_0402_10V6KHDMI@ C207 0.1U_0402_10V6KHDMI@ 1 2
R211
1K_0402_1%
R211
1K_0402_1%
12
R203
2.2K_0402_5%
HDMI@
R203
2.2K_0402_5%
HDMI@
12
R210 150_0402_1%R210 150_0402_1%
12
C204 0.1U_0402_10V6KHDMI@ C204 0.1U_0402_10V6KHDMI@ 1 2
C202 0.1U_0402_10V6KHDMI@ C202 0.1U_0402_10V6KHDMI@ 1 2
C200 0.1U_0402_10V6KHDMI@ C200 0.1U_0402_10V6KHDMI@ 1 2
C205 0.1U_0402_10V6KHDMI@ C205 0.1U_0402_10V6KHDMI@ 1 2
R209 150_0402_1%R209 150_0402_1%
12
LVDS
Digital Display Interface
CRT
U4D
PANTHER-POINT_FCBGA989
LVDS
Digital Display Interface
CRT
U4D
PANTHER-POINT_FCBGA989
L_BKLTCTL
P45
L_BKLTEN
J47
L_CTRL_CLK
T45
L_CTRL_DATA
P39
L_DDC_CLK
T40
L_DDC_DATA
K47
L_VDD_EN
M45
LVDSA_CLK#
AK39
LVDSA_CLK
AK40
LVDSA_DATA#0
AN48
LVDSA_DATA#1
AM47
LVDSA_DATA#2
AK47
LVDSA_DATA#3
AJ48
LVDSA_DATA0
AN47
LVDSA_DATA1
AM49
LVDSA_DATA2
AK49
LVDSA_DATA3
AJ47
LVDSB_CLK#
AF40
LVDSB_CLK
AF39
LVDSB_DATA#0
AH45
LVDSB_DATA#1
AH47
LVDSB_DATA#2
AF49
LVDSB_DATA#3
AF45
LVDSB_DATA0
AH43
DDPB_0N AV42
DDPB_1N AV45
LVD_VREFH
AE48
LVD_VREFL
AE47
DDPD_2N BF42
DDPD_3N BJ42
DDPB_2N AU48
DDPB_3N AV47
DDPC_0N AY47
DDPC_1N AY43
DDPC_2N BA47
DDPC_3N BB47
DDPD_0N BB43
DDPD_1N BF44
DDPB_0P AV40
DDPB_1P AV46
DDPD_2P BE42
DDPD_3P BG42
DDPB_2P AU47
DDPB_3P AV49
LVDSB_DATA1
AH49
LVDSB_DATA2
AF47
LVDSB_DATA3
AF43
LVD_IBG
AF37
LVD_VBG
AF36
DDPC_1P AY45
DDPC_0P AY49
DDPC_2P BA48
DDPC_3P BB49
DDPD_0P BB45
DDPD_1P BE44
CRT_BLUE
N48
CRT_DDC_CLK
T39
CRT_DDC_DATA
M40
CRT_GREEN
P49
CRT_HSYNC
M47
CRT_IRTN
T42
CRT_RED
T49
CRT_VSYNC
M49
DAC_IREF
T43
SDVO_CTRLCLK P38
SDVO_CTRLDATA M39
DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
DDPD_CTRLCLK M43
DDPD_CTRLDATA M36
DDPB_AUXN AT49
DDPC_AUXN AP47
DDPD_AUXN AT45
DDPB_AUXP AT47
DDPC_AUXP AP49
DDPD_AUXP AT43
DDPB_HPD AT40
DDPC_HPD AT38
DDPD_HPD BH41
SDVO_TVCLKINP AP45
SDVO_TVCLKINN AP43
SDVO_STALLP AM40
SDVO_STALLN AM42
SDVO_INTP AP40
SDVO_INTN AP39
R206
2.37K_0402_1%
R206
2.37K_0402_1%
12
C203 0.1U_0402_10V6KHDMI@ C203 0.1U_0402_10V6KHDMI@ 1 2
R204 2.2K_0402_5%R204 2.2K_0402_5%
1 2
R202
2.2K_0402_5%
HDMI@
R202
2.2K_0402_5%
HDMI@
12
R205 2.2K_0402_5%R205 2.2K_0402_5%
1 2
C206 0.1U_0402_10V6KHDMI@ C206 0.1U_0402_10V6KHDMI@ 1 2
R208 150_0402_1%R208 150_0402_1%
12
C201 0.1U_0402_10V6KHDMI@ C201 0.1U_0402_10V6KHDMI@ 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_PLTRST#
PCH_WL_OFF#
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
PCH_GPIO4
DGPU_PWR_EN1
USB_OC7#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC3#
USB_OC1#
USB_OC0#
USB_OC2#
DGPU_GC6_EN
PCH_GPIO2
USB_OC7#
USB_OC2#PCH_GPIO51
PCH_WL_OFF#
PCH_PLTRST#
USBRBIAS
PCH_GPIO51
CLK_PCI_LPBACK_R
CLK_PCI_EC_R
PCH_GPIO5
DGPU_HOLD_RST#_R
DGPU_HOLD_RST#_R
ODD_DA# ODD_DA#_R
USB20_N3
USB20_P3
USB20_N2
USB20_P2
DGPU_PWR_EN_R
USB20_N5
USB20_P5
USB20_N0
USB20_P0
USB20_N9
USB20_P9
USB20_N13
USB20_P13
USB30_RX_N1
USB30_RX_P1
USB30_TX_N1
USB30_TX_P1
USB30_RX_N3
USB30_RX_N4
USB30_RX_P3
USB30_RX_P4
USB30_TX_N3
USB30_TX_N4
USB30_TX_P3
USB30_TX_P4
USB20_P10
USB20_N10
CLK_PCI_DB_R
PCH_WL_OFF#
DGPU_PWR_EN1
PCH_GPIO5
DGPU_HOLD_RST#_R
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQA#
PCI_PIRQB#
PCH_GPIO4
PCH_GPIO2
DGPU_PWR_EN_R
ODD_DA#_R
DGPU_GC6_EN
PCH_GPIO51
NVDD_PWR_ENDGPU_PWR_EN_R
DGPU_GC6_EN
USB_OC4#
USB_OC3#
USB_OC1#
USB_OC6#
USB_OC5#
USB_OC0#
USB_OC0# <46>
PCI_PME#<42>
PLT_RST#<23,36,37,42,46>
CLK_PCI_EC<42>
CLK_PCI_LPBACK<15>
PCH_PLTRST#<6>
USB_OC1# <45>
PCH_WL_OFF#<36>
ODD_DA#<40,42>
USB20_P3 <45>
USB20_N3 <45>
USB20_N2 <45>
USB20_P2 <45>
DGPU_HOLD_RST#<23>
USB20_N5 <33>
USB20_P5 <33>
USB20_N0 <46>
USB20_P0 <46>
USB20_N9 <46>
USB20_P9 <46>
USB20_P13 <44>
USB20_N13 <44>
USB30_RX_N1<46>
USB30_RX_P1<46>
USB30_TX_N1<46>
USB30_TX_P1<46>
USB30_RX_N3<45>
USB30_RX_N4<45>
USB30_RX_P3<45>
USB30_RX_P4<45>
USB30_TX_N3<45>
USB30_TX_N4<45>
USB30_TX_P3<45>
USB30_TX_P4<45>
USB20_N10 <36>
USB20_P10 <36>
USB_OC4# <46>
DGPU_PWR_EN<23,48>
NVDD_PWR_EN<56>
CLK_PCI_DB<36>
DGPU_GC6_EN<27>
+3VS
+3VS
+3V_PCH
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (5/9) PCI, USB
Custom
18 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (5/9) PCI, USB
Custom
18 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (5/9) PCI, USB
Custom
18 64Monday, January 16, 2012
2011/07/21 2012/12/31
*
override/Top-Block
Low=A16 swap
PCI_GNT3#
A16 swap overide Strap/Top-Block
Swap Override jumper
Swap Override enabled
High=Default
Within 500 mils
Compal Electronics, Inc.
*
SPI
0
1
Reserved
0
Boot BIOS Strap bit1 BBS1
Bit11
LPC
Boot BIOS
Destination
GNT1#/
GPIO51
(Default)
Reserved
1
0
Bit10
01
1
USB DEBUG=PORT1 AND PORT9
GPIO53=This Signal has a weak internal pull-up.
NOTE: The internal pull-up is disabled after
PLTRST# deasserts.
WLAN
LEFT USB
Bluetooth
RIGHT USB (SUB/B)
LEFT USB
USB Camera
Some PCH config not support USB port 6 & 7.
RIGHT USB (Cable)
USB30
PORT1
PORT2
PORT3
PORT4
RIGHT USB (SUB/B)
LEFT USB
LEFT USB
PPT EDS DOC#474146
7/9 Reserve
RSVD
PCI
USB
U4E
PANTHER-POINT_FCBGA989
RSVD
PCI
USB
U4E
PANTHER-POINT_FCBGA989
RSVD23 AV5
RSVD1 AY7
RSVD2 AV7
RSVD3 AU3
RSVD4 BG4
RSVD5 AT10
RSVD6 BC8
RSVD7 AU2
RSVD8 AT4
RSVD17 BB5
RSVD18 BB3
RSVD19 BB7
RSVD20 BE8
RSVD21 BD4
RSVD22 BF6
RSVD9 AT3
RSVD10 AT1
RSVD11 AY3
RSVD12 AT5
RSVD13 AV3
RSVD14 AV1
RSVD15 BB1
RSVD16 BA3
RSVD25 AT8
RSVD24 AV10
RSVD26 AY5
RSVD27 BA2
RSVD28 AT12
RSVD29 BF3
PIRQA#
K40
PIRQB#
K38
PIRQC#
H38
PIRQD#
G38
REQ1# / GPIO50
C46
REQ2# / GPIO52
C44
REQ3# / GPIO54
E40
GNT1# / GPIO51
D47
GNT2# / GPIO53
E42
GNT3# / GPIO55
F46
PIRQE# / GPIO2
G42
PIRQF# / GPIO3
G40
PIRQG# / GPIO4
C42
PIRQH# / GPIO5
D44
USBP0N C24
USBP0P A24
USBP1N C25
USBP1P B25
USBP2N C26
USBP2P A26
USBP3N K28
USBP3P H28
USBP4N E28
USBP4P D28
USBP5N C28
USBP5P A28
USBP6N C29
USBP6P B29
USBP7N N28
USBP7P M28
USBP8N L30
USBP8P K30
USBP9N G30
USBP9P E30
USBP10N C30
USBP10P A30
USBP11N L32
USBP11P K32
USBP12N G32
USBP12P E32
USBP13N C32
USBP13P A32
PME#
K10
CLKOUT_PCI0
H49
CLKOUT_PCI1
H43
CLKOUT_PCI2
J48
USBRBIAS# C33
USBRBIAS B33
OC0# / GPIO59 A14
OC1# / GPIO40 K20
OC2# / GPIO41 B17
OC3# / GPIO42 C16
OC4# / GPIO43 L16
OC5# / GPIO9 A16
OC6# / GPIO10 D14
OC7# / GPIO14 C14
CLKOUT_PCI4
H40 CLKOUT_PCI3
K42
PLTRST#
C6
TP1
BG26
TP2
BJ26
TP3
BH25
TP6
AH38
TP7
AH37
TP8
AK43
TP9
AK45
TP16
Y13
TP17
K24
TP18
L24
TP19
AB46
TP20
AB45
TP21
B21
TP22
M20
TP23
AY16
USB3Rn1
BE28
USB3Rn2
BC30
USB3Rn3
BE32
USB3Rn4
BJ32
USB3Rp1
BC28
USB3Rp2
BE30
USB3Rp3
BF32
USB3Rp4
BG32
USB3Tn1
AV26
USB3Tn2
BB26
USB3Tn3
AU28
USB3Tn4
AY30
USB3Tp1
AU26
USB3Tp2
AY26
USB3Tp3
AV28
USB3Tp4
AW30
TP4
BJ16
TP5
BG16
TP15
AM5 TP14
AM4 TP13
AH12 TP12
H3 TP11
N30 TP10
C18
TP24
BG46
R306 8.2K_0402_5%
@
R306 8.2K_0402_5%
@
1 2
R22022_0402_5% R22022_0402_5% 1 2
RP1
8.2K_0804_8P4R_5%
RP1
8.2K_0804_8P4R_5%
18
27
36
45
R314
0_0402_5%
R314
0_0402_5%
1 2
R221 1K_0402_5%@R221 1K_0402_5%@
1 2
R17322_0402_5%
@
R17322_0402_5%
@
12
R223
100K_0402_5%
R223
100K_0402_5%
12
R21922_0402_5% R21922_0402_5% 1 2
R252 8.2K_0402_5%R252 8.2K_0402_5%
1 2
R7150_0402_5%
@
R7150_0402_5%
@
1 2
RP3
10K_1206_8P4R_5%
RP3
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R319 0_0402_5%
@
R319 0_0402_5%
@
1 2
R305 8.2K_0402_5%
@
R305 8.2K_0402_5%
@
1 2
C208
1U_0402_6.3V6K
@
C208
1U_0402_6.3V6K
@1
2
R215 1K_0402_5%@R215 1K_0402_5%@
1 2
R222 0_0402_5%R222 0_0402_5%
1 2
RP2
8.2K_0804_8P4R_5%
RP2
8.2K_0804_8P4R_5%
18
27
36
45
R213 8.2K_0402_5%R213 8.2K_0402_5%
1 2
U7
MC74VHC1G08DFT2G SC70 5P
@
U7
MC74VHC1G08DFT2G SC70 5P
@
B2
A1
Y
4
P
5G3
R212 8.2K_0402_5%R212 8.2K_0402_5%
1 2
R218 22.6_0402_1%R218 22.6_0402_1%
1 2
R225 8.2K_0402_5%R225 8.2K_0402_5%
1 2
RP4
10K_1206_8P4R_5%
RP4
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5
R297 8.2K_0402_5%
@
R297 8.2K_0402_5%
@
1 2
R214 8.2K_0402_5%
@
R214 8.2K_0402_5%
@
1 2
R318 0_0402_5%R318 0_0402_5%
1 2
R315
0_0402_5%
R315
0_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_GPIO28
AOAC_WAKE#
EC_SMI#
PCH_GPIO36
PCH_THRMTRIP#_R
PCH_GPIO49
PCH_BT_ON#
PCH_GPIO36
ODD_EN
PCH_GPIO6
DGPU_PWROK_R
PCH_GPIO1
EC_LID_OUT#
PCH_GPIO12
BT_DISABLE
PCH_GPIO38
AOAC_WAKE#
PCH_GPIO48
PCH_GPIO16
EC_SCI#
PCH_GPIO28
PCH_PECI_R
EC_SMI#
KBRST#
H_THRMTRIP#
PCH_GPIO35
PCH_GPIO39
PCH_GPIO68
PCH_GPIO70
KBRST#
PCH_GPIO57
PCH_GPIO67
PCH_GPIO38
GC6_EVENT#
NV_CLE
NV_CLE
PCH_GPIO70
PCH_GPIO68
PCH_GPIO37
PCH_GPIO37
PCH_GPIO69
PCH_GPIO69
GATEA20 <42>
EC_SCI#<42>
H_PECI <6,42>
H_CPUPWRGD <6>
KBRST# <42>
ODD_EN<40>
H_THRMTRIP# <6>
EC_SMI#<42>
PCH_BT_ON#<36,44>
DGPU_PWROK<27,53,56>
PCH_THRMTRIP#_R <23>
BT_DISABLE<36>
PCH_GPIO67<15>
GC6_EVENT#<23>
H_SNB_IVB# <6>
EC_LID_OUT#<42>
PCIE_WAKE#<16,36,37>
+3VS
+3VS
+3V_PCH
+3VS
+3VS
+3VS
+3VS
+3V_PCH
+3VS
+3VS
+3VS
+3VS
+3V_PCH
+1.8VS
+3VS
+3VS
+3V_PCH
+3V_DSW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (6/9) GPIO, CPU, MISC
Custom
19 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (6/9) GPIO, CPU, MISC
Custom
19 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (6/9) GPIO, CPU, MISC
Custom
19 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
*
This signal has a weak internal pull up
On-Die PLL Voltage Regulator
LOn-Die PLL Voltage Regulator disable
GPIO28
HOn-Die voltage regulator enable
*
PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
Low: VCCVRM VR Disable
INIT3_3V
This signal has weak internal
PU, can't pull low
Intel schematic reviwe recommand.
MB ID
H : Sandy Bridge
PROC_SEL L : INV Bridge
CLOSE TO THE BRANCHING POINT
PCH_GPIO38Function
SG
Reserve
DIS
UMA
PCH_GPIO67 PCH_GPIO70
00
01
10
11
14"
15"
0
1
X
X
X
X
X
X
X
X
PCH_GPIO69
14"L
XX
XXReserve
0
01
0
11
X
X
X
X
9/18 Reseve for SKU ID
R255 10K_0402_5%R255 10K_0402_5%
1 2
R240 1K_0402_5%@R240 1K_0402_5%@
1 2
R236
10K_0402_5%
R236
10K_0402_5%
1 2
R227 10K_0402_5%R227 10K_0402_5%
1 2
R247 10K_0402_5%R247 10K_0402_5%
1 2
R264 10K_0402_5%
@
R264 10K_0402_5%
@
1 2
R250 200_0402_5%R250 200_0402_5%
1 2
R242
10K_0402_5%
R242
10K_0402_5%
1 2
R245 10K_0402_5%@R245 10K_0402_5%@
1 2
R232 10K_0402_1%
@
R232 10K_0402_1%
@
1 2
R207 10K_0402_5%
AOAC@
R207 10K_0402_5%
AOAC@
12
R711
10K_0402_5%
@
R711
10K_0402_5%
@
1 2
R216
2.2K_0402_5%
R216
2.2K_0402_5%
R235 1K_0402_5%
@
R235 1K_0402_5%
@
1 2
R703
10K_0402_5%
@
R703
10K_0402_5%
@
1 2
R231 10K_0402_5%R231 10K_0402_5%
1 2
R712
10K_0402_5%
R712
10K_0402_5%
1 2
R226 10K_0402_5%R226 10K_0402_5%
1 2
R2240_0402_5%
AOAC@
R2240_0402_5%
AOAC@
12
R230 10K_0402_5%R230 10K_0402_5%
1 2
R217 1K_0402_5%R217 1K_0402_5%
1 2
R239 390_0402_5%R239 390_0402_5%
1 2
R708
10K_0402_5%
@
R708
10K_0402_5%
@
1 2
R706
10K_0402_5%
R706
10K_0402_5%
1 2
R238 10K_0402_5%R238 10K_0402_5%
1 2
R280 10K_0402_5%R280 10K_0402_5%
1 2
R709
10K_0402_5%
R709
10K_0402_5%
1 2
R243 10K_0402_5%R243 10K_0402_5%
1 2
R704
10K_0402_5%
@
R704
10K_0402_5%
@
1 2
R248 10K_0402_5%R248 10K_0402_5%
1 2
R3390_0402_5% R3390_0402_5%
1 2
R233 10K_0402_5%R233 10K_0402_5%
1 2
R228 10K_0402_5%R228 10K_0402_5%
1 2
R2370_0402_5%
@
R2370_0402_5%
@
1 2
R241 10K_0402_5% R241 10K_0402_5%
1 2
R259 10K_0402_5%R259 10K_0402_5%
1 2
R705
10K_0402_5%
R705
10K_0402_5%
1 2
R251 10K_0402_5%R251 10K_0402_5%
1 2
R244 10K_0402_5%@R244 10K_0402_5%@
1 2
R249 10K_0402_5%R249 10K_0402_5%
1 2
R229 10K_0402_5%@R229 10K_0402_5%@
1 2
CPU/MISC
NCTF
GPIO
U4F
PANTHER-POINT_FCBGA989
CPU/MISC
NCTF
GPIO
U4F
PANTHER-POINT_FCBGA989
GPIO27
E16
GPIO28
P8
GPIO24
E8
GPIO57
D6
LAN_PHY_PWR_CTRL / GPIO12
C4
VSS_NCTF_1
A4
VSS_NCTF_2
A44
VSS_NCTF_3
A45
VSS_NCTF_4
A46
VSS_NCTF_5
A5
VSS_NCTF_6
A6
VSS_NCTF_7
B3
VSS_NCTF_8
B47
VSS_NCTF_9
BD1
VSS_NCTF_10
BD49
VSS_NCTF_11
BE1
VSS_NCTF_12
BE49
TACH2 / GPIO6
H36
TACH0 / GPIO17
D40
TACH3 / GPIO7
E38
SATA3GP / GPIO37
M5
SATA5GP / GPIO49 / TEMP_ALERT#
V3
SCLOCK / GPIO22
T5
SLOAD / GPIO38
N2
SDATAOUT0 / GPIO39
M3
SDATAOUT1 / GPIO48
V13
PROCPWRGD AY11
RCIN# P5
PECI AU16
THRMTRIP# AY10
GPIO8
C10
BMBUSY# / GPIO0
T7
GPIO15
G2
TACH1 / GPIO1
A42
SATA2GP / GPIO36
V8
INIT3_3V# T14
STP_PCI# / GPIO34
K1
GPIO35
K4
SATA4GP / GPIO16
U2
VSS_NCTF_32 F49
A20GATE P4
TACH4 / GPIO68 C40
TACH6 / GPIO70 C41
TACH7 / GPIO71 A40
TACH5 / GPIO69 B41
VSS_NCTF_17 BH3
VSS_NCTF_18 BH47
VSS_NCTF_19 BJ4
VSS_NCTF_20 BJ44
VSS_NCTF_21 BJ45
VSS_NCTF_22 BJ46
VSS_NCTF_23 BJ5
VSS_NCTF_24 BJ6
VSS_NCTF_25 C2
VSS_NCTF_26 C48
VSS_NCTF_27 D1
VSS_NCTF_28 D49
VSS_NCTF_29 E1
VSS_NCTF_30 E49
VSS_NCTF_31 F1
TS_VSS4 AK10
TS_VSS3 AH10
TS_VSS2 AK11
TS_VSS1 AH8
NC_1 P37
VSS_NCTF_13
BF1
VSS_NCTF_14
BF49
VSS_NCTF_15 BG2
VSS_NCTF_16 BG48
DF_TVS AY1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCCAFDI_VRM
+1.05VS_VCCCORE
+VCCAPLLEXP
+1.05VS_VCC_EXP
+VCCAFDI_VRM
+VCCADAC
+VCCAFDI_VRM
+3VS_VCC3_3_6
+3V_VCCPSPI
+1.05VS_VCCDPLLEXP
+3VS_VCCA3GBG
+VCCP_VCCDMI
+1.05VS_VCC_DMI_CCI
+VCCA_LVDS
+VCCTX_LVDS
+1.05VS_VCCDPLL_FDI
+1.05VS_VCCAPLL_FDI
+1.5VS
+VCCAFDI_VRM
+VCCP_VCCDMI
+1.05VS
+1.05VS
+3VS
+1.05VS
+3VS
+3VS
+VCCP_VCCDMI
+3VS
+1.05VS
+1.8VS+VCCPNAND
+1.8VS
+1.05VS
+1.05VS
+3VS
+1.05VS_VCC_EXP
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (7/9) PWR
Custom
20 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (7/9) PWR
Custom
20 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (7/9) PWR
Custom
20 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
63mA
1700mA
3711mA
10mA
190mA
VCCVRM = 160mA detal waiting for newest spec
70mA
1mA
40mA
VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP
Intel recommand
stuff R265 and unstuff R266
This pin can be left as no connect in
On-Die VR enabled mode (default).
0.1uH inductor, 200mA
3.3
1.05
1.05
1.05
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC
VccADPLLA
VccADPLLB
Voltage Rail
VccCore
VccDMI
1.05
5
3.3
0.001
0.001
0.001
0.228
0.063
0.08
0.08
1.7
0.047
5
Voltage
S0 Iccmax
Current (A)
1.05
1.05VccIO 3.711
1.05VccASW 0.903
3.3VccSPI 0.01
3.3VccDSW 0.001
1.8 0.002VccDFTERM
3.3VccRTC 6 uA
3.3VccSus3_3
3.3 / 1.5VccSusHDA
0.095
0.01
VccVRM 1.8 / 1.5 0.167
1.05VccCLKDMI
VccALVDS 3.3
1.8VccTX_LVDS 0.04
0.001
0.07
PCH Power Rail Table
Refer to CPU EDS R1.5
VccSSC 1.05 0.095
VccDIFFCLKN 1.05 0.055
11/07 Change type to 0603
11/07 Change type to 0603
R399
0_0603_5%
R399
0_0603_5%
12
R296
0_0805_5%
R296
0_0805_5%
1 2
J2
PAD-OPEN 4x4m
@J2
PAD-OPEN 4x4m
@
12
R258
0_0603_5%
R258
0_0603_5%
12
C216
0.01U_0402_16V7K
C216
0.01U_0402_16V7K
1
2
R295
0_0603_5%
R295
0_0603_5%
12
C230
1U_0402_6.3V6K
C230
1U_0402_6.3V6K
1
2
C223
1U_0402_6.3V6K
C223
1U_0402_6.3V6K
1
2
C214
0.1U_0402_10V7K
C214
0.1U_0402_10V7K
1
2
C210
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
1
2
C218
22U_0805_6.3V6M
C218
22U_0805_6.3V6M
1
2
R265 0_0603_5%R265 0_0603_5%
12
T48PAD @T48PAD @
R263
0_0603_5%
R263
0_0603_5%
1 2
R260
0_0603_5%
R260
0_0603_5%
1 2
C220
1U_0402_6.3V6K
C220
1U_0402_6.3V6K
1
2
C221
10U_0603_6.3V6M
C221
10U_0603_6.3V6M
1
2
C209
10U_0603_6.3V6M
C209
10U_0603_6.3V6M
1
2
C224
1U_0402_6.3V6K
C224
1U_0402_6.3V6K
1
2
T47PAD @T47PAD @
C395
10U_0603_6.3V6M
@C395
10U_0603_6.3V6M
@
1
2
C215
10U_0603_6.3V6M
C215
10U_0603_6.3V6M
1
2
C217
0.01U_0402_16V7K
C217
0.01U_0402_16V7K
1
2
R300
0_0603_5%
R300
0_0603_5%
12
C228
0.1U_0402_10V7K
C228
0.1U_0402_10V7K
1
2
C212
1U_0402_6.3V6K
C212
1U_0402_6.3V6K
1
2
R293
0_0603_5%
R293
0_0603_5%
12
C226
1U_0402_6.3V6K
C226
1U_0402_6.3V6K
1
2
C213
0.01U_0402_16V7K
C213
0.01U_0402_16V7K
1
2
POWER
VCC CORE
DMI
VCCIO
CRTLVDS
FDI
DFT / SPI HVCMOS
U4G
PANTHER-POINT_FCBGA989
POWER
VCC CORE
DMI
VCCIO
CRTLVDS
FDI
DFT / SPI HVCMOS
U4G
PANTHER-POINT_FCBGA989
VCCCORE[1]
AA23
VCCCORE[2]
AC23
VCCCORE[3]
AD21
VCCCORE[4]
AD23
VCCCORE[5]
AF21
VCCCORE[6]
AF23
VCCCORE[7]
AG21
VCCCORE[8]
AG23
VCCCORE[9]
AG24
VCCCORE[10]
AG26
VCCCORE[11]
AG27
VCCCORE[12]
AG29
VCCCORE[13]
AJ23
VCCCORE[14]
AJ26
VCCCORE[15]
AJ27
VCCDFTERM[4] AJ17
VCCDFTERM[3] AJ16
VCCIO[17]
AN21
VCCIO[18]
AN26
VCCIO[19]
AN27
VCCIO[20]
AP21
VCCIO[23]
AP26
VCCIO[24]
AT24
VCCIO[15]
AN16
VCCIO[16]
AN17
VCCIO[21]
AP23
VCCIO[22]
AP24
VCCADAC U48
VCCTX_LVDS[1] AM37
VCCTX_LVDS[2] AM38
VCCALVDS AK36
VCCVRM[3] AT16
VCCVRM[2]
AP16
VCCAPLLEXP
BJ22
VccAFDIPLL
BG6
VCCIO[28]
AN19 VCCTX_LVDS[4] AP37
VCCTX_LVDS[3] AP36
VSSADAC U47
VSSALVDS AK37
VCCIO[27]
AP17
VCC3_3[6] V33
VCC3_3[7] V34
VCC3_3[3]
BH29 VCCDFTERM[2] AG17
VCCDFTERM[1] AG16
VCCDMI[1] AT20
VCCIO[25]
AN33
VCCIO[26]
AN34
VCCCORE[16]
AJ29
VCCCORE[17]
AJ31
VCCSPI V1
VCCCLKDMI AB36
VCCDMI[2]
AU20
C222
1U_0402_6.3V6K
C222
1U_0402_6.3V6K
1
2
L1
BLM18PG181SN1_0603~D
L1
BLM18PG181SN1_0603~D
12
R256
0_0603_5%
R256
0_0603_5%
12
C219
0.1U_0402_10V7K
C219
0.1U_0402_10V7K
1
2
R254 0_0603_5%R254 0_0603_5%
12
C211
1U_0402_6.3V6K
C211
1U_0402_6.3V6K
1
2
C227
0.1U_0402_10V7K
C227
0.1U_0402_10V7K
1
2
L2
0.1UH_MLF1608DR10KT_10%_1608
L2
0.1UH_MLF1608DR10KT_10%_1608
12
C225
1U_0402_6.3V6K
C225
1U_0402_6.3V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+PCH_V5REF_RUN
+PCH_V5REF_SUS
+1.05VS_VCCA_A_DPL
+3V_VCCPSUS
+VCCSUSHDA
+1.05VS_VCCUSBCORE
+PCH_V5REF_RUN
+PCH_V5REF_SUS
+3V_VCCPSUS
+3VS_VCCPCORE
+VCCA_USBSUS
+3VS_VCCPPCI
+3V_VCCPUSB
+3V_VCCAUBG
+VCCAFDI_VRM
+1.05VS_SATA3
+1.05VM_VCCASW
+PCH_VCCDSW
+3VS_VCC_CLKF33
+VCCDPLL_CPY
+VCCPDSW
+3VS_VCC_CLKF33
+VCCSUS1
+VCCACLK
+VCCRTCEXT
+VCCSST
+1.05VM_VCCSUS
+V_CPU_IO
+VCCAFDI_VRM
+VCCDIFFCLK
+1.05VS_SSCVCC
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_B_DPL
+1.05VS_VCCAUPLL
+VCC3_3_2
+1.05VS_VCC_SATA
+1.05VS_VCCDIFFCLKN
+1.05VM_VCCSUS
+VCCAPLL_CPY_PCH
+VCCSATAPLL
+1.05VS_VCCA_B_DPL
+3VS+5VS
+3V_PCH+5V_PCH
+1.05VS
+3V_PCH
+1.05VS
+3VS
+3VS
+1.05VS
+3V_PCH
+1.05VS
+1.05VS
+3V_PCH
+3VS
+3V_PCH
+3V_DSW
+3VS
+1.05VS
+1.05VS
+1.05VS
+RTCVCC
+VCCAFDI_VRM
+1.05VS_SATA3
+1.05VS_VCC_SATA
+1.05VS
+1.05VS
+1.05VS
+1.05VS
+1.05VS
+1.05VS
+1.05VS_VCCDIFFCLKN
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (8/9) PWR
Custom
21 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (8/9) PWR
Custom
21 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (8/9) PWR
Custom
21 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
1mA
1mA
1mA
228mA
80mA
80mA
VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec
903mA
1mA
10mA
95mA
55mA
Have internal VRM
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA
HOn-Die PLL voltage regulator enable
On-Die PLL Voltage Regulator
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA
HOn-Die PLL voltage regulator enable
On-Die PLL Voltage Regulator
For Deep S3
11/07 Change type to 0603
R273
0_0603_5%
R273
0_0603_5%
12
C237
22U_0805_6.3V6M
@
C237
22U_0805_6.3V6M
@
1
2
L6 10UH_LB2012T100MR_20%L6 10UH_LB2012T100MR_20%
1 2
C249
0.1U_0402_10V7K
C249
0.1U_0402_10V7K
1
2
R281
0_0603_5%
R281
0_0603_5%
12
C265
4.7U_0603_6.3V6K
C265
4.7U_0603_6.3V6K
1
2
R270
0_0603_5%
R270
0_0603_5%
12
C256
1U_0402_6.3V6K
C256
1U_0402_6.3V6K
1
2
D1
CH751H-40PT_SOD323-2
D1
CH751H-40PT_SOD323-2
21
POWER
SATA USB
Clock and Miscellaneous
HDA
CPURTC
PCI/GPIO/LPCMISC
U4J
PANTHER-POINT_FCBGA989
POWER
SATA USB
Clock and Miscellaneous
HDA
CPURTC
PCI/GPIO/LPCMISC
U4J
PANTHER-POINT_FCBGA989
DCPSUSBYP
V12
VCCASW[1]
AA19
VCCASW[2]
AA21
VCCASW[3]
AA24
VCCASW[5]
AA27
VCCASW[6]
AA29
VCCSUSHDA P32
VCCSUS3_3[6] P24
VCCIO[34] T26
VCCIO[4] AD17
VCCASW[7]
AA31
VCCASW[8]
AC26
VCCASW[9]
AC27
VCCASW[10]
AC29
VCCASW[11]
AC31
VCCASW[12]
AD29
V5REF P34
VCC3_3[4] T34
VCCRTC
A22
VCCSUS3_3[10] V24
VCCSUS3_3[9] V23
VCCSUS3_3[8] T24
VCCSUS3_3[7] T23
VCCIO[2] AC16
VCCADPLLB
BF47
VCCDIFFCLKN[1]
AF33
V5REF_SUS M26
VCCIO[3] AC17
DCPSUS[1]
T17
VCCSSC
AG33
VCCADPLLA
BD47
VCCVRM[4]
Y49
VCCACLK
AD49
DCPRTC
N16
VCCASW[4]
AA26
VCCDIFFCLKN[2]
AF34
VCCIO[7]
AF17
DCPSST
V16
VCCIO[5] AF13
VCCASW[22] T21
VCCASW[23] V21
VCCASW[21] T19
VCC3_3[1] AA16
VCC3_3[8] W16
VCCSUS3_3[2] N20
VCCSUS3_3[3] N22
VCCSUS3_3[4] P20
VCCSUS3_3[5] P22
VCCIO[29] N26
VCCIO[30] P26
VCCIO[31] P28
VCCIO[32] T27
V_PROC_IO
BJ8
VCCIO[33] T29
VCCDIFFCLKN[3]
AG34
VCCASW[13]
AD31
VCCASW[14]
W21
VCCASW[15]
W23
VCCASW[16]
W24
VCCASW[17]
W26
VCCASW[18]
W29
VCCASW[19]
W31
VCCASW[20]
W33
VCCIO[6] AF14
VCCVRM[1] AF11
VCCIO[12] AH13
VCCIO[13] AH14
VCC3_3[2] AJ2
VCCAPLLSATA AK1
DCPSUS[3]
AL24
VCCIO[14]
AL29
DCPSUS[4] AN23
VCCSUS3_3[1] AN24
VCCAPLLDMI2
BH23
DCPSUS[2]
V19
VCCDSW3_3
T16
VCC3_3[5]
T38
L3
10UH_LBR2012T100M_20%
@
L3
10UH_LBR2012T100M_20%
@
C247
1U_0402_6.3V
C247
1U_0402_6.3V
1
2
R274
0_0603_5%
R274
0_0603_5%
12
C248
1U_0603_10V6K
C248
1U_0603_10V6K
1
2
C238
0.1U_0402_10V7K
C238
0.1U_0402_10V7K
1
2
R282
0_0603_5%
R282
0_0603_5%
12
R269
0_0603_5%
R269
0_0603_5%
12
C244
1U_0402_6.3V6K
C244
1U_0402_6.3V6K
1
2
L3
0_0805_5%
L3
0_0805_5%
1 2
C255
0.1U_0402_10V7K
C255
0.1U_0402_10V7K
1
2
R283
0_0603_5%
R283
0_0603_5%
12
C240
0.1U_0402_25V6
C240
0.1U_0402_25V6
1
2
C271
0.1U_0402_16V4Z
C271
0.1U_0402_16V4Z
1
2
C229
22U_0805_6.3V6M
@
C229
22U_0805_6.3V6M
@
1
2
L5 10UH_LB2012T100MR_20%L5 10UH_LB2012T100MR_20%
1 2
C269
0.1U_0402_10V7K
C269
0.1U_0402_10V7K
1
2
R307
0_0603_5%
@
R307
0_0603_5%
@
12
C259
1U_0402_6.3V6K
C259
1U_0402_6.3V6K
1
2
R304
0_0603_5%
R304
0_0603_5%
12
R285
0_0603_5%
R285
0_0603_5%
12
C242
22U_0805_6.3V6M
C242
22U_0805_6.3V6M
1
2
C246
1U_0402_6.3V6K
C246
1U_0402_6.3V6K
1
2
R290
0_0603_5%
@R290
0_0603_5%
@
12
C262
1U_0402_6.3V6K
C262
1U_0402_6.3V6K
1
2
C266
0.1U_0402_10V7K
C266
0.1U_0402_10V7K
1
2
C251
1U_0402_6.3V6K
C251
1U_0402_6.3V6K
1
2
C233
1U_0402_6.3V6K
C233
1U_0402_6.3V6K
1
2
C258
0.1U_0402_10V7K
C258
0.1U_0402_10V7K
1
2
C235
0.1U_0402_10V7K
@C235
0.1U_0402_10V7K
@
12
R279
100_0402_5%
R279
100_0402_5%
12
C234
0.1U_0402_10V7K
C234
0.1U_0402_10V7K
1
2
C254
0.1U_0402_10V7K
C254
0.1U_0402_10V7K
1
2
R275
100_0402_5%
R275
100_0402_5%
12
C257
1U_0402_6.3V6K
C257
1U_0402_6.3V6K
1
2
C232
1U_0402_6.3V6K
C232
1U_0402_6.3V6K
1
2
+
C250
220U_B2_2.5VM_R35
+
C250
220U_B2_2.5VM_R35
1
2
T15 PADT15 PAD
C253
1U_0402_6.3V6K
C253
1U_0402_6.3V6K
1
2
C236
0.1U_0402_10V7K
C236
0.1U_0402_10V7K
1
2
C241
22U_0805_6.3V6M
C241
22U_0805_6.3V6M
1
2
C243 1U_0402_6.3V6K@C243 1U_0402_6.3V6K@1 2
C268
1U_0402_6.3V6K
C268
1U_0402_6.3V6K
1
2
C231
10U_0603_6.3V6M
C231
10U_0603_6.3V6M
1
2
C261
1U_0402_6.3V6K
C261
1U_0402_6.3V6K
1
2
R272
0_0603_5%
R272
0_0603_5%
12
R271
0_0603_5%
R271
0_0603_5%
12
+
C252
220U_B2_2.5VM_R35
+
C252
220U_B2_2.5VM_R35
1
2
R276
0_0603_5%
R276
0_0603_5%
12
R278
0_0603_5%
R278
0_0603_5%
12
R284
0_0603_5%
R284
0_0603_5%
12
C270
0.1U_0402_10V7K
@
C270
0.1U_0402_10V7K
@
1
2
C245
1U_0402_6.3V6K
C245
1U_0402_6.3V6K
1
2
R288
0_0603_5%
R288
0_0603_5%
12
T16PAD T16PAD
C267
0.1U_0402_10V7K
@
C267
0.1U_0402_10V7K
@
1
2
C263
0.1U_0402_10V7K
C263
0.1U_0402_10V7K
1
2
R286
0_0603_5%
R286
0_0603_5%
12
R277
0_0805_5%
R277
0_0805_5%
1 2
D2
CH751H-40PT_SOD323-2
D2
CH751H-40PT_SOD323-2
21
R268
0_0603_5%
@R268
0_0603_5%
@
12
C264
1U_0402_6.3V6K
@C264
1U_0402_6.3V6K
@
1
2
C239
1U_0402_6.3V6K
@C239
1U_0402_6.3V6K
@
1
2
R287
0_0603_5%
R287
0_0603_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (9/9) VSS
Custom
22 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (9/9) VSS
Custom
22 64Monday, January 16, 2012
2011/07/21 2012/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QIWY3 LA-8001P
1.0
PCH (9/9) VSS
Custom
22 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
U4I
PANTHER-POINT_FCBGA989
U4I
PANTHER-POINT_FCBGA989
VSS[159]
AY4
VSS[160]
AY42
VSS[161]
AY46
VSS[162]
AY8
VSS[163]
B11
VSS[164]
B15
VSS[165]
B19
VSS[166]
B23
VSS[167]
B27
VSS[168]
B31
VSS[169]
B35
VSS[170]
B39
VSS[171]
B7
VSS[173]
BB12
VSS[174]
BB16
VSS[175]
BB20
VSS[176]
BB22
VSS[177]
BB24
VSS[178]
BB28
VSS[179]
BB30
VSS[180]
BB38
VSS[181]
BB4
VSS[182]
BB46
VSS[183]
BC14
VSS[184]
BC18
VSS[185]
BC2
VSS[186]
BC22
VSS[187]
BC26
VSS[188]
BC32
VSS[189]
BC34
VSS[190]
BC36
VSS[191]
BC40
VSS[192]
BC42
VSS[193]
BC48
VSS[194]
BD46
VSS[195]
BD5
VSS[196]
BE22
VSS[197]
BE26
VSS[198]
BE40
VSS[199]
BF10
VSS[200]
BF12
VSS[201]
BF16
VSS[202]
BF20
VSS[203]
BF22
VSS[204]
BF24
VSS[205]
BF26
VSS[206]
BF28
VSS[207]
BD3
VSS[208]
BF30
VSS[209]
BF38
VSS[210]
BF40
VSS[211]
BF8
VSS[212]
BG17
VSS[213]
BG21
VSS[214]
BG33
VSS[215]
BG44
VSS[216]
BG8
VSS[217]
BH11
VSS[218]
BH15
VSS[219]
BH17
VSS[220]
BH19
VSS[222]
BH27
VSS[223]
BH31
VSS[224]
BH33
VSS[225]
BH35
VSS[226]
BH39
VSS[227]
BH43
VSS[228]
BH7
VSS[229]
D3
VSS[230]
D12
VSS[231]
D16
VSS[232]
D18
VSS[233]
D22
VSS[234]
D24
VSS[235]
D26
VSS[236]
D30
VSS[237]
D32
VSS[264] K7
VSS[265] L18
VSS[266] L2
VSS[267] L20
VSS[268] L26
VSS[269] L28
VSS[270] L36
VSS[271] L48
VSS[272] M12
VSS[273] P16
VSS[274] M18
VSS[275] M22
VSS[276] M24
VSS[277] M30
VSS[278] M32
VSS[279] M34
VSS[280] M38
VSS[281] M4
VSS[282] M42
VSS[283] M46
VSS[284] M8
VSS[285] N18
VSS[286] P30
VSS[288] P11
VSS[289] P18
VSS[290] T33
VSS[291] P40
VSS[292] P43
VSS[293] P47
VSS[294] P7
VSS[295] R2
VSS[296] R48
VSS[297] T12
VSS[298] T31
VSS[299] T37
VSS[300] T4
VSS[301] W34
VSS[302] T46
VSS[303] T47
VSS[304] T8
VSS[305] V11
VSS[306] V17
VSS[307] V26
VSS[308] V27
VSS[309] V29
VSS[310] V31
VSS[311] V36
VSS[312] V39
VSS[313] V43
VSS[314] V7
VSS[315] W17
VSS[316] W19
VSS[238]
D34
VSS[239]
D38
VSS[240]
D42
VSS[241]
D8
VSS[242]
E18
VSS[243]
E26
VSS[244]
G18
VSS[245]
G20
VSS[246]
G26
VSS[247]
G28
VSS[248]
G36
VSS[249]
G48
VSS[250]
H12
VSS[251]
H18
VSS[317] W2
VSS[318] W27
VSS[319] W48
VSS[320] Y12
VSS[321] Y38
VSS[322] Y4
VSS[323] Y42
VSS[324] Y46
VSS[325] Y8
VSS[328] BG29
VSS[329] N24
VSS[330] AJ3
VSS[287] N47
VSS[252]
H22
VSS[253]
H24
VSS[254]
H26
VSS[255]
H30
VSS[256]
H32
VSS[257]
H34
VSS[258]
F3
VSS[262] K39
VSS[263] K46
VSS[259] H46
VSS[260] K18
VSS[261] K26
VSS[331] AD47
VSS[333] B43
VSS[334] BE10
VSS[335] BG41
VSS[337] G14
VSS[338] H16
VSS[340] T36
VSS[342] BG22
VSS[343] BG24
VSS[344] C22
VSS[345] AP13
VSS[172]
F45
VSS[221]
H10
VSS[346] M14
VSS[347] AP3
VSS[348] AP1
VSS[349] BE16
VSS[350] BC16
VSS[351] BG28
VSS[352] BJ28
U4H
PANTHER-POINT_FCBGA989
U4H
PANTHER-POINT_FCBGA989
VSS[1]
AA17
VSS[2]
AA2
VSS[3]
AA3
VSS[5]
AA34
VSS[6]
AB11
VSS[7]
AB14
VSS[8]
AB39
VSS[9]
AB4
VSS[10]
AB43
VSS[11]
AB5
VSS[12]
AB7
VSS[13]
AC19
VSS[14]
AC2
VSS[15]
AC21
VSS[16]
AC24
VSS[17]
AC33
VSS[18]
AC34
VSS[19]
AC48
VSS[20]
AD10
VSS[21]
AD11
VSS[22]
AD12
VSS[23]
AD13
VSS[24]
AD19
VSS[25]
AD24
VSS[26]
AD26
VSS[27]
AD27
VSS[28]
AD33
VSS[29]
AD34
VSS[30]
AD36
VSS[31]
AD37
VSS[33]
AD39
VSS[34]
AD4
VSS[35]
AD40
VSS[36]
AD42
VSS[37]
AD43
VSS[38]
AD45
VSS[39]
AD46
VSS[43]
AF10
VSS[44]
AF12
VSS[46]
AD16
VSS[47]
AF16
VSS[48]
AF19
VSS[49]
AF24
VSS[50]
AF26
VSS[51]
AF27
VSS[52]
AF29
VSS[53]
AF31
VSS[54]
AF38
VSS[55]
AF4
VSS[56]
AF42
VSS[57]
AF46
VSS[59]
AF7
VSS[60]
AF8
VSS[61]
AG19
VSS[62]
AG2
VSS[63]
AG31
VSS[64]
AG48
VSS[65]
AH11
VSS[66]
AH3
VSS[67]
AH36
VSS[68]
AH39
VSS[69]
AH40
VSS[70]
AH42
VSS[71]
AH46
VSS[72]
AH7
VSS[73]
AJ19
VSS[76]
AJ33
VSS[77]
AJ34
VSS[78]
AK12
VSS[79]
AK3
VSS[80] AK38
VSS[81] AK4
VSS[82] AK42
VSS[83] AK46
VSS[84] AK8
VSS[85] AL16
VSS[86] AL17
VSS[87] AL19
VSS[88] AL2
VSS[89] AL21
VSS[90] AL23
VSS[91] AL26
VSS[92] AL27
VSS[93] AL31
VSS[96] AL48
VSS[97] AM11
VSS[98] AM14
VSS[99] AM36
VSS[100] AM39
VSS[102] AM45
VSS[103] AM46
VSS[104] AM7
VSS[105] AN2
VSS[106] AN29
VSS[107] AN3
VSS[108] AN31
VSS[109] AP12
VSS[110] AP19
VSS[111] AP28
VSS[112] AP30
VSS[113] AP32
VSS[114] AP38
VSS[116] AP42
VSS[117] AP46
VSS[118] AP8
VSS[119] AR2
VSS[120] AR48
VSS[121] AT11
VSS[122] AT13
VSS[123] AT18
VSS[124] AT22
VSS[125] AT26
VSS[126] AT28
VSS[127] AT30
VSS[128] AT32
VSS[131] AT42
VSS[132] AT46
VSS[133] AT7
VSS[134] AU24
VSS[135] AU30
VSS[136] AV16
VSS[137] AV20
VSS[138] AV24
VSS[139] AV30
VSS[140] AV38
VSS[141] AV4
VSS[142] AV43
VSS[143] AV8
VSS[144] AW14
VSS[145] AW18
VSS[146] AW2
VSS[147] AW22
VSS[148] AW26
VSS[149] AW28
VSS[150] AW32
VSS[151] AW34
VSS[152] AW36
VSS[153] AW40
VSS[154] AW48
VSS[155] AV11
VSS[156] AY12
VSS[157] AY22
VSS[158] AY28
VSS[40]
AD8
VSS[42]
AE3
VSS[45]
AD14
VSS[115] AP4
VSS[0]
H5
VSS[58]
AF5
VSS[32]
AD38
VSS[4]
AA33
VSS[74]
AJ21
VSS[75]
AJ24
VSS[41]
AE2
VSS[129] AT34
VSS[130] AT39
VSS[101] AM43
VSS[95] AL34
VSS[94] AL33
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+SP_PLLVDD
XTALIN XTAL_OUT
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N1
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P12
PCIE_CRX_C_GTX_N12
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_N15
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N2
PCIE_CRX_C_GTX_P14
PCIE_CRX_C_GTX_P15
PCIE_CRX_C_GTX_N14
PCIE_CRX_C_GTX_N15
PCIE_CRX_C_GTX_N0
PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3
PCIE_CRX_GTX_P4
PCIE_CRX_C_GTX_N2
PCIE_CRX_GTX_N4 PCIE_CRX_C_GTX_N4
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N5
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P2
PCIE_CRX_C_GTX_N6
PCIE_CRX_GTX_P3
PCIE_CRX_C_GTX_P6
PCIE_CRX_GTX_N3
PCIE_CRX_C_GTX_N7
PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_P8
PCIE_CRX_C_GTX_N8
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P10
PCIE_CRX_C_GTX_P9
PCIE_CRX_C_GTX_N9
PCIE_CRX_C_GTX_N10
PCIE_CRX_C_GTX_P10
PCIE_CRX_C_GTX_P11
PCIE_CRX_C_GTX_N11
PCIE_CRX_C_GTX_P12
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_C_GTX_P13
PCIE_CRX_C_GTX_N13
PCIE_CTX_GRX_P[0..15]
PCIE_CTX_GRX_N[0..15]
PCIE_CRX_GTX_N[0..15]
PCIE_CRX_GTX_P[0..15]
PLT_RST_VGA#
DGPU_HOLD_RST#
CLK_REQ_GPU#
VGA_SMB_DA2
VGA_SMB_CK2
PLT_RST#
PCH_THRMTRIP#_R
OVERT#
VGA_EDID_DATA
VGA_EDID_CLK
I2CB_SCL
I2CB_SDA
VGA_CRT_DATA
VGA_CRT_CLK
CLK_REQ_GPU#
CLK_PCIE_VGA
CLK_PCIE_VGA#
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
PLT_RST_VGA#
PEX_TERMP
GC6_EVENT#_R
OVERT#
GPU_VID5
OVERT#
GC6_EVENT#_R
+DACA_VDD
VGA_SMB_DA2
VGA_SMB_CK2
XTALOUT
XTALSSIN
XTALIN
XTAL_OUT
+PLLVDD
+SP_PLLVDD
GPU_VID0
GPU_VID2
GPU_VID1
GPU_VID3
GPU_VID4
+PLLVDD
VGA_EDID_DATA
VGA_EDID_CLK
VGA_CRT_DATA
VGA_CRT_CLK
I2CB_SCL
I2CB_SDA
VGA_AC_DET_R
VGA_AC_DETVGA_AC_DET_R
CLK_REQ_VGA#<15>
DGPU_PWR_EN<18,48>
PCIE_CTX_GRX_P[0..15]<5>
PCIE_CRX_GTX_N[0..15]<5>
PCIE_CRX_GTX_P[0..15]<5>
PCIE_CTX_GRX_N[0..15]<5>
DGPU_HOLD_RST#<18>
PLT_RST#<18,36,37,42,46>
EC_SMB_DA2 <15,39,42>
EC_SMB_CK2 <15,39,42>
PCH_THRMTRIP#_R <19>
CLK_PCIE_VGA<15>
CLK_PCIE_VGA#<15>
MEM_VREF <28,29,30,31>
GPU_VID0 <56>
GPU_VID2 <56>
GPU_VID1 <56>
GPU_VID3 <56>
GPU_VID4 <56>
GPU_VID5 <56>
GC6_EVENT# <19>
VGA_AC_DET <42,56>
DPRSLPVR_VGA <56>
+1.05VS_VGA
+3VS_VGA
+3VS_VGA +3VS_VGA
+VDD33MISC
+VDD33MISC
+VDD33MISC
+1.05VS_VGA
+VDD33MISC
+VDD33MISC
+VDD33MISC+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
QIWY3 LA-8001P
1.0
N13P-PCIE/DAC/GPIO
23 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
QIWY3 LA-8001P
1.0
N13P-PCIE/DAC/GPIO
23 64Monday, January 16, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of