LS 5588 NAW20 R0.3 Compal 5588P
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A B C D E 1 1 Compal confidential Schematics Document Mobile Penryn uFCPGA with Intel Cantiga_GM+ICH9-M SFF core logic 2 2 3 3 ULV core logic HDI board 2009-06-19 DISCRETE VGA M92 V.03 4 4 Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. Cover Sheet Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet E 1 of 35 A B C D E Compal confidential ULV Model Name : NAW20 File Name : LS-5588P ZZZ CK505 Mobile Peryn Thermal Sensor 1 PCB-MB page 4 page 16 page 4,5,6,7 H_A#(3..35) H_D#(0..63) DISCRETE VGA HDI BRD page 17,18,19,20,21 ATI M92 S2 1 Clock Generator ICS9LPRS387BKLFT MLF 72P LV/ULV Dual Core uFCPGA-956 CPU - SFF FSB 667/800/1066MHz 1.05V Intel Cantiga GS 600MHz DDR3 1066MHz 1.5V FCBGA 1363 - SFF DDR3-SO-DIMM X 2 BANK 0, 1, 2, 3 page 14,15 Dual Channel VRAM DDR3 512MB(64Mx16) page 8,9,10,11,12,13 2 2 DMI X4 SATA x3 RGB USB x9 Single Channel PCIE*3 Intel ICH9-M LPC WBMMAP-569 - SFF HDA page 22,23,24,25 3 3 Golden finger HDMI HDI to I/O board page 26 HDA LPC EC AUDIO PCIE CRT miniPCIE*1 USB LVDS USB*2 CMOS SATA ODD miniPCIE CardReader *2 HDD BT LAN I/O BRD PORTION 4 ESATA Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C 4 D Title Compal Electronics, Inc. Block Diagram Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet E 2 of 35 A Voltage Rails ( O MEANS ON X MEANS OFF ) Symbol Note : +B +5VALW +3VL +3VALW +1.5V +5VS +3VS : means Digital Ground +1.5VS power plane +0.75VS +VCCP : means Analog Ground +CPU_CORE +VGA_CORE @ : means just reserve , no build ME@ : means ME part. 45@ : means install after SMT. +1.1VS +1.8VS State 1 S0 O O O O S1 O O O O S3 O O O X S5 S4/AC O O X X S5 S4/ Battery only O X X X S5 S4/AC & Battery don't exist X X X X SMBUS Control Table 1 SOURCE INVERTER BATT SERIAL EEPROM THERMAL SENSOR (CPU) SODIMM CLK CHIP MINI CARD LCD X X V X V X X V X X X X X X X X ICH9 X X X X V V V X Cantiga X X X X X X X V SMB_EC_CK1 SMB_EC_DA1 KB926 SMB_EC_CK2 SMB_EC_DA2 KB926 SMB_CK_CLK1 SMB_CK_DAT1 LCD_CLK LCD_DAT I2C / SMBUS ADDRESSING DEVICE HEX ADDRESS DDR SO-DIMM 0 A0 10100000 CLOCK GENERATOR (EXT.) D2 11010010 Compal Secret Data Security Classification 2009/04/20 Issued Date Deciphered Date 2010/04/30 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A Title Compal Electronics, Inc. Notes List Size Document Number Custom LS-5588 Date: Wednesday, July 01, 2009 Rev 0.3 Sheet 3 of 35 5 4 3 2 1 XDP_TDI +VCCP XDP_DBRESET# D XDP_TDO XDP_TDI R1 1 2 54.9_0402_1% XDP_TMS XDP_TMS R2 1 2 54.9_0402_1% XDP_TRST# XDP_TDO R3 1 2 XDP_TCK XDP_BPM#5 R4 XDP_BPM#5 2 3 2 3 2 3 2 @ D9 PJDLC05_SOT23-3 D10 PJDLC05_SOT23-3 @ D11 PJDLC05_SOT23-3 XDP_TRST# R6 1 2 51_0402_1% XDP_TCK R7 1 2 54.9_0402_1% G5 K2 H4 K4 L1 [8] H_RS#0 H_RS#1 H_RS#2 H_TRDY# [8] [8] [8] [8] H_HIT# H_HITM# [8] [8] H_RESET# 1 C1251 @ For EMI 2 C Add 0 ohm per EMI request. 10/17 +3VS R03 2 0_0402_5% XDP_DBRESET# H_PROCHOT# Place Close to U1. XDP_BPM#5 [24] [31] +VCCP H_PROCHOT# PROCHOT# THERMDA THERMDC THERMTRIP# R22 R23 R24 H_THERMDA_R H_THERMDC_R 1 1 1 2 68_0402_5% 2 0_0402_5% 2 0_0402_5% C1034 U7 2 1 H_THERMDA 2 H_THERMDC 2 2200P_0402_50V7K THERM# 3 VDD H_THERMDA H_THERMDC 4 SMCLK DP SMDATA DN ALERT# THERM# GND 8 SMB_EC_CK2 7 SMB_EC_DA2 6 R3051 EC_SMB_CK2 [17,26] EC_SMB_DA2 [17,26] 2 10K_0402_5% +3VS 5 R306 B10 H_THERMTRIP# H_THERMTRIP# [8,23] R03 H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil H CLK BCLK[0] BCLK[1] 1 C1035 1 D38 BB34 BD34 1 1 1 [8] 1 R25 XDP_BPM#5_R XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# H_PROCHOT# THERMAL 1 2 1 2 [23] H_LOCK# H_RESET# H2 F2 AY8 BA7 BA5 AY2 AV10 AV2 AV4 AW7 AU1 AW5 AV8 J7 For ESD A35 C35 CLK_CPU_BCLK [16] CLK_CPU_BCLK# [16] 1 @ +3VS 1 2 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8 C1045 Address:100_1100 2 B C1036 2 @ 1 C1037 2 @ 1 C1038 2 @ 1 C1039 2 @ 1 C1040 2 @ 1 C1041 2 @ 1 C1042 2 @ 0.1U_0402_16V4Z For ESD 4/21 1 0.1U_0402_16V4Z H_A20M# H_FERR# H_IGNNE# H_INIT# H_STPCLK# H_INTR H_NMI H_SMI# 0.1U_0402_16V4Z PENRYN SFF_UFCBGA956 0.1U_0402_16V4Z RSVD01 RSVD02 RSVD03 RSVD04 RSVD05 RSVD06 RSVD07 BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# H_INIT# N1 0518/'09 RESERVED V2 Y2 AG5 AL5 J9 F4 H8 B STPCLK# LINT0 LINT1 SMI# HIT# HITM# B40 D8 9/20 [8] 0.1U_0402_16V4Z F8 C9 C5 E5 H_BR0# R10 51_0402_1% 0.1U_0402_16V4Z H_STPCLK# H_INTR H_NMI H_SMI# A20M# FERR# IGNNE# M2 [8] [8] [8] 0.1U_0402_16V4Z C7 D4 F10 H_DEFER# H_DRDY# H_DBSY# R03 0.1U_0402_16V4Z [23] H_A20M# [23] H_FERR# [23] H_IGNNE# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# ICH H_ADSTB#1 AN1 AK4 AG1 AT4 AK2 AT2 AH2 AF4 AJ5 AH4 AM4 AP4 AR5 AJ1 AL1 AM2 AU5 AP2 AR1 AN5 IERR# INIT# RESET# RS[0]# RS[1]# RS[2]# TRDY# ADDR GROUP 1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 N5 F38 J1 [8] [8] [8] 0.1U_0402_16V4Z H_A#[17..35] C BR0# LOCK# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# H_ADS# H_BNR# H_BPRI# 1 R1 R5 U1 P4 W5 DEFER# DRDY# DBSY# M4 J5 L5 R9 56_0402_5% H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 ADS# BNR# BPRI# 0.1U_0402_16V4Z [8] [8] [8] [8] [8] A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# CONTROL H_ADSTB#0 [23] [23] [23] [23] @ This shall place near CPU ADDR GROUP 0 [8] P2 V4 W1 T4 AA1 AB4 T2 AC5 AD2 AD4 AA5 AE5 AB2 AC1 Y4 [8] D12 PJDLC05_SOT23-3 U1A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 [8] @ 0.1U_0402_16V4Z H_A#[3..16] XDP/ITP SIGNALS [8] +VCCP D R03 3 Place close to U1. 54.9_0402_1% 2 54.9_0402_1% 1 1 C1043 2 @ A A Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Penryn(1/3)-AGTL+/ITP-XDP Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 4 of 35 4 3 2 1 +VCC_CORE A37 C37 B38 DATA GROUP 2 MISC BSEL[0] BSEL[1] BSEL[2] COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# AE43 AD44 AE1 AF2 COMP0 COMP1 COMP2 COMP3 G7 B8 C41 E7 D10 BD10 H_PSI# H_DSTBN#3 [8] H_DSTBP#3 [8] H_DINV#3 [8] H_DPRSTP# [8,23,31] H_DPSLP# [23] H_DPWR# [8] H_PWRGOOD [23] H_CPUSLP# [8] T11 2 [16] CPU_BSEL0 [16] CPU_BSEL1 [16] CPU_BSEL2 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 H_DSTBN#2 [8] H_DSTBP#2 [8] H_DINV#2 [8] H_D#[48..63] [8] PENRYN SFF_UFCBGA956 Cause CPU core power change to 1 phase, and not need support the pin, leave it as TP. 10/02 layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs CPU_BSEL B CPU_BSEL2 CPU_BSEL1 Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils. CPU_BSEL0 166 0 1 1 200 0 1 0 266 0 0 0 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP_001 VCCP_002 VCCP_003 VCCP_004 VCCP_005 VCCP_006 VCCP_007 VCCP_008 VCCP_009 VCCP_010 VCCP_011 VCCP_012 VCCP_013 VCCP_014 VCCP_015 VCCP_016 VCCA[01] VCCA[02] VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE AB28 AD30 AD28 Y26 AB26 AD26 AF30 AF28 AH30 AH28 AF26 AH26 AK30 AK28 AM30 AM28 AP30 AP28 AK26 AM26 AP26 AT30 AT28 AV30 AV28 AY30 AY28 AT26 AV26 AY26 BB30 BB28 BD30 D +VCCP J11 R27 1 E11 R28 1 G11 R29 1 J37 K38 L37 N37 P38 R37 U37 V38 W37 AA37 AB38 AC37 AE37 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% C 1 + Change to 330u_R9, casue high limitation. 12/14 C5 330U_D2E_2.5VM_R9M 2 B34 D34 +1.5VS BD8 BC7 BB10 BB8 BC5 BB4 AY4 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 BD12 VCCSENSE BC13 VSSSENSE [31] [31] [31] [31] [31] [31] [31] VCCSENSE [31] VSSSENSE [31] 1 C6 2 1 C7 2 Near pin D34 TEST5 TEST6 T9 T10 AW43 E37 D40 C43 AE41 AY10 AC43 AV38 AT44 AV40 AU41 AW41 AR41 BA37 BB38 AY36 AT40 BC35 BC39 BA41 BB40 BA35 AU43 AY40 AY38 BC37 F32 G33 H32 J33 K32 L33 M32 N33 P32 R33 T32 U33 V32 W33 Y32 AA33 AB32 AC33 AD32 AE33 AF32 AG33 AH32 AJ33 AK32 AL33 AM32 AN33 AP32 AR33 AT34 AT32 AU33 AV32 AY32 BB32 BD32 B28 B30 B26 D28 D30 F30 F28 H30 H28 D26 F26 H26 K30 K28 M30 M28 K26 M26 P30 P28 T30 T28 V30 V28 P26 T26 V26 Y30 Y28 AB30 10U_0805_6.3V6M TEST2 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 0.01U_0402_16V7K V_CPU_GTLREF T8 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# AP44 AR43 AH40 AF40 AJ43 AG41 AF44 AH44 AM44 AN43 AM40 AK40 AG43 AP40 AN41 AL41 AK44 AL43 AJ41 2 H_DSTBN#1 H_DSTBP#1 H_DINV#1 P44 V40 V44 AB44 R41 W41 N43 U41 AA41 AB40 AD40 AC41 AA43 Y40 Y44 T44 U43 W43 R43 D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# U1C 2 [8] [8] [8] H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# DATA GROUP 1 C F40 G43 E43 J43 H40 H44 G39 E41 L41 K44 N41 T40 M40 G41 M44 L43 K40 J41 P40 +VCC_CORE [8] 1 R30 54.9_0402_1% 1 R31 27.4_0402_1% 1 R32 54.9_0402_1% 1 R33 27.4_0402_1% H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16..31] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 DATA GROUP 0 D [8] [8] [8] [8] H_D#[32..47] U1B 2 H_D#[0..15] DATA GROUP 3 [8] Near pin B34 5 B PENRYN SFF_UFCBGA956 Length match within 25 mils. The trace width/space/other is 20/7/25. +VCC_CORE R34 1 +VCCP 2 VCCSENSE 100_0402_1% 1 R35 1 2 VSSSENSE 100_0402_1% R36 1K_0402_1% Close to CPU pin within 500mils. 1 V_CPU_GTLREF 2 Z=55 ohm R37 2K_0402_1% A 2 A Close to CPU pin AW43 within 500mils. Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Penryn(2/3)-AGTL+/ITP-XDP Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 5 of 35 5 4 VCCP_021 VCCP_022 VCCP_023 VCCP_024 VCCP_025 VCCP_026 VCCP_027 VCCP_028 VCCP_029 VCCP_030 VCCP_031 VCCP_032 VCCP_033 VCCP_034 VCCP_035 VCCP_036 VCCP_037 VCCP_038 VCCP_039 VCCP_040 VCCP_041 VCCP_042 VCCP_043 VCCP_044 VCCP_045 VCCP_046 VCCP_047 VCCP_048 VCCP_049 VCCP_050 VCCP_051 VCCP_052 VCCP_053 VCCP_054 VCCP_055 VCCP_056 VCCP_057 VCCP_058 VCCP_059 VCCP_060 VCCP_061 VCCP_062 VCCP_063 VCCP_064 VCCP_065 VCCP_066 VCCP_067 VCCP_068 VCCP_069 VCCP_070 VCCP_071 VCCP_072 VCCP_073 VCCP_074 VCCP_075 VCCP_076 VCCP_077 VCCP_078 VCCP_079 VCCP_080 VCCP_081 VCCP_082 VCCP_083 VCCP_084 VCCP_085 VCCP_086 VCCP_087 VCCP_088 VCCP_089 VCCP_090 VCCP_091 VCCP_092 VCCP_093 VCCP_094 VCCP_095 VCCP_096 VCCP_097 VCCP_098 VCCP_099 VCCP_100 VCCP_101 VCCP_102 VCCP_103 VCCP_104 VCCP_105 VCCP_106 VCCP_107 VCCP_108 VCCP_109 VCCP_110 VCCP_111 VCCP_112 VCCP_113 VCCP_114 VCCP_115 VCCP_116 VCCP_117 VCCP_118 VCCP_119 VCCP_120 VCCP_121 VCCP_122 VCCP_123 VCCP_124 VCCP_125 VCCP_126 VCCP_127 VCCP_128 VCCP_129 VCCP_130 VCCP_131 VCCP_132 VCCP_133 VCCP_134 VCCP_135 VCCP_136 VCCP_137 VCCP_138 VCCP_139 VCCP_140 VCCP_141 VCCP_142 VCCP_143 VCCP_144 VCCP_145 AL37 AN37 AP38 B32 C33 D32 E35 E33 F34 G35 F36 H36 J35 L35 N35 K36 R35 U35 P36 V36 W35 AA35 AC35 AB36 AE35 AG35 AJ35 AF36 AL35 AN35 AK36 AP36 B12 B14 C13 D12 D14 E13 F14 F12 G13 H14 H12 J13 K14 K12 L13 L11 M14 N13 N11 K10 P14 P12 R13 R11 T14 U13 U11 V14 V12 W13 W11 P10 V10 Y14 AA13 AA11 AB14 AB12 AC13 AC11 AD14 AB10 AE13 AE11 AF14 AF12 AG13 AG11 AH14 AJ13 AJ11 AF10 AK14 AK12 AL13 AL11 AN13 AN11 AP12 AR13 AR11 AK10 AP10 AU13 AU11 L9 L7 N9 N7 R9 R7 U9 U7 W9 W7 AA9 AA7 AC9 AC7 AE9 AE7 AG9 AG7 AJ9 AJ7 AL9 AL7 AN9 AN7 AR9 AR7 A33 A13 3 Security Classification Issued Date 2009/04/20 3 Compal Secret Data Deciphered Date 2010/04/30 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 Title Date: VCCP_017 VCCP_018 VCCP_019 VCCP_020 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110 VCC_111 VCC_112 VCC_113 VCC_114 VCC_115 VCC_116 VCC_117 VCC_118 VCC_119 VCC_120 VCC_121 VCC_122 VCC_123 VCC_124 VCC_125 VCC_126 VCC_127 VCC_128 VCC_129 VCC_130 VCC_131 VCC_132 VCC_133 VCC_134 VCC_135 VCC_136 VCC_137 VCC_138 VCC_139 VCC_140 VCC_141 VCC_142 VCC_143 VCC_144 VCC_145 VCC_146 VCC_147 VCC_148 VCC_149 VCC_150 VCC_151 VCC_152 VCC_153 VCC_154 VCC_155 VCC_156 VCC_157 VCC_158 VCC_159 VCC_160 VCC_161 VCC_162 VCC_163 VCC_164 VCC_165 VCC_166 VCC_167 VCC_168 VCC_169 VCC_170 VCC_171 VCC_172 VCC_173 VCC_174 VCC_175 VCC_176 VCC_177 VCC_178 VCC_179 VCC_180 VCC_181 VCC_182 VCC_183 VCC_184 VCC_185 VCC_186 VCC_187 VCC_188 VCC_189 VCC_190 VCC_191 VCC_192 VCC_193 VCC_194 VCC_195 VCC_196 VCC_197 VCC_198 VCC_199 VCC_200 VCC_201 VCC_202 VCC_203 VCC_204 VCC_205 VCC_206 VCC_207 VCC_208 VCC_209 VCC_210 VCC_211 VCC_212 VCC_213 VCC_214 VCC_215 VCC_216 VCC_217 VCC_218 VCC_219 VCC_220 C 4 AF38 AG37 AJ37 AK38 BD28 BB26 BD26 B22 B24 D22 D24 F24 F22 H24 H22 K24 K22 M24 M22 P24 P22 T24 T22 V24 V22 Y24 Y22 AB24 AB22 AD24 AD22 AF24 AF22 AH24 AH22 AK24 AK22 AM24 AM22 AP24 AP22 AT24 AT22 AV24 AV22 AY24 AY22 BB24 BB22 BD24 BD22 B16 B18 B20 D16 D18 F18 F16 H18 H16 D20 F20 H20 K18 K16 M18 M16 K20 M20 P18 P16 T18 T16 V18 V16 P20 T20 V20 Y18 Y16 AB18 AB16 AD18 AD16 Y20 AB20 AD20 AF18 AF16 AH18 AH16 AF20 AH20 AK18 AK16 AM18 AM16 AP18 AP16 AK20 AM20 AP20 AT18 AT16 AV18 AV16 AY18 AY16 AT20 AV20 AY20 BB18 BB16 BD18 BD16 BB20 BD20 AM14 AP14 AT14 AV14 AY14 BB14 BD14 5 2 1 D D +VCCP +VCC_CORE U1F PENRYN SFF_UFCBGA956 C +VCCP B B A A Penryn(3/3)-Power Compal Electronics, Inc. Size Document Number Custom LS-5588 Wednesday, July 01, 2009 Sheet 1 6 of 35 Rev 0.3 4 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 C55 1U_0402_6.3V6K 2 1 C54 1U_0402_6.3V6K 2 1 C53 1U_0402_6.3V6K 2 1 C52 1U_0402_6.3V6K 2 1 C51 1U_0402_6.3V6K 2 1 C50 1U_0402_6.3V6K 2 1 C49 1U_0402_6.3V6K 2 1 C48 1U_0402_6.3V6K 2 1 C47 1U_0402_6.3V6K 2 1 C46 1U_0402_6.3V6K 2 1 C45 1U_0402_6.3V6K 2 1 C44 1U_0402_6.3V6K 2 1 C43 1U_0402_6.3V6K 2 1 C42 1U_0402_6.3V6K 2 1 C41 1U_0402_6.3V6K 2 1 C40 1U_0402_6.3V6K 2 1 C39 1U_0402_6.3V6K 2 1 C38 1U_0402_6.3V6K 2 1 C37 1U_0402_6.3V6K 2 1 C36 1U_0402_6.3V6K 1 C35 1U_0402_6.3V6K 1 2 D 1 2 6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue. C ESR <= 1.5m ohm Near CPU CORE regulator +VCC_CORE 2 C58 + 1 + 2 220U_D2_2VK_R9 1 220U_D2_2VK_R9 + 220U_D2_2VK_R9 1 2 Del C37 to improve power plan. 6/14 B +VCCP 2 1 2 C70 1U_0402_6.3V6K 2 1 C69 1U_0402_6.3V6K 2 1 C68 1U_0402_6.3V6K 2 1 C67 1U_0402_6.3V6K 2 1 C66 1U_0402_6.3V6K 2 1 C65 1U_0402_6.3V6K 2 1 C64 1U_0402_6.3V6K 2 1 C63 1U_0402_6.3V6K 2 1 C62 1U_0402_6.3V6K 2 1 C61 1U_0402_6.3V6K 1 C60 1U_0402_6.3V6K C59 1U_0402_6.3V6K 4 2 High Frequence Decoupling 1 2 A Compal Secret Data Security Classification 2009/04/20 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 1 C31 10U_0603_6.3V6M 1 C30 10U_0603_6.3V6M 2 C29 10U_0603_6.3V6M 1 C28 10U_0603_6.3V6M 2 C27 10U_0603_6.3V6M 1 C26 10U_0603_6.3V6M 2 C25 10U_0603_6.3V6M 1 C24 10U_0603_6.3V6M 2 C23 10U_0603_6.3V6M 1 C22 10U_0603_6.3V6M 2 C21 10U_0603_6.3V6M 1 C20 10U_0603_6.3V6M 2 +VCC_CORE Issued Date PENRYN SFF_UFCBGA956 1 C19 10U_0603_6.3V6M 2 C18 10U_0603_6.3V6M 1 C17 10U_0603_6.3V6M 2 C16 10U_0603_6.3V6M 1 C15 10U_0603_6.3V6M 2 C14 10U_0603_6.3V6M 1 C13 10U_0603_6.3V6M 2 C12 10U_0603_6.3V6M 1 1 Mid Frequence Decoupling +VCC_CORE C11 10U_0603_6.3V6M AA15 AC15 Y10 AD10 AH12 AE15 AG15 AJ15 AH10 AM12 AL15 AN15 AR15 AM10 AT12 AV12 AW13 AW11 AY12 AU15 AW15 AT10 BA13 BA11 BB12 BC11 BA15 BC15 B6 D6 E9 F6 G9 H6 K8 K6 M8 M6 P8 P6 T8 T6 V8 V6 U5 Y8 Y6 AB8 AB6 AD8 AD6 AF8 AF6 AH8 AH6 AK8 AK6 AM8 AM6 AP8 AP6 AT8 AT6 AU9 AV6 AU7 AW9 AY6 BA9 BB6 BC9 BD6 B4 C3 E3 G3 J3 L3 N3 R3 U3 W3 AA3 AC3 AE3 AG3 AJ3 AL3 AN3 AR3 AU3 AW3 BA3 BC3 D2 E1 G1 AW1 BA1 BB2 A41 A39 A29 A27 A31 A25 A23 A21 A19 A17 A11 A15 A7 A5 A9 BD4 C34 1U_0402_6.3V6K VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361 VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 C10 10U_0603_6.3V6M A VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 C33 1U_0402_6.3V6K PENRYN SFF_UFCBGA956 G25 G23 G21 J25 J23 J21 L25 L23 L21 N25 N23 N21 R25 R23 R21 U25 U23 U21 W25 W23 W21 AA25 AA23 AA21 AC25 AC23 AC21 AE25 AE23 AE21 AG25 AG23 AG21 AJ25 AJ23 AJ21 AL25 AL23 AL21 AN25 AN23 AN21 AR25 AR23 AR21 AU25 AU23 AU21 AW25 AW23 AW21 BA25 BA23 BA21 BC25 BC23 BC21 C17 C19 E19 E17 G19 G17 J19 J17 L19 L17 N19 N17 R19 R17 U19 U17 W19 W17 AA19 AA17 AC19 AC17 AE19 AE17 AG19 AG17 AJ19 AJ17 AL19 AL17 AN19 AN17 AR19 AR17 AU19 AU17 AW19 AW17 BA19 BA17 BC19 BC17 C11 C15 E15 G15 H10 M12 J15 L15 N15 M10 T12 R15 U15 W15 T10 Y12 AD12 C9 10U_0603_6.3V6M B AM36 AR35 AU35 AV34 AW35 AW33 AY34 AT36 AV36 BA33 BC33 BB36 BD36 C27 C29 C31 E29 E27 G29 G27 E31 G31 J29 J27 L29 L27 N29 N27 J31 L31 N31 R29 R27 U29 U27 R31 U31 W29 W27 W31 AA29 AA27 AC29 AC27 AA31 AC31 AE29 AE27 AG29 AG27 AJ29 AJ27 AE31 AG31 AJ31 AL29 AL27 AN29 AN27 AL31 AN31 AR29 AR27 AR31 AU29 AU27 AW29 AW27 AU31 AW31 BA29 BA27 BC29 BC27 BA31 BC31 C21 C23 C25 E25 E23 E21 C32 1U_0402_6.3V6K C U1E VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] C8 10U_0603_6.3V6M D VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] 2 C57 U1D B42 F44 D44 D42 F42 H42 K42 M42 P42 T42 V42 Y42 AB42 AD42 AF42 AH42 AK42 AM42 AP42 AY44 AV44 AT42 AV42 AY42 BA43 BB42 C39 E39 G37 H38 J39 L39 M38 N39 R39 T38 U39 W39 Y38 AA39 AC39 AD38 AE39 AG39 AH38 AJ39 AL39 AM38 AN39 AR39 AR37 AT38 AU39 AU37 AW39 AW37 BA39 BC41 BD40 BD38 B36 H34 D36 K34 M34 M36 P34 T34 V34 T36 Y34 AB34 AD34 Y36 AD36 AF34 AH34 AH36 AK34 AM34 AP34 3 C56 5 3 2 Title Compal Electronics, Inc. Penryn(3/3)-GND/Bypass Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 7 of 35 4 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 [5] [5] [5] [5] J13 L13 C13 G13 G15 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 [4] [4] [4] [4] [4] F4 F2 G7 H_RS#0 H_RS#1 H_RS#2 [4] [4] [4] 1 1 1 2 J35 F6 J39 L39 2 0_0402_5% AY39 2 100_0402_1% BB18 K28 K36 2 R57 10K_0402_1% C79 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR A7 A49 A52 A54 B54 D55 G55 BE55 BH55 BK55 BK54 BL54 BL52 BL49 BL7 BL4 BL2 BK2 BK1 BH1 BE1 G1 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 R62 1 2 10K_0402_5% PM_EXTTS#1 R63 1 2 10K_0402_5% DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB [14] [14] [15] [15] BK18 BK16 BE23 BC19 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# [14] [14] [15] [15] BJ17 BJ19 BC17 BE17 M_ODT0 M_ODT1 M_ODT2 M_ODT3 BL25 BK26 SMRCOMP SMRCOMP# R43 R44 BK32 BL31 SMRCOMP_VOH SMRCOMP_VOL BC51 AY37 BH20 BA37 DDR3_NB_REF SM_PWROK SM_REXT SM_DRAMRST# [14] [14] [15] [15] 0_0402_5% 1 R46 R47 1 1 +1.5V 2 80.6_0402_1% 2 80.6_0402_1% 1 1 R429 D 2 @ 1.5V_PGOOD [28] 2 10K_0402_1% 2 499_0402_1% SM_DRAMRST# [14,15] B42 D42 B50 D50 R49 P50 CLK_MCH_3GPLL [16] CLK_MCH_3GPLL# [16] AG55 AL49 AH54 AL47 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 [24] [24] [24] [24] AG53 AK50 AH52 AL45 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 [24] [24] [24] [24] AG49 AJ49 AJ47 AG47 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 [24] [24] [24] [24] AF50 AH50 AJ45 AG45 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 [24] [24] [24] [24] C G33 G37 F38 F36 G35 Modify in 9/26 GFX_VR_EN G39 +VCCP B CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF AK52 AK54 AW40 AL53 AL55 R52 1K_0402_1% CL_CLK0 [24] CL_DATA0 [24] M_PWROK [24] CL_RST# [24] CL_VREF DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN# HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC F34 F32 B38 A37 C31 K42 D10 T38 T39 0.1U_0402_16V4Z 1 R53 499_0402_1% 2 CLKREQ#_B [16] MCH_ICH_SYNC# TSATN# R58 1 2 54.9_0402_1% [24] +VCCP C29 B30 D28 A27 B28 A CANTIGA GMCH SFF_FCBGA1363 within 100 mils from NB Del R48. 9/27 Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 BC35 BE33 BE37 BC37 [14] [14] [15] [15] C76 +3VS PM_EXTTS#0 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 1 2 2 PEG_CLK PEG_CLK# CLK R49 R50 1 1 SM_VREF SM_PWROK SM_REXT SM_DRAMRST# 2 PM_EXTTS#0 PM_EXTTS#1 0_0402_5% +1.5V 0.1U_0402_16V4Z C77 K26 G23 G25 J25 L25 L27 F24 D24 D26 J23 B26 A23 C23 B24 B22 K24 C25 L23 L33 K32 K34 2 Place them close to U4 pin BC51. 2 Near B6 pin DDR CLK/ CONTROL/COMPENSATION 2 2 1 1 R51 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# R48 1K_0402_1% Add R428 in 9/26 1 0.1U_0402_16V4Z 1 C72 C74 2 0.01U_0402_25V7K 2 R54 10K_0402_1% 2 R61 1 [24] PM_BMBUSY# [5,23,31] H_DPRSTP# [14] PM_EXTTS#0 [15] PM_EXTTS#1 [24,26,31] PM_PWROK [17,22,26] PLT_RST# [4,23] H_THERMTRIP# [24,31] PM_DPRSLPVR layout note: 1 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 1 L3 M2 Y2 AF2 H_SWNG 1 221_0603_1% @ 100_0402_1% 1 24.9_0402_1% R60 2 0.1U_0402_16V4Z C78 R42 1K_0402_1% RSVD22 RSVD23 RSVD24 RSVD25 BA31 BC25 BC33 BB24 [14] [14] [15] [15] 2 [5] [5] [5] [5] R56 2 1 1K_0402_1% 2 1 R59 2K_0402_1% 2 A 2 BB20 BE19 BF20 BF18 NCT25 T26 T27 T28 RSVD20 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 1 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20. 1 AW42 +1.5V [16] MCH_CLKSEL0 [16] MCH_CLKSEL1 [16] MCH_CLKSEL2 T30 T31 [10] CFG5 [10] CFG6 [10] CFG7 T32 [10] CFG9 [10] CFG10 T33 [10] CFG12 [10] CFG13 T34 T35 [10] CFG16 T36 T37 [10] CFG19 [10] CFG20 DDR3_NB_REF H_RCOMP T24 RSVD17 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 BB32 BA25 BA33 BA23 2 K2 N3 AA3 AF4 SMRCOMP_VOL [5] [5] [5] [5] +VCCP H_VREF J9 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 DMI H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 +VCCP 1 T23 1 L9 N7 AA7 AG3 B R55 2 0.01U_0402_25V7K 2.2U_0603_6.3V4Z C71 H_ADS# [4] H_ADSTB#0 [4] H_ADSTB#1 [4] H_BNR# [4] H_BPRI# [4] H_BR0# [4] H_DEFER# [4] H_DBSY# [4] CLK_MCH_BCLK [16] CLK_MCH_BCLK# [16] H_DPWR# [5] H_DRDY# [4] H_HIT# [4] H_HITM# [4] H_LOCK# [4] H_TRDY# [4] layout note: Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20 2 T21 T22 R45 3.01K_0402_1% CANTIGA GMCH SFF_FCBGA1363 Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces 1 SMRCOMP_VOH H_AVREF H_DVREF Trace < = 500mils 1 TCK TDI TDO TMS HDA L17 K18 @ 1K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 1K_0402_5% 2 2 2 2 SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 GRAPHICS VID H_RS#_0 H_RS#_1 H_RS#_2 1 1 1 1 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 ME H_CPURST# H_CPUSLP# +3VS F10 A15 C19 C9 B8 C11 E5 D6 AH10 AJ11 G11 H2 C7 F8 A11 D8 1 MISC H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 R38 R39 R40 R41 C75 H_VREF H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_SWING H_RCOMP J11 G9 H_RESET# H_CPUSLP# H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 Add them for Boundary Scan. 10/23 J43 L43 J41 L41 AN11 AM10 AK10 AL11 F12 AN45 AP44 AT44 AN47 C27 D30 T12 T13 T14 T15 T16 T17 T18 T19 T20 PM B6 D4 H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 CFG H_SWNG H_RCOMP H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# L15 B14 C15 D12 F14 G17 B12 J15 D16 C17 D14 K16 F16 B16 C21 D18 J19 J21 B18 D22 G19 J17 L21 L19 G21 D20 K22 F18 K20 F20 F22 B20 A19 @ 0.1U_0402_16V4Z C H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 HOST D J7 H6 L11 J3 H4 G3 K10 K12 L1 M10 M6 N11 L7 K6 M4 K4 P6 W9 V6 V2 P10 W7 N9 P4 U9 V4 U1 W3 V10 U7 W11 U11 AC11 AC9 Y4 Y10 AB6 AA9 AB10 AA1 AC3 AC7 AD12 AB4 Y6 AD10 AA11 AB2 AD4 AE7 AD2 AD6 AE3 AG9 AG7 AE11 AK6 AF6 AJ9 AH6 AF12 AH4 AJ7 AE9 2 U3B [4] RSVD H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 [4] [5] 3 H_A#[3..35] U3A H_D#[0..63] 2.2U_0603_6.3V4Z C73 5 [5] 4 3 2 Title Compal Electronics, Inc. Cantiga(1/6)-AGTL/DMI/DDR Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 8 of 35 5 4 3 2 1 D D [15] DDR_B_D[0..63] B MEMORY SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 BH22 BK20 BL15 DDR_A_RAS# [14] DDR_A_CAS# [14] DDR_A_WE# [14] AT50 BB50 BB46 BE39 BB12 BE7 AV10 AR9 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 AR47 BA45 BE45 BC41 BC13 BB10 BA7 AN7 AR49 AW45 BC45 BA41 BA13 BA11 BA9 AN9 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 BC23 BF22 BE31 BC31 BH26 BJ35 BB34 BH32 BB26 BF32 BA21 BG25 BH34 BH18 BE25 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 U3E DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 [14] [14] [14] DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_DQS#[0..7] DDR_A_MA[0..14] [14] [14] [14] [14] CANTIGA GMCH SFF_FCBGA1363 AP54 AM52 AR55 AV54 AM54 AN53 AT52 AU53 AW53 AY52 BB52 BC53 AV52 AW55 BD52 BC55 BF54 BE51 BH48 BK48 BE53 BH52 BK46 BJ47 BL45 BJ45 BL41 BH44 BH46 BK44 BK40 BJ39 BK10 BH10 BK6 BH6 BJ9 BL11 BG5 BJ5 BG3 BF4 BD4 BA3 BE5 BF2 BB4 AY4 BA1 AP2 AU1 AT2 AT4 AV4 AU3 AR3 AN1 AP4 AL3 AJ1 AK4 AM4 AH2 AK2 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 B A SA_RAS# SA_CAS# SA_WE# BC21 BJ21 BJ41 MEMORY SA_BS_0 SA_BS_1 SA_BS_2 SYSTEM SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 DDR C AP46 AU47 AT46 AU49 AR45 AN49 AV50 AP50 AW47 BD50 AW49 BA49 BC49 AV46 BA47 AY50 BF46 BC47 BF50 BF48 BC43 BE49 BA43 BE47 BF42 BC39 BF44 BF40 BB40 BE43 BF38 BE41 BA15 BE11 BE15 BF14 BB14 BC15 BE13 BF16 BF10 BC11 BF8 BG7 BC7 BC9 BD6 BF12 AV6 BB6 AW7 AY6 AT10 AW11 AU11 AW9 AR11 AT6 AP6 AL7 AR7 AT12 AM6 AU7 SYSTEM U3D DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 DDR [14] DDR_A_D[0..63] SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 BJ13 BK12 BK38 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 BE21 BH14 BK14 [15] [15] [15] DDR_B_RAS# [15] DDR_B_CAS# [15] DDR_B_WE# [15] AP52 AY54 BJ49 BJ43 BH12 BD2 AY2 AJ3 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 AR53 BA53 BH50 BK42 BH8 BB2 AV2 AM2 AT54 BB54 BJ51 BH42 BK8 BC3 AW3 AN3 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 BJ15 BJ33 BH24 BA17 BF36 BH36 BF34 BK34 BJ37 BH40 BH16 BK36 BH38 BJ11 BL37 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_DM[0..7] DDR_B_DQS[0..7] DDR_B_DQS#[0..7] DDR_B_MA[0..14] [15] [15] [15] C [15] B CANTIGA GMCH SFF_FCBGA1363 A A Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Cantiga(2/6)-DDR2 A/B CH Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 9 of 35 5 4 3 2 1 Strap Pin Table U3C D G45 F46 G41 C45 F44 G47 F40 A45 B40 A41 F42 D48 D40 C41 G43 B48 C 1 1 1 2 2 2 75_0402_5% 75_0402_5% 75_0402_5% J27 E27 G27 F26 B34 D34 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3 TVA_DAC TVB_DAC TVC_DAC TV R68 R69 R70 L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDS B36 F50 H46 P44 K46 D46 B46 D44 B44 PEG_COMPI PEG_COMPO L_CTRL_DATA L_DDC_CLK L_DDC_DATA TVA_RTN TV_DCONSEL_0 TV_DCONSEL_1 Tie to GND. 9/28 J29 G29 E29 D36 C35 J33 D32 G31 CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC VGA F30 CRT_BLUE GRAPHICS L37 J37 L35 PEGCOMP trace width and spacing is 20/25 mils. L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK PCI-EXPRESS D38 C37 K38 PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 U45 T44 PEGCOMP 1 R64 +VCC_PEG 49.9_0402_1% D52 G49 K54 H50 M52 N49 P54 V46 Y50 V52 W49 AB54 AD46 AC55 AE49 AF54 E51 F48 J55 J49 M54 M50 P52 U47 AA49 V54 V50 AB52 AC47 AC53 AD50 AF52 L47 F52 P46 H54 L55 T46 R53 U49 T54 Y46 AB46 W53 Y54 AC49 AF46 AD54 J47 F54 N47 H52 L53 R47 R55 T50 T52 W47 AA47 W55 Y52 AB50 AE47 AD52 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15 000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved CFG[2:0] FSB Freq select 2 C500 C501 C502 C503 C504 C505 C506 C507 C508 C509 C510 C511 C512 C513 C514 C515 C516 C517 C518 C519 C520 C521 C522 C523 C524 C525 C526 C527 C528 C529 C530 C531 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N15 [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P15 [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K CFG[4:3] Reserved CFG5 (DMI select) 0 = DMI x 2 1 = DMI x 4 0 = The iTPM Host Interface is enable * CFG6 * 0 =(TLS)chiper suite with no confidentiality CFG7 (Intel Management Engine Crypto strap) 1 =(TLS)chiper suite with confidentiality [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15 [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] [17] * CFG8 Reserved CFG9 0 = Reverse Lane,15->0, 14->1 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order * 0 = Enable CFG10 (PCIE Lookback enable) PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15 D 1 = The iTPM Host Interface is disable 1 = Disable CFG11 Reserved CFG[13:12] (XOR/ALLZ) 00 01 10 11 CFG[15:14] Reserved CFG16 (FSB Dynamic ODT) 0 = Disabled * = Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation(Default) 1 = Enabled * C * CFG[18:17] Reserved CFG19 (DMI Lane Reversal) 0 = Normal Operation * (Lane number in Order) 1 = Reverse Lane CFG20 (PCIE/SDVO concurrent) CANTIGA GMCH SFF_FCBGA1363 B 0 = Only PCIE or SDVO is operational. * 1 = PCIE/SDVO are operating simu. [8] CFG5 [8] CFG6 [8] CFG7 [8] CFG9 [8] CFG10 [8] CFG12 [8] CFG13 [8] CFG16 R72 1 2 @ 2.21K_0402_1% R74 1 2 @ 2.21K_0402_1% R75 1 2 @ 2.21K_0402_1% R77 1 2 @ 2.21K_0402_1% R78 1 2 @ 2.21K_0402_1% R79 1 2 R80 1 2 @ 2.21K_0402_1% R81 1 2 @ 2.21K_0402_1% B @ 2.21K_0402_1% +3VS [8] CFG19 [8] CFG20 R82 1 2 @ 4.02K_0402_1% R83 1 2 @ 4.02K_0402_1% A A Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Cantiga(3/6)-VGA/LVDS/TV Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 10 of 35 5 4 3 2 1 +VCCP +V1.05VM_AXF R85 +VCCP 2 4.7U_0805_10V4Z C104 2 R90 0_0603_5% C84 330U_D2E_2.5VM_R9M C86 C88 0.1U_0402_16V4Z C103 1 VTT TV C85 CRT PLL VCCA_SM_NCTF_1 VCCA_SM_NCTF_2 VCCA_SM_NCTF_3 VCCA_SM_NCTF_4 VCCA_SM_NCTF_5 VCCA_SM_NCTF_6 VCCA_SM_NCTF_7 VCCA_SM_NCTF_8 VCCA_SM_NCTF_9 VCCA_SM_NCTF_10 2 1 2 2 2 +VCCP R95 2 M25 N24 M23 2 10U_0805_6.3V6M C107 0.1U_0402_16V4Z C106 VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 1 1 C 2 +V1.05VM_AXF +VCCP +VCC_PEG R99 VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4 VCCD_HPLL BK24 BL23 BJ23 BK22 +1.5V_SM_CK +3VS_HV VCC_TX_LVDS VCCA_SM_CK_4 VCCA_SM_CK_3 VCCA_SM_CK_2 VCCA_SM_CK_1 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8 VCC_HV_1 VCC_HV_2 VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 T41 +1.05VM_PEGPLL C33 A33 1 2 1 2 2 0_0805_5% 1 1 + 2 +VCCP L1 AB44 Y44 AC43 AA43 +VCC_PEG AM44 AN43 AL43 +1.05VM_DMI 1 2 BLM18PG121SN1D_0603 1 2 VCCD_PEG_PLL VCCD_LVDS_1 VCCD_LVDS_2 1 1 1 1 2 +1.05VM_DMI +VCCP 1 2 R101 1 2 0_0603_5% 1 B 2 +VCCP_D CANTIGA GMCH SFF_FCBGA1363 VTTLF1 VTTLF2 VTTLF3 K14 Y12 P2 It can be "no-stuff". 1 2 1 2 C130 0.47U_0603_10V7K For disable internal graphics. M46 L45 D 2 0_0805_5% 1 BLM18PG181SN1D_0603 C129 0.47U_0603_10V7K 0.1U_0402_16V4Z C126 2 1 2 +1.05VM_MPLL C128 0.47U_0603_10V7K 0.1U_0402_16V4Z C125 AE43 +1.05VM_PEGPLL 1 2 C124 0.1U_0402_16V4Z AH12 +1.05VM_HPLL 1 C123 10U_0805_10V4Z B POWER C122 0.1U_0402_16V4Z 2 +1.5VS_QDAC N32 C121 1 N34 0.1U_0402_16V4Z 2 C120 0.1U_0402_16V4Z C119 10U_0805_6.3V6M 1 AU27 AU28 AU29 AU31 AT31 AR31 AT29 AR29 AT28 AR28 AT27 AR27 +VCCP R93 1 C116 220U_D2_4VM_R15 2 0_0603_5% 1 +1.05VM_HPLL C118 10U_0805_6.3V6M R100 For HDMI Disable. 2 C117 4.7U_0805_10V4Z +1.05VM_A_SM_CK AT24 AR24 AT22 AR22 AT21 AR21 AT19 AR19 AT18 AR18 VCCD_QDAC VCCD_TVDAC AXF 2 VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_12 VCCA_SM_13 VCCA_SM_14 VCCA_SM_15 VCCA_SM_16 VCCA_SM_17 1 +1.5V R89 1 SM CK 2 1 C113 C110 100U_D2_6.3VM 2 1 1U_0603_10V4Z 1 4.7U_0805_10V4Z 2 2 0_0805_5% 10U_0805_6.3V6M + 1 C111 R97 1 VCCA_PEG_PLL A31 2 +1.5V_SM_CK BLM18PG181SN1D_0603 DMI +1.05VM_A_SM AW24 AU24 AW22 AU22 AU21 AW20 AU19 AW18 AU18 AW16 AU16 AT16 AR16 AU15 AT15 AR15 AW14 D TV/CRT HDA +1.05VM_PEGPLL AG43 2 +VCCP C VCCA_PEG_BG VCC_HDA 1 For ESD A SM 0.1U_0402_16V4Z AJ43 1 LVDS C105 VSSA_LVDS HV 2 0_0603_5% 1 C112 R94 +1.5VS VCCA_LVDS1 VCCA_LVDS2 PEG V44 2 0_0603_5% 1 2 K30 R92 0_0402_5% VTTLF U43 U41 A PEG A LVDS change 0.1U to 22U for wavy issue. 5/20 +1.5VS_PEG_BG VCCA_TV_DAC 1 2 C98 10U_0805_6.3V6M VCCA_MPLL @ 1 C97 0.1U_0402_16V4Z VCCA_HPLL 2 C99 10U_0805_6.3V6M AE1 2 + C1258 +1.05VM_MPLL VCCA_DPLLB 2 1 1 0.1U_0402_16V4Z AF10 2 1 4.7U_0805_10V4Z install 0.1U & 10U for wavy issue. 7/29 +1.05VM_HPLL VCCA_DPLLA 2 1 C87 4.7U_0805_10V4Z J45 L49 VCCA_DAC_BG VSSA_DAC_BG 1 2.2U_0805_16V4Z L31 M33 For disable internal graphics. D VCCA_CRT_DAC R13 T12 R11 T10 R9 T8 R7 T6 R5 T4 R3 T2 R1 0.47U_0603_10V7K J31 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 C82 10U_0805_10V4Z +VCCP U3H C83 1U_0603_10V4Z Change to 330u_R9, casue high limitation. 12/14 +VCCP 1 2 D1 R103 1 1 CH751H-40_SC76 2 10_0402_5% R104 1 2 0_0402_5% +3VS_HV +3VS 2 +1.5VS_QDAC +1.5VS R105 1 2 BLM18PG181SN1D_0603 1 C133 2 1 2 10U_0603_6.3V6M 2 C132 0.1U_0402_16V4Z C131 0.022U_0402_16V7K 1 4.7UF issues probabiliy. A A Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Cantiga(4/6)-PWR Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 11 of 35 5 4 3 2 1 U3G AT38 AR38 AN38 AM38 AL38 AG38 AE38 AA38 Y38 W38 U38 T38 R38 AT37 AR37 AN37 AM37 AL37 AJ37 AH37 AG37 AE37 AD37 AC37 AA37 Y37 W37 U37 T37 R37 AT35 AR35 U35 AT34 AR34 U34 T34 R34 6326.84mA For disable internal graphics VCC_AXG to GND. AJ16 AH16 AD16 AC16 AA16 U16 T16 R16 AM15 AL15 AJ15 AH15 AG15 AE15 AA15 Y15 W15 U15 T15 For disable internal graphics VCC_AXG_NCTFto GND. VCC GFX NCTF VCC SM B 1 2 1U_0603_10V4Z 2 1U_0603_10V4Z 2 1 C155 2 1 0.47U_0402_6.3V6K 2 1 0.22U_0603_10V7K VCC_AXG_SENSE VSS_AXG_SENSE 2 0.22U_0603_10V7K 2 1 C154 1 1 C153 VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7 C152 AU45 BF52 BB38 BA19 BE9 AU9 AL9 C151 VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7 0.1U_0402_16V4Z AG13 AE13 C 0.1U_0402_16V4Z T43 T44 D C157 PAD PAD VCC_AXG_62 VCC_AXG_63 VCC_AXG_64 VCC_AXG_65 VCC_AXG_66 VCC_AXG_67 VCC_AXG_68 VCC_AXG_69 VCC_AXG_70 VCC_AXG_71 VCC_AXG_72 VCC_AXG_73 VCC_AXG_74 VCC_AXG_75 VCC_AXG_76 VCC_AXG_77 VCC_AXG_78 VCC_AXG_79 VCC_AXG_80 T32 U31 T31 R31 U29 T29 R29 U28 U27 T27 R27 U25 T25 R25 U24 U22 T22 R22 U21 T21 R21 AM19 AL19 AH19 AG19 AE19 AD19 AC19 W19 U19 AM18 AL18 AJ18 AH18 AG18 AE18 AD18 AC18 AA18 Y18 W18 U18 T18 R18 C156 CANTIGA GMCH SFF_FCBGA1363 VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42 VCC_AXG_43 VCC_AXG_44 VCC_AXG_45 VCC_AXG_46 VCC_AXG_47 VCC_AXG_48 VCC_AXG_49 VCC_AXG_50 VCC_AXG_51 VCC_AXG_52 VCC_AXG_53 VCC_AXG_54 VCC_AXG_55 VCC_AXG_56 VCC_AXG_57 VCC_AXG_58 VCC_AXG_59 VCC_AXG_60 VCC_AXG_61 VCC GFX VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 W32 AG31 AE31 AD31 AC31 AA31 Y31 W31 AH29 AG29 AE29 AD29 AC29 AA29 Y29 W29 AH28 AG28 AE28 AA28 AH27 AG27 AE27 AD27 AC27 AA27 Y27 W27 AH25 AD25 AC25 W25 AJ24 AH24 AG24 AE24 AD24 AC24 AA24 Y24 W24 AM22 AL22 AJ22 AH22 AG22 AE22 AD22 AC22 AA22 AM21 AL21 AJ21 AH21 AD21 AC21 AA21 Y21 W21 AM16 AL16 VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC SM LF B VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 POWER Y34 W34 AM32 AL32 AJ32 AH32 AE32 AD32 AA32 AM31 AL31 AJ31 AH31 AM29 AL29 AM28 AL28 AJ28 AM27 AL27 AM25 AL25 AJ25 AM24 N36 VCC_35 VCC_36 1 +VCCP VCC NCTF AC34 AA34 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 2 2 VCC CORE AJ40 AH40 AG40 AE40 AD40 AC40 AA40 Y40 AN35 AM35 AJ35 AH35 AD35 AC35 W35 AM34 AL34 AJ34 AH34 AG34 AE34 AD34 2 1 C140 2 2 1 0.01U_0402_16V7K C139 2 1 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 + 10U_0805_6.3V6M C138 C 2 1 C145 2 1 0.1U_0402_16V4Z C144 1 0.22U_0402_10V4Z C143 2 0.22U_0402_10V4Z C142 + 10U_0805_6.3V6M C141 220U_D2_4VM_R15 1 AT41 AR41 AN41 AJ41 AH41 AD41 AC41 Y41 W41 AT40 AM40 AL40 1 10U_0805_6.3V6M C137 330U_D2E_2.5VM_R9 +VCCP D VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC GFX +1.5V U3F BB36 BE35 AW34 AW32 BK30 BH30 BF30 BD30 BB30 AW30 BL29 BJ29 BG29 BE29 BC29 BA29 AY29 BK28 BH28 BF28 BD28 BB28 BL27 BJ27 BG27 BE27 BC27 BA27 AY27 AW26 BF24 BL19 BB16 POWER 3000mA Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA A A CANTIGA GMCH SFF_FCBGA1363 Compal Secret Data Security Classification Issued Date 2009/04/20 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Cantiga(5/6)-PWR/GND Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 12 of 35 5 4 3 2 1 U3I B VSS VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 U3J C43 A43 BD42 H42 BG41 AY41 AU41 AM41 AL41 AG41 AE41 AA41 R41 M41 E41 BD40 AU40 AR40 AN40 W40 U40 T40 R40 K40 H40 BL39 BG39 BA39 E39 C39 A39 BD38 AU38 H38 BG37 AU37 M37 E37 BD36 AW36 H36 BL35 BG35 AY35 AU35 AL35 AG35 AE35 AA35 Y35 M35 E35 A35 BD34 AU34 AN34 H34 BL33 BG33 AY33 E33 BD32 AU32 AN32 AG32 AC32 Y32 H32 B32 BJ31 BG31 AY31 AN31 M31 E31 N30 H30 AN29 AJ29 M29 A29 AW28 AN28 AD28 AC28 Y28 W28 H28 F28 AN27 AJ27 M27 BF26 BD26 N26 H26 BJ25 AY25 AU25 AN25 AG25 AE25 AA25 Y25 E25 A25 BD24 AN24 AL24 H24 BG23 AY23 E23 BD22 BB22 AN22 Y22 W22 H22 BL21 BG21 AY21 AN21 AG21 AE21 M21 E21 A21 BD20 H20 BG19 AY19 M19 E19 BD18 N18 H18 BL17 BG17 AY17 M17 E17 A17 BD16 AN16 AG16 AE16 Y16 W16 N16 H16 BG15 AY15 AN15 AD15 AC15 R15 M15 E15 BD14 H14 BL13 BG13 AY13 AU13 AR13 AJ13 AC13 AA13 W13 U13 M13 E13 A13 BD12 AV12 AP12 AM12 AK12 AB12 V12 P12 H12 BG11 AG11 E11 BD10 AY10 AP10 H10 BL9 BG9 E9 A9 BD8 BB8 AY8 AV8 AT8 AP8 CANTIGA GMCH SFF_FCBGA1363 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 AM8 AK8 AH8 AF8 AD8 AB8 Y8 V8 P8 M8 K8 H8 BJ7 E7 BF6 BC5 BA5 AW5 AU5 AR5 AN5 AL5 AJ5 AG5 AE5 AC5 AA5 W5 U5 N5 L5 J5 G5 C5 BH4 BE3 U3 E3 BC1 AW1 AR1 AL1 AG1 AC1 W1 N1 J1 AU43 BB42 AW38 BA35 L29 N28 N22 N20 N14 AL13 B10 AN13 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS D C N42 N40 N38 M39 VSS_359 VSS_360 VSS_361 VSS_362 VSS NCTF C VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 AJ38 AH38 AD38 AC38 T35 R35 AT32 AR32 U32 R32 T28 R28 AT25 AR25 T24 R24 AN19 AJ19 AA19 Y19 T19 R19 AN18 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS SCB D BA55 AU55 AN55 AJ55 AE55 AA55 U55 N55 BD54 BG53 AJ53 AE53 AA53 U53 N53 J53 G53 E53 K52 BG51 BA51 AW51 AU51 AR51 AN51 AL51 AJ51 AG51 AE51 AC51 AA51 W51 U51 R51 N51 L51 J51 G51 C51 BK50 AM50 K50 BG49 E49 C49 BD48 BB48 AY48 AV48 AT48 AP48 AM48 AK48 AH48 AF48 AD48 AB48 Y48 V48 T48 P48 M48 K48 H48 BL47 BG47 E47 C47 A47 BD46 AY46 AM46 AK46 AH46 BG45 AE45 AC45 AA45 W45 R45 N45 E45 BD44 BB44 AV44 AK44 AH44 AF44 AD44 K44 H44 BL43 BG43 AY43 AR43 W43 R43 M43 E43 B BL55 BL1 A55 D1 B55 B2 A4 VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 VSS_SCB_6 VSS_SCB_7 CANTIGA GMCH SFF_FCBGA1363 A A Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Cantiga(6/6)-PWR/GND Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 13 of 35 5 4 3 2 1 +V_DDR3_DIMM_REF +1.5V +1.5V [9] DDR_A_DQS#[0..7] JP3 [9] DDR_A_D[0..63] +1.5V DDR_A_D0 DDR_A_D1 [9] DDR_A_DM[0..7] 1 [9] DDR_A_DQS[0..7] DDR_A_DM0 R431 100_0402_1% D +V_DDR3_DIMM_REF DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 1 [15] +V_DDR3_DIMM_REF +V_DDR3_DIMM_REF 2 [9] DDR_A_MA[0..14] R432 100_0402_1% 1 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 2 C600 0.1U_0402_16V4Z 2 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 Layout Note: Place near JP4 C DDR_CKE0_DIMMA [8] DDR_CKE0_DIMMA DDR_A_BS2 [9] DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 Layout Note: Place these 4 Caps near Command and Control signals of DIMMA DDR_A_MA8 DDR_A_MA5 +1.5V 2 C607 C606 C605 C604 C603 1 2 1 2 1 1 2 C611 1 C610 2 0.1U_0402_16V4Z 1 C609 2 0.1U_0402_16V4Z 1 C608 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 2 10U_0805_6.3V6M 1 10U_0805_6.3V6M 2 10U_0805_6.3V6M 1 10U_0805_6.3V6M 2 10U_0805_6.3V6M 1 10U_0805_6.3V6M C602 DDR_A_MA3 DDR_A_MA1 + 2 C601 470U_D2_2.5VM_R15 @ M_CLK_DDR0 M_CLK_DDR#0 [8] M_CLK_DDR0 [8] M_CLK_DDR#0 DDR_A_MA10 DDR_A_BS0 [9] DDR_A_BS0 DDR_A_WE# DDR_A_CAS# [9] DDR_A_WE# [9] DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMA# [8] DDR_CS1_DIMMA# DDR_A_D40 DDR_A_D41 1 DDR_A_D42 DDR_A_D43 2 DDR_A_D48 DDR_A_D49 C618 1 10U_0805_6.3V6M 1 2 C617 1 2 1U_0603_10V4Z C616 2 1U_0603_10V4Z C615 1 1U_0603_10V4Z C614 1U_0603_10V4Z 2 DDR_A_DM5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 1 R434 2 10K_0402_5% C619 2.2U_0603_6.3V4Z 2 2 C620 0.1U_0402_16V4Z 1 1 205 G2 2009/04/20 DDR_A_DM1 SM_DRAMRST# 4 3 SM_DRAMRST# [8,15] DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDR_CKE1_DIMMA DDR_CKE1_DIMMA [8] C DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 M_ODT1 M_CLK_DDR1 [8] M_CLK_DDR#1 [8] DDR_A_BS1 [9] DDR_A_RAS# [9] DDR_CS0_DIMMA# M_ODT0 [8] M_ODT1 [8] [8] +V_DDR3_DIMM_REF R433 DDR_VREF_CA_DIMMA DDR_A_D36 DDR_A_D37 1 2 0_0402_5% DDR_A_DM4 DDR_A_D38 DDR_A_D39 1 2 1 2 B DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 PM_EXTTS#0 CLK_SMBDATA CLK_SMBCLK PM_EXTTS#0 [8] ICH_SMBDATA [15,16,24,26] ICH_SMBCLK [15,16,24,26] +0.75VS A 206 +0.75VS 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 D DDR_A_D12 DDR_A_D13 Compal Secret Data Security Classification Issued Date G1 DDR_A_D6 DDR_A_D7 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 FOX_AS0A626-U4SN-7F ME@ 2 A 1 R435 10K_0402_5% +3VS DDR_A_DQS#0 DDR_A_DQS0 C613 +0.75VS CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 DDR_A_D4 DDR_A_D5 C612 DDR_A_D34 DDR_A_D35 B CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 0.1U_0402_16V4Z DDR_A_DQS#4 DDR_A_DQS4 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 2.2U_0805_16V4Z DDR_A_D32 DDR_A_D33 Layout Note: Place near JP4.203 & JP4.204 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 DDR3 SO-DIMM A Standard 4.2mm Compal Electronics, Inc. Title DDR3-SODIMM SLOT1 Size Document Number Custom Date: Rev 0.3 LS-5588 Wednesday, July 01, 2009 Sheet 1 14 of 35 5 4 3 2 +1.5V [9] DDR_B_D[0..63] [9] DDR_B_DM[0..7] DDR_B_D0 DDR_B_D1 [9] DDR_B_DQS[0..7] DDR_B_DM0 [9] DDR_B_MA[0..14] DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 D DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 Layout Note: Place near JP5 DDR_B_D24 DDR_B_D25 Layout Note: Place these 4 Caps near Command and Control signals of DIMMA DDR_B_DM3 DDR_B_D26 DDR_B_D27 C627 C626 C625 C624 C623 1 1 C631 2 C630 1 0.1U_0402_16V4Z 2 C629 1 0.1U_0402_16V4Z 2 C628 1 0.1U_0402_16V4Z 2 10U_0805_6.3V6M 2 1 0.1U_0402_16V4Z 2 1 10U_0805_6.3V6M 2 1 10U_0805_6.3V6M 2 1 10U_0805_6.3V6M 2 10U_0805_6.3V6M C 10U_0805_6.3V6M C622 +1.5V 1 2 + 2 C621 470U_D2_2.5VM_R15 @ DDR_CKE2_DIMMB [8] DDR_CKE2_DIMMB DDR_B_BS2 [9] DDR_B_BS2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 Layout Note: Place near JP5.203 & JP5.204 M_CLK_DDR2 M_CLK_DDR#2 [8] M_CLK_DDR2 [8] M_CLK_DDR#2 DDR_B_MA10 DDR_B_BS0 [9] DDR_B_BS0 2 2 1 DDR_B_MA13 DDR_CS3_DIMMB# [8] DDR_CS3_DIMMB# 1 2 DDR_B_D32 DDR_B_D33 C636 1 10U_0805_6.3V6M C635 1 1U_0603_10V4Z C634 2 1U_0603_10V4Z C633 1U_0603_10V4Z C632 1U_0603_10V4Z 1 DDR_B_WE# DDR_B_CAS# [9] DDR_B_WE# [9] DDR_B_CAS# +0.75VS 2 +1.5V JP4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 [14] +V_DDR3_DIMM_REF 1 1 +V_DDR3_DIMM_REF [9] DDR_B_DQS#[0..7] DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 B DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DM7 DDR_B_D58 DDR_B_D59 1 2 R437 10K_0402_5% +3VS 1 R438 10K_0402_5% 1 C639 0.1U_0402_16V4Z A 2 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 2 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 G1 G2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 D DDR_B_DM1 SM_DRAMRST# SM_DRAMRST# DDR_B_D20 DDR_B_D21 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 DDR_CKE3_DIMMB DDR_CKE3_DIMMB 2009/04/20 C DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 M_CLK_DDR3 [8] M_CLK_DDR#3 [8] DDR_B_BS1 DDR_B_RAS# DDR_B_BS1 [9] DDR_B_RAS# [9] DDR_CS2_DIMMB# M_ODT2 DDR_CS2_DIMMB# M_ODT2 [8] 3 [8] +V_DDR3_DIMM_REF M_ODT3 M_ODT3 DDR_VREF_CA_DIMMB R436 1 DDR_B_D36 DDR_B_D37 [8] 2 0_0402_5% 1 2 DDR_B_DM4 1 C637 0.1U_0402_16V4Z 2 C638 2.2U_0805_16V4Z DDR_B_D38 DDR_B_D39 B DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 PM_EXTTS#1 CLK_SMBDATA CLK_SMBCLK PM_EXTTS#1 [8] ICH_SMBDATA [14,16,24,26] ICH_SMBCLK [14,16,24,26] +0.75VS 206 A +0.75VS DDR3 SO-DIMM B Reverse 4.0mm 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 [8] DDR_B_MA14 Compal Secret Data Security Classification 5 [8,14] DDR_B_D14 DDR_B_D15 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 FOX_AS0A626-U4RN-7F ME@ Issued Date DDR_B_D4 DDR_B_D5 2 Title Compal Electronics, Inc. DDR3-SODIMM SLOT2 Size Document Number Rev 0.3 LS-5588 Date: Wednesday, July 01, 2009 Sheet 1 15 of 35 0 0 1 0 1 0 266 200 1 100 1066 100 800 166 33.3 100 667 0_1206_5% 33.3 R122 33.3 1 2 1 2 1 2 1 2 1 2 1 2 C212 2 1 C213 1 2 CLK_48M_ICH @ 5P_0402_50V8C CLK_14M_ICH @ 12P_0402_50V8J 1 CLK_PCI_ICH @ 4.7P_0402_50V8C C214 2 C229 2 2 0_1206_5% 1 2 1 2 1 2 1 2 1 2 0.1U_0402_16V4Z C228 0 1 10U_0805_10V4Z C216 R121 0 2 0.1U_0402_16V4Z C227 1 10U_0805_10V4Z C226 PCI MHz 0.1U_0402_16V4Z C225 SRC MHz 1 +1.05VM_CK505 10U_0805_10V4Z C223 FSB MHz 0.1U_0402_16V4Z C222 CPU MHz 0.1U_0402_16V4Z C221 CLKSEL0 0.1U_0402_16V4Z C220 FSLA CLKSEL1 0.1U_0402_16V4Z C219 FSLB CLKSEL2 2 +VCCP 0.1U_0402_16V4Z C218 FSLC 3 +3VM_CK505 +3VS 0.1U_0402_16V4Z C224 4 0.1U_0402_16V4Z C217 5 1 2 1 CLK_PCI_EC @ 4.7P_0402_50V8C 1 2 D D +VCCP 2 Place close to U5 R123 @ 56_0402_5% R124 1 1 CLKREQ#_B_R CLKREQG_WWAN#_R FSA 2 1 R130 1 CPU_BSEL0 2 R131 MCH_CLKSEL0 1K_0402_5% 1 475_0402_1% 1 475_0402_1% R132 1 R134 2 10K_0402_5% R125 1 6 12 19 23 27 55 72 9/14 2 +1.05VM_CK505 VDDREF VDDPCI VDD48 VDD96_IO VDDPLL3 VDDSRC VDDCPU SCLK SDATA CPUT0_LPR_F CPUC0_LPR_F 31 38 52 62 66 2 C R136 @ 1K_0402_5% 1 1 MCH_CLKSEL1 2 R138 0_0402_5% CPUT1_LPR_F CPUC1_LPR_F CR7# CPUT2_ITP_LPR/SRCT8_LPR CPUC2_ITP_LPR/SRCC8_LPR 2 SRCT7_LPR SRCC7_LPR [8] [26] CLK_PCI_EC CLK_PCI_EC 33_0402_1% 2 R142 1 1 1 CPU_BSEL1 VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO R137 1K_0402_5% FSB PCI_CLK1 13 PCI2_TME 14 R141 @ 0_0402_5% 15 PCI CR#6 PCI2/TME SRCT6_LPR SRCC6_LPR PCI3 2 CR10# [22] CLK_PCI_ICH CLK_PCI_ICH 33_0402_1% 2 R145 1 27_SEL 16 ITP_EN 17 CLK_XTAL_IN CLK_XTAL_OUT 5 4 SRCT10_LPR SRCC10_LPR PCI4/27_Select PCI_F5/ITP_EN CR#11 SRCT11_LPR SRCC11_LPR X1 CR#9 X2 SRCT9_LPR SRCC9_LPR FSC 2 +3VS CLKREQ_WLAN# [26] CLKSATAREQ# [24] R133 1 NC +VCCP 9/20 R146 1 1 10K_0402_5% 1 CPU_BSEL2 2 10K_0402_5% 475_0402_1% 475_0402_1% 2 10K_0402_5% +3VS U4 +1.05VM_CK505 R148 R147 2 1K_0402_5% MCH_CLKSEL2 [8] CR#4 2 0_0402_5% CLK_48M_ICH [24] CLK_48M_ICH [26] CLK_48M_CR 1 [5] 1 1 +3VS PCI_STOP# CPU_STOP# B R128 2 R129 2 0_0402_5% R135 @ 1K_0402_5% [5] CLKREQ_WLAN#_R CLKSATAREQ#_R [26] Modify PN directly, from SA00001YJ20(HP) to SA000020H10(General) +3VM_CK505 2 +3VS CLKREQ#_B [8] CLKREQG_WWAN# [8] 1 [5] 1 2.2K_0402_5% R126 2 R127 2 2 10K_0402_5% 15_0402_1% 15_0402_1% 1 1 FSA 2 R149 2 R177 R150 0_0402_5% FSB CLK_14M_ICH 2 [24] CLK_14M_ICH 33_0402_1% 1 2 R151 FSC 20 2 7 SRCT4_LPR SRCC4_LPR USB_48MHz/FSLA CR#3 FSLB/TEST_MODE SRCT3_LPR SRCC3_LPR 11 10 9 ICH_SMBCLK [14,15,24,26] ICH_SMBDATA [14,15,24,26] 54 53 H_STP_PCI# [24] H_STP_CPU# [24] 71 70 CLK_CPU_BCLK [4] CLK_CPU_BCLK# [4] 68 67 65 CLK_MCH_BCLK [8] CLK_MCH_BCLK# [8] C CLKREQ#_B_R 64 63 61 60 CLK_MCH_3GPLL CLK_MCH_3GPLL# VGA_CLK_REQ# 58 57 56 [8] [8] VGA_CLK_REQ# CLK_PCIE_VGA CLK_PCIE_VGA# [18] [17] [17] CLKREQ_WLAN#_R 49 50 51 CLK_PCIE_MCARD CLK_PCIE_MCARD# [26] [26] CLKREQG_WWAN#_R 46 48 47 CLK_PCIE_WAN CLK_PCIE_WAN# [26] [26] 43 44 45 41 CLKREQA# 39 40 [26] CLK_PCIE_LAN CLK_PCIE_LAN# B [26] [26] 37 RP28 R_PCIE_ICH R_PCIE_ICH# 35 36 0_0404_4P2R_5% 1 2 4 3 CLK_PCIE_ICH CLK_PCIE_ICH# [24] [24] FSLC/TEST_SEL/REF0 Install. 11/06 SRCT2_LPR/SATAT_LPR SRCC2_LPR/SATAC_LPR 59 18 +3VS +3VS 26 +3VS CLK_XTAL_IN R153 10K_0402_5% 2 2 2 30 R154 10K_0402_5% 69 R155 10K_0402_5% 34 1 42 1 1 1 C234 22P_0402_50V8J R156 @ 10K_0402_5% @ PCI2_TME 3 R157 10K_0402_5% GNDPCI 27MHz_NonSS/SRCT1_LPR/SE1 27MHz_SS/SRCC1_LPR/SE2 CLK_PCIE_SATA [23] CLK_PCIE_SATA# [23] 24 25 28 29 27M_NSSC [18] 27M_SSC [18] GND48 GND CK_PWRGD/PD# 1 CK_PWRGD GNDCPU CR#A CLKSATAREQ#_R 21 GNDSRC GNDSRC REF1 GNDREF T_PAD 8 A 73 R158 @10K_0402_5% 2009/04/20 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 5 [24] GND ICS9LPRS387BKLFT MLF 72P 2 2 2 2 27_SEL 2 ITP_EN 1 2 1 1 Y1 1 C233 22P_0402_50V8J CLK_XTAL_OUT 1 14.31818MHZ_20P_1BX14318BE1A A 22 SRCT0_LPR/DOTT_96_LPR SRCC0_LPR/DOTC_96_LPR GNDSRC 32 33 2 Title CLOCK GENERATOR Size Document Number Rev 0.3 LS-5588 Date: Wednesday, July 01, 2009 Sheet 1 16 of 35 5 4 3 2 PCIE_MTX_C_GRX_P[0..15] [10] PCIE_MTX_C_GRX_P[0..15] ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET PCIE_GTX_C_MRX_N[0..15] [10] PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15] [10] PCIE_GTX_C_MRX_P[0..15] STRAPS U64A PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0 D AF30 AE31 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1 AE29 AD28 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 AD30 AC31 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N3 AC29 AB28 1 CONFIGURATION STRAPS PCIE_MTX_C_GRX_N[0..15] [10] PCIE_MTX_C_GRX_N[0..15] PCIE_RX0P PCIE_RX0N PCIE_TX0P PCIE_TX0N PCIE_RX1P PCIE_RX1N PCIE_TX1P PCIE_TX1N PCIE_RX2P PCIE_RX2N PCIE_TX2P PCIE_TX2N PCIE_RX3P PCIE_RX3N PCIE_TX3P PCIE_TX3N AH30 AG31 PCIE_GTX_MRX_P0 PCIE_GTX_MRX_N0 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 C1046 C1047 1 1 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_N0 AG29 AF28 PCIE_GTX_MRX_P1 PCIE_GTX_MRX_N1 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 C1048 C1049 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N1 AF27 AF26 PCIE_GTX_MRX_P2 PCIE_GTX_MRX_N2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 C1050 C1051 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N2 AD27 AD26 PCIE_GTX_MRX_P3 PCIE_GTX_MRX_N3 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 C1052 C1053 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N3 DESCRIPTION OF DEFAULT SETTINGS RECOMMENDED SETTINGS TX_PWRS_ENB GPIO0 PIN PCIE FULL TX OUTPUT SWING 1 TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 1 BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 1 BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0 BIF_VGA DIS GPIO9 VGA ENABLED 0 D 0 +3.3V_DELAY C W29 V28 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8 V30 U31 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 U29 T28 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10 T30 R31 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 R29 P28 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12 P30 N31 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13 N29 M28 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14 M30 L31 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15 L29 K30 B PCIE_RX7P PCIE_RX7N PCIE_RX8P PCIE_RX8N PCIE_RX9P PCIE_RX9N PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_RX12P PCIE_RX12N 2 2 1 1 C1054 C1055 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N4 PCIE_TX5P PCIE_TX5N Y23 Y24 PCIE_GTX_MRX_P5 PCIE_GTX_MRX_N5 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 C1056 C1057 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N5 AB27 AB26 PCIE_GTX_MRX_P6 PCIE_GTX_MRX_N6 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 C1058 C1059 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6 ROMIDCFG(2:0) PCIE_TX6P PCIE_TX6N R948 10K_0402_5% +3VS SMS_EN_HARD Y27 Y26 PCIE_GTX_MRX_P7 PCIE_GTX_MRX_N7 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 C1060 C1061 1 1 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N7 EC_SMB_CK2_PX PCIE_TX8P PCIE_TX8N W24 W23 PCIE_GTX_MRX_P8 PCIE_GTX_MRX_N8 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 C1062 C1063 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N8 V27 U26 PCIE_GTX_MRX_P9 PCIE_GTX_MRX_N9 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 C1064 C1065 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N9 PCIE_TX10P PCIE_TX10N U24 U23 PCIE_GTX_MRX_P10 PCIE_GTX_MRX_N10 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 C1066 PCIE_GTX_C_MRX_P10 C1067 PCIE_GTX_C_MRX_N10 PCIE_TX11P PCIE_TX11N 6 1 Q75A 2N7002DW-T/R7_SOT363-6 PCIE_TX12P PCIE_TX12N PCIE_RX13P PCIE_RX13N PCIE_TX13P PCIE_TX13N PCIE_RX14P PCIE_RX14N PCIE_TX14P PCIE_TX14N PCIE_RX15P PCIE_RX15N PCIE_TX15P PCIE_TX15N 3 PCIE_GTX_MRX_P11 PCIE_GTX_MRX_N11 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 AK30 AK32 L9 N9 N10 PAD T77 PCIE_CALRP PCIE_CALRN [4,26] 4 EC_SMB_DA2 [4,26] AUD[1] HSYNC PCIE_GTX_MRX_P12 PCIE_GTX_MRX_N12 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 C1071 PCIE_GTX_C_MRX_P12 C1072 PCIE_GTX_C_MRX_N12 P27 P26 PCIE_GTX_MRX_P13 PCIE_GTX_MRX_N13 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 C1073 PCIE_GTX_C_MRX_P13 C1074 PCIE_GTX_C_MRX_N13 P24 P23 PCIE_GTX_MRX_P14 PCIE_GTX_MRX_N14 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 C1075 PCIE_GTX_C_MRX_P14 C1076 PCIE_GTX_C_MRX_N14 M27 N26 PCIE_GTX_MRX_P15 PCIE_GTX_MRX_N15 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 C1077 PCIE_GTX_C_MRX_P15 C1078 PCIE_GTX_C_MRX_N15 AUD[0] VSYNC R864 1 2 1.27K_0402_1% AA22 R865 1 2 GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 SOUT_GPIO8 [18] GPU_GPIO9 [18] GPU_GPIO11 [18] GPU_GPIO12 [18] GPU_GPIO13 GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 SOUT_GPIO8 R936 R937 R938 R939 2 2 2 @ 2 @ GPU_GPIO9 GPU_GPIO11 GPU_GPIO12 GPU_GPIO13 R940 R941 R942 R943 2 2 2 @ 2 1 1 1 1 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% PLT_RST# PLT_RST# 1 2 0_0402_5% AL27 PERSTB 216-0728002 A11 M92-S2_FCBGA631 1 2 R347 1 1 1 1 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 1 1 1 1 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% @ @ GPIO_28_TDO R944 R945 R946 R947 [18,26] CRT_VSYNC [18,26] CRT_HSYNC [18] VSYNC_DAC2 [18] HSYNC_DAC2 2 2 2 2 @ B TEST PIN GPU M92 S2-XT +3.3V_DELAY VRAM_ID[2:0] C1372 0.1U_0402_16V4Z GPIO21_BB_EN @ @ +1.1VS Closed to GPU GENERICC @ @ VGA Thermal Sensor ADM1032ARMZ-2 NOTE: Change part number directly, from SA00002ZM10 to SA000030O20 M92XT -> LP, 2009/05/20 10K_0402_5% C PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET R892 [8,22,26] XX AMD RESERVED CONFIGURATION STRAPS STRAPS 2K_0402_1% 0 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET +3.3V_DELAY GPIO5_AC_BATT VSYNC_DAC1 and HSYNC_DAC1 pull up to HDMI & DISPLAYPORT AUDIO funciton Y22 0 AUD[1] AUD[0] 0 0 No audio function 0 1 Audio for DisplayPort and HDMI if dongle is detected 1 0 Audio for DisplayPort only 1 1 Audio for both DisplayPort and HDMI H2SYNC T24 T23 [18] [18] [18] [18] PCIE_REFCLKP PCIE_REFCLKN NC#1 NC#2 NC_PWRGOOD SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT GENERICC C1069 PCIE_GTX_C_MRX_P11 C1070 PCIE_GTX_C_MRX_N11 1 1 CALIBRATION For Future ASIC Pin N10 need pull down H2SYNC Q75B 2N7002DW-T/R7_SOT363-6 CLOCK CLK_PCIE_VGA CLK_PCIE_VGA# [16] CLK_PCIE_VGA [16] CLK_PCIE_VGA# EC_SMB_CK2 STRAPS T26 T27 0 0 0 ENABLE EXTERNAL BIOS ROM IGNORE VIP DEVICE STRAPS EC_SMB_DA2_PX PCIE_TX9P PCIE_TX9N BIF_RX_PLL_CALIB_BP V2SYNC R949 10K_0402_5% CCBYPASS PCIE_TX7P PCIE_TX7N 1 GPIO[13:11] VIP_DEVICE_STRAP_ENA 5 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 PCIE_RX6P PCIE_RX6N 0.1U_0402_16V7K 0.1U_0402_16V7K GPIO_22_ROMCSB 2 Y30 W31 PCIE_GTX_MRX_P4 PCIE_GTX_MRX_N4 1 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 PCIE_RX5P PCIE_RX5N AC25 AB25 2 AA29 Y28 PCIE_TX4P PCIE_TX4N 1 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5 PCIE_RX4P PCIE_RX4N BIOS_ROM_EN 2 AB30 AA31 PCI EXPRESS INTERFACE PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 GPIO21 BIF_RX_PLL_CALIB_BP Project VRAM size Vendor Part Number# JM51_PU 512MB(x4) Samsung 64Mx16x4 DDR3 JM51_PU 256MB(X2) Samsung 64Mx16x2 DDR3 JM51_PU 512MB(x4) Hynix 64Mx16x4 DDR3 JM51_PU 256MB(X2) Hynix 64Mx16x2 DDR3 Compal Part Number# VRAM_ID 2,1,0 SA000035700 100 101 SA000032400 000 010 DVPDATA 3.2.1 2 1 U69 1 2 [18] GPU_THERMAL_D+ C1371 1 2 2200P_0402_50V7K [18] GPU_THERMAL_D- 3 4 VDD SCLK D+ SDATA D- ALERT# THERM# GND A 8 EC_SMB_CK2_PX 7 EC_SMB_DA2_PX 6 THM_ALERT# 1 ADM1032ARMZ REEL_MSOP8 [18] +3.3V_DELAY 5 R950 A 2 4.7K_0402_5% +3.3V_DELAY 1 R951 2 4.7K_0402_5% Compal Secret Data Security Classification Issued Date 2009/04/20 Deciphered Date 2010/04/30 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. M92-S2 PCIE,STRAP Size Document Number Custom Date: Rev 0.3 LS-5588 Wednesday, July 01, 2009 1 Sheet 17 of 35 5 4 +1.8VS 2 1 @ 10K_0402_5% @ 10K_0402_5% 1 R953 1 R954 VRAM_ID1 2 VRAM_ID2 2 @ 10K_0402_5% VRAM_ID0 VRAM_ID1 VRAM_ID2 +3.3V_DELAY D DDC2_CLK 2 4.7K_0402_5% 1 R871 DDC2_DATA 2 4.7K_0402_5% 1 R873 VGA_PWRSEL0 1 10K_0402_5% 2 R875 CRT_DDC_CLK 2 4.7K_0402_5% 1 R878 CRT_DDC_DATA 2 4.7K_0402_5% 1 R893 HDMI_SCL 2 4.7K_0402_5% 1 R894 1 @ [26] DDC2_CLK [26] DDC2_DATA GPIO23_CLKREQB 1 10K_0402_5% @ GPIO24_TRSTB 10K_0402_5% @ ROMSE_GPIO22 1 10K_0402_5% 2 R905 1 R890 TXCAP_DPA3P TXCAM_DPA3N DPA TX2P_DPA0P TX2M_DPA0N TXCBP_DPB3P TXCBM_DPB3N DPB TX3P_DPB2P TX3M_DPB2N TX4P_DPB1P TX4M_DPB1N TX5P_DPB0P TX5M_DPB0N R1 R3 SCL SDA AF2 AF4 TXCD+ TXCD- [26] [26] 0_0402_5% 27MCLK AG3 AG5 TX0D+ TX0D- [26] [26] AH3 AH1 TX1D+ TX1D- [26] [26] AK3 AK1 TX2D+ TX2D- [26] [26] DAC1 R RB I2C B BB HSYNC VSYNC RSET GPIO24_TRSTB T5 PAD T6 PAD T7 PAD T76 PAD TESTEN L6 L5 L3 L1 K4 AF24 AB13 W8 W9 W7 AD10 1 +1.8VS R884 499_0402_1% AC14 [26] HDMI_HPD# GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16_SSIN GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB GPIO_29_DRM_0 GPIO_30_DRM_1 VARY_BL DIGON TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N D_RED AK6 AM5 1 2 R870 D_GREEN 1 D_BLUE TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N 150_0402_1% 2 R872 AJ7 AH6 150_0402_1% 1 TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N 2 R874 PAD T29 AB11 AB12 ENAVDD @ R1006 0_0402_5% XTALOUT XTALOUT_XTL ENAVDD [26] 27MCLK_XTL TXCLK_UP_DPF3P TXCLK_UN_DPF3N AK5 AM3 150_0402_1% AK8 AL7 TXOUT_U3P TXOUT_U3N AM26 D_RED AH20 AJ19 @ R03 AL21 AK20 R896 1M_0402_5% @ AH22 AJ21 4 AL23 AK22 1 1 OUT AL25 AJ25 D_GREEN AH24 AG25 D_BLUE AH26 AJ27 AVDD AVSSQ VDD1DI VSS1DI TXCLK_LP_DPE3P TXCLK_LN_DPE3N AD22 AG24 AE22 AE23 AD23 1 R876 TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N [26] TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N [26] CRT_HSYNC [17,26] CRT_VSYNC [17,26] TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N TXOUT_L3P TXOUT_L3N STRAP 2 IN GND 2 1 @ C1118 2 22P_0402_50V8J AL15 AK14 TXCLK_L+ [26] TXCLK_L- [26] AH16 AJ15 TXOUT_L0+ [26] TXOUT_L0- [26] AL17 AK16 TXOUT_L1+ [26] TXOUT_L1- [26] AH18 AJ17 TXOUT_L2+ [26] TXOUT_L2- [26] DAC2 B2 B2B C Y COMP JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO TESTEN XOUT 6 VSS 5 MODOUT XIN/CLKIN @ 4 VDD ASM3P2872AF-06OR_TSOT-23-6 R144 2 R_27M_SSC 1 33_0402_1% @ 1 C1105 0.1U_0402_10V6K C1104 1U_0402_6.3V4Z 04/22 1 2 @ 2 @ C Spread Spectrum For EMI +1.1VS (1.8V@120mA +DPLL_PVDD) AM12 AK12 1 AL11 AJ11 C1092 1 1 C1093 1 C1094 +DPLL_VDDC 1U_0402_6.3V4Z 2 MCK1608471YZF 0603 10U_0603_6.3V6M 1 1 C1095 1 C1096 C1097 10U_0603_6.3V6M 2 AK10 AL9 AH12 AM10 AJ9 1 L103 +DPLL_PVDD 1U_0402_6.3V4Z 2 MCK1608471YZF 0603 (1.1V@300mA +DPLL_VDDC) 2 2 0.1U_0402_10V6K 2 2 2 0.1U_0402_10V6K PAD T2 PAD T3 PAD T4 AL13 AJ13 HSYNC_DAC2 [17] VSYNC_DAC2 [17] AD19 AC19 +VDD2DI AE20 +A2VDD AE17 R957 +A2VDDQ 1 R955 1 2 R956 0_0402_5% +3.3V_DELAY 1 2 +AVDD (1.8V@70mA AVDD) L104 2 +VDD1DI 1U_0402_6.3V4Z 1 BLM18PG121SN1D_0603 C1098 VDD2DI VSS2DI +3.3V_DELAY REFOUT 2 +1.8VS H2SYNC V2SYNC 1 XTALOUT_XTL 3 216-0728002 A11 M92-S2_FCBGA631 L102 G2 G2B U71 27MCLK_SSIC AL19 AK18 +1.8VS R2 R2B R03 499_0402_1% +AVDD +VDD1DI D 3 27MHz_16PF_6P27000126 @ C1117 2 22P_0402_50V8J AK24 AJ23 XTALOUT_XTL Y6 GND Close to M92 [26] AK26 GENERAL PURPOSE I/O GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 LVDS CONTROL LVTMDP G GB 0_0402_5% 1 R881 2LCDI2C_CLK 1 2LCDI2C_DAT R959 0_0402_5% U6 [17] GPU_GPIO0 U10 [17] GPU_GPIO1 CLK_GPIO10 R1002 R_CLK_GPIO10 T10 [17] GPU_GPIO2 0_0402_5% EMI U8 U7 GPIO24_TRSTB 2 1 1 2 T9 R895 @ 10K_0402_5% R877 @ 0_0402_5% T8 ENABLT T7 [26] ENABLT ENAVDD SOUT_GPIO8 2 1 P10 [17] SOUT_GPIO8 R883 @ 10K_0402_5% GPU_GPIO9 P4 [17] GPU_GPIO9 R_CLK_GPIO10 P2 ENABLT GPU_GPIO11 2 1 N6 [17] GPU_GPIO11 R891 10K_0402_5% GPU_GPIO12 N5 [17] GPU_GPIO12 GPU_GPIO13 N3 [17] GPU_GPIO13 TESTEN 2 1 Y9 R889 1K_0402_5% VGA_PWRSEL0 N1 [33] VGA_PWRSEL0 R_27M_SSC M4 1 2 [16] 27M_SSC R879 @ 0_0402_5% BB_EN 2 1 R6 [17] THM_ALERT# R882 @ 10K_0402_5% R880 10K_0402_5% W10 @ 2 GPU_CTF M2 1 VGA_PWRSEL1 P8 T42 PAD BB_EN P7 [20] BB_EN ROMSE_GPIO22 N8 GPIO23_CLKREQB N7 [16] VGA_CLK_REQ# T11 R11 B TX0P_DPA2P TX0M_DPA2N TX1P_DPA1P TX1M_DPA1N 2 2 R960 DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23 LCD HDMI_SDA 2 4.7K_0402_5% R900 AA1 Y4 AC7 Y2 U5 U1 Y7 V2 Y8 V4 AB7 W1 AB8 W3 AB9 W5 AC6 W6 AD7 AA3 AC8 AA5 AE8 AA6 AE9 AB4 AD9 AB2 AC10 AC5 1 R952 R1005 U64F MUTI GFX VRAM_ID0 2 @ 27MCLK_XTL 2 1 C 3 U64B Internal pull low 10U_0603_6.3V 1 1 2 2 1 C1099 C1100 2 0.1U_0402_10V6K A2VDD GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 A2VDDQ A2VSSQ 0_0402_5% 0_0402_5% 2 1U_0402_6.3V4Z 1 BLM18PG121SN1D_0603 1 C1101 AE19 +VDD1DI (1.8V@45mA VDD1DI) L105 2 1 1 C1102 C1103 B HPD1 R2SET AG13 1 R885 10U_0603_6.3V 2 2 2 715_0402_1% 2 2 0.1U_0402_10V6K 1 AC16 DDC1CLK DDC1DATA 1 0.1U_0402_10V6K R886 249_0402_1% C1110 2 +DPLL_VDDC AF14 AE14 AD14 1.8V 27M_NSSC_R 1 AUX1P AUX1N PLL/CLOCK +DPLL_PVDD 2 27MCLK XTALOUT 2 2 R887 75_0402_1% AM28 AK28 DPLL_PVDD DPLL_PVSS DDC2CLK DDC2DATA DPLL_VDDC AUX2P AUX2N XTALIN XTALOUT NC1 NC2 R888 1 100_0402_5% +1.8VS 1U_0402_6.3V4Z 2 T45 PAD 1 BLM18PG121SN1D_0603 10U_0603_6.3V A T4 T2 [17] GPU_THERMAL_D+ [17] GPU_THERMAL_D- L109 1 C1114 2 1 2 C1115 1 2 (1.8V@1mA A2VDDQ) DDC/AUX VREFG R5 AD17 AC17 C1116 DPLUS DMINUS THERMAL DDCAUX5P DDCAUX5N DDC6CLK DDC6DATA TS_FDO TSVDD TSVSS NC_DDCAUX7P NC_DDCAUX7N CRT_DDC_CLK CRT_DDC_DATA AE6 AE5 CRT_DDC_CLK [26] CRT_DDC_DATA [26] AD2 AD4 R901 AC11 AC13 HDMI_SCL HDMI_SDA 1 1 R903 0_0402_5% 2 2 0_0402_5% CRT HDMI VGA_HDMI_SCL VGA_HDMI_SDA FLASH ROM [26] [26] U70 AD13 AD11 1 AB22 AC22 PAD T41 PAD T40 AE16 AD16 2 CLK_GPIO10 1 R143 @ 33_0402_1% 2 C1209 22P_0402_50V8J @ GPU_GPIO9 5 CLK_GPIO10 6 ROMSE_GPIO22 R1000 0_0402_5% R1001 EMI AC1 AC3 1 7 +3.3V_DELAY 0_0402_5% @ AD20 AC20 3 8 @ D Q 2 SOUT_GPIO8 C S TYPE 1 HOLD W VCC VSS 4 R03 M25P10-AVMN6P C1390 0.1U_0402_16V7K 0.1U_0402_10V6K A (1.8V@20mA TSVDD) 216-0728002 A11 M92-S2_FCBGA631 27M_NSSC_R EMI R1004 [16] 27M_NSSC 0_0402_5% 27M_NSSC_R 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 27MCLK_SSIC 5 Compal Secret Data Security Classification R1003 0_0402_5% @ 4 3 2 Title Compal Electronics, Inc. M92-S2 LVDS,CRT,HDMI Size Document Number Custom Date: Rev 0.3 LS-5588 Wednesday, July 01, 2009 Sheet 1 18 of 35 5 BA[2..0] 4 BA[2..0] MAA[12..0] [21] MAA[12..0] MDA[0..63] [21] 3 MDA[0..63] 2 1 U64G [21] U64C +1.8VS (1.8V@200mA +DPE_VDD18) +DPE_VDD18 DP E/F POWER DP A/B POWER B T78 PAD T79 PAD J25 K7 243_0402_1% 1 R902 T80 PAD 2 J8 K25 DRAM_RST# L10 CLKA1 CLKA1B RASA0B RASA1B CASA0B CASA1B CSA0B_0 CSA0B_1 CSA1B_0 CSA1B_1 CKEA0 CKEA1 NC_MEM_CALRN0 NC_MEM_CALRN1 WEA0B WEA1B MEM_CALRP1 NC_MEM_CALRP0 RSVD#1 RSVD#2 RSVD#3 DRAM_RST H27 A27 C23 C19 C15 E9 C5 H4 QSA#0 QSA#1 QSA#2 QSA#3 QSA#4 QSA#5 QSA#6 QSA#7 1 2 1 L112 BLM18PG121SN1D_0603 10U_0603_6.3V @ DQMA#[7..0] 2 R322 1 1 +1.1VS AG14 AH14 AM14 AM16 AM18 DPE_VDD10#1 DPE_VDD10#2 DPA_VDD10#1 DPA_VDD10#2 DPE_VSSR#1 DPE_VSSR#2 DPE_VSSR#3 DPE_VSSR#4 DPE_VSSR#5 DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5 AF6 AF7 +DPA_VDD10 1 AE1 AE3 AG1 AG6 AH5 L111 1U_0402_6.3V4Z 1 C1122 2 1 BLM18PG121SN1D_0603 1 C1123 10U_0603_6.3V 2 2 2 D C1124 0.1U_0402_10V6K +DPF_VDD18 2 AF16 AG17 0.1U_0402_10V6K L2 2 1 BLM18PG121SN1D_0603 DPF_VDD18#1 DPF_VDD18#2 NC_DPB_VDD18#1 NC_DPB_VDD18#2 DPF_VDD10#1 DPF_VDD10#2 DPB_VDD10#1 DPB_VDD10#2 DPF_VSSR#1 DPF_VSSR#2 DPF_VSSR#3 DPF_VSSR#4 DPF_VSSR#5 DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5 DPEF_CALR DPAB_CALR AE13 AF13 QSA#[7..0] [21] AF22 AG22 1 (1.1V@170mA +DPF_VDD10) QSA[7..0] 1U_0402_6.3V4Z 10U_0603_6.3V C1128 2 1 C1129 2 1 2 AF23 AG23 AM20 AM22 AM24 0.1U_0402_10V6K R898 150_0402_1% 1 2 +1.8VS AF8 AF9 C1130 [21] (1.8V@20mA +DPE_PVDD) AF17 AF10 AG9 AH8 AM6 AM8 AE10 R899 150_0402_1% 1 2 (1.8V@20mA +DPA_PVDD) +1.8VS C +DPE_PVDD L113 2 BLM18PG121SN1D_0603 L114 1U_0402_6.3V4Z 1 1 ODTA0 ODTA1 H26 H25 CLKA0 CLKA0# G9 H9 CLKA1 CLKA1# G22 G17 RASA#0 RASA#1 G19 G16 CASA#0 CASA#1 H22 J22 CSA0# G13 K13 CSA1# K20 J17 CKEA0 CKEA1 ODTA0 ODTA1 [21] [21] CLKA0 CLKA0# [21] [21] CLKA1 CLKA1# [21] [21] RASA#0 RASA#1 [21] [21] CASA#0 CASA#1 [21] [21] CSA0# [21] CSA1# [21] C1131 2 AG18 AF19 1 C1132 1 C1133 2 0.1U_0402_10V6K 2 WEA#0 WEA#1 CKEA0 CKEA1 WEA#0 WEA#1 PAD T74 PAD T75 PAD T71 DP PLL POWER DPE_PVDD DPE_PVSS DPA_PVDD DPA_PVSS AG8 AG7 +DPE_PVDD +DPA_PVDD 1U_0402_6.3V4Z 10U_0603_6.3V AG19 AF20 NC_DPF_PVDD NC_DPF_PVSS DPB_PVDD DPB_PVSS AG10 AG11 +DPB_PVDD 1 C1134 2 1 C1135 2 2 1 2 1 BLM18PG121SN1D_0603 C1136 0.1U_0402_10V6K 216-0728002 A11 M92-S2_FCBGA631 +1.8VS (1.8V@20mA +DPB_PVDD) L115 +1.5VS +1.5VS Close to K26 R906 100_0402_1% [21] [21] R908 100_0402_1% [21] [21] 1U_0402_6.3V4Z Close to J26 R907 100_0402_1% 2 1 BLM18PG121SN1D_0603 1 1 1 C1137 C1138 C1139 10U_0603_6.3V 2 +VDD_MEM15_REFD +VDD_MEM15_REF1 1 1 C1140 0.1U_0402_16V4Z R909 100_0402_1% 2 2 2 0.1U_0402_10V6K C1141 0.1U_0402_16V4Z B 2 +1.5VS CLKTESTA CLKTESTB (For future use only) R316 4.7K_0402_5% 216-0728002 A11 M92-S2_FCBGA631 +1.8VS (1.8V@120mA +DPLL_PVDD) L126 1 +DPA_VDD18 1U_0402_6.3V4Z 2 DRAM_RST# [21] DRAM_RST# @ 2 R317 2 AG20 AG21 1 C1127 +DPA_VDD18 +DPF_VDD10 4.7K_0402_5% 2 AE11 AF11 (1.1V@200mA +DPA_VDD10) 2 R321 4.7K_0402_5% NC_DPA_VDD18#1 NC_DPA_VDD18#2 +DPF_VDD10 +1.1VS L18 K16 AB16 G14 G20 1U_0402_6.3V4Z 1 C1125 C1126 [21] 10U_0603_6.3V G25 H10 C1121 0.1U_0402_10V6K 2 2 2 1 1 CLKA0 CLKA0B QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 2 0_0402_5% C1120 2 ODTA0 ODTA1 H28 C27 A23 E19 E15 D10 D6 G5 2 1 DPE_VDD18#1 DPE_VDD18#2 1 WDQSA_0 WDQSA_1 WDQSA_2 WDQSA_3 WDQSA_4 WDQSA_5 WDQSA_6 WDQSA_7 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 +DPE_VDD18 +1.8VS R897 1 1 RDQSA_0 RDQSA_1 RDQSA_2 RDQSA_3 RDQSA_4 RDQSA_5 RDQSA_6 RDQSA_7 E32 E30 A21 C21 E13 D12 E3 F4 10U_0603_6.3V C1119 1 K8 L7 MVREFDA MVREFSA DQMA_0 DQMA_1 DQMA_2 DQMA_3 DQMA_4 DQMA_5 DQMA_6 DQMA_7 1 AG15 AG16 2 +VDD_MEM15_REFD K26 +VDD_MEM15_REF1 J26 MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8 MAA_9 MAA_10 MAA_11 MAA_12 MAA_13/BA2 MAA_14/BA0 MAA_15/BA1 1U_0402_6.3V4Z 2 1 BLM18PG121SN1D_0603 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 BA2 BA0 BA1 2 C DQA_0 DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63 K17 J20 H23 G23 G24 H24 J19 K19 J14 K14 J11 J13 H11 G11 J16 L15 1 D K27 J29 H30 H32 G29 F28 F32 F30 C30 F27 A28 C28 E27 G26 D26 F25 A25 C25 E25 D24 E23 F23 D22 F21 E21 D20 F19 A19 D18 F17 A17 C17 E17 D16 F15 A15 D14 F13 A13 C13 E11 A11 C11 F11 A9 C9 F9 D8 E7 A7 C7 F7 A5 E5 C3 E1 G7 G6 G1 G3 J6 J1 J3 J5 2 MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63 MEMORY INTERFACE L110 MCK1608471YZF 0603 1 2 @ 1 4.7K_0402_5% C1259 1 C1260 C1261 10U_0603_6.3V6M 1 A 1 2 @ 2 0.1U_0402_10V6K @ C337 2 1U_0402_6.3V4Z A @ Compal Secret Data Security Classification Issued Date 2009/04/20 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title M92-S2 MEMORY Size Document Number Custom Date: 5 4 3 2 Compal Electronics, Inc. Rev 0.3 LS-5588 Wednesday, July 01, 2009 Sheet 1 19 of 35 5 4 3 2 1 2 1 2 U64D (1.8V@500mA +PCIE_GDDR) MEM I/O 1U_0402_6.3V4Z PCIE 2 10U_0603_6.3V 2 C1156 2 1 C1154 2 1 C1153 1 C1155 1 2 1 2 10U_0603_6.3V 10U_0603_6.3V VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17 PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8 PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8 PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12 +VDDC_CT +1.8VS 2 LV_TRANS1.8 1 BLM18PG121SN1D_0603 2 2 1 1 2 1 2 1 2 2 1 2 1 1 2 1 2 + C1176 330U_D2E_2.5VM_R9M 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 10U_0603_6.3V 1 2 10U_0603_6.3V 1 C1185 10U_0603_6.3V 1 C1186 1 C1187 2 1U_0402_6.3V4Z 2 C1305 1 2 1 2 10U_0603_6.3V 1U_0402_6.3V4Z 1 1 10U_0603_6.3V +VDDCI 1 2 2 1U_0402_6.3V4Z 1 NC_SPV18 SPV10 1 2 2 1U_0402_6.3V4Z 1 2 1 2 2 1 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 1 2 For S2: Install L124 and DO not Install L127 2 For S3: Install L127 and DO not Install L124 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z M13 M15 M16 M17 M18 M20 M21 N20 1U_0402_6.3V4Z 1 C1304 2 1U_0402_6.3V4Z 10U_0603_6.3V 1 2 2 1 (+VGA_CORE@2000mA +VDDCI) 1 2 M6 N11 N12 N13 N16 N18 N21 P6 P9 R12 R15 R17 R20 T13 T16 T18 T21 T6 U15 U17 U20 U3 U9 V13 V16 V18 V6 Y10 Y15 Y17 Y20 Y6 L120 MCK2012221YZF 0805 2 C1207 1 C1206 1 GND#56 GND#57 GND#58 GND#59 GND#60 GND#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87 GND VSS_MECH#1 VSS_MECH#2 VSS_MECH#3 A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6 D C A32 AM1 AM32 216-0728002 A11 M92-S2_FCBGA631 2 B Q73 BACK BIAS 1 BBP#1 BBP#2 +3VS SI2301BDS_SOT23 R03 +VGASENSE [33] +VGASENSE 3 D M11 M12 1U_0402_6.3V4Z GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8 GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55 1U_0402_6.3V4Z 1U_0402_6.3V4Z SPVSS +3.3V_DELAY 0.1U_0402_10V6K +BBP 1 C1192 2 J7 1 1 PCIE_VSS#1 PCIE_VSS#2 PCIE_VSS#3 PCIE_VSS#4 PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31 1U_0402_6.3V4Z 1U_0402_6.3V4Z C1202 H8 C1205 2 1 C1204 10U_0603_6.3V 1 C1203 1 1U_0402_6.3V4Z 1U_0402_6.3V4Z C1201 +SPV10 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z AA15 N15 N17 R13 R16 R18 R21 T12 T15 T17 T20 U13 U16 U18 U21 V15 V17 V20 V21 Y13 Y16 Y18 Y21 C1200 L122 1 MCK1608471YZF 0603 +VGA_CORE C1199 H7 B NC_MPV18 C1162 10U_0603_6.3V C1191 L8 2 0.1U_0402_10V6K +VGA_CORE 2 C1381 2 PCIE_PVDD 2 (+VGA_CORE@9000mA +VDDC) 2 VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8 2 1 C1161 1U_0402_6.3V4Z C1248 2 1 AM30 C1198 1 C1197 10U_0603_6.3V 1 C1196 BLM18PG121SN1D_0603 +PCIE_PVDD 1 C1160 2 C1379 VSSRHA 1 C1159 2 +1.1VS 1U_0402_6.3V4Z 1 C1158 1U_0402_6.3V4Z ISOLATED CORE I/O PLL 1U_0402_6.3V4Z 1 2 1 C1157 1U_0402_6.3V4Z VDDRHA 2 L121 2 1 C1380 L16 L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22 1U_0402_6.3V4Z C1292 2 +1.8VS MEM CLK L17 C1195 1 +PCIE_VDDC C1190 1U_0402_6.3V4Z C1194 1 2 (1.1V@2000mA +PCIE_VDDC) C1189 1U_0402_6.3V4Z 2 C1152 10U_0603_6.3V 1U_0402_6.3V4Z C1188 VDD_RHA1.5 1 2 1U_0402_6.3V4Z C1175 L119 2 BLM18PG121SN1D_0603 2 C1301 C1174 +1.5VS VDDR4#1 VDDR4#2 VDDR4#3 VDDR4#4 C1300 2 MCK2012221YZF 0805 1 C1173 AA11 AA12 Y11 Y12 POWER +VDDR4 VDDR5#1 VDDR5#2 VDDR5#3 VDDR5#4 2 1 C1172 1U_0402_6.3V4Z C1299 C1171 2 U11 U12 V11 V12 1 C1170 +VDDR5 C1151 C1169 2 1U_0402_6.3V4Z C1180 2 1 C1179 C1178 C1177 2 1 VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4 C1145 0.1U_0402_10V6K 1 C1168 AA17 AA18 AB17 AB18 VDDC#1 VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8 VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23 1 C1167 I/O 1U_0402_6.3V4Z 1 CORE 2 0.1U_0402_10V6K 1U_0402_6.3V4Z 10U_0603_6.3V VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4 2 +1.8VS L116 1 1 C1166 2 +3.3V_DELAY AA20 AA21 AB20 AB21 C1165 2 1 C1164 1 C1163 1 10U_0603_6.3V 1 LEVEL TRANSLATION (1.8V@110mA +VDDC_CT) L117 1U_0402_6.3V4Z +PCIE_GDDR AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26 2 10U_0603_6.3V 2 1 H13 H16 H19 J10 J23 J24 J9 K10 K23 K24 K9 L11 L12 L13 L20 L21 L22 C1150 1U_0402_6.3V4Z 2 1 C1149 1U_0402_6.3V4Z 2 1 C1148 1U_0402_6.3V4Z 2 1 C1147 1U_0402_6.3V4Z 2 1 C1146 1U_0402_6.3V4Z 2 1 C1144 1U_0402_6.3V4Z 1 C1143 1U_0402_6.3V4Z C1142 1U_0402_6.3V4Z D AA27 AB24 AB32 AC24 AC26 AC27 AD25 AD32 AE27 AF32 AG27 AH32 K28 K32 L27 M32 N25 N27 P25 P32 R27 T25 T32 U25 U27 V32 W25 W26 W27 Y25 Y32 2 2 2 1 R910 100K_0402_5% R444 0_0402_5% CH751H-40_SC76 D7 216-0728002 A11 M92-S2_FCBGA631 2 1 SUSP# 0.1U_0402_10V6K 2 +VGA_CORE 1 2 S 1 G 2 C1377 1U_0402_6.3V4Z 1 C1376 1U_0402_6.3V4Z 2 C1375 1U_0402_6.3V4Z 1 C1374 1U_0402_6.3V4Z 2 C1370 0.1U_0402_10V6K 1 U64E C1368 0.1U_0402_10V6K 2 C1366 0.1U_0402_10V6K C1365 0.1U_0402_10V6K 1 C 1 (1.5V@2200mA) 1 +1.5VS +1.8VS 1 2 D 2 S 2 2 G 1 3 S Q4 2 2 R2129 1 10K_0402_5% 1 2 2 R911 100K_0402_5% G 1 10U_0603_6.3V 1 2 S 2N7002_SOT23 C1208 0.1U_0402_10V6K 2 A 0.1U_0402_10V6K 1 100K_0402_5% G SSM3K7002FU_SC70-3 BB_EN=0V,for Back Biasing Disabled, Q2004=OFF,Q2005=OFF and Q2006=ON, Security Classification Compal Secret Data +BBP=+GPU_CORE 2009/04/20 2010/04/30 Deciphered Date BB_EN=+3.3V,for Back Biasing Enabled, Issued Date Q2004=ON,Q2005=ON and Q2006=OFF, THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +BBP=+1.8VSDGPU DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 VGA_CORE sense for Power Termination of VGA_CORE Q74 2 +VDDR5 1 D C1278 +5VS R2128 BB_EN 2 C1280 1 C1277 D 1U_0402_6.3V4Z 1 BLM18PG121SN1D_0603 1 3 2 [18] 2 0.1U_0402_10V6K L128 +VGA_CORE D C1303 2 G A 2 10U_0603_6.3V 3 +VDDR4 1 +1.8VS Q3 SI2301BDS_SOT23 S 1 2 1 C1281 Q2 SSM3K7002FU_SC70-3 C1391 1U_0402_6.3V4Z 1 C1298 1 L130 BLM18PG121SN1D_0603 1U_0402_6.3V4Z 1 BLM18PG121SN1D_0603 1 L123 2 +BBP Back Biasing 3 +1.8VS 4 3 2 Title Compal Electronics, Inc. M92-S2 PWR,GND Size B Date: Document Number Rev 0.3 LS-5588 Wednesday, July 01, 2009 Sheet 1 20 of 35 4 3 [19] [19] [19] [19] [19] [19] M2 N8 M3 BA0 BA1 BA2 [19] [19] [19] [19] [19] QSA0 QSA2 F3 C7 DQMA#0 DQMA#2 E7 D3 QSA#0 QSA#2 G3 B7 ODT/ODT0 CS/CS0 RAS CAS WE DQSL DQSU DML DMU C DQSL DQSU T2 [19] DRAM_RST# RESET 1 L8 ZQ/ZQ0 J1 L1 J9 L9 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 2 R912 240_0402_1% VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CLKA0 CLKA0# CKEA0 J7 K7 K9 +1.5VS A1 A8 C1 C9 D2 E9 F1 H2 H9 ODTA0 CSA0# RASA#0 CASA#0 WEA#0 K1 L2 J3 K3 L3 QSA1 QSA3 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 DQMA#1 DQMA#3 E7 D3 QSA#1 QSA#3 G3 B7 DRAM_RST# T2 96-BALL SDRAM DDR3 K4W1G1646E-HC12_FBGA96 MDA[0..63] VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 J1 L1 J9 L9 R913 240_0402_1% M8 H1 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 MDA30 MDA24 MDA31 MDA25 MDA27 MDA26 MDA28 MDA29 D7 C3 C8 C2 A7 A2 B8 A3 +1.5VS BA0 BA1 BA2 L8 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ M2 N8 M3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VREFC_A3 VREFD_Q3 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ BA0 BA1 BA2 B2 D9 G7 K2 K8 N1 N9 R1 R9 CLKA1 CLKA1# CKEA1 J7 K7 K9 [19] [19] [19] [19] [19] ODTA1 CSA1# RASA#1 CASA#1 WEA#1 K1 L2 J3 K3 L3 A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 QSA5 QSA4 F3 C7 DQMA#5 DQMA#4 E7 D3 QSA#5 QSA#4 G3 B7 DRAM_RST# T2 96-BALL SDRAM DDR3 K4W1G1646E-HC12_FBGA96 E3 F7 F2 F8 H3 H8 G2 H7 MDA45 MDA41 MDA47 MDA40 MDA44 MDA43 MDA46 MDA42 D7 C3 C8 C2 A7 A2 B8 A3 MDA33 MDA38 MDA32 MDA39 MDA35 MDA37 MDA34 MDA36 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 ODT/ODT0 CS/CS0 RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 M2 N8 M3 CLKA1 CLKA1# CKEA1 J7 K7 K9 A1 A8 C1 C9 D2 E9 F1 H2 H9 ODTA1 CSA1# RASA#1 CASA#1 WEA#1 K1 L2 J3 K3 L3 QSA7 QSA6 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 DQMA#7 DQMA#6 E7 D3 QSA#7 QSA#6 G3 B7 DRAM_RST# T2 +1.5VS L8 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ J1 L1 J9 L9 R915 240_0402_1% VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 96-BALL SDRAM DDR3 K4W1G1646E-HC12_FBGA96 E3 F7 F2 F8 H3 H8 G2 H7 MDA63 MDA59 MDA60 MDA62 MDA57 MDA58 MDA56 MDA61 D7 C3 C8 C2 A7 A2 B8 A3 MDA53 MDA48 MDA55 MDA50 MDA52 MDA51 MDA54 MDA49 D DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 +1.5VS BA0 BA1 BA2 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE DQSL DQSU DML DMU A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 +1.5VS A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ C B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 96-BALL SDRAM DDR3 K4W1G1646E-HC12_FBGA96 DQMA#[7..0] 1 1 2 R929 4.99K_0402_1% 1 2 2 R928 4.99K_0402_1% 1 1 2 2 1 2 C1216 1 2 C1215 1 R927 4.99K_0402_1% 2 1 C1214 2 2 C1213 1 2 C1212 2 2 2 2 1 2 1 VREFD_Q3 4.99K_0402_1% VREFC_A4 B R930 1 4.99K_0402_1% 2 VREFD_Q4 R931 4.99K_0402_1% 1 2 0.1U_0402_10V6K R926 4.99K_0402_1% R923 0.1U_0402_10V6K 2 4.99K_0402_1% 0.1U_0402_10V6K C1246 0.01U_0402_25V7K 1 R922 4.99K_0402_1% VREFC_A3 0.1U_0402_10V6K 56_0402_1% R925 4.99K_0402_1% VREFD_Q2 0.1U_0402_10V6K 2 VREFC_A2 0.1U_0402_10V6K 1 0.1U_0402_10V6K R924 4.99K_0402_1% 2 0.1U_0402_10V6K 2 VREFC_A1 R921 C1219 R920 4.99K_0402_1% +1.5VS 2 R919 4.99K_0402_1% +1.5VS 1 R918 4.99K_0402_1% +1.5VS 2 R917 4.99K_0402_1% +1.5VS 2 R916 4.99K_0402_1% +1.5VS 1 +1.5VS C1218 +1.5VS 1 +1.5VS QSA#[7..0] 1 QSA[7..0] 56_0402_1% 1 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA[12..0] VREFD_Q1 CLKA0# 1 R934 M8 H1 BA0 BA1 BA2 B CLKA0 1 R932 VREFC_A4 VREFD_Q4 +1.5VS B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 J1 L1 J9 L9 R914 240_0402_1% DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 BA0 BA1 BA2 L8 B1 B9 D1 D8 E2 E8 F9 G1 G9 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 M2 N8 M3 [19] [19] +1.5VS [19] U68 VREFCA VREFDQ 2 QSA#[7..0] VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ BA0 BA1 BA2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 MDA10 MDA12 MDA8 MDA13 MDA11 MDA15 MDA9 MDA14 E3 F7 F2 F8 H3 H8 G2 H7 C1217 [19] QSA[7..0] N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 1 [19] MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 U67 VREFCA VREFDQ 1 MAA[12..0] [19] DQMA#[7..0] M8 H1 1 [19] MDA[0..63] 1 [19] MDA18 MDA19 MDA16 MDA22 MDA20 MDA23 MDA17 MDA21 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 K1 L2 J3 K3 L3 ODTA0 CSA0# RASA#0 CASA#0 WEA#0 D7 C3 C8 C2 A7 A2 B8 A3 VREFC_A2 VREFD_Q2 +1.5VS BA0 BA1 BA2 J7 K7 K9 CLKA0 CLKA0# CKEA0 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 MDA5 MDA6 MDA0 MDA7 MDA1 MDA2 MDA3 MDA4 1 1 D A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 E3 F7 F2 F8 H3 H8 G2 H7 1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 1 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 U66 VREFCA VREFDQ 2 M8 H1 2 U65 VREFC_A1 VREFD_Q1 2 2 5 2 +1.5VS +1.5VS 2 2 2 2 1 2 1 2 1 2 1 2 1 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 2 1 2 1 2 1 2 1 2 1 C1387 2 1 C1384 2 1 C1388 2 1 C1386 2 1 C1385 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 1 C1383 2 1 C1236 2 1 C1235 2 1 C1234 2 1 C1245 2 1 C1233 2 1 C1244 2 10U_0603_6.3V6M 1 C1232 2 1 C1231 2 10U_0603_6.3V6M 1 1 C1289 C1243 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z C1230 2 10U_0603_6.3V6M C1328 1 C1229 2 C1237 1 C1242 2 10U_0603_6.3V6M C1224 1 C1228 2 C1247 0.01U_0402_25V7K C1223 1 C1227 1 C1222 1 C1226 56_0402_1% C1221 1 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M C1241 C1220 1 10U_0603_6.3V6M C1240 2 1 10U_0603_6.3V6M C1239 CLKA1# 1 R935 +1.5VS 56_0402_1% 10U_0603_6.3V6M C1225 2 C1238 CLKA1 1 R933 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z A A Compal Secret Data Security Classification Issued Date 2009/04/20 Deciphered Date 2010/04/30 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. VRAM DDR3 Size C Date: Document Number Rev 0.3 LS-5588 Wednesday, July 01, 2009 Sheet 1 21 of 35 5 4 3 2 1 +3VS 1 8.2K_0402_5% 1 PCI_STOP# 2 R160 8.2K_0402_5% 1 PCI_TRDY# 2 R161 8.2K_0402_5% 1 PCI_FRAME# 2 R162 U5B 8.2K_0402_5% 1 A11 B12 A10 C12 A8 A12 E10 C11 B9 D8 A4 E8 A3 D9 C8 C2 D7 B3 D11 B6 D5 D3 F4 E3 E4 B2 C4 C1 D1 E2 J4 H2 PCI_PLOCK# 2 R163 8.2K_0402_5% 1 PCI_IRDY# 2 R164 8.2K_0402_5% 1 PCI_SERR# 2 R165 8.2K_0402_5% 1 PCI_PERR# 2 R166 8.2K_0402_5% +3VS 1 8.2K_0402_5% 1 8.2K_0402_5% 1 PCI_PIRQC# 2 R169 8.2K_0402_5% 1 PCI_PIRQD# 2 R170 8.2K_0402_5% 1 PCI_PIRQE# 2 R171 8.2K_0402_5% 1 PCI_PIRQF# 2 R172 47K_0402_5% 1 PCI_PIRQG# 2 R173 8.2K_0402_5% 2 PCI_PIRQH# 1 R174 8.2K_0402_5% 1 PCI_REQ0# 2 R175 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# 8.2K_0402_5% 1 PCI_REQ1# 2 R176 8.2K_0402_5% 1 PCI_REQ2# 2 R178 8.2K_0402_5% 1 F1 F5 F2 C7 PCI REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME# Interrupt I/F PIRQA# PIRQB# PIRQC# PIRQD# PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 G4 E1 A9 E12 B11 C10 D6 C6 PCI_REQ0# PCI_GNT0# PCI_REQ1# D PCI_REQ2# PCI_REQ3# PCI_GNT3# D10 A5 E6 C9 C3 B1 T3 A7 D4 C5 H5 A6 A2 B8 PCI_IRDY# A21 B5 T1 PLT_RST# CLK_PCI_ICH PCI_PME# G3 G1 F3 H4 PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME# PLT_RST# [8,17,26] CLK_PCI_ICH [16] PCI_PME# [26] C PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# ICH9-M SFF ES_FCBGA569 PCI_REQ3# 2 8.2K_0402_5% A16 swap override Strap Low= A16 swap override Enble PCI_GNT3# High= Default * Place closely pin B10 Boot BIOS Strap B CLK_PCI_ICH PCI_GNT0# SPI_CS#1 Boot BIOS Location 0 1 SPI 1 0 PCI 1 R179 B PCI_PIRQB# 2 R168 C PCI_PIRQA# 2 R167 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI_GNT3# 1 1 2 R181 @ 1K_0402_5% 1 LPC @ C235 8.2P_0402_50V * 2 1 @ R180 10_0402_5% 2 D PCI_DEVSEL# 2 R159 PCI_GNT0# 1 1 [24] KBC_SPI_CS1# 2 R183 @ 1K_0402_5% 2 R182 1K_0402_5% @ A A DEL J3. 9/29 Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. ICH9(1/4)-PCI/INT Size Document Number Rev 0.3 LS-5588 Date: Wednesday, July 01, 2009 Sheet 1 22 of 35 5 4 3 2 1 +RTCVCC +RTCVCC 1 2 1 2 1 2 1 2 R184 LAN100_SLP 330K_0402_1% R185 SM_INTRUDER# 1M_0402_5% ICH_INTVRMEN C1250 2.2U_0603_6.3V4Z D [26] ICH_RTCRST# 20K_0402_5% 1 ICH_INTVRMEN LAN100_SLP E25 D25 [24] A14 D12 B14 D13 C13 A13 Add C599 ~ C602 to solve WWAN noise issue. 1/23 PAD D15 T47 C R198 +1.5VS Remove R227 & C199 [26] 2 24.9_0402_1% GLAN_COMP 1 HDA_BITCLK [26] HDA_BITCLK [26] HDA_SYNC R1007 +3VS [26] [26] [26] [26] [26] [26] [26] [26] SATA_RXN0_C SATA_RXP0_C SATA_TXN0_CR SATA_TXP0_CR SATA_RXN1_C SATA_RXP1_C SATA_TXN1_CR SATA_TXP1_CR AE7 AB7 HDA_RST# AA7 AB6 AE6 AC6 AA5 HDA_SDIN2 [26] HDA_SDOUT [26] IDE_LED# 2 R209 SATA_RXN0_C SATA_RXP0_C SATA_TXN0_CR SATA_TXP0_CR C1079 C1080 SATA_RXN1_C SATA_RXP1_C SATA_TXN1_CR SATA_TXP1_CR C1081 C1082 1 HDA_SDOUT AC7 PAD T49 AD8 AB8 10K_0402_5% 1 1 1 1 H22 H21 0_0402_5% HDA_SYNC HDA_RST# [26] HDA_SDIN0 [26] HDA_SDIN1 LDRQ0# LDRQ1#/GPIO23 9/27 J2 LPC_FRAME# H1 J1 Del PU R203~R204 for H_DPRSTP# & H_DPSLP#. [26] 9/27 +VCCP T46 PAD AC9 2 0.01U_0402_16V7KSATA_TXN0_R 2 0.01U_0402_16V7KSATA_TXP0_R AE14 AD14 AC15 AD15 2 0.01U_0402_16V7KSATA_TXN1_R 2 0.01U_0402_16V7KSATA_TXP1_R AD13 AC13 AA14 AB14 GLAN_CLK A20GATE A20M# LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 GPIO56 DPRSTP# DPSLP# FERR# CPUPWRGD IGNNE# INIT# INTR RCIN# GLAN_COMPI GLAN_COMPO NMI SMI# HDA_BIT_CLK HDA_SYNC STPCLK# HDA_RST# THRMTRIP# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDOUT HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 TP11 SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP SATALED# SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS 2 G22 D14 ICH_RSVD INTVRMEN LAN100_SLP FWH4/LFRAME# [26] LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 H3 J3 K5 L3 2 2 2 2 RTCRST# SRTCRST# INTRUDER# FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 N3 AB23 GATEA20 AE23 AE24 H_DPRSTP_R# AD25 H_FERR#_R GATEA20 H_A20M# R194 [26] [4] H_DPSLP# R195 R192 56_0402_5% 2 0_0402_5% 1 H_PWRGOOD AD23 H_IGNNE# AE21 AD24 L1 KB_RST# H_INIT# [4] H_INTR [4] KB_RST# [26] AD21 AC21 H_SMI# AC25 H_STPCLK# AC23 THRMTRIP_ICH# AC22 T48 H_NMI H_SMI# [5] H_FERR# H_FERR# [4] Place Close to U8. +3VS [4] +VCCP [4] [4] H_STPCLK# PAD R206 GATEA20 KB_RST# R196 R197 2 10K_0402_5% 2 10K_0402_5% 1 1 C R201 56_0402_5% [4] 2 54.9_0402_1% 1 H_THERMTRIP# placed within 2" from ICH9M SATA_TXN2_R SATA_TXP2_R 1 1 SATA_RXN2_C SATA_RXP2_C SATA_TXN2_CR SATA_TXP2_CR 2 2 CLK_PCIE_SATA# CLK_PCIE_SATA AD10 AE10 R212 1 CLK_PCIE_SATA# CLK_PCIE_SATA [4,8] SATA_RXN2_C [26] SATA_RXP2_C [26] SATA_TXN2_CR [26] SATA_TXP2_CR [26] C1083 C1084 0.01U_0402_16V7K 0.01U_0402_16V7K AC11 AD11 AB10 AA10 AC16 AB16 [5,8,31] [5] 2 56_0402_5% 1 AE22 AD12 AE12 AB12 AA12 H_DPRSTP# 1 R193 HDA_SDOUT @ 1K_0402_5% ICH_RSVD @ 1K_0402_5% CLRP1 SHORT PADS RTCX1 RTCX2 1 C1044 1U_0603_10V4Z 1 ICH_SRTCRST# SM_INTRUDER# G24 C24 C23 ICH_RTCRST# 2 +3VS 1 F25 G25 2 1 +RTCVCC XOR CHAIN ENTRANCE STRAP:RSVD R191 LPC_AD[0..3] U5A ICH_RTCX1 ICH_RTCX2 R318 RTC LPC RV XOR Normal(D) PCIE Bit1 LAN / GLAN CPU 2 Description IHDA 0 1 0 1 2 @ SATA HDA_SDOUT_CODEC 0 0 1 1 2 @ 1 1 D 1 R189 0_0402_5% C236 1U_0603_10V4Z ICH_RSVD 2 ICH_SRTCRST# 20K_0402_5% 1 R187 Change from 180K to 20K & 0.1u to 1u. 9/29 R188 0_0402_5% 330K_0402_1% 1 R186 [16] [16] 2 24.9_0402_1% Within 500 mils ICH9-M SFF ES_FCBGA569 B B ICH_RTCX1 R215 1 ICH_RTCX2 2 C247 C246 10M_0402_5% 1 1 1 4 2 3 Y2 2 32.768KHZ_12.5P_MC-146 15P_0402_50V8J 15P_0402_50V8J 2 A A Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. ICH9(2/4)_LAN,HD,IDE,LPC Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 23 of 35 5 4 3 +3VS 2 1 +3VALW PM_PWROK M_PWROK 0_0402_5% 1 2 GPIO48 10K_0402_5% GPIO1 10K_0402_5% SIRQ 2 10K_0402_5% 2 PM_CLKRUN# 8.2K_0402_5% 2 THERM_SCI# @ 8.2K_0402_5% GPIO22 2 8.2K_0402_5% 2 NPCI_RST# 10K_0402_5% GPIO17 2 @ 8.2K_0402_5% 2 2 PAD 1 1 R259 1 R261 T65 GPIO17 GPIO18 R03 PAD T52 PAD PAD T53 T54 GPIO22 [16] CLKSATAREQ# PAD [26] GPIO38 GPIO39 GPIO48 T55 GPIO48 +3VALW GPIO57 +3VS RP29 5 6 7 8 R264 1 PAD LID_SW# 10K_0402_5% 2 GPIO42 10K_0402_5% 2 WOL_EN 10K_0402_5% +3VS USB_OC#9 2 10K_0402_5% USB_OC#10 2 10K_0402_5% USB_OC#11 2 10K_0402_5% R274 2.2K_0402_5% 2 1 R277 1 R278 1 1 R280 ICH_SMBDATA ICH_SMBDATA 3 D S 3 1 2 G R230 1 @ 1 R281 @ R282 @ R242 1 1 1 @ R285 PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4 C269 1 C270 1 2 0.1U_0402_10V7K 2 0.1U_0402_10V7K GPIO38 10K_0402_5% 2 GPIO21 10K_0402_5% 2 HDD_HALTLED 47K_0402_5% 2 GPIO39 10K_0402_5% SATA GPIO SMB P25 P24 P21 P22 PCIE_RXN4 M25 PCIE_RXP4 M24 PCIE_C_TXN4 L24 PCIE_C_TXP4 L23 K24 K25 K21 K22 Q9 RHU002N06_SOT323 H24 H25 J24 J23 E24 E23 F23 [22] KBC_SPI_CS1# F22 G23 USB_OC#0 USB_OC#1 USB_OC#2 GPIO42 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 GPIO44 USB_OC#9 USB_OC#10 USB_OC#11 [26] USB_OC#0 [26] USB_OC#1 [26] USB_OC#2 [26] GPIO42 [26] GPIO44 2 USBRBIAS P4 N4 N1 P5 P1 P2 M3 M2 P3 R1 R4 R2 AE5 AD5 Within 500 mils R287 22.6_0402_1% SLP_M# CL_CLK0 CL_CLK1 CL_DATA0 CL_DATA1 CL_VREF0 CL_VREF1 CL_RST0# CL_RST1# MEM_LED/GPIO24 GPIO10/SUS_PWR_ACK GPIO14/AC_PRESENT WOL_EN/GPIO9 PERN2 PERP2 PETN2 PETP2 DMI1RXN DMI1RXP DMI1TXN DMI1TXP WLAN EXP PERN4 PERP4 PETN4 PETP4 WWAN PERN5 PERP5 PETN5 PETP5 DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_CLKN DMI_CLKP DMI_ZCOMP DMI_IRCOMP PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP DPRSLPVR C16 ICH_LOW_BAT# 1 2 R243 U4 ON/OFFBTN# D22 PM_DPRSLPVR 0_0402_5% LAN_RST 2 10K_0402_5% [26] R251 D19 EC_RSMRST#R U1 CK_PWRGD_R T4 M_PWROK USBP0N USBP0P USBP1N USBP1P SPI_CLK USBP2N SPI_CS0# USBP2P SPI_CS1#/GPIO58/CLGPIO6 USBP3N USBP3P SPI_MOSI USBP4N SPI_MISO USBP4P USBP5N OC0#/GPIO59 USBP5P OC1#/GPIO40 USBP6N OC2#/GPIO41 USBP6P OC3#/GPIO42 USBP7N OC4#/GPIO43 USBP7P OC5#/GPIO29 USBP8N OC6#/GPIO30 USBP8P OC7#/GPIO31 USBP9N OC8#/GPIO44 USBP9P OC9#/GPIO45 USBP10N OC10#/GPIO46 USBP10P OC11#/GPIO47 USBP11N USBP11P USBRBIAS USBRBIAS# 1 2 2 CK_PWRGD 0_0402_5% M_PWROK [8] CL_CLK0 [8] 4 [16] B23 C22 A18 CL_CLK0 E22 B18 CL_DATA0 F21 A17 CL_VREF0_ICH C17 B17 CL_RST# A22 E16 A15 D21 GPIO24 CL_DATA0 CL_RST# AC_IN WOL_EN USB DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 W23 W24 V21 V22 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 Y24 Y25 Y21 Y22 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 AB24 AB25 AA23 AA24 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 T21 T22 CLK_PCIE_ICH# CLK_PCIE_ICH AE2 AD1 AD3 AD4 AC2 AC3 AC5 AB4 AB2 AB1 AA3 AA2 Y1 Y2 W2 W3 V1 V2 Y5 Y4 U3 U2 V4 V5 R273 10K_0402_5% 1 R253 V25 V24 U24 U23 AB21 AB22 1 LAN_RST R257 3.24K_0402_1% [8] [8] GPIO24 [26] AC_IN [26] 1 1 2 2 +3VS C 0518/'09 RSMRST circuit @ R454 0_0402_5% DMI_RXN0 [8] DMI_RXP0 [8] DMI_TXN0 [8] DMI_TXP0 [8] 2 3 [26] EC_RSMRST# EC_RSMRST#R Q26 MMBT3906_SOT23-3 1 BAV99DW-7_SOT363 DMI_RXN1 [8] DMI_RXP1 [8] DMI_TXN1 [8] DMI_TXP1 [8] D13B @ R456 2.2K_0402_5% 1 1 2 R455 4.7K_0402_5% +3VALW D13A BAV99DW-7_SOT363 R457 DMI_RXN2 [8] DMI_RXP2 [8] DMI_TXN2 [8] DMI_TXP2 [8] 2 2.2K_0402_5% B DMI_RXN3 [8] DMI_RXP3 [8] DMI_TXN3 [8] DMI_TXP3 [8] CLK_PCIE_ICH# CLK_PCIE_ICH DMI_IRCOMP R276 1 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 [16] [16] 2 24.9_0402_1% Within 500 mils +1.5VS [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] Place closely pin AF3 Place closely pin H1 CLK_48M_ICH CLK_14M_ICH @ R283 10_0402_5% 1 @ 2 @ R284 10_0402_5% 1 @ C273 A C274 4.7P_0402_50V8C 2 4.7P_0402_50V8C ICH9-M SFF ES_FCBGA569 Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 [8,31] 1 DMI0RXN DMI0RXP DMI0TXN DMI0TXP PERN3 PERP3 PETN3 PETP3 M1 Add WOL_EN back. 10/10 PETP1 PCIE_RXN2 PCIE_RXP2 PCIE_C_TXN2 PCIE_C_TXP2 ICH_SMB_CLK 1 R262 R03 1 R255 1 A GPIO38 8.2K_0402_5% 2 GPIO21 8.2K_0402_5% 2 HDD_HALTLED 47K_0402_5% 2 GPIO39 8.2K_0402_5% 2 @ 2 0.1U_0402_10V7K 2 0.1U_0402_10V7K 2 1 R249 0.1U_0402_10V7K 0.1U_0402_10V7K RSMRST# CK_PWRGD ICH9-M SFF ES_FCBGA569 U5D GLAN_RXN T25 PERN1 GLAN_RXP T24 GLAN_TXN_C R24 PERP1 GLAN_TXP_C R23 PETN1 G +3VS +3VS C265 1 C266 1 2 2 PWRBTN# LAN_RST# CLPWROK SPKR MCH_SYNC# TP3 TP8 TP9 TP10 ICH_SMB_DATA 1 ICH_SMBCLK ICH_SMBCLK PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 [26] [26] [26] [26] Q8 RHU002N06_SOT323 D [14,15,16,26] R275 2.2K_0402_5% S [14,15,16,26] 2 1 R279 [26] [26] [26] [26] C271 1 C272 1 GPIO1 GPIO6 GPIO7 GPIO8 GPIO12 GPIO13 GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5 N23 N24 M21 M22 1 R270 2 1 2 1 GLAN_RXN GLAN_RXP GLAN_TXN GLAN_TXP TP12 BATLOW# B 10K_1206_8P4R_5% R269 [26] [26] [26] [26] VRMPWRGD DPRSLPVR/GPIO16 E USB_OC#1 USB_OC#6 GPIO44 USB_OC#2 4 3 2 1 T59 K4 AB20 C19 AB17 AC17 AD17 WAKE# SERIRQ THRM# [8,26,31] 2 100K_0402_5% C 5 6 7 8 SB_SPKR MCH_ICH_SYNC# ICH_RSVD [26] SB_SPKR [8] MCH_ICH_SYNC# [23] ICH_RSVD USB_OC#7 USB_OC#5 USB_OC#0 USB_OC#4 4 3 2 1 2 @ 1K_0402_5% 10K_1206_8P4R_5% RP30 B AE16 AE18 AD18 B25 C14 D20 AE17 K3 AC8 AC19 D17 E20 M4 AB18 AC18 AB19 AC20 A16 [26] EC_SMI# [26] EC_SCI# GPIO24 10K_0402_5% 2 AC_IN @ 100K_0402_5% 2 ME__EC_CLK1 10K_0402_5% 2 ME__EC_DATA1 10K_0402_5% R258 C A19 T51 2 R256 B24 GPIO1 GPIO6 GPIO1 GPIO6 Add R321 in 10/03. 1 VRMPWRGD CLKRUN#/GPIO32 PM_PWROK R241 1 D23 1 [26] [26] C21 L4 AD20 [26] [26] [26] 2 R254 PAD M5 PCIE_WAKE# SIRQ THERM_SCI# PWROK SLP_S3# SLP_S4# SLP_S5# 1 2 1 0_0402_5% 100K_0402_5% PM_CLKRUN# S4_STATE#/GPIO26 STP_PCI#/GPIO15 STP_CPU#/GPIO25 S4_STATE# 2 1 R252 2 2 B15 A20 E14 D 4 R250 R247 1 R248 1 VGATE H_STP_PCI#_R R_STP_CPU# SLP_S3# SLP_S4# SLP_S5# [16] [16] PAD 6 1 SMBALERT#/GPIO11 D18 B20 D16 CLK_14M_ICH CLK_48M_ICH T50 5 2 0_0402_5% 2 0_0402_5% [26] PCIE_WAKE# [26] SIRQ [26] THERM_SCI# [26,31] SLP_S3# SLP_S4# SLP_S5# PMSYNC#/GPIO0 ICH_SUSCLK 3 1 SUSCLK CLK_14M_ICH CLK_48M_ICH 1 1 R246 SUS_STAT#/LPCPD# SYS_RESET# K1 AB5 R3 2 2 R245 A23 CLK14 CLK48 1 R445 1 R240 1 [16] H_STP_PCI# [16] H_STP_CPU# LINKALERT# 10K_0402_5% 2 PCIE_WAKE# 10K_0402_5% 2 EC_SWI# 10K_0402_5% 2 XDP_DBRESET# 1K_0402_5% 2 S4_STATE# @ 10K_0402_5% 2 ICH_LOW_BAT# 10K_0402_5% 1 L2 LID_SW# RI# R260 PM_BMBUSY# LID_SW# +3VALW R244 XDP_DBRESET# T5 C25 2 1 R239 R236 [8] PM_BMBUSY# @ 10K_0402_5% [26] Add R621 in 12/03. C20 453_0402_1% R238 [4] XDP_DBRESET# EC_SWI# 2 2 2 2 R235 @ 10K_0402_5% 2 1 EC_SWI# GPIO21 HDD_HALTLED NPCI_RST# GPIO37 1 GPIO37 8.2K_0402_5% GPIO18 10K_0402_5% GPIO57 2 @ 10K_0402_5% 1 R237 [26] AE19 AA18 AE20 AA20 0.1U_0402_16V4Z C263 R233 +3VS Direct Media Interface 1 PCI-Express R232 SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37 GLAN D 9/21 SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1 SPI 1 C18 C15 B21 E18 A24 Clocks 1 R231 U5C ICH_SMB_CLK ICH_SMB_DATA LINKALERT# ME__EC_CLK1 ME__EC_DATA1 SYS GPIO Power MGT R227 R224 2.2K_0402_5% MISC GPIO Controller Link 1 1 1 R225 R223 2.2K_0402_5% 1 1 R222 2 R220 2 1 1 1 R271 1 R221 3 2 Title Compal Electronics, Inc. ICH9(3/4)_DMI,USB,GPIO,PCIE Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 24 of 35 5 4 3 +RTCVCC VCC3_3[06] VCC3_3[07] VCC3_3[08] +3VS G8 H7 H8 1 PCI +1.5VS_VCCSATAPLL VCCHDA 2 W17 0.1U_0402_16V4Z C303 1 VCCSATAPLL VCCSUSHDA VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCCSUS1_05[1] VCCSUS1_05[2] VCCSUS1_5[1] VCCSUS1_5[2] 2 U12 V12 W12 1 VCC1_5_A[04] VCC1_5_A[05] VCC1_5_A[06] ATX B U13 V13 W13 VCCPSUS 1U_0603_10V4Z C298 2 +1.5VS 1U_0603_10V4Z C299 C297 2 1 10U_0603_6.3V6M 1 ARX 1U_0402_6.3V6K C296 MBK1608301YZF 0603 VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03] W10 VCC1_5_A[07] U15 V15 1 VCC1_5_A[08] VCC1_5_A[09] W18 2 VCC1_5_A[10] G9 H9 +1.5VS_USBPLL VCC1_5_A[11] VCC1_5_A[12] V11 U11 VCCSUS3_3[05] VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] @ V10 T7 H15 +3VS 1 2 T9 U9 1 2 VCC1_5_A[15] VCC1_5_A[16] C308 0.1U_0402_16V4Z 2 VCC_LAN1_05_INT_ICH 1 G11 H11 2 +1.5VS 1 +1.5VS_GLAN 2 VCCGLAN1_5[1] VCCGLAN1_5[2] 1 C311 10U_0603_6.3V6M 2 10U_0603_6.3V6M C310 2 +3VS 2 1U_0603_10V4Z C285 +3VS 2 0_0603_5% +1.5VS VCCSUS1_5_ICH_1 T62 V7 VCCSUS1_5_ICH_2 T63 G14 G15 H14 R319 180_0402_1% 1 1 2 4.7U_0603_6.3V6K C287 C286 2 0_0603_5% @ 1 R320 R325 150_0402_1% 2 +3VALW 2 +3VALW 0_0603_5% +1.5VALW 1 2 +3VALW W8 J7 J8 K7 K8 L7 L8 M7 M8 N7 N8 P7 P8 1 1 2 1 2 2 VCCCL1_05 VCCCL1_5 VCCCL3_3[1] VCCCL3_3[2] G18 C304 0.1U_0402_16V4Z VCCCL1_05_ICH 1 2 H17 1 C305 J14 K14 2 1U_0402_6.3V6K +3VS 9/21 VCCGLANPLL H19 J18 +1.5VS_PCIE_ICH 1 R323 1 @ R324 1 VCCLAN3_3[1] VCCLAN3_3[2] J17 1 T60 T61 2 K16 GLAN POWER 0.1U_0402_16V4Z C309 MBK1608301YZF 0603 A G12 H13 R304 MBK1608301YZF 0603 2 1 VCCLAN1_05[1] VCCLAN1_05[2] R303 1 2 9/21 VCCUSBPLL USB CORE MBK1608301YZF 0603 VCCSUS1_05_ICH_1 VCCSUS1_05_ICH_2 H16 VCC1_5_A[13] VCC1_5_A[14] U8 0.1U_0402_16V4Z C307 2 0.1U_0402_16V4Z C306 1 1 AD7 R298 +1.5VS 2 1 R03 +3VALW VCCSUS3_3[04] 2 VCCPUSB 1 +1.5VS 2 4.7U_0603_6.3V6K C302 R296 +VCCP C294 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1 C290 C292 AA9 V14 W14 1 0.1U_0402_16V4Z C295 2 2 +VCCP +3VS AE9 0.1U_0402_16V4Z C300 1U_0402_6.3V6K 2 V18 C293 C291 1 0.1U_0402_16V4Z 2 VCC3_3[03] VCC3_3[04] VCC3_3[05] VCCP_CORE 9/19 C 1 1 MBK1608301YZF 0603 20 mils 1 R292 VCC_DMI VCC_DMI 9/29 (DMI) V16 U16 C289 1 2 20 mils 9/29 T17 U17 +1.5VS 2 0.1U_0402_16V4Z ICH_V5REF_RUN VCC3_3[02] +1.5VS_DMIPLL 2 2 0.1U_0402_16V4Z ICH_V5REF_SUS P19 1 1 0.1U_0402_16V4Z 1 VCC3_3[01] CH751H-40_SC76 VCCA3GP 2 D6 100_0402_5% 9/29 1 MBK1608301YZF 0603 0.1U_0402_16V4Z C301 R294 CH751H-40_SC76 V_CPU_IO[1] V_CPU_IO[2] 2 1 D5 2 0.1U_0402_16V4Z R293 100_0402_5% VCC_DMI[1] VCC_DMI[2] +5VALW +3VALW 2 1 +3VS 1 R290 VCCDMIPLL +5VS 2 C288 2 1 1 2 10U_0603_6.3V6M C281 2 1 2.2U_0402_6.3V6M 10U_0603_6.3V6M C280 C282 220U_D2_4VM_R15 C279 + 2 1 VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] B4 B7 B10 B13 B16 B19 B22 D2 D24 E5 E7 E9 E11 E13 E15 E17 E19 E21 F24 G2 G5 G10 G13 G16 G19 G21 H10 H12 H18 H23 J5 J9 J10 J11 J12 J13 J15 J21 J22 J25 K2 K9 K10 K11 K12 K13 K15 K17 K23 L5 L9 L10 L16 L17 L21 L22 L25 M9 M10 M12 M13 M14 M16 M17 M23 N2 N5 N9 N10 N12 N13 N14 N16 N17 N21 N22 N25 P9 P10 P12 P13 P14 P16 P17 P23 R5 R7 R8 R9 R10 R16 R17 R19 R21 R22 R25 T2 T8 T10 T11 T12 T13 T14 T15 T16 T23 2 40 mils 1 V5REF_SUS L11 L12 L13 L14 L15 M11 M15 N11 N15 P11 P15 R11 R12 R13 R14 R15 0.1U_0402_16V4Z C278 U7 J19 K18 K19 L18 L19 M18 M19 N18 N19 P18 R18 T18 T19 U18 U19 2 VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] V5REF 1U_0603_10V4Z C284 ICH_V5REF_SUS +1.5VS_PCIE_ICH BLM18PG181SN1D_0603 1 VCCRTC G7 0.1U_0402_16V4Z C277 2 G17 ICH_V5REF_RUN 0.01U_0402_16V7K C283 2 R289 1 +1.5VS D 1 U5E CORE C276 1 0.1U_0402_16V4Z C275 0.1U_0402_16V4Z 1 2 +VCCP U5F 20 mils VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] D C B VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] A1 A25 AE1 AE25 ICH9-M SFF ES_FCBGA569 A VCCGLAN3_3 ICH9-M SFF ES_FCBGA569 Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] U5 U10 W11 U14 W16 U21 U22 U25 V3 V8 V19 V23 W1 W4 W5 W7 W9 W15 W19 W21 W22 W25 Y3 Y23 AA1 AA4 AA6 AA8 AA11 AA13 AA15 AA16 AA17 AA19 AA21 AA22 AA25 AB3 AB9 AB11 AB13 AB15 AC24 AC1 AC4 AC10 AC12 AC14 AD2 AD6 AD9 AD16 AD19 AD22 AE3 AE4 AE11 AE13 AE15 V17 AE8 V9 J16 4 3 2 Title Compal Electronics, Inc. ICH9(4/4)_POWER&GND Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 25 of 35 5 4 3 2 1 B+ 1 C1033 0.1U_0603_50V4Z VS HDI_B_DET JP6 2 +RTCVCC D [31] MAINPWON [23] ICH_RTCRST# [24] GPIO1 [4,17] EC_SMB_DA2 [4,17] EC_SMB_CK2 [24] GPIO6 [24] GPIO48 [24] EC_SMI# GPIO WWAN WLAN LAN [24] [24] PCIE_TXP4 PCIE_TXN4 [24] [24] PCIE_RXP4 PCIE_RXN4 [24] [24] PCIE_TXP2 PCIE_TXN2 [24] [24] PCIE_RXP2 PCIE_RXN2 [24] [24] GLAN_TXN GLAN_TXP [24] [24] GLAN_RXN GLAN_RXP [24] SLP_S4# [24,31] VGATE [24] EC_RSMRST# [24] LID_SW# [24] GPIO24 [8,24,31] PM_PWROK [24] EC_SWI# [20] SUSP# [24] AC_IN [24] USB_OC#2 [24] USB_OC#1 [24] USB_OC#0 [24] ON/OFFBTN# [24] SLP_S5# [24] SLP_S3# [24] EC_SCI# [8,17,22] PLT_RST# [27,28] SYSON [23] LPC_AD0 [23] LPC_AD1 [23] LPC_AD2 [23] LPC_AD3 [23] LPC_FRAME# [24] SIRQ [23] KB_RST# [23] GATEA20 [16] CLKREQG_WWAN# C [18] [16] HDMI_HPD# CLK_PCI_EC [18] VGA_HDMI_SDA [18] VGA_HDMI_SCL B HDMI [18] [18] TX2D+ TX2D- [18] [18] TX1D+ TX1D- [18] [18] TX0D+ TX0D- [18] [18] TXCD+ TXCD- WWAN_CLK [16] CLKREQ_WLAN# [14,15,16,24] ICH_SMBDATA [14,15,16,24] ICH_SMBCLK [24] PCIE_WAKE# [22] PCI_PME# [16] CLK_48M_CR [16] CLKREQA# [16] CLK_PCIE_WAN# [16] CLK_PCIE_WAN WLAN_CLK [16] CLK_PCIE_MCARD# [16] CLK_PCIE_MCARD [16] CLK_PCIE_LAN# [16] CLK_PCIE_LAN LAN_CLK A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 B+ +5VS B+ +5VALW B+ +VL B+ +3VALW B+ +3VS B+ +3VS B+ +3VS RESERVED VR_ON GND HDI_B_DET/GND GND GND GND GND B+_BIAS GND +RTCVCC PC Beep ICH_RTCRST# HDA_RST GPIO1 HDA_SDOUT EC_SMB_DA2 HDA_SYNC EC_SMB_CK2 HDA_BIT_CLK GPIO6 HDA_SDIN0 GPIO48 HDA_SDIN1 EC_SMI# SATA_ACT# NC PSATA_ITX_DRX_P0 PCIE_ITX_EXPRX_P2 PSATA_ITX_DRX_N0 PCIE_ITX_EXPRX_N2 GND GND EC_THERM# PCIE_IRX_EXPTX_P2 GPIO42 PCIE_IRX_EXPTX_N2 GND GND PSATA_ITX_DRX_P1 PCIE_ITX_WLANRX_P1 PSATA_ITX_DRX_N1 PCIE_ITX_WLANRX_N1 GND GND 1.5VS PCIE_IRX_WLANTX_P1 1.5VS PCIE_IRX_WLANTX_N1 GND GND PSATA_ITX_DRX_P2 PCIE_ITX_LANRX_N0 PSATA_ITX_DRX_N2 PCIE_ITX_LANRX_P0 GND GND PSATA_IRX_DTX_P2_C PCIE_IRX_LANTX_N0 PSATA_IRX_DTX_N2_C PCIE_IRX_LANTX_P0 GND GND PSATA_IRX_DTX_P0_C PM_SLP_S4# PSATA_IRX_DTX_N0_C VGATE GND EC_RSMRST# USB20_P7 EC_LID_OUT# USB20_N7 GPIO24 GND PWRGD PSATA_IRX_DTX_P1_C EC_SWI# PSATA_IRX_DTX_N1_C SUSP# GND AC_IN USB20_P5 EC_USB_OC3# USB20_N5 EC_USB_OC2# GND EC_USB_OC1# USB20_P4 PWRBTN# USB20_N4 PM_SLP_S5# GND PM_SLP_S3# USB20_P3 EC_SCI# USB20_N3 PLT_RST# GND SYSON GPIO44 LPC_AD0 GND LPC_AD1 USB20_P8 LPC_AD2 USB20_N8 LPC_AD3 GND LPC_FRAME# USB20_P6 SIRQ USB20_N6 EC_KBRST# GND EC_GA20 USB20_P1 EXP_REQ# USB20_N1 RESERVED GND HDMI_HP USB20_P2 LPC_CLK0 USB20_N2 GND GND HDMI_SDA USB20_P0 HDMI_SCL USB20_N0 GND GND TX2D+ PANEL_BKEN_MCH TX2DENVDD GND LDDC_DATA_MCH TX1D+ LDDC_CLK_MCH TX1DCRT_VSYNC GND CRT_HSYNC TX0D+ GND TX0DG_DAT_DDC2 GND G_CLK_DDC2 TXCD+ GND TXCDCRT_RED GND GND WLAN_REQ# CRT_GRN WLAN_SMDATA GND WLAN_SMCLK CRT_BLU PCIE_WAKE# GND PCIE_PME LCD_A1+_MCH CLK_48M_CR LCD_A1-_MCH LAN_REQ# GND CLK_PCIE_EXP LCD_A0+_MCH CLK_PCIE_EXP# LCD_A0-_MCH GND GND CLK_PCIE_MINI LCD_A2+_MCH CLK_PCIE_MINI# LCD_A2-_MCH HDI_B_DET/GND GND CLK_PCIE_LAN# LCD_ACLK+_MCH CLK_PCIE_LAN LCD_ACLK-_MCH 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 +5VS +5VALW VL +3VALW +3VS VR_ON [31] D SB_SPKR [24] HDA_RST# [23] HDA_SDOUT [23] HDA_SYNC [23] HDA_BITCLK [23] HDA_SDIN0 [23] HDA_SDIN1 [23] IDE_LED# [23] SATA_TXP0_CR [23] SATA_TXN0_CR [23] THERM_SCI# [24] GPIO42 [24] SATA_TXP1_CR SATA_TXN1_CR HDA GPIO [23] [23] +1.5VS SATA_TXP2_CR SATA_TXN2_CR [23] [23] SATA_RXP2_C SATA_RXN2_C [23] [23] SATA_RXP0_C SATA_RXN0_C [23] [23] USB20_P7 USB20_N7 [23] [23] USB20_P5 USB20_N5 [24] [24] USB20_P4 USB20_N4 [24] [24] GPIO44 C [24] [24] SATA_RXP1_C SATA_RXN1_C USB20_P3 USB20_N3 SATA [24] [24] USB [24] USB20_P8 USB20_N8 [24] [24] USB20_P6 USB20_N6 [24] [24] USB20_P1 USB20_N1 [24] [24] USB20_P2 USB20_N2 [24] [24] USB20_P0 USB20_N0 [24] [24] B ENABLT [18] ENAVDD [18] DDC2_DATA [18] DDC2_CLK [18] CRT_VSYNC [17,18] CRT_HSYNC [17,18] CRT_DDC_DATA [18] CRT_DDC_CLK [18] D_RED [18] D_GREEN D_BLUE [18] [18] TXOUT_L1+ [18] TXOUT_L1- [18] TXOUT_L0+ [18] TXOUT_L0- [18] LVDS TXOUT_L2+ [18] TXOUT_L2- [18] TXCLK_L+ [18] TXCLK_L- [18] A HDI_B_DET FPC_O0P45X2P35 Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Golden finger Size Document Number Rev 0.3 LS-5588 Date: Sheet Wednesday, July 01, 2009 1 26 of 35 5 4 3 2 1 +1.5V to +1.5VS +1.5V +1.5VS U13 D 1 2 H_3P2 H1 HOLEA H_4P2 H6 HOLEA H_1P8N H10 HOLEA H3 HOLEA H4 HOLEA H5 HOLEA 2 C1184 0.1U_0603_25V7K FM1 1 +VCCP +1.8VS +1.5V +0.75VS +1.5VS +1.1VS H8 HOLEA H9 HOLEA H11 HOLEA C 1 C H7 HOLEA 1 C1182 0.1U_0603_25V7K 2 1 2 1 @ 1 S 1 3 Q25 2N7002_SOT23 1 R443 0_0402_5% @ G 1 D 2 1 SUSP 1 +1.5VS_GATE R396 100K_0402_5% H2 HOLEA 1 2 C1181 1 1 1 C1193 1 1 2 3 4 S S S G SI4800BDY-T1-E3_SO8 1 B+ D D D D 1U_0603_10V4Z 2 10U_0805_10V4Z C1183 1 10U_0805_10V4Z 8 7 6 5 D FM2 1 FM3 1 FM4 1 +3.3V_DELAY R312 R314 1 1 1 1 R311 R313 R315 1 R310 +5VALW 1 R309 1 1 1 +5VALW R307 Q77 2N7002_SOT23 R03 SYSON SYSON 2 1 [26,28] D8 SUSP# 1 2 3 2 Q17A G SUSP Q17B 5 SUSP# SUSP# [20] 4 S 6 D 2 2N7002DW-7-F_SOT363-6 SUSP B 100K_0402_5% 2N7002DW-7-F_SOT363-6 2 SYSON# 1 5 100K_0402_5% 3 2 3 Q20B SUSP 4 2 R308 470_0402_5% 2N7002DW-7-F_SOT363-6 2 6 Q20A SUSP 1 5 470_0402_5% 2N7002DW-7-F_SOT363-6 2 Q19B SUSP 2N7002DW-7-F_SOT363-6 2 3 2 6 Q19A SYSON# 470_0402_5% 4 5 1 2 3 Q18B SUSP 470_0402_5% 2N7002DW-7-F_SOT363-6 1 2 470_0402_5% 4 6 Q18A SUSP 2N7002DW-7-F_SOT363-6 2 470_0402_5% 2N7002DW-7-F_SOT363-6 470_0402_5% B R326 2 1 CH751H-40_SC76 2 +1.8VSPEN [32] 470_0402_5% A A Compal Secret Data Security Classification 2009/04/20 Issued Date 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. DC/DC Interface Size Document Number Custom LS-5588 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 27 of 35 A B C D 1 1 PR400 0_0402_5% 1 SYSON HCB1608KF-121T30_0603 1 4 TPS51117RGYR_QFN14_3.5x3.5 1.5V_PGOOD PR410 100K_0402_1% 2 1 2 PC404 4.7U_0805_25V6M 1 2 PC403 4.7U_0805_25V6-K 1 2 PR408 4.7_1206_5% 1 PC409 4.7U_0805_6.3V6K + 2 220U_B2_2.5VM_R25M PC410 PC411 680P_0603_50V8J +1.5VP 1 1 PC402 0.1U_0402_25V6 PQ400 NTMS4816NR2G_SO8 3 2 1 PC407 4.7U_0805_10V6K 1 LG_1.5V 10.7K_0402_1% 1 9 2 2 2 DRVL 2 3 2 1 @22P_0402_50V8J PC412 VBST TP 7 1 2 1 2 [8] 14 1 2 PC408 @10P_0402_50V8J PR409 10K_0402_1% 15 V5DRV PGOOD +1.5VP PL401 1UH_PCMB103E-1R0MS_20A_20% 1 PR406 B+ 2 1 VFB 1.5V_TRIP 1 +5VALW UG1_1.5V 1 6 11 10 2 1 5 TRIP LX_1.5V 2 2 1 +1.5VP 2 PC406 4.7U_0805_6.3V6K 1.5V_VFB 2 LL V5FILT 12 1 PQ401 NTMFS4946NT1G_SO8FL-5 1 VOUT UG_1.5V 2 5 0_0402_5% 1.5V_VF5FILT 4 PR407 10K_0402_1% 13 1 PR404 2 DRVH 2 PR405 100_0402_1% PGND 2 1.5V_VOUT 3 1 TON PR403 0_0402_5% 8 +5VALW 1 2 2 GND 1 +1.5VP 4 EN_PSV PU400 PR402 255K_0402_1% 2 5 6 7 8 PR401 PC405 0_0402_5% 0.1U_0402_10V7K BST_1.5V 1 2 BST_1.5V-1 1 2 PC401 2200P_0402_50V7K 2 PC400 @0.1U_0402_16V7K +5VALW PL400 +1.5V_B+ 1.5V_EN 2 1 [26,27] 2 PC413 @ 0.47U_0402_6.3V6K PJP400 +1.5VP 2 2 1 1 +1.5V (8A,320mils ,Via NO.= 16) @ JUMP_43X118 3 3 4 4 Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size B C 1.5VP Document Number Rev 0.3 LS5588P Date: A Compal Electronics, Inc. Wednesday, July 01, 2009 Sheet D 28 of 35 5 4 3 2 1 PR516 PL501 VCCP_B+ 1 HCB1608KF-121T30_0603 0_0402_5% PC519 @1000P_0402_50V7K C PC527 14 9 LG_VCCP TP VBST 1 2 PC507 4.7U_0805_25V6-K 2 1 PC506 4.7U_0805_25V6-K 1 2 3 2 1 5 6 7 8 2 PQ504 PR513 4.7_1206_5% PC521 4.7U_0805_10V6K 1 + 2 2 10 1 2 13.7K_0402_1% 4 PC514 4.7U_0805_6.3V6K 1 DRVL PR517 1 1 15 V5DRV 1 +5VALW TPS51117RGYR_QFN14_3.5x3.5 @22P_0402_50V8J 1 2 2 1 PR504 10K_0402_1% PGOOD 11 D PL503 2.2UH_PCMC063T-2R2MN_8A_20% AO4710_SO8 2 2 PC526 @10P_0402_50V8J VFB 12 B+ +1.05VCCP 2 3 2 1 1 6 TRIP 1 PC505 0.1U_0402_25V6 1 5 LL V5FILT LX_VCCP 1 2 4.12K_0402_1% VOUT 13 2 +1.05VCCP PR503 PGND 1 2 3 0_0402_5% 4 1 PC520 4.7U_0805_6.3V6K 2 PR519 DRVH UG1_VCCP 8 1 +1.05VCCP PR518 +5VALW 1 100_0402_1% 2 7 +5VALW TON GND 2 2 1 PR509 0_0402_5% UG_VCCP 2 PQ502 AO4466_SO8 4 EN_PSV PU501 PR524 255K_0402_1% 5 6 7 8 PR511 PC511 0_0402_5% 0.1U_0402_10V7K BST_VCCP 1 2 1 2 2 2 D PC504 2200P_0402_50V7K 1 1 1 2 SUSP# 2 [20] PC515 220U_B2_2.5VM_R25M PC517 680P_0603_50V8J C PJP500 +1.05VCCP 1 2 +VCCP (8A,120mils ,Via NO.= 6) PAD-OPEN 4x4m B B A A Compal Secret Data Security Classification Issued Date 2006/11/23 Deciphered Date 2007/11/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. 1.05VCCP Size Document Number Rev 0.3 LS5588P Date: Wednesday, July 01, 2009 Sheet 1 29 of 35 A B C D 1 1 +1.5V PU600 VIN 2 VCNTL GND NC VREF NC VOUT NC 6 +5VALW 5 3 2 4 7 8 2 PR600 1K_0402_1% 1 1 1 2 10U_0805_10V4Z PC601 1 2 +5VALW 10U_0805_6.3V6M PC600 1 TP PC602 1U_0603_10V6K 9 1 G2992F1U_SO8 PC605 @0.1U_0402_16V7K 2 2 G PQ601 RHU002N06_SOT323-3 1 2 1 2 2 S S PQ600 RHU002N06_SOT323-3 PR603 0_0402_5% 1 1 2 [20] SUSP# 3 1 3 G 2 PC603 0.1U_0402_10V7K PR602 1K_0402_1% 2 1 D 2 D +0.75VSP 1 PR601 10K_0402_5% PC604 10U_0805_6.3V6M 2 PJP600 +0.75VSP 1 2 +0.75VS (2A,80mils ,Via NO.= 4) PAD-OPEN 3x3m 3 3 4 4 Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size B C 0.75VSP Document Number Rev 0.3 LS5588P Date: A Compal Electronics, Inc. Wednesday, July 01, 2009 Sheet D 30 of 35 5 4 3 2 1 2 +VCCP D [5] +CPU_B+ 2 9 1 1 2 1 4.7U_0805_25V6-K PC206 1 2 4.7U_0805_25V6-K PC205 1 2 4.7U_0805_25V6-K PC204 1 2 3 2 1 VID3 VSS VIN 19 18 1 1 1 5 PQ201 NTMFS4946NT1G_SO8FL-5 PR214 7.68K_0805_1% 2 4 2 LGATE_CPU1 1 UGATE_CPU1 22 BOOT_CPU1 2 PHASE_CPU1 23 +VCC_CORE C PR213 4.7_1206_5% 24 2 3 2 1 VID4 VID5 VID6 PL201 0.45UH_ETQP4LR45XFC_25A_-25+20% 2 PC213 680P_0603_50V8J 21 NC ISL6261ACRZ-T_QFN40_6X6 PH3 under CPU botten side : CPU thermal protection at 85 degree C Recovery at 45 degree C PR218 464K_0402_1% 2 2200P_0402_50V7K PC202 1 5 6 7 8 1 PC210 1U_0603_10V6K 1 2 PC209 0.01U_0402_16V7K 31 32 33 1 2 PR208 0_0402_5% 35 36 38 39 37 DPRSTP# VR_ON VO VSUM 17 11 16 2 1 25 BOOT FB PC214 1000P_0402_50V7K PR212 0_0603_5% 2 1 1 PR217 6.81K_0402_1% 3V3 UGATE COMP 10 2 VW DFB 1 8 PHASE 29 26 VSSP OCSET 15 PR216 14.7K_0402_1% CLK_EN SOFT 7 1 27 LGATE VDD 6 2 PC212 0.015U_0603_25V7K 30 28 VCCP NTC DROOP 1 B+ VSUM @4.22K_0402_1% VR_TT# 5 2 PQ200 NTMS4816NR2G_SO8 4 20 4 2 14 1 VID0 RTN 2 RBIAS VSEN PR215 VID1 13 H_PROCHOT# PH201 @100K_0603_1%_TH11-4H104FT [4] H_PROCHOT# 1 3 2 1 PC211 0.22U_0603_10V7K VID2 PMON 12 1 DPRSLPVR 2 2 PR211 147K_0402_1% 34 1 1 PM_PWROK GND PAD FDE VDIFF 1 2 2 1 40 41 PU200 PC200 @0.1U_0402_16V7K PGOOD 1 VGATE PR210 @40.2K_0402_1% [8,24,26] PC208 2 2 2 PR207 1.91K_0402_1% PR209 @ 0_0402_5% C 1U_0603_6.3V6M 1 1 2 PR229 @ 0_0402_5% 2 1 PR205 0_0402_5% 1 0.1U_0603_50V7K PC201 PR204 1_0603_5% VR_ON +3VALW [24,26] PL200 HCB2012KF-121T50_0805 2 [5] [5] CPU_VID0 CPU_VID1 [5] [5] +5VALW 2 [26] H_PROCHOT# H_DPRSTP# VR_ON [5,8,23] 2 CPU_VID2 [5] 1 PR203 0_0402_5% 1 [5] 2 [26] CPU_VID3 1 PM_DPRSLPVR CPU_VID4 PR202 0_0402_5% [8,24] CPU_VID5 PR200 @ 68_0402_5% CPU_VID6 D 2 PC215 150P_0402_50V8J 2 1 1 [26] 1 D 3 8 + O - 4 2 2 TM-3 1 S PU7A LM393DG_SO8 1 PQ4 2N7002KW_SOT323-3 2 G VL 5 PR35 100K_0402_1% 2 6 + P 8 PR34 100K_0402_1% - G 1 1 1 O 4 +VCC_CORE MAINPWON 2 P 3 G 2 1 1 2 1 2 2 1 2 1 2008-07-17 2 PR228 11K_0402_1% PH200 10KB_0603_5%_ERTJ1VR103J PR33 21.5K_0402_1% PR227 1K_0402_1% 2 2 1 1 PR224 3.57K_0402_1% PC18 0.22U_0402_6.3V6K 2 PR29 47K_0402_1% TM-2 TM_REF1 1 1 2 2 PC223 330P_0402_50V7K 1 PC225 0.1U_0402_10V7K PC222 330P_0402_50V7K 2 1 2 PR225 0_0402_5% VSUM PR28 47K_0402_1% PR30 13.7K_0402_1% PH 2 PC221 1000P_0402_50V7K 1 VSSSENSE 2 1 [5] 1000P_0603_50V7K 1 1 2 PR223 0_0402_5% PC224 0.1U_0402_10V7K 1 2 VCCSENSE 2 2 PC220 [5] +CPU_B+ 1 2.21K_0402_1% 1 2 1 1 PC219 0.22U_0603_25V7K 2 2 PR222 B PC64 0.01U_0402_25V7K PR220 10_0603_5% PC19 1000P_0402_50V7K 1 VL PC217 1U_0603_10V6K PH1 2 VL +5VALW 2 1 PC218 390P_0402_50V7K PR221 330_0402_1% 1 2 PC216 47P_0402_50V8J VL 2 PR219 10_0603_5% PR226 4.53K_0402_1% B 2 100K_0603_1%_TH11-4H104FT 1 1 7 PU7B LM393DG_SO8 A PC226 0.22U_0603_10V7K 1 2 A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2005/06/23 2006/10/22 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title CPU_CORE Size Document Number Custom IAX00 Date: Rev 0.3 Wednesday, July 01, 2009 Sheet 1 31 of 35 2 +5VS 2 PC701 10U_0805_6.3V6M 1 +3VS 1 B 1 A C D PC702 1U_0402_6.3V6K 1 PU701 FB 2 APL5913-KAC-TRL_SO8 0.47U_0402_6.3V6K 1 1 1 2 1 PC703 2 EN POK 2 8 7 PC704 0.01U_0402_25V7K +1.8VSP 1 +1.8VSPEN R03 3 4 2 2 +1.8VSPEN VOUT VOUT GND 1 SUSP# 1 [20] [27] VCNTL VIN VIN PR702 4.64K_0402_1% 6 5 9 PR701 100K_0402_5% PC705 10U_0805_6.3V6M 2 PR703 3.65K_0402_1% PJP701 +1.8VSP 1 2 +1.8VS PAD-OPEN 4x4m 2 2 3 3 4 4 Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size 1.8VSP Document Number Rev 0.3 LS5588P Date: C Compal Electronics, Inc. Wednesday, July 01, 2009 Sheet D 32 of 35 4 3 PU801 TPS51117RGYR_QFN14_3.5x3.5 PC812 @ 47P_0402_50V8J 1 2 1 2 PC808 10U_0805_6.3V6M 1 2 5 6 7 8 PC807 10U_0805_6.3V6M 1 + 2 2 PC806 10U_0805_6.3V6M 1 PC805 330U_D2_2.5VY_R15M PC810 4.7U_0805_6.3V6K 4 1 1 2 1 PC802 10U_1206_25V6M PC801 10U_1206_25V6M 2 4 +VGA_COREP 2 PR808 10_0402_5% 9 LG_VGA +5VALW PR805 4.7_1206_5% 10 VGA_TRIP 1 2 PR807 9.1K_0402_1% 1 SW_VGA 11 D PC811 680P_0603_50V7K DRVL 12 1 PGOOD UG_VGA B+ PL802 1UH_PCMB103E-1R0MS_20A_20% 1 2 1VGA_SNB 2 V5DRV 13 PQ802 SI4634DY-T1-E3_SO8 TRIP VFB PQ801 SI4686DY-T1-E3_SO8 3 2 1 14 15 TP EN_PSV LL V5FILT PGND 6 VOUT GND PC809 4.7U_0805_6.3V6K 4 5 PR809 @0_0402_5% 2 1 2 1 VGA_FB 3 DRVH 8 VGA_V5FILT TON 7 PR806 100_0402_1% 2 2 VBST 1 PC804 @0.1U_0402_16V7K 2 1 2 1 4 0.1U_0603_25V7K PR804 0_0402_5% +VGA_COREP 2 1VGA_VOUT +5VALW 5 6 7 8 PR803 PC803 0_0402_5% BST_VGA 1 2BST_VGA-1 1 2 VGA_EN PQ803 SI4634DY-T1-E3_SO8 @ 5 6 7 8 PR802 0_0402_5% 1 2 SUSP# PD801 1SS355_SOD323-2 1 2 +5VS 3 2 1 [20] HCB1608KF-121T30_0603 1 2 VGA_IN 2 DGPU_PWR_EN PR815 0_0402_5% 1 2 1 PL801 PR801 205K_0402_1% 1 2 VGA_TON D 2 3 2 1 5 C C DGPU_RUN_PWROK PR810 10K_0402_1% 1 2 VGA_FB1 2 1 1 2 PR813 36.5K_0402_1% 2 1 1 +VGA_CORE @ JUMP_43X118 PJP803 D +1.5VS 2 +5VS 2 1 1 S PQ805 SSM3K7002FU_SC70-3 GVID1-2 D S PQ804 SSM3K7002FU_SC70-3 2 PC707 10U_0805_6.3V6M 2 1 1 PC710 1U_0402_6.3V6K B 1 1 2 PC709 10U_0805_6.3V6M 1 +1.1VSP 2 PC706 0.47U_0402_6.3V6K PC708 0.01U_0402_25V7K 2 APL5913-KAC-TRL_SO8 2 FB 3 4 1 PR705 0_0402_5% 1 2 SUSP# EN POK VOUT VOUT 1 B 8 7 VCNTL VIN VIN 2 [20] @ 6 5 9 1 DGPU_PWR_EN PR707 0_0402_5% 1 2 PR706 1.43K_0402_1% PU702 PC813 0.022U_0402_16V7K GND 3 @ JUMP_43X118 3 1 2 2 +VGA_COREP 1 2 PR812 115K_0402_1% 2 G 2 1GVID1-1 2 PR814 G 10K_0402_1% +VGASENSE [20] PJP802 1 PR816 10K_0402_1% [18] VGA_PWRSEL0 PR811 0_0402_5% 1 2 1 +5VS VGA_PWRSEL0 VGA_CORE 0 1V 2 PR704 3.65K_0402_1% PJP702 1 +1.1VSP 2 +1.1VS PAD-OPEN 4x4m 1 0.95V A A 2007/11/12 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/11/12 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title VGA_CORE/1.1V Size Date: 3 2 Document Number Rev 0.3 Wednesday, July 01, 2009 Sheet 1 33 of 35 5 4 3 2 Version change list (P.I.R. List) Item D 1 Page 1 of 1 for PWR Fixed Issue Reason for change Rev. PG# Modify List Date Phase D 1 2 3 4 5 6 7 C C 8 9 10 11 12 13 B 14 B 15 16 17 18 19 20 21 A A 22 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title PIR (PWR) Size Document Number Custom Date: 5 4 3 2 Rev 0.3 Wednesday, July 01, 2009 Sheet 1 34 of 35 5 Item 1 D 4 Fixed Issue 3 Reason for change Rev. 2 PG# Date Modify List Phase add PU7,PH1,PC18,PC19,PC64,PR33,PR30,PR34,PR35,PR29,PR28,PQ4 1.0 Change OVT Circuit 1 2 D 3 4 5 6 7 8 C 9 C 10 11 12 13 14 15 16 B 17 B 18 19 20 21 22 A A Compal Secret Data Security Classification Issued Date 2009/04/20 2010/04/30 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. HW Changed-List History-1 Size Document Number Rev 0.3 LS-5588 Date: Wednesday, July 01, 2009 Sheet 1 35 of 35
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