Cortex M4 Devices Generic User Guide
Cortex-M4%20Devices%20Generic%20User%20Guide
Cortex_m4%20Generic%20User%20Guide
DUI0553A_cortex_m4_Generic_User_Guide
cortex_m4_User_Guide
CortexM4_Generic_Users_Guide_DUI0553A_cortex_m4_dgug
User Manual:
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- Cortex-M4 Devices Generic User Guide
- Contents
- Preface
- Introduction
- The Cortex-M4 Processor
- 2.1 Programmers model
- 2.2 Memory model
- 2.2.1 Memory regions, types and attributes
- 2.2.2 Memory system ordering of memory accesses
- 2.2.3 Behavior of memory accesses
- 2.2.4 Software ordering of memory accesses
- 2.2.5 Optional bit-banding
- 2.2.6 Memory endianness
- 2.2.7 Synchronization primitives
- 2.2.8 Programming hints for the synchronization primitives
- 2.3 Exception model
- 2.4 Fault handling
- 2.5 Power management
- The Cortex-M4 Instruction Set
- 3.1 Instruction set summary
- 3.2 CMSIS functions
- 3.3 About the instruction descriptions
- 3.4 Memory access instructions
- 3.5 General data processing instructions
- 3.5.1 ADD, ADC, SUB, SBC, and RSB
- 3.5.2 AND, ORR, EOR, BIC, and ORN
- 3.5.3 ASR, LSL, LSR, ROR, and RRX
- 3.5.4 CLZ
- 3.5.5 CMP and CMN
- 3.5.6 MOV and MVN
- 3.5.7 MOVT
- 3.5.8 REV, REV16, REVSH, and RBIT
- 3.5.9 SADD16 and SADD8
- 3.5.10 SHADD16 and SHADD8
- 3.5.11 SHASX and SHSAX
- 3.5.12 SHSUB16 and SHSUB8
- 3.5.13 SSUB16 and SSUB8
- 3.5.14 SASX and SSAX
- 3.5.15 TST and TEQ
- 3.5.16 UADD16 and UADD8
- 3.5.17 UASX and USAX
- 3.5.18 UHADD16 and UHADD8
- 3.5.19 UHASX and UHSAX
- 3.5.20 UHSUB16 and UHSUB8
- 3.5.21 SEL
- 3.5.22 USAD8
- 3.5.23 USADA8
- 3.5.24 USUB16 and USUB8
- 3.6 Multiply and divide instructions
- 3.7 Saturating instructions
- 3.8 Packing and unpacking instructions
- 3.9 Bitfield instructions
- 3.10 Branch and control instructions
- 3.11 Floating-point instructions
- 3.11.1 VABS
- 3.11.2 VADD
- 3.11.3 VCMP, VCMPE
- 3.11.4 VCVT, VCVTR between floating-point and integer
- 3.11.5 VCVT between floating-point and fixed-point
- 3.11.6 VCVTB, VCVTT
- 3.11.7 VDIV
- 3.11.8 VFMA, VFMS
- 3.11.9 VFNMA, VFNMS
- 3.11.10 VLDM
- 3.11.11 VLDR
- 3.11.12 VLMA, VLMS
- 3.11.13 VMOV Immediate
- 3.11.14 VMOV Register
- 3.11.15 VMOV Scalar to ARM Core register
- 3.11.16 VMOV ARM Core register to single precision
- 3.11.17 VMOV Two ARM Core registers to two single precision
- 3.11.18 VMOV ARM Core register to scalar
- 3.11.19 VMRS
- 3.11.20 VMSR
- 3.11.21 VMUL
- 3.11.22 VNEG
- 3.11.23 VNMLA, VNMLS, VNMUL
- 3.11.24 VPOP
- 3.11.25 VPUSH
- 3.11.26 VSQRT
- 3.11.27 VSTM
- 3.11.28 VSTR
- 3.11.29 VSUB
- 3.12 Miscellaneous instructions
- Cortex-M4 Peripherals
- 4.1 About the Cortex-M4 peripherals
- 4.2 Nested Vectored Interrupt Controller
- 4.2.1 Accessing the Cortex-M4 NVIC registers using CMSIS
- 4.2.2 Interrupt Set-enable Registers
- 4.2.3 Interrupt Clear-enable Registers
- 4.2.4 Interrupt Set-pending Registers
- 4.2.5 Interrupt Clear-pending Registers
- 4.2.6 Interrupt Active Bit Registers
- 4.2.7 Interrupt Priority Registers
- 4.2.8 Software Trigger Interrupt Register
- 4.2.9 Level-sensitive and pulse interrupts
- 4.2.10 NVIC usage hints and tips
- 4.3 System control block
- 4.3.1 Auxiliary Control Register
- 4.3.2 CPUID Base Register
- 4.3.3 Interrupt Control and State Register
- 4.3.4 Vector Table Offset Register
- 4.3.5 Application Interrupt and Reset Control Register
- 4.3.6 System Control Register
- 4.3.7 Configuration and Control Register
- 4.3.8 System Handler Priority Registers
- 4.3.9 System Handler Control and State Register
- 4.3.10 Configurable Fault Status Register
- 4.3.11 HardFault Status Register
- 4.3.12 MemManage Fault Address Register
- 4.3.13 BusFault Address Register
- 4.3.14 Auxiliary Fault Status Register
- 4.3.15 System control block usage hints and tips
- 4.4 System timer, SysTick
- 4.5 Optional Memory Protection Unit
- 4.6 Floating Point Unit (FPU)
- Cortex-M4 Options
- Glossary