TRM_PSoC5 Cypress PSo C5LP Technical Reference Manual
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- PSoC 5LP TRM
- Contents Overview
- Contents
- Section A: Overview
- Section B: CPU System
- Top Level Architecture
- 4. Cortex™-M3 Microcontroller
- 5. PSoC 5LP Cache Controller
- 6. PHUB and DMAC
- 7. Interrupt Controller
- Section C: Memory
- Section D: System Wide Resources
- Top Level Architecture
- 14. Clocking System
- 14.1 Features
- 14.2 Block Diagram
- 14.3 Clock Sources
- 14.4 Clock Distribution
- 14.5 Low-Power Mode Operation
- 14.6 Clock Naming Summary
- 15. Power Supply and Monitoring
- 16. Low-Power Modes
- 17. Watchdog Timer
- 18. Reset
- 19. I/O System
- 19.1 Features
- 19.2 Block Diagrams
- 19.3 How It Works
- 19.3.1 Usage Modes and Configuration
- 19.3.2 I/O Drive Modes
- 19.3.3 Slew Rate Control
- 19.3.4 Digital I/O Controlled by Port Register
- 19.3.5 Digital I/O Controlled Through DSI
- 19.3.6 Analog I/O
- 19.3.7 LCD Drive
- 19.3.8 CapSense
- 19.3.9 External Memory Interface (EMIF)
- 19.3.10 SIO Functions and Features
- 19.3.11 Special Functionality
- 19.3.12 I/O Port Reconfiguration
- 19.3.13 Power Up I/O Configuration
- 19.3.14 Overvoltage Tolerance
- 19.3.15 I/O Power Supply
- 19.3.16 Sleep Mode Behavior
- 19.3.17 Low-power Behavior
- 19.4 Port Interrupt Controller Unit
- 19.5 Register Summary
- 20. Flash, Configuration Protection
- Section E: Digital System
- Top Level Architecture
- 21. Universal Digital Blocks (UDBs)
- 22. UDB Array and Digital System Interconnect
- 23. Controller Area Network (CAN)
- 24. USB
- 25. Timer, Counter, and PWM
- 26. I2C
- 27. Digital Filter Block (DFB)
- Section F: Analog System
- Top Level Architecture
- 28. Switched Capacitor/Continuous Time
- 29. Analog Routing
- 30. Comparators
- 31. Opamp
- 32. LCD Direct Drive
- 33. CapSense
- 34. Temperature Sensor
- 35. Digital-to-Analog Converter
- 36. Precision Reference
- 37. Delta Sigma Converter
- 38. Successive Approximation Register ADC
- Section G: Program and Debug
- Glossary
- Index