DDR2 DDR3 SDRAM Pcb Design Guide

User Manual:

Open the PDF directly: View PDF PDF.
Page Count: 16

Scroll down to view the document on your mobile browser.
 Signal Integrity and PCB layout considerations for DDR2-800 Mb/s and DDR3 Memories  Fidus Systems Inc. 900, Morrison Drive, Ottawa, Ontario, K2H 8K7, Canada Chris Brennan, Cristian Tudor, Eric Schroeter, Heike Wunschmann, and Syed Bokhari Session # 8.13
Abstract  The paper addresses the challenge of meeting Signal Integrity (SI) and Power Integrity (PI) requirements of Printed Circuit Boards (PCBs) containing Double Data Rate 2 (DDR2) memories. The emphasis is on low layer count PCBs, typically 4-6 layers using conventional technology.  Some design guidelines have been provided.       1. Introduction  DDR2 usage is common today with a push towards higher speeds such as 800 Mbps [1] and more recently, 1066 Mbps.  DDR3 [2] targets a data rate of 1600 Mbps.  From a PCB implementation standpoint, a primary requirement is delay matching which is dictated by the timing requirement. This brings into it a number of related factors that affect waveform integrity and delay.  These factors are interdependent, but where a distinction can be made, they can be termed PCB layer stackup and impedance, interconnect topologies, delay matching, cross talk, PI and timing. Cadence ALLEGRO™SI-230 and Ansoft’s HFSS™ are used in all computations.             Technology  DDR2   VDD /  Vref DDR3 Max Clock Freq. (MHz)/Data rate(Mbps)  533/1066  800/1600  Power Requirement VDD (Volts)  1.8 +/- 0.1  1.5  +/- 0.075 Vtt (Volts)  0.9 +/- 0.04  0.75 +/- TBD Vref (Volts)  0.9  +/-  0.018  0.75 +/- 0.015 Input Thresholds Vih/Vil (Volts)  0.9  +/-  0.2  0.75 +/- 0.175  Delay Matching Requirement  Match ADDR/CMD/CNTRL to Clock tightly  Yes  Yes Match DQ<7,0>, DM0 to DQS0 tightly  Yes  Yes Match DQ<15,8>, DM1 to DQS1 tightly  Yes  Yes Match DQ<22,16>, DM2 to DQS2 tightly  Yes  Yes Match DQ<31,23>, DM3 to DQS3 tightly  Yes  Yes Match DQS0-3  to Clock loosely  Yes  Not required               Table 1:  Comparison of DDR2 and DDR3 requirements CKE, CS, ODT, RAS,CAS,WE,BA0-2ADDR<15,0>Clock  CKP,CKN Address  Command/ Control DataStrobe (differential) DataMask  Data   Controller VDD / Vtt / Vref                       DQS0,DQS1,DQS2,DQS3    DM0,DM1,DM2,DM3   DQ <7,0>, DQ<15,8>,DQ<23,16>, DQ<31,24>  Memory

Navigation menu