DEC 11 HBMAA E D BM792 Read Only Memory And MR11 DB Bootstrap Loader
DEC-11-HBMAA-E-D BM792 Read-Only-Memory and MR11-DB Bootstrap Loader DEC-11-HBMAA-E-D BM792 Read-Only-Memory and MR11-DB Bootstrap Loader
User Manual: DEC-11-HBMAA-E-D BM792 Read-Only-Memory and MR11-DB Bootstrap Loader
Open the PDF directly: View PDF 
.
Page Count: 54
| Download | |
| Open PDF In Browser | View PDF |
BM792
read-only-memory
and MR11-DB
bootstrap loader
l
(
DEC-II-HBMAA-E-D
BM792
read-only-memory
and MR11~DB
bootstrap loader
digital equipment corporation maynard. massachusetts
0
1st Edition, July 1971
2 ns Printing, December 1971
3rd Printing (Rev), October 1972
4th Printing, December 1972
5th Printing, May 1973
6th Printing (Rev), January 1974
Copyright © 1971, 1972, 1973, and 1974 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Printed in U.S.A.
The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
PDP
FOCAL
COMPUTER LAB
CONTENTS
Page
CHAPTER 1 INTRODUCTION
1.1
1.2
1-1
1-1
SCOPE
GENERAL DESCRIPTION
CHAPTER 2 DETAILED DESCRIPTION
2.1
2.2
2.3
2.4
2.5
BASIC OPERATION
ADDRESS SELECTION
WORD SELECTION
DIODE MATRIX AND OUTPUT BUFFER
ANODE RECOVERY CIRCUIT
2-1
2-1
2-3
2-4
2-6
CHAPTER 3 PROGRAMMING AND OPERATION
3.1
3.2
GENERAL
PROGRAMMING THE ROM
3-1
3-1
CHAPTER 4 ROM ENGINEERING DRAWINGS
APPENDIX A BM792-YA PAPER-TAPE BOOTSTRAP LOADER
APPENDlXB BM792-YB BULK STORAGE BOOTSTRAP LOADER
APPENDlXC BM792-YC CARD READER BOOTSTRAP LOADER
APPENDlXD MRII-DB BULK STORAGE BOOTSTRAP LOADER
APPENDIXE BM792-YF BULK STORAGE BOOTSTRAP LOADER
APPENDlXF BM792-YH CASSETTE BOOTSTRAP LOADER
ILLUSTRATIONS
Figure No.
2-1
2-2
2-3
2-4
2-5
2-6
3-1
Title
Page
ROM Block Diagram
ROM Address Word Format
Simplified Logic Diagram of ROM Address Selection Circuits for
Addresses 773400 - 773476
Word Selection Circuit for 773X04 Address
Diode Matrix and Output Buffer, Simplified Logic Diagram
Anode Recovery Circuit
Physical Locations of Addresses and Bits in the ROM Diode Matrix
2-1
2-2
2-3
iii
2-4
2-5
2-6
3-3
TABLES
Table No.
I-I
2-1
2-2
A-I
B-1
C-I
D-I
D-2
D-3
E-I
F-I
Title
Preprogrammed ROMs
ROM Addresses
BCD Decoder Truth Table
BM792-YA Paper-Tape Bootstrap Loader Program
BM792-YB Bulk Storage Bootstrap Loader Program
BM792-YC Card Reader Bootstrap Loader Program
MR II-DB Bulk Storage Program Loader Listing
Starting Address
Power Up Start Vector Jumper Connections
BM792-YF Bulk Storage Bootstrap Loader Program
BM792-YH Cassette Bootstrap Loader Program
iv
Page
1-2
2-2
2-5
A-3
B-2
C-3
D-3
D-4
D-4
E-2
F-2
CHAPTER 1
INTRODUCTION
1.1 SCOPE
This manual provides the user with theory of operation, programming information, and schematics necessary to
understand and program the BM792 Read-Only-Memory (ROM). The level of discussion assumes that the reader
is familiar with basic digital computer theory.
Although the input and output signals of the ROM are carried by the Unibus
@ , it is beyond the scope of this
manual to describe the Unibus itself. A detailed description of the Unibus is presented in the PDP-ii Peripherals
Handbook.
1.2 GENERAL DESCRIPTION
The BM792 is a 32-word read-only-memory (ROM). The diode matrix and address selection circuits that constitute the ROM are mounted on an extra-width quad-board module. This module is inserted in either one of the
two small peripheral controller slots in the PDP-II processor or in one of the four slots in the DD-ll peripheral
mounting panel.
The ROM is available either unprogrammed (designated BM792) or preprogrammed (designated BM792-Y X,
where the letter in the X position identifies the program). The unprogrammed module can be programmed to
form code conversion tables or contain frequently-used mathematical values and subroutines. These applications
of the ROM provide an access time of 100 ns, which can increase the program speed.
Preprogrammed ROMs are used for implementing small standard programs required in PDP-Il System operation,
such as bootstrap loaders for paper tape or DECtape. The preprogrammed ROMs that are available at publication of this manual are described in the Appendices and listed in Table 1-1. As additional preprogrammed ROMs
become available, additional appendices will be published to describe them.
@ Unibus is a registered trademark of Digital Equipment Corporation.
1-1
Table 1-1
Preprogrammed ROMs
No. of Words
Read-In
Loading Area
KL, DL-A,
DL-B, PC, PR
162 max.
Highest Memory
No
TC, RC, RF,
RK,RP
256
o and up
773200-773277
No
CR,CM
Variable
Variable
64
773100-773277
Yes (Except TM)
TC, TM, RC,
RF,RK,RP
TM:256
Others:5l2
o and up
BM792-YF
32
773200-773277
No
TC,RK, RF
BM792-YH
32
773300-773377
Yes
TA
Module
Option
No. of Words
Address Range
Power-Up
Vector
M792-YA
BM792-YA
32
773000-773077
No
M792-YB
BM792-YB
32
773l00c 773l77
M792-YC
BM792-YC
32
M792-YD
M792-YE
MRll-DB
M792-YF
M792-YH
Devices
_ _ _ _ _ _ _ L....-_.
>-'
N
__________
o and up
256
o and up
64
--
-----------
---
---
-----------
CHAPTER 2
DETAILED DESCRIPTION
2.1
BASIC OPERATION
The ROM diode matrix contains 32 16-bit words, each of which can be applied to the bus under program control.
The ROM responds only to a DATI from the Unibus, DATO, DATOB, and DATIP are ignored. A block diagram
of the ROM is shown in Figure 2-1.
When both a DATI and a ROM address are sent to the ROM, the word in the addressed location of the diode
matrix is applied to the Unibus. When the ROM address is received, the 5-bit code on address lines AO 1 through
A05 is decoded to apply a signal to the cathodes of the diodes in the addressed word location. The word in the
addressed location is transferred through the output buffer to data lines DOO through DIS of the Unibus.
I
UNIBUS
A<06:17>
DATI
MSYN
SSYN
A<01:05>
ADDRESS
SELECTOR
ANODE
RECOVERY
SIGNAL
32 x 16
DIODE
MATRIX
1
WORD
SELECTOR
CATHODE
DRIVER
S I G N AL
r-------
OUTPUT
BUFFER
I
D<00:15>
11-0299
Figure 2-1
2.2
ROM Block Diagram
ADDRESS SELECTION
The address word format for the ROM is shown in Figure 2-2. Octal addresses for the ROM must be of the
773XXX format. The ROM reads-out only fuI116-bit words and does not issue byte data; thus, address bit AOO
is not used.
The addresses are further divided into eight groups, which are determined by address bits AOS, A07, and A06 and
listed ill Table 2-1.
2-1
WORD
SELECTION
ADDRESS
OCTAL
ADDRESS
7
3
3
GROUP
0-7
0-7
0-7
~~~~~~
ADDRESS
BIT ~-L__~-L__~-L__~~__~-L__~~__~~__~~__~~
11-0298
Figure 2-2 ROM Address Word Format
Table 2-1
ROM Addresses
Address Word Bit
Preprogrammed
ROMs
A08
A07
A06
Address Ranges
0
0
0
773000 - 773076
BM792-YA
0
0
I
773100-773176
BM792-YB, YD
0
1
0
773200 - 773276
BM792-YC, YE, YF
0
1
1
773300 - 773376
BM792-YH
1
0
0
773400 - 773476
1
0
1
773500 - 773576
1
1
0
773600 - 773676
1
1
1
773700 - 773776
In a PDP-II System, only one ROM module can be used for each of the eight address groups. Jumpers on the
module are connected in a configuration that causes the module to respond to its designated address group.
For example, when a ROM module is to be addressed in the group 773400 - 773476, bits A08, A07, and A06 of
the address word contain binary 100 as shown in Table 2-1. The bus lines for these bits are shown connected to
the circuits of the ROM in Figure 2-3, a simplified logic diagram of the address selection circuits. Figure 2-3 also
shows the address selection circuit jumpers connected to respond to address group 773400 - 773476. Asserted
bus lines are low and unasserted bus lines are high, so that the output of gate E 12 at pin 14 is high and the outputs
of pins 2 and 3 are low when a valid address is received. Each of the three outputs from the El2 gates is exclusive
NORed with a low or a high level, depending on the jumper configuration. The outputs of the three E13 gates
must be high to accomplish address selection; therefore, the jumper configuration shown responds to addresses in
the 773400 - 773476 group.
The signal, which results from the decoding of bits A08, A07, and A06, is gated with a signal generated by the
decoding of an address in the format 773XXX and receiving MSYN (Drawing D-CS-M792-0-1). The resulting
signal (pin 10 of gate E17) is gated with a signal generated by the decoding of a DATI on the control lines.
Therefore, pin 8 of gate El7 provides a low output signal when the ROM address, MSYN, and DATI are asserted
on the bus. This signal at pin 8 is used to accomplish the following in the ROM circuits (see Drawing
D-CS-M792-0-1):
1.
2.
3.
Assert SSYN on the bus.
Activate the word selection circuits.
Provide a gating signal to the output buffer.
2-2
+5V
H
PIN
L
CN2 BUS A08L
E13 TRUTH TABLE
EXCLUSIVE NOR
14
=
0
PIN
CP2
H
BUS A07L
=
0
PIN
C U1
:~[>-C
+5V
H
BUS
4
A06L~3
+5V
~
=
Wl
A
B
C
L
L
H
H
L
H
L
H
H
L
L
H
2/
I
11-0297
Figure 2-3 Simplified Logic Diagram of ROM Address Selection Circuits
for Addresses 773400 - 773476
2.3 WORD SELECTION
Bits A05 - AOI of the address word are decoded by the word selection circuits to select one of the 32 word locations in the diode matrix. A low-level signal is then applied to the diodes in the addressed word location, resulting in 16 bits of data being read out on the data bus lines.
Because address bit AOO is not connected to the ROM, byte addressing is ignored and a l6-bit word is read onto
the bus regardless of the state of AOO. In the octal coding of the address, AOO is considered in designating the
last octal digit. Therefore, the addresses of the words in the ROM use the following sequence:
773XOO
773X02
773X04
773X06
773XlO
773X12
etc.
An address of 773XO 1 would address the same location as 773XOO, and 773X03 would be the same as location
733X02.
A simplified logic diagram for the word selection circuits is shown in Figure 2-4. This diagram illustrates how
the circuits operate for a 773X04 address. Table 2-2 is a truth table for the Binary-Coded Decimal (BCD) decoders that are shown in the diagram and on Drawing D-CS-M792-0-1.
For address 773X04, binary code 000 10 is applied to the word selection circuits on address lines A05 - AOI as
shown in Figure 2-4. The D input of BCD 1 receives a low signal from the address selector circuits when addressing and bus signal conditions are satisfied. All inputs to BCD 1 are low with the result that output 0 is low (refer
to Table 2-2). Output 0 of BCD 1 is connected to input D of BCD 2. The other inputs of BCD 2 are as shown in
Figure 2-4 when address 773X04 is received. Table 2-2 shows that output 2 of BCD 2 is low with the input signal
configuration shown. Output 2 of BCD 2 is connected to the cathodes of the l6-bit positions of location 04 in
2-3
the ROM. The signal levels on the cathodes of the other 31 word locations are high. Thus, only the diodes in
location 04 are forward-biased, allowing the word in this location to be read by the output buffers and applied to
the Unibus.
TO CATHODES
OF DIODES IN LOCATION 04
EZZ
BCDZ
ABC
773X04
o (H)
1 (L)
BUS A03 L
L
14
H
D
L
L
BUS ADZ L
13
o (H)
BUS AOI L
o (H)
BUS A04 L
Z
13
L
o
A
L
L
o (H)
B E18 1
BCD 1
Z
BUS A05 L
L C
L
FROM
ADDRESS
SELECTOR
D
3
----:-L:::Ow~W::-::H:-::E:::N-::7=7:=:3X7."X:7.X,...A:-::D=D::-RE=:S=S-.---.J
MSYN.
a
DATI ARE RECEIVED
11-02.96
Figure 2-4 Word Selection Circuit for 773X04 Address
2.4 DIODE MATRIX AND OUTPUT BUFFER
The BM792 ROM is supplied with a complete diode matrix. A diode is wired into each of the 16-bit locations
of all 32 words. The binary content of each word is determined by the presence or absence of the diodes; thus,
the user can program the module by cutting out selected diodes. Presence of a diode in a bit location produces
a binary I and absence produces a binary O. The preprogrammed ROMs are manufactured with the diode configuration required for their programs.
A simplified logic diagram of the diode matrix and the output buffer is illustrated in Figure 2-5. The low output
buffer gating signal is present when the ROM address, MSYN, and DATI are asserted on the bus (refer to Paragraph 2.2). The word select signal is low when the particular word location is selected by the decoding of bits
A05 - AOI (refer to Paragraph 2.3).
Diode D492 for the DOl bit is in the circuit and is forward-biased. Therefore, a low level is gated with the output buffer gating signal, which results in the assertion of a low level on bus line DO I to signify a binary I. The
diode for the DOO bit is cut out of the circuit. Therefore, a high-level signal is gated with the output buffer gating signal, which results in the assertion of a high level on bus line DOO to signify a binary O. The remaining bit
positions in the word are read out on bus lines 002 through DOl 5 at the same time. The configuration of diodes
for the bit positions of the word determines the binary content of the word read out on the bus lines.
2-4
Table 2-2
BCD Decoder Truth Table
Input
Output
A
B
C
D
0
1
2
3
4
5
6
7
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
13
BUS 001
H
L=Low
H = High
TO REMAINING
DIODE POSITIONS
OF THIS WORD
ANODE
RECOVERY
SIGNAL
+5V
LOW
OUTPUT
BUFFER
GATING
SIGNAL
RI5
0495
I OUTPUT
0492
RI6
10
BUS 000
10-----
0528
LOW
WORD SELECT
SIGNAL
0 OUTPUl
11-0Z95
Figure 2-5 Diode Matrix and Output Buffer, Simplified Logic Diagram
2-5
2.5 ANODE RECOVERY CIRCUIT
The anode recovery circuit (see Figure 2-6) provides a voltage surge to the anodes of the diodes in the matrix
immediately after a word is read out. This voltage surge charges the capacitance of the diode in the matrix and
ensures that the anode lines in the matrix are at a high level for the next read out.
Transistors Q 1, Q2, and Q3 (see Figure 2-6) are turned off when the ROM is not being addressed. Pin 8 of E 17
goes from low to high when the bus addressing signals are concluded. The high signal turns on Ql and subsequentl~
Q2, which provides the positive voltage surge to the anodes of the diodes in the matrix.
Transistor Q3 of the anode recovery circuit is used as a clamp. When the voltage surge from the collector of Q2
reaches a high enough value, Q3 turns on and grounds out the surge.
+5V
+5V
R25
2K
+5V
02
R26
47
R24
1.5K
8.2K
TO ANODES
L---~I"v-....,..""'H>---
01
0 F D10 DE
MATR IX
+5V
R28
100
03
R27
100
11-0367
Figure 2-6 Anode Recovery Circuit
2-6
CHAPTER 3
PROGRAMMING AND OPERATION
3.1 GENERAL
The ROM operates in a manner similar to other memory devices that can be included in a PDP-II system. When
the ROM is used for storage of constants, the processor may be programmed to address the appropriate ROM
location for the required constant. When the ROM is used for storage of a subroutine, a jump instruction is used
to get into the subroutine and place the first address in the program counter. Then the program counter is
changed to address the other sequential steps in the subroutine. The last step of a subroutine stored on the ROM
should be either a jump instruction to a location out of the ROM or a return from subroutine instruction.
3.2 PROGRAMMING THE ROM
Programming the ROM is accomplished by cutting diodes out of the diode matrix in the configuration required
for the binary data words to be used. The diode must be removed for each bit position that is to read out as a
binary O.
The physical orientation of the diode matrix with respect to the addresses and -the bit positions is shown in Figure
3-1. Address 773XOO is shown with diodes removed in a configuration that reads out the binary word 1 010 010
all 101 a 11. With Figure 3-1 and a binary listing of up to 32 l6-bit words, the user can program his ROM module.
The ROM module must also be programmed to respond to one of the address groups determined by address bits
A08, A07, and A06 (refer to Table 2-1). Figure 3-1 shows the locations of the three sets of address-bit jumper
terminals which are labeled WI, W2, and W3 on the ROM printed circuit board. The relationship between the
jumper terminals and the address bit is as follows:
WI
W2
W3
A06
A07
A08
Jumper wires are connected across each of the three sets of jumper terminals on an unprogrammed ROM when it
is shipped from the factory. The jumper wire must be cut out from between the two terminals for each address
bit (A08, A07, or A06), that is a binary 1 in the ROM address used.
3-1
W3 (A08)
JUMPER
TERMINALS
W2 (A07)
JUMPER
TERMI NALS
"Jj~~~
________
ADD RESSE S
773X7 6
- ----..,,,,.'Ji!!
773X70
------- L~
773X60
---- ~
W1 (A06)
JUMPER
773X50
773X40
---~
773X30 ----~~
773 X20 - - - -r:
773X10{
773X06
773X04
773X02 _____ •
773XOO
BUS DATA LINES
01 5
D14
013
012
011
BINARY
1
0
1
0
0
OCTAL
1
010
009
0'08
0
0
007
006
005
004
0
003
002001
0
000
1
----------~-- r-----------~-----------~----------,~---------~---------2
2
3
5
3
}DATA WOR D FOR ADDRESS
773XOO FOR DIODE
CONFIG URATION SHOWN
Figure 3- 1 Physical Locations of Addresses and Bits
in the ROM Diode Matrix
3-3
CHAPTER 4
ROM ENGINEERING DRAWINGS
The following engineering drawings are applicable to the BM792 ROM:
Title
Drawing No.
Rev.
Page
ROM Diode Matrix M792
D-CS-M792-0-l
D
4-3
ROM Diode Matrix M792-YA
D-CS-M792-YA-I
H
4-5
ROM Diode Matrix
D-CS-M792-YB-l
ROM Card Reader Bootstrap
D-CS-M792-YC-l
ROM Diode Matrix
D-CS-M792-YD-l
A
4-7
4-9
4-11
ROM Diode Matrix
D-CS-M792-YE-l
D-CS-M792-YF-l
D-CS-M792-YH-l
A
4-15
ROM Diode Matrix
Cassette Bootstrap ROM
4-1
4-19
4-23
.1.
CIRCUITS ARE I'ftOf'RIETARY IN NATURE AND SHOULD H TIIU.TEO ACCOltDlNGLY
CO",IUGHT 1910 IY DIGITAL EQutPWEHT CORf'OIIIATION
4
BUS S SYN L
CJI
CF2 BUS C01L
CJ2
CK2
CE2
CO2
CCI
COl
CEI
CKI
Cpl
CRI
BUS C00L
BUS AI3L
4
BUS AI6L
BUS AJ5L
E9
BUS AI2L
BUS AI7L
10
BUS MSYN L
BUS AI4L
AH2
12
BUS AI0L
BK2-----,
BUS Ae)9L
BL2BM2====:J
BN2
CN2
BUS A0BL
BP2-----,
BR2BS2-----,
BT2CP2
CUI
CLI
BUS A07L
BUS A06L
BUS AIIL
+5V
CA2
DA2
AA2
GND
~f~~~~--~--~~--~~--~~--~--~--~--~--~~~--~----~~~~~
De2,DTI
UNLESS OTHERWISE INDICATED:
CZl =SPLIT WGS, ---- :::JUMPERS
CAPACITORS ARE ,Cluf, IOOV, 20%
RESISTORS ARE 8.2K, 1/4W, 5'"/0
DIODES ARE D664
E2, E4, E6, E8,EIO, EI2, E14, E15, E16= DEC380
EI7' DEC7400N
EI, £3, E5, E7, EJ I:: DEeSSSI
E13" DEC8242
E9" DEC314
E18- E?2 '" DEca2S)
~~~ 1~=Gt~V ON
~r~ ~4== Gt~v
-+__~
cv~____~__~B~U~S~A~~________
CFI _____~---"B'::USe....':A""":="2L=------------I__'=cJ
CHI------~--~B~US~A"~I~L~--------I_~
C€C380, DEC314
ON DEGS8el, DEC8242, DEC7400N
~l~ ~6:= ~~v ON
DECa25!
E19- 22 PINS 6 AND 7 NOT CONNECTED
EI8 PINS 4,5,6,7,9 NOT CONNECTED
WI, W2, W3 DESIGNATES WIRE JUMPERS
BUS
CU2 A04L
BUS
CVI A05L
TRANSISTOR & DIODE CONVERSION CHART
0664
DEC300&8
IN3606
2N&>09'
NO E
111-0-0
,,'"
WII !;I
~
EQUIPMENT
CORPORATION
ROM DIODE MATRIX
M792
SIZE
CODE
D
CS
HUM.Eft
M792-0-1
BCD ~
DEC FORM MO.
DRDII.
4-3
1- 1t)..-Z6LVII
bJtlflnN
n
r~2
~ ,--1}--~-,\~ON20,-0_1-1+-_-L---.J---"J~
;~6PF
CI"'CUITS ARE ~IHARY IN NATURE AND SHOULD IU TNUrED M:CO¥IOINGlY
COPVRIGHT 1970 IIY DIGITAL EQUIPMENT CORPCWiATION
RI
5%
Ell
3
I
<
CF2. BUS cmlL
Ell /
L-/
12~
-r-~.I.7
r,ll
EI5 "')].
BUS S SYN L
CJI
L1L- ~II E~15
-==--""=__________-++9'-',
3
9
10
BUS C00L
eJ2
CK2
EE2
4'
~~~
BUS AI6L
CDZ
eCI
eEl
CKI
EI5
EI7
14
BUS AI5L
_____
10
BUS MSYN L
II
7
BUS A09L
:
9
BUS A08L
E 14
EI7
j jj
~_Z
BMZ~
\~lO
IK
~_'
I
~~UF
t
C9
tCIO
CI2
t
C13 +C14
110%
CTI,DC2
DTI
I UNLESS
OTHERWISE
----- "JUMPERS
CAPACITORS ARE .OIUF,100V,20%
RESISTORS ARE 8.2K,1/4W,5%
DIODES ARE 0664
E2, E4,E6, E8,EIO, EI2, EI4, E15, E16= DEC380
E17" OEC7400
EI, E3, E5, E7, Ell =- OEC8881
E13= OEC8242
E9" OEC314
EI8-E22" OEC8251
~:~ ~="tN56
~:~ ~~= :~V ON
1:
~02~
RII
R2B
100
D39\:i1
RI3
~
33
Z
CU2
E5
~
6
~::c
~
BUS
c).l&LAP2
T
~;:
~~
~4~~~
"
E6
2
9
8
E5
C" --AN2
'"t-
~~AT2
100
~,
E8
~
E8
3
2
E7
31
E7
BUS
I 002
9
AU2
BUS,
13 001
AR2
~
2
BUS
10000
EB
E7
BUS
CVI
cI
.,IO~~~
6
A04L
E5
-
EG
-g~2N3639B~D4291
D5291~R-2-7-+-(
5
5
RI2
Q3
~
E6
8
~II~ ~6"," ~£V ON OEC8251
E19-E22 PINS 6AND7 ARE NOT CONNECTED
EI8 PINS 4,5,6,7,9 ARE NOT CONNECTED
RZ6
47
1---+------'
©
OEC3009~
1
AL2
BUS
10
II
BUS
OEC8881, OEC8242, DEC7400
AK2
146C
~AVZ f4-~
5
CHI
BUS,
£3
14
ON OEC380,OEC314
10
E3
2 3
BUS
7d~
E4
I 008
10
eFI
BUS
13 010
~AJ2
E3
E6
13 12
13 BUS
12~
rl!c.
II
E5
~AM2
QI
BUS A03L
CVZ
AHI
9'--
~l
r
INDICATED:
o =-SPLIT LUGS,
BUS
4 011
E3
E4
8
Ddl ~I
CI5
ea
6
E4
: 6r.!
e25
lei
tz +C3
rl~' T'
B.JS
~AH2
EI
2,
~
E4
1'K
2.20PF
5%
+~ ~~yF
AC~;;I
3
2
5
009
~
RB
L,1~r-~l-~;-~-F-ok]'r-C-16--ok]'r-C-174---1'.-cc-,B-,-e-,9--r1'-(e2-0-r-e2-'-1'~CC-~~-C-23~-----~L,~-~~2~N~~~l3~9~~(~;,:
GND
2
4
BT2------.l
12E>
13
EI3)d-'-
TCII
E2
6
II
/
II
EI2 \E---f-----E.J
~13
-+ ~V,_,----r--,-~--,__,--_r--~-,
Rfe I +
~c
14 12
852------,
IZ
BUS AIIL
1 4 9 : BUS
10 014
8
EI
O-------:::----AE2
4
10
BP2==:J
BRZ
~~__+-____~~~1 ~
~3
4
AD2
~I
BN2
n~1
~RZ2
BUS A06L
10
5
~~__+-_____52iB)~
~2
17
2
BUS
13 DIS
EI
~
II
RI9
IK
l-'-'~--+------:"-il ~
10
EI2
~'4
BUS A07L
II
13
6
1-',,,,4+-t-JL4
,--o-w.~
9
1312
rJ
~i ~~i
~~AFZ
EI5
Ria
Cli
14
EIO
®~F
12
10
CPI
CUI
j
~
E2
E2
8US AI4L
CRI
CP2
~
I
~
II
9
6
E9
\'3'-+-+-~'ce2-l-"
__"_9_d_---"')
13 EI7
II 6
2
BUS AI7L
BUS AI0L
CNZ
"
R2
__________~5d____
BUS AI2L
-"'==~
eDI
10
4
BUS AI3L
8
"
"
~
5
EI5
12
N
A05L
4-5
AS2
THIS SCHE ....,TlC IS rUANISt1EO ONLY FOR nST ... NO lII"INTEJroI"'NCE PUIlPOSES. Tt4[
CIItCUITS ... IIE PROPRIETARY IN N",'U"[ .... ND SHOULD IE ,,,u.no ACCOfIDINGlY
CO",IUGHT 1970 I'" DlGlT,It,l EQUIPWENT COliPOflAnON
l
1
e24
560pf
5%
RI
~\I
~Jg I
~
~b-"-~Iv--+-+--~--4-"-jL--/
Ell
BUS C(lI0L
---"=="'--------4-----+-+'0" EI5
eK2
8US S SYN L
14
BUS AI3L
10
£10
~11:EI7
116
7
2
eN2
ep2
eUI
eLi
-J~tJf
GND
AC2,ATI
·1"10%
gg~',~~1
-=l=-
BUS A07L
7
le2
TL TL
T'
le3
C4
....
0
~
DI65
T
BM2~
R6
8N2
BP2===:J
8R2
BS2~
BT2
1
I~)2 )EI3E YII-
12
II
~3
lei
lj:g
IK
R22
~3
BUS AIIL
1
5b
~'
4
"
BL2----.J
IK2I
~2
BUS A06L
BK2_
~I~
IF )E/' f ~)EY-
~_2
Ci
R5
B9)U
~'4
10
EJ2
I
o
"Ci
<0
Ci
R3
D132
~RIB
IK
-o-W:
9
R2
D66
R4
£15
~
£17
6
BUS A08L
2
'"
D99
BUS AI6L
eE2 ---"~~~_ _ _ _~5~~~
BUS AI5L
CO2
:
E9)BUS AI2 L
eel
10
BUS AI7L
eDI
II
BUS MSytJ L
eEl
BUS AI4L
eKI
12
BUS Alfbl
ID
45
epi
14
9
EI4
l"'-H---+-"j
BUS Af)9L
eRI
T
eJI
L-+I'~_~-I
E-'5'X>-'-3-=5=;~~-------' ~
~~"EI5
4EI539
B~
9
10
EI7
14
CF2 BUS C01L
eJ2
/
D33
T'
T'
le5
e6 le7
UNLESS OTHERWISE INDICATED:
0=SPLIT LUGS, ---- "JUMPERS
CAPACITORS ARE .Oluf, 100Y, 20%
RESISTORS ARE 8~2K, 1/4W, 5%
DIODES ARE 0664
E2, £4, E6,E8,EIO, EI2., EI4, E15, E16= DEC380
EI7 = DEC7400N
EI, E3, E5, E7, Ell = DEC8881
E13= DECS242
E9 = DEC314
EIS- E?2 =- DEC8251
~11~ I~~~~V ON
~:~
,~----~--EB~US~A~~~--------~~9'C
~
~~1~4____~
______+-~8~U~S~A~"~2~L________4~--~1213
~
eFI
BUSA01L
eHI
CEC380, DEC314
!,4:= Gt~V ON DECS881, DEC8242, DEC7400N
~:~ ~6==- ~~ ON
DEC8251
E19- 22 PINS 6 AND 7 NOT CONNECTED
Ela PINS 4,5,6,7,9 NOT CONNECTED
WI, W2, W3 DESIGNATES WIRE JUMPERS
G
---~----'==:.::-----+----"o7J
BUS
CU2 Aill4L
EIG
2
-----------~~~
BUS
CVI A05L
" -_ _ _ _ _-'--' C
mamaala
liI'ItOO
DEC
fCIItM HO.
DIID,,,
-
TIm
ROM DIODE MATRIX
~g~~6:A~I~~ $~E IC~;EI
IDATE
M7;~~~;
I
BCD E
t
4-7
J_~EV
1".1
nus SCHEMATIC 15 roffNISHED ONLY FOil TEST AND MAINTEN ..NCE PUffl'05£$. THE1
CIItCUITS AlliE PItOf'ItIET.. ffY IN N.. TURE ..NO SHOULD M TflUTED ACCOfIDlHGlY
'CCW'fItIGl-lT 197' IY OIG,lTAL EQUIPMENT COffl'OltATlOfoi
.-----
e24
560pf
~",)-<>-,,~0;.;28\,-1~+-_~_ r-:12..~
CF2 BUS C01L
.....
I
~
D33
Ell
/
BUS S SYN L
EIO
II
EI5
3
~
BUS C00L _ _ _ _ _ _ _ _ _ _+-+=9~
-,,~~~
~_"'
eJ2
BUS AI3L
4
eK2
5
BUS AI6L
eE2 ~~~--------~D-___
BUS AI5L
6
eD2
E9
BUS AI2L
9
eel
BUS AF7L
10
eDI
BUS MSYN L
II
eEl
BUS 'AI4L
12
eKI
10
EI5
9
4EI5
10
13
8~
14
EI7
14
Kl
EIO
j- ~EI7~
epl
eRI
eN2
BUS AI0L
9
BUS AfD9L
BUS A08L
9
~'4
10
EI2
W2
ep2
BUS A07L
7
~2
WI
CUI
eLi
BUS A06L
4
""'U-w
~3
BUS AIIL
~ IKRia
,---"iF
RI9
IK
EI4
.,
R2
D66
D132
~~
10
'"is
1
D99
11'----'
I
eJI
'----'
L-+~-----'3--==5==---)--r---Y~'~
~!!
I
2,
~
RI
5%
A05L
t
4-9
i:~
g>
I
8
TlIls drlllwlnl and SpoKlllcmons, herein, II'l! the prap'
erty01 Dlaltlll EqulpmantCol'J!Oratlon and shall nolbe
reproduced orCOllied Of und In wilDie orin part as
the basis for the manuladutll Of sale of ltams without
writt..n permiSSion.
I
7
I
6
I l:t
3
5
I
NOTES:
I. FO,€ DrOD€ LOC!;/.ION..S S;Ge
€rClI BOl9leLJ OVe-.RLI9Y.
D
D
+
+
+
+
+
+
+
-
-
5
4
3
Spt.ITUJ6.$
~
c
d
B.41 !fe.s.
C2¢
1(,,5
IDI~
I
o
900 c;, 732.
$ee 1V0T4' #1
b:tODG" Dc;,,, 4-
1100114-
£1.3
I.e.
/909712.
DeC 8242
22
I.c, DeC 31<1-
ciS-ceil!.
S
16
1014
o
CIO
h9..
\0
14
E~
C5~
I
0 16/
11
:(
c;+
foZ
""IT
I, C, De;c 82>:1
2.1
20
I~
r/~_£~/_T____________~~I._.C_.__
De
__
C_7_4~¢~¢~IV
____________t-/9~0~~~~~?_~~~~/~~. - I
QI
7;?.qIVSISTOIe DcC3¢¢~S
/oo.a;OO
17-
+
Z
1909704
1'1094-8 <>"
Co/a~-\}---D----A--lv----c---A--v_Ia#!F.--A--L.:.V--------_-/7_-=:_-_-_-:_-_.:;:.J- I!~
B
900':'73.5""
e:e. STIMPSON
l!:Ve;t.€T #"5:>4-7
I
/c2~.
1
CZS'
I
lees. 47./1. 1/4W S%
1300202
CI9/? i?e¢A~FI#V S'?h LJ/t)
10000ZI
E7CIle-b ClleCIJITB::lIlt€b
QTY
DESCRIPTION
REF DESIGNATION
FIRST USED ON OPTION MODEL
I
11/45
ETCH BOARD REV
I E I,
I I
r--
/0:2:
6
e.
K-co-/(J~Z-yt)- 9-
PART NO.
B
S
s-008917
X-y cooeCJINl17€ )ioa tOCllTION
I
S!
TEM
NO.
PARTS LIST
I I I I I I I I I
I
A 1--_--:-::-=-:-_ _-+_-+_----1
8Z51
3/+. (R0)+
'" 5. - (R0)
JWAIT FOR ERRORI
TSTB
BPL
TST
BMI
CLRB
JMP
@R0
.-2
@R0
BEGIN
@R0
110
JWAlT FOR DONE
JIS IT ENOZON£?
JNO. TRY AGAIN
,ADJUST POINTER
'NOW START ACTUAL READ
JERROR ENCOUNTERED?
JIF SO START OVER
IFOR DECTAPE.STOP TRANSPORT
JGO TO ROUTINE LOADED
.END
1<0
=%000000
= 0000621(
B-2
RI
=%000001
APPENDIX C
BM792-YC CARD READER BOOTSTRAP LOADER
The BM792-YC ROM is shipped with jumper wires connected for address group 773200-773276. Its diode
matrix is preprogrammed for loading binary data into the PDP-II memory from cards using the CRII or CMll
Card Reader. If the data represents a PDP-II program, the program can be automatically started upon completion of loading. The BM792-YC is used in PDP-II Systems that have at least 4K of read-write memory and a
card reader.
On the card that is read, each pair of columns (column 1 and column 2; 3 and 4; etc.) beginning with column 1
contains two 8-bit bytes which represent one l6-bit word. Also a control bit can be contained in the second
column of a pair. The eight bits that represent each byte are punched or marked in rows 2 through 9 of each
column.
The fIrst column of a pair contains the high-order byte (PDP-II bits 15-8) of the word and the second column
of the pair contains the low-order byte (PDP-II bits 7-0) of the word. A control bit punched or marked in row
o of the second column of a pair designates that the word in those two columns is a new Loading Address. Each
Loading Address must be equal to zero modulo two because loading must begin at a word boundary in memory
rather than a byte boundary. Loading is accomplished one word at a time, thus a new Loading Address can
appear anywhere on the card. However, a Loading Address must be in the fIrst two columns of the fIrst card
read.
The absence of control bits in rows 12, 11, 1, and 0 of the second column of a pair designates the word as a
Data Word to be loaded into the PDP-II memory. The Data Word can represent a machine instruction or data.
After each Data Word is loaded into memory the current loading address is incremented by two.
A control bit in row 1 of the second column of a pair designates the word as a Transfer Address. When a Transfer
Address is read, the bootstrap program issues a RESET and branches to the Transfer Address. The card which
contains the Transfer Address passes through the card reader, but no other Loading Addresses or Data Words are
read from it.
A program listing for the card reader bootstrap loader is provided in Table C-I. Hardware addresses in the PDP-II
use 18 bits; thus, bits A15, A16, and A17 are considered in designating the most significant octal digit of the
address. The software assembler uses 16-bit addresses; consequently, only bit Al5 is used to designate the most
significant octal digit of the address. Therefore, the addresses in Table C-l are listed as 173XXX instead of
773XXX.
C-l
The operating procedure for use of the BM792-YC card reader bootstrap loader is as follows:
Step
Procedure
Set the HALT/ENABLE switch to HALT, then to ENABLE.
2
Load the input hopper of the card reader with the cards to be read.
3
01'1 the card reader set the MODE switch to REMOTE.
4
On the card reader depress the RESET switch and observe that the associated green
indicator lights. The card reader is now on-line.
5
Set the starting address, 773200, into the switch register.
6
Depress the LOAD ADDR switch.
7
Depress the START switch. After a short pause, the card reader should read the data
on the cards into the computer memory.
C-2
Table C-l
BM792-YC Card Reader Bootstrap Loader Program
1
;eR BOOTSTRAP
2
3
4
1732~0
5
6
7
,'173200
81T08=400
8IT09·1000
'"'0'140121
;, :010:)0
81114040000
8
9
R0'=-~{0
:1 JIJ~01
10
11
12
13
'."D0002
j 4
1771 60
Rl=%l
R2=%2
R3=%3
R4=%4
PC=%7
CRS=177160
173200
?,'3000~
173202
1:12700
START'
~~g"003
~000~4
0000~7
1 CR STA iUS
15
16
17
18
19
2e
21
22
23
24
:?5
26
n
'6
29
~0
31
:-;2
173206
C'1~0n
173210
173214
173216
173220
173222
173224
173230
173232
173234
173236
173240
173242
cl3n21
~3
'4
173254
35
36
n
38
'9
40
41
42
43
0'1 4 30
'"'1371
0'15210
,10 5 0'13
"31027
00372
105710
START
04~0Ve
INC
CLR
Cc R
TESTCD' sIT
~R0,
1J~373
8PL
,"~303
SWA8
81SB
COM
8M I
TESTCD
R3
@R1,
R4
'·1~3~2
"1'322
040~"0
V80e05
0Z0113
0400~0
CRS
177150
1 73262
~ATA
'JDTe
Xr v
00002J7R
p"
00002J0R
R1
"2
0~002J1R
~3
,HRT
@R3
00002J2R
TESTCD
170224
173256
1 7 3232
ArT C
@R0,
TRM,S,
00002)3 R
0e002J4R
17322J0
TRANSF
1 (Ri)
R2
(R2,"
NEXTV
173216
173220
PC
R4
R3.
NEXTV
R3,
0;;042)0
0 D102)0
8 IT 14
I\J(
MOV
BR
TR'NSF' BIT
8EQ
RESET
JMP
R3
C-3
#81,14
onA
CONHNiS
;AND COLUMN nA~
: 13 CA~D O~NE nAG
; YE:S, ROD A CARD
, !S
DA TA
,END
r>'2J(lj~~1
8I T0!;
TRA~SF
GAT A'
n~755
elT09
8EQ
BGT
MOV
eR
2107 57
C31e27
Gn 1 7'S
@PC,
;MBVE TO A1
;HS; CR RUDY AND GEr e~B ADORE~$
; HID WA l! rOR READ'!, ON'I.!N[
,CLEAR
#B!T14
WA ITC
CMPS
~OOA"S
,RfAD A CIIRO
~R0
NEXTC
I.]
(Ril.
R3
~R0
0l'00~1
R0
R4
TST8
WAITC.
f.l~i4Z5
o~3002
(.,1
8NE
REGISTER
; CLEAR ALL pRESENT DEVle.s
;LOAD STATUS R[GISTER ~DORns
Rl
#8IT~818IU9,
8NE
1511 03
'''51 04
B\'772
121761
173256
173260
173262
173264
173266
173272
173274
173276
#CR$,
R0,
NEXTC'
NEXTV:
~1"l1;0Zl4
17~244
173246
173252
17716e
RESET
MOV
MOV
PIT
COLUt~N
sn
READV rbAG SEI
;NO~ ~, A! T rCR COI.UMN i\NO/M C~~D
; RURRANGE r~ING$
lAND GET TMlS eObuMN
I ! ~ TH!S SI:CONa CObUMN Or PA!~
Ir!RST, GEl
oor,[
AN©T~E~
,HST HIGH avn 01' CRS
lROW 1 IS TRANSr~R rl.AG
lROW 0"~.m IMPLlU OAU
IOTHERWISE ROW
~"1
;AND START NEW P~!R
;STORE DATA WO~O
;AND en NHI COLUMN
; HA! 7 rOR eAIiQ DON.
I~~~!E"
bOAD ADO
~A!~
bOOP
lTHEN eb[A~ CR rbA~$
;AND TRANsrER TO LO~~tO
;nl A TICHY
P~O\'l~AM
APPENDIX D
MR11-DB BULK STORAGE BOOTSTRAP LOADER
The MR II-DB is a 64-word bootstrap loader for the following bulk storage control devices: RF II, RKII, TC 11,
TM 11, RP 11, and RC II. This option can be used in any PDP-li system. It includes a feature of special value to
PDP-l 1/45 systems that are equipped with MSII Semiconductor Memory (MOS or bi-polar) Systems. On those
PDP-l 1/45 systems, the KBII-A start vector for power up can be selected for bootstrap load from any of the
above-listed devices, except the TM 11, which loses vacuum on power fail.
The MRll-DB option consists of two programmed ROM diode matrix modules. The M792-YD ROM Diode
Matrix stores the first 32 words of the bootstrap loader program at addresses 773100-773176. The M792-YE
ROM Diode Matrix stores the second 32 words of the bootstrap loader program at addresses 773200-773276.
Table D-l is a program listing of the MRll-DB Bootstrap Loader program that is encoded on the two ROM diode
matrix modules. PDP-II hardware addresses use 18 bits. The software assembler uses l6-bit addresses. Therefore, the addresses listed in Table D-l are listed as l73XXX, instead of 773XXX.
KEY START LOADING
Operate the MRll-DB Bulk Storage Bootstrap Loader as follows:
1.
Set the HALT/ENABL switch to HALT, then to ENABL.
2.
Set the console switches to the starting address assigned to the selected bulk storage device control,
as listed in Table D-2.
3.
Press LOAD ADRS.
4.
Press START.
The processor will start executing the bulk storage bootstrap loader program at the selected address. The program loads the first 512 words from unit 0 into memory, starting at memory location O. After the bootstrap is
loaded from the bulk storage device, the loader program causes the processor to start executing the bootstrap at
location O.
NOTE
When magnetic tape is the bulk storage medium, magnetic
drive unit 0 must be selected and positioned at the load
point.
Loading from Disks - The program starts at the selected address, then branches to a common routine that resets
all Unibus devices. Thus, disk address registers and current memory address registers are initialized to O. The
pointer to the device's word count register is located in R1. Then, the word count register is loaded with the 2s
D-l
complement of 512. The device command to read and go is issued to the device command register. As the 512word record is read into memory from the disk, the loader program checks for errors. If an error is detected,
the entire routine is repeated, starting at the selected address. When no errors are detected and the last word has
been transferred, the PC is cleared, and the bootstrap is executed, starting at memory location O.
Loading from Tapes - The program starts at the selected address for DECtape or magtape; then branches to a
common tape routine which first resets all the device registers. Then, the device's word count register (or byte
count) is decremented by one. If the routine is entered from the TC 11 address, a first command is issued to rewind the DECtape to the forward end zone. If the routine is entered from the TM 11 address, a first command is
issued to advance the magnetic tape one record. After the specified operation is done and checked for errors, the
program branches to the common disk loading routine that reads a 512-word record into memory from the selected tape storage device.
POWER UP LOADING
The MRII-DB provides for automatically loading a bootstrap program from a pre-selected bulk storage device
during the power up sequence. This feature is provided for PDP-l 1/45 systems with MOS or bipolar memory
and no power backup. The KB ll-A Central Processor Unit in those systems has a start vector jumper field located on DAP module M81 00. Table D-3 lists the start vector jumper connections required to select the specific
MRII-DB starting address for each type of bulk storage device.
START VECTOR PROGRAM OPERATION
The start vector jumpers on the DAP module select bits SV(07:00) of the start vector. Bits SV(OI :00) are always
O. High-order bits of the starting address are generated by CPU sign-extension logic, blocking bits II and 8. A
hard-wired address 773XXX with the SV(07:00) offset is generated. The power up sequence uses the resultant
address to load the PC and PS from the address pointed to by the start vector.
For example, jumper selection of the RK II provides start vector 260. The resultant address, 173260, accesses a
location provided by the MRII-DB, to load the PC with starting address 173110 and the PS with 000340. The
bulk storage program loader proceeds to load a bootstrap from the RK 11, with the CPU operating at priority
level 7, which prevents external devices from intermpting the program.
INSTALLATION
PDP-I 1/45 Systems - Install the M792-YD and M792-YE modules that comprise the MRII-DB option in two of
the three spaces reserved on the CPU backplane for small peripheral controllers. The quad-height slots are designated 26, 27, and 28. Refer to Table D-3 and remove jumpers WI through W6, as required, from the DAP
module to select the bulk storage device that is to provide the bootstrap program during power up.
NOTE
The TMJ1 must be restarted manually, with the tape
drive positioned at the load point. Therefore, power
up start vector selection is not provided.
Other PDP-ll Systems - Install the MRII-DB modules on a DDII-A Peripheral Mounting Panel that is connected to the Unibus by an M920 Unibus Connector module.
D-2
Table D-I
MRll-DB Bulk Storage Program Loader Listing
1 311'1
RFlll
~10732
1 31J
1 31:3
1 3~~1
0801451
177462
1/311<
1!311~
1i3:'l~
1)1~7n
"~'J445
1774~6
1~311~
~I ~
1/3l2k,
:>107n
li3122
~,
~~00~5
RKlll
1710'l5
~10
V
%7,~2
RR
177462
5
OTHER
MOV
%7,~2
SR
177 406
OTHER
TClll
li312~
1773 44
MOV
8R
177344
17312~
"'J;)~~5
5
'~''14003
10~03~
0240~0
4~03
1/313~
l i 3i3t
1(3i3~
1(313~
1(n4~
1/314'
1i3~4~
11314~
1!315~
1!3l5~
1/315q
1?3i5~
1(316~
11310(
1(3i6~
113160
1i3i7~
lj,li7~
17317q
1?3i7§
173~0.
1~0~00
0"'A423
176716
C;J572121
'J12~"1
0~5311
"'(1)57213
012041
031011
1(3~1~
1!3~1~
1(3(1~
1 3 2~
1 3 22
1 3 2~
1 3 4~
1 3 44
1 3 5~
1 3 52
1 3 5~
1 3 5
1 3 6
1 3 6
RESET
MOV
TST
MOV
DEC
TST
MOV
sIT
9EQ
TST
BIT
8EQ
JMP
17310~
'~~"'340
RFVEC:
RF11
34121
010702
Rclll
MOV
SR
177450
0!l~401
17 7450
OTHER:
0e00~5
01121200
@0572121
12112e21
012711
17703121
0112'41
032711
101212~0
~Ql1775
100757
~05~~7
1 3 7
1 3 7
1
0~n3412'
7
MOV
BR
172524
60003
60011
200
100000
MOV
8R
176716
AGAIN:
00012100
1731112i
0003 40
1732213
0003 40
173154
0003 40
17 31213
1 3 6
1 3 6
1 3 7
TAPES:
~0'~005
0102~0
1'10572121
']310 41
07.11406
('I!1'21112
1 3 20
1 3 3~
1 3 3~
1 3 34
1 3 30
RPlll
"'P702
F3~1l~
1'3~0b
1i3~1~
TM111
06iJ~11
~00200
0n776
0'~~0'H
TAPES
IADRS OF WORD COUNT
ILAST COMMAND
IFIRST COMMAND
IDONE MASK
IERROR MASK
1~0000
~60,,?3
1~3;2\l2
%7,"2
24001'1
110702
rM410
172524
RKVEC:
RCVEC:
RPVEC:
TCVEC:
RESET
MOV
TST
MOV
MOV
MOV
8IT
SEQ
8MI
CLR
'MOVING HEAD DISK (CARTRIDGE)
'COMMAND WORD
5
7,(i1 417
lFlXED HEAD DISK (256KW)
%7,%2
TAPES
'O,X2
OTHER
IADRS OF BYTE COUNT
ILAST COMMAND
IFIRST COMMAND
IDONE MASK
IERROR MASK
lMOVING HEAD DISK (PACK)
ICOMMAND WORD
%2,~~
(121) •
(121)·,%1
(1)
(121) •
(0) •. -(1)
(0) ,
• -2
(1)
(0).
(0) ,- (1)
OTHER
(2 )
(5 )
IS
T~E
RESET
IGET H~E ADDRESS or THE BRANCH
1%121 TO POINT AT LAST COMMAND
lGET T~E WORD COUNT ADDREsS
lSET UP FOR ADVANCe: 1 RECORD
'MOVE "0 TO ,IRST COMMAND
ICOMMAND WORD TO COMMAND REG,
ILOOK rOR DONE INDICATORS
INONE SET, TRY AGAIN
IDON£ 'IRST COMMAND, CIO£CK rOR ERROR
ILOOK F'OR S£T [RROll BITS
INO ERRORS
TRY T~E READ
IRERUN FOR ERRORS
.
I RF'l1 POWER UP VECTOR
%7, ~2
OTHER
I FI XED HEAO DISK (64KW)
IAORS OF WORD COUNT (COMMAND·21
ICOMMAND WORD (5 ) ! S T~E RESET
%2,,,0
(121) •
(0).,%1
#-10121121, (1)
(121) ,- (1)
#1130200, (1)
• -4
AGAIN
~7
121
RKll
340
Rcll
3413
RPll
340
Tca
34121
1%0 TO POINT AT WORD COUNT ADR!
IPOINT TO ADDR£SS
IWORD COUNT ADRS TO "1
ILOAD WORD COUNT
lCOMMAND TO COMMAND REG UnR
IcHECK FOR ERROR OR DONE
IIr NEITHER, KEEp l.OOKING
IERROR, TRV AGAIN
I FI Ll.ER
IRKU POWER UP VECTOR
I Rca
~OWER
UP VECTOR
1RPl1 POWEf! UP VECTOR
ITC11 POWER UP VECTOR
.END
D-3
Table D-2
Starting Address
Bulk Storage Device Control
Starting Address
(octal)
RFll (for RSII DECdisk)
RKII (for RK02 DECpack)
TCII (for TU56.DECtape)
TMII (forTUlOMagtape)
RPll (for RP02 Disk Pack)
RCII (for RS64 DEC disk)
773100
773110
773120
773136
773154
773220
Table D-3
Power Up Start Vector Jumper Connections
Bulk Storage
Control Device
Power Up
Vector Address
RFll
RKII
TCII
TMII
RPII
RCII
773214
773260
773274
None
773270
773220
Jumpers on DAP Module
WI
W2
W3
W4
W5
W6
In
Out
In
In
Out
In
Out
In
In
Out
In
In
Out
Out
Out
In
In
In
~
~
Out
Out
In
Out
~
In
In
~
In
Out
~
Out
Out
~
In
In
MAINTENANCE
Diagnostic program MAINDEC-II-DZMRA-D is provided with the MRII-DB Bulk Storage Bootstrap Loader
option. The diagnostic program can be used to troubleshoot and maintain the MRII-DB hardware. The available tests are:
PRGO: Logic Tests
PRG I: ROM data dump
PRG2: Single ROM address read data loop
These tests can also be used to check data reliability and as a post-installation checkout procedure. Complete
operating procedure is described in the MAINDEC description supplied as part of the diagnostic program
package.
Module schematics, parts lists, and component location drawings for the M792-YD and M792-YE ROM Diode
Matrix modules are located in the MRII-DB engineering drawing set. Module Schematics of the two modules
are also provided in Chapter 4 of this manual.
D-4
APPENDIX E
BM792-YF BULK STORAGE BOOTSTRAP LOADER
The BM792-YF ROM is shipped with jumper wires connected for address group 773200-773276, and its diode
matrix is preprogrammed for a bulk storage (disk or DECtape) bootstrap loader program. The BM792-YF can
only be used on a PDP-II System that has at least 4K of read-write memory and one or more mass storage devices, such as a disk or DECtape.
The actual bootstrap loader program, stored in the first 256 words of a disk or DECtape, is transferred from the
device into read-write memory by the BM792-YF program. The transfer is started from location 0 of the device,
and the loaded routine is assumed to be operative at read-write memory location O. The BM792-YF program
jumps to location 0 after a satisfactory completion of the transfer, so that there is automatic starting of the actual bootstrap loader program. If error conditions occur during the running of the BM792-YF program, the
program starts over again.
The sequence of operations used by the bulk storage bootstrap loader is as follows:
1.
It determines whether the device is a disk or DECtape from the address set in the Switch register.
2.
If the device is a DECtape transport, it moves the tape until the front end zone is sensed.
3.
It reads 256 words stored in the device, starting with address 0 of the device.
4.
The loader then stores the 256 words in read-write memory sequential locations, starting with location O.
5.
The loader checks for errors and starts the program over if any errors occur.
6.
The loader then jumps to read-write memory location 0 for automatic starting of the actual bootstrap
loader program.
A program listing for the bulk storage bootstrap loader is provided in Table E-l. Hardware addresses in the
PDP-II use 18 bits; thus, bits A15, A16, and Al7 are considered in designating the most significant octal digit
of the address. The software assembler uses 16-bit addresses; consequently, only bit A 15 is used to designate
the most significant octal digit of the address. Therefore, the addresses in Table E-l are listed as 173XXX instead
of 773XXX.
The operating procedure for use of the BM792-YF bulk storage bootstrap loader is as follows:
Step
Procedure
Set the HALT/ENABLE switch to HALT, then to ENABLE.
2
Set the ROM address, 7732XX, into the Switch register.
XX
Equipment
00
RKll Disk
06
RFll Disk
Tell DECtape
14
E-l
(continued on next page)
Procedure
Step
3
Depress the LOAD ADDR switch.
4
Depress the START switch. The disk or DECtape data should then read into the
read-write memory.
Table E-l
BM792-YF Bulk Storage Bootstrap Loader Program
'REG~SrERS lJSED
Rfh%
Rh%1
:JIZI1J0210
000001
Rl
Isq UP
Rl
J SET
UP RF11
jjl773~~,Rl
IS F.T
UP OECTAPE: ADDRESS
Rl,R~
177
011J57HJ
1"0754
MOV
iI',,,OHll
1'51'8
BPI.
1\>~0
1ST
BM!
0IZH'Ir"I6(,J
JMP
E-2
1IF" NO'! 'END HJNEI,
jlRY AGAIN
I REHT RW
I! SSIJE READ COMMAND
11.001' UNTI
IR[M'V
@H0
j
8~GP'
l'l'fl'l' AflAIN
~
! F" ERROR a
ANY U;>E MOIlON
,G5 TO THE -SOOT
i ~HOP
",11[11
ADDRESS
UNTIe
,"2
RESET
'~00"2'5
/100137
START!
fiKU ADDRESS
APPENDIX F
BM792-YH CASSETTE BOOTSTRAP LOADER
The BM792-YH ROM is shipped with jumper wires connected for address group 773300-773376, and its diode
matrix is preprogrammed for a tape cassette (TAll/TU60 Cassette System) bootstrap loader program. This
quad-sized module is one of the Small Peripheral Controllers (SPC) and can be mounted in any SPC slot in a
DD II-A, DD ll-B, or most PDP-II family processors. Any PDP-II System that has 4K of read-write memory
and a cassette can use the BM792-YH.
The actual bootstrap loader program, stored in the first 128 bytes of a cassette tape, is transferred from the
cassette into read-write memory by the BM792-YH program. The bytes are consecutively read from the cassette
and loaded into memory locations 0 through 177 (octal). When the loading is complete, program control is
transferred to location 0 so that the loaded program can be executed. At the point when the program control
is transferred, the cassette is positioned at the end of the second block of the first file so that the loaded program
can continue to read in additional data.
The sequence of operations used by the cassette bootstrap loader is as follows:
1.
The cassette is rewound and then spaced forward one block. This action skips the header block
(normally 32 bytes) associated with the first file and positions the tape at the second block of the
first file.
2.
The BM792-YH program consecutively reads 128 bytes from the cassette tape into read-write memory
locations 0 through 177 (octal).
3.
The first byte read is compared to octal 240 (NOP) and if it does not equal octal 240, the program
comes to a halt at location 17335Q. To restart the program from this halt, the CONT switch is
depressed.
4.
After the 128 bytes are read, the loader program checks the TAll error bit (block check error, offline error, etc.) and if an error is detected, the program comes to a halt at location 173350 and can
be restarted by depressing the CONT switch.
5.
If no error is detected, program control is transferred to location 0 to execute the loaded program.
A program listing for the cassette bootstrap loader is provided in Table F-l. Hardware addresses in the PDP-II
use 18 bits; thus, bits A15, A16, and Al7 are considered in designating the most significant octal digit of the
address. The software assembler uses 16-bit addresses; consequently, only bit Al5 is used to designate the most
significant octal digit of the address. Therefore, the addresses in Table F-l are listed as I 73XXX instead of
773XXX.
The BM792-YH program has no provisions for initializing the system since it does not issue a RESET instruction.
Initialization is necessary because other devices may issue interrupts or an internal processor option may be enabled. When the BM792-YH program is started from the console, initialization is performed because the START
F-I
Table F-l
BM792-YH Cassette Bootstrap Loader Program
1
2
3
4
5
1=1733210
~H"'J12I0121
Rh%0
0210001
Rh"l
R211"2
R3.%3
PCd?
f(J00Q102
00~11J1/l3
6
j
8
IUJI2I2I01
9 1733130
U2?0121
177500
1t331214
0"50Ul
0107"1
062103121121 l:'l 2
112103
"13210'2
000375
Ul
11
12
1~
173306
173310
173314
14
17332121
1~
173322
173324
173326
173330
173332
15
::;
lABS
17330121
17
1~
19
2f(J
~1
22
23
2~
173334
173336
173342
1121UJ
1021413
13031121
,R0 HO~D~ ADr,R~SS OF TA1l
,SELECT UNIT 2ERO
RESTRTI MOV PC,Ri
IUSE FOR PtC
ADO #T ABL.E.! , Hi /R! HOLD~ ADDRESS OF COMMAND TABLE
MOV #375,R2
;MEMORY POYNTER AND DATA f~AG
JMOVE TE~T BITS TO R~ .
MOVB (Rl)+,R3
C800TI
L.OOP11
L.OOP21
0flli 716
105202
UII1l?72
000002
1733~6
116012
120331
001H1
17335121
173352
01210210121
000755
STOP'
173354
173356
1733621
21"571121
1021774
DONEI
173362
173362
173364
173366
173370
01 '64121
002415
112024
0000eJr2I
173374
173376
0r210342J
0U000
MOV #177500,RIi'l
CL.R (RI1l)
.
TA~hE TO TAll
!IF CO~MA~n IS NlGATIVE, THEN OUIT
ITEST READY ANn T~ANSFER REQUEST 6ITS IN TACS
JBRANCH IF ~ITS ARE NOT SET
JADVANCE MEM~RY POINTER
IIF MINUS, TRY ANOTHER TABLE COMMAND
8MI LOOPl
~10VB 2(RP.I),(R2) IREAD DATA INTO MEMORY
CMPB R3,1iD#0
JFIRST BVTE READ SHOULD BE '24~1
SEQ LOOP2
IlF EQUAL, G~ READ ANOTHER BYTE
MOVB (R1)+,(RflI) JMOVE COMMAND FROM
8M l DOfliE
BJTS R3,(RIlJ)
SEQ l.OOP2
tNCB R2
2~
26
ii
28
29
30
31
32
3~
34
3'36
37
38
39
41D
IHALT ON
,RESTART
TST (RI2I)
!C~ECK
B~l
J8RA~CH
j,jAL,T
I STOP
CL,R
00511)07
TABLE I
1733~eJ
SR RESTRT
,WORD·
.WORD
.WORD
'H~0012111J
.WORO
PC
03'*400 + 24121
005*41?J~ ... 1"15
224*4fa0 ... ~24
0,0
VECTOR I CBOOT
I2lfal:5341ZJ
ERR~R
O~
CONTINUE
ERROR
TO HALT ON EPROR
F~R
,JUMP TO
~
L.OW BYTE
IHIGH 8YTE
, I LBS+REw 1hiD,,·Gr:J
IREAn"'GO
,REAo+rL8S+E~D
TAB~E
lTWO WORnS OF PILLER
JPOWER~Up
!POWER~Up
VEr,TOR (pC,
5TATUS (PS)
REAOy+TRANSFER REQUEST
SPACE fO~W~RD RLOCK+GO
REAO"'IL,BS
switch initializes the system prior to starting. However, if the BM792-YH program is started by a program
transferring control to location 173300, then that program must issue a RESET instruction prior to the JMP
173300.
Normally, the PDP-II processor's power-up vector is address 24/26; however, processors such as the PDP-l 1/40
and PDP-I 1/ 45 have jumper selectable power-up vectors that allow the vector address to be set to an address
within a restricted range in the highest 4K-words of Unibus address. The power-down vector remains at 24/26.
The BM792-YH provides a power-up vector at address 173374/6. When the power-up trap sequence executes
with a vector address set to 173374/6, program execution begins at 173300 with a priority level of 7.
The operating procedure for use of the BM792-YH cassette bootstrap loader when the cassette is operating from
cassette unit number 0 at the standard octal address of 777500 is as follows:
Step
Procedure
Write-lock the cassette for security.
2
Mount the cassette in cassette unit number 0 (left-hand drive unit on the TU60).
3
Set the HALT/ENABLE switch to HALT, then to ENABLE.
4
Set the ROM address, 773300, into the Switch register.
5
Depress the LOAD ADDR switch.
6
Depress the START switch. The cassette data should then read into the read-write
memory.
The operating procedure to bootstrap load from cassette unit number 1 or from a cassette unit other than one
at the standard octal address of 777500 is as follows:
Step
Procedure
Write-lock the cassette for security.
2
Mount the cassette in the selected unit.
3
Set the HALT/ENABLE switch to HALT, then to ENABLE.
4
Set the RO address, 777700, into the Switch register.
5
Depress the LOAD ADDR switch.
6
Set the address of the cassette unit into the Switch register.
7
Depress the DEP switch. This loads RO with the address of the cassette unit.
8
With the Switch register still set at the address of the cassette unit, depress LOAD ADDR
switch.
9
Set the octal designation for the cassette unit number into Switch register (000 for unit
number 0 or 400 for unit number I).
10
Depress the DEP switch. This establishes bit 08, the Unit Select bit, of the TAli Command and Status register.
11
Set the R7 address, 777707 into the Switch register.
12
Depress the LOAD ADDR switch.
(continued on next page)
F-3
Step
Procedure
13
Set 773306 into the Switch register.
14
Depress the DEP switch. This sets the PC to the BM792-YH restart address.
15
Depress the CONT switch. This starts the processor without system initialization.
When started at address 773306, the BM792-YH program uses RO to reference the
cassette registers but does not modify RO or the Unit Select bit.
,
When the 128-byte program is loaded from the cassette into the read-write memory,
this 128-byte program determines whether read-in will continue from this same cassette.
RO and the Unit Select bit can be modified by the loaded program so that a different
cassette can be accessed for loading.
F-4
BM792 ROM
DEC-II-HBMAA-E-D
READER'S COMMENTS
Your comments and suggestions will help us in our continuous effort to improve the quality and usefUlness of
our publications.
What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well
written, etc.? Is it easy to use?
What features are most useful?
What faults do you find with the manual? _ _ _ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ __
Does this manual satisfy the need you think it was intended to satisfy?
Does it satisfy your needs?
Why? __________________________
Would you please indicate any factual errors you have found.
Please describe your position.
Name
Street
Organization
____________________ Department _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
City _ _ _ _ _ _ _ _ _ __ State _ _ _ _ _ _ _ _ _ _ __
Zip or Country
-
-
- - - - - - -.-
-
-
-
-
-
-.- - - - - - - - - FoldHere -
-
-
-
-
Do Not Tear - Fold Here and Staple -
-
-
-- -- -- -- --
FIRST CLASS
PERMIT NO. 33
MAYNARD, MASS.
BUSINESS REPLY MAIL
NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be paid by:
Digital Equipment Corporation
Technical Documentation Department
146 Main Street
Maynard, Massachusetts 01754
•
·"
DIGITAL EQUIPM ENT CORPORATION
MAYNARD, MAS SACHUSETTS 01754
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : Yes Has XFA : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2010:06:24 16:22:30+10:00 Modify Date : 2017:08:04 07:17:40-07:00 Metadata Date : 2017:08:04 07:17:40-07:00 Format : application/pdf Document ID : uuid:df6567d3-72e0-4f13-a385-bc8b34e7987e Instance ID : uuid:9e9c0654-828c-ce40-9728-eaa6ca89dd03 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Page Layout : SinglePage Page Count : 54EXIF Metadata provided by EXIF.tools