ENRICO14_AMD_A00_0421 DELL M4040 DV14 AMD Brazos 4IU01 10265 1

DELL M4040 DV14 AMD Brazos 4IU01 10265-1

User Manual:

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5

4

3

2

1

Enrico 14
Muxless Discrete/UMA Schematics Document

D

D

AMD Ontario CPU FT1
AMD GPU Seymour XT
FCH HUDSON M1
PCB :10265
2010-04-21
REV : A00

C

C

B

A

B

DY :None Installed
UMA:UMA and Muxless platform installed
DIS_PX:DIS and Muxless platform installed
PSL:10mW internal schematic
10mW: 10mW schematic installed
Surge: Surege schematic installed
GIGA: GIGA schematic installed
10/100: 10/100 schematic installed
ROB: ROBOSON GPU installed



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

A

www.bblianmeng.com
3

2

Cover Page

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet
1

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of

109

5

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3

2

1

CHARGER

Project code : 91.4IU01.001
PCB P/N
:
Revision
: 10265-1

AMD Brazos UMA/Discrete Block Diagram

RGB CRT

AMD APU-Ontario
(FT1 BGA 413-Ball)

50

PCIe GPPs (4 parts)
DP1 (DP/HDMI/DVI)

TPS51125A
INPUTS
OUTPUTS 30

DDRIII
DIMM1
1066MHZ
14,15

DP0

PCIe x 4 Gen 2(Muxless)

LVDS

APU Core/NB Power
42,
43
ISL6265CHRTZ-T
31
INPUTS
OUTPUTS

HDMI

DP1

DDRIII SUS

x4 UMI(Gen 1)

TPS51216RUKR
INPUTS
OUTPUTS

74

PCIE x 1
USB 2.0 x 1

TPS51218
INPUTS
OUTPUTS

Mini-Card/Bluetooth
802.11a/b/g

46

65

DCBATOUT 1D1V_S5

SATA III(6 parts), 6Gb/s
INT CLK GEN

USB 2.0 x 3

HW MONITOR

AMD APU/FCH CORE Power
TPS51218
46
INPUTS
OUTPUTS 33

Right Side:
USB x3
61

ACPI 1.1

CAMERA
(Option)

USB 2.0 x 1

IDT 92HD87B1

B

44

APU VDDR/VDDP
AZALIA

Azalia
CODEC
&
OP AMP

TPS51216RGER
INPUTS
OUTPUTS

59

DCBATOUT 0D75V_S0

USB 1.1 (2 parts)

HP OUT

31

C

DDRIII VTT

FCH
Hudson-M1
USB 2.0 (14 parts)

Internal Analog MIC

RJ45
CONN

USB2.0

Realtek
RTS5138
32

MIC IN

Realtek
RTL8105

PCIE x 1

44

DCBATOUT 1D5V_S3

10/100

CardReader
SD/MMC/MS

APU_VDD
APU_VDDNB

DCBATOUT

51
83,84,85,86,87
gDDR3
64M*16b*4(512MB)/128M*16b*4(1024MB)

D

3D3V_AUX_S5
5V_AUX_S5
5V_S5
3D3V_S5

DCBATOUT

49

4,5,6,7,8

41

DDRIII
DIMM2
1066MHZ
14,15

AMD dGPU

C

DCBATOUT

27

DP0 (DP/HDMI/DVI/LVDS)

Seymour-XT

28,29

AD+

SYSTEM DC/DC
DDR III 1333

VRAM

40

OUTPUTS

BT+

D

CRT

BQ24707
INPUTS

1V_S0

DCBATOUT

AMD GPU CORE

49

USB 2.0

RT8208BGQW
26
INPUTS
OUTPUTS

LPC Bus

DCBATOUT VGA_CORE

29

92

B

AMD GPU CORE

2CH SPEAKER

NUVOTON

SPI

RT8015B
INPUTS

OUTPUTS

3D3V_S5

1D8V_S0

47

26

PCB LAYER

KBC

SATA II

SATA II

17,18,19,20,21,22

27

NPCE795P



L1:
L2:
L3:
L4:
L5:
L6:

Top
VCC
Signal
Signal
GND
Bottom

A

A

HDD
56

ODD
56

Flash ROM
2MB
60

Touch
PAD
69

Int.
KB

Thermal

Wistron Corporation

P2800

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

25 28

69

Title

Block Diagram

Fan
P2793
5

4

www.bblianmeng.com
3

Size
58

Rev

A3 Enrico 14 AMD
Date:

2

Document Number
Friday, April 22, 2011

A00
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28

109

5

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1

REQUIRED SYSTEM STRAPS
D

AZ_SDOUT

PULL
HIGH

PCI_CLK1

LOW POWER
MODE

Allow
PCIE GEN2

CLK_PCI_LPC
USE
DEBUG
STRAPS

PCI_CLK4

LPC_CLK0

LPC_CLK1

non_Fusion
CLOCK mode

ENABLE EC

CLKGEN
ENABLED
(Use Internal)

DEFAULT

PULL
LOW

PERFORMANCE
MODE

Force
PCIE GEN1

DEFAULT

TYPE
ENABLED

LPC_CLK2
Enable
boot timer
function

EC_PWM2

EC_PWM3

D

Reserved

2.2-kohm 5% pull-down

2.2-kohm 5% pull-down

LPC ROM

Not connected.

2.2-kohm 5% pull-down

SPI ROM

2.2-kohm 5% pull-down

Not connected.

Reserved

Not connected.

Not connected.

DEFAULT

IGNORE
DEBUG
STRAPS

Fusion
CLOCK mode

DISABLE EC

DEFAULT

DEFAULT

DEFAULT

CLKGEN
DISABLED
(Use External)

Disable boot
fail timer
function
DEFAULT

Note: EC_PWM2, EC_PWM3 default have internal 10kohm PU.
C

C

USB Table

PCIe Routing
APU

Pair

USB Device

0

USB 2.0 EXT.Port1

LANE0

LAN

1

Mini Card1 (WLAN)

LANE1

WWAN

2

USB 2.0 EXT.Port1

3

NC

LANE2

WLAN

4

NC

LANE3

CardReader

5

NC

6

USB 2.0 EXT.Port1

7

CCD Camera

8

NEWCARD

9

Card Reader

10

NC

11

NC

12

NC

13

NC

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

5

4

www.bblianmeng.com
3

Date:
2

Table of Content
Document Number

Rev

Enrico 14 AMD
Friday, April 22, 2011

A00
Sheet
1

3

of

109

5

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2

1

SSID = CPU

D

D

1 OF 5

APU1A

83 PEG_RXP1
83 PEG_RXN1

AB4
AC4

83 PEG_RXP2
83 PEG_RXN2

AA1
AA2
Y4
Y3

83 PEG_RXP3
83 PEG_RXN3
1V_S0

C

R401 1
2KR2F-3-GP

2

P_ZVDDP

Y14

P_GPP_RXP0 ONTARIO_FT1
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3

PCIE I/F

AA6
Y6

P_ZVDD_10

17 UMI_FCH_APU_RX0P
17 UMI_FCH_APU_RX0N

AA12
Y12

17 UMI_FCH_APU_RX1P
17 UMI_FCH_APU_RX1N

AA10
Y10

P_UMI_RXP1
P_UMI_RXN1

17 UMI_FCH_APU_RX2P
17 UMI_FCH_APU_RX2N

AB10
AC10

P_UMI_RXP2
P_UMI_RXN2

17 UMI_FCH_APU_RX3P
17 UMI_FCH_APU_RX3N

AC7
AB7

P_UMI_RXP0
P_UMI_RXN0

P_UMI_RXP3
P_UMI_RXN3

UMI I/F

83 PEG_RXP0
83 PEG_RXN0

DIS_PX

P_GPP_TXP0
P_GPP_TXN0

AB6
AC6

PEG_C_TXP0 C401 1
2 SCD1U10V2KX-5GP
PEG_C_TXN0C402 DIS_PX
1
2 SCD1U10V2KX-5GP

PEG_TXP0 83
PEG_TXN0 83

P_GPP_TXP1
P_GPP_TXN1

AB3
AC3

PEG_C_TXP1 C403 DIS_PX
1
2 SCD1U10V2KX-5GP
PEG_C_TXN1C404 DIS_PX
1
2 SCD1U10V2KX-5GP

PEG_TXP1 83
PEG_TXN1 83

P_GPP_TXP2
P_GPP_TXN2

Y1
Y2

PEG_C_TXP2 C405 DIS_PX
1
2 SCD1U10V2KX-5GP
PEG_C_TXN2C406 DIS_PX
1
2 SCD1U10V2KX-5GP

PEG_TXP2 83
PEG_TXN2 83

V3
V4

PEG_C_TXP3 C407 DIS_PX
1
2 SCD1U10V2KX-5GP
PEG_C_TXN3C408 DIS_PX
1
2 SCD1U10V2KX-5GP

PEG_TXP3 83
PEG_TXN3 83

P_ZVSS

AA14

P_ZVSS

P_UMI_TXP0
P_UMI_TXN0

AB12
AC12

UMI_TX0P_C
UMI_TX0N_C

C409 1
C410 1

2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP

UMI_APU_FCH_TX0P 17
UMI_APU_FCH_TX0N 17

P_UMI_TXP1
P_UMI_TXN1

AC11
AB11

UMI_TX1P_C
UMI_TX1N_C

C411 1
C412 1

2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP

UMI_APU_FCH_TX1P 17
UMI_APU_FCH_TX1N 17

P_UMI_TXP2
P_UMI_TXN2

AA8
Y8

UMI_TX2P_C
UMI_TX2N_C

C413 1
C414 1

2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP

UMI_APU_FCH_TX2P 17
UMI_APU_FCH_TX2N 17

P_UMI_TXP3
P_UMI_TXN3

AB8
AC8

UMI_TX3P_C
UMI_TX3N_C

C415 1
C416 1

2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP

UMI_APU_FCH_TX3P 17
UMI_APU_FCH_TX3N 17

P_GPP_TXP3
P_GPP_TXN3

1 R402
2
1K27R2F-L-GP

C

ONTARIO-FT1-GP

B

B


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

5

4

www.bblianmeng.com
3

Date:
2

APU_PCIE(1/5)
Document Number

Rev

Enrico 14 AMD
Friday, April 22, 2011

A00
Sheet
1

4

of

109

5

4

3

2

M_A0
M_A1
M_A2
M_A3
M_A4
M_A5
M_A6
M_A7
M_A8
M_A9
M_A10
M_A11
M_A12
M_A13
M_A14
M_A15

R17
H19
J17
H18
H17
G17
H15
G18
F19
E19
T19
F17
E18
W17
E16
G15

M_ADD0
M_ADD1
M_ADD2
M_ADD3
M_ADD4
M_ADD5
M_ADD6
M_ADD7
M_ADD8
M_ADD9
M_ADD10
M_ADD11
M_ADD12
M_ADD13
M_ADD14
M_ADD15

14,15 M_BS0
14,15 M_BS1
14,15 M_BS2

R18
T18
F16

M_BANK0
M_BANK1
M_BANK2

14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15

D

D15
B19
D21
H22
P23
V23
AB20
AA16

M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7

M_DQS0
M_DQS#0
M_DQS1
M_DQS#1
M_DQS2
M_DQS#2
M_DQS3
M_DQS#3
M_DQS4
M_DQS#4
M_DQS5
M_DQS#5
M_DQS6
M_DQS#6
M_DQS7
M_DQS#7

A16
B16
B20
A20
E23
E22
J22
J23
R22
P22
W22
V22
AC20
AC21
AB16
AC16

M_DQS_H0
M_DQS_L0
M_DQS_H1
M_DQS_L1
M_DQS_H2
M_DQS_L2
M_DQS_H3
M_DQS_L3
M_DQS_H4
M_DQS_L4
M_DQS_H5
M_DQS_L5
M_DQS_H6
M_DQS_L6
M_DQS_H7
M_DQS_L7

M_DIM0_CLK_DDR0
M_DIM0_CLK_DDR#0
M_DIM0_CLK_DDR1
M_DIM0_CLK_DDR#1
M_DIM0_CLK_DDR2
M_DIM0_CLK_DDR#2
M_DIM0_CLK_DDR3
M_DIM0_CLK_DDR#3

M17
M16
M19
M18
N18
N19
L18
L17

M_CLK_H0
M_CLK_L0
M_CLK_H1
M_CLK_L1
M_CLK_H2
M_CLK_L2
M_CLK_H3
M_CLK_L3

L23
N17

M_RESET#
M_EVENT#

F15
E15

M_CKE0
M_CKE1

14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15

C

14
14
14
14
15
15
15
15

M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7

14,15 M_RST#

M_EVENT#

14,15 M_DIM0_CKE0
14,15 M_DIM0_CKE1

14
14
15
15

M_A_DIM0_ODT0
M_A_DIM0_ODT1
M_B_DIM0_ODT0
M_B_DIM0_ODT1

W19
V15
U19
W15

M0_ODT0
M0_ODT1
M1_ODT0
M1_ODT1

14
14
15
15

M_A_DIM0_CS#0
M_A_DIM0_CS#1
M_B_DIM0_CS#0
M_B_DIM0_CS#1

T17
W16
U17
V16

M0_CS#0
M0_CS#1
M1_CS#0
M1_CS#1

14,15 M_RAS#
14,15 M_CAS#
14,15 M_W E#

U18
V19
V17

M_RAS#
M_CAS#
M_WE#

B

APU_VREF

ONTARIO_FT1

MEMORY
I/F

SSID = CPU

1

5 OF 5

APU1E

M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7

B14
A15
A17
D18
A14
C14
C16
D16

M_DQ0
M_DQ1
M_DQ2
M_DQ3
M_DQ4
M_DQ5
M_DQ6
M_DQ7

M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15

C18
A19
B21
D20
A18
B18
A21
C20

M_DQ8 14,15
M_DQ9 14,15
M_DQ10 14,15
M_DQ11 14,15
M_DQ12 14,15
M_DQ13 14,15
M_DQ14 14,15
M_DQ15 14,15

M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23

C23
D23
F23
F22
C22
D22
F20
F21

M_DQ16
M_DQ17
M_DQ18
M_DQ19
M_DQ20
M_DQ21
M_DQ22
M_DQ23

14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15

M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31

H21
H23
K22
K21
G23
H20
K20
K23

M_DQ24
M_DQ25
M_DQ26
M_DQ27
M_DQ28
M_DQ29
M_DQ30
M_DQ31

14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15

M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39

N23
P21
T20
T23
M20
P20
R23
T22

M_DQ32
M_DQ33
M_DQ34
M_DQ35
M_DQ36
M_DQ37
M_DQ38
M_DQ39

14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15

M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47

V20
V21
Y23
Y22
T21
U23
W23
Y21

M_DQ40
M_DQ41
M_DQ42
M_DQ43
M_DQ44
M_DQ45
M_DQ46
M_DQ47

14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15

M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55

Y20
AB22
AC19
AA18
AA23
AA20
AB19
Y18

M_DQ48
M_DQ49
M_DQ50
M_DQ51
M_DQ52
M_DQ53
M_DQ54
M_DQ55

14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15

M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63

AC17
Y16
AB14
AC14
AC18
AB18
AB15
AC15

M_DQ56
M_DQ57
M_DQ58
M_DQ59
M_DQ60
M_DQ61
M_DQ62
M_DQ63

14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15

M_VREF

M23

M_VREF_APU

M_ZVDDIO_MEM_S

M22

M_ZVDDIO_MEM_S
2

14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15

D

C

B

1D5V_S3

R502
39R2F-GP
1

ONTARIO-FT1-GP

DDR_VREF_S3
1D5V_S3
M_VREF_APU

1

2 0R0402-PAD

1

1

R501

2

C502
SCD1U10V2KX-5GP

2

2

R503
1KR2J-1-GP
1

M_EVENT#

C501
SC1KP50V2KX-1GP


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

AMD Confirm: PU Needed even if not used
Title

LAYOUT: place them close to APU

5

APU_DDR(2/5)
4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet
1

5

of

109

5

4

3

2

SSID = CPU
Boot Voltage

Brazos:
DP1 --> HDMI

SVD

0

0

1.1

0

1

1.0

1.2

1

0

0.9

1.1

(open)

(VCC/GND)

SCD1U10V2KX-5GP
1
SCD1U10V2KX-5GP
1

2C602 1 R602

2 51R2F-2-GP

2C603 1 R603

2 51R2F-2-GP

1.1

TDP1_AUXP
TDP1_AUXN

B2
C2

TDP1_HPD

C1

GTXP1
GTXN1

B9
A9

51 APU_HDMI_DATA0
51 APU_HDMI_DATA0#

1
1

2 C604 SCD1U16V2KX-3GP
2 C605 SCD1U16V2KX-3GP

GTXP0
GTXN0

D10
C10

TDP1_TXP2
TDP1_TXN2

51 APU_HDMI_CLK
51 APU_HDMI_CLK#

1
1

2 C608 SCD1U16V2KX-3GP
2 C609 SCD1U16V2KX-3GP

GTXP3
GTXN3

A10
B10

TDP1_TXP3
TDP1_TXN3

49 LVDSA_DATA2
49 LVDSA_DATA2#

B5
A5

LTDP0_TXP0
LTDP0_TXN0

LTDP0_AUXP
LTDP0_AUXN

A3
B3

49 LVDSA_DATA1
49 LVDSA_DATA1#

D6
C6

LTDP0_TXP1
LTDP0_TXN1

LTDP0_HPD

D3

LTDP0_TXP3
LTDP0_TXN3

100MHz

17 APU_CLKP
17 APU_CLKN

V2
V1

CLKIN_H
CLKIN_L

100MHz

17 DISP_CLKP
17 DISP_CLKN

D2
D1

DISP_CLKIN_H
DISP_CLKIN_L

42 APU_SVC_R
42 APU_SVD_R

J1
J2

SVC
SVD

APU_SIC
APU_SID

P3
P4

SIC
SID

APU_RST#_R
APU_PWRGD_R

T3
T4

RESET#
PWROK

APU_THERMTRIP#_VDDIO
APU_ALERT#

U1
U2
T2

PROCHOT#
THERMTRIP#
ALERT#

N2
N1
P1
P2
M4
M3
M1

TDI
TDO
TCK
TMS
TRST#
DBRDY
DBREQ#

1
2

DY

SRN0J-6-GP
4
3

0R0402-PAD1
H_CPUPWRGD 0R0402-PAD1

17,83 APU_RST#
17,36,42,71 H_CPUPWRGD

0R0402-PAD1

17 APU_PROCHOT#_VDDIO

2

R625
R626

2
2

R628

27,40 H_PROCHOT#
71 APU_TDI
71 APU_TDO
71 APU_TCK
71 APU_TMS
71 APU_TRST#
71 APU_DBRDY
71 APU_DBREQ#

1
0R0402-PAD1

42 APU_VDD_RUN_FB_L
42 APU_VDDNB_RUN_FB_L

TPAD14 TP614
2 R630

0R0402-PAD1

APU_VDDIO_SUS_FB_H

F4
G1
F3

APU_RUN_FB_L

F1

R631

2

B4
W11
V5

0819

1 1KR2J-1-GP

APU_TEST19_PLLTEST0

2 R606

1 1KR2J-1-GP

L_BKLT_EN 27
LVDS_VDD_EN 49
L_BKLT_CTRL 49
PCH_HDMI_CLK_R 51
PCH_HDMI_DATA_R 51

DP1_HPD

D

HDMI
1D8V_S0

DP1_HPD 51
LVDS_DDC_CLK 49
LVDS_DDC_DATA 49

DP2_HPD

X02

C12
D13
A12
B12
A13
B13

1 R612

2150R2F-1-GP

1 R615

2150R2F-1-GP

1 R617

2150R2F-1-GP

APU_TEST25_L_BYPASSCLK_L

2 510R2F-L-GP

1 R613

2 1KR2J-1-GP

1D8V_S0

CRT_RED 50
CRT_GREEN 50
1D8V_S0

CRT_BLUE 50
APU_TEST36_GIO_TSTDTM0_SERIALCLK
CRT_HSYNC 50
CRT_VSYNC 50

DAC_SCL
DAC_SDA

F2
D4

DDCCLK 50
DDCDATA 50

D12

1 R611

LVDS
ALLOW_STOP

E1
E2

TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31
TEST33_H
TEST33_L
TEST34_H
TEST34_L
TEST35
TEST36
TEST37

VDDCR_NB_SENSE
VDDCR_CPU_SENSE
VDDIO_MEM_S_SENSE

2 0R0402-PAD
2 0R0402-PAD
2 0R0402-PAD

DAC_ZVSS

2 R622

1 R619

2 1KR2J-1-GP

APU_TEST37_GIO_TSTDTM0_CLKINIT

1 R620
DY

2 1KR2J-1-GP

APU_BP0_TSTCLK_USCLK1

1 R621
DY

2 1KR2J-1-GP

1 499R2F-2-GP

R1
R2
R6
T5
E4
K4
L1
L2
M2
K1
K2
L5
M5
M21
J18
J19
U15
T15
H4
N5
R5

APU_THERMDA
APU_THERMDC
APU_TEST6_DIRECRACKMON
APU_BP0_TSTCLK_USCLK0
APU_BP0_TSTCLK_USCLK1
APU_TEST16_BP2
APU_TEST17_BP3
APU_TEST18_PLLTEST1
APU_TEST19_PLLTEST0
APU_TEST25_H_BYPASSCLK_H
APU_TEST25_L_BYPASSCLK_L
APU_TEST28_H_PLLCHARZ
APU_TEST28_L_PLLCHARZ
APU_TEST31_MEM_TEST
APU_TEST33_H_M_CLKTST_H
APU_TEST33_L_M_CLKTST_L
APU_TEST34_H_TSTCLKIN_H
APU_TEST34_L_TSTCLKIN_L
APU_TEST35
APU_TEST36_GIO_TSTDTM0_SERIALCLK
APU_TEST37_GIO_TSTDTM0_CLKINIT

1
1
1
1

TP602
TP603
TP604
TP616

TPAD14
TPAD14
TPAD14
TPAD14

1
1

TP605 TPAD14
TP606 TPAD14

K3
T1

APU_TEST38

1 R623
DY
1 R624
DY

2 1KR2J-1-GP
2 1KR2J-1-GP
R627
21KR2J-1-GP

1
APU_TEST18_PLLTEST1 71
APU_TEST19_PLLTEST0 71

1
1
1

TP607 TPAD14
TP608 TPAD14
TP609 TPAD14

1
1

TP610 TPAD14
TP611 TPAD14

1
1

TP612 TPAD14
TP613 TPAD14

1

TP615 TPAD14

X01

C

5V_S0

R664
100KR2J-1-GP
DP2_HPD

1

42 APU_VDDNB_RUN_FB_H
42 APU_VDD_RUN_FB_H

2 R605

VSS_SENSE
TEST38
DMAACTIVE#

RSVD#B4
RSVD#W11
RSVD#V5

R647
100KR2J-1-GPDY

ALLOW_STOP 17

ONTARIO_FT1

2

0721RN602

18 SCLK3
18 SDATA3

R610 1
R607 1
R608 1

DAC_HSYNC
DAC_VSYNC

DAC_ZVSS

TEST

DY

DAC_RED
DAC_RED#
DAC_GREEN
DAC_GREEN#
DAC_BLUE
DAC_BLUE#

SER

R601
1 0R2J-2-GP
2

2 510R2F-L-GP

APU_TEST18_PLLTEST1
2 150R2F-1-GP

1

LTDP0_TXP2
LTDP0_TXN2

D8
C8

VGA
DAC

A6
B6

49 LVDSA_CLK
49 LVDSA_CLK#

DISPLAYPORT
0

DISPLAYPORT
1

TDP1_TXP1
TDP1_TXN1

1 R609

2

2 C606 SCD1U16V2KX-3GP
2 C601 SCD1U16V2KX-3GP

49 LVDSA_DATA0
49 LVDSA_DATA0#

C

L_BKLT_EN_R
LVDS_VDD_EN_R
L_BKLT_CTRL_R

1
1

LVDS
Panel

71 APU_RST_L_BUF

DP_BLON
DP_DIGON
DP_VARY_BL

G2
H2
H1

51 APU_HDMI_DATA1
51 APU_HDMI_DATA1#

CLK

HDMI

D

DP_ZVSS

DP_ZVSS

TDP1_TXP0
TDP1_TXN0
DP MISC

51 APU_HDMI_DATA2
51 APU_HDMI_DATA2#

0.9

H3

CTRL

0.8

ANALOG/DISPLAY/MISC

A8
B8

APU_TEST25_H_BYPASSCLK_H 1 R604
2 OF 5

APU1B
GTXP2
GTXN2

2 C610 SCD1U16V2KX-3GP
2 C607 SCD1U16V2KX-3GP

1
1

JTAG

1

APU_TEST33_L_M_CLKTST_L

Sabine:
DP0 --> LVDS
DP1 --> CRT
DP2 --> HDMI

Boot Voltage

SVC

1

1

APU_TEST33_H_M_CLKTST_H

ONTARIO-FT1-GP
APU_RST#
C631 1
H_CPUPWRGD C632 1

X01

1D8V_S0
RN605
4
3

H_CPUPWRGD
APU_RST#

1
2

DY2SC10P50V2JN-4GP
DY2SC10P50V2JN-4GP
0811 AMD Nick change

X01

SRN300J-3-GP

0811 Remove level shifter

1D8V_S0

1

2

3D3V_S0

R629
1KR2J-1-GP

SRN1KJ-7-GP

84.T3904.C11
2ND = 84.03904.P11

R643

APU_ALERT#_FCH 19

APU_TEST35

2

0R0402-PAD
3D3V_S5

DY

Thripthrip# add integrated PU 10K

R632
1KR2J-1-GP
B

DY R646

10KR2J-3-GP

B

3rd = 84.03904.L06
MMBT3904-4-GP
APU_THERMTRIP#_VDDIO

2

1

B

APU_SVD_R
APU_SVC_R

4
3

1

1

RN607
1
2

APU_ALERT#

2

0809 Change to 1k

1

APU_THERMTRIP#_VDDIO_Q
2

R635
10KR2J-3-GP
1D8V_S0

3D3V_S0
E

C

H_THERMTRIP# 18,36

Q601

X01
1
2

CPU exceeds to 125℃

4
3

RN634
SRN1KJ-7-GP

49 LVDS_DDC_DATA
49 LVDS_DDC_CLK
3D3V_S0
RN608
8
7
6
5

1
2
3
4

APU_SID
APU_ALERT#
APU_THERMTRIP#_VDDIO
APU_SIC

SRN1KJ-4-GP

X01
RN

1D8V_S0

1

1
2
3
4

RN635
1
2

APU_SID
APU_SIC

RN601
8
7
6
5

A

APU_TRST#
APU_TMS
APU_TCK
APU_TDI

0R4P2R-PAD
4
3

SML1_DATA 27,85
SML1_CLK 27,85

A

SRN1KJ-4-GP
R640
APU_DBREQ#
2
300R2J-4-GP



Wistron Corporation

0802 Change to H_PROCHOT#

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

3D3V_S0
H_PROCHOT#
1 R641
2
1KR2J-1-GP

Title
Size
Custom

5

4

www.bblianmeng.com
3

APU_COntrol&Debug(3/5)
Document Number

Rev

Enrico 14 AMD

A00

Date: Friday, April 22, 2011
2

Sheet
1

6

of

109

5

SSID = CPU

4

VDDCR_CPU:
10uF X 7
1uF X 4
0.1uF X 5 180pF X 2

DY

DY

DY

DY

DY

DY

11A for 18W
4.5A for 9W

DY

APU1C

VDDCR_CPU
VDDCR_CPU
VDDCR_CPU
VDDCR_CPU
VDDCR_CPU
VDDCR_CPU
VDDCR_CPU
VDDCR_CPU
VDDCR_CPU
VDDCR_CPU
VDDCR_CPU
VDDCR_CPU
VDDCR_CPU
VDDCR_CPU
VDDCR_CPU

3

ONTARIO_FT1

3 OF 5

VDD_18
VDD_18
VDD_18
VDD_18
VDD_18
VDD_18
VDD_18

U8
W8
U6
U9
W6
T7
V7

W9

U11

2A for 18W
2A for 9W

0.15A for 18W
0.15A for 9W

DY

0.5A for 18W
0.5A for 9W

1D8V_S0

DY

DY

2

L701

DY

1D8V_S0

220 ohm 2A

DY

1V_S0

1V_S0

1
2
PBY160808T-221Y-N-GP

2

VDD_18:
10uF X 1
0.1uF X 1

3D3V_S0

1

1uF X 4
180pF X 1

0.2A for 18W

VDD_33:
1uF X 1
0.1uF X 1



Document Number

1

Sheet

7

of

109

A00

Rev

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

APU_Power(4/5)

Size
A3

Friday, April 22, 2011

Enrico 14 AMD

Date:

Title

Wistron Corporation

VDD_10: 5.5A for 9W
10uF X 2
1uF X 2
0.1uF X 2 180pF X 1

5.5A for 18W

VDDPL_10: 0.2A for 9W
10uF X 1
1uF X 1
0.1uF X 1 180pF X 1

VDD_18_DAC:
10uF X 1 1uF X 1
180pF X 1

DY

VDDPL_10

C748
SC10U6D3V5KX-1GP
2
1

DY

C752
SC1U6D3V2KX-GP
2
1

E5
E6
F5
F7
G6
G8
H5
H7
J6
J8
L7
M6
M8
N7
R8

VDD_18_DAC

VDDPL_10

U13
W13
V12
T12

A4

C747
SC1U6D3V2KX-GP
2
1

10A for 18W
8A for 9W

DY

DY

VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB
VDDCR_NB

VDD_10
VDD_10
VDD_10
VDD_10

VDD_33

C751
SCD1U10V2KX-5GP
2
1

DY

APU_VDDNB

DY

E8
E11
E13
F9
F12
G11
G13
H9
H12
K11
K13
L10
L12
L14
M11
M12
M13
N10
N12
N14
P11
P13

VDDIO_MEM_S
VDDIO_MEM_S
VDDIO_MEM_S
VDDIO_MEM_S
VDDIO_MEM_S
VDDIO_MEM_S
VDDIO_MEM_S
VDDIO_MEM_S
VDDIO_MEM_S
VDDIO_MEM_S
VDDIO_MEM_S

C743
SC1U6D3V2KX-GP
2
1

C709
SC1U6D3V2KX-GP
2
1

2A for 18W
2A for 9W

G16
G19
E17
J16
L16
L19
N16
R16
R19
W18
U16

C746
SCD1U10V2KX-5GP
2
1

APU_VDD

1uF X 5
180pF X 2

DY

1D5V_S3

DY

ONTARIO-FT1-GP

C750
SCD1U10V2KX-5GP
2
1

C713
SC4D7U6D3V5KX-3GP
2
1

DY

DY

C723
SC1U6D3V2KX-GP
2
1
C742
SC180P50V2JN-1GP
2
1

D

VDDCR_NB:
10uF X 5
0.1uF X 4

DY

VDDIO_MEN_S:
10uF X 2
1uF X 4
0.1uF X 3 180pF X 2

DY

3

C721
SCD1U10V2KX-5GP
2
1
C745
SC180P50V2JN-1GP
2
1

C706
SC10U6D3V5KX-1GP
2
1
4

C772
SC1U6D3V2KX-GP
2
1

D

C

A

B

www.bblianmeng.com

C726
SC10U6D3V5KX-1GP
2
1

C755
SC10U6D3V5KX-1GP
2
1

C771
SCD1U10V2KX-5GP
2
1

C744
SC4D7U6D3V5KX-3GP
2
1

C720
SCD1U10V2KX-5GP
2
1
C749
SC180P50V2JN-1GP
2
1

C708
SC1U6D3V2KX-GP
2
1

C719
SC180P50V2JN-1GP
2
1
C731
SC4D7U6D3V5KX-3GP
2
1
C741
SC1U6D3V2KX-GP
2
1
C762
SCD1U10V2KX-5GP
2
1
C770
SCD1U10V2KX-5GP
2
1

C725
SC1U6D3V2KX-GP
2
1

C754
SC10U6D3V5KX-1GP
2
1

C712
SC180P50V2JN-1GP
2
1
C761
SC1U6D3V2KX-GP
2
1

C724
SCD1U10V2KX-5GP
2
1
C753
SC1U6D3V2KX-GP
2
1

C730
SC4D7U6D3V5KX-3GP
2
1
C740
SC180P50V2JN-1GP
2
1

C769
SCD1U10V2KX-5GP
2
1

C

B

A

5

POWER

C715
SCD1U10V2KX-5GP
2
1

C718
SC1U6D3V2KX-GP
2
1

C714
SC10U6D3V5KX-1GP
2
1
C766
SCD1U10V2KX-5GP
2
1

C716
C701
SC1U6D3V2KX-GP
2
1
C756
SC10U6D3V5KX-1GP
2
1

C729
SC10U6D3V5KX-1GP
2
1
C739
SC1U6D3V2KX-GP
2
1
C760
SCD1U10V2KX-5GP
2
1

C768
SCD1U10V2KX-5GP
2
1

C735
SC180P50V2JN-1GP
2
1
C763
SC1U6D3V2KX-GP
2
1

C711
SCD1U10V2KX-5GP
2
1
C738
SC1U6D3V2KX-GP
2
1
C767
SC1U6D3V2KX-GP
2
1

C734
SC180P50V2JN-1GP
2
1

C717
SCD1U10V2KX-5GP
2
1
C737
SCD1U10V2KX-5GP
2
1

C705
SC10U6D3V5KX-1GP
2
1
SC1U6D3V2KX-GP
2
1
C757
SC10U6D3V5KX-1GP
2
1

C765
SC1U6D3V2KX-GP
2
1

C733
SCD1U10V2KX-5GP
2
1

5

4

3

2

1

SSID = CPU

D

D

4 OF 5

APU1D

C

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

ONTARIO_FT1

GROUND

A7
B7
B11
B17
B22
C4
D5
D7
D9
D11
D14
B15
D17
D19
E7
E9
E12
E20
F8
F11
F13
G4
G5
G7
G9
G12
G20
G22
H6
H11
H13
J4
J5
J7
J20
K10
K14
L4
L6
L8
L11
L13
L20
L22
M7
N4
N6
N8
N11

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSBG_DAC

N13
N20
N22
P10
P14
R4
R7
R20
T6
T9
T11
T13
U4
U5
U7
U12
U20
U22
V8
V9
V11
V13
W1
W2
W4
W5
W7
W12
W20
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
AA4
AA22
AB2
AB5
AB9
AB13
AB17
AB21
AC5
AC9
AC13
A11

C

B

B

ONTARIO-FT1-GP



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

5

4

www.bblianmeng.com
3

Date:
2

APU_VSS(5/5)
Document Number

Rev

Enrico 14 AMD
Friday, April 22, 2011

A00
Sheet
1

8

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

5

4

www.bblianmeng.com
3

2

Title

TRAVIS

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet
1

9

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

5

4

www.bblianmeng.com
3

2

Title

Reserved

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet
1

10

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Reserved

Size
A3

Document Number

Date:

Friday, April 22, 2011

Enrico 14 AMD

Rev

A00
Sheet
1

11

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Reserved

Size
A3

Document Number

Date:

Friday, April 22, 2011

Enrico 14 AMD

Rev

A00
Sheet
1

12

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Reserved

Size
A3

Document Number

Date:

Friday, April 22, 2011

Enrico 14 AMD

Rev

A00
Sheet
1

13

of

109

5

4

3

2

1

SSID = MEMORY

D

D

DM1

203
204

0D75V_S0

VTT1
VTT2

C1401
SCD1U10V2KX-5GP

1

SA0_DIM0
SA1_DIM0

DY

C1402
SC2D2U6D3V3KX-GP

C

2

1D5V_S3

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

SA0_DIM0

X01
4
3

SMB_DATA 18
SMB_CLK 18

2

1
2

R1401
0R0402-PAD

SRN22-3-GP
C1423 1
C1424 1

2SC10P50V2JN-4GP
2SC10P50V2JN-4GP

1

PCH_SMBDATA
PCH_SMBCLK

2

SA1_DIM0

RN1401

PCH_SMBDATA
PCH_SMBCLK

R1402
0R0402-PAD

B

1D5V_S3

SODIMM A DECOUPLING

Layout Note:
Place these Caps near
SO-DIMMA.

1

C1410
SC10U6D3V5KX-1GP

DY
2

1

DY
2

2

DY

C1409
SC10U6D3V5KX-1GP

1

C1408
SC10U10V5ZY-1GP

1
2

C1407
SC4D7U6D3V5KX-3GP

1
2

C1406
SC10U6D3V5KX-1GP

1
2

C1405
SC10U10V5ZY-1GP

DY

1

1
2

C1404
SC4D7U6D3V5KX-3GP

X01
1

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

1

77
122
125

2

RESET#

197
201

1

VREF_CA
VREF_DQ

199

C1417
SCD1U10V2KX-5GP

30

5,15 M_RST#

ODT0
ODT1

3D3V_S0

198

2

126
1

DDR_VREF_S3

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

PCH_SMBDATA 15,65
PCH_SMBCLK 15,65

Intel HR DM tied to GND
AMD still following previous design

C1416
SCD1U10V2KX-5GP

116
120

5 M_A_DIM0_ODT0
5 M_A_DIM0_ODT1

0721: Reserve Cap

12
29
47
64
137
154
171
188

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

200
202

5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15

2

M_DQS0
M_DQS1
M_DQS2
M_DQS3
M_DQS4
M_DQS5
M_DQS6
M_DQS7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7

C1403
SC4D7U6D3V5KX-3GP

5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15

10
27
45
62
135
152
169
186

SA0
SA1
NC#1
NC#2
NC#/TEST

M_DIM0_CLK_DDR1 5
M_DIM0_CLK_DDR#1 5

11
28
46
63
136
153
170
187

1

M_DQS#0
M_DQS#1
M_DQS#2
M_DQS#3
M_DQS#4
M_DQS#5
M_DQS#6
M_DQS#7

VDDSPD

M_DIM0_CLK_DDR0 5
M_DIM0_CLK_DDR#0 5

102
104

C1415

5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15

SDA
SCL
EVENT#

101
103

5
5

5,15
5,15

2

C1422
SC1U6D3V2KX-GP

1

DY
2

1
2

C1421
SC1U6D3V2KX-GP

1

DY
2

1
2

C1419
SC1U6D3V2KX-GP

B

C1420
SC1U6D3V2KX-GP

Place these caps
close to VTT1 and
VTT2.

0D75V_S0

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

M_DIM0_CKE0
M_DIM0_CKE1

SCD1U10V2KX-5GP

2

DYC1418
SC10U6D3V5KX-1GP

BA0
BA1

M_A_DIM0_CS#0
M_A_DIM0_CS#1

73
74

1

1

0D75V_S0

CK1
CK1#

114
121

5,15
5,15
5,15

2

2

C1413
SC1KP50V2KX-1GP

CK0
CK0#

M_RAS#
M_WE#
M_CAS#

TC1401
SE220U2VDM-8GP

1

C1412
2
1

DY

2

C1411
SC1KP50V2KX-1GP

SC2D2U6D3V3KX-GP

1

C

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

CS0#
CS1#
CKE0
CKE1

110
113
115

1

DDR_VREF_S3

M_DQ0
M_DQ1
M_DQ2
M_DQ3
M_DQ4
M_DQ5
M_DQ6
M_DQ7
M_DQ8
M_DQ9
M_DQ10
M_DQ11
M_DQ12
M_DQ13
M_DQ14
M_DQ15
M_DQ16
M_DQ17
M_DQ18
M_DQ19
M_DQ20
M_DQ21
M_DQ22
M_DQ23
M_DQ24
M_DQ25
M_DQ26
M_DQ27
M_DQ28
M_DQ29
M_DQ30
M_DQ31
M_DQ32
M_DQ33
M_DQ34
M_DQ35
M_DQ36
M_DQ37
M_DQ38
M_DQ39
M_DQ40
M_DQ41
M_DQ42
M_DQ43
M_DQ44
M_DQ45
M_DQ46
M_DQ47
M_DQ48
M_DQ49
M_DQ50
M_DQ51
M_DQ52
M_DQ53
M_DQ54
M_DQ55
M_DQ56
M_DQ57
M_DQ58
M_DQ59
M_DQ60
M_DQ61
M_DQ62
M_DQ63

NP1
NP2
RAS#
WE#
CAS#

2

5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

C1414
SCD1U10V2KX-5GP

109
108

M_A0
M_A1
M_A2
M_A3
M_A4
M_A5
M_A6
M_A7
M_A8
M_A9
M_A10
M_A11
M_A12
M_A13
M_A14
M_A15

1

5,15 M_BS0
5,15 M_BS1

5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15
5,15

NP1
NP2

2

5,15 M_BS2

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

1

M_RST#
A

DDR3-204P-25-GP

C1425

DYSCD1U10V2KX-5GP

A

2

62.10017.K11
H=5.2mm


Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR3-SODIMM1
Size

Document Number

Rev

Enrico 14 AMD
Date:
5

4

www.bblianmeng.com
3

2

Friday, April 22, 2011

A00
Sheet

1

14

of

109

5

4

3

2

1

SSID = MEMORY

DM2

C1521
SC1U6D3V2KX-GP
2
1

DY

5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14

M_DQS#0
M_DQS#1
M_DQS#2
M_DQS#3
M_DQS#4
M_DQS#5
M_DQS#6
M_DQS#7

5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14

M_DQS0
M_DQS1
M_DQS2
M_DQS3
M_DQS4
M_DQS5
M_DQS6
M_DQS7

12
29
47
64
137
154
171
188
116
120

5 M_B_DIM0_ODT0
5 M_B_DIM0_ODT1

126
1

DDR_VREF_S3

30

5,14 M_RST#

203
204

0D75V_S0

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2

200
202

1

1

1

2

2

2

SA0_DIM1
SA1_DIM1

Intel HR DM tied to GND
AMD still following previous design

R1502
0R0402-PAD

PCH_SMBDATA 14,65
PCH_SMBCLK 14,65

3D3V_S0

Intel HR B channel address is 01
AMD B channel address is 10

198
199

1D5V_S3

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

DY

C

1D5V_S3

C1510

1

DY
2

C1509

1
2

1

C1508

DY
2

1
2

C1507
SC4D7U6D3V5KX-3GP

2

1

C1506
SC10U6D3V5KX-1GP

1
2

C1505
SC4D7U6D3V5KX-3GP
C1513

1
2

Layout Note:
Place these Caps near
SO-DIMMB.

DY

SCD1U10V2KX-5GP
2
1

DY

1

SODIMM B DECOUPLING

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

2

77
122
125

SA0_DIM1
SA1_DIM1

C1504
SC10U10V5ZY-1GP

197
201

0721 change 4k7 to 10k

2

5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14

R1501
10KR2J-3-GP

1

M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7

R1532
69D8R2F-GP

DYDY

1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M_DIM0_CLK_DDR3 5
M_DIM0_CLK_DDR#3 5

11
28
46
63
136
153
170
187

R1531
69D8R2F-GP

2

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

102
104

5,14
5,14

C1512
SCD1U10V2KX-5GP

SA0
SA1
NC#1
NC#2
NC#/TEST

M_DIM0_CLK_DDR2 5
M_DIM0_CLK_DDR#2 5

1

VDDSPD

M_DIM0_CKE0
M_DIM0_CKE1

101
103

3D3V_S0

2

SDA
SCL
EVENT#

73
74

D

M_DIM0_CKE0
M_DIM0_CKE1

5
5

C1514
SCD1U10V2KX-5GP

10
27
45
62
135
152
169
186

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

M_B_DIM0_CS#0
M_B_DIM0_CS#1

C1503
SC10U10V5ZY-1GP

1
2

1
2

SC2D2U6D3V3KX-GP

C1520
SC1U6D3V2KX-GP
2
1

C1519
SC1U6D3V2KX-GP
2
1

C1518
SC1U6D3V2KX-GP
2
1

DY

Place these caps
close to VTT1 and
VTT2.

CK1
CK1#

BA0
BA1

114
121

5,14
5,14
5,14

SC10U6D3V5KX-1GP

0D75V_S0
B

DY

C1517
SCD1U10V2KX-5GP

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

CK0
CK0#

M_RAS#
M_WE#
M_CAS#

SC10U6D3V5KX-1GP

C1515
SCD1U10V2KX-5GP

2

1

DDR_VREF_S3

M_DQ0
M_DQ1
M_DQ2
M_DQ3
M_DQ4
M_DQ5
M_DQ6
M_DQ7
M_DQ8
M_DQ9
M_DQ10
M_DQ11
M_DQ12
M_DQ13
M_DQ14
M_DQ15
M_DQ16
M_DQ17
M_DQ18
M_DQ19
M_DQ20
M_DQ21
M_DQ22
M_DQ23
M_DQ24
M_DQ25
M_DQ26
M_DQ27
M_DQ28
M_DQ29
M_DQ30
M_DQ31
M_DQ32
M_DQ33
M_DQ34
M_DQ35
M_DQ36
M_DQ37
M_DQ38
M_DQ39
M_DQ40
M_DQ41
M_DQ42
M_DQ43
M_DQ44
M_DQ45
M_DQ46
M_DQ47
M_DQ48
M_DQ49
M_DQ50
M_DQ51
M_DQ52
M_DQ53
M_DQ54
M_DQ55
M_DQ56
M_DQ57
M_DQ58
M_DQ59
M_DQ60
M_DQ61
M_DQ62
M_DQ63

CKE0
CKE1

X01

110
113
115

SC10U10V5ZY-1GP

5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14

C

C1516

109
108

CS0#
CS1#

NP1
NP2

1

M_BS0
M_BS1

NP1
NP2
RAS#
WE#
CAS#

2

M_BS2

5,14
5,14

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

C1511
SC1U6D3V2KX-GP

5,14

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

C1502
SC2D2U6D3V3KX-GP
2
1

D

M_A0
M_A1
M_A2
M_A3
M_A4
M_A5
M_A6
M_A7
M_A8
M_A9
M_A10
M_A11
M_A12
M_A13
M_A14
M_A15

C1501
SCD1U10V2KX-5GP
2
1

5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14
5,14

B

SO-DIMMB is placed farther from
the Processor than SO-DIMMA

DDR3-204P-24-GP

62.10017.K01
H=9.2mm

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR3-SODIMM2
Size

Document Number

Rev

Enrico 14 AMD
5

4

www.bblianmeng.com
3

Date:
2

Friday, April 22, 2011

A00
Sheet

1

15

of

109

5

4

3

2

1

D

D

C

C

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

5

4

www.bblianmeng.com
3

Date:
2

Reserved
Document Number

Rev

Enrico 14 AMD
Friday, April 22, 2011

A00
Sheet
1

16

of

109

5

4

3

2

1

SSID = FCH

2

3D3V_S0

1

UMA

C1701 1
C1712 1

2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP

PCIE_TXP0_C
PCIE_TXN0_C

WLAN

65 PCIE_TXP2
65 PCIE_TXN2

C1713 1
C1714 1

2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP

PCIE_TXP2_C
PCIE_TXN2_C

LAN

31 PCIE_RXP0
31 PCIE_RXN0

WLAN

65 PCIE_RXP2
65 PCIE_RXN2

AA22
Y21
AA25
AA24
W23
V24
W24
W25

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

C

EXT clock_Gen
RN1702 2
0R4P2R-PAD 1

6 DISP_CLKP
6 DISP_CLKN

100MHZ

6 APU_CLKP
6 APU_CLKN

100MHZ

83 CLK_PCIE_VGA
83 CLK_PCIE_VGA#

X02

TP1705
TP1706

3
4
1
1

RN

TPAD14-GP
TPAD14-GP

M23
P23

FCHDISP_CLKP_R
FCHDISP_CLKN_R

U29
U28

NB_HT_CLKP
NB_HT_CLKN

T26
T27

RN1703 2
SRN22-3-GP 1

3
4

FCHAPU_CLKP_R
FCHAPU_CLKN_R

V21
T21

RN1701 2
SRN22-3-GP 1

3
4

FCHGFX_CLKP_R
FCHGFX_CLKN_R

V23
T23
L29
L28

WLAN

RN1704 2
0R4P2R-PAD 1

CLK_MINI1_R
CLK_MINI1#_R

3
4

N29
N28

RN

M29
M28

LAN

RN1705 2
0R4P2R-PAD 1

LAN_CLK_R
LAN_CLK#_R

3
4

T25
V25
L24
L23

RN

B

CLKREQ#

New Card

0

1

WLAN

2

WWAN

2

3

LAN

3

4

X

5

X

6

X

7

X

8

X

P25
M25

1

P29
P28
N26
N27

if LAN support Wake on S5,
do not use clock from FCH,
have use X'tal

T29
T28

SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N

INTE#_GPIO32
INTF#_GPIO33
INTG#_GPIO34
INTH#_GPIO35

GPP_CLK1P
GPP_CLK1N

32 CLK_PCH_48M

1

GPP_CLK3P
GPP_CLK3N
CLOCK GENERATOR
GPP_CLK4P
GPP_CLK4N
GPP_CLK5P
GPP_CLK5N
GPP_CLK6P
GPP_CLK6N

48M_OSC

2

L25

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LPC
LAD3
LFRAME#
LDRQ0#
LDRQ1#_CLK_REQ6#_GPIO49
SERIRQ_GPIO48

GPP_CLK7P
GPP_CLK7N
GPP_CLK8P
GPP_CLK8N

ALLOW_LDTSTP_DMA_ACTIVE#
PROCHOT#
LDT_PG
LDT_STP#
CPU
LDT_RST#

C1721
SC10P50V2JN-4GP

L26

DY
25M_X2

L27

G21
H21
K19
G22
J24

1

1

DY

2

KBC

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27

21
21
21
21
21

PCIE_RST#_C

R1708

1

33R2J-2-GP

2

PLT_RST# 31,65,71,83

PE_GPIO0 83

X01

C1711
SC150P50V2KX-GP

folloiwng Intel HR netname

Debug Strap
1D5V_VGA_PWOK

83,86

LDT_STP# connection is just
for chipset automation purpose.
It is an automatic test for
AMD validation team only
3D3V_S0

R1713
1KR2J-1-GP
1
2

APU_STOP#

R1712

X01

DY
RTC_SENSE 60

GPIO42

1

TP1707

TPAD14

GPIO46

1

TP1708

TPAD14

checklist:No PU Res
Integrated Resistor PU10K

PE_GPIO1 92,93

R1719 1
R1720 1

27

PM_CLKRUN#

222R2J-2-GP
2 0R0402-PAD
RN1706 1
0R4P2R-PAD 2

LPCCLK0_R
LPCCLK1_R
LPC_AD0_R
LPC_AD1_R
LPC_AD2_R
LPC_AD3_R

INT_SERIRQ

2

INT_SERIRQ

LPC_AD0 27,71
LPC_AD1 27,71

4
3

LPC_AD2 27,71
LPC_AD3 27,71

INT_SERIRQ

1
DY
10KR2J-3-GP

3D3V_S0

X01

LPC_CLK0 21,27
LPC_CLK1 21
4
3

LPC_FRAME#

R1714

integrated PU

32K_X1

0819
RN1707 1
0R4P2R-PAD 2

1D8V_S0

PE_GPIO0 ->VGA_RESET
PE_GPIO1 ->VGA_PowerEnable

PM_CLKRUN#

56

DY

Muxless support

SC10P50V2JN-4GP
C1716 1
2

SATA_ODD_DA#

C

0709

C1715 1

2 SC18P50V2JN-1-GP

R1715
20MR3-GP

X1701
X-32D768KHZ-67-GP

27,71

27

32K_X2

C17171

SC18P50V2JN-1-GP
2

ALLOW_STOP 6
APU_PROCHOT#_VDDIO 6
H_CPUPWRGD 6,36,42,71

APU_STOP#

B

APU_RST# 6,83

25M_X1

25M_X2

RTC

32K_X2

RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G

C1

32K_X1

C2

32K_X2

D2
B2
B1

INTRUDER_ALERT# 1

R1701 1
TP1701TPAD14

2 0R0402-PAD

PCH_SUSCLK_KBC

27

RTC_AUX_S5

HUDSON-M1-1-GP

2

1

0811 EMI

R1711

14M_25M_48M_OSC
32K_X1

25M_X1

3D3V_S0

AJ6
AG6
AG4
AJ4

H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19

DY

0712

0806

22R2J-2-GP

Use 48Mhz CLK For 5138

C1722

dGPU_PRSNT#

GPP_CLK2P
GPP_CLK2N

R1716

1

0

Device

CPU_HT_CLKP
CPU_HT_CLKN

2

GPP CLK port

NB_HT_CLKP
NB_HT_CLKN

DY

SC10P50V2JN-4GP

RN

31 CLK_PCIE_LAN
31 CLK_PCIE_LAN#

NB_DISP_CLKP
NB_DISP_CLKN

PCI_CLK3_R

RN

65 CLK_PCIE_WLAN
65 CLK_PCIE_WLAN#

PCIE_RCLKP_NB_LNK_CLKP
PCIE_RCLKN_NB_LNK_CLKN

R1721
0R2J-2-GP
1
2

3

31 PCIE_TXP0
31 PCIE_TXN0

0811 EMI

4

AA28
AA29
Y29
Y28
Y26
Y27
W28
W29

LAN

PCIE_CALRP
PCIE_CALRN

D

TP1703TPAD14

1

2

AD29
AD28

33MHZ

1

PCIE_CALRP_R
PCIE_CALRN_R

AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7

PCI_CLK1 21
PCI_CLK2 21
CLK_PCI_LPC 21,71
PCI_CLK4 21

1

590R2F-GP
2

1 R1710 2
2KR2F-3-GP

AD0_GPIO0
AD1_GPIO1
AD2_GPIO2
AD3_GPIO3
AD4_GPIO4
AD5_GPIO5
AD6_GPIO6
AD7_GPIO7
AD8_GPIO8
AD9_GPIO9
AD10_GPIO10
AD11_GPIO11
AD12_GPIO12
AD13_GPIO13
AD14_GPIO14
AD15_GPIO15
AD16_GPIO16
AD17_GPIO17
AD18_GPIO18
AD19_GPIO19
AD20_GPIO20
AD21_GPIO21
AD22_GPIO22
AD23_GPIO23
AD24_GPIO24
AD25_GPIO25
AD26_GPIO26
AD27_GPIO27
AD28_GPIO28
AD29_GPIO29
AD30_GPIO30
AD31_GPIO31
CBE0#
PCI I/F
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#_GPIO40
REQ2#_CLK_REQ8#_GPIO41
REQ3#_CLK_REQ5#_GPIO42
GNT0#
GNT1#_GPO44
GNT2#_GPO45
GNT3#_CLK_REQ7#_GPIO46
CLKRUN#
LOCK#

0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD

2

1R1709
1D1V_PCIE_S0

PCI EXPRESS I/F
UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

V2

PCI_RST#

2
2
2
2

1

AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24

UMI_APU_FCH_TX0P
UMI_APU_FCH_TX0N
UMI_APU_FCH_TX1P
UMI_APU_FCH_TX1N
UMI_APU_FCH_TX2P
UMI_APU_FCH_TX2N
UMI_APU_FCH_TX3P
UMI_APU_FCH_TX3N

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

TP1702TPAD14

1
1
1
1
1

2

AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27

X01
R1705
R1718
R1706
R1707

2

A_RX0P_C
A_RX0N_C
A_RX1P_C
A_RX1N_C
A_RX2P_C
A_RX2N_C
A_RX3P_C
A_RX3N_C

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

PCI_CLK0_R
PCI_CLK1_R
PCI_CLK2_R
PCI_CLK3_R
PCI_CLK4_R

1

0721 Change CAP 10V to 16V

2
2
2
2
2
2
2
2

W2
W1
W3
W4
Y1

10KR2J-3-GP

4
4
4
4
4
4
4
4

C1703 1
C1704 1
C1705 1
C1706 1
C1707 1
C1708 1
C1709 1
C1710 1

R1703
PCICLK0
PCICLK1_GPO36
PCICLK2_GPO37
PCICLK3_GPO38
PCICLK4_14M_OSC_GPO39
PCI CLKS
PCIRST#

DIS_PX 10KR2J-3-GP

2

UMI_FCH_APU_RX0P
UMI_FCH_APU_RX0N
UMI_FCH_APU_RX1P
UMI_FCH_APU_RX1N
UMI_FCH_APU_RX2P
UMI_FCH_APU_RX2N
UMI_FCH_APU_RX3P
UMI_FCH_APU_RX3N

PCIE_RST#
A_RST#

1

27,36 A_RST#
4
4
4
4
4
4
4
4

D

P1
L1

10KR2J-3-GP

PCIE_RST#_C
A_RST#_R

2

1

HUDSON-1

R1704 1 33R2J-2-GP
2

dGPU_PRSNT#

2

1 OF 5

FCH1A
C1702
SC150P50V2KX-GP

R1702
10KR2J-3-GP

C1718
SC1U6D3V2KX-GP

25M_X1

1

R1717

25M_X2

2 1MR2J-1-GP

1

A

X01

A

R1766
1KR2J-1-GP
2



4

3

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

X02

2

1

X1702
XTAL-25MHZ-155-GP

2

1

C1719
SC18P50V2JN-1-GP

X01

1

2

X02

Title

C1720
SC18P50V2JN-1-GP

HUDSON-M1_ACPI/PCI/CLK(1/6)
Size
A2
Date:

5

4

www.bblianmeng.com
3

2

Document Number

Rev

Enrico 14 AMD

A00
Sheet

Friday, April 22, 2011
1

17

of

109

5

3D3V_S5

4

0720 POP

USB_OC#2
USB_OC#1

4
3
SRN10KJ-5-GP
RN1801
4
3

0720: Change From 2.2K and POP
27,36,44,46,47 PM_SLP_S3#
27,44 PM_SLP_S5#
27 PM_PWRBTN#
36 FCH_PWRGD

RN1803
FCH_TEST0
FCH_TEST1
FCH_TEST2

8
7
6
5

DY

J2
K1
D3
F1
H1
F2
H5
G6
B3
C4
F6
AD21
AE21
K2
J29
H2
J1
H6
F3
J6
AC19

PM_PWRBTN#_R
2 0R0402-PAD

R1804 1

SRN2K2J-2-GP

EC_SCI#
EC_SWI#

2 10KR2J-3-GP
2 10KR2J-3-GP

DY
DY

R1806 1

R1807 1
R1808 1

2 0R0402-PAD
2 0R0402-PAD

R1801 1

2 0R0402-PAD

27 PCH_WAKE#

R1825 1

2 0R0402-PAD

27,31 PCIE_WAKE#

R1826 1

27 H_A20GATE
27 H_RCIN#
27 EC_SCI#
EC_SMI#

0817 Add 27

integrated PU
R1803 1
R1805 1

PM_PWRBTN#

2 10KR2J-3-GP

6,36 H_THERMTRIP#
3D3V_S0
27 RSMRST#_KBC

R1810 1

G1

R1815 1

2

29 HDA_SPKR
14 SMB_CLK
14 SMB_DATA

3D3V_S0

DY 2 10KR2J-3-GP
integrated PU

integrated PU

R1816 1

85 PEG_CLKREQ#
H_A20GATE
H_RCIN#

A00

56 ODD_DA_Q
56 SATA_ODD_PRSNT#

EC1801 1
SC22P50V2JN-4GP

2
R1819
R1820

R1821
R1822

1

TP1802

1

DY

20R2J-2-GP

USB_OC7#
EC_SWI#
USB_OC5#

SATA_ODD_PRSNT#_R

EC1802
SC180P50V2JN-1GP

2
2

1
1

2
2

SRN10KJ-6-GP

33R2J-2-GP
33R2J-2-GP

DY
3D3V_S5

HDA_CODEC_RST#

33R2J-2-GP
33R2J-2-GP

HDA_SYNC
HDA_RST#

GBE_PHY_INTR

T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7

TP_DEBUG_DAT
TP_DEBUG_CLK
SPI_CS2#
GPO160

E23
E24
F21
G29

2 R1823 1GBE_MDIO
10KR2J-3-GP

4
3
GBE_RXERR

SRN10KJ-5-GP
R1824
100KR2J-1-GP
1

Rename 0712
RN1808
RSMRST#_KBC

Confirm with SW, RSMRST# from KBC is push-pull.
It can be drived high by SW.

1
2

H3
D1
E4
D4
E8
F7
E7
F8

M3
N1
L2
M2
M1
M4
N2
P2

RN1807
1
2

2

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0

GBE_COL
GBE_CRS

2

HDA_SDIN0
HDA_CODEC_BITCLK

1
1

1

29 HDA_CODEC_SYNC
29 HDA_CODEC_RST#
RN1805

DY

TP1801

TPAD14-GP

CLKREQG#

21 HDA_SDOUT

29 HDA_CODEC_BITCLK
29 HDA_CODEC_SDOUT
29 HDA_SDIN0

1
2
3
4

2 0R0402-PAD

61 USB_OC#2
61 USB_OC#1

SMB_CLK
SMB_DATA

SRN2K2J-1-GP

8
7
6
5

HDA_SPKR_R

CLK_PCIE_WLAN_REQ#_R
0R0402-PAD

TPAD14-GP

R1818 1

RN1804
4
3

2

R1817 1

27 EC_SWI#

1
2

2 0R0402-PAD

SCLK1
SDATA1

65 CLK_PCIE_WLAN_REQ#

EC_SMI#

R1812 1

2 10KR2J-3-GP
2 10KR2J-3-GP

AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
F5
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
AA20

31 PCIE_CLK_LAN_RQ1#
C1801
SCD1U10V2KX-5GP

0812

DY
DY

NB_PWRGD

10KR2J-3-GP
2

2 0R0402-PAD RSMRST#_R

DY

R1813 1
R1814 1

PCIE_WAKE#_R

20R2J-2-GP

DY

R1809
1

FCH_TEST0
FCH_TEST1
FCH_TEST2
EC_A20M#_R
EC_KB_RST#_R
EC_SCI#
EC_SMI#_R

1

AMD recommand external PU

C

4 OF 5

FCH1D
HUDSON-1

SCLK1
SDATA1

SRN10KJ-5-GP
1
2
3
4

1

SSID = FCH

1
2

D

2

Integrated PU is not
supported when the pin is
configured for USB over
current function.

RN1802

1
2

3

4
3
SRN10KJ-5-GP

B

TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP

TP1803
TP1804
TP1805
TP1806

1
1
1
1

D27
F28
F29
E27

PCI_PME#_GEVENT4#
RI#_GEVENT22#
SPI_CS3#_GBE_STAT1_GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST0
TEST1_TMS
TEST2
GA20IN_GEVENT0#
KBRST#_GEVENT1#
LPC_PME#_GEVENT3#
LPC_SMI#_GEVENT23#
GEVENT5#
SYS_RESET#_GEVENT19#
WAKE#_GEVENT8#
IR_RX1_GEVENT20#
THRMTRIP#_SMBALERT#_GEVENT2#
NB_PWRGD
ACPI/WAKE UP EVENTS
RSMRST#

USBCLK_14M_25M_48M_OSC
USB_RCOMP

USB 1.1
USB_FSD1P_GPIO186
USB_FSD1N
USB_FSD0P_GPIO185
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB_HSD12P
USB_HSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
USB_HSD9P
USB_HSD9N
USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB 2.0
USB_HSD6P
USB_HSD6N
USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N

BLINK_USB_OC7#_GEVENT18#
USB_OC6#_IR_TX1_GEVENT6#
USB_OC5#_IR_TX0_GEVENT17#
USB_OC4#_IR_RX0_GEVENT16#
USB_OC3#_AC_PRES_TDO_GEVENT15#
USB_OC2#_TCK_GEVENT14#
USB_OC1#_TDI_GEVENT13#
USB_OC0#_TRST#_GEVENT12#
USB OC

USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N

HD AUDIO

GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL_RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL_TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR

G19

USB_RCOMP

2

R1811
11K8R2F-GP
1

USB MISC

CLK_REQ4#_SATA_IS0#_GPIO64
CLK_REQ3#_SATA_IS1#_GPIO63
SMARTVOLT1_SATA_IS2#_GPIO50
CLK_REQ0#_SATA_IS3#_GPIO60
SATA_IS4#_FANOUT3_GPIO55
SATA_IS5#_FANIN3_GPIO59
SPKR_GPIO66
SCL0_GPIO43
SDA0_GPIO47
SCL1_GPIO227
SDA1_GPIO228
CLK_REQ2#_FANIN4_GPIO62
CLK_REQ1#_FANOUT4_GPIO61
IR_LED#_LLB#_GPIO184
SMARTVOLT2_SHUTDOWN#_GPIO51
DDR3_RST#_GEVENT7#
GBE_LED0_GPIO183
GBE_LED1_GEVENT9#
GBE_LED2_GEVENT10#
GBE_STAT0_GEVENT11#
CLK_REQG#_GPIO65_OSCIN
GPIO

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0_GPIO167
AZ_SDIN1_GPIO168
AZ_SDIN2_GPIO169
AZ_SDIN3_GPIO170
AZ_SYNC
AZ_RST#

A10

SCL2_GPIO193
SDA2_GPIO194
SCL3_LV_GPIO195
SDA3_LV_GPIO196
EC_PWM0_EC_TIMER0_GPIO197
EC_PWM1_EC_TIMER1_GPIO198
EC_PWM2_EC_TIMER2_GPIO199
EC_PWM3_EC_TIMER3_GPIO200

GBE LAN

PS2_DAT_SDA4_GPIO187
PS2_CLK_SCL4_GPIO188
SPI_CS2#_GBE_STAT2_GPIO166
FC_RST#_GPO160
PS2KB_DAT_GPIO189
PS2KB_CLK_GPIO190
PS2M_DAT_GPIO191
PS2M_CLK_GPIO192

KSI_0_GPIO201
KSI_1_GPIO202
KSI_2_GPIO203
KSI_3_GPIO204
KSI_4_GPIO205
KSI_5_GPIO206
KSI_6_GPIO207
KSI_7_GPIO208
KSO_0_GPIO209
KSO_1_GPIO210
KSO_2_GPIO211
KSO_3_GPIO212
KSO_4_GPIO213
KSO_5_GPIO214
KSO_6_GPIO215
KSO_7_GPIO216
KSO_8_GPIO217
KSO_9_GPIO218
KSO_10_GPIO219
KSO_11_GPIO220
KSO_12_GPIO221
KSO_13_GPIO222
KSO_14_GPIO223
KSO_15_GPIO224
KSO_16_GPIO225
KSO_17_GPIO226

D

J10
H11
H9
J8

Pair
B12
A12
F11
E11
E14
E12
J12
J14
A13
B13

USB_PP9 32
USB_PN9 32

D13
C13
G12
G14

USB_PP7 49
USB_PN7 49

G16
G18

USB_PP6 82
USB_PN6 82

D16
C16
B14
A14

USB Device

0

USB 2.0 EXT.Port1

1

Mini Card1 (WLAN)

2

USB 2.0 EXT.Port1

3

NC

4

NC

5

NC

6

USB 2.0 EXT.Port1

7

CCD Camera

8

NEWCARD

9

Card Reader

10

NC

11

NC

12

NC

13

NC

E18
E16
J16
J18

USB_PP2 82
USB_PN2 82

B17
A17

USB_PP1 65
USB_PN1 65

A16
B16

USB_PP0 61
USB_PN0 61

D25
F23
B26
E26
F25
E22
F22
E21

C

RN1806

SCL2
SDAT2

1
2

4
3
SRN10KJ-5-GP

if not used SMBUS or GPIO ,PD 10K

SCL2
SDAT2
SCLK3
SDATA3

SCLK3 6
SDATA3 6
EC_PWM2 21
EC_PWM3 21

0719 AMD Confirm

G24
G25
E28
E29
D29
D28
C29
C28

3D3V_S5

RN1809
SCLK3
SDATA3

B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22

1
2

4
3
SRN2K2J-1-GP

B

EMBEDDED CTRL

HUDSON-M1-1-GP

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

HUDSON-M2(2/6)
Document Number

Rev

Enrico 14 AMD
5

4

www.bblianmeng.com
3

Date:
2

Friday, April 22, 2011

A00
Sheet

1

18

of

109

5

4

3

2

1

2 OF 5

FCH1B

0721 Change CAP to 10n

HUDSON-1
C1901 1
C1902 1

56 SATA_TXP0
56 SATA_TXN0

SATA HDD

56 SATA_RXN0_C
56 SATA_RXP0_C
C1903 1
C1904 1

56 SATA_TXP1
56 SATA_TXN1
D

2SCD01U16V2KX-3GP SATA_TXP0_C
2SCD01U16V2KX-3GP SATA_TXN0_C

SATA ODD

2SCD01U16V2KX-3GP SATA_TXP1_C
2SCD01U16V2KX-3GP SATA_TXN1_C

56 SATA_RXN1_C
56 SATA_RXP1_C

PLACE SATA AC DECOUPLING
CAPS CLOSE TO FCH

1D1V_SATA_S0

1KR2F-3-GP
R1902 1
2 SATA_CALP
R1903 1
2 SATA_CALN
931R2F-1-GP

C

AH9
AJ9

SATA_TX0P
SATA_TX0N

AJ8
AH8

SATA_RX0N
SATA_RX0P

AH10
AJ10

SATA_TX1P
SATA_TX1N

AG10
AF10

SATA_RX1N
SATA_RX1P

AG12
AF12

SATA_TX2P
SATA_TX2N

AJ12
AH12

SATA_RX2N
SATA_RX2P

AH14
AJ14

SATA_TX3P
SATA_TX3N

AG14
AF14

SATA_RX3N
SATA_RX3P

AG17
AF17

SATA_TX4P
SATA_TX4N

AJ17
AH17

SATA_RX4N
SATA_RX4P

AJ18
AH18

SATA_TX5P
SATA_TX5N

AH19
AJ19

SATA_RX5N
SATA_RX5P

AB14
AA14
AD11

68 SATA_LED#

GPIOD

TP621
TP620
TP619
TP618
TP617

FCH_SPI_DI
FCH_SPI_SI
FCH_SPI_CLK
FCH_SPI_CS0#
FCH_SPI_W P#

SATA_CALRP
SATA_CALRN
SATA_ACT#_GPIO67

AD16

SATA_X1

AC16

SATA_X2

J5
E2
K4
K9
G2

AH28
AG28
AF26

FC_OE#_GPIOD145
FC_AVD#_GPIOD146
FC_WE#_GPIOD148
FC_CE1#_GPIOD149
FC_CE2#_GPIOD150
FC_INT1_GPIOD144
FC_INT2_GPIOD147

AF28
AG29
AG26
AF27
AE29
AF29
AH27

FC_ADQ0_GPIOD128
FC_ADQ1_GPIOD129
FC_ADQ2_GPIOD130
FC_ADQ3_GPIOD131
FC_ADQ4_GPIOD132
FC_ADQ5_GPIOD133
FC_ADQ6_GPIOD134
FC_ADQ7_GPIOD135
FC_ADQ8_GPIOD136
FC_ADQ9_GPIOD137
FC_ADQ10_GPIOD138
FC_ADQ11_GPIOD139
FC_ADQ12_GPIOD140
FC_ADQ13_GPIOD141
FC_ADQ14_GPIOD142
FC_ADQ15_GPIOD143

AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26

SSID = FCH
GPIOD[150:128] are open drain GPIO pins
where as GPO160 is an open drain GPO pin.
These pins are not programmed to GPIO mode by default.
D

If use as GPIO, need to pull up to 1.8V_RUN

SERIAL ATA

[checklist]:integrated Clock Mode=>Left unconnected

TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP

FC_CLK
FC_FBCLKOUT
FC_FBCLKIN

FANOUT0_GPIO52
FANOUT1_GPIO53
FANOUT2_GPIO54

W5
W6
Y9

FANIN0_GPIO56
FANIN1_GPIO57
FANIN2_GPIO58

W7
V9
W8

TEMPIN0_GPIO171
TEMPIN1_GPIO172
TEMPIN2_GPIO173
TEMPIN3_TALERT#_GPIO174
TEMP_COMM
HW MONITOR
VIN0_GPIO175
VIN1_GPIO176
VIN2_GPIO177
VIN3_GPIO178
VIN4_GPIO179
VIN5_GPIO180
VIN6_GBE_STAT3_GPIO181
VIN7_GBE_LED3_GPIO182

B6
A6
A5
B5
C7

GPIO171
FCH_USB3.0PORT_EN#
MB_THRMDA_FCH
APU_TALERT#

A3
B4
A4
C5
A7
B7
B8
A8

PSW _CLR#
VRAM_SIZE1
VRAM_SIZE2
MEM_1V5
MEM_1V35
VIN_VDDIO
VIN_VDDR
GPIO182

SPI ROM
SPI_DI_GPIO164
SPI_DO_GPIO163
SPI_CLK_GPIO162
SPI_CS1#_GPIO165
ROM_RST#_GPIO161

NC#G27
NC#Y2

SATA_ODD_PW RGT 56

FCH_PROCHOT#_C

support ODD Zero power

1
TP1902

C

G27
Y2

VDDIO

R1904

1

MEM_1V5

1.5V

H

1.35V

L

2 0R0402-PAD

APU_ALERT#_FCH 6

MEM_1V35
Don't Care
H

HUDSON-M1-1-GP

XTAL
1'nd 82.30020.851
2'nd 82.30020.791

B

3D3V_S5

[VRAM_SIZE1:VRAM_SIZE2]
LL=512M / HL=1G / LH=2G

1

B

R1908

RN1902
GPIO171
FCH_USB3.0PORT_EN#
MEM_1V5
MB_THRMDA_FCH

10KR2J-3-GP
2

1G

1

SRN10KJ-6-GP

R1909
10KR2J-3-GP
2

RN1901

1
2
3
4

VIN_VDDR
GPIO182
VIN_VDDIO
MEM_1V35

8
7
6
5

VRAM_SIZE1
VRAM_SIZE2

1

8
7
6
5

R1910
10KR2J-3-GP
2

1
2
3
4

512M

SRN10KJ-6-GP

A



if not used HWM or GPIO ,PD 10K

A

Wistron Corporation
R1911 1

PSW _CLR#

2
10KR2J-3-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

HUDSON-M1 SATA/HWM/SPI(3/6)
Size

Document Number

Rev

Enrico 14 AMD
5

4

www.bblianmeng.com
3

Date:
2

Friday, April 22, 2011

A00
Sheet
1

19

of

109

5

4

3D3V_S0

1
2

1
2

C2001

1
2

C2004

C2003

1

1
2

VDDIO_AZ

A11
B11

197mA

VDDCR_11_USB_S

M21

47mA

3D3V_VPPL_SYS_S0

L22

62mA

1D1V_VPPL_SYS_S5

F19

17mA

3D3V_USB_S5

D6

5mA

3D3V_VDDAN_HWM_S5

L20

TBD

VDDCR_11_S

1
2

1
2

C2040

1
2

1

1
2

1
2

C2046

220 ohm 300mA
If support USB 3.0 or LAN wake-up, pls tie to 3.3V_S5
otherwise, tie to 3.3V_S0

1

L2012
2
BLM15AG221SS1D-GP
1

C2053
SCD1U10V2KX-5GP

1 R2006

VDDIO_AZ

2 0R0402-PAD
1

2

3D3V_S5

C2052
SC2D2U6D3V3KX-GP

2

68.00084.E21

1

1

1
C2051
SCD1U10V2KX-5GP

2

2

1

C2055
SCD1U10V2KX-5GP

C2050
SC2D2U6D3V3KX-GP

2

C2054
SC2D2U6D3V3KX-GP

2

68.00084.E21

1D1V_VPPL_SYS_S5

2
BLM15AG221SS1D-GP

68.00084.E21

68.00084.E21

Codec power use3.3V,VDDIO_AZ have to tied to 3.3V
Codec power use1.5V,VDDIO_AZ have to tied to 1.5V
If use 1.5V_S5 power,have to add LDO for it extra

220 ohm 300mA
1D1V_S5

1

1

L2011
2
BLM15AG221SS1D-GP
1

1

DY

L2009
BLM15AG221SS1D-GP
2

2

C2049

1
2

C2048

3D3V_VDDAN_HWM_S5
L2010

3D3V_VPPL_SYS_S0

3D3V_S5

1

VDDAN_1.1V_USB
SCD1U10V2KX-5GP

SC2D2U6D3V3KX-GP

3D3V_S0

1

1

DY

L2007
BLM15AG221SS1D-GP
2

VDDXL_3.3V

220 ohm 300mA
3D3V_S5

2

1
2

1
2

C2028

1
2

C2032

2

1D1V_S5

1

B

L2001
BLM15AG221SS1D-GP
2

68.00084.E21

220 ohm 300mA

C2020

C2019

1

C2011
C2018

2

1
2
1
2

1
2

C2015

1
2

C2017

1
2

C2010

C2014

C2016
C2027

1
2

TBD

C2047

1

113mA

M8

2 0R0402-PAD

2

1
2

C2045

C2044

VDDAN_33_HWM_S

F26
G26

R2001 1

1D1V_S5

220 ohm 300mA

68.00206.141

C

HUDSON-M1-1-GP

1

1D1V_S0

1D1V_S5

C2039

VDDPL_33_SYS
PLL
VDDPL_11_SYS_S

32mA

2

VDDIO_AZ_S
VDDCR_11_USB_S
VDDCR_11_USB_S

A21
D21
B21
K10
L10
J9
T6
T8

C2038

1
2

C2037

1
2

1

C2036

C2035

2

1
2

1
2

C2033

C2034
1
2

C2043

1
2

1

1

C2026
CORE S5
VDDCR_11_S
VDDCR_11_S

DY

C2031

1
2

VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S

VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA

VDDAN_11_USB_S
VDDAN_11_USB_S

145mA

SC2D2U6D3V3KX-GP

2

C11
D11

M6
P8

3.3V_S5 I/O

VDDXL_33_S

B

33 ohm 3A
L2003
1
2
PBY160808T-330Y-N-GP

3D3V_S5

SCD1U10V2KX-5GP

C2042

2

1

1
2

1
2

C2025

C2024

C2030

1
2

SERIAL ATA
VDDPL_33_SATA

VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S

63mA

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2041

C2009

2

1
2

1
2

C2008

C2007

1
2

1

C2006

C2005

2

1
2

1
2

C2013

C2012
1
2

1
2

C2023

1

C2021

C2022

2

C2029

VDDIO_GBE_S
VDDIO_GBE_S

L7
L9

SCD1U10V2KX-5GP

TBD

DY

DY

SC10U6D3V5KX-1GP

VDDCR_11_GBE_S
VDDCR_11_GBE_S

VDDPL_33_USB_S

DY

SC1U6D3V2KX-GP

VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE

SC10U6D3V5KX-1GP

A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19

DY

L2008
HCB2012KF-221T30-GP
1
2

220 ohm 3A

SCD1U10V2KX-5GP

567mA

AJ20
AF18
AH20
AG19
AE18
AD18
AE16

3D3V_USB_S5

68.00216.161
2ND = 68.00206.121

1D1V_CKVDD_S0

2 R2005
0R0402-PAD

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

D

X01

VDDPL_33_PCIE

USB I/O
SC1U6D3V2KX-GP

3D3V_S5

AD14

658mA
SC10U6D3V5KX-1GP

33 ohm 3A

TBD
2mA

SCD1U10V2KX-5GP

U26
V22
V26
V27
V28
V29
W22
W26

93mA

DY

L2006
PBY160808T-330Y-N-GP
2

68.00206.141

VDDRF_GBE_S 1

SC1U6D3V2KX-GP

1D1V_SATA_S0

M10

SC2D2U6D3V3KX-GP

220 ohm 300mA

1D1V_S0
0R0603-PAD
2

1

GBE LAN

600mA

VDDPL_3.3V_SATA
SCD1U10V2KX-5GP

SC2D2U6D3V3KX-GP

68.00084.E21

V1

DY

SCD1U10V2KX-5GP

AE28

TBD

DY

SCD1U10V2KX-5GP

43mA

DY

K28
K29
J28
K26
J21
J20
K21
J22

R2004

SC2D2U6D3V3KX-GP

1

VDDIO_33_GBE_S

PCI EXPRESS

510mA

SCD1U10V2KX-5GP

L2005
BLM15AG221SS1D-GP
2

C

1

VDDIO_18_FC
VDDIO_18_FC
VDDIO_18_FC
VDDIO_18_FC

N13
R15
N17
U13
U17
V12
V18
W12
W18

SC1U6D3V2KX-GP

FLASH I/O
AF22
AE25
AF24
AC22

3D3V_S0

1D1V_S0

CLKGEN I/O
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK

PCI/GPIO I/O

71mA

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

33 ohm 3A

CORE S0

VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11

VDDRF_GBE_S

X01

SC1U6D3V2KX-GP

68.00206.141

VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP

SC10U6D3V5KX-1GP

DY

1D1V_VDDCR_S0
POWER

SC1U6D3V2KX-GP

AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19

HUDSON-1

SC1U6D3V2KX-GP

1D1V_PCIE_S0

131mA
R2030
0R0402-PAD-2-GP

L2004
PBY160808T-330Y-N-GP
2

1

3 OF 5

FCH1C

DY

VDDPL_3.3V_PCIE
SCD1U10V2KX-5GP

SC2D2U6D3V3KX-GP

1D1V_S0

SCD1U10V2KX-5GP

L2002
BLM15AG221SS1D-GP
1
2

DY

SCD1U10V2KX-5GP

DY

SCD1U10V2KX-5GP

DY

SCD1U10V2KX-5GP

SC4D7U6D3V5KX-3GP

3D3V_S0

68.00084.E21

1

VDDIO_18_FC

2

R2003
0R2J-2-GP

220 ohm 300mA

SCD1U10V2KX-5GP

DY

SCD1U10V2KX-5GP

1

D

SC4D7U6D3V5KX-3GP

1D8V_S0

A00

2

2 0R0402-PAD

C2002

R2002 1

2

SSID = FCH

3

3D3V_FCH_VDDIO_S0

Del reservaton 1D5V_S5

C2056
SC2D2U6D3V3KX-GP

2

HW Montior Not implemented
or HW Montior balls not used GPIO
=> Decoupled cap not used

If support USB 3.0 or LAN wake-up, tie to 1.1V_S5
otherwise, tie to 1.1V_S0

HW Montior Not implemented
or HW Montior balls used as GPIO
=> Bead not used

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

HUDSON-M1 Power(4/6)
Size
A2

5

4

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3

Date:
2

Document Number

Rev

Enrico 14 AMD
Friday, April 22, 2011

A00
Sheet

1

20

of

109

5

4

3

2

1

SSID = FCH
REQUIRED STRAPS
REQUIRED SYSTEM STRAPS

D

3D3V_S5

R2107

3D3V_S0

D

CLK_PCI_LPC

PCI_CLK4

LPC_CLK0

LPC_CLK1

ENABLE EC

CLKGEN
ENABLED

LPC_CLK2

1

PCI_CLK1

2

R2106
2

USE
DEBUG
STRAPS

non_Fusion
CLOCK mode

(Use Internal)

DEFAULT

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

Allow
PCIE GEN2

LOW POWER
MODE

PULL
HIGH

1

1

1

1

1

AZ_SDOUT

DY

2
R2104
2
R2105
2
R2120
2
10KR2J-3-GP

18 HDA_SDOUT

10KR2J-3-GP

10KR2J-3-GP

DY

DY DY DY

10KR2J-3-GP

R2102
2

1

R2103

VDDIO_AZ

PERFORMANCE
MODE

PULL
LOW

DEFAULT

Force
PCIE GEN1

DEFAULT

Enable
boot timer
function

IGNORE
DEBUG
STRAPS

Fusion
CLOCK mode

DISABLE EC

DEFAULT

DEFAULT

DEFAULT

CLKGEN
DISABLED
(Use External)

Disable boot
fail timer
function
DEFAULT

17 PCI_CLK1
17,71 CLK_PCI_LPC
17 PCI_CLK4
17 PCI_CLK2
C

TYPE
ENABLED

17,27 LPC_CLK0
17 LPC_CLK1
18 EC_PW M3

C

Reserved

2.2-kohm 5% pull-down

2.2-kohm 5% pull-down

LPC ROM

Not connected.

2.2-kohm 5% pull-down

SPI ROM

2.2-kohm 5% pull-down

Not connected.

Reserved

Not connected.

Not connected.

2

DY
2

2K2R2F-GP

2K2R2F-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

EC_PWM3

1
R2119

1

1
R2113
2

R2114

1
R2112
2

R2111 1

R2121 1

DY

2

2

1

R2110 1

R2109
2

DY

2

1

18 EC_PW M2

R2108
2

0816

EC_PWM2

Note: EC_PWM2, EC_PWM3 default have internal 10kohm PU.
B

B

DEBUG STRAPS

PULL
LOW

2

2

2

2

2

2K2R2J-2-GP

2K2R2J-2-GP

2K2R2J-2-GP

2K2R2J-2-GP

2K2R2J-2-GP

DYDYDYDYDY
A

17
17
17
17
17

PULL
HIGH

1 R2118

1 R2117

1 R2116

1 R2101

1 R2115

PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23

PCI_AD27 PCI_AD26

PCI_AD25

PCI_AD24

USE PCI
PLL

Disable ILA
AUTORUN

USE FC
PLL

USE DEFAULT
PCIE STRAPS Disable PCI
MEM BOOT

PCI_AD23

(DEFAULT)

(DEFAULT)

(DEFAULT)

(DEFAULT)

(DEFAULT)

BYPASS
PCI PLL

Enable ILA
AUTORUN

BYPASS FC
PLL

USE EEPROM
PCIE STRAPS

Enable PCI
MEM BOOT


Wistron Corporation

Note: FCH has 15K internal PU FOR PCI_AD[27:23]

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

5

4

www.bblianmeng.com
3

A

Date:
2

HUDSON_STRAPPING_(5/6)
Document Number

Rev

Enrico 14 AMD
Friday, April 22, 2011

A00
Sheet
1

21

of

109

5

4

3

2

1

SSID = FCH
5 OF 5

FCH1E
HUDSON-1

D

C

B

Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16

VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA

A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19

VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB

Y4

EFUSE

D8

VSSAN_HWM

M19

VSSXL

P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23

VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK

GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSPL_SYS

VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK

AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8

D

C

M20
H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20

B

HUDSON-M1-1-GP


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Reserved

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet
1

22

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

23

A00
of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

24

A00
of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

25

A00
of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

26

A00
of

109

5

4

3

2

SSID = KBC

1

3D3V_AUX_KBC

X01

MODEL_ID_DET(GPIO07)

3D3V_AUX_KBC

PCB VERSION A/D(PIN98)

PULL-LOW RESISTOR

SA

100.0K

10.0K

3.0V

SB

100.0K

20.0K

2.75V

SC

100.0K

33.0K

2.48V

Reserved

100.0K

100.0K

1.65V

1

C2718
SCD1U10V2KX-5GP

44

4
VDD

PLT_RST#_EC
2
1 R2735
A_RST#
0R0402-PAD
LPC_CLK0 17,21
LPC_FRAME# 17,71
LPC_AD3
LPC_AD3 17,71
LPC_AD2
LPC_AD2 17,71
LPC_AD1
LPC_AD1 17,71
LPC_AD0
LPC_AD0 17,71
INT_SERIRQ 17
PM_CLKRUN# 17
L_BKLT_EN 6
ECSCI#_KBC

7
2
3
1
128
127
126
125
8
9
29
124
123
121
122

EC_GPIO10
ECSWI#_KBC

17,36

32
118
62
65
81
66
22
16

68 CHG_AMBER_LED#
29 KBC_BEEP

0810 Add
TP2701

1

31
117
63
64

28 FAN_TACH1
18 PM_PWRBTN#
18,31 PCIE_WAKE#
18,36,44,46,47 PM_SLP_S3#

40 AD_IA_HW

TPAD14

X01

H_A20GATE 18
H_RCIN# 18

68 WLAN_LED#
68 PWRLED#
ECRST#

GPIO52/PSDAT3/RDY#
GPIO50/PSCLK3/TDO
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1
GPIO17/SCL1
GPIO22/SDA1
GPIO73/SCL2
GPIO74/SDA2
GPIO23/SCL3
GPIO31/SDA3
GPIO47/SCL4
GPIO53/SDA4

F_CS0#
F_SCK
F_SDI/F_SDIO1
F_SDIO/F_SDIO0

27
25
11
10
71
72

BLON_OUT 49
AD_IA_HW2 40

70
69
67
68
119
120
24
28

BAT_SCL 39,40
BAT_SDA 39,40
SML1_CLK 6,85
SML1_DATA 6,85
PM_LAN_ENABLE 31

KB_DET#
TPDATA
TPCLK

EC_ENABLE#_1
PROCHOT_EC

85

X01
PCH_WAKE# 18

69
69
69

113
111

65 E51_RxD
65 E51_TxD

<------ TP

30
77

29 AMP_MUTE#
17 PCH_SUSCLK_KBC

<------ BATTERY / CHARGER
<------ CPU -Temp / eDP(Reserved)

13
12

EC_SPI_CS#_R
EC_SPI_CLK_R
EC_SPI_DI_R
EC_SPI_DO_R

90
92
86
87

2
2
2
2

R2736
R2719
R2737
R2722

EC_SPI_CS#
EC_SPI_CLK
EC_SPI_DI
EC_SPI_DO

60
60
60
60

L_BKLT_EN

0R0402-PAD

2
PROCHOT_EC

R2782

2

ECSCI#_KBC

3
H_PROCHOT#_EC

R2733
2
1
0R0402-PAD

H_PROCHOT#

G

X01
DY

5

18 EC_SMI#

1

DY
ECSMI#_KBC

3
2
BAS16-6-GP

B

2
1

1
2

X01

3D3V_AUX_KBC

2

10mW

DY

1
2

R27131

2 10KR2J-3-GP

3D3V_S0

PSL_IN1
0R2J-2-GP

FAN_TACH1

1

E51_RxD

1 R2708

2 10KR2J-3-GP
DY

BLUETOOTH_EN

1 R2709

2 10KR2J-3-GP

2
10KR2J-3-GP

PSL_IN1

0702 Modify:
Rename EC_GPIO70 to PSL_IN1

G

3D3V_AUX_KBC

X01
2N7002K-2-GP

1 R2767
DY

2

KBC_ON#_R
0R2J-2-GP

EC_ENABLE#_1

Q2705
D

S5_ENABLE

PSL_OUT

A

PSL_OUT
D

DY

4
3

0804 Add short pad separate

G
20100906 X01 Modify:
Add C2722 0.1uF between Q2703 G&S pin for
fixed leakage voltage to 3D3V_AUX_KBC under
DC mode.
20100917 X01:
Add Q2706 2N7002 to avoid leakage loop from
3D3V_S5 to 3D3V_AUX_KBC issue when 10mW
latched fail timing. Un-stuff C2713 to follow the standard schematics.

AC_IN#_KBC 1 R2763

AC_OK 2 R2768 1 PSL_IN1
0R0402-PAD

Q2704

AC_IN#_KBC

R2783

2
D2705

84.02130.031

1
BAT54CPT-GP

1

R2712

D

1
40

0R0402-PAD

SRN10KJ-5-GP

RTC_POWER
0R2J-2-GP

2

10mW

2

AC_IN#

C2713
SCD1U10V2KX-5GP

R2775
1
2
0R0402-PAD

PSL

2ND = 84.03413.A31

D

10mW

3

40 PWR_CHG_ACOK
Q2703
DMP2130L-7-GP

G

2

1 R2734

2
S

KBC_ON#_GATE

RTC_POWER

PSL

SCD1U10V2KX-5GP

SRN10KJ-5-GP

D2703

2

VBACKUP

3D3V_AUX_KBC

3D3V_AUX_S5

X01

C2722
1

KBC_ON#_R

1

SRN100KJ-6-GP

S5_ENABLE
EC_ENABLE#_1

10mW SOLUTION

3D3V_AUX_S5
R2756
2
1
0R0402-PAD

3D3V_AUX_S5

1
2

69

SRN4K7J-8-GP

0630 Modify:
Removed LID_CLOSE#
PH 10K on RN2705.

PSL SOLUTION

RTC_POWER
330KR2J-L1-GP

4
3

KROW[0..7]

KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

KBC_ON#


10mW

S

2N7002K-2-GP

G

84.2N702.J31

2nd = 84.07002.I31

Wistron Corporation
PSL_IN1

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

1

2

<------AMD Dont Have BL Keyboard

54
55
56
57
58
59
60
61

RN2705

RN2706

2ND = 83.00054.Q81
83.R2003.E81

4
3

2nd = 84.07002.I31

KBC_ON#

A

BAT_IN#
AC_IN#_KBC

6,40

D

S
S

Q2706

84.2N702.J31

PSL

KBC_ON#
0702 Modify:
Rename EC_GPIO71 to PSL_OUT

1 R2766

2

10mW

KBC_ON#_R
0R2J-2-GP

2N7002K-2-GP

2ND = 84.2N702.031

DY

R2769
100KR2J-1-GP

Title

2

1

69

RN2703

2

D2702

3
4

S

100KR2J-1-GP

2

DY

D

BAT_SCL
BAT_SDA

ECRST#

10mW 2ND = 83.00054.Q81

D

3D3V_AUX_KBC

84.2N702.J31

X01

83.R2003.E81

3

Reserved

1.048V

EC GPIO standard PH/PL

2N7002K-2-GP

R2704

1
68 KBC_PWRBTN#

1.204V

215.0K

KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16

DY

C2715
PMBS3906-GP
Q2701

2 0R0402-PAD

DY

83.00016.K11
2ND = 83.00016.F11

1 0R0402-PAD

1.358V

174.0K

100.0K

83.00016.K11
2ND = 83.00016.F11

G

R2732

PSL
BAT54CPT-GP

143.0K

100.0K

RN2701

3

2 R2778

100.0K

Reserved

X02

1

Q2702

BAS16-6-GP
PSL_IN2

Reserved

3D3V_AUX_KBC

PURE_HW_SHUTDOWN#

2

X01

1.65V

100KR2J-1-GP

2
R2780 1

D2704
1

100.0K

2.24V

R2770

High Active

ECSWI#_KBC

DY
18 EC_SCI#

Reserved

100.0K

KB_DET#

BAS16-6-GP

1

1.87V

ECRST#
R2705
10KR2J-3-GP

1

2
100KR2J-1-GP

2.0V

Reserved

76.8K

3D3V_AUX_KBC

2

X01EC_GPIO47

DY

83.00016.K11
2ND = 83.00016.F11

R2774

64.9K

100.0K

R2781

2

3
2

100.0K

KCOL[0..16]
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

NOTE:
Connect GND and AGND planes via either
0R resistor or one point layout connection.

EC_AGND

B

Reserved

X01

33R2J-2-GP
33R2J-2-GP
0R0402-PAD
33R2J-2-GP

1
1
1
1

NOTE:
Locate resistors R2719 and R2722 close
to the NPCE791L.

D2701

1

1

KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
GPIO15/A_PWM
KBSOUT5/TDO
GPIO21/B_PWM
KBSOUT6/RDY#
GPIO13/C_PWM
KBSOUT7
GPIO32/D_PWM
KBSOUT8
GPIO66/G_PWM
KBSOUT9/SDP_VIS#
GPIO33/H_PWM
KBSOUT10/P80_CLK
GPIO45/E_PWM
KBSOUT11/P80_DAT
GPIO40/F_PWM
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
VCC_POR#
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
GPIO87/CIRRXM/SIN_CR
GPIO83/SOUT_CR/TRIST#
KBSIN0
KBSIN1
GPIO55/CLKOUT/IOX_DIN_DIO
KBSIN2
GPIO00/EXTCLK
KBSIN3
KBSIN4
KBSIN5
PECI
KBSIN6
VTT
KBSIN7

103

X02

1

47.0K

2 OF 2

GPIO56/TA1
GPIO20/TA2
GPIO14/TB1
GPIO01/TB2

2 R2711 1
0R0402-PAD

18 EC_SWI#

100.0K

C

R2773
100KR2J-1-GP

EC_AGND

EC_AGND

0729 Add from page94 to here

2.48V

Reserved

NPCE795PA0DX-GP-U

28,36,85

1

33.0K

LCD_TST_EN 49

1

NPCE795PA0DX-GP-U

0R0402-PAD

2.75V

DV15_UMA

100.0K

2SC220P50V2KX-3GP

DY

VCORF

C2712
SC1U10V3ZY-6GP

3.0V

Reserved

20.0K

2

2

2

R2739
100KR2F-L1-GP

U2701B

GND
GND
GND
GND
GND
GND

CPU_THRM

SCD1U10V2KX-5GP
C2721
1 DY 2

GPIO2
GPIO3/AD6
GPIO4/AD5
GPIO5/AD4
PSL_IN2#_GPIO6
GPIO7/AD7
GPIO16
GPIO24
GPIO30
GPIO34/CIRRXL
GPIO36
GPIO41
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO46/CIRRXM/TRST#
GPIO51
PSL_IN1_GPIO70
PSL_OUT_GPIO71
VBKUP
GPIO75
GPO76/SHBM
GPIO77
GPIO81
GPO82/IOX_LDSH/TEST#
GPIO84/IOX_SCLK/XORTR#
GPIO97

18
45
78
89
116
5

SCD1U10V2KX-5GP
C2720
1 DY 2

2

C2719
1 DYSCD1U10V2KX-5GP
2

1.87V

SC1U6D3V2KX-GP

VCORF

SYS_THRM

C2703
SC2D2U10V3KX-1GP

AGND

2

36 IMVP_PWRGD

VGA_THRM

76.8

VOLTAGE

10.0K

1

PSL_IN1
PSL_OUT
VBKUP
1 0R0402-PAD

10 nF-0.1uF close to pin

100.0K

PULL-HIGH RESISTOR

100.0K
100.0K

2

ECSMI#_KBC

61 USB_PWR_EN#

0817 Vendorrecommand Add

Reserved

1

2
1

SERIES_ID

0817

R2726
100KR2F-L1-GP

MODEL_ID_DET
2

1
GPIO94/DA0
GPIO95/DA1
GPIO96/DA2

79
95
96
108
93
94
114
6
109
14
15
80
17
20
21
23
26
73
74
75
82
83
84
91
110
112
107

PSL_IN2
MODEL_ID_DET

2 R2772
RTC_AUX_S5
65 WIFI_RF_EN
65 BLUETOOTH_EN
36,46 1D1V_S5_PWRGD

2.0V

1

1

SERIES_ID

R2728

C

2

1
101
105
106

Inspiron
100KR2J-1-GP

69 CAP_LED#
36 S5_ENABLE
X01 85 PCIE_RST#
39 BAT_IN#
70,82 LID_CLOSE#
18 RSMRST#_KBC
18,44 PM_SLP_S5#
60 EC_SPI_WP#
38 RCID

0817

C2711 1

1 OF 2

LRESET#
LCLK
LFRAME#
LAD3
LAD2
LAD1
LAD0
SERIRQ
GPIO11/CLKRUN#
GPIO65/SMI#
ECSCI#/GPIO54
GPIO10/LPCPD#
GPIO67/PWUREQ#
GPIO85/GA20
KBRST#/GPIO86

GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3

0816

R2727
Vostro 100KR2J-1-GP

2.24V

64.9K

PULL-LOW RESISTOR

DV14_DIS

EC_AGND

102

VREF

97
98
99
100

28 FAN1_DAC
49 LCD_TST

68 BATT_WHITE_LED#

19
46
76
88
115
VCC
VCC
VCC
VCC
VCC

1

C2710
SCD1U10V2KX-5GP
2
1

104

SCD1U10V2KX-5GP

28 VGA_THRM
28 SYS_THRM

47.0K

100.0K

EC_AGND
U2701A

38 PSID_EC
28 CPU_THRM
3D3V_AUX_KBC

100.0K

EC_AGND

PCB_VER_AD

0816

C2702
SCD1U10V2KX-5GP

3D3V_AUX_KBC_VCC

AD_IA

DY 2

A00
Reserved

PCB_VER_AD

AVCC

40
C2714 1

EC_AGND

2

1
2

C2707
SCD1U10V2KX-5GP

1
2

C2706
SCD1U10V2KX-5GP

1

C2705

2

1
2

C2704
SCD1U10V2KX-5GP

1
2

C2701
SC2D2U10V3KX-1GP

DY

SCD1U10V2KX-5GP

1

D

C2708
SCD1U10V2KX-5GP
C2709
SC2D2U10V3KX-1GP
2
1

VBAT

R2771
2D2R3-1-U-GP

MODELID

1

0R0603-PAD
2

1

R2710
10KR2F-2-GP

2

3D3V_S0

2

R2702

VOLTAGE

1

1
R2724
47KR2F-GP
3D3V_AUX_KBC

PULL-HIGH RESISTOR

2

A00

84.2N702.J31
2nd = 84.07002.I31
4

www.bblianmeng.com
3

2

KBC Nuvoton NPCE795PA0DX Rev

Size
A2

Document Number

Date:

Friday, April 22, 2011

A00

Enrico 14 AMD
Sheet
1

27

of

109

5

4

3

2

SSID = Thermal

1

Fan controller P2793

X01
3D3V_AUX_KBC

0721 Pull-down: full speed, R2830 dummy.
5V_S0

1

2

1

1
2

AFTP2803
AFTE14P-GP

SCD1U10V2KX-5GP

1

D

C2818 C2832

2

1

1

1

FAN1

T8_P2800

VCC
DXP
DXN
OTZ

TDR
TDL
GND
ADJ

4
3
2
1

SYS_THRM 27
CPU_THRM 27

1

27 FAN_TACH1

R2829 2
0R0402-PAD

5
3
2

FAN_VCC

1
4

FAN_TACH1_C

*Layout* 15 mil

ADJ

FAN_VCC

1

5
6
7
8

1

2
3D3V_S0_thermal

X02
2
0R2J-2-GP

C

ADJ floating : OTZ shutdown temperature=85°C
ADJ pull-down : OTZ shutdown temperature=90°C
ADJ pull-up :
OTZ shutdown temperature=95°C

FOX-CON3-6-GP-U

DY

83.R5003.C8F

AFTP2801

1

D2802

DY CH551H-30PT-GP

C2816

DY
2

C2815

1

FAN_VCC

DY

5V_S0

74.02800.B71

2

SC4D7U6D3V3KX-GP

1

1

1

R2819

1.H/W T8 Shutdown

2

P2800EB0-GP

20.D0210.103

C2817
AFTE14P-GP
SC2200P50V2KX-2GP

C

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

3D3V_AUX_S5

3

3D3V_S0

1

0R0402-PAD

SCD1U16V2KX-3GP
2

C2828

1

X01

2

DY

AFTP2802
AFTE14P-GP

R2820
10KR2J-3-GP

U2801

2

C2829

2

2

3

1

1
R2802

2

X02

DY

P2800_DXN

R2823

X02

8
7
6
5

3D3V_S0

2.System Sensor, Put on palm rest
THERM_SYS_SHDN#1

GND
GND
GND
GND

C2831

X01
SC2200P50V2KX-2GP

1
PMBS3904-1-GP

FON#
VIN
VOUT
VSET

DYSCD1U10V2KX-5GP

2

2

2
SCD1U10V2KX-5GP

R2817
0R2J-2-GP

SC390P50V3JN-GP

NTC-100K-8-GP

Q2808

1
2
3
4

FAN_VCC

P2793AB0-GP

P2800_DXP

2ND = 84.03904.P11
84.03904.L06

2 R2830
DY 0R2J-2-GP

27 FAN1_DAC

ADJ

Layout notice :
Both DXN and DXP routing 10 mil
trace width and 10 mil spacing.

DY

1
5V_S0

2

C2827

SC10U6D3V5KX-1GP

C2830

D

U2802

R2816
107KR2F-GP

DY

SC4D7U6D3V3KX-GP

3D3V_S0_thermal

1

R2828 2
0R0402-PAD

1

1

3D3V_S0

R2831
100KR2J-1-GP
Q2805

D

27,36,85 PURE_HW _SHUTDOW N#

1

DY

DY

2 0R0402-PAD 3D3V_S0

2N7002K-2-GP

84.2N702.J31
2nd = 84.07002.I31

2

R2818
10KR2J-3-GP

C2811
SCD1U10V2KX-5GP

2

VGA Thermal sensor P2800

R2810 1

G

1

X02

THERM_SYS_SHDN#

S

2

1

3rd = 83.BAT54.S81

DY

2

D2801
BAT54PT-GP

83.00054.T81
2ND = 83.BAT54.D81

X02

1R2813

DY

2

DY 470KR2J-2-GP

R2815
100KR2J-1-GP

DY

P2800EB0-GP

U2805

0809 Vendor review and pop

ADJ_G709
THERM_SYS_SHDN# 1 DY
2T8_G709
R2811
0R2J-2-GP

86.9 ℃

SET
GND
OUT#

VCC

5

HYST

4

DY

2

DY

1
2
3

DY

C2808

G709T1UF-GP

DY

R2861

SCD1U10V2KX-5GP DY

DY 0R2J-2-GP
1

C2814

SCD1U10V2KX-5GP

2

DY

SC10U6D3V5KX-1GP

C2813

74.02800.B71

1

3D3V_VGA_S0_thermal
20R2J-2-GP

2

DY

1

1

VGA_THRM 27

2

R2814
3D3V_S0

4
3
2
1

2

0806 Rename

TDR
TDL
GND
ADJ

R2812
24K3R2F-1-GP
2
1

85 P2800_VGA_DXN

DY

2

2
P2800_VGA_DXN

VCC
DXP
DXN
OTZ

R2832
0R2J-2-GP

3D3V_VGA_S0_thermal5
C2812
6
SC2200P50V2KX-2GP
7
8

DY

B

3D3V_S0

11/4 Vendor recommand

1

1

Layout notice :
Both DXN and DXP routing 10 mil
trace width and 10 mil spacing.

U2803

R2805
150R2F-1-GP
2
1

0806 Rename

1

P2800_VGA_DXP

85 P2800_VGA_DXP

1

B

R(KΩ)= 0.0012*T^2- 0.9308T+ 96.147


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

5

4

www.bblianmeng.com
3

Date:
2

Thermal/Fan
Controllor EMC2102
Document Number
Friday, April 22, 2011

Rev

A00

Enrico 14 AMD
Sheet

28
1

of

109

3

AUD_HP1_JACK_R
AUD_HP1_JACK_L
AUD_EXT_MIC_R
AUD_EXT_MIC_L

C2922
C2921

1 SC1U10V3KX-3GP
1 SC1U10V3KX-3GP

2
2

AUD_HP1_JACK_R2
AUD_HP1_JACK_L2
AUD_AGND
MIC_IN_R 82
MIC_IN_L 82

1

82
82

Put C2921 and C2922 close to codec
0707 Modify:
Change R2911,R2914,R2917 change
to 0ohm 0603 from short pad.

AUD_CAP2

R2911

0R0603-PAD
2

1

AUD_V_B
C

0R0603-PAD
2

AUD_AGND
SC1U10V3KX-3GP
C2924
2
1

2

AMP_MUTE#

1
C2907
SC4D7P50V2CN-1GP

DY
2

C2923
SC1U10V2KX-1GP

2

1

AUD_PC_BEEP

AUD_PC_BEEP
Trace width>15 mils

120KR2J-L-GP
R2909
1
2

C2912

2

1 SCD1U10V2KX-5GP SB_SPKR_R

C2913

2

1 SCD1U10V2KX-5GP KBC_BEEP_R 1
R2910

AUD_AGND

AUD_AGND

Close to codec
INT_MIC_L_R 58,82

AUD_AGND

MIC IN

AUD_VREFOUT_B
HDA_CODEC_BITCLK

AUD_AGND

1

1

2
R2917

2

0R0603-PAD
2

C2916
SC1U6D3V2KX-GP

1

1

R2914

INT_MIC_L_R

2

2K2R2J-2-GP

C2915
SC10U6D3V5MX-3GP

R2920

2

1

AUD_VREFOUT_B

0730 Add internal MIC

C2910
SC10U6D3V5MX-3GP

2

1

C2909
SC1U10V2KX-1GP

2

2
1
2 60D4R2F-GP
2 60D4R2F-GP

1
1

AUD_VREG

AUD_VREFFLT
AUD_CAP2
AUD_VREFOUT_B

AUD_PC_BEEP

R2906
R2905

AUD_VREFFLT

C

AUD_SENSE_A
AUD_SENSE_B

CLOSE TO CODEC

C2914
SC2D2U10V3KX-1GP

+AVDD

0809 Vendor recommand

R2908
10KR2J-3-GP

C2908
SCD1U10V2KX-5GP

2
2
PUMP_CAPN
AUD_V_B

1

2010/06/30 Change to 92HD87 (71.92H87.A03)

1

30
29
28
27
26
25
24
23
22
21

CAP+
CAPVAVSS2
PORTB_R
PORTB_L
AVSS2
PORTA_R
PORTA_L
AVDD1

C2918
SC10U6D3V5MX-3GP

92HD87B1A5NDGXTBX8-GP

3D3V_S0

C2905
SCD1U10V2KX-5GP

41
40
39
38
37
36
35
34
33
32
31

0707 Modify:
updated U2901 part number from data base.

0R0603-PAD
2

D

2

18 HDA_CODEC_SYNC
18 HDA_CODEC_RST#

DVDD_LV
DMIC_CLK/GPIO_1
DMIC_0/GPIO_2
SDATA_OUT
BITCLK
SDATA_IN
DVDD
71.92H87.A03
SYNC
RESET#
PCBEEP

1

2

C2902
SCD1U10V2KX-5GP

1

2
1

C2904
SCD1U10V2KX-5GP

1

C2903
SC1U6D3V2KX-GP

2

HDA_CODEC_SDOUT
HDA_CODEC_BITCLK
1R2901
2HDA_CODEC_SDIN0
33R2J-2-GP
HDA_CODEC_SYNC
HDA_CODEC_RST#
AUD_PC_BEEP

18 HDA_CODEC_SDOUT
18 HDA_CODEC_BITCLK
18 HDA_SDIN0

Close to codec

1

PUMP_CAPP

C2917
SC4D7U6D3V3KX-GP

3D3V_S0

1

AUD_VREG

1
2
3
4
5
6
7
8
9
10

R2904

1

AUD_AGND

SENSE_A
SENSE_B
PORTF_L
PORTF_R
PORTC_L
PORTC_R
VREFFILT
CAP2
VREFOUT_A
VREFOUT_C

0625 Modify:
AUD_DMIC_CLK&AUD_DMIC_IN0 connector
to LVDS pin define.

0R0603-PAD
2

1

0R0603-PAD
2

AUD_AGND

11
12
13
14
15
16
17
18
19
20

2

C2901
SC10U6D3V5MX-3GP

5V_S0
R2903

R2902

AUD_AGND

THERMAL_PAD
EAPD
PVDD
PORTD_+R
PORTD_-R
PVSS
PORTD_-L
PORTD_+L
PVDD
AVDD2
VREG/+2_5V

U2901

1

D

+PVDD

+AVDD

+AVDD

Close to codec
AUD_DVDDCORE

58
58
58
58

1

+PVDD

AMP_MUTE#

AUD_SPK_R+
AUD_SPK_RAUD_SPK_LAUD_SPK_L+

1

5V_S0

2

SSID = AUDIO
27 AMP_MUTE#

2

AUD_SPK_R+
AUD_SPK_RAUD_SPK_LAUD_SPK_L+

C2906
SC1U10V2KX-1GP

4

1

5

From SB
HDA_SPKR 18

2
470KR2J-2-GP

0719 Modify:
Move RN2901 to closed AUDIO CODEC from speaker connector.

KBC_BEEP 27

From EC

B

B

2
1

AUD_VREFOUT_B

3
4

RN2901
SRN4K7J-8-GP

Azalia I/F EMI
HDA_CODEC_SDOUT

82 MIC_IN_R

1

82 MIC_IN_L

+AVDD

+AVDD
R2913
R2916
2K49R2F-GP
AUD_SENSE_B

A

1
AUD_AGND

1

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

2

2

2
C2920
SCD1U10V2KX-5GP

Wistron Corporation

R2919
EXT_MIC_JD# 82

Title

39K2R2F-L-GP
AUD_AGND

Close to Pin13
5


R2918
20KR2F-L-GP

C2919
SC1000P50V3JN-GP-U

1
2

DY

82

1

AUD_SENSE_A

AUD_HP1_JD#

20KR2F-L-GP

2

R2915
2K49R2F-GP

2

2

1

PCH_AZ_CODEC_SDOUT1

A

1

1

2

DY

R2912
47R2J-2-GP

4

Close to Pin14

www.bblianmeng.com
3

2

Audio Codec 92HD87B1

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

A00

Enrico 14 AMD
Sheet
1

29

of

109

5

4

3

2

1

D

D

C

C

B

B

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

AMP

Rev

Enrico 14 AMD
Sheet
1

30

A00
of

109

A

B

C

D

X01

1

SSID = LOM

LAN CHIP

R3117
1

1

1

2

2
0R0603-PAD
2

C3119

2

2

59 LAN_MDI0P
59 LAN_MDI0N

DVDD10

59 LAN_MDI1P
59 LAN_MDI1N

DVDD10
DVDD10
3D3V_LAN_S5

1

3D3V_LAN_S5
GPO

DY2

2
1

AVDD33
AVDD33
RSET
AVDD10
CKXTAL2
CKXTAL1
AVDD33
NC#41
LED0
DVDD3
GPO
LED1/EESK

R3105
0R0402-PAD

1
REGOUT
VDDREG
VDDREG
ENSWREG
EEDI
LED3/EEDO
EECS
DVDD10
LANWAKE#
DVDD33
ISOLATE#
PERST#

36
35
34
33
32
31
30
29
28
27
26
25

LANOUP_1.05S
AVDD33_REG
AVDD33_REG
ENSW REG
EEDI/SDA

R3106
0R2J-2-GP
2

DY
3

R3107 1
DVDD10

2 10KR2J-3-GP
3D3V_S0

PCIE_W AKE# 18,27

3D3V_LAN_S5
ISOLATE#
PLT_RST#_LAN

2

1
R3110
1KR2J-1-GP

R3109

X02

15KR2F-GP

RTL8105E-VC-GRT-GP

13
14
15
16
17
18
19
20
21
22
23
24

2

X5R

MDIP0
MDIN0
AVDD10
MDIP1
MDIN1
NC#6
NC#7
NC#8
NC#9
NC#10
NC#11
NC#12

C3111
SCD1U16V2ZY-2GP

SC4D7U6D3V3KX-GP

1

C3101

TPAD14-GP

1

TP3101

DVDD10

X01

0720

CLK_LAN_REQ#_R
PCIE_TXP0
PCIE_TXN0
CLK_PCIE_LAN
CLK_PCIE_LAN#

2

3D3V_LAN_S5
PCIE_W AKE#

10KR2J-3-GP2

EVDD10

DY

2

0R3J-0-U-GP
3D3V_S5

PA102FMG-GP-U
Q3103

2

1

4
3
2

17,65,71,83 PLT_RST#

S
1

2N7002K-2-GP

A

3D3V_LAN_S5

X01
RTL8111E-Stuff
RTL8105E-DY

R3103 1

1

LAN_ENABLE_R_C

RN3101
SRN10KJ-5-GP

Q3104
PMBS3904-1-GP

D

R3134
100KR2J-1-GP

2
R3108

B

3

C3105
PCIE_RXP0_C 1
PCIE_RXN0_C 1
C3104
PCIE_TXP0
PCIE_TXN0

C3128

2

1

G
2

2

2
2

X02

2PM_LAN_ENABLE_R

1KR2J-1-GP

C3129

SCD1U10V2KX-4GP

Q3102

G

27 PM_LAN_ENABLE

C3125

LANXIN

C3103 1

2 SC18P50V2JN-1-GP

3D3V_LAN_S5

SC1U10V2KX-1GP

1 R3118

1

D

SCD1U10V2KX-4GP

C3130
SCD1U10V2KX-4GP

X02

2 SC18P50V2JN-1-GP

X02

1

1

1

S
R3121
10KR2J-3-GP

main: 84.00102.031
2nd: 84.03403.031

C3102 1

X3101
XTAL-25MHZ-155-GP

1
2

1

2

1 R3122

X02
LANXOUT

2

R3120

DY

X01

C3131

4

2
0R3J-0-U-GP

1

SCD1U10V2KX-4GP

DY

1

PCIE_RXP0_C
PCIE_RXN0_C

2

3D3V_LAN_S5

R3119

1

3D3V_S0

18

0R2J-2-GP

DVDD10
NC#14
NC#15
CLKREQ#
HSIP
HSIN
REFCLK_P
REFCLK_N
EVDD10
HSOP
HSON
GND

0R0603-PAD
2

1

GND

1
2
3
4
5
6
7
8
9
10
11
12

AVDD33_REG

2

2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

R3104

1

1

C3121

PCIE_CLK_LAN_RQ1#

2

1

1

1

C3118

3
R3133

For Switch Regulator enable
3D3V_LAN_S5

49

3D3V_LAN_S5

3

4

84.03904.L06
2ND = 84.03904.P11

2

R3113
2K49R2F-GP
1
2

U3101

40 mils

DVDD10
LANXOUT
LANXIN
3D3V_LAN_S5
DVDD10

2

3D3V_LAN_S5
3D3V_LAN_S5

X5R

Q3101
PMBS3904-1-GP

DY
CLK_LAN_REQ#_R

48
47
46
45
44
43
42
41
40
39
38
37

1

1

C3117

2

C3114

2

C3109

SCD1U16V2ZY-2GP

1

DVDD10

C3113

SCD1U16V2ZY-2GP

2

DVDD10

SCD1U16V2ZY-2GP

2

DY

SCD1U16V2ZY-2GP

SC4D7U6D3V3KX-GP

SCD1U16V2ZY-2GP

0721

C3120

1

2CTRL10A_R
IND-4D7UH-192-GP

1

LANOUP_1.05S 1

R3115
1
C3115

1

L3101

R3101
10KR2J-3-GP

C3106
SC1U10V3ZY-6GP

2

60

DY

0R0603-PAD
2

11/18 change L3101 to slime type
mils X01

R3102
10KR2J-3-GP

3D3V_LAN_S5

1CLK_LAN_REQ#_EN 2

EVDD10

4

E

3D3V_S0

3

DY

PLT_RST#_LAN

1
0R2J-2-GP

www.bblianmeng.com
C

DY

SCD1U10V2KX-5GP
2
2
SCD1U10V2KX-5GP

PCIE_RXP0 17
PCIE_RXN0 17
PCIE_TXP0 17
PCIE_TXN0 17
CLK_PCIE_LAN 17
CLK_PCIE_LAN# 17



2 1KR2J-1-GP

1

Wistron Corporation

GPO

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

R3114

1

2

EEDI/SDA

Title

10KR2J-3-GP

D

Size
A3

Document Number

Date:

Friday, April 22, 2011

LOM

Rev

Enrico 14 AMD
Sheet
E

31

A00
of

109

5

4

3

2

1

SSID = SDIO

XD_D7

TP3204

1

TPAD14-GP

D

D

17 CLK_PCH_48M

XD_D6/MS_BS

XD_D6/MS_BS 74

XD_D5/SD_D2/MS_D5

XD_D5/SD_D2/MS_D5

XD_D4/SD_D3/MS_D1
XD_D3/SD_D4/MS_D4

0809 Vendor recommand
C3209
1

2

XD_D4/SD_D3/MS_D1
TP3205

1

74
74

TPAD14-GP

RREF

3D3V_S0

3D3V_CARD_S0

SCD1U10V2KX-5GP
C3203
2
1

V18

250mA

2

RREF
DM
DP
3V3_IN
CARD_3V3
V18
GND

SP10
GPIO0
SP9
SP8
SP7
SP6

18
17
16
15
14
13

XD_D2/SD_CMD
CR_GPIO0
1
XD_D1/SD_D5/MS_D0
XD_D0/SD_CLK/MS_D2
XD_W P/SD_D6/MS_D6 1
XD_W E#/SD_CD#

XD_D2/SD_CMD 74
TP3201
TPAD14-GP
XD_D1/SD_D5/MS_D0 74
XD_D0/SD_CLK/MS_D2 74
TP3206
TPAD14-GP
XD_W E#/SD_CD# 74

RTS5138-GR-GP

7
8
9
10
11
12

1

25
C3208
SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP
C3204
2
1

0809 Vendor recommand

C

1
2
3
4
5
6

USB_PN9_R
USB_PP9_R

43mA

CLK_IN
XD_D7
SP14
SP13
SP12
SP11

U3201

XD_CD#
SP1
SP2
SP3
SP4
SP5

R3201
1
2
6K2R2F-GP

24
23
22
21
20
19

SC100P50V2JN-3GP

C

71.05138.003

Close to chip
XD_ALE/SD_D7/MS_D3 74

XD_CLE/SD_D0/MS_D7

XD_CLE/SD_D0/MS_D7

XD_CE#/SD_D1

XD_CE#/SD_D1 74

XD_RE#/MS_INS#

XD_RE#/MS_INS# 74

XD_RDY/SD_W P/MS_CLK_R

1
C3206
SCD1U10V2KX-4GP

XD_ALE/SD_D7/MS_D3

C3207
SC4D7U6D3V3KX-GP

XD_CD#

1

74

2
TP3203

TPAD14-GP

R3208
1

XD_RDY/SD_W P/MS_CLK

74

22R2J-2-GP

2

2

1

3D3V_CARD_S0

0809 Vendor recommand

B

B

A00
USB_PN9_R R3206 1

2 0R0603-PAD

USB_PN9 18

USB_PP9_R R3207 1

2 0R0603-PAD

USB_PP9 18

1

CLK_PCH_48M

2

DY

EC3201
SC10P50V2JN-4GP

X01 EMI 12/13



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

32

A00
of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

33

A00
of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

34

A00
of

109

A

B

C

D

E

4

4

3

3

(Blanking)

2

2



1

1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

A

B

www.bblianmeng.com
C

D

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
E

A00
35

of

109

5

4

3

2

1

0816

ROSA Run Power

Power Sequence

3D3V_S5
D

2

10KR2J-3-GP
R3627

1

D

X01

R3674
1
DY 2
0R2J-2-GP

46 1V_S0_PWRGD

D3605
47 1D8V_S0_PWRGD

1 R3629

2 0R0402-PAD 2

1 R3634

2 0R0402-PAD 1

3VCORE_EN_R
18,27,44,46,47

1

+5V_RUN
5V_S0

2nd = 84.08882.037

2

42

3D3V_S5

D
D
D
D

1

1

X01

5V_RUN_ENABLE
R3605 1
0R0402-PAD
C3608

2

1

VCORE_EN

C3633
SCD015U25V2KX-GP

0816
4
3
2
1

U3601
2

DY

83.00056.Q11

AO4468-GP

3D3V_AUX_S5

2 0R0402-PAD

2ND = 83.00056.G11
3RD = 83.00056.K11

+5V_RUN Comsumption
Peak current 7.73A

84.04468.037

5
6
7
8

1 R3628

BAW56-5-GP

2

AO4468 MAX 11.6A
Rds(on) = 11~14mOhm
VGS=+/-20V

5V_S5

R3604
33KR2F-GP

S
S
S
G

X01

PM_SLP_S3#

1

15V_S5

R3624
10KR2J-3-GP

C3603
SC10U10V5ZY-1GP

2

2

DYSC6800P25V2KX-1GP

PS_S3CNTRL
2
100KR2J-1-GP

C

3D3V_S5

Q3602
2N7002KDW-GP

3D3V_S0

3

2

1

D3603

AO4468-GP
5
6
7
8

X01
PM_SLP_S3#
R3607

18,27,44,46,47

4
3
2
1

2

PM_SLP_S3#

X01

3
1 R3626

42 VRM_VDD_PWRGD

2 0R0402-PAD
1

U3602

BAW56-5-GP

23.3V_RUN_ENABLE
10KR2J-3-GP

X01
2

1
2

83.00056.Q11

1

1

RUN_ENABLE

+3.3V_RUN Comsumption
Peak current 8.14A

84.04468.037

S G D

18,27,44,46,47

+3.3V_RUN

2nd = 84.08882.037

D
D
D
D

84.2N702.A3F
2nd = 84.DM601.03F

AO4468 MAX 11.6A
Rds(on) = 11~14mOhm
VGS=+/-20V

4

5

6

D G S

S
S
S
G

1 R3606

C

C3604
SC10U6D3V5KX-1GP

2ND = 83.00056.G11
3RD = 83.00056.K11

C3605
SCD015U25V2KX-GP

2

44 1D5V_S3_PWRGD

1

RUNPWROK_D

3

1D1V_S5

1

27

1

R3625 2

0R0402-PAD

FCH_PWRGD

18

83.00056.Q11
2ND = 83.00056.G11
3RD = 83.00056.K11

1
2
3
4

AO4468-GP
21.1V_RUN_ENABLE

84.04468.037

2nd = 84.08882.037

33KR2F-GP

IMVP_PWRGD

1

R3633

0R0402-PAD

B

C3614
SC10U6D3V5KX-1GP

2

C3615
SCD033U25V2KX-GP

2

+1.5V_RUN for Mini-Card Comsumption
Peak current 1A

1

B

U3611
S
S
S
G

8 D
7 D
6 D
5 D

X01

R3673 2

BAW56-5-GP

1D1V_S0

1.5V_RUN for VGA Comsumption
Peak current 7.39A
+1.5V_RUN_CPU Comsumption
Peak current 3A

1

D3604
27,46 1D1V_S5_PWRGD

H_THERMTRIP#

6,18

2

X01

1D5V_S0

6,17,42,71

G

84.03404.B31
X01
2nd = 84.03400.B37
AO4468 MAX 11.6A
DY
Rds(on) = 28~42mOhm
VGS=+/-20V

1

PMBS3904-1-GP

DYQ3601

DY

2

DY1KR2J-1-GP

BAS16-6-GP
2

1

21.5V_RUN_ENABLE
10KR2J-3-GP

X01
DY

2

3
C3609
SC10U6D3V5KX-1GP

1

41 3V_5V_EN
1

2

C3610
SCD01U50V2KX-1GP

1
R3622

17,27 A_RST#

S

1

1 R3630

H_PWRGD_R

2
DY R3601
1KR2J-1-GP

X01

U3606
AO3404A-GP
D

1

H_CPUPWRGD

Total= 500mA

3

X01

C3602
SCD1U10V2KX-5GP
2
1

+1.5V_RUN
1D5V_S3

PURE_HW_SHUTDOWN#

27,28,85

83.00016.K11
2ND = 83.00016.F11
1 R3603

2

S5_ENABLE 27

1KR2J-1-GP

2

DY R3602
200KR2J-L1-GP

D3601

DIS uses 84.08039.037 TPCA8039-H Peak current=34A
UMA uses 84.07686.037 SI7686DP Peak current=35A
X01
A

A

1D1V_S0

5

1V_PWR
R3671 1

2 0R0805-PAD

R3666 1

2 0R0805-PAD

R3667 1

2 0R0805-PAD

R3668 1

2 0R0805-PAD

R3669 1

2 0R0805-PAD

R3670 1

2 0R0805-PAD

4



Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

www.bblianmeng.com
3

2

Power On Logic

Size
A2

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD
Sheet
1

A00
36

of

109

5

4

3

2

1

D

D

C

C

B

B



Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

www.bblianmeng.com

Power Plane Enable

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet

37

of

109

A

5

4

3

2

1

SSID = PWR.Support

DCin CONN
D

0721 Remove PSID schematic

D

2

5V_S5

1

PR3802
15KR2J-1-GP

3

2

3D3V_S5

PSID_DISABLE#_R_C

BAV99-8-GP
1

PR3801
1
2
0R0603-PAD

2

PQ3801
FDV301N-NL-GP

PR3807
PS_ID_R2

D

PS_ID_R

PR3806
2K2R2J-2-GP

PD3803

G

1

3

2

1

2
1
2
PR3811
100KR2J-1-GP

3D3V_S5

PR3803
10KR2J-3-GP
PMBS3904-1-GP
PQ3802

1

D

PS_ID

S

1

2

PSID_EC 27

33R2J-2-GP
1

PQ3803
27

C

G

RCID

2

D
C

DY

S

1

2

33R2J-2-GP

PR3812
100KR2J-1-GP

.

DY

2

PR3808
1

.
.
. .

PD3804
B240A-13-GP

DY

DY
2N7002E-1-GP

84.2N702.D31

This cap should be used
only as last resort for
EMI suppression.

+DC_IN

AD+

B

1
2

PC3806
SC10U25V5KX-GP

PC3804
SCD01U50V2KX-1GP

1

DY
2

1
2

DY

X01

2

B

PR3810
47KR3J-L-GP

R1

DY

AD_OFF_L

B

C

R1

C
B

AD_OFF_R

1

R2

E

DY

PQ3804
40 PW R_CHG_AD_OFF

20.F1498.007

1
1
1

1

1

Id= -10A
Qg= -22nC
Rdson=14~13mohm

PQ3805

AFTP3812
AFTP3813
AFTP3814

8
7
6
5

SI4835DDY-T1-GE3-GP

1128-SB

ACES-CONN14G-GP

D
D
D
D

PC3803
SCD01U50V2KX-1GP

A

PC3802
SCD1U50V3KX-GP

PU3801
S
S
S
G

2

2

1

DY
2

PD3801
P6SBMJ27APT-GP

1
2
3
4

PC3805
SCD01U50V2KX-1GP

9
10
11
12
13
14

PR3809
240KR3-GP

2
3
4
5
6
7

2

8
K

1

1

DCIN1

PC3801
SC1U25V5KX-1GP

X01

E

R2
PDTC124EU-1-GP

PDTA124EU-1-GP

PS_ID_R
+DC_IN
GND

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom

DCIN_JACK

Rev

Enrico 14 AMD

5

4

www.bblianmeng.com
3

Date:
2

A00

Friday, April 22, 2011

Sheet
1

38

of

109

5

4

3

2

1

SSID = BATT CONN

D

D

Batt Connecter

X01

27 BAT_IN#
BATT1

X01

10
1
AFTP3901

1

BT+
R3904

BAT_ALERT

2 100R2J-2-GP

PBAT_PRES1#

1

PD3902
C3901
SC2200P50V2KX-2GP

DY SMF18AT1G-GP
A

2

C3902
SCD1U50V3KX-GP

2

1

K

1

2
3
4
5
6
7
8
9
11
ALP-CON9-4-GP

20.81507.009

1128-SB

1

AFTP3906

C

C

2 100R2J-2-GP

PBAT_SMBDAT1

R3902

1

2 100R2J-2-GP

PBAT_SMBCLK1

B

2

EC3902
DY
SC10P50V2JN-4GP

1
1
1
1

AFTP3902
AFTP3903
AFTP3904
AFTP3905

PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
BT+

1

1

1

27,40 BAT_SCL

R3903

DY
2

27,40 BAT_SDA

EC3901
SC10P50V2JN-4GP

B

Close to Batt Connector
For actual location, need to be swap all pin

3

3

3

BAT_SCL

BAT_SDA

BAT_IN#
D3902

D3903

1
1

2

1

D3901

2

2
BAV99-8-GP

BAV99-8-GP

BAV99-8-GP

83.BAV99.D11

83.BAV99.D11

83.BAV99.D11

2nd = 83.00099.K11 2nd = 83.00099.K11
3rd = 83.00099.T11 3rd = 83.00099.T11

3D3V_AUX_KBC

2nd = 83.00099.K11
3rd = 83.00099.T11

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

BATT CONN

Rev

Enrico 14 AMD
Sheet
1

A00
39

of

109

5

4

3

2

1

SSID = Charger

D

D

AD+_TO_SYS

2

2

38 PWR_CHG_AD_OFF

PWR_CHG_SRN

DY

CHG_AGND

CHG_AGND

0

90W

1

0

130W

0
5

1

DY

1
2

1
2

2

EC4002
SCD1U25V2ZY-1GP

1

EC4001
SC2200P50V2KX-2GP

PC4009
SCD1U50V3KX-GP

PC4006
SC10U25V5KX-GP
2
1

1
2

PC4008
SC10U25V5KX-GP
2
1

1

D

PQ4003
2N7002E-1-GP

2

.

A

.
.
. .

PR4033

DY120KR2F-L-GP



Wistron Corporation

G

DY

GAP-CLOSE-PWR-3-GP

1
2

DY

S

1

DY

2

G

S

0

49K9R2F-L-GP

65W

PR4012
1
2
DY
316KR2F-GP
PR4037

1

AD_IA_HW2

CHG_AGND

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
AC_IN#
Title

2

AD_IA_HW

PC4001
SCD1U25V3KX-GP

PQ4007
2N7002A-7-GP

PWR_CHG_CSOP_1

PWR_CHG_ACOK

PR4036
DY
120KR2F-L-GP

AC_IN#

D

AD+

EC code only BQ24707
H_PROCHOT#

2010/11/10 X01

1

59K

27
A

2

33.2K

130W

PR4025
27
DY100KR2J-1-GP

B

PR4027
100KR2J-1-GP

1

90W

PR4061
100KR2J-1-GP

DY

2010/11/10 X01

2

24K

2

65W

PR4062
100KR2J-1-GP

2

PR4023

PWR_CHG_REGN

1

3D3V_AUX_S5

1

Adapter Type

CHG_AGND

PWR_CHG_REGN

ROSA

2

3D3V_AUX_S5

CHG_AGND

27

1

X01
2010/11/10 X01

GAP-CLOSE-PWR-3-GP
PG4006
1
2

5
6
7
8
AD_IA

PC4021
SCD1U25V2KX-GP
2
1

2
0R0402-PAD

DY

2010/11/10 X01

PR4022

2

S

1 PR4024
8K45R2F-2-GP

GAP-CLOSE-PWR

1
PC4022
1
SC220P50V2JN-3GP

PG4011
2

CHG_AGND

PWR_CHG_CMPOUT

G

PWR_CHG_IOUT

2

GND

BQ24707ARGRR-GP

7

IOUT

14

GND

ACOK#

1

DY

S

5

2

CHG_AGND

CHG_AGND

21

AD_IA_HW2 27

DYPR4026
100KR2J-1-GP

4

DY

2010/11/10 X01

DY
1

PWR_CHG_REGN

1
PQ4001
2N7002A-7-GP

D

G

PR4035
10KR2F-2-GP

2

1

3D3V_AUX_S5

2

D

DY

1

DY

PR4018
0R2J-2-GP
PR4023
59KR2F-GP

PQ4006
2N7002A-7-GP

SRP
ILIM
SRN

2

B

10

PWR_CHG_IFAULT
11 IFAULT#

2
10R2F-L-GP
2
7D5R2F-GP

2

1
1

PWR_CHG_ILIM
PR4017
100KR2J-1-GP

PR4028
15KR2F-GP

DY

1
PR4021
1
PR4020

PC4018
SC10U25V5KX-GP
2
1
PC4019
SCD1U50V3KX-GP

12

DELETE PC4014 X01

PC4017
SC10U25V5KX-GP
2
1

PWR_CHG_SRP

G

13

PWR_CHG_CMPIN

PC4016
SC10U25V5KX-GP
2
1

SDA

PWR_CHG_LODRV

PC4015
SC10U25V5KX-GP
2
1

PWR_CHG_BAT_SDA 8
1
GAP-CLOSE-PWR-3-GP

15

1

2
PG4008

LODRV

BT+

1
2
PR4016
D01R2512F-4-GP

2

SCL

2BT+_R

PG4010
GAP-CLOSE-PWR-3-GP
1
2

PWR_CHG_BAT_SCL 9
1
GAP-CLOSE-PWR-3-GP

D
D
D
D

27,39 BAT_SDA

3D3V_AUX_S5

DELETE PR4015 X01

2
PG4007

1

PC4013
SC3300P50V3KX-1GP

SI4178DY-T1-GE3-GP
PU4001
S
S
S

2010/11/10 X01

PWR_CHG_CMPIN

PWR_CHG_PHASE

X01

3
2
1

27,39 BAT_SCL

19

PHASE

PL4001
IND-5D6UH-52-GP

DY2

5
6
7
8

1
CHG_AGND

1
CMPIN

C

Charger Current=1.4~3.6A

PWR_CHG_HIDRV

18

HIDRV

4

DY

3
2
1

1
2

PWR_CHG_BTST

2
PC4007
SC1U25V3KX-1-GP

PG4009
GAP-CLOSE-PWR-3-GP
1
2

PC4024
SCD1U50V3KX-GP

REGN

16

CMPOUT

3D3MR2J-GP

4

GAP-CLOSE-PWR-3-GP
PG4001
1
2

PG4004
1
2

2
2

1

PWR_CHG_ACN

17

1

PC4020
SCD1U25V2KX-GP
1

3

GAP-CLOSE-PWR-3-GP
PG4005
1
2

1

1

1
BTST

ACDET

PC4011
SCD047U25V2KX-GP

2
1

PR4014

PR4013
100KR2F-L1-GP

CHG_AGND
CHG_AGND

6

A

DY

PC4023
SCD1U25V2KX-GP

please help to check
which net connect it

PWR_CHG_ACDET

VCC

K

ACN

1
27

20

PR4009
0R3J-0-U-GP
1
2

CHG_AGND

PWR_CHG_CMPOUT

2

AD_IA_HW

PU4005

CHG_AGND

X01

PWR_CHG_REGN
PD4001
SD103AWS-1-GP

2010/11/10 X01

2

S

G

2

DY

PR4011
19K1R2F-GP

PC4012
SCD01U50V2KX-1GP

49K9R2F-L-GP PR4031
2
1

D

PQ4004
2N7002A-7-GP

1

1

2

2010/11/10 X01

2

PG4002

2

2
20R5J-GP
2

2

1
PR4010
PWR_CHG_IOUT

X01

G

PC4010
SCD47U25V3KX-2GP

1
PR4029
30K9R2F-GP

DY

CHG_AGND CHG_AGND

PWR_CHG_VCC

2

316KR2F-GP

8
7
6
5

PWR_DCBATOUT_CHG

D
D
D
D

PR4008
20R5J-GP
1

D
D
D
D

Id= -10A
Qg= -22nC
Rdson=14~13mohm

PR4005
470KR2J-2-GP

SI4178DY-T1-GE3-GP
PU4004
S
S
S

C

DY

84.2N702.A3F
2nd = 84.DM601.03F

2010/11/10 PR4007
X01

PWR_CHG_CMPIN

2N7002KDW-GP

X01

ACP

6

PWR_CHG_ACP

1
AD+

1

120KR2F-L-GP

DY
2

S

PR4032

2

PC4002
SCD1U25V2KX-GP

2

5

1

4

2

GAP-CLOSE-PWR-3-GP

2

3

DY 1

1

1

PWR_CHG_ACOK

AD+

PG4003
GAP-CLOSE-PWR-3-GP
PR4006
0R2J-2-GP
2

2

PWR_CHG_CMPOUT

G

PU4003
S
S
S
G

1
2
3
4

SI4835DDY-T1-GE3-GP

PC4004
SCD1U50V3KX-GP

2

2

D

DY

PQ4002

AD+_G_1

PQ4005
2N7002A-7-GP

AD+_G_2

Id= -10A
Qg= -22nC
Rdson=14~13mohm

DC_IN_D

PR4034
100KR2J-1-GP

DY100KR2J-1-GP

SI4835DDY-T1-GE3-GP

BT+

1
2
PR4002
D01R2512F-4-GP

PC4003
SC1U25V3KX-1-GP
2
1

1

1
PR4030

6,27 H_PROCHOT#

1
2
3
4

1

3D3V_AUX_S5
PWR_CHG_REGN

PR4004
1
2
10KR2J-3-GP

0802 Rename H_PROCHOT#

PU4002
S
S
S
G

D
D
D
D

1

8
7
6
5

AD+

PR4001
10KR2F-2-GP
PR4003
100KR2J-1-GP

EE need pull high and net name

DCBATOUT

Size
Document Number
Custom

1128-SB

CHARGER BQ24707

Enrico 14 AMD

Date:
4

www.bblianmeng.com
3

2

Friday, April 22, 2011

Sheet
1

Rev

A00
40

of

109

A

B

C

SSID = PWR.Plane.Regulator_3p3v5v

PWR_5V_LL1

19

PWR_5V_DRVL1

24

PWR_5V_VO1

2

PWR_5V_FB1

23

3V_5V_POK

1

PWR_5V_ENTRIP1

1
2
3

1
2
3

1

2

1

1
1
2

2D2R5F-2-GP

ENTRIP1

VREF

GND

TONSEL

GND

SKIPSEL

VCLK

4
3
2
1

G

2

1

S

DY PC4122
SC560P50V-GP
2

ENTRIP2

2

PG4130

DY

PT4101

1

DY PR4112

1128-SB

15

PG4101
GAP-CLOSE-PWR-3-GP
1
2
PG4122
GAP-CLOSE-PWR-3-GP
1
2
3

PG4124
GAP-CLOSE-PWR-3-GP
1
2
PG4125
GAP-CLOSE-PWR-3-GP
1
2
PG4126
GAP-CLOSE-PWR-3-GP
1
2

1116:84.07716.037

25

PR4115
0R2J-2-GP

PWR_5V3D3V_VLK

DY

1

18

PR4116
33KR2F-GP
PWR_5V_FB1_R

2

0R0402-PAD
PR4122
1
2

51125_VREF

DY

PR4123
1
0R2J-2-GP

2

DY

PR4124
1
0R2J-2-GP

PR4118
PR4121

TPS51125
DY
ASM

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
H/S: TPC8061-H / 21mohm/30mOhm@4.5Vgs/ 84.08061.037
L/S: TPCA8065-H / 12mohm/15mOhm@4.5Vgs/ 84.08065.037

RT8205B
ASM
DY

SC4D7U6D3V5KX-3GP

2

TONSEL

CH2

GND

200kHz

265kHz

VREF

245kHz

305kHz

VREG3

300kHz

375kHz

VREG5

365kHz

460kHz

2

1

1

PR4120
21K5R2F-GP
2

2

Close to VFB Pin (pin2)

3V_5V_POK 46

PC4127
2

3D3V_PWR_2

1

3D3V_AUX_S5
PR4125

2

0R0402-PAD

SKIPSEL

VREG3 or VREG5

VREF(2V)

Operating
Mode

OOA Auto Skip

Auto Skip

Operating
Mode
CH1

DY

PR4119
100KR2J-1-GP

EN0

TPS51125:

PC4124
SC18P50V2JN-1-GP

3D3V_PWR_2

5V_AUX_S5

SC10U10V5KX-2GP

3D3V_PWR_2

PC4126

0R0402-PAD

Close to VFB Pin (pin5)

17

GAP-CLOSE-PWR-3-GP

3D3V_AUX_S5_5_51125 8

PR4118
1
0R2J-2-GP

1

1

3D3V_PWR_2

DY
PR4121

2

2

51125_VREF

2

2

2

PG4127
1

1

2

1 2

PWR_5V3V_SKIPSEL
14

3D3V_PWR_2

1
2

2
2

D

PG4118
GAP-CLOSE-PWR-3-GP
1
2

1

PWR_5V3V_TONSEL4

PGOOD

VREG3

51125_FB2_R
PC4125
DYSC18P50V2JN-1-GP

2

1

1116:84.07716.037

DY

1

K
A
4
3
2
1

PU4105
SI7716ADN-T1-GE3-GP

2

VFB1

1

VO1

VFB2

5V_S5
PG4119
GAP-CLOSE-PWR-3-GP
1
2

PG4123
GAP-CLOSE-PWR-3-GP
1
2

1
2
IND-2D2UH-46-GP-U

2

VO2

EN0

1

1
2

1
2

1
2

5
6
7
8

20

PC4120
SCD1U10V2KX-4GP

DRVL1

2

LL1

DRVL2

PG4116
GAP-CLOSE-PWR-3-GP
1
2

5V_PWR

PL4101

1

LL2

21

PG4111
GAP-CLOSE-PWR-3-GP
1
2

1

DRVH1

PWR_5V_DCBATOUT

PG4114
GAP-CLOSE-PWR-3-GP
1
2

S

VREG5

G

1

DY

PR4114
0R2J-2-GP

PR4117
10KR2F-2-GP

1

1

1
1

2
VIN

8
7
6
5
D
D
D
D
S
S
S
G

1
2PWR_3D3V_EN 13
PR4101
820KR2F-GP
PWR_3D3V_ENTRIP2
6
51125_VREF
3

1
2
3
4

DY S
2

PC4121
SC330P50V2KX-3GP

Design Current =7.1A
11.14A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

www.bblianmeng.com
C

D

TPS51125_5V/3D3V

Size
A2

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD
Sheet
E

A00
41

of

109

5

4

3

SSID = PWR.Plane.CORE.REG

2

10825

1
2
PC4210 SC47P50V2JN-3GP
PC4214 SC180P50V2JN-1GP
1
2
PR4227

33KR2F-GP

D

PC4218
1
2

26265_FB_NB_R

1

SC1KP50V2JN-2GP

DCBATOUT

D

PC4201
1
2

5V_S5

1

PR4209

1

SC1KP50V2JN-2GP

2
1

1 PR4228 2
22KR2F-GP

2

PC4209
SC1U10V3KX-4GP

GNDA_VCORE

2010/11/10 X01

6

1
2

1
2

1
2

C

4
3
2
1

2

Peak Current=11
Design Current =7.7A
16.5A

2

Wistron Corporation

PC4221 SC1KP50V2JN-2GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

1

2

DY

Title

SC33P50V2JN-3GP
EC4270

www.bblianmeng.com

VREG : +VCC_CORE&+VDDNB

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD
Sheet

A00
42

of

109

5

4

3

2

1

SSID = PWR.Plane.VDDNB.REG

D

D

1

4
3
2
1

SIR172DP-T1-GE3-GP
S
S
S
G

SCD1U25V3KX-GP

2

Peak Current=10
Design Current =7A
15A
A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

TPS51218_VDDNB

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD
Sheet
1

A00
43

of

109

5

4

3

2

1

SSID = PWR.Plane.Regulator_1p5v0p75v

DCBATOUT

PWR_DCBATOUT_1D5V
PG4401
1
2

GAP-CLOSE-PWR-3-GP
PG4402
1
2

D

D

GAP-CLOSE-PWR-3-GP
PG4403
1
2

0728

VBST

15

PR4401
PWR_1D5V_VBST 1
2
2D2R3J-2-GP

14

PWR_1D5V_DRVH

13

PWR_1D5V_SW

11

TPS51216_DRVL

EN/PSV
DRVH

2

1
2

2
1

PC4406
SCD1U50V3KX-GP

1
2

1
2

2

1128-SB

Design Current =10.32A
16.21A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

RT8207_1D5V_S3
Size
Document Number
Custom

Rev

A00

Enrico 14 AMD

Date:
5

4

www.bblianmeng.com
3

2

Sheet

Friday, April 22, 2011
1

44

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

VDDR & VDDP

Rev

Enrico 14 AMD
Sheet
1

45

A00
of

109

A

B

C

D

E

SSID = PWR.Plane.1V1REG
0824
DCBATOUT

2

2

5
6
7
8

2

1
2

1D1V_PWR

GAP-CLOSE-PWR-3-GP
PG4605
1
2

4
3
2
1

1

1

1
2

2

GAP-CLOSE-PWR-3-GP
PG4610
1
2
GAP-CLOSE-PWR-3-GP
PG4611
1
2
GAP-CLOSE-PWR

1

PR4608

DY

6K49R2F-1-GP

PC4610
SC18P50V2JN-1-GP

2

2

DY

GAP-CLOSE-PWR-3-GP
PG4609
1
2

PT4601
SE220U2VDM-8GP

PWR_1D1V_PWR

2

4
3
2
1

S
S
S
G
PC4609

2010/11/10 X01

2010/11/10 X01

GAP-CLOSE-PWR-3-GP
PG4607
1
2

1128-SB
PC4608

2

PU4603
SI7716ADN-T1-GE3-GP

2

DY

1

1
PR4606

0728

PC4607
SC1U10V2KX-1GP

151218_SW_GND_VTT_1D1V
2

TPS51218DSCR-GP-U1

4

GAP-CLOSE-PWR-3-GP
PG4606
1
2

1D1V_PWR

PL4601
1
2
IND-2D2UH-46-GP-U
2D2R5J-1-GP

SC330P50V2KX-3GP

1
1

PWR_1D1V_LGATE

5V_S5

SCD1U10V2KX-4GP

2

11
10
9
8
7
6

PG4608

PR4607
470KR2F-GP

GND
VBST
DRVH
SW
V5IN
DRVL

D
D
D
D

PC4601
SC1KP50V2KX-1GP

2

PGOOD
TRIP
EN
VFB
CCM

GAP-CLOSE-PWR-3-GP

PR4605 1
100KR2J-1-GP

1
2
3
4
5

5
6
7
8

PWR_1D1V_PWRGD
PWR_1D1V_TRIP
PWR_1D1V_EN
PWR_1D1V_FB
PWR_1D1V_CCM

A

1

PD4601
K
SDMK0340L-7-F-GP

PC4606
SCD1U25V3KX-GP
PR4601
2D2R3J-2-GP
PWR_1D1V_BOOT 1
2PWR_1D1V_BOOT_R2
1
PWR_1D1V_UGATE
PWR_1D1V_PHASE

2

2

1D1V_S5

PG4603
1
2

Design Current =7A
11A

PR4610
10K5R2F-GPDY

Wistron Corporation

2

I/P cap: 4.7U 25V K0805 X5R/ 78.47522.51L
Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B
O/P cap: 220U 2V EEFCX0D221ER 15mOhm 3.87Arms PANASONIC/79.22719.20L
H/S: SIS412DN/ 24mohm/30mOhm@4.5Vgs/ 84.00412.037
L/S: SIS412DN/ 24mohm/30mOhm@4.5Vgs/ 84.00412.037

1

PWR_1V_FB

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Vout=0.704V*(R1+R2)/R2
A

B

www.bblianmeng.com
C

D

Size
A2

Document Number

Date:

Friday, April 22, 2011

1.1V

Rev

Enrico 14 AMD

A00
Sheet

E

46

of

109

5

4

3

2

1

SSID = PWR.Plane.1V8REG

APW7153B for 1D8V_S0
PR4709

1

3D3V_S5

DY 2

1D8V_PW R

10KR2F-2-GP
3D3V_S5

Design Current =3A

1D8V_PW R

GND

2

1
1

1

2

2

11

SHDN/RT

PC4709

PR4710

2PW R_1D8V_COMP_R
1

2

DY

PW R_1D8V_FB

PC4713

PC4714

PR4707
16KR2F-GP

PC4716

2

1

PR4706

SCD1U10V2KX-4GP
PC4707

GND

COMP

74.07153.A73

PR4708
20KR2F-L-GP
PW R_1D8V_RT

1

FB

PW R_1D8V_COMP 10

1

3

2

LX#3

1

POK

9

1

PW R_1D8V_FB

PG4705
GAP-CLOSE-PW R-3-GP
1
2

1
2
IND-1D5UH-23-GP

2

8

PW R_1D8V_LX

2

4

1

LX#4

SC22U6D3V5MX-2GP

VDD

1

7

PL4702

SC22U6D3V5MX-2GP

5

SC100P50V2JN-3GP

PGND

2

PVDD

2

6

820KR2F-GP

PR4704
1MR2J-1-GP

SCD1U10V2KX-5GP

1

PC4708

D

PG4706
GAP-CLOSE-PW R-3-GP
1
2

PU4702
APW 7153BQBI-TRG-GP

2

1
2

2

PC4711
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

2D2R2F-GP

1

PR4705
PC4715

1

36 1D8V_S0_PW RGD

2

D

1D8V_S0
PG4704
GAP-CLOSE-PW R-3-GP
1
2

SC100P50V2JN-3GP

20KR2F-L-GP

PC4712
C

C

1DY

2

Vo=0.8*(1+(R1/R2))

SC47P50V2JN-3GP

D

X01
PQ4702
2N7002K-2-GP

18,27,36,44,46 PM_SLP_S3#

2

PR47111

S

G

84.2N702.J31

I/P cap: 4.7U 25V K0805 X5R/ 78.47522.51L
O/P cap: 22U 25V M0805 X5R/ 78.22610.51L
Inductor: 3.3uH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A

PW R_1D8V_RT_R

0R0402-PAD

B

1

B

DY
2

PC4710
SCD1U10V2KX-5GP


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

RT8015B_1D8V_S0
Enrico 14 AMD
Sheet
1

47

Rev

A00
of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Reserved
5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet
1

48

of

109

5

4

3

2

1

SSID = VIDEO
LVDS CONNECTOR

R4907
2
100KR2J-1-GP

1

INVERTER POWER

RN4901
BLON_OUT_C
LCD_TST_C

DCBATOUT_LCD

1
2
3
4

LCD_BRIGHTNESS

8
7
6
5

BLON_OUT 27
LCD_TST 27
L_BKLT_CTRL 6

DCBATOUT

DCBATOUT_LCD

SRN100J-4-GP

F4901
1

POLYSW-1D1A24V-GP-U
2

LCD1

USB_PN7
USB_PP7

18
18

2

2
1

3D3V_S0

3D3V_CAMERA_S0

A00

LCDVDD

R4906

2

EC4903
SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

AFTP4906
AFTP4907

1 0R3J-0-U-GP

2

TP4904TPAD14-GP

C4902

1

C4901

C4903
SC10U6D3V5MX-3GP

DY
2

1

32

1
1

C4904
SC1KP50V2KX-1GP

Camera Power
USB_CAMERA# R4903 1
2 0R0603-PAD
USB_CAMERA R4904 1
2 0R0603-PAD
LCD_TST_C
TP4903TPAD14-GP
1
3D3V_CAMERA_S0
3D3V_S0

ETY-CONN30E-2-GP-U2

USB_CAMERA#
USB_CAMERA

C4905
SCD1U50V3KX-GP

1

LVDS_DDC_DATA
LVDS_DDC_CLK
LVDSA_CLK
LVDSA_CLK#
LVDSA_DATA2
LVDSA_DATA2#
LVDSA_DATA1
LVDSA_DATA1#
LVDSA_DATA0
LVDSA_DATA0#

29
28
27
26
25
24
23
22
21
20
19
18
17
16

2

6
6
6
6
6
6
6
6
6
6

2
3
4
5
6
7
8
9
10
11
12
13
14
15
NP2

1

BLON_OUT_C
LCD_BRIGHTNESS

30

1

X01

69.50007.A31
2nd = 69.50007.A41

1

D

31
NP1
1

2

D

Close to LVDS connector

C

C

LVDSA_CLK
LCD_BRIGHTNESS
LVDSA_CLK#

EC4902

DY
SC33P50V2JN-3GP

SC33P50V2JN-3GP

2

DY

1

1

1

EC4901

DY

2

SC5D6P50V2CN-1GP
2

DY

EC4906

SC5D6P50V2CN-1GP
2

1

LCD_TST_C
EC4905

For EMI request

B

B

3D3V_S0

LCDVDD

1
DY R4905
100KR2J-1-GP

84.06402.B3D
2nd = 84.03456.D3D

1

FPVCC_CTL1

2

2
SCD1U25V2KX-GP

R4908
2
1
0R3J-0-U-GP

AO6402A-GP

2
330KR2J-L1-GP

1
C4906

D 6
D 5
S 4

R4913
150R3J-L-GP

Q4902

2

1
R4910

15V_S5

A00

Q4901
D
D
G

1
2
3

4

3

5

2

6

LCDVDD_1

1
2N7002KDW-GP

84.2N702.A3F
2nd = 84.DM601.03F

6 LVDS_VDD_EN

1

5V_S5

D4901

A

2
R4912 100KR2J-1-GP

A

Q4903

1

3
3LCDVCC_EN

1

FPVCC_CTL3

R1


2

27 LCD_TST_EN

R2
PDTC144EU-1-GP

2

Wistron Corporation

BAT54CPT-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

83.R2003.E81
2nd = 83.00054.Q81
3rd = 83.BAT54.081

5

Title

LCD/Inverter Connector

4

www.bblianmeng.com
3

Size
Document Number
Custom

Enrico 14 AMD

Date:
2

Friday, April 22, 2011

Rev

A00

Sheet
1

49

of

109

5

4

3

5V_CRT_S0
5V_CRT_S0

*Pi-filter & 150 Ohm pull-down
resistors should be as close
as to CRT CONN.
* RGB signal will hit 75 Ohm
first, then pi-filter, finally
CRT CONN.

CRT_RED_R
CRT_GREEN_R
CRT_BLUE_R

8
7
6
5

4
3

2

3

DY

SC22P50V2JN-4GP

1

SC22P50V2JN-4GP

BAV99PT-GP-U

CRT_R

D5003

2
L5001
CRT_GREEN_R

SRN0J-6-GP

3

DY

X01

1
BAV99PT-GP-U

C5007
SC10P50V2JN-4GP
2
1

1

1

CRT_B

CRT_B
C5006
SC10P50V2JN-4GP
2
1

1
2
3
4

CRT_DDCDATA_CON
CRT_DDCCLK_CON

4
3

C5004

2
SC8P250V2CC-GP

2
SC8P250V2CC-GP

RN5001
SRN150F-1-GP
RN5005

C5003

2
SC8P250V2CC-GP

1

C5002

C5005
SC10P50V2JN-4GP
2
1

L5003
1
2
SBK160808T-300Y-N-GP

8
7
6
5

X02

CRT_G

1
2
SBK160808T-300Y-N-GP

CRT_BLUE_R

C

2

DY DY C5009
C5008

L5002
68.00119.231
1
2
SBK160808T-300Y-N-GP

RN5004

DY

D

D5001

1
1

CRT RGB
CRT_RED_R

8
7
6
5

0R8P4R-PAD-1-GP

85 VGA_CRT_DDCDATA
85 VGA_CRT_DDCCLK

1

CRT_G

RN

1
2

DY

CRT_DDCDATA_CON
CRT_DDCCLK_CON

X01
1
2
3
4

3

BAV99PT-GP-U

SRN0J-7-GP

6 CRT_RED
6 CRT_GREEN
6 CRT_BLUE

CRT_R
RN5002
SRN4K7J-8-GP

2
2

DY

D5002

1
2

RN5003

1
2
3
4

85 VGA_CRT_RED
85 VGA_CRT_GREEN
85 VGA_CRT_BLUE

1

Layout Note:

SSID = VIDEO

D

2

5V_CRT_S0_R

5V_S0

5V_CRT_S0

500mA
D5004

F5001

1

2

2

1

FUSE-1D1A6V-4GP-U

69.50007.691
2nd = 69.50007.771

CH551H-30PT-GP

C

RN

1 RN5006 4
2
3
0R4P2R-PAD

6 DDCDATA
6 DDCCLK

5V_CRT_S0_R
CRT1

9
CRT_DDCDATA_CON
CRT_DDCCLK_CON

12
15

CRT_R
CRT_G
CRT_B
C5011 1

DY2

1
2
3

CRT_VSYNC_CON
CRT_HSYNC_CON

14
13

NC#4
NC#11

4
11

CHASSIS#16
CHASSIS#17

16
17

GND
GND
GND
GND
GND

5
6
7
8
10

VCC_CRT
DDCDATA_ID1
DDCCLK_ID3
CRT_RED
CRT_GREEN
CRT_BLUE
VSYNC
HSYNC

1

1

SC33P50V2JN-3GP

2

DY

D-SUB-15-129-GP
C5001
SC33P50V2JN-3GP

X01
B

AFTP509

20.20948.015

B

CRT Hsync & Vsync level shift

AFTP501
AFTP502
AFTP503
AFTP504
AFTP505
AFTP506
AFTP507
AFTP508

5V_CRT_S0

1 5V_CRT_S0
1 CRT_DDCDATA_CON
1 CRT_DDCCLK_CON
1 CRT_R
1 CRT_G
1 CRT_B
1 CRT_HSYNC_CON
1 CRT_VSYNC_CON

U5001

0R2J-2-GP
2

R5031 1

83,85 VGA_CRT_VSYNC

R5008 1

R5007 1

CRT_HSYNC1_1 1 R5001 2
10R2J-2-GP

CRT_HSYNC_CON

CRT_DDCDATA_CON
C5012

DY

SYNCOE#

6 CRT_VSYNC

4

2 0R0402-PAD

For UMA CRT
A

Y

GND

74AHCT1G125GW -1-GP

2 0R0402-PAD

DY

5V_CRT_S0
U5002

1

OE#

2

A

3

GND

VCC

5

Y

4

0R2J-2-GP
2

CRT_VSYNC1_1 1 R5004 2 CRT_VSYNC_CON
10R2J-2-GP

CRT_HSYNC_CON
C5013

DY

74AHCT1G125GW -1-GP

CRT_VSYNC_CON
C5014

DY

CRT_DDCCLK_CON
C5015

DY

SC100P50V2JN-3GP

For DIS CRT

DY

SC100P50V2JN-3GP
2

R5009 1

5

1

3
83,85 VGA_CRT_HSYNC

VCC

2

A

1

OE#

2

2
SC18P50V2JN-1-GP

1

1

2 0R0402-PAD

2
SC18P50V2JN-1-GP

R5010 1

1

For UMA CRT
6 CRT_HSYNC



A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

For DIS CRT
Title
Size

Document Number

A3
5

4

www.bblianmeng.com
3

Date:
2

DCIN

Rev

A00

Enrico 14 AMD
Friday, April 22, 2011

Sheet
1

50

of

109

5

4

3

2

1

SSID = VIDEO

HDMI CONN

HDMI Level Shifter & CONNECTOR

HDMI1

APU_HDMI_CLK#
APU_HDMI_CLK
APU_HDMI_DATA0#
APU_HDMI_DATA0

APU_HDMI_DATA1#
APU_HDMI_DATA1
APU_HDMI_DATA2#
APU_HDMI_DATA2

23

20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
22

D

APU_HDMI_DATA2 6
APU_HDMI_DATA2# 6
APU_HDMI_DATA1 6
APU_HDMI_DATA1# 6
APU_HDMI_DATA0 6
APU_HDMI_DATA0# 6
APU_HDMI_CLK 6
APU_HDMI_CLK#

6
5V_CRT_S0_R

DDC_CLK_HDMI
DDC_DATA_HDMI

X01

1

21

Impedance:100 ohm

D

2

SCD1U10V2KX-5GP

R5121

R5120

R5119

R5118

R5117

R5116

R5115

HDMI_PLL_GND

R5114

C

HPD_HDMI_CON

1
499R2F-2-GP

22.10296.171

2

1
499R2F-2-GP
2

1
499R2F-2-GP
2

1
499R2F-2-GP

1
499R2F-2-GP

2

2

1
499R2F-2-GP
2

1
499R2F-2-GP
2

2

1
499R2F-2-GP

C5102

SKT-HDMI19P-63-GP-U

0819

1

checklist:
suggestion to stuff 604-ohm for UMA and PX

D

C

R5131

2

DP1_HPD 6

1KR2J-1-GP

1

Q5103
2N7002K-2-GP

DY

R5132
2K2R2J-2-GP

S

G

2

84.2N702.J31
2nd = 84.07002.I31

1

5V_S0

R5113
100KR2J-1-GP

2

DY

B

B

3
4

5V_S0

2
1

RN5101
SRN2K2J-1-GP

6 PCH_HDMI_DATA_R
6 PCH_HDMI_CLK_R

0R0402-PAD1 R5129
0R0402-PAD1 R5130

2
2

DDC_DATA_HDMI
DDC_CLK_HDMI



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

HDMI Level Shifter/Connector

Size
A3

Document Number

Date:

Friday, April 22, 2011

Enrico 14 AMD
Sheet
1

Rev

A00
51

of

109

5

4

3

2

1

D

D

C

C

B

B


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

eDP

Rev

Enrico 14 AMD
Sheet
1

52

A00
of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

53

A00
of

109

(Blanking)



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

www.bblianmeng.com

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet

54

A00
of

109

5

4

3

2

1

SSID = User.Interface

D

D

C

C

ITP Connector
H_CPURST# use pull-up Resistor close
ITP connector 500 mil ( max ),
others place near CPU side.

B

B

CPU

ITP Connector
TCK(PIN 5)

TCK(PIN AC5)
FBO(PIN 11)



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

ITP

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet
1

55

of

109

5

4

3

2

1

SATA HDD Connector

SSID = SATA

X01
HDD1

C5604
SCD1U10V2KX-5GP

DY

DY

2

2

1

C5601
SC10U6D3V5KX-1GP

1

3D3V_S0

3D3V_S0

P1
P2
P3

V33
V33
V33

5V_S0

P7
P8
P9

V5
V5
V5

P13
P14
P15

V12
V12
V12

S2
S3

A+
A-

S6
S5

B+
B-

D

1

1

5V_S0
AFTP5607
AFTP5608
AFTP5609

2

2

C5606
C5605
SCD1U10V2KX-5GP
SC10U10V5ZY-1GP

HDD1_20
HDD1_21
HDD1_22

1
1
1

19 SATA_TXP0
19 SATA_TXN0
19 SATA_RXP0_C
19 SATA_RXN0_C

C5603
C5602

2 SCD01U16V2KX-3GP SATA_RXP0
2 SCD01U16V2KX-3GP SATA_RXN0

1
1

16
17

16
17

NP1
NP2

NP1
NP2

GND
GND
GND
GND
GND
GND
GND
GND

S1
S4
S7
P4
P5
P6
P10
P12

DAS/DSS

P11

D

SKT-SATA7P-15P-80-GP

62.10065.H71

C

C

ODD Connector
SATA_RX- and SATA_RX+ Trace
Length match within 20 mil

X01
3D3V_S0
ODD1

DY
5V_S0

DY

SKT-SATA7P+6P-26-GP-U

B

22.10300.201
0720: Modify Zero ODD Circuit

2

DY

2

DY

1

R5606
10KR2J-3-GP

0721 Remove ODD_DA PU

G547F1P81U-GP

4
3
2
1

EN/EN#
OC#
IN#3
OUT#6
IN#2 DY OUT#7
GND
OUT#8

ODD_PW R_5V

5
6
7
8

100 mil

TC5604

U5601

TC5603

74.00547.C79
2ND =

B

Current limit
Active High
typ =>2A

3D3V_S0

1

3D3V_S0

R5611
10KR2J-3-GP

1

AA+
BB+

1

S3
S2
S5
S6

19 SATA_ODD_PW RGT

2

19 SATA_RXN1_C
19 SATA_RXP1_C

2

R5604
0R2J-2-GP

19 SATA_TXN1
19 SATA_TXP1
SCD01U16V2KX-3GP2
1 C5607 SATA_RX1-_C
SCD01U16V2KX-3GP2
1 C5608 SATA_RX1+_C

DP
MD

S1
S4
S7
P5
P6
8
9

SC10U10V5ZY-1GP

1

0720: Modify Zero ODD Circuit

P1
P4

integrated PU
GND
GND
GND
GND
GND
GND
GND

2

SATA_ODD_DA#_C

+5V
+5V

2

18 SATA_ODD_PRSNT#

P2
P3

1

ODD_PW R_5V

1

SC10U10V5ZY-1GP

R5603 2
0R5J-5-GP

5V_S0

R5612
10KR2J-3-GP
R5608
SATA_ODD_DA#_C

ODD_PW RGT#

2

DY

1

SATA_ODD_DA#

S

D

G

0R2J-2-GP
Q5602
2N7002K-2-GP

DY

84.2N702.J31
D

G

When the drive is powered on, the FET to the MD/DA pin drive is OFF.
When the drive is powered off, the FET to the MD/DA pin is ON

S

A

Q5601
2N7002K-2-GP

DY



84.2N702.J31

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DY

2 R5607

1
0R2J-2-GP
2 R5613 1
0R0402-PAD

SATA_ODD_PW RGT

SATA_ODD_DA# 17
Title

ODD_DA_Q 18

0712
5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

HDD/ODD

Rev

Enrico 14 AMD

A00
Sheet
1

56

of

109

5

4

3

2

1

SSID = ESATA

D

D

C

C

(Blanking)

B

B

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

ESATA/USB Charger

Size
A3

Document Number

Date:

Friday, April 22, 2011

Enrico 14 AMD
Sheet
1

57

Rev

A00
of

109

5

4

3

2

1

SSID = AUDIO

5

Speaker
Connector
D

D

1

DY

AFTP5805

1

2

2

DY

EC5804
MLVG0402220NV05BP-GP-U

EC5803
MLVG0402220NV05BP-GP-U

DY
2

2

DY

EC5802
MLVG0402220NV05BP-GP-U

MLVG0402220NV05BP-GP-U

EC5801

SPK1
ACES-CON4-4-GP

6

2
3
4

1

29 AUD_SPK_L+
29 AUD_SPK_R29 AUD_SPK_R+

1

1

1

29 AUD_SPK_L-

20.F0765.004
AFTP5801
AFTP5802
AFTP5803
AFTP5804

1
1
1
1

AUD_SPK_LAUD_SPK_L+
AUD_SPK_RAUD_SPK_R+

C

C

FOR EMI
B

1DY
EC5810

2
SCD1U10V2KX-5GP

1
EC5811

2
SCD1U10V2KX-5GP

1
EC5812

2
SCD1U10V2KX-5GP

1DY
EC5813

2
SCD1U10V2KX-5GP

1
EC5814DY

2
SCD1U10V2KX-5GP

1DY
EC5815

2
SCD1U10V2KX-5GP

B

AUD_AGND
AFTP5808

0804 Change to AGND

MIC2

1

29,82 INT_MIC_L_R

3
1

A

AFTP5809

1

2
4

DY



A

Wistron Corporation

ACES-CON2-19-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
AUD_AGND
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Audio Jack

Rev

Enrico 14 AMD

A00
Sheet
1

58

of

109

LAN TransFormer

SSID = LOM

XF5901

31 LAN_MDI1P

Rx Side

9

31 LAN_MDI1N

MDO1-

8

11

6

10

7

MDO1+

1CT:1CT
Tx Side

14

3

16

1

MDO0-

MDO0+

2 0R3J-0-U-GP

1
2

X01

XFORM-12P-36-GP
C5904
SCD01U16V2KX-3GP

SC1KP3KV8KX-GP-U
1

1CT:1CT

X01

0R3J-0-U-GP

2

2

31 LAN_MDI0P

15

1
SC1KP3KV8KX-GP-U

31 LAN_MDI0N

Surge
RN5901
SRN75J-2-GP-U

1
2

TVLST2304AD0-GP

1
R5904

2
C5902
1

C5901
2

1

6

Non-Surge

R5901 R5902
75R5F-1-GP
2

4

LAN_MDI1N

MDO3+
MDO3-

R5903
1

3

LAN_MDI1P

MDO2+
MDO2-

75R5F-1-GP
2

LAN_MDI0N

X02

4
3

1

5

2

Non-Surge Surge Surge
EU5901

LAN_MDI0P

1

Surge

Surge

MDO0-

2

GT1206150ASMD-GP
ES5902
MDO1+

1

Surge

MDO1-

2

1
C5911

Non-Surge

2
SC1KP2KV6KX-GP

ES5901
MDO0+

SC1KP3KV8KX-GP-U
2

C5903
1

X01

GT1206150ASMD-GP

RJ45
RJ45

9
MDO0+

1

MDO0MDO1+
MDO2+
MDO2MDO1MDO3+
MDO3-

2
3
4
5
6
7
8
10

NP1

NP2

MDO0+
MDO0MDO1+
MDO1MDO2+
MDO2MDO3+
MDO3-

1
1
1
1
1
1
1
1

AFTP5907
AFTP5908
AFTP5901
AFTP5904
AFTP5902
AFTP5903
AFTP5905
AFTP5906



Wistron Corporation

RJ45-8P-76-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

22.10177.J61

www.bblianmeng.com

Size
A3

Document Number

Date:

Friday, April 22, 2011

LAN

Rev

Enrico 14 AMD
Sheet

59

A00
of

109

5

4

3

2

1

SSID = Flash.ROM

SPI FLASH ROM (2M byte) for KBC
2

DY R6005
R6009
0R0402-PAD

Reserved 795 use LPC ROM or 791 LPC ROM

used

1

C6001

2

4
3
1
2

R6002
2
1
100KR2J-1-GP

RN6002
SRN100KJ-6-GP

used

C6002
SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

DY

2

SPI_POW R

Reserved 795 use LPC ROM or 791 LPC ROM

1

1

1

SPI_VCC

1

R6008

DY 0R2J-2-GP

D

R6007
0R0402-PAD

0R2J-2-GP

1

2

3D3V_AUX_KBC

2

3D3V_S5

D

3D3V_AUX_KBC

2

3D3V_S5

SPI_HOLD_0#

U6001

2

C

VCC
HOLD#/IO3
CLK
DI/IO0

SPI_VCC

8
7
6
5

EC_SPI_CLK 27
EC_SPI_DO 27

W 25Q16BVSSIG-GP

1

Reserved 795 use LPC ROM or 791 LPC ROM

72.25Q16.001
2nd: 72.25Q16.001
3rd: 72.25F16.00P
4th: 72.02516.A01

used

SC4D7P50V2CN-1GP

R6001
10KR2J-3-GP

C

DY DYEC6001
EC6003
SC4D7P50V2CN-1GP

DY

CS#
DO/IO1
WP#/IO2
GND

1

SPI_SO
EC_SPI_W P#_R

2

DY

2 33R2J-2-GP
1 0R2J-2-GP

1

R6003 1
R6004 2

1
2
3
4

2

27 EC_SPI_CS#
27 EC_SPI_DI
27 EC_SPI_W P#

SSID = RBATT
RTC_AUX_S5

3D3V_AUX_S5
U6003

B

B

2

2

3
1

RTC1

RTC_PW R

1 R6006 2
510R2J-1-GP

1
2
NP1
NP2

CH715FPT-GP

1

C6005
SC1U6D3V2KX-GP

+RTC_VCC

X01

83.R0304.B81
2nd = 83.00040.E81

PWR
GND
NP1
NP2

BAT-AAA-BAT-054-P04-GP-U

Width=20mils

62.70001.061

2

3D3V_S0

Q6001

DY

R6032
10KR2J-3-GP

1

G
D

1
R6031
10MR2J-L-GP
A

RTC_SENSE 17

S


2

2N7002K-2-GP

A

84.2N702.J31

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Flash/RTC

Rev

Enrico 14 AMD

A00
Sheet
1

60

of

109

5

4

3

2

1

SSID = USB
USB20_VCCA

USB20_VCCA
U6102

USB_OC#1 18

LOW ACTIVE TYPE!!
1

27 USB_PW R_EN#

DY

1

TC6101

2

1

C6104

2

1

DY

TC6103

USB_PN0_R
USB_PP0_R

ST100U6D3VBML1GP

74.00547.A79

C6103

ST220U6D3VDM-15GP

G547F2P81U-GP

2

USB2

5
1
1

8
7
6
5

2

C6102
SC1U10V3ZY-6GP

OUT#8
OUT#7
OUT#6
OC#

SC10U10V5ZY-1GP

1

U6102_EN

GND
IN#2
IN#3
EN/EN#

2

1
2
3
4

D

100 mil

SCD1U16V2KX-3GP

5V_S5

AFTP6102

D

2
3
4
6

1

SKT-USB6-16-GP

22.10321.S01

X01

R6101

2
0R0402-PAD

X01
USB20_VCCB

USB_OC#2 18
U6102_EN

LOW ACTIVE TYPE!!

DY

1

C6108

DY
2

1

C6107

USB20_VCCA
USB_PN0_R
USB_PP0_R

1
1
1

TC6102

C

ST220U6D3VDM-15GP

G547F2P81U-GP

2

AFTP6101
AFTP6103
AFTP6104

2

8
7
6
5

SC10U10V5ZY-1GP

C6101
SC1U10V3ZY-6GP

OUT#8
OUT#7
OUT#6
OC#

1

GND
IN#2
IN#3
EN/EN#

100 mil

2

1
2
3
4

1

C

U6101

SCD1U16V2KX-3GP

5V_S5

1 R6104 2
0R0402-PAD

27 USB_PW R_EN#

X02

B

USB_PP0_R

R6103
1

0R0603-PAD
2

R6102
1

0R0603-PAD
2

B

USB_PP0 18

C6105
SC6D8P50V2DN-GP

2

1

X01

USB_PN0_R

USB_PN0 18

C6106
SC6D8P50V2DN-GP

2

1

X01



A

A

U6105
USB_PN0_R

1
2
3

ESD I/O1
GND
DY
ESD I/O2

ESD I/O4
VP
ESD I/O3

6
5
4

Wistron Corporation

USB_PP0_R

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

5V_S5
Title

IP4220CZ6-GP
Size

5

4

www.bblianmeng.com
3

Document Number

USB Power SW

Rev

Enrico 14 AMD
Date:
2

Friday, April 22, 2011

A00

Sheet
1

61

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

USB 3.0

Rev

Enrico 14 AMD
Sheet
1

62

A00
of

109

5

4

3

2

1

SSID = User.Interface

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Bluetooth

Rev

Enrico 14 AMD

A00

Sheet
1

63

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

F/P

Rev

Enrico 14 AMD
Sheet
1

64

A00
of

109

5

4

3

SSID = Wireless

2

1

Mini Card Connector(802.11a/b/g/n)

D

D

W LAN1

3D3V_S0

53

1
C6505

C6506

2

2

SCD1U16V2KX-3GP

DY

1

27 BLUETOOTH_EN
SCD1U16V2KX-3GP

1

X01

SC10U6D3V5KX-1GP

1
C6504

2

SC10U6D3V5KX-1GP

2

C6503

2

C6502
SCD1U16V2KX-3GP

1

1D5V_S0

1

3D3V_S0

AFTP6505
1
2
DY 0R2J-2-GP
R6535
18 CLK_PCIE_W LAN_REQ#
17 CLK_PCIE_W LAN#
17 CLK_PCIE_W LAN

27 E51_RXD
27 E51_TXD

5V_S5

17 PCIE_RXN2
17 PCIE_RXP2

1

1

W LAN_ACT
C6501

17 PCIE_TXN2
17 PCIE_TXP2

C6508

2

SC220P50V2KX-3GP

DY

SCD1U16V2KX-3GP

2

DY

C

W LAN_ACT
BT_ACT

1

3D3V_S0
2010/07/09 Pop R6510 for Wifi/BT combo module
1
2
27 BLUETOOTH_EN
0R3J-0-U-GP
R6510
5V_S5

1
R6503

2

+5V_MINI_DEBUG

DY 0R3J-0-U-GP

NP1
2

3
5
7
9
11
13
15

4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
NP2

1D5V_S0

W IFI_RF_EN 27
PLT_RST# 17,31,71,83
3D3V_S0
1D5V_S0
PCH_SMBCLK 14,15
PCH_SMBDATA 14,15
USB_P1USB_P1+

0726
X01
LED_W LAN#
LED_W PAN#

1D5V_S0

C

LED_W LAN# 68
LED_W PAN# 68

3D3V_S0

54
SKT-MINI52P-41-GP

X02

18 USB_PP1

1

R6406

2

USB_P1+

0R0402-PAD

X01

B

2

B

1

X01

C6509
SC6D8P50V2DN-GP

X01
1

R6405

2

USB_P1-

X01

2

0R0402-PAD

1

18 USB_PN1

A

C6510
SC6D8P50V2DN-GP

05/19 Add Common Mode Choke
2010/07/16 Change CMC L6401 to smaller 69.10118.001 (the same same as other CMCs on MB) and rename L6401 to TR6501.
Change R6406,R6405 to 0R 0402 size



A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

MINICARD(WLAN)/ITP CONN

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

A00

Enrico 14 AMD
Sheet
1

65

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

WWAN

Rev

Enrico 14 AMD
Sheet
1

66

A00
of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD

A00

Sheet
1

67

of

109

5

4

3

X01
1

1

2
0R0402-PAD

SSID = User.Interface

5V_S5

R1

DY
E
R2
PDTC124EU-1-GP

PLED1

1

3

B

LED_PW R

C

K

R6806
1
2 FPOW ER_LED_A 2
330R2J-3-GP

Q6801

A

FRONT POWER LED

LED-W -27-GP

83.01221.R70

27 PW RLED#
19 SATA_LED#

D

2

R6834

D

5V_S0
Q6805

HDLED1

R2

R6812
1
2
330R2J-3-GP

SATA_LED_R

C

3

E

R1

B

HDD_LED_A

PDTA143ET-GP

SATA HDD LED(White)

1A

K2

83.01221.R70

84.00143.M11

LED_PW R

EC6801 SC220P50V2KX-3GP
1
2

SATA_LED_R

EC6810 SC220P50V2KX-3GP
1
2

LED-W -27-GP

DY

DY

EC6807 SC220P50V2KX-3GP
W HITE_LED_BAT# 1
2

DY

EC6809 SC220P50V2KX-3GP
AMBER_LED_BAT#
1
2

X01

DY

Battery LED2(WHITE_LED)

1

R6835

2
0R0402-PAD
R6801

Q6807

B

R1

W HITE_LED_BAT# 1

C

DY

E
R2
PDTC124EU-1-GP

C

WHITE

BAT_W HITE#

2

LED-OW -3-GP

330R2J-3-GP

5V_S5

1

84.00124.H1K

27 BATT_W HITE_LED#
27 CHG_AMBER_LED#

C

3

2
1

R6836

CHLED1

2
0R0402-PAD

Q6808

B

R1

AMBER_LED_BAT# 2 R6803

C

DY

BAT_AMBER#

1

499R2F-2-GP

E

83.00326.G70
AMBER

R2
PDTC124EU-1-GP

84.00124.H1K

Battery LED1(AMBER_LED)
Wireless LED

5V_S0

D6831

B

Q6831
R2

W LAN_LED_B

1

W LED1

84.00144.P11

2
DY 0R2J-2-GP

DY

2

3

330R2J-3-GP
EC6832
SC220P50V2KX-3GP

1
R6839

2

1

R6833
W LAN_LED_R 1

C

PDTA144VT-GP
BAW 56-2-GP

27 W LAN_LED#

B

1

65 LED_W PAN#

LED-W -27-GP

2

W LAN_LED#_R

R1

3

E
A

2

65 LED_W LAN#

K

B

83.01221.R70

Power button
1A

A

27 KBC_PW RBTN#

KBC_PW RBTN#_C

1
2
R6802
100R2J-2-GP

PW RBT1
5
1B

2A
3A
4A

2B
3B
4B
6

A



Wistron Corporation

ACES-CONN8G-GP
AFTP6801

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

1
1

AFTP6802
Title

20.K0464.004
5

4

www.bblianmeng.com
3

2

LED Bard/Power Button

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet
1

68

of

109

5

3

2

1

SSID = KBC

KB1

AFTP6901

D

KB_DET# 27
AFTP6902
AFTP6903
AFTP6904
AFTP6905
AFTP6906
AFTP6907
AFTP6908
AFTP6909
AFTP6910
AFTP6911
AFTP6912
AFTP6913
AFTP6914
AFTP6915
AFTP6916
AFTP6917
AFTP6918
AFTP6919
AFTP6920
AFTP6921
AFTP6922
AFTP6923
AFTP6924
AFTP6925
AFTP6926

1

JAE-CON30-7-GP

5V_S0

27

KCOL[0..16]

27

RN6901
SRN10KJ-5-GP

C6901
SCD1U10V2KX-5GP

2

KROW [0..7]

1

5V_S0

TPAD1

TPCLK
TPDATA

C6902
SC33P50V2JN-3GP

AFTP6927

1

1

27
27

4A
3A
2A

DY DY
2

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2

KROW 7
KROW 6
KROW 4
KROW 2
KROW 5
KROW 1
KROW 3
KROW 0
KCOL5
KCOL4
KCOL7
KCOL6
KCOL8
KCOL3
KCOL1
KCOL2
KCOL0
KCOL12
KCOL16
KCOL15
KCOL13
KCOL14
KCOL9
KCOL11
KCOL10
CAP_LED_R

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32

C

TouchPad Connector

1
31
1

2
1

D

3
4

X01

4

1

C6903
SC33P50V2JN-3GP

1A

6
4B
3B
2B
1B
5

ACES-CONN8G-GP

CAP_LED_R

C

20.K0464.004

AFTP6957

AFTP6972

1

AFTP6929
AFTP6930
AFTP6931

20.K0565.030

1
1
1

5V_S0
TPCLK
TPDATA

20101116 X02 Modify:
Change R6906 to 1K from 390ohm for
fine tune LED illumination.
20101118 X02:
Dell recommand: change all white LEDs resistor to 620 ohm.
20101202 X02:
Dell recommand: change all white LEDs resistor to 604 ohm.

B

5V_S5

Q6902
R2

R6905

2

B

R6906
R1

1

27 CAP_LED#

B

CAP_LED_R

E
C

CAP_LED_Q

15KR2J-1-GP

1

2
604R2F-2-GP

CAP_LED_R

PDTA143ET-GP

84.00143.M11
2nd = 84.02143.011

3rd CAP_LED_1
= 84.00143.N11

1
R6907

2
DY100R2J-2-GP

CAP_LED:(X01 Low actived)
Connect to KB driving internal LED directly.(MAX 25mA)



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Key Board/Touch Pad

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet
1

69

of

109

5

4

3

2

1

SSID = Hall.Sensor
D

D

1

3D3V_S5

3D3V_S5
HALL1

C

DY

NP2
6
7
8
9

C

LID_CLOSE# 27,82
1

5
4
3
2

DY R6901
100KR2J-1-GP
2

-1_0623

10
NP1

ACES-CONN10C-2-GP

DY
2

1

C6904
SCD047U16V2KX-1-GP

20.F1513.010

B

B



Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
5

4

www.bblianmeng.com
3

Document Number

Hall Effect Sensor

Enrico 14 AMD

Date: Friday, April 22, 2011
2

Sheet

Rev

A00
70

of
1

109

A

5

4

3

2

1

SSID = Debug
RN7102
17,27
17,27
17,27
17,27

D

1
2
3
4

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

DY

LPC_AD3_R_DB1
LPC_AD2_R_DB1
LPC_AD1_R_DB1
LPC_AD0_R_DB1

8
7
6
5

X01

3D3V_S0

DB1

SRN0J-7-GP

1 DY
R7107
0R2J-2-GP

17,27 LPC_FRAME#

D

2
17,31,65,83 PLT_RST#
R7102 1

17,21 CLK_PCI_LPC

DY

LPC_AD0_R_DB1
LPC_AD1_R_DB1
LPC_AD2_R_DB1
LPC_AD3_R_DB1
LPC_FRAME#_R
2 0R2J-2-GP

X02
Layout close to SB

1
2
3
4
5
6
7
8
9
10
11
12

DY

MLX-CON10-7-GP

20.D0183.110
C

C

PCB Footprint = PAD-10P-177042
DY HDT+

HDT+ Connectors

1D8V_S0

0R2J-2-GP R7101 1
DBRDY3
DBRDY2
DBRDY1

6 APU_TRST#
B

DY

1
1

TP7101
TP7102

TPAD14
TPAD14

2APU_TRST#_R
1
1
1
1

TP7103
TP7104
TP7105
TP7106

TPAD14
TPAD14
TPAD14
TPAD14

1

TP7107

TPAD14

TPAD14
TPAD14
TPAD14
TPAD14
TPAD14
TPAD14
TPAD14
TPAD14
TPAD14
TPAD14

TP7108
TP7109
TP7110
TP7111
TP7112
TP7113
TP7114
TP7115
TP7116
TP7117

1
1
1
1
1
1
1
1
1APU_TEST19_PLLTEST0_R1
1APU_TEST18_PLLTEST1_R1

DY

1
2
3
4

B

APU_TEST19_PLLTEST0 6
APU_TEST18_PLLTEST1 6

DY
CRB:placed 0-ohm
checklist:if both SCAN and HDT+ header are implement
placed 15-ohm

RN7101
8
7
6
5

DY

APU_TCK 6
APU_TMS 6
APU_TDI 6
APU_TDO 6
H_CPUPWRGD 6,17,36,42
APU_RST_L_BUF 6
APU_DBRDY 6
APU_DBREQ# 6
0R2J-2-GP
2 R7105
0R2J-2-GP
2 R7106

DBRDY3
DBRDY2
DBRDY1

SRN10KJ-6-GP



Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
5

4

www.bblianmeng.com
3

Document Number

Dubug connector

Enrico 14 AMD

Date: Friday, April 22, 2011
2

Sheet

Rev

A00
71

of
1

109

A

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

RESERVED

Rev

Enrico 14 AMD

A00
Sheet
1

72

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

73

A00
of

109

5

4

3

2

1

SD/XD/MS Card Reader

SSID = SDIO

D

D

3D3V_CARD_S0
CARD1

11
4

1

For EMI

C7405
SC2D2U6D3V3KX-GP

2

1
2

C7404
SCD1U10V2KX-5GP

1

C7403
SCD1U10V2KX-5GP

DY

2

1

DY

C7402
SCD1U10V2KX-5GP

2

DY

2

1

C7401
SCD1U10V2KX-5GP

3D3V_CARD_S0

32 XD_D0/SD_CLK/MS_D2

MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3

12
13
10
7

MS_INS
MS_BS
MS_SCLK

8
15
5

GND
GND

23
24

SD_GND

21

MS_VSS
MS_VSS

2
16

SD_VSS/MMC_VSS1
SD_VSS/MMC_VSS2

9
17

SD_VDD/MMC_VDD
MS_VCC

20
3

SD_CD
SD_CD/DAT3/MMC_RSV

14
6

SD_CLK/MMC_CLK
SD_CMD/MMC_CMD

32 XD_CLE/SD_D0/MS_D7
32 XD_CE#/SD_D1
32 XD_D5/SD_D2/MS_D5

18
19
1

SD_DAT0/MMC_DAT
SD_DAT1
SD_DAT2

32 XD_RDY/SD_W P/MS_CLK

22

SD_WP/SW

32 XD_W E#/SD_CD#
32 XD_D4/SD_D3/MS_D1
R7407

33R2J-2-GP
2
1
32 XD_D2/SD_CMD

XD_D0/SD_CLK/MS_D2_R

NP1
NP2

NP1
NP2

XD_D1/SD_D5/MS_D0
XD_D4/SD_D3/MS_D1

XD_D0/SD_CLK/MS_D2_R

32
32

XD_ALE/SD_D7/MS_D3 32
XD_RE#/MS_INS# 32
XD_D6/MS_BS 32
XD_RDY/SD_W P/MS_CLK

32

CARD-PUSH-22P-GP

20.I0110.021

C

C

0810 Vendor Recommand

1
2

EC7410
SC6D8P50V2DN-GP

1
2

EC7409
SC6D8P50V2DN-GP

1
2

EC7408
SC6D8P50V2DN-GP

1
2

EC7407
SC6D8P50V2DN-GP

1
2

EC7406
SC6D8P50V2DN-GP

1
2

EC7405
SC6D8P50V2DN-GP

1
2

EC7404
SC6D8P50V2DN-GP

1
2

1
2

EC7403
SC4D7P50V2CN-1GP

For EMI

EC7402
SC6D8P50V2DN-GP

1
2

B

EC7401
SC6D8P50V2DN-GP

XD_ALE/SD_D7/MS_D3
XD_D1/SD_D5/MS_D0
XD_CLE/SD_D0/MS_D7
XD_CE#/SD_D1
XD_D5/SD_D2/MS_D5
XD_D4/SD_D3/MS_D1
XD_D2/SD_CMD
XD_D0/SD_CLK/MS_D2_R
XD_W E#/SD_CD#
XD_RDY/SD_W P/MS_CLK

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

CARD Reader Connector

Size
A3

Document Number

Date:

Friday, April 22, 2011

Enrico 14 AMD

Rev

A00
Sheet
1

74

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Express Card

Rev

Enrico 14 AMD
Sheet
1

A00
75

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

76

A00
of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

77

A00
of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
5

4

www.bblianmeng.com
3

Document Number

Reserved

Rev

Enrico 14 AMD

Date: Friday, April 22, 2011
2

Sheet

78

A00
of

1

109

A

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

79

A00
of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Reserved

Rev

Enrico 14 AMD
Sheet
1

80

A00
of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

5

4

www.bblianmeng.com
3

Date:
2

UNUSED PARTS/EMI Capacitors
Document Number

Enrico 14 AMD
Friday, April 22, 2011

Rev

A00

Sheet
1

81

of

109

5

4

3

2

1

X01
X02

SSID = USB
USB_PN2_R
D

R8203 1

2

USB_PP2_R R8204 1

2

0R0603-PAD
0R0603-PAD

USB20_VCCB

USB_PN2 18
IOBD1

USB_PP2 18

D

17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

USB_PN2_R
USB_PP2_R
USB_PN6_R
USB_PP6_R

X02
USB_PN6_R

R8201 1

USB_PP6_R R8202 1

2
2

0R0603-PAD
0R0603-PAD

USB_PN6 18
USB_PP6 18

18
PTW O-CON16-1-GP

20.K0429.016
C

C

IOBD2

17

SSID = AUDIO

1

29,58 INT_MIC_L_R

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

29 AUD_HP1_JACK_L2
29 AUD_HP1_JACK_R2
29 MIC_IN_L
29 MIC_IN_R
29 EXT_MIC_JD#
29 AUD_HP1_JD#
B

27,70 LID_CLOSE#
3D3V_S5

B

18
AUD_AGND

PTW O-CON16-1-GP

20.K0429.016


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

IO Board Connector

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet
1

82

of

109

5

4

SSID = VIDEO

3

2

CONFIGURATION STRAPS

1 OF 7

VGA1A

1

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 3K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

D

4 PEG_TXP0
4 PEG_TXN0

PEG_TXP0
PEG_TXN0

AF30
AE31

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

C8306
AH30 PEG_C_RXP0
C8305
AG31 PEG_C_RXN0

1
2
DIS_PX
1
2
DIS_PX

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

4 PEG_TXP1
4 PEG_TXN1

PEG_TXP1
PEG_TXN1

AE29
AD28

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

C8303
AG29 PEG_C_RXP1
C8304
AF28 PEG_C_RXN1

1
2
DIS_PX
1
2
DIS_PX

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

4 PEG_TXP2
4 PEG_TXN2

PEG_TXP2
PEG_TXN2

AD30
AC31

PCIE_TX2P
PCIE_TX2N

C8310
AF27 PEG_C_RXP2
C8309
AF26 PEG_C_RXN2

1
2 SCD1U10V2KX-5GP
DIS_PX
1
2 SCD1U10V2KX-5GP
DIS_PX

4 PEG_TXP3
4 PEG_TXN3

PEG_TXP3
PEG_TXN3

AC29
AB28

PCIE_TX3P
PCIE_TX3N

C8308
AD27 PEG_C_RXP3
C8307
AD26 PEG_C_RXN3

1
2 SCD1U10V2KX-5GP
DIS_PX
1
2 SCD1U10V2KX-5GP
DIS_PX

PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N

AA29
Y28

PCIE_RX5P
PCIE_RX5N

Y30
W31

PCIE_RX6P
PCIE_RX6N

W29
V28

PCIE_RX7P
PCIE_RX7N

V30
U31

PCIE_RX8P
PCIE_RX8N

U29
T28

PCIE_RX9P
PCIE_RX9N

T30
R31

PCIE_RX10P
PCIE_RX10N

C

PCI EXPRESS INTERFACE

AB30
AA31

R29
P28

PCIE_RX11P
PCIE_RX11N

P30
N31

PCIE_RX12P
PCIE_RX12N

N29
M28

PCIE_RX13P
PCIE_RX13N

PCIE_TX4P
PCIE_TX4N

AC25
AB25

PCIE_TX5P
PCIE_TX5N

Y23
Y24

PCIE_TX6P
PCIE_TX6N

AB27
AB26

PEG_RXP0 4
PEG_RXN0 4
PEG_RXP1 4
PEG_RXN1 4

PIN

TX_PWRS_ENB

GPIO0

Transmitter Power Savings Enable
0: 50% Tx output swing 1: Full Tx output swing

X

1

GPIO1

PCIE TRANSMITTER DE-EMPHASIS ENABLED
0:Tx de-emphasis disabled 1:Tx de-emphasis enabled

X

1

GPIO2

0:Advertises the PCIe device as 2.5GT/s capable at power on.
1:Advertises the PCIe device as 5.0GT/s capable at power on.

0

0

GPIO5_AC_BATT

GPIO5

optional input allow the system to request a fast
power reduction by setting GPIO5 to low.

?

0

GPIO8_ROMSO

GPIO8

RESERVED

0

0

TX_DEEMPH_EN

PEG_RXP2 4
PEG_RXN2 4

BIF_GEN2_EN_A

PEG_RXP3 4
PEG_RXN3 4

VGA_DIS

PCIE_TX7P
PCIE_TX7N

Y27
Y26

PCIE_TX8P
PCIE_TX8N

W24
W23

PCIE_TX9P
PCIE_TX9N

V27
U26

PCIE_TX10P
PCIE_TX10N

U24
U23

PCIE_TX11P
PCIE_TX11N

T26
T27

PCIE_TX12P
PCIE_TX12N

T24
T23

PCIE_TX13P
PCIE_TX13N

P27
P26

0:VGA Controller capacity enabled
1:The device won't be recognized as the system's VGA controller

GPIO9

ROMIDCFG[2:0]

GPIO21

X

X

RESERVED

X

0

X

0

RSVD

H2SYNC

RESERVED

0

0

RSVD

GENERICC

RESERVED

0

0

X

1

X

1

AUD[1]

HSYNC

AUD[0]

VSYNC

AUD[1:0]:11-Audio for both DisplayPort and HDMI

L29
K30

2010/06/10
Move CAPs close to CPU

2010/06/11 PIN
Need to check

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

P24
P23

R8301

1

85 TX_DEEMPH_EN

R8302

1

85 BIF_GEN2_EN_A

R8303

85 TX_PW RS_ENB

M27
N26

3D3V_VGA_S0

AK30
AK32

PCIE_REFCLKP
PCIE_REFCLKN

1V_VGA_S0
CALIBRATION

1DIS_PX 2 PW RGOOD
R8314
10KR2F-2-GP
R8316

ATI_RST#
1
2 VGA_RST#
0R0402-PADDIS_PX

N10

Y22 PCIE_CALRP

PCIE_CALRN

AA22 PCIE_CALRN

1
R8321

1
R8315

2
DIS_PX
2
DIS_PX

1K27R2F-L-GP
2KR2F-3-GP

3KR2J-2-GP

85 VGA_DIS
85 CONFIG0

R8306

1

2
DIS_PX

85 CONFIG1

R8307

1

R8308

1

DY
DY

2 10KR2J-3-GP

85 CONFIG2

ROBSON-GP-U

C8312
SC47P50V2JN-3GP

2

DY

71.ROBSO.M01

R8330
0R2J-2-GP
2
DY 1

X01

84 TESTEN

DY
DY

B

2 10KR2J-3-GP

17,86 1D5V_VGA_PW OK

PLT_RST#

93 1D8V_S0_VGA_PG

R8324
1
2
0R0402-PAD DIS_PX

C8311
SCD1U10V2KX-4GP

2

DY

2
3

0820

6,17 APU_RST#
5

R8322
2

DY

1 0R2J-2-GP

85 JTAG_TCK_VGA

R8329 1

1

DY

2 10KR2J-3-GP

R8310

1

DY

2 10KR2J-3-GP

85 GPIO5_AC_BATT

R8318

ATI_RST#

1

R8317

1

85 GPIO21_BB_EN

1

DY
DY
DY

DY

2 10KR2J-3-GP

Signal

Normal
mode

TESTEN

"1"(PU) "1"(PU)

"0"(PD)

"0"(PD) "1"(PU)

NC

JTAG_TRST#
R8313

2 10KR2J-3-GP

DY

JTAG_TCK

2 10KR2J-3-GP
2 10KR2J-3-GP

JTAG_TMS

CLK

Debug
mode

pilot run
mode

"1"(PU)

NC

"1"(PU) "1"(PU)

NC

2 10KR2J-3-GP

0R2J-2-GP


B
VCC

ADIS_PX
Y
GND

PE_GPIO0

U8302
U8302_Y

4

73.01G08.L04
2ND = 73.7SZ08.DAH

17

PE_GPIO0

1
2
3

B
VCC

5

Y

4

DIS_PX
A

ATI_RST#

4

dGPU mode

H

IGPU

L

ATI_RST# 85

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GND

74LVC1G08GW -1-GP

IGPU with BACO

73.01G08.L04
2ND = 73.7SZ08.DAH

R8331 1 DIS_PX2 0R0402-PAD

A

3D3V_VGA_S0

5

74LVC1G08GW -1-GP

17,31,65,71 PLT_RST#

1

R8326 1

JTAG SIGNAL OPTION

2 10KR2J-3-GP

U8301

1
1

A

DY

2

3D3V_VGA_S0

85 JTAG_TRST#_VGA

10KR2J-3-GP

R8309

85 BIOS_ROM_EN

R8327
1DIS_PX 2 5K11R2F-L1-GP

2 10KR2J-3-GP

Colay with Seymour-XT-S3
(71.SEYMR.M01)

R8323

1 10KR2J-3-GP

DY

3KR2J-2-GP
2010/07/13 Stuff for 5.0GT/S
1 DIS_PX
2 10KR2J-3-GP

1

2 10KR2J-3-GP

DY

R8328
2

2
DIS_PX

1

50,85 VGA_CRT_HSYNC

PERST#

2
DIS_PX

R8305

50,85 VGA_CRT_VSYNC

R8325

1

85 JTAG_TMS_VGA

1

AL27

PWRGOOD

PCIE_CALRP

STRAPS

R8304

85 GPIO8_ROMSO
CLOCK

17 CLK_PCIE_VGA
17 CLK_PCIE_VGA#

C

2010/06/11

DIS_PX

B

0

X

VIP Device Strap Enable indicates to the software driver that it sense
whether or not a VIP device is connected on the VIP Host interface.

V2SYNC

0
0 0 1
(256MB)

0

0:Disable external BIOS ROM device
1:Enable external BIOS ROM device

BIOS_ROM_EN GPIO_22_ROMCSB
VIP_DEVICE_STRAP_EN

0

BIOS_ROM_EN=1, Config[2:0] defines the ROM type
BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size

GPIO[13:11]

GPIO21_BB_EN

D

3D3V_VGA_S0

M30
L31

PLATFORM
SETTING

RECOMMEND

DESCRIPTION OF DEFAULT SETTINGS

STRAPS

H

Size

GPU_PEG/STRAPPING(1/5)

Document Number

A3

www.bblianmeng.com
3

Date:
2

Sheet
1

Rev

A00

Enrico 14 AMD
Friday, April 22, 2011

83

of

109

5

4

3

2

1

SSID = VIDEO
K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

MVREFDA
MVREFSA

K26
J26

MVREFDA
MVREFSA

MEM_CALRN0
TESTEN

J25
K7

MEM_CALRN0
TESTEN

MEM_CALRP1/DPC_CALR
MEM_CALRP0

J8
K25

MEM_CALRP1/DPC_CALR
MEM_CALRP0

L10

DRAM_RST

K8
L7

CLKTESTA
CLKTESTB

R8411
40D2R2F-GP

2

DIS_PX

C8402
SCD1U10V2KX-5GP

Rb

R8415
100R2F-L1-GP-U

DIS_PX

C8403
SCD1U10V2KX-5GP

89 MDA[32..63]

DIS_PX

2

2

2

DIS_PX

1

R8414
100R2F-L1-GP-U

DIS_PX

MVREFSA

2

1

MVREFDA

C

DDR3/GDDR3 Memory Stuff Option (ROBSON-S3/SEYMOUR-XT-S3)
DDR5

DDR3

MVDDQ

1.5V

1.5V/1.8V

Ra

40.2R

40.2R

Rb

100R

100R

DPC_CALR (Park/Robson-S3):
Analog calibration.
Connect DPxx_CALR to GND through a 150-Ω (1%) resistor.

1D5V_VGA_S0

B

R8403
R8408

1
1

2
DIS_PX
2
DIS_PX

150R2F-1-GP
R8407 1 DIS_PX
2

243R2F-2-GP MEM_CALRN0
MEM_CALRP0
243R2F-2-GP

83 TESTEN

R_MEM_2

R_MEM_1

R8405

2
DIS_PX

R8402
DRAM_RST_1 1

C8401
SC120P50V2JN-1GP
DIS_PX

1

C_MEM

R8409
5K1R2F-2-GP

R_MEM_3

TPAD14 TP8401
TPAD14 TP8402

1CLKTESTA
1CLKTESTB

MAA0 88,89
MAA1 88,89
MAA2 88,89
MAA3 88,89
MAA4 88,89
MAA5 88,89
MAA6 88,89
MAA7 88,89
MAA8 88,89
MAA9 88,89
MAA10 88,89
MAA11 88,89
MAA12 88,89
MAA13 88,89
A_BA0 88,89
A_BA1 88,89
A_BA2 88,89

DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7

E32
E30
A21
C21
E13
D12
E3
F4

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

RDQSA_0
RDQSA_1
RDQSA_2
RDQSA_3
RDQSA_4
RDQSA_5
RDQSA_6
RDQSA_7

H28
C27
A23
E19
E15
D10
D6
G5

QSAP_0
QSAP_1
QSAP_2
QSAP_3
QSAP_4
QSAP_5
QSAP_6
QSAP_7

88
88
88
88
89
89
89
89

WDQSA_0
WDQSA_1
WDQSA_2
WDQSA_3
WDQSA_4
WDQSA_5
WDQSA_6
WDQSA_7

H27
A27
C23
C19
C15
E9
C5
H4

QSAN_0
QSAN_1
QSAN_2
QSAN_3
QSAN_4
QSAN_5
QSAN_6
QSAN_7

88
88
88
88
89
89
89
89

ODTA0
ODTA1

L18
K16

ODTA0
ODTA1

CLKA0
CLKA0#

H26
H25

CLKA0
88
CLKA0# 88

CLKA1
CLKA1#

G9
H9

CLKA1
89
CLKA1# 89

RASA0#
RASA1#

G22
G17

RASA0# 88
RASA1# 89

CASA0#
CASA1#

G19
G16

CASA0# 88
CASA1# 89

CSA0#_0
CSA0#_1

H22
J22

CSA0#_0 88

CSA1#_0
CSA1#_1

G13
K13

CSA1#_0 89

CKEA0
CKEA1

K20
J17

CKEA0
CKEA1

88
89

WEA0#
WEA1#

G25
H10

W EA0#
W EA1#

88
89

PX_EN

AB16

RSVD#G14

71.ROBSO.M01

50R

R8419
51R2J-2-GP

50R

R_MEM_3

5K

5K

C_MEM

120pF

120pF

DY DY



A

DY

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

R8418
51R2J-2-GP

www.bblianmeng.com
3

86

2010/07/06
Schematics check list:
A pull-down resistor is required.

Title

floating (do not populate the capacitors and resistors).

4

PX_EN

Colay with Seymour-XT-S3
(71.SEYMR.M01)

For normal GPU operation, these signals can be left
5

B

R8421

C8406
SCD1U10V2KX-5GP
CLKTESTB
1
2

10R

2

R_MEM_2

88
89

DIS_PX10KR2J-3-GP

DY

1

10R

Place all these components very close to GPU
(Within 25mm) and keep all component close
to each Other (within 5mm) except R_MEM_2
1

R_MEM_1

C

G14

2

Designator
A

For Robson

88
88
88
88
89
89
89
89

R8420
PX_EN_R
1
2
0R0402-PADDIS_PX

C8407
SCD1U10V2KX-5GP
CLKTESTA
1
2

For SEYMOUR

D

ROBSON-GP-U

DIS_PX

2

are an example only. The Series R and || Cap values
will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board
to pass Reset Signal Spec.

10R2F-L-GP

2

51R2J-2-GP

basic topology should be used for DRAM_RST for
** This
DDR3/GDDR3/GDDR5.These Capacitors and Resistor values

DRAM_RST

2
DIS_PX

1

88,89 MEM_RST

1

DIS_PX

K17
J20
H23
G23
G24
H24
J19
K19
J14
K14
J11
J13
H11
G20
J16
L15
G11

2

Ra

2
1

Rb

1

R8410
40D2R2F-GP

DIS_PX

1

1

Ra

1D5V_VGA_S0

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14/BA0
MAA_15/BA1
MAA_BA2

1

PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC

MEMORY INTERFACE

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

D

1D5V_VGA_S0

3 OF 7

VGA1C

88 MDA[0..31]

2

Size

GPU Memory(2/5)

Document Number

A3
Date:

Rev

A00

Enrico 14 AMD
Friday, April 22, 2011

Sheet
1

84

of

109

4

3

VGA1B

Description

X02

DPB

AC6
AC5

C8528
1

C8527
1

2

2

U1
W1
U3
Y6
AA1

DIS_PX

0723 Add SMBUS

ROBSON-GP-U

SCL
SDA

0820

I2C

2

TPAD14 TP8505

1

R8524 2
1
DIS_PX
10KR2J-3-GP

83 GPIO8_ROMSO
83 VGA_DIS
83 CONFIG0
83 CONFIG1
83 CONFIG2

GPIO_6,GPIO_15_PWRCNTL_0,GPIO_16_SSIN,GPIO_20_PWRCNTL_1:
92 PWRCNTL_0
Voltage control signals for the core (VDDC and VDDCI).
TPAD14-GP
At Reset, these signals will be inputs with weak internal pull-down resistors.
VBIOS can define all voltage control signals to be either 3.3-V or open drain outputs (all signals
TPAD14-GP
must be the same type). The output state (high/low) of these signals is programmable for each PowerPlay state.

TP8502

1

TP8506

1

92 PWRCNTL_1
83 GPIO21_BB_EN
83 BIOS_ROM_EN
18 PEG_CLKREQ#

DY

23KR2J-2-GP

PWRCNTL_0

83 JTAG_TRST#_VGA

DY

23KR2J-2-GP

PWRCNTL_1

83 JTAG_TCK_VGA
83 JTAG_TMS_VGA

R
R#

TP8511

1

TPAD14 TP8503

1

TPAD14 TP8504
1D8V_VGA_S0TPAD14 TP8508

1
1

JTAG_TDO_VGA
RSVD

1

TPAD14
R8515 TP8509
499R2F-2-GP

PLACE VREFG DIVIDER AND CAP
CLOSE TO ASIC

GEN_A
GEN_B

AB13
W8
W9
W7
GENERICE_HPD4 AD10

1

DIS_PX

1D8V_VGA_S0

DPLL_PVDD

AC14

C8516

1

1

DIS_PX

AC16

DIS_PX

1

1

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4

DY
DY

20R2J-2-GP NC#AC22/XO_IN AC22
20R2J-2-GP NC#AB22/XO_IN2AB22

1

VDD2DI_GPU
AC19_GND1ROB
2

AE20

0R2J-2-GP
A2VDD_GPU

AE17

A2VDDQ_GPU

1

1

50 mA

R8504 2

130 mA
1.5 mA

4

R8508 2
R8505 2

ROB
ROB
ROB

AVDD_A2VDDQ
1 0R2J-2-GP

AVDD_A2VDDQ

B

1 0R2J-2-GP

A2VDD

1 0R2J-2-GP

AVDD_A2VDDQ

C8508

R2SET

1

ROB

XTALOUT

XTAL-27MHZ-85-GP
5

1
C8525

DY

AE6
AE5

DDC1CLK
DDC1DATA

DPLL_PVDD
DPLL_PVSS

VGA_CRT_DDCCLK 50
VGA_CRT_DDCDATA 50

AVDD_A2VDDQ

AD2
AD4

AUX1P
AUX1N

(1.8V@2mA A2VDDQ)

AC11
AC13

DDC2CLK
DDC2DATA

XTALIN
XTALOUT

C8510
AD13
AD11

AUX2P
AUX2N

0723 Add SMBUS

DY

SCD1U10V2KX-5GP

AUXP PD 100K
AUXN PU 100K
Draw on EDP circuit page

AE16
AD16

DDCCLK_AUX5P
DDCDATA_AUX5N
NC#AC22/XO_IN
NC#AB22/XO_IN2

R5
AD17
AC17

AC1
AC3

DDC6CLK
DDC6DATA

AD20
AC20

NC#AD20/DDCCLK_AUX3P
NC#AC20/DDCDATA_AUX3N

RN8501
SRN4K7J-8-GP

(3.3V@130mA A2VDD)

DIS_PX

2

71.ROBSO.M01
GPIO_VGA_04_CLK

Q8503
1
2
3

6

SML1_CLK 6,27

DIS_PX
5

DY

C8513
SCD1U10V2KX-5GP
A

Wistron Corporation

2N7002KDW-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SML1_DATA 6,27

2
SC12P50V2JN-3GP

www.bblianmeng.com

DY



84.2N702.A3F
2nd = 84.DM601.03F

3

C8512

4

X01
4

DY

A2VDD
R8509
1
2
0R0402-PADDIS_PX

TS_FDO
TSVDD
TSVSS

C8511

3D3V_VGA_S0
3D3V_VGA_S0

DPLUS
DMINUS

ROBSON-GP-U

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

0820

M92-S2/M93-S3

DPLL_VDDC

C8509

2

DIS_PX
3

DY
SCD1U10V2KX-5GP

R8501
AG13

GPIO_VGA_03_DATA
2

80.30034.641
2nd 80.30034.651
3rd 80.30034.681

(1.8V@100mA VDD2DI)

4
3

FAN_PWM_C

C8507

DY

AE19

A2VSSQ

Colay with Seymour-XT-S3

DIS_PX

DIS_PX

AD19
AC19

(71.SEYMR.M01)
Clock Input Configuraiton -GDDR3/DDR3
a) 27MHz crystal connected to XTALIN or XTALOUT or
b) 27MHz (1.8V) oscillator connected to XTALIN or
c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)

X8501
2XTALIN
SC12P50V2JN-3GP

1

C8522

DIS_PXSC1U6D3V2KX-GP
DIS_PX
2

1
2

C8520 DY
SC4D7U6D3V3KX-GP

1MR2F-GP

C8506

DY

AL13
AJ13

VREFG

THERMAL
T4
T2

2

TPAD14 TP8512

(1.8V@20mA TSVDD)
C8521

1DIS_PX 2

C8524 1

C8502

DY

TSVDD
L8504 DIS_PX
1
2
BLM15BD121SS1D-GP

R8502

X01

AVDD_A2VDDQ

AH12
AM10
AJ9

A2VDDQ/NC#AE17

DIS_PX

2010/07/06

AVSSQ

AVSSQ

AK10
AL9

VDD2DI/NC#AD19
VSS2DI/NC#AC19

HPD1

1

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP
2

R8510 1
R8511 1

C8523
SC2200P50V2KX-2GP

A

2

DIS_PX

C8504

DY

(1.8V@100mA VDD1DI)

H2SYNC
V2SYNC

28 P2800_VGA_DXP

28 P2800_VGA_DXN
1D8V_VGA_S0
2010/07/06
Schematics check list:
A 1-M ohm resistor must be connected
between XTALIN and XTALOUT when a crystal is used.

R8517
1
0R0402-PAD

AVDD_A2VDDQ

AVSSQ

C8503

DY

2

1
2

DIS_PX

AM28
AK28

C8501

DY

2
499R2F-2-GP

AL11
AJ11

C/NC#AH12
Y/NC#AM10
COMP/NC#AJ9

DDC/AUX
AD14

DIS_PX

1
R8514
AVDD_A2VDDQ

715R2F-GP

XTALIN
XTALOUT

(1.8V@65mA AVDD)

AM12
AK12

R2SET/NC#AG13

C8519

C

DIS_PX

GPU_RSET

AVSSQ

G2/NC#AL11
G2#/NC#AJ11

PLL/CLOCK

2
BLM18PG471SN1D-GP

X01

R8507
1
2
0R0402-PADDIS_PX

50,83
50,83

AE23
AD23

R2/NC#AM12
R2#/NC#AK12

DIS_PX

DPLL_VDDC

C8518

VGA_CRT_HSYNC
VGA_CRT_VSYNC

1D8V_VGA_S0

50
50

M92-S2/M93-S3

DAC2

(1.0V@125mA DPLL_VDDC)

C8517 DY
SC4D7U6D3V3KX-GP

AH26
AJ27

AG24
AE22

AVDD
AVSSQ
VDD1DI
VSS1DI

B2/NC#AK10
B2#/NC#AL9

M92-S2/M93-S3

1V_VGA_S0
1
L8506

VGA_CRT_BLUE

AD22

RSET

A2VDD/NC#AE20

C8514
SCD1U10V2KX-5GP

AF14
AE14

DIS_PX

HSYNC
VSYNC

JTAG_TRST#
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
RSVD#AF24

2

DIS_PX

VGA_CRT_GREEN

AH24
AG25

2

C8515

DIS_PX

SCD1U10V2KX-5GP
2
1

SC1U6D3V2KX-GP
2
1

1

DY
2

C8505
SC4D7U6D3V3KX-GP

R8516
249R2F-GP

AL25
AJ25

50

AVDD_A2VDDQ

B
B#

DAC1

GPU_VREFG

(1.8V@75mA DPLL_PVDD)

L8501
1 DIS_PX 2
BLM18PG471SN1D-GP

G
G#

R8523

2

B

L6
L5
L3
L1
K4
AF24

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB

71.ROBSO.M01
VGA_CRT_RED

1

TPAD14
2010/07/07
Change to RSVD based
on DS v3.05

TPAD14 TP8510

1

R8521 1

U6
U10
T10
GPIO_VGA_03_DATA U8
GPIO_VGA_04_CLK
U7
T9
GPIO6_VGA
T8
VGA_BLEN
T7
P10
P4
P2
N6
N5
N3
Y9
N1
GPIO16_SSIN
M4
GPIO17_VGA
R6
GPIO18_VGA
W10
THERMTRIP_VGA
M2
P8
P7
N8
N7

AM26
AK26

2

83 GPIO5_AC_BATT
GPIO17_VGA

AL19
AK18

SC4D7U6D3V3KX-GP
2
1

1
R8503
10KR2J-3-GP

AH18
AJ17

TXOUT_L3P
TXOUT_L3N

DIS_PX

GENERAL PURPOSE I/O

R8520 1

AA12

2010/07/07 Remove TP8517,TP8518,TP8506,TP8519,TP8512
R1
R3

DIS_PX

AL17
AK16

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

DPC

83 TX_PWRS_ENB
83 TX_DEEMPH_EN
83 BIF_GEN2_EN_A

AH16
AJ15

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AA3
Y2

DPC_VSSR#1/DVPCLK
DVPDATA_13/TX2P_DPC0P
DPC_VSSR#2/DVPDAT5
DVPCNTL_1/TX2M_DPC0N
DPC_VSSR#3/GND
DPC_VSSR#4/GND
NC#AA12
DPC_VSSR#5/DVPCNTL_MV0

3D3V_VGA_S0

C

Y4
W5

DVPCNTL_MV1/TX1P_DPC1P
DVPDATA_9/TX1M_DPC1N

AL15
AK14

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

SC1U6D3V2KX-GP

DY

DPC_VDD10#1/DVPDAT15
DPC_VDD10#2/DVPDAT17

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

W3
V2

DVPDATA_7/TX0P_DPC2P
DVPDATA_1/TX0M_DPC2N

SC4D7U6D3V3KX-GP
2
1

DY

0R2J-2-GP

2
C8529
SCD1U10V2KX-4GP

1

V4
U5

DVPDATA_3/TXCCP_DPC3P
DVPCNTL_2/TXCCM_DPC3N

1
2

2 R8512

27 PCIE_RST#

1

83 ATI_RST#

DY 1
0R2J-2-GP

2

R8525
2

DIS_PX

AA5
AA6

DPC_VDD10

SCD1U10V2KX-5GP

PURE_HW_SHUTDOWN#

Q5801_2

DIS_PX

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

C8526
1

DIS_PX

3

2

1

(1.0V@110mA DPC_VDD10)

DPC_VDD18#1/DVPDAT10
DPC_VDD18#2/DVPDAT23

AK24
AJ23

LVTMDP

M92-S2/M93-S3

SCD1U10V2KX-5GP

L8507
1
2
BLM15BD121SS1D-GP

DPC_PVDD/DVPDATA_11
DPC_PVSS/GND

1

1

1V_VGA_S0

DY

84.2N702.A3F
2nd = 84.DM601.03F

M93-S3/M92-S2
W6
V6

2

4

5

6
Q8501
2N7002KDW-GP

2010/06/11

R8526
10KR2J-3-GPDY

TXOUT_U3P
TXOUT_U3N

2

THERMTRIP_VGA

AL23
AK22

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AK8
AL7

TX5P_DPB0P
TX5M_DPB0N

1D8V_VGA_S0

1

THERMTRIP_R

2010/07/15 Modify:
Q8501 change to dual 2n7002.
Add R8512,R8521,C8529 for Q8501 pin2
turn on timming control.

AH22
AJ21

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AJ7
AH6

TX4P_DPB1P
TX4M_DPB1N

DVO

MEM_ID Control

D

AL21
AK20

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

AK6
AM5

TX3P_DPB2P
TX3M_DPB2N

AH20
AJ19

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

AK5
AM3

2

MEM_ID3
MEM_ID2
MEM_ID1
MEM_ID0

2 10KR2J-3-GP
2 10KR2J-3-GP
2 10KR2J-3-GP
2 10KR2J-3-GP

1

DY
DY
1G
Hynix

2

R8527 1
R8522 1
R8519 1
R8518 1

AK3
AK1

TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N

AB11
AB12

VARY_BL
DIGON

1

For Seymour,
2010/06/11
DPC_PVDD is DPC_VDD18
DPC_PVSS and all DPC_VSSR are DP_VSSR

LVDS CONTROL

AH3
AH1

TX1P_DPA1P
TX1M_DPA1N

2

0804 Modify for DV14 Config

DPA

SC1U6D3V2KX-GP

1D8V_VGA_S0

6 OF 7

1

DVPDATA[0:3] Default: Internal Pull down

AG3
AG5

TX0P_DPA2P
TX0M_DPA2N

2

DDR3 Hynix-H5TQ2G63BFR-11C (900MHz) 128M*16

VGA1F

AF2
AF4

TXCAP_DPA3P
TXCAM_DPA3N

DVCNTL_0/DVPDATA_18
DVCNTL_1/NC#L9
DVCNTL_2/TESTEN#2
DVDATA_12/DVPDATA_16
DVDATA_11/DVPDATA_20
DVDATA_10/DVPDATA_22
DVDATA_9/DVPDATA_12
DVDATA_8/DVPDATA_14
DVDATA_7/DVPCNTL_0
DVDATA_6/DVPDATA_8
DVDATA_5/DVPDATA_6
DVDATA_4DVPDATA_4
DVDATA_3/DVPDATA_19
DVDATA_2/DVPDATA_21
DVDATA_1/DVPDATA_2
DVDATA_0/DVPDATA_0

SCD1U10V2KX-5GP
2
1

0011

AE9
L9
N9
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7

SC1U6D3V2KX-GP
2
1

DDR3 SAMSUNG K4W2G1646C-HC11 (900MHz) 128M*16

1

DDR3 Hynix-H5TQ1G63DFR-11C (900MHz) 64M*16

1

0001
0010

LVDS Interface

2 OF 7

2

DDR3 SAMSUNG-K4W1G1646G-BC11(900MHz)64M*16

SC1U6D3V2KX-GP

0000

M93-S3/M92-S2

27,28,36

1

SSID = VIDEO

DVPDATA[0:3]

D

2

2

5

Memory ID Table

2

Title

GPU_DP/LVDS/CRT/GPIO(3/5)
Size
A2

Document Number

Date:

Friday, April 22, 2011

Rev

A00

Enrico 14 AMD
Sheet
1

85

of

109

5

4

3

2

1

SSID = VIDEO

1

C8637
SC4D7U6D3V3KX-GP

1

C8616
SC1U6D3V2KX-GP

2

2

1
2

2

C8615
SC1U6D3V2KX-GP

1

C8613
SCD1U10V2KX-5GP

C8632
SC1U6D3V2KX-GP

1

1

C8631
SC1U6D3V2KX-GP

2

2

2

2

C8630
SC1U6D3V2KX-GP

1

1

C8629
SC1U6D3V2KX-GP

Colay with Seymour-XT-S3
(71.SEYMR.M01)

S DIS_PX

DIS_PX
3D3V_VGA_S0
84.03400.B37 84.03400.B37

U8604
AO3418-GP
D

BIF_VDDC_1V

84.03418.031

1

R8604
1KR2J-1-GP

D

1V_VGA_S0

1D5V_VGA_PWOK

DIS_PX S

84.03418.031

R8608

B
VCC
ADIS_PX
Y
GND

4

4

3

1D5V_VGA_PWOK_R

5

DIS_PX2

PX_EN##

6

2

1
2

C8671
SCD1U10V2KX-5GP

1

C8675
SC1U6D3V2KX-GP

1
2

2

1

1D5V_VGA_PWOK

17,83

2N7002K-2-GP

84.2N702.J31
2nd = 84.07002.I31

1

E

DIS_PX

C8693

2

DY

84.T3904.C11
2ND = 84.03904.P11

3rd = 84.03904.L06

PX_EN#

PX_EN

8209A_EN/DEM_VGA1D5V_VGA_PWOK_R

PX_EN# PX_EN##

1

74LVC1G08GW-1-GP

73.01G08.L04

G

DIS_PX

Non-BACO= HIGH
BACO = LOW

Q8602

5

SCD1U10V2KX-5GP

3
Q8601

3D3V_VGA_S0

U8605
2

D

S
C

Q8604
MMBT3904-4-GP
1
2 Q8604_B B
DIS_PX 0629 Modify

PX_EN#

R8601
1
DY 2 1D5V_VGA_PWOK_R
0R2J-2-GP

1

X01

G

DIS_PX

2K2R2J-2-GP

1D5V_VGA_PWOK

DIS_PX
Q8603

1D5V_VGA_S0

1D5V_VGA_PWOK

C8672
SCD1U10V2KX-5GP

1

C8648
SC1U6D3V2KX-GP

1
2

2

C8645
SC1U6D3V2KX-GP

1

C8670
SC1U6D3V2KX-GP

1

DIS_PX

Q8603_G

R8609
1KR2J-1-GP

PX_EN##

92 8209A_EN/DEM_VGA

3D3V_VGA_S0

DIS_PX

2

2

2

C8647

3D3V_S5

5V_S0

2

1

1

1

DY

PX_EN

2

2
1
2
1
2

B

2010/07/08

2

U8606
AO3418-GP

BIF_VDDC

C8617

10KR2J-3-GP
1
R8606

VGA_CORE

S
DIS_PX

DY

10KR2J-3-GP
1
R8607

BIF_VDDC_CORE
D

R8610
1KR2J-1-GP

84

DIS_PX

2

0R2J-2-GP

2010/07/13 Modify:
Add C8601 for BIF_VDDC

BIF_VDDC

DIS_PX

2

71.ROBSO.M01

AO4468 MAX 3.1A
Rds(on) = 101~155mOhm
VGS=+/-12V

DY 1KR2J-1-GP DIS_PX

A

A00

C8660
SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

C8659

1
2

1
2

DIS_PX DIS_PX

0629 Modify

R8603

SCD1U10V2KX-5GP

1

C8677
C8669
SC1U6D3V2KX-GP SC1U6D3V2KX-GP

1

C8651
SC4D7U6D3V5KX-3GP

2

C8676
SC1U6D3V2KX-GP

2
1
2
1

C8654
SC10U6D3V5KX-1GP

C8665
SC1U6D3V2KX-GP

1

C8680
C8649
SCD1U10V2KX-5GP SC1U6D3V2KX-GP

1
2
1

C8646
SC1U6D3V2KX-GP

1

2

DIS_PX

C8695
SC10U6D3V5KX-1GP

2

G

5V_S0

DIS_PX DIS_PX

BBP#1
BBP#2

1

R8602

G

3D3V_VGA_S0

C

VGA_CORE

2

1ROB

U8603
AO3400A-GP
D

DIS_PX

ROBSON-GP-U

G

S

DIS_PX DIS_PX

DIS_PX

G

U8601
AO3400A-GP

DIS_PX

(GDDR3/DDR3 1.12V@4A VDDCI)

SPVSS

M11_M12

Rds(on) = 1ow
VGS=0.7~1.5V
BIF_VDDC

DIS_PX

SPV10

BACK BIAS
M11
M12

DIS_PX

SPV18

C8656
SC1U6D3V2KX-GP

1
2

VGA_CORE

2010/06/17_1

B

DIS_PX

MPV18

DY

M13
M15
M16
M17
M18
M20
M21
N20

DIS_PX

DIS_PX
2

C8636
SCD1U10V2KX-5GP

C8694
SCD1U10V2KX-5GP

1

C8692
SC1U6D3V2KX-GP

1

DIS_PX
2

1
2

DIS_PX

J7

DIS_PX

DIS_PX DIS_PX

SC10U6D3V5KX-1GP

C8605
SC4D7U6D3V3KX-GP

DIS_PX 2

DIS_PX
2

2
SPV18

H8

1

1

C8634
SC4D7U6D3V3KX-GP

DIS_PX

(1.8V@75mA SPV18)

68.00084.F81
2ND = 68.00217.701

H7

SPV10

1
DIS_PX 2
BLM15BD121SS1D-GP

68.00084.F81
2ND = 68.00217.701

BLM15BD121SS1D-GP

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

PCIE_PVDD

1

L8
SPV18

(120mA SPV10)

L8606

1

VSSRHA
PLL

MPV18

DIS_PX

ISOLATED
CORE I/O

2

C8674
1

L16

AM30

DIS_PX DIS_PX

55mA in BACO mode

VDDRHA

MPV18

C8635
SC1U6D3V2KX-GP

1V_VGA_S0

L8605

L17

BIF_VDDC

C8655
SCD1U10V2KX-5GP

2
C8690
SCD1U10V2KX-5GP

1

DIS_PX

DIS_PX
2

DIS_PX
2

2

DIS_PX

C8603
SC1U6D3V2KX-GP

1

1

C8604
SC4D7U6D3V3KX-GP

DIS_PX 2

BLM15BD121SS1D-GP

68.00084.F81
2ND = 68.00217.701

(Park: 1.8V@75mA MPV18)

MEM CLK

2

MPV18 DIS_PX

L8604
1

SC1U6D3V2KX-GP

C8673
1

C

D

1V_VGA_S0

DIS_PX DIS_PX

DIS_PX

2

NC#V11/VDDR5
NC#U11

SCD1U10V2KX-5GP

DIS_PX

C8679
SC1U6D3V2KX-GP

NC#AA11/VDDR4
DVCLK/VDDR4

DIS_PX

2

VDDR4/VDDR5
VDDR4
VDDR4/VDDR5

1

V11
U11

DIS_PX 2
HCB2012KF-221T30-GP

DIS_PX DIS_PX

VGA_CORE
AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
R21
U21

2

AA11
Y11

DIS_PX

1

DIS_PX

I/O

DIS_PX

2

V12
Y12
U12

VDDR3
VDDR3
VDDR3
VDDR3

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC/BIF_VDDC
VDDC/BIF_VDDC
CORE

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

1

2
2

AA17
AA18
AB17
AB18

DIS_PX

C8657
SC1U6D3V2KX-GP

1
2
1

VDD_CT
VDD_CT
VDD_CT
VDD_CT

M93-S3/M92-S2

DIS_PX

2

C8666
SC1U6D3V2KX-GP

DIS_PX

C8667
C8653
SC1U6D3V2KX-GP SCD1U10V2KX-5GP

C8652
SC1U6D3V2KX-GP

1
2
2

1

1

C8601
SC4D7U6D3V3KX-GP

DIS_PX

2

1
2
3D3V_VGA_S0

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

POWER

DIS_PX

DIS_PX

1

(1.0V@1920mA PCIE_VDDC)

LEVEL
TRANSLATION
AA20
AA21
AB20
AB21

DIS_PX

PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR

2

1

C8612
SC1U6D3V2KX-GP

1

C8627
SC1U6D3V2KX-GP

1
2
1
2

2

DIS_PX

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

L8707

(1.8V@504mA PCIE_VDDR)
AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

C8628
SC1U6D3V2KX-GP

1

(1.8V@110mA VDD_CT)

R8605
1
2
0R0402-PADDIS_PX

1D8V_VGA_S0
PCIE_PVDD

PCIE

VDDC_CT

C8699
SC4D7U6D3V3KX-GP

20100920 X01:
Reserve R8605 0402 0R for VDDC_CT.

4 OF 7

MEM I/O
H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22

DIS_PX
2

2
1D8V_VGA_S0

DIS_PX

VGA1D

DIS_PX

C8698
SC10U6D3V5KX-1GP

1

C8697
SC10U6D3V5KX-1GP

2

DIS_PX DIS_PX

DIS_PX

C8611
SC1U6D3V2KX-GP

2

DIS_PX

C8626
SC1U6D3V2KX-GP

1

C8610
SC1U6D3V2KX-GP

1

1

D

DIS_PX

C8625
SC1U6D3V2KX-GP

1
2

DIS_PX

C8624
C8609
SCD1U10V2KX-5GP SCD1U10V2KX-5GP

1D5V_VGA_S0

D

2ND = 73.7SZ08.DAH

2N7002KDW-GP

84.2N702.A3F

Non-BACO

0

1

1

0

1

BACO

1

0

0

1

0

A

2nd = 84.DM601.03F

S
2N7002K-2-GP

PX_EN# = High, BIF_VDDC = 1V_VGA_S0
PX_EN## = High, BIF_VDDC = VGA_CORE

84.2N702.J31



Wistron Corporation

2nd = 84.07002.I31

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

GPU_POWER(4/5)

Size
A2

Document Number

Date:

Friday, April 22, 2011

Rev

A00

Enrico 14 AMD
Sheet
1

86

of

109

5

4

3

2

1

SSID = VIDEO
1D8V_VGA_S0
DPAB_VDD18

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

DIS_PX

AF16
AG17

DPF_VDD18
DPF_VDD18

DPB_VDD18
DPB_VDD18

AE13
AF13

AF22
AG22

DPF_VDD10
DPF_VDD10

DPB_VDD10
DPB_VDD10

AF8
AF9

AF23
AG23
AM20
AM22
AM24

DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR

DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR

AF10
AG9
AH8
AM6
AM8

1ROB

N12_GND
R8704

1

1

1

1

2

2

R8706 1

2

0R0603-PAD

DIS_PX

DPAB_VDD10

2010/07/09 N11 and N12: in Seymour is NC

R8702

DY

D

1V_VGA_S0

C8705
SC10U6D3V5KX-1GP

DPAB_VDD18

C8703
SC1U6D3V2KX-GP

DPEF_VDD18

DY

DY

0R0603-PAD

2

DIS_PX

(1.0V@220mA DPAB_VDD10)

DPEF_VDD10

N11_GND

2

AE1
AE3
AG1
AG6
AH5

DY

R8705 1

C8713
SC4D7U6D3V3KX-GP

DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR

DY

C8712
SC1U6D3V2KX-GP

DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR

DPAB_VDD10

C8714
SCD1U10V2KX-5GP

1

AG14
AH14
AM14
AM16
AM18

2

C8719
SCD1U10V2KX-5GP

1
2

1
2

DPA_VDD10
DPA_VDD10

DY

C8702
SCD1U10V2KX-5GP

1

DPE_VDD10
DPE_VDD10

AF6
AF7

AG20
AG21

DIS_PX

C

2

0R2J-2-GP
1ROB
2

DIS_PXDPCD_CALR

1
R8701

2
AF17
150R2F-1-GP
DPEF_VDD18

0R2J-2-GP

AG18
AF19
DPEF_VDD18

AG19
AF20

DPEF_CALR

DPAB_CALR

AE10 DPAB_CALR

R8703
150R2F-1-GP
1DIS_PX 2

DPAB_VDD18

DPE_PVDD
DPE_PVSS

DP PLL POWER

DPF_PVDD
DPF_PVSS

DPA_PVDD
DPA_PVSS

AG8
AG7

DPB_PVDD
DPB_PVSS

AG10
AG11

DPAB_VDD18

ROBSON-GP-U

71.ROBSO.M01
Colay with Seymour-XT-S3
(71.SEYMR.M01)
B

1D8V_VGA_S0

(1.8V@150mA DPB_VDD18)
VSS_MECH
VSS_MECH
VSS_MECH

A32 VSS_MECH1
AM1 VSS_MECH2
AM32 VSS_MECH3

TP8701TPAD14
TP8702TPAD14
TP8703TPAD14

1
1
1

C8709

DY

ROBSON-GP-U

C8710

DY

SCD1U10V2KX-5GP
2
1

B

M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U9
V13
V16
V18
Y10
Y15
Y17
Y20

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6
T11
R11

DY

AE11
AF11

SC1U6D3V2KX-GP
2
1

N11_GND
N12_GND

GND
GND
GND/EVDDQ
GND
GND
GND/EVDDQ
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

DY

DPA_VDD18
DPA_VDD18

DPE_VDD18
DPE_VDD18

DPEF_VDD10

SC4D7U6D3V3KX-GP
2
1

C

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

2

AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32

DY

DP A/B POWER

1

0R0603-PAD

AG15
AG16

C8725
SCD1U10V2KX-5GP

2

DIS_PX

1

R8708 1

DY

2

5 OF 7

VGA1E

C8718
SC1U6D3V2KX-GP

1V_VGA_S0

DY

1

2

DY

2

1

DIS_PX

DP E/F POWER

C8720
SC1U6D3V2KX-GP

0R0603-PAD

C8717
SC4D7U6D3V3KX-GP

2

C8721
SC4D7U6D3V3KX-GP

R8707 1
D

(1.8V@300mA DPAB_VDD18)

7 OF 7

VGA1G

2

DPEF_VDD18

2

1D8V_VGA_S0

C8711

DY

71.ROBSO.M01

A


A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU_DPPWR/GND(5/5)
Size

A3
5

4

www.bblianmeng.com
3

Date:
2

Document Number

Rev

Enrico 14 AMD
Friday, April 22, 2011

Sheet
1

A00
87

of

109

5

4

3

2

1

SSID = VIDEO
1D5V_VGA_S0

1D5V_VGA_S0
VRAM1

D

VRAM1_VREF
VRAM2_VREF

1
R8801

C

A8
A1
C1
C9
D2
E9
F1
H9
H2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

H1
M8
L8

VREFDQ
VREFCA
ZQ

84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

84,89
84,89
84,89

A_BA0
A_BA1
A_BA2

M2
N8
M3

BA0
BA1
BA2

J7
K7

CK
CK#

1

R8804
56R2F-1-GP

R8803
56R2F-1-GP

DIS_PX

1

GPU_CLKA0_T

84
84

CKEA0
DQMA2
DQMA0

DIS_PX

84
84
84

W EA0#
CASA0#
RASA0#

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDA3
MDA7
MDA1
MDA4
MDA2
MDA6
MDA0
MDA5

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA21
MDA19
MDA23
MDA18
MDA20
MDA17
MDA22
MDA16

DQSU
DQSU#

C7
B7

DQSL
DQSL#

F3
G3

ODT

K1

CS#
RESET#

L2
T2

NC#T7
NC#L9
NC#L1
NC#J9
NC#J1

T7
L9
L1
J9
J1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

G1
F9
E8
E2
D8
D1
B9
B1
G9

CKE

D3
E7

DMU
DML

L3
K3
J3

WE#
CAS#
RAS#

QSAP_2 84
QSAN_2 84

VRAM1_VREF
VRAM2_VREF

QSAP_0 84
QSAN_0 84

1
R8802

2

DIS_PX

VRAM_ZQ2
243R2F-2-GP

ODTA0 84
CSA0#_0 84
MEM_RST 84,89

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A8
A1
C1
C9
D2
E9
F1
H9
H2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

H1
M8
L8

VREFDQ
VREFCA
ZQ

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

84,89
84,89
84,89

A_BA0
A_BA1
A_BA2

M2
N8
M3

BA0
BA1
BA2

84
84

CLKA0
CLKA0#

J7
K7

CK
CK#

84

CKEA0

K9

CKE

84
84

DQMA1
DQMA3

D3
E7

DMU
DML

L3
K3
J3

WE#
CAS#
RAS#

84
84
84

DIS_PX

K8
K2
N1
R9
B2
D9
G7
R1
N9

84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89

W EA0#
CASA0#
RASA0#

K4W 1G1646E-HC12-GP

2

C8802
SCD01U16V2KX-3GP

84

K9

2

2

DIS_PX

B

VRAM_ZQ1
243R2F-2-GP

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CLKA0
CLKA0#

1

84
84

2

DIS_PX

VRAM2

K8
K2
N1
R9
B2
D9
G7
R1
N9

MDA[0..31] 84

MDA[0..31] 84

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDA27
MDA29
MDA31
MDA25
MDA28
MDA24
MDA30
MDA26

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA12
MDA10
MDA13
MDA11
MDA8
MDA15
MDA9
MDA14

DQSU
DQSU#

C7
B7

QSAP_1 84
QSAN_1 84

DQSL
DQSL#

F3
G3

QSAP_3 84
QSAN_3 84

ODT

K1

ODTA0 84

CS#
RESET#

L2
T2

CSA0#_0 84
MEM_RST 84,89

NC#T7
NC#L9
NC#L1
NC#J9
NC#J1

T7
L9
L1
J9
J1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

G1
F9
E8
E2
D8
D1
B9
B1
G9

DIS_PX

D

C

K4W 1G1646E-HC12-GP

B

1D5V_VGA_S0

1

1

1D5V_VGA_S0

DIS_PXR8808
2K1R2F-GP

2

2

R8805
DIS_PX
2K1R2F-GP

VRAM2_VREF
C8805
SCD1U10V2KX-5GP

2

DIS_PX

1

1
R8807

2K1R2F-GP
DIS_PX

C8807

DIS_PXSC1000P50V3JN-GP-U
2

1

C8803
SCD1U10V2KX-5GPDIS_PX
C8806
SC1000P50V3JN-GP-U

2

2

2

DIS_PXR8806
DIS_PX
2K1R2F-GP

2

1

1

1

VRAM1_VREF

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

GPU-VRAM1,2 (1/4)

Document Number

A3
5

4

www.bblianmeng.com
3

Date:
2

Rev

A00

Enrico 14 AMD
Friday, April 22, 2011

Sheet
1

88

of

109

5

4

1
R8903

C

2

DIS_PX

VRAM_ZQ3
243R2F-2-GP

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

84,88
84,88
84,88

A_BA0
A_BA1
A_BA2

M2
N8
M3

BA0
BA1
BA2

J7
K7

CK
CK#

84

CKEA1

K9

84
84

DQMA5
DQMA4

D3
E7

DMU
DML

84
84
84

W EA1#
CASA1#
RASA1#

L3
K3
J3

WE#
CAS#
RAS#

1

DIS_PX

C7
B7

DQSL
DQSL#

F3
G3

ODT

K1

CS#
RESET#

L2
T2

NC#T7
NC#L9
NC#L1
NC#J9
NC#J1

T7
L9
L1
J9
J1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

G1
F9
E8
E2
D8
D1
B9
B1
G9

CKE

DIS_PX

DIS_PXDIS_PX

DIS_PX

QSAP_5 84
QSAN_5 84

C8914
SC1U6D3V2KX-GP
2
1

DQSU
DQSU#

C8915
SCD1U10V2KX-5GP
2
1

MDA45
MDA40
MDA47
MDA41
MDA44
MDA43
MDA46
MDA42

DIS_PX

C8918
SC10U6D3V5KX-1GP
2
1

D7
C3
C8
C2
A7
A2
B8
A3

C8923
SCD1U10V2KX-5GP
2
1

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

DIS_PX DIS_PX

C8920
SCD1U10V2KX-5GP
2
1

MDA35
MDA39
MDA33
MDA36
MDA34
MDA37
MDA32
MDA38

1

E3
F7
F2
F8
H3
H8
G2
H7

2

VREFDQ
VREFCA
ZQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

C8917
SC1U6D3V2KX-GP

H1
M8
L8

2

2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

DIS_PX

GPU_CLKA1_T

DIS_PX

VRAM3_VREF
VRAM4_VREF

QSAP_4 84
QSAN_4 84

1
R8904

DIS_PX

2 VRAM_ZQ4
243R2F-2-GP

ODTA1 84
CSA1#_0 84
MEM_RST 84,88

84
84

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A8
A1
C1
C9
D2
E9
F1
H9
H2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

H1
M8
L8

VREFDQ
VREFCA
ZQ

84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

84,88
84,88
84,88

A_BA0
A_BA1
A_BA2

M2
N8
M3

BA0
BA1
BA2

J7
K7

CK
CK#
CKE

CLKA1
CLKA1#

DIS_PX

K8
K2
N1
R9
B2
D9
G7
R1
N9

84

CKEA1

K9

84
84

DQMA6
DQMA7

D3
E7

DMU
DML

84
84
84

W EA1#
CASA1#
RASA1#

L3
K3
J3

WE#
CAS#
RAS#

K4W 1G1646E-HC12-GP

2

C8903
SCD01U16V2KX-3GP

A8
A1
C1
C9
D2
E9
F1
H9
H2

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

1

1

R8908
56R2F-1-GP

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88

CLKA1
CLKA1#

DIS_PX

VRAM4

K8
K2
N1
R9
B2
D9
G7
R1
N9

C8916
SC10U6D3V5KX-1GP
2
1

C8907
SC10U6D3V5KX-1GP
2
1

C8905
SC10U6D3V5KX-1GP
2
1

DIS_PX

VRAM3_VREF
VRAM4_VREF

R8907
56R2F-1-GP

1D5V_VGA_S0
MDA[32..63] 84
C8919
SCD1U10V2KX-5GP
2
1

C8912
SC1U6D3V2KX-GP
2
1

C8913
SCD1U10V2KX-5GP
2
1

C8910
SCD1U10V2KX-5GP
2
1

DIS_PX DIS_PX

DIS_PX DIS_PX

84
84

1

VRAM3

DIS_PXDIS_PXDIS_PX DIS_PX
DIS_PX

D

2

1D5V_VGA_S0

C8911
SC1U6D3V2KX-GP
2
1

C8908
SCD1U10V2KX-5GP
2
1

C8909
SC1U6D3V2KX-GP
2
1

C8906
SC1U6D3V2KX-GP
2
1

C8902
SC1U6D3V2KX-GP
2
1

SSID = VIDEO

3

MDA[32..63] 84

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDA61
MDA59
MDA62
MDA57
MDA63
MDA56
MDA60
MDA58

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA52
MDA53
MDA49
MDA54
MDA48
MDA55
MDA50
MDA51

DQSU
DQSU#

C7
B7

QSAP_6 84
QSAN_6 84

DQSL
DQSL#

F3
G3

QSAP_7 84
QSAN_7 84

ODT

K1

ODTA1 84

CS#
RESET#

L2
T2

CSA1#_0 84
MEM_RST 84,88

NC#T7
NC#L9
NC#L1
NC#J9
NC#J1

T7
L9
L1
J9
J1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

G1
F9
E8
E2
D8
D1
B9
B1
G9

D

C

DIS_PX

K4W 1G1646E-HC12-GP

B

B

1D5V_VGA_S0

1

1

1D5V_VGA_S0

R8905
2K1R2F-GP

R8901
2K1R2F-GP

DIS_PX

2

2

DIS_PX

VRAM4_VREF

DIS_PX

DIS_PX

C8924
SC1000P50V3JN-GP-U

1

1

R8906
2K1R2F-GP

C8904
SCD1U10V2KX-5GP

C8925

DIS_PXSC1000P50V3JN-GP-U

DIS_PX

2

2

2

DIS_PX

2

1

1

C8901
SCD1U10V2KX-5GP

2

DIS_PX

R8902
2K1R2F-GP

2

1

1

VRAM3_VREF



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

GPU-VRAM3,4 (2/4)

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

A00

Enrico 14 AMD
Sheet
1

89

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU-VRAM5,6 (3/4)
5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet
1

90

of

109

5

4

3

2

1

D

D

C

C

(Blanking)

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU-VRAM7,8 (4/4)
5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet
1

91

of

109

5

4

3

2

1

SSID = PWR.Plane.Regulator_VGACORE

D

D

VGA_CORE
1
DCBATOUT

PWR_DCBATOUT_VGA_CORE

1

PG9204
2

GAP-CLOSE-PWR
PG9207
1
2
GAP-CLOSE-PWR
PG9210
1
2
GAP-CLOSE-PWR
PG9213
1
2
GAP-CLOSE-PWR
PG9215
1
2

PWR_DCBATOUT_VGA_CORE

RT8208BGQW-GP

2
1

2

PWR_VGA_CORE_VOUT

2D2R5F-2-GP

PR9201
10R2J-2-GP

DY PC9213
SC560P50V-GP

2

DIS_PX

1

PWR_VGA_CORE_FB

1
2
1GND_SENSE_1

PWR_VGA_CORE_D1
PWR_VGA_CORE_D0

PT9203

1

1

PT9202

1128-SB

2

2

B

PR9213

DIS_PX

DIS_PX
2

DIS_PX
DIS_PX
2

2

GAP-CLOSE-PWR

49K9R2F-L-GP

PC9212
SC100P50V2JN-3GP

PR9210

PR9211

150KR2F-L-GP

PC9211

DY SCD1U10V2KX-4GP

1

1

DGPU_PWROK 93

75KR2F-GP

CH551H-30PT-GP

2 PR9212 1
0R0402-PAD

8209A_EN/DEM_VGA 86
1

8209A_EN/DEM_VGA

1

2

DY

1

2

2

DY

2

1
PR9209
10KR2J-3-GP

DY

2
PWR_VGA_CORE_PGOOD

PD9201
17,93 PE_GPIO1

GAP-CLOSE-PWR

PC9210

1

PC9209

DIS_PX

1

DIS_PX

GAP-CLOSE-PWR
PG9212
1
2

SC10P50V2JN-4GP

PR9208 10KR2F-2-GP
1
2

GAP-CLOSE-PWR
PG9220
1
2

GAP-CLOSE-PWR
PG9219
1
2

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
Inductor: 0.82uH PCMC063T-R82MN Cyntec 6.7mohm/8.0mohm Isat =24Arms 68.R8210.10V
O/P cap: 220U 2V EEFCX0D221R 15mOhm 2.7Arms Panasonic/79.22719.20L
H/S: SIR712DP/ POWERPAK/10.3mOhm/12.4mOhm@4.5Vgs/ 84.00172.037
L/S: SiR460DP/ POWERPAK/ 4.9mOhm/ 6.1mohm@4.5Vgs/ 84.00460.037
SC10P50V2JN-4GP

3D3V_VGA_S0

1

1

DIS_PX

PR9218
10KR2F-2-GP

3D3V_VGA_S0

PT9201

DIS_PX DIS_PX DY
2

DYPR9206

DIS_PX

2

1
2

1

PU9203

PWR_VGA_CORE_VOUT

B

GAP-CLOSE-PWR
PG9216
1
2

4
3
2
1

PWRCNTL_1 85

DIS_PX
0316-SC

GAP-CLOSE-PWR
PG9217
1
2

0825
PC9207

DIS_PX

1

1

COIL-D82UH-2-GP

0824

PWRCNTL_0 85

2

VOUT

DIS_PX2

2

GND

GAP-CLOSE-PWR
PG9214
1
2

GAP-CLOSE-PWR
PG9201
1
2

VGA_CORE_PWR

S
S
S
G

2

EM/DEM

GAP-CLOSE-PWR
PG9211
1
2

PL9201
1

1

1
2

17

GAP-CLOSE-PWR
PG9209
1
2

C

SE330U2VDM-L-GP

15

PWR_VGA_CORE_D1
PWR_VGA_CORE_D0

GAP-CLOSE-PWR
PG9206
1
2

GAP-CLOSE-PWR
PG9208
1
2

1128-SB

SE330U2VDM-L-GP

DIS_PX

PWR_VGA_CORE_FB

DIS_PX

SCD1U25V3KX-GP

SE330U2VDM-L-GP

DIS_PX
PC9208
SC1U10V2KX-1GP

7
3
14
5
6

DIS_PX

SIR460DP-T1-GE3-GP

PR9205
8209A_EN/DEM_VGA
11K3R2F-2-GP

PWR_VGA_CORE_UGATE
PWR_VGA_CORE_PHASE
PWR_VGA_CORE_LGATE

D
D
D
D

G0
FB
G1
D1
D0

12
11
8

2

PGOOD
CS

1

4
10

VDD

PR9203
2D2R3-1-U-GP
PC9201
PWR_VGA_CORE_BOOT
2
1PWR_VGA_CORE_BOOT_C
1
2

GAP-CLOSE-PWR
PG9205
1
2

VGA_CORE

1128-SB

SCD1U10V2KX-4GP

PWR_VGA_CORE_PGOOD
PWR_VGA_CORE_CS

UGATE
PHASE
LGATE

13

VGA_CORE_PWR
PG9203
1
2

Design Current =12.9A
19.03A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

RT8208B_+VGA_CORE
5

4

www.bblianmeng.com
3

2

Size
A2

Document Number

Date:

Friday, April 22, 2011

Rev

A00

Enrico 14 AMD
Sheet
1

92

of

109

3

2

AO4468 MAX 11.6A
Rds(on) = 11~14mOhm
VGS=+/-20V

PR9320

PWR_1D8V_VGA_EN

2

DIS_PX

0R0402-PAD

4

2

DIS_PX

1

SCD1U10V2KX-5GP

2

DY

PC9329
SCD01U50V2KX-1GP

2

3

2

S G D

PC9323

17,92 PE_GPIO1

DIS_PX

1D8V_S0_VGA_PG

83
D

84.2N702.J31
2nd = 84.07002.I31

PC9302

84.T3904.C11
2ND = 84.03904.P11

DY

3rd = 84.03904.L06

PR9335
100KR2J-1-GP

1

1

DIS_PX
1

1
3

9025_PWRGD_VGA_1V
3.3V_RUN_VGA_1

5

6

2
4

6

5
2

84.2N702.A3F
2nd = 84.DM601.03F

SCD1U10V2KX-5GP

DIS_PX

2K2R2J-2-GP

1
20KR2F-L-GP

D

2N7002K-2-GP

PQ9310_B BDIS_PX

DIS_PX
15V_S5

PQ9306
2N7002KDW-GP

DIS_PX

PR9333
2

PR9305
470R2J-2-GP

1 PR9340 2

1D8V_VGA_S0

E

1D8V_ENABLE_RC

1

2 1D8V_VGA_EN#
100KR2J-1-GP

DIS_PX
S

2

G

DIS_PX

1
PR9334

2N7002KDW-GP
DIS_PX
PQ9303
1

G

C

PQ9310
MMBT3904-4-GP
0629 Modify

1

1
2

DIS_PX
PQ9309

PQ9310_C

3D3V_AUX_S5

D G S
2nd = 84.DM601.03F
84.2N702.A3F

DIS_PX

SC10U6D3V3MX-GP

3D3V_VGA discharge

0504 chaomin

3.3V_ALW_1

0629 Modify

PC9331

2nd = 84.08882.037

84.02130.031
2ND = 84.03413.A31
G

DIS_PX

DIS_PX

AO4468-GP

D

PR9303
100KR2J-1-GP

D

1

84.04468.037

PC9330DIS_PX
SC10U6D3V3MX-GP

1
2
3
4

3D3V_VGA_S0

2

3D3V_VGA_S0

1

3D3V_S0

1D8V_VGA_S0
PU9306
S
8 D
S
7 D
6 D DIS_PXS
D
G
5

2

1 DY PR9301
2
0R2J-2-GP
DMP2130L-7-GP
PQ9302
S
DIS_PX D

3D3V_S5

1D8V_VGA_S0_PG

10KR2J-3-GP
1
PR9339

1D8V_VGA_S0

1D8V_S0

2

+3VS to 3.3V_DELAY Transfer

1

10KR2J-3-GP
1
PR9338

4

2

5

1D8V_ENABLE

PD9304

DY 1

2

17,92 PE_GPIO1

CH551H-30PT-GP

Different To Intel, AMD Is High Active

PE_GPIO1
PE_GPIO0
L

IGPU with BACO

H

H

C

0628 Modify:
Change PU9305 part number to 84.04468.037 same as U3601&U3602.

change low Rds(on) MOSFET

1D5V_VGA_S0

1D5V_S3

2
9025_PWRGD_VGA_1V

1

PR9313

PWR_1V_ADJ

PR9314
2

PWR_1V_VGA_PWRGD

DIS_PX 39KR2F-GP

DIS_PX
0629 Modify:
Reserved PD9301 connect DGPU_PWR_EN to
PWR_1D5V_EN for power down sequence.

0825

17,92 PE_GPIO1

2

DY

DIS_PX

1

2

92 DGPU_PWROK

1

PR9318

2

0R0402-PAD

DIS_PX

2

PR9317
470R2J-2-GP

15V_S5

S G D

PR9319
DIS_PX

100KR2J-1-GP

CH551H-30PT-GP

0R0402-PAD

DIS_PX

84.2N702.A3F
2nd = 84.DM601.03F

Discharge Circuit
1D5V_VGA_S0

0721

PQ9304
2N7002KDW-GP

PD9303

B

2

DIS_PX

D G S
5

1
PR9316

GAP-CLOSE-PWR

6

1

1

DIS_PX

PC9315
SCD01U50V2KX-1GP

PC9313

DY
2

DY

2

1

PR9311
10KR2F-2-GP

PC9312

SC10U6D3V3MX-GP

PR9315
1
20KR2F-L-GP

2

RT9025-25ZSP-GP

PC9311

0629 Modify:
Add PC9332 10uF 0603.
PC9314

DIS_PX

1

2

DIS_PX

DIS_PX

2

1

PR9312
2K2R2J-2-GP

X01

84.04468.037

2nd = 84.08882.037

2 1D5V_VGA_EN#
100KR2J-1-GP

2

CH551H-30PT-GP

5
6
7
8
9

1V_VGA_S0

AO4468-GP

0802 Rename to 1D5V_VGA_EN DIS_PX

1

1

2

DY

NC#5
VDD
VOUT
VINDIS_PX ADJ
EN
GND
PGOOD
GND

SC10U6D3V5MX-3GP

1

PU9302

4
3
2
1

3D3V_AUX_S5

GAP-CLOSE-PWR
PG9304
1
2

SC10U6D3V5MX-3GP

17,92 PE_GPIO1

DY

1V_VGA_PWR

Vo(cal.)=1V

SC100P50V2JN-3GP

2

SCD1U10V2KX-5GP

3D3V_VGA_S0

PD9301

PC9310

PG9303
1
2

1

PWR_1V_VGA_EN

0629 Modify:
Reserved PD9302 connect DGPU_PWR_EN to
PWR_1V_EN for power down sequence.

Park_Madison Does Not Support BACO, So follow Old Sequence
Seymour_Whistler_Robson Support BACO, So Change Sequence

Iomax>1.2A

RT9025 for 1V_VGA_S0

2

2

1 PR9310 2
0R0402-PAD

DIS_PX

1

3D3V_VGA_S0

PWR_1V_VGA_VDD

DIS_PX

SC1U6D3V2KX-GP

PC9309

DIS_PX

1

PC9308
SC10U6D3V5MX-3GP

so 1V_VGA_S0 EN have to fine tune RC delay
after VGA_Core

SC10U6D3V3MX-GP

DIS_PX

2

ramp-up before 1V_VGA_S0

1V_VGA_S0 should ramp up before 1D8V_VGA_S0

2

VGA_Coreshould

1
2
3
4

PC9301

1

PR9309
0R0402-PAD

S
S
S
G

4

DIS_PX

1D5V_S3

VGA_Core

1

B

3D3V_VGA_S0 should ramp-up before

1

1

0603

Seymour_Whistler_Robson Support BACO, So Change Sequence

PU9303
8 D
7 D
6 D
D
5

AO4468 MAX 11.6A
Rds(on) = 11~14mOhm
VGS=+/-20V

3

Park_Madison Does Not Support BACO, So follow Old Sequence

1D5V_VGA_S0

DIS_PX

5V_S5

1

L

2

H

IGPU

1

H

DIS_1D5V_VGA_S02

dGPU mode

1D5V_ENABLE_RC

C

1D5V_VGA_EN

DIS_PX
0802 Rename to 1D5V_VGA_EN
2N7002K-2-GP
G

DIS_PX

1D5V_ENABLE

0802 Rename to 1D5V_VGA_EN

1D5V_VGA_EN#

D
S

PQ9301

84.2N702.J31
2nd = 84.07002.I31

0628 Modify:
Simplify 1D5V_ENABLE control circuit.
Rmoved PQ9305,PR9327,PR9328 PQ9306.

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

DISCRETE VGA POWER

Size
A2

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD

A00
Sheet

1

93

of

109

5

4

3

2

1

SSID = VIDEO

D

D

C

C

B

B


A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LVDS_Switch
Size

Document Number

Rev

Enrico 14 AMD
5

4

www.bblianmeng.com
3

Date:
2

Friday, April 22, 2011

A00

Sheet
1

94

of

109

5

4

3

2

1

D

D

(Blanking)



Wistron Corporation
21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.
Title

Size
A0
Date:

Reserved

Docum ent Num ber

Rev

Enrico 14 AMD
Friday, April 22, 2011

Sheet

95

A00
of

109

C

C

B

B

A

A

5

4

3

www.bblianmeng.com

2

1

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number

Date:

Friday, April 22, 2011

Touch Panel

Rev

Enrico 14 AMD
Sheet
1

96

A00
of

109

1

1

DY

ODD_PW R_5V

1

1

4

EC9736
SCD1U25V2KX-GP
2
1

2

DY

EC9733
SCD1U25V2KX-GP
2
1

DY DY

DY

2

1

EC9703
SCD1U25V2KX-GP

2 EC9720
1
SCD1U25V2KX-GP

EC9737
SCD1U25V2KX-GP
2
1

5V_S0

3D3V_S0

DY

2
1
EC9714
SCD1U25V2KX-GP

EC9735
SCD1U25V2KX-GP
2
1

2

DY

X01 EMI 12/13

DY

EC9738
SCD1U25V2KX-GP
2
1

EC9702
SCD1U25V2KX-GP

X01 EMI 12/13

DY

EC9725
SCD1U25V2KX-GP
2
1

1
EC9713
SCD1U25V2KX-GP

5V_S5

DY

2

EC9712
SCD1U25V2KX-GP

2

5

3D3V_S0

EC9701
SCD1U25V2KX-GP

EC9711
SCD1U25V2KX-GP
2
1
EC9732
SCD1U25V2KX-GP
2
1

VGA_CORE

DY

2

DY

EC9719
SC47P50V2JN-3GP
2
1
EC9715
SCD1U25V2KX-GP
2
1
EC9716
SC47P50V2JN-3GP
2
1

EC9740
SCD1U25V2KX-GP
2
1

DY

EC9746
SCD1U25V2KX-GP
2
1

EC9717
SCD1U25V2KX-GP
2
1

DY

EC9743
SCD1U25V2KX-GP
2
1

DY

X01 EMI 12/13

EC9749
SCD1U25V2KX-GP
2
1

EC9718
SC47P50V2JN-3GP
2
1

1D5V_S3

EC9726
SCD1U25V2KX-GP
2
1

EC9748
SCD1U25V2KX-GP
2
1

1D5V_VGA_S0

DY

EC9721
SCD1U25V2KX-GP
2
1

EC9739
SCD1U25V2KX-GP
2
1

EC9742
SCD1U25V2KX-GP
2
1

DY

EC9745
SCD1U25V2KX-GP
2
1
EC9741
SCD1U25V2KX-GP
2
1

2

DY

EC9730
SCD1U25V2KX-GP
2
1

1D1V_S0

DY

DCBATOUT

DY DY DY

EC9731
SCD1U25V2KX-GP
2
1

5V_S5

EC9751 SCD1U25V2KX-GP
1 DY 2

EC9750 SCD1U25V2KX-GP
1 DY 2

DY DY

EC9763
SCD1U25V2KX-GP
2
1

SCD1U25V2KX-GP
2

DY

EC9752 SCD1U25V2KX-GP
1 DY 2

EC9760
SCD1U25V2KX-GP
2
1

EC9753
1

EC9764
SCD1U25V2KX-GP
2
1

DY DY DY DY

EC9769
SCD1U25V2KX-GP
2
1

3D3V_S5

EC9729
SCD1U25V2KX-GP
2
1

DY

EC9762
SCD1U25V2KX-GP
2
1

DY

Document Number

Friday, April 22, 2011



Title

Size
A3

Date:

EC9767
SCD1U25V2KX-GP
2
1

1D5V_S3

EC9761
SCD1U25V2KX-GP
2
1
EC9765
SCD1U25V2KX-GP
2
1

EC9757 SCD1U25V2KX-GP
1 DY 2

3D3V_S5

SCD1U25V2KX-GP
2

EC9756 SCD1U25V2KX-GP
1 DY 2

DCBATOUT

EC9755
1

5V_S5

EC9759
SCD1U25V2KX-GP
2
1

EC9754 SCD1U25V2KX-GP
1 DY 2

X01 EMI 12/16

1

EC9778
SCD1U25V2KX-GP
2
1

EC9770
SCD1U25V2KX-GP
2
1

+DC_IN

2

DY

DY DY DY

EC9775
SCD1U25V2KX-GP
2
1

EC9758
SCD1U25V2KX-GP

DY

EC9772
SCD1U25V2KX-GP
2
1

2

PW R_3D3V_DCBATOUT

EC9776
SCD1U25V2KX-GP
2
1

1

EC9768
SCD1U25V2KX-GP

EC9774
SCD1U25V2KX-GP
2
1

DY

2

DY DY DY DY

EC9777
SCD1U25V2KX-GP
2
1

3D3V_S5

EC9773
SCD1U25V2KX-GP
2
1

DY

DY

EC9782
SCD1U25V2KX-GP
2
1
EC9783
SC47P50V2JN-3GP
2
1
EC9780
SC47P50V2JN-3GP
2
1

DY

EC9784
SC47P50V2JN-3GP
2
1

1D5V_S3

EC9781
SC47P50V2JN-3GP
2
1

EC9771
SCD1U25V2KX-GP
2
1

3

X01 EMI 12/13

DY DY

3

EC9744
SCD1U25V2KX-GP
2
1
EC9747
SCD1U25V2KX-GP
2
1

EC9779
SC47P50V2JN-3GP
2
1

0824 EMI Request

DCBATOUT

EC9722 SCD1U25V2KX-GP
1 DY 2

DY DY

1

EC9723 SCD1U25V2KX-GP
1 DY 2

DCBATOUT

DY

DY

1

EC9724
SCD1U25V2KX-GP

EC9710
SCD1U25V2KX-GP
2
1

H3
HT85BE85R29-U-5-GP

1

EC9709
SCD1U25V2KX-GP
2
1

H7
HT85B95X975R29-S-GP

SPR2
SPRING-58-GP

1

EC9708
SCD1U25V2KX-GP
2
1

A00

SPR1
SPRING-58-GP

1

1

EC9707
SCD1U25V2KX-GP
2
1

Stand Off

4

1

H12
H11
STF217R113H162-GP
STF237R117H83-1-GP

1

EC9706
SCD1U25V2KX-GP
2
1

EC9734
SCD1U25V2KX-GP
2
1

H4
H5
HT85BE85R29-U-5-GPHT85BE85R29-U-5-GP

SPR4
SPRING-58-GP

1

H6
HT85BE85R29-U-5-GP

1

1

EC9705
SCD1U25V2KX-GP
2
1

DY

X02
SPR3
SPRING-62-GP

1

H2
HOLE256R115-GP

1

EC9704
SCD1U25V2KX-GP
2
1

X02

H9
H10
HOLE256R142-GP HOLE256R126-1-GP

5

1

CPU BRACKET

H8
HOLE256R142-GP

H1
HT85BE85R29-U-5-GP

1

D

C

B

A

1

EC9727
SCD1U25V2KX-GP
2
1
EC9728
SCD1U25V2KX-GP
2
1

EC9766
SCD1U25V2KX-GP
2
1

1

Wistron Corporation

A00

109

Rev

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

of

UNUSED PARTS/CAP

97

Enrico 14 AMD

1

Sheet

D

C

B

A

www.bblianmeng.com

5

4

3

2

Thermal Block Diagram

1

Audio Block Diagram

D

D

SPKR_PORT_D_L-

SPEAKER

SPKR_PORT_D_R+

Codec
92HD87B1
PAGE28

DXP

HP
OUT

HP1_PORT_B_L

P2800_DXP

HP1_PORT_B_R

MMBT3904-3-GP
SC2200P50V2KX-2GP

UMA
Thermal
P2800

C

DXN

P2800_DXN

C

Place near CPU
PWM CORE

MMBT3904-3-GP
PAGE27

GPIO5

KBC
NPCE795P

GPIO92

SYS_THRM

TDR

CPU_THRM

TDL

HP0_PORT_A_R

OTZ

THERM_SYS_SHDN#

2N7002

PURE_HW_SHUTDOWN#
IMVP_PWRGD

G

GPIO4
GPIO56

VGA_THRM

3V/5V

VR

PAGE28
P2800_VGA_DXP
DXP

FAN_TACH1

VGA
Thermal
P2800

TACH

FAN

THRMDA
SC2200P50V2KX-2GP

DMIC_CLK/GPIO1

SC2200P50V2KX-2GP

VGA

P2800_VGA_DXN
DXN

B

DMIC0/GPIO2

THRMDC

Place near GPU(DISCRETE only).

MMBT3904-3-GP
PORTC_L

VIN

5V

VREFOUT_A_OR_F

PGOD

TDR

B

FAN1_DAC

EN

D

S

Put under CPU(T8 HW shutdown)

GPIO94

MIC
IN

HP0_PORT_A_L

T8

Analog
MIC

PORTC_R
VREFOUT_C

PH

VIN

OTZ
VSET

VOUT

FAN CONTROL
A

P2793



A

Wistron Corporation

PAGE28

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

THERMAL/AUDIO BLOCK DIAGRAM

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD
Sheet
1

A00
98

of

109

5

4

3

2

1

POWER SEQUENCE
DCBATOUT
3D3V_AUX_S5
D

RTC_AUX_S5

D

KBC_ROM_STRAPS
S5_ENABLE
5V_S5

T2

Min

Max

Description

-

-

+3.3V_S5 to +1.1V_S5

-

+3.3V_S5 to resume reset (RSMRST#).

3D3V_S5

T1

T1
1D1V_S5

T2

10 ms

T7

98 ms

150 ms

FCH PWRGOOD assertion to LDT_PG assertion delay.

T8C

1.0 ms

2.3 ms

PCIRST# to LDT_RST#.

T9A

101 ms

113 ms

FCH PWR_GOOD to A_RST#.

T13

8 ns

RSMRST#(KBC_RSMRST#)
S5_ROM_STRAPS
T13
PWR_BTN#(PM_PWRBTN#)
PM_SLP_S3#/PM_SLP_S5#
C

-

PwrButton to SLP_S3# / SLP_S5# de-assertion

C

1D5V_S3
1D5V_S0
0D75V_S0
5V_S0
3D3V_S0
1D8V_S0
1D1V_S0
1V_S0
VCORE_EN

B

APU_VDD

B

APU_VDDNB
FCH_PWRGD

T7

H_CPUPWRGD
S0_ROM_STRAPS
T9A
A_RST#

T8C

APU_RST#



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

www.bblianmeng.com
3

2

POWER SEQUENCE

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

A00

Enrico 14 AMD
Sheet
1

99

of

109

A

B

C

D

E

Power Shape

Power Delivery Block Diagram

Regulator

LDO

Switch

AD+

AO4407A

4

Adapter

DCBATOUT

4

40

ISL6265C

TPS51218
42,43

TPS51218

46

TPS51216

46

44

BT+

Battery
APU_VDD

Charger
BQ24707

APU_VDD_NB

1D1V_S5

40

1V_S0

AO4468
36

DDR_VREF_S3

1D5V_S3

1D1V_S0

0D75V_S0

3

3

AD+

AD+

DCBATOUT

36
41

5V_PWR

5V_AUX_S5

15V_S5

A04468

TPS51125A

3D3V_PWR_2

1D5V_S0

3D3V_S5

BT+

5V_S5

5V_S5 36,38,41,42,44,46,49,61,65,68,69,92,93,97

5V_S0

5V_S0 6,28,29,36,50,51,56,68,69,86,97

RTC_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_S5
3D3V_PWR
PA102FMG

5V_S5

AO4468

31

36

3D3V_LAN_S5

3D3V_S0

RT8015B
48

UP7534BRA8

61

61

AO4468
36

RTL8105E-VB

AO6402A

USB20_VCCA

USB20_VCCA

2

1D8V_S0 6,7,17,20,42,47,71,93

1D5V_S3

1D5V_S3 5,7,14,15,36,44,93,97

1D5V_S0

1D5V_S0 36,65

1D1V_S5

1D1V_S5 20,36,46

1D1V_S0

1D1V_S0 20,36,97

1D1V_SATA_S0

1D1V_SATA_S0 19,20

1D1V_PCIE_S0

1D1V_PCIE_S0 17,20

APU_VDDNB
APU_VDD

1D05V_LOM

3D3V_CARD_S0 32,74

1D8V_S0

0D75V_S0

5V_S0

3D3V_AUX_KBC 27,28,39,60

3D3V_S0 6,7,14,15,17,18,20,21,27,28,29,31,32,36,42,49,56,60,65,71,93,97

DDR_VREF_S3

49

31

3D3V_AUX_S5 27,28,36,40,41,60,93

3D3V_S5 6,18,19,20,21,31,36,38,41,42,44,46,47,60,70,82,86,93,97

1V_S0

1D8V_S0

RTC_AUX_S5 17,27,60

3D3V_S0

VDDIO_AZ

UP7534BRA8

39,40

3D3V_S5

3D3V_CARD_S0
2

15V_S5 36,41,49,93

BT+

3D3V_AUX_S5

15V_S5

38,40

DCBATOUT 40,41,42,43,44,46,49,92,97

VDDIO_AZ

20,21

1V_S0 4,7,46
DDR_VREF_S3

5,14,15,44

0D75V_S0 14,15,44
APU_VDDNB 7,42,43
APU_VDD 7,42

LCDVDD


1

1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

A

B

www.bblianmeng.com
C

D

Power Block Diagram

Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD
Sheet
E

A00
100

of

109

5

4

3

2

1

2.2K
3D3V_S0
0 OHM
AE22
AD22

SMB_DATA
SMB_CLK

PCH_SMBDATA
PCH_SMBCLK

200
202

DIMMA(DM1)

200
202

DIMMB(DM2)

DY DY
D

14
SMB Addr=[XX]

10K

FCH

F5
F4

SCLK1
SDATA1

D

3D3V_S5

10K
D25
F23

32
30

SCLK2
SDATA2

15
SMB Addr=[XX]

WLAN

65
SMB Addr=[XX]

2.2K
3D3V_S5
B26
E26

0 OHM
APU_SIC
APU_SID

SCLK3
SDATA3

DY
1K
3D3V_S0

P3
P4

C

APU_SIC
APU_SID

C

2.2K

5V_HDMI_S0
0 OHM

APU

B2
C2

PCH_HDMI_CLK_R
PCH_HDMI_DATA_R

DDC_CLK_HDMI
DDC_DATA_HDMI
2.2K

15
16

3D3V_S0

HDMI

51
SMB Addr=[XX]

33 OHM
A3
B3

LVDS_DDC_CLK
LVDS_DDC_DATA
4.7K

13 LCD Panel
11 (LVDS Type)
49
SMB Addr=[XX]

5V_CRT_S0

0 OHM
F2
D4

B

CRT_DDCCLK_CON
CRT_DDCDATA_CON

DDCCLK
DDCDATA

15
12

DY DY

CRT
B

50
SMB Addr=[XX]

0 OHM
67
68

SML1_CLK
SML1_DATA

APU_SIC
APU_SID

4.7K
3D3V_AUX_KBC

EC
70
69

100 ohm

BAT_SCL
BAT_SDA

PBAT_SMBCLK1
PBAT_SMBDAT1
100 ohm

A

3
4

DY DY

Battery
connector

39
SMB Addr=[XX]

NPCE795PA0DX

A

short pad

5

4

PWR_CHG_BAT_SCL
PWR_CHG_BAT_SDA

9
8

Wistron Corporation

40
SMB Addr=[XX]

www.bblianmeng.com
3



Charger

BQ24707RGRRG4

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

2

SMBUS BLOCK DIAGRAM

Size
A2

Document Number

Date:

Friday, April 22, 2011

Rev

Enrico 14 AMD
Sheet
1

A00
101

of

109

5

4

3

2

1

Change notes DATE

VERSON DATE
X01

9/23

D

Page

Modify List

OWNER

50

Delete F5001, Share Fuse with HDMI

EE

71

DUMMY Debug Port DB1,RN7102, R7107

EE

27

Change R2724 value to 20K, X01 Version

EE

39,56

D

ME
Change BATT1,ODD1,HDD1 Connector

27

Add C2722 0.1uF between Q2703 G&S pin for fixed leakage voltage to 3D3V_AUX_KBC under DC mode.

EE

27

Add Q2706 2N7002 to avoid leakage loop from 3D3V_S5 to 3D3V_AUX_KBC issue when 10mW latched fail
timing. Un-stuff C2713 to follow the standard schematics.

EE

28

Change U2801, U2803 to 74.02800.A71

EE

C

C

X01

9/29

61

Change U6102 to 74.07534.079

EE

50

Change L5001,L5002,L5003 bead to 0402 size:68.00217.991

EE

Change DCIN1,RJ45,TPAD1,IOBD1 Connector

ME

Change IOBD1 Pin define

EE

Dummy APU_SIC, APU_SID level shifter, pop R644,R645

EE

38,59,69,
82

82

X01

10/13

6

B

B

6

X01

10/20

DUMMY Q3601,R3622 for reserved

EE

28

Change R2816,R2822 to 107KR,R2817 ,R2821to 226KR for new version P2800 chip

EE

39

Delete R3901 for double pull high

EE

49

Delete R4902 for double resister

EE

92
27,36

Change PURE_HW_SHUTDOWN#(R2705) power rail to 3D3V_AUX_KBC

EE
Power

Change PR9213 to 75K, PR9211 to 150K for VGA_CORE (Robson-LP)Output



Add GPIO97 for IMVP_PWRGD control ,Change D3605.2 to 1V_S0_PWRGD,Delete D3606,
Change D3603.1 to VRM_VDD_PWRGD for sequence

EE

86

Modify 1D5V_VGA_PWRGD to 1D5V_VGA_PWOK

EE

31

Dummy R3101,R3102,Q3101,R3108 for leakage

EE

Change R3607 to 10K,C3605 to 15n,PR4711 to 0ohm, PC4710 DY, C3610 DY, R3633 to 33K, C3615 to 33n,R3604 to33K
for sequence

EE

36,47
5

Add level shifter for H_Thermtrip#

36

27

A

EE

4

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

www.bblianmeng.com
3

2

Change notes
Size
A3

Document Number

Date:

Friday, April 22, 2011

Rev

A00

Enrico 14 AMD
Sheet
1

102

of

109

5

4

3

2

1

Change notes DATE

VERSON DATE
X01

10/20

D

Page

OWNER

20

Change R2004 to 0603 size for current tolerance

EE

93

Change PR9311 to 10K for 1V_VGA Voltage

Power

Add C6105,C6106,C6509,C6510 to 6.8p for solve SIV USB fail

EE

Change RN2705 8P4R to 4P2R and R2715, RN2705 DY

EE

Add PR4061 PR4062 100KR, empty other parts for fine tune sequence for leakage

EE

Modify C8524,C8525=12p, C1715,C1717=18p for crystal frequence match

EE

Add LED for WLAN

EE

61,65

27

40

10/27

Modify List

85,17

68

D

C

C
14

11/10

B

Change RN1401 to 22 ohm and pop C1423,C1424 for solved SMBus SIV Fail

EE

38

Change DCIN CONN pin define

EE

31

Solved leakage issue follow DV15

EE

68

Modify Wireless LED schematic

EE

85

Change L8502,L8503,L8507,L8505,L8513 to short pad for power

EE

Modify C1720=15p, C3102=15p for crystal frequence match

EE

28

Add G709 for thermal solution

EE

68

Delete RN6802,RN6801

EE

Change GPU from Robson LP to Seymour XT

EE

46

DY 1V to merge 1D1V

EE

27

Add two model ID for config

EE

58

Delete MIC2 and move mic1 to IO Board

EE

92

Update Seymour and Robson power plan setting(PR9219,PR9210,PR9214,PR9211)

EE

87

Pop R8421 for check list request

EE

68

Modify power LED schematic and charger LEDs

EE

Merge with power schematic

Power

Title

Add LID_CLOSE# pull high

EE

Size
A3

Document Number
Enrico 14 AMD

Date:

Friday, April 22, 2011

17,31

83~89

11/17

A

27

B

A



Wistron Corporation

www.bblianmeng.com

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Change notes
Rev
A00
Sheet

103

of

109

5

4

3

2

1

Change notes DATE

D

VERSON DATE

X01

11/24

Page

Modify List

OWNER

50,51

Modift CRT,HDMI share fuse schematic

EE

31

Change L3101 to slime type and add R3101 GIGA mark for 10/100 internal PU

EE

Change R2726, R2710 to F tolerance for accurate level to KBC

EE

Change WLAN LED design to meet on/off behavior SPEC

EE

Change RTC_POWER from RTC_AUX_S5 to 3D3V_AUX_S5 for saving RCT power and no influence on PSL

EE

6

Pull up LTDP0_HPD to 5V from AMD SCL 1.04

EE

6

Change RN634 to 2K2R follow AMD SCL 1.03

EE

27

27,65,68

27

D

C

C

12/2

6

Add level shifter for LVDS SMBus follow AMD SCL 1.04

EE

59

Rename part reference for Lan ESD

EMI

31

Set R3101 BOM option for 8105E DY

EE

31

Add RTC sense schematic

EE

27

Reserved

EE

27

Set R2769 empty, Duplicated function in page 40.

EE

28

Reserve R2861 for hysteresis

EE

36

Reserve C3633 for power up sequence tunning

EE

49

Modify TP4906,TP4907 to AFTP

EE

R2778 for EC power switch logic circuit.

B

B

17,31

A

Change 25MHZ, 32.768K to small size by source recommand

Sourcer

2

Modify Block Diagram

EE

36

Change U3606 P/N

EE

59

Modify Transformer schenatic from GIGA to 10/100 for latest config

EE



6

Remove level shifter for LVDS SMBus(AMD confirm)

EE

40

Reserve snuber 2.2ohm+560p for EMI solution

EMI

50

Change L5001,L5002 and L5003 from 220hm to 30ohm for EMI Solution

EMI

50

Change 2N7002E to 2N7002K for EOL

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Change notes

5

4

Sourcer

www.bblianmeng.com
3

2

Size
A3

Document Number
Enrico 14 AMD

Date:

Friday, April 22, 2011

Rev
A00
Sheet
1

104

of

109

5

4

3

2

1

Change notes DATE

VERSON DATE

D

Page

Modify List

OWNER

27

Modify R2776 to 64.9K

EE

59

Modify R5903,R5904 to 0603 size

EE

27

Change R2739 to 1% tolerance

EE

6

Change RN634 form 2.2KR to 1KR by AMD suggestion

EE

Change WLAN LED indicator for reserve EC and module circuit

EE

60

Change Q6001.G from +RTC_VCC to RTC_PWR

EE

15

Reserve R1531 and R1532 69.8R for memory glitch issue

EE

65,68

D

C

C

36,46

Stuff 0R and change to open-gap for merge power rail

EE

47

Change PQ4701 to ESD 2KV for Vendor EOL

EE

38,39

PD3801 change to P6SMBJ58A,PD3902 change to SMF18AT1G

Power

40

Add PQ4007 PR4012 and PR4037 to improve AC_IN# delay issue

Power

All

Change reference from PTCxx to PTxx for meet SMT Process

Power

B

B

41,42,44, Change PC4111,PC4116,PC4117,PC4204,PC4223,PC4203,PC4301,PC4302,PC4304,PC4403,PC4404,PC4405,PC4602,PC4603,
46,92
PC4604,PC4613,PC4614,PC4618,PC9202,PC9203,PC9204 to 10u 0805 size

12/7

92

PR9205 change to 13 Kohm for OCP setting

Power

6

Remove SIC,SID level shifter

EE

36

Reserve 1V_S0_PWRGD link for 1V_S0 power rail

EE

Change PD3801: 83.P6SMB.DAG(YS) change to 83.P6SBM.DAG(CHENMKO).

Power

86

Change U8601.U8603,U8604,U8606 pin G to 5v_S0

EE

28

Remove R2822,R2821,C2819 and NC U2803 OTZ pin

EE

36

Dummy C3609

EE

49

Change R4903,R4904 to 0603 size

EE

17

38

A

Power

Add RTC detect pin on REQ1#_GPIO40

EE

61,65

Move C6105,C6106,C6509,C6510 to Connector side

EE

61

Pop TC6102 and DY on IO Board side

EE



A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Change notes

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number
Enrico 14 AMD

Date:

Friday, April 22, 2011

Rev
A00
Sheet
1

105

of

109

5

4

3

2

1

Change notes DATE

VERSON DATE

D

12/7_1

Page

Modify List

OWNER

71

Pop DB1,RN7102,R7107 for debug

EE

74

DY EC7401,EC7403 for reserve

EE

36,46

Add PC4621 and PT4603 1V_PWR and change 1V_S0 to 1V_PWR

EE

14,59

Rename C59011 to C5901 and Change TC4101 to 79.22719.20L

EE

46

Dummy 1V power generator foe back up solution

EE

40

Add PR4063,PC4025 for EMI Snaber solution

17

Reserve damping resistor R1766 for crystal drive level adjustment

D

EMC

EE

C

C

65

Reserve BT_ACT for future module extension

EE

69

Change KB connector

EE

12/8

69

Add Caps led schematic and change AD_IA_HW2 to GPIO50, PCIE_RST# to GPIO36, CAP_LED change to GPIO30

EE

12/10

27

Add R2780 and DY R2732,Q2702 for

EE

12/13

68,82

Change IOBD2 and PWBTN1 pin define

EC "PROCHOT_EC" pin from PP to OD type

EE

B

B

38,40,41

12/14

12/15

Power

PC3806 PC4006 PC4008 PC4110 and PC4114 change to 10uF 25V 0805 size (78.10622.51L)

28

Change U2801,U2803 to B version(74.02800.B71)

EE

97

Add EMI Solution

EMI

40

Change PC4004 and PC4024 from 1uF to 0.1uF (78.10424.2BL)

28

DY R2816,R2817,C2831 for set ADJ floating

EE

61

DY TC6102 for reserve on IO board

EE

82

Change IOBD2 pin define and connector

20

Chnage R2004 to 0402 size

EE

17

Change R1766 location and change to 1KR for Put Rd at chip output side and suppress amplitude.

EE

6,65

Swap RN605,TR6501 for Layout

EE

Title

97

Add EMI Solution

EMI

Size
A3

Document Number
Enrico 14 AMD

EE

Date:

Friday, April 22, 2011

Power

EE, ME


A

12/17

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Change notes

36
5

Change C3615 tolerance from 16V to 25V for component derating high voltage tolerance
4

www.bblianmeng.com
3

2

Rev
A00
Sheet
1

106

of

109

5

4

3

2

1

Change notes DATE

VERSON DATE

12/21

D

Page

Modify List

OWNER

36

Delete R2779 for LID_Close# double pull high

EE

59

Change C5904 to 0.01u from vendor recommand

EE

50

Modify CRT Hsync & Vsync level shift follow DV15

EE

46

Modify 1V_S0 Schematic

EE

12/21_1

42

DY PR4214,PR4402 for pull up on R3624

EE

12/22

61

DY C6104,C6108

EE

12/22_1

56

Change HDD1 CONN to 62.10065.H71

ME

D

C

C

61

12/23

X02

EE

Change to 10u 0805 size

EE

12/23_1

Implement OPI Solution

EE

12/27

Crooect VGA setting, PR9210:150K, PR9211:75K

EE

41

Change PR4104 to 0 ohm,PR4106 to 200K

EE

83

DY R8309,R8310 to solve device error

EE

31

Move C3125 to Q3101.S ,R3134 to 100k to solve unnecessary pulse

EE

Change C3102,C3103 to 18P from vendor recommand

EE

17

Change RN1701 to 22 ohm for solve SIV solution

EE

50

Change RN5001 to 150 ohm for solve SIV solution

EE

Stuff C5002,C5003,C5004

EE

03/03

20

DY TC6101, Stuff TC6103

B

B

97

Add SPR3,SPR4

ME

59

Add RN5901 for nonuse Giga lan

EE


A

50,59,97
03/07

Change CRT ,TPAD1,RJ45 CONN, H10 Hole and add SPR3,SPR4

ME

Change VGA P/N to 71.ROBSO.M01

EE

85

DY R8525,R8526 and Q8501 for nonuse

EE

28

DY R2813,R2805,R2832,C2808,U2805,R2812,R2811, Stuff R2823 for P2800

83~87

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Change notes

5

4

www.bblianmeng.com
3

EE
2

Size
A3

Document Number
Enrico 14 AMD

Date:

Friday, April 22, 2011

Rev
A00
Sheet
1

107

of

109

5

4

3

2

1

Change notes VERSON DATE

Page
28,85

D

03/09

03/10

Modify List

OWNER

DY U2803,R2815,R2812,R2814,C2813,C2814. stuff RN8501,Q8503 for GPU temperature by SMBus

EE

27

DY D2701,D2704 and D2705, Add R2781,R2782 and R2783 for connect directly

EE

97

Change SPR3 to 34.39S07.003

EE

38,39

Rename AFPP3811,3812,3813,3814,3901,3902,3903,3904 to AFTP

EE

38,60

Delete AFTP6001,AFTP6002,AFTP3811

EE

17

Change C1719,C1720 to 18p for vendor recommand

EE

40

Delete PR4063 and PC4025 for EMI Solution

EE

D

C

C

03/10_1

03/11

71

Add R7102 to reserved

EE

27

Change R2724 to 33k for SC PCB version

EE

31

Add RN3101,Q3104 and R3108 to solve Lan leakage issue

EE

Change power gap P/N

EE

Change 0 ohm to short pad

EE

41,42,47

B

B

61,65,82

03/16

Delete TR6101,TR6501,TR8202,TR8201 CMC

EE

41

Change PR4103 from 150Kohm to 143Kohm for 5V OCP setting

Power

44

Change PR4408 from 75Kohm to 66.5Kohm for 1.5V OCP setting

Power

92

Change PR9205 from 13Kohm to 11 Kohm for VGA OCP setting

Power

47

Change PC4709 from 1.5KpF to 100pF for comp

Power

46

Dummy PC4602 and POP PC4604.

Power

03/17

28

DY C2818,D2802,C2816 and Stuff C2815

EE

03/22

40

DY PQ4007,PR4037,PR4012 for new version IC

EE

04/07

49

Add 0 ohm at Q4901.4 for reserved to avoid module leakage

EE

71

Change DB1 foorprint to PAD-10P-177042 for factory

EE

18

Change R1818 to 0 ohm

18

Change R2724 to 47K for X-build version

A

A00

request



A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Change notes

04/11
5

EE

for reserved non-zero power ODD

4

www.bblianmeng.com
3

EE
2

Size
A3

Document Number
Enrico 14 AMD

Date:

Friday, April 22, 2011

Rev
A00
Sheet
1

108

of

109

5

4

3

2

1

Change notes VERSON DATE
4/12

D

4/12_1

4/13

Page

Modify List

OWNER

40

DY PR4029,PR4028,PQ4004 and PQ4006 for nouse because just use 65W adapter

EE

40

Change C8617 to 10u for CRB to avoid voltage drop

EE

20

DY C2005,C2007, and add R2030 for nonuse

EE

97

Change H12,H13 to 34.4HL17.001 for ME asked

ME

97

Delete H13 for ME asked

ME

18

Change EC1801 to 22p for EMI solution

EMC

68

Change R6806,R6812,R6801,R6833 to 330 ohm for brightness

EE

D

C

C

56

DY R5612, Pop Q5602 for modify Zero power ODD

EE

51

Chnage RN5004 to ZZ.0R08P.ZHH to modify layout symbol is short pad

EE

4/17

28

Change R2817 to 0 ohm for setting T8 temperature from 85 to 90 degree to pass reliability test

EE

4/21

56

DY U5601,TC5604,R5606,Q5601,R1818,R5612, Stuff R5604,R5603 for remove Zero power ODD

EE

4/15

B

B



A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Change notes

5

4

www.bblianmeng.com
3

2

Size
A3

Document Number
Enrico 14 AMD

Date:

Friday, April 22, 2011

Rev
A00
Sheet
1

109

of

109



---

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